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DEC-8I-HODA-D

December 1970

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Document:	KB8I General Input Output Interface Option Description
Order Number:	DEC-8I-HODA-D
Revision:
Pages:	9
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-8i-hod/dec-8i-hoda-d.pdf

OCR Text

DEC-BI- HO DA-‘D

KB8/I

GENERAL INPUT/OUTPUT INTERFACE

OPTION DESCRIPTION

DIGITAL

EQUIPMENT

CORPORATION

MAYNARD, MASSACHUSETTS

lst Printing February 1970

The material in this manual is for information purposes and is subject to change without notice.

The Following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

KBB/I
GENERAL INPUT/OUTPUT INTERFACE OPTION

INTRODUCTION

Environmental Specifications

The KB8/I General Input/Output Interface
Option provides an interface between a positive
bus PDP—8/l and any I/O device. All data

Temperature: 32°F to l30°F (0°C to 54°C)
Relative Humidity: 10% to 95%, non—condensmg

transfers, both to and from the PDP-8/I, can be
controlled by the I/O device via the KB8/I.
The KB8/I operates in two basic modes: receive

Data Format

and transmit; they are designated as follows:

The data .format consists of 12 parallel data bits
transferred between the PDP—8/I and an exter-

KB8/I—A
KB8/I-B

nal device.

Receiver

Transmitter

The KB8/l—A and KB8/l—B variations can be
used separately or together in the same PDP—8/I
mainframe.
‘a

This manual discusses each mode as

Voltage levels for the KB8/l are CV for a logical 0V and +3V for a logical lV, providing
direct TTL logic interfacing and the appropriate
diode clamp protection.

separate function.
PROGRAMMING D ESCRI PTION

SPECIFICATIONS
The KB8/I-A consists of one M107 IOT Decoder,
one

M738 Receiver module, and one l5-ft I/O

The KB8/I utilizes device selection codes 36
and 37 for programmed IOT instructions. De—
vice selection code 36 is used by the KB8/I-B

cable (BC08A-l5).

Transmitter for the two IOT instructions.

The KB8/I consists of one M737 Transmitter/IOT

Receiver for the seven IOT instructions.

Decoder and one l5-ft cable (BC08A—l5).
Table l lists the power requirements.

The KB8/I-A Receiver uses the following in-

De-

vice selection code 37 is used by the KB8/l-A

structions:

Table l
Power Requirement Specifications"

Module

Voltage

Current (max.)

Ml07

+5V

245 mA

M737

+5V

300 mA

M738

+5V

370 mA

Skip on Receive Flag 1 (SKA)
Octal Code: 637]
Event Time: I
Indicators:

IOT, FETCH, PAUSE
4.25 us
When Receive Flag 1 is set,

Execution Time:

Operation:
skip the next instruction.
Symbol: Does RFl I? If yes, AC + l-: AC
=

b*Power is supplied by the PDP—8/I mainframe.

Skip on Receive Flag 2 (SK B)
Octal Code: 6372
2

Event Time:

-’

IOT, FETCH, PAUSE

Indicators:

Operation: Strobe data from external de—
vice into counter/buffer and set Receive
Flag 2 (jam transfer).
Symbol: Data CB

Execution Time:

4.25 ps

Operation: When Receive Flag 2 is set,
skip the next instruction.
Symbol: Does RF2 I? If yes, AC7” *AC
=

RF2

Stop Clock and Clear Receive Flag 2 (SCK CFB)
,

Octal Code: 6377

I, 2, 3
Indicators: IOT, FETCH, PAUSE
Event Time:

Clear Accumulator (ACCL)

Execution Time: 4.25 ps
Operation: Stop data modification by re-

Octal Code: 6373
Event Time: I, 2

IOT, FETCH, PAUSE

Indicators:

Execution Time: 4.25 ps
Operation: Each of l2 accumulator bits is

setting clock flip-flop and clear Receive

Flag 2 to binary 0.
Symbol: 0 Clock FF
~>

cleared to binary 0.

Symbol :

O *A CO -l 1

Octal Code: 6374
3

Indicators:

IOT, FETCH, PAUSE

Execution Time: 4.25 ps
Operation: Strobe data onto accumulator
bus and set Receive Flag 1 (iam transfer).
Symbol: Data sAco_n
RFl

Clear Receive Flag 1 (CFA)
Octal Code: 6375
Event Time: T, 3
Indicators:

IOT, FETCH, PAUSE

Octal Code: 6361
Event Time:
Indicators:

IOT, FETCH, PAUSE

gecutipn
peration.Til/“Vet: 4+25

P5
.

ransmit

Fl ag 1

IS set,
next
instruction.
the
skip
Symbol: Does TFl =1? If yes, AC + l» AC

Load Output Bus and Clear Transmit Flag 1

(LBD, CTFA)

Execution Time: 4.25 ps
Operation: Receive Flag 1 is cleared to
binary 0.

Symbol:

structions:

Skip on Transmit Flag 1 (STFA)

Event Time:

RF2

The KB8/I-B Transmitter uses the following in—

Strobe Data and Set Receive Flag 1 (5TB, SFA)

RFl
.

Strobe Data and Set Receive Flag 2 (SDN, SFB)
Octal Code: 6376
Event Time: 2, 3
Indicators: IOT, FETCH, PAUSE
Execution Time: 4.25 ps

Octal Code:

6362

Event Time:

Indicators:

IOT, FETCH, PAUSE

Execution Time: 4.25 ps
Operation: Load accumulator bits 0 through
ll into buffer register and clear Transmit

Flag 1.
Symbol:

ACO—H
0 ->TF]

Use of the KB8/I-A Receiver is illustrated in

The external device can increment the data by

the following programming example:

first enabling the clock in the M738 and then

sending one clock pulse per increment to the
START

counter/buffer.

The modified data is then sent
to the accumulator. Refer to Engineering
Drawing D-BS—K BBI-O-Ol to supplement the fol-

C LA

SDN,SFB
SKB

JMP
CFB

—1

/Strobe data in from
/device and set RF2
/Skip on RF2

lowing discussions.

/Jump back one instruction

IOT Decoder Circuit

/Clear RF2
ffransfer data to the ac—
/cumulator bus and set
/RF1

STB, SFA

RFl

/Skip
/Jump back one instruction

SKA

JMP .-l
CFA

/Clear RFl

/Jump to start

JMP

Each program instruction stored in core memory
is read into the PDP—8/I memory buffer register

(MB) for execution. When the computer recog—
(637X), it gen—
erates a select code based on the
378 configuration of bits MBO3 through MB08. Module
nizes a KB8/I—A IOT instruction

M107 of the KB8/I-A accepts this select code
and produces a SELECT enabling signal (D7,8). *

Use of the KBB/I-B Transmitter is illustrated in

The computer also enables its IOP generator to

the following programming example:

produce IOP pulses as determined by bits MBO9
through MBll These IOP pulses, together
with bits MBO9 through MBll (C7), are ANDed
into the decoder network (C7) with the SELECT
enabling signal to produce the seven IOT pulses
required by the KB8/I—A.
.

BEGIN

CLA
TAD

LDB, CTFA /Transfer data to the

STFA
JMP .-l
JMP

/external device and
/clear TFl

The outputs of the decoder are designated by

/Skip
/Jump back one instruction
/Jump to begin

ber before the hyphen indicates the octal value
This number corof bits MB09 through MBl l
to
the
least
responds
significant digit of the

‘

TFl

OPERATION

KBB/I—A Receiver (see Figure l)
The KBS/I—A Receiver receives 12 bits of data

two numbers separated

by a hyphen.

The num—

octal codes for the seven KBB/I—A instructions.
The number after the hyphen indicates the IOP
pulse (1, 2, or 4) at which the IOT occurs.
These numerical designations are used elsewhere
on the logic diagram to indicate inputs to other
circuits. An example is the designation IOT

1-1, which indicates a true signal resulting

in parallel from the external device and loads

them, upon application of the load pulse, into
the counter/buffer. The data presented to the
bus driver from the counter/buffer is sent (when
strobe pulse is used) to the PDP-8/I accumulator
as

12 parallel data bits.

*The alphanumeric designation refers to the co—
ordinate locations of signals and circuits on

DEC Drawing D—BS-—K B8I-O-OT.

STROBE

LOAD

12 PARALLEL

PARALLEL
DATA BITS

BUS
DRIVER

COUNTER/
BUFFER

FROM EXTERNAL
DEVICE

DATA BITS
TO
ACCUM ULATOR

DATA
MODIFIER

81-0166

Figure I

KB8/I-A Receiver

from the decoding of a 637l SKIP ON RECEIVE
FLAG l instruction and IOPI
For more infor-

Receiver Circuit

mation on IOT and device selection, refer to

Initially, the I/O device generates signal CLR
CNTR/BUFF, which clears all flip—flops in the
counter/buffer (B3). To be true, this signal

the input/output section of the DEC Small Com—

puter Handbook.

must be at CV for a minimum of 3 ps.

IOT 6-4

(B3)
iam-transfers the data
from the device into the counter/buffer. At
is then issued and

Clear Accumulator
The accumulator (AC) must be cleared to all
zeros before data transfer.
Otherwise, the re—
sulting word in the AC will be the inclusive OR
of the previous word in the AC and the current
word being transferred. To accomplish the
clearing, the KBS/l-A provides signal I/O BUS
IN AC CLR (D1) to the computer l/O bus. This
signal is generated whenever IOT 3—2 is issued

(D3)

this point, if the data is to be incremented, the
external device initiates 0 0V start clock pulse

(B7) which clears the clock flip—flop (B5).
The O-side output (high) of the clock flip-flop
is gated with a device—generated,

positive-

going clock pulse (B7) to provide a shift pulse
(one shift pulse per clock pulse). The shift
pulse is gated into the counter/buffer for the
amount of incrementation desired. If overflow

REC'V FLAG I.

from the counter/buffer occurs, +3V signal
OVERFLOW (B3) is sent back to notify the ex-

same manner as

When the data has been sufficiently incremented, an IOT 7—4 instruction is

generated signal designated SET FLAG 2 (C3).

issued (A6), which sets the clock flip-flop,
thereby inhibiting further shift pulses.

(D3) as REC'V FLAG I and generates the interrupt signal I/O BUS IN INT. The set output is
also applied to one input of a two-input NAND
gate (C2). When the 0V IOT 2-2 is issued, it
is amplified to 3V (C3) and applied to the other

ternal device.

With the data modification complete, IOT 4-4
(C2) is issued, initiating a strobe pulse to the
bus driver (B2), which, in turn, transfers the
contents of the counter/buffer to the PDP-8/I
accumulator. If incrementing of the data is not
desired, IOT 4-4 is issued immediately and the
data is transferred directly into the accumulator.

However,

REC'V FLAG 2 flip—flop is set by a device-

The set output is applied to the same NOR gate

input of the NAND gate. With both inputs
high, the NAND gate is enabled, producing
the signal I/O BUS IN SKIP.

INITIALIZE
When the system is first turned on, the PDP—B/I

Interrupt Request and Skip Circuits

generates a 3V INITIALIZE signal, which is inA program interrupt request can be generated by

verted and gated to the reset inputs of REC'V

the set side of either REC'V FLAG I

FLAG I, REC'V FLAG 2 and clock flip—flops.

(C4)

REC'V FLAG 2 (C3) flip-flop. The command
to skip the next instruction can be generated by
the combination of the set side output of either
the REC'V FLAG l or REC'V FLAG 2 flip-flop
and a programmed IOT instruction.

KB8/IB Transmitter (see Figure 2)
In the KBB/I—B Transmitter portion, 12 parallel

data bits are received from the PDP-8/I accu—
IOT 4—4 is issued when data from the external

device is ready to be strobed into the computer.
In addition, IOT 4-4 sets the REC'V FLAG I

flip-flop. The set output of this flip-flop is
applied to both a NOR gate (D3) and to one
input of a two-input NAND gate (D3). The CV
output of the NOR gate is designated I/O BUS
IN INT and initiates a program interrupt request
to the PDP-B/I. When the 0V IOT I-I is issued,
it is amplified (D4) to 3V and applied to the other
input of the NAND gate. This input, together
with the set output of REC'V FLAG I, qualifies
the NAND gate and generates the output signal
I/O BUS IN SKIP (DI), which, in turn, instructs

the computer to skip the next instruction. (IOT
I—I effectively samples the state of REC'V FLAG
I

output.)

The REC'V FLAG 2 flip—flop initiates an inter—

rupt request and a skip command in much the

mulator and, upon application of the select
level enable pulse, are loaded into the buffer
register. When input/output pulse 2 (IOP2) is
received, data stored in the buffer register is
strobed into the output buffer and presented to
the external device as I2 parallel data bits.
Refer to Engineering Drawing D-BS-K B8I-0-O2
for the following discussion.

Transmitter Logic Operation

The external device generates a set signal (C5)
which sets the XMIT FLAG I flip—flop (C5),
indicating that the device is ready to accept
data from the PDP-8/I.

If a program interrupt

request to the computer is required, the set out—
put of the XMIT FLAG I flip—flop and the de—

vice—generated signal PI ENABLE (C4) are
AN Ded together (C3). The output of the AND

SELECT LEVEL
ENABLE

12 PARALLEL
DATA BITS
FROM

BUFFER
REGISTER

OUTPUT
BUFFER

ACCUMULATOR

12 PARALLEL
DATA BITS
TO EXTERNAL
DEVICE

81-0165

K38/I—B Transmitter

Figure 2

gate is inverted to 0V to produce the signal

I/O BUS IN INT (C2).
is at 0V for the

The FLAG 1 signal

When IOPZ is decoded, the resulting signal is

(C4)

length of time that the flag is

gated (C6) with the select level, both to reset

For data to be transmitted via the K38/l-B, the

the XMIT FLAG l flip—flop and to transfer the
data stored in the buffer register to the output
buffer (34). The data is then immediately ap—
plied to the external device. Provision is also
made for the select level to be generated by an

computer supplies a device select code of 368

externally supplied signal instead of a program-

set, and allows the external device to monitor
the status of XMIT FLAG l flip—flop.

by means of memory buffer bits M303 through
M308. The KBB/I-B decodes bits M303 through
M308 (D6) and, when it recognizes the 368 configuration, generates a multipurpose select level
signal (output of OR gate, D5). This select
level enables the bus gate (36), allowing the
l2 data bits in the accumulator to be loaded
into the buffer register (35).

med IOT instruction.

The device initiates the

signal EXT ENABLE, which is inverted to 3V
(C6) and applied to the OR gate (D5) that pro—
duces the select level.

INTERFACE

A command to skip

the next instruction can be generated by the

ANDing (D3) of the select level, lOPl, and
the set output of XMIT FLAG l flip—flop. The
output of the AND gate is inverted to 0V (D2)
to produce the signal I/O BUS IN SKP.

The three module cards which comprise the
K38/l option are mounted within the PDP—8/I
mainframe. These cards are connected to the

external device by two 3C08A-15 cables, one
for receive and one for transmit. Each cable is

15 ft long.

On either end of each cable is an

M903 connector module which terminates the

cable. Engineering Drawing D-UA-BCO8A-0-O
details the BCO8A-15 cable and its associated
M903 modules.

MAINTENANCE
Maintenance procedures for the KBB/I Option
are

defined in diagnostic program MAINDEC—

81—DBGA.

DRAWINGS
D BS—K 38/1—0-01

Receiver

D BS-K B8/I —o-02

Transmitter

D BS—K B8/I -o-03

Acceptance Procedure
Engineering Specification
Cabhng

D BS-K 38/1-0—04

D —UA-BC08A—0-O