Digital PDFs

DEC-8I-HOCA-D

December 1969

27 pages

Original

0.9MB

Document:	KE8I Extended Arithmetic Element 19
Order Number:	DEC-8I-HOCA-D
Revision:
Pages:	27
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-8i-hoc/dec-8i-hoca-d.pdf

OCR Text

DEC-8/1-HOCA-D

KE8/I

EXTENDED ARITHMETIC
ELEMENT

DIGITAL

EQUIPMENT

CORPORATION

•

MAYNARD, MASSACHUSETTS

The material

in this manual is for

Informa-

tion purposes and is subject to change with-

out notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

EAE instructions have binary zeros in MB bits
04, 05, 06 and 07 and a binary one in one
or more of MB bits 08, 09, and 10. The EAE
microinstructions are augmented instructions
and they are microprogrammable. Therefore,
they can be combined to perform non-conflicting logical operations.

EXTENDED ARITHMETIC ELEMENT

LOGIC DESCRIPTION

INTRODUCTION

The KE8/1 EAE logic circuits are used asyn-

The KE8/I Extended Arithmetic Element (EAE)
option for the PDP-8/l enables the central

chronously to, but in conjunction with, the
accumulator (AC), link (L), and memory
buffer (MB) performing parallel arithmetic

processor to perform arithmetic operations at
higher speeds . These higher speeds are made

operations on positive binary numbers. Figure

possible by incorporating the EAE components

a simplified block diagram of the KE8/I

EAE option

with the existing central processor logic in
such a way that they operate asynchronously.

The EAE components consist of: a 12-bit
Multiplier Quotient (MQ) register, a 5-bit
Step Counter (SC), a 3-bit Instruction Register (EAE IR), and the EAE timing and control
logic

General Logic and Instructions

The transfer of information between most of
the KE8/I EAE registers and the PDP-8/I
central processor (CP) occurs during the EAE
instruction Fetch cycle.

The EAE logic is contained in twenty-five
modules located in the central processor mainframe, module locations C13 through C24
and SC regisand D12 through D24. The
ters are displayed on the PDP-8/l front panel

The instructions for the EAE are a class of

Group 3 Microinstructions containing binary
ones in MB bits 00 through 03 and 11 . These
bits, always being set, distinguish the EAE
instruction from all other instructions. These
instructions can be subdivided further into

two basic groups: the register load group
(single-cycle instructions not requiring EAE

EAE operation group (two cycle
EAE timing is started and
when
instructions

timing) and

the central processor is set to the Pause state)
All register load instructions have a binary

one in MB bits 04, 05, 06, or 07 and binary
zeros in bits 08, 09, and 10 except SCL
which has a binary one in MB]0' All other

All arithmetic opera-

tions, with the exception of NMI (normalize),
require an Execute cycle for referencing the

next memory location, thereby, obtaining
one of the operands for a multiply (MUY),
divide (DVI), or the number of shifts to be
performed during the long-shift feature. The

PAUSE flip-flop, in the CP, is set by the
EAE microinstructions when microprogrammed
for arithmetic operations because the comple-

tion of an arithmetic operation requires at
least 7.8 ps.

Setting the PAUSE flip-flop

prevents the CP from advancing in its cycle
until the arithmetic operation is completed.

At the finish of the arithmetic operation the
EAE logic sets the EAE END flip-flop which
direct sets the TS4 flip-flop, clearing the

PAUSE flip-flop, and allowing the CP to
continue the program.

EAE Instruction Register (EAE IR)

Step Counter (SC) Register

The EAE IR Is a 3-bIt register consisting of

The SC Is a 5-bit register loaded with the
complement of the contents of MB bits 07
through n for the ASR, LSR, SCL, and SHL
Instructions and Is set to contain ail zeros
for the DVI, MUY, and NMI instructions.
It is used to record the number of shifts performed and stops the shifting process after
the correct number of shifts.

flip-flops that are set to the contents of MB
bits 08,

09, and 10 during the Fetch cycle

MB bits 08, 09, and
10 determine if the EAE instruction is an SCL,

of an EAE Instruction

MUY, DVI, NMI, SHL, ASR, or LSR instruction.

All EAE instructions cause MB bits 08-10 to

be loaded into the EAE IR at TP3 of the Fetch
cycle (D-BS-KE8I-0-2 B-1,2,3). The input

Single-Cycle Instructions

to the EAE IRO flip-flop data input Is MBqs/

EAE IRl flip-flop data Input is MBq^ , and
EAE IR2 flip-flop data Input Is MB^q. The
clock inputs are pulsed by the output of a
negative NOR gate whose Input is from a twoinput NAND gate
The two inputs of the
gate are EAE INST and TP3
EAE
INST is high during TP3 of the Fetch cycle of
,

NAND

an EAE Instruction (D-BS-KE8I-0-2 C-4). A
four-input NAND gate has B FETCH (l),OPR

The single -cycle Instructions are CAM, CLA,
MQA, MQL, and SCA and require a Fetch
cycle only. These will be discussed first so
that the logic used by these and other instructions can be developed slowly and used as
steps for the more difficult instructions. Logical sequence one is during or before TS3, logical sequence two Is at TP3, and logical sequence three Is after TP3

(EAE instructions are a class of OPR instruction),

MBo3(l), and MBii(l) as input and

EAE INST as Its output. The last two Inputs
are true only for the EAE instructions.

Multiplier Quotient (MQ) Register

Clear the Accumulator (CLA)

The CLA instruction (76018) clears the AC
during logical sequence 1, therefore, this
instruction can be microprogrammed with
other EAE instructions that load the AC during

The

that acts as an extension of the AC during

logical sequence 2 such as SCA or MQA.
Since the EAE instructions are a class of group

a 12-bit bidirectional shift register

EAE operations. The MQ contains the multi-

3 instructions OPR Is always present during the

plier at the beginning of a multiplication

Fetch cycle of an EAE instruction and 0P2 Is

and the least significant half of the product
at the conclusion. The MQ contains the

present during TS3 of the Fetch cycle.

least significant half of the dividend at the

ENABLE is inhibited by MB04 being set
(D-BS-8I-0-4 C-2)
AC ENABLE Is high

start of a division and the quotient at the end.

and present only when the four-Input AND

The
contains the least significant part of
a number during a shift or a normalize operation.

gate has all four nputs high, that is, OP2,
ACENABLE, and MB
(0). AC
ENABLE is Inhibited by MBqJ (0) and MBo7(l)
i

-MQ

MQ
00

ACCUMULATOR

MULTIPLIER QUOTIENT

MQ
n

STEP COUNTER

MEM

SCL

SC CONTROL

MQ SHIFT

a GATING

GATING

CP REGISTER
SHIFT a TRANSFER

CP
TIMING

CONTROL

Figure 1

Simplified Block Diagram, KE8/I

EAE

CONTROL

TIMING

(D-BS-KE8I-0-2 C-6). The NAND gate must
have all input signals high to produce AC *

MQ ENABLE from the negative NOR gate

and OP2 are high but MBo4(0)
and MBq7(1) are low (being Ts) therefore,

MB^

drives .

(1)

AC * MQ ENABLE is not present. AC LOAD
is generated by four-input AND gate (D-BS81-0-6, D-7) with TP3, B FETCH (1), and OPR
as inputs. This AND gate output is inverted
by a NOR gate and used to load the AC

AC then load the MQ into the AC If the
AC is not cleared prior to this command the
.

contents of the
are inclusively ORed
with the contents of the AC. During this
instruction MB bits 08 through 10 are loaded
into the EAE IR.

MQ ENABLE

developed by a three-input

NAND gate (D-BS-KE8I-0-2 D-3) with
MB05 0)/ OP2, and MBii(l) as inputs. The
output of this

NAND

gate is connected to a
negative NOR gate whose output,
EN-

Clear Accumulator and Multiplier Quotient

(CAM)

ABLE, is developed by a four-input AND
gate (D-BS-8I-04 C -2) with inputs o f OP2,

AC •> MQ ENABLE, and MBo4(0)
The CAM instruction (762 Ig) clears the AC
during logical sequence

1 ,

as in CLA, and

AC - MQ
ENABLE is high because (D-BS-KE8I-0-2 C-6)
MB07 is a 0. The output of this AND gate is
.

cleared by MB bit 07 (1) and EAE INST.

connected to a NOR gate whose output (low)
goes to a negative NOR giving AC ENABLE.

AC ENABLE is inhibited by MB04 (D (D-BS81-0-4, C-2), AC -MQ ENABLE is also in-

AC LOAD is developed by a four-input AND
gate (D-BS-8I-0-6 D-7) with inputs of TP3,

during logical sequence 2 (at TP3) the
is

hibited by MBq4 (1) (D-BS-KE8I-0-2, C-7).

MQ LOAD

present (D-BS-KE8I-&-2, D-2)

because MBqj (1) and EAE INST are both high
during TP3, therefore,
LOAD is present
during logical sequence 2. AC LOAD is present during TP3 also (D-BS-8I-0-6, D-6 and 7)
the output of a four-input AND gate with inputs of TP3, B FETCH(I), and OPR drives a
NOR gate. The output of this NOR gate is
connected to a negative NOR gate whose out-

put Is AC LOAD.

B FETCH (1), and OPR.

whose output signal is AC LOAD AC LOAD
is developed for all EAE instructions in this
manner at TP3 of the Fetch cycle.
.

MQ V AC = >AC
Load Multiplier Quotient (MQL)

= >AC,0 = >MQ.

The MQL instruction (742] q) clears the MQ,
logical sequence

1 ,

loads the

the AC into the MQ,
Multiplier Quotient Load into Accumulator

(MQA)

then the AC is cleared

MQ into the AC. This command

given to load the 12 least significant bits of
the product into the AC after a multiplication
or to load the quotient into the AC after a

contents of

logical sequence 2,
.

AC - MQ ENABLE

developed by a four-input NAND
gate (D-BS-KE8I-0-2 C-6) with inputs of
MBn (1) , MBq7(]) / M^04(0) / q"d OP2 This
output is AC -*
ENABLE and is connected
to a negative NOR gate whose output is AC (high)

The MQA instruction (75018) '°*'^ the contents
of the

The output of this

AND gate drives the input of a NOR gate
whose output
connected to a negative NOR

MQ ENABLE. AC - MQ ENABLE causes the
AC bits to go directly to the data inputs of

issuing this command or the CLA instruction

MQ flip-flops (D-BS-KE8I-0-3 C-8)
AC MQ ENABLE appears on one side of the

can be combined with the MQA to clear the

two-input AND gates with an AC bit on the

division .

The AC should be cleared prior to

the

——

TP3 _J |_
EAE START

EAE RUN (1)

EAE ON (1)

EAE ON

250 ns PULSE

n _n _rL_ in_ |-|_„ |-L^ n

EAE TP

U
n
u

EAE TP
350 ns PULSES

EAE TG (1)
SC LOAD

_._rL..

SC=0

SC=1

EAE END(I)

CP PAUSE (0)

u
rL n

u
n

•vV

U
n

~i_r~n_r~

n
"~|J

__rL___rL__rL_
SC=2

SC = 3

SC = 4

SC=5

SC=6

sc=x

n ^^ n _n

^^^

cc u
Ujsr
"»•»

u
n
u

=X)6*-SC = 13

——

Figure 2

Timing Diagram, KE8/I EAE

other side.

MQ LOAD

developed during

logical sequence 2 here the

CAM

same as

the
instruction
Zero's are loaded into
the AC by inhibiti ng AC ENABLE (D -BS-8I.

0-4 C-2) because AC -* MQ ENABLE is low
at this time.

= >MQ, AC = >MQ,

= >AC

Step Counter Load into Accumulator (SCA)

qualifies, a negative

NOR gate qualifies

giving EAE BEGI N.

EAE BEGIN combines
with SCL giving EAE SET. EAE BEGIN also
combines w ith SCL and TP3 giving EAE START.
EAE START is inverted and applied to the
clock input of the EAE ON flip -flop and since
the data input is high (because EAE COMPLETE
is high) th e EAE ON flip-flop is set.
At the
same time EAE START is applied to the set input of the EAE RUN flip-flop this transition
from high to low sets the EAE RUN flip-flop.
During this time the pulse applied to the

The SCA instruction (74418) loads the contents
of the SC into the AC. The AC should be

clock input of the EAE
flip-flop is also
applied to a tapped time delay network.

cleared prior to this instruction or the C LA

Approximately 250 ns later this pulse comes
from the time-delay to an amplifier having
approximately a 100 ns delay. This pulse
(EAE TP) is applied to one side of a NAND
gate (D-BS-KE8I-0-2 6-5). The other side
of the NAND gate is high at this time because of EAE RUN (1)
The EAE TP pulse
is inverted through a negative NOR gate
and applied to the clock input of the EAE
flip-flop and to the input of the tapped
time-delay line. Therefore, approximately
each 350 ns this pulse will circulate through
this timing chain and EAE timing will continue.

instruction may be combined with the SCA to

clear the AC during logical sequence 1

The transfer of the SC to the AC happens during
logical sequence 2 so both instructions may
be combined. SC ENABLE is developed (D-BSKE8I-0-2 D-2) by a three-input NAND gate
with inputs of MB^^Cl), OP2, and MBo6(1).
The output of this NAND gate goes into a
negative NOR gate whose output is SC ENABLE AC LOAD is developed in this instruc,

tion exactly as in the

MQA instruction.

SC VAC = >AC.

Once EAE timing is started it is a continuous
cycle until stopped.

EAE Timing

The tapped delay line also has a 350 ns out-

All two cycle instructions start EAE timing

This output appears at nearly the same
time as the EAE TP and is applied to an ampli-

therefore, EAE timing is covered here with

fier where it

put

the understanding that all of these instructions
accomplish the starting of EAE timing in a
similar manner. During this discussion of EAE
timing see drawing D-BS-KE8I-0-2, Figure 1
Block Diagram, KE8/I EAE, and Figure 2
Timing Diagram, KE8/I EAE.

delayed approximately 100 ns
and then applied to the clock input of the
EAE RUN flip-flop. The data input of the
EAE RUN flip-flop is connected to the EAE
is

ON flip-flop (1) output therefore, as long
ON flip-flop set the EAE RUN

as the EAE

mately every 450 ns.
During an NMI instruction or any one of the

two-cycle instructions one of two NAND
gates (D-BS-KE8I-0-2 A-5) is qualified either

by NMI (the normalize instruction) and NORM
(the normalize condition) or OPR and B EXE-

CUTE (1). When either of these NANDgates

flip-flop will be clocked and set approxiTliis

ensures that the

EAE RUN flip-flop stays set during the circulation of EAE TP throughout the EAE timing
chain and that EAE RUN is turned off after
EAE TP.

When the EAE TP pulse comes out of the
NAND gate we have an EAE TP that is applied,

EAE TP is applied to the amplifier it
generates the last EAE TP pulse. This last

through a negative NOR gate, to the clock

pulse is applied to the input of the NAND
gate, to clock EAE
flip-flop, but at

input of the EAE TG (time generator) flip-flop.

The EAE TG flip-flop data input is low as
long as DVI LAST and EAE RUN (1) are present at the NAND gate connected to it. So
EAE TP resets this flip-flop, but approximately 100 ns later the 350 ns pulse appears from
the tapped time-delay network and is inverted
and applied to the set input of the EAE TG
flip-flop thereby, setting this flip-flop.

EAE

TG (1) provides a pulse (pulse width 100 ns)
supplying an MQ LOAD and SC LOAD. This

this

this time the other input of the gate is low,
since the EAE RUN flip-flop (1) side is

having been reset, therefore, the EAE TP
pulse dies.

One more pulse appears from

the delay network 350 ns output pulsing
the clock input of the EAE RUN flip-flop

and the direct set input of the EAE TG
flip-flop. The EAE TG flip-flop is set; the
EAE RUN flip-flop data input is low and
does not set

happens approximately each 450 ns during

EAE timing

EAE Timing Termination
EAE timing EAE COMPLETE (D-BS-KE8I-0-2 C-6) must go low.
When EAE COMPLETE goes low it is inverted
and applied to a NAND gate (D-BS-KE8I-0-2
In orde r to terminate

C-5). The other input of this NAND gate is
connected to the EAE RUN flip-flop (1) output.

NAND gate's output, now low, is connected to the d ata input of the EAE
flipflop. The next EAE TP pulses the clock input
of this f lip-flop causing it to reset. This same
EAE TP goes on to the time-delay line where it

The fi rst EAE TP pulse, after EAE COMPLETE goes low, pulses the clock input of
the EAE END flip-flop. At this time the
EAE END da ta input, connected to EAE
COMPLETE, is low, therefore, this EAE
TP clocks the EAE END flip-flop resetting
it. When EAE END (1) goes low its output
pulse is applied to a negative NOR gate
(D-BS-8I-0-2 D-4) and then to a NAND
gate and applied to the TS 4 flip-flop direct
set input and CP timing is restarted.

This

appears again,

350 ns, as another EAE TP.

EAE COMPLETE goes low, to end EAE
timing, under an y of several conditions.

EAE COMPLETE is the output of a NOR
gate (D-BS-KE8I-0-2 C-6)

There are four

inputs which can cause it to qualify.

This EAE TP again pulses the clock input of the

the left hand side the input is tied to an

EAE ON flip-flop assuring that it is reset as the

AND gate whose inputs are MUY, SCl(l),
SC3(1), and SC4(1). During an MUY instruction MUY is high. As soon as SCI
SC3,

data Input is still low.

At this time at the 350 ns

time-delay line output, there appears another
pulse delayed approximately 100 ns by the

and SC4all become ones, signifying the next

amplifier and then it pulses the EAE RUN flip-

to the last operation of this instruction, this

At this time the EAE RUN
flip-flop data input, which is connected to

AND gate qualifies giving EAE COMPLETE

flop clock input.

EAE ON flip-flop (1), is low, therefore, the
EAE RUN flip-flop Is reset. This same pulse
is

inverted and applied to the set input of the

EAE TG flip-flop once more setting this flipflop. At this time, there is one more EAE TP
circulating In the time-delay line.

When

low and thus EAE timing is terminated.

The second input from the left is connected
to a two-input AND gate. One of these
inputs is high when performing a

DVI instruction; the other input is DIV LAST. DIV LAST
is given by a negative NOR gate when either
input goes low. The left input comes from a

NAND gate whose inputs are SCO -3 = 0,

ACo3(0), MQ & LOW AC=0, and
=
MID AC 0. The last two signals are develop-

condition:

ADDER L, and SC4(0); these inputs, when
high, qualify this

NAND gate giving EAE

COMPLETE and terminating EAE timing.

other words if the AC is equal to or larger

than the MB this gate stops EAE timing.

The

right hand input is SCl(l), SC4(1),
this condition

and SC2(1);
met when only one operation

remains to be performed by the DVI instruction.

EAE timing is halted and the one remaining
EAE

shift is performed thus completing the

DVI instruction.

The third input from the left of the NOR
The fourth
input from the left is connected to an AND
gate with inputs of SC FULL and SCOO)
This condition is met during an ASR, LSR,
or SHL instruction when only one shift remains to be performed. When one of these
gate remains low at all times.

is being performed, the SC is
loaded with the complement of the number

ed (D-BS-KE8I-0-2 B-8) by NAND gates that
sample the contents of different
bits and

(D-BS-8I-0-6 B and C-4) NAND gates that
sample AC bits 4 through 1 1
When AC bits
08 through 11 are all O's (D-BS-8I-0-6 C-4)
a NAND gate qualifies giving a low out
which is inverted by a negative NOR gate
giving LOW AC =0. Immediately above
these gates is another pair. One of these,
a NAND gate, samples AC bits 04 through
07 and when all are zero this gate has a low
output qualifying a negative NOR gate whose
output signal is MID AC = 0. When MQqq
.

through Q3 (D-BS-KE8I-0-2 B-8) are all Os

a NAND gate qualifies a negative NOR gate
whose output is connected to one input of a
four-input NAND gate. The second Input

NAND gate receives a signal from
a negative NOR gate when MQ04 through
of this

The third input, of the four-

instructions

07 are all Os.

of shifts to be performed

NAND gate, receives a signal from
a negative NOR gate when MQqq through

SC FULL is gener-

ated (see D-BS-KE8I-0-3 B-7) by SCI, SC2,

SC3, and SC4 all being set to ones. These
inputs qualify a

NAND gate that, in turn,
NOR gate giving SC

qualifies a negative

FULL.

This signal qualifies one input to

AND gate on the fourth input. When
SCO(l) goes high both inp uts of this AND

the

gate are qualified giving EAE COMPLETE
terminating EAE timing.

input

The fourth input is high when
=0.
LOW AC
When these four conditions
are met simultaneously and the activated
NAND gate turns on the negative NOR
gate above it, the signal MQ & LOW AC =
This signal is connected to
is present.
1 ]

are all Os.

the middle input of the three-input

NAND

The fifth input from the left or the extreme
right hand input of the NOR gate causes

(D-BS-KE8I-0-2 A-5 and 6) combining with
ACo3(0) and MID AC=0, developed above,
thus terminating EAE timing. A number is
loaded into the AC and the MQ and is shifted left until ACqq /^ ACqi
Since ACqq

termination of EAE timing during the NMI

instruction.

This input receives its levels

from a three-input AND gate.
is

tied high, the middle input is

One input
high at all

times during the NMI instruction, and the
third input is connected to a negative

gate.

This

NOR

NOR gate has three inputs each

being driven by a

NAND gate, therefore,

any time one of the following three conditions is met EAE timing is terminated. First
condition: ACq] (0) and ACq2(1)
Second
.

the sign bit, ACqi

the first data bit.

Therefore, shifting occurs until the most
significant bit reaches ACq]

The control
of EAE timing thus depends on ACqi and
AC02 becaus e there is one mo re shift performed after EAE COMPLETE is generated.
The middle NAND gate terminates EAE
timing if all bits to the right of ACqo are
•

zeros. Third condition: When ACq 1 0)
and ACq2 (0) EAE timing is terminated by
the lost EAE TP

Special Case InstrucHons

There are two EAE instructions that do not fit
into either the single-cycle or two-cycle

These are the Normalize
Load from Memory
Counter
(NMI) and Step
(SCL). These, with their differences, are
discussed below.
instruction group.

NORM and NMI combine in a two-input
NAND gate (D-BS-KE8I-0-2 A-5) whose
output
connected to a negative NOR gate.
The output of this NOR gate is the sign al EA E
is

BEGIN and at TP3, of the Fetch cycle, EAE
START is generated and EAE timing is started.
This is the only condition where EAE timing is
started without an Execute cycle.

The normal-

ize test tree (D-BS-KE8I-0-2 B, C, and D-8)

keeps constantly testing the AC and

Normalize (NMI)

the normalized condition.

MQ for

When this condi-

tion is reached EAE timing is terminated as

The NMI instruction (7411g) is used, in part,
to convert a binary number to a fraction (and
its exponent) for

metic .

use in floating-point arith-

The AC and

MQ are acted on as one

long register and their contents are shifted left,

by this command, until the content of ACqO
is

not equal to ACqi .

into bit 11 of the

A "zero" is shifted

MQ each shift. When this

instruction is completed, the SC contains a

number equal to the number of shifts performed

Tlie contents of the L are lost.

During

was discussed under EAE Timing Termination.

NMI the following signals
are generated: AC ENAB LE, AC LOAD, A C
LEFT SHIFT, MQ LOAD, MQ LEFT SHIFT,
SC LOAD, an d increment SC. AC ENABLE
is produced by EAE AC ENABLE (D-BS-KE8IFor each shift during

A two-input NAND gate with inputs of B EA E ON, always pre sent with EAE
timing and EAE AC ENABLE. EAE AC EN0-2 D-5).
,

ABLE comes from the three-input NAND gate

NAND gate's output is always

the NMI instruction EAE timing is started but,

to the left.

the CP stays in the Fetch cycle and the PAUSE

high except during an EAE DVI instruction.

flip-flop is set.

This is the only EAE instruc-

tion that starts EAE timing, but does not re-

quire an Execute cycle.

During logical se-

quence 1 MB bits 08, 09, and 10 are loaded
into the EAE IRas in all EAE instructions. At
this time the SC is cleared.

A normalize test

(D-BS-KE8I-0-2 B, C, and D-8) checks
the number contained in the AC and MQ to
tree

determine if it is already in the normalized
condition. There are three NAND gates
(D-BS-KE8I-0-2 C-8) with outputs connected

NOR gate.

This i nput,

This

EAE AT EN ABLE and B EAE ON

gives EAE AC EN ABLE during EAE timing.

EAE AC ENABLE is one of the inputs to a
four-input negative

NOR gate (D-BS-8I-0-4

D-1) gi ving AC ENABLE. AC LOAD is generDuring
ated by EAE TP (D-BS-8I -0-6 D-7)
EAE timing each EAE TP pulse into the nega .

NOR gate gives AC LOAD. EAE LEFT
SHIFT ENABLE is generated by a four-input
NAND gate (D-BS-KE 8I-0-2 D-7) The inputs of th is gate are: EAE RIGH T SHIFT
ENABLE, B EAE ON, DIV LAST, and the

tive

The
NAND gate on the left-hand side checks

output of another three-inp ut

AC00(0) and ACqi (1) and the right-hand
NAND gate checks ACoi(0) and ACqo(1).

EAE RIGHT SHIFT ENABLE is high when
either EAE IRl (1) orWTis low. EAE IRl(l)

to a three-input negative

ACqo cbes not equal ACqi neither of

NAND gates will turn on. The center
NAND gate has inputs of MQ & LOW AC =

these

0, MID AC=0, ACo3(0), and ACo2(0),if none

NAND

gate does
of these conditions exist this
not qualify. The output of the three-input
negative NOR gate is low and

i s

a NAND gate giving the signal

Inverte d by

NORM.

NAND gate.

low during the NMI instruction, therefore,
the output of this NAND gate is high during
is

this

EAE instruction

B EAE

present during EAE timing .

ON is always
DIV LAST is high

at all times except the last division process

of the EAE DVI instruction.
is

The other input

connected to the output of a three-input

NAND gate. The three inputs to this NAND

the SC4 flip-flop.

gate are:

inputs are connected to a three-input

SC1(1), DVI, and 502(1).

The
output of this NAND gate will be high except
under these conditions during the EAE DVI
instruc tion, therefore,

gate.

of these inputs during EAE timing .

The other

Input(s) samples either one side or the other

negative NOR gate (D-BS-8I-0-5 D-4)
which gives AC LEFT SHIFT. MQ LOAD is
developed as the output of a four-input nega-

of the associated flip-flop and the "one" side
of each flip-flop following it, that is, SCO
samples SCI , SC2, SC3, and SC4; SCI

NOR gate (D-BS-KE8I-0-2 D-2) one

input is EAE TG(1).

NAND

One input of each NAND gate Is

bussed to EAE ON(l) giving a high to each

tAE LEFT SHIFT EN-

ABLE is one of the Inputs to a four-input

tive

The left-hand and center

samples SC2, SC3, and SC4; SC2 samples

As was shown in the

SC3, SC4, and etc. The set (one) and reset

discussion of EAE tinning EAE TG (1) goes low

outputs of the flip-flops are sampled directly

for approximately 100 ns at each

EAE TP pulse,

by one NAND gate and the reset and set

therefore, duri ng this time pulse

MQ LOAD

outputs are sampled by the other

NAND

gate.
Thus, for each SC LOAD generated the SC

generated. LEFT SHIR is generated by a
two-input NAND ga te (D-BS-KE8I-0-3 B-8)
The two inputs are: EAE RIGHT SHIR ENIs

will count one binary number higher, record-

ing the number of shifts performed.

ABLE, developed earlier, and B EAE ON,
also developed earlier, giving LEFT SHIR

AC.=AC. -1,ACqq=L,

which Is inverted by a negative NOR gate
and goes to one side of a bus connecting six

MQqq=AC^^, MQ. =MQ.-1,

two-input NAND gates. The other inputs
of these NAND gates are MQqi through

= MQ^^ until ACqqt^ACq^.

MQq^. There are six other two-Input
gates bussed together and connected to the

NAND
Step Counter Load From Memory (SCL)

output of a negative NOR g ate (D-BS-K E8I-

0-3 C-1 , 2, 3, and 4) with LEFT SHIFT as

The SCL instruction (7403g) requires two

The other inputs of these NAND
gates are MQq^ through MQ, , and the output of a four-input NOR gate . The righthand Input Is from a four -input AND gate
w ith th r ee inp uts tied high The fourth Input
is DVI.
DVI is high except during an EAE
its

Input.

sequential

memory locations, one containing

the Instruction and the following one containing the number to be loaded into the SC.

This

instruction loads the complement of the memory
word bits 07 through 11, the word located In

the next sequential

memory address, into the

DVI instruction therefore, the output of this

SC.

AND gate Is high except for this Instruction,
making the output of the NOR gate low so

tion since It goes into an Execute cycle but,

This instruction is a two-cycle instruc-

zeros are placed Into MQ,, during any left

not start EAE timing. During the
Fetch cycle, the memory address Is Increment-

shift operation.

ed by one and loaded into the PC; then the

it does

memory word is loaded Into the MB and IR.
The contents of the PC are loaded into the

SC LOAD is caused by one input of a negative NOR gate being pulsed low by EAE TG(1)

and the Execute state is entered. During
the Execute cycle, the contents of the mem-

each time the EAE TG flip-flop clears (D-BSKE8I-0-2 D-1). The SC register (D-BS-KE8I0-3 B and C-2 through 7) has a negative NOR
gate connected to the data input of each flipflop
Each of these NOR gates has three Inputs except the one driving the data input of

ory word (next memory address) are comple-

mented and loaded into the SC.
During the Fetch cycle, the signal EAE INST

is generated

(D-BS-KE8I-0-2 C-4) by a four-

two NAND gates. Thus, when in the SCL
instruction Execute cycle SCL is low and
preven ts the generation of EAE SET and EAE
START. This is the circuit that inhibits EAE

NANDgate with B FETCH(l), OPR,
MBosO), MB,,(1); inverting the output
gives EAE INbt. All EAE instructions during
TP3, MBns , 09^ and 10 are loaded in the
EAE IR. EAE E SET (D-BS-KE8I-0-2 C-3)
input

timing during the SCL instruction.

goes low because of the negative NOR gate
whose inputs are MBo9(0) (now high), and
MB^q(0) (now low). This output combines
with EAE INST in a NAND gate giving EAE"
During logical sequence 3 PC
E SET.

are loaded into the SC by
] ]
two-input NAND gates (D-BS-KE8I-0-3 B-2

MBo7 through

The right-hand NAND gate for
each SC flip-flop has one input bussed to
MB - SC ENABLE. The other input is connected to the "zero" output of MBq7 through ,•
flip-flops. When MB -SC ENABLE is generated, all NAND gates which are high on
through 7) .

ENABLE is generated by EAE E SET (D-BS-8I0-4 A-70 (inverted by a negative NOR gate)
and combined with TS4 (1) and a NANDgate.
The output of this NAND gate qualifies a
negative NO R giving PC ENABLE. E SET is
generated by EAE E SET into a negative NOR
gate (D-BS-8I-0-3 C-4) whose output is E
SET. Therefore, at TP4 of the Fetch cyle
the EXECUTE flip-flop is set.

both inputs (that is, if the MB bit sampling
is

the data-input of their respective flip-flops.

Thus if MBo7 is actually a zero, the MBo7(0)

During the

Execute cycle, B EXECUTE(I) combines with
OPR in a NAN D gate (D-BS-K E8I-0-2 C-2)
The PC is
whose output is EAE EXECUTE

side will be high, qualifying its

inverted by the

NAND gate,

NOR gate, and applied to

the data-input of the SCO flip-flop.

When

the clock input is pulsed the SCO flip-flop

incremented by one, as in two cycle instrucEXECUTE as an input to a
negative NOR gate (D-BS-8I-0-5 A-5 and 6)

tions, by EAE

will set ("one" side high) giving the comple-

ment of MBo7

whose output is PC INCREMENT. MBqj
through -ii are complemented and loaded
into the SC. MUY +DVI, EAE ON(0), OPR,
and B EXECUTIVE (1) are the four inputs to a
NAND gate (D-BS-KE8I-0-2 C-7) whose
output is inverted and applied to a negative

NOR gate giving MB- SC ENABLE.

not set), have outputs inverted by negative

NOR gates and these outputs are applied to

The contents of the PC will be loaded into
the MA because F SET (D-BS-8I-0-3 D-5) is
now present. Although the CP is in the
Execute cycle and B FETCH (1) is now low,
EAE INST, and therefore, EAE E SET are no
longer available to cause E SET. F SET is an
input to a negative NOR gate (D-BS-8I-0-4
A-7), the output combines with TS4(1); in a
NAND gate giving PC ENABLE and when
inverted by a negative NOR gate it gives

It should

be noted that the SCL instruction is the only
instruction which will give B EXECUTE(I) and
EAE ON(0) concurrently. SC LOAD is developed by a two-input NAND gate (D-BSK ESI -0-2 D-1) with inputs of TP3 and EAE

PC ENABLE.

BEGIN.
AC. =AC -1, ACqq = L,
The output of this NAND gate is connected
NOR gate giving SC LOAD.
EAE BEGIN is generated by a negative NOR
gate (D-BS-KE8I-0-2 B-4)
One of the inputs
to this NOR gate is the output of a two-input
NAND gate with OPR and B EXECUTE(l) as

MQqq^AC^^, MQ. =MQ.-1,

to a negative

MQ^^ until ACqqT^ ACq^

inputs. In order to prevent EAE timing from
starting,

EAE BEGIN combines with SCL in

Two-Cycle Instructions

gate is inverted and applied to a negative
NOR gate giving AC LOAD.
SHIFT is

There are five two-cycle instructions that

generated by a four-input NAND gate (D-BS81-0-5 D -2) with inputs of EA E
SHIFT

start

EAE timing. These are: ASR, LSR, SHL,

MUY, and DVI.

These instructions are coded

ENABLE, TT SHIFT ENABLE and the high output of a NAND gate. EAE NO SHIFT
ENABLE is generated by B EAE ON (D-BSK £81 -0-2 D-6) when applied to a negative

in bits 08 through 10 of the instruction word.

This coding transfers timing from the CP to

EAE timing at TP3 of the Fetch cycle with
the operation being performed during the

NOR gate whose output

ENABLE.

generated during the

EAE NO SHIFT

Execute cycle. Some EAE microinstructions
con be microprogrammed to perform one twocycle and one or more single-cycle micro-

present until approximately 100 ns after TP3

instructions if they are logically compatible.

of the Fetch cycle.

This signal

Fetch cycle of all EAE instructions and is

L ENABLE is inhibited by EAE L

Arithmetic Shift Right (ASR)

DISABLE

placed in the L and ACoQ-

(D-BS-8I-04 A-2)
EAE L DISABLE is generated by EAE INST and MBo9(l), inputs to a
NAND gate (D-BS-KE8I-0-2 D-4) whose
output is connected to a NOR gate giving
EAE L DISABLE. When L ENABLE goes low
the L is not enabled because L ENABLE is
one of the inputs to an AND gate; therefore,
the output of this AND gate goes low (D-BS81-0-8 A-8) and the L is "zeroed".

are loaded into the EAE IR, the L is zeroed,

The PC is loaded into the MA (as discussed

the contents of the AC are loaded directly

under the SCL instruction) during TS4 of the

The ASR instruction (7415g) causes the combined contents of the AC and
to shift
right one position more than the number con-

tained in the next sequential core memory
location .
bits shifted past MQ] ] are

lost and the sign bit,

contained in ACoQ/ >s

During the Fetch
cycle, the contents of MB bits 08 through 10

back into the AC, and the EXECUTE flipflop is set.

Fetch cycle. The EXECUTE flip-flop is set
by B FETCH (1), OPR, MBo3(l), and MB]i(1)
(D-BS-KE8I-0-2 C-4). These inputs to a
NAND gate give a low output inverted by a
negative NOR giving EAE INST. EAE INST
combines with the output of a negative NOR
gate (high because o f MBio(0) in a NAND
gate whose output is EAE E SET. EAE E SET
is applied to a negative NOR gate (D-BS-8I0-3 C-4) giving E SET. At TP4 the EXECUTE

During the Execute cycle the

contents of MBqo through ,, are complement-

ed and loaded into the SC.

EAE timing is
then started, setting the PAUSE flip-flop,

and causing CP timing to be suspended during
the rest of this instruction.

During logical sequence 1 of the Fetch cycle,
the Lis zeroed by AC ENABLE, AC LOAD,

SHIFT, and L E NABLE (Inhibited). AC ENABLE
is generated by AC - MQ ENABLE, MB04(0),
and OP2 as inputs to an AND gate the output
of which is inverted (D-BS-8I-0-4 C-2) and
applied to a nega tive NOR gate wh ose output

flip-flop is set too "1".

During TS3 of the Execute cycle MBq-^ through
1]

are complemented and loaded into the SC

as was discussed in the SCL instruction.

AC ENABLE. AC - MQ ENABLE is inhibited by MBo4(0) (D-BS-KE8I-0-2 C-6). AC

EAE

timing is started by OPR and B EXECUTE(l),

LOAD is developed by a four-input AND gate

flip-flop is set to a "1 " as was discussed in

(D-BS-8I-0-6 D-6) with TP3, B FETCH(l),
and OPR as inputs. The output of this AND

EAE timin g. Wh en EAE timing is started,
EAE IR(1), DVI, and B EAE ON combine in

now high (D-BS-KE8I-0-2 A-4)

The PAUSE

NAND gate (D-BS-KE8I-0 -2 D-8) generating

of this

tied high so it inverts the signal and applies

NAND gate goes low it disables the

NAND gate to the right, thereby inhibiting
EAE LEFT S HIFT ENABLE.

The NAND gate has the other input

gates.

EAE RIGHT SHIFT ENABLE. When the output

to an

AND gate. The other input of this

gate is connected to CARRY OUTO. The
second gate (an AND gate) has CA RRY OUT
for its o ther input, therefore, when CARRY
OUT and ACqoCI) are both either high or
low one of the two AND gates qual ifies turning on the NOR gate above g iving ADDER L

also inhibits

LEFT SHIFT (D-BS-KE8I-0-3 B-8) by causing
the output of this NAND gate to go high. At
the same time it is applied to a negative NOR
gate (D-BS-8I-0-5 D-5) giving RIGHT SHIFT.
EAE AC ENABLE is generated by a two-input
NAND gate (D-BS-KE8I-0-2 D-5) with inputs
of B EAE
and the high output of a NAND
gate to the le ft. The ou tput of this NAND
gate is EAE AMENABLE. It is now high because one of the inputs is DVI, which is high

(low).

When CARRY OUT

or ACoq(1) are

opposite (one high and the other low) the

AND gates are inhibited and the o utput of
the NOR gate (ADDER L) is high. ADDER L
and RIGHT SHIFT are inputs to an AND gate

(D-BS-8I-0-4 D-1) generating AC ENABLE.

(D-BS-8I-0-9 sheet 1 C-8) . When ADDER L
is high and this AND gate qualifies, a NOR
on REG BUSS 00.
gate is turned on and puts a
REG BUSS 00 is connected to the data-input

ASR ENABLE is generated by a negative NOR

of the ACqq flip-flop. Therefore, if ACqq is
a 1, the L is s et too "1" (ASR ENABLE and

only duri ng the EAE DVI instruction. EAE AC
ENABLE is applied to a negative NOR gate

gate driven by a three-input NAND gate

(D-BS-KE8I-0-2 D-4).

This

ACo(l) giving ASR L SET low thus a high is
applied to the data-input of the LINK flipflop), and a "1" is set back into ACqq. (ASR

NAND gate has

ON, EAE IRO(l), and EAE
ASR ENABLE is applied to a three-

inputs of B EAE
IRl 0) .

input

ENABLE and ACqq (1) combine and the resultant comb ines with CARRY OUT
giving

NAND gate (D-BS-KE8I-0-2 A-8) and

ADDER L low; ADDER L then combines with

combines with EAE IR2(0) and ACqII). When
ACqO) is high ASR L SET is low, but when
ACq(I) is low ASR L SET is high ASR L SET

RIGHT SHIFT applying a "1", through the
REG BUSS 00, to the data-input of the ACqq
flip-flop.) At the same time each AC bit is

applied to a four-input

AND gate (D-BS-8I-

0-8 C-8) where it combines with RIGHT SHIFT
and the output of a NAND gate (high because
EAE ON(0) is low)
The output of this AND
gate is inverted by a NOR gate and applied
to the data-input of the LINK flip-flop. With
each AC LOAD generated the LINK flip-flop
will set if ACoo is a "1" and will reset if ACqo
is a "0".
Each time ACqq is a "1" th e NAN D
gate turns on (D-BS-KE8I-0-2 A-8)
ASR L
SET goes low, turning off the AND gate,
giving a high (D-BS-8I-0-8 C-8) out of the
NOR gate, and putting a high on the data-

shifted right one place .

This operation is
repeated until the number in the SC register

generates SC FULL and SCO (1) and causes

termination of EAE timing .

ACqq = ACqq
AC,,= MQ^^

MQ. =MQ. + 1,
I

Logical Shift Right (LSR)

ASR ENABLE,

along with ACqoO), B EAE ON, and EAE
IR2(0) qualifies an

00,

AC. = AC. +

MQ,, lost.

input of the LINK flip-flop.

The LSR instruction (741 7g) causes the combined contents of the AC and the
to shift

AND gate (D-BS-8I-0-8

A-7) whose output (high when ACqq 'S a "1 " ,
low when ACqq is a "0") is inverted by a NOR
gate and appears at the inputs of two different

right one position more than the number In

the next sequential core memory location
after the instruction.

MQ bits shifted past

MQ]

are lost and fhe L is loaded with a "0"

during this operation.

During the Fetch cycle
the contents of MB bits qq through ,q are load-

ed into the EAR IR register, the L is 'zeroed",
the contents of the AC are loaded directly

(1)

the content of the L is lost,

(2)

the content of ACqq is loaded into the L

(3)

all

bits

MQqi is loaded into AC] ]; all other MQ
move one place left, and

(5)

MQ]] is loaded with a "0".

(4)

back into the AC, and the EXECUTE flip-flop
are
The contents of MBq7 through
is set.
the
during
loaded
into
SC
complemented and
the Execute cycle. Then EAE timing is started
and CP timing is suspended. The contents of
the AC and MQ are then shifted the required
number of times to the right.

other AC bits move one place left,

-.-^

During the Fetch cycle the contents of MB^q
through ,q are loaded into the EAR IR, the
contents of the PC are loaded into the MA,

and the EXECUTE flip-flop is set. The contents
of MBq7 through , t are complemented and
loaded into the SC during the Execute cycle.
Then the CP PAUSE flip-flop is direct set and
EAE timing is started. The contents of the AC
and
are then shifted left the required
number of times.

During logical sequence 1 of the Fetch cycle
the L is "zeroed" by AC ENABLE, AC LOAD,

NO SHIFT, and L ENABLE (inhibited) as discussed under the ASR instruction

The PC is

loaded into the MA (as discussed under the

SCL instruction) during TS4 of the Fetch cycle.
EAE timing is started and CP timing is suspended as discussed under EAE timing
The logic

The logic Is the same as for the ASR and LSR
instructions during the Fetch cycle. During

the Execute cycle the logic is the same as the

for this instruction is the same as the logic for
the ASR instruction with the follo wing excep t -

ASR and LSR, until the EAE timing is started.

Ion: ASR ENABLE is generated, (ASR L SET
remains high at all times during this instruc-

AC ENABLE Is ge nerated by EAE AC ENABLE.
EAE AC ENABLE Is generated by a NAND

NAND gate (D-

tion because the four-input

gate (D-BS-KE8I-0-2 D-5) with B EAE

are discussed under the ASR instruction.

=ACoO/
uu AC. =AC. + 1,
I

EAE LEFT SHIFT ENABLE Is applied to the

MQ. = MQ. + 1
I

and EAE ACENABLE (bec ause DVI is low).
EAE LEFT SHIFT ENABLE is generated by a
four- input NAN D gate with inputs of B EAE
ON, DIV LAST, EAE RIGHT SHIFT ENABLE,
and the high output of a NAND gate (D-BSKE8I-0-2 D-7) (high because one Input is
DVI which is low).

BS-KE8I-0-2 A-8) is disqualified by EAE IR2
The NAND gate is disqualified as it is
(0) )
a "1" for the LSR instruction. Thus the datainput of the LINK flip-flop remains low and
the L stays reset. The proper gates for the
shifting of the AC and MQ bits to the right

input of a negative

NOR gate (D-BS-8I-0-5

D-4) giv ing LEFT SHIFT.

EAE RIGHT SHIFT
ENABLE (high) combines with B EAE ON in

NAND ga te (D-BS-KE8I-0-3 B-8) giving
LEFT SHIFT. This signal is Inverted and
applied to two negative NOR gates (D-BSKE8I-0-3 C-1 and 8). This high output is
bussed to one Input of a series of two-Input
NAND gates The other Input to each of
g

Shift Left (SHL)

The SHL instruction (741 3g) causes the com-

bined contents of the AC and the
to shift
left one position more than the number in the
next sequential core memory location after
the instruction. The following occurs for

NAND gates (except the one for MQ] ])
is MQj -1
The NAND gate for MQ^,
connected to a NOR gate (D-BS-KE8I-0-3 B-1)
these

each shift:

two-cycle instructions are performed: MA +
- PC, MEM - MB, 1 - EAE ON, 1 1
PAUSE, PC - MA, and 1 - F. The only
difference during the Execute cycl e for MU Y
and DVI is that instead of loading MBZ-ll SC, the SC is cleared to receive the number
of multiply operations. For each operation
the SC is incremented. As will be shown
the SC will never need to count more than

and this NOR gate has inputs from four AND
gates
The right -hand AND gate has inputs
of -3V and DVI. Since DVI is high except
.

during the DVI instruction, this AND gate
has a high output. The output of this

AND

connected to the input of a NOR gate
whose output is c onnected to the input of a
NAND gate with LEFT SHIFT as the other
input. Since this NAND gate remains "turned off" except during the DVI instruction
is

the negative

NOR gate it

driving will

keep the data input of the MQ]] flip-flop

Before discussing the actual logic of the

LOA D pulse. Therefore,
low for ea ch
each time LEFT SHIFT is present and we are
not doing a

instruction some discussion of binary multi-

plication, as performed by the EAE, is neces-

To multiply two numbers together
(12^0 times 12^o) with the EAE, the following operations are necessary. These numbers

DVI instruction the MQii flip-

flop will reset to a "0".

sary.

This means that

for each shift Os are loaded into MQ^
^
and transferred from MQ^ , to the vacated

positions in the

MQ.

in binary form are:

*11

001 lOO^.

Step 1

AC. -AC. -1, AC^^-L,
00

MQqq =AC^^, MQ

MQ. -1

=MQ 11

001

100

XOOl

100

000 000

partial product

Step 2

Multiply (MUY)
001

The MUY
number in the MQ by the number held in

the next successive core memory location
At the end of
after the MUY instruction

XOOl
000
0000
0000

the instruction, the twelve most significant
bits of the product are contained in the AC

Step 3

instruction (74058) multiplies the

100
100

000
00
000

(from Step

second partial product

and the twelve least significant bits of the
product are contained in the MQ. During
the Fetch cycle the usual operations neces-

001

XOOl
000
0000
00110
00110

sary for an EAE instruction are performed:

MA +

MUY

- PC, MEM - MB, MEM - IR,
MBgg through ^q "'EAE IR, -L, and the
1

Execute major state is entered. During the
Execute cycle the usual operations for the

100
100

000
00

(from Step 2)

000

third partial product

Step 4

remainder, the least significant bit of the
multiplier is examined, and if it contains a 1

001

100
100

XOOl
000 000
0000 00
00110

EAE MEM ENABLE must be geneIf it contains a
then EAE MEM

the signal
rated .

ENABLE must be inhibited, allowing Os to be
added to the contents of the AC . The EAE
actually shifts the contents of the AC and

(from Step 3)

0011 00

to the right to add Os.

010010 000

fourth partial product

The least significant

bit is examined, and if it is a 0, then the L,

AC, and MQ are shifted to the right.

If the

LSB is a 1 , then the MEM is added to the AC
and the L, AC and
are shifted to the

Step 5 and 6

001

100
100

right.

XOOl
000 000
0000 00
00110
0011 00
000000
000000
00010010 000
In Step

When MQ]

is a
MEM ENABLE is
ENABLE, AC LOAD, MQ
LOAD, and SHIFT RIGHT are generated.
When MQ^ ] is a 1 , MEM ENABLE, AC
ENABLE, AC LOAD, MQ LOAD, SHIFT
RIGHT are generated During an MUY instruction, if MQ^^ is a 1 then EAE MEM ENABLE (D-BS-KE8I-0-2 D-6) is low. MQ,^ (0)

(from Step 1)
(from Step 3)
(from Step 4)
(from Step 5)

(from Step 6)
final product

(144iq)

and MUY are two inputs to a NAND gate

the least significant bit in the multi-

(Os and Is) are

When MQ^

EAE MEM ENABLE Is one of the inputs to a
negative NOR gate (D-BS-8I-0-4 D-7) giving

being used by the computer

the least significant bit in the multiplier is a

MEM ENABLE 0-4 and MEM ENABLE 5-1
Therefore, if MQ^
o
MEM ENABLE 0-11

the multiplicand is added to the partial prod-

tial

When the least significant bit in the

multiplier is a

product.

NAND

(0) is low this
ga te has a
^
high output giving EAE MEM ENABLE (low).

Since binary numbers

some definite rules can be established. When

uct.

(the LSB)

plier is multiplied by the multiplicand and

forms a partial product.

inhibited and AC

(from Step 2)

generated.

AC ENABLE is generated by

EAE AC E NABLE (D-BS-8I-0-4 D-1). EAE AC
ENABLE is ge nerated by B EAE ON, and EAE

then Os are added to the parThe number of operations nec-

Ac ENABLE (D-BS-KE8I-0-2 D-5). AC LOAD

essary to perform this multiplication is six.

When the same multiplication is performed

using 12-bit numbers, the number of operations

MQ LOAD and SC LOAD are generated by

necessary is twelve.

EAE TG(1) (D-BS-KE8 I-0-2D-1). RIGHT
SHIFT is generated by EAE RIGHT SHIFT ENABLE (D- BS-8I-0-5 D-5). EAE RIGHT SHIFT
ENABLE is generated by EAE IRl(l), DVI, and
B EAE ON (D-BS-KE8I-0-2 D-8). As each

Since the SC must incre-

ment one time less than the number of operations performed, the SC reaches 12 to terminate

EAE timing. Even when multiplying the largest
binary numbers that can be expressed in 12-bits
the number of operations is the same, and the

operation is performed, a four-input AND gate
tests the SC register until MUY, SCl(l),

number of bits in the product will not exceed
twenty-four. When an addition of either
Os or the multiplicand

generated by EAE TP (D-BS-8I-0-6 D-7).

SC3(1), and SC4(1) are all high (D-BS-KE8I-0
-2 B-7). When this condition exists, it signi-

made to the partial

product, the least significant bit does not

fies that the multiplication is finished and ter-

change.

minates EAE timing.

In order to determine whether to add

Os or to add the multiplicand to the partial

YX MQ = AC, MQ. 0-L
16

remainder (now in the AC) may have to be

Divide (DVI)

corrected, and the LINK cleared.

The correction depends upon the last two bits in the quotient. If the last two bits are MQiq =
and
=
MQii 1, the remainder is correct as is. If

The DVI instruction (74078) divides the 24-bit
dividend contained in the AC (12 most significant bits) and the
(12 least significant

bits)

by the number located in the next se-

the last two bits are both Is, the remainder

quential core location after the DVI instruc-

must be complemented.

tion.

of MQ]Q MQ]] result in an extra addition or

Other combinations

subtraction.

Divide Algorithm

The simplest divide algorithm, although not
the one used in the KE8/I, is that of subtraction test, subtractions and shifts. Assume
that a double-precision number has been
loaded into the AC and MQ, and that the

The first subtraction in any divide must produce
a negative result; otherwise, a condition known
as "divide overflow" exists. If divide overflow occurs (division by zero Is a classical
example), the resulting quotient cannot be
contained in 12 bits, and the EAE signifies
this fact by Immediately exiting from the divi-

dividend is present in the MEM register.

sion with the LINK set.

trial

subtraction is taken (for example,

+ AC is placed on the register bus)

A
MEM

If an
overflow results, the subtraction cannot be
made without causing a change in sign. The
entire AC and
are shifted left without
actually executing the subtraction, and a

Before EAE timing is started at TP3 of the

Execute cycle TP3 and EAE BEGIN combine
In a NAND gate (D-BS-KE8I-0-2 D-1) giving
SC LOAD. Therefore, the SC is cleared be-

shifted into

quotient.

MQ]

fore the DVI instruction

to form a part of the

]

of, the shift, and a 1 is loaded into MQ..
The process is very similar to long-hand

the KE8/I, the algorithm used is slightly
more complicated, although faster. A subtraction and shift is performed
If overflow
In

EAE AC ENABLE. EAE AC ENABLE is one
input to a n^ative NOR gate (D-BS-8I-0-4
B-1) giving AC ENABLE. Therefore JC ENABLE gates the AC flip-flop "0" outputs to

does not result (indicated at ADDER L), a

loaded In MQ]]
Subtractions and shifts
continue until overflow occurs. When over-

flow occurs, a

loaded in MQ]] , and the

the ADDER bus giving the complement of the
AC which combines with the contents of MEM.

next arithmetic operation is an add and shift.
The adding process continues until another
overflow is encountered and Os are loaded

The result is a subtraction with the complement
of the result left In t he AC. MEM ENAB LE
0-11 Is generated by EAE MEM ENABLE as
inputs to two neg ative NOR gates (D- BS-8I0-4 D-5 and 6). EAE MEM ENABLE is generated by a NAND gate (D-BS-KE8I-0-2 D-6)
with inputs of EAE IRO, B EAE ON, and the
high outputs of two NAND gates. The

inka MQ^ ^ for each addition. The Os are
loaded into the
for each addition. Overflow indicates that the partial remainder is

now positive and that the arithmetic operation
should become a subtraction.

Figure 3,

During the first operation AC ENABL E is
is one of
always generated because SCO-3 =
the inputs to a three- input negative NOR
gate (D-BS-KE8I-0-2 D-5) . This output is
connected to a NAND gate above giving

decimal division.

started.

KE8/I EAE DVI Algorithm, shows the operations performed by the EAE to divide 145,0
by 12]o. The quotient will be 12]q (in the
AAQ) with a remainder of 1 ,q (in tne AC).

If overflow does not result, the

subtraction is performed before, or as a part

At the conclus-

ion of the divide operation (SC = 13), the

Step
Link

Carry

Accumulafor

Multiplier Quotient

Memory

000 000 000 000

000 010 010 001

000 000 001 100

111

SC ENABLE
MEM ENABLE

in I'll 111

000 000 001 100
000 OOO 001 01
000 000 010 111

Comments

Counter

000 000 001 100

000 100 100 010

00 001

Output of ADDERS
AC and MQ LEFT SHIFT
End of 1st operation

AC ENABLE

111 111 101 000

MEM ENABLE

000 000 001 100
111 111 110 100
111 111 101 000

000 000 001 100

001 001 000 100

00 010

Output of ADDERS
AC and
LEFT SHIFT
End of 2nd operation

111 111 101 000
000 000 001 100

AC ENABLE

111 111 110 100

Output of ADDERS
AC and MQ LEFT SHIFT

111 111 101 000

MEM ENABLE
010 010 001 000

000 000 001 100

00 011

End of 3rd operation

AC ENABLE

111 111 101 000

000 000 001 100

MEM ENABLE

111 111 110 100

Output of ADDERS
AC and
LEFT SHIFT
End of 4th operation

111 111 101 000

100 100 010 000

000 000 001 100

00 100

AC ENABLE

111 111 101 000
000 OOO 001 100

MEM ENABLE

111 111 110 100
111 111 101 001

001 000 100 000

000 000 001 100

00 101

Output of ADDERS
AC and
LEFT SHIFT

End of 5th operation
111 111 101 001

AC ENABLE

000 000 001 100

MEM ENABLE
Output of ADDERS

111 111 110 101
111 111 101 010

010 001 000 000

000 000 001 100

00 110

AC and MQ LEFT SHIFT
End of 6th operation

AC ENABLE

111 111 101 010

MEM ENABLE

000 000 001 100

mill no 110
in 111 101 100

100 010 000 000

000 000 001 100

00 111

Output of ADDERS
AC and MQ LEFT SHIFT
End of 7th operation

AC ENABLE

111 111 101 100

MEM ENABLE

000 000 001 100
111 111 111 000
111 111 110 001

000 000 001 100

000 100 000 000

000

Output of ADDERS
AC and
LEFT SHIFT

End of 8th operation

AC ENABLE

111 111 110 001

MEM ENABLE

000 000 001 100
111

101

111 111 111 010

111 111 111 010
000 000 001 100
000 OOO OOO no
000 000 001 100

001 000 000 000

000 000 001 100

01 001

Output of ADDERS
AC and
LEFT SHIR
End of 9th Operation

AC ENABLE

MEM ENABLE
Output of ADDERS
010 000 000 001

000 000 001 100

010

AC and MQ LEFT SHIFT
End of 10th operation

SC ENABLE

111 111 110 011

MEM ENABLE

000 000 001 100
111

in 111 111

111 111 111 111

100 000 000 011

000 000 001 100

01 oil

MEM ENALBE
000 000 001 100

000 000 000 110

01 100

HI 111 no 101

no 101

111 111

no 101

000 000 001 100
000 000 000 001
000 000 000 001

Output of ADDERS
AC and
LEFT SHIFT
End of 12th operation

SC ENABLE
MEM ENABLE

111 111 101 001

000 000 001 100
111 111

AC ENABLE

111 111 111 111

000 000 001 100
000 000 001 01
000 000 010 no

Output of ADDERS
AC and
LEFT SHIFT
End of 11th operation

0OOOOO0O1

OOO 000 001 100

100

01 101

Output of ADDERS
LEFT SHIFT ONLY
End of 13th operation

Since 5C = 13 and MQI^O
and MQ11=0 MEM and AC -AC.

000 000 001100

Figure 3

000 000 001100

01101

KE8/1 EAE DVI Algorithm
18

NO SHIFT

right-hand

of these two signals Is generated . A threeinput negative NOR gate (D-BS-8I-0-9 sheet

NAND gate has a high output be-

cause one of its inputs is MUY. The left-hand
NAND gate has four Inputs: MQnO), SC|(1),
(low until at least the 8th operation when the

4 C-1) has inputs of:

SC = 8), and DIV LAST (low until the SC =13

SC^ (1) is an input
or divide overflow occurs)
for this gate because if divide overflow occurs

When either of these signals is low this NOR

gate has a high output which combines with
LEFT SHIFT in an AND gate and is Inverted by

then SCo_3 = 0, ADDER L, and SC4(0) (D-BSgate
KE8I-0-2 A-7) are inputs to a
giving DIV LAST. Since SCi(1) Is low for

NAND

the above

NOR gate causing AC]] to be

If neither of these signals is low
=
and MQqq = 1 or MQ]] = 1 and
(MQ]]
=
MQqq 0) then AC]] is set.

cleared.

divide overflow this gate is inhibited at this
time. Also since one or more of these inputs

DIV LAST goes high EAE MEM
ENABLE is present until the SC = 13. Figure
4, KE8/I EAE DVI Flow Chart, shows the decisions made by the EAE logic for each divide
or MQ] i = 1 and
If the SC =
operation

is high

EAE MQO ENABLE, and

the output of NAND gate (high during DVI because EAE
(0) is low during EAE timing).

u ntil

ADDER L Is generated by a series of gates
(D-BS-8I-08 A, B, C - 7 and 8) . The two
AND gates at the bottom of the series have
inputs sampling t he c ondition of the LINK

When AC ENABLE is present L
ENABLE is generated by a negative NORgate

MQqo =

then the necessary gates are enabled
to place a "0" in AC]] . It follows that, the

flip-flop.

number Is complemented as it Is shifted from
MQqo to AC] , If a subtraction is being perThis step Is necessary because the
formed
effect, complemented Instead of
in
AC is,
complementing MEM. A NAND gate with
and SC4(0) (D-BS-KE8IInputs of SCq_3 =
0-2 C-3) has an output of SC = 0. Since the
SC = 1 or more during the DVI Instruction

(D-BS-8I-0-4 B-4) with EAE AC ENABLE as
an input. L ENABLE is generated by a NOR

gate because when EAE AC ENABLE is high
EAE L DISABLE is low giving a low out of the
AND gate it drives making L ENABLE go high.

The AND gates (D-BS-8I-0-8 A-7 and 8) will
have low outputs unless eitlier LINK(l) and

operation 2 through 13 this gate has a high
output except during operation number 1 A
negative NOR gate, to the right, has MQii(O)
"1" this
is set to a
as an input so that MQ]

L ENABLE or LINK

]

with DVI In a two-Input NAND gate. Tlie
output of this gate is applied to two (2) three-

AND

The left-hand NAND

OUTO
hand AND
AND gates will olway s have one inpu t high,
or low, depending on CARRY OUT 0. The
is inverted and applied to the leftgate. Therefore, one of these

as its other
gate has MQo(0) and B EAE
"0".
inputs. MQo(O) is high if MQoQ is a
Therefore when MQii(0) is high (MQ] ] = 0)
and MQqo = 0, EAE MQO ENABLE is gener-

other Input is either h igh or low depe nding
Is high
on the status of L^ If CARRY OUT

ated. The NAND gate on the right has inputs
of B EAE ON, and MQo(l), while the NAND
gates output is inverted.

and LINK(O) and L ENABLE or LINK (1) and
L ENABLE are high the low output of the
NOR Is inverted t urning on the ri ght-hand
AND gate making ADDER L low. ADDER L
will be low if there is a carry and L ENABLE
and LINK(0) are both hi gh or L EN ABLE and

follows that when

MQn(0) is low (MQii = 1), a high is applied
and MQo (l)
If MQ]] =
to this NAND gate
.

high (MQOO = 1) then EAE MQO ENABLE

generated .

MQqo =

bine with CARRY OUT O. When ther e Is a
i s low
carry from ADDER 00, CARRY OUT
gate . CARRY
turning off the right-hand

input is low giving a high output that combines

NAND gates.

L ENABLE are

The outputs of these gates go to a NOR
whose output is applied to two
above
gate
AND gates (one through an inverter) and comhigh

input

(0) and

Consequently if MQ^ ^ = and
or MQ] | = 1 and MQqq = 1 , one

LINK(l) are both high. ADDER L will also
be low if there is not a carry and if either
19

ADDER L M01 =
ADDER LM0I1=0
1

ADDER L M011=1
ADDER L M0H = O

\
MQ11=0

MQ11 =

DIV

LAST BY DEFINITION

MEM a AC
ADDERS

M010=1

•

M01 1-

"AC

MO 10=

•

M010=

M010 = 0- M01

= 1

MEM a AC

MEM a AC
—»AC

— AC

ZI
MQ LEFT SHIFT
'

EAE ON
1

EAE END
i

0-—-PAUSE

Figure 4

M010 = 0- MQ1I=0

KE8/I EAE DVI Flow Chart

L ENABLE or LINK(O) is low or if L ENABLE

When the SC reaches thirteen EAE timing is

or LlNK(l) is low.

terminated as discussed under EAR timing.

When SC =

there are three gates (D-BSKE81-0-3 B-1) which check the sta tus of th e
SC. The bottom gate has inputs of EAE TP,
SCl(O), SC2(0), and SC3(0) giving an output
of SCO-3 =
which combines with SC4(0).
This output is connected to a NOR gate with
its output connected to a NAND gate, inverted and applied to the data-input of the MQi
i
flip-flop. Thus when SC =
MQi-i is clear-

put until the last operation, or until

NAND gates determine the content of MQ^

MQio(0)
is

This output combines with
another NAND gate. If MQio(O)

high (MQio= 0) this

NAND gate has a low

MQ^iO). Consequently if DIV LAST is low,
and_MQjo= 0, MQn = 1, then EAE SC
ENABLE is generated. An AND gate to the
right has inputs of MQio(l) and MQii(0).

ADDER L is an input to an AND gate and a

When these inputs are high (MQiq = 1 and

negative NOR gate (D-BS-KE8I-0-3 B-1).

MQ^i = 0) t his AND gate generates EAE
AC ENABLE. A NAND gate, further to the

The outpu t of the n egative NOR is ADDER L.
Therefore ADDER L is combined with MQii,

right, goes low o n the last division if

MQiq =

AC ENABLE. Therefore
MQiq/
MQi or if it is the last operation and MQ]q =
1

-i

As an example, d uring operation
two ADDER L is high because CARRY OUT
flop -flop.

thus generating EAE

if it is

not the last operation and

low, L ENABLE is high an d LINK(Q) is high
(since the L is a "0") giving ADDER L high.
is

ADDER L is combined with MQi ^(1) in an
AND gate. Since MQ^i = before the shift,

the AC is complemented.

During the lost operation, or when SC = 13,

a four input NAND gate (D-BS-KE8I-0-2
D-6) tests
bit 1 1 to determine whether or

the

output, which is inverted and combined with

]

determining whether to set or clear the MQi

DIV

LAST goes high.

During Steps 2 through 12 the other three

ed.

SC = 13 then a series of gates (D-BS-KE8I-02 C and D-5) test to determine if the AC is
to be complemented. A NAND gate (with
inputs of DIV LAST and DVI) has a high out-

AND gate's output is high when inverted

by a NOR and applied to a NAND gate above.
This turns the previously mentioned NAND
gate off, its high output is inverted by a negative NOR and clears the MQ^, flip-flop.
Thus MQ]] contains a "0" at the end of the

not

MEM ENABLE is to be generated.

DVI

high for all of the DVI instruction, DIV
LAST is high only during the last operation or
is

divide overflow.

SCl(l) is also high during

the last instruction so if MQii(l) is high

second operation.

MEM ENABLE is inhibited, but if MQtt(1) is
low or if MQii =
then MEM ENABLE is

During operation 10 (see Figure 4) CARRY
is low, L ENABL E is high, and LINK(l)
is high gi ving ADDER L high (D-BS-8I-0-8).

generated

OUT

NAND

During operation 12, a three-input
gate (D-BS-KE8I-0-2 D-7) with inputs of

ADDER L puts a high input on the left-hand

AND gate and a low input on the right-hand
AND gate (D-BS-KE8I-0-3 B-1), but MQii =
0, therefore, MQii(l)
low and both AND
gates have low outputs. The NOR gate above
has a high output which turns on the NAND

SCl(l ), DVI, and SC2(1) qualif ies and inhibits

lArLEFTSHlFTENABLE then generates

EAE NO SHIFT ENABLE giving NO SHIFT.
However, since E AE RIGHT SH IFT ENABLE

high (MQ) LEFT S HIFT is still presen t.
During o peration 13 since EAE LEFT SHIFT
is still

above it setting MQ^ ^

ENABLE and EAE NO SHIFT ENABLE are
After each operation the SC is incremented by

still

one and tested to see if it equals thirteen.

fore, the

high,

NO SHIFT

is still

present, there-

AC is either complemented and

loaded back into the AC o r just loa ded back.
SHIFT combines with ADDER L in an

AND gate (D-BS-8I-0-8 C-7) clearing the L
to a "0" indicating no overflow.

As soon as the DVI instruction is completed
EAE timing is stopped and CP timing is started
as explained under EAE Timing Termination.

AAAINTE NANCE

The maintenance procedures for the PDP-8/l
should be followed for the KE8/1 control logic.

ENGINEERING DRAWINGS
The following drawings pertaining to the
KE8/1 are included in this section
.

Drawing No.

Title

Rev.

D-BS-KE8I-0-1
D-BS-KE8I-0-2
D-BS-KE8I-0-3

EAE Flow Diagram
EAE Control

Multiplier Quotient

and Step Counter

0 — I83X QJ

drawing and »p»cific«tioni, herein, are tftt property at Digital

Equipment COfpontion atid «h»ll not lie

DVI

MUY

reproauced or copted or ustd in whot* or in tart as
le tMti* tor the manuracture or sate of it*m« witMut

MA +

—PC

MA +

—^PC
CSC^O OR

|j/QIO=MQ!l

MEM—MB

—IR

MB04(0).MBCS (0)»MB0 6 (0)»MB07(0)
AC +MQ

)

MB04(0).MB06 (0

SCL+ASR+LSR + SHL

AC + SC

lSC=O.L(lI]

MB 7-1

—SC

MB04 (0»MB06 (I)

SCL

O—AC
I

-t-

—EAE ON

—AC

+
MQlO(O)

MOIOCO)

MQII (0)

MEM ADD

(I)

— PAUSE

—EAE ON

MUY+DVI+ASR + LSR+SHL+SCL
BRK REQ

DATA

BRK REQ

PROGRAM

-—

BRK REQ

DATA

PROGRAM

ADD-^MA

—MA

MQII

(I)

—AC

EAE

JMS

SHL
AND
NMI

I^E

M Q

LOST

mIT

[

MUY

LOST

JMS

CYCLE

DVI

]

-» invert"}
|

-»

'
'

En'd"

-—{T},
LOST

CYCLE
1

i
1

jJNLESS OTHERWISE SPECIFIED

EQU

P M E NT
CORP ORATION

DRN^

UNLESS OTHERWISE SPECIFIED
J-,

TOLERANCES
DECIMALS
± 005

FRACTIONS

ANGLES

* 1/64

± 0°30'

FINAL SURFACE QUALITV

REMOVE BURRS AND BREAK SHARP
CORNERS

MATERIAL

DATE

'=>"''?

DIMENSION IN INCHES

<N'

MEM ADD

MQIO (I)

»j

E pH

\MUY + DVI + ASR+LSR+SHL4-SCL

DATA

0—EAE ON
t

I—

SC?t|3
SC=IJ
MQ 10(1)
«
MQI 1(0)

n WIUY + DVI + ASR + LSR

ASR + LSR

SCit|2
L & AC
ROTATE LEFT

—EAE IR

MB8-I0

MUY + DVI

— PA USE

AC—MQ

MB07(I)

MQ ROTATE LEFT
SC = I2

MQ—AC

Csct'q + L(Ol]

0—EAE ON

—AC

MB04(I>MB05(I)

MEM ADD TO AC

MUY+DVI

—AC

MB04(0«MBO5(O)»MBO6C0) + MB07CI)

QMaiOiitMQIjIl

MEM ADD TO AC
-\

MB04(0)»MB05(I

[SC=0 OR

MEM—MB

T2
MEM

G -r

Il»

y^'c^

nT^

DATE
/'

PROD.

DATE

^^ -';.., 7.,....,..'i(

i/y?

EAE FLOW
DIAGRAM

FIRST JSED ON

— UA-BI— 0—0
SIZE CODE

NUMBER

nrxnumnA

D FD KE8ISHEET

DEC FORM NO

-I

?-0-I83><|S9|o|2
This drawing and specifications, hereir. are the property af Dtgital Eaulpmtnt Cor^orMlon and shall fioI be
produced or copied or uud in whole of in part as
e basis for the menutacture or silt ot items without

NOTE;

SIGNAL NAMES INDICATE
ASSERTED STATES FOR,
HIGHM LEVELS PER DEC
STD 05 4

UNLESS OTHERWISE SPECIFIED
UNLESS OTHERWISE SPECIFIED
DIMENSION IN INCHES

TOLERANCES
DECIMALS

ooa

FRACTIONS

ANGLES

± l/M

- o*30'

FINAL SURFACE QUALPTY
REMOVE BUnnS AND BREAK SH>(rP

,'Y P.

l2ih,^

EQUIPMENT

DATE,

(?A^rM^

DATE

C )j. C^foA.^

In- 1'-

DATE

SDIDDiD CORPORATION
I

DATE
pjraj.

7!„/Y,^.^S*
FIRST USED ON
E

MULTIPLIER QUOT
$ STEP COUNTER

-UA -81— 0-0
NUMBER

CODE

REV.

-3

BS KE8II