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DEC-8I-H80A-D
December 1971
68 pages
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DC08A
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DEC-8I-H80A-D
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68
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https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-8i-h80/dec-8i-h80a-d.pdf
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Equipment Corporation Maynard, Massachusetts Digital PDP-8 Data Communications Equipment DC08A Serial Line Multiplexer SBRIflnSII UUbJUUBIU DEC-8I-H80A-D DC08A SERIAL LINE MULTIPLEXER DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS 1st Edition September 1969 2nd Printing March 1970 3rd Printing February 1 97 Copyright © 1969, 1970, 1971 by Digital Equipment Corporation The material in this manual tion purposes and is is for informa- subject to change with- out notice. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC PDP FLIP CHIP FOCAL COMPUTER LAB DIGITAL CONTENTS Page CHAPTER 1 INTRODUCTION AND DESCRIPTION 1.1 Scope of Manual 1-1 1.2 Equipment Application 1-1 1.3 Equipment Description 1-1 1.3. 1 DL8I Data Line Interface 1-3 1.3.2 DC08A Serial Line Multiplexer 1-3 1.4 System Operation 1-3 TTO (and TTINCR) Instruction Implementation 1-4 1.4.2 TTI Instruction Implementation 1-4 1.4.3 Conventional IOT Instructions 1-7 1.5 Line Interface Options 1-8 1.5.1 DC08B Local Terminal Connector Panel 1-8 1.5.2 DC08C Telegraph Line Adapter Panel 1-9 1.5.3 DC08D Telegraph Line Terminator Panel 1-9 DC08EB Telegraph Line Current Adjustment and Meter Panel 1-9 1.5.5 DC08F Modem Interface Control 1-9 1.5.6 DC08FE Channel Extension 1-9 1.5.7 DC08FF Channel Extension 1-9 1.5.8 DC08FX Control Extension 1-9 DC08H Automatic Calling Unit 1-9 1 1 1 .4. 1 .5.4 .5.9 CHAPTER 2 INSTALLATION 2.1 DL8I Data Line Interface Installation 2-1 2.1.1 Module Location 2-1 2.1.2 Special Wiring (Field Installation Only) 2-1 2.1.3 Power Requirements 2-1 2.1.4 Interface Cabling 2-1 2.2 Serial Multiplexer DC08A Installation 2-2 2.2.1 Module Location 2-2 2.2.2 Power Requirements 2-2 2.2.3 Interface Cabling 2-2 CHAPTER 3 3-1 OPERATION in CONTENTS (Cont) Page CHAPTER 4 THEORY OF OPERATION 4.1 General 4-1 4.2 Functional Description 4-1 4.2.1 Fetch Cycle (F) 4-1 4.2.2 Status Cycle (S) 4-8 4.2.3 Character Cycle 4-9 4.3 DL8I Detailed Logic Description 4-11 4.3.1 General 4-11 4.3.2 Fetch (F) Cycle 4-11 4.3.3 Status (S) Cycle 4-13 4.3.4 Character (C) Cycle 4-17 4.4 DC08A Detailed Logic Description 4-18 General H-- IO 4.4.2 Block Diagram Description 4-20 4.4.3 Line Control Module M750 4-20 4.4.4 Clock Skip and Interrupt Circuits 4-23 4.4.5 Line Register and Control Theory 4-25 4.4.6 Instruction Decoder 4-27 4,4,7 Line Control Gating Circuits 4-27 CHAPTER 5 MAINTENANCE 5-1 CHAPTER 6 DIAGRAMS 6-1 t A 1 A in APPENDICES r\rr o v-nara«jrer Mssemoiy juorounne utc-oi-rovM-i/ yv.uo o-Dir r>t r-m # a r*w r\s~r\c> n« i. <^l_ _*._.. a i. I r i. . _ • . B DEC-8I-F5VA-D DC08 5-Bit Character Assembly Subroutine B-l C MAINDEC 8I-D8AA-D DC08T1,- DC08 Off-Line IOT and Data Test C-I MAINDEC 8I-D8BA-D DCG8T2, DC08On-Line Data Exercise D-I ILLUSTRATIONS 1-1 Basic Block Diagram 1-2 1-2 Typical Service Series 1-5 1-3 Line Servicing Group of Instructions 1-5 IV CONTENTS (Cont) ILLUSTRATIONS (Cont) Page 1-4 Typical Teletypewriter Character (353g) 1~6 4-1 DL8I Flow Diagram (Sheet 1) 4-2 4-1 DL8I Flow Diagram (Sheet 2) 4-3 4-1 DL8I Flow Diagram (Sheet 3) 4-4 4-2 Format of TT Instruction Words in MB 4-7 4-3 Format of Line Status Word (LSW) 4-8 4-4 Simplified Log ic Diagram, F State, TS 3 4-12 4-5 Simplified Log ic Diagram, F-TS 4 4-13 4-6 Simplified Log ic Diagram, S and C States, S-TS 1 and C-TS 4-7 Simplified Log ic Diagram S-TS 2A and 2B 4-15 4-8 Simplified Log ic Diagram, S State, TS 2C 4-16 4-9 Simplified Log ic Diagram, S-TS 3 4-17 4-10 Simplified Log ic Diagram, S State TS 4 (S-TS 4) 4-17 4-11 Simplified Log ic Diagram, C State, TS 2 (C-TS 2) 4-18 4-12 Simplified Log ic Diagram, C State, TS 3 4-19 4-13 DC08A Simplified Block Diagram 4-21 4-14 Line Control Logic Diagram 4-22 4-15 Clock, Skip and Interrupt Logic Diagram 4-24 4-16 Line Register and R Register, Block Diagram 4-26 4-17 IOT Instruction Decoder, Block Diagram 4-28 4-18 Line Control Gating Circuits, Block Diagram 4-29 1 4-14 TABLES 1-1 Line Interface Options 1-2 1-2 IOT Instruction Codes and Functions 1-7 2-1 PDP-8I to DL8I Connector Pin Designations 2-2 2-2 DC08A to PDP-8/I Interface Cabling 2-3 2-3 Memory Signal Transfer Cable Pin Locations 2-3 2-4 Transmit and Receive Signal Pin Designations 2-4 4-1 PDP-8/I - DL8I - DC08A Interface Signal Reference Table 4-5 CHAPTER 1 INTRODUCTION AND DESCRIPTION 1.1 SCOPE OF AAA NUAL This manual describes the DC08 Data Communications equipment in general. both the DL8I Data Line Interface and the DC08A Serial Line Multiplexer. It contains specific information for Line interface hardware options are listed in this chapter; however, detailed information for each hardware option is a separate addendum to this manual. 1.2 EQUIPMENT APPLICATION The DC08 Data Communications equipment can interface as many as 128 serial, asynchronous, full-duplex communication lines to a PDP-8/I Computer. The DC08 equipment can be connected to a variety of lines with different baud rates; for example, communication can be with local or remote terminals, over telegraph, or any other low-speed data line. Communication can be simplex, duplex, or half-duplex (up to four different speeds), depending on the system configuration and the line options in use. be a full-duplex asynchronous line. In this manual, a data line is considered to A complete data communications system, including the PDP-8/I and the DC08, can be connected to a remote large-scale computer using a high-speed data link between computers. The DC08 and PDP-8/1 then converse with the individual data lines on a real-time (low-speed) basis and provide concentrated high-speed data to the larger computer. In this application, the DC08 becomes a part of what is termed the 6801 Data Communications System. The line interface options listed in Table 1-1 are used to connect the DC08 equipment to the different types of communication lines. 1.3 EQUIPMENT DESCRIPTION The DC08 equipment usually connects the PDP-8/1 Computer and one or more line interface options through use of the DL8I and the DC08A (see Figure 1-1). reference only. The PDP-8/1 and two specific line interface options are shown for At least one line sampling clock is required by the DC08 system. The choice of clock frequency depends on the application; therefore, the line sampling clock is shown separately and becomes an option. clock is supplied with the system, and unless otherwise specified, it is 110 baud. times the baud rate of the lines it is used to sample. One Each clock operates at five Up to four clocks can be used to sample four different data rates under program control 1-1 Table 1-1 Line Interface Options DC08B Local Terminal Connector Panel DC08C Telegraph Line Adapter Panel DC08D Telegraph Line Terminator Pane! DC08EB Telegraph Line Current Adjustment Panel DC08F EIA Modem Interface DC08FE Extension to DC08F for 32 lines DC08FF Extension to DC08FE for 32 lines DC08FX Extension to DC08F for line status control DC08H Automatic Calling Unit DC08Y Line Sampling Clock I | LINE DATA IN /OUT | INSTRUCTIONS, LINE NUMBER, CONTROLS PDP-8/I COMPUTER CONTROL SIGNALS CONTROL SIGNALS DL81 DATA LINE INTERFACE DC08A LINE SERIAL LINE SAMPLING MULTIPLEXER CLOGK(S) fl-OCATEDINPDP-8/1) [1-1 28 DATA LINES) -? — DIAL DIGITS.CONTROLS ^ L. ! I I DC08H.J DC08F AUTOMATIC MODEM DC08B TELETYPE CONNECTOR INTERFACE PANEL CALLING UNIT i • 1 I CALL CONTROL fDATA fDATA i: BELL 801 LOCAL TTY TERMINALS CALL Figure 1-1 Basic Block Diagram 1-2 OTHER LINE INTERFACE UNITS | I 1 DL8I Data Line Interface 1.3.1 The DL8I is the control interface between the PDP-8/1 and the DC08A. It is physically located in the PDP-8/1 processor and is connected to the DC08A by cable. The DL8I responds to the three special IOT instructions that are added to the PDP-8/1. On receipt of one of these special instructions, the DL8I takes control of the PDP-8/1 program for the time required to transfer data to or from the communication lines via the DC08A. The DL8I also maintains a control signal interface with the DC08A. 1.3.2 DC08A Serial Line Multiplexer The DC08A is mounted in a separate equipment cabinet located adjacent to the PDP-8/1 (with DL8I). The re- quired data line interfaces and line sampling clocks are mounted in the same cabinet as the DC08A, or in adjacent cabinets. The DC08A is essentially an automatically controlled, dual-purpose switch that: Connects any selected data line to a single line input to the computer for data transfers into the PDP-8/1. a. b. Connects the single line output of the computer to any selected data line for data transfers out of the PDP-8/1. NOTE The DC08 equipment employs bit multiplexing (as opposed to character or message multiplexing). Using bit multi- plexing, only one bit position of a data character can be transferred (in or out) each time the selected line is ser- The line data rates are very low compared to the computer cycle rate; thus, it is possible to service all viced. data lines in a relatively small percentage of available computer time 1.4 SYSTEM OPERATION The DC08 Data Communications equipment operates in response to the special IOT instructions associated with teletype information transfer. a. These special instructions are as follows: TTO (TT out) - This instruction acts on the AC register and on the selected output line. The in- struction is executed during one computer fetch (F) cycle to shift the AC contents one position to the right and transfer the rightmost bit (AC11) through the DC08A to the output line. 1-3 b. TTINCR (TT increment) - This instruction is usually microprogrammed with the TTO instruction to increment the line selection register (LSR). Incrementing the LSR causes selection of the next consecu- tive output line number (after the TTO action) and increases software efficiency. c. It is TTI (TT in) - This instruction is used to transfer the line state from an input line to the computer. the most complex of the TT instructions because it involves three locations in core memory and can cause two additional cycles to follow the F cycle. The memory locations are used to store the line status word (LSW) and the character assembly word (CAW) for each input data line. The additional cycles are used to examine the LSW (S cycle) and load the CAW (C cycle) with line data at the proper time. 1.4.1 TTO (and TTINCR) Instruction Implementation Serial data is transferred from the PDP-8/I to the data lines, using the TTO (6404) instruction. This can be done in two ways: a. randomly, in which case the line sequence must be individually specified and software loaded into the LSR using conventional IOT instructions b. 1.4.2 sequentially, using combined TTO and TTINCR (6405) instructions, which increments the LSR after TTI Instruction Implementation Serial data is assembled into the PDP-8/I from the data lines using the TTI (6402) instruction in a service series. The system performs the service series, scanning every line during each clock interrupt. times the baud rate. Interrupts occur at five A section of a typical service series is shown below in Figure 1-2, with details shown in Figures 1-3 and 1-4. NOTE CAW is initialized to 2000 for 8-bit characters and to 0200 for 5-bit characters. /LINE 47 8 0674 6402 TTI 0675 0470 LSW 0676 0200 CAW 0677 4511 JMS 0700 6402 TTI 0701 0100 LSW 0702 2000 CAW 0703 4511 JMS I ASSMBL 0704 6402 TTI I ASSMBL /LINE 10 /LINE 60 1-4 8 8 0705 0600 LSW 0706 2000 CAW 0707 4511 JMS 0710 6402 TTI 0711 0110 LSW 0712 0200 CAW 0713 4511 JMS 0714 6402 TTI 0715 0610 LSW 0716 2000 CAW 0717 4511 JMS 0720 6402 TTI 0721 0120 LSW 0722 0200 CAW 0723 4511 JMS I ASSMBL 0724 6402 TTI 0725 0620 LSW 0726 0200 CAW 0727 4511 JMS I ASSMBL I ASSMBL /LINE llg I ASSMBL /LINE 61 I 8 ASSMBL /LINE 12 /LINE 62 Figure 1-2 8 8 Typical Service Series LINE ACTIVITY ADDRESS ACTIVE /INACTIVE 6402—TTI REAL TIME CLOCK (LINE NUMBER) NOT USED [IN THIS (LINE SAMPLING COUNTER) EXAMPLE:LINE Oil] INSTRUCTION ADDRESS OF INSTRUCTION- 0110— LSW* 1 1 0710 — 6402 — 1 2 3 4 5 6 7 8 9 10 11 2 3 4 5 6 7 8 9 10 11 1 — 10 0712 — 2000 — 0713 — 451 —I 0711 01 1 2000— CAW* 4511 — JMS Figure 1-3 1 INITIALIZE Line Servicing Group of Instructions 1-5 START -k •K OCTAL -S-J OCTAL-5 OCTAL- 3 STOP*) I I SPACE LEVEL- LSB MSB MARK LEVEL I I 1 I START BIT TWO STOP BITS EIGHT DATA BITS NOTE: HEAVY LINES INDICATE N0N-CHAN6ING BIT STRUCTURE. Figure 1-4 Typical Teletypewriter Character (353 8 ) The service series consists of a string of line servicing instruction groups (TTI block), with one group of two instructions for each line. The TTI command uses three memory locations, the actual TTI instruction and the two locations following pected. it. The servicing group shown in Figure 1-3 does not consist of four instructions as ex- The two locations following, used for line status and character assembly purposes, are called the line status QUA ~nA ..%*.^ (I x>_.*<., ^,ivj \A/rtr/-J *U« l„ ,„~..J «-*.:..« I.. r i^ „«.«.«,»v,U mC y~U~r~ v.i'uiul-iCi uucmuijf nv/iu (TA\M\ y^-/-ii»/, -« iS»|jCbiivcijr. storage locations is usually a JMS (jump to subroutine). Tl IMC t 1 1 «i;__ r_ !_...?__ j.l_ iL IUI lUllOwiliy *._.. 131 1 u<- I I I I lie 1 1 II CC tti II I The subroutine can be used for limited data processing and storage and is usually entered only after the CAW is complete and R/ 0. The structure of the LSW is shown in the upper portion of Figure 1-3. of the particular line. active during the Bit is last sampling. line being serviced. Bits 9, if the line a Bit 1 10, and is 1 1 Bit is used to indicate the activity status was inactive during the last sampling; bit not used. Bits 2 is a 1 if the line was through 8 contain the line number (in octal) of the are used as a real-time counter to approximate the center of the bit to be sampled, thereby increasing the amount of telegraph distortion which can be tolerated over what could be tolerated with early or late sampling. Sampling takes place after the real-time clock, which is incremented on each service series after the start bit has been detected, reaches a count of two. The data is actually sampled between 40 and 60 percent after its starting point (where 50 percent is the theoretical center of the bit). Clock interrupts (and consequently complete service series) are occurring at five times the line data rate. Data seldom appears at exactly the same instant as the clock interrupt. The actual position (software) of the particular service group in the service series also affects sampling time. After the data is sampled, the real-time counter continues counting clock interrupts to a count of four and is reset to zero for the next data bit. This series continues until a complete character has been assembled in the CAW. When the real-time clock count equals two and a complete character has been loaded into the CAW, all steps have been performed except the JMS. When the character is assembled, the hardware causes a JMS to be performed to store the character and re-initialize the 1-0 CAW. If, however, hardware register R, software controlled, is at zero because the programmed number of storage subroutines have already been performed, the JMS is skipped until one of the next four service series. Then the character is stored and the CAW is reinitialized. Therefore, a TTI service group always requires at least two machine cycles (TTI and LSW); at times, three machine cycles (TTI, LSW, and CAW); and sometimes the service subroutines plus the storage subroutine. Conventional IOT Instructions 1.4.3 Table 1-2 lists the conventional IOT instructions used to program the DC08 equipment. are similar to those used in programming the 680 Data Communication System. These IOT instructions The basic difference is that load IOT's do not clear the AC. Table 1-2 IOT Instruction Codes and Functions IOT Code 6402 TTI Function Inputs data to MBO. Requires 2 or 3 machine cycles depending on line activity and real time clock count. Fetch (F) cycle and status (S) cycle are always performed. S-cycle summarization: . . . . . . . MEM 2-8 - LSR LH-HS LINE - MBO if MEMO = or HS = 1 - MB if MEMO = 1 and MEM 9 = and HS = 1 MEMO - 8 - MBO - 8 and - MB9-11 if MEMO = 1 and MEM9 = 1 and HS = +2 - PC if MB9 - 1 ^ 2 MEM + 1 1 - C if MB9 - 11 = 2 (enter C cycle) C-cycle summarization: <-p LINE -MBO and MEM * MB if HS=0 . MEM -MB if HS= 1 + 1 -PC if MB11 =0or if MB11 = and R=0 1 -LH if MB11 = 1 and R=0 MEM S£ AC and LINE - ACO if MB1 1 = 1 and HS = MEM - AC if MB1 1 = 1 and HS = and R ^ 0-LH if MB11 = 1 and R t^O 1 and R ? 1 no Tl OFF T2 OFF T3 OFF T4 OFF 6404 6422 6432 6442 6452 Outputs data from AC11 (buffered), summarized as: . 0-L . AC1 . L - ACO . AC SHIFT RIGHT Clears clock - LINE output flip-flop 1 1 enable flip-flop; inhibits clock 1 flag flip-flop. Clears clock 2 enable flip-flop; inhibits clock 2 flag flip-flop. Clears clock 3 enable flip-flop; inhibits clock 3 flag flip-flop. Clears clock 4 enable flip-flop; inhibits clock 4 flag flip-flop. 1-7 Table 1-2 (Cont) IOT Instruction Codes and Functions IOT Code Tl SKIP T2 SKIP T3 SKIP T4 SKIP 6421 6431 6441 6451 Function Causes program to skip next instruction if dock 1 fiag is set. Causes program to skip next instruction if clock 2 flag is set. Causes program to skip next instruction if clock 3 flag is set. Causes program to skip next instruction if clock 4 flag is set. Line Selection Register (LSR) Control Instructions TT I NCR 6401 Increments the LSR by 1. Can be microprogrammed to occur following TTO by code 6404 TTCL 6411 Clears the LSR TTLL TTSL 6412 6413 Clears the LSR and loads AC5-11 into the LSR. ORs AC5-11 into LSR Microprogram of TTCL and TTLL. 6414 TTRL ORs content of LSR into AC5-1 1 . AC must be zero for true transfer. R-Register (Load Distribution Counter) Control Instructions TTR I NCR 6461 Increments the R-register by 1. TT RR 6464 ORs content of R-register into AC7-1 1 . AC must be zero for true transfer. Clock Control Instructions Tl ON T2 0N T3 ON T4 0N 1 .5 6424 6434 6444 6454 Sets clock 1 enable flip-flop; clears clock 1 flag flip-flop Sets clock 2 enable flip-flop; clears clock 2 flag flip-flop Sets clock 3 enable flip-flop; clears clock 3 flag flip-flop Sets clock 4 enable flip-flop; clears clock 4 flag flip-flop LINE INTERFACE OPTIONS The purpose of the foiiowing paragraphs is to introduce the various line interface options. Technical details of each line interface option, as well as comprehensive functional descriptions, are contained in the addenda to this manual. Terminals (both local and remote), telegraph, and dataphone lines may be interfaced using the line interface options described below. 1.5. 1 DC08B Local Terminal Connector Panel me DC08B Local Terminal Connector Panel can connect as many as 43 local lines or data sets (data only) to the DC08A. A local line is limited to approximately 1500 ft of cable. Panels can be connected to a DC08A. Up to three DC08B Local Terminal Connector However, only 128 of the available 144 lines can be used. i-8 1.5.2 DC08C Telegraph Line Adapter Panel The DC08C can connect as many as 32 telegraph lines to the DC08A. Four DC08C Telegraph Line Adapter Panels can be used with the DC08A. 1.5.3 DC08D Telegraph Line Terminator Panel The DC08D provides demarcation point (terminal block) for interfacing between DEC equipment and 32 telegraph lines. 1 .5.4 DC08EB Telegraph Line Current Adjustment and Meter Panel The DC08EB provides rheostats and meters to adjust and monitor line current for transmit/receive on each of 32 lines, 1.5.5 DC08F Modem Interface Control The DC08F can be used to interface and control as many as 64 Bell System 103A, 103E, 103F, or the equivalent, data sets to the DC08A. Line control is provided by one DC08G module and cable set for every two data lines. A DC08G consists of a M753 module and two BC01B-25 data set connector cables to connect two data sets (modems) 1 .5.6 DC08FE Channel Extension The DC08FE is used to extend DC08F by an additional 32 data lines. 1.5.7 DC08FF Channel Extension The DC08FF is used to extend DC08FE by an additional 32 data lines. 1.5.8 DC08FX Control Extension The DC08FX provides DC08F with the capability of reading the carrier status of all lines at any time. The DC08FX is a wiring option in the DC08F hardware. 1 .5.9 DC08H Automatic Calling Unit The DC08H provides automatic callup interface for up to 10 data lines on a per-line basis, using DC08J module and cable sets connected to Bell System Type 801 automatic calling units, or equivalent. 1-9 CHAPTER 2 INSTALLATION 2. 1 DL8I DATA LINE INTERFACE INSTALLATION All PDP-8/I Computers are wired to accept the 13 modules that form the DL8I Datg Line Interface. No additional cables or power distribution lines are required. 2.1.1 Module Location Module Utilization drawing D-MU-8I-0-17 (Sheet 1) shows the rack location of the 13 DL8I modules. Five modules are mounted in locations C07 through Cll, and the remainder are mounted in locations D04 through Dll 2. 1.2 Special Wiring (Field Installation Only) All PDP-8/I Computers contain factory -installed jumpers that must be removed when options are installed in the field. Temporary Jumper drawing A-SP-8I-0-23 (Sheet 2) lists 20 jumpers that must be removed on installation of the 13 DL8I modules. 2.1.3 Power Requirements The DL8I modules are supplied by the PDP-8/I power supply with no additional power supply needed. 2.1.4 Interface Cabling A special cable connects location D04 in the PDP-8/I rack to location A09 in the DC08A rack and provides the interface between the DL8I and the DC08A. The cable type is W011 . Connector pin signal names and origins are listed in Table 2-1 NOTE Two signals, TT INST and LINE MUX(O), are on I/O bus lines. 2-1 Table 2-1 PDP-8I to DL8I Connector Pin Designations Signal Pins Origin Transmit Receive Module Module D2 B LINE HOLD DL8/1 M661 MI01 E2 BTP3 DL8/1 M660 M113 H2 B DL8/I M660 M751 K2 BC(0) DL8/I M661 M101 M2 STLR DL8/1 M661 M101 P2 B DC INST DL8/1 M660 M101 T2 LHS(l) DC08A M750 M516 V2 BR=0 DC08A M623 M516 MEM LSR SERIAL LINE MULTIPLEXER DC08A INSTALLATION 2.2 The DC08A, the required power supply, and the associated line interface units are mounted in a standard DEC Type CAB-8/I-A Cabinet. 2.2.1 Cabinet location must be no further than 6 ft from the PDP-8/1. Module Location Module Utilization drawing DC08-A-6 (Sheets 1 and 2) shows the rack location of the DC08A modules. total The number of M901 Cable Connector modules and M750 Line I/O Control modules depends on the number of communication lines in service. 2.2.2 Power Requirements Power is supplied by H7I0 Power Supplies mounted on the rear cabinet door. +5V 1.5A(1H710) Power required on a per line basis is 60 mA/line. 1 Thus, the number of H710 Power Supplies required is: H710for up to 48 lines 2H7I0sfor49 to 128 lines 2.2.3 Interface Cabling For interface cabling to the DL8I, refer to Paragraph 2.1.4. listed in Table 2-2. All cables are Type W0 11 2-2 The standard interface cabling to the PDP-8/1 is Table 2-2 DC08A to PDP-8/I Interface Cabling Location in DC08A BAC Cables (WO 11) Al BAC (0-8) BAC (9-11), BIOP(l-4), ^ BTS3, BTS1, B INITIALIZE J Bl BMB (0-5) A3 BMB(6-11) B3 AC BUS (0-8) ^ AC BUS (9-11), SKIP J INT-RQST BUS, AC CLEAR A5 "^ B5 RUN (0), BTTINST, LINEMUX (0)J Two additional W01 1-Type cables are required for transfer of signals MEM to MEM 11. listed in Table 2-3. Pin locations are The transmit module is G020 or G021 in the PDP-8/I, and the receive module is M751 in the DC08A. Table 2-3 Memory Signal Transfer Cable Pin Locations Pins Signals Pins Signals D2 MEM P MEMO MEM MEM 2 MEM 3 MEM 4 MEM 5 MEM 6 MEM 7 D2 MEM 8 MEM 9 MEM 10 MEM 11 E2 H2 K2 M2 P2 S2 T2 V2 E2 H2 1 K2 The interface between DC08A and any of the options (DC08B, DC08C, DC08F) consists of two signals for each communication channel - DLInn (data input from line nn) and DLOnn (data output to line nn). The transmit module for DLOnn and the receive module for DLInn is an M750. The signals are shown in Table 2-4. 2-3 Table 2-4 Transmit and Receive Signal Pin Designations Signal Pins Signal Pins DLIO CI DLI4 Ml DLOO Dl DL04 Nl DLI1 El DLI5 PI DLOl Fl DL05 Rl DLI2 HI DLI6 SI DL02 Jl DL06 Tl DLI3 Kl DLI7 Ul DL03 LI DL07 VI Location A29 Connectors Used: M901 Lines: DLI8 and DL08 to DLI15 and DL015 on same pins, but side 2. Lines Location Lines Location 0-15 A29 64-79 B29 16-31 A30 80-95 B30 32-47 A31 96-111 B31 48-63 A32 112-127 B32 The DC08B local terminal connector is interfaced to DC08A for 48 lines via three cables with M901 connectors. Each cable carries 32 signals (DLI and DLO for each line) and serves 16 lines. Cables First DC08B becond LK-08B Third DC08B DC08B DC08A A09 A29 A20 A30 A31 A31 A09 A32 A20 B29 A31 B30 A09 B31 A20 B32 A31 — 2-4 The cables are: The polarity definitions for data signal transfer between the line interface units and the M750 modules in the DC08A are: Mark = Low = Ground = OV Space = High = +3V For these polarities the M750 modules must be jumpered as follows: Output: E2 to U2 and R2 to T2 Filtered input: M2 to D2, Al to Jl, HI to CI, N2 to VI, Ul to Kl and L2 to El Direct Input: M2 to Jl, HI to CI , N2 to Kl and L2 to El 2-5 CHAPTER 3 OPERATION Operating procedures for the DC08 Data Communications System requires the addition of character assembly subroutines in the PDP-8/I repertoire. the system configuration. Either 8-bit or 5-bit subroutines (or both) can be used, depending on Both subroutines listed below can be obtained from the Program Library, Digital Equipment Corporation, Maynard, Massachusetts. Appendix A DEC-8I-F8VA-D, DC08 8-Bit Character Assembly Subroutine Appendix B DEC-8I-F5VA-D, DC08 5-Bit Character Assembly Subroutine 3-1 CHAPTER 4 THEORY OF OPERATION 4.1 GENERAL Theory of operation for the DC08 Data Communications System is divided into three parts: a. functional description of the DC08, with flow diagrams to illustrate the method of data transfer during TTO, TTINCR, and TTI instructions. b. detailed description of the DL8I logic, with reference to both simplified logic and flow diagrams. c. detailed description of the DC08A logic, with reference to both simplified logic and flow diagrams. Reference is also made to the DL8I and DC08A logic schematics. Continue to refer to the flow diagram, Figure 4-1 , as each function is described. 4.2 FUNCTIONAL DESCRIPTION The DC08 adds two major cycles to the PDP-8/I, STATUS (S) and CHARACTER (C), as well as a modified FETCH (F) cycle, each of which is described in appropriate sequence. Each cycle is subdivided into time states. The hardware implementation of each cycle is described in subsequent paragraphs. 4.2. 1 Fetch Cycle (F) (see Figure 4-1) The F cycle is common to all TTINCR, TTI and TTO instructions (6401 , 6402, and 6404). instruction decoding takes place, and the TTO or TTINCR instructions are performed. During this cycle, Portions of the TTI in- struction are performed during the S and C cycles that follow. 4.2.1.1 Time State 1 (F-TS 1) - During F-TS 1 , the content of the memory address register (MA) is incremented and transferred into the program counter register (PC). control of the DL8I. This is part of a conventional F cycle and is not under Instruction decoding has not yet taken place. 4-1 FETCH (F) CYCLE t (TT I/TTO) MA+! fPC MEM *MB MEM MR F-TS2 F-TS3 MB 9 (0) MB9(I) AC SHFT RIGHT MB 11(1) + MB 1(0) "-LSR 1 F-TS4 MB 10 (I) MB 10 (0) I PC »MA BRK REQ BRK REQ DATA PC ADO I CYCLE 3 CYCLE. JMS HR L Finnrp 4-1 Dl 8T Flr»w Dinnrnm ^lioot 1^ *MA STATUS (S) CYCLE (TTI ONLY) S-TS-I MA+I +PC »LSR S-TS-2A MEM—LSR 50 n« *HS 350ns S-TS-2B LH S-TS-2C ,MEMO (0) + HS (I) MEMO(l)HS(0) MEM(HI)-*MB(1-11) LINE 1MEM9C0) MEM9(I)J MBO MEM (0-8)-» MB (0-8) MEM+I—"-MB 0—•MBO-II) S-TS-3 MB (9-11) =2 MB (9-10*2 +2 +PC S-TS-4 BRK REQ PC *MA DATA add" I CYCLE BRK REQ PROGRAM ,DATA MB MA 3 CYCLE JMS I Figure 4-1 MR »WC DL8I Flow Diagram (Sheet 2) 4-3 PC »>MA C-TS CHARACTER (C) CYCLE 1 #{TTI ONLY) *PC MA+1 " C-TS 2 u HS(0) CD MEM »MB LINE "-MBO HS(I)| MEM HUB w C-TS 3 MB 11(0) MB 11(0) R:0 1 R*0 (STORE) r " i HS(0) HS(I) CO MEM »AC LINE »>AC0 MEM *AC 1 < * ' J C-TS 4 BRK REO BRK REO PROGR,AM± 10ATA DATA »MA add" I CYCLE i MA A 3 CYCLE L i JMS I PC »-MB I Finitro A-1 HR WC »E I DIPT Plnuf HT««r.«rv% KU««I- *3\ *»—* »-F Table 4-1 PDP-8/I - DL8I - DC08A Interface Signal Reference Table Signal Name Origin (mnemonic) Dwg Desti- Origin Dwg. Location nation No. & on Dwg No. & (Sheet) (Sheet) Dest. Location on Dwg B LINE HOLD DL8I DC08A DL8I-0-2 CI DC08-A-2(2) C3 BC(0) DL8I DC08A DL8I-0-2 CI DC08-A-2(2) B3 B STLR DL8I DC08A DL8I-0-2 B1 DC08-A-2(2) B3 BTP3 DL8I DC08A DL8I-0-2 C8 DC08-A-2(2) B3 DL8I DC08A DL8I-0-2 B8 DC08-A-2(2) B3 B DC INST DL8I DC08A DL8I-0-2 B8 DC08-A-2(2) B3 IFTSO) DC08A DL8I DC08-A-2(2) B3 DL8I-0-2 B8 BR=Q DC08A DL8I DC08-A-2(2) B3 DL8I-0-2 B8 AC00-AC11 BUS DC08A PDP-8/I DC08-A-2(2) B,C,D6 81-0-10 B1-B8 I/O SKIP DC08A PDP-8/I DC08-A-2(2) B6 81-0-10 B3 INT RQST DC08A PDP-8/I DC08-A-2(2) B6 81-0-10 B3 AC CLEAR BUS DC08A PDP-8/I DC08-A-2(2) B6 81-0-10 B2 B RUN(O) DC08A PDP-8/I DC08-A-2(2) B6 81-0-10 C2 LINE MUX(O) DC08A PDP-8/I DC08-A-2(2) A6 81-0-10 Bl DATA IN 0-127 DC08A PDP-8/I DC08-A-1 Total 81-0-10 B3-B8 BTTINST PDP-8/I DC08A 81-0-10 CI DC08-A-2(2) B6 DATA OUT 0-127 PDP-8/I DC08A 81-0-10 B3-B8 DCQ8-A-1(I,2) Totai B AC00-BAC11 PDP-8/I DC08A 81-0-10 D3-D8 DC08-A-2(1) B,C,D7 BMB00-BMB11 PDP-8/I DC08A 81-0-10 C1-C8 DC08-A-2(1) A,B,C,D4 MEM00-MEM07 & P PDP-8/I DC08A 81-0-14 C4-C8 DC08-A-2(2) C,D5 MEM08-MEM11 PDP-8/I DC08A 81-0-14 C1-C3 DC08-A-2(2) D3 BIOP 1,2,4 PDP-8/I DC08A 81-0-10 D2,D3 DC08-A-2(1) B7 BTS3 PDP-8/I DC08A 81-0-10 D2 DC08-A-2(1) B7 BTS1 PDP-8/I DC08A 81-0-10 Dl DC08-A-2(1) A7 B INITIALIZE PDP-8/I DC08A 81-0-10 Dl DC08-A-2(1) A7 MEM - LSR PDP-8/I DL8I 81-0-2(2) C5 DL8I-0-2 B8 LH -HS PDP-8/I DL8I 81-0-2(2) C4 DL8I-0-2 CI LINE(O) PDP-8/I DL8I 81-0-10 CI DL8I-0-2 C2 MEM DONE PDP-8/I DL8I 81-0-13 Dl DL8I-0-2 Bl MEMO PDP-8/I DL8I 81-0-14 C7 DL8I-0-2 B5 B MEM - LSR (1,2) 4-5 Table 4-1 (Cont) PDP-8/1 - DL8I - DC08A Interface Signal Reference Table Signal Name (mnemonic) Origin Dwg. No. & (Sheet) Location nation Desti- Origin on Dwg Dest. Dwg Location No. & (Sheet) on Dwg S(l) DL8I PDP-8/1 D LSI -0-2 D7 81-0-2 81-0-13 C6 D3 S(0) DL8I PDP-8/1 DL8I-0-2 D8 81-0-2 C6 81-0-13 D3 TT SET DL8I PDP-8/1 DL8I-0-2 D6 81-0-3 B2 TTSET DL8I PDP-8/1 DL8I-0-2 D6 81-0-4 A7 TT CARRY INSERT DL8I PDP-8/1 DL8I-0-2 B7 81-0-4 B7 TT CARRY INSERT DL8I PDP-8/1 DL8I-0-2 B7 81-0-5 B3 TT CARRY INSERT DL8I PDP-8/1 DL8I-0-2 B7 81-0-5 D3 STORE DL8I PDP-8/1 DL8I-0-2 B2 81-0-4 D7 TT I/O ENABLE DL8I PDP-8/1 DL8I-0-2 B2 81-0-4 B6 TT CARRY INSERT DL8I PDP-8/1 DL8I-0-2 B3 81-0-6 C5 MEM INH 9-11 DL8I PDP-8/1 DL8I-0-2 C4 81-0-4 C6 TT L DISABLE DL8I PDP-8/1 DL8I-0-2 D3 81-0-4 A3 C NO SHIFT DL8I PDP-8/1 DL8I-0-2 A4 81-0-5 D3 TT SHIFT ENABLE DL8I PDP-8/1 DL8I-0-2 B6 81-0-5 C2 TT SHIFT ENABLE DL8I PDP-8/1 DL8I-0-2 B6 81-0-8 A8 TT INCREMENT DL8I PDP-8/1 DL8I-0-2 D5 81-0-5 A7 TT RIGHT SHIFT ENABLE DL8I PDP-8/1 DL8I-0-2 D5 81-0-5 D5 TT CYCLE DL8I PDP-8/1 DL8I-0-2 D3 81-0-5 A5 TT AC LOAD DL8I PDP-8/1 DL8I-0-2 C2 81-0-6 D7 TT INST DL8I PDP-8/1 DL8I-0-2 D4 81-0-2(1) B3 TT INST DL8I PDP-8/1 DL8I-0-2 D4 81-0-8 A8,C8 TT INST DL8! pnp_8/T D LSI -0-2 D4 \j i QT_n_in — \j — wj Dl U TT DATA DL8I PDP-8/1 DL8I-0-2 D2 81-0-8 A8 TT LINE SHIFT DL8I PDP-8/1 DL8I-0-2 C5 81-0-9(1-4) C8 TT rAPPV TMCPDT C ni qt on d A l/ r —\j/ x r»i ot n \J \-yji.—\j—£. B-7 <»¥ 1 4-0 D/ r\ n/JV oi-u-y^; 1 k 1- Time State 2 (F-TS 2) - During F-TS 2, the content of the selected memory location is transferred into 4.2. 1 .2 MB bits 0,1, and 2 are then transferred into the instruction register (IR). memory buffer (MB) register. F-TS 1, this is part of a conventional F cycle and is not under control of the DL8I. As in Instruction decoding has not yet taken place. Time State 3 (F-TS 3) (see Figure 4-2) - During TS 3, the contents of the instruction register are de- 4.2. 1 .3 coded. An octal 6 in the instruction register indicates an IOT instruction. instruction. This is normally a 4.25 ps slow-cycle However, when the DL8I decodes on octal 4 in MB 3 through MB 5 and an octal MB 8, it inhibits the SLOW CYCLE signal, and disables the conventional IOT timing train. in MB 6 through At this point, the DL8I controls the PDP-8/I. NOTE The above sequence is not shown in Figure 4-1 because it takes place almost entirely under PDP-8/1 control, not DL8I conlrol. If the above conditions did not exist, i.e. 640X in MB (X can be to 7), this F cycle would be changed to a conventional IOT F cycle. Therefore, all succeeding discussion presumes that 640X, or TT instruction, is in MB. INDICATES TT INSTRUCTION r A OPERATION CODE 6 INDICATES IOT INSTRUCTION I INDICATES TTO-GENERATES I0P4 I INDICATES TTI-GENERATES I0P2 I INDICATES TTINCR-GENERATES > DEVICE SELECTION f 4 6 A. I tf A. sr f "\ r A Format of TT Instruction Words in MB During F-TS 3, the contents of MB 9 and MB 11 are decoded. ACO. into the link (L), If I0PI 1 1 Figure 4-2 is set r > If MB 9 is a 1 , indicating a TTO instruction, a and the content of the accumulator (AC) is shifted once to the right with shifted into MB 9 is a 0, indicating either a TTI or TTINCR instruction, the above sequence is bypassed. One bit of line data is shifted out of AC1 1 during a TTO instruction. MB 11 is decoded. If If MB 11 is a 1, indicating a TTINCR instruction, the line status register (LSR) is incremented MB 11 is a 0, indicating either a TTI or a TTO without microprogrammed TTINCR instruction, the LSR incre- mentation sequence is bypassed. 4-7 4.2. 1 .4 Time State 4 (F-TS 4) - During F-TS A, MB 10 is decoded. If MB 10 is a 1 , indicating a TTI instruction, the content of the PC register is shifted into MA, and the S flip-flop is set, thereby enabling the S cycle at the end of F-TS 4, for TP4. If MB 10 is a 0, indicating a TTI or a TTINCR instruction (or both microprogrammed), and if there is no break request, the contents of the PC register are transferred into MA, and the F flip-flop is again set: this enables another F cycle at the following TS 1 If a . break is called for, the PDP-8/I determines the type of break and processes it accordingly. 4.2.2 Status Cycle (S) (see Figures 4-1 and 4-3) The S cycle is the second phase of a TTI instruction. It ory location immediately following the TTI instruction. for input is started. utilizes the line status word (LSW) located in the mem- During the S cycle, the servicing of a particular line The line number is indicated by bits 2 through 8 of the LSW (see Figure 4-3). Bit indi- cates the status by association of the selected line, and bits 9 through 11 are used as a real-time clock to count the number of samples up to 2 (0 — 1 sampled and the character is assembled. 2) before entering the CHARACTER (C) cycle, when the data bit is If the count does not equal LINE ACTIVITY BIT 2, the next F cycle is entered. The clock REAL-TIME NOT USED 1 CLOCK SITS (LINE SAMPLING COUNTER) LINE NUMBER 2 3 A 5 6 7 1 Figure 4-3 " 9 10 1! 1 Format of Line Status Word (LSW) Time State 1 (S-TS 1) - During S-TS 1 , the content of MA is incremented and transferred into the 4.2.2. 1 PC register. The LSR is then cleared to allow insertion of the new LSW. 4.2.2.2 first Time State 2 (S-TS 2) - S-TS 2 is subdivided into three substates, S-TS 2A, 2B and 2C. substare (S-TS 2A), the appropriate bits of the pulse. During the LSW are transferred into the LSR in the DC08A by MEM -LSR During S-TS 2B the status of the line hold (LH) flip-flop, associated with the selected line, is transferred into the hold sync (HS) flip-flop (LH - HS). When the HS flip-flop is set, the character assembly word (CAW) contains a complete character which has not yet been processed because the program allows only a certain number of characters to be processed on each service cycle (see Paragraph 4.4.5.2). During substate S-TS 2C, bit of the LSW is decoded with the HS flip-flop as follows: a. MEM (0) + HS (1) of the LSW equals zero (indicating that the line was not active during the last service cycle) or the HS flip-flop is set (indicating a completed but as yet unstored character in the CAW), then bits 1 If bit through 1 1 of the LSW are transferred into bits signal on the input line is transferred into bit 1 through of the 11 of the MB (a start bit is a zero; therefore, its complement is a one. MB register. The complement of the sets the activity bit). All of the above is A conventional done to indicate a newly ac- tive line and also to bypass the real-time clock after a character has been assembled but not stored. b. MEM (1) • HS (0) of the LSW equals one (indicating that the line was active during at least the last service cycle) and the HS flip-flop is reset (indicating that there is neither a completed character nor a stored completed character yet in the CAW), then the following takes place: if bit 9 of the LSW equals zero, indicating If bit that the real-time clock has not yet reached a count of 4, the content of the LSW is incremented and transferred into the MB register. This, in effect, is adding one to the value of the real-time clock. If, however, bit 9 of the LSW equals one, indicating the real-time clock has reached a count of 5, then through 8 of the MB register, and a zero is transthrough 8 of the LSW are transferred into bits bits ferred into bits 9, 10, and 11 of the MB register, resetting the real-time clock to zero. Time State 3 (S-TS 3) - During S-TS 3, the value of bits 9 through 1 1 of MB are examined. 4.2.2.3 value is equal to 2, indicating the time is correct to sample the line, S-TS 4 is entered. CHARACTER (C) cycle. and TS 4 is entered. If, If this This leads to the however, the value is not equal to 2, the program counter is incremented twice, The program counter is incremented twice to skip the next two instructions (i.e. , skip the C cycle and the following instruction). Time State 4 (S-TS 4) 4.2.2.4 MB (9-11) = 2 a. When TS 4 is entered along this route, the content of the PC register is transferred to the MA register. Then, the CHARACTER (C) flip-flop is set, enabling the C cycle during the next TS 1. MB (9-11) 5^2 b. When S-TS 4 is entered along this route, the PDP-8/I Computer checks for data breaks. is no break request, the count of the PC register is transferred into the is set, thereby enabling another F cycle at the following TS 1 . If a If there MA register, and the F flip-flop break is called for, the PDP-8/I program determines the type of break and processes it accordingly. 4.2.3 Character Cycle (see Figure 4-1) The C cycle is the last cycle of the TTI instruction. Associated with the C cycle is a character assembly word (CAW). The software initializes one of the leftmost bit positions of the CAW (the actual position depends on character length). is complete. Received line data bits are shifted in from the left, one bit at a time, until the character Completion is determined by the appearance of the initialization bit at position 1 1 of the CAW. Between C cycles, the CAW is returned to memory for storage. 4-9 Time State 1 (C-TS I) - During C-TS 1, the content of the MA register is incremented and transferred 4.2.3.1 PC register. into the 4.2.3.2 Time State 2 (C-TS 2) - During C-TS 2, the status of the Mne HS fiip-fiop is examined. indicating that the CAW does not contain a character completed during the last pass, the CAW is If HS = 0, shifted one place to the right and transferred to the MB register, and the content of the incoming line is strobed into bit of the MB. If the HS = 1, indicating the selected CAW contains a fully assembled but unstored character, C-TS 3 is entered. 4.2.3.3 Time State 3 (C-TS 3) - During C-TS 3, decisions are made about processing of the completed CAW. MB11 = a. If the MB register bit 11 is a 0, the PC register is incremented, resulting in the program skipping the following instruction (usually JMS which leads to the store subroutine). MB 11 (0) implies that the character in the MB 11 = b. If CAW is not yet complete. 1 MB register bit 11 is a 1, a completed CAW is being processed and is either in the MB register or the memory sense buffer (if it has been completed and not processed, or if it has been completed during C-TS 2). The state of the line HS flip-flop indicates which of these conditions exists. A second decision is made by examining the count in the R register. R = c. This indicates that the program does not have enough time left during the current service cycle to process the completed character; as a result, the LH flip-flop associated with the particular line is set to 1, the PC register is incremented to skip the succeeding JMS (go to store subroutine) instruction, and C-TS 4 is entered. R/0 d. This indicates that the completed characters can be processed (i.e. , the program has enough time to go to through the character storage subroutine) One final decision remains; if the character was completed during the previous service cycle (indicated by HS = 1), the CAW is transferred to the accumulator, and the line hold flip-flop is reset. acter was completed during the present C-TS 2 (indicated by HS = 0), the CAW is If, however, the char- shifted right and transferred to the accumulator, and the LH flip-flop is reset. The right-shift, in the one case, and the direct transfer, in the other case, ensure that both characters have the same right justification. is When this action is complete, C-TS 4 entered. 4.2.3.4 Time State 4 (C-TS 4) - When C-TS 4 is entered, the PDP-8/1 first checks for data breaks. If there is no break request, the count of the PC register is transferred into the MA register, and the F flip-flop is set, thereby enabling another F cycle at the following TS 1 . If a of break and processes it accordingly. 4-10 break is necessary, the PDP-8/1 decides the type 4.3 DL8I DETAILED LOGIC DESCRIPTION General 4.3.1 Detailed description of the DL8I logic is limited to the development of the control signals required by the flow diagram (refer to Paragraph 4.2). Only those areas of the flow diagram relating to DC08 operation are described. Subdivision is according to major cycles and time states within major cycles. Identification of logic elements is accomplished by using the module location code followed by the output pin number. reference to both simplified logic diagrams and logic schematic DL8I-0-2. This scheme allows common For instance, signal TTL DISABLE is generated by gate D09-S2, shown on the simplified logic diagram (see Figure 4-4) and on logic schematic DL8I-0-2 at coordinates D3. ule in location D09. D09 is the specific module rack location; S2 is the specific pin number of the mod- Continue to refer to the DL8I flow diagram, Figure 4-1 , as each function is described. Fetch (F) Cycle 4.3.2 Time states F-TS 1 and F-TS 2 are functions relating to the PDP-8/I program only. The DL8I is affected starting with F-TS 3. Time State F-TS 3 - (see Figures 4-4 and D-BS-DL8I-0-2) 4.3.2. 1 a. 640X Decoding During TS 3, three special TT instructions, TTI (6402), TTO (6404), and TTINCR (6401), are decoded. Signal IOT is a decoded octal 6 in MB 0, MB 1 , and MB 2 on D-BS-8I-0-3. TT INST is used to disab le the normal IOT timing chain and inhibit a slow cycle, as shov/n on D-BS-8I-0-2 (Sheet I). causes the LINE -MB b. TT INST also transfer. Link Disable Gate D09-S2 generates TTL DISABLE which in turn disables the link by inhibiting signal L ENABLE (D-BS-8I-0-4). During all three time states, gate D09-S2 is enabled as follows: (1) During the F cycle, TT INST is low, thereby enabling the gate. (2) During the S cycle, the S flip-flop is set; therefore, S (0) is low, enabling the gate. (3) During the C cycle, the C flip-flop is set; therefore, C (0) is low, enabling the gate. NOTE- AM subsequent DC08 discussion assumes that the link is disabled by TT INST. c. MB 9 Decoding MB 9 is decoded by gate Cll-Nl which is enabled only when MB 9 (1) is high at F-TS 3, thereby generating TT I/O ENABLE, which causes I/O ENABLE (D-BS-8I-0-4) and then AC ENABLE to allow AC loading or right shift. 4-11 D09 P— DC INST INDICATES TO 0C08A A CONVENTIONAL (64XX) (D-BS- 81-0-2,8,10) MB0G«9 ^ ]^P°r; TT INST 1 BMBII(I) TP3_DLYD ! L ' ^ - — hs^TT RIGHT SHIFT EN ABLE (D-BS-81-0-5) DH> ~i TT INC R (6401) (D-BS-DC08-A0- 4 ' 2i d"ss DcosTaii; C :,,,...,?, A^A iyui* -T--T C: I:f:-J --iiiifjiii icu I :-. i.vjyi<- 4-12 r\; r ri..i.. l/iuQiuiii, r Jiure, -rr »> ijo d. Right Shift set the TT I/O ENABLE (used only for a TTO instruction) and TT RIGHT SHIFT ENABLE (D-BS-8I-0-5) shift. The shift occurs at TP 3 right internal accumulator an for network gating register PDP-8/I major when gate D09-V1 generates TTAC LOAD. In the case of a TTO instruction, the F flip-flop for the the case of TTINCR, selected line (D-BS-DC08-A-1) is loaded with data at the beginning of F-TS 3. In TTO and TTINCR the incrementing of LSR occurs at TP 3 delayed (150 ns). Thus, for microprogrammed (6405), TTI occurs before TTINCR. e. MB 11 Decoding decoded by a gate in the DC08A to produce TTINCR 150 ns after TP 3; TTINCR increments the LSR by one count to select the next successive line. MB 11 = 1 is Time State F-TS 4 (see Figure 4-5) 4.3.2.2 a. TTINCR, TTI, TTO Decoding MB 10 is decoded by gate D 10- El which is enabled by MB 10 = 1 and TTI N ST. The output at gate D10-E1 is S SET, which sets the status (S) flip-flop at TP4. b. TTSET The S~SET output is inverted to become TT SET. return to the F Cycle (D-BS-8I-0-3). c. TT SET causes PC - MA transfer and disables normal The status (S) cycle is entered next. TT INST MBIO(I) CI DtO 1 S SET El S TP4 WHEN SCI THE STATUS (S) CYCLE IS ENTERED. (ALSO SEE DWG D-BS-8I-0-2) 01 TT SET CSET C11 CI (D-BS-81-03) (SEE FIG 4-10) (SEE ALSO DWG D-BS-DL8I-0-2) Figure 4-5 4.3.3 Simplified Logic Diagram, F-TS 4 Status (S) Cycle During the S cycle, the line status word (LSW) is examined to determine if a character cycle is to 4.3.3.1 Time State S-TS 1 (see Figure 4-6) NOTE Time state S-TS 1 is applicable to the character cycle. Thus, the functions of Figure 4-6 apply to both S-TS 1 and C-TS 1 (except for STLR). 4-13 be entered. a. TTL DISABLE Gate D-09-S2 is activated by S = b. to produce TTL DISABLE. TT CYCLE TTL DISABLE activates gate C10-N1 to generate TT CYCLE. This signal increments the generating PC INCREMENT at TS1 (D-BS-8I-0-3) and, at TP 1, causes - PC transfer. MA register by MA c. STLR MEM STLR is generated by S = 1 after DONE ends to clear the line status register (LSR). prevents a premature STLR pulse at the end of a memory cycle (D-BS-DL8I-0-2). MEM DONE TT INST S(0) C(Q) _-. nna "H 009 X TTL DISABLE y^jf c C10 TT INST (D-BS-8I-04) TCYCL E JD (D-BS-8I-0-5) ^ SO) STLR .. MEMJJONE I Figure 4-6 4.3.3.2 a. , (D-BS-DC08-A-2) , J S2 (ALSQ SE£ ^ ^.^. Q . Z) Simplified Logic Diagram, S and C States, S-TS 1 and C-TS 1 Time State S-TS 2 - S-TS 2 is subdivided into three substates called S-TS 2A, 2B, and 2C. S-TS 2A (see Figure 4-7) MEM - LS R - Signal S = MEM LSR transfer pulse. 1 at TP 1 activates gates in the PDP-8/1 (D-BS-8I-0-13) to generate the The contents of MEM 2 through MEM 8 (the LSW) are strobed through the input gating circuits to the line selection register (LSR) in the DC08A. b. S-TS 2B (see Figure 4-7) LH - HS - The state of the line hold (LH) flip-flop of the selected line is transferred to the hold status (HS) flip-flop in the DL8I approximately 400 ns after the status transfer. The output of HS is used to initiate decoding of the c. LSW. S-TS 2C (see Figure 4-8) TT LINE SHIFT - This signal is generated in gate C11-M2 by the presence of MEMO = or The signal causes the MEM 1-11 -MB 1-11 transfer in the PDP-8/1 (D-BS-8I-0-9) and gates the line value into MB (LINE - MB 0). This is the new data bit from the selected line. TT LINE SHIFT completes one path through S-TS 2. When activity is established, MEM = 1 and (1) HS= 1. no further line shift is made in successive passes. MEM INH 9-1 1 - the alternative path through time state S-TS 2C occurs for the term HS (0) from inverter C09-F1 Gates C09-K2 and D10-L1 detect the value of MEM 9. If MEM 9 is active, gat e D09-N1 and nverter C09-N1 produce an output that satisfies gate C09-K2. The resulting MEM INH 9-1 1 output of C09-K2 allows transfer of only MEM 1-8 and (2) MEMO (1) • . i sets all zeroes in MB 9-11 (D-BS-8I-0-4). MB 9-11 is the real-time clock which, in this case, is 4-14 TP1 FROM ~ DL8I LH-»HS SO) (CII-FI) 6 D-BS- 81-0-2 MEM-»LSR H>i D-BS-DUBI-O-2 Figure 4-7 Simplified Logic Diagram S-TS 2A and 2B 4-15 J ME MOO) (IFMEM9»0) b TT INCR EM ENTD-BS-SI-0-5) 0)0 L1 K C 09 1 K2 MEM 1NH 9-11 ( ( " iF MEM9«0) (0-BS-8I-0-4) MEMO(O) + HSO) SO) TT LINE SHIFT (D-BS-8I-0-9) C11 M2 TS2(1) LINE(O) ^ (D-BS-8I-0-8) TT SHIFT ENABLE TTLINE (D-BS-8r-0-8) SHIFT TT RIGHT SHIFT ENABLE, „„.^ |CO£Xj C09 TT SHIFT ENABLE (D-BS-8I-0-5) F2 hlou i/»fc U-05-ULBI-0-2J Figure 4-8 4.3.3.3 Simplified Logic Diagram, S State, IS 2C Time State S-TS 3 (see Figure 4-9) - Time state S-TS 3 is used to examine the count of the real-time clock to determine if the character (C) cycle is to be entered. a. C SET Gate D TO -J 2 generates C SET when MB 10 = 1 and MB 11 = equals two). should be sampled. b. are coincident (real -time-clock count C SET indicates that the clock count of the LSW is to the count at which the line data This allows an immediate passage to time state S-TS 4. TT CARRY INSERT S If the real-time clock count does not equal two, gate C11-S2 is enabled, and the TT CARRY INSERT S signals are generated as shown. These signals cause the PC to be incremented by two counts (D-BS-8I-0-9, Sheet 4), and the next two instructions are skipped. 4.3.3.4 Time State S-TS 4 (see Figure 4-10) - During time state S-TS 4, the signals are generated to enable entry into the character (C) cycle or return to the next fetch (F) cycle. a. TTSET The C SET output of gate D10-J2 also activates gate CI 1-D1 and enables the input to the C flip-flop. Gate C 1 1 -D 1 and inverter C10-C1 develop TT SET in the same manner as described in Paragraph 4. 3. 2. 2. b, TT SET disables normal return to the fetch cycle. At TP 4, the C flip-flop is set and the character cycle is entered b. If C SET does not occur during S-TS 3, TT SET and its results are inhibited. entered in MA (PC -"MA), zrd the next fetch (F) cycle 4-16 Is entered. The PC + 2 count is S(l) MB 10(1) D10 P ° SET MBII(O) > C SET (MB9-11 = 2); SET C FLIP-FLOP J2 (F1G.4-I0) TT CARRY INSERT S [(MB9-II/2)] C SET TT CARRY INSERT S (D-BS-8r-0-9) 12 S(l) S2 TS3(I) TT CARRY INSERT S (MB 9-11 # 2)j TT CARRY INSERT C TT CARRY INSERT -(D-BS-8I-0-4) DO 9 N1 Figure 4-9 ^°¥ (D-BS-8I-0-5) Simplified Logic Diagram, (S-TS 3) TT SET 7T~^n? C11 jy^\ V A> > 1 WHEN FLIP FLOP C IS SUCH T C11 C(D— THATC(1)*1 THE CHARACTER CYCLE IS INITIATED TP4- Figure 4-10 4.3.4 C Simplified Logic Diagram, S State TS 4 (S-TS 4) Character (C) Cycle Time state C-TS 1 is the same as described for S-TS 1, Paragraph 4.3.3, except that STLR is not generated for the C cycle. Time State C-TS 2 (see Figure 4-1 1 and Drawing D-BS-8I-0-5) 4.3.4. 1 a. HS = Decoding HS = (HS flip-flop cleared) during C-TS 2, gates CI 1-J1, CI 1-H2 and C09-F2 combine to generate MEM register and effect a MEM - MB transfer. This action drops position. Inverter C10-V2 and gates C10-S2 and C10-N2 load the line data bit 11 and vacates the bit If the signals required to right-shift the bit into b. If MB 0. Thus, MB contains the incoming character data including the most recent data bit. HS = 1 Decoding HS = 1 (HS flip-flop is set) during C-TS 2, the right-shift of MEM is inhibited, and a simple MEM - MB transfer is done. 4-17 TT LINE SHIFT C09 >— TT SHIFT ENABLE (D-BS-8I-0-8) F2 cm— HS(O) TS2(1) C11 — -3 C11 J!. -TT RIGHT SHIFT ENABLE (DBS-8I-0-5) cio>o > TT I/O ENABLE C SR ENABLE LINE(O) -d C10 ) CIO (D-BS-Sr-O-IO) S2 C(D— J >— y™ TT DATA (D-BS- 81-0-8) CIO 4 (SEE ALSO D-BS-0L8I-0-2) 08-0045 Figure 4-11 Simplified Logic Diagram, C State, TS 2 (C-TS 2) Time State C-TS 3 (see Figure 4-12) - During C-TS 3, the CAW is examined to determine if a complete 4.3.4.2 character is contained in the MB register. If a complete character is present, the R register is checked to deter- mine if the character can be processed. MB11 = a. If character assembly is incomplete (MB 11 =0), gates D09-H2 and D09-N1 are activated, and the TT CARRY INSERT signals are generated. This results in incrementation of the PC (+1 * PC) and advancement to time state C-TS 4 (D-BS-8I-0-4,5,6). MB 11=1 b. assembly is complete, MB 11=1 enables gates D10-S1 and D10-V2, one of which is acti- If character vated depending on the state of the R register as follows: R = (1) generates LINE HOLD, which sets the LH flip-flop for the particular line in the DC08A, and processing must wait. In this case, the PC is incremented and C-TS 3 is ended. STORE generates TT AC LOAD (D-BS-DL8I-0-2) and MEM ENABLE TT AC LOAD causes MEM - AC transfer (D-BS-8I-0-6). The condition of flipflop HS deter mine s if a right-sh ift of MEM is do ne prior to the transfer. STORE also generates C NO SHIFT and C SR ENABLE C N O SHIFT causes N O SHIFT signal for straight MEM -AC (D-BS-8I-0-5). C SR ENABLE causes TT SHIFT ENABLE which inhibits NO SHIFT to allow a right shift in MEM and also allows the transfer of line status to MB 0. R 4 (2) generates STORE. (D-BS-8I-0-4). . 4.3.4.3 Time State C-TS 4 - Time state C-TS 4 is the same as time state S-TS 4, Paragraph 4.3.3.4, except that the next fetch (F) cvcle is alwavs enabled. 4.4 4.4.1 DC08A DETAILED LOGIC DESCRIPTION General Logic description of the DC08A Serial Line Multiplexer consists of a brief examination of the DC08A block dia- gram, followed by a description of the four groups of DC08A circuits. miry*l oi:l IW H"»<"it iliwt tnoro M^i *r Je *** '*>* # riiwr«ve W 17\mY ** nno • I ± i * »^ fr\r*tm\ wVltll Vi rlrniit vis »w)l l!r»<» i il During the descriptive paragraphs, keep in ll// KA/H(l\ ff\r anon rlnt« lina m*ir\ uet^s ?« Wus m* frr» W n trtfril Vimi r\( I OH W tnA'xi'Aitril iuvii f WWW \ / ™ «Tn Vsr^f i " ; such circuits (or 64 M750 modules). 4-18 <ac- a i b *wr : : - i-a* s <wb i >rf » ! t «5b l I TT CARRY INSERT{D-BS-8I-0-6) MB1H0) C(1) D09 TS3(1) TT CARRY INSERT C H2 LINE HOLD TT LINE SHIFT CO 9 -^H^ TT CARRY INSERT^"?!"? J"°"5| (D-BS-8I-0-5) _£\-JT SHIFT ENABLE(D-BS-8I-0-5) TT SHIFT ENABLE F2 TT RIGHT SHIFT ENABLE MB1K1) R*0 B LINE HOLD (D-BS- DC08- A-2) 010 C(1) V2 TS3 MB1K1) R)«0 D10 C(1) \_ STORE JO-^ (D-BS-8I-0-4) TS3 HS(1) C NO SHIFT (D-BS-8I-0-5) D07 C1 (STORE), D07> C DO^ OR < >C HS(O) ENAI SR ENABLE F1 TT I/O ENABLE o STORE D09 D09 TP3 TT AC LOAD (D-BS-8I-0-6) Viz JO— J VI Figure 4-12 Simplified Logic Diagram, C State, TS 3 4-19 TT RIGHT SHIFT ENABLE (D-BS-8I-0-5) 4.4.2 Block Diagram Description (see Figure 4-13) The DC08A consists of four functional circuit groups: a. Line register and control b. Clock skip and interrupt c. Instruction decoder d. Line control (one for each line); the line control has three types of inputs and outputs: (1) Multiplexed inputs and outputs (2) Line select inputs (3) Individual data line inputs and outputs The multiplexed inputs and outputs appear at each line control, but only one line control is selected at any given time by the line register (LINE SELECT). dividual Therefore, at any given time, only one line control DATA OUT and DATA IN lines appear at the line side of each line control module. function of the DC08A is to connect the selected line to the PDP-8/1. is being used. In- Thus, the major The M751 line register and control mod- uib \v-oj-v\~\jo-n-*j/ aecoae rne rL/r-0/1 une nurrtDer outputs ana generate a liinc jclc\_i grouping or signals comprising: a. HO for lines from 0-63 HO for lines from 64 - 127. b. GROUP is broken down as follows: 0-7 and 64-71 8-15 and 72 - 79 16 -23 and 80-87 88-95 24 -31 and 32 - 39 and 96 - 103 40 -47 and 104-111 48 -55 and 112-119 56-63 and 120 - 127 c. LINE n where n varies from 0-7 These signals, called LINE SELECT, can address up to 128 lines. matrix that interprets all TT instructions for internal use. The instruction decoder consists of a decodina The clock skip and interrupt circuits provide a maxi- mum of four different clock interrupt rates (one (110-baud) is included in the basic DC08A; the other three are optional). 4.4.3 Line Control Module M750 (Figure 4-14 and D-BS-DC08-A-1) The line control circuits interface each data line to the DC08. and two on each M750 module. There is one line control circuit for each line, Because the PDP-8/1 operates several orders of magnitude faster than any of the 4-20 LINE SELECTION REGISTER (LSR) INSTRUCTIONS LINE SELECT LINE LINE X, GROUP, HO SELECT GROUP. LINE CONTROL LINE REGISTER AND CONTROL 1-»-LINE OUT' LINE(O) TO/FROM POP 8/1MULTIPLEXED INPUTS AND { OUTPUTS TO ALL LINES MEM 2THRU8(LINE NBRFORS-CYCLE) BAC5THRUII (UNE NBR FOR TTO) SEE Fig.4-16 1 3 o< - (FOR LINE 0) LINE OUT- DATA IN LINE MUX OUT- SEE Fig.4-14 FOR DETAILS MULTIPLEXED LHS(O) MEM -*» LSR LHS(I) 53 TTLL II " I BAC5THRU110) (LSR READ OUT) TO ALL OTHER LINE CONTROL CIRCUITS (LINES 1T01 27) • CINT REQ SKIP • CLOCK 8 SKIP INSTRUCTIONS CLOCK SKIP AND INTERRUPT SEE Fig. 4-1 5 FOR DETAILS DECODED INSTRUCTIONS PDP-8/I CODED INSTR. D-BS- 81-0-10 INSTRUCTION DECODER SEE Fig. 4-17 FOR DETAILS Figure 4-13 DC08A Simplified Block Diagram FOR DETAILS >i lime] r ISELECTJ LOAD F- ->- LINE ENABLE; 1 -» LINE OUT LINE ENABLE LP GROUP Q See Note 1 See Note 2 H> (DATA OUT] < LINE MUX OUT (DATA IN) -« <3 •1^ i K> OTHER LINE CONTROLS C3 \> 1-*-LH. D — — DATA OUT LINE SINGLE DATA LINE ENABLE D-l INVERTER or I J FILTER I • DIRECT I DATA IN d NOTE: 1. THERE ARE TWO LINE CONTROLS PER M750 MODULE ONLYONE IS v SHOWN. 2.THESE ARE WIRING OPTIONS 1 LH LOAD LH -D>-zD- LINE ENABLE. —«— MULTIPLEXED LHS (1) -« ^ LHS(I) , <i » LH(O) . LINE ENABLE OTHER LINE CONTROLS (See Also D-BS-DC08-A-1) <3 Figure 4-14 Line Control Logic Diagram data lines that it is coupled to, it is necessary to store output data; the F flip-flop provides short-term output data storage. Input data, however, is sampled from the line in real-time. The LH flip-flop provides short-term line history, as described in DL8I flow diagram theory. signal. LINE ENABLE Line Selection - Gates 3 and 4 combine the LINE SELECT signals to form an internal 4.4.3.1 LINE ENABLE enables the F and LH flip-flops and the data input gate. F Flip-Flop - The F flip-flop provides short-term storage of output data when set by 4.4.3.2 1 - LINE OUT The output of the F flip-flop is routed through an inverter to the data line as with LOAD F and LINE ENABLE. DATA OUT. Data Input - Input data from the data line is either inverted, filtered, or wired directly to gate 5. 4.4.3.3 When gate 5 is enabled by the LINE SELECT signals, the value of the data line, appropriately processed, appears on LINE MUX OUT and is subsequently sampled in real-time by the PDP-8/I. LH Flip-Flop - The LH flip-flop provides a short-term history of the line being serviced. 4.4.3.4 flop is set if a character has been completely assembled, but has not been processed. the state: 4.4.4 (1 The LH flip- The LH flip-flop is set to - LH) by (LOAD LH). The zero output of LH is routed through gate 8 to MULTIPLEXED LHS(l) OUT, Clock Skip and Interrupt Circuits (see Figure 4-15 and Drawing D-BS-DC08-A-3) Up to four clocks of different frequencies can be included in the DC08A. The frequency of each clock should be five times the baud rate of the sampled data; therefore, five clock interrupts will occur during the sampling of Each clock is free running, but normally disabled by the clock flag flip-flop input gate. each bit of data. A TTX ON instruction sets the enable flip-flop, clears the clock flag flip-flop, and enables the clock flag flipflop input gate. The first positive clock transition sets the clock flag flip-flop, generating a clock n flag (where n is the clock number), which is combined with the other clock flags to generate INT. a bus driver to become INT RQST. clock has caused the interrupt. The program detects the interrupt request and attempts to determine which This is accomplished by generating skip instructions. When a skip is generated enabled, generating SKIP at gate A 16-B1. SKIP informs the PDP-8/I for the appropriate clock flag, its gate is that it has determined the clock causing the interrupt. flop and enables its input gate. CLOCK 1 FLAG(l). CLOCK 1 INT is coupled through For example, TTI ON (6424) clears the Clock Flag flip- The next positive transition sets the Clock 1 Flag flip-flop, generating FLAG(l) is combined with the other clock flags to generate INT. T4 SKIP (6451) is generated first, no SKIP signal is generated. Assuming The same logic holds true for T3 SKIP (6441) and When Tl SKIP (6421) is generated, however, a gate combines Tl SKIP and CLOCK T2 SKIP (6431). to generate SKIP. 4-23 1 FLAG (1) r '"I (SEE ALSO DWG.D-BS-DL08-A-3) (CLEAR) TT1 OFF/ON CLOCK F2 J2 I) 2 C 1 CLK FLAG T1SKIP(6421)A1 J^N vC *$» E'.' -'=o 1 D1_ CLOCK IFLAG(I) El —* § 1E A16 j°" JT^ A16 \>- E^*-«—WIRED OR A16 \> £> A16 V>- ( D-BS -OC08-A-2) E1 1 Dl TTt 0FF(6422)-0 (CLEAR) ENABLE D T2 SKIP(6431) C 2 ci CLOCK 2 FLAG (1) B1 (SET) ! (CLOCK 1 IS TYPICAL OF CLOCKS 2,,3. AND 4) ———— 4V J^S^ <r5> T3SKIP(6441) D2 I -J n one* a«m» *^ CLOCK FL AGO) 3 pi S J %. '&» T4SKIP(6451] H1 I CLOCK4FLAG0) K1 A1 ^^>o- £> A16>0- E> e^fc>o E> -^fc>o- Figure 4-15 Clock, Skip and Interrupt Logic Diagram INT (D-BS-DC08-A-2) Skip instructions are usually sequenced from 1 to 4. and clock 4 the lowest, with the others in sequence. Similarly, clock 1 is usually the highest frequency clock, Therefore, the higher frequency data lines are given priority over the slower ones. Line Register and Control Theory (see Figure 4-16 and Drawing D-BS-DC08-A-5) 4.4.5 a. The seven-stage line register with its associated decoder. b. The five-stage R register with its associated decoder. c. Output gates. 4.4.5.1 Line Register LR - The seven-stage line register LR (LI, L2, L4, L8, L16, L32 and L64) can be loaded with either the contents of MEM 2 through MEM 8, or BAC 5 through BAC input gates designated as BA 1 , setting the LR to the value of status (S) cycle of the TTI instructions after STLR clears the ables the series of input gates designated as BE is done during a TTO instruction. 1 , 1 1 . MEM - LSR enables the series of MEM 2 through MEM 8. LSR during S-TS 1 This is done during the (see Figure 4-6). TTLL (6412) en- ORing the LR with the value of BAC 5 through BAC 1 1 . This The LR can be incremented by TTINCR (6401) (or cleared by TTCL (6411) or by STLR during S-TS 1), both of which are ORed in the instruction decoder. The outputs of the LR are decoded and form the LINE SELECT group of signals, allowing selection of any one of 128 line control circuits. The contents of LR can also be ORed into accumulator positions AC5 through AC! 1 by IOT instruction TTRL (6414). 4.4.5.2 R Register - The number of assembled data characters that can be processed during a service cycle is generally programmed to be from 20 to 40 percent of the total number of data lines in use. The software enters the two's complement of this value into the load distribution counter (R register) at the beginning of a service cycle. Then, each time a character is processed, a count of one is effectively added to the value remaining in the R register by TTR INCR. When the content of the register reaches zero, no further character processing can take place until the next service cycle is entered with R^O. with the contents of BAC 7 through BAC 1 1 The R register (Rl, R2, R4, R8 and R16) is loaded by IOT instruction TTLR (6472). As each input data character is processed by a JMS, the program issues IOT instruction TTR INCR (6461). R register is incremented by one count. The program can then issue IOT instruction TTRR (6464) to read the R_ regi s ter count into accumulator positions AC 7 through AC as IOT instruction 6465. The 11 . TTR INCR and TTRR can be microprogrammed The R register can be cleared by IOT instruction TTCR (6471). 4-25 r TTCLJ6411) 4 STLR (CLEAR LSR) TT INCRI640I) B MEM—* LSR SEVEN LINE NBRs MEM MEM2-MEM8 INPUT GATES LOAD LSR BAC5-BACU AC INPUT GATES 33 7-BIT LSR (0) LINE REGISTER LSR I) [Line select] to m750 modules (LSR) HI OR LOW ORDER (See dwg D-BS-DCO8-A-0 0-63,64-127) FROM INSTRUCTION DECODER (Se«Fig.4-17and dwg D-BS-DC08-A-4) to EIGHT GROUP NBRs DECODER TTRL READLSR^ TTRR READ R O LSR OUTPUT GATES LSR REG. OR R REG. CONTENT TO AC VIA IB05-IB11 (See dwg D-BS-DC08-A-2) R OUTPUT GATES (CLEAR R) TTR INCR BAC7-BAC11 |( AC INPUT GATE RL»0 5-BIT R= R REGISTER R(0) DETECTOR RH °°.» BR>0 (See dwg D-BS- DC08-A-2) MEM 2 -MEM 8 ( BAC5-BAC1I (Also see dwg D- BS- DC08- A-5 Figure 4-16 Line Register and R Register, Block Diagram ) Output Gates - The output gates allow either the contents of the LR or the R register to be gated to 4.4.5.3 the accumulator. TTRL (6414) ORs the contents of the line register to AC 5 through AC 11; TTRR (6464) ORs the contents of the R register to AC 7 through AC 11 4.4.6 Instruction Decoder (see Figure 4-17 and Drawing D-BS-DC08-A-4) The instruction decoder circuits decode all IOT instructions issued by the program except TTI (6402), TTO (6404), and TT INCR (6401). TTI and TTO are not decoded in the DC08A. TT INCR is described in Paragraph 4.4.7. Coded IOTs are applied to binary decoder gates that produce outputs of octal 1 through 7. These seven signals are applied to three decoder timing gates (1, 2, and 4). The decoder gates are simultaneously enabled by DC INST during the IOT cycle and individually enabled by IOP1 , IOP2, and IOP4. The relative timing of the IOP pulses is shown in Figure 4-17. The decoded instruction is formed in three steps. The first two digits (64) are assumed with DC INST, because the 6400 series is reserved for data communications. binary decoder gates. The third digit (1 through 7) is the discrete output of the The fourth bit is determined by which decoder timing gate is enabled by an IOP. The program controls the issuance of IOPs and can issue any combination of IOP1, IOP2, and IOP4 for the purpose of microprogramming IOT instructions. Thus, 64 is implied by DC INST, and the last two digits of each instruc- tion are a combination of the binary decoder output and the programmed timing pulses. the R register, instruction TTLR (6472) is required. For example, to load The program issues an IOT code of 64XX, which results in DC INST and BMB06, 07, 08 for a binary 7. IOP1 is skipped, and then IOP2 enables decoder timing gate 2 to produce 6472 (TTLR). If the programmer desires to increment the R register with TTR INCR (6461) and then read the R register contents back into the AC with TTRR (6464), a microprogram can be implemented as follows: a. The IOT results in DC INST, and the program issues BMB06, 07, 08 for a binary 6. b. IOP1 enables decoder timing gate 1 to produce 6461 (TTR INCR), IOP2 is skipped, and then IOP4 enables decoder timing gate 4 to produce 6464 (TTRR). Thus, two instructions are decoded during the same IOT cycle. Each pair of clock control instructions (TTI ON and TTI OFF, etc) is applied to an OR function such that when either clock instruction is issued, the OR function produces an output. For instance, when either TTI OFF (6422) or TTI ON (6424) is issued, TTI OFF/ON results for the same duration as the instruction. 4.4.7 Line Control Gating Circuits (see Figure 4-18 and Drawing D-BS-DC08-A-4) The line control gating circuits both develop and amplify the signals that condition the M750 modules. control signals are applied to all The M750 modules (in either low or high order) in parallel. The output of the 4-27 STLR TTCL + STLR BMB06 _ 11! BlifB07 (2) (2) Bf*B08 (3) (3) ^ 6421 BINARY BMB06 BMB07 FROM PDP-8I -»DC08A INTERFACE (See dwg D-BS-DC08-A-2) ^ DECODER GATES (4)^ (5)^ •T1 SKIP 6431 fc HL (5) T2 SKIP DECODER TIMING 1 -*- | BMB08 (6) (6) fc <7L I TO LINE REGISTER AND CONTROL CIRCUITS T3SKIP GATE (See dwg D-BS-DCQ8-A-5) T4 SKIP_ TTR INCR | 6471 (7). tTct? OP 2 TTLL 6412 (1> I0P4 (2) DC INST TT1 OFF (64nn) 6432 (3) DECODER (4) TT2 OFF 6442 TIMING TT3 0FF GATE (5) I TS3 6452 2 (6) 6462 (7) 6472 TT4 OFF SPARE TTLR IOT END CO (1) | 6424 (2) •TT1 ON (3) •TT2 ON DECODER (4) | (5) TIMING GATE 4 TT3 0N 6454 (6) 6464 (7). 6474 TT4 ON TTRR SPARE 64 22 1 6424 APPROX. uSEC EACH 6432 0.8 6434 TTt CLOCK INST 6442 6444 OFF/ON TT2 OFF /ON OR- GATES 6452 * TO CLOCKS 1—4 TT3 OFF /ON SKIP 8 INTERRUPT (See dwg D-BS-DC08- A-3) TT4 OFF/ON 6454 (Also see dwg : igure 4-17 IOT Instruction Decoder, Block Diagram D-BS-DC08-A-4) B MB11 TP3 DLYD TT INST \, I? TT INCR fc * IOT INST TT INCR 6401 ) dwg u-bs-utuo-A-oj 1—»LINEOUT 0-63 DATA BAC11 (DATA OUT) ( OUT GATES B MB9 INITIALIZE LINE DRIVER INITIALIZE > DATA OUT) 1—»LINEOUT 64-127 INITIALIZE 0-63 INITIALIZE 64-127 LOAD F 0-63 FROM PDP-8I—»-DC08A-< LOAD F GATES INTERFACE (See dwg D-BS-DC08-A-2) LR (S ee figure 4-16 and DECODER TP3 (LOAD DATA) LOAD F 64-127 LINE CONTROL SIGNALS T TO M750 MODULES . (See dwg D-BS-DC08-A-1 LOAD LH 0-63 LOAD LH CO) ~ GATES * LINE HOLD _ DRIVERS LOAD LH 64-127 1—»LH 0-63 LINE HOLD DRIVERS —»LH 64-127 HO 0-63 HO 0-63 HO 64-127 1 *~ HO INV "HO 64-127 (Also see dwg D-BS-DC08-A-4) Figure 4-18 Line Control Gating Circuits, Block Diagram 4-29 iine register (LR) determines which M750 module responds to the control signal. Thus, the line control gating circuit produces the control signals, and the LR output determines which M750 module is affected. The gating circuits operate as follows: When outputting data to a line, TT INST enables the data out gates and the load F gates. BMB9 The output data on BAC 11 is applied to the M750 modules as At TP3 the load F gates apply LOAD F to the M750 modules, and the data is set into 1 - LINE OUT. a. also enables bo th sets of gates. the F flip-flop of the selected line. b. INITIALIZE is coupled through line drivers to all M750 modules. c. The combination of LINE HOLD and C(l) signals sets the value of the signal 1 - LH flip-flop of the selected M750 module. The HO 0-63 and HO 64-127 signals are outputs of the highest order flip-flop in line register (LR). These signals simply determine which half of the 128 lines are affected by all other line control gating d. signals. The uppermost gate shown in Figure 4-18 generates the TT INCR (6401) instruction, the description of which was omitted in Paragraph 4.4.6 because it occurs during TT INST. If BMB 11 is a one during TS 3 of the fetch (F) cycle, TT INCR (6401) increments iine register LR at TP 3 DLYD of TS 3. 4-30 CHAPTER 5 MAINTENANCE Maintenance of the DC08 Data Communications System is limited to the use of both off-and on-line diagnostic programs. Test modules are supplied with the system for use with the off-line diagnostic program. Test Module simulates 16 input/output lines. The test modules are inserted in DC08A locations A29 through A32 and B29 through B32 in place of the operational cables. number of operational input/output lines. Each G724 Up to eight test modules can be used, depending on the The diagnostic programs listed below can be obtained from the Program Library, Digital Equipment Corporation, Maynard, Massachusetts. Appendix C Maindec 8I-D8AA - DC08T1 , DC08 Off- Line IOT and Data Test Appendix D Maindec 8I-D8BA - DC08T2, DC08 On- Line Data Exercise 5-1 CHAPTER 6 DIAGRAMS This chapter contains all pertinent equipment diagrams for the DL8I and the DC08A. options are included in the particular addendum devoted to each option. The following drawings are contained in this chapter. Revision Page D-FD-DL8I-0-1 E 6-3 D-BS-DL8I-0-2 J 6-5 D-BS-DC08-A-1 (2 Sheets) C 6-7 Drawing 6-11 D-BS-DC08-A-2 (2 Sheets) D-BS-DC08-A-3 B 6-15 D-BS-DC08-A-4 C 6-17 D-BS-DC08-A-5 B 6-19 D-MU-DC08-A-6 (2 Sheets) B 6-21 C-CS-M750-0-1 A 6-25 D-CS-M751-0-1 A 6-27 D-CS-M752-0-1 A 6-29 6-1 Drawings for all DC08 STATUS FETCH (F) CHARACTER (C) (S) __i MA + MA +I-*>PC Tl I —PC PC MA+I T" 1 MEM - LSR | LH »HS 50 NS | !- ,i 1 350 NS HS(O) T2 1 MEM—^IR MEM9(0) MB9(0) MEM(l-ll)— mb(i-ii) MEM9 (l) ., MEM +I-»»Mb| | (l) MEM MEM^S».MB LINE-^MBO —MQ MEM (0— 8) LINE-»MB0 MB*" (0—8) 0-»-M B (9-1 l) MBII (0) T3 HS MEMO (l) • HS(O) MEMO (0)+ HS(l) MB9(l) | ,, MBII (l) AC R+0 SHIFT RIGHT MB (9- 1)=2 HS (0) MB (9-1 l)^2 | 1 LINE—ACQ MBII (0) MBIl(l) 4-2 I + 1 LSR | »PC | MB 10(0) MBIO(I) REQ RK BRK REQ BRK REQ ,, BRK REQ PROGRAM 1A DATA_ 1 j~PC—s>MA MA I I PC MA j ADD CYCLE I t 3 CYCLE | WC I *"E I O I CYCLE I I MA PC WC 1 j_T — MA 3 CYCLE | I JMS—IR~j BRK REQ BRK REQ I CYCLER 3CYCL JMS—IR I t>WC [ ! J MS—l"R I »E | Q D-FD-DL8I-0-1 6-3 HS MEM—AC MEM^AC Flow Diagram (I) i D-BS-DL8I-0-2 Data Line Interface 6-5 -LINE NOTE: ** FOR LINE A LINE B AND GROUP REFER TO PRINT DC08-A-5 A,ND/OB. DC<&8-A-I ^/^. , MUK OUT(0) pLHS(l) X SEE CHART ON SHEET*^ FOR. LOCATIONS AMD PIN LETTERS FOR SIGNAL ORIGIN15 OF i-*LH. 1-frL I N E O U T, HOjlNITI AL12E LCAD F + LOAD lH REFER TO PRINT DCOS -A- 4- + DCOSA-I. 2/2 1 Q.4- R5 B=i0-rL DIZ. I Lu^ri I ^7~Q ?J~Q 7^ Mn<7S!| T Rl$? T DcbCb4 D&64 EXbC=4- VPI4 D\=. i 1 Ei Aline ln(b) LINE IN (A} LAI A. J.N A- o~ -o: FCA) F(A") F(B) F(B) fz. kz. Ipz. rz. F(A) V IN (A) 31 C D«<£4 D<Z CATA OUT A,- [ D- L.H(A) -C D C FCB) D C D- D M9^ i * A-DATA JjJ ;.R," LHfB) -C fuINV IN (B) *—4- C RI2 ^3^00 DATA OUT(B") 310A ?; A^Dir I -V 1 1 0-*n H- ± IIIVETKTEP CUT (A) I — LW. INVERTER Cl'~ (p) +3.5V DCbXndL ZS -LINE OUT**-* D<bfe4FCB)' D(br4 OlCb _a x -r? r />" SELECT ONE SELECT ONE INITI ALTLE. * * * LOAD LH*** RS M75 (SEE UOTE) OT? filter :n i IN 'B) 3> 25_TT_ (a; FIL-ER OUT RH FILTER •FILTER -At- GROUP OUT (A) C=5 T_ Cd.S MFD LINE (A) * * + 3V LOAD F C4 LINE(B) G>.S MFD (?; ^F D-BS-DC08-A-1 Line I/O Control 0-127 (Sheet 6-7 1) V1150 LINES (OCTAL.) c- Z-3 MODULE 4-g w ^^ Sl. m c<a=5 Cd-T g^-q 10-1 M c10! LOCATION! LINES (DECIMAL^) LOCATION O-l C0I C0-. I IZ-13 14— 1^ SIGNAL NAME LOCATION PIN DATA IN <2<& _A£q_ OUT 00 _,. - OUT 01 IN oT OUT0Z. c&S Z4-Z5 zc— zi 3Q-31 JSL 34-35 44-4= outcviIN 0f Z.0-^.1 ZZ.-2.3 Z5 Zfc-ZH zs-zq 3Q-3I CIZ CI3 CI5 IN 0Cp ouTjatS" IN B1 ^-9B TiT IN ^3q~ CZ0 in aq out eg IN 10 C14- 44-4-5 Afo-41 4j3-4q ObO-Cbl 1C&-11 2_L 1Z-13 14-15 'fe-Bq CZS TJ ^ PU IN 13 OUT 13 lgXo-101" Tg>-T O<04 114-115 nca-nn 7t-13 "74 -~I5 IZO- Dge &T--Z big> IZfo-IZI SCto-sn Piz D'3 ' 30- 131 I3Z.-1= _ 154- 135 l3Cb-IB1 14-0- 14 B4-&5 &3-8H qz-q3 qp-qi yz. OUT 41 IN 4& OUT 4g> 150-151 152.- 153 154- 155" I5to-I51 110-111 ICbO-lCbl IZ-II3 (PIS DZQ &?.^> l&Z- I&3~ 114- n5 QZQs IGs4-lCb5~ iifo-in ot-i D^-S '<-c _nj ins ni- hb 114- 115 no,- hi NOTES 1. n?*,>-2jO— I7_l IZZ-1Z3 IZ4-IZ5 IZCc-IZI in iq is ~cr~ — - IN 49 OUT4q IN g. M IS OUT Z.O ?,! OUT Zl IN ZZ OUT -Z7 IN Z3 OUT "23 IN Z4 I0gp- IQ1 iSB-feSq _A3<£_ IN PIS 03 04-105 n OUT R4-q5 100-101 in IN IN ZO I I4Z- 14-5 D3Q T"_~ -f R-2S-2- - OUT IP, D<0q IZZ-IZ3 IZ4-IZS D~g- R2T IN 4<b OUT 714IN -2.5 OUT Z5 IN Zto OUT ZCb in zi OUT Zl in ze> OUT ZS in zq Out zq IN 30 OUT 30 ! V! 7JT : . T7z~ MZ ""KPT . A37j$- tt_~ DATA OUT Co3 _B31 - - h CI ^ -iiL _UI out qq" ZEE IN OUT IN I0JL 'IN Tl _LLL •IW'TZ."ourr rrz. T-72- IN 103 OUT j^q OUT IC -OUT Cb& g-« OUT CcQ "IN IP OUT 10. IN EZ T7T IN -J7T KZ~ T727" TTZT S-2- TTZ~ OUT 101 ^ P Z- IN 10= OUT 10S" IE2Z IN 110^ sz IN ' "B7i.q _&3<S_ _B3i OUT 114 -iLL IN 115 OUT 115 IN I Kb _BA. Sfo _VJ_ IN P.q. in sq OUT 8S _£Z_ OUT SPl INJ <=V£>~ out qg' IN S.L out qi E-2- OUT IZ0 oz IN IZ OUT-1ZI IN IZZ .I K.Z OUT 1ZZ IN1Z3 Nit. IN JE- OL in q3 OUTJB ooTq4 PZ ini q4- 3rr: INJ uz. IDATAxOUT. 95" Ml NZ IN 10& OUT 18" S5 10fo _IbL OUT Sfe in ai our an ~o7r VI XZZ '.(Z4- IN 1^5 OUT 105 J'g- IN 11 IN 1& in iq out iq ..IN FttZ) OUT SO IN SI OUT SI 1 1 OUT 10Z IN 14 Out 14" IN 1P5 PUT 15 XN.. 5a. OUT H<5 INJ ~DT CbCo IN fel dot (on IN fog, OUT SZ." XN B3 OUT S3 IN &4 OUT S4T _>1 Fir UZ. -___ DATA OUT 31 OUT 5<£ OUT 51 "SETOUT 5-2, IN 53 OUT 53 IN 54OuT 54 IN 55 OUT 55 IN 5<o OUT 5to IN 51 _ OUT 51 IN 53 OUT_5& _q" ini OUT sq IN CoCD OUT fed' IN fol OUT IN CoZ. OUT CoZ. i. ~cut ii VI TT2T" sz OUT Kb "P05 D0fo D01 " IN 43 TZ. ,, 14 TS D03 pzr OUT 14 IN 15 IN T^g- CbS-CcQ' "Tjf 1 ^5 - JT^i S CZ.4 CVZ_-C>3> <_>4-CbS GsCo-Gsl OZ- our i0 CZ.Z. <_<&-C_-! I04-I05~ OUT in sq OUT 3°l -IN 40 OUT 40 IN 41 OUT 41 _CJZ_ OUT CIB 5g- 5| 54E£b-51 3S Rl ____ IN OUTff IN DATA IN qc _B'2.q_ OUT Cb<^ __J_ ___L OUT 31 OUT' IN <b5 IN _)<_ IN 31 : te-iq •2-4- _3Zr33_ OUT Cb4 OUT 33 IN 34 OUT 34 IN 3.5 OUT 35 = ! DATA IN <2=4 JR. JHL IN (ZL. LOCATIONS £ DESTINATIONS LETTER SI&NAL NAME LOCATION PIN LETTER SI&NAL NAME LOCATION "PIN LETTER PIN OUT IN 0:1 C0Co CONNECTOR LETTER SIGNAL NAME ' BBS" LZ 17.4 T 7Fn ?^ IN \Z.(o OUT IZfo XN IIT RZ sz. TTZ~ DATA OUT IZ1 '. REFERENCE TO MODULE LOCATIONS (M15?S) THE DIA&NOSTICS REFER TO LINES IN OCTAL. CONVERSION 13 PROVIDED TO EASE UNDERSTANDING OF PRINTS WHICH REFER TO LINES IN DECIMAL IN D-BS-DC08-A-1 Line I/O Control 0-127 (Sheet 2) 6-9 notes: CABLE LENGTH NOT TO EXCEED FEET 2.PINS C,F, J,L,N,R. 6 U ARE GROUNDED ON ALi_ Wall's I. 10 PDP - 61 v,0M W0I U0I A0I 12 EAC ! 25(25 BAC t E2! W011 A0£ (I) I EAC 02 (0 K2 BAC ?i (0 EAC 04 ( PDP - 31 W0II W0I J03 A(Zi3 W0I A 04 D2 D2 I 8MB 0V> (I) E2 BMB 0! (1) E2 E2 K2 BMB 02 (1) H2 H2 D2 CO HZ\ ! I K2 BMB <Z>3 C0; K2 K2 M2 BMB 03 (0 M2 M2 I [ BAC 05 (1) VnBI Ml 01 BAC f^ 5 A ?Z BMB 04 C0) P2 P2 S2 BMB 04 CI) S2 S2 ' Ml 13 B0P \~CI BIS W BAC 06 CO Ml 01 BAC & 6 Ml 13 T2 BMB 0S C0} T2 T2 V FI V2 BMB 05 CO V2 V2 Vf2 PDP - SI W0II W0II B04 615 BAG 07 (!) V MUSI HI BAC V 7 Ml 13 B0Q BIS BAC 08 (0 M 10 Kl W0II J04 B03 BAC 08 MII3 BI5 B0Q V^KI BAC 06 BMB II CO V2 MI0I Vf 2 BMB Ll '" M AI0 WJIII W0II W0I1 J 02 B0I B02- BAC q BMB (!) MI0I V.MI SAC \_N Ml 13 YJ<2 1 W Ml 01 i K2 I ! BAC M 101 \-, si BMB ^ q + 3V M 13 (0 V-.SI BAC I \_N I BAC 10 *- BMB 0S CO I MII3 BI5 B0=) MI0I BMB K (l) 10 1 MI0I BMB <f\ /"* BIS 1 Ml^l V,UI AI0 AI0 3 B04 BAC CO BIS Ml 13 BIS 10(1) 10 BAC 0q B0><? H2i 3 1 BIS PDP - 81 VnN2 BMB 06 (0) W^ BMB 03 MI0I V^KI AI0 BMB 07 MI0I 11 \„UI BMB E0O 07 CO MliZSl BMB 07 &0q EI CP =2| C0) 4- MIZSI WJ2 BMB 0<5 CO MI0I BMB 06 AI0 BMB 06 (0) MI0I •2 I S INITIALIZE B INITIALIZE M 1 i Y-J-2 P V^.BI ..AI0 I Ml 13 V^SI BI6 INITIALIZE D-BS-DC08-A-2 PDP-8I DC08A Interface (Sheet 1) 6-11 PDP-8I W0I J 05 I AC 00 BUS D2 W0II PUP- 81 W0JI A<Z>5" H04 D2 D2 W0I A07 MEM P D2 PDP-8I W0JI W0II H0S B<Z7 D2 MEM 06 D2 0=1 E2 10 H2 1 BUS E2 E2 MEM 00 E£ E2 MEM AC 02 BUS H2 H2 MEM 01 HZ H2 MEM K2 MEM 02 K2 K2 MEM -V AC 01 E2 ' H2 AC 03 BUS M62s\di_ — M623 VEI 1606 IB07 M623 yj<^ M2 MEM izsa M2 05 BUS P2 MEM 04 P2 52 MEM 05 32 T2 MEM 06 T2 V2 MEM 07 VZ AC » All AC 04 BUS AC 06 BUS 1 K2 1 iV 1 M3I0 _1_ q A" AC gST BUS S.EE NOTE *l TP3 J H2 | ( || I50N5} M2 — HI - ^ _.. D^ TP3DLYD I AC 03 BUS M623 W-l PDP-8I W0I J06 pdp-31 W0II wan I W0II A09 D<24 B05 B LIME HOLD AC 03 BUS LINE HOLD C A" ~C M623 V.SI AC 10 BUS -C * B AC All P M623 W I B C BUS I MEM - LSR (0) C 12 (I) I/O SKrP All ™n <^4 AC LHB CO CLEAR BUS RUM Me as\_uf 00) aii y~^ B TT INST MI0I B0<* LINE MUX (0) D-BS-DC08-A-2 PDP-8I DC08A Interface (Sheet 2) 6-13 MI4I AI6 IF2 ^2 I UII C|clk. Flag lt>n c d OFF/ON* INIT -• N I Q Mlli J2 \ "2| V2 TT I -q OFF + INIT Al i D-4 enable: I P c "Jci Ta Al INT FLAG 3 £>— D2 D T2 J2 • ;r^r-Q)r> K2 ' CLK. Al - VI P TT3 OFF/ON* I NIT <" 1 P—*—t M 141 \_ P2 Dl|0 SKIP • S2 \zn^y> A Q Mil. K I >. | ;^iq_jc> CLOCK 3 M4ljZi Biq (IOT 424) £ TT3 0FF+IN1T -C( ENABLE 3|D— C Ml 13 M206 AIT \KI IUITIALIZE 51 J AI3 Ml 13 TTI OFF'INIT A 14 TT2 OFF AI6 I (IOT 4 4 4) E'J M I 13 \FI Ml 13 Ai3 Fl TT2 OFF* INIT 72 TT3 OFF* Kl TT4 OFF -INIT K_2 TTI OFF/ON*! NIT Nj TT2 OFF/ON* INIT N_2 TT3 OFF/ON+INIT SI TT4 OFF/ON * INIT AM HM1I3 \F2 Ml 13 E2 J AI3 INIT AI4 R2 P2 TMI 13 K2 qCLK.FLAG 2P-4 ,N2 TT2 OFF/CN + IN" Jl I D M2 \K I A 13 MH3 A14 C J2 J TTI L2 ^ MII3 JjJ AI3 OFF/ON H2 CLOCK 2 4 1(5 J2 \K2 M 113 AI4 f .< A2f LI ] TT2 OFF *INIT- ENABLE 2 D-" -C ON — +3V ' OFF/ON C D JMII3 \NI Ml 13 AI3 AI4 ,J2 CL0CK4.r M4I0 C HI T"T2 OFF/ON.* IN IT KI [D (IOT 434) -C CLK. FLAG 4- Q-n Ml B20 TT3 ' OFF/ ON iMII3 \N2 M2 J A 13 I Ml 13 A 14 M206 AI8 _JT4 TT4 OFF+INIT q D J[ci TT4 ON ("IOT 4£4) OFF/ON ENABLE 4 D-f -C I j 61 TM1I3 _RU AI3 \SI MII3 A '4 +3V M206 BI8 I I D-BS-DC08-A-3 Clocks 1-4 Skip and Interrupt 6-15 INE BWIB 09 TZ cCi) Ml 13 — AIT V2 TP3 >t£ CI _ [Al 'bi ^ M627 A24 / ~SI TT INST OUT 64-127 * PI i CI + 3V TT IWST- BAG BMBq I I f- TP3 - "AT N BI M62 7 VvEl A25 P^-— / M627 V,P2 A ZA — L H LOAD F I A24 . h P "1 INIT2AL1ZE LH S2 LINE HOLD LI 1 + 3V- A 24 'r2 HO 0-63 < j 64 -127* HO sl + 3V T2 , u* M627 \V.2 A24 p HO S4 - 127 * $- 63 # ^ -63* M627 W J2 INITIALIZE A2J 64- 127 * 0-63* / ! *NOTE: THESE TERMS ARE USED ON DC08-A-I AS l-»LH, LOAD LH,I->LINE OUT, LOAD F, HO, AND INITIALIZE D-BS-DC08-A-4 DC08-A Instruction Decoding 6-17 (IOT 40IJ TT IN CR (IOT 4MJTTCL (IOT 4I2JTTLL B *. r ;Ori::: i.inf^'a" MEM -> LSR MEM 06 ~0.1TJ,L4 6*C, FOR ALL : .:N= T±'5 : _ Ti J_"= , i_s e c -=r '...NES **'S , for all odd MEM GSy D-BS-DC08-A-5 Line Register and Control 6-19 D won 4 won < BAC, .00 \ \ 3 won 2 i moil CABL I / BAC ,89 LAt 1 BMB 02 \ / \ / TO * t BMB 1 CAB W0 F BBB .05 / \ 9 2 i m MEM P / \ \ I \ / 2 HOtD -TO - \ / 3MB BMB .05 ac T° m \\ // BUS 11 TO LSR YA B STLR / A « A M11 W011 W01I mi A Mil 1 BAC .09 3AC 09 TO 1! TO BAC 11 BIOP 1 BIOP 2 BIOP 4 BIOP BIOP 2 BIOP 4 BTS BTS BTS BTS BAC / I / \ BUB 06 BMB 11 BMB .06 TO BMB 11 3 2 TT3 B TT3 +-IN1T + INIT R=;0 V" TT2 TT2 OFF/ON + INIT TT4 TT4 OFF/ON +INIT -UNIT 2 1 2 1 2 i 2 1 i SKIP j SKIP RQST IB 10 CLK CLOCK 1 1 CLOCK INT IB11 64-127 IB09 FLAG SKIP TP3 ENABLE CLK IB08 L2 IB07 16 L0 L7 LI G0-7 & 64-71 L3 3 3 L5 LH BAC 2 1 A 2 1 BAC 2 1 ENABLE 2 i 2 1 RH 24 26 25 M627 m BMB ;09 10 BAC BAC BMB DC ,184411 108 11 109 INST G48-55 BUS BAC tOP 2 BMB RUN B TT 11 TS3 ,120427 10 INITIALIZE TP3 DLYD INITI- FLAG 4 CLOCK CLOCK 3 4 G24-31 888-95 G32-39 :96-*03 I7F TT INST " S INST LINE MOX G40-47 27 28 IOP Ifll LH TP 3 TTCR 0-63 0-63 TO LINE OUT 64-95 Tl | 30 29 32 31 L M901 Msfll ALIZE 64-127 64-127 2 DATA DATA DATA DATA DATA DATA DATA DATA IN IN IN IN IN IN IN IN 00-07 08-15 16-23 24-31 32-39 40-47 48-55 56-63 T2 SKIP 1 TO LF LOAD 1 TO LINE OUT 0-31 1 8 0-63 LOAD F F TO LH DC DATA DATA DATA DATA DATA DATA DATA DATA OUT OUT OUT OUT OUT OUT OUT 64-127 INST. 00-07 08-15 16-23 24-31 32-39 40-47 48-55 OUT 56-63 HO LOAD 10-63 64-127 34 2 i 35 2 i 36 2 37 2 i 38 2 i 40 39 2 i 2 i 42 41 2 i 2 i 44 43 2 i 2 i 2 F 32-63 HO a-63 64-127 TT8 DFR/DN TT TT4 OFF ON TTLL TT2 TTRL ON TTI DATA DATA DATA DATA DATA DATA DATA DATA TT3 OFF OFF TT2 IN IN IN IN IN IN IN IN OFF 64-71 72-79 80-87 88-95 TT3 ON 96-103 13W-1.11 112-11S120-127 TT4 OFF OFF/ON TTRR DATA DATA DATA DATA DATA DATA DATA DATA TT4 TTR OUT OUT OUT OUT OUT OUT OUT OUT ON INCR 64-71 72-79 80-87 88-95 96-193 1:H4-1t1 112-11(120-127 TTLR M301 MS01 MS01 CABLE. 1 B 33 M301 CABL t SKIP & TT2 VIT- IOP 4 1 G56-63 1 I M301 INITI- LOAD LIZE LH OFF/ON G16-23 450-87 ,112-919 LOAD TTI ON .0 BAC 4 2 i CLK 07 R8ST INITI- TTCL LIZE 96-127 = .0 BAC IOP B ! 1 RL G3-15 72-7 8 2 1 2 11 INT I I A t I 23 HO 80-63 2 2 AC CLR M7F? IB05 HO ENABLE CLOCK LOAD 11 I/O INITILIZE INITILIZE 1B.06 2 1 4 MEM 2 i FLAG RQST 2 1 22 21 2 1 FLAG OFF/ON B 3 2 i ;85 TO BUS 1 i ENABLE INT DLYD BAC 05 B IOP - TOBAC 20 19 M11 3 2 MEM 08 l„0 OFF/ON OFF/ON + INIT 2 i I/O TT4 OFF OFF/ON 18 "7! 2 i TT2 OFF TTI TTI OFF /ON OFF/OI> + INIT + TNIT + INIT TT4 OFF 17 1 H141 TP3 UNIT V 1:0 BUS " 2 OF TT3 0FF + INIT 2 l6 1 1 TT2 OFF ROST _ 15 M 310 1 + INIT -UNIT DC INS SKIP 1 SKIP B / TO AC 11 1 B I/O TO BUS (lARIF AC ;09 BUS INT s Mil 2 TTI OFF TT3 OFF TTI STLR \ 14 M 113 3 + INIT + INIT flAC /\ 1 1 C \ / A 2 i AC ;05 LINE HOLD B MEM / \ MEM ;07 1:0 B TB 3 / \ TO BUB Ml 2 1 ,i 13 M623 2 I B LINE 3MB :06 12 1! M101 CABL- 1 4 1 10 *011 = ac BUS .0.0 8 1 TO T° / BAC .08 m \ bac 7 »011 j / \ 6 5 D 1 Msai _ua,E 2 2 CAE LE 1 , i 2 i 2 i 2 i 2 i 2 i 2 i 2 i 2 i 2 i 2 i 2 i 2 TTI T3 SKIP T4 SKIP D-MU-DC08-A-6 Module Utilization (Sheet 1) 6-21 J -M7S2- M750 M7SS J J J 20 17 10 M75-B M75-3 J 21 22 M75B T7&TT j J I DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA QATA DATA DATA DATA DATA DATA LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES 4-5 6-7 8-9 10-11 12-13 14-15 16-17 18-19 22-23 24-25 26-27 40-41 2-3 42-43 M750 M750 T15T "¥751" I J J J J M75Q M750 M750 M750 I J J J M750 M75fl HTBTT JIZ5JL J J DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES 64-65 66-67 68-69 70-71 72-73 74-75 76-77 78-79 80-81 82-33 4-85 86-87 88-89 90-91 92-93 94-95 96-97 93-SS 1100-101 DATA DATA DATA LINES 104- 106- 105 23 24 26 25 M750 30 29 28 27 M750 32 DATA DATH DATA DATA DATA DATA DATA DATA DATA LINES LINES LINES LINES LINES LINES LINES LINES LINES LINES 48-49 50-51 52-53 54-55 56-57 58-59 60-61 62-63 44-45 46-47 M750 JH5JL DATA LINES DATA LINES DATA LINES 112113 DATA LINES 114115 33 34 35 36 37 38 39 40 41 43 42 44 M75P. ~wm~ DATA "H75IT DATA DATA DATA DATA DATA DATA LINES LINES LINES LINES LINES LINES 116- 120- 117 121 124125 D D-MU-DC08-A-6 Module Utilization (Sheet 2) 6-23 LINE A IN VD9 ?R8 ADIO + 3.5V 1 4 J_ R4 VI FILTER J B I F A + U I V DI6 *WV ^?DI5' 1 <^ VDI7 R3 wv -C2.TI GND jf VdI4 H FA INVERTER A IN. ^fD3 >R2 "£E> I ik DZ INVERTER B IN. 5 }• |» r^ED INVERTER B OUT +3.5V Ads DATA OUT B NOTES'. PIN 7 ON EACH IC = GND PIN 14 ON EACH IC = +5V EX3^ R7 1£D7 j^D8 DI3 G [0 -7] L64-7IJ IB05 AE2 IB06 IB08 IB09 IBIO AD2 ADI AC AAI I 32-39 48-55 96-I03J L.II2-II9J BV2 BT2 16 - 23 cl" ! g[' [.80-87] |j GND AC2, AT! BC2.BTI + 5V AA2_ BA2 EI4,EI5,EI7,-E20 E4,E7,EI0,EI2 E3.E6.E9 E2,E5,E8,EU,EI3,EI6 El RI-R7 CI-C20 INTEGRATED CKT. DEC74HI0N INTEGRATED CKT DEC74H50N INTEGRATED CKT. DEC7401N INTEGRATED CKT. DEC7474N INTEGRATED CKT. DEC7400N RES. I.5K I/4W 5% CC CAP. .OIMFD IOOV 20% DISC PARTS LIST REFERENCE DESIGNATION D-CS-M75 1-0-1 DESCRIPTION PARTS LIST 1909057 1909060 1905590 1905547 1905575 1300391 1001610 A-PL-M75I-0-0 PART NO. Line Register and Control M751 6-27 AH2 AJ2 AR2 BD2 BF2 BE2 BAI n Y ro CD O CD H O il -£ z -J t ^8 x8 TTCLI (6411) BMB9(I) BACIKI) - AKI -AF2 -ACI -BV2 BU2BSI BR! - AA2.BA2 + 5V NOTES: AC2.ATI BC2.BTI GND PIN 7 ON EACH IC = GNO PIN 14 ON EACH IC = +5V Ell E5,E8,EI4,EI6,EI7,EI9 E2 E4 El , E5,E6,£7,E9.EIO,EI2,EI3,E 5,E 18 1 AE2 BL2 BN2 BM2 AS2 INTEGRATED CKT. DEC7402N INTEGRATED CKT. DEC7400N INTEGRATED CKT. DEC74H40N INTEGRATED CKT. DEC744QN INTEGRATED CKT. DEC74I0N RES. 750 I/4W 5% CC RES. 330 I/4W 5% CC CAP. BBI BFI AN2 REFERENCE DESIGNATION D-CS-M752-0-1 .01 MFD 100V 20%DISC PARTS LIST DESCRIPTION PARTS LIST A-PL- M752-O-0 Instruction Decoder M752 6-29 Equipment Corporation Maynard, Massachusetts Digital printed in U.S.A. FIRFUHIRII kUUtSJUUHll
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