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DEC-8E-HR2C-D

December 1973

202 pages

Original

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Document:	MaintIntlOpts Vol2
Order Number:	DEC-8E-HR2C-D
Revision:
Pages:	202
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OCR Text

bus options
maintenance manual
internal

volume 2

1BIDBID

MAINTENANCE MANUAL

VOLUME 2

For additional copies order No. DEC-8E-H R2C-D from Direct Mail, Digital

Equipment Corporation, Maynard, Massachusetts 01 754

Price:

$25.00

digital equipment corporation • maynard massachusetts

1st Edition May 1972
2nd Printing (Rev) February 1973

The material in this manual is for informational

purposes and

subject to change without

notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

CONTENTS
Page

EXTENDED ARITHMETIC ELEMENT OPTION

PART 1

CHAPTER 1

KE8-E EXTENDED ARITHMETIC ELEMENT
Introduction

Section 1

1-1

1.1

General Description

1.2

Software

1-1

1.3

Companion Documents

1-1

Section 2

Installation

1.4

Installation

1-3

1.5

Checkout

1-3

Section 3

System Description

1.6

Step Counter Loading Operation (Figure (1-3)

1-4

1.7

Step Counter to Accumulator Loading Operation (Figure 1-4)

1-7

1 .8

The Shift Left Operation

1 -7

1.9

Right Shift Operations (Figure 1-5)

1-7

Instruction (Figure 1-6)

1-9

1.10

Normalize

1.11

Double-Precision Skip if Zero (DPSZ) (Figure 1-7)

1-9

1.12

Double-Precision Complement (DCM) (Figure 1-8)

1-10

1.13

Double-Precision Increment (DPIC) (Figure 1-9)

1-10

1.14

Double-Precision Store (DST) (Figure 1-10)

1-11

1.15

Double-Precision Add (DAD) (Figure 1-11)

1-11

1.16

Subtract AC from

MQ (SAM) (Figure 1-23)

1-13

1.17

Multiply Instruction (MUY) (Figure 1-13)

1-13

1.18

Divide Instruction (DVI) (Figure 1-15)

1-14

Section 4

Detailed Logic

1.19

EAE Instruction Decoding Logic

1-19

1.19.1

El R Register

1-19

1.19.2

MODE Flip-Flop Logic
ROM Logic

1-19

1-21

1.21

EAE Timing Logic
EAE Timing Generator Timing Diagram
EAE Source Control Signals

1.21.1

1-27

1.21.2

Data Line Enable Signals

1-29

1 .21 .3

Data Enable Signals

1-29

1 .22

EAE Route Control Signals

1 .22.1

Step Counter Loading and Control Logic

1-30

1.22.2

Step Counter Logic

1-32

1.22.3

Shift Right/Shift Left Control Logic

1-34

1.19.3

1.20
1.20.1

1-19

1-21

1-22

iii

-30

CONTENTS (Cont)
Page
1.22.4

Shift

OK Logic

1-34

1.22.5

EAE Carry In Logic

1-34

1.22.6

1-35

1 .22.7

MQ Register Shift Left Logic
AC to MQ Transfer Signals

1.23

Destination Control Signals

1-35

.24

EAE Start/Stop Logic
Extended EAE Logic
EAE Link Control Logic
EAE Skip Logic and GT Flag

1.25
1.26
1.27

-35

-37

1-37

1-37
1-39

Section 5

Maintenance

Section 6

Spare Parts

PART 2 MEMORY EQUIPMENT OPTIONS

CHAPTER 2 KM8-E MEMORY EXTENSION AND TIME-SHARE
Section 1

Introduction

2.1

Memory Extension Description

2.2

Time-Share Description

2-2

2.3

Extended Memory and Time-Share Summary

2-3

2.4

Software

2-3

2.5

Companion Documents

2-4

2-1

Section 2

Installation

2.6

Installation

2-4

2.7

Checkout

2-4

Section 3

Principles of Operation

2.8

Introduction

2-5

2.9

System Description

2-5

2.9.1

Control Logic

2-7

2.9.2

Instruction Field Register and Controls

2-8

2.9.3

Interrupt Buffer A

2-9

2.9.4

Data Field Register and Controls

2-9

2.9.5

Interrupt Buffer B

2-9

2.9.6

Extended Memory Addressing Output Control

2-9

2.10

Operating Functions

2-10

2.10.1

Status Operation

2-10

2.10.2

Interrupt Buffer Transfer to Memory and Restoration

2-1

2.10.3

Instruction Field Register Loading Operation

2-12

2.1 0.4

Time-Share Operation of the System

2-1

Section 4
2.11

Detailed Logic

2-15

Instruction Field Registers

CONTENTS (Cont)
Page
2.12

Instruction Field Output Multiplexer

2-15

2.13

Data Field Logic

215

2.14

Data Field Output Multiplexer

2-1

2.1 5

Data Field Output Gates

2-1

2.16

Interrupt Buffers Logic

2-19
2-19

2.17

Interrupt Inhibit Logic

2.18

Interrupt-Break Detect Logic

2-19

2.19

2-19

2.20

Data In Logic

2-19

2.21

User Flag Logic

2-19

2.22

Trap Detect Logic

2-23

2.23

Extended Memory Address Logic

2-23

Section 5

Maintenance

Section 6

Spare Parts

CHAPTER 3 MR8-E READ-ONLY MEMORY
Section 1
3.1

Introduction

Read-Only Memory Description

Section 2

3-1

Installation

3.2

Installation

3-1

3.3

Acceptance Test

3-2

Section 3

System Description

3.4

MR8-E Block Diagram

3-2

3.5

ROM Addressing

3-2

Section 4

Detailed Logic
3-4

3.6

Address Decoder

3.7

Switch Select Logic

3-4

3.8

Line Driver Select Logic and Line Drivers

3-7

3.9

Sense Logic and Memory Register

3-7

3.10

Clear Logic

3-9

3.1 1

Line Select Diode Matrix

3-9

Section 5

Maintenance

Section 6

Spare Parts

CONTENTS (Cont)
Page

CHAPTER 4

MI8-E HARDWARE BOOTSTRAP LOADER

Section 1

Introduction

General Description

4-1

4.2

Equipment Requirements

4-1

4.3

Companion Documents

4-2

4.4

Software

4-2

4.1

Section 2

Installation

4.5

Installation

4-2

4.6

Checkout

4-2

Section 3

Operating Procedures

Section 4

Principles of Operation

4.7

General Description

4-4

4.8

Major Portions of the M I8-E

4-5

4.8.1

Address and Data Information

4-6

4.8.2

Sequence of Operations

4-7

4.8.3

Bootstrap Timing (Figure 4-2)

4-7

4.9

Detailed Logic Description

4-7

4.9.1

Bootstrap Timing Logic (Figure 4-3)

4-7

4.9.2

Bootstrap Control Logic (Figure 4-6a and b)

4-1

4.9.3

Initial/Starting Address Jumper Network and Output Logic (Figure 4-7)

4-13

4.9.4

Extended Memory Field Output Logic (Figure 4-8)

4-13

4.9.5

12 x 32 Diode Matrix and Control Logic (Figure 4-9)

4-13

Section 5

4.10

Maintenance

Troubleshooting

4-13

4.10.1

MI8-E Bootstrap Diagnostic Program

4-16

4.10.2

Direct Memory Access Control Signal Verification

4-16

4.1 1

Bootstrap Hardware Troubleshooting Analysis

4-16

Section 6

Spare Parts

CHAPTER 5 MP8-E MEMORY PARITY
Section 1
5.1

Introduction

MP8-E Description

5-1

Section 2

Installation

5.2

Installation

5-1

5.3

Acceptance Test

5-2

CONTENTS (Cont)

Section 3

Principles of Operation

Section 4
5.4

Field Select Gating

5.5

Parity Generator

5.6

Error Flip-Flop and Gating

Detailed Logic

5.7

IOT Decoding and Skip, Interrupt Gating

5.8

Special

IOT Control

Section 5

Maintenance

Section 6

Spare Parts

PART 3 REAL-TIME CLOCK OPTIONS

CHAPTER 6 REAL-TIME CLOCK OPTIONS
Section 1

Introduction

Section 2

Block Diagram

Section 3

Detailed Logic

6.1

Select Logic

6.2

Interrupt Flip-Flop Logic

6.3

Clock Flag Logic

6.4

Clock Logic

6.4.1

DK8-EA
DK8-EC

6.4.2

Section 4

Maintenance

Section 5

Spare Parts

PART 4 POWER-FAIL OPTION

CHAPTER 7

KP8-E POWER-FAIL AND AUTO-RESTART

Section 1

Introduction

Section 2

M848 Block Diagram

Section 3

M848 Detailed Logic

7.1

Select Logic

7.2

Power Monitor Logic

7.3

Auto- Restart Logic

vii

CONTENTS (Cont)
Page

Section 4

Maintenance

Section 5

Spare Parts

PART 5 INTERPROCESSOR OPTION

CHAPTER 8

DB8-E INTERPROCESSOR BUFFER
Section 1

Introduction

Section 2

Installation

8.1

Installation

8-1

8.2

Acceptance Test

8-2

Section 3

System Description

Section 4

Detailed Logic

8.3

Device Select Logic

8-4

8.4

Operation Select Logic

8-4

8.5

Interrupt and Skip Logic

8-4

8.6

Input Data Gates and Output Buffers

8-7

Section 5
8.7

Maintenance
8-7

Data Transfer Test
Section 6

Spare Parts

PART 6 EXTERNAL BUS INTERFACE CONTROL OPTIONS

CHAPTER 9

KA8-E POSITIVE I/O BUS INTERFACE
Section 1

Introduction

Section 2

Block Diagram

Section 3

Detailed Logic

9.1

BIOP Pulse Generator Logic

9-1

9.2

B M B B uf f ers/ n verters

9-3

9.3

IOP Timing Logic

9-3

9.4

Data Gating Logic

9-8

9.5

Skip Counter Logic

9-8

Section 4

Maintenance

Section 5

Spare Parts

vi if

CONTENTS (Cont)
Page

CHAPTER 10 KD8-E DATA BREAK INTERFACE

10.1

Section 1

Introduction

Section 2

Block Diagram

Section 3

Detailed Logic
10-1

CP Register Control Logic

1 0-4

0.2

Cycle Select Logic

10.3

Priority Logic

10.4

B KM A Register Logic

10-8

10.5

Data Transfer Logic

10-10

10.6

WC Overflow Logic and EMA Register Logic

10-13

10-7

Section 4

Maintenance

Section 5

Spare Parts

ILLUSTRATIONS
Title

Figure No.

Page
1-2

1-2

EAE Interconnections
EAE System Block Diagram

1-5

1-3

Step Counter Loading, Flow Diagram

1-6

1-4

Step Counter to AC, Flow Diagram

1-7

1-5

SHIFT Operations, Flow Diagram

1-8

1-6

NORMALIZE Operation, Flow Diagram

1-9

1-7

DPSZ Instruction, Flow Diagram

1-9

1-8

DCM Instruction, Flow Diagram

1-10

1-9

DPIC Instruction, Flow Diagram

1-10

DST Instruction, Flow Diagram

1-12

1-11

1-12

1-14

DAD
SAM Instruction, Flow Diagram
MUY Instruction/Operation, Flow Diagram
MUY Instruction Data Paths

1-15

DIVIDE Instruction, Flow Diagram

1-16

Major Registers

1-17

1 -1 7

Divide Example

1 -1

1-18

El R Register and Controls

1-20

1-19

MODE Flip-Flop Logic
ROM Logic
ROM Instructions

1-21

1-1

1-12
1-13

1-20
1-21

Instruction, Flow Diagram

1-13
1-14

1-15

1-22

1-23

ILLUSTRATIONS (Cont)
Figure No*

Title

Page

1-22

ROM
irtinnc
flUIVI 9 nctnU\*
liui

1-23

1-24

EAE
Timino
*\
iiiuiiy — oair
vjy
FAF
Timinn
fnPnprafnr
L-/~\L.
lllllliy \3 CI ICI
L\Ji Timinn nianram
L/ldyidlll

1-25

^niirpp
Pnntrnl riata
Qimnli-f iorJ D
\s V\ on»-o rv»
ouui
uc WUllllUl
LsdLd Path
rdUl, DliTipMTIcU
DIOCK
UldQiaiTI

1-26

PrnfPQQnr
Qplpotinn L_uyiu
nnin
ui/Coiui Rpnictpr
ncyioici ocicOLivJii

1-27

Data
inp Fnahlp
^innalQ
uaia l_iiic
l lauic oiyiidio

1-28

1-29

EAE
nnir for Prnrpccnr
ryim. Data
uaia Onntrol
wui u
i_wy
r vJl*C0owi Plata
L/dLd f*nntrnl
VvUIILIUI f^ia+oc
VJdLco
EAE RontP
Hmnnm
IUUIC Control
VUIIUUI Rinnal
UImI lul Rlnrk
LMUVsix LxluyiCIIII

1-30

Stpn
oadina
onirwlC(J Hountpr
OUUI IICI L.UOUII
iy and
CHILI Pnntrnl
V-/V-/I
LI vJ
LUylL

1-31

1-32

EAE Stpn Cnnntpr
^
EAE
Shift Riaht/Shift
Left
Control
wlllH
—b
wVS llll Ul Lonir
l_UUIlf
1^1 IL/ul

1-33
1-34
1-35
1-36

MQ Reaister Shift Left Loair
AC MQ TRANSFER Sianal

1-37

Destination Control Loair

1-38

EAE Start/Stoo Loair
Extended EAE Loair
EAE Link Control
FAF Skin nnip

1-39

1-40
1-41

£.

i—

loll

1-24

1 /-*/"»

OQ
1-zo
1

i—

oct

ILJ

1 1 1 1 1 1

1
I

iv_,

04.

Shift
Loair
wl
II
l v_y X l_U^lu

FAF
nnir
Lnt farrv
V-/Ui
iii i_<jyiLr
y In

OR
-oo

' »

III L

AC\

2-1

Mpmnru
iviciiiuiy Fvtpncinn
a lci idiui Qimnlifipd
o
leu Rlnr^l/*
DlLiLtlx P^ianram
Uridyl dill

2-2

Tvniral
yfjiUrui Timp-Rharp
iiiic «_)iidic ^»\/<:tpm
oyOLCIII

9
O
Z-O

2-3

Mptnnrv/
and
lr*r>L' Hionrom
ivicinui y FytPncinn
l_ A uci lOIVJl
dliu Timp-Qharp
lc-OI Idl c rnntrol
VsUULlUI, Qwctpm
Oyolclll R
DIUUK.
L/ldyrdlll

0
R
z-o

2-4

Fvtpndpd
AHHrpccinn
i— a lc lucu Momnru
iviciiiuiy rAULii
cool iy, Fln\A/
nuw Hianrflm
L/idyidiii

o 1n

2-5

IF
r and
dllu DF
U DiQnlav/
L-MofJIdy Qtatuc
OLdLUo Durinn
L/Ul Illy TQ1
o

O
Z- 1 1

2-6

Intprrnnt
f pr Tran<;f
and RpQtnratinn
lci u|ji R
uuifiici
a 10 pr
ci tn
lu Mpmnrv
ividiiuiy dim
ricoLUi d lilh I, Fln\A/
iu w Hianram
U Idyr d in

2-7

Intprrnnt
iiiLciiu|jL Rnffpr
uui ici Tran<ifpr
idiiaici tn
lkj Mpmnrv/
iviciiivjiy and
diivJ RpQtnratinn
ncoLUi d liui

9
Z- 10
O

2-8

Instrurtion
ion uuiivi Rpai*itpr
icyi jlci Loadinn
luuui *H/ Flow
vv Dianram
\J loyi oi

9
z- 14
*t

2-9

Instrurtion
oair
uu uiiiiui Fiplri
i&iu Rpaistprs
cy o lci o and
a ivi (Patina
vj li iy luuiu

9-1R
z- o

2-10

Instrurtion
iltoil UbllUII Fipld
ICIU Outnut
UUljJUL Mnltinlpypr
IVI U L (Jl CACI

9
z- 17
1

1 1 1

0 0

1 1

2-11

Data Fipld Loair

9-1R
z- o

2-12

Data
L/uio Fipld
IVI U LI fJIC ACl
ICIVJ Outnut
UULJJUl Mnltinlpypr

9
Z- 1R
o

2-13

Data
L/(3Lu Fipld
ICIU Outnut
vyULLJUL fiatps
VJuLCO

9
z- 1Q
y

2-14

Intprrnnt
oair
IILCIILJLJL Rnffprs
UUI ICI O L-V/y
c

9 9H
z-zu

2-15

Intprrnnt
LCI ILJLJL Inhihit
II II Ul L I— oair
vJ VJ

9
91
z-z

2-16

Intprrnnt
oair
IICI Upi Rrpak
U CUi\ Dptprt
l^/CLCV^L L_v/yiL#

9
91
Z-Z

9-17

ncyioLcr uiuar i_ugic

o
01
z-z

L/did in i_uyiu

o
oo
z-zz

2-19

User Flag Logic

2-22

2-20

Time-Share Trap Logic

2-23

2-21

Extended Memory Address Logic

2-24

3-1

Read-Only Memory Block Diagram

3-3

3-2

H241 Braid Board

3-4

3-3

Address Decoder Logic

3-5

ILLUSTRATIONS (Cont)
Pintiro Mn

Title

Page

3-4

Switch Select Logic

3-6

3-5

Line Driver Select Logic

3-6

Line Drivers and Diodes

3-7

Sense Logic and Memory Register

3-10

3-8

Clear Logic

3-10

3-9

Read Timing Diagram

3-11

3-10

Line Select Diode Matrix

3-12

4-1

MI8-E Block Diagram

4-6

4-2

Bootstrap Timing

4-8

4-3

Bootstrap Timing Logic

4-9

4-4

74123 Logic Diagram and Truth Table

4-10

4-5

CLEAR GO Signal Waveform Analysis

4-11

Bootstrap Control Logic

4-12

4-7

Initial/Starting Address Jumper Network

4-14

4-8

Extended Memory Field Output Logic

4-15

4-9

12X32 Diode Matrix

4-15

4-6

5-1

MP8-E Block Diagram

5-3

5-2

Field Select Gating

5-4

5-3

74180 8-Bit Parity IC

5-6

5-4

Parity Generator

5-6

5-5

ERROR Flip-Flop and Gating

5-7

5-6

IOT Decoding and Skip, Interrupt Gating

5-9

5-7

Special IOT Control

5-9

6-1

Real-Time Clock (DK8-EA, DK8-EC), Block Diagram

6-2

Select Logic

6-3

INTERRUPT Flip-Flop Logic

6-4

Clock Flag Logic

6-5

Clock Logic DK8-EA

6-5

6-6

Clock Logic, DK8-EC

6-6

7-1

M848 Power Fail and Auto-Restart Option, Block Diagram

7-2

Select Logic

7-3

Power Monitor Logic

7-4

Power Fail Timing

7-5

Auto- Restart Logic

7-7

7-6

Auto-Restart Timing

7-8

8-1

Interprocessor Buffer, Block Diagram

8-4

8-2

Device Select Logic

8-5

8-3

Operation Select Logic

8-5

8-4

Interrupt and Skip Logic

8-6

8-5

Input Data Gates and Output Data Gates and Drivers

8-8

9-1

Positive I/O Bus Interface, Block Diagram

9-2

BIOP Pulse Generator Logic

9-3

BMB Buffers/Inverters

9-4

IOP Timing Logic

9-5

ILLUSTRATIONS (Cont)
Figure No.

Title

r aye

9-5

Waveforms, IOP Timing Logic

9-7

9-6

Data Gating Logic

9-9

9-7

Skip Logic

9-10

9-8

Timing, Skip Logic Application

9-11

10-1

Data Break Interface, Block Diagram

10-2

CP Register Control Logic

10-3

Cycle Select Logic

10-5

10-4

Timing, Register Control and Cycle Select Logic

10-6

10-5

Priority Logic

10-7

10-6

BKMA Register Logic

10-9

10-7

Data Transfer Logic

10-11

10-8

Word Count Overflow and EMA Register Logic

10-13

TABLES
Table No

Title

Psino
r age

1-1

Divide Instruction Table of Combinations

1-17

1-2

1-27

1-3

EAE Combinations of DATA T and DATA F

1-29

1-4

Recommended KE8-E Spare Parts

1-48

2-1

KM8-E Extended Memory and Time-Share Option Instruction

2-7

2-2

Recommended KM8-E Spare Parts

2-25

3-1

Line and Switch Identification for ROM Addresses

3-8

3-2

Typical Error Typeout

3-13

3-3

Recommended MR8-E Spare Parts

3-13

4-1

MI8-E Bootstrap Loader Option Encoding Scheme

4-3

4-2

Recommended MI8-E (M847) Spare Parts

4-17

5-1

MP8-E IOT Summary

5-8

5-2

Recommended MP8-E Spare Parts

5-10

6-1

Recommended DK8-EA/DK8-EC - (M882/M883) Spare Parts

6-6

7-1

Recommended KP8-E Spare Parts

7-9

8-1

Connection from J1 to J2

8-1

8-2

Simultaneous Receive and Transmit Operation by Two PDP-8/E

Computers Using nterprocessor Buffer
I

8-7

8-3

DB8-E Recommended Spare Parts

8-9

9-1

KA8-E Cable Information

9-12

9-2

KA8-E Recommended Spare Parts

9-13

10-1

8271 IC Control Signals

10-5

10-2

Control Signals, Cycle, Type, and Direction of Transfer

10-12

10-3

KD8-E Cable Information

10-14

10-4

KD8-E Recommended Spare Parts

10-15

xii

PREFACE

This manual, the second in a series of three, describes nonperipheral

options of the PDP-8/E and PDP-8/M.

The content of this manual includes installation procedures, theory
of operation, and maintenance procedures for the options described.
It is

assumed that the reader is thoroughly familiar with Volume 1 of

this series, and with the applicable sections of the

PDP-8/M Small Computer Handbook.

xiii

1972 PDP-8/E &

xiv

PART 1
EXTENDED ARITHMETIC ELEMENT OPTION

CHAPTER 1
KE8-E EXTENDED ARITHMETIC ELEMENT

SECTION 1

INTRODUCTION

GENERAL DESCRIPTION

1.1

The KE8-E Extended Arithmetic Element option enables the PDP-8/E to perform arithmetic
speeds by incorporating EAE components with the existing central processor

operations at high

logic so that they operate asynchro-

nously. All logic is contained on two quad-size modules, designated M8340
and

M8341 which plug directly into
The two modules are interconnected by one H851 Connector. A second H851
Connector interconnects the M8341 to the major registers control module (Figure 1-1 ). This
connector carries register gating and
,

the OMNIBUS.

controls from the EAE modules to the register controls module.

A third H851 Connector interconnects the pro-

cessor's M8330 Timing Generator Module with the EAE control, supplying

clock and IOT functions to the EAE.

The basic OMNIBUS signals connect to each module.
1.2

SOFTWARE

The following programs are used in the maintenance of the KE8-E option.
a.

KE8-E EAE Test Part
MUYandDVI.

KE8-E EAE Test Part 2 (MAINDEC-8E-DOMB) - This program tests the MUY and DVI instructions.

KE8-E EAE Extended Memory Exerciser (MAINDEC-8E-DORA) - The KE8-E Extended Memory

(MAINDEC-8E-DOLB) - This program tests all EAE instructions except

Exerciser is a test of the KE8-E "B Mode" instructions which, during the DEFER
cycle, use the word
following the instruction to obtain the operand. The capability of each instruction
to access every

memory field from every memory field through nonautoindex and auto-index is tested.
1.3

COMPANION DOCUMENTS

The following documents and publications are necessary in the operation, installation, and maintenance
option:

PDP-8/E & PDP-8/M Small Computer Handbook - DEC, 1 972
PDP-8/E Maintenance Manual - Volume 1

Introduction to Programming - DEC, 1972

DEC engineering drawings M8340-0-1 and M8341-0-1
KE8-E EAE Test Part 1 MAI NDEC-8E-DOLB-D
KE8-E EAE Test Part 2, MAINDEC-8E-DOMB-D
KE8-E EAE Extended Memory Exerciser, MAINDEC-8E-DORA-D

e.
f.

1-1

of this

1-2

SECTION 2 INSTALLATION
The KE8-E EAE option is installed on site by DEC field service personnel.

The customer should not attempt to

unpack, inspect, install, checkout, or service the equipment.

1.4

INSTALLATION

Perform the following procedures to install the KE8-E options:
Ste P

Procedure

Remove the modules from the shipping containers.

Inspect the modules for any apparent damage.

Connect the modules as follows:
a.

Insert the EAE modules between the Timing
Generator and the CP Major Registers
and Register Control as follows:

M8330
M8340
M83 41
M8310
M8300

Timing Generator

EAE Decoder and Step Counter
EAE Multiplexers and Timing Generator
CP Major Registers Control
CP Major Registers

The five modules must be installed in this order with no vacant slots
between them
for the H851 Connectors to fit properly.
b.

Install

H851 Connectors (five total) to connect the five modules.

at the top of these modules will be utilized when all

All connectors

H851s are installed.

NOTE
The EAE is a complex instruction decoder that extends the basic PDP-8/E instruction set. It is intimately connected with the basic central processor
and relies heavily on an M8300 and M8310 in good

Many potential problems can be avoided
by running Instruction Test (MAINDEC-8E-DOAB)
and Instruction Test II (MAINDEC-8E-DOBB) becondition.

fore installing the EAE to verify the condition of the

CPU. These tests should be run again after EAE installation to verify that the EAE is not malfunctioning

and thereby modifying the basic instruction set.
1.5

CHECKOUT

Perform the following procedures to checkout the KE8-E option:
Ste P

Procedure

Verify that both EAE modules have been installed

Perform acceptance test procedures provided in Volume 1

Paragraph 2.3.

Load MAINDEC-8E-DOLB and perform EAE Test - Part I.

Load MAINDEC-8E-DOMB and perform EAE Test - Part II.
(continued on next page)

1-3

Procedure

Step

Load MAIN DEC-BE- DOR A and perform EAE extended memory exerciser (even if

4K machine).
Make entry on user's log that the acceptance test for the KE8-E was performed

satisfactorily.

SECTION 3 SYSTEM DESCRIPTION
The organization of the EAE system block diagram (Figure 1-2) follows the organization of the detailed logic
description.

The detailed logic is organized by source, route and destination and contains logic diagrams repre-

senting each block illustrated in Figure 1-2.
Signals generated within the EAE control the operation of the M8300 Major Registers

Module during EAE instruc-

TP3 and at the same time starts the
tions. The processor timing extension logic causes the processor to halt at
The EAE
Generator. This extends TS3 to enable data to be applied to the adders a number of times.

EAE Timing

selects which register is to go into the adders by asserting a combination of signals

shown in the EAE source con-

by asserting a com
What happens to the data when it is on route to
the AC Register or
bination of signals in the EAE route control signals block. The destination of the data is either
its destination is accomplished

trol logic block.

the

MQ Register.

The
The EAE was designed for hardware compatibility with old programs that were written for the PDP-8/I.
compatible
PDP-8/I
the
A
is
Mode
on.
turned
is
computer
MODE flip-flop is cleared, selecting Mode A, when the
specifically for
mode. Mode B is selected (via the mode-change instruction) only when using programs developed
this EAE.

To better understand how the EAE functions, 13 of the EAE instructions are described in terms of functional
flow to illustrate how the EAE completes each instruction.

NOTE
EAE operation is more integrated with the CPU than
most options. Before attempting to study EAE theory
of operation, the reader should thoroughly understand
CPU theory and review sections of Volume 1 as he is
reading this chapter.

1.6

STEP COUNTER LOADING OPERATION (Figure 1-3)

The Step Counter controls the number of shifts performed during the ASR, LSR, and SHL instructions. It also
required to normalize
controls the number of steps taken during MUL or DVI, and records the number of shifts
a number.

Mode
The KE8-E provides two methods of loading the Step Counter. The ACS instruction is used by the new, or
of
is
instruction
The SCL
B, instruction set; the SCL instruction is used by the old, or Mode A, instruction set.
interest because this same method of step counter loading is used within the

SHL, LSR, and ASR instructions in

both modes.
the AC
The ACS instruction takes place in a manner similar to an I/O transfer to a peripheral. The contents of
edge of
leading
At
the
cleared.
are placed on the DATA BUS during TS3. CO is grounded so that the AC will be

TP3 the five least-significant bits are loaded into the Step Counter.

1-4

•

EAE
TIMING

•

LOGIC
•

EAE ON
TG
TG2
1

EAE SOURCE
PROCESSOR
TIMING
EXTENSION

LOGIC

•

NOT LAST XFER

CONTROL LOGIC
REGISTER
ENABLE
SIGNALS

RESTART

•

I"eae instruction

•

DATA LINE

decoding logic

ENABLE
SIGNALS
MODE
•

F/F

EN
EN2
1

AC -

BUS

—»

MODE B
•DATA T

DATA
ENABLE
SIGNALS

•

ROM
AND

ENO

DATA F

ROM Z
I"eae

route control"

~*| SIGNALS

STEP

COUNTER

LAST STEP

LOG IC

EXTENDED
EAE
LOGIC

SET
•F D SET
NEXT LOC H
•

F E

•

RIGHT
LEFT

SHIFT
LOGIC

SHIFT OK

•LINK DATA

LINK
CONTROL
LOGIC

•

SKIP

LOGIC

ADLK
LINK LOAD

CARRY IN

ADLK DIS

LOGIC

SKIP

MQ CONTROL

•

"MQ ENA

LOGIC

I"£ae destination"

control signals
LOAD
LOGIC

Figure 1-2

AC LOAD

MQ LOAD

EAE System Block Diagram

The SCL instruction is somewhat more complicated. The Step Counter is to be loaded with the 1 's complement
of the next word in memory.

As soon as the instruction is decoded, the SKIP line on the OMNIBUS is grounded.

As explained in Paragraph 3.38 of Volume 1, the SKIP line is tested during IOT and OPERATE instructions.
Grounding the SKIP line causes the next location (which, in this instance, contains the data for the Step Counter)
to be skipped as an instruction.

During TS4 of the FETCH cycle, several control lines into the M8300 Major Registers Module are asserted by the

KE8-E via the H851 Connectors. These signals (ENO and CARRY IN) cause the next location in memory to be
addressed and treated as an operand (F E SET). During TS2 of the EXECUTE cycle, the contents of the five
least-significant
is

MD lines are inverted and applied to the inputs of the Step Counter. At TP2 the Step Counter

loaded.

1-5

NEW
ONLY

OLD
ONLY

ACS

SCL

TS1

TS2

SET SCLD

AT TP2 L

DATA BUS
-*SC

COL
TS3

1+SKIP

ENO

CARRY IN

TS4

(MA + 1 -* MA)
1-*E

MD^SC

TS3

TS4

1 -* F

8E-0426
Figure 1-3

Step Counter Loading, Flow Diagram

1-6

STEP COUNTER TO ACCUMULATOR LOADING OPERATION (Figure 1-4)

1.7

The contents of the Step Counter are ORed with the contents of the AC and the result transferred to the AC.

The entire operation is so similar to an IOT input OR transfer that it will not be discussed further.

THE SHIFT LEFT OPERATION

1.8

SCA
NEW: 10
OLD: 1X

The shift left (SHL) instruction (Figure 1-5) is a 2-cycle instruction.
The first cycle fetches the instruction word; the second cycle fetches
a number that specifies the number of shifts that are to occur.

TS1

The

TS2

entire operation is identical to the SCL instruction up to and including TP2 of the

SC V DATA

EXECUTE cycle.

At the start of TP3 of the EXECUTE cycle, the EAE must shift the
contents of the AC, MQ, and Link left by the number of places specified in the Step Counter.

Normal machine timing stops at TP3 and

TS3

EAE timing begins; one shift operation occurs with each clock pulse
until the last shift has been performed.

Once the EAE is on, the following signals to the M8300 are asserted:
Signal

Function

LEFT L

Enables left shift gates at output of adders.

SHL + LD EN L

Enables MQ left shift path.

ADLK DIS L

Disconnects the normal Link-AC1 1 shift

TS4

-F

8E-0427
path. Also disconnects the ACO-Link shift

Figure 1-4

path.

Step Counter to AC,

Flow Diagram

The following logic functions also occur:
Signal

MQO

MQ DATA

Function

ADLK L

Establishes shift path from MQO to AC1 1

ACO ^ LINK DATA L

Establishes shift path from ACO to Link.

MQ LOAD and LINK LOAD
added to the step count. When the step count reaches 37, the EAE starts its shut-down

negated (high) so 0 is shifted into the MQ1 1. For each shift AC LOAD,

are developed and 1

process.
If the

instruction mode is A, the EAE merely performs its last shift with

NOT LAST XFER high. The processor

restarts, and the total number of shifts is one more than the number in the second core location.

tion mode is B, a special line within the EAE, SHIFT

required to cause AC shifts, and inhibits LINK

OK H,

If the

instruc-

negated. Negating SHIFT OK H negates the signals

LOAD and MQ LOAD. Thus, the processor starts without taking

the final shift; the number of places shifted is equal to the number in the second core location.
1.9

RIGHT SHIFT OPERATIONS {Figure 1-5)

Two right-shift instructions, ASR and LSR, are available in the EAE option. The only difference between the
two instructions is how the Link is handled. The Link is loaded at TP3 of the FETCH cycle via the OMNIBUS.
If

the LSR instruction (logical right shift) is being processed, no data is placed on the LINK DATA line and thus

the Link is cleared.

If the

ASR instruction (arithmetic right shift) is being processed, ACO is placed on the LINK

DATA line and the Link is thus made equal to ACO.
1-7

ASR

SHL

LSR

TS1

TS2

ACO^ LINK DATA
ADLK DIS L.
LINK LOAD.

ADLK DIS L
LINK LOAD

(ADO-* LINK)

(0-*LINK)

TS3

ENO

CARRY IN

TS4

(MA+1
MA)

ENO

CARRY IN

{MA+1 +
MA)

WE
MD^SC
START EAE TC AT TP3.

START EAE TC AT TP3.

IF EAE ON;

LEFT L
SHL + LD EN L
ACO-^ LINK DATA
MQ LOAD, LINK LOAD

RIGHT L
MQ11 + GT DATA
MQ LOAD, GT LOAD
AC LOAD

AC LOAD

ADLK DIS MUST

ADLK DIS L
MQ0-* ADLK L

BE HIGH

TS3

RESTART CP WHEN
SC = 37
IF "NEW"

ANDSC = 37,

DISABLE SHIFT PATHS,
NO MQ, LINK, OR GT
LOAD.
TS4

Figure 1-5

SHIFT Operations, Flow Diagrams

As in the case of SHL, the computer enters the EXECUTE cycle to obtain step-count information. When the

EAE is turned on at TP3 of the EXECUTE CYCLE, the following signals are asserted:
Function

Signal

RIGHT L

Enables MQ right shift, enables right shift gates at

adder outputs.

MQ1

GT DATA

Enables path from MQ1 1 to the GT flag.

1-8

LOAD and MQ LOAD are generated for each shift and the step count is
GT LOAD is also generated for each shift, although the GT flag held cleared if it is in Mode A.

Like the SHL instruction, AC

incremented.

Notice that the Link is not loaded, and that ADLK DIS L is high. These two conditions mean that the Link is

not modified during shifting, but that the output of the Link is coupled to the input of ACO. All other details
are similar to those given for the SHL instruction.

NORMALIZE INSTRUCTION (Figure 1-6)

1.10

Normalization is the process by which the 24-bit fixed-point word in the AC and MQ Registers is converted to
floating-point format and expressed as a fraction and the corresponding power of two.

The 1-cycle NORMALIZE instruction is completely implemented during TS3 of the FETCH state. Because the

OMNIBUS signal
NOT LAST XFER L is asserted and, at TP3, processor timing comes to a halt and the EAE Timing Generator is
started. The Normalize operation only occurs if SHIFT OK H remains H, as determined by comparing ACO to
AC1 If the two are not equal, SHI FT OK H grounded, thereby causing the EAE timing to halt and restart
final shift count is important to this operation, the Step Counter is initially cleared (zeroed).

the processor timing.

As long as ACO and AC1 are equal, AC, MQ, and Link will shift one place to the left as if they were one long regis
ter, as explained for the

SHL instruction. Each time a shift occurs,

ues until the EAE finds ACO not equal to AC1

added to the Step Counter. This contin-

Another condition for which the Normalization process is ter-

minated is when AC2-MQ11 are all equal to 0 (the word cannot be normalized). The Normalization process also
terminates in Mode B if the 24-bit word in the AC and MQ equals 40000000 (only ACO is a 1); CO is grounded

during TS3 so that the AC is cleared.

111

DOUBLE-PRECISION SKIP IF ZERO (DPSZ) (Figure 1-7)

The 24-bit number in the AC and MQ is tested.

If all

bits are 0, the next instruction is skipped.

any bit is a 1,

the next instruction is executed.

NMI

TS1

TS2

TS2
0-»>SC

MQ = 0,

IF AC &

START EAE TC
AT TP3

^ SKIP

ADLK DIS L
ACO-^LDATA
SC + 1 -» SC
IF EAE ON, SHIFT
LEFT UNTIL ACO ^
AC1,OR AC1-MQ11
= 0.

WHEN NORMALIZED,
RESTART CP.
IF "NEW" & AC,

MQ = 40000000,
CO L.

1->F

1 -*

8E-0428

Figure 1-6

8E-0429

NORMALIZE Operation, Flow Diagram

Figure 1-7

1-9

DPSZ Instruction, Flow Diagram

1.12

DOUBLE-PRECISION COMPLEMENT (DCM) (Figure 1-8)

The objective of the DCM instruction is to form the 2's complement of the 24-bit word in the AC and MQ. Since
the M8300 Major Registers Module is capable of only 12-bit arithmetic, the complete DCM operation requires

two passes through the adders. These passes are labeled Step 1 and Step 2 in Figure 1-8 and in the following
paragraphs.

The entire operation takes place in the FETCH cycle.

The DCM instruction uses the SWP instruction built into the M8310. (One requirement of the DCM instruction

MQ -> AC path, and bit 7, controlling the AC MQ path, both be 1s.) Thus, as the
DCM instruction decoded, the M8310 causes MQ BUS L and AC -+ MQ ENA L (described in Volume Paragraph 3.40). At the KE8-E, two other lines to the M8300 are being controlled. These lines are DATA F L, which
asserted for both operations and CARRY IN L, which
unconditionally asserted for Step
and asserted
Link
for Step 2. The KE8-E also disables normal Link gating and places CARRY OUT L from the adders onto the
LINK DATA L line of the OMNIBUS. The Link, AC, and MQ are loaded at the conclusion of each step. (AC
LOAD and MQ LOAD occurs at the end of Step because of the SWP portion of the instruction.) The processor's
is that

bit 5, controlling the
is

is 1

timing chain is stopped and the EAE's timing chain is run for one step to provide the extra time and load pulses
for Step 2.

One of the more severe tests of the DCM instruction is to perform this operation on a cleared AC and MQ, since
such a task requires the carry to propagate through all 24 bits.

1.13

DOUBLE-PRECISION INCREMENT (DPIC) (Figure 1-9)

The DPIC instruction adds 1 to the 24-bit word in the AC and MQ in the same manner as the DCM instruction.
The only difference is that DATA F L is not asserted, allowing the contents of the DATA BUS to be applied to
the adders without being complemented.

TSl

TS2

AC-+MQ, MQ-*AC
BECAUSE OF INSTR.

ADLKDISL
CARRY IN
CARRY OUT ^LINK DATA.
DATA F
[MQ LOAD, AC LOAD]
LINK LOAD.
START EAE TC, ONE CYCLE.

AC-»MQ,MQ-»-AC
BECAUSE OF INSTR,

COMMON TO
BOTH STEPS

ADLK DIS L
CARRY IN
CARRY OUT-* LINK DATA
STEP 1
TS3

[MQ LOAD, AC LOAD]
LINK LOAD

START EAE TC, ONE
CYCLE ONLY

L SCARRY IN

CARRY OUT-> LINK DATA
DATA F

SCARRY IN

CARRY OUT -* LINK DATA

STEP 2

AC LOAD,

MQ LOAD

LINK LOAD

LINK LOAD.
1

TS4

- F

1->F

8E-0430
Figure 1-8

DCM Instruction, Flow Diagram

Figure 1-9

1-10

DPIC Instruction, Flow Diagram

DOUBLE-PRECISION STORE (DST) (Figure 1-10)

1.14

The contents of MQ and AC are stored at the double-precision location (two consecutive memory locations). The
AC, MQ, and Link are not changed by this instruction. When the EAE decodes the DST instruction (Figure 1-10),
the next location is accessed in a manner similar to the SCL instruction.

Instead of grounding F E SET, however,

the DST instruction grounds F D SET, thereby causing the computer to enter the DEFER major state and treat
the next location as an address.

At the conclusion of the DEFER cycle, the computer enters the EXECUTE CYCLE. Simultaneously, a flip-flop
within the EAE sets. This flip-flop (EX1 ) grounds F E SET, causing the processor to perform two consecutive

EXECUTE cycles and forcing MA + 1 -> MA at the end of the first EXECUTE cycle. EX1 is cleared at the end of
the first of these EXECUTE cycles, allowing normal processing to resume at the conclusion of the second

EXECUTE.
During each of the EXECUTE cycles, the following processor signals are asserted during TS2:
Signal

Function

MORBUS
DA T Q T

}

Gates MQ Re 9' ster to MB-

MD DIS

Removes the MD, which is normally applied to the

MB via the adders.
(AC-* MQ ENA L is also grounded, but has no effect since the MQ is not loaded at TP2.)
During TS3, the usual gating is set up to swap the contents of the AC and MQ. Hence, the sequence of events
during the EXECUTE cycle is:

1/15

Store the least-significant twelve bits, presently in the MQ.

Swap the AC and MQ.

Address the next memory location.

Store the most-significant twelve bits presently in the MQ.

Swap the AC and MQ to return the bits to their original locations.

DOUBLE-PRECISION ADD (DAD) (Figure 1-11)

The DAD instruction has many similarities to the DST and DCM instructions. Like the DST instruction, it uses a
second memory word as a deferred address.
secutive memory locations.

EXECUTE cycles to obtain data from two conThe DAD instruction handles its carry to and from the Link in a manner similar to
It

also requires two

the DCM instruction.

During TS3 of the FETCH cycle, ADLK DIS is grounded, enabling the OMNIBUS LINK DATA and LINK LOAD
inputs.

At TP3, LINK LOAD is generated. Since no data was placed on LINK DATA, the Link is cleared. Other

than clearing the Link, the DAD instruction process is identical to that of the DST instruction for the first two

machine cycles.
During each of the two EXECUTE cycles, a word is obtained from memory and applied to the adders via the MD
lines.

During TS3, the output of the Link is applied to the carry input of the adders. The contents of the MQ

are gated to the other inputs to the adders.

The carry output of the adders is applied to the LINK DATA input

1-11

DST

TS1

TS2

TS3

DAD

TS1

TS2

TS4

ENO
CARRY IN

{MA + 1 MA)

ADLK DIS L
LINK LOAD
(O^L)

1-»EX1

MQ-BUSl
DATAT >
MDDIS

TS3

MQ-+MB

MQ-*BUS
AC -* MQ ENA L
AC LOAD {SWAP AC,
MQ, LOAD MQ)

^SKIP

ENO

(MA+1 MA)

CARRY IN
1

ENO
TS4

CARRY IN
1

-* E

TS1

TS2

SAME AS E1
L-*-

CARRY IN

EN1 (MD)

SAME AS E1

MQ** BUS

AC-*MQ ENAL
CARRY OUT •+ LINK DATA
AC LOAD
MQ LOAD
LINK LOAD
ADLK DIS L
TS3

ENO L

CARRY IN L
1

TS3

TS4

SAME AS El

8 E-0424

Figure 1-10

DST Instruction, Flow Diagram

Figure 1-11

1-12

DAD Instruction, Flow Diagram

of the Link; the path from the AC to MQ is enabled. At TP3 the AC, Link, and MQ are loaded. Hence, the
old AC is moved to the MQ, while the sum of the old

MQ and the MD

loaded into the AC.

The Link provides

and receives carry information.

1.16

SUBTRACT AC FROM MQ (SAM) (Figure 1-12)

The SAM instruction subtracts AC from MQ and places the result in
the AC, Link, and GT flag. The

not modified. The entire op-

eration takes place during the FETCH cycle.

The MQ is gated to the adders by grounding source control lines ENO
and EN2 at the H851 Connectors. As listed in Table 3-4 of Volume 1,
the

ADLK DIS L
DATA F
CARRY IN
ENO L

MQ Register

is gated

to one of the sets of adder inputs.

the DATA BUS by grounding AC -> BUS, DATA F, and CARRY IN.

MQ-»-

EN2L J ADDRESS
CARRY OUT-* LINK
DATA

A "Greater Than" signal is generated and applied to the GT flag. The
carry from the address is applied to the Link inputs.

[AC LOAD]

The AC, Link,

and GT are loaded, completing the operation.

LINK LOAD

GT GATING EN A
GT LOAD

The "Greater Than" signal is derived as follows:
a.

MQ and the old AC are of different signs, the MQ
less
positive. The MQ
greater than the AC
the MQ
than the AC
the MQ
negative.
If the

8E-0422
b.

Figure 1-12

The AC

complemented and introduced to the other set of adder inputs via

the

MQ and the old AC are of the same sign, the MQ

greater than (or equal to) the old AC if the output of the

SAM Instruction,

most-significant bit of the adder is positive. Otherwise, the

Flow Diagram

less than the AC.

Logic at the input of the GT flag computes the "Greater Than" signal.

1.17

MULTIPLY INSTRUCTION (MUY) (Figure 1-13)

The MUY instruction combines the multiplicand (which was previously loaded into the MQ Register) with a multiplier

(obtained from memory by the

MUY instruction), using the rules of binary multiplication. The result

AC and MQ. The multiplication requires twelve (decimal) steps which are counted by the Step Counter.
the multiplier is added to the AC. Regardless of the state of MQ1
is a
At each step, MQ1 is examined. If
the AC and MQ are shifted right in the same manner as is done for the LSR instruction, except that the GT flag
repeated for the new MQ1 until the twelve steps have been completed. At
is not loaded. This same process
this point, the AC and MQ contains the 24-bit product.
left in the

The MUY instruction requires one FETCH cycle to fetch the instruction, one DEFER cycle (Mode B only) to
obtain the multiplier address, and one EXECUTE cycle to obtain the multiplier and accomplish the multiply
operation.

The decoded instruction clears the Step Counter and places a 0 in the Link by asserting ADLK DIS L and LINK

LOAD L.

then accesses the next location in memory (refer to SCL instruction).

patible, Mode

A instruction set

If the older,

in use, the next sequential address contains the multiplier.

grounds F E SET L and goes directly to the EXECUTE cycle.

PDP-8/I com-

The EAE, therefore,

EAE is in Mode B, F D SET L is grounded
multiplier.
At the conclusion of the DEFER
of
the
and the processor enters the DEFER state for the address
cycle, the processor automatically enters the EXECUTE state.

1-13

If the

During the first part of the EXECUTE cycle, the multiplier is read

onto the MD lines. At TS3, NOT LAST XFER L is asserted on the

OMNIBUS; at TP3, processor timing halts. The EAE timing chain is

TS1

then started. The right-shift signals are asserted (refer to the LSR in-

TS2

struction for further details). Each time MQ1 1

by the EAE.

a 1, EN1

grounded
o-»sc
LINK LOAD (0 - L)

EN1 is ground, ENO is grounded by the M8310 Major

Registers Control Module.

ADLK DIS L

Grounding EN1 and ENO causes the word

on the MD lines to be added to the partial product. This process continues for the twelve steps necessary to complete the multiplication.

The last step is made with NOT LAST XFER high, causing the processor to resume its timing.

The data paths for the MUY instruction are illustrated in Figure 1-14.
1

^SKIP

This figure also illustrates the control signals that must be enabled to

^(MA+1^MA

ENO

make this instruction possible.

CARRY INJM)
NEW: 1 - D
OLD: 1 -* E

DIVIDE INSTRUCTION (DVI) (Figure 1-15)

1.18

There are two common methods of doing binary division:
Restoring divide (the standard long-hand method):

subtract.

If the result is

+, place a 1 in the quotient.

AC -» BUS L
START EAE TC AT TP3
IF EAE ON, RIGHT L
IF MQ11 = 1; EN 1 L,
AC LOAD,

Try to
If the

result is - , the subtraction does not take place; place a 0 in

the quotient.

In either case, shift left.

MO LOAD.
REPEAT 12 TIMES.
RESTART CP WHEN

Nonrestoring divide (the method used in PDP-8/E): Always

make the subtraction and always shift left.

SC = 13 8

the result is +,

ADLK DIS MUST BE

place a 1 in the quotient; the next step will also be a subtract.

If the result is

HIGH.

-, place a 0 in the quotient; the next

step will be an add. This method requires a final correction
step if the final remainder is -.

Figure 1-15 illustrates the DVI Instruction. This instruction requires

one FETCH, one DEFER (Mode B only), and one EXECUTE cycle.

The instruction clears the Step Counter at TP3 of the FETCH cycle.
The next memory location is accessed, as explained for the SCL instruction.

TS4

-F

the instruction mode is B, the CPU must obtain the op-

erand address by entering the DEFER major state. Otherwise, the

CPU goes directly into the EXECUTE state.
The first subtraction takes place at TP3 of the EXECUTE cycle, before the

EAE is turned on. At the same time, the Link* is set. The

Figure 1-13

MUY Instruction/

Operation, Flow Diagram

EAE is turned on only if there is a carry from the most-significant bit of the adder. Otherwise, a condition known
as divide overflow exists, and the quotient cannot be contained in the 12 bits available. If the EAE is turned on,
the last divide step clears the Link. Thus, the Link is used as a program flag to indicate whether or not divide

overflow occurred.

*Link refers to Processor Link, DIV LIMK refers to EAE Link.

1-14

MAJOR REGISTER BUS

ADDER OUTPUT
MULTIPLEXER

CARRY OUT

RIGHT L

CARRY IN

ADDERS

•

DATA CONTROL
GATES

ENO L

MULTIPLEXER

EN1 L

DATA T L
DATA F H

7S
DATA BUS

ADDER

MAJOR REGISTER BUS

Figure 1-14

MQ
1

MUX

RIGHT L

MUY Instruction Data Paths

The Major Registers are shown in Figure 1-1 6. This figure, an expansion of Figure 3-79 of Volume 1 shows the
,

signals that are important to the divide process.

Notice that the M8300 has no provision for complementing the

MD. The only means of complementing is via the data control gates which are in the AC shift path. In order
-* AC. The AC now contains the complement of the result. Successubtract, the KE8-E must cause AC plus MD
-*
AC, since the AC is already in complemented form. To change from
sive subtractions merely cause AC plus MD
to

subtraction to addition, the KE8-E must cause AC plus

AC. Of course, successive adds are performed by

AC. Complementing is accomplished by grounding DATA F, and must be performed each time
first two divide steps
the quotient bit changes. The logic merely grounds DATA F if MQ10 * MQ1 1 after the

AC plus MD

have established quotient bits in MQ10 and MQ1 1

DATA F

grounded for the first two steps.

As explained above, AC may be in its true or complemented form as the divide operation progresses.
always in its true form, and is the source of unprocessed dividend bits that are shifted into AC1 1

The MQ is

If the

word

shifted into AC1 1
being loaded into the AC is in complemented form, MQO must be complemented as it is
logic merely examines MQ1 1

If it is a 1 ,

MQO

is complemented as it is shifted into AC1 1

The fundamental rule governing the quotient bit is as follows:
If the sign

If the

of the dividend does not change, MQ1 1 -> MQ1 1

sign of the dividend changes, MQ1 1

MQ1 1

But the sign might have changed because the logic grounded DATA F, so the fundamental
must be expanded to:
If

DATA F H and no sign change, or if DATA F L and the sign changes,
MQ11 -+MQ11.

1-15

The

DATA F H and the sign changes, or
MQ11 ^MQ11.

DATA F L and no sign change,

Since DATA F L is caused by MQ10 ¥= MQ1 1, a little Boolean manipulation yields:
If

MQ10 = 0 and no sign change, or if MQ =

MQ10 = 0 and the sign changes, or if MQ10 =

and the sign changes, 0
1

and no sign change, 1

MQ1 1
MQ11.

The sign change is derived from DIV LNK (the AC sign bit after the shift) XORed with

CARRY

OUT. All combinations of MQ10, MQ1 1 D V LNK and CAR R Y OUT are shown in Table 1 -1
,

together with the resulting quotient bit.

TS1

TS2

ENO
\ (MA + 1 + MA)
CARRY IN J
NEW:
OLD:

1-*D
1-*E

TS1

TS2

DIVISOR -t-MD LINES

AOLK DIS L
SHL+LD ENAL
AC -* BUS L

ASSERTED FOR ENTIRE TIME STATE

LINK DATA L
DATA F L

E TS3 EAE ON (FIRST STEP DIVIDE OVERFLOW TEST)

DVI

EN1 L
0-* MQ DATA

LEFT L

SET LINK, MAKE

MOO*-* ADLK

FIRST SUBTRACTION.
IF NO CARRY, ENTIRE
OPERATION ABORTS
BECAUSE OF DIVIDE

LINK LOAD

AC LOAD

MQ LOAD
IF

CARRY OUT L: STOP CP,

OVERFLOW

START EAE TIMING
IF SC ^ 12, LEFT L

IFSC = 0OR IFMQ11 * MQ10,

DATA F L
MQO XOR MQ11 -+ ADLK L
EN1 L

ADO - DIV LNK DATA
DIV LNK XOR CARRY OUT
XOR MQ10- MQ DATA L
AC LOAD
MQ LOAD
DIV LNK LOAD

EAE ON — NORMAL DIVIDE
STEPS (12 TOTAL)

LEFTH
IF MQ10 = 1,

DATA F L

IF MQ11 =0, EN1 L
LINK DATA H

SC= 13- DIVIDE CORRECTION

AC LOAD
LINK LOAD

RESTART CP

1- F

Figure 1-15

DIVIDE Instruction, Flow Diagram

1-16

MAJOR REGISTER BUS

DIV LNK
(

KE8-E)

ADO

ADDER OUTPUT
MULT PLEXER

LEFT L

ADDERS

CARRY IN

CARRY OUT

DATA CONTROL *
GATES

MULTIPLEXER

DATA T
DATA F

DATA BUS

DATA LINE MUX *

AC LOAD

MAJOR

•

—

»*BUS

MQ LOAD
MQ DATA

SH L

Figure 1-16

Major Registers

Table 1-1
Divide Instruction Table of Combinations

What goes in-

MQ10

MQ11

DIV LNK

CARRY OUT

DATA F

0
0

H
H
H
H

0
0

to MQ11
(MQ DATA)

yes

0
0

yes

H
H
H
H

hJ
1

SIGN CHANGE

l—*XOR«*_l

1—

fcYOR

1-17

Step

Carry

Link

Accumulator

Multiplier Quotient

000 000 000 000

000 010 010 001

111 111

I'll

Counter

ACT -ADDERS (FIRST STEP)

111

000 000 001 100
ooo ooo ooi oi r
ooo ooo oio ii

ill 111 101 000
000 000 001 100
n in no ioo^
11 ill 101 000

Comments

MD
000 100 100 010

00 000

001 001 000 100

00 001

ADDERS

MQO-*AC11

/
11 111 101 000
000 000 001 100
11 111 110 100^
11 111 101 000

AC
010 010 001 000

ADDERS (MQ10= MQ11)

00 010

/
11 111 101 000
000 000 001 100
11 111 110 100j
11 111 101 000

100 100 010 000

n in ioi ooo
000 000 001 100
u ui no loo
11

111

ioi

oo/

001 000 100 000

00 100

/
11

ill 101 001

000 000 001 100
11

111 110 101-

111 101

oio'

010 001 000 000

00 101

/
11111 101 010
000 000 001 100

inn no noii

in ioi ioo

oo no

100 010 000 000

m
mm

ioi ioo

000 000 001 100
n
ooo j
11

111

110001

oo in

000 100 000 000

/
n in noooi
000 000 001 100
11 111 111 TOT.
11 111 111 010

001 000 000 000

111 ill 111 010
000 000 001 100
000 000 000 110,,
000 000 001 100

010 000 000 001

01 001

000

in in noon

AC^ADDERS (MQ10^MQ11)

000 000 001 100

m in in in.
in in m in

100 000 000 011

01 010

AC
ADDERS (MQ10 = MQ1
MQO AC1 1 (MQ11 = 1)

in in in in
000 000 001 10 0
666 000 601 01
000 000 010 110*

ooo ooo ooo no

AC -> ADDERS (MQ10 =£MQ1 1)

111 111 101 001

000 000 001 100

m in

116 ioi.

in in no lor

000 000 001 100

01 100

Since SC = 1 5g, MQ1 0 = 0, and MQ1 1 = 0;

in in no ioi
000 000 001 100
000 006 660 001,
ooo ooo ooo oor

Figure 1-17

MQ plus AC -+AC

(Divide Correction).

000 000 001 100

01 101

NO SHIFT

Divide Example - Divides 221 8 by 14 8

1-18

Thirteen divide steps take place (the first step tests for divide overflow; the next twelve steps determine the
quotient).

A final remainder correction step is made as the CPU is restarted and the Link is cleared. For the
the last regular divide step was a subtract. The
If MQ10 =

correction step, the left-shift signals are all negated.

AC is in complemented form before the correction step; hence DATA F must be grounded to re-complement the

AC to its true form as a part of the correction process.

MQ1 1 = 0, the divisor must be added to the remainder

(this is the correction step mentioned in the first part of this section).

Figure 1-17 shows an example of the division process.

SECTION 4 DETAILED LOGIC
1.19

EAE INSTRUCTION DECODING LOGIC

The EAE instruction decoding logic consists of the EAE Instruction Register (E R), the MODE flip-flop, and
ROM 1 and ROM 2. The decoding logic recognizes EAE commands from the processor and interprets them in
I

terms of EAE instructions.

1.19.1

EIR Register

The EIR Register (Figure 1-18) comprises 12 D-type flip-flops (IC 74H74).

It is

loaded at TP2 of the FETCH

major state with the 12 Memory Data bits (MD0-11) and provides outputs of EIR N(1) or EIR N(0), where N
corresponds to the EIR bit designation. The most active EIR bits correspond to bits MD7-10 and play a dominant role in the EAE coding scheme.
all

flip-flops are cleared at TP4.

1.19.2

If the

system is about to answer an interrupt and is not doing a data break,

Otherwise, the flip-flops are cleared at TP1 of FETCH.

MODE Flip-Flop Logic

The MODE flip-flop (Figure 1-19) comprises one J-K flip-flop (IC 74H106) which responds to SWAB and SWBA
instructions. Two modes of operation were designed into the EAE to accommodate the user having programs
that were written for a PDP-8/I or to accommodate the new user.

Mode A corresponds to the PDP-8/I type soft-

ware; Mode B corresponds to the new instructions that are provided. The EAE always starts in Mode A. The

MODE flip-flop allows the programmer to switch modes at his convenience. The flip-flop

clocked at the trail-

ing edge of TP2 whenever the basic EAE instruction in a FETCH state is decoded.

1.19.3

ROM Logic

The ROM logic (Figure 1-20) consists of two ICs, each containing a 32 8-bit word capability and selected by the
combination of 5 inputs.
Figures 1-21 and 1-22 illustrate

ROM operation. ROM

enabled during either a FETCH or EXECUTE cycle,

when an EAE instruction has been decoded and the instruction is not a mode-swapping instruction.

ROM 2

enabled during a FETCH cycle, when an EAE instruction has been decoded and the instruction is not a mode-

swapping instruction. Each EAE instruction can be easily traced to eight output ROM signals, each representing
a specific command to somewhere in the

EAE logic. An indication of what each output is doing and where it is

going can be seen at the bottom of each matrix.

For the purpose of ROM decoding a 0 can be considered active

and function as a 1 in normal logic terminology. For example, ROM 26 L causes an MA plus 1 to the MA. The
specific EAE instructions causing this

ROM instruction can be seen on the matrix.

1-19

1-20

oEIR4 (0)

»-3V

EIR5 (0)

•

SWAB L

EIR6 (1)
7447

MODE B H

MODE

IN IT H

—n

EIR7 (0)

EIR8 (0)
EIR9 (1
EIR10 (1)

EIR4 (0)

EIR5 (0)

SWBA L

EIR6 (0)

Z>M>

EIR7 (1)

7431 <

EIR8 (1)
EIR9 (0)
EIR10 (0)

EIRO (1)
EIR1

EAE INST

(1)

EIR2 (1)

CLOCK MODE F/F

EIR3 (1)
EIR11 (1)

FETCH
TP2

Figure 1-19

1.20

MODE Flip-Flop Logic

EAE TIMING LOGIC

through
The EAE timing logic is illustrated in Figure 1-23. The components consist of six D-type flip-flops, TG1

TG1

TG4, an E SYNC flip-flop, and an EAE ON flip-flop, plus a variety of control and input gates. Flip-flops
clock major
through TG4 are configured as a switch-tail ring counter. TG2(1), TG3(1) and TG4(0) are used to
Pulse),
Time
(EAE
ETP
form
to
combined
L
are
LandTG3(1)
events in the EAE logic. For example, TG2(1
)

which is the primary clock pulse to step the Step Counter and load registers.

The length of the switch-tail ring counter is controlled by ROM 12 L, which indicates whether an add

(and

the EAE Timing Generator
possibly a shift) or merely a shift operation is taking place. If adds are taking place,
Registers Module.
must run at a slower rate to allow time for carries to propagate in the adders of the M8300 Major
required to
are
pulses
clock
Six
into
TG2.
(complemented)
If ROM 12 L is high, TG1 is disabled and TG4 shifts
If
ROM
12 L is
complete the timing generator cycle; hence, ETPs are 300 ns from leading edge to leading edge.
leading edge.
low, TG1 is in the Shift Register. The ETPs are then 400 ns from leading edge to

1 .20.1

EAE Timing Generator Timing Diagram

A timing diagram (Figure 1-24) relates the transition from processor timing to EAE timing. The signal NOT LAST
XFER L, which is grounded when the processor is to stop, is not shown on the diagram (refer to Paragraph 1 .25
at TP2D; at the leading edge of
for information on the EAE start/stop logic). NOT LAST XFER L is asserted

1-21

TP3, processor timing halts. The EAE Timing Generator operation begins on the leading edge of TP3, which dc

SYNC flip-flop. EAE timing begins when flip-flop EAE ON is set; the timing chain is started on the
next 20-MHz clock input from the processor timing generator. The first ETP occurs when TG4 is set and TG2

sets the E

is reset.

ETP occurs once every 300 ns or 400 ns (depending upon ROM 12 L) and continues as long as LAST STEP, or

SHIFT OK, or DCM + DPIC is not low. Any one of these signals will cause a 0 to be clocked into the E SYNC
flip-flop, thus beginning a series of events that ends the

EAE timing and restarts the processor timing.

Each time an ETP is generated by timing, the Step Counter is stepped one more time until the total number of
shifts have been completed.

FETCH
EIRO(1
EIR1 (1

EIR2{1
EIR3(1
EIR1K1

SWBA L
SWAB L
EAE INSTRUCT

ROM 11 L
Y1

ROM 12 L
Y2
14

NEW
EIRO (1

ROM 13 L
Y3

INSTRUCT H
13

)

MODE B

ROM 14 L
Y4

EIR8 (1

)

EIR9 (1

)

ROM

ROM 15 L

ROM 16 L

ADLK DIS L

EIR10

)

( 1

ROM 17 L
Y7

ROM 18 L
Y8

FETCH L

SWAB L
SWBA L

ROM 21 L
Y1

ROM 22 L
Y2

MODE (0)

•

ROM 23 L
Y3

EIR6 (1)

ROM 24 L
Y4

EIR8(1

)

EIR9 (1

)

EIR10 (1

)

•

ROM 2

ROM 25 L
Y5

ROM 26 L
Y6

ROM 27 L
Y7

F D SET L

ROM 28 L
Y8

F E SET L
8E-0440

Figure 1-20

1.21

ROM Logic

EAE SOURCE CONTROL SIGNALS

EAE demands on the processor are more extensive than most other options. Data can be selected from the AC,
MQ, MD, MB, PC or from the CPMA Register. How the data is selected and its source are illustrated in Figure
1-25.

The AC or the MQ can be applied to one set of adder inputs via the DATA BUS. The MD, MQ, PC, or

the CPMA Register can be applied to the second set of adder inputs.

1-22

FUNCTION
00
01

02
03

NOP

F-

F • (ACS

+ SCL)

F« MUY
F» DVI

F- NMI
F- SHL
F- ASR
LSR
F

F •

04
05
06

12
13

14
15
16
17

371
Q7
d/7

•0

i
l

OCTAL
377
377

143
377
171

371

377

371

37 7

377

•

0
0

1
1

377
231
231
331

n
u

0
o

377
376
267

241

•

0
0

NOP
SCL
MUY

•

24
25

NOT USED
E
SHL
ASR
E
E
LSR

•

34
35
36

1
1

32
33

1
1

•

1
1

F-DPSZ
DPIC
F
F
DCM
F • SAM

22
23

NOP

•

F- DAD
F- DST

III

SCA

Y.3

NOT USED
DAD
E
E
DST
NOT USED

•

NOT
NOT
NOT
NOT

142
366
366

USED
USED
USED
USED

X
X

LU CH
_J«cC

0.0

Figure 1-21

331
377

ROM

1-23

Instructions

FUNCTION

0
0

NOP
ACS
NEW MUY
NEW DVI

NMI

SCA
DAD
OST
NOP

NOP
SCL
OLD MUY
OLD DVI

SCA
SCA- SCL

SCA-OLD MUY
SCA.OLD DVI

SCA • NMI
SCA • SHL
SCA - ASR
SCA • LSR

Y8
>

1
1

DPSZ
DPIC
DCM
SAM

SHL
ASR
LSR

NMI

1
1

0
0

0
0
0

0
0

Figure 1-22

ROM 2 Instructions

1-24

OCTAL
377
177
331
331

337
372
372
372

367
371
371
377

357
277
277
277

377
372
332
332

337
372
372
372

367
362

322
322

327
362
362
362

-I

1-25

o
o

-UJ

zz
-< — UJ
UJ(- CD

<£
UJ

1-26

ADDER
OUTPUT MUX

ADDERS

DATA

ENO

EN1

EN2

•

DATA T

•

DATA F

CONTROL GATE

•

DATA BUS

MD Me

DATA LINE

MUX

30
AC

Figure 1-25

1 .21 .1

AC— BUS
MQ— BUS

Source Control Data Path, Simplified Block Diagram

determine what
The processor register selection logic is illustrated in Figure 1-26. Signals ENO, EN1, and EN2
the decoding
by
illustrated
is
selected
is
that
data
data will pass through the Register Input Multiplexer. The

scheme shown in Table 1-2.
Table 1-2
Register Select Decoding Scheme

ENO

EN1

EN2

low

PC Register (not selected
by KE8-E)

low

high

MD Lines

low

high

low

MQ Register

low

high

CPMA Register

NOTE
When EN1 is grounded by EAE, gating within the
M8310 Major Registers Control automatically grounds
ENO. Thus, the EAE need only ground EN1 to select

MD to the adders.

1-27

P/0 MAJOR REGISTER LOGIC
8235
E20

EIR3 (1)

MD DISABLE

12
•

EN1

TS2-

DST4-DA0

DCA«E«TS2

L
EIR10 (1

ENO

)

8235
E20

DAD+DST
BTS3

zry
J
1

+ 3V

8235
E27
MQ11 L

NORMAL DVI

BTS3

LAST STEP L

LAST DVI

8235

MQ11 L-

E31

ROM 12 L
EAE ON (0)

ROM 15 L
MS, IR DIS

-L>

^=^~~) MUY.EAE
ROM

14 L

ON L

note:

NEXT LOC H
TS4

—q

X>i_
'

EN2

+ 3V
IR10 (1)

eir9 (D

—H—^y

^ SAM

8235

ROM 22
TS3

Figure 1-26

Logic Summary:

If pin 7 is low, the A inputs
are inverted and connected to
the outputs. If pin 9 is low,
the B inputs are connected to
the outputs. Outputs are
open- collector.

Processor Register Selection Logic

1-28

1 .21 .2

Data Line Enable Signals

As illustrated in Figure 1-25, signals AC -> BUS and MQ -+ BUS are used to gate either the contents of the AC

MQ Register to the DATA BUS. The generation of these two signals shown in Figure 1-27.
Signal AC-» BUS occurs during ail shift instructions, including MUY and DVI, as dictated by signal ROM 15 L
during TS3. Signal MQ ^ BUS
asserted by E and NEW INSTR. E and NEW INSTR also generate AC^ MQ
EN A L. This arrangement automatically transfers the contents of the MQ Register to the DATA BUS and the
contents of the AC Register to the MQ. The DAD and DST instructions follow this procedure. There are other
times (DCM and DPIC) when MQ -> BUS and AC ^ MQ L are asserted, but these situations are handled in the
M8310 by the MQA and MQL bits (refer to Volume 1).
Register or the

+ 3V

•

MQ—*BUS L

8235

BTS3

NEW INST

TS3

8235

ROM 15 L

—BUS

Logic Summary:

If pin 7 is low, the A inputs
are inverted and connected to
the outputs. If pin 9 is low,
the B inputs are connected to
the outputs. Outputs are
open-collector.

Figure 1-27

1 .21 .3

Signals

Data Line Enable Signals

Data Enable Signals

DATA T and DATA F allow data to move from the DATA BUS to the adders. The type of data being

applied to the adders is illustrated in Table 1-3.

Table 1-3

EAE Combinations of DATA T and DATA F
Signal

Type of Data Applied to Adders

DATAT

DATA F

low

Complement of contents of DATA BUS

low

high

Contents of DATA BUS

high

low*

Zero

DATA F

grounded by a gate in the M8310 Register Control if DATA T is high.

1-29

The data usually placed on the DATA BUS by the EAE option will be the contents of the AC Register or the

MQ Register. Signals DATA T and DATA F can be asserted by either the Major Registers Control logic or the
EAE data control logic (Figure 1-28). Signal DATA T is brought low during TS2 when a DAD + DST instruction
is being executed during an EXECUTE cycle. However, DATA T is also brought low during TS3 of all EAE cycles,
as described in Paragraph 3.35.3 of Volume 1

DATA F is pulled low by a SAM, DCM, or DPIC instruction during TS3. During a normal DVI, DATA F is low
if

MQ10 and MQ1 1 are alike. During the last divide step (the correction step), LAST STEP L tests MQ10 for a 1

8235
E20

EIR10 (1

)

M8310 REG. CONTROL

f+OPR

[

BTS3

— —=M^C>
O

—

MQIO L

\ ~

i€>i
BTS3 -

8235
E27

ORMAL DVI

DVI -

LAST STEP L

8235

ROM 22

EIR10H)

TS3

ON FOR SAM OR DCM

Figure 1-28

1.22

Logic Summary;

If pin 7 is low, the A inputs
are inverted and connected to
the outputs. If pin 9 is low,
the B inputs are connected to
the outputs. Outputs are

open-collector.

EAE Data Control Logic for Processor Data Control Gates

EAE ROUTE CONTROL SIGNALS

The EAE route control signals control shifting right, shifting left, carry in, and carry out. These elements are
represented in the simplified block diagram given in Figure 1-29.

1.22.1

Step Counter Loading and Control Logic

The Step Counter loading and control logic is illustrated in Figure 1-30. The logic controls loading, reading, and
incrementing the Step Counter.

1-30

I— CL

Q
-XL

O
o

2
c
o

o
DC
LU

1-31

TP2 D
18

L—3

~
SC LOAD L

-CO L

TP3

0
C

DATA
XFER

+ 3V
D

DATA

TP3

HL>

J~V°-sc

ROM 23 L—d

(

TG2

(

1>=

j—^ ETP

ROM 21 L

TG3

SC H

^V ^

SHIFT °* H
~]

ROM ,5 L

SHIFTS

L>- '+

TS3
ROM 25 L

d
J

C |_

J
)

— DATA H
8E-0432

Figure 1-30

Step Counter Loading and Control Logic

Two sources of data (the AC and MD) can be loaded into the SC by two different instructions. If the last five bits
of the AC are to be loaded into the Step Counter, the ACS instruction generates ROM 21 L, which sets the DATA
XFER flip-flop at TP2. Because ACS is a Mode B instruction, MODE B H and DATA XFER (1) H generate CO L
and DATA XFER (1) asserts SC LOAD L. Signal CO L is used to clear the AC Register at the same time the SC
is loaded. Signal DATA
SC H is used to gate the contents of the DATA BUS to the Step Counter. At TP3,
DATA XFER is cleared and the SC is loaded.
If

an SCL, SHL, ASR, or LSR instruction is decoded and the major state is EXECUTE, ROM 18 L is asserted. At

TP2D, SC LOAD L is asserted, which causes the complement of the last five MD bits to be loaded into the Step
Counter. Signal +1

ROM 15 L

SC L is generated at EAE Timing Pulse (ETP) time by SHIFT OK H and ROM 15 L.

decoded when a shift operation is to take place.

When it is desired to load the AC Register with the contents of the Step Counter, instruction SCA asserts ROM 25 L.
During TS3 L, SC -* DATA H is asserted, gating the contents of the Step Counter to the DATA BUS.
1.22.2

Step Counter Logic

The Step Counter logic is illustrated in Figure 1-31. IC 8266 transmits the complement of DATA 7 through 1
and the uncomplemented MD bits. When signal DATA -» SC goes high, the DATA BUS bits (low for 1

)

are ap-

plied to the Step Counter (high for 1). Otherwise, bits MD7-11 (low for 1) will be complemented and applied to

the Step Counter (high for 1).

The Step Counter loads the contents of the four input lines when SC LOAD L is

received and increments when it receives the signal +1 -* SC L.

to count up to zero.
Signal

The Step Counter is IC 74193.

It is

usually used

When the count reaches 0, signal SC = 0 L is asserted.

LAST STEP L is generated when SC = 13 8 during an MUL, when SC = 14 8 during a DVI, and when

SC = 37 for all operations.

1-32

1-33

1.22.3

Shift Right/Shift Left Control Logic

The shift right/shift left control logic is illustrated in Figure 1-32. The 8235 ICs are multiplexers that receive

LEFT L is enabled during an
SHL NORMALIZE, or DVI instruction. The shift-right (ASR or LSR) and multiply instructions cause RIGHT L
select signals at pins 7 or 9 to select signals being received at pins 1, 2, 10, or 14.
f

to be asserted.

1.22.4

Shift

OK Logic

The shift OK logic (Figure 1-33) monitors the contents of the* AC and MQ during the NMI instruction and checks
for LAST STEP L.

When LAST STEP L becomes low during an SHL, LSR, or ASR instruction, SC = 37.

If the

MODE flip-flop is set, indicating the new or Mode B instruction set in use, SHIFT OK H grounded to prevent
the last shift from occurring. During an NMI instruction, SHIFT OK H
grounded when the number becomes
is

normalized, to prevent an extra shift from taking place as the processor is restarted.

EAE Carry n Logic

1 .22.5

Signal
is

CARRY IN L

developed by the EAE under the conditions shown in Figure 1-34.

decoded when an SAM, DCM, or DPIC instruction is to be performed.

If the

ROM output, ROM 22 L

EAE is off (SAM or Step

DPIC and DCM) CARRY IN L is generated.
IN L if

ROM 13 L controls the coupling of carries, and introduces a CARRY
the Link is set during Step 2 of DPIC and DCM and the two EXECUTE cycles of the DAD instruction.

8235
E24
SHIFT OK H

ROM 14 L

LEFT

ROM 12 L
ROM 15
EAE ON
8235
E27

note:

DIV

ROM

DIV- LAST STEP

BTS3
LAST STEP

RIGHT L
8235
E31

EAE ON

ROM

HZZZj

A SR + L SRVEAE ON L| 7

0
<

8235

ROM 12

MUY-EAE ON L

Figure 1-32

EAE Shift Right/Shift Left Control Logic

1-34

Logic Summary:

If pin 7 is low, the A inputs
are inverted and connected to
the outputs. If pin 9 is low,
the B inputs are connected to
the outputs. Outputs are
open- collector.

(AC2-11 =0) -MQ=0

AC4-11 = 0

AC2-AC3 =

0—

NEW H
LAST STEP

NORMS + SHL+ASR+LSR
EAE ON (1)

SHIFT OK H

NORMS -f SHL + ASR + LSR

NEW INST H

* Low only for NMI

ROM 22
TS3

MS.IR DIS

Shift

ROM 13 L

LINK

=L>
1

OK Logic

BTS3

—
^

NEXT LOC H

Figure 1-34

EAE ON (0)

TS4 L

—

instruction.

Figure 1-33

1 .22

NEW H

•

CARRY IN

J
EAE Carry In Logic

MQ Register Shift Left Logic

The MQ Register shift left logic is illustrated in Figure 1-35. Decoded outputs ROM 14 L and ROM 15 L, with
EAE, select such signals as SHI FT OK H and CARRY OUT L, etc.

Signal

MQ DATA L provides quotient infor-

mation to MQ1 1 during a divide. Otherwise, MQ DATA L remains high, shifting zero into MQ1 1 for NMI and

SHL instructions. Signal SHL + LD EN L forces the MQ Register to shift one place to the left. Also shown with
this logic is the Dl V LINK and other gating required to generate the quotient bit.
1 .22.7

AC to MQ Transfer Signals

MQ ENA L can be asserted. This gating is used during
MQ swapping process. AC MQ ENA L also generated for

Figure 1-36 illustrates the conditions when the signal AC

the DAD and DST instruction as a part of the AC

the DPIC and DCM instructions in the M8310, as described in Volume 1, Paragraph 3.40.

1.23

DESTINATION CONTROL SIGNALS

The signals that actually cause register loading are called destination control signals.

In the case of the EAE, only

MQ LOAD L signals are developed in the EAE logic. Other loading signals, including MB
LOAD L, are asserted by the processor. Figure 1-37 illustrates how the AC, MQ, and MB Register loading signals

the AC LOAD L and

are generated.

1-35

ROM 14 L

^DVI H

ROM

ADO L
DIV
LINK
AC LOAD L

SHL + LD

4-3V

SHIFT OK H

—P>0-4d 8235

EN L

E24

CARRY OUT

SC=0 L

MQ10 L

ROM

DATA L

^ J

EAE ZZj

ONJ (0)

ROM 14 L

ROM 12 L

ROM

IN.

JBTS3

8235

J (SHL + NORMS
I-

)

•

Logic Summary-

If pin 7 is low, the A inputs
are inverted and connected to
the outputs. If pin 9 is low,
the B inputs are connected to
the outputs. Outputs are

2 L

cl">

ROM 14L

N DVI H

EAE ON

open-collector.
8E-044I

MQ Register Shift Left Logic

Figure 1-35

DAD+ DST

•

ENA L

Figure 1-36

MQ TRANSFER Signal

AC LOAD L

8235
E27
15

TP3

NORMAL DVI

note:

MQ LOAD L
ROM 14 L
RO M 12 L

J AST

STEP

•

LAST DVI,

DAD + DST L

TG2

SI " L >
d

SHIFT OK H

(

TG4(0)

=l>
1

8235

MB LOAD L
|

PART OF PROCESSOR

Figure 1-37

Logic Summary:

If pin 7 is low, the A inputs
are inverted and connected to
the outputs. If pin 9 is low,
the B inputs are connected to
the outputs. Outputs are
open-collector.

Destination Control Logic

1-36

1.24

EAE START/STOP LOGIC

The EAE start/stop logic, shown in Figure 1-38, transfers timing generation from the CPU to the EAE. Up to TP3
of certain EAE cycles the generation of all timing signals is under CPU control. At TP3, timing control can be
transferred to the EAE to allow high-speed multiple shifts and/or adds.

At the conclusion of these special opera-

tions, timing is returned to the CPU.

The EAE grounds OMNIBUS signal NOT LAST XFER L before TP3 when the current instruction and major state
requires running the EAE timing chain.

The N LX flip-flop is clocked 100 ns after the trailing edge of TP2, after

the ROMs and associated decoding have had ample time to settle.

If the

D input to N LX is high, one of the fol-

lowing instructions has been decoded; the major state is the one in which the EAE operation is to take place.
Instructions which start the EAE Timing Chain:

ASR, LSR, SHL, NMI, MUY, DVI, DPIC, DCM
The output of the NLX flip-flop is applied to one input of a two-input NAND gate (labeled A in Figure 1 -38)
whose output grounds NOT LAST XFER L. At the same time, the other input of gate A is high, unless a Divide

NOT LAST XFER L is low at the leading edge of TP3, CPU timing
EAE TG START H ANDed with TP3 and the result
used to set the E SYNC flip-flop. At the trailing edge of TP3, the EAE ON flip-flop is clocked and sets. The EAE's
Overflow situation is detected by gate B.
is

interrupted as described in Volume 1

Paragraph 3.21

timing chain is now running.

The EAE continues to run until some condition within the EAE causes EAE STOP H to go high. At the leading
edge of the next ETP, E SYNC clears. At the trailing edge of the same ETP, EAE ON clears and stops the EAE.

RESTART L has the same effect on the Timing Generator of the CPU (but not the Major Registers) as does
BUS STROBE L - it starts the CPU if NOT LAST XFER L is high. RESTART L is generated twice, once when
the EAE starts (it has no effect then), and once when the EAE stops. NOT LAST XFER L is high by the time
the second RESTART L signal is generated, because N LX
cleared by one of the EAE's timing generator flipSignal

flops (TG2) a short time after the trailing edge of TP3 and well before the leading edge of the first ETP.

1.25

EXTENDED EAE LOGIC

The extended EAE logic (Figure 1-39) consists of a D-type flip-flop called EX1 and its associated logic. When set,
EX1 forces a second EXECUTE cycle and causes the processor to access the next sequential memory location.
Signal

NEXT LOC H

used to generate CARRY IN L and to ground EXO, which causes

MA +

to the

The logic gating for the EX1 data input is limited to either a DAD or DST instruction. DAD, DST, MUY, and

DVI are the only EAE instructions that enter a DEFER cycle. For both MUY and DVI instructions, EIR6(1) is
low and, therefore, prevents the EX1 flip-flop from being set.

1.26

EAE LINK CONTROL LOGIC

The EAE link control logic (Figure 1-40) contains all of the Link Control elements required to load the Link and
to disable the Link so that it is not affected by certain processor-EAE operations.

Link operation within the processor, refer to Volume 1

Paragraph 3.39.

1-37

For a better understanding of

1-38

F E

EXT LOC H

ROM 26

FETCH

<3r

EX1

SET

INIT H

TP4
MA, MS, LC

MODE B H
EIR6

EIRO(1)
EIR1

EIR2(
EIR3(
EIR1K1)

N DAD+DST

EAE INSTRUCT

—
Figure 1-39

Signal

DEFER—d

(
I

(1)

Extended EAE Logic

LINK DATA L provides information to be loaded into the Link by the LINK LOAD L pulse. This infor-

mation may be one of the following:

Enable

None

Used By

Result if Link Loaded

DVI (to clear overflow

Zero

indication) MUY,

LSR,

DAD

ROM 11 L

Carry from adders

DAD, DPIC, DCM

ROM 13 L

ACO

ASR, NMI

DVI EAE ON (0)

One

DVI (to anticipate
overflow)

The LINK LOAD L signal is generated at TP3 if ROM 17 is low (usually to preset the Link) and at ETP time during left shifts.
if

During the execution of DVI, the Link is set at TP3 (for possible overflow indication) and cleared

the DVI process reaches LAST STEP L (meaning a legal divide has occurred). During the right shift and

MUY

instructions, the Link is not modified.

During left shifts, data is introduced from MQO to AC1 1 via a line called ADLK L. During SHL or NMMnstruc
tions,

MQO is gated directly to ADLK L. For DVI, MQO is sometimes inverted before being applied to ADLK L.

The gating logic, which depends on MQ1 1 and whether the first divide step has taken place (EAE ON), is also

shown in Figure 1-40.
The ADLK DIS L signal disables the normal Link gating described in Volume 1, Paragraph 3.39.

ADLK DIS L

must be low any time the LINK LOAD L/LINK DATA L inputs are used or whenever left shifts are performed
in order to avoid conflict with the normal link gating.

1.27

This line is grounded by ROM 16 L.

EAE SKIP LOGIC AND GT FLAG

The EAE skip logic is illustrated in Figure 1-41. There are two methods of generating a SKIP L signal.

Signal

NEXT LOC H, which is generated by the extended EAE logic, is inverted and applied to the SKIP L line. Signal
NEXT LOC H also generates CARRY IN L.
1-39

c
cS

1-40

1-41

The SKIP line Is also grounded when a DPSZ instruction is being performed. This instruction tests the AC and
the

MQ for 0. If both registers equal zero, the SKIP L signal will be asserted. SKIP L

flip-flop in the processor's logic at TP3.

used to set the SKIP

For information on the processor's skip logic, refer to Volume 1

Para

graph 3.38.

The more complex part of the skip logic involves the Greater Than (GT) flag. When the GT flip-flop is set, instruction SGT forces the SK IP line to go low.

The GT flag can be changed by one of three methods:

Method

Source of Information

DATA

RTF instruction

SAM instruction

Set if

MQ greater than or equal to AC;

cleared otherwise.

ASRor LSR

Previous MQ1

The GT flag is cleared if the EAE is in Mode A; hence, the flag is active only for Mode B instructions.

SECTION 5 MAINTENANCE
Since the EAE is physically connected to the Central Processor Timing Generator and OMNIBUS, a definite
possibility exists that some EAE malfunctions will not be caused by the EAE modules.

For this reason, the fol-

lowing procedure is suggested.

Step

Procedure

Remove M8340 and M8341 from the OMNIBUS.

Perform processor-related diagnostics to ensure processor reliability.

Insert M8340 in

OMNIBUS and connect

to the Timing Generator via the "J" top

connector.

Perform PDP-8/E Instruction Tests 1 and 2.

Insert M8341 in

Perform PDP-8/E Instruction Tests 1 and 2.

Connect M8341 to M8310 via "F" connector.

Perform PDP-8/E Instruction Tests 1 and 2.

OMNIBUS and connect it to M8340 connector H.

NOTE
If problems are encountered

during this procedure,

they can be isolated by troubleshooting the processor, and tracing the malfunction back to the last module or connector that was added to the system.

When this procedure fails to isolate a malfunction,
perform EAE Instruction Tests 1 and 2, and the EAE
Extended Memory Test. One of these tests should
give some idea of the problem.

Once the problem is pinpointed, write and toggle in a
simple program using the malfunctioning instruction.

1-42

The following basic ideas can be built upon or modified to suit any special purpose:
1.

Mode Changing Instructions
0/

SWAB
SWBA
JMPO

7431

7447

5000

SCL or ACS (dependent on mode)
Mode A
0/

LAS
DCA.+2
SCL

7604

3003
7403

Mode B
0/

OPERAND
JMPO

XXXX
5000

7431

SWAB

7604

LAS

7403

ACS
JMP .-2

5001

SCA or SCA, CLA
Mode A
0/

7604

LAS

3003

DCA .+2

7403

SCL

XXXX

OPERAND

7441 or
7641

SCA or SCA, CLA

7000
I

5 or 6 NO OPS Wl LL HOLD THE AC

FOR OBSERVATION

JMPO

5000

Mode B
0/

SWAB

7431

7604

LAS

7403

ACS
SCA or SCA, CLA

7441 or

7641

7000

NO OPS TO HOLD AC FOR OBSERVATION
JMP 1
4.

SHL Shift Left
Mode A
0/

7604

LAS (Shift Count = one more than the last five bits of the location following SH L)

3006

DCA
TAD MQ
MQL

1050
7421

(continued on next page)

1-43

TAD AC
SHL
SHIFT COUNT

NO OPS WILL HOLD AC AND MQ FOR OBSERVATION

CAM
JMPO
Mode B
0/

7604

LAS (Shift Count = last five bits of location following SHL)

3007

1051

DCA
SWAB
TAD MQ
MQL
TAD AC

7413

SHL

XXXX

SHIFT COUNT

7431

1050
7421

7000 ^

NO OPS Wl LL HOLD AC AND MQ FOR OBSERVATION

7000 J

7621

CAM

5001

JMP 1

7431

1050

1051

SWAB (Start here if Mode B)
TAD MQ (Start here Mode A)
MQL
TAD AC

7411

NMI

7421

7000

^
>

HOLDS AC AND MQ FOR OBSERVATION

7000 J
5001
6.

ASRorLSR
0/

7604

LAS (Shift Count = One more than this number in location following ASR or LSR
Mode A)
DCA (Shift Count = Number in location following ASR or LSR if Mode B)
SWAB (Start here if Mode B)
TAD MQ (Start here if Mode A)
if

3007
7431

1050
7421
1051

7415 or
7417

XXXX

MQL
TAD AC
ASR or LSR
SHIFT COUNT
(continued on next page)

1-44

NO OPS TO HOLD AC AND MQ FOR OBSERVATION

MUY
Mode A
0/

LAS (Multiplier)

DCA
TAD MQ
MQL
TAD AC
MULTIPLY
MULTIPLIER

HOLD AC AND MQ FOR OBSERVATION
JMP
Mode B

SWAB
LAS (Multiplier)

DCA 100
TAD MQ
MQL
TAD AC
MULTIPLY
ADDRESS OF MULTIPLIER

HOLD AC AND MQ FOR OBSERVATION
JMP
8.

DVI

Mode A
0/

LAS (Divisor)

DCA
TAD MQ

MQL
TAD AC
DVI

DIVISOR

HOLD AC AND MQ FOR OBSERVATION
JMP
(continued on next page)

1-45

Mode B

LAS (Divisor)

DCA 100
TAD MQ
MQL
TAD AC
DIVIDE

ADDRESS OF DIVISOR
HOLD AC AND MQ FOR OBSERVATION
JMP
9.

SAM

HOLD AC, MQ AND STATUS FOR OBSERVATION
JMP
10.

DAD or DLD
0/

7431

1050
7421
1051

7443 or
7763

SWAB
TAD MQ
MQL
TAD AC
DAD or DLD

ADDRESS OF WORD

HOLD AC AND MQ FOR OBSERVATION

11.

DST

CONFIGURE AC AND MQ

SWAB
DST
LOCATION OF WORD

DLD

HOLD AC AND MQ FOR OBSERVATION
(continued on next page)

1-46

12.

DPIC
0/

13.

7431

SWAB

7573

DPIC

5001

JMP

7431

SWAB
TAD MQ

DCM
0/

1050
7421
1051

7575
1051

MQL
TAD AC
DCM
TAD Original AC

7521

SZA
HLT
SWP

1050

TAD Original MQ

7440

SZA
HLT

7440
7402

7402

14.

7621

CAM

5001

JMP

DPSZ
0/

7431

SWAB

7621

CAM

7451

DPSZ

7402

HLT
JMP

5001

The programs listed above, when used in conjunction with the flowchart, ROM encoding matrix, and print set,
provide simple, repetitive troubleshooting instructions.

Use the following check list as a guideline.
a.

Instruction was properly loaded into the Op-decoder.

ROM address

ROM outputs are correct.

Step Counter decodes last step properly.

correct.

Control and loading signals listed on the flow chart are occurring at the correct time in relation to

time states and bit configurations.

SECTION 6 SPARE PARTS
Table 1-4 lists recommended spare parts for the KE8-E. These parts can be obtained from a local DEC office or

from DEC, Maynard, Massachusetts.

1-47

Table 1-4

Recommended KE8-E Spare Parts

DEC Part No.
i

y uoooo

Description
lU utu /H/O

1Q fiRR7fi

1Q
OQQRR
y-uyyoo
i

uu o
i

Quantity
1
1

ip
ncp 7>i 1 o
IL» UtLr /41 /

IP
r\cp "7>iiqq
ILr Ufcu /41yo

in
nOQQyl
iy-uyyo4

IL»

IP r\cr*
qocc
UtU ozbb

ly-Uyzb/

IC DEL 74H1

iy -UOOOO

IC DEC 74H20

ly-OoDoo
1 9-09486

IC DEC 74H40

IC DEC 384

19-09004

IC DEC 7402

19-09667

IC DEC 74H74

9-09059
1 9-099/3

IC DEC 74H30

IC DEC 97401

y-U94oo
no nni A
a1
zo-UU

IC DEC 380

y-uy /uo

RUM (Drives ROM 11—18)
encoded hum (unves HUM zl—zo)
ip
ILr ncp
UtU 7>inR
/4UO
IP
RPP
QQQ1
ILr UCL OOO

19-0551

ip npp 74.no

lu Encoded
ILr

1Q
HQQ^n
y-uyyou
i

19-07686

IC DEC 7404

19-09062

IC DEC74H53

19-10011

IC DEC 7486

19-09935

IC DEC 8235

13-00295

Resistor 33012 1/4W,5%

13-00365

Resistor 1K, 1/4W, 5%

13-00317

Resistor 470ft, 1/4W, 10%

10-00067

Capacitor 6.8 fif, 5V, 20% Solid Tantalum

10-01610

Capacitor 0.01 fif, 100V, 20% Ceramic Disk

1-48

1
1

]

PART 2
MEMORY EQUIPMENT OPTIONS

CHAPTER 2
KM8-E MEMORY EXTENSION AND TIME-SHARE

SECTION 1

INTRODUCTION

The KM8-E Memory Extension and Time-Share option generates a 3-bit address for the extended memory address
This address allows the use of more than 4K of memory and, when required, is used as a prerequisite in a

lines.

time-sharing system.
All logic is contained on one M837 quad-size module that plugs directly into the

OMNIBUS.

All signals enter and leave the module via the OMNIBUS.

2.1

MEMORY EXTENSION DESCRIPTION

Memory extension hardware is required when more than 4K of memory is to be addressed. Except for data
break devices, the KM8-E Memory Extension is the only means by which extended memory addresses can be applied to the three extended memory address lines called EMA 0-2. Memory is divided into 4K fields, starting
with field 0, for the basic 4K memory, up to field 7, when 32K of memory is employed. Each 4K of memory receives and decodes the

EMA signals. This provides the addressing capability of up to 32,768 memory locations.

There are two types of fields: the Instruction Field, which acts as an extension to the PC and direct argument
addresses; and the Data Field, which augments the address of indirectly obtained arguments. When the program-

mer desires to use one field for instructions and a different field for data, he directs the corresponding field address to either the Instruction Field Register or the Data Field Register contained on the KM8-E. The field addresses are applied to the

EMA lines by specific instructions and conditional logic. Safeguards are provided so

that during unplanned events, such as interrupts and data breaks, no field addresses are lost.

Program instructions

allow any field address to be stored; this is particularly important to the programmer desiring to nest interrupts.

A simplified block diagram showing the basic transfer paths dealing with memory addressing and field addressing
The KM8-E is the only route by which fields above field 0 may be selected. The only exception is the data break device that has the capability of selecting its own memory field. The programmer has
is

shown in Figure 2-1

two methods of selecting memory fields. One method is via the Console Switch Register; the second method is
via an

JOT instruction.

In either event, field information

loaded into the appropriate register in the extension

control. The extension control automatically responds to the appropriate instructions and major states by placing

the contents of the correct field register onto the EMA lines.

2-1

DECODER

4K MEM

EMA BITS
Q

EMA

MEMORY
EXTENSION

0
0

A-

FIELD
FIELD 0
FIELD

FIELD

DATA BUS

FIELD 6
FIELD 7

D LINES

PROCESSOR

MEMORY
CONTROL

TIMING -N

Figure 2-1

2.2

Memory Extension, Simplified Block Diagram

TIME-SHARE DESCRIPTION

The time-share portion of the KM8-E is used only when a time-sharing system is to be employed. The KM8-E
Module contains a jumper in the inhibit logic that prevents the operation of the time-share function. Unless this
jumper is to be removed from the module, the reader need not be concerned with the time-share description in
this chapter.

The KM8-E Memory Extension and Time-Share option provides the necessary additional hardware for a generalpurpose time-share system. This option, coupled with a time-sharing program, such as TSE, and 12K to 32K of
core, allows a maximum of 16 users to independently run programs. This creates the appearance that each user

has the computer to himself.

As a system, the user can be considered operating in one of three levels:
and c) user level.

A typical system

Teleprinter Control.

illustrated in Figure 2-2.

not logged-in level, b) monitor level,

The user interface to the system is the KL8-E

The monitor program performs a dominant role in controlling operation between the pro-

cessor and the KM8-E option and between the users and the processor.

The monitor is a complex of subprograms to coordinate the operations of various programs and user consoles.
The monitor allocates the computer's time and services to various users; it grants a slice of processing (computing)
time to each job, and schedules jobs in sequential order to make the most use of the mass-storage device. The
monitor also handles user requests for hardware operations (reader, punch, etc.), swaps (moves) programs between memory and mass storage, and manages the user's private files. Thus, the primary time-sharing capability is
provided by the system monitor and the PDP-8/E Processor. However, certain additional hardware not provided

by the PDP-8/E Processor is needed to accommodate the special requirements of time-sharing and extended addressing capability.

For more information on the monitor and user programming, refer to Chapter 10 of Introduction to Programming.

Figure 2-2

2.3

Typical Time-Share System

EXTENDED MEMORY AND TIME-SHARE SUMMARY

As a memory extension control, the KM8-E provides:
a.

Hardware to allow the programmable selection of the extended memory field (fields 1 through 7),
allowing the extended addressing capability of the processor from a basic system of 4096 addresses
to an extended memory system of up to 32,768 addresses.

Hardware to prevent an interrupt or data break from interferring with the extended addressing scheme.

Hardware to save and restore a field return address.

As a time-share control, the KM8-E provides:
a.

Hardware to distinguish between user and monitor modes.

Hardware to trap certain instructions, causing an interrupt and placing the time-share system in monitor mode.

2.4

Ability to establish user mode.

SOFTWARE

The following programs are used in time-sharing and memory extension operations:
a.

System Programs
1.

TSE Time-Sharing Monitor (DEC-T8-MRFB) - TSE (Time-Sharing System for the PDP-8/E
Computer) is a general-purpose, stand-alone, time-sharing system. TSE offers each of a maximum
of 16 users a comprehensive library of programs for compiling, assembling, editing, loading, saving, calling, debugging, and running user programs on-line.

2-3

Diagnostic Programs

Extended Memory Address Test (MAINDEC-8E-D1 FA) - This program tests all of memory (up
to 32K) not occupied by the program to verify that each location can be uniquely addressed.

Extended Memory Checkerboard (MAINDEC-8E-D1 BA) - This program is designed to provide
worst-case half-select noise conditions to determine the operational status of core memory.

The

patterns generate worst-case noise conditions in all used fields of a PDP-8/E equipped with at
least 8K of core memory.
3.

Extended Memory Control and Time-Share Test (MAINDEC-8E-D1 HA) - This program tests
the Extended Memory Control and Time-Share option logic for proper operation.

The program

exercises and tests the control lOT's, time-share instruction trapping, and the ability to address
all

2.5

fields, program interrupt, and auto-index.

COMPANION DOCUMENTS

The following documents and publications are necessary for the operation, installation, and maintenance of this
option:
a.

PDP-8/E & PDP-8/M Small Computer Handbook — DEC, 1972

PDP-8/E Maintenance Manual - Volume 1

Introduction to Programming - DEC, 1972

DEC engineering drawing, Memory Extension and Time-Share Option, number E-CS-M737-0-1

Extended Memory Address Test, MAINDEC-8E-D1 FA-D
Extended Memory Control and Time-Share Test, MAINDEC-8E-D1 HA-D

SECTION 2 INSTALLATION
The KM8-E Memory Extension and Time-Share option is installed on-site by DEC Field Service personnel. The
customer should not attempt to unpack, inspect, install, checkout, or service the equipment.

2.6

INSTALLATION

Perform the following procedures to install the KM8-E option:

Step

2.7

Procedure

Remove the module from the shipping container.

Inspect the module for any apparent damage.

Connect the module to a convenient OMNIBUS slot.

CHECKOUT

Perform the following procedure to checkout the KM8-E option:

Step

Procedure
Verify that the extended memory modules have been installed.

2-4

Step

Procedure

Perform acceptance tests provided in Volume 1

Load MAINDEC-8E-D1 FA, Extended Memory Address Test. This program tests all of
memory (up to 32K) not occupied by the program to verify that each location can be

Chapter 2, Paragraph 2.3.

addressed uniquely.

Load MAINDEC-8E-D1BA, Extended Memory Checkerboard. This diagnostic program
provides worst-case half-select noise conditions and verifies the operational status of core

memory.
6

Load MAINDEC-8E-D1 HA, Extended Memory Control and Time-Share Test. This program tests the Extended Memory Control and Time-Share option logic for proper operation. The program exercises and tests the control lOT's time-share instruction trapping;
and, if time sharing is implemented, the ability to address all fields, program interrupt,

and auto-index.
7

Make entry on user's log that the acceptance test for the KM8-E option was performed
satisfactorily.

SECTION 3 PRINCIPLES OF OPERATION
2.8

INTRODUCTION

The KM8-E system description is given in terms of its functional operation. From the functional point of view,
instructions that make either the memory extension or time-share portion do something must be considered, as
well as the philosophy of why the events happen as they do.

The system description, therefore, is a composite

treatment of the hardware, represented in block diagram form, and of the flow of events, represented in flow

diagram form. The events that occur in the Memory Extension and Time-Share option are considered fully; the
events within the processor are considered only partially. Such areas as major register gating and how the processor functions are completely described in Volume 1

2.9

SYSTEM DESCRIPTION

A block diagram representing all of the functional elements of the KM8-E Memory Extension and Time-Share
option is given in Figure 2-3. The logic can be considered divided into three groups: the Control (located on the
left

portion of the illustration), the Instruction Field Registers (located in the center of the illustration), and the

Data Field Registers (located in the far right of the illustration). The only interface is the OMNIBUS. All signals
entering and leaving the system, therefore, are directed from and to the OMNIBUS.

Data paths between the

KM8-E and the processor are via the DATA BUS. Data is directed to the console status indicators via the DATA

BUS during TS1 to tell the operator which instruction and data fields have been addressed. When the data field
and/or the instruction field are to be stored in memory, the data path is from the DATA BUS to the AC Register.

A DCA instruction is then used to store information in memory. The data paths between the processor and the
KM8-E are via the DATA BUS and MD lines.
Special inhibiting features are designed into this option.

For example, during a data break operation, when some

peripheral such as a disk is being operated, control lines such as CPMA DIS prevent the transmission of data to the

EMA lines. For the case of programmed interrupts, the logic provides the means of holding an interrupt back una CI F or RMF instruction has been completely processed.

til

2-5

snai nwo

Another design feature is the time-share trap logic that signals the monitor when certain instructions are used
by the user.

2.9.1

Control Logic

The control logic (Figure 2-3) for the Memory Extension and Time-Share option contains elements similar to
most I/O devices. These are the device selector logic, operations decoders, and the C1, INT RQST, and SKIP signal lines.

Before operation begins, an IOT instruction addressed to this option is required. The INT RQST and

SKIP lines are directly controlled by the USER INT flip-flop that functions to detect a TRAP signal. This flipflop signals the monitor that a TRAP has been detected; the monitor then evaluates and takes appropriate action.

The USER MODE L control signal is used in the processor to prevent the processor from responding to HLT, OSR,
and IOT instructions. The INT INHIBIT flip-flop serves to ground the INT IN PROG line, thereby preventing an
interrupt from occurring when instruction field changes are being processed.

For the user not desiring to use the time-share portion of the option, a simple jumper on the module prevents the
User Flag (UF) flip-flop from being loaded. The instructions used with the Memory Extension and Time-Share

option are listed in Table 2-1. For a detailed explanation of each instruction, refer to the KM8-E Memory option
description in Chapter 7 of the PDP-8/E & PDP-8/M Small Computer Handbook.

Table 2-1

KM8-E Extended Memory and Time-Share Option Instructions

MEMORY EXTENSION OPERATIONS
Data Field and Instruction Field Operations

RMF

Restore Memory Field

RIB

Read Interrupt Buffer
Data Field Operations

CDF
RDF

Change to Data Field
Read Data Field
Instruction Field Operations

RIF

Read Instruction Field

CIF

Change to Instruction Field

FLAG OPERATIONS
GTF
RTF

Get the Flags
Restore the Flags

TIME-SHARE OPERATIONS
CI NT

Clear User Interrupt

SINT

Skip on User Interrupt

CUF
SUF

Clear User Flag

Set User Flag

2-7

2.9.2

Instruction Field Register and Controls

The Instruction Field Register receives new instruction field information from any one of three sources:
a)

Memory Data Lines, b) DATA BUS, c) Interrupt Buffer. The main registers are the Instruction Buffer Register

and the Instruction Field Register. The three output lines of the Instruction Field Register are connected, via the
Extended Address Output Multiplexer, to the three EMA lines.

The control logic (Figure 2-3) associated with the Instruction Field Register governs data flow, providing the
necessary gating and the primary control signals to enable gating, loading, clocking, etc. This logic selects either

the Save Field, the DATA BUS, or the Memory Data lines as input and outputs this information to either the

Extended Address Output Multiplexer or the DATA BUS. The flow of data is from the bottom to the top of the
illustration.

When the contents of the Interrupt Buffer are transferred to the Instruction Field Register, an RMF

instruction gates the Save Field bits through the Instruction Field Multiplexer.

When the contents of the InstrucMD 6—8 through the

tion Register were previously stored in some memory location, the CIF instruction gates bits
Instruction Field Multiplexer.

The DATA BUS Receiver Gates receive data from the AC Register or the Console Switch Register. During TS3
of the FETCH state, the contents of the AC are applied to the DATA BUS, while the KM8-E Operations Decoder
is

decoding the RTF instruction. The RTF instruction immediately gates bits 5—8 into the Instruction Buffer

Input OR Gates. This information may have been fetched from memory during the previous memory cycle or
input from the Console Switch Register.

The contents of either the MD lines or the Save Field are gated through the Instruction Field Multiplexer by instruction

RMF or CIF. The Instruction Buffer Input OR Gates, in turn, apply either DATA 5-8, MD 6-8, or

the Save Field to the Instruction Buffer Register and apply the UF flip-flop, obtained from the Save Field, to the

User Buffer. The purpose of the Instruction Buffer is to prevent the logic from prematurely loading the Instruction Field Register.

a CIF,

RTF, or RMF instruction is issued, the actual change of field does not take place until the next JMP in-

struction has been completed or until the EXECUTE cycle of a JMS instruction has been entered.

The new in-

struction field is first loaded into the Instruction Buffer and then transferred from the Instruction Buffer to the
Instruction Register at TP4 so that memory is not disturbed.

Although data is available for input to the Instruction Buffer Register and the User Buffer, loading does not occur until the loading lines are asserted.

To load the Instruction Buffer, signal line KEY CONTROL must be

grounded or one of the three loading instructions (RTF, CIF, RMF) must be asserted (grounded) and clocked in
by TP3. Manual loading of data at the Console Switch Register creates LOAD ADDRESS L for the Instruction
Buffer Clock input and KEY CONTROL for the buffer loading. Bits IF 0—2, representing one of eight possible
instruction fields, are on the buffer output lines when the buffer is loaded.
ceives IF 0-2 and the UF flip-flop.

Bits IF 0-2 are then ORed with

The instruction field input logic re-

DATA 5-8 unless the operator is manually

loading data into the Switch Register or an RTF instruction is executed. These conditions allow only DATA 5-8
to enter the Instruction Field Register.

The UF flip-flop is inhibited if the TIME SHARE DIS signal is asserted.

Program loading of the Instruction Field Register is accomplished by a directly addressed JMP or JMS instruction
at the end of

FETCH, or by a JMP or JMS at the end of DEFER, or by an RTF instruction. Manual loading is

accomplished by signal KEY CONTROL, which is developed when the operator loads data into the Console
Switch Register. The clocking for programmed loading occurs at TP4; for manual input, clocking occurs any time

LOAD ADDRESS L

asserted.

Once the Instruction Field Register is loaded, the contents are ready to be loaded into either the Extended Address Output Multiplexer or the Interrupt Buffer.

2-8

2.9.3

nterrupt Buffer A

Interrupt Buffer

A functions to save the contents of the instruction field when an interrupt occurs. Signal INT

IN PROG H loads the UF flip-flop and bits IF 0—2 at TP4.

When the interrupt has been serviced and the memory

extension is again activated, the contents of the Interrupt Buffer are input to the Instruction Field Multiplexer by
an RMF instruction and the field change sequence of events will be repeated. Should the programmer wish to
nest interrupts, he can store the contents of the Interrupt Buffer using the GTF instruction (or RIB instruction).

The machine can be restored to its original condition using the RTF (or CIF and CDF) instruction.

2.9.4

Data Field Register And Controls

The Data Field Register and Controls function to receive a new data field from any one of three sources:
a)

Memory Data Lines; b) DATA BUS; c) Interrupt Buffer. The output lines of the Data Field Register are con-

nected to the Extended Address Output Multiplexer and, when selected, address the data field by means of a

combination of three bits on the EMA lines.

The simplified blocks (Figure 2-3) concerned with the Data Field Register and Data Field Register operation
represent the flow of data, the necessary gating, and the primary control signals to enable gating, loading, clocking, etc.

They function to select either the Save Field, DATA BUS, or memory data lines as an input and output

this information to the

EMA lines or the DATA BUS.

The flow of data is from the bottom to the top of the illustration. When the contents of the Interrupt Buffer are
transferred to the Data Field Register, an RMF instruction gates the Save Field bits through the Data Field Control Multiplexer.

When a CDF instruction is executed, bits MD 6-8 are gated through the Data Field Control

Multiplexer.

The DATA BUS Receiver Gates receive data from the AC Register or the Console Switch Register. During TS3
of the FETCH state, the contents of the AC are applied to the DATA BUS while the KM8-E Flag Instruction

Decoder decodes the RTF instruction. The RTF gates bits 9 through 1 1 into the Data Field Register.

The contents of either the MD lines or the Interrupt Buffer (RMF instruction) are gated through the Data Field
Control Multiplexer. At TP3, the new data field is loaded into the Data Field Register. The manual loading operation is similar to manual loading of the Instruction Field Register.

2.9.5

nterrupt Buffer B

Interrupt Buffer B saves the contents of the data field whenever an interrupt occurs. Signal

INT IN PROG H

loads data field bits DF 0-2 at TP4. When the interrupt has been serviced and the memory extension is to be
activated, the data field is restored to the Data Field Register by the

2.9.6

RMF instruction.

Extended Memory Addressing Output Control

The three EMA 0-2 lines address any one of 8 memory fields. When any combination of these lines is grounded,
the result is a selected memory field.

The Extended Address Output Multiplexer with the DF EN flip-flop deter-

mines whether the EMA bits will be the data field or the instruction field (Figure 2-3).
illustrating the conditions which determine the selection is shown

A simplified flow diagram

Figure 2-4.

JMP or JMS instruction is activated, the instruction field is addressed. Otherwise, the logic tests the DEFER state. The DF EN flipBeginning at the top of the flow diagram, the logic tests for a JMP or JMS instruction.

If the

flop is clocked by TP4 or LOAD ADDRESS if the field is applied at the console switches.

operation, the extended address will not be applied to the

2-9

EMA

If a

data break is in

lines at that time. As soon as the data break ends,

the Extended Address Output Multiplexer will be enabled to gate either the instruction field or data field bits

out to the EMA lines and thereby select a memory field.

The rule for data field usage is as follows:

current instruction is an AND, TAD, ISZ, DCA or EAE instrucDEFER state, the next EXECUTE cycle will use the data field. All

If the

tion, and if the processor is currently in the

other machine cycles that are not data break cycles use the instruction field.

Notice that the DEFER state is tested at the end of the current processor cycle. The decision whether the processor is to go to the EXECUTE state or the FETCH state is clearly indicated in Figure 3-1 7 of Volume 1

The

same type of decisions that determine if the next state is to be EXECUTE or FETCH determine if the instruction
field or data field is to be addressed.

YES

POSSIBLE
INSTRUCTION
FIELD

CHANGE

Figure 2-4

2.10

TO INPUT OF DF
EN F/F

0 TO INPUT OF DF
EN F/F

Extended Memory Addressing, Flow Diagram

OPERATING FUNCTIONS

The following paragraphs provide some examples of KM8-E operation. These descriptions reflect the flow of
events for illustrative purposes and do not reflect the method by which this option is to be programmed.

2.10.1

Status Operation

Occasionally the user wants to select the STATUS position on the Console Selector Switch.

IND L will be generated at the start of TS1 and remain until TS2.

2-10

Signal

When he does this,

IND is used in the memory extension

and time-share logic to gate the contents of the IF and DF Registers through the output multiplexers and onto
the DATA BUS.

Refer to the system block diagram given in Figure 2-3 and to Figure 2-5 for the bit arrangement

illustrating the status.

Only bit 3 and bits 5 through 1 1 represent the status of the Memory Extension and Time-

Share Control.
Bit 3 represents the interrupt status of the INT INHIBIT flip-flop. Signal

INT INHIBIT is generated at TP3 when-

ever an RTF, KEY CONTROL, CIF, or RMF signal is asserted, and negated at TP3 whenever a JMP or JMS instruction occurs. This prevents any memory field from being lost during a program interrupt. Thus, whenever
bit 3 of the status indicator is illuminated, indicating a program interrupt inhibiting condition, the processor has

not started a JMP or JMS instruction since the last instruction field change instruction was performed.
IF and DF Registers are loaded and

When the

INT IN PROG H is asserted, the contents of the registers are loaded into the

Interrupt Buffers at TP4.
Bits 5 through 8 represent the contents of the instruction field and the flag in the IF Register; bits 9 through

represent the contents of the data field in the DF Register.

2.10.2

Interrupt Buffer Transfer to Memory and Restoration

A simplified explanation of how the Interrupt Buffers could be stored in memory and restored to the Instruction
Field and Data Field Registers is illustrated in Figures 2-6 and 2-7. An RIB or GTF instruction creates the necessary gating signals to allow the instruction field and data field to pass through the corresponding output multi-

DATA BUS. The same instruction grounds the C1 line, which causes the contents
of the DATA BUS to be loaded into the AC Register. A DCA instruction transfers the contents of the AC Register to the corresponding addressed memory location. The next time the field
to be addressed, the TAD instrucplexers and be applied to the

tion returns the data to the AC Register and an

RTF instruction allows the corresponding bits to be loaded into

the Instruction Buffer and Data Field Registers at TP3.

The addition of PC, AC, and MQ handling allows nesting

of interrupts.

CONSOLE STATUS INDICATORS

01
X X X

3456789

NO
INT

IFO

INT
INH

IF1

IF2

DFO

DF2

INSTRUCTION FIELD

10
DF1

DATA FIELD
2

t
IND

IND

IND
8E-03I8

Figure 2-5

IF and DF Display Status During TS1

2-11

RESULT

2.10.3

Instruction Field Register Loading Operation

The Instruction Field Register loading operation is illustrated in the Instruction Field Register loading flow dia-

gram (Figure 2-8). The first four decision blocks represent
a go condition if any one of the blocks contain a status of
yes.

ENABLE OUTPUT

MULTIPLEXERS

SF-

•

DATA BUS

For example, KEY CONTROL is developed when the

operator depresses the EXTD ADDR LOAD key. The cor-

responding clock input is LOAD ADDRESS.

GROUND C1

DATA BUS

FETC H DC A

SAVE FIELD

trol, the next three conditions are tested.
|

—^MEMORY

If the

load-

ing of the Instruction Field Register is under program con-

An RTF instruc-

tion allows the Instruction Field Register to be loaded at

LOCATION X
TP4. Otherwise, the major states are tested.
EXIT TO
MAIN PROGRAM

WAIT FOR TADX

If the proces-

sor is in the FETCH state and not performing an RTF instruction, JMP or JMS is tested and finally MD3L is tested.
When MD3H is present (indicating direct addressing), the

Instruction Field Register will be loaded at TP4. Otherwise, a DEFER state with JMP or JMS is tested.

Note that

the Instruction Field Register is not loaded during a data
break.

—

AC
DATA BUS
RECEIVER GATES

The input is at TP4 to ensure that there is no ad-

dress mixup during the current memory cycle.

2. 1 0.4

Time-Share Operation of the System

Because much of the logic is shared between the time-share
operation and the memory extension operation, it may not
DATA 5-8DATA 9-H

•IB
- DF

be obvious what logic is specifically dedicated to the timeshare function.

The time-share portion operates in two modes as denoted
Figure 2-6

Interrupt Buffer Transfer

to Memory and Restoration, Flow Diagram

by the UF flip-flop (refer to the system block diagram presented in Figure 2-3).
1

When the UF flip-flop is in the logic

state, the system is operating in the user mode and a user

program is running in the central processor. When the UF flip-flop is in the logic 0 state, the system is operating
in the executive

mode and the time-sharing monitor is in control of the central processor.

The four instructions developed by the Time-Share Operations Decoder are used by the monitor in the executive

mode and are never executed by a user program. The trap logic is a monitoring device to assure the system that
When TRAP is developed, INT RQST is grounded and SKIP is en-

the user is programming valid instructions.
abled.

The monitor then takes over and examines the invalid instruction and determines what action must be

taken.

The UF flip-flop also plays an important role in monitoring for valid instructions. When the UF flip-flop is a 1

USER MODE L is developed and the grounded line, which goes to the processor, inhibits STOP and I/O PAUSE.
The processor is operating in the executive mode during the time that memory extension or time-sharing instruc-

The user mode begins when an SUF instruction has been completed. This sets the
USER BUFFER flip-flop and inhibits the processor interrupt until the next JMP or JMS instruction. At the conclusion of either of these instructions, the UF flip-flop is transferred to the Instruction Field Register. At that
time, the UF signal is applied to the processor I/O control output gating where USER MODE L is developed.
tions are being processed.

2-12

DF REGISTER

IF BUFFER

IFO

DFO DF1 DF2

IF2

IF1

BUFFER 6 DF REG

AC5-11

—MEM

LINK

NT
BUS

NO
INT

ION

SUF

SFO

(

SF2

SF1

INTERRUPT BUFFER A

INT

SF3

)

SUF

SFO

SF1

SF2

1 1

INTERRUPT BUFFER B

INHIB

CONT

SF'5

SF4

SF3

SF4

SF5

NOT GENERATED BY KM8-E

Figure 2-7

Interrupt Buffer Transfer to Memory and Restoration

The following is a summary concerning valid and trapped instructions:

FUNCTION NORMALLY:

AND
TAD
ISZ

DCA
JMP
JMS
most OPERATES

TRAPPED INSTRUCTIONS:
HLT

Monitor Return. Machine must not stop because all users

would be shut down.

OSR, LAS

Requires special action.

A user does not have his own Switch

IOT

Requires interpretation (usually a device code change) by the

monitor. For example, any user can use a KSF instruction
(octal 6031). If executed by the computer, this instruction

would test the flag of the console TTY (the operator). However, the monitor alters this instruction by changing the middle
6 bits to the device code of the user's TTY.

2-13

Figure 2-8

Instruction Register Loading, Flow Diagram

2-14

SECTION 4 DETAILED LOGIC
The following description represents an expansion of the Memory Extension and Time-Share Control system
block diagram given in Figure 2-3.

2.11

INSTRUCTION FIELD REGISTERS

The Instruction Field Registers and gating logic are illustrated in Figure 2-9. The major parts are the Input Multiplexer, Instruction Buffer, and Instruction Field Register.

the instruction field is to be changed, instruction CIF causes MD bits 6-8 to pass through the Input Multiplexer.

If the

instruction field is to be restored, instruction RMF causes the save field bits from Interrupt Buffer A to

the data is to come from the DATA BUS, the signal DATA IN gates in bits
DATA 5-8. Bit 5 holds the content of the UF flip-flop. The Instruction Buffer receives three bits. The same

pass through the Input Multiplexer.

signals that were used to gate the bits through the Input Multiplexer are used to load the Instruction Buffer at

TP3. The Instruction Field Register loads the inputs by DATA IN or during a JMP or JMS. The outputs are applied to the input gates of the Extended Address Output Multiplexer and Interrupt Buffer A.

2.12

INSTRUCTION FIELD OUTPUT MULTIPLEXER

The Instruction Field Output Multiplexer is illustrated in Figure 2-10.
trol gates.

consists of an 8235 IC and various con-

Data selection lines select either the instruction field or the save field which, in turn, is applied to the

DATA BUS. Signal IND L or instruction RIF selects the instruction field. Instruction GTF or RIB gates the conused to indicate the status of the UF fliptents of SUF and SFO through SF2 to the DATA BUS. Bit DATA 5
is

flop.

2.13

DATA FIELD LOGIC

The data field logic is illustrated in Figure 2-1 1
Field Register.

consists of an 8266 IC Input Multiplexer and an 8271 IC Data

Instruction CDF is used to select bits MD 6-8; instruction RMF selects save field bits SF3 through

SF5, which are to be restored from the Interrupt Buffer B. Signal DATA IN L gates in three DATA BUS bits,

DATA 9-1

The data field bits are loaded into the Data Field Register by DATA IN L or by CDF or RMF at LOAD ADDRESS
time or TP3.

2.14

DATA FIELD OUTPUT MULTIPLEXER

The Data Field Output Multiplexer is illustrated in Figure 2-12. Data Field bits DFO-2 and INT INHIBIT (1) H
are selected by IND L. This places these bits onto the DATA BUS during TS1 and into the Status Display on the
front panel.

2.15

The contents of the Interrupt Buffer can be selected by the GTF or RIB instruction.

DATA FIELD OUTPUT GATES

The Data Field Output Gates are illustrated in Figure 2-13. The contents of data field bits DFO-2 are applied to

DATA 6—8 when the RDF instruction is used.

2-15

o
CT3

C
CD

C
O

QQQQ

or
Ixl

1 <

ID
Q_

L"_
<0

°
2

O
,«
<°

°
2

2-16

DATA 5
RIB L

INO

—^

Hi
8235

SUF

4>
IFO
DATA 6

SFO

IF1
SF1

IF2
-

L
Figure 2-10

Instruction Field Output Multiplexer

2-17

DATA 8

DATA

Data Field Logic

Figure 2-1 1

l~8 235
I

ND L

INT INHIBIT (1) H

vw-

+ 5V

—°^i^^n>-|- DATA3
>'

DFO

DATA 9

SUF 3
I

SUF 4

DATA 10

—<3|^>

DATA
SUF 5 -^°T>
GTF
RIB

Figure 2-12

Data Field Output Multiplexer

2-18

INTERRUPT BUFFERS LOGIC

2.16

DFO
DATA 6

Interrupt Buffers A and B are illustrated in Figure 2-14.

Buffer A is used to store the contents of the instruction field
in the event of an

interrupt; Buffer B is used to store the con-

tents of the data field in the event of an interrupt.

DATA 7

Each time

an interrupt occurs, the buffers are loaded at TP4.

2.17

INTERRUPT INHIBIT LOGIC

When the processor is honoring an interrupt, INT IN PROG H
is asserted.

}DF L

This signal is asserted at +5V, and is driven posi-

tive by a load resistor.

Thus, anytime INT IN PROG H is to

be negated, the signal line is simply grounded. Within the

Figure 2-13

Data Field Output Gates

memory extension logic there is a period of time in which
INT IN PROG H must not be asserted; for example, when the processor has issued a CIF instruction and has not
yet encountered a JMP or JMS. These logical conditions are represented in the logic diagram illustrated in Figure
2-15. Signal
nal line

2.18

INT INHIBIT (1) H is carried to DATA 3 of the DATA BUS to report to the Status Display that sig-

INT IN PROG H has been negated, thereby inhibiting any interrupts.

INTERRUPT-BREAK DETECT LOGIC

The interrupt-break detect logic ensures that no critical operation, such as clearing of the IB, IF or DF registers
or loading the Save Field Register, is accomplished while a data break is taking place.

At the time an interrupt is

being honored, both of these operations must take place. The two signal lines representing these activities (INT
IN PROG H and MA, MS, LD CONT) are tested.

2.19

Refer to Figure 2-16 for the detailed logic.

The Instruction Buffer, the Instruction Field Register, and the Data Field Register will be cleared at TP4 (Figure
an interrupt and no data break is occurring, or if the machine is powered up.

2-1 7)

if there is

2.20

DATA IN LOGIC

The data in logic develops DATA IN L to load the memory extension registers or to allow bits 5-8 of the DATA

BUS to be gated into the instruction field logic and bits 9-1 1 of the DATA BUS to be gated into the data field
logic. Signal DATA IN L is asserted by the program when an RTF instruction is decoded, or under manual control during TS1

2.21

Refer to Figure 2-18 for the logic diagram.

USER FLAG LOGIC

The User Flag (UF) is used only when the time-sharing portion of this option is implemented. The UF logic
(Figure 2-19) is a D-type flip-flop that acts as a buffer in the same manner as the Instruction Buffer. Signal UF

LOAD H is generated by the instruction field loading logic when DATA 5 is a or SUF is asserted and clocked
in by either an RMF or RTF instruction at TP3. The UF flip-flop can be set by instruction SUF and cleared by
1

the instruction SUF and cleared by the logical conditions shown in Figure 2-19.

2-19

TO INSTRUCTION FIELD
OUTPUT MULTIPLEXER
SUF

SFO

SF1

SF2

SF2
SF1

TO INSTRUCTION
FIELD INPUT

SFO

MULTIPLEXER

SUF

(INT
(

PROG«MA,MS LOAD CNT) H

LOAD ADD + TP4

•

INTERRUPT
BUFFER A

MA, MS LOAD CNT) L
4-

(8271

)

TTTT

USER
FLAG

IBO

IB1

IB2

FROM INSTRUCTION
BUFFER

TO DATA FIELD

OUTPUT MULTIPLEXER
SF3

SF5

SF4

SF5

I TO DATA
SF4 } FIELD INPUT

MULTIPLEXER

JJL

—
LOAD ADD + TP4 MA, MS LOAD CNT) L —
(INT IN PROG MA, MS LOAD CNT) H
-

(

BUFFER

+ 3V

NTERRUPT
(8271

B
)

BDFO^ to EXT'D
ADDRESS

BDF1

BDF2

OUTPUT
I

MULTIPLEXER

AAA
TO DATA FIELD

OUTPUT GATES
DFO

Figure 2-14

DF1

DF2

Interrupt Buffers Logic

2-20

INT IN PROG. MA

MS LOAD CNT) HTP4 H-

OK H
d[(jmp+jms)] l

—

[f-MD3(JMP+JMS)]l

DATA

IN
N L
GIF

SUF

Figure 2-1 5

Interrupt Inhibit Logic

INT IN PROGRESS

MA, MS LD CONT

INT IN PROG, MA, MS

LOAD CNT

Interrupt Break Detect Logic

Figure 2-16

TP4 H (INT IN PROG MA, MS LOAD CNT
-

)

H -

RUN LIB, IF,

POWER OK H

Figure 2-17

2-21

DF CLEAR L

DATA IN

8E-0414

Figure 2-18

TP3

•

SUF L

RUN L

POWER OK H
TP3 H
CUF L

•

Data In Logic

>
>

r
UF
C

UF (1) H

LOAD ADDRESS H

TP3 H

RMF L

Figure 2-19

User Flag Logic

2-22

UF LOAD H

2.22

TRAP DETECT LOGIC

The trap detect logic (Figure 2-20) is used when the time-sharing portion of this option is implemented. When
it is

not implemented, the time-share disable circuit will contain jumpers that will hold the (0) side high and the

(1) side low.

Signal USER

MODE L will be high because UF (1) will be low. Signal TRAP

indicate an IOT (F.UM.6xxx) or special operate (F.UM.74x1

2.23

high if the MD lines

where bits 9 or 10 are 1s).

EXTENDED MEMORY ADDRESS LOGIC

The extended memory address logic (Figure 2-21

)

includes the output gates within the 8235 IC and the DF EN

and EMA DISABLE flip-flops with corresponding control logic. The output gates, IC 8235, are a multiplexer of

which the data selected for output is determined by the EMA DISABLE and DF EN flip-flops. The EMA

DISABLE flip-flop serves the same function as the MAC flip-flop in the M8310 CPU Control Module, and is used
to disable the output multiplexer at TP4 in the event of a data break.

The interrupt break logic signal clears the EMA DISABLE flip-flop at TP4 or when the machine is in the manual
mode. The DF EN flip-flop determines if the output data is the data field or the instruction field.

If the

proces-

sor is not doing a JMP or JMS instruction, but is in the DEFER state, the data field will be addressed during the

next machine cycle.
will

If the

processor is doing a JMP or JMS or is not in the DEFER state, the instruction field

be addressed.

[tTmE SHARE
DISABLE

USER INT F/F

INITALIZE

TNT ROST L

SKIP L

FtRAP DETECT LOGiC
MD3

3>i
n

MD9

MDIOJ

J
mdii

USER MODE L
UF (1) -

MDO MD1 -

'
FLUSERMODE

—

y
_i
Figure 2-20

Time-Share Trap Logic

2-23

2-24

SECTION 5 MAINTENANCE
The general procedures concerning preventive and corrective maintenance are given in Volume 1, Chapter 4.

When corrective maintenance is required, the technician should use the maintenance programs given in Section 2
of this chapter to determine the nature of the problem.

Refer to the option schematic, drawing number

E-CS-M737-0-1, for IC locations and pin numbers. Test points have been provided on the module to facilitate
troubleshooting.

SECTION 6 SPARE PARTS
Table 2-2 lists recommended spare parts for the KM8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

Table 2-2

Recommended KM8-E Spare Parts

DEC Part No.

Description

19-05575

IC DEC 7400

19-09705

IC DEC 8881

19-09615

IC DEC 8271

19-09935

IC DEC 8235

19-09934

IC DEC 8266

19-09594

IC DEC 8251

19-09667

IC DEC74H74

19-05547

IC DEC 7474

19-05577

IC DEC 7420

19-05576

IC DEC 7410

19-09686

ICDEC 7404
ICDEC74H00
IC DEC 384A
IC DEC6314A

19-09056

19-09486
19-09972

13-00365

Resistor 1K, 1/4W,5%

10-01610

Capacitor 0.01

10-05306

Capacitor 6.8 mF, 35V, 10%

2-25

MF DISK, 20%

Quantity

6
1

CHAPTER 3
MR8-E READ-ONLY MEMORY

SECTION 1
3.1

INTRODUCTION

READ-ONLY MEMORY DESCRIPTION

The MR8-E is a 256-word Read-Oniy Memory (ROM) option used in the PDP-8/E. The MR8-E consists of an

M880 Quad Module that is inserted into the OMNIBUS and an H241 Braid Board mounted on the M880 Module.
The thickness of the module and braid board requires that two spaces be allotted for this option on the OMNIBUS,
although the MR8-E plugs into only one of these spaces. Each ROM option occupies two pages (400 8 locations)
of the 32 10 pages (7777 8 locations) in each field.

The MR8-E can be located starting at the beginning of any even-

numbered page in any field, such as 0000 8 00400 8 or 64400 8
,

Note that the corresponding core memory loca-

tions cannot be used by the software while the MR8-E is installed in the OMNIBUS.

signed to the MR8-E is addressed,

When a memory location as-

ROM ADD L will be asserted which, in turn, disables core memory.

From a programming point of view, and as viewed from the OMNIBUS, the MR8-E is addressed the same way as
core memory (Paragraph 3.24, Volume 1 ). Within the MR8-E these 400 8 words are organized as 200 8

lines, each

running through or around 24 ferrite cores (two 12-bit words). Each drive line is terminated by a diode on one

end and by a switch tied to a decoder on the other end. The memory locations are selected by MAOO to MA1
and EMAOO to EMA02. The MR8-E is interfaced to the processor by the OMNIBUS.

SECTION 2 INSTALLATION
The MR8-E will be installed on site by DEC Field Service personnel. The customer should not attempt to unpack,
inspect, install, checkout, or service the MR8-E Module.

3.2

INSTALLATION

Perform the following steps to install the MR8-E Read-Only Memory:
Step
1

Procedure

Remove power from the PDP-8/E by turning Power Switch to OFF.
Ensure proper diodes are installed in the M880 Module to select the starting address
of

ROM (drawing CS-M880-0-1

Insert the MR8-E

(M880 and H241) into the OMNIBUS (refer to Table 2-3, Volume 1)

for module installation priority.

3-1

3.3

ACCEPTANCE TEST

Perform the following steps to check the MR8-E Modules:
Step

Procedure

Load ROM Test Tape Low (MAINDEC-8E-D1 JA-PB1 or ROM Test Tape High
(MAINDEC-8E-D1 JAPB2). Refer to diagnostic write up for correct loading procedures.

)

Allow the diagnostic to run for 20 minutes with no errors.

NOTE
Refer to Section 5 for the procedure to change

ROM contents

if errors

are found.

SECTION 3 SYSTEM DESCRIPTION
3.4

MR8-E BLOCK DIAGRAM

The MR8-E consists of an M880 Drive and Sense Module and an H241 Braid Board Assembly. The M880 Module
contains the logic for addressing 256 words of memory located on the H241 Braid Board Assembly.
is

addressed in the same way as PDP-8/E Core Memory (Paragraph 3.24, Volume 1).

If the

The MR8-E
MR8-E is placed in

the same field with a 4K core memory, the two pages of core memory with the same addresses as

accessed by the program.
of

ROM cannot be

the software tries to write in ROM, the new information will be lost and the contents

ROM will not be changed. When the MR8-E detects an address to which

(Figure 3-1) which disables core memory.

must respond it asserts ROM ADD L

The 400 8 words of the MR8-E memory are organized as 200 8 lines

with each line containing two words. The 200 8 lines run through or around 24 10 ferrite cores and sense windings
(Figure 3-2). Each of the 200 8 lines is terminated by a diode at one end and in 8 groups of 16i 0 lines tied to the

outputs of a BCD decoder at the other end.

3.5

ROM ADDRESSING

Addressing of the 400 8 locations is accomplished as follows.
a.

The three EMA lines and the four most-significant MA lines (MA00-MA03) are decoded in Address
Selection

AND gate within the MR8-E to determine whether the currently addressed location is within

the option.

The Address Selection gate consists in part of 14 10 diodes, seven of which must be removed

EMA and most-significant MA bits for which the MR8-E is active. If the
MR8-E is selected, a gate at the output of the Address Selection gate asserts (grounds) the ROM ADD L
line on the OMNIBUS, thereby disabling the core memory that would normally respond to that address.
In addition, a second output of the Address Selection gate (labeled FIELD L on the logic diagrams) en-

to define the combination of

ables decoding of the remaining
b.

MA lines.

MA04 through MA07 are decoded and select one of 20 8 (16 10

)

drivers, each of which is connected to

10 8 (8 10 diodes.
)

MA08 through MA10 select one output of the line select decoder which is a BCD-to-decimal decoder.
One of 10 8 outputs from the BCD-to-decimal decoder is selected and forward biases the diode selected
by MA04 through MA07 so that current will flow through the selected line and induce a signal in the
sense winding if it passes through the core. Data is taken from the MR8-E using high-permability ferrite
U- and l-cores mated to form a closed magnetic path.

The 200 8 lines run through or around the 24 10

U-cores, the 24 l-cores are wound with a 50-turn sense winding.

When current is driven through a selec-

ted line, which passes through the mated core, a 2.5V to 3.0V signal is magnetically induced in the

winding. The signal induced in the sense winding is fed to a DTL-type gate and clocked by a strobe
pulse.

If the

selected line passes around (not through) the mated core, no signal is induced in the sense

winding.

3-2

MA08, MA09,MA10^

FIELD L

SWITCH
DIODE
SELECT
LOGIC

BRAID

WORDS

BOARD

MA-00 TO MA-03,
ROM ADD L

EMA-00 TO EMA-02
OMNIBUS j
SIGNALS

MEMORY
ADDRESS
DECODER

STROBE
LINE
DRIVER
SELECT

MA04

FIELD H

MA07

MA11

WORD
SELECT

CLEAR L

LOGIC

MD DIR L

MEMORY

AND

Figure 3-1

Read-Only Memory Block Diagram

3-3

MD-00

TO MD-11

The selected line causes a 24-bit word to be read. MA1 1 controls which half of the addressed word is
The output of the DTL gates is clocked into a 1 2-bit Memory Buffer

applied to the Memory Register.
Register.
e.

FIELD H, NOT CLEAR Land MD DIR L enable the output of the Memory Register to the MD lines.

Figure 3-2

H241 Braid Board

SECTION 4 DETAILED LOGIC
The logic in the MR8-E is broken into functional groups for discussion purposes. The block diagram in Figure 3-1
should be used to understand the interaction of the groups of logic.

3.6

ADDRESS DECODER

The Address Decoder (Figure 3-3) receives bits MAOO through MA03 and EMAOO through EMA02 for decoding.
The 14 diodes (7 of which are removed) select the high-order address of ROM.

the

MA and EM A bits indicate
ROM can be accessed by

the selected address is within ROM FIELD L, ROM ADD will be asserted, so that only
the program.

FIELD L enables gates to allow MA04 through MA1 1 to be decoded and used to select a line driver,

switch, and word 0 or 1

3.7

SWITCH SELECT LOGIC

The switch select logic (Figure 3-4) decodes MA08 through MA1 0 and selects one of the groups of diodes on the
H241 Braid Board Assembly using the proper switch line. FIELD L is used to enable E26 AND gates and the output of the AND gates is applied to the 74145 IC. The 74145 IC is a BCD-to-decimal decoder that pulls one of the

output lines low when the 3-bit input is decoded. The output of E27 is applied to the 8 switches that enable the
selection of the proper diode and one of the 16 line drivers (Figure 3-5).

3-4

MA03 L

MA02

MA01 L

MAOO L

EMAOO L

EMA02

Figure 3-3

Address Decoder Logic

3-5

"(16 DIODES)

li2H3_
swooMA10

MA09L

MA08

FIELD L
Diodes located on H241 module.

Figure 3-4

Figure 3-5

Switch Select Logic

Line Driver Select Logic

3-6

^D121

3.8

LINE DRIVER SELECT LOGIC AND LINE DRIVERS

The line driver select logic (Figure 3-5) decodes MA04 through MA07 and selects one of the 16 line drivers. Each
line driver has 8 diodes in its collector circuit, each of which

is tied

to one end of the 8 switch lines on the braid

board (Figure 3-6). There are 16 line drivers, with 8 diodes each, to select 128 lines (256 words) on the braid
board.

The E12 AND gates are enabled by FIELD L; MA05 through MA07 are applied to E15 and E19. E15 and

E19 are BCD-to-decimal decoders that assert one output line for each input and cause the line driver to forward
bias 8 diodes.

MA04 is used to select a control input at pin D on E1 5 or E 19. When MA04 is 1 (low), E20 is dis-

abled and input D of E19 has a low enabling input that allows E19 to pull one output low and select one of its
line drivers.

When MA04 is 0 (high), E20 and E16 are enabled and input D of E15 has a low (enabling) input.

Note that each line driver has 8 diodes tied to 8 different switch lines in the diode matrix (Figure 3-6). When the
diode is selected by a line driver and the switch on the other end of a line is selected, current flows through that
line and induces a voltage in the sense windings of those cores that have a line passing through them.
lists the lines in

Table 3-1

the braid board and the two words associated with each line.

The diode tied to each line has the same numerical designation as the line, i.e., line 1 has D1 tied to one end.

3.9

SENSE LOGIC AND MEMORY REGISTER

The sense windings of the 24 ferrite cores are tied to DTL AND gates (Figure 3-7) on the M880 Module. As
stated previously, when current flows through the selected line a voltage is induced in the sense windings shown
as A1

through A1 1 for word 0, and B1 through B1 1 for word 1

MA1

applied to E26 allows one of the words

to be applied to the Memory Register when FIELD L and STROBE Lare applied to E24.
(sense winding A) is applied to the Memory Register; if MA1 1

is 1 ,

MA1

is 0,

word 0

word 1 (sense winding B) is applied to the

Memory Register.
The Memory Register is made up of 12 set-reset type flip-flops that hold the 12 bits of data until MD DIR L, NOT

CLEAR L and FIELD H are received. The result enables the AND gates and applies the contents of the Buffer
Register to the

MD lines.

SN7442
E15 AND E19

+ 5V

LINE

LINE 8
|

LINE 121

LINE 128
|

LINES AND DIODES INSIDE DOTTED LINE ARE ON THE H241
8E-0347

Figure 3-6

Line Drivers and Diodes

3-7

Table 3-1
Line and Switch Identification for ROM Addresses

Line

Number
i
i

Sw.

Line

Addresses*

Term

Number

ooo nni

Sw.
Addresses*

Term

on
ZU, 191
Z

H-Z

199
ZO
ZZ, 19^

9
Z

4*3
HO

1I Z*+, 1I

9
o
4

3
4

004 oor
006 \j\j
007

010,01

012,013
014,015

016,017
020,021

022,023

024,025

026,027

030,031

14
15

i
i

9R
ZO
19R
197
ZQ, Z /
1 on 1 oi
OU, O

1^9
Oc.

47
48
49
50

142,143

144,145

146,147

150,151

032,033

154,155

54
55
56

152,153

034,035
036,037

156,157

040,041

160,161

042,043

162,163

044,045

164,165

046,047
050 051

9
o
4

uo
R4
RR
RR
R7
RR
6Q

166,167
170 171
1 79
1o
IC.fl17^
1 74 1 7R
17R 177
900
901
ZUU,ZU

22
23

24
9R
26
97
28
29
30
31

32
on
OO
34

052 053
054 055
056 057
oro 061
06? Ofi^
064 ORR
Ofifi 067
070 071

0
i
i

072,073
074,075
076,077

UU,lUl

72
hi
to

102,103

35
36
37

104,105

74
75

106,107

110,111

38
39

112,113

9
z
o

m
1

OO
134 135
1

136,137

140,141

909 90^
904 90R
90R 907
910 911
91 9 91?
O
1

4
K
U

D
7

n
u
i
i

9
Z
q
\5

214,215
216,217
ZZUfZZ
222,223
I

R
1

0
1

224,225

226,227

230,231

232,233

114,115

234,235

116,117

236,237

*These addresses are within the MR8-E. To get the absolute address, add the starting address of the MR8-E to the MR8-E addresses, i.e.,

MR8-E starts at 4400, line 1 23 contains absolute addresses 4764 and 4765. 4764 is word 0 and 4765 is word 1
by Bit 11 applied to the MR8-E.

3-8

The word will be selected

Table 3-1 (Cont)
Line and Switch Identification for ROM Addresses

Line

Number

Addresses*

OA(\ OA 1

oZ
oo

^4Z,z4o
Z4*f ,z40

OH
OO
DO

9KO 9K1
9K9 ORQ

Term

105
106

320,321
322,323

107

324,325

Sw.

108

326,327

109

330,331

110

9R4. 9RR

lit
ill

332,333
334,335

9«n 9P1

1 1

336,337

340,341

342,343

344,345

114

z
o
o

I 1
I I

970 971
Z/U,Z/

979
97^
Zl Z,ZI
O
974 97K

5
1 1 c
lib

346,347

1
11/

350,351

352,353

354,355

1 1
I

p;
D

o
13

9R9 9R^
0£M 9RR
OCR OC7
ZOO,
ZD/
I

Addresses*

Line

Number

z
o
o

Z40,z4/

Sw.

Term

lift

96
97
98
99
100

122

362,363

304,305
306,307

123

364,365

124

366,367

101

310,311

125

370,371

102

312,313
314,315
316,317

126

127

372,373
374,375

128

376,377

276,277

120

356,357

300,301

121

360,361

302,303

103
104

*These addresses are within the MR8-E. To get the absolute address, add the starting address of the MR8-E to the MR8-E addresses, i.e.,
MR8-E starts at 4400, line 123 contains absolute addresses 4764 and 4765. 4764 is word 0 and 4765 is word 1 The word will be selected
by Bit 1 1 applied to the MR8-E.
.

3.10

CLEAR LOGIC

The clear logic (Figures 3-8 and 3-9) clears the Memory Register and enables gates to place data from the Memory
Register on the

MD lines of theOMNIBUS. The Memory Register

into the memory cycle) clearing the

cleared when RETURN H goes high (100 ns

CLEAR flip-flop.

At STROBE TIME, the CLEAR flip-flop is set, enabling the Memory Register output gates (Figure 3-7) to transfer
the contents of the Memory Register to the

MD lines, when MD DIR

asserted (MD DIR on the OMNIBUS is

low).

3.11

LINE SELECT DIODE MATRIX

The line select diode matrix (Figure 3-10) selects one of the lines which pass through or around the ROM core
and allows current to flow through one line for each address. One end of each line is tied to a switch; the other

end is tied to a diode. The diode is in the collector of a line driver (DR0 to DR15) and the selected diode is

3-9

WORD

MD 00

* EACH GATE ENABLES HALF OF THE SENSE GATES
** DOTTED LINES INDICATE MISSING LOGIC IDENTICAL TO THAT SHOWN.

Figure 3-7

Sense Logic and Memory Register

+ 5V

8E-0345

Figure 3-8

Clear Logic

3-10

Ons

100ns

200ns

300ns

400ns

500ns

600ns

700ns

800ns

900ns

[

•I
RETURN

STROBE

WRITE

CLEAR L

* Approximate

times

**For reference only

8E-0353

Figure 3-9

Read Timing Diagram

forward biased by the switch select logic to allow current flow through the line. Current flow through the line
causes a voltage to be induced in the sense windings of the cores through which the line passes. This voltage is

applied to the DTL logic (Figure 3-7) and gated to the Memory Register by MA1 1 and STROBE L.

SECTION 5 MAINTENANCE
The MR8-E diagnostic (MAINDEC-8E-D1JA-PB1 or MAINDEC-8E-D1JA-PB2) should be run when a ROM malfunction is suspected. Use the following procedure to change the contents of ROM or to correct errors.

Step

Procedure

Remove the H241 with cover and standoffs from M880.

With Side 2 of the H241 up, find the line that corresponds to the address of the word to
be changed. Each line contains two words, so the 128 lines contain 256 addresses (Table
3-1).

Cut the line to be changed.

Solder the new wire to the lug as follows:
a.

you are placing new words in these addresses, string the wire through all 24 cores

using all the tie down jumpers.

The 24 cores correspond to the two 1 2-bit words of
the line (Figure 3-2). For a logical 1, string the wire inside the "U" core; for a 0,
string the wire outside the core.
b.

Terminate the wire on the proper switch (Table 3-1).

you are correcting an error in the MR8-E, the diagnostic program will provide all

the information needed.

A typical typeout would be as shown in Table 3-2. For

this error, cut Line 5, replace it, and string wire through the cores as shown in the

The 24 bits shown correspond one-to-one with the
24 cores on the board, from left to right. The line should be terminated on SW4.
insert portion of the typeout.

an error occurs in the field, check the diode before replacing the line.

Check electrical continuity.

3-11

(DRO)11 Dl

y. D2

11 D9

% D10

3![

D13

t D15

(ORD-

t D12

$. D11

-013 c

>12c

X 016
H6

15 c

(DR2) -

I D17

18 C

% D21

X D20

t 019

t D18

I—oi7<

>20C

19 C

X D23

X D22

21 <

D24

220—<>

22C

>— 24C

(DR3) -

t D25
25C

V D26
—0 26C

X 027

X D34

X D35

X D28

>27C

•

28 o—

29C

t D32

% D31

t D30

029

>30c

>32c

31 <

(DR4) -

X D33

>34C

»33C

£ D36

'35C

>36C

D43

D44

$ D39

X D38

037

•370-4

>38C

D40

—O40O—

'39<

(DR5) y_

D41

—041 O-Hi
(DR6)

X D42

t D45

44C

>43C

046

D48
—^5480—*

X D47

—O46 0-4

45c

47 C

•

^ D50

X D49

£ 052

X 051

>50o

>49C
(DR7)

'420

X 053

056

X 055

D54

-O560-4

'55C

>54C

>53c

»52C

>51 <

X 057

X D58

X D59

3fc

X 061

D60
560c

>59c

'58C

)57C

062

3fc

—0620—

•61 <

D63

D64

—0640-H

>63C

(DR8) -

X 065

>65C

(DR9)

D66

3fc

—066C

f D68

D67

>68C

>670-H»

069

D70

70 C

>69C

072

071

--071 o-4

o 72o

D75C

-074C

$ D76

X D75

074

D73

X D77

X 080

X D79

D78

^8QO

'79C

7SO-HI

»77C

>76 C

(DR10)

X 081
>81

X D83

X D82

3fc

I D86

$ D85

D84
>84C

>83c

>82C

'85C

L-o 86<

D93

D94

I D88

$ 087
>87C

—OS
588C

(DR11) -

t D89

>89C

D90

t D92

D91

—091 O—

—O90C

3|t

»93C

>92C

X 095

>95C

94 c

096

—096C

•

(DR12)

% D97

X D98

>97C

'98C

D105

V D106

D99

—099

D100

—O100O—

D102

0101

—O101O

— 102O
01

I D10D4

D103

—O103O—

I—O104
01040H>

(DR13) 3L

—O105O-*

D107

—O106O—

—O107O-4

D114

D115

0108

—O108O-H

3[
t

0109

X 0111

D110

—O109O—

110O-4

D1<12

>1 1 1 c

I—011 2o—

(DR14) -

£ 0113

>113o->

—01140—

X 0116

•1150—

120

X 0119

X D117

t 0118

>117o

>118Q

•1160-4

>1190-

120oh»

(DR15)

D121

D122

01210

—O1220—

(SW0)

(SW1)

D123

D124

—01240-

-01230-

(SW3)

(SW2)

0125

D126

—01250

>—01260

(SW4)

(SW5)

D127

—01270-4
(SW6)

D128
)128o-<»

(SW7)
8E-0344

Figure 3-10

Line Select Diode Matrix

3-12

Table 3-2
Typical Error Typeout

ADDR

Good

Bad

Driver

Line

Diode

7010

3635

3637

Insert

011110011101

010101010100

Term

SW4

SECTION 6 SPARE PARTS
Table 3-3 lists recommended spare parts for the MR8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

Table 3-3

Recommended MR8-E Spare Parts

DEC Part No.

Description

15-05321

Transistor DEC 4258

15-03100

Transistor DEC 3009B

11-60114

Diode D664

19-10047

IC DEC 74145
ICDEC 7442
IC DEC 8881
IC DEC 846
ICDEC 74H74
ICDEC 384
ICDEC 6380
IC DEC74H11
ICDEC 7402
IC DEC 7410
IC DEC 7400

19-10046
19-09705

19-09688
19-09667

19-09486
19-09971

19-09267
19-09056

19-05576
19-05575

3-13

Quantity

2
1

10
1
1

1
1
1
1

2
1

1
1

CHAPTER 4
MI8-E HARDWARE BOOTSTRAP LOADER

SECTION 1
4.1

INTRODUCTION

GENERAL DESCRIPTION

The MI8-E Bootstrap Loader option uses a 32-word Read-Only Memory (ROM) with diodes that can be arranged
to accommodate any program up to 32 words in length.

The Bootstrap Loader option is available in the following

configurations:

RIM Program

Option Designation

MI8-E

Unencoded

MI8-EA,B
MI8-EC
MI8-ED
MI8-EE
MI8-EF
MI8-EG
MI8-EH

Paper Tape

TC08 DECtape
RK8
Typeset

Edu System (low)
Edu System (high)
TD8-E DECtape

Each configuration contains a uniquely encoded ROM in the form of a specific Read- In Mode (RIM) program.

Without this option, RIM would be toggled into memory by the operator at the programmer's console. The RIM
loader instructs the computer to receive and store, in core, data from any of the above peripherals in RIM-coded

format.

The MI8-E Bootstrap Loader is contained on one quad-size module, designated M847, that plugs directly into the

OMNIBUS. All signals enter and leave the module via the OMNIBUS.
4.2

EQUIPMENT REQUIREMENTS

The following basic equipment is necessary to operate and maintain the MI8-E Bootstrap Loader:
a.

b.
c.

d.
e.
f.

PDP-8/E Computer
ASR-33 Teletype or Equivalent

Low- or High-Speed Paper-Tape Reader
Low- or High-Speed Paper-Tape Punch
MI8-E Bootstrap Diagnostic
Bootstrap Loader Option

4-1

4.3

COMPANION DOCUMENTS

The following documents and publications are necessary for the operation, installation, and maintenance of this
option:

4.4

PDP-8/E & PDP-8/M Small Computer Handbook - DEC, 1 972

PDP-8/E Maintenance Manual — Volume 1

Introduction to Programming — DEC, 1 972

DEC engineering drawing, Bootstrap Loader Option, number M847-0-1

MI8-E Bootstrap Loader Diagnostic Manual, MAINDEC-8E-D1 IA-D-(D)

SOFTWARE

The MAINDEC-8E-D1 IA-D diagnostic is used to troubleshoot and verify the operation of the MI8-E Bootstrap
Loader option in all configurations shown in Paragraph 4.1

The diagnostic is available in a low- and high-core version. The version used to test an MI8-E Module will depend
on the memory locations utilized by that particular module. The low-core version occupies and uses memory locations 0200-1777, the high-core version occupies and uses memory locations 4200-5777.

Use the version that

does not conflict with the memory locations of the bootstrap block for the MI8-E Module under test.

SECTION 2 INSTALLATION
The MI8-E Bootstrap Loader option is installed on-site by DEC Field Service personnel. The customer should
not attempt to unpack, inspect, install, checkout, or service the equipment.

4.5

INSTALLATION

Perform the following procedures to install the MI8-E option:

Step

Procedure

Remove the module from the shipping container.

Inspect the module for any apparent damage.

Verify that the initial address, field address, and starting address jumpers are correct ac-

cording to Table 4-1

Verify that the diode matrix is properly cut.

Connect the module to a convenient OMNIBUS slot. The module should be located
reasonably close to the MM8-E Modules.

4.6

CHECKOUT

Perform the following procedures to checkout the MI8-E option:

Step
1

Procedure

Perform acceptance tests provided in Paragraph 2.3, Volume 1.

4-2

Step

Procedure

If this verification

was not performed satisfactorily, refer to Section 5 for troubleshooting

procedures.

Make proper entry on user's log that the acceptance test for the MI8-E option was performed satisfactorily.

Table 4-1

MI8-E Bootstrap Loader Option Encoding Scheme
unto cp

MI8-E

MI8-EA

MI8-ED

Option

Unencoded

RK8

Paper Tape

ULUtape
INITIAL

MI8-EE
Typeset

MI8-EF

MI8-EG

MI8-EH

Edu Sys

TD8-E

Low

High

Dectape

7300

7737

7554

0023

7756

7737

6007

ADDRESS

6014

7600

6007

7771

6007

1312

Data

0776

6774

6751

6014

7604

4312

7326

1374

6745

6011

7510

4312

1337

6766

5025

5360

3343

6773

2376

6771

7200

7106

6766

5303

5340

5360

6733

7106

6771

6777

6011

7240

5031

6012

5344

3726

5356

1354

7777

7420

1376

2326

3361

3773

7777

5357

5343

5303

1361

1354

5756

7600

5732

3371

3772

4356

6603

2000

1345

1375

3357

6766

1345

5376

3367

7754

6032

7755

6031

0600

5357

0220

6036

6771

7106

7006

3373

6622

1300

4356

5352

6774

7777

5752

6771

Data
Starting

6011

0331

5357

1327

6016

7640

5376

7106

5315

7777

7006

2321

7510

5712

5357

5374

7354

7006

7756

6031

6011

7747

5367

0077

6034

6016

7400

7420

7777

3776

3376

5356

5357

0220

7737

6034

7420

n
it

3376
\

6031

7006

3776

5315

6776

5357

5367

7577

6014

6036

7510
5374

7577

6032

5356
0

7737

7754

7703

Address

4-3

1110

7300

SECTION 3 OPERATING PROCEDURES
The operating procedures for the Bootstrap Loader are as follows:
Step

Procedure

RUN lamp is on, depress the HLT key and observe that the RUN lamp is off.

If the

Depress and raise the SW key.

Observe that the RUN lamp is again illuminated.

SECTION 4 PRINCIPLES OF OPERATION
4.7

GENERAL DESCRIPTION

The relation of the Bootstrap Loader and the CPU is similar to that of the operator's console and the CPU. Both
the loader and the panel must:
a.

Initialize the CPU.

Load Address.

Load Extended Address.

Deposit instructions in sequential locations.

Load starting address of the program just deposited.

Start the program.

to define the first address in which

}

to deposit instructions

Because the operation of the Bootstrap Loader is closely tied in with the operation of the processor, the reader
should have a thorough understanding of the processor control signals. Detailed theory of the processor and

memory is given in Chapter 3, Volume 1

;

the control signal description is provided in Chapter 9 of the PDP-8/E

& PDP-8/M Small Computer Handbook.
A summary description of the control signals necessary to accomplish the six operations listed above is given in
the following:

Operation
Initialize (Bootstrap)

Affect on CPU

Assert

Ground:

POWER OK H (Pin

BV2)

Causes the CPU's MA Control flipflop to clear.

Also causes the CPU's

timing generator to generate.
Initialize (Panel)

INITIALIZE H (Pin CR1)

INITIALIZE H, clearing the AC,
Link, all flags, and the Interrupt and

Break systems.

Load Initial Address

Ground:

LA ENABLE L (pin

BM2)

Loads the address placed on the data lines into the

CPMA register.

Place initial address onto the

data lines of the OMNIBUS
Pulse:

PULSE LA H (Pin DR2)

(continued on next page)

4-4

Operation

Affect On CPU

Assert

Load Extended Address

Ground:

KEY CONTROL L

Loads the addresses placed on bits

6-8 and 9-1 1 of the DATA BUS
into the IF and DF of the Memory

(Pin DU2)

Place extended address bits onto Data 6-8 and Data 9-1
Pulse:

Deposit (used by panel)

Extension Control, Type KM8-E, if

one is in the machine.

PULSE LA H (Pin DR2)

Ground:

KEY CONTROL L

Causes one memory cycle to occur.

MS, IR DISABLE L (Pin CV1)

Word on DATA BUS is deposited,
and PC is incremented. Machine

Place bits to be deposited onto

stops at end of memory cycle.

(Pin DU2)

DATA BUS.
Pulse (low):

MEM START L

(Pin AJ2)

Same as Deposit above, except
KEY CONTROL L (Pin DU2)
goes high during TS3 of compu-

Deposit (used by bootstrap)

Same as above, except that the machine continues to run.

ter's cycle.

Same operation as Load Initial Address except for the word placed on the

Load Starting Address

DATA BUS.
Start Program

Pulse (low):

MEM START L

Starts program.

(Pin AJ2)

To minimize the logic needed for the MI8-E, an extra Load Extended Address operation takes place just before
starting the program.

4.8

Hence the complete sequence of operations is:

Initialize the CPU, Bootstrap, and all system devices.

Load Initial Address.

Load Extended Address.

Deposit 32 words into memory.

Load Starting Address of the bootstrap program just deposited.

Load Extended Address.

Start the bootstrap program.

MAJOR PORTIONS OF THE MI8-E

A block diagram of the major portions of the MI8-E is shown in Figure 4-1 When power is applied to the com.

puter, critical control flip-flops within the MI8-E are initialized so that the MI8-E is inoperative and the computer

can run normally.

If the switch

labeled

SW on the operator's console is moved to the "down" position and then

to the "up" position, the MI8-E will operate.

NOTE
SW should be left in the "up" position when the MI8-E
is not being used. If SW is left in the "down" position,
the MI8-E will operate if the machine is stopped and the
console's OFF/POWER/PANEL LOCK switch is moved
to the PANEL LOCK position.

4-5

DATA
LINES
OF THE

OMNIBUS

12-BIT BY

32-WORD

DIODE MATRIX

DATA
OUTPUT
GATES

32-BIT SHIFT REGISTER

I. F,S

ADDRESS
JUMPERS

Figure 4-1

4.8.1

ADDRESS
MULTIPLEXER

MI8-E Block Diagram

Address and Data Information

Address information is stored in three sets of jumpers denoted as follows:
Designation
10—11 1

Function
10 is the most-significant bit. The address encoded in the
jumpers
the first of 32 successive locations into which instructions will be loaded by the

Initial address.
is

MI8-E.

S0-S1 1

F2, F1, FO

Starting address. SO is the most-significant bit. This address is the address at which
the MI8-E will start the program after the bootstrap program has been stored.
Field bits.

F2 is the most-significant bit. These bits are loaded into both the IF and

DF of the Memory Extension Control, Type KM8-E.

4-6

In all cases, the presence of address jumpers indicates a binary 0; the absence

of a jumper indicates a binary 1.

Unencoded MI8-E boards are shipped with all jumpers in place.
Data to be deposited in memory is encoded by the presence (binary 0) or absence (binary 1) of diodes in a

12-bit

by 32-word matrix. The positions of words and bits within words are clearly indicated in etch on the board; the
presence or absence of diodes and jumpers for standard bootstraps is shown on the engineering drawings.

4.8.2

Sequence of Operations

When SW is operated while the computer is on but not running, the MI8-E's timing and control logic is activated.
The MI8-E first grounds POWER OK H to initialize the computer. Simultaneously, it clears the 32-bit shift regisThe timing and control logic then loads and F addresses into the CPU and

ter that drives the diode matrix.

Extension Control, respectively, by enabling the appropriate address multiplexer and then placing signals onto the

OMNIBUS. These signals have already been described in Paragraph 4.7. The MI8-E then shifts a 1 into the first
bit of the 32-bit long shift register, enables the matrix data output gates, and starts the
processor's timing chain.
Thus, the contents of the first word in the matrix are placed on the DATA BUS. Control signal MS, IR DISABLE L,

applied to the OMNIBUS, causes this word to be written into memory.

The KEY CONTROL L signal causes the
next sequential address to enter the CPMA, KEY CONTROL L is allowed to go high during TS3 of the processor's

cycle so that the processor continues to run.

At the end of each memory cycle (TP4) the single 1 is shifted down

the shift register, and a 0 is shifted into the first bit of the register. This process continues until all 32 words have

been deposited.

When the 1 reaches the last bit of the shift register, control circuitry causes the processor to stop. The timing of
the MI8-E is restarted. After loading the "S" and "F" addresses into the CPU and Extension Control, the processor is again started and the MI8-E's job is done.

4.8.3

Bootstrap Timing (Figure 4-2)

A timing diagram illustrating the primary timing and control signals within the bootstrap, as well as the processor
timing, is shown in Figure 4-2.

4.9

The development of each signal is shown in the detailed logic.

DETAILED LOGIC DESCRIPTION

The following paragraphs present portions of the MI8-E logic.

All illustrations are interrelated and, therefore,

should be considered collectively. The sequential operation of each circuit is presented in the system description.

4.9.1

Bootstrap Timing Logic (Figure 4-3)

A timing chain is created in the timing logic by connecting, in series, four time-delay flip-flops designated D1
through D4. The 74123 IC has a retriggering characteristic that makes an automatic restart capability possible.

However, the restart loop is concerned only with D3 and D4 and is controlled by the logical conditions of one
flip-flop designated

ACTIVE and a second flip-flop designated DATA.

Refer to Figure 4-4 for details about the 74123 IC.

The restart operation makes use of the last line in the truth

table, which states that the one-shot will initiate a timing cycle if the

A and B inputs are enabled and the Master

Reset input (C) is brought from low to high.

Again referring to Figure 4-3, the logic to the right of D1
the GO flip-flop.

used to ground POWER OK H and serves to control

GO will set when D1 times out only RUN L not asserted (the machine is stopped), RUN L
POWER OK H, which would otherwise stop the processor timing.
Therefore, once the bootstrap
activated, GO remains set until processor timing begins. RUN L results and clears
the GO flip-flop.
if

also prevents the bootstrap from grounding
is

4-7

4-8

4-9

5V
R EXT

EXT

H
14(6)j

15(7)

2(10)

LTV-

_ Q
13(5)

Q
4(12)

T
c

3(11)

NOTE:
Pin numbers not in parentheses are for delay

;

those within parentheses are for delay 2.

OUTPUTS

INPUTS
A

t
H

1
L

| TRANSITION

FROM HIGH TO LOW

| = TRANSITION

FROM LOW TO HIGH

_T~|_

OUTPUT WAVEFORMS(DURATION DETERMINED
BY THE R AND C ATTACHED TO THE ONE-SHOT)
8E-0378

Figure 4-4

74123 Logic Diagram and Truth Table

A positive-going transition on the SW line sets D1 for a period of
feedback loop remove any switch contact bounce.
(if

1 .2 fxs.

On the input line, the RC network and

On the output of D1 (1), the circuitry asserts POWER OK L

RUN L is not asserted) and asserts CLEAR GO L when RUN L is asserted. Because CLEAR GO L is connected

to the clear side of GO, the net result is:
a.

If the

computer is running, ignore the output of D1 (0).

the computer is stopped and D1 triggers, set GO.

The conditions upon which CLEAR GO L is generated are shown graphically in Figure 4-5.
Signal

POWER OK H goes low shortly after D1 (1) goes high. This causes the M8330 Timing Module to create a

560-ms INITIALIZE H pulse to clear the processor and options.
1 .2-/xs

In the meantime, D1

delay times out. This causes D1 (0) to go high; this transition clocks GO.

becomes reset because the

GO (0) L half-qualifies the input

to D2. At the end of the 560-ms INITIALIZE H pulse, the trailing edge sets D2 for a period of 180 ns. The D2
(0) negative-going output sets the

for a period of 500 ns.

ACTIVE flip-flop and the DEP flip-flop and the trailing edge of D2 (0) sets D3

At the trailing edge of D3 (1 ), the negative-going transition sets D4.

A restart path beSignal LOAD

ginning with D4 (1) H and gated by ACTIVE (1) H and DATA (1) Lgenerates LOAD PULSE H.

PULSE H (trailing edge) clocks the FIELD flip-flop on the first pass and clocks the DATA flip-flop on the second
pass. The trailing edge of each LOAD PULSE H causes D3 to start another timing cycle. Once the DATA flipflop is clocked, DATA (1 H inhibits LOAD PULSE H and hence another restart operation until LAST is set (fol)

lowing the 32-word dump operation). The last D4 (1) H with DATA (1) H asserts MEM START L.

4-10

MEM START L

(1)

(LO IF EITHER A or B HIGH)

(LO ONLY IF A and B HIGH)

—

SW
*H a
RUN L IS HIGH
IF

CLEAR GO L

+3V
+3V

CLEAR GO L

WHEN RUN LOV

+3V

IF PWR OK H
RUN L (H)

CLEAR GO L

—*L S

WIDTH
DETERMINED
EXTERNALLY
NOTE:
The

letters

A-I refer to Figure 3

Figure 4-5

asserts

CLEAR GO Signal Waveform Analysis

RUN L in the timing module and RUN L asserts CLEAR GO L, which then resets the GO flip-flop. The

timing chain remains inactive until LAST

4.9.2

WORD H sets the LAST flip-flop and with TP4 creates RESTART.

Bootstrap Control Logic (Figure 4-6a and b)

Four flip-flops are shown in Figure 4-6a. LAST, ACTIVE, and DEP are cleared by POWER OK H being low.
ACTIVE (1) low clears SECOND. ACTIVE (0) now high generates SYSTEM CLEAR L. SYSTEM CLEAR L
clears the FIELD flip-flop, the

DATA flip-flop, and the 32-bit shift register.

When the timing chain reaches D2, D2 (0) sets flip-flops DEP and ACTIVE. ACTIVE (1) H now half-qualifies
STOP Land DEP (1) H generates MS, IR DISABLE L FIELD (1) Land ACTIVE (0) L generate NOT FIELD H.
This signal, combined with SECOND (0) H, asserts INITIAL ADD L Signal ACTIVE (0) L, combined with

DATA (0) H, asserts LA ENABLE L.
When the timing chain reaches D4 and generates LOAD PULSE H, PULSE LA H is asserted.

This loads the initial

address into the CPMA.

When D4 times out (at the trailing edge of LOAD PULSE H), FIELD is clocked. FIELD
H
half-qualifies
the
DATA
flip-flop clock input and FIELD (0) L qualifies FIELD TO DATA BUS.
(1)

With FIELD set, ACTIVE set and DATA reset, FIELD TO DATA BUS, KEY CONTROL Land LA ENABLE L
cause the memory field to be addressed. The trailing edge of LOAD PULSE H also asserts RESTART and the
timing chain is again activated.

4-11

D2(0)L

MS IR DIS L

7474
DEP

T
D

SECOND (0)
INITIAL

NOT FIELD H

ADD L

STARTING
ADD L

SYSTEM
CLEAR L

7474
SECOND
TP4

LAST WORD
(0)

PWR

— D2(0)

7474
ACTIVE

OK H

@ TP4

PWR
OK H

7474
LAST

START MEMORY H
LAST WORD H
D4(0)

^>H>

DATA (0)

SHIFT

CLOCK H

*—
C|

\_ FIELD
DATA BUS
J

NOT
FIELD H

KEY
CONTROL L

ADDRESS ENABLE
j

ENABLE L

DATA ENABLE

MEM
START
SYSTEM.
CLEAR

SYSTEM
CLEAR

7474
D4(1 )

PULSE LA H
LOAD PULSE H

M70ft

+ 5V o

Figure 4-6

Wv-

Bootstrap Control Logic

4-12

The next LOAD PULSE H at the trailing edge clocks the DATA flip-flop and again asserts RESTART.

DATA (1

H now half-qualifies MEM START. When D4 is again set, D4 (1) asserts MEM START L D4 (0) L, combined
with DATA (0) L generates START MEMORY H and SHIFT CLOCK H.

SECOND is clocked by the trailing edge
of START MEMORY H in preparation for STARTING ADDRESS. Signal MEM START L starts the processor
timing and SHIFT CLOCK H activates the 32-bit shift register. The 32-word dump operation now begins. Signal
LAST WORD H is asserted when the 32nd word is reached. LAST is clocked at TP4 and LAST (1 qualifies
STOP L. LAST (0) at TP4 asserts SYSTEM CLEAR L and restarts the timing chain. SYSTEM CLEAR L again
)

DATA and FIELD.

clears flip-flops

With SECOND set, the next address must be the starting address.

When the starting address is loaded into the
CPMA, the timing chain goes through two additional restarts for the field address and Memory Start. When

MEM START L

again qualified, START

MEMORY H

The trailing edge of START MEMORY H
SYSTEM CLEAR L. This prevents a second 32-

asserted.

this time clocks the ACTIVE flip-flop and ACTIVE (0) asserts

word dump and removes all bootstrap signals from the OMNIBUS.

4.9.3

Initial/Starting Address Jumper Network and Output Logic (Figure 4-7)

The initial and starting addresses, determined by jumpers
12-bit word for each type of address.

for initial address and S for starting address, provide a

Removing a jumper causes a 1 of the corresponding bit to be placed onto

the DATA BUS. Otherwise a 0 will be submitted. The 7235 IC multiplexer selects either the initial address or
the starting address, depending upon which control line is asserted low.

4.9.4

Extended Memory Field Output Logic (Figure 4-8)

The extended memory field output logic is jumper-selectable to provide either a 1 or 0 on each corresponding bit.
Signal FIELD

DATA BUS H, developed in the bootstrap control logic, is used to apply 1s and 0s to the DATA

BUS.

4.9.5

12 x 32 Diode Matrix and Control Logic (Figure 4-9)

A partial illustration of the 12 x 32 diode matrix and control logic is shown in Figure 4-9. The diode matrix is
arranged in 32 columns and 12 rows to accommodate 32 1 2-bit words. Each word is applied to the output logic
gates by 8-bit parallel-out serial shift registers with the first word being applied by SHIFT CLOCK H during TS1.

Four 74164 ICs, each providing 8 outputs, are used to sequentially bias the diodes corresponding to the selected
Each time SHIFT CLOCK H is received, the 74164 IC shifts to the next sequential output line. Carry to
the next IC is accomplished by the last IC output line, except for the output line labeled "31 ". When 31 has been
row.

reached, LAST
in

WORD H

generated and applied to the LAST flip-flop. Signal SYSTEM CLEAR L is generated

the control logic to clear the shift registers.

SECTION 5 MAINTENANCE
The general procedures concerning preventive and corrective maintenance are given in Chapter 4, Volume 1

When corrective maintenance is required, the technician should use the maintenance program given in Section 2
of this chapter to determine the nature of the problem.

4.10

TROUBLESHOOTING

The option schematic, drawing number E-CS-M847-0-1 must be referred to for IC locations and pin numbers.
,

Test points are provided on the module to facilitate troubleshooting.

4-13

START ADD L

DATA

BUS
DATA 0

DATA

DATA 2

DATA 3

—

^y> wv-i

6
5

+5V o+3V o-

DATA 5

DATA 6

13 |D-

DATA 7

8235

+5V o-

+3V o-

-15V o15
+ 5V o+ 3V o-

-15V o-

"9"

o+ 3V o-

DATA 8

+ 5V

vw—

-15V o-

—

+ 5V o-

+3V o-

8235

vw-J

-15V o-

2 |D-

DATA 10

DATA 11

+ 5V o-

+ 3V o-15V ch-

H^32)
H^lTp

+ 5V o-

+ 3V o-

-0^2

-15V o-

Figure 4-7

vw-lf-

WW^
wv-Jf

15
14

Initial/Starting Address Jumper Network

4-14

VvV

+ 5V o

DATA 06

DATA 09

+ 5V o

DATA 07

DATA 10

+ 5V °

DATA 08

J7
FIELD —*> DATA BUS H

Figure 4-8

Extended Memory Field Output Logic

TS1SHIFT CLOCK

SYSTEM CLEAR

D
31

C
A
741 64

B
23

D
7

74)1164

™164

LAST WORD H

ST WORD

nBATAn
1

•
•
•

<I-W*—

-32 WORDS
+5V
DATA ENAB H

Figure 4-9

2 X 32 Diode Matrix

4-15

BUS
DATA 00

MI8-E Bootstrap Diagnostic Program

4.10.1

The operation of the MI8-E Bootstrap Loader should first be verified by the MI8-E Bootstrap Diagnostic Program,

MAINDEC-8E-D1 1 A-D, with corresponding MAI ND EC operating procedures.
4.10.2

Direct Memory Access Control Signal Verification

Because the bootstrap loader uses direct memory access control signals in a manner similar to the operator's console (front panel), addressing memory and depositing information must be accomplished in the same manner.

Proper operation of signals such as PULSE LA H, LA ENABLE L, KEY CONTROL L, MEM START L, and
STOP L can be verified by performing the following procedure at the programmer's console:

Step

Procedure

Load Address 7777.

Load Address 0000.

Load Extended Address 7.

Load Extended Address 0.

Deposit bit 1 1 then 10 ... 0 individually.

MA should equal 0014.

Load Address 0000.

Exam. You should see bit 11, then 10 ... 0 until the MA = 0014.

Turn Rotary Switch to the state position.

Depress and hold LOAD ADDRESS.

1 1

Put SW up.

SW indicator should be off.

Put SW down.

Deposit in location 0/7240

No major state should be lit (F,D,E).

SW indicator should be on.

1/7402.

Load and start location 0.

Turn Rotary Switch to AC position.

Depress CLEAR.

Load location 0. Deposit 5000.

Load and start location 0. Run light should be on.

Depress SINGLE STEP.

If the
If

AC should = 7777.

AC should = 0000.

Run light should be out.

above procedures were completed successfully, the problem is in the MI8-E Bootstrap Loader hardware.

the procedures indicate a malfunction, the MI8-E should be removed and the procedure tried again; the prob-

lem is in the programmer's console, the CPU or the Memory Extension Control.

4.11

BOOTSTRAP HARDWARE TROUBLESHOOTING ANALYSIS

A very convenient troubleshooting aid is the Programmer's Console Status Display. The mere presence or absence
of any one of the addresses used in the Bootstrap Loader option can localize the problem by the process of

4-16

elimination.

If the

problem is that the option fails to continue after the initial address is loaded and the RUN

lamp does not come on, the probable cause is the FIELD flip-flop or associated circuitry. However, if the field
address is loaded but the RUN lamp does not come on, the probable cause is the ENABLE flip-flop or associated
circuitry.

can be assumed that all of the logic leading up to the logic that controls MEM START functions

properly.
If

the RUN lamp comes on but the 32-word dump operation does not begin, it can be assumed that the DATA

flip-flop functions and the problem is somewhere in the 12 x 32 diode matrix logic.

No dump might indicate

that the first shift register is malfunctioning.
If the

RUN lamp comes on and the dump operation takes place but then fails to stop, the problem is in the Shift

The problem also causes the most-significant MA lights to run at half intensity. Examination of memory shows that all locations have been cleared. The reason for the failure is that the single 1
Register or LAST flip-flop.

which should shift down the 32-bit shift register has been lost, probably because of a malfunctioning 74164 IC.

A malfunction will also occur if a 74164 IC picks up a bit. In this situation, fewer than 32 words will be deposited.
Some of these words will be the OR of two or more of the words encoded in the diode matrix.
When an incorrect word is deposited, the faulty diode can be located by determining which word and bit fails.
This is easily accomplished by addressing the bootstrap initial address and depressing the EXAM key. When the
rotary switch is in the
If

MD position, each of the 32-bit words can be examined.

bootstrap timing operates properly, the SINGLE STEP and CONTINUE keys may be used to single-step the

bootstrap. This technique may be used to find out if data is being deposited correctly.

SECTION 6 SPARE PARTS
Table 4-2 lists the recommended spare parts for the MI8-E. These parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

Table 4-2

Recommended MI8-E (M847) Spare Parts

DEC Part No.

Description

Quantity

19-10436

IC DEC 74123

19-09004

19-05575

IC DEC 7402
IC DEC 7474
IC DEC 8235
IC DEC 74164
IC DEC 7400

19-09705

IC DEC 8881

19-09686

IC DEC 7404

19-09485

IC DEC 380

19-09486

IC DEC 384

15-03100
11-00114

Transistor DEC 3009

13-01423

Resistor 6.8K, 1/4W, 5%

10-00006

Cap., 0.01 fxF, 100V, 20%

19-05547

19-09935
19-10041

Diode D664

4-17

1
1
1

1
1

CHAPTER 5
MP8-E MEMORY PARITY

SECTION 1
5.1

INTRODUCTION

MP8-E DESCRIPTION

The MP8-E Memory Parity option adds the circuits required to generate, store, and check the parity of memory
words. The MP8-E consists of three quad boards, which are inserted into the OMNIBUS.

An H220 Memory

A G227 Memory X-Y Driver is used to provide word select
A special G105 Sense-Inhibit Module, which also contains IOT decoding, is used.

Stack is used to store parity for all words in memory.
currents.

This option expands the memory system from 12 to 13 bits per word.

When a word is written into memory, its

parity is computed, and odd parity (odd number of binary ones in the 13-bit word) is generated and stored in the

13th, or parity, bit.

When a word is retrieved from memory, the parity of the 13-bit word is checked.

even

parity is detected, a memory error has occurred.

Much of the MP8-E is identical to the MM8-E 4K Core Memory described in Chapter 3, Section 4, Volume 1

The

MP8-E is discussed in Chapter 7 of the PDP-8/E & PDP-8/M Small Computer Handbook. The reader should have
a thorough understanding of this material before proceeding.

One major difference exists between the MP8-E and its description in the PDP-8/E & PDP-8/M Small Computer
Handbook. The MP8-E is disabled whenever it encounters Read-Only memory. Thus, the initialization process
described in the handbook is unnecessary.

The CEP instruction (used for diagnostic purposes) will work, as de-

scribed, as long as the next EXECUTE cycle deals with a location that does not ground the
line on the

OMNIBUS.

ROM ADDRESS L

(This EXECUTE cycle can even be the result of an indirect reference to a nonexistent

memory field, if desired.)

SECTION 2 INSTALLATION
The MP8-E will be installed on site by DEC Field Service personnel. The customer should not attempt to unpack,
inspect, install, test, or service the equipment.

5.2

INSTALLATION

Use the following procedure to install the MP8-E:

Step

Procedure

Ensure power is off.

Install the MP8-E on the position

Install the four

indicated in Table 2-3 of Volume 1

H851 Edge Connectors between the three modules.

5-1

ACCEPTANCE TEST

5.3

To check the MP8-E, run the MP8-E diagnostic program, MAINDEC-8E-D1 DA. The program should be run 15
minutes for each 4K MM8-E in the machine; e.g., if the machine has 16K of memory, run the diagnostic for 1
Refer to the program writeup for instructions on how to run the program.

hour.

SECTION 3 PRINCIPLES OF OPERATION
Parity in the PDP-8/E is handled in a somewhat unconventional manner.

The conventional method of handling

parity is to use a special 13-bit memory stack and sense-inhibit system in each of the memory fields.

In the

PDP-8/E, however, the standard memory, Type MM8-E, is used for data and instruction storage, regardless of

whether the system contains the parity option. When parity is desired, an additional memory is added. This
special memory handles the parity bit for all possible memory fields.

The advantage of this method of handling

parity is that no special memory stack is required.

Figure 5-1 is a block diagram of the MP8-E.

The lower half of this figure is identical to the lower half of Figure

3-33 in Volume 1 only the portion above the broken line is different. Eight of the twelve memory bits are used,
;

corresponding to the eight possible fields. The FIELD signal into the G227 X-Y Driver is permanently enabled.
Hence, during each memory cycle all eight parity bits are read and rewritten into the parity core memory.
Field select gating decodes the extended address bits (EMA 0, 1, and 2) and

MD DIR L. The three EMA lines

determine which of the eight parity bits are to be examined and possibly modified. All other bits are automatically rewritten from the local parity sense register.

Sense Register.

MD DIR L

low, the selected bit is rewritten from the

high, however, the parity of the twelve

MD lines is written into the parity memory.

The selected bit read from the parity core memory is combined with the bits on the twelve MD lines.

If parity is

erroneous, the ERROR flip-flop is set. The ERROR flip-flop can be interrogated by a SKIP instruction, and can

cause an interrupt. lOTs permit clearing of the Error flag, enabling the disabling of parity interrupt, and intentional reading of even parity for diagnostic purposes.

SECTION 4 DETAILED LOGIC
The G227 X-Y Driver and H220 Memory are discussed thoroughly in Volume 1. No attempt will be made in
this chapter to duplicate that discussion.

In addition, certain portions of the

parts of the G104 described in Volume 1.

These portions are:

G105 are identical to corresponding

Strobe Control Logic

(Vol. 1, Paragraph 3.27.8)

Sense Amplifiers

(Vol. 1, Paragraph 3.27.9)

Sense Flip-flops

(Vol. 1, Paragraph 3.27.10)

Inhibit Drivers

(Vol. 1, Paragraph 3.27.12)

Current Control Circuit

(Vol. 1, Paragraph 3.27.13)

-6V Supply and Slice Control

(Vol. 1, Paragraph 3.27.14)

These parts will not be described here in detail.

5.4

FIELD SELECT GATING

The field select gating (Figure 5-2) connects the output of a SENSE flip-flop to the input of the corresponding
Inhibit Driver.

The output of gate A must be low in order to rewrite a 1 into the parity memory.

5-3

TO INHIBIT DRIVER,
BIT 0

.NHI BIT

WRITE PARITY L

ENABLE H

TO SEVEN

OTHER
CIRCUITS

MEM OUT H
i

(H IF

MD DIR L IS L)

READ PARITY L

EMA 2

1V-

(H=1)

EMA 0-

—
Figure 5-2

OUTPUT OF SENSE
FLIP-FLOP 0

8251

Field Select Gating

5-4

The EMA bits are buffered from the OMNIBUS and applied to the input of an 8251 Binary-to-Octal Decoder.

One of the output lines of the 8251 is low for any combination of EMA bits.

All outputs of the 8251 are in-

verted and applied to portions of the field select gating logic.
If the

FIELD 0 H line in Figure 5-2 is low (field 0 is not selected), gates A2 and Care disabled. The output of

gate B is high, enabling gate A1

Thus, the output of SENSE flip-flop 0 is applied, via gate A to the input of the
f

Inhibit Driver, writing the previously read bit back into memory.
If the

FIELD 0 H line is high, Field 0 has been selected. The output of SENSE flip-flop 0 is gated onto the

READ PARITY L bus via gate C. The source of information for the Inhibit Driver is now a function of MD DIR L.
If

MD Dl R L

low during the latter half of the memory cycle (as it is for all fetches and non-autoindexed defers),

gate B is enabled and the SENSE flip-flop provides the rewrite data.

MD DIR L

gate A2 is enabled, and WRITE PARITY L provides the data for the Inhibit Driver.

high, gate A1

disabled,

A low on WRITE PARITY L

writes a 1 in the parity bit.

5.5

PARITY GENERATOR

The heart of the Parity Generator is the 74180 8-bit parity generator IC which is shown in Figure 5-3. Two of
these ICs are cascaded to form the 12-bit gated parity generator shown in Figure 5-4. Line A is high if a 1 has
been read as the parity bit from memory. As will be discussed in Paragraph 5.6, the ODD PARITY H line is

sampled part way through the memory cycle, before MD DIR L can go high. During the latter half of the memory
cycle, if

MD Dl R L goes high, odd parity

sent to the selected Inhibit Driver via the WRITE PARITY L line.

(The state of WRITE PARITY L is ignored by the field select gating if MD DIR L is low.)

CONTROL H
5.6

EVEN PARITY

normally low, as will be described in Paragraph 5.8.

ERROR FLIP-FLOP AND GATING

Before discussing this logic in detail, a review of MD DIR L and its ramifications in the machine cycle is necessary,

MD DIR L

is a

signal that indicates the source of information on the

MD lines. At the beginning of every

memory cycle MD Dl R L is low, causing the contents of the currently active memory's Sense Register to be placed
on the MD lines. At TP2, MD Dl R L may or may not change.

D cycle.
a

will

not change during an F or non-autoindexed

will change on all other cycles unless grounded by an option other than the

CPU (for example, during

BREAK cycle with data direction from memory to peripheral). In any event, if MD DIR L remains low after

TP2, no modification of memory is possible and the PDP-8/E may well be performing a "fast" 1 .2-jus cycle.

MD Dl R L goes high after TP2, the PDP-8/E

definitely performing a "slow" 1 .4-/xs cycle and is most likely

modifying memory.
In a fast cycle, the

MD lines have just about changed state by the leading edge of TP2, and there

insufficient

time for the Parity Generator to settle. During such cycles, the parity decision must be deferred to the trailing
edge of TP2 in order to gain 100 ns more time for the Parity Generator to settle. Since MD Dl R L cannot change,
there is no danger that the information on the MD lines will change.
In a slow cycle, the

MD lines have set up 200 ns before TP2. The parity decision must be made at the leading

edge of TP2, since MD DIR L may well change and place new information (the contents of CPU's MB Register)

on the MD lines.

The ERROR flip-flop and its gating are shown in Figure 5-5. Assume that the ERROR flip-flop is cleared, and
that the odd parity is received from the parity generator logic. At the leading edge of TP2, the SLOW flip-flop is

clocked. At the trailing edge of TP2, the FAST flip-flop is clocked. Since no parity error has occurred, both
flip-flops remain cleared.

5-5

MEM OUT H
(LOW IF MD DIR L IS HIGH)

READ PARITY L
{FROM FIELD SELECT GATING)

F
MDOO H

MD01 H

EVEN

ODD

I ODD

MD02 H

MD03 H

MD04 H

Z EVEN

MD05 H

EVEN

ODD

MD06 H

MD07 H

I ODD

MD08 H

MD09 H

MD10 H

MD11 H

—
—

Z EVEN

r
EVEN PARITY CONTROL H
(FROM SPECIAL IOT CONTROL)
(NORMALLY LOW)

Figure 5-4

Parity Generator

5-6

ODD PARITY
TO ERROR

(

FLIP-FLOP GATING)

WRITE PARITY L
TO FIELD SELECT
GATING
(

ODD PARITY
(FROM PARITY
GENERATOR)

(TO SKIP GATING)

SLOW

PARITY ERROR H

MEM OUT L

"(TO INTERRUPT GATING)

FAST

TP2 L-

C Q

CLR ERROR L
(FROM IOTDECODER)

Figure 5-5

ERROR Flip-Flop and Gating

Now assume that the ODD PARITY H line becomes low during a fast cycle. MEM OUT L is low and MEM OUT H
is high, since these lines are controlled by MD DIR L. The ODD PARITY H line, therefore, is low at the trailing
edge of TP2, when the FAST flip-flop is clocked. Gate A is enabled, presenting a high signal to the D input of the

ERROR flip-flop, and simultaneously requesting an interrupt. The SLOW flip-flop may have been set at the leadlow.
ing edge of TP2, but gate B is disabled because MEM OUT L
is

Last, assume that the ODD PARITY H line becomes low during a slow cycle. At the leading edge of TP2, the
SLOW flip-flop is clocked and set. MD DIR L goes high, the result of a flip-flop in the CPU's timing generator being clocked by TP2. Therefore, MEM OUT H goes low, disabling gate A; MEM OUT L goes high, enabling gate B.
The MD lines change, the Parity Generator starts to respond, and the FAST flip-flop clocked at the trailing
is

edge of TP2. The state of the FAST flip-flop is ignored because gate A is now disabled.
Regardless of the type of cycle, the D input of the ERROR flip-flop is high well before TP3, allowing an interrupt
request to be generated during the current memory cycle (if the interrupt system is enabled).

At the trailing edge

of TP3, the ERROR flip-flop is clocked, setting the ERROR flip-flop. During all succeeding memory cycles, the

D inputs to both the FAST and SLOW flip-flops are high, maintaining the error condition. The three flip-flops
remain set until CLR ERROR L is generated in the IOT decoder logic (discussed in Paragraph 5.7).

CLR ERROR

L clears FAST and SLOW at the leading edge of TP3. At the trailing edge of TP3, ERROR (its D input is now low)
is

clocked and thus cleared.

ROM ADDRESS L is low, gates A and B are both disabled and PARITY ERROR H, therefore, low. No indisabled so that any previously detected
terrupt request
made. Also, the clock input to the ERROR flip-flop
is

error will not be lost.

5.7

IOT DECODING AND SKIP, INTERRUPT GATING

A summary of the lOTs for the MP8-E
is

given in Table 5-1

The logic is shown in Figure 5-6. The device code

decoded by a 314 gate in a manner similar to any OMNIBUS decoding scheme. As in any internal device, the

5-7

device must ground INTERNAL I/O L when it sees its device code to inhibit operation of the KA8-E.

Decoding

of the IOT operation is done by an 8251 Binary-to-Octal Decoder.

The EPI L and DPI L signals are used to set and clear, respectively, the RE (Interrupt Enable) flip-flop. The
I

CMP L and the SMP, CMP L signals are ORed together, gated with TP3, and the result used to clear both the FAST
and SLOW flip-flops in the ERROR flip-flop and gating logic. As was explained in Paragraph 5.6, the ERROR
flip-flop is then cleared at the trailing edge of TP3. The SMP L and the SMP, CMP L signal is ORed together and
the result ANDed with ERROR (1) to drive the SKIP L line of the OMNIBUS. The SKIP L line is also grounded
any time the SPO L line is grounded.

The one remaining output of the 8251 the CEP L line, is used to enable the special IOT control described in the
,

following paragraph.

NOTE
This IOT decoding scheme is somewhat special, and

should not be used as an example of general I/O de-

coding design.

Table 5-1

MP8-E IOT Summary
Octal

Mnemonic

6100

DPI

Disable MP8-E interrupts.

6101

SMP

Skip if no parity error.

Description

6102

Not used.

6103

EPI

Enable MP-E interrupts.

6104

CMP

Clear parity error flag.

6105

SMP, CMP

Skip if no parity error, clear error flag.

6106

CEP

Check for even parity. Complement the
read parity but write odd parity in the

next EXECUTE cycle only. Used for
diagnostic purposes.

Execution to a ROM

address results in no operation.

6107

5.8

SPO

Skip if MP8-E is in machine.

SPECIAL IOT CONTROL

The CEP instruction gating requires additional comment. As shown in Figure 5-7, CEP ANDed with TP3 sets the

DAE flip-flop, causing one input of gate A to go low. The next time the computer's major state becomes
EXECUTE, OMNIBUS signal E L goes low. Gate A fully enabled, generating EVEN PARITY CONTROL H and
causing the output of gate B to go low. At the leading edge of TP2, the output of gate B goes high again; DAE
clears; and EVEN PARITY CONTROL H is negated.
is

EVEN PARITY CONTROL H drives one input of the Parity Generator, causing the MP8-E to intentionally read
wrong parity to test the MP8-E logic. Since EVEN PARITY CONTROL H is negated at TP2 (before the memory
starts to rewrite), odd parity is written into the parity memory.

5-8

INTERRUPT ENABLE
(IRE) FLIP-FLOP

MD03 H
MD04 H MD05 LMD06 H MD07 HMD08 H-••

DEVICE

INTERNAL I/O L

I/O PAUSE L-

ERROR (1

MD09 H

)

EPI L

SMP, CMP L

CEP L

TO SPECIAL
IOT CONTROL

-4>

Figure 5-6

—[>>

IOT Decoding and Skip, Interrupt Gating

DAE
E L-

TP2

ITIALIZE L

EVEN PARITY CONTROL H
(TO PARITY GENERATOR

CEP-TP3 L

)

Figure 5-7

Special

5-9

IOT Control

SECTION 5 MAINTENANCE
The MP8-E diagnostic program is a particularly good test of core memory stacks. If a stack operates properly in
the MP8-E, it is virtually certain to operate properly in any MM8-E, unless there is a problem with one of the four
bits that the MP8-E does not use.

The MP8-E diagnostic should be run as a regular part of system maintenance.

Diagnostic messages and the program listing should serve to pinpoint any commonly encountered malfunctions.

The same procedures as described under memory troubleshooting in Paragraph 4.7, Volume 1 are applicable.
Note that the standard memory checkerboard programs are insufficient tests of the MP8-E, since a checkerboard
pattern of all 1s and all Os is used.

The odd parity of all Os is 1. Likewise, the odd parity of all 1s is 1. The strobe

adjustment procedure for the MP8-E is the same as for the MM8-E, with the exception of the checkerboard pro-

gram used.

SECTION 6 SPARE PARTS
Table 5-2 lists recommended spare parts for the MP8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

Table 5-2

Recommended MP8-E Spare Parts

DEC Part No.

Quantity

Description

12-10043

Rotary Switch

16-09651

Transformer 8010

16-09996

Transformer 6501

16-09478

Transformer 1775

16-10031-0

Delay Line, 100 ns

13-10032

Resistor, 16.9 ohm, 6W, 1%

13-02858

Resistor, 100 ohm, 1/8W, 1%

13-02956

Resistor, 196 ohm, 1/8W, 1%

13-04858

Resistor, 348 ohm, 1/8W, 1%

13-02953
13-03114

Resistor, 750 ohm, 1/8W, 1%

13-02871

Resistor, 1.21K ohm, 1/8W, 1%

Resistor, 1Kohm, 1/8W,

13-04833

Resistor, 1 .96K ohm, 1/8W, 1%

13-04856

Resistor, 4.64K ohm, 1/8W, 1%

13-04885

Resistor, 9.09K ohm, 1/8W, 1%

13-02941

Resistor, 14.7K ohm, 1/8W, 1%

13-03156

Resistor, 34.8K ohm, 1/8W, 1%

13-05128

Resistor, 56.2K ohm, 1/8W, 1%

13-05252

Resistor, 68.1 K ohm, 1/8W, 1%

13-10071

Thermistor, 1K, 1%

11-05275

Diode D672

11-00114

Diode D664

11-09991

Zener Diode 1/4M6, 8AZ1

19-10010

Diode Pack DEC 2501

(continued on next page)

5-10

Table 5-2 (Cont)

Recommended MP8-E Spare Parts

DEC Part No.
15-02155
15-01881

Description

Quantity

Transistor DEC 1008

Transistor DEC 2219

1
1

15-03100

Transistor DEC 3009B

15-10062
15-09649

Transistor DEC 3734

15-10015

Transistor DEC 4008

15-05312
15-03409-01

Transistor DEC 4258

Transistor DEC 3762

Transistor DEC6534B

19-05575
19-05590
19-09004

IC DEC 7400

IC DEC 7401

IC DEC 7402

19-09686

IC DEC 7404

19-05580

IC DEC 7450

19-05547

IC DEC 7474

19-10724

IC DEC 74180

19-09057

IC DEC74H10

19-09267

IC DEC74H11

19-05586
19-09967

IC DEC74H40

19-09704

IC DEC 314

19-09485

IC DEC 380

UC\s I

*-r

n \J\J

IC DEC 74H74

19-09486

IC DEC 384

19-09594

IC DEC 8251

19-09705

IC DEC 8881

5-11

PART 3
REAL-TIME CLOCK OPTIONS

CHAPTER 6
REAL-TIME CLOCK OPTIONS

SECTION 1

INTRODUCTION

Three real-time clock options are available for use with the PDP-8/E. The DK8-EA and DK8-EC are similar; each
consists of a clock frequency source and control logic contained on a single quad module that plugs into the

OMNIBUS. These two clock options cause program interrupts of the PDP-8/E at predetermined intervals that
are not subject to program control. The options can be used by the programmer to sample processes or to count
events. The DK8-EP, a more sophisticated clock option, provides a large amount of program control.

It provides

the means to measure and/or count intervals and events in different ways. This option is discussed in detail in the

LAB 8-E Maintenance Manual. Only the DK8-EA and DK8-EC are discussed here.

SECTION 2 BLOCK DIAGRAM
The difference between the DK8-EA and DK8-EC options is the way in which the clock frequency source operThe DK8-EA derives a clock frequency of 100 Hz (for 50-Hz primary power) or 120 Hz (for 60-Hz primary
power) from a power supply ac voltage. The DK8-EC derives a clock frequency of 1 Hz, 50 Hz, 500 Hz, or 5 kHz

ates.

from a 20-MHz crystal-controlled oscillator. Because the options are similar in all other respects, the logic description pertains to both, except when the clock frequency logic is discussed.

Reference designations on logic

symbols, E3, E12, for example, are for reference only. They may or may not coincide with the reference designations on a specific schematic drawing.
Figure 6-1

is a

block diagram of the DK8-EA/C. The control logic consists of the select logic, the INTERRUPT

flip-flop logic, and the clock flag logic.

The clock frequency is provided by the clock logic.

When an IOT instruction causes I/O PAUSE L to be asserted by the CPU Timing Generator, the option select
logic decodes bits MD-03 through MD-11. The INTERNAL I/O L signal is asserted to direct the positive I/O bus
interface to ignore the IOT instruction. The three instructions that pertain to the DK8-EA/C are 6131, 6132,
and 6133. 6131 and 6132 are used in the INTERRUPT flip-flop logic where they set and clear, respectively, the

INTERRUPT flip-flop.

If this

flip-flop is set, the clock flag is logically connected to the interrupt system.

Upon

receipt of an interrupt request, the computer begins to execute the interrupt servicing routine to determine the
identity of the requesting device.
logic asserts SKIP L.

When the 6133 instruction in the servicing routine is decoded, the clock flag

At the same time, the CLOCK FLAG flip-flop is cleared. The computer then proceeds to

the subroutine associated with the Real-Time Clock option. Both the INT RQST L and SKIP L signals are negated.

The next clock pulse asserts INT RQST L again and the procedure is repeated. Each succeeding clock pulse
causes an interrupt request until the 6132 instruction clears the INTERRUPT flip-flop.

6-1

INTERNAL I/O L

I/O PAUSE L

MD03-11

6131

SELECT

6132

LOGIC

INTERRUPT

CLOCK FLAG
LOGIC

F/F LOGIC

INT RQST L
SKIP L

CLOCK
LOGIC

OMNIBUS SIGNALS

Figure 6-1

Real-Time Clock (DK8-EA, DK8-EC), Block Diagram

SECTION 3 DETAILED LOGIC
6.1

SELECT LOGIC

The select logic is shown in Figure 6-2. The SELECT signal is asserted by NAND gate E5 when a 613X instruction
is

decoded. The SELECT signal, in turn, asserts INTERNAL I/O L, which causes the positive I/O bus interface to

ignore the IOT instruction.

The SELECT signal is gated with bits MD-09 through MD-1 1 to provide instruction

6131, 6132, or 6133.

6.2

INTERRUPT FLIP-FLOP LOGIC

The INTERRUPT flip-flop logic is shown in Figure 6-3. The flip-flop, E11B, is cleared by INITIALIZE; it can be
set by the first clock pulse following power turn-on.

This flip-flop remains set until cleared by the 6133 instruc-

tion, as is discussed in Paragraph 6.3.

The first TP1 pulse to be generated after E1 1 A is set causes flip-flop E7 to be set; the 1 -output of E7 provides
the desired high level at one input of NAND gate E9. The other input of the gate is from the 1 -output of the

INTERRUPT flip-flop.
INT RQST L.

If the select

logic decodes 6131 , the

INTERRUPT flip-flop is set at TP3 and E9 asserts

The 6132 instruction is used to disable the interrupt capability of the option.

It,

like the 6131 instruction, is

contained in the background program and, when decoded by the select logic, clears the INTERRUPT flip-flop at

TP3.

6.3

CLOCK FLAG LOGIC

The clock flag logic is shown in Figure 6-4. When 6133, which is usually located in the interrupt servicing routine,
is

decoded by the select logic, NAND gate E9B in the clock flag logic asserts SKIP L (E7 is set at TP1 following

power turn-on). At TP3, the CLOCK FLAG flip-flop is cleared. Simultaneously, the CPU SKIP flip-flop, which
is

conditioned by SKIP L, is set. This action causes the program counter to be incremented during TS4. Thus,

the instruction following 6133 is skipped and the next instruction that is performed is the first instruction of the
real-time-clock subroutine.

At TP1 of this instruction, latch E7 in the clock flag logic is cleared, negating both

6-2

8E-0160

Figure 6-2

Select Logic

INT RQST L and SKIP L. The next interrupt request occurs when the CLOCK FLAG flip-flop is again set by a
clock pulse and the following TP1 pulse causes E7 to be set.
Naturally, the time required for the service loop must be less than the clock period.

free-running.

Furthermore, the clock is

Hence, the program must be able to handle two nearly simultaneous clock interrupts when the

CLOCK INTERRUPT flip-flop is enabled. Consider what happens if the clock is enabled just before it is ready
to generate a clock pulse.

The enabling process generates an interrupt and the CPU may still be executing the first

clock subroutine when the option requests the second program interrupt.

this occurs, the interrupt servicing

routine is entered immediately after the first clock subroutine is exited, and the second execution of the subroutine occurs just after the first. Thus, an uncertainty of one count is always present because of the unknown clock

phase.

6.4

6.4.1

CLOCK LOGIC
DK8-EA

The clock logic for the DK8-EA is shown in Figure 6-5. The DK8-EA connects to the 28- Vac output of the H724
or H724A Power Supply via the cable supplied with the option.

The cable connects to the option with an 8-pin

connector (2 pins are not used). Each ac input is wired, via the board etch, to an adjacent pin so that the 28 Vac
is

not dead-ended (the KP8-E Power Fail and Auto Restart option also uses the 28-Vac output of the power supply;

both options are in the system, one is connected directly to the power supply, while the second is connected to

J1 of the first).

6-3

6132

TP3-

SELECT

INT RQST L

SELECT
°

TP1

0 E11A 1
CLOCK FLAG
DEC 7474

NOTE:
See Vol.1 Appendix A for details of

CLOCK

+3.5V

DEC7474IC

Figure 6-3

INTERRUPT Flip-Flop Logic

The circuit consists of a full-wave rectifier, a clamp, and a Schmitt trigger. The rectified ac voltage is clamped to

+5V by D1 to prevent damage to the E 12 IC. E12 is wired as a Schmitt trigger and its output is a reasonably
well-shaped square wave with a pulse repetition frequency that is twice the frequency of the primary power
source.

6.4.2

DK8-EC

The clock logic for the DK8-EC is shown in Figure 6-6. The basic clock frequency, 20 MHz, is provided by a
crystal-controlled oscillator (see the option schematic). This frequency is divided by a factor of four by the two
J-K flip-flops, E17 and E18 (when both the J and the K inputs are high, the 1 output is changed with each positive transition at the C input).

The 5-MHz clock frequency is applied to a chain of DEC 7490 decade counters,

each counter except the last is wired to divide by ten; the last counter is wired to divide by five. The output of
counter E4, E8, E12, or E21 can be selected by connecting a jumper wire, as illustrated in Figure 6-6. (The option is manufactured with an etch connection from the output of E21 to the terminal that connects to the

CLOCK FLAG flip-flop; if a clock frequency of other than
jumper from the terminal to the desired flip-flop output.)

6-4

Hz is desired, cut the etch connection and wire a

CLOCK-

+ 3.5V-

CE11 AC-

CLOCK
FLAG

E7
DEC
7475

DEC
D 74741

E11BO)INT RQST L

Figure 6-4

Clock Flag Logic

TO H724
OR H724A

Figure 6-5

Clock Logic DK8-EA

6-5

CLOCK

CRYSTAL-

CONTROLLED
TRANSISTOR
OSCILLATOR

Figure 6-6

Clock Logic, DK8-EC

SECTION 4 MAINTENANCE
General instructions concerning preventive and corrective maintenance are given in Chapter 4, Volume 1

When

corrective maintenance is required, use the MAINDEC-8E-D8AA maintenance program to determine the nature

of the problem.

The option schematics, E-CS-M883-0-1, E-CS-M882-0-1 E-CS-M860-0-1 and E-CS-M51 8-0-1
,

must be referred to for IC locations and pin numbers. Test points are provided on the option to facilitate troubleshooting.

SECTION 5 SPARE PARTS
Table 6-1 lists the M882/M883 spare parts. Spare parts can be obtained from any local DEC office or from DEC,

Maynard, Massachusetts.

Table 6-1

Recommended DK8-EA/DK8-EC - (M882/M883) Spare Parts

DEC Part No.
19-9705

19-9704

19-9485
19-9051

19-9050

19-9004
19-5589
19-5576
19-5575
19-5547

19-9486

Description

Quantity

DEC 8881
DEC314
DEC 380
DEC 7490
DEC 7475
DEC 7402
DEC 7470
DEC 7410
DEC 7400
DEC 7474
DEC 384
(continued on next page)

Table 6-1 (Cont)

Recommended DK8-EA/DK8-EC - (M882/M883) Spare Parts

DEC Part No.

Description

(M883 only)

18-9880

Crystal

16-9651

Pulse Transformer (M883 only)

iu-yb/o

Capacitor 0.047 juF, 16-15 + 20%

10-1610

Capacitor 0.01 juF, 100V, 20%

10-0016

Capacitor 100 pF, 100V, 5%

10-0014

Capacitor 68 pF, 100V, 5%

10-0011

Capacitor 47 pF, 100V, 5%

10-0006

Capacitor 10 pF, 100V, 5%

10-1765

Capacitor 0.005 nF,

6-7

Quantity
1

PART 4
POWER-FAIL OPTION

CHAPTER 7
KP8-E POWER-FAIL AND AUTO-RESTART

SECTION 1 INTRODUCTION
The KP8-E Power-Fail and Auto-Restart option monitors the computer's primary power source and initiates a
controlled shut-down sequence if a power failure occurs. This power-fail sequence protects the operating program

by storing the contents of the PC Register, AC Register, MQ Register, and the Link in known memory locations.

When normal primary power is restored, the KP8-E automatically restarts the computer in location 0000.
The Power-Fail and Auto-Restart option consists of the M848 quad module which is inserted into the OMNIBUS
and connected to the computer ac power supply by a 7007128 power cable. The PDP-8/E supplies 28 Vac and
the PDP-8/F and PDP-8/M supply 56 Vac.

The 56 Vac input is reduced to 28 Vac by removing a jumper (W2)

on the M848 module.

SECTION 2 M848 BLOCK DIAGRAM
The KP8-E block diagram is shown in Figure 7-1. The power monitor logic checks the PDP-8/E power supply
28 Vac output or the PDP-8/F and PDP-8/M 56 Vac power supply output which reflects the condition of the
primary power source.

If line voltage drops

below a predetermined minimum value, the UP signal is negated

andthePWR LOW flip-flop is set, asserting the OMNIBUS INT RQST L signal.

Filter capacitors in the power

supply guarantee continued operation for 1 ms; this is sufficient time for the interrupt request to be recognized

and the program interrupt routine to be carried out (because of the time limitation, the KP8-E SPL instruction,
Skip on PWR LOW flag, 6102, should be the first status check made by the program interrupt routine).

SECTION 3 M848 DETAILED LOGIC
7.1

SELECT LOGIC

The select logic is shown in Figure 7-2. When the SPL instruction (6102) is decoded, the logic asserts the

INTERNAL I/O L signal that causes the positive I/O bus interface to ignore the IOT instructions. The status
of the PWR

LOW flip-flop

signal is asserted.

is checked; if the flag is set, indicating a power failure has occurred, the SKIP L
The program then skips the next sequential instruction and jumps to a subroutine that begins

executing the power-fail routine.

7-1

I/O PAUSE

SELECT
LOGIC

MD03-1

INTERNAL I/O

6102 (SPL)
SKIP L

PWR
L0W

INT RQST

IND
KEY CONTROL L
•LA ENABLE L
*MS, IR DISABLE
•PULSE LA
» MEM
START L
1

56VAC or 28VAC
(H724 OR H724A 28 VAC)
(H740D 56VAC)

DOWN

POWER
MONITOR

AUTO
RESTART

LOGIC

AUTO
RESTART
ON/OFF
S1

M848 Power Fail and Auto-Restart Option, Block Diagram

Figure 7-1

7.2

POWER MONITOR LOGIC

The power monitor logic is shown in Figure 7-3. The logic directly monitors the ac output of the computer's
power supply, to which the option is connected by a cable. The cable connects to the option with an 8-pin
connector (2 pins are not used)

Each ac input at J1 is wired via the board etch to an adjacent pin so that the

ac is not dead-ended (the DK8-E Real-Time Clock option (line frequency) also uses the ac output of the power
supply; if both options are in the system, one is connected directly to the power supply while the second is

connected to J1 of the first).

NOTE
The W2 jumper must be removed when the KP8-E is installed
in a PDP-8/F or PDP-8/M.

The ac is full-wave rectified and applied to two comparator circuits. One of these circuits includes transistor
and
pair Q4/Q5 and initiates the auto-restart sequence. The second circuit includes transistor pair Q2/Q3
initiates the power-fail sequence.

There are two thresholds for power fail.

An upper threshold, 105 Vac, that
Q4 and

sets the PWR LOW flip-flop.
is used to start the RESTART logic, and a lower threshold, 95 Vac, that

Q5 detect the 105 Vac threshold; Q2 and Q3 detect the 95 Vac threshold. The upper and lower thresholds
have a tolerance of ±15%. Q2 provides a trigger for one-shot E7 when the amplitude of the line voltage, and
hence, the amplitude of the ac input of J 1, is above the desired minimum.

The - 10.3 Vdc reference voltage is

generated by a precision voltage regulator that is not shown (see the option schematic for this and for resistor
values).

Figure 7-4 presents idealized waveforms to illustrate how E7 is controlled by the comparator circuit.

If the

of suffline voltage is above the selected minimum value, the positive transition at the collector of Q2 will be
icient amplitude to trigger E7.

Because the period of the collector waveform is less than the triggered delay

time of E7, the one-shot will remain active.

If the line voltage falls

below the minimum value for as little as

one-half cycle, as illustrated, E7 times out and an interrupt request is generated. Even though the power re-

covers almost instantaneously, the power-fail sequence is carried out.

The timing diagram shows the UP signal being asserted by the half-cycle immediately following the missing
half-cycle. Thus, the auto-restart sequence begins 1500 ms later, as detailed in the following paragraphs.
7-2

7-3

E9
DIR
7474

0|— OIR

:
R24

E7
9601
15ms

R30

{AUTO RESTART\
LOGIC CLEARS
PWR LOW FF /

0
PWR

LOW

7474

-H
HHL
H
D

INT
qst

Vl
/

(CPD

-UP (TO AUTO RESTART LOGIC)

* W2 MUST BE REMOVED WHEN INSTALLED IN PDP-8/M
COMPUTER TO REDUCE 56VAC TO 28VDC.

Figure 7-3 Power Monitor Logic

7.3

AUTO-RESTART LOGIC

The computer must resume operation by executing the instruction that was stored in location 0000, field 0,
by the power-fail routine. Consequently, the CPMA Register and the IF and DF Registers of the KM8-E option
must be loaded with Os before CPU timing is renewed. Furthermore, the CPU Major State Register must be
manipulated so that a FETCH cycle is entered when timing begins. The auto-restart logic meets these require-

ments by simulating some of the operations that normally occur when the programmer's console is being used.
Thus, to load the CPMA Register with 0s, the auto-restart logic first asserts the LA ENABLE L signal (at the

same time, the MS, IR DISABLE L signal is asserted; this signal places the CPU in the DMA state, ensuring that
the first timing cycle begins in the FETCH state).
a.

The LA ENABLE L signal:

ensures that only "bus" information is placed on the DATA 0-1 1

lines; because nothing has

access to "bus" at this time, the DATA 0-1 1 lines carry 0s (Volume 1, Section 5, Paragraph
3.3.3, for clarification);

causes the 0s on the DATA 0-11 lines to be gated through the CPU Major Register gating
to the MAJOR

REGISTERS BUS.

7-4

28 VAC

PWR LOW

INT RQST

(1)

Figure 7-4 Power Fail Timing

After a delay to ensure that the control lines have settled, the logic asserts PULSE LA. This signal causes the

CPU to generate the CPMA LOAD L signal that loads the CPMA Register with address 0000. CPMA LOAD L
also sets the F flip-flop of the Major State Register; thus, a FETCH cycle will be entered when timing begins.

IND1 is asserted at the same time as LA ENABLE to ensure only Osare on the bus if the programmer's console
is

not installed (Volume 1, Paragraph 3.33.10).

When the CPMA Register has been loaded and the F flip-flop set, the auto-restart logic asserts the KEY CONTROL
L signal. After a delay that enables the control line to settle, PULSE LA is asserted again. However, because
KEY CONTROL L is true, CPMA LOAD L is not generated by this assertion of PULSE LA, nor is the Major
State Register clocked.

7-5

Rather, the Oson the DATA 0-11 lines are loaded into the IF and DR Registers of the KM8-E option (the
auto-restart logic allows for the KM8-E option even if the option is not contained in the system). After this
assertion of the PULSE LA signal, the MS, IR DISABLE L, IND1, and LA ENABLE L signals are negated and
a final delay period is allowed.

When this delay times out, MEM START L is asserted, initiating CPU timing,

and the computer fetches the instruction from location 0000.

The auto-restart logic is shown in Figure 7-5; the relative timing of the logic is shown in Figure 7-6. The

ENABLE/DISABLE switch, S1, must be in the ENABLE position (up) if the automatic restart is to function
after a power interrupt has occurred.

If S1

in the

DISAB LE position, the PWR LOW flip-flop is cleared when

ac power comes up, but the program must be restarted manually.

The auto-restart sequence begins when the power monitor logic asserts the UP signal. The positive transition
of this signal triggers one-shot multivibrator El. During the active 1500 ms of this one-shot, all system equip-

ment (computer, peripherals, options) can complete operations initiated by the OMNIBUS INITIALIZE signal.
At the end of the 1500 ms delay, bistable latch E5 is triggered and the LA flip-flop is set. This latch sets the

KC (key control) flip-flop, clears the PWR LOW flip-flop, and triggers the E3 one-shot (the 0-output of E1
provides a required high signal at one input of E3; as the timing diagram illustrates, this high precedes the E3
trigger signal by an appreciable amount of time).
L,

The 1-output of the LA flip-flop asserts the LA ENABLE

IND1 and MS, IR DISABLE L signals. The E3 one-shot, when it times out after 250 ns, triggers one-shot

E4, which is active for 100 ns. During the 100 ns period, NAND gate E6 is enabled and PULSE

LA is asserted.

Thus, the CPMA Register is loaded and the FETCH flip-flop is set. The E3 one-shot is retriggered, via NOR
gate E6C, coincidently with the leading edge of the PULSE LA signal; while the KC flip-flop is cleared 100 ns
later to assert the

KEY CONTROL L signal. When E3 times out the second time, PULSE LA is produced again.

Thus, the F and DF Registers are loaded at this time.
I

As before, E3 is retriggered coincidently with the lead-

ing edge of PULSE LA. At the end of PULSE LA, when E4 times out for the second time, the LA flip-flop is

cleared, and LA

ENABLE L and MS, IR DISABLE L are negated.

When E3 times out for the third time, it once again triggers E4. However, because the LA flip-flop is now
clear, no PULSE LA signal is produced. Instead, the 1-output of E4 asserts MEM START L and CPU timing
begins by fetching the instruction in location 0000.

At TP1 time of this FETCH cycle, the KC flip-flop is set

by NOR gate E6A and the KEY CONTROL L signal is negated.

The DIR (Direction) flip-flop ensures that a Restart Sequence is initiated only when ac voltage is rising, through
the Restart threshold, toward normal line Voltage Condition.

SECTION 4 MAINTENANCE
General instructions concerning preventive and corrective maintenance are given in Volume 1, Chapter 4.

When

corrective maintenance is required, the technician should use the maintenance program, MAINDEC-8E-DOKC-

D (D), to determine the nature of the problem. The option schematic, drawing no. E-CS-M848-0-1, must be
referred to for IC locations and pin numbers. Tests points have been provided on the option to facilitate

troubleshooting.

7-6

7-7

7-8

SECTION 5 SPARE PARTS
Table 7-1 lists recommended spare parts for the KP8-E. These parts can be obtained from any local DEC office
or from DEC, Maynard, Massachusetts.

Table 7-1

Recommended KP8-E Spare Parts

DEC Part Number
i

i-uyyy

Quantity

Description

RJrt^o

A71 1 /AM

Q\/

11-00114

Diode, D664

11-00275

Diode, D672

15-03100

Transistor, 3009B

15-03409-01

Transistor, DEC 6534B

19-05547

ICDEC 7474
ICDEC 7400
ICDEC 7410
IC DEC 7402
ICDEC 7475
ICDEC 9601
ICDEC 384
ICDEC 8881
ICDEC 6380
ICDEC 6314

19-05575

19-05576

19-09004
19-09050
19-09373
19-09486
19-09705
19-09971

19-09972

7-9

PART 5
INTERPROCESSOR OPTION

CHAPTER 8
DB8-E INTERPROCESSOR BUFFER

SECTION 1

INTRODUCTION

The DB8-E Inter processor Buffer is designed to plug directly into the PDP-8/E OMNIBUS. This option allows
two PDP-8/E Computers to transfer data between themselves, one 12-bit word at a time, at a software- limited
rate of 50 kHz.

The DB8-E can also be used to transfer data to user-designed logic on single-ended data lines.

The basic DB8-E option has one M8326 Module and one BC08-R cable (up to 100-ft long). The DB8-EB has one
M8326 Module, two BC08-R cables, and two 5409209 Module Adapters for connection to user-designed logic.
Device codes on the module are jumper-selected between 50 and 57, allowing a maximum of eight Interprocessor
Buffers to be used in one PDP-8/E.

SECTION 2 INSTALLATION
The DB8-E Interprocessor Buffer is installed on site by DEC Field Service personnel. The customer should not
attempt to unpack, inspect, install, checkout, or service the equipment.

8.1

INSTALLATION

To install the Interprocessor Buffer, remove power from PDP-8/E No. 1 and insert the M8326 Module into the

OMNIBUS.

Refer to Table 2-3, Volume 1, for information about recommended module priorities (the DB8-E

is a non-memory option).
Remove power from PDP-8/E No. 2 and insert the second M8326 Module into its
OMNIBUS. Connect one of the BC08-R cables between J 1 of the first and J2 of the second DB8-E Module.

Connect the second BC08-R cable between J2 of the first DB8-E and J1 of the second DB8-E. This will connect
the output of PDP-8/E No. 1 buffer to the input of PDP-8/E No. 2 module and the output of PDP-8/E No. 2 to
the input of PDP-8/E No. 1. Table 8-1 shows the pin-to-pin connections of J 1 and J2.

Table 8-1

Connection from J1 to J2

Adapter

J1 Pin No.

J2 Pin No.

Module Pins

J1TT

J1RR

J1D

V1
U1
T1

J1F
J1J

Module Pins

J2C
J2E
J2SS
J2PP

J2MM

8-1

V2
U2
A2
B2
C2
(continued on next page)

Table 8-1 (Cont)

Connection from J1 to J2

Adapter

Adapter
J2 Pin No.

J1 Pin No.

Module Pins

J1L
1 M

J2KK

I9HH

i—

J1R
J1T
J1V
J1X
J1Z
J1BB

J2EE
J2CC

J2AA

J2Y
J2W
J2U

J1DD

J2S

NOTE: All pins not listed are tied to ground.

8.2

ACCEPTANCE TEST

The acceptance test should be performed when the DB8-E Modules are installed and periodically after installation
A working M8326 Test Module is needed to perform this test. The

to check the operation of the DB8-E logic.

programs in Section 5 can be used for preliminary operational checks.
Perform the following steps to check the DB8-E Modules installed in the PDP-8/E OMNIBUS.

NOTE
The PDP-8/E under test will be referred to as PDP-8/E
No. 1; the PDP-8/E with test module used to check the
DB8-E Module in PDP-8/E No. 1 will be referred to as
PDP-8/E No. 2.

Procedure

Step
1

Remove the DB8-E Module from PDP-8/E No. 2 and install the test module in its place;
connect the cables from the DB8-E Module to the test module.

Load binary loader in PDP-8/E No. 1 and No. 2.

Load diagnostic MAI ND EC-8E-DOPA-PB in PDP-8/E No. 1 and No. 2.

Run Part 1 and Part 2 of the test for 5 minutes each. There should be no errors.

If there are no errors, remove the test module from PDP-8/E No. 2 and reinstall the
DB8-E Module.

To check the DB8-E Module in PDP-8/E No. 2, repeat Steps 1 through 5 with test
module in PDP-8/E No. 1.

8-2

SECTION 3 SYSTEM DESCRIPTION
The Interprocessor Buffer (Figure 8-1

)

receives or transmits data under control of programmed instructions from

the CPU. Data can be put on the DATA BUS of the OMNIBUS to be transferred to the accumulator, or data can

be taken from the DATA BUS and transferred to another PDP-8/E or user's equipment.

The following instructions are used to program interprocessor data transfers.
Skip on Receive Flag (DBRF)
Octal Code:

65X1

Operation:

Skip if the RECEIVE FLAG equals one.

Read Incoming Data (DBRD)
Octal Code:

Operation:

65X2
Read the incoming data into the AC, clear the RECEIVE F LAG, and set DONE
flip-flop.

Skip on Transmit Flag (DBTF)
Octal Code:

65X3

Operation:

Skip if the DONE FLAG equals one.

Transmit Data (DBTD)
Octal Code:

65X4

Operation:

Transfer the contents of the AC Register to the transmit buffer. Transmit data

and set the FLAG.
Enable Interrupt (DBEI)
Octal Code:

65X5

Operation:

Enable the interrupt request line.

Disable Interrupt (DBDI)
Octal Code:

65X6

Operation:

Disable the interrupt line.

Clear Done Flag (DBCD)

Octal Code:

65X7

Operation:

Clear the

DONE FLAG.

To transfer data from PDP-8/E No. 1 to PDP-8/E No. 2, data is loaded into the AC of PDP-8/E No. 1 and transferred to the output buffer of its DB8-E using the 65X4 IOT.

In addition to loading the output buffer,

IOT

65X4 also sets the FLAG flip-flop in PDP-8/E No. 2. When the program in PDP-8/E No. 2 has sensed its FLAG
flip-flop, data is gated into the AC of PDP-8/E No. 2 using IOT 65X2. IOT 65X2 then sets the DONE flip-flop
of PDP-8/E No. 1, indicating the transfer was completed, and clears the FLAG flip-flop of PDP-8/E No. 2.

PDP-8/E No. 1 then clears its DONE flip-flop using IOT 6507.

SECTION 4 DETAILED LOGIC
The logic in the Interprocessor Buffer will be broken into functional groups for discussion purposes. Figure 8-1
should be used to understand the relationship between each group of logic.

8-3

DEVICE SELECT LOGIC

8.3

are gated by I/O PAUSE when a 65XX
Bits MD03 through MD1
An INT I/O L and SELECT L will be asserted to allow the operation decoder to receive

The device select logic is shown in Figure 8-2.
instruction is decoded.
its

input and to cause the positive I/O bus interface to ignore the IOT instruction.

8.4

OPERATION SELECT LOGIC

SELECT L in Figure 8-3 will enable the gates for bits MD09 through MD1 1 and allow inputs to the operation decoder which is a BCD-to-decimal decoder. (Refer to Appendix A, Volume 1, for details about the 8251

IC.)

The

decoder will supply signals that represent instructions 65X1 through 65X7. When a 65X2 instruction is decoded,
the C line select logic will pull CO and C1 low to allow data to be transferred from the DATA BUS to the AC.

8.5

INTERRUPT AND SKIP LOGIC

The interrupt and skip logic is used to interrupt the program when a data transfer is required. To allow an interrupt to occur, the INT EN A flip-flop must be set (Figure 8-4) by a 65X6 instruction.

The 1 -output of the INT

ENA flip-flop will go to E17 and assert one side of the AND gates allowing them to generate INT RQST L. A
more detailed explanation of interrupt and skip logic can be found in Volume 1.
Table 8-2 shows the signal and data flow required to transfer information between two PDP-8/E Computers.

FLAG TO
PDP-8E NO.2

TRANSMIT
FLAG DRIVER

OUTPUT BUFFERS
AND DRIVERS

DEVICE

SELECT LOGIC

OUTPUT
DATA GATES

SELECT L^
INPUT
DATA GATES

OPERATION

DATA LINE
SELECT LOGIC

DECODER

SKIP
LOGIC

CLEAR FLAG
INITIALIZE

INTERRUPT

REQUEST

LOGIC

TRANSMIT
FLAG FROM PDP8/E NO.2
INTERRUPT

ENABLE

Figure 8-1

Interprocessor Buffer, Block Diagram

8-4

CO L

8-5

8-6

8.6

INPUT DATA GATES AND OUTPUT BUFFERS

The input data gates (Figure 8-5) will be enabled by a 65X2 instruction and transfer data to the AC via the

DATA BUS.
Table 8-2

Simultaneous Receive and Transmit Operation by

Two PDP-8/E Computers Using Interprocessor Buffer
PDP-8/E No. 2 Data Receiver

PDP-8/E No. 1 Data Transmitter
Data is transferred from AC to the DATA BUS and
applied to the data inputs of buffer flip-flops by

programmed instructions.
Data is received and FLAG is set by signal at J2E.

A 6504 instruction clocks the buffer flip-flops and
transmits information to PDP-8/E No. 2 and simul-

INT RQST if ENA is set, and SKIP generated and

taneously sends a signal from J1 RR of PDP-8/E

subroutine to read data is started.

No. 1 to J2Eof PDP-8/E No. 2.

6502 instruction gates data to DATA BUS. TP3 and
6502 instruction enable signal to J1TT to be transmitted to J2C of PDP-8/E No. 1

The trailing edge of the signal at J2C sets the

DONE flip-flop to indicate PDP-8/E No. 2 has
read data.
Signal is removed from J2C when 6502 signal is re-

The Flag is cleared by trailing edge of 6502 instruc-

moved from gate in

tion.

PDP-8/E No. 2.

DONE is cleared by 6507 instruction.
PDP-8/E No. 2 is ready to receive or transmit data.

PDP-8/E No. 1 is ready to transmit or receive data.

The SELECT L signal applied to the output data gates will allow 1s to be transferred from the DATA BUS to the
data input side of flip-flops in the output buffer.
flip-flop will

When a 65X4 instruction is generated, the clock input of the

be pulsed and the data will be transferred to the input gates of PDP-8/E No. 2. This instruction will

also cause J1 RR to go high and set the FLAG in PDP-8/E No. 2.

Buffer is +3V for true ( 1

)

The data transferred from the Interprocessor

signals and 0.0V for false (0) signals.

SECTION 5 MAINTENANCE
Refer to Volume 1 for maintenance information about PDP-8/E Computers.

The acceptance test given in Section

2 should be performed when an error is suspected in the DB8-E.

8.7

DATA TRANSFER TEST

Perform the following programs to transfer data from the switch register of PDP-8/E No. 1 to the AC of PDP-8/E
No. 2.

8-7

INT I/O L

Input Data Gates and Output Data Gates and Drivers

Figure 8-5

PDP-8/E No. 2

PDP-8/E No. 1
Address

Contents

200

7604
6504
6503
5202
6507
5200

201

202
203
204
205

Address

Contents

200

6501

201

5200
6502
5200

202
203

After the programs are loaded, load address 200 and start both PDP-8/Es.
display contents of SR on PDP-8/E No. 1
a.

All 1s

All Os

It is

The AC lights of PDP-8/E No. 2 will

recommended that the following be tried.

A single in each bit position
A single 0 in each bit position.
1

8-8

SECTION 6 SPARE PARTS
Table 8-3 lists recommended spare parts for the DB8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

Table 8-3

DB8-E Recommended Spare Parts

DEC Part No.

Description

19-05547

IC DEC 7474

19-05575

IC DEC 7400

19-05579

IC DEC 7440

19-09486

IC DEC 384

19-09594

IC DEC 8251

19-09686

IC DEC 7404

19-09973

IC DEC 97401

19-09971

IC DEC 6380

19-09972

IC DEC 6314

8-9

Quantity

PART 6
EXTERNAL BUS INTERFACE CONTROL OPTIONS

CHAPTER 9
KA8-E POSITIVE I/O BUS INTERFACE

SECTION 1

INTRODUCTION

The KA8-E Positive I/O Bus Interface permits use of a PDP-8/I or PDP-8/L type peripheral with the PDP-8/E.
the peripheral is a data break device, a KD8-E data break interface must also be in the system.

The concept of

data transfers and the interrelationship of the KA8-E Positive I/O Bus Interface, the KD8-E Data Break Interface,

and the OMNIBUS are explained in Chapters 6 and 10 of the PDP-8/E & PDP-8/M Small Computer Handbook.

A detailed discussion of CPU operation during a programmed I/O transfer is presented in Volume 1, Chapter 3,
Section 6. The reader should be thoroughly familiar with this referenced information to benefit from the detailed logic discussion presented in this chapter.

SECTION 2 BLOCK DIAGRAM
Figure 9-1

a functional block diagram of the Positive I/O Bus Interface.

When an IOT instruction is placed on

the OMNIBUS MD lines, the I/O PAUSE L signal is asserted by the CPU timing generator.
is

INTERNAL I/O L

not asserted by an internal peripheral, I/O PAUSE L causes the interface IOP timing to assert the NOT LAST

TRANSFER L signal. Thus, CPU timing

suspended at TP3 time. Simultaneously, IOP timing is initiated and

the IOP signal that is subsequently generated enables the BIOP pulse generator to produce one or more pulses.

These pulses are used by the peripheral in conjunction with BMB bits to decode IOT instructions.

The IOT instruction can clear and set flags and registers within the peripheral, or it can direct a data word transfer
or a SKIP operation.

Data words are transferred between the data gating logic and the CPU via the DAT ACM 1

lines; between the peripheral and data gating, the data path depends on the direction of transfer, as shown in the

block diagram. The OMNIBUS C lines are asserted within the data gating logic in combinations that depend on
the type and direction of transfer.
If a

SKIP operation is directed by the IOT instruction, the peripheral asserts the external SKIP L signal when con-

ditions warrant.

IOP timing clocks the skip counter and either the DATA10 or DATA1 1 line, or both, is activated.

SECTION 3 DETAILED LOGIC
9.1

BIOP PULSE GENERATOR LOGIC

Figure 9-2 shows the BIOP pulse generator logic, which converts bits MD9-1 1 to BIOP pulses 4, 2, and 1, respectively.

A logic 1 on any MD line conditions a corresponding NAND gate for enabling at TP2 time. When the

NAND gate is enabled,

dc-sets a flip-flop that, in turn, conditions another

9-1

NAND gate. Simultaneously, the

EXTERNAL BUS
f

BMBOO-11

SKIPL

BIOP 1, 2, 4

AC CLEAR L

BAC 00-11

ACOO-11

DATA

GATING
LOGIC

DATA 10

BUFFERS/

INVERTERS

BIOP
PULSE
GENERATOR

<•

I0P

STOP L

IOP
TIMING

MD9-11
(

MDO-11

TP2

I/O
PAUSE L

NOT
LAST
TRANSFER

TP3
L

BUS
STROBE

C2L

DATAO-11

C1L

COL

OMNIBUS
8E-0171

Positive I/O Bus Interface, Block Diagram

Figure 9-1

flip-flop causes the STOP

L signal to be negated.

an I/O transfer involving an external bus peripheral is in

progress, the STOP L signal enables TP3 to initiate the IOP timing operation.

The IOP timing logic (Paragraph

9.3) responds by asserting a signal (IOP) that enables the flip-flop conditioned

NAND gate. The resulting signal

is buffered

and designated BI0P4, BI0P2, or BI0P1

For example, if MD bit 9 is a logic 1, flip-flop I04 is dc-set at TP2 time (note that the 10 flip-flops are cleared at
each TP1 time). The O-output of the flip-flop causes STOP L to be asserted and, providing the 101 and I02 flipflops are cleared (MD bits 10 and 11 are logic 0), the 1 -output conditions

NAND gate E24 for enabling by the

IOP signal. When the IOP timing asserts the IOP signal, E24 is enabled and the BIOP4 pulse is generated. The
width of the pulse can be varied by adjusting a potentiometer in the IOP timing logic, thereby asserting the IOP
signal for the desired amount of time (Paragraph 9.3).

When the IOP signal is negated, E24 is disabled. Because

the output of E24 is connected to the clock input of I04, the flip-flop is cleared when E24 is disabled (note that

the D inputs of the 10 flip-flops are connected to ground; thus, a positive transition at a clock input clears the
flip-flop).

The O-output of I04 negates the STOP L signal; this action causes the IOP timing logic to terminate

the I/O dialogue.

This example stipulated that bits MD10 and MD1 1 were logic 0. Suppose, instead, that all three MD bits are
logic 1.

All three 10 flip-flops are then set at TP2.

The STOP L signal is asserted and the 1-output of 101 con-

ditions E1 1C for enabling by the IOP signal. Observe that the O-output of 101 disables both

NAND gate E8B and

NAND gate E24. Thus, the IOP signal enables E1 1C first and the BI0P1 pulse is generated.

When the IOP signal

is negated,

E1 1C is disabled and 101

cleared. This action removes the disabling signal from E8B; however, E24

remains disabled because the O-output of I02 is one of its inputs.
abling by the IOP signal. When this signal

NAND gate E8B

now conditioned for enWhen

again asserted by the IOP timing logic, B10P2 is generated.

BI0P2 ends, I02 is cleared, removing the disabling signal from E24. Now the BI0P4 pulse is generated, as detailed earlier.

9-2

note:
FLIP-FLOPS are DEC 7474 (See Volume

Appendix A for details)

Figure 9-2

BIOP Pulse Generator Logic

Thus, the BIOP Pulse Generator logic operates in such a way that the BIOP pulses are not assigned specific time
slots.

If only

one of the MD bits is a logic 1 then the corresponding BIOP pulse, whether 4, 2, or 1
,

at the first assertion of the IOP signal.
first and its corresponding

9.2

generated

more than one MD bit is logic 1 the least-significant bit is selected
,

BIOP pulse is generated; the most-significant bit is selected last.

BMB BUFFERS/INVERTERS

The preceding paragraphs discussed the BIOP pulse generator. A peripheral uses these BIOP pulses in conjunction
with BMB bits to decode IOT instructions. The BMB bits are derived from the OMNIBUS MD bits, which are
buffered and inverted by the interface. Figure 9-3 shows the buffer/inverter and network.

BMB bits 03-08 are used in peripheral device selection logic. Both the true and the false states of these bits are
derived from the corresponding

MD bit; this minimizes the device selection network in the external peripheral.

Although programmed transfer peripherals use the BMB bits only for device selection, data break peripherals receive output (from the CPU) data via the BMB00-11 lines. Thus, all 12 BMB bits are derived, as shown in

Figure 9-3.

9.3

IOP TIMING LOGIC

Figure 9-4 shows the IOP timing logic, which determines the duration of BIOP pulses and the separation between
individual pulses, if more than one is programmed. Separation and duration can be varied individually by poten-

tiometers that are indicated on the logic diagram and on the KA8-E etch as IOP SEP and IOP WIDTH. These

9-3

9-4

P/O DEC 74123
10

E3B

STB

J 100 ns

1
'

BUS
STROBE L

£
J

P/O DEC 74123

E2A
REST
275ns
r 0

i±

[7/0 DEC 74123

E2B
200

175ns

"TT

aaa,

J— ^

P/0 DEC 74123

vl\

WIDTH

(

IOP
»

fK>^

STOP L

I/O PAUSE L

i
I

IOP

600 ns

3ms
0

"TT

P/O DEC 74123

£
J

E3A
100

E10

H>4

100ns

„

+ 3V -4
NOT LAST
TRANSFER L

E4B
WIDTH

fp/O DEC 74123

HHr-

J~
1

E4A
SEP

E28^3—

200ns

INTERNAL
I/O L

1ms
c

TP3

Figure 9-4

IOP Timing Logic

9-5

-AAA/

VW
AAr—4-

IOP
SEP

-IOP

potentiometers determine the triggered delay time of associated one-shot multivibrators, shown as part of

DEC 74123 ICs. Briefly, the one-shots contained within a 74123 can be triggered by:
a.

a positive transition at pin 2, if, prior to the transition, pin

low and the clear (C) input is high (for

the "B" half of the IC, substitute pin 10 and pin 9 for pin 2 and pin 1

respectively),

a negative transition at pin 1 , if, prior to the transition, pin 2 is high and C is high,

a positive transition at the C input, if, prior to the transition, pin

Figure 9-5 shows the IOP timing for a typical I/O transfer.

low and pin 2 is high.

The IOP signal is asserted twice during the time that

I/O PAUSE is active; thus, two BIOP pulses are generated by the BIOP pulse generator (the identity of the BIOP
pulses does not affect the waveform relationship).

The waveforms representing SEP and WIDTH are shown for

the minimum allowable triggered delay time, viz., 200 ns for SEP and 600 ns for WIDTH.
values allow these delay times to be increased to five times the minimum value.

The potentiometer

Refer to both figures while

studying the following description.
If the

I/O transfer involves an external bus peripheral (INTERNAL I/O L remains negated) and the BIOP pulse

generator negates the STOP L signal, and NAND gate E28 asserts the NOT LAST TRANSFER L signal; this signal
indicates to the CPU timing generator the impending interruption of normal timing.
initiated, while

At TP3 time, IOP timing is

CPU timing is suspended in TS3.

IOP timing begins when the SEP one-shot is triggered by the positive transition at its C input. SEP (0) is used to
trigger the 100 one-shot, which, in turn, triggers WIDTH.

WIDTH (0) sets the IOP flip-flop; the resulting IOP

signal enables the BIOP pulse generator to begin the BIOP pulse.

The STB (Strobe) one-shot, triggered by the

end of WIDTH (0), clears the IOP flip-flop; thus, the duration of the BIOP pulse is 100 ns longer than the duration of WIDTH (0).

A BUS STROBE L signal

generated by STB (1 ) at the end of each BIOP pulse to execute

the instruction represented by the BIOP pulse (BUS STROBE L causes the AC LOAD L signal to be asserted in the

CPU; see Volume 1, Chapter 3, Section 6 for details). When the first BIOP pulse has ended, the sequence outlined
begins again, this time with STB (0) triggering the SEP one-shot.
nal is asserted by the BIOP pulse generator.

When the last BIOP pulse ends, the STOP L sig-

This signal ensures that the WIDTH one-shot is not triggered by the

next transition of 100 (0). Therefore, the IOP flip-flop remains clear through the remainder of the IOP timing.

When REST (0) (the Restart one-shot), which is triggered by the STOP L signal transition, goes positive after
275 ns, STB is triggered again, producing a final BUS STROBE L signal. This BUS STROBE terminates I/O dialogue and reinstates CPU timing.

The 100 one-shot is necessary for proper triggering of WIDTH.

when SEP times out.

If the

It provides a

negative transition at pin 9 of WIDTH

negative transition were supplied by the 0-output of SEP, WIDTH would trigger at the

same time as SEP. On the other hand, if the negative transition were supplied by the 1-output of SEP, WIDTH

would trigger at TP2 time, when the STOP L signal is negated. Consequently, the 100 one-shot is quite important
to the timing operation.

The 200 one-shot is also important to the timing logic. Note on Figure 9-5 that the STOP L signal is shown to
have a spike that is coincident with the trailing edge of the first BUS STROBE signal (if three BIOP pulses were
generated, there would be two spikes shown). This spike is a representation of the tendency of the STOP L signal

to go low at the end of the IOP signal (NAND gate E8A in the BIOP pulse generator becomes momentarily indecisive at this point in the timing).

The 200 one-shot brackets this spike in time and, thus, prevents the REST one-

shot from triggering prematurely.

9-6

TP1

n
JT
I/O PAUSE

NOT LAST TRANSFER L

STOP L

SEP

(0)

100

(0)

WIDTH (0)

200

(1)

REST

(0)

STB

(0)

IOP (BIOP)

BUS STROBE

Figure 9-5

Waveforms, IOP Timing Logic

9-7

9.4

DATA GATING LOGIC

The data gating logic is shown in Figure 9-6. During a programmed I/O transfer, data is transferred to or from the

CPU on the OMNIBUS DAT AO— 1 1 lines. Output data (from the CPU) is gated from the DATA lines through an
interface buffer/inverter network (illustrated in Figure 9-6 for bits 0 and 1 1 ) to the external bus BAC00-1
lines.

the output transfer is to be accompanied by a clearing of the CPU AC Register, the peripheral is directed

(by the BIOP pulse) to assert the OMNIBUS CO L signal.
external bus AC CLEAR line.

CO L signal.

If the

The peripheral does this indirectly by grounding the

The AC CLEAR L signal causes NAND gate E25D on the interface to assert the

AC Register does not have to be cleared, the C-lines remain negated high throughout the trans-

fer.

On the other hand, an input transfer must always be accompanied by the assertion of at least one C-line. Note
that when a data word is transferred from the peripheral on the external bus AC00-1 1 lines, the interface

IN L signal is asserted by NOR gate E29.

If the data is

DATA

placed on the AC lines during the BIOP pulse (as it must

NAND gate E25C asserts the C1 L signal. Simultaneously, the AC INPUTS -* DATA BUS signal gates the
data onto the OMNIBUS DATAO-1
lines. The result of these actions
an OR operation of the AC contents
and the data on the DATAO-1
lines. The peripheral can cause a jam input by grounding the AC CLEAR line,
thereby asserting the CO L signal. Thus, only the information on the DATAO-1 lines is placed in the AC Register. Note that if data word 0000 8 is transferred from the peripheral, the DATA IN L signal
not asserted. To
transfer 0000 8 the peripheral must ground the AC CLEAR line and, in effect, cause a jam input of zeros.
be),

These are the four types of data transfers that can be made by the PDP-8/I type peripherals. Another form of
I/O transfer, other than a 12-bit data word, utilizes the interface skip logic to update the CPU PC Register. This

type of transfer is discussed in Paragraph 9.5.

9.5

SKIP COUNTER LOGIC

The peripheral, when directed by an IOT instruction, can cause a skip of 1
tiates a SKIP operation by grounding the external bus SKIP line.

asserts the

OMNIBUS DATA 10 and/or DATA1

2, or 3 program instructions.

It ini-

The interface skip logic, shown in Figure 9-7,

lines, depending on the number of instruction skips required

(during a SKIP operation the peripheral does not place data on the AC00-1 1 lines). At the same time, the

OMNIBUS C lines are manipulated to provide a path for the DATA bits through the CPU major register gating
to the PC Register.

The DATA bits are added to the contents of the PC Register, increasing the program count

in the register by 1, 2, or 3.

The timing diagram of a typical SKIP operation is shown in Figure 9-8. Refer to this diagram and to Figure 9-7
while studying the description that follows. The timing diagram shows that two BIOP pulses, 1 and 2, are generated during the IOT instruction.

The imaginary peripheral that applies to this example decodes these two BIOP

pulses and responds by grounding the SKIP line.

ary peripheral does not necessarily exist.

Keep in mind that this is an example, only, and that this imagin-

The combination of BIOP1 and BIOP2 can produce a variety of opera-

tions, depending on how a peripheral decodes the pulses.

Nevertheless, when TP3 starts IOP timing, this peripheral is directed to initiate a SKIP operation by asserting

SKIP L. The SKIP line controls the D-input of flip-flop E9, which is clocked when the STB one-shot is triggered.
Because STB is triggered at the end of each BIOP pulse, E9 can be clocked twice during IOP timing. Note that
the 100 one-shot dc-sets E9. Thus, E9 is set at the first triggering of the 100 one-shot, or (as shown in Figure 9-8)

during a previous IOP timing cycle. Thereafter, 100 and STB are griggered alternately. Thus, E9 is alternately
cleared and set, as long as SKIP L is asserted. Each time E9 is cleared, SKIP 1, the first stage of the 2-stage binary

counter, is clocked.

In this example, the binary counter is clocked twice, indicating that two instructions are to

9-8

*BACOO

*BAC11

A
DATAO

DATA1 1

AAA
C1L

INT
RQST L

COL

E28

DATA

INPUTS—^DATA BUS

IN L

E29

(

)

*ACOO

IOP

note:

*AC
CLEAR
L

* Denotes External Bus Signal.

Figure 9-6

Data Gating Logic

9-9

*INT
RQST

9-10

BI0P1

BI0P2

STB

(1)

100

(0)

SKIP

SKI P 2 (1)

REST

(0)

CEN

(0)

DATA

HOATA 10

Figure 9-8

to be skipped.

Timing, Skip Logic Application

SKIP 2 is set at the second triggering of STB. The C-line enable (CEN) flip-flop is dc-set by the

REST one-shot, enabling NAND gates E25 and E28B (note that CEN is clocked by STB at the same time that
it:

dc-set by

REST; the dc-input takes precedence in such a case). The assertion of C2 L, while C1 L and CO L

remain negated, provides a path for DATA10 through major register gating to the PC Register. C2 L and BUS

STROBE (generated when REST times out) assert PC LOAD L and DATA10 is added to the contents of the PC
Register, updating it by two.

of REST (0).

Note that the SKIP line must be negated before STB is triggered by the trailing edge

not, the binary counter is erroneously clocked one more time.

9-11

SECTION 4 MAINTENANCE
There are no specific maintenance procedures for the KA8-E itself. Each DEC peripheral that connects to the

KA8-E has an associated MAINDEC or exerciser program that enables the technician to maintain both the option
and the KA8-E interface. Because all of these peripherals use the one interface, a fault in the interface can be
isolated by running a number of

MAINDEC programs. If all programs result in errors, one can reasonably con-

clude that the KA8-E is at fault.
General information concerning corrective maintenance is included in Volume 1, Chapter 4.
find this material helpful.

The technician will

The interface schematic, E-CS-M8350, indicates important test points, IC locations,

and pin numbers and should be used whenever maintenance is being performed.

The KA8-E connects directly to a single peripheral via three cables that are supplied with the interface (refer to
the PDP-8/E & PDP-8/M Small Computer Handbook, Chapter 10, for cabling rules and suggestions). Each cable

connects to the interface with a 40-pin Berg connector and to the peripheral with a DEC M953A cable connector.

From-To information for the cable is given in Table 9-1 (the cables are identical). Refer to the PDP-8/E & PDP-8/M
(

Small Computer Handbook for details concerning cable connections.)

Table 9-1

KA8-E Cable Information

From
(M953A Cable Conn.)

(Berg Conn.)

To
(Berg Conn.)

Gnd
Gnd
Gnd

Gnd

Gnd
D2
Gnd

Gnd

BB
CC

EE
FF

Gnd

Gnd
M1
Gnd

Gnd

Gnd
H2
Gnd

Gnd
T2
Gnd

NN
PP

Gnd
K2
Gnd

Gnd
V2
Gnd
Gnd

Pins A2, B2, U1, and V1

UU
VV

on M953A not used.

Pins A1, C1, F1, K1, N1, R1,T1, C2, F2,J2, L2, N2, R2, and U2 on M953A are ground pins.

9-12

SECTION 5 SPARE PARTS
Table 9-2 lists recommended spare parts for the KA8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

Table 9-2

KA8-E Recommended Spare Parts

DEC Part No.

Description

15-03100

Transistor, DEC3009B

19-09705

IC DEC 8881

Quantity
1

19-10010

IC DEC 2501

19-09971
1 Q_nQQ91

IC DEC 6380

19-09928

IC DEC 7416

19-09686

IC DEC 7404

19-09373

IC DEC 9601

19-09486

ICDEC 384
IC DEC 7402
IC DEC 7430
ICDEC 7420
IC DEC 7410
ICDEC 7400
ICDEC 7474

19-09004
19-05578
19-05577
19-05576
19-05575
19-05547

(M835only)

]

11-00114
11-00113

Diode D664

Diode D662

BC08J-10

Cable, 10 ft.

IC DEC 74123 (M8350 only)

9-13

CHAPTER 10
KD8-E DATA BREAK INTERFACE

SECTION 1

INTRODUCTION

The KD8-E Data Break Interface is used by peripherals to transfer large blocks of data between the peripheral
and memory. This interface cannot provide all the necessary signals for such a data transfer. Consequently, the
positive I/O bus interface must also be used in the system.

The concept of data transfers and the interrelationship

of the data break interface, the positive I/O bus interface, and the OMNIBUS are explained in Chapters 6 and 10
of the PDP-8/E & PDP-8/M Small Computer Handbook, DEC 1972.
ing a data break transfer is presented in Volume 1
iar with this referenced

A detailed discussion of CPU operation dur-

Chapter 3, Section 6. The reader should be thoroughly famil-

information to benefit from the detailed logic discussion presented in Section 3.

SECTION 2 BLOCK DIAGRAM
Figure 10-1

is a

functional block diagram of the KD8-E Data Break Interface.

asterisks (on the block diagram only).

OMNIBUS signals are indicated by

When an interface receives a BRK RQST L signal from its peripheral, the

request accept: logic uses the next INT STROBE to assert signals that indicate acceptance of the request. These
signals are used by the CPU and the peripheral in preliminary operations and by the interface priority network.

The priority network compares the priority ranking of a peripheral with that of all other peripherals that make a
break request at the same time. The interface of the highest ranking peripheral generates a PRIORITY signal that
allows its CP Control logic to assert CP control lines. This action enables the peripheral to assume control of the

CP Major Register gating and to directly address, via the BKMA Register logic, memory locations associated with
the data transfer. The direction of transfer and the type of transfer are controlled by the interface data transfer
logic.

When the cycle select logic indicates that the true BREAK (BK) cycle is in progress, the data word is trans-

ferred to, or from, the address indicated by the

BKMA Register logic. If the data transfer

from the peripheral,

the data word is placed on the DATA 0-1 1 lines of the OMNIBUS by the data transfer logic.

SECTION 3 DETAILED LOGIC
10.1

CP REGISTER CONTROL LOGIC

Figure 10-2 shows the CP Register control logic.

The NBR flip-flop determines if the interface can assert the CP

NEW BRK OK L signal, which is asserted within the interface when conditions allow a data transfer (the
NEW BRK OK L signal discussed fully in Paragraph 10.2). If NEW BRK OK L has been asserted by the interface and the BRK RQST L signal has been asserted by the peripheral, the NBR flip-flop is set by the INT STROBE
of the

10-1

BRK

*MD DATA

MA 0-11

DATA 0-11 DIR L CONT L
I

DATA TRANSFER LOGIC

BKMA REGISTER LOGIC
(ADDRESS SELECTION)

TS2 L
DATA IN L
j

MD 0-11

DATA 00-11

DATA ADDRESS 0-11

MS.IR

MALC L

DISABLE L

MAC

CP CONTROL
LOGIC

TP4 TP1

PRIORITY

BK CA WC
CYCLE SELECT
LOGIC

TP 4

3-CYCLE L

PRIORITY

NETWORK

rrx~
TS4

ACTIVE

DATA
0-11

REQUEST ACCEPT
LOG C

BRK IN CPMA
PROG L DISABLE L

INT

STROBE

BRK
RQST L

ADDRESS
ACCEPTED L

INDICATES OMNIBUS SIGNAL

8E-0I79

Figure 10-1

signal (Figure 10-2).

Data Break Interface, Block Diagram

The O-output of NBR then sets the ACTIVE flip-flop, which asserts the BRK IN PROG L

and CPMA DISABLE L signals. The CPMA DISABLE L signal conditions a flip-flop on the Major Register Control module (Volume 1, Figure 3-102) so that TP4 can clear the flip-flop; the resulting signal, MAC L, removes the

CPMA Register outputs from the MA lines. The BRK IN PROG L signal, which can be displayed on the programmer's console, ensures that only data break devices place priority information on the DATA lines during TS4.
When TS4 is entered, the 1 -output of the ACTIVE flip-flop asserts the priority signal for this (our) interface. If
other peripherals have made break requests at INT STROBE time, each peripheral's interface asserts a priority
signal at TS4.
if it

The priority network (Paragraph 10.3) in each active interface examines these signals to determine

has the highest priority of all the devices currently attempting to use the data break system.

our peripheral

is not of sufficiently high priority, it must wait until the next TS4 signal; at that time the priority signals are

again compared.

our peripheral has highest priority, the D-inputs of the MAC1 and MAC2 flip-flops are taken

to a positive voltage; the flip-flops are then set at TP4.

The 1 -output of MAC1 not only asserts the MS,

DISAB LE L signal, which places the CP in the DMA state, but also conditions the MALC flip-flop so that can
be set when the TP1 pulse occurs. The -output of MALC then asserts the MALC L signal, which ensures that
the CPMS Register and the CPMA Register will resume normal operation in the correct major state and at the corit

rect memory address, respectively.

10-2

TO BKMA LOGIC
0
INITIALIZE-

MALC
D

MS.IR
"DISABLE L

MAC1

MAC 2

-01

6
X>7

FROM
PRIORITY

ACTIVE

TS4 L

TS1

z5D

—

BRK IN
PROG L

ADD ACCEPTED L

L
0

NBR

-0|

TP 2

to
INT STROBE

NEW BRK OK L—

t- BRK

Figure 10-2

RQST L

CP Register Control Logic

10-3

DISABLE L

Note that ADD ACCEPTED L is asserted during TS1 of the first cycle following INT STROBE, regardless of the

outcome of the priority check. This signal clears the break request flip-flop in the peripheral, allowing the peripheral to make another request when it is ready. At TP1 the NBR flip-flop is cleared, also regardless of what occurs
,

in the priority network.

Thus, this flip-flop is active for only the short time necessary to indicate acceptance of

ACTIVE flip-flop is cleared only at TP2 of a true break cycle (defined and explained in Paragraph 10.2), which can be delayed for some time by priority considerations. Both NBR and

the break request.

In contrast, the

ACTIVE are used extensively as control signals in other functional sections of the interface.
10.2

CYCLE SELECT LOGIC

After our interface takes control of the CP, a data transfer can be made.
in this state as long as MS,

during the

DMA

The CP is in the DMA state and remains

Each timing cycle (a "slow" cycle of 1 .4 ixs) that occurs

IR DISABLE L remains low.

state is used by the interface/peripheral to accomplish tasks necessary for the data transfer.

actual data word transfer takes place during the Break (BK) cycle of operation.

For

The

-cycle peripherals only the

BK cycle is necessary; however, 3-cycle devices require a Word Count (WC) cycle and a Current Address (CA)
cycle before the BK cycle. This section describes the method of selecting each of the three cycles of operation;
the details of what occurs during each cycle are presented in succeeding sections, except that certain BK cycle
operations are detailed here.
Figure 10-3 shows the cycle select logic.

the respective operation cycle is entered.

When one of the three flip-flops shown (WC, CA, and BK) is set at TP4,
If the

peripheral is a 3-cycle device, the 3 CYCLE line is wired to ground

within the peripheral. Thus, pin 2 of the DEC 8271 IC is positive voltage (high). This high is gated to the D-input
of the

WC flip-flop, providing the 8271 load (L) input

Appendix A, for details about the 8271

IC).

also high and the shift (S) input is low (see Volume 1,

This provision is met each time the interface accepts a break request

from the peripheral (the 1 -output of NBR goes high at INT STROBE time). The WC flip-flop is set at TP4 - the
same TP4 at which MAC1 and MAC2 are set (because the D-input of both the CA and BK flip-flops is low, TP4
Note that TP4 is NANDed with the output of a NOR gate (E18) that can be enabled by
CP
the 0-output of the ACTIVE flip-flop. This means that the WC flip-flop can be set even though access to the
clears these flip-flops).

has been claimed by another peripheral during TS4 (the ACTIVE flip-flop is set prior to the priority

remains set until TP2 of the BK cycle).
are suspended for at least one cycle.

check and

If this happens, the operations that normally occur during the

WC cycle

flip-flops at TP4.

One of these normal operations is the clocking of the 8271
is placed in the "hold" mode by the NBR and MALC flip-flops

To suspend this clocking process, the 8271

The NBR flip-flop is cleared at TP1 of the suspended cycle, while the MALC flip-flop remains in
until our periphthe clear state (MALC is set at TP1 of a normal cycle). The "hold" condition remains in effect
(Table 10-1).

eral has priority; at this time a normal

WC cycle

entered.

At TP1 of the normal WC cycle NBR is cleared and MALC is set (NBR remains clear until a new break request is
flip-flops
accepted). As Table 10-1 shows, the 8271 IC is placed in the right-shift mode. In this mode, the three
comprise a shift register that is right-shifted by clock pulses. Thus, TP4 of the WC cycle causes the high at the
The CA flip-flop, also, can be
1 -output of WC to be shifted into the CA flip-flop (CA is set, while WC is cleared).
set regardless of the results of the TS4 priority check (as before, the 0-output of

ACTIVE enables TP4 to clock

The normal CA cycle operations are then suspended for at least one timing cycle. At TP1 of the
CA
suspended cycle, MALC is cleared; the 8271 is placed in the "hold" mode, preventing TP4 of the suspended

the flip-flop).

cycle from clocking the flip-flops.

When our peripheral has priority, the normal CA cycle is entered, MALC is

set at TP1 time, and the 8271 IC is again placed in the right-shift mode.

and, at TP4, the BK flip-flop is set, while the CA

flip-flop is cleared.

10-4

The CA cycle operations are carried out

BRK CYCLE L

BREAK L

NEW BRK OK L

CYCLE L

NBRO)

Figure 10-3

Cycle Select Logic

MALC(O)

ACTIVE(O)

Table 10-1

8271 IC Control Signals

NBR F/F

MALC F/F

Clear

Low

Hold

Low

High

Parallel

High

Low

Right Shift

Set

Clear

Set

8271 IC Control State

Load

The BK flip-flop, too, is set regardless of priority. If another peripheral has priority, the normal BK cycle operations are suspended and the 8271 IC is placed on the "hold" condition for at least one cycle. When our periph-

BK cycle is entered at TP4. The 0-output of BK if NANDed with the 0-output of
MAC1 to assert NEW BRK OK L, BRK CYCLE L, and B BREAK L (Figure 10-3). Because MAC1 is cleared at

eral has priority, the normal

TP4 if another peripheral has priority, these signals are asserted only during a normal break cycle.

NEW BRK OK

L tells the NB R flip-flop that data is about to be transferred and that a break request can be accepted at the next

INT STROBE time; BRK CYCLE L is applied to the programmer's console display to indicate the normal or
"true break" cycle; B BREAK L clocks the data into or out of the peripheral's buffer register, depending upon
the direction of transfer. At TP2 of the true BK cycle the ACTIVE flip-flop is cleared, negating the CP Register

10-5

If the peripheral

control lines.

has not asserted the BRK RQST L signal before INT STROBE time of this cycle,

NBR and ACTIVE remain clear and the CP Register control lines remain negated. MAC1, MAC2, and BK are
cleared at TP4, while

MALC cleared at TP1 of the next timing cycle (because ACTIVE is clear when this TP4
MALC used to enable TP4 to clock the BK flip-flop). If a break request was made beis

occurs, the O-output of

fore INT STROBE time, the

WC flip-flop

set at the same time that the BK flip-flop is cleared; the break opera-

tion is repeated as many times as necessary.

Figure 10-4 is a timing diagram relating the signals discussed in this section and in the preceding section, CP Register Control Logic (the time scale does not reflect true processor timing; refer to Volume 1, Chapter 3, for timing

information).

TP 1

TP2

n
TP3

TP4
INT

STROBE

BRK RQST L

NBOK

"1
1

—

NBR (1)

ADD ACCEPTED

ACTIVE (1)

PRIORITY™"™

*CPMA DISABLE L
* BRK IN PROG L

MAC1 (1)

MAC2 (1)
*MS,IR DISABLE L
* MALC

(1)

MALC L
3- CYCLE L

8271 "L"

8271 "S"

WC (1)
CA (1)
BK (1)
B

BREAK L

* BRK

CYCLE L
* AS CONTROLLED BY
"OUR" PERIPHERAL

NOTE:
3-Cycle device xfer showing 1 word xfer with a priority break during CA cycle ;WC cycle

Figure 10-4

shown for second word xfer.

Timing, Register Control and Cycle Select Logic

10-6

10.3

PRIORITY LOGIC

Figure 10-5 shows the priority logic. Each peripheral interface contains a nearly identical circuit; differences
exist only in the placement of jumper wires, which are designated A0-A1 1

and BO— B1 1 in Figure 10-5. The

priority of a peripheral is established on the interface by removing a particular
in

A jumper (all A jumpers are wired

place during production of the interface) and installing the corresponding B jumper.

a "0" priority for our peripheral, remove AO and install jumper BO.

gates (ICs E17, E34, and E49). Thus, the output from

For example, to establish

Note that this action disables all 12 NAND

NOR gate E18 is low. When the interface accepts a break

request from the peripheral, the ACTIVE flip-flop is set at INT STROBE time.

The 0-output of ACTIVE enables

NAND gate E10 to assert the PRIORITY signal; therefore, our interface/peripheral begins the data break operation.

Because our peripheral has only to request a break for that request to be granted, our peripheral has been

assigned highest priority.

No other interface can have its AO jumper removed, or its BO jumper connected.

PRIORITY

TS4 L

Figure 10-5

Priority Logic

10-7

As many as 1 1 other peripherals can have a break request accepted by their respective interfaces at INT STROBE
time.

No matter what priority has been established for these peripherals, each of the 1 1 interfaces has an AO

jumper in place. Note that when our interface ACTIVE flip-flop is set, NAND gate E37 brings the DATA 0 line
low (our BO jumper is in place) during TS4. Because all interfaces monitor the DATA lines, NAND gate E1 7D
of each other interface is enabled. Thus, these interfaces cannot assert their PRIORITY signals as long as our
peripheral requests data breaks.

As another example, consider what happens if our peripheral ranks only third highest in the peripheral priority
structure. This priority is established on our interface by removing jumper A2 and connecting jumper B2.

Be-

cause jumpers AO and A1 are left in place, two other interfaces can keep our peripheral from beginning a data

break operation.

If the

second highest priority peripheral has a break request accepted at the same time our

DATA

peripheral's request is accepted, its interface brings the

line low during TS4 time.

NAND gate E17C on

our interface is enabled and the PRIORITY signal remains negated. Until this other peripheral has completed the

As has been implied, priority decreases from left to right,

data break operation, our peripheral remains inactive.
i.e.,

the lower the priority of the peripheral, the higher the number of the A jumper removed and B jumper in-

stalled.

Thus, to establish priority on the lowest ranking peripheral's interface, remove jumper A1 1 and install

jumper B1 1.

10.4

BKMA REGISTER LOGIC

Figure 10-6 shows the

BKMA Register logic. This logic enables the peripheral to reference memory locations

associated with the data break transfer.

A peripheral that has made a break request must provide its interface

with a memory address via the DATA ADDRESS 0-1 1 lines (Figure 10-6). This address is gated through DEC

8266 (refer to Volume 1, Appendix A, for details of this IC) to the parallel-load inputs of the 8271 ICs (the
gating for bits 0 through 10 is identical; thus, the description and the illustration detail events for only bit 0 and
bit 11).

When the interface accepts the peripheral's request at INT STROBE time, the 0-output of the NBR flip-

flop enables

NOR gate E15, placing the 8271 ICs in the "load" condition (Table 10-1). At the same time, one

input of NAND gate E14 is sent high by the 0-output of the ACTIVE flip-flop. At TP4, E14 is enabled and the

BKMA Register flip-flops are loaded with the address on the DATA ADDRESS lines. If the peripheral has priority, the MAC2 flip-flop
set, also at TP4; the 1-output of the flip-flop enables NAND gate E1, placing DATA
ADDRESS bit 0 on the MAO line. If the peripheral does not have priority, the address retained in the BKMA
cleared at
set at a later TP4 time. The NBR flip-flop
Register but not gated onto the MA lines until MAC2
is

TP1, regardless of the outcome of the priority check, and NOR gate E1 5 places the 8271 ICs in "hold".
If the peripheral

is a

-cycle device, the address placed on the

or from which the data word is to be transferred.
flip-flop of the cycle select logic is set, the

the peripheral is placed on the

MA lines at TP4

that of the memory location to

Note that NAND gate E26 is enabled in this situation (the BK

WC flip-flop

Thus, the full 12- or 15-bit address supplied by

clear).

MA lines. However, the peripheral a 3-cycle device, the WC cycle entered
NAND gate E26, disabled during the WC cycle, in turn disables NAND
is

first after a break request is accepted.

DATA ADDRESS bit

not gated onto the MA1 1

MA1 1 is high, logic 0, during
the cycle. The address placed on the MA lines during the WC cycle is that of the memory location containing the
gate E40. Thus,

peripheral's

WC Register; this address

1 1

line; rather,

hard-wired in the peripheral and is even (bit 1 1

logic 0) so that the

During the WC cycle, the count in the WC Register is transferred from memory to the CP, incremented, and returned to the register. At TP4, the WC flip-flop is cleared and the CA flip-flop is set.

If the

peripheral still has

NAND gate E37 enabled, pulling the MA1 line low. The MA0-10 lines carry the same address as
incremented and the new address is that of
during the WC cycle. Thus, the peripheral's hard-wired address
priority,

the memory location containing the peripheral's CA Register.

10-8

E26

MAC 2(1)

MALC(O)—

WC(1)

L- ACTIVE (0)

DATA

ADDRESS 0

Figure 10-6

BKMA Register Logic

10-9

MAC1 (0)

At the same time (TP4) that the CA Register address is placed on the MA lines, the CA flip-flop enables NAND

BKMA Register in the "load" condition.
Also, NAND gate E18 removes the DATA ADDRESS lines from the parallel-load inputs of the BKMA Register,
gate E18. This gate, in turn, enables NOR gate E15, which places the

substituting the MDO-1 1 lines.

Note that these actions do not take place prior to the negative transition at the

BKMA Register flip-flop clock inputs. Thus, the BKMA Register retains the WC Register address until TP4 of
the CA cycle.

During the CA cycle, the address in the CA Register is transferred from memory to the CP, incremented, and returned to the register. The address, after incrementation (the current address), is that of the location to or from

which the data is to be transferred. Thus, this current address must be placed in the BKMA Register, and trans-

MA lines at the beginning of the BK cycle. The current address sent via the MD lines
At TP2, the result returned to the MD lines and remains on these lines for the
latter portion of the CA cycle. Therefore, at TP4 of the CA cycle, the BKMA Register parallel-load inputs reflect
the current address. Because the BKMA Register
in the "load" condition, the current address
loaded into the
reffed from there to the

to the CP where it is incremented.

At approximately the same time, the BK flip-flop is set, while the CA flip-flop is cleared. Because E37

disabled and E26 is enabled, the contents of

BKMAO—

1 1

are placed on the MAO-1 1 lines.

Also at TP4, NAND gate E18 is disabled. This action removes the MD lines from the parallel-load inputs, selects
the DATA ADDRESS lines, and places the

BKMA Register in "hold". Note that the MALC flip-flop keeps NOR

gate E18 enabled throughout the BK cycle (ACTIVE is cleared at TP2), if the peripheral has priority. These two
gates ensure that the

bKMA Register

ready to begin a new transfer, if the interface accepst a break request at

INT STROBE time of the BK cycle.
During the BK cycle, the data word is transferred to or from the location specified by the current address. The
logic that accomplishes this transfer through the interface is covered in the following section, which also details

the special operations of all three cycles.

10.5

DATA TRANSFER LOGIC

The data transfer logic (Figure 10-7) controls the direction and type of data transfer. Table 10-2 shows the relationship between the type and direction of transfer and the signal levels of the various control lines.

The table

should be used with Figure 10-7 for a good understanding of the logic details.
If the

transfer is to be from the memory to the peripheral, a 1 2-bit data word is transferred from the addressed lo-

cation via the positive I/O bus interface.

The Data Break Interface asserts the MD Dl R L signal so that the data

word is rewritten in the memory location during the write half of the timing cycle.
is

used to ground the MD DIR line. The BK (1) and MAC1

gress.

(1 )

NAND gate E8B (Figure 10-7)

signals ensure that the true break cycle is in pro-

The third input to E8B is high because NAND gate E10A is enabled. E10A is controlled by the Dl (Data

In) and

INC (INCrement) flip-flops, which are both cleared at TP1 time of an output (from memory) transfer.

Note that the peripheral need not assert any control lines for an output transfer. However, if an input (to memory) transfer is to be carried out, the peripheral usually grounds the
discussion).

this first cycle is a
is

DATA IN line (exceptions are noted in the

The Dl flip-flop is set at TP1 of the first cycle of the data break.

WC cycle. Since the BK flip-flop

clear,

NAND gate E13

If the
is

peripheral is a 3-cycle device,

disabled (note that the Dl flip-flop

significant in the operation of E13 only during the BK cycle; thus, the decision to set or clear this flip-flop, by

DATA IN L signal, need not be made during either the WC or CA cycles). One input of
NAND gate E8A is high. If this a normal WC cycle (this interface's peripheral has priority), E8A is enabled during TS2 by NAND gate E10B, pulling the DATA 11 line low. This single bit of data
transferred to the CP and
added to the word count, which
brought to the CP from the WC Register, providing the BRK DATA CONT L
asserting or negating the

10-10

signal is asserted by the interface.

NAND gate E23

gate E15 is disabled, enabling E23 (MAC1
is incremented.

is set

used to assert this signal. Because this is a

WC cycle, NAND

because the peripheral has priority). Therefore, the word count

Because the MD Dl R L signal is negated (both E8C and E8B are disabled during the WC cycle),

this new word count is placed in the

DATA 11

DATA 0 *

WC during the write half of the memory cycle.

— jpy

8E-OI85

OMNIBUS SIGNALS
Figure 10-7

Data Transfer Logic

During the CA cycle of the 3-cycle transfer, the current address is incremented in much the same way as the word
count. Again, DATA 1 1 is pulled low by E8A during TS2 if the peripheral has priority. E23 asserts the BRK

DATA CONT L signal, which enables DATA

1 1

and the current address to be added in the CP.

If the

MD Dl R L

signal is negated, the new address is sent to the CA Register dur ing the write half of the cycle. Note that the MD

DIR L signal is negated only if the NCAI (No Current Address Increment) flip-flop is clear. This flip-flop is

10-11

clocked at TP1 of a timing cycle and is normally clear. However, the peripheral can ground the CA INC INH line,
causing the NCAI flip-flop to be set at TP1

NAND gate E8C then asserts the MD Dl R L signal during the CA

cycle. Thus, although the current address is incremented as usual, the original address (the one that was in the

CA Register at the beginning of the cycle) is returned to the CA Register during the memory write.

Table 102
Control Signals, Cycle, Type, and Direction of Transfer

Cycle

Direction

of Transfer

Out

Type

Word

Current

No Current

12-Bit

of Transfer

Count

Address

Increment

ADM

Data Word

Increment

High

Low

Low
Low

Low
Low
Low

High

Low
Low

Low

High

Low

High

Low

Low
Low
Low

High

Low

High

MD DIR L
BRK DATA CONT L
DATA IN L
MB INC L
CA INC INH L

High

During the BK cycle of operation, whether of a 1- or 3-cycle operation, an input or output transfer can take place.

As described at the beginning of this section, there is only one type of output data transfer, i.e., the transfer of a
12-bit data word from the addressed location.
ried out.

However, there are three types of input transfers that can be car-

One of these is similar to the transfer that takes place during the WC and CA cycles, and is designated

MB Increment. To accomplish this transfer, the peripheral grounds only the MB INC line. At TP1 the INC flipflop is set, while the Dl flip-flop is cleared.

NAND gates E10A and E15 are disabled by the INC flip-flop. Thus,

E32 asserts the BRK DATA CONT L signal and, because E8C is disabled during the BK cycle, E8B negates the

MD DIR L signal. During TS2 the DATA 11 line

pulled low by E8A. This single bit is transferred to the CP,

where it is added to the data word that is brought from the addressed memory location. The incremented data is
then sent back to the addressed location during memory write.

Another type of input transfer, similar to the MB Increment, is designated Add to Memory (ADM). The periph-

MB INC and DATA IN lines so that both the Dl flip-flop and the INC flip-flop are set at TP1.
During TS2 of the true break cycle, a 12-bit data word carried on the peripheral's DATA 00-1 lines is gated
through the interface to the OMNIBUS DATA lines. This data is added in the CP to the data brought from the
eral grounds the

addressed memory location, and the result is rewritten in the memory location.

The third type of input transfer is that of a 12-bit data word to the addressed memory location. The peripheral

NAND gate E15
NAND gate E10A disabled
again high.
also disabled, the MD DIR L signal
by the -output of Dl and, in turn, disables E8B. Because E8C
placed on the OMNIBUS DATA lines and transferred to the addressed memory
During TS2, a 2-bit data word

grounds only the DATA IN line; thus, TP1 sets the Dl flip-flop, while clearing the INC flip-flop.
is

enabled and causes NAND gate E23 to negate the BRK DATA CONT L signal.
1

location.

10-12

10.6

WC OVERFLOW LOGIC AND EMA REGISTER LOGIC

WC Overflow logic and the EMA Register logic. The WC OVERFLOW L signal generated
asby the interface during either a normal WC cycle or a true BK cycle the OMNIBUS OVERFLOW L signal
about
asserted during a WC cycle to indicate that the last word of a block
serted by the CP. OVERFLOW L
then used by the peripheral to terminate the data break operation. Durto be transferred. WC OVERFLOW L
asserted to indicate that an input transfer has resulted in assertion of
ing a BK cycle the OVERFLOW L signal
used in the peripheral as directed by the program.
the CP CARRY OUT L signal. In this case, WC OVERFLOW L
Figure 10-8 shows the

+ 5V

CA(1)-

-WC OVERFLOW L
MAC1 <n-

OVERFLOW L
(BJ2)

WORD COUNT OVERFLOW
EMA

EMA 0

EMA 2

BK (I) -

MAC10)1

BEAO
C
,

NBR(O)

BEA2

BEA1

X
00

ACTIVE (0)-

EXTENDED DATA ADDRESS

EMA REGISTER

Figure 10-8

be-0186

Word Count Overflow and EMA Register Logic

The EMA Register logic is used to specify the complete 15-bit memory address to or from which data is to be
transferred. EMAO is the MSB of the 1 5-bit address, while MA1 1 is the LSB (see Chapters 9 and 10 of the

PDP-8/E& PDP-8/M Small Computer Handbook for definitions of OMNIBUS and External bus signals relating
to extended memory). If the computer contains only the basic 4K memory, EMA 0, EMA 1, and EMA 2 are

When memory is extended (up to 32K, if desired), these three most significant bits are used to indicate
which memory field is to take part in the data transfer. The peripheral specifies the memory field via the External
bus Extended Data Address 00-02 lines (Figure 10-8). This field address is loaded into the BEA (Break Extended
logic 0.

Address) register at TP4 of the first cycle of the break operation (Figure 3-4).

If the

peripheral is a 3-cycle device,

WC cycle. However, note that BEA Register information placed on the EMA lines only dur
ing a true BK cycle. Thus, for a 3-cycle device the WC and CA Registers must be located in memory field 0, the

the first cycle is the

basic 4K.

The location to or from which data is to be transferred can be contained in an extended memory field.

10-13

SECTION 4 MAINTENANCE
There are no specific maintenance procedures for the KD8-E itself. Each DEC peripheral has an associated

MAINDEC or exerciser program that enables the technician to maintain both the option and the KD8-E Interface.
General information concerning corrective maintenance is included in Volume, Chapter 4.
find this material helpful.

The technician will

The interface schematic, E-CS-M8360-0-1, indicates important test points, IC locations,

and pin numbers; it should be used when maintenance is being performed.

The KD8-E connects directly to a single peripheral via two cables that are supplied with the interface (refer to
PDP-8/E & PDP-8/M Small Computer Handbook, Chapter 10, for cabling rules and suggestions). Each cable connects to the interface with a 40-pin Berg connector and to the peripheral with a DEC M953A cable connector.

From-To information for the cable is given in Table 10-3 (the cables are identical; refer to Chapter 10 of the

PDP-8/E & PDP-8/M Small Computer Handbook for details concerning proper connection of the cables).
Table 10-3

KD8-E Cable Information

From
(M953A Cable Conn.)

Gnd
Gnd
Gnd
B1

From

(Berg Conn.)

(M953A Cable Conn.)

(Berg Conn.)

Gnd

C
D

Gnd

BB
CC

Gnd
D2
Gnd

EE
FF

Gnd

Gnd
M1
Gnd

Gnd

Gnd
H2
Gnd

Gnd
T2
Gnd

R
S

T
U

Gnd
K2
Gnd

NN
PP

Gnd
V2
Gnd
Gnd

UU
VV

Pins A2, B2, U1 and V1 on M953A not used.
Pins A1 , C1 , F2, K1 , N1 , R1 , T1 , C2 r F2, J2, L2, N2, R2, and U2 on M953A are ground pins.

SECTION 5 SPARE PARTS
Table 10-4 lists recommended spare parts for the KD8-E. These spare parts can be obtained from any local DEC
office or from DEC, Maynard, Massachusetts.

10-14

Table 10-4

KD8-E Recommended Spare Parts

utu ran iMo.

Description

Quantity

10-01610

Capacitor 0.01 juF, 100V, 20%

11-00113

Diode D662

19-05575

IC DFP 7400

19-05579
19-09004
19-09057
19-09267

!C DEC 7440
IC
740?
V_/ DEC
L/ l_
/tut
•

IC DEC 74H10

IC DEC 74H1

19-09971

IC DEC 6380

19-09486

IC DEC 384

19-09615

IC DEC 8271

19-09667

ICDEC74H74
IC DEC 7404
IC DEC 6314
IC DEC 97401
IC DEC 7416
IC DEC 8266
IC DEC 7412
IC DEC 2501

19-09686
19-09972

19-09973

19-09928
19-09934
19-09955

19-10010

10-15

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146 Main Street, Bldg. 1-2
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Digital Equipment Computer Users Society (DECUS) maintains a user Library and publishes a catalog of programs as well as

the DECUSCOPE magazine for its members and non-members who request it. For further information please write to:

DECUS
Digital Equipment Corporation

146 Main Street

Maynard, Massachusetts 01754
Send Digital's software newsletters to:

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My computer is a

PDP-8/E

PDP-9

PDP-8 /L

PDP-8/I

DPDP-10

DPDP-12

LINC-8

PDP-1 1

PDP-1

Other

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known)

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FIRST CLASS
PERMIT NO. 33

MAYNARD, MASS.
BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES

Postage will be paid by:

Digital Equipment Corporation

Technical Documentation Department

146 Main Street

May nard, Massachusetts 01754

PDP-8/E MAINTENANCE MANUAL

VOLUME II

READER'S COMMENTS

DEC-8E-HR2C-D

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of
our publications.

What is your general reaction to this manual?

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FIRST CLASS
PERMIT NO. 33

MAYNARD, MASS.
business reply mail

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES

Postage will be paid by:

Digital Equipment Corporation

Technical Documentation Department
1

46 Main Street

Maynard, Massachusetts 01754

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WORLD-WIDE SALES AND SERVICE

DIGITAL EQUIPMENT CORPORATION

MAIN OFFICE AND PLANT
146 Main Street.

Maynnrd. Massachusetts. U.S.A. 01754 • Telephone: From Metropolitan Boston: 646-8600 • Elaawhere: (6J7>S97-5f f J
TWX: 710-347-0212 Cable: DIGITAL MAYN Telex: 944457

UNITED STATES
MID-ATLANTIC

NORTHEAST
REGIONAL OFFICE
275 Wymen Street, Waltham. Massachusetts 02154
Telephone: (6171-890-0320/0330

TWX: 710-324-8919

WALTHAM

— SOUTHEAST (cont)

KNOXVILLE
6311 Kingston Pike, Suite 21
Knoxvllle. Tennessee 37919
TWX: 810-583-0123
Telephone: (615)-5B8-6571

CENTRAL (cont)
NEW ORLEANS
3100 Rldgelake Drive. Suite 108
Metairle, Louisiana 70002
Telephone: 504-837-0257

15 Lunda Street, Waltham. Massachusetts 02154
TWX: 710-324-6919
Telephone: (617)-891-1030

CENTRAL

CAMBRIDGE/ BOSTON

REGIONAL OFFICE

REGIONAL OFFICE:

310 Soquel Way, Sunnyvale, California 94086
Telephone: (408) 735-9200

Main Street. Cambridge. Massachusetts 02139
TWX: 710-320-1167
Telephone: (6171-491-6130

899

ROCHESTER
130 Aliens Creek Road. Rochester, New York 14618
TWX: 710-253-3078
Telephone: (716)-4S1-1700

CONNECTICUT
Meriden. Conn 06450
TWX: 710-461-0054
Telephone: (203)-237-8441 /746B
240 Pomeroy Ave

WEST

1850 Frontage Road, Northbrook, Illinois 60062
TWX: 910-686-0655
Telephone: (312H98-250O

400 Penn Center Boulevard
Pittsburgh. Pennsylvania 15235

Telephone: (412)-243-9404

WEST LOS ANGELES

TWX: 710-797-3657

MID-ATLANTIC

— SOUTHEAST

CHICAGO
1850 Frontage Road. Northbrook. Illinois 60062
TWX: 910-686-0655
Telephone: (312)-498-2500

REGIONAL OFFICE:

U S. Route 1, Princeton. New Jersey 08540
TWX: 510-685-2338
Telephone: (609}-452-2940

NEW YORK
95 Cedar Lane, Englewood, New Jersey 07631
Telephone: (201)-871-4984. (2123-594-6955, (212)-736-0447

TWX: 710-991-9721
NEW JERSEY
123 Raute 46. Parslppany. New Jersey 07054
Telephone: (201)-335-3300
TWX: 710-987-8319

ANN ARBOR
230 Huron View Boulevard. Ann Arbor, Michigan 48103
TWX: 810-223-6053
Telephone: (313)-761-1150

INDIANAPOLIS

Telephone: (317)-243-8341

U.S. Route 1

TWX: 810-341-3436

MINNEAPOLIS
TWX: 910-576-2818

Telephone: (612)-854-6562-3-4-5

LONG ISLAND

Park Hill Bldg 35104 Euclid Ave.
Wlllouqhby. Ohio 44094
TWX: 810-427-2608
Telephone: (216)-946-8484

Huntington Quadrangle
.

(212)-895-8095

PHILADELPHIA
Station Square Three. Paoll. Pennsylvania 19301
Telex: 510-668-8395
Telephone: (215>647-49Q0/4410

TWX: 910-335-1230

SAN FRANCISCO
1400 Terra Belle

560 San Antonio Rd., Palo Alto, California 94306
Telephone: (41 5) -969-6200
TWX: 910-373-1266
7850 Edgewater Drive
Oakland, California 94621
Telephone: (415) 635-5453/7830

TWX: 910-366-7238

ALBUQUERQUE

CLEVELAND
.

Telephone: (516) 694-4131

3444 Hancock Street
San Diego. California 92110
Telephone: (714) 298-0591. 0593

OAKLAND

Princeton. New Jersey 08540
TWX: 510-685-2338
Telephone: (609) 452-2940

R.me 1S07 Huntington Station, New York 11746

SAN DIEGO

PALO ALTO

Suite 111. 8030 Cedar Avenue South.
Minneapolis. Minnesota 55420

PRINCETON

1510 Cotner Avenue, Los Angeles, Callforna 90025
TWX: 910-342-6998
Telephone: (213)479-3791/4318

Mountain View, California 94040
Telephone: (415)-984-6200
TWX: 910-373-1266

—

Suite G
Beachway Drive
Indianapolis, Indiana 46224

ANAHEIM
801 E. Ball Road. Anaheim. California 92805
TWX: 910-591-1189
Telephone: (714)-776-6932/8730

PITTSBURGH

ST. LOUIS
Suite 110. 115 Progress Pky., Maryland Heights.
Missouri 63043

Telephone: (314)-B78-4310

TWX: 910-764-0831

6303 Indian School Road. N.E.
Albuquerque, N.M. 87110
Telephone: (505) 296-541 1 /5428

TWX: 910-989-0614

DENVER
2305 South Colorado Blvd.. Suite #5
Denver. Colorado 80222
Telephone: (303) 757-3332/758-1656/758-1659

Executive Building
Rlverdale. Maryland 20840
6811 Kenllworth Ave
TWX:
Telephone: (301)-779-1600/752-8797

DAYTON

TWX: 910-931-2650
SEATTLE

3101 Kettering Blvd.. Dayton. Ohio 45439
Telephone: (51 3)-299-7377
TWX: 810-459-1676

Telephone: (206) 454-4058/455-5404

DURHAM/CHAPEL HILL

MILWAUKEE

SALT LAKE CITY

WASHINGTON
,

2704 Chapel Hill Boulevard
Durham, North Carolina 27707
Telephone: (919)489- 3347
TWX: 510-927-0912

B531 W. Capitol Drive, Milwaukee. Wisconsin 53222
Telephone: (414) 463-91 10
TWX: 910-262-1 199

Suite 130, 7001 Lake Eilenor Drive, Orlando. Florida 32809
Telephone: (305)-851 -4450
TWX: 810-850-0180

8655 North Stemmons Freeway
Dallas, Texas 75247

Telephone (2l4)-638-4880

ATLANTA
7815 Clearview Place, Suite 100,
Atlanta. Georgia 30340
Telephone: (404)-451 -3734/3735/3736

TWX: 910-861-4000

HOUSTON
3417 MilBm Street. Suite A. Houston. Texas 77002

TWX: 810-757-4223

TWX: 910-443-2306

431 South 3rd East. Salt Lake City, Utah 84111
Telephone: (801) 328-9838
TWX: 910-925-5834

PHOENIX

DALLAS

ORLANDO

1521 130th N.E.. Bellevue. Washington 98005

Telephone: (713)-524-2961

TWX: 910-881-1651

4358 East Broadway Road
Phoenix, Arizona 85040
Telephone: (602) 268-3488

TWX: 910-95CM691

PORTLAND
Suite 168
5319 S.W. Canyon Court, Portland, Ore. 97221
Telephone: (503) 297-3761/3765

INTERNATIONAL
NEW ZEALAND

EUROPEAN HEADQUARTERS

SWEDEN

Digital

Equipment Corporation International Europe
RoutB de I'Aire
Geneva 26. Switzerland
Telephone: 42 79 50
Telex. 22 683

Digital

STOCKHOLM

AUCKLAND

Vretenvagen 2, S-171 54 Solna, Sweden
Telephone: 98 13 90
Telex: 170 50
Cable: Digital Stockholm

Auckland. New Zealand
Telephone: 75-533

1711

FRANCE

Digital

France

Telex: 21339

GRENOBLE
10 rue Auquste Ravler, F-38 Grenoble, France
Telephone: (76) 87 87 32
Telex: 32 882 F (Code 212)

CANADA
Digital

Equipment

GmbH

150 Rosamond Street, Carleton Place. Ontario
Telephone: (613) 257-2615
TWX: 610-561-1651

Telephone: 37 19 85. 37 02 30

OTTAWA
Telex: 166 43

Equipment Corporation

COPENHAGEN

3 Muenchen 13, Wallenatelnplatz 2
Telephone: 0811-35031
Telex: 524-228

COLOGNE

Equipment of Canada. Ltd.

CANADIAN HEADQUARTERS

c/o Flrma Service
Waldenmarthranesgate 84-B-86
Oslo 1, Norway

Digital

MUNICH

Equipment Corporation Ltd.

Hilton House, 430 Queen Street, Box 2471 A.

OSLO

DENMARK

GERMANY
Digital

Digital

NORWAY

Equipment Digital S.A.R.L.

PARIS
327 Rue de Charenton, 75 Parle 12
Telephone: 344-76-07

Equipment Aktlebolag

Vesterbrogade 140. 1620 Copenhagen V

SWITZERLAND
Digital

Equipment Corporation S A.

120 Holland Street, Ottawa 3, Ontario K1Y 0X7
Telephone: (613) 725-2193
TWX: 610-562-8907

TORONTO
230 Lakeshore Road East, Port Credit, Ontario
Telephone: (416) 274-1241
TWX: 610-492-4306

MONTREAL
9675 Cote de Ll.rsse Road
Dorval, Quebec, Canada 760
TWX: 610-422-4124
Telephone: 514-636-9393

S Koeln, Btsmarckstrasse 7,
Telephone; 0221-522181
Telex: 888-2269

GENEVA

Teleqram: Flip Chip Koeln

5531

FRANKFURT

1211

Edmonton, Alberta, Canada
TWX- 610-831-2248
Telephone: (403) 434-9333

6078 Neu-lsenburq 2
Am Forsthaus Gravenbruch 5-7
lelephone: 06102-5526
Telex: 41-76-82

HANNOVER
3 Hannover, Podblefsktstrasse 102
Telephone: 0511-69-70-95
Telex: {

ZURICH
Scheuchzerstrasse 21
CH 8006 Zurich. Switzerland
Telephone: 01/60 35 66
Telex: 56059

Equipment Corporation

Ges m.b.H

VIENNA
Marian Iferatraese 136, 1150 Vienna 15, Austria
Telephone: 85 51 88

Equipment S.p.A.

Digital

Equipment Co..

Ltd.

U.K. HEADQUARTERS
Arkwr-ght Road, Reading, Berks.
Telephone: 0734-583555
Telex: 84327

READING
he Evening Post Building. Tessa Road
Reading, Berks.
I

BIRM INGHAM
Birmingham Road. Sutton Coldfield, Warwicks.
Telephone: (0044) 21-355 5501
Telex: 337 060

29/31,

Upper Precinct. Walkden. Manchester M28 5AZ

Telephone: 061-790-8411

Telex: 668666

LONDON
Bilton House. Uxbrldqe Road, Ealing, London W.5.
Telephone: 01-579-2334
Telex: 22371

EDINBURGH
Shiel House. Cralgshill, Livingston,

West Lothian, Scotland

MILAN
Corso Gerlbaldi 49, 20121 Mllano, Italy
Telephone: 872 748 694 394

Telex: 33615

SPAIN

Equipment of Canada, Ltd.
West 12th Avenue
Vancouver 9. British Columbia, Canada

Digital

2210

TWX: 610-929-2006

BUENOS AIRES
Coasin S.A.
Virrey del Pino '1071
Telephone: 52-3185

VENEZUELA

Atalo Ingenleros S.A.. Enrigue Larreta 12. Madrid 16
Telephone: 215 35 43 / Telex: 27249

CARACAS

BARCELONA
Atalo Ingenleros S.A.. Ganduxer 76, Barcelona 6
Telephone: 221 44 66
Digital Equipment Corporation Ttd.

AUSTRALIA
Digital Equipment Australia Pty. Ltd.

P.O. Box 491, Crows Nest
N.S.W. Australia 3085
Telephone: 439-2566
Telex: AA20740
Coble: Digital. Sydney

MELBOURNE
60 Park Street. South Melbourne. Victoria, 3205
Telephone: 696-142
Telex: AA40618

PERTH

NETHERLANDS

643 Murray Street

West Perth. Western Australia 6005

Digital Equipment N.V.
Sir Winston Churchilllaan 370

Riiswijk/The Hague, Netherlands
Telephone: 070-995-160
Telex: 32533

BELGIUM

Buenos Aires
Telex: 012-2284

Coasin S.A. (Saies only)
Apartado 50939
Salana Grande Ho. 1, Caracas
Telephone: 72-9037

Cable:

INSTRUVEN

CHILE
SANTIAGO
Coasin Chile Lt<!a. (sales only)
Casilla 14588, Correo 15, Santiago
Telephone: 396753

Cable:

COACHIL

Telephone: 214-993

Telex: AA92140

BRISBANE
139 Merivale Street, South Brisbane
Queensland, Australia 4101
Telephone 444-047
Telex: AA40616

JAPAN
TOKYO
Rlkel Trading Co., Ltd. (sates only)
Kozato-Kaikan Bldg.
No. 18-14, Nlehlahimbashl 1-chome
Minato-Ku, Tokyo, Japan
Telex: 781-4208
Telephone: 5915246
Digital Equipment Corporation International
Kuwa Building Mo. 17, Second Floor
2 7 Nishi-Azabu 1-Chome
Minato-Ku, Tokyo, Japan
Telephone: 404-1,894/6
Telex: TK-6428

PHILIPPINES
Stanford Computer Corporation
P.O. Box 1608
416 Dasmnrinas St., Manila
Telex: 742-0352
Telephone: 49-68-96

INDIA

BRUSSELS
Digital Equipment N.V./S.A.
108 Rue D'Arlon
1040 Brussels. Belgium

Telephone: 02-139256

VANCOUVER

MADRID

Telephone: 32705 / Telex: 727113

THE HAGUE

103 Street

SYDNEY

MANCHESTER
13

ARGENTINA

UNITED KINGDOM

EDMONTON

Telephone: (604) 736-5616

ITALY
Digital

AUSTRIA
Digital

Route de ('Aire
Geneva 26. Switzerland
Telephone: 42 79 50
Telex: 22 683

Telex: 252S7

ADELAIDE
6 Montrose

Avenue

Norwood, South Australia 5067
Telephone: 631-339
Telex: AA82825

H.S. Sonawala Mg Director (Sales Only)
HINDITRON SERVICES PUT LTD.

69/ A Nepean Sea Road

Bombay, India