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DEC-14-HGZA-D1

December 1970

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DEC-14-HGZA-D

MAINTENANCE MANUAL

VOLUME

The PDP-14 system and its unique approach to machine control, including its physical parts, its circuitry, and its expressed or implied
methods of programming, are patent-pending. Ail rights are claimed
by Digital Equipment Corporation. The information presented herein is proprietary in nature,

and is intended solely to inform our cus-

tomers in the use of our products.

DIGITAL

EQUIPMENT

CORPORATION

•

MAYNARD, MASSACHUSETTS

(I)

1st

'ITie

material in tliis manual is for informa-

tion purposes and is subject to change with-

out notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL

Printing March 1970

CONTENTS
Page

CHAPTER 1

GENERAL

1.1

PDP-14 System

1-1

1.2

Maintenance Levels

1-2

1.2.1

On-Line

1-2

1.2.2

Off-Line

1-2

1.3

Test Equipment and Spares

1-3

CHAPTER 2

ON-LINE MAINTENANCE

2.1

General

2-1

2.2

Machine or Process System Fault Isolation

2-2

2.2.1

Fault Isolation Technique

2-2

2.2.2

NEMA Enclosure Input and Output Tables

2-2

2.2.3

System Troubleshooting Example #1, Control Input Device Malfunction

2-5

2.2.4

System Troubleshooting Example ^^2, Control Output Device Malfunction

2-6

2.2.5

System Troubleshooting Example #3, PDP-14 System Malfunction

2-6

2.3

PDP-14 System Fault Isolation

2-6

2.3.1

PDP-14 Control Unit and Storage Box Checkout Procedure

2-6

2.3.2

PDP-14 Storage Box Fault Isolation Procedure

2-13

2.3.3

PDP-14 Read Only Memory Checkout Procedure

2-16

2.3.4

PDP-14 Output Box Fault Isolation Procedure

2-19

2.3.5

PDP-14 Input Box Fault Isolation Procedure

2-22

2.3.6

PDP-14 Accessory Box Fault Isolation Procedure

2-24

2.3.7

Fault Isolation Without Test Computer

2-29

CHAPTER 3

THEORY OF OPERATION

3.1

General

3_]

3.2

System Functional Description

3_3

3.2.1

Internal

Mode Instruction Set

3_3

3.2.2

Cycle Control and Data Transfer

3-9

3.2.3

External Computer Interface and Skip Comparator

3-10

3.3

Detailed Circuit Descriptions

3-10

3.3.1

Test Flop and Conditional

3-10

3.3.2

Major States

3-13

3.3.3

Timing Cycle

3-16

Jumps

CONTENTS (Cont)
Page

3.3.4

Manual Control and Power Detection Circuits

3-21

3.3.5

Read Only Memory (ROM) Circuits

3-25

3.3.6

Input Box Circuits

3.3.7

Output Box Circuits

3.3.8

Storage Box Circuits

3.3.9

Accessory Box Circuits

3.4

External Computer Interface

3.4.1

External Control Instruction Set

3.4.2

External

3.4.3

External Computer Interface Circuits

3.4.4

Interrupt and External

CHAPTER 4

3-29
3-31

3-31
3-31

3-34
3-36
3-38

Mode Instruction Set

3-39
3-40

Mode Control Circuits

OFF-LINE MAINTENANCE

4.1

General

4-1

4.2

Component Fault Isolation Procedures

^-'

4.2.1

Control Unit Procedure

4-2

4.2.2

ROM Assembly Procedure

4-3

4.2.3

Accessory Box Procedure

4.2.4

Hints and Kinks

4.3

Module Repair Techniques

4-6
4-7
4-8

TABLES

1-1

Maintenance Test Equipment

'"3

1-2

Module Spares

'-4

2-1

Test Program Error Code/Module Location Cross Reference

2-11

2-2

Test Program Address/S-Box Module Location Cross Reference Table

2-14

2-3

Output Box Fault Isolation

2-21

2-4

Input Box Fault Isolation

2-23

2-5

Accessory Box Module/ABE-14 Error Code Cross Reference

2-28

2-6

Accessory Box Module Location/Address Cross Reference

2-28

3-1

PDP-14 Internal Mode Instruction Set

3-6

3-2

PDP-14 Register and Counters

3-8

3-3

External Control (lOT) Instruction Set

3-36

3-4

External Mode Instruction Set

3-38

ILLUSTRATIONS
Page
Frontispiece

PDP-14 Controller
1-1

PDP-14 Controller, Simplified FuncHonal Diagram

1-1

2-1

NEMA Enclosure Input Box Terminal Assignment Table With Sample Entries

2-3

2-2

NEMA Enclosure Output Box Terminal Assignment Table With Sample Entries

2-3

Mainframe Module and Cable Connector Map, Front View

2-8

2-4

Storage Box Module and Cable Connector Map, Front View

2-15

2-5

Input and Output Boxes Module and Cable Connector Maps, Front View

2-20

2-6

Accessory Box Module and Cable ^onnector Map, Front View

2-27

3-1

PDP-14 Controller, Simplified Block Diagram

3-2

PDP-14 Controller, Detailed Block Diagram

3-4

3-3

Instruction Word Formats

3-4

Gated Flip-Flop and Equivalent Logic Circuit

3-11

3-5

Test Flop and Associated Circuits, Simplified Logic Diagram

3-12

3-6

PDP-14 Controller, Flow Diagram

3-14

3-7

Control Logic Timing Diagram

3-15

3-8

Fetch/Execute Major States Toggle

3-16

3-9

Start Cycle Control, Simplified Logic

Diagram

3-17

3-10

Pause Cycle Control, Simplified Logic Diagram

3-18

3-11

I/O Cycle Control, Simplified Logic Diagram

3-20

3-12

TSl, TS2, End Cycle Pulse, and Timing Pulse Generators, Simplified Logic Diagram

3-22

3-13

Manual Controls and Power Sense Circuits, Simplified Logic Diagram

3-23

3-14

Read Only Memory (ROM), Simplified Logic Diagram

3-26

3-15

3-27

3-16

ROM Timing Diagram
ROM Data Sense Circuits, Simplified Logic Diagram

3-17

Input Box Circuits, Simplified Logic Diagram

3-30

3-18

Output and Storage Box Circuits, Simplified Logic Diagram

3-32

3-19

Output Box AC Control Circuit, Simplified Schematic Diagram

3-33

3-20

Timer Module, Time Delay Circuit, Simplified Schematic Diagram, and Equivalent
Logic Diagram

3-35

3-21

External Computer Interface, Detailed Block Diagram

3-40

3-22

Interrupt and External

3-23

External and Output Flags, Simplified Logic Diagram

3-43

4-1

Control Unit Mainframe Wirewrap Panel, Rear View, Showing Pin Coordinate Scheme

4-4

3-5

Mode Controls, Simplified Logic Diagram

3-28

3-41

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CHAPTER 1

GENERAL

1.1

PDP-14 SYSTEM

The PDP-14 System is designed to replace relay control systems in industrial and other applications using AC
control power.

Control relay wiring is replaced by a control program stored in Read Only Memory (ROM)

modules located in the PDP-14 mainframe assembly (see Figure 1-1).

MA NFRAME ASSY.

READ ONLY

MEMORY
CONTAINING

CONTROL

PROGRAM
SELECT ED
INSTRUCTION

MACHINE OR

PROCESS
SYSTEM
LIMITSWITCHES,

PRESSURE-

INPUT

INPUT
BOXES

SELECTED
FOR TEST

wfiRn
*°''°
1

1
1

„,,^„,,^
OUTPUT

MACHINE OR

SELECTED

CONTROL

1
1

UNIT

OUTPUT
BOXES

SWITCHES,

SOLENOIDS,

MOTOR
CONTACTORS,

PUSHBUTTONS.
ETC

PROCESS
SYSTEM

__J

ETC.

OUT =UT SELECTED FOR TEST

Figure 1-1

PDP-14 Controller, Simplified Functional Diagram

To accomplish its purpose, the PDP-14 tests the status (on or off) of machine or process system limit switches,
pressure switches, push buttons, etc, and its own outputs.

The PDP-14 compares these conditions, one at a

time, with information from the control program within the ROM. The results of these comparisons cause outputs
associated with these conditions to be turned on or off.

1-1

The basic operation sequence is as follov^s:

first,

the control unit obtains an instruction from the control

program contained within the ROM (Fetcji major state); second, the control unit performs the operation specified

by the instruction (Execute major state),
i

The control program instructions take thrfe basic forms.

Test Instructions - These instructions cause the control unit to test an input or output, specified
in the instruction, to determine whether that input or output is on or off.

Decision-Making Instructions - These instructions are used to determine the future action of the
program through the use of cpnditional jumps performed on the basis of test instruction results.
These program jumps lead toiadditional test instructions and, eventually, to turning a particular
output on or off.

c .

Control Instructions - These instructions cause the control unit to turn on or off an output specified
by the instruction. Additiorjal instructions are used to faqilitate transfer of information between
the PDP-14 System and an external computer, and to perform internal "bookkeeping" functions.

Th*.PDP-14 User's Manual (DEC-14-GGiZA-D) provides detailed programming and installation information,

which is beyond the scope of this Maintenance Manual

MAINTENANCE LEVELS

Two distinct PDP-14 maintenance levels'ore presented in this manual

Both levels provide fault isolation and

o»n-a«H^n procedures; no preventive maintenance is required.

1.2.1

On-Line

Chapter 2 presents maintenance proceduijes to be performed without disconnecting the PDP-14 from the machine
or process system.

This material

presejited in a step-by-step format in order that the maintenance electrician

can rapidly isolate and correct the fault Jsy simply substituting modules, in the rare event the fault is within the

PDP-14 Controller.
Although Paragraph 2.3.7 describes a method of fault isolation and correction using only module substitution,
it is

recommended that the maintenance jirograms and a test computer be utilized to assist in fault isolation.

The test computer (Digital Equipment Corporation, PDP-8/l, PDP-8/L, or PDP-12) can also be used for
tion of new control programs as required to meet changes in the machine or process system.

genera-

A complete package

of programs is provided with each PDP-lft.

1.2.2

Off-Line

Chapter 4 provides techniques and infornjiation required to repair defective modules or other PDP-14 components.

The defective module or other components must be removed to a location suitable for repair of relatively delicate

1-2

electronic equipment.

In addition, personnel

performing these procedures must be familiar with digital

equipment hardware, electronic and logic schematic diagrams, and electronic equipment repair techniques.
These personnel must also thoroughly understand the operation of PDP-14 circuits.

To assist in this. Chapter 3

consists of a complete discussion of PDP-14 circuits oriented toward the technician with a good understanding

of basic electronic and digital circuits.

Volume II of this manual contains a complete set of engineering physical (ports location) drawings and electrical
schematic diagrams of PDP-14 modules to be used with Chapter 4 in fault isolation and repair of defective

modules.

The techniques in Chapter 4 require a test computer and maintenance programs, in addition to stan-

dard electronic test equipment.

TEST EQUIPMENT AND SPARES

Table 1-1
a

list

lists

the test equipment required (but not supplied) for the two levels of maintenance.

Table 1-2 is

of recommended spore modules.

Toble 1-1

Maintenance Test Equi pment

On-Line
Maintenance

Equipment Description

Test Computer:

Digital Equipment Corp. PDP-8/l,

PDP-8/L, or PDP-12
Teleprinter:

Optionol

Off-Line
Maintenance
Required

(recommended)

Teletype Corp. 33ASR

Optional

Required

(recommended)
Test Computer Interface Pkg .

Optional
(recommended)

Required

Bandwidth Min. 5 mHz,
Min. Gain 1 V/cm, external trigger or dual trace

Not used

Required

Volt/Ohm Meter:

1,000 ohms/volt

Not used

Optionol

Module Extender:

Digital Equipment Corp.

Not used

Required

DA 14-1 (for PDP-8/I),
DA14-L (for PDP-B/L or PDP-12).
Oscilloscope:

Type W982

(four)

1-3

Table 1-2

Module Spares
Type
Usage

Description
(one each)

M740

Instruction Decoder and Register Control

Control Unit

M741

Major States and Timing

Control Unit

M742

PDP-14 Sjwitch and Power Control

Control Unit

M743

K Interface Control

Control Unit

M744

Control Unit

M745*

PDP-14 to PDP-8/L, -8/1 Interface

Control Unit

M746

Bus Register

Control Unit

M747

Incrementing Bus Register

Control Unit

G922

Control Unit

G924

ROM Brajd Board
ROM Senbe Amplifier
ROM Selection

M921*

Device Code Select Jumper Board

Control Unit

M106*

Dot NOR Gates

Control Unit

K578

AC Inputi

K614

Isolated AC Switch

0-Boxes

K302**

Two Timeb

A-Boxes

K272***

Retentive Memory

A-Boxes

K207

Flip-Flop;

0-, S-, and A-Boxes

K161

Binary-td-Octal Decoder

I-,

0-, S-, and A-Boxes

K135

Inverters

I-,

0-, S-, and A-Boxes

BC14A

Cable

I-,

0-, S-, and A-Boxes

G923

Control Unit

*RequIred only for external compufer interface.
**Required only if accessory bc^x time delays are used.

***Required only if accessory Hox retentive memories are used.

1-4

-Boxes

CHAPTER 2

ON-LINE MAINTENANCE

2.1

GENERAL

The PDP-14 Conlroller requires no periodic maintenance.
the event of a machine or process system malfunction.

Maintenance consists of fault isolation and repair in

Though the PDP-14 Controller is seldom the cause of the

malfunction, the neon lamps on the PDP-14 input and output boxes are very useful tools for determining whether
the problem is in the machine or process system (and where within the machine or process system) or within the

PDP-14 System.
The machine or process system is defined as the machine, or group of machines, under the control of a PDP-14
The machine or process system includes all control solenoids, limit switches, etc, and all control

Controller.

wiring between these elements and the PDP-14 input and output box terminals.

On-line repair consists of two major steps, which must be performed in sequence:
Procedure

Step

Fault isolation to wiring and components outside the PDP-14 Controller or

to PDP-14 Controller components; and

Localization and repair of the machine or process system wiring or compo-

nent (limit switch, pushbutton, solenoid, motor contactor, etc), or localization and repair of the PDP-14 Controller by substitution of plug-in
components

Paragraph 2.2 describes the techniques to follow in order to make maximum use of the PDP-14 lamps in locating
a defective component outside the PDP-14 Controller.

If it is determined

from following the procedures of Paragraph 2.2 that the trouble is definitely within the

PDP-14, Paragraph 2.3 contains step-by-step procedures to locate the defective PDP-14 component.

On-line

repair of the PDP-14 is limited to substituting a properly functioning component (module) for the defective

component.

If the

trouble is determined to be within the PDP-14 Control Unit mainframe but cannot be isolated

using the procedures described in Paragraph 2.3, the mainframe must be removed from the

NEMA enclosure and

sent to a test area where specially trained personnel and electronic test equipment are available to perform

detailed troubleshooting and repair procedures.

2-1

MACHINE OR PROCESS SYSTEM FAULT ISOLATION

2.2

The techniques described under this heading isolate the malfunction to a machine or process system component

(AC control wiring, limit switches, pushbuttons, solenoids, motor contactors, etc), or to the PDP-14 system
(input and output boxes, and control unit modules).

2.2.1

Fault Isolation Technique

The machine or process system malfunction is usually apparent at one or more machine stations, or may be indicated by fault indicator lamps on the operator's console.

In either case, the machine or process system circuits

associated with the fault should be checked, using the neon lamps on the PDP-14 input and output boxes.

If the

neon lamps on the PDP-14 input and output boxes disagree with the actual status of the machine, the

trouble is not in the PDP-14.

Thus,

if a

carriage reaches the end of its travel and depresses a normally-open

limit switch operating lever but the associated input box lamp does not light, the trouble must be in the limit

switch or in the wiring to the PDP-14 input box terminal adjacent to the lamp.

If a

motor is not running, but the PDP-14 output box lamp corresponding to the contactor for that motor is lighted,

the trouble is not in the PDP-14.

The trouble is in the AC wiring from the output box to the contactor, within

the contactor, in the high power wiring to the motor, or within the motor itself.

However, if the motor fails to run when the carriage activates the limit switch, and the input box lamp associated
with the limit switch is lighted but the output box lamp associated with the motor contactor is not lighted, then
there is a malfunction within the PDP-14.

In other words, if the combination of input box lights, as observed,

does not produce the correct output lamp response, the procedures in Paragraph 2.3 must be followed to isolate
the trouble to a PDP-14 input or output box or control unit module.

2.2.2

NEMA Enclosure Input and Output Tables

To assist in locating the input box lamps associated with a particular control function, a list is posted inside the

NEMA enclosure door to identify each input box terminal

A sample of the input table format Is presented in

Figure 2-1

A similar table lists the output box terminals and the conditions required to turn each output on. A sample of
the output table format is presented in Figure 2-2.

NOTE
There is usually an interlock on the NEMA enclosure door. This
interlock must be defeated in order to observe output box lamps.

2-2

)

Input Box Terminal Assignments

Input Box

and
Terminal Number

Input
Input Device

Device

Functional Description of Active State

Identification

X Number

UNCLAMP

Applies power to input terminal when pressed.

XIO

Pushbutton, lOPB

A16

Head Retracted
Limit Switch, 4LS

Applies power to input terminal when machine head is fully retracted.

X20

A14

Clamps In Limit

Limit switch applies power to input terminal when clamp is engaged.

X16

Limit switch removes power from input terminal when clamp Is reledsed.

X21

Switch, ILS

A17

Clamps Out Limit
Switch, 5LS

Figure 2-1

NEMA Enclosure Input Box Terminal Assignment Table With Sample Entries

Output Box Terminal Assignments
Output Device Control Equation
X=Input Terminal, Y=Output Terminal, +=OR, *=AND,

Output Device
Identification

Output Device

ANOT

2LT=3PB+C4PB+2LT)*/3LT

Red AUTOMATIC
Console Lamp, 2LT

}\.

Amber MANUAL

i2.

3LT = 3PB*!!5PB+3LT)
Yl = X0*(X2 + Yl

Machine Head FULL DEPTH
Amber Console Lamp, 5LT

S9.

5LT

Release Clamp

SlA. SOLB = 4LS*3LT*10PB+C<1LS*2LS*5LT+SOLB)*/5LS*/6LS*2LT3
Y5 = X17*Y1 * X7 +i:( X15 * Y2+ YS )* /X20 *Y0 3

Console Lamp, 3LT

Solenoid B

X0*<X1

=
=

Y0>*/Y1

C3LS*/4LS)+C1LS*2LS*5LT)
(X16*/X17)+(X15 * Y2)

Figure 2-2

Y Number

NEMA Enclosure Output Box Terminal Assignment
Table With Sample Entries

Y2
Y5

The input and output box terminals are numbered in octal from top to bottom starting with the lamp in the top
left corner then down the right row of

lamps (0_ through 37„ for input boxes, 0_ through 17^ for output boxes).

The right-hand column of the Output Box Terminal Assignment Table defines the conditions required to turn a
particular output

These conditions are stated in Boolean algebra, which is simply a shorthand method of

describing the conditions necessary to turn on the output box terminal

The slash symbol

(/) is used to

indicate

negation of a signal; e.g., /X17 means NOT X17.

When the asterisk symbol (*) appears between two terminal designators, the conditions on either side of the
asterisk

MUST be present in order to satisfy that portion of the statement.

Thus

X16*A17
means that the lamp associated with input terminal X16 must be on, and the lamp associated with input terminal

X17 must be off in order to turn the output terminal ON.

When the plus symbol (+) appears between two terminal designators, either one or the other condition flanking
the plus symbol (or both) must be present in order to satisfy that portion of the statement.

Thus

X16+/X17
means that the lamp associated with input terminal X16 must be on, or the lamp associated with input terminal

X17 must be off (or both conditions) in order to turn the dependent output ON.
Parentheses are used to combine a group of conditions to be considered a SINGLE condition in relation to other
conditions outside the parentheses.

Thus the Boolean statement

X16*(A17+X15)
means that either the lamp associated with input terminal X17 be off, or the lamp associated with input terminal

X15 be on; and, in addition to this requirement, the lamp associated with input terminal X16 must be on.
Several sets of parentheses, nested one within the other,

may be used in a single Boolean equation. Always

check lamps starting with those outside any parentheses, then check those within the innermost sets of parenthesesnoting whether or not the relationship within a single set of parentheses is satisfied before going to the next wider
set of parentheses.

In this way

associated output lamp to light.

can be determined if the combination of lamps, as observed, should cause the
Thus

X16*((A17 + Y13) *X15)

2-4

means the lamp associated with input terminal X17 must be off, or the lamp associated with output terminal Y13
must be on, or both.

one of these three possibilities is observed on the lamps, then, additionally, the lamp

associated with input terminal

X15 must be on.

If the

conditions described thus far are observed in some form,

then the lamp associated with input terminal X16 must also be on in order for the output lamp and

circuit con-

trolled by this relationship to be turned on.

NOTE
Whenever groups of parentheses are encountered, always
work from the innermost sets, then consider the contents
of the innermost sets as single conditions to be considered
in relation to the other conditions bracketed by the next
wider set of parentheses.

2.2.3

System Troubleshooting Example *1, Control Input Device Malfunction

As an example of the system troubleshooting procedure, assume that on automatic transfer line
blocks is stopped by a malfunction.

machining engine

A visual check of the line reveals that the left-hand clamp holding the

blocks under a particular machining head is still clamped, even though the engine block at that station has al-

ready been machined and the clamp should have released.

The trouble is therefore associated with the clamp

and its control circuitry.

The NEMA enclosure housing the PDP-14 is opened (the Interlock must be defeated) and the solenoid controlling
the clamp release is located in the output box terminal assignment table inside the NEMA enclosure

sample entries in Figure 2-2).

The PDP-14 Output Box and terminal number associated with the clamp release

solenoid are noted, and the lamp associated with that terminal

The lamp associated with the clamp solenoid is not lighted.
tioned.

door (see

is observed.

This does jnoj^ mean that the PDP-14 has malfunc-

simply means that the trouble is apparently not in the clamp release solenoid or the control wiring

between the output box and the solenoid.

It is

now necessary to return to the output box terminal assignment table and compare the conditions required to

turn on output box terminal Y6 with the existing state of the input and output box lamps.

lamp associated with input terminal X20 is not lighted.
terminal Y6,

It is

observed that the

As this condition is necessary in order to activate output

can now be assumed that the trouble is definitely not in the PDP-14 system, but must be in the

outside circuit associated with input terminal X20.

The input box terminal assignment table is now consulted, and it is found that input terminal X20 is connected
to limit switch 4LS,

Figure 2-1).

which should be

ON when the machine head

fully retracted (see sample entries in

The machine head is observed to be fully retracted; therefore, the trouble must be in the limit

switch or its associated wiring.

A check of the limit switch reveals that it has, in fact, failed.

switch puts the line back in production again.

2-5

Replacing the

2.2.4

System Troubleshoofing Example ^2, Control Output Device Malfunction

The same machine system malfunction described in Paragraph 2.2.3 is observed. This time the lamp associated
with output terminal Y6 is lighted.

The trouble is not in the PDP-14 System, but must be in the solenoid, in

the wiring between the output box and the solenoid, or in the machinery between the solenoid and the clamp.

Examination reveals that a defective hydraulic valve, controlled by the solenoid, prevented release of the

clamp.

The valve is replaced and the line put back in production.

2.2.5

System Troubleshooting Example #3, PDP-14 System Malfunction

The same machine system malfunction described in Paragraph 2.2.3 is observed. This time the lamp associated
with output terminal Y6 is not lighted, but all the conditions required to activate output terminal Y6 are present.

The trouble must be assumed to be in the PDP-14 System

NOTE
Each PDP-14 Output Box terminal is fused.

If it is

suspected

that an output load has exceeded five amperes, the output
circuit should be repaired to remedy the overcurrent condition
(shorted wiring, solenoid winding, etc), and the output box
fuse associated with that terminal should be checked. If the

output box fuse is blown, the lamp associated with that output will not light.
If the

trouble is in the PDP-14 system, the procedures in Paragraph 2.3 must be followed to isolate the trouble

to a control unit module or to an input or output box.

2.3

PDP-14 SYSTEM FAULT ISOLATION

The procedures under this heading should not be performed until the procedures described in Paragraph 2.2 have

been performed and the trouble has been definitely isolated to the PDP-14 System. The test computer procedures
in

Paragraphs 2.3.1 through 2.3.6 must be performed in sequence, the one exception being that the procedure

Paragraph 2.3.4 may be performed first if it is suspected that an output box fuse has been blown because of a

control output short or other circuit overload conditions.

If an

external computer is not available for fault isolation. Paragraph 2.3.7 describes a few simple substitution

techniques which may be used to isolate the defective PDP-14 System module.

2.3.1

PDP-14 Control Unit and Storage Box Checkout Procedure

CAUTION
PDP-14 and/or test computer circuits may be damaged if
modules or connectors are inserted or removed with
power ON.

2-6

Step

Procedure

Remove PDP-14 confrol unit shield cover.

Connect test computer (PDP-8/l or PDP-B/L) system power cable to convenience
outlet on PDP-14 control unit switch panel

Place PDP-14 Control Unit and Test Computer Panel Switches in OFF position.

Connect three control cables between the test computer and the PDP-14 control
unit as follows:

From

To Test Computer

PDP-14

PDP-8/I

PDP-8/L

PDP-12

Location

(4K)

(8K)

A19

JOS & J06

D34

B34

N16

A20

J03 & J04

D35

B35

N15

B20

JOl & J02

D36

B36

N14

Disconnect all Input (I) Box, Storage (S) Box, Accessory (A) Box, and Output (O)
Box cables from PDP-14 control unit mainframe.

NOTE
These connectors should be labeled with the I or O box
letter designator or mainframe location designator to

facilitate replacement when testing

completed.

Insert all storage box (S-Box) cable connectors into adjacent PDP-14 mainframe
output box locations (see Figure 2-3). Always insert full S-Box cable connectors

making certain that cables leaving the top of the S-Boxes are connected to
mainframe row C connectors and cables leaving the bottom of the S-Boxes are
connected to the mainframe row D connectors.
first,

NOTE
Any number of "full" S-Boxes can be checked at one time,
but only one half S-Box con be checked at one time, and
its cable connector must be inserted into the lest sequential
mainframe output box connector (this will always be in row C).
If additional half S-Boxes must be checked, the first half S-Box
tested must be disconnected at the mainframe, the next half
S-Box cable connected, and the entire test cycle repeated.

ON position.

Place PDP-14 control unit and test computer power switches in

Place PDP-14 START/STOP switch momentarily in STOP position.

Set test computer SWITCH REGISTER to "JTT^ ^-

The correct switch config-

uration for this is
111

Press the

111

LOAD ADDRESS switch on test computer.

2-7

ROM#l

ROM #2

ROM #3

ROM #4

(Required)

(Optional)

r~
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14

31 30

32
<u

J)
J3

X
o

— — — —

w—

^ t i VN^^ ^

EMPTY
J)
-Q

-Q

ti.

^
O-

1 1 5

X
O

°?is

Q
o.

Q-i

-Q

J)
J3

\
i

CO
CM
CS
(D

«
15

*
CO cs
cs cs cs

O O O

O O o

X
o

^ -Q
6 Uo
a>

•«*

cs
cs

o O

CO
cs
o-

C^l

^
CO
CM
CS cs CS
O O o
5^"

C^4

<j-

E:^

cs
cs

X
o

6
U-

JJ
-Q

_«
Si

t
s

2 S

15:
-Si

Confusion With Numbers
"1" and "0".

a 6
X y: 5

X
o

_a>

-D

f
1

<jO

X
o

1 1

2 1

o o o O o o o o
32 31

30 29 28 27 26 25 24 23 22 21

20 19 18 17 16 15 14 13 12

1 1

10 9

COLUMN
Figure 2-3

"O", and "Q"

are not used to Prevent

g g
2 5

O Box Letter Designators "I",

•<5

Configuration Shown.

O o o o O O o o
_« _a>
.Q -Q

Maximum Mainframe

;

o
u
U
< u UJ o —J —J Z of
X

!
j

O -Q
D

NOTES:

U o

„ „ „ _

S3
I

MR14B

^MR14A

^
1

6 u u w

Q
Q
O-

MR14

g
2

X
o

-g

u
< u LU O

12 11

Mainframe Module and Cable Connector Map, Front View

Step

Procedure

Load f-he TEST-14 paper tape Into the test computer teleprinter paper-tape
reader as follows:
a .

Set the reader START/STOP/FREE switch to the FREE position

Release the cover guard by means of the latch at the right and open
cover

Insert the leader (start) end of the punched tape from the rear over the
reader sprocket wheel so that the small holes in the tape engage the

sprocket teeth and there are 3 holes spaces on the tape to the left of the
sprocket wheel

The leader portion of tape has a single row of large

holes and a single row of small holes.

d.
12
13

Close reader cover.

Place paper-tape reader START/STOP/FREE switch to START position.
Press test computer START switch momentarily.

reader until

Tape should now move through
completely read and only the trailing portion remains in the

reader

NOTE
If tape

stops before it has been completely read, place tape

leader in reader and press test computer

CONT switch

momentarily.
14

Remove the trailing portion of the TEST-14 paper tope from the reader by releasing the cover guard with the latch and opening the reader cover.
the tape off the sprocket wheel

Enter the number 2008 o" ^'^st computer console SWITCH REGISTER.

Lift

The

correct switch configuration for this is

000

010

000

LOAD ADDRESS switch on test computer console.

Press the

Enter the following configuration in the SWITCH REGISTER switches:

000
if

000

PDP~14 control unit module positions C20 and D20 are empty, or enter
000

000

100

000

PDP~14 control unit module positions C20 and D20 contain modules.

Press the START switch on test computer console.

Program will type

HOW MANY-I-BOXES?

Respond to this question by typing the number zero.

then press the carriage return (RETURN) key.

2-9

Procedure

Step

NOTE

19 (Cont)

Do not type the letter "o".

This character is not recog-

nized by the test program.

Program will type

HOW MANY 0-BOXES?
20

Respond to this question by typing the number zero.

Then press the RETURN I<ey

The program will type

HOW MANY HALF S-BOXES?

Respond to this question by typing the number of S-Box connectors inserted in
succeeding output box connector locations, then press RETURN key.

NOTE
Do not type the letter "I".

This character is not recognized

by the test program.

The test program will now start and run automatically.

PASS

If the

program types

COMPLETE

the PDP-14 has been tested and found to be operating properly.

In this case,

the problem can be assumed to be in an Input or Output box or in the machine
control program; proceed to Paragraph 2.4.

If the

program types anything else,

proceed to the following step.

NOTE
If the test

program types PDP-14 STOPPED, substitute PDP-14

control unit modules at locations AB23 (M741) and AB22

(M742). If the test program types PDP-14 HUNG, or if the test
computer RUN lamp goes out, substitute PDP-14 control unit
modules at locations AB23 (M741) and AB18 (M745).

If the test program detects a malfunction in the PDP-14 control unit, the
program will identify the problem area by typing a two-letter error code
flanked by asterisks. The module locations referenced by each two-letter
error code are identified in Table 2-1
Module types are presented in paren,

theses following the module locations (a module map is presented in Figure 2-3).

Substitute the module at the first location listed for a particular error code in

Table 2-1.

Press test computer STOP switch.
switch configuration for this is

000

010

000

001

2-10

Enter 201- in switch register.

The correct

Table 2-1
Test Program Error Code/Module Location Cross Reference
Error

Module

Error

Module

Code

Location/

Code

Locati on/

Typed

(Type)

Typed

(Type)

*AA**

AB18
A17
B17

C17
D17
C18
D18
AB23
AB24
C23
D23
*AB**

C19
D19
CIS
D18
AB24
C23
D23

**AC **

C21
D21

C18
D18
AB24
C23
D23

**AD**

C20
D20
C18
D18
AB24
C23
D23

(M745)
(M746)
(M746)
(M746)
(M746)
(M746)
(M746)
(M741)
(M740)
(M746)
(M746)

**AJ**

(M747)
(M747)
(M746)
(M746)
(M740)
(M746)
(M746)

**AE**

Same as **AB**

**Ap**

Same as **AD**

**AG**

Same as **AB**

**AH**

Same as **AD**

**AI**

AB18
AB23
C19
D19
C18
D18
AB24
C23
D23

**AL**

Same as **AJ**

**AM**

Same as **AJ**

**AN**

Same as **AJ**

**AO**

Same as **AJ**

**AP**

Same as **AJ**

**AQ**

Same as **AJ**

**AR**

AB23
AB24
C23
D23

(M741)
(M740)
(M74^)
(M746)

AB23

(M741)
(M744)
(M740)
(M746)
(M746)

AB24
C23
D23

(M747)
(M746)
(M746)
(M740)
(M746)
(M746)

**^1-**

Same as **AJ**

**AU**

Same as **AJ**

**^y**

Same as **AJ**

**AW**

CD22
AB24
C23
D23

2-11

(M744)
(M740)
(M746)
(M746)

**AX**

Same as **AJ**

**AZ**

Same as **AJ**

**g^**

Same as **AJ**

**BB**

Same as **AJ**

**BC**

Same as **AJ**

**BD**

Same as **AJ**

**gg**

Same as **AJ**

**BF**

Same as **AJ**

**BG**

Same as **AJ**

(M745)
(M741)
(M747)
(M747)
(M746)
(M746)
(M740)
(M746)
(M746)

(M746)
(M746)

Same as **AJ**

CD22

(M747)

(M740)

**AK**

**AS**

(M746)
(M746)
(M746)
(M746)
(M740)
(M746)
(M746)

AB24
C23
D23

Table 2-1 (Cont)
Test Program Error Code/Modu e Location Cross Reference

Error

Module

Error

Module

Code

Location/

Code

Location/

Typed

(Type)

Typed

(Type)

**BH**

CD24
Boxt
AB22

(M743)

AB23
AB24
C23
D23

(M742)
(M741)
(M740)
(M746)
(M746)

**BI**

Same as **BH**

**Bj**

CD24
AB24
C23
D23

(M743)
(M740)
(M746)
(M746)

**BK**

Same as **BJ**

**DI **

Same as **BH**

**BM**

AB22

CD24
AB24
C23
D23

(M742)
(M743)
(M740)
(M746)
(M746)

**BN**

Same as **BH**

**BO**

AB23
AB24

(M741)
(M740)

C23

(M746)
(M746)

D23

Refer to Paragraph 2.3.2.

2-12

**op**

Same as **BO**

**BQ**

Same as **BH**

**BR**

Same as **B0**

**BS**

Same as **BH**

**gj**

Same as **BO**

**BU**

Same as **BO**

**gy**

Same as **BJ**

**BW**

Same as **BO**

**BX**

Same as **BH**

**DY**

Same as **BH**

**BZ**

Same as **BJ**

**CA**

Same as **BJ**

**CB**

Sameas**BH**

**cc**

Same as **BH**

**CD**

AB18
AB24
C23
D23

(M745)
(M740)
(M746)
(M746)

**CE**

C19
D19
AB22
AB24
C23
D23

(M747)
(M747)
(M742)
(M740)
(M746)
(M746)

Step

Procedure

Press ihe LOAD ADDRESS swifch on test computer console. Test program will
now be repeated without typing questions. If the some error code is typed as

was typed during the previous test pass, substitute the module at the next location listed for that error code in Table 2-1 .

Continue to repeat this step until
program types PASS COMPLETE (regardless of pass number). The module just
substituted

defective and should be returned to the proper facility for repair.

If all

modules have been substituted and the same error code is again typed, or

if the

program types something other than a two-letter error code flanked by

asterisks, the control unit mainframe must be repaired off line, using information

provided in Chapters 3 and 4 of this manual

2.3.2

If the control unit and S-Boxes are functioning properly, proceed to Paragraph
2.3.2 to check the PDP-14 Program Storage modules.

PDP-14 Storage Box Fault Isolation Procedure

The storage boxes are checked by the test computer during the procedure described in Paragraph 2.3.1 above.
If

error code

**BH** (or any of the codes listed subsequently in Table 2-1 which refer to **BH**) is typed by

the test computer, the control unit module at location CD24 should first be substituted.

If,

upon repeating the test program, the same error code is printed, the following procedure should be performed

to check out the suspected storage box:

Step

Procedure

Note the leftmost 4-digit number associated with the error code.

Locate this number in Table 2-2.

(The numbers are listed in sets of 4.)

Note the mainframe location designator directly above the group of numbers
2-2 which contains the printed number.

in Table

Observe the S-Box connector inserted at this mainframe location.

This con-

nector should identify the S-Box with which it is associated.

Turn test computer and PDP-14 system OFF.

CAUTION
Failure to shut down test computer and PDP-14 System before removing or inserting modules can damage PDP-14

System components.

Remove the cover from the S-Box identified in step 4 by loosening eight 5/16
hex head screws which secure the cover to the S-Box shell

Referring again to Table 2-2, substitute the module at the S-Box locations
listed in the right-hand column, directly across from the group of numbers in
the Table containing the number printed by the program (see Figure 2-4).

Turn PDP-14 and test computer ON, and repeat the test (Paragraph 2.3. 1)
from step 16 until the defective module is located.

2-13

Tabl e2-2
Test Program Address/S-Box Modu le Location Cross Reference Table

S-Box cables must be inserted in sequence in the mainframe O-Box
Upper S-Box cables must be inserted in mainframe row C and lower S-Box cables must be inserted in
mainframe row D.
Upper S-Box Cable connected to Mainframe Module Location (see Figure 2-3)
C26
C25
C31
C30
C29
C28
C27
C32

NOTE:

In order for this table to be valid, all

locations.

0000-0003

0040-0043

0100-0103

0140-0143

0200-0203

0240-0243

0300-0303

0340-0343

Replace
S-Box

Module at
Location/
(Type)

A4(K207)
B3(K161)

A2(K135)

Leftmost
4-digit

number

0004-0007

0044-0047

0104-0107

0144-0147

0204-0207

0244-0247

0304-0307

0344-0347

typed by

B4(K207)
B3(K161)

A2(K135)

program

0010-0013

0050-0053

0110-0113

0150-0153

0210-0213

0250-0253

0310-0313

0350-0353

A1(K207)
B2(K161)

A2(K135)
0014-0017

0054-0057

0114-0117

0154-0157

0214-0217

0754-0257

Lower S-Box Cable connected to Mainframe Module Location (see Figure 2-3)
D32
D31
D30
D29
D28
D27

0314-0317

0354-0357

D26

D25

0020-0023

0060-0063

0120-0123

0160-0163

0220-0223

0260-0263

0320-0323

0360-0363

C4(K207)
C3(K161)
D2(K135)

0024-0027

0064-0067

0124-0127

0164-0167

0224-0227

0264-0267

0324-0327

0364-0367

D4(K207)
C3(K161)
D2(K135)

0030-0033

0070-0073

0130-0133

0170-0173

0230-0233

0270-0273

0330-0333

0370-0373

C1(K207)
C2(K161)
D2(K135)

0034-0037

0074-0077

0134-0137

0174-0177

0234-0237

0274-0277

0334-0337

0374-0376

D1(K207)
C2(K161)
D2(K135)

Leftmost
4-digit

number

B1(K207)
B2(Ki6i)
A2(K135)

typed by
program

STORAGE BOX

J)
J3

U
•^

hs
'E
o
o
o
CN
CN CN
D
V
^ ^
IN

r-N

1c
o
U

Half Storage Box Modules

K
N.
O
5 5 O
CN
CN
V V V
:^
R

W
K
O
5 ^ o
CN
CN
^ S2 S V

rs.

These modules added to form
^

Full Storage

Box

^
U

hs
o
<N

c
"D

h-s

o
CN
^ ^

"o
-1-

o
4

J
2

COLUMN
Figure 2-4

Storage Box Module and Cable Connector Map, Front View

2-15

Procedure

Step

the fault is not isolated, return to Table 2-1 and substitute the remaining control

unit modules listed for the

**BH** error code.

If the above procedure fails to isolate a defective module, turn ail power off,
remove all modules from the S-Box, and remove the S-Box connector panel by
loosening six Phillips head screws slightly and sliding the panel from beneath

the screw heads.

Substitute a properly functioning connector panel and replace all modules (see

Figure 2-4).

2.3.3

PDP-14 Read Only Memory Checkout Procedure

The control program for the machine system is stored within the PDP-14 Control Unit in Read Only Memory (ROM)
Assuming that the PDP-14 and the test computer are already interconnected and that

modules (see Figure 2-3).

power is ON in both machines, the ROM modules are checked by the following procedure.

NOTE
The PDP-14 Control Unit must be tested and found to be
working properly, using the procedure in Paragraph 2.3.1,
before testing the ROMs with this procedure.
Procedur e

Step

Place PDP-14 START/STOP switch momentarily in STOP position.

Set test computer SWITCH REGISTER to 7777^.
111

Press the

111

The switch configuration for this is

111

LOAD ADDRESS switch on test computer

Load the VER-14 paper tape into the test computer teleprinter paper tape reader
as follows:

b.
c.

Set the reader START/STOP/FREE switch to the FREE position

Release the cover guard by means of the latch at the right and open cover.
Insert the punched tape leader from the rear over the reader sprocket wheel

so that the small holes in the tape engage the sprocket teeth and there are

3 hole spaces on the tape to the left of the sprocket wheel
d

5
6

Close reader cover.

Place paper tape reader START/STOP/FREE switch to START position.
Press test computer START switch momentarily.

Tape should now move through

reader until completely read and only trailing portion remains in reader.

NOTE
If tape

stops before it has been completely read, place

tape leader in reader and press test computer CONT
If tape cannot be read, refer to
Chapter 4 of this manual to reload the BIN tape.

switch momentarily.

2-16

Procedure

Step

Remove the trailing portion of the VER-14 paper tape from the reader by releasing
the cover guard with the latch and opening the reader cover.

Lift

the tape off the

sprocket wheel

Load the LOAD-14 paper tape into the test computer teleprinter paper tape reader
using the procedure described in Step 4, above.

9
10

Place the paper tape reader START/STOP/FREE switch to START position.
Press the test computer START switch

momentarily.

The tape should now move

through reader until it is completely read and only the trailing portion remains
in

reader.

NOTE
If the

tape stops before it has been completely read, place

the tape leader in reader and press the test computer

CONT

tape cannot be read, refer to
Chapter 4 of this manual to reload the BIN tape.

switch momentarily.

If the

Remove the trailing portion of the LOAD-14 paper tape from the reader by releasing
the cover guard, using the latch at the right, and opening the reader cover.

Lift

the tape off the sprocket wheel

Load the PDP-14 program tape into the test computer teleprinter paper tape reader
The fan-fold paper tape contain-

using the procedure described in Step 4, above.

ing the control program is divided into sections containing the ROM program for
each of the ROM modules used in a particular installation. The leader punching
identifies the ROM module program contained in that segment of the tope as follows:
leader for ROM *1, one row of large holes; leader for ROM ^2, two rows of large
holes; leader for ROM *3, three rows of large holes; and leader for ROM *4, four
rows of large holes. To test a particular ROM, locate the appropriate leader in the
fan-fold paper tape and insert this leader in the paper tape reader.

Enter 74008 '" test computer SWITCH REGISTER switches.

The correct switch con-

figuration for this is

100

000

LOAD ADDRESS switch momentarily.

Press the test computer

Press the test computer START switch momentarily.

The PDP-14 program tape should
now move through the paper tape reader until it is completely read and only the
trailing portion remains in the reader.

NOTE
If the

tape stops before the ROM segment has been completely

read, place the tape leader in the reader again and press the
test computer

CONT switch momentarily.

Set the test computer SWITCH REGISTER to 60008-

The correct switch configuration

for this is

no
17

000

Momentarily press the test computer LOAD ADDRESS switch.

2-17

Step

Procedure
Set the test computer SWITCH REGISTER for the

ROM module to be tested

This

information is set into the two leftmost switches of the register as follows:

ROM #1; set switches to 00.
ROM #2; set switches to 01
ROM #3; set switches to 10.
ROM *A; set switches to
1 1

Set the remainder of SWITCH REGISTER switches to 0.

NOTE
The SWITCH REGISTER setting must agree with the PDP-14
program tape read into the test computer in Step 12, above.
19

Momentarily press the test computer START switch.
Momentarily move the PDP-14 START/STOP switch to START position.
test program will

now run.

If the

ROM module under test

The VER-14

functioning properly,

the teleprinter bell will ring in approximately one minute. If the program types
anything, the ROM module is defective, and must be replaced by a ROM module

containing the same PDP-14 program.

Do not remove defective module yet.

Momentarily press the PDP-14 and test computer STOP switches.

If the ROM module just tested was not defective and if there are additional ROM
modules which have not been tested, return to Step 12 and repeat this procedure
from that point until a defective ROM is located or until all ROM modules have
been tested

If a defective ROM module is discovered, place the PDP-14 and test computer
power switches OFF before removing ROM assemblies.

CAUTION
Insertion or removal of modules or connectors with power

applied can damage PDP-14 circuits.

Each ROM consists of a G924 module and an assembly consisting of a G922 module
and a G923 module. Substitute the G924 module first, and then repeat the VER-14
program. If the ROM under test continues to malfunction, remove the MR14A assembly, consisting of the G922 and G923 modules. Separate the two modules by
placing the aluminum keeper plate of the G922 module down and removing the 15
screws which secure the G923 module to the G922 module. Lift the G923 module
straight up from the G922 module. Substitute a spare G923 module, replace the
15 screws, replace the assembly in the control unit, and repeat VER-14. If VER-14
indicates an error, the new wiring should be checked for mistakes.

CAUTION
The ferrite transformer cores exposed during this procedure
Do not attempt to bend or otherwise apply
force to them. Be particularly careful when tightening

ore delicate.

the 15 screws.

2-18

Procedure

Step

NOTE

24 (Cont)

The G922 module which holds the wire braid containing
the control program contains no active electronics and
is

therefore not subject to malfunctions.

a spare

ROM module is substituted for a defective module, repeat this procedure

from Step 19.

Turn Power Switches OFF, remove test cables from PDP-14 mainframe, and reconnect all Input and Output box cables.

If all

ROM modules are functioning properly, proceed to Paragraph 2.3.4 to check

PDP-14 input and output boxes.

2.3.4
If the

PDP-14 Output Box Fault Isolation Procedure
trouble has been isolated to the PDP-14 System, but the preceding test computer checkout procedures

indicate that both the PDP-14 Control Unit and the control program

ROM modules are functioning properly,

then the malfunction must be in an input or output box.

If only a

single output fails to perform properly, the trouble is probably in that output box.

contains four output modules (K614) and seven associated modules (see Figure 2-5).

Each output box

To check the suspected

output terminal, only the output module containing that terminal and its associated modules need be substituted

by performing the following steps:

WARNING
Remove all power within the NEMA enclosure before proceeding
If the power is on, dangerous voltages are exposed during the following steps.
.

Procedure

Step

Remove the clear plastic protective cover from the output box by loosening four
captive thumbscrews

Remove the AC wiring from the terminals of the suspected output module (K614).

Remove the suspected output module by loosening the two 5/16" clamp screws
holding the module to the output box shell, and substitute a properly functioning
K614 module.

Connect the AC control wiring to the substitute output module terminals.

Replace the clear plastic protective cover.

Turn NEMA enclosure power ON.

NOTE
If the

enclosure door is equipped with a power interlock,

this interlock must be defeated in order to supply the out-

put boxes and PDP-14 with power.

2-19

OUTPUT BOX
4

INPUT BOX
4

.£1

U
A

-*-

®, U ,®
o
^®
®c

©s U
©^

•o

W
1^-

1—

(22)

lO
CO

@.
©^

K614

(15)

r—

CO©

s@
© > ©
©
©
©
@
4

COLUMN

COLUMN
NOTE

Circled Numbers Represent' Neon Lamps
and Associated Screw Terminals for AC
Control Lines.

Figure 2-5

Input and Output Boxes Module and Cable

Connector Maps, Front View

2-20

Procedure

Step

Place the PDP-14 POWER switch in ON position and allow a few seconds for the
power supply output voltage to stabilize.

Momentarily place the PDP-14 START/STOP switch in START position.

If the output box terminal now functions properly, return the defective output
module to the proper facility for repair. If the terminal still malfunctions, proceed to step 10.

Place the PDP-14 POWER switch in OFF position, turn all NEMA enclosure power
and refer to Table 2-3 to continue substitution of output box modules related

off,

to the malfunctioning output box terminal (see Figure 2-5 for module locations).

WARNING
Hazardous voltages are present on input and output box
terminals.

Always turn NEMA enclosure power OFF

before removing clear plastic protective covers from boxes.

Table 2-3

Output Box Fault Isolation
Defective Output

Number

Terminal

Substitute Modules at These Locations

One at a Time in Order Listed

AB4 (K614)
C3(K161)

B3 (K207)

4
5

CD4 (K614)

6
7

C3 (K161)
D3 (K207)

ABl (K614)

C2 (K161)

B2 (K207)

CD1 (K614)
C2(K161)

D2 (K207)

A2 (K135)

(ALL)

Procedure

Step
11

If the

preceding steps do not isolate a defective module, the trouble may be in

an associated input box (the control unit and ROM modules having already been
tested and eliminated as possible causes of the malfunction). However, the output box terminal assignment listing inside the NEMA enclosure door should be
carefully examined to determine if the conditions necessary to control the malfunctioning output terminal are also used to control other output box terminals.
In this way, it should be possible to eliminate most of the conditions that must

be checked, using the procedure below for input box fault isolation.

2-21

Procedure

Step
If t-he above

steps fail to isolate the trouble within the output box,

and a check

of the boxes associated with control conditions forthe malfunctioning output
terminal fails to isolate the trouble, the output box connector panel must be
substituted by removing all AC control wiring, the cable to the PDP-14 Control

Unit, and all output box modules.

Then remove the six Phillips-head screws securing

the connector panel to the output box frame
Substitute a properly functioning connector panel by securing it to the output box
frame with six Phillips-head screws, then replace all output box modules (see

Figure 2-5), as well as the AC control wiring and the cable to the PDP-14 Control
Unit.

2.3.5
If

PDP-14 Input Box Fault Isolation Procedure

several output box circuits are malfunctioning, and these output circuits share a single input box control con-

dition according to the output box terminal assignment listing in the

NEMA enclosure door, then the defective

component is probably in the input box circuits associated with the suspected input box terminal

The procedure

would then be as described below.

An input box circuit should also be checked if it is a condition required by only one output, and that output is
malfunctioning.

If the

output box circuits associated with the malfunctioning output terminal have been found

to be functioning properly using the procedure in Paragraph 2.3.4, then the input box circuits associated with

the suspected terminal should be checked.

WARNING
Remove all power within the NEMA enclosure, including
power to PDP-14 input box AC control circuits, before
processing. If power is on, dangerous voltages are exposed on the input box terminals during the following
procedure
Step

Procedure

Remove the clear plastic protective cover from the input box by loosening the
four captive thumbscrews that pass through the cover.

Remove the AC wiring from the terminals of the suspected input module (K578).

Remove the suspected input module by loosening the two 5/16" clamp screws
holding the module to the input box shell, and substitute a properly functioning
K578 module.

Connect the AC control wiring to the substitute input module terminals.

Replace the clear plastic protective cover.

2-22

Step

Procedure
Turn NEMA enclosure and all control input power ON.

NOTE
If enclosure door is equipped with a power interlock,
this
interlock must be defeated in order to supply output boxes

and PDP-14 with power.

ON position.

Place the PDP-14 POWER switch in

Momentarily place the PDP-14 START/STOP switch in START position.

If the

affected output box terminals now function properly, return the defective

input module to the proper facility for repair.

If the

terminals still malfunction,

proceed to Step 10.
10

Place the PDP-14 POWER switch in OFF position, turn all
off, including power to the input box control
to continue substitution of input box

terminal .

NEMA enclosure power

AC circuits, and refer to Table 2-4

modules related to the suspected input box

A module location map is presented in Figure 2-5 to assist in locating

the modules listed in Table 2-4.

Table 2-4
Input Box Fault Isolation

Defective Input
Terminal

Substitute Modules at These Locations

Number

One At a Time in Order Listed

AB4 (K578)
C3 {K161)

6
7

CD4 (K578)

C2(K161)

ABl (K578)

C3(K161)

23
24

25
26
27
28

CD1 (K578)
C2 (K161)

29
30
31

32
(ALL)

B2 {K135)

WARNING
Hazardous voltages ore present on input and output box
terminals.

Always turn NEMA enclosure power OFF

before removing clear plastic protective covers from

boxes

2-23

Procedure

Step

the preceding steps fail to isolate a defective input box module, the input box
connector panel must be substituted by removing all AC control wiring, the cable
If

to the PDP-14 control unit, and all input box modules.

Then remove six Phillips-

head screws securing the connector panel to the input box frame.
12

Substitute a properly functioning connector panel by securing it to the input box

frame with six Phillips-head screws, then replace all input box modules (see Figure
2-5), the AC control wiring, and the cable to the PDP-14 Control Unit.
13

the preceding steps have failed to isolate the defective component and an ac-

cessory box (A-Box) is used in the PDP-14 System, proceed to Paragraph 2.3.6.

2.3.6

PDP-14 Accessory Box Fault Isolation Procedure

Accessory boxes (A-Boxes) contain time delay and latching relay modules.

Checkout using the test computer

consists of the following procedure.

NOTE
The PDP-14 Control Unit must be tested and found to be
working properly, using the procedure in Paragraph 2.3.1,
before testing accessory boxes in this manner.
Assuming that the PDP-14 and the test computer are already interconnected and that power is

ON in both

machines, the A-boxes are tested as follows:

Procedure

Step

Place PDP-14 START/STOP switch momentarily in STOP position.
Set test computer SWITCH REGISTER to 1111^.

The correct switch configuration

for this is

in
3

Press the

111

LOAD ADDRESS switch on test computer.

Load the ABE-14 paper tape into the test computer teleprinter paper-tape reader
as follows:

Set the reader START/STOP/FREE switch to the FREE position

Release the cover guard by means of the latch at the right and open cover.

Insert the leader (start) end of the punched tape from the rear over the readejr

sprocket wheel so that the small holes in the tape engage the sprocket teeth
and there are three hole spaces on the tape to the left of the sprocket wheel

The leader portion of the tape has a single row of large holes and a single
row of small holes.
d

Close the reader cover.

Place paper-tape reader START/STOP/l=REE switch to START position.

2-24

Procedure

Sf-ep

Press test computer START switch momentarily.

Tape should now move through

reader until completely read and only trailing portion remains in reader.

NOTE
If

tape stops before it has been completely read, place tape
CO NT switch momen-

leader in reader and press test computer
tarily.

Remove the trailing portion of the ABE-14 paper tape from the reader by releasing
the cover guard with the latch and opening the reader cover. Lift the tape off the
sprocket wheel

Enter the number 200g on test computer console SWITCH REGISTER.

The correct

switch configuration for this is

000

010

000

LOAD ADDRESS switch on the test computer console.

Press the

Enter the following configuration in the SWITCH REGISTER switches:

000
11

000

Press the START switch on the test computer console.

Program will type

A-BOX IS CONNECTED TO SLOT
12

Complete this statement by typing the letter designator of the box according to the
control unit O-box cable connector designator to which the accessory box is connected (see Figure 2-3). Do not type the alphanumeric (row and column) identification within the control unit.

After typing the single letter, press the carriage

return key.

NOTE
Only one accessory box can be tested during one ABE-14
pass.

This procedure must be repeated beginning with

Step 8 if additional A-boxes are used.

ABE-14 program will type

IDENTIFY THE HARDWARE ASSOCIATED WITH EACH ADDRESS BY TYPING:
TIMER* M FOR RETENTIVE MEMORY* ALL ELSE EMPTY

T FOR

0000

NOTE
Retentive memory modules (K272) may only be inserted in accessory box locations A1, Bl, CI, and D1 .

Each K272 module

contains only one addressable latching relay. This relay can

only be addressed by the even octal address shown for that A-box
location position in Figure 2-6. If a K272 module is inserted in
location Al , the response to the ABE-14 query 0010 should be

followed by a carriage return. The response to the ABE-14
query Oil should be only the carriage return. This note applies
to K272 modules located at Bl, CI, and Dl for ABE-14 queries
0012 and 0013, 0014 and 0015, and 0016 and 0017 respectively.

2-25

Procedure

Sfep
13

Respond to this query by typing a T if a K302 module is located at this position
Accessory box modules may be observed by removing the cover. If no module is inserted in the accessory box

within the accessory box (see Figure 2-6).

position corresponding to 0000, type nothing.

Press the carriage return key.

ABE-14 program will type

0001
15

Respond to this query as described for 0000 in Step 13 of this procedure.

this response by pressing the carriage return key as described in Step 14 of this

procedure
16

Respond to queries 0002 through 0017 as described in Steps 13 through 15 of this
When query 0017 has been answered and the carriage return key

procedure.

pressed, the test program will be performed.

K272 modules are tested, the

program will type

POWER-DOWN
17

Respond to this print-out by placing the PDP-14 ON/OFF switch momentarily
then back to ON position. The program will type POWERDOWN up to four times, depending on the number of K272 modules inserted in
in OFF position,

the A-box.

The response is always as described above in this step.

the accessory box is functioning correctly, the test computer teleprinter bell

will ring to indicate the end of the test program.

an error is detected, the

program will type a two-letter error code corresponding to the defective module
or group of modules within the accessory box.

NOTE
ABE-14 types the delay measured for K302 modules.

This

figure must be compared with system documentation to de-

termine if the delay is correct.

This delay may be adjusted

using procedures described in Chapter 4.

Refer to Tables 2-5 and 2-6 to substitute the appropriate Accessory Box modules.
19

preceding steps fail to isolate the fault, substitute a properly functioning
connector panel by removing the cable to the control unit and all accessory box
If the

Then remove the six Phillips-head screws securing the connector panel
to the accessory box frame. Substitute a properly functioning connector panel by
securing it to the accessory box frame with the six Phillips-head screws. Then
modules.

replace all accessory box modules (see Figure 2-6) and the cable to the control
unit.

2-26

OCTAL

ADDRESS

COLUMN

JB
Jl

0000

0010

U
#-

Ov|

CM
>,
'c CO
O
O CM
r— CO \^
CO
D
v: )^
U. 6
^
CN

0001

OOn

(Valid for K302 only)

U
0002

0012
CM

O
00
^ 6

K
rv CM
O
o
o
CN CM CO
v:

04
hs
CM

L-

0003

0013

0004

(Valid for K302 only)

0014
CM

o
CO
V 6

>>,

f^
•o
p—
i^

r—
>o
r—

K
CN
o
00
CM

^ b^

s/.

0005

0015

0006

(Valid for K302 only)

0016
0>(

X o o O fc
CM
CM CM CO ^
^
^
^ O

CN
^^
CO "c

r-s

:i<i

0007

0017

(Valid for K302 only)

NOTES:
K302 is designated T in ABE-14 test program
K272 is designated M in ABE-14 test program

Figure 2-6

Any K302 or K272 module position may be left empty if not required.

Accessory Box Module and Cable Connector Map, Front View

2-27

Table 2-5
Accessory Box Module/ABE-14 Error Code Cross Reference

Accessory Box Module Type

ABE-14
Error

(Refer to Table 2-6 for module location based on 4-digit address

Code

printed with error code)

**BL**

**BN**
**BQ**

K207, K161, K135

**BX**
**gY**
**CB**

K302

**CG**
K272, K302, K207, K161, K135

**CH**

Table 2-6
Accessory Box Module Location/Address Cross Reference

Octal
Address

K302 (T)

K272 (M)

K207

K161

K135

Location

0000

0001

0002

0003

0004

0005

0006

0007

0010

0011

0012

0013

0014

0015

0016

0017

~
B3

C3
D3

~
A2

B2
Bl

2-28

2.3.7

Fault Isolation Without Test Computer

If a test

computer is not available and the fault has been definitely isolated to the PDP-14 System, a few simple

substitutions based on the symptoms observed may isolate and correct the fault.

all output box lamps are off and PDP-14 power is on, substitute control unit modules at AB22
(M742) then at AB23 (M741).

CAUTION
Always turn PDP-14 power OFF before substituting modules
to avoid possible damage to PDP-14 circuits.

If a single output terminal fails to turn on under any condition, substitute for the fuse associated
with that terminal in the K614 module containing the terminal in question. This is accomplished

by removing the K614 module from the output box and removing the fuse (located behind finned
heat sinks) using right-angle needle-nose pliers.
c .

The fuses are not soldered to the circuit board.

of the control outputs (output box lamps) come on when PDP-14 power is turned on but the
machine or process system fails to perform properly, substitute modules at the following locations in
the PDP-14 control unit one at a time and in the order listed:
If some

CAUTION
Always turn PDP-14 power OFF before substituting
modules to avoid possible damage to PDP-14 circuits.

C18 (M746)
D18 (M746)
C23 (M746)
D23 (M746)
AB24 (M740)

C19(M747)
D19(M747)
C21 (M746)
D21 (M746)

Memory Buffer Register
Memory Buffer Register
Instruction Register
Instruction Register

Instruction Decoder

Program Counter #1
Program Counter #1
Program Counter #2
Program Counter ^2

NOTE
Because modules are substituted one at a time, only one
These modules

spare module of each type is required.

M740, M741, M742, M746, M747. Module types
M743, M744, and M745 are used primarily when the
PDP-14 System is connected to an external computer.

are:

If the

above suggestions do not isolate and correct the PDP-14 System malfunction, an input box or accessory

box circuit may be faulty.

In this case,

the PDP-14 System should be taken off line for more detailed fault

isolation procedures.

2-29

CHAPTER 3

THEORY OF OPERATION
3.1

GENERAL

See Paragraph 1.1 for a description of the PDP-14 System General Philosophy.

Additional information of this

nature is also contained in the PDP-14 User's Manual

The control program is organized so that all the conditions required to turn a particular output on or off are
listed in a set of control

data words.

Control logic circuitry compares each program-specified function condi-

tion with the actual state of that function, testing each function state against its specified condition until a
logical decision to turn the output on or off can be made.

This process is repeated for up to 255 controllable output functions (see Figure 3-1).
is

again performed automatically.

Then the entire program

Thus, a given set of conditions for a particular output is examined repeatedly,

at a rate depending on length of memory.

Typical examination rates are:

IK of memory
2K of memory
3K of memory
4K of memory

15 milliseconds

30 milliseconds
45 milliseconds
60 milliseconds

Up to 256 machine system control inputs (limit switches, pushbuttons, etc) may be utilized as control conditions.
In order to increase the flexibility of the PDP-14 System, three additional functions are available:

retentive memories, and storage flip-flops.

time delays,

The delay timers and retentive memories are contained in accessory

boxes; the storage flip-flops are contained in storage boxes.

Full storage boxes contain 32 flip-flops; half

storage boxes contain 16 flip-flops.

The storage flip-flops, timers, and retentive memories (latching relays) are all controlled in the same manner
as output boxes which control the machine system directly.

addition to 256 input conditions, the PDP-14 control logic can test the state of every output condition, every

storage flip-flop condition, every latching relay condition, and the output state of all time delays.

3-1

NEMA ENCLOSURE
I

ADDITIONAL OUTPUT
STORAGE, AND ACCESSORY
BOXES TO A TOTAL OF 255
CONTROLLABLE FUNCTIONS

PDP-14 MAINFRAME

«
,

INTERNAL
1

15 VAC

POWER

60 Hz

POWER TO
ALL UNITS

UP TO 32 AC
INPUTS FROM
MACHINE SYSTEM

—

INPUT BOX
(32 AC TO
DC LEVEL

INSTRUCTION

WORD
ADDRESS

WORD

ING RELAYS)

STORAGE BOX
(32

STORAGE

FLIP-FLOPS)
UP TO
AC

BUS

TEST
BUS

ON/OFF

OUTPUT BOX

CONTROL

(16 FLIP-FLOPS

BUS

SAC SWITCHES)
z

OUTPUT
TEST
BUS
1

COMMON

—

OUTPUTS
TO
MACHINE

SYSTEM

CONTROL LOGIC CIRCUITS

CONVERTERS)

(TIMERS a LATCH-

READ ONLY MEMORY
-(UP TO 4,096 12BIT PROCESS CONTROL DATA WORDS)

BUS

INPUT

ACCESSORY BOX

SUPPLY
ADDITIONAL
INPUT BOXES
TO A TOTAL OF
256 MACHINE
SYSTEM INPUT
(8 BOXES)

AC
-POWER

-J

BOX AND FUNCTION i SELECTION BUS
OUTPUT TEST BUS

_J
14-0046

Figure 3-1

PDP-14 Controller, Simplified Block Diagram

NOTE
Storage and accessory boxes ore accessed by control logic

The number of outputs available for
machine control is diminished as the number of accessory and

circuits as outputs.

storage boxes is increased.

Figure 3-1 illustrates only internal mode operation.

In this mode, system operation

control program stored in the PDP-14 Read Only Memory.

controlled solely by the

However, the entire system may be monitored and

controlled by one of several general purpose computers; or, information may be transferred between this system

and another PDP-14 System controlling associated machine systems.

When the control program is contained in

an associated general purpose computer, the PDP-14 said to be operating in external mode.

Paragraph 3.2 provides an overall functional description of the PDP-14 system as operated in internal mode, and
includes a description of the basic instruction set.

Paragraph 3.3 describes in detail nonstandard logic hardware including operation of the "test flop" (test flag),
the basic functional element of the PDP-14 system, and its associated conditional jump circuits.

Paragraph 3.4 describes computer interface operations and logic circuits, including external computer instructions affecting PDP-14 System operations and

PDP-14 interface circuits required for external computer control

Throughout this chapter, reference will be made to detailed block diagrams (block schematics) and module
schematic diagrams (circuit schematics) contained in Volume II of this manual

These figures will be referenced

by a Roman numeral two (II) followed by a dash and the figure number in volume II (e.g., 11-12).

3.2

SYSTEM FUNCTIONAL DESCRIPTION

A detailed block diagram of the PDP-14 System is presented in Figure 3-2.

The paragraphs under this heading

describe the major functional blocks shown and their normal functional relationships during internal mode operation.

A brief description of the hardware required for computer interface operation is provided, but detailed

information on external mode operation is presented in Paragraph 3.4.

3.2.1

Internal

Mode Instruction Set

There are two major classes of instruction words in the PDP-14 instruction set (Table 3-1).

Class instructions

are used to access a specific input, output, storage, or accessory box terminal either to test the current state
of that terminal or function, or, in the case of output, storage, and accessory boxes, to set or clear the selected

function or terminal .

Basic instruction word formats are presented in Figure 3-3.

Class II instructions control the internal operations of control logic circuits.
those that perform program jumps.

This class of instructions includes

A jump instruction transfers control to a different port of memory.

3-3

rROM MODULE
:r
EXTERNAL
COMPUTER

STORED
CONTROL
PROGRAM

INTERFACE
WITH
PDP-8I,
PDP-8L,
OR PDP12

PGM.
ADDR.

MEMORY
BUFFER

)

PROGRAM ®
COUNTER #1

OP
CODE

INST.

PROGRAM ®
COUNTER #2

SKE+SKZ

DECODER

—

BIT BUS

UNDECODED PORTIONS OF BUS
BITS INDICATED IN

INSTRUCTION
WORD ADDRESS

OUTPUT

DECODER

(SEE FIG.
3-21

(

)

MSB = 0,LSB= 11

INCREMENT
OR

SPARE
REGISTER

DECREMENT

COMPARATOR

(4-11)

SKIP

TXN+TXF+TYN+TYF
CO
I

INST

WORD

INPUT

NOTES
1. REGISTER ADDRESSES INDICATED
BY CIRCLED NUMBERS

CLASS H INSTRUCTIONS)
(CLASS I
INSTRUCTIONS)

JFN+JFF

EXTERNAL
CONTROL
DECODER

SYN-t-SYF^

WITHIN
PAGE
JUMPS

(3)-

(4-5)

ARITHMETIC
CONTROL

^
SET

RESET
PULSER

(6-8)

SOURCE REG.
DECODER

GATES

(8-11)

INTERRUPT

(4-6)

CONDITIONAL
JUMP

MAJOR
STATE a

BOX
SELECT
DECODER

TIMING

CONTROL

TEST FLOP
X

TO ADDITIONAL
INPUT BOXES

32
115 VAC

CONTROL

TEST RET

DEST REG.
DECODER

-/* INPUT

INSTRUCTIONS)
Y SEL.

- ENABLE (Y
INSTRUCTIONS)

SYN+SYF

Y TEST RET

TO MORE
OUTPUT,
y STORAGE,
OR ACCESSORY

)

(8 LINES)

-/-

(9-11)

X SEL.
- ENABLE (X

r/o

BOX PAIR. SELECT

TERMINAL SELECT uBUS

FU,LL

INPUT

STORAGE BOX

BOX

(32 FLIP-FLOPS)

INPUTS.

Figure 3-2

BOXES

PDP-14 ConJroller, Detailed Block Diagram

OUTPUT
BOX

16 AC
SWITCHES

115

VAC

CONTROL
OUTPUTS

BASIC

OPCODE FIELD-

OPERATION —TEST AND CONTROL INSTRUCTIONS
FIELD

DECODER

—

(TXN)

TTTERMINAL SELECT

(TXF)

I,EVEN AND ODD BOX SELECT

(TYN)

I/O BOX PAIR SELECT

(TYF)

ON AND OFF TEST/CONTROL BIT

(SYN)

OUTPUT REGISTER FORMAT

(SYF)

"-TRANSFER TO PDP-8

(SAME AS TEST AND CONTROL)
L- INFPUT AND OUTPUT FUNCTION SELECT (0=X,1«Y)

(TXD)

(TYD)

SPARE (ALWAYS ZERO)

SELECTED TERMINAL STATE

•— TEST FLOP STATE

TRANSFER ARITHMETIC INSTRUCTIONS-

TRR

DESTINATION REGISTER

EEM
LEM
SOURCE

SKE
SKZ

ARITHMETIC OPERATION AT DESTINATION

jMPA FIRST WORD of two
J MS J

W°'"' INSTRUCTIONS

(DECODED WITH BASIC OPCODE)

JMR
CONDITIONAL JUMPS

JFF
J FN

ROM ADDRESS IN PAGE

L- ON AND OFF CONDITION BIT

(JMP + JMS INSTRUCTION ADDRESS +I) + (PC2) FOR JMR

SECOND WORD OF
"UNCONDITIONAL JUMPS
mpI SECOND WORD

TT ROM ADDRESS

OF TWO WORD

MS J INSTRUCTIONS

— ROM PAGE NUMBER.

IN PAGE *!
>

ADDRESS
IN
IK

ROM

— ROM BANK NUMBER
14-0046

Figure 3-3

InstrucMon Word Formohs

3-5

Table 3-1

PDP-14 Internal Mode Instruction Set
Assembly

Language

Op Code Field

Mnemonic

MSB (Bit 0)

Definition

TXN

010 1

Set test flop if specified input is ON.

TXF

010

Set test flop if specified input is OFF.

TYN

001

Set test flop if specified output terminal, storage flipflop, latching relay, or timing circuit output is

TYF

001

ON.

Set test flop if specified output terminal, storage flipflop, latching relay, or timing circuit output is OFF.

SYN

oil

Set

ON specified output terminal, storage flip-flop,

latching relay, or start delay timer.

SYF

Set OFF specified output terminal, storage flip-flop,
latching relay, or clear delay timer.

CLR

oil on 111 111

Sets OFF all output terminals, storage flip-flops,

(3377g)

clears delay timers when address

and

3773(256]o) is specified.

For this reason, only 255io controllable output functions

ore available.

JFN

110 1

If test flop is set (ON), jump to relative address specified
by bits 4-11 of JFN instruction word and reset test flop.
If

test flop

reset (OFF),

jump is not performed, and next

sequential instruction is executed.

JFF

1100

If test flop is reset (OFF), jump to relative address specified
by bits 4-11 of JFF instruction word. If test flop is set,
jump is not performed but test flop is reset, and next se-

quential Instruction is executed.

JMP

100 010 010 100

Unconditional jump to instruction word located at the ad-

(4224g +NNNNg)

(NNNN3) specified in the next sequential memory
address (two-word instruction).
dress

100 110 100 101

Unconditional jump to subroutine instruction word located

(4^5g)

at the address specified in the next sequential
dress (two-word instruction).

memory ad-

Return address to resume

primary routine is stored, minus 1,

PC2 for use by JMR

instruction at end of subroutine.
J MR

000 on 101 100

Unconditional return jump from subroutine to primary rou-

(0354g)

tine address stored by JMS instruction in PC2, plus one.

Used at completion of all subroutines.

TXD

111

TYD

111

TRM

Provides state of selected input terminal and current state
of test flop to external monitoring computer.
1

Provides state of selected output terminal and current state
of test flop to external monitoring computer.

100010010 110

TRM Is a two-word instruction which transfers the next se-

(4226g + NNNNg)

quential

ROM word to the PDP-14 Output Register for use
by a monitoring external computer. No restrictions are
placed on the contents of the transferred word.

3-6

Table 3-1 (Cont)

PDP-14 Int-erna! Mode Instruction Set
Assembly
Language

Op Code Field

Mnemonic

MSB (Bit 0)

Definition

SKP

ROM instruction.

000 011 100 100

Skip the next sequential

(0344g)

following the skipped instruction

The instruction

executed (the second

sequential instruction following the SKP instruction).

SKE

Causes PCI to skip the next sequential ROM memory address if the PDP-14 register specified by the X-field is

110 111 XXX 100
(67X4g)

equal to the contents of PC2.

SKZ

110 011 XXX 100

Causes PCI to skip the next sequential ROM memory ad-

(63X4g)

dress if the PDP-14 register specified by the X-field is

equal to zero.

There are two types of program jumps employed in the PDP-14 system.

Unconditional jumps (JMS,

are made whenever the Jump instruction is encountered in the control program.

PDP-14, however, are two conditional jump instructions.

In a

JMP, JMR)

Basic to the operation of the

conditional jump (JFF, JFN), the jump to a

specified control program address is performed if and only if some condition is satisfied.

In the

PDP-14, the

two conditional jump instructions are performed if and only if the state of the test flop agrees with the condition
specified for the test flop in the conditional jump instruction.

.Also included in Class II are those instructions which transfer data

between pairs of registers within the PDP-14.

Each register and counter is identified in Figure 3-2 by a circled number corresponding to the octal number

decoded to access that register or counter.

If the

counter specified in the instruction is capable of basic arith-

metic operations (incrementing, decrementing), the arithmetic operation is also defined in the instruction.

The basic instruction Op Code (operation code) is contained in the most significant four bits (bits 0-3) of all
words except the second word of two-word instructions where these bits specify the ROM "page" in which the
instruction word specified by the remaining bits

located.

The op code decoder sets up the controls required

to execute the instruction specified in bits 0-3 of the instruction word.

With the exception of the two-word instructions, the remaining bits of the instruction word form the effective
address; that is, the address of the input or output, or internal registers affected by the instructions.

Bits 4-11

are decoded in Class I instructions to select an input or output (X or Y) function, bits 4-7 being decoded by

the box select decoder to select half the inputs of a particular input box and all the outputs of an output box.
Bits 8-11

are bused to all input storage and accessory output boxes, but only the box enabled by the box select

decoder is permitted to complete the selection process by decoding bits 8-11
input and an output function.

Bits 4-11

always select both an

The final selection process is determined by the basic Class I Op Code.

3-7

If the

instruction code mnemonic contains on X, only the selected input is accessed.

If the

code contains a Y, only

the selected output or function is accessed for monitoring or control

Class II instructions employ the same four-bit Op Code (bits 0-3).

The remaining bits of the instruction word

define which register or counter is to be the source of the data transfer, and which register or counter is to be
the destination, as well as what arithmetic operation is to be performed on the data by the destination register.

NOTE
The terms "register" and "counter" are not used in the strict

PC2 is not a counter, it is a gated flipThe Spare Register is capable of basic arith-

sense of the terms.
flop register.

metic operations with bits 6-11 (incrementing, decrementing).
Instruction word bits 6-8 define the source register, and bits 9-11 define the destination register.

The octal

code designations of the various registers are indicated by a circled number within each register or counter of
Figure 3-2.

There is no register or counter corresponding to 0- (000„).

the "dummy" register.

This empty register designator is called

Table 3-2 summarizes the registers and counters within the PDP-14, their capabilities,

and major uses.

Table 3-2

PDP-14 Register and Counters
Source/

Name

Major Use

Destination

Capabilities

Code

Dummy

000 (source only)

No operation

As source, provides all ones

(No Register)
Instruction Register

to destination

001

Memory Buffer

010

Spare Register

Oil

Stores instruction word for

Flip-flop register storage

execution

only

Stores word read from

ROM

Flip-flop register storage only

Utility counter, return ad-

Increment, decrement,

dress storage for nested sub-

transfer

routines

Program Counter *1

100

Stores address of next

ROM

Program Counter *2

Input Register

101

110 (source only)

Increment, decrement,
transfer

instruction

Stores return address during

Flip-flop register storage

subroutines

only

Flip-flop buffer from data
transfer from external

com-

Only as stated under major
use

puter to PDP-14

Output Register

110 (destination

Flip-flop buffer for data

only)

transfer to external

computer

Only as stated under major
use

from PDP-14

(No Register)

111 (destination)

Only as stated under major

Halt

use

3-8

the destination counter or register is capable of performing the operation listed, bits 4 and 5 of Class II

instructions specify the arithmetic operation as follows:

Bits

Arithmetic Operation

Transfer
1

Transfer

3.2.2

Transfer, decrement by one

Transfer, increment by one

Cycle Control and Data Transfer

In addition to the registers and counters described in the preceding

paragraph, a method of transfer between

selected source and destination registers and counters is required.

This is accomplished by a single 12-bit

data transfer bus.

When a particular register or counter is selected as the source of a data transfer, output

gates from that register to the data transfer bus are enabled.
also enabled.

The selected destination register or counter is

The destination register is either (1) force loaded as a simple flip-flop register, or (2) is used

to combine the data held in the source register with the contents already in the destination counter as described

above in Paragraph 3.2.1.

Registers and counters not selected as the destination in a Class II instruction are unaffected by the data present

on the data transfer bus.
bit (wire) of the bus will

If source

be at a logic one potential

The selected destination register will therefore be loaded

with all ones (if an increment is also performed, the register is cleared).

In Figure 3-2, all possible sources for a particular register or counter are shown entering the register box from

the top.

Only one source is active at a particular time. Likewise, all possible destinations are shown leaving

the register box from the bottom, but only one destination is active (the transfer bus being considered as one
destination for the source register).

To complete a functional description of the PDP-14, it is necessary to mention the major states in which the
instruction words are obtained and performed.

ROM (or from an external computer).
state is decoded and executed.

During the Fetch state, an instruction word is obtained from the

During the Execute state, the instruction word obtained during the Fetch

The PDP-14 contains only these two major states.

Within each major state, additional timing pulses and time delays are required to properly synchronize the
transfer of data and permit data to stabilize from the

ROM and external computer lines.

The two major states and cycle timing are discussed in detail in Paragraphs 3.3.2 and 3.3.3.

3-9

3.2.3

External Compul-er Interface and Skip Comparator

In order for an external

provided.

computer to be interfaced with the PDP-14, a special external control decoder is

This decoder is under control of the external computer; upon decoding an interrupt signal from the

external computer, the decoder will stop the PDP-14 internal timing at the appropriate point in the PDP-14

A signal ("flag") is also produced by the

cycle and synchronize the PDP-14 with the external computer.

PDP-14 whenever the output register is loaded with data for an external computer..
Data transfer between the PDP-14 system and an external computer is accomplished via the input and output
registers.

In addition,

PDP-14 instructions from the external computer during an interrupt or during external

mode operation are loaded directly into the memory buffer register (via the memory port). The ROM memory
modules are disabled during interrupts and when PDP-14 instructions are received from an external computer.

The skip comparator is employed primarily as a diagnostic tool

It is

used to test the contents of a specified

source register against the contents of PC2 when an SKE (skip if equal) instruction is executed, or to test the
contents of a specified source register for all bits equal to zero when an SKZ (skip if zero) instruction is executed.
If the

specified skip condition is satisfied, the instruction immediately following the skip instruction is skipped

and the second sequential instruction is fetched and executed.

3.3

DETAILED CIRCUIT DESCRIPTIONS

The circuit schematics presented in Volume II of this manual consist of standard electronic and MIL-STD-806
logic symbols.

An important exception, however, is a special symbol used for gated flip-flops.

This symbol

and its equivalent logic circuit is shown in Figure 3-4. When the clock level is high, the state of the flip-flop
cannot be changed from the data input or output terminals.

3.3.1

Test Flop and Conditional Jumps

The input, output, storage, or accessory condition to be tested is selected by the address field of Class I instructions (see Figure 3-3).

The return from test condition is compared with the state of bit 3 of a TXN, TXF,

TYN, or TYF instruction in the test comparator (Figures II-2 and 3-5).
If the selected

condition is the same state as the state of bit 3 of the test instruction word, the "test true" output

of the test comparator sets the test flop at the end of the execute major state.
test flop to the

A loop from the set output of the

OR gate data input to the test flop ensures that no subsequent test will have any affect upon the

test flop once it is set

The Jump comparator (see Figure 3-5) is enabled for JFN or JFF instructions. The jump comparator tests the state
of the test flop against the requirements of the conditional instruction to enable setting the "JF OK" flip-flop.

3-10

(DC SET)

LOGIC SYMBOL

(DATA) I'SET
'RESET

CLOCK

-(SET OUT-

PUT-

DIFFERENTIATOR

^jT
(CLOCK)-

^'N__k.CL(LOCK

^ PU LSE

(RESET
OUTPUT- I)

(DC RESET)

Figure 3-4

Gated Flip-Flop and Equivalent Logic Circuit

The conditional |ump instructions also employ bit 3 of the instruction as the test condition.
has bit 3 of the instruction word set.
test flop

set.

state for the JF

A JFN instruction

Therefore, the jump comparator will set the JF OK flip-flop only if the

A JFF instruction includes bit 3 in the reset state; therefore, the test flop must be in the reset

OK flip-flop to be set.

The test flop is reset by a JFF or JFN instruction, regardless of whether or not the conditions required for the
conditional jump are met.
test flop,

In fact, the

and they will always reset it.

JFF and JFN instructions are the only instructions which will reset the
If the

jump comparator enables setting the JF OK flip-flop, the ROM

memory page address specified in bits 4-11 of the JFN or JFF instruction is enabled; a transfer of this address
is

then made to PC 1

NOTE
Because the final output from the jump comparator to the

JF
flip-flop is inverted, the set output of the JF
flip-flop is the "0" output of the flip-flop symbol

3-11

(M743)

INITIALIZE(L)-

(M74I)

— PAGE JUMP OK(L)
PAGE JUMP OK(fl)

SAMPLE
RETURN
CO
I

TEST COMPARATOR

LINE
(INVERTED
FORM)

IR03 (TEST CONTROL BIT)

I
I

Figure 3-5

"EXECUTE (H)
TYN+TYF+TXN+TXF
END CYCLE PULSE
INITIALIZE L

IR03(H)
(JUMP CONTROL BIT)

Test Flop and Associated Circuits, Simplified Logic Diagrar

(JFN*JFF)(L)TSl

EXECUTE -'(4)

The jump is called a page jump because only a partial ROM address can be held in bits 4-1 1 of the conditional
jump instruction word.
(Bits

0-11).

An unrestricted jump to any address within the ROM requires all instruction word bits

Address bits 0-3 are therefore called the "page" selection field and bits 4-11 specify the location

within a page containing the instruction word.

The unconditional jumps (JMP, JMS, and JMR) provide the

entire address field so that page restrictions do not apply.

The conditional jumps will always be made to an address within the page specified by bits 0-3 of PCI at the
time the jump is performed.

Data input to the JF OK flip-flop is enabled by the timing pulse, but data is

available only during time state

of an execute cycle.

Thus, the JF OK flip-flop can only be set during time

of an execute cycle if the conditional jump condition is satisfied.

state

If the

JF OK flip-flop is set during time state 1, bits 4-11 of the instruction register are gated to PCI bits 4-11

during time state 2.

The address contained in the conditional jump instruction will now be read, and the in-

struction at that address supplied to the instruction register for execution.

This address is in the control program

"page" specified by the original contents of bits 0-3 of PCI

If the

JF OK fiip-flop is not set during a conditional jump instruction execution, the test flop is cleared and

the next sequential instruction (PC)+1

read and executed.

The conditional jump is not performed if the JF OK

flip-flop is not set.

3.3.2

Major States

Figure 3-6 illustrates the two major states, fetch and execute, of the PDP-14 control unit.

indicated at the top of the flow chart.

The timing states are indicated down the left side of the chart.

fetch state is invariable and is always used to obtain a new instruction word from

Figure 3-7.

3.3.2.1

The

ROM (or an external computer)

Major state and timing cycle relationships are shown

to be executed during the following execute major state.
in

These two states are

These circuits are shown in block diagram form in Figure II-2.

Fetch - The fetch major state during internal mode operation is invariable, it always places an in-

struction word into the instruction register and increments PCI in preparation to read the next sequential

word

from ROM (whether this word will in fact be read depends on what happens during the following execute major
state)

However, during the pause cycle at the beginning of the fetch major state, an interrupt flag set by an external
computer will be honored by the PDP-14.
data bus instead of from the ROM.
instruction register.

When this flag is honored, the memory buffer is loaded from the input

During time state

1 ,

the contents of the memory buffer are transferred to the

This is the only method an external computer has to interrupt the PDP-14 system.

Unless

the instruction gated into the memory buffer during an interrupt is an EEM (enter externa! mode) instruction.

3-13

START
CYCLE

FETCH

EXECUTE
TXN+TXF+TYN+TXD+
TYF+SYN+SYF+TYD

ALL INSTRUCTIONS
TRR

SKE+SKZ

EEM+LEM

JMP+JMS

EXT MODE (I)

INTERRUPT (1)-EXT MODE
INTERRUPT (l)EXT MODE (1)

O—MB
I

—EXT

—

MB
O
PDP8-BAC
MB

O—MB

—

FLAG

— EXT FLAG

— MB
y/////m

MEMORY

ADDRESS
PROPOGATION DELAY
TO INTERFACE

MEM GO

CYCLE
MEM GO
I0Tt64

0— EXT FLAG
PDP8-BAC— MB

lOT 164

— EXT FLAG

MEM DONE

SYN+SYF

PDP8-BAC— MB
EXT DONE

EXT DONE

EEM
TRANSFER
REG X
REG Y

—

LEM

0— EXT MODE

1— EXT MODE

}

TIME
STATE

—

SOURCE REG
X = PC2
I— SKIP OK

SKZ

JFF

SOURCE REG

X=0

1— SKIP OK

JFN

TEST FLOP=0

TEST FLOP=t

1— JF OK

REG X

Y=7

0— RUN

ff,

7//,

SAMPLE
RETURN
DELAY

— REG Y
Y= 7

REG X— REG Y

TSl

OUTPUT
SET RESET
STROBE

W/M

TRANSFER

SKE

YtIR

0— RUN

Y=7

13
O— RUN

INTERRUPT (1)
PCI + 1

TIME

—

PCI

STATE 2
TS2

SKIP OK (1)

PCI +

I— PCI

— SKIP OK

SKIP OK (0)

vlF

OK (11

REGY = PCI

OK (0) JMP

TRM.TRS

REG YtPCI

JMS

PCI(0-3)»MB(4-8)

—

PCI

0— JF OK

PCI+1— PCI

MB— PCI

TXD + TYD

Z3
—» FETCH

LOAD OUTPUT
REGISTER

— TEST FLOP

I— EXECUTE

J
IF

TEST TRUE

I— TEST FLOP

i=e

END
CYCLE

0—
— EXECUTE

PULSE

FETCH

RUN (0)
HALT
I

RUN (1)
I

START CYCLE
I

Figure 3-6

PDP-14 Controiier, Flow Diagram

3-14

TWO -WORD

INTERNAL
A
JFN SKE SKZ
NOP JMR SKP JFF
WITH INTERNAL MEMORY

TIME

FETCHdIH
{A23J1)

X
TXM TXF TYN TYF
TXD TYD SYN SYF
WITH INTERNAL MEMORY

WITH INTERNAL MEMORY

(MICROSECONDS).

INPUT /OUTPUT

A
JMP JMS TRM

20.8

•>^

^
VA-

EXECUTE (1) H
(A23E1)

PAUSE (1) H

650

(B23T2)

TS1 (1) H
I

(B23M2)

500

r!-4|
TS2 (1) H
(B23L2)

START CYCLE H IISQ.
"«

(A23T2)

MEM. GO H
(A23N1)

..n

-re

MEM. DONE L
(AZ3E2)

-PA
I

END CYCLE L
a
START EXTERNA
(A23F1)0R(B23K2)

uufl^

T PULSE

(B23H

00 (IS

-ye

.Ji

'n^

4 00n8-

-400n8
NOTE: MAINFRAME TEST POINT
COORDINATES INDICATED
IN PARENTHESES

I/O CYCLE (1)H,

(BZ3UZ)

18.5|is

I/O STROBE Lj.

(B23R1)^
!l2;is

Figure 3-7

Control Logic Timing Diagram

3-15

the Interrupt will result in only a "cycle steal" operation; that is, the instruction specified by the external

computer will be performed but control will then revert to the PDP-14 ROM program, picking up at the instruction following the lost

If,

ROM program instruction executed.

during an interrupt, the external computer places an EEM instruction on the input data bus, the external

mode flag is set and all subsequent instructions must come over the input data bus until the external computer
initiates a

LEM (leave external mode) instruction.

To execute this instruction, the PDP-14 resets the external

mode flag and resumes the ROM program at the address currently stored in PCI
into the external program, this address will not be the next sequential

•

Unless specifically programmed

ROM instruction following the last ROM

instruction executed.

The fetch/execute control flip-flop is set to the fetch
state when the PDP-14 is initialized in order to obtain

the first instruction word from the

ROM or external

computer (see Figure 3-8).

3.3.2.2

Execute - The fetch/execute control flip-

AB23
flop is toggled to the execute state by the fetch major

(M741)

EXECUTE (H)-

FETCH (H)

state end cycle pulse (see Figure 3-8).

Three types of

execute cycles exist, as shown in Figure 3-7.
I

FETCH/

EXECUTE
C

INITIALIZE (L)

If an

internal instruction is decoded during the fetch

cycle, no pause cycle (involving ROM or external

computer) is required.

If a

two-word type instruction

(JMP, JMS, TRM) is decoded, a pause cycle is reEND
CYCLE
PULSE(L)

quired during the execute major state.
is in

This pause cycle

addition to the two time states required for an in-

ternal instruction execution.

Execution of instructions

involving input or output functions (input boxes, output boxes, storage boxes, or accessory boxes) do not
require either a pause cycle or the two time state

Figure 3-8

3.3.3

cycles.

Fetch/Execute Major States Toggle

Timing Cycle

As described in Paragraph 3.3.2, the timing cycle for the fetch major state is fixed while the timing cycle for
Execute may be one of three sequences (see Figure 3-7).

The discussions under this heading describe the start,

pause, input/output, time states, and end pulse timing.

These circuits are shown in block diagram form in

Figure II-2.

3-16

3.3.3.1

Start Cycle -

Figure 3-9).
transistor.

A start cycle pulse is initiated by an end pulse or by an external start pulse (see

The start pulse generator produces a negative-going pulse to the base of the start cycle delay

The negative-going pulse on the base of this NPN transistor turns the transistor off, permitting

the charge of the anode of the start cycle delay capacitor to rise.

When this charge reaches the threshold of

the input gate of the start pulse generator, the start pulse is initiated.

AB23

(M741)

+ 5V

1=0. SRC

+ 0.7V-

-4.3V-

200 n sec

START DELAY

START CYCLE (H)

END CYCLE (L)

EXT START (L)
(FROM MANUAL'
SWITCH CIRCUITS)
RUN(H)

k—H n150
sec

Figure 3-9

Start Cycle Control, Simplified Logic

Diagram

The start cycle pulse is terminated by a loop from the output of the start pulse generator to its input.

When the

charge on the start pulse generator capacitor is bled through the resistor to ground, the output of the start pulse
generator inverter goes high, turning on the transistor which in turn terminates the start cycle pulse.

As long as

the RUN flip-flop is set, the start cycle pulse generator output gate is enabled.

3.3.3.2

Pause Cycle (Memory and External Control) - The Pause control flip-flop (Figure 3-10) is set if a JMP

or JMS instruction is decoded during an execute major state or if the fetch major state flip-flop is set.

The pause

flip-flop clock is triggered by the positive edge of the start cycle pulse or by the memory done or external done

pulses.

3-17

INITIALIZE (L)

FETCH (L)
CLEAR MEM.BUFFER{L)

EXTERNAL GO(H)

MEMORY GO(H)

MEMORY + EXIT. DONE (L)
(TO DC SET OF TS 1)

NOTES:
1,

MEM DONE(L)
EXT. DONE(L)

Figure 3-]0

ENABLE LOOP (H) IS HELD (ON) AS LONG AS AT LEAST
ONE ROM MODULE IS INSTALLED IN MAIN FRAME.

Pause Cycle Coniroi , Simplified Logic Diagram

A loop from the pause (L) output of the Pause flip-flop to the data Input gate disables that gate so that when the
memory done or external done pulse occurs the flip-flop will be reset.

Setting the Pause flip-flop triggers a

pulse generator, the output of which clears the memory buffer and initiates a

ROM read cycle, if in internal

mode, or requests a new instruction from an external computer if in external mode or if an external interrupt

Note that if an interrupt instruction (TRM) occurs while the PDP-14 is in external mode, the pause

occurs.

circuit will initiate a

ROM read cycle during the execute major state. This feature

useful in checking the

ROM program from an external computer. A loop from the memory go (H) gate output to the enable loop gate
prevents the PDP-14 timing from "hanging" in the pause cycle if there are no ROM modules installed in the
mainframe.

NOTE
Timing cycle will hang if ROM modules are installed in
other than sequential locations, beginning at

ROM

This situation may occur during maintenance when the PDP-14 is being operated from an external computer.

This

loop ensures that the PDP-14 is running (no operation instruction cycles) and can therefore be controlled from

an external computer.

An external computer cannot interrupt the PDP-14 if the PDP-14 is not running, thus no

external instructions can be performed if the PDP-14 is hung.

The output of the enable loop gate is combined in an OR gate with the memory done and external done lines.

The output of this OR gate supplies the clock pulse to reset the pause flip-flop and sets time state 1 (TSl) flipflop to continue the major state cycle.

3.3.3.3

Input/Output (I, O, S, and A Boxes) - The l/O cycle flip-flop is clocked by the leading edge of the

start cycle pulse (see Figure 3-1 1).

The data input is controlled by a NAND gate, which is satisfied if an

Input/Output type instruction (TXN+TXF+TXD+TYD+TYN+TYF+SYN+SYF) is decoded during the execute major
state.

An address decode delay circuit is employed to permit the address selection process to be completed

before the strobe l/O pulse is initiated.

This delay must compensate for propagation to and decoding of the

low order address bits within the selected box.

A subsequent data return delay circuit compensates for the data returned from the selected box address before
producing the l/O done pulse.

The l/O done pulse or initialization resets the l/O cycle flip-flop.

The l/O

done pulse also initiates the end cycle control circuit (the two time states are not required during l/O instruction execution).

The strobe pulse is used with SYN or SYF instructions to gate set or reset data onto the control buses to the
selected output, storage, or accessory box function addressed.

The l/O done pulse delays the end cycle pulse

sufficiently to allow data to stabilize on data return bus before the end cycle pulse clocks test results on that

data into the test flop.

The delayed end cycle pulse also clocks the loading of the output register during TXD

and TYD instructions.

3-19

SYN+SYF(H)-

^I>-

STROBE SET/RESET
"CONTROL BUSSES(L)

(i-STROBE I/O (L)
I/O CYCLE (D-

—

lA) CYCLE (H)

ONE SHOT

•

ONE SHOT

I/O DONE PULSE

GENERATOR

I/O CYCLE

ADDRESS
DECODE
DELAY

RETURN
DATA
DELAY

START
CYCLE (H)

EXECUTE (H)

TXF+TXD+TXN+ TYD +
TYN* TYF+ SYNt SYF +

—

INITIALIZE (H)

Figure 3-11

l/O Cycle Control, Simplified Logic Diagram

PULSE

AMPL. D

I/O DONE (H)
(TO END CYCLE

LOGIC)

Time States, Timing Pulse, and End Cycle Circuits - The two time state flip-flops, TSl and TS2,

3.3.3.4

control data transfer within the mainframe (see Figure 3-12).

Both flip-flops are reset during initialization.

During the fetch major state, the TSl flip-flop is set (DC set input) by the memory done pulse from the ROM

module, or by an external done pulse from an external computer if an interrupt or external mode instruction
occurred during the initial pause cycle of the fetch state.

During the execute major state, the TSl flip-flop is set (data input) if TS2 is reset and so long as the decoded
instruction

not an input/output or two-word instruction.

The clock is provided for this condition by the

trailing edge of the start cycle pulse.

Upon being set, TSl initiates a timing pulse delay. The timing pulse generator is triggered at the end of this
delay.

The data input to the TS2 control flip-flop is the set

The timing pulse clocks both time state flip-flops.

output of the TSl flip-flop.

Therefore the TS2 flip-flop is set when the timing pulse occurs.

Time state two has its own timing pulse delay circuit.

Two delay circuits are required because one could not

recover rapidly enough following the reset of time state one to be of any use as a time state two delay (time
state two follows time state one at the same clock time).

At the end of the TS2 flip-flop is reset because TSl

was previously reset. The existence of the timing pulse while TS2 is set also produces the end cycle pulse (the
time state flip-flops are clocked on the trailing edge of the timing pulse, the end cycle pulse begins on the
leading edge).

As the time states are not used for input/output instructions, the end pulse is also produced by

the l/O done pulse.

The end cycle pulse clocks execute and fetch major state control flip-flops, test flop operations, and output
register loading for TXD and TYD instructions.

3.3.4

Manual Control and Power Detection Circuits

Initialization is accomplished automatically by its power detection circuits, or by the STOP/START switch.

When PDP-14 internal power is first switched on, the collector output of the power up sense circuit is held low
because of the on bias maintained on its base through a capacitor, the other side of which is connected to the

+5 volt power bus (Figure II-l and 3-13).
this bus

The output of the transistor is connected to the start (L) bus.

When

low, the capacitor in the input circuit to the Schmitt trigger is shorted and the initialize line is

active to ensure that all control flip-flops are reset, all output, storage and accessory flip-flops are reset, and
that the memory buffer and instruction registers are cleared.

The run flip-flop is also reset by the initialize

line.

When the +5 volt bus voltage ceases to rise, the charge on the capacitor bleeds down rapidly, permitting the
power up sense transistor to turn off. The start (L) line level goes high as a result of the transistor being turned

3-21

TSKH)

TS2(H)

TP(H)

500 n sac

END
CYCLE
PULSE (L)

MEM + EXT
DONE (L)

INITIALIZE

TS2

-d

I/O DONE

PULSE(H)

^^
(TXD + TYD +
TXN +TXF +

TYN +TYF +

SYN+SYF
<

INHIBIT
'

TSI

(JMP-HJMS)

-TSKH)
EXECUTE (H)START
CYCLE
(H)

lOOnsec

T ENABLE
(L)

TP
DELAY

Figure 3-12

TSI, TS2, End Cycle Pulse, and Timing Pulse Generators,
Simplified Logic Diagram

3-22

DELAY
Q1

NOTES;

POWER UP SEN ^^

BUS
DIFF AMPL.

Q3,Q4

\
^

-o|>oll

WAVEFORMS SHOWN IN DETAIL M742 CIRCUIT
SCHEMATIC IN VOLUME I.
2. OR GATE OUTPUT IS ACTIVE UPON RELEASE
OF CONTINUE OR START SWITCH, OR UPON
POWER UP ON +5V BUS.
3. POWER UP AT T0 SHOWN BY DASHED LINES.
1.

SHUT DOWN(L)

200 n sec

w
CO

START CYCLE
CONTROL)

(TO

Figure 3-13

Manual Controls and Power Sense Circuits, Simplified Logic Diagram

off.

This terminates the initialize signaj and releases the capacitor in the input circuit of the Schmltt trigger.

Voltage now rises at the input to the Scimitt trigger.

When this voltage reaches approximately +2.8 volts,

the Sohmitt trigger fires through a pulse jamplifier, producing a 200 ns pulse which sets the run flip-flop (DC set).

In order to shut down the machine syster^ in a predictable manner when PDP-14 power is removed (accidently or

deliberately), a power down sense circuft monitors the +5 volt internal power bus.

constantly compares this bus against a pi|ecision voltage divider reference.

A differential amplifier

When the voltage monitored at the

differential amplifier input voltage divider falls below this voltage, the initialize line is activated which resets

the run flip-flop, all control flip-flops, and all output, storage, and accessory box flip-flops.
j

is available in

Sufficient power

the power supply filters cjnd within individual module +5-volt bus filter capacitors to permit

completion of this operation, even though primary power has been completely removed at the power supply.

3.3.4.2

Manual Controls - When movid to the STOP position momentarily, the STOP/START control push-

button resets the run flip-flop at the trailing edge of the end cycle pulse.

An AND gate loop from the set out-

put to the data input of the run flip-flofj prevents unintentional setting of the run flip-flop when the STOP

button is released.

Once reset, the runj flip-flop can only be set by the Schmitt trigger and external start pulse

generator via the DC set input to the fli^-flop.

NOTE
For M742 prlinted circuit revisions C or higher, the STOP
position of tlhe START/STOP switch resets output, storage,
or accessory box control flip-flops.

only stops PDP-14

activity at the end of the instruction being fetched or ex-

ecuted wheri the button was pushed in systems containing
M742 modules prior to revision C.
Resetting the run flip-flop enables the S|TART and CONTINUE controls by turning on the switch transistor to

provide a ground return for the manual pitches through the transistor emitter-collector circuit.

With the run flip-flop reset, pressing th^ CONTINUE switch momentarily will, upon releasing the button,
activate the Schmitt trigger and externa|l start pulse generator, which sets the run flip-flop.

resumes at the point where it was stopp^J-

The program now

The CONTINUE switch does not produce an initialize signal

With the run flip-flop reset, placing th^ START/STOP switch momentarily in the START position will produce
an initialize signal while the switch is [pressed; then, upon release of the switch, it will activate the Schmitt
trigger and external start pulse generat<^r to set the run flip-flop.

The program is started at ROM address OOOOg,

with all output, storage, and accessory |box flip-flops reset (retentive memory latching relays are not affected).

The run flip-flop can also be reset when( the PDP-14 is operated in external mode. This halt is executed when
7o is decoded by the destination registej- decoder from instruction word bits 9-11 The pulse produced as a result
of this decoder output line and the timirjig pulse during time state 1 is ORed with the initialize line at the DC
.

reset input of the

RUN flip-flop.
3-24

NOTE
JMP, JMS, EEM, LEM, and all TRR instrucHons enable
the destination register.

The halt is performed whenever

this register contains 7q,

Instructions of this nature in

the

ROM program will cause the PDP-14 to "hang" (Stop

running).

The destination register field should never conROM instruction word.

tain 7q in a

3.3.5

Read Only Memory (ROM) Circuits

Four Read Only Memory (ROM) modules may be inserted in the PDP-14 mainframe.
to 1,024,« 12-bit control program instruction words.

Each module contains up

A simplified logic diagram of one ROM module and the

module selection scheme is presented in Figures 11-20 and 3-14.

3.3.5.1

Instruction Word Selection - The maximum number of instruction word addresses in the PDP-14 is

4,096,^.

This is the maximum number that can be contained (in binary) in program counter *1 .

Every ROM

address is obtained from this counter which always holds the complete 12-bit address.

The most significant two bits of the address specify the ROM module containing the instruction word.

These two

ROM module decoder located at mainframe location AB22 (M742 module). ROM modules
must be installed in adjacent locations in the mainframe, or the PDP-14 will hang. If no ROM modules ore
installed, the PDP-14 will execute NOP instructions.

bits are decoded by a

Program Counter bits 2-5 are decoded to select one of 16 matrix transistor rows.

one of 8 matrix transistor columns via eight current switch transistors.
to one of 128 programmable drive wires.

Bits 6-8 are decoded to select

Each transistor in the matrix is connected

Each drive wire is routed through 8 of 12 sense transformers, so the

selection process is completed by decoding the least significant address bits (bits 9-11) to select one set of 12

sense amplifiers corresponding to one instruction word.

3.3.5.2

Timing Circuits - A ROM cycle is initiated by a "mem go" pulse from the pause cycle control circuit

(Figure 3-15).
"^1

The mem go pulse is gated into only the ROM module selected by bits

and

of program counter

Within that module, the mem go triggers the current switch pulse generator which turns on the current

switch transistor selected by bits 6-8 of program counter "^ .
transistors.

This completes the emitter return path to 16 matrix

The base of one of the 16 transistors has already been selected by program counter bits 2-5; the

delay to allow the decoding propagation to take place was produced by the start cycle control circuits before
the mem go pulse was transmitted

In order to prevent drive wire switching transients from being detected by the sense amplifiers, a strobe delay

circuit is also triggered by the mem go pulse.

The trailing edge of the strobe delay triggers the strobe pulse

3-25

NOTES
ROM TRANSFORMER
SENSE WINDINGS ON G923 BOARD
DRIVE WIRES (PROGRAM) ON G922 BOARD
1

(TO TIME STATE

Figure 3-14

Read Only Memory (ROM), Simplified Logic Diagram

CONTROL)

too

TIME (NANOSECONDS)

START CYCLE (A23T2)

CYCLE (B23T2)

MEM GO (A23N1)

READ CURRENT SWITCH

PAUSE

200

300

500

400

—I

"~L

+ 2Vniin.

FERRITE XFMR OUTPUT OV
-0.8V

STROBE DELAY

STROBE PULSE (B13K1)
MEM. D0NE(L)(B13L1)

ROM—»MB

TSl (B23M2)

NOTES
1TEST POINTS ACCESSABLE FROM WIRING SIDE OF MAINFRAME
OBARE SHOWN FOR R0M*1, OTHER WAVE FORMS MUST BE
ASSEMBLY
ROM
OF
MODULE
ON
G923
SERVED

ROM Timing Diagram

Figure 3-15

generator.

The strobe pulse enables the group of 12 sense amplifiers

A "mem done" pulse is triggered by the trailing edge of the strobe
time state 1 , and the trailing edge resets the pause

flip-flop.

selected by bits 9-1 1 of program counter

pulse. The leading edge of this pulse initiates

During the overlapping period, ROM data

gated into the memory buffer register.

3.3.5.3

Data Sense Circuits - There are 96 two-part ferrite sense

are arranged in rows of twelve transformers each,

transformers in each

instruccorresponding to the 12 data bits of a control program

eight sets of sense transformers,
tion word. Each of the 128 drive wires threads
eight words.

ROM module. These

The correct word is obtained by selecting the set

the least significant bits (9-11) of program counter

3-27

so each drive wire actually holds

of sense amplifiers according to the contents

Each bit of the control program data is stored by routine the drive wire through a sense transformer, if the bit
is

a "1 ", or around the transformer,

if the

bit

a zero.

The pattern of one drive wire through or around each

of the 96 sense transformers defines the control program data in eight adjacent

ROM addresses.

Figure 3-16 illustrates the method used to obtain one bit of the selected data word and place it on the bus to

the memory buffer register.

drive wire selected in the transistor matrix passes through the sense trans-

If the

former, a positive-going pulse is induced in the secondary, or sense, winding of the transformer.

The sense

amplifier is not enabled by the strobe pulse, however, until after switching transients caused by placing current

on the selected drive wire have settled.

These transients are quite short compared to the transformer-induced

current in the sense winding.

ROM
MODULE

STROBE
TO II MORE WORD
XXXN SENSE AMPLS
INTERNAL
DATA BUS

FROM 7 MORE

MAIN
FRAME

TO
MEMORY
ENABLE TO REST OF
BUFFER REGISTER

BUFFER
BITn

BIT n (L)

BITn SENSE
AMPL'.S

TWO-PART FERRITE
SENSE TRANSFORMER

ROM DATA BUS
TRANSMITS
DATA IN INVERTED

FORM

WORD XXXN

DATA BITn OF

BITn SENSE AMPL

12- BIT

BUFFER
REGISTER

ROM DATA
BUS BITn(L)

WORD XXXN
STROBE (H)
PAUSE (H)

(BUFFER REGISTER

ENABLE (H))
DRIVE WIRE BRAID MADE UP
OF 128 DRIVE WIRES, EACH
WIRE THREADED THROUGH
OR AROUND 8 SETS OF 12 SENSE
TRANSFORMERS AS REQUIRED
FOR EACH BIT WITHIN 8 ADJACENT ROM ADDRESSES. DRIVE
WIRE IS THREADED THROUGH

FROM UP TO 3 ADDITIONAL ROM MODULES (BITn)

TRANSFORMER FOR "l" BIT, AROUND
TRANSFORMER FOR "O" BIT

Figure 3-16

ROM Data Sense Circuits, Simplified Logic Diagram

3-28

the selected drive wtre passes through the sense transformer, the output of the sense amplifier (shown as a

NAND gate) is active. This active low overrides the seven other bit n sense amplifiers in the seven word sets
which were not selected by bits 9-1 1 of PCI

The bit n storage flip-flop, which was enabled by the leading edge of the pause cycle, is set if the selected
sense amplifier is active.

Once the flip-flop is set, it will remain set until the trailing edge of the pause

cycle; thus the flip-flop stores the bit n data and holds the data on the memory buffer register bus until the data

can stabilize in the bit n flip-flop of the memory buffer register.

Data is in inverted form ("1" = low) on the

memory buffer bus

3.3.6

Input Box Circuits

A block diagram of input box circuits is presented in Figure 11-37. A simplified diagram of input box circuits
and input terminal selection is presented in Figures 11-56 and 3-17.
terminal
is

selected by decoding instruction register bits 4-6.

The input box containing the desired

Within the input box, instruction register bit 8

used to select one of two binary (12 bits 9-11) to eight-line decoders in combination with the box select line.

Each of the eight decoder output wires enables a pair of input detectors.

One of the pair is connected to the

"sample return ^1 " line, and the other is connected to the "sample return *2" line.

The outputs of the un-

selected input detector circuits are held low by their selection lines.

selected terminals is

If either of the

active, the sample return line to which it is attached is permitted to go low by the enabling lines from the

decoder.

Instruction bit 7 is used to select the sample return line carrying data from the terminal of the pair selected by
instruction register bits 8-1 1

The terminal selection process thus far described is simultaneously carried out to select a corresponding Y function
(output, storage, or accessory box terminal or function).
is

Therefore, the final selection of an input box terminal

restricted to those instructions which specify an X (input box) address.

These instructions are TXN, TXF,

andTXD.
There are 32 identical input detector circuits in each input box.

One such circuit is shown in Figure 3-17.

The control input from the external machine system is returned to AC ground through the primary of an isolation
transformer.
is

on.

A neon lamp is also connected across the input to provide a visual indication that the control line

A diode detector, voltage divider, and filter capacitor develop the DC logic levels required within

PDP-14 circuits.

3-29

TO 28

MORE INPUTS

116 VAC

CONTROL

INPUT
TERMINAL

i__|

INPUT
\\v* TERMINAL
SELECTED

^r^ FLOP)
(10

TEST

1
u
o

L (TXD)

BOX PKG.

NOTES'

SELECT

1.^ = EXTERNAL AC RETURN
_L = INTERNAL DC SUPPLY RETURN

(DECODED

FROM IR
BITS 4-6)
IR BITS 9-11