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DEC-12-HR1A-D

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OCR Text

Oigitai Equipment Corporation

Maynard, Massachusetts
I

PDP-12
Maintenance Manual

Volume

|>RINCIPLES OF

fOPERATION

I
f

0
1

DEC- 12- HR A1

PDP-12

MAINTENANCE MANUAL

VOLUME

PRINCIPLES OF OPERATION

DIGITAL

EQUIPMENT

CORPORATION

•

MAYNARD, MASSACHUSETTS

1st Printing

The material in this manual is for informational

purposes and

subject to change without

notice.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts;

DEC

PDP

FLIP CHIP

FOCAL
COMPUTER LAB

DIGITAL
UNIBUS

May 1971

CONTENTS
Page

CHAPTER

CENTRAL PROCESSOR

1.1

Introduction

1.2

PDP-12 Functional Element.s Overview

1.2.1

CP Functional Element.s

M
I-l
I-I

1.2.2

Core Memory and Memory Control

1.2.3

Input/Output

1.3

Data Flow

1-3

1.3.1

Internal Flow

1.3.2

Major Registers

1.3.3

Adder

1-4

1-4
1-4
1-6

1.4

Central Processor Timing Description

1.5

.Major States

1-7

1-9
.6

Console Inputs and Timing

1.6.1

Console Timing (dwg. CST)

.6.2

Cotusole Switch Functions

.6.3

I/O PRESET

.6.4

FILL and EXAM

1.6.5

FILL STEP

1.6.6

STEP EXAM

1.6.7

START 20
START 400
START LS
DO

1.6.8

1.6.9

1.6.10

1-1 3

1-14

1-14
1-15
1
I

-11 .2/
s

1
1

-I1 27
s

1-16
1-16
1-16

1-16
1-16

1.7

Central Processor Timing — Logic Description

1.7.1

T5 RECYCLE

1.7.2

CP Timing and the Memory Read-Write Cycle

fdwgs. CPTP, CPT, CPR

1.8

The Central Processor in Action

Time State 1: CPTTSl H

1-18

1-18
1-18

1.8.2

Get Next Instruction: CPS GNI (dwg. CPS M] 15
K04)

1.9

8-Mode Instructions

1.9.1

FETCH Cycle
DEFER Cycle
EXECUTE Cycle

1.9.2

1-17
1-17

1.8.1

1.9.3

CPS)

1-18
1-27

1-27
1-27

1-29

1.9.4

8-Modc Operate Instructions

1.10

INTERRUPT

1.1

LINC Mode Instructions

1-30
1-31

1-32

1.1 1.1

LINC FETCH

1.1 1.2

Full Address Instructions

1.1 1.3

Index Class Instructions

1-32

1.12

a Class Instructions

1.12.1

SET Instruction 0040 -t

1-34
1-34

1-38
I

+ a

1-38

XSK Instruction (Index and Skip) 0200 -r + a
I

.12.3
.1

2.4

DIS (Display) 0 140 +

-t-

SAM 01 00-t-N (0 < N < 37)

1-39
1-39

CONTENTS (Cont)
Page
1.13

Miscellaneous Instructions

1.14

Shift and Rotate Instructions

1-41

1.15

Skip Instructions

1-42

1.16

Operate Instructions

1-42

1.16.1

lOB

1-42

1.17

1-43

1.18

RSW Instruction
LSW Instruction

1.19

LINCtape Instructions

1-44

1-40

1-43

1.20

TRAP Instructions and INTERRUPT

1-44

1.21

Engineering Drawing Descriptions

1-44

1.21.1

Console Indicators (D-BS-EP12-0-CIN)

1-44

1.21.2

Central Processor Run (D-BS-EPl 2-CPR)

1-44

1.21.3

Central Processor States (D-BS-EPl 2-0-CPS)

1-44

1.21.4

Central Processor Time States (D-BS-EPl 2-0-CPT)

1-45

1.21.5

Central Processor Time Pulses (D-BS-EP 1 2-0-CPTP)

1-45

1.21.6

Console Switch Inputs (D-BS-EPl 2-0-CSI)

1-45

1.21.7

Console Starts (D-BS-EPl 2-0-CST)

1-45

1.21.8

CARRY INSERT (D-BS-EPl 2-CYI)

1-45

1.21.9

Flow and End Shift (D-BS-EPl 2-FLE)

1-46

1.21.10

LINK Logic (D-BS-EPl 2-0-FLK)

1.21.11

I/O and EXT

1-46

MEM Cables (D-BS-EP 12-0-ICB)

1.21.12

Instruction Register (D-BS-EPl 2-0-INR)

1-46

1.21.13

Instructions (D-BS-EPl 2-0-INS)

1.21.14

I/O Input Part A (D-BS-EP 12-IOA)

1-46

1.21.15

I/O Input Part B (D-BS-EPl 2-O-IOB)

1-46
1-47

1.21.16

I/O Control and Timing (D-BS-EPl 2-IOC)

1.21.17

I/O Buffers (D-BS-EP 12-0-100)

1-47

1.21.18

Relay Buffer (D-BS-EPl 2-O-IOR)

1-47

1.21.19

Interprocessor Cables (D-BS-EPl 2-0-IPC)

1.21.20

1.21.22

MEM EXTN AC Inputs (D-BS-EPl 2-0-MEA)
MEM PAGE EXTN Control (D-BS-EPl 2-0-MPG)
MUL Quotient (D-BS-EPl 2-0-MQR)

1-47

1.21.23

Processor Miscellaneous A (D-BS-EPR-O-PMA, PMB)

1-47

1.21.24

Processor Register Bits 0 through 1

1.21.25

1-48

1.21.26

1-48

1.21.27

1-48

1.21.28

1-48

1.21.29

Processor Register Load Control (D-BS-EP 12-0-RCL)

1.21.30

1.21.21

(D-BS-EPl 2-0-PR A through PRF)

MQ Inputs (D-BS-EPl 2-RCS)

1-47
1-47
1-47

1-48

1-49
1-49

1.21.31

SKIP FF and H BIT (D-BS-EPl 2-0-SKH)

1-49

1.21.32

EP 12 SKIPS (D-BS-EPl 2-0-SKL)

1-49

1.21.33

Special Level

1-49

(D-BS-EPl 2-0-SLA)

CONTENTS (Cont)

CHAPTER 2 MEMORY
2.1

Introduction

2.2

Physical Description

2-1

2.3

Read/Write

2-1

2.3.1

Sense Register (MEM)

2-4

2.4

Memory Addressing

2-4

2.5

MCI 2 Memory Extension Control

2-8

2.5.1

Instruction Field Register (IF)

2-8

2.5.2

Data Field Register (DF)

2-8

2.5.3

Instruction Buffer Register (IB)

2-8

2.5.4

Save Field Register (SF)

2-10
2-10

2.5.5

Break Field Register (BF)

2.5.6

Field Selection

2-10

2.5.7

Interrupt Inhibit

2-11

2.6

Memory Block Schematics

2-11

2.6.1

Interprocessor Cables (D-BS-EM 1 2-0-IPCM)

2-1

2.6.2

MCS Sense Amplifiers and Inhibit Drivers (D-BS-EM 12-MCS)

2-11

2.6.3

MCT Memory Control (D-BS-EM 2-0-MCT)
MCX Y-Axis Selection (D-BS-EM 12-0-MCX)
MCY r-Axis Selection (D-BS-EM 2-0-MCY)

2.6.4
2.6.5

2-11

2-13

2.6.7

MEM EXTN Buffer (D-BS-MC12-0-MXB)
MEM EXTN Field (D-BS-MCl 2-0-MXF)

2.6.8

MXI Inhibit Drivers (D-BS-MC12-0-MXI)

2.6.9

MEM EXTN Register (D-BS-MC 2-0-MXR)
MXX Y-Axis Selection (D-BS-MC 12-0-MXX)
MXY r-Axis Selection (D-BS-MC 12-0-MXY)

2.6.6

2.6.10
2.6.11

2-12

2-13

2-14

2-14
'

CHAPTERS

2-14
2-14
2-14

I/O BUS

3.1

Introduction

3.2

Block Diagram Descriptions

3-1

3.2.1

Program-Controlled Transfers

3-1

3.2.2

Data Break Transfers

3-3

3.3

Flow Diagram Descriptions

3-5

3-1

3.3.1

Direct Program Transfer (lOT)

3-6

3.3.2

Program Interrupt Transfer (INTERRUPT)

3-6

3.3.3

Data Break Transfers (BREAK)

3-6

3.4

Block Schematic Descriptions

3-7

3.4.1

I/O and External Memory Cables (D-BS-EPl 2-0-1 CB)

3-7

3.4.2

I/O Inputs Part A (D-BS-EPl 2-O-IOA)

3-7

3.4.3

I/O Inputs Part B (D-BS-EPl 2-O-IOB)

3-7

3.4.4

I/O Control and Timing (D-BS-EP 1 2-O-IOC)

3-7

3.4.5

I/O Output Buffers (D-BS-EPl 2-0-100)

3-8

CONTENTS (Cont)
Page

CHAPTER 4 TELETYPE
4-1

4.1

Introduction

4.2

Teletype Control

4-1

4.3

Receiver (TTI)

4-1

4.4

Transmitter (TTO)

4-2

4.5

Detailed Logic Description

4-2

4.5.1

Read Cycle

4-2

4.5.2

Print/Punch Cycle

4-4

CHAPTERS LINC DEVICES
5.1

Introduction

5-1

5.2

Tape Control

5-1

5.3

A/D Control

5-1

5.4

CP Flow Diagram Description

5-3

5.5

Sense Line Control

5-4

5.6

Relay Control

5-5

5.7

Display Control

5-7

5.7.1

Timing

5-9

5.7.2

Character Generation

5-10

5.7.3

Addressing

5-10

5.7.4

Data Handling

5-15

5.8

PDP-12 Speaker

5-15

CHAPTER 6 LINCTAPE CONTROL SYSTEM
6.1

Introduction

6-1

6.2

General Description

6-1

6.3

Referenced Documents

6-3

6.4

Specifications

6-3

6.5

LINCtape Format

6-4

6.5.1

Track Arrangement

6-4

6.5.2

Word Assembly and Disassembly

6-4

6.5.3

Overall LINCtape Format

6-6

6.5.4

Non-Standard LINCtape

6-7

6.5.5

Detailed LINCtape Block Format

6-7

6.5.6

LINCtape Standard Format Summary

6-8

Block Diagram Discussion

6-1

6.6.1

Extended Operations

6-12

6.6.2

Extended Addressing

6-14

6.6.3

Basic Read/Write Discussion

6-14

6.6.4

Tape Processor Register Description

6-17

6.7

System Drawing Discussio

6-20

6.7.1

Tape Processor Major State Flow (TCI 2-0-1 0)

6-20

6.7.2

Timing Diagram Discussions

6-21

6.6

CONTENTS (Cont)
Page
6.8

Block Schematic Discussion

6-26

6.8.1

Tape Control States and Instruction (TC12-0-LCS)

6-26

6.8.2

Tape Extended Operations (TC 2-0-LCS)

6-27

6.8.3

Tape Extended Fields (TCI 2-0-LCXF)

6-27

6.8.4

Tape Group Counter (TCI 2-0-LGP)

6-28

6.8.5

Tape Instructions (TCI 2-0-LIN)

6-28

6.8.6

Interprocessor Signals (TC 2-0-LIP)

6-28

6.8.7

Tape Unit and Motion (TC12-0-LMU)

6-29

6.8.8

Tape Register Enable Control (TC12-0-LRE)

6-29

6-30

6.8.9

Tape Register Load Control (TCI 2-0-LRL)

6.8.10

Transport Control (TCI 2-0-LTC)

6-30

6.8.11

Tape Delays (TCI 2-0-LTD)

6-30

6.8.12

Tape Maintenance Signals (TC12-0-LTM)

6-31

6.8.13

Tape Reader-Writers (TC12-0-LTR)

6-31

6.8.14

LINCtape Register Bus (TCI 2-0-LTRA-F)

6-32

6.8.15

Tape States (TC12-0-LTS)

6-32

6.8.16

Tape Time Pulses (TC 2-0-LTT)

6-33

6.8.17

Tape Mark Window (TC12-0-LWN)

6-33

CHAPTER 7 PREWIRED OPTIONS
7.1

Introduction

7.2
7.2.1

AG 2 and AM 2 Options
AG 12 Preamplifier

7-2

7-1
7-1

7.2.2

AM 12 Expanded Multiplexer

7-2

7.2.3

Logic Description

7-2

7.3

DP 2-A Teletype and DP 2-B Asynchronous Modem

7-2

7.3.1

Component Description

7-3

7.3.2

Programming

7-4

7.3.3

Cable Connections — DPI 2-B

7-5

7.3.4

Logic Description

7-5

7.4

KE12 Extended Arithmetic Element

7-5

7.4.1

Timing and Control Logic

7.4.2

Multiplier Quotient Register (MQ)

7-6

7.4.3

Step Counter Register (SC)

7-7

7.4.4

EAE Instructions

7-7

7.4.5

Load Group

7-7
7-8

7.4.6

EAE Operate Instructions

7.5

KPl 2 Power Failure Restart

7-1 1

7.5.1

Programming

7-14

7.6

KTl 2 Time-Sharing Option

7-14

7.6.1

TSS/Monitor Program

7-16

7.6.2

KTl

7-16

7.6.3

General Logic Description

7-17

7.6.4

Detailed Logic Description

7-18

Program Instructions

vii

CONTENTS (Cont)
Page

7.7.1

KW 2-A Real Time Interface and KW12-B, -C Simple Clocks
KW 2-A — Real-Time Interface

7.7.2

KW12-B and KW12-C Simple Clocks

7-24

7.7.3

Block Diagram Discussions

7-25

7.8

TC12-F — 8 Tape Control

7-28

7.8.1

Logic Description (TCI 2-F-LTP8)

7-28

7.8.2

Instructions

7-28

7.9

XYl 2 Incremental Plotter Control

7-29

7.9.1

Logic Description

7-30

7.9.2

Logic Operation

7-30

7.9.3

XY 2 Instructions

7-31

7.7

7-19

ILLUSTRATIONS
Figure No.

Title

Art No.

Page
1-2

1-1

Central Processor Overview

12-0233

1-2

PDP-12 Data Flow

12-0085

1-5

1-3

CP Adder, Simplified Logic Diagram

12-0234

1-6
1-7

1-4

CP Timing Cycle; Time Pulses and Time States

12-0236

1-5

CP Timing and Run

12-0062

1-8

1-6

CP, Major State Block Diagram

2-0060

1-10

1-7

Console Switch Inputs to the PC

12-0222

1-14

1-8

8-Mode Address Modification

1-9

LINC-Mode Address Modification

12-0072

1-10

lOT Timing

12-0246

2-1

Elements of PDP-12 Core Memory

1 2-0249

2-2

PDP-12 Core Memory Stack

2-3

Simple Core Memory Plane

81-0046

2-3

2-4

Page Addressing in 8 Mode

12-0247

2-5

Simplified Memory Address Selector and Read/Write

2-0048

1-28
'

1-33

2-3

Current Control

81-0061

2-6

CP and Memory Timing Relationships

12-0235

2-7

Extended Memory Block Diagram

81-0089

2-9

2-8

Representative Inhibit Current Waveforms

81-0020

2-12

2-9

Representative Sense Amplifier Waveforms

81-0033

2-13

3-1

Program-Controlled I/O Bus Block Diagram

12-0245

3-2

Data Break I/O Bus Block Diagram

12-0237

3-4

4-1

Teletype Control Block Diagram

12-0075

4-2

Teletype Read Cycle Timing Diagram

12-0197

4-3

Print/Punch Cycle Timing Diagram

81-0050

4-5

5-1

A/D Control General Block Diagram

12-0038

5-2

A/D Control Block Diagram

12-0037

5-3

Sense Line Control Clock Program

12-0028

5-5

5-4

Sense Line Control Functional Block Diagram

12-0027

5-6

5-5

Relay Control Functional Block Diagram

12-0025

5-6

viii

ILLUSTRATIONS (Cont)
Figure No.

Title

Art No.

Page

5-6

Display Control General Block Diagram

12-0036

5-8

5-7

Display Control Block Diagram

12-0031

5-8
5-1

5-8

Bit Positions of DSC Instruction

12-0035

5-9

Display Point Location

12-0032

5-11

5-10

Display Addressing Block Diagram

12-0034

5-12

5-1

Display, Letter A

12-0033

5-13

5-12

Data Handling Block Diagram

12-0029

5-16

5-13

Speaker and Control

12-0241

5-17

6-1

LINCtape System Configuration

12-0221

6-2
6-3

TU55 LINCtape Transport
TU56 Tape Transport

6-2

6-4

Track Allocation Showing Redundantly Paired Tracks

6-5

6-1

6-2

6-5

Structure of 12-Bit Data Word (4 Tape Lines)

12-0223

6-5

6-6

Standard LINCtape Format

12-0224

6-6

6-7

LINCtape Reel to Memory Comparison

12-0225

6-7

6-8

Standard LINCtape Detailed Format

12-0226

6-7

6-9/6-10

6-9

LINCtape Overall Block Diagram

12-0227

6-10

Read/Write Buffer Interface Diagram

12-0228

6-1

Extended Operations Buffer Bit Assignments

6-12

Read/Write Simplified Logic

12-0229

6-15

6-13

Read/Write Logic and Waveforms

12-0230

6-16
6-18

^12
6-13

6-14

Reading A Block Mark

12-0231

6-15

PDP-1 2 LINCtape Flow Diagram

12-0006

6-19

7-1

Multiplexer Selection

12-0232

7-3

7-2

Simplified Block Diagram, KEl 2 EAE

81-0095

7-7

7-3

12-0248

7-12

7-4

KE 2 EAE D VI Flow Chart
KE 2 EAE DVI Algorithm

7-5

Typical Power Failure Program Service Routine

2-0039

7-15

12-0196

7-15

7-13

7-6

Automatic Restart Program Events

7-7

KT 12 Simplified Block Diagram

12-0210

7-18

7-8

KW12-A Real Time Interface Functional Relationship

12-0238

7-20

7-9

KW 2-A Organization

12-01 10

7-21

7-10

Simplified Input Synchronizer Logic Diagram

12-0194

7-22

7-1 1

KW 2-A Timing Diagram
KW 2-B and KWl 2-C Simple Clocks, PDP-1 2 System
1

12-0205

7-23

12-0242

7-25

81-005

7-30

7-12

Functional Relationships
7-13

XY12 Block Diagram

TABLES
Table No.

Title

Page

1-1

Major Registers

1-4

1-2

Time States and Time Pulses

1-9

1-3

Summary of Operations

1-1

1/1-12

TABLES (Cont)
Table No.

Title

Page

1-4

Functional Logic Description, START LSW

1-5

Functional Logic Description, ADA 1 12

1-21

2-1

Field Select Codes

2-10

4-1

Teletype Instruction Description

4-6

5-1

Inversion Effects

5-4

5-2

Pattern Words for Character Display

5-14

6-1

DEC Documents

6-3

6-2

Summary of Equipment Specifications for the LINCtape Control

6-3

LINCtape Format Summary

6-8

6-4

Mark Track and Channel Assignment

6-11

7-1

Prewired Options

7-1

7-2

Module Requirement for DP12-A and DP12-B

7-4

7-3

DP 12 Instruction Mnemonics

7-4

DP12-B Cable Connector Wiring

7-6

7-5

KT12 Program Instructions

7-16

7-6

KT 12 Modules

7-17

7-7

KW12-A Clock Time Base Ranges

7-19

7-8

XY12 Incremental Plotter Specifications

7-29

7-9

XY 2 Instructions

7-31

1-19

CHAPTER 1
CENTRAL PROCESSOR

1.1

INTRODUCTION

Tlie PDP-1 2 (Programmed Data Processor-1 2) is a versatile digital computer that makes use of two

distinct

operating modes within its single Central Processor (CP); each operating mode has its own complete instruction
set.

With this feature, the PDP-1 2 is both a laboratory-oriented machine with built-in facilities for I/O, auxiliary

storage, and control and sensing of external equipment; and a general-purpose computer with flexible
bility, to which numerous peripheral devices

word length of

2 bits.

I/O capa-

may be easily attached. The logic is fully parallel, using a basic

The processor cycle time is

.6 jus ±20 percent; most instructions require from one to

three cycles for execution.

NOTE
In the following discussions of the CP, System Drawings Volume
III of this manual is referenced often; the reader should refer to

the system drawings as they are referenced.

The system drawing

numbers are arranged in alphabetical order by a three-letter de-

The complete system drawing numbers for the logic
The system
drawing numbers always contain D-BS-EP12-0; thus, only the
signation.

are D-BS-EP12-0-CIN through D-BS-EP12-0-SLA.

last three letters are used to reference system drawings in the text.

1.2

PDP-1 2 FUNCTIONAL ELEMENTS OVERVIEW

Tlie functional elements of the PDP-1 2 are grouped in three categories (see Figure 1-1):

ory, and Input/Output. Principal data and control paths are shown in the figure.

Central Processor, Mem-

Related functions are grouped

within boxes, accompanied by the three-letter reference designation to the appropriate system drawing
in Volume III.

number

For example: PDP-1 2 operations are initiated from the console switches, the circuit elements of

which are shown in block schematic CSI. Inputs from the switches can be sent directly to the CP shift
gates
(dwgs. PRA through PRF) or to the console timing logic (dwg. CST). This reference system relates every
element
in this figure to one or more of the block schematics.

CP Functional Elements

1.2.1

Functional elements of the CP are grouped as follows;
a.

Console Switches and Indicators

Console and CP Timing Logic

Instruction Decoding and Register Control

Active Registers and Processor Register Bus

I/O Control and Buffers and Teletype

® Teletype

® Circuits

the registered trademark of Teletype Corporation, Skokie, Illinois.

ric
ACTIVE REGISTER S REGISTER BUS LOGIC

PRA
PRB
PRC
PRD
PRE

s
2

INR
INS

MODIFICATION
CONTROL

SKH
SKL

FLE
FLK

SLA

PRF
PMA
PMB

SHIFT GATES

INSTRUCTION
DECODING

RCA
RCB
RCC
RCD

RCL
RCS
CYI

MO
MOR
SENSE
REGISTER
(

TIMING

CPR
CPS
CPT
CPTP

MEM

)

MEMORY
CONTROL

CENTRAL
PROCESSOR

Hmip

mgm
L

CORE MEMORY

MCS
MCT
MCX
MCY

rouiTf

PROCESSOR REGISTER BUS

CONSOLE
INDICATORS
CIN

CONTROL
TIMING
CST

CONSOLE
SWITCHES
CSI

EXTERNAL
DEVICES
BUFFERS

INPUT
BUFFERS

100

lOA.IOB

OUTPUT

I/O

CONTROL
IOC

TELETYPE
RECEIVER

TELETYPE
TRANSMITTER
TTO

TTI

Figure 1-1

teletypTI

Central Processor Overview

1-2

Console Switches and Indicators

These switches on the console front panel

Provide data inputs to the processsor register bus logic, via the register

Control inputs that start the machine by initiating the console manual timing

gates and the shift gates
chain, which in

turn starts the CP timing cycle.

The console indicators usually represent the contents of all active registers and
flip-flops in the PDP-12.

the states of most of the control
These indicators can provide valuable assistance in troubleshooting.

Console and CP Timing Logic - Console and CP timing logic control the sequence
the console switches initiate a sequence of manual-function time states

of CP operations. Signals from

and pulses. The final console time pulse

starts CP timing, which continues until the processor is

stopped. CP timing controls the start of the memory
Read-Write cycle and synchronizes the transmission of data between the
I/O buffers and the CP.

Instruction Decoding and Register Control - The contents of the
signal levels and set flip-flops that ultimately (through the

instruction register (IR) are used to establish

various elements of the register control circuits) deter-

mine the paths of data into, through, and out of the active registers and the

processor register bus logic.

Active Registers and Processor Register Bus - These circuits are the vital

components of the PDP-12 Central
The active registers (AC, PC, MA, IR, and MB) determine the locations in which the
program and data
are stored in memory and store the data. Data can be sent from
these registers to various other elements of the
Processor.

system (e.g„ the I/O buffers or memory control), but data can enter the active
sor register bus. This facility is illustrated in Figure I-l

registers only through the proces-

Information paths go from the active registers into the

From the shift gates, data enters any of the active

registers via the processor register bus.

I/O Control and Buffers; Teletype Logic - Information leaving or entering

the I/O Bus must pass through the
I/O buffers. The I/O Control synchronizes the transmission of data
between the buffers and the processor
register bus, under the control of CP timing.

Data that pass between the Teletype and the CP have a separate path and
receiver.

control:

the Teletype transmitter and

Incoming data pass through the Teletype receiver to the internal I/O Bus; outgoing

data move from the

AC, through the Teletype transmitter, directly to the device.

1.2.2

Core Memory and Memory Control

The transmission of data between core memory and the CP is controlled by the
cycle is initiated by CP timing; information is strobed from

memory Read-Write cycle. This
memory into a buffer (dwg. MEM) located in the

memory control and passes to the register bus logic.

Later in the Read-Write cycle, the contents of the CP memory buffer condition the inhibit drivers of the memory control to
determine the pattern that is written back into
the cores.

1.2.3

Input/Output

I/O devices are divided into two main categories: those that are
connected to the CP through the I/O Bus and
those that communicate directly with the CP.

The latter group includes the LINCtape, display, A/D converters,
and relays. Each of these devices has its own control and its own distinct
data
paths.

Two types of devices are connected to the I/O Bus:
a.

The pre-wired bus options, including real-time clocks, incremental plotter, extended
(EAE), po wer fail restart, and additional Teletypes of Dataphones.®

©Dataphone is a registered trademark of the Bell Systems.

1-3

arithmetic element

Other devices that are not pre-wired options, which can be added using the BA 12 Peripheral Expander;
these devices include the line printer, high-speed paper-tape reader and punch, card reader, etc.

1.3

DATA FLOW

1.3.1

Internal Flow

The principal paths of data flow are shown in Figure 1-2. At the center of this flow is the cyclic path from the
active registers (SOURCE) through the enable gates, adders, and shifters onto the processor register bus

(ROUTE), and back to the active registers (DESTINATION).

Logical and arithmetic operations, shifts, and in-

ternal data transfers are all performed as the data are circulated.

An instruction is fetched from core memory and placed in the IR. The contents of the IR are interpreted, using
binary-to-octal decoders (dwg. INS) and other logic (dwg. SLA, SKL, FLE), to provide signals that determine the

events that are to occur as data move through the processor logic.

The paths from the active registers or external

sources to the enable gates are established by the register control logic (dwg. RCA through RCD), according to

the signals that result from the decoded instruction.

The enable gates (dwgs. PMA, PMB, PRA through PRF),

which are multiple-input NAND/NOR gates, combine the enabled inputs and send the outputs to the adders,
where they are combined with the Carry Insert input (dwg. CT/) to provide both a Sum Output and a Carry

Output to the next higher-order adder.
cess.

A simplified schematic of the adder (see Figure 1-3) illustrates this pro-

The sum output is routed to the Shift gates (dwgs. PRA through PRF), where, depending on signals from

the shift control logic (dwgs. RCS, FLE), the output is passed through directly or shifted right or left.

The

The key to understanding the internal flow is: information can enter an active register (AC, PC, MA, MB, and
IR) only through the register bus. Outputs from these registers may go anywhere:
MQ, etc. The memory field registers and buffers, however, are treated differently.

I/O buffers. Teletype, memory,

NOTE
The MQ is not part of the register bus logic; information enters
it only from the AC.
1.3.2

Major Registers

The major registers are listed and described in Table 1-1
Table 1-1

Major Registers
Description

Accumulator (AC)

2 Bits

This register contains data being operated upon.

Its contents can

be shifted or rotated right or left; incremented, cleared, or complemented; stored in memory or added to the contents of a memory register; and logically or arithmetically compared with the
contents of any memory register. The AC holds the sum after an
addition and part of the product after a multiplication.
is also

The AC

involved in the transfer of data to and from various other

registers outside the CP.

The Link is an extension of the AC. When a Carry occurs out of
ACOO during a 2’s complement addition, the Link is complemented.
It may be set or cleared independently of the AC under 8-Mode

Link (L) 1 Bit

control and may or may not be included in shifting and rotating

operations performed on the contents of the AC.

Program Counter (PC)

2 Bits

This register contains the address of the next instruction to be

executed within the memory field selected by the Instruction

1-4

aPUNCH

TPTR

MEMORY

cqRE

•"
WRITE

\/
INHIBIT

DRIVERS

1-5

Table 1-1 (Cont)
Major Registers
Description

Major Register

Program Counter (PC) 12 Bits (Cont)

Field Register.

In 8 Mode, the PC is used as a 12-bit counter;

in LINC Mode, it is used as a 10-bit counter.

This register contains the complete binary code of the instruc-

Instruction Register (IR) 12 Bits

tion being executed.

Memory Address Register (MA) 12 Bits

This register contains the address for memory references. Whenever a core memory location is being accessed, both for reading

and for writing, the MA contains the address of that location.
Information passing between memory and other registers in the

Memory Buffer (MB) 12 Bits

PDP-12 must go through the memory buffer register, whether the
transfer involves the CP, an external I/O device, or another mem-

ory register. The instruction register (IR) is the only register that
can be loaded directly from memory.

Mode Status Register

This register indicates the current operating mode (LINC or 8) of

Bit

the CP.

This register selects the memory field containing the executable

Instruction Field Register (IF) 5 Bits

program. In the LINC Mode, it is used to designate one of up to
thirty-two 1024-word segments. In the 8 Mode, the three high-

order bits of the IF are used to designate one field (of up to eight

4096-word fields).
This register selects the memory field containing data to be in-

Data Field Register (DF) 5 Bits

directly accessed by the memory reference instructions of a pro-

gram. The fields are specified in each mode in the same way that
the IF specifies the instruction field.

1.3.3

Adder

The arithmetic unit of the CP is the adder. The CP contains 2 adders (see prints PRA through PRF).
1

simplified schematic of the adder is shown in Figure 1-3.

A
1

III—

ADDER TRUTH TABLE
B
Z
C IN
1

0
0
0
0

0
0

SUM

0
0

TEST

0
1

COUT
0
0
0

0
0

— NO QUALIFIED GATE

—A

— ——

__ c

Figure 1-3

CP Adder, Simplified Logic Diagram

1-6

CARRY
TEST

As shown in the truth table, when both A and B are logical Os (+3V in this case), a logical
If either input

0 is the output at 2.

A or B is a logical

(OV in this case), a logical one is the output at 2. If both inputs A and B
1
contain a logical one, the output is 0 and a Carry Out is generated. If Input
A or B is true, and Carr/ Insert is
true, then

1.4

2=0 and C Out =

Input A and B and C results in 2 =

and Carry Out = 1.

CENTRAL PROCESSOR TIMING DESCRIPTION

CP timing determines the order of events in the PDP-1 2. CP timing comprises a series of signal levels

designated
time states, each of which is terminated by a time pulse. During a time state,
operating conditions are established
the register gate inputs are enabled, and data are operated on in the adders

and shifters. The time pulse causes

data at the shifter outputs to be loaded into the specified active registers.

Time pulses also synchronize CP op-

erations with memory operations, as well as with I/O control.

The duration of the CP timing cycle is 1.6 /as ± 20 percent. The cycle is divided into five time
states ranging from
250 ns to 520 ns in duration. The time pulses, which are approximately 100 ns long, simultaneously
terminate
one time state and initiate the next. Time states are triggered by leading edges of time
pulses; thus, the duration
of the pulse does not affect the length of the cycle.

The relation of time pulses to time states is shown in Figure 1-4. Information is processed through
the register
bus during every time state, data can circulate through this logic, into and out of the active
times in a single cycle.

registers, up to five

The end of one cycle signals the start of the next.

MFTP2

500 ns

350ns

300 ns

TS2

TS3

TS4

350 ns

TS1

LTP5
TP5

—

TP4|

L
9

J
1.0

1.1

1.2

SET CYCLE

done
T5 RECYCLE

TP5D

TP5S

’

^—o A

1.3

L
14

1.5

1.6

1.7

18
1

Figure 1-4

2'0236

CP Timing Cycle: Time Pulses and Time States

The first CP timing cycle is initiated by the conditions established at the end of the Manual
Chain. The cycle begins with Time Pulse 1 (TPl); the first time state is TS2.
to TP5, then to TSl, which is the beginning of another cycle.

Function Timing

The sequence proceeds from TS2

For certain LINC instructions and for the PDP-8

EAE operations, a special pulse, TP5D, causes TS5 to recycle until the operation is complete.
Both the console and CP timing chains are propagated by a series of pulses taken from delay
states are established by cross-coupled

line taps.

The time

NOR gates used as RS flip-flops. The sequence and duration of pulses and

levels in both chains are shown in Figure 1-5.

Table 1-2 shows the function of each time state and time pulse used by the CP.

1-7

(<,

SWITCH BUMPS. CONNECT, BOUNCE, ETC

ST FLTR

500ms, KEY RELEASED

INTEGRATING FILTER NETWORK RENDERS lOOms DELAY (IN-

OUTPUT
ST OUTPUT

•OUT)

CST MFSTO L

THIS LEVEL

CST MFTSO H-

Zjit

|~|

CST MFTP 0 H
CST MFTS IH

%
-

iiii_F=L_o

_Q^

CST MFTP IH

TRUE WHILE A SWITCH

DELAY = CST MFTP

2tia

ACTIVATED

SIDE OF FF)

DELAY= CST MFTP 2H
(I

SIDE OF FF)

CST MFTS 2H
|~|

CSTMFP2H

STANDARD PULSE 150ns

SOns

(MFTP2- 10 PRESET SET RUNn
+ (AUTO RESTART)
)

RUN

* ST OUTPUT-(RUN= 0 + NO PAUSE = 0)- IN PROGRESS = KEY TO PRESET
XK 10 PRESET OCCURS WHEN POWER IS APPLIED AND WILL SET CYCLE DONE, MEM IDLE, EN MEM AND TSI
XXX CYCLE TIME INCLUDES PROPAGATION DELAY
)

I-

(

Figure 1-5

CP Timing and Run

Table 1-2

Time States and Time Pulses

Time State/Pulse

Function

TSl

Readies CP for next cycle and restart timing or start timing

TPl

Finds starting location of program or instruction; generates

START MEM if EN MEM is set
TS2

Accesses memory for information

TP2

Completes memory access and/or finishes finding address

TS3

Clears previous commands and/or determines if indirect or
direct addressing is used

Places memory information into buffer to be acted upon

TP3

Decodes command and/or enables register for functions to be

TS4

performed

TP4

Performs operations

TS5

Cleans up and finishes instruction or enters extra cycles if instruction not complete

TP5S

Checks if any outside peripheral is ready to send or receive
information

TP5D

Starts the TPS sequence of pulses when T5

RECYCLE is set

Checks for T5 RECYCLE

OFF PAUSE

Does another cycle or cleans house to start new instruction

TPS

and performs operations
Sets up memory for outside peripheral if ready to send or re-

LTP5

ceive information

T5 RECYCLE

1.5

Recycles in TS5 to complete long commands

MAJOR STATES

Most PDP-12 instructions require more than one cycle to accomplish decoding, access to memory for data, and
execution of the specified operations. In addition, special operations are required when a Program Interrupt or
a Data Break is requested.

To accommodate these different kinds of events, nine different timing-cycle opera-

tional sequences have been established, designated Major States.

These Major States and associated operations

are tabulated in Table 1-3, which is a condensation of the information presented on the Major State Flow Dia-

grams (PDP-1 2-0-10 through 23).

shown in Figure 1-6.

A block diagram of the Major States and principal distinguishing features is

It can be seen

from Table 1-3 and Figure 1-6 that certain Events are associated with specific

time pulses, regardless of the Major States in which they occur. For example, the

loaded only at TPl. The

MB is normally loaded at TP3. The memory Read-Write cycle is started at TPl (except when using KEY DO)
whenever memory access is required, and the MEMORY STROBE triggers TP2 and reads the contents of the
addressed register into MEM.

1-9

Figure 1-6

CP, Major State Block Diagram

1-10

Table 1-3

Summary of Operations

immmm
LINC

from IF & PC

from MB

or IR

LINC

Current

Address

Break

Tape Break

from TAPE ADD

from PC, MB

from MB

or IR (XSK)

from IR & IF

from DATA

CDSC & SET)

from MB

ADD

(3-cycle)

Save Fields,

Increment

Clear IF &DF*

or DATA

ADD

LINC
Set MA,

Clear

INTEN,

Clear M A,

TRAP

INTEN

*at TP5D

TPID

Clear Cycle Done

Load PC:

TS2
(DSC) Set

Clear IR

from PC & SKIP

from MEM

Clear IR

from MEM

from MEM or

Vertical size

TP2

Strobe Mem.

from MEM or LSW

from MEM

from MEM, AC, or PC

(DSC) from MEM,

and RSW

incremented

or RSW

Set Flow

Load IR from MEM or

LSW.

autoindex

MEM

AC
Set INT PAUSE

Half-word Load
Clear SKIP & H

TAPE BUF

CARRY ->
WC OVERFLOW

Carry -^SKIP

Carry

DATA IN

MB
Set PAUSE or

INT PAUSE
(IMP) MB & MA

(IMP)

->PC

MB~^PC

(SAM, Rotates)
Set T5 RE-

(OPR) Set SKIP,

CYCLE

Clear AC, L

MBO-^H

MB->AC
AC i/2 -word shifts

MB or AC

Restart Display

MA ->PC

Start Tape

IMP Set I'ield

Comp. AC, L

(MUL)AC->MQ

Clear INT

Rotate AC. L

Set RECTCLE SYNC

INHIBIT

MA ->PC

Set FLO. lOT PAUSE

(lOT) set

lOT PAUSE

MSC class op-

Rotate AC, L

orations

RSW

->•

OFF
PAUSE

Set T5 RECYCLE

(MUL)

Set SKIPCLR

AC 'A-word .shifts

MB ->IB. DF

Complement

(DSC) Load

co-ordinate

(DSC) Set Intensity

Set SKIP.

(lOT) I OP

INT INHIBIT

event times

(JMP)O-^PC

1,2,4

Wait for word

buffers

Last Word;

& Vert Buffers

La.st Checksum ->•

(SAM) Recycle
till

ready;

Clear lOT PAUSE

(DIS) Set display

then AD

AC
(Rotate) AC &

(JMP) IR & IF -^PC

MO shifts
To FETCH, DEFER, EXECUTE, or

INTERRUPT

To FETCH

control buffers

To I-XECUTE

To FETCH

(lOT) lOP events

(MUL) Recycle till done [TP5D]

EXECUTE

To FETCH. EXEC 2. or TAPE BREAK

To DSC control

LTP5: Set

flow

(DSC done, SET)

To FETCH

Clear INT PAUSE

Ext. Address

To FETCH

ToCA

BREAK

orTBRK

To FETCH

The names of the Major States describe the nature of the events which occur during

The Major States

the cycle.

are as follows:

FETCH — A new instruction is obtained from the core memory specified by the contents of the MA,
and loaded into the IR, where it is decoded. (The instruction is also loaded into
the
at the same
time.) If no further memory reference is required, the specified
operations are carried out during T4

ROTATE

and T5. LINC
class EAE, MUL, and
instructions (except when in Fast-Sample mode)
recycle in T5 until the required operations are completed.

SAM

DEFER - Whenever an indirect memory reference is required, the DEFER state is entered immediately
after FETCH.

Data are read from the addressed memory locations into the MB, where the

available as an operand for an address in the next cycle (which is

data becomes

EXECUTE for all instructions except

8-Mode JMP). In the latter case, the new address is placed in the PC, and the next
cycle is

FETCH.

EXECUTE — The MA is set up, and data from memory are accessed. Operations are carried out during
time states 3, 4, and 5. For EAE instructions MUL, SAM, and ROTATE, the
processor recycles in T5
until the operation is complete.

EXEC 2 — This state is used in LINC Mode only, to provide the additional memory reference required
by SET and DSC instruction. For DSC, the display buffers are loaded during T5, and
the display control sequence is initiated.

INTERRUPT - If the Program Interrupt is enabled and an Interrupt Request occurs, the INTERRUPT
The memory field registers are saved; the
is set to the proper Interrupt
Address; and the PC is loaded from the MA. Refer to Chapter 3 for a detailed
discussion of the
state is entered at TPl.

INTERRUPT state.
WORD COUNT - This is the first cycle of a three-cycle Data Break. The contents of the Word
register (number of words being transferred) are incremented.

Count

Refer to Chapter 3 for detailed descrip-

tion.

CURRENT ADDRESS - This is the second cycle of a three-cycle Data Break. The contents of the
Current Address register (address of the data being transferred) are incremented.
Refer to Chapter 3
for further explanation.

BREAK - This is the last cycle of a three-cycle Data Break, and it is the only cycle of a single-cycle
Break. In either case, the data are transferred between memory and the
I/O Bus

during the BREAK

state.

TAPE BREAK ~ This is a Data Break cycle used only by the LINCtape processor for transferring data
between memory and the LINCtape buffer. Refer to Chapter 6.

1.6

CONSOLE INPUTS AND TIMING

The PDP- 2 console switches provide data and control inputs for starting and operating the
CP. Figure 1-7 shows
the principal information paths from the console to the CP. Control inputs
(STARTs, EXAMs, FILLs, DO,
1

CONT, I/O PRESET) start the console timing chain to perform the operations required. The stop switches
the internal operations to halt under various conditions.
for program branching.

The LEFT and RIGHT SWITCHES are data inputs, sensed by the program or used in the

course of a DO operation.
registers.

cause

The SENSE switches are inputs to the skip logic (SKL)

The INST FIELD switches and high-order LEFT SWITCHES set the memory field

The MODE switch determines the initial operating mode (LINC or 8) to be established when

I/O

PRESET is pressed.
Whenever a Console Control switch is actuated (dwg. GST), the console timing chain is started.
sists of three time states, each terminated by a time pulse.

begin.

1-13

This chain con-

The last time pulse may cause a CP timing cycle to

1.6.1

Console Timing (dwg. CST)

The manual function timing chain is initiated whenever a control switch (START, FILL, EXAM, CONT, DO, or
I/O PRESET) is pressed. The entire circuit is found on a single double-width M700 Module.

The switch output is smoothed by an integrating filter, for input to a Schmitt trigger. The trigger output, a
negative-going pulse, starts the timing chain, provided that the

RUN flip-flop (dwg. CPR) is clear and that a

LINCtape operation is not in progress. The trigger output generates METSO L, which remains low until the
switch is released.

At the same time that METSO L is established, MFTPO H occurs and inaugurates a series of delays, each about

MFTPO H sets the MFTSl flip-flop; 2 /xs later, and MFTPl H sets MFTP2 to terminate the previous time state by clearing MFTSl. Finally, MFTP2 H clears MFTS2. For all control switches except I/O
PRESET, MFTP2 H initiates the CP timing cycle; thus, CST METP2 L direct-sets the RUN flip-flop (dwg. CPR).
The pulse also generates CPTP SET CYCLE DONE L, which sets the CYCLE DONE flip-flop (dwg. CPT).
2 jus in length.

1.6.2 Console Switch Functions

The manual function timing chain is initiated by these switches: I/O PRESET, FILL, EXAM, FILL STEP, STEP

EXAM, START 20, START 400, START LS, DO and CONT. Brief descriptions of their operations are given
here; the START LS Switch is described in detail in Section .8.
1

Except for CONT, all the control switches cause the SKIP, H, and Major State flip-flops to be cleared at MFTPO.
Except for I/O PRESET, all these switches inaugurate at least one cycle of CP timing.

TO MEMORY
CONTROL

Figure 1-7

Console Switch Inputs to the PC

1-14

1.6.3

I/O PRESET

The CP is set to initial conditions by KEY I/O PRESET or by a signal called MCT POWER CLR L, which generates
I/O PRESET when the machine is turned on. The switch signal, CSI KEY I/O PRESET L, is inverted and
gated
with MFTPl H to provide CST I/O PRESET, in both H and L versions. These two signals clear almost every
active register and flip-flop in the CP.

CST I/O PRESET L also generates IOC I/O PRESET, which is used to clear

most of the flip-flops in the various I/O device controls.

At MFTP2, the CP operating mode is established according to the setting of the console MODE switch.

KEY I/O

PRESET H is gated with MFTP2 to produce MPG MEM EXTN PRESET L (dwg. MPG), which is inverted (dwg.
CPR) to yield CPR SET MODE H. This, in turn, is gated with the output of MODE switch (KEY LINC) to establish the mode.

The mode-controlling flip-flop is shown as a pair of cross-coupled NOR gates (CPR). LINC memory

fields are established at MFTP2; Memory Page Extension Control flip-flops IB03,

IF03, SF06, DF03, and DF04

are direct-set.

I/O PRESET does not clear the IR. The three high-order bits, IR bits 0 through
2, are directly set to Is by lOR
I/O PRESET (dwg. INR) to ensure no conflict between the setting of the MODE switch and a mode-change
in-

struction (LINC) that might have been left in the IR.

NOTE
The I/O PRESET operations are also executed when
computer power is turned on; the processor is set for 8

MODE, regardless of the position of the MODE switch.
In the following descriptions of the flow diagrams,

is often referenced.

T^^j is comprised of

TS^ and TP^.

FILL and EXAM

1.6.4

The FILL switch is used to deposit instructions or data from the memory, using the LEFT SWITCHES
the PDP-1 2 Control Panel to specify the address used.

(LSW) on
The EXAM switch is used to examine the contents of the

core location specified by the LEFT SWITCHES. The logic for the FILL and EXAM
functions is identical during
manual timing. At MFTP2, the bits of the LSW are loaded into the MA. This action is accomplished
by enabling

LSW during MFTS2 (dwg. RCCj and loading MA at MFTP2 (dwg. RCL). The RUN flip-flop is set (dwg. CPR),
and memory timing is started (dwg. CST). The Get Next Instruction (GNI) signal (dwg. CPS)
is disabled because

no subsequent Major State is required. The outputs of the LEFT SWITCHES (dwg. RCC) are enabled
during TSl
and are loaded into the MA (dwg. RCL) at TPl

TP2 H

CPS DEFER (0) H

During T2, the instruction register (INR) is cleared by CPTP

CPS EXECUTE (0) H

CPS EXECUTE 2 (0) H, as shown on the INR print. The
only difference between a FILL function and an EXAM function occurs at T3. The
contents of RSW are loaded
•

•

MB for a FILL function, and MEM is loaded into MB for an EXAM function. No action occurs during T4,
and during T5 the RUN flip-flop (CPR) is cleared to stop timing. The AUTO flip-flop

into

(dwg. CST) is also reset if

had been set by pressing the AUTO switch.

1.6.5

FILL STEP

When the FILL STEP key is depressed, the contents of RSW are loaded into memory at the location specified

LSW. At MFTPO the SKIP, H, and Major State flip-flops are cleared.
During MFTPl the FILL STEP flip-flop is direct-set (dwg. CST), and the AUTO flip-flop is
is

depressed simultaneously with the FILL STEP switch. At MFTP2,

cause the

is loaded

set if the

AUTO switch

into itself (dwg. RCB), be-

always enabled during MFTP2, which occurs at the same time as TPl. The RUN flip-flop
is

direct-set by CST

MFTP2 (dwg. CPR), and the EN MEM flip-flop is set (dwg. CST). The Get Next Instruction

1-15

gate is inhibited (dwg. CPS), thereby preventing the FETCH flip-flop from being set to initiate another FETCH

At T2 the IR is cleared (dwg. INR)\ at T3 the RIGHT SWITCHES (RSW) are enabled (RCD), and their

cycle.

contents are loaded into the MB. During T5, the RUN flip-flop is cleared by the FILL STEP input on the data
side of the flip-flop, and the

AUTO flip-flop is cleared (dwg. CST) if the AUTO switch had previously been

depressed.

After the FILL STEP operation is completed and the EILL STEP switch is released, a STEP EXAM operation is

performed. The STEP EXAM flip-flop is set at TPS, as shown on the CST print. Signal CST STEP EXAM ( 1

•

CST MFTSO H produces CSI (KEY STEP EX. METSO) L. This signal is ANDed with CPT TSl (1) H to

produce a Carry Insert at T1 to increment the MA. The remainder of the function is treated as in the STEP

EXAM function.
1.6.6

STEP EXAM

When the STEP EXAM switch is depressed, the contents of memory are displayed by the memory buffer display
on the front panel. The address of the data to be displayed is specified by the memory address (MA). At MFTPl
the STEP
print.

EXAM flip-flop is set by CSI KEY STEP EXAM IN H and CST SET KEYS H, as shown on the CST

The AUTO flip-flop is al'o set if the AUTO switch is on. At MFTS2, Carry Insert (dwg. CYI) is enabled

by KEY STEP EXAM and CPT TSl (dwg. CYI) and loaded during TPl to increment the MA. The RUN and

START MEM flip-flops are set, and GNI is disabled. During T2 the IR is cleared. At TS3, MEM is enabled (dwg.
RCB) and loaded into the MB at TP3. During T5 the RUN, STEP EXAM, and AUTO flip-flops are cleared.
1.6.7

START 20

At MFTS
PMB BMSC 07 H is enabled by MFTSl (1) H and CSI KEY ST 20 H, as shown on the PMB print. At MFTPl
This switch causes the processor to start at location 20 of the currently selected instruction field.

bit 07 is loaded into the Program Counter (PC).

to the MA.

1.6.8

At MFTP2, the PC, now containing the number 20, is loaded in-

The FETCH and RUN flip-flops are also set at this time to start the program at location 20.

START 400

The switch has the same effect as START 20, except that PMA TMSC 03 H is enabled to start the program at
400.

1.6.9

START LS

This switch causes the processor to start the program at the address specified by the LEFT SWITCHES. At METS 1
the bits of LSW are enabled by CSI KEY LSW H • CST MFTS 1 ( 1 ) H to provide RCC EN LSW H, which is routed

(dwgs. PRA through PRF) and ANDed with CSI LSW 00 through 1 1 H.

METP
00-01

1 ,
•

LSW are loaded into the PC during
Flip-flops IB03-04 and IF03-04 are also direct-set at this time by CSI LSW
RCC ST LSW EN H, as shown on the MPG print. When extended memory is used, CSI IE 00 through 02
as shown on the RCL print.

flip-flops are direct-set I BOO through 02, as shown on the memory extension register {MXR) print.
flip-flop is direct-set as shown on the CPR print, by CSI

MFTP2 L

•

The RUN

-CSI KEY I/O PRESET L to start memory

and timing.

1.6.10

This switch causes the processor to perform one instruction. In the LINC Mode, the processor performs the
instruction defined by the LEET SWITCHES.

RIGHT SWITCHES are also used if the instruction is a two-word
format instruction. In the 8 Mode, the processor performs the instruction defined by the LEET SWITCHES only.

1-16

At MFTPl, the AUTO flip-flop (dwg. CST) is clocked and set if the

The DO flip-flop is direct-set by CST MFTPl and CSI KEY

AUTO Switch on the front panel is depressed
DO. The ENABLE MEM flip-flop (dwg. CST) is

DO L, which is routed from the 0 side of the DO flip-flop. At MFTP2 or TPl the
EETCH flip-flop (dwg. CPS) is set. The RUN flip-flop (dwg. CPS) is also direct-set
by C^T MFTP^ *-CSI KEY
I/O PRESET H.
direct-cleared by CST SET

At T1 PC IS enabled and loaded into MA. At T2, MA is loaded
into the PC, and the IR is cleared. During TS3
LSW are enabled by RCC EN LSW L (as shown on the RCC print) and routed to
the logic shown on the PRA
through PRF prints, where IR and MB are loaded simultaneously
at TPS. At T5, the RUN and AUTO flip-flops
,

are cleared and memory timing is stopped, if the

AUTO switch

not depressed or a multicycle instruction was

not executed.

1 .7

CENTRAL PROCESSOR TIMING - LOGIC DESCRIPTION (dwgs. CPTP, CPT, CPR,

The CP timing cycle can begin only when the three flip-flops

IDLE are all in the

state.

CPS)

CPR RUN, CPT CYCLE DONE, and CPT MEM

RUN and CYCLE DONE are set by MFTP2; MEM IDLE is set when a MEM

DONE

pulse occurs at the end of a memory Read-Write cycle.

The cycle starts with the TPl pulse, which is provided in both
time, the memory Read-Write cycle is initiated
a

positive- and negative-going forms. At the
same
by generating the CPTP START MEMORY H pulse (except

DO switch function is depressed). The pulse CPTP TPl H sets off the first delay

(dwg. CPTP). This also establishes CPT TS2 H by
setting the flip-flop

TS2 to the

Levels TSl through TS4 are conditioned by means
of
flip-flops, shown on dwg.

The next pulse, at 350 ns, is gated with CST EN MEM

is being

the

state (dwg. CPT).

RS-type

CPT as cross-coupled NAND gates.

The first pulse, tapped off the delay line at 100 ns, is CPTP
flop.

when

line in the time pulse sequence

TPID H, which clears the CPT CYCLE DONE flip(0)

H to provide CPTP TP2 whenever a DO function

executed and memory has not been enabled. In normal
operation, however, CPT? TP2 is triggered

MCT STROBE L pulse from memory control. TP2 L clears TS2 and sets TS3; TP2

(dwg. CPTP). TP3 and TP4 are tapped off this line
at 250 ns and 550
previous time state and sets the next one.

ns, respectively.

Each of these clears the

TS5 is established by setting a D-type flip-flop, CPT TS5

CPTP TP4 H, gated with INT PAUSE (0) H, sets off the next delay

H starts the next delay

line in the series, produces

(dwg. CPT) ”

CPTP TP5S

(generated immediately), and clocks the delay line.

The first pulse from the delay is CPTP OFF PAUSE H, tapped
(see Paragraph 1.7.1).

350 ns.

at 100 ns; it controls the action of T5
RECYCLE
Time pulse CPTP TP5 H is tapped at 300 ns. The next pulse
is CPTP TP5D H tapped at

The last pulse, LTP5, is tapped at 400 ns. This pulse clocks
the enabling flip-flops for extended memory IF,
DF,
BF, and SF registers (MCI 2-0-MXF). Finally, if T5
RECYCLE is clear, CPTP TP5 H sets CPT TSl, starting the
delay line (dwg. CPTP), which, tapped at 200 ns,
sets the CYCLE DONE flip-flop (dwg. CPTP)
and establishes
one of the conditions for TPl.

1.7.1

T5 RECYCLE

The LINC instructions ROR, ROL, SCR, SAM, and MUL, and
tune at the end of a cycle to complete their operations.

the PDP-8 EAE instructions all require additional

To provide more time, time states TS5 and TPS are

repeated until the operation is finished.

1-17

When CPTP TP4 H sets CPT TS5, it is also gated with one of the recycle condition signals at NOR GATE Ml 17
location L22 to set the RECYCLE SYNC flip-flop (dwg. CPT).

The output of this flip-flop enables the data in-

output of T5
put of the T5 RECYCLE flip-flop, which is set at the occurrence of the OFF PAUSE H pulse. The
TSl L is
SET
RECYCLE causes TS5 to remain set when CPTP TPS H occurs. At the same time, the signal CPT
1

inhibited, thus preventing TSl

from being established. The timing chain to produce T5 is restarted by CPTP

TP5D H, gated with CPT T5 RECYCLE (1) H. As soon as the recycle condition is no longer true, the RECYCLE
SYNC flip-flop is cleared, disabling the T5 RECYCLE flip-flop (at the next CPTP OFF PAUSE H pulse) and
allowing the normal sequence of events to proceed.

CP Timing and the Memory Read-Write Cycle

1.7.2

In normal operation, the memory cycle is initiated once during each CP timing cycle.

At TP

the CPTP START

MEMORY H pulse is produced, which starts the memory timing chain (dwg. MCT refer to Chapter 2 for a de;

The Read-Write cycle proceeds independently, but the CP cycle is dependent upon the mem-

tailed description).

ory cycle at two points:
a.

TP2 is initiated by the MCT STROBE L pulse; the CP cycle then proceeds to completion.

TPl is not asserted until the memory cycle is finished, and MEM IDLE (1) H is true.

In practice, the memory cycle is somewhat faster than the CP cycle; consequently, there is no delay at either of
the two points.

1.8

THE CENTRAL PROCESSOR IN ACTION

The following discussion is conducted on a gate-chasing level and is keyed directly to the logic schematics in
Volume III (also, refer to Tables 1-4 and 1-5). The activities of the CP are detailed sequentially, from the
pressing the START LS through the completion of a LINC 1/3 class instruction.

Two important signals, not directly in this sequential flow but essential to the understanding of processor action,
are CPS GNI and CPT TSl.
1.8.1

Time State 1

CPT TSl H

Whenever the processor is not running (RUN flip-flop is clear), the flip-flop TSl (dwg. CPT) is in the 1 state,
because the processor does not stop until a cycle is complete. The final pulse CPTP TPS H, sets CST TSl (1) H.

CPT I/O PRESET L also sets TSl to 1.
1.8.2

Get Next Instruction: CPS GNI (dwg. CPS Ml 15 K04)

The circuitry that produces the CPS GNI is a very common example of the PDP-1 2 inhibit logic. Basically, the
signal is true unless one or more of several disabling conditions is true. Refer to the inputs on the gate that produces CPS GNI L (dwg. CPS Ml 15 K04). This gate is a NAND gate; thus, the signal is true only when all the inputs are high.

The names for two of these inputs are preceded by negation signs (- ).

In each case, this notation

means that the input is high when the named signal is not true. To find the source of the signal, remove the
negation and change H to L. Example: The source of -CPS DEFER SET H is CPS DEFER SET L. Examination

of the AND-NOR gate expansion M 1 60 (dwg. CPS) reveals that a similar condition holds for some inputs.

Consequently, unless specifically inhibited, CPS GNI L is always true.

1-18

Table 1-4

Functional Logic Description,

START LS

Logic Component

Time State/

Logical

Major State

Sequence

Location and

Description

Drawing Reference
1

NOR GATE
Ml 15, K13

START LS produces the signal CSI
KEY STARTS H, as do any of the start

(CSI)

keys.

INVERTER

CSI KEY STARTS H is inverted to CSI

Mill, K13

KEY STARTS L.

(CSI)
3

NOR GATE

The signal CSI KEY STARTS L qualifies

Ml 17, L22

the gate and is routed through a filter

(CST)

and Schmitt trigger to eliminate switch
bounce.

NAND GATE

From the Schmitt trigger, a 100 ns pulse

NOR gate and is ANDed

M700

(CST)

with the signal at pin KP2. The gate

sent to the

qualifies because the

RUN flip-flop is

not set at this time.

MFTSO

MFTPO

NAND GATE

The output MFTSO L is inverted to

M700 (CSD

MFTSO H.

NAND GATE

Approximately 50 ns after MFTSO oc-

M617, J07

curs, the signal MFTPO and -CSI KEY
CONT H produce CPS CLR STATES to

(CPS)

clear all Major State flip-flops.

MFTSl

AND/NOR GATE

CSI KEY CONT H and CST MFTPO

Ml 60, J27

produce the signal CKH CLR SKIPS to

(CPS)

direct-clear the

NAND GATE

CSI KEY ST LSW and CST MFTSl

Ml 13, K30

produce RCC ST LSW EN L.

H and the SKIP flip-flops.

(RCO
9

NOR GATE
M617, H23
(RCC)

RCC ST LSW EN L is inverted to RCC
ST LSW EN H.

AND/NOR GATE

RCC START LSW EN H ANDed with

Ml 60, K36
(MPG)

CSI LSW 00 H (if LSW 00 is depressed)

produces MPG SET IB-IF 03 L to
direct-set IB 03 and IF 03 flip-flops.

’

NAND GATE

IB 04 and IF 04 flip-flops are direct-set

Ml 13, K36
(MPG)

01 H, if LSW 01

NAND GATE

Extended memory flip-flops IF 0

Ml 13, K38«& K40

by RCC ST LSW EN H and CSI LSW
is

depressed.

through 2 are set by RCC ST LSW EN H

and CSI IF 0 H through CSI IF 02 H.

1-19

Logic Component

Location and

Drawing Reference

MPTPl occurs approximately 2 ms after

(CST)

MFTS

NAND GATE
M113, H21
(RCL)

NOR GATE
M617, J21
(RCL)

MFTS2

flip-flop is set.

CST MFTPl H and CSI KEY STARTS L
produce the signal RCL START PC L.
The PC LOAD signal is produced by
RCL START PC L. The PC is loaded
with the contents of LSW.

CST MFTPl H sets CST MFTS2 and
clears CST MFTS 1.

NAND GATE

This signal CPS GNI H produces the

Ml 17, K05

signal CPS

(CPS)

following conditions are true;
a.

FETCH SET L when the

-CPS INTERRUPT SET (no interrupt has occurred)

-CPS TAPE SET (no tape break
request has occurred)

—CPS BREAK SET (no three-cycle
data break request has occurred).

NAND GATE
M113,H24

CPS FETCH SET L produces the signal
RCC PC FOR MA.

(RCQ

NAND GATE
M115,H25

(RCQ

RCC PC FOR MA and CST MFTS
(0) H and CPT TSL (1) H produces the
Enable signal RCC EN PC 2-1 H.
1

MFTP2 or

Approximately 2 ms after CST MFTPl H

TSl

has occurred, CST MFTP2 occurs.

CST
MFTP2 clears the flip-flop CST MFTS2.

NAND GATE

CST MFTP2 and -CSI KEY I/O PRESET

Ml 13, L26

produce the Load signal RCL LOAD

(RCL)

MA H.

NOR GATE

Signals CST MFTP2 L and -CSI KEY I/O
PRESET produce the signal CPR SET

M112, LIO
(CPR)

RUN L to direct-set the RUN flip-flop
and start CP timing.

1-20

Table 1-5
Functional Logic Description, ADA I 12
Logic Component,

Time State/

Logical

Major State

Sequence

Location and

Description

Drawing Reference
It is assumed

that the instruction is in

memory and will be fetched.
TSl

FLIP-FLOP
M216, J12

The signal CPT SET CYCLE DONE L
direct-sets the

CYCLE DONE flip-flop.

iCPT)
2

FETCH

TPl

NAND GATE

Because all inputs on the gate are true,

M617, LOS
{CPTP)

TPl L.

NAND GATE

CPTP TPl L produces CPTP TP

the gate qualifies and generates CPTP

M617, LOS
{CPTP)
4

FLIP-FLOP

When the signal CPS FETCH SET L is

M2 16, K06

true, the flip-flop is set by the pulse

{CPS)

CPTP TPl H. All other Major State
flip-flops are cleared.

NAND GATE

The signal CPTP START MEMORY L is

Ml 12, K06

generated here.

{CPTP)
6

NOR GATE

CPTP TPl L produces the signal RCL

M617, J21

LOAD MA H. The MA contains the

{RCD

address where the instruction is to be
fetched.

DELAY LINE
M3 10, H06

CPTP TPl H triggers the delay line and
produces the signal CPTP TPl D 100 ns

{CPTP)

later.

NOR GATE

CPS FETCH (1) L produces the signal
CYI PC INCREMENT.

Mils, LOS

{CYD
9

NAND GATE
M617, J06

The pulse CPTP TP 1 direct-dears the
CPT TSl flip-flop and direct-sets the

{CPT)

CPT TS2 flip-flop.

NOR GATE

CPS FETCH (1) H produces the signal
CPS FETCH B (1) H.

M617, J07
{CPS)

TS2

AND/NOR GATE

CYI PC INCREMENT and CPT TS2

M160, J26
{RCB)

(1) H qualify the Enable gates to produce RCB EN MA 0-4 H and RCB

EN MA 5-11 H.
12

AND/NOR GATE

The signal CYI CARRY INSERT L is

M160, Lll

generated by signals CYI PC

{CYI)

INCREMENT H and CPT TS2 (!) H
and CST EN MEM (1) H.
1-21

Logic Component,

Location and

Drawing Reference

The signal CYI CARRY INSERT L is
routed to adder bit 1 1 to increment the
PC. If PRF PARTIAL SUM L already
contains a logical 1

the output out of

the adder is zero and a Carry Out to the

next higher order adder occurs.

NOR GATE

Approximately 500 ns to 520 ns after

MEMORY H pulse the

M617, J07

the CPT START

{CPTP)

MCT STROBE L pulse occurs, producing
the signal CPTP TP2 H. The MCT
STROBE L signal also clears the MEM
IDLE flip-Oop.

NAND GATE
M113,H21
iRCL)

CYI PC INCREMENT H and CPTP
TP2 H produce the signal RCL LOAD
PC H, which is used to load the PC
register.

CPTP TP2 H

CPS DEFER (0) H CPS
EXECUTE (0) H CPS EXC 2 (0) H
produce the signal INR CLEAR IR L to
•

•

direct-clear the IR.

NAND GATE
M617,H38

CPTP TP2 L clears the CPT TS2 flip-flop
and sets the CPT TS3 flip-flop.

ilNR)

NAND GATE
Ml 17, H30
{RCB)

RCB EN MEM H is produced by RCB
GO MEM TS3 L. (This signal is high because the inhibit logic that produced it
is

not qualified.)

CPT TS3 (1) H

•

CPS INTER (0) H
CST EN MEM (1)H.
•

•

INVERTER

Approximately 350 ns after CPTP TP2 H

Mill, J09

CPTP TP3 L is generated.

{CPTP)

NAND GATE

CPTP TP3 H and CPS EXEC (0) H pro-

Ml 13, H21

duce RCL LOAD MB H. The contents

{RCL)

of MEM are loaded into the MB.

NAND GATE

CPTP TP3 and CPS FETCH B ( ) H produce the signals INR LOAD IR 0-7 and
INR LOAD IR 8-1 1. The contents of

MI13,H36
{INR)

MEM are loaded into the IR. ADA

12(1 1 32g ) can now be decoded.

AND/NOR GATE

CPTP TP3 H

Ml 60, 27

duces the signal SKH CLEAR SKIPS L,

{SKH)

which direct-dears the H and the SKIP
flip-flop.

1-22

•

CPS FETCH (1) L pro-

Table 1-5 (Cont)
Functional Logic Description, ADA I 12
Logic Component,

Time State/

Logical

Major State

Sequence

Location and

Description

Drawing Reference

TS4

NAND GATE

CPR L MODE H

M113, J33

IROl (0) H produce the signal INS SGRP

ms)

L, which is inverted to INS SGRP H.

DECODER

INS SGRP H, in conjunction with IR

M161, J35

bits 2 through 6, decodes INS

•

INR IROO (0) H

•

INR

ADA H.

(INS)

NAND GATE
M115,H31
(INS)

INS SGRP H *INR IR 02 (1 ) H produce
the signal INS INDEX CLASS L, which
is inverted to INS INDEX CLASS L H.

DECODER

INRIR08(1)H

M161, J39

duce INS

(INS)

•

INR IR 10 (1)H pro-

NEQ 12 H and INS N EQ 12

The ADA instruction is decoded into

usable parts (INS ADA, 1=1, and

= 12).

NAND GATE
Ml 13, J33

INS INDEX CLASS L H INS (I EQ 1
B EQ 0) L produces INS LINC IND I
•

RECT H when INS (I EQl
is

BEQ 0) L

not true.

NAND GATE

INS LINC INDIRECT H

Ml 60, K08

(1) H produce the signal CPS

(CPS)

SET L.

(CPTP)

CPTP TP4 L is generated approximately
300 ns after CPTP 3 L. CPTP TP4 L
clears flip-flop CPT TS4 and direct-sets
flip-flop CPT TPS.

(CPTP)

CPTP OFF PAUSE occurs approximately
250 ns after CPTP TP4 L and CPTP

TP5

•

CPS FETCH B

DEFER

TPS H is generated approximately 250 ns
after CPTP

FLIP-FLOP
M2 16, L07

OFF PAUSE H.

The MEM IDLE flip-flop is set by CPT

MEM DONE H.

(CPT)
31

FLIP-FLOP
M216, L17

The RUN flip-flop is clocked by CPTP
TPS H and is left-set because the inhibit

(CPR)

logic that produces the signal

CPR EN

RUN H is not qualified.
32

FLIP-FLOP
M216, J03

The TS5 flip-flop is clocked by CPTP
TPS H. The data input of the flip-flop is

(CPT)

connected to the T5 RECYCLE flip-flop.
Because the T5 RECYCLE flip-flop is
not set, the TS5 flip-flop is reset.

1-23

Table 1-5 (Cont)
Functional Logic Description, ADA 112
Logic Component,

Location and

Drawing Reference
33

NAND GATE
Ml 15, J05
(CPT)

CPT lOT PAUSE (0) H CPTP TP5 H
CPT T5 RECYCLE (0) H produces the
signal CPT SET TS L which sets the
•

•

TSl flip-flop.
34

NAND GATE

The signal INS (L INDEX -jS ^ 0) L (j3 =

Ml 15, K29

FETCH ( H and CPT TS
H produce the Enable signal RCA
ENABLE IR 8-1 H.

(RCA)

2) and CPS

1 )

( 1 )

DEFER

With flip-flops CPR RUN • CPT MEM

(CPTP)

TPl

IDLE

•

CPT CYCLE DONE set, CPTP

TPl L pulse is produced.
36

FLIP-FLOP

M2 16, K06
(CPS)

The flip-flop is clocked by CPTP TPl H.
The data side of the redefined DEFER
flip-flop is low because the inhibit logic
was qualified by CPS FETCH B (1) H
INS LINC INDIR H.
•

NAND GATE
(CPTP)

CPTP TPl L and CST EN MEM produce
the signal CPTP START MEMORY H to
start another memory cycle.

NOR GATE

Approximately 500 ns to 520 ns after

M617, J07
(CPTP)

CPTP TPl H, the signal MCT STROBE is
generated at the memory and routed to
the NOR gate to produce CPTP TP2 H,

M112, JIO

which is routed into a delay line.
39

FLIP-FLOP
M2 16, L07

The MEM IDLE flip-flop is direct-cleared
by MCT STROBE L.

(CPT)

NAND GATE

CPTP TP2 L clears flip-flop CPT TS2
and sets flip-flop CPT TS3.

Ml 13, K30
(CYT)

NAND GATE

CPS DEFER B (1) H and INS INDEX
-INS NEQ 00 H produce
the signal CYI LINC INDEXING H.

CLASS L H

•

Ml 13, K30

CYI LINC INDEXING H and INR IR 07
(1) H produce the signal CYI T3

(CPF)

INDEX H.

AND NOR GATE

The signals CYI T3 INDEX H and CPT
TS3 (I) H and -PMA HALF WORD L
produce the signal CYI CARRY INSERT

Ml 13, K30
(CYF)

1-24

Table 1-5 (Cont)

Functional Logic Description, ADA I 12
Logic Component,

Time State/

Logical

Major State

Sequence

Location and

Description

Drawing Reference

NAND GATE
Ml 17, H30
{RCB)

CST EN MEM (1) H CPT TS3 (1) H
CPS INTER (0) H RCB GO MEM TS3
L (The last signal is high because the
•

•

inhibit logic did not qualify it.)

the signal RCB E

EM MEM 6-1

produce

MEM 0-5 H and RCB

H. The address in the

CPTP

TPS

NAND GATE

CPS EXC 2 (0) H

Ml 13,H21
{RCL)

the signal RCL

CPTP TPS H produce
LOAD MB H. The con•

tents of MEM, along with Carry Insert,
are loaded into the MB.

TS4

{CRT)

NAND GATE

CPTP TPS clears flip-flop CPT TS3 and
sets flip-flop CPT TS4.

Ml 17, H30
iSKH)

MB bit 00 = 1, then signals CPT? TP4

H CPS DEFER B (1) H CPR L
MODE H PRA MB 00 ( ) K direct-set
the H flip-flop.
•

•

TS5

FLIP-FLOP

CPTP TP4 L direct-sets the TS5 flip-flop.

M2 16, JOS
{CRT)

TPS

TSl

{CRTR)

CPTP TPS is generated 400 ns after
CPTP TP4 L.

FLIP-FLOP

CPTP TPS H clocks the RUN flip-flop.

M2 16, L07

The data input of the flip-flop is true

{CRR)

because the inhibit logic is not qualified.

{CRT)

CPTP TPS H direct-dears the TS5
flip-flop and sets the TSl flip-flop.

FLIP-FLOP
M216, J12

The signal CPT SET CYCLE DONE L
direct-sets the

CYCLE DONE flip-flop.

{CRT)
53

NAND GATE

CPS DEFER SET H

M117, L13
{RCB)

5-11.

AND/NOR GATE
Ml 60, J26

EXECUTE
TPl

CPTS (1) H CPS
DEFER (0) H produces RCB EN MB
•

INS INDEX CLASS L H
(1)

•

CPS DEFER

CPT TSl (1) H produces RCB

{RCB)

EN MB 2-4 H.

NAND GATE

The RUN, MEM IDLE and CYCLE

M617, LOS

DONE flip-flops are set; thus, CPTP

{CRTR)

TPl H is produced, and the EXECUTE
cycle is entered.

1-25

Location and

Drawing Reference

NAND GATE

The inhibit logic is no longer qualified,

Ml 17, K05

and the EXECUTE cycle is entered.

(CPS)

NOR GATE
M617, J21
(RCL)

CPTP TPl H produces RCL LOAD
MA H. The new address is placed in the
MA.
CPTP TPl clears CPT TSl flip-flop and

(CPT)

(0)
sets CPT TS2 flip-flop.

Approximately 520 ns after CPT TSl

(CPTP)

MCT STROBE from memory produces
CPTP TP2 H and clears the MEM IDLE
flip-flop.

NAND GATE
M117,H30
(RCB)

RCB GO MEM TS3 L CPS INTER
H CPTTS3 (1)H CST EN MEM
( ) H produce RCB EN MEM 0-5 H and
RCB EN MEM 6-1 H.
•

•

Approximately 350 ns after CPTP

(CPTP)

TP2 H, CPTP TP3 occurs.

NAND GATE

CPS EX 2 (0) H

M113,H21

the signal RCL

(RCL)

•

CPTP TP3 H produce

LOAD MB H. The MB

has been loaded with the contents of

MEM.
FLIP-FLOP
M2 16, L07

CPT MEM DONE L sets the MEM IDLE
flip-flop.

(CPT)

NAND GATE

INS ADA L

M113, J25
(RCB)

produces RCB AC ADDS L.

AND/NOR GATE

RCB AC ADDS H CPT TS4 (1) H
CPS EXECUTE B (1) H produce RCB
EN MBL. RCB EN MB L enables MB 0

M 160,126
(RCB)

•

CPS EXECUTE B (1) H

•

through 1.

AND/NOR GATE

RCB AC ADDS

M160, J20
(RCA)

duce the signals RCA EN AC 0-5 H and

RCA EN AC 6-1

•

CPT TS4 (1) H proH.

The summation

of AC and MB are enabled and are loaded
into the register bus.

(CPTP)

CPTP TP4 is true.

1-26

Table 1-5 (Cont)
Functional Logic Description, ADA I 12
Logic Component,

Time State/

Logical

Major State

Sequence

Location and

Description

Drawing Reference

NAND GATE

RCB AC ADDS L CPTP TP4 H produce the signal RCL LOAD AC. The
summation of MB and AC is loaded into
•

M113,H21
{RCL)

the AC.

FLIP-FLOP

If overflow out of adder bit 00 occurs.

M216, J12

the

FLOW flip-flop is set.

(FLE)

1.9

8-MODE INSTRUCTIONS

When computer power is first applied, the PDP-1 2 is placed in 8 Mode by MCT PWR CLEAR L. The PDP-1
Computer can also be switched to 8 Mode from LINC Mode by setting the MODE switch to 8 Mode and pressing
I/O PRESET.
Direct and indirect addressing schemes are used in the 8 Mode.

A block diagram of the addressing scheme used in

the 8 Mode is illustrated in Figure 1-8.

The following paragraphs describe 8-Mode FETCH, DEFER, and EXECUTE cycles.

A brief description of con-

trol signals for all 8-Mode instructions is also included.

1.9.1

FETCH Cycle

All 8-Mode instructions are treated identically during T2 and T3 of the

when the DO flip-flop is set by the DO key:

FETCH cycle. The only exception occurs

the PC is not advanced, and the contents of LSW are loaded into

MB and IR. When the DO key is cleared during T2, ENABLE MA (dwg. RCB) and a CARRY INSERT (dwg.
CYF) for bit
is

are generated during TS2.

The PC is advanced in this fashion during TP2. The IR (dwg. INR)

also cleared during TP2.

During TP3, the SKIP and H flip-flops (dwg. SKH) are cleared.

An ENABLE MEM signal is generated {d'^g.RCB)
MEM is simultaneously loaded into MB and IR during TP3. An instruction is decoded during
T4 into a memory reference instruction (MRI), operate instruction (OPR), or Input/Output transfer instruction
during TS3, and

(lOT). During T4, the instruction register (dwg. INR) is gated to the instruction decoders (dwg. INS), which are
qualified by the

MODE flip-flop. Bit 03

examined during this time to determine the addressing scheme and the

next Major State. If bit 03 is set, the DEFER flip-flop (CPS) is set, thereby initiating a DEFER cycle. If bit 03
is

not set, the EXECUTE flip-flop is set, thereby initiating an EXECUTE cycle for all instructions except OPR

and IMP.

1.9.2

DEFER Cycle

During T1 of the DEFER cycle, the selection of page 0 or current page is determined by MB bit 04. If MB bit 04
= 0, MB bits 5-1 1 are enabled (dwg. RCB) during TSl and loaded into MA bits 5-1 (dwg. RCL) at TPl. MB bits
1
0-4 were not enabled during this transfer; consequently, 0 is automatically placed in
selects an address on page 0.

MB bit 04 =

MA bits 0 through 4, which

an indirect address on the current page is selected and MB bits

1-27

INDIRECT^n. NO

ADDRESS

-EXECUTE

vjR03="l^^

^ES (MB CONTAINS AN ADDRESS)
CURRENT'
PAGE
^IR04*I ^

-MA5-II

MB5-II-

-MAO-4

-^^MOOE^
AUTO INDEX
MA8=I ^
YES (CARRY INSERT)

JUMP

^^NO

1-28

0-1 1 are loaded into the MA.

During T2 STROBE, memory is read. At TS3, the decoder is checked
to

determine if the locations in absolute address 0010 through 0017 have
auto-indexing is selected, a Carry Insert (dwg. CYI) is generated and

been selected for auto-indexing.

IMP was decoded at TP4, the MB is loaded into the PC, and the computer proceeds to
For any other instruction, the EXECUTIVE flip-flop is set, and the EXECUTE
1.9.3

added during the MEM to MB transfer.

another FETCH cycle.

Major State is entered.

EXECUTE Cycle

The EXECUTE Major State is entered from either the FETCH or DEFER cycle,
scheme used.

If the

depending on the addressing

EXECUTE cycle is entered from the FETCH cycle, IR bit 04 is examined to determine if

the current page or page 0 is addressed (similar to operation in the

DEFER cycle). When EXECUTE is entered

from the DEFER cycle, the MB is loaded into the MA, becau.se it contains

the effective address of the operand.

During T2, the address specified by the MA is read into the MB as it is for

all

compute cycles, except the EXC 2

Major State and a SET instruction.
During the remaining time states, the MRI instructions are executed. They
are as follows:
a.

AND and TAD

ISZ

DCA

IMS

AND (0000)

The AND instruction causes a bit-by-bit Boolean AND operation between the
of the AC and the data word specified by the instruction or MB.
tents of

MEM are loaded into the MB.

contents

During T3, the con-

During T4 the following functions are enabled and loaded into the AC

simultaneously,

thus placing JJl and MB into the AC.
a.

AC, the complement of AC (dwg. RCQ

BCL, a logical AND of MB (dwg. RCQ

The result in the AC is then complemented during T5 by enabling AC and loading

AC.

The truth table for the logical AND operation is shown below.

TAD (1000)

Result

Two’s complement add. The logical flow of AND and TAD is identical through
T3 of
the EXECUTE cycle. During T4, the AC and the MB are enabled
and loaded into the
AC and LINK to find the sum of AC and MB. The GNI is set to initiate a new FETCH
cycle.

ISZ (2000)

Increment and Skip if zero.
1 1

MEM (dwg. RCB) and CARRY INSERT (dwg. CF7) to bit
MB at TP3. PRA CARRY 00 (dwg. SKH) is

are enabled during TS3 and loaded into

tested for Overflow; if Overflow occurs, the SKIP flip-flop is set.

At T1 of the next

FETCH cycle, the PC is enabled and if the SKIP flip-flop is set, a CARRY INSERT
(dwg. CYI) is generated to increment the MA.

DCA (3000)

Deposit and clear the AC. During T3 the AC is loaded into the MB.
The control sigAC ENABLE (dwg. RCA) and MB LOAD (dwg. RCL). At T4 the AC is

nals are

cleared by not providing AC enable and loading AC.

1-29

JMS (4000)

1.9.4

Jump to subroutine. The instruction stores the pointer address (PC) in the first location
of subroutine at T3, enables PC (dwg. RCC), and loads the MB (dwg. RCL). Control
of the program is transferred to the second location of the subroutine at T4 by incrementing the contents of the MA with a CARRY INSERT and loading the PC.

8-Mode Operate Instructions

Operate instructions require only one cycle for completion and can be microprogrammed. The FETCH cycle for
Tl, T2, and T3 has been described previously. Operate instructions are divided into two classes.
instruction is decoded (dwg. INS) by ANDing IR bits 00, 01, and 02, and the output from the

An Operate

MODE flip-flop

(dwg. CPR). IR bit 03 is examined (dwg. SLA), to determine if Operate 1 or Operate 2 class instructions are to
be decoded.

Operate 1 Qass Instructions — Operate 1 instructions are decoded when IR bit 03 = 0. Operate 1 instructions
are primarily used to manipulate the LINK and the AC.

MB bits 04 and 06 are used to clear or complement the

AC as shown below:

CMA (7040)

MB04

MB06

Action

Instruction

AC-^ AC

NOP

AC
0-^ AC
AC + AC

CLA

CMA

CLA, CMA

CompleMent the AC is decoded by signals SLA OPRl H, CPT TS4 (1) H, and PRD
MB06 (1) H (dwg. RCC), thus enabling AC. The AC is automatically loaded by an
Operate instruction during every TP4 (dwg. RCL).
1

CLA (7200)

CLear the AC. No Enable signal is provided during TS4, and the AC is loaded during
TP4. The effect is that of loading all zeros into the AC, thus clearing the AC.

CLA, CMA

CLear and CoMplement the AC. The result of clearing and complementing the AC is

(7240)

that all AC bits contain binary

Is.

This is done simply by ORing AC and AC (dwg.

RCL) and loading the AC.

MB bits 05 and 07 are used to clear or complement the LINK as shown below.

CML (7020)

MB05

MB07

L->L
L->L

CML

0->L

CLL

L+ L-^L

CLL, CML

Action

Instruction

NOP

CoMplement the LINK is decoded by SLA MB07 (1) H, and ANDed with SLA (OPRl
TS4) H (dwg. FLK). If the LINK = 0, the AND/OR combination routed to the data
-FLK
side of the LINK flip-flop is disqualified, setting the LINK to
If the LINK =
NOT ADDER LINK H is qualified, setting the LINK to 0 when the flip-flop is clocked
•

by RCL AC LOAD H at TP4.

CLL(7100)

CLear the LINK is accomplished by inhibiting NOT LINK ENABLE, which qualifies the

AND/OR gate routed to the data input of the LINK when RCL AC LOAD H clocks the
LINK flip-flop (dwg. FLK).
CLL, CML

CLear and CoMplement the LINK results in setting the LINK flip-flop to

(7120)

accomplished by inhibiting the AND/OR input of the LINK (dwg. FLK).

1-30

This is

Increment the AC is decoded by SLA OPRl H • PRF MB 1 1 (1) H (dwg. CYI). This
CARRY INSERT at TP4 to adder bit 1 1 (dwg. PRF). MB08 and
MB09 are used to rotate the AC right or left; MB 10 determines whether to rotate once

IAC(7001)

action generates a

or twice.

RAR (7010)

RotAte Right is decoded by PRE MB08 (1) H

•

SLA OPR SHIET EN H (RCS) to

produce RCS EN SHIFT RIGHT H which is routed to the Load gates (dwgs. PRA
through PRF).

RAL (7004)

RotAte Left is decoded by PRE MB09 (1) H SLA OPR SHIFT EN H (RCS) to produce RCS EN SHIFT LEFT, which is routed to the Load gates (dwgs. PRA through
•

PRF).

RTR(7012)

Rotate Twice Right and Rotate Twice Left is decoded by SLA OPRl H

and RTL

(1)

•

CPT TS5

H PRF MB 10 (1) H. This gate (dwg. SLA) accommodates another Rotate opera-

tion during T5 for a total of two Rotate operations; one during T4 and another during

(7006)

T5.

Operate 2 Qass Instructions
are decoded {i.e.

Operate 2 class instructions are decoded the same way Operate 1 class instructions

by ANDing IR bits 00 through 02).

SMA (7500)
SPA (7550)

R bit 03 =

Skip on a Minus AC (dwg. SKH) is executed by testing AC bit 00. This signal ANDed
with MB bit 05 sets the SKIP flip-flop at T4 when AC 00 = 01 and MB08 = 0.
Skip on a Positive AC is executed by the same gate as SMA, except the signal is ANDed
with MB08 1 (H), the reverse sensing bit.

SZA (7440)

Skip on a Zero AC is executed by testing AC bits 00 through 1 1 for Os. When MB bit
06 is set and the AC is equal to zero, SKH AC EQ 0 is enabled to set the SKIP flip-flop
at T4.

SNA (7450)

Skip on a Non-zero AC. In this case, the same gate that was used for SZA is used.

H AC EQO is not qualified, thereby qualifying the AND/OR combination SLA OPR2
PRE MB 08 (1) H, which sets the SKIP flip-flop at T4.
SNL (7420)

Skip on a Non-zero LINK is executed by FLK LINK ( 1 ) H and PRD MB 07; if the gate
is

SZL (7430)

•

qualified, the SKIP flip-flop is set at T4.

Skip on a Zero LINK is decoded by the same gate as SNL, except that it is ANDed
with the reverse sensing bit MB 08 ( 1 ) H.

OSR (7404)

Inclusive

OR of Right Switch Register with AC. OSR is decoded by PRE MB09
L
TS5) H to enable RSW (RCD). During TS5, the AC is ORed with
( 1 )

and RCA (OPR2

•

RSW by enabling SET AC (RCA).
HLT (7402)

The computer stops at the conclusion of the current machine cycle.

SLA OPR

•

PRF MB 10 (1) H

•

HLT is decoded by

CPS FETCH. This signal is routed to the AND/OR

combination controlling the data to the RUN flip-flop.

CPR HALT H is ANDed with

TSS UF (0) H. TSS UF (0) H is routed to +3V if the TSS 12 option is not included.
The RUN flip-flop is cleared at TP5 to stop processor timing.
1.10

INTERRUPT

INTERRUPT is checked at T1 of every EETCH cycle. When the program interrupt facility is enabled by the ION
instruction (6001), and the Interrupt Request signal is tnie, the INTERRUPT Major State is

entered.

The ION

MB bits 03 through 08 CPTP TP4 H to provide IOC PROC lOT
L, which is ANDed with PRE MB 10 (1 H to set the INTERRUPT
)
ENABLE flip-flop. The INTERRUPT ENABLE

instruction is decoded (dwg. IOC) by INS lOT •

•

1-31

INTERRUPT DELAY flip-flop. IOC INTERRUPT DELAY (0) H is ANDed with other signals
CPS INTERRUPT SYNC (I) is ANDed with -CPS BREAK
SET H, -CPS TAPE SET H, CPS GNI H to provide CPS INTERRUPT SET L to set the INTERRUPT flip-flop.
flip-flop sets the

to set the INTERRUPT SYNC flip-flop (dwg. CPS).

In the

INTERRUPT cycle during TSI, the DF and IF are transferred to the save field register by CPS INTERRUPT

SET H CPT TS 1) H, which provide MEA LOAD SF L. MEA LOAD SF L or MPG LINC SET L to provide
MPG LOAD SF (dwg. MPG), which clocks the SAVE FIELD flip-flops and loads the IF and DF into the SF. The
•

•

(

IF and IB flip-flops are direct-cleared at this point by MPG-0-IF-IB03-04 L, and the DF flip-flops are cleared by

MPG 0-DF03-04 L (dwg. MPG). This action is necessary because all interrupts are trapped to the IF 0.
INTERRUPT occurs in the PDP Mode, the MA is cleared (location 0000) by inhibiting the enable gates and
loading the MA with all Os. The INTERRUPT ENABLE flip-flop is also direct-cleared (dwg. IOC) (see Paragraph
If the

1.21 for LINC Mode interrupts).

LINC MODE INSTRUCTIONS

1.11

LINC-Mode instructions are grouped in the following manner according to their addressing schemes and interrelationships.

A block diagram for LINC-Mode addressing is shown in Figure 1-9.

Direct Address

a Class Instructions

MSC Instructions

Rotate and Shift Instructions

Skip Instructions

Operate Instructions

LINCtape Instructions

Trap Instructions and Interrupt

1.11.1

Class Instructions

LINC FETCH

LINC instructions are identical during T1 through T3 of the FETCH cycle. If the DO flip-flop is not set at Tl,
the PC is enabled and loaded into MA2 through 11. If the SKIP flip-flop is set, the

incremented by CARRY

INSERT. The current field (IF03 and 04) is also loaded into MAOO and 01. At T2, the Program Counter is incremented by CYI PC INCREMENT and FETCH (dwg. CYP). The PC is loaded by CYI PC INCREMENT and
CPTP TP2 (dwg. RCL). The IR is cleared by CPTP TP2 (dwg. INR). During TS3, MEM is enabled and loaded
into the MB by RCB GO MEM TS3H
CPS ENTER (0) H CPT TS3 (1) and CST EN MEM (1) H (dwg. RGB).
•

•

The MB is loaded by EXC 2 (0) H and TP3 H. The IR is loaded every TP3 during a FETCH cycle.

DO flip-flop is set, at Tl, the MA is not incremented by the SKIP flip-flop, because the EN MEM flip-flop
DO L. A CARRY INSERT for a SKIP is only possible when CPS FETCH SET H
CST EN MEM (1) H are true (dwg. CYI). At T2, the PC is also not incremented because the EN MEM flip-flop
If the
is

direct-cleared by CST SET

not set. During T2, the IR is cleared, as is the case in all FETCH cycles during T2. At T3, LSW are enabled by

•

RCC EN LSW. The switch inputs are routed to enable gates (dwgs. PRA through PRF) and loaded into MB and
IR simultaneously.

1-32

1.1 1.2 Full Address Instructions

MB Bits 00 and 01 indicate the operation to be performed, while bits 02 through

contain the address of the

operand. The Full Address instructions are limited to the current instruction field (IF) addresses 0000 through
1777. Full Address instructions are decoded from IR bits 00 and 01 into 2000 (ADD), 4000 (STC), and 6000

(IMP) (dwg. INS).

The EXECUTE Major State for ADD and STC is identical for both instructions during Tl.

MB02 through

MA always loaded during TPl. IF 3 and 4 are enabled (dwg. RCB)
and loaded into bits 00 and 01 of the MA to stay in the current field. Memory
strobed during T2.
are enabled (RCB) and loaded into MA.

ADD Instruction - For the ADD instruction, MEM is enabled and loaded into MB during T3 of
the EXECUTE cycle. During T4, MEM and AC are enabled and loaded into the AC to add the
contents of MB and AC, leaving the sum in the AC.
STC Instruction - For the STC instruction, AC is enabled and loaded into MB during T3 of the
EXECUTE cycle, thus storing the contents of the AC in the MB; the AC is cleared during T4.

IMP (6000) Instruction — The LINC IMP instruction is used to change program sequence, and also,
in conjunction with the LIE instruction, to change the instruction fields.

The DJR instruction is also

used in conjunction with the IMP instruction. The DJR instruction clears the SAVE PC flip-flop,

which disables PC in TS3 of the EXECUTE Major State and enables MEM. This procedure ensures
that location 0000 will not be changed when the next {and only the next) LINC-Mode JMP is used.

This operation is useful because an Interrupt may occur within a LINC-Mode subroutine that uses
location 0000 of the current IF to retain the subroutine return; therefore, it must not be destroyed.
The JMP is further decoded in TS4 of the FETCH cycle to provide X = 0 and X
0 (dwg. INS).

When X = 0, and, if the SAVE PC flip-flop is set, the next instruction is fetched from address 0000
of the current memory field. When X ^ 0, IB 00 through 04 are transferred to IF 00 through 04, by
MPG LOAD IF03 — 04 of TP4of the FETCH cycle, the IF register is loaded with the contents of the
IB register.

During the EXECUTE Major State at Tl, MA2 through
is cleared and IF 03 and 04 are loaded into
MAOO and 01. Memory is strobed in T2, and the status of the SAVE PC flip-flop determines whether
PC or MEM is enabled at T3. At TP3, with the SAVE PC flip-flop set, PC 02 through
is loaded into MB 02 through
and MB bits 00 and 01 are set with RCC SET PCO-1. At T4, the SAVE PC flip1 1

1 ,

flop is set. This accomplishes the storing of the contents of the PC + 6000 in location 0000 of the

current memory field.

The operand address of the JMP instruction is placed in the PC at T5 enabling IR 2 through

1, which

enables IF 03—04 to PCOO— 01 and loads the PC.

1.1 1.3

Index Qass Instructions

LINC instructions, with IR bits 0 and

on a zero and IR bit 2 on a one, are known as Index Class instructions.

There are four methods of addressing, called 1(5, with the Index Class instructions. The four methods are as
follows, where I = IR07,

< < 17.
j3

= 0 j3 = 0, operand address is in next location.

= 0 j3

= 1 j3 = 0, operand is in next location.

= 1 d

0, operand address is in (5 register.

0, operand address -1 in |3 register,

d register is incremented by one during instruction execution.

1-34

All four methods have identical functions in the FETCH cycle of the instruction.

cycle is entered after the FETCH cycle.

For 1

and 4 the DEFER

The signal CPS DEFER SET L is true because INS LINC INDIR H is

DEFER flip-flop is set at TPl. For

= 0, = 0 the signal SLA2 WORD FORMAT H
true,
NAND gate with output pin J1 which yields RCC EN PC 2-1 H, thus transferring the
PC to the MA at TPl. The contents of MEM are loaded into the MB at TPS and then transferred to the MA at
TPl of the EXECUTE cycle, because RCB TSl EN MB L is true and RCB EN MB 2 through 4 H and RCB EN
MB 5 through 11 H are generated.
true; therefore, the

thus qualifying the Ml 15

For I = 0, j3

0 and I = 1

0 bits 8 through 1 1 of the IR are transferred to MAOS through 1 1 and MA02

through 07 are cleared. This is accomplished with the signal INS (L INDEX * B EQ 0) L which gives RCA

ENABLE IR 08 through
H. At TPS MEM is transferred to the MB and if =
CYI CARRY INSERT L is
generated and the MB is indexed by one. The MB is transferred to the MA at TPl of the EXECUTE cycle, thus
1

giving the address of the operand.

For I = 1, P = 0 the signal SPS DEFER SET L is not true and the EXECUTE cycle is entered after the FETCH
cycle.

PC 02 through

is transferred

MA 02 through

at TPl

of the EXECUTE cycle.

The functions for Index Class instructions, except MUL, are executed at TS through T5 of the EXECUTE cycle
and are listed below;
Instruction

Octal Code

LDA

1000

Description

LoaD the Accumulator. At TPS, MEM is loaded into MB, and MB is loaded
into AC at TP4, thus loading the contents of memory into the AC.

STA

1040

STore the Accumulator. At TSS, AC is enabled by RCB (STC

•

DCA STA)
•

(dwg. RC4) and is loaded into MB at TPS for storage in memory.

ADA

1100

ADd to the Accumulator. At TPS, MEM is loaded into MB, and at TS4 MB
is enabled on one side of the adder and AC on the other; consequently, the
contents of memory are added to the AC by loading AC at TP4.

ADM

1140

ADd to Memory. At TSS, MEM and AC are enabled as shown (dwgs. RCA
and RCB) in the same manner as in the ADA instruction; however, both MB
and AC are loaded at TPS to place the summation of the memory and the

AC into the memory and AC. The FLOW flip-flop is set (dwg. FL£) if an
arithmetic overflow occurs.

LAM

1200

Link Add to Memory. For the LAM instruction the LINC, MEM, and AC
are enabled at TSS and are loaded into

struction is similar to the
to AC 1 1 via

MB and AC at TPS. The LAM in-

ADM instruction, except the LINK

enabled

CARRY INSERT (CYI).
NOTE

For the BCL, BSE, BCO, and SAE instruction, MEM is
enabled at TSS and loaded into MB during TPS.

BCL

1540

The BCL instruction is a logical AND of MB and AC. Bit Clear is decoded
by INS BCL SLA TS4 to provide an enable gate to the adder, using the
*

RCC EN BCL H. The AC is enabled by RCC BSL EN AC L (dwg.
RCA). The AC is loaded at TP4.
signal

BSE

1600

The BSE instruction is an inclusive OR between the AC and the MB. Bit
Set is decoded by INS BSE
SLA TS4 to provide an enable gate to the
•

adder, using the signal RCC EN BSE.

1-S5

The AC is loaded at TP4 (dwg. RCL).

Instruction

Octal Code

Description

640

The BCO instruction is an exclusive OR of MB and AC. BCO is decoded by
SLA TS4 H INS BCO to provide RCC EN BCL L and RCC EN BSE L.
The AC is loaded at TP4.

BCO

•

SAE

1440

Skip if the Accumulator is Equal to the operand. The SAE instruction is de-

coded by SKL AC EQ MB H • INS SAE H to provide SKL LINC EX SKIP H
to both the data and the clock input of the SKIP flip-flops.

SRO

500

Rotate and Skip. The memory is loaded into the MB and rotated one place

MB bit into MB bit 00 at T3. SRO is decoded by
SLA EX TS3 H to provide RCS EN RIGHT SHIFT H, which

to the right to bring

INS SRO H

•

1 1

is routed

to the inputs on the adders. At TPS, the SKIP flip-flop is clocked
by SKL LINC EXC SKIP H if INS SRO and PRA MBOO (0) are high.

LDH

1300

LoaD AC with Half-word. At TS3, MEM is enabled and loaded into MB to
The AC is also loaded by INS LDH L

retain the complete word in memory.

CPS EXECUTE B (1) H

•

CPTP TP3 H (dwg. RCL). At TS4, if the H flipflop is 0, RCD EN AC N- 6 R H is enabled, which is ANDed with PRA AC
•

01 (1) H to provide PMB TMSC 07.
Bit 02 is routed to

TMSC bit 8, and the process continues. The AC is loaded
AC to right-half of the AC,

at TP4, thus transferring the left-half of the

leaving the left half cleared.

When H =

AC 6-1

INS LDH H • SLA EX TS4 H

left-half with the Load

STH

1340

•

SKH H (1 ) H provide RCA EN

(dwg. RCA), which retains the right-half of the AC and clears the

AC pulse.

STore Half-word from AC. When the H flip-flop is 0, the right side of the
AC is enabled by INS STH H SKH H = (1) H (dwg. RCA) and is loaded
into the left side of the MB by TMA TMSC 00 through 05 (dwg. PMA).
RCB EN MEM 6-11 H is also enabled to retain the right- half of the word.
•

When the H flip-flop is

( 1 )

AC 6 through
is enabled by INS STH H
SKH
H and is loaded into MB. RCB EN MEM 0 through 5 is also enabled to
1 1

1 ,

•

retain the left-half of the word in memory.

SHD

1400

Skip if Half-word Differs. At TS3, MEM is enabled and loaded into MB.

When H = 0, at TP4 the right and left side of the AC are swapped by routing
1
to 0 through 5 of Processor Miscellaneous A (dwg. PMA)
and routine 0 through 5 to 6 through
of Processor Miscellaneous B (dwg.

signals 6 through

PMB).
At TP5, if INS SHD H • SKH (0) H
signal

•

-SKL ACL EQ MBL H are true, the

SKL LINC EX SKIP H is generated (dwg. SKL), setting the SKIP

Flip-flop (dwg. SKH).

The right and left half are swapped again at TP5
When H = 1, if INS SHD SKH (1) H -SKL
ACR EQ MBR are true, the signal SKL LINC EX SKIP is also generated,
setting the SKIP flip-flop at TP5.
to provide the original word.

DSC

1740

•

MEM

Display Character; at TS3,
is enabled and loaded into MB. If the
display is busy, the T5 timing chain is inhibited by -CPT EN INT PAUSE H
(dwg. CPTP), which is set low by DSC BUSY (dwg. CPT).

DSC BUSY
CPTP TP3 also direct-sets the INTERNAL PAUSE flip-flop. When DSC

•

BUSY goes low, -CPT EN INT PAUSE is high and initiates the T5 timing
chain, thus clearing the INTERNAL PAUSE flip-flop at the generation of

1-36

Instruction

Octal Code

Description

DSC

the next OFF PAUSE pulse.

(Cont)

into the intensification register (dwg. DSf) by DSC LD IN H, (dwg. DSQ.

When the display is not busy, MB is loaded

The AC is loaded into the vertical register (dwg. DSY) by DSC LD VERT H.
The VERTICAL flip-fiop VA7 and VA8 (dwg. DSQ and VA9 and VAIO
(dwg. DSY) are cleared at T5 by DSC INITIALIZE L to provide automatic

The HORIZONTAL flip-fiop HA9 is direct-set, and HA 10 is direct-

spacing.

cleared by DSC INITIALIZE L to move four points over from the starting

point of the display. The EXEC 2 Major State is now entered by CPS
EXECUTE B (1) H SLA (DSC SET) H (dwg. CSP).
•

•

At TPl of the EXEC 2 Major State, the MA is set to a one by CARRY INSERT,
which is enabled by CPS EXECUTE (1) H INS DSC H CPT TSl (1) H,
•

•

to obtain the next address at address 0001 of the current field for the hori-

zontal axis. At TP2, the AC is incremented by 30g (bits 07 and 08 are set to 1).
1). This is done by signals PRD AC 07 (1) L
DSC SIZE (1) L, which provide
PMB TMSC 07 H, and signals SLA DSC CNT MB H PMA SIZE ( 1) H,
which provide PMB TMSC 08 H. The two resulting signals are routed to the
*

•

enable gates of the adders. For half-size characters, 14g (bits 08 and 09) is
added to the AC by enabling PMB BMSC 08 and PMB BMS 09 H.

For full-size characters, at T3 the summation of MEM and lOg (bit 08 = 1)
is

enabled by RCA SET AC H and provides PMB BMSC 08 H. The sum-

CPTP TP3 H (dwg. RCL). For half-size
RCA DSC SET AC H
DSC SIZE 0 H. At T5, the VERTICAL flip-flops V8 through 1 (dwg.
DSY) are zeroed by DSC LD VTL and DSC CLR V8-1 L, which are
enabled by CPT TS5 B (1) H SLA (DSC EXECUTE 2) H (dwg. DSQ.
The DSC ACTIVE flip-flop is also set by DSC LD HORZ H. The CP
timing can now continue with another timing cycle while the timing chain
(dwg. DSQ is started to complete the DSC instruction. The DSC instrucmation is loaded by -INS SET H

•

characters, PMB BMSC 09 H is enabled by

•

tion and the associated circuitry are described in further detail in the

Display Control section of Chapter 5.

MUL

240

The contents of the AC (multiplicand) are MULtiplied by the contents of
the register Y (multiplier). The product is left in the AC and the MQ; the
sign of the product appears in the LINK and ACq

At T3, MEM is enabled (dwg. RCB) and loaded into the MB by CPTP TP3 •
-INS SET, causing the multiplier to be loaded into the MB. The downcounter (IR bits 08 through 1 1 ) are zeroed by CPTP TP3 • SLA (MUL •

EXECUTE) H (dwg. INR). At T4, the multiplicand is checked for the sign
by checking AC bit 00. When AC bit 00 = 0, RCS EN AC TO MQ H
loads AC into the MQ, and the sign bit is placed in the LINK for future
reference by signal INS MUL GO
RCS EN AC TO MQ H. When AC
bit 00 =
RCS EN — AC TO MQ H loads AC into the MQ, and the LINK
is set to 1. The RECYCLE SYNC flip-flop (dwg. CPT) data input is set
high by SLA (MUL EXECUTE TS4) L, and CPTP 5 H clocks the flip-flop.
The RECYCLE SYNC flip-flop is set, and high signal is sent to the data input of the T5 RECYCLE flip-flop, which is clocked 50 ns later by CPTP
OFF PAUSE. The T5 RECYCLE is initiated. For the duration of the MUL
instruction, T5 RECYCLE remains set, resulting in repeated generation of
•

•

the T5 timing chain (dwg. CPTP).

1-37

Instruction

Octal Code

Description

MUL

MB is now loaded into the AC to check the sign. In the down counter, IR

(Cont)

bits 08 through

are set to 1 for a value of 17g

The IR is set to 17 by signals SLA MUL GO H

•
-INS N EQ 01 H, which
produce INR COUNT ENAB H (dwg. /NR). INR COUNT ENAB H is used

INR IR
(0) H sets bit 11, INR IR 0 H sets
INR CARRY 10 L sets bit 09, and INS N EQ 00 sets

to enable the four IR bits.
bit 10, INR IR 09
bit 08.

•

This N counter is decremented at the occurrence of the TP5D pulse.

When N =

If the AC bit 00 = 0,
MB and AC simultaneously; the
LINK remains unchanged. If AC bit 00 = 1, RCC T5 COMP AC L is used to
load AC into MB and AC simultaneously, and the LINK
complemented.
When N = 6, the AC is cleared, because contained the multiplier from
1

7, the sign of the multiplier is checked.

the AC is enabled and loaded into the

the previous operation and it must be 0000 initially when the multiplication

begins in the next cycle.

The down counter is again decremented.

Multiplication begins when

N = 15; the AC

always enabled by

SLA MUL ADD L CPT TS5. The MB is also enabled when MQ bit
= 0
by SLA MUL ADD H MQR MQ (
H. RCS EN MQ SH RIGHT H is also
•

1 1

•

)

N = 5 until N = 3, and the AC is loaded at every TPS. The
AC is loaded into the AC and shifted right one place
= 0, and the summation of MB and AC is loaded into
whenever MQ bit
AC and shifted right one place whenever MQ bit
=
The partial product
of AC bit
is moved into AC bit 00, and the MQ is rotated right one place.
This operation is repeated ten times from N = 5 to N = 3.
activated, from

result is that the

1 1

When N = 2, the AC is left unchanged by loading AC into the AC for a
fractional multiplication indicated by H = 1 or MQ is loaded into the AC
and shifted right one more place for an integer multiplication indicated by
H = 0. When N = 1 the AC is left unchanged by loading AC into AC if the
,

LINK = 0, or the AC is complemented if the LINK =

The RECYCLE
SYNC flip-flop is cleared and, at the next OFF PAUSE pulse, T5
RECYCLE is cleared initiating another Major State.
1.12

a CLASS INSTRUCTIONS

There are three a class instructions; SET, DIS, XSK; each instruction uses registers 0000 through 001 7 in a
unique way. The following paragraphs contain a brief description of the instructions and a detailed description
of the flow diagrams associated with each instruction.

a = 0 < a < 17

1.12.1

SET Instruction 0040

-i-

1 -i-

Set the contents of memory register a equal to the contents of memory register Y.

ADDRESSING FOR SET:
I
a
Y
0
0</3< 17
Y(P-H)
0</3<17
P-H
1

For I = 0, the DEFER state is entered after the FETCH state. CPS FETCH (1) H * INR IR 07 (0) H * INS
SET H are true, making CPS DEFER SET L true. The operand address is loaded into the MB at TP3. The MB

1-38

is
I

transferred to the MA at TPl of the EXECUTE cycle, and the operand is loaded into the MB at TP3. When
= 1, the MA is loaded with the contents of the PC at TPl of the EXECUTE cycle and the operand is loaded

into the

MB at TP3.

The EXEC 2 state is always entered for the SET instruction. CPS EXC 2 SET L is true at TPl thus enabling
,

the data input to the flip-flop. At TPl, bits 8 through 1 1 of the IR are transferred to
bits 2 through 7 are cleared.

IF 3 and 4 are loaded into MA 0-1

MA 8 through

retaining the same memory bank.

and MA

The RCL

LOAD MB L pulse is inhibited for this cycle; therefore, the contents of the MB are written into memory at TP3.
1.12.2

XSK Instruction (Index and Skip) 0200 + I + a

At TPl of the EXECUTE cycle, the a register IR08-1 1 is loaded into the MA 8 through

1, MA 2 through 7 are
MA 00 and 01. The a register strobed at TP2, and at TP3 MEM
loaded into MB for = 0; MEM is incremented by CARRY INSERT for =
and loaded into the MB. At TPS,
if the Skip condition is met, PRA CARRY 02 H is generated and
ANDed with INS XSK H (dwg. SKL). This

cleared, and the current field is loaded into

signal provides

1.12.3

SKL LINC EX SKIP, which sets the SKIP flip-flop.

DIS (Display) 0140 + I + a

A point is intensified on the display with the horizontal position specified by bits 3 through

of the a register,

and the vertical position specified by bits 3 through 1 1 of the AC. The EXECUTE cycle is always entered after
the FETCH cycle for this instruction.

MB 00 is loaded into the channel flip-flop at TPS to select one of two

channels. If the display has not completed the previous display instruction, the signal CPT EN INT PAUSE L is
true and the CP timing will pause in time state 5 (CPT TS5 (1)) until DSC BUSY becomes false. This allows TPS

to occur and the necessary load pulses are generated to perform the display.

The M71 1 Scope Control Module

generates all the clock and load pulses to complete the instruction.

DSC INITIALIZE L is the first pulse generated, yielding the DSC LD VERT H, DSC LD HORZ H, and DSC SET
IN 1

L pulses. The DSC LD HORZ H pulse starts the 2S ms setup delay and sets the ACTIVE flip-flop. When

the delay has timed out an intensify pulse (DS CINTEN) is generated, and the ACTIVE flip-flop is cleared, thus
signifying the completion of the display.

The following instructions are not a class instructions; however, they are used in conjunction with memory and,
consequently, will be discussed here.
Instruction

Octal Code

Description

LIE

060600+N

0 < N < 37. This instruction sets the instruction field to the value “N”.
It is utilized in conjunction with the

LINC JMP instruction - the LIE in-

struction loads the IB register with the value “N”, and the next LJMP instruction transfers the IB to the IF register.

The LIE signal is ANDed with

CPTP TP4 to give MPG LINC SET L, which generates the Load IB pulse.
The LINC SET pulse also generates a MPG LOAD SFL pulse, which transfers the contents of the IF to the save field register.

LDF

0640+N

0 < N < 37. This instruction loads the data field register with the value N.
This signal LDF is gated with CPS FETCH (1) and CPTP5 to generate

MPG LINC SET DF L. This pulse clocks DF03 L4 and also generates

MXF LOAD DFO-2 H.

1-39

1.12.4

SAM 0100+N (0 < N < 37)

The SAM instruction samples one of 32 channels, and converts the analog voltage on that channel to a ten-bit
binary number that is contained in the AC at the completion of the instruction. This is a single-cycle instruction;

however, to allow sufficient time for the conversion, the timing chain is recycled in TS5 when the fast sample
option is not selected.

The SAM level is decoded at TS4 and is ANDed with YAD A-D PAUSE (

and YADC FAST SAM (0). When
YADC A-D RECYCLE L is generated and the CPT RECYCLE SYNC flip-flop is set
of the IR are loaded into YADC IR 07-1 at TP4 to select the channel. YADC LOAD A-D IR
1

)

these three signals are true,
at TP4.

Bits 07-1 1

also initiates a 6 ^s delay to allow the analog voltage to settle and, at the completion of the delay, the

conversion

YADC START pulse. The YADC DONE pulse is generated when the conversion is complete
and the YADC A-D PAUSE flip-flop is cleared. This disables the YADC A/D RECYCLE level; the RECYCLE
is

started with the

SYNC and T5 RECYCLE flip-flops are also cleared with the next TPS pulse. The AC is loaded with the contents
of the A/D register at every TPS; thus, the final converted number is transferred with the last LOAD AC pulse.

1.13

MISCELLANEOUS INSTRUCTIONS

MSC Instructions — This LINC-Mode instruction set contains single-cycle Operate instructions similar to the
8 Mode. The instructions are classified MSC on LINC FETCH lA (dwg. D-FD-PDP-12-0-12) and are labeled
N = 0 through N = 7. The MSC signal is true when IRO-6 are on a zero. The operations of the MSC instructions
1

are as follows:

N = 0 performs a HLT (0000). The RUN flip-flop is cleared (dwg. CPR) by INS MSC H
CPS FETCH ( ) H and TPS.

00 H
b.

INS NEQ

I-bit.

•

is used to decode an AXO (0021) or XOA (0001) instruction, depending
on the state of the
This instruction is discussed in the LINCtape processor chapter.

N = 2 (0002) is used to perform the PDP instruction. The PDP instruction changes the MODE flipflop to 8 Mode (dwg. CPR). The instruction is executed by CPTP TPl H
INS MSC H INS NEQ
•

•

02 H.
d.

N = 3 is used to perform the TAC or the TMA instruction. This instruction is discussed in Paragraph
6.6.1

(LINCtape Control).

N = 4 and I = 0 are used in conjunction with AC bits 2 through 7 to decode an ESF (0004) instruction.
(1)

(2)

ESF and AC bit 2 ( 1 ) set the TRAP flip-flop (dwg. CPS), which allows the use of LINC-8 programs or other undefined instructions (refer to Paragraph 1.19).
ESF and AC bit 3 (1) set the TAPE TRAP flip-flop (dwg. RCD), which allows the user to inhibit all tape instructions and interrupt the main program when the

(3)

EN TRAP flip-flop is set.

ESF and AC bit 4(1) sets the DSC SIZE flip-flop (DSC) for half-size characters to be displayed on the VR12.

( 4)

ESF and AC bit 5 ( ) sets the YADC FAST SAMPLE flip-flop (YADC) for the Fast Sample
mode of analog inputs.

(5)

ESF and AC bit 6 (1) sets the ENABLE TELETYPE INTERRUPT flip-flop (dwg. RCA) to

disable the program interrupt when the Teletype flag is set, even if the interrupt facility is

enabled.
( 6)

ESF and AC bit 7 ( ) generates an I/O preset to clear all device flags.
1

1-40

N = 4 and

= 1 are used to decode and execute the SFA (0024) instruction.

decoded by INS MSC H

•

INR IR 07 (1) H

•

N = 4 and I = 1 are
INS NEQ 04 H to produce RCA EN LD MSC 4.

This instruction places the contents of the special function flip-flops into the

AC. AC bits 0
through 1 and 7 through 1 1 are cleared. This instruction is used to check the status of
the special
functions register.
g.

N = 5 is decoded into a QAC (0005) instruction. The contents of MQ 0 through 10 are placed
in AC
through 1, and AC 0 is cleared. The instruction is executed by SLA (MSC TS5)
INS EQ 5 H to provide RCC EN MQ H. AC is then loaded by INS N EQ5 L (dwg.
RCL). RCC
EN MQ and CPR L Mode provide RCS EN SHIFT RIGHT H.
1

•

N = 6 (0006) is decoded into a DJR instruction which direct-dears the SAVE PC flip-flop
(dwg. RCD). The DJR instruction has been discussed in conjunction with the IMP
instruction.

N-

decoded into a CLR (001 1) instruction. The AC is cleared by disabling the register bus

and loading AC, using the signal INS EQ 1

MSC H
/.

•

INS N EQ

L (dwg. RCL). The LINK is cleared by signal INS

H (dwg. FLK), and the MQ is cleared by loading MQ (dwg. RCL).

N = 14 is used for an ATR (0014), AC to Relays instruction. The contents of AC 6 through
are transferred to the relay buffer.

The instruction is decoded by INS MSC H

•

INS NEQ 14 H

•

CPTP5 H (dwg. /OR) to provide the signal lOR LOAD RELAY L that clocks the RELAY BUFFER
flip-flops.

RTA (0015), Relays to AC instruction. The contents of the relay buffer
AC 6 through 1. The instruction is decoded by signal SLA (MSC TS5) L
and INS NEQ 15 L to provide the signal RCD EN RELAYS H (dwg. RCD). The side of the
RELAY flip-flops is routed through processor miscellaneous B gates, and the AC is loaded by the
signal N EQ 5 L and CPTP TP5 (dwg. RCL).
1

5 is decoded into an

are transferred into

•

N = 7 is decoded into COM (0017) complement the Accumulator instruction. The instruction is
decoded by SLA (MSC TS5) H INS NEQ 17 H to provide the signal RCC T5 COMP AC L.
1

•

AC is loaded by the signal INS NEQ
1.14

The

7 and CPTP TP5 (dwg. RCA).

SHIFT AND ROTATE INSTRUCTIONS

The Shift and Rotate instructions in the LINC Mode are ROR, SCR, and ROL. The operations for
all these instructions are identical for TSl through TS3 in the LINC FETCH cycle.
shifted or scaled “N” places.

At T4 of FETCH

The contents of the AC and MQ are

< N < 17).

N is examined for 0. If N = 0, no operation is performed, and the CP proceeds to fetch the

next instruction.

When N ^ 0 and either ROR, ROL, or SCR is decoded, signal SLA L ROTATES is produced (dwg. SLA).

SLA L
ROTATES produces the signal INR COUNT ENAB H which is ANDed with TP4, to direct-set the RECYCLESYNC flip-flop (dwg. CRT). CPTP OFF PAUSE is generated (dwg. CPTP), 50 ns after TP4, which sets the T5
RECYCLE flip-flop.
The following list is a description of LINC Mode Shift and Rotate instructions:

ROR (030 n)

The contents of the AC and the MQ are Rotated to the Right N places.
At TS5, AC is enabled by SLA ROTATES (dwg. RCA). SHIFT RIGHT
enabled by SLA (ROR
SCR) and CPT TS5 B (1) H. RCL LOAD AC H
and RCL LOAD MQ H are generated at CPTP5. The Link is included in
is

the shift when IR bit 07 =
to LINK (dwg. FLE).

1-41

(dwg. FLK).

ADDER bit

rotated back

SCR (034 n)

The contents of the AC and the MQ are Scaled Right N places. The sign bit

AC is enabled and rotated into the MQ

(contents of ACCO) is not changed.

in the same manner as accomplished in

If I =

Link is not changed.

ROL (024 n)

ACl

the

ROR instruction. If

is shifted

= 0 the

into the Link.

the Link is
The contents of the AC are Rotated to the Left N places. If 1 =
The AC is enabled (RCB) by SLA ROTATES and loaded
shifted into the ACl
at CPTP TPS. RCS EN SHIET LEFT H is enabled by INS ROL and CPTP TPS H
1

FLE LOW END SHIFT IN is enabled by the ROL instruction

(dwg. RCS).

IR 07 (0) and AC 00 (0).

1.15 SKIP INSTRUCTIONS

The Skip instructions are one-cycle instructions. When the Skip condition is true and IR 07 = 0, the SKH SKIP
the inverse occurs: the SKIP flipflip-flop is set and the next sequential instruction is skipped. When IR 07 =
1

flop is set when the Skip condition is not true.

The Skip instructions in the LINC Mode are SXL, SNS, SKP, APO, AZE, LZE, QLZ, and FLO.

SXL (040 n)

Skip On external Level, N. The external levels for SKL X SENSE L associated

with the SXL instructions are shown on the SKL print. The AND/OR combination Ml 41

Module at location K37 (dwg. SKH), decodes the XL levels.

The following Skip conditions are decoded by INS SKP and NEQ 0 through 05 and N EQ 11, 12, 14, 15 and 16
(dwg. SKH), Each of these gates when qualified produces the signal SKL I SENSE L, which sets the SKIP flipflop.

SNS (044 n)

SeNse Switch inputs CSI SNS 00 through 05 are ANDed with INS N EQ 00 L
through 05 to provide SKL I SENSE L.

SKP (0456)

SKP unconditionally. When this instruction is executed, the SKL

SENSE

level is always true.

APO (0451)

Skip if Accumulator is Positive by testing the contents of AC bit 0. This
instruction is decoded by INS N EQ 1 1

AZE (0450)

•

PRA AC 00 (0) H (dwg. SKL).

SKH AC EQ 0 L and -CYI CARRY
OK L are ORed together and the output signal is ANDed with INS N EQ 10
Skip if Accumulator is 0000 or 7777 (-0).
to provide SKL I SENSE L.

LZE (0452)

Skip if the Link is 0. The LINK bit is ANDed with N = 1 2 to generate SKL I

SENSE L.

FLO (0454)

Skip if the Flow flip-flop is set. This instruction is executed by FLE FLOW (1)

H
QLZ (0455)

•

INS NEQ 14 (dwg. SKL).

Skip if MQ

MQR MQ

= 0.

(0) H is ANDed with

5 to generate

SKL SENSE L.
I

1.16

OPERATE INSTRUCTIONS

1.16.1

lOB

lOB is decoded with INS lOT L by INS LOPR H

•

INS N EQ 00 H

•

CPS EXECUTE (1) H.

permits one 8-Mode lOT instruction to be executed after the lOB instruction is given.

Tlie lOB instruction

The octal code for the

lOT instruction is located in the next sequential memory location.
The INS lOT level is generated by ANDing the signals INS L OPR H, INS N EQ 00, and CPS EXECUTE (1).
The CPT lOT PAUSE flip-flop is set by CPTP TP4 and lOT, and the I/O timing chain is initiated. The lOT
timing is shown in Figure 1-10.

lOT TIMING

TP 4 (H)
lOT PAUSE

mil

II II

1500

II ll II II

2000

ill Ml INI ll

2500
1

3000

M III II II

_ri
J

(H)

lOP SHIFT (L)

TP 5

1000

500

lOP SHIFT (H)

u
m

rfi

1
1

OFF lOP (H)

lOP CLOCK (H)

1
1

n
1.

lOP SAMPLE
lOP

lOP 2
lOP 3

lOP's (H)

10 STROBE (H)

J lOP 1F MB9
800 ns
1

(

laBOOns

J I0P4IF MB IK
s:

(e.9.w/N0T

)

800 ns

TL_
NORMALLY

JlOP2 IF MBIO(l) L

1)»

TL_
lOT ON NEXT 10 CLOCK

AN lOT) TP5=1— TS1

(t) (H)

Figure 1-10

lOT Timing

The logic for the lOP generator consists of a re-entrant delay chain which generates three time states. These time
states are gated with

MB bits 11, 10, and 9 to generate lOP

lOP 2, and lOP 4 respectively. CPTP5 and CPT

lOT PAUSE ( ) generate IOC lOP SHIFT. The leading edge of the shift pulse sets lOP FF
1

sets 10 SAMPLE.

and the trailing edge

Approximately 500 ns later, I/O STROBE is generated if lOB 11 = 1. This pulse is used to

IOC OFF lOP is generated approximately another 200 ns
IOC 10 CLOCK is generated another 100 ns later, this pulse restarts the timing

generate the load pulses to load data from the I/O Bus.
later and clears IOC lOP SAMPLE.

generator if lOT PAUSE = 1. The next SHIFT PULSE sets IOC lOP FF2 and clears lOP FFl.

The timing

sequence continues for two more timing cycles. The signals IOC OFF lOP H and IOC lOP 3 (0) clear CPT lOT

PAUSE, terminate the lOT instruction, and allow the CP to enter the FETCH Major State.
1.17

RSW INSTRUCTION

The RSW instruction (0516) places the contents of the RIGHT SWITCHES into the AC. IR bits 0 through 5 are
decoded to yield INS LOPR H. INS LOPR H is gated with CPT TS5 B (1) H to produce SLA (LOPR

which is ANDed with INS NEQ 16 to enable RIGHT SWITCHES 0 through

1.18

•

TS5) H,

The AC is loaded at TP5.

LSW INSTRUCTION

The LSW instruction (0517) places the contents of the LEFT SWITCHES into the AC. SLA (LOPR
gated with INS N EQ 1 7 H to enable LEFT SWITCHES 0 through 1 1. The AC is loaded at TP5.

•

TS5) H is

1.19 LINCtape INSTRUCTIONS

LINCtape instructions are two-word format instructions. These instructions include RDE, RDC, RCG, WRI, WRC,

WCG, CHK, and MTB. Other LINCtape-oriented instructions include Skips (STD, TWC, IBZ, STB, and LMR) and
Operate instructions (AXO, XOA, TAG, and TMA). For a more detailed discussion of LINCtape instructions, refer to Chapter 6.

TRAP INSTRUCTIONS AND INTERRUPT
When an INTERRUPT occurs and the CP is in the LINC Mode (if the EN TRAP flip-flop is not set), 0040 is
loaded into the MA by enabling PMB TMSC 06 H. PMB SET INT ADD L is true, giving PMB TMSC 06 H.
When the ENABLE TRAP flip-flop is set, PMB TMSC 06 H and PMA BMSC 05 H are both enabled and loaded
into the MA, thereby loading location 0140 into the MA. PMA BMSC 05 H is enabled by CPS TRAP L and PMB
1.20

SET INT ADD L.
The instructions that can be trapped and their codes are listed below:

Code

Instruction

0501-0515

Operate 01-15

0521-0535

Operate 01-15 (1=1)

0700-0737

LINCtape operations when TRAP and EN TAPE TRAP flip-flops are set

0740-0777

EXECUTE

0540-0577

Undefined

1700-1737

Undefined

1.21

Of these instructions, two are unique: 1700 and

720. If these instructions are trapped to 140g

the return

jump in location 140g is incremented twice instead of once, because these instructions are I-j3 class instructions.

ENGINEERING DRAWING DESCRIPTIONS
The name of each block schematic has a unique three-letter code (i.e., CIN RCA). The name of all the signals
generated on that particular print are prefixed with this code.

1.21.1

Console Indicators (D-BS-EP12-0-CIN)

The connectors shown on this drawing are single-width modules with the A side at the top of the drawing and
the B side at the bottom.

The signals shown on this drawing are connected through cables to the console indi-

cator panel.

1.21.2 Central Processor Run (D-BS-EP12-CPR)

The MODE and RUN flip-flops and their associated logic are contained on this drawing. The MODE R/S flipflop comprises two M617 NOR gates and is set to 8 Mode when power is turned on. The
MODE flip-flop may
be changed by a manual switch or under cornputer control.

The RUN flip-flop must always be set to generate computer timing. The RUN flip-flop is direct-set with either
of the following key functions (FILL, EXAM, FILL STEP, and STEP EXAM) START

20, 400, and LSW.

1.21 .3 Central Processor States (D-BS-EPl 2-0-CPS)

The logic for the nine Major States is contained in this drawing. Only one state can be entered at TPl
the major control signals is Get Next Instruction (GNI).

One of
GNI is controlled by inhibit logic and must be true to

1-44

enter a FETCH cycle. A FETCH cycle can be inhibited, however, by a Tape Break, Data Break, or an
INTERRUPT request. The Tape Break has priority over all BREAK and INTERRUPT States. The Data Break

has the second highest level of priority and is controlled by the BREAK SYNC flip-flop.

The INTERRUPT

has the third highest priority level and is controlled by the INTERRUPT SYNC flip-flop.

1.21.4 Central Processor Time States (D-BS-EP12-0-CPT)
Elip-flops TSl through TS5 and logic for T5

RECYCLE are contained on this drawing, as well as the INTERNAL

PAUSE and lOT PAUSE flip-flops. Two more flip-flops that are necessary for the generation of time states
CYCLE DONE and MEM IDLE are shown on this drawing.
The TSl through TS4 flip-flops are cross-coupled NOR gates. TS5 is direct-set by TP4 and can be controlled by
the T5 RECYCLE flip-flop and TPS.

The T5 RECYCLE flip-flop is set only when the RECYCLE SYNC flip-flop is true. The CYCLE DONE and

MEM IDLE flip-flop have to be set to start another timing cycle. The CYCLE DONE flip-flop is set by MFTP2
and CFTP SET CYCLE DONE. The MEM IDLE flip-flop is set by I/O PRESET, and MCT MEM DONE.
1.21.5 Central Processor Time Pulses (D-BS-EP12-0-CPTP)

The generation of all time pulses is depicted in this drawing. The timing chain is started off by the occurrence

MEM IDLE flip-flops have to be set. TP2 is the result
of a STROBE signal from memory when EN MEM is set or is generated approximately 350 ns after TPl when
of TPl.

To generate TPl

the RUN, CYCLE DONE, and

EN MEM is cleared. The time pulses are generated from TPS to TPS, independent of the memory or the time
states.

1.21.6 Console Switch Inputs (D-BS-EP12-0-CSI)

The logic for all console switch inputs is found on this drawing. Switches that have similar functions are ORed
together before they are routed to an Ml 1 1 Inverter.

CSI KEY STARTS.

The Key Start switches are ORed to provide a single output

A similar procedure is followed for KEY FILL, FILL STEP, EXAM, and STEP EXAM to

generate CSI (EILLS + EXAMS).

1.21.7 Console Starts (D-BS-EP12-0-CST)

Manual function states are generated in M700 Module. Manual time pulses are generated whenever any one of
10 keys is depressed on the console control panel. Each switch is routed to a filter and a Schmitt trigger to
generate METSO. Manual timing proceeds automatically through the delay lines.

The input at KP2 must be true

to initiate the manual function states, and timing which controls the start of the memory Read/Write cycle.

The DO flip-flop is used to perform one instruction at a time.

It also clears the EN MEM flip-flop. The FILL
STEP flip-flop is direct-set when the PILL STEP key is depressed; the PILL STEP flip-flop is cleared at TP5D,

at which time the

STEP EXAM flip-flop is set, because the Fill Step function is followed by a Step Exam function.

The AUTO flip-flop allows the STEP EXAMS, PILL STEPS and DO functions to be repeated at a time rate determined by the delay of the manual control knob AUTO RESTART DELAY on the A/D panel.

1 .21 .8

CARRY INSERT (D-BS-EPl 2-CYI)

The signal CARRY INSERT is connected to adder bit 1 1 and is used to increment the major registers. All the
logic to generate CYI

CARRY INSERT L

shown on this drawing.

The four registers that can be incremented are MA, PC, MB, and AC.

1.21.9

Flow and End Shift (D-BS-EP12-FLE)

The logic for the FLOW flip-flop, High-End Shift and Low-End Shift, is contained on this drawing. The FLOW
flip-flop is used to indicate Overflow from

AC bit 00 when doing an arithmetic operation in LINC Mode. The

FLE HIGH END SHIFT IN H is connected to adder bit 0 and is used for ROTATE RIGHT instructions.
The signal FLE LOW END SHIFT IN H is connected to adder bit
and is used when doing ROTATE LEFT
signal

instructions.

1.21.10

LINK Logic (D-BS-EP12-0-FLK)

The logic for the LINK flip-flop is contained on this page. The LINK flip-flop is an extension of the AC. When
a

CARRY OUT occurs out of AC bit 00 during a 2s complement addition, the LINK is complemented. It can

be set or cleared independently of the AC under 8-Mode control, and may be included in shifting and rotating
operations performed on the contents of the AC.

K09 and the NOR gate M 60 at location J
1

1.21.11

I/O and EXT

The LINK adder is comprised of a M

1 1

Inverter at location

MEM Cables (D-BS-EPl 2-0-ICB)

The cable connections N14 through N18 shown on this drawing are used to interface external I/O devices to
the computer. Cable connections N20 through N24 are used in conjunction with the

MM 8

-A or -B Extended

Memory. Cable connection N13 is used to sense external levels.

1.21.12 Instruction Register (D-BS-EPl 2-0-INR)

The instruction register and its associated logic is contained on this drawing. The IR is direct-cleared when the

NAND gate M617 at location H38

qualified.

Flip-flops IROO through IR2 are direct-set by I/O PRESET to

ensure that the first random instruction in the IR is not CHANGE MODE when power is turned on. The IR is

connected to the register bus and is normally loaded during FETCH. IR bits 08 through 1 1 (N bits) are used as
a down counter for

MUL instructions and LINC ROTATES. Instruction register bit 07 is called the

bit for

LINC Mode addressing and LINC instructions.
1.21.13 Instructions (D-BS-EPl 2-0-INS)
This drawing shows the major decoding of instructions and associated logic. Decoding is accomplished by binary
to decimal decoders.
this drawing.

By grounding pin Ul, only binary-to-octal is decoded. Seven Ml 61 Decoders are shown on

Only one decoder is used to decode 8-Mode instructions.

1.21.14 I/O Input Part A (D-BS-EPl 2-10 A)
Inverters for signals from the External I/O Bus are shown on this drawing. The Internal/External I/O Bus is
shown on the right side of the drawing and comprises MS 16 Modules in locations M17 and Ml 8.

1.21.15 I/O Input Part B (D-BS-EPl 2-O-IOB)
State signals from external peripheral devices are shown here. These signals request a function from the CP or

modify the operation of the program. The three signals EXT DAO-2 select the extended memory fields for Data
Break devices. The 1 2 XL signals XLO-XLl 3 are external skip levels for the LINC SXL instruction.

1-46

1.21.16 I/O Control and Timing (D-BS-EPl 2-IOC)

The I/O timing chain is shown on the bottom of the drawing. lOP control pulses are generated by the logic on
this drawing and routed to peripherals.

flops INTERRUPT

Interrupt control is shown on the top right side of drawing.

The flip-

ENABLE and INTERRUPT DELAY allow the processor to finish the current instruction

before recognizing the interrupt. The logic for the three-cycle Data Break control is shown on the top left comer

of the drawing.

Word Count Overflow indicates that data transfer is complete. Address Accepted indicates that

the computer has acknowledged the Break Request.

1.21.17 I/O Buffers (D-BS-EPl 2-0-100)
All the output signals are buffered before going onto the I/O cables.

These signals are used for both data and

synchronization pulses for the I/O devices.

1.21.18 Relay Buffer (D-BS-EPl 2-0-10 R)

The logic to control the relays is shown on this drawing. Relay register bits 00 through 05 are loaded with AC
bits 06 through

when the ATR instruction is executed. The ATR instmction is decoded by a NAND gate

Ml 15, to generate the lOR LOAD RELAYS pulse.
1.21.19 Interprocessor Cables (D-BS-EPl 2-0-IPC)

The cables shown on this drawing connect the memory and the Central Processor.

1.21.20

MEM EXTN AC Inputs (D-BS-EP12-0-MEA)

The logic on this drawing shows the extended memory I/O Bus. The instmction RDF is decoded by the NAND
gate Ml 17 at location L24, and

1 .21 .21

RMF is decoded by NAND gate M617 at location L05.

MEM PAGE EXTN Control (D-BS-EPl 2-0-MPG)

The control logic for LINC fields is shown on this drawing. Under normal operating conditions the IB and IF flipflops are set identically.

When a LIF instmction is decoded, the IB flip-flops are set to contain the new field re-

quested and the Save Field (SF) flip-flops are loaded with the contents of the IF and DF flip-flops. The fields are

not changed, however, until the next JMP Y instruction (Y

0000) is executed. When the JMP (Y

0000) is

executed, the new field is clocked into the IF flip-flops from the IB flip-flops.

1 .21

.22

MUL Quotient (D-BS-EPl 2-0-MQR)

The MQ register and associated logic is shown on this drawing. The MQ is loaded only from the AC and is used
as an extension of the

AC when doing ROTATE instmctions and for the KE12 Option. The MQ also contains

the least significant bits of the partial product when performing a

MUL instruction.

1.21.23 Processor Miscellaneous A and B (D-BS-EPR-O-PMA, PMB)
Eight extra enable gates to the adder are provided on these two drawings for bits 00 through 12.

The enable

gates accommodate I/O Bus, A/D, Display, Tape, Relay, and any miscellaneous signals for transfer to a main
register.

1-47

1.21.24 Processor Register Bits 0 through 1 1 (D-BS-EP12-0-PRA through PRF)

The logic on these drawings shows six M2 21 Main Register Modules and additional gating. Each module handles
two bits of each of the four registers (AC, MB, PC, and MA). There are two inputs to the adder; each is connected
to an

AND/NOR combination enable gate. Each adder is connected to the next higher order adder by CARRY

OUT, and to the lower order adder by CARRY IN. Adder outputs combine with the shifting logic to enable or
disable major registers through the register bus.
is routed

Comparator logic is also provided between AC and MB, which

to the Skip logic.

On the PRA drawing, the AND/NOR gate Ml 60 at location HI 3, and the NAND gate M627 location J14 inhibit
the adders from indexing beyond bit 2 in LINC Mode.

PRA CARRY IN 01 H is connected to the Carry input of

bit 01.

1.21.25 Register Control A (D-BS-EPl 2-0-RCA)

The enable logic for the AC is contained on this drawing. The AC can be enabled in separate halves for half-word
instructions.

The enable logic for the IR is also contained on this drawing. Depending on the instruction being

executed, IR02-07 or IR08-1 1 is enabled.

1.21.26 Register Control B (D-BS-EPl 2-RCB)
This drawing contains enable logic for MA, MB, MEM, IF, and DF.
are divided into sections to facilitate the various instructions.

The enable levels for the MA, MB, and MEM

Sometimes only specified bits are required for a

transfer between registers.

1.21.27 Register Control C (D-BS-EPl 2-0-RCC)

The enable logic for the PC, MQ, and the AC COMPLEMENT are shown on this drawing. Other Miscellaneous
functions are also enabled on this drawing.

The complement of the AC is usually enabled at TS5, except for an

8-Mode Complement AC instruction. The entire PC is normally enabled in 8 Mode. In LINC Mode, PC02
through 1 1 are enabled because PC 00 and 01 contain the current field. The logic to enable the MQ is found on
the right side of the drawing.

The enable gating for a BIT CLEAR and BIT SET is also shown.

The signal RCC EN I/O BUS H is shown on this drawing, and the signal routed to the T MSC logic.
1.21.28 Register Control D (D-BS-EPl 2-0-RCD)

Enable logic is shown for the following signals.
a.

RCD EN A D H — this signal is routed to B MSC to provide the inputs for the A/D register.

EN AC N-6 L and EN AC N-6R — these signals are used for half-word operations.

EN RSW - this signal is routed to the enable gates (dwgs. PRA through PRF). It enables
the 12 right console switches onto the register bus.

RCD EN DATA ADD — this signal is routed to the inputs to main registers. It enables the
external address lines during a break request.

RCD EN TAPE BUS - this signal enables the tape bus and is routed to MBSC.

The Save PC flip-flop and TAPE TRAP flip-flops are also shown on this drawing. Both flip-flops are controlled
by Miscellaneous instructions, as explained in Paragraph 1.13.

1-48

1.21.29 Processor Register Load Control (D-BS-EP12-0-RCL)

The Load Control gates for major register gates (MB, MA, MQ, AC and PC) are shown on
in the logic on the left, the

State.

this drawing.

As shown

MB is always loaded at TPS except for a SET instruction in the EXECUTE 2 Major

The MA is loaded when a manual key is depressed that generates MFTP2 H, or by CPTP

TPl L. The MQ
The control logic to load the AC

loaded for MUL, CLR, DSC • EXECUTE, EAE, and ROTATE instructions.

shown on the top right of the drawing; the control logic to LOAD PC is shown on the bottom

right of the

drawing.

Example of the Load Operation:

To transfer the contents of the MB register to the AC, the MB is enabled on the main register bus

RCS EN NO SHIFT and a Load AC pulse is generated.
1.21.30 Register Shift and

MQ Inputs (D-BS-EPl 2-RCS)

The shift logic to control the shifting operations of the register bus is shown on this drawing:

ENABLE NO

SHIFT, ENABLE SHIFT RIGHT, and ENABLE LEFT SHIFT. Only one of the shift
control signals can be true
at one time. The logic to shift the contents of the MQ register right or left
is also contained on this
drawing.

The logic to enable AC to MQ during a MUL instruction is shown on this drawing.
1.21.31

SKIP FF and KBIT (D-BS-EPl 2-0-SKH)

The control logic for the SKIP flip-flop is shown on this drawing.

All Skip instructions that are executed set the

SKIP flip-flop when the Skip condition is true. The output of the SKIP flip-flop is routed to
CARRY INSERT

MA in the next FETCH cycle when the SKIP flip-flop is set. The logic to decode
8-Mode Operate Skips is shown on this drawing. Sense Line inputs for LINC Skip instructions are ANDed
with IR bit 07 to produce SKH L FETCH SKIP L. Both the H and SKIP flip-flops are
direct-cleared by SKH
CLR SKIPS L. The H flip-flop is used for Half-word instructions, and is set whenever MB bit 00 is during the
(dwg. CYI) to increment the
all

DEFER cycle.
1.21.32

EP12 SKIPS (D-BS-EPl 2-0-SKL)

The logic contained on this drawing is used for LINC Skip instructions. The signal SKL I SENSE
L is qualified
by one of 14 possible internal Skip conditions, the signal SKL X SENSE L is produced by one of
12 possible

external Skip conditions and, four internal Skip conditions.

The signal SKL LINC EX SKIP L is used for SHD,

SRO, SAE, and XSK instructions.
1.21.33 Special Level 1 (D-BS-EP12-0-SLA)
This drawing contains logic for special level signals. The INDEX CLASS and 2

WORD FORMAT signals are

decoded on the top left side of the drawing. Control signals for arithmetic, rotate, and multiplication
operation,
are established at the bottom left side of the drawing.

At the center of the drawing, instructions that require

similar logic are combined to produce one single instruction control signal.

At the right side of the drawing,

control signals for a specific time state are produced.

The 8-Mode Operate

decoded.

1-49

and Operate 2 instructions are also

CHAPTER 2

MEMORY

2.1

INTRODUCTION

The PDP-12 uses a 4096-word, mass storage, 12-bit random access core memory. Memory expansion can be accomplished in increments of 4096 words to a maximum of 32,768 words. However, any increase in size of the
memory from the basic configuration necessitates the addition of the Type MCI 2 Memory Extension Control
with the first 4K of extended memory. The first 4K of extended memory is plugged directly into the processor

mainframe. The balance of the extended memory (MM8/I options) must be located external to the computer.

2.2

PHYSICAL DESCRIPTION

The elements that constitute the PDP-12 core memory system and their functional relationships are illustrated in
Figure 2-1

For simplicity the illustration depicts a 5-bit system, although the PDP-12 computer is a 12-bit sys-

tem.

As shown in Figure 2-1 memory is addressed through the memory address register (MA). Address selection is
,

achieved through the X and Y selection matrix.

One sense register element (MEM), sense amplifier, and inhibit

driver is required for each bit.

Memory stack (DEC Part No. 30-05256-1) is a triple-width module (see Figure 2-2).
sor mainframe locations C4, D4, and C6, D6.

It is plugged into

the proces-

The cables are connected to two W025 Modules that are plugged in-

to location A5, B5 for inhibit and A6, B6 for sense.

The ferrite core memory consists of 12 planes, each containing 4096
ray.

ferrite cores arranged in a 64 x

Each core assumes a stable magnetic state corresponding to either a binary

a simple

64-core ar-

or a binary 0. Figure 2-3 shows

4x4 core array.

Each core is threaded by four windings: X, Y, sense, and inhibit. There are 64 X and 64 Y selection lines; one X
line is threaded in series through each corresponding horizontal row in each array, as is a

cal columns.

Y selection line in verti-

Each individual selection line (X or Y), therefore, threads 768 (64 x 12) individual cores in the

4096 jq word stack. One sense line is wound through every core of each array. There are, therefore, 12 sense
lines. One inhibit line also threads through each core array for a total of twelve inhibit windings.
2.3

READ/WRITE

Each X, Y, and inhibit line, when excited, carries a current of insufficient magnitude to cause a change in the
magnetic state of a core; this current is designated the half-select value.

X and Y half-select currents, simultane-

ously flowing through a common core in the same direction, are cumulative and produce sufficient flux in the
core to cause a change of state, provided the core is not already in that state. This current, now designated /w//select (flowing in the Write direction, through a core initially in the 0 state), causes the core to change to the
state.

If current flow is in the

Read direction (and the core is in the

state), a change to 0 state occurs.

)
DIGIT

EACH

FOR

Memory

I
(
Core

AMPLIFERS

PDP-1

SENSE

Elements

2-1

Figure

2-2

INHIBIT

Figure 2-2

PDF- 12 Core Memory Stack

READ

WRITE

ai-0046
INHIBIT

SENSE

WINDING

Figure 2-3

Simple Core Memory Plane

INHIBIT

To write a 0 into a memory location, half-select current is caused to flow in the inhibit winding associated with
that bit. This current flows in the opposite direction to Y Write current.

The selected core, therefore, is sub-

jected only to X half-select current, and no change of state occurs; the Y and inhibit half-select currents cancel

one another. Effectively, a 0 is written into the location (cores are always assumed to be initially in the 0 state
prior to a Write cycle). Full-select current in the Read direction through a core in the 0 state causes no change of
state.

When reading, the change of state of a selected core from a

to a 0 induces a voltage of approximately 45

mV in

the associated sense winding. This voltage is amplified and sets the associated flip-flop in the sense register.

The

memory bit location is now 0, because this is a Read-Destroy memory system. A selected bit location containing
a 0 does not induce a voltage of sufficient amplitude to set a sense register flip-flop, because no change

of state

occurs in the core.

When one core of the 64 x 64 core array is subjected to full-select current, the remaining 63 cores threaded by
each line are half-selected. Half-selecting a core causes a small output to be sensed by the sense winding (approximately 5 mV). The polarity of these half-select outputs is dependent upon the initial states of the cores.
As a

worst case example: If all

26 cores subjected to half-read current are in their 0 state, the voltage sensed is of the

same polarity and much greater in amplitude ( 126 x 5 mV) than the individual output from the selected core.
This problem is overcome by winding the sense lines in such a way that the effects of the voltages sensed from
the half-selected cores do not add.

The sense amplifiers provide amplification of the analog output of the addressed memory ferrite cores. During
the

READ portion of the memory cycle, sense amplifiers detect the analog signals induced in the sense windings.

These signals are amplified (the Is only) and strobed into their respective sense register flip-flops, setting only
those corresponding bits of the register to

(3V level).

A sense amplifier circuit is provided for each of the 12 core planes in memory. If, during a Read operation, the
addressed core in a plane makes a

to 0 state transition, the flux change induces a current in the sense winding

to 50 mV voltage pulse at the input to the sense amplifier. This input is amplified, shaped, and, after threshold detection, used to set a SENSE flip-flop connected to the output of

of that plane. This current develops a 40

the corresponding sense amplifier when a STROBE signal is received from memory control. Addressed
cores that
were already in the 0 state, when saturated by the full-select Read flux, induce a limited amount of noise into
their sense winding.

The voltage level produced by this noise (in the order of 5 mV) is sufficient to activate the

sense amplifier associated with that plane.

The SENSE flip-flop for that bit, therefore, remains unaffected, indi-

cating a logic 0 in that location.

Because this type of readout destroys the content of the addressed cell (by switching all cores to Os), the data
stored in the sense register are transferred to the

MB for restoration to their original location during the WRITE

portion of the memory cycle; however, with some software instructions, the output of the sense register is not
gated to the MB, and there is no core restoration.

2.3.1

Sense Register (MEM)

All data that is read from core memory through the sense amplifiers are strobed first into this 12-bit register.

It ac-

cepts data only from core memory (Is only) and transfers data directly through the major register gating network.

2.4

MEMORY ADDRESSING

Selection of one 12-bit word from the 4096, that may be addressed in one field is accomplished through X and
^
Y selection switch matrices. Bits 00 through 05 of the memory address (MA) word are used to select one of 64

2-4

X lines that thread through each of the 12 planes. MA Bits 06 through

select one of 64

Y lines in a similar

Memory addressing is shown in Figure 2-4.

manner.

The memory selector switches decode the address specified by the CP memory address (MA), and select the
proper source and return lines for both X- and Y-axes.

Even though page addressing is used in 8 Mode, the MA always contains the absolute addresses for the selected

memory field. A relationship between absolute address and page addressing in the 8 Mode is shown in Figure 2-4,
The polarity of the magnetic field applied to the addressed cores is determined by the direction of current flow
through the core Read/Write windings.

7600-7777 {

7400 -7577 {

7200 -7377

7000-7177

6600-6777{

6400-6577

6200-6377{

6000-6177

5600-5777
5400-5577

5200-5377

5000-5177 {

4600-4777

4400-4577

4200-4377

4000-4177

3600-3777

3400-3577

3200-3377

3000-3177 {

2600-2777 {

2400-2577 {

2200-2377
2000 - 2177 {

1600 -1777 {

1400 -1577 {

1200-1377 {

000 -

177

0600-0777

0400-0577

0200-0377

0000-0177

}

000-177

000-177
}
}
}
}

}
}
}

000-177
000-177

000-177

000-177
}
}
}
}
}
}
}
}
}
}
}
}

}

000-177

000-177
000-177
000-177

CURRENT

000-177

PAGE

000-177
Y RETURN

000-177

000-177
000-177

000-177
000-177
000-177

000-177
}
}
}
}

000-177

000-177
000-177

000-177
}
}
}

}
}
}

Y RETURN

RETURN

000-177

000-177
000-177

000-177
}

PAGE (0-37)

PAGE ADDRESS (0-177)

ABSOLUTE ADDRESS (0000-7777)
12 - 0 247

Figure 2-4

Page Addressing in 8 Mode

2-5

TO AXES Y lO-YTT

01-0061

Figure 2-5

Simplified Memory Address Selector and

Read/Write Current Control

Figure 2-5 provides a simplified version of the selection of a Y-axis memory cell

and the method of determining
the Read/Write current direction. It is assumed in the drawing that bits 6 through
1 1 contain 0, selecting address

NOTE
The component designation numbers used in Figure 2-5 have
been arbitrarily assigned in this discussion, and do not relate
to actual designations.

2-6

With a Read operation in process, the Read (

)

line enables gates 3

and 6. The outputs of these gates turn on

both Q3 and Q6. This establishes a positive source and negative return for the windings of all Y-axis cores serviced by address-selection gates 1 and 2. This is the proper polarity and current direction for a Read operation.

With MA 06 through 11 = 0, gates

and 2 have been enabled, both Q1 and Q2 conduct, and current flows

through D1 and Q1 to D8. The Read current then passes through D8 and the winding of cores on the Y-axis of
00, and switches the cores to the 0 state if the X-axis is also selected. There are 12 x 64 cores along this Y-axis,

one for each bit and each X-axis. The Read current then passes through D7, Q2, and returns to the Memory Supply (-) through Q6.

The current does not pass through the cores on the 01-07 and 10-77 Y-axis, because of

back-biased diodes within the matrix and on their address selection switch.
In a Write operation, Q4 and Q5 are turned on by gates 4 and 5, reversing the direction of current flow.
dress selection path now becomes D4, Q2, D5; the cores of the YOO axis, D6, Q1

rection attempts to set the cores to the

passes is set to the

state.

The ad-

and D2. This new current di-

As previously stated, each core through which Write current

state, unless the inhibit driver associated with that core has been activated by the sensing of

logic 0 in that particular bit position of the Central Processor MB.

Figure 2-6 illustrates the timing relationship between the CP and memory Read/Write FETCH cycle.

The cycle

time shown is 1 .8 ps, which is due to the characteristics of the core memory. The STROBE pulse is adjusted to

match the core output of the memory. The relationship of the times given are approximate, with the exception
of MEM START/TP 1 and STROBE/TP2. TPl generates MEM START and STROBE generates TP2.

MEMORY

PROCESSOR

TPl

TPS

TP2

TPl

12-0235

Figure 2-6

CP and Memory Timing Relationships

2-7

The MA and FIELD are loaded at TPl and MEM START is generated. Approximately 200 ns later MEM BEGIN
is generated,

which sets the READ flip-flop and the memory Read cycle is initiated.

STROBE is generated ap-

proximately 300 ns later, and the contents of memory are loaded into the MEM register.

TP2 is generated by

STROBE and the contents of the PC are incremented by one. TPS is generated approximately 320 ns after TP2,
and the contents of the MEM register is transferred to the MB and IR. The READ flip-flop is cleared and, approximately 200 ns later, the INHIBIT flip-flop is set. Approximately 50 ns later, the WRITE flip-flop is set and
the memory Write cycle is initiated.
tents of the

The contents of the IR are now decoded to define the instruction. The con-

MB are written back into memory, MEM FINISH clears the WRITE flip-flop and generates MEM

DONE. The MEM IDLE flip-flop is set by MEM DONE, thus indicating the end of the memory cycle.
2.5

MC 2 MEMORY EXTENSION CONTROL
1

Additional core memory can be added to the standard PDP-12 in 4096-word increments. The addition of seven

4K fields, plus the standard memory, yields the maximum storage capacity of 32,768 words. Figure 2-7 illustrates the extended memory organization.

As shown in this block diagram, the PDP-1 2 mainframe contains the

standard memory (field 0). The MCI 2 Option provides the first memory extension and the memory selection
control for all eight memory extensions. Local memory timing for both field 0 and field
sic memory.

is provided

by the ba-

This control and associated Read/Write and addressing techniques do not differ from those of the

basic PDP-12.

2.5.1

Instruction Field Register (IF)

This three-bit register determines the memory field to be used for storage and retrieval of program instructions.

The IF register may be loaded from either the IF switch register (IFSR) or the Instruction Buffer (IB) register.
All program-executed transfers to the IF enter from the IB (D-BS-MC12-0-MXR).

The contents of the IFSR,

however, are loaded directly into the IF, and the IB, under manual control of the KEY START LSW.

When a
IMP or JMS instruction is executed, the contents of IB are transferred to the IF. When an Interrupt occurs, the
contents of the IF are transferred to the Save Field register (SF). At the end of the Interrupt subroutine, the
contents of the SF are restored to the IF through the IB by execution of the RMF (Restore Memory Field) instruction.

When the CIF (Change Instruction Field) instruction is executed, the contents of the MB06 through

MB08 are transferred to the IB, and then the contents of IB are transferred to the IF at the execution of a IMP or
JMS instruction. During the time between the CIF instruction and the JMP or JMS, Program Interrupts are inhibited.

2.5.2

Data Field Register (DF)

This three-bit register determines the field to be used for data storage and retrieval. The DF can be loaded from
either MB06 through MB08, or the Save Field register.

The CDF (Change Data Field) instruction can be used to alter the content of the DF to permit selection of a different field of memory. Bits 06, 07, and 08 of the

CDF instruction contain the desired field address. During a

Program Interrupt operation, the contents of the DF are automatically stored in the Save Field register and restored to the DF upon completion of the Interrupt subroutine by the

2.5.3

RMF instruction.

Instruction Buffer Register (IB)

This three-bit register provides input buffering for data transfers made into the IF under program control.
al transfers from

ManuIFSR are made directly into the IF and, simultaneously, into the IB. The IB is loaded into IF at

the execution time of every JMP or JMS instruction. Transfers into IB are made under program control during

the execution of CIF (Change Instruction Field) and

RMF (Restore Memory Field instructions.
)

2-8

Diagram

Block

Memory

Extended

2-7

Figure

2-9

2.5.4

Save Field Register (SF)

This six-bit register provides temporary storage during a Program

Interrupt for the contents of both IF and DF.

When the Interrupt state is entered, the contents of the IF and DF are loaded into the
sion of the Interrupt subroutine, an

SF register. At the conclu-

RMF instruction loads the contents of SFO-2 into IB for subsequent transfer

into IF and the contents of SF3-5 into DF.

The last instruction in the subroutine (IMP 10) completes the trans-

fer from IB to IF.

2.5.5

Break Field Register (BF)

The three-bit register determines the field to be used for storage and retrieval
using the Data Break facility.

for data transfers from I/O devices

The BF is loaded from the EXT DATA ADD 0,

and 2 lines by the load BF pulse,
which is generated at the end of every cycle. Each device puts its own
field address on the EXT DATA ADD
0,
1, and 2 when it requests a BREAK.

2.5.6

Field Selection

Figure 2-7 illustrates the memory extension control gating that

allows access to all memory fields. The gate output EAO, EAl and EA2, taken collectively, form a code that selects
one of the memory fields. The EAO and EAl
levels enable one of the four MM8I Memory Controllers
(each of which controls two memories). The EAO and

EAl configurations are: 00 (for fields 0 and 1), 01 (for fields 2 and
6 and 7).

3), 10 (for fields 4 and 5) and
The third enable level (EA2) specifies which of the two memory fields within

(for fields

the group indicated by

EAO and EAl is selected. Table 2-1 clarifies select coding, and the distinction between the enable

levels.

Table 2-1
Field Select Codes

Memory Controller

EAO

EAl

EA2

Selected

(EAO and EAl)
0
0
0
0

n
'

2
1

The memory field enable gates may be activated from one of the following three
register, or the

Field

Selected

BF register. The IF register is gated to the EAO, EA

sources:

the IF register, the DF

and EA2 levels at all times except during a

BREAK cycle or an indirectly referenced data handling instruction.
When START, EXAM, or KEY FILL is actuated, the IF register is gated to EAO, EAl, and

EA2 to generate the
memory field select code. The DF register is gated to the extended addressing bits when any
indirectly-addressed,
memory-referenced instruction other than IMP or IMS is executed. The BF decoder
allows the BF to generate
the memory field select code during a BREAK cycle.

2-10

Interrupt Inhibit

2.5.7

The interrupt inhibit logic disables the data input to the INT SYNC flip-flop in the processor from the time a CIF
instruction is decoded, until a JMP or JMS command finishes the CIF command. This prevents honoring an In-

terrupt before the field is changed. Interrupt synchronization is restored after the IF is loaded from the IB, al-

lowing further Program Interrupts to occur.

2.6

MEMORY BLOCK SCHEMATICS
Interprocessor Cables (D-BS-EM 1 2-0-IPCM)

2.6. 1

All cable connections shown on D-BS-EM

2-0-IPCM are routed to the cable connections shown on

D-BS-EP 2-0-IPC. These cables connect the memory to the CP.
1

MCS Sense Amplifiers and Inhibit Drivers (D-BS-EM 2-MCS)

2.6.2

Twelve inhibit drivers are associated with each memory stack. Inhibit current waveforms should be inspected
and compared with the waveforms in Figure 2-8. Inhibit current amplitude is approximately 290 mA. Each inhibit driver is enabled by

MC7 B INHIBIT H and MCT B FIELD 0 H, and the corresponding MC bit on a zero.

Twelve sense amplifiers (G020 or G021) are associated with each memory stack; each amplifier transforms the
analog pulse output of the ferrite core to a digital logic level. The G020 Module is used in computers that have a
basic 4K memory; when an additional 4K memory is added, this module is replaced with a G021, which provides

an additional amplifier input.

The sensor windings for each bit enter a differential amplifier with a threshold

voltage established as a function of the fixed SLICE voltage. The test points (pins El and K2) after the amplifier

allow observation of the waveforms for comparison with those shown in Figure 2-9.

2.6.3

MCT Memory Control (D-BS-EM 12-0-MCT)

The logic shown on this drawing consists of the memory voltage regulators (G805, G826), two voltage drivers
(G228), two strobe delays (M3 10), memory control flip-flops, and associated gating and buffers.

The voltage regulators monitor the various voltages used in the system. When a voltage does not meet the correct
operating potential, the MCT POWER OK level goes high and generates the MCT PWR STOP L signal, which halts
the computer.

The G826 Regulator also generates MCT POWER CLEAR when the system power is turned on.

The two G228 Drivers contain the switches for the memory Read/Write currents. The two M3 60 Strobe Delays
generate the MCT STROBE pulses for memory fields 0 and

The MCT FIELD flip-flop selects the strobe for the

appropriate memory field. The three memory timing delays (310) generate the necessary timing pulses to control the

READ, WRITE, and INHIBIT flip-flops. MCT MEM DONE is generated at the end of the timing se-

quence.

The control flip-flops have the following functions:

MCT MEM ENABLE — The output of the flip-flop is buffered to produce MCT B MEM ENABLE H.
This level enables the SENSE flip-flops onto the
flip-flop is set by CPTP

MEM lines for transfer to the CP registers. The

START MEMORY to select the first 8K of memory fields 0 and 1.

MCT Field — When set to the 0 state, the first 4K (field 0) is selected. When set to the state, the
second 4K (field) is selected. MXFGA2 H controls the data input and the flip-flop is clocked with
1

CCPT START MEMORY H, which is gated with -EAO and EA

2-1

MEM START
0.0

ABNORMAL INHIBIT
CURRENT waveform

BAD transformer, OPEN DIODE

OPEN WINDING
* 1-0020

Figure 2-8

Representative Inhibit Current Waveforms

MCT READ — Set when the READ portion of the memory cycle is being performed. It enables
the appropriate gates to control the Read current.

MCT INHIBIT — Set when the WRITE portion of the memory cycle is being performed. It enables the appropriate gates to control the Write current.

2.6.4

MCX X-Axis Selection (D-BS-EM 2-0-MCX)
1

The X-Axis selection of the memory stack is achieved by decoding the MAOO through MAOS bits.

MAOO through
MA02 are decoded into a binary count of 0 through 7, and MA03 through MAOS are also decoded into a binary
count and routed to the X selectors. These selectors are connected to a diode selection matrix and select one
core in the 8 x 8 matrix of 64 cores.

sents the stack winding traversing the
as

The inductor symbol connecting the centers of the two sets of diodes repre1

2-core planes.

The windings are identified on the diode selection boards

X 0-77j^. Suspected opens and shorts in the windings, detected during dynamic tests, should be verified by

2-12

CORE

CORE-0

CLEARED BY

MEM BEGiN
note: core outputs are observed differentially at the pins noted,
TIMING IS +5%,

Figure 2-9

81-0033

Representative Sense Amplifier Waveforms

measurements across the points with an ohmmeter. The resistance of the Read/Write winding is 3.5f2
±10 percent.

The forward and reverse resistance of the diodes in the matrix should be checked when address selection

failures are attributed to stack failures.

2.6.5

MCY 7-Axis Selection (D-BS-EM12-0-MCY)

The 7-Axis selection of the memory stack is achieved by decoding the MA06 through MAI 1 bits.
through MAOS are decoded into a binary count of 0 through 1

MA06

7, and MA07 through MAI 1 are also decoded into

a binary count 0 through 7 and routed to the Y selectors. These selectors
are connected to the diode selection
matrix and select one of 64 planes. The windings are identified on the diode selection boards as
Y 0-77
8

2.6.6

MEM EXTN Buffer (D-BS-MC12-0-MXB)

The signals required to control the Extended Memory Option (MM8I) are buffered for extra driving capabilities.

Two M6 17 Modules in locations M22 and M23 buffer the MA bits. The two M6 17 Modules in locations M24 and
M25 buffer the MB bits. A Non-Existent Memory Detect Module is also included to generate a strobe pulse and
allow the computer timing chain to continue if a non-existent memory is addressed.

2-13

MEM EXTN Field (D-BS-MC12-0-MXF)

2.6.7

The gate outputs EAO, EAl, and EA2, select up to 8-4K memory fields. The EAO and EAl levels enable one of
the four memory controllers (each of which controls two memories).

The EAO and EAl configurations are: 00

(for fields 0 and 1); 01 (for fields 2 and 3); and 10 (for fields 4 and 5).

The third enable level (EA2) specifies

which of the two memory fields within the group indicated by EAO and EAl is selected. Register enable flipflops are also provided for the Instruction Field, Data Field, and Break Field.

MXI Inhibit Drivers (D-BS-MC12-0-MXI)

2.6.8

The function of the inhibit drivers is identical to those described in Paragraph 2.6.2. These drivers coiitrol the
second 4K memory field.

MEM EXTN Register (D-BS-MC12-0-MXR)

2.6.9

The memory extension registers increase the addressing capabilities up to 32K of core memory. There are three,
3-bit registers:

DF (Data Field), IF (Instruction Field) and BF (Break Field). The 3-bit IB (Interrupt Buffer) reg-

ister acts as an intermediate holding buffer for the IF, and is loaded with the LIF, GIF,

and RMF instructions.

The contents of the IB are transferred to the IF with the LING, JMP and 8, JMP instructions. The DF register is
loaded with the LDF, GDF, and the RMF instructions. The BF register is loaded with the three extended address
bits

EXTO through 2, which are controlled by the peripheral devices. The register is clocked with the MXF LOAD

BF pulse, which is generated at the end of every GP timing cycle.
The 6-bit SF (Save Field) register retains the contents of the IF and DF registers in the event of a program interrupt.

The SF register outputs are gated onto the data inputs of the IF and DF register flip-flops, which are re-

stored with the

2.6. 10

RMF instructions.

MXX X-Axis Selection (D-BS-MG12-0-MXX)

JT-Axis selection is identical to the functions described in Paragraph 2.6.4. Thesi selectors are utilized for the

second 4K memory field.

2.6.1 1

MXY y-Axis Selection (D-BS-MG12-0-MXY)

F-Axis selection is identical to the function described in Paragraph 2.6.5. These selectors are also utilized for the

second 4K memory field.

2-14

CHAPTER 3
I/O BUS

3.1

INTRODUCTION

The Input/Output (I/O) Bus section of the PDF- 12 System contains the bus drivers,
logic required for communication between the system and

bus receivers, and control

peripheral equipment containing digital interface logic

compatible with the I/O Bus.

The I/O Bus may be operated in two major modes:

for program-controlled or device-controlled transfers.
Program-controlled transfers require that the program contain subroutines (or at
least a JUMP to an I/O routine)
that directly control data transfer. Data Break transfers are controlled
by the peripheral device on a cyclestealing basis.

The transfers are made between instructions of the program being performed.

Chapter 3 is divided into three sections:
a.

3.2

Block Diagram Descriptions

Flow Diagram Descriptions

Block Schematic Descriptions

BLOCK DIAGRAM DESCRIPTIONS

The following discussions describe the relationships of the major functional blocks
tional elements are used for both program-controlled and Data

of the I/O Bus. Certain func-

Break transfers. Both types of peripherals may be

connected to the I/O Bus at the same time.

3.2.1

Program-Controlled Transfers

There are two classes of program-controlled transfers as follows:
a.

One that uses a conditional skip instruction to test the state of the selected peripheral. If the
flag is set, the program skips to a data transfer subroutine,

then continues. However, in many

cases, it is necessary to service the peripheral within a certain period

of time, or the data from
the peripheral is lost. In these cases, the conditional skip instruction
is followed immediately

by a IMP .-1 instruction, and the program is halted in a time-wasting loop until the

selected

peripheral sets its Transmit or Receive Flag.
b.

A more efficient transfer uses a Program Interrupt feature. The program currently being
processed continues normally until any, peripheral on the bus sets a flag; if the
program has
previously enabled the Interrupt facility, an Interrupt-conditioned IMP is then

performed to

a subroutine that interrogates each peripheral to determine which

flag has been set.

this has been determined, the appropriate data transfer subroutine

is performed,

When

and the pro-

gram resumes with the instruction following the last program instruction executed before
Interrupt IMP.

3-1

the

Direct Program Transfer — Figure 3-1

data transfers.

a block diagram of the PDP-1 2 logic used for direct program I/O Bus

The Interrupt facility is also shown in this drawing, but is used only for Interrupt program trans-

fers.

The most significant octal digit of an Input/Output Transfer (lOT) instruction is 6^

When this digit is decoded

(dwg. INS), the lOP generator is enabled (dwg. IOC). The least significant octal digit of the lOT instruction determines which of the three lOP pulses are gated out to the peripheral via the lOP buffers. These pulses time
data transfer events within the peripheral.

BUSES TO AND FROM PERIPHERAL
POSITIVE BUS DEVICES

PDP-12 INPUT/OUTPUT BUSES AND CONTROL LOGIC

DATA IN(EXT I/O BUS 0-^tl)
L= I, H = 0

CLEAR ACCUMULATOR
(EXT AC CLEAR BUS

DATA OUT (100 BAC
I,
L=0

)

0—!()

DEVICE SELECT (BMB 3-11)
(DIFFERENT DEVICE CODES

FOR INPUT AND OUTPUT
TRANSFERS)
AND H AVAILABLE

DATA TRANSFER TIME PULSES
(BI0P1, BI0P2, BI0P4)

EXT SKIP BUS L

EXT
INTERRUPT

REQUEST L

L =

Figure 3-1

Program-Controlled 1/0 Bus Block Diagram

3-2

The peripheral device is selected by the middle octal digits NN (6NNXg) of the lOT instruction. Each peripheral
)

contains a device select decoder which gates the buffered lOPs (dwg./OC) from the bus into that peripheral when
it is

addressed.

Data transfer usually takes place between the AC and the peripheral data register during the last lOP (lOP 4).

lOP

the first lOP, is usually enabled by lOT Skip instructions to gate the status of the selected peripheral flag

onto the skip bus. The second lOP pulse (lOP 2) is normally used to clear the flag.

NOTE
In some peripherals, the least significant three bits of the lOT
instruction are used within the peripheral in combination with

the BIOP pulses to produce “sub-device” control pulses.

Program Interrupt Transfer - Figure 3-1 illustrates the Program Interrupt facility and its relationship to the pro-

gram counter. The Interrupt facility is turned on and off by program instructions: ION enables the facility, lOF
disables the facility.

When the Interrupt facility is enabled, any peripheral that sets its flag activates the Interrupt Bus.

If the current

program is being executed in 8 Mode, the Interrupt facility loads the Program Counter (PC) with absolute address

0001 g.

If the current program is being executed in

LINC Mode, the PC is loaded with absolute address 0041 g.

The previous contents of the PC are stored in OOOOg and 0040g, respectively.

A subroutine starting at address 000 Ig or 004 Ig now proceeds to check each of the peripherals on the bus until
the device with the set flag is encountered. This device flag causes a program skip so that the next instruction ex-

ecuted is a JMP to the appropriate service routine for that peripheral. If the addressed peripheral does not have
its flag set,

the skip to that service routine is not performed, and the subroutine continues to interrogate periph-

erals.

With the exception of the Interrupt Bus and the Interrupt facility, the hardware involved with Program Interrupts
is

the same as that used in direct program transfers.

3.2.2

Data Break Transfers

There are two classes of peripheral-controlled Data Break transfers: single-cycle or three-cycle. Although simpler

and faster, the single-cycle Data Break requires more digital hardware within the peripheral to monitor word
count and control the current address of the data being transferred to or from the PDP-12.

The three-cycle Data Break, though shghtly slower than a single-cycle Data Break, greatly reduces the digital hardware required in the peripheral. The three-cycle Data Break uses two core memory registers to monitor WORD

COUNT and CURRENT ADDRESS, and therefore requires three core memory cycles instead of one for each
transfer.

NOTE
Only one Data Break peripheral can be connected directly to
the PDP-12. A Data Multiplexer must be used if more than
one of these peripherals is to be used in the system.

A DM04

Multiplexer must be used if only positive bus peripherals are
involved. If negative bus peripherals are used, a DM0 1 Multiplexer and a DW08A I/O and Data Break Converter must be

located between the peripherals and the PDP-12 Data Break

Both negative and positive bus peripherals may be
used in the same system if a DM04, DW08A, and DM01 (if
facility.

more than one negative bus peripheral) are used.

3-3

Single-Cycle Data Break - A block diagram of both single- and three-cycle Data Breaks is presented in Figure 3-2.
Single-cycle data and control paths are shown as solid lines.

— BREAK ENABLE

NOTES^
a.

3-cycle break data paths (nat used in single-cycle break)
are shown by dashed lines.
Circled numbers refer to cycles of 3-cycle break.
12-0237

Figure 3-2

Data Break I/O Bus Block Diagram

The device-requesting service sets its Break Request flip-flop. The Break Request is honored
at the completion of
the instruction in progress when the Break Request occurred. At this time,
a Break Enable signal from Data
Break Control to the peripheral is initiated and remains active until the end of the

BREAK cycle. The peripheral

supplies the core memory address to the

MA register. Data

transferred via the memory buffer register, the di-

rection of transfer being controlled by the peripheral via the Data In/Data

Out Bus and the Data Break Control.

The External Data Address output from the peripheral is used as the input to the MA register.

Thus, there is a

discrete core memory address for each value read by the peripheral.

A special use of the Data Break facility is Memory Increment. In this mode of use, when addressed, the contents
of a peripheral-specified core location is incremented by one. The peripheral
must generate the signal EXT

INCREMENT MB L, but no data output to the MB is required.
Three-Cycle Data Break - Data and control paths exclusively a part of the three-cycle

Data Break are shown in
dashed Unes on Figure 3-2. The single-cycle Data Break forms the third cycle of the
three-cycle Data Break, with
the exception that the data address is taken from a core memory Current
Address register instead of directly
from the peripheral.

The three-cycle Data Break is enabled by the signal EXT 3 CYCLE L (dwg. JOB). When the
request is honored
by the processor at the end of the current instruction, the address of the Word Count
the peripheral via the

MA register.

The contents of the Word Count register are incremented during the first cycle of the three-cycle
This register specifies the length of the data table for a given peripheral, and is initially

Data Break.

loaded by the program

WORD

with the complement of the
COUNT. As the data transfer progresses, this count is incremented until
overflow occurs in the Memory Buffer register, when the final data word is transferred.
The Word Count Overflow is provided as a bus signal IOC WC OVERFLOW (0) H to the peripheral, which
then can be used as an
INTERRUPT condition to inform the program that the block of data has been completely transferred to or from
the peripheral.

The second cycle of the three-cycle Data Break is used to obtain the CURRENT ADDRESS within
in core memory.

the data table

The Current Address register is the next sequential address following the Word Count register

address, the Memory Address register being incremented automatically at the end

of the first cycle. The

CURRENT ADDRESS is incremented in the memory buffer, and the contents of the Mcmcr/ Buffer register are
used during the final cycle of the Data Break to address in the data table of core memory. The signal
lOB CA

INCREMENT H fdwg. lOB), allows peripheral control over incrementing the Current Address register.
During the final cycle of the three-cycle Data Break, the data word is transferred between the peripheral

memory via the Memory Buffer register.

and core

This third cycle is identical to the single-cycle Data Break, except that

the core memory data address is specified by the contents of the Memory Buffer

ware flip-flop register within the peripheral.

3.3

FLOW DIAGRAM DESCRIPTIONS

The following discussions describe the sequence of events shown on flow diagrams for Interrupt and Data
Transfers in Volume III of this manual.

Break

3 3.1
.

Direct Program Transfer (lOT)

The flow diagram for a program-controlled Input/Output Transfer (lOT) is shown as part of Volume III drawing

D-FD-PDP-

2-0-2 1 at coordinates A-C, 2.

NOTE
In this and subsequent discussions, alphanumeric coordinates
refer to the border around all engineering drawings, and are

meant as an aid to locating the portion of the drawing under
discussion.

At T4 (time state 4) of any 8 Mode FETCH cycle, the lOT PAUSE flip-flop (dwg. CPT) is set if an lOT op code
(6XXXg ) is decoded. With the PAUSE flip-flop set, T5 continues until all three lOP pulses have occurred
(whether or not all three are gated to the peripheral by the least significant digit of the instruction). The termination of IOC lOP 4 H, IOC OFF lOP H resets the lOT PAUSE fhp-flop to terminate T5, and the program continues with the memory start pulse of the FETCH cycle of the following instruction.

3 3.2
.

Program Interrupt Transfer (INTERRUPT)

The flow diagram for a jump to an Interrupt routine is shown as part of Volume III drawing D-FD-PDP- 2-0-20
1

(B-D, 1-4).

Assuming that the Interrupt flag (dwg. CPS) has been raised by a peripheral during the previous instruction

EXECUTE cycle (prior to T5), the data field and instruction field are transferred to the Save Field register by
the start memory pulse (Tl) of the first cycle of the INTERRUPT Major State.
If the current instruction is being performed in 8 Mode, the
in the PC just prior to the Interrupt is stored.

MA register

is loaded

with OOOOg, where the address

(An indirect Jump 0 may be done at the end of the device-servicing

routine, to return to original program.) Location 0040g

is used

for the same purpose in LINC Mode.

Locations

000 Ig and 004 Ig are used to begin the service routine, as the MA + !-» PC during T3 of the Interrupt cycle.

TRAP Flag is set (a software Interrupt feature), the two corresponding locations are 0140„O and 01 41 „5

The

the

Interrupt Enable flip-flop is cleared at Tl of an Interrupt cycle.

The instruction register is cleared during T2. At T3 the contents of the PC, plus a skip, are transferred to the
memory buffer to be stored as the return address upon completion of the Interrupt routine. The INTERRUPT
cycle is completed at Tl by incrementing the new contents of the

MA register by one, and transferring the next

sequential address of the Interrupt routine to the Program Counter.

3 3.3
.

Data Break Transfers (BREAK)

The flow diagram for both single- and three-cycle Data Breaks is shown on Volume III drawing
D-FD-PDP-1 2-0-23.

Single-Cycle Data Break - The single-cycle Data Break cycle is entered at coordinates D,3 of the flow diagram.

At Tl of this cycle, the address from the peripheral hardware address register is gated into the Memory Address
registers to the Break Field registers.

gated.

If extended memory is used, three additional memory address bits are also

The instruction register is cleared at T2.

At T3, one of three events occurs.
eral is loaded into the Memory

If the peripheral is transferring data into core memory, data from the periph-

Buffer register.

If the peripheral

accepting data from core memory, data at the

selected address is loaded into the Memory Buffer register and transferred via the

3-6

BMB lines (one ICB). If the

peripheral is operating as a Memory Increment device, no data is transferred, but the contents of the selected

ad-

dress (corresponding to the sample value of the parameter being measured by the peripheral) are incremented

one.

The BREAK cycle is completed at the end of T3, and control returns to the program in progress at the time the

BREAK occurred with T1 of the FETCH cycle.
Three-Cycle Data Break - The three-cycle Data Break is entered at coordinates D,7 of the flow diagram, which is

T1 of the WORD COUNT cycle. The address of the Word Count register in core memory must still be provided;
because this is a fixed address, the peripheral may be hardwired to provide it, thus eliminating a hardware register
in the peripheral.

If extended memory is used, three additional Memory Address bits are also gated in.

The in-

struction register is cleared at T2.

At T3 of the WORD COUNT cycle, the core memory Word Count register is incremented by one. The Word
Count register was previously loaded with the negative value of the number of words in the core memory data
table for the peripheral.

Because the Word Count register is incremented each time a transfer occurs with this

peripheral, the complete table transfer is completed when the word count is zero. This condition is
indicated by

WC OVERFLOW). The CURRENT
ADDRESS (dwg. CPS) flip-flop is now set, and the break continues immediately with the CURRENT ADDRESS
an overflow out of the sign bit of the Memory Buffer register (IDO

cycle of the three-cycle Data Break.

During T1 of the CURRENT ADDRESS cycle, the second cycle of a three-cycle Data Break, the

MA register

incremented by one to obtain from core memory the contents of the Current Address register. The instruction
register is cleared at T2. Normally at T3, the contents of the Current Address register are
incremented by one
and loaded into the MB. This leaves the CURRENT ADDRESS of the next core memory data table word in the

Memory Buffer register. Under special applications, the increment of the Current Address register may be inhibited and the register contents are returned to core memory unchanged.

Because the contents of the Current Ad-

dress register are incremented before they are used as the address of the word in the data table,

address of the data table must be specified by initializing software as (address-

the starting

1) in order that the first (and sub-

sequent) transfers occur at the correct core memory address. The BREAK flip-flop is now set, and the threecycle Data Break continues into the

BREAK cycle.

The BREAK cycle for the three-cycle Data Break is identical to the single-cycle Data Break, with the following
First, the core memory address at which the data transfer occurs is transferred directly

important differences.

from the Memory Buffer register (still holding the incremented CURRENT ADDRESS) to the Memory Address
register.

Second, it is not possible to use a three-cycle Data Break to build a histogram, because the histogram re-

quires the peripheral to supply the memory address from its data output. In a three-cycle Data Break,
12 bits of

the core memory data address are supplied from the Current Address register.

3.4

BLOCK SCHEMATIC DESCRIPTIONS

The discussions under this heading briefly describe the logic presented on the five I/O block schematics in Vol-

ume III of this manual. Refer to Chapter 5 of the PDP-12 System Reference Manual for timing diagrams of I/O
Bus operations.

3.4.1

I/O and External Memory Cables ( D-BS-EP 1 2-0-1 CB

All external I/O Bus connections to the PDP-12 are made via module sockets at mainframe coordinates N14

through N18. The socket at N14 provides connections for the 100 BAC (to peripheral) Bus; the lOT Buffered

In/Out Pulses (BIOPs 1

2, 4); Buffered Time States 2 and 5, available to peripherals for synchronizing events;

and the Initialize Bus, available to all lOT peripherals.

3-7

The Buffered Memory Bus output is provided to the peripherals via mainframe module socket N15. The logic
true level output is high for all twelve bits; in addition, inverted form logic is provided for bits 3 through 8 in or-

der to facilitate setting up device code decoders in addressable (lOT) peripherals. This socket provides the data

output to Data Break peripherals.

AC inputs (EXT I/O Bus) from lOT peripherals are accepted at mainframe module socket N16. This socket also
accepts I/O Bus signals for Interrupt Request, Skip, and Clear Accumulator. A Buffered Output Bus signal from
the PDP-12

RUN flip-flop (dwg. CPR) is also provided at this socket.

Core memory addresses are accepted from Data Break peripherals via the mainframe module socket at N17. This
socket also provides the connections for the following Data Break I/O Bus signals:

Break Request, Increment

Memory Buffer, and Data In/Data Out Control. Data Break Output Bus signals provided at this socket are the
Buffered Break Pulse (active for the duration of the BREAK cycle), the Address Accepted Pulse (used by threecycle peripherals), and one Initialize Pulse for use by Data Break peripherals.

Data inputs from Data Break peripherals are accepted via mainframe module socket N
tains connections for Data Break I/O Bus inputs:

ment (for use by three-cycle peripherals).

This socket also con-

three-cycle/single-cycle control, and Current Address Incre-

If extended core

memory is used, the additional three address bits

from the peripheral are also accepted at this socket. The Word Count Overflow output to three-cycle Data Break
peripherals is also routed via this socket.

The remainder of the sockets shown on this drawing are used for Extended Memory and External Level signals

(may be used as flags from non-digital external equipments).

3.4.2

I/O Inputs Part A (D-BS-EP 12-0-10 A)

The bus receivers for Data Break peripheral data input and address buses, and the data input gates for lOT peripherals (B-D, 1-2) are shown on this block schematic.

3.4.3

I/O Inputs Part B ( D-BS-EP 12-O-IOB)

This block schematic contains the lOT input bus gates: Interrupt Request, Skip, and Clear Accumulator.

The

Data Break request bus inputs: Break Request, Three-Cycle/Single-Cycle, Increment Memory Buffer, Data In/
Data Out, and Increment Current Address are shown at coordinates C-3, 4. The Data Break extended core memory address bus receivers are shown on this drawing. The pullup resistors shown at B-D, 2 are part of the Pro-

gram Interrupt bus.

3.4.4

I/O Control and Timing (D-BS-EP 1 2-O-IOC)

Control elements for lOT and Data Break transfers are shown on this drawing.

lOT transfers are initiated when the lOT PAUSE (dwg. CPT) flip-flop is set. This signal is introduced to the I/O
control logic to reset the third bit of a three-bit shift register (C, 6-8).

The lOT PAUSE flip-flop also initiates the

lOP delay line pulse generator logic (B, 1-6) and sets the lOP SAMPLE flip-flop (C, 4).
The lOP SAMPLE flip-flop enables the three lOP output gates at location B, 4-8. The Enable is ANDed in these
gates with the three flip-flops of the shift register, and with the least significant three bits of the lOT instruction.

The lOT bits determine which of the lOP pulses are to be gated out to the peripheral; the shift register determines the timing of the selected pulse or pulses. The shift register and pulse generator delay line determines lOP
pulse timing.

The shift register and delay line operate as follows. On the trailing edge of Central Processor TPS (Time Pulse 5),
following setting of the lOT PAUSE flip-flop, the delay line input is initiated and the third flip-flop of the shift

3-8

of the register which controls

lOP 1. The SAMPLE flip-flop is also set when the delay line propagation begins. Therefore, if
the least significant bit of the lOT instruction is set, BIOP
is immediately available on the bus.
1

The I/O STROBE pulse occurs 750 ns after CPTP TP 5 and CPT I/O PAUSE. Part of the delay
is caused by the
delay line which is trapped at 500 ns, and the other part by propagation delay through
gates and pulse amplifiers.
If the least significant octal digit of the lOT instruction is other than

0 (location B, 1-3), the STROBE pulse is

used for gating within the processor.

At 650 ns into the delay hne, the lOP SAMPLE flip-flop is reset by the IOC OFF lOP H at location
C, 1 This
terminates the I OP currently in progress. After 1200 ns, the propagated pulse is
returned to the input of the de.

lay line via the IOC I/O

CLOCK H at location B, 2. This causes an IOC lOT SHIFT H pulse, and the process is

repeated with IOC lOP 2 flip-flop set.

The lOT PAUSE flip-flop is reset at the completion of IOC lOP 4 H (generated by the IOC lOP
3 flip-flop) by
ANDing the IOC lOP 3 flip-flop with the IOC Off lOP H pulse.

The IOC I/O PRESET L signal used to produce the lOO BA INITIALIZE H signal is developed
this drawing.

in logic shown on

The WORD COUNT OVERFLOW and ADDRESS ACCEPTED flip-flops used with Data

Break

peripherals are shown at locations D, 6 and D, 5 respectively.

The Interrupt facility logic is shown at location D, 4-2.
3.4.5

I/O Output Buffers (D-BS-EP 12-0-100)

The output buffers (bus drivers) for standard lOT and Data Break peripherals are shown on this
cations B-D, 7-8, the Data Output Buffers for lOT peripherals are shown.

drawing. At loThe data output buffers for Data

Break peripherals are shown at locations B-D, 4-5 and C-D, 1-2. Bits 3 through 8 of this
bus are also used to address lOT peripherals; therefore, both true and inverted forms of these bits

are provided to facilitate setting up

the device select decoders within the peripherals.

The lOP buffers for lOT

peripherals are shown at B-C, 1-2. CP time state buffers for TS2 and TS5 are
also provided and are shown at B, 1-2. The signal 100 BA INITIALIZE H and 100 BB INITIALIZE
H are generated on
logic shown on this drawing at B, 1-2.

The bus signal buffers for CP RUN, BREAK, ADDRESS ACCEPTED, and WORD COUNT OVERFLOW

shown at A-B, 4-8.

3-9

are

CHAPTER 4
TELETYPE

4.1

INTRODUCTION

The Teletype® Model 33 ASR is used on all standard configurations of the PDP-1 2 Computer and is connected
internally to the I/O Bus (dwg. 10 A).

The Teletype is accessed for input or output by programs in either the

LINC or PDP (dwg. CPR) operating mode. The Teletype is equipped with a paper-tape reader and punch; the
reader and keyboard use the same input path and instructions, while the printer and punch use the same output

path and instructions. The maximum transfer rate in either direction is 10 characters per second. The Teletype
has both full-duplex and half-duplex capability. In full-duplex operation, data may be transmitted in both directions simultaneously, without interference.

In half-duplex operation, data may be transmitted in only one direc-

tion at a time.

Although other Teleprinter and tape devices are compatible with the PDP-1 2, only the Model 33 ASR is considered in this discussion.

4.2

TELETYPE CONTROL

The ASR Teletype and the Teletype Control functions (see Figure 4-1) are logically divided into two sections:
the receiver (dwg. TTI) or Teletype input (TTI) which consists of the keyboard, tape reader, and associated

Tele-

type control circuitry for computer input; and the transmitter (dwg. TTO) or Teletype output (TTO), which consists of the Teleprinter,

tape reader, and Teletype control circuitry for computer hardcopy output (printed page

or perforated tape).

For output, the Teletype Control converts an 8-bit ASCII character code into an

-unit serial code, and trans-

mits it to the Teleprinter/punch. For input, the control assembles the serial code into an 8-bit character and
places it on the I/O Bus for transmission to the AC.

A free-running 880-Hz clock, along with respective clock dividers (one in the receiver and one in the transmitter
circuitry), provides the means of synchronizing the computer to the

During the receiving or transmitting of the

10-Hz rate of the Model 33 ASR Teletype.

1-unit Teletype word, the Teletype Control senses the last two units

(stop pulses) to maintain a positive synchronous lock.

4.3

RECEIVER (TTI)

The Teletype Control performs a Read operation in which an asynchronous serial data word from the Teletype
keyboard or tape reader is clocked into the receiver TTI shift register, where it is held as an 8-bit word for parallel

transfer to the AC.

The readiness of the device for a transfer is signaled by a status signal (KEYBOARD FLAG

(1) L) which results in an Interrupt Request to the processor.

^Teletype is a registered trademark of the Teletype Corporation.

4-1

At the program-determined time, the assembled

Figure 4-1

Teletype Control Block Diagram

8-bit word is strobed in parallel into the accumulator via the I/O Bus.

The receiver (dwg. TTF) is then cleared

and ready to repeat the transfer data.

4.4

TRANSMITTER (TTO)

The Teletype Control TTO performs a print and/or punch operation in which a parallel 8-bit word from the AC
is

loaded into the TTO shift register, from which it is clocked as an asynchronous serial

1-unit word, to the

ASR-33 Teletype unit. At the Teletype unit, the word is decoded and printed and/or punched on tape. Transfer
control between the AC and the Teletype is accomplished by a programmed Teletype instruction. When the
Teleprinter Flag is set, the parallel data transfer from the AC to the TTO shift register is programmed, and the
1

10-Hz clocking of the word to the Teletype decoder begins. The TTO register control and shift register are

then cleared to receive the next word.

A detailed logic description is provided for the Read cycle, the Print/

Punch cycle, and the program instruction set for Teletype operation.

4.5

DETAILED LOGIC DESCRIPTION

The following paragraphs describe the Read (dwg. TTF) and Print/Punch (dwg. TTO) cycles, and the program instructions for Teletype operation.

4.5.1

Read Cycle

Figure 4-2 shows the sequence of events that occur when a serial word from the Teletype unit is assembled in the
receiver.

The receiver circuitry is shown on engineering drawing D-BS-EP12-0-TTI.

The clock (dwg. TTO) is free-running and produces TTO TTI CLOCK H pulses at 880 Hz for the receiver, and,
by use of two flip-flop frequency dividers, 110 Hz TTO SHIFT pulses for the transmitter.

4-2

INITIALIZE

CONTINUOUS PULSES AT 880 HZ RATE
TTI

CUDCK

tI2345678I2

SERIAL
CHARACTER

—u

_____

STOP STOP

1 1 1

TTO SHIFT

220 H?
”ATE

j II urn mm,,

§
1

1 1 1

p—

DISTRIBUTION

1 1

.inhibited WHEN I

— CLEARED
IN

active IS

PRESET

3
IN LAST UNIT

•

3
IN STOP

0
3

IN STOP 2

CLEARED BY KCC

KEYBOARD
FLAG

INSTRUCTION (6032)

Figure 4-2

Teletype Read Cycle Timing Diagram

When the computer is turned on or the CSI START (START LSW, START 20, or START 400) key is depressed,
the processor IOC I/O PRESET H level is generated.

IOC I/O PRESET H clears the TTI IN ACTIVE (1) L flipDETECTOR (1) H flip-flop, and generates TTI KCC L to clear the TTI Keyboard Flag and
set the TTI READER RUN flip-flop. Clearing the TTI IN ACTIVE (1) L flip-flop generates the TTI START
ENABLE L signal. This signal, combined with the start bit (produced in the Teletype distributer by program
control) or the output of the Schmitt trigger, allows a TTO TTI CLOCK H pulse to generate TTI REC PRESET L.
The TTI REC PRESET L pulse allows the serial data from the Teletype to synchronize with the receiver logic in
flop, the TTI SPIKE

the following manner:

TTI REC PRESET L sets the TTI IN ACTIVE flip-flop and the TTI register flip-flops to a binary
1, and clears the TTI READER RUN flip-flop. With TTI READER RUN cleared, a relay in the
ASR tape reader is energized and releases the tape-feed latch; tape motion is thus stopped only be-

tween sensing of the end of character and the beginning of the next character. In addition, the
TTI SPIKE DETECTOR flip-flop is set to sample the line after the start bit is received. If the
start bit is not present at this time, the TTI IN

ACTIVE flip-flop clears and awaits another TTI

Preset signal. This eliminates noise on the start bit in the first 1/2 unit. If the start bit is still present, e.g., no false start due to noise, TTI shift pulses are generated and the start bit is loaded (a

binary 0) into TTI 0. The shift pulses are synchronized to occur during the middle of each serial

4-3

bit-time.

As Figure 4-2 illustrates, each succeeding TTI SHIFT H pulse loads the character bits

into the receiver serial shift register.

When the start bit is shifted into TTI 7, the next TTI SHIFT

H pulse produced sets the TTI IN LAST UNIT and TTI KEYBOARD FLAG (1) L flip-flops. Setting of the TTI IN LAST UNIT clears the TTI IN ACTIVE flip-flop, disabling further TTI shift
pulses. When cleared, TTI IN ACTIVE allows the TTI CLOCK SCALE 2 pulses to set the TTI IN
STOP

and TTI IN STOP 2 flip-flops, which count out the stop time. TTI IN STOP 2 when set,

LAST UNIT flip-flop, thus allowing Start Enable to produce TTI REC PRESET
when the start bit of the next character appears at the output of the Schmitt trigger.

clears the TTI IN

When the KEYBOARD FLAG (1) L Hip-flop is set, TTO TT INT L fdwg. TTO) is generated, TTO
TT INT L generates lOB INT RQST H in the CP. If the Program Interrupt facility is enabled, lOB
INT RQST H indicates to the PDP-1 2 that a device is requesting service. The program then enters
a Search subroutine to determine which device issued the Interrupt.

cuting a series of flag-checking Skip instructions.

This is accomplished by exe-

When the Keyboard Flag-sensing instruction

KSF (6031) is performed, and the flag is raised, TTI SKIP (dwg. TTI) is generated, producing lOB
lOB I/O SKIP H forces the processor program counter to increment by

I/O SKIP H in the CP.

one; thus the next instruction is skipped.
the skip occurs.

A service routine for the Teletype receiver is entered when
READER RUN set to re-

In this routine, the TTI Keyboard Flag is cleared, TTI

lease a new serial word to the receiver, and the previously assembled word is strobed in parallel to

the processor.

4.5.2

Print/Punch Cycle

Figure 4-3 illustrates the sequence of events that occur when a parallel word from the AC is loaded into
transmitter logic, and disassembled into serial word format for use by the Teletype unit.

the

The transmitter logic is

shown on engineering drawing D-BS-EP 2-O-TTO.
1

When the computer is turned on, or when the START (START 20, START 400, or START LSW) key is depressed, the processor IOC I/O PRESET L level is generated. This level clears the TTO ENABLE,
TTO

OUT

ACTIVE, TTO TPR ELG (1 L (Teleprinter Flag), and TTO register flip-flops. Execution of the program instruc)

tion TLS (6046) generates

TTO SELECT H in the transmitter logic, and IOP2 and IOP4 in the processor. IOP4
and TTO SELECT H combine in the transmitter logic to load the parallel word (AC bits AC04 through
into the TTO register, and set the TTO ENABLE flip-flop.

ACl 1)
IOC IOP2 H and TTO SELECT H are combined to

clear the Teleprinter Flag.

TTO shift pulses are produced by dividing TTO CLOCK L pulses with TTO FREQ DIV. The frequency at the
TTO CLOCK L output is 220 Hz, and is provided by the M452 CLOCK Module at NOS (dwg. TTO). The output
of TTO FREQ DIV flip-flop is 10 Hz. Synchronization is provided by using both of these clock
pulses as shown
1

Figure 4-3, and described below.

When the first TTO CLOCK pulse following the setting of TTO ENABLE occurs, the following

OUT ACTIVE flip-flop is set, the start bit is placed on the line to the Print
OUT STOP set (discussed later). Alternate TTO
CLOCK pulses produce a TTO SHIFT pulse, which shifts the data word bit-by-bit into the LINE
events take place:

the

Selector Magnet driver (TTO line), and TTO

As data is shifted onto the PSM line, binary Os are shifted into the TTO register through
ENABLE flip-flop. When the parallel-to-serial conversion is completed, an 8-input
NAND gate senses all Is in the TTO register, and its output TTO=0 enables the Teleprinter Flag
to be set simultaneously with the next (and last) TTO SHIFT pulse. When TTO
OUT ACTIVE is
cleared, TTI SHIFT is disabled, and the two 1-unit stop bit times are counted out
by the TTO
OUT STOP register. The first TTO CLOCK pulse occurring after TTO ACTIVE was cleared,
clears the TTO OUT STOP
flip-flop. The TTO OUT STOP
.5 and the TTO OUT STOP 2 flipflip-flop.

the TTO

flops are cleared by the next two consecutive pulses.

TLS instruction has been issued
(Print/Punch Another Character), the operation commences with the occurrence of the first

4-4

If another

Figure 4-3

Print/Punch Cycle Timing Diagram

TTO CLOCK pulse after TTO OUT STOP 2 is cleared. For the print/punch operation with the
ASR-33, a 2-unit OUT stop time period is required because of the inherent electro-mechanical delay time in the Teletype unit.

When the Teleprinter Flag is set, TTO TT INT L (dwg. TTO) is generated. TTO TT INT produces
lOB INT RQST H in the processor. If the Program Interrupt facility is enabled, lOB INT RQST H
The program then enters a Search subroutine to determine which device issued the interrupt. This is accomplished by executing a series of flag-check

indicates that a device is requesting service.

Skip instructions.

When the Teleprinter flag-sensing instruction TSF (6041) is performed and the

TTO TT SKIP is generated, producing I/O SKIP in the processor. I/O SKIP forces
the program counter to increment by one; thus, the next instruction is skipped. A service routine
flag is raised,

for the Teletype transmitter is entered when the skip occurs.

For the transmitter service, a new

character is transferred to the transmitter to be printed or punched by the Teletype unit. Table
4-1 contains descriptions of the Teletype keyboard/reader and the Teleprinter/punch instructions.

4-5

Table 4-1

Teletype Instruction Description

6031

Generates IOC lOPl to sense the status of the TTO Keyboard
Flag.

When the flag is set, the next sequential program instruc-

tion is skipped. This indicates that the assembled word is

ready for transfer to the AC.

6032

Generates IOC IOP2 to clear the Keyboard Flag and set TTI

READER RUN flip-flop. In addition, TTO TT AC CLEAR is
generated to clear the AC.

6034

Generates IOC 10P4 to transfer the assembled word in parallel
to the

AC through the major register bus. The Keyboard Flag

flip-flop is not cleared.

6036

Generates IOC IOP2 and IOC 10P4 to perform the functions
of the KCC and KRS commands during a single computer cycle.

The Keyboard Flag flip-flop is cleared.
6041

Generates IOC lOPl to sense the status of the Teleprinter Flag.
When the flag is set, the next sequential program instruction is
skipped. This indicates that the print/punch operation has

completed.

6042

Generates IOC IOP2 to clear the Teleprinter Flag.

6044

Generates IOC IOP4 to load the parallel word into the transmitter register, initiating the print/punch operation.

6046

Generates both IOC IOP2 and IOC IOP4 to combine the functions of the TCF and TPC instructions in one computer cycle.

CHAPTER 5
LINC DEVICES

5.1

INTRODUCTION

The I/O control devices in this chapter are control modules that interface with the PDP-12A LINC System. All
other peripherals are considered optional I/O devices, and are omitted from this discussion.
The LINC System I/O devices are as follows:

5.2

Tape Control

Relay Control

A/D Control

Display Control

Sense Line Control

Speaker Control

TAPE CONTROL

The TU55 and TU56 Transports are controlled by a fully-buffered tape processor; once initiated by the LINC
program, tape operations are carried out independently of the CP. Tape control is described in detail in Chapter
6 of this manual.

5.3

A/D CONTROL

Sixteen analog input channels are provided with the PDP-12A System. The first eight channels are wired to
potentiometers, all of which provide a variable reference voltage of -5 V to +5V. The potentiometers can be varied

by control knobs located on the data terminal panel. The second eight channels can be plugged into the data
terminal panel through standard phone jacks, for which the inputs should be ±1 V.

An additional 16 channels (20 through 27 and 30 through 37) can be added as an option to the PDP-12A. This
option (AM 12 and AG 12) is described in Chapter 7 of this manual.
Figure 5-1 illustrates the relationship of the CP to the A/D Conv^er.

A SAM instruction decoded in the CP is

routed to the A/D Control, where the A/D Converter is started to convert an analog input signal. The control,
timing, addressing, and data relationship is illustrated in Figure 5-2. There are two types of inputs to the A/D
Converter. Channels 0 through 7 are potentiometer inputs that can be manually adjusted by the operator.
Channels 10 through 17 are external analog inputs that are applied to differential preamplifiers. The preamplifiers provide impedance matching, common-mode rejection, overload protection, and isolation to the computer
and external reference source. Both input types described above are routed to FET-switched multiplexers. The

SAM (Sample) instruction selects one channel at a time for A/D conversion. The selected channel is applied to
& HOLD circuit through a buffer amplifier. The SAMPLE & HOLD circuit (D-BS-AD 2-0-YAD)

the SAMPLE

establishes the level of the analog voltage signal and applies it to the A/D Converter, where a 1 0-bit A/D conver-

sion takes place.

When the conversion is complete, the contents of the conversion buffer are strobed in parallel

The numerical representation of the signal is placed in AC bits 3 through 1 1 the sign is in AC bits
0 through 2. The total time from the selection of a multiplexer channel until the actual word is placed in the
to the AC.

;

AC is approximately
is

1 9 fxs.
The PAUSE flip-flop is set at this time, and the processor waits until the instruction
completed. The program for continuous sampling of channel 1 is as follows:

5-1

SAM

19.2 /as

STA

4.8 /as

XSK

3.2 /as

JMP.-3

3.2 /as

TOTAL

Figure 5-1

30.4 /as

A/D Control General Block Diagram

It can readily be seen that the sampling frequency would be

The high-

1(30.4 x 10'^ ), or approximately 33 kHz.

number of samples is increased,
est sampling frequency for five channels would be approximately 6 kHz. As the
instruction before a SAM instrucThe
ESF
possibilities.
bandwidth
input
the sampling rate is decreased, restricting
tion solves this problem (see FAST SAMPLE).

during a LINC FETCH state.

A single LINC-Mode SAM instruction is used for A/D control

A FAST SAMPLE (special function) instruction, which is a SAM instruction initialized by an ESF instruction, also
institutes an A/D conversion readout to the Central Processor AC.

With a FAST SAM, the order of events is respecified channel (as

the current contents of the converted buffer are transferred to the AC, then the
addressed in the octal code of the current SAM instruction) is selected and a new conversion commences.

versed:

The

time advantage is
results of this new conversion can then be read by a subsequent FAST SAM instruction. A
Processor

Central
realized because less than 1.6 ^xs is required to execute a readout of the conversion buffer to the
that
a previous
provided
With a FAST SAM, the requirement for the CP to pause for 1 9 jUS is eliminated

AC.

SAM instruction has been given and 19 us has elapsed between the previous and current SAM instruction.
When a FAST SAMPLE instruction is decoded and the YADC A D BUSY flip-flop is not set (indicating that a
previous conversion is still in progress), the AC is loaded with the data from a previous instruction by
LOAD IR H (as shown on the YADC print) and a new conversion is started by YADC START H pulse.

signal

YADC

The conversion in progress can be read only when the conversion is done, about 19 fis later, when another FAST

SAM instruction is given.

5-2

12-0037

Figure 5-2

5.4

A/D Control Block Diagram

CP FLOW DIAGRAM DESCRIPTION

SAM Instruction
At T4 of the FETCH cycle, the RECYCLE SYNC flip-flop (dwg. CPT), is direct-set by signals YADC A D RECYCLE L and CPTP TP4 H. YADC RECYCLE L was previously enabled by signals YADC A D PAUSE (1) H,
YADC FAST SAM (0) H, and INS SAM H. YADC A D PAUSE was left set (1) from the previous SAM instruction or I/O PRESET. Simultaneously, YADC LOAD A D IR H is enabled to load YADC IR 07 through
with
1 1

the channel to be sampled. This number is decoded by the A1 31 Multiplexers (dwg. YAD,

YADA, and YADB).

The A/D Control enters a 5 ms settling delay to permit the chosen amplifiers to reach a stable state.

YADC A D
BUSY was set at the beginning of this transition. The trailing edge of the 5 ms delay sets up a ms delay and sets
YADC HOLD. YADC HOLD(l) L is used to begin a HOLD cycle on the A404 Sample & Hold circuit (dwg. YAD)
1

and the 1 ms delay gives the circuit time to stabilize. The negative-going edge of the

ms delay pulse produces a

YADC START H pulse, which initiates an A/D conversion (dwg. YAD).
During the initial 5 ms time delay, CPTP OFF PAUSE H sets CPT T5 RECYCLE, Following this pulse, the occurrence of CPTP TPS will clock a
into CPT TS5 for as long as CPT T5 RECYCLE is a 1. Hence, the CP is held
1

in Time State 5 during the

SAM instruction.

5-3

At each occurrence of a TPS during the SAM instruction, the AC is loaded with the current contents of the A/D
Converter. Signals YAD ADOS through 1 1 are inverted by inverters producing signals YAD ADOS through 1.
These signals, along with the inverted YAD 2 are fed into the adder via PMA BMSC 00 through 1 (dwgs. PRA,
1

PRB, PRC, PRD, PRE, and PRF).

RCL LD AH H is generated every TPS to accomplish this.

The following table indicates the effect of inverting the last 9 bits of the A/D Converter to achieve a 1 ’s complement result in the AC:
Table 5-1
Inversion Effects

A214 Preamplifier

A404 S & H

Input Voltage

Output Voltage

+ 1000

0.000

0000

0777

+.985

0.075

0001

0776

Resulting 10 bits
in A81

Result in AC

+.005

+4.975

0777

0000

-.005

+5.025

1000

7777

.985

+9.925

1776

7001

1.000

+ 10.000

1777

7000

Note that YAD 02 is duplicated on BMSC 00 through 02 (dwg. PMA).

The signal YAD DONE H is generated by the A/D Converter after the result is complete. This signal clears YADC
A D BUSY, YADC HOLD, and YADC A D PAUSE. YADC A D RECYCLE is now disabled. The next occurrence
of CPTP TPS clears CPT RECYCLE SYNC. The next CPTP OFF PAUSE clears CPT RECYCLE, allowing the
following occurrence of TPS to clear CPT TS S and set YADC A D PAUSE. Hence, timing is advanced to a new

memory cycle (TSl), with YADC PAUSE set for the next SAM instruction.
Execution of a FAST SAM instruction permits the programmer to interrogate the contents of the A/D Converter
(left from the previous conversion), strobe this data into the AC, and start a

new conversion. This avoids the

problems incurred with the regular SAM instruction (i.e., lower sample rate, possibility of missing a Request or
an Interrupt during SAM execution, etc.).

As the FAST SAM instruction requires only 1.6 /is for execution, other programming can be accomplished before
returning to initiate another FAST SAM (not less than 18.2 jas). The A/D Control is put into a FAST SAM mode
by performing instruction ESF (0004) with AC05 = 1. This sets YADC FAST SAM. The 5 ms and 1 ms time delay
string are generated in an analogous manner to the regular SAM instruction, but at CPTP TP5D. This allows the
previous contents of the A/D Converter to be strobed into the AC at TPS beforehand (as explained above).
Note that unless A D BUSY = 1 (dwg. PADC), YADC A D RECYCLE L is not generated, and the processor continues to the FETCH state after TPS. If a conversion was in progress, however, when FAST SAM was given, the
CP will recycle in TSS until the conversion is complete, read the final result into the AC at TPS, and start a new
conversion at TPSD.

5.5

SENSE LINE CONTROL

As illustrated in Figure S-3, the PDP-12 contains a total of 16 sense line inputs. These inputs provide the user
with a facility to directly test external conditions such as relay closures, in addition to the normal array of
peripheral I/O devices.

Of the 16 external sense line inputs, three have been defined:

5-4

SXL
SXL
SXL

Key Struck

(KST)
(STD)

(TWO

Tape Instruction Done
Tape Word Complete

The remaining sense lines require an input of +3V, and are reserved for the user to implement in his particular
system. The succeeding program sequence is altered (skipped) under the following conditions:
= 0 and the condition is met

1=1 and the condition is not met

Figure 5-3

Sense Line Control Clock Program

As shown in Figure 5-4, the user’s external sense line inputs are routed through the External I/O Input Bus
(D-BS-EP12-0-IOB). Each of the 16 sense lines is applied to an AND gate (D-BS-EP12-0-SKL). The sense line
inputs are ANDed with the program-requested skip condition indicated by N EQ 00 through 17.

When a sense

N EQ input is also high, SKL X SENSE L is produced (dwg. SKL). SKL X
SENSE L is ANDed with INS SXL L (see SKH print) and the SKIP flip-flop (D-BS-EPl 2-0-SKP) is set if I = 0.
When SKL X SENSE is high, the SKIP flip-flop is set if =
line level is at +3V and the associated

5.6

RELAY CONTROL

The relay buffer is a six-bit register connected to six relays that are mounted on the data terminal panel. The
relays can be used for controlling experiments or external equipment not otherwise directly interfaced with the
PDP-12A Computer. The contact rating of the relays is 2A, at 28 Vdc non-resistive load. One A at 110 Vac
Contact closure time is approximately 20 ms. The condition of the relay (closed
or open) is displayed on the console front panel. The six programmable double-pole, double-throw relays are
resistive load is also acceptable.

activated by LINC-Mode instructions, and can be examined by the AC at any time.

As shown in Figure 5 - 5 the relay buffer register flip-flops are collectively clocked by the same signal (lOR LOAD
RELAYS H). The lOR LOAD RELAYS L signal is enabled by INS MSC H INS N EQ 14 H CPTP TP 5 H. A
pulse (lOR LOAD RELAYS H) to the relay buffer enables the flip-flops to be set to the same states as the corre,

•

sponding AC register flip-flops (bits 6 through 1

only).

)

5-5

•

Figure 5-4

Figure 5-5

When the AC flip-flop is set to

Sense Line Control Functional Block Diagram

Relay Control Functional Block Diagram

the associated relay buffer flip-flop is set, causing the relay to energize.

The

relay buffer flip-flops that are set ground the base junction of a corresponding relay driver/amplifier transistor

(03 through Q8) located on the data terminal panel. The grounded base in turn causes the relay driver-amplifier
to saturate, thereby energizing the relay armature.

Two separate programmed instructions arc necessary to effect a transfer between the AC register and the relays:
a LOAD AC instruction and an ATR (AC to relays) instruction. If the programmer wishes to initiate a rcadback
from the relay register to the AC register, a RTA (relays to AC) instruction transfers the contents of the relay
side of the respective relay
buffer register as follows: The output of the relay buffer to the AC is routed to the
and applies through
FLAYS
H)
signal,
relay
(RCD
FN
R
with
the
enable
ANDed
output
is
buffer flip-flops. The
PRD).
PRA
through
(dwgs.
enable
gates
to
the
through
PMB BMSC 6
1

5-6

DISPLAY CONTROL

5.7

The basic PDP-1 2 includes a rack-mounted 7 x 9 in. CRT display for presenting data in graphic, symbolic, and

An interactive CRT display of data stored in memory or on tape is provided by use of the
LAP6-D1AL program. Sample analog inputs or stored data in memory can also be presented in graphic form on
alphanumeric form.

either of the two channels on the VRl 2.
nel Select switch to Channels

Waveforms can be displayed simultaneously by turning the VR12 Chanand 2. The Display instruction (DIS) brightens a spot in a 5 1 2 x 5 1 2 array at

specified coordinates, x: (vertical) and y (horizontal).

The Display Character instruction (DSC) brightens spots in

a subarray of 2 x 6 points, according to the pattern held in memory.

Alphanumeric and other characters are

generated on a point-by-point basis at high speed.

An optional display can be driven in parallel with the display scope for additional display capability.

If desired,

two different displays can be presented on each scope.

The potentiometer control knobs (numbered 0 through 7) mounted on the data terminal panel, while not
directly related to the display system, can be used by the operator to set or vary
display parameters used by the
program (for example, to determine the size or position of the display). These potentiometers are directly con-

nected to input channels 0 through 7 of the multiplexed A/D conversion system.

The X and y deflection voltages are derived from fully buffered 9-bit (0 to 6V) D/A Converters. These analog
output voltages are available on the 24-contact blue ribbon connector of the data terminal panel, allowing
the
user to connect an auxiliary scope (VR 1 2, Tektronix 503, or similar unit) for remote display
of the same information sent to the PDP-1 2 display.

The pin assignments are;
1

Channel Select

Shield Ground

GND

Y HQ Ground

Shield Ground

Y Deflection

Intensified Pulse

Shield Ground

GND

13-18

Not Used

Shield Ground

503 Intensify

X HQ Ground

GND

X Deflection

Shield Ground

22-24

Not Used

The output drive capability of the D/ A Converters is -0.3V to -6V, which is capable of driving a load resistance
of IKfl connected to ground. This allows up to 200 ft of cable for a remote display
scope. These analog outputs
can also be used forx-v plotters, auxiliary scope display, or any voltage-controlled device.
Figure 5-6 shows the relationship of the LINC Scope Control (VC 12) to the CP and to the

VRl 2 Point Plot Dis-

The VC 12 Control allows the CP to continue with the main program without consuming any more CP time

play.

than the time necessary to decode the DIS or DSC instruction.

Only when a new DSC instruction is given while the previous instruction is still being executed by the
Display
Control, does the CP have to wait. Only the VCl 2 is covered in this manual; consult the
VRl 2 Point Plot Display
Maintenance Manual, DEC-CR-H6AA-D for information pertaining to the operation and

maintenance of the VRl 2.

The Display Control discussion is divided into four functional parts (see Figure 5-7):
a.

Timing — discusses the clock and delay circuits that control the order and sequence of events.
Character Generation — discusses the addressing (.v-axis and .v-axis coordinates) and shifting of
intensification bits (display characters or spot).

5-7

Addressing — discusses the location on the Display Scope Face at which the Display Character or the
intensified spot occurs.

Data Handling — discusses the relationship between the bit word and the character or spot displayed.

Figure 5-6

Display Control General Block Diagram

TO VRI2
Y-AXIS
DEFLECTION

TO VRI2
X-AXIS

DEFLECTION

Figure 5-7

Display Control Block Diagram

Timing

5.7.1

In the previous paragraphs, the Display Control
circuitry was described awfully buffered. Fully
buffered in this
context ni^ans that the Display Control itself initiates
the timing or sequence of events. The CP can
then advance
continue on with the next programmed instruction.
The
actual time consumed by
tn
he CP IS 4.8 to 6^4 ms. A single DIS, however, requires
3.2 ms for execution, and not less than 25
ms for completion. Thus the CP would be idle for an
unacceptable period of time if there was not a separate
timing function
the Display Control circuitry itself. There are four
distinct time intervals required for the display
of an alphanumeric character or single point. The Display Control
and D/A Converters are initialized for these time periods
dunng the LINC EXECUTE (dwg. PDP-12-0-17 and
-18), and EXECUTE 2 (dwg. PDP- 12-0-20) cycles.

Display Instruction

The DIS instruction enters the EXECUTE cycle with the
instruction appearing in the memory buffer
(MB) and
instruct, on register (IR) of the CP. At TPI of
the EXECUTE
cycle, the

a-repster containing horizontal coordinate information

MA is loaded with the address of the

by RCL LOAD MA H. The MB is loaded with the
contents
he o-register when the I-bit - 0 (bit
7), or the contents incremented by
if 1=1 by RCL LOAD MA H at
TP3

This specifies the horizontal coordinate.

The INTERNAL PAUSE flip-riop will hold the processor
accomplished by CPT INT PAUSE being set at TP3 by

in TSS if the display was previously

BUSY

This is

DSC BUSY H and DSC or DIS during an EXECUTE cycle.

The absence of CPT INT PAUSE (0) H will now inhibit

further generation of CPTP TPS. Hence, the computer
is
complete, CPT EN INT PAUSE H will enable
generation
of CPTP n/riifnen
OFF PAUSE u
H and CPTP TPS to clear CPT INT PAUSE and advance timing to the
next memory cycle

C^P

EXECUTE cycle, display registers are set up to intensify the point. DSX

CHAN IS loaded from MBOO to choose which of two VR
are loaded with the honzontal coordinates

2 ( 1 4) channels are to be utilized.
stored in the MB, DSX HA9 and 10 are set to I

hence, all horizontal information will be displayed

DSC SET IN

through 1 1 register and V7 through 10 (dwg, DSC

sets DSI INI 1 to enable a single point
to be intensified

on the CRT by two dots.

At »is time the vertical coordinate is loaded into the DSY V3
K) are c eared,

DSX H3 through
and 0 respectively

later,

DSC ACTIVE

lirng (d'wg."va

DSC Instruction
The DSC instruction enters the EXECUTE cycle with
^

the instruction appearing in the

MB and the IR. When the

“"'ains a character pattern obtained from P-class addressing

PdTiTo- eT"'*"

(dwg.

As seen on PDP-1 2-0-17, the processor will go into an
action IS described above.

Internal Pause mode if the Scope Control is busy

This

The same initializing of registers occurs during TSS,

with the exception that the MB is loaded into the
intensity
horizontal registers, and DSC ACTIVE is not
set. The EXECUTE 2 d-register 1
of the current instruction field (which contains
the horizontal coordinate) is addressed.
T2 loads the AC9 (which
contains the vertical coordinate) with a
30« and 1
offset, which replaces the last few
bits of the given coordinate
s ensures proper vertical spacing
between displayed characters, and causes characters
to appear on the same
horizontal plane. T3 puts the sum of the contents
of )3-register 1 and an offset into the MB. This
is done for the
same reason as above, and is described in more detail
in Paragraph 5.7.2. The horizontal
and vertical offsets are
loaded into the AC and MB (dwgs. PMA through
PMF) via the BMSC and TMC gates (dwg. PMB) They are enab ed with signals RCA DSC SET AC H and SLA
DSC CNT MB H. The status of DSC SiIe, which is L, with
bit 4 of the AC and the ESF instruction,
determines whether a full-size (AC04 =1). or half-size offset
is to be
register rather than the channel and

instituted.

decrfmentedZ VA?an^^
is

(dwg. DSX) with the MB (horizontal coordinate)

ney f “"u I”"™"'"'

and clears V8 through

m“>=mented and

the next instruction

fetcir
5-9

Display T1
2-0-4 occurred simultaneously with T5 of the previous
The Initial Point Set-up Delay indicated on drawing VC
INITIAL DELAY L.
EXECUTE (DIS) or EXECUTE 2 (DSC) cycle. It will last 25 ps, as determined by DSC
1

Display T2

movement is allowed when doing a DSC. When the PRR
Display T2 is a 1.5 ms period in which a point-to-point
increased to 7 ms. However, if bit 1 1 of the
Switch (located on M7 1 1) is in the SLOW position, the period is
to 0.5 ms. Start timing is shown on drawreduced
is
period
intensity register = 0 (no point to be intensified), this
H and DSC ACTIVE (1) H. SHORT
DELAY
INITIAL
ing DSC. The START input to the clock is caused by DSC

CLOCK 2 speeds up this period when necessary.
Display T3
Display T3 is the intensification interval.
at

The CLKl OUTPUT becomes high and an intensification pulse occurs

DSC INTEN H if DSI IN 11 ( 1) H is true. This output will be positive, going negative,

switch is - (negative). The intensity

if the

polarity

on the M7
pulse width is determined by the setting of the WIDTH switch

Module, 0.5 fis if MIN., 10 ms if MAX.
Display T4

and intensification registers are modified before
This time interval is a non-adjustable 8 ms period where the x. y,
H, which shifts the intensification register
SHIFT
DSC
generates
intensifying the next point. CLK 2 (dwg.

DSQ

right one place.

DSX HA9 is complemented by the shift pulse (moving
be complemented
is off (half-size characters), HA 0 will
SIZE
If DSC

Hence, a new bit appears in DSI IN 1 1.

the X coordinate 4 dot places right or left).
10 H).
by the shift pulse as well (via DSC

As HA9 and HA 10 are entered as opposites, the net effect of this
HA
= 0, the point is on the left side of the
dot by only 2 horizontal positions. When HA9

operation is to move the
no changes to the vertical (Y) register are
character in the same horizontal plane as the previous point. Hence,

When HA9=(1), we are again intensifying
or 4 (full-size). This action is seen on
(half-size)
by
incremented
2
be
must
a right point and the vertical register
When the intensifiDSC and DSY. Control returns to Display T2 until all points have been displayed.

necessary (note the error on VC 12-0-4, Rev. C and previous issues).

drawings

out), the point or character is complete and DSC
cation register is completely cleared (all points have been shifted
is a 1-dot case of the DSC instruction in
instruction
DIS
that
a
Note
ACTIVE is cleared, terminating the display.
this control logic.

(Character Generation

5.7.2

by six (vertical) grid on the scope display
Characters are generated by intensifying points within a two (horizontal)
12-bit operand. When the operand is obtained, each bit in
face, according to the bit configuration of a selected
within the intensification grid (see Figure 5-8).
the intensification shift register controls one of 1 2 specific locations
not intensified conversely if bit 1 1 is 1 the
of the intensity register is 0, the corresponding grid point is
display instructions (DSC), a second
character
consecutive
two
programming
associated point is intensified. By
six overall grid. Through proper
by
four
a
producing
thus
first,
the
of
six grid is displayed to the right

If bit

;

two by

selection of operands, the combined grids can now display letters

of the alphabet, numbers, and symbols meaning-

ful to users of the PDP-12A (see Figure 5-9).

5.7.3

Addressing

of accurately controlling where (on the
Providing a visual display, whether video or graphic, requires a means
this is accomplished by the Display
PDP-12A,
the
In
place.
take
to
surface of the displaying media) the display is
Addressing function.

The PDP-12A Display Control uses the rectangular coordinate method of locating

the position on a CRT screen

which contains a total
where a particular display will occur. For this reason, the PDP-1 2A Video Display (VRl 2),

5-10

usable display area of 58.5 sq. in. (6.5 x 9 in.), is divided into a grid of 5 1
2,o x 5 1 2,o points. The horizontal
distance between points is 0.0176 in.; the vertical distance is 0.0127 in. Therefore, the
location of any point on
the screen can be expressed in terms of the vertical and horizontal point locations. (See
Figure 5-8.)

POINT

Figure 5-8

(0 + 377)

POINT

(BIT 6)

(BIT 0)

POINT

(BIT 7)

(BIT 1)

POINT

(BITS)

(BIT 2)

POINT

(BIT 9)

(BIT 3)

POINT

(BIT 10)

(BIT 4)

POINT

(BIT II)

(BIT 5)

Bit Positions of DSC Instruction

RECTANGLE ARRAY 6.5 "BY 9'
OF 10000 X 10000 POINTS

(777,+ 377)

(5l2|o X 5l2|o)

(

0 0
,

)

(777, 0

)

7
(0,-377)
'(777,-377)

Figure 5-9

Display Point Location

In addressing any single point or group of points (characters),
the horizontal (x-axis) and the vertical (y-axis)
coordinates must be provided. This is accomplished in the Display Control
circuitry by two 9-bit words held in
the vertical and horizontal registers, respectively.

Before display occurs, the display location is determined by the addressing function of the Display Control circuitry
(Figure 5-10). The circuitry is comprised of two 9-bit registers that supply the horizontal and vertical coordinates.
Both of the registers have individual bit (9 each) D/A Converters. These converters establish the proper voltage
levels (fully-buffered) that position, on the display

CRT or other display surface, the display character or an intensi-

fied spot.

TO VR-12
VERTICAL
DEFLECTION
CIRCUITS

TO VR-12

HORIZONTAL
DEFLECTION
CIRCUITS

TO VR-12 Z-AXIS (INTENSITY)
CIRCUITS

Figure 5-10

Display Addressing Block Diagram

In addition to providing the display address, the vertical and horizontal registers and associated D/A Converters
are incremented by the Display Control circuitry so that the intensified points comprising the character matrix

can be uniformly separated and displayed in the correct format. This separation results in display characters that
are large enough to read, and also provides for two different sizes of displays. The approximate heights of the
characters are 0.3-in. and .15-in., respectively.
In addition to point separation (resulting in the two display character sizes), the addressing function allows the
control circuitry to increment the two registers in both the vertical axis O) and horizontal axis (x), so that ade-

quate spacing results between characters and between lines of characters (see Figure 5-11). This automatic spacing
and 30g points
is accomplished by adding lOg points (full-size) and 4 points (half-size) to the horizontal register
(full-size) and 14g points (half-size) to the vertical register; thus the progression of characters and intensified points

appear right-reading, with proper line separation.

The DIS instruction belongs to the a instructions. The DSC belongs to the
point, DIS a is used.

class instructions.

Display of a single point on the scope with location x = 525 and y

following program:

5-12

To display a single

= 240 would use the

*20

CLR

/CLEAR AC, LINK, MQ
/PLACE HORIZONTAL

SET I 5

/LOCATION IN 5

525

LDA

/PLACE VERTICAL

/LOCATION IN AC

240
DIS 5

/DISPLAY POINT AT COORDINATES SPECIFIED BY
/SET AND LDA INSTRUCTIONS

/DISPLAY POINT AGAIN

JMP.-l

When the DSC instruction is used, the vertical coordinate is held in the AC. The horizontal coordinate is held in
register 0001

When a DSC instruction is executed, the following events occur:
a.

The display intensification pattern is transferred fromy to the Display Control intensification
buffer.

The contents of bits 3 through 6 of the AC are placed in the Display Control y buffer:

bits

7 through 1 1 of the AC are set to 30g for a full-size character.
c.

The contents of register 0001 (the x-coordinate) are incremented by lOg and transferred to the
Display Control x-buffer.

Symbols may be displayed using the LEFT and RIGHT SWITCHES with the following program. The LEFT
SWITCHES generate the pattern for the left half of the symbol matrice shown in Figure 5-11, and the RIGHT

SWITCHES generate the right half.

EXAMPLE TO SCALE
OF THE LETTER "a"

©o©©
©®©
®©®©
0® ©
®® 0
Figure 5-1 1

2 CONSECUTIVE DSC

INSTRUCTIONS
1st

HALF.C(Z-REGISTER)
4477 OCTAL

2nd HALF.C(Z-REGISTER)

7744 OCTAL

Display, Letter

5-13

4020/BEGIN
BEGIN,

/POINTER FOR WORD
/POINTER LOCATION -1
/GET LEFT SWITCHES
/STORE IN FIRST ADDRESS
/GET RIGHT SWITCHES
/STORE IN SECOND ADDRESS
/DISPLAY FIRST HALF ADDRESS +

SET I 3
0067

LSW
STC 70

RSW
STC 71

DSC I 3

/SPECIFIED BY

DSC

/DISPLAY SECOND HALF ADDRESS +

/SPECIFIED BY

CLR

(3
1

/CLR

/RESTORE HORIZONTAL
/JUMP RESTART

STC
IMP BEGIN
1

Memory location I contains the h-bit plus the horizontal coordinate; the AC contains the vertical coordinate.
The following table provides a list of pattern words for character display.
Table 5-2
Pattern Words for Character Display

4477
7744
5177

4577
4145
4477
4044
4136
2645

1077

7710
4543

/A
/B

2651

4136

2241

4177
3641

3077

7741

4142
4076

1077

4324
177

0523
500

4177

0000
2040
0410

4477
3044
4276
376
4477
3146

5121

7741

4163

2000
2077
3410
1010
0

4040
4077

177

7500

7402
677

/BACK ARROW

2050
50
404
437
605

/SPACE

0
/-

404
404
1

6006
60
3614
1436

0
601

/NUMBER SIGN

4030
4136

7721

/DOLLAR SIGN

3641

7701

4677

2101

1463

1446

177

6130
5166

6314
770

6341

7701

/APOSTROPHE

4651

176

7741

301

6151

7730
3077
7706
4177

0041

4523

5-14

2151

Table 5-2 (Cont)
Pattern Words for Character Display

5.7.4

Data Handling

The Data Handling function of the PDP-12A Display Control is concerned with the relationship between the
operand (the data character word or display point) and the character or spot displayed. The Data Handling
function is comprised of the intensification shift (z-axis) register, the clock, gating, and control signals. Control
of the Data Handling function is through timing and display. See Figure 5-12.

The z-axis register holds the operand, whether it is a full 12-bit character word or simply a point. The action of
the z-axis register is explained first for a DSC instruction and secondly for a DIS instruction. The purpose of the
clock and gating is to sense the state of bit 1 1 of the z-axis, to generate intensification pulses concurrent with a
logical

state, and to withhold an intensification pulse if the content of bit 11

is in

the 0 state.

A START pulse

received from display control and timing that enables the display clock, (dwg. DSC).

then routed through a Channel Select switch (one or two or both) to the VR12 Display and/or a remote display,

The intensification pulse

During the execution of DSC instruction, the z-axis intensity register holds the data character word for display.
This is accomplished by systematically shifting right and examining the contents of bit 1 1 of the z-axis register.
If the current content of the bit location is a logical 1, an intensification pulse is generated for .5 ps; if the current

content of bit 1 1 is a logical 0, no pulse is generated. Next, the register is shifted one place to the right, the content of bit 10 is located in bit 11, bit

sensed again, and the process is repeated until the entire z-axis register

contains all Os. This entire operation takes 15 to 51 ps, depending on the number of logical Is initially deposited
in the z-axis register.

NOTE
The instruction setup requires either 4.8 or 6.4 ps. The Display
Control then allows 25 ps for point coordinate settling, 1 ps for
each unintensified point, and 3 ps for each intensified point.

When no points remain to intensify, the display process is completed, leaving the vertical and horizontal coordinates of the

D/A at the last intensified point of the DSC instruction.
5.8

PDP-1 2 SPEAKER

The PDP-1 2 Speaker is mounted on the rear of the A/D (0 through 7) panel; the volume control is mounted on
the left front side of this panel. The speaker is included in all system configurations and, although not strictly a

LINC device, is included in this section.
The speaker frequency is dependent on the frequency of change of ACOO. Each time ACOO changes, an output is
generated unconditionally to the speaker.

5-15

i?-00?9

Figure 5-12

Data Handling Block Diagram

A block diagram of the speaker and its control is illustrated in Figure 5-13. The speaker capability can be
illustrated by the following program (START 20, 8 Mode).

0020

7001

5020

INCREMENT AC
JUMP START

5-16

1
I

—

“
1

C-CS-700059 64-0-1
I

12-0241

Figure 5-13

Speaker and Control

5-17

CHAPTER 6
LiNCTAPE CONTROL SYSTEM

6.1

INTRODUCTION

This chapter, together with the referenced documents, provides information on the principles of operation of the

Type TCI 2 LINCtape Control and associated tape transports Types TU55 or TU56. This chapter assumes a prior
knowledge and understanding of the PDP-1 2 Central Processor (CP) and the TU55/TU56 Tape Transports.
6.2

GENERAL DESCRIPTION

The LINCtape System (Figure 6-1) is supplied with the basic PDP-1 2A and -12B Computer Systems, and serves as
an auxiliary magnetic tape data storage facility.

The LINCtape System stores information at fixed positions on

magnetic tape similar to a magnetic disk or drum storage device, rather than at unknown or variable positions as
in conventional magnetic-tape systems.

This storage facility provides for replacement of blocks of data on tape in

a random fashion, without disturbing previously recorded information.

Specifically, during the writing of infor-

mation on tape, the system reads format (mark) and timing information from the tape, and uses this information
to determine the exact position at which to record the written information.

The same mark and timing infor-

mation is used to locate data to be read back from the tape.

BASIC LINCTAPE SYSTEM
(2TU55S OR

TU56 DUAL TRANSPORT)

Figure 6-1

LINCtape System Configuration

6-1

that operates directly into core

The PDF- 12 LINCtape Control is an independent, fully-buffered tape processor
Break) facility.
memory on a cycle-stealing basis, with the CP using the Tape Break (Single-Cycle Data

A maxi-

mum LINCtape configuration comprises eight TU55 Transports or four TU56 Dual Transports (see Figures

6-1

format tape will carry 131,000 words, thereby
6-2, and 6-3) and the TCI 2 LINCtape Control. Each standard
adding up to an additional one million words of accessible storage to the computer.
are directly executable by the tape processor.

Figure 6-2

TU55 LINCtape Transport

Figure 6-3

TU56 T ape T ransport

All LINCtape instructions

the CP waits until a tape operation is complete before continuing.
If programmed he the No Pasisc
Mode, the CP can continue with the program as soon as the LlNCtape instmction
has been interpreted and the

Normally,

operation initiated.

6.3

REFERENCED DOCUMENTS

The Digital Equipment Corporation documents listed in Table 6-1 contain material

which supplements the information contained in this chapter. These documents are supplied with each
PDP-1 2 Computer, or may be obtained
from the nearest DEC field office, or from the main office:
Digital Equipment Corporation
1

46 Main Street

Maynard, Massachusetts
Table 6-1

DEC Documents
Doc. No.

Title

DEC-12-SRZA-D

—

Description
|

PDP-1 2 System Reference

Programming and operating information for the

Manual

PDP-12, including brief instnictions on the TCI

LlNCtape Control. Also a partial LlNCtape library
system and list of the LlNCtape utility routines.
DEC-1 2-HR2A-D

PDP-1 2 Maintenance

Information on installation and mainteTiarice, in-

Manual Vol. II

eluding the LlNCtape Control. Also trouble-

j
1

shooting and repair and replacement.
\

DEC-12-HR3A-D

PDP-1 2 Maintenance

A complete collection of the PDP-1 2 Engineeriiig

Manual Vol. Ill

Drawings.

PDP-12 Maintenance
Manual Vol. IV

A complete collection of all module schematics

Type TU55 Tape Trans-

Transport drive logic and internal operations, plus

DEC-12-HR4A-D

H-TU55

port Maintenance Manual

preventive and corrective maintenanxc instructiens.

Type TU56 Tape Trans-

Same as the TU55.

H-TU56

port Maintenance Manual
6.4

—

SPECIFICATIONS

A summary of the characteristics of the LlNCtape Control and associated equipment is listed in Tabhe 6-2.
Table 6-2

Summary of Equipment Specifications for the LlNCtape Control
Tape Characteristics and Density
a.

Tape Density; Approximately 420 bits/in.

Each word is assembled in approximately

Tape speed is approximately 80 in. per second

Data block transfer rate is approximately 30 ms

20 qs

NOTE
Transfer rates vary by 20% as the effective reel diameter
changes.

6-3

Table 6-2 (Cont)

Summary of Equipment Specifications for the LINCtape Control
Addressing
a.

Mark and timing tracks allow searching for a particular block.

Time
a.

Start time is 1 50 ms ± 15 ms; stop time is 1 50 ms ± 15 ms.

Turn Around time is 200 ms ± 50 ms.

Input Signals to Transport from Control

Commands

FORWARD

Normally complementary levels

REVERSE

Normally complementary levels

STOP

ALL HALT

(Stop transport)

Unit Select

Select unit 0 through 7

Information

Analog Write signals to the tape heads

Output Signal from Transport to Control

WRITE ENABLE

Control

(Ground level assertion)
Analog Read Signals from the tape heads

Information

Environmental Conditions

Thermal Dissipation

2150 BTU/HR

Operating Temperature

50° - 95°F ambient

Humidity

10% — 90% relative humidity

NOTE
The magnetic tape manufacturer recommends 40% — 60%
relative humidity and 60° — 80°F, as an acceptable operating
environment for LINCtape.

6.5

LINCTAPE FORMAT

6.5.1

Track Arrangement

LINCtape uses a 5-channel format. To reduce bit dropout and minimize the effect of skew, each channel is redundantly recorded on two nonadjacent tracks of the 10-track LINCtape (see Figure 6-4). The five LINCtape
channels include: a timing channel (simultaneously recorded on tracks 1 and 10); a mark channel (tracks 2 and
9); data channel

(tracks 3 and 6); data channel 2 (tracks 4 and 7); and data channel 3 (tracks 5 and 8).

Information is transferred between the tape and the LINCtape Control through a 10-track Read/Write head.
Series connection of corresponding track heads within each channel and the use of Manchester phase-recording

techniques, rather than amplitude-sensing, virtually eliminate dropouts.

6.5.2

Word Assembly and Disassembly

When reading, the tape Read/Write Buffer (RWB) register assembles 12-bit computer length words from four
consecutive 3-bit lines read from the data channel tracks (DC1-DC3) of tape (see Figure 6-5). At the same time
the mark track is decoded to specify whether the current

6-4

2-bit word represents a data word, a block number, or

TAPE TRANSPORT BASE PLATE

3 /4

Figure 6-4

Track Allocation Showing Redundantly Paired Tracks

FORWARD TAPE MOTION
CM

REDUNDANT
CHANNELS
NOT SHOWN

NOTE:

NUMBERS 0 THRU 11 ARE THE BIT POSITIONS OF THE
ASSEMBLED 12-0IT DATA WORD IN THE RW0 REGISTER
12-0223

Figure 6-5

tape control information.

Structure of

2-Bit Data Word (4 Tape Lines)

The LINCtape Control uses timing signals from the timing

reading of the mark track, and reading from, or writing

Control disassembles 1 2-bit words and distributes the
cessive data channel lines (see Figure 6-5),
is

track to synchronize the
on, the data channels. During data writing,
the LINCtape

bits in such a manner that they are

recorded on four suc-

A checksum* is recorded after the data (at the end of the block) and

used during subsequent checking operations to verify

the data.

^Checksum — See Paragraph 6.6.4.

6-5

6.5.3 Overall LINCtape Format

Figure 6-6 shows the overall format for a standard reel of LINCtape. Each reel of standard LINC-formatted tape
contains the following primary areas:
a.

Leader of blank tape

Front end zone

Data area

Interblock zones

End zone

Trailer of blank tape

The tape leader and trailer are nothing more than approximately five ft of blank tape that is provided to protect
the data storage areas of tape while installing, threading, or removing tapes on the transport hubs.

The end zones,

both front and back, provide additional protection to the data areas, and, in standard computer-programmed tape
operations, the detection of an end zone either reverses the tape motion, or brings both reels to a complete stop

without pulling the tape off the trailing reel. The front interblock zone and the negatively numbered front blocks
provide block separation and buffering for Tape Acceleration, Turnaround, and Search operations.

532, „ BLOCKS

}

FULL

LEADER

[

TAPE

(BLANK)

END
ZONE

BN INTERBLOCK

INTERBLOCK
ZONE

boiSg 1014a

ZONE

END
ZONE

TRAILER <
(BLANK)

(

aooog

512, n

USEABLE BLOCKS

END

INTERBLOCK

END

MARKS

Figure 6-6

Standard LINCtape Format

The beginning of a block of tape data is indicated by the forward block mark. When the mark decoder senses a
block code on the mark track, the Read/Write Buffer register contains the number of that particular block. Blocks
-lOg through -1 and blocks lOOOg through lOldg on a standard LINCtape provide a turnaround area and are not
available to the programmer for data assignment, although the format is identical to that of block 000 through

777g

These additional blocks allow smooth searching and turnaround when accessing the blocks at the begin-

ning and the end of the tape. Following the last data block is another end zone, and, as mentioned above, this

segment provides protection to the data areas and prevents running beyond the formatted area of the tape.

LINCtapes are subdivided permanently into blocks by the initial marking process (MARK

2), or formatting

which records a fixed pattern on the tape. This pattern includes fixed block addresses that permit addressing the
information stored on tape by means of a block number. Information is transferred and checked in units of

complete blocks that are specified by their block addresses. Each block includes a checksum for verifying the
integrity of information transfers with the tape.

Standard LINCtape contains lOOOg (512i o) addressable blocks numbered consecutively from 000 through 777g.

Each block on a standard LINCtape contains 400g (256i q) data words corresponding to the contents of onequarter of a LINC Mode core memory field (1024i o-word field of memory in LINC Mode). See Figure 6-7.

The first core memory address involved in the data transfer is the first address within the specified memory quarter
(see Figure 6-8). Quarter 0 begins with address 0, quarter 1 with address 400g, and so on, up to quarter 7, which

begins with address 3400g.

6-6

BLOCK • 1 QUARTER OF A

MEMORY field
(256,o) LOCATION S

£1^0.00

nT*'

”

FIELD

01
1

BANK

OF MEMORY

REEL LINCTAPE
CONTAINS 512in

FIELD OF

FIELD 02

MEMORY 200 O 9

> 10,0000

14096,0

LOCATIONS

0024, q) LOCATIONS

BLOCKS

BL0CK=1/4 FIELD
OF LINC MODE MEMORY

FIELD 04

FIELD

extended
MEMORY

ETC.
'

UP TO
32,768,0
LOCATIONS
OR 8 BANKS
12-0225

Figure 6-7

LINCtape Reel to Memory Comparison

6.5.4 Non-Standard LINCtape

The length of blocks as well as the format of the block addresses can be varied by using a
non-standard marking
program. Once a given tape is marked, however, the format is fixed for that tape unless
it is completely erased
and re-marked.

6.5.5 Detailed LINCtape Block Format

Figure 6-8 illustrates a detailed single LINCtape block and a portion of the
adjacent areas. Each area of the
block, along with its associated mark track code, is shown. Starting at the left
is the forward block number area

PDP-12 LINCTAPE FORMAT
1

DM
255

1111

1110

0 0

512 DATA

BLOCKS

data

three EACHi
I

0 0

FIVE

EACH

DqDi Dz Ds
D4 Ds De D7

Ds DgDioDn
|

PROTECTS
THE BLOCK

NO. WHEN R/wl

IDENTIFIES
[

THE BLOCK

DATA WORDS

WHEN WRITING,! 2's COMPLE-| REVERSE BM
SIGNALS CP
MENT SUM
USED TO
at final
OF ALL DATA IDENTIFY
MARK THAT
WORDS PLUS BLOCK WHEN
CHECKSUM IS THE
TAPE IS
THE NEXT
CONSTANT
BEING
WORD (CM)
7777=0000.
SEARCHED IN
NEXT 2CMs
THE REVERSE

PROVIDES
BLOCK
separation

0000-0777

(STD LTAPE)

CURRENT IS
TURNED ON al
OFF OR WHEnI

[

SWITCHING

FROM R-»W
OR W-*R

[

I
I
I

INSURES
WRITER CURRENT IS OFF
BEFORE REV

|bmis
ENCOUNTERED

DIRECTION.

NOTES
READ AND WRITE DATA ONLY IN THE FORWARD DIRECTION. CAN READ BLOCK NUMBERS
IN EITHER DIRECTION (FORWARD OR REVERSE).
2 MARK AND DATA TRACKS ARE WRITTEN AND ARE READ IN BINARY FORM
THE CHECKSUM IS WRITTEN IN COMPLEMENT FORM (BY PHASE).
1

Figure 6-8

{

Standard LINCtape Detailed Format

6-7

BM (51ock Mark), which is identified by its unique mark track code. Recorded on the three data channels
(disregarding the redundant tracks) is the block number, a 12-bit word that identifies this particular block.

Note

that every word on the tape occupies four lines or columns.

NOTE
The recording technique and arrangement of the Read/Write
Buffer register is explained in Paragraph 6.6.3.

Continuing from left to right, the next area is the guard word, GM (Guard Mark). The guard word protects the
adjacent block number area from transients when the Read/Write current is turned on and off, and allows time
for the tape processor to switch Read, Write, or Search Modes.

Following the guard word is the data word abbreviated DM and FM (Data Mark and Final Mark, respectively).

The data word is the information recorded on tape from core memory. The final data word (FM) is specially
identified to signal the mark track decoder that this is the end of the current data block.

The final data word is followed by three check words, CM (Check Mark). The first checksum word contains the
checksum (recorded complement of the sum of data words). The CM also guarantees that the data writers will
be turned off before the reverse block number area is encountered by the tape heads. The next two Check Mark
areas, which contain the mark track identification for checksum words, provide an additional buffer area to

protect the reverse block number (RBM) which follows the third checksum word.

The reverse block number, RBM (Feverse Flock Mark) is used to identify the block when the tape is being searched
in the reverse direction.

The next five words comprise the interblock zone IM (/nterblock Mark). When an IM has been decoded by the
mark track decoder, and, if the IBZ instruction has been programmed, the tape processor signals the CP and the
main program can be interrupted to allow the CP to skip to a tape service routine.
6.5.6 LINCtape Standard Format Summary

Table 6-3 presents a summary of the standard LINCtape format; listed are the various zones of LINCtape, the

number of words in each zone, and the function of each zone.
Table 6-3

LINCtape Format Summary

Number of Words

Mark

Function

1024

Front End Zone

4096

First Intermediate Zone

Forward Block Zone Number

GM
DM

Guard Word

255

FM
CM
(R) BM
IM j

/ per block

First 255

Data Words

Final Data Word

Check Marks

Backward Block Number

Second Intermediate Zone

2048

6-8

Back End Zone

LINCTAPE TRANSPORT

LINCTAPE

CONTROL TC12
CENTRAL PROCESSOR

TRANSPORT
CONTROL

tape unit select, direction a motion

BINARYTIMING READ

“~1

TIMING TRACK
READER/WRITER

READ/WRITE OR CHECK INSTRUCTIONS

-TAPE TIMING

MARK FF(1)

(LIN)

TIMING

BIT-7 (MOTION)

GENERATOR

TPO-4

MOTION
a
TAPE UNIT

(LTS.LTT)

READER/WRITER

MARK WRITE
WINDOW REGISTER!
3
DECODER

MAINTENANCE COMMANDS
(LTS.LMU.LTD.LTC)

CHECK /BLOCK
M ARKS

MOTION
DELAYS

Tmotion

MAINTENANCE
REGISTER
a
DECODER

TAPE MODE
CONTROL

RWB SHIFT
1

READER/WRITER

^WB 0-3

WRITE FF

WRITE FF(1)

PHASE SHIFT
READER/WRITER
BUFFER REGISTER

DATA CHANNEL 2

TAPE
.h-t
MEMORY

REQUEST
MB a AC
(LCS.LTS.LRE
LRL.LIP.LGP)

y1_J

READER/WRITER C^RWB

\r|

—

8-11
j

-WRITE FF(1)

XT. OPS. INSTR

(XOB)
12-BITS
(LCX.LCXF)

PROGRESS
a PAUSE

V\jMBLK,,TBLK/ EXT. ADD.

TAPE MEMORY
ADDRESS SETUP
REGISTER
12-BITS

12- BITS

ACCUMULATOR
EXTENDED ADDRESS FORMAT

12-BITS

LTRA-F)

ADDRESS

ADDER

BLOCK NUMBER
vi(LTRA-F)|

TAPE BUFFER
REGISTER

(LTRA-F

(T8)
12-BITS

READ/SEARCH
A.

CHECKSUM

DATASUM + CHECKSUM (TRANSFER SUM)
TAPE
TB-»TAC->TAC

ACCUMULATOR

TAPE BLOCK

(TAC)
12-BITS

NUMBER
BLOCK ADDRESS

(LTRA-F)

TWO SERIES -CONNECTED

(LTRA-F)

BLOCK ADDRESS

MEMORY BUFFER
REGISTER
(MB)

READ/WRITE HEADS
(LTRA-F)

READ/WRITE DATA WORD

® TAPE BREAK REQUEST® MB a AC ENABLE
{

INCREMENT

2-BITS

N
^

ENABLE

4-BIT
SERIAL SHIFT

WRITE FF(1)

DATA CHANNEL 3

ADDRESS
TAPE BREAK

(RWB)

READER/WRITER

FROM CP

ACO-7 MAINTENANCE

DATA CHANNEL

(LTM.LTMR)

(LWN)

TRACK J

(INR)

BITS 7, 9,10 ail

EXTENDED
OPERATIONS
BUFFER

TPO-4
MAG. TAPE

INTRUCTION
REGISTER

WORD INSTR,

EXTENDED OPERATIONS COMMANDS

END/INTERMEOIATE
LINE COUNT

MARK FF(1)

TAPE
INSTRUCTION
REGISTER
4 -BITS

3-BITS

(LIN)

.MARKS

MARK READ

BIT-8 (TAPE UNIT SELECT)

CONTROL LOGIC

TT0K.TT1

MARK TRACK

TO-OCTAL
DECODER

LTR)

(3)

PROGRESS a PAUSE

12- BITS

CP CONTROL
I

NOTES

CONTROL SIGNAL PATHS SHOWN ABOVE ARE FOR FUNCTIONAL PURPOSES
ONLY
REFER TO DATA FLOW DIAGRAM (FIGURE
AND DATA FLOW DISCUSSION.
LETTERS ENCLOSED IN PARENTHESIS
SHOULD BE PREFIXED WITH "TC12-0-( 1"for TOMPI ftp
DRAWING REFERENCE DESIGNATOR FOUND IN VOLUME Ht SYSTEM
DRAWINGS.
)

(

)

12 - 0227

Figure 6-9

LINCtape Overall Block Diagram

6-9/6-10

Table 6-4 provides a summary of LINCtape channel (tape) assignments.

Table 6-4

Mark Track and Channel Assignment
Mark Track Codes

(R)

End Mark

0000

nil

Interblock Mark

BM
BM

1110

Forward Block Mark

GM
DM
FM
CM

0111

Reverse Block Mark

0010

Guard Mark

1001

Data Mark

1011

Final Mark

0001

Check Mark

—

Timing Track

DDDD
DDDD
DDDD

Data Track 1

Data Track 2

DDDD

Data Track 6

Channel Assignment

MT
DTI

DT2
DT3

DT6
D = Data bits (4 lines)
6.6

nil

Mark Track (see code above)

Data Track 3

BLOCK DIAGRAM DISCUSSION

Figure 6-9 shows an overall functional block diagram of the LINCtape Control. Data and control signal paths

have been simplified for the purpose of this discussion.

A source-route-destination discussion of data flow is

presented in Paragraph 6.6.4.

Timing pulses for tape operations are generated from signals provided by the timing tracks; these signals are read

by the timing track tape head (actually 2 heads in series). The Read/Write outputs are used to generate tape
pulses TTO through TT4, which synchronize and control all LINCtape operations once the CP has initialized the

tape processor, and proper tape speed is achieved.

Mark track data is used to locate specific areas on the tape. These marks identify block zones, intermediate zones,
check zones, and beginning- and end-of-tape areas. Mark track decoding is accomplished by the Window register

and mark track decoder. Outputs of the decoder go to the motion and tape unit control and the tape mode
(Major State) control logic. The motion and tape unit control logic selects a particular tape transport and deter-

mines the tape direction for the selected tape transport. The tape instruction, a two-word instruction from the
CP, is deposited in the tape instruction register (first word) and the TBN register (second word).

A conventional

binary-to-octal decoder determines the specific tape operation to be performed, i.e., a single block read (RDE) or

perhaps a group instruction: Write and Check Group (WCG).

NOTE
Extended Tape operations and Extended Addressing Tape
operations are discussed in Paragraph 6.6. 1

Once the CP has supplied the two-word tape instruction, the tape processor assumes complete control of the tape
operation and generates all necessary command, control, and timing signals to complete the tape operation.

6-11

Data bits are read from and written onto three data channels of tape (disregarding the redundant tracks). The
data are assembled (during a Read) and disassembled (during a Write) in the Read/Write Buffer register (RWB).

One line of tape is read by the data channel tape heads to produce three corresponding bits in the RWB register
(see Figure 6-1 0).

The data in the RWB are then shifted left one place, and three more bits are read from the tape.

After four Read-And-Shift operations, the RWB register contains a complete 12-bit word, read from four lines of

Data is also written on tape three bits at a time from the RWB register in a similar (though reversed) man-

tape.

ner as in the Read operation. The RWB register sends tape information to the tape buffer (TB) during a Read

operation and receives the 12-bit data word from the TB during a Write instruction.

Extended Operations

6.6.1

The Extended Operations facility allows transmission of data between tape and any program-defined area of

memory. Extended Operations are controlled by the contents of the Extended Operations Buffer (XOB), which
in

turn must be loaded from the CP accumulator prior to giving the first word of the tape instruction to the tape

processor.

The miscellaneous instruction AXO loads the XOB from the Central Processor AC.

The specific operations that can be performed from the Extended Operations facility are:
a.

Extended Memory Addressing

Mark Condition

Enable Tape Interrupt

Maintenance Mode

Enable Extended Address Mode

Do Not Pause During Execution

Hold Unit Motion

Extended Units

MAJOR TAPE REGISTER BUS
12-0226

Figure 6-10

Read/Write Buffer Interface Diagram

6-12

Unlike the other data or control registers, the XOB is not located on the register bus modules, but on various
modules throughout the tape processor. The following paragraphs discuss the functions of the XOB register with
the corresponding AC bits (see Figure 6-11).

—

EXTENDED OPERATIONS BUFFER (XOB)
0

Figure 6-1 1

777

LiJ jj

Extended Operations Buffer Bit Assignments

Extended Memory Addressing (XOB 0-2) - The three most significant bits, 0 through 12, are the Extended
Memory Address bits. See the TCI 2-0-LCXF Block Schematic discussion. Central Processor AC bits 0 through 2
are loaded into tape field flip-flops 0 through 2, thus designating the 4K memory field to be addressed.

Bit

NOTE
XOB 3 is not used.

Mark Condition (XOB 4) — The MARK flip-flop (shown in drawing TCI 2-0-LCX) is used in conjunction with the

MARK switch on the operator’s console to allow the MARK 2 program to format virgin or previously marked
The MARK flip-flop can be set only when MARK 2 program running and the MARK swdtch is depressed
1

tape.

by the operator, thereby minimizing the possibility of accidentally destroying a tape format by enabling the

MARK flip-flop.
Enable Tape interrupt (XOB 5) - When this flip-flop is set (TCI 2-0-LCX), a Program Interrupt will occur whenever the Interrupt is enabled and the Tape Done flag is set.

Maintenance Mode (XOB 6) — When this flip-flop (TC12-0-LTM) is set, all timing signals and data are prevented

from entering the tape control registers from the tape unit Read/Write circuits. Instead, lOT instructions are used
as input to the tape control to simulate the functions of the tape head and processor.

In addition to the lOT

functions shown on drawing TCI 2-0-LTMR, Appendix F of the System Reference Manual contains a listing of
tape maintenance functions.

all the

Enable Extended Address Mode (XOB 7) - When this flip-flop is set (TCI 2-0-LCX), the limitation of block-to-

memory quarter transfers no longer applies. The transfer is executed as follows:
1

The contents of the TMA Setup register are placed in the TMA.

The second word of the tape instruction is taken as an

The transfer is effected between tape and designated area of the memory field specified by bits 0 through
2 of the XOB discussed above.

6-13

1-bit block number and placed in the TBN.

Do Not Pause During Execution (XOB 8) — When this flip-flop is enabled (TCI 2-0-LCX), the CP continues with
the main program after the tape instruction is initiated.

Hold Unit Motion (XOB 9) — This flip-flop (TCI 2-0-LCX) when set, keeps the tape unit in motion after the completion of the instruction, even though the unit is deselected (logically).

Extended Units (XOB 10-1 1) — The preunit flip-flops (TCI 2-0-LMU) select one of up to six additional transports
(units 2 through 7) which may be part of the tape system.

Refer to Page 3-47, Paragraph 3.6.7 of the System

Reference Manual.

6.6.2 Extended Addressing

Extended Address format is used for tape operations with nonstandard formatted tape. The standard LINCtape
format, as described in Paragraph 6.5.3, is not used.

To address more than lOOOg tape blocks, the second tape

instruction word requires more than the nine bits allotted in standard LINCtape format. In Extended Addressing,
therefore, the second word is allotted

bits for addressing the desired data blocks.

Group instructions (transfers

of more than one data block per tape operation) cannot be performed in this mode. In the Extended Addressing

mode of operation, the number of data words in a block can vary (400g words in a standard LINCtape block).
Prior to issuing the tape instruction, the first Memory Address in the data transfer is loaded from the AC and

placed into the

TMA Setup register, using the instruction, TMA. The second word of the tape instruction is

taken as an 1 1-bit block number (bits 1-11), and placed in the TBN. The transfer is effected between tape and
the designated address of the 4096-word memory field which is specified by bits 0 through 2 of the Extended

Operation Buffer (XOB). The transfer is thus independent of the LINC Memory Field Assignments. The CP may
pause or not pause during an Extended Addressing operation, depending on the state of bit 8 of the XOB.

NOTE
A standard MARK program is available for

29 words per block,

and up to 2000g blocks per reel of tape.

The address for an Extended Address operation is provided before the tape instruction is given.
class instruction is given, loading the CP accumulator, which in turn is loaded into the

the

1-bit address.

A miscellaneous

TMA Setup register with

The tape instruction is then given and the operation is performed.

As in all Extended Memory operations, whether with tape or some other mass storage device, data transfers will
not cross 4096, o memory bank boundaries; address 1111

followed by address 0000.

6.6.3 Basic Read /Write Discussion

The functional diagram of the Read/Write logic for the LINCtape Control is shown in Figure 6-12. Each channel
of the Read/Write circuitry contains a logic level converter and input gates, a Write amplifier governed by the
flip-flop outputs, and a Read amplifier.

Read inputs are paralleled with the Write amplifier outputs across the

head, allowing the Read amplifier to respond to signals from both the tape head and Write amplifier.

The Read amplifier is a high-gain differential amplifier augmented by a transient positive feedback. When a signal
of either polarity is sensed by the head, the Read-amplifier outputs switch immediately and are asserted, thus
preventing head cross-talk (simultaneously writing the data channels, while reading the timing and mark tracks).

The Read amplifier outputs U2 and V2 are standard DEC logic levels of -3V and ground (negative logic).

6-14

1 St.

2 nd.

NOTES:
Polaritiss shown on gates ore true when the

RWB is shifted and LC2 (0) (also,
not in the Chechword

major state). In the
example, the result isANDed with RWB 00
considered at. At TPO LC2 will complement

therefore,LC2—»0 and PHASE —»L. The
Input to the Write amplifier complemonfs,changing polarization on the tape from
*L
*R.

R—

toL—

1Z-02Z9

Figure 6-12

Read/Write Simplified Logic

When input E2 is more positive than D2, the output V2 is asserted at ground and U2 is negative; when D2 is more
positive, the output levels are reversed.

Due to the positive feedback, the Read amplifier oscillates in the absence

of changing input signals. The Read amplifier output waveforms are therefore rectangular whenever the differential input signal is indeterminate (see

Figure 6-13).

The Write amplifier is a saturated grounded-emitter push-pull amplifier, with its outputs resistive-coupled through
pins J2 and K2. If enable level (pin R2) is asserted negative, the Write amplifier is governed entirely by the state

of the flip-flop.

When the flip-flop is 1, K2 floats while J2 is returned through the resistance and saturated outWhen the flip-flop is 0, J2 floats while K2 is negative. In the two tracks corresponding to

put collector to -1 3V.

each channel on tape, information is recorded in a manner that makes Read signals from the two head inductors
reinforce on playback.

6-15

WRITING

LOAD(TTO)

,,,
'

RWB SHIFT LEFT

COMPLEMENT (TT3)

(2)

(3)

DATA (GND=1)

(4)

RWB OUT

WRITE CURRENT

(6)

READ AMPL OUTPUTS

Tr~1

n_i

f~i

L~]

MOVES
I

r~i

MOTION

TAPE

L_n

POLARIZATION,

n_j
L_rn_j

DIRECTION OF

—— — —
1_
—
—
L_n_j— ru—
—
—n
—
I

TLJ

(5)

(7)

LEFT-TO- RIGHT RELATIVE TO TAPE

THIS CHANNEL

READING

(

)

HEAD VOLTAGES

(9)

READ AMPL OUTPUTS

(10)

RWB SHIFT LEFT (TT3)

(TTO)

<’1>

D read
I

NOTE

Pins shown ore on the

G882 Module

Figure 6-13

Read/Write Logic and Waveforms

The two inductors can be considered as a single-head inductor, the winding of which is center-tapped to ground,
and which reads and writes in a single track.

When the Write flip-flop contains 0, current flows from ground through the head inductor into K2, and the
polarization of the head core is oriented clockwise.

The tape polarization, as the tape moves across the head, is

oriented down (left-to-right), regardless of the direction of tape motion. Similarly, when the flip-flop contains
a

tape polarization is oriented down regardless of the direction of tape motion. When reading, the current in1
duced in the head by a change in polarization flows opposite to the current required to cause the same change;
,

consequently, the current induced by a left-to-right (L-R) tape-polarization change is a current flowing out of
the head toward pin E2.

The head is a source; therefore, when a terminal is a current source, it is positive. Thus

a L-R tape-polarization change causes the Read amplifier input E2 to be positive; consequently, V2 is ground

and

U2 is negative. In like manner, the right-to-left (R-L) polarization change induces a positive signal at D2 and results in

V2 being asserted negative and U2 at ground.

The Manchester phase-recording technique used in the LINCtape Control requires two pulses to write each bit on
a Load pulse which is a TB ^ RWB or a LRL SHIFT RWB and occurs at TTO, and a Complement
pulse
which is LTS PHASE H and occurs at TT3. Therefore, for the purpose of this discussion, the two pulses will be

tape:

referred to simply as the Load pulse and the Complement pulse respectively.

The Load pulse loads the Write flip-flop with the value of the bit to be written (Read/Write Buffer register bits
4, and 8, which are written simultaneously).

Depending on the state of the Write flip-flop (see Figure 6-12), the

Load pulse may or may not cause a magnetic polarization change to take place on the tape. The Complement

6-16

pulse however, causes a tape magnetic polarization change.

It is this loading (RWB shift) and subsequent
complementing (PHASE), occurring alternately at 15-jus intervals, that cause full magnetic polarization changes

on the tape.

When reading, the logical value of a recorded bit is detected by sensing the tape head inductor output as the
polarization change passes over the tape head inductor.

and 1 1 with the RWB shift pulse.
took place.

The output level is clocked into RWB-register bits 3, 7,

If the logical value was a

a right-to-left (R-L) tape magnetic polarization

If the logical value was a 0, a left-to-right (L-R) polarization took place.

As shown in Figure 6-13, the Load and Complement pulses alternate. This relationship is shown in lines 1 and 2
and occur at approximately 1 5 -ms intervals. Line 3 shows a string of consecutive bits to be written on tape. In
line 4, the Write flip-flop receives each bit at a Load pulse and assumes the opposite state on the Complement

pulse.

In line 7, the direction of tape magnetic polarization is labeled as R and L for right and left, respectively.

The
R-L and L-R transitions are detected by the Read amplifier as negative and positive half-sinusoids at pin E2

(opposite polarity at pin D2). If the tape is read in the same direction as written, the tape position corresponding
to the time that the Write flip-flop was complemented will show a R-L change as a 1

;

a L-R change as a 0.

The

tape head voltages at Read amplifier inputs pins E2 and D2 are shown in line 8; the Read amplifier outputs are

shown in line 9. During reading operations, the Load (RWB shift) pulses in line 10 (TP3) coincide with those in
line 2 which complemented the Write flip-flop when writing.

sults in a ground level at

into the

The R-L polarization change, representing a 1

U at the time of the Load (shift) pulse. Consequently, as shown in line

1 1 ,

re-

is shifted

RWB as the first bit read.

If the tape is read opposite to the direction in which it was written (when for example, reading reverse

block

numbers) the magnetic polarizations reach the head gap in reverse order; that is, the head senses a L-R change

where a

was written, etc. The contents of the mark channel are selected to the advantage of this condition.

Data written in one direction and read in the opposite direction will be complemented (see Figure 6-14).
6.6.4 Tape Processor Register Description

The following paragraphs discuss the major registers of the TCI 2 LINCtape Control as shown on the PDP-12
LINCtape Flow Diagram (see Figure 6-15).
Tape Accumulator (TAC) — The

2-bit

TAC serves as the arithmetic register in the tape processor. When reading

the datasum* is computed in the TAC and added to the checksum** read from tape to determine if the data
transfer was accurate.

When writing, the datasum is also computed in the TAC and, when the final Data Mark

signal is detected, the resulting datasum is written on tape in complement form (checksum).

The contents of the

TAC (transfersum***) can be read into the CP accumulator, using the LINC-Mode TAC instruction. AC contents
equal to minus zero indicate an accurate transfer. During SEARCH operations, the computations to determine
the desired block number are performed in the TAC.

Tape Buffer (TB) - The Tape Buffer is an intermediate register primarily used to hold all the tape data from the

RWB register. The TB receives the 2-bit tape word from the RWB register during a Read operation, and transfers the tape word to the RWB register during a Write operation. During the Read operation, when a
tape word
1

* Datasum - 2’s complement of all the data words

in a block.

**Checksum - complement of the datasum, written on tape immediately following the Final Mark.
***Transfersum — contents of TAC after comparing a new datasum with the checksum previously written on the tape.

6-17

10 10

1
1

DT3

DT2

DTI

COMPLEMENT

0 000

0 10

DT3

(COMPLEMENT
OBVERSE)
A
010101010 OBVERSE^ NOT
COMPLEMENT, BUT

010101010

REVERSE ORDER

COMPLEMENT
OBVERSE

••

TAPE DIRECTION FORWARD

(

TAPE DIRECTION REVERSE (•

NOTE

HEAD DIRECTION)
HEAD DIRECTION)

;

The reverse block number is written on tope in obverse form
when the tope is formotled by the MARK 12 progrom.

Figure 6-14

Reading A Block Mark

to be transferred to the CP, a 12-bit parallel transfer is made from the TB to the CP memory buffer.

When

writing, the direction is reversed; information from the CP memory buffer enters the TB, and is transferred to

the

RWB register for disassembly onto the tape.

Read/ Write Buffer (RWB) - The Read/Write Buffer register is a three-section shift register which corresponds to
the three lines of data on tape (see Figure 6-5).

During a Read operation, the RWB is loaded in four discrete

operations three bits at a time. After the RWB has been loaded and shifted the fourth time, the fully assembled
1

2-bit tape word is parallel-transferred to the TB.

During a Write operation the RWB is loaded in a single 1 2-bit

parallel transfer from the tape buffer, where it is sequentially disassembled in four operations, three bits at a time,

while being recorded on tape.

Tape Block Number (TBN) — The Tape Block Number
tape block to be accessed in a data transfer.

2-bit control register is loaded with the number of the

As the tape is searched, the block number read from tape is com-

pared with that in the TBN. During group operations, the TBN contains the number of the first block to be
accessed.

Tape Memory Address (TMA) — The Tape Memory Address 12-bit control register holds the Memory Address

TMA is loaded from the TMA Setup register at
TMA is loaded with IF 3 and 4 or DF 3 and 4, and
and 2. The TMA is incremented by
GPO and GPl depending on the quarter of memory defined by MB bits 0,

accessed during a data transfer. In Extended Address Mode, the
the beginning of a tape instruction. In standard mode, the

for each data word transferred.

6-18

Diagram

DIAGRAM

Flow

FLOW

LINCtape

PDP-12
LINCTAPE

6-15

Figure

PDP-12

6-19

TMA Setup Register — This

2-bit register defines the first address in memory to be accessed in a data transfer

when operating in Extended Address Mode. The TMA Setup register is loaded from the CP accumulator with
the MSC I 3 instruction.

Extended Operations Buffer (XOB) — This 12-bit control register selects the various extended tape operations.
These operations include extended memory addressing, tape interrupt, the no-pause condition, hold
motion, and
extended tape units (tape units 2 through 7). The XOB is loaded from the CP accumulator. Refer
to Paragraph
6.6.1, Extended Operations.

LINCtape Instruction Register and I Bit — This 3-bit register is loaded with the three least significant

bits of the

CP instruction register (IR), and decoded to determine the particular tape operation to be performed. The I-bit
flip-flop is loaded from bit 7 of the CP instruction register.

This flip-flop determines whether or not the selected

tape unit will stay in motion after completion of the tape instruction.

Tape Bus Gating Network - All data transfers occurring in the LINCtape Control to and from the CP,
exception of the RWB and the selected tape unit Read/Write heads, are implemented through
gating network (see Figure 6-15).

with the

the major-register

The network contains a separate gate structure and common register input bus

for all 12-bit parallel transfers. Transfers between registers within the LINCtape
Control, as well as transfers into

and out of core memory, occur via the tape bus that is the output of the adder logic.

6.7

SYSTEM DRAWING DISCUSSION

The following paragraph is divided into seven areas; each keyed to one of the specific LINCtape Flow or

Timing

diagrams (D-FD-TC12-0-10 through D-FD-TC12-0-16) which comprise the Major State flow

and timing of the
LINCtape Control logic. The discussions and referenced drawings present an overview of the tape
processor

operations. Detailed discussions concerning the specific logic are presented in Paragraph

6.8 (Block Schematic

Discussions).

6.7.1

Tape Processor Major State Flow (TCI 2-0-10)

A brief description of the five Major States of the TCI 2 Tape Control illustrated in TCI 2-0- 10 is presented below:
IDLE:

As the name implies, no tape operation is currently under progress. However,
the tape processor control logic is ready to receive a tape instruction from the
CP. Although the tape processor logic is inactive, a tape transport can be moving
although it is not logically selected.

If,

during execution of the WRC, WRG, RDG,

and RDC instructions, a bad checksum results, the IDLE state will be entered
after each block transfer, and then the

SEARCH:

SEARCH state, to repeat the instruction.

The SEARCH state is entered only from the IDLE state. The tape processor is in
this state when searching for a desired block. When the desired block
is found and
the selected tape transport is moving in the forward direction, the BLOCK state
is

BLOCK:

entered.

The BLOCK state can be entered only from the SEARCH state with the TAC EQ
7777 * FWD * BM * TP2 signal. The tape processor remains in this state while
performing all data transfers with the CP.

6-20

CHECK WORD;

The CHECK WORD state is entered from the BLOCK state with the BLOCK (1)
*

TP2 signal. When all of the data constituting a block is transferred, the tape

WORD state, indicating that the checksum is acThe CHECK WORD flip-flop controls the phase of the checksum
written on tape. See drawing TCI 2-0-LTS and its description, Paragraph 6.8.1 5.
processor enters the CHECK

cessed on tape.

TURN AROUND:

The TURN AROUND state is entered from the CHECK WORD state with 1 = 0*
CM * CHECK WORD { ) * TP 1 Its main function is to stop the tape transport
at the completion of a tape instruction when the I bit is not set.
1

6.7.2 Timing Diagram Discussions

The timing diagrams flow horizontally from left to right with the timing references shown vertically.

LIN C tape Instruction Setup Timing (TCI 2-0-1 1) — Shown on the LINCtape Instruction Setup Timing drawing
are:
a.

The interrelationship of timing between the tape processor and the CP.

The two major timing setup pulses of a tape instruction execution; MTP SETUP and MTP SETUP 2.

Time of events and order of events beginning with receipt of a tape instruction through tape transport
unit selection, direction, and motion control.

The execution of any tape operation by the LINCtape Control requires the sequence of events (some of which
are conditional, depending upon the specific instruction), as depicted on the Instruction Setup drawing.

The Instruction Setup Timing drawing shows the interrelationship between time states of the CP (the lower half
of the drawing) and the tape processor (the upper halD- Note that no attempt was made to scale the time refer-

ence going from left to right across the drawing. The events depicted on this timing diagram occur during the
initializing of the tape processor by the CP when a tape instruction is issued.

MTP SETUP (magnetic tape setup), conditions the tape processor to receive the first word of the two-word tape
instruction (TCI 2-0-LIP). This process occurs at TS5 of the CP FETCH cycle. Several tape processor actions

take place:

The PRE U2 flip-flop is loaded with bit 8 of the Instruction Register (TCI 2-0-LMU).

The Tape Instruction Register (TINR) is loaded (TC12-0-LIN) and the PROGRESS flip-flop is set
(TCI 2-0-LIP).

The tape processor is forced to the IDLE state and the Window register is initialized (TC12-0-LWN).
If the HOLD MOTION flip-flop is set, the tape UNIT EN fiip-flop (TCI 2-0-LMU) is cleared.

During TS4 of the CP EXECUTE cycle, the following tape processor events occur:
1

(MTP SETUP 2);

The Central Processor MB, which contains the starting block address, is enabled (bits 3 through 1
(TC12-0-LRE).

If an Extended Addressing Format Tape operation is to be performed,

MB bits 0 through 2 are also

enabled.

AT TP4 of the EXECUTE cycle of the CP, the MTP SETUP 2 pulse is generated and the following occurs:
1

The IN PROGRESS flip-flop (TCI 2-0-LIP) is set, enabling the tape processor to begin the tape
instruction.

Central Processor MB bits 3 through 1 1 (0 through 1 1
is

set) are loaded into the TBN, and

if the EX ADD FORMAT flip-flop, TC 2-0-LCX
MB bits 0 through 2 are loaded into the GROUP Register

(TC12-0-LGP).

6-21

Instruction Field 3 and 4 and Data Field 3 and 4 of the CP are loaded Tape Instruction Field 3 and 4

(TC12-0-LCXF).
After MTP SETUP 2, the tape processor is completely in control of the tape operation. If the NO PAUSE flipflop (TC12-0-LCX) is not set, the CP pauses in TS5 and awaits a Tape Break Request as shown on drawing

TC12-OLIP.

A series of Motion Delay pulses are generated by the tape processor, as shown on drawing TCI 2-0-LTD;

MTN DLY clears the MOTION flip-flop if a new tape transport unit to be selected.
MTN DLY 2 deselects all tape transports and clears the UNIT EN flip-flop (TCI 2-0-LMU).
3. MTN DLY 3 loads the UNIT (tape transport select flip-flops and clears the DIRECTION flip-flop
1.

(Reverse), and selects the new tape unit (conditional).
4.

MTN DLY 4 sets the UNIT EN and the MOTION flip-flops, if the selected tape is in an operational
condition.

LINCtape Search Timing (TCI 2-0-1 2) — Shown on the LINCtape Search Timing drawing are:
1

The sequence and timing of tape processor actions during a SEARCH for a particular block address.
Address Setup calculations for the current block transfer. Normal LINCtape format non-group. Normal

LINCtape format group, and Extended Format.
Before any tape transfer can be performed, the desired block (address) of data must be located.

Following the events described in the Instruction Timing Setup, the tape processor enters the SEARCH state. As
shown on the SEARCH Timing drawing, the mark track is being scanned; when a Block Mark or Reverse Block

Mark (depending upon transport direction) is sensed and decoded, the following events occur:
1.

TSO enables the RWB register, which contains the block number.

The TB is loaded with the contents of the RWB at TPO.

At TP4, the TMA is loaded with the first Memory Address to or from which the data is being transferred.
In Extended Address mode, the

TMA

loaded with the contents of the TMA Setup register.

At TSl enable the TAC and TB, and load the TAC, performing the addition of both at TPl. The TAC
contains the desired block number and the TB contains the block number just read from the tape which
is in complement form. The TAC should contain 1111
^ when the desired block is located on the tape.

When the desired block is located and the transport is moving in the forward direction, the BLOCK state
is

entered. If the block number read is not the desired block, the tape transport either continues in the

same direction, or the direction is reversed, depending on the status of bit 0 of the TAC.
For the MTB instruction the PROGRESS flip-flops (TCI 2-0-LIP) are cleared, terminating the instruction, and the contents of the

TAC are transferred to the Central Processor AC if NO PAUSE is cleared

(CP IDLE) (TC12-0-LCXF).

The format shown as “ADDRESS SETUP GATING” is as follows:
(TINRl

= 0) and (QNO = 0) then (TIFO-2 ^ TFO-2) and (T1F3-4 ^ TMAO-1) and (QNl-2 ^

(0->TMA4-ll).
a.

TINRl
TINRl

= 0, indicates a nongroup instruction
= 1, indicates a group instruction

QNO = 0, indicates the operation involves the instruction field
QNO = 1, indicates the operation involves the data field

(QN = quarter number is stored in the GP register)

6-22

TMA2-3) and

If performing a group instruction, the second term of the above sample would be:

TAC9 = 0, indicating the operation involves the instruction field, or
TAC9 = indicating the operation involves the data field
TIFO-2 -» TFO-2, or TDFO-2 ^ TFO-2 identifies the particular 4K memory field involved.
1

TIF3-4->TMA0-l, or
TDF3-4 ^ TMAO-1 identifies the field or memory bank.

1/4 of the LINC memory field.

QNl-2 -» TMA2-3, identifies which quarter number of which

In Extended Format, the

TMA Setup

TMA.

The upper two Address Setup Gating expressions constitute the nongroup instructions, consisting of RDE, RDC,
WRI, and WRC.

The second two Address Setup Gating expressions constitute the group instructions consisting of RCG, WCG,
and non-data transferring instructions:

MTB and CHK.

The Extended Format instructions consist of AXO, XOA, TMA, and TAG.
Block Mode Reading (TCI 2-0-1 3) -The Block Mode Reading timing diagram shows the functions performed

when executing Read instructions when in the BLOCK and CHECK WORD states.
The events depicted on this drawing occur when the tape processor is performing the following Read instructions
and the desired block is located:

RDE
RDC
RCG

Read Tape
Read and Check

Read and Check Group

Observing the drawing from left to right, the Guard Mark (GM) is detected by the mark track decoder

(TC12-0-LWN) and serves as a buffer area. The RWB is shifted left
channels are shifted into bits 3, 7, and 1

place at TP3, and data from the three data

of the RWB.

When a Data Mark (DM) is decoded during a Read operation, the following functions occur:
1

The RWB is enabled at TS4 and is loaded into the TB at TP4.
At TSO, the TB and TAC are enabled; the data word in the TB and the partial datasum is in the TAC.
At TPO, the TAC is loaded (TAC * TB ^ TAC), and the TAPE BRK REQ flip-flop (TCI 2-0-LIP) is set,
requesting a TAPE BREAK cycle from the CP.

If the CP is paused, it leaves the

TAPE BREAK

PAUSE state and enters the TAPE BREAK state. If the CP is not paused, the

state is entered at the end of the current instruction.

Timing is now referenced to the CP (CP

timing).

TMA is transferred to the M A.
cleared.
incremented and the TAPE BRK REQ flip-flop
2. At TP2, the TMA
enabled on the tape bus and loaded into the MB at TP3 for deposit in memory. The
3. At TS3, the TB
1.

At TP

the

CP pauses again at TS5 and waits for another Tape Break Request. This is repeated for all Data Marks
(DM).
After the first Tape Break, the CP pauses in the TAPE BREAK state for the completion of the block transfer.

When a Final Mark (FM) is encountered, indicating the last data word in the block, the identical operations are
repeated.

6-23

After the FM, the Check Mark (CM) is encountered. This signifies that the checksum has been read and is in
the

RWB register.
1.

The checksum is loaded into the TB at TP4 and added to the TAC at TPO.
is equal

to zero, the

If the

NO PAUSE flip-flop

TAC is loaded into the AC at TPl.

The CHECK WORD state is entered at TP2. For a RDE instruction, if the (transfer check) TAC equals
7777g the PROGRESS and IN PROGRESS flip-flops are cleared at TP4. If the TAC is not equal to
7777g the PROGRESS and IN PROGRESS flip-flops are cleared at TP2 of the next CM, thus terminating the instruction. For the RDC instruction, if the TAC is not equal to 7777g the complete
tape
,

operation is repeated until the TAC does equal 7777g. Then the PROGRESS and IN PROGRESS
flip-flops are cleared, terminating the tape operation.

Block Mode Write (TCI 2-0-14) — Shown on the Block Mode Write timing diagram are the operations of the

tape

processor executing the Tape Write instruction:

WRI

Write Tape

WRC
WCG

Write and Check
Write and Check Group

NOTE
It is assumed that the correct block has been located on the

tape (see SEARCH timing, TCI 2-0-1 2).

When the desired tape block has been located and the transport is moving in the forward direction, the BLOCK
state is entered and the following tape processor events occur:
1.

The WRITE SYNC flip-flop (TCI 2-0-LCS) is set with the next TPl pulse after entering the BLOCK
state, and the

WRITE flip-flop is set with the following TPS pulse.

The line counters (LCOO and LCOl) are both set with BM * TP4.

After two counts (LCOO (0) LCO 1 ( 1 )), the TAPE BRK REQ flip-flop (TC 1 2-0-LIP) is set.

When the CP enters the TAPE BREAK state, data is read from the address specified by the TMA and is
loaded from the MB into the TB register.

The TB is added to the TAC at TPO to generate the datasum. The TB is also transferred to the RWB

At TPS, the outputs of the RWB register bits 0, 4, and 8 are complemented, thus writing the first line
on tape. To complete the writing of a 12-bit word on tape (4-lines), the RWB is shifted left 3 times,

and the output of RWB bits 0, 4, and 8 are complemented after each shift.
This sequence of events continues until the FM is decoded from the mark window (TCI 2-0-LWN)

and the fol-

lowing events occur:
1

The datasum (which has been computed in the TAC) is loaded into the TB, transferred to the RWB,
and written on tape in complement form.
At TP2 * FM, the CHECK WORD state is entered, controlling the PHASE level (TC12-0-LTS) which
controls the writing of the checksum.

When the CM is decoded from the mark track, the WRITE SYNC and the WRITE flip-flops are cleared and the
Write amplifiers are disabled.

For a WRI instruction, the WRITE CYCLE flip-flop and the PROGRESS flip-flop are cleared, indicating the
completion of the instruction. For a WRC instruction, the WRITE CYCLE flip-flop is cleared and the
check
portion of the instruction is performed (see Block Mode checking). For the WCG instruction, if
the GP EQ
GPCNT flip-flop (TC12-0-LGP) is on a zero, the group count register is incremented and another block is written.
This process is continued until the GP EQ GPCNT flip-flop is set, (1). Then the check portion
of the instruction
is

performed.

6-24

Block Mode Checking (TC12-0-15) - Shown on the Block Mode Checking timing diagram are the
the tape processor when executing a

operations of

CHK (Check one Tape Block), and the check portions of the WRC and WCG

instructions.

The functions of the tape processor when executing the checks are similar to the Read instruct’ons (TCI 2-0-1

except for the absence of the data transfers to the CP.

No tape processor operations occur during a GM. When a DM is encountered, the following events occur:
1 .

The RWB is enabled at TS4 and is loaded into the TB at TP4.

At TSO the TB and TAC are enabled.

The TAC is loaded at TPO (performs the addition of the TB and TAC).

The above action is repeated with each DM and the FM; thus, the datasum is now computed in the

TAC.

When the CM is encountered, indicating that the checksum has been read, the following events take place:
1.

The three functions in 1, 2, and 3 above are repeated.

NO PAUSE flip-flop is cleared:

The TAC is enabled on the tape bus at TSl.

The tape bus is loaded into the Central Processor AC (TAC

AC).

The CHECK WORD state is entered at TP2.

For a CHK instruction, the PROGRESS flip-flops are cleared, terminating the instruction.
If a

WRC instruction is being performed, and the contents of the TAC is not 7777a (indicating a bad check), the

WRITE CYCLE flip-flop is set, the SEARCH state is entered, and the current block is rewritten and checked
again.

This sequence continues until a good transfer check (TAC = 7777g

) is

obtained.

WCG instruction is being performed, the same functions occur as for the WRC. Each block in the group is
checked and, if a bad transfer check is obtained, the WRITE CYCLE flip-flop is set, and
the current block and
the remaining blocks in the group are rewritten and checked until a good transfer
check is obtained for the total
If a

number of blocks in the group.
Mark Timing (TCI 2-0- 16) — Shown on the Mark Timing diagram are the functions of the tape
executing the

MARK

processor when

2 tape formatting program. Accomplished when formatting virgin tapes are the following:

Recording the Timing tracks (tape tracks 1 and 10)

Recording the Mark track codes (tracks 2 and 9)

Numbering the blocks both forward and reverse (tracks 3 through 8)

The first three waveforms: mark clock, time counter 01, and time counter 00 (TC12-0-LTS)
establish the
necessary timing intervals for the timing tracks. The mark clock is a M401
Variable Clock, an RC-coupled multivibrator which produces timing pulses at a repetition rate of
7.5 ^ls (±5%) when enabled from the Mark flip-flop
(TC12-0-LCX). Fine adjustment can be made from an internal potentiometer (see tape
adjustments). The time
counters constitute a simple frequency divider which will provide the 1 /as timing
pulse
separation necessary for
5
the timing track.

LTS TIME WRITE (TC12-0-LTS) - is a

5-/as square wave that is recorded

and TP3 when read from the tape.

6-25

on the timing tracks to generate TPO

PHASE (TC12-0-LTS) — provides a signal to introduce the magnetic polarization when writing in the mark and
data channels.

Mark Window Register {TC12-0-LWN) — controls the format written on the mark track.

It is loaded

from AC bits

8 through 1 1, shifted left, and recorded serially to give the necessary control marks which define the areas on
tape.

6.8

BLOCK SCHEMATIC DISCUSSION

The remaining paragraphs contain detailed discussions of the LINCtape Control logic. Each discussion of the
referenced block schematic drawing (Volume III, D-BS-TC 1 2-0-LCS through D-BS-TC 1 2-0-LWN) also calls out
the signals and logic levels originating or interfacing with other modules, for purposes of clarity.

It is recom-

mended that the reader read Paragraph 6.7, this manual, before utilizing the 6.8 discussions, to ensure a complete
overview of the operations of the LINCtape Control.

6.8.1

Tape Control States and Instruction (TCI 2-0-LCS)

The five Major Tape State flip-flops: IDLE, SEARCH, BLOCK, CHK WRD (Check Word) and TURN ARND
(Around) and their respective enabling logic are shown. In addition, the WRITE AND WRITE SYNC flip-flops
and associated control logic are shown and discussed.

IDLE — There are five conditions in which the IDLE flip-flop is set and hence, the IDLE major state
entered;
1

TAPE PRESET (Power Clear, ESF and AC7 ( ), lOT 6 52 and ACo ( ))
1

MTP SETUP (Start a tape instruction)
LTT CLOSE WINDOW (Tape timing is not correct)

CHECK WRD (1) * IN PROGRESS (1) * TPl when the tape instruction is not completed in the
CHECK WORD state; (WRC, WRG, RDG)
5. TURN ARND (1) * TP2 (End of tape instruction).

SEARCH — The SEARCH flip-flop is set when the tape processor is in the SEARCH state (indicating that it
is

searching for the desired block number on tape).

It is set with

the first TPl pulse, and cleared when the

FWD * SEARCH * TP2). For the MTB
cleared when the first Block Mark (BM) is encountered on the tape (MTB * BM * TP2).

desired block is located on the tape (with the signal TAC = 7777 *
instruction, it is

The SEARCH flip-flop, along with the BM signal (TCI 2-0-LWN), is used to generate the signals necessary
to perform the initialization of the line counters and the setup of the

TMA register.

BLOCK — The BLOCK flip-flop is set with the same signal that clears SEARCH. The BLOCK Major State is
entered only from the SEARCH Major State.

It is set

during all active data transfers with the CP and is one

of the qualifying levels to enable data on the tape bus and initiate P Tape Break request.

CHECK WORD - The CHECK WORD flip-flop is set when the tape processor has completed the transfer
of a block of data. When a Read instmetion has been performed, the CHECK WORD flip-flop is set, indicating that the checksum has been accessed and is available in the TAC.

For a Write instruction, it comple-

ments the phase of the checksum and allows it to be written an tape in complement form.

TURN AROUND — When the TURN ARND flip-flop set, the MOTION flip-flop is cleared when the next
BM encountered on the tape at the completion of a tape instruction. If the I-bit not set, the TURN
AROUND state is entered, thus allowing the tape transport to stop. The TURN ARND flip-flop set with
the signal, (CM * CHK WRD * TPl), and is cleared with (TPl * BM * TURN ARND (D).
is

The WRITE SYNC flip-flop synchronizes the WRITE flip-flop with the tape timing and mark tracks, thus
protecting the control information (timing and mark tracks, block numbers, etc,) on tape, and assures that

6-26

data is written in the correct data areas of each block.
pulse after the tape processor enters the BLOCK state.

The WRITE SYNC flip-flop is set with the first TPl
The WRITE flip-flop is set with the next TPS pulse.

Both the WRITE SYNC and the WRITE flip-flops are cleared with LCS CLR WRITE, which is generated
with CM and TSl (1).

The WRITE CYCLE flip-flop — (lower left), is one of the qualifying levels for the WRITE flip-flop. During

WRC and WCG instructions, holds the WRITE flip-flop cleared. It also controls
WCG instruction. The WRITE CYCLE flip-flop set at the
start of every tape instruction. In the event of a bad checksum for a WRC WCG instruction, it is set in order
that the affected block can be rewritten. The flip-flop is cleared with CM * CHECK WORD * TPl,
the check portions of the

the COUNT GPCNT pulse (TC12-0-LGP) for a

The LCS TAPE OK signal is true when the requested tape transport has the correct manual switch settings:
Unit Selector on line (0 through 7)

REMOTE/OFF/LOCAL switch to REMOTE
WRITE/LOCK, ENABLED for Write instructions
6.8.2 Tape Extended Operations (TC12-0-LCX)

The Tape Instruction Field flip-flops 3 and 4 and the Tape Data Field flip-flops 3 and 4 determine which IK field
of a particular 4K memory bank is accessed for data transfers to tape. They are loaded with IF 3 and 4, and

DF 3 and 4 at the beginning of a tape instruction (MTP SETUP 2).
The five flip-flops shown on the right select a particular Extended Tape operation. The MARK, TAPE INT EN,

EX ADD FORMAT, NO PAUSE and HOLD MOTION flip-flops are selected with the AXO instruction and AC
bits 4 through 9 respectively (AC06 (1) selects Maintenance Mode).

MARK — The MARK flip-flop

used during all tape-formatting operations.

TAPE INT EN — Allows the tape control to interrupt the CP at the completion of a tape instruction.

EX ADD FORMAT — Is used for nonstandard format tapes. When this format is selected, the eleven least
significant bits (bits
through 1 1) of the second word of a tape instruction designate the tape block number.
The first Memory Address for the data transfer is loaded from the AC into the TMA Setup register prior to
the tape instruction. This can be any random 12-bit address. Group instructions cannot be performed when
1

EX ADD FORMAT is selected.

NO PAUSE — When the NO PAUSE flip-flop

is set,

the CP does not pause for the duration of the data trans-

The CP continues with the program, and the tape control will request a tape break when it is ready to
transfer a word of data.
fer.

HOLD MOTION — The HOLD MOTION flip-flop allows the operator to keep a tape transport in motion
even through that particular unit is not logically selected by the tape control.

6.8.3

Tape Extended Fields (TC12-0-LCXF)

Tape Fields 00 through 01 (LCXF TFO through TF02) extend the capability of the TMA register to allow the
addressing of up to 32K of core memory.

When the Extended Address format is selected, the fields are loaded with ACq _2 by the AXO instruction. When
the Extended Address format is not selected, the fields are loaded with TIF 0 through 02 or TDF 0 through 02

by the BM * SEARCH * TPl pulse. Tape Instruction Field 0 through 02 (TIF 0 through 02) and Tape Data Field
0 through 02 (TDF 0 through 02) are loaded with IF 0 through 02 and DF 0 through 02 respectively, at the initiation of a tape instruction. This allows full buffering of the tape processor; the CP does not have to provide the
field assignment after the tape instruction

is initiated.

6-27

6.8.4

Tape Group Counter (TC12-0-LGP)

The three group count flip-flops (GPCNT 0 through 2) and associated gating logic comprise the counter for the

RDG and WCG instructions. The LPG COUNT GPCNT pulse increments by one (+1) at the end of each block
The three group flip-flops (GP 0 through 2) are loaded with MB 0 through 2 from the second word of

transfer.

the tape instruction and indicate the number of additional blocks to be transferred after the first block.

The

GP CNT flip-flops are compared with the GP flip-flops after each block transfer. When the group (GP) and the
group count (GPCNT) flip-flops are equal, the GP EQ GPC flip-flop is set, indicating that the requested number
of blocks have been transferred.

6.8.5

Tape Instructions (TCI 2-0-LIN)

Two major operations are performed by the logic shown on the LIN drawing. The contents of the Tape Accumulator (TAC) are examined for the correct checksum (7777g), and tape instruction decoding.

Decoding of the

tape operation to be performed is accomplished by the three tape instruction register flip-flops TINR 0 through 2

shown on the right side of the drawing. Decoded are bits 9 through 1 1 of the first word of the two-word tape
instruction.

The contents of the CP Instruction Register (INR 9 through

1) are loaded into the tape instruction

right of the drawing.

The I flip-flop, when set, allows the selected tape transport to be left in motion after com-

pletion of the current instruction.

When the I flip-flop is a zero, the tape control will enter the TURN AROUND

state, thus stopping the transport.

The binary-to-octal decoder is the same as those used by the CP for instruction decoding (Ml 61). Outputs 0
through 3, true when bit 9 is a zero, are the Read and MTB instructions. Outputs 4 through 7, true when bit 9
is

a one, are the Write and Check instructions.

The AND gate network shown on the left of the drawing decodes the contents of the TAC register. The gate is
qualified when the datasum for the Data Transfer instruction is correct, and also when the desired tape block has

been located during a SEARCH.

6.8.6 Interprocessor Signals (TCI 2-0-LIP)

The primary tape control interprocessor signals are generated by the logic shown on this drawing. The tape
processor is fully buffered and independent of the CP; therefore, certain signals must be provided to the CP from
the tape control so that both processors may operate asynchronously or interleaved, depending upon the

program.

TAPE BRK REQ — When the TAPE BRK REQ flip-flop is set, the tape processor is indicating to the CP that it is
ready to effect another transfer of a word of data. The CP then enters the TAPE BREAK state and the memory
address register (MA) is loaded with the tape memory address (TMA) at TPl
is

If the signal LIP

TAPE OUT (Read)

true, the contents of the tape buffer (TB) are enabled on the tape bus, loaded into the MB, and subsequently

written into memory.

When the signal LIP TAPE OUT is not true (Write), the contents of memory designated

by the MA are loaded into the MB, then loaded into the tape buffer (TB), and subsequently written on tape.
This operation is similar to all one-cycle Data Break I/O devices.

CHK SUM LOAD AC — The CHK SUM LOAD AC signal is supplied to the CP register load control logic, where
is used to generate an AC load signal to load the checksum into the AC.
it

TAPE PAUSE — When the TAPE PAUSE signal is true, the CP will pause until the complete data transfer has
been accomplished. When the TAPE PAUSE signal is not true, the CP continues to execute the main program
after initiating the tape instruction.

6-28

TAPE INTERRUPT - This signal is connected to the common interrupt bus of the CP. At the completion of a
tape instruction the TAPE DONE flip-flop is set and, if the TAPE INTERRUPT is enabled, the CP
is interrupted,
signaling the CP that the tape instruction is complete.

IN PROGRESS and PROGRESS - These two flip-flops indicate the status of the tape processor. When they are
set,

there is some tape operation in progress.

The PROGRESS flip-flop is set with MTP SETUP (TS5 of the first

word of the tape instruction) and generates the TAPE PAUSE signal if NO PAUSE operation is selected (see
Tape Extended Operation TC12-0-LCX). The IN PROGRESS flip-flop is set with MTP SETUP 2 (TS5 of the
second word of the tape instruction) and is instrumental in controlling the tape processor states. Both flip-flops
are cleared at the completion of all tape instructions except the MTB instruction. In this case, the IN
PROGRESS
flip-flop is cleared when the first
if the

BM is encountered on tape. The PROGRESS flip-flop is cleared at this time only

ACIP delay (TC 2-0-LTD) has timed out. This prevents the issuance of another tape instruction while the
1

tape transport is turning around, thus preventing undesirable tape snapping.

TAPE WORD - This flip-flop is used in conjunction with the MARK 12 tape formatting program. It is applied
to the skip logic and is checked with the SXL 17 instruction.
6.8.7

Tape Unit and Motion (TCI 2-0-LMU)

The logic shown in this drawing performs tape transport selection, direction and motion control, and enabling
levels.

Tape unit selection is controlled by the unit flip-flops U 0 through 2 and the preunit flip-flops PREU 0

through 2 which select up to eight TU55 or four dual tape transports (units). The tape unit flip-flops are de-

coded by the transport control logic (shown on TC12-0-LTC). PRE U2 and U2 select units 0 and 1. The PRE
U2 flip-flop is loaded with bit 08 of the CP instruction register, with the LIP MTP SETUP pulse.

PRE UO and PRE U1 are loaded with AC bits 10 and

2 are jam-transferred into UO through 2 with the LTD

respectively, by the

AXO instruction. PRE UO through

MTN DLY 3 signal. The preunit flip-flops are compared

with the unit flip-flops to determine if a different tape unit is being selected.

When a change in tape units is
made, LMU NEW UNIT is true (high) and the motion flip-flop is cleared; it could have been set from the previous

tape instruction. The UNIT EN flip-flop enables the unit selection signals to the tape transport, thereby eliminating transients on the selection when changing tape units.

The DIRECTION (an OR gate) flip-flop controls the direction of tape travel on the selected tape unit. When
DIRECTION is cleared (0), the tape moves in the Reverse direction (when facing the transport; left-to-right).

When the flip-flop is .set (1), the direction is Forward (right-to-left).
At the beginning of each tape instruction, reverse direction is selected if the motion flip-flop is cleared.
6.8.8 Tape Register Enable Control (TCI 2-0-LRE)

The enable signals generated by the logic shown on this drawing are used to condition the tape processor major
registers, the CP accumulator (AC) and memory buffer (MB).

The EN AC level is generated by a TMA (MSC

3) instruction; AC ->

TMA Setup. It

also generated with a tape

maintenance (lOT 61 54) instruction. The EN MB, which is generated by the tape processor during the second

word of a tape instruction, enables the block number to be loaded from the MB into the TBN register.

It is also

enabled during the TAPE BREAK cycle of all Write instructions. The MB is loaded into the tape buffer (TB).

The logic shown on the lower left side of the drawing generates the levels necessary to perform the correct addressing of memory. These signals are enabled at TTS 4 • BM • SEARCH.

6-29

When TINR (Tape Instruction Register)

bit
is

1 1

to determine a group instruction, specific address gates are enabled.

If bit 11

a 0, the instruction

a non-group instruction and a different addressing sequence is utilized.

The logic shown on the right side of the drawing generates the tape processor major register enable signals. To
accomplish a data transfer from a particular register, this register is enabled onto the tape bus, and the appropriate
load pulses are generated.

The EN GPCNT signal for the Group Count register (for a multiple block transfer) is

also generated the same time as the

6.8.9

EN TBN (TBN +

TBN during multiple block transfer).

Tape Register Load Control (TC12-0-LRL)

The Load pulses shown on this drawing strobe the data from the tape bus into the specified registers. When the
register is clocked, the data enabled on the tape bus is jam-transferred into that particular register.

The SEIIFT RWB pulse shifts the RWB register left in three four-bit segments. Data from the three data channels
(on tape) are read into bits 3, 7, and 1 1 of the RWB register when reading, and, when writing, data is shifted out

on RWB bits 0, 4, and 8.

6.8.10 Transport Control (TC12-0-LTC)

The control logic shown on this drawing provides the interface between the tape processor and the TU55/56
Tape Transports. The right side shows the unit select gating network and the logic converters. Both the TU55
and TU56* require negative logic levels of -3 and OV.

Shown on the left side of the drawing are the transport control logic level converters and the transport unit selector decoder.

The B UNIT SEL level is true when only one tape transport is selected. The WRITE EN LEVEL is true when the

WRITE switch is (operator-selected) enabled on the selected tape unit. Both of these signals generate the TAPE

OK level shown on the TCI 2-0-LCS drawing.
6.8.1 1

Tape Delays (TCI 2-0-LTD)

The tape delays are divided into two basic groups: the motion delays and the tape transport fail delays.
The motion delays MTN DLY

through 4 provide the signals that select the tape unit and control the selected

tape unit motion (forward or reverse).

MTN DLY

used to clear the MOTION Bip-Bop (TCI 2-0-LMU) if a

MTN DLY 2 deselects all tape units by
LMU UNIT EN Bip-Bop (TCI 2-0-LMU). MTN DLY 3 zeros the DIRECTION Bip-Bop (TCI 2-0-LMU)
(reverse) and selects the new tape unit. MTN DLY 4 sets the UNIT EN and MOTION Bip-Bops
(TCI 2-0-LMU) if
the TAPE OK signal is true (TCI 2-0-LCS).
different tape unit has been selected since the previous tape instruction.
clearing the

Six status signals are generated by the delay generators shown in the upper half of the LTD drawing:
the TTOK
(Tape Timing OK), XTLK (Crosstalk), ACIP (Acceleration In Progress), TAPE EAIL DELAY, NO TAPE and

TAPE EAIL.

TTOK — The TTOK (Tape Timing OK) delay assures that the tape is moving fast enough over the tape head
(within 50 percent of maximum) so that the information read from tape is meaningful.

When the outputs are
not true, tape timing pulses are inhibited and the tape processor enters the IDLE state. The M307
IntegratingOne-Shot is triggered by the signal from the timing track (LTT READ 0) at an approximately 30
a delay period of 48 ms.

ms rate, and has

The delay is also triggered by LTT SIMULATE TPO, which results from an lOT 6151

Maintenance instruction.
^optional positive

6-30

XTLK DELAY - The cross-talk delay inhibits erroneous tape timing pulses (TPO and TP3) due to noise on the
signal from the timing track.

When the outputs are true, tape timing pulses are inhibited. The M307 Integrating-

One-Shot is triggered by TPO and TP3 at approximately a

5 ms rate, and has a delay period of 9 ms

ACIP ™ The Acceleration In Progress signal is used to inhibit tape timing pulses while the tape transport is in the
process of accelerating up to speed and decelerating for a tape turnaround, thereby allowing the

operational speed before allowing the timing generator to decode the timing track.

tape to reach

The M307 Integrating-One-

Shot is triggered by a change in direction or when the MOTION flip-flop goes to the

state, and has a delay pe-

riod of 1 80 MS.

TAPE FAIL DELAY - This 300 ms delay generates a NO TAPE signal, which will then qualify the TAPE FAIL
signal to control the

MOTION flip-flop (TCI 2-0-LMU).

TAPE FAIL — The TAPE FAIL DELAY generates a TAPE FAIL pulse every 300 ms, when tape timing pulses
fail

to occur after the initiation of a tape instruction.

The M307 Integrating-One-Shot is triggered by MTP SETUP

and by the NO TAPE pulse, which is generated when the delay times out.

If the absence of the TPO pulse was
due to the TAPE OK signal, the MOTION flip-flop remains cleared until this signal becomes

true.

6.8.12 Tape Maintenance Signals (TC12-0-LTM)

The 4-bit maintenance instruction register shown on this drawing is decoded to generate the enable
the various tape maintenance operations performed with lOT 6154.

signals for

lOTs 6151 and 6152 are gated with the AC

bits to generate the pulses to load the various tape registers.

These lOTs are used for maintenance purposes only.

6.8.13 Tape Reader-Writers (TCI 2-0-LTR)

Shown on the drawing are the Read/Write circuits associated with the five tape channels. These circuits
of G882 Modules, which are high gain differential amplifiers connected directly to

consist

the Read/Write heads through

W032 Connector Cable. The reader-half of the module receives outputs from the Read/Write head to produce
complementary outputs at terminals V2 and U2. At terminals J2 and K2, the writer-half of the G882
Module
produces complementary outputs that go into the Read/Write head for writing on tape.

G882 negative level (OV, -3V) to positive (OV -i-3V) levels. The W5
to negative logic (OV -3V) levels.

The W603 converts the

2 converts the M222 positive logic (OV, -i-3V)

There are five identical tape channel tracks as follows: one timing, one mark

and three data tracks.
Basic timing signals for tape operation are provided by the timing track through
the tape Read/Write head shown
on the left of the drawing. The timing signal read from this channel is essentially a
sinusoid with a period of

approximately 30 ms; each time the sinusoid crosses the zero reference (

5 ms), the reader output changes.

output from the reader is connected to a +3V and OV line by W603 and goes through

The

buffers to generate LTR T

READ, which in turn generates TPO and TP3, the two basic timing pulses for tape processing.
Unique control marks, defining specific areas of tape, are recorded on the mark track.

mark track reader and sent to the window shift register (see Tape Mark Window), for

This data is read by the
decoding. During the

marking of tape (using the MARK 12 program, for instance), data is entered into the mark
the window register flip-flop 0 at TPO.

channel writer from

The mark writer flip-flop is then complemented at TP3. Therefore, the

magnetic flux on the tape is changed from 0 to

or from
to 0 in synchronization with TT3 (corresponding to
the time that the three data writers are complemented). This process insures
that tlie tape head signal, when read
1

back, will be maximum at TP3. which means that the Read amplifier will be fully
at TP3 when

data is read.
6-31

saturated with either a 0 or a

Three data tracks are used for data storage. Data is recorded on tape serially, in groups of four 3-bit lines which
correspond to the one 1 2-bit data word. The Read/Write buffer disassembles data to be written on tape or receives (assembles) data from the three data tracks during reading.

Writing of data from the RWB is accomplished
by data writer flip-flops D1-D3 WRITE, respectively, by the TPO pulse. Approximately 15 jus later, the writer
flip-flops are complemented by time pulse TP3, which writes the data on tape.

reader on readback when data is strobed in at TP3.

This flux change saturates the

TP3 initiates the RWB shift-left pulse, which loads the reader

outputs into bits 3, 7, and 1 1 of the RWB register and shifts the other RWB bits left one place.

6.8.14 LINCtape Register Bus (TC12-0-LTRA-F)

The six 12-bit registers shown on this drawing store information during all LINCtape operations. The 12-bit
inter-register transfers are gated into the major register network by enabling gates (TCI 2-0-LRE).

abling gates are conditioned by the tape processor or maintenance enable levels such as the EN

All the en-

TAC, EN TB, etc.

These enable levels allow the data from a register to enter the major register gating network in a parallel transfer.

When the contents of a register(s) are enabled, the data enter the major register gating network through the adders
and onto the tape bus lines. When any inter-register transfer within the tape processor is performed (excepting
the serial parallel shifting transfers of the RWB register), all 12-bit inter-register data enter the tape bus lines 00
through 1 1 through the major register gating and adder networks. These lines are the data input (terminal D) of
all the

The data on these bus lines are loaded into the specified register by a clocking action;

TAC is the destination, the TAC LOAD (TCI 2-0-LRL) pulse is generated. There are five major register
Load pulses. They are: LOAD TMA SETUP, LOAD TBN, LOAD TB, LOAD TMA and LOAD TAC. Only the
RWB register does not require the use of the adder. The adder has a carry input which allows a 2-bit addition

i.e., if the

with ripple carry.
Special note should be taken of the Read/Write Buffer register insofar as it functions as a shift register.

Tape Read operation, the data is loaded into the RWB bits 3, 7, and
pulse.

During a

from the tape readers by the SHIFT RWB

After the four separate Read and Shift Left operations, the RWB register contains the complete 1 2-bit

word, Then an EN RWB and a Load TB pulse loads the word into the tape buffer (TB) for transfer to the CP on
the tape bus.

During a Tape Write operation, the TB is loaded (in parallel) into the RWB register.
to tape, it is loaded from

When the word is transferred

RWB bit locations 0, 4, and 8 to the tape heads (D3, D2, and D1 respectively).

6.8.15 Tape States (TCI 2-0-LTS)

Shown on the Tape States drawing are the five tape time states generator flip-flops (TTSOO through 04), the line
counter flip-flops (LCOO through 02), a mark clock, and time counters TCOO and TCOl.

The five tape time states (TTSOO through 04) are controlled by corresponding tape time pulses TPO through TP4
(TCI 2-0-LTT). The time state flip-flops are used to synchronize the loading of the various tape registers. Data
are enabled on the tape bus with a time state signal, and the selected register is loaded with
the time pulse. As in
the CP, time states enable and time pulses load the registers.

A time pulse terminates a time state and sets the

next state; i.e., TPO terminates TTSO and sets TTS 1

The line counter comprises LCOO through 01 and LC 02 into a 3-bit up counter that synchronizes the 1 2-bit
,

computer word with the tape word (4 three-bit lines).

LCOO and LCOl provide the four count, and LC02 pro-

When a Write operation is executed, the TAPE BRK REQ is set (TCI 2-0-LIP) at a count
of one, indicating that the tape processor is ready to receive another word from the computer.
LC02 controls

vides the clock pulse.

the PHASE level that writes data on tape (TC 1 2-0-LTRA-F).

6-32

The TIMING OK signal verifies that the selected tape transport is operating correctly to accomplish data

transfers.

All the tape timing pulses are inhibited when this signal is not true.

The TIME WRITE and MARK CLOCK signal are used to generate a timing track when formatting a virgin tape.
The MARK CLOCK clocks TCOl every 7.5 ps. The output of TCOl is a 15 jus square wave which clocks TCOO.
6.8.16 Tape Time Pulses (TC12-0-LTT)

The timing track signal from the tape is used to establish all tape processor synchronization. TPO and TPS generate the pulses to establish the tape time states (TCI 2-0-LTS).

The logic circuitry shown on this drawing gates the timing signals from the Read/Write tape heads (TC12-0-LTR),
shapes and amplifies them for generating TPO and TPS. These pulses occur at an interval of approximately
15 /is

TPO generates TPl one ps later, and TPl generates TP2 one jUs later. TPS generates TP4 one /is later. These
pulses generate the Load pulses required to transfer data to the various registers.

TPO

TSO

TP2

TPl

TP3

TP4

TPO

iMS

t>is

14 4S-

1ms

-«14ms-

TS1

TS2

TS3

TS4

TSO

The CLOSE WINDOW pulse initializes the tape processor.

It is generated by TAPE PRESET (TCI 2-0-LIP),
(TCI 2-0-LIP), MTP SETUP at the beginning of each tape instruction and when the tape timing does not meet

specifications.

6.8.17 Tape Mark Window (TCI 2-0-LVVN)

Shown in the drawing is the mark track logic which consists of a four-bit window register, a window shade flipflop, and all the necessary gating for controlling and decoding the window register.

When a virgin tape is to be formatted, AC bits 8, 9, 10, and
left,

1
are loaded into the window register and shifted
out to the mark track reader/ writer and written on the mark channel of the tape. During all other tape
1

operations, this information is read back by serially shifting the mark track data with the
•

into the window register (WIND 03).

LOAD WINDOW pulse,

The four window register bits and the SHADE are decoded to generate the

various signals necessary to identify the information read/ written in the three data channels (Dl,

These signals enable the appropriate logic levels which control the data transfers.

6-33

D2, and D3).

CHAPTER 7
PREWIRED OPTIONS

7.1

INTRODUCTION

Thirteen prewired options are available for the PDP-12 Computer System; the mainframe of the system is pre-

wired to accept these options. Table 7-1 lists the options in alphabetical order and their applicability to the vari-

ous system configurations that are defined in Chapter

of the PDP-12 System Reference Manual.

Table 7-1
Prewired Options

Type

Name

AG12

Preamplifier

AM 12

Expanded Multiplexer

DP12-A
DP12-B

Teletype Dataphone

KE12
KP12
7. KT12
8. KW12-A
9. KW12-B
10. KW12-C
5.

7.2

Teletype Dataphone (EIA Level)

Extended Arithmetic Element

Power Failure Restart

PDP-12A
PDP-I2A
PDP-12 A, B,C
PDP-12A, B,C
PDP-12A, B,C
PDP-12 A, B,C

Time-Sharing Options

PDP-12A, B,C

Real-Time Clock
Simple Clock

PDP-12A, B,C
PDP-12A, B,C
PDP-12 A, B,C

Simple Clock

11.

TC12-F

8 Tape Control

PDP-12A, B

12.

XY12

Incremental Plotter

PDP-12 A, B,C

AG 12 AND AM 12 OPTIONS

The analog-to-digital converter (AD 12) includes
drives a SAMPLE
is

System Application

6 channels of input through a FET-switched multiplexer that

& HOLD circuit. The SAMPLE & HOLD output is converted by the

0-bit A/D converter that

controlled by the LINC-Mode SAM instruction. Eight of these sixteen channel (Channels 0 through 7) inputs

are wired directly to potentiometers that are used by numerous software programs as parameter inputs.

maining eight channels (Channels 10 through

The re-

7) are wired to differential preamplifiers that provide an input

range of ± IV and an input impedance of 70 k^2 300 pF in parallel. The common frequency of the preamplifiers
passes signals up to 60 kHz at 308 down.
1

The preamplifiers provide 10,000 percent overload protection with

MS recovery time. As explained in Chapter 5 on the A/D Control, two modes of sampling operation are used, in

which the user is given the option of pausing until A/D conversion is complete, or continuing with the programming.

The AD

2 can be expanded by another 1 6 channels for a total of 32 channels by ordering the

7-1

AM 2 option.
1

7.2.1

AG 12 Preamplifier
If high input impedance for sensitive signals is required, the

preamplifiers.

AG 12 option provides an additional 16 differential

The preamplifiers consist of two A2 14 Modules that are plugged into locations E29 and F29. An

extra Analog Extension Panel Assembly (DEC Part No. 7006046) with two blue ribbon connectors (Amphenol

26-4401-24P) are also provided. The Amphenol connector is mated with a connector (DEC Part No. 12-03578)
to provide user interface.

Two 6783 Modules are used to route signals from locations F30 and F31 to the Am-

phenol connectors. The Analog Extension Panel Assembly is shown on Volume III drawing D-AD-7006040-0-0.

The specifications for AG 12 are as follows:

7.2.2

Input Voltage Range:

±1V

Input Resistance:

70 k^2, ±2%, 300 pF in parallel

Common Mode Rejection:

±3.5V from system fault line ground

Input Protection:

±67V from fault line indefinitely

Overvoltage Recovery Time: 8 MS

Frequency Response:

0- to 30-kHz flat

60 kHz — 3 dB down

AM 12 Expanded Multiplexer
The AM 12 option consists of two additional A

3 1 Multiplex Modules that are plugged into locations D31 and

D30 respectively. User interface is provided through two W02I Modules, which are plugged into location F30

(CHA 20 through 27) and F31 (CHA 30 through 37) on the computer wire panel.
The specifications for the AMI 2 are as follows:

±1V

Input Voltage Range:

Input Resistance:

10 Mfi,

300 pF to selected mutiplex

7.2.3

Input Protection:

20V RMS for 5s
±8V indefinitely

Common Mode Rejection:

None

Logic Description

As shown in Figure 7-1 and the TADC print, IR bits 07 through 1
bits 08 and 09 are decoded to provide

are used to select a particular multiplexer.

N EQ 00, N EQ 10, N EQ 20, and N EQ 30. These signals are used to par-

tially enable the select logic for one group of 8 (Channels 0 through

10 through 17, 20 through 27, or 30

through 37) FET switches. IR bits 09, 1 0, and 1 1 are decoded into 00 through 07 to provide the signal necessary
to enable a particular FET switch.

The control instruction for this logic is SAM, which has been described in

Chapter 1.

7.3

DP12-A TELETYPE AND DP12-B ASYNCHRONOUS MODEM

The DP 2-A Teletype and DP 2-B are prewired options that permit interfacing a second Teletype or Modem, re1

spectively, to the PDP-1 2 Computer. Either the PDP12-A or the PDP12-B may be installed at one time, but both

cannot be installed at the same time.

7-2

Figure 7-1

PI 2-A Teletype Interface is designed to

2-0Z3Z

Multiplexer Selection

interface

0-baud ( 1 0 characters per second) asynchronous

vices utilizing US ASCII bit code. Teletype
input (DTTI) to the printer

de-

or paper-tape punch, as well as Teletype

output (DTTO) from the keyboard or paper-tape
reader, is transferred by the DPI 2-A under
program control.
The 33 ASR Console Teletype is recommended for
this application.

The DPI 2-B Asynchronous Modem Interface is a
user-specified rate in the

crystal-controlled interface capable of accepting
data at any
10 to 100,000 baud range. The unit is designed
for US ASCII bit code.

u -duplex, and signals are EIA-compatible.

No- 103, Datapoint 3300 Display, or any other

meeting the requirements mentioned above.
7.3.1

Operation is

Suitable devices utilizing the DPI 2-B as an

interface are Bell Data-

EIA-compatible (see EIA-standard RS232-B) device

The DP 2-B can also be used for interprocessor
1

communications.

Component Description

The module requirements for DPI 2-A and DPI 2-B
The M850 Module is connected at one end of the
other end is terminated in a 6 in. DB-25P

25-ft cable (BCOl-A-25), that is supplied

with the DPI 2-B

25-pm connector, wired in accordance with EIA Standard

The W076 Module is mounted on the cable to
Teletype Connector or M850 EIA Lever

options are shown in Table 7-2.

RS232-B

a DEC-supplied Teletype. Either a
Teletype-compatible W076

Converter can be utilized as a connector on the

7-3

DPI 2-A and DPI 2-B

The

Table 7-2

Module Requirement for DP12-A and DP12-B

DP12
A B

Module Slot

Description

Module

M09, N09

M10,N10^'

G700YA
M216

Dataphone Disable

N03'-'

Six Flip-Flops

N12

M405
W076
G718
M850

Crystal Clock

Nil

Teletype Connector

N03

Timing Jumper

Nil

EIA Level Converter

N03 ^

M706
M707

Teletype Receiver
Teletype Transmitter

X
X
see below

X
see below

To prevent false computer interrupts when neither module is in place, a G700YA Dataphone Disable Module is
DATA L, disabling the
supplied. This module, when inserted in connector slot NOS, grounds the signal DTTI
Interrupt from the DTTI

KEYBOARD FLAG.

When ordering a DP12-B option, the intended baud rate must be specified. The crystal clock (M405) is selected
to be 128 times the baud rate at baud rates less than 10,000 baud.

For baud rates between 10,000 and 100,000

required to remove
baud, the oscillator frequency is 1 6 times the baud rate. In this higher rate range, it is also
the wire connecting N1 2L2 to N 1 1D2 on the mainframe and add a jumper wire from N 1 2L2

to N1 2M1

Examples;
a.

For a computer display terminal operating at 2400 baud;
Crystal clock frequency = 2400 baud x 128 = 307.2 kc.

For a modem operating at 10,000 baud;
Crystal clock frequency = 10,000 x 16 = 16 kc.

7.3.2

Programming

Programming of the DP 12 is identical to that of the system Teletype, but uses I/O codes 40 and 41.
mnemonics for the DPI 2 System are not recognized by the program assembler (LAP6-DIAL VI through V5),

Instruction

and must be defined by the programmer (see Table 7-3). The instructions use IOC lOPl for performing skips,

IOC IOP2 for clearing flags and the AC, and IOC IOP4 to perform data transfers. The LINC instruction ESF
(AC bit 6 = 1) can be used to disable computer Interrupts when the Keyboard Flag is raised.
Table 7-3

DP 12 Instruction Mnemonics
Instruction

Octal Code

Mnemonic

Description

Skip on Keyboard Flag

6401

DKSF

The contents of the PC are incremented by
1

skipping the next instruction when the

Keyboard Flag is high.
Clear Keyboard Flag and

6402

DKCC

Clears the

AC and Keyboard Flag, assem-

bles a new character in the

DTTI buffer,

and resets the Keyboard Flag high when
ready to transfer a new word.

(continued on next page)

7-4

Table 7-3 (Cont)

DP 12 Instruction Mnemonics
Instruction

Octal Code

Mnemonic

6404

DKRS

Read Keyboard Buffer

Description

The contents of DTTI buffer are ORed with

Static

bits 4 through

of the AC. Neither the

AC nor the Keyboard Flag is cleared.
Read Keyboard Buffer
Dynamic

DKRB

6406

Microinstruction of DKCC and DKRS. AC
and Keyboard Flag cleared, contents of

DTTI transfer into bits 4 through
AC.

of the

A new character is loaded into the

DTTI register, resetting Keyboard Flag high.
Skip on Teleprinter Flag

6411

DTSF

The contents of the PC are incremented by
I

(skipping the next instruction) when the

Teleprinter Flag is high.

Clear Teleprinter Flag

6412

DTCF

Load Teleprinter and

6414

DTPC

Set the Teleprinter Flag low.

The contents of bits 4 through

are loaded into the

of the AC
DTTO buffer, then
1 1

shifted out serially to transmit a character.

The Teleprinter Flag is high.

Load Teleprinter

6416

DTLS

Microinstruction of DTCF and DTPC.

Sequence

The

Teleprinter Flag is cleared and the contents

of bits 4 through
ferred to the

of the AC are transDTTO buffer. When the char1

acter has been shifted out, the Teleprinter
Flag is reset to a high. A new character
can
be loaded into the DTTO buffer now.

7.3.3

Cable Connections - DP12-B

The 25-pin connector mounted on one end of
being greater than +3V, and a logical 0

7.3.4

(A logical 1 is defined as
The connector wiring is as shown in Table 7-t.

Logic Description

Logic used for DPI 2 is similar to that used on
7.4

the BCOl-A Cable meets EIA standards.

less than -3V.)

the PDP-1 2 Teletype. Refer to Chapter
4 for details.

KE12 EXTENDED ARITHMETIC ELEMENT

The Extended Arithmetic Element (EAE) option

for the PDP- 2 enables the CP to
perform arithmetic
1

These higher speeds are made possible by

mg CP f
logic in such a way that they operate
asynchronously.

control logic, a

2-bit Multiplier Quotient Register

are discussed in Section 7.4.4.

7.4.1

opera-

incorporating the EAE components with the

ex-

The EAE components consist of EAE timing and

(MQ), and a 5-bit Step Counter (SC). The EAE
instructions

Timing and Control Logic
^

r a block
Ki‘°u diagram of
tied
the KE12

™

accumulator (AC), MQ link (L), and memory
“Parations of high speed on positive binary

EAE option.
7-5

buffer

numbers. Figure 7-2 is a simpli-

Table 7-4

DP12-B Cable Connector Wiring
Signal Name

Pin Number
1

Protective Ground*

Transmitted Signal**

Received Data**

Signal Ground*

Data Terminal Readyf

20
*

Pins 1 and 7 are tied together

* With respect to the computer
I

Held at +5V

Cable Connection — Slot NOS

+5V

B2
C2

-15V
Ground

D2
E2
F2

DTTI DATA IN L

DTTO MAGNET DRIVER H

K2
L2

DTTI READER RUN (0) H

M2
N2
P2

R2
S2

instruction
Most of the transfer of information between the KE 2 and the PDP-1 2 CP occurs during the EAE
1

FETCH cycle. All arithmetic operations, with the exception of NMI (normalize), require a FETCH cycle for
(MUY) or
referencing the next memory location. During the FETCH cycle, one of the operands for a multiply
a divide (DVI) is obtained, or the number of shifts to be performed during the

long-shift feature is obtained.

The T5 RECYCLE is set by the EAET ON to provide EAET5 RECYCLE when programmed for arithmetic opthe CP from aderations, which require at least 7.8 /as for completion. Setting the CPT T5 RECYCLE prevents
the
vancing in its cycle until the arithmetic operation is completed. At the finish of the arithmetic operation,

EAE logic clears the EAET ON flip-flop to 0, which causes the CPT RECYCLE SYNC flip-flop to clear. Then,
sets TSl
50 ns after the CPT RECYCLE SYNC flip-flop clears, CPT T5 RECYCLE clears and the next TPS pulse
and are
CP
of
the
N-register
the
in
decoded
are
for
EAE
allowing the CP to continue with the program. MB bits
routed to the EAE logic.

7.4.2

Multiplier Quotient Register (MQ)

The MQ is a

2-bit register that acts as an extension of the

AC during EAE operations. The MQ contains the

multiplier at the beginning of a multiplication, and the least significant half of the product at the

The MQ

conclusion.

end.
contains the least significant half of the dividend at the start of a division and the quotient at the

The MQ contains tlic least significant part of a number during a shift or a normalize operation.

7-6

CENTRAL PROCESSOR

Figure 7-2

7.4.3

Simplified Block Diagram, KE12 EAE

Step Counter Register (SC)

The EAE SC is a 5-bit register loaded with the complement of the
LSR, SCL, and SHE instruction, and is set to contain all Os for
record the number of shifts performed, and stops the

7.4.4

contents of MB bits 7 through 1 1 for the ASR,

DVI, MUY, and NMI instructions.

shifting process after the correct number of

It is used

shifts.

EAE Instructions

The instructions for the EAE are a class of GROUP 3
through 03 (hence, code 7nnn) and bit 1

Microinstructions containing binary Is in MB bits 00

indicating the EAE group.

The setting of these bits distinguishes the

EAE instruction from all other instructions; all EAE except NMI are two-word

instructions.

These instructions

can be subdivided further into two basic groups: the load
group and the EAE operation group (instructions

when EAE timing is started and the CP is in the T5 RECYCLE state).

used

The EAE microinstructions are augmented

microprogrammable instructions. They can, therefore, be combined
to perform non-connieting

logical opera-

tions.

7.4.5

Load Group

Clear the Accumulator (CLA) - The CLA instruction
this instruction can be microprogrammed
2, such as

(7601) clears the AC during logical sequence 1
with other EAE instructions that load the AC during

;

therefore

logical sequence’

SCA or MQA.

Clear the Accumulator and Multiplier Quotient (CAM) cal sequence

as in CLA; during logical sequence 2 the

0 = > AC, 0 = >

The CAM instruction (762

7-7

is cleared

)

clears the

by enabling MB bit 07.

AC during logi-

Multiplier Quotient Load into Accumulator (MQA) — The

MQ into the AC. This command

is given

MQA instruction (7501) loads the contents ot the

to load the 12 least significant bits of the product into the

multiplication, or to load the quotient into the AC after a division.

AC after a

The AC should be cleared prior to issuing

The CLA instruction can be combined with the MQA to clear the AC and then load the MQ into
the MQ are inclusively ORed with
the AC. If the AC is not cleared prior to the MQA command, the contents of

this command.

the contents of the AC.

MQ V AC = > AC
Load Multiplier Quotient (MQL) - The MQL instruction (7421) clears the MQ at logical sequence 1 and

loads

AC to MQ ENABLE is develthe contents of the AC into the MQ
causes the AC
oped by a four-input NAND gate, as shown on Drawing D-BS-EP12-0-RCS. AC to MQ ENABLE
at logical sequence 2; then the AC is cleared.

bits to be loaded into the data inputs of the
in the

MQ flip-flops. RCL MQ LOAD

is developed

in the same manner as

CAM instruction during sequence 2.
0 = > MQ, AC = > MQ, 0 = > AC

of the SC into the
Step Counter Load into Accumulator (SC A) — The SCA instruction (7441 ) loads the contents
the SCA
AC. The AC should be cleared prior to this instruction, or the CLA instruction may be combined with

AC during logical sequence 1. The transfer SC to AC occurs during logical sequence 2, both instrucexactly as in the MQA intions, therefore, can be combined. RCL AC LOAD is developed in this instruction

to clear the

struction.

SC V AC = > AC

EAE Operate Instructions

7.4.6

that
There are five EAE instructions that set CPT T5 RECYCLE: ASR, LSR, SHL, MUY, and DVI. Instructions
08
in
bits
coded
are
instructions
These
require T5 RECYCLE are referred to as EAE timing in this section.

through 10 of the instruction word; this coding transfers timing from the CP to EAE timing at TP3 of the

FETCH cycle, with the operation being performed during the EXECUTE cycle.
Arithmetic Shift Right (ASR) - The ASR instruction (74I5g) causes the combined contents of the AC and

location. The
to shift right one more position than the number contained in the next sequential core memory

following occurs:

The contents of MQl

are lost.

ACOO is loaded into the L.
ACOO is loaded into ACOO.

During the FETCH cycle, the contents of MB bits 08 through 1 1 are loaded into the N counter (IR bits 08
through 1 1), Link is zeroed, the contents of AC are added directly back into AC, and the EXECUTE flip-flop is
set.

During the EXECUTE cycle, the contents of MB bits 08 through 1

step counter (SC).

are complemented and loaded into the

EAE timing is then started.

Logical Shift Right (LSR) - The LSR instruction (741 7g) causes the combined contents of the AC and the
to shift right one position more than the number in the next sequential core memory location.

occurs:

MQll is lost.
L is loaded with a zero.

7-8

The following

During the FETCH cycle, the contents of MB bits 08 through
the contents of the AC are loaded directly back into

MB 08 through

are loaded into the N register, the L is zeroed

the AC, and the EXECUTE flip-flop is set.

The contents of

are complemented and loaded into the SC during the

EXECUTE cycle. Then EAE timing is
started, and CP timing is suspended in T5 RECYCLE.
The contents of the AC and MQ are then shifted the num1

ber of times to the right as specified by the SC.

Shift Left (SHL) - The SHL instruction (741
left one position more than the

3g) causes the combined contents of the AC and the

MQ to shift

number in the next sequential core memory location after the instruction.

The

following occurs for each shift:
1.
2.
3.

The content of the L is lost,
The content of ACOO is loaded into the L,
All other AC bits move one place left,
MQOO is loaded into AC
all other MQ bits move one place left, and
MQ! is loaded with a 0.
1

;

During the FETCH cycle, the contents of MB08 through

10 are decoded in the N-register, the contents of the PC

are loaded into the MQ, and the

EXECUTE flip-flop is set. The contents of MB07 through
are complemented
and loaded into the SC during the EXECUTE cycle.
Then the T5 RECYCLE is set and EAE timing is started.
The contents of the AC and MQ are then shifted left the required
number of times.
1

The logic IS the same as for the ASR and LSR instructions during
the logic is the same as the ASR and LSR until

Multiply (MUY) - The

the FETCH cycle. During the EXECUTE cycle,

the EAE timing is started.

MUY instruction (7405g) multiplies the number in the MQ by the number held in the
MUY instruction. At the end of the instruction, the twelve most

next successive core memory location after the

of the product are contained in the AC and the twelve
least significant bits of the product are
contained in the MQ. During the FETCH cycle, the
usual operations necessary for an EAE instruction
are performed. During the EXECUTE cycle for MUY, the
SC is cleared to receive the number of Multiply operations.
For each operation, the SC is incremented. The SC does
not have to count more than 1
significant bits

Before discussing the actual logic of the

MUY instruction, some discussion of binary multiplication as performed

by the EAE is necessary. To multiply two numbers together
(12
erations are necessary. These numbers in binary
form are:

001 1002
Step

j^.

times

12,o)

with the EAE, the following op-

001 100

xOOl 100

000 000

€1

Step 2

Partial Product

001 100

xOOl 100

000 000
0000 00

(from Step

0000 000

Second Partial Product

(continued on next page)

7-9

step 3

001 100

xOOl 100

000 000
0000 00

(from Step 2)

001100
00110 000

Third Partial Product

Step 4

001 100

xOOl 100

000 000
0000 00
00110 0
001100

010010 000

(from step 3)

Fourth Partial Product

Steps 5 and 6

001 100

xOOl 100

In Step 1

000 000
0000 00
00110 0
001100
000000
000000

(from Step 1)

00010010 000

Final Product (

(from Step 2)
(from Step 3)
(from Step 4)
(from Step 5)
(from Step 6)

144 JO

the least significant bit in the multiplier is multiplied by the multiplicand and forms a partial product.

Because binary numbers (Os and 1 s) are being used by the computer, some definite rules can be estabhshed.

When the least significant bit in the multiplier is a 1, the multiplicand is added to the partial product. When the
least significant bit in the multiplier is a 0, then Os are added to the partial product. The number of operations
necessary to perform this multiplication is six.

When the same multiphcation is performed using

2-bit numbers,

the number of operations necessary is twelve. Because the SC (D-BS-KE12-0-EAES) must increment one time
less than the number of operations performed, the

SC reaches 12 to terminate EAE timing. Even when multi-

plying the largest binary numbers that can be expressed in 12-bits, the number of operations is the same, and the

number of bits in the product does not exceed 24. When an addition of either Os or the multiplicand is made to
the partial product, the least significant bit does not change.

To determine whether to add Os or to add the mul-

tiplicand to the partial product the least significant bit of the multiplier is examined; if it contains a 1, the signal

EAE MB ENABLE H must be generated. If it contains a 0, then EAE MB ENABLE must be inhibited, allowing
0 to be added to the contents of the AC. The EAE actually shifts the contents of the AC and MQ to the right to
add Os. The least significant bit (LSB) is examined, and if it is a 0, then the L, AC, and MQ are shifted to the
right.

If the

LSB is a

then the MB is added to the AC, and the L, AC, and

MQ are shifted to the right.

Divide (DVI) — The DVI instruction (7407g) divides the 24-bit dividend contained in the AC (12 most significant bits) and the

MQ (12 least significant bits) by the number located in the next sequential core location after

the DVI instruction.

7-10

The simplest Divide algorithm, although not the one used in the

KE12, is that of subtraction test, subtractions,

and shifts. Assume that a double-precision number has
been loaded into the
IS

present

AC and MQ, and that the dividend
MEM + AC is

m the MEM register as read from memory. A test subtraction is taken (for example,

placed on the register bus). If an OverOow results,
the subtraction cannot be made
sign.

The entire AC and MQ are shifted left without actually executing

without causing a change in

the subtraction, and a 0 is shifted into
the MQl 1 to form a part of the quotient. If
Overflow does not result, the subtraction is performed before,
or as
a part of the shift, and a 1 is loaded into the
MQl 1. The process is very similar to longhand decimal division.
In the KE12, the algorithm used is slightly more

complicated, although faster. A subtraction and shift is perA Flow Chart for the DVI instruction is shown in Figures 7-3 and 7-4. If Overflow does
not result (indicated by FLK ADDER LINK), a
is loaded in MQl 1, and the next arithmetic
operation is an Add and

formed.

Shift.

The adding process continues until another Overflow is encountered,
tion.

and Os are loaded into MQl 1 for each addi-

Overflow indicates that the partial remainder is now positive, and

that the arithmetic operation should be-

come a subtraction. At the conclusion of the Divide operation
(SC = 13), the remainder (now

in the AC) may
have to be corrected, and the LINK cleared. The
correction depends on the last two bits in the quotient.
last two bits are

MQ 0 = 0 and MQ
1

If the

the remainder is correct as is. If the last two bits are
both

mainder must be complemented. Other combinations of
MQl 0 and MQl 1 result in an extra

the re-

addition or sub-

traction.

The first subtraction in any Divide must produce a negative result;
flow exists. If Divide Overflow occurs (division by
0 is a classical
contained in 12 bits, and the EAE signifies this by immediately

Normalize (NMI) - The NMI instruction (741
its exponent)

otherwise, a condition known as Divide Over-

example), the resulting quotient cannot be

exiting from the division with the Link set.

1) is used, in part, to

for use in floating point arithmetic.

tents are shifted left, by this command, until the

convert a binary number to a fraction (and
The AC and MQ are treated as one long register and their con-

content of ACOO is not equal to ACOl

When this instruction is completed, the SC contains a number equal

to the number of shifts performed.

The con-

tents of the L are lost. During the NMI instruction,

EAE timing is started, but the CP stays in a FETCH cycle
and the T5 RECYCLE is set. The NMI is the only EAE
instruction that starts EAE timing but does not require
an EXECUTE cycle. During logical sequence
MB bits 08, 09, and 10 are loaded into the N register and the SC
IS cleared. A normalize test tree
(D-FD-KEl 2-0-2) checks the number contained in the AC and
1

the

MQ to deter-

mine if it is already in the normalized condition.
Step Counter Load from Memory (SCL) - The SCL
tions, one containing the number to be loaded

ry word bits 07 through

instruction (7403) requires two sequential memory loca-

into the SC. This instruction loads the complement of
the memo-

(the word located in the next sequential memory

tion is a two-cycle instruction; it goes into an

address) into the SC. This instruc-

EXECUTE cycle but does not start EAE timing. During the

FETCH cycle, the MA is incremented by one and loaded into the PC; then the memory

word is loaded into the

MB and IR. The contents of the PC are loaded into the MA and the EXECUTE
state is entered. During the
execute cycle, the contents of the memory word (next MA) are complemented and
loaded
into the SC.

7.5

KP12 POWER FAILURE RESTART

A M703 Power Fail Module located at the memory section of the Central Processor location

F03, is utilized for
program in the event of power failure. When a power failure occurs,
an
Interrupt Flag is decoded as shown on drawing
D-BS-KPl 2-0-PWF. When the power goes below the
this option, which protects an operating

specified

operative level, the MCT SHUT

DOWN signal goes low and sets the PWF PWR LOW flip-flop. The zero side of

the flip-flop is gated onto the common interrupt bus

in the CP, which is enabled at this time.

7-1 1

The PWF STOP OK

12-0248

Figure 7-3

KE 2 EAE DVI Flow Chart
1

7-12

Link

Carry

Step

Accumulator

Multiplier-Quotient

Memory

UUU 000 000 000

000 010 010 001

000 000 001 100

111 111 111 111
1

0
0
0
1

000 000 001 100
000 000 001 oil
000 000 010 111
111 111 101 000
000 000 001 100
111 111
100
111 111 101 000

Counter

AC ENABLE

MEM ENABLE
000 100 100 010

Output of ADDERS

000 000 001 100

00 001

AC ENABLE

MEM ENABLE

001 001 000 100

Output of ADDERS

000 000 001 100

00 010

111111 101 000

AC ENABLE

010 010 001 000

000 000 001 100

00 on

111 111 101 000
000 000 001 100
0
1

AC ENABLE

100 100 010 000

Output of ADDERS

000 000 001 100

00 100

AC ENABLE

000 000 001 100
1

MEM ENABLE

111 111
100
111 111 101 001

111

001 000 100 000

000 000 001 100

00 101

in 101 001

AC ENABLE

MEM ENABLE

111 111
101
111 111 101 010

010 001 000 000

000 000 001 100

00 no

AC ENABLE

MEM ENABLE

no no

111 111
111 111 101 100

100 010 000 000

Output of ADDERS

000 000 001 100

00 111

AC ENABLE

000 000 001 100
111 111 111 000
111 111
001

111 111

MEM ENABLE
000 100 000 000

Output of ADDERS

000 100 001 100

01 000

no 001

AC ENABLE

MEM ENABLE

in 111 111 101
111111111 010

111 111 111 010
000 000 001 100
000 000 000 no
000 000 001 100
111 111

001 000 000 000

000 000 001 100

01 001

AC ENABLE

MEM ENABLE
010 000 000 001

000 000 001 100

01 010

noon

111 111 111 111
111 111 111 111
111 111 111

AC ENABLE

100 000 000 on

000 000 001 100

in in no loi
in 111 no 101
111 111

AC ENABLE
000 000 000 11

000 000 001 100

Output of ADDERS
01 100

AC and MQ LEFT SHIFT
End of 12th operation

AC ENABLE
000 000 001 100

000 000 001 100

01 101

MEM ENABLE
Output of ADDERS
MQ LEFT SHIFT ONLY
End of 13th operation

no 101

000 000 001 100
000 000 000 001
000 000 000 001

AC and MQ LEFT SHIFT

MEM ENABLE

000 000 001 100
0

Output of ADDERS

End of 11th operation

111 111 101 001

Output of ADDERS

AC and MQ LEFT SHIFT
End of 10th operation

MEM ENABLE

000 000 001 100
000 000 001 on
000 000 010 no

Output of ADDERS
AC and MQ LEFT SHIFT

End of 9th Operation

000 000 001 100
0

AC and MQ LEFT SHIFT
End of 8th operation

000 000 001 100
0

AC and MQ LEFT SHIFT
End of 7th operation

111 111 101 100

Output of ADDERS
AC and MQ LEFT SHIFT

End of 6th operation

111 111 101 010
000 000 001 100
1

Output of ADDERS
AC and MQ LEFT SHIFT

End of 5th operation

000 000 001 100
1

AC and MQ LEFT SHIFT
End of 4th operation

111 111 101 000
0

Output of ADDERS

AC and MQ LEFT SHIFT
End of 3rd operation

MEM ENABLE

111 111
100
111 111 101 000

AC and MQ LEFT SHIFT
End of 2nd operation

MEM ENABLE

no 100

111 111

AC and MQ LEFT SHIFT
End of 1st operation

111 111 101 000
000 000 001 100
0

Comments

Since SC= 13 and MQ10=0

and MQl 1=0 MEM and AC->AC,

000 000 001 100

Figure 7-4

000 000 001 100

01 101

KE12 EAE DVI Algorithm

7-13

NO SHIFT

signal goes low for

off for this 1

ms and is connected to the G826 Voltage Regulator to inhibit the regulator from shutting

ms duration. This allows the subroutine time to store all the active registers and initialize the pe-

ripheral devices before halting the computer.

A toggle switch located on the M703 Module controls the automatic restart feature of the option. When the
primary power. A
switch is in the ENABLE or on position, the following functions occur upon restoration of
200 ms delay is initiated and at the end of the delay, the PWF RESTART pulse is generated. This pulse initiates
function. The RCL
the manual function timing chain which sets the RUN flip-flop and simulates a START key
START PC pulse is generated and the PC is cleared allowing the program to start at address 0.
7.5.1

Programming

A skip circuit provides programmed sensing of the condition of the Power Low Flag by adding the following instructions to the computer’s repertoire:

SPL Skip on Power Low
Octal Code:

6102

Event Time:

Execute Time:

4.25 /is

Operation:

The condition of the Power Low Flag is sampled; if set (indicating a power failure has occurred), the contents of the PC are incremented by one, skipping the
next sequential instruction.

Symbol:

If Power

Low Flag =

1 ,

then PC + 1 -»• PC

Figures 7-5 and 7-6 illustrate the Automatic Restart Program Events and Typical Power Failure

Program Service

Routine, respectively.

7.6

KTl 2 TME-SHARHMG OPTION

The KT12 Time-Sharing Option prewired in the processor section of the PDP-12 provides the additional logic
and other options
circuits required for the TSS/ 12 Time-Sharing System. Certain configurations of I/O devices

must also be used with the TSS/ 12 Time-Sharing System. The minimum equipment required for a four-user
Time-Sharing System is:
a.

PDP- 1 2 with KT 2 Time-Sharing Option

MCI 2 Memory Extension Control and 8K of memory

RF08 Disk Control

RS08 Disk File

Asynchronous Serial Line Interfaces Full-Duplex, Dual Channel (four required) DC02E, DC02F,

or PTOC
/.

PR 2 High-Speed Tape Reader - 300 characters per second

KE12 Extended Arithmetic Element

PDP-1 2 Option Cabinet

The TSS/ 12 Time-Sharing System permits up to 16 users to operate their individual programs in an apparently
simultaneous manner. Operation and reaction time of some I/O devices and of human operators is slow compared to the speed of the CP; time-sharing allows the CP to proceed to other tasks rather than wait for slower

7-14

PROGRAM MUST BE RESTARTED
MANUALLY,
UPON

RESTART, THE
INSTRUCTION IN
LOCATION OOOOg
IS

PEREORMED

LOCATION

0/JMP X

LOCATION X CONTAINS THE
BEGINNING OF THE RESTART
PROGRAM, WHICH RESTORES
THE CONTENTS OF LINK. AC, PC
AND ANY OTHER INFORMATION
STORED BY PWR FAIL SERVICE
SUBROUTINE. CONTINUATION
OF THE PROGRAM
AUTOMATICALLY OCCURS.

Figure 7-5

CONTINUE

MAIN PROGRAM

Typical Power Failure Program Service Routine

ENTER DEVICE
SEARCH
SUBROUTINE

POWER FAIL SUBROUTINE NOT ENTERED
THE REGISTER CONTENTS ARE NOT
SAVED PROGRAM, HAS TO BE MANUALLY
RESTARTED FROM BEGINNING,

STOP THE NEXT SEQUENTIAL
'NSTRUCTION AND ENTER

THE PROGRAM CONTINUES FLAG CHECKING
NOTE WITH REAL-TIME APPLICATIONS
THE TIME REQUIRED FOR
CHECKING REDUCES THE TIME
FOR THE real-time SERVICE
SUBROUTINE POSITION KPI2
INQUIRY NEAR THE BEGINNING

KPI2 SERVICE ROUTINE

DCA AC

/IN^^RRUPT was CAUSED BY POWER LOSS FLAG

RAR
DCA LINK

/GET LINK
/SAVE LINK
/GET MO
/SAVE MQ
/GET PC
/SAVE PC
/GET RESTART JUMP INSTRUCTION
/DEPOSIT RESTART INSTRUCTION IN

MQA
DCA MQ
TAD OOOOo

DCA PC
TAD RESTRT X
DCA OOOOg

HLT

Figure 7-6

Automatic Restart Program Events

'-15

OOOOg

operations.
is

As a result, it seems to each user as if each had full use of the processor. The program of each user

executed for only a fraction of a second at a time; the different programs are interspersed without interfering

with each other and without noticeable delays in the response to each user.

TSS/Monitor Program

7.6.1

Time-sharing of the PDP-1 2 Central Processor by a group of users is controlled by a group of subprograms called

TSS/12 Monitor, which coordinates the operation of various I/O devices, allocates CP time and services to the
users, and controls user access to the CP.

User programs are usually stored in disk memory and are transferred

into core memory; activation of the user programs is handled by a sequential loop algorithm under the control

of the TSS/Monitor. The user program is allowed to run for a fixed period of time and is then stopped. The
contents of the PC and the various registers are stored at the time execution is stopped; the program is returned
to disk storage; and the next user program is read into core memory for processing.

User programs are terminated by the TSS/12 Monitor for various reasons other than the expiration of their allotted time period.

They are terminated when the output buffer is filled, when an input is requested and the in-

put buffer is not filled, and under certain other conditions.

User programs are not allowed to perform HLT, OSR, or lOT instructions in the usual manner because normal
processing of these instructions would disrupt the operation of the CP or interfere with the operation of I/O devices shared with other users.

When one of these instructions appears in a user program, a User Interrupt (UINT)

takes place and the TSS/Monitor takes control of the CP. Three instructions are added by the KTl 2 to permit

the TSS/Monitor to process UINTs caused by HLT, OSR, or lOT instructions.

7.6.2

KTl 2 Program Instructions

The KTl 2 uses three additional instructions to permit the TSS/Monitor to handle UINTs and to control the

UINT logic circuits. These instructions are listed with their octal codes and descriptions in Table 7-5.
Table 7-5

KTl 2 Program Instructions
Mnemonic

Octal

Code

CINT

6204

Clears User Interrupt. Resets the UINT flip-flop to 0 state.

6254

Skip on UINT.

Description

SUF

6274

When the UINT flip-flop is in the

state, the

incremented by one and the program skips the next instruction.

Sets the User Flag. Sets the User Buffer (UB) flip-flop and inhibits

Processor Interrupts until after the next IMP or JMS instruction.

The contents of the UB are transferred to the UF with the next

JMP or JMS instruction.

SADC

6145

Sample A/D Channel

NOTE
Processor Interrupts are inhibited between the SUF
instruction and the loading of the UF flip-flop.

7-16

The KTl 2 operates in two modes, as denoted by the UF nip-Hop. When the UF flip-flop
is in the logic
operation is in the user mode and a user program is executed in the CP.
state, operation is in the executive mode and the TSS/Monitor

in control of the CP.

tions are used by the TSS/Monitor only in the executive mode, and

state,

When the UF flip-flop is in the logic 0
The three added instruc-

are never used by the user program. If a user

program attempted to use one of these instructions, execution would be blocked
cause these are lOT instructions (octal code 6XXX).

and a UINT would result, beThe LINCtapes are used the same way as DECtape is used

on the TSS8. Also, a new set of lOTs (8 Mode) has been implemented for
time-share mode users.

The KTl 2 requires two additional modules. Additional gates from modules used
with other prewired options are
also required.

The additional modules are shown in Table 7-6.

Table 7-6

KTl 2 Modules
Module

Quantity

M216
Ml 17

Flip-Flops

NAND Gates
NAND/NOR Gate

M121
M623
Ml

Slot

H
H

M
M
M

Bus Driver
Inverter

Row

21*

40*

These modules are shared with other prewired options.

General Logic Description

7,6.3

The PDP-12 CP operates in the executive mode (UF(0) high) so that the
sary housekeeping and service routines, or in the user mode
Its

Location

Use

Type No.

TSS/12 Monitor can perform the neces-

(UF(1) high) so that an individual user can perform

programmed tasks. Either mode of operation is subject to Program Interrupts
that are handled by

rupt logic of the CP.

When a user program is operating (user mode), the decoding of HLT,

tions causes an Interrupt, and the execution of these instructions
circuits that generate an Interrupt in the user mode when

aborted.

the Inter-

OSR, or lOT instruc-

A simplified diagram of the logic

an HLT, OSR, or lOT is programmed is shown in Fig-

ure 7-7.

When either an HLT, OSR, or lOT instruction is decoded in the CP Instruction Register
flop is set, the Int Req Bus level changes to a true state and the
i.

(IR), and the

UF flip-

following functions are performed:

The UINT, and the INTERRUPT SYNC Save User Flag (SUF) flip-Hops are set.

The CP enters the INTERRUPT state at the next CPTPl pulse, the UP flip-Hop

cleared at TS3

and the standard functions for the INTERRUPT cycle are executed.

The Int Req Bus level remains true until the CINT instruction is given: therefore,

this instruction

should be executed in the Interrupt handling subroutine.

lOT 6254 SINT checks the status of the UINT flip-flop. When this instruction is
executed and the UINT flipflop is set, the I/O SKIP BUS level becomes true, and the PC is
struction.

7-17

incremented by skipping the next sequential in-

INT REO BUS

Figure 7-7

7.6.4

KTI 2 Simplified Block Diagram

Detailed Logic Description

Engineering drawing D-BS-KT 1 2-0-TSS is a detailed block schematic of the logic circuits that are added to the

PDF- 12 for the KTI 2. The TSS User Buffer (UB), the TSS User Flag (UF), Save User Flag (SUF), and the UINT
flip-flops with their associated gating circuits are shown on this diagram.

The TSS UB, TSS UF, and TSS SUF

flip-flops can be considered as 1-bit extensions of the Instruction Buffer (IB) register, the Instruction Field (IF)
register, and the Save Field (SF) register, respectively.

These registers are part of the extended memory logic and

are shown on engineering drawing D-BS-MC12-0-MXR.

The signals used to clock these registers are also used to

clock the TSS UB flip-flop, TSS UF flip-flop, and TSS SUF flip-flop.

TSS User Buffer (UB) — This is a D-type flip-flop shown in location H29. The data input level is derived from

AND/NOR gate and is true when the signal is low (ground), when the SUF instruction is
initiated, or when the RMF instruction is given and the SUF flip-flop is in the
state. The flip-flop is clocked at
the output of a Ml 21

TP5D of both of these instructions.
The flip-flop is cleared with the signal MXFO-IF-IB L shown on engineering drawing TSS. This signal is generated
with key I/O PRESET, or when entering the INTERRUPT cycle.

TSS User Flag (UF) — The Clock Input is clocked at TP4 of a JMP or a IMS instruction. This strobes the contents of the TSS UB flip-flop into the TSS

UF flip-flop. The flip-flop is cleared with key I/O PRESET, or at TSS

of the INTERRUPT cycle. The output of the TSS UF flip-flop is gated with the instructions HLT, lOT, and

OSR. When the TSS UF flip-flop is in the

state, normal operation of these instructions is aborted, and an In-

terrupt Request is sent to the CP.

7-18

TSS Save User Flag (SUF) - This flip-nop is used to store the contents of
the monitor to restore normal operation after an Interrupt.

the TSS User Flag and thus enable

The Clock Input is clocked when entering the

INTERRUPT cycle, thus loading the SUF with the contents of the TSS UF flip-flop.
User Interrupt (UINT) - The data input level TSS INT REQ
gate and is true when low (ground),

i.e.,

is derived from the output of an M121
AND/NOR
when one of the instructions HLT, OSR, or lOT is decoded from

CP instruction register (IR) and the TSS UF is set. It is also true when the
struction being executed is not the CINT instruction.

the

TSS UINT flip-flop is set and the in-

The flip-flop is clocked with the TP5D pulse and cleared

with I/O PRESET or the CINT instruction.

Skip and Interrupt Levels - TSS INT SKIP L is derived

from a NAND gate M

The inputs to the NAND gate are true when executing the

7 and is true when low (ground).
SINT instruction and the TSS UINT flip-flop is in the
1

This level is gated onto the I/O SKIP BUS with the
M623 Bus Driver. The common input to the bus
dnver, pm M2, is true when the KT 1 2 flip-flop is inserted
(M2 6) in location H29. The TSS INT REQ Bus level
is true when low, and is also gated
on the I/O Interrupt with the M623 Bus Driver.
1

state.

7.7

KW12-A REAL TIME INTERFACE AND KW12-B, -C SIMPLE CLOCKS

KW 2-A — Real-Time Interface

7.7.1

The KWI 2-A can be used to generate Program Interrupts over a range of
7-7 below)

intervals of 2.5 /xs to 40.96s (see Table

m time base applications; detect external and internal events in order to count them,

against a time base, measure the interval between them,

measure them

use them as a time base standard, or control sample

times of A/D conversions. Figures 7-8 and 7-9 illustrate
the basic relationships

between the KWI 2-A and the

PDP-12 System; for instance, the A/D sample feature.
Table 7-7 lists the time base parameters available with the
tal

clock, is under program control as determined

KWI 2-A. The time base, generated by a 400 kHz crysby the rate field of the clock control word (first word) (XNXX).
Table 7-7

KW 2-A Clock Time Base Ranges
1

Time Base Range*

Resolution

(Stopped)

0.0025 - 10.2400 ms

- 40.96 ms
— 409.6 ms

0.01
0. 1

0.001 - 4.096s
0,01
1

Rate Field

2.5 JUS

400 kHz

10 JUS

100 kHz

100 JUS

10 kHz

ms
10 ms

kHz
100 Hz

Oor 7

- 40.96s

Frequency

— 4096 counts of Input T Events
Time base within each range selected, using mode field of clock control word.

The three external events inputs, INPUTS
ence of events detected in I/O or

through 3, may be simulated by program/subroutines on the occur-

DMA peripherals. The appropriate simulated input

7-19

transferred from the AC

information by the CLLR instruction (6132).

Figure 7-8

KW 2-A Real Time Interface Functional Relationship
1

A clock enable word (CLEN instruction) is required to enable the desired Input Event lines and the clock conditions selected to produce a Clock Interrupt Request to the CP. If an external input (an instrument or the power
line waveform) and the corresponding Interrupt are both enabled, a Program Interrupt is generated by the Event.

A clock status word (CLSA instruction) informs the program of the clock condition in a clock-initiated Program
Interrupt. A summary of lOT instructions associated with a KWl 2-A is presented in the PDP-12 System Reference Manual, Paragraph 6.2.

The KWl 2-A is a prewired PDP-12 option with an input control panel, which mounts behind the vertical door on
the left front of the PDP-12.

The Real-Time Interface can be used to synchronize the Central Processor to exter-

nal events, count external events, measure intervals of time between events, or provide program interrupts at

programmable intervals from 2.5 ms to over 40s. Some of the above-mentioned operations can be done simultaneously.

INPUT channel

may be used to enable an external source to drive the counter. This external source may be

switch-selected to be either the power line waveform or an actual signal from a laboratory instrument.

The pro-

grammable selection of the rate is accomplished with the three rate-bits of the clock control register (CLLR instruction).

Input Synchronizers

Three input channels (INPUTS 1 through 3) are used to convert external events into a synchronized control and
status signal for the clock.

Each input channel consists of an input Schmitt trigger with pulse generator, five flip-

flops, and associated control gating.

The Schmitt trigger and pulse generator convert the preselected voltage

threshold crossing by an external signal into a single event (pulse). This Schmitt trigger has level and slope

7-20

INPUT

INPUT 2

INPUT 3

100kHz

10kHz

1kHz

100
1

Figure 7-9

selection controls available on the front panel.
positive- or negative-going slope.

2 - 0(10

KW 2-A Organization
1

They provide selection of only threshold between ±6V and either

The Schmitt trigger has a hysteresis of 0.3V.

The five input circuit Oip-Oops are: INPUT ENABLE, INPUT, PRE EVENT, EVENT, and ENABLE
EVENT

INTERRUPT (see Figure 7-10). Figure 7-1

shows a basic timing of the Input Synchronizer.

Not shown in Figure 7-10 is the logic which clears the EVENT and PRE EVENT Hip-flops when the
struction is given. This logic ensures that events occurring during the execution of
the present
are indicated when the next

CLSA in-

CLSA instruction

CLSA instruction is given.

External signals (from up to three instrument/sources) are connected to the INPUT jacks

on the front panel via
standard 3-conductor telephone plugs. Each INPUT and OUTPUT jack is wired in
parallel to permit convenient
connection ot the external input signals to the KWl 2-A, and if desired, the Analog-to-Digital
nal devices.

inputs up to ±50V.

A level control and a slope control are associated with each input. The level control selects

the threshold voltage at which the trigger pulse is generated.
nal causing a trigger pulse.
is

Converter or exter-

The input is differential, ±5V range, input resistance greater than 10.00012, and protected against

The slope determines the polarity of the input sig-

The trigger pulse sets the associated input llip-flop of the clock if that input channel

enabled.

7-21

INPUT

ENABLE

INTER.

REQ L

12-0194

Figure 7-10

Simplified Input Synchronizer Logic Diagram

KW12-A Real-Time Interface Instructions — The KW12-A is controlled by PDF- 12 lOT instructions. These instructions can be used with either 8 or LINC Mode. Execution time for the lOTs is 4.25 ms when in 8 Mode, and
5.9 MS when in LINC Mode (using lOB). Refer also to Paragraph 6.2.1 .3 of the System Reference Manual
Detailed Discussion

Clock control is accomplished by programmed lOT instructions. As with any device utilizing the I/O Bus, the

most significant digit of the lOT instruction is 6nnng. The center two octal digits (bits 3 through 8 of the lOT
instruction) form the clock’s device code, which must be 13g.

The device decoder within the clock enables the

clock lOP gates when this device code occurs in an lOT instruction (Drawing D-BS-KWl 2-0-CLC).

The lOP

pulses, recombined with the bits of the three least significant octal digits of the lOT instruction, produce the

complete clock instruction set (613ng).

The clock control word (CLLR instruction) is transferred from the AC to the clock control registers (a 6132 instruction).

The most significant digit of this word is stored in the RATE register (Drawing D-BS-KW 2-0-CLR).
1

These three bits are decoded to select one of the five internal clock rates, or no rate (clock stopped) to the clock
counter (Drawing D-BS-KW 2-0-CLKA, B). The clock MODE control register is loaded with the second most
1

significant digit of the clock control word (bits 3, 4, and 5).

simulate events on clock INPUTS CHAN-1

Bits 7, 9, and

2, and 3, respectively (Drawing

of the clock control word, if set,

D-BS-KW 2-0-CLEA, B, and C).
1

These bits are not stored, but act in the same manner as external events on these inputs. Bits 6, 8, and 10 of the

do ck control word are not used.
The clock enable word is transferred from the AC to the clock enable flip-flops with a CLEN (6134) instruction.
The flip-flops of this register are shown as the EN INPUT and EN EV (N) T (Enable Event Interrupt) flip-flops
on the three input channel block schematics (Drawing D-BS-KW 2-0-CLEA, B, and C) and the EN OV IN T
1

7-22

SYNC.

STROBE

—

— ——

COUNTER
^

100ns

II
I

600ns BUFFER
HERE

— 1^
SYNC
STROBE 2

SYNC
STROBE

)

INPUT
FLIP-FLOP COUNTER
INCREMENTED
HERE -

juLjclr

PRE-EVENT
FLIP-FLOP
INPUT

FLIP-FLOP

EVENT
FLIP-FLOP
Timing diagram for Channel 1 only If the
6g and Channel 1 input

PRE-EVENT
FLIP-FLOP

rate field equals
is

EVENT

CP INTERRUPT
HERE

NORMAL

ERROR

Normally PRE-EVENT Is reset.
If however, EVENT was already set,
PRE-EVENT remains set as an error
flag; indicating that more than one
input occured between cleoring of the

may be used to increment the
counter. For this case the
timing diagram is shown below.
3.

EVENT flip-flop
2. EVENT is cleared only by the CPU using
the

FLIP-FLOP

enabled

6135 (CLSA) instruction

following exception

Inputs

Error indication that 6135
(CLSA) instruction wos not
issued soon enough followin g
an EVENT.

with the
to

Channel

12-0205

Figure 7-1 1

KW12-A Timing Diagram

(Enable Overflow Interrupt) flip-flop on the D-BS-KW12-0-CLIO block schematic. Bit 4 of the clock enable
word, if set, causes transfer of the contents of the clock buffer register to the clock counter if the CLR MODE
register contains

or 5. This bit (4) is not stored in the clock; the transfer occurs when the clock enable word is

transferred from the AC. Gating for bit 4 is shown at coordinates A, 6 on block schematic D-BS-KWl 2-0-CLR.

Transfers from the AC to the buffer preset register are accomplished using a CLAB (6133) instruction.
fer register is shown across the bottom of block schematics D-BS-KWl 2-0-CLKA and D-BS-KWl

The buf-

2-0-CLKB as

CLKA BUFOO-05 and CLKB06-1 1.
Clock status data is transferred from the clock to the AC, using the CLSA (6135) instruction. The status register
in the clock consists of the EVENT (N) and PRE EVENT flip-flops of each of the three input channels and
the

OVERFLOW flip-flop. The relationship and timing of the EVENT and PRE EVENT flip-flops are discussed below (see also Figure 7-1

Drawing D-BS-DW-1 2-O-CLIO shows the gates from the status register flip-flops to

the CP internal I/O bus at C, D-2.

Clock Interrupts are produced by one or more of four conditions set up in the clock enable flip-flops (see Figure
7-10).

These conditions are an EVENT on an interrupt-enabled input channel and/or clock counter OVERFLOW

if enabled.

Internal clock data transfers are controlled by the

MODE register. The most significant bit of this register
and 2), and is used to enable the OVERFLOW signal

(MODE 0) is independent of the lesser two bits (MODE

7-23

to the A/D Converter option to initiate a Sample.

The lesser two bits of the MODE register control transfers be-

tween the clock counter (CNT) and the clock buffer preset register (BUF).
the clock counter (CNT) at the time an enabled

MODE bit

set, the count in

EVENT occurs is transferred to the clock buffer preset register.

The details of this logic are shown on D-BS-KWl 2-0-CLC and on each of the three input channel drawings

(D-BS-KW12-0-CLEA, B, and C) of Volume III.
is enabled,

MODE bits

and 2 (least significant bits) are set and INPUT 3

the shift counter (clock counter) contents are transferred to the clock buffer preset register and the

clock continues to count. This logic is also shown on D-BS-KWl 2-0-CLC. If

MODE bit

MODE register bit 2 is set and

reset, the contents of the clock buffer preset register are transferred to the clock counter when the

counter overflows, or when a clock enable word with bit 4 set (1) is transferred from the CP accumulator to the
clock. This logic is shown on D-BS-KWl 2-0-CLR.

Except for minor differences that permit external events on the input channels to increment the clock counter,
the three INPUT channels are identical.

INPUT CHAN 2 is discussed here as typical of the three; it is shown in

Volume III on block schematic D-BS-KWl 2-0-CLEB. Events outside the PDP-12 System are accepted at a
Schmitt trigger which drives a pulse generator (M503 Module). The time relationship of the EVENT and PRE
EVENT flip-flops is shown in Figure 7-11. The SYNC generator is a ring counter (shown on block schematic
D-BS-KWl 2-0-CLC). INPUT CHAN (CLEA) differs from INPUT CHAN 2 (CLEB) and CHAN 3 (CLEC) in
that it may be used to increment the clock counter from an external source to count events when the RATE
1

(CLLR instruction) is 6g (ACOl + 02 (1) ). On block schematic
D-BS-KWl 2-0-CLEA it can be seen that a counter-to-buffer transfer (CNT TO BUF) is inhibited and the EVENT

field of the clock control word

flip-flop is set when the

RATE field is 6g. This logic prevents the clock buffer preset register from copying the

contents of the clock counter (CNT) each time the counter is incremented by an event on channel 1. Because
the EVENT flip-flop is set each time this mode of operation is initiated, the clock counter is also incremented.

The SYNC generator senses two purposes:
a.

Primarily, it prevents transfer from the clock counter register into the clock buffer before the in-

crement has had time to propagate through all 12 bits of the shift counter. This time is the limiting factor for the maximum rate at which the clock may be incremented.
b.

Because of its relationship to the maximum clock rate, the SYNC generator strobes the PRE
EVENT and EVENT flip-flops (Drawing D-BS-KWl 2-0-CLEA, B, and C). An error condition is
indicated if two Events occur on the same input channel at a rate faster than the clock can incre-

ment. This feature is particularly important for INPUT CHAN
clock counter.

when it is used to increment the
The SYNC generator is inhibited during CLBA (6136) and CLCA (6137) instruc1

tions which transfer data from the clock buffer register and the clock counter to the CP. This

function is performed by the I/O SYNC flip-flop shown on D-BS-KWl 2-0-CLC near the SYNC
ring-counter, and prevents counter-to-buffer transfers while a clock buffer-tp-AC transfer is occurring.

7.7.2

KW12-B and KW12-C Simple Clocks

The KW12-B and KWl 2-C clocks can provide Program Interrupts at manually selected clock rates. The KWl 2-B
Interrupt rate is set by a jumper and potentiometer on the M401 Oscillator Module which uses an RC time base.

The KWl 2-C uses a crystal M405 Oscillator Module. The only program control for these clocks is ON and OFF.

The only data available from the KW 2-B and KWl 2-C is a Clock Interrupt occurring at the preset time-base rate.
1

The only clock status information available to the program is clock ON or OFF. A simplified block diagram,
showing the relationships of the KWl 2-B and KWl 2-C to the CP is shown in Figure 7-12. Descriptions of time
base ranges and the instruction set are presented in Paragraph 6.4.2 of the PDP-12 System Reference Manual.

7-24

PDP-12

SYSTEM

I
I

KW 12-B OR
ON/OFF
CENTRAL
KW12-C
a INTERRUPT
PROCESSOR
REAL
CONTROL
1

TIVE(SIMPLE)!

CLOCK
OPTION
(NOTE 1)

TIME

INTERRUPT
TIME
SKIP

KW12-B has manual adjustable R/C time
base

KWt2-Chas factory preset crystal time
base
12-0242

Figure 7-12

K W 2-B and KW 2-C Simple Clocks,
1

PDP-12 System Functional Relationships

KW12-B
The KW12-B provides a simple means of interrupting the CP at intervals determined

by a variable TC Oscillator

(M40 Clock) Module. The KWl 2-B may be turned ON or OFF only under program
1

ations in frequency require a manual operation; physically
a potentiometer.

control.

However, any vari-

changing the oscillator by the use of wire jumpers and

Refer to Volume III, Drawing D-BS-KWl 2-0-CLUB.

The KWl 2-B uses the M401 Clock in slot location FI 8, thus precluding the

installation of any combinations of

KW12-A, -B, or -C together in the same PDP-12 cabinet. Paragraph 6.2.2 of the System

Reference Manual lists

the frequencies available for the KWl 2-B Simple Clock.

KWl 2-C
The KWl 2-C Simple Clock also uses the M405 Clock Module (in slot location

FI 8), as does the KW12-A Real-

Time Interface. However, there are no decade counters providing different
frequencies. Any fixed frequency (as
ordered by the user; between 5 kHz and 50 kHz) provides frequency
stability of .01 percent between 0° and
+55°C. As with the KWl 2-B Simple Clock, the KWl 2-C can be turned ON
or OFF only under program control.
Any variations to the frequency would require changing the crystal CRl on the M405
Module.
7.7.3

Block Diagram Discussions

Clock I/O Co ntrol (D-BS-KW 1 2-0-CLR)

The logic shown on this block schematic basically comprises the device

decoder, at coordinates D6 and D7; the

lOP Transfer Decoder, at C and D2 and C and D3 and the SYNC
generator at B4-7.
;

7-25

The SYNC timing chain generator produces the SYNC STROBE which:

clocks the input event signal to the

EVENT and PRE EVENT flip-flops and 2) increments the Clock Counter. The timing chain generator is a ringcounter which disables momentarily, the lOT timing chain which allows the clock counter to settle out after

each increment. At coordinates A6 and A4 are One-Shot Delay flip-flops that provide delays of 600 and 100 ns,
respectively, to allow the clock counter time to settle.

The clock device decoder senses the second and third most significant bits, tests them for 13g, and allows the
lOP pulses to be gated to the clock.

The lOP Transfer logic provides the lOP signals to the correct clock functional logic areas, depending upon the
coding of the least significant bits of the clock lOT instruction.

INPUT CHAN 1 (D-BS-KW12-0-CLEA)
This block schematic shows the logic discussed in the Detailed Discussion of the Input Synchronizers and the
basic timing (see Figure 7-11). External events (either pulse or sinusoidal signals) are applied to the Schmitt trig-

ger shown at D7 (an M503 Module).

An adjustable THRESHOLD control (front panel) applies only preselected

voltage levels to the Schmitt trigger inputs.

The Schmitt trigger produces a pulse of

/is duration.

then output through an emitter follower which provides isolation to switching transients.
to a pulse amplifier (at S2) which shapes the output to the proper logic level (a

(Enable Input) gates on and off input signals to the clock.

It is set

/is

The pulse is

The signal is applied

±5V signal). The EN Input

and cleared under program control. The

INPUT flip-flop is set by an external signal from the Schmitt trigger input or under program control with the

CLLR instruction. The INPUT flip-flop provides synchronization between external timing and internal clock
rates.

The PRE EVENT flip-flop is strobed into the EVENT flip-flop by the STROBE
flip-flop if

signal.

The EVENT flip-flop is loaded with the PRE EVENT flip-flop on the next STROBE
ond STROBE
is

This clears the INPUT

EVENT is cleared.

and set to a

by the sec-

following the setting of the INPUT flip-flop. Subsequent to EVENT being loaded, PRE EVENT

cleared.

The EN EV INT (Event Enable Interrupt) flip-flop permits external events to cause program interrupts.

It is set

and cleared by the CLEN instruction.

The occurrence of CLC STROBE 2 with EVENT (0) and PRE EVENT (1) is the actual single event used by other
parts of the clock logic, such as counting and transfers from counter to buffer-preset register.

The status of the EVENT and PRE EVENT flip-flops is loaded into the AC under program control. When this

EVENT flip-flops are cleared. If a second input occurs before the EVENT flip-flop is cleared, then both the PRE EVENT and EVENT flip-flops will remain set, intransfer occurs, the corresponding INPUT, PRE EVENT, and

dicating an error.

INPUT CHAN 2 (D-BS-KW12-0-CLEB)
INPUT CHAN 3 (D-BS-KW12-0-CLEC)
The logic shown on these drawings is similar to that on D-BS-KWl 2-0-CLEA, except that there is no extra gating
(coordinates C4 and D3, on -CLEA) to permit incrementing the event count (CLKA, B, or C CNT) without the

lOT.

7-26

CLOCK lO INPUT (D-BS-KW12-0-CLIO)
Shown on the right side (C2 and D2) of this drawing are the clock status bits. These can be examined by the
program by issuing a CLSA (6135) instruction.

The EN OVF INT (Enable Overflow Interrupt) flip-flop enables a program interrupt if set by the CLEN
instruction.

(6134)

Note that if the clock skip is enabled (CLIO INT SKIP BUS), the clock interrupt is also enabled

(CLIO INT RQST BUS). A clock skip flag cannot be enabled without the interrupt also being enabled.

CLOCK & BUFFER (D-BS-KW12-0-CLKA, B)
The two registers shown on the CLKA and CLKB drawings are the clock counter register (CNTOO
shift register that holds the current count, and the clock preset

through 1 1), a

buffer, which interfaces the clock with the AC.

The buffer preset register (BUF) is used to buffer the current count in the clock register at the
event when operating with CLR

MODE

set.

occurrence of an
With MODE 1 cleared (0) and MODE 2 set (1), the buffer preset

overflow occurs. The buffer preset register can
be loaded into the AC, or the AC can be transferred into the buffer preset register.

The counter register (CNT) is a 1 2-bit shift counter that is loaded from the buffer preset register or
ferred into the buffer preset.

can be trans-

The counter may be used to count events, measure intervals of time between

events, or provide processor interrupts at program-selected intervals from

2.5 ns to over 40s.

CLOCK RATE (D-BS-KW12-0-CLR)
The logic on this drawing consists of: the clock RATE control register (upper left), the
MODE control register
(upper right), and the clock rate (COUNT) decoder.

The logic across the bottom of the drawing shapes and amplifies an External A/D
the COUNT register load signal (CLR

Initialize signal and generates

LOAD CNT).

The RATE control flip-flops are set by the clock control word (CLLR instruction) and are

applied to the clock

rate decoder logic (coordinates B and C6) to establish the clock interval.

The MODE control nip-flops, also set by the clock control word, establish the clock action

as determined by bits

3 through 5 of the clock control word. Refer to the System Reference Manual,
Paragraph 6.2.1 .3.
flip-flop enables an initialize signal to the A/D option which will start

a conversion, or if

The MODE 0
MODE 0 is not set, the

A/D option will be initialized by the clock at the occurrence of OVERFLOW.
The clock rate decoder selects the rate at which the clock will operate. The logic shown at
coordinates B and C6
and B and C7 form inhibit logic. That is, when any CLTB NNN HERTZ H signal
(where N = frequency) goes
low, the associated gate no longer qualifies, thereby causing the CLR

COUNT flip-flop to increment the clock

counter. These load pulses will occur at the rate selected by the RATE flip-flops.

The CLR OVERFLOW flip-flop is set when the clock counter (CLKA, B) is full (up to 4096 counts) and
sult in a clock interrupt request if the CLIO

will re-

EN OVF INT flip-flop is set (see KW12-0-CLIO).

CLOCK TIME BASE (D-BS-KW12-0-CLTB)
The logic shown on this drawing comprises three decade counters (four flip-flops), binary
use of hardwired preset pulses to count by 10 instead of 16.
to 4s) and are driven by a

counters modified by
The counters provide the frequency intervals (2.5 jus

100 kHz signal generated by an M405 (400 kHz clock) Module through two frequency

dividers (flip-flops CLTB 00, 01).

Note that the logic for the counters is located on the same module as the In-

put Synchronizers (Drawings D-BS-KWl 2-0-CLEA, B, C).

7-27

7.8

TC12-F - 8 TAPE CONTROL

The TC12-F DECtape option extends the capability of the TCI 2 LINCtape System to read and write DECtapes
that are formatted on the PDP-8, PDP-9, PDP-10, or PDP-15 computers. This option is utilized with the

PTYC12-F user’s program (see program document DEC-12-YJYA-D for the program description and the difference between the LINCtape and DECtape formats).

TC12-F Operation

When the LTP8 TAPE flip-flop is set (1) (see dwg. LTP8), the TC12-F is selected. This will inhibit the LWN EN

WIND DECODE signal and invert the timing track input. Data from the MARK Track are shifted into the
RC12-F mark window register and decoded. When reading, data are assembled in the Read/Write Buffer (RWB)
and loaded into the TAC register, and subsequently transferred to the AC with the TAC-to-AC (MSC 3) instruction.

When writing, data are transferred from the AC to the TB with lOT 6154 and loaded into the RWB and

written on tape.

7.8.1

The Tape Break state is not entered for a tape operation employing the TCI 2-F option.

Logic Description (TC12-F-LTP8)

The control logic is shown on the TC12-F-LTP8 block schematic (see Volume III of the Maintenance Manual).

LTP8 TAPE — When this flip-flop is set (

the TCI 2-F option is selected and portions of the TCI 2 LINCtape

Control are disabled. The LWN EN WIND DECODE level is disabled and the input from the timing track is inverted.

WINDOW REGISTER - (LTP8 W1 through W9)
register with every TP3 pulse.

Data from the mark track are shifted into this 9-bit window

The register bits are decoded to give the signal LTP8 BM. This signifies that a

block mark has been detected on the tape and the block number (BM) is in the Read/Write Buffer (RWB).

(It is

assumed here that the reader is familiar with the LINCtape Control theory.)

BLOCK - When the signal LTP8 BM is true, the BLOCK flip-flop is set
is

(

1) with TP4.

The status of the flip-flop

checked with the SKL 14 instruction.

LTP8 WRITE - When the WRITE flip-flop is set, the LTP8 WRITE SEL signal is true. This controls the status
of the LCS WRITE SYNC and LCS WRITE flip-flops, in order to accomplish the writing of data on tape.

LTP8 TAPE WORD — The line counter (LCS) is decoded to generate this signal when every fourth line is encountered on tape. This signifies that a 12-bit word is assembled in the RWB register and is ready for transfer to
the TAC with the next TP4 pulse (LTP8 LD TAC).

7.8.2

Instructions

The following instructions are used in conjunction with the TCI 2-F option:

IOT6152

AC Bit
AC 4(1)
AC 5 (1)

Functions
Clear Block
Set Backward

(continued on next page)

7-28

lOT 6152

AC Bit

Functions

AC 6 (1)
AC 7 (1)
AC 9 (1)
AC 10(1)

Select Unit

Set Forward
Set 8 Motion and Forward if Motion = 0
Sel 8 Tape and

^ Write

SKL 14 = Skip on 8 Block
SKL 17 = Skip on 8 Word
Tape Preset = 0

Write

0 ->• Motion
Deselect 8 Tape

7.9

XY 2 INCREMENTAL PLOTTER CONTROL
1

The XY12 Incremental Plotter Control generates the necessary levels to control the plotters listed
The control logic accepts lOT instructions from the PDP-12 and converts them to specific
that are transmitted to the plotter, producing the desired pen and drum

in Table 7-8.

operational commands

movements. Discrete points may be

plotted, and vertical, horizontal, or diagonal lines may be produced in

any combination by application of the
proper programmed commands. The control is contained on one M704
Double-Width Integrated-Circuit Module
located in the CP mainframe, location MN05. The control logic is compatible
with the CalComp Digital Incremental Plotter Model 563 (30 in.-wide) and Model 565 (12 in.-wide). Each of these
models can be purchased
with the incremental step size of 0.0 0 in., 0.005 in., and 0. 1 0 mm.
1

Table 7-8

XY12 Incremental Plotter Specifications
Name
CalComp

Model

563

Paper Width

Speed

Step Size

(inches)

(step/minute)

(inches)

2,000

.01

.003

.1-mm
565

18,000

.01 -in.

.003-in.

.1-mm

Complot

DP-1-1

18,000

DP- 1-5

18,000

.005-in.

DP-1-M2
DP-l-Ml

18,000

.25-mm
.1-mm

.01 -in.

When the XY12 option, a cable assembly (7005543) is provided which has a W023 Card
Connector at one end,
and a 25-pin Cannon Connector at the other. This cable, which is 0 ft long,
fits either the
2 in. or 30 in. mod1

el.

The PDP-8 CalComp Diagnostic (MainDEC 08-D6CC-D(D) 0) tests any CalComp

Figure 7-13 illustrates the functional relationship between the

mental plotter.

7-29

or Houston Plotter.

PDP-12, the XY12 control logic, and the incre-

PDP-1

t/i9:

(/5

aufi

PEN RIGHT

MB03 THROUGH MB08
lOP PULSES t,2,4

PEN LEFT_

|—

DRUM UP__

|—

XYI2

DIGITAL

CONTROL
LOGIC
1

DRUM DOWN

|—

PEN UP_

(—

INITIALIZE

PEN DOWN

INCREMENTAL
PLOTTER

^
81-0051

Figure 7-13

XY 2 Block Diagram
1

The paragraphs that follow describe the operation of the control logic portion of the plotter as it relates to both
the PDP-1 2 and the mechanism. Maintenance procedures and a description of the plotter mechanism and its operation are provided in the CalComp Digital Incremental Plotter Maintenance Manual and Houston Plotter Manual supplied with the system.

control logic.

The maintenance procedures pertaining to the PDP-1 2 also apply to the XY12

The recommended maintenance procedures for the CalComp Plotters are described in the re-

spective California Computer Products Inc. manuals, and Houston Plotter manuals.

7.9.1

Logic Desaiption

The XY12 control logic interprets a PDP-1 2 instruction in the memory buffer register to generate control
pulses that set the motion control flip-flops. These flip-flops initiate plotter motion by moving the pen up,

down, left, or right and/or moving the drum up or down.

The PDP-1 2 instructions are decoded to initiate plotter functions in the following manner. Memory buffer bits
0 through 2 contain operation code 6g indicating an I/O instruction. The PDP-1 2 Memory Buffer bits 3
,

through 8 contain the device code to select the XY12. Three device codes have been assigned to the plotter control.

These codes (dwg. PCL) and their functions are as follows: 50g (Plotter Flag Up and Pen Up); 5 1 g (Pen

Right and Drum Down); and 52g (Pen Left and Down). Bits 9, 10, and
pulses in the PDP-1 2.

of the instruction generate the lOP

The lOP pulses combine with levels in the XY 2 control logic to generate specific signals
1

that initiate plotter motions.

7.9.2

Logic Operation

The following paragraphs describe the operation of the XY 12 control logic. Logic circuitry for this option appears on engineering drawing D-BS-XY12-0-PCL.

Whenever the computer is turned on, IOC 10 PRESET H is

generated, which in turn generates PCL 10 PRESET L. This signal direct-dears the PLTR ELAG (Plotter Flag)
flip-flop and generates the signal PC L FAST OP DONE (Fast Operate Done) to clear the Pen Right, Pen Left,
Drum Up, and Drum Down motion control flip-flops.

The PC PLTR lOT H and the PCL 50 INST H level are the decoded select levels used in the XY

PLTR lOT H is generated whenever the lOT contains 50g
When active, this level is at +3V.

7-30

5 1g

2 logic.

PCL

or 52g (from memory buffer bits 3 through 8).

The PCL 50 INST H level is generated and active only when the PDP-12 Memory Buffer bits
7 and 8 are cleared.
The inverse of this signal, PCL 50 INST H, is also used, and is generated whenever MB07 or

MB08 is set, e.g., 50o

or 52g address code.

The lOT levels (PCL PLTR lOT H, PCL 50 INST H and PCL 50 INSTH) combine with the

lOP pulse to generate specific control pulses.

The plotter operations are classified as being either fast (Pen Right, Pen Left, Drum Up, Drum
(Pen Up, Pen Down) motion.

Down) or slow
When a fast-motion instruction is executed, the following events occur in sequence.

With any one of the fast-motion control flip-Uops set, plotter motion is initiated and
gered. After this second delay time (5.0 ms total), the Plotter Flag
sets.

the first 2.5 ms delay is trigWhen a slow-motion instruction is per-

formed, the events occur in a manner similar to the fast-motion operation.

The slow-motion (either Pen Up or

Pen Down) flip-flop and the 35 ms delay are triggered; after this delay period,
ated, and the second 35 ms delay is triggered.
flip-flop.

PCL SLOW OP DONE H is generPCL SLOW OP DONE H direct-dears the Pen Up motion-control

This long delay time allows the drum to settle in position and also prevents

erroneous plots.

The Plotter Flag is set by the execution of any plotter-motion instruction. When this
occurs, the INT INT RQST
BUS L activates (OV), and the INT SKIP BUS L gate is partially enabled. INT INT RQST BUS L indicates
to the
PDP-1 2 that the device is requesting service if the Program Interrupt facility
the computer then enters a Search subroutine to determine which

7.9.3

Under program control,

is enabled.

device caused the Interrupt.

XY 12 Instructions

Table 7-9 contains the instruction set for XY12 operations.

Table 7-9

XY 2 Instructions
1

Mnemonic

Octal Code

PLSF

6501

Operation
Skip on Plotter Flag. This instruction decodes to generate

PLTR lOT, 50 INST, and lOPl to check the flag status. If
the flag is set, lO BUS IN SKIP is generated.
PLCF

6502

Clear the Plotter Flag. This instruction decodes to generate

PLTR lOT, 50 INST, and IOP2 to clear the flag.
PLPU

6504

Pen Up. This instruction decodes to generate PCL PLTR
lOT, H PCL 50 INST H, and IOC IOP4 H to raise the plotter pen from the surface of the paper.

PLPU is a slow oper-

ation.

PLPD

6524

Pen Down. After the drum and/or pen are moved, a PLPD
instruction decodes to generate PCL PLTR lOT H, IOC

IOP4 H, and PRD MB07(1) H. This lowers the pen to the
surface of the paper.

PLPR

6511

PLPD is a slow operation.

Pen Right. This instruction decodes to generate PCL PETR

lOT H, IOC lOP F H, and PRE MB08 (
plotter pen one increment to the right.

)

H to move the

It is a fast

operation.

This instruction can be combined with the Drum Up (65 1

or Drum Down (6514) instruction to produce a diagonal
plot.

(continued on next page)

7-31

INDEX (Cont)

D (Cont)

C (Cont)

Indicators, Function, 1-3

DKRS Instruction, 7-5
DKSF Instruction, 7-4

Indicators, Logic, 1-44

DM01 Data Multiplexer, 3-3

Starts, 1-45

DM04 Data Multiplexer, 3-3

Switches, Function, 1-14

Do Not Pause During Execution Fhp-Flop, 6-14

Switch Inputs, 1 -45

DO Switch, 1-16

Timing, 1-14

DP12-A Teletype Interface, 7-2

Console

Core Memory (see Memory)

DPI2-B Asynchronous Modems Interface, 7-2

CPSGNI, 1-18

Drawing Numbers, l-I

CPTTSl, 1-18

DSC Instruction, 1-36, 5-7, 5-9

Cross-Talk Delay, 6-31

Major State, 1-13

DTCF Instruction, 7-5
DTLS Instruction, 7-5
DTPC Instruction, 7-5

DTSF Instruction, 7-5

Current Address

DVI Instruction, 7-10

DW08-A I/O and Data Break Converter, 3-3

D
Data

Break Converter, 3-3

Break Signals, 3-8

EAE Instructions, 7-7

Break Transfers, 3-3, 3-6, 3-8

Eight Mode Instructions, 1-27, 1-30

Field Register, 1-6, 2-8

Enable Extended Address Mode Flip-Flop, 6-13

Internal Flow,

Enable Tape Interrupt Fhp-Flop, 6-13

1-4

Mark, 6-8

End Zones, LINCtape, 6-6

Multiplexer, 3-3

Engineering Drawing Descriptions, 1-44

Datasum, 6-17

EX ADD Format Flip-Flop, 6-27

DCA Instruction, 1-29

EXAM Switch, 1-15

DECtape Option, TC12-F, 7-28
Defer

EXEC 2 Major State, 1-1 3

Execute
Cycle, 1-29

Cycle, 1-27

Major State, 1-13

DF Register, 1-48, 2-14

Extended Address Operation, 6-14

Direction Flip-Flop, 6-29

Extended Arithmetic Element, 7-5

Direct Programs Transfer, 3-2, 3-6

Extended Memory

DIS Instruction, 1-39, 5-7, 5-9

Cables, 1-46

Display

I/O Bus, 1-47

LINCtape Addressing, 6-13

Addressing, 5-10

Control Data Handling, 5-15

Extended Operations Buffer, 6-20

Control, LINC Mode, 5-7, 5-9

Extended Units Flip-Flops, 6-14

Timing, 5-9

External Memory Cables, 3-7

Divide Overflow, 7-11

DKCL Instruction, 7-4
DKRB Instruction, 7-5

Index-2

INDEX (Cent)

F
Fast Sample Instruction, 5-2, 5-4

FETCH

(Cont)

Incremental Plotter Control XY12, 7-29

Index Class Instructions, 1-34

Cycle, 1-27

Inhibit

Major State, 1-13

Current Waveform, 2-1

Field Flip-Flop, 2-1

Drivers, 2-14

FILL STEP Switch, 1-1

Flip-Flop, 2-8, 2-12

FILL Switch, 1-15

Winding, 2-1

Final Mark, 6-8

In Progress Flip-Flop, 6-29

FLO Instruction

Input Channels, KW12-B, -C, 7-26

LINC Mode, 1-42

Input Synchronizers, 7-20

Flow and End Shift Logic, 1-46

Flow Diagrams

Instruction Decoding Logic, 1-46
Instruction Field Register, 1-6, 2-8

Interrupt and Data Break Transfers, 3-5

SAM Instruction, 5-3

Instruction Register, 1-6, 1-15, 1-46
Instructions

Full Address Instructions, 1-34

ADA, 1-35
ADM, 1-35
a Class, 1-38

AND, 1-29
APO, LINC Mode, 1-42

Get Next Instruction: CPS GNI, 1-18

Group Instruction, 6-23

ASR, 7-8

Guard

AZE, LINC Mode, 1-42
BCL, 1-35

Mark, 6-8

BCO, 1-36

Word, 6-8

BSE, 1-35

CAM, 7-7
CDF, 2-8

CIF, 2-8
Half-Select Current, 2-1

CINT, 7-16

H Bit Logic, 1-49
HLT Instruction, 1-31

CLA, 7-7
CLA, 8 Mode, 1-30

Hold Motion Flip-Flop, 6-27

CLL, 1-30

Hold Unit Motion Flip-Flop, 6-1

CLSA, 7-20

CLEN, 7-20
CLLR, 7-19
CMA,l-30
I

CML, 1-30
DCA, 1-29

lAC Instruction, 1-31
I

Bit Flip-Flop, 6-20

DIS, 1-39, 5-7, 5-9
IB Register, 2-8

DKCC, 7-4
DKRB, 7-5
DKRS, 7-5

Idle

State, 6-20

Flip-Flop, 6-26

DKSF, 7-4
IF Register, 1-48, 2-14

DSC, 1-36, 5-7, 5-9

Index-3

INDEX (Cont)

(Cont)

Instructions (Cont)

DICE, 7-5
DIES, 7-5

MUL, 1-37
MUY, 7-9

DTPC, 7-5

NMI, 7-11

DTSF, 7-5

Operate, 1-42

(Cont)

DVI, 7-10

Operate 1 Class, 1-30

EAE, 7-7

Operate 2 Class,

Eight Mode, 1-27, 1-30

OSR, 1-31

Fast Sample, 5-2, 5-4

PLCF, 7-31

FLO, LINC Mode, 1-42

PLDD, 7-32

-3

Full Address, 1-34

PLDU, 7-32

Group, 6-23

PLPD, 7-31

HLT, 1-31

PLPL, 7-32

lAC, 1-31

PLPR, 7-31

Index Class, 1-34

PLPU, 7-31

lOB, 1-42

PLSF, 7-31

lOF, 3-3

PLUD, 7-32

ION, 3-3

QLZ, LINC Mode, 1-42

ISZ, 1-29

RAL, 1-31

IMP, 2-8

KRS, 4-6

RAR, 1-31
RMF, 2-8
ROL, LINC Mode, 1-42
ROR, LINC Mode, 1-41
Rotate, LINC Mode, 1-41

KSF, 4-6

RSW, 1-43

LAM, 1-35
LDA, 1-35

RTL, 1-31

LDF, 1-39

SADC, 7-16

LDH, 1-36

SAE, 1-36

IMS, 1-30, 2-8

KCC, 4-6

KRB, 4-6

RTR, 1-31

SAM, 1-40, 5-1, 5-3

LIF, 1-39

LINC Mode,

SCA, 7-8

1-32

LINC Mode JMP, 1-34
LINC Mode Skip, 1-42, 1-49

SCR, LINC Mode, 1-42

LINC Mode Shift and Rotate, 1-41

SHA, 1-36

LINCtape, 1-44

Shift, LINC Mode, 1-41

Load Group, 7-7

SHL, 7-9

SET, 1-38

LSR, 7-8

SINT, 7-16

LSW, 1-43

SKP, LINC Mode, 1-42

LZE, LINC Mode, 1-42

SMA, 1-31

Miscellaneous LINC Mode, 1-40

SNA, 1-31

MQA, 7-8

SNL, 1-31

MQL, 7-8

SNS, LINC Mode, 1-42

MSC, LINC Mode, 1-40

SPA, 1-31

lndex-4

INDEX (Cont)

(Cont)

Instructions (Cont)

(Cont)

lOB Instructions, 1-42

SPL, 7-14

lOF Instruction, 3-3

SRO, 1-36

ION Instruction, 3-3

STA, 1-35

lOP Generator, 3-2

STH, 1-36

lOP Sample Flip-Flop, 3-8

SUE, 7-16

lOT Transfers, 3-6, 3-8

SXL, LINC Mode, 1-42

lOT Pause Flip-Flop, 3-8

SZA, 1-31

IR Logic, 1-48

SZL, 1-31

ISZ Instruction, 1-29

TAD, 1-29
Tape, 6-28

TCP, 4-6
Teletype, 4-6

TLS, 4-6

IMP Instruction, 2-8
IMS Instruction, 1-30, 2-8

TPC, 4-6
Trap, 1-44

TSF, 4-6

WCG, LINC Mode, 6-24
WRC, LINC Mode, 6-24

KCC Instruction, 4-6

WRI, LINC Mode, 6-24

KEI2 Extended Arithmetic Element, 7-5
KP12 Power Failure and Restart, 7-1

XSK, 1-39
Instruction Setup Timing, LINCtape, 6-21

Interblock Mark, 6-8
Interblock Zones, LINCtape, 6-6, 6-8

Interprocessor Cables, 1-47, 2-1

Interprocessor Signals, 6-28
Interrupt

KRB Instruction, 4-6
KRS Instruction, 4-6
KSF Instruction, 4-6
KT12 Time-Sharing Option, 7-14
KW12-A Real-Time Interface, 7-19
KW12-B, -C Simple Clocks, 7-24

Cycle, 3-6

Delay Flip-Flop, 1-47

Enable Flip-Flop, 1-47
Facility, 3-2
Inhibit, 2-1

Instructions, 1-44

Major State, 1-13
I/O

LAM Instruction, 1-35
LAP-6 DIAL Program, 5-7

LDA Instruction, 1-35
LDF Instruction, 1-39
LDH Instruction, 1-36

Buffer, 1-3, 1-47, 3-9

Leader, LINCtape, 6-6

Bus, 3-1

LIF Instruction, 1-39

Cables, 1-46, 3-7

LINC Mode

Control and Timing, 1-47, 3-8

Fetch Cycle, 1-32

Inputs, 1-46, 3-8

Instructions, 1-32

Output Buffers, 1-47, 3-9

IMP Instruction, 1-34

PRESET Switch, 1-15
STROBE Pulse, 3-9

Skip Instruction, 1-42, 1-49
Shift and Rotate Instructions, 1-41

Index-5

INDEX (Cont)

M (Cont)

L (Cont)

MA Register

LINCtape
Format, 6-4

Decoding, 2-12, 2-1

Instructions, 1-44

Logic, 1-48

Instruction Setup Timing, 6-21

Operation, 2-4

Instruction Register and I Bit, 6-20

Mark

Non-Standard, 6-7

Condition, 6-13

Flip-Flop, 6-13, 6-27

Search Timing, 6-22

Timing, 6-25

LINCtape Control System

Track Code, 6-7

Window Register, 6-26

Block Diagram Discussion, 6-1
Block Schematic Discussion, 6-26

MB Register Logic, 1-48

Extended Operations, 6-12

MCI 2 Memory Extension Control, 2-8

General Description, 6-1

MEM Enable Flip-Flop, 2-1
MEM EXTN

Major Register Description, 6-17
Major States, 6-20

AC Inputs,

-47

Read/Write, Basic Discussion, 6-14

Buffer, 2-13

Specifications, 6-3

Field, 2-14

System Drawing Discussion, 6-20

Registers, 2-1

Timing Diagram Discussions, 6-21

Memory
Addressing, 2-4

Link
Bit, 1-4

Address Register, 1-6

Logic, 1-46

Block Schematics, 2-1

Load

Buffer, 1-6, 3-5

Control Gates, 1-49

Control, 1-3, 2-1

Group Instructions, 7-7

Extension Control, 2-8

Pulse, 6-1

External Cables, 3-7

LSR Instruction, 7-8
LSW Instruction, 1-43

Field Selection, 2-10

LTP8

Physical Description, 2-1

Increment, 3-5

Write Flip-Flop, 7-28

MEM PAGE EXTN Control Logic, 1-47
MEM Register Logic, 1-48, 2-4

Tape Flip-Flop, 7-28

Tape Word, 7-28

MFTPO, 1-14

LTS Time Write. 6-25

MFTPl, 1-14

LZE Instruction, LINC Mode, 1-42

MFTP2, 1-14
MFTSO, 1-14
MFTS2, 1-14

M
Maintenance Mode Flip-Flop, 6-13
Major Registers, 1-4

Major States
Description, 1-9

LINCtape Control System, 6-20
Logic, 1-44

Miscellaneous LINC Mode Instructions, 1-40

Mode Flip-Flop Logic, 1-44
Mode Status Register, 1-6
Motion Delay Pulses, 6-22

MQA Instruction, 7-8
MQL Instruction, 7-8
MQ Register, 1-47, 7-6

Index-6

INDEX (Cont)

M (Cont)

P (Cont)

MSC Instructions, LINC Mode, 1-40

PLPU Instruction, 7-31

MUL Instruction, 1-37
MUL Quotient Logic, 1-47

PLSF Instruction, 7-31

Multiplier Quotient Register, 7-6

MUY Instruction, 7-9

PLUD Instruction, 7-32
Power Failure and Restart Option, 7-1
Processor Register Bus, 1-3

Program Controlled Transfers, 3-1
Program Counter, 1-4, 1-48, 3-3

N
NMI Instruction, 7-1
No Pause Flip-Flop, 6-27

Program Interrupt, 3-1
Program Interrupt Transfer, 3-3, 3-6
Progress Flip-Flop, 6-29

PRR Switch, 5-10

O
Operate 1 Class Instructions, 1-30
Operate 2 Class Instructions, 1-31

Q
QLZ Instruction, LINC Mode, 1-42

Operate Instructions, 1-42

Options

AG 12, 7-1

AM 12, 7-1
DP 12 A, 7-2

RAL Instruction, 1-31
RAR Instruction, 1-31

DP12B, 7-2

Read

KE12, 7-5

Amplifier, LINCtape, 6-14

KP12, 7-11

Flip-Flop, 2-8, 2-12

KT12, 7-14

Operation, 2-7

KW12-A, 7-19

Read/Write

KW12-B, -C, 7-24

Buffer, LINCtape, 6-4, 6-12, 6-18, 6-32

TC12-F, 7-28

Circuits for Tape, 6-31

XY12, 7-29

Cycle, 1-18

OSR Instruction, 1-3

Logic, 6-14

Operation, 2-1

Winding, Resistance, 2-13

Real-Time Interface KW12-A, 7-19

Page Addressing, 2-5

PC Register, 1-4, 1-48, 3-3

Regsiter Control, 1-48

Phase, 6-26

Registers

PLCF Instruction, 7-31

AC, 1-4, 1-48

PLDD Instruction, 7-32
PLDU Instruction, 7-32

Active, 1-3

Plotters, 7-29

Data Field, 1-6. 2-8

PLPD Instruction, 7-31
PLPL Instruction, 7-32
PLPR Instruction, 7-31

DF, 1-48, 2-14

BF, 2-10, 2-14

IB, 2-8
IF, 1-48, 2-14

Index-7

INDEX (Cont)

S (Cont)

R (Cont)

SCR Instruction, LINC Mode, 1-42

Registers (Cont)
Instruction, 1-6, 1-15, 1-46

Search
Flip-Flop, 6-26

Field Register, 1-6, 2-8

Major, 1-4

State, 6-20

MA, 1-48, 2-4, 2-12, 2-13

Timing, 6-22
Sense

MB, 1-48

MEM, 1-48, 2-4

Amplifiers, 2-4, 2-1

MEM EXTN, 2-14

Line Control, LINC Mode, 5-4

Memory Address, 1-6

Winding, 2-1, 2-4

Mode Status, 1-6

MQ, Multiplier Quotient, 1-47, 7-6

SET Instruction, 1-38

MUY, 7-9

SF Register, 2-10

PC, 1-4, 1-48, 3-3

SHD Instruction, 1-36

SC, Step Counter, 7-7

Shift Instructions, LINC Mode, 1-41

Sense, 2-4

Shift Logic, 1-49

SF, 2-10

SHL Instruction, 7-9

Tape Accumulator, 6-17

Simple Clock KW12-B, -C, 7-24

Tape Block Number, 6-18

Single-Cycle Data Break, 3-4, 3-6

Tape Buffer, 6-17

SINT Instruction, 7-16

Tape Memory Address, 6-18

Skip Flip-Flop Control Logic, 1-49

Tape Register Control, 6-29, 6-30

SKP Instruction, LINC Mode, 1-42

TMA Setup, 6-20

SMA Instruction, 1-31
SNA Instruction, 1-31

TTO, 4-4
Relay Buffer, 1-47, 5-5

SNL Instruction, 1-31

Relay Control, LINC Mode, 5-5

SNS Instruction, LINC Mode, 1-42

Reverse Block Mark, 6-8

SPA Instruction, 1-31

RMF Instruction, 2-8
ROL Instruction, LINC Mode, 1-42
ROR Instruction, LINC Mode, 1-41

Speaker, 5-1

Rotate Instructions, LINC Mode, 1-41

SRO Instruction, 1-36

RSW Instruction, 1-43
RTL Instruction, 1-31
RTR Instruction, 1-31

STA Instruction, 1-35

Run Flip-Flop Logic, 1-44

Special Level Signals, Logic, 1-49

SPL Instruction, 7-14

START 20 Switch, 1-1 6
START 400 Switch, 1-16
START LS Switch, 1-16
Step Counter Register, 7-7

STEP EXAM Switch, 1-16
S

SADC Instruction, 7-16
SAE Instruction, 1-36
SAM Instruction, 1-40, 5-1, 5-3
Sample and Hold Circuit, 5-1

SCA Instruction, 7-8

STH Instruction, 1-36
SUF Instruction, 7-16

SXL Instruction, LINC Mode, 1-42
SYNC Generator, KW12-A, 7-24
SZA Instruction, 1-31
SZL Instruction, 1-3

SC Register, 7-7

Index-8

INDEX (Cont)

TAD Instruction, 1-29
Tape

T (Cont)
Time State 1: CPT TSl, 1-18
Timing Cycle, 1-7

Accumulator Register, 6-17

TLS Instruction, 4-6

Block Number Register, 6-18

TMA Setup Register, 6-20

Break Major State, 1-13

TN, 1-15

Break Request, 6-28
Buffer Register, 6-17

TPC Instruction, 4-6
TP5D Pulse, 1-7

Bus Gating Network, 6-20

Trailer, LINCtape, 6-6

Control, LINC Mode, 5-1

Transfersum, 6-17

Control States, 6-26

Transport Control, 6-30

Delays, 6-30

Trap Instructions, 1-44

Direction and Motion Control, 6-29

T5 Recycle Flip-Flop, 1-17

Extended Operations, 6-27

TSF Instruction, 4-6

Fail, 6-31

TSS

Fail Delay, 6-3

Interrupt, 7-19

Group Counter, 6-28

Monitor Program, 7-1

Instructions, 6-28

Save User Flag, 7-

Interrupt, 6-29

Skip, 7-19

Maintenance Signals, 6-31

Time-Sharing System, 7-14

Mark Window, 6-33

User Buffer, 7-18

Memory Address Register, 6-18

User Flag, 7-18

Pause, 6-28

TTO Register, 4-4

Read/Write Circuits, 6-31

TU55/TU56 Transports, 5-1

Turn Around

State, 6-21

States, 6-32

Flip-Flop, 6-26

Time Pulses, 6-33
Timing OK Delay, 6-30

TAPE INT EN Flip-Flop, 6-27

Tape Word Flip-Flop, 6-29

TCI 2-F 8 Tape Control, 7-28

User Interrupt (UINT), 7-19

TCF Instruction, 4-6
Teletype

Control, 4-1
Receiver, 4-1

VC-12 LINCscope Control, 5-7

Transmitter, 4-2

VR12 Point-Plot Display, 5-7, 5-10

Read Cycle, 4-2
Print/Punch Cycle, 4-4

Instructions, 4-6

Three-Cycle Data Break, 3-5, 3-7

WCG Instruction, LINC Mode, 6-24

Time Pulses, 1-7, 1-45

WIDTH Switch, 5-10

Time-Sharing Option, 7-14

Window Register

Time States, 1-7, 1-45

Tape Mark, 6-33

TCI 2-F, 7-28
Index-9

INDEX (Cont)

W (Cont)
Word Count
Cycle, 3-7

Major State, 1-13
Overflow, 3-5

Word Count Overflow Flip-flop, 3-9

WRC Instruction, LINC Mode, 6-24
WRI Instruction, LINC Mode, 6-24
Write
Amplifier, LINCtape, 6-15

Cycle Flip-Flop, 6-27
Flip-Flop, 2-8

Operation, 2-7

Sync Flip-Flop, 6-26

X
XSK Instruction, 1-39
X-Axis Selection, 2-12, 2-14

X Winding, 2-1, 2-12
XY12 Incremental Plotter Control, 7-29

Y
Y-Axis Selection, 2-13, 2-14

Y Winding, 2-1

Index- 10

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PDP-I2 Maintenance Manual, Volume I
DEC-1 2-HRlA-D

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