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DEC-08-I8AA-D

December 1970

39 pages

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Document:	DM01
Order Number:	DEC-08-I8AA-D
Revision:
Pages:	39
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OCR Text

Digital Equipment Corporation
Maynard, Massachusetts

PDP-8
Maintenance Manual

DMO1
Data

Multiplexer

Eiflfifllall

UmnuomIHm>>IU

2:5
02::
05> zcrjnrmxmm
_<_>_zamz>zo_m _<_>zc>_.

052.2.

mDCiZmza

003302352

Z><Z>mp §>mm>OIcmmHHm

lst Printing September 1967
2nd Printing September 1968
3rd Printing May 1969

4th Printing January 1970

1967, 1968, 1969, 1970 by Digital Equipment Corporation

The material in this manual is for information purposes and is subiect to change without notice.

The following are trademarks of Digital
Corporation, Maynard, Massachusetts:
DEC

Equipment

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONTENTS

Chapter

Page

INTRODUCTION..........................

SCOPE..

OPERATION

.....

...........

......

.....

.......

...................

3.1

General

3.2

Logic Operation

............................

...............

.....

.......

............................

......

.2-1

.....

l-l

3-1

......3-i

.......

3-1

3-l

3.2.]

Multiplexer Control (BS-D-DMOl-O-Z).

3.2.2

Level Production from Multiplexer Control (BS-D-DMOl-O-ll)

.....

3-3

3.2.3

Data Address Line Selector (BS-D-DMOl-0-4)

3.2.4

Data Bits Line Selector (BS-D-DMOl-0-3)

INTERFACE......
5

................

............

.....

3-4

.................

4-]

Corrective Maintenance

6-]

.........................................

6-]

Mounting

7.2

Environmental Conditions

7.3

Power Requirements

..........

.............

..........

..................

.............

........

.........

7.1

SCHEMAT'ICS

......

Power Supply Checks

INSTALLATION

8.1

...................................................

Preventive Maintenance

6.1.1

6.2

POWER SLJF’PLY 5-1
MAINTENANCE

6.1

.......

...........

.....

........7-l

.............................................

...........

6-]

7-1

....................

7-l

...................

.....................

7-l

..............

............

Semiconductor Substitution

...........

8-]

.................

......

........

......

8-1

.......

6-]

.....

8—1

TABLES

Table
6-]

Type 728 Power Supply Output Checks (Drawing CS-B-728).
Semiconductor Substitution

.......

......

............

ILLUSTRATIONS

Figure
1-]

DMOl General Block Diagram......

......

........

DMOl Data Break Signals
3-2

PDP-8

DMOl Timing Diagram

.......

l-l
3-2
3-3

CON TE NTS

(continued)
Page

Figure
Power Supply (CS-B-728)

................

............................

8'2

8-2

Diode Gate (CS-B-Bl4l)

.............................................

8-2

8-3

Diode Cluster (RS-B-ROOZ)

8-4

Dual Flip-Flop (RS-B-R202)

8-5

Invefler(CS-B-Sl07)

8-6

Diode Gate (CS-B-Slll)

8-7

DC Carry Chain (RS-B-Sl8l)

8—8

Dual Flip-Flop (CS-B-SZOZ)

8-9

Clamped Loads (CS—B-W005)

8—10

Signal Cable Connector (RS-B-W02l)

8-11

Pulse Amplifier (CS-B-W640)

8-12

Utilization Module List (UML-D-DMOl-O-S)

8-13

Multiplexer Control (BS-D-DMOl-O-Z)

8—14

Level Production from Multiplexer Control (BS-D-DMOl-O—ll)

8-15

Data Address Line Selector (BS-D-DMOl-0-4)

8-16

Data Bits Line Selector

8-17

DMOl Interconnecting Cable Diagram (IC-DMOl-O-l3)

8—18

I/O Connectors (BS-D-DMOl—O-o)

8-19

Data Multiplexer Connectors (BS-D-DMOl-O-5)

.....................

8-3

...........................................

8-3

.................................................

8—4

.............................................

8—4

..........................................

8-5

...........................................

8-5

..........................................

..................................

..........................................

............................

.................................

8—6

8—6
8—7
8-9
8-H

.............

8-l3

.........................

8-15

(BS-D-DMOi-O—3)..............................; 8—17
...................

.....................................

..........................

8—19
8-21
8—23

CHAPTER]
INTRODUCTION

This manual covers the maintenance of the data multiplexer, designated as Type DMOl ,
in production at the Digital

now

Equipment Corporation of Maynard, Massachusetts.

The DMOl is essentially a switching device for use between the PDP—8®and a maximum of
seven

peripheral or I/O devices, as shown in figure 1-]

The.peripheral devices include high-speed

magnetic tape systems, high-speed drum memories, and CRT display systems containing memory elements,
all of which use the PDP-8 data break Facility.

MAXIMUM
or
SEVEN
PERIPHERAL
DEVICES

PDP‘B

DiviOi
DATA
MULTIPLEXER

rlgure

l-l

UMUI

ueneral

BIOCK Ungl‘Gm

® PDP isfie registered trademark of the Programmed Data Processor manufactured by Digital Equipment

Corporation of Maynard, Massachusetts.

l-l

CHAPTERZ
SCOPE

TIA:1-

Type DMOl

It details information on logical operation, interface characteristics and connections, and

installation and mounting

Uses of the levels and pulses

covered in this manual.

produced by the peripheral devices and the PDP-8

are

not

For further information on such signals, reference to the PDP-8 User's Handbook

F-85 and instruction manuals of the specific peripheral devices is advised

2-1

CHAPTER3
OPERATION

3 .l

GENERAL

The Data Multiplexer Type DMOl,

noted, acts as a switch between the PDP-8 and a

maximum of seven high-speed peripheral devices which use the data break facility.

Whenever a device using the data break facility requests a break, the device produces a
number of signals.

As figure 3—]

shows, only the signals from the selected peripheral device pass through

the DMOl into the PDP-8.

LOGIC OPERATION

3 .2

The following paragraphs describe the logic operation of the DMOl Data Multiplexer as it relates to the PDP-8 and the peripheral devices connected to it.
to an engineering

(Each maior heading references directly

drawing found in chapter 8 of this manual.)

Multiplexer Control (BS-D-DMOl-O—Z)

3.2.l

Figure 8-13 illustrates the logic control circuitry of the DMOl

Data MultipleXer.

Upon receipt

of PDP-8 timing pulses and a BRK REQ (break request) level from the peripheral device requesting the
data break, this control

accepted) pulse

logic produces MPX, B ENABLE, and BRK REQ levels and ADD ACC (address

For ease in explanation, it is assumed the peripheral device producing the BRK REQ l level
is requesting service.

Similar operations occur when other peripheral devices request data breaks.

The timing diagram in figure 3-2 is used in coniunction with the multiplexer control descrip=
tion

During the PDP-8 turn-ion period, or whenever the operator presses the START key, POWER
CLEAR pulses (=3v, lOO-nsec pulses at a lO-kHz rate) clear the BREAK IN PROGRESS (figure 8-4), and

the B ENABLE, and MPX flip-flops (figure 8-8).

These pulses are accepted, and their function imple—

mented, without the need for device selection through addressing.
All BRK REQ levels enter the DMOl
322 and SI ll diode gate (figure 8-6) at 823.

drawing

through the R002 diode network (figure 8-3) 'at location
This circuitry is shown in the upper right corner of the

The ground BRK REQ l level is applied to terminal L of the above modules.

input terminals are at —3v

The remaining

f
——

—-

——

-—

——

—

DAO—O THROUGH DAM-O ——————-<>
DAD-I

THROUGH DAI1—1 H

BAG —2 THROUGH DAN-2 —<>

‘

ADDRESSING

BAG —3 THROUGH DA11—3 —<>

LINE

BAG -4 THROUGH BAH—4 ——<>

SELECTOR

OAO

OAO THROUGH DAII ————————¢

————————

5 THROUGH mm —5 ————-<>

—

DAG -6 THROUGH DAIt—G —-———<>

ADDRESS SELECTION
T

LINES

CYC SEL-O

SEL

THROUGH

-————-——

CYC SEL

CYL SEL —-—-.
II

DAEX
—-

MPX

3-0
THROUGH

DAEX

3 —.

DAEX 3—6

LINES
DAEX 2-0
DAEX 2 ——'—.

THROUGH
DAEX 2- 6

DAEX I-O
DAEX 1 —-—-—.

THROUGH
DAEX 1-6

B X

MPX 0

THROUGH
B <)(- MPX 6
SEL

PERIPHERAL
i
DEVICES

> Pop 8
_

B ENABLE O
THROUGH ———O
B ENABLE s
BREAK REQUEST o
¥-—————- BREAK

——-——<>

THROUGH

——

BREAK REQUEST 6

—————

BREAK REOUEST —-—-—-—O

MULTIPLEXER

CONTROL
_

ADD ACC-O
+——'~——

THROUGH

"——‘

ADDRESS

ACCEPTED

POWER CLEAR

—"""-———

ADD ACC-G

WCOV

I
B ENABLE O
THROUGH 6

WCOV— 0
*—-—-—— THROUGH
WCOV
6
-

SEL

DATA -OUT

THROUGH
—<)I
DATA -0UT- 6

——

SEL

DA SEL DEV

THROUGH
DA SEL DEV-6

SEL

"T’Hca‘ln'féfl

+1» CA INH
—

”——

—

——

—

‘

DA TAIN —.

T
—.l
SEL

+'
—_

-—-—-

—

+1—.CA INH —9

°
6

OBO -0 THROUGH OBn-o ————<>

030 —l THROUGH Dan-1 —O
DBO

—

2 THROUGH

0811—2 ~—————-—-<>

030—3 THROUGH Dan—3 ———<>
D80 —4 THROUGH Dan—4 —————-<>

DATA
LINE

-————

OBO THROUGH 0811

SELECTOR

¢
,

080- 5 THROUGH 0811—5 ——<>
DaO-s THROUGH OBn-s —<>

Figure 3—l

DMOI Data Break Signals

The -3v output of the SI II diode gate is inverted by the Sl07 module (figure 8-5) at
location B32.

The resulting BRK REQUEST ground level goes to the PDP-8 major state generator to

signal the computer that a data transfer is to take place

BRK REQ l is also applied to terminal E of the W005 clamped load (figure 8-9) at location B9
and shown across the middle of the drawing

terminal of the MPX—I

The level enables the DCD gate associated with the set

flip-flop. The corresponding gate of the remaining MPX flip-flops is inhibited.

A PDP-8 T1

timing pulse sets the MPX-1 flip—flop, enabling the DCD gate connected to the

of the B ENABLE 1

set terminal

terminal F of the S181

flip-flop. The ground level from the 1 side of the MPX-1 is applied to

clc carry chain

(figure 8-7) at B12 and shown across the lower portion on the

drawing. Through this operation, all MP“ flips—flops that are less significant (to the rig..t of) tnan
MPX-1

Because of this Function, the peripheral device producing BRK REQ 1

held in the 0 state.

are

is given priority over the less significant peripherals.

MEM
DONE
ADD
ACC.

Figure 3—2
A -3v level is-

the drawing

present

PDP—8

at K of the

MEMSTART
T1

1’2

—

DM01 Timing Diagram

S111 module at B30 and also shown across the lower part of

When an ADDRESS ACCEPTED pulse arrives from the PDP-8, B ENABLE 1 is set and a -3v
1

ADD ACC-1

pulse is generated

The levels and pulses produced by multiplexer control are used by other circuits of the DM01,
as

covered in the following sections.

Level Production from Multiplexer Control (BS-D—DM01-0-11)

3.2.2

The logic circuitry of figure 8-14 uses the output levels of the MPX and B ENABLE flip-flops
to

produce levels and pulses for use by both the DMO1 and the peripheral devices.
The logic element on the left side of the drawing consists of seven, 2-input, diode gate-

inverter-clamped load networks. The $111 diode gates at locations 36, B8, and 323 have paired inputs
which form AND gates.

One terminal of each gate is common, and is at —3v whenever a break is in

progress.

Proceeding with the example, a -3v level from the set B ENABLE 1 flip-flop provides the
level necessary to give the desired -3v B

MPX 1 level from the W005 clamped load at B9.

The gated driver, made up of the $111 diode gates at A16, A17, and A18 and the W640

pulse converters (figure 8-11) at B29, A14, and A15 produce a -3v WCOV (word count overflow) pulse
when suitable inputs are present.

Because 0 -3V B ENABLE level is present,

produced when 0 -3V WCOV pulse arrives. The B
device 1

MPX 1 level and WCOV-1

3-3

-3v WCOV-1

pulse is

pulse go to peripheral

The two paralleled inverters on the right side of the drawing produce levels that are used by
DMOl selector networks.

A -3v DB SEL DEV T

level, which is used by the selector networks shown in

Figure 8-16 and discussed in section 3.2.4, is generated by applying a ground level from the B ENABLE l

flip—flop to terminal H of the Sl07 diode gate CIT Al2. The output is at terminal F at B4.
DA SBL DEV l is used by the logic circuitry of figures 8—l5 and 8-l6, and is explained in
section 3.2.3.

The level is produced by inverting the MPX—l ground level present at terminal H of the

Sl07 inverter at B5.

The output is present at F, location Al3.

Data Address Line Selector (BS—D-DMOl-0-4)

3.2.3

The circuitry shown across the top of figure 8-15 serves to permit the l2-bit address from the

peripheral device requesting the break to enter the PDP—8 memory address register.
through a logical AND operation

This is accomplished

The terminals labeled E, H, K, M, P, S, and U of the Bl 4l Module (figure 8-2) at location
Cl receive the levels designated DA SEL DEV 0 through

DA SEL DEV 6,

respectively. The most signi-

ficant data address bit from the peripheral devices is applied to terminals F, J, L, N, R, T, and V of

module Cl; the least significant is applied to module Cl2.

Continuing with the example, a -3v DA SEL DEV l level, applied to terminal H, provides
one

level needed by the AND gate.

The data address bits, designated DAO—l through DAll-l ,

applied to the remaining terminal of the gate

are

The output levels, DAG through DAl l , which go to the PDP-8 memory address register, appear
at the

SlO7 inverter output at locations B7 and Bl5

The logic circuitry across the lower part of the drawing functions in a similar manner.
DA SEL DEV 1 enables the same terminal of each Bl 41 Module.
A CYC SEL-l level from peripheral device 1 is logically ANDed with DA SEL DEV l in the
diode gate at Cl3.

The output CYC SEL level, available at terminal R of the inverter at Bl5, goes to

the PDP-8 major state generator.

The Bl4l diode gates at locations Cl4, C15, and Cl6 permit the extended memory address
bits from peripheral device l to enter the PDP—S.
DAEX 3,

3.2.4

are

The output levels, designated DAEX l, DAEX 2, and

available at the Sl07 inverter terminals F and D at B25 and T at 315,

respectively.

Data Bits Line Selector (BS-D-DMOl-0-3)
Data bits from the selected peripheral device reach the PDP-8 memory buffer register through

the logic circuitry, made up of the Bl 4l diode gates at locations Cl7 through C28, and illustrated
across

the top of figure 8-l6.

This circuitry operates in the same manner as that used for data addressing; namely,
DB SEL DEV I

provides one level required by the gate string, and the data bits From peripheral device I,

designated DBO—I thrOUgh DBlI-I, previde the remaining levels.
The l2-bit output, comprised of the bits labeled D30 through DBll,

are

found at the Sl07

inverter outputs at locations 325 and B26.
An INCREMENT CA INHIBIT (+1 —> CA INH) level, which is used during 3-cycle breaks,
is produced by ANDing the DB SEL DEV I and +I -—>CA INH levels.

Similarly, G DATA IN level, which specifies the data transfer direction, is produced by
ANDing DA SEL DEV I with DATA OUT.
These two levels are terminated at pins N and R,
location B32

respectively, of the Sl07 diode gate at

CHAPTER4
INTERFACE

All interface connections to the DMOl
the back of the multiplexer.

are

made at assigned module receptacle connectors at

Theinterfacing between the PDP-8, DMOl, and the peripheral devices

is shown in the following figures:

Figure 8-17

DMOl Interconnecting Cable Diagram (IC-DMOl-O—l3)

Figure 8-l8

I/O Connectors (BS-D-DMOl-O-é)

Figure 8-19

Data Multiplexer Connectors

4-1

(BS-D-DMOl-O-5)

CHAPTERS
POWER

SUPPLY

ADEC Type 728 Power Supply (table 8—1) generates the voltage levels (+10 and -l5 vdc)

required for operation of the multiplexer.

Chapter 8 contains the schematic of this power supply and chapter 6, the output check data.
The DEC System Modules Catalog (C-lOO) provides detailed information on the operational characteristics of the supply

5-1

CHAPTER6

MAINTENANCE

6.1

PREVENTIVE MAINTENANCE

The general preventive maintenance procedures provided in the PDP—8 Maintenance Manual

(F-87) apply to the multiplexer control logic
6.1 .l

Power Supply Checks

Table 6-] shows the output voltage checks needed for the Type 728 Power Supply used in
this equipment.

Per terr‘l

‘L

power supp l"
y checks described in table 6-.
“"

Use a multimeter to make the

output voltage measurements with the normal load connected, and an oscilloscope to measure the peak-

to—peak ripple content on all dc outputs of the supply. The +’I0v and -I5v supplies are not adiustable;
therefore, if any output voltage or ripple content is not within specifications, consider the power supply
defective and initiate troubleshooting procedures.
TABLE 6—I

TYPE 728 POWER SUPPLY OUTPUT CHECKS

(Drawing CS-B-728)

fifgiiizrifsi

Power Supply
Output

Red (+) to

Acceptable

Nominal

Output
(vdc)

Output
Range (v)

Maximum

Output

Peak-to-Peak

Current (a)

Output Ripple (v)

+10

+9.5 to +1] .0

0.7

—l5v

-I4.5 to 46.0

0.7

Yellow (—)
Yellow (+) to
Blue (-)

6.2

CORRECTIVE MAINTENANCE

The simplicity of the system and the logic description provided in this document permit the use
of standard troubleshooting techniques for isolating the trouble quickly and efficiently.
maintenance under most conditions,

For economical

replace the inoperative module with one from spares and return the

defective module to DEC for repair or replacement.

CHAPTER7
INSTALLATION

MOUNTING

7.1

The DMOl Data Multiplexer is 10-1/2 inchesflhigh, and is designed for mounting in a standard

l9-inch-wide rack

ENVIRONMENTAL CONDITIONS

7.2

No special environmental conditions are required for proper operation of the DMD]
O

remperarure may vary between 32° and 1130'
.

7.3

(“O and 55° C).

POWER REQUIREMENTS

The DMOl obtains its primary power From a Type 728 Power Supply.

Ambient

CHAPTER8
SCHEMATICS

The following pages contain schematics oF all modules used in the DMOl Data Multiplexer.
8.1

SEMICONDUCTOR SUBSTITUTION
Standard EIA components specified in table 8-]

can

replace the majority of DEC semicon-

dustors used in modules of the data multiplexer and shown in the schematic section of this publication.

Exact replacement is recommended For semiconductors not listed.

TABLE 8-]

SEMICONDUCTOR SUBSTITUTION

DEC

EIA

D662

1 N645

D664

1 N3606

DEC 3009A

2N3009

2N3605

same

DEC3639

2N 3639

DEC3639—l

2N3639

TI
DEC
T-4I5I3

RED
-

cmcII JONES
NOJOI
TERMINAL STRIP

4L
-

HOV

RED

«0.000 MFD

15.595

zovoc

25w

YEL

0v
YEL
"5V

+1_
-

I60.00° “FD
20 VDC

B LU
.

ILUE

-|5V

NOTE:
IN ORDER To KEEP OUTPUT VOLTAeE wITHIN
THE FOLLOWING LIMITS:

+Iov: +9.5 TO +uv
-I5V: -I4.s TO -Iev
THE LOAD|NG sIIOULO BE wITIIIN THE FOLLOWING LINITs:
BOTH SIDES
LOADED

+IOV 0 T0
T|5V |.O T0

7.0 AMPS
8.0 AMPS

ONE SIDE
LOADED

NOV 0 T0
-I5V LO T0

7.5 ANPS
8.5 AMPS

sun or TNE OUTPUT

THE EQUATION:
Iv

CURRENTS ARE LIMITED BY

51Io +615 553

HEYHAN MFG. CO. TAB TERMINALS

Power Supply (CS-B-728)

Figure 8—1

A
A

% + IOV

“30,000

IO0,000

[DIS
D662
DI5

E 0662

l
DIS
p

DI3

09
L

DI7

025

RII

7,500

7.500

7,500

RI3

7,500
a

UNLESS OTHERWISE
RESISTORS
DIODES

ARE

INDICATED:

I/4W',5°/a

ARE D664

TRANSISTORS ARE DEC 36394

Figure 8—2

Diode Gate (CS-B-BI4I)

8-2

%—I5v

DIO
.4

0664

#fiOF
05

EQ”*

45%
0664
09

HC}’

0664

40K
04
J
0664
DB
LJ
'1

LO:

0664

40N
03

“C>

0664
07

PC%7

0664

£5
02

RC
0664
06

TC
0664

40V
0

U0;
0664

Figure 8-3

Diode Cluster (RS-B-ROOZ)

+IOV
R4

IOQOOO
'Ql

6ND
D42
0-682

D4i

D-662

D40
D-662

036

Figure 8-4

RIZ

R15

Rl9

R20

l5,000

15,000

4,700

[5000

IiOOO

Dual Flip-Flop (RS-B-R202)

8—3

C5
.Ol
MFD

039
D-GGZ

I- EXAMPLE
DGL5

Ens

I00.ooo

§R5

I00.000

I00,000

‘

gRs

I00.000

II‘
I

ER?
I-

00—4

NO—<

LO—1
03

0I2

DI3
D-662

D-662

RIO

3.000

RII

3,000

06:

RI2

0-662

3,000

3.000

3,000

020
0-662

Ispoo

02I
0-662

l5,000

RIS

022
0-662

I5.Doo

R20

023
0-662

|5,000

E
UNLESS

OTHERWISE

RESISTMS
DIODES ARE

027

ARE

029

028

DID

0-662'

I
‘

RI5

.00:
2|

:STRATE

I5.ooo

I.5oo

I
I

DII

‘

R2I

0662‘

-662

D-662I

026

"am-"I

RIT

0-662I

CC GND

‘

one
0-662

I
07

RI3

I
08

DI6

-__CI

I
I

%\.0I I
”Fm

I
v

DI5
D-

ITO—1

0I4
0-662

Ro—4

------

I ‘2

I
I
I
I

III

Fo—I

-----

‘

I
I

I' IIoo,ooo
I I

I00,000

fi’MuovI/A)

I
I

IJQB-Isv

—3v

I
I

______

030

INDICATED:

I/4wisx

D-664

TRANSISTORS ARE

DEC 3639

PRINTED CIRCUIT REV. FOR
DGL

BOARD IS SIA

figure 8-5

InverIer (CS-B-SIO7)

QAIIIOVIA)
r“-_—"II
-

I00,ooo

Ioopoo

'
I
DI9

I
I
I

I
I

DID

I
OH

0?
0-664
K

OP
R

06
0-664
I

043“

o—fl—«b—ON

I5.000

3,000

I5,ooo

3,000

EXAMPLE DGL5
-----------

ARE

“

I
I

.500

I
I
.

—3v

'STRATE

L__-__.J

DEC 3639

I/4W;l0%

D—662

PRINTED CIRCUIT REV. FOR

BOARD IS

INDICATED:

OTHERWISE

TRANSISTORS

DGL

I
I

DIODES

DIG

F—OT

I
I

I
m5
0-664

RESISTORS

DI?

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