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DEC-08-I6AA-D

December 1967

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Document:	34D Oscilloscope Display Control
Order Number:	DEC-08-I6AA-D
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Pages:	25
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DEC-O8— IOAA— D

OSCILLOSCOPE

DISPLAY

CONTROL

340

INSTRUCTION MANUAL

NOVEMBER I967

DIGITAL EOUIPMENT

CORPORATION O‘MAYNARO. MASSACHUSETTS

This manual contains proprietary information.

It is provided to the

of Digital Equipment Corporation
help them properly
the
contents to any
equipment. Revealing
or
for
other
is
organization
person
prohibited.
any
purpose

customers
'use

and maintain DEC

CONTENTS

INTRODUCTION

SCOPE

.........................................

...............................................
‘

OPERATION

...........................

...............

Program Instructions

Logic Operation

....................................

..............

.2.l

Processor Turn-On

.2.2

Coordinate Channels

.2.3

Intensity Circuits

.2.4

Light Pen Operation
INTERFACE

.......

........................

...................................

.................................

., ......

...................

..................................

......................................
g

POWER SUPPLY

MAINTENANCE

..........................................

.........................................

l
l .l

Preventive Maintenance

..................................

Power Supply Checks

Oscilloscope Maintenance
INSTALLATION

.................................

..........................................

Cabinet and Desk Top Configuration

Environmental and Power Requirements
ENGINEERING DRAWINGS

.........................

........................

.................................

ILLUSTRATIONS

Figure
4-]

PDP-8 to 34 D Control Interface,

Control Signals
4-2

X/Y Address, Data and Function

............

oooooooooooooooooooooooooooo

PDP-8 to 34 D Control Interface, X and Y Coordinate Address and

Brightness and Light Pen Address

oooooooooooooooooooooooooooo

PDP-8/S to 34D Control Logic Interface

..........................

4—4

PDP—8/S to 34D Control Logic Interface

......................

4-5

PDP—8/S Control Interface, Brightness, Light Pen, and X and Y
Coordinate Control Address

oooooooooooooooooooooooooooo

TABLES
I

Table

Page

3-]

Control Instructions

.3-2

Coordinate-Channel Logic Conversion Table

6-]

.......

................................

.......

......

........

.........................

......

DRAWINGS

Display (Sheetl)...........1.......'.'.....V...I.

BS-D—34D-O-2

Display (Sheet 2)

UML-D-34D—0-3

Utilization Module List

WD-D-34D-O—4

PDP-8 Options BOA-BOD

B-CS-A601-O—i

3 Bit

B-CS-A704-O—l

-lOV PrecisiOn Power Supply

B-CS-Rl 07-0-l

Inverter

B-CS-Rl ll-O-T

Diode Gate

D'Ac

BS-D-34D-0—2

.....

...............

ENGINEERING

.....

Type 779 Power Supply Output Checks

......

...............

1..

...............

‘

.............................

........................................

.....................

..........................................

.......................................

17
l9
2i

2]
22

‘

B—CS-R202-0-i

Dual Flip-Flop

........................

.............

CSéB-R203

Triple Flip-Flop

B—CS—R302-0—i

Delay. .'

B-CS-W68l-O-l

Scope Intensitier

......

................

...............................

..............................

..,

Q g .' '.
.

.........................

C-CS-Wl 03—O-l

Device Selector

..........

..........
_

INTRODUCTION
Digital Equipment Corporation of Maynard, Massachusetts, offers as part of its product line

oscillOscope display, designated Type 34D, which may be supplied as an option to a PDP-8 or

PDP-8/S system.

1digital computer to be displayed

The display unit allows information from a

the

oscilloscope as a point of light whose location is specified by two lO-bit digital words.

‘

The basic 34D Oscilloscope Display Unit consists of a Tektronix RM-503 Oscilloscope or
.

equivalent and its associated logic controls.
A photomultiplier
over,

light pen, optional with the 34D,

to communicate with,

can

be employed to exercise control

running computer program.

SCOPE
-

This manual provides complete-maintenance data on the logic circuitry,

34D Oscilloscope Display and both the PDP-8 and PDP—8/S.
mation on

it relates to the
,

This manual also includes detailed infor-

logic operation, interface characteristics and connections, and installation and mounting.

OPERATION

The 34D Oscilloscope Display accepts both vertical and horizontal lO—bit coordinate address
words from bits 2 through ll of the PDP-8 accumulator.

34D
_

Pulses that are generated internally by the

Oscilloscope Display control logic transfer the 10-bit words into
The outputs of these buffers, converted from digital to analog

buffer.

flection inputs to the display oscilloscope.

X-axis buffer and a Y-axis

levels, provide dc-level de-

Logic circuits implement these function by interpreting
i

commands (IOP pulses)

i
V

generated

in the computer.

A 6-bit address code, in the computer memory buffer,
to the

logic control of the display.

The sensing of the address code by the logic circuits enables the

receipt of prOCessor-generated IOP pulses.
of the display unit.

the}

In the display control

logic, IOT pulses control operation

Upon receipt of IOP pulses, the functions of the IOT pulses that. are generated in

display 'control logic
IOT 051

provides the basic activating signal

are as

follows.

(061) clears the 10-bit X (Y) buffer registers.

IOT 052 (062) loads the lO-bit X (Y) buffer registers with data .from the processor accumulator.

IOT 0541(064) intensifies the point of light at the location determined by the X- and Y-address words.

IOT 07l allows the program to skip if the light pen flag is 0 ONE.
IOT O72 clears the light pen flag.

IOT O74 clears the

brightness registers.

IOT 075 sets brightness register to l

IOT 076 sets brightnessre'gister to 2.
IOT 077 sets brightness register
3 l
.

to 3.

Program Instructions
Table 3-l

lists the instructions from the processor that provide all necessary control over the

Operation of the Type 34D Oscilloscope Display.
Table 3-1
Control Instructions
'

Mnemonic

Octal Code

DCX (DCY)

605i

Operation
Generates an IOP pulse at event time 1 to clear

(606i)

the X (Y) buffer in preparation for receiving new

display data.
6053 (6063)

DXL (DYL)

Generates an IOP pulse at event time l

(IOPl)

and an IOP pulse at event time 2 (IOP2) to clear

the .X (Y) buffers and then load in new data from

bits 2 through ll of the accumulator.
i

i
’

DIX (DIY)
»

Generates an IOP pulse at event time 3 (IOP4) to
intensify the point defined by the content of the-X— and Y-coordinate buffers. This command can

6054 (6064)
.
.

be combined with the DXL (DYL) command.
DXS

Generates IOP pulses IOP] , IOP2, and IOP4 at

6057

eventvtimes l,» 2, and 3, respectively, to execute

the combined functions performed by the DXL and
DIX commands.

The X-coordinate buffer is cleared

and loaded with‘new data; then the point defined

by the X- and’Y-buffers is intensified.
DYS

6067

_
,

_
i
‘

Generates IOP pulses IOPl IOP2, and IOP4 at
i, 2, and’3, respectively, to execute
the ‘combined functions performed by the DYL and
DIY commands. The Y-coordinate buffer is cleared
,

event times

and loaded with new data; then the point defined
by the content of the X- and Y-buffers is intensified.
DSB

607X

Generates an IOP pulse at event time 3 (IOP4) to
load the content of bits 10 and H ofthe instruction
into the brightness register. 'When the instruction
is 6075, the minimum brightness (0.4 ps) is set,
when 6076, the'medium brightness is (0.8 ps)‘is

set, and when 6077, the maximum brightness (3 ps)
is set.

3 .2

Logic Operation
‘

The following paragraphs describe the operation of the logic control of the Type 34D Oscil-

Ioscope DisPlay as it relates to the PDP-8 and PDP- 8/S

computers.

Logic controls for the oscilloscope

display appear on DEC engineering drawing BS-D—34D- 0- 2, sheets l and 2 locatedIn section 8 of this
manual.

When referring to particular logic controlsIn the text, the sheet number and coordinate lo-

cation will
.

bevgiven.

The coordinate location is a letter/number designation used on DEC drawings to

facilitate the location of individual logic controls.
3.2.]

Processor TUrn-On

During the processor turn-on period, or whenever the START key is

depressed, POWER CLEAR pulses (—3V, lOO-ns pulses at

10 KHz rate) clear the light pen flag flip—

flop (sheet l, D5) and set brightness registers O and l (sheet 1, B5) to the ONE state.

With both

brightness registers in the ONE state, the point otlight on the oscilloscope is at maximum brightness.
3.2.2

Coordinate Channels

Because the horizontal

(X) and vertical (Y) coordinate channels

operate identically, only the horizontal channel will be discussed in‘ detail.
3.2.2.1

I_n_it_i_ale_ -'- Computer—generated command pulses initiate operation at the 34D Oscilloscope

Display.

The Computer sendsthe address code at the peripheral device over the I/O bus lines.

This

display control logic senses the address code, through connectors BOD3‘and BOD4 (sheet 2, Dl), in
the Wl03 Device Selector at BOAlO, BOBlO (sheet 2, C2,

D2). (The address code is stored in com-

puter memory butter bits 3. through 8.) Sensing, by the display control logic, of its own discrete address codeallows acceptance of the IOP pulses, generated by the computer, and provided at terminals

K, M,: and P otconnector BOD2 (sheet 2, Cl). The decoded address enablesthe input gates to the
three pulse amplifiers (PA) on the Wl03 Device selector at BOAlO, BOBlO (sheet 2,

C2).

When en4

abled, these gates permit incoming IOP pulses to activate their respective PA to produce the IOT pulses

actually used within the display control circuits.
3.2.2.2

Clearing and Loading the Butter

Initially, the‘computer generates a DCX instruction, set—

ting up the I/O address, and transmitting an IOPl pulse to the display control through terminal K of.“
.

connector

BOD2 (sheet 2, Cl). The lOO-ns pulse (IOT O5l), which isgenerated by the ADAE PA in

the Wl03 Device Selector, clears all ten R203 Data Butter Registers at connectors BOAl6 through
BOAl8, BOA24 (sheet 2, 82 through B8).

The DCX instruction is normally generated at the start of

the program run to ensure that the data butter registers are all in the ZERO state.

For the remainder

of the program, the clear instruction is combined with the load instruction (delayed by 1
increase the speed of operation

ps) to

Typically, an IOPl pulse (at’ event time i) and an IOP2 pulse (at event time 2) are generated
by the processor in the same computer cycle.
control

The IOT 051

(event time 1) pulse, generated within this

logic, clears'the ten R203 Data Buffer Registers (BOAlé through BOATS, VBOA24) (sheet 2, 32

through B8) to prepare them for acceptance of
at event time 2),

new

The IOT 052

data.

pulse(positive—going transition

occurring either 1 us or 4. 75 us later, is applied to the tenzDCD gates (sheet 2,

DXL and DCX (1 ps and 4. 75 us, respectively) determine
when the IOT 052 pulse appears at the input to the DCD gates in the
buffer.
The horizontal address word'Is loaded into the data buffer registers through connectors BOA]
BZ through BB) in the butter

The inStructions

and

BOA2I(sheet 2, BZ thrOugh B8). This, together, with the positive-going IOT 052 pulse enables
the DCD gate. When enabled, the DCD gate activates the data
flip-flop register and sets it to the
ONE level (-3V).

With any bit a logic ZERO (-3V) at connectors BOAl and BOA2, the corresponding

DCD gate is inhibited preventing the data Flip—flop From being‘set to the ONE state.

Thus the output.

of the flip-flop is now set to the same number held by the accumulator.

3.2.2.3

Digitaleto-Analog Conversion

—

The i0-‘-bit_ horizontal address word at the output of the data

flip-flops is converted into an analog voltage between ground and -lOV.

This is accomplished by four

3-input A601 Digital-to-Analog Converters at connectors BOA20 through BOA23 (sheet 2, B2 through
B8).

(The D/A converter, at connector BOA23, utilizes only the most significant input, pin U.)

The

analog voltage varies between its upper and lower limits in 'l024 discrete intervals, and‘is directly pro-

portional to the numerical value of the coordinate address.
A —3V input signal at all inputs to the D/A converter produces a ground level output.

Con-

versely, a CV at all inputs produces a -lOV analog output (see Table 3-2). This output connects to the
oscilloscope throughvpin D of connector BOA32 (sheet 2, A2).

accessibility to 1024 possible locations (210)

Ten data flip-flop registers'provide

the oscilloscope.

Table 3-2
Coordinate-Channel Logic Conversion Table
‘

Digital

Address

and

Flip—Flop States

D/A Converter Input

llllllllll

D/A

Buffer Output

xxxxxxxxxx

llllllillO

xxxxxxxxxO

100000000l

x00000000x

Converter

Output
mostpositive (ground)

Table 3—2
Coordinate-Channel Logic Conversion Table (continued)

Digital Address

Buffer Output

D/A

and

Converter

Flip-FlOp States

D/A Converter Input

Output

iboooooooo

xooooooooo

and

‘

0111111111

0xxxxxxxxx

0111111110

0xxxxxxxx0

000000000X

0000000001

mostnegative(-10volts)

0000000000

logic zero

0 = ground

ZERO state

1 =
=

-3V

logic one
ONE state

Intensity Circuits

3.2.3
an

At event time 3, the computer generates a DIX

instruction‘and transmits

IOP4 pulse which is received by the 34D Oscilloscope Display at pin P of connector BOD2 (sheet 2,

C1).

The W103 Device Selector Pulse Amplifier (AR AS) generates a 100-ns pulse (IOT 054) which,

in its positive-going transition, enables the EF DCD gate in the R302 at connector BOA29 (sheet 2,

This triggers the input to the delay and causes its output to change from a ground level
1 ps.

C2).

(0V) to -3V for

When the output returns to ground, it is applied to and halt-enables the three DCD gates con-

trolling the high-, medium-, and low—intensity delay circuits.

The level of brightness intensity is de-

pendent upon the output of the two R202 Brightness Register Flip-Flops at connector BOA26 (sheet 1,
B5). By way of example, the low brightness delay (sheet 2, C5) will operate only when the outputs
from BRO and BRi

are

0 and 1, respectively.

When this occurs, the requirements For the DEJH diode

gate (sheet 2, D4) are. satisfied and the -3V level at inputs D and E is inverted by the JH gate to pro—
duce a ground level.

This ground level is applied to the EF DCD gate (sheet 2, C4) and, when com-

bined with the IOT 054 positive-going pulse, enables that gate.
JKM delay whose output is applied to the W681
An

The DCD gate in turn triggers the

Intensity Amplifier (INT AMP, sheet 2, C6) for 0.4 ps.

output at 25V, produced by the intensity amplifier, is connected to the oscilloscope through pin F

of connector BOA32 (sheet 2,
manner as

C7).

the low brightness output.

The medium and high brightness outputs are produced in the same

The brightness register is loaded from the contentsof memory buffer bits 10 and ii

connector BOA4

(sheet 1, C5)

as a

D58 instruction is generated by the PDP-8.

is 6075, memory buffer bits 10 and ii contain a 0 (-3V) and a l

through

If the instruction code

(GRD) which appear at pins T and V,

respectively, of connector BOA4. The 0 level (—3V) at pin T is first inverted by the JK diode gate
(sheet 1, C5) which provides a ground level to the DE DCD gate (sheet 1, BS). When coupled with an
IOT 074 negative-going pulse, the DE DCD gate will be enabled placing brightness register BRO in the

CLEAR state.-

The 0 level (-3V) at pin T is also present at the level

input to the KL DCD gate, but it

only serves to inhibit the gate.
The T level

(GRD) at pin V is inverted by the LM gate (sheet 1, C5) producing a —3V level

output which inhibits the NP DCD gate (sheet 1, C5). The T level (GRD) at pin V half enables the

UV DCD gate. An IOT 074 pulse fulfills the DCD gate, setting brightness register BRl to the 1 state.

(The two diode gates in R107 at connector BOA25 (sheet 1, BS) permit collector-triggering of the
brightness register flip-flops by a power clear pulse.)
3.2.4

Light Pen Operation

A photomultiplier light pen may be used with the 34D to communicate

with a computer program. Basically, the light pen detects a point of light on the CRT and supplies it
as a

negative voltage level to the—display control circuits through pin V of connector BOA32 (sheet 1,

D8).

Because this signal is not a standard DEC level, it is buffered by an emitter follower in module

W681 at connector BOA3l

(sheet 1, D7).

istics required for DEC logic operation.

This buffering provides impedance and amplitude—characterPin R of the diode gate in module Rl ii at connector BOA27

(sheet 1, D6) receives the buffered signal and, together with the -3V light pen strobe at pin S is inverted by the transistor at pin U.

This inverted signal collector triggers the light pen flag flip-flop

(sheet 1, C5) setting it to the ONE state.

The light pen strobe is generated by the W68l

Amplifier at connector BOA31 (sheet 2, C6).

The outputs of the 0.4, 0.8,

Intensity

and 3 ps delays are OR-

combined so that the activation of any one produces a strobe pulse of the same duration as the intensify

signal that is transmitted to the oscilloscope.

The —3V output of the light pen flag flip-flop is inverted by the R] H at connector BOA27

(sheet l, C6) and activated the interrupt line (pin M of BOA6, sheet 1, C7).
A ONE on the light pen flag flip—flop also half-enables the skip command input gate (sheet 1,

pin E, C6).
a

The requirements for a skip are completed when bit 9 of the memory buffer register contains

ZERO (pin D) and when an IOT 07]

signal is generated (pin F).

three conditions acts as a NAND gate driving an inverter.

The diode gate connected to

Thus when all three

inputs

are

the

ONES, the

output at pin H is at 0 GND level. This GND level is brought out to pin K of connector BOA6 (sheet 1,
l

C6) to initiate the

skip instruction.

’

The light pen flag flip-flop can be cleared by a power-clear pulse or by the combination of
an

IOT 072 pulse and bit 9 of the memory buffer in the ZERO state.

The IOT O72 pulse is generated by

the AK AL power amplifier in the W103 Device Selector at connector BOA12/BOBIZ (sheet 1,
is applied as a ground level to the UV DCD

gate in module R203 at connector BOA24 (sheet 1

B3).
,

D5).

Bit 9 of the memory buffer at pin S of connector BOA4 is a —3V level which is inverted and applied to

the UV DCD gate.

With pins U and V qualified, the DCD gate is enabled and clears the light pen flag

flip-flop.
4

INTERFACE
This section illustrates the interface connections and signals between the PDP-8 and the

PDP-8/ S and the 34D Oscilloscope Display Unit. Figures 4-1 and 4-2 show the interface between the.
-

PDP—8 and the 34D.

Figures 4—3 through 4-5 illustrate the interface connections between the PDP-B/S

and 34D logic control.

Figure 4-6 indicates the connections between the 34D logic and the oscilloscope.

DISPLAY CONTROL

POP-8

BOAZ

MF34

BODZ

R107 BOAZS

POWER CLEAR

mos

'0'” 1

BOAIO/BOBt-O (x)
BOAH/BOBH (Y)
some/30912 (BR/LP)

IOP 2
'0’: 4

30m

ME34

(Y) o

AC2

AC3

x (Y) 1

AC4

x (Y) 2

AC5

(Y) 3

AC6

(Y) 4

ACT

(Y) 5

AC8

(Yrs

BOAZ

MF34

9001

8002
7

Ace

(Y)

AC1O

(Y) a

ACli

(Y) 9

sows

PFZ

8006

<)—-———— SKIP

<1— Rttt-BOAZ? (H)

<)-——-——-)~TERRUPT

<)—— Rm-eonm (N)

Figure 4-1

PDP-8 to 34D Control Interface,

X/Y

Address Data and Function Control Signals

ME35

BOA3

3003

MEMO)
M33“)

MBMO)

W103

M84“)
M85(0)
M85“)

MF35

BOA4

DONG/80810 (X COORDINATE)
BOAH/BOBH (Y COORDINATE)
BOAIZ/BOBIZ (BRIGHTNESS AND

8004

UGHTPEN)

M86(0)

MBGH)
M87(O)

> W103

M87“)

MEMO)
M88( 1)

Figure 4-2 PDP-8 to 34D Confrol Interface, X and Y
Coordinate Address and Brightness and Light Pen Address

E39

PTOB-A

Pros4a

PTOB—C

A13,A14

A06,A07

A22,A23

('10

H10

AO1/DO1

BACON)
BAC1 (I)
V

BAC2U)

BAC3(1)
POP-SIS

BACMI)

34D CONTROL
z

'0:

BACSU)
'0

BACSH)

«m

<40)

BACTH)
BACBH)

NOTE: PINS C.F,J,L,N,R.U GROUNDED

839

PT08 -A

PTos-s'

PTOB-C

813,814

806.807

822,823

AOZ/BOZ

BAGS“)
BACIOU)
BACHU)
ION

PDP~8IS

34D CONTROL

IOP2
[OF-‘4

‘

I/O
CLEAR

NOTE!

PINS

C,F,J,L,IN.R.U GROUNDED

Figure 4-3

PDP-8/S to 34D Control Logic Interface

E38

PTOB-B

PTOB-C

A13,A14

A29,A30

0—b— ICOO

A05/ 005

IMOO

H<}-— 1cm

IMO!

0—9— |C02
H

O—G— I003
K

POP-BIS

mn—

ICO4

<)—- ICO5

(PVT‘J

<)-—- was
<3-—— mm
<)—— Icoe

IMOZ

(HM'UZXIMU <4mvzx1mo <-|U)'UgXImO <4M'UZXINU
IM03

|M04

340 CONTROL

IM05

IMOG
lMOT

IMOB

NOTE: PINS

C,F,J,L,N,R,U GROUNDED

EST

PDP-B/S

PT08-A

PTOB-B

811,8t2

813,314

PTOB-C'

329,830

A06/006

<4UD‘UIXINO <40)“ngsz <4m-03X1rno <—|U)‘DZXIMO <4mv2x1mo

340 CONTROL

LCIF

NOTES PINS C,F,J,L.N,R.U

GROUNDEO

Figure 4-4

E40

PDP-8/S to 34D Control Logic Interface

PT08~A

PTOS

A15, A16

A08.Ao9

PT08

A24,A25

A03/ 003

BMBO(Ol
D

BMBNO)
E

BMBZlO)
H

BMB3lll
K

34D CONTROL

8M83(0)

POP-SIS

BMBMI)
p

BMBMO)
S

BMBSU)
T

BMBSlO)
V

NOTEI

PINS C,F,J,L.N.R.U GROUNDED

Figure 4-5 PDP—8/S Control Interface, Brightness, Light
Pen, and X and Y Coordinate Control Address

PTOS

D40

PT08

815,816

BMBGII)

PTOB -C

824,825

AO4/DO4

o
E

BMB7I 1)
H

BMB7IO)
K

PDP~ 8/3

808,809

BMBBII)
M

BMB8IO)
P

BMBSIO)
s

BMB
T

BMBIIIO)
v

NOTES PINS C,F,J,L,N,R,U

GROUNDED

<-IU)"UZXINO <dwvzxzmo

34D CONTROL

Figure 4-5 PDP-8/S Control Interface, Brightness, Light
Pen, and X and Y Coordinate Control Address (continued)

OSCILLOSCOPE

DISPLAY CONTROL

BOA32

——

DEFLECTION INPUT

——-——#

DEFLECTION INPUT

———->l

80A32

‘r——

REFER TO APPROPRIATE

OSCILLOSCOPE MANUAL
FOR CONNECTIONS

BOA32

———-——-

INTENSITY ————H

BOA32

X+Y NEGATIVE INPUTS' (*5Vl --U

Figure 4-6

34D Control to Oscilloscope Interface

POWER SUPPLY

A DEC Type 779 Power Supply that is provided with the display control

three voltage levels (+10,

logic generates the

—15, and —30 Vdc) required for operation of the display and it's logic.

Section 8 of this document contains the schematic of the power supply DEC Drawing Number

R5—B-779). Detailed information on the operational characteristics of this power supply is provided in
the DEC Systems Modules Catalog (C-l00).
6

MAINTENANCE

6 .1

Preventive Maintenance
The general preventive maintenance procedures in the PDP-8 Maintenance Manual

Doc.

(DEC

F-87) also apply to the display control logic.

6.1 .l

Power Supply Checks

Table 6-l lists the output voltage checks required for the DEC Type

779 Power Supply used in this equipment.

Table 6-l ,

use a

To perform the power supply output checks described in

multimeter to make the output voltage measurements with the normal load connected,

and an oscilloscope to measure the peak-to—peak ripple content on all do outputs of the supply.

The

+l0V and —l5V supplies are not adiustable; therefore, if any voltage or ripple content is not within

specifications, consider the power supply defective and initiate troubleshooting procedures.

Table 6-l

Measurement

Terminals at

Power Supply

0“pr
Orange (+) to

Type 779 Power Supply Output Checks

Max1mum

Nominal

Acceptable

Output
(Vdc)

Output
Range (V)

Current

+l0

+9.6 to ll .0

7.5

Yellow (—)

Output

(amp)

Maximum
Pea k

-to-Plea
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6.2

Oscilloscope Maintenance
For information on maintenance and troubleshooting procedures, refer to the documentation

provided by the manufacturer of the oscilloscope.
a

Tektronix RM

The basic 34D Oscilloscope Display Unit utilizes

-‘503 Oscilloscope; however, other models may be used.

INSTALLATION

7.]

Cabinet and Desk Top Configuration
When the oscilloscope is

supplied

either part of a cabinet—mounted or desk top PDP-8

system configuration, it normally mounts in a standard l9-in. radio rack adjacent to the central pro7

cessor.

The" logic controls and power supply for the Type 34D Oscilloscope Display'Unit are mounted
in the same cabinet as the oscilloscope when supplied as part of a desk-top configuration.

Otherwise

the logic controls and power supply are normally'mounted in the PDP-8 cabinet itself.

Environmental and Power Requirements

7.2

The environmental and power requirements for the 34D logic controls are as specified in the
PDP—8 Maintenance Manual

(DEC Doc. F-87).

For the oscilloscope specifications, refer to the ap—

propriate oscilloscope manufacturer's documentation supplied with the Type 34D Oscilloscope Display
Unit.

ENGINEERING DRAWINGS

This section contains the following logic diagrams, wiring diagrams, and module schematics

which are pertinent to the Type 34D Oscilloscope Display Unit:
'

35-0340-0-2

Logic Diagrams
‘

UML—D-34D-O-3

Utilization Module List

WD-D-34D-0-4

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