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DEC-08-I5AA-D

December 1967

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Document:	RM08 Serial Drum
Order Number:	DEC-08-I5AA-D
Revision:
Pages:	96
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INSTRUCTION

MANUAL

SERIAL DRUM SYSTEM
TYPE RMO8

DIGITAL EQUIPMENT CORPORATION

MAYNARD, MASSACHUSETTS

DEC—08—I5AA—D

SERIAL DRUM SYSTEM
TYPE RM08

INSTRUCTION MANUAL
November I967

DIGITAL EOLJIPMENT CORPORATION

MAYNAFIO, MASSACHUSETTS

CONTENTS

CHAPTER I
INTRODUCTION

Purpose

Physical Description

lsboio

Abbreviations
Associated Publications

CHAPTER 2
PRINCIPLES OF OPERATION

Functional
o

Description

Device Selector

. _.|

Drum Core Location Counter (DCL)
Drum Track (DTA) and Sector Address

NMNNNNNNNNNN\OONOmetn-h-hw

\00\l0\(J‘|-§ON

(DSA) Registers

Drum Field and Sector Number Registers
Sector Number Counter
Drum Final Buffer (DFB)

Drum Serial Buffer (DSB)
Drum Head Selection

Drum Control
0

Read-Write Parity

Recording and Playback Technique
Drum Format
Drum Write Cycle
Write One Sector-Detailed

Description

Drum Read Cycle
Read One

Sector

Detailed Description

Parity Check
Parity Error/Data Error Detect
Drum Track Selection Circuits

Mechanical
Power

Description of Drum

Supply and Distribution (RMO8 Drum System)
»

CHAPTER 3
INTERFACE

CONTENTS (continued)

CHAPTER 4
INSTALLATION AND OPERATION
Site Requirements

Controls and Indicators
CHAPTER 5

PROGRAMMING

01010101 #05.)

Instructions

5-]

Drum Format and Program Timing

5-2

Programming Subroutines

5-3

Field Lockout Switches

5-4

CHAPTER 6
MAINTENANCE
Preventive Maintenance

Mechanical Checks
Power Supply Checks

O\O~O\O\O~O\O\O~O\O\O~O~O\O\O\O\O~O\NNNNN
—-I

\x'crouluboio

Timing Checks
Drum Sense Amplifier Checks

Drum Head Mounting Adjustments
Pad Leveling Adiustment

Marginal Checks
Corrective Maintenance

System Troubleshooting
Diagnostic Program

Signal Tracing
Aggravation Tests
Circuit Troubleshooting

0~(J1-l>-CAJI\)

Repair

6-12

Head Pad Replacement

6-13

Validation Test

6-14

Log Entry

6-14

CHAPTER 7
ENGINEERING DRAWINGS

Drawing Numbers

7—1

Circuit Symbols

7—l

CONTENTS, (continued)

ILLUSTRATIONS
1-1

Component Location—RMO8

1-2

2-1

Type RM08 Functional Diagram

2-2

2—2

Simplified Timing

2-3

Simplified Logic of Writing Circuits

2-5

2-4

Typical Recording and Playback Timing

2-6

2-5

Drum Format

2—7

2—6

Word Format

2-8

2-7

Write Cycle Timing

2-1 1

2—8

Read Cycle Timing

2-14

2—9

Drum Head Mounting

2-17

2-1 0

Operating Position of the Head Pad

2—1 8

Field Lockout Switch Panel

4—1

6—]

Stop Screw Position

6-4

6-2

Operating Positions of Head Pad

6—5

—

NRZ Writing

2—4

TABLES

Specifications

Analysis of Instructions for Write Cycle
Analysis of Instructions For Read Cycle
Controls, Indicators, and Switches For RMO8 Serial Drum

Type RMO8 Serial Drum Instructions
Maintenance

Equipment

Spare Module List
ENGINEERING DRAWINGS
BS-E—RMO8-O-2

Drum X & Y Select and Drum Heads Serial DrUm

7-3

BS—E-RMO8—O—3

DFB, DSB Register and Control

7-5

BS-D-RMO8—O-4

Drum Control Data Channel

7-7

BS-D-RM08—O—5

DCL DTA, SA & SC Register & Control Serial Drum

7-9

UML-D-RM08-O-6

Utilization Module List (Part I)

7—] i

UML—D-RMO8-O—6

Utilization Module List (Part 2)

7—l 3

WD—D-RMO8-O—IO

Serial Drum Buss Schedule

7-I 5

PW-D-RM08-0-12

Serial Drum Power Wiring

7—1 7

ENGINEERING DRAWINGS (continued)
BS—D—RAAOB—O-Zi

Sector Counter Readout Number Counter & Number Register

7—19

FD—D-RAAO8-O—23

Flow Diagram

7-21

CL-A-RMOB—O-i 5

Serial Drum RM08 R/W Head Select Drum Side

7—23

CL-A-RMO8—O-i 6

Serial Drum RM08 Clock Rack Plug

7-24

CL—A—RMO8—O-i 7

Serial Drum RM08 Selection Cable

7—25

VVS—A-RAAO8-O-18

Field Lockout Panel Wiring Serial Drum RM08

7—26

AA—RAAO8—O—24

Drum Core Location Indicator Cable

7-27

iA—RAAO8-O-25

Drum Sector Counter Indicator Cable

7—28

iA-RAAO8-0—26

Drum Final Buffer Indicator Cable

7-29

AA-RAAO8—O—27

Drum Track Address Indicator Cable

7-30

cs—779-5

Power Supply

B—CS—836—O-2

DC Remote Power Control

7—31

CS—B-iZi3

Quadruple Flip—Flop

7—32

B-Cs-1304—o—1

Delay

7—32

CS-B—i410—23

Pulse Generator

7-33

Drum Sense Amp

7-33

B-CS—4102-0—i

Inverter

7-34

RS—B—4106

Inverter

7—34

B-CS—4112—O—1

Diode Gate

7-35

RS—B—4ii3

Diode

7-35

B-CS-4ii4—O—1

Diode

7—36

B-CS—4il5-O-1

Diode

7—36

cs-4127-7

Capacitor-Diode—Inverter

7—37

B-CS-4i4i—O—i

Diode Unit

7—37

cs-4215-1o

4—Bit Counter

7—38

CS—4216-10

Quadruple Flip—Flop

7—38

cs-4217-4

4—Bit Counter

7-39

B-CS—4301—O-1

Delay

7-39

cs-C—4222-9

7—Bit Counter with Read In Gates

7—40

CS-C-4220‘

8—Bit Buffer Register

7-41

cs—c—4225-5

8—Bit BCD or

B—CS-4303-O-i

Integrating One-Shot

7-43

CS—440i-ii

Clock

7-43

CS-B—4529

Drum NRZ Writer

7-44

cs-1537—5
_

7-31

‘

Binary Counter

7-42

EN GINEERING DRAWIN GS (continued)

B—C 5-4530-0—1

Drum X Select

7-44

B-C S-453l -O—i

Drum Y Select

7-45

CS—B-4604-I 8

Pulse Amplifier

7-45

CS-4605—3

Pulse Amplifier

7—46

CS—B—4606—I I

Pulse Amplifier

7-46

CS-B-él 02-6

Inverter

7-47

CS—B-6106—7

Inverter

7—47

CS-B-ol lO

Diode Gate

7—48

CS—B—él I 3-2

Diode

7—48

B-C 5-61 1 5-0—1

Diode Gate

7—49

B—CS-Rl 07-0—1

Inverter

7—49

vii

RM08 SERIAL DRUM SYSTEM

CHAPTERI
INTRODUCTION

This manual describes the operation of and provides maintenance information on the Digital

Equipment Corporation Type RM08 Serial Drum System.

PURPOSE

I .i

The Type RM08 Serial Drum System is used in conjunction with the Programmed Data Processor-8

(PDP—8) as an auxiliary data storage device.
and retrieved in sectors of 16 computer words.
core

Information in the PDP-8 can be stored in the RM08 drum.
Sectors are automatically transferred between the PDP—8

memory and the drum after program initialization.

Transfer of each word is interleaved with the

running computer program under control of the PDP-8 data break facilities.

A word is transferred in

parallel (l2 bits at a time) and is read from or written onto the surface of the rotating drum in serial
fashion (one bit at a time).
Words within the drum system consist of 12 information bits and a parity bit.

Parity bits are

generated internally when writing, and are checked when reading. The drum system has 64 tracks

track holds 64 sectors of i6 13-bit words.

each

The storage capability can be expanded to 256 tracks (262, I44

words).

I .2

PHYSICAL DESCRIPTION
The Type RM08 Serial Drum System is contained in a DEC computer cabinet 23—i/23n. wide,

27-1/16 in. deep, and 69-1/8 in. high.

All indicators are located on a panel at the front of the machine.

A coordinate system is used to locate racks,

modules, cable connectors and terminals.

Each

5-1/4 in. position on the front of the cabinet is assigned a capital letter beginning with A at the top,
as

indicated in Figure I-l

viewed from the wiring side

Modules are numbered from I

through 25 from left to right in a rack, as

(front). Connectors are numbered from I thr0ugh 6 from left to right, as

viewed from the front of the machine.

Blank-module and

connector locations

are

numbered, and

not

terminals on a module connector are designated by capital letters from top to bottom.
is the fourth location from the top (D), the ninth module from the left

top of the module.

For example, D09E

(09), and the fifth terminal from the

Engineering drawing D—RMO8-O—6 (Chapter 7) shows the module types used in racks
‘

IC, ID, andIE.
Table 1-1 lists the specifications for the Type RM08 Serial Drum System.

I —l

RM08 SERIAL DRUM SYSTEM

iNomATOR

PANEL

TYPE

832

POWER CONTROL
BLANK

Loac

779
TYPE
POWER SUPPLY

LOG":

Loac

12FLw-cmp
SLOTS

HELD

LOCKOUT

swncn

PANEL

BLANK

TYPE

836

POWER CONTROL

BLANK
BLANK

Figure 1—]

Component Location-RM08

Table 1-]

Specifications
Dimensions:

23-1/2 in. wide
27—i/l6 in. deep
69—i/8in.lfigh
Service Clearances:

8-3/4in} flont
14-7/8 in

rear

Weight:
500 lb.

Power Requirements:

115V, 60 c/s,single phase

240V, 50 C/s, single phase

8A} starting current

4A startingcurrent

5A running current

2.5A running current

Power Control Point:

Local or remote

(computer)

Signal Cables:
H

lO-ft, 9-conductor coaxial cables with W021 connectors

RM08 SERIAL DRUM SYSTEM

Table l—l

(continued)
Specifications

Ambient Temperature:

60°F to 100°F

Initial Starting Delay:
5 min.

Drum Motor:

single phase, 2 pole, induction, capacitor start and run

ll5V or 245V,
Write

Current):

l20 mA
Drum

Speed:

3600 rpm

(60 c/s)
‘

3000 rpm (50 c/s)
Word Transfer Time:
l5.6 p5 (3600 rpm)
l9.5 us (3000 rpm)
Sector Transfer Cycle:
250 p5
3T3 p5

(3600 rpm)
(3000 rpm)

Access Time:
8.65 ms (17.3 ms max at 3600 rpm)

l0.3 ms (20.5 ms max at 3000 rpm)

ABBREVIATIONS
The Following abbreviations are used in text throughout this manual and on the engineering

drawings of Chapter 7.
Definition

Abbreviation
AC

Accumulator in computer

ACT

Active

AMP

Amplifier

COND

Condition

CLR

Clear

DCL

location counter
Drum
Icore
serlal drum

Abbreviation
DDC

Definition

Drum data channel in serial
drum

DE
DF and DFB

Data error
Drum final buffer in serial

drum
DS

Device selector in serial drum

DSA

Drum sector address

DTA

Drum track address

INT

Interrupt control in computer

DCT

Drum control element in

serial drum

RM08 SERIAL DRUM SYSTEM

Abbreviation
IOT

MA and MAR

Definition

Parity error

Memory address register in

Pulse generator

Request flip-flop

Mem°ry “He" ”59'5“" '“

R PARITY

computer
PA

PUlse amplifier

PA R

Parr't y

DSB CONTROL

Drum serial buffer control

(_ 3V source)

l .4

Definition

Input/Output transfer
computer

Abbreviation

Read/write parity flip-flop in
.

serial drum
,

SC.

Sector counter in serial drum

Sector address

TRA

Transfer

ASSOCIATED PUBLICATIONS
The following documents are pertinent to the RM08 Serial Drum Systems.
PDP—8 Users Handbook,
PDP—8 Maintenance Manual,

Systems Modules Catalog, C-lOO
FLIP—CHIP Modules Catalog, C-l05

RM08 SERIAL DRUM SYSTEM

CHAPTER2
PRINCIPLES

OPERATION

FUNCTIONAL DESCRIPTION

2.1

The major functional areas of the Type RM08 Serial Drum
and are described in the following paragraphs.
are

contained in Chapter 7.

Detailed engineering diagrams for the serial drum logic

The references in text are to the engineering drawing numbers.

information transfer flow is illustrated in

2.1 .l

System are illustrated in Figure 2—1

Complete

Dwg. No. D-RMO8-O—23.

Device Selector

During the execution of an IOT instruction, the device selector receives MB bits 3 through 8
and the IOPI ,

IOP2, and IOP4 pulses from the computer. The internal structure of the device selector,

which consists of three Type 4605 modules,
circuits during an IOT instruction.

permits it to generate the IOT pulses which control the drum

The device selector is shown in the lower right—hand corner of

Dwg. No. D—RM08—O-4.

2.l .2

Drum Core Location Counter

(DCL)

The drum core location counter (Dwg. No.

D-RMO8-O-5) is a 15-bit register which addresses

the next core location to or from which the next word is to be transferred.

Prior to transfer of the initial

word in a block, the address of the first word is set into the DCL under program control from the computer

accumulator.

2.l .3

As each word is transferred, the DCL is incremented by one.

Drum Track

(DTA) and Sector Address (DSA) Registers

The DTA and DSA registers (Dwg. No.

D-RM08-O-5) comprise a l4—bit register (8 tracks and

6 sectors) which addresses the drum track and sector which is currently transferring data.
tion of a successful last sector transfer (error flag is 0), these registers are incremented

2.] .4

Upon comple-

by one.

Drum Field and Sector Number Registers

The drum field register is a 2-bit register which holds the drum field.

The sector number

registers can only be changed by an IOT. The drum field register is a 2-bit register which specifies one
of four drum fields (64K wordsper field) to which the data will be transferred.
in

(Dwg. No. D-RM08—0—3).

2-1

These registers are shown

RMO8 SERIAL DRUM SYSTEM

DATA TO BE WRITTEN ON THE DRUM I12 BITS)

“AREA:

DATA READ FROM THE DRUM (IZ BITS)

SELECT CODE
3 IOP

IOP

TO ALL LOG'C

SELECTOR

GENERATOR

IOT COMMAND
PULSES (7)

DEVICE

PULSES

DRUM FINAL

ELEMENTS

BUFFER

(DFB,
2
I2

DRUM
INPUT/ OUTPUT
3m,
FACILITY

SKIP

READ / WRITE

GATES

PARITY

COMPLETION FLAG

(DSB)

PARITY
ERROR

ERROR FLAG

INTERRUPT
PROGRAM

SERIAL

BUFFER

INPUT/OUTPUT

SKIP

REQUEST

INTERRUPT
READ
STROBE

”RWAL

CONTR
DATA
AC INPUT

ERROR

DATA
READ

——D‘

AND PARITY ERROR (2)
<>————————

GATES

WRITER

AMPLIFIER

READ / WRITE
BUSSES (2)

DATA
ERROR

CLOCK PULSE (T2)

TIMING

CLOCK
TRACK

<>—————

AMPLIFIER
i

BREAK REQUEST

SECTOR

TRANSFER DIRECTION

DATA
BREAK

00%mNpngngo

DATA
CHANNEL

DRUM

ADDRESS ACCEPTED

”

‘

To DFB AND DCL
TRACK AND

SECTOR SELECTION

AccglMTuPLUATTOR

DRUM
8

AND

TRACK
SECTOR

RéaDRESS
STER 6

(12)

x AND Y

DRUM

SELECT

MEMORY

CLOCK TRACK
TRACK o

6.16.32.64
128192 ,or

(DAR)

SECTOR
NUMBER

5S‘HEADS

FIELD
REGISTER

TRANSFER LOCATION
IN COMPUTER CORE

MEMORY (I2 BITS)
3

i___.__o
1 + LAST ADDRESS OF

MEMORY
ADDRESS

DATA TRANSFER (l2 BITS)

DRUM CORE

LOCATION

55:3“;

<>——————————-

Q—

PDP‘B

RMoa—

COMPUTER

BREAK

SERIAL MAGNETIC DRUM SYSTEM

FIELD

Figure 2-]

Type RMO8 Functional Diagram

255

RMOS SERIAL DRUM SYSTEM

Sector Number Counter

2.1 .5

The sector number‘counter (Dwg. No.

D—RMOB-O-Zl) is a 7-bit counter which contains the

25 complement of the sector number register.

The number of sectors transferred is counted, and any

overflow produces a flag interrupt condition.

The sector counter is a 6—bit counter which is incremented

automatically after each sector of clock information.
Drum Final Buffer (DFB)

2.l .6

The drum final buffer (Dwg. No.

E—RMO8-O-3)‘ is a l2-bit register under control of the data

break facility which is a buffer between the memory buffer register and the drum serial buffer.

write—in, the DFB holds the next word to be written.

During

During read—out, the DFB stores the word read

from the drum until it is transferred to the PDP-8.

2.1 .7

Drum Serial Buffer (DSB)

The drum serial buffer (Dwg. No.

E—RMO8—O-3) is a 14-bit register which contains a data

word and two control bits. This register serves as a serial-to-parallel converter during read-out, and
as a

parallel—to—serial converter during write-in.

Information is read from the drum into the DSB in

serial fashion and is transferred into the DFB in parallel.

During write—in, a word is transferred in par-

allel from the DFB to the DSB and written serially around the drum.

2. l 1.8

Drum Head Selection

Selection of a drum head is performed in the drum X and Y select circuits (Dwg. No.

E-RMO8-O—2) and in the diode matrix within the drum housing.

The l6 FIELD LOCKOUT switches,

when closed, inhibit the X0 and XI selection modules to prevent writing on certain tracks which may
contain data the programmer wishes to preserve.

Each switch inhibits writing on four tracks

(40961 0

words).

2.l .9

Drum Control

The basic timing pulses for the machine are generated in the DCT from pulses received from
the clock track amplifier.

gates.

The DCT also contains a 4-stage device consisting of four negative diode

Each state of this device corresponds with and

initiates one of the machine control states:

(IDLE), transfer (TRA), active (ACT), or transfer done (COMP FLAG).
No.

D-RM08-O—4).

2-3

idle

This logic is shown on Dwg.

RMO8 SERIAL DRUM SYSTEM

2.l

Read-Write Parity
As each bit of a word is written on the drum surface, the R PARITY
flip—flop counts the number

of binary l's and produces a l3th bit to provide odd
parity.

When data is read from the drum, this flip—

flop again counts the l's and sets the parity error (PE) flip-flop if an even number is detected in any
The condition of the PE flip-flop is indicated in the DCT as one of the two
possible causes of an

word.
error

condition.

2.2

These circuits are shown in area C4 of Dwg. No. E-RM08-O—3.

RECORDING AND PLAYBACK TECHNIQUE
The recording and playback technique employed in the

(non—return-to-zero) phase modulation.

This technique records binary l's and 0's by controlling the

direction of flux change on the drum surface.
a

Type RMO8 Serial Drum System is NRZ

For example,

flux change in one direction represents

l, and a flux change in the opposite direction represents a 0.

diagram

To clarify this point, consider the timing diagram Figure 2—2 and the
simplified logic

Figure 2-3. As shown on these drawings, a positive voltage swing (identified by the arrow) from the
write flip-flop produces a flux change to write a
to write a

pulse.

l, and a negative voltage swing produces a flux change

The read/write circuits are synchronized so that recording occurs on the

phase A time

The write flip—flop must be in a state so that the phase A pulse can
complement the flip-flop to

write the specified bit.

The phase B pulse shifts the bit to be written into the last bit of the data

the D530 flip-flop.

The delayed phase B pulse senses the DSBO bit to put the write

state so that the next

phase A pulse complements the write flip-flop to write the bit specified by DSBO.

BITS TO BE WRITTEN

|<—1—.|¢—o——.l<——1——>l‘——1—.l<—o——.|<——o—'——>

flip—flop in the proper

U‘.

DELAYED

.3335 3333

7—___F U

L___l—_L__

DRUM FLUX

r—L

J—__l

Figure 2-2

Simplified Timing

2—4

l_l

NRZ Writing

RM08 SERIAL DRUM SYSTEM

(SHIFT REGISTER)

088

0580

SHIFT DIRECTION

0381

GB SHIFT PULSE

088"

————f
DRUM READ

WRITE HEAD

___OT T<>_____
DSBO°

0‘

WRITE

’b

.— DSBO'
A

De DELAYED —-—~

«~—

DB DELAYED

GB PULSE

Figure 2-3

Simplified Logic of Writing Circuits

Obviously, when the state of write flip-flop is switched by the delayed phase B pulse, it
causes a

flux change on the drum surface.

This flux change is not sensed, however,

as a

binary l bit

because the drum is sensed during playback (reading) for a flux change only at phase A time.

Detailed

information on the principle of NRZ recording using phase modulation is shown on Figure 2-4.

2 .3

DRUM FORMAT
Data from the computer is written on drum tracks that circumscribe the drum cylinder as shown

in Figure 2-5.

The RM08 has 256 tracks; each data track contains 64 sectors and each sector contains

16 13-bit words

(0 through 17 octal).

The 13-bit word consists of 12 data bits and a

parity bit.

The words within any particular sector are stored consecutively on the track.
words on the track are for sector 0; the next 16 words for sector 1, etc.,

last l6 words on the drum track are words 0 through 17 for sector
word throughout the drum track.

The first 16

shown in Figure 2-5.

778. There

The drum also contains a clock pulse track.

are

The

13 clock pulses per

The clock pulse track

supplies clock pulses to the drum control logic at l.2 [.15 (60 0/5) intervals to synchronize writing and
reading of the drum. There is a TC ps gap between sectors within each track and a 300 p5 gap to separate
the beginning and end of each track.

A 300 ps gap, where no clock pulses exist, separates the beginning

and end of each track.

2-5

RM08 SERIAL DRUM SYSTEM

0
TIME IN ,_
MICROSECOND s

’

I
fl

—u—-

,—

IILFLTLLTTLITL—
'

«BILILFLMILILIIIL
JAM TRANSFER

Dse°
(EXAMPLE OF
WORD TO BE

WRITTEN)

COMPLEMENT

WRITE DATA
FLIP -FLOP

WRITE 4

+1 SATURATE

'/"\

HEAD
CURRENT

\/\

[1/

-I SATURATE
+ D SATURATE

'DRUM
SURFACE
FLUX

HEAD VOLTAGE _¢ SATURATE
(INPUT To
SLICE
SENSE AMPLIFIER
AT TERMINALS
\ LEVEL
F AND H) AND
SENSE AMPLIFIER
SLICE LEVEL

(TERMINAL 8)
READ
STROBE

READ

‘\

1—1

F\/‘
\7L_/.U

\_/\/\/

VLTTTIVI—

m
(TERMINAL

SENSE AMPLIFIER
OUTPUT

(TERMINAL L)

0388

‘

L-‘TI

LI'

'Figure 2— 4

L_IL_I

Typical Recording and Playback Timing

2—6

[—1

RM08 SERIAL DRUM SYSTEM

TRACK 2
TRACK 4
TRACK O
/
f
J

r
If

[—

CLOCK TRACK

SECTORO

TOP OF
DRUM

SECTOR 77

WORD

10 # SEC

WORD 17

WORD

SECTOR

GAP

SECTOR 0

SECTOR

WORD

SECTOR 0

WORD

SECTOR 0

Figure 2-5

300 fit SEC
GAP

WORD

SECTOR

WORD 16

17
77

SECTOR

WORD

SECTOR 77

10“ SEC

WORD

GAP

SECTOR

17
76

Drum Format

Figure 2-6 shows a closer view of the word format in a sector.
word of the track, word 0 of sector 0 and word 1 of sector 0.

The words shown are the first

The first clock pulse (index pulse)

following

the 300 ps gap
does not write a bit; it alerts the drum control circuits of the beginning of timing pulses.
The next 12 drum clock pulses write the 12 data bits of the word.

bit is written; i.e., if the 12 bits contain an even number of 1
's,
off parity.

To separate sectors,

After 12 bits are written,
a

odd

parity

parity bit of 1 is written to generate

10—ps gap exists after the 16th word of each sector and preceding the

first word of the succeeding sector.

2.4

DRUM WRITE CYCLE
As a quick reference» source, Table 2—1 ,

Analysis of Instructions for the Write Cycle, is

located at the end of this chapter.
In general, the DRCW instruction

control
core

logic.

(see Table 5-1) initiates a drum write cycle in the drum

IOT instruction 6624 must be given

memory field, drum field and number of sectors to be transferred.

if the core memory field, drum field and block size remain the same.
certain control

‘

initially before DRCW in order to select the proper
This instruction may be given once

The DRCW command normalizes

flip-flops in the drum control logic, sets the read/write flip—flop to the write state,

RM08

sets

SERIAL DRUM SYSTEM

the drum 4-state device to idle, sets the data in/out signal to notify' the computer data break facility

that the transfer} direction is out of the computer, loads the DCL from the accumulator, and sets the break

request flip—flop to initiate a data break.

NOTE

The drum control

logic incorporates a 4-state device to signify

drum control status.

The four states are IDLE, TRA, ACT, and COMP
one state at a time is entered and, during a normal trans—
Only

FLAG.

Entry into any state disables all

fer, the states advance in sequence.
other states.

The IDLE state indicates that the drum has not been acti—

vated by the program or it is waiting for a 200—ps delay to set the TRA
state.

The TRA state indicates that the drum control is set up to transfer

data, but the beginning of the drum track has not been encountered.
The ACT state is entered at the beginning of the track to transfer data.
The FLAG stage indicates the completion of a sector transfer.

INDEX PULSE

llllllllllllll‘

DRUMCLOCK

Hill.

HIHHHHHHHI

.
BITWRTTEN

1234567891011;

01234

:1
-<

SECTOR 0

.4
"

WORDt

Figure 2-6

The break request signal,

break cycle.

SECTOR 0
WORD]

Word Format

generated by the break request flip—flop,

initiates a computer data

During the data break cycle, the DFB is loaded from the memory location specified by the

DCL and the contents of the DCL are incremented so that the next data break cycle addresses the next

higher memory location.

The drum control circuits now_wait for the execution of the DRTS command

(see Table 5-l).
The DRTS command loads the drum track and sector address from the accumulator into the DTA
and DSA registers.

The DRTS command also loads the is SNC from the SNR+— ls complement of SNR.

The DTA address register selects the specified track for the ensuing write cycle, and the DSA selects one
sector of the track.

The DFB register contents are transferred into the DSB register.

also initiates a 200 ps delay to permit the track selection circuits to set up.

2—8

The DRTS command

RMOS SERIAL DRUM SYSTEM

After the 200 ps delay, the TRA (transfer) state is set.
duce the 2s complement of SNR.
gap

The first clock pulse of the selected sector (first clock pulse after the

the drum) sets the 4-state device to ACT (active).

address (SC

DSA), writing begins immediately.

erate the shift

If the sector counter is equal to the sector

The ACT signal enables the drum clock pulses to gen—

pulses and the write pulses (phase-A pulses).

The first word to be written is shifted into

After a data bit is shifted into the most significant bit of the DSB (DSBO),

the~ DSB by the shift pulses.
the phase-A

The SYNC is incremented by I to pro-

pulse complements the write'data flip-flop.

With the NRZ writer enabled, the data bit in DSBO is written on the drum.

The control

pulses continue shifting the contents of the DSB and writing the DSBO contents until the l2 data bits and
the parity bit are written.

After the 13 bits are written, the DSB is again loaded from the DFB and the

circuits are set up to write another 'word, and the break request is sent to the computer to reload the DFB

with the next word to be written.
written.

Writing continues in this manner until all l6 words of a sector are

The end of the sector (beginning of the

IO—ps gap) sets the drum 4-state device to FLAG if

SCOV is a one or sets the 4—state device to TRA if SCOV is a zero.

If TRA is set then the next l6-word

sector will

be written, if Flag is set then it indicates the completion of the data transfer.

2.4.]

Write One Sector-Detailed Description
The 6624

instruction loads the

core

memory bank, drum field, and puts

0l8 into SNR. The

DRCW command (Table 5-1) that is executed by the computer starts the write cycle.
this IOT instruction is 6605.

The execution of 6605 generates IOPl , IOP2, and IOP4 pulses in the

(Refer to the PDP-8 Users Handbook or the PDP-8 Maintenance Manual for the explanation

computer.

of the IOT instruction.)
Device Selector as shown

Memory buffer bits 3 through 8 and the IOP pulses are applied to the 4605
on

Dwg. No. D—RM08-0-4, coordinates C7.

(Hereafter, drawing references

‘will show only the last digit of the drawing and the coordinate, e.g., 4C7.)
ture

The internal gating struc-

of the 4605 circuit permits the IOT 6605 instruction to generate IOT 6601 and 6604 pulses (see

Table 2—l).
can

The octal code of

Note that the IOT 660i

pulse sets the 4-state device to IDLE (4A5).

The 4-state device

be in only one state at a time because the feedback from the current state disables the other three

states.

After the DRCW execution, the DCL register contains the memory address of the first word to

be written on the drum.
a

data break cycle

The DRCW has set the break request flip-flop; therefore, the computer executes

(Table 2-1) to load the DFB from the memory location specified by the DCL register.

The contents of the DCL register are incremented so that it addresses the next higher memory location.

(Information on the computer data break cycle can be found in the PDP-8

2-9

Maintenance Manual.)

RMO8 SERIAL DRUM SYSTEM

The control circuits now wait for the computer to execute the DRTS instruction.

The DRTS

instruction, 66l5, applied MB bits 3 through 8 and the IOP pulses to the device selector (4C7) to generate

the IOT 661i and 6614 pulses.

These pulses perform the operations outlined in Table 2-l

brief, they load the DTA and DSA registers from the accumulator, load the ONE's complement of SNR
—-> SNC,

state

transfer the contents of the DFB into DSB, and trigger the 200—ps delay which sets the TRA

(435/6) and H to SNC.
The D58 is loaded with the word to be written, and assuming that the 200-ps delay (485),

which permits the track selection circuits to set up, is completed, the 4—state

device is set to TRA.

Note that no phase—A (CPA) or phase—B (‘93) pulses are generated since ACT

O (i El l ,

4C3). Therefore,

the D58 is not shifted and no writing occurs.

The TAKE WORD signal

(generated during DRTS) is enabled and sets the break request (RQ)

This break generates the second word into the DFB.

flip—flop.

The DFB is transferred to the D53.

this point, word zero is in the DSB and word ONE is in the DFB.
The index pulse at the beginning of the desired sector generates the START pulse which sets
the 4-state device to the ACT state if SC

SA.

The drum clock pulses are shaped by PG I410 (4C2) the

output of which triggers the (BLOCK3.4—ps)and DATA (lZ—ps) integrating single shots.
are

clock pulses, the BLOCK and DATA multivibrators are held in the ONE state.

sence

of drum clock pulses,

the 300-ps gap
a

zero,

As long as there

However, in the ab—

during the iO—ps gap, the ZERO‘state is enforced for BLOCK, and during

the ZERO state is enforced in both BLOCK and DATA. When SC

SA and SNCOV is

the TRA is set, then the BLOCK going to 0 ONE will set ACT.
-

If the first four bits of the word to be written are 001 I ,

(3Dl) generates the OB + ACT pulse.

This pulse

shown in

Figure 2-7, the ACT signal

enables the WRITE DATA circuits (3D2) to put the WRITE

DATA flip—flop into the proper state to write the designated DSBO bit at phase A pulse time.

The ACT

signal gating (DA (I EIIR, 4C3) does not permit the index pulse to generate a phase—A pulse.

The second

drum clock pulse generates the phase A pulse, and it complements the WRITE DATA flip—flop.
WRITE DATA flip-flop output is coupled to the NRZ

bit.

Writer Module, Type 4529 to write the designated

The ensuing phase—B pulse generates the shift pulse

(38]) to shift the D88.

The phase-B pulse,

which was delayed to permit rise time of DSBO, generates the OB + ACT pulse which again

the proper state of the WRITE DATA flip—flop.
I

by the DSBO flip—flop.

The

establishes

The next phase-A pulse writes the second bit specified

RM08 SERIAL DRUM SYSTEM

rFlRST
DRUM CLOCK

MALI.»

I Wm

_._-._.I._ I“;

ACT

ACT+IDB

I
U

.4,_._

DATA‘

mm
‘

_.-IL._

ll
’/

l
I

osso‘k—ofl~o—.k-1—.k—1—+—o

WT
11

U—

I—_I
=IA

TAKE worm

:15

o——’I

Z
J
E
V
C
-"-—-<-—-—‘I——~—4—*——'>—_—[

DSB INI COND

COND

+4oo;¢3Ec

088 CLR

1) F —’DSB

Figure 2-7

Write Cycle

Timing

I_I

OVERFLow'

038 IN I

u
f

Wfi
LI

I
I

'.
l

'
a

PARITY

‘R U) a

I—WRITE

WRITE

/——U

CLOCK PULSE

I___

RM08 SERIAL DRUM SYSTEM

After ii shifts of the DSB register, DSB2 through DSBll contain all 0's becaUse the DSBS

flip—flop, which is continually reset by the shift pulses, shifts 0's into the DSB. 'Note that DF—F’DSB
pulse initially sets DSBS; this insures at least I bit in DSBZ through DSBII during the H shifts when a
word is wirtten in the event that the DSB was originally all 'O's.

flip—flop (3C4) since DSB2 through DSBli are all 0's.
flop to write the parity bit.
written.

Since the R

The OVERFLOW signal enables the R PARITY flip-

The shift pulses complement the R PARITY flip-flop for each 1 bit that is

PARITY flip-flop is initially set,

odd number of 1's leaves the R PARITY flip-

the WRITE DATA flip—
PARITYO signal (1 DlO-M, 3D2)
that the phase—A pulse writes‘a O parity bit
generate odd parity.

flop in the reset state.
flop to reset so

The 12th shift pulse sets the OVERFLOW

In this case, the R

causes

Writing continues until all l6 words of the address sector are written. The drum clock pulse
that writes the parity bit of the 16th word of sector 77

is the last drum clock pulse before the 10 ps gap.

The BLOCK one-shot multivibrator (3C1) reverts-to

ZERO state 3.4 ps after the last drum clock pulse.

the8

This signal BLOCK 0-3B6) sets the 4-state device to the FLAG state if SNCOV is a i

to a

TRA state

if SNCOV is a 0.

After the FLAG state is set, the actions that follow depend on the computer.
is programmed to write only

one

sector, the DRSC instruction (octal code 6622)

If the computer

generates the IOP 6622

pulse to sense the FLAG state (i ElOM, 4A7). When the FLAG state is l, the I/O SKIP causes the com—
puter to skip the next instruction and exit from the DRSC loop.
the drum control for errors.

This is accomplished by the DRSE instruction which generates the IOT 662]

pulses to sense the PEO-DEO state (4A8).

If no errors occur, the I/O SKIP signal causes the computer to

skip the next instruction and exit from the drum routine.
next instruction which contains a JMP to an

2.5

error

If an error occurs, the program will not skip the

check routine.

DRUM READ CYCLE
As a quick reference source, Table 2-2,

The DRSE (code 662i) may then sense

Analysis of Instruction for the Read Cycle,

is located

the end of this chapter.
The 6624 IOT is given first.

normalizes control flip-flops in

The DRCR instruction loads the DCL from the accumulator,

preparation for the read cycle, sets the 4-state device to IDLE, sets the

DATA IN/OUT signal to DATA IN, and sets the READ/WRITE flip-flop to read.
the DRTS instruction to

The program execute

load the DTA, DSA registers from the accumulator, SNR to SNC (ONE's comple-

ment) and after a 200-ps delay plus i to SNC and sets the TRA state.

If SC

SA then the next index

pulse sets the ACT state which enables the drum control circuits to read the drum.
addressed drum track is strobed into the least significant bit of the DSB register,
of the DSB are shifted.

checked.

Data read from the

(DSBS) and the contents

After" 12 shifts, the DSB contains the word read from the drum; then parity is

If a parity error occurs, the parity error flip-flop is set to indicate the error.

2-12

The DSB contentsl

RM08 SERIAL DRUM SYSTEM

are

transferred to the DFB and the break request signal is sent to the computer.

The computer enters a

data break cycle to transfer the DFB contents into the memory location specified by the DCL register.
The DCL contents are then incremented.

Transfer continues in this manner until all l6 words of the

After the last word of the sector is encountered, BLOCK is reset to a ZERO to

addressed sector are read.

signify the completion of the sector transfer.

Read One Sector

2.5.l

Detailed Description

The 6624 IOT is given first.

The DRCR instruction (octal code 6603) applies the MB bits 3

through 8 and the IOP pulses to the device selector to generate the IOT 660i and 6602 pulses. Table 2—2
shows

the detailed signal flow of the DRCR instruction. In brief, the DRCR instruction sets the IDLE state,

clears the READ/WRITE flip-flop, and loads the DCL from the accumulator.
remains clear to signify the READ state.

The READ/WRITE flip-flop

The READ signal causes the DATA IN signal

(4B7) to be -3V to

signify a DATA IN direction to the data break circuits in the computer.
The DRTS instruction is then executed to load the DTA and DSA registers with the drum track
and sector address of the forthcoming read Cycle (loads the ONE's complement SNR to
in Table 2-2, the DRTS instruction prepares the control circuits to read the first word.

inserted into DSBll

word has been read from the drum.

Therefore when DSBF is

The Read Cycle Timing Diagram,

As shown

Note that a l is

(by DSB INI COND + 400 ns) (3C8) and the DSB register is cleared.

the I that was inSerted into DSBH is in DSBF (332).
one

SNC).

After l2 shifts,

ONE, it indicates that

Figure 2—8, illustrates this

condition.

After TRA is set, the control circuits wait for the index pulse and SC
sets

(4C2) enables the drum clock pulses to pi

B (49B) pulses.

As the drum

The index pulse

duce phase A (<DA), READ STROBE, and phase

rotates, the flux changes induce signals into the read heads. The addressed

drum read head output is applied to the Type I537 Sense Amplifier.

0.25 us afterthe phaseApulse,
l is read from the drum;

sets

SA.

the BLOCK one—shot multivibrator (4Cl) to START which in turns sets the 4-state device to ACT (4A6).

The ACT signal

The READ STROBE, which occurs

senses the sense amplifier (3C6) and produces a DATA READ pulse when

pulse is produced when a O is read from the drum.

The DATA READ pulse

the DSBS flip-flop (3C8), and the shift pulse shifts the I from the DSBS into DSBI I , as it shifts the

D53 register.

RM08 SERIAL DRUM SYSTEM

DRUM CLOCK
PULSES

0A PULSES

{—Inoex

U
"'1
I

I2 #sec

.U
5

[0.55 SEC

W”

WWLJLILI

—fi

Lt]

—> I

WWLJLILILI

5
|

0.3

SEC

-->l|

READ STROBE

DATA READ

35‘

--H

‘—

H—70nSEC

III

l
l

SHIFT PULSE

K—4OO

ACT

I<—

I_I

i
OB PULSES

PULSE

OVERFLOW

TAKE WORD

DSB INI COND

DSB lNl COND
+ 400 nSEC

DSB CLR

Figure 2—8

Read Cycle

2—14

Timing

RMO8 SERIAL DRUM SYSTEM

The shift pulse also resets the DSBS flip-flop.

If the data bit read from the drum is O, the

DSBS flip—flop remains reset and the shift pulse shifts a 0 into the D581]
tinue in this manner until the original 1 bit
into the DSBF flip—flop, the DSBFl

the drum are in the DSB register.

that

was

Data transfers

flip-flop.

in D585 is shifted into DSBF.

con-'

As the l is shifted

The 12 bits read from

signal sets the OVERFLOW flip—flop (3C4).

The next phase-B pulse, enabled by READ and OVERFLOW, generates

TAKE WORD and DSB INI COND (3C2,

3C3).

The DSB INI COND signal checks parity

later) and prepares the circuits to read the next word from the drum.
the DSB contents into the DFB and sets the RQ flip-flop (4A2).

The TAKE WORD

The next phase—B

(explained

(3B2) transfers

pulse resets the

OVERFLOW flip—flop.
When the RQ flip—flop is set, the word read from the drum is in the DFB.

The RQ signal

initiates a computer data break cycle to transfer the DFB contents into the memory location specified

by the DCL (refer to Table 2—2).
Data transfer continues in this manner until all words of the addressed sector have been read.

As the

lO-ps gap is encountered, clock pulses cease to occur and the BLOCK multivibrator reverts to

the ZERO state.

This signal sets the TRA state if SCNOV is 0 and sets flag state if

the flag state set, the program senses the flag state to exit from the read routine.

SCNOV is 1.

With

If TRA was set then

the next sector will be transferred.

2.5.2

Parity Check
As a word is read from the drum, the DATA READ pulse complements the R PARITY flip—flop

(3C4).

The R PARITY is initially set.

drum.

Since odd parity is generated during the write cycle, the R PARITY flip-flop should be in a reset

state after the

sets

The DATA READ pulse occurs only when a l is read from the

12—bit word plus the parity bit are read fr0m the drum.

If not, the DSB INI COND pulse

the PE flip—flop to indicate a parity error.

2.6

PARITY ERROR/DATA ERROR DETECT
A parity error

drum.

(PE), described previously, occurs when a word is incorrectly read-'out of the

A data error (DE) is generated when the computer does not answer a break request before anather

break request is made.

The break request signal sets the ER SYNC flip—flop (4A3).

which occurs during a data break resets the ER SYNC flip—flop.

flip-flop remains set.

If a data break does not occur, this

The next RQ signal is enabled by ER SYNC to setthe data'error flip-flop.

The DRCF (clear flag) instruction generates the IOT 66H

(4A3),

DTA (531), PE

The T2D pulse,

(3C5), and sets IDLE (4A5).

Instruction

pulse that resets the DE flip—flop

DREF loads the condition of PE and DE

into accumulator bits 0 and l, respectively, to permit programmed evaluation of
tion DREF also generates the IOT 6612 pulse, which clears the AC (O'—'AC,

2—15

an error

flag.

Instruc-

4C5) and generates a

RM08 SERIAL DRUM SYSTEM
delayed 6612D (400 ns) pulse which transfers DE to ACT (4A4) PE to ACO (3D5) and the contents of the
sector counter to the accumulator

SC —'———’ AC
0—»5
7 —>II'

The state of the PE and DE flip-flops is

sensed by instruction DRSE and causes a program skip if no error occurs.

This condition of PE(l) +‘ DE(I)

will set SNCOV to terminate a transfer.
In the ON

position, the MAINTENANCE ON/OFF switch (4D2) applies

(I D9F, 4C3) which enables the phase A, phase B, and READ STROBE pulses.
or a

can

PEO'DEO

to the

gate

Detection of a data error

parity error inhibits the clock signals so that all data transfer stops and the contents of all registers

be observed to locate the cause of the error.

In the OFF position the equipment functions normally

and data errors or parity error can be detected via the error flag at the end of a sector transfer.
maintenance SW ON will

The

only operate if the instruction for clearing the error flag is not regenerated

and transfer restarted.

2.7

DRUM TRACK SELECTION CIRCUITS
The drum track selection circuits are shown in Dwg. No. E—RM08-0—2.

are

DTA bits 4 through 7

applied to the Y-selection circuits, and DTA bits 0 through 3 are applied to the X-selection circuits.

The addressed X-selection circuit applies the read and write buses to a set of drum read/write heads.
The addressed Y—selection circuits provide a single return path for the group of read/write heads addressed

by the X selection circuits.

Hence the DTA selects a‘single drum read/write head by the coincidence of

the X— and Y-selection lines.

For example, when

the DTA is clear (DTA

the X0 line select the read/write head that is labeled
written by that read/write head.

"0—778"

The

000000000), the Y0 line and

”0-778" refers to the 64 sectors

Similarly, all other read/write heads are labeled with their track and

sector address.

FIELD LOCKOUT switches are provided so that data can be retained on certain fields to be

available for reading only.

There are 16 FIELD LOCKOUT switches (Figure 4-1).

writing on four drum tracks.

Switch 0 inhibits tracks 0 through 3; switch I inhibits tracks 4 through 7;

Each switch prevents

and, consequently, switch 15 inhibits tracks 74 through 77. The lockout is accomplished as follows.
The DTA4 and DTA5 bits are applied to four decoders (5D5).

through

LO3 is

Each decoder output

LOO

logic I when the bit contents of DTA4 and DTA5 are 00 through II, respectively.

WRITE signal is also an input to the decoders.

LOCKOUT switches as shown in (3Di

The

LO0 through LO3 signals

2D2, 2D3). When switch I is closed,

are

The

applied to the FIELD.

LO0 applies

negative

potential to the X0 selection to prevent writing on the addressed track 0. Similarly, the other seven
switches lock out their‘associated tracks.

2-16

RM08 SERIAL DRUM SYSTEM

2.8

MECHANICAL DESCRIPTION OF
The full

DRUM.

complement of magnetic heads is mounted on the drum in a series of blocks, with a

line of eight heads in each block, and the gaps coplanar at one surface,

mechanical diagram,

(Figure 2-9).

shown in the simplified

The flat surface serves as the pad or slider of a hydrodynamic bearing,

using the boundary layer of air clinging to the rotating drum as a lubricating or self—pressurizing medium.
A single thin strip of spring steel connects each

steel reed serves as a combined motion pivot,

magnetic head/bearing pad to the drum frame. The spring

loading spring, and mounting cantilever.

The action of

this simple mechanical system for placing the magnetic head pad in close proximity to the drum surface
when the drum is at operating speed is illustrated in Figure 2—10.

ADJUSTABLE
STOP

“I

ACTUATING
FORCE
-

MOUNTING BAR
DRUM FRAME

.t \ EFFECTIVE
PIVOT

HYDRODYNAMIC
AIR BEARING

PAD,

WITH

INTEGRAL
MAGNETIC HEADS

SPRING
REED

DRUM
RECORDING
SURFACE

Figure 2-9

Drum Head Mounting

STEEL

POINT

RM08 SERIAL DRUM SYSTEM

ACTUATING
FORCE

SPRlNG
STEEL
GAP

Figure 2—l0

Operating. Position of the Head Pad

The mechanical actuator moves the head into close proximity of
drum is up to speed.

As the drum comes to speed,

closes and sets a time delay relay (red cap).

The

the. drum surface when the

centrifugal switch, mounted on the motor end,

relay energizes in 1.5 min and sets another time delay

relay (yellow cap) which supplies actuating power to the linear motor actuator for 65.
motor

After the linear

pulls in the heads, a holding coil, which is energized from rectified ac, holds in the heads.

l .5-min delay

permits the drum to reach full speed prior to actuation

exceeded because the linear motor has a very short duty

cycle and

The

The 6—5 interval should not be

can

burn out if left energized.

circuit breaker that is thermally actuated by the linear motor current provides ‘further protection for the
motor.

Normal shut down of drum power on any power failure will

instantly raise the heads.

Motor

burnout, although not anticipated, results in speed loss so that the centrifugal switch opens and raises
’

the heads.
A fuse mount, located under the right—hand front corner of the cabinet, contains a switch

that can be used to actuate the heads.

The drum centrifugal switch must be

closed'to operate this switch.

If holding coil fails to hold at the end of the pull-in cyCle, the manual switch must be

opened and closed to restart the cycle.

2.9

POWER SUPPLY AND DISTRIBUTION

(RM08 DRUM SYSTEM)

The 120 Vac for the RM08 Serial Drum is supplied by a lZO-Vac outlet.
the Type 832 Power Control in the RM08 Drum System (refer to Dwg. No.
tacts in

The ac is applied to

D-RM08-O—12). Relay con-

the RM08 Drum 836 Power Control connect terminal 1 to 2 when the relay is energized.

The

relay is energized by -l5V from the PDP-8 power supply (Dwg. No. PW—D-RM08-O—l2 and RS-836).
With the circuit breaker on and the REMOTE/LOCAL switch in the REMOTE position,
to

power is supplied

relay contacts Kl and K2_when the —15V from the PDP—8 computer energizes the relay in the 836

Power Control.

In the LOCAL position,

power is applied to the Kl and K2 relays when the circuit

RM08 SERIAL DRUM SYSTEM

breaker is
ac

the

on.

The K2 contacts enable the fast—on

time

delay relay

K3 which enables the

delayed—off ac power.

delayed—on fast-off

The Kl

contacts

apply

power.

The fast-on delayed—off ac power is applied to the blower fan, drum motor, and the +10V
and -l5V power supply in the Type 779 Power

Supply.

The delayed-on fast-off ac power is applied to

the dual l5‘-V power supply in the Type 779 Power Supply only,

(refer to Dwg. No.

D—RM08-0-

Supply is grounded, and the yellow terminal remains unconnected.

The red terminal of the 779 Power

This provides -30V at the green terminal which is used in the NRZ writer,

read sense amplifier, and the

X— and Y-selection modules.

When power is
to

normalize control

initially applied to the RM08 Drum System, a DDC CLEAR pulse is generated

flip—flops in the drum control circuits. This is accomplished by the Type 440i

module (Dwg. No. D-RM08-0-

) supplying DDC CLEAR pulses to the system. An RC network delays

the -l5V to terminal V of the 440i

module; shortly after the application of poWer, terminal V is suf-

ficiently negative to inhibit the clock pulses, and the drum can function normally.
Tables 2—1 and 2-2 show the analysis of instructionsfor the write and read cycle,

respectively.

These tables provide a reference to detailed signal flow duringga write or read cycle.

Table 2—]
Analysis of Instructions for Write Cycle

»
.

Instruction,
Operation,
or
Signal

Function

DRCW (6605)
IOT 6601

pulse

Generates IOT 660i and 6604 pulses (4C7).

(Via lEllW, (4Bl) Clears, RQ, READ/
WRITE, ER SYNC, DE, and via lCllV

‘

(4A4) sets IDLE.
Generates DDC CLEAR

OVERFLOW,

PAR ERROR (3C4,
IOT 6604 pulse

(484) which clears

R PARITY, WRITE DATA,

3C5).

Transfers AC to DCL (5Bl)

Clears AC
Sets RQ,

(4C5)

WRITE, and ER SYNC (4A2, 4A3).

DATA BREAK CYCLE

DCL to MA signal resets RQ and generates
DRA (4Bl)
DRA increments the DCL

contents(DCLl4-lC6,

5C6) and clears DFB (3A2)
T2A pulse from computer (482) resets ER SYNC
and generates T2D

T2D transfers MB to DFB (3A).

RMO8 SERIAL DRUM SYSTEM

Table 2-l

(continued)
Analysis of Instructions For Write CyCIe
Instruction,

Operation,
or Signal

Function

DRTS (66l5)

Generates IOT 66“ and

IOT 66H

Clears DTA and DSA

pulse

6614 pulses (4C7).

Clears PAR ERROR (3C5)

Clears DE (ICO9—4B3).
IOT 66I4 pulse

Transfers AC to DTA and SA (5C1)

Clears AC (4C5)
Generates TAKE WORD (3C2)

SNR—>SNC

Triggers 200—ps delay (4B5) that sets TRA
H to SNC.

TAKE WORD

Set RQ (4B2)

Generates DSB INI COND (3C3).
DSB INI COND

Clears DSBF (332) and DSBS (3C8)
Generates DFB-—-~DSB (3C3) which sets
DSBS (3C8), and transfers DFB and DSB (3C3).
Generates DSB INI COND + 400 ns which
sets R PARITY.
I

<l>A pulse

Complements WRITE DATA (3C5)
Generates ¢B pulse (4C5).

d>B pulse

Resets OVERFLOW if OVERFLOW

Generates SHIFT pulse if

(3C4)

OVERFLOW=O(3BI)

(Delayed) generates OB+ACT pulse (3D2).
DRSC

(6622)

Generates IOT 6622 pulse which senses the

flag state (4A7).
IOT 6624 pulse

Loads AC10,

AC1} into DFR (21B2), loads

ACO through AC5 into SN register.
Loads AC6 through AC8 into DCLO-2 (5Al ).

IOT 66I2

O-—+AC

Generates 66l2D
6612D loads PE

---.ACO, DE—-->AC],

SC—-———’AC
7—Il'
0—’5

2-20

RM08 SERIAL DRUM SYSTEM

Table 2-2

Analysis of Instruction for Read

Cycle

Instruction,

Operation,
or Signal

Function

DRCR (6603)

Generates IOT 6601 and 6602 pulses (4C7).

IOT 660l

(Via'lEl lW, (4Bl) Clears RQ, READ/WRITE,
ER SYNC, DE and via lCl lV (4A4) setsIDLE

pulse

Generates DDC CLEAR (434) which clears

OVERFLOW, R PARITY, PAR ERROR, WRITE
DATA (3C4, 3C5).
IOT 6602 pulse

_Clears DFB

Transfers AC to DCL

Clears AC.
DRTS (6615)

Generates IOT 661T and 66l4 pulses (4C7).

IOT 66“

Clears DTA and DSA

pulse

Clears PAR ERROR (3C5).
Clears DE (lCO9-4B3).
IOT 66l4 pulse

Transfers AC to DTA and SA (5Cl)

Clears AC (4C5)
Generates DSB INI COND (3C3)
SNRw-‘SNC
After 200 ps sets TRA, and H to SNC

Clears DSB (3C8) and DSBF (3B2)

DSB INI COND

Sets PAR

ERROR if READ

ACT

R PARITY

]

(3C5)
Clears DSBS (3C8)
Generates DSB INI COND + 400 ns which
sets R

PARITY (3C4) and D53”

(3B8).

Generates READ STROBE (4C)

¢A pulse

Generates ¢B pulse (4C8).
'

c.DB pulse

Generates SHIFT PULSE if OVERFLOW

o (331)

Resets OVERFLOW (3C4) if OVFLO(I)

Generates TAKE WORD when OVERFLOW
l

(3C1, 3C2).

2-2l

RM08 SERIAL DRUM SYSTEM

Table 2-2 (continued)

Analysis of Instruction for Read Cycle
Instruction,
Function

Operation,
or Signal
TAKE WORD

Generates DSB INI COND (3C3)
Transfers DSB to DFB during READ (3B2)
Set RQ

DATA BREAK CYCLE

(432).

DCL to MA signal resets RQ and generates
DRA (4Bl)

DRA increments DCL contents (DCLl4—lC6,

5C6)
T2A pulse from computer (482) resets ER

‘

SYNC and generates T2D, T2D clears DFB

(3Al).
T2 generates DFB——" MB (internal to PDP—8)
I

Generates IOT 6622 pulse which senses

DRSC (6622)

FLAG (4A7).
'

DRFS (6624)

Generates IOT 6624 pulse (4C8).

IOT 6624 pulse

Loads ACIOI

ACH into DFR (21 B2), loads

AC0 through AC5 into SN register
Loads

IOT 6612

AC6 through AC8 into DCL 0—2 (5Al).

Same as write cycle.

2—22

RMO8 SERIAL DRUM SYSTEM

CHAPTER3
INTERFACE

All
or

logic signals which pass between the computer and the serial drum are standard

standard DEC pulses.

A standard DEC level is either ground

(0.0V to —O.3V) or nominal —3V.

dard DEC pulses are nominal 2.5V in amplitude (2.3V to 3.0V) and are 0.4 ps in duration

ules).

Positive pulses are referenced to ground

DEC levels
Stan-

(500 kc mod—

(0.0V to +2.5V) and negative pulses are referenced to

ground.
Standard DEC ground potential signals are symbolized by an open diamond

DEC negative signals by a solid diamond (-—.).
an

(--<>) and standard

Standard DEC positive pulses are also represented by

open diamond, and negative pulses by a solid diamond.

The input and output signals of the RMO8 pass through connectors (i F2, lF3,

etc.).

The

connectors, and associated input and output signals are contained on the logic drawings (refer to

Chapter 7).

Refer to the PDP-8 Maintenance Manual for interface information in and out of this unit.

13—]

RM08 SERIAL DRUM SYSTEM

CHAPTER4
INSTALLATION

4.1

AND

OPERATION

SITE REQUIREMENTS
The installation site must provide floor space at least 24 in. wide and 28 in.

date the serial drum.

deep to accommo—

At least 9 in. must be provided in front of the cabinet and IS in. at the back to

allow opening of the doors For maintenance.
Power to the RM08 is Supplied from a Il5 Vac output.

Current drawn from the power source

is 8.0A starting surge and 5.0A running.

The ambient operating temperature recommended is from 70° to 85°F.

4.2

CONTROLS AND INDICATORS

Manual control of the serial drum is accomplished through switches on the switch panel

(Figure 4—I ).

Table 4—1 lists the switches and provides a brief descrition of their functions.

Figure 4—1

Field Lockout Switch Panel

4-1

RM08 SERIAL DRUM SYSTEM

Table 4-1

Controls, Indicators, and Switches for RM08 Serial Drum
Control, Indicator, Switch

Function

MAINT ON/OFF

Allows maintenance personnel to select the normal or stop-

(Field Lockout

on—error

panel)

ment

mode of operation.

In the OFF position the equip—

functions normally and data errors or parity errors can
be detected only by the error flag at the end of a sector

transfer.
error

In the ON

position detection of data error or parity

by the machine inhibits generation of clock signals

(<PA, Read Strobe, and <PB) so that all data transfer stops and
the contents of all registers can be observed to locate the
cause

of the error.

LOCAL/REMOTE

In the REMOTE

(832 Power Control)

the application of power to the serial drum.

position, the PDP—8 computer controls
In the

position, power is supplied to the serial drum.
In both LOCAL and REMOTE positions, the circuit
LOCAL

breaker must be on before power is applied to the serial
drum.

In the OFF position power is turned off from the

serial drum.

ON/OFF
(832 Power Control)

Applies ac power to the serial drum. The ac power is sup—
plied from the computer; therefore, power must be turned
on

the computer before this switch is effective.

FIELD LOCKOUT

Each switch can control the inhibiting of a group of 4 con-

(I6 Switches Field

secutive tracks

Lockout panel)

formation stored on those tracks cannot be accidentally

(4096 words) during writing so that the in-

destroyed.

4.3

INDICATOR PANEL
The indicator panel

lamps (Figure 4—2) provide visual indication of the machine status and

The functions denoted by these

lamps are shown in Table 4—2.

4-2

RMO8 SERIAL DRUM SYSTEM

Figure 4-2

Indicator Panel

Table 4-2
Indicator Panel

Lamps

Indicator

Function

SECTOR NUMBER (6)

Light to indicate 1's in the sector number register.

SECTOR COUNTER (6)

Light to indicate I's in the sector counter.

FINAL BUFFER

Light to indicate I's in the drum final buffer.

(12)

TRACK ADDRESS (8)

Light to indicate I's in the drum track address register".

SECTOR ADDRESS (6)

Light to indicate I's in the drum sector address register.

CORE LOCATION

Light to indicate I's in the drum core location counter.

(15)

RDY

Lights to indicate that the drum is up to speed and ready for transfers.

TRA

Lights to indicate receipt of IOT pulse. It also indicates that the
machine has been taken out of IDLE state and is waiting for clock

pulses to be read from the drum.
is in the correct position before

ACT

FLG

This indicator assures that the drum

Initiating a transfer.

Lights to indicate that the machine has been taken out of the TRA
(transfer) state and is actively engaged in a data transfer.

Lights to indicate that a sector transfer has been completed and the
machine has been taken out of the active state.

The machine remains

in this state until the flag is cleared when the machine is set to either

the IDLE or the TRA state.
IDL

Lights to indicate that the drum is in the IDLE state.

RD/WR

Light to indicate that the machine is In either the read or write mode.

Lights to indicate that a data request signal has been sent to the
computer to request a data break to transfer a word.

4-3

Table 4-2 (cont)
Indicator Panel

Lamps

Indicator

Function

Lights to indicate that the machine has detected a parity error after
read-in From drum to core.

If the MAINT ON/OFF switch is OFF

when a parity error occurs, the drum error flag is set to I; it the
switch is ON, the IDLE state is set and the transfer terminated.
DE

Lights to indicate that the machine has detected a data error, be—
the data request signal from the drum was not answered before
another request was given.
cause

RM08 SERIAL DRUM SYSTEM

CHAPTER5

PROGRAMMING

INSTRUCTIONS

5.]

The operation of the RM08 Serial Drum is controlled by the IOT instructions listed in Table 5—l

Table 5—l

Type RM08 Serial Drum Instructions
Octal

Mnemonic

Code

Symbol

6603

DRCR

Operm'O“
Load the drum core location counter with the core memory

location information in the accumulator.
a

specified core location.*
6605

DRCW

Prepare to read

number of sectors of information from the drum into the
Clears the AC on completion.

Load the drum core location counter with the core memory

location information in the accumulator.
a

Prepare to write

number of sectors of information into the drum from the

specified core location.* Clears the AC.
6611

DRCF

Clear completion flag

66l2

DRES

Load the condition of the parity error and data timing error

and error flag.

flip-flops of the drum control into accumulator bits 0 and l,
respectively, to allow programmed evaluation of an error

66l5

DRTS

flag. Load the condition of the drum sector counter into the
accumulator bits 6——.l l, for program evaluation of the
drum address. First, clears the AC then loads.
Loads the drum address register with the track and sector address held in the accumulator.

Load the contents of the drum
field and sector number register into the drum track register

(DTAo, DTA1) and sector number counter, respectively.
Clear the completion and error flags, and begin a transfer
(reading or writing).*
662T

DRSE

6622

DRSC

Clears the AC.

Skip the next instruction if the error flag is a 0 (no error).

Skip next instruction if the completion flag is a l (sector
transfer is complete).

*The sector,

track, and core memory address are suitably incremented and allow transfer of the next

sequential sector without respecifying addresses up to 64 sectors.

5-l

RM08 SERIAL DRUM SYSTEM

Table 5-l

(continued)

Type RMO8 Serial Drum Instructions
Octal

Mnemonic‘

Operation

Code

Symbol

6624

DRFS

Load the drum field register with the contents of the ac-

cumulator bits l0 and ii

(ACOm, AC0”

Field 0).

Load

the sector number register with the contents of the accum—

ulator, bits 0 through 5, to specify the number of sectors to
Load the three most significant
bits of the drum core location register (DCLO_2) with the
contents of the AC bits 6, 7, 8, to specify the core memory
block to be used during the drum transfer. If the DRFS is
not given before each DRTS instruction, the drum will transfer

be transferred (1 to 1008).M

the field and sector number left in the drum field and sector

number register.
If memory blocks are changed

(4K), then 6624 must be given

before 6605 in order to break to the correct extended memory
block.

**1008= 00
DRUM FORMAT AND PROGRAM TIMING

5.2

Chapter 2 explained the drum format and showed diagrams of the drum format and word format.
A sector transfer begins when the continuously rotating drum reaches the index mark I .2 us before the

beginning of the data in a selected track and sector.
Because the selection of the track read-write head requires 200 ps of stabiliaztion time for
continuous transferring,

new

track must be specified during the first 200 ps of the 300—ps interval.

During transfer, if a data timing or parity error occurs, the track and sector address are not advanced
and operations stop at the conclusion of the sector transfer.
error

This feature allows the program to sense for

conditions and to locate the track and sector where transmission fails.

The drum completion flag is set to l upon completion of a transfer,

causing a program interrupt.

The flag is cleared either by a clear flag (DRCF) or automatically when one of two transfer instructions

(DRTS, DRCN) is given.
The error flag, which should be checked at the completion of each transfer, indicates either
of the following conditions.
a.

period.

A parity error has been detected after reading from drum to core.

The data break request signal from the drum was not answered within the required l6—ps

This condition can occur if other devices with higher priority are connected to the data break

5-2

RM08 SERIAL DRUM SYSTEM

facility. Thus, in reading from the drum the data work stored in core memory is incorrect; in writing) on
the drum, the next word has not been received from the computer.

5.3

PROGRAMMING SUBROUTINES
The following program examples indicate the operation of the drum system in single and mul—

tiple sector transfers.
Subroutine to Transfer (Read) One Sector

(1)

CLA

/Calling sequence

(2)

TAD ADDR

/Initial core memory address

JMS READ

(3)
I

(4)

1000

/lO sectors, memory field 0, drum field

(5)

/Tracl< and sector address

(6)

READ

(7)

DRCR

/DRCW to write

(8)

TAD 1 READ

/Load AC with sector count (ACO-5)

/Memory field (AC6—8), drum field (AC9—ll)
(9)

DRFS

/Load sector counter (any value up to 77),
Load memory field register, and load drum

field register

(10)

ISZ READ

(11)

CLA

(12)

TAD 1 READ

/Load AC with track and sector address

(13)

DRTS

/Load serial drum DTA and start transfer

(14)

DRSC

/Done?

(15)

JMP .—1

/No

(16)

DRSE

/Errors?

(17)

JMP ERR

/Jump to error check routine

(18)

152 READ

(19)

JMP I READ

The first instruction

/Return

(CLA) clears the accumulator so that the core memory starting address of

the data block to be transferred can be loaded into the accumulator by the second instruction

The third instruction is a

iump to subroutine at address READ.

In executing this instruction the contents

of the program counter (which now contains the address of the fourth memory

sixth memory location

(TAD ADDR).

location) are stored in the

(designated READ), the contents of the accumulator are unchanged, and program

control advances to the seventh memory location.

The DRCR instruction is executed to transfer the initial

RM08 SERIAL DRUM SYSTEM

core

memory address from the accumulator into the drum core location counter and to establish the read

status in the drum.

The next instruction TADs indirectly from the READ location.

At this time the READ

location contains the l2-bit address of location four, which was deposited here as the contents of the
program counter during the execution of the third instruction

The DRFS instruction loads the drum with

accumulator with sector number, drum field, and core field.
the sector number, drum field, and core field.

loads it into the AC

Therefore, the TAD instruction loads the

The ISZ READ again increments location READ and then
The DRTS instruction transfers the

This TAD loads the track and sector address.

track and sector information contained in the accumulator into the DTA and DSA registers, clears both
drum flags, and initiates transfer.

The DRSC instruction senses the drum completion flag and increments

the contents of the program counter if the flag is a l

The program advances to instruction l5 which is a

thus indicating that the transfer is not complete

iump back to location l4 to check the flag again.

When the flag indicates that the transfer has been completed, the program advances to the instruction l6
which is the DRSE instruction.

The DRSE instruction senses the error flag and skips the next instruction

if no error has been detected.

If an error has been detected, the error flag is l and the program ad-

vances

the next instruction to transfer program control to the error check routine.

error, the program advances to the ISZ READ instruction.

Finding no drum

The next—to-last instruction is the ISZ at

The READ location contains the address of the track and sector address (location 4).

address READ.

The ISZ instruction increments the contents of READ so that it contains the address of the RETURN to

the main program.

5.4

Therefore, the JMP I READ instruction returns program control to the main program.

FIELD LOCKOUT SWITCHES
The FIELD LOCKOUT switches

it is available for reading only,

associated track addresses.

(Figure 4—1) permit data to be retained on certain tracks where

Turning a LOCKOUT SWITCH to the ON position inhibits writing on its

The octal address inhibited by each switch are shown below.

Address

Switch

Address

0000-377

4000—43 77

0400-777

4400—4777

lOOO-l 377

5000—5377

1400-] 777

l I

5400-5777

6000—63 77

6400-6777

Switch
0

2000-2377

2400—2777

2000-3377

‘

7000—7377
'

5-4

7400-7777

RMO8 SERIAL DRUM SYSTEM

CHAPTERé
MAINTENANCE

Maintenance of the Type RM08 Serial Drum consists of a test and maintenance program

MAIN DEC-O8- D5AA—D,

procedures repeated periodical ly as preventive maintenance, and tasks performed

after equipment malfunction as corrective maintenance.
ment

(or equivalent) listed in Table 6—l

Maintenance activities require use of the equip—

and standard hand tools,

Table 6-]

cleansers, test cables, and probes.

Maintenance Equipment

Equipment

Multimeter

Model

Manufacturer

630-NA/26O

Triplett/Simpson
‘

Tektronix

Oscilloscope
Variable Power

Supply

540 Series
734

DEC
I

System Module Extender*

DEC

I954

System Module Puller*

DEC

I960

Diagnostic Program

DEC

Digital-5-55-M

*One supplied with the equipment

If it is necessary to remove modules,
power before extracting or inserting modules.

use

the Type I960 System Module Puller.

Turn off all

Carefully hook the small flange of the module puller over

the center of the module rim, and gently pull the module from the panel.

Use a straight even pull to

avoid damage to plug connections or twisting of the printed-wiring board.

Since the puller does not

fasten to the module, grasp the rim of the module to prevent it from falling.

To gain access to adjustment controls on the module,

the module, and insert a Type I954 System Module Extender into the

points for signal tracing, remove
proper module slot in the panel,

and then reinsert the module into the extender.

6.I

PREVENTIVE MAINTENANCE
Perform preventive maintenance tasks prior to initial operation of the equipment and period-

ically during its operating life.

Perform these tasks in accordance with a reasonable schedule to discover

progressive deterioration, to correct minor damage, and thus forestall future failure. Compile a log book
to record data found

during the performance of preventive maintenance to indicate the rate of. circuit oper-'

ating deterioration and provide information to determine when components should be replaced.

6-]

RM08 SERIAL DRUM SYSTEM

Preventive maintenance tasks consist of mechanical checks such as cleaning and visual

inspec-

tions, checks of specific circuit elements such as the power supply, clock timing, sense amplifiers, and

magnetic heads, and marginal checks to aggravate borderline conditions or intermittent Failures so that

they can be detected and corrected.

All preventive maintenance tasks should be performed every six

months or 1,000 equipment operating hours, whichever occurs first.

6.] .l

Mechanical Checks
To assure good mechanical operation of the equipment,

perform the following steps and the

indicated corrective action for any substandard conditions that may be found:
a.

Clean the exterior and the interior of the equipment cabinet using a vacuum cleaner

clean cloths moistened in nonflammable solvent.
b.

Clean the air filter at the bottom of the cabinet.

Remove the filter by removing the fan

and its housing which are held in place by two knurled and slotted captive screws.
soapy water,

Wash the filter in

dry in an oven or by spraying with compressed gas, and spray with Filter— Kote (procured

from Research Products Corporation,

Madison, Wisc.).

light machine oil. Wipe off excess oil.

Lubricate door hinges and casters with a

Visually inspect the equipment for completeness and general condition. Repaint any

scratched or corroded areas with DEC blue enamel number 3277—1565.
e.

Inspect all wiring and cables for cuts, breaks, fraying, deterioration, kinks, strain, and

mechanical security.
f.

For mechanical security,

inspect switches, knobs, iacks, connectors, transformers, fan,

capacitors, and lamp assemblies.

6.1 .2

Inspect modules for proper seating in the racks.

Inspect power supply capacitors for leaks, bulges, or discoloration.

Power Supply Checks

Check the output voltage and ripple content of the Type 779 Power Supply.

Check the +lOV

output between the yellow (—) and orange (+) connectors to assure that it is between 9.5V and II .0V with
less than 800 mV ripple.

Check the -l5V and the +l5V outputs (green to yellow and red to yellow,

respectively) to assure that they are between l4.5V and l6.0V with less than 400 mV ripple.
These supplies are not adiustable; thus if the output voltage or ripple content is not within
the tolerance specified, the supply is defective.

6—2

RMO8 SERIAL DRUM SYSTEM

Timing Checks

6.l .3

Using the oscilloscope and referring to Dwg. No. D-RMO8—O-4, check the timing of the

Type 4303 Integrating Single Shots at location lC4, lCl3 and the Type l304 Delay at location lCl5.
If necessary,

adjust the timing of these modules by turning the potentiometer screw which is accessible

through a hole in the handle.
Check the single-shot by observing the l output at lC4W while triggering the oscilloscope on
lC4K.

During each revolution of the drum, the single-shot is triggered every l.2 ps for approximately

l7 ms during data reading and receives no pulses during the 300—ps gap.

should be at ground level during the gap,

The output at terminal lC4W

drop to -3V at the first triggering pulse, and remain at -3V

for 3.4 ps after the last triggering pulse is received before reverting to ground potential.
at

lCl3W should be at CV for 7 ps during the

The output

lO-ps gaps between the 64 sectors and at CV for 300 ps

during the large 300 ps gap. Any other time it should be at ground.
Check the timing of the delay module by observing the negative read strobe pulse at terminal
lClSE while triggering the oscilloscope on the ¢A pulse at lCl4J.

pulses by approximately 0.25 ps.

Observe the read strobe pulses and the amplified output of a magnetic

read head by connecting the second
tant

Read strobe pulses should follow <l>A

input of the dual-trace oscilloscope to terminal lE25S.

that the read strobe pulses occur at the negative peak of the sinusoidal read signal.

It is

impor—

Measurements

should be made using several different heads, and the read strobe pulse should be adjusted for an average
of the measurements to eliminate

6.l .4

large differences in peak playback time.

Drum Sense Amplifier Checks

The Type l537 Drum Sense Amplifier modules at locations lCl

track) are checked for proper slice or threshold level at terminal S.

(clock track) and lE25 (data

This measurement can be made with

the oscilloscope by measwing the amount by which the base line shifts above ground when the signal is
connected to the input. The clock track sense amplifier slice level should be+l00 mV.
sense

The data track

amplifier slice level should be +l50 mV. Adjustment of theslice level can be achieved by turning

the potentiometer screw which is accessible through a hole in the module handle.

6.l .5

Drum Head Mounting Adjustments

Adjustment of the magnetic heads is provided by the stop screw for each pad of heads and its
actuating arm, as shown in Figure 6-1

With this stop screw properly positioned, the actuating arm moves

the pad to a position-where the reed is slightly bent and the pad is tangent to the drum surface at the line
of head gap.
to

These adjustments are made at the factory and under normal circumstances should not have

be changed,

least no more than minor adjustment.

ceed in the following manner.

6—3

Should adjustment be necessary, however, pro—

RMO8 SERIAL DRUM SYSTEM

Connect an oscilloscope to lE25S to observe the preamplifier output for the drum head

in question.

Figure 6-l

lo.

Stop Screw Position

Set the DTA to address the drum head in question.

Drawing No. BS-E—RM08-0-2 shows

the bar and pad location and the octal address of each drum head.
c

Set the drum control status to read.

Using a 5/64 hexagonal for socket heads, adjust the stop screws until a maximum output

is noted on'the oscilloscope as shown in

Figure 6—2.

The adjustment screw is located on the right-hand

side of each bar as one views the drum as shown in Figure 6-1

6-4

RMO8 SERIAL DRUM SYSTEM

2le

L HEAD PAD

RETRACTED

mum

CENTER

E\RV‘ifi §S\E\ \<‘\ E\ \ E
HEADS

APPROACHING

INITIAL

: HYDRODYNAMIC FILM
ROTATING

DRUM

1:?-

HEAD GAP TANGENT,
MAXIMUM SIGNAL
AMPLITUDE

SIGNAL
4.

ADJUST

STOP

AMPLITUDE
BACKED

REDUCED

0F TOO

FAR

Figure 6-2

Operating Positions of Head Pod

6—5

RMO8 SERIAL DRUM SYSTEM

CAUTION

If head adjustment is attempted with diode boards in place,
make sure that the adjustment wrench is placed and/or in—

sultated to prevent shorting connections or components to

ground.
The best method of making this check is to run a program in which the patterns of all Os, all

ls, or alternate ls and 05 are written on the selected track, then read the data and monitor the output
of the selected track.

If data on the selected track is to be retained, it should be read into core memory

before proceeding with this adjustment.

Rewrite the selected track and read the recorded signal after

every adjustment.

6.l .6

Pad Leveling Adjustment

The amplitude of head playback signals
as

among the eight heads in each pad is set

uniformly

possible by using the pad leveling screws which are accessible at the outer surface of each bar, ap-

proximately adjacent to the upper and lower edges of each pad.

This may be checked on head number 0

(sectors 0-77) and 7 (sectors 0—77) (top and bottom heads) with secondary reference to heads 2 and 7.
Clockwise rotation of a pad leveling screw tends to increase signal amplitude at that end of the pad.

Continuously write and read the selected heads always alternating between the two.
6.l .7

Marginal Checks
Marginal checks are performed to aggravate borderline conditions within the logic to reveal

observable faults.
ance

to forestall

Therefore, these conditions can be corrected during scheduled preventive mainten-

possible future equipment failure.

aid to locate marginal

These checks can also be used as a troubleshooting

intermittent components, such as deteriorating transistors.

formed by operating the equipment logic circuits from an external,

The checks are per-

adjustable power source, such as the

DEC Type 734 Variable Power Supply.

Raising the bias voltage above +lOV is equivalent to lowering the amount of base drive on a

particular transistor.
tends to

This in turn simulates a lower gain driving transistor, thus raising the bias voltage

indicate low gain transistors.

Lowering the bias voltage below +lOV simulates a condition where

the voltage drop across the previous driving transistor

VCE drop (leakage) transistors

(VCE) has increased. This tends to indicate high

low gain driving transistors.

The -l5V supply margins are not checked

in the serial drum because to raise or lower the —15V does not affect the majority of control
it is the collector load voltage and is usually clamped to —3V.

The +lOV margin should be about i5V.*

*The 1537 Sense Amplifier, lCl and lE25, has only i2V margins on +lOV(B).

6-6

logic, since

RM08 SERIAL DRUM SYSTEM

By recording the level of bias voltage at which circuits fail, progressive deterioration can be

plotted and expected failure dates predicted. Therefore, these checks provide a means of planned replacement. Marginal checks of the +10 (A) supply (top switch at the left of the rack) to rack E varies
the slice level on the drum sense amplifier modules and therefore is a valuable tool in verifying the

capability of the machine to read and write on the drum surface. Normally increasing the +10 (A) supply
by three or f0ur volts also increases the slice level and causes bits to be dropped out. Decreasing the
+10 (A) source by three or four volts usually lowers the slice level and causes bits to be picked up.

Marginal check terminals are provided on color—coded connectors which are connected in
common

to all

racks, so that an external power supply can be attached to any connector to marginal

check all racks.

The color coding of these connectors from top to bottom is as follows:
1

Green:
Red:

+10 Vdc marginal—check supply

+10 Vdc internal supply

Black:

gr0und

Blue:

—15 Vdc internal supply

Yellow: *—15 Vdc marginal-check supply
Three Single-pole single—throw switches at the end of each rack of logic allow selection of either the

normal internal power Supply or the external

marginal-check power supply for distribution to the logic.

The top switch selects the +10V supply routed to terminal A of all modules in that rock.

In the down

position the fixed internal +10V supply connected to the red terminal is supplied to the modules, and in
the up

position the marginal—check voltage Supplied to the green terminal is supplied to terminal A of

the modules.

The center switch performs the same selection as the top switch for connection of a nominal

+10V level to terminal B of all modules.

minal C of all modules.

The bottom switch selects the —15V Supply to be routed to ter—

In the down position, the fixed -15V output of
the internal power supply, re—

ceived at the blue terminal, is supplied to the modules; while in the up position, the marginal-check

voltage, connected to the yellow terminal,
To perform marginal
0.

is supplied to terminal C of all modules.

checks, use the following procedure.

Connect the external

marginal-check power supply to the colored connectOr on any rack

between the green (+) and the black (ground) terminal.
b.

Energize the marginal—check power supply and adjust the outputs to supply the nominal
‘

+10 Vdc.
c.

Set the top switch on the rack to be checked to the up position.
Start equipment operation in a repetitive pattern or in a routine which fully utilizes

the circuits in the rack
from the

to be tested.

The diagnostic drum program,

MAINDEC-O8-D5AA-D, obtainable

Digital Program Library should be used unless a user has developed a special maintenance program

6—7

RMO8 SERIAL DRUM SYSTEM

Record the

Lower the +IOV marginal-check power supply until normal system operation is interrupted.

mariginal-check voltage. At this pointlmarginal transistors

can

be located and

replaced.

Start equipment operation, then decrease the +IOV marginal—check supply until normal

operation is interrupted.

At this point record the marginal—check voltage.

Transistors can again be

located and replaced.
9.

Stop operation and return the top switch to the down position.

Repeat steps b through 9 for the center switch on the logic rack that is being checked.

Repeat steps b through h for each rack of logic to be checked.

Deenergize and/or disconnect the external marginal-check power supply.

CORRECTIVE MAINTENANCE

6.2

No special test equipment nor tools are required for corrective maintenance other than a broad

bandwidth oscilloscope and a standard multimeter.

understanding of the system logic.

The best corrective maintenance tool is a thorough

Persons responsible for maintenance should become thoroughly familiar

with the system concept and the operation of specific cirCUits as described in Chapter 2; program tech—

niques, described in Chapter 5; the engineering drawings, presented in Chapter 7; and the location of
mechanical and electrical components.

Diagnosis and remedial action for a fault condition is performed in the following phases:
a.

Preliminary investigation to gather all information and to determine the physical-and

electrical security of the system.
b.
tic

System troubleshooting to locate the fault to within a module through the use of diagnos-

programming, signal tracing, or aggravation techniques.
c

6 .2.I

Circuit troubleshooting to locate defective parts within a module.

Repairs to replace or correct the cause of the malfunction.

Validation tests to assure that the fault has been corrected.

Log entry to record pertinent data.

System Troubleshooting
Do not attempt to troubleshoot the drum system without first gathering all information possible
A

concerning the fault, as outlined under Preliminary Investigation.
Cammence troubleshooting by performing that operation in which the malfunction was initially

observed, using the same program. Thoroughly check the program for proper control settings. Careful
checks should be made to assure that the serial drum is actually at fault before continuing corrective
maintenance procedures.

Faults in equipment transmitting or receiving information or improper connections

6—8

RM08 SERIAL DRUM SYSTEM

of the system frequently give indications very similar to those caused by drum malfunction.

From that

portion of the program being performed and the general condition of the indicators, the logical section
of the machine at fault can usually be determined.
'If the fault has been determined to be within the RM08 Serial
to a specific

logic function, perform the diagnostic program procedure.

been narrowed to a

Drum, but cannot be localized
When the location-of a fault has

logic element, continue troubleshooting to locate the defective module or component
If the fault is intermittent,

by means of signal tracing.

form of aggravation test should be employed to

locate the source of the fault.

6.2.] .l

Diagnostic Program

Refer to program number MAINDEC—O8-O5AA-D from the Digital

Program

Library.
6.2.1.2

Signal Tracing

-—

If the fault has been located within a functional

logic element, program the

equipment to repeat some operation in which all functions of that element are utilized.

Use the oscil-

loscope to trace a signal flow through the suspect logic element. Oscilloscope sweep may be synchronized by control signals or clock pulses available at individual module terminals.

Trace the signal from

the output back to its origin.

6.2.] .3

Aggravation Tests

—

Intermittent failures caused by poor wiring connections can often be re—

vealed by vibrating the modules while running a repetitive test cycle.

Often, wiping the handle of a

screwdriver across the back of a suspected row of modules is a useful technique.

By repeatedly starting

the equipment and vibrating fewer and fewer modules, the malfunction can be localized to within one
or

two

modules.

After

isolating the malfunction in this manner, check the seating of the modules in the

connector, check the module connector for wear or misalignment, and check the module wiring for cold
solder joints or wiring kinks.
‘

6.2.2

Circuit Troubleshooting

Where downtime must be kept at a minimum, it is suggested that a provisioning parts program
be adopted to maintain one spare of each module type (Table 6-2) which can be inserted when

system troubleshooting procedures have located the fault to a particular component.
Bench troubleshooting procedures can be performed to correct the defective components.

Where

downtime is not critical, the spare parts list can be reduced and signal tracing techniques can be utilized
to troubleshoot modules within the

equipment. This practice involves module removal by means of a Type

T960 System Module Puller, insertion of a Type l954 System Module Extender into the logic rack, insertion of the suspect module in the module extender, and osiclloscope signal tracing of the module with the

equipment energized and operating.
6-9

RMO8 SERIAL DRUM SYSTEM

Table 6-2

Spare Module List
Module No.

Name

1213

Flip—Flop

1304

Delay (One Shot)

1410

Pulse Generator

1537

Drum Sense

4102

Inverter

4106

Inverter

4112—47

Negative Diode NOR

4113

Negative Diode NOR

4114—74

Negative Diode NOR

4115-17

Positive Diode NOR

4127

Capacitor-Diode Gate

4141-R

Negative AN D-NOR Gates

4215-X

Complementing Flip—Flops

4216

Shift Register

4217

Complementing Flip-Flops

4220-377

Buffer Register

4222—77

Counter Flip-Flops

,4225

Counter Flip-Flops

4301

Delay (One Shot)

4303

Integrating Single Shot

4401

Variable Clock

4529

Drum Writer

4530

Drum X Select

4531

Drum Y Select

4604

Pulse Amplifier

4605

Pulse Amplifier

4606

Pulse Amplifier

6102—145

Inverter

6106-17

Inverter

Amplifier

RMO8 SERIAL DRUM SYSTEM

Table 6-2 (cont.)
Spare Module List
Module No.

Name

6110

Negative Diode NOR

6113

Positive Diode NOR

6115-12

Positive Diode NOR

R107

Inverter

Static and dynamic circuit troubleshooting procedures may be performed at a bench.

Visually

inspect the module on both the component side and the printed-wiring side to check for short circuits in
the etched wiring and for damaged components.

confirm a fault condition observed,

use

.If this inspection fails to reveal the cause of trouble or

the multimeter to measure resistances.

CAUTION

Do not use the lowest or highest resistance ranges of
the multimeter when checking semiconductor devices.

The X10 range is suggested.

Failure to heed this warning
in
result
to
may
damage
components.

Do not attempt to measure resistance of

any clock
The voltage applied to the test probes is sufficient
to erase information from the drum surface.

head.

MeasUre the forward and reverse resistances of diodes. 'Diodes should measure approximately
20 ohms forward and more than 1000 ohms reverse.

If readings in each directionore the same and no

parallel paths exist, replace the diodes.
Measure the emitter-collector and emitter-base resistance of transistors.

Most catastrophic

failures are due to short circuits between the collector and the emitter or due to an open circuit in the
base-emitter path.
emitter.

A good transistor indicates an open circuit in both directions between collector and

Normally 50 to 100 ohms exist between the emitter and the base or between the collector and

the base in the forward direction, and open-circuit conditions exist in the reverse directions.
mine forward and reverse directions,

To deter—

transistor can be considered as two diodes connected back-to-back.

.6-11

RM08 SERIAL DRUM SYSTEM

In this analogy PNP transistors are considered to have both cathodes connected together to form the base
and both the emitter and collector assume the Function of an anode.
sumed to be a common—anode

In NPN transistors, the base is as-

connection and both the emitter and collector

are

assumed to be the cathode.

Multimeter polarity must be checked before measuring resistances, since many meters (including the

Triplett 630) apply a positive voltage to the common lead when in the resistance mode.

Note that al-

though incorrect resistance readings are a sure indication that a transistor is defective, correct readings
give no guarantee that the transistor is functioning properly. More reliable indication of diode or transistor malfunction is obtained through the use of one of the many inexpensive in-circuit testers commercially

available.

Damage or cold—solder connections can also be located using the multimeter.
meter to the
or

lowest resistance range and connect it across the suspected connection.

Set the multi-

Poke at the wires

components around the connection, or alternately rap the module lightly on a wooden surface, and

multimeter for open—circuit indications.
Often the response time of the multimeter is too slow to detect the rapid transients produced

observe the

by intermittent connections.

Current interruptions of very short duration, caused by an intermittent

connection, can be detected by connecting a 1 .5V flashlight battery in series with a i500—ohm resistor
across

the suspected connection.

Observe the

voltage

across

the i500—ohm resistor with an oscilloscope

while probing the connection.

Dynamic bench testing of modules can be performed through the use of special equipment.

Type 922 Test Power Cable and either a Type 722 or Type 756 Power Supply can be used to energize a
system module.
as

These supplies provide both the +10 Vdc and -l5 Vdc operating supplies for the module

well as ground and —3V sources which may be used as signal inputs.

nected to any terminal
on

the power cable.

6.2.3

inputs can be con-

normally supplied by logic level by means of eyelets provided on a Jones plug

Type 91] Patch Cords may be used to make these connections on the Jones plug.

In this manner logic operations and voltage measurements can be made.

Power Supply,

The signal

When using the Type 765 Bench

marginal checks of an individual module can also be obtained.

Repair
In all soldering and unsoldering operations in the repair and replacement of parts, avoid place—

ment of excessive

solder or flux on adjacent parts or service lines.

When soldering semiconductor devices

(transistors, crystal diodes, and metallic rectifiers) which may be damaged by heat, the special precautions that follow should be taken.
a.

Use a heat sink, such as a pair of pliers, to grip the lead between the device and the

joint being soldered.

RM08 SERIAL DRUM SYSTEM

Use a 6V soldering iron with an isolation transformer.

Use the smallest soldering iron

adequate for the work.
c.

Perform the soldering operation in the shortest possible time to prevent damage to the

component and delamination of the module etched wiring.
When any part of the equipment is removed for repair and replacement, make sure that all leads or wires
which are unsoldered,

otherwise disconnected,

their respective terminals

6.2.4

are

legibly tagged or marked for identification with

Head Pad Replacement

This replacement should be performed only by qualified personnel.

To replace the head pads,

the tools that are listed below are required.
a

Surface plate (at least 3 ft by 2 ft)

Two 2—inch machinists'

Aligning pin, VRC (Vermont Research Corp.) part no. 59P7

Steel Scale,

Height comparator with 0.000, 050 inch calibration (or finer), with less than 5 gram

contact pressure.

parallels

l/32-inch calibrations

The "Electroprobe” manufactured by Federal Products, Providence, R.I., is suggested.

Adjustable height gage, 3- to 4—in. micrometer caliper

Replacement of the head pad must be done with the head mounting bar removed from the drum.
This is done by removing the four socket head cap screws at the ends of the bar,

disconnecting the matrix

wiring, and setting the head mounting bar on the two parallels on the Surface plate.
the

Place the bar with

bearing surface of the pads upward and the stop adjusting screws accessible at the edge of the surface

plate.
Remove the head pad by removing screws at the pad and those holding the leads with a strain

relief and the associated connector.

Insert the new pad,

bending the leads gently. Replace all screws.

Check polarization of connector locating pins (which also serve as mounting screws) to ensure proper

mating with the other half. Before tightening head pad mounting screws, insert the aligning pin through
the corresponding hole in the bar and up into the aligning hole in the loose pad.
Insert aligning pin into the pad carefully,

making sure that no leads are caught at the pin hole.

With the pin in place, scale the distance from each end of the pad to the reed mount and adjust'the parallel within l/64 inch.

Tighten pad mounting screws and recheck parallelism.

pin and proceed to height adjustment.

Remove the aligning

RMO8 SERIAL DRUM SYSTEM

Using housing flat—to-drum dimensions and the required drop allowance, measure the thickness
of the bar and parallels in use and calculate the height setting for the height gage as follows.

Housing—to—Drum Dimension

Drop Allowance

Required Bar-to—Head Dimension

Required Bar-to-Head Pad Dimension + Parallel Thickness + Bar Thickness
Setting

Height Gate

Set the height gate to size using the micrometer caliper; then use the height gage to set the
comparator to zero or center range.
actuated position.

Rotate the actuator link and allow the head pad to move into

Using a hexagonal wrench in the corresponding stop screw, lower the pad being

adjusted until the height comparator reads approximately zero at the center of the pad.
tion of the entire pad.

Check eleva—

Using the two differential pad leveling screws between the read mount and bar,

and the stop screw for overall elevation, set the pad level within 0.0001 in.

(leading to the trailing

edge) and 0.0002 in. (end to end).
Replace the bar on the drum housing. Replace all matrix boards and wiring.

Monitor the

output signal from the replaced head pad (as described previously for head pad adjustment) while letting
this pad approach the recording surface for the first time.
actuator to move the

pad into "flying position,

As the stop screw is moved out, allowing the

compare output levels on heads 1 and 8

(top and bottom)

Balance these levels with :th% with the differential screw adjustment at partial output

in the pad.

levels; then move the stop screw out father until the ”peaking" process (described under Head Adjustment)
is complete.

Validation Test

6.2.5

Following the replacement of any electrical component of the equipment, a test should be
performed to assure the correction of the fault condition and to make any adjustments of timing or signal
levels caused by the replacement.
most

This test should be taken from the preventive maintenance procedure

applicable to the portion of the system in which the error was found.

For example, if a filter ca—

pacitor was replaced in the proper supply, the ripple check for that power supply should be repeated as

specified under Power Supply Checks.

If repairs or replacements are made in an area which is not

checked during preventive maintenance,the diagnostic program should be run or an appropriate operational
test should

be devised.

For example, if a flip—flop is repaired or replaced, the register or control func—

tion performed by the flip-flop should be checked in entirety by manually setting and clearing, by programmed exercise of the function, or by repeating the diagnostic program.

6.2.6

Log Entry
Corrective maintenance activities are not completed until they are recorded in the maintenance

log.

Record all data indicating the symptoms given by the fault, the method of fault detection, the com—

ponent at fault, and any comments which would be helpful in maintaining the equipment in the future.
6-14

RMO8 SERIAL DRUM SYSTEM

CHAPTER7
ENGINEERING

DRAWINGS

This chapter contains reduced copies of the DEC engineering prints on the Type RMO8 Serial
Drum.

Only those drawings are included which are essential and are not available in the referenced

documents that are pertinent to this system are included.

7.1

DRAWING NUMBERS
DEC engineering drawing numbers contain five groups of information separated by hyphens.

For example,

drawing number BS-D—RMO8—O-4 includes the information that follows.

BS
D

RMO8
0
4

—

type of drawing

original drawing size
equipment type
manufacturing series of the equipment
drawing number within the series

The drawing types are listed below:

BS, block schematic or logic diagram
CD, cable diagram
CL, cable list
CS, circuit schematic diagram
FD, flow diagram
ID, interconnection diagram
MA, mechanical assembly diagram
ML, module location diagram
PW, power wiring diagram
RS, replacement schematic diagram
SD, system diagram
TD, timing diagram
TFD, timing and flow diagram
TSL, terminal strip location diagram
UML, utilization module list
WD, wiring diagram
WL, wiring list
WS, wiring sheet

7.2

CIRCUIT SYMBOLS
The block schematics of DEC equipment are multipurpose drawings that combine signal

logical function, circuit type and physical location, wiring, and other pertinent information.
circuits are shown in block,

flow,

Individual

semi-block form, with special Symbols that define the circuit operation.

These symbols are defined in the FLIP CHIP Modules Catalog and the

Systems Module Catalog.

DTA 50
DTAGO
DTA70

DTA5

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DTA7'

DTA50

DTABI
DTA7O

DTASO

DTAG:
DTA7

DTA5'

453I

DTAGO

IEI3

DTA7

Y 4

DTAsg
DTAG |
DTA 7

DTA 5 I

DTAe
DTA7

[

DTA5l
DTAG'

DTA7'
DTA

DTA 6

DTA 7

DTA5°

DTA60
DTA7I

DTA5?

DTAeO

DTA 7

DTA50I
DTAe

DTA7'
DT A5

‘

mueg
DTA7

Elmo

Y|4

DTA5l

DTAeo
DTA7|
DTASl
DTAG'
DTA7

DTASI

DTAGI
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Mariano

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107

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1C99H

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