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DEC-08-HIEA-D

December 1970

137 pages

Original

8.1MB

Document:	RF08 PrelimMaintMan
Order Number:	DEC-08-HIEA-D
Revision:
Pages:	137
Original Filename:	https://svn.so-much-stuff.com/svn/trunk/pdp8/src/dec/dec-08-hie/dec-08-hiea-d.pdf

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Maintenance Manual

IISKCONTROL

RF08
AND RSOBDISK

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Preliminary Printing, January I970
2nd Printing (Rev) June I970

The material in this manual is for informa—

tion purposes and is subject to change without notice.

The following are trademarks of Digital

Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONTENTS

Page
CHAPTER I

GENERAL DESCRIPTION

1 .I

Introduction

1-1

I .2

Specifications

1-1

CHAPTER 2

INSTALLATION

2 .I

Introduction

2 .2

Requirements

2.2.]

Unpacking the R508 Disk

2 .2 .2

Disk Motor Power

2.2.3

Logic Power

2.2.4

Ground Circuits

2.2.5

Connection of RF08 to Central Processor

2.2.6

Connection of RF08 to R508

2.2.7

Connecting the Purging Blowers

2.3

Activating the Disk

2 .4

Periodic Maintenance

CHAPTER 3

PRINCIPLES OF OPERATION

3 .I

Introduction

3.2

R508 Functional

3.2.]

Timing Tracks

3.2.2

Disk Selection

3.2.3

Track Selection

3.2.4

Write Lock Out

3.2.5

Writing Data

3.2.6

Reading Data

3.2.7

R508 Logical Functions

3.3

RF08 Functional

3 .3 .1

Address

3 .3 .2

Memory Buffer Registers

3 .3 .3

Address Control

3 .3 .4

Data Control

3.3.5

Timing Control

3 .3 .6

Input/Output Control

Description

Registers

CO NTE NTS

(Cont)
Page

wwwww

RF08 Logic Description

3-13

Address Selection

3-13

Writing Data on the Disk

3-19

.5.1

General Discussion

3-19

.5.2

Logic Flow in Writing Mode

3-21

Reading Data from the Disk

3-22

Data Flow When Reading

3-23

.6.2

Operation at the End of an Address Track

3-25

O\ o.)

End of Data Transfer

3-26

U1-Pt-P
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1..

CHAPTER 4

OPERATION AND PROGRAMMING

4.1

Introduction

4.2

Table of Instructions

4—1

4.3

Address Configuration

4—3

4.4

Writing Data on the Disk

4—4

4.5

Reading Data from the Disk

4-5

4.6

Status Register

4—5

4.6.1

Photocell Sync Mark (PCA)

4-5

4.6.2

Data Request Enable

(DRE)

4-6

4.6.3

Write Lock Selected

(WLS)

4-6

4.6.4

Error Interrupt Enable

(EIE)

4—6

4.6.5

Photocell Interrupt Enable (PIE)

4—6

4.6.6

Completion Interrupt Enable (CIE)

4-6

4.6.7

Core Memory Extension Field

4-6

4.6.8

Data Request Late

(DRL)

4-6

4.6.9

Nonexistent Disk

(NXD)

4-6

4.6.10

Parity Error (PER)

4-7

4.7

Data Transfer Involving Two Disks

4—7

4.8

Overflow of Disk Capacity

4—7

4.9

Programming Differences Between RF08/R308 and DF32

4-7

4.10

Instruction and Data Transfer Execution Times

4-8

4.10.1

IOT Execution

4-8

4.10.2

Data Transfer

4-9

4.10.3

Data Break

4-9

4.10.4

Reliability

Priority

4—9

CO NTENTS

(Cont)
Page

CHAPTER 5

MAINTENANCE

5.]

Introduction

5.2

Test

5.3

Timing Tracks and Data Track Timing

5.3.1

Timing Track Gain Adjustment

5.4

Timing Track Slice Adjustment

5.5

Guard Band and PCA Adjustment

5.6

Data Track Gain

5.7

Preliminary Data Track Slice Adjustment

5.8

Data Gating Adjustment

5.8.1

TASD Adjustment

5.8.2

DC WIND Adjustment

5.8.3

DC DATA Adjustment

5.8.4

DC COP Optimization

5.8.5

Final Slice Adjustment

5.8.6

Additional Adjustments

(AGC Equalization)

MODULE CIRCUIT SC HEMATICS

CHAPTER 6

6.1

Equipment

Introduction

APPENDIX A

REFERENCE DOCUMENTS

APPENDIX B

DISK

APPENDIX C

LOADING PROCEDURE

APPENDIX D

RFO8 SIGNAL MNEMONICS

APPENDIX E

TIMING TRACK WRITER

I/O PROGRAMMING EXAMPLE

ILLUSTRATIO NS
RSO8 Read/Write Logic
RSOBM Disk
Dc Power Wiring

Diagram

Power and Motor Control Circuit Schematic

120 Vac 60 Hz Schematic Diagram
705-8 Power Supply

Diagram

ILLUSTRATIONS

(Cont)

RF08 to PDP-8/PDP-8/I Interconnection Cable Diagram
RF08 to R508 Interconnection Cable Diagram
R508 Block Diagram

Circular Timing Diagram

Selected Write Head Simplified Diagram

Writing Current Pulse Diagram
Disk Address and Data Track Timing Diagram
RF08 Disk Control Block

Diagram

Address Selection Simplified Block
Address Flow
Write Flow

Diagram

3-10

Simplified Diagram, Writing Data on the Disk

3-11

Data Flow When Reading

3-12

DMAR Read Flow Diagram
Write Lockout Switch

Diagram

EMA and DMA Transfer Diagram

Analog Slice Waveform Diagram
Diode Gate 3133

Diode Gate Bl34
Diode Gate BI35
Diode Gate B137
Diode Inverter 3165

Dual RS

Flip-Flop 8212

Delay Line B310
Tapped Delay Line 33“
Variable Delay Line BBIZ
Pulse Amplifier 86“

500 OR Bus Driver B683
Diode Gate 5123

Flip-Flop $202

6-10

Triple Flip- Flop 5203

6-10

Flip-Flop 5206

6-H

Dual

Device Selector W103

6-12

Binary-To-Octal Decoder BI52

6-13

ILL USTRATIO NS

(Cont)
Page

6-18

Diode Gate BT72

6-14

6-19

(Dne-Shot Delay B301

6-14

6—20

Disk Read Amp and Slice G085

6-15

6-21

Disk Writer G284

6-16

6—22

Series Switch (3285

6-16

6-23

Centertap Selector C3286

6-17

6-24

Diode Cluster R002

6-17

6-25

Diode Gate RlTl

6-18

6—26

Delay R302

6-18

6—27

Integrating One-Shot R303

6-19

6—28

Input Output Control

6-21

6-29

Timing Control

6—23

6—30

Address Control

6-25

6—31

Data Control

6-27

6-32

Status Register

6-29

6-33

Disk Memory Address

6-31

6-34

Extended Memory Address

6-33

6—35

Disk Memory Butter

6-35

6—36

Memory Butter Hold

6-37

Track C3enerator

6-39

6—38

Timing Control

6-41

6-39

Wired Assembly

6—43

6—40

Data Control

6-45

6-41

Automatic Gain Control

6-47

6-42

Head Matrix

6-49

6—43

Head Matrix

6-51

6-44

Timing Track Writer

6-53

6—45

Memory Address

6-55

6-46

Writer and Head Amplifiers

6-57

6-47

Timing Control

6-59

vii

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RF08 Disk Control and R508 Disk

(Rock Mounted, Front View)

Chapter 1
General Description

1.1

INTRODUCTION

The RF08 Disk Control and the R508 Disk (see Frontispiece) combine to provide high—speed bulk storage for
DEC PDP-8,

PDP-8/I, PDP-8/L, LINC-8 and PDP—12 computers.

Each R508 Disk has a storage capacity of

2048 words on each of 128 tracks, giving a total storage capacity of 262, 144 words.
bits of data,

plus a 13th bit for read parity checking.

four R508 Disks (see Figure

Each word contains 12

The RF08 Disk Control (see Figure 1—1) controls up to

1-2) giving the disk file a maximum storage capacity of 1,048,576 words.

The disk file operates under program control of the associated compatible computer and uses the three-cycle
data break facility of the computer.

While operation is identical with any central processor, all references in

this manual are to the PDP-8 central processor.

The length of a data block is variable and is specified by
the word count (WC) register.

loading the word length as a negative number into

The length of a single block is limited only by the maximum number of words

(4096) that can be specified in a 12-bit register.
The starting address for a data transfer can be selected randomly.
transferred sequentially to or from the disk.

which can be from l to 4096 words.
dress (CA) register.
transferred

Address

The initial instruction (to read or write) executes the block transfer,

The first address to be useditfor data transfer is placed in the current ad-

As the block transfer proceeds, the current address register is incremented, and data is

sequentially to or from a block of consecutive memory addresses.

77508 is permanently assigned

address register.

1.2

The data words in the data block are then

the word count register in the PDP-8; address

77518 is the current

When the disk is addressed, these memory locations are selected automatically.

SPECIFICATIONS

Specifications for the RF08 and R508 Disk File system are summarized in Table 1-1.

1-1

”g"? ”s

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Figure 1—]

R508 Read/\Nri’re

Logic

(Logic Modules and Write—Lockou’r Swi’rches)

Figure 1-2

RSO8M Disk

1—2

(Wi’rh Cover Removed)

“

RF08

and

Table l-l

R508 Disk File System

Summary of Specifications

Four R5085 can be controlled by one RF08 to provide storage For up

Disks

Storage Capacity

l,048,576 words.

Each R508 stores 262, M4 l3-bit words (l2 data bits plus l even

parity bit).

Memory Locations Used

Word Count

7750

775T8 Current Address
(SO-Hz Power

50-Hz Power

Data Transfer Rate

l6.0 ps per word

l9.2 ps per word

Minimum Access Time

258 ps

320 ps

Average Access Time

l6.9 ms

20.3 ms

Maximum Access Time

33.6 ms

40.3 ms

Program Interrupt

33 ms clock flag
Data transmission complete Flag
Error flag

Write Lockout Switches

Eight switches per R508 are capable of locking out any combination
16,384 word blocks in address 0 to 131,071.

of eight
Data Tracks

128

Words Per Track

2048

Recording Method

NRZI

Density

ll00 bpi

Timing Tracks

Three, plus three spare (spares can be used to recover data on disk).

Operating Environment

Disk Operating:

(maximum)

Recommended temperature 60° to

in temperature not to exceed i20°F/hr.

80%.
can

Maximum wet bulb,

l00°F; a change

Relative humidity 8% to

78°F; no condensation (storage or operating)

be allowed.

Disk Stopped:

Relative humidity 0 to 55 %, no condensation.

Temperature range 0° to l20°F.

Vibration/Shock

Adequate isolation is provided to prevent data errors.
CAUTION
Extreme vibrations should be avoided while the R508 is
tra nsFe rri ng

Heat Dissipation

Power

Requirements

(Logic Only)

RFO8:

l5OW

R508:

300W

information

ll5/230 Vac i 10%, single phase, 50 i 2 Hz or 60 i 2 Hz, 5A (maximum)
For logic power.
NOTE

Logic power For one RF08 and up to four R5085 is provided
by one DEC Type 705B power supply. Additional line cur—
rent is required for the R508 disk motor, shown as Follows.

1—3

Table l-l

(Cont)

RF08 and R508 Disk File System Summary of Specifications

R508 Motor Power

Motor Start:

5.5A for 20 i 35

Requirements

Motor Run:

4A continuous @ ll5 Vac.

A stepdown autotransformer

is provided for 230 Vac operation.

Line Frequency Stability

Maximum line Frequency drift 0.l

generator set or static

ac/ac

Hz/s.

A constant frequency motor-

inverter should be provided for installa-

tion with unstable power sources.

Motor Bearing Life

Expected operating life of at least 20,000 hours, under standard computer operating environment.

Reliability

Five recoverable errors and one nonrecoverable error in l

transferred.

l010 bits

A recoverable error is defined as an error that occurs

only once in four successive reads.

All other errors are nonrecoverable.

NOTE
On—off cycling of the R508 is not recommended.

For

this reason, the R508 motor control operates independ-

ently of the computer power control.
Cabinet

A DEC cabinet is designed to accommodate one

R5085 and a power supply.
in a second cabinet.

RF08, up to two

Two additional R5085 can be mounted

Other equipment should not be mounted in disk

cabinets.

Shipping Information

Weight of an RF08, one R508, a power supply and cabinet:
590 lb
500 lb

(crated)
(uncrated)

Weight of an RF08, two R5085, a power supply and cabinet:
690 lb

(crated)

600 lb (uncrated)

(The RF08/R508 are shipped mounted in cabinets.)

Chapter 2
Installation

INTRODUCTIO N

2 .l

The RF08 and R508 mount in a standard DEC cabinet Type H950 using "Chassis—Track” slides (part number

C-300-S—20).
are

to be

Installations with one or two R508 Disks require a single cabinet; however, if three of four disks

installed, a second cabinet is required.

A single power supply, Model 705B, supplies power to all

logic circuits.

Each disk is a sealed unit that contains the drive motor,

for the heads.

A separate chassis for each disk contains the R508 Logic and Motor Control.

disk, heads, and electrical networks

CAUTION

The R508M Disk Assembly MUST NOT be opened in the
field by personnel other than authorized DEC Field

Engineers.

Special procedures, alignment and adjust-

fixtures, and cleaning equipment is required to
service the disk. Any attempt to remove the recording
ment

surface by inexperienced or untrained personnel will

invariably destroy the surface of the disk. Any unauthorized openings of the RSO8M Disk Assembly will
void all warranties applying to the unit.

RE QUIREMENTS

2.2

For disk file power requirements see Figures 2-l ,

2-2, and 2—3.

3—wire, pigtail line cord for North American installations.
are

2.2. l

The disk system is supplied with a 25 ft, 30A,

Table 2—l

specifies the Hubble connectors which

be attached to the line cord.

Unpacking the R508 Disk

Before proceeding with the following unpacking instructions, it is recommended that the cabinet front dress

panel be removed and the rear door opened for easy access to the components.

2—l

Unpacking Instructions:
Procedure

Step

Remove the silver cloth tape From around the Disk drive motor protection pan

and then remove the pan and the bag oF Drierite desiccant.

Unwrap the Disk drive motor leads (blue, green, yellow, red, and black)

From around the motor.

Connect the drive motor color—coded wires oF Step 2 to the indicated color-

coded connections on the back of the R508 Disk motor control chassis.
Remove the drive motor lock located on the drive motor shaFt.

Turn the drive motor control switches on the back oF the R508 motor control

chassis to the OFF position.
Switch the H7l8 power supply line Filter circuit breaker to OFF.

2.2.2

Disk Motor Power

The Disk motor operates From a 105 to 130 Vac, 60 Hz 2‘: 2 Hz power bus (50 Hz, 230 Vac on special order).
Because oF synchronous drive motor characteristics, the maximum rate oF ac power source Frequency driFt must
not exceed

0.1

Hz/s.

Line transients exceeding the operating voltage limits will

regulating the power supply voltage.

require site provisions For

Disk motor power must be supplied From an unswitched bus.

Table 2—l

Primary Power Connectors
(North American Installations Only)
Line Voltage (Single Phase)

2.2.3

Hubbell Connector Part Number

ll5V

60 Hz

30A

333l—6 or 333i

230V

60 Hz

20A

none

supplied

ll5V

50 Hz

30A

none-

supplied

230V

50 Hz

20A

3321—6 or 3321

Logic Power

The logic power supply should be connected to the central processor switched power bus.

The power supply

(see Figure 2-4) has suFFicient capacity to power one RF08 Disk Control and Four R508 Disks. This power supply
must not

be used to supply power to other units.

transFer reliability.

Noise generated on the power supply buses could aFFect data

2 .2.4

Ground Circuits

The cabinet containing the disk file must be grounded by mechanical connection to the central processor.

All

grounds must be connected to a common ground point to prevent circulating currents in the ground circuits. All

grounds must be installed before connecting the unit to the ac power mains, to prevent possible damage to the

logic circuits.

Connection of RF08 to Central Processor

2.2.5

Figure 2—5 shows proper cable connections between the RF08 Disk Control and the central processor and proper
termination techniques at the time of installation.

Cables should be routed away from ac power lines and from

other data cables that might introduce noise.

2.2.6

Connection of RF08 to R508

The cable interconnections between the RF08 Disk Control and R508 Disk for installations with one to four R508
Disks is shown in Figure 2—6.

Cables must be routed to allow the R508 Disk

Logic Chassis to be pulled all the

way out without damaging the cables.

Connecting the Purging Blowers

2.2.7

Set the H7l8 power supply line filter circuit breaker to ON.

POWER TO THE DISK DRIVE MOTOR MUST NOT

BE ON.

NOTE

The purge unit hose has not been connected at this point;

therefore, turning the Disk power on purges the purge unit
prior to making connection to the disk unit. This purging
should be performed for at least one half hour.
After the purging period, remove the Disk unit purge cap and connect the purge unit hose to it.

2.3

ACTIVATING THE DISK

The following sequence shows the proper procedure for activating the disk.
Procedure

Step
l

Remove the disk drive motor shaft locks from each R508M Disk in the system

and check for loose wires.
2

Turn the H7l8A Power Line Filter ON

(the switch is located in the bottom rear
lamp is illuminated, indi—

part of the RF08 Cabinet) and observe that the pilot

cating that power is available at the output of H7l8A.

Procedure

Step

Turn the DISK POWER switch ON

lighting the START and OPERATE lamps.

This switch is located in the rear of the R308 Disk Logic Chassis.
NOTE

The disk is inoperable while the START lamp is lit.

Power

transients, caused when the DISK POWER switch is operated, can cause data errors if another disk in the system
is operating and transferring data.

Make certain the disk is running and that its blower is operating.
After 20 sec, the START lamp will go out; this indicates the acceleration run
is complete, and the disk motor has switched to run power.

2.4

Repeat Steps I through 5 above for other disks.

PERIODIC MAINTENANCE

The air filters in the disk purging system are the only items that require periodic service or replacement.
disk is located in a particularly dirty area, or close to a line printer,

If the

frequent service may be necessary;

however, for the average office environment, the following service schedule should be followed.

Monthly Service:
Vacuum the polyethyrene foam prefilter, located in the bottom front of the disk cabinet.

top of the disk cabinet should be inspected and cleaned as required.

The cabinet filter on

Both operations can be performed while

the system is operating.

Six Month Service:
Turn off each disk at its power control
on

panel and disconnect disk and logic power by tripping the circuit breaker

the H7l8A Power Line Filter and on the computer system.

Perform the Monthly Service.

Additional Six Month Service:
The procedure below is followed for additional six month service.
Procedure

Step
I

Remove the foam prefilter screening and retainer, then remove the foam element.
Wash the foam in warm water and detergent, rinse thoroughly and set it aside
to

dry.

Remove the hoses from the absolute filter system (top aluminum cover).
the eight cover screws, lift and discard the absolute filter.

Remove

Procedure

Step

Replace the absolute Filters with DEC P/N l2—09388 Filters. CareFully shake
loose material that may be lodged on the Filter.

out any

NOTE

DO NOT blow oFF dust From the new Filter with an air hose,
since this may puncture the Filter media

CareFully lower the new Filter into place, making certain the Foam gasket Faces
upward.

Replace the top aluminum cover and tighten the hold down screws.

Reinstall

the Foam preFilter.
It is necessary to let the Filter purge itselF beFore reconnecting disk hoses.
Turn on the system power and H7l8A power. The blower is now operational.

Allow the blower to run For at least 30 minutes beFore reconnecting the hoses.
Reconnect the hoses and purge the disk File For an additional 30 minutes.
Restart each disk system.

2—5

s
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Chapter 3
Principles of Operation

3 .l

INTRODUCTIO N

The description in this chapter refers to the operation of one R508 Disk.
with control

The RF08 Disk Control is provided

logic for addressing up to four R5085. The disks are connected in parallel to the data address lines.

Each additional disk has a modified decoding card which decodes the addresses supplied by bits 7 and 8 of the
Extended Memory Address (EMA).

3.2

All other functions are identical when extra disks are installed.

R508 FUNCTIONAL DESCRIPTION

The R508 contains a storage disk, read/write data heads, a data write driver, timing track amplifiers, and data
recovery electronics.

Except for head selection, all data transfers between the R508 and RF08 are serial binary.

Head selection is in parallel binary.

Figure 3-l shows the organization of the R508; while Figure 3-2 is a

circular timing diagram of the address tracks.
NOTE

Appendix B contains a typical RF08/R508 I/O routine.

3.2.]

Timing Tracks

There are three timing tracks which are written permanently on the disk and detected by three independent read

amplifiers.

A set of complete spare tracks is also provided.

lock with the primary set of tracks.
set of tracks is

These tracks are written on the disk in exact phase—

Thus, data written on the disk can be recovered in the event the primary

lost by accidental erasure or component failure.

When switching to spare tracks, the timing track

amplifiers must first be adjusted before attempting to recover data.
CAUTION
An ohmmeter should never be used to test the timing tracks.

Connection of an ohmmeter to the disk heads will erase the

prerecorded timing tracks. Extreme care must be used when
making oscilloscope measurements near the timing track connector, since even a momentary short to the ground of these
pins will erase the timing tracks.

13-]

NXD

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The R508 has no circuitry for writing new timing tracks; a separate track writer (RSO8TA) is used for this

purpose.

The timing tracks (see Figure 3-2) are identified in Sections 3.2. I. I, 3.2. I .2, and 3.2. l.3.

3.2. I .I

Track A, Strobe-Clock Track

address.

The output of this track is used to strobe all of the serial data and address operations in the RF08 and

the R508.

This track contains thirteen ls followed by a single 0 for each angular

Track A provides the clock rate for the disk:

II60 ns (60 Hz) between bits.

The 13th bit provides

for an even parity check; while the I4th bit-time provides a gap to permit the user to turn off/on the write

amplifier.

3.2. I .2

The I4th bit—time is not provided with a TAP to prevent data transfer between data words.

Track B,

est order bit

Binary Address Track

Binary addresses are written sequentially around this track. The low-

is read off Track B first, and the highest order bit is read last.

This sequence allows the disk memory

address logic in the RFO8 to increment the DMA register by performing a serial add of
read and compared.

dress is written.
next

word—time.

plus one as the address is

The binary address is placed one word before the actual location in which data for that ad-

This placement allows the disk file to locate an angular address and begin data transfer in the
An extra address, shown as a special address, has

3—2

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Figure 3—2

NUMBER

REV.

Raga—fl—O

DIST.[TJ]f[I[

Circular Timing Diagram

3-3

address is sensed by the RF08 to instruct the disk file to switch to the next higher track.

A 550 i 50 p5 head

switching gap is provided to allow this switching to occur. The data for address 3777 8 is written during the

special address word period; therefore, no data is recorded during address time 00008.

3.2. l.3

Track C, Word—End Track

contain binary Os.

Track C contains binary is at bit—times l2 and 14; all other bit—times

These bits (binary ls and Os) indicate the boundaries of a data word.

time 12 appears as BTCS- and the binary l at bit-time l4 appears as BTCS+.

The binary l at bit—

These signals are separated in the

R508 to allow them to control separate word-end functions in the RF08.

3 2. 2
.

Disk Selection

EMA bits 7 and 8 are used to select one of the four disks that can be installed with the RF08.

When only one

disk is installed, it is always designated as disk 0.

A select level from the disk select circuit inhibits the reading of the address track and the reading and writing
of data, except when a disk has been selected by EMA bits 7 and 8.

When more than one R508 is installed, the address tracks of the units not selected must be disabled.

logic

signal from the disk select circuit enables the recognition of the address tracks for the selected disk only.

The

enabled signals are then placed on a negative (—3V) OR bus between the R508 and the RF08.

3 .2.3

Track Selection

Extended memory bits 0 through 6 select the disk head using an X-Y diode matrix selector scheme.

Identical

paths are used for reading and writing of data on the disk.
The selection of the X diode matrix uses EMA bits 0, l, 2 and 6 to select 1 of 16 data lines which connect to
the G286 Center-Tap Selector Modules.
a

A selected center—tap is connected to the +20 Vdc power supply through

saturated transistor; while the unselected center-taps are connected to the —15 Vdc power supply through a

resistor.

The G285 Series Switch Module is used to select one of eight Y line pairs.
a

The selected series switch enables

pair of transistors to pass the differential read or write signals. Only at the coincidence of a selected Y line

pair and X center-tap are the head diodes biased into conduction.
read from or written on at a time.

Therefore, only T of the l28 tracks can be

The outputs of the eight series switches are bused to permit the use of a single

read and a single write amplifier.

3-5

3.2.4

Write Lock Out

Any of the eight Y lines can be locked out from writing when bit 6 of the EMA address is 0, thus, allowing the
addresses for the lower half of the disk

(addresses 0 to 3777778) to be locked out in blocks of 400008 words.

The lockout circuits are controlled by toggle switches on the R508 unit.
circuits are inhibited.

If a locked-out track is selected by the program,

When EMA bit 6 is a l, the lockout
a

logic level is sent to the RF08 to

enable setting of the appropriate flags.

3.2.5

Writing Data

The data head selected by the EMA to write data is
described in Section 3.2.3.

_PHANTOM

CENTER'TAP

The output from the

write amplifier is connected to the same point as the

input to the read amplifier, permitting use of the
same

R 1
750a

signal paths for reading or writing.

" /°

7500'1%

5Q,33}J.H
W

"phantom center—tap" (see Figure 3-3) is used to

select the direction of the write current through the
SELECTED

head.

The value of resistors RT and R2 is large com—

pared to the resistance of the selected head.
-

(ONE

HEAD
C

128)

When
\__.___—— To

pomt A IS connected to +20 Vdc through a center—tap

SERIES

SW IT C H

_._._.__—/
08

selector, the head is enabled for writing.

0409

Writing is

accomplished by connecting point B or C (one at a
time) to -l5 Vdc through the write amplifier. When
reading,

current of

Figure 3_3

approximately 5 mA with good

Selected Write Head

Simplified Diagram

balance, flows from points B and C.
The resistance of the head is low (5 ohms); thus, equal current flows in R] and R2 under steady state conditions. For

example, if point B is connected to -l5 Vdc (with point C floating)approximately 45 mA flows through the head
windings. When point C is at -l5 Vdc (point B is floating) approximately 45 mA flows in the opposite direction.
Saturation magnetic recording is used; thus, either polarity current is flowing when writing.

Previously re-

corded data are always erased during writing.

The NRZI recording technique is used in the R308 Disk.

A binary l is represented by a change in the direction

of the magnetic flux along the disk track, and a binary 0 is represented by no change in magnetic flux.

binary l is written by reversing the direction of write current in the head.
The Write Flip-Flop (WFF) is used in the R508 Disk to determine the polarity of the write current.
in magnetic flux represents a binary

l, the WFF circuit is toggled to write a 1 (see Figure 3-4).
3—6

Since a

change

3.2.6

Reading Data

DATA
0

When data on a track is to be read, the write drivers
are

disabled by a

ure

3-5 represents the output signals

logic signal from the RFO8. Fig-

CLOCK

from the selected

l
I

head.
to

Head selection for the read mode is identical

CURRENT

Because the

I
I

READ
SIGNAL

magnetic head can respond only to a change in mag-

flux, an output appears only when a binary l is

written.

lines, are supplied to an am—

plifier and amplitude detection circuit.

netic

WRITE +

the write mode; however, the output signals, which

appear on the Y select

I
I

08_O408

The output voltage from the selected head

Figure 3'4

is proportional to the time derivative of the magnetic

flux in the head.

Because of the

Writing Current Pulse Diagram

recording surface and

head parameters, the output approximates the shape of a cosine squared (bell) pulse.

A binary 0 is indicated

for no output signal because the magnetic flux on the disk is not altered when writing a binary 0.

R508 Logical Functions

3.2.7

In addition to converting digital write signals into current in the appropriate head and analog—to—digital

version of data and timing track read signals, the R508 performs

logical functions on the recovered data.

con—

These

logical functions are described in the following subparagraphs.

3.2.7.l

Timing Signals

The C5085 Read Amplifier (see Figure 6-38) amplifies the head signals and converts

them into digital form through use of a threshold detector.

available.

For Track A

Separate positive and negative threshold outputs are

(bit-strobe track) only timing information is useful; therefore, the 6085 outputs are
For Track B (address track) the address track data is inverted to an NRZ

ORed for use in the R508 and RFO8.

data output for transmission to the RF08 by the Track B Hold (TBH) flip-flop.

from Track C (word-end track) are used for separate

The negative and positive outputs

logical functions in the RFO8. Thus, the TC BTCS- and

TC BTCS+ signals are transmitted directly to the RFO8.

3.2.7.2
tween

Origin Gap Pulse (PCA)

address

The origin gap pulse indicates that the selected disk is at its original (be—

37778 and 00008) position. As the disk revolves, Track

integrating one-shot set to 50 us.
recovers

A is continuously retriggering an R303

However, 50 ps after the end of the Track A pulses, the triggering one—shot

and triggers the R302 one-shot which produces the 100 ps flag, thus indicating the completion of a

disk revolution.

WRITE

COMPLEMENTS
FOR 1

PARITY

DATA

76538

1
1

aURTTPg’TFEF

\STROBED

;

250nseCV

TAP IS
AFTER TRACK B

A
ll

TIMING
FOR RF/RS

TRACK B
ADDRESS

1247 8

:
'

1I
:
1

11'

:4.
A1

If
1

0
TB 5 IS

n sec

AFTER TAP

STROBEDV

‘54

TRACK C

‘

‘1

‘

l
l

CLEARED
BY TAP

31d

MAGNETIC SIGNALS SHOW
FLUX (BIDIRECTION WRITTEN
ON THE DISK SURFACE.

TBH

THE

TRACK C PULSE
IS 500 nsec AFTER
TRACK B 250 n sec
AFTER

TRACK A

BIT

1
1

‘

‘F- T?’
10

‘

;
I

NO TAP
AT BIT 14

‘

TAP

TB5=1 SETS
TBHALGO

‘Fi

BTBH
ADDRESS
BITS

1
1

‘

TAP BIT

11L

PARITY ALWAYS
LEAVES WRITE
FF SET.

;

TRACK A

l
1

TAP D 250nsec
AFTER TAP

WR'T'NG

EVEN PARITY
SHOWN

“1

DATA ON

DISK

‘

MAGNETIC

’

IS LOWEST

BIT 13 PARITY
BIT 14 IS WORD END

‘

1
1
1

BTCS+

ADDRESS AND DATA ARE:
WRITTEN LOWEST ORDER
BIT FIRST.

1
1

‘

BTICS—

V
08—0250

Figure 3-5

3.2.7.3

Data vs Timing Skew Circuits

Disk Address and Data Track Timing

Due to differences in electromagnetic parameters and dynamic runout

of the disk surface, timing skew between data and timing signals is possible.

permit skew of up to 160% of the bit cell.

by two of the one-shots.

Diagram

Three B301 one-shots are used to

The data and timing pulses are converted to standardized pulse widths

A third one—shot changes the position of the timing window (DC WIND);

consequently,

the standard pulses (DC DATA and DC WIND) overlap.

The DC WIND pulse is adjusted to permit the earliest and latest DC DATA pulses to overlap by "the same amount.
The pulses are ANDed to set the MBI register and also to indicate a data I has been read (see
Figure 6-40).
MBI is transmitted to the RF08 as the serial read data.

The Track A timing pulses clear MBI at the end of each data cell.

parity of the data word to be computed.

If MBI clears, PAR is toggled to permit the

PAR is cleared for each word

(see Figure 6-40).

Because data is written in even parity, PAR must be cleared at the end of each Word if no error has occurred.

3.2.7.4

RF08/R508 Bus

—

The bus is terminated in the RF08 and the last RSO8.

terminations at each end of the cables;

such as track select

consequently, signals

are

High-speed signals have IOOQ

propagated without reflections.

Slow signals,

lines, are terminated through a resistor (to +IOV) in the RF08 and 1000 (to ground) in the

last R508.

3—8

With a positive to -3V swing,

3.3

acceptable noise margins are maintained on the track select signals.

RF08 FUNCTIONAL DESCRIPTION

A general discussion oF the RF08 circuits is Followed by a detailed discussion oF the Functions oF the RF08
(see

Figure 3-6).

3.3. I

Address Registers

The RF08 has two address registers which contain separate program instructions.
lowest order ll bits oF the address which corresponds to the addresses (0000

The DMA register contains the

37778) recorded

track.

The address loaded into the DMA is compared by a bit

RF08.

The comparison is accomplished by shiFting the address through the DMA and

transFer.

the RF08

comparator in the address control section oF the

bit in the DMA with the bits oF the address being read oFF the disk.
For this Function.

comparing the lowest order

The timing control provides timing signals

When the angular address is located, a signal is sent to the data control to allow inFormation

During inFormation transFer, the address in the DMA is incremented by l Following each data-word

transFer. At the end oF data transFer, the DMA contains the address oF the last data word

transFerred; this address

can be read
by the PDP—8.

The EMA is loaded by a separate command From the PDP—8, except For the lowest order bit, which is loaded
with the highest order bit oF the DMA address.
must be

Because the 20—bit address capability oF the disk File system

loaded From the 12—bit PDP-8 accumulator, two address transFers are required.

Bits 7 and 8 oF the EMA

select one oF Four disks that can be controlled by the RF08, and bits 0 through 6 select the head in that disk

(track number) that is to be used For data transFer.
The EMA register is a 9-bit binary ripple counter, which can be cleared and loaded with a parallel iam transFer.

3.3.2

Memory BuFFer Registers

There are two memory buFFer registers in the RF08: MBH and DMB.
loaded with data From the PDP—8 Memory BuFFer.
the DMB.

During the write mode, the MBH is parallel

The contents oF the MBH are then transFerred in parallel to

During the read mode, the MBH is loaded with data transFerred in parallel From the DMB.

tents oF MBH are

then transFerred in parallel to the PDP-8.

The con—

Because the DMB register is continuously performing

serial-to-parallel read or parallel-to-serial write conversions, two registers are required For each data word.
Since only the bit-time

(l 160 ns) between words is available to load the DMB with data From the PDP-8, the

MBH is required to buFFer that data.

3-9

DATA

FROM

8MB (WRITE)

DATA TO DMB (WRITE)
BUFFER

DATA TO BMB (READ)

HOLD

(MBH)
DATA BREAK REQUEST

‘

DATA TO BIT I FROM DISKIBMBII
MEMORY
BUFFER

WLMBHP
RLMBHP

(DBR)

SDMBP

ADDRESS ACCEPTED(ADD ACC)

DATA COMPLETION FLAG

(DCF)

DATA
CONTROL

WEP

(DC)

BTCS

WORD COUNT OVERFLow (WCO)

ADC
A DDR E 5 S FROM AC

‘

ADDRESS TO Ac

(DMB)

5323's???
ADDRESS

DEP

—>DISK AND TRACK SELECT TO DISK(S)

SAD
TAP

HSE

FROM DISK

BTCS+

FROM DISK

TAP FROM [“5"

(TC)

BWEP TO DISK

TCP

(EMA)

BTCS—
TIMING
CONTROL

SDMAP

PUP-8
OR
POP-BI

I
DISK
MEMORY
ADDRESS

IDMAE TO BITI

BTBH ADDRESS BIT FROM DISK

ADDRESS
CONTROL

BITII CONTENTS

(AC)

(DMA)

STATUS TO Ac

01—8

INTERRUPT ENABLE

—BAC‘

STATUS

ERRORS FROM DISK

INTERRUPT

PER
DRL

WLS
HSE

IOT COMMANDS FROM BMB

INPUT /OUTPUT
‘

CLEAR AC

SKIP

CONTROL

-—) IOT COMMANDS TO ALL BLOCKS
SYNC MARK FROM DISK

NON-EXISTENT DISK (NXD) FROM DISK

POWER CLEAR
KEY

BIT SERIAL

-—-——-é

BIT PARALLEL

——-—>

CONTROL

SINGLE BIT
08’0251

Figure 3-6

RF08 Disk ConfroI BIock

Diagram

When a word transfer is complete, the next data word is parallel transferred into the DMB from the MBH when

writing, or out of the DMB to the MBH when reading.
When writing, the data in the lowest order bit (DMB H) is written on the disk.
data are shifted down one bit, and the new bit in DMB H is written.

After the bit is written, the

After 12 shifts, the data have been

shifted completely through the DMB, a clear signal clears the DMB flip-flops, and another parallel transfer of
data from the MBH occurs.

When reading, the bit read from the disk is loaded into DMB 0.
other bit is loaded into DMB 0.

This bit is then shifted down one bit and an—

The lowest order bit is written onto the disk first, causing the first bit read to

be in DMB ll after all l2 bits are read.

Data are then transferred in parallel to the MBH.

transfer is used to transfer data from DMB to MBH when in the read mode.

A double rail

iam

Signals from the data control deter—

mine the direction of transfer and also the timing at BTCS+.

Address Control

3 3 3
.

The address control compares the address read from the disk address track with the address loaded into the DMA.
When the address in the DMA has been
data transfer to begin.

located, the address control generates an ADC logic level which allows

After each word of data is written, the address control generates a DEP; the DEP is used

by the data control as an end—of-word strobe signal

The address control increments by l the address in the

DMA, using a serial add during each word following a DEP.

Therefore, the DMA is incremented by the number

of data words transferred.

The address control also provides an HSE signal which increments the contents of the EMA after the last address

(37778) is read from the address track of the disk. This allows data transfer to continue, using the next head
the disk
0000

(or the next disk when the last address on a disk has been reached). The address in the DMA is reset to

after data has been transferred to or from the last angular address on the track.

The origin gap in the timing tracks is long enough to permit

"spiral

read and write operations.

While reading,

the amplifier recovers from the track switching overload during the origin gap.
In multiple disk installations, the rotational positions of the disks are not synchronized and a normal rotational

positioning latency occurs when spiralling between disks. The overflow from the most significant EMA bit
(AC bit 4) resets the synchronizing logic for automatic disk switching.
the transfer continues after the ADC flip-flop is set.

A normal address search is initiated and

Data Control

3.3.4

The data control is instructed, by decoded IOT instructions,

to control

either the writing or reading of data

When address control supplies an ADC signal, indicating that the angular address has been located, the data

control is enabled to control data transfer between the disk and memory buffers as described in Section 3.3.2.
Data transfers, within the RFO8,

occur

control are strobed by the DEP flip—flop.
is strobed by the Tl

the end of a data word.

Data transfers received from the address

In the write mode, the MBH

timing signal from the PDP-8.

The PDP-8 supplies a WCO pulse during the last programmed transfer.
sets the

DCF flip-flop.

3 3 5

Timing Control

The WCO pulse ends data transfer and

The timing pulses from disk Tracks A and C are converted to clock signals in the RF08.

The Track A pulse is a

strobe for address search and data transfer and occurs in the first 13 of the T4 bit—times.

Track C pulses signify

the end of a data word and are transmitted on two separate lines.
The TAP is used to shift the address through the DMA register.
DMA contents until the contents of bit H
to

generate SDMAP.

occurs

at bit-time

data word

are

A delay is provided that prevents shifting the

set-up by the address control.

The next ll TAP pulses are used

After the end of the llth shift, the circuit is reset by the Track C pulse (BTCS-), which

12.

Resetting the circuit delays generation of the SDMAP for the first and last A pulse in a

When the address confirmed signal is received from the address control, the TAP pulses are used to produce the

SDMBP.

These pulses are produced as long as data are transferred to or from the disk.

There are 13 SDMAP

pulses developed for each data word; however, the l3th pulse has no affect on data loaded into the DMB,
because of the information transfer timing between the MBH and DMB.

Two separate Track C pulses are provided by the disk:

establish a WDE signal.
times.

the first, BTCS- occurs at bit-time 12 and is used to

This signal appears as a pulse and is used to present data transfer for the last two bit-

The second pulse, BTCS+, occurs at bit—time i4, and in addition to ending the WDE hold-off period,

develops the TCP and WEP.

This pulse is used by other sections of the RF08 and by the R508 to signify the end

of a data word.

3.3.6

Input/Output Control

The RF08 is controlled by IOT instructions received from the PDP-8.
Device Selection Modules in the

input/output control.

These instructions are decoded by the W103

The octal device codes assigned to the RF08 Disk Control

3-12

are

The IOP lines are used to specify the operations.

608, 6T8, 628, and 648.

Note that microprogramming

of IOP lines is used for IOTs such as read (DMAR:6603) and write (DMAW:6605).

The decoded IOT instructions are gated with conditions in the RF08 and BMB lines to provide control pulses.

3.4

RFO8 LOGIC DESCRIPTION

Address Selection

3.4.]

Address selection is divided between track selection and angular addressing (see Figure 3—7).

address is located by the DMA and the address control circuits.
a

7-bit bus to the R508.

Section 3.2.1).

Track selection is performed by the EMA over

Bits 7 and 8 of the EMA select the disk in multiple—disk installations.

Locating a Track Address

3.4. l .l

The angular

Three timing tracks are permanently recorded on the disk (refer to

An ll-bit starting address is loaded from the PDP-8 address control into the DMA by the

DMAR or DMAW command at IOP time 2 or 4.

When a DRE signal is generated by the input/output control,

the address control begins to compare the bits in the DMA with the bits read off Track B on the disk.
is a flow diagram of address comparison for track addresses

address

37778 is followed by

Figure 3-8

(address 0000 8 to 37778). The special case where

"special address" causes a head switch (see Figure 3-9). Figure 3—8 shows the

sequence of events that follows:

a .

A DMAR (6603) or DMAW (6605) is placed in the MB of the PDP—8.

Either signal generates IOT 602
IOT 604 in the RF08. Either IOT generates a LDMAP, which loads the contents of AC bits I
through ll into DMA bits I through ll. Note that the content of AC bit 0 is loaded into the EMA
bit 0 at the same time; however, the EMA is not involved with track address selection.

The DRE flip—flop is set by either of two signals.

If the disk is passing through the head switching

gap, the LDMAP sets DRE. If the disk is positioned on an address, MRS is set by LDMAP. The
4—bit time counter (TCA, TCB, TCC, TCD) receives WEP (derived from BTCS+) to count to T610

and reset to 00008 (setting the DRE).

The waiting time is provided as a settling time for DMA logic.

Once set, DRE remains set until all the data words have been transferred, or until the last word on

the disk has been used.
c.

When DRE is set at the end of a Word, an enabling level is provided to allow the next TAP to set
the SAD flip—flop. SAD is set by the first TAP pulse, and address search begins at the beginning
of an address word.

The first address bits appear at the address control as BTBH and TBH. The contents of DMA ll are
ANDed with the state of the ACH. ACH is set, resulting in the generation of true IDMAE and

IDMAE—, which represents the contents of DMA bit ll.

The IDMAE levels and TBH levels are conindicating that BTBH and DMA ll
contain complements, ABC is set, indicating that the bits do not compare. ABC was cleared by
WEPD before address comparison began and remains clear if the exclusive OR is not true.
nected to an exclusive OR gate.

If the exclusive OR is true,

because it is generated at bit—time 14 by BTCS+. The
The second TAP pulse is ANDed with SAD (which is not set)
to generate the SDMAP. The contents of the DMA are shifted one bit to the right. At the same
time, the state of IDMAE is placed in DMA bit I. This places the contents of DMA bit ll into DMA
bit I; the result being rotation of the address in the DMA.
For the first bit comparison, TCP is not true

ACH flip-flop has been previously set.

3-13

SELECT
________________

A
fl

EXTENDED

‘

R508

I—

0,1,2 ,3

HEAD SELECT

AMDEDIREFSYS

T0 PDP8

EMA7,8

84A:

CONTROL

DRE

EMAI—S

6—II

SELECTOR

WRITE

MATRIX

HEAD

TAP Tcp

EMAO

BAC

FROM

'HT

ADDRESS

fi__
,

SWAP

’VI‘S

I
I

I BTCS

TRACKC BITS

I
I

HEAD

ADDRESS

I
,

IOT 602,

I
L

I
I

________

ADDRESS

DMH‘”

T0 PDPa

‘

(STROBES)

‘

T0 DMA,

DMAI—II

pr8

IOMAE

BHC

DISK

‘

604,624

MEMORY

BTAS TRACK A BITS

(END OF WORD)

IIOT 6O2I

________

?
HSE

BACO

READ/

TIMING

I——I

HEAD

SDMAP

BAG

I
I
I_

as“

CONTROL
'

w
(ADDRESS)

ADC

PEP

BTCS

I.'

604,624

DATA

——-————§ RLMBHP
T0 MEMORY

CONTROL

BUFFER HOLD
BMB

BM 3—H

DRE

FROM PDP
IOP

CONTROL

I0P1,2,4

FROM PDP
ALL
LINE
NOT SHOWN
ARE TO BE SHOWN AS
OR SINGLE
PULSE"
z.

BIT

—> BIT
“a

OTHERWISE

”CONTROL

SERIAL

PARALLEL

CONTROL OR
SINGLE PULSE
08-0255

Figure 3-7

Address SeIecI'ion Simplified BIock

Diagram

The new content of DMA bit ll generates a new IDMAE, and the process returns to point i on the
Flow chart.
The last address bit occurs at bit-time 12.

This address bit is Followed by BTCS-, which resets SAD
WDE is set, resetting SAD and inhibiting the

and causes a branch at point 2 on the flow chart.

generation of SDMAP until the First TAP pulse appears aFter SAD is reset (at the beginning of the
next word). The first and thirteenth TAP pulses are prevented from generating SDMAP pulses.
h.

ADC is cleared when the DRE has been cleared.

DRE is now set, allowing the state of the ABC
flip-flop to be strobed by the 13th TAP pulse. IF ABC is set, the address has not been located,
since at least one bit of the DMA was the complement of the associated BTBH bit. In this case, the
first bit of the next address Word is compared with the contents of DMA H, and SAD is set by the
First TAP pulse oF the next address word. Another comparison of H bits takes place, and the process
branches again, checking to see if ABC was set.

When the track address (corresponding to the address in the DMA) is read, the ABC is clear at bit-

The 13th TAP pulse strobes a set command into the ADC. This enables a data transfer to
begin, starting with the next word. The process continues to point 1 on the Flow chart and continues
shiFting the contents of the DMA through one address word, until BTCS- is true again. The ADC is
set on the last word; the Track C pulse derived From BTCS+ at bit—time T4 to strobe the generation
of a Data End Pulse (DEP) is then enabled.
time T3.

DEP resets ACH and the process returns to point 1 of the flow chart. When point 3 is reached,
IDMAE is the complement of DMA bit ll. When SDMAP rotates the contents of the DMA, the

complement of DMA H is placed in DMA l. The process returns to point 1 of the flow chart aFter
(l) is placed in DMA l as a binary 0. When the content oF DMA H is binary O,
ACH is set by SDMAP. Because of the propagation delay, a binary l is written into DMA l. The
process returns to point i, and the remaining SDMAP shifts place the contents of DMA it into
each DMA H

DMA l.

Because the address is read off with the lowest order bit First, the effect is to add one

count to

the DMA

After the lost data word is transferred, DRE is cleared by DCF.

This clears ADC and also inhibits

setting SAD. ABC is reset, and ACH remains set. The address control is now ready For a new address
comparison when IOT 602 or 604 is generated. At the end of the data transfer, the DMA register
contains either the last address used (For a read operation) or the last address used plus one (For a
write operation).

3.4.1 .2

Operation oF the EMA

The EMA register is used to hold the two bits used to select a disk and the

high-order six bits of the track select. The least significant track select bit is bit 0 of the DMA.

Note that

the indicator panel shows the EMA and DMA differently than they are actually implemented in the hardware.

Referring to Figure 4-2, note that the boundaries of the hardware registers are different than the PDP-8 word
boundaries, also the EMA Flip-Flop is named according to the binary weight.
dicator panel is bit

For example, EMA 9 on the in-

23 in the EMA register and is named EMA 3 (see Figure 6-34).

Numbering the DMA flip-

Flop is consistent with the PDP-8 scheme.

The EMA operates as a binary counter and is incremented once each time a head switch enable occurs.

output of the EMA is parallel binary to the disks.

The

GENERATE
601

IOT

DMA

CLEAR

I
GENERATE
IOT

602 OR

604

GENERATE

LDMAP

NO
WAIT
END

DATA

WORDS

TRANSFER

CLEAR

ABC

m
DRE
SET

SET

SAD

SET

DRE

YES

ADC

IS
ACH
SET

N0
INVERT

DMAE

YES

S IDMA
EXCLUSNE
OR WITH
BTBH

YES

RESET

SAD

YES

?
”0

SET

ABC

IS
SAD
SET

?
YES

GENERATE

GENERATE
N0

DEP

SDMAP,
ROTATE
1

CLEAR

DMA

RmHT

YES

ACH

GENERATE SDMAP
IS
DMA11
o

SHIFT
”0

Figure 3—8

OF DMA 11

DMA
YES

SET

DMA,1 RIGHT,

PLACE COMPLEMENT

ACH

Address Flow Diagram

3-16

3.4. l .3

Head Switch Enable (HSE)

The last address on a data track is address

address is provided, called a special address.

the disk.

37778.

One more timing

Figure 3-2 shows the format of this special address recorded on

The location of the special address corresponds to the location of data for address

data word is written during the word time following the associated address.

angular address operation, in that it increments the EMA by one count.

37778, because

Head—switch operation differs from

A head—switching gap is provided

immediately after incrementing to allow 550 ps for the electronic logic to respond to the new head address.
The DMA is complemented to

00008 by addign

provision is made for resetting the DMA to 0.

one

count to the

Note that the two highest order bits

determine which of the four possible disks is to be addressed.

logic switches to the next higher disk.
switch.
are

last angular address

(37778); therefore,

(bits 26 and 27) of the EMA

If the current disk is filled, the head—switching

EMA bit 6 is complemented from binary l to binary O to signify this

Reentry into the data transfer loop is slightly different when a new disk is addressed. These differences

described in Section 3.4.1.4.

Figure 3—2 shows the logic flow for the track switching sequence described

below.

a .

At the beginning of address word 37778, the DMA register contains 37768.

Note that the contents

of the DMA register follow the disk address location by 1 count, and the DMA is incremented by
adding l to its contents, not by referring to the address read from the disk. During address 37778,

the H SDMAP pulses are generated, adding 1 count to the contents of the DMA.

At the end of address word 37778, the DEP clears the ACH flip—flop.

The contents of the DMA are

binary ls, except for DMA H, which is binary 0. During the next address (special address), an—
other ] is added to the DMA, leaving all is in the DMA at the end of this address. Data for address
37778 are written during the special address time, and a DEP is generated at the end of special
address, which clears the ACH flip-flop.
c.

At the end of the special address, the ACH flip-flop is clear,

inverting the contents of DMA ii.
The DMA thus contains all binary ls. The ABC flip-flop is set, because the contents of the DMA
did not compare with the track address. (This condition holds true for every address following the

address which compares and sets the ADC flip-flop.)

At the end of the special address, BTCS- goes true at bit-time
at

the special address contains address

tains a binary

l).

generate the TEP.
e.

12, setting WDE.

The address track

l0,0008 (all binary Os, except at bit—time 13, which con—

Binary l causes BTBH to go true at bit-time l3.

BTBH is ANDed with WDE to

WDE is reset by BTCS+ at bit-time T4 in the normal manner.

The TEP pulse is used as a set pulse at the HSE flip—flop. This pulse is gated by a level at the flipFor the level to be true, ADC and WCO must be set, indicating that a data transfer has oc—
curred, and that words remain to be transferred. If these conditions are met, HSE is set. The output
of HSE (l) generates an enabling level to reset ADC. However, ADC is not reset until the DEP pulse
is generated at bit-time l4. Clearing ADC prevents data transfer. When ADC is reset, a pulse is

flop.

sent to reset HSE.

EMA O is complemented by a set HSE.

Complementing EMA 0 adds a l to the contents of the EMA

Bits 0 through 6 of the EMA select the head used to read or write on the disk; adding 1 to

the EMA instructs the disk to move to the next track.

For a head switch on the same disk, EMA

bit 7 and 8 are not changed.
9.

Following the special address is a head-switching gap of approximately 550 ps. The gap is provided
to allow the head-selection matrix in the R508 to settle before attempting data transfer. A switchinggap gate (PCA) is generated in the R508 and used in the disk switching function only.

GENERATE

NOTES:
1.2
2

DMAW
5

ARE

BIT WRITING
AT

ADC

AND

DATA BREAK

LOOP STARTS
CONTINUES AS
SET

LONG

AT IOP I
GENERATE
SCLP 1. AND

BSCLP

I
AT [OP 4

GENERATE
WAIT

CDMBP,LDMAP
CLEAR WCS,
SET MRS.DBR,R/W

16 WORDS

SET DRE

IS
ADDRESS
ACCEPTED

LOCATE
TRACK

ADDRESS

YES

SET

DBR
RESET
B

DBR

BREAK

AND T1

SET Aoc

GENERATE
WTE

l
AT

ADC

BREAK

To GENERATE

LDMBP

GENERATE
AT NEXT

CMBHP

TCP, GENERATE

l
SET

DEP

AT T1

DCF

CLEAR DRE .ADc

GENERATE
WLMBHP

ADD1 T0

DMA,NEXT
END OF
IS

Gggg;

[

LDMBP

SET HSE

ABC

CLEAR

] I

ADC

END OF

TRANSFER

ADD 1 To

EMA,SWITCH

(9/

HEADS

END OF

TRANSFER
GENERATE

GENERATE

SDMBP

CDMBP

WITH TAP

WAS NXD
FLAG

SET

JUMP To

ILLEGAL
PROGRAM
HALTS AT
STROBE

SET WFF

w1=1=

WITH TAP D

COMPLEMENT

YES

WFF

Figure 3-9

Write Flow Diagram

3-18

CD AND (9

At the end of the switching gap, address 00008, with its associated TAP pulses and BTCS pulses,
is read. To continue data transfer, this address must be confirmed, and ADC set. The contents of
the DMA are 37778 (all binary Is), and the ACH flip-flop is clear. The ACH and DMA II are

exclusively ORed to form IDMAE— which effectively inverts all Is in the DMA to Os. Each BTBH (O)
is compared with the IDMAE- signal which appears at the exclusive OR gate as 05. DMA II will
always be a binary I as the address is shifted through the DMA, and the ACH flip-flop will not be
set by the SDMAP pulses, because a 0 must be present in DMA II at SDMAP time to set ACH. Each
SDMAP pulse shifts a binary 0 into DMA bit I; at the end of the address (word 0), the DMA contains
00008.
i.

At the end of the address 0 word, the ABC is cleared.

The TCP pulse strobes the contents of the

However, the ACH flip-flop is still reset at the end of the address 0 word,

ABC and sets ADC.

because no DMA II (0) was seen. Setting the ADC also provides a pulse to set the ACH.
prevents adding I to the DMA during address word I.

Data for address 00008 is written during address word I.

A DEP is generated,

This

clearing the ACH

flip-flop, and the DMA has I count added to it during address word 2.
k.

Note that the TEP pulse sets the ABC flip—flop.

This ensures that ABC does not compare the binary
This erroneous setting of the ADC cannot occur during the
head-switch function; however, it could occur at the beginning of a read or write instruction. If
the DMA is loaded with 00008 by the DMAW or DMAR instruction, and the address search starts
after address 00008 has passed the address heads, the special address leaves the ABC flip-flop clear.
Os in the special address and set ADC.

Therefore, TEP is used to set ABC at special address and to prevent setting ADC.

3.4. I.4

HSE With a Full Disk

in bits 0 through 6 of the EMA.

The last angular address on the last track of a disk is represented by binary Is

In this case,

generation of the HSE (I) (refer to subparagraph d, Section 3.6. I.3)

bits 0 through 6 of the EMA to go to O and complement bit 7.

EMA 6, going from binary I to binary 0,

provides a pulse to reset the DRE flipvflop and set the MRS flip-flop.

Head switching is accomplished as pre-

causes

viously described; however, clearing the DRE prevents address search until I6 words have been counted.
I6 word settling time is required because a

new

disk has been selected.

The

If the new disk is positioned at the

switching gap, the I6 word delay is bypassed, and address search starts at address 00008.

3.5

WRITING DATA ON THE DISK

Figure 3-IO is a simplified block diagram of the functions used in writing data on the disk. Figure 3—9 is a flow

diagram that shows the sequence of operations and identifies the circuit components used. Address circuit
operation is described in Section 3.4, and a discussion of the address search in this section is limited to the

placement of address circuit functions in their proper positions in the writing sequence.

3.5.I

General Discussion

The writing instruction

is DMAW (66058). This instruction, at IOP time I, clears the DMA and the MBH registers

and clears the RFO8 logic to prepare for writing.

the first data word location.

number.

At IOP time 4, the DMA register is loaded with the address of

A separate instruction has already loaded the EMA register with the disk and track

The three—cycle data break facility of the PDP—8 is then requested.

3-19

When the PDP-8 accepts this

request, it locates the data for the first word and loads it into the MBH register.

The data bits are then written on the disk serially,

located, and the data is loaded into the OMB register.

data break is sent to the PDP-8.

lowest order bit first, and a new request for a
transferred from the DMB to the disk, 0

without issuing a
been tra nsfe rred

new

The specified track address is

data word is loaded into the MBH.

While the data bits are being

This procedure continues,

DMAW instruction, until the number of data words specified in the word count register have

Information required by the PDP—8 before the DMAW instruction can be issued is described in Chapter 4.

number of words transferred is sufficient to fill one address track

(or the remainder of one), the system automat—
If the last address of the last track is

ically switches to address 0000 8 of the next rack and continues writing.

used on a disk, the system automatically switches to the next disk, if one is installed.
set and

disks

can

be used in the program as an error indication.

If the

If not,

NXD flag is

However, if the disk file has the maximum of four

installed, a program that exceeds the capacity of the disk file will cause the system to switch to the first
At the completion of writing (word count register

address of the first disk and continue writing.

O), the last

address + l is present in the EMA and DMA registers.

______________________

Rsoe

DATA

FROMD————>
PDP

8'2?
9’

MEMORY

DISK

MEMORY

BUFFER
HOLD

‘0 T

BUFFER

604

(SHIFT
REGISTER)

‘

WRITE

HEAD

DRIVER

8” "

l
|

WRITE

|
|

l
LDMBP

WW (II

WLMBHP

,_,.v,,4._

DATA

ADDRESS

READER

CMBIIE

_____________________

SDMBP
BTcs—

TIMING

DATA

CONTROL

ADC

EEEEEBTHF FEW '55 H??? S'FJEB
SIGNALS

ARE

SINGLE

BIT"

22:.

T I

"CONTROL 0 R

“M,

ADDRESS

CONTROL

BITS

BREAK

.l
FROM

BIT

SERIAL
T

——-O

ADDRESS

BIT

pop"

"'
'

‘4’

PARALLEL

CONTROL
SING L E

OR
BIT
08-0256

Figure 3—l0

Simplified Diagram, Writing Data on the Disk

3—20

3.5.2

Logic Flow in Writing Mode

Logic signal flow for the writing mode is discussed below.

3.5.2.1

Sequence of Events that Load the DMB Register
The DMAW command is generated in the PDP-8, and at IOP time T, CDMAP and SCLP l and 2 are
generated, clearing the DMA and RF08 logic. This operation is described in Chapter 4 for the
DCMA instruction.
At IOP time 4, the DMA is loaded with the first data word address from the accumulator of the

PDP-8.
is set,

The DBR is set, requesting a three-cycle data break from the PDP-8.
indicating the write mode.

At this point, the

logic flow divides into two alternate paths.

The W flip—flop

Point l indicates the beginning of

the address search which is shown on this flow chart to indicate the control the address circuits have
over

data transfer.

The operation of the address circuits is described in detail in Section 3.3.

At point 2, the system waits for an Address Accepted (ADDR ACC) signal from the PDP-8,

the start of the data break cycle.
a

When ADDR ACC is received, DBR is reset.

indicating

The PDP-8 supplies

B Break pulse and a Tl pulse as it continues through the data break cycle.

The B Break pulse sets CMBH, generating a clearing pulse (CMBHP) for the MBH register. The Tl
pulse follows. The B Break, Ti, and R/W (l) are ANDed to reset the CMBH flip-flop and to genand 2. This loads the MBH register with the contents of the PDP-8 memory buffer.
The data break is now completed, and the PDP-8 continues with the next insthction.

erate WLMBHP l

The disk file waits until the angular address has been located. The amount of delay depends on the
time required to read the track address. The minimum time required is approximately 260 ps (the
time it takes TCA, TCB, TCC, and TCD to count 1610 words of 16 ps each). This assumes that the
correct track address appeared on the l7th word following the LDMAP pulse. TCA, TCB, TCC, and
TCD are reset when any of the following conditions occur: a change takes place from read to write,
from write to read, or a track select or disk select. Resetting allows the read/write amplifiers to
settle before any reading or writing is done. If the address being searched on the disk is in the
correct position when TCA, TCB, TCC, and TCD are counting, the time until that address appears
again is 33.3 ms (60 Hz). The DBR is accepted at the end of the PDP-8 instruction in progress,
within approximately 4 ps; therefore, no inhibiting logic is provided to prevent continuation if the
DBR is not accepted. When the address circuits locate the track address, the ADC level goes true.
The WEP (occurring at bit—time T4), the ADC level, and the W (T) level are ANDed to generate
LDMBP, which transfers the data in the MBH to the DMB.
The logic flow divides after LDMBP has been generated (see Point 3, Figure 3-9).

Continuation of

the writing process is described in Section 3.5.2.2.
If the WCS is clear when LDMBP is generated, the DBR flip-flop is again set, and a new data break
is initiated at point 2 on the flow diagram

(see Figure 3-9).

When the last data word is transferred to the MBH register, the WCO pulse is received from the
PDP-8. This pulse sets the WCS at point 3 on the flow diagram. This inhibits the DBR flip-flop
from being set by the LDMBP pulse.

The last
End
A DFSC instruction may be generated by the

Instead, the LDMBP pulse sets the WCO flip-flop.

data word is written on the disk, and the DEP, at the end of this word, sets the DCF flip—flop.

of transfer is indicated to the PDP-8 when DCF is set.
PDP-8 to produce a skip instruction. See Chapter 4 for a detailed description.

3-21

Writing the Data Word in the DMB on the Disk

3.5.2.2
0 .

At point 3 on Figure 3-9, the data word has been transferred into the DMB.
Write flip-flop (WFF)

was

set

by the BSCLP.

In the R508, the

Before the address is confirmed, the buffered write

(BWTE) level is false, inhibiting writing current. In addition, EMA bits 7 and 8 select the disk to
The select (SLT) level is true only for the disk that has been selected.

be used.

indicating that the address has been located, it is ANDed with SLT and
Write current flows in the head, writing a flux
(I)
transition onto the disk over any previous information written on the selected track.

When ADC becomes true,
WFF

energize the DSL+ data sense line.

The enabling level for the WFF is provided when BWDE is true and the content of DMB II is a I.
If DMB II is a binary O, the enabling level is not generated. The BWDE level is true (logic I) for
the first 12 bit—times, and false (logic 0) for bit-times I3 and 14.

The WFF is strobed by Track A Slice Buffered Delayed (TASBD), when BWTE is present. TASBD is
generated by the Track A pulse and delayed 250 ns. If the enabling level at the WFF is true, the
WFF is complemented by TASBD. This clears the WFF (for the first I written) and reverses the

writing current, energizing DSL-. The magnetic flux written on the disk is reversed. For each I
be written on the disk, the WFF is complemented, reversing writing current direction.

to
e.

If a binary O is to be written on the disk, the content of DMB is a

logic 0 at BDDMB II. This

condition inhibits the enabling level at the WFF; therefore, there is no effect when TASPD strobes

the WFF.

The write current remains unchanged, and any previous data is erased.

If ADC remains true, TAP is used to generate SDMBP to write the next bit.

After the 12th bit is written on the disk, BTCS- occurs,

the enabling level at WFF.
at

the set input to WFF.

setting the WDE flip-flop.

This inhibits

At the same time, however, the WDE (I) level appears as BWDE (I)

At bit-time

I3, the last TAP pulse in the data word strobes WFF and sets it.

If an even number of binary ls are written, WFF is already set, and a binary O is written.

If an

odd number of binary Is are written, WFF is set from binary 0 to I, and a binary I is written. The
13th bit is the parity bit and ensures that each word has an even number of binary Is written, in-

cluding a parity bit. Because this is the last bit in a word, WFF is always set at the beginning of the
next word. When reading, the number of binary Is in a word is counted by a 1-bit register; therefore, loss of a bit in reading can be detected.
h.

The process loops back to point 3 of the flow chart (see Figure 3—9) and continues as long as ADC
is set. ADC can be cleared either by the end of a data transfer or by a head switch. A head switch
on the same disk reenters the process at point 4 of the flow chart, and a disk switch reenters the
process at point I. When the address is confirmed again and ADC is set, the writing begins again
point 5 of the flow chart.

If EMA bit 6 is a binary I and is incremented to binary 0 during a head switch, the current disk is
If the next higher disk is not installed a nonexistent disk (NXD) flag is set. However,
addressing a nonexistent disk prevents the timing track signals from operating the RF08 address
circuits. DRE and ADC remain clear, and the process halts at points I and 5 of the flow chart
(see Figure 3-9). The data word loaded in the MBH register cannot be written on a disk. However,
the associated data break for loading this word into the MBH register has been executed, and the

filled.

word count and cuwent address registers hold a count that is I greater than both the number of words
to be transferred and the current address.
(Note that the number in the word count register is a

negative number.)

3.6

READING DATA FROM THE DISK

The DMAR instruction sets the RFO8

logic for reading.

Initially, the address placed in the DMA register is

located on the disk; once this address is located, the data is read serially from the disk, low—order bit first,

3-22

and then shifted into the DMB.

At the end of each word read, the data shifted into the DMB is parallel

transferred into the MBH, and a data break is requested.
data address is read into the DMB.

Meanwhile, the next data word from the next higher

When the PDP-8 accepts the DBR, the data in the MBH is strobed into the

PDP-8 memory buffer and stored in the address specified.

Each data word is read until the word count is O. The

number of words read in the block is specified by placing the number in the word count register before issuing
the instruction DMAR.

The addresses, to which the data read is transferred, are specified by the current address

These registers are both located in the PDP—8 and described in Chapter 4.

cremented by I each time a DBR occurs.

The current address is in—

The series of words read from the disk is transferred to a series of

The word series (in a block on a disk) are read from adjacent addresses; that is, the

addresses in core memory.

first word read comes from the address specified by the DMA contents, the second word comes from the next

address, etc.

No addresses are skipped during a block transfer.

Data Flow When Reading

3.6.l

Figure 3-H is a block diagram of data flow when reading, and Figure 3—12 depicts the DMAR Read Logic flow.
The following text is a discussion of DMAR logic flow:
The DMAR instruction is generated by the PUP-8.

are

At IOP time

The Read/Write flip—flop is clear,

At IOP time 2, the first disk address is loaded into the DMA.

i, SCLP and SCLP I and 2 pulses

generated, clearing TCA, TCB, TCC, TCD and DMA.

enabling the contents of the MBI (in the R508) to be read into DMB 0 when ADC becomes true.
Next, the track address is located as described in Section 3.4. l

ADC goes true at the end of the

address word which matches the contents of the DMA register.

'—

_________________

R568

_‘l

|
BITS

HEAD

____

BUFFER

HOLD

0‘”

p D p

S DMBP
TAP

R/W (O)

RLMBPH

CMBHP

IOT 602
I

TIMING

DATA

(READ)

CONTROL

BTCS—

CONTROL

SPECIFIED

UNLESS

OTHERWISE

SIGNALS

ARE"CONTROL

SINGLE

BIT

AD D RE 88 TRACK

BIT

SERIAL

-—.

BIT

PARALLEL

fl.

CONTROL
SINGLE

ADC

ADDRESS
'

BITS
=0

l
._.._.__.____._.___J._.__.—. .J

BR/w (O)

.__. TO

READER

MEMORY

(SHIFT

ADDRESS

MEMORY

LOAD

}

D ”A

DISK
BIT I

SLICE

l
'
I
'

DATA

WRITE

CONTROL

BIT

Figure 3-H

Data Flow When Reading

3—23

06-0249

GENERATE

DMAR
NOTES1
1

ADDRESS
AND

LOOP

CONTINUES

FROM

POINT

<:>

ATIOPI
GENERATE
SCLPIANDZ
BSCLP

WTEISINHIBITED BYR/W CLEAR

3_POINT

4.AT POINT

IS END OF TRANSFER TO POP-8‘
TCP STROBES

PARITY

ATIOPZ

CHECK,DEP SETS DBR.

GENERATE

LDMAP,CLEAR
WCS,R/W
SETMRS

w———D{D

IS
PCA

TRUE

WAIT
16 WORDS

LOCATE
ADDRESS
SEE FIG.3-G

SET
IS
ADC

ADC

YES

SET
p

GENERATE
SDMEP

YES

BMBIAI

ENDOF
TRANSFER

SET DMBO

CLEARDMBO

BTCS- TRUE

POP-8 READS
DATAIN MBH

CLEAR

DBR

AT DEP

GENERATE
RLMBHP

0———

SETPER

Figure 3-12

DMAR Read Flow Diagram

3—24

SET

DBR

POP—8
GENERATES
ADDR ACC

The first Track A Pulse (TAP) of the next data word generates the SDMBP shift pulse which right shifts

cl.

the DMB l bit before any data is strobed in.

There are l2 more TAP pulses in each data word,

therefore, the data is shifted 12 times although SDMBP generates l3 shifts in the DMB.
MBI is cleared by the first TAP pulse, and the contents of MBI are delayed 40 ns before acting on

DMB 0.

This delay compensates for cable and logic skew time, ensuring that MBI is present at the

correct time to act upon

DMB 0.

The contents of MBI are iam—transferred into DMB 0.

After the first bit of the data word is read, BTCS— is not true, and the

reading process loops.

is set, and the second TAP pulse generates the second SDMBP pulse.

This condition causes the data

in DMB O to shift into DMB l.

ADC

Following SDMBP, the contents of MBI, representing the second bit

of information read from the disk, are loaded into DMB 0.

l2), BTCS— goes true. BTCS- is ANDed with Read/Write (0)
(l) to generate CMBHP, which clears the MBH register. At bit—time l4, BTCS+ goes true,
generating the TCP pulse. TCP generates DEP which is ANDed with Read/Write (O) to generate the
Read Load Memory Buffer Hold Pulses (RLMBHP l and 2).

At the end of a data Word (bit—time

and ADC

RLMBHP l and 2 transfer the data in the DMB to the MBH. Only after all l2 data bits have been
strobed and shifted into DMB O, are RLMBHP l and 2 generated. The first data bit strobed, which
is the lowest order bit, is not in DMB ll.

RLMBHP l and 2 is ANDed with WCS (O) to set the Data Break Request (DBR) flip—flop. Point 3 on
the flow diagram depicts this (see Figure 3-l2). WCS inhibits a DBR after the PDP—8 word count

register becomes 00008, which signifies the end-of-transfer.
When the PDP-8 accepts the DBR, it generates ADDR ACC as part of the three-cycle data break

which clears the DBR flip-flop.

The data in the MBH register is strobed into the PDP—8 memory
This point is the end of read transfer between the disk and PDP—8. If words remain to be
transferred (indicated by a negative WCO), the transfer loops back to point l on the flow chart (see
buffer.

Figure 3-l2).

3.6.2

Operation at the End of an Address Track

When all of the data from one address track has been read, and data transfer is to continue at the beginning of
the next track, ADC is cleared, and data transfer is inhibited until the switch has been completed.

When the

switch has been completed, ADC is set again, and data transfer continues from address 00008 of the new track

selected.

Automatic head switching to the new track increments the EMA by l; the new track number is the

old track number +l.
ation at the end of a

Operation of the head switching logic is described in detail in Section 3.4. l.3.

Oper-

disk, when a new disk is automatically selected, is described in Section 3.4.l.3 and

3.4. i .4 (also see Figure 3-12).
The program branches at point 4 of the flow chart (see Figure 3—12).
is set to indicate the end of a track.
not go to 0,

The EMA is incremented, and the next head is addressed. If EMA 6 does

the new head is on the same disk, and address search begins at address

firmed, and reading transfer begins at the next address time.

00008.

This address is con-

The data is delayed one word from its associated

address; therefore, the first data will be read from address 00008.
addressed.

If ADC is clear, and WCO is set, then HSE

If EMA 6 does go to O, a

new

disk has been

If the switch attempts to locate the new disk at any point on a track other than the head switching gap,

DRE is cleared to prevent address search.

When address

00008 is located

3—25

the new disk, reading begins again.

3.6.3

End of Data Transfer

The number of data words transferred is specified by the number placed in the Word Count Register (WCR) before
the DMAR instruction is generated.

Each time a data word is transferred, the WCR is incremented by l.

is added before the data word is transferred and before the contents of the WCR are checked.

the WCR is O, WCO is generated.

The l

If the content of

Operation is similar to the execution of an 152 instruction, except that the

WCO pulse is generated, rather than a skip.

In a read transfer, the WCO pulse clears the WCO flip-flop

immediately and simultaneously sets the WCS flip—flop.

The data word corresponding to the last DBR is trans—

ferred and the next data word on the disk is read into the DMB and loaded into the MBH; however, DBR is not
set.

DEP l and WCO

(O) are ANDed at the input to the DCF flip—flop, setting DCF.

3—26

Chapter 4
Operation and Programming

4.1

INTRODUCTION

RF08/RSO8 operation is under program control of the computer.
WRITE LOCKOUT switches located on the R508 logic chassis

The only operator controls are the

(see Figure 4-1).

This chapter discusses the operation and programming oF a single
‘

however, it is equally applicable to all R5085 in a

R508 Disk;

system

except where noted

WRITE

max-out

Power For the RF08/RSO8 logic circuits is provided by the cen-

tral processor switched power bus.

Disk motor power is provided

from a separate unswitched power bus.

When the disk is at rest,

the heads are in contact with the disk.

When the disk is oper-

ating, the heads are held a small distance From the disk by a
cushion of air.

4.2

$3”

TABLE OFINSTRUCTIONS
-

Table 4 I shows the Instructions used to program the RFO8/RSO8.
-

All programming instructions use standard IOT instructions with
IOP pulses

:‘-$:TQR&G‘E
3*???”1’?

fix
"

21..

:52

252225242272
2222222532222

3 75422232225722?
.3 géafififlfi ?? .7?
:

2242.222: 222222

22222522225525 2

Two instructions initiate the operation of the three-cycle data

break Facility:

instruction

DMAW, which loads the Disk

Memory Address register (DMA) with the contents of the AC
'

S
IC
00 dth
e
db eglns w“'t';
Ins ruc t'Ion DMAR, w h'hl
Ing an d't

DMA with the contents of the AC and begins reading.

Figure 4-I Write Lockout Switch Diagram

Table 4-1
Mnemonic and Octal Code Instructions
Mnemonic

Octal Code

Description

DC MA

6601

(SCLP) at IOP time 1. Clears Disk
(DMA), Parity Error Flag (PEF), Data Request Late
and
sets
Flag (DRL),
logic to initial state For read or write. Does not
clear interrupt enable or extended address registers.
Generates System Clear Pulse

Memory Address

DMAR

6603

Generates SCLP at IOP time 1

(see DCMA).

At IOP time 2, the

computer loads DMA with the contents of AC and then clears the AC.
Read continues for the number of words in the WC register (PDP-8

address
DMAW

6605

77508).

Generates SCLP at IOP time 1

(see DCMA).

At IOP time 4, the

DMA is loaded with the contents of AC and the AC is then cleared.
A data break is immediately requested by the RFO8. When the disk
angular address is located, writing begins; the disk address is incremented For each word written

DCIM

6611

Clear the disk interrupt enable and the extended address registers at
IOP time 1.

DSAC

6612

(Maintenance Instruction)
6615

This instruction, with DCMA, clears all

Flags.

At IOP time 2, skip the next instruction it Address Confirmed (ADC)

indicating that DMA address and disk angular address
(ABC is clear at TCP). The AC is then cleared.

is true, thus
compare

DIML

1, clear the interrupt enable and the memory address
At IOP time 4, load the interrupt enable and
memory address extension registers with data in the AC and clear
At IOP time

extension registers.

the AC
DIMA

6616

Clear the accumulator at IOP time 2. At IOP time 4, load the contents oF the status register into the AC for evaluation.
The contents
of the status register are not altered. Similar to DSAC; however,
M39 is a binary 1,

DFSE

662 1

inhibiting skip on ADC.

Skip next instruction if Data Request Late (DRL), Parity Error (PER),
(NXD) Flag

Write Locked Track Selected (WLS) or Nonexistent Disk
is set.

DFSC

6622

Skip next instruction it the Data Completion Flag (DCF) is set.

DISK

6623

Skip next instruction if either an error or Data Completion Flag is set.
(Microprogrammed OR of DFSE and DFSC.)

DMAC

6626

Clear the AC at IOP time 2.
AC at IOP time 4.

Load the contents of the DMA into the
The contents of the DMA are not altered.

DC XA

6641

Clears the 8 EMA register bits.

DXAL

6643

At IOP time 1, clears the 8 EMA register bits (same as DCXA). At
IOP time 2, loads the EMA with bits 4 through 11 of the AC. Data
in bits 0 through 3 of the AC are

end of IOP time 2 (see
DXAC

6645

ignored.

The AC is cleared at the

Figure 4-2).

Clears the AC at IOP time 1. At IOP time 4, the 8 EMA register
bits are loaded into bits 4 through 11 of the AC. The contents of the
EMA are not disturbed.

Table 4-l

(Cont)

Mnemonic and Octal Code Instructions
Mnemonic

Octal Code

DMMT

6646

Description
For maintenance purposes only. With the appropriate maintenance
cable connections and the disk disconnected From the R508 logic,

(Maintenance Instruction)

the Following standard signals may be generated at IOT 646 and
associated AC bits.

AC is cleared.

The maintenance register is

initiated by issuing an IOT 601 command.

ACH (I) ->TTA pulse
AC10 (I) ~>TTB pulse
AC9 (I) ->TTC pulse
Ac7
AC6
ACO

(T) —>DATA PULSE (DATA HEAD #0)
(I) +1 ->Photocell
(T) +1

->DBR

Setting DBR to binary 1 causes a Data Break Request in the computer.
NOTE
TTA must be generated to strobe the TTB signal into the
address comparison network.

DMAR'DMAW' OR

DXAL 0R DXAC

EMA TRANSFERS
DXAL

PDP-8/I

PDP-e/I ACCUMULATOR

DMA?

DMA

ACCUMULATOR

TRANSFERS

3mg]

0'1|2]3l4l516|7|8|9ll0_l|10‘l1213l4l5l6l718|9l1fl11
DMAC

DXAC
DMA

EMA
INDICATOR

PANEL

-—>

4lslelvlelelwln011l2|3|4|5lelvle|9lwlu
20 BIT BINARY ADDRESS

( D ISK ADDR ES S )

219
HARDWARE

REGISTERS

——>S[E"LSEKCT

ANGULAR ADDRESS

TRACK SELECT

2°

2'0

08-0422

Figure 4-2 EMA and DMA Transfer Diagram

4.3

ADDRESS CONFIGURATION

To address the maximum storage capability oF the disk system

(1,048,576 words), a 20-bit binary address is re-

quired. The 12 lower-order bits are called the Disk Memory Address (DMA) and are transferred From the
accumulator by the DMAW (write) or the DMAR (read) instructions.
Extended Memory Address

The eight higher-order bits, Form the

(EMA) and are loaded From bits 4 through H oF the PDP-8 accumulator (see Figure 4-2)

Assignment of the PDP-8 AC bits are chosen to form a 20-bit true binary address. Because there are 2048 words
per track, ll bits are required to determine the angular address.

quired to specify one of 128 tracks per disk

In addition, seven bits of the address are re-

Similarly, two bits are required to select one of four disks.

Thus

the sub-fields of the EMA and DMA are related to the actual physical placement of data bits.
The typical program is concerned with a true binary address rather than with angular addresses, tracks, or disks.

Sequencing across tracks or disks is program transparent, except for disk switching latency.
The contents of the EMA register are loaded into the PDP-8 AC by the DXAC instruction.

the AC at IOP time l and transfers the contents of EMA to the AC at IOP time 4.
are

not

Because AC bits 0 through 2

involved in the EMA address, these bits will be 05 after the DXAC command is executed.

The highest-order bit of the EMA (bit 0) is programmed by the instructions for the DMA.

operate on EMA bits I through 7.
a

This instruction clears

Figures 4-l and 4-2 show this division.

The EMA instructions

Because the RF08 is programmed with

2-word absolute address, this division becomes significant only for the maintenance of the RF08 and for critical

software timing

4.4 WRITING DATA ON THE DISK
Before data transfer can occur, two words of information must be loaded into the PDP-8 memory.

locations

77508 and 77518

are

Memory

specified as the Word Count (WC) and Current Address (CA) registers, respective-

ly, for the disk file by hard wiring in the RF08. The number placed in the WC register (address 77508) is the
2's

complement of the number of words to be transferred; i.e.

is loaded into address

77508.

The CA (core memory location

if seven data words are to be transferred, 7771

77518)

is always incremented before use,

therefore,

it is set to one less than the core memory location to be addressed for the first data word transfer.

For example, if a block transfer is to write core locations

should be loaded with

40008 through 4006 8 onto the disk, the WC register

777l8 and the CA register with 3777 8 before issuing the DMAW IOT.

The PDP-8 then

places the contents of address 4000 8 in its Memory Buffer (MB) and strobes these contents into the RF08 Memory
Buffer Hold register (MBH) to begin data transfer.

The DMAW instruction establishes a Data Break Request (DBR) for the PDP-8.

When the request is acknowledged

by the PDP-8, a three-cycle data break transfer is selected. When the PDP-8 completes the three-cycle data
break, it returns to the program, and the R508 writes the information loaded into the MBH onto the disk. After
the word is written, the RF08 generates another Data Break Request (DBR), and the three-cycle data break is

repeated.

The end of data transfer is signaled to the RF08 by a Word Count Overflow (WCO) from the PDP-8,

when the RF08 requests the last data word to be written.

When transfer is complete (DCF set), the DMA and

EMA registers in the RF08 contain the address of the last data word written.

4.5

READING DATA FROM THE DISK

Reading uses the three-cycle data break facility of the PDP-8, as described in the preceding paragraphs.
Before starting a read cycle, one address less than the first core address

disk is to be transferred) must be placed in core location
must

be placed in core location 7750

(into which information read from the

77518. Also, the number of words to be transferred

the 2's complement.

The Extended Memory Address (EMA) is then

loaded into the EMA register from the PDP-8 accumulator with the DXAL instruction.
a

discussion of loading the memory address.

Refer to Section 4.3 for

Next, the initial disk address is placed in the PDP-8 accumulator

and is loaded into the RF08 DMA register at the beginning of the DMAR read command.
is

loaded, the address is located and reading begins.

After the DMA address

At the end of the word, the data is transferred from the

Disk Memory Buffer (DMB) to the Memory Buffer Hold register (MBH), and the Data Break Request (DBR) flag is
The DMB is now free to read the next data word, while the PDP—8 accepts the data word stored in the

set.

MBH and resets the DBR flag.

As the PDP-8 advances through its data break cycle, initiated by accepting the DBR flag, it adds a l to both the
word count

(in 77518) and the current address (in 77518). When the next data word has been transferred to the

DMB, the cycle repeats. This continues until the word count becomes 0, which sets the Data Completion Flag

(DCF), ending data transfer.

At the end of a data transfer, the disk address is one greater than the last disk

address from which data was read.

The new disk address is contained in the DMA and EMA registers.

EMA is loaded by the DXAL instruction, which establishes the nine high-order bits of the disk address.

The

The 12

lower-order bits are loaded from the PDP-8 AC into the DMA with the DMAW IOT instruction.

77518 contains the last address into which data
tains
00008

Address

can

be stored in the PDP—8 memory.

Address 7750

COH—

4.6

STATUS REGISTER

The status register contains the disk flag, interrupt control bits, and core memory extension bits.

These bits are

described in the following paragraphs.

4.6.]

Photocell Sync Mark (PCA)

There is no photocell in the R508, consequently, the PCA signal is generated logically.
because it is similar in function to the DF32 photocell.
word

(37778) appears

the tracks of the disk.

It is designated PCA

The PCA flag occurs approximately 50 ps after the last

The flag is set for 100 us to indicate the origin mark on the disk.

Special logic is provided in the RF08 to override the normal lé-word synchronizing period for either the DMAW
or

DMAR instructions issued during this time.

For example, if successive 4096 word fields are to be written con-

tinuously on the disk, the program can optimize the transfers by setting up the next transfer during PCA time to

eliminate rotational

latency.

Note that this Feature is valuable only when the starting angular address

(DMAl-DMAH) is less than 178.

4.6.2

Data Request Enable (DRE)

The DRE signal is used for maintenance purposes and indicates that the control is searching for an address or

transferring data

4.6.3 Write Lock Selected

(WLS)

The WLS signal indicates that the selected disk address is write-locked via the switches on the R508.
bit is set only on the DMAW instruction.

The status

Regardless of the commands issued to the RF08, data cannot be written

in a write-locked area.

4.6.4

Error Interrupt Enable

(EIE)

The EIE signal enables an interrupt on the inclusive OR of WLS, DRL, NXD, and PER.

4.6.5

Photocell Interrupt Enable (PIE)

The PIE signal enables an interrupt on PCA; however, caution should be exercised when enabling this interrupt
because the interrupt request lasts only 100 p5.

4.6.6

Completion Interrupt Enable (CIE)

The CIE signal enables an interrupt on completion of an operation (WCO issued by the computer).

4.6.7

Core Memory Extension Field

The core memory extension field is for data transfers.

4.6.8

Data Request Late (DRL)

This flag indicates the PDP-8 did not honor the data break request soon enough to prevent the loss of data (refer
to

Section 4.10).

4.6.9

Nonexistent Disk

(NXD)

This flag indicates a disk has been selected that does not exist logically.
a

physical disk with a logical number (refer to Section 4.8).
4-6

A iumper card in the R508 associates

4.6.10

Parity Error (PER)

The PER flag indicates a parity error occurred in the read mode.

The flag is set and the interrupt is requested

(if EIE enabled) at the end of the erroneous word.
Care must be exercised if combinations of interrupt enables are used, since one, two, or three interrupts may
occur

during a single transfer, depending on the timing of the interrupt requests.

By storing the current address (CA) at the time of the PER interrupt, it is possible to approximate the location on
the disk causing the error.

The transfer always continues until it receives a Word Count Overflow (WCO) pulse

from the PDP-8.

4.7

DATA TRANSFER INVOLVING TWO DISKS

If more than one disk is installed, a transfer can start on one disk and end on a second disk.

Switching between

disks is performed automatically by the RF08; i.e. , no additional instructions are required in the program.
cause

Be-

the angular positions of RSO8M disks are not synchronized, an accessing latency occurs when the transfer

sequence switches from the last address of disk n to the first address of disk n

4.8 OVERFLOW OF DISK CAPACITY

When less than four disks are controlled by an RF08 Control, a read/write transfer from the last physical address
causes

the Nonexistent Disk (NXD) flag to be set.

If four disks are controlled by an RF08 Control, the addressing

from address 3,777,777

"wraps around"; i.e.

08 without setting the NXD flag. Transfers continue

When switching disks, the RF08 logic must resynchronize to the new timing tracks.

given disk, a delay must be provided to permit the read amplifier to recover.
recovery delays requires 16 word times.

50 Hz disks.

the addressing will sequence

described in Section 4.5.

When switching tracks on a

The synchronizing or amplifier

Thus, the minimum access time is 260 us for 60 Hz disks and 320 us for

The origin gap is of sufficient length (550 us) to permit spiral reading or writing

The write-to-read recovery time of the data amplifier must be considered for specialized programming applications.

The amplifier recovery time depends on the data previously written.

write of all zeros.

4.9

Worst case occurs after on

204810

Best case is defined by the minimum access time.

PROGRAMMING DIFFERENCES BETWEEN RF08/R508 AND DF32

Programming for the RF08/R508 follows the general programming layout of the DF32. Table 4-2 lists the
mnemonic instructions and corresponding octal code for the RF08/R508 and the DF32.

Each instruction is

The addressing of both disks is similar;

Followed by a comparison of the differences between the two units.

however, the R508 has 27 tracks, while the DF32 has only 24. This added addressing capability is placed in the
Extended Memory Address
most

(EMA) register, which has been extended with three more significant bits. The two

significant bits address the disk by number (disk 0-3), in both units. Where the mnemonics differ, the DF32

mnemonic can be used to obtain the desired octal code during assembly.

Table 4-2

Comparison of DF32 and RF08/RSO8 Instructions
DF32

Octal

RF08/R508

Mnemonic

Code

Mnemonic

DCMA

6601

same

Identical functions.

DMAR

6603

same

Identical functions.

DMAW

6605

same

Identical functions.

DCEA

6611

DCIM

Clears interrupt enable, does not clear EMA.
memory address extension on both units.

DSAC

6612

same

Identical functions.

DEAL

6615

DIML

RF08/RSO8 to DF32 Comparison
.

Clears

Similar, except functions transmitted from the AC are
different.

EMA information not transmitted.

See

DXAL.
DEAC

6616

DIMA

Similar, except that functions transmitted to the AC
are

DFSE

6621

same

6622

same

(none)

6623

DISK

See DXAC.

Instruction is skipped on error, rather than skip
no

DFSC

different.

error.

-—

NXD added as an error.

Identical functions.
New instruction.
or

both.

Skips on error or data completion,
(DFSE and DFSC combined.) Skip enabled

at IOP 2.

DMAC

6626

same

Identical functions.

(none)

6641

DCXA

Clears EMA

(none)

6643

DXAL

Clears and loads EMA with information in the

accumulator.

4.10

(none)

6645

DXAC

Clears accumulator and loads address in EMA into the
accumulator.

(none)

6646

DMMT

Maintenance instruction (refer to Table 4-1).

INSTRUCTION AND DATA TRANSFER EXECUTION TIMES

4.10.1

IOT Execution

All of the instructions used by the central processor to control the RFO8 are IOT instructions.
described in the maintenance manual for the associated user's central processor.
time for an IOT instruction is approximately 4.25 p5.

4—8

These are fully

In the PDP-8 series, execution

4.10 .2

Data Transfer

Each l2-bit data word transferred requires a three-cycle data break, (4.5 ps duration).

Timing of the data

break requests is controlled by disk file operation and is asynchronous with respect to central processor operation.
The central processor acknowledges the highest priority Data Break

Request at the end of an instruction cycle.

After all data breaks are serviced, the central processor continues with the next instruction.

Data Break

4.10.3

Priority

Two Factors affect the latency period between the DBR and the transfer of data between the PDP-8 and the RFO8.

First, the data break cannot be honored until completion of the current instruction, which can be up to l8.5 ps
for worst case conditions such as EAE normalize (optional).

Second, any outstanding break requests from higher

priority devices must be honored before responding to the RF08 Data Break Request (DBR).
If the particular installation uses the DMD] Data Multiplexer, the RF08 system must be the highest priority data

break device and, therefore, should be attached to the device zero port.
The RF08 has a Data Request Late (DRL) flag which indicates that a DBR was not honored in time for normal
If the DRL is set, one or more words may have been omitted on a read (although the correct number

operation.

of words will have been transferred).

Similarly on a write, too many words can be transferred from core, but

may be missing ”in the middle"

one or more

Depending on the duration of the latency period before the PDP-8 answers the data break, data words may be
omitted

(as described above) or an erroneous data transfer may occur.

If EAE normalize
erroneous

4.10.4

(NMI) is executed while the RF08 is transferring data, the DRL flag will be set to indicate an

transfer.

If correct data is required, the operation must be repeated.

Reliability

Software, utilizing the RF08/R508 Disk subsystem, should make provisions for errors in data transfer.
not

This does

imply that the RF08 is unreliable, but it is an acknowledgment of the fact mechanical devices are not as

inherently reliable as solid state devices.
In most applications, automatic rereading of bad data is sufficient.

before calling it a ”hard" error.
error

correction must be used.

Eight to ten rereads should be attempted

For applications requiring extreme reliability, additional

error

detection and

The following are useful techniques:

Adding longitudinal parity checks, Hamming codes, or cyclic redundancy checks into the data for

additional error detection and correction.
I

Use of the RF08 address registers as a cross check after completion of a read or write operation.
The registers can be compared with those values computed from the record length and starting

address.

4-9

Reading the data immediately after it is written. A ”read after write” operation is especially
It requires no additional time because the disk is

valuable when loading the system onto disk

much faster than the peripheral supplying the data.

Multiple copies of the data can be kept on the disk

For maximum protection against electronic,

disk failure, the data must be written on data tracks whose two most-significant octal

head,
digits differ by 03 or more and whose least-significant digits are not the same.
or

4-10

Chapter 5
Maintenance

INTRODUCTION

The RF08/RSO8 Disk has been properly aligned at the factory prior to shipment and should not require further

alignment. If, however, realignment is required, the following procedures must be performed, in the order
presented

5 .2

TEST EQUIPMENT

The test equipment and diagnostic programs required for alignment are:

Type 543 Tektronix oscilloscope, or

the equivalent, with two IOX probes and ground clips; Track Selection Subroutine SA0265; and Disk Data

Diagnostic subroutine SA20I.

5.3

TIMING TRACKS AND DATA TRACK TIMING

The following alignment procedures are to be performed on the G085 Disk Read Amplifier and Slice Module
mounted in

5.3. I

logic panel locations A02 and B02, A03 and B03, A04 and BO4, AI2 and BI2.

Timing Track Gain Adjustment

The following is the proper procedure for adjusting the Timing Track Gain.
Procedure

Step
I

It is important that the

Calibrate the the oscilloscope to produce IV per cm.
two IOX

probes be properly compensated.

Ground the channel I probe to the ground pin of the G085 Module under test.

Trigger the oscilloscope from ON-LINE, set the horizontal sweep to 5 ms/cm,
DC-couple the oscilloscope probe, and calibrate channel I to produce a verti—
cal amplitude of 0.2 V/cm. The effective gain with the IOX probes is IV per cm.

With the channel I probe connected to A02-T (see Figure 6-38), adiust the
A section of gain control R21 to produce an average amplitude of 7V peak-to-

peak.
5

Repeat Step 4, alternately connecting the channel
location A04 and

4a[‘304).
5-I

I probe to A03—T (Module

5.4

TIMING TRACK SLICE ADJUSTMENT

The following is the proper procedure for Timing Track Slice adjustment:

Procedure

Step
1

Before makine Slice adjustments, the positive overshoot must be recorded.

channel l to produce only O.l

V/cm,

DC—couple the channel l

probe,

Set

set the

horizontal time base to 2 ps/cm, and trigger the oscilloscope from internal AC.
Connect the channel l probe to BOZ-E for TTA adjustment, BO3—E for TTB, and BO4—E
for TTC

(see Figure 6—38).

Position the oscilloscope vertical

display until the baseline rests on the horizontal
graticule and place the trailing edge of the waveform on the vertical center
graticule.
center

Measure and record the difference between the baseline and the positive transition
over

the baseline of the

trailing edge.

Set channel l to produce O.l V/cm, DC—couple the channel 1 probe, place the
oscilloscope in the ADD mode (do not invert), trigger channel l trace from internal
AC, and set the horizontal sweep to 0.2 ps per cm. Be certain that the probes are
properly compensated.
Connect the channel 1 probe to A02—T and ground it to AO3—C; connect the channel
2 probe to BOZ—E and ground it to B02-C.

Change the horizontal sweep to 2 ns/cm and center the display on the oscilloscope
horizontal center graticule. Return the sweep to 2 ps/cm and adjust the oscilloscope
to produce a stable display.
Subtract the overshoot of the trailing edge of the slice waveform measured in Step 4
from the amplitude of the trailing edge of the sliced analog waveform shown in

Figure 5-l

Adjust the slice potentiometer on the G085 Module in location BO2 to produce a
slice level of l.35V above the baseline (see Figure 6-20).
Repeat Step 9 for Timing Track B (TTB) and C (TTC) and for G085 Modules in loca—
BOB-T, and BO4—E. When making each measurement, ground the
channel probe to the module ground point. Ground termination points are shown
in Figure 6—20.
tions A03-T,

5.5

GUARD BAND AND PCA ADJUSTMENT

The following is the proper procedure for guard band and PCA adjustment:

Step
l

Procedure
Set channel l of the oscilloscope to produce O.l

V/cm and DC—couple the probe.
V/cm and DC—couple the probe. Place the oscilloscope in
the ADD mode, trigger channel l only from internal DC negative, and set the
Set channel 2 to O.l

horizontal sweep to 50 ps/cm.
Connect the channel l probe to BO8—M on the R508 and the channel 2 probe to
AO2—T.

5—2

CHANNEL
X

BASELINE

OVERSHOOT(2)
B XX E

l= AxxT

CHANNEL 2=BxxE
A+B= ANALOGY+ SLICE

LEVEL

SLICE

\ BASELINE

NOTES:
1. Measure and record the

overshoot (2).

It is approx. I volt.

2.Subtract overshoot (2) from Y, then
average

points
SLICE

the

leading

and

trailing slice

to establish the slice level.

LEVEL =

(Y-Z +X
—--)—

08-0480

Figure 5-]

Analog Slice Waveform Diagram

Procedure

Step

5.6

Sync the oscilloscope and adjust the upper potentiometer on BO8 until the negativegoing square wave is 100 ps in duration. This time duration is of minimum value,
however, IIO ps provides more reliable results.

Vary the potentiometer on B07 until a single spike appears centered on the square
wave, thus ensuring the proper guard band.

DATA TRACK GAIN (AGC

EQUALIZATION)

The Following is the proper procedure for Data Track Gain adjustment:
Procedure

Step
I

To successfully perform Data Track Gain adjustments, the

RF08/R508 system must

be capable of writing all Is on every data track; it must also be capable of reading,

with errors permissable, on each data track.
2

Write all Is on all data tracks,

Set the oscilloscope vertical amplitude to 0.2 V/cm, set the sweep speed to 2 ms/cm
triggered from ON—LINE, and connect the channel I probe to A12T grounding it to

using Disk Data Diagnostic subroutine SA20I

AIZ—S.
4

Using Disk Data Track selection subroutine SA0265, adjust the (3085 gain potenreading of 7V peak-to-peak on data track 000.

tiometer in location AI2 to obtain a

Procedure

Step

Using Disk Data Track selection subroutine SA0265, measure and record the ampli—
tudes of all data tracks on the R508 Amplitude Sheet.

Observe the results and

equalize the data tracks as required using AGC jumpers.
After equalizing the data tracks,

set

the (5085 gain so that the highest amplitude

track is I2V peak—to-peak.
NOTE

Average data track amplitude must never exceed I2V peak-

to—peak or go below 4.5V peak-to-peak. If these condiadjust the gain of the C3085 module, lo-

tions are not met,

cated in slot AI2, to compensate for the difference, then
repeat Step 5
.

If compensation is not met,

reject the unit and change the

read/write head to low or high TK.

5.7

PRELIMINARY DATA TRACK SLICE ADJUSTMENT

The following is the proper procedure for preliminary Data Track Slice adjustment:

Step
I

Procedure

Setup the oscilloscope as described in Section 5.4, Step I; be certain to measure
the overshoots.
Read all Is onto the disk,

01-wa
5.8

Connect the channel I

using the Disk Data Diagnostic subroutine SA20I.

probe to BZO—F and adjust DC DATA to produce 500 ns.

Connect the channel I probe to BII-F and adjust WIND to produce 500 ns.
Connect the channel I probe to
Set the (3085 module slice

BI9—_E and adjust B30I to produce 500 ns.

level, in, location BIZ, to I.35V.

DATA GATING ADJUSTMENT

The following subparagraphs contain the proper procedures for adjusting their respective data gates.

5.8. I

TASD Adjustment

Step
I

Procedure

Connect the channel I probe to TC TAS (connection BIOL); connect the channel 2

probe to TC TASD (connection BIO-N) (see Figure 6—38). Internally trigger the
oscilloscope from the AC, place the oscilloscope on negative, channel I mode
only, and an alternate sweep of I00 ns/cm.

5—4

‘

Step

Procedure

Adjust the B3I2 variable delay in location BIO to produce a 250 ns delay on
channel 2 (see Figure 6-9).
NOTE

Any time the gain or slice of TTA is changed, this adiustment must

5.8.2

be made.

DC WIND Adiustment

Procedure

Step

5.8.3

Connect the channel I probe to BII-F and monitor DC WIND.

Adjust B3OI For a 500 ns delay to produce a 500 ns output (see Figure 6—40).

DC DATA Adiustment

Procedure

Step
I

Using the Track Selection subroutine 5A0265, select data track 000.

Connect the channel I

probe to B20-F and monitor DC. DATA. Adiust B3OI for a

500 ns delay to produce a 500 ns output (see Figure 6-40).

5.8.4

DC COP Optimization

Procedure

Step
I

Connect the channel I probe to BI9-T, the 500 ns TC TAP delay (see Figure 6—40).

Connect the channel 2 probe to BZO-F, the DC DATA output.

Select each data track on the.switch register and record the delay between
DC DATA and TC TAP.

Reconnect the channel I probe to BI I—F, the DC WIND 500 ns delay.

Alternately switch to the data tracks having the least and most delay From TC TAP,
as
previously recorded. Adiust the potentiometers on B19 and B30] for a 500 ns
delay until DC WIND and DC DATA coincidence are equal.
6

Reconnect the channel I

probe to A07-H (DC DOP) and set the oscilloscope for

positive triggering.
7

Observe the results of the two data tracks monitored in Step 5. If either one of
the two data tracks produces a DC DOP level of less than 200 ns, the recording
head corresponding to that data track must be changed.

5-5

5.8.5

Final Slice Adiustment

Procedure

Step

Connect the channel l probe to B20-F, the 500 ns DC DATA delay connection

(see Figure 6-40).

Raise the slice level by adiusting the control on (3085 Module 812.

Using Disk Data Diagnostic subroutine SA20]
read operation for reading of data.

write all Os on the disk, then use the

Do not alternately read and write.

Lower the slice level until a data bit pickup occurs, then record this slice level.
Find the average of the two slice levels measured in Section 5.8.5,

then set the slice level

5 8.6
.

Steps l and 3,

this average.

Additional Adjustments

The following steps are provided to simplify the diagnosing of problems and to aid in the necessary adjustments.
A

Bit Pickups

Slice-to-Low:

Increase the slice level using the procedures in Section 5.6.

A slice adjustcompromise can be madeby testing for dropouts with a 5252 pattern and checking for
pickups with a 5252 or 4001 pattern.
ment

Following this procedure, repeat DC DOP Optimization procedures in Section 5.8.4. If a
bit pickup is still present, use a write/read single-word transfer by writing all Os onto the disk.
To locate and observe the failing DMA, sync the oscilloscope externally from the ADC flip—
flop (B2l-N) as shown in Figure 6-30. Connect the channel 1 probe to Al2-T and observe
the resulting waveform (see Figure 6-40).
If a varying amplitude pulse doublet appears, record the data track. This is an indication
that the read/write head is defective.

Gain—to-High:

Reduce the gain, as described in Section 5.5, and check the slice and

DC DOP levels.

Disk Plating Inperfections:

Although errors can occur on a specific data track and on the DMA,
To localize the problem, trigger the oscilloscope ex—
they
ternally by connecting the channel l probe to the ADC flip-flop (B21-N) as shown in
Figure 6-30. Connect the channel l probe to Al2-T (see Figure 6-40) and observe the wave—
form with disk data set to read a one word transfer on the failing DMA (see Figure 6-33).
can

be localized to a single bit.

If a stable single-cycle sinusoidal pulse is present, it indicates there is a hole in the magnetic
recording surface requiring that the disk be replaced if the amplitude is sufficient to produce
an error (refer to Section 5.6).

Environment:

Alternating line current transients usually cause bit pickups producing random

The disk is precisely synchronized to the ac line frequency, thus, periodic errors can
be caused by devices such as proportionally controlled heaters.
errors.

5.
B

Matrix Failures:

Test the (3285 and C3286 Modules.

Bit Dropouts

Slice-to-High:

Perform the procedures outlined in Section 5.6.

5—6

Gain-to-Low:

Perform the procedures outlined in Section 5.6.

Plating—Induced Dropout: If dropouts persistently occur in a given Extended Memory Address
(EMA) (see Figure 6—34) and Disk Memory Address (DMA) (see Figure 6—33) record all is
,

the disk.

Setup the oscilloscope as indicated in Section 5.8.6, Step A3, and observe the amplitude level.
decrease of 50% or less (several bits in

A sudden

length) in the amplitude, indicates a dropout on the disk surface.

If the

dropout is below l.8V peak—to-peak, the disk must be replaced.

5.8.7

G085 Module Identification

The dynamic range of the amplifier section of the G085 Amplifier Module is increased in revision D and later

modules.

Revision B modules can be modified to permit the increased range.

later modules, the analog signal output from Section A, pins T and U,

Older or unmodified modules are limited to 9V peak—to-peak.
l500 pf capacitors CH and Cl2.

5—7

must be

On revised modules or on D or

less than l2V peak—to—peak.

Revised B level modules can be identified by

Chapter 6
Module Circuit
Schematics

6.1

INTRODUCTION

The module schematic diagrams in this Chapter pertain to the modules used in the RF08 Disk Control and the
R508 Disk.

Table 6—1 and 6-2 lists the modules and the quantity of each used in the System.

Figures 6-28 to 6-37 are the Block Schematics for the RF08 Disk Control, and Figures 6—38 to 6—43 are the
Block Schematics for the R508 Disk.

Table 6-1
Modules Used in the RF08 Disk Control

Figure

Module Type

Quantity

6-1

B133

Diode Gate

B—CS—B133—0-1

6-2

B134

Diode Gate

B—CS—B134—O-1

6—3

B135

Diode Gate

B-CS-B135-0—1

6-4

3137

Diode Gate

B-CS—B137—0-1

6-5

8165

Diode Inverter

B—CS-B165-0-1

6-6

3212

Dual RS Flip-Flop

C-CS-B212-O-1

6-7

B310

Delay Line

A—RS—B—310

6-8

B311

Tapped Delay Line

B—CS—B311-0-1

6-9

B312

Diode Gate

B-CS—B312-0-1

6-10

3611

Pulse Amplifier

B-CS-B611-O-1

6-11

3683

Bus Driver

B-CS-B683-0—1

6-12

5123

Diode Gate

B-CS—5123-0-1

6-13

5202

Dual Flip-Flop

B-CS-5202-0-1

6-14

5203

Triple Flip-Flop

B-CS-SZO3-O-1

6-15

5206

Dual Flip-Flop

B-CS—5206—0—1

6-16

W103

Device Selector

C-CS—W103—0—1

Description

Drawing Number

Table 6-2
Modules Used in the R508 Disk

Figure

Module Type

Quantity

Description

Drawing Number

6-]

8133

Diode Gate

B-CS—Bl33—0—l

6—2

B134

Diode Gate

B—CS—Bl34-0-l

6—3

8135

Diode Gate

B-CS-Bl35-0-l

6-4

B137

Diode Gate

B-CS-Bl37-0—l

6-l7

Bl52

Binary-to-Octal Decoder

B—CS—Bl52-0-l

6-5

B165

Diode Inverter

B-CS—Bl65-O—l

6-l8

8172

Diode Gate

B—CS-Bl72—0-l

6—6

82l2

Dual RS Flip-Flop

B-CS-B2l2-0-l

6-19

B30]

Delay One—Shot

B—CS-B30l—0-l

6—9

B312

Diode Gate

B—CS-B312-O-l

6-10

Béll

Pulse Amplifier

B-CS-Bél l-O-l

6—H

3683

Bus Driver

B—CS—B683-0—l

6-20

G085

Disk Read Amp and Slice

B-CS-G085—0—l

6-2]

G284

Disk Writer

B—CS-G284—0—l

6-22

G285

Series Switch

B-CS-G285-O-l

6—23

G286

Centertop Selector

B-CS-G286-0-l

6—24

R002

Diode Cluster

B—CS-R002—0—l

6—25

R11]

Diode Gate

B—CS-Rlll-O-l

6—26

R302

Delay

B—CS-R302—0—l

6-27

R303

Integrating One-Shot

B-CS-R303—0-l

6—l5

5206

Dual Flip-Flop

B-CS-SZOé—O-l

6—2

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Appendix A
Reference Documents

A .l