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DEC-08-H6BA-D

December 1968

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Document:	AX08 Laboratory Peripheral
Order Number:	DEC-08-H6BA-D
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Pages:	66
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OCR Text

Digital Equipment Corporation
Maynard, Massachusetts

a“Eula“

PPD-8
AX08

LABORATORY PERIPHERAL
INSTRUCTION MANUAL

DEC—O8— H6BA-D

AXDB
LABORATORY

RERIRI—IERAL

INSTRLIOTION

MANUAL

July 1968

DIGITAL EOLJIPMENT

CORPORATION 0 MAYNARD, MASSACHUSETTS

The Following are registered trademarks of Digital Equipment Corporation,

Maynard

Massachusetts

DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONTENTS

Page
CHAPTER I

GENERAL INFORMATION

susub

Introduction

1-]

Physical Description

I—I
1-]

Physical Characteristics
Functional Units

1-2

Options

1-3

System Characteristics

1-3

Reference Documents

1-4

CHAPTER 2'
OPERATION AND PROGRAMMING
General

Controls and Indicators
Enable Registers

I/O Instructions
2.4.1

Microprogramming

2.5

Display Control

2.6

Enable Register Bit Configurations

2.7

Clocks and Schmitt Trigger Inputs

2.8

Multiplexer and ADC

2.9

Diagnostics
CHAPTER 3
PRINCIPLES OF OPERATION

3.1

Block Diagram

3.2

IOT Decoding

3.3

Clocks
V

3.3.]

Crystal Clock

3.3.2

RC Clock

3.4

Enable Register

3.5

Contingency Register

3.6

Synchronization or "Sync" Channels

3.7

Input Channel Selection

Optional

Option XR

CON TE NTS

3.7

Input Channel Selection

3.8

Analog-to-Digital Conversion

3.9

Display Control

3.10

Input Mixers

(Cont)

CHAPTER 4
MAINTENANCE

4.1

Introduction

4.2

Diagnostics

4.3

Calibration

CHAPTER 5
ENGINEERING DRAWINGS
ILLUSTRATIONS
1—]

AX08 Operational Flow Diagram

I—2

AX08 Front Panel Controls
2-2

DiSplay Axis Organization

2-4

3-I

AX08 Block Diagram

3-2

IOT Decoding

Logic

3-3

Crystal Clock Logic

3—4

3-4

RC Clock Flag Logic

3—5

Enable Register

3-6

Contingency Register

3-7

”Sync” Channel Logic

3—7

3-8

Input Channel Selection Logic

3-8

3—9

Analog-to-Digital Timing

3—9

3-IO

Analog-to-Digital Conversion

3-IO

3-II

‘X- and Y- Registers

3-I2

3—12

Display Command Logic

3—I3

3-I3

Intensity Logic

3-I4

3—I4

Display Registers

3—15

3-I5

Input Mixer

3-15

3—5

TABLES

3992
1—]

Operating Characteristics Anolog-to-Digitol Conversion

1—3

1—2

Power Requirements and Environment

1—3

A—D Conversion

1—4

2-1

AX08 IOT Instructions

2-2

Enable Register

2—5

weewmfit

Type AXO8 Laboratory Peripheral

CHAPTER I
GENERAL INFORMATION

1.]

INTRODUCTION

The AX08 can be considered either a multi-purpose PDP-8—series peripheral or as an integral

part of the Lab-8 Hardware/Software System (PDP-8 or 8/I, AX08, Lab-8 Averaging Program. The
AX08 provides a facility for monitoring up to four channels of analog information
see

(expandable by option,

Paragraph l .4), performing analog-to-digital conversion (ADC) for data storage at the computer,

performing digital-to-analog conversion (DAC) on inputs from the computer for display, sensing time
through two real-time clocks, and sensing digital inputs.

For ADC, the AX08 uses the successive

approximation technique. Standard PDP-8 I/O instructions initiate and monitor the operations of the
AX08.
This manual provides a description of operation, programming, theory, and maintenance
of the AX08.

The level of discussion assumes familiarity with the PDP-8 Programmed Data Processor

and a working knowledge of DEC

I .2

logic symbology.

PHYSICAL DESCRIPTION

The AX08 is housed in a single cabinet designed especially to provide simple interconnection»
and easy access to

logic modules. The back—wired panels provide interface with the PDP-8 type com-

puters. The signal connections to the computer or to other external equipment are made via DEC cable
connectors that

plug directly into module slots.

A control/indicator panel is located on the front of

the AX08.
Power is supplied from either the computer or from a standard DEC power supply

Reference

power -l0V for ADC and DAC is provided by DEC Type A704.

I .2 .1

Physical Characteristics
Dimensions:

Panel Width
Panel Height

Standard

lO—l/Z in.

Double Rack

Depth 18-3/4 in.
1/0 Cables:

DEC Type WOll

W02l modules located per drawing

(see UML, Chapter 5)
Power:

Module power is supplied by Type 728 or (for 50 Hz operation) 728A power supplies. If the PC 8/1 option is selected,
the Type 779 or (for 50 Hz operation) 779A power supply is

also provided

Reference voltage is provided by an A704.

1-]

1.3

FUNCTIONAL UNITS

The AX08 provides a 9—bit display with two axes and intensity control (see Paragraph 1 .4),
a

9-bit ADC with four channels of multiplexed input

(expandable to 24) incorporating preamplifiers
'

and sample and hold.

The basic operational flow is shown in Figure 1-]

Channel selection is accomplished by

decoding IOT instructions From the computer, and conVersion is controlled by command, timing, and
control sequences of the computer and AX08 logic; completed. analog-to—digital conversions are sent
from the Y-register, through the input mixer to the computer.

Computer inputs through the butter are

controlled through decoded IOT instructions and AX08 logic to provide analog outputs for display.
Both ADC and DAC use the same registers and in case of simultaneous requirement, ADC has priority.

—T >I_'T

F—V

tF—i/>I
———I\

o—v

l—

l
I

/—\

: km)
:
\V/

| xc |

l
_I
.:1>I_
#7

——

(INTENSITY)

I
|

OSCILLOSCOPE

—

‘

ImeF‘U—Hl—CZ

—

—;R7;H:N‘E;S’IXTIP__—I
_

D/A LADDER

______

]<"___—l_fiI

BITSTK:1 "x”-REGI5TER

D/A LADDER (9

——

I—

(i:

(SBI‘TST
"Y"-REGISTER

SAMPLE
AND
HOLD

/77
COMPARATOR

ADC-CONTROL

|
PDP-e/I

EXTERNAL

CLOCK

VARIABLE]

SCHMITT
TRIGGER

s
T.

F? l
l
l
I

DIGITAL

INPUTS

l
I
I

FINE

@—~L-___J
ifiié‘éEEI—H

RANGE

R
E

l____-l

CLOCK

(FRONT PANEL)

N
A
L

LCRYSTAL l—Jl

CLOCK

’T‘
g

(XRll

|_ __j

‘

1D|G|TAL

OUT@<—1'—I¢—————l
I

‘

‘
3

DIGITAL

OUT

<——|

(XR)

4——

L_.J

Figure 1-1

AX08 Operational Flow Diagram

The interrupt and control scheme for this is described in Chapters 2 and 3.

1—2

—

I .4

OPTIONS
The following Options may be added to the AX08:
OPTION XR

This Option expands the registers of the AX08 to include three levels of

brightness control on the scope, eight digital inputs (contingency), three digital outputs and one
additional pulse input.

A single XR may be added to an AX08.

OPTION XM (Multiplex expansion)

The first four channels of additional analog input are

This includes the preamplifiers, additional multiplexing and expansion of

included in Option XM.

the channel selection register.
OPTION XC

A single AXOBXM may be added to an AX08.

This option is for the expansion of the ADC channels beyond eight.

AX08XC adds four channels of preamplified multiplexed analog input.
to an AX08 with XM option

1.5

Four option XC's may be added

SYSTEM CHARACTERISTICS

The Following tables define the major operating characteristics of AX08.

Table l-l

Operating Characteristics
Analog-to-Digital Conversion

Conversion

Successive approximation

Word

9 bits

Length

including sign

Accuracy

il/Z LSB i0.2%

Speed

5 17 ps

Preamplifier Input

i l

Sample and Hold

Full scale track in 2 ps

Number Notation

Signed 2's complement

.024V full scale, 50K

input impedance

Clocks

Crystal Clock

Set to 100 ps

RC Timing Clock

Variable from 2 sec to 20 ps

Each

Table l-2
Power Requirements and Environment

Reference Voltage

-IOV nominal

Input Power

Std. DEC voltages

Operating Temperature

0°C to 50°C

Table I-3
A-D Conversion

Analog Input
Voltage (i2 mV)

Digital Output
(signed 2's complement) (ii/2 LSB)

0377

+1.020
+0.768
+0.5I2
+0.256
+0.004
+0.000
-0.004
-0.256
-0.5I2
-0.768
-I .024

0300
0200
0100

0001
0000
7777
7700
7600

7500

7400

REFERENCE DOCUMENTS

Title

Document No.

Digital Logic Handbook

C-l05

Specifications and descriptions of FLIP CHIP modules,
simplified explanation of the selection and use of
these modules in numerous applications.

Small Computer Handbook

C800

Describes operation and programming of PDP-8/I

(I967/I968 Edition)
PDP-8 Interface Manual

Description

computer.
F-85

Contains computer organization information,detailed

description of all instructions, basic PDP—8 programming data, and operating procedures.
AX08 Bulletin

Contains operation and programming data at the user's

level.

CHAPTER 2

OPERATION AND PROGRAMMING

2.1

GENERAL

This chapter contains operation and programming instructions for the AX08.

Since the

AXO8 is a special I/O device for the PDP-8 series of computers, refer to the applicable documents of
PDP-8 literature for programming information.

2.2

CONTROLS AND INDICATORS

Figure 2-l

2.3

AX08 Front Panel Controls

ENABLE REGISTERS

The Enable Register is used to
a .

Selectively enable interrupts for the ADC, the ADC timing error indicator, Schmitt
triggers, the crystal clock and the RC clock
.

Initialize and run the RC clock.

c .

Shift between two speeds of the RC clock.

Provide automatic initiation of ADC upon RC or external timing pulses.

Enable an external clock pulse to set the'RC clock flag (and cause ADC if enabled).

1/0 INSTRUCTIONS

2.4

The AX08 IOT instructions are called by PDP-8 IOP l, 2, and 4 pulses.
cussion of PDP-8 programmed data transfers,

Chapter 2 of the PDP-8 User's Handbook

including IOP l, 2, and 4 generation is contained in

The PDP-8 instruction op codes for the AX08 IOT's are of the form:
bits 6 through 8, and B represents bits 9 through ll of the instruction word.
IOT instructions.

A complete dis—

63AB, where A represents

All AX08 instructions are

Table 2-] lists the IOT instructions and defines them in terms of IOP

l, 2 and 4

control.

Table 2-l
AX08 IOT Instructions

IOT

Instruction

IOP

630x

631X

632X

Dxc

DXL

Clear X Register

Load X from AC

’DYC

DYL

Clear Y Register

Load Y trom 'AC

IOP
4

91s (6304)
Intensity point

E (6314)
Intensity point

SKXK

SKER

Skip on Crystal

Skip on ADC timing error

Clk flag

convert command received

DSB

(OPT XR)

Set Brightness

DSBVO

when last conversion not

DSB l

DSB 2

dim
normal

yet read into AC
633X

XRIN
'

OR external sense

_S_l_<_A_D
Skip on ADC done

XRCL

bright

‘

Clear all bits of
external sense register

that correspond to set
bits in AC

634x

SKRK

ZTEN

OTEN

Skip on RC timing
clock flag

Zeros in AC clear

Ones in AC set bits in

635x

bits in Enable

Enable Register then AC

is cleared

CLER

CLXK

CLRK

Clear ADC timing

Clear crystal

Clear RC clock flag

and

error

Flag

error

condition

0 —% ADCERR,
o % ADCIP

clock flag

Table 2-I

(Cont)

AX08 IOT Instructions

IOT

Instruction

636X

IOP

IOP
4

ICMX
Increment multiplexer

RADC (6362)

ADCV (6364)

channel (set to Chan 0

O 9 AC

Initiate Conversion

if at maximum imple-

ADC buffer% AC

mented channel)

—> ADC done

0 %

637X

ACMX

ADCIP

RADC (6372)
O——> AC

Set multiplex

ADCV (6374)
Initiate Conversion

ADC buffere AC
0 ——> ADC DONE
O —> ADCIP

2 .4. I

Microprogramming

Microprogramming of most AX08 IOT's (except SKXK DSB or SKER DSB) is allowed.

As an

example of microprogramming effectiveness, note that with the combination of instructions ACMX
RADC ADCV, it is possible to set up a multiplex channel, start a conversion, and read the results of
a

previous conversion all in one instruction.

2.5

DISPLAY CONTROL
In AX08

operations, ADC takes precedence so that a display command will have no effect

if an ADC is taking place

(conversion in progress or complete and value not yet read from buffer). The

display control consists of two 9-bit DAC's and scope blanking facility.
The axis organization for display is shown in Figure 2-2.

Loading the Register X with DXC DXL and Y with DYC DYL drives the display as shown
in Figure 2-2.

Intensification is accomplished with 6304 or 6314 (DIS

6304).

The commands DCX (Display X-Axis Clear-630I) and DYC (Display Y-Axis Clear-63I I)
clear the X- and Y-registers (to 000), and set X-OUT and Y-OUT to -5V.
effect.

Power clear has the same

The IOT's DXL (Display X-Axis Load-6302) and DYL (Display Y-Axis Load-63I2) load from

the accumulator into the X- and Y-registers

(AC bits 3-“ to X and Y bits 0-8).

Since 000 inthe X-

and Y-registers implies half—scale, AC bit 3 is complemented before being transferred to the X-register

(half—scale on X is represented in the AC as 400).

2-3

YOUT

0,377

0.0

777,377

————————

I
l

l
l

l
I
—10v

0,—377

XOUT=

-10V

777,~377
0V

NOTES

Figure 2-2

SYSTEM

REVERTS

DYC

POWER CLEAR

UNDER

DXC;

Display Axis Organization

If an ADC conversion is in process (a convert pulse has been given but RADC or CLER has

not) then the display control instructions DYC, DXC, DIS DXL and DYL will have no effect. Thus,
in automatic conversion mode, an inadvertent diSplay command will not destroy the conversion.

Brightness control is set from MB bits IO and II when instruction DSB (6324) is given.

(Optional

option XR)

IOT's 6304 and 6314 both intensify a point; however it is obvious that within the structure

of PAL III (symbolic machine language assembler, see DEC document Digital-8-3-5), it is only necessary to specify one mnemonic

(DIS

6304) to handle both sequences of micro instructions:

DXC DXL

DIS and DYC DYL DIS.

2.6

ENABLE REGISTER BIT CONFIGURATIONS
Enable Register flip-flop outputs, control certain optional modes of operation

A description

of the Enable Register bits and how they are set from the AC with the instructions ZTEN OTEN is shown
in Table 2-2.

Table 2-2
Enable Register

“£02?

2:215?

SKEN

Slows RC Clock rate by Factor of 8

CVEN

Conversions initiated by RC or external clock pulse

RKEN

RC Clock flag causes interrupt

XKEN

Crystal clock Flag causes interrupt

EREN

ADC timing error causes interrupt

ADEN

ADC Done flag causes interrupt

(option XR)

(aption XR)

(option XR)

EXEN

External clock available as RC timer.

Sl , S2,S3 can cause

interrupts.

CNEN

RC counting chain enabled

Set pulse channel 0 (SO) Flag to l

R4, R2, and Rl may (if implemented) be used to provide logic control of digital devices (e.g. relays).

2.7

CLOCKS AND SCHMITT TRIGGER INPUTS

There are four instructions concerned with the two clocks in the AX08.

Crystal Clock:
IOT 632i

IOT 6352

Skip on crystal clock Flag
Clear crystal clock Flag

RC or External Clock:
IOT 634i

IOT 6352

Skip an RC clock flag
Clear RC clock flag

The crystal clock Flag
Enable Register

l will cause an

interrupt request to be generated it bit 3 of the

.Note that there is no way to stop and start the crystal clock and to absolutely

synchronize the clock. with a program.

The sequence

CLXK
SKXK

JMP.-l
will synchronize within a jitter of 0

to 5.75 ps

(i30%).

2-5

The RC clock flag

T will

cause an

interrupt request to be generated it bit 2 of the Enable

The rate of clock pulses can be changed by a Factor of 8 by changing bit 0 of the Enable
Bit O

l selects the slower speed.

Power clear sets bit 0

By turning the RC counting chain off and then on (OTEN with AClO) program-RC clock

synchrony is possible.
The ADC may also operate in synchrony with the RC clock by setting enable register bit
1

RC clock pulses, if so enabled, cause an A/D conversion, starting at the RC pulse time.

This

eliminates the jitter characteristic of programmed ADC control.

The ”external" input on the front panel can be used as an RC clock by setting bit 9 (l) in
the Enable Register.
to enable

interrupts from pulse inputs Sl

SO, Sl
XRIN.

(It the user wishes, RC clock may be disabled by bit 10 (0).

$2, or 53.

52, S3 and the ”contingency" inputs may be read into the AC by the instruction

(S3 and the ”contingency" inputs C0 through C7 are Optional, part of option XR.)
51 through S3 are set by front panel

Bit 9 (l) also serves

inputs to Schmitt triggers.

CO through C7 are set by

digital logic level OV. $0 is set under program control via the Enable Register.

ENABLE

ll(l).

50 through S3 and CO through C7 are cleared by setting corresponding bits in the AC
and executing the instruction XRCL.

the bits in the register
events

Note that in the microprogrammed sequence:

XRIN XRCL, only

l, at the time of the XRIN are cleared by the XRCL. This prevents missing

that occur in the 2 ps between XRIN and XRCL (provided that the maximum rate on any single

input does not exceed the programmed sampling rate on the register).

2.8

,MULTIPLEXER AND ADC
Power clear sets the multiplexer register to Os.

until the

The ICMX instruction increments this register

largest implemented channel number is reached. The next ICMX resets the multiplex register

to channel

0.
The instruction ACMX iam sets the contents of the AC into the multiplex register.
RADC clears the accumulator and the Flag ADCIP then sets the AC with the contents of the

ADC buffer.

ADCV initiates a conversion and sets theflag ADCIP(l)
the same action if auto conversion mode is enabled CVEN(l)

17 ps later, the conversion is complete

and the ADC DONE Flag is raised which causes an interrupt if ADEN(l)

SKAD senses the state of ADC DONE.

(or external) clock pulses cause

(see Table 2-2).

Skip is on ADC DONE(l).

ADC DONE flag.

2-6

RADC will

clear the

The IOT's ACMX,

RADC, and ADCV may be microprogrammed since ACMX iam sets the

multiplex register and RADC iam sets the AC. Reading of conversion result on one channel and initiation of conversion on another may all be done in one instruction

If conversions are done at a rate that does not permit the operating program to read the

result before initiation of another conversion, the Flag "ADC Timing Error" will be raised.
may be sensed by the instruction SKER.

it EREN(l)

ENABLE 4(1).

Skip is on ADC ERR(l).

This Flag

ADC ERR“) will request an interrupt

ADC ERR may be cleared by the instruction CLER (which also clears ADC

DONE and ADCIP).

ADCIP(l) disables the display instructions 630X and 63lX.
Front panel analog knobs are connected to channels 34, 35, 36 and 37 (from top to bottom)

DIAGNOSTICS

2.9

Chapter 4, Maintenance, contains descriptive material on diagnostic testing philosophy for
the AX08

CHAPTER 3
PRINCIPLES OF OPERATION

3 .l

BLOCK DIAGRAM

The major Functional elements oF the system are shown in Figure 3-1 , AX08 Block Diagram.
All AX08 operations are controlled by the computer program; decoded IOT's provide the commands
that initiate ADC or DAC operations, and skip and interrupt request logic alerts the computer to
conditions in the AX08.

Analog inputs are processed through preamplifiers, multiplexers, and sample and hold circuits to a comparator

(in the ADC Control).

Successive approximation is achieved by the Y-OUT

analog equivalent oF the digital value in the Y-register being Fed back to the comparator to control
The X-register keeps track oF the step number in the approximation

the input to the Y-register.

Final

output value oF the ADC is the content oF Y-register which is sent to the computer via the input mixer.
DAC For display, is accomplished by transfer oF data words From the computer AC to the Xand Y-registers where the ladder networks provide the Y-OUT and X-OUT analog equivalents as out-

puts to the

display. The display control (with option XR) provides three diSplay intensity levels; bright,

normal, or dim.
The system has two clocks:

crystal controlled clock that is set to ICC ps and an RC timing

clock that is variable From roughly 20 ps to 25.

The crystal clock can be used to calibrate the RC clock.

The external register provides a buFFer For inputs 50 through 52, ($0 is sync
9M) and as

part oF option XR, S3 and 8-bits oF digital inputs
.

The IOT decoder decodes IOT instructions From the computer to control AX08 operation

together with the l2-bit Enable Register. The Enable Register provides Function control levels which

selectively enable interrupt conditions and in general, control optional modes oF operation.

3.2

IOT DECODING

Generation oF all IOT commands For the system is shown in Figure 3-2.

Memory buFFer bits

6, 7 and 8 From the computer provide the 3-bit cOde For generation OF 100 through 107, and memory
buFFer bits 3, 4 and 5 when Oll enable the decoder gates.
with the IOP timing pulses
For system operation

The decoded IOO through IO7, in coniunc-

l, 2 and 4 From the computer, generate the IOT and maior control commands

Table 2-l presents the generation and operation oF all IOT's.

3-]

(TO OSCILLOSCOPEI
Z

""I

DISPLAY CONTROL

__.._J

INTENSIFY

—I>%

x-REGISTER

L
r
I
P

Y—OUT

"—‘——I_°—’A_:I=

SAMPLE

—H

Y-REGISTER

_
,

AND
HOLD

IOT DECODER

COMPARATOR

p—-——

Aoc CONTROL
_

CHANNEL

SELECT'ON

EXTERNAL

(H }————<>—.l PL
A

[VARIABLE I.
I CLOCK r

Z-S

IO LOGIC

—>

RANGE
CRYSTAL

SCHMITT
TRIGGER

SO
s

ENABLE

Ii;

‘

ACCUMULATOR

F"“1
SCHMITT
TRIGGER I“"‘

—-——-—_.I

___

__I

INPUT
MIXER
I

I
I

———————>‘

——

CR0 .
.1
I

———-—————q

:~::

'CONTINGENCY" REGISTER

7 I

A—
\l

I._I
s2

INTERRUPT SKIP

—>

so@——
s1

—>

CLOCK

FINE

————.|_-_J
EXTERNAL
REGISTER

Figure 3—1 AXO8 Block Diagram

TYPICAL

DECODER
COMMAND +MB 6,7,8

000$

000

-———

001

—

-—

—

010
011
100
101

110
111

DEVICE CODE
011

AND

IOT DXC

104

—r>
w—D 105
1—D

106

1—. 107

102

——m

1———> DIS GRP

100 ——>

105
—-———-—. IOT DSB

IOP4

———H

—————>

IOT Dxc

10131 ——>

103
AND

‘———————>

IOT DXL

IOPZ ———->

————————>

XTAL CLK (01
(IOT CLXK)

_.______.

RCLK (O)
(IOT CLRK)

105
AND

-——————-—.

IOT XRIN

10P1—-—D

100 —>

AND
IOP 2

103 —.
AND

8'8

——>

4—» 103

——q
0R

101

—1--D 102

3,4,5

100

100————

TL.

AND

IOP 4

IOP 2

AND

———————D IOT SKAD

IOP 2

106

104

107

1 AND

*—-. IOT RADC

OR
101

IOP1

——>

101

——>

AND

———-——§ IOT DYC

102 ———>

,——————> IOT ZTEN

——>1

IOP 1

104
AND

——>

AND

.—————T

AND

IOT

AND

-—-> 10T SKER

IOP2

MBQ(O)

OTEN

AND

1——————-’

IOT ACMX

AND

———————>

IOT XRCL

Figure 3-2

IOP 1 —u

-———————D IOT CLER

IOP1——-D
——h

L———> IOT ICMX

103

AND

AND
——u

AC CLEAR

105 —.

102 ———H

IOT ADCV

107 ———u

—> IOT SKXK
IOP4

r—>

106 _.
AND

IOP2

AND

IOP 4 ————-——u

————-—> IOT DYL

IOPZ ——>

M89101

‘—-————-D IOT SKRK

104

AND

10P1’

AND
10P1

IOT Decoding Logic

IOP 4

——>

3.3

CLOCKS

3.3.]

Crystal Clock
The crystal clock serves as a timer and provides a pulse every TOO ps to set the XTAL CLK

flag (flip—Flop) (Figure 3-3). The state of the crystal clock flag is used by the IOT SKXK (skip on

crystal clock Flag) to cause a skip request if the flag is set.
'

IOT SKXK is caused by BMB bit 9(0) and

the combination of 102 decoded in the decoder (MB 6, 7, 8 as CW) and the IOP 1 pulse from the com-

puter.

To cause an interrupt request, the l state of the flag is ANDed with XKEN(l) from the Enable

XKEN

—‘> INT REQ

AND

L—D SKIP REO

CLXK

IOT

Figure 3—3

3.3.2

AND

XTAL CLK
FLAG

100JJSEC

IOT

(1)

SKXK —D‘

Crystal Clock Logic

RC Clock

The RC Clock consists of a 5-stage counter, count control

terrupt request logic.
can

logic, and output skip and in-

The clock's counting rate is adjustable by front panel control and the RCLK flag

be set at the end of either 32 or 4 pulses From this counter chain

The operator can control the RC clock pulse rate by using the timing control RANGE switch
and the FINE

(potentiometer) adiustment in the front panel.

Variable Clock that produces 100

These adiustment inputs control an R401

pulses From a stable RC-coupled oscillator.

The RANGE switch

selects one of ten capacitor controlled Frequency ranges; the FINE control permits fine adjustment to
the desired pulse rate to provide the CNT CL pulses to the counter.
As shown in Figure 3—4, it the Flag

(flip-flop RCLK) is cleared and SKEN (l) is present (from

the Enable Register, caused by IOT OTEN and ACO(l)), then the RCLK flag will be set every 32-clock

pulses (enabled by IOT OTEN and AC bit lO(l) in the Enable Register).

It SKEN

(0) is present (from

the Enable Register by IOT ZTEN, which commands reset it AC bit is 0, and AC bit 0 (O), the RCLK

flag is set at the count of tour in the counter.

3-4

SKEN (1) ———->

IOT SKRK

AND

l—>

SKIP REQ

AND

l—p

INT

25::

SKEN (0) —D

RANGE

FINE

SPEE
CLOC
RKEN

REC

(1)

EXEN (1) -——D
AND

'————-——~———p

RCT ICK

EXCK —'>I

RC Clock Flag

Figure 3—4

Logic

Whenever the EXEN(l) from the Enable Register is present,

(set by IOT OTEN and AC 9(l)0

and positive going external clock pulse EXCK arrive, the flag RCLK will be set.

The state of the flag may be tested by the computer command IOT SKRK(skip on RC clock

flag).

An interrupt request occurs when RKEN

(T) from the Enable Register (set by IOT OTEN and

AC2(l)) and the RCLK flag is set.

3.4

ENABLE REGISTER

The Enable Register is used to:

Selectively enable interrupts from the ADC, the ADC timing error indicator,

crystal controlled clock, the RC clock, and the Schmitt triggers;
I

Initialize and run the RC clock;
_

Shift between two speeds of the RC clock, one 8-times faster than the other;
Provide for automatic initiation of ADC conversion upon receipt of every RC flag setting

pulse;
Enable an external clock pulse to set the RC flag instead of the RC timer provided;

Control 3 digital outputs (Optional
The Enable Register control

level

option XR)

flip-flops

are

reset under control of

IOT ZTEN

(zeros in

the AC clear corresponding bits in the Enable Register) ,- and are set under control of IOT OTEN

(ones

in the AC set bits in the enable) as shown in Figure 3-5.

Three bits of the Enable Register are reserved for the optional digital outputs

These bits, as

with other bits of the Enable Register, are set with the combination of instruction ZTEN OTEN

The effects of the Enable Register are described in Chapter 2 (Paragraph 2.5).

IOT ZTEN

IOT ZTEN
AND

AND

0 —> $st (0)

Aco (O) —u
$st
IO T 0 T EN

ADEN

—.

IOT OTEN

SKENI”

‘

AND

—.l

IOT ZTEN

—v

AND

AND
AC1 (D)

0 ~—-»

—>

9’5le

AC6lO) ——u

CVEN

IOT OTEN ——>

‘

IOT OTEN

csz 111

AND
A02 (01 ——>

AND

0 ———-D RK EN (0)

R2
IOT OTEN ——>

xDT OTEN

AND

1
RK F. N 1)

——> R2“)

—> R1 (0)

——>

AND
AC7 (1) —>

AC2 (11 —>

IOT ZTEN ——>

—>
AND

AND
XKEN (01

D —>

AC8 (01 —u

AC3 10) —>

XKEN

107 OTEN

_.‘

)(KENH)

AND

Acsm —u

Rlll)

Acam —.

—-—.

IOT ZTEN

AND
AC4 (0) —->

—u

AND

o ”T, EREN l0)

——->

D —p

AC9(O) %

EREN

:xeN 10)

EXEN
.

1or OTEN __.

EREN (1)

AND
AC4 (11

o ,_. R2 (0)

ACT (01 —~

RKEN

IOT OTEN

R4“)

———u

IOT ZTEN

IOT ZTEN —u

lOT ZTEN

AND

AC6 11)

Ac1111—u

IOT OTEN

—. R4 (0)

AND

IOT ZTEN

ADEN (1)

AND
Acs (11 —.

Aco (11 —>

IOT ZTEN

0 a ADEN (0)

AC5 (0) —~

‘

AND

—> EXEN (1)

mm) —>

-——9

IOT ZTEN —AND

CNEN (0)

ACIO lo) ‘—.

CNEN
tOT OTEN ———’
1

AND

CNEN (1)

A010 (i) —.

Figure 3-5

3.5

CONTINGENCY REGISTER

Enable Register

OPTIONAL (OPTION XR)

The contingency register Flip—Flops CRO through CR7 are set by CO through C7 inputs applied

through the connector on the control panel. The basic logic is shown on Figure 3-6.
are

3.6

sent to the AC through the input mixer

by IOT XRIN

The CR outputs

SYNCHRONIZATION OR "SYNC”
A level may be output on $0 (sync channel) by the instruction OTEN with ACT I (l) as shown

in Figure 3-7.

Flip-Flops SI and 52 are set by the output of Schmitt triggers.

The inputs and lower

threshold levels For these Schmitt'triggers are available on the front panel of the AX08.

part of option XR, as are the contingency inputs (CO through C7)

Sync $3 is

IOT XRCL

IOT XRCL —.1

AND

0 -———D CRO (0)

AC4 (1) —'

—u
o

AC6 (1) —.

——> c R4 (0)

CR4

CRO

—D CRO(1)

CO——-—-———’

—> CR4 (1)

—-—> CR5(O)

—> C R51)

—> CR6(0)

IOT XRCL —u

IOT XRCL —->

AND

0 r-—> CR1 (0)

AC5 (1) —>

AC9 11) —>
CR5

CR1
1

—. CR1 (1)

—-'> CRZ(O)

C1—.

IOT XRCL

AND

AC6 (1) -—DI

mm (1) —>
CR6

CR2
_.

C2—~—--D

-—-D CR2(1)

——> CRem

—§ CR7(O)

—> c R7 1 1 1

‘

IOT XRCL

IOT XRCL
AND

AC7 (1)

AND
0 —-> CR3 (0)

mu m —>

CR3

C3 -—->‘

CR7
CR3 (1)

Figure 3-6

10 T

‘

Contingency Register

XRCL

AND

——>

AND

1—.

ACO(1)
so
I 0T OTEN

»—> so

AC11(1)

0-»
AND

a
o

AC1(1)

PULSE1

TR LEVEL1

ST.

—>

AND

—’

—> 51

‘

0—.

A02“)
52

PULSEZ

‘

$.T.

—>1

TR LEVELZ

AND

Acsm ——>
33
PULSE3 ——o

1
—.

ST.

TR LEVEL 3 —.

Figure 3-7

"Sync

3-7

Channel Logic

IOT

RESET

ACMX

MPX

)

MXA—‘
A

AC 7 (O)

—>

CHANNEL

AND
—> MX-A

._.

UNIT

MXBj
CHANNEL

—>

4 -CHANNEL

—> MX-B

AND

—> MX-C

AC8 (0)

2
3

MPXO

AC7 (1)

0 —.

—.

AND

4-CHANNEL
U NIT

MPX1

AC8 (1)

—u

DECODER -—-> MX-D

MXCj

AND

CHANNEL 10 —.

—> MX-E

AC9 (O) ——->

8-8

——> MX—F

—. MX-H

—>(

4-CHANNEL

UN IT

MPX2

AC9 (1)

MX D

CHANNEL 14 —D
15

4-CHANNEL
UN

AC10 (O)

AND
> MXO

MX E

AND
MPX3

CHANNEL 20 —.

AC10 (1)

2‘

AND

4-CHANNEL
UNIT

22
AND

AC11 (0) )

)——-. MX1

AND

MXF—l

3 MXZ
MPX4

AND

CHANNEL 24
25

AC11 (1) i

26
27

AND

—-’ MX3

IOT ICMX
NEXT MX OK
I06

AND

Figure 3-8

Input Channel Selection Logic

—‘I

4-CHANNEL
UNIT

SELECTED
CHANNEL
INPUT

3.7

INPUT CHANNEL SELECTION

The multiplexer register is iamset from the AC7 through II with IOT ACMX (Figure 3-8).
The register may be incremented by the IOT ICMX.
channel number implemented at each installation.

A diode card (W002) is cut to decode the highest

If the highest channel number is reached, the

multiplex register is reset to zero at the next ICMX. Thus, for all but the highest channel number in
the MPX register, NEXT MX OK is available and ICMX counts the MPX register.

In the highest chan-

nel , NEXT MX OK is not present, therefore ICMX will not count the register but instead generates
RESET MPX, which sets the register to 0.

MXO through MX3 select the channel within a AI30 multiplexer module.
MXA through MXF select the channel group (multiplexer module) if option XM is

implemented.

MX-H

selects the multiplexer module assigned to the Front panel knobs.

3.8

ANALOG-TO-DIGITAL CONVERSION
The overall Function diagram and the major timing of the analog-to-digital conversion

(ADC) operation are shown in Figures 3-9 and 3—I0 respectively.
approximation type

ADC

The converter is a 9-bit successive

HOLD

TRACK————————
MSB

T‘wl

DONE

Figure 3-9

Analog-to—Digital Timing

3-9

L i

‘L L i

IOT RADc

[
‘ >_
.! >’_
E

CLR Ac

SAMPLE a. HOLD
5

COMP—

MULTI—
PLEXORS

TRACK

ARATOR

0
n

Y-OUT

0——> HOLD

D/A

INPUT
MIXER

(Y-OUT Is
POSITIVE)

TOO

:>AC

ADC GO

IOT

ADCV

Y-REGISTER

CERR

AND

ADC so
‘

‘

(SET-X,SET-Y)

SKAD

‘@

CVENH)

CVT 2

__.T

AND

x— REGISTER

RCTICK

CVT 1

ADClP( m

(FROM Rc OR
EXTERNAL CLOCK)

01-8

INT REQ

T
CLOCK)

(D
AND

CONVERT

EREN

M88
DELAY

IOT

SKER

Q——-

1500

ADCERR
HOLD

1—.
0

AND

L.
AND

ADC DoNEm —>

“"1"

IOT CLER

IOT RADC
ADC GO

IOT CLER

Figure 3-10

Analog-fo-Digifql Conversion

REQ

t f f f J

ADEN (1)

ENAaLEs

AND

SKP
’D A

’b A

750 ns
CLOCK

SKP REQ

00%;

—>

INT

REQ

The ADC in the AX08 has preamplifier input channels that accept ii .024V full scale.

The

input channels and multiplexing are available in multiples of from four to 24 channels. Channel select

signals are applied to all multiplexer modules (a module switches 4 channels).
The conversion sequence begins by a clock pulse enabled by CVEN
a

computer command ADCV and ADCIP (0).

(l) and ADCIP (0) or by

This generates ADC GO, setting the sample and hold in

the track state, which sets the X- and Y-registers to 000 (half analog scale).

2 ps

later, the sample

and hold returns to the hold state and a l .5 ps delay provides settling time for the MSB

(most significant

bit) decision. When the l.5 ps times out, the CV clock is enabled to generate 9 CVT 1's and CVT 2's
as

shown on the timing diagram.
A CVT l

pulse shifts the X-register one place to the right as shown in Figure 3-] l

complemented before shifting to Xl
through X8 into ADC DONE

X0 is

When the bit originally set to 0 by ADC GO is shifted (as a

the conversion is complete and terminates at the next CVT2 pulse.

l)
CVTl

and CVT2 pulses are alternately generated (as shown on the timing diagram) by clock pulses which also
cause

generation of STROBE COMPARE pulses.
In the conversion process, the X—register serves as a step marker.

The active X bit is used to select which bit of the Y-register will be

through the X-register by CVTl

set by CVT2 and which bit will

be cleared by CERR.

the DAC.

One set bit is stepped

The X-register is then shifted by CVTl

CVT2 and the X-register generate test values for

Slightly before the next CVT2, Y-OUT-from the

DAC ladder network is compared with the sample and hold output in the comparator.

If, as a result,

Y-OUT is too positive, STROBE COMPAR generates CERR clearing the test bit set at the last CVT2 or,
for the first decision, sets to T.

This is done by using the X-register to point to the last test bit.

Then

CVT2, slightly after CERR time, sets the next test bit in the Y-register (CVTl has shifted the X-register

right).

In this way, all bits of Y are successively set and

reset.

After 8 shifts, CVTl and X8(l) set ADC DONE.

3.9

(if this results in Y-OUT too positive) are

DISPLAY CONTROL

D/A ladders (X and Y) for display control

reSpectively.

are

cleared by pulses ”SET X” and "SET Y"

These are generated by IOT DXC and IOT DYC ifthere is no A/D conversion in progress

(ADCIP(0)) (See Figure 3-12).

IOT's DXL and DYL generate LOAD X and LOAD Y to transfer from

the AC3 through ll into X0 through X8, Y0 through Y8 (again if ADCIP(0)).

AC3 is complemented

before setting X0.
If option XR is implemented, DB-register and associated delays are installed

cleared to O which selects normal

DB is power

intensity (also selected at all times if XR not implemented). This

OUT

10V REF
TO

LADDERS

AC+t
1

SET x

x111)

x211)

CVT 2

x311)

x111)
LOAD Y

AC3“)

“-8
1

7L3]

AhL

AC4“)

ACSU)

x511)

{pi}

1
Y8

‘J
1A}

{‘1‘}

xs11)

ACBU)

xs11)

fl]

AC7“)

,L'J—‘Al

x711)

[JD

x411)

EFL

D
Y7

'LlJ—‘Al

xe11)

AC 6(1)

1
Y6

‘LAE

x311)

71-1 A I,

x511)

{1:}

x211)

.LIJ-IAL

x411)

1
Y4

CERR

x711)

xa11)

FA'L

HA‘L

AC9“)

AC‘MG)

‘

x0;

SET x

I!“

CVT1

x111)

xom)

x311)

x211)

x11D)

xe 11 )

x2111)

x31D)

x411)

x511)

X4(@)

x510)

flfl

xe11)

x711)

X6(0)

x7110)

LOAD x
AND

AND

Ac411)

A0511)

A0611)

Ac711)

AC8(1)

AND

AC9(1)

Ac1o11)

AND

AC 316)

Figure 3—H

X- and Y- Regis’re rs

setting of DB disables BRIGHT and DIM intensity (see Figure 3—13).

Disabling may be removed by

setting either DBO(l) or DBl(l). This is done by strobing BMBIO and complement of BMBll
upon IOT DSB.

into DB

Thus,

DSBO:

DIM

DSBl:

NORM

DSB2:

BRIGHT

DB(Ol)

DB(OO)

—

DB(IO)

IOT

IOT DXC
AND

ADCIPm)

ADC

35.

AND

‘

SETY

ADCIP (D) —-

—>

(SO—J

DYC

ADC

’b

—.l

IOT DYL

IOT DXL
AND

a» LOAD x

AND

L——————> LOAD Y

ADCIPlOl .._..

ADCIPM) ——D

Figure 3-l2

Display Command Logic

INPUT MIXERS

3.l0

ICT's RADC and XRIN strobe contents of AX08 registers into accumulator as shown in
Figure 3-l5. RADC sends AC CLEAR with data on input mixers. AC CLEAR, causes lOO ns pulse,

clearing AC.
100

In PDP-8, the 500 ns delay insures that data is still available at AC when the internal

clear pulse ends.

In the PDP-8/I these pulses are examined at IOP strobe time, the AC is

disabled, and the I/O bus enabled

buffer as a signed 2's complement,

l2-bit, right-justified word.

the transfer bus.

‘(50 through 53, CRO through CR7) into AC as shown.

Sign extension is performed, loading ADC
XRIN strobes entire external register

ADCIPU)

INTENSIFY

NORM

(088 (1)
BRIGHT

(DSB(2I
DIM

(088(3)

INTENS
DISABLE

BRIGHT

DISABLE

IOP 4

DIM

DIS GRP

MBIIII)

MBIIDM)

IOT DSB

M310“)

Figure 3—13

MBI‘IIID)

In’rensi’ry Logic

D/A

Y- DEFLECTION

D/A

X- DEFLECTION

LADDER

SET

—

I
BAC

BAC4“)
BAC 3 (0)

3 (I)

500

nsec

—

I
AND

AND

LOAD X'—‘.'

Y -——-.I

Figure 3-I4

RADC

AND

LOAD

Display Registers

IMOQ

IMQI

IMDZ

1M9?)

IM@4

IMOS

XMQG

IMO7

IM08

IMQS

IMID

IMH

AND

Y0“)

Y1“)

Y2“)

Y3“)

Y4“)

Y5“)

Y6“)

Y7“)

Y8“)

Y0“)

FROM Y REG

IMDO

IM¢I

IMEZ-

$0“)

$1“)

$2“)

IM¢4

IM¢5

IM¢6

IM¢7

IMQB

IM¢9

IMID

IMII

CR9“)

CRI“)

CR2“)

CR3“)

CR4“)

CR5“)

CR6“)

CR7“)

IM¢3

IOT XRIN

$3“)
#/

SYNCHRONIZATION (OR
SYNC) CHANNELS

CONTINGENCY

(OPTION

Figure 3-I5

Inpu’r Mixer

XR)

CHAPTER 4

MAINTENANCE

4.I

INTRODUCTION
This chapter contains the information required for maintaining the AX08 System when

operating with a PDP-8 or 8/1 programmed data processor.
Preventive maintenance includes such routine periodic checks as, visual

inspections, stand-

ard cleaning procedures, adjustments, and the occasional running of diagnostics to expose weakened
conditions before they become malfunctions.

Both troubleshooting and preventive maintenance include procedures that range from basic
power

supply checks to intricate logic checking techniques involving programmed operation (diagnos—

tics) of the processor (PDP-8 or PDP-8/I).
For a detailed understanding of diagnostic procedures, reference should be made to the

pertinent processor maintenance manual and applicable software documentation.
The maintenance equipment specified in the PDP-8 Maintenance Manual with the addition
of a precision voltage supply (EDC VS-ll

equivalent), is adequate for performing tests on the LAB-8

system.
Detailed designations and location information of all modules

are

and assemblies in the system
presented on drawings D-MU-AXO8-0—II and A-PL-AXO8—0-II listed in Chapter 6. All input/

output connectors with pin and signal information are shown on drawing D-BS-AXO8—0-9 in Chapter 6.

4.2

DIAGNOSTICS

The AX08 diagnostic

(MAINDEC 8/I-D6AA-D) tests the functions described here

The

operation of this diagnostic is described in the writeup supplied in the Software Kit.

4.3

CALIBRATION
In an Operating system,

(with part III of the AX08 diagnostic) readings of 0000. iI/Z LSB is

produced with 0V i2 mV (offset); 0376 iI/Z LSB with 1.016V i2 mV (gain); and 7402 iI/Z LSB with
-I .016V i2 mV.
tion

Adjustment of the A202's may be necessary from time to time to provide this calibra—

GAIN

//-376

OFFSET

+376

“0'

AZOZoo

/
OFFSET

Channels 34 through 37 (front-panel knobs) may be used to set up the A401 if it should

l/2 to l turn From Full stop in either direction should range the converter from

require readiustment.
-376 to 740i

If this cannot be

set to convert to 0376.
to convert to 7402.

done, set the pot to 3/4 turn from Full clockwise, and adjust A40l off-

Then set the pot 3/4 turn From Full counter—clockwise, and adjust A401 gain

Repeat until both end conditions are met.

CHAPTER 5
ENGINEERING DRAWINGS

This chapter contains copies of all engineering drawings and replacement schematics necessary to understand and maintain the Type AX08

Laboratory Peripheral System.

The engineering drawings

supplied here are in addition to a complete set of drawings supplied with each system

Should any

discrepancy exist between the drawings in this manual and those supplied with the equipment, assume
that the drawings supplied with the equipment are correct.

Drawings are listed below in the order in

which they appear in the manual.

Engineering Drawings
Drawing No
D—BS-AXOS-O—l

Title

Revision

_P_age

(Sheet I)

IOT Decoders

5-3

D-BS-AXOB-O—I (Sheet 2)

IOT Decoders

5—5

D-BS-AXO8-O—2

Timers and Synchronization or

D-BS—AX08-0-3

ADC Control

5-9

D-BS-AX08-0—4

Enable and Contingency Registers

5-H

D-BS-AXO8-O-5

Buttered AC Bits and MPX IOT's

5—13

D—BS-AXO8-0-6

Scope and Multiplexer Controls

"Sync" Channels

5—7

5—15
\

D-BS-AXO8—O-7

Input Mixers

5—1 7

D-BS-AX08-0-8

X and Y Registers

5-l9

D—BS-AXO8—O-9

I/O Connectors

5—21

D-BS-AXOB-O-IO

Additional Channels (Option XC)

5-23

D-MU-AXOB-O-ll (Sheet 1)

AX08 Lab Peripheral

(UML)

5—25

D—MU-AXO8-0-ll (Sheet 2)

AX08 Lab Peripheral

(UML)

5—27

D-AD-70q583l-O—O

Control Panel Assembly

D-AD-7005832-0-0

Rear Panel Assembly

‘

5-29

5-3l

Revision

Page

Replacement Schematics
'

Type

Title

A130

Multiplex Linc-8

5-34

A202

Two Analog Preamplifiers

5-34

A40l

Sample and Hold

5-35

Replacement Schematics (Cont)
Title

Type

Revision

Page

A502

Comparator

5-35

A601

Digital-Analog Converter

5—36

A604

Digital-Analog

5-36

A704

Reference Supply

5-37
V

A706

Power Supply for A202

R002

Diode Network

R107

Inverter

R113

NAND/NOR Gate

R121

NAND/NOR Gate

R122

NOR/NAND Gate

R123

Input Bus

R151

Binary to Octal Decoder

R202

Dual

Flip-Flop

R203

Triple Flip-Flop

R205

Dual

Flip-Flop

R302

Dual

Delay Multivibrator

R401

Variable Clock

R405

Crystal Clock

R603

Pulse Amplifier

VV500

High Impedance Follower

VV501

Schmitt Trigger

VV681

Scope Intensifier

ogzmwmwn>wl>gzgm

5-37

5-38
5-39
5-39
5-40

5-40
5-41
5-41
5-42
'

5-42

5-43
5-43
5-44

5-44
5-45
5-45
5-46

5-46

XOT SKER

IOT 5mm

o—AAFT—DXQT

L
WT—DIOT

—4>

ms?

SW7

'N
::C¢(5_<>

Rug

10P2—>A\¢

R\¢7

1032M

109

R\¢7
Arpg

“915)

BMB em

BMB

¢2
¢3

7c¢>

BMB

(251

:0
5

BMB 703

(64

“3

Q35

956

¢7

BMB e<¢>

BMB 80)

10p

4—»

5 ADCV

(\)/\

UVNA

mP\ 4mm;

lOP

A\¢

To Q’ZY

¢¢—<> NV
K
IO gzn

R\¢7

POWER

E
CLEAR —»

‘:

F23;

¢e
N
WT—aro

XRIN

o—M—T—R

10P4§va

edibmA

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ITEM DESCRIPTION CONNECTION
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TABLE

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BRN

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832R

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D32J

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GND

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R202 Dual

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RIG

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R302 Dual

Delay Multivibrafor
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R405 Crysfol Clock

5 -44

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0-664

FOR VALUES 0F

GND

RI3

l0,000
04
DEC 2894-28

EC2894-28

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DIODES ARE 0-6
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R603 Pulse Amplifier

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l,500

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l,500
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l,500

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3,000

1,500.

0— 654
ARE
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DEC 2894-3

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LRs
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33°

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A HOV (A)
4

|,500
DB

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0662

06
DEC 2894-35
05
DEC3646 -E

POSOTIVE

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mv:
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5,000
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an:

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Scope Infensifier

5—46