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Document:	VAX 11/780 Hardware Handbook
Order Number:	MISC-68417815
Revision:
Pages:	374
Original Filename:

OCR Text

1979-80

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HARDWARE HANDBOOK

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CORPORATE PROFILE
Digital Equipment Corporation designs, manufactures, sells and services computers and associated peripheral equipment, and related
software and supplies. The Company’s products are used world-wide
in a wide variety of applications and programs, including scientific
research, computation, communications, education, data analysis. industrial control. timesharing, commercial data processing, word proc-

essing, health care. instrumentation. engineering and simulation.

VAXII
780

HARDWARE HANDBOOK

The information in this document is subject to change without notice
and shouldnot be construed as acommitment by Digital Equipment

Corporation. Digital Equipment Corporation assumes no responsibili-

ty for any errors that may appear in this manuai.

VAX, VMS, SBI, PDP, UNIBUS, MASSBUS
are trademarks of

Digital Equipment Corporation

This handbook was designed, produced and typeset

by DIGITAL's Sales Support Literature Group
using an In-house text-processing system
operating on a DECSYSTEM-20.

CONTENTS
CHAPTER1 VAX-11/780 HARWARE INTRODUCTION
SYSTEMINTRODUCTION. ...

THE VAX-11/780 CENTRAL PROCESSING UNIT

THE CONSOLESUBSYSTEM...................
THE MEMORY SUBSYSTEM ...................
THE INPUT/OUTPUT SUBSYTEMS .............

CHAPTER2 CONSOLE SUBSYSTEM
INTRODUCTION

... .

CONSOLEINTERFACEBOARD.................
CONSOLEBUS STRUCTURE...................
CONSOLE/VAX-11INTERACTION .............
READ ONLY MEMORY (ROM) .................
THE CONSOLE COMMAND LANGUAGE .......
CONSOLE ERRORMESSAGES.................

CHAPTER 3 CENTRAL PROCESSOR
INTRODUCTION

... e

HARDWAREELEMENTS........ ...t t
PROCESSOROPERATION.................0t

USER PROGRAMMING CONCEPTS ...........
USER PROGRAMMING ENVIRONMENT .........
SYSTEM PROGRAMMING CONCEPTS .........
SYSTEM PROGRAMMING ENVIRONMENT .....

CHAPTER4 PROCESS STRUCTURE
PROCESS DEFINITION ..............oovinnnt.
PROCESS CONTEXT ........cciiivinniiinnn..

ASYNCHRONOUS SYSTEM TRAPS (AST) .......
PROCESS STRUCTURE INTERRUPTS .........
PROCESS STRUCTURE INSTRUCTIONS .......
USAGEEXAMPLE. ..... ... .ot

CHAPTER 5 EXCEPTIONS AND INTERRUPTS
vttt eeeeeaee
INTRODUCTION
tt
e e
INTERRUPTS . oo et

SERIOUS SYSTEM FAILURES ...........onn...
SYSTEM CONTROL BLOCK (SCB) .............
STACKS

SERIALIZATION OF EXCEPTIONS AND
INTERRUPTIONS ... .. e
INITIATE EXCEPTION ORINTERRUPT .........

CHAPTER6

MEMORY MANAGEMENT

INTRODUCTION ... .. 101
VIRTUALADDRESSSPACE.......................... 102
VIRTUALADDRESS ..............
it 104

ADDRESS TRANSLATION .................ccouunn, 105
ACCESSCONTROL .........civiiiiiiiiin., 107
SYSTEM SPACE ADDRESS TRANSLATION
.......... 109
PROCESS SPACE ADDRESS TRANSLATION .......... 111
MEMORY MANAGEMENT CONTROL ................ 115
FAULTS AND PARAMETERS ........................ 117
PRIVILEGED SERVICES AND ARGUMENT
VALIDATION ... . . . i 118

ISSUES ... .

119

CHAPTER7 SYNCHRONOUS BACKPLANE INTERCONNECT
INTRODUCTION ... e 125
SBISTRUCTURE. ...... ...t 126
SYNCHRONOUS BACKPLANE INTERCONNECT

THROUGHPUT

CHAPTER 8

... ... i 145

MAIN MEMORY SUBSYSTEM

INTRODUCTION . ...
MEMORY CONTROLLER ..........................
BASIC MEMORY OPERATIONS ....................

INTERLOCKCYCLES. ...
ERROR CHECKING AND CORRECTION (ECC) ......
MEMORY CONFIGURATION REGISTERS
..........
MEMORY INTERLEAVING
........................
ROMBOOTSTRAP . ...

CHAPTERS9

147
148
149

152
153

153
159

160

UNIBUS SUBSYSTEM

INTRODUCTION ...
UNIBUS SUMMARY ... . ... ... i
UNIBUSADAPTER ...t

163
163
168

SBI ACCESS TO UNIBUS ADDRESS SPACE ........
170
UNIBUS ACCESS TO THE SBI ADDRESS SPACE ......175

UNIBUS ADAPTER DATA TRANSFER PATHS ........
178
INTERRUPTS ... ...
190
UNIBUS ADAPTER (NEXUS) REGISTER SPACE......
194
SBI ADDRESSABLE UNIBUS ADAPTER REGISTERS ..196

POWER FAIL AND INITIALIZATION

CHAPTER 10

................

216

MASSBUS SUBSYSTEM

INTRODUCTION ... ..., 223
MASSBUS ADAPTER OPERATION
.................. 227

CONTROL PATH . ..ot 229
ESS t 229
i
CC
...
MBAA
... .o 231
.
RS
GISTE
NALRE
INTER
CHAPTER 11 PRIVILEGED REGISTERS

e 245
i iiaatt
INTRODUCTION ...t
SYSTEM IDENTIFICATION REGISTERS (SID) .......... 245
CONSOLE TERMINAL REGISTERS .................. 246
CLOCKREGISTERS ... ciiiiiiiie i 247
VAX-11/780 ACCELERATOR ... 250
VAX-11/780 MICRO CONTROLSTORE................ 252

CHAPTER 12 PRIVILEGE INSTRUCTIONS

INTRODUCTION ..t 257

CHAPTER 13 SYSTEM ARCHITECTURAL IMPLICATIONS
INTRODUCTION ..o 269
DATA SHARING AND SYNCHRONIZATION ............ 269
CACHE .ot et 270
RESTARTABILITY . 271
eeees 272
INTERRUPTS ..ttt
R
=T0 ) 21 J R 272
=]
IJOSTRUCTURE ...t 272
CHAPTER 14 RELIABILITY AVAILABILITY
MAINTAINABILITY PROGRAM

nees 275
INTRODUCTION ..ot
nns 275
.coonn
......
......
RES
HARDWARE RAMP FEATU

APPENDIX A

COMMONLY USED MNEMONICS ...t 281

APPENDIX B

INSTRUCTIONINDEX ... 285

APPENDIX C

I/OSPACERESTRICTIONS ... 297

APPENDIXD

INTERNAL DATA (ID) BUS REGISTERS .............. 299

APPENDIXE

ADDRESS VALIDATIONRULES ............coihhnnnn 313

APPENDIXF
VIRTUAL TO PHYSICAL ADDRESS TRANS

LATION

....317

APPENDIX G

OPERAND SPECIFIERNOTATION . ............

...
... 321

GLOSSARY ... ...
INDEX

...

325
353

PREFACE

VAX-11/780 is DIGITAL'’s 32 bit extension to its 11 family of minicomputers. VAX-11/780 is a fully integrated computer system featuring
state-of-the-art hardware technology coupled with a powerful virtual
memory operating system, VAX/VMS (Virtual Address Extension/Virtual Memory system). VAX-11 hardware is characterized by its
flexible instruction set, 32 bit capability, byte addressability, stack orientation, and highly efficient page-oriented memory management
scheme. VAX/VMS is a high-performance operating system designed
to complement the VAX-11 hardware. VAX/VMS encompasses a highly sensitive scheduling algorithm, extensive record and file management capabilities, and virtual memory features achieved by an extremely efficient paging algorithm.

VAX-11/780 is general purpose in nature, with the inherent capability
to deal with a multitude of user environments. Designed to optimize
throughput, the system enables enormous amounts of data to flow
through it swiftly and unobstructed. Data transfers are accomplished
via the 32 bit high speed Synchronous Backplane Interconnect (SBI).
This hardware mechanism ties the system components together by
providing a common point of interface including the communications
protocol. The SBI interconnects the central processor, main memory
(8 million bytes maximum), the UNIBUS subsystem and a mass storage subsystem comprising a maximum of 4.3 billion bytes. VAX11/780 supports a 32 bit word architecture, thereby establishing a
virtual address space of 22 or 4.3 billion bytes for user application.
The VAX-11 instruction set consists of 243 instructions including general-purpose, special function, commercial, and floating point. An optional high-speed floating point accelerator is available for user applications demanding superior floating point performance.

The VAX/VMS operating system is flexible in supporting many user

environments such as time-critical, interactive program development,
and batch, either concurrently, independently, or in any combination.

The VAX-11 handbook documentation set is presented in three books:

e The VAX-11 Architecture Handbook introduces VAX-11 system ar-

chitecture, addressing modes, and the native mode instruction set.

e The VAX-11 Software Handbook introduces the VAX/VMS virtual

memory operating system, it operation, hardware interaction, daia
structures, features, and capbilities.

vii

e This book, the VAX-11/780 Hardware Handboo
k, introduces the
VAX-11 hardware elements, including the high-sp
eed synchronous

backpliane interconnect, the central processor unit,

console subsystem,

MASSBUS

and

memory, and memory management.

UNIBUS

intelligent

subsystems, main

This book describes the first of a series of VAX-11 Processor

s, there-

fore, certain chapters pertain to system wide architect

ure as well as

processor specific information.

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CHAPTER 1

VAX-11/780 HARDWARE INTRODUCTION
SYSTEM INTRODUCTION

VAX-11/780 is a high-performance multiprogramming computer sys-y
tem. The system combines a 32 bit architecture, efficient memor
management, and a virtual memory operating system to provide essentially unlimited program address space.

data
The processor’s variable length instruction set and variety of
effibit
high
e
promot
string,
ter
charac
and
types, including decimal
implecally
specifi
set
tion
instruc
and
re
hardwa
sor
proces
ciency. The
ment many high-level language constructs and operating system
functions.

and
VAX-11/780 is a multiuser system for both program developmentriven
event-d
uled,
y-sched
priorit
a
is
It
on.
executi
system
application
the
system: the assigned priority and activities of the processes injobs
itical
Time-cr
need.
they
system determine the level of service
while
receive service according to their priority and ability to execute,ncy
for
reside
y
memor
and
time
CPU
of
ion
allocat
es
the system manag
normal executing processes.

VAX-11/780 is a highly reliable system. Built-in protection mecha
and
ty
integri
data
ensure
re
softwa
and
re
nisms in both the hardwa
logsystem availability. On-line diagnostics and error detecting and
es
featur
re
softwa
and
ging verify system integrity. Many hardware
power,
the
should
ry
recove
tic
provide rapid diagnosis and automa
hardware, or software fail.

The system is both flexible and extendable. The virtual memory opercan
ating system enables the programmer to write large programstthat
requirwithou
rations
configu
y
execute in both small and large memor
ing the programmer to define overlays or later modify the program to
take advantage of additional memory. The command language

enables users to modify or extend their command repertoire easily,
and allows applications to present their own command interface to
users.

Appendix A contains a table of commonly used VAX-11/780 system
mnemonics.

Introduction

Architecture Overview
VAX is the architecture for the VAX-11/780.
The goals of the VAX
architecture were to provide a significant
enhancement to the virtual
addressing capability of the PDP-11 series consiste
nt with small code
size, easy exploitation by higher-level languag
es, and a high degree of
compatibility with the PDP-11 family of minicom
puters. While VAX-11
is not strictly binary-compatible with the PDP-11
binary code, it does

implement a compatibility mode which executes most

tions.

PDP-11 instruc-

VAX-11 architecture is characterized by a powerful and
complete

struction set of 244 basic instructions, a wide range of

in-

data types, an

elegant set of addressing modes, full demand paging
memory management, and a very large virtual address space
of over four billion

bytes. The native mode instruction set is found in
Appendix B. 170

Space restrictions on the use of the native
mode instruction set is

defined in Appendix C. Arithmetic and logical operatio
ns can be performed on byte integers (8 bits), word integers (16
bits), and 32-bit
longword integers; plus, some instructions can perform
operations on
64-bit quadword integers. Additionally, the Native Mode
instruction

set includes floating point operations, character string
packed decimal arithmetic, and many instruct

manipulations,

ions which improve the

performance and memory utilization of systems
and applications
which can be performed on variable-length bit fields—a
new data type
for the 11 family.

Another significant feature of the VAX-11
architecture is that instruction addressing is virtually arbitrary. This means
that there are no fixed
formats, and no restrictions as to the location
of an operand for a
particuiar instruction or even the instruc

tion itself. Thus, operands and

instructions can begin on any byte address

, odd or even. The result of
this flexibility is that higher-level langua
ge compilers, such as
FORTRAN, can generate code that is optimal
ly smaller in size, very
efficient, and easy to manipulate in the compile
r’s data structures. This
results in greater performance and
lower memory utilization. The

VAX/VMS operating system makes the
hardware work together as

one unit to provide the VAX-11/780 with

its multiuser, multiprogram-

ming, virtual memory capabilities. For further

VAX architecture, refer to the ARCHITECTURE

information concerning

HANDBOOK.

Software Overview
VAX/VMS is the general-purpose operati
ng system for the VAX11/780. It provides a reliable, high-perform
ance environment for the

concurrent execution of multiuser
timesharing, batch, and time-criti-

cal applications. VAX/VMS provides:

Introduction

e virtual memory management for the execution of large programs
e event-driven priority scheduling

e shared memory, file, and interprocess communication data protection based on ownership and application groups

e programmed system services for process and subprocess control
and interprocess communication

VAX/VMS uses the VAX-11/780 memory management features to
provide swapping, paging, and protection and sharing of both code
and data. Memory is-allocated dynamically. Applications can control
the amount of physical memory allocated to executing processes, the
protection of pages, and swapping. These controls can be added after
the application is implemented.

CPU time and memory residency are scheduled on a pre-emptivee
priority basis. Thus, time-critical processes do not have to compet
with lower priority processes for scheduling services. Scheduling rotates among processes of the same priority.

VAX/VMS includes system services to control processes and process
execution, control time-critical response, control scheduling, and obtain information. Process control services allow the creation of subprocesses as well as independent detached processes. Processes can
communicate and synchronize using mailboxes, shared areas of
memory, or shared files. A group of processes can also communicate
and synchronize using multiple common-event flag clusters.

Memory access protection is provided both between and within
processes. Each process has its own independent virtual address
space which can be mapped to private pages or shared pages. A

process cannot access another process’s private pages. VAX/VMS

uses the four processor access modes to read and/or write-protect
individual pages within a process. Protection of shared pages of memory, files, and interprocess communication facilities such as mailboxes
and event flags, is based on User ldentification Codes individually
assigned to accessors and data.

A complete program development environment is offered. In addition
to the native assembly language, it offers optional high-level programming languages commonly used in developing both scientific and
commercial applications: FORTRAN, COBOL, and BASIC. It provides
the tools necessary to write, assemble or compile, and link programs,
as well as to build libraries of source, object, and image modaules.
VAX/VMS data management inciudes a fiie system that provides volume structuring and protection, and record management services that
provide device-independent access to the VAX-11/780 peripherals.
3

Introduction

The VAX/VMS on-disk structure provides a multiple-

level hierarchy of

named directories and subdirectories. Files
can extend across multi-

ple volumes and can be as large as the volume
set on which they
reside. Volumes are mounted to identify
them to the system.
VAX/VMS also supports multivolume ANS format
magnetic tape files
with transparent volume switching.

The VAX/VMS record management input/output
system (RMS) provides device-independent access to disks, tapes,
unit record equipment, terminals, and mailboxes. RMS allows
users and application

programs to create, access, and maintai

n data files with efficiency and

economy. Under RMS, records are regarde
d by the user program as

logical data units that are structured and accesse
d in accordance with
application requirements.
RMS provides sequential record access to sequenti
al file organiza-

tions, and sequential, random, or combined

file organizations.

record access to relative

For further information concerning VAX-11
software and the
VAX/VMS operating system, refer to the VAX-11
SOFTWARE HAND-

BOOK.

Hardware Overview
The VAX-11/780 computer system consists of the

central processing

unit (with integral floating point and decimal and
characte

structions), the console subsystem, the main

r string in-

memory subsystem, and

the 1/0 subsystem. The 170 subsystem include
s the Synchronous
Backplane Interconnect (SBI), the UNIBUS and the
MASSBUS sub-

system.

The SBI is the internal connection path that links
the CPU with its
subsystems. The VAX-11/780 hardware configur
ation is illustrated in
Figure 1-1.
THE VAX-11/780 CENTRAL PROCESSING
UNIT
The VAX-11/780 processor is a 32-bit high-s
peed microprogrammed

computer that executes instructions

in native mode, and nonprivileged

PDP-11 instructions in compatibility mode.

The processor can directly address four gigabyt

es of virtual address

space, and provides a complete and powerfu
l instruct

ion set that in-

cludes integral decimal, character string, and
floating point instructions. The VAX-11/780 includes an 8K byte
cache, integral memory
management, sixteen 32-bit general register

els, and an intelligent console (LSI-11).

s, 32 interrupt priority lev-

WITH FULL

FLOATING POINT,

DECIMAL , AND

CHARACTER

CONSOLE
SUBSYSTEM

CPU

STRING | A |

INSTRUCTIONS

CACHE

MEMORY

MEMORY SUBSYSTEM

256KB | i1

MEMORY

ECC MOS| H

CONTROLLER
PORT FOR —
REMOTE

DIAGNOSIS

LSI-N
MICROCOMPUTER

) UP TO 8 M BYTES
MAXIMUM

FLOPPY
DISK

- - !
F-——

SF=—771 _ MEMORY

=== 3

b—--- 256KB

BL_-}i CONTROLLER I --JECC MOS|
________ -

1/0 SUBSYSTEMS
ONSOLE
TERMINAL

MB(/\s.a)
secC

FPA = FLOATING POINT ACCELERATOR

S DIAGNOSTIC CONTROL STORE
= WRITABLE
WDC
WCS= WRITABLE CONTROL STORE

Figure 1-1

UNIBUS

ADAPTOR

(V.5MB/sec)

UNIBUS

gl>

MASSBUS

{2.0MB/sec)

MASSBUS

ADAPTOR

UP TO 4 TOTAL

VAX-11/780 Hardware Configuration

uononposu)

[ng]

CENTRAL PROCESSING UNIT

Introduction

Figure 1-2 illustrates the elements of the central processing unit.

CONSOLE

SUBSYSTEM

CPU WITH

FULL

FLOATING POINT,

DECIMAL,AND = |

C | CHARACTER STRING | p
S|
INSTRUCTIONS
| A

CACHE

MEMORY

|
|

S
B
I

Figure 1-2

Central Processor

Native Instruction Set — The VAX-11 instructions are an extension of
the PDP-11 instruction set. The VAX-11 instruction set provides 32-bit
addressing, 32-bit 1/0 operations, and 32-bit arithmetic. Instructions
can be grouped into related classes based on their function and use:

Instructions to manipulate arithmetic and logical data
types—These include integer and floating pointinstructions,
packed decimal instructions, character string instructions, and bit

and field instructions.

The data type identifies how many bits of storage are to be treated

as a unit and how the unitis to be interpreted. Data types that may

be used are:

Data Type

Represented As

Integer

byte (8 bits), word (16 bits), longword
(32 bits), quadword (64 bits)

Floating point

4-byte floating or 8-byte double floating

Packed decimal

string or bytes (up to 31 decimal digits,
2 digits per byte)

Character string

string of bytes interpreted as character
codes; a numeric string is a character
string of codes for decimal numbers

(up to 64K bytes)
Bits and bit-fields

field length is arbitrary and is defined

by the programmer (0 to 32 bits in
length)

Introduction

Integer, floating point, packed decimal, and character data are
stored starting on an arbitrary byte boundary. Bit and bit field data
do not necessarily start on a byte boundary. A collection of data
structures can be packed together to use less storage space.
Instructions to manipulate special kinds of data—These include
queue manipulation instructions (i.e., those that insert and remove queue entries), address manipulation instructions, and

user-programmed general register load and save instructions.
These instructions are used extensively by the VAX operating system.

Instructions to provide basic program flow control—These include branch, jump, and case instructions, subroutine call instructions, and procedure call instructions.
Instructions to quickly perform special operating system func-

tions—These include process control instructions (such as two
special context switching instructions which allow process context
variables to be loaded and saved using only one instruction for

each operation), and the Find First instruction which (among other
uses) allows the operating system to locate the highest priority
executable process. These instructions contribute to rapid and
efficient rescheduling.
Instructions provided specifically for high-level language constructs—During the design of the VAX-11 architecture, special
attention was given to implementing frequently-used, higher-level
language constructs as single VAX-11 instructions. These instructions contribute to decreased program size and increased execu-

tion speed. Some of the constructs which have become single
instructions on the VAX-11/780 include:

the FORTRAN-computed GOTO statement (translates into
the VAX-11/780 CASE instruction)

the loop construct (e.g., add, compare, and branch translates
into the VAX-11/780 ACB instruction)

an extensive CALL facility (which aligns the stack on a longword boundary, saves user-specified registers, and cleans up
the stack on return. The CALL facility is used compatibly
among all native mode languages and operating system services.)

VAX-11/780 instructions and data are of variable length. They need
not be aligned on longword boundaries in physical memory, but may

begin at any byte address (odd or even). Thus, instructions that do not
require arguments use only one byte, while other instructions may
7

Introduction

take two, three, or up to 30 bytes depending on the number of argu-

ments and their addressing modes. The advantage of byte alignment
is that instruction streams and data structures can be stored in much
less physical memory.
The VAX-11/780 processor offers nine addressing modes that use the

general registers to identify the operand location. Seven of these are
essentially the same as for the PDP-11:

displacement

(similar to the PDP-11 index
mode)

displacement deferred

(similar to the PDP-11 index deferred mode)

The two new addressing modes are:
indexed

literal

Because the instruction set is so flexible, fewer instructions are required to perform any given function. The result is more compact and

efficient programs, faster program execution, faster context switching,
more precise and faster math functions, and improved compiler-gen-

erated code.

General Registers and Stacks — The VAX-11/780 CPU provides 16
32-bit general registers which can be used for temporary storage, as
accumulators, index registers, and base registers. Although all can be

used as general-purpose registers, four have special significance depending on the instruction being executed: Register 12 (the CALL
argument pointer); Register 13 (the CALL frame pointer); Register 14

(the stack pointer); and Register 15 (the program counter).

Stacks are associated with the processor’s execution state. The
processor may be in a process context (in one of four modes, kernel,
executive, supervisor, or user) or in the system-wide interrupt service

context. A stack pointer is associated with each of these states. Whenever the processor changes from one state to another, Register 14 (the
stack pointer) is updated accordingly.

Introduction

Caches — The VAX-11/780 CPU provides three “cache’” systems—the memory cache, an address transiation buffer, and an instruction buffer.

MEMORY CACHE

The memory cache (typically 95% hit rate) provides the central processor with high-speed access to main memory. The memory cache
reduces main memory read access time from 1800 nanoseconds to an
effective 290 nanoseconds, and has a cycle time of 200 nanoseconds.
The memory cache also provides 32 bits of lookahead. On a cache
miss, 64 bits are read from main memory—32 bits to satisfy the miss
and 32 bits of lookahead.

INSTRUCTION BUFFER

The instruction buffer consists of an 8-byte buffer that enables the
CPU to fetch and decode the next instruction while the current
instruction completes execution. The instruction buffer in combination
with the parallel data paths (which can perform integer arithmetic,
floating point operations, and shifting all at the same time) significantly
enhances the VAX-11/780’s performance.
TRANSLATION BUFFER

The VAX-11/780 provides an address transiation buffer that eliminates extra memory accesses during virtual-to-physical address
translations most of the time (typically 97% hit rate). The address
translation buffer contains 128 likely-to-be-used virtual-to-physical
address translations.

Clocks — The standard VAX-11/780 CPU includes two clocks—a programmable real-time clock used by system diagnostics and by the
VAX operating system for accounting and scheduling, and a time-ofyear clock, which insures the correct time-of-day and date. The timeof-year clock is used by the operating system to enable unattended
automatic restart following any service interruption, including a power
failure.

Writable Diagnostic Control Store (WDCS) — 12K bytes (plus parity)
of WDCS are provided to allow the Diagnostic Console Processor to
verify crucial parts of the system, (i.e., the CPU, the intelligent console,
the SBI, and the memory adapter). In addition, the WDCS can be used
to implement updates to the VAX-11/780’s microcode.
Memory Management — The VAX-11/780 memory management

hardware enables the VAX operating system to provide a flexible and
efficient virtuai memory programming environment. Haraware memory management, in conjunction with the operating system, provides
facilities for paging (with user control) and swapping.

Introduction

In addition, the VAX-11/780 memory management provides four hierarchical modes: kernel, executive, supervisor, and user, with
read/write access control for each mode.

The memory management hardware facilitates the sharing of programs and data, and allows larger program size and increased per-

formance.

THE CONSOLE SUBSYSTEM
The VAX-11/780’s integrated console consists of an LSI-11 microcom-

puter with 16K bytes of read/write memory and 8K bytes of ROM
(used to store the LSI diagnostic, the LS| bootstrap, and fundamental
console routines), a floppy disk (for the storage of basic diagnostic
programs and software updates), a terminal, and an optional remote

diagnosis port.
Figure 1-3 illustrates the console subsystem.

The console subsystem serves as a VAX operating system terminal, as
the system console, and as a diagnostic console. As a VAX terminal, it
is used by authorized system users for normal system operations. As
the system console, it is used for operational control (i.e., bootstrapping, initialization, software update). As a diagnostic console, it can
access the central processor’'s major buses and key control points

through a special internal diagnostic bus. The console allows operator

diagnostic operations through simple keyboard commands.

CENTRAL
PROCESSOR

P%ELE?E

DIAGNOSIS

LSI-11
MICRO -

COMPUTER (R)
Y

FLOPPY

DISK

TERMINAL

Figure 1-3

Console Subsystem

The floppy disk serves many useful purposes. During system
installation, the floppy disk is used as a load device. The hardware
bootstrap reads a file from the fioppy; this file in turn loads the operat-

ing system from the system volume.
10

Introduction

In addition, hard core diagnostics (i.e., those that test “crucial” system
components) are stored on floppy. Testing of the LSI-11 is performed
:
at power up; microdiagnostics are performed on command.

Because the floppy device is standard on all VAX-11/780 systems,
software updates are distributed on this device. Simple commands
typed at the console terminal automatically update the system software from the floppy.

THE MEMORY SUBSYSTEM

The main memory subsystem consists of ECC MOS memory, which is
connected to the SBI via the memory controller, as illustrated in Figure
1-4.

CENTRAL
PROCESSOR
ro— = ]

e ———- h| 1

ECC MOS |-

CONTROLLER
5

=-1

MEMOR

re——--1

=T13:

UP TO 8 M BYTES

MAXIMUM

[.___4ECC MOS o

e e e _ - -)

Figure 1-4

~——- CONTROLLER

256KB

MEMORY

e e—-

Memory Subsystem

The VAX-11/780 physical memory is built using either 4K or 16K MOS
RAM chips. Memory is organized in quadwords (64 bits) plus an 8-bit
ECC (Error Correcting Code), which aliows the correction of all singlebit errors, and the detection of all double-bit errors.

MOS memory may be added in increments of either 128K or 256K
byte units to a maximum of either one or four million bytes per controller (depending upon chip capacity). Two memory controllers may
be connected to a VAX-11/780 system, for a total of either two or eight
million bytes of physical memory. (The minimum memory requirement
is 128K bytes utilizing 4K RAM chips and 256K bytes utilizing 16K RAM
chips.)

The memory cycle time is 600 nanoseconds. This is equal to the mem-

ory access time since MOS memory has nondestructive read-out.
Read access time at the central processor (including SBI overhead) is
1800 nanoseconds. This is measured from the time the processor

transmits a read request until the processor receives all 64 bits of
data. (The central processor always reads 64 bits from memory.) In
11

Introduction

spite of the 1800 nanosecond memory access time, the VAX-11/780
processor realizes an effective average operand access time of 290
nanoseconds, due to the large optimized memory cache.

The memory controllers allow the writing of data in full 32 and 64 bit

units.

Each memory controller buffers up to four memory access requests.
This “request buffer” substantially increases memory throughput and
overall system throughput and decreases the need for interleaving for
most configurations.
Interleaving is possible with two controllers and equal amounts of
memory on each. Interleaving for VAX-11/780 systems should be
used when more than two MASSBUS adapters are connected and the

MASSBUS and UNIBUS devices are transferring at very high rates,
greater than

one million bytes/second. Interleaving is enabled/disabled under program control. It is performed at the quad-

word level (each 64 bits) due to the memory organization. Note that in
most cases interleaving will not be required due to the memory con-

troller’s request buffer.
THE INPUT/OUTPUT SUBSYSTEMS
The VAX-11/780's I/0 subsystem consists of the SBI, and the UNIBUS

and MASSBUS devices connected to the SBI through special buffered
interfaces called adapters. As illustrated in Figure 1-5, each VAX11/780 system has one UNIBUS adapter and can have up to four

MASSBUS adapters.

The Synchronous Backplane Interconnect — The SBl is the primary
control and data transfer path in the VAX-11/780 system. The SBI has
a physical address space of one gigabyte (30 bits of address).

CENTRAL
PROCESSOR

1
s

1.5M BYTES/SECOND

UNIBUS

ADAPTOR

ENIBSSON

8
N

MASSBUS

2.0M BYTES/SECOND

ADAPTOR

MASSBUS

UP TO 4l TOTAL
Figure 1-5

1/0 Subsystem
12

Introduction

Physical address space is all possible memory and I/O addresses that
a processor can access. In the VAX-11/780 system, half of the physical
address space is for memory addresses and half for I/0 addresses, as
illustrated in Figure 1-6.

PHYSICAL MEMORY

1GB

512 MB
(8MB AVAILABLE
FOR PHYSICAL
ADDRESSING)}
512

(30 BITS) fi
1/0 REGISTERS

512M8B

1GB

Figure 1-6

SBI Physical Address Space

Presently, VAX-11/780 will support up to either two or eight million
bytes of main memory (depending upon storage chip capacity).

Each SBI device (i.e., CPU, MASSBUS adapter, UNIBUS adapter,
memory controller) has a unique priority. When a device wants to
transmit on the SBI, it asserts a unique request line. At the end of the

next 200 nanosecond cycle, each SBI device wanting to use the SBI
examines the SBI request lines for higher priority devices. The highest
priority device uses the next cycle, while other devices must wait.
Whenever possible, an SBI device currently in control of the SBI will
free the SBI so that a new transaction may occur on the next cycle.
This communication protocol enables:

Distributed arbitration. Since each device connected to the SBI
determines whether or not it will receive the next cycle (rather
than a central arbitrator making the decision), signals need travel
only one times the length of the SBI, with the advantage of increased speed. Additionally, devices perform a parity check on
the control information, assuring that the arbitration is proceeding
correctly.

Single 32-bit and two back-to-back 32-bit transfers. The SBI data
path is 32 bits wide. The protocol allows single (32-bit) and double
(64-bit) data transfer as transactions. (The I/0 adapters always try

to transfer data in 64-bit quadwords).

Every transaction on the SBI (i.e., data transfer, address transfer, or
command transfer) is parity-checked and confirmed by the receiver.
13

Introduction

In addition, substantial protocol checking occurs on évery cycle, resulting in high data integrity.
The UNIBUS — General-purpose and customer-developed devices
are connected to the VAX-11/780 system via the VAX-11/780’s UNI-

BUS. Since the SBI deals in 30-bit addresses (one gigabyte), 18-bit
UNIBUS addresses must be translated to 30-bit SBI addresses. This
mapping function is performed by the UNIBUS adapter, a special
interface between the SBI and the UNIBUS, which translates UNIBUS

addresses, data, and interrupt requests to their SBI equivalents, and
vice versa.

The UNIBUS adapter does priority arbitration among devices on the
UNIBUS, a function handled by logic in the PDP-11 CPUs. The
address translation map permits contiguous disk transfers to and
from noncontiguous pages of memory (these are called scatter/gather
operations).

The UNIBUS adapater allows two kinds of data transfer: program interrupt and direct memory access (DMA). To make the most efficient

use of the SBI bandwidth, the UNIBUS adapter facilitates high-speed
DMA transfers by providing buffered DMA data paths for up to 15
high-speed devices. Each of these channels has a 64 bit buffer (plus
byte parity) for holding four 16 bit transfers to and from UNIBUS devices. The result is that only one SBI transfer (64 bits) is required for

every four UNIBUS transfers. The maximum aggregate transfer rate
through the Buffered Data Paths is 1.5 miillion bytes/second. In addition, on SBI-to-UNIBUS transfers, the UNIBUS adapter anticipates upcoming UNIBUS requests by prefetching the next 64-bit quadword
from memory as the last 16-bit word is transferred from the buffer to
the UNIBUS. The result is increased performance. By the time the
UNIBUS device requests the next word, the UNIBUS adapter has it
ready to transfer.

Any number of unbuffered DMA transfers are handled by one direct
DMA data path. Every 8 or 16-bit tranfer on the UNIBUS requires a 32bit tranfer on the SBI (although only 16 bits are used). The maximum
transfer

rate through

the

Direct

Data Path

is 500 thousand

bytes/second.

The UNIBUS adapter permits concurrent program interrupt, unbuffered and buffered data transfers. The aggregate throughput rate of
the Direct Data Path, plus the 15 Buffered Data Paths, is 1.5 million
bytes/second.

The MASSBUS(es) — High-performance mass storage devices, such
as the RP series moving head disks, are connected to the VAX-11/780

system using a MASSBUS adapter. The MASSBUS adapter is the
14

Introduction

interface between the MASSBUS and the SBI, and performs all control, arbitration, and buffering functions. Address mapping is similar to
that performed by the UNIBUS adapter.

There may be a totai of four MASSBUS adapters on each VAX-11/780
system. Each adapter can accommodate data transfers of 128K bytes
maximum to and from noncontiguous pages in physical memory
(scatter/gather). The VAX operating system supports transfers of 64K
bytes maximum to be consistent with other devices.
Each MASSBUS adapter uses a 32-byte silo data buffer, which permits transfers at rates up to two million bytes/second to and from
physical memory (8M bytes/second with all four). As in the UNIBUS
adapter, data is assembled in 64-bit quadwords (plus byte parity) to
make maximum efficient use of the SBl bandwidth.

On memory-to-MASSBUS transfers, as on memory-to-UNIBUS trans-

fers, the adapter anticipates upcoming MASSBUS data transfers by
prefetching the next 64 bits.

Optional Hardware Equipment

Prewired mounting space is available within the VAX-11/780 CPU

chassis for mounting the following optional equipment:
1)

A High-Performance Floating Point Accelerator. The FPA is an
independent processor that works in parallel with the base CPU to
execute the standard floating point instruction set with substantial
performance improvement. The FPA takes advantage of the
CPU’s instruction buffer to prefetch instructions, and the memory
cache to access main memory. Once the CPU has the required
data, the FPA overrides the normal execution flow of the standard

floating point microcode and forces use of its own code. Then,
while the FPA is executing, the CPU can be performing other
operations in parallel, for example, fetching the third operand of a
three-address instruction. The result is much greater throughput
and decreased execution time.

Up to two million bytes (total) of MOS Memory with ECC.

Main Memory Battery Backup for ten minutes for each one million
bytes of memory.

12K bytes (plus parity) of user writable control store (WCS). The
user can modify or add to the native mode instruction set by
programming the WCS.

CHAPTER 2

CONSOLE SUBSYSTEM
INTRODUCTION

The Console Subsystem serves as the interface between the operator

and the VAX-11/780 system. The console subsystem provides the
user with improved system maintenance features and greater operating system flexibility. The user interface to the subsystem is via the
console command language, which is quite similar to the system command language. The traditional lights and toggle switch functions have

been replaced by simple English language commands entered into
the system terminal. The system terminal (TTAO) is the logical first
terminal of the system. The floppy disk , an integral part of the subsystem, stores microdiagnostics and system software. This facilitates fast
diagnosis (initiated both locally and remotely), simplified system bootstrapping

and

initialization,

and

improved

software

update

distribution. Figure 2-1 functionally illustrates the console subsystem.

BUS -=

= CLOCK CONTROL

—————®
V BUS

CONSOLE/CPU

INTERFACE

RN
ROM

Q-BUS
4

RXV-11

FLOPPY

4K MEM

LSI-11

CONTROL

DLV-11

DcL>\£>_T”
(OPT)

]

FoTo T
I

RXO1

| (OPTIONAL]J
b

RXO1

TERMINAL

— —— 4

Figure 2-1

EIA CONNECTION

FOR REMOTE
TERMINAL

Console Subsystem
17

Console Subsystem

The console subsystem is comprised of six major components:
e an LSI-11 microprocessor (KD11-F) including a 4K by 16-bit semi-

conductor random access memory (RAM).
e a floppy disk drive (RX01) and controller (RXV11); a second optional

floppy disk drive is also available.
e a system terminal and two serial line interface units (DLV11-E), one

serial line unit provided for optional remote diagnosis port.
e console interface board (CIB) including 4K by 16-bit read only mem-

ory (ROM) for the LSI-11 microprocessor.
e the control panel on the VAX-11/780 cabinet.

e bus structure. The internal data (ID) bus is a high speed data path
connecting major functional areas of the VAX-11/780 CPU.

CONSOLE INTERFACE BOARD
The Console Interface Board links the console subsystem to the VAX11/780 central processor. The CIB contains interfaces to the console
subsystem bus structures; registers accessible to each bus; and all the
hardware necessary to implement the console functions. In addition,

the CIB contains a 4K by 16-bit ROM which provides the core of the
console LSI-11 software.
All data transfer operations between the VAX-11/780 processor and
the console LSI-11 are routed via the TO Internal Data and FM Internal
Data privileged registers on the CIB. The interaction of the console
subsystem and the VAX-11/780 processor, however, is directly related
to the states of the two processors. The VAX-11/780 processor may be
either running or haited. When running, the VAX processor is executing normal VAX-11 code. The processor can then be halted in one of
two ways:
e internal system error

e halt command via console (console must be in console command

mode to activate halt command)
If the processor is halted via an error detection, the console subsystem

automatically enters the console command mode (e.g., CPU doubleerror halt).
The LSI may perform in either the program I/0 mode or the console
command mode. When the LSI-11 is in the program [/O mode, it
passes console terminal input character by character to the VAX11/780 software. Data sent from the VAX-11/780 software to the con-

sole terminal is passed by the LSI-11 software directly to the terminal.
When the LSI-11 is in the console command mode, it interprets all

console terminal output in order to perform diagnostic and
maintenance functions and to implement the console command lan-

guage (CCL). Therefore, four possible system states could exist. They
are:

Console Subsystem

e VAX-11/780 running—LSI-11 program |/0 mode

e VAX-11/780 running—LSI-11 console command mode
e VAX-11/780 halted—LSI-11 program |1/0 mode
e VAX-11/780 halted—LSI-11 console command mode

Figure 2-2 illustrates the VAX-11/780 and LSI-11 interaction and oper-

ating mode combinations.

cI8

VAX11/780

cPU

LSI

PASSING ASCII CHARACTERS

VAX-11

SOFTWARE

;’ngRAM
MODE

“SET

TERMINAL

"CONTINUE"

PROGRAM"

“TP"

‘[HALT STATE
{CONSOLE MODE

ESSE?LE WA

Figure 2-2

CONSOLE

CONSOLE COMMAND LANGUAGE
(e.g. EXAMINE)

170

MODE

VAX-11/780 and LSI-11 Interaction and System
Operating States

VAX-11/780 Running — LSI-11 in Program I/O

In this mode of operation, the console terminal acts like any other user
terminal and may be used in conjunction with normal user application
programming. The Console Interface Board (CIB) passes character
data between both processors. In this mode, the LSI-11 console software does not interpret commands typed at the console terminal.
VAX-11/780 Running — LSI-11 in Console Command Mode
In this mode, the operator is able to halt the VAX-11/780 processor via
the console terminal by typing the HALT command, and resume execution of the processor by entering the CONTINUE command. How-

ever, by entering the CONTINUE command, the console is automati-

cally updated to program I/O mode. When the VAX-11/780 is
executing instructions and the LSI-11 is in the program I/0 mode, to
halt the VAX processor. the operator must change console modes
19

Console Subsystem

from program I/0 mode to console command mode and then input
the HALT command.

The system operator can enter the console command mode from the
program I/0O mode by typing control-P (}P). Similarly, the operator can

change from console command mode to program 1/0 mode by typing
“Set Terminal Program”. While the VAX processor is executing code,
only the following subset of commands are permitted:
e SHOW

e SET
e WAIT DONE

e HELP

e EXAMINE /VBUS
e CLEAR

Note that the functions which may be performed by the console are
limited to those requiring no direct response by the VAX-11/780 processor (except HALT). The console software does not pass commands
to the executing VAX processor software. Conversely, the console will
not accept output from the executing software of the VAX-11/780
processor. Therefore, the VAX-11/780 software cannot communicate

with the console floppy disk or console terminal.

VAX-11/780 Halted — LSI-11 in Program 1/0 Mode
This mode of operation contains no system functionality and should
not be utilized.

VAX-11/780 Halted — LSI-11 in Console Command Mode
In this mode, the full functionality of the console command set is available to the system operator. Through the use of the console command
language, the system operator has the capability to:
e Initiate and terminate software being executed by the VAX-11/780
processor.

¢ Display and modify memory elements including main memory, 1/0,
general register and process register address space.

e Control the processor clock to provide single step clock modes for
use in basic hardware or program development.

e Initiate macro and micro diagnostics.

For further information regarding the console language, a complete
listing of the console commands is includedin this chapter.

CONSOLE BUS STRUCTURE
Communication between the elements of the console is achieved by

three separate bus configurations. The ID (Internal Data) Bus links
20

Console Subsystem

together the major functional areas of the central processor. The V
bus interfaces the LSI-11 microprocessor and its peripheral hardware
to the VAX-11 CPU via the CIB (Console Interface Board). The V bus is
utilized by the console, while the LSI-11 is in the console I/0 mode, to
access the Central Processor’'s major buses and key control points.
INTERNAL DATA BUS

The Internal Data Bus is a high speed data path between the major
functional areas of the CPU. The ID bus may be controlled from the
console interface logic in a maintenance mode operation. This allows
access to writable control store and internal registers from the console.

When the Console Interface Board generates the ID MAINT signal, it
inititates a maintenance operation, allowing the console to assert |ID
bus address and control signals (and data, if appropriate). The ID Bus
Registers are located in Appendix D.
QBUS

The Q bus (LSI-11 bus) connects the LSI-11 processor (and its ROM
and RAM memories), the console terminal interfaces, and the floppy
disk interface to the Console Interface Board, and thus to the VAX-11
CPU. The 16 address signals and 16 data signals share the same bus
lines. Fourteen other LSI-11 signal lines are used in the VAX-11/780
configuration for control signals (note that the DMA control lines are
not used).

Note that the serial line interface and the floppy disk interface cannot
communicate directly with the Console Interface Board, nor can the
CIB communicate directly with them. All transfers initiated from the
interfaces begin with interrupts to the LSI-11 processor.

V BUS

The V bus consists of eight serial data lines, a load signal line, a clock
signal line, and a self test line. Each of the participating VAX-11 CPU
modules contains a V bus shift register. The data input lines to the shift
register monitor specific test points on the CPU module, as shown in

Figure 2-3. The LOAD signal causes the shift register to parallel load
from the test points when the VAX-11 CPU is in a stable condition. The
clock signal can then be used to read the latched data serially from
each of the shift registers into a register on the CIB. The LSI-11 must
read the register before clocking in the next serial bit from each of the
shift registers.

Console Subsystem

MODULE TEST POINTS
—

SELF TEST

‘

SHIFT REGISTER

PARALLEL
LOAD

‘
D

SERAL
CLOCK

Data

ONE OF EIGHT
SERIAL DATA LINES
US REGISTER

SELF

TEST

Figure 2-3

LOAD | CLOCK

V Bus Block Diagram

CONSOLE/VAX-11 INTERACTION
All data transfer operations between the VAX-11 CPU and

LSI-11 are routed via the TO and FM ID Registers on the

the console

CIB. The LSI-

11 Console may look at various points in the VAX-11 CPU
via the V
Bus or it may look at data on the ID Bus. The TO ID Register
is a data
buffer, serving two functions. First, it may be loaded by the
LSI-11 with
data from the console terminal, one ASCII character to be
read by the
VAX-11 microcode. The low order eight bits of the
TO ID register

contain the ASCII character (RXDB <7:0>). Bits <11:8>
specify the
console unit at which the data originated. Logical unit
00 is reserved

for the operator terminal. Second, the LSI-11 may write

to any ID bus
address through the TO ID register by executing an ID
maintenance

cycle.

The terms TO and FR (FROM) are used with respect
to the VAX-11

CPU.

The FM ID Register is also a data buffer, serving a dual function.

First,
it may be loaded by the VAX-11 microcode with data
to be passed to
the console subsystem. The low order eight bits of the FM
ID register

contain the ASCII character to be passed to the LSI-11.
Bits <11:8>
specify one of the logic units in the console subsystem.
Second, the
LSI-11 may read any ID bus register through the FM
ID register by

executing an ID maintenance cycle when the VAX-11

CPU is halted.

The TO and FM internal data registers are illustrated in Figure 2-4.

Console Subsystem

]
0

X SEL< 3.0>

Figure 2-4

RX DATA

RX SEL <XO>

120

21U

TX DATA

TO and FM ID Registers

READ ONLY MEMORY (ROM)

The Console Interface Board contains 4K words of ROM. This ROM
contains the core of the LSI-11 console operating system, including

the power up routines, the terminal and the floppy drivers. The LSI-11

begins executing instructions in the ROM when power is applied to the

THE CONSOLE COMMAND LANGUAGE
The console command language commands are listed and described

below in alphabetical order.

SYNTAX: ALL COMMANDS ARE TERMINATED BY CARRIAGE RETURN.

‘EXAMINE’ AND ‘DEPOSIT’ <QUALIFIERS
> SWITCHES FOR

ADDRESS SPACE:

‘/P’

PHYSICAL MEMORY (THE DE-

YV’

VIRTUAL MEMORY

Iik

INTERNAL (PROCESSOR)

Jicy

GENERAL REGISTERS 9 THRUF

‘VR

VBUSREGISTERS

‘JIF

IDBUS REGISTERS

FAULT)

REGISTERS
(RO THRU PC)

‘EXAMINE’ AND ‘DEPOSIT’ <QUALIFIERS> SWITCHES FOR
DATA-LENGTH:
‘B

BYTE(8BITS)

WORD (2BYTES)

/L'

LONGWORD (2 WORDS)

QUADWORD (4 WORDS)

<ADDR> IS A <NUMBER>, OR ONE OF THE FOLLOWING

SYMBOLIC ADDRESSES

Console Subsystem

‘RO,R1,R2,......,R11,AP,FP,SP,PC’ (GENERAL

REGISTERS)

‘PSLT

PROCESSOR STATUS WORD
LAST ADDRESS

‘+’

ADDRESS FOLLOWING ‘LAST’

ADDRESS
!

ADDRESS PRECEDING ‘LAST

ADDRESS
‘@’

USES LAST EXAMINE/DEPOSIT
DATA FOR ADDRESS

<NUMBER> = STRING OF DIGITS IN CURRENT DEFAULT
RADIX,

STRING OF DIGITS PREFIXED WITH A DEFAULT RADIX
OVERRIDE (%0 FOR OCTAL, %X FOR HEX).
‘BOOT

-BOOTS THE CPU FROM DEFAULT DEVICE

‘BOOT <DEVNAM>'

-TAKES THE FIRST THREE ALPHANUMERIC CHARACTERS OF <DEVNAM>,
AND EXECUTES THE INDIRECT FILE

‘<DEVNAM>BOO.CMD’

‘CLEAR SOMM'’

-CLEAR ‘STOP ON MICRO-MATCH’ ENABLE. NOTE: ID REGISTER 21 IS THE
MICRO-MATCH REGISTER

‘CLEAR STEP’

-ENABLE NORMAL (NO STEP) MODE

‘CONTINUFE’

-ISSUES A CONTINUE TO THE ISP

‘DEPOSIT

-DEPOSIT <DATA> TO <ADDR>

[/ <SWITCH(ES)>]
<ADDR> <DATA>’

‘DIAGNOSFE’

-BOOTS THE DIAGNOSTIC SUPERVISOR
FROM DEFAULT DEVICE

‘DIAGNOSE <DEV-

-TAKES THE FIRST THREE ALPHANU-

NAM>’

MERIC CHARACTERS OF <DEVNAM>,
AND EXECUTES THE INDIRECT FILE

‘<DEVNAM>SUP.CMD’
‘ENABLE DX1

-ENABLES CONSOLE SOFTWARE TO AC-

CESS FLOPPY DRIVE 1 ON THOSE SYSTEMS WITH DUAL FLOPPIES
‘EXAMINE

-DISPLAY CONTENTS OF <ADDR>

[/ <SWITCH(ES)>]

<ADDR>"’
24

Console Subsystem

‘EXAMINE IR’

-EXAMINES INSTRUCTION REG (IR), DISPLAYS OP-CODE, SPECIFIER, & EXECUTION POINT COUNTER

‘HALT’

-HALTS THE ISP

‘HELP’

-PRINTS THIS FILE

‘INITIALIZE’

-INITIALIZES THE CPU

‘LINK’

-CAUSES CONSOLE TO BEGIN
COMMAND LINKING. CONSOLE PRINTS
REVERSED PROMPT TO INDICATE LINKING. ALL COMMANDS TYPED BY USER
WHILE LINKING ARE STORED IN AN INDIRECT COMMAND FILE FOR LATER EXECUTION. TYPING CONTROL C TERMINATES LINKING. (ALSO REFERENCE THE
PERFORM COMMAND)

<ADDR>]

-LOAD FILE TO MAIN MEMORY, STARTING AT ADDRESS 0, OR DDR> IF SPECI-

<FILENAME>’

FIED

‘LOAD/WCS

-LOAD FILE SPECIFIED TO WCS

‘LOAD[/START:

<FILENAME>’

‘NEXT <NUMBER>’

-<NUMBER> STEP CYCLES ARE
DONE,TYPE OF STEP DEPENDS ON LAST
‘SET STEP’ COMMAND

‘PERFORM’

-EXECUTE A FILE OF LINKED COMMANDS
PREVIOUSLY GENERATED VIA A ‘LINK’
COMMAND.

‘QCLEAR

-DOES A QUAD CLEAR TO <ADDRESS>,

<ADDRESS>’

WHICH IS FORCED TO A QUAD WORD
BOUNDARY (CLEARS ECC ERRORS)

‘REBOOT’

-CAUSES A CONSOLE SOFTWARE RELOAD

‘REPEAT <ANYCONSOLECOMMAND>’

-CAUSES THE CONSOLE TO REPEATEDLY EXECUTE THE <CONSOLE-COMMAND>, UNTIL STOPPED BY A (CONTROL C)1C

‘SET CLOCK SLOW’

-SET CPU CLOCK FREQ TO SLOW

‘SET CLOCK FAST

-SET CPU CLOCK FREQ TO FAST

‘SET CLOCK NORMAL’

-SET CPU CLOCK FREQ TO NORMAL
25

Console Subsystem

‘SET DEFAULT

-SET CONSOLE DEFAULTS. NOTE:

<OPTIONS> ARE: OCTAL, HEX, PHYSI-

[,...,<OPTION>]’

CAL, VIRTUAL, INTERNAL GENERAL,
VBUS, IDBUS, BYTE, WORD, LONG, QUAD

‘SET RELOCATION:

-PUT <NUMBER> INTO CONSOLE RELO-

<NUMBER>’

CATION REGISTER. RELOCATION REGIS-

TER IS ADDED TO EFFECTIVE ADDRESS
OF PHYSICAL AND VIRTUAL EXAMINES

AND DEPOSITS
‘SET SOMM’

‘SET STEP BUS’

-SET ‘STOP ON MICRO-MATCH’ ENABLE
-ENABLE SINGLE BUS CYCLE CLOCK
MODE

‘SET STEP

-ENABLES SINGLE INSTRUCTION MODE

INSTRUCTION’
‘SET STEP STATFE’

-ENABLE SINGLE TIME STATE CLOCK
MODE

‘SET TERMINAL FILL:

-SET FILL COUNT FOR # OF BLANKS

<NUMBER>’

WRITTEN TO THE TERMINAL AFTER

<CRLF>
‘SET TERMINAL

-PUT CONSOLE TERMINAL INTO ‘PRO-

PROGRAM’

GRAM /0 MODFE’

‘SHOW’

-SHOWS CONSOLE AND CPU STATE

‘SHOW VERSION’

-SHOWS VERSIONS OF MICROCODE AND
CONSOLE

‘START<ADDRESS>’

-INITIALIZES THE CPU, DEPOSITS <AD-

DRESS> TO THE PC, ISSUES A CONTINUETO THEISP
‘TEST’
‘TEST/COM’

-RUNS MICRO-DIAGNOSTICS
-LOADS MICRO-DIAGNOSTICS, AWAITS
COMMANDS

‘UNJAM’
‘WCS’

-UNJAMS THE SBI

-CALLS MICRODEBUGGER. (FOR DEBUGGER HELP, TYPE ‘@WCSMON.HLP’)

‘WAIT DONFE’

-WHEN EXECUTED FROM AN INDIRECT
COMMAND FILE, THIS COMMAND WILL

CAUSE COMMAND FILE EXECUTIONTO

STOP UNTIL: A) A ‘DONE’ SIGNAL IS RE26

Console Subsystem

CEIVED FROM THE PROGRAM RUNNING
IN THE VAX-11/780 (COMMAND FILE EXECUTION WILL CONTINUE), OR B) THE
VAX-11/780 HALTS, OR OPERATOR
TYPES A 1C (COMMAND FILE EXECUTION
WILL TERMINATE)

“4P’(CONTROL-P)

-PUT CONSOLE TERMINAL INTO ‘CON-

SOLE 1/0’' MODE

(UNLESS MODE SWITCH IN ‘DISABLE)

‘@ <FILENAME>’

-PROCESS AN INDIRECT COMMAND FILE

CONSOLE ERROR MESSAGES

This section lists all console error messages and defines their format
and meaning. All console error messages are prefixed by a question
mark, to distinguish them from informational messages. Where user
interaction is required, the necessary steps appear in parentheses
following the respective error description.
Syntactic Errors

2 <TEXT-STRING>'IS

The <TEXT-STRING> is not a complete

INCOMPLETE

console command.

2 <TEXT-STRING>’IS

The <TEXT-STRING> is not recognized as

INCORRECT

? FILE NAME ERR

a valid command.

A <FILENAME> given with acommand

cannot be translated to RAD50. (<FILENAME> is invalid)

?2IND-COM ERR

The console detected an error in the format

of an indirect command file. Possible errors
are:

1) More than 80 characters in an indirect
command line or

2) An indirect command line did not end
with a CARRIAGE-RETURN and LINE
FEED.

Command Generated Errors

?FILE NOT FOUND

A <FILENAME> given with a ‘LOAD’ or ‘@’

command does not match any file on the

currently loaded floppy disk. This error can

also be generated by a ‘HELP’, ‘BOOT or an
attempted WCS load if HELP FILE, BOOT
FILE or WCS FILE is missing from Floppy.
27

Console Subsystem

?NO CPU RESPONSE

The console timed out waiting for a response from the CPU. (Retry, indicates pos-

sible CPU-related hardware fault)

?CPUNOT IN

CONSOLE WAIT
LOOP,COMMAND
ABORTED

?CPU CLOCK
STOPPED,COMMAND
ABORTED

A console command requiring assistance
from the CPU was issued while the CPU was
notin the console service loop. (HALT CPU,

re-issue command)
A console command that requires the CPU

clock to be running was issued with the
clock stopped. (Clear step mode; re-issue
command)

CANT DISABLE BOTH
FLOPPY’s, FUNCTION

An attempt was made to disable both the
remote and local floppy.

ABORTED

Micro-Routine Errors
The console uses various micro-code routines in the CPU’s control

store to perform console functions. The following errors are generated

by micro-routine failures:

?MIC-ERR ON
FUNCTION

A micro-error occurred in the CPU while

servicing a console request. SBI error registers are dumped after this message is print-

ed. (Action dependent upon error)

?INT-REG ERR

A micro-error occurred while attempting to

reference a CPU internal (processor) register. An illegal address will cause this error.

?MICRO-ERROR,

CODE=X

An unrecognized micro-error occurred. The
code returned by the CPU is not in the
range of recognized error codes. ‘X’ is the
code returned by the CPU.

?MEM-MAN FAULT

CODE=XX

A virtual examine or deposit caused an error in the memory management micro-routine. XX’ is a one byte error code returned

by the routine, with the following bit assignments:

Bit 0 = Length violation (bits numbered
from right)

Bit 1 = Fault was on a PTE reference

Bit 2 = Write or modify intent
28

Console Subsystem

Bit 3 = Access violation

Bits 4 through 7 should be ignored

CPU Fault Generated Error Messages

?INT-STACK INVALID

?CPU DOUBLE-ERR
HALT

The CPU halted because the interrupt stack

was marked invalid.

A machine check occurred before a previous machine check had been handled,

causing the CPU to execute a ‘Double Error’
Halt. (Examine ID Registers 30-3F (hex);
contents will aid in locating cause of machine check).

?ILL I/E VECTOR

The CPU detected an iliegal Inter-

?NO USRWCS

CPU detected an Interrupt/Exception vec-

?CHM ERR

rupt/Exception vector.

tor to user WCS and no user WCS exists.

A change mode instruction was attempted

from the interrupt stack.

INT PENDING

This is not actually an error, but indicates

?MICRO-MACHINE

Indicates that the VAX-11/780 micro-ma-

TIME OUT

that an error was pending at the time thata
console-requested halt was performed.
(Continue CPU to clear interrupt).

chine has failed to strobe interrupts within
the max time period allowed.

Messages Generated by Floppy Errors

?FLOPPY
ERROR,CODE=X

The console Floppy driver detected an error. Codes are as follows: (Codes always
printed in HEX Radix).

CODE 1-Floppy hardware error. (CRC, Parity, etc.)

CODE 2-File not found.

CODE 3-Floppy driver queue overfull.

CODE 4-Console software requested an
illegal sector number.
Ty

2FLOPPY NOT READY

The console floppy drive failed to become
ready when booting. (Retry)
29

Console Subsystem

?NO BOOT ON
FLOPPY

Console attempted to boot from a floppy
that does not contain a valid boot block.

(Change floppy disk)

?FLOPPY ERROR ON
BOOT

A floppy error was detected while attempting a console boot. (Retry)

Messages Related to Version Compatibility

?WARNING-WCS &

FPLA VER MISMATCH

The microcode in WCS is not compatible

with FPLA. This message is printed on each

ISP START or CONTINUE, but no other action taken by console.
?FATAL-WCS & PCS
VER MISMATCH

The rriicrocode in PCS is not compatible

with thatin WCS. ISP START and CONTIN-

UE are disabled by console.

?REMOTE ACCESS
NOT SUPPORTED

Printed when console mode switch enters

‘REMOTE’ position, and the remote support

software routines are not included in the

console.

Console Generated Errors
?TRAP-4, RESTARTING CONSOLE

?UNEXPECTED TRAP
MOUNT CONSOLE

FLOPPY, THEN TYPE

The console took a time-out trap. Console

will restart.

Console trapped to an unused vector. Con-

sole reboots when
{C typed.

1C
?Q-BLKD

Console’s terminal output queue is blocked.
Console will reboot.

CHAPTER 3

CENTRAL PROCESSOR
INTRODUCTION
hardware reThe VAX-11/780 Central Processing Unit (CPU) is the ions
requestoperat
etic
arithm
and
logic
the
ming
sponsible for perfor
rmance,
perfo
higha
ed of the computer system. The processor is
of variable-

microprogrammed computer that executes a large set
length instructions in native mode, and non-privileged PDP-11 instructions in compatibility mode.

ity, thereby
The CPU maintains 32-bit addressing and data capabil
ss space
addre
virtual
of
allowing it direct access to four billion bytes
virtual
32-bit
a
of
terms
in
on
locati
a
nces
(2%2). That is, the CPU refere
actual
the
not
is
it
se
becau
virtual
d
terme
is
ss
address. This addre
ement
manag
y
address in physical memory. The processor's memor address under
hardware translates a virtual address to a physical
operating system control.

used for temThe processor provides 16 32-bit registers that can bebase
registers.

porary storage, as accumulators, index registers, andam Counter, and
Four registers have special significance: the Progr
CALL facility. The
three registers that are used to provide an extensive
use the general
that
modes
ssing
addre
of
y
variet
a
processor offers
including an
registers to identify instruction operand locations,
g capability.
ndexin
post-i
true
des
indexed addressing mode that provi

It includes integral
The native instruction set is highly bit efficient.
ctions, as well as
instru
point
ng
floati
and
,
string
decimal, character
and data are
integer, logical, and bit field instructions. Instructions
ary or, in the
bound
byte
ary
variable length and can start at any arbitr
ng point
Floati
y.
memor
in
bit
ary
arbitr
case of bit fields, at any
ng point
floati
al
option
an
by
ced
enhan
be
can
tion
instruction execu
accelerator.

The processor’s instruction set is defined by the micro. code loaded
into the programmable read-only memory (control store)
33

Central Processor

The VAX-11/780 processor inclu

des the following functional hardw

components:

are

8K byte two-way set associativ
e memory cache
8 byte prefetch instruction buffer

128 entry address translation buffer
12K byte writable diagnostic contro

l store (WDCS)

time-of-year clock
programmable real time clock

integral memory management
optional floating point accelerator

(FPA)

optional 12K byte customer writab

le contro| store (WCS)

This chapter is divided into three

sections. The first section discu

sses

processor hardware, functi
onality and example proce
ssor operation.

The second section discusses the

processing system from the

programming characteristics of the

user's point of view. And the

last section

looks at the processing syste
m, but from an operating syst
em

viewpoint.

HARDWARE ELEMENTS
The VAX-11/780 CPU is a fast,
high-performance, 32-bit micro
pro-

grammed

computer.

The CPU

from the fact that it can handle
neously.

derives its speed and

performance

several independent functions simul

ta-

The CPU can process both 32-bit
data and addresses while maintaining the ability to manipulate:
® bits (up to 32)
® bytes
® words

® longwords
® quadwords

e 32-bit floating point (single
preci

sion)

® 64-bit floating point (double
preci

sion)

® packed decimal (up to 31 digits
)

® character strings (up to 64K

bytes)

The following sections describe

the VAX-11/780 processor hardw

are:

Control Store

The control store is a read-only memo

words plus 3 parity bits per micro

ry containing 4K 96 bit micro-

word. The control store conta

ins the

program that describes the operat
ion and sequencing of the centra
l

Central Processor

processing unit. It also contains the native, compatibility, and floating
point instruction sets. The control store contains a 96 bit buffer, enabling it to execute one microword while simuitaneously fetching the
next.

Data Paths

The data path subsystem consists of four independent and parallel
sections used to process addresses and data specified by the
instruction set. The arithmetic section is used to perform both arithmetic and logical operations on data and addresses. The exponent
and sign section is used for fast exponent processing of floating point
instructions. The data shift and rotate section packs and unpacks
floating point and decimal string data. And finally, the address section
calculates virtual addresses for the transiation buffer.

8K Byte Two-Way Set Associative Memory Cache

The memory cache is the primary cache system for all data coming
from memory, including addresses, address translations, and instructions. The memory cache is an 8K byte, two-way set associative, writethrough cache.

Write-through provides reliability because the contents of main memory are updated immediately after the processor performs a write.
Most write-through cache systems tie up the processor while main
memory is updated. However, this processor buffers its commands to
avoid waiting while main memory is updated from the cache. There-

fore, while providing the reliability of a write-through cache, this
system also provides much the same performance as a write-back
cache.

The memory cache also reduces the average time the processor waits
to receive main memory data by reading eight bytes at a time from
main memory, and transferring four bytes to the CPU data paths, or

instruction buffer. Since the remaining four bytes are already avail-

able, the memory cache also provides pre-fetching. The cache memo-

ry system carries byte parity for both data and addresses for increased integrity. Cache locations are allocated when data is read
from memory. When both of the possible locations for a particular
datum are already filled, one of the previously cached data is randomly replaced.

Address Translation Buifer

The address translation buffer is a cache of likely-to-be-used physical

address translations. !t significantly reduces the amount of time spent
by the CPU on the repetitive task of dynamic address translation. The
cache contains 128 virtual-to-physical page address translations
35

Central Processor

which are divided into equal sections: 64 system space

page transiations and 64 process space page translations. Each of these
sections
is two-way associative. There is byte parity on each entry
for increased
integrity.

8 Byte Prefetch Instruction Buffer

The 8 byte instruction buffer improves CPU performance by prefetch-

ing data in the instruction stream. The control logic continously fetches data from memory to keep the 8 byte buffer full. It effectively elimi-

nates the time spent by the CPU waiting for two memory cycles where
bytes of the instruction stream cross 32-bit longword boundaries. In

addition, the instruction buffer processes operand specifiers in advance of execution and subsequently routes them to the CPU.

12K Byte Writable Diagnostic Control Store (WDCS)
The writable diagnostic control store consists of 1024 96-bit (12K byte)

control words plus three parity bits per control word. These locations
are used to contain basic instruction microcode, diagnostic
microcode, and reserved space to accommodate future additions or

improvements made by DIGITAL to the instruction set.

Processor Clocks
The VAX-11/780 processor contains a programmable
and a time-of-year clock. The interval or real-tim

real-time clock

e clock was designed

to permit the measurement of finely resolved variable
intervals which
are identified by interrupts (i.e., scheduling,
diagnostics, etc.). The
real-time clock is based upon a crystal oscillato
r with an accuracy of

0.01%, and a resolution of one usec. The time-ofyear clock is used by
software to perform various timekeeping functions
. Its major function
is to provide the correct time to the system after
power failure or other

system interruptions.

Optional Floating Point Accelerator

The floating point accelerator is an optional high-sp
eed processor

extension. When included in the processor, the floating
point accelerator executes the addition, subtraction, multiplic
ation, and division

instructions that operate on single- and double-p
recision floating
point operands, including the special EMOD and
POLY instructions in
both single- and double-precision formats. Additiona
lly, the floating
point accelerator enhances the performance of 32-bit
integer muitiply

instructions.

The processor does not have to include the floating point

accelerator

to execute floating point operand instructions. The
floating point accelerator can be added or removed without changing
any existing
software.

Central Processor

sor, a
When the floating point accelerator is included in the proces
takes as

floating point operand register-to-register add instructioner multiply

er-to-regist
little as 800 nanoseconds to execute. A regist
loop of the POLY
inner
The
usec.
one
as
little
as
takes
instruction
degree of polynomial.

instruction takes approximately one usec per
(WCS)
Optional 12K Byte User Writable Control Store 96-bi
t (12K byte) con-

sts of 1024
The user writable control store consicontr
ol word. These locations are
per
bits
y
parit
three
plus
s
trol word
augmenting the speed and
for
omer
optionally available to the cust
power of the basic machine with customized functions.
Figure 3-1 illustrates the central processing unit.
PROCESSOR OPERATION

aces of the
For those interested in the hardware operations and interf
of code is
piece
e
VAX-11/780 CPU elements, the execution of a sampl
into its
ded
expan
first
is
described below. A FORTRAN |V DO LOOP
ic imspecif
ne
machi
VAX
into
then
and
VAX-11 MACRO equivalent,
al
physic
to
virtual
tion,
descrip
this
of
es
purpos
the
plementation. For
translation values, although valid, have been assumed.

Example: FORTRAN IV DO LOOP
J=0

Do 1001 =1,10

J=J+N(l)

100

VAX MACRO EXPANSION
RO
CLRL
1000

MOVL

1002

1005

#1,R1

ADDL2

1$:

100B
1FFC

N<R1>,R0

AOBLEQ

#10,R1,1$

.BLKL

CENTRAL PROCESSOR IMPLEMENTATION
CcPU

Operation

Component

ALU,R

Cache

1000 — PC

Translate virtual 1000 to physical 1F600

Does Cache presently contain address 1F600? (NO)

therefore,

CONSOLE_SUBSYSTEM

CONSOLE

CENTRAL PROCESSOR

)

TERMINAL

Ls1-n

RANSLATION

BUFFER

/O SUBSYSTEM

DATA CACHE

REMOTE

DIAGNOSIS

[¢)

ARITHMETIC /

weicwnr.

MOS
MEMORY

8¢

MEMORY
[CONTROLLER

SBI

INTERFACE

REGISTERS

DATA| BUS (MDJ

|
L

INTERNAL

MEMORY

MaSSBUS

5
r4
cPy

INSTRUCTION

INTERFACE

BUFFER

MASSBUS

ADAPTER

|
|

MASSBUS

DEVICES

S
N
S o

DIAGNOSTICS

BUS

UNIBUS

ADAPTER

UNIBUS

*PCS - PROGRAMMABLE READ ONLY
MEMORY CONTROL STORE

FLOATING

WCS
- WRITABLE CONTROL STORE

ACCELERATOR

WDCS5- WRITABLE DIAGNOSTIC CONTROL STORE

—

** INFORMATION

Figure 3-1

INSTRUCTION

BUFFER

ONLY

FROM

The Central Processing Unit

SBI

INTERFACE

UNIBUS
DEVICES

108582014 [enuan

T
1

Central Processor

CPU

Operation

Component
SBI
Cache

Fetch 1F600-1F607 from memory

Store address range 1F600-1F607 and correspond-

ing contents in Data Cache

(IB)

Obtain instructions from physical addresses 1F600-

ALU,R

Ask IB for instruction -- (CLRL)

ALU,R

Clear RO

1F603

(IB asks

Cache for
more)

IB retrieves physical addresses 1F604-1F607 from
Cache

ALU, R

Ask IB for next instruction -- (MOVL)

ALU,R

Ask IB for destination specifier -- (R1)

(IB asks

Cache for
more)

Cache asks SBI for 1F608

SBl

Asks memory for physical addresses 1F608-1F60F

ALU,R

Store 1in R1

ALU,R

Ask IB for next instruction -- (ADDL2)

ALU,R

Calculate base address of N (virtual 1FFC)

ALU,R

Adds 4*R1 to address of N to yield virtual address
2000

Cache

Look up address of N[1] : physical address A0O
Searches for physical address A0O, but finds it not
there, therefore,

SBI

The SBI enters a wait mode because it is currently

completing the fetch operation of physical addresses

SB!

1F608-1F60F

Finishesthe prefeich
operation of physica! ad-

dresses 1F608-1F60F

Grabs 1F608-1F60B
39

Central Processor

CPU

Operation

Component
Cache

Gets 1F608-1F60F

SBlI

Starts fetch of physical addresses A00-A07

Cache

Gets A00-A07

ALU,R

A00-A03

ALU,R

Asks IB for destination specifier (R6)

(IB asks
for 1F60C)

Cache sends 1F60C-1F60F to IB

ALU,R

Add (A00-A03) (i.e., N[1]) to RO

ALU,R

Ask IB for instruction (AOBLEQ)

(IB asks for
more data)

Cache asks SBI to get 1F610 from memory

ALU, R

Asks IB for next specifier (R1)

ALU,R

Add 1to R1, compare to 10, if less than or equali to

10 then branch
ALU,R

Flush (clear) IB, load virtual 1005 into PC

Fetch 1005 from cache (resumption of loop)

ALU,R

Ask IB for next instruction (ADDL2)

SBI

Memory data (1F610) arrives

Cache

Takes data, but IB doesn't grab it

on the 11th increment,

ALU,R

Add 1to R1, compare to 10, now however R1 = 11

Central Processor

CPU

Component

Operation

and do not branch, but fall through to the next instruction

ALU,R

Ask IB for next instruction

USER PROGRAMMING CONCEPTS

t
A program is a stream of instructions and data that a user can reques
able
execut
An
e.
execut
and
link,
te,
transia
to
the operating system
program is called an image. When a user runs an image, the contextin
which the image is executed is called a process. A process is thet
complete unit of execution in this computer system. Process contex
includes the state of the image it is currently executing and itincludes
the limitations on what an image is allowed to do, which primarily
depend on the privileges of the user who runs the image.
Process Virtual Address Space

byte.
Most data are located in memory using the address of an 8-bit locabyte
a
y
identif
to
s
addres
virtual
32-bit
a
uses
ammer
The progr
tion. A virtual address is not a unique address of a location in memory,
as are physical memory addresses. Two programs using the same
virtual address might refer to two different physical memory locations,
or refer to the same physical memory location using different virtual
addresses.

s
The set of all possible 32-bit virtual addresses is called virtual addres
an
as
viewed
be
can
)
storage
(mass
space
s
space. Virtual addres
array of byte “locations” (2% or over four billion bytes in length). Virtual
ses
address space is divided into two halves. The set of virtual addres
one
is
es,
execut
it
image
an
ng
designated for use by a process, includi
ing half
half of the total virtual address space. Addresses in the remainined
and
mainta
ns
locatio
to
refer
to
used
are
space
s
addres
of virtual
protected by the operating system.
Instruction Sets

in eiThe VAX-11/780 processor is capable of executing instructions
proces
the
mode
native
in
bility.
compati
or
native
modes:
ther of two
a
izes
recogn
tions,
sor executes a large set of variable-length instruc
In
s.
register
e
purpos
general
32-bit
variety of data types, and uses 16
1
compatibility mode the processor executes a set of PDP-1
purl
genera
16-bit
8
uses
and
data,
integer
izes
recogn
instructions,
pose registers. Both instruction sets are closely related and their programming characteristics are similar. Thus, a user process can

exe-

r, the
cute both native mode and compatibility mode images. Howeve
that of
than
ive
extens
more
erably
consid
is
set
tion
instruc
mode
native
41

Central Processor

compatibility mode execution.
The native mode instruction set
consists of 244 basic instructions, many
of which correspond directly to
high-level language statements
. Additionally, the native mode

instruction

set includes floating point operations,
character string

manipulations,

packed decimal arithmetic, and
many instructions
which improve the performance
and memory utilization of systems
and applications software.

A native instruction consists of an operat

ion code (opcode) and zero

Oor more operands, which are descri
bed by data type and addressing

mode.

Data Types
The data type of an instruction opera
nd identifies how many

storage are to be treated as a unit, and

bits of

what the interpretation of that

unit is. The processor’s native instruc
tion set recognizes four primary
data types: integer, floating point,
packed decimal, and character

string. In addition, the processor can
also manipulate a fifth data type,
the variable bit field, in which the progr
ammer defines the size of the
field and its relative position. Table 3-1
illustrates the VAX-11/780 data
types.

The address of any data item is the address
of the first byte in which
the item resides. All integer, floating point,
packed decimal, and character data can be stored starting on an arbitrar
y byte boundary. A bit
field, however, does not necessarily start on
a byte boundary. A field is
simply a set of contiguous bits (0-32) whose
starting bit location is

identified relative to a given byte address. The native

can interpret a bit field as a signed or unsigne

instruction set

d integer.

Registers and Addressing Modes
A register is a location within the proces
sor that can be used for

temporary data storage and addressing.
The assembly language programmer has 16 32-bit general register
s available for use with the

native instruction set. Some of these register
s have special significance. One register is designated as
the Program Counter, and it
contains the address of the next instruc
tion to be executed. Three
general registers are designated for use
with routine linkages: the

Stack Pointer, the Argument Pointer, and the Frame
An instruction operand can be located in

grammer chooses to specify an operan

Pointer.

main memory, in a general
The way in which the pro-

d location is called the operand

addressing mode. The processor offers a variety

of addressing modes

and addressing mode optimizations. There
is one addressing mode

that locates an operand in a register. There are

six addressing modes

Unsigned

Byte

8 bits

-128to +127

0to 255

Word

16 bits

-32768 to +32767

010 65535

Longword

32 bits

=23 to +2%'-1

0 to 23%2-1

Quadword

64 bits

-263to0 +2°%3-1

0 to 2°%*-1

+2.9 X 10-%"t0 1.7 X 10%®

Floating Point
ey

Signed

Floating

32 bits

Double Floating

64 bits

approximately seven decimal
digits precision

approximately sixteen decimal

digits precision

numeric, two digits per byte

Packed Decimal

0 to 16 bytes

(31 digits)

Character String

0 to 65535 bytes

one character per byte

Variable-length

0 to 32 bits

dependent on interpretation

String

Bit Field

1088800.d [BJjus)

Integer

RANGE (decimal)

I-€ 3iqel

SIZE

sadA] ejeqg

DATATYPE

Central Processor

that locate an operand in memory using a register to:
e point to the operand

e point to a table of operands
e pointto a table of operand addresses

There also are six addressing modes that are indexed modifications of
the addressing modes that locate an operand in memory. Finally,
there are two addressing modes that identify the location of the operand in the instruction stream: one for constant data, and one for
branch instruction addresses.

Stacks, Subroutines, and Procedures
A stack is an array of consecutively addressed data items that are
referenced on a last-in, first-out basis using a general register. Data
items are added to and removed from the low address end of the
stack. A stack grows toward lower addresses as items are added, and
shrinks toward higher addresses as items are removed.

A stack can be created anywhere in user program address space and
can utilize any register to point to the current item on the stack. The
operating system, however, automatically reserves portions of each
process address space for stack data structures. User software refer-

ences its stack data structure, called the user stack, through a general
register designated as the Stack Pointer.

A stack is a powerful data structure because it is able to pass argu-

ments to a routine
in a highly efficient manner. In particular, the stack
structure enables the programmer to write reentrant routines because

the processor can handle routine linkages automatically, using the
Stack Pointer. Routines can also be recursive because arguments can
be saved on the stack for each successive call of the same routine.

The processor provides two kinds of routine call instructions: those for
subroutines, and those for procedures. In general, a subroutine is a
routine entered using a Jump to Subroutine or Branch to Subroutine
instruction, while a procedure is a routine entered using a Call instruc-

tion.
The processor provides more elaborate routine linkages for procedures than for subroutines. The processor automatically saves and
restores the contents of registers the programmer wants preserved
across procedure calls. The processor provides two methods for

passing argument lists to called procedures: by passing the arguments on the stack, or by passing the address of the arguments else-

where in memory. The processor also constructs a list or record of
procedure call nesting by using a general register as a pointer to the

place on the stack where a procedure has its linkage data. This record
44

Central Processor

of each procedure’s stack data, known as its stack frame, enables
proper returns from procedures even when a procedure leaves data
on the stack. In addition, user and operating system software can use
the stack frame to trace back through nested calls to handle errors or
debug programs.

Condition Codes

A user program can test the outcome of an arithmetic or logical operation. The processor provides a set of condition codes and branch
instructions for this purpose. The condition codes indicate whether the
previous arithmetic or logical operation produced a negative or zero
result, or whether there was a carry or borrow, or an overflow. There
are a variety of branch on condition instructions: those for overflow
and carry or borrow, and those for signed and unsigned relational
tests.

Exceptions

There are some situations in which the programmer may not want to

test the outcome of an operation. The processor recognizes many
events for which testing is not necessary,and automatically changes
normal program flow when they occur. These events, called exceptions, are the direct result of executing a specific instruction.
Exceptions also include errors automatically detected by the processor, such as improperly formed instructions.

All exceptions trap to operating system software. There are essentially
no fatal exceptions. All exceptions either wait for the instruction that
caused them to complete before trapping or they restore the processor to the state it was in just prior to executing the instruction that
caused the exception. In either case, the instruction can be retried
after the cause of the exception is cleared. Depending on the exception, it may be desirable to correct the situation and continue. If not,
the operating system issues an appropriate message and aborts the
instruction stream in progress. To continue, the programmer can re-

quest the operating system software to start execution of a condition
handler automatically when an exception occurs.

USER PROGRAMMING ENVIRONMENT
A process context includes the definition of the virtual address space
in which it executes an image. An image executing within a process
context controls its execution through the use of one of the instruction
sets, the general purpose registers, and the Processor Status Word.
These hardware resources are discussed in detail in the following
IO

sections.

Central Processor

Process Virtual Address Space Structure
The processor and operating system provide a muitiprogramming
environment by dividing virtual address space into two halves: one
half for addressing context--dependent code and data, and one half for

addressing context-independent code and data.
The first half, termed per-process space, is capable of addressing
approximately two billion bytes. An image executing in the context of a
process and the operating system on behalf of the process use ad-

dresses in process space to refer to code and data particular to that
process context. A process cannot represent virtual addresses in any

process space but its own. Thus, code and data belonging to a process are automatically protected from other processes in the system.

The second half of virtual address space is called system space. The
operating system assigns the meanings to addresses in system space.

The significance of any address in system space is the same for every
process, independent of process context.

Per-process space is further subdivided into two regions. Addresses
in the first region, called the program region, are used to identify the

location of image code and data. Addresses in the second region,
called the control region, are used to refer to stacks and other temporary program image and permanent process controlinformation

maintained by the operating system on behalf of the process. Program
region addresses are allocated from address 0 and up, and control
region addresses are allocated from address 23'—1 and down.

System space is also subdivided into two regions. The operating system assigns the system region addresses for linkages to its service

procedures, for memory management data, and for 1/0 processing
routines. The second region is reserved for future use.

General Registers
Instruction operands are often either stored in the processor's general
registers or accessed through them. The 16 32-bit programmable
general registers are labelled RO through R11 (decimal). Registers can

be used for temporary storage, accumulators, base registers, and
index registers. A base register contains the address of the base of a

software data structure such as a table or queue, and an index register
contains a logical offset into a data structure.

Whenever a register is used to contain data, the data are stored in the

register in the same format that would appear in memory. If a quadword or double floating datum is stored in a register, it is actually
stored in two adjacent registers. For example, storing a double fioat-

ing number in register R7 loads both R7 and R8.

Central Processor

Some registers have special significance depending on the instruction
being executed. Registers R12 through R15 have special significance
for many instructions, and therefore have special labels. These special
registers are:

e The Program Counter (PC or R15), which contains the address of
the next byte to be processed in the instruction stream.

e The Stack Pointer (SP or R14), which contains the address of the

base (or top) of a stack maintained for subroutine and procedure

calls.

o The Frame Pointer (FP or R13), which contains the address of the
base of a software data structure stored on the stack called the
stack frame, which is maintained for procedure calls.
e The Argument Pointer (AP or R12), which contains the address of

the base of a software data structure called the argument list, which
is maintained for procedure calls.

A register’s special significance does not preclude its use for other
purposes, except for the Program Counter. The Program Counter
cannot be used as an accumulator, as a temporary register, or as an

index register. In general, however, most users do not use the Stack
Pointer, Argument Pointer, or Frame Pointer for purposes other than

those designated.

Addressing Modes

The processor’s addressing modes allow almost any operand to be
stored in a register or in memory, or as an immediate constant. There
are seven basic addressing modes that use the general registers to
identify the operand location. They include:
o Register mode

e Register Deferred mode
e Autodecrement mode

e Autoincrement mode

e Autoincrement Deferred mode
e Displacement mode

e Displacement Deferred mode

Of these seven basic modes, all except register mode can be modified
by an index register. When an index register is used with a basic mode
to identify an operand, the addressing mode is the name of the basic
mode with the suffix “indexed”. For example, the indexed addressing
mode for register deferred is called “register deferred indexed” mode.
Therefore, in addition to the seven basic addressing modes, the processor recognizes six indexed addressing modes.
47

Central Processor

The processor also provides literal mode addressing, in which an

unsigned 6-bit field in the instruction is interpreted as an integer
or
floating point constant. Table 3-2 summarizes the VAX-11/780 ad-

dressing modes.

Program Counter
The program counter contains the address of the next byte to be
processed in the instruction stream. That is, just before the processor

begins to execute an instruction, the program counter contains the
address of the first byte of the next instruction. General register 15

contains this address. The program counter update is totally transpar-

ent to the programmer.

The Program Counter itself can be used to identify operands. The

assembler translates many types of operand references into address-

ing modes using the Program Counter. Autoincrement mode using the
Program

Counter, or immediate mode, is used to specify in-line

constants other than those available with literal mode addressing.

Au-

toincrement Deferred mode using the Program Counter, or absolute
mode, is used to reference an absolute address. Displacement and
Displacement Deferred modes using the Program Counter are used to

specify an operand using an offset from the current location.

Addressing using the Program Counter enables the programmer to
write position independent code. Position independent code can be

executed anywhere in virtual address space after it has been linked,

since program linkages can be identified as absolute locations in virtu-

al address space and all other addresses can be identified relative to

the current instruction.

The Stack Pointer, Argument Pointer, and Frame Pointer
The Stack Pointer is a register specifically designated for use with

stack structures. To place items on a stack, the programmer can use
autodecrement mode addressing through the Stack Pointer, and to
remove them, use Autoincrement mode. The programmer can refer-

ence and modify the top element on a stack without removing it
by

using Register Deferred mode, and can reference other elements of
the stack using Displacement mode addressing.

The processor designates Register 14 as the Stack Pointer for use with

both the subroutine Branch or Jump instructions, and the procedure

Call instructions. On routine entry, the processor automatically saves

the address of the instruction that follows the routine call on the stack.

It uses the Program Counter and the Stack Pointer to perform the

operation. Before entering the subroutine, the Program Counter con-

tains the address of the instruction following the Branch, Jump, or Call

(Rn)

Autodecrement

-(Rn)

Autoincrement
Autoincrement Deferred

(Rn) +

(Absolute)

Displacement
|

Displacement Deferred

n = 0 through 15
x = 0 through 14

@ (Rn) +

Indexed

@ # address

[Rx]

{‘&T} address nt (Rn)

displaceme

address
@ {VIYTTBY } displacement

(Rn)

108S920.1d [BJjU8D

Z-€ 3|qel

{SI;} # constant

sapo Buissalppy

:-llrfr:errna;diate)

Central Processor

instruction. The Stack Pointer contains the address of the last item on
the stack. The processor pushes the contents of the Program Counter
on the stack. On return from a subroutine, the processor automatically
restores the Program Counter by popping the return address off the

stack.

Also for the procedure Call instructions, the processor designates
Register 12 as an Argument Pointer, and Register 13 as a Frame

Pointer. The Argument Pointer is used to pass the address of the
argument list to a called procedure, and the Frame Pointer is used to

keep track of nested Call instructions.

An argument list is a formal data structure that contains the arguments
required by the procedure being called. Arguments may be actual
addresses of data structures, or addresses of other

values,

procedures. Figure 3-2 illustrates the argument pointer and list. An
argument list can be passed in either of two ways: by passing only its

address, or by passing the entire list on the user stack. The first
method is used to pass long argument lists, or lists that you want to
preserve. The second method is generally used when calling pro-

cedures that do not require arguments, or when building an argument

list dynamically.

N
##65 [+—
a7
ARG

AR.G2

[
Figure 3-2

Argument Pointer and List

The importance of the way the Call instructions work is that nested
calls can be traced back to any previous level. The Call instruction
s

always keep track of nested calls by using the Frame Pointer register.
The Frame Pointer contains the address on the stack of the items
pushed on the stack during the procedure call. The set of
items

pushed on the stack during a procedure cail is known as a call frame
or stack frame. Figure 3-3 illustrates the Call Frame. Since the previous contents of the Current Frame register are saved in each
call

frame, the nested frames form a linked data structure which can be
unwound to any level when an error or exception condition occurs

any procedure.

Central Processor
CALL

FRAME

STACK

GROWTH

5P
*«—

- FP

CONDITION HANDLER
REGISTER

MASK

CONTR.

PSW

OLD AP

OLD FP
RETURN PC

OLD RO-----R1

«———O0LD 5P

Figure 3-3

Call Frame

Processor Status Word

The Processor Status Word (a portion of the Processor Status Longword) is a special processor register that a program uses to check its
status and to control synchronous error conditions. The Processor
Status Word, illustrated in Figure 3-4, contains two sets of bit fields:
e the condition codes
e the trap enable flags

TIITTTT1]

FLOATING UNDERFLOW TRAP ENABLE
INTEGER OVERFLOW TRAP ENABLE
TRACE TRAP ENABLE

NEGATIVE CONDITION CODE
ZERO CONDITION COOE
OVERFLOW CONDITION CODE

CARRY [BORROW) CONDITION CODE

Figure 3-4

Processor Status Word

The condition codes indicate the outcome of a particular logical or
arithmetic operation. For example, the Subtract instruction sets the
Negative bit if the result of the subtraction operation produced a negative number, and it sets the Zero bit if the result produced zero. The
31

Central Processor

programmer can then

use the Branch on Condition instruct
ions to

transfer control to a code sequence that

handles the condition.

There are two kinds of traps that concern the

and arithmetic traps. The trace trap is used

Arithmetic traps include:

user process: trace traps
for debugging programs.

e integer, floating point, or decimal string overfiow
was too large to be stored in the given format

e integer, floating point, or decimal string divide

divisor supplied was zero

, in which the result

by zero, in which the

‘

e floating point underflow, in which the
result was too small to be
expressed in the given format

Handling Exceptions
When an exception occurs, the processor

immediately saves the cur-

rent state of execution and traps to the
operating system. The
operating system automatically searches
for a procedure that wants to

handle the exception. Procedures that respon
d to exceptions are

called condition handlers. The user can
declare a condition handler
for an entire image and for each individual
procedure called. In addition, because the processor keeps track
of nested calls using the
Frame Pointer register, it is possible to declare
condition handlers for
procedures that call other procedures in which
exceptions might occur. The operating system automatically
traces back through call

frames to find a condition handier that wants

that occurs.

to handle an exception

SYSTEM PROGRAMMING CONCEPTS

The processor is specifically designed to support

a high-performance

multiprogramming environment. The characte
ristics of the hardware
system that support multiprogramming are:
¢ rapid context switching
e priority dispatching

e virtual addressing and memory manage
ment

As a multiprogramming system, VAX-11/780
not only provides the
ability to share the processor among process
es, but also protects
processes from one another while enablin

each other and to share code and data.

g them to communicate with

Context Switching
In a multiprogramming environment, several
individual streams of
code can be ready to execute at any one time.

To support multiprogramming for a high-performan
ce system, the
52

Central Processor

processor enables the operating system to switch rapidly between
individual streams of code. A process is a stream of instructions and
data defined by a hardware context. Each process has a unique identification in the system. At any one time, the stream of code being
executed is determined by its hardware context. Hardware context
includes the information loaded in the processor’s registers that identifies:

e where the stream’s instructions and data are located
e which instruction to execute next

e what the processor status is during execution

The operating system switches between processes by requesting the
processor to save one process hardware context and load another.
Context switching occurs rapidly because the processor instruction
set includes save hardware context and load hardware context instructions. The operating system’s context switching software does
not have to individually save or load the processor registers which
define the hardware context.

Priority Dispatching

To share processor, memory, and peripheral resources among many

processes, the processor provides two arbitration mechanisms that
support high-performance multiprogramming: exceptions and interrupts. Exceptions are events that occur synchronously with respect to
instruction execution, while interrupts are external events that occur
asynchronously.

The flow of execution can change at any time, and the processor

distinguishes between changes in flow that are local to a process and
those that are system-wide. Process-local changes occur as the result
of a user software error or when user software calls operating system

services. Process-local changes in program flow are handled through
the processor's exception detection mechanism and the operating
system’s exception dispatcher.

System-wide changes in flow generally occur as the result of

interrupts from devices or interrupts generated by the operating system software. Interrupts are handied by the processor’s interrupt detection mechanism and the operating system’s interrupt service routines.

System-wide changes in flow take priority over process-local changes
in flow. Furthermore, the processor uses a priority system for servicing
interrupts. To arbitrate between all possible interrupts, each kind of
interrupt is assigned a priority, and the processor responds to the
highest priority interrupt that is pending.
53

Central Processor

The processor services interrupts between instructions, or at well-

defined

points during the execution of long, iterative instructions.
When the processor acknowledges an interrupt, it switches rapidly to

a special system-wide context to enable the operating system to service the interrupt. System-wide changes in the flow of execution are
totally transparent to individual processes.

Virtual Addressing and Virtual Memory
The processor’s memory management hardware enables the operating system to provide an environment that allows users to write pro-

grams without having to know where the programs are loaded
in

physical memory, and to write programs that are too large to fit in the
physical memory allocated.

The processor provides the operating system with the ability to provide virtual addressing. A virtual address is a 32-bit integer that a
program uses to identify storage locations in virtual memory.
Virtual

memory is the set of all physical memory locations in the system plus

the set of disk blocks that the operating system designates as exten-

sions to physical memory.

A physical address is an address that the processor uses to identify
physical memory storage locations and peripheral controller registers.

It is the address that the processor sends out on the SBI bus to which
the memory and peripheral adapters respond.

The processor must be able to translate the virtual addresses provided by the programs it executes into the physical addresses recognized

by the memory and peripherals. To provide virtual to physical address

mapping, the processor has address mapping registers controlled by

the operating system and an integrated address translation buffer.

The mapping registers enable the operating system to relocate pro-

grams in physical memory, to protect programs from each other,
and
to share instructions and data between programs transparent
ly or at
their request. The address translation buffer ensures that the virtual

address to physical address translation takes place rapidly.

SYSTEM PROGRAMMING ENVIRONMENT

Within the context of one process, user-level software controls its

execution using the instruction sets, the general registers, and
the

Processor Status Word. Within the multiprogramming environment,
the operating system controls the system’s execution using a set of
special instructions, the Processor Status Longword, and the internal
processor registers.

Central Processor

Processor Status Longword

A processor register called the Processor Status Longword (PSL) determines the execution state of the processor at any time. The loworder 16 bits of the Processor Status Longword is the Processor Status Word available to the user process. The high-order 16 bits provide
privileged control of the system. Figure 3-5 illustrates the Processor
Status Longword.

The fields can be grouped together by functions that control:
e the instruction set the processor is executing

e the access mode of the current instruction
e interrupt processing

INTLLN

6 15

20
Il

PROCESSOR STATUS WORD

—

INTERRUPT PRIORITY LEVEL
PREVIOUS ACCESS MODE

CURRENT ACCESS MODE

EXECUTING ON THE INTERRUPT STACK
INSTRUCTION FIRST PART DONE

!
l

TRACE PENDING

COMPATABILITY MODE

Figure 3-5

Processor Status Longword

The instruction set the processor executes is controlled by the
compatibility mode bit in the Processor Status Longword. This bit is
normally set or cleared by the operating system. The initial environment is established by the operating system but any process, including user, can change it. In particular, compatibility mode processes
switch to native mode with EMTs and native processes can perform an
REI instruction to get into compatibility mode.
Processor Access Modes

In a high-performance multiprogramming system, the processor must

provide the basis for protection and sharing among the processes

competing for the system’s resources. The basis for protection in this
system is the processor’s access mode. The access mode in which the

processor executes determines:

e instruction execution privileges: what instructions the processor will
execute

e memory access privileges: which locations in memory the current
instruction can access
55

Central Processor

At any one time, the processor is executing code in the context of a

particular process, or it is executing in the system-wide interrupt service context. In the context of a process, the processor recognizes four
access modes: kernel, executive, supervisor, and user. Kernel is the
most privileged mode and user the least privileged.

The processor spends most of its time executing in user mode in the
context of one process or another. When user software needs the
services of the operating system, whether for acquisition of a
resource, for 1/0 processing, or for information, it calls those services.

The processor executes those services in the same or one of the more
privileged access modes within the context of that process. That is, all
four access modes exist within the same virtual address space. Each
access mode has its own stack in the control region of per-process

space, therefore each process has four stacks: one for each access
mode. Note that this makes it easy for the operating system to context
switch a process even when it is executing an operating system service procedure.

In any mode except kernel, the processor will not execute instructions

that:
e halt the processor

e load and save process context
e access the internal processor registers that control memory management, interrupt processing, the processor console, or the proc-

essor clock

These instructions are privileged instructions that are generally reserved to the operating system.
In any mode, the processor will not allow the current instruction to
access memory unless the mode is privileged to do so. The ability to

execute code in one of the more privileged modes is granted by the
system manager and controlled by the operating system. The memory

protection

the

privilege affords

enforced

by the

processor.

general, code executing in one mode can protect itself and any portion

of its data structures from read and/or write access by code executing
in any less privileged mode. For example, code executing in executive
mode can protect its data structures from code executing in supervisor or user mode. Code executing in supervisor mode can protect its

data structures from access by code executing in user mode. This
memory protection mechanism provides the basis for system data

structure integrity.

Protected and Privileged Instructions

The processor provides three types of instructions that enable user
56

Central Processor

mode software to obtain operating system services without jeopardizing the integrity of the system. They include:
e the Change Mode instructions

e the PROBE instructions

e the Return from Exception or Interrupt instruction

User mode software can obtain privileged services by calling operating system service procedures with a standard CALL instruction. The
operating system’s service dispatcher issues an appropriate Change
Mode instruction before actually entering the procedure. Change
Mode allows access mode transitions to take place from one mode to
the same or more privileged mode only. When the mode transition
takes place, the previous mode is saved in the Previous Mode field of
the Processor Status Longword, allowing the more privileged code to
determine the privilege of its caller.

A Change Mode instruction is simply a special trap instruction that can
be thought of as an operating system service call instruction. User
mode software can explicitly issue Change Mode instructions, but
since the operating system receives the trap, non-privileged users
cannot write any code to execute in any of the privileged access
modes. User mode software can include a condition handler for
Change Mode to User traps, however, and this instruction is useful for
providing general purpose services for user mode software. The system manager ultimately grants the privilege to write any code that
handles Change Mode traps to more privileged access modes.
For service procedures written to execute in privileged access modes
(kernel, executive, and supervisor), the processor provides address
access privilege validation instructions. The PROBE instructions enable a procedure to check the read (PROBER) and write (PROBEW)
access protection of pages in memory against the privileges of the
caller who requested access to a particular location. This enables the
operating system to provide services that execute in privileged modes
to less privileged callers and still prevent the caller from accessing
protected areas of memory.

The operating system’s privileged service procedures and interrupt
and exception service routines exit using the Return from Exception or
Interrupt (REI) instruction. REI is the only way in which the privilege of
the processor’s access mode can be decreased. Like the procedure
and subroutine return instructions, REI restores the Program Counter
and the processor state to resume the process at the point where it
was interrupted.

REI performs special services, however, that normal return instruc-

Central Processor

tions do not. For example, REI checks to see if any asynchronous
system traps have been queued for the currently executing process

while the interrupt or exception service routine was executing, and
ensures that the process will receive them. Furthermore, REI checks to
ensure that the mode to which it is returning control is the same as, or

less privileged than, the mode in which the processor was executing
when the exception or interrupt occurred. Thus REI is available to all
software, including user-written trap handling routines, but a program
cannot increase its privilege by altering the processor state to be re-

stored.

When the operating system schedules a context switching operation,
the context switching procedure uses the Save Process Context
(SVPCTX) and Load Process Context (LDPCTX) instructions to save
the current process context and load another. The operating system’s
context switching procedure identifies the location of the hardware
context to be loaded by updating an internal processor register.

Internal processor registers include not only those that identify the

process currently executing, but also the memory management and
other registers, such as the console and clock control registers. The
Move to Processor Register (MTPR) and Move from Processor Register (MFPR) instructions are the only instructions that can explicitly

access the internal processor registers. MTPR and MFPR are
privileged instructions that can be issued only in kernel mode.
Memory Management
The processor is responsible for enforcing memory protection
between access modes. Memory protection, however, is only a part of

the

processor's

memory management function.

particular,

the

memory management hardware enables the operating system to pro-

vide an extremely flexible and efficient virtual memory programming
environment. Virtual and physical address space definitions provide
the basis for the virtual memory available on a system.

Virtual address space consists of all possible 32-bit addresses that
can be exchanged between a program and the processor to identify a
byte location in physical memory. The memory management hardware transiates a virtual address into a 30-bit physical address. A

physical address is the address exchanged between the processor
and the memory and peripheral adapters over the SBI bus. Physical

address space is the set of all possible physical addresses the processor can use to express unigue memory locations and peripheral con-

trol registers.

Physical address space is an array of addresses which can be used to

Centiral Processor

represent 23° byte locations, or approximately one billion bytes. Half of
the addresses in physical address space can be used to refer to real

memory locations and the other half can be used to refer to peripheral

device control and data registers. The lowest addressed half of
physical address space is called memory space, and the highestaddressed half I/0 space.

Chapter 6, Memory Management, describes the way in which the

memory management hardware enables the operating system to map
virtual addresses into physical addresses to provide the virtual memory available to a user process.

Virtual to Physical Page Mapping

Virtual address space is divided into pages, where a page represents
512 bytes of contiguously addressed memory. The first page begins at
byte zero and continues to byte 511. The next page begins at byte 512
and continues to byte 1023, and so forth. The first eight pages of
virtual address space, and their addresses in both decimal and hexadecimal are:

PAGE
0
1
2
3
4
5
6
7

ADDRESS(10)

ADDRESS(16)

0000-0511
0512-1023
1024-1535
1536-2047
2048-2559
2560-3071
3072-3583
3584-4095

0000-01FF
0200-03FF
0400-05FF
0600-07FF
0800-09FF
0A00-OBFF
0C00-0DFF
0E00-OFFF

The size of a virtual page exactly corresponds to the size of a physical
page of memory, and the size of a block on disk.

To make memory mapping efficient, the processor must be able to
translate virtual addresses to physical addresses rapidly. Two features
providing rapid address translation are the processor’s internal address translation buffer, which is described later, and the translation
algorithm itself.

Figure 3-6 compares the virtual and physical address format. The
high-order two bits of a virtual address immediately identify the region
to which the virtual address refers. Whether the address is physical or
virtual, the byte within the page is the same. Thus, the processor has to
know only which virtual pages correspond to which physical pages.

Central Processor

VIRTUAL ADDRESS

31 3029 28

l l 0

VIRTUAL PAGE NUMBER

s BYTE WITHIN PAGE —»

MEMORY ADDRESS
1/0 SPACE ADDRESS
PHYSICAL ADDRESS

31 30 29 28

9 [ 8

‘ ‘ *———
PAGE FRAME NUMBER
0

+<—BYTE WITHIN PAGE —»

MEMORY ADDRESS
I/O SPACE ADDRESS

Figure 3-6

Virtual and Physical Address Format

The processor has three pairs of page mapping registers, one pair for
each of the three regions actively used. The operating system’s memory management software loads each pair of registers with the
base

address and length of data structures it sets up called page tables.
The page tables provide the mapping information for each virtual page
in the system. There is one page table for each of the three regions,

A page table is a virtually contiguous array of page table entries. Each

page table entry is a iongword representing the physical mapping for
one virtual page. To translate a virtual address to a physical address,

therefore, the processor simply uses the virtual page number as an
index into the page table from the given page table base address.

Each translation is good for 512 virtual addresses since the byte within
the virtual page corresponds to the byte within the physical page.

Exception and Interrupt Vectors
The processor can automatically initiate changes in the normal flow of
program execution. The processor recognizes two kinds of events

that

cause it to invoke conditional software: exceptions and interrupts.

Some exceptions affect an individual process only, such as arithmetic

traps, while others affect the system as a whole, for example, machine

check. Interrupts include both device interrupts, such as those signal-

ing 1/0 completion, and software-requested interrupts, such as those
signaling the need for a context switch operation.

The processor knows which software to invoke when an exception or
interrupt occurs because it references specific locations, called vec-

tors, to obtain the starting address of the exception or interrupt dis-

patcher. The processor has one internal register, the System Control

Block Base Register, which the operating system loads with the physi-

cal address of the base of the System Control Block, which contains

Central Processor

rs. The processor locates each
the exception and interrupt tvecto
the System Control Block. Figure
vector by using a specific offse into
em Control Block. Each vector
3.7 illustrates the vectors in theceSyst
, and contains the system
the
tells the processor how to servi ine toevent
execute. Note that vector 14region virtual address of thetorout
control store to execuie user
(hex) can be used as a trap writorablecont
ains information passed to
defined instructions, and the vect
microcode.

r synchronously
arbitration since they ,occu
Exceptions do not require
other hand,
on
execution. Interrupts therequ
with respect to instruction
ests that
rupt
inter
een
betw
arbitrate
can occur at any time. To the
rrupt priinte
31
es
gniz
reco
r
esso
proc
may occur simuitaneously,

Interrupt Priority Levels

ority levels.

levels are reserved for interruptssgenThe highest 16 interrupt prioritylowe
st 16 interrupt priority level are
erated by hardware, and the
assoftware. Table 3-3 lists theuser
by
d
reserved for interrupts requeste
al
Norm
ity.
highest to lowest priority
signment of each level, from
level zero.
prior
t
rrup
inte
is
h
whic
,
fevel
ess
proc
software runs at

a special system, the processor enters esso
To handle interrupt requests
r executes in
proc
the
em-wide context,
wide context. In the systial
k. The interstac
t
rrup
inte
the
ed
k call
kernel mode using a spec rencstac
ause
ware
ed by any user mode soft rrupt,becand
rupt stack cannot be refe
all
inte
an
r
cts the interrupt stack afte

sele
the processor onlyped
interrupts are trap through system vectors.
rrupt priority level of
ine executes at the inte
The interrupt service routWhe
an interrupt
the processor receivesutin
the interrupt request.er thannthat
g software,
exec
y
of the currentl
request at a level highthe request and
rrupt atits
inte
new
the
ices
the processor honors interrupt serviceserv
ine issues the REI (Return
priority level. When the t) instruction, rout
the processor returns control
from Exception or Interrup
to the previous level.

us and data registers.
has a set of control/stat
An 1/0 device controllergned
space, and
esses in physical address
- The registers are assi s aréaddr
the operby
d,
ecte
prot
mapped, and thus
their physical addresse age
of physiion
port
That
.
ware
t soft
ating system’s memory manh devimen
ted is
loca
are
s
ster
regi
er
roll
cont
ce
cal address space in whic
called 1/0 space.
ical address
I/O space occupies the highest-addressed half of phys
1/O Space and I/O Processing

Central Processor

Machine Check
Kernel Stack Not Valid

Power Fail
Reserved or Privileged Instru

ction
Customer Reserved Instruction

Reserved or Iliegal Operand
Reserved or lllegal Addressing
Mode
Access Violation
Translation Not Valid (page
fault)
Trace Trap

Breakpoint Trap

? EXCEPTION VECTORS

Compatibility Mode Trap
Arithmetic Trap

Change Mode to Kernel
Change Mode to Executive

Change Mode to Supervisor
Change Mode 1o User

Software Level 1
Software Level 2

Software Level F
Interval Timer

100
101

13F
140

17F
180

1BF

1CO

1FF

Device Level 14, device 0
Device Level 14, device 1

Device Level 14, device 15
Device Level 15, device 0

? INTERRUPT VECTORS

Device Level 15, device 15
Device Level 18, device 0

Device Level 16, device 15
Device Level 17, device 0

Device Level 17, device 15

Offset from System Control

Block Base Register (HEX)

Figure 3-7

System Control Block

Central Processor

Table 3-3

Interrupt Priority Levels

HARDWARE EVENT

PRIORITY

Hex

Decimal

17
16
15

13
12
11

23
22
21

19
18
17

Machine Check, Kernel Stack Not Valid
[Power Fail

‘

Memory, or

Bus Error
|Clock

7
SOFTWARE EVENT

14
13

OA
09

10
09

01
00

Reserved for
DIGITAL

12
11

$ Device Interrupt

|UNIBUS BR4

OE
0D

0C
0B

)

|UNIBUS BR7
JUNIBUS BR6
|UNIBUS BR6

PRIORITY
OF

Processor,

Device
Drivers

|Timer Process -

|Reserved for DIGITAL

01
00

|Queue Asynchronous System Trap (AST)
|[I/0 Post

|Process Scheduler

|AST Delivery

[|Reserved for DIGITAL
|User Process Level

Central Processor

space, and is 229 bytes in length. A portion of 1/0 space is
mapped into UNIBUS addresses, and is called UNIBUS

specifically

space.

No special processor instructions are needed to referenc
e I/0 space.
The registers are simply treated as locations containi
ng integer data.
An /0 device driver issues commands to the periphera
l controller by

writing to the controller’s registers as if they were physical
memory

locations. The software reads the registers to obtain
the controller

status. Note that accesses to UNIBUS registers may be

made with byte
or word instructions only. The driver controls interrupt
enabling and

disabling on the set of controllers for which it is responsib
le. When
interrupts are enabled, an interrupt occurs when
the controller re-

quests it. The processor accepts the interrupt request
and executes

the driver’s interrupt service routine if it is not currently
higher priority interrupt level.

executingon a

Process Context
For each process eligible to execute, the operating system creates a

data structure called the software process control block. Within the
software process control block is a pointer to a data structure called

the hardware process control block. It contains the hardware process
context,

i.e., all the data needed to load the processor’s
programmable registers when a context switch occurs. To give control

of the processor to a process, the operating system loads the processor’s Process Control Block Base register with the physical address of

a hardware process control block and issues the Load Process Context instruction. The processor loads the process context in one oper-

ation and is ready to execute code within that context.

process

control

block

not only contains the state of the

programmable registers, it also contains the definitio
n of the process

virtual address space. Thus, the mapping of the process

cally context-switched.

is automati-

Furthermore, the process control block provides the
mechanism for
triggering asynchronous system traps to user processe
s. The Asynchronous System Trap field enables the processor
to schedule a software interrupt to initiate an AST routine and ensure
that itis delivered
to the proper access mode for the process.

I R

| i

CHAPTER 4

PROCESS STRUCTURE
ITION

PROCESS DEFIN
ion by the VAXA process is the basic entity schedulabled for execut
space and both
ss
addre
an
of
ts
consis
ss
proce
11/780 processor. A
a process is
hardware and software context. The hardware contextnsofimage
s of the
contai
defined by a Process Control Block (PCB) that
(PSL),
ord
longw
status
sor
proces
14 general purpose registers, the
s, the
pointer
stack
ocess
per-pr
four
the
the program counter (PC),
ers
regist
length
and
base
the
by
d
define
y
memor
process virtual
In
fields.
l
contro
POBR, POLR, P1BR, and P1LR, and several minor must be moved
PCB
the
of
ty
order for a process to execute, the majori
some of its
into internal registers. While a process is being executed, rs.
When a
registe
l
interna
the
in
ed
updat
being
is
t
hardware contex
in the
stored
is
t
contex
process is not being executed, its hardware
rs
registe
eged
privil
the
of
ts
process control block. Saving the conten

a new
in the PCB of the currently executing process and then loadingterme
d

set of context in the privileged registers from another PCB is s after
context switching. Context switching occurs as one proces
another is scheduled for execution.
PROCESS CONTEXT

Process Control Block Base (PCBB)

s is pointThe process control block for the currently executing proces
) regis(PCBB
Base
Block
l
Contro
ed to by the content of the Process
Base
Block
l
Contro
s
Proces
The
r.
registe
ter, an internal privileged
register is illustrated in Figure 4-1.

323029
7

MBZ l

Figure 4-1

PHYSICAL LONGWORD ADDRESS OF PCB

2 10

MBZ

Process Control Block Base Register (Read/Write)
67

Process Structure

Process Control Block (PCB)
The process control block (PCB) contai

ns all of the switchable process

context collected into a compact form
for ease of movement to and

from the privileged internal registers.

Although in any normal operat-

ing system there is additional software contex

following description is limited to that portion

t for each process, the
of the PCB known to the

hardware. The process control block is illustra

ted in Figure 4-2.

PROCESS

CONTROL BLOCK {PCB)

KSP

1PCB

ESP

Ssp

use

212

c 16

120

124

128

132

136

140

144

1 48

152

RIO

:56

160

AP(R12}

164

FP(R13)

172

PSL

176

POBR
MBZ

AST-LVL |MBZ

180
POLR

P1BR

I\:A

MBZ

- 88

PILR

Figure 4-2

Process Control Block

184

192

Process Structure

A description of the process control block follows;
Long

word Bits

Mnemonic Description

<31:0> KSP

Kernel Stack Pointer. Contains the

stack pointer to be used when the
current access mode field in the
Processor Siatus Longword (PSL) is
zero and Interrupt Stack (IS) is
zero.

<31:0> ESP

Executive Stack Pointer. Contains

the stack pointer to be used when
the current access mode field in the
PSLis 1.

<31:0> SSP

Supervisor Stack Pointer. Contains

the stack pointer to be used when
the current access mode field in the
PSLis 2.

<31:0> USP

User Stack Pointer. Contains the

stack pointer to be used when the
current access mode field in the PSL
is 3.

4-17

<31:0> RO-R11,

General registers R0-R11, AP, and

<31:0> PC

Program Counter.

<31:0> PSL

Program Status Longword.

<31:0> POBR

AP,FP

FP.

Base register for page table de-

scribing process virtual addresses
from zero to 23°—1.

<21:0> POLR

Length register for page table

located by POBR. Describes effective

fength of page table.

<23:22>MBZ

Must be zere.

Process Structure

<26:24> ASTLVL

Contains access mode number established by software of the most

privileged access mode for which an
Asynchronous System Trap is pending.

(ASTs will be discussed in the next
section.) Controls the triggering
of the AST delivery interrupt dur-

ing REI (return from interrupt or
exception) instructions.

ASTLVL
0
1

2
3

4
5-7

Meaning
AST pending for access mode 0 (kernel)

AST pending for access mode 1 (executive)
AST pending for access mode 2 (supervisor)

AST pending for access mode 3 (user)

No pending AST

Reserved to DIGITAL

<31:27>MBZ

Must be zero.

<31:0>

Base register for page table describing process virtual addresses

P1BR

from 23°t0 23'—1,
23

<21:0>

P1LR

Length register for page table located by P1BR. Describes effective

length of page table.

<30:22>MBZ

Must be zero.

<31>

Performance Monitor Enable. Controls
a signal visible to an external

PME

hardware performance monitor. This
bitis set to identify those processes for which monitoring is de-

sired and to permit their behavior

to be observed without interference
from other system activity.

Process Structure

Software symbols are defined for these locations by using the prefix
PTX$L_and the mnemonic shown above. For example, the PCB offset
to R3 is PTX$L_R3. The following are also defined:
Longword 21

PTX$L_POLRASTL

PTX$L_P1LRPME

Longword 23

To alter its POBR, P1BR, POLR, P1LR, ASTLVL or PME, a process
must be executing in kernel mode. It must first store the desired new
value in the memory image of the PCB, then move the value to the
appropriate privileged register. This protocol results from the fact that
these are read-only fields (for the context switch instructions) in the
process control block.

Process Privileged Registers

The ASTLVL and PME fields of the PCB are contained in registers
when the process is running. In order to access them, two privileged
registers are provided. These are the AST Level register and the PME
register. The AST Level register is illustrated in Figure 4-3.

3.2

3
IGNORED; RETURNS O

Figure 4-3

AST-LVL

AST Level Register (Read/Write)

31
MBZ

Figure 4-4

Performance Monitor Enable Register (Read/Write)

At bootstrap time, PME is cleared.
71

mZvlo

An MTPR src, #ASTLVL with src<2:0> GEQU 5 results in a reserved
operand fault. At bootstrap time, the content of ASTLVL is 4. The
Performance Monitor Enable register is illustrated in Figure 4-4.

Process Structure

ASYNCHRONOUS SYSTEM TRAPS (AST)
Asynchronous System Traps are a technique for notifying a process of
events that are not synchronized with its execution and initiating processing for asynchronous events with the least possibie delay. The
delay in delivery may be due to either process nonresidence or an
access mode mismatch. The efficient handling of ASTs in VAX-11
requires some hardware assistance to detect changes in access mode
(current access mode in PSL). Each of the four execution access

modes, kernel, executive, supervisor, and user, may receive ASTSs;
however, an AST for a less privileged access mode must not be permitted to interrupt execution in a more protected access mode. Since
outward access mode transitions occur only in the REIl instruction,
comparison of the current access mode field is made with a privileged

ber for which an AST is pending. If the new access mode is greater
than or equal to the pending ASTLVL, an IPL 2 interrupt is triggered to

cause delivery of the pending AST.

General Software Flow for AST processing:
1.

Anevent associated with an AST causes software enqueuing of an

AST control block to the software PCB, and the software sets the
ASTLVL field in the hardware PCB to the most privileged access
mode for which an AST is pending. If the target process is currently executing, the ASTLVL privileged register also has to be
set.

The (IPL2) interrupt service routine should compute the correct

new value for ASTLVL that prevents additional AST delivery interrupts while in kernel mode, and move that vaiue to the PCB and

the ASTLVL register before lowering IPL and actually dispatching
the AST. This interrupt service routine normally executes on the
kernel stack in the context of the process receiving the AST.

The (IPL2) interrupt service routine should compute the correct
new value for ASTLVL that

prevents additional AST delivery

interrupts while in kernel mode and move that value to the PCB
and the ASTLVL register before lowering IPL and actually dispatching the AST. This interrupt service routine normally executes on the kernel stack in the context of the process receiving

the AST.
4.

At the conclusion of processing for an AST, the ASTLVL is recomputed and moved to the PCB and ASTLVL register by software.

PROCESS STRUCTURE INTERRUPTS
Two of the software interrupt priorities are reserved for process structure software.

Th ey are :

Process Structure

(IPL.2) — AST delivery interrupt.

This interrupt is triggered by an REI that detects PSL <current mode>
GEQU ASTLVL and indicates that a pending AST may now be
delivered for the currently executing process.
(IPL3) — Process scheduling interrupt.

This interrupt is only triggered by software to allow the software run-

ning at IPL 3 to cause the currently executing process to be blocked
and the highest priority executable process to be scheduled.

PROCESS STRUCTURE INSTRUCTIONS
Process scheduling software must execute on the interrupt stack
(PSL<IS> set) in order to have a noncontext-switched stack available
for use. If the scheduler were running on a process’s kernel stack, then
any state information it had there would disappear when a new process is selected. Running on the interrupt stack can occur as the result
of the interrupt origin of scheduling events; however, some synchronous scheduling requests such as a WAIT service may cause rescheduling without any interrupt occurrence. For this reason, the Save
Process Context (SVPCTX) instruction can be executed while on either the kernel or interrupt stack and forces a transition to execution
on the interrupt stack.

All of the process structure instructions are privileged and may only be
executed in kernel mode. In the following description of the load and
store process context instructions, the following notation conventions
are used:

Notation

tmp

Meaning

tmp1 and tmp2 are pseudo registers which are not
normally implemented in hardware
indicates comment statement

-«

()

<N:M>
i}

[]

the back arrow is an assignment operator, i.e., the

value indicated on the right is copied to the register
or pseudo register indicated on the left

this indicates the contents of the address specified
by the included expression

this notation indicates the field consisting of bits N

thru M of the immediately preceding value
indicate an exception

used to group terms for clarity, and usually appear in
logical expressions

Process Structure

LDPCTX Load Process Context
Purpose: restore register and memory management context

Format: Opcode

Operation:
if PSL<current mode> NEQU 0 then

{privileged instruction fault};
{invalidate per-process translation buffer entries};
IPCB is located by physical address in PCBB

KSP<(PCB);
ESP<«(PCB+4);

SSP<«(PCB+8);
USP<«(PCB+12);
RO<(PCB+16);
R1<«(PCB+20);
R2<«(PCB+24);
R3<«(PCB+28);
R4<«(PCB+32);

R5«(PCB+36);
R6<«(PCB+40);
R7<(PCB+44);

R8<«(PCB+48);
R9<«(PCB+52);
R10<—(PCB+56);

R11<«(PCB+60);
AP<—(PCB+64);

FP<(PCB+68);
tmp1<(PCB+80);
if tmp1<31:30> NEQU 2] OR [tmp1<1:0> NEQU 0] then

{reserved operand abort};
POBR<«tmp1;
if (PCB+84)<31:27> NEQU 0 then {reserved operand abort};

if (PCB+84)<23:22> NEQU 0 then {reserved operand abort};
POLR<—(PCB+84)<21:0>:

if (PCB+84)<26:24> GEQU 5 then {reserved operand abort};
ASTLVL<«(PCB+84)<26:24>;
tmp1<—(PCB+88);

tmp2<«tmp1 + 228
if tmp2<31:30> NEQU 2] OR [tmp2<1:0> NEQU 0] then

{reserved operand instruction};
P1BR<«tmp1;

if (PCB +92)<30:22> NEQU 0 then

{reserved operand fault};
P1LR«(PCB+92)<21:0>;

Process Structure

PME<«(PCB+92)<31>;

if (PCB+92)<30:22> NEQU 0 then {reserved operand abort};
if PSL <I1S> EQLU 1 then
begin

ISP<-SP;

{interrupts off};
PSL<IS><0;

Iget KSP

SP<«(PCB);
finterrupts on};
end;

Ipush PSL
Ipush PC

—{SP)<—(PCB+76),
—(SP)<«(PCB+72);
Condition Codes:
N<N;

Z<Z;

V<V,

C<C;
Exceptions:

reserved operand

reserved instruction
Opcodes:

06 LDPCTX Load Process Context
Description:

The Process Control Block is specified by the privileged register
Process Control Block Base. The general registers are loaded from
the PCB. The memory management registers describing the process
address space are also loaded and the process entries in the translation buffer are cleared. Execution is switched to the kernel stack. The
PC and PSL are moved from the PCB to the stack, suitable for use by a
subsequent REI instruction.
NOTE

Some processors keep a copy of each of the perprocess stack pointers in internal registers. In those
processors that do, LDPCTX loads the internal registers from the PCB. Those processors that do not
keep a copy of all four per-process stack pointers in
internal registers keep only the current access mode
switch this with
=1
g-w-v- and
register in an internal register
1OYivewT
the PCB contents whenever the current access
mode field changes.

Process Structure

SVPCTX Save Process Context
Purpose: Save register context

Format: Opcode

Operation:

if PSL<current mode> NEQU 0 then

{privileged instruction fault};
IPCB is located by the physical address in PCBB
(PCB)<KSP;
(PCB+4)<ESP;
(PCB+8)<«<SSP;
(PCB+12)<-USP;

(PCB+16)<R0;

(PCB+20)<«R1;
(PCB+24)«<R2;
(PCB+28)«-R3;
(PCB+32)<«R4;
(PCB+36)<«R5;

(PCB+40)<R6;
(PCB+44)<«R7;
(PCB+48)<«RS;
(PCB+52)«R9;

(PCB+56)<«R10;
(PCB+60)«R11;
(PCB+64)«AP;
(PCB+68)<FP;

(PCB+72)«(SP)+;

Ipop PC

(PCB+76)«(SP)+;

'pop PSL

if PSL<IS> EQLU 0 then

begin
PSL<IPL><MAXU(1, PSL<IPL>);

(PCB)<SP;

Isave KSP

{interrupts off};
PSL<IS> «1;

SP <« ISP;

{interrupts onj;
end;

Condition Codes:
N<N:;

Z<2Z;
VeV,

C<_C:

Process Structure

Exceptions:

reserved instruction

Opcodes:

07 SVPCTX Save Process Context
Description:

The Process Control Block is specified by the privileged register Proc-

ess Control Block Base. The general registers are saved into the PCB.
The PC and PSL currently on the top of the current stack are popped

and stored in the PCB. If a SVPCTX instruction is executed when IS is
clear, then IS is set, the interrupt stack pointer activated, and IPL is
maximized with 1 because of the switch to the interrupt stack.
Notes:

The map, ASTLVL, and PME contents of the PCB are not saved
because they are rarely changed. Thus, not writing them saves
overhead.

Some processors keep a copy of each of the per-process stack
pointers in internal registers. In those processors that do,

SVPCTX stores the internal registers into the PCB. Those processors that do not keep a copy of all four per-process stack pointers
in internal registers, keep only the current access mode register in

an internal register and switch this with the PCB contents whenever the current access mode field changes.

Between the SVPCTX instruction that saves the state for one process and the LDPCTX that loads the state of another, the internal
stack pointers may not be referenced by MFPR or MTPR instructions. This implies that interrupt service routines invoked at a
priority higher than the lowest one used for context switching

must not reference the process stack pointers.

USAGE EXAMPLE
The following example is intended to illustrate how the process struc-

ture instructions can be used to implement process dispatching software. It is assumed that this simple dispatcher is always entered via an
interrupt.

;

ENTERED VIA INTERRUPT

IPL=3

RESCHED: SVPCTX

:Save context in PCB

<set state to runnable>
77

Process Structure

MTPR @#PHYSPCB,PCBB

;Set physical PCB
address in PCBB

LDPCTX

;Load context from

PCB
;For new process

REI

;Place process in

execution

diilgiiitial

VAX 1/780

MO Il
llIIIllllllIlllll_llllllll!l!l_lI!!ljll_llldll 1L

CHAPTER 5

EXCEPTIONS AND INTERRUPTS
INTRODUCTION
s within the
At certain times during the operation of a system, event
outside
softwa
of
system require the execution of particular pieces control byreforcin
ga
ers
transf
ssor
the explicit flow of control. The proce
curthe
in
ted
indica
tly
explici
that
from
l
contro
change in the flow of
rently executing process.

currently executing
Some of the events are relevant primarily to the
t of the current
contex
the
in
re
process and normally invoke softwa
ion.

process. The notification of such events is termed an except
the system as a
Other events are relevant to other processes, or tocontex
notifie
m-wid
whole, and are therefore serviced in a syste interrupt, andt.theThesyste
man
d
terme
is
cation process for these events
upt stack” (IS).

interr
wide context is described as “executing on cythethat
they require high
urgen
such
of
are
upts
interr
Further, some
with independent
ed
roniz
priority service, while others must be synch
y logic that
priorit
has
ssor
proce
events. To meet these needs, the
point in
any
at
event
ty
priori
st
highe
the
to
e
grants interrupt servic
upt
interr
its
d
time. The priority associated with an interrupt is terme
priority level (IPL).

to priority. Only
The processor arbitrates interrupt requests according
the current IPL
than
higher
is
st
reque
upt
interr
when the priority of an
processor
(Bits <20:16> of the processor status longword) will the upt
service
interr
The
t.
raise the IPL and service the interrupt reques
usually
not
will
and
st
reque
upt
routine is entered at the IPL of the interr
the
from
ent
differ
is
this
that
Note
sor.
proces
change the IPL set by the

PDP-11 where the interrupt vector specifies the IPL for the ISR.
procesInterrupt requests can come from devices, controllers, othermode
can
kernel
in
ing
execut
are
sors, or the processor itself. Softw

MTPR src, #
raise and lower the priority of the processor by executing
a processor
er,
Howev
d.
desire
y
priorit
new
the
ns
contai
src
IPL where
the prirmore,
Furthe
cannot disable interrupts on other processors.
of the
level
y
priorit
the
affect
not
ority level of one processor does
y
priorit
upt
interr
s,
system
or
rocess
multip
in
other processors. Thus,

d resources.
levels cannot be used to synchronize access to sharetions
that run
excep
those
ing
Even the various urgent interrupts includ
re

at IPL 1F (hex) do so on only one processor. Thus, specialorsoftwa
.
action is required to stop other processors in a multiprocess system
81

Interrupts and Exceptions

Most exception service routines execute
at IPL 0 in response to

exception conditions caused by the softwar
e. A variatio

serious system failures, which raise IPL

n from this is
to the highest level (1F, hex) to

minimize processor interruption until the
problem is corrected. Exception service routines are usually coded
to avoid exceptions; however,
nested exceptions can occur.

Processor Interrupt Priority Levels (IPLs)
The processor has 31 interrupt priority levels
(IPLs), divided into 15
software levels (numbered, in hex, 01
to OF), and 16 hardware levels
(10 to 1F, hex). User applications, system
calls, and system services all
run at process level, which may be
thought of as IPL 0. Higher num-

bered interrupt levels have higher priority

; that is to say, any requests

at an interrupt level higher than the
proces

rupt immediately, but requests at a lower

sor’s current IPL will interor equal level are deferred.

Interrupt levels 01 through OF (hex) exist
entirely for use by software.
No device can request interrupts on those
levels, but software can
force an interrupt by executing MTPR
src,#SIRR (Software Interrupt
Request Register). Once a software interru
pt request is made, it will be
cleared by the hardware when the interru
pt is taken.

Interrupt levels 10 to 17 (hex) are for
use by devices and controllers,
including UNIBUS devices. UNIBUS levels
BR4 to BR7 correspond to
VAX-11 interrupt levels 14 to 17 (hex).
Interrupt levels 18 to 1F (hex) are for use
by urgent conditions, including the interval clock, serious errors, and
power fail.

Contrast Between Exceptions And Interr
upts
Generally exceptions and interrupts are
very similar. When either is
initiated, both the processor status (PSL)
and the program counter
(PC) are pushed onto a stack. Howev
er there are seven important
differences:
1.

An exception condition is caused by

the execution of the current
instruction, while an interrupt is cause
d by some activity in the

computing system that may be
independent of the current

instruction.
2.

An exception condition is usually
serviced in the context of the
process that produced the except

ion condition, while an interrupt

is serviced independently from the curren

The IPL of the processor is usually not

tly running process.

changed when the proces-

sor initiates an exception, while the
IPL is always raised when an
interrupt is initiated.

Iinterrupts and Exceptions

Exception service routines usually execute on a per-process
stack, while interrupt service routines normally execute on a perCPU stack.

Enabled exceptions are initiated immediately no matter what the
processor IPL is, while interrupts are held off until the processor
IPL drops below the IPL of the requesting interrupt.
Most exceptions cannot be disabled. However, if an exception-

causing event occurs while that exception is disabled, no exception is initiated for that event even when enabled subsequently.
This includes overflow, which is the only exception whose occurrence is indicated by a condition code (V). If an interrupt condition
occurs while overflow is disabled, or the processor is at the same

or higher IPL, the condition will eventually initiate an interrupt
when the proper enabling conditions are met if the condition is
still present.

The previous mode field in the PSL is always set to kernel on an
interrupt, but on an exception it indicates the mode of the exception.

INTERRUPTS

The processor services interrupt requests between instructions. The
processor also services interrupt requests at well-defined points during the execution of long, iterative instructions such as the string
instructions. For these instructions, in order to avoid saving additional
instruction state in memory, interrupts are initiated when the instruction state can be completely contained in the registers, PSL, and PC.
N Ok~

The following events cause interrupts:

Device completion (IPL 10-17 hex)
Device error (IPL 10-17 hex)
Device alert (IPL 10-17 hex)

Device memory error (IPL 10-17 hex)

Console terminal transmit and receive (IPL 14 hex)
Interval timer (IPL 18 hex)

Recovered memory or bus or processor errors (implementationspecific, IPL 18 to 1D hex). The VAX-11/780 processor interrupts
at 1B on memory errors.

Unrecovered memory or bus or processor errors (implementa-

tion-specific, IPL 18 to 1D hex)
Power fail (IPL 1E hex)
10.
11.

Software interrupt invoked by MTPR #SIRR (IPL 01 to OF hex)
AST delivery when REI restores a PSL with IS clear and mode
greater than or equal to ASTLVL.
83

Interrupts and Exceptions

Each device controller has a separate set of interrupt vector locations
in the system control block (SCB), thus eliminating the need to poll

controllers in order to determine which controller originated the inter-

rupt. The vector address for each controller is fixed by hardware.

In order to reduce interrupt overhead, no memory mapping information is changed when an interrupt occurs. Thus the instructions, data,
and contents of the interrupt vector for an interrupt service routine
must be in the system address space or present in every process at

the same address.

Urgent Interrupts—Levels 18-1F (Hex)
The processor provides eight priority levels for use by urgent

conditions including serious errors (e.g., machine check) and power
fail. Interrupts on these levels are initiated by the processor upon
detection of certain conditions. Some of these conditions are not interrupts. For example, Machine Check is usually an exception but it runs
at a high priority level on the interrupt stack.

Interrupt level 1E (hex) is reserved for power fail. Interrupt level 1F
(hex) is reserved for those exceptions that must lock out all processing
until handled. This includes the hardware and software “disasters”
(machine check and kernel stack not valid). It might also be used to

allow a kernel mode debugger to gain control on any condition.

Device Interrupts—Levels 10-17 (Hex)
The processor provides eight priority levels for use by peripheral de-

vices. Any given implementation may or may not implement all eight

levels of interrupts. The minimal implementation is levels 14-17 (hex)
that correspond to the UNIBUS levels BR4 to BR7 if the system has a

UNIBUS.

Software-Generated Interrupts—Levels 01-0F (Hex)
The processor provides 15 priority interrupt levels for use by software.

Software Interrupt Summary Register
Pending software interrupts are recorded in the Software Interrupt
Summary Register (SISR). The SISR contains 1’s in the bit positions

correponding to levels on which software interrupts are pending. All

such levels, of course, must be lower than the current processor IPL,

or the processor would have taken the requested interrupt. Figure 5-1
illustrates the software interrupt summary register.

16 15

PENDING SOFTWARE INTERRUPTS

MBZ

Figure 5-1

F,E,DC/BA98,7,6543,2]

NwZlo

Interripts and Exceptions

Software Interrupt Summary Register (Read/Write)

At bootstrap time, the contents of SISR are cleared. The mechanism
for accessing itis:

MFPR #SISR,dst

Reads the software interrupt summary
register.

MTPR src,#SISR

Loads it, but this is not the normal way of
making software interrupt requests. It is
useful for clearing the software interrupt
system and for reloading its state after a
power fail, for example.

Software Interrupt Request Register
The software interrupt request register (SIRR) is a write-only four-bit
privileged register used for making software interrupt requests. Figure
5-2 illustrates the software interrupt request register.
3

IGNORED

Figure 5-2

REQUEST

Software Interrupt Request Register (Write Only)

Executing MTPR src,#SIRR requests an interrupt at the level specified
by src<3:0>. Once a software interrupt request is made, it will be
cleared by the hardware when the interrupt is taken. If src<3:0> is
greater than the current IPL, the interrupt occurs before execution of
the following instruction. If src<3:0> is less than or equal to the current IPL, the interrupt will be deferred until the IPL is lowered to less
than src<3:0>, with no higher interrupt level pending. This lowering of
IPL is by either REI or by MTPR x,#IPL. If src<3:0> is 0, no interrupt
will occur or be requested.

Note that no indication is given if there is already a request at the
selected level. Therefore, the service routine must NOT assume that
there is a one-to-one correspondence of interrupts generated and
requests made. A valid protocol for generating such a correspondence is:
85

Interrupts and Exceptions

The requester uses INSQUE to place a control block describing
the request onto a queue for the service routine.

The requester uses MTPR src,#SIRR to request an interrupt at the
appropriate level.

The service routine uses REMQUE to remove a control block from
the queue of service requests. If REMQUE returns failure (nothing
in the queue), the service routine exits with REI.

If REMQUE returns success (an item was removed from the
queue), the service routine performs the service and returns to
step 3 to look for other requests.

Interrupt Priority Level Register
Writing to the IPL with the MTPR instruction will load the processor
priority field in the Program Status Longword (PSL), that is,
PSL<20:16> is loaded from IPL<4:0>. Reading from IPL with the
MFPR instruction will read the processor priority field from the PSL.

On writing IPL, bits <31:5> are ignored, and on reading IPL, bits

<31:5> are returned zero. Figure 5-3 illustrates the interrupt priority

level register.

IGNORED; RETURNS O

Figure 5-3

PSLL20: 16>

Interrupt Priority Level Register (Read/Write)

At bootstrap time, IPL
is initialized to 31 (1F, hex).
Interrupt service routines must follow the discipline of not lowering IPL
below their initial level. If they do, an interrupt at an intermediate level

could cause the stack nesting to be improper. This would result in RE!
faulting. Actually, a service routine could lower the IPL if it ensured
that no intermediate levels could interrupt. However, this would result

in unreliable code.
Interrupt Example

As an example, assume the processor is running in response to an
interrupt at IPL5; it then sets IPL to 8, and then posts software requests
at IPL3, IPL7, and IPL9. Then a device interrupt arrives at IPL11 (hex).

Finally IPL is set back to IPL5. The sequence of execution is:

Interrupts and Exceptions

event

state af_ter

event

contents of

SISR

IPLin
PSL on

IPL (hex)

(hex)

stack

(initial)
MTPR #8,#IPL
MTPR #3,#SIRR

5
8
8

0
0
8

0
0
0

MTPR #7,#SIRR

MTPR #9, #SIRR interrupts to

0
8,0

device interrupts to

9,8,0

device service routine REI
IPL9 service routine REI

9
8

88
88

5,0

immediately

IPL3 service routine REI

8,0

MTPR #5,#IPL changes IPL to 5
and the request for 7 is

granted immediately

IPL7 service routine REI
initial IPL5 service routine

REIl back to IPLO and the

request for 3 is granted

SERIOUS SYSTEM FAILURES
Although serious system failures are exceptions, they are discussed
here rather than in the Architecture Handbook because they are not

linked to user software, but rather are processed by privileged software.

Kernel Stack Not Valid Abort

Kernel stack not valid abort is an exception that indicates that the
kernel stack was not valid while the processor was pushing information onto the kernel stack during the initiation of an exception or interrupt. Usually this is an indication of a stack overflow or other executive
software error. The attempted exception is transformed into an abort
that uses the interrupt stack. No extra information is pushed on the
interrupt stack in addition to PSL and PC. IPL is raised to 1F (hex).
Software may abort the process without aborting the system. However, because of the lost information, the process cannot be
continued. If the kernel stack is not valid during the normal execution
of an instruction (inciuding CHMK or REi), the normai memory rman-

agement fault is initiated. If the exception vector <1:0> for Kernel
Stack Not Valid is 0 or 3, the behavior of the processor is UNDEFINED.
87

Interrupts and Exceptions

Interrupt Stack Not Valid Halt
An interrupt stack not valid halt is an exception that indicates that the
interrupt stack was not valid or that a memory error occurred while the
processor was pushing information onto the interrupt stack during the
initiation of an exception or interrupt. No further interrupt requests are

acknowledged on this processor. The processor leaves the PC, the
PSL, and the reason for the halt in registers so that it is available to a
debugger, the normal bootstrap routine, or an optional watchdog
bootstrap routine. A watchdog bootstrap can cause the processor to
leave the halted state.

Machine Check Exception
A machine check exception indicates that the processor detected an
internal error in itself. As usual for exceptions, this exception is taken
independently of IPL. IPL is raised to 1F (hex). Implementation-specif-

ic information is pushed on the stack as longwords. The processor
specifies the number of bytes pushed by placing the number of bytes
pushed as the last longword pushed (0 if none, 4 if one,...). This count

excludes the PC, PSL, and count longwords. Software can decide, on
the basis of the information presented, whether to abort the current
process if the machine check came from the process. Machine check
includes uncorrected bus and memory errors anywhere, and any other processor-detected errors. Some processor errors cannot ensure

the state of the machine at all. For such errors, the state will be preserved on a “best effort” basis. If the exception vector <1:0> for
machine check is 0 or 3, the behavior of the processor is UNDEFINED.

SYSTEM CONTROL BLOCK (SCB)
The System Control Block is a page containing the vectors by which
exceptions and interrupts are dispatched to the appropriate service
routines.

System Control Block Base (SCBB)
The SCBB is a privileged register containing the physical address of
the System Control Block, which must be page-aligned. Figure 5-4
illustrates the system control block base register.

31 3029
MBZ

9
sCBB

Figure 5-4

0
MBZ

System Control Block Base Register (Read-Only)
88

Interrupts and Exceptions

At bootstrap time, the contents of SCBB are UNPREDICTABLE. SCBB

must specify a valid address in physical memory or the processor

operation is UNDEFINED.
Vectors

A vector is a longword in the SCB that is examined by the processor
when an exception or interrupt occurs, to determine how to service the
event.

Separate vectors are defined for each interrupting device controller
and each class of exception. Each vector is interpreted as follows by
the hardware. The contents of bits <1:0> can be interpreted as:
0
1

Service this event on the kernel stack unless already running on
the interrupt stack, in which case service on the interrupt stack.
Service this event on the interrupt stack. If this event is an exception, the IPL is raised to 1F (hex).

Service this event in writable control store, passing bits <15:2> to
the installation-specific microcode there. If writable control store
does not exist or is not loaded, the operation is UNDEFINED. On
the VAX-11/780 processor, the operation in this case is a HALT.

Operation UNDEFINED. Reserved to DIGITAL. On the VAX11/780 processor, the operation is a HALT.

For codes 0 and 1, bits <31:2> contain the virtual address of the
service routine, which must begin on a longword boundary and will
ordinarily be in the system space. CHMx is serviced on the stack
selected by the new mode. Bits <1:0> in the CHMx vectors must be
zero or the operation is UNDEFINED. On the VAX-11/780 processor,
these bits are ignored in the CHMXx vectors.

System Control Block (exception and interrupt vectors)
Vector

Name

Notes

Unused
Machine Check

Reserved to DIGITAL.
Processor-and error-specific in-

(hex)

00
04

formation is pushed on the stack,
if possible. Restartability is

processor-specific. Vector<1:0>
must be 1 for meaningful operation.
IPL is raised to 1F (hex). The
number of bytes of parameters is

pushed on the siack and is impiementation-dependent. This vector
causes an abort/fault/trap.
89

Interrupts and Exceptions

Vector

Name

Notes

Kernel Stack

Vector<1:0> must be 1 for mean-

Not Valid

ingful operation. IPL is raised to

(hex)
08

1F (hex). This vector causes an
abort. There are zero parameters.

Power Fail

IPL is raised to 1E (hex). This

vector causes an interrupt. There
are zero parameters.

Reserved/

Opcodes reserved to DIGITAL and

Privileged

privileged instructions. This

Instruction

vector causes a fault. There are
zero parameters.

Customer

XFC instruction. This vector causes

Reserved

a fault. There are zero parameters.

Instruction

Reserved

This vector causes a fault/abort.

Operand

There are zero parameters.

Reserved Ad-

This vector causes a fault. There

dressing Mode

are zero parameters. For greater

detail refer to the Architecture
Handbook.

Access

Virtual address, etc., causing

Control

fault is pushed onto stack. This

Violation

vector results in a fault. There
are two parameters.

Translation

Virtual address, etc., causing

Not Valid

fault is pushed onto stack. This
vector results in a fauit. There
are two parameters.

Trace Pending

(TP)

This vector results in a fault.
There are zero parameters. For
greater detail refer to the

Architecture Handbook.

Interrupts and Exceptions

Vector

Name

Notes

Breakpoint

This vector results in a fault.
There are two parameters. For

(hex)

Instruction

greater detail refer to the
Architecture Handbook.
30

Compatibility

A type code is pushed onto the
stack. This vector results in a
fault/abort. There is one parameter.

Arithmetic

A type code is pushed onto the
stack. This vector results in a
trap. There is one parameter.

38-3C

Unused

Reserved to DIGITAL.

CHMK

The operand word is sign-extended
and pushed onto the stack. Vector
<1:0> MBZ. This vector results in

atrap. There is one parameter.
44

CHME

The operand word is sign-extended
and pushed onto the stack. Vector
<4:0> MBZ. This vector results in
atrap. There is one parameter.

CHMS

The operand word is sign-extended

and pushed onto the stack. Vector
<1:0> MBZ. This vector results
in atrap. There is one parameter.
4C

CHMU

The operand word is sign-extended

and pushed onto the stack. Vector
<1:0> MBZ. This vector results
in a trap. There is one parameter.
50-80

Unused

Reserved to DIGITAL.

Software

This vector results in an inter-

Level 1

rupt. There are zero parameters.

Interrupts and Exceptions

Vector

Name

Notes

Software

Ordinarily used for AST delivery.

Level 2

This vector results in an inter-

(hex)
88

rupt. There are zero parameters.

8C-BC

Software

This vector results in an inter-

Levels 3-F

rupt. There are zero parameters.

interval

IPL is 18 (hex). This vector

Timer

results in an interrupt. There are
zero parameters.

C4-F4
F8

Unused
Console

Terminal
Receive
FC

Console Ter-

minal

100-1FC

Reserved to DIGITAL.
IPL is 14 (hex). This vector

results in an interrupt. There are
zero parameters.
IPL is 14 (hex). This vector

results in an interrupt. There are

Transmit

zero parameters.

Device

This vector resuits in an

Vectors

interrupt. There are zero
parameters.

In the VAX-11/780 processor, only hardware levels 14 to 17 (hex) are

available to a NEXUS external to the CPU, and there is a limit of 16

such NEXUSs. A NEXUS is a connection on the SBI, which is the
internal interconnection structure. The NEXUS vectors are assigned

as follows:

100-13C IPL 14 (hex) NEXUS 0-15
140-17C IPL 15 (hex) NEXUS 0-15
180-1BC IPL 16 (hex) NEXUS 0-15

1C0-1FC IPL 17 (hex) NEXUS 0-15

STACKS

At any time, the processor is either in a process context (IS=0) in one

of four modes (kernel, executive, supervisor, user), or in the systemwide interrupt service context (IS=1) that operates with kernel privileges. There is a stack pointer associated with each of these five

states, and any time the processor changes from one of these states to

another, SP (R14) is stored in the process context stack pointer for the

interrupts and Exceptions

old state and loaded from that for the new state. The process context

stack pointers (KSP=kernel, ESP =executive, SSP=supervisor, USP=

user) are allocated in the PCB, although some hardware implementations may keep them in privileged registers. The interrupt stack pointer (ISP} is in a privileged register.
Stack Residency

The USER, SUPER, and EXEC stacks do not need to be resident. The

kernel can bring in or allocate process stack pages as address translation not valid faults occur. However, the kernel stack for the current
process and the interrupt stack (which is process-independent) must

be resident and accessible. Translation not valid and access control

violation faults occurring on references to either of these stacks are
regarded as serious system failures, from which recovery is not possible.

If either of these faults occurs on a reference to the kernel stack, the
processor aborts the current sequence and initiates kernel stack not
valid abort on hardware level 1F (hex). If either of these faults occurs
on a reference to the interrupt stack, the processor halts. Note that this
does not mean that every possible reference is checked, but rather
that the processor will not loop on these conditions.

It is not necessary that the kernel stack for processes other than the
current one be resident, but it must be resident before a process is
selected to run by the software’s process dispatcher. Further, any
mechanism that uses Translation Not Valid or Access Control
Violation faults to gather process statistics, for instance, must exercise
care not to invalidate kernel stack pages.
Stack Alignment

Except on CALLXx instructions, the hardware makes no attempt to align
the stacks. For best performance on all processors, the software
should align the stack on a longword boundary and allocate the stack
in longword increments. The following instructions are recommended
for pushing bytes and words on the stack and popping them off in
order to keep it longword-aligned:
e convert byte to long (CVTBL)
e convert long to byte (CVTLB)
e convert long to word (CVTLW)
e convert word to long (CVTWL)

e move zero-extended byte to long (MOVZBL)
e move zero-extended word to long (MOVZWL)

Interrupts and Exceptions

Stack Status Bits
The interrupt stack bit (IS) and current mode bits in the privileged

Processor Status Longword (PSL) specify which of the five stack
pointers is currently in use as folows:

MODE

ISP

KSP

ESP

SSP

USP
The processor does not allow current mode to be nonzero when I1IS=1.
This is achieved by clearing the mode bits when taking an interrupt or
exception, and by causing reserved operand fault if REl attempts to

load a PSL in which both IS and mode are nonzero.

The stack to be used for an interrupt or exception is selected by the
current PSL<IS> and bits <1:0> of the vector for the event as follows:

VECTOR<1:0>
00

O | KSP | 1SP
PSLLIS>
1 | ISP | ISP

Values 10 (binary) and 11 (binary) of the vector<1:0> are used for

other purposes.

Accessing Stack Registers

The processor implements five privileged registers to allow access to
each stack pointer. These registers always access the specified pointer even for the current mode. If the process stack pointers are implemented as registers, then these instructions are the only method for
accessing the stack pointers of the current process. If the process
stack pointers are kept in the PCB, the MTPR and MFPR of these

registers access the PCB. The register numbers were chosen to be the
same as PSL <26:24>. The previous stack pointer is the same as PSL
<23:22> unless PSL <IS> is set. Note that interrupt service routines

invoked at a priority higher than the lowest one used for context
switching must not reference the process stack pointers. At bootstrap
time, the contents of all stack pointers are UNPREDICTABLE. Figure

5-5 illustrates the process stack pointer.

Interrupts and Exceptions

VIRTUAL ADDRESS OF TOP OF STACK

Figure 5-5 Process Stack Pointer Implemented As Read/Write
Register

KSP =0
ESP =1
sSSP =2
USP =3
ISP =4

Kernel Stack Pointer
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer

SERIALIZATION OF EXCEPTIONS AND INTERRUPTIONS

wbd A

The sequence in which recognition of simultaneously occurring interrupts and exceptions takes place is indicated in the following list.
Machine check exception
Arithmetic exceptions

*Console halt or higher priority interrupt
Trace fault (only one per instruction)

Start instruction execution or restart suspended instruction

*the order in which console halt and interrupt recognition occur is not
dictated by the VAX architecture (i.e., some future VAX machines may
not take these in the same order as the VAX-11/780, which takes
console halts before interrupts).
~

NOTE

The VAX architecture allows certain instructions to
be suspended at well-defined intermediate points in
their execution in order to take memory manage-

ment faults, console halts, or interrupts. In this case,
the hardware uses PSL<TP> and PLS<T> to ensure that no additional trace faults occur when the
suspended instruction is resumed.

As an example, if an instruction is started with T=1, it gets an

arithmetic trap and an interrupt request is recognized. The following
sequence occurs:

Theinstruction finishes, storing all its results.
95

Interrupts and Exceptions

The overflow trap sequence is initiate
d, pushing the PC and PSL
(with TP=1), loading a new PC
from the vector, and creating a

new PSL.

The interrupt sequence is initiated,

pushing the PC and PSL ap-

propriate to the trap service routin
e, loading

vector, and creating a new PSL.

a new PC from the

If a higher priority interrupt is notice
d, the first instruction of the
interrupt service routine is not execu
ted. Instead, the PC and PSL

appropriate to that routine are

saved as part of initiating the

interrupt. The original interrupt
executed when the higher priorit

new

service routine will then be

y routine terminates via REI.

The interrupt service routine runs and

exits with REI.

The trap service routine runs and exits
having TP=1.

with REI, which finds a PSL

The trace occurs, again pushing PC
and PSL, but this time with

TP=0.

Trace service routine runs and exits with

REI.

INITIATE EXCEPTION OR INTERRUPT
The following pseudo algol descr
ibes the sequence of

events which

occurs on initiation of excep
tions and interrupts. If a higher
priority

interrupt condition occurs after the
start of this sequence, the interrupt
will not be taken until the sequence
completes. On the VAX-11/780, all
UNDEFINEDs shown in the pseudo
algol are HALTSs.
if vector < SCB[vector];
lget correct vector
if vector<1:0> EQLU 3 then {UND
EFINED;
if vector<1:0> EQLU 0 and {machine-c
heck or

kernel-stack-not-valid} then {UNDE
FINED;
if vector<1:0> NEQU 0 and {CHMXx|}
then {UNDEFINED};
if vector<1:0> EQLU 2 then

begin
if fwritable control store exists and

then {enter writable control store}

is loaded}

else [UNDEFINED;
end;

if PSL<IS> EQLU 0 then

begin

Iswitch stacks

PSL<current-mode>-SP <«SP; Isave
if vector<1:0> EQLU 1 then

SP « ISP;
else

old SP

Interrupts and Exceptions

SP <« new-mode-SP; lkernel-SP unless CHMx
end;

—(SP) < PSL;

lon a fault or abort, the saved

I condition codes are UNPREDICTABLE
las backed up, if necessary
—(SP) < PC;
{push parameters if any};

PSL<CM,TP,FPD,DV,FU,IV,T,N,Z,V,C> <« 0;
if {interrupt} then

!clean out PSL

tkernel mode

PSL<previous-mode> <« 0;

else

PSL<previous-mode> « PSL<current-mode>;

PSL<current-mode> <new-mode; !kernel-mode unless CHMXx
if {interrupt} then

Iset new IPL

PSL<IPL> <« new-IPL

else

if vector<1:0> EQLU 1 then

PSL<IPL> «31;

I11F (hex)

if vector<1:0> EQLU 1then PSL<IS> «1; otherwise keep old IS
llongword-aligned

PC <« vector<31:2> ' 0<1:0>;
{enable interruptsi;

Condition Codes (if vector<1:0> code is 0 or 1):
N < O0;
Z<0;

V «0;

C<«0;
Exceptions:

interrupt stack not valid
kernel stack not valid
Description:

The handling is determined by the contents of a longword vector in the
system control block that is indexed by the exception of the interrupt
being processed. If the processor is not executing on the interrupt
stack, then the current stack pointer is saved and the new stack pointer is fetched. The old PSL is pushed onto the new stack. The PC is

backed up (unless this is an interrupt between instructions, a trace
pending fault, or a trap) and is pushed onto the new stack. The PSL is
initialized to a canonical state. IPL is changed if this is an interrupt or if
it is an exception with vector<1:0> code 1. Any parameters are

pushed. Except for interrupts, the previous mode in the new PSL is set
to the old value of the current mode. Finally, the PC is changed to point
to the longword indicated by the vector<31:2>.
97

Interrupts and Exceptions

Notes:
1.

Interrupts are disabled during this
sequence.
If the vector<1:0> code is invalid, the behavi
or is UNDEFINED.
On a fauit or abort or interrupt, the saved
condition codes are
UNPREDICTABLE. On an abort or fault or
interrupt that sets FPD,
the general registers except PC, SP and
(unless modified by the
instruction) FP are UNPREDICTABLE unless
the instruction de-

scription specifies a setting. On a Kernel
Stack Not Valid abort,

both SP and FP are UNPREDICTABLE. In
this case, UNPREDICTABLE means unspecified; upon REI the
instruction behavior and
results are predictable. This implies that
processes stopped with
FPD set cannot be resumed on proces
sors of a different type or
engineering change level.

If the processor gets an access control violatio
n or a translation

not valid condition while attempting to push
information on the

kernel stack, a kernel stack not valid abort is
initiated and IPL is
changed to 1F (hex). The additional information,
if any, associated
with the original exception is lost. However
, PSL and PC are
pushed on the interrupt stack with the same

been pushed on the kernel stack.

values as would have

If the processor gets an access control violatio
n or a translation

not valid condition while attempting to push
information on the

interrupt stack, the processor is halted and
only the state of ISP,
PC, and PSL is ensured to be correct for subsequ
ent analysis.
The PSL and PC have the values that would
have been pushed on
the interrupt stack.

As usual for faults, if the processor gets an
Access Violation or
Translation Not Valid fault during the executi
on of a CHMXx in-

struction, it saves PC, PSL, and leaves SP as
it was at the beginning of the instruction except for any pushes
onto the kernel

stack.

The value of PSL<TP> that is saved on the stack
fault

clear

trace

clear

interrupt

is as follows:

from PSL<TP> (if after
traps, before trace) clear

(otherwise)

abort

from PSL<TP>

trap

from PSL<TP>

CHMx

from PSL<TP>

Interrupts and Exceptions

BPT, XFC

clear

reserved instruction

clear

The value of PC that is saved on the stack points to the following:
fault

instruction faulting

trace

next instruction to execute

instruction interrupted or
next instruction to execute

interrupt

instruction aborting or detecting Kernel Stack Not Valid (not ensured on machine

abort

check)
trap

next instruction to execute

CHMx

next instruction to execute

BPT, XFC

BPT, XFC instruction

first byte of the reserved in-

reserved instruction

struction

The non-interrupt stack pointers may be fetched and stored by
hardware in either privileged registers or in their allocated slots in
the PCB. Only LDPCTX and SVPCTX always fetch and store in the
PCB (see Chapter 7). MFPR and MTPR always fetch and store the
pointers whether in registers or the PCB.

EO20BEA vax wreo

ilI

00}

i Qi

CHAPTER 6

MEMORY MANAGEMENT

conthe hardware and software thatipro
Memory management describesical
mult
a
in
ally,
Typic
ry.
trol the allocation and use of physessesmemo
ry
memo
cal
physi
in
e
resid
may
gramming system, several proc re that one process will not affect
to ensu
at the same time. Therefore, atin
prog system, memory protection is(priv
oper
the
other processes or
hierarchical iINTRODUCTION

ware reliability, four
vided. To further improve softcontr
from
memory access. They are, user.
lege) modes are provided tokernel, olexecu
and
,
visor
super
tive,
most to least privileged:
individual page level, where a page may

Protection is specified at the
te for each of the four access
be inaccessible, read-only, or read/wri
r privileged mode is also
lesse
a
to
modes. Any location accessiblemode
hermore, for each access
Furt
s.
leged
accessible to all more privi
.

mode, any location that s writable is also readable

s are
uted by the CPU, virtual addresse
While an image is being execthes
ss
acce
to
used
be
can
s
esse
addr
generated. However, before bee tran
s.
esse
addr
ical
phys
into
ed
slat
instructions and data, they must
rmainfo
g
pin
maintains tables of map virtual page
Memory management software
of where each 512-byte
k
trac
keep
that
tion (page tables)
The CPU utilizes this mappings.informais located in physical memory.addr
esses to physical addresse
tion when it translates virtual

ides both the
ment is the scheme that prov
Therefore, memory manage
of the VAXms
anis
ory mapping mech
memory protection and mem
gned and
desi
been
has
eme
ment sch
11/780. The memory manage
:
goals
wing
follo
oo b~

implemented to achieve the

Provide a large address space for instructions and data.
Allow data structures up to one gigabyte.

Provide convenient and efficient sharing of instructions
Contribute to software reliability.
101

and data.

Memory Managemen

A virtual memory syst
em is used to provide
a large address space,
while allowing programs
to run on small memory
size hardware configurations. Programs
are executed in an exec
ution environment
termed a process. The
software operating syst
em uses the mechanisms described in this
chapter to provide each
process with a 4billion-by

te virtual address space.

The virtual address space
is divided into two equal addr
ess spaces,
the process address spac
e and the system address
space. The system
address space is common
for all processes and is
not context
switched

. The operating system
is located in system addr
ess space
and is implemented as a
series of callable procedur
es. Thus, all of the
syst
em code is available to
all other system and user
code

s via a
simple CALL. Process
address space is Separate
for each process.
However, several processe
s may have access to the
same page, thus
providing controlled shari
ng.

VIRTUAL ADDRESS SPA
CE
The address space seen
by the programmer is a linea
r array of
4,294,967,296 bytes. This
results from the fact that
a virtual address is
32 bits in length. The
virtual address space
is broken into 512-byte
units called
protection.

pages. The page is the
basic

unit of both relocation

This virtual address Spac

and

e is too large to be containe

available main memory

d in any presently

. Therefore memory man

agement provides the
mapping mechanism
to map the active part
of the virtual address
space to
the available physical
address spac

e. Memory manage
men

also provides Page prot

ection between processe

s. The oper

ating system controls the mem
ory management tabl
es that map virtual addres

ses into physical mem
ory addresses. The inac
tive but used parts
of the virtual address
Space are mapped into
external storage media
via the Operating syst
em.

The virtual address space
is divided into two parts. The
lower half,
known as “per-process space
,” is distinct for each process
running on
the system. The upper half,
known as “system space”, is
shared by all
processes. Furthermore,
the per-process virtual
address space is di-

vided into two equal parts
, program space (P0 spac
e) and control
spac
e (P1 space). Virtual addr

ess spaceis illustrated in

102

Figure 6-1.

Memory Management
VIRTUAL ADDRESS
(32 BITS)

~ 0000 0000

VIRTUAL ADDRESS
SPACE

PO REGION
(PROGRAM)

GROWTH DIRECTION

3FFF FFFF

L By ol g
SEGHC

4000 0000

PER

PRO

SPACCEESS

GROWTH DIRECTION
P1

_7FFF_FFFE_

REGION

[CONTROL)

8000 0000

SYSTEM REGION

GROWTH DIRECTION

_BFFF_FFFF

C000 0000

SYSTEM

SPACE

RESERVED

EFFE

FFFF

Figure 6-1

Virtual Address Space

Process Space

The lower half of virtual address space is termed “process space.”
Each process has a separate address translation map for per-process

space, so the per-process spaces of all processes are completely
disjoint. The address map for per-process space is context-switched

when the process running on the system is changed.
System Space

The upper half of virtual address space is termed “system space.” All

processes use the same address translation map for system space, so

system space is shared among all processes. The address map for
system space is not context-switched.
Page Protection

Independently of its location in the virtual address space, a page may

be protected according to its use. Thus, even though ali of the system
space is shared, in that the program may generate any address, the
program may be prevented from modifying or even accessing por103

Memory Management

tions of it. A program may also be prevented from accessing or
modifying portions of per-process space.
For example, in system space, scheduling queues are highly protected, whereas library routines may be executable by code of any privi-

lege. Similarly, per-process accounting information may be in perprocess space, but highly protected, while normal user code in perprocess space is executable at low privilege.

VIRTUAL ADDRESS
in order to reference each instruction and operand in memory, the
processor generates a 32-bit virtual address. As the process

executes,

the system translates virtual addresses to physical addresses. The
virtual address format is illustrated in Figure 6-2.

VIRTUAL ADDRESS
SPACE

VIRTUAL ADDRESS

IVIRTUAL PAGE NO. [OEQEET]
"

VIRTUAL PAGE \\\\\\\\\\\\\\ )

Figure 6-2

Virtual Address

{

Bits <31:9> Virtual Page Number
The virtual page number field specifies the virtual page to be
referenced. There are 8,388,608 pages of 512 bytes each in the virtual

address space. When bit 31 is set, the address is system virtual. Bit 30

is used in conjunction with process virtual addresses to distinguish
between the program and control regions. When bit 30 is set, the

control region is referenced, and when it is clear, the program region

is referenced.

104

Memory Management

Bits<8:0> Byte

The byte number field specifies the byte address within the page. A
page contains 512 bytes.

Virtual Address Space Layout

Access to each of the three regions (PO, P1, System) is controlled by a
length register (POLR, P1LR, SLR). Within the limits set by the length
registers, the access is controlled by a page table that specifies the
validity, access requirements, and location of each page in the region.
ADDRESS TRANSLATION

The action of translating a virtual address to a physical address is
governed by the setting of the Memory Mapping Enable (MME) bit.
When MME is 0, the low order bits of the virtual address are the
physical address and there is no page protection. The number of bits
is implementation-dependent. This section describes the address
translation process when MME is 1.

The address translation routine is presented with a virtual address, an
intended access (read or write) and a mode against which to check
that access. If the access is allowed and the address maps without
faulting, the output of this routine is the physical address corresponding to the specified virtual address.

The mode that is used is normally the current mode field of the PSL,
but per-process page table entry references use kernel mode.
The intended access is read if the operation to be performed is a read.
The intended access is write if the operation to be performed is a write.
If, however, the operation to be performed is a modify (i.e., read followed by write) the intended access for the read portion is specified as
a write.

Page Table Entry (PTE)

All virtual addresses are translated to physical addresses by means of
a Page Table Entry (PTE). The page table entry is described in Figure
6-3.

31 30

272625 24

PROT

M{O|OWN|

32221

PFN

Figure 6-3

Page Table Entry

105

Memory Management

Bit<31> Valid bit
The operating system uses the V bit to indicate whether the corre

sponding page is part of the process working set (i.e., the set of physi-

cal pages currently being used by the process). If the V
bit = 0 (not
valid), the page is not in the working set. The hardware then
issues a
Translation Not Valid fault (i.e., “page fault”’) during address
transla-

tion. The pager retrieves this page and brings it into physical
memory
allowing continued execution of the process image. The V bit
governs
the validity of the M bit and PFN field.

Bits <30:27> Protection code

The protection code specifies read-write access to each page. This
field is explained more fully under the ACCESS CONTROL section of

this chapter. This field is always valid and is used by the hardware

even when V=0,

Bit<26> Modify bit
Set if page has already been recorded as modified. M=0 if page has
not been

recorded

modified.

Used

by hardware only if V=1.

Hardware sets this bit on a valid, access-allowed memory access as-

sociated with a modify or write access, and optionally on a PROBEW
or implied probe-write. If a write or modify reference crosses a page

boundary and one page faults, it is UNPREDICTABLE whether the
page table entry M bit for the other page is set before the fault. It is
UNPREDICTABLE whether the modification of a process PTE M bit
causes modification of the system PTE that maps that process page
table. Note that the update of the M bit is not interlocked in a multiprocessor system.

Bit<25> Reserved to DIGITAL
This bit is reserved to DIGITAL and must be zero. The hardware does
not necessarily test that this bit is zero because the PTE is established

only by privileged software.

Bits <24,23> Reserved
Reserved for software use as the access mode of the owner of the

page (i.e., the mode allowed to alter the page); not examined or altered by hardware.

Bits <22,21> Reserved to DIGITAL
These bits are reserved to DIGITAL and must be zero. The hardware

does not necessarily test that these are zero because the PTE is
established only by privileged software.

106

Memory Management

Bits <20:0> Page Frame Number (PFN)
The upper 21 bits of the physical address of the base of the page.
Used by hardware only if V=1.

Software symbols are defined for the described fields using PTES as
the prefix.

ACCESS CONTROL

Access control is the function of validating whether a particular type of
memory access is to be allowed to a particular page. Every page has
associated with it a protection code that specifies for each mode
whether or not read or write references are allowed. Additionally, each
address is checked to make certain that it lies within the PO, P1, or
system region.
Mode

There are four hierarchically ordered modes in the processor. The
modes, in the order of most to least privileged, are:
Kernel. Used by the kernel of the operating system for page man0
agement, scheduling, and I/O drivers.

1
2
3

Executive. Used for many of the operating system service calls

including the record management system.

Supervisor. Used for such services as command interpretation.
User. Used for user level code, utilities, compilers, debuggers,
etc.

The mode at which the processor is currently running is stored in the
Current Mode field of the Processor Status Longword (PSL).
Protection Code

Associated with each page is a protection code (located within the

page table entry for that page) that describes the accessibility of the

page for each mode. The protection codes available allow choice of

protection for each access level within the following limits:
1. Each level’s access can be read/write, read-only, or no access.
2. If any level has read access then all more privileged levels also
have read access.

If any level has write access then all more privileged levels also

have write access.

The protection code is encoded in a 4-bit field in the Page Table Entry
described in Table 6-1. Associated with each protection code is the
access status for each of the access modes. During address transiation, the protection code is the first field in the PTE that is checked.
107

Memory Management

Table 6-1

CODE
DECIMAL

Protection Codes

MNEMONIC

BINARY

0000

0001

0010

K
NA

E
-

S
-

]

COMMENT

UNPREDICTABLE

RESERVED

0011

0100

NOACCESS

RW ALL ACCESS

0101

0110

ERKW

0111

1000

sSw

RwW

1001

SREW

1010

SRKW

1011

1100

URSW

1101

UREW

1110

URKW

1111

- =NO access

K=Kernel

R=read only

E=Executive

RW =read/write

S=Supervisor
U=User

Software symbols are defined using PTE$K _as a prefix to the mne-

monics listed in Table 6-1.

This code was chosen to keep the complexity of hardware access
checking reasonable for implementations not using a table decoder.

The access is allowed if:

(CODE NEQU 0) AND
((CODE EQLU 4) OR (CM LSSU WM) OR (READ AND (CM LEQU RM)))

CM is current mode
RM is left two bits of code

WM is 1's complement of right two bits of code
Length Violation
Every virtual address is constrained to lie within one of the valid addressing regions (PO, P1, or System). The algorithm for making these

checks is a simple limit check. The formal notation for this check is:
108

Memory Management

case VAddr <31:30>
set

(0):

IPO region
if ZEXT (VAddr<29:9>) GEQU POLR
then (length violation);

(1):

IP1 region

if ZEXT (VAddr<29:9>) LSSU P1LR
then (length violation);

(2):

IS region
if ZEXT (VAddr<29:9>) GEQU SLR
then (length violation);

(3):

reserved region
(length violation);

Access Control Violation Fault
An access control fault occurs if the current mode of the PSL and the
protection field(s) for the page(s) about to be accessed indicate that

the access would be illegal. A fault of this type will occur if the address
causes a length violation to occur.

SYSTEM SPACE ADDRESS TRANSLATION

A virtual address with <31:30>=2 (i.e., binary 10) is an address in the

system virtual address space as illustrated in Figure 6-4.

313029

VIRTUAL PAGE NO. {VPN)

Figure 6-4

System Space Address

109

BYTE #

Memory Management

The system virtual address space is defined by the System

Page Table

(SPT), which is a vector of page table entries (PTEs). The system page

table is always located in physical address space. Therefore the

base
address of the SPT is a physical address and is located in the System

Base Register (SBR) described in Figure 6-5. The size of the SPT in
longwords, i.e., the number of PTEs, is contained in the System Length

Register (SLR) described in Figure 6-6. The SBR points to the first PTE
in the SPT. In turn, this PTE maps the first page of system virtual
space, i.e., virtual byte address 80000000 (hex).

31 3029

MBZ

PHYSICAL

Figure 6-5

LONGWORD ADDRESS

maz

System Base Register

22 21

mBZ

LENGTH OF SPT IN LONGWORDS

Figure 6-6

System Length Register

The virtual page number is contained in bits <29:9> of the virtual
address. Thus, there could be as many as 2?' pages in the system
region. (Typically the value is in the range of a few hundred to a few

thousand system pages.) A 22 bit length field is required to express
the values 0 through 22! inclusive. At bootstrap time, the content of
both registers is UNPREDICTABLE. The translation from system virtual address to physical address is illustrated in Figure 6-7.

Thus, the arithmetic necessary to generate a physical address from a
system region virtual address is:

SYS_PA = (SBR+SVA<29:9>*4)<20:0>'SVA<8:0> ISystem Region
NOTE

For all occurrences within this chapter, the parentheses indicate contents of, the angle brackets

indicate referenced

bits, and the apostrophe

indicates concatenation.
110

Memory Management

33 2

Hl2 ,

VIRTUAL
(SYSTEM
ADDRESS)

SVA:

EXTRACT

212

3,2

BYTE

2 :1 0

10 9

CHECK LENGTH
ADD

rPHYS BASE ADR OF SPT

SBR:

JEJ

YIELDS

PHYS ADR OF PTE

JB]

FETCH

]

PTE:

PEN

CHECK ACCESS :

3312

PHYS ADR OF DATA:
Figure 6-7

9ls

10,9

[

‘o|

1 O

System Virtual To Physical Translation

PROCESS SPACE ADDRESS TRANSLATION

The process virtual address space is split into two separately mapped
regions according to the sefting of bit 30 in the process virtual address. If bit 30 is 0, the PO region of the address space is selected, and
if bit 30 is 1, the P1 region is selected.

The PO region of the address space maps a virtually contiguous area

that begins at the smallest address (0) in the process virtual space and
grows in the direction of larger addresses. In contrast, the P1 region of
the address space maps a virtually contiguous area that begins at the
largest address (23'—1) in the process virtual space and grows in the
direction of smaller addresses.

Each region (PO and P1) of the process virtual space is described by a
virtually contiguous vector of page table entries. In contrast with the
system page table, which is located in physical address space, the two
process page tables are located in system virtual address space.

Thus, for process space, the address of a PTE is a virtual address in
system space, and the fetch of a PTE is simply a fetch of a longword
using a system virtual address.

111

Memory Management

There is a significant reason to address process
rather than physical space. A physically addres

page tables in virtual

sed process page table

that required more than a page of PTEs (i.e., that
mapped more than
64K bytes of process virtual space) would
require physically contiguous pages. Such a requirement would make
dynamic allocation of
process page table space very awkward.

A process space translation that causes a translat
usually cause one memory reference for a

ion buffer miss will

PTE. If the virtual address

of the page containing the process PTE is also

missing from the translation buffer, a second memory reference is require
d.
When a process page table entry is fetched

, a reference is made to

system space. This reference is made
as a kernel read. Thus, the
system page containing a process page
table is either “No Access”

(i.e., protection code zero) or will be accessi
ble (protection code nonzero). Similarly, a check is made against
the system page table length
register (SLR). Thus, the fetch of an entry
from a process page table

can result in access or length violation faults.

PO Space

The PO region of the address space is mapped

by the PO page table
(POPT) that is defined by the PO base registe
r (POBR) and the PO
length register (POLR). POBR contains
a virtual address in the system
half of virtual address space which is the
base address of the PO page
table. The PO base register is illustrated
in Figure 6-8. POLR contains
the size of the PO page table in longwords,
i.e., the number of page
table entries. The PO length register is
illustrated in Figure 6-9. The

page table entry addressed by the
PO base register maps the first
"page of the PO region of the virtual
address space, i.e., virtual byte

address 0.

31 30 29

2.1

SYSTEM VIRTUAL LONGWORD ADDRESS

Figure 6-8

2726
MBZ

PO Base Register

243020

IGN

MBZ

{MmBZ

LENGTH OF POPT IN

Figure 6-9

PO Length Register
112

LONGWORDS

Memory Management

The virtual page number is contained in bits <29:9> of the virtual
address. Thus, there could be as many as 2?' pages in the PO region. A

22-bit length field is required to express the values O through 221

inclusive. POLR<26:24> is ignored on MTPR and read back 0 on

MFPR. At bootstrap time, the content of both registers is UNPREDICTABLE. An attempt to load POBR with a value less than 2% results in a
reserved operand fault. The translation from PO virtual address to
physical address is illustrated in Figure 6-10.

33 2

(PROCESS VIRTUAL

ADDRESS)

|
EXTRACT

312

BYTE

2,2

10 9

PVA:

]

210

0
CHECK LENGTH
ADD

POBR:

[

SYS VIRT BASE ADR OF POPT

YIELDS

lg]

SYS VIRT ADR OF PTE

FETCH-REFERS TO SYSTEM SPACE
ADDRESS TRANSLATION SECTION
OF THIS CHAPTER

;

PTE:

m
2

Figure 6-10

v 0

PHYS ADR OF DATA:

PO Virtual To Physical Translation

Thus, the arithmetic necessary to generate a physical address from a
PO region virtual address is:

PVA_PTE=

PTE_PA=

(PVA<29:9>*4)+POBR

IPO Region

(SBR+PVA_PTE<29:9>*4)<20:0>'PVA_PTE<8:0>

PROC_PA= (PTE_PA)<20:0>'PVA<8:0>
113

Memory Management

P1 Space
The P1 region of the address space is mapped by the P1 page table
(P1PT) that is defined by the P1 base register (P1BR) and the P1
length register (P1LR). Because P1 space grows backwards, and because a consistent hardware interpretation of the base and length

registers was desired, P1BR and P1LR describe the portion of P1
space that is not accessible. P1BR contains a virtual address of what

would be the PTE for the first page P1, i.e., virtual byte address
40000000 (hex). The P1 base register is illustrated in Figure 6-11.
P1LR contains the number of nonexistent PTEs. The P1 length register

is illustrated in Figure 6-12.

Note that the address in P1BR is not necessarily an address in system
space, but all addresses of PTEs must be in system space.

21
VIRTUAL

Figure 6-11

31 30
I

LONGWORD

ADDRESS

P1 Base Register (Read/Write)

22 A
maz

MBZ

0
2¢2]-LENGTH OF PIPT IN LONGWORDS

Figure 6-12

P1 Length Register (Read/Write)

P1LR<31> is ignored on MTPR and reads back 0 on MFPR. At boot-

strap time, the content of both registers is UNPREDICTABLE. An at-

tempt to load P1BR with a value less than 23'—22% (7F800000, hex)
results in a reserved operand fault. The translation from P1 virtual

address to physical address is illustrated in Figure 6-13.

Thus, the arithmetic necessary to generate a physical address from a
P1 region virtual address is:

PVA_PTE=

PTE_PA=

(PVA<29:9>*4)+POBR

IP1 Region
(SBR+PVA_PTE<29:9>*4)<20:0>'PVA_PTE<8:0>

PROC_PA= (PTE_PA)<20:0>'PVA<8:0>
114

Memory Management
33 2

VIRTUAL
{PROCESS
ADDRESS)

PVA:

]

EXTRACT

212

312

BYTE

2110

9 8

10 9

CHECK LENGTH
ADD

PI1BR:

r SYS VIRT BASE ADR OF P1PT

[tfl

YIELDS

[i SYS VIRT ADR OF PTE

JEJ

FETCH-REFER TO SYSTEM SPACE
ADDRESS TRANSLATION SECTION
OF THIS CHAPTER

PTE:

22
1 0

]

IT[
— W

CHECK ACCESS

PHYS ADR OF DATA:

Figure 8-13

PFN

3 [2

i
oig
1

|o|

9'8

(=]

33
10

P1 Virtual To Physical Translation

MEMORY MANAGEMENT CONTROL

There are three additional privileged registers used to contro! the
memory management hardware. One register is used to enable and
disable memory management, the other two are used to clear the
hardware’s address transiation buffer when a page table entry is
changed.

Memory Management Enable

The map enable register, MAPEN, contains the value of 0 or 1 according to whether memory management is disabled or enabled respec-

tively. The map enable register is a privileged register and is illustrated
in Figure 6-14.

115

Memory Management

MBZ

Figure 6-14

Map Enable Register (Read/Write)

At bootstrap time, this register is initialized to 0.
When memory management is disabled, virtual
addresses are

mapped to physical addresses by ignoring their
high order bits. All

accesses are allowed in all modes and no modify

bit is maintained.

Translation Buffer

In order to save actual memory references when repeated

ly referenc-

ing pages, a hardware implementation may include
a mechani

sm to

remember successful virtual address translat

ions and page statuses.

Such a mechanism is termed a translation buffer,

Whenever the process context is loaded with LDPCTX
buffer is automatically updated (i.e., the process

, the translation

virtual address trans-

lations are invalidated). However, whenever a page

table entry for the

system or current process region is changed
, other than to set the
page table entry V bit, the software must notify
the translation buffer of

this by moving an address within the corresp
onding page into the
translation buffer invalidate single register (TBIS).
The TBIS register is
illustrated in Figure 6-15.

Whenever the location or size of the system map
is changed (SBR,
SLR) the entire translation buffer must be cleared
by moving 0 into the

translation buffer invalidate all register (TBIA).
The TBIA register is

illustrated in Figure 6-16.

Since the content of the translation buffer at bootstr
ap time is UN-

PREDICTABLE, the entire translation buffer must
be cleared by moving 0 into TBIA before enabling memory manage
ment.

0
VIRTUAL ADDRESS

Figure 6-15

Translation Buffer Invalidate Single (write only)

116

Memory Management

31
MBZ

Figure 6-16

Translation Buffer Invalidate All (write only)

FAULTS AND PARAMETERS

There are two types of faults associated with memory mapping and

protection. A Translation Not Valid fault is taken when a read or write

reference is attempted through an invalid PTE (PTE<31>=0). An
Access Control Violation fault is taken when the protection field of the
PTE indicates that the intended access to the page for the specified

mode would be illegal. Note that these two faults have distinct vectors

in the system control block. If both Access Control Violation and
Translation Not Valid faults could occur, then the Access Control Violation Fault takes precedence. An Access Control Violation fault is
also taken if the virtual address referenced is beyond the end of the
associated page table. Such a “length violation” is essentially the
same as referencing a PTE that specifies “No Access” in its protection
field. To avoid having the fault software redo the length check, a
“length violation” indication is stored in the fault parameter word described in Figure 6-17.

([ p |1 |15

SOME VIRTUAL ADDRESS IN THE FAULTING PAGE
PC OF FAULTING INSTRUCTION
PSL AT TIME OF FAULT

Figure 6-17

Fault Parameter Word

The same parameters are stored for both types of fault. The first
parameter pushed on the kernel stack after the PSL and PC is the
initial virtual address that caused the fault. A process space reference
can result in a system space virtual reference for the PTE. If the PTE
reference faults, the virtual address that is saved is the process virtual
address. In addition, a bit is stored in the fault parameter word indicating that the fault occurred in the PTE reference.
117

Memory Management

The second parameter pushed on the kernel stack contains the follow-

ing information:

L<0>

Length Violation. Set to 1 to indicate that an Access
Control Violation was the result of a length violation
rather than a protection violation. This bit is always 0

for a Translation Not Valid fault.
P<1>

PTE Reference. Set to 1 to indicate that the fault
occurred during the reference to the process page

table associated with the virtual address. This can be
set on either length or protection faults.

M<2>

Write or Modify Intent. Set to 1 to indicate that the
program’s intended access was a write or modify.

This bit is 0 if the program’s intended access was a

read.

PRIVILEGED SERVICES AND ARGUMENT VALIDATION

Change Modes
There are four instructions provided to allow a program to change the
mode at which it is running to a more privileged mode and transfer

control to a service dispatcher for the new mode.

CHMK

Change mode to kernel

CHME

Change mode to executive

CHMS

Change mode to supervisor

CHMU

Change mode to user

(Refer to the Architecture Handbook for greater detail.) These
instructions provide the only mechanism for the less privileged code

to call the more privileged code. When the mode transition takes
place, the previous mode is saved in the Previous Mode field of the

PSL, thus allowing the more privileged code to determine the privilege

of its caller.

Validating Address Arguments
Two instructions are provided to allow privileged services to check
addresses passed as parameters. To avoid protection holes in the

system a service routine must always validate that its less privileged

caller could have directly referenced the addresses passed as param-

eters. This validation is done with the PROBE instructions.

Notes on the PROBE Instructions
1.

The valid bit of the page table entry mapping the probed address

is ignored.

Alength violation gives a status of “not-accessible.”
118

Memory Management

On the probe of a process virtual address, if the valid bit of the
system page table entry is clear, then a Translation Not Valid fault
occurs. This allows for the demand paging of the process page
tables.

On the probe of a process virtual address, if the protection field of
the system page table entry indicates no access, then a status of
“not-accessible” is given. Thus, a single no access page table
entry in the system map is equivalent to 128 no access page table
entries in the process map.

It is UNPREDICTABLE whether the modify bit of the examined

page table entry is set by a PROBEW.

ISSUES

During the system design stage, the following question was raised:
Would a physically based, physically contiguous system page table
require a large amount of memory to handle a reasonable number of
very big processes?

Size Of System Page Table

To examine the size of the system page table, note first that one page
of the SPT maps 64K Bytes of system virtual address space. The
system virtual address space contains the following mapped quantities:

Operating system code and data (excluding memory management data): 64 to 96K Bytes, 1to 1.5 pages.

Memory management data for physical page management: 4106
longwords per physical page of memory. One longword of page
table maps one page of memory management data which handles
24 physical pages of memory. One page of page table handles 3K

Shared code
— command interpreter

physical pages = 1.5M Bytes of physical memory.

—

debugger

—

record manager

—

OTSes, FORTRAN, COBOL, BASIC

Allowing 16K Bytes for each of the above items, the total is 96K Bytes
or 1-2 pages of system page table.

Process page tables. One longword of SPT maps one page of
process page table which in turn maps 65K Bytes of process
virtual address space. 16 longwords of SPT maps 1M Byte of
process virtual address space. One page of SPT maps 8M Bytes.
A very straightforward balance set management design that re119

Memory Management

served a fixed (SYSGEN) number of balance set slots, each with a
fixed (also SYSGEN) maximum virtual address space, would use
only 2 pages of SPT to allow 16 processes of up to 1M Byte each
in the balance set.

It would appear from the foregoing analysis that a 6-page SPT wouid
handie a very reasonable system, and that increasing the 1M Byte
process virtual space to 4M Bytes and 16 processes in the balance set

would add only 6 more pages of SPT for a total of 12. A smaller system
with 256K Bytes of memory and 8 balance set processes, each 512K

Bytes maximum size, would need about 3 pages of SPT.

Sharing
To discuss sharing, it is useful to assume a section in the operating
system. A section is a collection of pages that have some relationship
to each other. Though units as small as pages may indeed be shared,

sections are the usual unit of sharing.

Shared Sections In Process Space — Sharing in the process half of
the virtual address space requires that the page table fragments for
the sections being shared be replicated
in the process page table(s).

Clearly this introduces multiple PTEs for the same physical page. This
is a problem traditionally avoided by one or more levels of indirection,
i.e., the PTE points to the shared PTE that points to the page. We can
avoid introducing this level of indirection in the hardware by observing
the following software rules:
1.

A share count is maintained for each shared page in memory and
in effect counts the number of direct pointers to that page.

When a process releases a page from its working set, and itis a
shared page as indicated in the working set data base, the private

PTE must be changed to point to the shared PTE for the page, and
the private copy of the modify bit must be ORed into the shared
PTE. Then the share count is decremented, and if the count is now

0, the page is released and the shared PTE is updated to reflect
that. Note that the process’s working set data base allows it to find
its private PTE, and the physical page data base points to the

shared PTE.

When a process gets an invalid page fault, one of the possible
states of the “invalid” PTE is that it points to a shared PTE. Of
course, that PTE might say that the page was not resident and
required a page read. Whether or not the read was necessary, the
shared PTE is eventually copied to the private PTE and the share

count of the page is incremented.

120

Memory Management

Note that throwing a process out of the balance set is the

equivalent of releasing all its pages.

The use of the indirect page pointer as a software-only mechanism seems to be adequate for this form of sharing. It should be

noted that it is very difficult to change the PFN of a page in memo-

ry when it is actively being shared. That would require a scan of

the page tables for all the processes in the balance set.

Shared Sections In System Space — When a process is using a
shared section in the system region of the address space, it is refer-

encing a single shared page table. Since it is possible for a process

simply to reference such a shared section without ever having declared its intention to do that, the operating system must be prepared
to do something reasonable when such a reference faults. A
straightforward design for this kind of sharing is:

Have programs explicitly declare their intention to use each
shared system section. This could be done statically at compile or
link time or dynamically at runtime.

2
3.

Have the balance set manager swap in and lock down the entire

section when the process intending to use it is swapped in.
Of course, the balance set manager maintains share counts on
the section and discards its pages only when no process in the
balance set wants it.

If a process faults such a page because it failed to declare its

intention to use the section, then that is considered a programming error.

Another approach for shared system sections allows a process to
reference pages of the section with no prior declaration of its intent to
use them. Such pages would be demand paged within a pool of pages
reserved for that purpose. There would be a list of the pages in use in
that pool, and a fault for a new one would cause one in the pool to be
replaced. This would use the same sort of working set management

that is used for the process address space, but it would be global
across processes.

Protection Check Before Valid Check

The page table entry has been defined as having a valid bit that only
controls the validity of the modify bit and page frame number field.
The protection field is defined as always being valid and checked first.

The motivation for this design is the behavior the PROBE instruction
would exhibit if the valid bit had to be set before it could check
protection. PROBE woulid actually have to fault in the page to make it
valid, so that it could check the protection and then indicate whether
121

Memory Management

or not the intended access was permissible. For the vast percentage of

PROBE instructions, the access is permitted and faulting the page
in
the PROBE is reasonable. But a program could be run in user mode

that would PROBE all around in the system region of the
virtual address space faulting all the swappable pages of the system. Though

this would not violate the integrity of the operating system, it
certainly
would mess up any statistics that the system might be gathering
about
the relative worth of the swappable pages.

EXAMPLE
Appendix F contains a virtual to physical address

122

translation.

123

CHAPTER 7

SYNCHRONOUS BACKPLANE INTERCONNE

a path that
nect (SBI) is the dat
Backplane intercon
The Synchronousproc
hardware
the
and
,
tem
sys
sub
the memory
links the central foressother, UNI
VAX
and MASSBUS. The -11/780
adapters provided ted in FigBUS
ure 7-1.

INTRODUCTION

bus structure is illustra

NECT

SYNCHRONOUS BACKPLANE INTERCON

UNIBUS

MASSBUS

UNIBUS
DEVICES

MASSBUS
DEVICES

ADAPTER

Figure 7-1 Basic Bus Configuration

essor, memory subsysSBI, the central proc
When interfaced to the
.
tem, and 1/0 controllers are known as NEXUSs
connection to the SBl and is capable of acting
A NEXUS is a physical
as any of the following:
and address
Commander — A NEXUS which transmits command
information.
izes command and address
Responder — A NEXUS which recogn
iring a response.
requ
information as directed to it anddriv
es the signal lines.

Transmitter — A NEXUS which
samples and examines the signal lines.

Receiver — A NEXUS which

125

Synchronous Backplan

e Interconnect

A NEXUS also performs

priority arbitration for
its access to the SBI.
A NEXUS may perfor
m more than one func
tion, as illustrated in
the
two following examples
.

When the CPU issues
a read command it is
a commander since it
issues command/address
information. At the sam
e time it is a transmitter since it is driving
the signal lines. When
the device (responder)
returns the requ

ested data, the CPU
is considered a rece
iver since it
examines the signal
lines.

Also, since it examines
returns the requeste

the signal lines, it is a

d data by driving the

ter.

receiver. When memory

signal lines, it is a tran

smit-

All NEXUSs receive ever

y SBI transfer. Logic
in each NEXUS deterUS is the designated
receiver for this transfer
.

mines whether the NEX

Data may be exchanged

between the following

® The central processo
r and
® /0 controllers and
mem

¢ Central processor and

system elements:

memory subsystem.

ory subsystem.

1/0 controllers.

The communication prot
ocol allows the informat

multiplexed in such
a way that up to 32
data

progress simultan

eously.

The SB!

ion path to be time-

exchanges may be

provides checked, para

with a common system

llel information transfer

clock. In each clock

synchronous

period or cycle (duratio

n
nect arbitration, info
rmation transfer and
transfer
confirmation may occu
r. Utilizing the 200
nsec clock period, the
SBI
achieves a maximum
information transfer
rate of 13.3 million byte
s
per
seco
of 200 nsec) intercon

nd.

SBI STRUCTURE
The SBI is comprised

of 84 signal lines as illu

strated in Figure 7-2. Its

maximum physical
length may not exc
eed 3 met

of the SBI are divided
® Arbitration

into the following function

ers (9.8 ft). The line

al groups:

® Information
® Response

® Interrupt

® Control

126

Synchronous Backplane Interconnect

TR<1500>

INFORMATION TRANSFER
P<1:0> (PARITY)

TAG<2:0> (TAG)

1D<4:0> {IDENTIFIER]

M<3:0> {MASKI

B8<31:00> (INFORMATION)

TRANSMIT/
RECEIVE

RESPONSE
FAULT

CNE<1:0> (CONFIRMATION}

NEXUS

IRt

TrnantaN

ARBITRATION

TRANSMIT/
RECEIVE

NEXUS

CONTROL
UNJAM
FAIL

DEAD

Figure7-2

CLOCK (6 LINES)

INTERRUPT REQUEST

REQ <7:4> (REQUEST)
ALERT

MP1-2

SPARE (2 LINES)

Uy
4

T
1t

INTLK (INTERLOCK}

SBI Signal Description

Arbitration Lines

TR (transfer
There are 16 bus arbitration lines. Each arbitration line,
ishing a
request) <15:01>, is assigned to one NEXUS, therebytoestabl
7-3).
Figure
fixed priority access to the information path (referTROO is reserv
ed
where
Access priority increases from TR15 to TR0OO,
for use as a hold signal for the following reasons:

1. NEXUS requires two or three adjacent cycles for a write type
exchange.
2. NEXUS requires two adjacent cycles for an Extended Read exchange.

3. Central processors for Interrupt Summary Read exchanges.
4.

TROO is reserved for an SBI UNJAM operation.
127

Synchronous Backplane Inter

0
1

2
3

MEMORY CONTROLLER # 1
MEMORY CONTROLLER # 2
UNIBUS ADAPTER

*
*

\RESERVED FOR
[ FUTURE USE

8
9

INCREASING PRIORITY

connect

HOLD

LINE

MASSBUS ADAPTER # |

MASSBUS ADAPTER
#2
MASSBUS ADAPTER # 3
MASSBUS ADAPTER #4

: RESERVED FOR

[ FUTURE USE

15 *

CENTRAL PROCESSOR

Figure 7-3

SBI Priority Access

To acquire control of the information
path, a NEXUS asserts its assigned (transfer request) line at the beginn
ing of a cycle.
At the end of the cycle, the NEXUS exami
request lines of higher priority. If no

nes the state of all transfer

higher priority NEXUS is arbitrat-

ing for control of the SBI, the NEXUS

will remove its transfer request

and assert information path signals.
The

lowest priority NEXUS arbitrating for control of the SBI is the
central processing unit. The CPU

does not require a transfer request signal,

control of the SBI when no higher priorit

since by default it will gain

y NEXUS is arbitrating.

Information Lines

The

information transfer group exchanges
command/addresses,
data, and interrupt summary information.
Each exchange consists of

one to three information transfers.

For write commands, the commander
uses two or three succes

sive

SBI cycles. The number of successive
cycles requir

ed depends on

whether one or two data words are to
be written in the exchange. In the
first case, the commander transmits the
command/address in the first
cycle, and a data word in the secon
d cycle. In the second case, the

commander transmits the command/ad
dress in the first cycle, data

word 1in the second cycle, and data word

2 in the third cycle.

Read commands are also initiated with a comma

nd/address transmit-

ted from the commander. However, since
data emanates from the

responder, the requested data may
be delayed by the characteristic

access time of the responder. As
in a write exchange, the read ex-

change will transmit data using one or two
ing on whether one or two data words were
128

successive cycles depend-

requested.

Synchronous Backplane Interconnect

An interrupt summary exchange is in response to a device-generated

interrupt to the CPU. The exchange is initiated with an interrupt summary read transfer from the CPU. The exchange is completed two

cycles later with an interrupt summary response transfer containing
the interrupt information.

The Information Transfer Group is subdivided into the following five

fields:

Length in Bits
2 (P <1:0>)
3(TAG <2:0>)
5(ID <4:0>)
4 (M <3:0>)
32 (B <31:00>)

Field
Parity check
Information Tag
Source/Destination ldentity
Mask
Information
PARITY FIELD

The parity field (P<1:0>) provides even parity for detecting single bit
errors in the information transfer group. A transmitting NEXUS
generates PO as parity for the Tag, Indentifier, and Mask fields and P1
as parity for the Information field. The parity field is illustrated in Figure 7-4.

PARITY

FIELD

TAG
FIELD

NTIFIER
D€
FIELD

e
D B WD
1D<4:07>
TAG<2:0>
P<1:0>

MAS K

FIELD

M<3:0>

INFORMATION FIELD

8<31:00>

—

COMMAND FORMAT

FUNCTION
FIELD

F<3:0>

Figure 7-4

TM~

ADDRESS
FIELD

A<27:00>

Parity Field Configuration

PO and P1 are generated in such a way that the sum of all logical one
bits in the checked field, including the parity bit, is even.

When the SBI is idle, the information transfer path assumes an all-zero

state, therefore, the parity field should always carry an even parity.
TAG FIELD

The tag field (TAG<2:0>) is asserted by a transmitting NEXUS to

indicate the information type being transmitted on the information
129

Synchronous Backplane Interconnect

lines. The tag field determines the interpretation of

the ID and B fields.

In addition, the tag field, in conjunction with
the mask field, further

defines special read and write data conditions.

Four tag fields and four reserved fields are defined

as:

TAG <2:0>

B<31:00> contents

000

READ DATA

011

COMMAND ADDRESS

101

WRITE DATA

110

INTERRUPT SUMMARY READ

The remaining tag fields, 001, 010, 100, and 111,

are reserved.

e Read Data Tag
A tag field content of 000 specifies that
the information field
B<31:00> contains data requested by a
previous read type command. The retrieved data may be one of
three types: read data, corrected read data, and read data substitute.
The retrieved data type is
identified by the mask field M<3:0>. Read data
is the normal expect-

ed error-free data type, where M<3:0> =
0000. Corrected read data
(CRD) is represented by M<3:0> = 0001, and
read data substitute is

represented by M<3:0>

= 0010. The recipient of the read data
is

designated by ID<4:0>. The read data tag formats

are illustrated in

'_*_ B<31:00>

figure 7-5.

DATA
P! ]PO' 000 LQCIPlENT]
0000 l

READ DATA FORMAT

—

PARITY <110>—’

TAG <2:0>
1ID<4:0>

MASK<3:0>

READ DATA <31:00>

I—L
I P1 | PO [ 000 ]RECIP‘ENT'
DATA
0001
—

PARITY <1:0>—#

8<31:00>
CORRECTED READ DATA FORMAT

—

TAG <2:0>
1D <4:0 >

MASK<3:0>
READ DATA <31:00>

)

130

j‘
]
J

Synchronous Backplane Interconnect

}-——/B<3]:00> ’-’————-\
]

SUBSTITUTE READ DATA FORMAT

DATA
0010
RECIPIENT

PARITY <1:0> -—J

TAG <2:0>
1D <4:0>

MASK <3:0>

READ DATA <31:00>

Figure 7-5

Read Data Tag Formats

e Command/Address Tag

data lines contain a
A tag field content of 011 specifies that the
identifyuniqu
a
is
:0>
command/address word, and that ID<4 command. eAscode
rated in
illust
that
of
)
ing the logical source (commander
ss
addre
an
and
field
on
functi
a
into
ed
divid
is
Figure 7-6, B<31:00>
field to specify the command and its associated address.
B<31:00>

N
.

TAG

MASK

FUNCTION

ADDRESS

TAG<2:0>

10<4:0>

M<3:0>

F<3:0>

A<27:00>

TAG<2:0> = 011 = COMMAND/ADDRESS FORMAT
ID<4:0> = LOGICAL COMMAND SOURCE
M<3:0> = COMMAND DEPENDENT
F<3:0> = COMMAND CODE

A<27:00> = READ/WRITE, ADDRESS OF INTENDED NEXUS

Figure 7-6

Command/Address Format

of the data in a write
The ID field code represents the logical source addre
ss of where the
the
command, and the address field specifies the
sents the
field
ID
data is to be written. For a read command, on specified repre
address
the
in
locati
the
at
logical destination of the data
field.

longword adThe 28 bits of the address field define a 268, 435,d456
two sections.
into
divide
is
dress space (1, 073, 741, 824 bytes) which ved for prima
ry memoAddresses 0-7FFFFFF (hex) (A27=0) are reser

(A27=1) are reserved
ry. Addresses 8000000 (hex) - FFFFFFF (hex)
ry begins at address 0, the

for device contro! registers. Primary memo
ge elements. Figure
address space is dense and consists only of stora
. Note that both
space
ss
addre
al
physic
27 illustrates the VAX-11/780
physical and SBI addresses are provided.
131

Synchronous Backplane Interc

onnect

280-le s8I o
LONGWOR
ADDRESSES

30-BIT PHYSICAL
BYTE ADDRESSES

000 0000

0000 0000

1-4M BYTE

MEMORY CONTROLLER 1

1-4M BYTE

MEMORY CONTROLLER 2

ADDRESS
9FF

FFFF

800

0000

2000

0000

800

0800

2000

2000 [ q,

8K BYTES

800

1000

2000

4000 | 155

8K BYTES

\FFF_FFFF

SPACE

8K BYTes|

)

ADAPTOR OR
:
,
ADDRE

800

7000

2007

800

7800

2007

]
|

€000

SPACE

A TOTAL OF

128

BYTES

i
i

[1eps

8K BYTES

EOOD [ 1ars

8K BYTES

J
128K RESERVED
ADDRESS SPACE

804 0000
805

0000

806 0000

2010 0000 [ yniBUSO ADDRESS SPACE
2014

0000

UNIBUS| ADDRESS

THE UNIBUS ADAPTOR
sPACE | | THE
IBUS ADAPTC

2018 0000 f yNigys2 ADDRESS SPACE

807 0000

210C 0000 [ ynigus3 ADDRESS SPACE

FFF

3FFF

FFFF

)

DRRS THESE

FFFF

Figure 7-7

SBI Physical Address Space

The user has access to the physical
address space via the 30-bit

physical byte address. However, since
NEXUS registers are accessible
only as longword addresses, syste
m hardware converts the physical

byte address (30 bits) to the SBI longw
ord address (28 bits). This

translation is described in Figure 7-8.

132

Synchronous Backplane Interconnect
VIRTUAL ADDRESS FOR OPERAND OR INSTRUCTION REFERENCE

210

31 3029

0 0:P0
01 =Pl

10 =Y

AN VIRTUAL ADDRESS \

B2 ARE AN
N BITS
« ALWAYS PHYSICA'\L

1 1 = RESERVED

ADDRESS BITS
. \\<8:2>
N

TRANSLATED FROM

31 30

vl PROT

27 2 25

ADDRESS ON
CPU PHYSICAL
ADDRESS BUS

2) 20

TRANSLATION BUFFER

0 N8

PAGE FRAME NUMBER

o~ PAGE

LONGWORD

L ,/

////
////

2\119_1

l j
.I[

— —4-

7 BITS ONE

ZEROTO
ANDUSED
~” ARE
ALIGN DATA

2,10
b Bl |

?/8

7V4

\ N\

]

—J-d

\
A

\
AY

1S CONCERNED

\\27

ADDRESS
ON S5BI

ON SBI BECAUSE MEMORY 15 LONGWORD ORIENTED
BIT 29 BECOMES BIT 27 RDS

AND

FETCHES ARE QUADWO

Figure 7-8

Physical To SBI Address Translation

not lost,
The low order two bits of the physical to SBI translation arecomm
and
SBI
the
ing
adjoin
field
mask
the
by
but are represented
address format.

nments based
The control address space is sparse with address assig
longword
32-bit
2048,
a
ed
assign
is
on device type. Each NEXUS
ed are
assign
sses
addre
The
status.
and
l
contro
address space for
determined by the TR number as shown in Figure 7-9.

SPECIFIES ONE OF THE

SPECIFIES ONE

2048 LOCATIONS

F_A__\

—

OF 16 NEXUS

15 14

27 26
1

ASSIGNED TO EACH NEXUS

11 10

MUST

————

BE ZERO

TR#

—

SPACE

BLOCK)
y’

A<27:00>

Figure 7-9

Control Address Space Assignment
133

Synchronous Backplane Interc

onnect

The command/address tag forma

ts are illustrated in figure 7-10.

P1|PO|

011

oDRGATES
T

DETINANONDERED J 0001 '

REA

~—

READ MASKED FORMAT—

TEESKB?E

PaRITY <1:0>—
4

READ DATA AT THIS

ADDRESS

(

TAG <2:0>
1D <4:0>

MASK <3:0>
FUNCTION<3:0>

PHYSICAL ADDRESS < 27:00>

p0 | 011

DETRATONDRIED" | 0100 |

F o para

ETESTO

READ INTERLOCKED MASKED FORMAT-

READ DATA AT THIS ADDRES
S

<
J

PARITY <1:0> —?
TAG<2:0>

ID<4:0>

MASK<3:0>
FUNCTION<3:0>
PHYSICAL

ADDRESS <27:00>

{CAL

AT 0

4 °%° ,

INATION
—

READ DATA AT THIS ADDRESS
READ EXTENDED FORMAT-

)

pariTy<1:0> 4
TAG <2:0>

ID <4:0>

MASK <3:0 >

IGNORED BY MEMORY

FUNCTION <3:0>
PHYSICAL ADDRESS <27:00>

B<31:00>

adl:za>l¢—‘s<27:oo> \_..{
Prirof

EoF

T WRITE

0010

WRITE MASKED FORMAT-

PaRITY <1:0>_____#

ADDRESS WHERE DATA IS TO BE WRITTEN
y,

TAG <2:0>

ID <4:0>

MASK <3:0>

FUNCTION <3:0>
PHYSICAL

ADDRESS <27:00>

B<31:00>

BB
|

PI|PO]

—

SO0kReRt

[RDICATES
oF

ITE_DATA

1D <4:0>

(0111

ATA

PARITY <1:0> ——
4
TAG <2:0>
‘

T
j
l

MASK <3:0>
FUNCTION <3:0>

PHYSICAL

ADDRESS <27:00>

134

527:005 e

—

WRITE MASKED INTERLOCKED FORMAT-

ADDRESS WHERE DATA 1S TO BE
WRITTE

T
i

Synchronous Backplane Interconnect

'———— B<31:00>

|B<51528'>|.———— B<27:00> _____‘l

:;Ng.k%fi&. 011 ||
(o1 1pol 011 [SOORE"
Rhire oana MRS
P11
N

‘

PARITY <1:0> 4
TAG <2:0>

WRITE EXTENDED FORMAT-

ADDRESS WHERE DATA IS TO BE WRITTEN

ID<4:0>

MASK <3:0>
FUNCTION<3:0>

PHYSICAL ADDRESS <27:00>

Figure 7-10

Command/Address Tag Formats

e Write Data Tag

A tag field content of 101 specifies that B<31:00> contains the write
data for the location specified in the address field of the previous write
command. The write data will be asserted on B<31:00> in the SBl
cycle immediately following the command/address cycle. The ID field

transmitted is that of the commander. Figure 7-11 illustrates the write
data tag format.

[

N,
PARITY <110>—-—J

RREE

! he l BYTE 3 ’ BYTE 2 \ BYTE 1 \ BYTE OJ

TAG<2:0>"1

ID<4:0>

MASK<3:0>
WRITE DATA <31:00>

* MASK=1 IF THAT PARTICULAR BYTE IS TO BE WRITTEN

Figure 7-11

Write Data Tag Format

e Interrupt Summary Tag

A tag field content of 110 defines B<31:00> as the interrupt level
mask for an interrupt summary read command. The level mask
(B<07:04>) is used to indicate the interrupt level being serviced as the
result of an interrupt request. In this case, the ID field identifies the
commander, which is the CPU. Although unused, M<3:0> is to be
transmitted as zero.

135

Synchronous Backplane Interconnect

The interrupt sequence consists of two exchanges:

The first exchange indicates the interrupt level being serviced.
The interrupt level is determined by:

I/0 controller asserts interrupt

CPU strobes the interrupt, and if level 7 is the current level,

interrupt code is called which performs the Interrupt Service

Request

The second exchange is the response, where the device requesting the interrupt identifies itself. From the identity of the
device and the interrupt level the starting address of the service

routine can be determined.

Figure 7-12 illustrates the interrupt summary tag format.

P PO‘ 110 lsouace !0000 !o

]z’z’z zq 0000 }

0 LEVEL,
V]

PARITY <1:0> ——f
TAG <2:0>

1D <4:0>
MASK <3:0>
REQUEST LEVEL<3:0>

Pl Polooo}:svmnou oooo]

lo]

{oJ

PARITY <1:0> ———3
TAG <2:0>

1D<4:0>
MASK <3:0>
VECTOR GENERATING PAIR

Figure 7-12

Interrupt Summary Tag Format

® Reserved Tags

Tag (<2:0>=111) is reserved for diagnostic purposes. Tag codes 001,

010, and 100 are unused and reserved for future definition.
136

Synchronous Backplane Interconnect

SOURCE/DESTINATION IDENTITY FIELD
The ID field (ID<4:0>) contains a code which identifies the logical
source or logical destination of the information contained in
B<31:00>. ID codes are assigned only to commander and responder
NEXUSs (which issue/recognize command/address information).
Each NEXUS is assigned an ID code which corresponds to the TR line

which it operates. For example, a NEXUS assigned TRO5 would also
be assigned ID code=5.
MASK FIELD

The mask field (M<3:0>) has two interpretations. In the primary interpretation, M<3:0> is encoded to specify operations on any or all bytes

appearing on B<31:00>. The mask is used with the read masked,
write masked, interlock read masked, interlock write masked, and
extended write masked commands. As shown in Figure 7-13 each bit
in the mask field corresponds to a particular byte of B<31:00>.

SELECTS BYTE(S) FOR AN OPERATION

MASK

TAG

)

INFORMATION

COMMAND /ADDRESS

OR WRITE DATA

BYTE 3 BYTE 2 BYTE 1 BYTE OJ ADDRESS LONGWORD LOCATION
MASK AS BYTE SPECIFIER

Figure 7-13

Mask Field Format

As previously mentioned, the secondary interpretation is used when
Tag<2:0> = 000 (read data). Figure 7-14 illustrates the read data
mask field.

DESCRIBES DAT

DATA DESCRIBEC

MASK

DATA LONGWORD

3210

o]
o]
o]

0
1

CORRECTED READ DATA-DATA HAD A ONE-BIT ERROR WHICH HAS BEEN CORRECTED

READ DATA SUBSTITUTE-DATA CONTAINS AN UNCORRECTABLE ERROR

READ DATA -DATA IS CORRECT

MASK AS DATA

Figure 7-14

INTEGRITY SPECIFIER

Read Data Mask Format
137

Synchronous Backplane Interconnect

Response Lines
There are three response lines, broken down into two fields, confirmation CNF<1:0> and Fault (FAULT). CNF <1:0> informs the transmitter whether the information was correctly received, or if the receiver
can process the command. FAULT is a cumulative error indication of
protocol or information path malfunction, and is asserted with the

same timing as the confirmation field. The CPU latches the fault signal,
which in turn latches all the fault status registers and the SBI silo. The

silo is a hardware mechanism used to record the last 16 SBI transactions. The silo aids in rapid error detection. The fault is then cleared by
the software.

Either field is transmitted to the receiver two cycles after the
associated information transfer. Confirmation is delayed to allow the
information path signals to propagate, be checked, decoded by all
receivers, and to be generated by the responder. During each cycle

every NEXUS in the system receives, latches, and makes decisions on
the information transfer signals. Except for multipie bit transmission

errors or NEXUS malfunction, one of the NEXUSs receiving the information path signals will recognize an address or ID code. This NEXUS
then asserts the appropriate response in CNF. The confirmation codes

and their definitions are listed in Table 7-1.

Table 7-1

Confirmation Code Definitions

CNF Code

Definitions

00, No Re-

The unasserted state and indicates no responseto a

sponse (N/R)

commander’s selection.

01, Acknowl-

The positive acknowledgement to any transfer.

edge (ACK)
10, Busy

(BSY)

The response to a command/address transfer, and

indicates successful selection of a NEXUS which is
presently unable to execute the command.

11, Error

(ERR)

The response to a command/address transfer, and

indicates selection of a NEXUS which cannot execute the command.

A BSY (10) or ERR (11) response to transfers other than command/address transfers will be considered as no response from the
transmitter.

138

Synchronous Backplane Interconnect

Interrupt Request Lines

The interrupt request group consists of four request iines
(REQ <7:4>) and an alert (ALERT) line. A request line is assigned to

each NEXUS that interrupts and represents its assigned CPU interrupt
level. The lines are used by NEXUS to invoke a CPU to service a

condition requiring processor intervention. The request lines are priority encoded in an ascending order of REQ4-REQ7. A requesting
NEXUS asserts its request lines synchronously with the SBI clock to
request an interrupt. Any of the REQ lines may be asserted simultaneously by more than one NEXUS, and any combination of REQ lines
may be asserted by the collection of requesting NEXUSs.
The alert signal is asserted by NEXUSs which do not implement

interrupt request lines. Its purpose is to indicate to the CPU a change
in NEXUS status of power condition or operating environment. NEXUSs which implement the REQ lines report these changes by requesting an interrupt.

Control Lines
The control group functions synchronize system activities and provide

specialized system communications. The group includes the system

clock which provides the universal timebase for any NEXUS connected to the SBI. The group also provides initialization, power fail, and
restart functions for the system. In addition, a path is provided for
coordinating memories to assure access to shared structures.

The control lines are comprised of the following subgroups: clock
functions, interlock line, dead signal function, fail function, and the
UNJAM function.

CLOCK FUNCTIONS
Six control group lines are clock signals and are used as a universal

time base for all NEXUSs connected to the SBI. All SBI clock signals
are generated on the CPU clock module and provide a 200 nsec clock

period.
INTERLOCK LINE
The interlock line will be discussed in the command code description
section.

DEAD SIGNAL FUNCTION
The Dead signal indicates an impending power failure to the clock

circuits on bus terminating networks. NEXUSs will not assert any SBI
signal while Dead is asserted. Thus, NEXUSs prevent invalid data from
being received while the bus is in an unstable state.

The assertion of the power supply DC LO to the clock circuits or

terminating networks causes the assertion of Dead. Dead is asserted
139

Synchronous Backplane Interconnect

asynchronously to the SBI clock and occurs at least two usec before
the clock becomes inoperative. With power restart, the clock will be
operational for at least two usec before DC LO is negated. The nega-

tion of DC LO negates Dead.
FAIL FUNCTION

A NEXUS asserts the Fail (FAIL) function asynchronously to the SBI

clock when the power supply AC LO signal is asserted to that NEXUS.
The assertion of Fail inhibits the CPU from initiating a power up
service routine. Fail is negated asynchronous to the SBI clock when all

NEXUSs that are required for the power up operation have detected
the negation of AC LO. The CPU samples the Fail line following the

power down routine (assertion of FAIL) to determine if the power down
routine should be initiated.

UNJAM FUNCTION
The UNJAM function restores (initializes) the system to a known, well

defined state. The UNJAM signal is asserted only by the console of the
CPU, and is detected by all NEXUSs. The CPU asserts UNJAM only
when a console key is selected. The duration of the UNJAM pulse is 16

SBI cycles and is negated at TO.
When the CPU intends to assert UNJAM it will assert TROO for 16 SBI

cycles. The CPU will continue to assert TROO for the duration of UNJAM and for 16 SBI cycles after the negation of UNJAM. This use of

TROO insures that the SBI is inactive preceding, during, and after the
UNJAM operation.

COMMAND CODE (Function <3:0>) DESCRIPTION
Information bits B<31:00> carry most of the information on the SBI.
Information appears on these lines in command/address format, data

format, interrupt summary read format, or interrupt summary response format. In command/address format, information is grouped
in three fields: M<3:0>, the byte mask; F<3:0>, the function code;

and A<27:00>, a 28-bit physical address. Function codes are shown
in Figure 7-15. Bit 27 of the SBI address field determines whether the
longword address A<27:00> is located in memory or I/0 space (refer

to Chapter 8, figure 2).
Read Mask Function (F=0001)

Once the commander has arbitrated for and gained control of the SBI,
it asserts the information transfer lines at TO. The receiver latches
open at T2 and closes at T3. Information in these latches is stable from

T3tothe next T2.

140

Synchronous Backplane Interconnect

FUNCTION | ADDRESS

MASK
M<3:0>

F<3:0>

A<27:00>

MASK

FUNCTION

USE

CODE

DEFINITION
RESERVED

IGNORED

0000

USED

0001

READ MASKED

USED

0010

WRITE MASKED

IGNORED

0011

RESERVED

USED

0100

INTERLOCK READ MASKED

IGNORED

0101

RESERVED

IGNORED

0110

RESERVED

USED

0111

INTERLOCK WRITE MASKED

IGNORED

1000

EXTENDED READ

IGNORED

1001

RESERVED

IGNORED

1010

RESERVED

USED

1011

EXTENDED WRITE MASKED

IGNORED

1100

RESERVED

IGNORED

1101

RESERVED

IGNORED

1110

RESERVED

IGNORED

1111

RESERVED

Figure 7-15

SBI Command Codes

The command/address format instructs the NEXUS selected by
A<27:00> to retrieve the addressed data word, and transfer it to the
logical destination specified in the ID field. The addressed NEXUS will
respond to the command/address transfer with ACK (assuming the
NEXUS can perform the command at this time) two SBI cycles after
the assertion of command/address. Figure 7-16 illustrates the SBI
read function.

Write Masked Function (F=0010)

The write masked function instructs the NEXUS selected by A<27:00>

to modify the bytes specified by M<3:0> in the storage element addressed by A<27:00>, using data transmitted in the next succeeding
cycle. Figures 7-13 and 7-14 illustrate SBI write functions. Figure 7-17
illustrates a single SBI write transaction while Figure 7-18 illustrates
two SBI write transactions from devices A and B.

141

Synchronous Backplane Interconnect

5Bl

ACTIVITY

EVENTS

'l'

READ
MASK

ARBITRATION

MEMORY |

HOLD

INFORMATION

COMMAND

TRANSFER

DATA

ADDRESS

(TO A)

CONFIRM

CONFIRMATION

CONFIRM

(BY

(BY A)

MEMORY)

Figure 7-16

s8I

ACTIVITY

ARBITRATION

]

200 nsec 4-*_—’.._531 CYCLE

]

SBI Read Transaction

EVENTS

ACQUIRE
coNiROL |

HOW

WRITE
MASK

Teanerer N

COMMAND |
ADDRESS

DATA

(C/a)

CONFIRM | CONFIRM
(C/A)
{DATA)

CONFIRMATION

—

Figure 7-17

}‘

SBI

200nsec

SBI CYCLE

TRANSACTION

Single SBI Write Transaction
142

TIME
"

Synchronous Backplane Interconnect
SBI

ACTIVITY

ARBITRATION

EVENTS

HOLD

WRITE

INFORMATION
ANSFE

commanp|
ADDRESS
A

HOLD4

DATA
A

|commanp|
ADDRESS

WRITE

—>

DATA
B

CONFIRM | CONFIRM | CONFIRM | CONFIRM

CONFIRMATION

(c/a-A) |(DATA-A)| (c’a- 8) [iDATA-B)

[

—
Figure 7-18

a1 e
Two SBI Write Transactions

Interlock Read Masked (F=0100)
This command, used to insure exclusive access to a particular memo-

ry location, causes the NEXUS selected by A<27:00> to retrieve and
transmit the addressed data as for Read Masked. In addition, this
command causes the selected memory controller NEXUS to set an

Interlock flip-flop. Only memory NEXUSs have the ability to assert
Interlock. While this flip-flop is set the NEXUS wiil assert the INTLK
signal synchronously at time TO. Interlock is asserted during the same

cycle as the confirmation signal. In the preceding cycle, the commander must assert Interlock. While the INTLK signal is asserted, the NEX-

US will respond with BSY confirmation to Interlock read masked commands. The Interlock flip-flop is cleared on receipt of an Interlock
write masked function. Interlock read masked and Interlock write

masked are always paired by commanders utilizing them.

Interlock Write Masked (F=0111)
The Interlock write masked function instructs the NEXUS selected by
A<27:00> to modify the bytes specified by M<3:00> in the storage
element addressed, using data transmitted in the succeeding cycle

with TAG=101. Additionally, the Interlock flip-flop is cleared.

Extended Read (F=1000)
The Extended Read function instructs the NEXUS selected by
A<27:00> to retrieve the addressed 64-bit data and transmit it to the
143

Synchronous Backplane Interconnect

ID accompanying the command as in the read masked function. The
responder transmits the data in two successive cycles with the low 32
bits (A00=0) preceding the high 32 bits (A00=1). Two data words are
always transmitted.

M<3:0>

and A00 of the received com-

mand/address word are ignored. M<3:0> must be transmitted as

0000 by the commander. Figure 7-19 illustrates extended read trans-

actions by two separate devices, A and B, reading memory via a single
memary controller.
SB1
ACTIVITY

EVENTS

ARBITRATION

IMEMORY|

HOLD

EXT

INFORMATION

READ | READ

TRANSFER

WMEMDRY | HOLD

D‘z“

DATA | DATA

(1o Al | (0 &)

Dara

o e | 0w

cin | CIA
A

ICONERM JICONFR
M

CONFIRMATION

ONF

10 A) |10 B}

]

Figure 7-19

CONFIRMICONFR
M|

18y A} 8y A)

w0 |y 8

200 nsac
SBI CYCLE

Extended Read Transactions Via Single Memory

Controller
Figure 7-20 illustrates extended read transactions by two separate

devices, A and B, reading memory via separate memory controllers,
M1 and M2.
ACTIVITY

EVENTS

o
>

ARBITRATION

EXT

#F&';;‘E‘;'ON

EXT

"CEAD

"c‘;‘f

HOLD

b ]

HOLD

alro arfmo

JCONFIRMICONF IRM |

RMATH
CONFIRMATION

1
T

]

1
T

{8y A [(BY A)[isv 8 [(BY )

Extended

Figure 7-20

mto w

JICONFRM JCONF IRMICONFIRMICONFIR
M|

1o A}{(10 8}

TMM

DATA} | DATAZ | DATA) | DATA2
o

l
T

Time

200 nsec

SBI CYCLE

Read Transactions Via Separate Memory

Controllers
144

Synchronous Backplane Interconnect

Extended Write Masked (F=1011)
The Extended Write Masked function instructs the NEXUS selected by
A<27:00> that 64 bits of data are to be written. The receiver ignores
A00 of the command/address transfer. A<27:00> indicates the low 32
bit word address. The write data is transmitted in two 32 bit words. The
first word corresponds to A00=0 and the second word corresponds to
A00=1. M<3:0> that accompanies the command address transmission indicates bytes to be written in the first write data word. M<3:0>
that accompanies the first write data word transmission indicates
bytes to be written in the second write data word. The M<3:0> field of
the second data word cycle is ignored by receivers but must be trans-

mitted as zeros. The assertion of a particular mask bit signifies that the
byte corresponding to that mask bit is to be modified. The NEXUS
impiementing the Extended Write Masked function must implement all
combinations of M<3:0>.

SYNCHRONOUS BACKPLANE INTERCONNECT THROUGHPUT
The following is a derivation of the aggregate throughput rate of the
SBl:

200 nanoseconds/cycle = 5 million cycles/second.

Each cycle can carry an address (memory request) or four bytes of
data.

Thus, one cycle is used to request eight bytes of data (to be read or
written), and two cycles are used to carry data (at four bytes/cycle).
5 million cycles/second x 4 bytes/cycle = 20 million bytes/second.
20 x 2/3 (1 of every 3 cycles is an address) = 13.3 million
bytes/second.

145

CHAPTER 8

MAIN MEMORY SUBSYSTEM
INTRODUCTION

Main Memory is a dynamic MOS (metal oxide semiconductor), random access memory designed to interface with the VAX-11/780 synchronous backplane interconnect.

The memory subsystem consists of a controller and one to sixteen
array boards utilizing either 4K or 16K N-channel MOS IC storage
elements. Each array board can contain 64K or 256K bytes of memory,
giving the system a capacity of either one or four megabytes, depending upon size of storage chips used.

Memory is capable of random access read and write operations to a
single 32-bit longword or extended 64-bit quadword. Memory is also
capable of random access write to an arbitrary byte, series of contiguous bytes, or a series of noncontiguous bytes. The memory array
board has been organized to optimize eight byte read/write access.

Memory features an error checking and correcting scheme (ECC)
which can detect all double bit errors and detect and correct all single

bit errors. The error detection and correction algorithm requires an
entire quadword of data and thus during any type of read or write
operation an entire quadword of data is fetched from the array.
Eight ECC check bits are stored with each quadword and accessed
with the data to determine its integrity. Therefore, a total of 72 bits are
accessed at once.

The basic memory subsystem is illustrated in Figure 8-1. |

147

Main Memory Subsystem

CPU

SBI

MEMORY

CONTROLLER

ARRAY
BOARD |

ARRAY
BOARD 2

Figure 8-1

| |

Areay
BOARD 16

Main Memory Configuration

MEMORY CONTROLLER
The memory controller is the NEXUS interfacing main memory to the

SBI. The controller examines the command and address lines of the
SBI for each SBI cycle. To initiate and complete a memory write
masked, interlock write masked, or extended write masked transaction, the controller must receive a recognizable command or address
and data in two or three SBI cycles. However, to perform a read
masked, extended read, or interlock read masked operation, the con-

troller need only recognize an appropriate command/address. The
controller provides the necessary timing and control to complete all
memory transactions. The controller informs a commander, via a con-

firmation, of a successful write operation and contends and arbitrates

for SBI bus control to transmit information during a read masked,
extended read, or interlock read operation. However, before the controller will initiate a memory cycle operation, it checks for bus
transmission parity errors and other fault conditions and reports these

conditions to the commander, conforming to the SBI protocol. Data
transfers to and from main memory are protected by ECC logic, i.e.,
main memory contains single bit error detection and correction and

double bit error detection logic to improve system reliability.

Error reporting provides an early warning to protect the system from
performance degradation. The system error logging feature requires
tagging single bit errors and uncorrectable errors during memory
read transmission from the memory subsystem. Also saved in the
memory controller are the syndrome bits for the first memory read

error and the error address for error logging and servicing. The memory controller retains this information until the first error is serviced.

148

Main Memory Subsystem

There are ten bits in register B that are used for ECC diagnostics only.

In addition to its error detection capabilities, the controller provides
the logic to buffer commands, addresses, and data, thus improving
memory throughput.

A system may require more than one memory controller. If the system
requires a two-controller interleaved memory configuration, the mem-

ory controllers must have consecutive TR selects. The interleave bit
will be cleared on power up and must be set by writing to configuration

register A in each controller. Each controller must have the same array
size and be issued the same starting address. In the case of multiple
memory controllers, (up to four) each controller will assume a different

starting address on power up. The proper starting address will be
written into the configuration B register from the SBI bus.
A read-only memory that can be addressed on the SBI bus resides in
the memory subsystem. The address, timing, and control logic to read
the information from the ROM for booting the system is also contained
in the subsystem.

The memory controller provides power up initialization logic and refresh control logic for the dynamic MOS memory devices. The dynamic MOS memory cell is a capacitor in which the stored charge
represents a data bit. As the stored charge tends to diminish over a
period of time, each cell requires a refresh cycle every 2 msec to retain
the charge reliability.

BASIC MEMORY OPERATIONS

The memory subsystem operates synchronously with the SBI clock
cycles, satisfying the system communication protocol. As discussed in
Chapter 7, SYNCHRONOUS BACKPLANE INTERCONNECT, the
physical address space is divided into two equal areas, memory address space, and I/0 address space. Figure 8-2 illustrates the physical
address space.

The 28-bit (A<27:00>) SBI longword address field (refer to figure 8-2)
is capable of accessing up to 512 M bytes of main memory. The hardware, however, will currently support a maximum of 2 Mbytes of main
memory utilizing the 4K chip design and 8 Mbytes utilizing the 16K
chip design. Physical memory operations are performed when bit
<27> of Figure 8-2 is zero. I1/0 operations occur when bit <27> is
one. The operation field identifies one of the following six transactions
performed by the memory subsystem:
e Read Masked

e Extended Read
e Interlock Read Masked
149

Main Memory Subsystem

F———‘ A<27:00> ——ci
3

[OPERATION /0]

ONGWORD ADDRESS

0
PHYSICAL
MEMORY
ADDRESSES

512 MB

170
ADDRESSES

OPERATION =READ MASKED

DORESSE

WRITE MASKED

ETC..
1,000 m8

SBI PHYSICAL
ADDRESS SPACE

Figure 8-2

Physical Address Space

¢ Write Masked

e Extended Write Masked
e Interlock Write Masked
A write mask operation is executed to transfer one to four bytes of

data to memory. A read mask operation, however, is only capable of
transtferring four bytes of data from memory.

An Extended Read is executed to transfer eight bytes of data (two
longwords) from memory to a requesting NEXUS. An Extended Write

Masked, on the other hand, provides a byte-selectable transfer of up

to eight bytes to memory. Interlock Read Masked and Interlock Write

Masked perform the same function as Read Masked and Write
Masked but also provide process synchronization.

Read Cycle

The read cycle will fetch 32 bits of data from the addressed location in

the memory subsystem, will check for a single or double bit error, will

correct a single bit error if it exists, and will transmit the data word
along with the proper tag and ID code of the commander that request-

ed the data. In the event a single bit error occurs during the read
150

Main Memory Subsystem

operation, corrected data would be rewritten into the memory in a
subsequent memory cycle. In the case of a double bit error, the exact
data and check code read is rewritten to ensure that the double bit

error recurs on subsequent reads. In either case, an indication of the
error condition wouid be tagged and transmitted with the corrected
data or uncorrectable bad data during the next available bus cycle to
the requester. The sequence of events that initiates a read cycle in a
memory subsystem is as follows:

Any commander on the SBI (central processor or /0 controller) that
wants to initiate a read cycle in any one of the memory subsystems on
the bus will arbitrate and gain control of the bus. Having gained control, the commander then transmits a command or address tag and
identification code information on the bus. All subsystems on the bus
monitor and decode the tag and command or address lines prior to
initiating any action. If the decoded address corresponds to the memory subsystem and if no faults are detected, it would immediately
(unless already busy) initiate a memory cycle. If the memory is presently executing a cycle, the command will be stored in the queue, if
there is room in the buffer, until the present cycle is complete. Either
way, the memory will notify the commander that the message has
been received. The address under interrogation would be fetched
from the memory, while the memory controller in the meantime would
request, arbitrate, and gain control of the bus to transmit the data
along with the commander’s identification code. Read cycles with single bit errors require an extra bus cycle to correct the error, and
therefore the controller would re-request the bus and transmit data
after gaining control of the bus.
Extended Read

The extended read cycle is the same as the read cycle, except that it
fetches 64 bits of data from the addressed location. Also, the data
would be transmitted on the SBI in two successive bus cycles; the
lower 32 bits are transmitted first and then the upper 32 bits. In the
event a single bit error occurs, the start of data transmission would be
delayed until the memory controller re-requests the bus and gains
control of the bus.
Write Masked

The write masked function instructs the memory controller selected by
the address (A <27:00>) to modify the bytes specified by (M<3:0>)in
the storage element addressed, using data transmitted in the next
succeeding cycie.

This is accomplished in the memory subsystem in two successive
memory cycles, a read followed by a write cycle as the memory is
151

Main Memory Subsystem

organized as an 8K x 72, with an ECC over 64-bit width. During the
read portion of the cycle, the 64-bit word is retrieved, the error code
checked, and the appropriate bytes are modified in the upper or lower
half of the word. New check bits are then encoded and the modified
word is written into the memory. If a single bit error occurs during the

read portion of the cycle it would be corrected. In the case of an
uncorrectable error the bad data would be rewritten into the memory

with the bad check code and the new data would not be used.

Up to four bytes in the upper or lower word can be modified in a write
masked cycle.

Extended Write Masked
The extended write masked function instructs the memory controller
selected by the address (A <27:00>) to first modify the bytes specified
by (M<3:0>) in the low 32 bits of storage element addressed, using
data transmitted in the next succeeding cycle. Then the controller is to
modify the bytes of the high 32-bit storage element specified by the
masks (M<3:0>) field found in the first data word cycle, using data
transmitted in the next succeeding cycle. The mask field in the second
data word transmission is ignored.

The implementation of this cycle is similar to write masked except in
the following areas:

e One to eight bytes of an address can be modified during this operation in the upper and lower word.
e An extended write masked that specified modification to all eight
bytes does not execute a read cycle first but unconditionally writes

the new 64 bits and eight check bits to the designated address. This
is described as a full write cycle.

INTERLOCK CYCLES
The interlock cycles are special memory cycles used for process synchronization. They consist of the interlock read cycle and the interlock
write cycle. The memory controller treats the interlock cycles as a pair
of cycles, with an interlock read masked always followed (an arbitrary
number of cycles after) by an interlock write masked. Interlock read
and write cycles are 32-bit operations. The interlock line on the SBI is
used to coordinate activity between memory controllers. An interlock
timer of 512 bus cycles is started with the acceptance of an interlock
write. If the interlock write is not found, after 512 bus cycles, the inter-

lock line is cleared.

Interlock Read
The interlock read masked cycle is implemented in the same manner
as the read masked cycle, with the following exception. The interlock
152

Main Memory Subsystem

read has a special function code which the memory controller decodes and also monitors the interlock line on the bus to verify any
interlock activity elsewhere in the system. If the interlock line is not
asserted, the memory controller addressed would acknowledge the
cycle and set its interlock line on the SBI until a valid interlock write
has been received.

In the case of a single bit error, the controller corrects the data and
transmits it with the proper tag. If an uncorrectable error occurs, the
read data substitute tag with the bad data would be transmitted and
the memory would rewrite the bad data and bad ECC.
Every commander on the SBI capable of issuing an interlock
command should also assert the interlock line on the bus for one cycle
immediately following the interlock read mask command. This is to
insure cooperation among memory controllers responding to interlock
reads without ambiguity.
Interlock Write
The interlock write masked cycle is similar to the write masked cycle
with the following exceptions:

The set state of the interlock line on the SBI would verify the integrity of
the command prior to acknowledging the cycle and implementing it.
The interlock flip-flop would be cleared and consequently the interlock
line on the bus would be deasserted.
If the interlock line was not asserted, the write interlock command

would not be executed and the interlock sequence fault would be set.

ERROR CHECKING AND CORRECTION (ECC)
The ECC scheme used in the memory subsystem is capable of detecting a single or double bit error. It is also capable of correcting all single
bit errors. This is accomplished by storing eight parity bits, called

check bits, along with the 64 data bits in each memory location. Each

check bitis generated by parity-checking selected groups of data bits
in the given data quadword. When parity is again checked during a
read, an incorrect bit will be detected by the parity-checking logic and

will develop a unique 8-bit syndrome which will identify the bit in error.
Error correction logic may thus correct the bit in error. There are 72

unique syndromes pointing to individual bits in the coded quadword.

MEMORY CONFIGURATION REGISTERS
There are three configuration registers in the memory controller to

provide configuration-dependent information to the operating system

and diagnostic software. These are addressable registers with read
and write access.
153

Main Memory Subsystem

Memory Configuration Register A
Figure 8-3 illustrates memory configuration register A.

31 3029 28 27 26 2524 B 2 2]

615

9 8
MEMORY

SIZE

‘ t——PWR up

PWR DWN

XMT FLT
MLT XMT

S
000

|[TYPE|

0
ILV

ILV
EN

INTLK SEQ ERR
WR SEQ ERR
PAR ERR

Figure 8-3

Memory Configuration Register A

Bits <31:26> SBI Fault Status

Bits <23:22> Power Up Power Down Status
These bits work in conjunction with the Alert line. If the memory is

strapped to inhibit ROM decode, the assertion of AC LO will set the
power down status, clear the power up status and activate the Alert

line. The deassertion of the AC LO signal will set power up status, clear

power down status and assert the Alert line. Writing a one to the active
status bit will clear it and deassert Alert.

Bits <15:09> Memory Size
These bits contain the binary representation of the memory size in 64K
byte increments, zero inclusive. For the 4K chip, bits <12:09> are
used. For the 16K chip, bits <14:09> are used. These bits are read-

only.

Bits <04:03> Memory Type
These bits specify the memory type. This refers to the 4K MOS chip

implementation or the 16K MOS chip implementation. These bits are

Bit <4>

Bit<3>

Description

Error condition, no array cards plugged

4K chip

16K chip

—

read-only.

Error condition, both 4K and 16K chip

in.

array boards are being used.

154

Main Memory Subsystem

00 is 0, the memory is
rleave information. If bit rlea
These bits contain inte0is
ved. Bits 01 and 02
inte
is
em
syst
a 1, the
not interleaved. If bit0 and
interleave write
should be 0. Bit 08 is the
are not used at this time08 is writ
take on
bit
ten to with a one, 00 yswillread
enable bit. When bit the written
as a
alwa
will
08
Bit
is.
data
whatever state bit 00 inwith a 0, interlea
.
ged
bit 00 will be unchan ly soTheit
0. If bit 08 is written to ives its power vefrom
the +5V BAT supp bit will
interleave flip-flop rece
, this
retains its state during battery backup. On a cold start

Bits <02:00> Interleave

come up "0".

Memory Configuration Register B

Figure 8-4 illustrates memory configuration register B.
31 302928 27

MEMORY STARTING ADDRESS

5413121109 8 7

SUBSTITUTE ECC

BYPS
REFRESHI L——ECC
FORCE ERR
r

BIT

MEM INIT STATUS

ENABLE WRITE TO MEMORY
STARTING ADDRESS
FILE INPUT POINTER
FILE OUTPUT POINTER

Figure 8-4 Memory Configuration Register B
Register B contains the following information:

ter)
Pointer (File Read Adddresbes Coun
Bits <31:30> File Outptout the
from the
read
woul
that
address
These two bits point and oper
rol
and
on by the timing contndcommand and data filememory cyclated
depe
,
time
ate
e atthe appropri
logic for starting a new memory busy
also
line. This information is read
the
of
e
ing on the stat
file
the
in
lems
prob
c
logi
rol
useful for diagnosing the file cont
least signifi. path. Bit <31> is the most significant bit, bit <30> is the

Write Address Counter)
Bits <29:28> File Input Pointer (File
buffer (File) is four addresses deep
The memory controlier commandstate
can be read via these two bits.
and the Write Address Counter able file
address into which the comThese bits point to the next avail
g the

cant bit.

ion will be written after acceptin
mand address or data informat
in diagfrom the SBi. These bits assisBitt <29
command address and dataprob
> is
path.
write
file
the
in
nosing the file control logic >lems
is the least significant bit.
the most significant bit, bit <28

155

Main Memory Sub

system

Bits <27:15> Memory Starting

Address

These bits indicate the start
ing address of the memory
controller in
64K byte granularity or incr
ements. These bits are writa
ble and can be
aitered by the system after
power up. During a cold start
the memory
contr

oller would come up with
a default starting address
depending
on the starting address jump
ers in the memory backplane.
A cold start

is defined as a CPU power up
ory power supply. Ther

from inactive battery backup

e are two starting addr

and mem-

ess jumpers in the mem-

ory controller backplan
e, and in a four controller
system the default

starting address assignments

Controller No.

are as follows for cold starts

Starting Address

Jumpers

SA 01SA 00
1

OPEN OPEN

zero

OPEN GND

4 Megabyte

GND OPEN

8 Megabyte

GND GND

12 Megabyte

Also during battery back
up the contents

are saved.

of the starting address bits

Bit <14> Write Enable to Mem
ory Starting Address
This bit must be at a one state
during a write to register B

alter the state of the mem

ory starting address. If bit

writes to register B will leav

in order to

e the starting address unch

<14> is a zero,
anged.

Bits <13:12> Memory Initializa

tion Status
contain the recovery mode

These are read-only bits and
necessary to

information

determine whether or
not the memory has

from battery backup and there

fore contains valid data.

Bit <12>

Bit<13>

recovered

Description

Initialization cycle in process.
means the memory is prese

This

ntly writing a

known data pattern and chec
k code
throughout the storage area.
A command
issued to the array at this time
will

receive a busy response.

Invalid state

156

Main Memory Subsystem

Bit <12>

Bit<13>

Description

This state means the memory contains

valid data. This state after a CPU Power
Fail implies that all memory data was
saved.

This state signifies that initialization

is complete and that the power restoration was from a cold state. No data was
preserved.

Bit <10> Refresh Indication

This bit is used for diagnostic purposes only, and will verify the access

time delay due to refresh collision.
Bit <09> Force ERR

This bit is used in conjunction with bits <07:00>. When it is set, it will
enable the ECC substitute bits to replace the actual check bits for the
ECC computation when operating on an address with SBI bits 3and 12
active. Writing a one sets this bit and writing a zero clearsit.
Bit <08> ECC BYPS

This bit is set to totally bypass (BYPS) the ECC check function. If this
bit is set, the data that is read from the memory will be placed on the
SBI exactly as it is found. Also, no CRD or RDS flag will accompany the
data if it is in error but the error log will continue to operate normally
(register C).

Writing a one sets this bit, writing a zero clears it. This bit is used for
diagnostics only.

Bits <07:00> Substitute ECC Bits

These bits can be substituted for the eight check bits read from the
memory, providing that bit <09> in Register B is set to a one and the
address read contains SBI bits 3 and 12 active. These bits are for
diagnostics only and can be used to simulate any single bit or multiple
bit error, thereby checking the entire ECC path. Writing a one sets the
bits, writing a zero will clear them.

MEMORY CONFIGURATION REGISTERC

Figure 8-5 illustrates memory configuration register C.

157

Main Memory Subsystem

31 3029 28 27

8 7
ERROR ADDRESS

ERROR

0
SYNDROME

' LERROR LOG REQ
HIGH ERR RATE
INH CRD

Figure Figure 8-5

Memory Configuration Register C

This register gathers all the ECC error information:

Bit <30> Inhibit CRD
This bit is used to prevent constant CRD flags

from being sent to the

commander when working in sequential

memory locations with single

operating system. Writing a one to this

bit prevents subsequent CRD

cell failures, thus preventing repeated error

service invocation by the

flags from being transmitted to the comma

nder until such a time as the

commander writes a zero to bit <30>. Howeve

r, in the event an uncor-

rectable error occurs in the memory it would

regardless of the state of this bit.

be reported right away

BIT <29> HIGH ERROR RATE
This bit flags the high error rate in the memory
error occurs between the time the first error

time the error service subroutine was invoked
tem. This bit can be cleared by writing a one.

by setting this bit if an

message was sent and the

by the operating sys-

BIT <28> ERROR LOG REQUEST FLAG
This bit is set when the first error occurs during the memory

controller's response to an SBI read cycle. This would indicate to the error

service subroutine whether the controller has logged an

error during
its operation or not. When this bit is set, any subsequent CRD
reports
to the bus commander will be inhibited. In a multiple memory control-

ler system, this is needed in determining which controller
sent the

error message. This can be cleared by writing a one.

BIT <27:08> ERROR ADDRESS
The SBI longword address at which the first
read error occurred
during memory controller response to an SBI read
command is saved
in these bits. Subsequent error addresses, if they
occur, are not saved
until the first one is serviced.

The address field is described as follows:
(bit order is least to most)

158

Main Memory Subsystem

Bit <08> indicates the word in error.
0 = lower word
= upper word

Bits <20:09> indicate the 4K chip address in error.
Bit <21> indicates the 4K chip array bank in error.
0 = lower 4K chip
1 = upper 4K chip

Bits <23:22> are unused for 4K chip.

Used in 16K chip for two necessary extra chip address bits. All chip
address and bank address bits shift left two.
Bits <27:24> indicate the array card in error.
> ERROR SYNDROME

BIT <7:00
that
These eight bits store the error syndrome of the first error word
The
nd.
comma
read
SBI
an
to
se
respon
in
y
was read from memor
the
ed
servic
syndrome will be saved until the error service routine has
indibe
will
but
saved
be
error. Subsequent error syndromes will not
cated by bit <29>.

MEMORY INTERLEAVING

the non-interleaving
The memory subsystem is capable of operating inves
memaory subsysimpro
eaving
or two-way interleaved mode. Interl
tem throughput on the bus.

ed
In a single memory controller system the starting address is assign
ed
encod
is
tem
subsys
y
memor
the
of
size
The
ap.
bootstr
by the ROM
Array
from the number of array cards plugged into the backplane.
or
indicat
an
gged
misplu
are
boards
boards must be contiguous. If
light would indicate configuration error.

Interleaving can be used to increase the overall speed of the memory

subsystem when there are two memory controllers with equal
amounts of MOS memory on each. The effectiveness of interleaving is
based on the principle that most memory operations are performed on
consecutive memory locations. While one controller is fetching data,
the other controller is available to decode an address for the next
operation. On VAX-11/780, the two memory controllers access alternate quadwords.

With an interleaved memory system, both controllers must have consize,

array
tigucus bus TR select levels (odd and even pairs), the same their
interhave
must
llers
contro
both
the same starting address, and
leaved bits set.

159

Main Memory Subsystem

It is also possible to have two two-way interle

aved memory systems,

four controliers, by following the rules just
listed and assigning the

second interleaved memory system a starting address

cation above the final address of the first interlea

that is one lo-

ved set.

Four memory controliers on one bus may require
reassigning of bus
TR select levels of the other SBI NEXUS.

ROM BOOTSTRAP
A four kilobyte programmable read-only memory

to boot the system
resides in the memory controller and it uses
a 1K x 4, bipolar, high
speed device. The memory is organized as
a 1K x 32 and is assigned
4K byte 1/0 address space. The ROM can be
addressed via the SBI
interface in the memory controlier during system
initialization. All the
address, data and control logic for addressing
the ROM bootstrap is in
the memory controller. The ROM is packag
ed in such a way that ECOs
can be easily handled by providing sockets in
the PROM locations.

ROM access time = 5 bus cycles (with respect to the

160

commander).

161

162

CHAPTER 9

UNIBUS SUBSYSTEM
TION

INTRODUC
y interface
The UNIBUS Subsystem is the hardware developer's primar
drives and
disk
peed
high-s
the
than
to VAX-11/780. All devices other
asynchroan
S,
UNIBU
the
to
ted
connec
are
orts
magnetic tape transp
through
SBI
nous bidirectional bus. The UNIBUS is connected to the y arbitr
ation
priorit
does
the UNIBUS adapter. The UNIBUS adapter

among devices on the UNIBUS.

to the UNIThe UNIBUS adapter provides access from the processor
translatby
y
memor
S
UNIBU
to
and
ers
regist
device
eral
BUS periph
equiSBI
their
to
ts
reques
ing UNIBUS addresses, data, and interrupt

map
valents, and vice versa. The UNIBUS adapter address transiation
map
The
s.
addres
SBl
30-bit
a
to
s
addres
S
UNIBU
translates an 18-bit
t
reques
cessor
nonpro
for
y
memor
system
to
access
direct
provides

UNIBUS peripheral devices and permits scatter/gather disk transfers.

the
The UNIBUS adapter enables the processor to read and writesor
peripheral controlier status registers. In the case of proces
interrupt request devices, this constitutes the transfer.:

tanding
This chapter is organized to provide the reader with an undersUNIBU
S
The
r.
Adapte
S
UNIBU
/780
of the UNIBUS and the VAX-11
S,
UNIBU
the
logic,
r
adapte
S
UNIBU
the
of
ised
subsystem is compr
and associated peripheral devices. Figure 9-1 illustrates the UNIBUS
subsystem configuration.
UNIBUS SUMMARY

The UNIBUS, a high-speed communication path, links together 1/0
devices to the UNIBUS adapter. Device-related address, data, and
control information are passed along the 56 lines of the UNIBUS. The
UNIBUS adapter handlies all communications between the UNIBUS
and the SBI, and fields device-generated interrupts.

The following UNIBUS summary description takes into account the
presence of the UBA, which performs the following UNIBUS functions:
e arbitration
e interrupt fielding

e power fail/restart
e initialization
163

UNIBUS Subsystem

AOO0-A17 { ADDRESS)

DO0-DI5 (DATA]

‘>

C00-CO1 {CONTROL)

MSYN {MASTER SYNC)
SSYN {SLAVE SYNC)

PA-PB (PARITY)
UNIBUS

BR4-BR7 (BUS REQUEST)

DEVICE

UBA

BG4-BG7 (BUS GRANT)
NPR (NONPROCESSOR REQUEST)

NPG (NONPROCESSOR GRANT)
SAC
( SLAVE_
K ACKNOWLEDGE
)
INTR {INTERRUPT)

BBSY (BUS BUSY)
INIT (INITIALIZE)

AC LO (AC LINE LOW)

DC LO [DC LINE LOW)

Figure 8-1

UNIBUS Configuration

For example, the UBA enables the system
to accept device interrupts
and transfer the iequests from the
UNIBUS to the SBI. However, UBA

and SBI operations between the VAX-1
1/780 CPU and UNIBUS are

transparent to the UNIBUS devices.

Communications And Contro!
A master/slave relationship define
s all

communications between devices on the UNIBUS. The devic
e in control of the bus is considered
the master; the device being addres
sed is the slave. Communication
on the UNIBUS is interlocked, that
is, each control signal issued by the
master device must be acknowledg
ed by a corresponding response

from the slave to complete the transf

er.

Bus Request Levels
Each device uses one of five priority
levels for requesting bus control:
Non-Processor Requests (NPR) and
four Bus Requests (BR). The NPR
is used when a device requests a direct
access data transfer to memo-

ry or another device (i.e., a transf
er not requiring processor

tion). Normally, NPR transfers are
made

vice (e.g., disk drive) and memory.

interven-

between a mass storage de-

Two bus lines are associated with
the NPR priority level. The device issues
its request on the NPR line;
the UBA responds by issuing a grant
on the Non-Processor Grant
(NPQ) line.

164

UNIBUS Subsystem

A BR level is used when a device interrupts the VAX-11/780 CPU in
order to request service. The device may require the CPU to initiate a
transfer. Or it may need to inform the CPU that an error condition
exists. Two lines are associated with each of four BR levels. The bus
request is issued on a BR line (BR7-BR4); the bus grant is issued on
the corresponding Bus Grant line (BG7-BG4).
Priority Structure And Chaining

When a device requests use of the bus, the handling of that request
depends on the location of that device in a two-dimension devicepriority structure. Priority is controlled by the priority arbitration logic
of the CPU and the UBA.

The device-priority structure consists of five priority levels: NPRof and
BR7-4. Bus requests from devices can be made on any one the
request lines. The NPR has highest priority; BR7 is the next highest

priority, and BR4 is the lowest. The priority arbitration logic is structured so that if two devices on different BR levels issue simultaneous
requests, the priority arbitration logic grants the bus to the device with
the highest priority. However, the lower priority device keeps its request up and will gain bus control when the higher-priority device
finishes with the bus (providing that no other higher-priority device
issues a BR).

Since there are only five priority levels, more than one device may bea
connected to a specific request level. If more than one device makes
request at the same level, the device closest (electrically) to the UBA
has highest priority. The grant for each BR level is connected to alla
devices on that level in a daisy-chain arrangement (chaining). When
corresponding BG is issued it goes to the device closest to thetheUNIs BG
BUS adapter. If that device did not make the request it permit
device
the
s
reache
BG
the
to pass to the next closest device. When
ts it
preven
and
grant
the
es
captur
making the request, that device
nally,
Functio
chain.
the
in
device
uent
subseq
any
to
from passing on
NPG chaining is similar to BG chaining.
Device Register Organization

The actual transfer of data and status information over the UNIBUS is
accomplished between status, control, and data buffer registers located within the peripheral devices and their control units. All device
registers are assigned addresses similar to memory addresses. These

registers can therefore be accessed by word type memory reference
instructions {i.e., MOVW,

BITW, &etc.).

Control and status functions are assigned to the individual bits withint
the corresponding addressable registers. Since the register conten
165

UNIBUS Subsystem

can be controlied, setting and cleari
ng register bits can control service
operations. Internal device status
may be loaded into the appropriate
register and retrieved when a progr
am instruction addresses that register. Depending on the function,
register bits may be read/write, read
only, or write only. The number
of addressable registers in a device
(and control unit) varies depending
on the device's function.

UNIBUS Line Definitions
The UNIBUS consists of 56 signal
lines which may be divided into

three function groups: bus contro
l, data transfer, and miscellane
ous
signals. The 13 lines of the bus
control group comprise those signal
s
required to gain bus control throu
gh an NPR/BR or for a priorit
y
arbitration to select the next bus
master while the current bus maste
r
is still in control of the bus. The
40 bidirectional lines of the data
transfer group are those signal
s required during data transfers
to or
from a slave device. The miscellane
ous group are the initialization and
power fail signals required on
the UNIBUS. Table 9-1 descr
ibes the

bus signals within each group.

Table 9-1
SIGNAL LINE

UNIBUS Signal Descriptions

DESCRIPTION

Data Transfer Group
Address Lines
(A<17:00>)

These lines are used by the maste
r device to select
the slave (actually a unique memo
ry or device register address). A <17:01> specifies
a unique 16-bit

word; SA00 specifies a byte within

Data Lines

(D<15:00>)

Control

the word.

These lines transfer information betwe

en master and

slave.

These signals are coded by the maste

(C1,C0)

control the slave in one of the four

r device to

possible data

transfer operations specified below
. Note that the
transfer direction is always desig
nated with respect
to the master device.

Data Transfer Designation Descriptio

Data in (DATI): a data word or byte transf
erred into
the master from the slave.
166

UNIBUS Subsystem

Data in Pause (DATIP): similar to DATI except that it
is always followed by a DATO or DATOB to the same
location. The master keeps control of the UNIBUS
during the entire DATIP-DATO sequence.

Data Out (DATO): a data word is transferred out of
the master to the slave.

Data Out Byte (DATOB): identical to DATO except
that a byte is transferred instead of a full word. Address bits A0O determine which byte will be written.
A00=0, iow byte (D07-00) is written. AO0O=1, high
byte (D15-08) is written.

Parity A-B
(PA,PB)
Master Synchronization
(MSYN)

These signals transfer UNIBUS device parity information. PA is currently unused and not asserted. PB,

when true, indicates a device parity error.

MSYN is asserted by the master to indicate to the
slave that valid address and control information (and
data on a DATO or DATOB) are present on the UNIBUS.

Slave Synchronization
(SSYN)

SSYN is asserted by the slave. On a DATO it indicates that the slave has latched the write data. On a
DATI or DATIP it indicates that the slave has assert-

interrupt
(INTR)

This signal is asserted by an interrupting device, after it becomes bus master, to inform the UBA that an

ed read data on the UNIBUS.

interrupt is to be performed, and that the interrupt
vector is present on the data (D) lines. INTR is negated upon receipt of the assertion of SSYN by the UBA
at the end of the transaction. INTR may be asserted
only by a device which obtained bus mastership under the authority of a BG signal.

Priority Arbitration Group

Bus Request

These signals are used by peripheral devices to re-

(BR7-BR4)

quest control of the bus for an interrupt operation.

Bus Grant

These signals form the UBA’s response to a bus re-

(BG7-BG4)

quest.

Only one of the four will be asserted at any time.

Nonprocessor

This is a bus request from a device for a transfer not

Request

requiring CPU intervention (i.e., direct memory ac-

(NPR)

cess).
167

UNIBUS Subsystem

Nonprocessor

This is the grantin response to an NPR.

Grant (NPG)
Select Acknowiedge

(SACK)

SACK is asserted by a bus-requesting device after
having received a grant. Bus control passes to this

device when the current bus master completes its
operation.

Bus Busy

(BBSY)

BBSY indicates that the data lines of the UNIBUS are

in use and is asserted by the UNIBUS master.

Initialization Group
Initialize (INIT)

This signal is asserted by the UBA when DC LO is
asserted on the UNIBUS, and it stays asserted for
ten msec following the negation of DC LO. It is used

to initialize UNIBUS peripherals.

AC Line Low

(AC LO)

This is a signal which indicates that a power failure is
about to occur on the UNIBUS. The assertion of this
signal initiates the UNIBUS power fail sequence of
the UBA and can cause an interrupt to the VAX-

11/780 CPU. It may also be used by peripheral devices to terminate operations in preparation for
power loss.

DC Line Low
(DC LO)

This signal is available from each system power supply and remains clear as long as all DC voltages are
within the specified limits. If an out-of-voltage condition occurs, DC LO is asserted.

THE UNIBUS ADAPTER
The UNIBUS Adapter provides the interface between the asynchronous UNIBUS and the Synchronous Backplane Interconnect in the
VAX-11/780. The UNIBUS Adapter provides the following functions:

® Access to UNIBUS address space (i.e., UNIBUS device registers)
from the SBI
® Mapping of UNIBUS addresses to SBI addresses for UNIBUS DMA
transfers to SBI memory

e Data transfer paths for UNIBUS device access to random SBI memory addresses and high-speed transfers for UNIBUS devices that
transfer to consecutive increasing memory addresses
e UNIBUS interrupt fielding

e UNIBUS priority arbitration

e UNIBUS power fail sequencing

The UNIBUS Subsystem is illustrated in Figure 9-2.
168

UNIBUS Subsystem

SBI
MEMORY

780
CPU

SYNCHRONOUS BACKPLANE INTERCONNECT

UNIBUS
ADAPTER

UNIBUS
DEVICE 1

UNIBUS

DEVICE
n

UNIBUS
DEVICE

UNIBUS
TERMINATOR

Figure 9-2

UNIBUS Subsystem

VAX-11/780 hardware will support a UNIBUS Adapter in one of four
physical address spaces. The UNIBUS adapter maintains two independent address spaces within the Synchronous Backplane
Interconnect I/0 address space. The first area of addressable space is
within the area reserved for all NEXUSs (i.e., UBA, MBA, memory

controller) internal registers. Each NEXUS (UBA) register address
space occupies 8K bytes (16 pages of 512 bytes/page). This address
space contains all control and status registers of the UBA, registers
required for UNIBUS interrupt fielding, and registers required for
mapping UNIBUS device transfers to the SBI address space. The second address space is the UNIBUS address space associated with the

UBA. The UNIBUS address space occupies a total of 256K bytes (512
pages of 512 bytes/page). Figure 9-3 illustrates the SBI I/O address
space.

169

UNIBUS Subsystem

CONFG REG
STATUS REG
SBI MEMORY

CONTROL

REG

DIAG CONT. REG
FMER

ADDRESS SPACE

FUBAR

OTHER ADAPTER

BRRVRS

REGISTERS

BRSVRS

UBA INTERNAL

MAP REG'S

DATA PATH REG'S

REGISTERS

SBI ADDRESS

/ OTHER ADAPTER

BY THE UBA

\ UNIBUS 1/0

SPACE CONTROLLED

REGISTERS

ADDRESS SPACE AND
UNIBUS MEMORY ADDRESS

SPACE

000000

UNIBUS MEM
ADDRESS SPACE
757777(8)

OTHER

1/0 ADDRESS
SPACE

760000(8)

UNIBUS 1/0
ADDRESS SPACE

777777(8)

Figure 9-3

SBI1/0 Address Space

SBI ACCESS TO UNIBUS ADDRESS SPACE
The UNIBUS Address Space (248K bytes of memory space and 8K

bytes of device register space) is accessible as part of the SBI I/0

Address Space. The UBA translates SBl command/addresses to UNI-

BUS command/addresses, thereby giving the software the ability to
read and write UNIBUS device registers using word type memory
reference instructions (MOVW, BITW, etc.).

Device Registers are assigned 170 addresses within the UNIBUS Address Space spanning 760000,—777777,. In VAX-11/780 physical
byte address terms, the device registers occupy address space
201XE000,,—201XFFFF,¢. The hexadecimal digit 3,7,B or F,4 is substituted in place of the X value within the physical address, depending
upon which one of four UNIBUS address spaces the UBA is configured
for (refer to Figure 7-7, SBI Physical Address Space, Chapter 7). Table

9-2 illustrates the

UNIBUS device register address structure.
170

UNIBUS Subsystem

Table 9-2

UNIBUS Device Address Space

UNIBUS ADDRESS

PHYSICAL BYTE

ADDRESS SPACE

(OCTAL)

LOCATIONS (HEX)

UNIBUS 0 Address

760000-777777

2013E000-2013FFFF

760000-777777

2017E000-2017FFFF

760000-777777

201BEO00-201BFFFF

760000-777777

201FE000-201FFFFF

UNIBUS I/0

Space

UNIBUS 1 Address
Space

UNIBUS 2 Address
Space

UNIBUS 3 Address
Space

Table 9-3 illustrates the translation of SBI to UNIBUS transfer opera-

tions involved in accessing the UNIBUS address space.
Table 9-3

SBI FUNCTION

CPU-Initiated Transfer

TRANSFER

UNIBUS FUNCTION

DIRECTION

Read-masked (word

device to UBA

DATI

UBA to device

DATO or DATOB

device to UBA then
UBA to device

DATIP then DATO or
DATOB

or byte)

Write-masked (word
or byte)

Interlock Readmasked then Inter.

locked Write-masked

During such transfers, the UNIBUS Adapter becomes the highest pri-

ority UNIBUS Non-Processor request (NPR) device.
Address And Function Translation

Figure 9-4 shows the SBI command/address format for accessing the
UNIBUS address space for UBAs 0 through 3. Each SBl address (longword address) covers two 16-bit UNIBUS addresses (word addresses). In addition to the SBI address being decoded, the SBI function and byte mask is decoded to determine the word or byte to be
accessed. The SBI to UNIBUS address and command translation is
shown below.

171

UNIBUS Subsystem

28 27 262524 232221 2019 8 17 16 15

LONG WORD ADDRESS

<3=0>T <3:0> ‘Iolojololo[ojo‘ol‘lblo
MASK

FUNC

UBA UNIBUS
ADDRESS DECODE

UNIBUS ADDRESS SPACEO

UNIBUS ADDRESS SPACE 1
UNIBUS ADDRESS SPACE2
UNIBUS ADDRESS SPACE3

0
1
1

1
O
1

UNIBUS
CONTROL
AND
BYTE ADDRESS
ENCODER

UNIBUS

CONTROL

ADDRESS

210

UNIBUS ADDRESS BITS
UA <17:00>

C<1:0>

Figure 9-4

17:02

l I I
.

SBI To UNIBUS Control Address Translation

Table 9-4 illustrates the translation from SBI Mask and Function fields

to UNIBUS Control and Address fields.

Only the function byte mask combinations shown will be valid. All
other function

byte mask combinations addressed to the UNIBUS
address space will be given an ERR confirmation. The UNIBUS ad-

dress space will respond only to word or byte SBI references. Note
that extended transfers cannot be made to either the UNIBUS address
space or the UNIBUS Adapter Registers.

The translation from SBI Mask and Function to UNIBUS control and
byte address is handled by the UNIBUS control and byte address
encoder illustrated in Figure 9-4.

When the VAX-11 software initiates a data transfer, reading from or
writing to a UNIBUS device register, the UBA will recognize the ad-

dress as being an address within the UNIBUS address space and will
pass the lower 16 SBI address bits through to the UNIBUS as UNIBUS
address bits UA <17:02>. The UNIBUS Adapter generates UNIBUS

address bits UA <1:0> and control bits C <1:0> by decoding the SBI
mask and function bits. Table 9-5 shows the relationship of the UNI-

BUS space controlled by UBA #0 to the SBI address space.
172

UNIBUS Subsystem

Table 9-4

SBI Function-Mask Translation To UNIBUS

Control-Address

Function
<3:0>

SBI

Read Mask

Write Mask

Mask
3210

Control
C<1:0>

DATI

Unibus

Address
A <1:0>

0 011
0 010
01 00O
1
1 00
1 0 00

DATI
DATI
DATI
DATI
DATI

0 0
00
10
1
1

0
0

DATOB

0 01O
01 00
1 0 00
0011
11 00

DATOB
DATOB
DATOB
DATO
DATO

DATIP
DATIP
DATIP
DATIP
DATIP

01
1 0
11
00
1 0

Interlock Read Mask
(Sets Interlock
Flip Flop for
DATIP-DATO
Sequence)

0 0 01
0 010
0100
1 000
0 011
1

DATIP

Interlock Write Mask

DATOB

0 01O
0100
1 000
0 011
1100

DATOB
DATOB
DATOB
DATO
DATO

0 0
10
10
0 0

0
1
1
0
1

1
0
1
0
0

SBI To UNIBUS Transfer Failures

If, during a read sequence to the UNIBUS address space, data is
received from the UNIBUS device with UNIBUS PB asserted (UNIBUS
Device Parity Error) then the data will be sent to the SBI as a Read
Data Substitute.

If, for some reason, an access is made to the UNIBUS address space
and the transfer is not completed on the UNIBUS (i.e., nonexistent
device), the following will occur:

Anall-zeroes word will be sent as a read data for a read transfer.

The UNIBUS address bits <17:02> will be stored in the Failed

The bit indicating the cause of failure (UBA Select Time Out or
SSYN Time Out) will be set in the UBA Status Register. Note that
in the case of a Write Transfer to the UNIBUS, the error bit is set at

UNIBUS Address Register(FUBAR).

173

System

UNIBUS And SBI Address Space

30 bit

Address Space

18 bit

Physical Byte Address

{not fo scale)

Unibus Address Space

{Iex)

{(Hex)

18 bit

Unibus Address Space
(Octal)

20100002

20100000

00002

00000

000002

000000

Memory

20100006

20100004

00006

00004

000006

000004

2010000A

Unibus

Address

2010000«

0000A

00008

000012

000010

2010000

Memory

Space

2019000C

N000E.

0000C

100016

000014

20100012

Address

20100010

00012

00010

000022

000020

Space

Other
Adaptor

Vil

Registers

2013DFF6

2013DFF4

3ADFF6

Unibus

2013DFFA

2013DFFR

3DFFA

3IDFF8

Adaptor

2013DFFF

2013DFFC

3DFFE

IDFFC

Registers

20131002

Other

3IDFF4

For

Ilxpansion

757766

757764

(496 pages)

757772

757770

757776

757774

page

512 bytes

2013F000

31002

3E000

760002

760000

2013FK006

2013F004

Unibus

3IE006

3E004

760006

760004

2013 F00K

3E00A

3008

760012

760010

Address

Registers

SO13EOIS

Reserved

2013E00A

Adaptor

Unibus

2013K012

2013F011

I/0

2013F010

[3K013

3F012

3R0II

3K010 | 760023

760022

760021

Space

760020

|w—o

Sfr'g’ge for

Address Space

.
Upper

Other

(10)

16 bit words

/0
Address Space

Note:

These addresses

2013FFF6

2013FFI4

2013FFFA
2013FFFE

refer to UBA ¢,

IFFF6

3FFF4

2013FFFHK

iFFFA

3FFF8

777772

777770

2013FFFC

IFFFF

3JFFFC

777776

777774

777766

777764

walsAsqns SNgINN

Table 9-5

UNIBUS Subsystem

least 13 usec after the command was issued and acknowledged
by the UBA. It will therefore not be immediately known to the
software. If the software has set the SUFFIE (SBI to UNIBUS Error
Interrupt Enable), the setting of UB select Time Out or SSYN Time

Out will initiate an adapter interrupt request (13 usec for SSYN

timeout, 50 usec for select Time Out).

This method gives the VAX-11 software an opportunity to exit gracefully from a transfer failure rather than being trapped out of a program

due to a Read Data timeout. The method is also consistent for read
and write failures.

UNIBUS ACCESS TO THE SBI ADDRESS SPACE
UNIBUS initiated transfers to UNIBUS memory addresses are mapped
by the UBA to SBI addresses on a page-by-page basis, allowing UNI-

BUS data transfers to discontiguous pages of SBI memory. The SBI
uses a 30-bit addressing scheme and a 32-bit wide data path, while
the UNIBUS uses an 18-bit addressing scheme and a 16-bit data path.
The SBI is synchronous, supporting a maximum of 16 NEXUSs while
UNIBUS functions are asynchronous, supporting a large number of
devices.

The UNIBUS Adapter accepts one of two forms of input from the
UNIBUS:

e Hardware-generated interrupts
e Direct memory access transfers

Terminal input, for example, is an interrupt-driven process in which
the DZ-11 (terminal interface) initiates an interrupt sequence. The interrupt service routine for the terminal driver will accept and process
the data resulting from the terminal input. This process is therefore
classified as a non-direct memory transfer.

In contrast, once initiated by the software, an RK06 disk will transfer its
data directly to or from SBI memory via the UBA without processor
intervention. The RK06, therefore, is a direct memory access (DMA)
device. The direct memory access transfer may be further divided into
two groups:

e Random access - access of noncontiguous addresses
e Sequential access - access of sequentially increasing addresses

The UNIBUS adapter can channel data through any one of 16 data
paths for UNIBUS devices performing DMA transfers. The UBA provides a direct data path to allow UNIBUS transfers to random SBI
addresses. Each UNIBUS transfer through the direct data path is
mapped directly to an SBI transfer, thereby allowing only one word of
information to be transferred during an SBI cycle. The UBA provides
175

UNIBUS Subsystem

15 buffered data paths (BDP), each of which allows a sequential access device on the UNIBUS (a device that transfers to consecutive
increasing addresses) access to the SBI in a more efficient manner
than that offered by the direct data path. Each of the BDPs stores data

for the UNIBUS, so that four UNIBUS transfers are performed for each

SBlI transfer, making more efficient use of the SBI and memory. Using
the BDPs, the UBA can support high-speed DMA biock transfer devices such as the RK06 disk subsystem and the DMC-11. The Buffered

Data Paths also allow a UNIBUS device to operate on random longword aligned 32-bit data.

UNIBUS To SBI Address Translation
The UNIBUS Adapter provides for direct memory access transfers to

main memory via the memory controllers connected to the Synchronous Backplane Interconnect. The UNIBUS Adapter translates

UNIBUS memory addresses to SBI addresses through a UNIBUS to
SBI address translation map. The UNIBUS Adapter physically contains 496 (decimal) hardware map registers utilized in mapping UNI-

BUS memory page addresses to SBI page addresses (longwords).
Each map register is assigned an SBI longword address. The map
register contains the SBI page address and the data path required to
transfer data between the UNIBUS and the SBI.

Each UNIBUS address is mapped to an SBI address in three sections:

SBl page address. (one page equals 512 bytes)

Longword within an SBI page. (one longword equals four bytes)

Word or byte within a longword.

NOTE
To avoid confusion between UNIBUS and SBI address bits, UNIBUS address bits will be shown as UA
<bit num> and SBI address bits will be shown as SA
<bit num>.
As illustrated in Figure 9-5, the UNIBUS to SBI page map translates

UNIBUS memory page addresses to any SBI page address. The map
allows the transfer of data to discontiguous pages of SBI memory. The
map translates the nine UNIBUS page address bits (UA<17:09>) to

the 21 SBI page address bits (SA<27:07>).
There are 496 map registers provided to map the entire UNIBUS
memory address space at once, thereby reducing the problem of

register allocation. Each map register corresponds to the UNIBUS
page which is to be mapped. The map registers are available to the

VAX-11 software as part of the SBI /0 address space. These registers
176

UNIBUS Subsystem

ADDRESS

CONTROL

MAP REG NUMBER

MAP\h

3 8

]

2 1

BYTE WITHIN PAGE

— I\

REG

UNIBUS TO SBI
ADDRESS

TRANSLATION
MAP

—
- $BI PAGE ADDRESS
{PAGE FRAME NUMBER!
i21 BITS)

LT
B W N 2O

NUM

494
495

FUNC

SBI COMMAND ADDRESS

MASK

ENCODE

3 '0131‘
I

S8! PAGE ADDRESS (PFN)

MASK i FUNC

Figure 9-5

7 6

[

LONG WORD ADD

UNIBUS To SBI Address Translation

are discussed in detail in the section titled SBI ADDRESSABLE UNIBUS ADAPTER REGISTERS.

UNIBUS address bits UA <08:02> determine the longword within a
page and are seen by the SBI as address bits SA <06:00>. These
seven bits are concatenated with the mapped page address to form
the 28-bit SBI address.

The two low order UNIBUS address bits (UA<01:00>) and the two
control bits (C<1:0>) determine the SBI function and byte mask (F<3:
0>, M<3:0>).

The mask field points to either one or two bytes within the longword
address. The function field selects either read or write and the
associated qualifier. The mask and the function fields are illustrated in
the following table. Table 9-6 illustrates the translation from the UNIBUS control and byte address fields to the SBI function and mask
fields.

177

UNIBUS Subsystem

Table 9-6

UNIBUS Field To SBI Field Translation

UNIBUS

SBI

BYTE
CONTROL

C<1:.0>
DATI

ADDRESS

A<1:0
0 0
0

M<3:0>

FUNC<3:0>>
READ MASK

1.0
DATO

MASK

FUNCTION

3210
00 1 1

1100

WRITE MASK

0
0
0
f
0010

1
f
1100

DATOB

DATIP

followed by
DATO

0100
1000

INTERLOCK READMASK

0
1

1100

OR
0

0
1
1
1100

INTERLOCK WRITE MASK

DATOB

INTERLOCK WRITE MASK

1.0

0
0
0
1
0010
0100

1000

UNIBUS ADAPTER DATA TRANSFER PATHS

Data is transferred between the UNIBUS and the SBI through
one of
the 16 data paths of the UNIBUS Adapter:
1.

The direct data path (DDP) translates each UNIBUS data transac-

tion (DATI, DATIP, DATO, DATOB) directly to an SBI
function for
each UNIBUS word (or byte) transfer, thereby transferring
data
between SBI memory and a UNIBUS device in 16-bit quantities
.

The Buffered Data Paths allow fast, sequential access
UNIBUS
devices to access the SBI in a more efficient manner than
is offered by the Direct Data Path. Each buffered data path (BDP1-15
)
accumulates data and transfers the data as words or

bytes to or

from the UNIBUS device. The BDPs perform quadword transfers
(64 bits) to SBI memory addresses. The BDPs will respond
to
UNIBUS DATI, DATO, and DATOB functions but will not respond

to the DATIP function.

178

UNIBUS Subsystem

The Buffered Data Paths also allow a UNIBUS device to operate
on random 32-bit longword-aligned data.

The data path to be used by a particular device is assigned by the
software when setting up the map registers. The data paths are numbered from DPO to DP15. DPO is the direct data path (DDP) and DP1
through DP15 are the buffered data paths, BDP1 through BDP15 respectively. One or more transferring UNIBUS devices can be assigned
to DPO. No more than one transferring UNIBUS device, however, can
be assigned to any one of the BDPs at any time. If, during a DMA
transfer, the UNIBUS address points to an invalid map register or a
map register that has a parity error within the high order 16 bits, the

UNIBUS transfer will be aborted (SSYN Timeout in the UNIBUS
device), and the bit indicating the problem will be set in the UBA status
register (IVMR or MRPF). Note that for this implementation, the low
order 16 bits of the map register are accessed only when an SBI
transfer is required, and only at that time is parity checked on the low
16 bits of the map register.

Direct Data Path (DDP)

The Direct Data Path (DPO0) translates each UNIBUS data transfer
function (DATI, DATO, DATOB) to a unique SBI function (Read Mask,
Write Mask). The DDP can transfer words or bytes directly between
the UNIBUS and SBI memory. In addition, the DDP allows a UNIBUS
device to interlock its operation with the system by translating a
DATIP-DATO/DATOB UNIBUS sequence to an Interlock Read Mask Interlock Write Mask SBI sequence, thereby setting and clearing the
memory interlock.

Each UNIBUS word (or byte) transfer is translated by the UNIBUS
adapter to an SBI transfer. The UNIBUS transfer does not complete

until the SBI transfer has been completed. The SBI address, function
and byte mask are mapped directly from the UNIBUS address and
control lines, and the state of an internal interlock flip flop in the case
of a DATIP-DATO sequence.

Use of the Direct Data Path

e The Direct Data Path can be assigned to more than one transferring
UNIBUS device.

e The DDP must be used by any device wanting to execute an inter-

lock sequence (DATIP-DATO/DATOB) to the SBI.
e The Direct Data Path must be used by devices not transferring to
consecutive increasing addresses or devices that mix read and write
functions.

e The maximum throughput via the DDP is approximately 400K words
per second:
179

UNIBUS Subsystem

e The DDP is the simplest data path, as far as programming
goes,
since the map registers are the only UNIBUS adapter registers re-

quired to be accessed when initiating a UNIBUS device transfer.

Table 9-7 illustrates the translation of UNIBUS to SBI data transfer
operations.

Table 9-7

UNIBUS-Initiated Transfer Via The Direct Data Path

UNIBUS FUNCTION

TRANSFER

SBI FUNCTION

DIRECTION
DATI

UBA to device

Read-masked (16

bits)
DATO or DATOB

device to UBA

(byte)

Write-masked (8 or

16 bits)

DATIP then DATO or

UBA to device then

DATOB

Interlock Read-

device to UBA

masked then Interlock Write-masked

Buffered Data Path (BDP)
There are 15 Buffered Data Paths, DP1-DP15. The Buffered
Data
Paths are provided for the following reasons:
1.

To be used by fast DMA block transfer devices such as the RKO86,

DMC-11, etc. The BDPs allow UNIBUS devices to make more
efficient use of the SBI and memory and therefore improve sys-

tem performance. The use of BDPs improves the effective UNI-

BUS bandwidth.

To enable word-aligned block transfer devices to begin and

end

on an odd byte of SBI memory. (Byte offset operation
will be

discussed under Byte Offset Data Transfers).

To allow a UNIBUS device to operate on random longwordaligned 32-bit data from SBI memory so that all 32 bits of the
longword are read or written at the same time.

The software assigns a UNIBUS Transfer to a Buffered Data Path when
it sets up the map registers corresponding to the transfer.

The software must assure that no more-than one active transfer is
assigned to a particular BDP at any time.

A UNIBUS device transfer using the Buffered Data Path must have the

following properties:
1.

1t must be a block transfer. (A block is greater than or equal to one
byte). BDP maintenance (purge) will be initiated by the software
180

UNIBUS Subsystem

following each block transfer. The purge operation is a softwareinitiated function of the UBA that clears the BDPs of any remaining
bytes of data. These bytes will be transferred to SBI Memory for

UNIBUS to Memory Write operations or cleared for UNIBUS to
Memory Read Operations.

All transfers within a block must be to consecutive increasing

All transfers within a block must be of the same function type,
Memory Read (DATI) or Memory Write (DATO or DATOB). The
DATIP UNIBUS function will not be recognized by the BDP. A
SSYN Timeout will result in a device attempting a DATIP to a BDP.

addresses.

Each BDP contains eight bytes of DATA buffering, forming a quadword-aligned memory image. DATA is transferred between the UNIBUS and a BDP as words or bytes. Data is transferred between the
BDP and SBI memory as quadwords or between the BDP and an SBI
I/0 register as longwords.

The Buffered Data Paths are transparent to the UNIBUS device. The
device will perform its transfer as if transferring directly to memory.
The operation of the BDPs is described in the following section:
UNIBUS Data Transfers To Memory

As a UNIBUS device transfers data to memory (DATO,DATOB) via a
BDP, the BDP will store the data and complete the UNIBUS cycle. The
Buffered Data Paths are implemented so that a quadword image is
formed in the BDP before an SBI cycle is initiated. When the UNIBUS
device addresses the last byte or word of a physical quadword, the
UBA will complete the data cycle and the BDP wili perform an extended write operation, thereby transferring the stored bytes of data. The
SBI transfer will be completed before recognizing additional UNIBUS
transfers. The BDP will set its Buffer Not Empty (BNE) bit whenever a
UNIBUS Write to the BDP is performed, and clear the BNE bit each
time the SBI transfer is executed. The BNE bit indicates whether or not
valid data is contained in the BDP. Figure 9-6 illustrates a Buffered
Data Path transfer. In this illustration, a Buffered Data Path transfer of
four 16-bit data words to the Buffered Data Path takes place. The
fourth data transfer initiates the extended write transfer of all 64 bits to
memory.

The BDP stores the UNIBUS address of data contained in the BDP.
The BDP stores the UNIBUS address of the current transfer in order to
transfer the remaining bytes to memory at the end of a block transter.
This is the purge function that will be discussed in a later section.
181

UNIBUS Subsystem

BDP BYTES

UNIBUS TRANSFERS

BNE STATE

I
DATA TO ADDRESS

(HEX)

;

3]
DATO

XXXX0

DATO

WORD

WORD 1

WORD

XXXX2

16 8IS

DATO

)

16 BITS

DATO

EMPTY

WORD

XXXX4

BITS

XXXX6

16 BITS

woqo 1

WORD

WORD 3

woqo

WORD 1

wonio

SBI EXTENDED

WRITE TO

MAPPED UNIBUS
ADDRESS{MEMORY)

64 BITS

EMPTY

DATO

XXXX8

16 BITS

WOHRD

1
DATO

XXXXA

16 BITS

DATO
]

WOTD

WORD

_XXXXC

6 BITS

DATO

WORD S

XX XXE

16 BITS

WORD 5

WORD

WOR

WORD 5

WORD

SBI EXTENDED

WRITE TO
MAPPED UNIBUS
ADDRESS (MEMORY)

64 BITS

EMPTY

Figure 9-6

UNIBUS Transfer To Memory
182

)

UNIBUS Subsystem

The BDP also stores the type of function and the state of each byte of
the data buffer (buffer state). The buffer state is transmitted as the SBI

mask bits during the BDP to SBI write cycle so that only the correct
bytes will be written into memory.

UNIBUS Data Transfers From Memory

As a UNIBUS device performs Memory Read operations (DATI) via a
BDP, the BDP tests the state of its data buffers. If the buffers do not
contain data for the UNIBUS transfer, the BDP will initiate an Extend
Read operation to memory. The BDP will then transfer data for the
current cycle to the UNIBUS, thereby completing the UNIBUS cycle,
store the remaining bytes in its buffers, and set the BNE bit. If the data
is available in the data buffers, then the
for the current UNIBUS cycle
BDP will pass the data to the UNIBUS and complete the cycle. The

BDP will prefetch the next quadword of data (Extended Read Transfer)

after each UNIBUS access to the last word of a quadword-aligned
group. The Buffer Not Empty (BNE) bit is cleared by the BDP before
the prefetch and set when the Read Data returns, thereby indicating
the state of the BDP. Figure 9-7 illustrates the Buffered Data Path
transfer from memory to the UNIBUS.

Software Note:

Since the prefetch allows the possibility of the UBA crossing a page
boundary into nonexistent memory, resulting in a 100 usec timeout, it
is recommended that the software allocate an additional map register
following a block. This map register must be invalidated. When the
prefetch crosses this page boundary to the invalid map register, the
prefetch will be aborted immediately, thereby eliminating the 100 usec

timeout. The UBA does not record any UBA or SBI errors that may

occur during the prefetch operations since this is an anticipatory
function based on the next probable address. If an error does occur
then the prefetch will be aborted and the BDP will not be filled with
data. If the UNIBUS device accesses the same BDP again, then the
BDP to SBI read will be initiated and any errors that occur will be
logged at this time.

Byte Offset Data Transfers
The BDPs enable word-aligned UNIBUS devices (devices beginning

transfers on word boundaries and transferring an integral number of

words) to begin and end a block transfer at an ODD byte of SBI memory. To use this feature, the software will set the Byte Offset bit of the
map registers involved during the devices transfer.
183

UNIBUS Subsystem

.
DATI

ADDRESS XXXXO

WORD 2

WORD 0

DATA

WORD 0

woRD 1

BNE

BIT

(EmMPTV!

[

WORD 3

|
|

DATI
XXXX0

]

WORD

XXXUD

WORD

]

WORD 2

WOF*D 3

DATI

WORD 2
WORD 3

DATI

WORD 2

]

WORD 3

OATI

WORD 3

XXXX&

WO’TD

WORD O

LAST DATA WORD
TRANSFER CAUSES
NEW SBI READ

—

READ

/
OATI

WORD

KEE

WORD §

DATI

woRD 7

XXXX

WORD

[

woroa

DATA

DATI

WORD 7

WORD 6

WORD S

wo*oa

DATT

WORD 7

WORD 6

XXXXE

WORD 5

wopi[)a

[

WORD 11
WORD ¢

Figure 9-7

’

]

$BI

¥
|

BNE BIT

wORD 6

XXxXC

—~» READ

{PREFETCH)

WORD 10
WORD 8
i

READ

DATA

UNIBUS Transfers From Memory
184

‘

UNIBUS Subsystem

When the Byte Offset bit is set for a transfer using the BDPs, the BDP
will, in effect, increase the SBI memory address by one byte. The data
will apppear on the UNIBUS in the byte or word indicated by the
UNIBUS Address. The data will appear on the SBI shifted to the left
(increased) by one byte. The UNIBUS adapter will distribute the data,
and adjust the SBI address and byte mask so that the data will get to
or come from the correct memory location. This operation is transparent to the UNIBUS device.

Figure 9-8 shows the relative position of data being transferred
between a UNIBUS device and SBI memory. Figure 9-8 top shows the
relative positions without Byte Offset and Figure 9-8 bottom shows the
position with Byte Offset.

RELATIVE POSITION OF DATA BETWEEN UNIBUS AND SBI

SBI MEM
ADDRESS
SPACE

UNIBUS
ADDRESS
SPACE

WITHOUT BYTE OFFSET

8 -

UBA

——

80P
B8O=0

|
-

m |C

[*]

WITH

m |C

d
b

c
a

BYTE OFFSET

18
14
UBA

F—

BDP

BO=1

g f

SBI ADD

bD LADS
=

UNIBUS
+

1BYTE

b«

EACH LETTERED BROX REPRESENTS 1 BYTE (8 BITS)

Figure 9-8

Relative Position Of Data Between UNIBUS And SBI
185

UNIBUS Subsystem

Purge Operation
The purge operation is a software-initiated function of the UBA in
which the Buffered Data Paths are purged of data and initialized. The

Buffered Data Path used by a UNIBUS device must be purged at the

completion of the device's transfer. The software initiates the purge by

writing a one to the BNE bit of the data path register (DPR) corresponding to the Buffered Data Path to be purged. The UBA will perform

the following, depending on the transfer function that was being
performed by the BDP:
1.

Writes to memory. If there are any remaining bytes of data in the

BDP, this data will be transferred to memory. The UBA will then
clear the BNE bit, function bit and buffer state bits and leave the

BDP in its initialized state. If an error occurs during this transfer,
the Buffer Transfer Error bit of the data path register will be set,
indicating that the data was not successtully transferred to memo-

ry. Software must clear this bit before the BDP can be used again.

If there were no data remaining in the Buffered Data Path, then the

buffer is left in its initialized state.

Reads from memory. The UBA will initialize the BDP by clearing

the BNE bit of the DPR.

Longword-Aligned 32-Bit Random Access Mode
The UNIBUS adapter can be used in a mode so that a UNIBUS device
can operate on random longword-aligned 32-bit quantities without
requiring purge operations. This mode is selected by setting the longword access enable (LWAE) bit 26 of the map register corresponding
to the UNIBUS transfer. A Buffered Data Path must be selected for this
operation.

In this mode, a UNIBUS device must first operate on the low order
word of the longword and then the high order word. An operation is
considered to be a read from memory (DATI) or a write to memory

(DATO) or a read/write (DATI/DATO). The UNIBUS DATIP function
code is not valid for transfers using Buffered Data Paths, and any
device performing the DATIP through a Buffered Data Path will receive

an SSYN timeout (NXM).

The Buffered Data Path will not perform the prefetch operation when

this mode is enabled, thereby allowing for random access of longword-aligned 32-bit quantities. This mode eliminates the need for the
purge operation at the completion of the transfer, providing the UNI-

BUS device operates on both words of the longword and operates on

them in order (i.e., low word, then high word).

Maximum throughput in this mode is approximately 1.7 Mbyte/sec as

illustrated in Figure 9-9.

186

UNIBUS Subsystem

SECOND WORD TO BDP TO SBI
2.6 US MIN————————TM

FIRST WORD TO BDP
e—————800 ns

REC
MSYN

3.4 US MIN. PER WORD (4 BYTES) = 1.17 MBYTE/SEC. MAX.

Figure 9-9

REC
MSYN

Random Access Mode Throughput

The operation of the UBA for the longword-aligned 32-bit access

mode is determined by the function (DATI, DATO/DATOB) and address (A1, A0) received from the UNIBUS and the state of the buffer
not empty (BNE) bit of the data path register, corresponding to the
Buffered Data Path being used for this operation, within the UBA.
(BNE SET = buffer not empty, BNE CLEAR = buffer empty).

The following statements summarize the operation of the UBA for the
longword-aligned 32-bit random access mode of operation.
DATI Functions

SBI reads will occur when a DAT! operation is received and the
Buffered Data Path is empty (BNE = 0).

The BNE bit will be set in response to a successful SBI read
generated by a DATI operation to the low order word (A1 = 0).
Longword data from memory is stored in the Buffered Data Path.
3. The BNE bit will be cleared by a DATI operation to the high order
2.

word (A1 = 1).

If the BNE bit is set, data from the Buffered Data Path will be
returned to the UNIBUS device.

DATO/DATOB Functions

The BNE bit will be set by a DATO or DATOB operation. The data
from the UNIBUS device will be stored in the Buffered Data Path
and the byte mask bit is set within the data path register to
indicate the bytes or words that have been written by the UNIBUS
device.

SBI writes will occur when a DATO operation occurs to the high
order word or when a DATOB operation occurs to the high order
byte. The bytes or words that were written (i.e., those for which the
byte mask bits are set) are written into main memory.

The BNE bit will be cleared after a SBI write operation.
187

UNIBUS Subsystem

The UBA operations per UNIBUS access, as a function of BNE and
received UNIBUS function and address for this mode of operation are:

PRESENT

BNE

STATE

FUNCTIONA1,A0

BNE

UBA OPERATIONS

STATE

WORD, STORE DATA

WORD

DATI

SBIREAD,RETURN LOW

DATI

SBIREAD, RETURN HIGH

1
1

DATI
DATI

0
1

X
X

DATO

STORELOW WORD

DATO

STOREHIGH WORD,SBI

DATO

STORELOW WORD

DATO

STOREHIGHWORD,SBI

WRITE

DATOB

STOREBYTEO

DATOB

STORE BYTE 1

DATOB

STORE BYTE 2

DATOB

RETURN LOW WORD
RETURN HIGH WORD

WRITE

STORE BYTE 3,SBI

1
0
1

0
1

WRITE

STORE BYTE 0

STORE BYTE 1

DATOB

STORE BYTE 2

DATOB

DATIP

STORE BYTE 3,SBI

WRITE

UBADOESNOT

RESPOND (NXM TO
UNIBUS DEVICE) NO

CHANGE
1

DATIP

UBADOESNOT

RESPOND (NXM TO

UNIBUS DEVICE) NO

CHANGE

To enable this mode of operation, Bit 26 of the map register has been
changed to the Longword Access Enable (LWAE) bit. This bit when set

and when a buffered data path is selected, will enable the longwordaligned 32-bit random access mode. It is a read/write bit and is
cleared on initialization.

188

UNIBUS Subsystem

Programming the UBA for longword-aligned random access mode
requires loading the map registers with the following data:
Map register valid, must be set.

BIT<31>

Must be zero.

BIT<30:27>
BIT<26>

LWAE

BIT<25>

Longword access enable, must be set.
ignored during Direct Data Path

transfers.

BIT<24:21> DPDB

Byte offset, must be zero.
Data path designator bits, must use a

buffered data path, BDP1-BDP15. LWAE bit
is ignored when DPDB = 0 (Direct Data
Path).

Page frame number, SBI page address.

BIT<20:00> PFN

The allowed UNIBUS sequences for this mode of operation are:
A1,A0

1. DATI

SBI READ—Low word is returned to UNIBUS device. Both words are stored in BDP.
BNE bit is set.

High word from BDP is returned to UNIBUS

DATI

2. DATO

device. BNE is cleared.

O
-

=2 0O

=+
—

DATO

Low word is written to BDP. BNE bit is set.
SBI WRITE—High word is written to BDP—
then low word and high word are transferred to memory. BNE bit is cleared.

Byte 0 is written to BDP, BNE is set.
Byte 1 is written to BDP, BNE is set.
Byte 2 is written to BDP, BNE is set.
Byte 3 is written to BDP, SBI WRITE

SBI READ-Low word is returned to UNIBUS device. Both words are stored in BDP.
Low word of BDP is written by

UNIBUS device.

High word from BDP is returned to UNIBUS
(]

device.

SBI WRITE-High word of BDP is written by
UNIBUS device and modified longword
is returned to the memory.
189

UNIBUS Subsystem

Additional BDP Software Information
1.

For purge operations in which data is
transferred to memory, the
SBI transfer takes about 2 usec. The
UBA will not respond to Data
Path Register Read during this period
(Busy Confirmation), thus

preventing a race condition when
testing for the BNE bit to be

cleared.
2.

The Buffer Transfer Error bit (BTE)
of the data path registers
indicates that an error occurred during
an operation involving a
buffered data path. Once this bit is
set, UNIBUS transfers using
the BDP will be aborted until the bit
is cleared by the software. The
purge operation does not clear the

BTE bit.

Any purge operations initiated by the softwa

re to BDPs for which
ed are treated by the UBA as

the purge or initialization is not requir

a NO-OP.
4.

A purge operation to Data Path Regist
er 0 (Direct Data Path) is
treated by the UBA as a NO-OP.

INTERRUPTS

SBI interrupts can be generated from two

subsystem: either from a UNIBUS device

sources within the UNIBUS

or from the UNIBUS adapter.

Interrupts from the UNIBUS can occur
at any one of the four request
levels, as determined by the UNIBUS
BR lines. Interrupts from the
UNIBUS adapter will occur at one assign
ed request level. This level is

assigned by backplane jumper.

The UNIBUS adapter contains one reques
t sublevel. The UBA will

therefore require four of the 64 possib
le SBI interrupt vectors (1 for
each of the 4 required levels). The four
vectors will each “point” to a
UBA Service Routine corresponding
to an interrupt request level.

Each UBA service routine must read and
test the BR Receive Vector
Register corresponding to the level of interru
pt:

BRRVR 7 for Req Level 7
BRRVR 6 for Req Level 6
BRRVR 5 for Req Level 5
BRRVR 4 for Req Level 4
From the contents of the BRRVRs, the
UBA service routine will determine whether the interrupt was genera
ted from within the UBA Status
Register, from the UNIBUS device,or from
both, The UBA service routine can then service the interrupt as
determined by testing the con-

tents of the BRRVR.

190

UNIBUS Subsystem

Bit <31>

Bits <15:00>

No service required.

UNIBUS service as indicated by

vector V received from the

UNIBUS device (UNIBUS device
Interrupt Service Routine).

UNIBUS Adapter service required.
Read configuration register and

status register to determine

the service required.

UNIBUS and UNIBUS Adapter service

required.

1. Save the vector V (received
from the UNIBUS device).
2. Read UBA configuration register and status register.

3. Perform UBA service as indicated by configuration and
status register.

4. Index into UNIBUS device ser-

vice routine with vector V.

ved from the UNIBUS device.
V is the vector field of the BRRVR recei
r was not received from
vecto
a
Zero is the null vector indicating that
the UNIBUS device.
from an SBI Interrupt SumSoftware Note: The zero vector resultingprete
d as a Passive Release
mary Read must be reserved and inter
Condition.

Interrupts From The UNIBUS
interrupts to SBI request interThe UBA will translate the UNIBUS BRSwitc
(IFS) bit and the BR Interrupts, providing the Interrupt Fielder ol hregis
ter are set. The assercontr
rupt Enable (BRIE) bit of the UBA
interrupt transaction
SBI
an
te
initia
will
tion of the SBI request lines
ce routine. This routine will then
vectoring to the UBA interrupt servi
VR) corresponding to the
read the BR Receive Vector Registerthe(BRR
BRRVR command, the
read
level of the interrupt. On receiving

UBA will test that the following conditions are true:

is as1 The UNIBUS BR line corresponding to the BRRVR number
2

serted.

The BRRVR does not contain an aiready valid vector.
UNIBUS AC LO is not asserted.

If all of the three conditions are met, then the UBA will issue
191

the

UNIBUS Subsystem

UNIBUS Bus Grant and comp
lete the UNIBUS interrupt trans
action.
The BRRVR is loaded with the
interrupt vector by the successful
com-

pletion of the interrupt trans
action. The device vector recei
ved during
the transaction will be sent as
the read data to the BRRVR Read
Com-

mand. If a UBA interrupt
is active then the vector will
be sent as a
negative quantity (bit 31 sent
as a one).

The BRRVR is cleared by the
successful completion of the
SBI Read
Data Cycle, otherwise the vecto
r is saved and the BRRVR remai
ns full.
If conditions 1,2,3 are not met
then the contents of the BRRV
R (either
the stored vector, from a previ
ously failing SBI read data
cycle, or

zero) will be sent as read data.
If a UBA interrupt is active then
bit 31
will be sent as a one.

The foliowing sequence is perf

ormed for UNIBUS device inter

rupts:

Abusrequestline is asserted

The UNIBUS adapter asser
ts the SBI request line, corr
esponding
to the UNIBUS BR line, to
initiate the interrupt transactio
n in the

When the interrupt summary
read corresponding to the abov
e

by the UNIBUS device.

CPU.

request level is seen by
the UNIBUS adapter, the
UNIBUS adapter
asserts the request sublevel
assigned to the UBA.

The CPU will then transfer
control to the UNIBUS adap
ter
interrupt service routine.

The UNIBUS interrupt service

routine will execute aread to
the BR
sponding to the level of interr
upt.

receive vector register corre

The UNIBUS adapter will issue
the UNIBUS Bus Grant corre
sponding to the ievel of the

interrupt being serviced provi

following conditions are met:

ding the

Adapter interrupt is not pendi

ng; BR
R is asserted; the BRRVR does
not

line corresponding to the BRRV
contain a previous vector.

The UNIBUS interrupt trans
action is completed, the vecto
r is
loaded into the corresponding
BRRVR, and the vector is given
to
the UNIBUS Interrupt Service
Routine as a Read DATA.
The BRRVR will be cleared
when the ACK Confirmation
is re-

ceived for the Read DATA.

The UNIBUS interrupt servi
ce routine will then dispatch
to the
UNIBUS device service routi
ne (or service the UBA) as indic
ated
by the received interrupt vecto
r.

192

UNIBUS Subsystem

NOTE

The UNIBUS adapter interrupt service routine
(UBASR) is the routine that will interface the CPU
interrupt process to the individual UNIBUS device
service routines. This routine will provide the additional level of dispatch required for UNIBUS-initiated
interrupts.

Failure To Complete The UNIBUS Interrupt Transaction

If for some reason, the UNIBUS initiated an interrupt transaction and
then fails to complete (i.e., passive release), the interrupt vector will
not be loaded into the interrupt vector register. The following mechanism will allow the UNIBUS interrupt service routine to gracefully exit.
The idle state of the BRRVR is zero. If, when reading the interrupt

vector register, the UNIBUS interrupt service routine receives the zero
vector, it will log an error (if desired) and return from the service
routine.

Once successfully loaded, the BRRVR will maintain the interrupt vec-

tor until an ACK confirmation to the BRRVR Read Data has been
received, or an Adapter Init sequence is initiated. If the ACK
confirmation is not received for the Read Data then the BRRVR full bit
will not be cleared, and subsequent reads to that BRRVR will result in
the stored vector being returned for the Read Data until ACK is received for the Read Data.

Interrupts From The UNIBUS Adapter To The SBi

When the UNIBUS adapter interrupt enable bit is set, and a condition
warranting an interrupt occurs in the UNIBUS Adapter, the following
sequence occurs:

The UNIBUS adapter asserts its assigned request line.

When the Interrupt Summary Read, corresponding to the above
request level, is seen by the UNIBUS adapter, the request
sublevel assigned to the UNIBUS adapter is sent to the CPU as an
Interrupt Summary Response.

With this information, request level and request sublevel, the CPU
can dispatch to the UNIBUS adapter service routine, which wil
then read the BR Receiver Vector Register corresponding to the
level of interrupt. The BRRVR will contain a negative value (bit 31
set).

The UBA service routine will detect the negative value and branch
to a routine that will read the Configuration Register and Status
Register to determine the service required.
193

UNIBUS Subsystem

The request line will remain asserted

until all conditions (bits of the
UNIBUS adapter status register) have been
cleared by the software.
UNIBUS ADAPTER (NEXUS) REGISTER SPACE

Each NEXUS register address space
occupies 16 pages (512
bytes/page) of Synchronous Backplane
Interconnect I/0 address

space. The address location of the UNIBU

S adapter is determined by

the transfer request priority number assign
ed to the adapter. The

transfer request number is determ
ined by electrical jumpers on the

NEXUS backplane and may vary from one

next.

system configuration to the

Table 9-8 illustrates the physical base addres
s and SBI base address
for a NEXUS assigned to any one of the SBI
transfer request numbers.

Table 9-8

Transfer Number Address Assignment

SBI TRANSFER

ADDRESS BASE
PHYSICAL(HEX)

REQUEST NUMBER

20000000

20002000

20004000

20006000

20008000

2000A000

2000C000

2000E000

20010000

20012000

20014000

20016000

20018000

2001A000

2001C000

2001E000

Table 9-9 lists each of the UNIBUS Adapte
r registers and its associated physical address offset.

Table 9-9

UNIBUS Adapter Register Address Offset

UNIBUS

BYTE OFFSET

ADAPTER REGISTER

(PHYSICAL HEX)

Configuration Register

UNIBUS Adapter Control Register

194

000

004

UNIBUS Subsystem

UNIBUS Adapter Status Register

008

Diagnostic Control Register
Failed Map Entry Register

00C

Failed Map Entry Register

018

Buffer Selection Verification Register 0
Buffer Selection Verification Register 1
Buffer Selection Verification Register 2
Buffer Selection Verification Register 3

020

010

Failed UNIBUS Address Register

014

Failed UNIBUS Address Register

Buffer Receive Vector Register 4
Buffer Receive Vector Register 5
Buffer Receive Vector Register 6
Buffer Receive Vector Register 7

01C
024

028

02C
030

034
038

03C

Data Path Register 0
Data Path Register 1

040

Data Path Register 14
Data Path Register 15

078

044

07C
080

Reserved

7EC

Reserved

Map Register 0
Map Register 1

800

Map Register 494
Map Register 495

EBS8

804

EBC
ECO

Reserved

EFC

Reserved

for
The offset within the UNIBUS Adapter Address Space istheshown
al
physic
to
t
respec
with
rs
registe
r
adapte
S
UNIBU
each of the
S
UNIBU
other
all
of
ses
address. As described in Table 9-9, the addres
by
s
addres
r
registe
ration
configu
Adapter Registers are relative to the
195

UNIBUS Subsystem

an offset. The base address
of the configuration register is
the physical base address described in
Table 9-8, Therefore, the byte
offset for
the configuration register in Table
9-9 is 000.

SBI ADDRESSABLE UNIBUS ADAP
TER REGISTERS
The UNIBUS adapter registers
occupy eight pages of the SBI
I/0
address space. These registers
fall into four categories: map regist
ers,
data path registers, interrupt
vector registers and control and
status
registers. The UNIBUS adapt
er registers are

all 32-bit registers and

can only be written as longw
ords. These registers will,
however, re-

spond to byte or word read
commands. These registers
will also respond to the Interlock Read—
Interlock Write sequence
but will not

affect the interlock of the SBI.
The following sections discuss
the function and content of each of the UNIB
US adapter registers.

Configuration Register (CNFGR)
The configuration register conta
ins the SBI fault bits, the UNIB
US
adapter and UNIBUS environmen
t status bits, and the UNIBUS adap-

ter code. This register is requi

red to interface with the SBI. Figur

e 9-10

illustrates the configuration regist

er.

313029282726

2322

1817 16

7.6

6§

UNIBUS ADAPTOR
CODE
UNIBUS INIT COMPLETE
UNIBUS POWER DOWN

UNIBUS INIT ASSERTED
ADAPTOR POWER UP

ADAPTOR POWER DOWN
TRANSMIT FAULT

MULTIPLE TRANSMITTER FAULT
INTERLOCK SEQUENCE FAULT
UNEXPECTED READ DATA FAULT

WRITE SEQUENCE FAULT
PARITY FAULT

Figure 9-10

Configuration Register Bit Configuratio

The contents of the Configuration Regist

er are as follows:

Bits <31:27> SBI fauits
These bits are set when the UNIB
US adapter detects specific fault

conditions on the SBI. These bits canno

t be set once FAULT has been

asserted. The negation of FAUL
T and the disappearance

of the fault
conditions clear the bits. The settin
g of any of the bits <31:26> will

Cause the UNIBUS adapter to assert

196

the FAULT signal on the SBI.

UNIBUS Subsystem

Bit <31> Parity Fault (PARFLT)

PAR FLT is set when the UNIBUS adapter detects an SBI parity error.
Bit <30> Write Sequence Fault (WSQFLT)

a Write Masked,
WSQ FLT is set when the UNIBUS adapter receivescomm
and which is
Extended Write Masked, or interlock Write Masked
not immediately followed by the expected write data.
Bit <29> Unexpected Read Data Fault (URD FLT)

which a
URD FLT is set when the UNIBUS adapter receives datadforcomm
and
Read Masked, Extended Read, or Interlock Read Maske
has not been issued.

Bit <28> Interlock Sequence Fault (1ISQ FLT)

a UNIBUS
ISQ FLT is set when an Interlock Write Masked command or
a
t
address space is received by the UNIBUS adapter withou previous
Interlock Read Masked command.

Bit <27> Multiple Transmitter Fault (MXT FLT)

on the SBI
MXT FLT is set when the UNIBUS adapter is transmittingmatch
those
not
and the IB bits transmitted by the UNIBUS adapter do tes a multip
le
indica
ence
latched from the SBI. The lack of correspond
transmitter condition.

Bit <26> Transmit Fault (XMT FLT)

XMT FLT is set if the UNIBUS adapter was the transmitter duringthea
detected fault condition. When the software subsequently reads
SBlin
configuration and status registers of each of the NEXUSs on the
be
will
r
adapte
S
UNIBU
the
fault,
the
of
source
the
y
order to identif
identified as that source if bit 26 is set.
Bits <25:24> Reserved and Zero

Status
Bits<23,22,18,17,16> are UNIBUS Subsystem Environmentaptl Enable
Interru
n
uratio
Config
the
and
set
are
bits
Bits. If any of these
S adapter
bit (CNFIE) of the control register is also set, then the UNIBU
the UNIto
ed
assign
level
the
at
will initiate an SBI interrupt request
BUS adapter.

Bit <23> Adapter Power Down (AD PDN)

s AC LO.
This bit is set when the UNIBUS Adapter power supply assert
the Adapter
It is cleared by writing a one to the bit location or when
Power Up bit is set.

Bit <22> Adapter Power Up (AD PUP)

Itis cleared by
This bit is set by the negation of power supply AC LO. Adapt
er Power
the
of
setting
the
by
writing a one to the bit location or
Down bit.

Bits <21:19> Reserved and Zero
197

UNIBUS Subsystem

Bit <18> UNIBUS INIT Asserted (UB INIT)
The assertion of UNIBUS Init will set

this bit. Itis cleared by the setting
of the UNIBUS Initialization Complete
bit (UBIC) or by the writing of a

one to this bit location.

Bit <17> UNIBUS Power Down (UB PDN)
This bit is set when UNIBUS AC LO is
asserted. It indicates that the
UNIBUS has initiated a power down
sequence. The setting of the
UNIBUS initialization complete bit or writing
a one to this location will
clear UB PDN.
Bit <16> UNIBUS Initialization Compil
ete (UBIC)
This bit is set by a successful comple
tion of a power up sequence on
the UNIBUS. It is the last of the status
bits to be set during a UNIBUS

adapter initialization sequence, and
it can be interpreted to mean that
the UNIBUS adapter and the UNIBU
S are ready. The assertion of
UNIBUS AC LO or UNIBUS INIT, or
the writing of a one to this bit
location will clear UBIC.

Bits <15:08> Reserved
Bits <7:0> Adapter Code
These bits define the code assigned
10 shows the bit assignment.

to the UNIBUS adapter. Table 9-

Table 9-10

Adapter Code Bit Assignment

BIT NUMBER

7 [ 6 | s{alal2

SPACE

;

0
!

Adapter code bits 1 and 0 are deter

indicate the starting address of the

mined by backplane jumpers and
UNIBUS Address space associated

with the UNIBUS Adapter, as shown

198

in Table 9-11.

UNIBUS Subsystem

Table 9-11

Selectable UNIBUS Starting Addresses

UNIBUS
ADDRESS
SPACE

STARTING ADDRESS OF THE UNIBUS
ADDRESS SPACE, BASE 16 (PHYSICAL

BYTE ADDRESS)

20100000(16)
0
(16}
2014000

0
1

20180000(16)
201C0000{16)

2
3

Note that the lowest two bits of the Configuration Register (Vb and Va)

correspond to SBI address bits 16 and 17.
Control Register (UACR)

The UNIBUS Adapter Control Register enables the software to control

operations both on the UNIBUS Adapter and on the UNIBUS. All bits
except for the Adapter INIT bit are set by writing a 1 and cleared by
writing a 0 to the bit location. The Adapter INIT bit is set by writing a
one to the bit location and is self clearing. Figure 9-11 shows the
Control Register bit configuration.

6 5 4 32 10

313029282726
4132|110

MAP REGISTER

DISABLE BITS

INTERRUPT FIELD SWITCH
BR INTERRUPT ENABLE

UNIBUS TO SBI ERROR INTERRUPT ENABLE

SBI TO UNIBUS ERROR INTERRUPT ENABLE
CONFIGURATION INTERRUPT ENABLE
UNIBUS POWER FAIL
ADAPTOR INIT

Figure 9-11

Control Register Bit Configuration

The contents of the control register are as follows:
Bit <31> Reserved and zero.

Bits <30:26> Map Register Disable <4:0> (MRD)

This field of five read/write bits disables map registers in groups of 16,
according to the binary value contained in the field. The MRD bits
prevent double addressing if UNIBUS memory is used. This field is
loaded with a binary value equal to the number of 4K word units of
memory attached to the UNIBUS, as shown in Table 9-12.
199

UNIBUS Subsystem

Table 9-12

MRD <4:0>

Map Register Disable Bit Functions

AMOUNT OF UNIBUS

MEMORY

MAP REGISTERS

(WORDS)

DISABLED

00000

NONE

00001

0 1O 15 (10)

00010

0 TO 31 (10}

00011

12K

0 TO 47 (10}

11110

120K

0 70 480 (10)

124K

0 TO 495 (10)

DMA transfers to addresses controlled by disabled map

registers are

not recognized by the UNIBUS adapter. No error
bits are set and no

transfers are initiated. However, SBI access to disabled

is permitted. The MRD field is initialized as zero, with

enabled.

map registers

all map registers

Bit <25:07> Reserved and Zero

Bit <6> Interrupt Field Switch (IFS)
This bit determines whether interrupts from a UNIBUS
device
UNIBUS outside of the UNIBUS adapter will be fielded by the

CPU or passed to the UNIBUS inside of the UNIBUS adapter.
is set (1), then the interrupt will be passed to the SBI, if the

on the

VAX-11
If the bit

BR Interrupt

Enable bit of the control register is set. If the bit is cleared
(0), then the
interrupt will be passed to the UNIBUS inside of the
UNIBUS adapter,
where it is in effect ignored.

The power up state of the IFS bit is 0. The bit is also
cleared by the
adapter unit and SBI dead signals. This bit and BRIE
must be set by
the software to receive UNIBUS device interrupts.

Bit <5> Bus Request Interrupt Enable (BRIE)

When this bit is set it allows the UNIBUS adapter to pass interrupts
from the UNIBUS to the VAX-11 CPU. The power up state
of the BRIE
bit is 0. The bit is also cleared by the Adapter INIT, SBI UNJAM,
and
SBI Dead signals. This. bit and IFS must be set by the software
to
receive UNIBUS device interrupts.

Bit <4> UNIBUS to SBI Error Field Interrupt Enable (USEFIE

)
The USEFIE bit enables an interrupt request to the VAX-11 CPU
ever any of the following Status Register bits is set on

RDTO (Read Data Time Out)
RDS (Read Data Substitute)

200

when-

a DMA transfer.

UNIBUS Subsystem

CXTER (Command Transmit Error)
CXTO (Command Transmit Time Out)
DPPE (Data Path Parity Error)
IVMR (Invalid Map Register)
MRPF (Map Register Parity Failure)

The power up state of the USEFIE (UNIBUS Error Field Interrupt

Enable) bit is zero. SBI UNJAM and Adapter Init will clear the bit.

Bit <3> SBI To UNIBUS Error Field Interrupt Enable (SUEFIE)

If this bit is set, the UNIBUS adapter will generate interrupt requests to
the VAX-11 CPU when one of the two bits in the SBI to UNIBUS data
transfer error field is set.

UBSTO (UNIBUS Select Time Out)
UBSSYNTO (UNIBUS Slave Sync Time Out)

The power up state of this bit is zero. SBI UNJAM, SBI Dead, and

Adapter INIT will clear the bit.

Bit <2> Configuration Interrupt Enable (CNFIE)
If this bit is set, the UNIBUS adapter will initiate an interrupt request to

the VAX-11 CPU whenever any one of the environmental status bits of
the configuration register is set.

AD PDN (Adapter Power Down)
AD PUP (Adapter Power Up)
UB INIT (UNIBUS INIT Asserted)
UB PDN (UNIBUS Power Down)

UBIC (UNIBUS Initialization Complete)

The power up state of this bit is set (1). The bit is cleared by Adapter
INIT, SBI UNJAM, and SBI Dead.

Bit <1> UNIBUS Power Fail (UPF)

When this bit is set, it initiates a power fail sequence on the UNIBUS,
asserting AC LO, DC LO, and INIT. The software uses this bit to initialize the UNIBUS. The UNIBUS will remain powered down as long as
UPF is set. Thus the software can initialize the UNIBUS by setting and

then clearing the UPF bit.

Bit <0> Adapter INIT (ADINIT)

When this bit is set it will completely initialize the UNIBUS adapter and
the UNIBUS. The map registers, the data path registers, the status
register, and the control register will be cleared. The UNIBUS adapter
will initialize all of its control logic, and will generate a power fail sequence on the UNIBUS. The adapter initialization sequence takes only
500 usec to complete, while the UNIBUS power fail sequence requires
25 msec.

Only the configuration register and the diagnostic control register can
be read during the adapter initialization sequence. And only the con201

UNIBUS Subsystem

figuration register, the diagnostic control register, and the control
ister can be written during the adapter initialization sequence.

reg-

Once the sequence has been completed, all UNIBUS adapter registers

can be accessed. However, the UNIBUS cannot be accessed until the

UNIBUS initialization sequence has been completed as well. The soft-

ware can test for this condition by reading the UBIC bit of the configu-

ration register, or by setting the configuration interrupt enable
bit of
the control register and looking for the interrupt generated by
the
setting of the UBIC bit. Note that the assertion of UNIBUS INIT (UBIN-

IT) can also initiate an interrupt . The Adapter INIT bit can be set by

writing a one to the bit location, and it is self-clearing.

Status Register (USAR)
The UNIBUS Adapter Status Register contains program status
and

error information. Bits <27:24> are read only bits which are
set and

cleared by operations within the UNIBUS adapter. Bits <10:00> can
be read and cleared by writing a one to the appropriate bit location.

Specific conditions which occur on the UNIBUS adapter will set these

bits. Writing a zero has no effect on any of the bits. Figure 9-12 shows
the Status Register bit configuration.

27262524

BRRVR 7 FULL

BRRVR 6 FULL
BRRVR & FULL
BRRVR 4 FULL

READ DATA TIMEOUT
READ DATA SUSTITUTE
CORRECTED READ DATA

COMMAND TRANSMIT ERROR
COMMAND TRANSMIT TIMEOUT
DATA PATH PARITY ERROR

INVALID MAP REGISTER
MAP REGISTER PARITY FAIL

LOST ERROR BIT
UNIBUS SEL TIMEOUT

UNIBUS SSYN TIMEOUT

Figure9-12

Status Register Bit Configuration

202

UNIBUS Subsystem

The contents of the status register are:

Bits <31:28> Reserved and Zero

Bits <27:24> BR Receive Vector Register Full

the state of the SBI addressable BR receive vector
These bits indicate
registers. Each bit is set when the interrupt vector is loaded into the

corresponding BRRVR during a UNIBUS interrupt transaction, provid-

ing that the SBI processor is fielding UNIBUS device interrupts.
Each bit is cleared by the successful completion of a read data
transmission following a read BRRVR command. The software will see
these bits set only after a read data failure has occurred during the

execution of the read BRRVR command, and the UNIBUS interrupt

vector has been saved by the UNIBUS adapter.
Bit 27=BRRVR 7 Full
Bit 26=BRRVR 6 Full
Bit 25=BRRVR 5 Full
Bit 24=BRRVR 4 Full

Bits <23:11> Reserved and Zero

The remaining bits identify specific data transfer errors. They are read
and write-one-to clear bits.

Bit <10> Read Data Time Out (RDTO)

The UNIBUS Adapter sets the Read Data Time Out bit when the following conditions are met: When a UNIBUS device has initiated a DMA
read transfer, when the UNIBUS adapter has successfully transmitted
a read command on the SBI, and the SBI memory has not returned the
requested data within 100 usec, and when the UNIBUS device has not
timed out. Note that the normal UNIBUS timeout is 10-20 usec, and
that after 10-20 usec, the UNIBUS device will set its nonexistent memory bit. Thus, the Read Data Time Out bit will be set on the UNIBUS
adapter status register only if the UNIBUS device timeout function is
inoperative, or takes more than 100 usec.

Bit <9> Read Data Substitute (RDS)
This bit is set if a read data substitute is received in response to a

UNIBUS to SBI read command (DMA read transfer). No data will be
sent to the UNIBUS device, and when the device timeout occurs, the
nonexistent memory bit will be set within the UNIBUS device.
Bit <8> Corrected Read Data (CRD)

The UNIBUS adapter sets this bit when it receives corrected read data
in response to an SBI read command during a DMA read transfer. The
setting of this bit has no effect on the completion of the UNIBUS
transfer.
203

Bit <7> Command Transmit Error (CXTER)
The UNIBUS adapter sets this bit when it receives an error confirma-

tion in

response to an SBI command transmission during a DMA

transfer.

Bit <6> Command Transmit Timeout (CXTO)
This bit is set when a command transmission times out during a UNIBUS to SBI data transfer or during a BDP to SBI write or purge.

Note that the normal UNIBUS timeout is 10 usec, which will result in
the UNIBUS device setting its nonexistent memory bit and will also

abort the UBA to SBI transfer. The CXTO bit will therefore only be set
for a UNIBUS to SBI transfer if the device’s timeout mechanism is
inoperative. The UBA will, however, attempt to perform a BDP to SBI

write or purge operation for the full 100 usec timeout period if busy or
no response confirmation is received, thereby setting the CXTO bit.

The bit is not set for a prefetch operation since the prefetch works by

anticipated addresses (i.e., the next address) and any errors resulting
from the prefetch are considered to be invalid.

Bit <5> Data Path Parity Error (DPPE)
This bit is set when a parity error occurs in the Buffered Data Path
during either a UNIBUS to BDP DATI, a BDP to SBI write, or a purge.

Note that during a purge operation the address to be mapped is aiso

obtained from the BDP and it is possibie for a parity error to occur

when fetching the address from the BDP. This parity error will also set
the DPPE bit and abort the SBI transfer that would have taken place.
Also note that any condition that sets the DPPE bit will also set the
buffer transfer error bit in the DPR of the Buffer Data Path in which the
error occurred, thereby aborting any SBI transfers in progress and

any future UNIBUS transfers through that BDP until the buffer transfer

error is cleared.

Bit <4> Invalid Map Register (IVMR)
The UNIBUS adapter sets this bit during a DMA transfer or purge
operation when the UNIBUS address points to a map register which

has not been validated by the software, or when the DMA transfer
crosses an SBI page boundary for which the map register has not
been validated.

Bit <3> Map Register Parity Failure (MRPF)
This bit is set with the occurrence of a map register parity failure when

a UNIBUS address is being mapped to an SBI address on a DMA

transfer operation or a purge operation.

Seven of the bits just listed (RDTO, RDS, CXTER, CXTO, DPPE, IVMR,

and MRPF) form an error-locking field. If any one of these bits is set,

the field is locked until the bit indicating the error is cleared. The Failed

204

UNIBUS Subsystem

Map Entry Register (FMER) is also locked and unlocked with this field.
And the setting of any of these bits will cause the UNIBUS adapter to
initiate an interrupt request if the interrupt enable bit for the UNIBUS to
SBI data transfer error field (USEFIE) in the control register is set.
Bit <2> Lost Error Bit (LEB)

The UNIBUS adapter sets this bit if the locking error field is locked and
another error within this field occurs. The lost error bit does not initiate
an interrupt request.

Bit <1> UNIBUS Select Time Out (UBSTO)
The UNIBUS adapter sets this bit if it cannot gain access to the UNIBUS within 50 usec in the execution of a software initiated transfer
(SBI to UNIBUS transfer). When UBSTO is set it indicates that the
UNIBUS Adapter has issued NPR on the UNIBUS but has not become
bus master. This condition indicates the presence of a hardware problem on the UNIBUS. The UNIBUS may be inoperative, or one device
may be holding it for extended periods. Note that if the UNIBUS does
become inoperative, it may be possible to clear the problem with the

assertion of UNJAM on the SBI, by setting and clearing of the UNIBUS
power fail bit (control register bit 1) or by setting Adapter INIT (control
register bit 0).

Bit <0> UNIBUS Slave Sync Time Out (UBSSYNTO)

This bit is set when an SBI to UNIBUS transfer (software-initiated
transfer) times out during the data transfer cycle on the UNIBUS. The
timeout occurs after 12.8 usec. UBSSYNTO indicates a transfer failure
resulting when a nonexistent memory or device on the UNIBUS is
addressed.

The two bits just discussed, UBSTO and UBSSYNTO, form an SBI to
UNIBUS transfer error-locking field. They are set by the occurrence of
the conditions mentioned and cleared by writing a (1) to the bit location. The setting of either bit will cause the UNIBUS adapter to make
an interrupt request on the SBI if the SBI to UNIBUS error interrupt
enable bit (SUEFIE) in the control register is set. The setting of either
UBSTO or UBSSYNTO will lock the failed UNIBUS address register
(FUBAR), thus storing the high 16 bits of the UNIBUS address
identified with the failure. The FUBAR will remain locked until the
UBSTO and UBSSYNTO bits are cleared.

Diagnostic Control Register (DCR)

The Diagnostic Control Register provides control and status bits which
aid in the testing and diagnosis of the UNIBUS adapter. The bits of this
register, when set, wiii defeat certain vital functions of the UNIBU

adapter. The DCR is therefore not intended for use during normal
system operation. Figure 9-13 shows the bit configuration of the DCR.
205

UNIBUS Subsystem

313029282726

242322 21

UNUSED

1918

UNUSED

1616

UNUSED

SAME AS CONFIGURATION REGISTER BITS <23:00>
SPARE

MICROSEQUENCER

DISABLE

INTERRUPT

DEFEAT

DATA
PATH
PARITY

DEFEAT
MAP

PARITY

Figure 9-13

Diagnostic Control Register Bit Configuration

Bit <31> Spare
This read/write bit has no effect on any UNIBUS adapter operation. It
can be set by writing a one and cleared by writing a zero to the bit
location. SBI Dead, Adapter INIT, and a power up sequence on the

UNIBUS adapter will clear this bit.

Bit <30> Disable Interrupt (DINTR)
When it is set, this bit will prevent the UNIBUS adapter from recognizing interrupts on the UNIBUS. It is useful in testing the response

of the
UNIBUS adapter to the passive release condition during a UNIBUS
interrupt transaction. This bit is set by writing a one and cleared
by
writing a zero to the bit location. SBI Dead, Adapter INIT, and the
power up sequence on the UNIBUS adapter will also clear DINTR.

Bit <29> Defeat Map Parity (DMP)
When it is set, this read/write bit will inhibit the parity bits of

the map

registers from entering the map register parity checkers.
The map
register parity generator checkers generate and check parity on
eight
bit quantities. Each parity field (eight data bits and one parity
bit) is

implemented so that the total number of ones in the field is odd.

For example, if bits <7:0> of a map register equal zero, then
the parity
bit equals one. However, if the DMP bit is set, then the parity bit
is
disabled and the parity checkers will see all zeros. This results
in a

map register parity failure. Then, if the DMP bit is set, the parity
checkers will see correct parity. Note, however, that if bits <7:0> of the
map
register contain an odd number of ones, the generated parity
bit will

be zero. The state of the DMP bit will therefore have no effect on

parity result in this case.

When the integrity of the parity generator checkers is to
map register must contain data so that at least one

206

the

be tested, the

of the bytes con-

UNIBUS Subsystem

tains an even number of ones. The DMP bit, when set, will disable the
parity bit, and the map register parity failure can be detected during a
DMA transfer. SBI Dead, Adapter INIT, and the power up sequence on

the UNIBUS adapter will clear this bit.

Bit <28> Defeat Data Path Parity (DDPP)

The DDPP bit functions in the same way as the DMP bit. When it is set,
the DDPP bit will inhibit the parity bits of the data path RAM from
entering the parity checkers. The data path parity generator checkers
generate and check parity on eight bit data units. Each parity field
(eight data bits and one parity bit) is implemented so that the total
number of ones in the field is odd. When the integrity of the parity
generator checkers is to be tested through use of the DDPP bit, the
total number of ones in at least one of the bytes of data must be even.
With the parity bit disabled by the DDPP bit, a data path parity failure
will result during a DMA transfer via that buffered data path. SBI Dead,
Adapter INIT, and the power up sequence on the UNIBUS adapter will
clear the DDPP bit.

Bit <27> Microsequencer OK (MIC OK)

The MIC OK bit is a read-only bit which indicates that the UNIBUS
adapter microsequencer is in the idle state. The microsequencer will

enter the idle state after it has completed the initialization sequence or
once it has completed a UNIBUS adapter function.

The MIC OK bit can be used by diagnostics to determine whether or
not the microsequencer has completed a successful power up se-

quence and whether or not it is caught up in any loops. Note that SBI
dead, UNIBUS adapter power supply DC LO, and Adapter INIT force
the microsequencer into the initialization routine. Once the routine has
been completed and the microsequencer has entered the idle state,
MIC OK will be true (1).

Bits <26:24> Reserved and Zero

Bits <23:00> Same as bits <23:00> of the Configuration Register
Failed Map Entry Register (FMER)

The Failed Map Entry Register contains the map register number used
for either a DMA transfer or a purge operation which has resulted in
the setting of one of the following error bits of the status register:
IVMR, MRPF, DPPE, CXTO, CXTER, RDS, RDTO. This register is
locked and unlocked with the UNIBUS to SBI data transfer error field
of the status register. The contents of the FMER are valid only when
the register is loaded. The FMER is a read-only register. Attempts to
write to the FMER will result in an SBI error confirmation. No signals or
events will clear the register.

207

UNIBUS Subsystem

The software can read the FMER to obtain the map register number

associated with the failure. It can then read the contents of the
failing
map register to determine the number of the data path which

failed.

Figure 9-14 shows the bit configuration for the Failed Map Entry Regis-

ter.

UNUSED

—

MAP REGISTER NUMBER

Figure 9-14

Failed Map Entry Register Bit Configuration

Bit <31:09> Reserved and Zero
Bits <08:00> Map Register Number (MRN)
These bits contain the number of the map register which was in

use at
the time of a failure. Bits <08:00> correspond to bits <17:09>
of the
UNIBUS address.

Failed UNIBUS Address Registers (FUBAR)
The FUBAR contains the upper 16 bits of the UNIBUS address

translated from an SBI address during a previous software-i
nitiated data
transfer. The occurrence of either of two errors indicated
in the status
register will lock the FUBAR: UNIBUS Select Time Out
(UBSTO) and

UNIBUS Siave Sync Time Out (UBSSYNTO). When
the error bit is
cleared, the register will be unlocked.

The FUBAR is a read-only register. Attempting to write to
the register
will result in an error confirmation. No signais or condition
s will clear
the register. Figure 9-15 shows the bit configuration
of the FUBAR.
The contents of the FUBAR are listed below.

UNUSED

——
hd

FAILED UNIBUS TO SBI ADDRESS

UNIBUS ADDRES BITS <17:02>

Figure 9-15

Failed UNIBUS Address Register Bit Configuration
208

UNIBUS Subsystem

Bits <31:16> Reserved and Zero

Bits <15:00> Failed UNIBUS to SBI Address
These bits correspond to UNIBUS Address bits <17:02>.

Buffer Selection Verification Registers 0-3 (BRSVR)
These four read/write do-nothing registers are provided in order to
give the diagnostic software a means of accessing and testing the
integrity of the data path RAM. Four spare locations in the data path
RAM have been assigned to these registers. Writing and reading the
BRSVRs has no effect on the behavior of the UNIBUS adapter. The
BRSVR bit configuration is shown in Figure 9-16.

16 15

31
UNUSED

v—

TEST DATA

Figure 9-16

Buffer Selection Verification Register Bit Configuration

The contents of the BRSVRs are listed below.
Bits <31:16> Always Zero

Bits <15:00> Read/Write Bits

BR Receive Vector Registers 4-7 (BRRVR)

The UNIBUS adapter contains four BR receive vector registers:
BRRVR 7, BRRVR 6, BRRVR 5, and BRRVR 4. Each BRRVR corresponds to a UNIBUS interrupt bus request level: 7, 6, 5, 4. Each
BRRVR is a read-only register and will contain the interrupt vector of a
UNIBUS device interrupting at the corresponding BR level. Each
BRRVR is read by the software as a part of the UNIBUS adapter interrupt service routine. Note that the UNIBUS adapter interrupt service
routine is the routine to which the VAX-11 CPU will transfer control
once it has determined that the UNIBUS adapter has transmitted an
interrupt request on the SBI.

If the IFS and BRIE bits on the control register are set, so that UNIBUS

interrupt requests are passed to the SBI, then the VAX-11 CPU responds with an Interrupt Summary Read command. The UBA sends
its request sublevel as an Interrupt Summary Response. The software
then invokes the UBA interrupt service routine, initiating a read transfer to the appropriate BRRVR. The UNIBUS adapter will assert the

contents of the BRRVR on the SBI as read data if the corresponding
209

UNIBUS Subsystemn

BRRVR Full bit in the status register is set. If the BRRVR Full bit is not
set, the Read BRRVR command causes the UNIBUS adapter to fetch

the interrupt vector from the interrupting UNIBUS device. The interrupt vector is loaded into the BRRVR only at the successful completion

of a UNIBUS interrupt transaction. The UNIBUS adapter will then send

the contents of the BRRVR to the SBI as read data. The BRRVR used is
cleared only when the UNIBUS adapter receives an ACK confirmation

for the read

data. Following this exchange, the UNIBUS adapter
interrupt service routine will use the contents of the BRRVR to branch

to the appropriate UNIBUS device service routine.

Four types of failure conditions can occur when the software is reading
a BRRVR and the VAX-11 CPU is servicing a UNIBUS device interrupt:
1.

If the software attempts to read a BRRVR for which a BR interrupt
line is not asserted, and BRRVR is not full, the zero vector (all

zeroes data) will be sent as read data.
2.

If the BR line asserted by the interrupting UNIBUS device is released during the interrupt summary read transfer, and the vector

is not received from the device (passive release), then the zero
vector will be sent as read data.

If the vector has been received from the interrupting device, but
an ACK confirmation is not received following the read data
transmission, then the BRRVR will not be cleared, and the BRRVR

Full bit will remain set. Subsequent read commands to the full
BRRVR will cause the UNIBUS adapter to send the stored vector,

but the BRRVR will remain full until the UNIBUS adapter receives
an ACK confirmation for the read data. Note that the BRRVR Full
bits always reflect the state of the BRRVRs.
4.

If the IFS bit in the control register is cleared and the software
reads a BRRVR, then the zero vector will be sent as read data.

The contents of the BRRVR are also used by the software to determine
whether or not the UNIBUS adapter itself has an interrupt pending. Bit
31 of the BRRVR is the Adapter Interrupt Request Indicator. Although
the bit is present in all four BRRVRs, it will be active only in the BRRVR

corresponding to the interrupt request level that has been assigned to

the UNIBUS adapter. If bit 31 is set when the software reads the
BRRVR, then an adapter interrupt request is pending.

Figure 9-17 shows the BR Receive Vector Register bit configuration.

210

UNIBUS Subsystem

19 18 17 16
31 30 20 28 27 26 25 24 23 22 21 20

00
13 12 1 10 09 08 ¢7 06 05 04 03 02 01
15 14

EENEEIEEEEREREEEEENENEEEERERERER
T

UNIBUS DEVICE INTERRUPT VECTOR

Figure 9-17

BR Receive Vector Register Bit Configuration

The contents of the four BRRVRs are as follows:
Bit <31> Adapter Interrupt Request Indicator.

0=No UBA interrupt pending.
1=UBA interrupt pending.

Bits <30:16> Reserved and zero

Bits <15:00> Device Interrupt Vector Field

These bits contain the device interrupt vector loaded by the UNIBUS
adapter during a UNIBUS interrupt transaction.
Data Path Registers 0-15 (DPR)

The UNIBUS adapter contains 16 data path registers (DPR 0 to DPR
15), each of which corresponds to one of the 16 data paths. DPR 0,
corresponding to the direct data path, is always 0.
Figure 9-18 shows the Data Path Register bit configuration.

16 156

24 23

31302928
UNUSED

BUFFER STATE BITS

BUFFERED UNIBUS ADDRES (2-17)

BUFFER | DATA
NOT

EMPTY

PATH

FUNCTION

BUFFER
TRANSFER
ERROR

Figure 9-18

Data Path Register Bit Configuration

The DPR bit functions are as follows.
e Buffer Not Empty and the Purge Operation

Bit <31> Buffer Not Empty (BNE)

Each DPR contains a data path status bit called Buffer Not Empty. This
bit is Read-Write one to clear bit.

0=Buffer empty.
1=Buffer not empty.
211

UNIBUS Subsystem
.

If this bit is set (1), the BDP contains valid data. If clear, then the BDP
does not contain valid data. The UNIBUS adapter uses the bit to determine the proper action for DMA transfers via the BDP. If bit 31 is set as
a DATI transfer begins, the data in the BDP will be asserted on the
UNIBUS. If bit 31 is clear on a DATI, the UNIBUS adapter will initiate a

read transfer to SBI memory, load the read data into the BDP, thereby
setting bit 31, and gate the addressed data to the UNIBUS.

For a DMA write transfer via the associated BDP, the BNE bit is set
each time UNIBUS data is loaded into the BDP. The bit is then cleared

when the contents of the BDP are transferred to SBI memory.

The software will write a one to this bit to initiate the purge operation.

The purge operation is required at the completion of a UNIBUS device
block transfer and is performed in the following way:
1.

Write transfers to memory. If any bytes of data remain in the

corresponding BDP (BNE is set), the UNIBUS adapter will transfer

this data to memory. The UNIBUS adapter will then initialize the

BDP and clear the BNE bit. If no data remains to be transferred
(BNE is cleared), the purge operation will be treated as a no-op (it

is a legal do-nothing function).

Read transfers to memory. If any bytes of data remain in the BDP,

the UNIBUS adapter will initialize the BDP by clearing the BNE bit.
If no data remains, the purge will be treated as a no-op.

In addition, the following considerations apply to the purge operation:
e For purge operations in which data are transferre
d to memory, the

SBI transfer takes about 2 usec. The UBA will not respond to Data

Path Register read transfers during this period (busy confirmation),
thereby preventing a race condition when testing for BNE bit.
¢ A purge operation to Data Path Register Zero (Direct
Data Path) is

treated by the UBA as a no-op.

Bit <30> Buffer Transfer Error (BTE)
This is a read-write one to clear bit. The UNIBUS adapter sets the BTE

bit if a failure occurs during a DMA write transfer, or a purge, or for a
data path parity failure during a DMA read transfer via the associated

BDP. If bit 30 is set, any additional DMA transfers via the BDP will be
aborted until the bit is cleared by the software. Note that if a parity
error on the UNIBUS occurs during a DMA read, the UNIBUS signal

PB will be asserted, giving the UNIBUS device the opportunity to abort

its own DMA transfer. The purge operation does not clear the BTE bit.

Bits <29:00> Read-Only Bits

Bit <29> Data Path Function (DPF)
212

UNIBUS Subsystem

This bit indicates the function of the DMA transfer using this data path.
0=DMA Read
1=DMA Write

Bits <28:24> Unused

Bits <23:16> Buffer State (BS)
These eight bits indicate the state of each of the eight byte buffers of
the associated BDP during a DMA write transfer. They are included in
the Data Path Register for diagnostic purposes only. The UNIBUS
adapter generates the SBI mask bits from the BS bits during a DMA
write transfer or purge operation. The bits are set as each byte is
written from the UNIBUS. The bits are cleared during the SBI write
operation.
0=Empty.

1=Full

Bits <15:00> Buffered UNIBUS Address (BUBA)

This portion of each DPR contains the upper 16 bits of the UNIBUS
address, UA <17:02>, asserted during the DMA transfer using the
associated BDP. If the transfer through the associated BDP is in the
byte offset mode, and the last UNIBUS transfer has spilled over into
the next quadword, then these bits contain UA <17:02>. This is the
UNIBUS address from which the SBI address will be mapped should a
purge operation occur before the next UNIBUS transfer.

Map Registers 0-495(10)

The UNIBUS adapter contains 496 map registers, one for each UNIBUS memory page address (a page = 512 bytes).

REG

Offset

MRO

800

MR1

804

MR2

808

MR3

80C

MR494

FB8

MR485

FBC
213

UNIBUS Subsystem

When a DMA transfer begins, the upper nine address bits
asserted by
the UNIBUS device select one of the map registers which the
software
has set up. The map register in turn tests for the validity
of the current
UNIBUS transfer, steers the transfer through one of the
16 data paths,

determines whether or not the transfer will take place
mode if

in the byte offset
a BDP has been selected, and maps the UNIBUS page
ad-

dress to an SBI page address.

The map registers are numbered sequentially from 0 through
495(10).
There is a one to one correspondence between each map register
and
UNIBUS memory page address (i.e., MRO corresponds to
UNIBUS
memory page 0, MR1 to UNIBUS Memory Page 1.....MR49
5 to UNI-

BUS memory page 495). Each map register contains the informatio

required to effect the data transfer of the UNIBUS device

addressing

that page:
1.

The fact that the software has loaded the map register

ter valid).

(map regis-

The number of the data path to be used by the transfer and,

BDP is used, whether it is in byte offset mode.

if a

The SBI page to which the transfer will be mapped.

Since the map register is implemented with a bipolar RAM, the
contents of the map registers will be checked by parity. If, during
a

UNIBUS transfer, the parity test fails, the map register parity fail bit of
the UNIBUS adapter status register will be set and the UNIBUS trans-

fer will be aborted.

Figure 9-19 illustrates the map register bit configuration.

27 26 25 24

21 2019

o
e

RESERVED
AND
ZERO

MAP

DATA

SBI PAGE ADDRESS

PATH

DESIGNATOR

BYTE
OFFSET
BiT

ADDRESS
IT 27
1/0 DESIGNATOR

LONGWORD
ACCESS
ENABLE

Figure 9-19

Map Register Bit Configuration

NOTE

In the interest of brevity, for the map register description, “this UNIBUS page” refers to “The UNI-

BUS memory page corresponding to this map regis-

ter.”

214

UNIBUS Subsystem

The contents of a map register are as follows:

Bit <31> Map Register Valid (MRV)
0=not valid - initialized state.
1=valid.

The MRV is set by the software to indicate that the contents of the map

register are valid. The MRV is tested each time that “this UNIBUS
page’ is accessed. If the bitis set (1), the transfer continues. If the bit is

not set, the UNIBUS transfer is aborted (nonexistent memory error in
the UNIBUS device) and the invalid map register bit is set in the UNIBUS adapter status register.

The MRV can be set and cleared by the software.

Bits <30:27> Reserved Read/Write Bits
Bit <26> Longword Access Enable (LWAE)
This is a read/write bit. If set, and the map register selects a BDP, then

the longword-aligned 32-bit random access mode is enabled for the
BDP. The longword-aligned 32-bit random access mode has been
discussed above. This bit has no effect if the Direct Data Path is
selected by the map register. This bit is cleared on initialization.
Bit <25> Byte Offset Bit (BO)

This is a read/write bit. If set, and “this UNIBUS page” is using one of
the BDPs, and the transfer is to an SBI memory address, then the
UNIBUS adapter will perform a byte offset operation on the current
UNIBUS data transfer. The software can interpret this operation as
increasing the physical SBI memory address, mapped from the UNIBUS address, by one byte. This allows word-aligned UNIBUS devices
to transfer to odd byte memory addresses.

UNIBUS transfers via the DDP or to SBI I/0 addresses will ignore the
Byte Offset bit.

This bit is cleared on initialization.

Bits <24:21> =Data Path Designator Bits (DPDB)
Direct Data Path (DDP)
0000 =

0001=

Buffered Data Path 1

1111=

Buffered Data Path 15

The DPDBs are read/write bits that are set and cleared by the software
to designate the data path that “this UNIBUS page” will be using.
215

UNIBUS Subsystem

The software can assign more than one UNIBUS transfer

to the DDP.

The software must assure that no more than one active UNIBUS

fer is assigned to any BDP.

trans-

The DPDBs are cleared on initialization.

Bits <20:00> SBI Page Address (SPA 27:07, also known
as Page

Frame Number, PFN)

The SPA bits contain the SBI page address to which “this UNIBUS

page” will be mapped. These bits perform the UNIBUS to
SBI page
address translation. When an SBI transfer is initiated the contents
of

SPA<27:07> are concatenated with UNIBUS address bits UA<8:2>
to form the 28-bit SBI address.

POWER FAIL AND INITIALIZATION
The UNIBUS adapter controls the UNIBUS power fail, power up, and

initialization sequences of the UNIBUS. This section explains the behavior of the UNIBUS subsystem for each of the following:

System Power Up

System Power Down

UNIBUS Power Down

Programmed Power Down

SBIUNJAM

System Power Up
The UNIBUS remains in a powered down state as long as the
UNIBUS
adapter is in a powered down state. During System Power
Up, the
UNIBUS adapter will initiate the UNIBUS power up sequence,
provided the UNIBUS has power. Once the power up sequence
has been

completed, the UNIBUS Initialization Complete bit of the
UNIBUS
adapter status register is setand an interrupt request is initiated
to the
CPU. If the UNIBUS power was not on at the time that the
system
powered up, the power up sequence will not continue until
the UNI-

BUS power has been turned on. The power up sequence will
com-

pletely initialize all registers and functions of the UNIBUS adapter.

deassertion of power supply AC LO will set the adapter power

the Configuration Register and initiate an interrupt request.

The

up bit in

SBIl Power Fail
The UNIBUS adapter will initiate a UNIBUS power fail sequence
whenever an SBI power failure is detected (SBI Dead asserted).
The UNI-

BUS will remain powered down as long as SBI Dead is asserted.

The
UBA will initiate the UNIBUS power up sequence when SBI Dead is

released.

216

UNIBUS Subsystem

UNIBUS Power Fail

A power loss on the UNIBUS will initiate a UNIBUS power fail sequence. The UNIBUS power down bit of the status register will be set
and the UNIBUS adapter will initiate an interrupt request (providing
the CNFIE bit is set). The UNIBUS will remain in a powered down state
until UNIBUS power has been restored, at which time a UNIBUS power
up sequence is initiated. The UNIBUS initialization complete bit of the
status register will be set on a successful power up sequence and the
UBPDN bit will be cleared. The UNIBUS power fail lines will not affect
the state of the SBI power fail lines.

Programmed UNIBUS Power Fail

The software can induce a power fail sequence on the UNIBUS by first

setting and then clearing the UNIBUS power fail bit of the control
register. The UNIBUS adapter will initiate a power fail sequence when
the UPF is set. Once it has been initiated, the power fail sequence will
continue to completion independent of the state of the UPF. On completion of the power down sequence, the UNIBUS adapter will initiate a
power up sequence if or when the UPF is cleared, provided power is
normal for both the UNIBUS and UNIBUS adapter.

Setting the AD INIT bit will also initiate a power fail and initialization
sequence on the UNIBUS as well as completely initialize all registers
and functions of the UBA.
SBI UNJAM

The assertion of SBI UNJAM will initiate the UNIBUS power fail and
initialization sequence. It will also clear all interrupt enable bits of the
UBA control register. It will initialize the UBA SBI logic so that the UBA
is available for an SBI Command.

EXAMPLE

Presented is a program to read data from the RK06 disk subsystem
into memory. The program full documented and is designed to demonstrate the loading of the UBA map registers, the use of a buffered
data path (including the purge), access to UNIBUS device registers,
and initialization of the UNIBUS. In order to run the progra, it must be
loaded from the floppy disk by the console into memory. Initially, the
program can be assembled and linked under VAX/VMS and then

transferred to the floppy disk using the RSX-11M utility program FLX.

- The file structure of the fioppy is RT-11 format.

217

READ

FROGRAM

DISK

s e

FROM

THIS

FROGRAM

WILL

USE

MAF

THE

RKO6

WILL

MEMORY

ELOCK

AND

WILL

MAF

WILL

READ

DATA

WILL

RING

THE

LETECTED.

THE

FROGRAM

MAF

THE

FURGE)r»

SYMBOL

DEFINITIONS

SYMEOLS:

URA..BASE

UBALCNFR

UBA_UBIC

TQO

UBA

OFFSET

i
i

LOALING

FATH

MALE

FOR

UBA

CONFIGURATION

UBA

ADIARTOR

THE

(INCLUDING

AND

INITIALIZATION

&4,

CONTROL

INIT

COMFLETE

"X8

~X40

OFFSET

UEA

OFFSET

AND UNIBUS INITIALTZATION
STATUS REGISTER

TOD

URA

DATA

BUFFER

USED

~X80000000

~X40000000

FATH

~X800

NOT

PURGE

END

BUFFER
OFFSET

“XB0OG0OQ00

7X2000000

VALID

BIT

RYTE

OFFSET

DK.CS1

~00

OK_CS2

~010

DK_IS

~01z2

IK_DE
OK_IA

=
=

~020
"06

DRK_WC

OK.BAa

~04

SCLR

~040

FACACK

READ

MISC

~0777440

BASE

UNTEBUS
RK611

~o2

RK&11

i
f

RK611
RRK611

~03
"021

SYMBOLS:

WORD

RK&11

kK611

BUS ADLDRESS REGISTER
SUBSYSTEM CLEAR
FACK ACKNOWLEDGE AND

DISK
ERELL

ASCII

CONSOLE

MOVL

ADORESS

#UBA_BASEyY RO
#UBA_ADINIT,URA_CR(RO)

RKNé11

INIT:

MAF

RKé11

MOVL

RKé11

URA_EASE

MAF

RIT

THE

LOADS

XFER.

ERROR EIT
REGISTER 0

INTO

LOAD

INIT

DRIVE STATUS REGISTER
DESIRED CYLINDER REGISTER
DISK ADDRESS REGISTER

BELL

SECTION

FOR UNIRUS ADDRESS
EASE ADDRESS OF IIN&11
CONTROL STATUS REGISTER 1
CONTROL STATUS REGISTER 2

TXDR

UNIERUS,

DATA

ADDRESS

i
#
i

REGISBTER

RIT
EBUFFER

TRANSFER
UBA MAF

BYTE.OFST

RELATED SYMBOLS:
UNIBUS_EBASE = "X20100000

FATH

EMFTY

MAF_VALID

BEGIN:

~X1

OFFSET

THE

DATA

CTOR

ARE

REGISTERS»

(DFS),

ERRORS

UBA_SR

THIS

UNIERUS

FATH

CYLINDER
NO

CLAIM

DK_BASE_ADD

THE

DEVICE

DATA

2,
IF

BUFFERED

UBA_IIF _RTE

ANY

TRACK

RKO6
TRANSFER

UBA_DIIFO

UBA_MRO

EUT

BUFFERED

"X20004000

UBA_DF_ENE

THIS

THE
THE

DEMONSTRATE

"X10000

FROM

4547,

STARTING

~X0

= TX4
UBA_ADINIT =

THE

BYTES

CONSOLE

UNIEUS

UBA_CR

RK&11

THE

THE UNIEUS.
FROGRAMMING STYLE,

USE

ORIVE
OF

USE

MEMORY
3210

AIDRESS

REGISTERS

DESIGNED

ACCESS

INITIALIZATION

UBA

FROM
EBELL

REGISTERS,

ELEGANCE

UBA

INTD

TRANSFER

STARTING

COUNT

READ

AND

TRAANSMIT

AND

UEA’S

UEA

THEN

RIT

DATA

RIT

SET

SET.

BUFFER

INITIALIZES

ADDRESS

AND

INTO

UNIERUS

UBA

AND UNIBUS ARE BEING INITIALIZED,
THE FROGRAM CANNOT MAKE
ACCESSES TO THE URA OR THE UNIEUS
DURING THIS FERIDD OF TIME.
THAT’S OK BRECAUSE WE HAVE LOTS
TO IO IN THE MEAN TIME...

SECTTON

FIND

THE

ASHL

WILL

OFFSET
¥2r

SET

THE

MAF

INITIAL

MAF_REG:

REGISTERS

MAF

i
¥

ADDL

FUBRA_MRO»

FURBA_RAGE,

USED

AND

FUT

FOR

THE

INTO

TRANSFEF.

k1.

MULTIFLY THE MAF REGISTER RY
Ta FIND L1§ UFFSE1T
AND FUT

PoAUD

THE

OTHE

§OAID

218

EASE

ADDRESS

OFFSET

THE

UBA

AND

BASE

FUT

THE
IN

4
IMTO

MAF

REGISTERS

R1.

ADDRESS

AND

BUT

1IN

R1 NOW CONTAINS THE ALDRESS OF THE FIRST MAF REGISTER TO RE LOADNED.
IN RZ.

NUMBER (F THE FIRST
THIS SECTION WILL DETERMINE THE PAGE FRAME MEMORY
AIDRESS 18 SHIFTED
MEMORY FAGE TO RE ACCESSED. THE FHYSICAL NUMBER.

$
i

WILL THEN RE INSERTELD
THE DATA FATH NUMBER TO RBE USED FOR THE TRANSFER
INTO THE DATA FATH DESIGNATOR FIELL ANDI THE vaLID ®BIT IS SET.

RIGHT NINE BITS TO EBECOME THE FAGE FRAME

RISL

. VALTIII»
#MAFP

;
;

FAGE FRAME NUMEER.

INSERT RITS 0-3 OF DF.NUM INT)

RITS 21~24 OF R2,
SET MAF VALID BIT.

DATA FATHS I8
DNETERMINE IF THE EYTE ALIGNMENT EBIT OF THE RUFFERED TRANSF
53
REQUIRED. THE RK&11 ONLY KNOWS AEOUT WORID ALIGNED RIT OF
THE START MEM ADDRESS IS OLDDI' THEN THE EYTE OFFSET
MAF REGISTERS MUST BE SET.

RITL
REQL

RISL

CONT$:

TURN START ADDRESS INTO THE

INSV

OF_NUMs 21 4, R2

¥-9y MEMSADy R2

ASHL

w
ar

STORE

THIS SECTION WwlLl DETERMINE THE CONTENTS OF THE MAF

i 18 MEM ADDRESS 0QDD7T
+ IF NOT THEN CONTINUE.

~“X1s MEMSAD
CONTS$

YES -- SET BYTE OQFFEET EIT

[

#RYTE_OFST» R2

FCONTINUE

NOF

v s s e

> Mr NI s ey ey MR £ WD SR M R > Wy

THIS SECTION COMFUTES THE CONTENTS OF THE RR&11 BUS ALDRESS REGISTER

ANDl THE EXTENDED ADDRESS EITS OF CONTROL STATUS REGISTER 1.
RKé611 ASE
THE RESULT OF THIS SECTION WILL EBE THAT WHEM THE
ALDRESS ONTO THE UNIERUSs UNIERUS ADDRESS BRITS -117309> WIL

THE MAF REGISTER THAT CONTAINS THE FPAGE FRAME NUMEBER FOR THE TRANSFER
THE
ANIl UNIEUS ADDRESS BITS <Bi0x WILL CONTAIN THE EYTE OFFSET WITHIN
.,
FAGE

THE CONTENTS OF THE REGISTERS WILL RE AS FOLLOWS?
AND
7 o1
RA
DK_.CE1
» WILL CONTAIN THE FOINTER
BA <
UK EBA
TO THE MAF REGISTER THAT CONTAINS THE FAGE FRAME NUMRER
THE

TRANSFER,

FOR
Be 08 ¢ 00> WILL CONTAIN THE EYTE OFFSET WITHIN THEAF PAGLES
DK.LEA
TO SET UF TO CONTAIN THE INITIAL UNIBUS Al
USED
F3 WILL BE

THE

TRANSFER.

ASHL

¥9y MAF_REGy» R3

MAF RE
REGISTERS

SHIFT
MAF

i
5

: NUMBEFR TO FORM

[NT

BICL3

$~XFEFEFEOQ, MEMSAD: R4 § CLEAR ALL BUT RYTE

RISL

R4y R3

FAGE

THE

ANII COMBINE WITH MAF REGIS
IN

THIS SECTION WILL DETERMINE THE WORID COUNT FOR THEIF TRAN
RBYTE
CONVERT BYTE COUNT TO WORD COUNT FOR THE RKé&i1l.
CONTAIN ALl

[HEN THE WORD COUNT MUST RE INCREMENTELD TO

.,
TRANSFER

INCL
ASHL.

INGV

INTO

TRACK AND SECTOR - WILL USE RT.
i INSE

TRACK: #8y #3» RI

THE VALUES 0OF THE REGIS

BITS

"D FOR

= UBA _RASE ALDRE
- ADDRESS OF FI

e
<

COUNT

WORD

AND TRACK

TRACK INTO
O

THE

TRANS FEFR

HIAVE

ARES

D FOR TRANSEER

. CONTENTS FOR THE
UNTEUS NDT
= INTTIS
SECTOR

RA.

i GET

SECTORy KY

AT THIS FOINT ALL OF THE VALUES REQUI
DETERMINED,

0nn

; INCREMENT EYTE COUNT TO ACLOUNT
COUNT.
FOR ODD BYTE
i CONVERT TO WORD COUNT @&ND LOAD

RCOUNT
f-1y BCOUNTy R4

THLS SECTION WILL SET UF DISK ANDNRESS
MOVL

EROFOINTER

R3.

FCE I,

INCL

BCOUNT

ASHL.

t-1y

WOKD

MUST

BCOUNT,

SECTION

WILL

MOVL.

SECTORy

INSV

TRACK>

#8y

THIS

FOIN T

DETERMINED.

SET

ALL
THE

FOR

DIISK

#3y

THE

UBA_RASE

WORD

SECTOR

FOR

ws
s

SECTION

FAGES

ARE

ADDRESS
-

USED
WAS

THE

INITIAL

MOVL

BECOUNTy

MOVL

R2y

BGTR

2%
R2y

CLRL

THE

SECTION

SUBSYSTEM

URA

MAF

USED

FUNCTION

WILL

ALL

THE

DETERMINED

MAF

DRIVE,

USED

LOA

BYTE

LOAD'

MAF

INCREMENT

(ASSUMES

REEN

FOR

TKANSFER

IK_.CS2(R1)

DR.OACRLY

USED

FOR

MUST

INITIAL
THE

AROVE

THE

MEMORY
MAF

FHYSICAL

AND

PAGE

ARE

STORED

MAFS

SET

SET
UF

INVALIDATE
STOF
GO

WORL

INTO

K1,

s
-

MOV

MNEGW

CYLINDER, DR_DS(R1)
R4y
DK_WC(R1L)

LOAD

MOVW

R3y

SHOULD

ITS

THE
WILL

TRANSFER
FAGE

ALIGNEL.

EXFECTED

TRANSFER
LIMIT.

DIISK

FOR

ADDRESS

OF RKé11 T0
SURSYSTEM CLEAR

ADDRESS

SECTOR

AEOVE.

FROM

ACKNOWLEDGE

KEEF

CYLINDER

LOAD

278
1.OW

START

NUMBER

READY

LOAD

FACK AKNOWLEDGE
BE INITIATED.
FORMAT..

RK&11

FACK

NOT

URA

DRIVE

ISSUE

WAIT

NOT

MAF

7EASE
A

LOAD

UP?

MAF
SINCE

BYTE

STORED

DR._CS1{R1)

MAY

THE

SELECT

TSTR

BYTES FER FAGE.

SEQUENCE,

EGEN

KEYOND

TRANSFER

NUMBER.
FAGES

MEMORY).

ARE 200(HEX)

ALL

NO
SET

FRAME

CONTIGUOUS

220

UEA.

ACCESSES

COUNT
INTD Ré
REGISTER WITH CONTENTS

ONE
TRANSFER

LIK.CSL(RL)

THE

UNIRUS,

RZ2.

THERE

THE
R2.

FHYSICAL

MUST

WILL

FHYSICAL

H+UNTRUS. -BAS Ey Rl
OR_.CS2(R
(R1)
ISSUE

DK_BALRLY

AND

TRANSFER

LISK

THAT

BLOCK

DETERMINED

ACCESSES

FFACACK,

HAVE

TESTING

EE ISS USED TO THE RKé11ly
ISSUEDs AND THE DISK TRANSFER

RIs

INTO

CONTINUE

STORED

WILL

MavW

TRACK

INITIALIZATION COMFPLETE?

KEEF
-

CONTENTS

THE

WAS

MOVW

ERE

UNIEUS

CONTIGUOUS

FSCLR
Y

MOVW

IS UNIEUS
NO

THE

FOR_EASE_ADD,

MOV

RS,

YES

AND

WE ARE NOW FINISHED WITH K1 AND
R2.
FINI' RASE ALDRESS OF RK&11 AND
LOAD

ADDL.3

MAF

REGISTERS

TRANSFER.

FERFORM

UNIBUS

TRANSFER

IK_DA

CLEAR

USE

K4.

TRANSFER

FOR

THAT

(R1)+

WILL

0-2
OF

FOR

ASSUMES

(R1)

THIS

WILL

MUST W E COMFLETE REFORE MAKING
CONFIGURATION REGISTER) OR THE

(R1)+

+F7X200y

MOVL

THAT

FOR

ACCESSES

SUEBL.

INITIAL

ADDRESS

UBA_CNFR(RO)

PREVIOUSLY

THE

MAF

THE

TRACK

REGISTERS

R1.

INCL

NOTE

THE

FROGRAM

FOR

FIRST

AND

SEQUENCE

LOAL

MAF

THIS

0OF

INVOLVE

THAN

WILL

THE

LOAD

NUMEER.
*

BITS

THIS

TRANSFER.

SECTIONS

CONTIUOUS.

ACCOUNT

AND

COUNT

#UBA_URICy

BEQL

QLD

THE

ADDRESS

UNIBUS

BRITL

COUNT

SECTOR

THE

INITIAL

182

ANII

COUNT.

WORD

SECTOR

FOR

( OTHER

TRACK

ARE:

UEA

R4,

REQUIRED

ADDRESS

INITIALIZATION

INTO

COUNT

BYTES

COUNT

BYTE
TO

REGISTERS

CONTENTS

THE

BYTE
ALL

RYTE

ODD'

8-10

TRANSFER.

EITS

THE

FOR

INSERT

VALUES
OF

THE

CONTAIN

INCREMENT

REMAINING

FOR

RKé11,
TO

CONVERT

ANLRESS

THE

COUNT
THE

WORD'

INCREMENTEL

GET

VALUES

THE
COUNT

TECTIRvTap

COUNT

DETERMINE

COUNT

WORD

THIS

WILL

BYTE

TRANSFER.

SECTION
THE

w
wr

THEN

THIS

CONVERT

AND

TRACK

FUNCTION

WATTING

ADDRESS

COMFLIMENT
ORDER

ADTRESS

BITS

INTOQ

WORD

COUNT

UNIRUS

UK.EO6

REG

ar
o
ar
er
w

THE

OK_FUNC+
R3s #8»

MOV

K4y

TSTE

OK..CE1(R1)

EGEQ

RKé11

FURGEI.

INSY

$-146

MOVL

[

ASHL

DK.CS1(R1)

SHIFT UNIEUS ADLRESS RIGHT 16 ERITS
LOAD FUNCTION INT(O R4 AND
INSERT ALDRESS BITS 17 AND 15 FROM
R3 RITS 1:0 INTO ERITS 9:8 OF
EXTENDED UNIRUS ADDRESS
R4,
RITS.

ISSUE FUNCTION ANI GO TO RKé11

WAIT FOR TRANSFER TO COMFLETE
NOT COMFLETE - KEEF WAITING.

THE URA RUFFERED LATA FATH MUST NOW EE

HAS REEN COMFLETED

THE FURGE IS REQUIRED TD MOVE ANY DATA REMAINING IN THE URA

TO MEMORY AND TO INITIALIZE THE BUFFEREL DATA FATH FOR ANY SURSEQUENT
THE FURGE IS ACCOMFLISHED RY SETTING THE BNE RIT OF THE
.
TRANSFERS
DATA FATH REGISTER USED EY THE TRANSFER.

COMFUTE OFFSET OF DATA FATH REGISTER USED FOR TRANSFER AND FUT IN R2
DP_NUM»
Y
#UBA_DFQ
FURA_DF _ENE»

$£25

ASHL

AIDL
MOVL

URA. BRASE (R2 ) 5
!

FURA_IF .RTE,

BITL

UBA_BAGE(RR))

HALT

TSTW

OK.CS1 (K1)

EGEQ

HALT

TEST FOR ANY ERRORS THAT MAY HAVE
OCCURRED WITHIN THE URA BUFFER

TRANSFER.,

i
[
i

OTEST FOR RK6L1 ERROR
COMTINUE IF THERE WERE NO ERRORS
HALT FOR FRROR DETECTED IN RK611

CONTINUE IF THERE WERE NOQ ERRORS
HALT FOR ERROR DETECTED ERY DATA
URA STATUS REGISTER
FATH REGISTER.
SHOUL.D CONTAIN ERROR RIT.

RING BELL ON CONSOLE

#RBELL

MTFR

REG 0O
SET EBNE RIT OF DATA FATH REGISTER
USED BY THE TRANSFER.

i
i
§
§
[
3

REGL

MULTIFLY DF.NUM KY 4 -@* R2
ADD IN DFFSET OF DATA FATH

IF NO ERRORS

HALT

TRACK?

+LONG
+LONG

CYLINDER:

+LONG

SECTOR?
OK_FUNC:

+LONG

JENDO

+LONG

Neb

+LONG

ces

+LONG

ECOUNT?
MAF_.REG?
TR _NUM?
DRIVE:

+LONG

can

FERAMETERS ARE SFECIFIED EBELOW?

TRANSFER

THE
MEMSAD?

START ADDRESS
NUMEER OF EBYTES OF TRANSFER

MEMORY

STARTING MAF REGISTER TO BE USED FOR TRANSFER.,
UEBA DATA FATH TO BE USED FOR TRANSFER.
DRIVE NUMEBER TOQ RE USED FOR TRANSFER
STARTING TRACK
STARTING CYLINDER
STARTING SECTOR
OISK FUNCTION

REGIN

221

222

CHAPTER 10

MASSBUS SUBSYSTEM
INTRODUCTION
ace between the
The MASSBUS adapter (MBA) is the hardware interf
BUS
speed
synchronous backplane interconnect and the highion path MASS
g the
linkin
nicat
commu
storage devices. The MASSBUS is the
.
drives
e
devic
ge
stora
MASSBUS adapter to the mass

The MASSBUS adapter performs the following functions:

e Mapping of addresses from virtual (program) to physical (SBI).
e Data buffering between main memory transfer to the MASSBUS and
vice versa.

e Transfer of interrupts from MASSBUS device to the SBI.
adapters,
The VAX-11/780 will support a maximum of four MASSBUS
A MASSBUS

llers.
each adapter supporting up to eight device contro
ge devices. Each
stora
mass
of
n
natio
combi
any
rt
suppo
will
er
adapt
drives. Each disk
tape
eight
to
up
rt
magnetic tape controller will suppo
controller can
one
Only
drive.
disk
single
a
controller will support
transfer data at any one given time. The data transfer rate is depend-

accessed. Figure
ent upon the particular mass storage device being uratio
n.
config
stem
subsy
10-1 illustrates a typical MASSBUS
two indeThe MASSBUS is comprised of 54 signal lines divided into
the synand
(bus)
path
l
contro
us
hrono
pendent groups: the async
BUS
MASS
dual
indivi
ibes
descr
10-1
Table
(bus).
path
chronous data
signal line function.

Table 10-1

SIGNAL LINE
CONTRCOLBUS

Control and Status
(C00-15)

MASSBUS Line Descriptions

DESCRIPTION

Transfers 16 parallel control or status bits to
or from the drive.
223

Massbus Subsystem

c
SYNCHRON

OUS

BACKPLAN

INTERCON

NECT

MASSBUS

ADAPTOR

DEVICE ©

DISK
CONTROLLER

MASSBUS

(DATA AND
CONTROL PATHS)

DEVICE

MAGTAPE

CONTROLLER

[

MAGTAPE
1

]

;

U [macrare
7

Figure 10-1

DEVICE

> STORAGE

CONTROLLER

MEDIUM

MASSBUS Subsystem Conf

iguration

Table 10-1 (cont.)

SIGNAL LINE

CONTROL BUS
Control Bus Parity
(CPA)

DESCRIPTION

Transfers odd control bus parity to
or from
the drive. Parity is simultaneously trans-

ferred with control bus data.
Drive Select (DS0-2)

Transfers a 3-bit binary code from

the MBA

to select a controller. The drive respo

nds

when the (unit) select switch in the contro

ler corresponds to the transmitted

code.

binary

Transfers a 5-bit binary code from the MBA
to select a particular drive register.

224

Massbus Subsystem

Table 10-1 (cont.)

SIGNAL LINE
CONTROL BUS

Controller to Drive
(CTOD)

DESCRIPTION

indicates in which direction information is to
be transferred on the control bus. For a
controller-to-drive transfer, the MBA asserts CTOD; for a drive-to-controller transfer, the MBA negates CTOD.

Demand (DEM)

Asserted by the MBA to indicate a transfer

is to take place on the control bus. Fora
controller-to-drive transfer, DEM is asserted by the MBA when data is present. Fora
drive-to-controller transfer, DEM is asserted by the MBA to request data and is
negated when the data has been strobed

from the control bus. In both cases, the RS,
DS, and CTOD lines are asserted and allowed to settle before assertion of DEM.

Transfer (TRA)

Asserted by the drive in response to DEM.

For a controller-to-drive transfer, TRA is asserted when the data is strobed and negated when DEM is removed. For a drive-tocontroller transfer, TRA is asserted when

the data is asserted on the bus and negated
when the negation of DEM is received.

Attention (ATTN)

The drive asserts this line to signal the MBA
of any change in drive status or an abnormal condition. ATTN is asserted any time a
drive’s ATA status bit is set. ATTN is common to all drives and may be asserted by
more than one drive at a time.

Initialize (INIT)

Asserted by the MBA to initialize all drives

on the bus. This signal is transmitted whenever the MBA receives an initialize command.

Fail (FAIL)

When asserted, this line indicates a power
fail condition has occurred in the MBA or
the MBA is in maintenance mode.

225

Massbus Subsystem

Table 10-1 (cont.)

SIGNAL LINE

DESCRIPTION

DATA BUS
Data (D00-15)

Data Bus Parity (DPA)

These bidirectional lines transfer 16 paralle
l
data bits between the MBA and drives.

Transfers an odd parity bit to or from the

drive. Parity is simultaneously transf

erred

with bits on the data bus.

Sync Clock (SCLK)

Asserted by the drive during a read

operation to indicate when data on

the data

write operation SCLK is asserted to

the

bus is to be strobed by the MBA. During

MBA to indicate the rate at which data

would be presented by the MBA on the

bus.

Write Clock (WCLK)

Run (RUN)

data

Asserted by the MBA to indicate when
data
written to the drive is to be strobed.

Asserted by the MBA to initiate data trans-

fer command execution. During a data

transfer, the drive samples RUN at

the end

of each sector. If RUN is still asserted,

the
drive continues the transfer into the next

sector; if RUN is negated, the drive

nates the transfer.

End-of-Block (EBL)

termi-

Asserted by the drive at the end of each

sector. For certain error conditions

where it

is necessary to terminate operations im-

mediately, EBL is asserted prior to
the normal time. In this case, the transfer is termi-

nated prior to the end of the sector.

Exception (EXC)

Asserted by the drive or MBA to indicat

error condition during a data transfer
command. EXC remains asserted

trailing edge of the last EBL pulse.

Occupied (OCC)

e an

until the

Indicates acceptance of a valid data trans-

fer command.

Figure 10-2 illustrates the MASSBUS signal

226

line configuration.

MASSBUS CONTROL BUS

C00-15 {CONTROL /STATUS)
CPA{CONTROL BUS PARITY

DS00-02 (DRIVE SELECT)

RSO0-04 {REGISTER SELECT)
CTOD [ TRANSFER DIRECTION)
DEM (DEMAND)

IRV

Massbus Subsystem

[TRANSPER)
TBA
ATTN (ATTENTION)

MASSBUS

ADAPTER

MASSBUS
Ve

DATA BUS

D00-15 (DATA)

DPA (DATA_BUS PARITY]
SCLK {SYNC CLOCK)

INIT {INITIALIZE)

WCLK (WRITE CLOCK)

RUN {START,CONTINUE, STOP)
EBL (END OF BLOCK)
1

EXC({EXCEPTION)
OCC (OCCUPIED}

Figure 10-2 MASSBUS Signal Line Configuration
MASSBUS ADAPTER OPERATION

internal
The MASSBUS adapter consists of an SBI/MBA interfaace,simplif
ied
is
registers, control paths and data paths. Figure 10-3
SBI
the
ts
connec
bus
l
block diagram of the MBA. A tristate interna
module to the internal registers, control paths, and data patns, and

provides for the passage of data to the various functional blocks.
The MBA accepts and executes commands from the CPU and reports

The
the necessary status changes and fault conditions to the CPU.
MASSa
from
or
to
data
of
block
a
or
data
r
MBA can transfer registe
stores
BUS device. A 256 X 32-bit (bits <30:21> are not writable) RAM
The
erred.
transf
be
to
the physical page addresses of the block of data
BUS
MASS
the
to
bits)
(16
words
memory data (64 bits) will be sent in
the second
drive in the order of the first word (bits 15 to 0), followed byfeatur
es are
word (bits 31 to 16) of a long word. Special diagnostic
MASSand
MBA
the
of
built in the hardware to allow on-line diagnosis
BUS drives.

drive with a maximum
The MBA is capable of handling a MASSBUS
wide MASSBUS
16-bit
the
data transfer rate of 16 bits per usec via ols data trans
fers between
contr
er
data path. The MASSBUS adapt
adapter can
BUS
MASS
A
ry.
memo
cal
physi
and
MASSBUS devices
227

Massbus Subsystem

T T T WASSEUS ADAPTER
T T T T T
|

= TN
I

CONTROL
PATH

]

|
!

SBI BUS

K" INTERNAL BUS

DATA

INTERFACE [N\

|
|

MASSBUS

\l;“

|
]

INTERNAL

I
|

REGISTERS

{

Figure 10-3

MASSBUS Adapter

transfer 16 bits at a time to a mass
storage

device or it can receive 16
bits at a time from a MASSBUS
drive. The MBA contains a 32-byt
e
buffer used to store data enroute
to either main memory or mass

storage. Transfers (data only) along
the SBI, to or from main memory,
occur in 64-bit (8-byte) increments.
Therefore, there are four MASS-

BUS transfers (16 bits each) per
SBI transaction. The MASSBUS

adapter will accept only aligned longw

ord reads and writes to its exterpt to address a nonexistent regist
er

nal or internal registers. An attem

in the MASSBUS adapter will prompt

a no-response confirmation.

MBA Registers
There are two sets of registers in the MBA

external. The MBA internal registers

address space: internal and

are the registers which are physi-

cally located in the MBA. The externa
l registers are located in the
MASSBUS drives and are drive-depend
ent.

There are eight internal registers and

a 256 X 32-bit RAM. The internal

register is primary function is to
monitor MBA and operating status
conditions. The internal registers
also control certain phases of the
data transfers between the SBI and
the MASSBUS device such as:
® maintaining a byte count to ensure
that all of the data to be trans-

ferred has been accounted for

® converting virtual addresses to
physical addresses for referencing

data in memory

228

Massbus Subsystem

The eight internal registers are:

MBA Configuration Register (CSR)
MBA Control Register (CR)
MBA Status Register (SR)

MBA Virtual Address Register (VAR)
MBA Byte Count Register (BCR)
MBA Diagnostic Register (DR)

MBA Selected Map Registef (SMR)

MBA Command Address Register (CAR)
NOTE

The selected map register and the command
address register are read only and are valid only
during data transfers.

The MBA contains 256 32-bit map registers which are used to map
program virtual addresses into SBI physical addresses. Bits <30:21>
of the map register are reserved and are not writable. The mapping
registers allow transfers to or from contiguous or non-contiguous
physical memory. Figure 10-4 illustrates the mapping of a virtual address to an SBI address.

CONTROL PATH

the
The control path handles the transfer of control data to and frommap
space
s
addres
MBA
the
of
s
section
MASSBUS devices. Certain
into registers physically located within MASSBUS devices. The MASSBUS control path is used to communicate with these data path registers.

US
The data path controls the data transferred to and from the MASSB
(2
16-bit
into
d
device and the SBI. The 32-bit SBI data word is divide
ming
perfor
When
US.
byte) segments required as data on the MASSB
8-bit
a read from MASSBUS device the data path assembles the two
inand
silo
A
format.
SBI
32-bit
the
into
US
bytes from the MASSB
data
the
ing
put/output data buffer provide the means for smooth
transfer rate. The data path also contains a write check circuitthewhich
data
can be used under program control to verify the accuracy of
transfer function.

MBA ACCESS

Each SBI device (NEXUS) is assigned a 2048, 32-bit jongwordof (8K
byte) control address space. This space is accessible as part the
229

Massbus Subsystem

17 16

VIRTUAL

ADDRESS

MAP POINTER

210

LONG WORD

JBYTE

%/*/ D

INDEX INTO MAP REGISTERS

MAP

31 30
|

v!|

REGISTERS

21 20
RESERVED

o
PHYS

PAGE ADDRESS

DIRECT

TRANSFER

27
SBI

ADDRESS

Figure 10-4

NG
PHYSICAL PAGE ADDRESS

’

Virtual To SBI Address Translation

SBI 1/0 longword address space. The comma

to access the MBA registers is illustrated

29 28

17 16

B
TRANSFER
UEST

IO----------OREQ

LEVEL

nd/address format used

in Figure 10-5.

R1NIOY
M
OfA

0
VARIABLE

LINT. OR EXT.
Figure 10-5

MASSBUS Adapter Addressing Forma
Address)
230

t (Physical Byte

Massbus Subsystem

Bit <29> =1

I/O Address space

Bits <28:17>

All zeros

Bits <16:13>

Transfer request number of this
MBA

Bits <11:10>

MBA internal register

Bits<9:5>=must be zero

Bits <4:0> =register select offset

MBA external register

> =device select
Bits<9:7
Bits<6:0> =register select

MBA MAP

Bits<9:0>=MAP address

Invalid (No response to an ad-

dress with these bits on)

INTERNAL REGISTERS
The MBA internal registers are described as follows:

MBA Configuration/Status Register (Byte Offset=0)

FAULT STATUS

ADAPTER

ALERT OR

DEPENDENT STATUS

INTERRUPT STATUS

8 7

6 15

24 23

ADAPTER - CODE

Bit <31> SBI parity error

Set when an SBI parity error is detected. Cleared by power fail or the
deassertion of fault signal. Setting of this bit will cause fault to be
asserted on SBI.

Bit <30> Write data sequence(WS)

Set when no write data is received (neither tag=write data nor ID)
following a write command. Cleared by power fail or the deassertion of
fault signal. The setting of this bit will cause the assertion of fault on

231

—

power fail or the deassertion of fault signal. The settin

cause assertion of fault on SBI.

[(@]

Bit <29> Unexpected read data (URD)
Set when read daia is received when it is not €

SBl.

Massbus Subsystem

Bit <28> This bit must be zero.
Bit <27> Multiple transmitter (MT)

Set when the ID on the SBI does not agree with the ID transmitted by

MBA while MBA is transmitting information on the SBI. Cleared by
power fail or the deassertion of fault signal. The setting of this bit will

cause the assertion of fault on SBI.

(Fault signal will be asserted at the normal confirmation time for one
cycle if MBA detects one of the fault conditions. The negation of the

fault signal on the SBI will clear all the fault status bits).
Bit <26> XMTFLT

Set when SBI fault is detected at the second cycle after MBA transmits
information to the SBI. Cleared by power fail or the deassertion of fault
signal.

Bits <25:24> Zeros
Reserved for future use.

Bit <23> Adapter power down (PD)
Set when the MBA receives assertion of AC LO. Clear when MBA
power goes up. Cleared by assertion of INIT, UNJAM, DC LO, or writing one to this bit. The setting of this bit will cause interrupt to CPU.

Bit <22> Adapter power up (PU)
Set when MBA receives the deassertion of AC LO. Reset when MBA
power goes down. Cleared by assertion of INIT, UNJAM, DC LO or

writing a one to this bit. The setting of this bit will set |E bit and
interrupt CPU.

Bit <21> Over temperature (OT)
Zero

Bits <20:8> All zeros
Reserved for future use.

Bits <7:0>
Each adapter is assigned a unique code identifying it.
MBA adapter code is:
Bits <7:0>=00100000

232

Massbus Subsystem

MBA Control Register (Byte Offset =4)

4 3210

Bits <31:4> All zeros
Reserved for future use.

enance Mode

Bit <3> MB Maint
which will
The setting of this bit will put MBA in the maintenance mode
MASSthe
ne
exami
and
se
exerci
to
ammer
allow the diagnostic progr
set,
is
bit
BUS operations without a MASSBUS device. When this so that allMBA
the
will block RUN, DEM, and assert FAIL to MASSBUS The MBA canBUS.
MASS
the
from
devices on MASSBUS will detach

ss.

not be put in maintenance mode while a data transfer is in progre
Bit <2> Interrupt Enable

upt CPU
Set by writing a one or power up which allows MBA toorinterr
INIT.
when certain conditions occur. Cleared by writing zero
Bit <1> ABORT

will initiate
Abort data transfer. Write one to set. The setting of thisngbitcomma
nds,
sendi
stop
the data transfer abort sequences which will
stop address and byte counter.

Negate.Run.

Assert EXEC to MASSBUS.
Wait for EBL.

Set DTABT to one at the trailing edge of EBL.
Interrupt CPU if IE bitis one.

This bit will be cleared by writing a zero, INIT or UNJAM.
Bit <0> Initialization (INIT)

The bit is self-clearing. It will always read as zero. The setting of this bit
will:

Clear status bits in MBA Configurator register.
Clear ABORT and IE in MBA Control register.
'
Clear MBA Status register.
Clear MBA Byte Count register.

Clear control and status bits of diagnostic registers.
233

Massbus Subsystem

Cancel all pending commands excep

t Read Data Pending.

Abort data transfer.

Assert MASSBUS INIT.
MBA Status Register (Byte Offse

t=8)

31
0

Bit <31> DTBUSY
Data transfer busy.

Bit is set when a data transfer
command is

received. It is cleared when data
transfer is terminated normally or
when a data transfer is aborted.

Bit <30> NRCONF

No response confirmation. This bit

is set when the MBA receives a no

résponse confirmation for
the read command or write
command and

write data sent to the SBI. It is
cleared by writing a one to the
bit or
INIT. The setting of this bit will cause
retry of the command.

Bit <29> CRD
Corrected read data. This bit is set
when TAG of read data received
from memory is CRD. It is cleared by
writing a one to this bit or by INIT.

Bits <28:20>
All zeros. Reserved for future use.

Bit <19> PGE
The PGE bit is set when one or more

of the following conditions exists:

Program tries to initiate a Data Transf

er when MBA is currently per-

forming one.

Program tries to load MAP, VAR,
or Byte counter when

rently performing a Data Transfer

operation.

Program tries to set MB Maintenanc
e Mode

operation.

The bit is cleared by writing a one.
interrupt to the CPU if IE is set.

Bit <18> NFD

MBA is cur-

during a Data Transfer

The setting of this bit will cause an

Nonexisting drive. This bit is set when

1.5 usecs after assertion of DEM. The

drive fails to assert TRA within
bit is cleared by writing a one to

the bit. The setting of this bit will send
zero read data back to the SBI,
and interrupt CPU if IE is set.

234

Massbus Subsystem

Bit <17> MCPE

MASSBUS control parity error. This bit is set when a MASSBUS control parity error occurs. It is cleared by writing a one to the bit. The
setting of this bit will cause an interrupt to CPUIf IE is set.
A

Bit <16> ATTN

Attention from MASSBUS. Asserted when the attention line in the
MASSBUS is asserted. The assertion of this bit will cause an interrupt
to the CPU if IE is set.
Bits <15:14>

All zeros. Reserved for future use.
Bit <13> DT CMP

Data transfer completed. This bit is set when the data transfer is terminated either due to an error or normal completion. [t is cleared by
writing a one to this bit or INIT. The setting of this bit will cause an
interrupt to the CPU if IE bit in control register is set.
Bit <12> DTABT

Data transfer aborted. This bit is set with the trailing edge of the EBL
when data transfer has been aborted. It is cleared by writing a one to
this bit or INIT. The setting of this bit will cause an interrupt to the CPU
if IE bitis set.

Bit <11> DLT

Data late. This bit is set when:

1) for a write data transfer or write check data transfer, data buffer is
empty when WCLK is sent to MASSBUS or

2) for a read data transfer, the data buffer is full while SCLK isit
received from MASSBUS. This bit is cleared by writing a one to
or INIT. The setting of this bit will cause the data transfer operation
to be aborted.

DLT will most likely be set if the system is in single step operation and
if the MBA is not in maintenance mode.
Bit <10> WCK UP ERR

Write Check Upper Error. This bit is set when a compare error is
detected in the upper byte while MBA is performing a write check
operation. It is cleared by writing a one to this bit or INIT. The setting of
this bit will cause the data transfer operation to be aborted.
Bit <09> WCK LWR ERR

is
Write Check Lower Error. This bit is set when a compare error
check
write
a
ming
detected in the lower byte while MBA is perfor
235

Massbus Subsystem

operation. It is cleared by writing a one

to this bit or INIT. The setting of

this bit will cause the data transfer operat

ion to be aborted.

Bit <08> MXF
Miss transfer error. This bit is set when

an SCLK or OCC is not rer busy is set. It is cleared by

ceived within 500 usec after data transfe

writing a one to this bit or INIT. The
setting of

interrupt to the CPU if IE bit in control registe

this bit will cause an

r is set.

Bit <07> MBEXC

MASSBUS Exception. This bit is set when
EXC is received from
MASSBUS. It is cleared by writing a one to
this bit or INIT. The setting

of this bit will cause the data transfer operat

ion to be aborted.

Bit <06> MDPE
MASSBUS data parity error. This bit is set

when the MASSBUS data

parity error is detected during a read
data transfer operation. It is

cleared by writing a one to the bit or INIT.
The setting

cause the data transfer operation to be

of this bit will

aborted.

Bit <05> MAPPE
Page Frame Map Parity Error. This bit
is set when a parity error is
detected on the page frame number read
from the PF map. It is
cleared by writing a one to this bit or INIT.
The setting of this bit will

cause the data transfer operation to

be aborted.

Bit <04> INVMAP
Invalid map. This bit is set when the valid
bit of the

number is zero when byte count is not zero.

one to this bit or INIT. The setting of this

operation to be aborted.

next page frame
It is cleared by writing a

bit will cause the data transfer

Bit <03> ERR CONF
Error Confirmation. This bit is set when
the MBA receives an error

confirmation for the read command or write

command. ltis cleared by
of this bit will cause the data

writing a one to this bit or INIT. The setting

transfer operation to be aborted.

Bit <02> RDS
Read Data Substitute. This bit is set when
the tag of the read data

received from memory is read data substit

one to this bit or INIT. The setting of

operation to be aborted.

ute. It is cleared by writing a

this bit will cause the data transfer

Bit <01> IS TIMEOUT
Interface Sequence Timeout. An interface
236

sequence is defined as the

Massbus Subsystem

time from when arbitration for the SBI is begun until:

ACK is received for a command address transfer that specifies
)

read or,

2)
.

ACK is received for a command address transfer that specifies

write and ACK is also received for each transmission of write data
or,

ERR confirmation is received for any command/address transfer.

The maximum timeout is 102.4 usecs. The setting of this bit will
cause data transfer abort. Cleared by writing a one to this bit or
INIT.

Bit <00> RD TIMEOUT

Read Data Timeout is defined as the time from when an interface
sequence that specifies a read command is completed to the time that
the specified read data is returned to the commander. The maximum
time out is 102.4 usecs. The setting of this bit will cause data transfer
abort. Cleared by writing a one to this bit or INIT.

MBA Virtual Address Register (Byte Offset=12)
31
0

MAP SELECT

9 8

17 16

BYTE OFFSET

The program must load an initial virtual address (pointing to the first
byte to be transferred) into this register before a data transfer is initiated. Bits 9 through 16 select one of 256 map registers. The contents of
the selected map register and the values in bits 0 through 8 are used to
assemble a physical SBI address to be sent to memory. Bits 0 through
8 indicate the byte offset into the page of the current data byte. Note
the MBA virtual address register is incremented by 8 after every memory read or write and will not point to the next byte to be transferred if
the transfer does not end on a quadword boundary. (It will point 8
bytes ahead.) Also upon a write check error, the virtual address register will not point to the failing data in memory due to the preloading of
the silo data buffer. The virtual address of the bad data may be found

by determining the number of bytes actually compared to the MASSBUS (the difference between bits 16 to 31 of RS04 and their initial

value) and adding that difference to the initial virtual address.

237

Massbus Subsystem

MBA Byte Counter (Byte Offset=16)
31

16 15
MASSBUS BYTE COUNTER (READ ONLY)

0
SBI BYTE COUNTER (READ/WRITE)

Program loads the 2's complement of the number of bytes for the data
transfer to bits <15:0> of this register. MBA hardware will load these

16 bits into bits <31:16>. Bits <31:16> serve as the byte counter for
the number of bytes transferred through the SBI interface. The starting

byte count with 16 bits of 0's is the maximum number of bytes of a data

transfer.

Diagnostic Register (Byte Offset=20)

The diagnostic register may only be read or written while in maintenance mode. Care must be taken while reading or bit-setting this
register to insure that the data path is not loading the silo. If the data

path is loading the silo while this register is read, the data may be

altered.

Bit <31> IMDPG
Invert MASSBUS Data Parity Generator.

Bit <30> IMCPG
Invert MASSBUS Control Parity Generator.

Bit <29> IMAPP
Invert Map Parity.

Bit <28> BLKSCOM
Block Sending Command to SBI. During a data transfer, the setting of
this bit will eventually cause a DLT bit set and CPU interrupt.

Bit <27> SIMSCLK

Simulate SCLK. When MMM bit is set, writing a one to this bit will
simulate the assertion of SCLK, and writing a zero to this bit will simu-

late the deassertion of SCLK.

Bit <26> SIMEBL

Simulate EBL. When MMM bit is set, writing a one and writing a zero to
238

Massbus Subsystem

this bit will simulate the assertion and deassertion of EBL.
Bit <25> SIMOCC

Simulate OCC. When MMM bit is set, writing a one and writing a zero
to this bit will simulate the assertion and deassertion of OCC.
Bit <24> SIMATTN

Simulate ATTN. When MMM bit is set, writing a one and writing a zero
to this bit will simulate the assertion and deassertion of ATTN.
Bit <23> MDIB SEL

Maintenance MASSBUS Data Input Buffer Select. When the bit is set

to one, the upper eight bits (B<15:8>) of MDIB will be sent out from
B<7:0> of Diagnostic Register if the Diagnostic Register is read.
When this bit is zero, the lower eight bits (B<7:0>) of MDIB will be sent
out from B<7:0> of Diagnostic Register if a bit is read.
Bits <22:21> MAINT ONLY

Read/write with no effect. (Used to test writability of these bits).
Bit <20> MFAIL

MASSBUS Fail (read-only). Fail is asserted when MMM is set.
Bit <19> MRUN

Maintenance MASSBUS Run (read-only).
Bit <18> MWCLK

Maintenance MASSBUS WCLK (read-only).

Bit <17> MFXC

Maintenance MASSBUS FXC (read-only).
Bit <16> MCTOD

Maintenance MASSBUS MCTOD (read-only).
Bits <15:13> MDS

Maintenance MASSBUS Device Select (read-only).
Bits <12:8> MRS

Maintenance MASSBUS Register Select (read-only).
Bits <7:0> U/L MDIB

Maintenance Upper/Lower MDIB.

Selected Map Register (Byte Offset =24)

This register is read-only and has the same format as a map register
but is valid only when DT Busy is set. This is the contents of the map
register pointed to by bits 16 through 9 of the virtual address register.
239

Command Address Register (Byte Offset=28)

This register is read-only and valid only

when DT Busy is set. It is the

value of bits <31:0> of the SBI during the

the MBA's next data transfer cycle.

Command/Address part of

MBA External Register (Byte Offset=400 to
7FC)
External registers are MASSBUS device-depende
nt. Each device has

a maximum of 32 registers.

MBA Map (Byte Offset=800 to BFC)
3)

Bit <31>
Valid Bit

Bits <30:21>
Zeros. Reserved for future use.

Bits <20:0>

Physical Page Frame Number.
The MBA contains 256 map registers, each of which

may be selected
by address bits 0 to 9 when bits <11:10> are 10. Map registers
can

only be written when there is no data transfer operation in progress. A

write to a map register during a data transfer will be ignored

the setting of PGE.

and cause

Data Transfer Program Flow
1)

Initialize MASSBUS Adapter.

Mount pack into drive.

Startdrive spinning.

Wait for ready light.

Issue Pack ACK to drive.

Load desired cylinder, sector, track, and

Load starting virtual address into MBA'’s virtual

registers in drive.

address register.
Load 2's complement of number of bytes
to be transferred into
byte count register in MBA.

Load starting map (pointed to by bits <9:16>

cal page address.

10) Load successive maps with physical
addres
11) Issue read/write command to drive.
240

of VAR) with physi-

ses to rest of pages.

Massbus Subsystem

EXAMPLE

Presented is a program to read data from the RP05/RP06 disk subsystem into memory. The program is written in the VAX-11 MACRO assembly language. It is not meant to run with memory management
enabled, and will not run under VAX/VMS. This program illustrates the
procedures involved in setting up the MASSBUS adapter to transfer
bytes of data to memory. In order to run the program, it must be
loaded from the floppy disk by the console into memory. Initially, the
program can be assembled and linked under VAX/VMS and then
transferred to the floppy disk using the RSX-11M utility program FLX.

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243

244

CHAPTER 11

PRIVILEGED REGISTERS
INTRODUCTION

The processor register space provides access to many types of CPU
control and status registers such as the memory management base

registers, the PSL, and the multiple stack pointers. These registers are
explicitly accessible only by the Move to Processor Register (MTPR)
and Move from Processor Register (MFPR) instructions which require
kernel mode privileges. This chapter describes those privileged processor registers not found elsewhere in this handbook.

Appendix D contains a description of the ID Bus registers of which the
privileged processor registers are a subset. Therefore, those registers
containing a processor address are privileged and can be accessed
via the MTPR and MFPR instructions only. Chapter 2, Console Subsystem, contains a description of the ID Bus.

SYSTEM IDENTIFICATION REGISTERS (SID)

The system identification register is a read-only constant register that
specifies the processor type. The entire SID register is included in the
error log and the type field may be used by software to distinguish
processor types. Figure 11-1 illustrates the system identification register.

24 23

TYPE SPECIFIC

TYPE

Figure 11-1

System Identification Register

A unique number assigned by engineering to identify

Type

a specific processor:

Reserved to DIGITAL (error)

VAX-11/780
245

Privileged Registers

2 through 127

Reserved to DIGITAL

128 through 255

Reserved to CSS
and customers

Type specific

Format and content are a function of the value in

type. They are intended to include such information
as serial number and revision level.

For the VAX-11/780, the type specific format is:

ECO LEVEL

PLANT

SERIAL NUMBER

CONSOLE TERMINAL REGISTERS
The console terminal is accessed through four internal
are associated with receiving from the terminal and two

registers. Two

with writing to
the terminal. In each direction there is a control/status register
and a

data buffer register. Figure 11-2 illustrates the console receive
con-

MBZ

Figure 11-2

o
m—

Z09|~

T‘“Tg

trol/status register.

Console Receive Control/Status Register (RXCS)

Figure 11-3 illustrates the read-only console receive

161514

Figure

11-3

MBZ

E
E

data buffer

DATA

Console Receive Data Buffer Register (RXDB)

At bootstrap time, RXCS is initialized to 0. Wheneve
r a datum is received, the read-only bit DONe is set by the console.
If IE (interrupt

enable) is set by the software, then an interrupt

is generated at interrupt priority level (IPL) 20. Similarly, if DONe
is already set and the

246

Privileged Registers

software sets IE, an interrupt is generated (i.e., an interrupt is generated whenever the function (IE and DON) changes from 0 to 1). If the
received data contained an error such as overrun or loss of connec-

tion, then ERR is set in RXDB. The received data appears in DATA.
When an MFPR #RXDB,dst is executed, DONe is cleared as is any
interrupt request. If ID is 0 then the data is from the console terminal. If
ID is non-zero, then the entire register is implementation dependent.
In the case of the VAX-11/780, if ID = 1, data is from the floppy disk.
At bootstrap time, TXCS is initialized with just the RDY bit set (ready).
Whenever the console transmitter is not busy, it sets the read-only bit
RDY. If IE (interrupt enable) is set by the software, then an interrupt is
generated at IPL 20. Similarly, if RDY is already set and the software
sets IE, an interrupt is generated (i.e., an interrupt is generated
whenever the function (IE AND RDY) changes from O to 1). The soft-

ware can send a datum by writing it to DATA. When an MTPR src.#

TXDB is executed, RDY is cleared as is any interrupt request. If IDis

written 0, then the datum is sent to the console terminal. if ID is non-

Figure 11-4

mr o

8
MBZ

MBZ

Q= |=<0Ox|~N

zero, then the entire register is implementation dependent. In the case
of VAX-11/780, if ID = 1, data is sent to the floppy disk. Figure 11-4
ilustrates the console transmit control/status register.

Console Transmit Control/Status Register (TXCS)

Figure 11-5 illustrates the read-only console transmit data buffer
register.

12 1

MBZ

Figure 11-5

7
DATA

Console Transmit Data Buffer Register (TXDB)

CLOCK REGISTERS

The clocks consist of an optional time-of-year clock and a mandatory
interval clock. The time-of-year clock is used to measure the duration
247

Privileged Registers

of power failures and is required by the operating system for unattended restart after a power failure. The interval clock is used for accounting, for time-dependent events, and to maintain the software date and

time.
Time-of-Year Clock (optional)
The time-of-year clock consists of one longword register. The register
forms an unsigned 32-bit binary counter that is driven by a precision
clock source with at least .0025% accuracy (approximately 65 seconds
per month). The counter has a battery back-up power supply sufficient
for at least 100 hours of operation, and the clock does not gain or lose
any ticks during transition to or from stand-by power. The battery is

recharged automatically. The least significant bit of the counter represents a resolution of 10 milliseconds. Thus, the counter cycles to 0

after approximately 497 days.

If the battery has failed, so that time is not accurate, then the register is
cleared upon power up. It then starts counting from 0. Thus, if software
initializes this clock to a value corresponding to a large time (e.g., a

month), it can check for loss of time after a power restore by checking
the clock value. The time-of-year clock register is illustrated in Figure
11-6.

0
TIME

Figure 11-6

OF YEAR SINCE

SETTING

Time-of-Year Clock Register (TODR)

A value written to TODR with <27:0> non-zero results in an UNPREDICTABLE value in TODR. If the clock is not installed, then the clock
always reads out as 0 and ignores writes.

Interval Clock
The interval clock provides an interrupt at IPL 24 at programmed
intervals. The counter is incremented at 1 usec intervals, with at least
.01% accuracy (8.64 seconds per day). The clock interface consists of
three registers in the privileged register space: the read-only interval
count register, the write-only next interval count register, and the

interval clock control/status register.

Figure 11-7 illustrates the interval count register.

248

Privileged Registers

0
INTERVAL

Figure 11-7

COUNT

Interval Count Register (ICR)

Figure 11-8 illustrates the next interval count register.

3
NEXT INTERVAL COUNT

Figure 11-8

Next Interval Count Register (NICR)

Figure

11-9

MBZ

ZCcmlo

O
me

MBZ

31 30

—AZ =N

Figure 11-9illustrates the interval clock control/status register.

Interval Clock Control/Status Register (ICCS)

Interval Count Register

The interval register is a read-only register incremented once every
microsecond. it is automatically loaded from NICR upon a carry out
from bit 31 (overflow) which also interrupts at IPL 24 if the interrupt is
enabled.

Next Interval Count Register

The reload register is a write-only register that holds the value to be
loaded into ICR when it overflows. The value is retained when ICR is

loaded. NICR is capable of beifig loaded regardless of the current

values of ICR and ICCS.

Interval Clock Control/Status Register (ICCS)
The ICCS register contains control and status information for the interval clock.

ERR<31>

Whenever ICR overflows, if INT is already set, then ERR is set. Thus,
ERR indicates a missed clock tick. Attempt to set this bit via MTPR
clears ERR.
249

Privileged Registers

MBZ<30:8>
Must Be Zero.
INT<7>

Set by hardware every time ICR overflows. If IE is set then an interrupt
is also generated. An attempt to set this bit via MTPR clears INT,
thereby re-enabling the clock tick interrupt (if IE is set).

IE<6>

When set, an interrupt request at IPL 24 is generated every time ICR
overflows (INT is set). When clear, no interrupt is requested. Similarly,

if INT is already set and the software sets IE, an interrupt is generated
(i.e., an interrupt is generated whenever the function (IE AND INT)
changes from 0 to 1).

SGL<5>
A write-only bit. If RUN is clear, each time this bit is set, ICR is
incremented by one.

XFR<4>
A write-only bit. Each time this bit is set, NICR is transferred to ICR.

MBZ<3:1>
Must Be Zero.

RUN<O>
When set, ICR increments each microsecond. When clear, ICR does
not increment automatically. At bootstrap time, run is cleared.

Thus, to set up the interval clock, load the negative of the desired
interval into NICR. Then an MTPR #1X51,#ICCS will enable interrupts,
reload ICR with the NICR interval and set run. Every “interval count”

microseconds will cause INT to be set and an interrupt to be requested. The interrupt routing should execute an MTPR #{XC1,#ICCS to

clear the interrupt. If INT has not been cleared (i.e., if the interrupt has
not been handied) by the time of the.next ICR overflow, the ERR bit will
be set.

At bootstrap time, bits <6> and <0> of ICCS are cleared. The rest of

ICCS and the contents of NICR and ICR are UNPREDICTABLE.
VAX-11/780 ACCELERATOR

The VAX-11/780 processor has an optional accelerator for a subset of
the instructions. Two internal registers control the accelerator: ACCS

and ACCR.

ACCS is the accelerator control/status register. It indicates whether an
accelerator exists, controls whether it is enabled, identifies its type and
250

Privileged Registers

reports errors and status. At bootstrap time, the type and enable are
set: the errors are cleared. Figure 11-10 illustrates the accelerator
control/status register.

31 30 29 28 27 26

R[S
RIB
R|Z|F|F|V
R

MBZ

S0B

mez

8 7

R R R

000

Figure 11-10

16 15 14

Tve
YPE

Accelerator Control/Status Register (ACCS)

ERR<31>

Read-only bit specifying that at least one of bits RSV, OVF, and UNFis
set. Note that bits <31:27> are normally cleared by the main processor microcode before starting the next macro instruction.
MBZ<30>
Must Be Zero.
UNF<29>

Read-only bit specifying that the last operation had an underflow.
OVF<28>

Read-only bit specifying that the last operation had an overflow.
RSV<27>

Read-only bit specifying that the last operation had a reserved
'
operand.
MBZ<26:16>
Must Be Zero.
ENB<15>

Read/write field specifying whether the accelerator is enabled. At
bootstrap time, this is set if the accelerator is installed and functioning.

An attempt to set this is ignored if no accelerator is installed.
TYPE<7:0>

Read-only field specifying the accelerator type as follows:

0 = No accelerator

1 = Floating point accelerator

Numbers in the range 2 through 127 are reserved to DIGITAL. Numbers in the range 128 through 255 are reserved to CSS/customers.
251

Privileged Registers

The accelerator maintenance register (ACCR) controls the accelera-

tor’'s microprogram counter. At bootstrap time its contents
are UNPREDICTABLE. Figure 11-11 illustrates the accelerator maintenan
ce
register.

24 23

T
L

MBZ

Figure 11-11

TRAP ADDRESS

14 13

IC\

9
MBZ

(CINe]

0
MICRO

Accelerator Maintenance Register (ACCR)

ETL<31>
Enable Trap Address Load. A write-only bit that

when set causes <23:
16> to be loaded into the accelerator’s trap address
register. Subse-

quently, the main processor’'s microcode can force
the accelerator to
trap to this location by asserting an internal
signal.

MBZ <30:24>
Must Be Zero.

TRAP<23:16>
Trap Address. A read/write field used by the main processo

r to force

the accelerator to a specified micro location.

EML<15>
Enable Micro PC Match Load. A write-only bit that
when set causes
<8:0> to be loaded into the accelerator’s micro PC match
register.

MPM<14>
Micro PC Match. A read-only bit that is set wheneve

r the accelerator’s
micro PC matches the micro PC match register.
This is useful
primarily as a scope sync signal.

MBZ<13:9>

Must Be Zero.
PC<8:0>

Next Micro PC on read. This contains the next micro
address to be

executed.

Match Micro PC on write. If EML is also set, then
this updates the

micro PC match register.

VAX-11/780 MICRO CONTROL STORE
The VAX-11/780 processor has three registers for control/s

tatus of its

252

Priviieged Registers

microcode. Two are used for writing into any writable control store
(WCS) and one is used to control micro breakpoints. Figure 11-12
illustrates the writable control store address register.

1615 14 13 12

]

WCS ADDR

'£| CTR

MBZ

Writable Control Store Address Register (WCSA)

Figure 11-12

Figure 11-13 illustrates the writable control store data register.
0

A
WCS DATA

8 7

PRESENT

Figure 11-13

Writable Control Store Data Register (WCSD)

Reading WCSD indicates which control store addresses are writable.
If WCSD<n> is set, then addresses n*1024 through n*1024+1023 are
writable (i.e., that WCSA<12:10> EQLU n corresponds to writable
control store). n=4 corresponds to WCS that is reserved to DIGITAL

for diagnostics and engineering change orders. Other fields correspond to blocks of control that can be used to implement customer or
CSS specific microcode. Each word of control store contains 96 bits
plus 3 parity bits. To write one or more words, initialize WCS ADDR to
the address and CTR to 0. Then each MTPR to WCSD will write the

next 32 bits and automatically increment CTR. When CTR becomes 3,
it is automatically cleared and WCS ADDR is incremented. If PIN is set,

then any writes to WCSD are done with inverted parity. An attempt to

execute a microword with bad parity results in a machine check. At
bootstrap time, the contents of WCSA are UNPREDICTABLE. Figure
11-14 illustrates the microprogram breakpoint address register.
31

Figure 11-14

13 12

Mmaz

MICRO PC

Microprogram Breakpoint Address Register (MBRK)
253

]

Privileged Registers

Whenever the microprogram PC matches the
contents of MBRK, an

external signal is asserted. If the console
has enabled stop on micro-

break, then the processor clock is stopped

when this signal is assert-

ed. If the console has not enabled microbr
eak, then this signal is

available as a diagnostic scope point. Many diagnos

instruction to trigger this method of giving

tics use the NOP

a scope point. At bootstrap

time, the contents of MBRK are UNPREDICTABLE.

254

255

dhaital

T
T

CHAPTER 12

PRIVILEGE INSTRUCTIONS

n
ss to privilege operations withi
The privilege instructions allowgeacce
cona
ide
prov
ns
uctio
e instr
the VAX-11 system. The chan egedmodsoft
ware 1o request services of
ivil
unpr
for
m
anis
mech
trolled
ns
cular, the change mode instructio
more privileged software. In partiexec
or
or,
rvis
supe
e,
uting at executiv
are the only normal way for codeto a mor
e privileged mode. in all cases,
ge
chan
to
es
mod
user access
ring
sfer control to a fixed location
the change mode results inthetran
k.
depending upon contents of System Control Bloc
to a
ware executing in response tion
The probe instructions allow soft
s
loca
al
virtu
d
ifie
spec
sibility of
change mode to probe the acces
verican
ware
soft
leged
privi
,
Thus
by the program that changed moe.
could be
fy that the arguments passed to it represent locations that
accessed by its caller.
m
n provides a controlled mechanis
The extended function instructio
the
in
e
ocod
micr
dard
stan
nonof
for software to request services
mode.
r software running in kernel Bloc
writable control store or simuthelato
k.
rol
Cont
em
The request is controlled by contents of the Syst provide softr register instructions registers
The move to and from processo
access to the internal control memoware executing in kernel modesuch
operations as control of the ess
ws
of the processor. This allo
tion of the address of the Proc
ry management system and selec
te. The load and save procControl Block of the next process to execu
e software to save and
mod
el
kern
allow
ess context instructions ter
memory management status of a
restore the general regis and
s.
proccess when switching between processe
associthe
Refer to Appendix G for a description of symbolic notation

INTRODUCTION

ated with the instruction descriptions.
257

Privilege Instructions

CHM

CHANGE MODE
Purpose:

request services of more

privileged software

Format:

opcode

Operation:

if PSL<IS> EQLU 1{then

code.rw

HALT;

lilegal from
Interrupt stack

{switch stack pointer from
current-mode to MINU (opc
ode-

mode, PSL<current-mode

>) b

—(SP)

«~—PSL;

—(SP)

«~—PC;

—(SP)

«<SEXT (code);

linitiate CHMx

exception

PSL <CM, TP, FPD, DV, FU,I

V,T,N,Z, V,C> «0:

Iclean out PSL

PSL<previous-mode>
«<PSL<current-mode>:
PSL<current-mode>
+<MINU (opcode-mode,

PSL<current-mode>);
Imaximize
PC <-{SCB vector

Condition

Codes:

for opcode-mode};

privilege

Z<0;
N «0;

V«0:

C <0
Exceptions:

hait

Opcodes:

BC
BD

BE
BF

Description:

CHMK

Change Mode to Kern
el
Change Mode to Exec
utive
Change Mode to Supe
rvisor

CHME

CHMS
CHMU

Change Mode to User

Change Mode Instruct
ions allow proc

essors to change

their
access mode in
a controlled mann
er. The instruct
ion only ine (i.e., decreases
the access mode).

Creases privileg

A change in mode
also results in a cha
nge of stack pointers
;
the old pointer is save
d, the new pointer is
loaded. The PSL,
PC, and code passed
by the instruction are
pushed onto the
stack of
the new mode. The

tion following the CHM
ed. After execution,

saved PC addresse
s the

x instruction. The cod

the new stack’s appe

sign extended

arance is:

code

PC of next instruction

old PSL

258

instruc-

e is sign extend-

:(SP)

Privilege Instructions

CHM

Notes:

The destination mode selected by the opcode is used to select
a location from the System Control Block. This location
addresses the CHMx dispatcher for the specified mode.
By software convention, negative codes are reserved to CSS

Example:

CHMK #7

‘request the kernel mode service

CHME #4

:request the executive mode service

and customers.

CHMS #-2

:specified by code 7

:specified by code 4

:request the supervisor mode service

:specified by customer code —2

259

PROBE

PROBE ACCESSIBILITY

Purpose:

verify that arugments can be

Format:

Opcode mode.rb, len.rw, base.

Operation:

probe-mode < MAXU(mode<
1 0>, PSL<previousr-mode>);
condition codes < jaccessibility
of (base) | and jaccessiblity
of (base + ZEXT(len)-1)} using
probe-modej;

accessed

Condition

N <« 0:

Codes:

Z «if both accessible then 0; else

V«0;

C<0
Exceptions:

Opcodes:

Description:

translation not valid

PROBER

PROBEW

Probe Read Accessibility
Probe Write Accessibility

The PROBE instruction check
s the read or write accessibilit
y
of the first and last byte specified
by the base address and the

zero extended length. Note
that the bytes in between
are not

checked. System software must
check all

two end bytes it they are to be

pages between the

accessed.

The protection is checked again
st the mode specified in bits
<1:0> of the mode operand
that is restricted (by maximization) from being more privil
eged than the previous acces
s
mode field of the PSL. Note

equivalent

PSL<previous-mode>.

that probing with a mode opera

probing

the

mode specified

Probing an address only retur
page(s) and has no affect on their

ns the accessibility of the

residency. However, probing

a process address may
cause a page fault in the
system ad-

dress space on the per-process

page tables.

Notes:

Example:

MOVL

4(AP),R0

PROBER

#0,.#4,R0O

;Copy address of first arg so
;that it can’t be changed
;verify that the longword pointe
;to by the first argument could
;read by the previous acces

mode

;Note that the argument list

itself

MOVQ

8(AP),RO

;must aiready have been probe

;copy length and address
;of buffer arguments so that

;they can’t change

260

Privilege Instructions

PROBE

PROBEW

$0,R0,R1

-verify that the buffer described
:by the second and third arguments

:could be written by the previous
;access mode

:Note that the argument list must
-already have been probed and
that

‘the second argument must be
known

:to be less than 514

261

XFC

EXTENDED FUNCTION CALL
Purpose:

Format:

provide for customer extensions

Operation:

{XFC fault};

Condition

N «0;

Codes:

to the instruction set

opcode

Z<0;
V «0;

C <0
Exceptions:

opcode reserved to customer
customer reserved exception

Opcodes:

Description:

This instruction requests services of

XFC

Extended Function Cali

non-standard microcode

or software. If no special microc
ode is loaded

then an excep-

tion is generated to a kernel mode
software simulator (see
Chapter 12). Typically, the next byte
would specify which of

several extended functions are
requested. Parameters would

be passed either as normal operan

ds, or more likely in fixed

registers.

262

Privilege Instructions

MFPR

MTPR
MOVE FROM PRIVILEGED REGISTER

MOVE TO PRIVILEGED REGISTER
Purpose:

Format:
Operation:

provide access to the internal privileged regsters

opcode src.rl, regnumber.rl

opcode regnumber.rl, dst.wl

MFPR

if PSL<current-mode> NEQU kernel then {reserved instruction falt};

PRS [regnumber] < src;
dst <«<PRS[regnumber];

Condition
Codes:

MTPR

IMTRP
IMFPR

N < dst LSS 0;
Z < dstEQL G;
V<0

C <« C;

Exceptions:

reserved operand
reserved instruction

Opcodes:

Description:

Notes:

DA
DB

MTPR
MFPR

Move to Privileged Register

Move from Privileged Register

The specified register is loaded or stored. The regnumber op-

erand is a longword that contains the privileged register
number. Execution may have register-specific side effects.
A reserved operand fault occurs if the privileged register
1.
does not exist or is read only for MTPR or write-only for
MFPR. It also occurs on some invalid operands to some
registers.

A reserved instruction fault occurs if instruction execution
is attempted in other than kernel mode.

The following table is a summary of the registers accessible in the privileged
register space.

The “type” column indicates read-only (R), read/write (R/W), or write-only (W)
characteristics.

“Scope” indicates whether a register is per-CPU or per-process. The implicaton is that, in general, registers labeled “CPU" are manipulated only through
software via the MTPR and MFPR instructions. Per-process registers, on the
other hand, are manipulated implicity by context switch instructions. The “init”

column indicates that the register is (“yes”) or is not (“no”) set to some predefined value (note: not necessarily cleared) by a processor initialization command. A “—” indicates initialization is optional.

The number of a register, once assigned, will not change across implementations or within an implementation. Implementation-dependent registers are
263

MFPR

MTPR
assigned distinct addresses for each implementation. Thus, any

privileged register present on more than one implementation will perform the same
function
whenever implemented. All unsigned positive numbers are
reserved to

DIGITAL; all negative numbers (i.e., with bit 31 set) are reserved
to CSS and

customers.

Each register number has a symbol formed as PR$_ followed by
mnemonic.

the register’s

VAX-11 Series Registers

Mne-

Num-

monic

ber

Kernel Stack Pointer

Type

Scope

Init?

KSP

R/W

PROC

—
—

Executive Stack Pointer

ESP

R/W

Supervisor Stack Pointer

PROC

SSP

R/W

User Stack Pointer

PROC

—

UsP

R/W

PROC

—

Interrupt Stack Pointer

ISP

R/W

CPU

PO Base Register

—

POBR

R/W

PROC

—

PO Length Register

POLR

R/W

RPOC

P1 Base Register

—

P1BR

R/W

P1 Length Register

RPOC

—

P1LR

R/W

System Base Register

PROC

—

SBR

R/W

System Length Register

CPU

—_

SLR

R/W

CPU

—
—

Process Control Block Base

PCBB

R/W

System Control Block Base

PROC

SCBB

R/W

Interrupt Priority Level

CPU

—

IPL

R/W

AST Level

CPU

yes

ASTLVL

R/W

Software Interrupt Request

PROC

yes

SIRR

Software Interrupt Summary

CPU

—

SISR

R/W

Interval Clock Control

CPU

yes

ICCS

R/W

Next Interval Count

CPU

yes

NICR

CPU

Interval Count

—

ICR

CPU

Time of Year (optional)

—

TODR

R/W

Console Receiver C/S

CPU

RXCS

R/W

Console Receiver D/B

CPU

yes

RXDB

Console Transmit C/S

CPU

—

TXCS

Console Transmit D/B

R/W

CPU

yes

TXDB

Memory Management Enable

CPU

—

MAPEN

R/W

CPU

yes

—

Trans. Buf. Invalidate Ali

TBIA

Trans. Buf. Invalidate Single

CPU

TBIS

CPU

Performance Monitor Enable

—

PMR

R/W

System |dentification

PROC

ves

SID

CPU

264

Privilege Instructions

MFPR

MTPR
VAX-11 Series Registers
Mne-

monic
ACCS

Accelerator Maintenance

ACCR

WCS data
SBI Fault/Status
SBI Silo
SBI Silo Comparator
SBI Maintenance
SBI Error Register
SBI Timeout Address
SBl Quadword Clear

WCSD
SBIFS
SBIS
SBISC
SBIMT
SBIER
SBITA
SIBQC

WCS address

Micro Program Breakpoint

Num-

ber Type
40 R/W

Init?
yes

R/W

CPU

45
48
49
50
51
52
53
54

R/W
R/W
R
R/W
R/W
R/W
R
W

CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU

yes
yes
no
yes
yes
yes
—
—

WCSA

44 R/W

MBRK

60 R/W

265

Scope
CPU

CpPU

Privilege Ins

LDPCTX

SVPCTX
LOAD PROCESS CONTEXT
SAVE PROCESS CONTEXT

Purpose:

save and restore register and memory management context

Format:

opcode

Operation:

if PSL<current-mode>NEQU 0
then {opcode reserved to DIGITAL faultj;
finvalidate per-process translation buffer entries};
ILDPCT]

jload process general registers from Process Control
Block};

{load process map, ASTLVL, and PME from PCB};
{save PSL and PC on stack for subsequent REI|:
{save process general registers into Process Control
Block!;

{remove PSL and PC from stack and save in PSBY;
{switch to Interrupt Stack};

Condition

N <« N;

Codes:

Z<+27;
V<V,

C <« C;

Exceptions:

reserved operand
reserved instruction

Opcodes:
Description:

LDPCTX

Load Process Context

SVPCTX

Save Process Context

The Process Control Block is specified by the internal processor register Process Control Block Base. The general registers

are loaded from or saved to the PCB. In the case of LDPCTX,
the memory management registers describing the process ad-

dress space are also loaded and the process entries in the

transiation buffer are cleared. If SVPCTX is executed while
running on the kernel stack, execution is switched to the inter-

rupt stack. When LDPCTX is executed, execution is switched

to the kernel stack. The PC and PSL are moved between the

PCB and the stack, suitable for use by a subsequent REI in-

struction.

266

267

268

CHAPTER 13

SYSTEM ARCHITECTURAL IMPLICATIONS
INTRODUCTION

Portions of the VAX-11 architecture have implications on the hardware
system structure. The areas of interaction are: data sharing and synchronization, restartability, interrupts and errors, and the /0 structure. Of these, data sharing is most visible to the programmer.
DATA SHARING AND SYNCHRONIZATION

Data (or instructions) may be shared among various entities including
programs, processors and |I/0 devices. Entities sharing data may do
so explicitly by referencing the same datum or implicitly by referencing different items within the same physical memory location.
In the VAX-11 architecture, implicit sharing is transparent to the programmer. The memory system must be implemented so that the basis
of access for independent modification is the byte. Note that this does
not imply a maximum reference size of one byte but only that
independent modifying accesses to adjacent bytes produce the same
results regardless of the order of execution. For example, locations 0
and 1 contain the values 5 and 6 respectively, and one processor
executes INCB 0 and another executes INCB 1. Then, regardiess of

the order of execution, including effectively simultaneous, the final
contents must be 6 and 7.

Access to explicitly shared data that may be written must be synchron-ized by the programmer or hardware designer. Before accessing
shared writable data, the programmer must acquire control of the data
structure. Five instructions are provided to permit interlocked access
to a control variable. BBSSI and BBCCI instructions use hardwareprovided primitive operations to make a read and then a write reference to a single bit within a single byte in an interlocked sequence.
The ADAWI instruction uses a hardware-provided primitive operation
to make a read and then a write operation to a single aligned word in
an interlocked sequence to allow counters to be maintained without

other intertocks. The INSQUE and REMQUE instructions use a hardware-provided primitive operation to make a series of aligned long269

Sysiern Architecturai impiications

word reads and writes in an interlocked method to allow queues to be

maintained without other interlocks. Use of the hardware primitives
guarantees that no read operation that is within the synchronizing part
of these instructions can occur between the synchronized reads and
the writes of these |nstruct|ons Hardware designers must use these
primitive operations dlrectly when making references in an interlocked
sequence. Hardware faults during an interlocked sequence must not

hang any processor. On the VAX-11/780, only interlocking instruc-

tions are locked out by the interlock.
The SBI primitive operations are interiock read and interiock write.
In order to provide a functionality upon which some UNIBUS
peripheral devices rely, processors must insure that all instructions
making byte- or word-sized modifying references (.mb and .mw) use
the DATIP - DATO/DATOB functions when the operand physical ad-

dress selects a UNIBUS device. This constraint does not apply to
longword, quadword, field, floating, double or string operations if implemented using byte- or word-modifying references. This constraint
also does not apply to instructions precluded from 1/0 space references.

The operation of the ADAWI instruction is interlocked against similiar
operations on other processors in a multiprocessor system.

In a multiprocessor system, any software clearing the V bit, or changing the protection code of a page table entry for system space that it

issues an MTPR xxx,#TBIS, must arrange for all other processors to

issue a similar TBIS. The original processor must wait until ali the
other processors have completed their TBIS before it allows access to

the system page.

CACHE
A hardware implementation may include a mechanism to reduce
access time by making local copies of recently used memory contents.

Such a mechanism is termed a cache. A cache must be implemented
in such a way that its existence is transparent to software (except for
timing and error reporting/control). In particular, the following must be
true:

Program writes to memory, followed by starting a peripheral out-

put transfer, must output the updated value.
2.

Completing a peripheral input transfer followed by the program

A write or modify followed by a HALT on one processor followed

reading of memory must read the input value.

by a read or modify on another processor must read the updated
value.

270

System Architectural Implications

A write or modify followed by a power failure, followed by restoration of power, followed by a read or modify, must read the updated value provided that the duration of the power failure does not
exceed the maximum nonvolatile period of the main memory.

In multiprocessor systems, access to variables shared between
processors must be interlocked by software executing BBxxl,

ADAWI, or xxxQUE instructions. In particular, the writer must execute an interlocking instruction after the write to release the inter-

lock, and the reader must execute a successful matching interlock
instruction before the read.

Valid accesses to i/0 registers must not be cached.

On the VAX-11/780, this is achieved by a cache that writes through to
memory and watches the memory bus for all external writes to memory.

At bootstrap time, the cache must be either empty or valid.
RESTARTABILITY

The VAX-11 architecture requires that all instructions be restartable
after a fault or interrupt that terminated execution before the instruction was completed. Generally, this means that modified registers are
restored to the value they had at'the start of execution. For some
complex or iterative instructions, intermediate results are stored in the
general registers. In the latter case, memory contents may have been
altered but the former case requires that no operand be written unless
the instruction can be completed. For most instructions with only a
single modified or written operand, this implies special processing
only when a multibyte operand spans a protection boundary, making it
necessary to test accessibility of both parts of the operand.

In order that instructions which store intermediate results in the
general registers not compromise system integrity, they must insure
that any addresses stored or used are virtual addresses, subject to
protection checking, and that any state information stored or used
cannot result in a noninterruptable or nonterminating sequence.

Instruction operands that are peripheral device registers being accessed, may produce UNPREDICTABLE results because of instruction
restarting after faults. in order that software may dependably access
peripheral device registers, instructions used to access them must not
permit device interrupts during their execution.

Memory modifications produced as a byproduct of instruction execu-

tion, e.g., memory access statistics, are specifically excluded from the
constraint that memory not be altered until the instruction can be
completed.
271

Instructions that abort are constrained only to insure
memory protection (e.g., registers can be changed).

INTERRUPTS

Underlying the VAX-11 architectural concept of an interrupt
is the

notion that an interrupt request is a static condition,
not a transient
event, which can be sampled by a processor at appropria
te times.

Further, if the need for an interrupt disappears before a processo
r has
honored an interrupt request, the interrupt request can
be removed

(subject to

implementation-dependent timing

constraints) without

consequence.

It is necessary that any instruction changing the processo
r priority
(IPL), so that a pending interrupt is enabled, must allow
the interrupt to
occur before executing the next waiting instruction.

Similarly, instructions that generate requests at the software

levels must allow the interrupt to occur, if processor priority
before executing the apparently subsequent instruction.

interrupt
permits,

ERRORS

Processor errors, if not inconsistent with instruction completio

create high-priority interrupt requests. Otherwise, they must

instruction execution with a fault, trap, or abort.

n, must

terminate

Error notification interrupts may be delayed by the apparent
completion of the instruction in execution at the time of the error, but
if en-

abled, the interrupt must be requested before processor context
is

switched.

I/O0 STRUCTURE
The VAX-11 1/0 architecture is very similar to the PDP-11 structure,
the principal difference being the method by which processor
registers (such as the PSL) are accessed (reference the Architectu
re Hand-

book). Peripheral device control/status and data registers
appear at
locations in the physical address space, and can therefore be
manipulated by normal memory reference instructions. On the VAX-11/7
80

implementaton, this 1/0 space occupies the upper half of the
physical
address space and is 2?° bytes in length. Use of general instructio
ns
permits all the virtual address mapping and protection mechanis
ms
described in Chapter 6, Memory Management, to be used
when
referencing I/0 registers.

NOTE
Implementations that include a cache feature must
suppress caching for references in the 1/0 space.

272

System Architectural Implications

For any member of the VAX-11 series implementing the UNIBUS,

there will be one or more areas of the i/0 physical address space,

each 2'® bytes in length, which “maps through” to the UNIBUS addresses. The collection of these areas is referred to as the UNIBUS
space.

Constraints on I/O Registers

The following is a list of both hardware and programming constraints
on 1/0 registers. These items affect both hardware register design and
programming considerations.
1.

The physical address of an 1/0 register must be an integral multiple of the register size in bytes (which must be a power of two),
i.e., all registers must be aligned on natural boundaries.
References using a length attribute other than the length of the
register and/or unaligned reference may produce UNPREDICTABLE results. For example, a byte reference to a word-length
register will not necessarily respond by supplying or modifying
the byte addressed.

In all peripheral devices, error and status bits that may be asynchronously set by the device must be cleared by software writing a
“0”. This is to prevent clearing bits that may be asynchronously
set between reading and writing a register.

Only byte and word references of a read-modify-write (i.e., “.mb”
or “.mw”) type in UNIBUS 1/0 spaces are guaranteed to interlock
correctly. References in the 1/0 space other than in UNIBUS
spaces are UNDEFINED with respect to interiocking. This includes
the BBSSI| and BBCCI instructions.

String, quad, double, floating, and field references in the 170
space result in UNDEFINED behavior.

273

CHAPTER 14

RELIABILITY AVAILABILITY

MAINTAINABILITY PROGRAM
INTRODUCTION

A significant factor guiding the development of the VAX-11/780 computer system was an extensive reliability, availability, maintainability
program (RAMP). This program affected all aspects of the product,
from the design of the basic hardware and software architectures
through the final product, the VAX-11/780.

The first goal of the RAMP program was to utilize system design criteria that would effectively increase the mean time between failure rate
(MTBF) of the system. Product reliability therefore implies a design
that minimizes hardware, software, and system failures.
The second goal of the RAMP program was to incorporate a design
that provided fewer and less time consuming maintenance steps, performed with greater ease and better diagnostic tools. System maintainability can be measured in terms of mean time to repair (MTTR).

The objective of the RAMP program was to decrease the MTTR
through better diagnostic programs and procedures, and packaging
that facilitates repairs. The VAX-11/780 computer system was designed and built with integral hardware and software features that
continually monitor and verify system integrity.
HARDWARE RAMP FEATURES

A summary of the VAX-11/780 hardware RAMP features contributing

to the overall reliability of the system follows:

e Four Hierarchical Access Modes (kernel, executive, supervisor,
and user) protect system information and improve system reliability
and integrity.

e A Diagnostic Console, consisting of an LSI-11 microcomputer,
floppy disk, and console terminal, provides both local and remote
diagnosis of system errors and simplifies system bootstrap and software updates. Simple console commands replace lights and switches. The diagnostic console provides faster and easier maintenance
procedures and increases availability.
275

Re/:ab'l!".}y’I_\‘va'n’lab:l.(iu Admimbmiom

® Automatic Consistency and Error Checking detects abnormal instruction uses and illegal arithmetic conditions (overflow, underflow,
and divide by zero). Continual checking by the hardware (and uniform exception handling by the software) increases data reliability.

e Special Instructions, such as CALL and RETURN, provide a
standard program-calling interface for increased reliability.
¢ Integral Fault Detection and Maintenance Features, including:

ECC on memory detects all double-bit errors and corrects all singlebit errors to increase availability and aid in maintenance.

ECC on the RP0S, RP06, and RKO06 disks detects all errors up to 11
bits and corrects errors in a single error burst of 11 bits.

An SBI history silo maintains a history of the 16 most recent cycles
of bus activity and may be examined to aid in problem isolation.

Maintenance registers permit forced error conditions for diagnostic
purposes.

A high resolution interval timer permits testing of time-dependent
functions.
Extensive parity checking is performed on the SBI, MASSBUS and
UNIBUS adapters, memory cache, address transiation buffer,
microcode, and writable diagnostic control store.

A watchdog timer in the LSI-11 diagnostic console detects hung
machine conditions and allows crash/restart recovery actions.

Clock margining provides diagnostic variation of the clock rate and
aids in problem isolation.

Disabling of the memory management and the cache aids in isolating hardware problems.

e Fault Tolerance Features, including:
Detection and recording of bad blocks on disk surfaces increase the
reliability of the medium.
Write-verify checking hardware in peripherals is available to verify
all input and output disk and tape operations and to ensure data
reliablity.

Track offset retry hardware enables programmed software recovery
from disk transfer errors.

An in-depth description of each of the hardware RAMP features follows:

276

Reliability Availabiiity Maintainabiiity Program

Hierarchical Access Modes

The memory management hardware defines four hierarchical modes
of access privilege: kernel, executive, supervisor, and user. Read and
write access to memory is designated separately for each access
mode. The VAX operating system is designed so that only the most
critical components run in highly privileged access modes (kernel and
executive). This “layered” design increases protection, and consequently, data reliability and integrity, for the system and for users.
Diagnostic Console

The diagnostic console is an integral part of the VAX-11/780 processor. It includes an LSI-11 microcomputer, floppy disk, and console
terminal and is used for both remote and local diagnosis and system
maintenance activities.

The diagnostic console is an integral part of the system. If the LSI-11
console terminal is inoperative, another terminal may be substituted.
However, the microcomputer and the floppy diskette are crucial system components; if these units are inoperative, the reliability of the
system is seriously impaired. The LSI-11 performs a self-test on
power-up.

Consistency and Error Checking

During the execution of many instructions, consistency checks are
performed on the operands specified. If these checks fail, an exception is signalled and the current instruction sequence is suspended.
The exception handler is entered and the system software or the
user's program provides an appropriate response to the condition.
Such checks increase data reliability by preventing various error con-

ditions from propagating through a data base or a system. Some of

the checking performed includes:

e Arithmetic Traps Traps occur when overflow, underflow, and divide
by zero arithmetic conditions are detected. Hardware detection of
these error conditions allows checking to be used in high performance software, where software checking would be prohibitively
slow. Several of the arithmetic traps, integer overflow, index, and
decimal string, are new on the VAX-11/780. Overflow and underflow
traps may be enabled or disabled by setting bits in the Processor
Status Longword, allowing the arithmetic exception conditions to be
ignored, if appropriate.

e Limit Checking Traps Decimal string instructions all have length
limit checks (0-31 decimal digits) performed on output strings to
ensure that instructions do not overwrite adjacent data.

277

Reliability Availability Maintainability Program

® Reserved Operand Traps “Reserved-to-customer” and “reserved
-

to-DIGITAL” fields and opcodes ensure that customer
extensions to
the VAX-11/780 architecture (e.g., user-defined instructio
ns or data
structures) do not conflict with future DIGITAL expansions.

Special Instructions
The CALL and RETURN instructions have hardware-impleme

ister save/restore and consistency checking. The

nted reg-

use of these instruc-

tions provides a standard interface which is identical on

calls and system calls.

user routine

The CRC (Calculate Cyclic Redundancy Check) instruction
provides
powerful block checking error code calculations, such
as are

in communications applications.

needed

Integral Fault Detection and Maintenance Features
These features aid in the diagnosis of hardware errors and
in the
efficient maintenance of the system. Specific features include
the
following:
® Memory error correcting code (ECC) will correct all
single-bit

memory errors, and will detect double-bit memory errors. ECC
provides
protection for non-repeatable errors by automatically correcting

data. Detections and corrections are noted in the error log
as a
preventive maintenance aid.

® Disk error correcting code detects all errors up to 11 bits
and cor-

rects errors in a single error burst of 11 bits. Detections
and correc-

tions are noted in the error log as a preventive maintenance
® A System Identifications (SID) hardware register maintains

aid.
informa-

tion pertinent to the system processor: type and serial number. This

information may be examined (during the software logging process,
for example) to determine the engineering status of the processor.

® A sixteen-level silo monitors SBI activity and contains a
history of
the 16 most recent cycles of bus activity. If an error
or
predetermined special condition occurs, the silo is latched
(i.e., the
error or condition can cause the silo contents to
“freeze”: see the

SBI Silo Comparator, in the following paragraph) and the contents
of the silo can be examined to help determine the cause
of the
problem.

e Several maintenance registers contain bus-specific maintenan

ce information and can be examined at the time of an error to
help
determine the cause. These registers are:

—

SBI Fault/Status Register, which detects faults and conditions

the SBI

278

Reliability Availability Maintainability Program

—

SBI Silo Comparator, used to lock the SBI silo on predetermined
conditions (e.g., specific number of cycles after an event)

—

SBI Error Register, which indicates the type of error detected by
'
SBI hardware
SBI Timeout Address, which contains the physical address that
caused a timeout condition on the SBI
Cache Parity Register, which indicates where parity errors were

—
—

detected

—

SBI Maintenance Register, used to force error conditions in the
cache or SBI for diagnostic and simulation purposes (e.g., forced
bus timeout or cache miss)

—

Translation Buffer Parity Register, which indicates where parity
errors were detected

e A high resolution interval timer (1 usec) is used by diagnostics to test

time-dependent functions without requiring machine-specific timing
loops in programs.

e Parity and protocol checks are performed on SBI data and address.
Parity checks are performed on: MASSBUS data, control and address translation; UNIBUS address translation; memory cache data
and address; address translation buffer transaction; microcode; writable user diagnostic control store (1 parity bit for each 32 bits); and
CPU internal buses.

e A watchdog timer in the LSI-11 detects hung machine conditions
(such as a hang in the microcode or a halt condition). Indicator lights
on the front panel show whether the VAX-11/780 CPU is running or
in a halt state. If the auto/restart switch on the processor console is
set, automatic crash/restart recovery actions are initiated after either a hang condition or a halt.
e Clock margining is provided and causes the SBI clock rate to be

varied by console commands to aid the field service engineer in
diagnosing intermittent hardware problems.

e Memory management and the cache may be disabled by
diagnostics to aid in isolating hardware problems.
Fault Tolerance Features

These features provide the means to continue processing without loss
of information, even though hardware errors may be occurring. Specific features include the following:

e The VAX-11/780 performs dynamic bad block handling. Bad blocks
may occur when a disk surface becomes worn, or as a resuit of a
failure in the hardware that performed the data transfer. When the
VAX-11/780 hardware detects a bad block during a read, the VAX
279

Reliability Availability Maintainability Program

operating system marks the header of the file in which the error
occurred. When the file is eventually de-aliocated, the system

checks the file header to see if any bad blocks exist in the file. If so,
they are designated “permanently in use” and are not allocated for
use by other files.
Verify checking hardware for mass storage peripherals is supported

by the VAX device drivers. The hardware compares each block for
errors immediately after the block is read or written. Checking may

be performed on all reads or writes to a file or volume, or specified
for a single read or write. This capability increases readability (but
also increases the time to complete the read or write operation).

Track offset retry hardware is used (by the operating system) to
attempt recovery from disk transfer errors. If an error occurs during

a read operation, the error is signalled by the disk hardware and the
operation retried. If the retry fails, the disk head may be repositioned slightly (offset) on either side of the normal track location in
an attempt to read the data correctly.

280

APPENDIX A

COMMONLY USED MNEMONICS
Ancillary Control Process
American National Standard

American Standard Code for Information Interchange
Asynchronous System Trap
Asynchronous System Trap Level
Channel Control Block

Compatibility Mode bit in the hardware PSL
Channel Request Block
Cyclic Redundancy Check
Data Access Protocol
Device Data Block

DIGITAL Data Communications Message Protocol

Driver Data Table

Decimal Overflow trap enable bit in the PSW

Exit Control Block
Error Correction Code

Executive Mode Stack Pointer
Exception Service Routine
Files-11 Ancillary Control Process
File Access Block
Fixed Control Area
File Control Block
File Control Services
Function Decision Table
Frame Pointer
First Part (of an instruction) Done

Floating Underflow trap enable bit in the PSW

Global Section Descriptor
Global Symbol Table
Interrupt Dispatch Block
Interrupt Priority Level
I/0 Request Packet
Image Section
Image Section Descriptor
Interrupt Stack Pointer
Interrupt Stack bit in PSL
Interrupt Service Routine

integer Overflow trap enable bit in the PSW
Kernel Mode Stack Pointer
281

Appendix A

fat
&

MASSBUS Adapter
Must Be Zero

Monitor Console Routine
Master File Directory
Move From Process Register instruction
Memory Mapping Enable
Move To Process Register instruction
Mutual Exclusion semaphore

Network Services Protocol
Operator Communication Manager

Program region Base Register
Program region Length Register

Program region Page Table
Control region Base Register
Control region Limit Register

Control region Page Table
Program Counter
Process Control Block
Process Control Block Base register
Page Frame Number
Process ldentification Number
Performance Monitor Enable bit in PCB

Program Section

Processor Status Longword
Processor Status Word
Page Table Entry

Queue Input/Output Request system service

Record Access Block
Record’s File Address
Record Management Services
Read, Write, Execute, Delete

Synchronous Backpiane Interconnect
System Base Register
System Control Block
System Control Block Base register

System Length Register
Stack Pointer
System Page Table
Supervisor Mode Stack Pointer

System Virtual Address
Trace trap Pending bit in PSL
UNIBUS Adapter

Unit Control Block
User Environment Test Package
User File Directory
User Identification Code

282

Appendix A

User mode Stack Pointer
Volume Control Block

Virtual Page Number
Window Control Block
Writeable Control Store

Writeable Diagnostic Control Store

283

284

APPENDIX B

INSTRUCTION INDEX

B.1. MNEMONIC LISTING
MNEMONIC
ACBB
ACBD
ACBF
ACBL
ACBW
ADAWI
ADDB2
ADDB3
ADDD2
ADDD3
ADDF2
ADDF3

ADDL2

ADDL3
ADDP4
ADDP6

ADDW2
ADDW3
ADWC

AOBLEQ
AOBLSS
ASHL
ASHP
ASHQ
BBC
BBCC
BBCCI
BBCS
BBS
BBSC
BBSS
BBSSI

BCC
BCS
BEQL
BEQLU

BGEQ
BGEQU

INSTRUCTION

Add compare and branch byte
Add compare and branch double
Add compare and branch floating
Add compare and branch long

Add compare and branch word
Add aligned word interlocked
Add byte 2 operand
Add byte 3 operand

Add double 2 operand
Add double 3 operand
Add floating 2 operand
Add floating 3 operand
Add long 2 operand
Add long 3 operand
Add packed 4 operand
Add packed 6 operand
Add word 2 operand
Add word 3 operand
Add with carry

Add one and branch on less or equal

Add one and branch on less
Arithmetic shift long

Arithmetic shift and round packed
Arithmetic shift quad

Branch on bit clear
Branch on bit clear and clear

Branch on bit clear and clear interlocked

Branch on bit clear and set
Branch on bit set

Branch on bit set and clear
Branch on bit set and set

Branch on bit set and set interlocked
Branch on carry clear
Branch on carry set
Branch on equai

Branch on equal unsigned
Branch on greater or equal

Branch on greater or equal unsigned
285

Appendix B

MNEMONIC

INSTRUCTION

BGTR

Branch on greater

BGTRU

BICB2
BICB3
BICL2

BICL3
BICPSW
BICW2
BICW3

BISB2

BISB3
BISL2
BISL3
BISPSW

BISW2

BISW3

Branch on greater unsigned
Bit clear byte 2 operand
Bit clear byte 3 operand

Bit clear long 2 operand

Bit clear long 3 operand

Bit clear program status word

Bit clear word 2 operand
Bit clear word 3 operand
Bit set byte 2 operand

Bit set byte 3 operand

Bit set long 2 operand

Bit set long 3 operand
Bit set program status word

Bit set word 2 operand

BITB

Bit set word 3 operand
Bit test byte

BITL

Bit test long

BITW

Bit test word

BLBC
BLBS
BLEQ

BLEQU

BLSS
BLSSU

Branch on low bit clear
Branch on low bit set

Branch on less or equal
Branch on less or equal unsigned

Branch on less
Branch on less unsigned

BNEQ

Branch on not equal

BNEQU

Branch on not equal unsigned

BPT

BRB
BRW

BSBB
BSBW

BvC
BVS

CALLG

CALLS
CASEB

Break point fault
Branch with byte displacement
Branch with word displacement
Branch to subroutine with byte

displacement
Branch to subroutine with word

displacement
Branch on overflow clear
Branch on overflow set

Call with general argument list
Call with stack

Case byte
Case long

CASEL
CASEW
CHME
CHMK
CHMS

Change mode to supervisor

CHMU

Change modto
e user

CLRB
CLRD

Case word
Change mode to executive
Change mode to kernel

Clear byte

Clear double

286

Appendix B
OPCODE

MNEMONIC

INSTRUCTION

CLRF
CLRL
CLRQ
CLRW
CMPB

Clear float
Clear long
Clear quad
Clear word
Compare byte

CMPC3
CMPC5

Compare character 3 operand
Compare character 5 operand

CMPP4

Compare packed 3 operand
Compare packed 4 operand

CMPV

Compare field

CMPW

Compare word

CMPD
CMPF
CMPL
CMPP3

CMPZV

CRC
CvTBD
CVTBF

CVTBL
CvTBwW

CvTDB
CVTDF
CVTDL
CVTDW
CVTEB
CVTFD
CVTFL
CVTFW

CVTLB
CVTLD
CVTLF
CVTLP
CVTLW
CVTPL
CVTTP
CVTPT

Compare double
Compare floating
Compare long

Compare zero-extended field
Calculate cyclic redundancy check
Convert byte to double
Convert byte to float
Convert byte to long
Convert byte to word
Convert double to byte

Convert double to float
Convert double to long

Convert double to word
Convert fioat to byte
Convert float to double
Convert float to long
Convert float to word
Convert long to byte

Convert long to double
Convert long to float
Convert long to packed
Convert long to word
Convert packed to long

Convert trailing numeric to packed
Convert packed to trailing numeric

CVTPS

Convert packed to leading separate numeric 08

CVTRDL
CVTRFL

Convert rounded double to long
Convert rounded float to long

CVTSP

Convert leading separate numeric to packed 09

CVTWL

Convert word to byte
Convert word to double
Convert word to float
Convert word to long

DECB
DECL

Decrement byte
Decrement long

CVTwB
CviwD
CVTWF

DECW

Decrement word

287

MNEMONIC

INSTRUCTION

DIVB2
DIVB3

Divide byte 2 operand
Divide byte 3 operand

DIvD2
DIVD3

DIVF2
DIVF3

DivL2

DIVL3
DIVP
Divw2

DIVW3

EDITPC
EDIV

EMODD
EMODF
EMUL

EXTV

Divide double 2 operand

Divide double 3 operand
Divide floating 2 operand
Divide floating 3 operand
Divide long 2 operand

Divide long 3 operand
Divide packed

Divide word 2 operand
Divide word 3 operand

Edit packed to character
Extended divide
Extended modulus double

Extended modulus floating
Extended multiply
Extract field

EXTZV

Extract zero-extended field

FFC
FFS

Find first clear bit
Find first set bit

HALT

Halt

INCB

Increment byte
Increment long

INCL

INCW

INDEX
INSQUE

Increment word
Compute index

Insert into queue

INSV

insert field

JMP

Jump

JSB

Jump to subroutine

LDPCTX

Load process context

LOCC
MATCHC
MCOMB
MCOML
MCOMW

MFPR
MNEGB
MNEGD
MNEGF

MNEGL
MNEGW
MOVAB
MOVAD

MOVAF

MOVAL

Locate character

Match characters

Move complemented byte
Move complemented long

Move complemented word

Move from privileged register
Move negated byte

Move negated double
Move negated floating

Move negated long

Move negated word
Move address of byte

Move address of double
Move address of float

Move address of long

288

Appendix B

MNEMONIC

INSTRUCTION

MOVAQ
MOVAW

Move address of quad
Move address of word

MOVB
MOVC3
MOVC5
MOVD
MOVF
MOVL
MOVP
MOVPSL

MOVQ
MOVTC
MOVTUC
MOVW

MOVZBL
MOVZBW
MOVZWL

Move byte

Move character 3 operand
Move character 5 operand
Move double
Move float
Move long
Move packed

Move processor status longword
Move quad

Move translated characters

Move translated until character
Move word

Move zero-extended byte to long
Move zero-extended byte to word
Move zero-extended word to long

MTPR

Move to privileged register

MULB2
MULB3

Multiply byte 2 operand
Multiply byte 3 operand
Multiply double 2 operand
Multiply double 3 operand

MULD2
MULD3

MULF2
MULF3
MULL2
MULL3
MULP

. Multiply floating 2 operand
Multiply floating 3 operand
Multiply long 2 operand
Multiply long 3 operand
Multiply packed

MULW3

Multiply word 2 operand
Multiply word 3 operand

NOP

No operation

POLYD

Evaluate polynomial double
Evaluate polynomial floating

MULW2

POLYF
POPR

PROBER
PROBEW

PUSHAB
PUSHAD
PUSHAF
PUSHAL

PUSHAQ
PUSHAW
PUSHL

PUSHR
REI

REMQUE

Pop registers

Frobe read access
Probe write access

Push address of byte
Push address of double
Push address of float

Push address of long
Push address of quad
Push address of word
Push long

Push registers

Return from exception or interrupt

Remove from queue

289

Appendix B

MNEMONIC

INSTRUCTION

RET

Return from called procedure

ROTL

RSB

SBWC
SCANC
SKPC

SOBGEQ
SOBGTR

SPANC
SuUBB2

SUBB3
SuBD2

OPCODE

Rotate long
Return from subroutine

Subtract with carry
Scan for character
Skip character

Subtract one and branch on greater or

Subtract one and branch on greater

Span characters
Subtract byte 2 operand
Subtract byte 3 operand

Subtract double 2 operand

SUBD3
SUBF2

Subtract double 3 operand
Subtract floating 2 operand

SUBF3

Subtract floating 3 operand
Subtract long 2 operand

SUBL2
SUBL3

SUBP4
SUBP6
SuBw2
SUBWS3
SVPCTX

TSTB

TSTD
TSTF
TSTL

TSTW
XFC

XORB2
XORB3
XORL2
XORL3
XORW2
XORW3

Subtract long 3 operand
Subtract packed 4 operand

Subtract packed 6 operand
Subtract word 2 operand
Subtract word 3 operand

Save process context
Test byte

Test double
Test float
Test long
Test word
Extended function call
Exclusive OR byte 2 operand

Exclusive OR byte 3 operand
Exclusive OR long 2 operand

Exclusive OR long 3 operand
Exclusive OR word 2 operand

Exclusive OR word 3 operand
*Reserved to DEC*
*“Reserved to DEC*
“Reserved to DEC*
*Reserved to DEC*

*Reserved to DEC*
“Reserved to DEC*

“Reserved to DEC*

*Reserved to DEC*
*Reserved to DEC*

ESCD
ESCE

ESCF

*“Reserved to DEC*

*Reserved to DEC*
*Reserved to DEC*

290

equal

Appendix B

B.2. OPCODE LISTING
OPCODE

MNEMONIC

INSTRUCTION

HALT
NOP

Halt

No operation

Return from exception or interrupt

REI
BPT
RET
RSB
LDPCTX
SVPCTX

Break point fault

Return from called procedure
Return from subroutine
Load process context
Save process context

CVTPS

Convert packed to leading separate

CVTSP

Convert leading separate numeric to

numeric

packed

Compute index

INDEX
CRC
PROBER
PROBEW
INSQUE

Calculate cyclic redundancy check
Probe read access

REMQUE
BSBB
BRB

BNEQ,

Branch with byte displacement

BNEQU

BGTR
BLEQ
JSB
JMP

BGEQ
BLSS
BGTRU
BLEQU
BVC
BVS

BGEQU, BCC
BLSSU, BCS

suRP4
(A

SUBP6
CVTPT
MULP

Branch to subroutine with byte dis-

placement

BEQL, BEQLU

ADDP4
ADDP6

Probe write access
Insert intc queue
Remove from queue

Branch on not equal unsigned, Branch

on not equal

Branch on equal, Branch on equal un-

signed

Branch on greater

Branch on less or equal
Jump to subroutine
Jump

Branch on greater or equal
Branch on less

Branch on greater unsigned

Branch on less or equal unsigned
Branch on overflow clear
Branch on overflow set

Branch on greater or equal unsigned,

Branch on carry clear

Branch on less unsigned, Branch on

carry set

Add packed 4 operand
Add packed 6 operand

Subtract packed 4 operand
Subtract packed 6 operand

Convert packed to trailing numeric
Multiply packed
291

Appendix B

OPCODE

MNEMONIC

CVTTP

DivpP

Divide packed

MOVC3

Move character 3 operand
Compare character 3 operand

CMPC3
SCANC
SPANC
MOVC5

CMPC5
MOVTC
MOVTUC
BSBW

BRW
CvTwL

CVTwB
MOVP

CMPP3
CVTPL

CMPP4
EDITPC
MATCHC

LOCC

SKPC
MOVZwL

ACBW

MOVAW
PUSHAW
ADDF2
ADDF3

SUBF2
SUBF3

MULF2
MULF3
DIVF2

DIVF3

CVTFB

CVTFw

CVTFL
CVTRFL
CVTBF
CVTWF

CVTLF
ACBF

MOVF
CMPF
MNEGF

INSTRUCTION
Convert trailing numeric to packed

Scan for character
Span characters
Move character 5 operand

Compare character 5 operand

Move transiated characters
Move translated until character

Branch to subroutine with word dis-

placement

Branch with word displacement
Convert word to long

Convert word to byte

Move packed
Compare packed 3 operand
Convert packed to long
Compare packed 4 operand

Edit packed to character
Match characters
Locate character
Skip character
Move zero-extended word to long
Add compare and branch word

Move address of word
Push address of word

Add floating 2 operand
Add floating 3 operand
Subtract floating 2 operand

Subtract floating 3 operand
Multiply floating 2 operand

Multiply floating 3 operand
Divide floating 2 operand
Divide floating 3 operand

Convert float to byte

Convert float to word
Convert float to long

Convert rounded float to long

Convert byte to float

Convert word to float
Convert long to float
Add compare and branch floati
ng
Move float

Compare floating
Move negated floating

292

Appendix B

MNEMONIC

INSTRUCTION

TSTF
EMODF
POLYF
CVTFD

Test float

Extended modulus floating
Evaluate polynomial floating
Convert float to double
RESERVED to DEC

Add aligned word interlocked

ADAWI

RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC
RESERVED to DEC

Add double 2 operand
Add double 3 operand

ADDD2
ADDD3
sSUuBD2
sSuBD3
MULD2
MULD3
DIVD2
DIVD3

Subtract double 2 operand
Subtract double 3 operand
Multiply double 2 operand
Muitiply double 3 operand
Divide double 2 operand
Divide double 3 operand

CVvTDB

Convert double to byte

CVTDW
CVTDL
CVTRDL

Convert double to long

Convert double to word

Convert rounded double to long

Convert byte to double
Convert word to double
Convert long to double

CVTBD
CVTWD
CVTLD
ACBD

Add compare and branch double
Move double
Compare double

MOVD

CMPD
MNEGD
TSTD

Move negated double

Test double

Extended modulus double
Evaluate polynomial double

EMODD
POLYD

Convert double to float
RESERVED to DEC

CVTDF

Arithmetic shift long
Arithmetic shift quad
Extended multiply
Extended divide

ASHL

ASHQ
EMUL

EDIV

CLRQ, CLRD
MOVQ

MOVAQ,

MOVAD

PUSHAQ, PUSHAD

Clear quad, Clear double
Move quad

Move address of quad, Move address of

double

Push address of quad, Push address of

double

293

Appendix B

MNEMONIC
ADDB2
ADDB3

suBB2
SuBB3
MULB2

MULBS3
DlvB2

DIVB3

BISB2
BISB3
BICB2

BICB3
XORB2
XORB3

MNEGB

CASEB
MOvB
CMPB
MCOMB

BITB

CLRB
TSTB

INCB

Add byte 2 operand
Add byte 3 operand

Subtract byte 2 operand
Subtract byte 3 operand
Multiply byte 2 operand

Multiply byte 3 operand

Divide byte 2 operand
Divide byte 3 operand

Bit set byte 2 operand
Bit set byte 3 operand
Bit clear byte 2 operand

Bit clear byte 3 operand
Exclusive OR byte 2 operand
Exclusive OR byte 3 operand
Move negated byte

Case byte

Move byte
Compare byte
Move complemented byte
Bit test byte
Clear byte
Test byte

DECB

Increment byte
Decrement byte

CVTBL

Convert byte to long

CvTBW
MOVZBL
MOvZBW

ROTL
ACBB
MOVAB

INSTRUCTION

Convert byte to word
Move zero-extended byte to long
Move zero-extended byte to word

Rotate long

Add compare and branch byte
Move address of byte

PUSHAB

Push address of byte

ADDW?2
ADDWS3

Add word 2 operand
Add word 3 operand

SUBW2

sSuUBwW3
MULW2
MULW3

DIvw2
DIVW3
BISW2
BISW3
BICW2
BICW3
XORW2

XORWS3

Subtract word 2 operand

Subtract word 3 operand
Multiply word 2 operand
Multiply word 3 operand

Divide word 2 operand
Divide word 3 operand
Bit set word 2 operand
Bit set word 3 operand
Bit clear word 2 operand
Bit clear word 3 operand
Exclusive OR word 2 operand

Exclusive OR word 3 operand
294

Appendix B

MNEMONIC

INSTRUCTION

MNEGW
CASEW

Move negated word
Case word

MOVW
CMPW

Move word
Compare word

BITW
CLRW
TSTW
INCW
DECW

Bit test word
Clear word
Test word
Increment word
Decrement word

BISPSW
BICPSW

Bit set processor status word
Bit clear processor status word

MCOMW

Move complemented word

POPR
PUSHR

Pop registers
Push register

CHMU

Change mode to user

CHMK
CHME
CHMS

Change mode to kernel
Change mode to executive
Change mode to supervisor

ADDL2
ADDL3
SUBL2
SUBL3

Add long 2 operand
Add long 3 operand
Subtract long 2 operand
Subtract long 3 operand

BISL2
BISL3
BICL2
BICL3
XORL2
XORL3

Bit set long 2 operand
Bit set long 3 operand
Bit clear long 2 operand
Bit clear long 3 operand
Exclusive OR long 2 operand
Exclusive OR long 3 operand

MULL2
MULL3
DIVL2
DIVL3

MNEGL

Multiply long 2 operand
Multiply long 3 operand
Divide long 2 operand
Divide long 3 operand

Move negated long

CASEL

Case long

MOVL
CMPL

Move long
Compare long

MCOML
BITL

Move complemented long
Bit test long

CLRL, CLRF

Clear long, Clear float

DECL

Decrement long

TSTL
INCL

ADWC

SBWC
MTPR

MFPR

Test long
Increment long
Add with carry

Subtract with carry
Move to processor register

Move from processor register
295

Appendix B
OPCODE

MNEMONIC

MOVPSL

PUSHL

MOVAL, MOVAF

INSTRUCTION
Move processor status longword

Push long
Move address of long, Move address of

float

PUSHAL, PUSHAF

Push address of long, Push address of

float

BBS

Branch on bit set
Branch on bit clear

BBC

BBSS

Branch on bit set and set

BBCS

Branch on bit clear and set
Branch on bit set and clear
Branch on bit clear and clear

BBSC
BBCC
BBSSI

Branch on bit set and set interlocked
Branch on bit clear and clear interlocked

BBCCI
BLBS

Branch on low bit set
Branch on low bit clear

BLBC
FFS

Find first set bit
Find first clear bit
Compare field

FFC

CMPV
CMPZV

Compare zero-extended field
Extract field

EXTV
EXTZV

Extract zero-extended field

INSV

Insert field

ACBL

Add compare and branch long
Add one and branch on less

AOBLSS
AOBLEQ

Add one and branch on less or equal

SOBGEQ

Subtract one and branch on greater or

equal

SOBGTR

Subtract one and branch on greater
Convert fong to byte

CvTLB

CvTLw

Convert long to word

ASHP

Arithmetic shift and round packed
Convert long to packed

CVTLP

CALLG

Call with general argument list
Call with stack
Extended function call

CALLS

XFC

ESCD to DEC
ESCE to DEC
ESCF to DEC

296

APPENDIX C

I/0 SPACE RESTRICTIONS
A subset of native mode instructions is not used to reference 170

space. The reasons for this are:

1.
2.

String instructions are restartable via PSL<FPD>.
The PC, SP, or PCBB cannot point to I/0 space.

1/0 space does not support operand types of quad, floating, double, field, or queue; nor can the position, size, length, or base of

them be from I/O space.

The instruction may be interruptable because it is potentially a

Only instructions with a maximum of one modify or write destina-

slow instruction in some implementations.

tion can be used. The destination must be the last operand.
In any case, the programmer is responsible for ensuring that any

memory reference to I/0 space is in an instruction which cannot take
an exception after the first I/0 space reference. This includes deferred
references to 1/0 space.

Instructions for which any explicit operands can be in I/0 space are:

MOV{B,W,L], PUSHL, CLR{BW,L}, MNEG{B,W,L}, MCOM{BW,L},
MOVZ{BW,BL,WL}, CVT{BW,BL,WB,WL,LB,LW}, CMP{B,W,L},
TST{B.W,L}, ADD{B,W,L}2, ADD{B,W,L}3, ADAWI, INC{B,W,L}, ADWC,
SUBIB.W,L}2, SUB{B,W,L}3, DEC{B,W,L}, SBWC, BIT{B,W,L},
BIS{B,W,L}2, BIS{B,W.L|3, BIC{B,W,Li2, BIC{B,W,L}3, XOR{B,W,Li2,
XOR{B.W,L13, MOVA{BW,L}, MOVAQ, PUSHA{BW,L|, PUSHAQ,
U},
CASE{B,W,L}, MOVPSL, BISPSW, BICPSW, CHMI{K,E,S
PROBE|R,W}, MTPR, MFPR

Instructions for which all operands except the branch displacement

can bein /0 space are:

BLB {S,C}

Instructions for which some operand can be in I/0 space are:

XFC

REMQUE

(depending on implementation)
addr (destination)

In spite of the above rules, it is possible for a specific hardware implementation to execute macro code from the 1/0 space and/or to
allow the stack or PCB to be in I/0 space. This might, for exampie, oe
used as part of the bootstrap process. If this is done, then it is valid for
software to transfer to this code.

297

298

APPENDIX D

INTERNAL DATA (ID) BUS REGISTERS

Instruction Buffer Register
ID Address 00
Processor Address —

24 23

16 15

8 7

—/\

r1 1 l11[ 1 L 1 I 1 1 1 Ii1 I

BYTE 3 ————J
DATA
DATA BYTE 2

‘

0
J

DATA BYTE 1
DATA BYTE O

Time of Day Register
ID Address 01

Processor Address 1B

24 23

16 15

VAN

l..,.l...l..ll.

TIME BYTE 3 ——————’

TIME BYTE 2
TIME BYTE 1
TIME BYTE O

8 7

I..‘.

.lJ
J

Reserved Register

[___o

ID Address 02
Processor Address —

Appendix D

System Identification Register
ID Address 03

Processor Address 3E

TYPE

ECO

L.
—
LEVEL

24 23

|
—

12 N

]
A

)

PLANT

SERIAL NUMBER

Console Receive Control/Status Register
ID Address 04

Processor Address 20

EM°E°I°l°I°f°leol°l°l°I°I°!:l:l°l°l°l°I°l°lZl;i T[T
]

INTERRUPT ENABLE

Console Receive Data Buffer Register
ID Address 05
Processor Address 21

L; P SR
DATA BYTE 3 “—1

DATA BYTE 2
DATA BYTE 1
DATA BYTE O

24 23

l PO SRS G T S
N

16 1S

P l .

N PN PR j

As defined in the software, bits <7:0> define the data field, bits

<11:8> define the ID field and bit <15> is the error bit. However,
the
hardware is not restricted to this convention.

300

Appendix D

Console Transmit Control/Status Register
ID Address 06

Processor Address 22

ool o oo o] el | Tl ol
¥

READY

INTERRUPT ENABLE

Console Transmit Data Buffer Register
ID Address 07

Processor Address 23
2N

24 2

16 15

8 7

J\.

[ 1 1 1 | 1 L 1 [ 1 1 1 l L 1 L [i 1 1 JY 1 1 1 1 1 I i| ]
N

—

—
DATA BYTE3 4

DATA BYTE 2

DATA BYTE 1
DATA BYTE 0

As defined in the software, bits <7:0> define the data field, and bits
<11:8> define the ID field. However, the hardware is not restricted to
this convention.

DQ Register

ID Address 08
Processor Address —

Next Interval Register

ID Address 09

Processor Address 19

301

Interval Clock Control/Status Register
ID Address OA

Processor Address 18

[o'JoMolo:olofo‘firo{o:olololol?lflolorolofoloril’iTi‘lo[oxofi

INTERRUPT REQUESY
R

INTERRUPT ENABLE
SINGLE CLOCK
TRANSFER
RUN

Interval Counter Register
ID Address 0B
Processor Address 1A
3N

24 23

COUNT IN MICROSECONDS

ID Address 0C

Processor Address 13 (Accesses AST level bits <2:0>)
Processor Address 3D (Accesses Performance Monitor Enable

bit <3>)
SUMMARY

LTP
l
R T

CONTROL STORE PARITY ERROR

PR
T

NESTED ERROR

EXPONENT ARITHMETIC LOGIC UNIT N BIT

EXPONENT ARITHMETIC LOGIC UNIT Z BIT

ARITHMETIC LOGIC UNIT N BIT
ARITHMETIC LOGIC UNIT Z BIT
ARITHMETIC LOGIC UNIT CARRY BIT 31
ARITHMETIC TRAP CODE
PERFORMANCE MONITOR ENABLE
AST LEVEL

Vector Register
ID Address 0D

Processor Address —
26 25 24 23

2) 20

EEHHII AN

16 15

CEERR00N

;\,——/

NUMBER OF ONES
VECTOR

302

;_w___/

Appendix D

Software Interrupt Register
ID Address OE

Processor Address 15
20

24 23

8 7

16 15

%87 654321 A Lil
‘0 0 OlOIO‘OIOlOIO}O\Ol l L 1 L \F A EDCBAG
L L L I 1 1 L
1 A
;

o —C
4

ACTIVE
INTERRUPT PRIORITY LEVEL
REGISTER
SOFTWARE INTERRUPT

Processor Status Longword Register
ID Address OF

Processor Address 12

31 302928 27 262524232221 20

l Mol | |

COMPATABILITY MODE
TRACE PENDING
FIRST PART DONE
INTERRUPT STACK

e
N

16 15

l A 1 1
e

8 7

olololololololo|ov‘w.xvT Nz Vj
1

‘

CURRENT MODE

PREVIOUS MODE
INTERRUPT PRIORITY LEVEL

DECIMAL OVERFLOW TRAP ENABLE
FLOATING UNDERFLOW TRAP ENABLE
INTERIOR OVERFLOW TRAP ENABLE

TRACE

CONDITION CODES

Translation Buffer Data Register
ID Address 10
Processor Address —

H .|

26252423

21 20

16 15

8 7

65432Sl‘fl
21109 SO 87 RIS
7161514131
l |0|0]0J0‘0[201918
R U S S W
| S

PROTECTION CODE

MODIFY
PAGE FRAME NUMBER

Reserved Register
ID Address _1 1
Processor Address —

423

8 7

Appendix D

Translation Buffer Control Register 0
ID Address 12
Processor Address —

o
FFT T T] T
REPLACE

)

BOTH

REPLACE GROUP 1
REPLACE GROUP O
FORCE MISS GROUP 1
FORCE MISS GROUP 0
FUNCTION SELECT
ADDRESS SELECT
MEMORY CONTROL 3———
MEMORY CONTROL 2

MEMORY CONTROL !
MEMORY CONTROL O

INSTRUCTION BUFFER WRITE CHECK
AUTO RELOAD
TRANSLATION BUFFER HIT GROUP |
TRANSLATION BUFFER HIT GROUP
O
FORCE TRANSLATION BUFFER PARITY ERROR

MEMORY MANAGEMENT ENABLE

Translation Buffer Control Register 1
ID Address 13

Processor Address —
TRANSLATION BUFFER
PARITY ERROR BITS

INSTRUCTION

PHYSICAL
ADDRESS
r—

BEGEEcEEacNN HIHIHHI o ]

GROUP 1 *DM BYTE 2 PARITY ERROR
GROUP| DM BYTE | PARITY ERROR
GROUP' DM BYTE O PARITY ERROR
GROUP O DM BYTE 2 PARITY ERROR
GROUP 0 DM BYTE 1 PARITY ERROR
GROUP 0 DM BYTE O PARITY ERROR
GROUP | *AM BYTE 2 PARITY ERROR

GROUP 1 AM BYTE | PARITY ERROR
GROUP 1 AMm BYTE O PARITY ERROR
GROUP 0 AM BYTE 2 PARITY ERROR
GROUP 0 AM BYTE | PARITY ERROR
GROUP 0 aM BYTE O PARITY ERROR
CPU TRANSLATION BUFFER PARITY ERROR

LAST TRANSLATION BUFFER WRITE PULSE
BAD INSTRUCTION PHYSICAL ADDRESS

INSTRUCTION BUFFER TRANSLATION BUFFER MISS
PARITY ERROR
CHECK

AUTO RELOAD

Accelerator Control Register 0
ID Address 14

Processor Address —
3

2423

Appendix D

Accelerator Control Register 1
ID Address 15
Processor Address —
8 7

16 15

423

k)|

‘1..|1|||||1|..|l.|A11|1|11|l-Ln‘

Accelerator Maintenance Register
ID Address 16
Processor Address —

16 15

24 23

00[
00000
U ST
PP

8 7

OOO
llOOIO
|
TR Y

J—
—

TRAP ADDRESS

WRITE TRAP ADDRESS
LOAD MICROBREAK
MICROMATCH

MICROBREAK MATCH

Accelerator Control/Status Register
ID Address 17

Processor Address 28

([T lolot?lflolololo!ololtl;lololololo|o|3|3lo>ololo_gg
31

ERROR ————T

RESERVED OPERAND
ACCELERATOR ENABLE
ACCELERATOR TYPE

SBI Silo Register
ID Address 18

Processor Address 31
31

8 7

25 24 23

I TR

{

AFTER FAULT —-U \—;IV_JT

SBI INTERLOCK
0
TAG

MASK BIT 3 OR DATA BIT 31

MASK BIT 2 OR DATA BIT30

| OR DATA BIT 29
MASK BIT
BIT O OR DATA BIT 28
MASK

CONFIRMATION 1
CONFIRMATION 0

SBI TRANSFER REQUEST NO:

305

—t

Appendix D

SBI Silo Register
ID Address 19
Processor Address 34

FTT

————

CENTRAL PROCESSOR TIME OUT
CENTRAL PROCESSOR TIME OUT STATUS 1
CENTRAL PROCESSOR TIME OUT STATUS 0
CENTRAL PROCESSOR ERROR CONFIRM ACTION
INSTRUCTION BUFFER READ DATA SUBSTITUTE

—— e

i l

CORRECTED READ DATA
READ DATA SUBSTITUE

L] T TITT 7T

READ DATA SUBSTITUE INTERRUPT ENABLE

INSTRUCTION BUFFER TIME OUT
INSTRUCTION BUFFER TIME OUT STATUS 1|
INSTRUCTION BUFFER TIME OUT STATUS
0
INSTRUCTION BUFFER ERROR CONFIRMA
TION
DOUBLE BUS ERROR

;
SR

SBI NOT BUSY

SBI Time Out Address Register
ID Address 1A
Processor Address 35

28 27

[¢]

MODEI
MO
DEO

PROTECTION CHECK
PHYSICAL ADDRESS <29:02>

SBI Fault Signal Register
ID Address 1B

Processor Address 30
31

2423

165

l| O000 o{0

PARITY FAULT

UNEXPECTED READ

Py
T i

MULTIPLE TRANSMITTER FAULT

DATA

TRANSMITTING DURING FAULT
FAULT LATCH
FAULT INTERRUPT ENABLE
FAULT SIGNAL
FAULT LOCK

N
RN N
]N
| l OIO:O]O
O'OiG!O 0-0'0i0JCc

|
[
J

.‘

)

0 0¢

Appendix D

SBI Silo Comparator Register
ID Address 1C

Processor Address 32
31 3029

\
|

LOCK——J
SILO
SILO INTERRUPT ENABLE

L A

24 23

LOCK UNCODITIONAL

g 7

16 15

loolo 0 olol ‘o‘o
0, 0!i o'olo
]
|

LOCK CODE

MASK OR COMMAND
TAG

COUNT

SBl/Cache Maintenance Register
ID Address 1D

Processor Address 33

T LTI TFEEEE
T
MTI‘“’—J 1T

FAULT

DATA FAULT

FORCE INVALIDATE

REVERSE CACHE PARITY

1
MISS GROUP
FORCE REPLACE
GROUP 0

FORCE MISS GROUP 0

FORCE

)

———

REVERSE PARITY BITO
FORCE WRITE SEQUENCE

FORCE_UNEXPECTED READ__I
MULTIPLE TRANSMITTER FAULT
FORE
MAINTENANCE lDENTIFICATION——J
ENABLE SBI INVALIDATE

16 15

2428

—————— ———

‘‘ ‘
I | ‘
;

| |

FORCE REPLACE GROUP 1
DISABLE SBI

REVERSE PARITY BIT 1
GROUP 1 MATCH
GROUP 0 MATCH
FORCE TIME OUT

Cache Parity Register
ID Address 1E
Processor Address —
0

8 7

16 15

B2,
0|0 o'ol l ’ | Lolo o[olo o{ol; .aom B2B3|BOB] 32335051 azlaom
b

]

ANT ERROR
CPU ERROR

—

GROUP1 DATA PARITY OK

GROU: ) DATA PARITY OK

GROUP 0 ADDRESS PARITY OK
GROUP1 ADDRESS PARITY OK
307

4
|

¥A

$
‘

—

$
'
i

—

Appendix D

Reserved Register
ID Address 1F
Processor Address —
3

2423

16 15

Micro Stack Register
ID Address 20

Processor Address
—
31

16 15

eloleleleleolefelolofefe
o lolo [olelo,

]

—

CONTROL STORE ADDRESS

Micro Match Register
ID Address 21

Processor Address 3C
31

2423

1615

Mo]o’olo]o,o’olololo]olo[o]o;olo]olollz 1N109 8765432 :!
T

CONTROL

STORE ADDRESS

Writable Control Store Address Register
ID Address 22

Processor Address 2C
31

24 23

16 15

MO'O'0,0’0(0)0,0!0[0‘OIOIOIOIOI l

1 L, —

INVERT PARITY

MODULO THREE COUNTER
CONTROL STORE ADDRESS

IYZ nio 9 8l7 6 54 3 2 q
"

J
T

Writable Control Store Data Register

ID Address 23
Processor Address 2D
kll

16 15

—

DATA TC WRITEABLE CONTROL STORE

308

Appendix D

PO Base Register

ID Address 24

Processor Address 08

210

¥ 15

(SR

BASE VIRTUAL ADDRESS FOR PO SPACE PAGE TABLE ENTRIES ——-J

P1 Base Register

ID Address 25

Processor Address 0A
210

6 15

RPN

BASE VIRTUAL ADDRESS FOR P1 SPACE PAGE TABLE ENTRIES_——’

System Base Register
ID Address 26

Processor Address 0C

2 10

16 15

BASE PHYSICAL ADDRESS FOR SYSTEM SPACE
PAGE TABLE ENTRIES

lo]o]

Reserved Register
ID Address 27
Processor Address —

16 15

24 23

Kernel Stack Pointer Register
ID Address 28

Processor Address 00
3N

16 15

423

lllllLAlllllllllll
309

8 7

Appendix D

Executive Stack Pointer Regster
ID Address 29
Processor Address 01
k]

24 23

16 15

Supervisor Stack Pointer Register
ID Address 2A

Processor Address 02

2423

16 15

User Stack Pointer Register
ID Address 2B

Processor Address 03

24 23

16 15

L.-l-..lll.l..ll
Interrupt Stack Pointer Register
ID Address 2C
Processor Address 04

24 23

1619

First Part Done Address Register
ID Address 2D

Processor Address —
an__

— L ]

‘.;.ln;;llxxl..i

16 15

Appendix D

D Save Register

24 23

16 15

8§

ID Address 2E
Processor Address —
7

Aljllllllllll]nlLllll lJllALlJ

Q Save Register
ID Address 2F

.,.114:l|111..11;.11111[..1L..1

Processor Address —

Temp 0 to Temp 9 Registers

2423

16 15

8 7

.;11.1:[111].;1]1..1;11»AllA;

ID Address (30 to 39)
Processor Address —

Process Control Block Base Register
ID Address 3A

16 15

Processor Address 10

PHYSICAL ADDRESS OF PROCESS CONTROL BLOCK———“

System Control Block Base Register
ID Address 3B

Processor Address 11
H

N | I

PHYSICAL PAGE ADDRESS OF THE SYSTEM CONTROL BLOCK—J
311

8 7

1615

24 23

| LJ
_J

Appendix D

PO Length Register

ID Address 3C
Processor Address 09
31

242322 21

0000
PN
B

615

00
1

—

LENGTH OF PO PAGE TABLE (IN LONGWORDS)} S

P1 Length Register

ID Address 3D
Processor Address 0B
3

2423 22 21

LOOOOO
-

OOI

1615

—

LENGTH OF P1 PAGE TABLE {IN LONGWORDS)

System Length Register
ID Address 3E

2423 222

16 15

&OOOOOOOOOI
1

q i

[<)

Processor Address 0D

—

LENGTH OF SYSTEM PAGE TABLE{IN LONGWORDS)

Reserved Register
ID Address 3F

_ 2423

%15

312

[ =

Processor Address —

APPENDIX E

ADDRESS VALIDATION RULES
The memory management system described in Chapter 6 separates
validation from the access of arguments. It is necessary to adopt certain coding conventions to prohibit unauthorized user access to sensitive data. Specifically it must not be possible for a user to call an inner
access mode in such a way that will corrupt system integrity (e.g.,
cause supervisory code to write over itself) or incorrectly allow access
to data that would otherwise have been inaccessible (e.g., the reading
of a password table).

The following discussion sets forth operating system requirements
that must be adhered to when accessing arguments from an inner
access mode to avoid a breach of security.

The following requirements are made concerning operating system
software:

Operating system software (kernel and executive mode) is trustworthy and does not maliciously attempt to break down the protection mechanisms (e.g., change the mapping or protection of
pages at arbitrary times).

The protection of a shared page may not be changed uniess the

The protection of a page with a nonzero 1/0 pending count (a

share count (a software construct) is one and the process attempting the change is that sharer. Share count=a software
maintained record of the number of processes sharing a page.

software construct) may not be changed until the count goes to
Zero.

Operating system software will not deliver ASTs to outer access
modes while the process is executing in an inner access mode.

Arguments passed to an inner access mode can be maliciously
destroyed asynchronously by another process (e.g., shared data)

or by an 1/0 transfer, but not by a less privileged mode of the
executing process itself.

Kernel and executive stacks are never allocated in shared memory or accessible to other than their respective access modes.

The following summarizes related aspects of the VAX hardware:
1. Four access modes are provided and there is a stack per-process

per-access mode.

Protection is hierarchical with the innermost access mode being

the least restricted and the outermost the most restricted.
313

Appendix E

Four instructions are provided to change the processor mode
to
the four access modes (CHMU, CHMS, CHME, and CHMK);
furthermore, when a process is executing a change mode instruction

the access mode can only be decreased (changed to a more
privileged mode) or left the same.

Two instructions are provided to validate the accessibility of arguments: Probe Read (PROBER) and Probe Write (PROBEW).

These instructions validate the accessibility of arguments using

the maximization of the Previous Mode field of PSL and a
specified access mode. Thus only current and more restricted access
modes can be probed.

The Return from Interrupt instruction (REI) insures that the
cur-

rent mode field of the restored PSL is greater than or equal to
the
current mode field of the current PSL and that the previous mode

field of the restored PSL is greater than or equal to the current
mode field of the restored PSL.

Given the previous operating system requirements, the following rules

guarantee that less privileged

modes cannot pass erroneous ad-

dresses to more privileged modes.
1.

All addresses (including indirect addresses) passed as argument

s
to an inner access mode must be copied (preferably to a register,

but in any case to an area of memory that is not modifiable by
less
privileged modes) before the accessibility of the actual argument

is validated. In some programs such an address will later be used

asynchronously

post

information

back

to an outer access

mode. In such cases, the least privileged access mode that can

perform the specified read or write operation must be copied
from the corresponding page table entry and stored with the argument address.

NOTE
Using least privileged does not work properly when

the data structure resides in pages with different
protection and the first page has a lesser protection
value than the others. When checking the accessibil-

ity of such a structure in the context of the serial
execution of the process, the check will succeed, but

later when the accessibility is checked again during
the asynchronous posting of information, the check
will fail. This situation is considered to be an operat-

ing system bug (may cause the generation of a bug
check) and merely causes no information to be post-

ed.

314

Appendix E

The synchronous validation of argument addresses (i.e., as the

The asynchronous validation of argument addresses (i.e., as the

result of serial program execution) must be explicitly coded using
Probe instructions specifying an access mode of zero (i.e., cause
maximization to previous access mode).

result of software interrupts) must be explicitly coded using Probe
instructions specifying the least privileged access mode stored
when the argument address was saved (see 1) and with a previous
access mode field equal to or greater than that of the current
mode field of PSL (i.e., cause maximization to least privileged
access mode).

4.
5.

All arguments to be written must be PROBEWed before they are
written (otherwise there would be a potential protection violation).
All arguments to be read must be PROBERed before they are
read to defend against arguments mapped to I/O space and
thereby causing an 1/0 side effect.

All addresses passed from an outer access mode to an inner
access mode must be copied and validated before being passed
as arguments in a call to a more inner access mode. This insures
the integrity of intermediate modes.

This discussion is centered on the validation of argument addresses.

There are other arguments that also deserve similar handling. Such
arguments are typically address modifiers (e.g., a buffer length) and in
most cases must also be copied to insure system integrity.

315

316

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BYTE DISPLACEMENT

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CONTENTS OF P18R
VIRTUAL ADDRESS OF PIPTE

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31130729 (28 27‘{»26 25| 2at23t22 {21 (20w |17

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VIRTUAL PAGE NUMBER {LONGWORD)

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320

APPENDIX G

OPERAND SPECIFIER
NOTATION

OPERAND SPECIFIERS

Operand specifiers are described in the following way:
<name> <access type> <data type>
where:

Name is a suggestive name for the operand in the context of the
instruction. The name is often abbreviated.

Access type is a letter denoting the operand specifier acces type:
a

Calculate the effective address of the specified
oprand. Address is returned ina longword which is
the actual instruction operand. Context of address
calculation is given by <data type>.

No operand reference. Operand‘specifier isa

branch displacement. Size of branch displacement
is given by <data type>.

Operand is read, potentially modified and written.

Note that this is NOT an indivisible memory opera-

tion. Also note that if the operand is not actually

modified, it may not be written back. However, modi-

fy type oprands are always checked for both read
and write accessibility.

Operand is read only.

Calculate the effective address of the specified operand. If the effective address is in memory, the address is returned in a longword which is the actual
instruction operand. Context of address calculation
is given by <data type>.

it the effective addres is Rn, then the operand actual-

ly appears in R[n], orinR[n+1]’R[n].
Operand is written only.
321

Appendix G

“Xg0——ago

Data type is a letter denoting the data type of

the operand:

byte
double floating
floating
longword
quadword
word

first data type specified by instruction
second data type specified by instruction

OPERATION DESCRIPTION NOTATION

The operation of each instruction is given as a sequen

assigment statements in an ALGOL-like syntax.

define the syntax formally; it is assumed to be
+

ce of control and

No attempt is made to

familiar to the reader.

addition
ubtraction, unary minus

multiplication

division (quotient only)

¥ *

’

exponentiation

concatenation

is replaced by

is defined as
Rn or R[n]

PC, SP, FP, or

contents of register Rn

the contents of register R15, R14, R13, or R12

respectively

PSW

the contents of the processor status word

PSL

the contents of the processor status long word

(x)

contents of memory location whose address

(x)+

contents of memory location whose addres

is x

s is X; X

incremented by the size of operand referenced

=(x)

at x

x decremented by size of operand to be referen

ced
at x; contents of memory location whose address
is x

<Xiy>

a modifier which delimits an extent from bit
position
X to bit position y inclusive

<x1,x2,....xn>

a modifier which enumerates bits x1 WX2...,XN

322

Appendix G

x through y inclusive

X...Y

arithmetic parentheses used to indicate precedence

AND

logical AND

logical OR

XOR

logical XOR

NOT
LSS

LSSU

logical (ones) conplement
less than signed
less than unsigned

LEQU

less than or equal signed
less than or equal unsigned

EQL

equal signed

EQLU

equal unsigned

NEQ

not equal signed

NEQU

not equal unsigned

LEQ

GEQ
GEQU
GTR

greater than or equal signed
greater than or equal unsigned
greater than signed

GTRU

greater than unsigned

REM (x,Y)

remainder of x divided by y
minimum unsigned of xandy

SEXT (x)
ZEXT (x)
MINU (x, Y)

is signed extended to size of oprand needed
is zero extended to size of operand needed

The following conventions are used:

of
e Other than that caused by () +,0or —( ), and the advancement
side
left
the
on
ing
appear
nds
opera
of
ns
portio
or
PC, only oprands
of assignment statements are affected.

e No operator precedence is assumed, other than that replacement

(<) has the lowest precedence. Precedence is indicated explicityly
by{ }.
e All arithmetic, logical, and relational operators are defined in the

g opercontext of their operand. For example “+” applied to floatinds
is an

ands means a floating add while “+” applied to byte opera
integer byte add. Similarly, “LSS" is a floating comparison when
323

Appendix G

applied to floating operads while
“LSS"” is an integer byte comparison when applied to byte operands.

Instruction operands are evaluated

fier conventions. The order in
tion description has no effect

according to the operand speci-

which operands appear in the

on the order of evaluation.

instruc-

Condition codes are in general affect
results, not on “true” results (whic

ed on the value of actual stored

h might be generated internally

greater precision). Thus,
for example, 2 positive integ
ers can be

added together and the sum stored
, because of overfiow, as a

negative value. The condition
codes will indicate a negative
value
even though the “true” result is
clearly positive.

324

GLOSSARY

an instruction and
abort An exception that occurs in the middle ofindete
rminate state,
an
in
y
memor
and
potentially leaves the registers
so that the instruction cannot necessarily be restarted.

absolute indexed mode An indexed addressing mode in which the
base operand specifier is addressed in absolute mode.

as the
absolute mode In absolute mode addressing, the PC is used
adthe
ns
contai
PC
The
mode.
ed
deferr
t
register in autoincremen
dress of the location containing the actual operand.

(month, day,
absolute time Time values expressing a specific date
expressed
always
are
values
time
te
and year) and time of day. Absolu
in the system as positive numbers.

s modes in which
access mode 1. Any of the four processor acces
from most to
order
in
are,
modes
software executes. Processor access
(mode 1),
ive
execut
0),
(mode
kernel
least privileged and protected:
ssor is in
proce
the
When
3).
(mode
user
and
2),
supervisor (mode
l of, and
contro
ete
kernel mode, the executing software has complsor is in any
other
proces
the
responsibility for, the system. When

cmode, the processor is inhibited from executing privilegedt instru
access
curren
the
ns
contai
ord
Longw
Status
sor
tions. The Proces
mode field. The operating system uses access modes to defines.proFor
tection levels for software executing in the context of a proces
most
is
and
mode
ive
execut
and
kernel
in
example, the executive runs

and runs in
protected. The command interpreter is less protected
and is not more
supervisor mode. The debugger runs in user mode
protected than normal user programs.

accesses instruction
access type 1. Theway in which the processor
y, address, and branch.

operands. Access types are: read, write, modif
its arguments.
2. The way in which a procedure accesses

address that is not
access violation An attempt to referencetoanrefer
ence an address
pt
attem
an
or
ry
memo
mapped into virtual
that is not accessible by the current access mode.
325

address

A number used by the operating syste

m and user software

to identify a storage location. See
also virtual address and physic
al

address.

address access type

The specified operand of an instruction

directly accessed by the instruction.
The address of the

is not

specified op-

erand is the actual instruction
operand. The context of the addre
ss
calculation is given by the data
type of the operand.

addressing mode
example,

The way in which an operand
is specified; for

the way in which the effective
address of an instruction

operand is calculated using the genera
register addressing modes are called

l registers. The basic general

: register, register deferred, au-

toincrement, autoincrement deferr
ed, autodecrement, displacement,
and displacement deferred. In
addition, there are six indexed
ad-

dressing modes using two genera
l registers, and literal mode addressing. The PC addressing modes
are called: immediate (for register deferred mode using the PC),
absolute (for autoincrement deferr
ed
mode using the PC), and branch.

address space

The set of all possible addresses
available to a

process. Virtual address space
refers to

the set of all possible virtual

addresses. Physical address space
refers to the set of all possible
physical addresses sent out on the
SBI.

allocate a device

To reserve a particular device unit

use. A user process can allocate

allocated by any other process.

for exclusive

a device only when that device is

not

alphanumeric character
An upper or lower case letter (A-Z,
a-z), a
dollar sign ($), an underscore (=), or
a decimal digit (0-9).

American Standard Code for Inform

ation Interchange (ASCII)

set of 8-bit binary numbers repres
enting the alphabet, punctuation,

numerals, and other special symbo

ls used in text representation and

communications protocol.

Ancillary Control Process (ACP)

A process that acts as an interface
driver. An ACP provides functions

between user software and an 1/0

supplemental to those performed
in the driver, such as file and directory management. Three examples
of ACPs are: the Files-11 ACP
(F11ACP), the magnetic tape ACP
(MTACP), and the networks ACP
(NETACP).

Argument Pointer

General register 12 (R12). By convention,
AP

contains the address of the base

of the argument list for procedures

initiated using the CALL instructions

asynchronous

A mode of activity that operates withou

t respect to a
clock. For example, asynchronous
hardware uses ready and done

326

Glossary

signals to schedule operations rather than time intervals. If two activi-

ties are asynchronous, the second can begin before the first is complete.

Asynchronous System Trap

A software-simulated interrupt to a

user-defined service routine. ASTs enable a user process to be notified asynchronously with respect to its execution of the occurrence of
a specific event. If a user process has defined an AST routine for an
event, the system interrupts the process and executes the AST routine
when that event occurs. When the AST routine exits, the system resumes the process at the point where it was interrupted.

Asynchronous System Trap level (ASTLVL) A value keptin an internal processor register that is the highest access mode for which an
AST is pending. The AST does not occur until the current access

mode drops in priority (rises in numeric value) to a value greater than
or equal to ASTLVL. Thus, an AST for an access mode will not be
serviced while the processor is executing in a higher priority access
mode.

autodecrement indexed mode An indexed addressing mode in
which the base operand specifier uses autodecrement mode addressing.

autodecrement mode

In autodecrement mode addressing, the con-

tents of the selected register are decremented, and the result is used

as the address of the actual operand for the instruction. The contents

of the register are decremented according to the data type context of
the register: 1 for byte, 2 for word, 4 for longword and floating, 8 for
quadword and double floating.

autoincrement deferred indexed mode An indexed addressing
mode in which the base operand specifier uses autoincrement de-

ferred mode addressing.

autoincrement deferred mode In autoincrement deferred mode
addressing, the specified register contains the address of a longword
which contains the address of the actual operand. The contents of the
register are incremented by 4 (the number of bytes in a longword). If

the PC is used as the register, this mode is called absolute mode.
autoincrement indexed mode An indexed addressing mode in
which the base operand specifier uses autoincrement mode addressing.

autoincrement mode In autoincrement mode addressing, the contents of the specified register are used as the address of the operand,
then the contents of the register are incremented by the size of the
operand.
327

balance set

The set of all process working sets currently resident in

physical memory. The processes whose working
sets are in the bai-

ance set have memory requirements that balance with
available memory. The balance set is maintained by the system swapper
process.

base operand address

The address of the base of a table or array
referenced by index mode addressing:

base operand specifier

The register used to calculate the base

operand address of a table or array referenced by
index mode ad-

dressing.

base priority

The process priority that the system assigns a process

when it is created. The scheduler never schedules a process

below its
base priority. The base priority can be modified only
by the system

manager or the process itself.

base register
A general register used to contain the address of the
first entry in a list, table, array, or other data structure.
BBCCI
Branch on Bit Clear and Clear Interlock instruction. One
can
think of it as a Clear Interlock Bit instruction with a branch
side-effect if
the bit is already clear. This instruction permits interlock
ed access to a
control variable.

BBSSI

Branch on Bit Set and Set Interiock instruction. One can

think of it as a Set Interlock Bit instruction with a branch side-effect

the bit is already set. This instruction permits interlocked access
control variable.

binary

bit

A number system using two symbols: 0 and 1.

Binary digit. Any two-state device. A bit is said to be set

when it represents the value 1, to be clear (or off) when

the value 0.

bit string

to a

(or on)

it represents

See variable-length bit field.

bits per inch

A measure of the recording density of magnetic tape,
indicating the number of bits that can fit in one inch
of the recording
surface.
block
1. The smallest addressable unit of data that the specified
device can transfer in an I/0 operation (512 contiguous bytes
for most
disk devices). 2. An arbitrary number of contiguous bytes
used to

store logically related status, control, or other processin

g information.

block I/0

A data accessing technique in which the program manipu-

lates the blocks (physical records) that make up a file,
instead of its

logical records.

328

Glossary

bootstrap block

A block in the index file on a system disk that con-

tains a program that can load the operating system into memory and
start its execution.

buffer

A temporary data storage area in a process address space.

Buffered Data Path (BDP) A data path supporting block transfer
devices on the UNIBUS. A block transfer device is one that transfers
data to consecutive increasing addresses.

byte A byte is eight contiguous bits starting on an addressable byte
boundary. Bits are numbered from the right, 0 through 7, with bit 0 the
low-order bit. When interpreted arithmetically, a byte isatwo’s
complement integer with significance increasing from bits 0 through 6.
Bit 7 is the sign bit. The value of the signed integer is in the range -128
to 127 decimal. When interpreted as an unsigned integer, significance
increases from bits 0 through 7 and the value of the unsigned integer
is in the range 0 to 255 decimal. A byte can be used to store one ASCII
character.

cache memory A small, high-speed memory placed between slower
main memory and the processor. A cache increases effective memory
transfer rates and processor speed. It contains copies of data recently
used by the processor, and fetches several bytes of data from memory
in anticipation that the processor will access the next sequential series
of bytes.

call frame

See stack frame.

call instructions The processor instructions CALLG (Call Procedure
with General Argument List) and CALLS (Call Procedure with Stack
Argument List).

call stack The stack, and conventional stack structure, used during
a procedure call. Each access mode of each process context has one
call stack, and interrupt service context has one call stack.
central processor The collection of interconnected logic modules
that execute the control and arithmetic functions of a computer system. A central processor includes the logic which fetches and decodes
instructions stored in main memory, an arithmetic logical unit for computation, and the primary /O interfaces for the computer system.

Change Mode instruction The processor instruction that raises the
access mode of the currently executing procedure by trapping to the
operating system’s change mode handlers. Procedures can only issue
a CHM to a more protected access mode. An RE! issued from within
that access mode changes the mode back to a less protected access
mode.

329

Giossary

channel

A logical path connecting a user process to a physical de-

vice unit. A user process requests the operating system to assign a
channel to a device so the process can transfer data to or from that

device.

character

A symbol represented by an ASCIl code. See also alphan-

umeric character.

character string

A contiguous set of bytes. A character string is
identified by two attributes: an address and a length. Its address is the

address of the byte containing the first character of the string.

Subsequent characters are stored in bytes of increasing addresses.

The length is the number of characters in the string.
command

An instruction, generally an English word, typed by the

user at a terminal or included in a command file which requests the

software monitoring a terminal or reading a command file to perform
some well-defined activity. For example, typing the COPY command
requests the system to copy the contents of one file into another file.

compatibility mode

A mode of execution that enables the central

processor to execute non-privileged PDP-11 instructions. The operat-

ing system supports compatibility mode execution by providing an
RSX-11M programming environment for an RSX-11M task image. The
operating system compatibility mode procedures reside in the control

region of the process executing a compatibility mode image. The pro-

cedures intercept calls to the RSX-11M executive and convert them to

the appropriate operating system functions.

compiler

A program that translates a program written in a high-level
language (such as FORTRAN or BASIC) into an object program.

condition

An exception condition detected and declared by soft-

ware. For example, see failure exception mode.

condition codes

Four bits in the Processor Status Word that indi-

cate the results of previously executed instructions.

condition handler
execute when

A procedure that a process wants the system to

an exception condition occurs. When an exception

condition occurs, the operating system searches for a condition

handler and, if found, initiates the handler immediately. The condition
handler may perform some action to change the situation that caused

the exception condition and continue execution for the process that
incurred the exception condition. Condition handlers execute in the

context of the process at the access mode of the code that incurred

the exception condition.

condition value
tion condition.

A 32-bit quantity that uniquely identifies an excep330

Glossary

context

The environment of an activity. See also process context,

hardware context, and software context.

context switching Interrupting the activity in progress and switching
to another activity. Context switching occurs as one process after
another is scheduled for execution. The operating system saves the
interrupted process’ hardware context in its hardware process control
block (PCB) using the Save Process Context instruction, loads another

process’ hardware PCB into the hardware context using the Load
Process Context instruction, scheduling that process for execution.
contiguous Physically adjacent and/or consecutively numbered
units of data.

contiguous area A space allocation on disk where the reserved area
for all blocks in a file is physically adjacent on the recording medium.

console The manual control unit integrated into the central processor. The console includes an LSI-11 microprocessor and a serial line
interface connected to a hard copy terminal. It enables the operator to
start and stop the system, monitor system operation, and run diagnostics.

console terminal

The hard copy terminal connected to the central

processor console.

control region The highest-addressed half of per-process space
(the P1 region). Control region virtual addresses refer to the process-

related information used by the system to control the process, such
as: the kernel, executive, and supervisor stacks, the permanent /0

channels, exception vectors, and dynamically used system procedures (such as the command interpreter and RSX-11M program-

ming environment compatibility mode procedures). The user stack is
also normally found in the control region, although it can be relocated
elsewhere.

Control Region Base Register (P1BR) The processor register, or its
equivalent in a hardware process control block, that contains the base
virtual address of a process control region page table.

Control Region Length Register (P1LR) The processor register, or
its equivalent in a hardware process control block, that contains the
number of nonexistent page table entries for virtual pages in a process
control region.

copy-on-reference A method used in memory management for
sharing data until a process accesses it, in which case it is copied
before the access. Copy-on-reference allows sharing of the initial values of a global section whose pages have read/write access but contain pre-initialized data available to many processes.
331

current access mode
The processor access mode of the currently
executing software. The Current Mode field of the Processor
Status
Longword indicates the access mode of the currently
executing software.

cylinder

The tracks at the same radius on all recording surfaces

disk.

of a

data structure
Any table, list, array, queue, or tree whose format
and access conventions are well-defined for reference by one
or more
images.
data type

In general, the way in which bits are grouped and in-

terpreted. In reference to the processor instructions,
the data type
an operand identifies the size of the operand and
the significa

nce of

the bits in the operand. Operand data types include:
byte, word,
longword, and quadword integer, floating and double floating,
charac-

ter string, packed decimal string, and variable-length

delta time

bit field.

A time value expressing an offset from the current date

and time. Delta times are always expressed in the system
as negative
numbers whose absolute value is used as an offset
from the current

time.

demand paging
One technique that enables a program to execute
without having all of its pages residentin physical memory.
In demand
paging, a program page is not brought into physical memory
until itis

actually needed. If there is insufficient physical
memory, the least recently used page in the system is moved out of memory
to make room

for the needed page. The page moved out may belong to
in the system residing in physical memory. For the

this system, see paging.

device

any program

technique used in

The general name for any physical terminus or link connect-

ed to the processor that is capable of receiving, storing,
or

transmitting data. Card readers, line printers, and terminals are
examples of
record-oriented devices. Magnetic tape devices and
disk devices are
examples of mass storage devices. Terminal line
interfaces and

interprocessor links are examples of communications devices.

device interrupt
An interrupt received on interrupt priority level 16
through 23. Device interrupts can be requested only by
devices, con-

trollers, and memories:

device name

The field in a file specification that identifies the device

unit on which a file is stored. Device names also include the
mnemon-

ics that identify an 1/0 peripheral device in a data transfer
request. A
device name consists of a mnemonic followed by a controller
identification letter (if applicable), followed by a unit number (if applicable
),
and ends with a colon (:).

332

Glossary

device queue

See spool queue.

device register A location in device controlier logic used to request
device functions (such as I/0 transfers) and/or report status.
device unit One drive, and its controlling logic, of a mass storage
device system. A mass storage system can have several drives connected to it.

diagnostic

A program that tests logic and reports any faults it

detects.

Direct Data Path (DDP) A data path allowing UNIBUS transfers to
random SBI addresses. Each UNIBUS transfer through the direct data
path is mapped directly to an SBI transfer, thereby allowing only one
word of information to be transferred during an SBI cycie.

direct 1/0 An I/0 operation in which the system locks the pages
containing the associated buffer in memory for the duration of the /0
operation. The 1/0 transfer takes place directly from the process
buffer.

direct mapping cache A cache organization in which only one address completion is needed to locate any data in the cache because
any block of main memory data can be placed in only one possible
position in the cache. Contrast with fully associative cache.
displacement deferred indexed mode An indexed addressing
mode in which the base operand specifier uses displacement deferred
mode addressing.

displacement deferred mode In displacement deferred mode addressing, the specifier extension is a byte, word, or longword displacement. The displacement is sign-extended to 32 bits and added to a
base address obtained from the specified register. The result is the
address of a longword which contains the address of the actual operand. If the PC is used as the register, the updated contents of the PC
are used as the base address. The base address is the address of the
first byte beyond the specifier extension.

displacementindexed mode Anindexed addressing modein
which the base operand specifier uses displacement mode addressing.

displacement mode In displacement mode addressing, the specifier extension is a byte, word, or longword displacement. The
displacement is sign-extended to 32 bits and added to a base address
obtained from the specified register. The result is the address of the
actual operand. If the PC is used as the register, the updated contents
of the PC are used as the base address. The base address is the
address of the first byte beyond the specifier extension.
333

Giossary

Distributed Priority Arbitration Each device connected to the SBI
decides whether or not it has access to the bus (rather than a central
arbitrator making the decision). That is, each device on the SBI main-

tains its own priority arbitration logic.

double floating datum

Eight contiguous bytes (64 bits), starting on

an addressable byte boundary, which are interpreted as containing

floating point number. The bits are labeled from right to ieft, 0

to 63. A

containing bit 0. Bit 15 contains the sign of the number. Bits 14

through

four-word floating point number is identified by the address of the

byte

7 contain the excess 128 binary exponent. Bits 63 through
16 and 6
through 0 contain a normalized 56-bit fraction with the redundant
most
significant fraction bit not represented. Within the fraction,
bits of

decreasing significance go from 6 through 0, 31 through
16, 47
through 32, then 63 through 48. Exponent values of 1 through
255 in
the 8-bit exponent field represent true binary exponents
of -128 to
127. An exponent value of 0 together with a sign bit of 0
represent a

floating value of 0. An exponent value of 0 with a sign bit of
1 is a
reserved representation; floating point instructions processing
this

value return a reserved operand fault. The value of a floating datum is
in the approximate range (+ or -) 0.29 x 10**-38 to 1.7 x 10**38.
The
precision is approximately one part in 2**55 or sixteen decimal

drive

on which a recording medium (disk cartridge, disk pack,
tape reel) is mounted.

driver

digits.

The electro-mechanical unit of a mass storage device system
or magnetic

The set of code that handles physical I/0 to a device.

echo
A terminal handiing characteristic in which the character
s
typed by the terminal user on the keyboard are also displayed
on the
screen or printer.

effective address

The address obtained after indirect or indexing

modifications are calculated.

error correction code (ECC)

tion, double bit error detection.

Single bit error detection and correc-

error logger
A system process that empties the error log buffers
and writes the error messages into the error file. Errors logged
by the

system include memory system érrors, device errors
and timeouts,

and interrupts with invalid vector addresses.
exception

An event detected by the hardware (other than an interruptor jump, branch, case, or call instruction) that changes
the normal
flow of instruction execution. An exception is always
caused by the
execution of an instruction or set of instructions (whereas

an interrupt

is caused by an activity in the system independent of the
current

334

Glossary

instruction). There are three types of hardware exceptions: traps,
faults, and aborts. Examples are: attempts to execute a privileged or
reserved instruction, trace traps, compatibility mode faults, breakpoint instruction execution, and arithmetic traps such as overflow,
underflow, and divide by zero.

exception condition A hardware- or software-detected event other
than an interrupt or jump, branch, case, or call instruction that
changes the normal flow of instruction execution.
exception enables
exception vector

executable image

See trap enables.
See vector.

An image that is capable of being run in a proc-

ess. When run, an executable image is read from afile for execution in
a process.

executive The generic name for the collection of procedures included in the operating system software that provides the basic control
and monitoring functions of the operating system.

executive mode

The second most privileged processor access

mode (mode 1). The record management services (RMS) and many of

the operating system’s programmed service procedures execute in
executive mode.

failure exception mode A mode of execution selected by a process
indicating that it wants an exception condition declared if an error
occurs as the result of a system service call. The normal mode is for
the system service to return an error status code for which the process
must test.

fault A hardware exception condition that occurs in the middle of an
instruction and leaves the registers and memory in a consistent state,
so that eliminating the fault and restarting the instruction will give

correct results.
field 1. See variable-length bit field.

'
2. A set of contiguous bytes in

a logical record.

floating (point) datum Four contiguous bytes (32 bits) starting on an
addressable byte boundary. The bits are labeled from right to left from
0 to 31. A two-word floating point number is identified by the address
of the byte containing bit 0. Bit 15 contains the sign of the number. Bits
14 through 7 contain the excess 128 binary exponent. Bits 31 through

16 and 6 through 0 contain a normalized 24-bit fraction with the redundant most significant fractionbit not represented. Withinthe fraction,
bits of decreasing significance go from bit 6 through 0, then 31
through 16. Exponent values of 1 through 255 in the 8-bit exponent
335

Glossary

field represent true binary exponents of -128 to 127. An
exponent
value of 0 together with a sign bit of 0 represent a floating
value of 0.

An exponent value of 0 with a sign bit of 1 is a reserved representa
tion;
floating point instructions processing this value return a reserved
operand fault. The value of a floating datum is in the approxima
te range
(+ or-)0.29 x 10**-38 to 1.7 x 10**38. The precision
is approximately

one partin 2°° or seven decimal digits.
foreign volume

Any volume other than a Files-11 formatted volume

which may or may not be file structured.

frame pointer
General register 13 (R13). By convention, FP contains
the base address of the most recent call frame on the stack.

fully associative cache

A cache organization in which any block of
data from main memory can be placed anywhere in the cache.
Address comparison must take place against each block in the
cache to

find an yparticular block. Contrast with direct mapping cache.
general reNister

Any of the sixteen 32-bit registers used as the pri-

mary operands of the native mode instructions. The

general registers

include 12 general purpose registers which can be used as accumula-

tors, as counters, and as pointers to locations in main
memory, and

the Frame Pointer (FP), Argument Pointer (AP), Stack Pointer
(SP),
and Program Counter (PC) registers.
generic device name

A device name that identifies the type of

device but not a particular unit; a device name in which the
specific

controller and/or unit number is omitted.

giga

Metric term used to represent the number 1 followed by nine

zeros.

hardware context

The values contained in the following register
s

while a process is executing: the Program Counter

Status Longword (PSL); the 14 general register

(PC); the Processor

s (R0 through R13); the

four processor registers (POBR, POLR, P1BR
and P1LR) that describe
the process virtual address space; the Stack
Pointer (SP) for the cur-

rent access mode in which the processor
is executing; plus the contents to be loaded in the Stack Pointer for
every access mode other
than the current access mode. While a
process is executing, its

hardware context is continually being update

d by the processor. While

a process is not executing, its hardware
context is stored in its hard-

ware PCB.

hardware process control block (PCB)

A data structure known to

the processor that contains the hardware context
when
not executing. A process’ hardware PCB resides

336

a process is

in its process header.

Glossary

Hit Rate (cache-main memory) The percentage of times the CPU
requests data and that data appears in cache, therefore not requiring
a main memory access.

image An image consists of procedures and data that have been
bound together by the linker. There are three types of images: execu-

table, sharable, and system.

image privileges

The privileges assigned to an image when it is

immediate mode

In immediate mode addressing, the PC is used as

linked. See process privileges.

the register in autoincrement mode addressing.

indexed addressing mode Inindexed mode addressing, two
registers are used to determine the actual instruction operand: an
index register and a base operand specifier. The contents of the index
register are used as an index (offset) into a table or array. The base
operand specifier supplies the base address of the array (the base
operand address or BOA). The address of the actual operand is calculated by multiplying the contents of the index register by the size (in
bytes) of the actual operand and adding the result to the base operand
address. The addressing modes resulting from index mode addressing are formed by adding the suffix “indexed” to the addressing mode
of the base operand specifier: register deferred indexed, autoincrement indexed, autoincrement deferred indexed (or absolute indexed),
autodecrement indexed, displacement indexed, and displacement deferred indexed.

index register

A register used to contain an address offset.

instruction buffer An 8-byte buffer in the processor used to contain
bytes of the instruction currently being decoded and to prefetch instructions in the instruction stream. The control logic continously

fetches data from memory to keep the 8-byte buffer full.
interleaving Assigning consecutive physical memory addresses alternately between two memory controllers.

interrupt An event other than an exception or branch, jump, case, or
call instruction that changes the normal flow of instruction execution.
Interrupts are generally external to the process executing when the

interrupt occurs. See also device interrupt, software interrupt, and
urgent interrupt.

interrupt priority level (IPL) The interrupt level at which the processor executes when an interrupt is generated. There are 31 possible
interrupt priority levels. IPL 1 is lowest, 31 highest. The levels arbitrate
contention for processor service. For example, a device cannot interrupt the processor if the processor is currently executing at an inter337

rupt priority level greater than the interrupt priority level of the

interrupt service routine.

interrupt service routine
interrupt occurs.

interrupt stack

device’s

Theroutine executed when a device

The system-wide stack used when executing in in-

terrupt service context. At any time, the processor is either in a process context executing in user, supervisor, executive or kernel mode,

or in system-wide interrupt service context operating with kernel privi-

leges, as indicated by the interrupt stack and current mode bits in the
PSL. The interrupt stack is not context-switched.

interrupt stack pointer

The stack pointer for the interrupt stack.
Unlike the stack pointers for process context stacks, which are stored

in the hardware PCB, the interrupt stack pointer is stored in an internal
register.

interrupt vector

See vector.

I/O driver

See driver.

I/O space

The region of physical address space that contains the

configuration registers, and device control/status and data
registers.

The space is located in physical address space, but can be
addressed
virtually through the SCBB register using the MTPR and MFPR
instructions.

job queue

A list of files that a process has supplied for processing
by a specific device, for example, a line printer.

kernel mode
The most privileged processor access mode (mode 0).
The operating system’s most privileged services, such as I/0
drivers
and the pager, run in kernel mode.

linker

A program that reads one or more object files created by
language processors and produces an executable image file,
a
sharable image file, or a system image file.
literal mode

In literal mode addressing, the instruction operandisa

constant whose value is expressed in a 6-bit field of the

instruction. If

the operand data type is byte, word, longword, or quadword, the

operand is zero extended and can express values in the range 0 through
63
(decimal). If the operand data type is floating or double floating,
the 6-

bit field is composed of two 3-bit fields, one for the exponent and the
other for the fraction. The operand is extended to floating or
double
floating format.

locality

See program locality.

338

Glossary

logical block

A block on a mass storage device identified using a

volume-relative address rather than its physical (device-oriented) ad-

dress or its virtual (file-relative) address. The blocks that constitute the
volume are labeled sequentially starting with logical block 0.
longword

Four contiguous bytes (32 bits) starting on an addressable

byte boundary. Bits are numbered from right to left with 0 through 31.

The address of the longword is the address of the byte containing bit
0. When interpreted arithmetically, a longword is a two’s complement
integer with significance increasing from bit 0 to bit 30. When interpreted as a signed integer, bit 31 is the sign bit. The value of the
signed integer is in the range -2,147,483,648 to 2,147,483,647. When
interpreted as an unsigned integer, significance increases from bit 0 to
bit 31. The value of the unsigned integer is in the range 0 through
4,294,967,295.

macro

A statement that requests a language processor to generate

a predefined set of instructions.

main memory

See physical memory.

mass storage device

A device capable of reading and writing data

on mass storage media such as a disk pack or a magnetic tape reel.

MASSBUS adapter

The NEXUS connecting the MASSBUS subsys-

tem to the SBI. The MASSBUS adapter provides virtual to physical
address mapping functionality, data transfer buffering between the
MASSBUS and main memory, and transfer of interrupts from the
MASSBUS device to the SBI.

memory controller

The NEXUS interfacing main memory to the SBI.

The memory controller provides the necessary timing and control to
complete all memory transactions.

memory management

The system functions that include the hard-

ware’s page mapping and protection and the operating system’s image activator and pager.

Memory Mapping Enable (MME)

A bit in a processor register that

governs address translation.

modify access type

The specified operand of an instruction or pro-

cedure is read, and is potentially modified and written, during that
instruction’s or procedure’s execution.

Monitor Console Routine (MCR)

The command interpreter in an

RSX-11 system.

mount a volume

1. To logically associate a volume with the physical

unit on which it is loaded (an activity accomplished by system software
at the request of an operator). 2. To load or place a magnetic tape or
339

Glossary

disk pack on a drive and place the drive on-line (an activity accomplished by a system operator).

native mode

The processor’s primary execution mode in which the

programmed instructions are interpreted as byte-aligned, variable-

length instructions that operate on byte, word, longword, and quadword integer, floating and double floating, character string, packed
decimal, and variable-length bit field data. The instruction execution
mode other than compatibility mode.
network

A collection of interconnected individual computer

systems.

NEXUS
nibble
node

SBlinterface logic.
The low-order or high-order four bits of a byte.
Anindividual computer system in a network.

numeric string

A contiguous sequence of bytes representing up to

decimal digits (one per byte) and possibly a sign. The numeric

string is specified by its lowest addressed location, its length, and its
sign representation.

offset

A fixed displacement from the beginning of a data structure.

System offsets for items within a data structure normally have an associated symbolic name used instead of the numeric displacement.
Where symbols are defined, programmers always reference the sym-

bolic names for items in a data structure instead of using the numeric
displacement.

opcode

The pattern of bits within an instruction that specify the op-

eration to be performed.

operand specifier

The pattern of bits in an instruction that indicate

the addressing mode, a register and/or displacement, which, taken
together, identify an instruction operand.

operand specifier type

The access type and data type of an instruc-

tion’s operand(s). For example, the test instructions are of read access
type, since they only read the value of the operand. The operand can

be of byte, word, or longword data type, depending on whether the
opcode is for the TSTB (test byte), TSTW (test word), or TSTL (test
longword) instruction.

operator’s console

Any terminal identified as a terminal attended

by a system operator.
packed decimal

A method of representing a decimal number by

storing a pair of decimal digits in one byte, taking advantage of the fact

that only four bits are required to represent the numbers zero through
nine.

340

Glossary

packed decimal string A contiguous sequence of up to 16 bytes
interpreted as a string of nibbles. Each nibble represents a digit except the low-order nibble of the highest addressed byte, which
represents the sign. The packed decimal string is specified by its
lowest addressed location and the number of digits.

page 1. A set of 512 contiguous byte locations used as the unit of
memory mapping and protection. 2. The data between the beginning
of file and a page marker, between two markers, or between a marker
and the end of afile.

page frame number (PFN) The address of the first byte of a page in
physical memory. The high-order 21 bits of the physical address of the
base of a page.

pager A set of kernel mode procedures that executes as the result of
a page fault. The pager makes the page for which the fault occurred

available in physical memory so that the image can continue execu-

tion. The pager and the image activator provide the operating system’s
memory management functions.

page table entry (PTE) The data structure that identifies the location
and status of a page of virtual address space. When a virtual page isin
memory, the PTE contains the page frame number needed to map the
virtual page to a physical page. When it is not in memory, the page
table entry contains the information needed to locate the page on
secondary storage (disk).

paging The action of bringing pages of an executing process into
physical memory when referenced. When a process executes, all of its
pages are said to reside in virtual memory. Only the actively used
pages, however, need to reside in physical memory. The remaining
pages can reside on disk until they are needed in physical memory. In

this system, a process is paged only when it references more pages

than it is allowed to have in its working set. When the process refers to
a page not in its working set, a page fault occurs. This causes the
operating system’s pager to read in the referenced page if it is on disk
(and, optionally, other related pages depending on a cluster factor),

replacing the least recently faulted pages as needed. A process pages

only against itself.

parity A count maintained to check the reliability of a group of bits.
Even parity refers to the use of a parity bit appended to a group of bits

which is set to make the sum of all the bits an even value, where odd
parity makes the sum of all the bits an odd value.
per-process address space See process address space.

341

Glossary

physical address
The address used by hardware to identify a location in physical memory or on directly-addressable secondary storage

devices such as a disk. A physical memory address consists of a page
frame number and the number of a byte within the page. A physical

disk block address consists of a cylinder or track and sector

number.

physical address space

The set of all possible 30-bit physical addresses that can be used to refer to locations in memory
(memory

space) or device registers (I/0 space).

physical block

A block on a mass storage device referred to by its
physical (device-oriented) address rather than a logical (volume-re
lative) or virtual (file-relative) address.
physical I/O functions

A set of I/0 functions that allow access to all

device level I/0 operations except maintenance mode.
physical memory

The memory modules connected to the SBI that

are used to store: 1) instructions that the processo
r can directly fetch

and execute, and 2) any other data that a processo
r is instructed to
manipulate. Also called main memory.

position dependent code
Code that can execute properly only in
the locations in virtual address space that are assigned
to it by the
linker.

position independent code

Code that can execute properly without
modification wherever it is located in virtual address space, even if its

location is changed after it has been linked. Gs)nerally, this code uses
addressing modes that form an effective address relative to the PC.

primary vector
A location that contains the starting address of
a
condition handler to be executed when an exceptio
n condition occurs.

If a primary vector is declared, that condition handler
is the first

handler to be executed.

privilege

See process privilege, user privilege, and image privilege.

privileged instructions

In general, any instructions intended for use

by the operating system or privileged system programs

instructions that the processor will not execute unless

. In particular,

the current ac-

cess mode is kernel mode (e.g., HALT, SVPCTX, LDPCTX,
MFPR).

process

MTPR, and

The basic entity scheduled by the system software that pro-

vides the context in which an image executes. A process consists
address space and both hardware and software context.

process address space
process context

of an

See process space.

The hardware and software contexts of a process.

342

Glossary

process control block (PCB) A data structure used to contain process context. The hardware PCB contains the hardware context. The
software PCB contains the software context, which includes a pointer
to the hardware PCB.

process header A data structure that contains the hardware PCB,
accounting and quota information, process section table, working set
list, and the page tables defining the virtual layout of the process.

process header slots That portion of the system address space in
which the system stores the process headers for the processes in the
balance set. The number of process header slots in the system determines the number of processes that can be in the balance set at any
one time.

process identification (PID)

The operating system’s unique 32-bit

binary value assigned to a process.

process page tables

The page tables used to describe process

virtual memory.

process priority The priority assigned to a process for scheduling
purposes. The operating system recognizes 32 levels of process priority, where 0 is low and 31 high. Levels 16 through 31 are used for
time-critical processes. The system does not modify the priority of a
time-critical process (although the system manager or process itself
may). Levels 0 through 15 are used for normal processes. The system
may temporarily increase the priority of a normal process based on
the activity of the process.

process privileges The privileges granted to a process by the
system, which are a combination of user privileges and image privileges. They include, for example, the privilege to: affect other
processes associated with the same group as the user’s group, affect
any process in the system regardless of UIC, set process swap mode,

create permanent event flag clusters, create another process, create a
mailbox, perform direct 1/0 to a file-structured device.

process space The lowest-addressed half of virtual address space,
where per-process instructions and data reside. Process space is di-

vided into a program region and a control region.

processor register A part of the processor used by the operating
system software to control the execution states of the computer system. They include the system base and length registers, the program

and control region base and length registers, the system control block
B G
amfhiarara
i
'
i
and many more.
request register,
interrupt
the~ software
base register,
[

343

Glossary

Processor Status Longword (PSL)

A system programmed proces-

sor register consisting of a word of privileged processor status and the

PSW. The privileged processor status information includes: the cur-

rent

IPL (interrupt priority level), the previous access mode, the
current access mode, the interrupt stack bit, the trace trap pending
bit, and the compatibility mode bit.

Processor Status Word (PSW)
The low-order word of the Processor
Status Longword. Processor status information includes: the condition

codes (carry, overflow, zero, negative), the arithmetic trap enable bits

(integer overflow, decimal overflow, floating underflow), and the trace

enable bit.

Program Counter (PC)
General register 15 (R15). At the beginning
of an instruction’s execution, the PC normally contains the address
of
a location in memory from which the processor will fetch the next
instruction it will execute.
program locality
A characteristic of a program that indicates how
close or far apart the references to locations in virtual memory
are

over time. A program with a high degree of locality does not
refer
many widely scattered virtual addresses in a short period of time.

program region
The lowest-addressed half of process address
space (PO space). The program region contains the image
currently

being executed by the process and other user code called by
the

image.

Program Region Base Register (POBR)

The processor register, or

its equivalent in a hardware process control block, that contains
the

base virtual address of the page table entry for virtual page
number 0
in a process program region.

Program Region Length Register (POLR)

The processor register,

or its equivalent in a hardware process control block, that
number of entries in the page table for a process program

pure code

contains the
region.

See reentrant code.

quadword
Eight contiguous bytes (64 bits) starting on an addressable byte boundary. Bits are numbered from right to left, 0 to 63. A

quadword is identified by the address of the byte containing the loworder bit (bit 0). When interpreted arithmetically, a quadword is a
two’s
complement integer with significance increasing from bit 0 to
bit 62.

Bit 63 is used as the sign bit. The value of the integer is in the

2% 10 2%°1.
queue

range -

1. n. A circular, doubly-linked list. See system
queue. v. To

make an entry in a list or table, perhaps using

2. See job queue.

344

the INSQUE instruction.

Glossary

queue priority

The priority assigned to a job placed in a spooler

queue or a batch queue.

read access type An instruction or procedure operand attribute indicating that the specified operand is only read during instruction or
procedure execution.

reentrant code Code that is never modified during execution. It is
possible to let many users share the same copy of a procedure or
program written as reentrant code.

register A storage location in hardware logic other than main memory. See also general register, processor register, and device register.
register deferred indexed mode An indexed addressing mode in
which the base operand specifier uses register deferred mode addressing.

register deferred mode In register deferred mode addressing, the
contents of the specified register are used as the address of the actual
instruction operand.

register mode In register mode addressing, the contents of the
specified register are used as the actual instruction operand.
return status code

See status code.

scatter/gather The ability to transfer in one I/0 operation data from
discontiguous pages in memory to contiguous blocks on disk, or data

from contiguous blocks on disk to discontiguous pages in memory.
secondary storage

Random access mass storage.

secondary vector A location that identifies the starting address of a
condition handler to be executed when a condition occurs and the

primary vector contains zero or the handler to which the primary vec-

tor points chooses not to handle the condition.

section A portion of process virtual memory that has common
memory management attributes (protection, access, cluster factor,

etc.). Itis created from an image section, a disk file, or as the result of a
Create Virtual Address Space system service.

sharable image

An image that has all of its internal references re-

solved, but which must be linked with an object module(s) to produce
an executable image. A sharable image cannot be executed. A sharable image file can be used to contain a library of routines. A sharable
image can be used to create a global section by the system manager.
A

slave terminal

u vvvvvvvvvvvvv

A terminal from which it is not possible to issue com-

mands to the command interpreter. A terminal assigned to application

software.

345

software context
The context maintained by the operating system
that describes a process. See software process control block (PCB).

software interrupt

An interrupt generated on interrupt priority level

1 through 15, which can be requested only by software.

software process control block (PCB)
The data structure used to
contain a process’ software context. The operating system
defines a

software PCB for every process when the process is
created. The
software PCB includes the following kinds of informati
on about the
process: current state; storage address if it is swapped

out of memory;

unique identification of the process, and address of
the process
header (which contains the hardware PCB). The software
PCB resides
in system region virtual address space. It is not swapped
with a process.

software priority

See process priority and queue priority.

spooling
Output spooling: The method by which output to a lowspeed peripheral device (such as a line printer) is placed
into queues
maintained on a high-speed device (such as disk) to await
transmission to the low-speed device. Input spooling: The method
by which
input from a low-speed peripheral (such as the card
reader) is placed
into queues maintained on a high-speed device (such as disk)
to await
transmission to a job processing that input.
spool queue

The list of files supplied by processes that are to be

processed by a symbiont. For example, a line printer

files to be printed on the line printer.

stack

queue is a list of

An area of memory set aside for temporary storage, or for

procedure and interrupt service linkages. A stack
uses the last-in,

first-out concept. As items are added to (“pushed on”) the
stack pointer decrements. As items are retrieved from

the stack, the stack pointer increments.

stack frame

stack, the

(“popped off")

A standard data structure built on the stack during a

procedure call, starting from the location addressed by

the FP to lower

addresses, and popped off during a return from procedure
. Also
called call frame.

Stack Pointer

General register 14 (R14). SP contains the address of

the top (lowest address) of the processor-defined stack.

Reference to
SP will access one of the five possible stack pointers, kernel,
execu-

tive, supervisor, user, or interrupt, depending on the value

in the cur-

rent mode and interrupt stack bits in the Processor
Status Longword

(PSL).

state queue A list of processes in a particula
r processing state. The
scheduler uses state queues to keep track of processe
s’ eligibility to

346

Glossary

execute. They include: processes waiting for a common event flag,
suspended processes, and executable processes.

status code

A longword value that indicates the success or failure of

a specific function. For exampie, system services always return a status code in RO upon completion.

store through

See write through.

supervisor mode The third most privileged processor access mode
(mode 2). The operating system'’s command interpreter runs in super-

visor mode.

synchronous Refers to a mode of activity that operates using an
external timing mechanism. For example, synchronous data

transmission hardware uses fixed time intervals to frame characters,
where as asynchronous data transmission hardware uses start and
stop codes. If two activities are synchronous, the second cannot take
place until the first is complete.

Synchronous Backplane Interconnect (SBI) The part of the hardware that interconnects the processor, memory controllers, MASSBUS adapters, the UNIBUS adapter.

system In the context “system, owner, group, world,” the system
refers to the group numbers that are used by operating system and its
controlling users, the system operators and system manager.

system address space

See system space and system region.

System Base Register (SBR) A processor register containing the

physical address of the base of the system page table.
System Control Block (SCB) The data structure in system space

that contains all the interrupt and exception vectors known to the
system.

System Control Block Base register (SCBB) A processor register
containing the base address of the system control block.

system device The random access mass storage device unit on
which the volume containing the operating system software resides.
System Identification Register A processor register which contains
the processor type and serial number.

system image The image that is read into memory from secondary

storage when the system is started up.

‘System Length Register (SLR) A processor register containing the
length of the system page table in longwords, that is, the number of
page table entries in the system region page table.
347

Giossary

System Page Tabie (SPT)

The data structure that maps the system
region virtual addresses, including the addresses used
to refer to the
process page tables. The system page table

(SPT) contains one page

table entry (PTE) for each page of system region

virtual memory. The
physical base address of the SPT is contain
ed in a register called the

SBR.

system queue

A queue used and maintained by operat
ing system
procedures. See also state queue.

system region
The third quarter of virtual address
space. The lowest-addressed half of system space.
Virtual addresses in the system
region are sharable between processes.
Some of the data structures
mapped by system region virtual addres
ses are: system entry vectors,

the system control block (SCB), the system
page table (SPT), and
process page tables.

system space

The highest-addressed half of virtual address space.