VAX 11/780 Hardware Handbook

This document, the "VAX-11/780 Hardware Handbook" from 1979, provides a comprehensive overview of the VAX-11/780 computer system's hardware components, architecture, and functional operation.

Key Components & Architecture:

• Central Processing Unit (CPU): A high-performance, microprogrammed 32-bit processor. It features a 4-gigabyte virtual address space, a rich instruction set (243 instructions, including integral decimal, character string, and floating-point), an 8KB cache, an address translation buffer, and 16 general registers. An optional Floating Point Accelerator (FPA) is available.
• Synchronous Backplane Interconnect (SBI): This 32-bit, high-speed bus (13.3 MB/sec throughput) acts as the central communication path, linking the CPU, main memory, and I/O subsystems. It employs distributed arbitration and extensive parity checking for high data integrity.
• Main Memory Subsystem: Comprises ECC (Error Checking and Correcting) MOS memory, configurable up to 8 million bytes. It supports single-bit error correction and double-bit error detection, with memory controllers managing transactions and supporting interleaving for performance.
• Console Subsystem: An intelligent, LSI-11 microcomputer-based system with a floppy disk and terminal. It functions as the system console for operational control (bootstrapping, initialization), a diagnostic console for error detection and maintenance, and a VAX operating system terminal.
• Input/Output (I/O) Subsystems:
  • UNIBUS: Connects general-purpose and user-developed peripheral devices. A UNIBUS adapter translates addresses between UNIBUS and SBI, facilitating data transfers (Direct Data Path and Buffered Data Paths for high-speed DMA) and interrupt handling.
  • MASSBUS: Designed for high-performance mass storage devices (e.g., RP series disks). MASSBUS adapters manage data transfers and address mapping between these devices and the SBI.

Core System Concepts & Features:

• Virtual Memory Management: A fundamental aspect, providing a large virtual address space and enabling programs to run independently of physical memory constraints. It incorporates page-oriented memory management, virtual-to-physical address translation, and hierarchical access modes (kernel, executive, supervisor, user) for robust protection and controlled data sharing.
• Process Structure: Defines how the system manages execution, including detailed mechanisms for context switching (saving and loading process states) and Asynchronous System Traps (ASTs) for event notification.
• Exceptions and Interrupts: Differentiates between synchronous (exceptions) and asynchronous (interrupts) events, explaining how the processor handles them based on priority levels and the System Control Block (SCB).
• Reliability, Availability, Maintainability (RAMP): The VAX-11/780 incorporates numerous RAMP features, such as ECC, on-line diagnostics, error logging, hardware consistency checks, and a watchdog timer, all aimed at minimizing downtime and facilitating rapid repairs.

The document serves as a detailed guide to the VAX-11/780's hardware, illustrating how its components and architectural design contribute to its high performance, reliability, and versatility in a multiuser, multiprogramming environment.