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AA-H307B-TE

February 1979

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Document:	VAX 11/780 Data Path Description
Order Number:	AA-H307B-TE
Revision:	000
Pages:	335
Original Filename:

OCR Text

VAX 11/780
DATA PATH DESCRIPTION
AA-H307B-TE

February 1979

Diqital Euipment Corporation - Maynard, Ma

Page 2

First Printing, February 1979
The information in this document is subject to change without notice
and should not be construed as a commitment by Digital Equipment
Corporation. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.
The software described in this document is furnished under a license
and may be used or copied only in accordance with the terms of such
license.
No responsibility is assumed for the use or reliability of software or
that is not supplied by DIGITAL or its affiliated companies.

eq~ipment

Copyright (C) 1979 by Digital Equipment Corporation
The postage prepaid READER'S COMMENTS fo~~ on the last page of this
document requests the user's critical evaluation to assist us in
preparing future documentation.
The following are trademarks of Digital Equipment Corporation:
DIGITAL
DEC
PDP
DEC US
UNIBUS
COMPUTER LABS
COMTEX
DDT
DECCOMM
ASSIST-11
TMS-11

D.ECsystem-10
DECtape
DIBOL
EDUSYSTEM
FLIP CHIP
FOCAL
INDAC
LAB-8
DECsystem-20
RTS-8

.MASSBUS
OMNIBUS
OS/8
PHA
RSTS
RSX
TYPESET-8
TYPESET-10
TYPESET-11
ITPS-10

Page 3

CHAPTER 1

DATA PATH SPECIFICATION

ARITHMETIC SECTION
1.1
ALU
1.1.1
•
AMX
1.1. 2
•
BMX
1.1. 3
SHF
1.1. 4
KMX
1.1. 5
MASK
1.1.6
LC and RC
1.1. 7
LA and LB
1.1.8
RLOG and PCSV
1.1.9
1.2
EXPONENT SECTION
EALU
1. 2.1
EAMX
1.2.2
•
•
•
EBMX
1. 2. 3
•
1.2.4
FE
STATE
1. 2. 5
•
1.2.6
SMX
•
SC
1. 2. 7
DATA SECTION
1.3
DFMX
1. 3.1
1.3.1.1
BUS DFMX
QMX
1. 3. 2
•
DMX
1. 3. 3
•
1. 3. 4
DAL
1. 3. 5
Q
1.3.6
D
•
MDBAL
1.3.6.1
•
1. 3. 7
D PGEN
•
1.3.8
BAL
RAMX
1. 3. 9
•
1.3.9.1
RBMX
ADDRESS SECTION
1. 4
1.4.1
VIBA
• •
VA
1. 4. 2
•
•
VAMUX
1. 4. 3
1. 4. 4
PC
•
1.4.5
PC ADD
•
PCMX
1. 4. 6
•
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6

2.7
2.8
2.9

•

1-3
1-3
1-5
1-7
1-11
1-14
1-18
1-18
1-19
1-25
1-26
1-26
1-27
1-28
1-29
1-30
1-31
1-32
1-33
1-33
1-34
1-35
1-36
1-37
1-38
1-41
1-44
1-46
1-46
1-50
1-50
1-51
1-51
1-52
1-53
1-54
1-55
1-56

MICRO SEQUENCER SPECIFICATION
NORMAL MODE
MICRO ECO CONTROL (UECO) MODE
•
MICRO TRAP (UTRAP) MODE
CONTROL STORE PARITY ERROR MICRO TRAP MODE
CACHE STALLS
SYSTEM INITIALIZE
MICRO SUBROUTINE FIELD (USUB)
JUMP FIELD (JFIELD OR UJMP)
BRANCH ENABLE FIELD (UBEN)

2-1
2-1
2-3
2-4
2-6
2-7
2-8
2-8
2-8

Page 4
2.10
2.11
2.12
2.13
2.14
2.15
2.16
CHAPTER 3

. . . 2-9
. . . . . .. .. . . .. .. .. . . . . 2-9
.. .. .. .. . . . . . . . . . . . 2-9
2-10
. . . . .. . . . .. 2-11
2-13
.........
.• . 2-14

OTHER FIELDS - UBS+UBCT (NOT ON USC)
CALL SUBROUTINE
RETURN SUBROUTINE
POWER UP OR DOWN
CONSOLE CONTROLLED OPERATIONS
PICO SEQUENCER AND PRIORITY DECODING
UPC ADDRESS LATCHING
INTERNAL DATA BUS SPECIFICATION

. . . . 3-1
. .. ... . .. ... . .. .. .. .. .. 3-2
3-1
3-3
. .. .. .. .. ... ... ... . . ... ... 3-3
3-3
. . . .. .. .
. . . . . 3-3
. . .. . .. .. 3-5
3-4
.
3-5
.. .. .. .. .. . .. ... ... ... ... .. ... ... 3-5
3-5
. . . 3-5
.....
. . .. .. .. .. .. . . .. .. .. . .. 3-6
3-6
3-6
. . . . . . .. .. .. . . . . 3-6
3-7
.. .. .. .. . . .. .. .. .. .. 3-7
.
.
3-7
. . . . .. . . .. .. . .. .. ..
.. .. 3-8
. . . . . . . . . .. .. .. . . .. .. 3-8
3-8
.
3-8
......
.. .. .. . . .. .. 3-9
.........
. . . . .. . .. .. . . .. .. .. . . .. . 3-9
3-9
.... .
.
. . . . . . . 3-10
....
. .. . . .. . .. .. .. . . .. .. 3-10
3-10
.. .. .. . . .. .. 3-11
. .. . .
3-11
31.....11
.
..
....
3-12
..........
. .. .. . . .. .• ' 3-12
........
.
3-12
.
.. .. .. .. .. .. . . .. .. 3-13
.. .. .. .. .. .. . . .. . .. .. .. . . . .. . . 3-13
3-13
3-14
. . ... .. ... . . . . .. .. ... . . .. .. 3-15
3-16
. . . . . 3-16-

3.1
FUNCTIONAL OPERATIC~
•
Normal Operation
3.1.1
• •
3.1.1.l
ID BUS Addresses
•
3.1.1.2
ID BUS Directional Control
3.1.1.3
ID BUS Data
• •
•
Signal Summary
3.1.1.4
• •
3.1.1.5
ID BUS Control
.
Maintenance Operation • •
3.1.2
• • •
•
Console Control of ID BUS
3.1.2.1
3.2
ID BUS REGISTER DESCRIPTION
•
3.2.1
IBUF DATA
3.2.2
SYSTEM ID
3.2.3
CNSL RXCS
3.2.4
CNSL RXDB
•
3.2.5
CNSL TXCS
3.2.6
CNSL TXDB
3.2.7
CLOCK CONTROL/STATUS
3.2.8
NEXT INTERVAL COUNT
3.2.9
INTERVAL COUNT
3.2.10
TIME OF DAY
3.2.11
ACC REG 0 THRU 1
•
3.2.12
ACC MAINT
3.2.13
ACC CONTROL/STATUS
3.2.14
TBUF DATA
3.2.15
TBUF REG 0
3.2.16
TBUF REGl
3.2.17
SBI SILO
3.2.18
SB! TIMEOUT ADDRESS
3.2.19
SBI FAULT/STATUS
3.2.20
SBI SILO COMPARATOR
3.2.21
SBI MAINTENANCE
3.2.22
SBI CACHE PARITY
3.2.23
US TACK
3.2.24
UBREAI<
3.2.25
wcs ADDRESS
3.2.26
wcs DATA/STATUS
3.2.27
D,Q (MAINT MODE ONLY)
3.2.28
SIR
3.2.29
.
PSL
•
•
3.2.30
CPU ERROR/STATUS
3.2.31
VECTOR
•
•
3.2.32
FPDA, D.SV, Q.SV
3.2.33
POBR, PlBR, SBR, POLR, Pl LR, SLR, PCBB,
SCBB KSP, ESP, SSP, USP, ISP

Page 5
CHAPTER 4

INSTRUCTION BUFFER

4.1

BUFFER DATA PATH • • • • • • • • • • • • • • • 4-1
Buffer Register • • • • • • • • • • • • • • • 4-1
4 .1.1
SHIFT
NETWORK • • • • • • • • • • • • • • • • • 4·-2
4.2
Multi
pl ex er Shi ft Network • • • • • • • • • • 4 ·-2
4.2.1
MICRO Control use • • • • • • • • •
• • 4-3
4.2.1.l
INPUT MULTIPLEXER • •
• • • • • • • • • • • 4-4
4.3
BYTE ROTATOR
• • • • • • • • • • • • • • • 4·-4
4.4
I-STREAM DATA MUX • • • • • • • • • • • • • • • 4-5
4.5
PC UPDATES • • • • • • • • • • •
• • • .• • 4-6
4.6
4.7
IR DECODE • • • • • • • • • • • • • • • • • • • 4-7
Register Latched Number • •
• • •
• • 4-8
4.7.1
Context Lookup • • • • • • • • • • • • • 4-8
4.7.1.1
Specifier 1 Constant
• • • • • 4-8
4.7.1.1.1
Specifier 2 Constant
• • • • • 4-9
4.7.1.1.2
Data Length Field • • • • • • • • • • • • 4-9
4.7.1.2
4.8
EXECUTION POINTS • • • • • • • • • • • • • • • 4-9
4.9
FIRST PART DONE • • • •
• • • • • • • • • • 4-10
4.9.1
IB Addressing • • • • • •
• • • • • • • • 4-10
4.10
CACHE INTERFACE • • •
• • • • • •
• 4-11
ACCELERATOR INTERFACE • • • • • • • • • • • • • -4-11
4.11
CHAPTER 5
5.1
5 .1.1

INTERRUPTS & EXCEPTIONS

INTERRUPTS • • • • • • • • • • • • • •
• • 5-1
Interrupt Priority Level (IPL)
• • • • • • • 5-1
System Control Block • • • • • • • • • • • • 5-2
5.1.2
5 .1. 3
Vectors • • • • • • • • • • • • • • •
5-2
Interrupt Requests and their Vectors • • • • 5-3
5.1. 4
Description of Interrupt Conditions • • • • • 5-5
5 .1. 5
5.1.5.1
CPU Power Fail • • • • • • • • •
• • 5-5
5.1.5.2
CPU Timeout • • • • • • • • •
• • 5-5
5.1.5.3
SBI Fault • • • •
• • •
• • • • • 5-5
5.1.5.4
SBI Alert • • • • •
• • • • •
• • 5-6
5.1.5.5
CRD/RDS • • • • • • • • • • • •
• • 5-6
5.1.5.6
SB! SILO Compare
• • • • • • 5-6
Interval Timer • • •
• •
• • 5-6
5.1.5.7
External Device Interrupts • • • • • • • 5-7
5.1.5.8
Console Terminal Interrupts •
• • 5-7
5.1.5.9
Software Interrupts • • • • • • • • • • • 5-7
5.1.5.10
UWORD Control for Interrupts
• •
5-8
5.1. 6
Interrupt Strobe • • • •
• • 5-8
5.1.6.1
5.1.6.2
Interrupt Acknowledge • • • • • •
• • 5-8
5 .1. 7
Registers used for interrupt servicing
• 5-9
Interrupt priority level register - IPLR 5-9
5.1.7.1
5.1.7.2
System control block base register - SCBB 5-9
Vector
register, VECTOR • • • • • • • • • • 5-10
5.1.7.3
5.1.7.4
Asynchronous system trap level reg. ASTR 5-11
Software interrupt summary register SISR 5-11
5.1.7.5
5.1.7.6
Software interrupt request register SIRR 5-12

Page 6
EXCEPTIONS • • • • • •
• • • • 5-12
5.2
Classes of exceptions • • • • • •
• •
5-13
5.2.1
5.2.1.1
Traps • • • • • • •
• • • • • • • • • • 5-13
5.2.1.2
Faults • • • • • • • • • • • •
• • 5-13
5.2.1.3
Aborts • • • • • •
• • • • • •
• • 5-13
Exception conditions and their vectors • • • 5-13
5.2.2
Description of exception conditions • • • • • 5-14
5.2.3
Machine check - Raises IPL to lF • • • • 5-14
5.2.3.
5.2.3.1.1
Read timeout • • • • • • • • • • •
5-14
5.2.3.1.2
Read data substitute • • • • • • •
5-15
Translation buffer parity error • ~ • 5-15
5.2.3.1.3
Cache parity error • • • • • • •
• 5-15
5.2.3.1.4
Control
store
parity
error
•
•
•
•
•
•
5-15
5.2.3.1.5
Illegal Machine Sequence Error • •
5-15
5.2.3.1.6
Kernel stack not valid - Raises IPL to lF 5-16
5.2.3.2
Reserved DEC opcodes & priv. instr • • • 5-16
5.2.3.3
Reserved cust opcodes • • • • • • • • • • 5-16
5.2.3.4
Reserved operands • • • • • • • • • • • • 5-16
5.2.3.5
Illegal floating number - Fault • • • 5-16
5.2.3.5.1
Bit field too wide - Fault • •
• • 5-16
5.2.3.5.2
Illegal entry mask - Fault • • • •
5-17
5.2.3.5.3
5.2.3.5.4
PSW MBZ FIELD not zero - Fault..
5-17
5.2.3.5.5
Illegal PCB entry - Abort
•• 5-17
5.2.3.5.6
Illegal PSL image - Fault • • • • • • 5-17
Illegal processor reg - Fault • • • • 5-17
5.2.3.5.7
5.2.3.5.8
Decimal string too long - Fault • ~ • 5-18
Reserved pattern operator - Fault
5-18
5.2.3.5.9
5.2.3.6
Reserved addressing modes - Fault • • • • 5-18
Access control violation - Fault
•• 5-18
5.2.3.7
5.2.3.8
Translation not valid - Fault • •
5-19
Trace trap - TRAP • • • • • • • •
• • 5-20
5.2.3.9
5.2.3.10
BPT opcode - FAULT • • • • • • •
• • 5-20
Compatability mode trap - TRAP/ABORT
5-20
5.2.3.11
5.2.3.12
Ar i t hm et i c trap - TRAP • • •
• • 5- 2 1
CHMX opcodes • • • • • •
• • • • • • 5-22
5.2.3.13
5.2.4
Acknowledging exceptions
• • • • 5-23
Error acknowledging • • •
• • •
. 5-23
5.2.4.1
Arithmetic trap ac kn owl edging • • •
• 5-2 3
5.2.4.2
Trace trap acknowledging
• • • • • • 5-23
5.2.4.3
5.2.4.4
UWORD control for exceptions • • • • • • 5-24
5.3
MACHINE HALTS • • • • • • • • •
• • • • • • 5-24
5.3.1
Halt conditions • • •
• • • • • • 5-24
Halt Instruction
• • •
• 5-24
5.3.1.1
CNSL halt • • • • • • • .
• • •
. 5-24
5.3.1.2
CHMX instructions • • • •
• • • • •• 5-25
5.3.1.3
Interrupt stack not valid • • • • •
• 5-25
5.3.1.4
Halt
code
from
vector
•
•
•
•
5-25
5.3.1.5
5.4
UTRAP FUNCTION • • • • • •
• • •
. 5-25
UTRAP Conditons And Their Vectors •
• •• 5-25
5.4.1

Page 7
Description of utrap conditions • • • • • • • 5-26
5.4.2
5.4.2.1
System Init • • • • • • • • • • • • • • • 5-26
5.4.2.2
Errors
• • • • • • • • • • • • • • • • • • 5-26
5.4.2.3
Reserved Floating Operand • • • • • • • • 5-26
5.4.2.4
TBUF Miss • • • • • • • • • • • •
• • 5-26
5.4.2.5
Protection Violation • • • • • •
• • 5-26
5.4.2.6
MBIT • • • • • • •
• • • • • • • • 5-26
5.4.2.7
Page Boundary • • • • • • • • • • • •
5-26
Unaligned Data
• • •
• • • • • •
5-26
5.4.2.8
5.5
SERIALIZATION OF EVENTS AT FORK A •
• • • • 5-27
CHAPTER 6

6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
CHAPTER 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7 .10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19

MACHINE CHECK ABORT/FAULT/HALT
6-1
. . . . . .• .• .• .• .• .• .• . • 6-2
6-3
. .. .. .. .• .• .. .. .. •• 6-3
. . • 6-3

MACHINE CHECKS
INSTRUCTION ABORTS • • • • •
INSTRUCTION FAULTS
INSTRUCTION HALTS • • • •
ERROR LOGOUT • • • •
INITIALIZATION OF CP, TBUF,
SBI STATUS REGISTERS • •
CPU/CONSOLE INTERFACE STATE •
HALT IDENTIFICATION CODES • •
RETRYABLE INSTRUCTION LIST •

CACHE, &
• • • • •
• • • • •
• • • • •
• • • • •

•
•
•
•

•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•

6-6
6-6
6-7
6-8

CACHE-SBI-TB SUBSYSTEM
MD BUS • •
• • • • • •
CS BUS
• • • • • • • •
V BUS •
• • •
• •
CLOCK BUS •
• • •
•
ADDRESS BUS •
• • • • •
FROM IB • • • • • • • • •
TO IB • • • • • • •
• •
FROM MICROSEQUENCE. • • • •
TO MICROSEQUENCER • •
FROM TRAPS AND INTERRUPTS •
TO TRAPS AND INTERRUPTS • •
FROM DATA PATH - NONE • • •
TO DATA PATH • • • • • • •
SELECTED INTERNAL SUBSYSTEM
MICROBRANCHES • • • • • • •
MICROORDERS • • • • • • •
REGISTERS • • • • • • • •
GENERAL DESCRIPTION • • •
MICROCODING SUGGESTIONS •

•
•

•
• • •
•
•
•
• • • • • •
• • • • •
• • • • • •
• • • • •
• • • • •
• • • • • •
• • • • • •
• • • • • •
• • • • •
SIGNALS • •
• • • • • •
• • • • •
• • •
• • • • •
• • • • •

•
•
•
•
•

7-1
7-1
7-2
7-2
7-2
7-2
7-3
7-3
7-3
• 7-4
• 7-4
• 7-6
• 7-6
7-6
• 7-6
• 7-7
7-11
• 7-30
• 7-31

• •
• •
• •
• •
• •
• •
••
•
•
•
•

•
• • •
• • •
• • •

Page 8
CHAPTER 8
8.1
8.2

8.3
8.4
8.5

CHAPTER 9

VAX 11/780 CONSOLE SUBSYSTEM
THE CONSOLE/CPU INTERFACE • • • • • • • • • • • 8-3
ID BUS REGISTERS ON CIB • • • • • • •
• 8-6
THE Q-BUS REGISTERS (FIGURES 4 AND 5)
• 8-8
USE OF- THE Q-BUS REGISTERS •
• •
• 8-20
TERMINAL CONTROL REGISTERS IN THE PROCREG SPACE 8-26
VAX 11/780 ACCELERATOR INTERFACE

9.1
DEFINITIONS . • • • • • • • • • • • • • •
9.2
INTERFACE SPECIFICATION • • • • •
9.3
GLOSSARY OF INTERFACE SIGNALS • • • •
9.4
ACCELERATOR INTERFACE OPERATION • • • •
9.4.l
Data transfer • • • •• .' •
• •
Initial data transfer • • • • •
9.4.l.l
9.4.2
Accelerator control • • • • • • • • •
Accelerator trap • • • • •
9.4.2.l
Alternate trap function ••
9.4.2.2
9.4.2.3
CPU branches
• • • • • • •
9.4.3
System clock • • • • • • • • •
9.5
DATA INTERFACE • • • • • • •
• • •
9.5.l
Data to accelerator • • • • • • • • •
Data from accelerator • • • • •
9.5.l.l
9.5.2
Alternate data transfers • • • • •
9.5.3
Accelerator status registers • • • •
9.5.3.l
Accelerator maintenance register
9.5.4
General register updates • • • • • •
9.6
ISB INTERFACE • • • • • • • • • • • • •

• • • • 9-2
• • • 9-2
• • • 9-2
•
• 9-6
• • • 9-6
• • • 9-6
• • • • 9-7
• • • 9-7
• 9-7
• 9-7
• 9-8
• • • • 9-8
• •• • 9-8
• 9-8
• 9-9
• • • • 9-9
• • • • 9-9
• • • • 9-9
• • • • 9-10

APPENDIX A
A. l
A. 2

APPENDIX B

B.l
B.2
B.3
B.4

CONTROL WORD
THE CONTROL WORD
ABORT CONDITION •

...........

• A-1
• A-5

WRITABLE CONTROL STORE
WRITEABLE CONTROL STORE MEMORY • • • • • • • • B-1
WRITE DATA TO WCS • • • • • • .• • • • • • • • • B-1
WCS ADDRESS REGISTER • • • • • • • • • • • • • B-2
EXTERNAL JUMPER SELECTIONS & RAM TYPE SELECTION B-2

Page 9

APPENDIX C
C.l
C.2
C.3
C.4

c.s

MICRO-CODE DEBUGGER INTERFACE
OBJECTIVES • • • • • • • • • • • • • • • • • • C-1
MICRO-CODE DEBUGGER ENTRY & EXIT • • • • • • • C-1
MICRO-CODE DEBUGGER/MICRO-MACHINE/STATE CONTROL C-2
MICRO-CODE DEBUGGER INTERNAL REGISTER &
MEMORY EXAMINE & DEPOSIT • • • • • • • • • • • C-4
LIST OF DEPENDENT MICRO-ORDERS • • • •
• • C-5

APPENDIX D

WCS DEBUGGER HELP FILE

APPENDIX E

PROM CONTROL STORE SPECIFICATION

E.l
E.2
E.3

PROM ADDRESS PATH • • • • • • • • • • • • • • • E-1
PARITY ERROR DETECTION • • • • • • • • • • • • E-1
EXTERNAL JUMPER SELECTIONS & CS TYPE SELECTION E-2

CHAPTER 1
DATA PATH SPECIFICATION

The VAX 11/780 CPU DATA PATH consists of four sections for processing
data and addresses as specified in the VAX and compatibility mode
instruction sets.
The EXPONENT, ADDRESS, ARITHMETIC, and
DATA
sections each operate as independent units which are capable of
processing data or addresses in parallel with the operations taking
place in the other sections.
The block diagram for the VAX 11/780 CPU Data Path is given in
1-1.

Figure

DATA PATM

NOTES:

EXPONENf SECTION

AODR£~S

VA-

r- ____

Il-

r-------,

J ______. ,

tO~'ioOLf

'
I

l. - - - - - - - J

: - -T~~F- ;.:.; ~;;..; - - -:

(

I
I

'
I

%911

PC CTO 8"Wl

UUf'

"Eli l),.TA)

•u
•

TO AND vaoM ACC:

T.S.

c r.s..

'--------~

DECIMAL
C.OM\TAl'IT

NlBS~ I

wcr.

a:
<
.....
c

I
t

:.::

L--- - - - -- ~

,1 8J:T
SM%FT l"lAT9'lJ

•

I
I
I

'SWAP

OAL!-

.....

r- -- - -- --,

:::>

CtNTUUtAL OATA)

MA51C
74Sll•

<~E'-11. .. AL

Cal

'
I

......

DATA $ECTION

·1

IS$••

,--

tJ
0

..J
al

-------,
ACC

I
I

1-1

"------- ---~

• ........

e-..

<
u

....

ABMIC

:o. f"LU EXP.DREG
PC _ ___.

8. 1, c1 :ti. 4

SPICON
SPIC.OW
SC.

,
PC.SV
74Sl"'t~

•

.- . ------ -,

..,

1
I

t&Jl9

.. a

-,.-c-

-A.-

14all "!Z
"14-S'I

161132
"14S'8

RL019
"14~66

ADD/SU~

~--------

•I
I
I

"A ADOA£SS,

....... <•"3:t11•>.

o.c.
I

0.
Ul

:c
i""

<
a.

L--------'

II:(

91T

E!....OCK DIAGRAM

1--SCAL-,-~-----

Sllf

lllUMlfll

o :~s Ms22s-o - 1

l)OST

C&l

I PROCESSOlll
RlGtsT ERS

....

I
I

i'St

1 I ..TlRMAL

r.s..

1141<.RO
1
SEQUUIC(fl I

.---------,

L.A
-r(..i&X""S'l
74S&8

&~O

,--------,

SHr VAL

•c._-.

N
.-4

""·

SBI CNT'-

...

(._..]_ _ _ _
sa1_ _ ~

SECT'IOH

DATA PATH SPECIFICATION
1.1

Page 1-3

ARITHMETIC SECTION

The ARITHMETIC SECTION of the DATA PATH contains the
GENERAL
REGISTERS, a bit mask generator, a constant generator, shifter,
temporary storage registers, and register inputs from the ADDRESS and
DATA SECTIONS so that the necessary arithmetic and logical operations
can be performed on data and addresses.
Three data types are processed in the ARITHMETIC SECTION which consist
of 8 bit bytes, 16 bit words, and 32 bit long words.
The data type is controlled by the UDT control field which selects the
desired sign or zero extension, index constants, index shifting, and
GENERAL REGISTER storage control.

1.1.1

ALU

Arithmetic and Logic Unit
The ALU provides the main processing power of the ARITHMETIC SECTION
by performing 32 bit arithmetic with fast carry look ahead logic or 32
bit logical operations.
ALU data types:
32 bit arithmetic or logical operation (.OP.).
00

+----------------------------------------------------------------+
I
I
I

A(31:00)

.OP.

8(31:00)

I
I
I

ALU CONTROL
The ALU operation is controlled by the UALU field of the UWORD which
may define the function explicitly or allow the function to be
controlled by the instruction decode logic.
The command codes are
grouped into two classes, arithmetic and logic modes. The arithmetic
mode operation requires more processing time and puts restrictions on
the source data used in the case of slow constants (section 1.3.5),
register set contents (section 1.3.7), Temporary scratch pad contents
{section 1.3.8), packed floating format (section 1.3.3) or the
conditional BMX selection of PC in the state immediately following the
loading of the first specifier (section 1.3.3). There are no similar
restricitons on logic mode functions.

DATA PATH SPECIFICATION

Page 1-4

UALU
Uword Arithmetic and Logic Unit control field, 4 bits.
Uword hex code
(D)

0
1
2
3
4
5

7
8
9

A
B

D
E

Function

Mode

A.MINUS. B
A.MINUS. B (RLOG)
A.MINUS.B.MINUS.l
INSTRUCTION DEP.
A.PLUS.B.PLUS.l
A.PLUS.B
A. PL US • B • ( RLOG )
A.ORNOT.B
A.OR.B
A.XOR.B
A.ANDNOT.B
A.AND.B
.NOT.A
A.PLUS.B.PLUS.C
A.OR.B
A.AND.B
B
A

A
A
A
A&L
A
A
A
L
L
L
L
A
L

L
L
L

(D)
When the UALU field = 3 the ALU functions are the result of the
instruction being executed. Under Instruction Dependent mode the full
32 logical and arithmetic functions of the ALU (74Sl81) are available.

DATA PATH SPECIFICATION

Page 1-5

(D)

The C input to the ALU can be forced for either PSL
This will provide the useful ALU functions of:
A.PLUS.B.PLUS.C

A.PLUS.B.PLUS.NOT.C

A.MINUS.B.MINUS.C

A.MINUS.B.MINUS.NOT.C

A.PLUS.C

NOT

can

forced

PSLC.

A.PLUS.NOT.C

A.MINUS.C

A.MINUS.NOT.C

A.PLUS.A.PLUS.C

A.PLUS.A.PLUS.NOT.C

Independent of the ALU function selected, the AMX
zero giving:
B+l etc.

When UALU field = 1 or 6 the RLOG stack is updated with the general
register
(RA)
address,
the lower four bits of the KMX and a bit to
determine if an add or subtract is requested.

1.1. 2

AMX

alu A input Multiplexor
The AMX provides the data source for the A input to the ALU.
Sign or
zero extension of the data type from either the D or Q register in the
DATA SECTION is provided since the ALU operates on 32 bit data
structures only.
AMX data types:
LA

LA(31:00)

RAMX or SXT[L]

RAMX(31:00)

DATA PATH SPECIFICATION

Page 1-6

SXT[B]

00
RAMX(07:00)

RAMX07

SXT[W]
16

00
RAMX(l5:00)

RAMX 15

OXT[B]

08 07

-----------------------------------------------------------2-----1
I
I
I 0<------------------------------------)0 I

RAMX(07:00)

OXT[W]

0<--------------------------)0

00
RAMX(l5:00)

0
31

0<-------------------------------------------------~-------->0

DATA PATH SPECIFICATION

Page 1-7

AMX CONTROL
The data format of the RMX is selected by the UAMX field of the UWORD,
while the sign or zero extension position is chosen by the UDT field.
The zero extension of a long word data type is a special case and will
force all zeroes at the output of AMX.
UAMX
Uword alu A input Multiplexor control field, 2 bits.
LA
1
RAMX
(Sign eXTension)
2
RAMX SXT [UDT]
(.
eXTension)
3
RAMX OXT [UDT]
UDT
Uword Data Type select field, 2 bits.
0
1
2
3

LONGWORD
SXT[L] or 0
WORD
SXT[W] or OXT[W]
BYTE
SXT[B] or OXT[B]
INSTRUCTION DEPENDENT
Any of above

When UDT = 3 the instruction decode logic determines the data type to
be
used
in the ARITHMETIC SECTION.
This provides data type
information for
instruction
execution
and
operand
specifier
evaluation.
For instructions requesting Float Quad or Double Float
context will be a LONGWORD data type.

1.1.3

BMX

alu B input Multiplexor
The BMX provides the data source for the B input to the ALU.
The
GENERAL REGISTERS and the D register are routed to the ALU B input so
the instruction executions requiring the A.MINUS.B function can be
performed without swapping the operand from one ALU input to the
other.
The PC input is provided to route the address information in the
ADDRESS SECTION back into the ARITHMETIC SECTION. This also allows PC
displacement addressing modes to be calculated with the AMX selecting
the sign extended displacement value.

DATA PATH SPECIFICATION

Page 1-8

(D}

The PC or LB input is conditionally selected where source mode
R.EQL.PC selects the PC otherwise LB input is chosen. The BMX uword
field must be set to 1.
(D)

The RLOG, PCSV input is selected by providing
RLog and setting the BMX uword.= O.

the

signal

UMSC

Read

(D)

The packed floating format puts back together the fraction (D), the
exponent (EALU), and the sign (SD) of the result of the Data path
floating point operations into VAX floating point data format.
The LC input allows temporary storage locations to be routed into
ALU for ARITHMETIC SECTION operations.

the

The KMX input supplies the constants necessary in
instructions and evaluation of operand specifiers.

execution

The MASK input routes the output of the bit MASK generator to the
for logical operations. BMX data types:

ALU

the

{D)

RBMX

{D)

D(23:08)

I
I
I SD I
I
I

14
EALU(07:00)

D(30:24)

I
I

DATA PATH SPECIFICATION

Page 1-9

00
LB(31:00)

00
LC(31:00)

31
PC(31:00)

(D)
31

O<-------------------------->I

RLoG(OS:OO)

PCSV(07:00)

I
31

O<--------------------------->O

KMX(l5:00)

31
MASK(31:00)

DATA PATH SPECIFICATION

Page 1-10

BMX CONTROL
The BMX input is selected by the UBMX field of the UWORD.
UBMX
Uword alu B input Multiplexor control field, 3 bits.
0
1
2
3
4
5
6
7

MASK
COND
Packed Floating
LB
LC
PC
KMX
RBMX

{D)

When UBMX = 2, a packed floating
point data type is assembled by
taking
the fraction position from the DREG, the sign from control
logic, and the exponent from the EALU.
Due to the routing delays
involved both the EALU and the ALU must be selected for logic mode to
insure that data is available in the ARITHMETIC SECTION. The SD bit
contains the sign of the destination fraction in floating point
operations. SD had been loaded and controlled by the USGN field of
the
UWORD
during
execution
of
floating
point instructions.
Conditional selection of PC and LB is provided when UBMX=l.
The
selection of Rlog must be made with UBMX=O and the presents of the
signal UMSC Read Rlog.
USGN
Uword SiGN control field, 3 bits.
(D)

NOP

SS<--ALU15
SD<--SD

SS <--SD
SD<--SD

SS<--SS
SD<--SD

SS<--SS
SD<--SS

SS<--ALU15.XOR.SS
SD<--ALU15

Page 1-11

DATA PATH SPECIFICATION
6.

SS<--.NOT.ALU15.XOR.SS
IF IR[l] ELSE, SS<--ALU15.XOR.SS
SD<--ALU15

SS<--0
SD<--0

When UMSC = Read Log the RLOG stack and PCSV data is supplied to the B
input of the ALU. This selection causes a pointer .into the RLOG stack
to be decremented at the end of the Micro-instruction allowing the
next
element
of the RLOG stack to be read in a subsequ~nt
Micro-instruction.
The PCSV data remains constant until a new
instruction is begun.

1.1.4

SHF

SHiFter
The SHF is used as a multiplier to create the correct index values for
address caculations in INDEX mode specifier evaluations. The index
value is multiplied by the appropriate number to index tables of byte,
word, long word, or quad word data entries. For byte organized tables
the index value is multiplied by 1 (ALU directly with no· left
shift - LO), word tables the index value is multiplied by 2 (left
shift of 1 - Ll), long word tables by 4 (left shift of 2 - L2), and
quad word tables by 8 (left shift of 3 - L3).
The data type
information is either explicitly determined to be BYTE, WORD, or LONG
WORD or is determined by the instruction decode logic and is
controlled by the UDT field.
The SHF is also used in the execution of multiply and divide and
compatibility mode rotate and shift instructions. In these cases the
SHF has the capability of either a left shift by 1 (Ll) or a right
shift by 1 (Rl) or by 2 (R2) with the shift input controlled by the
US! field. SHF data types:
ALU
00

31
ALU(31:00)

DATA PATH SPECIFICATION

Page 1-12

ALU [Ll]
31

ALU(30:00)

-------~----------------------------------------------------------

I
Determined by------USI field
31

I
x
1--->I
I
I
I
I
31
30
I
I
x x
I
I
I
I

ALU [Rl]
00
ALU (31: 01)
ALU [R2]
29
ALU(31:02)

----------------------Determined by USI field
31

00
ALU(31:00)

ALU (W]

00
I

o I

ALU(30:00)

ALU [L]

L2
02

ALU(29:00)

00
00

DATA PATH SPECIFICATION

Page 1-13

ALU[Q] or ALU[L3]

ALU (28: 00)

000

SHF CONTROL
The data type of the SHF is selected by the USHF field of the UWORD.
In three of the shifted data types the shift input is determined by
the USI field. The UDT field determines which of the remaining
shifted data types is chosen.
USHF
Uword SHiFter control field, 3 bits.
(D)

1
2
3

4
5
6
7

ALU
ALU [Ll]
ALU [Rl]
ALU [UDT]
ALU[R2]
ALU [L3]
DO NOT USE
DO NOT USE

For USHF = 1, 2, or 4 the USI field determines the shift input.
For USHF = 3 or 5, the shift input is zeroes.
US!
Uword Shift Input control field, 3 bits.
(D)

1
2
3
4
5
6
7

PSL[N]
ALU31

(Do NOT use when writing RA, RB or RC)

0
0
0
Q31
0
1

For USHF = 3 the UDT field determines the shift amount.

Page 1-14

DATA PATH SPECIFICATION
UDT
Uword Data Type select field, 2 bits.
LONG WORD
WORD
BYTE
INSTRUCTION DEPENDENT

0
1
2

ALU [L]
L2
ALU[W]
Ll
ALU[B]
LO
Any of above and ALU[Q]

(D)

When UDT = 3 the instruction decode logic, SP1CON(02:00)
the data type which will control the shifting.

1.1.5

determines

KMX

Constant

(K)

Multiplexor

FK
Fast constant

(K)

multiplexor

SK
Slow constant (K) rom
The KMX is used to select a constant explicitly specified by the micro
instruction or to select an index constant dependent on the data type
and register type of the operand specifier being evaluated.
In VAX
mode
of operation, SPlCON
(Specifier 1 CONstant)
is a number
determined from the data type of the operand specifier
being
evaluated.
In 11 Compatibility mode SPlCON is a number determined
from the data type and register type of the source mode/reg. field of
the instruction.
SP2CON (Specifier 2 CONstant) in 11 Compatibility
mode is the number 1 or 2 determined from the data type and register
number of the destination mode/reg. field of the instruction, and in
Vax mode is the number O. SPlCON may be the number 1,2,4, or 8. Both
SPlCON and SP2CON are generated by the instruction decode logic.
The SC input to FK provides a path for the 10 bit data in the EXPONENT
SECTION to enter the ARITHMETIC SECTION and is also used as a constant
register in arithmetic operations.
The fast constants from FK are generally
decrement
data
and
in
the evaluation
auto-decrement addressing modes.

used to increment or
of auto-increment and

The SK rom provides the remainder of micro program constants used to
execute instructions, isolate bits or bit fields, provide exponent
biasing and select shift constants.

DATA PATH SPECIFICATION

Page 1-15

KMX data types:

I
I
l<-----------------constant-------------->I
I
I

I
I
IO<-------------------------->OI
I
I

SPlCON

I
I
IO<--------------------------->OJ SP2CON
I
I

I
I
IO<--------------------------->OI
I
I

I
.I
SC(09:00)
IO<--------------->OI
I
I
A ------------------------------------------KMX, SK, FK CONTROL
The constants are selected by the UKMX field of the UWORD.
Constants
selected from the SK ROM take additional lookup time and therefore
must only be used in the ARITHMETIC SECTION when the ALU is selected
for logic mode. This means that constants from SK must be stored in a
register before being used in arithmetic operations in the ALU.
Any
register to which a load path exists may be used (including t.e SC and
then selected from FK in the subsequent micro instruction).

DATA PATH SPECIFICATION

Page 1-16

An alternate method for using the SK would be to select a constant in
one micro instruction and then (selecting the same constant) in the
next micro instruction, use it in an arithmetic operation. Care must
be taken to insure that a micro trap cannot occur between the two
micro instructions so that the access time of the slow constant is
violated if the second micro instruction is restarted.
(D)

The only restriction in using the slow constants in the EXPONENT
SECTION is that the NABS (A.MINUS.B) function not be selected.
UKMX
Uword constant (K) Multiplexor select field, 6 bits.
00
01

#8
#1

02
03

#2
13
#4
SPlCON
SP2CON/tO
SC
(TBD)
(TBD)
(TBD}
(TBD)
(TBD}

04
05

06
07
08
09

OA
OB
OC
OD

(TBD}
{TBD)

10
11
12

(TBD)
(TBD)
(TBD}
{TBD}

(TBD}

14
15
16
17
18
19

(TBD}
(TBD}
(TBD)
(TBD)

lA
18

lC
10

lE
lF
20
21

22
23

24
25

(TBD)

(TBD}
(TBD}
(TBD)
(TBD)
(TBD}
(TBD)
(TBD}
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)

DATA PATH SPECIFICATION
26
27
28
29
2A
28
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F

(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)
(TBD)

Page 1-17

DATA PATH SPECIFICATION
1.1. 6

Page 1-18

MASK

Bit MASK generator
The MASK is used to generate a bit pattern which can be used to
isolate fields of bits thru use of the logical functions of the ALU.
This occurs in the execution of bit field instructions and in the
memory
management
process of translating virtual, to physical
addre~ses when they are not already translated in the TBUF.
MASK data type:
00

MASK(31:00)

MASK = single 0 bit in a field of ones
MASK CONTROL
The MASK generator is controlled by SC(04:00) which is used to address
a bit position in a long word of ones and insert a zero in that
position.
The procedure to generate a mask to retain all bits from bit position
P and above would involve setting AMX=O, BMX=MASK, SC=P and performing
an A.PLUS.B.PLUS.l ALU operation.
To generate a mask to retain 5 bi ts from position P the settup would
be: AMX=O,
BMX=MASK,
SC=P.PLUS.S and ALU=A.PLUS.B.PLUS.l.
The
resultant mask could then be added to the previously acquired mask to
isolate the required bit field.

1. 1. 7

LC and RC

LC - Latch C
RC - Register set C
RC is used as a temporary storage area for addresses and operands
generated during the execution of the micro program. There are 16, 32
bit temporary registers available and 1, 32 bit storage latch.
The
latch, LC, is used to hold the contents of a previously fetched
temporary register in RC for use in the ARITHMETIC SECTION.

DATA PATH SPECIFICATION

Page 1-19

Generally, the contents of RC are fetched in one micro instruction
into LC and then used by the ALU in the next micro instruction. RC
may however, be read into LC and used in the same micro instruction if
the ALU is selected for logical mode.
LC, RC data type:
31

00
LC(31:00)

LC, RC CONTROL
The loading of LC, the writing of RC,
controlled by the USPO field of the Uword.
command code control information.

1.1.8

and the RC address are
Refer to section 1.3.8 for

LA and LB

Latch A and Latch B
RA and RB
Register set A and Register set B
RA and RB combine to form a two address port storage location for the
16 processor GENERAL REGISTERS.
These registers are used in the
addressing mode evaluations and as fast memory storage by the
instruction set. The two port feature allows fast access to both the
source register from RB and the destination register from RA in the
execution of register to register mode instruction.

DATA PATH SPECIFICATION

Page 1-20

LA and LB are used to hold the contents of a general register which
had been fetched previously for use in the ARITHMETIC SECTION.
Generally the contents of RA and RB are fetched in one micro
instruction into LA and LB and then used by the ALU in the next micro
instruction. RA and RB may however, be read into LA and LB and used
in the same micro instruction if the ALU is selected for logical mode.
LA data type:
31

00
LA(31:00)

LB data type:
00

31
LB(31~00)

SCRATCH PAD CONTROL
The three register sets, RC, RB, and RA, and their associated latches,
LC,
LB and LA are controlled by a seven bit opcode field of the UWORD
designated USPO. This field controls the writing of the scratch pads,
the loading of the latches, and the address source of the register.
The address supplied to the RC register set can come from two sources.
It can be generated explicitly as a register number (RN) in the USPO
field or it may come from the SC register bits 03:00.

DATA PATH SPECIFICATION

Page 1-21

The RA and RB sets can be addressed explicitly as a register number
(RN)
in ·the USPO field or by an Address Code Number (ACN). The ACN
number selects the address for RA and RB from several register fields
of the instruction operand specifiers.
In 11 compatibility mode the
register address comes from either the register field for the source
mode/register or destination mode register codes in the instruction
opcode.
The ACN for the RA and RB sets also selects SC(03:00) as the address
source. This allows the GENERAL REGISTERS to be sequentially indexed.
The USPO field also allows individual control of RC from that of RA
and RB.
In these cases when one may be read and the other written the
contents of RC cannot be interchanged with the contents of RA, RB or
vice versa in the same micro-instruction. Those USPO codes are 60 to

7F.
(D)
RC register write operations are a.ways Longword data types.
The RA and RB register write operations are context dependent and is
controlled by the UDT uword.
In operations requiring Float, Quad or
Double Float context Longword data type will be used.
UDT
Uword Data type select field, 2 bits.
0
1
2
3

LONGWORD
32 BITS
WORD
16 BITS
BYTE
8 BITS
INSTRUCTION DEPENDENT:

Any of above

When UDT=3, The Instruction decode logic determines to be used
and RB register write operations.

DATA PATH SPECIFICATION

Page 1-22

USPO
Uword Scratch Pad Opcode, 7 bits.
NOOP
LOAD LC[SC(03:00)]
WRITE RC[SC(03:00)]
LOAD LA,LB[ACN]

00 to 05
06
07
08 to OF

05
0

10 to 17

(D) 18 to IF

ACN

WRITE RA,RB[ACN]

ACN

LOAD LC [RN]
05

06
0

30 to 3F

RN=(7:0)

LOAD LA[RN]

20 to 2F

02
1

WRITE RC[RN]

DATA PATH SPECIFICATION

40 to 4F

Page 1-23

LOAD LA,LB[RN]
04

03
0

00
RN

-----~-------------------------------

50 to SF

WRITE RA,RB[RN]

1
60 to 6F

LOAD LA, LB [Rl]
and WRITE RC[RN]

1 · I

I
70 to 7F

LOAD LC [RN]
and WRITE RA,RB[Rl]

The ACN field of USPO has two interpretations, one for VAX mode and
one for 11 compatibility mode. In VAX mod.e there are three register
fields in the instruction which are examined.
These are SPlR
(SPecifier 1 Register), SP2R (SPecifier 2 Register), and PRN (Previous
Register Number). SPlR is the register number from the operand
specifier currently being examined by the IBUF control logic. SP2R is
the register number from the byte following the operand specifier in
IBUF and PRN is the register number from the last operand specifier in
IBUF.

DATA PATH SPECIFICATION

Page 1-24

(D)

In 11 compatibility mode there are two register fields in the
instruction which are examined. These are the SRC R (SouRCe Register)
and the DST R (DeSTination Register) numbers found in the source and
destination
mode/register
fields.
The
FPA,
Floating
Point
Accelerator, will keep a copy of the RA register.
The FPA will
receive the RA address and a two bit encoded write enable field
describing the RA write operation data type.
FPA RA Write Control field
0
1
2

WORD
LONGWORD
BYTE
NO WRITE

ACN - VAX mode
Address Code Number
(D)

RA address

RB address

S~l

1
2

3
4
5
6
7

SPl R
SP2 R
SP2 R
PRN
PRN.PLUS.l
SC(03:00)
SPl R.PLUS.l
0

R
SP2 R
SPl R
PRN
PRN.PLUS.l
SC(03:00)
SPl R.PLUS.l
0

ACN - 11 compatibility mode
(D)

RA address

RB address

0
1
2
3
4
5

SRC R
DST R
SRC R
SRC R
SRCR.OR.l
$C(03:00)
SRC R.PLUS.l
0

6
7

SRC R
DST R
DST R
SRC R
SRCR.OR.l
SC(03:00)
SRC R.PLUS.l
0

DATA PATH SPECIFICATION
1.1.9

Page 1-25

RLOG and PCSV

RLOG - Register LOG stack
PCSV - Program Counter save register
The RLOG stack and PCSV register provide sufficient information to the
microcode so that the contents of the general registers may be
restored to their original values in order that an instruction may be
restarted.
If a memory management fault occurs which requires a
macro-level trap routine to be run it is necessary to back-up the
general registers that had been auto-incremented and auto-decremented
during the execution of the instruction causing the fault.
The RLOG stack keeps track of the register numbers and constant values
used to update the registers in specifier evaluations. There are 16
locations in the RLOG stack and at each instruction fetch a pointer
into the stack is initialized and an RLOG empty flag asserted. When
the micro-code fault routine reads the RLOG the pointer is decremented
and the next entry in the stack becomes available.
The PCSV register saves the lower 8 bits of the PC at the time an
instruction is fetched.
Since no instruction is longer than 256
bytes, the entire 32 bit starting PC may be reconstructed if a fault
occurs.
RLOG data type:
(D)

ADD/SUB

12 11

KMX(03:00)

RA ADDRESS BITS
(03:00)

PCSV data type:
07

00
PC(07:00)

DATA PATH SPECIFICATION

Page 1-26

RLOG CONTROL
The RLOG stack is written when the UALU field specifies an RLOG update
operation.
If the operation is A.PLUS.B (RLOG UPDATE), RLOG08 is set
to a one, otherwise it is set to zero.
Whenever the UMSC field selects the Read RLOG function, the current
value is read out of the stack and the pointer is incremented at the
end of the micro-instruction.
PCSV CONTROL
Each time an instruction is fetched, the PCSV register gets the low
bits of the PC.

1.2

EXPONENT SECTION

The EXPONENT SECTION is used to perform exponent processing in
parallel with fraction processing in the ARITHMETIC and DATA SECTIONS
of the Data Path when floating point instructions are being executed.
When processing exponents the 10 bit exponent path is interpreted as
an 8 bit exponent and a 2 bit overflow/underflow code.
The EXPONENT SECTION is also used for controlling the SC register when
it _is used to generate masks, to address RA, RB, or RC, to address
processor registers, or to be used as a shift value in the DATA
SECTION.

1. 2 .1

EALU

Exponent Arithmetic and Logic Unit
The EALU performs the processing of data in the EXPONENT SECTION.
It
consists of an ALU circuit with fast carry look ahead, a negative
absolute value look up rom and a multiplexor. The rom and multiplexor
are used in NABS (A.MINUS.B) mode to provide a shift value in floating
point arithmetic alignment.
EALU data type:
00

EXP 0(09:00)

DATA PATH SPECIFICATION

Page 1-27

EALU CONTROL
The EALU function is controlled by the UEALU -field of the UWORD and is
defined as arithmetic or logical.
The only restriction on EALU source
data is that the NABS (A.MINUS.B) function not be used when a slow
constant is being used from KMX unless the proper set-up time has been
met as described in section 1.3.5.
UEALU
Uword Exp.
(D)

A
A. OR. B

1
2
3
4
5
6
7

1. 2. 2

Arithmetic and Logic Unit control field, 3 bits.

A.AND.B
B

A.PLUS.B
A.MINUS.B
A.PLUS.I
NABS (A. MINUS. B)

EAMX

Ealu A input Multiplexor
The EAMX provides the data source for the A input to the EALU.
Whenever the STATE register is selected as the data source, the STATE
register is loaded in the same micro instruction.
EAMX data types:
09

SC(09:00)

09
0

STATE(07:00)

DATA PATH SPECIFICATION

Page 1-28

EAMX CONTROL
The EAMX input is selected by the UMSC field of the Uword.
Whenever
the UMSC field selects the LOAD STATE REG code the EAMX is switched so
that the STATE REG is fed to the input of the EALU.
At the end of
that micro instruction, the STATE register is loaded. At all other
times the SC register is selected at the EAMX.

1.2.3

EBMX

Ealu B input Multiplexor
The EBMX provides the data source for the B input to the EALU.
The
EBMX rece iv.es either the exponent from the FE register or the exponent
field from the AMX when the EXPONENT SECTION is used for exponents
processing.
Constants from the KMX or shift values from the control logic of the
DAL are used as data sources for the EBMX so that a shift count in SC
may be operated on. Constants may also be selected to set or clear
flags in STATE.
The SHF VAL is a hardware generated number of left shifts necessary to
normalize the contents of the D register. The normalized number is
obtained by shifting to the left of the most significant "l" in the D
register to the BIT 31 position. This process can be accomplished in
one machine cycle with the UDK uword = D enabling the D register to be
updated with the normalized number.
EBMX data types:
09

00
FE (09: 00)

00
KMX(09:00)

DATA PATH SPECIFICATION

Page 1-29

(D)

09
0

AMX(l4:07)

05 04

I
I
I

O<------------------->O
II
.

SHF VAL(04:00)

EBMX CONTROL
The EBMX is controlled by the UEBMX field of the UWORD.
UEBMX
Uword Ealu B input Multiplexor control field, 2 bits.
(D)
0
FE
1
KMX
2
AMX EXP
3
SHF VAL

1. 2. 4

Floating Exponent register
The FE is used to hold exponents or temporary values for processing in
the EXPONENT SECTION.
FE data type:
00

09
LOAD FE

EXP 0(09:00)

DATA PATH SPECIFICATION

Page 1-30

FE CONTROL
The loading of the FE register is controlled by the UFEK field of
UWORD.

the

UFEK
Uword Floating Exp.
0
1

1. 2. 5

control (K) field, l bit.

HOLD
LOAD

STATE

STATE register
The STATE register contains 8 flag bits which are generated by the
micro program to be used in program flow control. Each four bit group
of the STATE register is used as a 16 way branch condition in the
micro sequencer section of the CPU. By using the logical operations
of the EALU and the constants from KMX a micro instruction may set or
clear individual bits in the STATE register • .
STATE data type:
00

LOAD STATE

EXP D(07:00)

STATE CONTROL
The loading of the STATE register is controlled by selecting the
STATE REG of the UMSC field of the UWORD.

LOAD

DATA PATH SPECIFICATION
1.2.6

Page 1-31

SMX

Shift count Multiplexor
The SMX provides a data link from the ARITHMETIC SECTION into the
EXPONENT SECTION and allows either a 10 bit data field or an 8 bit
exponent to be routed to the SC register from the ALU.
The SMX also has FE as a data source so that the values in FE
can be swapped in a single micro instruction.

and

The EALU data source of the SMX allows processing of the SC register
in the EALU for incrementing or decrementing values in the SC.
SMX data types:
09

00
EXP 0(09:00)

00
FE(09:00)

00
ALU(09:00)

00
ALU(l4:07)

DATA PATH SPECIFICATION

Page 1-32

SMX CONTROL
The SMX data type is selected by the USMX field of the UWORD.
USMX
Uword Shift count Multiplexor control field, 2 bits.
0
1

EALU
FE
ALU
ALU EXP

1.2.7

Shift Count register
The SC is used extensively in the CPU for different control functions.
The ID BUS control section uses SC(OS~OO) to address an internal
processor register word. The DATA SECTION of the Data Path uses
SC (09, 04: 00)
to control the shift amount in the DAL.
The ARITHMETIC
SECTION uses SC(04:00) to generate a bit mask and SC(03:00) to form a
register address in the RA, RB, and RC register sets.
The SC is also used to store exponents in the EXPONENT SECTION.

SC data type:
00

09
LOAD SC

SMX(09:00)

SC CONTROL
The loading of SC is controlled by the USCK field of the UWORD.
USCK
Uwo rd Shift Count control (K)
0
1

HOLD
LOAD

field, 1 bit.

DATA PATH SPECIFICATION
1.3

Page 1-33

DATA SECTION

The DATA SECTION controls the shifting, the byte alignment, the
unpacking of floating data types, and the moving of data to and from
the DATA CACHE or ID BUS interface.

1.3.l

DFMX

Data Format Multiplexor
The DFMX is the input link from the ARITHMETIC to the DATA section and
generates data types in either integer or unpacked floating formats.
In unpacked floating format the sign and exponent fields are stripped
off and the fraction bits assembled in the correct sequence with zero
guard bits and the hidden one inserted.
Integer format:
00

SHF(31:00)

Unpacked floating format:
31 30

23 22

07 06

I 0 1 I
I
I

SHF(06:00)

SHF(31:16)

I
I
I o o o o o o o I
I
I

DFMX CONTROL
The DFMX formats are controlled by the UQK and UDK fields of the
UWORD.
If either control field calls for unpacked floating data the
DFMX will select that format, otherwise integer format will be used.
Refer to sections 1.5.5- and 1.5.6 for control codes.

DATA PATH SPECIFICATION
1.3.1.1

Page 1-34

BUS DFMX -

This is a tri-state bus that provides a data link from the Arithmetic
Section, DFMX, or from the Floating Point Accelerator to the Data
Section.
The Accelerator uses this path to sample RA scratch pad write data
route data into the Datapath via the D register or Q register.

Tri-state control of the Bus DFMX is accomplished by programming the
UDK or UQK uword fields. Accelerator control is made by selecting
UDK=A or UQK=B. Arithmetic section control, DFMX, is the default
programming of the above uword codes.

DATA PATH SPECIFICATION
1.3.2

Page 1-35

QMX

Q register Multiplexor
The QMX provides paths for loading the Q register from either the
ARITHMETIC SECTION via the DFMX, from the Floating Point Accelerator,
from the D register such that the ARITHMETIC SECTION may
be
simultaneously used for other operations; from the ID Bus or with the
generation of a constant of six in each 4 Bit NIBBLE for use in
decimal arithmetic.
Each NIBBLE X constant is generated by the lack
of an ALU byte X carry.
QMX data types:
31

00
BUS DFMX(31:00)

31
0(31:00)

ID(31:00)

-----------------------------------------------------------------(D)

00
6

I
I

QMX CONTROL
The QMX data type is selected from the UQK field of the UWORD.

Page 1-36

DATA PATH SPECIFICATION
1. 3. 3

OMX

D register Multiplexor
The DMX provides the necessary paths for loading the D register from
the
ARITHMETIC section via the DFMX, from the Floating Point
Accelerator, the CACHE MEMORY interface via the MD BUS, distinct
sections of the total CPU and from the DAL.
DMX data types:
00

31
MD BUS ( 31 : 0 0 )

0(07:00)

0(15:08)

0(31:24)

0(23:16)

31
BUS D FMX ( 31 : 0 0 )

OAL(31:00)

OMX CONTROL
The OMX data types are selected from the
Refer to section 1.5.6 for control codes.

UOK

field

the

UWORO.

DATA PATH SPECIFICATION
1. 3. 4

Page 1-37

DAL

Data AL ig nmen t
The DAL allows the D register contents to be shifted a maximum of 32
positions to the right with the least significant end of the Q
register shifted in or 31 positions to the left with the most
significant end of Q shifted in. Positive shift numbers will cause
left shifting, negative shift numbers (two's complement notation) will
cause right shifting, negative zero value will cause a 32 bit shift (Q
register), and positive zero will result in D unshifted.
The DAL is used to perform the shifting operations required in the
execution of bit field, multiply, divide, shift and decimal arithmetic
instructions. It is also used to isolate bit fields in the virtual to
physical address translation process.
DAL shift range:
Shift amount = 000000 (NO SHIFT)
(D)

31
0(31:00)

Shift amount = 011111 (LEFT 31)
(D)

31
DOO

0(31:01)

Shift amount - 100000 (RIGHT32,

(D)

31
Q(31:00)

DATA PATH SPECIFICATION

Page 1-38

Shift amount = 111111 (RIGHT 1)
(D)

QOO

0(31:01)

Shift amount = 100001 (RIGHT 31)
(D)

Q(31:01)

I
I
I D31 I
I
I

DAL CONTROL
The DAL with the shift amount selected by either the contents of SC or
by a shift value determined by a hardware look-up may be specified by
the UDK field of the UWORD.
When the UDK field specifies that the D register be loaded with the
contents of the Q register the DAL is selected for a RIGHT shift of 32
and the OMX selects the DAL.
Refer to section 1.5.6 for control
codes.

1.3.5

Q register
The major function of the Q register is to be used with the D register
to hold data structures which are larger than 32 bits. This occurs in
the execution of field and double floating instructions.
The Q register also is used to hold the multiplier and quotient
in the execution of the multiply and divide instructions.

bits

During evaluation of instruction operands the Q register is used to
hold the first operand while the next one is being evaluated. In
general, Q is used as a temporary storage location for data generated
in thP ARITHMETIC SECTION.

Page 1-39

DATA PATH SPECIFICATION
Q register data types:

Load Q

31
QMX(31:00)

Shift left (single shift)
31

Q(30:00)

I
I
Determined by-----------USI field
Shift left (double shift)

02 01

Q(29:00)

x x
I

Determined by-----------USI field

Page 1-40

DATA PATH SPECIFICATION

Shift right (single shift)
31

Q(31:01)

I
------------Determined by
US! field
Shift right (double shift)
31

x x
I

Q(31:02)

---------------Determined by
USI field
Q CONTROL

The Q register loading and shifting is controlled from the
of the UWORD with shift inputs selected by the USI field.

UQK

UQK
Uword Q register control (K)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

field, 4 bits.

HOLD
DOUBLE SHIFT LEFT
DOUBLE SHIFT RIGHT
Reserved
Reserved
SINGLE SHIFT LEFT
SINGLE SHIFT RIGHT
Reserved
LOAD SHF (Integer format)
LOAD SHF (Unpacked floating format)
LOAD Decimal Const (NIBBLE ALU carry dep)
LOAD ACC 'DATA
LOAD D
Reserved
LOAD ID BUS
LOAD ZEROES

The shift input to the Q register is selected by the USI field.

field

DATA PATH SPECIFICATION

Page 1-41

USI - Q input
Uword Shift Input control field, 3 bits.
(D)

ALU CARRY 31 (to be used for single shift only)
Q31
031

1
2

3
4
5

1.3.6

0
0

ALU CARRY 31 (To be used for single shift only)

D register
The D register acts primarily as the data interface connection between
the DATA PATH and Memory or the DATA PATH and remotely located
sections of the CPU and FPA. When used for ID BUS write transfers,
odd
parity is generated on a per byte basis.
Parity on data received
from the ID is not checked.
The D register is used in conjunction with the Q register to hold data
structures larger than 32 bits.
It may also be used as a temporary
storage location for data generated
in the ARITHMETIC SECTIO..
D
register data types:
LOAD D

00
DMX(31:00)

Shift left (single shift)

01
D(30:00)

I
I
Determined by------USI field

DATA PATH SPECIFICATION

Page 1-42

Shift left (double shift)
02

D(29:00)

I
I
Determined by------USI field
Shift right (single shift)
30

0(31:01)

-----------Determined by
US! field
Shift right (double shift)
30

0(31:02)

--------------Determined by
USI field
D CONTROL
The D register loading and shifting is controlled from the
of the UWORD with shift inputs selected by the USI field.

UDK

field

DATA PATH SPECIFICATION

Page 1-43

UDK
Uword D register control (K)
0
1

2
3
4

5
6

7
8
9

A
B
C
D
E
F

field, 4 bits.

HOLD
DOUBLE SHIFT LEFT
DOUBLE SHIFT RIGHT
Reserved
SINGLE SHIFT LEFT if .NOT, ALU CARRY.ELSE LOAD SHF(INT FORM).
SINGLE SHIFT LEFT
SINGLE SHIFT RIGHT
Reserved
LOAD SHF (Integer format)
LOAD SHF (Unpacked floating format)
LOAD ACC DATA
LOAD D NIBBLE SWAP
LOAD Q
LOAD D (Shifted by SC (09, 04:00))
LOAD D (Shifted by SHF VAL)
LOAD ZEROES

(D}

The shift input to the D register is selected by the USI field.
The
CACHE and SBI Subsystem can load the D register only when the UDK
uword = O.
USI - D input
Uword Shift Input control field, 3 bits.
0

Q31

QOO
0

Q31

6
7

SAVED ALUOl/ALUOO
SAVED ALUOl/ALUOO

If UDK=D the D register is shifted in the DAL by the
by SC09 and SC(04:00).

value

specified

For UDK=E the D register is shifted in the DAL by a value determined
by a hardware lookup table.
This is used for the normalization of
fractions and is completed in 1 machine cycle.

DATA PATH SPECIFICATION

Page 1-44

When UDK=C, the DAL is selected for a shift of 32 which produces the Q
register on its outputs.
When USI=6 or 7 and the D register is selected for a double shift,
ALUOO is shifted into D on the first shift and ALUOl on the second
shift of the machine cycle. If a single shift has been selected,
ALUOl will be shifted in.
If a memory read operation is specified by the UDK fields of the UWORD
the D or Q register is loaded with the contents of the Memory Data
Bus. Data is stored in memory or byte boundaries but accessed on the
MD BUS on a long word boundary. To load the D register with the
correct data alignment a right shifting procedure is done by the
MDBAL.

1.3.6.1

MDBAL -

Memory Data Byte Alignment
The MDBAL provides the correct data alignment from the MD BUS for
in the Data Path.

use

MDBAL CONTROL
The right shifting process is controlled by two bits of the Virtual
Address register, VA(Ol:OO).
These two bits specify the least
significant byte position of a memory read access and the number of
right shifting of bytes required for loading into the D Register.
VA(Ol:OO)
0
0
l
l

0
1
0
1

MD Bus shift right positions
SHF[RO]*
SHF[R8]
SHF[Rl6]
SHF[R24]

If the memory control field of the UWORD specifies a memory read
operation, the D register is loaded with the contents of the MD BUS.
If the data length requires a second memory reference due to the
starting byte of the Longword add~ess being read, a mask is generated
to selectively enable the loading of bytes into the register in order
to assemble the entire data type being read. Data on the MD BUS will
be rotated according to the byte address used for the reference.

* [RX] x being equal to the bit positions shifted right.

MEMORY
READ

I
I
I
I
I
I

1------------1
I
I
I
I
I
I
I

I 3 I

ADR(Ol:OO)

DATA
TYPE:

LOAD
MASK:

2ND
REF:

LOAD
MASK:

I L I

----I
I
I

1111

I
I
I
I

I
I
I
I
I
I
I

\
\

----I w I

-----

----I B I
-----

-----

I
I
I

1111

\
1111

\
\
\

I L I

I
I
I
I

I
I

I
I
I

1111

\
\

-----

\
\

-----

----I B I
----I
I
I

I
I
I

1111

I L I

I
I
I
I
I
I
I

------IADR+4 I
-------

-------

1110

0010

1100

1000

IADR+4 I

I
\

----I wI
-----

I
\

I o I

1 I

1------------1

2 I

I
I
I
I
I
I

IADR+4 I

Figure 1-2

I w I
I
I
I

I L I

I w I

DATA PATH SPECIFICATION

Page 1-46

ADR 01, 00
MD

BUS DATA:

1.3.7

I BYTE 3/7 I BYTE 2/6 I BYTE 1/5 I BYTE 0/4 I

I BYTE 0/4 I BYTE 3/7 I BYTE 2/6 I BYTE 1/5 I

-------------------------------~----~--------

I BYTE 1/5 I BYTE 0/4 I BYTE 3/7 I BYTE 2/6 I

I BYTE 2/6 I BYTE 1/5 I BYTE 0/4 I BYTE 3/7 I

D PGEN

D reg Parity GENerator
The D PCGEN circuit generates one parity bit for each byte
register to be transmitted along with data on the IB BUS.
is generated.

1.3.8

in the D
Odd parity

BAL

Byte ALignment
The BAL is used to rotate the contents of the D register so that the
bytes are aligned with the byte address in which data is to be
written. A byte mask is generated by the hardware to control which
bytes in a long word address are to be written into memory or as an
indication as to what bytes are being read.

Page 1-47

DATA PATH SPECIFICATION
BAL data types:
= 0

A DR ( 0 1 , 0 0 )

24 23

16 15

08 07

I P3 I P2 I Pl I PO I D BYTE 3 I D BYTE 2 I D BYTE 1 I D BYTE 0 I
I

D Byte Parity

ADR ( 01, 00)

I
I
I
I
I
I
I
I
I
I P2 I Pl I PO I P3 I D BYTE 2 I D BYTE 1 I D BYTE 0 I D BYTE 3 I
I
I
I
I
I
I
I
I
I
I
\

D Byte Parity
= 2

A DR ( 0 1 , 0 0 )

I Pl I PO I P3 I P2 I D BYTE 1 I D BYTE 0 I D BYTE 3 I D BYTE 2 I

\
I

D Byte Parity

DATA PATH SPECIFICATION
ADR(Ol,00)

Page 1-48

I
I
I
I
I
I
I
I
I
I PO I P3 I P2 I Pl I D BYTE 0 I D BYTE 3 I D BYTE 2 I D BYTE 1 I
I
I
I
I
I
I
I
I
I
I

D Byte Parity
BAL CONTROL
The byte shift value is selected by the ADR address bits 01 and 00,
and the BAL output drivers are turned on by the memory control logic
in the Data Cache control.
A four bit byte mask is generated to enable the writing of individual
bytes into memory. For long word data types at ADR(Ol:OO) = 1, 2, or
3 or word data types of ADR(Ol:OO) = 2 or 3 a second memory reference
must be performed to complete the data write operation, in which case
a second byte mask must be generated. A code in the UMSC field of the
UWORD specifies the second reference of this data alignment procedure.
BYTE MASK field is also generated during Memory read operations.

MEMORY READ
OR WRITE

XFERS

I
I
I
I
I
I

1------------1
I

I
I
I
I
I
I

1------------1

I
I
I
I
I
ADR(Ol:OO)

\
\

I
\

TYPE:

BYTE
MASK:

I L I
I
I
I

1000

I
I
2ND
REF:

I
I

-------

I w I

I B I

I L I

I
I
I

1000

1100

\
\

\
1000
\

\
\

I WI

I B I

I L I

I WI

I B

I
I

I
I
I

I
I

1100

0100

I
I
I

1110

0110

0010

-----

I
I

I ADR+4 I

-------

------IADR+41
-------

0111

0001

0011

0001

BYTE
MASK:

I
I

I o I

-----

I
DATA

I
I
I
I
I

Figure 1-3

\
\

I B I

I
I
I

1111

0011

0001

I L I

Page 1-50

DATA PATH SPECIFICATION
1.3.9

RAMX

ALU

RAMX data types:
00

31
D(31:00)

31
0(31:00)

1.3.9.1

RBMX -

Register Brox Multiplexor.
The RBMX is a link for t~e DATA SECTION to provide data to the
input of the ARITHMETIC SECTION.
RBMX data types:
31

------------------------------------------------~----------------

0(31:00)

. 00

31
D(31:00)

Page 1-51

DATA PATH SPECIFICATION
RAMX and RBMX Control
The data type of the RAMX and RBMX is selected by the
the UWORD.

URMX

field

URMX
Uword Register Multiplexor control field, 1 bit.
RAMX RBMX

1.4

Q
D

ADDRESS SECTION

The ADDRESS SECTION of the Data Path
address
for
operand references,
instruction buffer address.

is used to
the program

keep the virtual
counter, and the

Each address register has counting ability so that the commonly used
address arithmetic performed does not require use of the ARITHMETIC
SECTIONQ

1.4.1

VIBA

Virtual Instruction Buffer Address counter
The VIBA holds the address for the instruction stream
fetched by the instruction buffer (IBUF) control logic.

data

being

VIBA data type:
L~D

ALU(31:00)

VIBA CONTROL
The loading of the VIBA is selected by a control code in the UIBC
field of the UWORD.
This takes place whenever the instruction
execution changes sequence such as in the case of JUMP and successful

Page 1-52

DATA PATH SPECIFICATION
BRANCH instructions or as in the initiation of
routine.

trap

interrupt

The IBUF control logic will increment the VIBA (by 4) whenever it
successfully fetched instruction data.

1.4.2

has

Virtual Address counter
The VA holds the address which the micro program generates in the data
path to read or write a memory location. The VA will primarily
contain a virtual address which must be converted to a physical memory
address by the TRANSLATION BUFFER.
At other times the VA may hold a physical memory address which has
been generated by the micro program during the translation process or
when the memory management mechanisms are turned off.
The VA may also be used to index into the TBUF whenever the TBUF is
being updated or invalidated by the micro program.
During the
execution of the PROBE instruction the indexing is used to determine
if an access violation would occur if the memory reference to that
virtual address was actually performed.
The VA also provides a load path from the ARITHMETIC SECTION into
PC.

the

VA data type:
00

ALU(31:00)

VA CONTROL
The loading of the VA is controlled by the UVAK field of the UWORD. A
command code in the UACK field specifies that the VA counter be
incremented by four.
The load
operation
will
override
the
incrementation if both functions are selected simultaneously.

DATA PATH SPECIFICATION

Page 1-53

UVAK
Uword Virtual Address control (K) field, 1 bit.
0
1

1. 4. 3

HOLD
LOAD

VAMUX

Virtual Address MUltipleXor
The VAMUX address interface logic formats the address into either the
vax address format or the 11 compatibility format and selects either
the VA or the VIBA as the address source.
VAMUX formats:
VAX MODE
31

00
VA(31:00)

02 01

VIBA(31:00)

00
0

11 COMPATIBILITY MODE
31

I
I

O<------------------------>O I

VA(lS:OO)

I
I
I O<------------------------>O I
I
I

02
VIBA(l5:02)

I
I
I
I o I o I
I
I
I

DATA PATH SPECIFICATION

Page 1-54

VAMX CONTROL
The Compatibility Mode bit in the PSL register controls which
format is selected in the VAMX multiplexor.

address

The address select is provided by a signal from the TBM.
The VA is
selected
as the address source whenever the micro program is
requesting a memory reference. At all other times, the micro program
selects the VISA as the address source and the IBUF control logic is
allowed to use the cycle to request a memory transfer.

1.4.4

Program Counter
The PC is used to hold the address of the opcode each time a new
instruction execution is started, and is incremented as each of the
operand specifiers are being evaluated.
PC data type:
04

PCMX(31:04)

00
PCAMX(03:00)

PC CONTROL
The loading of the PC is controlled by the UPCK field of the UWORD.
Command codes in the UPCK field specify incrementation of the PC by 1,
2, 4 or N. The value N is determined by the instruction buffer
control logic and is used to increment the PC beyond instruction
stream bytes associated with each specifier.

Page 1-55

DATA PATH SPECIFICATION
UPCK
Uword Program Counter control (K)
0
1
2

1. 4. 5

field, 3 bit.

4 PC<--PC+l
5 PC<--PC+2
6 PC<--PC+4
7 PC<--PC+N

NO-OP
PC<--VA
PC<--IBA
VA<--VA+4

PCADD

Program Counter ADDer
NMX
Number Multiplexor
The PCADD and NMX allow the numbers 1, 2, 4 and N to be added to the
PC register.
The number N comes from the Instruction buffer control
and may be the numbers 1, 2, 3, and 5. The four bit output of the
PCADD is loaded into the lower four bits of the PC register and if a
carry results the upper 24 bits of the register is incremented.
PCADD data type:
03

PC(04:00) .PLUS.NMX(3:0)

NMX data type:
03

02
0

fl,2,3,4, or 5

DATA PATH SPECIFICATION

Page 1-56

PCADD, NMX CONTROL
The PCADD and NMX are controlled by the UPCK field of the UWORD.

1.4.6

PCMX

Program Counter Multiplexor
PCAMX
PC Adder Multiplexor
The PCMX and PCAMX provide the data input to the PC register.
Whenever the PC register is being loaded the PCAMX selects the PCMX
for the low 4 bits and the PCMX selects either the VA register or the
VIBA register.
Whenever the PC register is counted the PCAMX selects the PCADD to be
loaded into the low 4 bits of the register while the upper 24 bits of
PC may be incremented.
PCMX data types:
31

00
VA(31:00)

VIBA(31:00)

00
0

DATA PATH SPECIFICATION

Page 1-57

PCAMX data types:
03

00
PCMX(03:00}

00
PCADD (03: 00}

PCMX, PCAMX CONTROL
The PCMX and PCAMX are controlled by
field.

the

UPCK

field

the

UWORD

CHAPTER 2
MICRO SEQUENCER SPECIFICATION

The purpose of the Micro Sequencer is to control CPU operations and
functions and control the Micro Word Fields to ensure known operation
during Powering Up, Powering Down, Micro Traps, Stalls, Micro Word
ECOs, and console operations.

2 .1

NORMAL MODE

The Micro Word is controlled by the Micro Program Counter address
lines.
(UPC) The Branch Enable field (BEN) and/or the Jump field (J
Field) control the next Micro Address (NUA) which forms the.UPC.

2.2

MICRO ECO CONTROL (UECO) MODE

The purpose of the UECO logic is to allow Micro words that need
changes to be updated and written into Writeable control store (WCS).
This greatly reduces the requirements for changing many Prom Chips by
programming only one FPLA per CPU.
When a uword ECO is needed, the UPC address of the Prom uword is put
into an FPLA. In addition, a new address to be used is put into the
FPLA which references WCS.
During CPU operation and when the UPC matches an address in the FPLA,
the FPLA outputs a signal to the stall control and Pico sequencer.
Upon receipt of an ECO Dispatch signal a clear uword fields signal and
an abort cycle signal are generated. These signals create in effect a
NO-OP cycle in which to allow a new uword from WCS to be accessed.
The FPLA output is clocked into the UECO register at CPT 0 of the
NO-OP cycle.
This register holds the lower six bits of the WCS
address which contains the program patch. The UMX select lines then
allows the UECO register to be the source for the UPC address lines.
WCS is then accessed and the new uword is clocked into the uword
registers at CPTO of the next cycle.

MICRO SEQUENCER SPECIFICATION

Page 2-2

Control is returned to the normal Prom control store sequence
Ben and J Fields of the uword from WCS.

the

The eight bit output from the FPLA is used as follows:
07= not presently used
06= signals the ECO sequence to begin
<OS:OO>= the UECO address in WCS to be accessed.

UECO FLOW
I
I
I
I

v
*****************

*
*
*
*
*****************
*

UINSTR A
I

UECO FLOW

*****************
NORMAL --->I

** NO-OP UINSTR **

*****************
*****************
*
UINSTR B
*
I
*
NEEDS
*<---BYPASSED
I
*
ECO
*
UINSTR
I
*****************
I
I

*****************
*****************
*
*
* UECO'D UINSTR *
*
UINSTR C
*<-------*FOR UINSTR B IN*

*****************

wcs

*****************

I
I

v
Figure 2-1

NO-OP UINSTR TO
ALLOW TIME TO
ACCESS THE WCS
ADDRESS WITH THE
REVISED UINSTR
B

REVISED UINSTR B.
AND BEN FIELDS
ARE USED TO SELECT
ADDRESS FOR UINSTR C
AND GO BACK NORMAL
PROM UINSTR.

MICRO SEQUENCER SPECIFICATION
2.3

Page 2-3

MICRO TRAP (UTRAP} MODE

Utraps are due to faults or errors in the CPU.
Upon receiving a utrap
signal the Micro sequencer control (USC} sends out the signals clear
uword and abort cycle. to other CPU subsystems. These signals create
NO-OPs and allow time to direct the CPU to error handling micro code.
The utrap signal is clocked into the Pico sequencer at CPTO.
The
utrap cycle then selects the UMX to make the vector address the UPC
address for the new uword to be clocked into the users registers at
the next CPTO.
The utrap cycle clears the Ben,USUB, and JField registers on the use.
Ben 10
(HEX}
is then enabled to allow the CEH module to control the
NUA bits <03:00> as per the type of utrap.
The utrap vector address areas are:
Prom

0100

up to

OlOF

(HEX)

wcs

1100

upto

llOF

(HEX}

vector
The console can direct the utrap
CIBN UPC 12(1} H bit is set in the console.

The UTRAP vectors are in HEX and their functions are:
XlOO

System Ini t

XlOl

Unaligned Data Trap

Xl02

Page Trap

Xl03

M Bit

Xl04

Protection Violation

Xl05

Translation Buffer Miss

Xl06

Reserved Floating Operand

Xl07

Trans.

Xl08

Cache Parity Error

Xl09

Reserved

XlOA

Reserved

XlOB

Reserved

Buffer Parity Error

wcs

when

the

MICRO SEQUENCER SPECIFICATION
XlOC

RDS Error

XlOD

Time Out

XlOE

Odd Address Error

XlOF

Control Store Parity Error

Page 2-4

When a utrap is iniated by the hardware, the Micro Program ~ounter
save register (UPCSV) contents are pushed onto the Micro Stack memory
(USTACK) to specify the address of the NEXT normal uword to be used
when returning from the utrap routine. The UPCSV is clocked at CPT O
and therefore holds the UPC of the current executable uinstr.
During
utrap sequences the current executable uinstr is NO-OP'd while the
ustack push is done.
The ustack pointer (USP) address is decremented prior to
information onto the ustack.

writing

the

When in a utrap cycle a signal for clearing utraps is sent to the CEH
module at CPT 75 to acknowledge a utrap cycle (uword no-op to set up
the utrap vector address) being in progress.

2.4

CONTROL STORE PARITY ERROR MICRO TRAP MODE

This utrap differs from the other utraps in that the clocking of the
UPCSV is inhibited at CPT 0 • The UPCSV contents which are pushed
onto the ustack are the address of the control store uword which
failed parity checking instead of the updated address as in any other
utrap.

Page 2-5

MICRO SEQUENCER SPECIFICATION

UTRAP FLOW
I
I
I
I

v
*****************

*
*
*

UINSTR A

*<------------- UTRAP DETECTED

*****************
I
I
I

UTRAP FLOW

--->----------------I
*****************
*NO-OP UWORD TO *
*SPECIAL FIELDS *

NORMAL --->I

*******************

*****************

**
*

UINSTR B

*
*

I
I
I
I
I

I
I

*<----

*****************

I
I
I
I
I

* (X) UINSTR **
*
*
*****************

START OF UTRAP HANDLER
ROUTINE. BEN + J FIELDS
DETERMINE NEXT UWORD
ADDRESS.

I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I

NO-OP FOR (1) UWORD,
SET VECTOR FOR NEXT
UWORD. VECTOR ADDRESS
=0100 THRU OlOF, OR
1100 -- llOF. PUSH
UPC SV TO USTACK
(ADDRESS OF UINSTR B) •

*****************

* (X+N) UINSTR

*****************
I
I

*****************

*
*******************
* RETURN UINSTR *
I

Figure 2-2

USES USTACK FOR NEXT
UINSTR ADDRESS (UINSTR
B) • J FIELD AND BEN
SHOULD BE CLEAR.
ECO
TO DISPATCH THE
RETURN IN
CERTAIN CASES

MICRO SEQUENCER SPECIFICATION
2.5

CACHE STALLS

Cache Stalls are basically due to the Cache data not present
reads, and the Cache waiting on I/O subsystems during writes.

during

For a complete definition of conditions causing a Cache stall refer to
the Cache Subsystem Specification. During Cache Stalls other uword
functions are temporarily put in a NO-OP state by sending out the
clear uword signal to other subsystem units. This NO-OP condition may
last for several Micro cycles until Cache is finished and negates the
stall signal.
Upon- completion of Cache Stall the next uinstr to be perform~d would
be the uinstr that would have been executed if the stall had not
occured.
The UPCSV contents are selected thru the UMX to be the UPC to be used
to address the uword when the stall signal is asserted and when the
stall signal becomes false.
STALL FLOW
I
I

SPECIAL FIELDS ARE HELD OR CLEARED
UNTIL STALL IS FINISHED. UPCSV
MAINTAINS THE ADDRESS OF B, WHICH
WILL BE ENTERED UPON THE FINISH
OF STALL.

*****************

*
*
*

UINSTR A

*
*

*****************
I

STALL DETECTED

*****************

*
*
* NO-OP UINSTR *<-----*
*
I

NORMAL --->I

*****************

I
I

I
I
I

*****************

UINSTR B

* YES

*<-----*

*****************

*****************
STALL FINISHED?

*NO

***********************

I
I
I
I

v
Figure 2-3

*-----

MICRO SEQUENCER SPECIFICATION
2.6

Page 2-7

SYSTEM INITIALIZE

During !nit the following conditions are held:
o
All USC ~egisters are held clear except the UECO
BREAK, and the V-Bus registers.

UPCSV,

UPC

The UMX selects are held so that a constant utrap vector is
the UPC address and the decision point branch is inhibited.

The Init state is held for one Micro cycle after the system
Init level goes way to ensure all CPU subsy~tems start
operations synchronously.

For all conditions that generate initialize refer to the
and ICL modules specification.

CEH

INIT
I

!<------------------I

*****************
SYSTEM
*
*
!NIT.
*
*
UINSTR
*
*
*****************
I
I
*****************

I
I
I
I
I
I
I
I
I

*YES

DCLO?

*---------*

***********************
I NO
I

*****************
UINSTR
*
*
A
*
*
START UP
*
*
*****************
I
I

I
I
I

v
Figure 2-4

THIS FORCES THE !NIT. LOOP
UNTIL POWER BECOMES OK.
WHEN POWER BECOMES OK, THE
FIELD OR BEN FIELD OF THE
UINSTR AT VECTOR LOCATION
XlOX WILL GENERATE THE NEXT
UINSTR ADDRESS FOR START UP.

Page 2-8

MICRO SEQUENCER SPECIFICATION
2.7

MICRO SUBROUTINE FIELD (USUB)

The uSub field is a two bit field and the operations are:
CODE

FUNCTION

OPERATION

NO-OP

No effect

Call

USP Decrements
uStack Word written
with UPCSV Data
uPC<---(JField orBen)

Return

uStack word
UPC<---(JField or Ben)
or(uStack return
address-13 bi ts)
USP Increments

Decision Point
Branch (DPB)

F.P.A to control UPC <12>
JField to control UPC <11:08>
I Buff to control UPC <07:00>

Control store bus bits <65:64> make the uSub Field.

2.8

JUMP FIELD (JFIELD OR UJMP)

Jump Field <12:00> 13 bits forms the base address for the next
address.
(NUA) Control store bus bits <12:00> make the Jfield.

2.9

BRANCH ENABLE FIELD (UBEN)

UBen is a 5 bit field and the type of branches enabled are:
FUNCTION

OPERATION

Ben 00
Ben OF-01
Ben lB-10
Ben lF-lC

No Ope ration
1 of 15-(8) way Branch conditions
1 of 12-(16) way Branch conditions
1 of 4-(32) way Branch conditions

Control store bus bits <76:72> make the uBen Field.

Micro

MICRO SEQUENCER SPECIFICATION
2.10

Page 2-9

OTHER FIELDS - UBS+UBCT (NOT ON USC)
(See ID Bus

2.11

sp~cif ication)

FUNCTION

OPERATION

Push uStack

USP Decrements
ID Bus Data Bits <15:00> written
Uses:
1.
Pass Parameters from
D register to
a subroutine
2.
Put a return
address on uStack
for console control

Pop uStack

ID Bus (uStack word)
USP Increments
Uses:
1. Adjust uStack
2.
Read the stored
UPCSV to
determine
error locations

CALL SUBROUTINE

If the uinstr specifies a call subroutine function the UPCSV is pushed
onto the uStack and forms the return address to be used later.
The
Ben, JField, and/or Decision point branch then determine the start of
the subroutine UPC.
The Micro stack pointer (USP)

2.12

is.decremented prior to the push.

RETURN SUBROUTINE

The push of the call subroutine puts the UPC of the uinstr
that has
the CALL onto the uStack.
When a return function is specified the
uStack is "OR" D with the J field and/or Ben field of the
return
uinstr
to make t
return to the correct next uinstr past the call
uinstr.
After the return address is popped off the uStack, the USP is
incremented.

MICRO SEQUENCER SPECIFICATION

Page 2-10

CALL SUBROUTINE AND RETURN
I
I
I

UPCSV PUSHES THE ADDRESS
OF UINSTR A ONTO THE USTACK.
BEN, J FIELD OR OPCODE
SPECIFIER THEN DETERMINES
THE START OF THE SUBROUTINE
UPC.

v
*****************

* UINSTR A CALL *
*
*
*****************
I

*****************
*
* (X) UINSTR
START
*
*
SUBROUTINE
*
*
*****************

NORMAL----->!
I

*****************

*
*

UINSTR B

*
*

*<----

*****************
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I

I
I
I
I
I

I
I

*****************
*
*
* (X+N) UINSTR *
*
*
*****************

I
I
I
I

v
I

I
I

*****************
*
*
* RETURN UINSTR *
*
*
*****************

I
I

I
I
I

-----------------------------<--USTACK USED FOR RETURN ADDRESS.
J FIELD 'OR' D WITH USTACK DATA
TO MAKE THE CORRECT RETURN TO
UINSTR B.
Figure 2-5

2.13

POWER UP OR DOWN

These conditions force the initialize signal which keeps the USC in an
initialize state until after power becomes good.
A constant uTrap
vector is put onto the UPC lines during bad power.

MICRO SEQUENCER SPECIFICATION
2.14

Page 2-11

CONSOLE CONTROLLED OPERATIONS

The following registers can be accessed by the console:
The uStack can be written from the ID Bus by a push function.
This
causes the USP to decrement and then write the ID Bus data onto the
uStack.
The uStack can be read from the ID Bus by a POP function.
The
data is given to the ID Bus and then the USP is incremented.

uStack

Maintenance return can select the uStack as a source for the NUA.
This causes the NUA to get the uStack and then the uSP is incremented.
The
console
signal
to
generate
maintenance
return
is
CIBN D MAINT RTN L.
The uPC break register can be written from or read by the ID Bus.
The WCS address register can be written from or read by the ID Bus.
The WCS Data can be written from the ID Bus in 32 data bit groups.
When the WCS Data is read by the ID Bus, bits <07:00> reflect the
eight possible WCS lK address assignments and the presence of the WCS
control store modules.
All zeroes will be read back on ID Bus bits
<31:08>.
The uPCSV register, the branch input lines and many other USC
can be read by the V-Bus to the console.

signals

The Break match signal goes to the clock control and will enable the
CP clock to be stopped during CPTO of a desired Micro word address if
the console enable bit is set which also goes to the clock control.
The Break match signal becomes true when the UPC break register
contents equals the uPC address of the NEXT uword to be used.
This
signal also is gated to the backpanel during CPT 150 time for an
oscilloscope sync and to TPl by the module handle.
The console can direct any uTrap handling to WCS instead of the normal
Prom CS by forcing uPC <12> to a 'ONE' during uTraps. This is done by
the signal CIBN UPC 12(1) H.
The.console can
C IBN ROM NOPL.
be true.

direct a micro word no-op cycle by the signal
This forces the CLR uword and abort cycle signals to

The timing of ID Bus read/writes
accordance with the ID Bus spec.

USC

registers

done

The size of the registers accessed under ID bus operations are:
uStack = 16 Bits
"1'.:",... Break = 13 Bi ts
wcs address = 16 Bits
WCS Data = 32 Bits Write, 8Bits read

Page 2-12

MICRO SEQUENCER SPECIFICATION
use ID Bus address assignments are in Hex as follows:
ADDRESS

20
21
22
23

Micro stack
uPC Break
WCS address
WCS Data

When writing or reading the use registers by way of the
LEAST significant bits will be used to pass the data.

Bus,

the

WCS address register format

13 12

14
PAR
INV

MODULO
3 CNTR

00
ADDRESS

= O = NORmal Parity
1 = Inverted Parity
<14:13> = 00 = WCS Data Bits <31:00>
01 =
<63:32>
10 =
<95:32>
11 = No Group Selected
<12:00>
= WCS address
<15>

The modulo-3 counter will count as follows in binary:
00
01
10------ COUNTER OVERFLOW AND ADDRESS INCREMENT

I
00-----11
can only be loaded (INVALID)
The count of (11) can only be loaded and when loaded no further WCS
data writes or address increments can take place until the modulo-3
counter and entire register are reloaded with a valid count.

MICRO SEQUENCER SPECIFICATION

Page 2-13

overflow from the Modulo-3 counter occurs when the count goes
(10) to (00) and increment the binary address in bits <12:00>.

from

The Modulo-3 counter increments after each WCS write.
This allows the
data to be written in successive higher order 32 bit groups without
having to perform a WCS address write each time before writing data.
To write WCS, the WCS address register must be loaded and then a WCS
write data must be performed.
These cycles may be either back to back
or spaced in time.
Microstack output data is clocked into a register at CPT
until the next CPTO.

and

held

V-Bus operation allows certain signals on the Micro sequencer to be
read by the console in a transparent mode in respect to the micro
sequencer.
The ID Bus address and read/write decoding are in accordance with
ID Bus specification.

2.15

the

PICO SEQUENCER AND PRIORITY DECODING

The Pico sequencer consists of flip-flops clocked at CPTO to hold
the
conditions as exist at the beginning of a micro cycle.
The conditions
held are:
Initialize
Maintenance return
Cache Stall
Micro Trap
UECO
Priority of levels is as follows:
Highest Priority

Lowest Priority

Initialize
Maintenance Return
Cache Stall
Micro Trap
uECO
Normal

When maintenance return is true from the console, the CPU clock must
be stopped and under control of the console.
Maint.
return keeps the
NUA lines as the selected source of the UPC lines.
Maintenance return also inhibits writing of the ustack if a
push operation occurs during the maint.
utrap.

utrap

MICRO SEQUENCER SPECIFICATION
2.16

Page 2-14

UPC ADDRESS LATCHING

The UPC latches hold the UPC lines stable to ensure that the control
store bus lines are not changing. This is to prevent a false uword
parity error. Control of the USC UMX tri-stating and decision point
branch UMX tri-stating and UPC latching keeps the UPC valid.
At CPT 50 plus gate delays the USC UMX or decision point branch UMX
are tri-state enabled. The UPC lines <09:00> are valid at CPT 90 plus
lOns of clock skew to the control store address inputs. The UPC lines
<12:10> are valid at CPT 94 + lOns of clock skew at the contr61 store
chip enable inputs. The inverter and open collector nand gate latches
are enabled at CPT 125.
At CPT 150. time plus gate delays the UMX
tri-states are disabled with the latches holding the UPC levels.
At
CPT 50 the latches are opened and the next UPC address cycle can
begin.
The present address in the UPCSV register will be displayed in 13 leds
mounted near the module handle.
A separate LED by the E-F handle
section will be used to display the stall condition.

CHAPTER 3
INTERNAL DATA BUS SPECIFICATION

The Internal Data Bus is a high speed data path connection between the
major functional areas of the CPU. It has four purposes:

3.1

Allows data to be transferred to/from the internal status and
control registers and translation buffer.

Allows data in the form of displacements, and short & long
literals to be transferred from the Instruction Buffer to the
CPU and ACC data paths.

Allows data transfers between memory (via the D register) and
the ACC data paths to take place.

Allows access of the internal registers from the console
under console control in a maintenance operation mode.

FUNCTIONAL OPERATION

The ID BUS control is derived from a control field in the UWORD in
normal operation and from the console interface logic in maintenance
operation.

3.1.l

Normal Operation

Data transfers over the ID BUS are always directed to the Q and from
the D register in the CPU data paths. The ACC will, however, snapshot
the data on the bus when a transfer is being made from the IBUF to the
Q register.

INTERNAL DATA BUS SPECIFICATION

Page 3-2

3.1.1.1 ID BUS Addresses - The ID BUS signal lines contain a six bit
field
to
specify which internal register has been designated as the
source or destination of data on the bus.
The address assignments are as follows:

00
01
02
03
04
05
06
07
08
09
OA
OB

OD
OE
OF
10
11
12
13
14
15
16
17
18
19
lA
18
lC
lD
lE
lF

IBUF DATA
TIME OF DAY
NOT USED
SYSTEM ID
CNSL RXCS
CNSL RXDB (TO ID)
CNSL TXCS
CNSL TXDB (FROM ID)
DQ (ID MAINT ONLY)
NEXT INTERVAL REG.
CLOCK CS
INTERVAL COUNTER
CES
VECT
SIR
PSL
TBUF DATA
-RSVDTB UF REGO
TBUF REGl
ACC REGO
ACC REGl
ACC MAINT REG.
ACC CONTROL/STATUS
SBI SILO
SBI ERR REG
SBI TIMEOUT ADDRESS
SB! FAULT/STATUS
SB! SILO COMPARATOR
MAINTENANCE
CACHE PARITY
-RSVD-

20
21
22
23
24
25
26
27
28
29
2A
28
2C
2D
2E
2F
30
31
32
33

USTACK
UBREAK
WCS ADDRESS
WCS DATA/STATUS
POBR
PlBR
SBR
RSVD FOR SYS SPACE
KSP
ESP
SSP
USP
ISP
FPDA
D.SV
Q.SV
TO
Tl
T2
T3

35
36
37
38
39
3A
3B
3C
3D
3E
3F

TS
T6
T7
TB

T9
PCBB
SCBB
POLR
PlLR
SLR
RSVD FOR SYS SPACE

INTERNAL DATA BUS SPECIFICATION

Page 3-3

3.1.1.2 ID BUS Directional Control - One of the signal lines on the
ID BUS will specify whether an internal register is to be read onto
the bus or if data is to be clocked from the bus into the internal
register.
The D register in the Data Paths always acts as the source
and the Q register as the destination.
ID WRITE L
H - ID BUS DATA<--(ADDRESSED REG.)
L - (ADDRESSES REG.)<--ID BUS DATA

3.1.1.3

ID BUS Data - There are 32 data signals on the ID BUS.

3.1.1.4

Signal Summary - There are 39 signals on the ID BUS:
SIGNAL NAME

NO. OF LINES

-----------

------------

BUS ID D[31:00] L

32
or

ID LEFT ADDR (5:0) H
ID RIGHT ADDR (5: 0) H

ID LEFT WRITE L
ID RIGHT WRITE L

6
1

3.1.1.5 ID BUS Control - The ID BUS signals are controlled by a field
in the UWORD.
The same UWORD field also controls MD BUS operation and
therefore requires a 1-bit field
in the UWORD for BUS control
definition.
It is important to understand that the ID BUS is always active.
That
is,
when the BUS control field defines MD BUS operations the ID
address and write signals are zero and thus controlling the IBUF DATA
to be gated onto the ID BUS data lines.
The UQK field of the UWORD
will select the appropriate time to clock the ID BUS data into the Q
register.

INTERNAL DATA BUS SPECIFICATION
The UWORD fields which
follows.

control

Page 3-4
ID

and

BUS

operations

are

UFS I ________________
UM CT [ 3 : 0 ] I

I X I UC ID [ 2 : 0 ] I
UFS - UWORD
0
1

Function Select, 1 bit

- UMCT [3:0] = MD BUS CONTROL; ID BUS <-- IBUF DATA
- UCID (2:0] = ID BUS CONTROL & Console Control
No MD BUS function selected by micro instruction.

UMCT - UWORD Memory Control Field, 4 bits
UFS=O:

SEE CACHE-SBI-TB SUBSYSTEM SPEC.

UFS=l:

UCID - UWORD Console and ID bus control field
4 - ID DATA <-- (Internal Reg [SC 5:0])
5 - ID DATA<-- (Internal Reg [UKMX 5:0])
6 - (Internal Reg [SC 5:0]) <-- ID DATA
7 - (Internal Reg [UKMX 5:0]) <--ID DATA

Internal Register addresses are generated either from the SC data path
register or from the UKMX field of the micro-instruction.
& Console Control:
0 - NO-OP
1 - UNUSED
SEE UWORD SPEC.
2 - CNSL ACK
3 - CNSL CONT

3.1.2

Maintenance Operation

The ID BUS may also be controlled from the console interface logic in
a maintenance mode operation. This allows access to writable control
store, the USTACK, and visibility of internal registers from the
console without the need of main microcode running. In maintenance
mode operation only, the Data Paths D & Q registers may be addressed
as an internal register over the ID BUS.

3. 1.2.l Console Control of ID BUS - Control of
the
ID
BUS
is
accompl isned
via an interface signal generated by the console
interface logic, ID MAINT.
When this signal indicates a maintenance operation the console
assert ID BUS address and write signals and may assert data.

3.2
3.2.l

will

ID BUS REGISTER DESCRIPTION
IBUF DATA

00
DATA(31:00)

-READ ONLY REGISTERSEE IBUF SPEC

3.2.2

SYSTEM ID

00
ID (31:00)

-READ ONLY REGISTERSEE CONSOLE SPEC

3.2.3

CNSL RXCS

08 07

I O<----------------------->O I

06
DONE

I
I
I
I RIE IO<--~---->OI
I

I
w

-READ/WRITE REGISTERSEE CONSOLE SPEC

I
V1

3.2.4

CNSL RXDB

00
DATA(31:00)

-READ ONLY REGISTERSEE CONSOLE SPEC

3.2.5

CNSL TXCS

08 07

I
I
I
I
I
I 0<---------------------->0 I RDY I TIE IO<----------->OI
I
I
I
I
I
-READ/WRITE REGISTERSEE CONSOLE SPEC

3.2.6

CNSL TXDB

31
DATA(31:00)

-WRITE ONLY REGISTERSEE CONSOLE SPEC

3.2.7
31

CLOCK CONTROL/STATUS
16 15

08 07

I INTR I CLK I SGL I

IO<----->OIERRIO<-->OI
I
I
I

REQ I

I
IE I CLK I XFER IO<---->OI RUN I
I
I
I
I
I

-READ/WRITE REGISTERSEE INTERVAL TIME CLOCK SPEC

3.2.8

NEXT INTERVAL COUNT

00
COUNT(31:00)

-WRITE ONLYSEE INTERVAL TIME CLOCK SPEC

3.2.9

INTERVAL COUNT

00
COUNT(31:00)

-READ ONLY REGISTERSEE INTERVAL TIME CLOCK SPEC

3.2.10

TIME OF DAY
00

TIME(31:00)

I
.I
I

-READ/WRITE REGISTERSEE TIME OF DAY SPEC

I
.....,J

3.2.11

ACC REG #0 THRU #1

00
DATA(31:00)

SEE ACCELERATOR SPEC

3.2.12

ACC MAINT

I
I

ILOADI
I UBKI

ACC UPC

16 15

ACC TRAP UPC

-READ/WRITE REGISTER--SEE ACCELERATOR SPEC

3.2.13

ACC CONTROL/STATUS

27 26

07 06 04 03

I
I
I
I
I ACC I
I REV I ACC
I
I ERR I ERROR STATUS I EN I O<--------------->O I LVL I TYPE I
I
I
I
I
I
I
I
-READ/WRITE REGISTER--SEE ACCELERATOR SPEC

3.2.14

TBUF DATA

00
~

DATA(31:00)

'°tD
w

-WRITE ONLY--SEE CACHE SUBSYSTEM SPEC

I
CD

3.2.15

TBUF REGO
---

21 20

18 17

08 07

16 15

I
I REPL I FORCE I FORCE I
I 0<-->0 I BOTH I REPL I MISS I
I
I
I
I
I

TB I TB I
I Gl I GO I
I HIT I HIT I

LAST
REF

I FORCE I
I TB PE I
I
I

00
MME

-READ/WRITE REGISTERSEE CACHE SUBSYSTEM SPEC

3.2.16

TBUF REGl

21 20

08 07

I
I
I
TBUF
I
I O<---->O I PARITY ERR 1
I
I
I

I
I
I LAST I
I WP I
I
I

I
I
TBUF
I
I IPA STATUS I
I
I

-READ/WRITE REGISTERSEE CACHE SUBSYSTEM SPEC

3.2.17

SBI SILO

I FIRST
I AFTER
I FAULT
I

I
I
I
I
I B ( 31: 2 8)
I INTLK I ID(4:0) I TAG(2:0) I
or
I
I
I
I M( 3: 0)
I
I
I
I

25 24

22 21

18 17

16 15

I
I
I
I CNF(l:O) I
I
I
I
I

TR(lS:OO)

-READ ONLYSEE SBI REGISTER DEFINITION

V.J
I
y:,

3.2.18

SB! TIMEOUT ADDRESS

MD
SEL

28 27

PROT
CHK

PA(29:2)

-READ ONLYSEE SB! REGISTER DEFINITION

3.2.19

SB! FAULT/STATUS

PAR
FLT

URD
FLT

MXM
FLT

20 19

26'

XMIT

I
I

I
I
I

I INTR
I
I

IO<---------->OI FLT

FLT
IE

SB!
FLT

FLT
SILO
LOCK

O<------------------->O

-READ/WRITE REGISTERSEE SBI REGISTER DEFINITION

3.2.20

SBI SILO COMPARATOR

27 26

I SILO I SILO I
I
I
I LOCK I LOCK I LOCK I LOCK I
I
I IE I UNCOND I CODE I
I
I
I
I
I

20 19

23 22

I
I
CMD/ I
MASK I
I

-READ/WRITE REGISTERSEE SBI REGISTER DEFINITION

16 15

TAG

I
I
I
I COUNT I O<---------->O I
I FIELD I
I
I

3.2.21
31

SBI MAINTENANCE

--·-·--- - - - 28 27

23 22

17 16

15 14

13 12

09 08

I
I FORCE SBI
I
FAULT
I

I
I MAINT
I ID(4:U)
I

FORCE
SBI
IN VAL

EN
I REV I
SBI I CACHE I FORCE
INVAL I PAR I MISS
I
I

I
I FORCE
I REPL
I

I DIS
I SB!
I CYC
I

I
I REV I MATCH
I Pl I
I
I

I
I FORCE
I
TO
I

I
I
IO<----->OI
I
I
I
I

-READ/WRITE REGISTERSEE SBI REGISTER DEFINITION

3.2.22
31

SB! CACHE PARITY
16 15

I
I CACHE
I O<-------->O I PAR
I
I ERR
I
I

CP
ERR

PARITY
OK

-READ ONLYSEE SB! REGISTER DEFINITION

3.2.23

USTACK
16 15

I
I
I O<---------------------->O I
I
I

DATA(l5:00)

-READ/WRITE REGISTERSEE MICRO SEQUENCER SPEC

w
I

.....
.....

3.2.24

UBREAK

I
I
I

13 12

O<---------------------->O I

DAT A ( l 2: 0 0 )

-READ/WRITE REGISTERSEE MICRO SEQUENCER SPEC

3.2.25
31

WCS ADDRESS
16 15

I O<--------------~->O
I·

13 12

I
I INV I DATA I
I CS I SLICE I
I PAR I SEL I

WCS ADDR(l2:00)

-READ/WRITE REGISTERSEE MICRO SEQUENCER SPEC

3.2.26

WCS DATA/STATUS

WCS DATA(31:00)

-WRITE ONLY BITS08 07

I
I
I
I

O<---------------------------------->o II
I
-READ ONLY BITS
SEE MICRO SEQUENCER SPEC

00
WCS 11< BANK
AVAILABILITY

J. 2. n

p,Q_j!:~HJ'r__ ~rnDE

ONLY)

00
DATA TO Q REG.(31:00)

-WRITE ONLY BITS00

31
D REG(31:00)

-READ ONLY BITS-

3. 2. 28

SIR
21 20

I
I
I O<----------------->O I
I
I

16 15

IPLA

SIR(OF:Ol)

I
I
I o I
I
I

-READ/WRITE REGISTERSEE INTERRUPTS $ EXCEPTIONS SPEC

3.2.29

PSL

29 28 27

25 24 23

22 21

20 16 15

08 07

I
I
I
I
I
I
I
I c UR I PREV I
I
I
I
I
I
I
I
I
I
I
I
I CMP I TP I 00 I FPD I IS I MOD I MOD I 0 I IPL IO<-->OI DV I FU I IV I T IN I Z I V I C I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-READ/WRITE REGISTER-

w
I
......
w

17 16

O<---------------->O

NESTED
ERR

12 11

CS PAR
STATUS

PE
SUM

FIELD

07 06

UBRANCH
CCC

04 03

AR ITH
TRAP
CODE

PME

DESCRIPTION

ASTLVL
(Asynchronous System
Trap LeVeL)

Loaded or read by micro-code
in MTPR Src, @#ASTR or
MFPR @#ASTR, dst.
Used
in
execution of REI instruction
for AST delivery. Read/Write.
Cleared on power up.

PME
(Performance Monitor
·Enable)

Loaded or read by micro-code
in MTPR Src, @#PMR or MFPR
@#PMR, dst.
Cleared on power
up. Read/Write.

ARITH TRAP CODE
(ARITHmetic TRAP
CODE)

Loaded by hardware for enabled
integer overflow traps when
the V bit
is set using
the
CCL7
function of the UCCK
field of the UWORD.
Must be
loaded
by
microcode
for
arithmetic traps detected by
other means.
If non-zero an
ARITHMETIC
TRAP
occurs.
Read/Write.
Cleared on power
up.
NOTE: The write is disabled
if the appropriate Trap enable
in PSL is O for the code being
loaded.
The codes have
meaning:
0
1
2
3
4
5
6
7

the

following

NO ARITHMETIC TRAP PENDING
INTEGER OVERFLOW
INTEGER DIV by ZERO
FLOATING OVERFLOW
FLOATING DIV by ZERO
FLOATING UNDERFLOW
DECIMAL OVERFLOW
DECIMAL DIV by ZERO

ASTLVL

Loaded by the micro-code or
by the CCLl function of the
UCCK field of
the
UWORD.
Read/Write.
Cleared on power
up.

UB H!\NC H CC
( M i c r o BRANCH

Condition Codes)

BIT
7 - ALUC
8 - ALUZ
9 - ALUN
10 - EALUZ

11 - EALUN
CS PE(2:0)
(Control Store Parity
Error)

Status indicators for Control
Store Parity errors as
fol lows:
CS PEO - CS DATA(31:00)
CS PEI - CS DATA(63:32)
CS PE2 - CS DATA(95:64)
Cleared on power up or by
writing a one into CS PE SUM
bit position. Read Only.

CS PE SUM
(Control Store Parity
Error SUMmary)

The 'or' of CS PE ( 2: O)
Read/Write.

NESTED
ERR

Read/only bit used by
micro-code
in
memory
management flows. Cleared on
power up.

3.2.31

VECTOR

0<--->0

VALID

21 20

PRIOR

16 15

NUMB
ONES

09 08

O<------>O

VECTOR
w
I

.......

-READ/WRITE REGISTERSEE INTERRUPTS & EXCEPTIONS SPEC

lJ1

3.2.32

FPDA, D.SV, Q.SV

DATA(31:00)

DESCRIPTION

Read/write registers used by micro-code in memory
management flows.
TO thru T9
31

00
DATA(31:00)

DESCRIPTION

Read/write registers used by micro-code as temporary
holding registers.

3.2.33

POBR PlBR SBR POLR PlLR SLR PCBB SCBB KSP ESP SSP USP ISP
00

DATA(31:00)

-Read/Write System registers-

CHAPTER 4
INSTRUCTION BUFFER

The instruction buffer is a eight byte array that fetches and decodes
instruction
$tream data to decode opcodes and operand address
information. It is basically made of a fifo type byte buffer with
decode logic to generate micro addresses and branch conditions.
The major sections of the instruction buffer are:

4.1

Buffer Data Path

I-Stream Data Mux

IR Decode Logic

BUFFER DATA PATH

The instruction buffer data path consists of four major components:

4.1.l

A buffer register for storage of information.

A multiplexer shift
buffer register.

data

thru

the

An input multiplexer for selecting data from memory
the shift network.

from

A byte rotator used to convert the long word
from the cache into byte addresses positions.

aligned

data

each.

The

network

for

advancing

Buffer Register

This register is divided into eight sections of nine bits
nine bit sections contain:
8 Bits of data
l Bit to indicate valid data

INSTRUCTION BUFFER

Page 4-2

The bytes within the register are designated as bytes 7 thru O.
Byte
O corresponds
to data with the lowest value memory addresses.
Likewise, the memory address increases with higher number byte
positions.
Most Sig
Mem Adrs

Least Sig.
Mem Adrs

Byte Position
The chip types for this register are 74Sl74's for bytes 7 thru 2.
bytes 1,0 will be 74Sl75's.
The entire register
conditions.

4.2

will

clocked

CPU

with

For

gating

SHIFT NETWORK

4.2.1

Multiplexer Shift Network

The shifting scheme for the instruction buffer is a four input
multiplexer that is arranged to shift nine bit sections by O, 1, 2 or
4 positions right at each micro cycle.
The control of the shifter
will be from a decode of 4 bits of the micro word. The micro controls
are:
UIBC
0 1 2 3 4 5 6 7 8 9 A B C D E F -

NOP
STOP
FLUSH AND LD VIBA
START
CLR BYTES 0,1
CLR BYTES 2,3
NOT USED
B DEST
NOT USED
NOT USED
NOT USED
NOT USED
CLR BYTE 0
CLR BYTE 1
CLR BYTES 0,1,2,3
CLR BYTES 1-5 CONDITIONAL

INSTRUCTION BUFFER
4.2.1.1

Page 4-3

MICRO Control Use -

0 - NOP - Default
buffer.

State.

Has

effect

the

instruction

1 - STOP
The assertion of this code will
disable
the
instruction buffer cache requests. Current use is for micro
code fault routines.
2 - FLUSH - This code is used to clear all valid bits of the IB.
This will be used for jumps or branches and ·other conditions
that change the PC. The same micro STATE will load the
virtural IBA.
3 - START - The assertion of
operations to the cache.

this

code

will

resume

prefetch

4 - CLR 0,1 - This is used for compatibility mode to advance to
the next OP code. It is also used in VAX mode for optimized
fast execute (S , R or R, R) or 16 bit branch destinations.
5 - CLR 2, 3 - This is used only in compatibility mode for
discarding 16 bit displacements and literals after they have
been used.
7 - B DEST - This code is used by the microcode to extract branch
destinations from the instruction stream.
C - CLR 0 - This is used in VAX
opcode.

mode

advance

the

D - CLR 1 - This is used in VAX mode for discarding the specifier
from
the IB.
It is only used for displacement mode
addressing, absolute addressing or long literals.
In these
modes, the last thing removed from.the instruction buffer is
the specifier. In all other modes, the specifier will be
removed by hardware.
E - CLR 0,1,2,3
This is used in compatibility
optimizing literal to register instructions.

mode

for

F - CLR 1-5 Conditional - This is used in VAX mode for discarding
long literals or displacements from the IB. The hardware
will decode the specifier and/or opcode to determine 8,16, or
32 bits of data.
In the modes that do not have I-stream data
other than the specifier, the specifier itself will be
discarded. This code is used at all FORK entries.

INSTRUCTION BUFFER
4.3

Page 4-4

INPUT MULTIPLEXER

The input MUX is used to determine if data is to be loaded from the
shift multiplexer or the cache data.
The select of this MUX is
controlled individually for each 9 bit section. It is selected for
the shifter if the 9 bit section being shifted in is val d. Otherwise
it is selected for cache data.

4.4

BYTE ROTATOR

This hardware is located as one of the sources to the input MUX.
It
is controlled by the IB by the low order two bits of the IB address
register. These two bits will rotate the long word data such that the
byte address will specify which byte is in the low order 8 bits.
IBA

Byte Positions

INSTRUCTION BUFFER
4.5

Page 4-5

I-STREAM DATA MUX

One of the functions of the instruction buffer is to sort out
displacements, literals and other information and present it to the
CPU data path. The IB will do as much as possible to make the data be
in a useable form.
This implies sign extension and shifting where
necessary. To do this requires a decode of the mode, specifier,
context lookup and opcode.
For compatibility mode, the IDMX will be selected for either
and 2 or byte 0 shifted for branch displacements.
1.

-------------------------------------3

16 Bit Instruction

-------------------------------------1

ID BUS B3,B2
{SXT ON 83-7)

-----\/-----

16 Bit Displacement
16 Bit Literal

ID BUS BO
{SXT ON B0-7)

---\/-----

BR
OPCODE

---\/--8 BIT
BRANCH DISPLACEMENT

The branch displacement will be left shifted by one and sign
on bit 7. For VAX Mode The IDMX Will Be As Follows:
Mode

Data

Comment

S#
S#
S#
S#

7:0
7:0
7:0
7:0

Ze r o ex tended
Zero extended
Zero extended
Zero extended

(E)
R

(R)

-(R)

0
1

2
3
4

{R) +

-----\/-----

bytes

x
x
31:00

1,2, or 4 bytes depending
on context.

extended

Page 4-6

INSTRUCTION BUFFER
Sign extended.
@(R)+

31:00

@ DB

Sign extend
Sign extend
Sign extend
Sign extend

Sign extend on bit 7
Sign extend on bit 15

Dl6

@ Dl6

E
F

D32
@ D32

7:0
7:0
15:00
15: 00
31:00
31:00

8 Bit BDest
16 Bit BDest

7:0
15:0

on
on
on
on

bit
bit
bit
bit

7
7
15
15

Floating Short Literal
31

16 15 14 13 12 11 10 9 8 7 6 5 4

ID BUS

Zeros

I o I 11

I I I I I I I zeros I

Zeros

I
7
SPECIFIER

4.6

413 210

I OI OI EXP

IFRAI

PC UPDATES

PC Delta is a three bit number that is added to the low order bits of
the PC register.
The PDP-11 architecture has defined that each time a
length of I-stream is fetched, that the PC is updated to
reflect it.
This means that during displacement mode addressing off of PC, that
the PC is pointing at the end of the displacement.
In order to
eliminate an extra micro instruction on this flow, the hardware will
determine the length of I-stream data to be used and create a value to
be added
to the PC.
The end
result is that displacement mode
addressing can be done very quickly with the instruction buffer.
The PC update value will reflect the specifier (if any) and the length
of
I-stream required.
Addressing modes that require additional data
are:
Mode

89-

Length

A-

(R)+ if R=PC
@(R)+ if R=PC
DS

@ D8

CD-

@ Dl6

Dl6

Context Dependent
4 Bytes
1 Byte
1 Byte
2 Bytes
2 Bytes

INSTRUCTION BUFFER
E-

F-

D32
@ D32

Page 4-7
4 Bytes
4 Bytes

The complete number to be added to PC will include the length number
for
the addressing mode plus one for the specifier. Note that the
update for the opcode must be handled seperately by micro code.
Compatibility mode updates will work in a similar manner.
The
hardware will determine if any address calculation is required and the
mode.
If the following I-stream data is required, the number two will
be added to the PC.
If not, a zero will be added.
If a fault is detected such as error, TB miss or stall,
will force the PC update to be zero.

the

hardware

If the opcode is a single byte instruction, the update number will
zero.
If the decision point entry is to an execute flow, the
will be zero.

update

number

If first part done is set, the PC update will be zero.

4.7 · IR DECODE
The IR decode will be done by the use of Roms.
There are presently
eight major execution points that are using a hardware generated
address.
The evaluation of additional operands will be done by a
micro subroutine which is directed by a special subroutine call on the
specifier.
Additional
information such as context information and
register
addresses are obtained from the IR decode.
The register numbers will
be:
4 bits
4 bits
4 bits

SRC Reg from byte 1 (SPl ADR)
DST Reg from byte 2 (SP2 ADR)
SRC Reg latched from byte 1 (PRN ADR)

Note that the SRC register number will ~lways be valid and
the
destination register is an assumption of S or R specifier for byte l
followed by R specifier for the destination.
The register numbers
will be multiplexed
for compatibility mode versus VAX mode.
The
multiplexer will be A 745158 with (L)=l polarity.
The outputs will be
stable at CPUTO plus 27 N.S.
(Clock skew not considered.)

INSTRUCTION BUFFER
4.7.1

Page 4-8

The SRC register latched outputs will be clocked at CPU TO during the
MICRO state that does a execution point entry or a MICRO subroutine
call to a specifier evaluation. This will physically be done by the
MICRO control that bumps the specifier from byte 1.

4.7.1.1 Context Lookup - The context lookup information will also
come from a Rom. This implies that the context information will not
become available until CPU TO plus 100 NS from the time the execution
point, specifier or opcode has been changed. This information will
define:
byte
Word
Long
Float
Double
Quad
ASRC
VSRC

4.7.1.1.1 Specifier 1 Constant - This constant will be used by MICRO
code to do register updates for auto increment or auto decrement
modes. This will be done with 4 lines connected to the fast constants
multiplexer on the data path boards. The number generated for VAX
mode will be:
1 2 4 8 -

Byte
Word
Long/Float
Quad/Double

This will be generated
execution point entry.

from

the

context

lookup

table

for

each

During compatability mode, this number will be derived from a decode
of the instruction.
This constant is only selected during the
evaluation of the source operand. All single operand instructions and
register class instructions use SP2 constants.
The number generated will either be 1 or 2. A one is generated if it
is a byte instruction and ~he register field is not register six or
seven. A two is generated if it is a word instruction or byte
instruction with register six or seven.

INSTRUCTION BUFFER

Page 4-9

4.7.1.1.2 Specifier 2 Constant - This constant will be used by micro
code during compatibility mode flows. It is used for auto increment
or auto decrement address mode updates. The number generated will be
either one or two. A one is generated if it is a byte instruction and
the destination register is not register six or seven.
A two is
generate if it is a word instruction with destination register six or
seven.
During VAX mode, this number will be zero.

4.7.l.2 Data Length Field - A three bit field is generated from the
operand context table to control the UDT, scratch pad control or AMX
sign extention. The following numbers are generated.
l - 8 bit Data Type
2 - 16 bit Data Type
4 - 32 bit Data Type

(Byte)
(Word)
(Long, Float, Quad, Double)

Also generated is a signal that indicates the
either floating or double floating type.
determine condition code setting.

4.8

instruction
This will

opcode is
be used to

EXECUTION POINTS

Execution points are places in the micro flows where the IR decode
logic directs instruction execution. Execution point entries are of
two basic forms. The entry point will either evaluate an operand
specifier,
or
enter an execution flow unique to the present
instruction.
The mechenism for doing a execution point entry is by making the USUB
field equal to three. In order to make the instruction buffer do the
proper operation, the UIBC field must be set to F. In order to get
the PC at the correct valve, the UPCK field must be set to F. The
UMCT field must be set up to allow IB data to the ID BUS and the Q
register must be clocked.
This micro control selection will perform the necessary functions to
evaluate an operand specifier.
The Q register will receive any
literal, address or displacement data. The PC will be updated to
point to the beginning of the next specifier or opcode.
The
instruction buffer will advance over the data transferred into the Q
register.
If the entry was to an execution flow, the hardware will force the
update to be zero and the instruction buffer to hold.

INSTRUCTION BUFFER
4.9

Page 4-10

FIRST PART DONE

This is a flag that is set by micro code that indicates an interrupt
was taken during the middle of an instruction.
At the completion of
the interrupt service routine, the instruction is fetched a second
time.
Instead of evaluating specifiers again, the IR decode will
enter an execution flow.
This done by setting the execution point count to 7 with First Part
Done = 1. This implies that interruptable instructions have a maximum
of 7 execution points.
In order to get to the next instruction, the micro code must load a
new address into the IBA and flush the IB.
Before doing so, it must
clear First Part Done.

4.9.l

IB Addressing

The address registers for the instruction buffer memory cycles are
located
in the data path and translation buffer.
The data path holds
the virtual address of the IB.
The translation buffer has the
physical address for the IB.
The virtural address is used for two
reasons.
First is for error
reporting~
The other use
is when a page boundary is crossed.
The
virtural address is used to check the translation buffer for the new
page.
The physical address register
is loaded from the output of the
translation buffer.
After each reference, the address is incremented.
If a page boundary is not crossed, the address must still be valid.
If a
page boundary is crossed, the hardware forces a translation to
occur and the physical address is loaded.
If the translation fails,
the data locations are flagged
in the
instruction buffer.
When the code requests this data, a TB fault is
taken.
The code then interperts the cause.
Both the virtural and physical addresses count by 4 bytes at
The control of this counting is done by the IB.

time.

INSTRUCTION BUFFER
4.10

Page 4-11

CACHE INTERFACE

The interface to the cache is done with the MD BUS and several control
signals.

4.11

IB request H - Asserted when there is room to put data in the
instruction
buffer
and the address registers are not
counting.

IB READ DATA L - Asserted when data is to be loaded into
IB. It is inhibited during flush states.

Count H - Asserted during the micro state following a read
operation from cache to IB. It is used to count both the
virtural and physical address register.

the

ACCELERATOR INTERFACE

The interface to the floating point accelerator is done by tracking
the IR decode. The instruction opcode and the three bits of exe·cution
point count are sent to the FPA. The FPA will decode opcodes that it
wishes to operate on. The execution point count allows it to decide
when to jam the MICRO program into wcs.
The restriction to this
inter~ace
is that the FPA must follow the same combinations of
specifier evaluations and execution entries as the CPU. Also, no new
instructions that require specifier calculations can be implemented
without modification to the IR decode logic.
In order to do optimizations of register to register and short literal
to register, some additional information is passed:
1.

DST R Mode H - Indicates that specifier two
mode and R is not PC.

IMMED L - Indicates that specifier one is (PC)+.

VAX SL L - Indicates that specifier one is a short liTeral.

R Mode H - Indicates that specifier one is R mode
not PC.

and

BO VAL ( 1) H - Indicates that
contain val id information.

Bl VAL (1) H - Indicates that the specifier position in the
instruction buffer contains valid data. specifier are valid.

the

eight

(if

bits

any)

opcode

CHAPTER 5
INTERRUPTS & EXCEPTIONS

This chapter discusses interrupts, exceptions, machine halts
UTRAP function.

5.1

and

the

INTERRUPTS

Interrupts are the notification of events in the system which require
a change in the flow &f control and are generally independent of the
currently executing process. They are characterized by the following:

5.1. l

Interrupts always occur at the end of instructions or
well defined points of long iterative instructions.

during

Interrupts always push two long-words of state on either the
kernel or interrupt stacks consisting of the PSL and PC of
the next instruction.

Interrupts always cause the processor to raise its
Priority Level (IPL)
to that of the highest
Priority Request (IPR).

Interrupt
Interrupt

Interrupt Priority Level (IPL)

There are 32 IPL levels defined within the processor and for an IPR to
be serviced it must be greater than the IPL level of the current
process. The IPL is a five bit field in the Processor Status Longword
reg i st e r ( Ps L) •

INTERRUPTS & EXCEPTIONS

Page 5-2

There are several methods for changing the current IPL level:

5.1.2

An MTPR instruction is executed in kernel mode to the IPL
register.
This will load a 5 bit number defined in the
instruction operand into the IPL field of the PSL.

The IPL field of the PSL is loaded
execution of the REI instruction.

The IPL field is set to one if current IPL is zero and the
process is not executing on the interrupt stack (PSLIS=O) in
the execution of the SVPCTX instruction.

The IPL field is set to the highest Interrupt priority
request active (IPRA) level during the execution of the
interrupt sequence.

The IPL field is set to IPL IF (highest priority)
in the
execution of the exception sequence for Kernel Stack Not
Valid and Machine Check Faults.

from

the

stack

the

System Control Block

The system control block is a page in memory containing the vectors by
which Interrupts and Exceptions are dispatched to the appropriate
service routines. The system control block page is pointed to by the
System Control Block Base reg (SCBB) located in the internal processor
register space and accessed with the MTPR and MFPR instructions.
The processor micro code insures that bit 31 and bits 8 thru 0 of
SCBB are always loaded with zeroes.

5.1.3

the

Vectors

A vector is a longword in the system control block which is used to
point to the interrupt or exception service routine and which
describes how the event is to be serviced. The vector is formed by
adding the contents of the SCBB register to a nine bit hardware
generated vector which is dependent on the event being serviced.

INTERRUPTS & EXCEPTIONS

Page 5-3

The low two bits of the contents of the vector fetched from the system
control block contain a code which indicates how the event is to be
serviced as follows:
Code

5.1.4

Operation

Service event on the kernel stack unless
already on the Interrupt stack (PSL
IS=l)

Service event on the Interrupt stack

Service event in WCS. Bits 15:02 are
parameter to service routine

HALT

Interrupt Requests and their Vectors

Interrupt requests are sampled by the micro code during the execution
of each instruction and if the IPR level is greater than the IPL and
no exceptions occur during the instruction a branch at FORK A in the
flows is taken to the interrupt micro-code service routine. Each
interrupt request signal is a level which is sampled at CPT150 time in
certain micro-instructions and is then prioritized and the highest
priority request level is compared with the PSL IPL level.
The hardware will generate the nine bit interrupt dependent vector in
the Vedtor register which is available to micro-code but not to
macro-code software. For SBI or Unibus interrupts the micro-code
polls devices on the IPR level being serviced using the Interrupt
Summary Read command. A sub-level bit mask of devices with pending
interrupts at that IPR level is returned and written into the Vector
register. Bits 31 thru 16 are prioritized in the Vector register
according to lowest bit set has highest priority and are used to
generate the 9 bit vector when a device interrupt is being serviced.
Refer to section 1.7 , Registers used for Interrupt Servicing.
Interrupt priority request occur on 31 levels with IPR lF the highest
priority to IPROl the lowest. !PROO does not exist since the priority
request must be greater than the IPL level of the processor to be
serviced.
The following is a list of interrupt conditions and their
assigned vectors from highest priority to lowest priority.

INTERRUPTS & EXCEPTIONS

Page S-4

INTERRUPT PRIORITY REQUESTS

Level

Condition

IPR lF
IPR lE
IPR lD
IPR lC
IPR 18
IPR lA
IPR 19
IPR 18
IPR 17
IPR 16
IPR lS
IPR 14

NONE ASSIGNED
CPU POWER FAIL
CPU TIMEOUT
SBI FAULT
SBI ALERT
CRD/RDS
SBI SILO COMPARE
INTERVAL TIMER
SBI REQ7/UNIBUS BR7
SBI REQ6/UNIBUS BR6
SBI REOS/UNIBUS BRS
SBI REQ4/UNIBUS BR4
CONSOLE TERM. REC.
CONSOLE TERM. XMIT.
SOF'IWARE REQ OF
•
OE
OD
"

-----

IPR OF
IPR OE
IPR OD
IPR oc
IPR OB
IPR OA
IPR 09
IPR 08
IPR 07
IPR 06
IPR 05
IPR 04
IPR 03
IPR 02
IPR 01

Vector

------

---------

•
•
"
II

"
"n
•
"
"

•
"

OB
OA
09
08
07
06
05
04
03
02 or AST DEL.
01

60
SC
SS
S4

so
co

lCO-lFC
180-lBC
140-17C
100-13C
F8
FC
BC
BS
B4
BO
AC
AS
A4
AO
9C
98
94
90
SC
88
84

INTERRUPTS & EXCEPTIONS
5.1.5

Page 5-5

Description of Interrupt Conditions

5.1.5.l ·CPU Power Fail - This interrupt occurs if a power
fail
warning is received for the processor (AC LO) or from a critical
system element CSBI FAIL). Critical system elements include the SB!
Clock circuitry, SB! terminators, Bootstrap Memories or Main Memory
(in the standard configuration).
There will be a guaranteed 5
millisecs of good power after the assertion of this interrupt. This
interrupt may occur immediately after a power up sequence has begun;
however, at least 5 millisecs is guaranteed from the assertion of the
Power Fail until the possibility of a power up sequence.is allowed.
This interrupt is cleared
macro-code intervention.

hardware/micro-code

and

requires

5.1.5.2 CPU Timeout - This interrupt occurs if the processor attempts
to write data into a non-existing physical address or receives an ERR
confirmation on the SB! Bus for the second longword during an extended
read operation. This may be caused ,by software if the memory mapping
is incorrectly set up or by a hardware failure.
NOTE
CPU
timeout
interrupts
do
not
necessarily occur during the instruction
which caused them since the processor is
allowed to continue execution while an
SB! write cycle is pending.

No additional state information is saved on the stack other than the
PC and PSL at the time of the interrupt. Error status will be latched
in the SB! ERROR and SB! TIMEOUT ADDRESS registers. This interrupt is
cleared by macro-level software by a write ones to clear operation on
the CP TIMEOUT or IB TIMEOUT bits in the SB! ERROR register.

5.1.5.3 SB! Fault - The SB! Fault interrupt occurs if an SB! bus
error was detected by any device on the bus including the processor.
If the processor detects a fault condition which prevents the
completion of a read cycle for the CPU an exception condition is also
generated. Generally this appears as a Read Timeout Machine Check
exception.
This interrupt is cleared by macro-level software by clearing the
Fault Interrupt bit in the processor's FAULT/STATUS register which
also unlocks the Fault status in each device.
This interrupt will
occur only if enabled in that register.

INTERRUPTS & EXCEPTIONS

Page 5-6

5.1.5.4 SB! Alert - This interrupt occurs when a device which does
not contain SB! Request sequencing logic wishes to interrupt the
processor and may be caused by device power fail, device power up, or
dangerous environmental conditions in the device. Currently main
memories in non-standard configurations use this interrupt to report
changes in it's power status.
This interrupt is cleared by macro-level software by clearing
Alert status bits in each device's configuration register.

the

5.1.5.5 CRD/RDS - The Corrected Read Data (CRD) interrupt is asserted
if the processor received read data which had been corrected by main
memory. The Read Data Substitute (RDS) interrupt is asserted if the
processor received uncorrected read date on a read cycle to the
Instruction Buffer. If during the execution of instructions from the
Instruction Buffer a change in program flow is encountered (branch,
jump, etc.) before the bad data is used this interrupt will remain
asserted.
However, if an attempt is made to use the bad data an
exception will occur and the RDS interrupt removed.
These interrupts occur only if enabled in the processor's SBI ERROR
register and must be cleared by macro-level software by writing ones
to clear to the CRD,RDS, or IB RDS bits in that register.
Additionally the software must clear the error condition in the memory
configuration register if continued logging of errors and recording of
address information is desired.

5.1.5.6 SBI SILO Compare - This interrupt occurs when a match is
detected on particular signal fields of the SBI bus. The signal field
being checked can be program selected by control bits in the SILO
COMPARATOR register.
The previous 15 cycles on the SB! bus will be
latched in the SILO register for interrogation by software.
This interrupt will occur only if enabled in the SILO COMPARATOR
register and must be cleared by macro-level software by writing a one
to clear to the Silo Lock bit in that register.

5.1.5.7 Interval Timer - This interrupt will occur when the Interval
Count register overflows. This interrupt will occur only if enabled
in the Clock Control Status register and must be cleared
by
macro-level software by writing the Interrupt Request bit in that
register.

INTERRUPTS & EXCEPTIONS

Page 5-7

5.1.5.8 External Device Interrupts - External device interrupts occur
at IPR 17 to IPR 14 and correspond to SB! REQ7/UNIBUS BR7 to SBI
REQ4/UNIBUS BR4 levels respectively.
These
interrupts result from
device completion, device errors, and important device status changes.
When an external device interrupt is being serviced in micro-code the
processor will issue an Interrupt Summary Read command at the serviced
level to poll devices with pending interrupts at that level.
A bit
pair mask is returned on bits 31, 15 to bits 17, 01 indicating devices
needing service.
·
The hardware/micro-code will prioritize the returned data according to
lowest bit set is highest priority and generate an interrupt vector
for that level and highest priority device.
Generally, device interrupts must be enabled and always
macro-level software intervention to clear the interrupt.

require

5.1.5.9 Console Terminal Interrupts - The console terminal receive
interrupt occurs when the Done bit in the RXCS register is set.
The
interrupt enable bit must be set in that register for the interrupt to
occur.
The console terminal transmit interrupt occurs when the RDY bit in the
TXCS register is set.
Likewise, the interrupt enable bit must be set
in that register for the interrupt to occur. The receive interrupts
has higher priority than the transmit interrupt.
These interrupts are cleared by hardware/micro-code
macro-code intervention.

and

requires

5.1.5.10 Software Interrupts - There are
15
interrupt
priority
requests for use by the software, IPR OF to IPR 01.
The Software
Interrupt Summary Register (SISR) contains l's in bit positions 15
thru 01 corresponding to levels IPR OF to IPR 01 respectively with
pending interrupts.
Bits 20 thru 16 of the SISR contain the level of
the highest interrupt priority request active
(IPRA) of both the
hardware and software levels.
Macro-level software may book a request by using the MTPR instruction
and writing a bit per request desired to the SISR or by writing the
level number of a request to the Software Interrupt Request Register
(SIRR).
Using the SIRR register to book a software request is
preferred since it will not inadvertently clear other requests
pending.
Writing the SISR main1y occurs when restoring state
information after a power fail.
Micro-code will interpret writes to the SIRR as a bit set operation to
the SISR.
The mask generator in the CPU data paths can be used to
decode the request level.desired.

INTERRUPTS & EXCEPTIONS

Page 5-8

During the execution of the REI instruction the micro-code compares
the current mode bits in the new PSL image with the asynchronous
system trap level (ASTLVL) in the ASTR register.
If the two bit
current mode is greater than the three bit ASTLVL an AST is delivered
at IPR02. This is performed by the micro-code doing a bit set to the
SISR before completing the execution of REI.
The micro-code/hardware will clear the software interrupt level being
serviced by reading the SISR to determine the priority (IPRA),
decoding the level in the mask generator of the data paths, and
performing a bit clear ope~ation in the SISR. No macro-level software
intervention is required.

5.1.6

UWORD Control for Interrupts

There is a two bit Uword field designated Uword Interrupt and
Exception control (UIEK) which is used to monitor and acknowledge
interrupt conditions. The functions available are as follows:
UIEK
0

NO-OP
Interrupt Strobe (ISTR)
Interrupt Acknowledge (IACK)
Exception Acknowledge (EACK)

2
3

5.1.6.1 Interrupt Strobe - The ISTR function is used to clock the
state of interrupts at IPR lF to IPRlrr and cause a new priority
arbitration to occur. This is genrally done in the state prior to
returning to the IRD state so that the Interrupt branch can be
performed at Fork A.
During the execution of long iterative instructions the ISTR function
is used to periodically monitor Interrupt activity and to allow a
subsequent micro branch to be performed on the Interrupt signal.

5.1.6.2 Interrupt Acknowledge - The IACK function is used to clear
the Power Fail, Console Term. Rec, and Console Term Xmit interrupts
when they are being serviced by the micro-code routine.
In addition
the PSL is set to a predetermined state as follows:
PSL:

CMP
TP
FPD
IS

<-- 0
<-- 0
<-- 0
<-- IS

INTERRUPTS & EXCEPTIONS
CUR MOD
PRV MOD
IPL
DV
FU
IV
T
N

5.1.7

Page 5-9

<-- 0 (KERNEL)
<-- 0 (KERNEL)
<-- IPRA (IPR being serviced)
<-- 0
<-- 0
<-- 0
<-- 0
<-- 0
<-- 0
<-- 0
<-- 0

Registers used for interrupt servicing

5.1.7.1

Interrupt priority level register= IPLR -

Processor Reg (PR) Address - 12
Internal Data bus (ID) Address - not an ID reg.
31

5 4

' <--------------------------------------------> 0 'I
'
'
I 0

BITS
IPL

5.1.7.2

I
I
I
I o I o I
I
I
I

IPL

COMMENTS

Interrupt Priority Level

IPL field of PSL
read/write

System control block base register= SCBB -

PR Address
ID Address
31

NAME

11
38

9 8
PFN

I
I
I O<---------~--->O I
I
I

INTERRUPTS & EXCEPTIONS

5.1.7.3

Page 5-10

COMMENTS

BITS

NAME

PFN

Page Frame Number

Holds the base physical
address of the system control
block page. Zero bits are
always forced to zero when
written. read/write

Vector register, VECTOR -

PR Address - Not available to software
ID Address - D
31

25 24

I
I
I O<->O I PRIOR
I
I VAL

16 15

21 20

I
PRIOR I

NUMB
ONES

9 8

I
I
I O<--------->O I
I
I

VECTOR

BITS

NAME

COMMENTS

PRIOR
VAL

Priority Valid

Indicates at least one
bit was set when the last
PRIOR field was determined.
Read only.

PRIOR

Priority Encode

The priority encoded value
of the last bit mask
written into bits 31 to 16
of the VECTOR register.
Bit 31 represents the lowest
priority {PRIOR=F) and
bit 16 the highest (PRIOR=O).
Used to form the Vector,
bits 8:0 when IPRA
indicates an external
interrupt. Read Only.

NUMB
ONES

Number of Ones

The number of ones in the
data last written into the
Vector register bits 31 to 16.
Read only.

VECTOR

Interrupt Vector

A hardware generated
number determined by
IPRA. Read Only.

Page 5-11

INTERRUPTS & EXCEPTIONS
5.1.7.4

Asynchronous system trap level reg.

=ASTR -

PR Address - 13
ID Address - Not an ID address
31

3 2

I
I
I O<--------------------------------------------->O I
I
I

NAME

BITS
ASTLVL

5.1.7.5

ASTLVL

COMMENTS

Asynchronous System
Trap Level

Used to deliver AST interrupts
in REI execution. Read/Write

Software interrupt summary register= SISR -

PR Address - 15
ID Address - E
21 20

I
I
I O<----------------->O I
I
I

BITS

16 15

IPRA

I
I
I 0 I
OF<----------------->01 I
I

NAME

IPR

COMMENTS

IPRA

Interrupt Priority
Request Active

The level of the highest
priority interrupt pending
condition of the last
Interrupt strobe time
or write to SISR.
Read Only

IPR OF
to 01

Interrupt Priority
Request OF to 01

Software interrupt request
pending f 1 ag s.
Read/Write.

INTERRUPTS & EXCEPTIONS
5.1.7.6

Page 5-12

Software interrupt request

PR Address - 14
ID Address - Not an ID register

0
----------------------------------------·-----------------------I
I
I
I 0<--------------------------------------------------)0 I SIR I
I
I·
.I
4 3

5.2

BITS

NAME

SIR

Software Interrupt
Request

COMMENTS
The level of the request
t.at software wishes to
book in the SISR. An
SIR=O books no request.
Write Only.

EXCEPTIONS

Exceptions are the notification of events which force a change in the
flow
of
control
for the currently executing process.
Their
characteristics are as follows:
1.

Exceptions occur in the
instruction during which
detected.

middle or at -he end of
an
the exception condition had been

Exceptions always push two long-words of state on either the
kernel or interrupt stacks consisting of the PSL and PC of
the instruction (sometimes the PC of the next instruction).
Additionally up to 16 longwords of exception parameter
information may be pushed.

Exceptions generally do not change the processor's IPL level.
Only for Kernel Stack Not Valid and Machine Check Faults is
the IPL altered in which case it is forced to IPL lF (highest
priority).

Exceptions which occur while disabled do not cause an
exception when subsequently enabled. Arithmetic traps are
the only exceptions which can be disabled.

Page 5-13

INTERRUPTS & EXCEPTIONS
5.2.1

Classes of exceptions

Exceptions may fall into three categories depending upon when they
occur and how they leave the machine state. The three classes are
Traps, Faults, and Aborts.

5.2.1.1 Traps - A trap is an exception condition which occurs at the
end of the instruction. The PC saved on the stack is that of the next
instruction.

5.2.1.2 Faults - A fault is an exception which occurs in the middle
of an instruction, but which leaves memory and the general registers
in the same state as at the beginning of the instruction.
The PC
saved on the stack is that of the instruction in which. the fault was
detected so that the instruction may be restarted when the fault
condition is eliminated.

5.2.1.3 Aborts - An Abort is an exception which occurs in the middle
of an instruction but potentially leaves the registers and memory
indeterminate, such that the instruction
cannot
be
correctly
restarted.
The PC saved on the stack does not necessarily point to
the beginning of the next instruction.

5.2.2

Exception conditions and their vectors

Exception conditions are detected thru the use of
the micro sequencing control:

two

mechanisms

ubranches

a unique micro state is reached by performing a
test of an exception condition using the UBEN
field of the Uword or by using the special
micro call function to branch on a decision
point (DPT).

utraps

a hardware detected micro trap occurs which
alters the normal machine flow and causes
unique micro service routines to be executed.

Each of the micro service routines will manufacture the exception
vector called for using a generator set of constants from the UKMX
function of the Uword. Likewise, the micro service routines will put
together the necessary parameters to be saved on the stack from state
information stored within the processor registers.
Exception codes
will be furnished by the UKMX function.

INTERRUPTS & EXCEPTIONS

Page 5-14

The following is a list of exception conditions, their class, and
their assigned vectors.
In most cases the exception conditions are
·mutually exclusive; however, in cases of conflict the exception
condition detected by the utrap function will have higher priority.
EXCEPTION CONDITIONS

Condition

---------

MACHINE CHECK
KERNEL STACK NOT VALID
RESERVED DEC OPCODES&
PRIVILEGED INSTRUCTIONS
RESERVED CUSTOMER OPCODES
RESERVED OPERANDS
RESERVED ADDRESSING MODES
ACCESS CONTROL VIOLATION
TRANSLATION NOT VALID
TRACE TRAP
BPT OPCODE
COMPATABILITY MODE TRAP
ARITHMETIC TRAP
CHMK. OPCODE
CHME OPCODE
CHMS OPCODE
CHMU OPCODE

5.2.3

____

Class

04
08
10

FAULT/ABORT
ABORT
FAULT

14
18
IC
20
24
28
2C
30
34
40
44
48
4C

FAULT
FAULT/ABORT
FAULT
FAULT
FAULT
FAULT
FAULT
TRAP/ABORT
TRAP
TRAP
TRAP
TRAP
TRAP

Vector
_.._

-----

Description of exception conditions

5.2.3.1 Machine check - Raises IPL to IF - Machine check exceptions
push additional parameters onto the stack to assist in the evaluation
of the condition causing the abort. Refer to Chuck Mathis' MACHINE
CHECK DESCRIPTION AND SPECIFICATION for a list of the parameters.

5.2.3.1.l Read timeout - Read timeouts occur wh~n the processor
performing a read or interlock read command on the SBI bus.
This exception is detected by the utrap function for data path
and by the ubranch function for IBUF cycles.

cycles

INTERRUPTS & EXCEPTIONS

Page 5-15

5.2.3.1.2 Read data substitute - Read Data Substitute errors occur
when the processor is performing a read or interlock read on the SBI
bus and the memory has returned uncorrected read data.
This exception is detected by the utrap function for data path
and by the ubranch function for IBUF cycles.

cycles

5.2.3.1.3 Translation buffer parity error - TBUF parity errors occur
when the processor is performing a virtual address reference and
memory mapping is enabled and a parity check on the translation buffer
indicates an error.
This exception is detected by the utrap function for data path
and by the ubranch function for IBUF cycles.

cycles

5.2.3.1.4 Cache parity error - Cache Parity errors occur when the
processor is performing a read memory reference and a parity check of
the cache indicates an error.
This exception is detected by the utrap function for data path
and by the ubranch function for IBUF cycles.

cycles

5.2.3.1.5 Control store parity error - This error condition occurs
when
the
micro
machine detects a parity error in the next
micro-instruction and may cause a Machine Check Abort at any time
(including during the halt state while in console wait).
This exception is detected by the utrap function.

5.2.3.1.6 Illegal Machine Sequence Error - This
error
condition
occurs if an illegal micro-instruction is reached and will generally
indicate a hardware failure in the instruction decode circuitry.
This exception is detected by the ubranch function.

INTERRUPTS & EXCEPTIONS

Page 5-16

5.2.3.2 Kernel stack not valid - Raises IPL to lF - This exception is
reported if a Translation Not Valid or Access Control Violation Fault
would have occurred while pushing onto the Kernel stack in the
exception, interrupt, or CHMX micro flows.
The vector for this
exception should define servicing on the interrupt stack.
No additional parameters are pushed for this
exception is detected by the ubranch function.

exception.

This

5~2.3.3

Reserved DEC o~codes & priv. instr - Reserved Dec Opcodes are
the following:
36, 3 , 57 to SF, 77, EF, FD to FF. Privileged
Instructions are the following:
Not Kernel Mode and HALT, MTPR, MFPR,
LDPCTX, SVPCTX.
No additional parameters are pushed for this
exception is detected by the ubranch function.

exception.

This

5.2.3.4 Reserved cust opcodes - Reserved Customer Opcodes are FC. No
additional parameters are pushed for this exception. This exception
is detected by the ubranch function.

5.2.3.5 Reserved operands - No additional parameters are pushed onto
the stack.
The RSVD OPERAND type can be determined by the OPCODE
pointed to by the pushed PC.

5.2.3.5.1 Illegal floating number= Fault - A floating
sign=l and exponent=O.

operand

with

Occurs in: MOVF, MOVD, MNEGF, MNEGD, CVTFX, CVTDX, CVTRFL, CVTRDL,
CMPF, CMPD, TSTF, TSTD, ADDF(2,3), ADDD(2,3), SUBF(2,3), SBUD(2,3),
MULF(2,3), MULD(2,3), DIVF(2,3), DIVD(2,3), EMODF, EMODD, POLYF,
POLYD, ACBF, ACBD.
This exception is detected by the utrap function when the
calls for - Check Float Operand.

UMSC

field

5.2.3.S.2 Bit field too wide - Fault - Size operand is greater than
32 or less than 0 or when the-bit field is located in a register with
position operand greater than 31 or less than O.

INTERRUPTS & EXCEPTIONS

Page 5-17

Occurs in: EXTV, EXTZV, INSV, CMPV, CMPZV, FFC, FFS, BBS, BBC,
BBSC, BBCS, BBCC, BBSSI, BBCCI.

BBSS,

This exception is detected by the ubranch function.

5.2.3.5.3

Illegal entry mask - Fault - Unspecified

Occurs in:

CALLG, CALLS

This exception is detected by the ubranch function.

5.2.3.5.4 PSW MBZ FIELD not zero - Fault - Bits 15:08 of the new
value is non-zero.
Occurs in:

PSW

RET, BISPSW, BICPSW

This exception is detected by the ubranch function.

5.2.3.5.5 Illegal PCB entry - Abort - The MBZ fields
and PCB+92 are non-zero.
Occurs in:

the

PCB+84

LDPCTX

This exception is detected by the ubranch function.
The PC pushed on the stack points to the opcode.

5.2.3.5.6 Illegal PSL image - Fault - The new PSL from the stack
not have the correct format.
Occurs in:

did

REI

This exception is detected by the ubranch function.

5.2.3.5.7 Illegal processor reg - Fault - The
register address does not exist.
Occurs in:

internal

MTPR, MFPR

This exception is detected by the ubranch function.

processor

INTERRUPTS & EXCEPTIONS

Page 5-18

5.2.3.5.8 Decimal string too long= Fault - Length operand is greater
than 31 or less than o.
Occurs in: MOVP, CMPP(3,4), ADDP(4,6), SUBP(4,6), MULP, DIVP,
CVTPL, CVTPN, CVTNP, ASHP.

CVTLP,

This exception also occurs if an invalid numeric
character other than 0 thru 9) is encountered.

ASCII

Occurs in:

digit

(an

CVTNP

This exception is detected by the ubranch function.

5.2.3.5.9 Reserved pattern operator - Fault - More input digits or
less input digits are requested by the pattern than are specified or
an unimplemented or reserved pattern operator is encountered.
Occurs in:

EDITPC

This exception is detected by the ubranch function.
The PC pushed on the stack points to the opcode.

5.2.3.6 Reserved addressing modes - Fault - One of
the
following
addressing modes was encountered aur1ng the evaluation of an operand
specifier:
Specifier

Situation Illegal

Short Literal Mode

Modify, write, address source, or withiri
index mode.

Address source, or within index mode.

Index Mode

Within index mode, or with PC as index.

No additional parameters are pushed for this exception.
This exception is detected by the ubranch function.

5.2.3.7 Access control violation - Fault - The exception occurs when
the processor is performing a virtual reference and the protection
code for that page found in the translation buffer does not allow
access for the type of reference being performed (read or write). In
the current mode (Kernel, Exec, Super., or User).

INTERRUPTS & EXCEPTIONS

Page 5-19

An access control violation also occurs if during the translation
process the micro-code discovers that the page frame number of the
Virtual Address CVA(29:09) for per process address space and VA(30:09)
for system address space) is outside the bounds as specified in that
address space's length register.
Additional parameters pushed include:
1.

Virtual Address

- VA reg. for data path cycles & VIBA for
IBUF cycles.

Fault Parameter

- location in microflows & ubranch.

I
I WRITE OR
I O<--------------------->O I MODIFY
I
I ACCESS

REFERENCE I
LENGTH I
TO
I VIOLATION I
PTE
I OCCURRED I

The protection violation is detected by the utrap function for data
path cycles and the ubranch function for IBUF cycles. The length
violation is detected by the ubranch function and the virtual address
is always located in VA.

5.2.3.8 Translation not valid - Fault - The exception occurs when the
processor is performing a virtual reference and if during the
translation process (due to a TBUF miss utrap) an invalid page table
entry (VALID bit=O in PTE) is encountered.
Additional parameters pushed include:

Virtual Address

- VA register.

Fault Parameter

- location in microflows & ubranch.
03

I
I WRITE OR
I O<--------------------->O I MODIFY
I
I ACCESS

01
REFERENCE
TO
PTE

The translation proc~ss is begun by the utrap function for data path
cycles and by the ubranch function for IBUF cycles. If an IBUF cycle
needs translation then the VIBA is placed in the VA register and the
process begun.
If during the translation process this exception is
detected by the ubranch function the VA register always contains the
correct virtual address.

INTERRUPTS & EXCEPTIONS

Page 5-20

5.2.3.9 Trace trap - TRAP - This exception occurs at the end of every
instruction which has-t°he T bit in PSL set at the beginning of the
instruction.
If enabled this trap must occur even if exception or
interrupts occur for the instruction being executed.
The following instructions handle Trace Traps in special ways:
RET, CHMX, REI, BISPSW, & BICPSW, CALL
The trap occurs at Fork A using the ubranch function if the trap
pending TP bit in PSL was set Upon entering the IRD micro-state. At
the end of the IRD micro-state the T bit is sampled and if set the TP
bit is set. Microcode can set or clear TP and T during the execution
of instruction which handle Trace Traps in a special way to get the
proper results.
No additional parameters are pushed for this exception.

5.2.3.10 BPT opcode= FAULT - This trap occurs when the BPT opcode is
encountered in the instruction stream.
No additional parameters are pushed.
This condition is detected by the ubranch function.

5.2.3.11 Compatability mode trap - TRAP/ABORT - This trap occurs when
a
reserved opcode or an illegal instruction is encountered when
executing instructions in compatability mode. The following is a list
of opcodes (in octal) which trap:
HALT, WAIT, RESET, SPL, MARK, FADD, FSBU, FMUL, FDIV, 17XXXX, 000007,
000077, 000210 to 000227, 007000 to 007777, 075040 to 076777, 1064000
to 106477, 106700 to 107777, IOT, BPT, EMT, TRAP, JMP*DMO, JSR*DMO.
In addition a Compatability mode Abort may occur if an odd address
error is detected during the following memory references when in Comp.
Mode:
1.

Any reference with VAOO=l and not a
executed.

byte

instruction

Any opcode fetched from an unaligned word address.

being

INTERRUPTS & EXCEPTIONS

Page 5-21

The address fetch in the evaluation of addressing modes 3, 5,
and 7.

The index word fetch in the evaluation of addressing modes
and 7.

Additional parameters pushed include:
1.

Trap Code:

to
11

- location in micro-flows
RSVD or Illegal Opcode
IOT opcode
BPT opcode
EMT opcode
TRAP opcode
ODD ADDRESS ERROR

12
f3
14
15

Detection of the special opcodes for this exception
with the ubranch function and will result in a Trap.

accomplished

Odd address errors are detected using the utrap function and will
cause an ABORT since the PC pushed onto the stack is not necessarily
that of the next instruction and that the instruction cannot be
restarted.

5.2.3.12 Arithmetic trap - TRAP - This trap occurs when an overflow
or
underflow
condition
is
detected during the execution of
instructions and the particular trap condition for that instruction
has been enabled by the DV, FU, and IV enable bits in the PSL. The
instruction is always completed.
The following
indicated:
1.

trap

conditions

are

detected

for

the

instructions

Integer Overflow - Enabled by IV
Occurs in: MNEG B,W,L; CVT WB,LB,LW; ADD 8(2,3), W(2,3) I
L(2,3);
INC B,W,L; ADWC; SVB 8(2,3), W(2,3), L(2,3); DEC
B,W,L; SBWC;
MUL 8(2,3), W(2,3), L(2,3);
DIV 8(2,3),
W(2,3), L(2,3);
EDIV;
ASHL;
ASHQ;
CVTF B,W,L; CVTD
B,W,L; CVTRFL; CVTRDL; EMODF; EMODD; ACB B,W,L; AOBLEQ;
AOBLSS; SOBGEQ; SOBGTR; CVTPL.

Integer Divide by zero - Always Enabled
Occurs in:

DIV 8(2,3), W(2,3), L(2,3);

EDIV

INTERRUPTS & EXCEPTIONS
3.

Page 5-22

Floating Overflow - Always Enabled
Occurs in: CVTDF; ADD F(2,3), D(2,3); SUB F ( 2, 3) , D(2,3);
MUL F(2,3), D(2,3); DIV F(2,3), D(2,3); PLOY F,D; ACB F,D.

Floating Divide by Zero - Always Enabled
Occurs in:

DIV F(2,3), D(2,3).

Floating Underflow - ENabled by FU
Occurs in: ADD F(2,3)' D(2,3);
SUB F(2,3)' D(2,3);
MUL
F(2,3), D(2,3);
DIV F(2,3), D(2,3); EMOD F,D; PLOY F,D;
ACB F,D.

Decimal Overflow - Enabled by DV
Occurs in: EDITPC;
ADDP(4,6);
CVTLP; CVTPN; CVTNP; ASHP;

SUBP ( 4, 6);

MULP;

DIVP;

Decimal Divide by Zero - Always Enabled
Occurs in:

DIVP

Additional parameters pushed include:
1.

Trap Code:

fl
#2
f3
#4
#5
#6
#7

- CPU ERROR/STATUS REG
Integer Overflow
Integer Divide by Zero
Floating Overflow
Floating Divide by Zero
Floating Underflow
Decimal Overflow
Decimal Divide by Zero

This trap is detected by the ubranch function.

5.2.3.13 CHMX opcodes - At the completion of execution of
CHME, CHMS, and CHMU instructions a trap is performed.
Additional parameters pushed include:
1.

Sign extended operand - D register.

This trap is detecied by the ubranch func~ion.

the

CHMK,

INTERRUPTS & EXCEPTIONS
5.2.4

Page 5-23

Acknowledging exceptions

Most of the exception conditions do not require special action by the
micro-code to complete the exception service code. Certain errors,
arithmetic traps, and trace traps do, however, require special
servicing.

5.2.4.1 Error acknowledging - The micro-code must clea~ the.following
error status bits in the indicated register for error logging to
continue.
1.

Read Timeout - SBI ERROR REG.

READ DATA SUBSTITUTE - SBI ERROR REG.

TBUF PARITY ERROR - TBl REG.

CACHE PARITY ERROR - CACHE PARITY ERR REG.

CS PARITY ERROR - CPU ERR/STATUS REG.

5.2.4.2 Arithmetic trap acknowledging - The micro-code must
clear
pending arithmetic traps after they are serviced or when other
exceptions occur, particularly those which restart the instruction.
The method for clearing these conditions will be by writing zeroes
the trap code in the CES register.

5.2.4.3 Trace trap acknowledging - The micrQ-code must clear the TP
bit in the PSL to allow the next instruction to be executed without
another Trace Trap occurring first.
In order that exception conditions can properly be serialized the TP
bits must be set to the proper state when pushing the PSL on the stack
if a Trace Trap is pending while servicing other exceptions.

INTERRUPTS & EXCEPTIONS

Page 5-24

5.2.4.4 UWORD control for exceptions - The UIEK field of the UWORD
provides an exception acknowledge function (EACK) which sets the PSL
into the following state:
PSL:

CMP
TP
FPD
IS
CUR MOD
PRV MOD
IPL
DV
FU
IV
T
N

z
v
c

5.3

<-- 0
<-- 0
<-- 0
<-- IS
<-- KERN
<-- CUR MOD
<-- IPL
<-- 0
<-- 0
<-- 0
<-- 0
<-- 0
<-- 0
<-- 0
<-- 0

MACHINE~HALTS

The halt state of the machine is defined as the micro-machine being in
the CONSOLE WAIT state and responding only to console commands. · If an
exception occurs while executing any console command or while in the
Console Wait state an exception routine will be initiated in which a
branch is performed on a CONSOLE COMMAND MODE flag to prevent pushes
to the stack.

5.3.1

Halt conditions

5.3.1.1 Halt Instruction - If a HALT instruction is executed while in
Kernel Mode (PSL CURMOD=O) the machine halts.

5.3.1.2 CNSL halt - At any tim~ during the execution of instructions
the console may request that the machine come to a HALT. This is
performed by a CNSL HALT REQUEST being asserted and serviced as an
interrupt which does not push onto the stack nor change the IPL level.
A CNSL HALT is serviced below Exceptions and above all other
Interrupts and only at the end of instructions.

INTERRUPTS & EXCEPTIONS

Page 5-25

5.3.1.3 CHMX instructions - If a
CHMK,
CHME,
CHMS,
or
CHMU
instruction is encountered and the IS bit in PSL=l then the machine
comes to a halt before any execution of the instruction occurs.

5.3.1.4 Interrupt stack not valid - If a Translation Not Valid or
Access Control Violation Fault would have occurred while pushing onto
the Interrupt stack in the exception or interrupt micro code service
flows a machine halt occurs with INTR STACK NOT VALID repor~ed.

5.3.1.5 Halt code from vector - If an Interrupt or Exception occurs
and the halt code is found in the Vector location then the CPU will
halt after pushing the appropriate parameters onto the stack.

5.4

UTRAP FUNCTION

During the execution of micro-instructions the hardware detects
certain error conditions and initiates a trap in micro-code to one of
several service flows. The micro-PC is pushed onto the micro stack so
that certain micro processes can be continued.

5.4.1

UTRAP conditons and their vectors

The following is a list of conditions and
(first is highest) which cause a utrap:
CONDITION
1.
2.

3.
4.
5.
6.
7.
8.

SYSTEM !NIT
ERRORS:
CS PARITY
ODD ADDRESS
TIMEOUT
READ DATA SUBSTITUTE
CACHE PARITY ERROR
TBUF PARITY ERROR
RESERVED FLOATING OPERAND
TBUF MISS
PROTECTION VIOLATION
MBIT
PAGE BOUNDARY
UNALIGNED DATA

their

VECTOR
100
lOF
lOE
lOD
lOC
108
107
106
105
104
103
102
101

relative

priority

Page 5-26

INTERRUPTS & EXCEPTIONS
5.4.2

Description of utrap conditions

5.4.2.l System Init - DC LO is
received from thesBI bus.

asserted

for

the

CPU

DEAD

5.4.2.2 Errors - Description of errors can be found in
on Exceptions.

the

sections

5.4.2.3 Reserved Floating Operand - This condition occurs when the
UMSC field of the Uword has the CHECK FLOAT OPERAND function and
ALU15=1 with ALU(l4:07)=0.

5.4.2.4 TBUF Miss - This occurs when the processor is doing a virtual
reference----wlt'fliii'emory mapping enabled (MME=l) and there is no address
translation in the TBUF.

5.4.2.5 Protection Violation - This occurs when the processor is
doing a virtual reference with memory mapping enabled (MME=l) and the
TBUF entry indicates the page being referenced is protected from the
mode and reference type being used.

5.4.2.6 MBIT - This occurs when the processor is doing a virtual
write reference with memory mapping enabled (MME=l) and the TBUF entry
indicates the the page should be marked as being modified.

5.4.2.7 Page Boundary - This occurs when the processor is doing a
virtual reference with memory mapping enabled (MME=l) and the data
The micro-code
type will cause a reference across a page boundary.
will then probe the next page to insure that a Translation Not Valid
or Access Violation Fault will not occur.

5.4.2.8 Unaligned Data - This occurs when the processor is doing any
memory reference and the data type indicates a second reference is
required. Quad and Double data types are treated as two sequential
longword references so that two UNALIGNED DATA uTRAPS will.occur if
the data is not on a longword boundary.

INTERRUPTS & EXCEPTIONS
5.5

Page 5-27

SERIALIZATION OF EVENTS AT FORK A

The first decision point branch after the I~D state is used to perform
Arithmetic and Trace Traps occurring for the previous instruction. In
addition console halt requests and Interrupts are sampled. If one of
these conditions are to be serviced the PC must be backed up since it
was advanced in anticipation of executing the next instruction.
The following list is the priority of branches taken at Fork A so that
the proper tr~p and interrupt sequencing can occur.
Highest listed first:
1.

ARITHMETIC TRAP

CNSL HALT REQUEST

INTERRUPT

TRACE TRAP

IBUF STALL

IBUF ERRORS

OPCODES & SPECIFIERS

CHAPTER 6
MACHINE CHECK ABORT/FAULT/HALT

.,.1 MACHINE CHECKS
A machine check function can be initiated by a hardware forced
micro-trap, by the micro-code's testing for an I-buffer error on a
·memory reference, or by the firmware detecting a sequencing error.
A machine check can be caused by any one of the following conditions:
CONTROL STORE PARITY ERROR This condition occurs when the hardware detects a control store
parity error while reading a micro-word. A micro-trap is used to
initiate the error handling micro-code.
READ DATA SUBSTITUTE Read data substitute (RDS) errors occur when the processor is
performing a read or interlock read on the SBI bus and the memory
has returned uncorrected read data.
TRANSLATION BUFFER PARITY ERROR TBUF parity errors occur when the processor is translating a
virtual address for a virtual memory reference (MME=l) , and a
parity error occurs on data read-out of the translation buffer.
CACHE PARITY ERROR CACHE parity errors occur when the processor is performing a read
memory reference and a parity check is detected on data read out
of the cache •.

MACHINE CHECK ABORT/FAULT/HALT

Page 6-2

READ TIMEOUT/SB! ERROR CONFIRMATION Read timeouts and Error Confirmations occur when the processor is
performing a read or interlock read command on the SBI bus and an
SBI Error is detected as there is no response to the processor's
read memory or I/O read reference.
NOT SUPPOSE-TO-BE-HERE When micro-code detects it
has
arrived
at
an
illegal
micro-address, it pushes that address onto the micro-stack and
transfers control to the error handling micro-code.
The IPL is raised to "lF" when any one of the above conditions occur.
On CP memory reference errors, micro-traps are used to initiate the
error handling micro-code. On I-Buffer memory reference errors, the
micro-code detects on specifier evaluations the error and transfers
control to the error handling micro-code.
See the "INTERRUPTS & EXCEPTIONS SPECIFICATION", Rev. B for addition
details on the hardware implementation of the above micro-traps and
"IBUF SPECIFICATION" for hardware specs for the micro-branch on IBUF
memory reference errors.

6.2

INSTRUCTION ABORTS

Instructions are aborted on the following cases:

Control store parity error micro-traps

Error occurs during memory management micro-code

Error occurs during interrupt or exception micro-code

"Not suppose to be here•, detected by micro-code.

The "NESTED ERROR" flag is used by users of the memory management
micro-routines to tell the error handling micro-code to do an abort
sequence.

MACHINE CHECK ABORT/FAULT/HALT
6.3

Page 6-3

INSTRUCTION FAULTS

On RDS, TBUF parity error, CACHE parity error, or a READ TIME
OUT/ERROR Confirmation;
the instruction being executed (or setup}
will be faulted if an abort or halt situation does not exist.
This will allow selected instructions to be retryed by the operating
software. For the instructions that are retryable, see Appendix A.
The "EFP" (Error First Pass) flag is left set on faults and must be
reset by the operating software before continuing. Manually writing
zeros to ID[SBI FAULT] clears it, and software can reset it using the
MTPR (---0) instruction. It is also cleared by system initialization.
(If it is not cleared, the CPU will be halted on the next machine
check) •

6.4

INSTRUCTION HALTS

The instruction being executed (or setup) will be halted if,

Processor is in Console Mode.

"EFP" (Error First Pass) flag is set on entry
handling micro-code.

A memory error occurs while attempting to push parameters on
the kernel or interrupt stack.
(Write timeout or Error
Confirmation)

The "EFP" (Error First Pass) flag is set and tested
handling micro-code to determine the halt situation.
R/W bit in the "SBI FAULT" status register, bit 25.

6.5

the

error

by the error
This flag is a

ERROR LOGOUT

On Machine Checks, the Error Handling micro-code will attempt to log
out the relevant status registers and the VA Register as parameters on
the stack selected by the Machj ine Check Exception Vector.
(Suggest
that software always use Interrupt stack to keep from losing error
information if stack is not resident or valid.)
Also two additional longword parameters are pushed on the stack
are:

which

Page 6-4

MACHINE CHECK ABORT/FAULT/HALT
SUMMARY PARAMETER:
BYTEtO,

Identification of the machine check
fault/abort sequence.

that

initiated

the

CODE
00 - CP READ TIMEOUT/SB! ERROR CONFIRMATION FAULT
02 - CP TBUF PARITY ERROR FAULT
03 - CP CACHE PARITY ERROR FAULT
05 - CP RDS FAULT
OA - IB TBUF PARITY ERROR FAULT
OC - IB RDS FAULT
OD - IB READ TIMEOUT/SB! ERROR CONFIRMATION FAULT
OF - IB CACHE PARITY ERROR FAULT
Fl - CS PARITY ERROR ABORT
F2 - CP TBUF PARITY ABORT
F3 - CP CACHE PARITY ERROR ABORT
F4 - CP READ TIMEOUT/SB! ERROR CONFORMATION ABORT
FS - CP RDS ABORT
F6 - CP "NOT-SUPPOSE-TO BE HERE" ABORT
BYTEfl,

Flag noting that a CP timeout or
interrupt was pending.
This flag will be set
interrupt was pending.

Error

non-zero

Confirmation

value

this

The operating software must examine the previously logged
out parameters to determine and handle these error
interrupts. (This possible pending interrupt has been
cleared in order to handle the machine check sequence.
The logged-out information is the only record that it was
pending) •
·
BYTES 3&4 - MBZ
LENGTH PARAMETER
BYTEfO,

Number of bytes logged out exclusive of this parameter

BYTES 11-3 MBZ
The layout and contents of the logout area on the stack as follows:

MACHINE CHECK ABORT/FAULT/HALT

Page 6-5

( 1)

28
(HEX)

I
(2) I
I

I
I
I

SUMMARY PARAMETER

---------------------------------------'
,
.I

C3)

CES

( 4)

TRAPPED UPC

(5)

VA/VI BA

(6)

(7)

TB ERO

(8)

TBERl

(9)

TIME.ADDR

(10)

PARITY

(11)

SBI. ERR

(12)

( 13)

PSL
ERROR LOGOUT AREA MAP/SP

SP:

MACHINE CHECK ABORT/FAULT/HALT
6.6

Page 6-6

INITIALIZATION OF CP, TBUF, CACHE, & SBI STATUS REGISTERS

The following status registers are initialized by the
micro-code.

Error

Handling

TBUF ERROR REG! (TBERl) Register is written to clear accumulated TBUF parity error
information & FLUSH IB microrder is used to clear IB errors.
SB! ERROR REG (SBI.ERR) A one is written to CP Timeout also to clear CP Timeout
Error Confirmation.

and

CPU

FLUSH.IS is used to clear I-Buffer errors.
Writing to CP timeout also unlocks the timeout address register.
CACHE PARITY REG (PARITY) Contents of this register are written to itself to clear
cache parity error bit. (Write one to clear type bit.)

6.7

the

CPU/CONSOLE INTERFACE STATE

Console Mode:
The cpu will halt after leaving the error halt code in ID[D.SV].
The
information on the machine check is their respective
error/status registers. "Note, Console Responsible for logging &
clearing these registers".
Double Error Halt:
The cpu will halt if it finds on
micro-code that "EFP" is set.

entry

the

Error

handling

The information on the first error will be in ID[TO-T9] and
See layout of ID[TO-T9].
U-STACK (trapped micro-addresses).
Unpredictable on CS Parity errors.
The information on the 2nd
error/status registers.

error

will

the

associated

The cpu will be halted after leaving a double error halt code
ID[D.SV].

Page 6-7

MACHINE CHECK ABORT/FAULT/HALT

Figure 7.1

6.8

SUMMARY PARA.

CES

TRAPPED UPC

VA/VI BA

D-REG

TB ERO

TBERl

TIME.ADDR

PARITY

SBI.ERR

First Error Info on Double Error Halts in ID-Registers

HALT IDENTIFICATION CODES

Values left in ID[D.SV] for
halts.

printout

Console

whenever

0 = Operation requested by console, completed successfully.

the

CPU

Page 6-8

MACHINE CHECK ABORT/FAULT/~ALT
1 = Memory management fault, see

<31-8>

for

specifics

(on

Console

(occurs

console

Request).
2 = Error occurred on Console Request.

3 = Warm/Cold Start Power-up sequence
"!NIT" also).

completed

4 = Interrupt Stack not valid.

5 = CPU Double Error Halt (see Machine Mheck Abort/Fault/Halt Spec for
details)!!! Sys Has Crashed!
6 = Halt instruction.
7 = Illegal I/E Vector Code/<l :0 >

8 = No user

wcs

(I/E vector specs user WCS).

9 = Error interrupt ( s) pending on "HALT" command.
A = CHM halt.
B = (open)

NOTE
4,5,7,8 codes represent system crashes
and require a Sys Rebott to continue!!!

6.9

RETRYABLE INSTRUCTION LIST

See the attached list for instructions that are retryable and the
specific information and conditions. A summary and interpretation is
as follows:
[applies only to CP Errors, all instructions faultable on
IB Errors]
INSTRUCTIONS THAT ARE NOT RETRYABLE ON CP ERRORS:
ADDN4
ADDN6
ASHN
CHME?
CHMK?
CHMS?
CHMU?
CMPN3
CMPN4
CVTLN

CVTNL?
CVTNP
CVTPN
EDITPC
INSQUE
LDPCTX
MOVN
MULN
POPR
PUS HR

REI
REM QUE
SUBN4
SUBN6
SVPCTX
XFC

MACHINE CHECK ABORT/FAULT/HALT

Page 6-9

There are also restrictions on retrying some instructions
that are retryable.
Restrictions are noted using notes on
the attached list.
[x]

Means instruction is conditionally retryable.
Some restrictions are:
1.

Cannot retry unaligned writes.

The Error handling micro-code aborts all such ~ases.
2.

Instructions Referencing I/O Space

Software required to decide if retryable or not.
In addition these restrictions, the instructions with the
following notes also have the added restrictions as noted.
[2]

Cannot retry any write.
On the instructions noted, the operating software must
examine the logged out information on the stack to determine
if they were doing a write. If so they are not retryable.

[3]

Can cause a SBI Fault.
On the instructions so noted, SBI fault will occur if the
interlocked write is aborted because of a TB parity error.
(Interlock timeout in unit receiving the previous interlock
read).
Operating software must determine that this case
exists.

[4]

Machine check while pushing information on stack (Kernel).
The Error Handling micro-code aborts all such cases.

[?]

Means retryability to be determined later.

[NR] Instruction is not retryable.

90
6F
4F
Fl
3D
80
81
60
61
40
41

ACBB
ACBD
ACBF
ACBL
ACBW
ADDB2
ADDB3
ADDD2
ADDD3
ADDF2
ADDF3
ADDL2

ADD COMPARE AND BRANCH BYTE I x
ADD COMPARE AND BRANCH DOUBLE I
ADD COMPARE AND BRANCH FLOATING
- ADD COMPARE AND BRANCH LONG I x
ADD COMPARE AND BRANCH WORD I x
ADD BYTE 2 OPERAND I x I
ADD BYTE 3 OPERAND I x I
ADD DOUBLE 2 OPERAND I x I
ADD DOUBLE 3 OPERAND I x I
ADD FLOATING 2 OPERAND I x I
ADD FLOATING 3 OPERAND I x I
ADD LONG 2 OPERAND I x I

x
I x I
I
I

MACHINE CHECK ABORT/FAULT/HALT
Cl
20

21
AO
Al
08

F3
F2
78

F8
79
El
ES
E7

E3
lE
lF
EO
E4
E2
E6
13
13
18

lE
14

lA
8A

88
CA
CR
89
AA
AB
88

C9
88
A8

A9
93
03

83
E9

ES
15
18
19

lF
12
12
03
11

ADDL3
ADDN4
ADDN6
ADDW2
ADDW3
ADWC
AOBLEQ
AOBLSS
ASHL
ASHN
ASHQ
BBC
BBCC
BBCCI
BBCS
BCC
BCS
BBS
BBSC
BBSS
BBSSI
BEQL
BEQLU
BGEQ
BGEQU
BGTR
BGTRU
BICB2
BICB3
BICL2
BICL3
BICPSW
BICW2
BICW3
BISB2
BISB3
BISL2
BISL3
BISPSW
BISW2
BISW3
BITB
BITL
BITW
BLBC
BLBS
BLEQ
BLEQU
BLSS
BLSSU
BNEQ
BNEQU
BPT
BRB
BRW

Page 6-10

ADD LONG 3 OPERAND I x I
ADD NUMERIC 4 OPERAND I NRI
ADD NUMERIC 6 OPERAND I NRI
ADD WORD 2 OPERAND I x I
ADD WORD 3 OPERAND I x I
ADD WITH CARRY I [2] I
ADD ONE AND BRANCH ON LESS OR EQUAL I x I
ADD ONE AND BRANCH ON LES I x I
ARITHMETIC SHIFT LONG I x I
ARTHMETIC SHIFT NUMERIC I NRI
ARITHMETIC SHIFT QUAD I [2] I
BRANCH ON BIT CLEAR I x I
BRANCH ON BIT CLEAR AND CLEAR I x I
BRANCH ON BIT CLEAR AND CLEAR INTERLOCKED I [3] I
BRANCH ON BIT CLEAR AND SET I x I
BRANCH ON CARRY CLEAR I x I
BRANCH ON CARRY SET I x I
BRANCH ON BIT SET I x I
BRANCH ON BIT SET AND CLEAR I x I
BRANCH ON BIT SET AND SET I x I
BRANCH ON BIT SET AND SET INTERLOCKED I [3] I
BRANCH ON EQUAL I x I
BRANCH ON EQUAL UNSIGNED I x I
BRANCH ON GREATER OR EQUAL I x I
BRANCH ON GREATER OR EQUAL UNSIGNED I x I
BRANCH ON GREATER I x I
BRANCH ON GREATER UNSIGNED
x
BIT CLEAR BYTE 2 OPERAND I x I
BIT CLEAR BYTE 3 OPERAND I x I
BIT CLEAR LONG 2 OPERAND I x I
BIT CLEAR LONG 3 OPERAND I x I
BIT CLEAR PROGRAM STATUS WORD I x I
BIT CLEAR WORD 2 OPERAND I x I
BIT CLEAR WORD 3 OPERAND I x I
BIT SET BYTE 2 OPERAND I x I
BIT SET BYTE 3 OPERAND I x I
BIT SET LONG 2 OPERAND I x I
BIT SET LONG 3 OPERAND I x I
BIT SET PROGRAM STATUS WORD I x l
BIT SET WORD 2 OPERAND I x I
BIT SET WORD 3 OPERAND I x I
BIT TEST BYTE I x I
BIT TEST LONG I x I
BIT TEST WORD I x I
BRANCH ON LOW BIT CLEAR I x I
BRANCH ON LOW BIT SET I x I
BRANCH ON LESS OR EQUAL I x I
BRANCH ON LESS OR EQUAL UNSIGNED I x I
BRANCH ON LESS I x I
BRANCH ON LESS UNSIGNED I x I
BRANCH ON NOT EQUAL I x I
BRANCH ON NOT EQUAL UNSIGNED I x I
BREAK POINT TRAP I [4] I
BRANCH WITH BYTE DISPLACEMENT I x I
BRANCH WITH WORD DISPLACEMENT I x I

MACHINE CHECK ABORT/FAULT/HALT
10
30

IC
ID
FA
FB
SF
CF
AF
BD
BC
BE
BF
94

7C
04
D4
7C
B4
91
29
20

71
51
Dl
35
37

EC
Bl
ED
OB
6C

4C
98
99

68
76
6A
69
48

4A
49
F6

4E
F9
F7
36
26
24

68
48

33
6D

BSBB
BSBW
BVC
BVS
CALLG
CALLS
CASES
CASEL
CASEW
CHME
CHMK
CHMS
CHMU
CLRB
CLRD
CLRF
CLRL
CLRQ
CLRW
CMPB
CMPC3
CMPCS
CMPD
CMPF
CMPL
CMPN3
CMPN4
CMPV
CMPW
CMPZV
CRC
CVTBD
CVTBF
CVTBL
CVTBW
CVTDB
CVTDF
CVTDL
CVTDW
CVTFB
CVTFD
CVTFL
CVTFW
CVTLB
CVTLD
CVTLF
CVTLN
CVTLW
CVTNL
CVTNP
CVTPN
CVTRDL
CVTRFL
CVTWB
CVTWD

Page 6-11

BRANCH TO SUBROUTINE WITH BYTE DISPLACEMENT I x I
BRANCH TO SUBROUTINE WITH WORD DISPLACEMENT I x I
BRANCH ON OVERFLOW CLEAR I x I
BRANCH OF OVERFLOW SET I x I
CALL WITH GENERAL ARGUMENT LIST I [2] I
CALL WITH STACK I [2] I
CASE BYTE I x I
CASE LONG I x I
CASE WORD I x I
CHANGE MODE TO EXECUTIVE I ? I
CHANGE MODE TO KERNAL I ? I
CHANGE MODE TO SUPERVISOR I ? I
CHANGE MODE TO USER I ? I
CLEAR BYTE I x I
CLEAR DOUBLE I [2] I
CLEAR FLOAT I x I
CLEAR LONG I x I
CLEAR QUAD I [2] I
CLEAR WORD I x I
COMPARE BYTE I x I
COMPARE CHARACTER 3 OPERAND
x I
COMPARE CHARACTER 5 OPERAND
x I
COMPARE DOUBLE I x I
COMPARE FLOATING I x I
COMPARE LONG I x I
COMPARE NUMBERIC 3 OPERAND
?
COMPARE NUMBERIC 4 OPERAND
?
COMPARE VIELO I x I
COMPARE WORD I x I
COMPARE ZERO-EXTENDED VIELO I x I
CALCULATE CYCLIC REDUNDANCY CHECK I x I
CONVERT BYTE TO DOUBLE I [2] I
CONVERT BYTE TO FLOAT I x I
CONVERT BYTE TO LONG I x I
CONVERT BYTE TO WORD I x I
CONVERT DOUBLE TO BYTE I x I
CONVERT DOUBLE TO FLOAT I x I
CONVERT DOUBLE TO LONG I x I
CONVERT DOUBLE TO WORD I x I
CONVERT FLOAT TO BYTE I x I
CONVERT FLOAT TO DOUBLE I [2] I
CONVERT FLOAT TO LONG I x I
CONVERT FLOAT TO WORD I x I
CONVERT LONG TO BYTE I x I
CONVERT LONG TO DOUBLE I [2] I
CONVERT LONG TO FLOAT I x I
CONVERT LONG TO NUMERIC I NRI
CONVERT LONG TO WORD I x I
CONVERT NUMERIC TO LONG I ? I
CONVERT NUMERIC TO PACKED I NRI
CONVERT PACKED TO NUMERIC I NRI
CONVERT ROUNDED DOUBLE TO LONG I x I
CONVERT ROUNDED FLOAT TO LONG I x I
CONVERT WORD TO BYTE I x I
CONVERT WORD TO DOUBLE I [2] I

MACHINE CHECK ABORT/FAULT/HALT
40
32
97
D7
87
86

87
66
67
46
47

C6
C7
27
A6

A7
38
7B

74
54

7A
EE
EF
EB
EA
00
96

D6
B6
FO
OE
17

16
06

3A
39
92

D2
B2
DB

72
52

CE
AE
9E
7E

DE
DE
7E

3E
90
28

2C
70

CVTWF
CVTWL
DECB
DECL
DECW
DIVB2
DIVB3
DIVD2
DIVD3
DIVF2
DIVF3
DIVL2
DIVL3
DIVN
DIVW2
DIVW3
EDIT PC
EDIV
EMO DD
EMODF
EMUL
EXTV
EXTZV
FFC
FFS
HALT
INCB
INCL
INCW
INSV
INS QUE
JMP
JSB
LDPCTX
LOCC
MATCHC
MCOMB
MCOML
MCOMW
MFPR
MNEGB
MNEGD
MNEGF
MNEGL
MNEGW
MOVAB
MOVAD
MOVAF
MO VAL
MOVAQ
MOVAW
MOVB
MOVC3
MOVCS
MOVD

CONVERT WORD TO FLOAT I x I
CONVERT WORD TO LONG I x I
DECREMENT BYTE I x I
DECREMENT LONG I x I
DECREMENT WORD I x I
DIVIDE BYTE 2 OPERAND
x I
DIVIDE BYTE 3 OPERAND I x I
DIVIDE DOUBLE 2 OPERAND I [2] I
DIVIDE DOUBLE 3 OPERAND I f 2] I
DIVIDE FLOATING 2 OPERAND I x I
DIVIDE FLOATING 3 OPERAND I x I
DIVIDE LONG 2 OPERAND I x I
DIVIDE LONG 3 OPERAND I x I
DIVIDE NUMERIC I NRI
DIVIDE WORD 2 OPERAND
x I
DIVIDE WORD 3 OPERAND I x I
EDIT PACKED TO CHARACTER I NRI
EXTENDED DIVIDE I [2] I
EXTENDED MODULUS DOUBLE I [2] I
EXTENDED MODULUS FLOATING f [2] I
EXTENDED MULTIPLY I [2] I
EXTRACT VIELD I x I
EXTRACT ZERO-EXTENDED VIELD I x
FIND FIRST CLEAR BIT I x I
FIND FIRST SET BIT I x I
HALT I [4] I
INCREMENT BYTE I x
INCREMENT LONG I x
INCREMENT WORD I x
INSERT VIELD I x I
INSERT INTO QUEUE I NRI
JUMP I x I
JUMP TO SUBROUTINE I x I
LOAD PROGRAM CONTEXT I NRI
LOCATE CHARACTER I x I
MATCH CHARACTERS I x I
MOVE COMPLEMENTED BYTE I x I
MOVE COMPLEMENTED LONG I x I
MOVE COMPLEMENTED WORD I x I
MOVE FROM PRECESSOR REGISTER 1(2] I
MOVE NEGATED BYTE I x I
MOVE NEGATED DOUBLE I [211
MOVE NEGATED FLOATING I x I
MOVE NEGATED LONG I x I
MOVE NEGATED WORD I x I
MOVE ADDRESS OF BYTE I x I
MOVE ADDRESS OF DOUBLE I x I
MOVE ADDRESS OF FLOAT I x I
MOVE ADDRESS OF LONG I x I
MOVE ADDRESS OF QUAD I x I
MOVE ADDRESS OF WORD I x I
MOVE BYTE I x I
MOVE CHARACTER 3 OPERAND
x I
MOVE CHARACTER 5 OPERAND
x I
MOVE DOUBLE I [2] I

Page 6-12

MACHINE CHECK ABORT/FAULT/HALT

so
DO
34

DC
7D
2E
2F
BO
9A
9B

3C
DA
84

64
6S
44
4S

cs
2S

AS
01
7S
SS

9F
7F
Dlf

DF
7F

3F
DD
BB

02
OF
04

9C
OS
D9
2A
3B
F4

FS
2B
82
83

62
63
42

C_2

MOVF
MOVL
MOVN
MOVPSL
MOVQ
MOVTC
MO VT UC
MOVW
MOVZBL
MOVZBW
MOVZWL
MTPR
MULB2
MULB3
MULD2
MULD3
MULF2
MULF3
MULL2
MULL3
MULN
MULW2
MULW3
NOP
POLYD
POLYF
POPR
PROBER
PROBEW
PUSHAB
PUS HAD
PUSHAF
PUS HAL
PUS HAQ
PUSHAW
PUSHL
PUS HR
REI
REMQUE
RET
ROTL
RSB
SBWC
SCANC
SKPC
SOBGEQ
SOBGTR
SPA NC
SUBB2
SUBB3
SUBD2
SUBD3
SUBF2
SUBF3
SUBL2

Page 6-13

MOVE FLOAT I x I
MOVE LONG I x I
MOVE NUMERIC I ? I
MOVE PROGRAM STATUS LONGWORD I x I
MOVE QUAD I [2] I
MOVE TRANSLATED CHARACTERS I x I
MOVE TRANSLATED UNTIL CHARACTER I x I
MOVE WORD I x I
MOVE ZERO-EXTENDED BYTE TO LONG I x I
MOVE ZERO-EXTENDED BYTE TO WORD I x I
MOVE ZERO-EXTENDED WORD TO LONG I x· I
MOVE TO PROCESSOR REGISTER I x I
MULTIPLY BYTE 2 OPERAND I x I
MULTIPLY BYTE 3 OPERAND I x I
MULTIPLY DOUBLE 2 OPERAND I [2] I
MULTIPLY DOUBLE 3 OPERAND I [2] I
MULTIPLY FLOATING 2 OPERAND I x I
MULTIPLY FLOATING 3 OPERAND I x I
MULTIPLY LONG 2 OPERAND I x I
MULTIPLY LONG 3 OPERAND I x I
MULTIPLY NUMERIC I NRI
MULTIPLY WORD 2 OPERAND
x I
MULTIPLY WORD 3 OPERAND
x I
NO OPERATION I x I
EVALUATE POLYNOMIAL DOUBLE I [2] I
EVALUATE POLYNOMIAL FLOATING I x
POP REGISTERS I NRI
PROBE READ ACCESS I x I
PROBE WRITE ACCESS I x I
PUSH ADDRESS OF BYTE I x
PUSH ADDRESS OF DOUBLE I x I
PUSH ADDRESS OF FLOAT I x I
PUSH ADDRESS OF LONG I x I
PUSH ADDRESS OF QUAD I x I
PUSH ADDRESS OF WORD I x I
PUSH LONG I x I
PUSH REGISTERS I NRI
RETURN FROM EXCEPTION OR INTERRUPT I NRI
REMOVE FROM QUEUE I NRI
RETURN FROM CALLED PROCEDURE I x I
ROTATE LONG I x I
RETURN FROM SUBROUTINE I x
SUBTRACT WITH CARRY I [2] I
SCAN FOR CHARACTER I x I
SKIP CHARACTER I x I
SUBTRACT ONE AND BRANCH ON GREATER OR EQUAL I x I
SUBTRACT ONE AND BRANCH ON GREATER I x I
SPAN CHARACTERS I x I
SUBTRACT BYTE 2 OPERAND
x I
SUBTRACT BYTE 3 OPERAND I x I
SUBTRACT DOUBLE 2 OPERAND I [2] I
SUBTRACT DOUBLE 3 OPERAND I [2] I
SUBTRACT FLOATING 2 OPERAND I x I
SUBTRACT FLOATING 3 OPERAND I x I
SUBTRACT LONG 2 OPERAND I x I

MACHINE CHECK ABORT/FAULT/HALT
C3
22
23
A2
A3
07
9S
73

S3
OS
BS
FC
BC

CD
AC
AD

SUBL3
SUBN4
SUBN6
SUBW2
SUBW3
SVPCTX
TSTB
TSTD
TSTF
TSTL
TS1W
XFC
XORB2
XORB3
XORL2
XOPL3
XORW2
XORW3

08
09

OA
S7

SB
S9

SA
SB
SC
SD
SE
SF
77

FD
FE
FF

ESCO
ESCE
ESCF

SUBTRACT LONG 3 OPERAND I x I
SUBTRACT NUMERIC 4 OPERAND I NRI
SUBTRACT NUMERIC 6 OPERAND I NRI
SUBTRACT WORD 2 OPERAND I x I
SUBTRACT WORD 3 OPERAND I x I SAVE PROCESS CONTEXT I NRI
TEST BYTE I x I
TEST DOUBLE I x I
TEST FLOAT I x I
TEST LONG I x I
TEST WORD I x I
EXTENDED FUNCTION CALL I NRI
EXCLUSIVE-OR BYTE 2 OPERAND I x I
EXCLUSIVE-OR BYTE 3 OPERAND I x I
EXCLUSIVE-OR LONG 2 OPERAND I x I
EXCLUSIVE-OR LONG 3 OPERAND I x I
EXCLUSIVE-OR WORD 2 OPERAND I x I
EXCLUSIVE-OR WORD 3 OPERAND I x I
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO CEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *
* RESERVED TO DEC *

Page 6-14

CHAPTER 7
CACHE-SBI-TB SUBSYSTEM

7 .1

MD BUS

MD Bus transfers longword aligned data amongst the cache,
interface, data path, and instruction buffer. Signals are:
BUS

BUS

BYTE

PARITY

where

BUS

BYTE

MASK

where x runs 0 to 3

TBMD

D TO

TBMD

MASK

SBI

where XX runs 00 to 31

x runs 0 to 3

Parity is computed over each 8 data bits, such that if the 8 data bits
are low, the parity bit will be high. The mask is not checked. Byte
mask high means write on a write cycle, and means this byte is wanted
on a read cycle.
The data, parity, and mask are all long word
aligned.
The D TO MD signal directly drives the enables of the data and parity
drivers on the data path. The MASK TO MD signal directly drives the
enable of the mask driver on the data path.

7.2

CS BUS

This subsystem uses 6 cs bits:
BUS
BUS
BUS
BUS
BUS
BUS

cs
cs
cs
cs
cs
cs

42
47
46
45
44
43

H
H
H

UFS
UADS
UMCT3
UMCT2
UMCTl
UMCTO

These bits will be received by 74Sl94 chips on the TBM board.

Page 7-2

CACHE-SBI-TB SUBSYSTEM
7.3

V BUS

This subsystem will meet the V bus spec.

7.4

Available signals TBS.

CLOCK BUS

Clock signal loading is:

7.5

ADDRESS BUS

The address is received in three sections;
VA REG < 8:2> H
VA MUX <15:9> L
VA MUX <31:16> L
The first group of seven bits is the low bits of the CPU virtual
address register, unbuffered.
During a subsystem activity using a
virtual or physical address in the VA register, these bits will be put
on the PA bus, the subsystem internal physical address bus. During a
microcode requested load of the Instruction Physical Address Register
(IPA) the low seven bits will be copied from the VA bits.
The next set of seven bits is the output of multiplexers. One set of
data inputs is attached to the VA register, the other set is attached
to the IA register. These multiplexer bits are constantly enabled.
The upper sixteen bits are driven the same way as the middle seven,
except that the enables of the multiplexers are driven by a CPU
generated signal to provide zeros for compatibility mode.
All
microcode-specified memory operations use the address from the VA.
The IA is used only for automatic reloading of the IPA.

7.6

FROM IB
the IPA should be incremented.
after the IB receives data. Not

IDPJ COUNT H
means that
Only present one cycle
present during FLUSH.

IDPJ FLUSH L
means that the old IPA is no longer valid.
Microcode should not do FLUSH and READ.V.NEWPC in the same
state.

CACHE-SBI-TB SUBSYSTEM

7.7

IRCH IB WRITE CHK H means that if the microcode does a
READ.V.IBCHK the check should be for write access. This
signal is clocked at the same time as the CS bits.

IDPJ IB REQ H
means that if the microcode allows an !BREAD,
the IB would like to use it, or if miss data comes back, the
IB would like to receive it.

TO IB
A.

SBLR IB READ DATA L
bus this microcycle.

TBMX IB MISS L
means that on the most recent load
IPA, no entry was found in the translation buffer.

TBMX IB ERR L
1.

2.
3.

7.8

means that data for the IB is on te
of

MD
the

means that either

on the most recent load of the IPA, an entry was found in
the TB but protection code was bad or
on the most recent load of the IPA, a parity error
occured or
the SBI interface detected an error during a cycle being
done for the IB which resulted in data never being
delivered.

FROM MICROSEQUENCER
A.

7.9

Page 7-3

uses ABORT CYCLE H means that the word coming from the
control store should not be used because of a microtrap or
ECO or console crock.

TO MICROSEQUENCER
A.

SBLT STALL L
means that the next
temporarily prevented from executing.

TBMD LAST REF CODE 1 H
TBMD LAST REF CODE 0 H

microword

should

are microbranch conditions.
They are the output of a
register clocked on any state which saves context (not
inhibited by UMISC field). The codes are:

Page 7-4

CACHE-SBI-TB SUBSYSTEM
CODE

1 I 0 I means

--1---1----------------0 I 0 I READ with RCHK
0 I 1 I READ with WCHK
1 I 1 I WRITE with WCHK
1 I 0 I INTLK READ

TBMX BRANCH CODE 1 H
TBMX BRANCH CODE 0 H
are microbranch
register.
CODE

conditions.

They

are

the

output

1 I 0 I means

--------1---1----------------------------------------0 I 0 I WONDERFUL
0 I 1 I TBHIT and PROTECTION OK and MBIT ERROR
1 I 1 I TBMISS
1 I 0 I TBHIT and PROTECTION VIOLATION

7.10

7.11

is a microbranch condition.

TBMB KERNEL MODE H

FROM TRAPS AND INTERRUPTS
A.

(TEMP) !SR CODE 1 H and 0 H
specify the level at which an
interrupt summary read SBI transaction should be executed if
the microcode orders
one.
Stable
from
before
the
microcommand until after it.

(TEMP) CURRENT MODE 1 H and 0 H
are the current mode bits
of the PSL used for checking protection for certain virtual
references and for auto-refill of the IPA. Stable all during
any of them.

(TEMP) CSPAR ERR H

(TEMP) CMODDADRS TRAP L

(TEMP) PAGE TRAP H

indicates data crossing page boundary.

TO TRAPS AND INTERRUPTS
A.

Several signals which cause interrupts.
1.

SBLM CRD RDS INTR L
requests an interrupt
receives a CRD or an RDS from the SBI.

the

CPU

SBLM TIMO CNF INT L
requests an interrupt if the CPU
times out or receives an ERR confirmation on the SBI.

CACHE-SBI-TB SUBSYSTEM
3.

Page 7-5

SBHE SBI REQ 7 R H
SBHE SBI REQ 6 R H
SBHE SBI REQ 5 R H
SBHE SBI REQ 4 R H
These are the SBI interrupt requests.

SBHE SBI ALERT R H

is the SB! ALERT signal.

requests an
SBHK COMP INTR H
silo comparator matches.

the

SB!

SBHL FAULT INTR H
requests an interrupt because of
assertion of FAULT on the SBI.

the

interrupt

when

Several signals which cause microtraps.
1.

SBLM TIMEOUT TRAP L
requests a microtrap
timeouts which prevent further progress.

CPU

SBLP PAR ERR TRAP L
requests a microtrap on
cycles which encounter a cache parity error.

CPU

read

SBLR RDS TRAP L
requests microtrap if a CPU READ
receives an RDS from the SBI.

cycle

TBMU PROT UTRAP L
requests a microtrap if a translation
for the CPU causes protection violatiori.

TBMW TB PAR UTRAP L
requests a microtrap on
errors during translation for the CPU.

TBMW MBIT UTRAP L
requests a microtrap if a translation
for the CPU doing a writecheck uses a TB entry with the
MBIT not set.

TBMW MISS UTRAP L
requests a microtrap if a translation
for the CPU does not find an entry in the TB.

parity

Several microtrap enable signals.
1.

TBMN PAGE EDGE H
indicates that the data crossing page
boundary microtrap is enabled and VAREG <8:3> are high.

TBMW EN CMODDADRS H
indicates that this type of memory
cycle should enable the compatibility mode odd address
trap.

TBMW EN UNALIGN TRAP H
indicates that this type
cycle should microtrap if the data is not aligned.

TBMW SAVE CONTEXT H means that this type of memory cycle
requires that certain context information be saved. This
signal is overridden in the data path by certain UMISC field
codes.

CACHE-SBI-TB SUBSYSTEM

Page 7-6

7.12

FROM DATA PATH - NONE

7.13

TO DATA PATH

7.14

7.15

SBLP MD to D L
means that the D register should
from the MD bus.

TBMD D TO MD L
path.

the

data

TBMD MASK TO MD L
data path.

turns on the MD bus mask drivers

the

TBMC ENABLE IA H

is the input which switch the VAMUX.

turns on the MD

bus

drivers

loaded

SELECTED INTERNAL SUBSYSTEM SIGNALS
A.

SBHM SET SBI CYCLE H means that the MD bus cycle coming up
will be used by the SBI interface, usually to transfer d~ta
from a read miss or to invalidate a location in the cache
that was written on the SBI.

SBLK BUFFER FULL H means that the register in the SB!
interface used to hold addresses for SBI cycles is full,
because the previous write has not been acknowledged, the
expected read data has not arrived, etc.

SBLR VALID H
cache tag.

SBLR SET FORCE SBI L
is the output of a circuit which will
grab the first opportunity after a CPU write miss parity
error to clear out the entry with the error.

TBMU CANCEL L
indicates to the SBI interface that the cycle
requested by the microcode should not be completed this cycle
because of some error condition known on TBM or because an
auto-refill of te IPA is in progress.

is the input to the

valid

bit

MICROBRANCHES

(See "VAX 11/780 Microcode" .for up to date information).
A.

BEN15 - LAST REFERENCE

the

data

CACHE-SBI-TB SUBSYSTEM

Page 7-7

This subsystem provides bits one and zero for this BEN.
code is:
UPC
I
1 I o

RETRY
MICROORDER

0
0
1

1
1

BEN 10 - TRANSLATION TEST
This subsystem provides bits one and zero for this BEN.
code is given under microorders 0,2 below.

7.16

The

MICROORDERS

The available microorders are shown in the
follow, indexed by the order number (decimal).
0,2

chart.

Descriptions

These are used to get the
translation
buffer's
attention to load set of microbranch codes which can be
tested in the next microinstruction.
MSB LSB
The code is

1
0

TBMISS
PROTECTION VIOLATION.NOT
TBMISS
NOT PROT VIOLATION.NOT
TBMISS.WCHK.MBIT
NO PROBLEM

This is the normal virtual write.
Retry involves
1.

This

is_

retryable.

using the previous cycle type microbranch to find
out which of the four retryable cycles was being
done.
sending the proper microorder again in combination
with
the
proper
saved context code in the
miscellaneous field.

This code does a virtual write without a protection
check or modify bit check. It is used for. cycles that
are prechecked by microcode, such as writing page table
entries.

Page 7-8

CACHE-SBI-TB SUBSYSTEM
7

This is the virtual interlock write.

Normal virtual read.

Nocheck vir~ual read for page tables, etc.

Virtual read with write check for
Retryable.

Virtual read with protection check read or write
specified by the instruction buffer. The. retry branch
will indicate whether to retry as code 8 or .10.

This cycle is used whenever the microcode wishes to
reload the IPA, whether because of a macroprogram
transfer of control
or
to
restart
instruction
prefetching after loading the TB with a translation of
a previously missing page. It causes a virtual read
cycle with data to the instruction buffer. All errors
are handled with the IB error mechanism.

Virtual interlock read, used for interlock instruction.
Retryable.

Nocheck virtual interlock read.
No known use
present,
but
may
be needed if MBIT update
respecified as interlocked.

Physical Read, for LDPCTX etc.

Physical Write, for STPCTX etc.

29,23

Physical Interlock Read and Write.
present.

Causes a Read Interrupt Summary transaction on the SBI.

Causes an Extended Write on the SBI. The data written
is unpredictable. Used to clear out double ECC errors
in MOS. The location in cache will be invalidated.

16,17

Asserts Hold and Unjam on the SBI.
console UNJAM command sequence.

Writes good parity non-valid data and tag in both
groups at the index position specified. No SBI cycle.
Used on all index positions at power up. Also used by
microdiagnostics.
May also be used by certain error
routines.

Causes a write of the specified address and data, with
good parity, marked valid, in the group specified by
the force replacement bits. Used by microdiagnostics.
No SBI cycle.

Retryable.

modifying

For

known

use

accesses.

use

at
is

the

Page 7-9

CACHE-SBI-TB SUBSYSTEM
31,48-63

Allows initiation of read cycles by the instruction
buffer while performing the ID bus operation specified.
This code should be used in most places where an
explicit memory operation is not required in order to
allow the IB to acquire I stream bytes. Should not be
used during IB FLUSH states.

32-47

ID bus operation only, IB cycle initiation is blocked.
This code should appear in all locations of error trap
routines until the IB can be turned off to prevent
multiple errors.

NO OPERATION

3,4,15,22,24,26,27,28,30
READ
WRITE
TBMISS
A
A
PROTECTION
A
A
DATA CROSS PAGE
A
A
DATA NOT ALIGNED
N
N
WCHK.TBMBIT
A
A
CM.ODD ADRS
A
A
A
TB PARITY
A
CACHE PARITY
A
No Trap
TIMEOUT
B
B
*Not a Trap
CRD
URD (RDS)
A*
CS PARITY
A
A

RESERVED, UNPREDICTABLE, DO NOT USE
EFFECT OF TRAPS
A: No good read data
memory not written
cache not written
cache sideeffected
memory not sideeffected
B: No good read data
memory may be written
cache may be written
cache sideef fected
memory may be sideef f ected
N: all normal effects
*: memory sideeffected
sideeffected includes
changes in status bits

CACHE-SBI-TB SUBSYSTEM
Memory Control Functions

Page 7-10
October 11, 1976

trap on
I I FI
I IT A
o
sI
Y = u trap on c ond it ion
I I UI Cl IB C X A T D T
Bl
* = utrap on condition unless MSC/
I I NI HISIM CPL B DB C II
SECOND.REF or RETRY.NO.TRAP
A
IVI Cl EIAII EA I UAP P El
N =do not utrap on condition
D MCT Fl/I Tl CIVIS S G G F DA A RI
- =hardware behaviour undefined.
S 3210 SIPI NI KIEIS SEN MR RR RI
uncode must prevent condition
--------+-+--+--+-+-----------------+---------------------0 0000 OIVI
I RININ N N N N NY N NI TEST.RCHK
0 0001 OIVI
I ININ N N N N N N N NI MEM.NOP
0 0 0 l 0 0 IV I I WIN I N N N N N N Y N N I TEST. WCHK
o 0011 o I I I I I
I

o 0100 o I I

I I

0 0101 0 IV I WI
IN IY N - - N - Y N Y I WR IT E. V. NOC HK
0 0110 OIVI WI WIYIY Y * * Y Y Y N YI WRITE.V.WCHK
0 0111 OIVIIWI
INI- - - - - - Y N Yf LOCKWRITE.V.XCHK

0 1000 OIVI
0 1001 OIVI
0 1010 OIVI
0 1011 OIVI

RI RIYIY Y **NY Y Y YI
RI
INfY N - - N - Y Y YI
RI WIYIY Y * * Y Y Y Y YI
RIIBIYIY Y Y Y Y Y Y Y YI

READ.V.RCHK
READ.V.NOCHK
READ.V.WCHK
READ.V.IBCHK

0 1100 OIVI RI RININ N N N NY N N NI READ.V.NEWPC
0 1101 OIVIIRI
INIY N - - N - Y Y YI LOCKREAD.V.NOCHK
0 1110 OIVIIRI WIYIY Y - - Y - Y Y YI LOCKREAD.V.WCHK
o 1111 o I I I I I
I
1
1
1
1

0000
0001
0010
0011

OI IHOLD ININ N N N N N N N NI
OI IUNJAMININ N N N N N N N NI
OIPIINVALINfN N N N N N N N NI
OIPI VAL ININ N N N N N N N NI

1
1
1
1

0100
0101
0110
0111

OIPIEXTWRININ N N N N N N N YI EXTWRITE.P
OIPI W ININ N N N N N N N YI WRITE.P
Of I
I I
I
OIPI IW ININ N N N N N N N YI LOCKWRITE.P

1
1
1
1

1000 o I I
1001 OIPI R
1010 OI I
1011 OIPI ISR

1
1
1
1

1100 11 I
1101 OIPI
1110 o I I
1111 OIII

0 XXXX 11 I
1 XXXX !III

SBI.HOLD
SBI.HOLD+UNJAM
INVALIDATE
VALIDATE

I I
I
ININ N N N N N NY YI READ.P
I I
I
ININ N N N N N N N YI READ.INT.SUM

I I
I
IR ININ N N N N N.N Y YI LOCKREAD.P
I I
I
R ININ N N N N N N N NI ALLOW.IS.READ
R

I INN N N N N N N NI NO MEMORY OPERATION
ININ N N N N N N N NI DEFAULT: ALLOW IB READ

Abort Ref on Trap? A A A

A A A R A (A=any, R=read)

CACHE-SBI-TB SUBSYSTEM
7.17

Page 7-11

REGISTERS

HEX ID ADRS

10
11
12
13
14 to 17
18
19
lA
18
lC
lD
lE
lF

TRANSLATION BUFFER DATA REGISTER
NOT USED AT PRESENT
TB REGISTER 0
TB REGISTER 1
NOT USED BY THIS SUBSYSTEM
SILO DATA REGISTER
SB! ERROR REGISTER
TIMEOUT ADDRESS REGISTER
SBI FAULT-STATUS REGISTER
SILO COMPARATOR REGISTER
MAINTENANCE REGISTER
CACHE PARITY REGISTER
NOT USED AT PRESENT

TRANSLATION BUFFER DATA REGISTER
This register is write only from the ID bus. It is used to
write the translation buffer.
The virtual address to be
translated must be in VA, the PTE must be in D (the MBZ bits
must be zero).
Which group is written is selected as
follows:
1. if the REPLACE BOTH bit is on in TB REGISTER 0, both
groups are written. Otherwise,
2.
if one of the groups has a good entry for the address
being translated, that entry will be updated. Otherwise,
3. if one of the FORCE REPLACE bits in TB REGISTER 0 is on,
the selected group will be written. Otherwise,
4. a randomly chosen group will be written.

TB REGISTER 0
bitl

name and use

MME - read/write bit. If not set, the TB parity,
miss, protection, Mbit, and page boundary microtraps
are disabled and any address which would normally be
translated is used directly from the VA or VIBA as
appropriate.

CACHE-SBI-TB SUBSYSTEM
1-4

Page 7-12

FORCE TB PARITY ERROR CODE - read/write.
bit code
4 3 2 1
0 0
0 0
0 1
0 1
1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
0
0
0
0
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

force error is
GROUP
ADRS/DATA byte

0
0
0
1
1
1

DO
Dl
D2
DO
Dl
D2
AO
Al
A2
AO
Al
A2

NOT USED

TBGO HIT - read only. This is the latched output
the group zero address checker. For diagnostics.

CACHE-SBI-TB SUBSYSTEM

Page 7-13

TBGl HIT - as above for group 1

8-15

LAST REF - read only.
These
bits
contain
the
following
information about the most recent non-NOP
memory request by microcode.
15
14
13
12
11
10
09
08

UFS
UADS
UMCT3
UMCT2
UMCT1
UMCTO
IB WCHK from the instruction buffer
This cycle was delayed one cycle by
an auto-reload of the IPA

FORCE TBGO MISS - read/write. Causes the group 0
address checker to say no match.

FORCE TBGl MISS - same for group 1. {NOTE: The force
miss bits also disable TB parity checking on that
group.)

18,19

TB FORCE REPLACE CODE - read/write.
Affects-which group is written by the Translation
Buffer Data Register as follows:
19

18 I result

0
1
1

1 I GROUP 0
0 I GROUP 1
1 I DO NOT USE

--------1------------0
0 I RANDOM GROUP
20

REPLACE BOTH - read/write.
See Translation Buffer
Data Register for effect. Normally used when clearing
the TB.

TB REGISTER 1
bitf

name and use

0-3

IPA INFO - read only. These bits contain information
about the most recent load of IPA as follows:
bit
0
1
2
3

AUTO LOAD - this load was automatic, not the
result of READ.V.NEWPC
PROTECT - there was a protection violation on
this load (or miss).
PARITY - there was a parity error on this load.
MISS - there was a TB miss on this load.

CACHE-SBI-TB SUBSYSTEM

Page 7-14

BAD IPA - read only. The information in IPA and IPA
INFO is not useful.
Set by counting across a page
boundary or by FLUSH, cleared by loading the IPA.

NOT USED

LAST TB WRITE PULSE - read only.
This bit indicates which group was most recently
written.
It is indeterminate if both groups were
written.

NOT USED

CP TB PAR ERR - cleared by any write to this register.
This bit indicates that the TB has requested a TB PAR
ERR microtrap.
TB PAR BITS - cleared by any write to this register.
This group of bits will all be loaded if there is a TB
parity error and either TB parity traps are enabled or
the IPA is being loaded. Each bit gets a one if its
corresponding checker detects an error, and a zero
otherwise.

9-20

bit

group

ADRS/DATA

byte I

0
0
0
1

A
A
A
A
A
A

D
D
D
D
D
D

10
11
12
13

14
15

l
1

16
17
18
19

0
0
0
1
1

1
2
0
l

2
1

2
0

CACHE-SBI-TB SUBSYSTEM
18

Page 7-15

SILO DATA REGISTER
Listed below are the bit assignments for the SBI Silo.
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

NAME
First entry after FAULT cleared
SB! INTLK
SBI ID4
SB! ID3
SB! ID2
SBI IDl
SBI IDO
SBI TAG2
SBI TAGl
SBI TAGO
NOTE:
SBI M3 or SB! B31
Silo bits 21-18 are
SB! M2 or SBI B30
written with SBI B31-B28
SB! Ml or SBI B29
when the SBI TAG FIELD
SBI MO or SB! B28
specifies command address
SB! CNFl
TAG. Otherwise, SBI M3-MO
SBI CNFO
are written in these bit
SBI TRIS
positions.
SBI TR14
SBI TR13
SBI TR12
SBI TRll
SBI TRIO
SB! TR09
SB! TR08
SBI TR07
SBI TR06
SBI TROS
SB! TR04
SBI TR03
SBI TR02
SBI TROl
SBI TROO

The SB! Silo is a history register of the state of the
indicated SB! signals for the past 16 SBI cycles. While
FAULT is not asserted on the SB!, the silo is written and its
4 bit address counter is updated every cycle. When FAULT is
asserted, writes into the silo are prevented, and the normal
update of the counter is inhibited. The silo address counter
will increment only when the silo is read over· the ID bus
while FAULT is asserted. When FAULT is deasserted, the first
location written has Bit 31=1. This register is read only.

Page 7-16

CACHE-SBI-TB SUBSYSTEM
19

SB! ERROR REGISTER
BIT f

DESCRIPTION

TYPE

31-16
15
14
13
12
11
10
9
8
7

Not used
RDS/CRD Interrupt Enable
CRD
RDS
CP timeout
CP timeout status 1
CP timeout status 0
Not used
CP SBI Error Confirmation
IB RDS
IB Timeout
IB Timeout status 1
IB Timeout status O
IB SB! Error Confirmation
Multiple CP Error
SB! Interface not busy
Not used

5
4

3
2
1
0

RW
RWCL
RWCL
RWCL
R
R

R
R

RWCL
RWCL
R

R
R

R
R
R

Bit 15 & 14
Bit 14, CRD (Corrected Read Data)
sets whenever CRD is
returned to the CPU. The AND condition of bit 14 and bit 15
CRD/RDS interrupt enable causes an interrupt to be requested.
Bit 13
This bit set whenever RDS (Read Data Substitute) is returned
to the CPU. The AND condition of this bit and bit 15 causes
an interrupt to be requested.
Bit 12

CP Timeout

This bit will set any time there is a
requested cycle.
While this bit is
requested.
Bits 11-10

timeout for a CP
set an interrupt is

CP Timeout Status

These bits described the type of timeout that has occurred.

Page 7-17

CACHE-SBI-TB SUBSYSTEM
BITS
11110
0

0
1

1
0

DEVICE NO RESPONSE
DEVICE WAS BUSY
WAITING FOR READ DATA
IMPOSSIBLE CODE

If notification of timeout was by interrupt (not microtrap)
and the code is 10 the cycle was a read, if codes 00 or 01
the cycle was a write. If notification is by microtrap the
type of cycle can be found in TB REGO bits 15 to 8.
Bit 8
This bit sets whenever a CP requested cycle receives an error
confirmation to a command address transfer. While this bit
is set an interrupt will be requested.
NOTE
Writing a "l" in bit 12 clears bit positions 12-10
8 & 2.

Bit 7
Bit 7, IB RDS will set any time for any RDS sent to the CPU
while the SB! interface is fetching data for the instructuion
buffer on the SBI. This bit is write one to clear.
It is
also cleared by flushing the instruction buffer.
Bits 6-3
These bits take on similar meaning .to bits 12-10, & 8, except
these
bits
set only for instruction buffer initiated
requests. Writing a "l" in bit 6 clears bits 6-3. Bits 6-3
clear with the FLUSHING of the instruction buffer.
Notification is by IB error microbranch.
always READ.

The cycle

type

Page 7-18

CACHE-SBI-TB SUBSYSTEM
Bit 2

Multiple CP Error

This bit will set when a second CP timeout or CP SBI error
confirmation occurs with a previous CP timeout or CP SBI
error confirmation set in the register. This bit is reset in
the same manner as bits 12-10, & 8, by writing a "l" in bit
12.
Bit 1
This bit is a "l" whenever the SBI interface is not busy
doing something on the SBI. Bits 14 & 13 (CRD & RDS) should
not be reset by microcode when this bit is "O" (SBI BUSY).
lA

TIMEOUT ADDRESS
This register is a holding register for the Physical
sent on the SBI. Its format is listed below:
31

Address

PA <29:2>

Bi t 31 = MODE 1
30 = MODE 0
29 = Protection Checked Reference
PA = Physical Address
When a timeout occurs on the SBI, this register will latch up
with the physical address of the timeout. This register
remains latched until the timeout error bit (located in the
SBI error register, bit 12) is written as one. This register
will not latch up when a timeout occurs while the SBI is
getting data for the Instruction Buffer. This register is
read only.
Bits 31-29 provide the mode of the reference that resulted in
the timeout.
Bit 29 is 0 for references not subject to
hardware protection check.
lB

SBI FAULT - STATUS REGISTER
Listed below are the bit assignments for the FAULT/STATUS
register, also included is a description of the type of bit.
R read only, RW read-write, and RWCL read write one to clear.

CACHE-SBI-TB SUBSYSTEM
BIT i
31
30
29
28
27

26
25
24
23
22

21
20
19

18
17
16
15-00

NAME
Parity FAULT
Reserved
Unexpected Read Data FAULT
Reserved
Multiple Xmitter FAULT
Transmitter during FAULT cycle
Spare 0
Spare 1
Reserved
Reserved
Reserved
Spare 2
FAULT LATCH
FAULT Interrupt Enable
SBI FAULT Signal
FAULT Silo Lock
Not used

Page 7-19
TYPE
R
R

R
R

RW.
RW
R

R
R

RW
RWCL
RW
R
R

Bits 31-26 are the FAULT bits defined in the SBI spec.
25, 24 & 20 are spare read/write bits.

Bits

Bits 19-17
Bit 19, FAULT latch sets on the leading edge of the SBI FAULT
signal.
While this bit is set, the CPU will assert FAULT on
the SBI. This bit is write one to clear. When this bit is
set and bit 18 (FAULT Interrupt Enable)=! an interrupt will
be requested. Bit 17, the SBI FAULT signal provides the
ability
to detect the FAULT signal being continuously
asserted on the SBI.
Bit 16
The SBI Silo may lock due to two conditions (1) the SBI FAULT
Signal or (2) the SBI Silo comparator finding a compare.
If
the SBI FAULT Signal was the reason for locking the Silo then
Bit 16, FAULT Silo LOCK, will be set.
If the comparator
locked the silo, a bit in the comparator register will set.
If both mechanisms occur simultaneously, both bits will set.
Bit 16 will clear·when a 1 is written into bit 19.
The SBI
FAULT signal must be deasserted for the silo to unlock.
lC

SILO COMPARATOR REGISTER
The Silo Comparator allows the SBI Silo to become locked
under another mechanism besides the assertion of FAULT on the
SBI.

Page 7-20

CACHE-SBI-TB SUBSYSTEM

The Silo Comparator may lock the silo under 2 modes of
operation.
The first . mode is unconditional lock. This
allows the SBI Silo to become locked anywhere from 0 to 15
cycles after this register is written.
The number is
determined by the count field contained in this register.
The count field is always set in l's complement, that is to
lock unconditionally after one cycle, the number E would be
set in the count field. The count field is incremented until
it is equal to all l's.
The second mode of operation is conditional lock.
When
certain conditions exist on the SBI, a compare signal will be
generated. This compare signal is latched.
The output of
this latch allows the counter to be incremented. When the
count fild is equal to all l's the SBI Silo will lock.
In both cases the Silo will be unlocked by writing a number
other than F in the count field. The SBI FAULT signal must
be deasserted for the silo to unlock.
The compare modes that are provided are:
1.

SB! ID = Maintenance ID

SB! ID = Maintenance ID
and
SB! TAG = Comparator TAG

SBI ID = Maintenance ID
and
SB! TAG = Comparator TAG
and
SB! B<31:28> or SB! M<3:0> =Comparator
Field

Command/Mask

* When the comparator tag is

equal to command/address the
comparator command/mask field will be compared against
B<31:28>, the command function, otherwise the compare will
be against SB! M<3:0>.

The Maintenance
register.

bits

are

located

the

Maintenance

The AND condition of Comp Silo lock and Silo Lock· Interrupt
Enable cause an interrupt to be requested. Listed below are
the bit definitions for the comparator register.

Page 7-21

CACHE-SBI-TB SUBSYSTEM
BIT

NAME

TYPE

31
30

Comp Silo Lock
Silo Lock Interrupt Enable
Lock Unconditional
Conditional lock codes
Conditional lock codes
Compare Command or Mask 3
Compare Command or Mask 2
Compare Command or Mask 1
Compare Command or Mask 0
Compare TAG 2
Compare TAG 1
Compare TAG 0
Count Field 3
Count Field 2
Count Field 1
Count Field 0

28
27
26
25
24

22
21
20

19
18

17
16

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

Conditional Lock Codes
BIT
28 27
0
0
1

0
1
0

No compare
ID only
ID. TAG
ID. TAG. command function or mask

RW - Read Write
RWCL - Read, Write one to clear

* Any write to this register with bits 19 to 16 not all

ones

will clear this bit.
lD

MAINTENA~CE

Listed below are the
register.

bit

assignments

for

the

maintenance

CACHE-SBI-TB SUBSYSTEM

Page 7-22

BIT

NAME

TYPE

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7-0

Force PO Reversal on SBI
Force Write SEQuence FAULT
Force Unexpected Read Data FAULT
Force Multiple Xmitter FAULT
Maintenance ID4
Maintenance ID3
Maintenance ID2
Maintenance IDl
Maintenance IDO
Force SB! Invalidate
Enable SBI Invalidate
Reverse Cache Parity Field
Reverse Cache Parity Field
Reverse Cache Parity Field
Reverse Cache Parity Field
Force Miss Group 0
Force Miss Group l
Force Replacement Group 0
Force Replacement Group 1
Disable SB! cycles
Force Pl Reversal on SBI
Group 1 Match
Group 0 Match
Force Timeout
Not Used

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
R

R - Read Only
RW - Read Write
REVERSE CACHE PARITY FIELD DEFINITION
20 19
18 17
__
________

DESCRIPTION

0
0

NOP
Reverse Parity Groupl, Byte A, Address
Reverse Parity Group!, Byte B, Address
Reverse Parity Groupl, Byte c, Address
Reverse Parity GroupO, Byte A, Address
Reverse Parity GroupO, Byte B, Address
Reverse Parity GroupO, Byte c, Address
Unused
Reverse Parity Groupl, Byte 3 Data
Reverse Parity Groupl, Byte 2 Data
Reverse Parity Groupl, Byte l Data
Reverse Parity Groupl, Byte 0 Data
Reverse Parity GroupO, Byte 3 Data
Reverse Parity GroupO, Byte 2 Data
Reverse Parity GroupO, Byte l Data
Reverse Parity GroupO, Byte 0 Data

..,.

0
0
0
0

0
0

0
1

l
1

0
1

1
1
1
1

1
1

0
0
0

0
0

l
l

0
0

1
1

l
l

0
0
0
0

0
l

l
1

l
l

0
1
0
1

0
l
0
l
0
1

-----------

CACHE-SBI-TB SUBSYSTEM

Page 7-:23

Bits 31 & 11
While these bits are set, the appropriate parity generator in
the SBI interface is reversed. The SBI interface must be
forced to transmit to force this FAULT on the SBI.
Bit 30
While this bit is set, all writes done by the ·SBI interface
will cause a write sequence FAULT. This is done by changing
the WRITE DATA TAG to the TAG reserved for diagnostic use.
Bit 29
While this bit is set, the SBI interface will transmit TAG=O
(read data), ID=Maintenance ID, DATA=undefined, parity ok.
This will cause unexpected read data FAULT in the NEXUS
selected by the maintenance ID.
Bit 28
While this bit is set, multiple transmitter FAULT can be
forced in any NEXUS. For NEXUS other than the CPU, the error
is forced by reading the NEXUS -configuration register. After
the
command address transfer specifying read, the CPU
transmits the conditions specified under bit 29, except the
TAG which is transmitted as 111, the reserved TAG. When the
NEXUS returns the read data, with ID=CPU ID, that NEXUS will
have a multiple transmitter FAULT (provided that maintenance
ID was set to a value that would cause an ID mismatch to
occur).
The CPU has this error forced by doing a write command.
The
CPU ID will be transmitted for the command address transfer.
The maintenance ID will be transmitted with the write data.
When the received ID is compared against the CPU ID, after
the write data transmission, a mismatch will occur resulting
in a multiple xmitter FAULT.
Bits 21-23
These are the maintenance ID bits. They are used for forcing
unexpected read data FAULTS, forcing multiple transmitter
FAULTS and as a compare field for the Silo Comparator.
Bit 22
Setting this bit forces writes done by the CPU on the SBI
become a write invalidate to the CACHE.

Page 7-24

CACHE-SBI-TB SUBSYSTEM
Bit 21

When this bit is set write invalidates from the SB! are
allowed. When this bit is "O" write invalidates from the SB!
are ignored.
This bit must be on for normal
system
operation.
Bit 17-20
These bits are the reverse CACHE Parity Field. Setting this
field to a specific code causes the indicated byte to have
its parity bit continously asserted. To force the error trap
the appropriate CACHE operation should be initiated.
Bits 16-15
These bits provide a method of forcing misses in the CACHE.
Misses are not forced for write operations. This prevents
the CACHE data from becoming stale.
The bits have . the
following meaning.
BIT

FUNCTION

16 15
0
0
1

0
1
0

No misses forced
Force miss on Group 1
Force miss on Group 0
Force miss on Group 1 and Group 0

Misses are forced only for read requests for the Data Path or
instruction buffer.
Misses are not forced for write or
invalidate operations. Setting these bits will also cause
parity errors to be ignored.
Bits 14-13
Normally, replacement in the CACHE is
provide for overriding the random bit.
BIT

CACHE REPLACEMENT

14 13
0
0
1

0
1
0

Random
Group 1 always
Group 0 always
Undef i.ned

random.

These

bi ts

CACHE-SBI-TB SUBSYSTEM

Page 7-25

Bit 12
While this bit is set, no SBI cycles will be started.
For
read operations with a CACHE miss, the data in the D register
will be unpredictable.
Bits 10-9
These two bits are clocked every time there is· a read request
for the Data Path or the instruction buffer that results in
(1) a CACHE Hit or (2) an SB! cycle started due to a CACHE
Miss. (approximate)
Bit 8
This bit provides a mechanism for forcing timeouts on a read
operation.
This is done by loading the timeout counter with
'FF' after the read command has been accepted.
IE

CACHE PARITY ERROR REG
The bit definitions for this register are listed below:
BIT #

-----

DESCRIPTION

-----------

TYPE

31-16
15
14
13
12
11

Not used
Any Parity Error
CP Parity Error
Parity OK CDM Group! Byte 0
Parity OK CDM Group! Byte 1
Parity OK CDM Groupl Byte 2
Parity OK CDM Group! Byte 3
Parity OK CDM GroupO Byte 0
Parity OK CDM GroupO Byte 1
Parity OK CDM GroupO Byte 2
Parity OK CDM GroupO Byte 3
Parity OK CAM GroupO Byte 0
Parity OK CAM GroupO Byte 1
Parity OK CAM GroupO Byte 2
Parity OK CAM Groupl Byte 0
Parity OK CAM Group! Byte 1
Parity OK CAM Group! Byte 2

R
RWCL
R
R
R
R
R
R
R
R
R
R
R
R

10
9
8
7

6
5
4
3
2

1
0

R
R

Bit 15

------

This bit will set any time a CACHE parity error is detected
on a IB or CP read operation. Writing a "l" to this bit
position forces O's in all positions of the register (same
~tate as on power up).

CACHE-SBI-TB SUBSYSTEM

Page 7-26

Bit 14
When bit 15 is set, this bit signifies whether the CACHE
parity error was for the CP, Bit 14=1, or the instruction
buffer, bit 14=0.
Bits 13-0
When bit 15 is set, these bits identify the CACHE bytes which
did not have an error.
NOTE
This register will clear if it is holding a parity
error for the instruction buffer and the instruction
buffer is flushed.

ID REGISTERS "ON" TBM BOARD

ADRS
HEX
31
10

TB DATA
WRITE ONLY

27 26

PROTECTION
CODE

A
L
I
D

21 20

PHYSICAL ADDRESS PAGE FRAME NUMBER

MUST BE ZERO

SEE VAX 11/780 ARCHITECTURE HANDBOOK
31

21 20

18 17

16 15

FORCE TB
PARITY ERROR
CODE

M
M
E

-----------------------------------------------------------------------------------------------------R
LAST REFERENCE WAS:
I
E B

TB REG 0

p 0

L T
A H

SEE

FORCE TB
REPLACE
CODE
Gl I GO
I
I
I

FORCE TB
MISS
Gl I GO
I
I
I
I

u
F

A
D

I
B

w
c

ff
K

I
I
I
I TBI TBI
A I Gl I GOI 0
R IHITIHITI
I
I
I
I
I
I
I
I
I

CACHE SUBSYSTEM SPEC
R/W-------------------R/W--RO-----------------------------------RO--RO--R/W-----------R/W

"NORMAL" USE

-------->

!NIT

----->

x
x

21 20

x
x

9 8

x
x

1 (ON)

------------------------------------------------------------------------------------------------------I PA INFO
TB PARITY ERROR BITS
ILASTI
I
I
I
I
I CPI
13

REG 1

GROUP--> I 1
A/D --> I D
BYTE--> I 2
I
I
I

SEE CACHE SUBSYSTEM SPEC

I 0
I D
2 I 1
I
I
I

I 0
I D
I 0
I
I
I

I 1 I 1 I 1
I A I A I A
I 2 I 1 I 0
I
I
I
I
I
I
I
I
I

0 I TBI 0
A IPARI
0 IERRI
I
I
I
I
I
I

I TB
I WP
I
I
I
I

I
I
I
I
I
I

IBADI M IP EIP EIA LI
IIPA I I IA RIR RIU OI
I s IR RIO RIT Al
I
I
I s II IT IO DI
IT I
I
I
I
I
IY I
I
I
I
I

READ ONLY EXCEPT ANY WRITE TO THIS REGISTER CLEARS

--> I
!NIT ------->

THESE BITS
0

ID REGISTERS ON SBI BOARD
31

I
18 SBI SILO
!NIT UNPREDICTABLE

SBI
ERROR

INIT

TIMEOUT
ADDRESS

22 21

SBI
I
I FAULT I INTLK I
I
I
I

16 15

NOT USED, ZERO

25 24

I AFTER I

31
19

SBI ID

I
I SBI M3-MO OR
I
831 - B28
I

SBI
TAG

18 17

16 15

I
I
SBI
I CNFl-0
I

SBI TR<l5:00>

I
I MODE
I
l
I

I
I MODE
I
0
I

IRDS I C IR I
I
I
I
I CP I I B I I B I I B I I B I I BI
I
I
I
!INTI R I D I CP I TOI TOI ZERO IERRIRDSI TO I TOI TO IERRIMULTINOTIZEROI
I ENI DI SI TO ISTllSTOI
ICNFI
I
ISTll STOICNFIERR IBSYI
I

0<---------------0--------------------------------------------------------->

I
I
I
I

PROT
CHK

28 27

PHYSICAL ADDRESS<29:2>
0

!NIT UNPREDICTABLE

31 30 29

FAULT/
STATUS

CLEAR ON !NIT

I
I
I
I
I
I
I
I
I
I
I
I
I
I FLT I
I FLT I
IPTYI 0 IUNEXI 0 I MLTIXMITI 0 I 0 I 0 I 0 I 0 I 0 IFLTIINTIFLTISILOI
I FLT I
I RD I
I XM IT I FLT I
I
I
I
I
I
I LTH I EN IS IG I LCK I

NOT USED, ZERO

27 26

23 22 20 19

I CMP I
I
I COND I
I SILO I INT I LOCK I LOCK I COMPARE !COMP !COUNT I
I LOCK I EN IUNCONDI CODESICOM OR MASKI TAG !FIELD I

COMPARATOR

NOT USED, ZERO

CLEAR ON INIT
lD

SBI MAINTENANCE

23 22

17 16

I REVfWRTI UNfMULTf
IFORCEI ENI
REV
IFORCEIFORCEIFORCEIFORCEIDISI REVfGRP IGRP IFORCEI
IP<O>ISEQIEXPIXMITI MAINT ID I SB! fSBif CACHE PARI MISS! MISS! REP I REP fSBIIP<l>I 1 I 0 I TO I NOT USED, ZERO
I
fFLTI RDI
I
I INV IINVI
I GRO I GRl I GRO I GRl ICYCI
IMTCHIMTCHI
I
CLEAR ON !NIT
31

IE CACHE PARITY

CLEAR ON !NIT

16 15

NOT USED, ZERO

ANY
PTY
ERR

CP
ERR

PARITY OK FIELD

CACHE-SBI-TB SUBSYSTEM
7.18

Page 7-30

GENERAL DESCRIPTION

The Translation Buffer is 64 entries deep, two way associative.
Virtual address bits 14 thru 9 are used as the index. This cache
translates addresses in the VA register for microcode requested
cycles, and translates addresses in the VIBA for automatic reloads of
the IPA (Instruction Physical Address) register.
This cache is
bypassed for physical address references or when MME bit is off.
The IPA keeps a pretranslated copy of the VIBA (Virtual Instruction
Buffer
Lookahead
Address)
to
prevent the waste .of repeated
translation. The IPA and VIBA are counted in step.
When the IPA
counts accross a page boundary, prefetching is prevented until the IPA
is automatically reloaded.
The reload is controlled by hardware
sequencing logic which will start the reload during any ALLOW.IS.READ
microcycle. The reload is completed in the following cycle. If this
cycle requested a memory operation it is stalled for 200 nanoseconds.
Once the reload is completed, prefetching will start again, unless a
miss or other error occurred during the reload. In this case the IB
will eventually run out of data and notify the microcode of the error.
Note that the reload sequence occurs even if MME is not on.
The IPA can be loaded by microcode using the READ.V.NEWPC command.
This is normally used when macrocode transfer of control occurs or
when prefetching has stopped because of a translation miss and a new
entry has been put in the TB.
When a memory cycle is to be performed, the appropriate address (VA,
IPA, or translation)
is selected by the PAMUX onto the PA BUS. The
data cache uses addresses on the PA BUS to search for data.
The Data Cache is two-way associative.
Each group contains 1024
long-word entries. One address is stqred for each two long-words (one
quad-word). If a hit occurs, the appropriate long-word is transmitted
on the MD BUS.
If a miss occurs, the quad-word containing the
requested data is brought in from memory and placed in the cache (the
appropriate long-word is also transmitted to the requestor). If the
requested data is in I/O space instead of memory, only the appropriate
long-word is read in, and it is not placed in the cache.
The replacement strategy is RANDOM.
This means that when a new
quad-word block is brought into the cache, it is placed in one group
or the other as a random selection, not according to the previous
entry's age or other characteristic.
The write strategy is write-thru, and not-write-allocate.
Write-thru
means that any write data transmitted from the CPU to the cache is
immediately passed along to main memory.
Not-write-allocate means
that if the CPU transmits write data and a corresponding entry is not
present in the cache the data is simply sent to memory with no new
entry being made in the cache.

CACHE-SBI-TB SUBSYSTEM

7.19

Page 7-31

MICROCODING SUGGESTIONS
A.

To prevent auto-reloading of the IPA:
1.

An auto-reload will not start if an ALLOW.IS.READ (either
type) is not used.

If a page boundary has not been crossed already, it will
not be crossed if the IB cannot count the IPA, which will
not happen if the IB is stopped.

A FLUSH of the IB will stop any auto-reload.

Do not meddle with the VIBA anytime that an
happen.

auto-reload

After a new entry is placed in the TB as a result
miss, a READ.V.NEWPC is required to load the IPA.

Do not do FLUSH and READ.V.NEWPC in the same microstate.

Writing any of this subsystem's ID registers while a
operation is in progress is strongly unrecommended.

The microcommands in this
subsystem's
hardware
error
microtraps should contain NOP until the IB can be turned off,
to reduce the likelihood of multiple errors, and until ID REG
12 is saved, to prevent loss of information.

Cache error registers should be read out, saved, and
before doing any more memory references on errors.

Remember that FLUSH clears out certain IB error information.

Remember that all
microcommands
for
explicit
memory
operations use the address in VA, including READ.V.NEWPC.

Do not change the VA register in a memory
reference
microstate.
Do not change D register in a write microstate.
There may be restrictions on the D register clock control
field of read microstates, see the data path spec.

When using the INVALIDATE microcommand to clear the cache,
use long-word context.
Both groups are cleared at once. All
1024 combinations of address bits 11 thru 2 must be cleared.

When clearing the TB, set the Replace Both bit and send an
all zero word to the TB. For a complete clear, use all 64
combinations of address bits 14 thru 9.

may
IB

memory

cleared

Page 7-32

CACHE-SBI-TB SUBSYSTEM
M.

The MBZ bits in entries for the TB must be zero.

Many of the force error bits in this subsystem are meant for
microdiagnostics only and will hang the system if set by
macrocode.

Remember that finding one error bit set somewhere does not
mean there are no other errors.
Due to the independent
asynchronous operation of the IB, many interesting error
combinations are possible.

The system will not run if misses are being forced on both
groups of the TB.
It will run with misses forced on both
groups of the data cache.

Make sure that an autoreload is not in progress and does
start when reading or writing any TB ID register.

not

Do not reset the CRD or RDS bits if an SB! cycle is still
progress for the IB.

Do not read silo data when the silo is not locked.

Do not change the current mode bits in
memory reference is being requested.

u.
v.

Do not request a READ.V.NEWPC unless prefetching is stopped.

Because of the UNIBUS DATIP problem, the first WRITE.V
following a READ.V with write check must be the corresponding
write unless the read is aborted.

Do not set or clear MME without preventing AUTO-RELOAD.

Do not reset timeout
progress.

bits

SBI

the

cycle

PSL

while

still

any

CHAPTER 8
VAX 11/780 CONSOLE SUBSYSTEM

The VAX
11/780
console
subsystem
consists
of
four
major
components: an LSI-11 microprocessor (KD-llF), which includes 4K of
RAM; a single floppy disk and controller; a terminal and two serial
interfaces, one for remote capability; and a CPU/console interface
(CIB) which includes 2K or 4K of ROM.
The console system provides three major functions:
1.

Traditional "lights and switches" functions such as
deposit, halt, start, single instruction, etc.

examine,

Diagnostic
functions,
including
the
and
maintenance
capability to load diagnostic microcode into WCS, control
execution, and monitor results; control single step clock
functions;
and examine key system points via a serial
diagnostic bus.

Materialize the terminal
I/O registers in the processor
register space.
In the VAX 11/780 system, these register are
on the ID bus and are in reality a mechanism by which VAX
11/780
microcode
and LSI-11 software can communicate.
Therefore, this same port is also used for floppy I/O
transfers and any other (software defined) communication.
(See Appendix)

The functions in items 1 and 2 are implemented at the user level by a
set of keyboard commands and responses at the terminal.
The LSI-11 in
turn controls the VAX 11/780 CPU through a set of control/status and
data registers in the Q-bus I/O space, which connect to the ID bus,
the V-bus (the serial diagnostic bus) and many internal points in the
CPU.

I \
I

IU
IS
I
I
I
I
I
I
I
I
I

c
s
E
Q

u
E
N

\ I

I \

I \
II

........

'......

N
T

CX>

(')

\ I

t-'

\ I

l:IJ

-----------------------------I

I
CONSOLE/CPU
I
INTERFACE _________ I

en
t<
en

2K/4K I
ROM I

I
I

O:J

l:IJ

----------------------------I I
I I
I I
___________________________ I I ___________________

Q-BUS

I ~------------1 1------------1 1------------1 I- - - - -

I I
I I
I I

LSI-11

I I
I I
I I

I
I
I
I

4K MEM

I I
I I
I I

RXV-11

DLV-11

FLOPPY
CON TR!..

(OPT)

I I
I I
I I

*********

*
* RXOl
*

DLV-11

*
*
*

TErMINAL

*********

Figure 8-1

I
I I
I I
I I
I I

EIA CONNECTION
FOR REMOTE TMNL

VAX 11/780 CONSOLE SUBSYSTEM
8.1

Page 8-3

THE CONSOLE/CPU INTERFACE

The Console Interface Board (CIB) is a board in the CPU backplane.
It
contains a Q-bus interface, an ID~bus interface and termination, and
all the necessary hardware to implement the various control functions
needed.
In addition a Read-only memory of either 2K X 16 or 4K X 16
is provided for the "core" of the console LSI-11 software. There is,
of course, a method by which the LSI-11 can force microcode execution
at any microaddress. This mechanism is used to call various console
service
microroutines.
Also,
physical
memory references are
accomplished by using the virtual reference mechanism,. but· with the
Memory Mapping Enable (MME) bit turned off.

FUNCTIONS IMPLEMENTED BY CIB

FUNCTIONS IMPLEMENTED BY MICROROUTINES
Virtual examine byte, word, longword
Virtual deposit byte, word, longword
Examine general registers
Deposit general registers
Examine processor register
Deposit processor register
Continue
Initialize TB, cache, etc.
Quad clear
SBI unjam
FUNCTIONS IMPLEMENTED BY HARDWARE
Stop clock
Start clock
Step one time state

(result of CPU initialize signal)

Page 8-4

VAX 11/780 CONSOLE SUBSYSTEM
Step one SB! cycle (stops in CPU TO)
Select one of four clock frequencies
Assert CPU initialization signal
Interrupt VAX CPU (terminal registers)
Halt at end of current instruction
Step single instruction
Stop clock upon microbreak match (in CPTO of match state)
Force UPC<l2> to WCS on microtrap
Force NOP on selected ROM fields
Clock VBUS
Assert VBUS loopback bit
Load VBUS registers
Read VBUS serial channels

Sense positions of auto-restart, boot, lock, and remote switches
Time-out off VAX 11/780 interrupt strobe signal,
run light

use

assert

Provide a write-only register
responder)

the

bus

(FM

ID)

(as

Provide a read-only
responder)

the

bus

(TO

ID)

(as

and

clock

Write to any ID bus address (requires console control
running)

Read any ID bus address (when clock is stopped or running)
Synchronize use of FM ID and TO ID via ready & done bits
Read clock states

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-5

Sense assertion of console acknowledge (reply to halt request)
Sense when system clock is stopped
Maintenance return (forced jump to UPC off top of microstack)
Turn floppy disk power on or off
Read ID address and direction lines (clock stopped only)
Materialize JMP into ROM at 173000 and 173002
The capability to read/write at any ID address permits
accesses to implement the following functions (and others).
Push microstack
Pop mic rostack
Write microbreak
Read microbreak
Read WCS address
Write WCS address
Write WCS data
Read WCS status

Page 8-6

VAX 11/780 CONSOLE SUBSYSTEM
8.2

ID BUS REGISTERS ON CIB

All of these registers except the SYS.ID register are essentially
dual-ported between the ID bus (for VAX 11/780 access) and the Q-bus
(for LSI-11 access).
This section describes the appearance of the ID bus registers on the
VAX 11/780 side of the interface, i.e., as seen by VAX 11/780
microcode. The appearance of these registers to the LSI-11 is
described in section 4.0.
The CIB as 5 ID bus addresses assigned, from 3(16) to 7(16).
------------------------------~----

SYS. ID

SYS ID< 31 : 0 >

R/O

I RX I RX I
I DNE I IE I

RXCS

TO ID(RXDB) R/O

R/W

TO ID<31:0>

I TX I TX I
I RDY I IE I

TXCS

FM ID(TXDB)

R/W

W/O

FM ID<31:0>

ID registers as seen by VAX 11/780 microcode
Figure 8-2

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-7

ID03

System Identification SYS ID is a read only register used to materialize the system
ID register in the procreg space.
CExact format is TBS) •
The 32 bits come out to pins for backpanel switches. Pull-up
resistors are provided on the board.

ID04

Receiver Control/Status register
The RXCS is used to materialize the RXCS for the terminal
receiver data buffer in the procreg space, and to syncronize
data transfers from the LSI-11 to microcode through the TO ID
register.
RXCS<7> - Receiver Done (RX DNE) - R/O
Set by the LSI-11 to indicate to microcode that valid
data is available in the FM ID register. Cleared
automatically by the hardware when the TO ID register
is
read
on
the
ID
bus.
Cleared by system
initialization.
RXCS<6> - Receiver Interrupt Enable (RXIE) - R/W
When set, enables an interrupt at IPL 13 and vector CC
to the VAX 11/780 CPU.
(See Interrupts and Exceptions
specification), each time RX ONE makes a transition
from 0 to 1. Only one interrupt for each transition is
generated.
If RX DNE is already set and RXIE goes from
a 0 to a 1, the interrupt will also occur. Cl~ared by
system initialize.

!DOS

To ID register (TO ID) - R/O
(Note:

"To" and "From" are with respect to the LSI-11).

Contains up to 32 bits of data from the LSI-11, to be read by
microcode.
Valid only when RX DNE is set. Reading TO ID on
the ID bus automatically clears RX ONE.
ID06

Transmit Control/Status (TXCS) - R/W
The TXCS is used to materialize the TXCS for the terminal
transmit data buffer (FM ID) in the space, and to synchronize
data transfers from microcode to the LSI-11 through the FM ID
register.
TXCS<7> - Transmitter Ready (TX RDY) - R/O
Set by the LSI-11 to indicate it is ready to accept
another
character in the TXDB
(FM ID)
register.
Cleared automatically by a write to the FM ID on the ID
bus; cleared by system initialize.
TXCS<6> - Transmit Interrupt Enable (TXIE) - R/W
When set, enables an interrupt at IPL 13 and vector C4
to the VAX 11/780 CPU, each time TX RDY goes from a 0
to a 1.
Only one interrupt occurs for each 0-1
transition.
If TX RDY is already set and TXIE makes a
0-1 transition, the interrupt will also occur. Cleared
by system initialize.

VAX 11/780 CONSOLE SUBSYSTEM
ID07

Page 8-8

From ID register (FM ID) - W/O
Loaded by microcode with up to 32 bits of data to be passed
to the LSI-11. Should be loaded only when TX RDY is a "one".
Writing to FM ID on the ID bus will automatically clear
TX RDY.

Use of the TO ID and FM ID registers
Under normal circumstances, when the VAX 11/780 CPU is running, only
the 16 low bits of the FM ID and TO ID are used, and all references to
the RXCS, TO ID, TXCS, and FM ID are the result of microcode
interpretation of MFPR's and MTPR's. For MTPR and MFPR references to
TO ID and FM ID, microcode does not test the state of
the
corresponding READY or DONE bits prior to referencing the data
register; to do this would affect interrupt latency time.
It is
assumed under these circumstances that macro level instructions have
already tested the synchronizing bits.
When the CPU is halted (i.e., in the console wait loop) microcode uses
the same two registers (this time all 32 bits) to pass parameters
to/from LSI-11 software. For any references other than MFPR's and
MTPR's,
it is microcode's responsibility to test the appropriate
synchronizing bit prior to referencing the register. The bit must be
a "one" before the read or write can take place.
Since the LSI-11 has no knowledge qf the state of the TXIE and RXIE
bits, a mechanism is provided to disable these interrupts to the VAX
11/780 and inhibit any change in the state of the "interrupt pending"
flops while the console is in control and using the TO ID and FM ID
registers for examines, etc.
It should also be understood that the TXCS and RXCS bits are totally
divorced from the corresponding bits in the DLV-11.
In program I/O
mode, the LSI-11 simply passes data from/to the CIB, to/from the
DLV-11.

8.3

THE Q-BUS REGISTERS

This section describes the functions and appearance of the registers
on the Q-bus which the LSI-11 uses to control and monitor the CPU and
handle data transfers and control of the ID bus.
For the breadboard, this block of addresses starts at location
173000(8).
However, a block of 16 addresses has been assigned to the
CIB, starting at 163000(8). A wire jumper will permit selecting which
address group is used.

Page 8-9

VAX 11/780 CONSOLE SUBSYSTEM
Read-only memory
There will be either 2K words or 4K words of ROM starting at Q-bus
address 140000(8) and running to either 147776(8) or 157776(8). This
memory will contain the "core" of the console operating system, which
includes power up routines, drivers, look-up tables, and basic areas
of functionality such as examine, deposit, halt, etc.

foe

::>

r.::a
::E:

....

'a:

0::

foe

--1
10

'a:

'a:
1---1
10
I

.......

U")

.......

U")

.......

<
foe
<
Cl

<
<
Cl

....

<
foe
<
Cl

::E:

.......
::E:

0::

U")

.......

I U")
I
I r-t
I
1---1

1---1
10
I

r.::a
0::

<
0..
Cl)

foe

1---1
10
I

r.::a
::E:

I U")
I
I r-t
I
1---1

I
I
1--

I U")
I r-t

I
I

::c

<
foe

I
I
I
I
I

I U")
I r-1

I
I

r.::a

a:
<
0..
Cl)

....

0
..J

r.::a
0::

I
I
I
I
I

I U")
I r-t

r.::a
0::

.......

0
0::

<
0..

0::

Cl)

0
0
0

<QI

0
0

0
.......
0

0
0

.......

::E:

<
0..

.......
0

lX3014

RX
I
ONE I

RX DONE

R/W
......
......

....J

1X3016

TX I
ROY I

TX READY

R/W

I
15

Q-bus Registers, low 8. X=6 or 7
Figure 8-3

1X3020

TO ID<l5:0>

TO ID LO

1X3022

TO ID H

TO ID<31:16>
15

lX3024

FM ID LO

·I
I
I

R/W
0

FM ID<lS:O>
15

1X3026

R/W

FM ID HI

R/O
0

FM ID<31:16>
15

R/O
0

1X3030

ID C/S

<
>

I
I
ID I REC I
REC
I
ID I
ID I
I CYCLE I WRITE I ID ADDRS<S:O> I MAINT I WRITE I
I
I
I
I
I
I

ID ADDRS<S:O>

.....
.....

R/W

.........

.......

1X3032

8 7

0
(')

MCR

I
I\
I\
I
I HLT I \
I \
I CPU
I REQ I
\
I
\
I RESET
I
I
\I
\I

I\
I
I TRAP I STAR
J
I \
I MAINT I TO I INTR I ROM I SOMM I CLK I FREQ
I \ I RTN I WCS I DISAB I NOP I
I STPD I
<l>
I
\I ENABLE I
I
I
I
I
I

15
14
13
1X3034 MCS

I
I FREQ
I <O>
I

I
I STS
I
I

I
I
I
I SBC I PRO- I
I
I CEED I
I
I
I

R/W

0
t""
ts.I

°'

en
t<

"i
ts.I

I\
I\
I\
I FLPY I
I\
ICNSLI
I HALT I RDY I ONE I\
I\
I AUTO I RE- I
I \
J \
I \
I OFF I BOOT I \
ICMNDI RUN I STATE I IE I IE I \
I \
I RST. I MOTE I LOCK I
I \ I \ I \ I
\ I MODE I
I
I
I
\ I \ I
15

R/W

--------------------------------------------------------------------~------------

1X3036

VBUS SER CHNL<7:0>

V-BUS
15

8 7

Q-bus Registers, high 8. X=6 or 7
Figure 8-4

I
v
I
v I v I
I SLFTST I LOAD I CLK I

I CPT I CPT I CPT I CPT I
I o I 1 I 2 I 3 I
6

R/W

VAX 11/780 cm .'~.~

SUE~Y~TEM

Page 8-12

Control/Data registers (refer to Figures 8-3 and 8-4)
00.
02.

ROMO - Read only memory 0 - R/O
ROM! - Read only memory 1 - R/0
These two registers, at 173000(8) and 173002(8), will contain a
JMP X instruction to the LSI-11, where X is the starting location
of the power-up code in the ROM. These two words are physically
ROM locations 0 and 2, which therefore also appear at addresses
140000 and 140002. The LSI-11 will be configured to fetch at
173000
{a jumper option) upon power up, to execute the jump into
the power-up code.

04.

spare - Unused, will time-out if referenced.

06.
10.

ID bus data<lS:O> - ID DATA LO - R/O
ID bus data<31:15> - ID DATA HI - R/O
These two registers provide visibility directly to the received
data on the ID bus, and are valid only when the clock is stopped.

12.

Spare - Unused, will time-out if referenced.

14:

Receiver Done - RX DONE - R/W
RX DONE<?> is the "backside" of the RX ONE bit in the RXCS
register.
It is set by the LSI-11 to indicate to the microcode
that valid data has been placed in the TO ID register.
It is
cleared automatically by a read reference to TO ID on the ID bus,
or by system initialize. The 1-->0 transition of RX DNE will
interrupt the LSI-11, if enabled.

15:

Transmitter Ready - TX READY - R/W
TX READY<?> is the "backside" of the TX RDY bit in the TXCS
register on the ID bus. When set by the LSI-11 it indicates to
VAX 11/780 microcode that the LSI-11 is ready to accept another
longword in the FM ID register.
It is cleared automatically by a
write reference to FM ID on the ID bus, or by system initialize.
The 1-->0 transition of TX ROY will interrupt the LSI-11, if
enabled.

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-13
NOTE

1) The LSI-11 has no visibility to the
VAX 11/780 interrupt enables, TXIE and
RXIE.
2)
If the clock is running, clocking RX
DNE and TX RDY from Q-bus data is done
at CPT60-CPT90.
THus, these bits will
be stable at CPT200 when read on the ID
bus. This is so microcode can be in a
tight loop on ROY or DNE setting and the
LSI-11 can set the bit from the Q-bus
during
reference on the ID bus to the
same bit.
3) TX RDY
and
RX
ONE
are
not
automatically set by a reference on the
Q-bus to FM ID or TO ID; they must be
explicitly set by the LSI-11.
20:
22:

To ID register, low half - TO ID LO - R/W
To ID register, high half - TO ID HI - R/W
These two registers contain the 32 bits which microcode will read
(into the Q-register in the CPU) when doing a read reference from
ID bus address 05(16). See the TO ID register. The data in TO
ID LO and TO ID HI is also the data placed on the ID bus during
an ID bus write cycle invoked by the ID C/S register.
They are
readable for diagnostic purposes.

24:
26:

From ID register, low half - FM ID LO - R/O
From ID register, high half - FM ID HI - R/O
These two registers permit reading data loaded
into the FM ID
register on the ID bus as a result of a write reference to ID
address 07(16).
In addition the FM ID LO and FM ID HI registers
are loaded with the ID bus data during an ID bus read cycle
invoked by the ID C/S register.

30.

ID Control/Status - IDC/S - R/W
The IDC/S is used to monitor the ID address and direction lines,
(see ID bus specification) and control console-generated ID bus
cycles directly. Combined with the ID DATA registers, the TO ID
registers, and the FM ID registers, it permits reading or writing
any ID address while the clock is running or in single step mode,
and
reading any ID address when the clock is stopped. Note that
writing ID registers still requires stepping the clock if it is
not running.
IDCS<lS> - ID CYCLE - R/W

Page 8-14

VAX 11/780 CONSOLE SUBSYSTEM

When written as a 1, ID CYCLE will cause ID MAINT to be asserted
for one clock cycle (CPTO to CPTO) if the clock is running, or
asserted at the next CPTO if single stepping.
ID CYCLE is
cleared automatically at the end of the ID cycle; therefore, the
LSI-11 will normally read it as a zero, unless stepping in single
time state mode. See ID MAINT description.
IDCS<l4> - ID REC WRITE - R/O
IDCS<l3:8> - ID REC ADDRS<S:O> - R/O
These 7 bits allow reading the state of the ID bus left address
and direction lines, and are valid only when the clock is
stopped. NOTE: Due to receiver inversions, these bits will be
read as the complement of the logical state of the corresponding
bus wire. On these lines, logical 1=+3V, which will be read as a

IDCS<7> - ID MAINT - R/W
ID MAINT will assert automatically at the next available CPTO
following writing a 1 to ID CYCLE, and remain asserted until the
following CPTO, when it is cleared. This bit steers the MUX in
the CPU which selects the source of the ID bus address and WRITE
lines from the CPU or the console. During the time ID MAINT is
asserted, the ID bus address and WRITE lines will be sourced from
IDCS<6: O>.
If the CPU clock is running, ID MAINT is read only, and writing
to it has no effect. Note that if the clock is running, it would
be read as a 0 by the LSI-11 since it is asserted only for a 200
nanosecond cycle.
If the CPU clock is not running (i.e., CLK STOPPED is set - see
MCR description) , then the LSI-11 may set and clear ID MAINT by
writing a one or zero to it. Note that this permits statically
reading ID registers via the ID DATA registers.
The address and WRITE fields may be loaded in the
instruction that writes a "one" to ID CYCLE or ID MAINT.
Both ID CYCLE
initialize.

and

MAINT

are

cleared

LSI-11

same
system

IDCS<6> - ID WRITE - R/W
IDCS<S:O> - ID ADDRS - R/W
These bits are loaded with the address and direction to be used
during an ID cycle invoked by ID CYCLE, or while ID MAINT is
asserted. IDC/S<6>, the WRITE bit, should be set to invoke a
write cycle, and cleared to invoke a read. The ID ADDRS bits are
loaded in true form (unlike the REC ADDRS bits, which are read
inverted).
In addition, these bits are cleared by LSI-11
initialize.

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-15

For writes, data is sourced from the TO ID registers. For reads
(static)
the data is read in the ID DATA registers, while for
dynamic reads the data is available in the FM ID registers
following the cycle.
See details on use of the IDC/S.
32:

Machine Control Register - MCR - R/W
NOTE
R/Wl indicates a bit that is readable;
to clear it, a "one" is written to that
position.

MCRlS - Halt Request - HLT REQ - R/W
Set by the LSI-11 to force microcode to the console wait loop.
The VAX 11/780 CPU will recognize this request and set a HALT
PENDING flop.
Upon passing through the IRD state, if the HALT
PENDING is set, microcode will set a Console Command Mode
(CNSL CMND MODE)
bit and enter the console wait loop,
indicated by the assertion of HALT STATE (see MCS bit 7). A
microcode CONTINUE function,
invoked by the console, will
reset both the HALT PENDING flag and CNSL CMND MODE, and enter
IRD.
If HALT REQ is still set, HALT PENDING will again set,
but not until leaving IRD.
Hence, a CONTINUE with HALT REQ
set results in a single instruction execution.
To resume
normal
instruction execution, the LSI-11 must first clear HLT
REQ, then issue a CONTINUE function.
Cleared by system
initialize.
NOTE
Microcode can branch on the state of the
CNSL CMND MODE bit.
This is so that
microcode can tell, in various error
routines,
whether
the
routine was
entered
as
a
result
of
some
console-requested
function or normal
machine execution.
MCR14 - Reserved
MCR13 - Reserved
MCR12 - CPU reset - CPU RESET - R/W
When set, CPU RESET will force assertion of the
(DC LO
equivalent)
internal
initialization
signal.
Upon
de-assertion, microcode will enter the power-up initialization
microcode.
Cleared by LSI-11 system initialize.

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-16

MCRll - Reserved
MCRlO - Maintenance return enable - MAINT RET ENABLE - R/W
Writing a "one" to this bit causes a maintenance return.
Specifically, the top element of the microstack is popped and
J-field inputs are disabled. The result is a forced jump to
the address on the top of the microstack. The actual signal
to the microsequencer is asserted from approximately CPTlSO to
CPTSO.
If in single time state mode, MAINT RTN ENABLE will
remain asserted from the time it was written as a "one" until
the next CPT150 state is entered, when it will clear.
NOTE
The console should not attempt a MAINT
RET function unless the CPU is in the
console wait loop.
MCR9

- Trap to writable control store - TRAP TO WCS - R/W
When set, TRAP TO WCS will force bit 12 of the UPC to a "one"
whenever a microtrap occurs, to force the trap into wcs.
Should be set or cleared only when in the halt state or clock
is stopped. Cleared by LSI-11 initialize.

MCR8

- VAX 11/780 Interrupt Disable - VAX 11/780 INTR DISAB - R/W
This bit, when set, disables the TX ROY and RX DNE interrupts
to the VAX 11/780 CPU, regardless of the state of the TXIE and
RXIE bits. Furthermore, it inhibits any change of state of
the interrupt pending flops (on the CIB) in the terminal
interrupt control logic. This bit is necessary to allow use
of the ID registers and ROY and ONE bits for console functions
without causing extraneous interrupts to the VAX 11/780 CPU.

MCR7

- Rom no-op - ROM NOP - R/W
This bit, when set, generates CLR UWORD and ABORT CYCLE in the
microsequencer. This has the same effect as a STALL, to force
NOP's on the various subsystem control fields so that random
patterns from WCS will not produce undesired side effects
during testing. If set while the clock is stopped, it is
necessary to step to a CPTO before the effect of ROM NOP will
be felt. Cleared by LSI-11 initialize.

MCR<6> - Stop on microbreak match - SOMM - R/W
When a match is detected between the microbreak register and
the UPC, if SOMM=l, the clock is stopped in CPTO of the cycle
in which the match is occurring, and CLK STPD will be
asserted. Cleared by LSI-11 initialize.

Page 8-17

VAX 11/780 CONSOLE SUBSYSTEM
MCR<5> - Clock Stopped - CLK STPD - R/O

This signal originates in the clock control logic and
is set
when the clock is not running. The signal will be negated for
one clock step or one cycle when either single time state or
single cycle is stepped, but the ·LsI-11 is not fast enough to
see this. However, the signal is also used in several places
on the CIB to determine whether synchronizing to the clock is
necessary or not. Cleared by LSI-11 system initialize.
MCR<4:3> - Frequency select<l:O> - FRl and FRO - R/W
These two
follows:

bits

FRl
0
0
1
1

FRO
0
1
0
1

determine

the

clock

frequency

source

10. 0 Mhz, (normal)
10.525 Mhz, 5% short
8.925 Mhz, 12% long
external source

FRl and FRO should not be changed if the
Both are cleared by LSI-11 initialize.

clock

running.

MCR<2> - Single Time State - STS - R/W
When the clock is running, setting STS will cause the clock to
stop,
in any of the four time states. As long as STS is set,
and regardless of the state of SBC, writing a "one" to PROCEED
will step the clock one time state (e.g., from CPTlOO to
CPT150). Cleared by LSI-11 initialize.
MCR<l> - Single Bus Cycle - SBC - R/N
If asserted (and STS=O) while the clock is running, the clock
will stop in CPTO.
As long as SBC is set (and STS=O), writing
a "one" to PROCEED will step the clock to the next CPTO (i.e.,
one ROM/SB! cycle}.
Cleared by LSI-11 initialize.
MCRO

- Proceed - PROCEED - W/O
Writing a "one" to PROCEED will either step the clock one time
state (if STS=l) or one cycle (if SBC=l and STS=O} or, if both
STS=O and SBC=O, will start the clock running continuously,
Writing a "one" to PROCEED when the clock is running has no
effect. Read as a zero, cleared by LSI-11 initialize.

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-18
NOTE

1) The proper method to stop the clock
is via the SBC bit, so that the stopped
state is known (CPTO).
2) CPTO=SBITl, i.e., SBI time
lead the CPU by one time state.

states

3) Clearing STS and SBC will not start
the clock.
It is necessary to write a
"l" to PROCEED, after STS and SBC are
cleared.

34:

The Miscellaneous Control and Status register (MCS)

MCS<lS> - Reserved
MCS<l4> - Reserved
MCS<l3> - Reserved
MCS<l2> - Floppy on - FLPY ON - R/W
When set, applies power to the floppy disk drive via a relay.
When cleared, removes power from the floppy. Set by LSI-11
initiali~e.

MCS<ll> - Boot - BOOT - R/Wl
Set by a 0-->l transition of the boot signal from the control
panel BOOT button.
Cleared by writing a "one" or LSI-11
system initialize.
MCL<lO> - Reserved
MCS<9> - Console Command Mode - CNSL CMND MODE - R/O
Permits reading the state of the CNSL CMND MODE bit. This bit
is set by the microcode assertion of HALT STATE, and remains
set until cleared by microcode while executing a CONTINUE
function.
MCS<S> - run - RUN - R/O
This bit is the "1° side of a retriggerable one-shot clocked
by the VAX 11/780 interrupt strobe signal, and will remain a
"l" as long as the CPU is strobing interrupts at least every
(TBS) microseconds.
While the CPU is running and executing
programs, negation of RUN generally indicates some type of
problem;
e.g., hung in a microcode loop or a hardware
failure. This one-shot is also used to light the "RUN"
indicator on the front panel.

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-19

MCS<7> - Halt State - HALT STATE - R/O
This is the raw decoded output of a ROM field, which is
asserted if and only if the microcode is in the console wait
loop. This is required because CNSL CMNO MODE, which is set
upon entry into the console wait loop, will remain set even if
microcode leaves the loop. HALT STATE therefore is used to
ascertain that microcode did return to the wait loop following
a console microcode function (other than CONTINUE), and that
microcode is in the wait loop prior to doing a console ID
cycle.
MCS<6> - Transmit Ready Interrupt Enable - RDY IE - R/W
MCS<S> - Receiver Done Interrupt Enable - ONE IE - R/W
These two bits enable the corresponding interrupt to the
LSI-11 upon a 1-0 transition of the TX ROY or RX ONE bits. If
TX ROY or RX ONE is already O, and the corresponding IE is
set, the interrupt will occur. Cleared by LSI-11 initialize.
MCS<4> - Reserved
MCS<3> - Reserved
MCS<2:0> - Panel switch sense - R/O
These 3 bits sense the position of the control panel
as follows:

switches

MCS<2> ·-Auto restart switch - AUTO RST - R/O
MCS<l> - Remote mode - REMOTE - R/O
MCS<O> - Lock - LOCK - R/O

The V-bus register
In addition to the V-bus functions, V-bus
state of the CP clock as follows:
V-bus<7> V-bus<6> V-bus<S> V-bus<4> These bits are
stopped.

<7:4>

permit

only

when

reading

the

CPTO
CPTl
CPT2
CPT3

read-only

and

meaningful

the

clock

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-20

LSI-11 interrupts

8.4

Vector

Priority

What

300(8)
304(8)

higher
lower

TX ROY
RX DNE

USE OF THE Q-BUS REGISTERS

Program I/O
Program I/O mode is when the FM ID and TO ID registers are used as the
TXDB and RXDB respectively when VAX 11/780 software wishes to
communicate with the LSI-11 or the ope~ator terminal, via MTPR's and
MFPR's.
Figure
8-5 shows the interaction between VAX 11/780
·-macrocode, microcode, and LSI-11 software.
(ISR:=interrupt service
routine) •
Console microcode routines
When the CPU is in the console wait loop, the console may request
microcode routines to perform various functions, such as an examine
virtual address. The TO ID and FM ID registers are used to pass
parameters needed or supplied by these routines, and the transfers are
interlocked in a manner similar to Figure 8-5, except that instead of
the setting of TX RDY or RX DNE interrupting the VAX 11/780 CPU, it is
VAX 11/780 microcode's responsibility to test the appropriate bit for
being a "one" before reading or loading the TO ID or FM ID register
over the ID bus.
The LSI-11 forces entry to those microroutines by writing to the
microstack via the ID bus {see next section), which pushes the address
on the microstack, then asserting MAINT RTN in the MCR.
All console
microroutines except CONTINUE must exit back to the console wait loop.

VAX 11/780 MACROCODE

LSI-11 SOFTWARE

MICROCODE

*****************

** TX RDY ISR

'.....

CX>
0

*
*
*****************

(')

TX RDY = l?

\NO
************
\-------->*ERROR
*
\
************

YES
*****************
MTPR,
*
*
DATA,
*-*
TXDB
*
*
*****************

t"1

tlJ

* TX RDY <-- 0 *

REI

-->*
FM ID<----DREG
*- - - - - - -->* TX ROY ISR
*
*
* INTR LSI-11
*
*
***********************
*****************
(VIA ID BUS)
I

*
*
*******************
- - - - -

- en
t<
en

*****************

***********************

toi
tlJ

\NO
************
\-------->*ERROR
*
\
************

TX RDY = O?

I YES
*****************
INTR VAX 11/780 CPU
* READ FM ID
*
- -<- - - - - - - - - - - - - - -<- - - - - - - - -* TX RDY<--1
*

*****************

************
*RT!
*
************

*****************

** TX ROY !SR **
*
*
*****************

FOR TRANSMIT DATA
FIGURE 8-SA

VAX 11/780 MACROCODE

LSI-11 SOFTWARE

MICROCODE

-------~-------

....

*****************

**
*

RX DNE ISR

....J

(X)

*****************

I
I

RX DNE
I

= l?

\NO
************
\-------->*ERROR
*

YES

*****************
MFPR,
*
*
RXDB,
*-*
STORE
*
*
*****************

cn
0
r.-e

************

tlJ

***********************

-->*

QREG<----TO ID

*
*- - - - - - -->*
* INTR LSI-11
*

* RX DN E <-- 0

***********************

RX ONE ISR

*ERROR

NO
I
*<------/

************

RX ONE

I
IN

- - - - - - - - - - - - - - - - - - - - - - -

cn
t<
en

*
*

tlJ

-3

************

- - - - -

*****************

(VIA ID BUS)

INTR VAX 11/780 CPU

*****************

\YES
I
\--->!
\ I

= O?

*****************

ANOTHER CHAR?

\
IYES
I

* LOAD TO ID RX *
I
-* DNE<---1
*<---------

I
I

*****************

I
I

!<------------------------------

************
*RTl

************

*****************

** RX ONE ISR **
*******************

FOR RECEIVE DATA
FIGURE 8-58

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-23

There is of course the possibility that the FM ID and/or the TO ID
register was in use for terminal I/O at the time of the entry to the
console wait loop, either as a result of a halt instruction or an
LSI-11 halt request such as for single instruction step.
In order not
to loose terminal data, the LSI-11 must do the following:
(Figure 8-6
will help follow this).
1.

If, at the time of the halt, the TX RDY bit=O, the LSI-11
must first read the FM ID register (and presumably ~ither act
on the data or at least save it) and set the TX RDY bit.
Note that this will set the TX RDY interrupt pending bit (if
TXIE=l). If TX RDY=l, indicating no new data, go directly to
2.

If, at the time of the halt, the RX DNE bit=l, indicating the
TO ID register has not yet been read by microcode, the LSI-11
must save the content of TO ID and the state of the RX DNE
bit.
If RX DNE=O, indicating the buffer has been read,
proceed to 3.

Set VAX 11/780 INTR DISABLE. This now "freezes" the state of
the VAX 11/780 interrupt control logic, and the TO ID and FM
ID, and synchronizing bits, may then be used freely for other
functions.

When ready to continue, the LSI-11 must do the following:
1.

Set TX RDY.

If RX DNE=O upon entry (halt) I then clear the VAX 11/780 INTR
DISABLE and go to 3.
If RX DNE=l upon entry, then restore
data to TO ID and set RX DNE, then go to 3, else restore old
data to TO ID, set RX DNE, and issue the continue.

Re-enable VAX 11/780 interrupts;
issue CONTINUE.

enable

LSI-11

interrupts;

*****************
HALT
*
* CPU
(CNS
LACK)
*
*

***
*A*
***

*****************
I

TX ROY = O?

*****************
\YES
* READ FM ID
*
\----->* TX RDY<--1
*

----------------------*****************
I NO
I
I<-----------------------I

\YES
\---------------

RX ONE = O?

/
\
-----------------------

I
I

NO
*****************
* TMPl<---TO ID *
* TMP2<--RX ONE *

I
I
I

*
*

I
I

*
*

*****************
I
I<-----------------------*****************
*VAX 11/780 INTR*
* DISABLE<--! *

*****************
I<-----------------------*****************
I
* USE REGISTERS *
I
*FOR CNSL FCTNS *
I

I
/

*******************

-----------------

A CONTINUE?

I
I

\NO
I
\--------------\

I YES
*****************

** TX RDY<--1
*

*
*
*****************
I

***
*A*
***
FIGURE 8-6

.....

*****************
\NO
*TO ID<---TMP 1 *
\---------->* RX DNE<---1 *

RX DNE=O
UPON ENTRY?

YES
*****************
I

*
*

RX DNE<--0

....J

*
*

*****************
I
I
I
I
I

*****************
I
I<----------------------------*****************
*
VAX 11/780 INTR*
* DISAB<---0 *
* ENAB LSI-11 *
*
INTR
*
*****************
I

*****************
*ISSUE CONTINUE *
*
FUNCTION
*

*******************

CX>
0

n·

en
0

t""

ts.I

en
t<
en

ts.I

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-25

This sequence is necessary for two reasons: to prevent causing
spurious interrupts to the VAX 11/780 CPU, and to ensure the
interrupts do occur during single instruction stepping.
Direct ID bus references

Clock running
Writing to ID registers is accomplished by first loading the
data to be written into the TO ID LO and TO ID HI registers,
then writing the register address, with the WRITE bit=l and
ID CYCLE=!, into ID C/S. ID CYCLE may be set by a separate
instruction, but in either case the data from the TO ID
register will be written into the addressed register.
Reading is accomplished similarly, except that the ID WRITE
bit=O (i.e, read), and the data from the specified register
is available in the FM ID LO and FM ID HI following the
cycle.

Clock stopped
Reading ID registers with the clock stopped {presumably in
CPTO) is done by setting ID MAINT in the ID C/S register, and
placing the desired address in the address field, with
WRITE=O. Since all ID register strobes are disabled in CPTO,
it is necessary to step the clock to whichever state, other
than CPTO, the desired register is gated onto the ID bus. As
long as ID MAINT is set, the clock is in the correct time
state, and WRITE=O, the addressed register may be read
through the ID DATA LO and ID DATA HI registers, and the
address may be changed while ID MAINT is set. ID MAINT
should be cleared prior to starting the clock again.
It is impossible to write to ID registers when the clock is
stopped without stepping through time states. However, ID
writes may be accomplished by first ensuring the clock is in
CPTO, then loading the desired ID address into ID C/S, along
with ID MAINT=l, and the data in TO ID LO and TO ID HI.
Invoking a single cycle via PROCEED will then write the TO ID
data to the selected register, and clear ID MAINT. Reads may
be done in a similar manner.

VAX 11/780 CONSOI r: ~.;esYSTEM
8.5

Page 8-26

TERMINAL CONTROL REGISTERS IN THE PROCREG SPACE

The following is a proposal for the terminal communication registers
which must appear in the processor register space. The interface
basically consists of a transmitter and a receiver data buffer
register 16 bits in width, and appropriate control and status
information for each.
Note that bits <11:8> of the data buffers are used as a. •unit code",
with unit code 00 (8) assigned to the operator terminal.- Thfs is so
that the interface may be •subsetted• to a simple terminal interface
on those implementations which have only that basic functionality.
There may be a bit which indicates that the interface can do more than
simple terminal functions;
if so, that bit belongs in a CPU
configuration register (TBS in Chapter 9), not in the control/status
registers defined below.
Please note that this appendix describes the terminal registers as
seen by macro level software via MTPR's and MFPR's, independent of
specific implementations. Section 3.0, on the other hand, describes a
set of registers on the ID bus as seen by microcode, and which will be
used in the VAX 11/780 implementation to materialize these terminal
registers (among other things).
This proposal, in some form, will be ECO'd into Chapter 9
the TBS's for the terminal registers.

provide

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-27

RXC/S:

I \
/.
\

DONE
31

16 15

RIE

8 7 .

12 11

I
I
I RX DATA
I

RX
SEL<3:0>

RXDB:

8 7

. I
I
I

TXC/S:

I \
I

RDY

\
TIE

8 7

TXDB:

TX
SEL

I
I
I TX DATA
I

Page 8-28

VAX 11/780 CONSOLE SUBSYSTEM
RXC/S - Receiver control/status
RXCS<7>

receiver done - read only
Set when the data in RXDB is valid and ready to be
read. Cleared by reading RXDB or by system initialize.

RXC/S<6>

receiver interrupt enable - read/write
When set, enables an interrupt to the CPU whenever
receiver done becomes set. Cleared by program control
or by a CPU reset.

RXDB - Receiver data buffer - read only
RXDB<7:0>

RXDB<ll:8>

receive data
Contains one byte of data from the
RXDB<ll:S>.

unit

speciiied

receive unit select
RXDB<ll:8> specify from which logical unit the· data in
RXDB<7:0> originated. Logical unit 00 is reserved for
the operator terminal.

Reading RXDB automatically clears receiver done in the RXC/S longword.
Reading RXDB when receiver done is zero has UNPREDICTABLE results.
TXC/S -.Transmitter control/status register
TXC/S<7>

transmitter ready - read only
When set, indicates that TXDB is ready to accept
another character for transmission. Cleared by a write
to TXDB; set by a CPU reset.

TXC/S<6>

transmitter interrupt enable - read/write
When set, ~nables an interrupt which occurs whenever
transmitter ready becomes set.
Cleared by program
control or by a CPU reset.

TXDB - transmit data buffer - write only
TXDB<7:0>

transmit data
Written by program with the character to be transmitted
to the logical unit specified by TXDB<ll:S>.

TXDB<ll:8>

transmit unit select
Written along with TXDB<7:0> to specify the logical
destination of TXDB<7:0>. Logical unit 00 is reserved
for output to the operator terminal.

Writing to TXDB clears transmitter ready in TXC/S.
Writing·
when transmitter ready is zero has UNPREDICTABLE results.

TXDB

VAX 11/780 CONSOLE SUBSYSTEM

Page 8-29

Note that when this interface is used for the operator terminal, the
logical unit select fields are both all zeros and the interface
appears much like a minimal DL-11.
In the VAX 11/780 implementation,
non-zero unit select fields may be used to initiate I/O with other
devices (namely, the floppy), or general software communications with
the LSI-11.
Should software attempt communications to/from units
other than unit zero on those implementations which have only the
terminal, bits <15:8> are ignored and the characters stjll go to the
terminal, which possibly prints garbage. This is probably acceptable,
since it is the result of a clear-cut software error.

CHAPTER 9
VAX 11/780 ACCELERATOR INTERFACE

The VAX 11/780 Accelerator interface provides mechanisms for:
1.

Main Machine/Accelerator synchronization.

Explicit control of the Accelerator machine state by the main
machine.

Transferring of main machine control to Internal
the Accelerator at any arbitrary Decision Point.

Instruction stream interpretation by the Accelerator.

Transfer of 32 bit data words from the ISB
to
the
Accelerator, from the Accelerator to the main machine Data
Path or from the main machine Data Path to the Accelerator.
Also,
prov1s1on
is made for incorporating within the
accelerator single or multiple copies of the processor
general register set.

Transfer of Accelerator status flags into
micro control machine branch logic.

main

machine

Transfer of condition code information into the main
condition code logic.

machine

the

wcs. space by

Each of these mechanisms is defined in such a way that the use may
defined to suit a general Accelerator.

Each of these functions will be described in more detail in succeeding
sections of this specification.

VAX 11/780 ACCELERATOR INTERFACE

Page 9-2

In summary, the Accelerator interface allows the Accelerator to
examine the instruction stream and •pick out• instruction operation
codes which it determines belong to it and then transfer control of
the main machine to an "Accelerator handler" in main machine WCS while
it processes the instruction.

9.1

DEFINITIONS

INSTRUCTION STREAM BUFFER (ISB)
The Instruction pre processing
hardware which pre fetches and decodes operation codes and operand ·
specifiers from the process Instruction Space.
CENTRAL PROCESSING UNIT (CPU) - The processing hardware consisting of
control store, control machine, registers and data processing hardware
which comprises the basic VAX 11/780 computer.
ACCELERATOR - An optional, autonomous, data processing machine which
operates in conjunction with the CPU to increase processing speed for
specific instructions within the VAX-11 architecture.
This
is
accomplished
by
transparently (at the macro level) overriding
emulation of those instructions by the CPU and instead causing the
required processing to be accomplished in the Accelerator, whose
processing ~lements are optimized to perform the required operations.
I

9.2

INTERFACE SPECIFICATION

Figure 9-1 depicts a block qiagram of a VAX 11/780 ACCELERATOR
interfaced to the VAX 11/780 Computer System. This diagram will be
referred to throughout the remainder of this specification.

9.3

GLOSSARY OF INTERFACE SIGNALS

OP CODE:
copy of
ISB.

EXECUTION POINT COUNTER - Three bits from the ISB which
denote where in the process of instruction execution of the
CPU is. The case of execution point counter = O and an
enable signal from the ISB is used to determine that the CPU
is presently in the IR DECODE state.

Eight bits of information from the ISB which are a
the data contained in byte O (OP CODE byte) of the

The Accelerator also uses the Execution Point
determine when to force CPU control to WCS.

Counter

VAX 11/780 ACCELERATOR INTERFACE
3.

Page 9-3

SRCl SPECIFIER TYPE: Three signals from the ISB which
determine the location of data referenced by the Operand
Specifier in byte 1 of the ISB. The encoded locations are:
CODE
011 Data
111 Data
110 Data
101 Data

is
is
is
is

in General Register
in Memory
Short Literal
Immediate

All other codes cannot occur.
4.

SRC2 SPECIFIER = REGISTER:
One bit which when asserted
indicates that the byte of Data in byte 2 of the ISB would
evaluate to Register if it is an operand specifier. The only
time this is meaningful is if SRCl specifier is one byte in
length.

VALID:
Four signals from the ISB which indicate to the
accelerator whether or not the information on the OP CODE,
SRCl SPECIFIER TYPE and SRC2 SPEC = REGISTER lines is valid.
The signals are as follows:
BYTE 0 VALID (OPCODE VALID)
BYTE l VALID (SPECIFIER 1 VALID)
BYTE 2 VALID (SPECIFIER 2 VALID)
STALL + SVC {ALL INFORMATION VALID)

REGISTER NUMBERS: Two four bit quantities which designate
the registers denoted by SRCl and SRC2 operand specifiers if
they are indeed Register Operand Specifiers.
These may be
used by the accelerator to pre-fetch register contents at the
beginning of each IRD to expedite operations involving
register data.
Note that these register numbers will
operand specifiers other than SRCl = SRC2

undefined

= Register.

for

DECISION POINT OVERRIDE: A signal from the ACCELERATOR to
the
CPU
control
machine
which, when asserted, will
unconditionally assert Address Bit 12 on input of the micro
sequencer address mux.
The effect of this is to cause
transfer of control to the internal WCS module at the current
execution.

VAX 11/780 ACCELERATOR INTERFACE

Page 9-4

ID BUS: The 32 bit bidirectional bus which is the
mechanism whereby data is entered into the Accelerator.

ACCELERATOR CONTROL FIELD: This is a two bit field used to
command the operation of the Accelerator. Three of these
codes are fixed use and the fourth is accelerator dependent.
The codes are:
ACF

00 01
10 11 -

main

NO OPERATION
CPU SYNC
ACCELERATOR TRAP
ACCELERATOR SPECIFIC CODE

The CPU trap and CPU sync codes will be used by the power up
or abort micro routines. Therefore, all accelerators must
use these codes.
CPU SYNC: One signal, derived from the ACF field, which
used to synchronize CPU and Accelerator functions.
functions as a binary semaphore or flag which is tested
the Accelerator when synchronism is required.

is
It
by

ACCELERATOR TRAP: A signal from the ACF Field which when
asserted
will cause a transfer of control within the
Accelerator to the micro address specified by the TRAP
ADDRESS word in the next micro cycle.

10.

TRAP ADDRESS:
3 bits from the CPU control word which specify
explictly the micro address in the ACCELERATOR Control space
to which ACCELERATOR Control is to be transferred.
These 3
bits are formed by redefining the (USI) field in the CPU
control word.

11.

ACCELERATOR STATUS FLAGS: Three bits which are passed from
the ACCELERATOR to the CPU control machine branch logic.
These bits can be tested by the CPU by selecting BEN 6.
The
meaning
of
these bits varies with the state of the
CPU/Accelerator machine combination.
Once convention is established, however, in cases where
synchronization is required. ACC<OO> is defined AD HOC to be
the signal Accelerator Sync. This signal is tested by the
CPU at synchronizing points and together with CPU sync forms
a bidirectional synchronization
interlock.
NOTE: That
ACC<02:01>
remain
free
of
definition
even
during
synchronization. Therefore, information may be passed to the
CPU and interpreted in context at each synchronization point
by the ACCELERATOR if so desired.

VAX 11/780 ACCELERATOR INTERFACE

Page 9-5

12.

ACCELERATOR CONDITION CODES: The Accelerator has access to
the PSL condition codes from the CPU.
For each instruction
implemented by the·Accelerator, the PSL condition codes may
want to be changed. Therefore, the Accelerator takes the PSL
condition codes at the start of the instruction and returns
four new condition code bits based on the result of the
operation
and
the
previous
condition
code
states.
NOTE: That
these return lines are different than the
condition codes coming to the accelerator.
The returned
condition codes are latched by the CPU.
This information is
then transfered to the PSL condition codes in the next CPU
micro state by setting the UMSC field to a 6.

13.

GENERAL REGISTER ADDRESS: Four signals from the CPU control
machine which are latched copies of the SPA address (latched
in the CPU at TISO).
During the second half of each micro
cycle
(TlOO-->TO)
the
address lines of the internal
ACCELERATOR General Register sets are forced
to agree with
this address.
It is during this time that any updates to the
CPU general register are copied into the ACCELERATOR General
Registers Copies.

14.

GENERAL REGISTER WRITE ENABLE: Two bits which encode how
much, if any, of the general register addressed by the
General Register ADDRESS lines is being written in the CPU.
The codes are as follows:
WREN

01
l

1
0

00
1 No Write
0 Write Byte (Byte 0)
0 Write Word (Bytes O, 1)
1 Write Long Word (Bytes 0, 1, 2, 3)

These bits are latched in the
cycle.

CPU

TISO

each

micro

15.

GENERAL REGISTER UPDATE BUS: 32 data lines from the CPU to
the Accelerator.
These lines are a buffered copy of the data
inputs to the CPU general register sets. This is the data
written into the ACCELERATOR General Register Copies when an
update is indicated by WREN<OO:Ol>. This bus is also used to
return data back to the CPU.
It is the task of the
Accelerator to decide. which data to return. Control of the
direction of transfer on this bus is done by a control code
in either UQK or the UDK fields in the CPU.

16.

!SB CALL: A signal from the !SB to the ACCELERATOR which
when asserted
indicates that I Stream Data (either short
literal or Immediate Data) is being driven onto the ID Bus by
the !SB during the current cycle.

VAX 11/780 ACCELERATOR INTERFACE
9.4

Page 9-6

ACCELERATOR INTERFACE OPERATION

CPU<-->ACCELERATOR INTERFACE
The main function of the CPU/ACCELERATOR Interface is to provide
synchronization between the two cooperating processes and to pass
status information for the purpose of altering control flow in either
or both machines.
Synchronization is obtained by the use
of
semaphores.
When
synchronization
is
required, the following sequence· of ·events
transpires (refer to figure 9-1). For the purpose of illustration
synchronization of a data transfer from the CPU to the ACCELERATOR is
discussed. NOTE: That this transfer of condition codes must be done
at a syncronization point defined by accelerator and CPU micro code.

9.4.1

Data transfer

The example of Figure 9-2 shows a transaction in which a data word is
being
fetched from memory by the CPU.
In this example, the
ACCELERATOR is waiting for the Data and indicates such by asserting
ACCEL SYNC. In each micro cycle while it is waiting for CPU SYNC the
ACCELERATOR reads data from the ID bus and treats it as if it were the
data it was expecting. In some cases, the ACCELERATOR may even begin
processing this data if it can safely do this without destroying any
internal information required at ~ later time.
Meanwhile, the CPU generates the Virtual Address of the required
and completes the memory reference.

data

Note that any faults encountered in this memory reference have no
effect on the ACCELERATOR state - hence servicing of TB faults, cache
parity errors, unaligned data traps, etc., can occur transparently.
Once the memory reference has been successfully completed and the data
safely stored in the CPU D register, the CPU drives it onto the ID bus
and asserts CPU SYNC. In this state, it tests for ACCEL SYNC and
finding it asserted, continues.
The ACCELERATOR, meanwhile, has finally received CPU SYNC indicating
that the data which it has received was indeed the data it required
and it continues processing.

9.4.1.1 Initial data transfer - The bi-directional interlock shown in
Figure 9-2 is not always necessary. In some cases, (noteably during
initial argument loading or whenever the ACCELERATOR is guaranteed to
be idle (i.e., waiting for data input) the test for ACCEL SYNC by the
CPU may be safely bypassed as in Figure 9-3.

VAX 11/780 ACCELERATOR INTERFACE

Page 9-7

Note also in Figure 9-3 that the ACCELERATOR is designed in such a way
that it is, after receipt of the first argument, continuously using ID
bus data for processing as if it were valid data and storing the
result in a scratch register while waiting for CPU SYNC. When the CPU
SYNC is received, indicating that the data is on the ID BUS in the
·current cycle, the ACCELERATOR has already successfully completed one
micro cycle of its required execution.

9.4.2

Accelerator control

In addition to synchronization of the ACCELERATOR and the CPU, the
interface provides two mechanisms whereby the CPU may explicitly alter
control flow in the ACCELERATOR.

9.4.2.1 Accelerator trap - The first
function.
When the CPU wishes to
program to a specific uaddress it
ADDRESS<03:00> and asserts ACCEL TRAP.

is
the
ACCELERATOR
TRAP
force the ACCELERATOR control
asserts this uaddr on TRAP
(See Figure 9-4).

In the following
ustate, ACCEL control will be unconditionally
transferred to this micro address. Figure 9-4 illustrates how the CPU
would use the ACCEL TRAP function to cause a transfer of control
within the ACCELERATOR control machine to uAddress 6. This mechanism
would be used primarily for
initialization of the ACCELERATOR and
perhaps in some catastrophic fault conditions.

9.4.2.2 Alternate trap function - Each implementation of Accelerator
will likely require a means of subroutine calls.
This can be
implemented in a few different ways.
One approach would be the
complex scheme of a micro stack with call and return capabilities.
Another means could be a trap to a specific address. This may be done
by a field of bits located in the Accelerator maintenance register.
This would allow routines to be entered where there is enough overhead
available to allow a constant to be written into the status register.
These traps could also be defined to imply syncronization points.
The most useful need for this appears to be for micro diagnostics.

9.4.2.3 CPU branches - As has previously been discussed, the primary
mechanism for passing control/status information from the ACCELERATOR
to the CPU is the three bit ACCEL STATUS FLAG Field.
One of these three bits (i.e., bit 0) is predefined to be ACCEL SYNC.
The remaining two however may be used to convey different information
at different times. Within the CPU these three bits form one branch

VAX 11/780 ACCELERATOR INTERFACE

Page 9-8

enable input into the control machine. Thus, at any synchronization
point, an eight way branch within the CPU can be used to test internal
Accelerator conditions (ACC<OO> is predefined as ACCEL SYNC.
The ACCELERATOR control machine may, at different sync points within a
given execution, switch these status flag inputs to various internal
hardware outputs such as "overflow detected", •undefined variable",
etc., or drive the bits directly. The only requirement is, of course,
that the CPU recognize what significance these bits have in current
context.

9.4.3

System clock

One important item which has not been mentioned yet but rather assumed
is the SYSTEM CLOCK input to the ACCELERATOR. Both the CPU and
ACCELERATOR use this system clock for timing.
Furthermore, both
control
machines utilize synchronous 200 nsec u states (i.e.,
ACCELERATOR TO = CPU TO etc.) as far as the control interface is
concerned.
Clock inputs are differential ECL and consist of decoded TO, TSO,
TlOO, TISO as well as Tph and the two phase clocks.
(See VAX 11/780
Clock Spec.) Thus, with some care 25 nsec intervals within the 200
usec ROM state can be established within the data prcoessing section
of the ACCELERATOR.

9.5

DATA INTERFACE

Connecting the ACCELERATOR and the CPU are two 32 bit data busses, the
System ID Bus and the ACCELERATOR GEN REG Bus.

9.5.1

Data to accelerator

Data is transfered to the Accelerator by means of the system ID BUS.
This transfer is done by the CPU asserting data onto the ID BUS and
issuing CP SYNC. This implies that the transfer is done at a sync
point.
Note that no ID bus address is required for this transfer.
The Accelerator simply accepts the current ID bus data.

9.5.1.1 Data from accelerator - Results returned from the accelerator
is done via the Accelerator General Register Bus. This tr·ansfer is
done by the CPU selecting the Accelerator data onto the 3-state
general register bus.
This implies that this transfer is done at a
syncronization point where the data is meaningful.

VAX 11/780 ACCELERATOR INTERFACE
9.5.2

Page 9-9

Alternate data transfers

The data returned from the Accelerator could also be accomplished over
the system ID bus. There are two drawbacks to this scheme. First is
the timing consideration of when the result data is stable it must be
stable sooner for an ID bus transfer. The second drawback is that the
ID bus data can only go into the CPU Q Register. This implies that if
the data is to be written to memory, an additional state of overhead
is added.

9.5.3

Accelerator status registers

In addition to serving as a path for input and output data, the System
ID bus provides READ/WRITE Access to the ACCELERATOR STATUS and
MAINTENANCE registers. The ACCELERATOR STATUS register is accessible
to macro level software via MTPR and MFPR instructions.
Both
registers are accessible to the console processor.
By examining this register (bits 0 - 3) the console (or macro level
software) can determine what type (if any) ACCELERATOR is installed.
By writing bit 15 of the ACCEL STATUS register the console or macro
level software may at any time turn the ACCELERATOR on or off.
Turning the unit off will disable all control output signals which
effectively removes the ACCELERATOR from the system. This allows the
system to continue operation in degraded mode for most ACCELERATOR
failures.
Bits 30 thru 27 contain error
accelerator type.

information

based

the

particular

Bit 31 is an error summary flag which is set when
bits (30:27) are set.

any

the

error

9.5.3.l Accelerator maintenance register - This
register
contains
information
useful
to micro diagnostic programs.
(Accelerator
Dependent)

9.5.4

General register updates

A second method of passing data to the ACCELERATOR would be through
the processor General Register set. Provision for maintaining "n"
copies of the processor General Register set within the ACCELERATOR is
provided.
The ACCELERATOR may Read data from these internal copies
from TO to TlOO of any micro state. It then relinquishes control of
these copies to the CPU via the General Register Address, Data and
Write enable lines of the CPU/ACCELERATOR interface.

VAX 11/780 ACCELERATOR INTERFACE

Page 9-10

During this portion of the cycle the CPU will cause the ACCELERATOR
General Register copies to be written (updated) in an identical manner
to the CPU general register sets.
Note that the ACCELERATOR General Register copies are WRITE ONLY
Memory to the CPU and READ ONLY Memory to the ACCELERATOR. Operations
with destinations within the general register set processed by the
ACCELERATOR still require passing of the result through the CPU D
register. The purpose of this section of the DATA INTERFACE is to
provide rapid access to data contained in the General Register. sets by
the ACCELERATOR.

9.6

ISB INTERFACE

A key to the operation of the ACCELERATOR is enough visibility of
I stream and CPU machine state to be able to determine:
1.

When to begin processing an instruction (i.e., when
is in IRD).

When to force the CPU control flow into the
handler package.

WCS

the

CPU

Accelerator

This is accomplished by, in the ACCELERATOR quiescent state (WAIT)
examining the output of an "ON BOARD" instruction decode network. All
u address targets for the ACCEL control machine are the WAIT state
except
for the instructions for which the unit was designed.
Furthermore, this target uaddress is forced to the WAIT STATE address
except when the CPU is in IRD, no interrupts or exceptional conditions
are pending, and the ISB data being supplied is valid.
When the ACCELERATOR has determined that it should begin execution, it
leaves WAIT and the on board decode has no further function until the
next IRD state.
At some point in the CPU control program, the ACCELERATOR will
determine that the general flows provided in the CPU micro code do not
efficiently serve its requirements and it will assert EXECUTION POINT
OVERRIDE.
This will force a one to micro address bit 12. The net
effect of this action is to force transfer of control in the CPU
control machine to the WCS module at the next Decision Point.
Note that the 8 bits being asserted by the Instruction Buffer are
unmodified by this action.
Therefore, each target uaddress which
might occur in the normal flow must be duplicated in the WCS handler.
Worst Case this would be 256 locations, but this number should be
considerably smaller.

VAX 11/780 ACCELERATOR INTERFACE

Page 9-11

8 BITS OPCODE

INSTRUCTION
BUFFER

------------------------------------->
3 BITS EXECUTION POINT
ACCELERATOR
------------------------------------->
3 BITS SPECIFIER TYPE
------------------------------------->
4 BITS VALID CODES
------------------------------------->
8 BITS REGISTER NUMBERS
------------------------------------->
1 BIT SPECIFIER-2=REGISTER
------------------------------------->
1 BIT WCS OVERRIDE

---------------

l<--------1

I - 8 BITS OF MICRO ADDRESS

v
CPU

ID BUS

------------------------------------->
2 BITS ACF
------------------------------------->
3 BITS USI
------------------------------------->
6 BIT GENERAL REGISTER CONTROL
------------------------------------->
32 BITS GENERAL REGISTER DATA
------------------------------------->
SYSTEM CLOCK
------------------------------------->
1 BIT COMPATIBILITY MODE
------------------------------------->

FIGURE 9-1
BLOCK DIAGRAM OF VAX 11/780 ACCELERATOR SUBSYSTEM INTERFACE

VAX 11/780 ACCELERATOR INTERFACE

Page 9-12

CREATE VA

SIGNIFY READY

VA<-ALU

I
I
I WAIT FOR CP SYNC I
I
ACCR TO BUS
I

ACC SYNC

l<-------------------1

I STILL WAITING

READ MEMORY

I
I
I

D<-CACHE

ACC SYNC

l<-------------------1

ACC<-ID BUS
WAIT FOR
CP SYNC

----------->I

ACKNOWLEDGE
-------------------I
---->I ACC<-ID BUS
I
I
I
I

-------------------SEND DATA

1--------1I

-------------------ID<-D
CP SYNC<-1

ACC SYNC

l<--------------1

--------------------

l--------------------<-------------------1
I

ACC SYNC
-------------------DONE XFER
--------------------

--------------------

I
-ACC SYNC
--------------------

I
I
I
I
I

-------------------ID<-D
CP SYNC
I
-------------------I
I
I
I ________________ _
I

FIGURE 9-2

VAX 11/780 ACCELERATOR INTERFACE

Page 9-13

CPU

ACCEL

I WAIT FOR !ST DATA
I
WORD .

CREATE VA FOR
FIRST MEM REF

I STORE ID BUS DATA I
I BRANCH ON CPU SYNC I
CPU SYNC

I
DO FIRST MEM
I
I REF-GET ADDITIONAL I
I
OP SPECINFO
I

WAIT FOR 10 DATA
WORD

I STORE ID BUS DATA I
I BRANCH ON CPU SYNC I

DREG<-CACHE
QREG<-ID BUS

CPU SYNC

I FORM NEXT VA
I
I& PASS DATA TO ACCELI
ID BUS<-DREG
CPU SYNC<-1

WAIT FOR lST
DATA WORD

CPU SYNC

----------------------·
I STORE ID BUS DATA I

1-------------->I BRANCH ON CPU SYNC I
CPU SYNC

DO SECOND MEM
REF

WAIT FOR 2ND
DATA WORD
OPERATE USING
ID BUS DATA
TEMP<--RESULT
BRANCH ON CPU SYNC

DREG<-CACHE

CPU SYNC
PASS 2ND DATA
WORD TO ACCEL
ID BUS<-DREG
CPU SYNC<-1

WAIT FOR 2ND
DATA WORD
I

CPU SYNC

OPERATE USING
ID BUS DATA
I
TEMP<-RESULT
I BRANCH ON CPU SYNC

1-------------->I
1.

CPU SYNC

I
I

I
CONTINUE

CONTINUE
Figure 9-3

VAX 11/780 ACCELERATOR INTERFACE

Page 9-14

CPU

ACCELERATOR
I
I
I

I EXCEPTIONAL CONDITION I
I
I HAS OCCURRED - VECTOR I
I
I ACCELERATOR TO ABORT I ACCEL I
TRAP I
I
TRAP ADDR - •006•
I->I
I
ACCEL TRAP <-- 1
I
I

ANY· RANDOM
MICROSTATE

1-----------------------1
I
I
I
I
I
I
CONTINUE

(006)

I
I FIRST MICRO STATE
I OF •ABORT• ROUTINE
I

FIGURE 9-4
USE OF TRAP FUNCTION BY CPU TO UNCONDITIONALLY MODIFY
ACCELERATOR CONTROL FLOW

I
I
I
I
I
I

131130 29 38 27126125124 23 22 21 20 19 18 17116115 14 13 12 11 10 9 8 716 5 413 2 1 OI

I
I
I
I
I
I
l---v---1
I
I
I
I
!----------ACCELERATOR TYPE
I
I
1------------------------------------------ACCELERATOR ENABLE/DISABLE

I
I

ID ADDRESS 17(16)

1-----v-----I
I

I
I
I

I
1-----------------------------------------------------------------------------------ACCELERATOR ERROR FLAGS
--------------~----------------------------------------------------------------------------ERROR

FIGURE 9-5
ACCELERATOR STATUS REGISTER

SUMMARY FLAG

APPENDIX A
CONTROL WORD

THE SIX (6) lK * 4 ROMS USED FOR VAX MODE ON THE IRC MODULE ( M8224 )
MAKE UP A 12 BIT CONTROL WORD WHICH IS USED TO DETERMINE THE MAJOR
EXECUTION POINTS OF THE INSTRUCTIONS.THE 12 BIT FIELD IS SPLIT INTO
THREE (3),FOUR (4) BIT FIELDS WHICH ARE:
BITS
3:0
7:4
11:8

A.l

FIELD

DESCRIPTION

ADR
CTL
CTX

ADDRESS
CONTROL
CONTEXT

THE CONTROL WORD

THE CONTROL WORD IS SHOWN BELOW.
VAX

DECODE
ADDRESS

CONTROL

CONTEXT

-------------~---------------------------------~-------------

I
I
I LENGTH
I
I

I
TYPE
I

I
I
ACCESS I
I
I

I
I
I
I
I 16 WAY ADDRESS
I
I
I
I

I
MODE
I

----~--------------------------------------------------------

CTX3 CTX2 CTXl CTXO

ADDRESS: THE ADDRESS FIELD IS USED TO PROVIDE A 16 WAY LITERAL
DISPLACEMENT WHEN GENERATING AN EXECUTION ADDRESS.THE
ADDRESS IS ONES COMPLEMENTED BEFORE GOING TO THE MICRO
SEQUENCER.
EXAMPLE:IF BITS 03:00 = S, THEN THE ADDRESS FIELD ON
THE INPUT TO THE MICRO SEQUENCER WOULD BE AN
•A•.IN THIS CASE ALL EIGHT (8) VAX DECODE BITS
ARE ONES COMPLEMENTED.

Page A-2

CONTROL WORD.

CONTROL: THE CONTROL FIELD IS SPLIT INTO TWO (2) ,TWO (2) BIT
FIELDS WHICH ARE THE "MODE" FIELD ( BITS 05:04 ) AND
THE "ACCESS" FIELD (BITS 07: 06) •.THESE FIELDS ARE DECODED AS FOLLOWS:
MODE:

OPERATION

----------~~~----------------------

SELECT SPECIFIER
EXECUTE IF R MODE ( ONE OPERAND )
OPTIMIZED ( TWO OPERANDS )
SELECT EXECUTE

ACCESS: 07

OPERATION

0
1
0
1

BRANCH
READ
WRITE
MODIFY

0
0
1
1

0
1
1

CONTEXT: THE CONTEXT FIELD IS SPLIT INTO TWO (2),TWO (2) BIT
FIELDS WHICH ARE THE "TYPE" FIELD ( BITS CTXl:CTXO )
AND THE "LENGTH" FIELD (BITS CTX3:CTX2 ).THESE FIELDS
ARE DECODED AS FOLLOWS:
TYPE:

CTXl I

CTXO

OPERATION

0
0

1
1

INTEGER
FLOAT
VSRC
ASRC

CTX2

OPERATION

0
1
1

BYTE
WORD
LONG
QUAD

LENGTH: CTX3

DEFINITIONS:
SELECT SPECIFIER:

THIS CODE IS USED TO SELECT THE SPECIFIER
DECODE LOGIC.THE EXECUTION ADDRESS WILL BE
DETERMINED BY THE ADDRESSING MODE OF THE SPECIFIER. THE ADDRESSES THAT CAN BE GENERATED BY

CONTROL WORD

Page A-3
THIS LOGIC ARE SHOWN IN THE SPECIFIER DECODE
TABLE.

EXECUTE IF R MODE:

THIS CODE IS USED TO CHECK IF THE SPECIFIER IN
BYTE ONE IS REGISTER MODE.IF IT IS REGISTER
MODE,THEN THE ONES COMPLEMENT OF THE VAX DECODE
BITS 07:00 ARE USED AS THE EXECUTION ADDRESS.IF
THIS CONDITION IS NOT MEET THEN THE SPECIFIER
DECODE LOGIC IS SELECTED BY HARDWARE.

OPTIMIZED:

THIS CODE CHECKS FOR SHORT LITERAL TO REGISTER
( SAl,REG} OR REGISTER.TO REGISTER ( REG,REG ).
IF EITHER OF THESE CONDITIONS ARE MEET,THEN THE
HARDWARE WILL MODIFY THE SPECIFIER ADDRESS. IF
THESE CONDITIONS ARE NOT MEET,THEN THE SPECIFIER
ADDRESS IS NOT MODIFIED.

SELECT EXECUTE:

WHEN THIS CODE IS USED,THE VAX DECODE BITS 07:00
ARE ONES COMPLEMENTED AND USED AS AN EXECUTION
ADDRESS.

BRANCH:

THE BRANCH CODE WILL SELECT THE BRANCH DECODE
LOGIC ONLY AT EXECUTION POINT O. AT ANY OTHER
EXECUTION POINT THIS CODE CAN ONLY BE USED AS
A LITERAL FOR AN EXECUTION ADDRESS.

READ:

THIS CODE IS USED WHEN A SPECIFIER EVALUATION
WANTS TO READ DATA.THIS CODE CAN ALSO BE USED
AS A LITERAL FOR AN EXECUTION ADDRESS WHEN THE
SELECT EXECUTE MODE IS USED.

WRITE:

THIS CODE IS USED WHEN A SPECIFIER EVALUATION
WANTS TO WRITE DATA.THIS CODE CAN ALSO BE USED
AS A LITERAL FOR AN EXECUTION ADDRESS WHEN THE
SELECT EXECUTE MODE IS USED.

MODIFY:

THIS CODE IS USED DURING A READ-MODIFY-WRITE.
THIS INFORMS THE TRANSLATION BUFFER THAT THE OPERATION IS A READ WITH A WRITE CHECK.THIS CODE
CAN ALSO BE USED AS A LITERAL FOR AN EXECUTION
ADDRESS WHEN THE SELECT EXECUTE MODE IS USED.

INTEGER:

THIS CODE.IS USED WITH INTEGER DATA TYPES.
REFER TO THE CONTEXT TABLE FOR COMMON USES
OF THIS CODE.

FLOAT:

THIS CODE IS USED WITH FLOATING DATA TYPES.
REFER TO THE CONTEXT TABLE FOR COMMON USES
OF THIS CODE.

VSRC:

THIS CODE IS ONLY USED WITH FIELD INSTRUCTIONS.
IT IS USED WHEN THE CALCULATED EFFECTIVE ADDRESS
IS USED AS THE OPERAND~THIS INCLUDES REGISTER
·ADDRESSES.

CONTROL WORD

Page A-4

ASRC:

THIS CODE IS USED FOR INSTRUCTIONS THAT REQUIRE
THE CALCULATED EFFECTIVE ADDRESS TO BE USED AS
THE OPERAND.THIS EXCLUDES REGISTER ADDRESSES.

SPEC~FIER

MODE
0
l

2
3
4
5

6
7
8
9

A
B

D
E
F

MNEMONIC

DECODE TABLE

s"'t
s"'t

R/=PC
00
00
00
00

E
R'
(R)
-(R)
(R) +
@(R)+
DB
@D8
DI6
@Dl6
D32
@D32

04
08
OA
09
OB
OD
OF
OD
OF
OD
OF

s"'t

S"'f

R=PC
00
00
00
00
IC
I4
I8
IA
I9
lB
OD
OF
OD
OF
OD
OF

QUAD
02
02
02
02
6/16
IF

ABORT
01/03
01/03
01/03
01/03
lD
7/I7,S/15

-----------------------------------------

CONTEXT TABLE
LENGTH

TYPE

USE

BYTE
WORD
LONG
QUAD
BYTE
WORD
LONG
QUAD

INTEGER
INTEGER
INTEGER
INTEGER
FLOAT
FLOAT
FLOAT
FLOAT

BYTE DATA TYPE
WORD DA TA TYPE
LONGWORD DATA TYPE
QUADWORD DATA TYPE
UNDEFINED
UNDEFINED
FLOATING DATA TYPE
DOUBLE-FLOATING DATA TYPE

CONTROL WORD
A.2

Page A-5

ABORT CONDITION

ABORT CONDITIONS: THE FOLLOWING IS A LIST OF ABORT ADDRESSES
AND THE CONDITIONS WHICH CAUSE THEM TO BE
GENERATED.
ADDRESS

CONDITIONS

1. WRITING INTO A SHORT LITERAL.
2. E MODE FOLLOWED BY A SHORT LITERAL.
3. USING A SHORT LITERAL AS AN VSRC OR ASRC.

QUAD CONTEXT AND
1. WRITING INTO A SHORT LITERAL.
2. E MODE FOLLOWED BY A SHORT LITERAL.
3. USING A SHORT LITERAL AS AN VSRC OR ASRC.

1. USING REGISTER MODE FOR AN ASRC.
2. E MODE FOLLOWED BY REGISTER MODE.

CONTEXT TYPE IS QUAD AND
1. USING REGISTER MODE AS AN ASRC.
2. E MODE IS FOLLOWED BY REGISTER MODE.

1. REGISTER MODE AND RN EQUALS PC

RN EQUALS PC AND
1. USING REGISTER MODE AS AN ASRC.
2. E MODE IS FOLLOWED BY REGISTER MODE.

RN EQUALS PC WITH QUAD CONTEXT.

CONTEXT IS QUAD AND "'RN" IS EQUAL TO PC
1. USING REGISTER MODE AS AN ASRC.
2. E MODE IS FOLLOWED BY REGISTER MODE.

THE ADDRESSING MODE IS REGISTER DEFFERED
AND "RN" IS EQUAL TO PC.

THE ADDRESSING MODE IS AUTO DECREMENT
AND THE "RN 8 IS EQUAL TO THE PC.

l. E MODE WITH THE *RN* EQUAL TO PC.

1. E MODE FOLLOWED BY E MODE.

Page A-6

CONTROL WORD
00

HALT

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8
8

NOP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

1
8

REI

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

·a

8
8
8

CONTROL WORD

Page A-7

BPT

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

3
8

a
a
a
a
a
a

RET

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

RSB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

4
8

8
·8

8
8

8
8
8
8
8
8

Page A-8

CONTROL WORD

LDPCTX

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG·
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE·
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

SVPCTX

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8

CVTPS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
WORD
BYTE
LONG
LONG

INT
ASRC
INT
INT
INT
ASRC
INT
INT

READ
READ
BRANCH
BRANCH
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
EXECUTE
SE LS PC
SELSPC
EXECUTE
EXECUTE

0
0
F

7
8

A
0
0

8
3

CONTROL WORD

Page A-9

CVTSP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
WORD
BYTE
LONG
LONG

INT
ASRC
INT
INT
INT
ASRC
INT
INT

READ
READ
BRANCH
BRANCH
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
-EXECUTE
SE LS PC
SE LS PC
EXECUTE
EXECUTE

0
0
F

INDEX

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
WRITE
READ

SE LS PC
SE LS PC
EXECUTE
SE LS PC
SE LS PC
SE LS PC
SE LS PC
EXECUTE

0
0

CRC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
LONG
LONG
LONG
WORD
BYTE
LONG
LONG

ASRC
INT
INT
INT
INT
ASRC
VSRC
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SELSPC
EXECUTE
EXECUTE
SE LS PC
SELSPC
SE LS PC
EXECUTE

0
0

E
0
0

8
4

6
0
0
0
0
8

4
0
00
E

Page A-10

CONTROL WORD

PROBER

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
WORD
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
ASRC
INT
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

PROBEW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
WORD
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
ASRC
INT
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

INS QUE

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG.

ASRC
ASRC
ASRC
INT
INT
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
READ

SELSPC
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

1
0

8
8
8
8

1
0

8
8
8
8

0
0

8
8
8
8
8

CONTROL WORD

Page A-11

REM QUE

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
·EXECUTE
EXECUTE
EXECUTE
EXECUTE

BSBB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

D
8
8
8
8
8
8
8

BRB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8
8

ADDRESS
0
B

0
8
8
8
8
8

Page A-12

CONTROL WORD

BNEQ/BNEQU

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

BEQL/BEQLU

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8
8

BGTR

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ·
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8
8

CONTROL WORD

Page A-13

BLEQ

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8
8

JSB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
8
8
8
8
8
8

JMP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

1
8
8
8
8
8
8

Page A-14

CONTROL WORD

BGEQ

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8
8

BLSS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

BGTRU

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
REi\D
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8

8
8
8
8

8
8
8
8
8
8

CONTROL WORD

Page A-15

BLEQU

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
. EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8
8

BVC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

BVS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
REA_D
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

Page A-16

CONTROL WORD

BGEQU/BCC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUrE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

BLSSU/BCS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDP4

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
WORD
BYTE
LONG
LONG
LONG

INT
ASRC
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
SE LS PC
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8
8
8
8

5
0
0
8
8

CONTROL WORD

Page A-17

ADDP6

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
WORD
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
ASRC
INT
ASRC
INT

READ
READ
B·RANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
SE LS PC
SE LS PC
SE LS PC
EXECUTE

0
0
5
0
0

SUBP4

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
WORD
BYTE
LONG
LONG
LONG

INT
ASRC
INT.
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SELSPC
SE LS PC
EXECUTE
EXECUTE
EXECUTE

0
0
5
0
0
8
8

SUBP6

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
WORD
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
ASRC
INT
ASRC
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
SE LS PC
SE LS PC
SE LS PC
EXECUTE

0
0

5
0
0
0
0

CONTROL WORD

Page A-18

CVTPT

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
ASRC
INT
ASRC
INT

READ
READ
BRANCH
WRITE
READ
READ
READ
WRITE

SE LS PC
SELSPC
EXECUTE
EXECUTE
SE LS PC
SELSPC
SE LS PC
EXECUTE

0
0

MULP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
WORD
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
ASRC
INT
ASRC
INT

READ
READ
. BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
SE LS PC
SE LS PC
SE LS PC
EXECUTE

0
0

CVTTP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
ASRC
INT
ASRC
INT

READ
READ
BRANCH
WRITE
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
EXECUTE
SE LS PC
SE LS PC
SE LS PC
EXECUTE

0
0
F

D
0
0
0

4
0
0
0
0

c
0
0

CONTROL WORD

Page A-19

DIVP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
WORD
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
ASRC
INT
ASRC
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
SE LS PC
SE LS PC
SE LS PC
EXECUTE

0
0
2
0
0
0
0

MOVC3

EXC PT

LENGTH

TYPE

ACCESS

MODE

P.DDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
LONG
LONG
LONG

INT
ASRC
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
WRITE
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE

CMPC3

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
LONG
LONG
LONG

INT
ASRC
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
BRANCH
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE

0
F

5
0

8
8

ADDRESS
0
0
F

D
0

8
8
6

Page A-20

CONTROL WORD

SCANC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
BYTE
LONG
LONG

INT
ASRC
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SELSPC
EXECUTE
EXECUTE
SE LS PC
SELSPC
EXECUTE
EXECUTE

0
0

SPANC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
BYTE
LONG
LONG

INT
ASRC
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
EXECUTE
SE LS PC
SELSPC
EXECUTE
EXECUTE

0
0
F
9
0
0

MOVCS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
INT
INT
ASRC
INT

READ
READ
BRANCH
WRITE
READ
READ
READ
WRITE

SELSPC
SELSPC
EXECUTE
EXECUTE
SE LS PC
SELSPC
SELSPC
EXECUTE

9
0
0
8
5

8
5

0
F
l
0
0
0

CONTROL WORD

Page A-21

CMPCS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
INT
INT
ASRC
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
EXECUTE
· SELSPC
SE LS PC
SE LS PC
EXECUTE

0
0

MOVTC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
BYTE
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
ASRC
INT
ASRC
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
SE LS PC
SE LS PC
SE LS PC
EXECUTE

0
0

MO VT UC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
BYTE
BYTE
WORD
BYTE
LONG

INT
ASRC
INT
INT
ASRC
INT
ASRC
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SELSPC
SE LS PC
SE LS PC
SE LS PC
EXECUTE

0
0

c
0
0
0
6

0
0
0

0
7

c
0
0
0
0

Page A-22

CONTROL WORD

BSBW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

D
8
8
8
8
8
8
8

BRW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

BRANCH
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

CVTWL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8

8
8
8
8

CONTROL WORD

Page A-23

CVTWB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
WORD
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
SE LS PC
·EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
4

0
8
8
8
8

MOVP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
LONG
LONG
LONG

INT
ASRC
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE

0
0
F
B
0
8

CMPP3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
BYTE
LONG
LONG
LONG

INT
ASRC
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE

0
0
F

6
0
8
8
A

Page A-24

CONTROL WORD

CVTPL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
ASRC
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

CMPP4

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
WORD
BYTE
LONG
LONG

INT
ASRC
INT
INT
INT
ASRC
INT
INT

READ
READ
BRANCH
READ
READ
··READ
READ
WRITE

SE LS PC
S·ELSPC
EXECUTE
EXECUTE
SE LS PC
SE LS PC
EXECUTE
EXECUTE

0
0

EDIT PC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
BYTE
BYTE
LONG
LONG
LONG

INT
ASRC
INT
ASRC
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
. SELSPC
EXECUTE
EXECUTE
EXECUTE

0
0
9
0
0
8
8

0
8
8
8

A
0
0
8

CONTROL WORD

Page A-25

MATCHC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
BYTE
LONG
LONG
WORD
BYTE
LONG
LONG

INT
ASRC
INT
INT
INT
ASRC
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
WRITE

SE LS PC
SELSPC
EXECUTE
EXECUTE
. SELSPC
SE LS PC
EXECUTE
EXECUTE

0
0
F

LOCC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
WORD
LONG
LONG
BYTE
LONG
LONG
LONG

INT
INT
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
BRANCH

SE LS PC
SELSPC
EXECUTE
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE

0
0
F

0
0
8

7
0
8
8

SKPC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
WORD
LONG
LONG
BYTE
LONG
LONG
LONG

INT
INT
INT
INT
ASRC
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
BRANCH

SELSPC
SELSPC
EXECUTE
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE

0
0
F

7
0
8
8

Page A-26

CONTROL WORD

MOVZWL

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ACBW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
BRANCH
MODIFY
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
B
0
8
8
8
8

MOVAW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDRESS
0

5
0

8
8
8
8
8

8
8
8
8
8
8

Page A-27

CONTROL WORD

PUSHAW

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8

ADDF2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
1

ADDF3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
1
0
8
8
8
8

ADDRESS
0

E
8
8
8
8

Page A-28

CONTROL WORD

SUBF2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE·
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8

SUBF3

EXC PT

LENGTH

TYPE

-ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

·o

MULF2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
l
0
8
8
8
8

F
0

E
8
8
8
8

CONTROL WORD

Page A-29

MULF3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SELSPC
SELSPC
EXECUTE
SELSPC
.EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
0
0

8
8
8
8

DIVF2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SELSPC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8

DIVF3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

E
2

2
0

8
8
8
8

Page A-30

CONTROL WORD

CVTFB

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

CVTFW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
WORD
WORD
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

·O
A

CVTFL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDRESS
0

A
0
8
8
8
8
8

8
8
8
8
8

A
0

8
8
8
8
8

Page A-31

CONTROL WORD

CVTRFL

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
INT
INT
INT
INT
INT

READ
BRANCH
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
.EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8

CVTBF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
FLOAT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
0
8
8
8
8
8

CVTWF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
FLOAT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
RE.AD
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
0
8
8
8
8
8

ADDRESS
0

Page A~32

CONTROL WORD

CVTLF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
FLOAT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
0
8
8
8
8
8

ACBF

EXC PT

LENGTH

TYPE

_ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
BRANCH
MODIFY
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

·O

MOVF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
. EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

A
0
8
8

8
8

A
0
8
8
8
8
8

CONTROL WORD

Page A-33

CMPF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
INT
INT
INT
INT
INT

READ
READ
BRANCH
READ
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

MNEGF

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

TSTF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

E
8
8
8
8
8

ADDRESS
0

A
0
8
8
8
8
8

2
8
8

8
8
8
8

CONTROL WORD

Page A-34

EMODF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EP5
EP6
EP7

LONG
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
FLOAT
INT
FLOAT
INT
INT

READ
READ
BRANCH
READ
WRITE
WRITE
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
SE LS PC
SE LS PC
EXECUTE
EXECUTE

0
0

8
8

POLYF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EP5
EP6
EP7

LONG
WORD
LONG
BYTE
LONG
LONG
LONG
LONG

FLOAT
INT
INT
ASRC
FLOAT
INT
INT
FLOAT

READ
READ
BRANCH
READ
WRITE
READ
READ
BRANCH

SE LS PC
SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

CVTFD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EP5
EP6
EP7

LONG
QUAD
QUAD
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
0
8
8
8
8
8

7
0
0
0

D
0

7
8
8

CONTROL WORD

Page A-35

RESERVED

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8

ADAW I

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
LONG
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
VSRC
INT
INT
INT
INT
INT

READ
MODIFY
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
1
0
8
8
8
8
8

RESERVED

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8

8
8

8
8
8
8
8
8

CONTROL WORD

Page A-36

RESERVED

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8
8

RESERVED

EXC PT

LENGTH

TYPE

-ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
.READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

·8

RESERVED

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

8
8
8

8
8
8
8

CONTROL WORD

Page A-37

RESERVED

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS.
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8
8

RESERVED

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8
8

RESERVED

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8
8

Page A-38

CONTROL WORD

ADDD2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

ADDD3

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

SUBD2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ.
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
1

EP2

1
5
B

8
8
8
8

ADDRESS
0

0
5
0

8
8
8

5
B

8
8
8
8

Page A-39

CONTROL WORD

SUBD3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SELSPC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
5
0
8
8
8
8

MULD2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

MULD3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

7
3
B

8
8
8
8

3
0

8
8
8
8

Page A-40

CONTROL WORD

DIVD2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

6
4
B
8
8
8
8

DIVD3

EXC PT

LENGTH

TYPE

-ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

·O
0

CVTDB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

4
0

8
8
8
8

c
0

8
8
8
8
8

CONTROL WORD

Page A-41

CVTDW

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

CVTDL

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

CVTRDT

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
INT
INT
INT
INT
INT
INT
INT

READ
BRANCH
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDRESS
0

c
0

8
8
8
8
8

ADDRESS
0

c
0
8
8
8
8
8

A
0

8
8
8
8
8

Page A-42

CONTROL WORD

CVTBD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
QUAD
LONG
LONG
LONG
LONG
LONG

INT
INT
FLOAT
INT
INT
INT
INT
INT

READ
BRANCH
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
3
0

8
8
8
8
8

CVTWD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
QUAD
LONG
LONG
LONG
LONG
LONG

INT
INT
FLOAT
INT
INT
INT
INT
INT

READ
BRANCH
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
3
0
8
8
8
8
8

CVTLD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
QUAD
LONG
LONG
LONG
LONG
LONG

INT
INT
FLOAT
INT
INT
INT
INT
INT

READ
BRANCH
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

3
0
8
8
8
8
8

CONTROL WORD

Page A-43

ACBD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
FLOAT
INT
INT
INT
INT

READ
READ
READ
MODIFY
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
B
0
8
8
8
8

MOVD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
E
0

8
8
8
8
8

CMPD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

D
8
8
8
8
8

Page A-44

CONTROL WORD

MNEGD

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8

TSTD

EXC PT

LENGTH

TYPE

. ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

6
3
8
8
8
8
8
8

EMO DD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRES8

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
BYTE
BYTE
QUAD
LONG
QUAD
LONG
LONG

FLOAT
INT
INT
FLOAT
INT
FLOAT
INT
INT

READ
READ
READ
READ
WRITE
WRITE
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
SE LS PC
SE LS PC
EXECUTE
EXECUTE

0
0
9
0

ADDRESS
0

0
8
8

CONTROL WORD

Page A-45

POLYD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
WORD
LONG
BYTE
QUAD
LONG
LONG
QUAD

FLOAT
INT
INT
ASRC
FLOAT
INT
INT
FLOAT

READ
READ
READ
READ
WRITE
READ
READ
BRANCH

SE LS PC
SE LS PC
EXECUTE
SELSPC
EXECUTE
EXEC-UTE
EXECUTE
EXECUTE

0
0

CVTDF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
LONG
LONG
LONG
LONG
LONG
LONG
LONG

FLOAT
FLOAT
FLOAT
INT
INT
INT
INT
INT

READ
BRANCH
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
8
8
8
8
8

RESERVED

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8
8

A
0

7
8
8

CONTROL WORD -

Page A-46

ASHL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
EXECVTE
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8

ASHQ

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
QUAD
QUAD
QUAD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

EMUL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
QUAD
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
WRITE
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
SE LS PC
EXECUTE
EXECUTE
EXECUTE

0
0

3
0

8
8
8
8

6
0
0

8
8
8

CONTROL WORD

Page A-47

EDIV

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
QUAD
QUAD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
VSRC
VSRC
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SE LS PC
· SELSPC
EXECUTE
EXECUTE
EXECUTE

0
0
0
0
8
8
8

CLRQ

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

WRITE
WRITE
READ
READ
READ
READ
READ
READ

EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8

MOVQ

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
QUAD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8
8
8

Page A-48

CONTROL WORD

MOVAQ/MOVAD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SELSPC
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
8
8
8
8
8
8

PUSHAQ/PUSHAD

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

QUAD
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDB2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

7
8
8
8
8
8
8

4
8
8
8
8
8

CONTROL WORD

Page A-49

ADDB3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
5
0
8
8
8
8

SUBB2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
.READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8

SUBB3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
5
0

8
4

8
8
8
8

Page A-50

CONTROL WORD

MULB2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

MULB3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8

DIVB2

·Exe PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

2
E
E
8
8
8
8

E
0

3
F
E
8
8
8
8

CONTROL WORD

Page A-51

DIVB3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
.EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

BISB2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
4
8
8
8
8
8

BISB3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
5
0
8
8
8
8

F
0
8
8

8
8

·CONTROL WORD

Page A-52

BICB2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8

BICB3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
5
0
8
8
8
8

XORB2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
4

4
8
8
8
8
8

8
8
8
8
8

CONTROL WORD

Page A-53

XORB3

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

MNEGB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ·
READ
READ

OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

s
s
s
s
s

CASES

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDRESS
0

0
5
0

s
s
s
8

c
0
8

8
8
8

Page A-54

CONTROL WORD

MOVB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

OPT
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
8
8
8
8
8
8

CMPB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRI.TE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

·o

MCOMB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
.INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

6
8
8
8
8
8

6
0
8

8
8
8
8

Page A-55

CONTROL WORD

BITS

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

CLRB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

WRITE
WRITE
READ
READ
READ
READ
READ
READ

EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
8
8
8
8
8
8

TSTB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDRESS
0
0

6
8
8
8
8
8

2
8
8·

8
8
8
8

Page A-56

CONTROL WORD

INCB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

MODIFY
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
1

8
8
8
8
8
8

DECB

EXC PT

LENGTH

TYPE

- ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

MODIFY
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

·O

CVTBL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8

3
0

8
8
8
8
8

CONTROL WORD

Page A-57

CVTBW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUT°E
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8

MOVZBL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8

MOVZBW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

3
0

5
0

8
8
8
8
8

Page A-58

CONTROL.WORD

ROTL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
EXEC.UTE
EXECUTE
EXECUTE
EXECUTE

0
0
0
8
8
8
8

ACBB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
BRANCH
MODIFY
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

MOVAB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SELSPC
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

O·
B
0

8
8
8
8

0
8
8
8
8
8
8

CONTROL WORD

Page A-59

PUSHAB

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUT.E
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8

ADDW2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDW3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

ADDRESS
0

4
8
8
8
8

5
0

8
8

CONTROL WORD

Page A-60

SUBW2

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

SUBW3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
0
8
8
8
8

MULW2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESf

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SELSPC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
2

ADDRESS
0

4
8
8
8
8
8

E
E
8
8
8
8

CONTROL WORD

Page A-61

MULW3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC

0
0

EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8

DIVW2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

DIVW3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
F
0
8
8
8
8

~XEC.UTE

3
F

E
8
8
8
8

CONTROL WORD.

Page A-62

BISW2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

BISW3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
5
0
8
8
8
8

BICW2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
4
8
8

8
8
8

8
4

8
8
8
8
8

CONTROL WORD

Page A-63

BICW3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
5

0
8
8
8
8

XORW2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
4
8
8
8

XORW3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
5
0
8

8
8
8

CONTROL WORD

Page A-64

MNEGW

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE . ·
EXECUTE
EXECUTE
EXECUTE

CASEW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

MOVW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

OPT
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

ADDRESS
0

6
0

8
8
8
8
8

c
0
8
8
8
8

8
8
8
8
8
8

CONTROL WORD

Page A-65

CMPW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8
8

MCOMW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8

BITW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
WORD
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE.
EXECUTE
EXECUTE

0
0

6
0

6
8
8
8
8
8

Page A-66

CONTROL WORD

CLRW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

WRITE
WRITE
READ
READ
READ
READ
READ
READ

EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8
8
8

TSTW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8

INCW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

MODIFY
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8

CONTROL WORD

Page A-67

DECW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

MODIFY
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
1
8
8
8
8,
8
8

BISPSW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
4

BICPSW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
4

8
8
8
8

·a

8
8
8
8
8

Page A-68

CONTROL WORD

POPR

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8
8

PUS HR

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

CHMK

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
7

6
8
8
8
8
8
8

8
8
8
8
8
8

CONTROL WORD

Page A-69

CHME

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
.EXECUTE
EXECUTE
EXECUTE
EXECUTE

7
8
8
8
8
8
8

CHMS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

7
8
8
8
8
8
8

CHMU

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

WORD
WORD
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
7
8
8
8
8
8
8

Page A-70

CONTROL WORD

ADDL2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8

ADDL3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8

SUBL2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8

4
8

a·
8
8
8

5
0

4
8
8
8
8
8

CONTROL WORD

Page A-71

SUBL3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SE LS PC
-EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8

MULL2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE.

MULL3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
REA.O
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

5
0

2
E
E
8
8
8
8

0
8
8
8
8

CONTROL WORD

Page A-72

DIVL2

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE·
EXECUTE
EXECUTE
EXECUTE

DIVL3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
·EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
WRITE
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
F
0

BISL2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
4
8
8
8
8
8

ADDRESS
0

3
F

E
8
8
8
8

8
8
8
8

CONTROL WORD

Page A-73

BISL3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
5

8
8
8
8

BICL2

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT·
INT
INT
INT
- INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

BICL3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP.6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

4
8
8
8
8
8

0
8
8
8
8

CONTROL WORD

Page A-74

XORL2

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8

XORL3

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
WRITE
READ
READ
READ
READ

SE LS PC
OPT
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8

MNEGL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

OPT
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

6
0
8
8.
8
8
8

ADDRESS
0

5
0

CONTROL WORD

Page A-75

CASEL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
MODIFY
READ
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
1
0

8
8
8
8

MOVL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

OPT
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
8
8
8
8
8
8

CMPL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

6
8
8
8
8
8

CONTROL WORD

Page A-76

MCOML

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
WRITE
READ
READ
READ
READ
READ

OPT
EXECUTE
SE LS PC
· EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8
8
8
8
8

BITL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG'
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

6
8
8
8
8
8

CLRL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

. LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

WRITE
WRITE
READ
READ
READ
READ
READ
READ

EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

ADDRESS
0
6

8
8
8
8

8
8

CONTROL WORD

Page A-77

TSTL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
. LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

2
8
8
8
8
8
8

INCL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

MODIFY
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE·
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8

DECL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

MODIFY
WRITE
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
1

1
8
8
8
8
8
8

CONTROL WORD

Page A-78

ADWC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
8

8
8
8
8
8

SBWC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

OPT
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

4
8
8
8
8
8

MTPR

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

8
8
8
8
8
8

CONTROL WORD

Page A-79

MFPR

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
·INT
INT

READ
BRANCH
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

MOVPSL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
.LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

WRITE
WRITE
READ
READ
READ
READ
READ
READ

EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

1
0
8
8
8
8
8
8

PUSHL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ·
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

EPl

EP2
EP3
EP4
EPS
EP6
EP7

ADDRESS
0

8
0

8
8
8
8
8

7
8
8
8
8
8
8

CONTROL WORD

Page A-80

MOVAL/MOVAF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SELSPC
SELSPC
EXECUTE
EXECUTE
EXECUTE.
EXECUTE
EXECUTE
EXECUTE

0
0

PUSHAL/PUSHAF

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl·
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

ASRC
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
READ
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

BBS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
VSRC
VSRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
7

8
8

8
8
8

ADDRESS
0

7
8
8
8
8
8
8

8
8
8
8
8

CONTROL WORD

Page A-81

BBC

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
I.ONG
LONG
LONG

INT
VSRC
VSRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

BBSS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
VSRC
VSRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
7

BBCS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
VSRC
VSRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE.LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDRESS
0

A
8
8
8
8
8

Page A-82

CONTROL WORD

BBSC

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPI
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
VSRC
VSRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

BBCC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPI
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
VSRC
VSRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

BBSSI

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPI
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
VSRC
VSRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
7

ADDRESS
0

7
A

8
8
8
8
8

7
A

8
8
8
8
8

A
8
8
8
8

Page A-83

CONTROL WORD

BBCCI

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
VSRC
VSRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

BLBS

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
BRANCH
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8

BLBC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
BRANCH
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ADDRESS
0

7
A
8
8
8
8
8

ADDRESS
1
0

8
8
8
8
8
8

Page A-84

CONTROL WORD

FFS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
VSRC
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
WRITE
READ
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE

0
0

FFC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
VSRC
INT
INT
INT
INT

READ
READ
WRITE
READ
.READ
WRITE
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE

0
0
1
0

CMPV

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
VSRC
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
WRITE
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE

0
0
1
0

0
0
8
8

E
0

8
8

D
0

6
8

CONTROL WORD

Page A-85

·ED

CMPZV

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
VSRC
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
WRITE
READ

SE LS PC
SELSPC
EXECUTE
SELSPC
EXECUTE
SELSPC
EXECUTE
EXECUTE

0
0
1
0
1
0
6

EXTV

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
VSRC
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
WRITE
READ
READ

SE LS PC
SE LS PC
EXECUTE
SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE

0
0
1
0

EXTZV

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
VSRC
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
WRITE
READ
READ

SE LS PC
SE LS PC
EXECUTE
SE LS PC
EXECUTE
SE LS PC
EXECUTE
EXECUTE

0
0
1
0
1
0

8
8

CONTROL WORD

Page A-86

INSV

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
BYTE
BYTE
LONG
LONG
LONG

INT
INT
INT
INT
VSRC
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SE LS PC
SE LS PC
EXECUTE
EXECUTE
EXECUTE

0
0
7
0
0

8
8
8

ACBL

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
BRANCH
MODIFY
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0

AOBLSS

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

B
0

8
8
8
8

ADDRESS
0

c
9
8
8
8

8
8

Page A-87

CONTROL.WORD

AOBLEQ

EXC PT

LENGTH

TYPE

ACCESS

MODE

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
MODIFY
WRITE
READ
READ
READ
READ
READ

SE LS PC
EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

SOBGEQ

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

MODIFY
BRANCH
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

1
1
8
8
8
8
8
8

SOBGTR

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

MODIFY
BRANCH
READ
READ
READ
READ
READ
READ

EXEC/R
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

1
1

ADDRESS
0

c
9
8
8
8
8
8

8
8

Page A-88

CONTROL WORD

CVTLB

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
IN"T
INT
INT
INT
INT

READ
WRITE
READ
WRITE
. READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
4
9
0

CVTLW

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
WORD
LONG
WORD
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
WRITE
READ
WRITE
READ
READ
READ
READ

SE LS PC
EXECUTE
EXECUTE
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE

·O
4

ASHP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
WORD
LONG
BYTE
BYTE
WORD
BYTE
LONG

INT
INT
INT
ASRC
INT
INT
ASRC
INT

READ
READ
BRANCH
READ
READ
READ
READ
BRANCH

SE LS PC
SE LS PC
EXECUTE
SELSPC
SE LS PC
SE LS PC
SE LS PC
EXECUTE

8
8

9
0

8
8

3
0
0
0
0
A

CONTROL WORD

Page A-89

CVTLP

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7.

LONG
WORD
LONG
BYTE
LONG
LONG
LONG
LONG

INT
INT
INT
ASRC
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
WRITE

SE LS PC
SE LS PC
EXECUTE
SE LS PC
EXECUTE·
EXECUTE
EXECUTE
EXECUTE

0
0

CAL LG

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

BYTE
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

ASRC
ASRC
ASRC
INT
INT
·INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
SE LS PC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
0

CALLS

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
BYTE
BYTE
LONG
LONG
LONG
LONG
LONG

INT
ASRC
ASRC
INT
INT
INT
INT
INT

READ
READ
WRITE
READ
READ
READ
READ
READ

SE LS PC
SELSPC
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

0
0
0

D
0
8
8

8
3

8
8

8
8
8
8
8

CONTROL WORD

Page A-90

XFC

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE.
EXECUTE
EXECUTE
EXECUTE

9
8
8
8
8
8
8
8

ESCO

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

ESCE

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE

8
8
8
8
8
8
8

CONTROL WQRD

Page A-91

ESCF

EXC PT

LENGTH

TYPE

ACCESS

MODE

ADDRESS

EPO
EPl
EP2
EP3
EP4
EPS
EP6
EP7.

LONG
LONG
LONG
LONG
LONG
LONG
LONG
LONG

INT
INT
INT
INT
INT
INT
INT
INT

READ
READ
READ
READ
READ
READ
READ
READ

EXECUTE
EXECUTE
EXECUTE
EXECUTE
EXECUTE·
EXECUTE
EXECUTE
EXECUTE

c
8
8
8
8
8
8
8

APPENDIX B
WRITABLE CONTROL STORE

B.l

WRITEABLE CONTROL STORE MEMORY

The writable control store memory consists of 1024 words.
Each word
contains 96 data bits, of which 3 parity bits (1 per each 32 bits of
data). The Control Store (CS) bus outputs are tri-state.
TTL HIGH = "l"
TTL LOW = "O" The normal parity generated is even.

B.2

WRITE DATA TO WCS

The write sequence will require two machine cycles. The first being
the writing of the WCS address register from the ID bus. The second
being the writing of the WCS data to WCS memory from the ID bus.
The
write WCS address cycle and the WCS write data cycle may either be
consecutive cycles or the address may be loaded and sometime later the
data may be loaded.
The same lK module of WCS MUST NOT be the control store in use by the
CPU and have a WCS write data operation being performed on it during
the same machine cycle. The data written into WCS is in true form.
Writing WCS under console control is done by writing the WCS address
register and then doing a WCS write data operation for each 32 bits of
data to be written.
The WCS address counter bits <14:13> (on the micro sequencer) are
loaded with a WCS write address command. These stages are-a modulo-3
counter that selects the 32 bit data group to be written. At the end
of each WCS write data command the counter is incremented, when the
modulo-3 counter overflows; the WCS address register bits <12:00> are
incremented by one.

WRITABLE CONTROL STORE
B.3·

Page B-2

WCS ADDRESS REGISTER

Layout
15

I
PARITY
INVERT

WCS ADDRESS REG. AND
<.12: 00> COUNTER

MODULO
3

COUNTER

BIT 15

= 1 = INVERT PARITY
= 0 = NORMAL PARITY

BIT<l4:13> = 00
= 01
= 10
= 00

B.4

I
I
I
I
I·

= GROUP A = DATA BITS<3l:OO>
= GROUP B = DATA BITS<63:32>
GROUP C = DATA BITS<95:64>
GROUP A

EXTERNAL JUMPER SELECTIONS AND RAM TYPE SELECTION

There are five back panel pins to be used with jumpers or switches for
selecting the one of eight lK segments to be assigned the WCS module.
The voltage level will be at 'O' volts with jumper installed and at
'+3' volts with the jumper removed. The jumper (JS) when out selects
the lower 4K area, and when in selects the upper 4K area. The jumpers
Jl, J2, J3, J4 are to select a WCS module for a particular lK area
from a possible of four lK areas.
Jl

MEM BANK SELECTED

OUT

IN
OUT

IN
IN
OUT

IN
IN
IN
OUT

lST
2ND
3RD
4TH

x
x
x

x
x

----------------lK SEGMENT
lK SEGMENT
lK SEGMENT
lK ·SEGMENT

x = DON'T CARE CONDITION
There is a provision for reading the summary of available writeable
control store segments by doing an ID bus read of the WCS .memory data
register. When this command is received by the micro sequencer
control, a signal is generated which tells all WCS modules to transmit
bits <07:00> onto the ID bus.
ID bus bit 00 represents the 1st lK of
available WCS and bit 07 represents the 8th lK of available WCS memor~
segments.

APPENDIX C
MICRO-CODE DEBUGGER INTERFACE

C.l

OBJECTIVES

wcs.

"The prime objective of the micro-code debugger is to allow
user
to
micro-step
his
micro-program and to examine
micro-machines
internal
registers
without
destroying
micro-machine's state".

the
the
the

Develop a tool needed to debug micro-programs,
Features required and specified here-in are:
-

both

ROM

Entry & Exit, Micro-code Debugger
Micro-Machine State control
Examine & Deposit to Internal Registers
Examine Control Storage Location
Deposit to WCS Location

Also covered are the expected usage restrictions.

C.2

MICRO-CODE DEBUGGER ENTRY & EXIT

The Micro-Code Debugger may be entered from the console _program by
WCS.
The console program is re-entered upon exit from the Micro-code
debugger.
The transfer between the micro-code debugger and the console program,
on both entry and exit, can occur without loss of micro-machine state
if the micro-machine's clock is running or stopped.
·
On both entry and exit,
initialized state.

the

program

(LSI-11)

entered

its

MICRO-CODE DEBUGGER INTERFACE

Page C-2

Specific features provided are:
1.

Load Micro-Code Debugger
If the micro-machine is running or stopped, allow the
Micro-code debugger program to be loaded such that the
micro-machine can be continued correctly upon the debugger
assuming control of the micro-machine.

Load Console Program
If the micro-machine is running or stopped, allow the console
program to be loaded such that the micro-machine can be
continued correctly upon the console program assuming control
of the micro-machine.

C.3

MICRO-CODE DEBUGGER- MICRO-MACHINE- STATE CONTROL

On entry to the Debug<!er from the. Console program, the micro-machine
can be either running or stopped in any TIME STATE tTO-T3).
(time
state readable over V-Bus by console)
If it is stopped the micro-code debugger will advance the clock using
single state step IMO "T3" and will put the micro-machine into the
micro-step mode.
On stopping the micro-machine (or on initial entry if stopped), the
micro-code debugger will examine the Machine State and ·the next
micro-instruction to be executed to determine if it is dependent upon
the current micro-machine state;
if so, special action is required by
the micro-code debugger (later
referred
to
as
a
dependent
micro-instruction):
"STALL" Asserted
If "stall" is asserted, the micro-debugger will "single time
state" the micro-machine until •stall" is de-asserted during T3
by the
micro-machine.
(if
not
de-asserted
after
600
micro-machine cycles, Error Message is printed).
"Dependent Micro-Instruction"
The micro-code debugger will examine the next micro-instruction
to be executed to determine if it is a dependent o~e. This is
done
by
comparing
each
of
the
micro-orders
in
the
micro-instruction against a list of dependent micro-orders.
If
any exist, a warning message is printed on the console, not to
use the micro-debugger's examine & deposit features.

MICRO-CODE DEBUGGER INTERFACE

Page C-3

Specific features are:
1.

Enter Micro-Step Mode
The debugger will be entered into the Micro-Step Mode if
Micro-Machine is stopped.

the

Micro-Step
If the micro-machine is stopped, the micro-machine will
execute one micro-instruction and then stop during T3 prior
to starting execution of the next micro-instruction.
Also single state stepping of the micro-machines clock is
required through the micro-instruction for several reasons,
i.e., setup time required for "slow constants".

Leave Micro-Step Mode
The debugger will leave Micro-Step Mode & the micro-machine
will start running at normal clock speed at the address in
the UPCSV on the next "proceed" command.

Set Micro-Break (SOMM)
If the micro-machine is stopped, the "SOMM" bit will be set,
and On, "PROCEED". The micro-machine will be stopped after
executing the micro-instruction whose address is specified in
10[21].
This feature uses the micro-machine's stop-on-micro-break
match feature to stop itself during TO of the addressed
micro-instruction.
Then the micro-debugger will advance
execution of the current instruction into "T3" state.
The micro-machine
"proceed" command.

will

remain

stopped

until

gets

and

STOP
If the clock is running, this feature will stop
advance it into "T3" of the next micro-instruction.

In addition the micro-code debugger will implement a number of
switches, etc.
to allow micro-breaking on a list of micro-addresses
using the micro-step feature, i.e., Proceed/B.

MICRO-CODE DEBUGGER INTERFACE
C.4

Page C-4

MICRO-CODE DEBUGGER INTERNAL REGISTER & MEMORY EXAMINE & DEPOSIT

The following internal registers and memory may be examined and/or
modified
using
this
feature.
Since the micro-state of the
micro-machine may be modified by the supporting micro-routines in the
micro-machine, the micro-code debugger prints a warning message when
this will occur. (specified earlier in the spec.)
The user can generally get around this problem by entering the machine
into micro-step mode, and micro-stepping the micro-machine until a
warning message is not printed.
The micro-machine facilities that can be examined and or modified are:
IBA, Q, VA, MICRO-PC, D, SC, LA, LB, STATE LC, FE,
(R.O.), RA, RC, ID, & MEMORY.

PC,

RLOG

& PCSV

The micro-code debugger
completes
execution
of
the
current
micro-instruction by advancing the clock using single state step into
TO and applying "ROM NOP" to stop starting execution of the next
micro-instruciton.
Then micro-code debugger saves and restores the various registers that
can be indirectly changed by the supporting micro-routines so that
micro-machine can be successfully restarted (if· a warning message was
not printed) on the next micro-instruction to be executed.
On debugger initiated memory references, the user
must
clear
ID-Registers, TBERl, SBI.ERR, & PARITY if a memory exception occurs
and he wants to continue his micro-program.
Deposits & Examines to memory during memory management
destroy the micro-machine state (no warning printed).

firmware

will

Examine Control Store Location
Since the control store cannot be read by the debugger, the micro-code
debugger examines a load image file that has been opened on a floppy
disk and prints the contents of the field(s)
requested.
(warning
messages can be ignored)

Deposit To WCS Location
Deposits to the field(s) specified in WCS and on the load image floppy
file.
Previous warning messages must be observed.

Page C-5

MICRO-CPDE DEBUGGER INTERFACE
C.5

LIST OF DEPENDENT MICRO-ORDERS

PRINT WARNING MESSAGE*
BEFORE

AFTER

ACF/SYNC

BEN/ALU 1-0.NEQ.ZERO

BEN/TB. TEST

------

FS/=O&MCT/(ALL CODES EXCEPT
"ALLOW. IB. READ)
FS/=O&MCT/LOCKREAD.V.NOCHK
LOCKREAD.V.WCHK
SB I.HOLD
SBI.HOLD+UNJAM
LOCKREAD.P

-----

*
*
*
*
*
*

SUB/SPEC

Sequences that must be avoided using micro-step:
1.

Interlocked read/writes.

SB! UNJAM sequence.

I/O programs.

CS parity error.

Memory Examine/Deposit during memory management F/W.

On sequences 1), 2), & 5) above, Micro-break match can be set to a
micro-instruction following the sequence, then clearing "step" and
then doing the "Proceed" command will execute the sequence at machine
speed, allowing the micro-programmer to skip over these problems.

* Before or after execution of next micro-instruction.

Page C-6

MICRO-CODE DEBUGGER INTERFACE
Future Possible Enhancements
1.

Reducing restrictions on MCT/FIELD micro-orders.
By reading over the V-Bus, determine if micro-trap is pending
or not.
If not, do not print warning message (associated
one).

Examining ID Bus Registers without using Micro-Machine clock.
When the machine is stopped during
ID-REGS.

T3,

allow

examining

If not in T3, use micro-code routine to do the examine after
asking the user if he wants to destroy the machine state.
3.

Examine/Deposit after Warning Message.
Ask user if he really wants to destroy state.
"YEs•, do requested Examine or Deposit.

If response is

APPENDIX D
WCS DEBUGGER HELP FILE

The WCS Debugger help file may be accessed by typing at the console:
>>>@WCSMON.HLP
To call the WCS debugger, type at the console:
>>>WCS
MICRO-DEBUGGER HELP FILE

REV-0

MAY 1977

TO STOP PRINTING, TYPE C
DEBUGGER COMMANDS(ALL TERMINATED BY CARRIAGE RETURN)
'E/P <ADDRESS>'

-EXAMINE PHYSICAL MEMORY

IE/ID <ADDRESS>'

-EXAMINE .ID BUS REGISTER

'E <ADDRESS>'

-EXAMINE WCS LOCATION,

DISP~AY

ALL FIELDS

'E <ADDRESS> <FIELDNAME-l>,<FIELDNAME-2>,,,,<FIELDNAME-N>
EXAMINE WCS LOCATION, DISPLAY ONLY FIELDS
THE FIELDS SPECIFIED
NOTE: <FIELDNAMES> =

. ACF,ACM,ADS,ALU,BEN,BMX,CCK,ClD,DK,DT,EAL
EBM,FEK,FS,IBC,IEK,UJM,KMX,MCT,MSC,PCK,QK·
RMX,SCK,SGN,SHF,SI,SMX,SPO,USU,VAK

'ERA <ADDRESS>'

-EXAMINE AN RA REGISTER

'E RC <ADDRESS>'

-EXAMINE AN RC REGISTER

WCS DEBUGGER HELP FILE

Page D-2
-EXAMINE ONE OF THE SYMBOLICALLY NAMED

'E <SYMBOLIC-NAME>'

REGISTERS
NOTE: <SYMBOLIC-NAMES> = DR,FER,IBA,LA,LB,LC,Q,RL,SC,SR,UPC
'D/P <ADDRESS> <DATA>' -DEPOSIT <DATA> TO PHYSICAL MEMORY
'D/ID <ADDRESS> <DATA>'

-DEPOSIT <DATA> TO ID BUS REGISTER

'D <ADDRESS> <FIELDNAME-1> <DATA-l>,<FIELDNAME-2> <DATA-2>, ••••••••
-DEPOSIT TO WCS LOCATION, PUTTING <DATA-1>
INTO <FIELDNAME-1>, ETC. UNSPECIFIED FIELDS
ARE UNCHANGED.
NOTE: THE '/Z' QUALIFIER MAY BE USED TO CAUSE ALL UNSPECIFIED
FIELDS TO BE CLARED.
'D RA <ADDRESS> <DATA>'

-DEPOSIT <DATA> TO AN RA REGISTER

'D RC <ADDRESS> <DATA>'

-DEPOSIT <PATA> TO AN RC REGISTER

'D <SYMBOLIC-NAME> DATA>'

-DEPOSIT <DATA> TO ONE OF THE SYMBOLICALLY
NAMED REGISTERS (SEE LIST ABOVE).

NOTE: DEPOSITS TO THE RLOG STACK(RL).ARE NOT SUPPORTED.
'CONTINUE'

-RESUME MICRO-INSTRUCTION EXECUTION AS
SPECIFIED BY CONTENTS OF MICRO-PC(UPC)

'START <ADDRESS>'
'HALT'

-START MICRO-SEQUENCER AT <ADDRESS>.
-HALT THE MICRO-SEQUENCER

'SET SOMM'

-SET THE 'STOP ON MICRO-MATCH' ENABLE

'CLEAR SOMM I

-CLEAR THE 'STOP ON MICRO-MATCH' ENABLE

WCS DEBUGGER HELP FILE

Page D-3
-ENABLE SINGLE MICRO-INSTRUCTION STEP MODE.

'SET STEP'

START OR CONTINUE WILL ALLOW ONE MICROINSTRUCTION TO EXECUTE, THEN HALT THE
MICRO-SEQUENCER.
'CLEAR STEP'

-DISABLE SINGLE MICRO-INSTRUCTION STEP MODE.

'RETURN I

-RETURN TO THE CONSOLE PROGRAM

'OPEN <FILENAME>'

-OPEN SPECIFIED FILE ON FLOPPY DRIVE 0

'OPEN DXl:<FILENAME>'

-OPEN SPECIFIED FILE ON FLOPPY DRIVE 1

NOTE:

'OPEN' IS USED TO SPECIFY A FILE CONTAINING THE MICRO-CODE
CURRENTLY LOADED IN THE WCS PORTION OF THE CONTROL STORE.
(ADDRESSES 1000(16) & UP IN THE CONTROL STORE)
THIS FILE WILL BE USED FOR ALL EXAMINES QF THE WCS,
SINCE THE WCS IS NOT DIRECTLY READABLE.

APPENDIX E
PROM CONTROL STORE SPECIFICATION

The control store (CS) bus outputs are tri-state
TTL HIGH = 0 1"
TTL LOW = "O"
CS bus output loading by other subsystems
A maximum of 2 loads/bit, external
sequencer modules will be allowed.
of the module fingers.

E.l

to the control store and the micro
User receivers are to be within 6 inches

PROM ADDRESS PATH

The PROM address is selected by Micro Program Counter
(UPC)
bits <09:00>.
UPC Bit <12> selects either the lower 4K bank or the higher 4K bank of PROM.
UPC Bits <11:10> select one of the four lK segments to be accessed.

E.2

PARITY ERROR DETECTION

The parity tree is 99 bits wide and
is done in two levels.
The parity
checking
is for 96 data bits and 3 parity bits.
Each parity bit makes up
even parity for 32 consecutive data bits. That is, there will be an even
number of l's in the 33 bit field (32 data and 1 parity). For example:
BIT

-------------------

31 30 29
3
1 0 1 <--------0--------> 1
1 0 0 <--------0--------> 1

2
0
0

1
0
0

0
0
0

PARITY
l
0

EVEN
EVEN

If the micro program tried to access non-existant control store memory, then
NO CS bus drivers ·would be enabled. This would cause an all l's condition
including parity on the CS bus due to the terminator pull-up resistor.
The
parity error detection logic will see this as odd parity and flag a micro
word parity error, then resulting in a micro trap.

PROM CONTROL STORE SPECIFICATION
E.3

Page E-2

EXTERNAL JUMPER SELECTIONS AND CS TYPE SELECTION

There are five back panel pins to be used with jumpers or switches for board
and segment selection.
The jumper {JS) when in selects the lower 4K bank,
and when out selects the upper 4K bank. The jumpers Jl, J2, J3, J4 each
select a lK segment when removed. When a jumper is in, that particular lK
segment is disabled.
Jl
J2
J3
J4

selects or disables
selects or disables
selects or disables
selects or disables

the
the
the
the

1st
2nd
3rd
4th

lK segment
lK segment
lK segment
lK segment

Page

Index-I

INDEX

Abort Condition, A-5
Aborts, 5-13
ACC CONTROL/STATUS, 3-8
ACC MAINT, 3-8
ACC REG #0 THRU #1, 3-8
Accelerator control, 9-7
ACCELERATOR INTERFACE, 4-11
ACCELERATOR interface operation,
9-6
Accelerator maintenance register,
9-9
Accelerator status registers, 9-9
Accelerator trap, 9-7
Access control violation - fault,
5-18
Acknowledging exceptions, 5-23
ADDRESS BUS, 7-2
Address Section, 1-51
Address section
data path, 1-51
Alignment
byte, 1-46
data, 1-37
memory data byte, 1-44
Alternate data transfers, 9-9
Altern~te trap function, 9-7
ALU, 1-3
A input multiplexor, 1-5
B input multiplexor, 1-7
AMX, 1-5
Arithmetic and logic unit, 1-3
Arithmetic Section, 1-3
Arithmetic section
data path, 1-3
Arithmetic trap - TRAP, 5-21
Arithmetic trap acknowledging,
5-23
Asynchronous system trap level reg.
ASTR, 5-11
BAL, 1-46
Bit field too wide - fault, 5-16
Bit mask generator, 1-18
BMX, l-7
BPT opcode - FAULT, 5-20
Branch Enable Field (uBen), 2-8
BUFFER DATA PATH, 4-1
Buffer Register, 4-1

BUS DFMX, 1-34
Byte alignment, 1-46
BYTE ROTATOR, 4-4
CACHE INTERFACE, 4-11
Cache parity error, 5-15
Cache Stalls, 2-6
Call Subroutine, 2-9
CHMX instructions, 5-25
CHMX opcodes, 5-22
Classes of exceptions, 5-13
CLOCK BUS, 7-2
CLOCK CONTROL/STATUS, 3-6
CNSL halt, 5-24
CNSL RXCS, 3-5
CNSL RXDB, 3-6
CNSL TXCS, 3-6
CNS L TXDB, 3-6
Compatability mode trap
TRAP/ABORT, 5-20
Console Control of ID BUS, 3-5
Console controlled Operations,
2-11
Console Terminal Interrupts, 5-7
Context Lookup, 4-8
Control store parity error, 5-15
Control Store Parity Error
Micro Trap mode, 2-4
Control store parity error
trap mode, 2-4
CPU branches, 9-7
CPU ERROR/STATUS, 3-14
CPU Power Fail, 5-5
CPU Timeout, 5-5
Cpu/console interface state, 6-6
CRD/RDS, 5-6
CS BUS, 7-1
D, 1-41
D PGEN, 1-46
D register, 1-41
multiplexo~, 1-36
parity generator, 1-46
D,Q (MAINT MODE ONLY), 3-13
DAL, 1-37
Data alignment, 1-37
Data format multiplexor, 1-33
Data from accelerator, 9-8

Page
DATA INTERFACE, 9-8
Data Length Field, 4-9
Data path
address section, 1-51
arithmetic section, 1-3
data section, 1-33
exponent section, 1-26
Data Section, 1-33
Data section
data path , 1-3 3
Data to accelerator, 9-8
Data transfer, 9-6
Decimal string too long - fault,
5-18
Definitions, 9-2
Description of
exception conditions, 5-14
Interrupt Conditions, 5-5
utrap conditions, 5-26
DFMX, 1-33
OMX, 1-36
EALU, 1-26
EAMX, 1-27
EBMX, 1-28
ECO control, 2-1
Error acknowledging, 5-23
Error logout, 6-3
Errors, 5-26
Exception conditions
and their vectors, 5-13
Exceptions, 5-12
EXECUTION POINTS, 4-9
Exponent
ALU, 1-27
arithmetic logic unit, 1-26
Exponent Section, 1-26
Exponent section
data pa th, 1-2 6
External Device Interrupts, 5-7
External jumper selections and
cs type selection, E-2
ram type selection, B-2
Fast constant multiplexor, 1-14
Faults, 5-13
FE, 1-29
FIRST PART DONE, 4-10
FK, 1-14
FPDA, D.SV, Q.SV, 3-16
From data path - none, 7-6

Index-2

FROM IB, 7-2
FROM MICROSEQUENCER, 7-3
FROM TRAPS AND INTERRUPTS, 7-4
Functional Operation, 3-1
General description, 7-30
General register updates, 9-9
Halt code from vector, 5-25
Halt conditions, 5-24
Halt identification codes, 6-7
Halt Instruction, 5-24
I-STREAM DATA MUX, 4-5
IB Addressing, 4-10
IBUF DATA, 3-5
ID bus, 3-1
ID BUS Addresses, 3-2
ID BUS Control, 3-3
ID BUS Data, 3-3
ID BUS Register Description, 3-5
Id bus registers on cib, 8-6
Illegal entry mask - fault, 5~17
Illegal floating number -'fault,
5-16
Illegal Machine Sequence Error,
5-15
Illegal PCB entry - abort, 5-17
Illegal processor reg - fault,
5-17
Illegal PSL image - fault, 5-17
Initial data transfer, 9-6
Initialization of cp, tbuf, cache, &
sbi status registers, 6-6
Initialize, 2-7
INPUT MULTIPLEXER, 4-4
Instruction aborts, 6-2
Instruction faults, 6-3
Instruction halts, 6-3
Interface specification, 9-2
Internal data bus, 3-1
control, 3-3
directional control, 3-3
normal operation, 3-1
Internal register, C-4
Interrupt Acknowledge, 5-8
Interrupt Priority Level (IPL),
5-1
Interrupt priority level register
IPLR, 5-9
Interrupt Requests

Page
and their Vectors, 5-3
Interrupt stack not valid, 5-25
Interrupt Strobe, 5-8
Interrupts, 5-1
INTERVAL COUNT, 3-7
Interval Timer, 5-6
IR DECODE, 4-7
ISB INTERFACE, 9-10
JFIELD, 2-8
Jump field, 2-8
Jump Field (JField or uJMP), 2-8
Kernel stack not valid
raises IPL to lF, 5-16
LA, 1-19
LA and LB, 1-19
Latch
A, 1-19
B, 1-19
c, 1-18
Latching
UPC address, 2-14
LB, 1-19
LC I 1-18
LIST OF DEPENDENT MICRO-ORDERS,
C-5
Machine check - raises IPL to lF,
5-14
Machine checks, 6-1
Machine halts, 5-24
Maintenance Operation, 3-4
MASK, 1-18
MBIT I 5-26
MD BUS I 7-1
MDBAL, 1-44
Memory data byte alignment, 1-44
MICRO Control Use, 4-3
Micro ECO control (UECO) Mode, 2-1
Micro sequencer
ECO control mode, 2-1
normal mode, 2-1
parity error trap mode, 2-4
trap mode, 2-3
Micro Subroutine Field (USUB), 2-8
Micro Trap (UTRAP) Mode, 2-3
MICRO-CODE DEBUGGER, C-2, C-4
ENTRY & EXIT, C-1
MICRO-MACHINE State Control, C-2

Index-3

Microbranches, 7-6
Microcoding suggestions, 7-31
MICROORDERS, 7-7
Multiplexer Shift Network, 4-2
Multiplexors
ALU A input, 1-5
ALU B input, 1-7
constant, 1-14
fast, 1-14
slow, 1-14
NEXT INTERVAL COUNT, 3-7
NMX, 1-55
Normal Mode, 2-1
Normal Operation, 3-1
Number multiplexor, 1-55
Objectives, C-1
Other Fields
UBS+UBCT (not on USC) , 2-9
POBR, PlBR, SBR, POLR, PlLR, SLR, PCBB,
SCBB KSP, ESP, SSP, USP, ISP,
3-16
Page boundary, 5-26
Parity error
trap mode, 2-4
Parity error detection, E-1
Parity generator
D register, 1-46
PC, 1-54
PC UPDATES, 4-6
PCADD, 1-55
PCAMX, 1-56
PCMX, 1-56
PCSV, 1-25
Pico sequencer, 2-13
and Priority decoding, 2-13
Power
down, 2-10
up, 2-10
Power up or Down, 2-10
Priority decoding, 2-13
Program counter, 1-54
adder, 1-55
adder multiplexor, 1-56
multiplexor, 1-56
Program counter save register,
1-25
Prom address path, E-1
Protection violation, 5-26

·Page
PSL, 3-13
PSW MBZ FIELD not zero - fault,
5-17
Q, 1-38
Q register, 1-38
multiplexor, 1-35
QMX, 1-35
RA, 1-19
RAMX, 1-50
RB, 1-19
RBMX, 1-50
RC, 1-18
Read data substitute, 5-15
Read timeout, 5-14
Register AMX multiplexor, 1-50
Register BMX multiplexor, 1-50
Register Latched Number, 4-8
Register log stack, 1-25
Register set
A, 1-19
B, 1-19
c, 1-18
REGISTERS, 7-11
Registers used for
interrupt servicing, 5-9
Reserved
addressing modes - fault, 5-18
cust opcodes, 5-16
DEC opcodes & priv. instr, 5-16
floating operand, 5-26
operands, 5-16
pattern operator - Fault, 5-18
Retryable Instruction List, 6-8
Return Subroutine, 2-9
RLOG, 1-2 5
SB! Alert, 5-6
SB! CACHE PARITY, 3-11
SB! Fault, 5-5
SBI FAULT/STATUS, 3-10
SBI MAINTENANCE, 3-11
SBI SILO, 3-9
SB! SILO COMPARATOR, 3-10
SBI SILO Compare, 5-6
SBI TIMEOUT ADDRESS, 3-10
SC, 1-32
Scratch pad control, 1-20
Selected internal
subsystem signals, 7-6

Index-4

Sequencer, 2-1
Serialization of events
at Fork A, 5-27
SHF, 1-11
SHIFT NETWORK, 4-2
Shifter, 1-11
Signal Summary, 3-3
SIR, 3-13
SK, 1-14
Slow constant multiplexor, 1-14
SMX, 1-31
Software interrupt
request register - SIRR, 5-12
summary register - SISR, 5-11
Software Interrupts, 5-7
Specifier 1 Constant, 4-8
Specifier 2 Constant, 4-9
Stalls
cache, 2-6
STATE, 1-30
System clock, 9-8
System Control Block, 5-2
System control block
base register - SCBB, 5-9
SYSTEM ID, 3-5
System init, 5-26
System Initialize, 2-7
TBUF DATA, 3-8
TBUF miss, 5-26
TBUF REGO, 3-9
TBUF REG!, 3-9
Terminal Control Registers
in the Procreg Space, 8-26
The console/cpu interface, 8-3
The Control Word, A-1
The q-bus registers, 8-8
TIME OF DAY, 3-7
TO DATA PATH, 7-6
TO IB, 7-3
TO MICROSEQUENCER, 7-3
TO TRAPS AND INTERRUPTS, 7-4
Trace trap - TRAP, 5-20
Trace trap acknowledging, 5-23
Translation buffer parity error,
5-15
Translation not valid - fault,
5-19
Trap mode, 2-3
Traps, 5-13

Page
UALU, 1-4
UAMX, 1-7
UBMX, 1-10
UBREAK, 3-12
UDK, 1-43
UDT, 1-7, 1-14
UEALU, 1-27
UEBMX, 1-29
UECO, 2-1
UFEK, 1-30
UJMP, 2-8
Unaligned data, 5-26
UPC address latching, 2-14
UPCK, 1-55
UQK, 1-40
Use of the q-bus registers, 8-20
USGN, 1-10
USHF, 1-13
US!, 1-13, 1-41
USMX, 1-32
USTACK, 3-11
USUB, 2-8
UTRAP, 2-3
conditons and their vectors,
5-25
f unction, 5-2 5
UWORD control for exceptions, 5-24
UWORD Control for Interrupts, 5-8
V BUS, 7-2
VA, 1-52
VAMUX, 1-53
VECTOR, 3-15
Vector register, VECTOR, 5-10
Vectors, 5-2
VIBA, 1-~l
Virtual address
counter, 1-52
multiplexor, 1-53
Virtual instruction buffer
address counter, 1-51
WCS ADDRESS, 3-12
Wes address register, B-2
WCS DATA/STATUS, 3-12
Write data to wcs, B-1

Index-5

VAX 11/780 DATA PATH
DESCRIPTION
AA-H307A-TE
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