VAX 11/780 Data Path Description

This document, "VAX 11/780 DATA PATH DESCRIPTION (AA-H307B-TE)" from February 1979, provides a comprehensive technical description of the VAX 11/780 CPU's internal architecture and operational mechanisms.

Key aspects covered include:

1. Data Path Specification: Detailed descriptions of the CPU's core processing units, including the Arithmetic Section (ALU, registers, shifters for data manipulation), Exponent Section (for floating-point operations), Data Section (handling data formatting, alignment, and various data registers), and Address Section (for virtual address generation and program counter management).
2. Micro Sequencer Specification: Explanation of the CPU's control unit, covering its normal operation, microcode ECO (Engineering Change Order) control, micro traps for error handling, cache stalls, system initialization, and the mechanisms for subroutine calls, jumps, and branching.
3. Internal Data Bus (ID BUS) Specification: A detailed overview of the high-speed internal bus connecting major functional areas of the CPU, including its functional operations (normal and maintenance modes) and the numerous internal registers accessible via this bus.
4. Instruction Buffer (IB): Description of the eight-byte array responsible for fetching and decoding instruction stream data, including its data path, shift network, input multiplexers, and how it handles PC updates and interacts with the cache and accelerator.
5. Interrupts & Exceptions: A thorough explanation of how the system handles asynchronous events (interrupts) and synchronous error conditions (exceptions, traps, faults, aborts), detailing their priority levels, vectors, and the mechanisms for detecting and acknowledging them.
6. Machine Check Abort/Fault/Halt: Specifics on severe error conditions that lead to machine checks, instruction aborts, faults, or halts, including error logging and lists of retryable instructions.
7. Cache-SBI-Translation Buffer (TB) Subsystem: Details on the memory hierarchy and address translation components, including various internal buses (MD, CS, V, Clock, Address), registers, and microcoding suggestions for their interaction.
8. Console Subsystem: Description of the LSI-11 based console and its interface with the CPU for diagnostic, control, and I/O functions, including accessible registers and operational modes.
9. Accelerator Interface: Details on the optional co-processor interface, covering synchronization, data transfer, accelerator control, status flags, and general register updates for enhanced processing.
10. Appendices: Supplementary technical details on the microcode control word format, writable control store (WCS) specifications, PROM control store, and the micro-code debugger interface for development and diagnostics.

In essence, the document provides a deep dive into the VAX 11/780 CPU's internal data flow, control logic, error handling, and interfaces with memory, console, and optional accelerators, crucial for understanding its hardware architecture.