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MISC-68409916

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Document:	KA630-A Processor Specification
Order Number:	MISC-68409916
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Pages:	85
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KA630-A

Processor

Specification
Rev. 3.4

Date: 26-Apr-85

PRE LIM I N A R Y

Jay Nichols
DTN 223-7094
ML5-5/E71

COM PAN Y

CON F IDE N T I A L

Copyright (c) 1983, 1984 by Digital Equipment Corporation
The information in this document is subject to change
without notice and should not be construed as a commitment
by Digital Equipment Corporation. Digital Equipment
Corporation assumes no responsibility for any errors that
may occur in this document.
This specification does not describe any program or product
which is currently available from Digital Equipment
Corporation. Nor does Digital Equipment Corporation commit
to implement this specification in any program or product.
Digital Equipment Corporation makes no commitment that this
document accurately describes any product it might ever make.

Table of Contents
Page
1.0

Introduction....................................
1.1 Scope of Document
1.2 Applicable Documents

1-1
1-1
1-1

2.0

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 KA630 and MS630 Option Summary
2.2 KA630-A Processor Module Feature Summary

2-1
2-2
2-3

3.0

Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Dimensions
3.2 KA630 Module Pinouts
3.3 KA630 Module Connectors
3.4 MS630 Module Pinouts
3.5 MS630 Module Connectors

3-1
3-1
3-2
3-2
3-5
3-6

4.0

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . .
4.1 DC Power Consumption
4.2 Bus Loads
4.3 DeOK Signal
4.4 POK Signal
4.5 Battery Backup Specifications

4-1
4-1
4-1
4-2
4-2
4-2

5.0

Environmental and Reliability
5.1 Storage Conditions
5.2 Operating Conditions
5.3 Mean Time Before Failure

5-1
5-1
5-1
5-1

6.0

Central Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 MicroVAX CPU Chip Description
6.2 Processor State
6.2.1 General Purpose Registers
6.2.2 Processor Status Longword
6.2.3 Processor Registers
6.3 Instruction Set
6.4 Interrupts and Exceptions
6.4.1 Interrupts
6.4.2 Exceptions
6.4.3 Machine Check Parameters
6.4.4 Halt Conditions
6.4.5 System Control Block (SCB)
6.5 Hardware Detected Errors
6.5.1 Non-Existent Memory Errors
6.5.2 Parity Error Detection
6.5.3 Interrupt Vector Timeouts
6.5.4 "No Sack" Timeouts
6.6 Latency Specifications
6.6.1 Interrupt Latency
6.6.2 Interrupt Service Time
6.6.3 DMA Latency
6.7 System Identification

6-1
6-1
6-2
6-2
6-3
6-:4
6-8
6-8
6-9
6-10
6-11
6-12
6-13
6-15
6-15
6-15
6-16
6-17
6-17
6-17
6-18
6-18
6-19

7.0

Memory Management ...............................
7.1 Physical and Virtual Address Space
7.2 Memory Management Control Registers
7.3 System Space Address Translation
7.4 Process Space Address Translation
7.4.1 PO Region Address Translation
7.4.2 PI Region Address Translation
7.5 Page Table Entry

7-1
7-1
7-2
7-2
7-4
7-4
7-6
7-8

8.0

Floating Point ..................................

8-1

9.0

KA630 Memory System ................... . . . . . . . ..
9.1 Memory System Summary
9.2 KA630 Local Memory
9.3 Mapping Registers
9.3.1 Mapping Register Format
9.3.2 Mapping Register Addresses
9.3.3 Q22-Bus Map Operation
9.4 Memory System Registers
9.4.1 Memory System Error Register
9.4.2 CPU Error Address Register
9.4.3 DMA Error Address Register
9.5 Memory System Operation

9-1
9-1
9-1
9-1
9-1
9-2
9-3
9-4
9-4
9-8
9-8
9-9

10.0

KA630 Boot and Diagnostic Facility ............. .
10.1 Boot and Diagnostic Register
10.2 ROM Memory
10.2.1 ROM Sockets
10.2.2 ROM Address Space
10.2.3 KA630-A Console Program Operation

10-1
10-1
10-3
10-3
10-3
10-4

11. 0

Time of Year Clock ............................. .
11.1 Battery Backed-up Watch Chip
11.2 Watch Chip Registers
11.2.1 Time of Year Data Registers
11.2.2 Control and Status Register A
11.2.3 Control and Status Register B
11.2.4 Control and Status Register C
11.2.5 Control and Status Register D
11.2.6 RAM Memory
11.3 Powerup
11.3.1 Valid RAM and Time
11.3.2 Invalid RAM and Time

11-1
11-1
11-1
11-2
11-2
11-3
11-4
11-4
11-4
11-5
11-5
11-5

12.0

Interval Timer ............................... .
12.1 Interval Clock Control/Status Register
12.2 Interval Timer Operation

12-1
12-1
12-1

13.0

Console Serial Line ........................... .
13.1 Console Functionality
13.2 Console Registers
13.2.1 Console Receiver CiS Register
13.2.2 Console Receiver Data Buffer
13.2.3 Console Transmitter ciS Register
13.2.4 Console Transmitter Data Buffer
13.3 Additional Specifications
13.4 Break Response

13-1
13-1
13-1
13-2
13-3
13-4
13-5
13-5
13-5

14.0

Q22-Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.1 Bus Initialize Register
14.2 Multi-level Interrupts
14.3 Interprocessor Communication Facility
14.3.1 Interprocessor Corom Register
14.3.2 Interprocessor Doorbell Interrupts

14-1
14-1
14-1
14-1
14-2
14-3

15.0

Multi-Processor Considerations ................ .
15.1 Auxiliary/Arbiter Differences
15.2 Multi-Processor Features
15.3 KA630 Based Multi-Processor Systems
15.4 PDP11 Based Multi-Processor Systems

15-1
15-1
15-2
15-2
15-3

Appendix A

Module Pinouts ...........................

A-I

Appendix B

Connector and Jumper Summary

B-1

Appendix C

Physical Address Assignments

C-1

REVISION HISTORY
REV

DATE

0.0

27-Jun-83

Working Document: For use by Mayflower
Design Team.

1.0

02-Aug-83

Preliminary Spec: Sent out for review.

2.0

01-Nov-83

The more significant changes include:
1) the change from memory daughter
boards to memory expansion modules;
2) expansion of Q22-Bus map to 4MB;
3) the change in the handling of
multi-level Q22-Bus interrupts,
including the elimination of the
Interrupt Control Register;
4) further simplification of the
multi-processor hooks and arbiter/
auxiliary differences
5) Changes to the Memory System Error
and Memory Error Address Registers and
elimination of the PDP-II compatible
Memory Control and Status Register.

3.0

20-Feb-84

The more significant changes include:
I} The 24-pin external connector has
become two connectors: a 10-pin console
SLU connector and a 20-pin Display and
Configuration Connector.
2) Memory expansion signal pinouts for
the CD Interconnect have been defined.
3) The Memory Error Address Register
has been split out into two registers:
the CPU Error Address Register and the
DMA Error Address Register.
4)
The definition of Memory System
Error Register bit <00> (PAR ENB) has
been clarified.
5} The number of BDG Code bits has been
reduced from three to two, affecting both
the Boot and Diagnostic Register and the
Display and Configuration Connector.

3.1

20-Jul-84

The more significant changes include:
1) The names KDQ32 and MSA32 have been
changed to KA630 and MS630 respectively.
2) The four error display bits in the
Boot and Diagnostic Register are now
read/write bits (section 10.1).
3) The battery backup specification for
the Time of Year Clock is now 240 hours.

REASON

REV

DATE

3.2

17-0ct-84

The more significant changes include:
1) Console SLU Connector Pin 01 has been
defined (section 3.3.3).
2) Section added on system identification
registers (section 6.7).
3) Memory Arbiter gives higher priority
to external device requests (section 9.5).
4) Note added on treatment of address
bit 0 during byte reads (section 9.5).
5) The setup of TOY Clock CSR A has been
corrected {section 11.2.1}.

3.3

04-Mar-85

The more significant changes include:
1) The DC Power AC/DC loading values have
been added (sections 4.1 and 4.2).
2) Mean Time between Failure specifications
have been updated (section 5.3).
3) The Local Memory External Access Enable
bit in the Interprocessor Communication
Register is now cleared by writes to Bus
Initialize Register; reflects design,
which can not be changed (section 14.3.1).

3.3

04-Mar-85

The more significant changes include:
1) The maximum operating temperature was
reduced to reflect characteristics of
the current version of MicroVAX chip
(section 5.2).

REASON

1.0

Introduction

1.1

Scope of Document

This specification documents the functional, physical and
environmental characteristics of the KA630-A Processor
Module. It also provides information on the MS630 memory
expansion modules which are documented more completely in
the MS630 Memory Module Specification.
1.2

Applicable Documents

The following reference material contains detailed information
regarding the V~~-ll family, the KA630-A module, and the required
environment.
KA630-A Console Program Specification
MS630 Memory Module Specification
MicroVAX Architecture Reference Manual
MicroVAX CPU Chip Engineering Specification
MicroVAX CPU Chip Design Specification
MicroVAX FPU Chip Engineering Specification
MicroVAX FPU Chip Design Specification
VAX Architecture Handbook
VAX Software Handbook
VAX Hardware Handbook
DEC STD 32

VAX Architecture Standard

DEC STD 102
DEC STD 160

Environmental Specification
Q-Bus Specification

2.0

General Description

The KA630 is a quad height Q22-Bus VAXll which consists of a
single KA630 processor module.
The KA630 module contains a MicroVAX Central Processor Chip,
which includes Memory Management, an optional Floating Point
Processor Chip, either 256KB or 1MB of on-board memory, a
Q22-Bus interface, a Q22-Bus Map for DMA transfers, an Interval
Timer, a Boot and Diagnostic Facility, a console serial line
unit and a time of year clock with support for battery backup
(batteries are located on the system back panel) .
The KA630 module utilizes the backplane CD Interconnect and a
50-pin connector to communicate with up to two MS630 memory
expansion modules, each of which may contain 1MB, 2MB, 4MB or
8MB of additional local memory.
The KA630 module can be configured as the arbiter CPU or as one
of three auxiliary CPU's. An interprocessor communication register
facilitates the use of this module in multiprocessor systems.
When configured as the arbiter CPU, the KA630 mounts in the first
slot of a Q22-Bus backplane. This first backplane slot, plus any
slots occupied by MS630 modules, must feature the CD Interconnect.
The arbiter KA630 arbitrates Bus Mastership and fields Q22-Bus
interrupt requests BR7-4. It can also respond to interrupt
requests from its own interval timer, console serial line unit
and interprocessor doorbell.
When configured as an auxiliary CPU, the KA630 mounts in any
Q22-Bus/CD-Interconnect backplane slot not already occupied by
the arbiter CPU or associated memory expansion modules. The
arbiter may be a Q22-Bus PDPll or another KA630. The auxiliary
KA630 requests bus mastership to access the Q22-Bus. It does not
field Q22-Bus interrupt requests, but can respond to interrupt
requests from its own interval timer, console serial line unit
and interprocessor doorbell.

2.1

KA630 and MS630 Option Summary

The KA630-A processor module is available with either 256KB or
1MB of on-board memory and with or without the floating point
processor. The option designations are as follows:
Option

Description

KA630-AA

Quad height Q22-Bus MicroVAX CPU Module includes
MicroVAX processor chip, floating point processor
chip, 1MB on-board memory, Console SLUr Interval
Timer, Boot/Diag ROM, and Q22-Bus Map/Interface;
accepts up to two MS630 memory expansion modules;
can be configured as Arbiter or Auxiliary CPU.

KA630-AB

KA630-AA without floating point processor chip.

KA630-AC

KA630-AA with only 256KB of on-board memory_

KA630-AD

KA630-AC without floating point processor chip.

The MS630 memory expansion modules are available with 1MB, 2:t-1B,
4MB or 8MB of memory_ The option designations are as follows:
Option

Description

MS630-AA

1MB Memory Expansion Module for KA630-A Processor;
dual height module with 256K RAM's.

MS630-BA

2MB Memory Expansion Module for KA630-A Processor;
(half populated MS630-BB) .

MS630-BB

4MB Memory Expansion Module for KA630-A Processor;
quad height module with 256K RPJ~1S.

MS630-CA

8MB Memory Expansion Module for KA630-A Processor;
quad height module with 1M RAM's.

2.2

KA630-A Processor Module Feature Summary

KA630-A Processor Module Summary
Quad Height Module
Configurable as Arbiter or Auxiliary CPU
Each System contains one Arbiter CPU
Each System may contain up to three Auxiliary CPU's
MicroVAX Processor Chip
MicroVAX Subset of VAX Data Types
MicroVAX Subset of VAX Instruction Set
Full VAX Memory Management
Float.ing Point Processor Chip (on KA630-AA and KA630-AC only)
Subset of VAX Floating Point Data Types
Subset of VAX Floating Point Instruction Set
Local Memory
256KB or 1MB of on-board local memory
Supports up to two MS630 Memory Expansion Modules, each
containing 1MB, 2MB, 4MB or 8MB of additional local memory
Byte parity generation and checking for all local memory
64KB Boot and Diagnostic ROM
Subset VAX Console Program
Power-up Diagnostics
Boot Programs for Standard Devices
Console Serial Line Unit
Accessed via four VAX Internal Processor Registers
Externally Settable Baud Rates
KA630 Interprocessor Communication Register
Interval Timer
10 Millisecond Interrupts
Interrupts Enabled via Internal Processor Register
Time of Year Clock
Q22-Bus Interface
Direct Memory Accessing (DMA)
Q22-Bus Map which allows DMA to access Local Memory
via a 4MB Window divided into 8192 independent pages
Arbiter KA630 Fields Q22-Bus Interrupt Requests BR7-4
240 Ohm Termination

3.0

Physical Specifications

3.1

Dimensions

The MS630-AA is a dual height module:
Height

5.187 +.015/ -.020 inches

Length

8.430 +.010/ -.010 inches

Width

.375 inches maximum (non-conductive)
.343 inches maximum (conductive)

The KA630-A, MS630-BA, MS630-BB and MS630-CA are quad height
modules:

Note:

Height

10.457 +.015/ -.020 inches

Length

8.430 +.010/ -.010 inches

Width

.375 inches maximum (non-conductive)
.343 inches maximum (conductive)

Width, as defined for digital equipment modules, is the
height of components above the surface of the module.

+------------------------------------------------------+
J2

+-+

Row D

+---+

Row C

+--+

Row B

! J3 !

+---+

Row A

Front View of KA630 Connector Locations
Figure 3-1

+-+

3.2

KA630 Module Pinouts

The KA630 AB row module pinouts are compatible with the Q22-Bus
specification (DEC standard 160). The SRUN L signal appears on
pin AF1. The CD row module pinouts utilize the CD-Interconnect
to communicate with up to two memory expansion modules.
Note:

The KA630 Module can not be used in slots for which the
Q22-Bus is connected to both the AB and CD rows (Q22/Q22
configuration). The backplane CD rows must be compatible
with the entire CD-Interconnect specification (required
for the use of MS630 modules) or must make no connections
except for the +5 volt and ground pins designated by the
CD-Interconnect specification.

Appendix A summarizes the module pinouts for the KA630 module.
3.3

KA630 CPU Module Connector Pinouts

Figure 3-1 shows the locations of the KA630 Memory Expansion
Connector (J1), the Configuration and Display Connector (J2)
and the Console SLU Connector (J3).
3.3.1

KA630 Memory Expansion Connector Pinouts

The Memory Expansion Connector (J1) is a 50-pin connector which
features the following control, data and ground signals:
BUFEN 1:0
BDIRT
PE 3:0
MD 31:00
GND

L
L
H
H

(2 pins)
pin)
pins)
(32 pins)
(11 pins)
(I
(4

The CD interconnect (refer to section 3.2 and Appendix A) features
the following 29 additional address and control signals for the
memory expansion modules:
09:00
7:0
BMCAS 3:0
BMSWT 2:1
MSID
4:0
MAA
RAS

H
H
H

(10
(8
(4
(2
(5

pins)
pins)
pins)
pins)
pins)

3.3.2

Configuration and Display Connector Pinouts

The Configuration and Display Connector (J2) is a 20-pin
connector which features the following pinouts:
Pin

Mnemonic

01
02
03

GND
GND
GND

04
05

CPU CDO L
CPU CDl L

Meaning
Ground.

CPU Code <1:0>. This 2-bit code determines
whether the KA630 is configured as the
arbiter or as one of the three auxiliaries:
CPU CD <1:0>
00
01
10
11

Configuration
KA630 Arbiter
KA630 Auxiliary #1
KA630 Auxiliary #2
KA630 Auxiliary #3

CPU Code <1:0> can be read by software
via the Boot and Diagnostic Register
(section 10.1).
In the Mayflower system, these signals are
not connected at the FCC Cutout, but are
negated by the KA630 pull-up resistors.
06

GND

07
08
09
11

DSPL
DSPL
DSPL
DSPL

BTRY VCC

GND

13
14

BDG CDO L
BDG CDI L

Ground.
00
01
02
03

L
L
L
L

Display Register Bits 03:00. When asserted,
each of these four output signals lights
a corresponding external LED. DSPL <03:00>
are asserted (low) by power up and by the
negation of DCOK. They are updated by the
boot and diagnostic programs via the Boot
and Diagnostic Register. Writing a "1"
asserts the corresponding signal; writing
a "0" negates it.
Battery Backup Voltage for TOY Clock.
Ground.
Boot and Diagnostic Code <1:0>. This 2-bit
code can be read by software via the Boot
and Diagnostic Register (section 10.1). The
KA630 ROM program may use BDG CD <1:0> to
select various Boot Device or Diagnostic
test parameters at power up and at system
restart. In the Mayflower system, BDG CD
<1:0> is provided by a 3-position switch
on the CK-KA630-A (the manufacturing test
code, "3", can not be selected).

Mnemon·ic

HLT ENB L

Meaning
Halt Enable. This input signal controls
the response to the halt conditions. If
HLT ENB is asserted (low), then the KA630
halts and enters the console program if:
1.
Program executes a Halt instruction
in Kernel Mode
2.
Console detects a break character
3.
Q22-Bus Halt line is asserted (but
only if the KA630 is configured as
an arbiter CPU)
4.
The Interprocessor Communication
Register AUX HLT bit is set (but
only if the K~630 is configured
as an auxiliary CPU)
If HLT ENB is negated, then the Halt line
and break character are ignored and the
ROM program responds to a halt instruction
by restarting or rebooting the system.
If HLT ENB is negated, and if the KA630 is
configured as an auxiliary, the ROM program
responds to assertion of the ICR AUX HLT bit
by rebooting.
HLT ENB can be read by software via the
Boot and Diagnostic Register (section 10.1).
In the Mayflower system, HLT ENB originates
from a switch on the FCC Cutout.

GND

17
18
19

BRS 00 L
BRS 01 L
BRS 02 L

+SV

Note:

Ground.
Baud Rate Select <02:00>. This 3-bit code
selects the console terminal baud rate.
In the Mayflower system, BRS <02:00>
is provided by an 8-position switch on
the FCC Cutout.
Fused +5 Volts

The KA630 module provides 10K pull-up resistors for
the eight input signals (pins 4-5, 13-1S and 17-19).

3.3.3

Console SLU Connector Pinouts

The Console SLU Connector (J3) is a 20-pin connector which
features the following pinouts:
Pin

Meaning

Mnemonic

Reserved. This signal is asserted (+12
volts) whenever the on-board initialize
signal is negated. Use of this signal for
Data Set Ready is not recommended as it
may not be implemented in future designs
(refer to +12 volts, pin 10 below) .

GND

SLU OUT L

04
05

GND
GND

Ground.
Console SLU Output from the KA630 module.
Ground.
Ground.
Key (No Pin) .

06
08

SLU IN +
SLU IN -

GND

Ground.

+12V

Fused +12V. The Mayflower System uses +12V
for the data set ready signal.

3.4

Console SLU Differential Inputs to the
KA630 module. The received serial data
connects to SLU IN -. The signal return
connects to SLU +.

MS630 Module Pinouts

The MS630-AA memory module is a dual height module which mounts
in the CD rows of the next successive slot after either a KA630
module or another MS630 module.
The MS630-BA, MS630-BB and MS630-CA memory modules are quad
height modules, each of which can mount in the next successive
slot after either a KA630 module or another MS630 module.
The MS630 AB row module pinouts connect with +5 volts (pins AA2,
BA2 and BVI) and ground (pins AC2, AJ1, AMI ATl, BC2, BJl, BMI
and BTl) only. The MS630 also connects pin AM2 to pin AN2
(passing BIAK) and pin AR2 to AS2 (passing BDMG). The CD row
module pinouts require the CD-Interconnect to communicate with
the KA630 module and/or another MS630 module.
Note:

The MS630 Modules can not be used in slots for which the
Q22-Bus is connected to both the AB and CD rows (Q22/Q22
configuration). The backplane CD rows must be compatible
with the CD-Interconnect specification.

Appendix A summarizes the module pinouts for the MS630 modules.

+------------------------------------------------------+
Jl

,
!
+-+

Row D

+---+

Row C

Row B

+--+

+---+

Row A

+-+

Front View of the MS630 Connector Location
Figure 3-2
3.5

MS630 Connector Pinouts

The Memory Expansion Connector (Jl) is a 50-pin connector which
features the following control, data and ground signals;
BUFEN 1:0
BDIRT
FE 3:0
MD 31:00
GND

L
L

L
H

pins)
pin)
pins)
(32 pins)
(11 pins)
(2

(1
(4

Refer to the MS630 MicroVAX II Memory Module Specification for
additional details on the memory interconnects.

4.0

Electrical Specifications

4.1

DC Power Consumption

The KA630-A CPU module power requirements are:
+5V +/- 5%

+12V +/- 5%

KA630-AA ( 1MB, FP)

6.2

0.14

KA630-AB (1MB, no FP)

5.9

0.14

KA630-AC (256KB, FP)

TBD

0.14

KA630-AD (256KB, no FP)

TBD

0.14

Note:

Amps maximum

Typical currents are 10% less than the specified
maximum.

The MS630-A/B module power requirements are determined for
the refresh-only, (non-read/non-write) condition. Reading or
writing memory on one of these modules significantly increases
the required power, but results in a corresponding decrease in
the power required by the memory on the CPU module. For memory
module power requirements under full operating conditions,
refer to the MS630 Memory Module Specification.
The MS630-A/B module power requirements under refresh-only
conditions are:
+5V +/- 5%
MS630-AA (1MB)

1.0

MS630-BA (2MB)

1.3

KA630-BB (4MB)

1.8

KA630-CA (8MB)

TBD

4.2

Amps maximum

Bus Loads

The KA630-A CPU Bus Loads are:
2.7
1.0

AC Loads
DC Loads

The MS630 modules do not place any DC or AC loads on the Q-Bus.

4.3

DeOK Signal

The KA630 receives the BDeOK signal from the Q22-Bus and uses it
to initialize the MicroVAX Chip and all clearable'KA630 registers.
The KA630 will perform a system reboot if DeOK is negated (for
100 nsec or longer) and then reasserted.
Note:

The arbiter KA630 asserts BINIT L 200 nsec maximum
after the negation of BDCOK and maintains BINIT L
assertion until 2 msec min after assertion of BDCOK.

4.4

POK Signal

The KA630 receives the BPOK signal from the Q22-Bus and uses it
for Power Up/Power Down sequencing. During Power Up, the KA630
control logic suspends instruction execution by asserting the
MicroVAX chip DMR input. After POK has been asserted, this DMR
input is negated and the MicroVAX chip begins execution of the
KA630 console program. When POK is negated, the KA630 traps
through the Power Down vector location.
4.5

Battery Backup Specifications

When De power is supplied to the KA630 module, it charges the
external batteries from +5 volts through a 220 ohm resistor.
When DC power is removed from the KA630 module, it drains the
external batteries at a rate of 200 uamps maximum (50 uamps
measured typical) .
Note:

These batteries supply power to the KA630 Time of Year
Clock only. There are no battery backup hooks for the
memory system.

5.0

Environmental and MTBF Specifications

5.1

Storage Conditions

The KA630 module has an ambient storage temperature range of
-40'C (-40'F) to +65'C (149'F). Storage relative humidity is
10% to 90%, non-condensing, altitudes to 9.1 km (50,000 ft).
5.2

Operating Conditions

The K~630 module meets or exceeds the requirements for operation
within a system placed in a DEC Standard 102 Class B Environment.
The operating temperature for a KA630 module mounted in a box
within a cabinet is SIC (41'F) to 50 f C (122'F) ambient at the
module. The maximum outlet temperature rise allowed is 5'C (9'F)
above 40'C (104'F). Derate maximum temperature by l'C for each
1000 meters (IfF for each 1000 ft) of altitude. Operating
relative humidity is 10% to 90%, non-condensing.
The airflow required to meet these specifications is 250 lfm.
Note:

The module will operate with a 150 Ifm airflow if the
maximum temperature is restricted to 40'C (104'F).

Note:

When the next revision of MicroVAX chip is available,
the maximum operating temperature should be increased
to allow for a class C operating environment.

5.3

Mean Time Before Failure -- MTBF (Estimate)

The estimated hard error rates for the KA630 and MS630 modules
are as follows:
Class B
Environment
KA630-AA
KA630-AB
KA630-AC
KA630-AD

25.0
25.0
25.0
25.0

MS630-AA
MS630-BA
MS630-BB

93.0
59.0
39.0

khrs.

Class C
Environment
18.5
18.5
18.5
18.5
66.0
42.0
27.0

khrs.

Calculations of the soft error rates are based on the following
assumptions:
1.

Although all 256KB RAM chips are currently spec'ed to have
an active soft error rate of 10 errors per chip per million
hours, certain RAM's (sold by NEC, Fujitsu and Toshiba)
have demonstrated a soft error rate of less than 3 errors
per chip per million hours when the chips are continuously
accessed. Memory Engineering is negotiating with these
vendors to bring their specified soft error rate in line
with test data.

Based on an understanding of how alpha particles cause
soft error rates, it can be stated that, for a RAM chip
which is not being accessed, the probability of a soft
error is reduced by a factor of 3.

During normal system operation, a substantial number of
soft errors will never be detected because the location
in which they occur will be overwritten before being read.

Based on assumptions one and two above, the soft error rate for
MicroVAX II systems is specified at 108 soft errors (3 errors
times 36 RAM chips) per million hours for the first megabyte of
memory and 36 soft errors per million hours for each additional
megabyte of memory. Assumption three provides assurance that the
observed soft error rate will be less that the specified rate,
even if the per chip soft error rates are somewhat greater than
assumed above.
The estimated soft error rates for the KA630 and MS630 modules
are as follows:
Memory
Size

Soft Error
MTBF

Memory
Size

Soft Error
MTBF

1MB
2 MB
3 ME
4 ME

9,259
6,944
5,556
4,630
3,968

6MB
7 MB
8 MB
9 ME

3,472
3,086
2,778
2,525

5MB
Note:

hours

The soft error rate for a single KA630-AC or KA630-AD
CPU module (256KB memory) is 27,778 hours. If combined
with one or more MS630 modules, round the total memory
size up to the next full megabyte and use the table
given above.

For a 9 ME system, running 3 shift operation (24 hours a day)
for 7 days each week, the specified soft error rate is one
error every 15 weeks.

6.0

Central Processor

This section provides summary information about the MicroVAX
CPU chip and the MicroVAX architecture. It is not intended as
a complete reference, but rather to give an overview of the
user-visible features.
For a complete description, consult
the "MicroVAX CPU Chip Engineering Specification" and the
"MicroVAX Architecture Reference Manual".
6.1

MicroVAX CPU Chip Description

The Central Processor and Memory Management functionality is
contained within the 68-pin MicroVAX CPU chip. This MicroVAX
chip is a 32-bit virtual memory microprocessor, implemented
in ZMOS (double metal NMOS). Its key features are:
1.

Subset VAX data types. The MicroVAX CPU chip supports
the following subset of the VAX data types: byte, word,
longword, quadword, character string, and variable
length bit field. Support for f floating, d floating,
and g floating is available via an external floating
point-unit. Support for the remaining VAX data types
can be provided via macrocode emulation.

Subset VAX instruction set. The MicroVAX CPU chip
implements the following subset of the VAX instruction
set: integer and logical, address, variable length bit
field, control, procedure call, miscellaneous, queue,
MOVC3/MOVC5, and operating system support. Floating
point is implemented via an optional external floating
point unit. The remaining VAX instructions can be
implemented via macrocode emulation (the MicroVAX
chip provides microcode assists for the emulation
of the character string, decimal string, EDITPC and
CRC instructions).
Note:

If there is no optional floating point unit,
the floating point instructions may also be
emulated via macrocode emulation.

Full VAX memory management. The MicroVAX CPU chip
includes a demand paged memory management unit which
is fully compatible with VAX memory management. System
space addresses are virtually mapped through single
level page tables, process space addresses through
double level page tables.

Industry standard external interface. The MicroVAX CPU
chip's external interface is a 32-bit extension of the
industry standard microprocessor interface. The MicroVAX
CPU chip can be easily interfaced to industry peripheral
chips from Motorola, National, and other vendors.

Large virtual and physical address space. The MicroVAX
CPU chip supports four gigabytes (2**32) of virtual
memory, and one gigabyte (2**30) of physical memory.

High performance. At its maximum frequencYI the MicroVAX
CPU chip achieves a 200 nsec microcycle and a 400 nsec
Ilo (memory) cycle.

Single package. The MicroVAX CPU chip is packaged in a
standard 68-pin surface mounted chip carrier and requires
no special clock generator or support chips.

6.2

Processor State

The processor state consists of that portion of a process's state
which is stored in processor registers rather than in memory. This
section describes the general purpose register set, the Processor
Status Longword and the Processor Registers which are accessed
via the Move To Processor Register (MTPR) and Move From Processor
Register (MFPR) instructions.
Non-privileged software can access the general purpose register
set and bits 15:00 of the Processor Status Longword (i.e. the
Processor Status Word). The Processor Registers and bits 31:16
of the Processor Status Longword can only be accessed by
privileged software.
6.2.1

General Purpose Registers

There are 16 general purpose registers denoted Rn where n is in
the range 0 through 15. The bits of a register are numbered from
the Fight 0 through 31:
3

o
+---------------------------------------------------------------+
1

+---------------------------------------------------------------+
Certain of these registers have been assigned special meaning by
the VAX-II architecture:
1.

R15 is the program counter (PC). The PC contains the
address of the next instruction byte of the program.

R14 is the stack pointer (SP). The SP contains the
address of the top of the processor defined stack.

R13 is the current frame pointer (FP). The VAX-II
procedure call convention builds a data structure on
the stack called a stack frame. The FP contains the
address of the base of this data structure.

R12 is the argument pointer (AP). The VAX-II procedure
call convention uses a data structure termed an argument
list. The AP contains the address of the base of this
data structure.

6.2.2

Processor Status Longword

The Processor Status Longword is implemented per the MicroVAX
Architectural Reference Manual which may be referenced for
further information on these bits.

3 3 2 2 2 2 2 222 2 2
1 0 987 654 3 2 1 0

1 1

8 7 654 3 2 1

6 5

+-+-+---+-+-+---+---+-+---------+---------------+-+-+- +-+-+-+-+-+

I I I
I CIT!

IFI I
I
IMI!
I P ! I I CUR I PRV! B I
I

IMIPIMBZIDISIMODIMODIZI

IPL

I I I I I I I I I
I D! F I I I I I I I I
MBZ

lVIUIVITINIZIVICj

+-+-+---+-+-+---+---+-+---------+---------------+-+-+- +-+-+-+-+-+

Bit(s)

Mnemonic

Meaning
Compatibility Mode. This bit always reads as
zero, loading a "1" into this bit causes a
reserved operand trap.
Note:

29:28

The Compatibility Mode Instructions can
be emulated by macrocode. Since the
emulation software runs in native mode,
the CM bit is never actually set.

Trace Pending.
Must be zero.

FPD

First Part Done.

Interrupt Stack.

25:24

CUR

Current Mode.

23:22

PRV

Previous Mode.

21
20:16

Must be zero.
IPL

Interrupt Priority Level.

Bit(s)

Mnemonic

15:08

Meaning
Must be zero.

Decimal Overflow Trap Enable. This read/write
bit has no effect on MicroVAX hardware; it
can be used by macrocode which emulates
VAX decimal instructions.

Floating Underflow Fault Enable.

Integer Overflow Trap Enable.

Trace Trap Enable.

Negative Condition Code.

Zero Condition Code.

Overflow Condition Code.

Carry Condition Code.

6.2.3

Processor Registers

The Processor Registers can be accessed through the MFPR and
MTPR privileged instructions.
6.2.3.1

Processor Register Summary

Each of the Processor Registers listed in the table below falls
into one of the following categories:
1

implemented by MicroVAX Chip as specified in
Mi croVAX SRM
implemented external to the MicroVAX, by the
KA630 logic
read as zero, nop on write
implemented by MicroVAX Chip uniquely
access not allowed; results in reserved operand fault

An fiR" following the category number indicates that the register
is cleared by power up and by the negation of DCOK.

- - - . - - - - - - - - - - .- -....•-- ---.---.....-.--.--..--- -------.-.--..---.-.
..

Number

Mneumonic

Type

Category

Kernel Stack Pointer
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer
reserved
reserved
reserved

KSP
ESP
SSP
USP
ISP

r/w
r/w
r/w
r/w
r/w

1
1
1
1
1

PO Base Register
PO Length Register
PI Base Register
PI Length Register
System Base Register
System Length Register
reserved
reserved

POBR
POLR
PIBR
PILR
SBR
SLR

Process Control Block Base
System Control Block Base
Interrupt Priority Level
AST Level
Software Interrupt Request
Software Interrupt Summary
Interprocessor Interrupt
CMI Error Register

PCBB
SCBB
IPL
ASTLVL
SIRR
SISR
IPIR
CMIERR

Interval Clock Control/Status
Next Interval Count
Interval Count
Time Of Year
Console Storage Receiver Status
Console Storage Receiver Data
Console Storage Transmit Status
Console Storage Transmit Data

ICCS
NICR
ICR
TODR
CSRS
CSRD
CSTS
CSTD

Console Receiver cis
Console Receiver D/B
Console Transmit cis
Console Transmit D/B
Translation Buffer Disable
Cache Disable
Machine Check Error Summary
Cache Error

RXCS
RXDB
TXCS
TXDB
TBDR
CADR
MCESR
CAER

r/w
w
r/w
r/w
r/w
r/w

40
41
42
43
44
45
46
47

Accelerator Control/Status
Console Saved ISP
Console Saved PC
Console Saved PSL
NCS Address
NCS Data
reserved
reserved

ACCS
SAVISP
SAVPC
SAVPSL
WCSA
WCSB

r/w
r/w
r/w
r/w
r/w
r/w

o
1

2
3

4
5
6
7
8
9

10
11

12
13
14
15

16
17
18
19
20
21

22
23
24
25
26

27
28
29

30
31
32
33
34

35
36
37
38

5
5
5

r/w
r/w
r/w
r/w
r/w
r/w

1
1
1
1
1
1

5
5

r/w
r/w
r/w
r/w

1
1

r/w
r/w
r/w

5
5

lR
lR
lR

r/w

3
3
3
3
3
3
3

r/w
r/w
r

r/w
w

r/w
r

2R
2R
2R
2R
3
3
3
3

5
4
4
4

5
5
5
5

Number

-----

-------------

Mneumonic

---------

Type

Category
3
3
3
3
3
3
3
2

--------

48
49
50
51
52
53 .
54
55

SBl Fault/Status
SBl Silo
SBI Silo Comparator
SBl Maintenance
SBl Error Register
SBI Timeout Address Register
SBl Quadword Clear
10 Bus Reset

SBlFS
SBlS
SBlSC
SBlMT
SBIER
SBITA
SBIQC
IORESET

r/w
r
r/w
r/w
r/w
r
w
w

56
57
58
59
60
61
62
63

Memory Management Enable
TB Invalidate All
TB Invalidate Single
TB Data
Microprogram Break
Performance Monitor Enable
System Identification
Translation Buffer Check

MAP EN
TBIA
TBIS
TBDATA
MBRK
PMR
SID
TBCHK

r/w
w
w
r/w
r/w
r/w
r
w

64:127

reserved

6.2.3.2

lR
1·
1

3
3
3
1
1

Category One Processor Registers

Processor registers which are implemented as specified by the
MicroVAX or VAX Architecture Reference Manual are classified
as category one processor registers. Section 6.2.3.1 lists all
category one registers implemented by the MicroVAX chip.
The following category one registers are also referenced in
other sections of this specification:
Number
8

9
10
11
12
13
17
18
20
21
56
57
58
62

Register Name
PO Base Register
PO Length Register
PI Base Register
PI Length Register
System Base Register
System Length Register
System Control Block Base
Interrupt Priority Level
Software Interrupt Request
Software Interrupt Summary
Memory Management Enable
TB Invalidate All
TB Invalidate Single
System Identification

Mnemonic

Section

POBR
POLR
PIBR
PILR
SBR
SLR
SCBB
IPL
SIRR
SISR
MAP EN
TBIA
TBIS
SID

7 .4.1
7.4.1
7 . 4 •2
7.4.2

7.3
7.3
6.4.5
6.4.1
6.4.1
6.4.1
7.2
7.2
7.2
6.7

6.2.3.3

Category Two Processor Registers

Those KA630 processor registers which are implemented external
to the MicroVAX chip are classified as category two processor
registers. Refer to the following sections for a description of
these registers:
Number

Mnemonic

Section

32
33
34
35
55

Console Receiver Cis
Console Receiver D/B
Console Transmit CIS
Console Transmit D/B
10 Bus Reset

RXCS
RXDB
TXCS
TXDB
IORESET

13.2.1
13.2.2
13.2.3
13.2.4
14.1

-----

6.2.3.4

-------------

--------

-------

Category Four Processor Registers

Processor registers which are implemented within the MicroVAX
chip and which are unique to the MicroVAX chip (i.e. they are
not contained in the MicroVAX or VAX Architecture Reference
Manual). Refer to the following sections for a description of
these registers:
Number

----24
41
42
43

-------------

Interval Clock Control/Status
Console Saved ISP
Console Saved PC
Console Saved PSL

Mnemonic

Section

ICCS
SAV1SP
SAVPC
SAVPSL

12.1
6.4.4
6.4.4
6.4.4

--------

-------

6.3

Instruction Set

The MicroVAX Chip implements all instructions in the following
VAX instruction groups:
1.
2.
3.
4.
5.
6.
7.

Integer arithmetic and logical
Address
Variable length bit field
Control
Procedure call
Miscellaneous
Queue
Character string moves (MOVC3 and MOVCS)

The following instruction groups are implemented by the optional
MicroVAX floating Point Chip (if the optional chip is not present,
then they may be emulated in software):

1.
2.
3.

F floating
G-floating
D=floating

The MicroVAX chip provides special microcode hooks to aid the
emulation of the following instruction groups by macrocode:

1.
2.
3.
4.

Character string (except MOVC3 and MOVCS)
Decimal string
CRC
Edit

The following instruction groups are not implemented, but may
be emulated by macrocode:
1.
2.
3.

H floating
Octaword
Compatibility Mode Instructions

Appendix F lists the entire VP~ instruction set, indicating
which instructions are implemented in the optional floating
point hardware, which instructions are emulated and which
instructions are not implemented.
6.4

Exceptions And Interrupts

Both exceptions and interrupts divert execution from the normal
flow of control. An exception is typically handled by the
current process (e.g. an arithmetic overflow) while an interrupt
is typically transfers control outside the process (e.g. an
interrupt from an external hardware device).

6.4.1

Interrupts

The MicroVAX architecture has 31 interrupt levels which are used
as follows:
Interrupt
Levels
non-maskable
IF
IE
19 - ID
18
17
16
15
14
10 - 13
01 - OF

Interrupt
Condition
HALT L asserted
unused
PWRFL L asserted
unused
unused
BR7 L asserted
Interval Timer Interrupt, BR6 L asserted
BR5 L asserted
Console Terminal Interrupts, Interprocessor
Doorbell Interrupts, BR4 L asserted
unused
software interrupt request

Note:

Because the Q22-Bus
the four bus grants
level 4 bus grant),
after responding to
is set = 14 after a
doorbell interrupt,
timer interrupt.

does not allow differentiation between
levels (i.e a BR7 device could grab a
the KA630 CPU must set the IPL = 17
any interrupt request BR7-4. The IPL
console terminal or interprocessor
and it is set = 16 after an interval

Note:

When the KA630 is configured as an auxiliary CPU it ignores
Q22-Bus BR7-4 interrupt requests, but does respond to IPL 14
requests from its own console serial line unit and from its
interprocessor doorbell (in that order of priority). It also
responds to interrupt requests from its own interval timer.

The interrupt system is controlled by the Interrupt Priority Level
Register (IPL, corresponds to PSL<20:16», the Software Interrupt
Request Register (SIRR), and the Software Interrupt Summary
Register (SISR).
3

1
5 4
o
+-------------------------------------------------+----------+
I
ignored, returns 0
IPSL<20:16>! :IPL
+-------------------------------------------------+----------+

3
1

4 3

+----------------------------------------------------+-------+
!
ignored
I request I :SIRR
+----------------------------------------------------+-------+

3 1 1
1 6 5

+----------------------------+-----------------------------+-+
I
I
!

I Pending Software Interrupts !MI
I
I B I : S I .'3?
IF E DeB A 9 8 7 6 5 432 llZI

+----------------------------+-----------------------------+-+
6.4.2

Exceptions

The MicroVAX architecture recognizes six classes of exceptions.
exception class

instances

arithmetic traps/faults

integer overflow trap
integer divide by zero trap
subscript range trap
floating overflow fault
floating divide by zero fault
floating underflow fault

memory management exceptions

access control violation fault
translation not valid fault

operand reference exceptions

reserved addressing mode fault
reserved operand fault or abor~

instruction execution exceptions

reserved/privileged instr. faul~
emulated instruction faults
extended function fault
breakpoint fault

tracing exception

trace trap

system failure exceptions

memory read error abort
memory write error abort
kernel stack not valid abort
interrupt stack not valid abort
machine· check abort

----_._.----.-------

6.4.3

Machine Check Parameters

In response to a machine check, the following parameters are
pushed on the stack:

+----------------------------------------------------- --+
I

byte count (OOOOOOOC hex)

machine check code

PSL

+----------------------------------------------------- --+

:SP

+----------------------------------------------------- --+
I
most recent virtual address
I
+----------------------------------------------------- --+
I
internal state information
I
+----------------------------------------------------- --+
!
PC
I
+----------------------------------------------------- --+
+----------------------------------------------------- --+
The parameters are:
machine check code (hex):
1
2
3
4

=
=
=
=
=

5
6
7

=
=
=
=
=

8
9
80
81
82
83

=
=

impossible microcode state (FSD)
impossible microcode state (SSD)
undefineQ FPU error code 0
undefined FPU error code 7
undefined memory management status (TB miss)
undefined memory management status (M = 0)
process PTE address in PO space
process PTE address in P1 space
undefined interrupt ID code
read bus error, VAP is virtual address
read bus error, VAP is physical address
write bus error, VAP is virtual address
write bus error, VAP is physical address

most recent virtual address:
<31:0>

current contents of VAP register

internal state information:
<28:24> =
<23:20> =
<19:16> =
<14>
<7:0>

current contents of ATDL register
current contents of STATE<3:0>
current contents of ALU cond codes
current contents of VAX restart bit
PC increment at the time of the exception
(reported as zero if FPD set in saved PSL)

PC:

<31:0>

PC at the start of the current instructions

PSL:

<31:0>

current contents of PSL

6.4.4

Halt Conditions

If the hardware or kernel software environment becomes severely
corrupted, the chip may be unable to continue normal processing.
In these instances, the chip passes control to recovery code
beginning at physical address 20040000 (hex). The previous state
of the machine is stored in temporary registers which may be
read as Processor Registers via the MFPR instruction:
1.

IPR 42 contains the saved PC
IPR 43 contains the saved PSL, the saved
Map En bit and the error code
IPR console.psl bits<31:16,07:00> contain the
a.
saved PSL
IPR console.psl bit<15> contains the saved Map En bi~
b.
IPR console.psl bits<14:08> contain the error code
c.
IPR 41 contains the previous interrupt stack pointer
Note:

There are severe restrictions on the usage of
these saved values (e.g. they must be accessed
before executing certain instructions which use
the registers for temporary storage).

The halt process sets the state of the chip as follows:
PSL
PC
MAP EN
ASTLVL
SISR

=
=
=
=

041FOOOO (hex)
20040000 (hex)
0
Unchanged
(set to 4 by power up)
Unchanged
(cleared by power up)

The error codes indicating the reason for the halt are as follows:
Error Code
2
3
4

5
6
7
8
A

10
11

condition
assertion of external halt
initial power on
interrupt stack not valid during exception
machine check during machine check
or kernel stack not valid exception
HALT instruction executed in kernel mode
SCB vector bits<1:0> = 11
SCB vector bits<1:0> = 10
CHMx executed while on interrupt stack
ACV or TNV during machine check exception
ACV or TNV during kernel stack not valid exception

6.4.5

System Control Block (SCB)

The System Control Block (SCB) consists of two pages which contain
the vectors for servicing interrupts and exceptions. The SCB is
pointed to by the System Control Block Base Register (SCBB).
332
109

9 8

+---+---------------------------------------+-----------------+
IMBZI
physical longword address of PCB
I
MBZ
I :SCB3
+---+---------------------------------------------------------+
The System Control Block format:
vector

name

unused

machine check

type

#param

abort

notes

refer to section
6.4.3.

kernel stack not valid

abort

serviced on interrup~
stack, IPL is raised
to IF

power fail

interrupt

IPL is raised to IE

fault

reserved/privileged
instruction
extended instruction

fault

reserved operand

fault!
abort

a
a

reserved addressing
mode

fault

aceess control
violation

fault

parameters are virtual
address, status code

translation not valid

fault

parameters are virtual
address, status code

trace pending (TP)

fault

breakpoint instruction

fault

unused

arithmetic

XFC instruction
not always recoverable

compatibility mode
in VAX
trap/
fault

parameter is type code

type

#param

CHMK

trap

CHME

trap

CHMS

trap

parameter is operand
word

CHMU

trap

parameter is operand
word

50-5C

unused

60-80

unused

vector

name

38-3C

unused

notes

parameter is operand
word
parameter is opera~d
word

software level 1

interrupt

software level 2

interrupt

ordinarily used for
AST delivery

software level 3

interrupt

ordinarily used for
process scheduling

software levels 4-15

interrupt

interval timer

interrupt

IPL is 16 (INTTIM L)

unused

emulation start

fault

same mode exception,
FPD = 0: parameters ar~
opcode, PC, specifiers

emulation continue

fault

same mode exception,
FPD = 1: no parameters

90-BC

DO-F4

unused

Console Receive

interrupt

IPL is 14

Console Transmit

interrupt

IPL is 14

100-lFC adapter vectors

interrupt

Not implemented by
the KA630

200-3FC device vectors

interrupt

Correspond to Q22-3us
Vectors OOO-lFC;
KA630 appends the
assertion of bit <09>

6.4.5.1

KA630 Assigned Device Vector

The KA630 uses System Control Block (SCB) device vector 204
for the interprocessor doorbell interrupt (section 14.3.2).
6.5

(hex)

Hardware Detected Errors

The KA630 detects certain error conditions during program
execution. These conditions, and the resultant actions, are
described below.
6.5.1

Non-Existent Memory Errors

If the MicroVAX chip attempts a read or write access to a
non-existent location in local memory or I/O Space, the
KA630 asserts the error (ERR) signal to the chip.
If the MicroV&X chip attempts a read or write access to the
Q22-Bus, a bus timeout error can occur. If BRPLY L is not
asserted within 10 microseconds following the assertion of
BDIN L or BDOUT L, the KA630 asserts the ERR signal to the chip.
If ERR is asserted, the MicroVAX processor responds as follows:
1.

For write accesses and for non-pre fetch reads, the
MicroVAX processor recognizes a machine check and
traps through vector 04.

For pre fetch operations, the MicroVAX processor aborts
the prefetch cycle and performs a non-prefetch read if
an instruction fetch is required from that location.

6.5.2

Parity Error Detection

Parity errors can be detected during read operations from the
local memory address space, from the Q22-Bus memory address
space or from the Q22-Bus I/O Page address space.
Memory System Error Register bit <00> (section 9.4.1) enables
parity error detection for all reads from local memory, whether
it is accessed through local memory address space or through
the Q22-Bus memory address space (via the Q22-Bus Map). MSER
<00> has no effect on parity error detection for reads from
external Q22-Bus memory or devices.
During read operations from the local memory address space, parity
is checked only for those bytes designated by the MicroVAX chip
Byte Mask signals, BM <3:0>. Because the MicroVAX chip must receive
a stable signal on ERR at least 150 nsec before it requires stable
data, performance considerations dictate that any parity error

which occurs during reads from local memory address space will not
cause an ERR assertion duri~gthe cycle for which the parity error
was detected. Instead, the KA630 asserts ERR for the next cycle and,
if that cycle was a pre-fetch read cycle, for the cycle after that
as well.
.
Note:

When a parity error occurs during a local memory access
via local memory address space, the MicroVAX is allowed
to complete that cycle and may execute an instruction
which alters the MicroVAX chip's internal state. However,
the MicroVAX recognizes a machine check and traps through
vector 04 when it attempts the next external cycle.
/Justification for this incompatibility with past VAX-II
processors rests on two considerations: 1) a performance
improvement of 10-15% over a design which would stall all
read cycles to allow parity detection within the cycle
and 2) an estimated local memory parity error rate of
from once every six months (KA630 with two MS630-BB
modules, each containing 4MB of 256K RAM; three shift
operation) to once every ten years (KJI.630with no
memory expansion modules; single shift operation)./

During read operations from Q22-Bus space (including the access of
local memory through the Q22-Bus Map), a parity error is detected
if both BDAL <17> and BDAL <16> are asserted. When a parity error
is detected, the KA630 asserts ERR to the MicroVAX chip.
Note:

When the processor reads local memory via the Q22-Bus
memory space, parity is checked on both bytes of each
word accessed, even if the processor only requested a
single byte.

If ERR is asserted, the MicroVAX processor responds as follows:
1.

For non-prefetch reads, the MicroVAX processor recognizes
a machine check and traps through vector 04.

For pre fetch operations, the MicroVAX processor aborts
the pre fetch cycle and performs a non-pre fetch read if
an instruction fetch is required from that location.

6.5.3

Interrupt Vector Timeouts

An interrupt vector timeout occurs when BRPLY L is not asserted
within 10 microseconds after an interrupt is acknowledged
(BIAK L). The KA630 asserts the Error (ERR) signal to its
MicroVAX chip. The processor aborts the interrupt cycle and
continues as if the interrupt request had never occurred.

6.5.4

"No Sack" Timeouts

A "No Sack" timeout occurs when BSACK t is not asserted within
10 microseconds after a DMA is granted (BDMG L). The timeout
is ignored.
The KA630 continues as if the DMA request had
never occurred.
6.6

Latency Specifications

6.6.1

Interrupt Latency (Estimates)

Interrupt
interrupt
(BIAK L).
following

latency is defined as the time between receiving an
request (BIRQ L) and acknowledging the request
The interrupt latency can be divided into the
components:

The length of time the processor runs at an interrupt
priority level which masks out the interrupt. This
time period is highly software dependent.

The length of time the processor takes to execute the
last instruction before the interrupt. For instructions
which do not access the Q-Bus, this time period is as
follows:
a.
b.

Longest Non-Preemptable Instruction
Preempting an Instruction

2.4 usee
5.4 usee

Each Q-Bus access would add approximately 1.0 usec for
word accesses and 1.5 usee for longword accesses. A bus
timeout, which could occur on the last Q-Bus access,
would add an additional 10-15 usec.
3.

Note:

The length of time it takes the KA630 to gain Q22-Bus
mastership. Because the arbiter KA630 is the highest
priority DMA device, this period is equal to the time
required for the previous bus master to finish its
data transfer(s) and relinquish the bus. Eight block
mode transfers would typically require about 5 usec
(as currently planned, the KA630 will assert DMR when
it needs the bus, limiting a block mode device to no
more than eight additional transfers). A non-existent
memory timeout would typically require 10-15 usec.
This represents a change from the traditional priority
structure where DMA devices have a higher priority than
either CPU fetches or interrupts. The justifications
for this change are:
1.
2.
3.

The KA630 CPU usually runs out of local memory,
greatly reducing bus utilization by the CPU.
Modern DMA devices are buffered and better able
to withstand the increase in DMA latency.
The result is a significant improvement in
interrupt latency which has degraded with the
increased use of buffered DMA devices.

6.6.2

Interrupt Service Time

Interrupt service time is defined as the time between
acknowledging the interrupt and fetching the first instruction
of the service routine.
The KA630 service time is 4.4 usec.
6.6.3

DMA Latency

DMA latency is defined as the time between receiving a DMA
Request (BDMR L) and granting the request (BDMG L).
This
calculation has traditionally been made assuming that the
DMA request occurs while the CPU has control of the bus and
that there are no conflicting DMA requests. The result of
this calculation is, therefore, the CPU induced latency. The
DMA latency seen by any device is a combination of the CPU
induced latency and the latency induced by other DMA devices.

The CPU induced DMA latency is the time required to complete
the longest CPU operation which retains control of the bus.
The longest KA630 operation which retains control of the bus
is a 32-bit read-lock/write-unlock to non-block-mode memory.
Typical CPU induced DMA latencies for the KA630 can be
summarized as follows:
Cycle
32-bit read-lock/write (non-block-mode)
32-bit read-lock/write (block-mode)
32-bit read (non-block-mode)
32-bit read (block-mode)
32-bit write (non-block-mode)
32-bit write (block-mode)
16-bit read-lock/write
16-bit read
16-bit write
Note:

Latency
4.2 usec
3.2
2.0
1.5
2.0
1.5
2.2
1.0
1.0

Two successive byte writes, a word write followed by a
byte write and a byte write followed by a word write
are subsets of the 32-bit write (non-block-mode). A
single byte write is a subset of the 16-bit write.

When a CPU which is the lowest priority device has relinquished
control of the bus, it does not regain control of the bus until
all DMA requests have been honored. Thus, two high bandwidth
devices could exchange control of the bus, effectively locking
out the CPU until one of them has completed its set of transfers.
The arbiter KA630 CPU is the highest priority bus device in a
system. After it has relinquished control of the bus, it can
regain control of the bus during the next bus arbitration.
Note:

System level DMA latency calculations must take into
account the fact that the arbiter KA630 can request the
bus as the highest priority bus device.

6.7

System Identification

As noted in section 6.2.3, the read-only System Identification
Register, Processor Register 62, is implemented by the MicroVAX
chip. On the KA630-A, and on all other processors which use the
MicroVAX chip, the System Identification Register always reads
as "0000 0008".
The KA630-A, as must all processors which use the MicroVAX chip,
implements a 32-bit System Identification Extension Register at
physical location 2004 0004. This 32-bit register exists within
the KA630-A console program ROM (section 10.2).
2 2
4 3

3
1

1 1

6 5

+----------------------------------------------------------------+
!
SYSCODE
!
VERSION!
reserved
!
+----------------------------------------------------------------+
Bits

Mnemonic

31:24

SYSCODE

System Code. This field reads as "1" for
the KA630-A.

23:16

VERSION

Version number of console program ROM.

15:00

--~~-----,.-----,-----------

- ._-------_._--------------

Meaning

Reserved.

- ~-------"~------ -._-------

7.2

Memory Management Control Registers

Memory management is controlled by three processor registers:
Memory Management Enable (MAPEN), Translation Buffer Invalidate
Single (TBlS), and Translation Buffer Invalidate ALL (TBlA).
MAPEN contains one bit:
MAPEN<O>

MME enables memory management.

1 0

+---------------------------------------------------------+-+
I
I

MBZ

IMI
I MI : M}~..PE::
lEI

+---------------------------------------------------------+-+

TBIS controls translation buffer invalidation. Writing a virtual
address into TBIS invalidates any entry which maps that virtual
address.
3

+-----------------------------------------------------------+
I

I :TBIS

Virtual Address

+-----------------------------------------------------------+

TBIA also controls translation buffer invalidation. Writing a zero
into TBIA invalidates the entire translation buffer.
3
1

+-----------------------------------------------------------+
I

MBZ

I :TBIA

+-----------------------------------------------------------+
7.3

System Space Address Translation

A virtual address with bits <31:30> = 2 is an address in the system
virtual address space.
System virtual address space is mapped by the System Page Table
(SPT), which is defined by the System Base Register (SBR) and the
System Length Register (SLR). The SBR contains the physical address
of the System Page Table. The SLR contains the size of the SPT in
longwords, that is, the number of Page Table Entries. The Page
Table Entry addressed by the System Base Register maps the first
page of system virtual address space, that is, virtual byte
address 80000000 (hex).

332
109

210

+---+-------------------------------------------------------+---+
I MBZ I

I MBZ I : S3:,

physical longword address of SPT

+---+-------------------------------------------------------+---+
3

2 2
2 1

+-------------------+-------------------------------------------+
I

MBZ

length of SPT in longwords

+-------------------+-------------------------------------------+
332
109

9 8
o
+---+--------------------+--------+

SVA:
(System Virtual
Address)
3
1

! 2 I

I
212
312

I
I

extract and
check length

2110

+--------+--------------------+--+
I

byte

+---+--------------------+--------+

I 0I

+--------+--------------------+--+

I
I
I
I
!
I
1

add
SBR:

+-----------------------------+--+
I

! 01

Physical Base Adr of SPT

+-----------------------------+--+
yields

+-----------------------------+--+
I

I 01

Physical Adr of PTE

+-----------------------------+--+
fetch

PTE:

3 3
1 0

2 2
1 0

III

+-+--------+--------------------+
PFN

+-+--------+--------------------+

check access I this access check
I in current mode
I
Physical Address
of Data:

I
!
I
I
I
I
I
I
I
1

!
I
I
I
I
I
I
I
I
I
!
I
I
V 0

I
I
!
I

918

I !

+--------------------+--------+
+--------------------+--------+

System Virtual to Physical Translation

7.4

Process Space Address Translation

A virtual address with bit <31> = 0 is an address in the
process virtual address space. Process space is divided into
two equal sized, separately mapped regions. If virtual address
bit <30> = 0, the address is in region PO. If virtual address
bit <30> = 1, the address is in region Pl.
7.4.1

PO Region Address Translation

The PO region of the address space is mapped by the PO Page
Table (POPT), which is defined by the PO Base Register (POBR)
and the PO Length Register (POLR). The POBR contains the
system virtual address of the PO Page Table. The POLR contains
the size of the POPT in longwords, that is, the number of Page
Table Entries. The Page Table Entry addressed by the PO Base
Register maps the first page of the PO region of the virtual
address space, that is, virtual byte address O.
332
109

210

+---+----------------------------------------------------+---+
I 2 I

system virtual longword address of POPT

IMBZI

+---+----------------------------------------------------+---+
2 2
2 1

3
1

+----------------+-------------------------------------------+
I

MBZ

:POBR

length of POPT in longwords

+----------------+-------------------------------------------+

:POLR

332
109

PVA:
(Process Virtual
Address)

9 8
o
+---+--------------------+--------+
1 0 I
1
byte
1
+---+--------------------+--------+

I
212
312

3
1

extract and
check length

I
I
2110

+--------+--------------------+--+
I
0
I
! O!
+--------+--------------------+--+
add

+-----------------------------+--+
I Sys Virt Base Adr of POPT I 01
+-----------------------------+--+

POBR:

+-----------------------------+--+
I
Virtual Adr of PTE
I 01
+-----------------------------+--+
fetch by system space
translation algorithm,
including length and
kernel mode access checks

PTE:

2 2
1 0

o
+-+--------+--------------------+
III
I
PFN
!
+-+--------+--------------------+
1

check access

Physical Address
of Data:

1 this access check
I in current mode

I
I
I
I
I
I
I.
I
I

i
I
I

yields

3 3

I
I
I

918

1
1

I
I
I
I
I
I
I
I
!

!
I
!
I
I
!
I
I
V 0

+--------------------+--------+
1
I
I
+--------------------+--------+

PO Virtual to Physical Translation

7.4.2

PI Region Address Translation

The PI region of the address space is mapped by the PI Page
Table (PIPT), which is defined by the PI Base Register (PIBR)
and the PI Length Register (PILR). Because PI space grows
towards smaller addresses, and because a consistent hardware
interpretation of the base and length registers is desirable,
PIBR and PILR describe the portion of PI space that is NOT
accessible. Note that PILR contains the number of non-existent
PTEs. PIBR contains the virtual address of what would be the
PTE for the first page of PI, that is, virtual byte address
40000000 (hex).
The address in PIBR is not necessarily a
valid physical address, but all the addresses of PTEs must
be valid physical addresses.
3

2 I 0

+-------------------------------------------------------+---+
!

virtual longword address of PIPT

IMBZI

+-------------------------------------------------------+---+
2 2
2 1

3
1

+---------------+-------------------------------------------+
I

MBZ

:PIBR

length of PIPT in longwords

I :PILR

+---------------+-------------------------------------------+

332
109

PVA:
(Process Virtual
Address)
3
1

9 8

!
I

I
I
!
I
I
I
I
I
I
I
I
!
!
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
!
!
I
I
I
V 0

+---+--------------------+--------+
I 1 I
I byte I
+---+--------------------+--------+
I

212
312

extract and
check length

2110

+--------+--------------------+--+
o
I
I 0I
+--------+--------------------+--+
add
PIBR:

+-----------------------------+--+
I
Virt Base Adr of PIPT
I 01
+-----------------------------+--+
yields

+-----------------------------+--+
I
Virtual Adr of PTE
I 01
+-----------------------------+--+
fetch by system space
translation algorithm,
including length and
kernel mode access checks
3 3
1 0

PTE:

2 2
1 0

+-+--------+--------------------+
111
I
PFN
I
+-+--------+--------------------+

check access I this access check
I in current mode
I
12
19

Physical Address
of Data:

I
I
I
!

918

+--------------------+--------+
I
!
I
+--------------------+--------+

Pl Virtual to Physical Translation

---- -------------------------------------------_._-_._-------,----

7.5

Page Table Entry

The format of a valid page table entry is:

2 222 2 2 2 2
765 4 3 2 1 0

3 3

1 0

+-+-------+-+-+---+---+---------------------------------------+
IMIOIOWNI 0 I

IVI PROT

PFN

I :PTE

+-+-------+-+-+---+---+---------------------------------------+
where:
V

PROT
M
OWN
PFN

=
=
=
=

Valid Bit
(must be set)
Protection Code
Modify Bit
Owner Bits
Page Frame Number

If Bit <31> (the V bit) is clear, the format of the remaining
bits are not examined by the hardware.

8.0

Floating Point Processor Description

The Floating Point Processor option consists of a 68 pin ZMOS
(double metal NMOS) Floating Point Unit (FPU) chip.
The key features of the FPU chip are as follows:

Subset VAX Data types. The MicroVAX FPU chip supports
byte, word, longword, f floating, d floating and
g floating data types. The h floating data type is not
supported, but may be implemented by macrocode emulation.

Subset VAX Instruction Set. The MicroVAX FPU chip
implements all VAX floating point instructions except
for the h floating instructions and the floating point
instructions which are implemented by the MicroVAX CPU
chip. The h floating data type is not supported, but
may be implemented by macrocode emulation.

--~ ------------~----------------,~-----------------"--------,---------------,

9.0

KA630 Memory System

The KA630 Memory System consists of the KA630 local memory as
well as the Q22-Bus Map which allows Q22-Bus master devices to
access this local memory. The Memory System also includes two
registers which are used primarily for diagnostic purposes.
9.1

Memory System Summary

The KA630 supports up to 16MB of local memory. The KA630 CPU
typically accesses this memory directly, via physical addresses
00000000 - OOFFFFFF (hex). Any Q22-Bus master device, including
the KA630 CPU, can access this memory indirectly through the
Q22-Bus Map. The Q22-Bus Map contains 8192 mapping registers,
each of which can map a page (512 bytes) of Q22-Bus space into
a selected page in local memory. Mapping can be independently
enabled and disabled for each page.
The KA630 CPU Module accesses the Q22-Bus memory address space
via physical addresses 30000000 - 303FFFFF (hex). It accesses
the Q22-Bus I/O space via physical addresses 20000000 - 20001FFF.
9.2

KA630 Local Memory

The KA630-AA and KA630-AB MicroVAX CPU Modules feature 1MB of
on-board memory; the KA630-AC and KA630-AD MicroVAX CPU Modules
feature 256KB on-board memory, The KA630-A module utilizes the
backplane CD Interconnect and a 50-pin connector to communicate
with up to two MS630 memory expansion modules, each of which may
contain 1MB, 2MB, 4MB or 8MB of additional local memory. A KA630
module with two MS630 memory expansion modules can thus have a
maximum of 16MB local memory. All local memory performs byte
parity generation and checking.
Note:

When a KA630 module has 16MB of expansion memory (i.e
two MS630-CA modules), its on-board memory is disabled.

9.3

Mapping Registers

The Q22-Bus Map contains 8192 mapping registers, each of which
can map a page (512 bytes) of Q22-Bus space into a selected page
of local memory.
9.3.1

Mapping Register Format

Each of the mapping registers is a 32 bit long word with the
following format:

3 3
1 0

1 1

5 4

+-+-----------------------------+-----------------------------+
!V!

A23 - A09

+-+-----------------------------------------------------------+

Bit{s)

Mnemonic

Meaning
Valid. When a mapping register is selected by
a Q22-Bus address, the Valid bit determines
whether the Q22-Bus map is enabled for that
address. If the Valid bit is set, the map
is enabled. If the Valid bit is clear, the
map is disabled and the KA630 does not
respond to that address.
Unused. These bits always read as zero.

30:15
14:00

A23-A09

Address bits A23 - A09. When a mapping register
is selected by a Q22-Bus address, and if that
register's Valid bit is set, then these fifteen
bits are used as local memory address bits 23
thru 09. Q22-Bus address bits 08 thru 00 are
used as local memory address bits 08 thru 00.

Note:

Each mapping register is located on a long word boundary
and must be written using long word instructions. Byte
and word instructions will load these registers with
undefined data.

9.3.2

Mapping Register Addresses

(Hex Addresses 2008 XXXX)

The mapping registers are located within the local register space
at physical addresses 2008 8000 - 2008 FFFC. They can only be
accessed from the on-board processor.
The physical address of each register was chosen so that register
address bits <14:02> are identical to Q22-Bus address bits <21:09>
of the page which they map.
Register
Address

Q22-Bus Addresses
Mapped (Hex)

2008
2008
2008
2008

8000
8004
8008
800C

00
00
00
00

0000
0200
0400
0600

00
00
00
00

01FF
03FF
05FF
07FF

00
00
00
00

000
001
002
003

000
000
000
000

00
00
00
00

000
001
002
003

777
777
777
777

2008
2008
2008
2008

8010
8014
8018
80lC

00
00
00
00

0800
OAOO
OCOO
OEOO

00
00
00
00

09FF
OBFF
ODFF
OFFF

00
00
00
00

004
005
006
007

000
000
000
000

00
00
00
00

004
005
006
007

777
777
777
777

Q22-Bus Addresses
Mapped
(Octal)

Q22-Bus Addresses
Mapped
(Hex)

2008
2008
2008
2008

3F F800
3F FAOO
3F FCOO
3F FEOO

FFFO
FFF4
FFF8
FFFC

9.3.3

3F F9FF
3F FBFF
3F FDFF
3F FFFF

Q22-Bus Addresses
Mapped
(Octal)

17
17
17
17

774
775
776
776

000
000
000
000

17
17
17
17

774
775
776
777

777
777
777
777

Q22-Bus Map Operation

At power up time, the Q22-Bus mapping registers, including the
valid bits, are undefined. External access to local memory is
disabled so long as the Interprocessor Communication Register
(ICR) LM EAE bit is cleared.
After completion of the ROM diagnostic programs which are part
of the KA630 console program, an arbiter KA630 enables the
mapping registers to map sufficient local memory space to boot
the system and then sets the LM EAE bit. When the operating
system gains control, it may either invalidate or reassign
various pages as required.
After completion of its ROM diagnostic programs, but before
setting the LM EAE bit,the auxiliary KA630 ROM programs clear
all mapping register valid bits.
The Q22-Bus Map monitors each Q22-Bus cycle and responds if
the following three conditions are met:
1.

The Interprocessor Communication Register LM EAE bit
is set.

The Valid bit of the selected mapping register is set.

During read operations, the mapping register must map
into existent local memory. (During write operations,
the KA630 returns Q22-Bus BRPLY before checking for
existent local memory; the response depends only on
conditions 1 and 2 above).

The translation from Q22-Bus address to local memory physical
address is as follows:
2

9 8

Q22-Bus Address

+------------------------+--------+
I
I byte !
+------------------------+--------+
extract and
use to select
mapping register

I
I
I

I
!
I

Selected Mapping Register:
3 3

1 1

1 0

5 4

+-+----------+-----------------------------+
! V!
!
!-+----------+-----------------------------+
!

!2
!3

9 8

+-----------------------------+--------+
Physical Address of Local Memory

+-----------------------------+-------~+

9.4

Memory System Registers

The three registers associated with the Memory System are located
in the local register I/O address space and can only be accessed
by the on-board processor. Software uses the Memory System Error
Register to monitor parity and non-existent memory errors and
to control parity generation and checking for the local memory.
The CPU Error Address Register contains the address of the page
in local memory which caused a parity error during an access by
the on-board CPU. The DMA Error Address Register contains the
address of the page in local memory which caused a parity error
during an access by an external device.
9.4.1

Memory System Error Register

(Hex Address: 2008 0004)

The Memory System Error Register (MSER) is located in the local
register I/O address space at physical address 2008 0004. It
can only be accessed by the on-board processor.
MSER <07:05> and MSER <03> indicate the status of machine check
traps through System Control Block (SCB) vector 04. MSER bit
<04> is set if an external Q22-Bus device receives a parity
error while reading KA630 local memory.

~~-

~-- --~-~-.~~----------------.-~---

----------------.-------------

When CPU read operation parity error sets MSER bit <06> or <OS>,
MSER <09:08> contains a code which identifies the source of the
error as Q22-Bus memory, as on-board local memory or as one of the
two memory expansion modules. Additional parity errors can not
update the contents of MSER <09:08> until after software has
cleared bits MSER <06:05>.
MSER bit <01> is a write wrong parity bit which is set for
diagnostic purposes only.
MSER bit <00> is a parity error enable bit which enables local
memory parity checking for both CPU and DMA reads.
1

o 987 654 3 2 1 0
+---------------------------------------------------------------+
unused, returns 0
! ! ! ! !
! O! ' !
+---------------------------------------------------------------+
! !
MEM CD1 ----------------------------+ !
MEM CDO ------------------------------+
CPU NXM --------------------------------+
CPU LPE ----------------------------------+
!
CPU QPE ------------------------------------+ !
DMA QPE --------------------------------------+
MS LEB ----------------------------------------+
WRW PAR --------------------------------------------+
PAR ENB ----------------------------------------------+
1

Bit(s)

Meaning

Mnemonic

31:10
09
08

Unused. Reads as zero.
Memory Code 1 - O. When one of the two CPU
parity error bits (MSER <06:05» is set,
the two read-only MEM CD bits are loaded
with a 2-bit code which indicates the source
of the parity error per the following table:

MEM CD1
MEM CDO

00
01
10
11

Q22-Bus Memory or Device
KA630 On-Board Memory
Memory Expansion Module #1
Memory Expansion Module #2

A second parity error will not update this
code unless software has cleared the CPU
parity error bits.MEM CD <1:0> are cleared
by power up, by the negation of DCOK and by
writes to the Bus Initialize Register.

-- -

... ------.- ........

--.---....

--~

--.-~---.----.

Meaning

Bit(s)

Mnemonic

CPU NXM

CPU Non-Existent Memory Error. This bit
is set by any CPU non-prefetch read
or write operation which references
non-existent memory, causing a trap
through SCB vector 04. Writing a "1" to
this bit clears it; writing a "0" to this
bit has no effect. CPU NXM is cleared
by power up, by the negation of DCOK and
by writes to the Bus Initialize Register.

CPU LPE

CPU Local Address Space Parity Error. If
parity error detection is enabled (MSER
<00> is set), then CPU LPE is set by any
CPU read access (prefetch or non-prefetch)
to local memory address space which causes
a parity error. The MicroVAX chip does not
receive an error indication on that cycle.
The next MicroVAX cycle is aborted,
causing a trap through SCB vector 04.
Writing a "1" to this bit clears it;
writing a "0" to this bit has no effect.
CPU LPE is cleared by power up, by the
negation of DCOK and by writes to the
Bus Initialize Register.
Note: Only those memory bytes selected by
MicroVAX chip outputs BM <3:0> can
cause a CPU LPE parity error.
Note: Because the fetch which caused the
parity error is not aborted, it
could be difficult for software to
determine the result of the error.
For this reason, parity errors which
set this bit are generally treated
as fatal errors.

CPU QPE

CPU Q22-Bus Address Space Parity Error.
CPU QPE is set by any CPU non-prefetch
read access to the Q22-Bus Address Space
which results in a parity error, causing
a CPU trap through SCB vector 04. If the
CPU is accessing local memory via the
Q22-Bus Map, parity detection is enabled
only if MSER <00> is set. If the CPU is
accessing the Q22-Bus, parity detection
is enabled or disabled at the external
Q22-Bus memory or device. Writing a "1"
to this bit clears it; writing a "0" to
this bit has no effect. CPU QPE is cleared
by power up, by the negation of DCOK and
by writes to the Bus Initialize Register.

Meaning

Bit(s)

Mnemonic

DMA QPE

DMA Q22-Bus Address Space Parity Error.
If parity error detection is enabled
(MSER <00> is set), then DMA QPE is set
by any external read access to KA630 local
memory which results in a parity error.
This type of parity error does not cause
the epu trap through seB vector 04. (The
DMA device typically interrupts with an
error indication). Writing a Ifl" to this
bit clears it; writing a "0" to this bit
has no effect. DMA QPE is cleared by pov;rer
up, by the negation of DeOK and by writes
to the Bus Initialize Register.

MS LEB

Memory System Lost Error Bit. This bit is
set by an operation which sets MSER <06>
or <05> after one or both of those bits
have already been set. Writing a "I" to
this bit clears it; writing a "OTI to this
bit has no effect. MS LEB is cleared by
power up, by the negation of DeOK and by
writes to the Bus Initialize Register.
Unused.

Read as zeros.

WRW PAR

Write Wrong Parity. If this read-write bit
is set, and either the epu or a Dt-:!.A device
writes to local memory, then wrong parity
is written into the parity bits of the
MOS RAM's. If this bit is clear, correct
parity is written. WWR PAR is cleared
by power up, by the negation of DeOK and
by writes to the Bus Initialize Register.

PAR ENB

Parity Enable. If this read-write bit is
set, local memory parity error detection
is enabled. If this bit is clear, parity
errors are ignored during all epu and
DMA reads from local memory. PAR ENB is
cleared by power up, by the negation of
DeOK and by writes to the Bus Initialize
Register.
Note:

PAR ENB controls parity detection
for all CPU reads from local memory,
including accesses via the Q22-Bus
Map. PAR ENB has no affect on epu
reads from external Q22-Bus memory.

9.4.2

CPU Error Address Register

(Hex Address: 2008 0008)

The CPU Error Address Register (CEAR) is located in the local
register I/O address space at physical address 2008 0008. It
can only be accessed by the on-board processor and contains
valid information only when either MSER <06> (CPU LPE) or
MSER <05> (CPU QPE) is set.
The CPU Error Address Register contains the address of the page
in local memory which caused a parity error during an access by
the on-board CPU. The contents of this register is latched when
either MSER <06> or MSER <05> is set. Additional local memory
parity errors have no effect on the CE~~ until software clears
MSER <06:05>.
Local memory address bits <23:09> are loaded into CEAR bits
<14:00>. CEAR bits <31:15> always reads as zero.
3

1 1

5 4

a
+----------------------------------------------------------------+
unused, returns 0

Local Memory
Address Bits <23:09>

+----------------------------------------------------------------+
9.4.3

DMA Error Address Register

(Hex Address: 2008 OOOC)

The DMA Error Address Register (DEAR) is located in the local
register I/O address space at physical address 2008 OOOC. It
can only be accessed by the on-board processor and contains
valid information only when MSER <04> (DMA QPE) is set.
The DMA Error Address Register contains the address of the page
in local memory which caused a parity error during an access by
an external device. The contents of this register is latched when
MSER <04> is set. Additional local memory parity errors have no
effect on the DEAR until software clears MSER <04>.
Local memory address bits <23:09> are loaded into DEAR bits
<14:00>. DEAR bits <31:15> always reads as zero.
3

1 1

5 4

o
+----------------------------------------------------------------+
unused, returns 0

Local Memory
Address Bits <23:09>

+----------------------------------------------------------------+

9.5

Memory System Operation

The KA630 memory system can perform the following data transfer
and memory refresh cycles:
1.
2.
3.
4.
5.
6.
7.
Note:

MicroVAX accesses local memory directly
MicroVAX accesses local memory through Q22-BusMap
MicroVAX accesses on-board registers in the local
or Q22-Bus I/O address space.
MicroVAX accesses Q22-Bus memory or registers
External Q22-Bus device accesses local memory through
Q22-Bus Map
External Q22-Bus device accesses the KA630 Interprocessor
Communication Register (in the Q22-Bus I/O space)
KA630 performs memory refresh cycle
The MicroVAX does not require access to the memory system
when it accesses internal processor registers (including
those implemented external to the MicroVAX chip) .

Access to the local memory data/address paths and control of the
Q22-Bus are arbitrated independently. An external device can gain
control of the Q22-Bus and access a KA630 register (in the Q22-Bus
address space) while the MicroVAX chip is accessing local memory.
When an external device accesses KA630 local memory, MicroVAX
cycles are not interrupted until the Q22-Bus Map has decoded the
local memory address.
When the local memory is between cycles, it continually decodes
the address on the MicroVAX address/data lines. When it receives
a refresh or external device request, it switches off the
MicroVAX address/data lines and monitors the address lines from
the refresh logic or from the Q22-Bus Map.
When the local memory is between cycles{ the arbitrator for
the local memory responds to requests in the following order
of priority:
1.
2.
3.

MicroVAX request
External device request
Refresh request

When the local memory is completing a cycle, the arbitrator for
the local memory responds to requests in the following order
of priority:
1.
2.
3.

External device request
Refresh request
MicroVAX request

The local memory cycle time is 400 nsec for all read, write or
refresh cycles.

The MicroVAX must have control of the Q22-Bus:
1.
2.
3.
4.

Before it can perform any read-lock cycle.
Before it can access local memory via the Q22-Bus Map
Before it can access the Interprocessor Communication
Register or one of the Q22-Bus map registers.
Before it can perform Q22-Bus cycles

On an arbiter KA630, which contains the Q22-Bus arbitrator, the
MicroVAX has control of the Q22-Bus except when the KA630 has
granted an external DMA request. On an auxiliary KA630, the
MicroVAX can gain control of the Q22-Bus only by posting a DMA
request.
The MicroVAX accesses Q22-Bus memory and registers by using the
following Q22-Bus cycles:
1.
2.
3.
4.
5.
6.
7.

Data-Out-Byte (DATOB) for 8-bit writes
Data-In (DATI) for 16-bit reads (non-locked)
Data-Out (DATO) for l6-bit writes
Block Data In (DATBI) for 32-bit reads (non-locked)
Block Data Out (DATBO) for 32-bit writes
A DATI followed by a DATO for 16-bit read lock
followed by a 16-bit write unlock
A DATBI followed by a DATBO for 32-bit read lock
followed by a 32-bit write unlock

Note:

When performing 32-bit reads from non-block mode memory,
two successive DATI cycles are substitued for the DATBI
cycle. When performing 32-bit writes to non-block mode
memory, the two successive DATO cycles are substitued
for the DATBO cycle. The same sUbstitutions are made
for the 32-bit read lock followed by a 32-bit write
unlock. In all three cases, the KA630 retains control
of the bus between successive DATI and/or DATO cycles.

Note:

When the processor reads a byte from the Q-Bus the
KA630-A performs a DATI cycle with address bit 0
correctly reflecting the byte address.

KA630 Boot and Diagnostic Facility

10.0

The KA630 Boot and Diagnostic Facility features one 16-bit
register and two 28-pin ROM Sockets for 16K, 32K or 64K bytes of
16-bit read-only memory. The ROM memory is located on consecutive
word boundaries and may be accessed via longword, word or byte
references.
The ~_630-A CPU Module populates the two ROM sockets with 64K
bytes of 16-bit ROM (or EPROM). This ROM contains the KA630-A
Console Program. If this ROM is replaced for special applications,
the new ROM must contain some version of the Console Program.
10.1

Boot and Diagnostic Register

(Hex Address: 2008 0000)

The 16-bit Boot and Diagnostic Register (BDR) is located at physical
address 2008 0000. It can be accessed by KA630 software, but not by
external Q22-Bus devices. The BDR allows the Boot and Diagnostic ROM
programs to read various KA630 configuration bits and to load the
4-bit error display.
111
5 4 3

1
2

o 0

654

o 0 0 0

----+

PWR OK
HLT ENB

-------+

CPU CDI
CPU CDO

----------------+
-------------------+

BDG CDI
BDG CDO

----------------------+
-------------------------+

DSPL
DSPL
DSPL
DSPL

----------------------------------------+
-------------------------------------------+
----------------------------------------------+
-------------------------------------------------+

03
02
01
00

Bit(s)

Mnemonic

PWR OK

Power OK. This read-only bit is set if
the Q22-Bus BPOK signal is asserted and
clear if BPOK is negated.

HLT ENB

Halt Enable. This read-only bit reflects
the status of external connector pin 13
(section 3.3.2). The set condition of
this signal enables the various external
halts. Also, following the execution of
a HALT instruction in kernel mode, the
KA630 ROM Program reads the HLT ENB bit
to decide whether to enter the Console
program (HLT ENB set) or to restart the
operating system (HLT ENB clear) .

13:12
11
10

Meaning

Unused. Always Reads as zero.
CPU CDI
CPU CDO

CPU Code <01:00>. These two read-only bits
originate from connector pins 14:15. They
indicate whether the KA630 is configured
as the arbiter or as one of the three
auxiliaries:
CPU CD <1:0>
00
01
10
11

09
08

BDG CDI
BDG CDO

Configuration
KA630 Arbiter
KA630 Auxiliary #1
KA630 Auxiliary #2
KA630 Auxiliary #3

Boot and Diagnostic Code <1:0>. This
2-bit read-only code reflects the status
of configuration and display connector
pins 14:13 (refer to section 3.3.2). The
KA630 ROM programs use BDG CD <1:0> to
determine the power up mode as follows:
CPU CD <1:0>
00
01
10
11

Power Up Mode
Run.
Language Inquiry.
Test.
Manufacturing.

Refer to section 10.1.1 for more details
07:04

Unused. Always Reads as zero.

Bit(s)

Mnemonic

03
02
01
00

DSPL 03
DSPL 02
DSPL 01
DSPL 00

10.2

ROM Memory

10.2.1

ROM Sockets

Meaning
Display <03:00>. These four write-only
bits update an external LED display.
Writing a "I" to a bit lights the
corresponding LED. Writing a "a" to
a bit turns its LED off. The display
bits are set (all LED's are lit) by
power up and by the negation of DeOK.

The two ROM sockets are compatible with 8K, 16K and 32K X 8
ROM's. A machine-inserted jumper selects the pin 27 input to
be either +SV (for 8K and 16K parts) or ROM Address bit 14
(for 32K parts) .
The KA630-A is shipped with two 32K X 8 ROM's and with the
jumper in the ROM Address bit 14 position.
10.2.2

ROM Address Space

The entire Boot and Diagnostic ROM may be read via either the
64KB Halt Mode ROM space or the 64KB Run Mode ROM space. Writes
to either of these address spaces will result in a non-existant
memory trap.
Any I-Stream Read from the Halt Mode ROM space places the
KA630 in Halt Mode. The front panel RUN light is off and the
Halt input to the MicroVAX chip is disabled.
Any I-Stream Read which does not access the Halt Mode ROM
space, including reads from the Run Mode ROM space, places
the KA630 in Run Mode. The front panel RUN light is lit and
the Halt input to the MicroVAX chip is reenabled.
Writes and D-Stream Reads to any address space have no effect
on Run Mode/Halt Mode status.
Note:

I-Stream Reads include all instruction fetches (except
when the MicroVAX chip retries a fetch following a
non-existent memory or a parity error) and certain
character string data fetches (again, except for those
retries which follow an error). All reads which are not
I-Stream Reads are D-Stream Reads.
A clear implication of this note is that, when running
in Halt mode, the ROM programs can not use character
string instructions to fetch data from outside the
Halt Mode ROM address space.

------------""----"--------""---------------------

10.2.2.1

Halt Mode ROM Address Space

The KA630 always responds to the full 64KB Halt Mode ROM Space
(Hex Addresses: 2004 0000 - 2004 FFFF). When the KA630 contains
l6KB of ROM memory, it appears four times, once within each l6KB
of the Halt Mode ROM space. When the KA630 contains 32KB of ROM
memory, it appears twice, once within each 32KB of ROM space.
10.2.2.2

Run Mode ROM Address Space

The KA630 always responds to the full 64KB Run Mode ROM space
(Hex Addresses: 2005 0000 - 2005 FFFF). When the KA630 contains
16KB of ROM memory, it appears four times within the Run Mode
ROM space. When the KA630 contains 32KB of ROM memory, it
appears two times within the ROM memory space. Note that the
Run Mode ROM space accesses the same ROM code as the Halt
Mode R0l1 space.
10.2.3

KA630-A Console Program Operation

The KA630-A CPU Module populates the two ROM sockets with 64K
bytes of l6-bit ROM (or EPROM). This ROM contains the KA630-A
Console Program which can be entered by transferring program
control to location 2004 0000.
Section 6.4.4 lists the various halt conditions which cause the
MicroVAX to transfer program control to location 2004 0000. These
conditions include the kernel mode halt instruction, assertion of
the external halt input to the chip and certain fatal machine
checks. When DCOK has been negated, either at power up time or by
reboot, the combined assertion of DCOK and POK initiates program
execution at location 2004 0000.
When running the KA630-A Console Program provides the services
expected of a VAX-II console system. In particular, the following
services are available:
1.

Automatic restart or bootstrap following processor halts
or initial power up.

An interactive command language allowing the user to
examine and alter the state of the processor.

Diagnostic tests executed on power up that check out
the CPU, the memory system and the Q22-Bus Map.

Support of video or hardcopy terminals as the console
terminal as well as support of QVSS based bitmapped
terminals.

Refer to the KA630-A Console Program Specification for a complete
description of these features.

10.2.3.1

Power Up Modes

The Boot and Diagnostic ROM programs use Boot and Diagnostic Code
<1:0> (section 10.1) to determine the power up modes as follows:
Code

Mode

Run (factory setting). If the console terminal supports
the Multi-national Character Set (MCS), the user will
be prompted for language only if the time-of-year clock
battery backup has failed. Full startup diagnostics are
run.

Language Inquiry. If the console terminal supports MCS,
the user will be prompted for language on every power up
and restart. Full startup diagnostics are run.

Test. ROM programs run wrap-around serial line unit (SLU)
tests.

Manufacturing. To provide for rapid startup during certain
manufacturing test procedures, the ROM programs omit the
power up memory diagnostics and set up the memory bit map
on the assumption that all available memory is functional.

11.0

KA630 Time of Year Clock

11.1

Battery Backed-up Watch Chip

The KA630 contains the Motorola MC146818 CMOS watch chip and
battery backup circuitry which interfaces, via the external
connector, to a set of batteries which are mounted on the
FCC cutout. The battery backup for this chip is spec'd to
be greater than 240 hours when using three Ni Cad batteries
in series.
The operating system software must fetch the correct time from
this chip whenever power is restored to the system. If the power
was off long enough for the battery voltage to go below spec, or
if the battery was temporarily disconnected while the system
power was off, the time in the watch chip is undefined. If the
operating system detects a cleared Valid RAM and Time (VRT) bit
(in watch chip register CSR D), it must prompt the system
operator (or whoever turns on the system) for the time and then
load this time into the watch chip.
Although the MicroVAX Interval Timer interrupts have a resolution
of 10 ms, the watch chip only has a resolution of seconds.
Therefore, the time resolution is as follows:
While under full power supply power
After power down for less than 240 hours
<while watch chip is powered by battery}

11.2

10 milliseconds
1 second

Watch Chip Registers

The watch chip contains 64 eight bit registers, 10 of which contain
time of day data, 4 of which are CSRs, and the remaining 50 provide
50 bytes of battery backed-up RAM. They are addressed as follows
from a base address of 200B 8000:
Number

o
1

2
3
4

5
6
7

Function
seconds
second alarm
minutes
minute alarm
hours
hour alarm
day of week
date of month
month
year

Address Offset
from base address
00
02
04
06
08

OA
OC
OE

10
12

Comments
used on reads only
not used
loaded and read
not used
loaded and read
not used
not used
loaded and read
loaded and read
loaded to produce
28 or 29 day Feb.
(not read by VMS)

Comments

Address Offset
from base address

Number

Function

10
11
12
13

CSR A
CSR B
CSR C
CSR D

14
16
18
lA

loaded and read
loaded and read
not used
read-only

1st byte of RAM

Uses assigned by
the ROM code

50th byte of RAM

Note:

Even though the addressing is on word boundaries, the time of
year data and the RAM locations are loaded into or read out
of the chip a byte at a time.

11.2.1

Time of Year Data Registers

Software should read the time of year data registers only after
reading a cleared Update in Progress bit (CSR A <7» and only when
all interrupts are disabled (this assures that reading of the
registers will not be delayed beyond the time for which they are
valid). When the Update in Progress bit is clear, the content of
these registers is guaranteed to be stable for 244 microseconds
minimum.
Software should load the time of year data registers only after
setting the SET bit (CSR B <7». After loading the correct time
and date into the time of year data registers, software loads
20 (hex) into CSR A and then clears the SET bit by loading 6
into CSR B.
ADDRESS

UNITS

DECIMAL
RANGE

HEXADECIMAL
RANGE

200B 8000
200B 8004
200B 8008
200B 800E
200B 8010
200B 8012

seconds
minutes
hours
day of mo.
month
year

o - 59

00
00
00
01
01
00

11.2.2

0 - 59
0 - 23
1 - 31
1 - 12
o - 99

- 3B
- 3B
- 17

- IF

- OC
- 63

Control and Status Register A

Control and Status Register A (CSR A) contains the Update in
Progress bit (UIP), the divider selection bits (DV <2:0» and
the rate selection bits (RS <3:0».
7

! RS2

! RSI

+-----+-----+-----+-----+-----+-----+-----+-----+
! UIP

! DV2

(0)

! DV1 ! DVO
! (1) ! (0)

! RS3

(O)

(O)!

(0)

! RSO

(0)

+-----+-----+-----+-----+-----+-----+-----+-----+

The UIP bit is a read only bit that is set when there is an update ~~
progress within the chip. This bit must be read prior to reading the
time. If the UIP bit is a 1, an update is in progress and the time
registers are undefined. If the UIP bit is a 0, there is a minimum
of 244 usec available prior to the next update cycle. (To completely
read the 5 time registers should only require about 40 usec, worst
case, if interrupts are disabled) .
This register is undefined after battery power has been lost.
Whenever the operating system software loads the time of year
data registers, it must also load 20 (hex) into CSR A. Setting
DV <2:0> = 2 sets up the timer for operation with the 32.768 khz
oscillator. Setting RS <3:0> = 0 disables the unused interrupt
and square wave outputs from the chip.
This register is not affected by the chip going into or out of
the normal BBU mode, so long as the battery voltage remains
within spec.
11.2.3

Control and Status Register B

Control and Status Register B (CSR B) contains the SET bit, four
bits which enable chip functions which are not used in the KA630
design and three bits which control timer format and operation.
7

+-----+-----+-----+-----+-----+-----+-----+-----+
! SET! PIE! AlE! UIE ! SQWE! DM
! (0) ! (0) ! (0)
(O)! (1)

!24/12! DSE !
(1)
(0)

+-----+-----+-----+-----+-----+-----+-----+-----+
SET is a read-write bit that is used to enable and disable clock
operation. When written with a 0, the internal time updates occur
every second. When written with a 1, the updates are disabled so
that the program may load the time of year registers. This bit
must be set prior to setting the time. If the chip is in the
middle of an update, setting this bit aborts the update.
Periodic Interrupt Enable (PIE), Alarm Interrupt Enable (AlE),
Update Ended Interrupt Enable (UIE) and Square-Wave Enable (SQWE)
are read-write bits which enable and disable chip outputs that
are not used by the KA630 design.
Data Mode (DM) is a read-write bit which controls whether the
time and date registers use binary or BCD formats. This bit is
loaded with "1" to select binary format.
24/12 is a read-write bit which controls whether the hour register
operates in 24-hour or 12-hour mode. This bit is loaded with a
"1" to select 24-hour mode.

~~-~~~~-.-~.-----

-------,--------

Daylight Savings Enable is a read-write bit which enables or
disables special daylight savings time changes for the last
Sunday in April and the last Sunday in October. This bit is
loaded with a "0" to disable this function.
This register is undefined after battery power has been lost.
Whenever the operating system software loads the time of year
data registers, it must restart the timer by loading 6 (hex)
into CSR B. Loading 6 into this register clears the SET bit and
correctly loads the DM, 24/12 and Daylight Savings Time bits.
This register is not affected by the chip going into or out of
the normal BBD mode, so long as the battery voltage remains
within spec.
11.2.4

Control and Status Register C

This read-only register accesses interrupt flags which pertain
to functions not implemented by the KA630 design.
11.2.5

Control and Status Register D

Control and Status Register D (CSR D) is read-only register which
contains the Valid RAM and Time bit (VRT). The remaining seven bits
always read as zeros.
7

+-----+-----+-----+-----+-----+-----+-----+-----+
! VRT I

Read as zeros

+-----+-----+-----+-----+-----+-----+-----+-----+
The Valid RAM and Time (VRT) bit is read by the software, before
reading the time registers, to verify the validity of the time.
If the battery voltage goes below spec during the BBD mode, this
bit is set to 0 by the hardware sensing circuitry during powerup,
indicating that the time registers are undefined. The VRT bit is
automatically set when this register is read. If this bit was
clear, the time registers must be updated immediately, since this
bit will subsequently indicate that the chip contains a valid time
setting.
Note:

If battery voltages are removed and then restored during
power down, KA630 logic guarantees that VRT = O.

11.2.6

RAM Memory

The fifty bytes of ~~ memory are used by the KA630-A Console
Program to store information required to restart the machine
following a Halt which transfers program control to location
20040000 (hex). One of these RAM locations, designated the
Console Program Mailbox (CPMBX), is used for communication
between the operating system and the console program.
The use of these bytes is defined in the
Program Specification.

K~630-A

Console

11.3

Powerup

Following a power up, the KA630 console program reads the VRT
bit in CSR D. If this bit is set, the RAM and time data are
valid. If this bit is clear, then the RAM and time data are
invalid, and the console program disables the clock by setting
the CSR B SET bit.
When the operating system gains control of the machine, it checks
the CSR B SET bit. If that bit is set, then the operating system
must request the correct time of year from the operator (or from
whoever turns on the system).
11.3.1

Valid RAM and Time

If the VRT bit is set, then the RAM and Time data is valid. The
operating system reads the UIP bit in CSR A, to assure that an
update isn't in progress. If this bit is read as a 1, the watch
chip is doing an update and the data is invalid until it is
through. The maximum time for the update is 1.984 ms.
If the UIP bit is read as a 0, then the clock registers can be
read by the operating system. The operating system reformats the
time into a 32-bit count and loads it into the memory location
which contains the time of day count during system operation.
11.3.2

Invalid RAM and Time

If the VRT bit is clear, then the RAM and Time data is invalid.
The operating system stops timer operation by setting the SET
bit (CSR B <7» and then requests the time of year from the
operator. After loading the correct time and date into the time
of year data registers, the operating system loads 10 (hex)
into CSR A and then clears the SET bit by loading 6 into CSR B.
The operating system also reformats the time into a 32-bit count
and loads it into the memory location which contains the time of
day count during system operation.

12.0

Interval Timer

The KA630 Interval Timer is contained within the MicroVAX chip.
When it is enabled, the interval timer posts an interrupt
request every 10 msec.
12.1

(IPR 24)

Interval Clock Control/Status Register

The Interval Clock Control/Status Register (ICCS) is accessed as
internal processor register 24 (decimal). ICCS implementation
is unique to the MicroVAX Chip and consists of a minimal
interval timer control.
3

765

+----------------------------------------------+-+--------------+
unused, returns 0

! 0 0 0 0 0 0

+----------------------------------------------+-+--------------+
Interrupt Enable (IE)

-------------------------+

ICCS <6> (IE) is a read-write bit which enables and disables the
interval timer interrupts. When this bit is set, an interval timer
interrupt is requested every 10 msec. When ICCS <6> is clear,
interval timer interrupts are disabled. ICeS <6> is cleared by
power up and by the negation of DCOK.
12.2

Interval Timer Operation

When lees <6> is set, the interval timer posts an interrupt
request every 10 msec. The interval timer is the highest
priority device at interrupt priority level 16 (hex). The
interrupt vector for the interval timer is eo (hex).

13.0

KDQ11 Console Serial Line Unit

13.1

Console Functionality

The console serial line provides the KA630 processor with a
serial interface for the console terminal. The console serial
line is full duplex. It provides an RS-423 EIA interface which
is also RS-232C compatible.
This serial line interface is based on the DC319 Digital Link
Asynchronous Receiver Transmitter (DLART), described in Digital
Purchase Specification A-PS-2117312-0-0.
The receive and transmit baud rates are always identical and are
determined by the Baud Rate Select signals (BRS <02:00> L) which
are received from an external 8-position switch via a connector
mounted at the top of the module.
The Baud Rate is selected as follows:
BRS02 L

BRSOO L

Baud Rate

H
H

300
600

H
H

L
L

H
L

1200
2400

H
H

H
L

4800
9600

L
L

19200
38400

13.2

BRSOI L

Console Registers

There are four registers associated with the Console Serial
Line Unit. They are accessed via internal processor registers
32-35 (decimal), per section 6.2.3:
Number
32
33
34
35

Mnemonic

Console Receiver Control/Status
Console Receiver Data Buffer
Console Transmit Control/Status
Console Transmit Data Buffer

----- - - - - - - - - - - -

----- - - - - -

RXCS
RXDB
TXCS
TXDB

-.-----..--- - - - - - - - - - - . - - - .

13.2.1

Console Receiver Control/Status Register

(IPR 32)

III

3
1

210
8 7 6 5
o
+------------------------------------+-+-----+-+-+--------------+
unused, returns 0

! 0 0 O!

0 0 0 0 0 0

+------------------------------------+-+-----+-+-+--------------+

Bit(s)

----------+

RX DONE
RX IE

------------------+
--------------------+

Mnemonic

31:12
11

RCV ACT

Meaning
Unused.

RCV ACT

10:08

Read as zeros.

Receiver Active. This read-only bit is
set at the center of the start bit of the
serial input data and is cleared at the
expected center (per Dh~RT timing) of the
stop bit at the end of the serial data.
RX DONE is set one bit time after RCV ACT
clears.
Unused.

Read as zeros.

RX DONE

Receiver Done.
This read-only bit is set
when an entire character has been received
and is ready to be read from the RBUF
Register. This bit is automatically cleared
when RBUF is read. It is also cleared by
power up, by the negation of DeOK and by
writes to the Bus Initialize Register.

RX IE

Receiver Interrupt Enable. This read-write
bit is cleared by power up, by the negation
of DeOK and by writes to the Bus Initialize
Register. If RX DONE and RX IE are both set,
a program interrupt is requested.

05:00

Unused.

Read as zeros.

13.2.2

Console Receiver Data Buffer (IPR 33)
I I I 111 1
6 5 4 3 2 1 0

3
1

8 7
o
+----------------------------+-+-+-+-+-+-----+------------------+
unused, returns 0

!O! !O 0 O!

+----------------------------+-+-+-+-+-+-----+------------------+
ERR ---------+
OVR ERR -------+
FRM ERR ---------+

-------------+
Received Data Bits ------------------+
RCV BRK

Bit{s)

Mnemonic

31:16

Meaning
Unused. Always read as zero.

ERR

Error.
This read-only bit is set if
RBUF <14> or <13> is set. ERR is clear
if these two bits are clear. This bit
cannot generate a program interrupt.

OVR ERR

Overrun Error. This read-only bit is set
if a previously received character was
not read before being overwritten by
the present character.

FRM ERR

Framing Error. This read-only bit is set
if the present character had no valid stop
bit.

NOTE:

Error conditions remain present until the next character
is received, at which point, the error bits are updated.
The Error bits are cleared by power up and by the
negation of DeOK.

12
11

10:08

Unused. This bit always reads as "0".
RCV BRK

Received Break. This read-only bit is set
at the end of a received character for
which the serial data input remained in
the SPACE condition for all 11 bit times.
RCV BRK then remains set until the serial
data input returns to the MARK condition.
RCV BRK is also cleared by power up and by
the negation of DCOK.
Unused. These bits always read as "0".

Bit(s)

Meaning

Mnemonic

Received Data Bits. These read-only bits
contain the last received character.

07:00

Console Transmitter Control/Status Register

(IPR 34)

3
1 8 7 6 5

3 2 1 0

13.2.3

+--------------------------------------------+-+-+---- -+-+-+-+
unused, returns 0

!O 0 O!

to!

+--------------------------------------------+-+-+---- -+-+-+-+
! !

TX RDY

----------------------+ !

TX IE

------------------------+

MAINT

--------------------------------+

XMIT BRK
Bit(s)

----------------------------------+

Mnemonic

Meaning
Unused.

31:08

Read as zeros.

TX RDY

Transmitter Ready. This read-only bit is
cleared when XBUF is loaded and sets whe~
XBUF can receive another character. XMT R:~
is set by power up, by the negation of DCC~
and by writes to the Bus Initialize Reg~sts~.

TX IE

Transmitter Interrupt Enable. This
read-write bit is cleared by power up, by
the negation of DCOK and by writes to the
Bus Initialize Register. If both TX RDY a~d
TX IE are set, a program interrupt is
requested.

05;03
02

Unused. Read as zeros.
M1UNT

Maintenance. This read-write bit is used
to facilitate a maintenance self-test. When
~AINT is set, the external serial input is
disconnected and the serial output is used
as the serial input. This bit is cleared by
power up, by the negation of DCOK and by
writes to the Bus Initialize Register.
Unused.

Read as zero.

Bit(s)

Mnemonic

XMIT BRK.

13.2.4

Meaning
Transmit Break. When this read-write bit
is set, the serial output is forced to
the SPACE condition. XMIT BRK is cleared
by power up, by the negation of DCOK and
by writes to the Bus Initialize Register.

Console Transmitter Data Buffer (IPR 35)

XBUF bits <31:08> are not used. XBUF bits <7:0> are write-only
bits used to load the transmitted character.
13.3

Additional Specifications
Serial Data Format:

8-bit data, No Parity,
One Stop Bit

Interrupt Vectors:

F8 (hex)
FC (hex)

Interrupt Priority:

IPL 14 (hex); same as BR4 on Q-Bus
(the console serial line un1t is
the highest priority BR4 device)

Note:

13.4

Receiver
Transmitter

Following a console terminal interrupt, the KA630
CPU sets the IPL = 14. The IPL is set = 17 for
external Q22-Bus BR4 interrupts.

Break Response

The KA630 Console Serial Line Unit may be configured either to
perform a halt operation or to have no response when a break
condition is received. A halt operation will cause the processor
to transfer program control to ROM location 2004 0000 (hex).
The Halt on Break Option is enabled if the Connector HLT ENB
signal is asserted (refer to sections 3.3.2 and 10.1).
The DLART recognizes a break condition at the end of a received
character for which the serial data input remained in the SPACE
condition for all 11 bit times. The Break Recognition line remains
asserted until software reads the RBUF.

14.0

Q22-Bus Control

14.1

Bus Initialize Register

(IPR 55)

The Bus Initialize Register is accessed as internal processor
register 55 (decimal). On an arbiter KA630, writing to this
register asserts the Q22-Bus BINIT signal for 10 usec (+/- 20%)
and clears all on-board register bits which are specified as
being cleared by writes to the Bus Initialize Register. On an
auxiliary KA630, writing to this register does not assert the
Q22-Bus BINIT signal, but it does clear all on-board register
bits specified as being cleared by writes to the Bus Initialize
Register. For either configuration (arbiter or auxiliary), this
register always reads as zero.
Note:

An auxiliary KA630 module receives BINIT from the Q22-Bus
and uses that signal to initialize the MicroV~~ chip and
to clear all internal register bits which are specified
as being cleared by the negation of DCOK (i.e. the
assertion of the Q22-Bus BINIT signal has the same
effect on auxiliary modules as the negation of DCOK) .

14.2

Multi-level Interrupts

When the KA630 is configured as the arbiter CPU, it responds
to interrupt requests BR7-4 with the standard Q22-Bus interrupt
acknowledge prototcol (DIN followed by IAK). The console serial
line unit and the interprocessor doorbell can request interrupts
at BR level 4 and have priority over all Q22-Bus BR4 interrupt
requests. After responding to any interrupt request BR7-4, the
MicroVAX CPU sets the processor priority to IPL 17. All BR7-4
interrupt requests are disabled unless software lowers the
processor priority.
When the KA630 is configured as an auxiliary, it does not respond
to interrupt requests from the Q22-Bus. However, it does respond
to the BR4 level interrupt requests from its console serial
line unit and interprocessor doorbell.
Interrupt requests from the KA630 interval timer are handled
internally by the MicroVAX chip. Interval timer interrupt
requests have a higher priority than BR6 interrupt requests.
After responding to an interval timer interrupt request, the
MicroVAX CPU sets the processor priority to IPL 16. Thus, BR7
interrupt requests remain enabled.
14.3

Interprocessor Communications Facility

The KA630 Interprocessor Communication Facility allows other
processors on the system to request program interrupts from
the KA630 without using the Q22-Bus interrupt request lines.
It also controls external access to local memory (via the
Q22-Bus map) and allows other processors to "halt" an
auxiliary CPU.

14.3.1

Interprocessor Communication Register

The Interprocessor Communication Register resides in the Q22-Bus
I/O page address space and can be accessed by any device which
can become Q22-Bus master (including the KA630 itself). The ICR is
byte accessible, meaning that a write byte instruction can write
to either the low or high byte without affecting the other byte.
The I/O Page address of the ICR varies with the four configurations
of arbiter and auxiliary KA630:
Hex 32-Bit
Address

Octal 22-Bit
Address

2000
2000
2000
2000

17
17
17
17

777
777
777
777

500
502
504
506

1
1

IF40
IF42
IF44
IF46
1
5

1
4

ICR
ICR
ICR
ICR

(KA630 Arbiter CPU)
(KA630 Auxiliary #1)
(KA630 Auxiliary #2)
(KA630 Auxiliary #3)

+--+-----------------+--+--+--+--+-----------+--+
o
0 0 0
! O!
0 0 0 0
+--+-----------------+--+--+--+--+-----------+--+

°°

DMA QPE

---+

AUX HLT

-------------------------+

DBI IE
LM EAE

-------------------------------+
----------------------------------+

DBI RQ

-------------------------------------------------+

Bit(s)

Mnemonic

DMA QPE

14:09
08

Meaning
DMA Q22-Bus Address Space Parity Error.
This read-only bit is set if Memory System
Error Register bit <04> (DMA QPE) is set.
The DMA QPE bit indicates that a parity
error occured when an external device (or
CPU) was accessing the KA630 local memory.
Unused.

AUX HLT

Read as zeros.

Auxiliary Halt. On an auxiliary KA630,
AUX HLT is a read-write bit. When set,
typically by the arbiter CPU, it causes
the on-board CPU to transfer program
control to the Halt Mode ROM Code. On
an arbiter KA630, AUX HLT is a read-only
bit which always reads as zero. It has no
effect on arbiter CPU operation.

Bit(s)

Mnemonic

Meaning
Unused.

Read as zero.

DBI IE

Doorbell Interrupt Enable. This bit, when
set, enables interprocessor doorbell
interrupt requests via ICR <00>. When the
on-board CPU is Q22-Bus master, DBI IE
is a read-write bit. When an external
device (or CPU) is bus master, DBI IE
is a read-only bit. DBI IE is cleared
by power up, by the negation of DCOK and
by writes to the Bus Initialize Register.

LM EAE

Local Memory External Access Enable. This
bit, when set, enables external access to
local memory (via the Q22-Bus map). When
the on-board CPU is Q22-Bus master, LM EAE
is a read-write bit. When an external
device (or CPU) is bus master, LM EAE is
a read-only bit. LM EAE is is cleared by
by power up, by the negation of DCOK and
by writes to the Bus Initialize Register.

04:01
00

14.3.2

Unused.
DBI RQ

Read as zeros.

Doorbell Interrupt Request. If ICR <06>
(OBI IE) is set, writing a "1" to DBI RQ
sets OBI RQ, thus requesting a doorbell
interrupt. If ICR <06> is clear, writing
a fll" to OBI RQ has no effect. Writing a
"0" to DBI RQ has no effect. OBI RQ is
cleared when the CPU grants the doorbell
interrupt request. OBI RQ is held clear
whenever DBI IE is clear.

Interprocessor Doorbell Interrupts

If the Interprocessor Communication Register OBI IE bit is
set, any Q22-Bus Master can request an interprocessor doorbell
interrupt by writing a lilt! into ICR bit <00>.
Interrupt Vector:

204

Interrupt Priority:

IPL 14 (hex); same as BR4 on Q-Bus
(the interprocessor doorbell is the
second highest priority BR4 device,
directly after the console serial
line unit) .

Note:

(hex)

Following a interprocessor doorbell interrupt,
the KA630 CPU sets the IPL = 14. The IPL is
set = 17 for external Q22-Bus BR4 interrupts.

15.0

Multi-Processor Considerations

15.1

Auxiliary/Arbiter Differences

When the KA630 is configured as an auxiliary, its operation diffe=s
from operation as an arbiter KA630 in several important areas:
1.

The arbiter KA630 arbitrates bus mastership per
the Q22-Bus DMA protocol; the arbitration logic
is disabled on an auxiliary KA630.

Both the arbiter and auxiliary KA630 request bus
mastership via the Q22-Bus DMA Request protocol.
a.
They both assert BDMR on the Q22-Bus.
b.
The arbiter KA630 receives DMGl from its
arbitration logic; the auxiliary receives
DMGl from its Q22-Bus BDMGI pin.
c. Only the auxiliary KA630 actually asserts
BSACK on the Q22-Bus.

The arbiter KA630 asserts the Q22-Bus BlNlT signal
when DCOK is negated and when its CPU software writes
to its Bus Initialize Register; the auxiliary KA630
never asserts Q22-Bus BINIT, but receives BlNIT and
uses it to initialize the MicroVAX chip and to clear
all internal registers which are cleared by the
negation of DCOK. (Refer to section 14.1).

The physical address of the Interprocessor Communication
Reqister is different for each of the four KA630
arbiter/auxiliary configurations (per section 14.3.1).

An auxiliary KA630 can be halted by setting bit <08>
(AUX HLT) of its lnterprocessor Communication Register.
On an arbiter KA630, this feature is disabled and
AUX HLT is a read-only bit which always reads as zero.
(Refer to section 14.3.1).

The CPU halts are controlled by the external connector
HLT ENB input. However, the external halts which are
affected differ somewhat for the arbiter and auxiliary
KA630 modules. (Refer to section 3.3.2).

Each arbiter or auxiliary KA630 module can field interrupt
requests from its interval timer, from its console device,
and from its interprocessor doorbell. Only the arbiter
KA630 can field interrupts from Q22-Bus interrupt request
lines BR7-4.

The arbiter asserts BlAKO to the Q22-Bus when it responds
to a Q22-Bus interrupt request; the auxiliary asserts
BlAKO to the Q22-Bus when it receives the assertion of
BIAKI from the Q22-Bus.

15.2

Although both the arbiter and auxiliary KA630 modules
contain the same time of year clock and battery back-up
circuitry, it is assumed that the auxiliary will be
configured without batteries and that its clock will
never actually be enabled.
Multi-Processor Features

The following features have been added to the KA630 to allow its
use in multi-processor systems:

15.3

A 2-bit code, received at the external connector{ allows
the KA630 module to be configured as the arbiter or as
one of three auxiliaries (section 3.3.2). Section 15.1
presents a list of arbiter/auxiliary differences.

The Interprocessor Communication Register (section 14.3)
provides a mechanism for interprocessor interrupts, for
enabling and disabling external access to local memory
and for flagging local memory parity errors caused by
external references. On auxiliary KA630 modules, it
also provides a mechanism for "halting!! the CPU.
KA630 Based Multi-Processor Systems

The KA630 multi-processor features were designed for use in a
message passing environment similar to the System Communications
Architecture (SCA) which is currently layered on the CI Port
Architecture.
Each KA630 processor in a system fetches instructions and data
primarily from its own local memory. The various processors
communicate via message queues stored in local memory which
has been mapped to the Q22-Bus address space. Typically, the
processors use the interprocessor doorbell feature to interrupt
each other after placing a message in an empty queue.
In most systems all Q22-Bus devices would be under the direct
control of the arbiter processor which fields all interrupts.
When a disk controller is under the direct control of the
arbiter CPU, then the arbiter must set up the transfer of
program and data information between the corresponding disks
and the auxiliary processors. The auxiliary processor would
be responsible for setting up its own Q22-Bus Map to point
to the local memory space which is a target of that transfer.

Following a power up or system restart, the auxiliary CPU runs
its self-test diagnostics, clears the valid bits in its Q22-Bus
Map mapping registers, enters Halt Mode ROM space and then sets
its own Interprocessor Communication Register bits <08> (AUX HLT)
and <06:05> (DBI IE and LM EAE). The arbiter CPU waits for the
auxiliary's LM EAE bit to set, "boots" the auxiliary CPU by
loading the appropriate programs and data into the arbiter's
own local memory which are mapped (via the Q22-Bus map) to an
assigned Q22-Bus address space. The arbiter then clears the
auxiliary's AUX HLT bit. The auxiliary CPU, still in Halt Mode
ROM space, waits for its AUX HLT bit to clear and then begins
auxiliary execution at a specified location in the Q22-Bus
address space (referencing local memory in the arbiter) _
15.4

PDP-II Based Multi-Processor Systems

Up to three auxiliary KA630 modules may be added to a KDFII-B
or KDJII-B based Q22-Bus system. Operation of a PDP-II based
system is similar to that of a KA630 based system. However,
the following issues must be addressed:
1.

When a PDP-II processor is arbiter, its "local" memory
is actually Q22-Bus memory_ This appears to present no
special problems. Obviously, a portion of the Q22-Bus
memory address space must be reserved for mapping the
auxiliary KA630 modules! local memory.

Since the PDP-II does not contain an interprocessor
communication register, an external device must be added
which allows the auxiliary KA630 modules to interrupt
the PDP-II.
/Since the KA630 console program does not interrupt the
arbiter CPU, they do not require modification if this
external device is not compatible with the KA630
interprocessor communication register (one could use
either a DLVll or a DRVl1) ./

APPENDIX A
Module Pinouts
A.I

KA630 Module Pinouts

The KA630 AB row module pinouts are compatible with the Q22-Bus
specification (DEC standard 160). The SRUN L signal appears on
pin AFI. The CD row module pinouts utilize the CD-Interconnect
to communicate with up to two memory expansion modules.
Note:

Tables A-I and A-2 list the KA630 AB and CD slot pinouts.
AAl
ABl
ACI
ADI
AEI
AFI
AHI
AJI
AKI
ALI
AMl

ANI
API
ARI
ASI
ATI
AUl
AVI

BIRQS L
BIRQ6 L
BDAL16 L
BDAL17 L
SRUN L
GND
GND
BDMR L
BHALT L
BREF L
GND

AA2
AB2
AC2
AD2
AE2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
Av2

+5
GND
+12
BDOUT L
BRPLY L
BDIN L
BSYNC L
BWTBT L
BIRQ4 L
BIAKI L
BIAKO L
BBS7 L
BDMGI L
BDMGO L
BINIT L
BDALOO L
BDALOI L

BAI
BBI
BCl
BDI
BEl
BFl
BHI
BJI
BKI
BLI
BMI
BNI
BPI
BRI
BSI
BTl
BUI
BVI

BDCOK H
BPOK H
BDAL18 L
BDAL19 L
BDAL20 L
BDAL21 L
GND
GND
BSACK L
BIRQ7 L
BEVNT L
GND
+5

KA630 Module AB Slot Pinouts
Table A-I

BA2
BB2
BC2
BD2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

+5
GND
+12
BDAL02 L
BDAL03 L
BDAL04 L
BDAL05 L
BDAL06 L
BDAL07 L
BDAL08 L
BDAL09 L
BDALIO L
BDALII L
BDALl2 L
BDAL13 L
BDAL14 L
BDAL15 L

CAl
CBl
CCI
CDI
CEI
CFl
CHI
CJl
CKl
CLI
CMI
CNI
CPI
CRI
CSI
CTI
CUI
CVI

GND

CA2
CB2
CC2
CD2
CE2
CF2
CH2
CJ2
CK2
CL2
CM2
CN2
CP2
CR2
CS2
CT2
CU2
CV2

+5
MAA<9> L
GND
RAS<5> H
BMCAS<O> L
RAS H
BMCAS H
MSID<O> L
MSWT H
RAS<4> H
MSID<l> L
MAA L
MAA<2> L
MAA<O> L
MAA<8> L
MSID<4> L
RAS<O> H

DAI
DBI
DCl
DDI
DEI
DFI
DHI
DJI
DKI
DLI
DMI
DNI
DPI
DRI
DSI
DTI
DUI
DVI

GND

DA2
DB2
DC2
DD2
DE2
DF2
DH2
DJ2
DK2
DL2
DM2
DN2
DP2
DR2
DS2
DT2
DU2
DV2

+5
MAA<7> L
GND
MAA<5> L
MAA<4> L
MAA<3> L
M..Zl.A<6> L
MSID<2> L
RAS<3> H
RAS<7> H
MSID<3> L
RAS<2> H
BMCAS<2> H
BHCAS<3> R
RAS<6> H

KA630 Module CD Slot Pinouts
Table A-2
A.2

MS630 Module Pinouts

The MS630-AA is a dual height module which mounts in the CD rows
and, therefore, has CD Row pinouts only. The MS630-BA, MS630-BB
and MS630-CA are quad height modules which have both AS and CD
row pinouts.
The MS630 AB row ,module pinouts connect with +5 volts (pins AA2,
SA2 and BVI) and ground (pins AC2, AJI, AMI, ATI, BC2, BJI, BMI
and BTl) only. The MS630 also connects pin AM2 to pin AN2
(passing BIAK) and pin AR2 to AS2 (passing BDMG). The CD row
module pinouts require the CD-Interconnect to communicate with
the KA630 module and/or another MS630 module.
Note:

The MS630 Module can not be used in slots for which the
Q22-Bus is connected to both the AS and CD rows (Q22/Q22
configuration). The CD rows must be compatible with the
the CD-Interconnect specification.

Tables A-3 and A-4 list the MS630 AS and CD slot pinouts.

AAI
ABI
ACI
ADI
AEI
AFI
ARI
AJI
AKI
ALI
AMI
ANI
API
ARI
ASI
ATI
AUI
AVI

AA2
AB2
AC2
AD2
AE2
AF2
AH2
AJ2
AK2
AL2
AM2
AN2
AP2
AR2
AS2
AT2
AU2
AV2

GND
GND

GND

+5
GND

BlAK L
BlAK L
BDMG L
BDMG L

BAI
BBI
BCl
BDI
BEl
BFI
BHl
BJI
BKI
BLI
BMI
BNl
BPI
BRI
BSI
BTl
BUI
BVI

BA2
BB2
BC2
BD2
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2

GND
GND

GND
+5

+5
GND

MS630 Module AB Slot Pinouts
Table A-3
CAl
CBl
CCI
CDI
CEI
CFI
CHI
CJl
CKI
CLI
CMI
CNI
CPl
CRI
CSI
CTI
CUI
CVl

MAA<9> L
RAS<5> H
BMCAS<O> H
RAS H
BMCAS H
MSlD<O> L
MSWT<l> H
RAS<4> H
MSID<l> L
MAA L
MAA<2> L
MAA<O> L
MAA<8> L
GND
RAS<O> H

CA2
CB2
CC2
CD2
CE2
CF2
CH2
CJ2
CK2
CL2
CM2
CN2
CP2
CR2
CS2
CT2
CU2
CV2

+5
MAA<9> L
GND
RAS<l> H
BMCAS<O> L
BMCAS<l> H
MSlD<2> L
MSWT<l> H
RAS<O> H
MSID<3> L
MAA<l> L
MAA<2> L
MAA<O> L
MAA<8> L
MSlD<4> L

DAI
DBI
DCI
DDI
DEI
DFI
DHI
DJI
DKI
DLI
DMI
DNI
DPI
DRI
DSI
DTI
DUI
DVl

MAA<7> L
MAA<5> L
MAA<4> L
MAA<3> L
MAA<6> L
MSlD<2> L
RAS<3> H
RAS<7> H
MSID<3> L
RAS<2> H
BMCAS<2> H
BMCAS<3> H
Spare
GND
RAS<6> H

DA2
DB2
DC2
DD2
DE2
DF2
DH2
DJ2
DK2
DL2
DM2
DN2
DP2
DR2
DS2
DT2
DU2
DV2

+5
MAA<7> L
GND
MAA<5> L
M..n.A<4> L
MAA<3> L
MA..2\<6> L
RAS<3> H
BMCAS<2> H
BMCAS<3> H
Spare
MSlD<4> L
RAS<2> H

MS630 Module CD Slot Pinouts
Table A-4

----------------------------------------------.------.---

APPENDIX B
Indicators, Switches, and Jumpers
B.l

KA630 Indicator Lights

Five Light Emitting Diodes are mounted at the top of KA630 Module.
The single green LED is lit if the Q-Bus BDCOK signal is asserted.
The four red LED's are controlled from the Boot and Diagnostic
Display Register. The status of these four bits is also available
on the connector mounted at the top of the KA630 module.
B.2

Switches

The KA630 contains no switches. All configuration information is
received via the external connector described in section 3.3.2.
B.3

Manufacturing Test Jumpers

To be supplied.

APPENDIX C
Physical Address Assignments
C.l

General
Address Range
0000
0100
2000
2000
2004
2005
2006
2008
200C
3000
3040

C.2

0000
0000
0000
2000
0000
0000
0000
0000
0000
0000
0000

Contents

OOFF FFFF
1FFF FFFF
2000 1FFF
2003 FFFF
2004 FFFF
2005 FFFF
2007 FFFF
200B FFFF
3FFF FFFF
303F FFFF
3FFF FFFF

Local Memory Space (16MB)
Reserved Memory Space ( 496MB)
Q22-Bus I/O Space (8KB)
Reserved I/O Space (248KB)
Halt Mode ROM Space
(64KB)
Run Mode ROM Space
(64KB)
Reserved Local ROM Space (128KB)
Local Register 1/0 Space ( 256KB)
Reserved I/O Space (255.25 MB)
Q22-Bus Memory Space (4MB)
Reserved I/O Space (252MB)

Q22-Bus I/O Space

The only KA630 register located in the 8KB Q22-Bus I/O address
space (2000 0000 - 2000 IFFF) is the Interprocessor Communication
Registers. This register is accessible by both the KA630 CPU and
external Q22-Bus devices:
Hex 32-Bit
Address

Octal 22-Bit
Address

2000
2000
2000
2000

17
17
17
17

IF40
1F42
IF44
1F46

777
777
777
777

500
502
504
506

(KA630 Arbiter CPU)
(KA630 Auxiliary #-1)
(KA630 Auxiliary #2)
(KA630 Auxiliary #3)

C.3

Local Register I/O Space

The 256KB Local Register I/O Space (2008 0000 - 200B FFFF)
contains KA630 registers which are not accessible from the
Q22-Bus. Most of the addresses in this space are unassigned
and respond as non-existent memory.
The following KA630 registers have device addresses within
the Local Register I/O Space:
Hex 32-Bit
Address
2008
2008
2008
2008

0000
0004
0008
OOOC

2008 8000

Register
Boot and Diagnostic Register
Memory System Error Register
CPU Error Address Register
DMA Error Address Register
Q22-Bus Map Registers

2008 FFFC
200B 8000

200B 807E

Time of Year Clock
Registers