KA630-A

This document is a preliminary specification (dated April 26, 1985) for the Digital Equipment Corporation (DEC) KA630-A Processor Module and its associated MS630 memory expansion modules. The introduction explicitly states that it does not describe a currently available product nor a commitment to implement.

The KA630-A is a quad-height Q22-Bus VAX11 processor module built around the MicroVAX CPU chip. Its key features and capabilities include:

• Core Processing: Integrates the MicroVAX CPU chip (a 32-bit virtual memory microprocessor with a subset of the VAX instruction set and full VAX memory management) and an optional Floating Point Processor.
• Memory System: Offers 256KB or 1MB of on-board memory, expandable up to a total of 16MB via two MS630 memory expansion modules (available in 1MB to 8MB capacities). All local memory includes byte parity generation and checking.
• Peripherals & Interfaces: Features a Q22-Bus interface with a DMA map, an Interval Timer, a 64KB Boot and Diagnostic ROM for system console functions and power-up diagnostics, a Console Serial Line Unit, and a battery-backed Time of Year Clock.
• Multiprocessor Support: The module can be configured as an arbiter CPU (managing Q22-Bus mastership and system-wide interrupts) or an auxiliary CPU within multiprocessor systems. An Interprocessor Communication Register facilitates communication and allows other processors to halt auxiliary CPUs. The arbiter KA630 is designed with the highest DMA priority.
• Operational Details: The specification details hardware-detected errors (e.g., non-existent memory, parity errors), various interrupt and DMA latency characteristics, power-up modes, and register descriptions.