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EX-QAEQA-TE-PRE

September 1994

430 pages

Original

23MB

Document:	Alpha 21164 Microprocessor Hardware Reference Manual
Order Number:	EX-QAEQA-TE
Revision:	PRE
Pages:	430
Original Filename:

OCR Text

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Digital Equipment Corporation
Maynard, Massachusetts

Pre1iminary, September 1994

/\.

Possession, use, or copying of the software described in this publication is authorized
pursuant to a valid written license from Digital or an authorized sublicensor.

:i"ca'?f!!~~t ~:li:;:J~::,~=t~~u~c!,~

this publication is

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'\I\.

corre~ ,:~\ll''lt&\
••

ii:~~~jltiµcts

· : \l!l! :~ ~;

Digital Equipment Corporation makes no representations that the use of
in the
manner described in this publication will not infringe on existing or fuJtm~ patei\~jj~ts, nor do ·(JV
the descriptions contained in this publication imply the granting of ij~~~40 mak~fj~~' or sell ·.··

~;;~;.;:c~~=~-ifu ~ M~~ion.

C1'-t:>$.tw

ew1:::~'•,~

The following are trademarks of Digital Equipment
AlphaGeneration,
AXP, DEC, DECchip, Digital, OpenVMS, VAXJ:::YAX DQ~NT, the··:A,:lphaGeneration design
mark, and the DIGITAL logo.
.. \}'
..,.,'tl\~\..
·

o{Jk!!!~j'tpany.

Hewlett-Packaxd

is a registered traMmark
IEEE is a registered trademark of The In~tj@.Q.]~:f::.;Electrl&1~l::~.µd Electronics Engineers, Inc.
OSF/1 is a registered trademark of Open 5,1hvati.(t19µndatfo.ijf
Prentice Hall is a registered trademark_q~]?rentice~Bi.l\:Jnc. of Englewood Cliffs, NJ.
Windows NT is a registered tradema:d(ifjlfj~rosoft CoWation.
All other trademarks and

This document was

registe~~j:jr:=~:=~M~K~I~ the ;roperty of their respective holders.

~!·a~:;~\~~
'%\t~~'ttt{~;:-%0

(~t~~Jl

+1\t~t~{l;t\·

''Y

Veraion 2.1.

:-:·:·:·:

···:·:·::::::::::::::::::..

<\(~1~ ~~eri!f

Preface ..................................... .

·~71du::;~~;~~!;~. ::::::::~ili :::~;~i1~:'.'.fi\'~l ~[~ l~ }: :::::::::
1.1.2

Integer Data Types .... .'. At:b~.... ··~\H!~Lt:~.,. . ............. .

ln~~:nal~~;;~;~~~~~~~i:;lt[;;Wf>: :::::::
2.1.1
2.1.1 .1

Instruc~fp. Fetchl@h4 DecodMfQnit ................... .

2.1.1.4
2.1.1.s

Instnietiih. Trarislation Buffer .................... .
Int#.rrnpt~\[\\~[ht~.... · :~:= - • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

lnstriiCtiQn. DecOiliHuid Issue ..................... .

~:~:~:~
~:~:~

2.1.4
2.1.4.1

~~~::li:~1~\~;:::::::::::::::::::::::::::

~~!~i:lf~\~!~i~n· U~it:: : :: : :: : :: : : :: : : : : :: :: :

' '"·· M~iP..9,YAi\.dd~l~s Translation Unit .................... .

fl?

\Uifa Traiilation Buffer ......................... .

A•iliJ1~!-ii!il{!l!\\\\(i&~~!;::~~~ :~d: ~e: ~i~~ ~:d~~s: ~I~: ::::::::::

./:\i~r·· 2.1.5.II:
.{[::::[[;'.:..
2. t~~wr
···:::tllh::.,. 2dUf 1
·.:,:\lii!j[g~jJ;:;.6.2
2MUS.:~3

2.1··~a:~i\)·

2.1. 7 · ·:-

c~Mi~:·Control and Bus Interface Unit ................. .
Cach·~ Organization ............................... .
Data Cache .................................. .
Instruction Cache .............................. .
Second-Level Cache ............................ .
External Cache ............................... .
Serial Read-Only Memory Interface ................... .

xxi

1-1
1-2
1-2
1-3
1-3

2-2

2-4
2-5
2-5

2-6
2-7
2-8
2-9
2-9

2-10
2-10
2-11
2-11
2-12
2-12
2-12
2-12
2-13
2-13
2-13
2-13

iii

Pipeline Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pipeline Stages and Instruction Issue . . . . . . . . . . . . . . . . . .
Aborts and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

·:\~~~~~~lf:::--17
":::2k18

2.3.3
2.3.3.1
2.3.4
2.4
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
Fill Operation ........... :··. A~th~.... ··:>~~lt~~~kh.:-.· . . . . . . . . . . .
2.6
Mbox Store Instruction Execution .. :'·::~l@t:~.....··:'?ffk: . . . . . . . . . .

2-31
2-32

Ordering of.Ji!ncacHiJ.bl~ Spacf:t\ffite Instructions . . . . . . .
Performance .~ea~u:r@w.erit/$ypport-Performance Counters . . . .

2-36
2-36

2.2
2.2.1
2.2.2
3

/\.2-13

~:~· Sch!:i=~u:n~o~~!: R~ie~·:::::::::::::::::::::: :ift;j~l~\\4,13~,
0
~:~:~
~~~~~::sD~~~~ '.1'.1~. I~~~~- ~. ~]~~~~~.'~lib : ~~\j
8

!1; Wri~]~i;~[~~t!r1'.';~;tia}: \:-: :T :T !~
2.7.5
2.8
2.9
2.10

3
3.1
3.2

3-1
3-3

4
4-2
4-2
4-4
4-4
4-4

4.2.2
iv

System Clock .................................... .

4-5
4-5
4-6

4.2.3
4.2.4
4.2.4.1
4.2.4.1.1

4.2.4.1.2
4.3

Delayed System Clock ............................. Ah
4-8
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ·A]\:k.. 4-8
Reference Clock Examples . . . . . . . . . . . . . . . . . . . . . . . . \Jl::.. 4-9
Case 1: ref_clk_in_h Initially Sampled Low by}/t:::;:::,,,.,.... -:::{:\:jt,
DPLL ............................. dh:· :··':'''YYU!Jtt){~1o

~~~2: -~~~~~~~.I~'.~~.l~ .S.a~~l~~·~'t\t .... +q~'

Physical Address Considerations ..............-~:':''.!:':':!. • • • ··::~::q@>:,... •

4-.fU~

Noncached Read Operations .......... WL.. ~dt: . >UW>Y. .

4-13

~::i~~;!~~~s·s·~~~~~~::::::::::::: ::•~~~:ll!Jti1~.:::i~j'.'

::;:~
4.3.3
4

::~·

Bca~~n~~;~:!!r~t·e· ~~~~~t~~~s. : : : : : . :,,~i:Li~=~~:,. :.' ' .'. : :~i!l !·1;, , :.,.,:,a1!l j\~ : : : :

!=~~
:=~:

4.4.1
4.4.1 .1

Duplicate Tag Store ........... ::~~jj:p~::·:·:'·:·~::::}~:~~[\}fa,,. · >Y:~::~:?~,... . . . . .
Full Duplicate Tag St9re . . .~:&&:\ . . . . . ··:' ' Hlh::::. . . . . . . . . .

4.5.2

Write Invalidate Cache ,Qii.t:r~nc§''llmtpcoi Systems . . . . . . .

4-21

4.5.4
Flush Cache CoheJi.ncy{Jk9tocol Systems . . . . . . . . . . . . . . .
4.5.5
Flush-Based Prq~gfpl Stati:~[M~.chines . . . . . . . . . . . . . . . . . .
4.5.6
Cache ~b~rencytlb.µisactiorNQonflicts . . . . . . . . . . . . . . . . .
4.5.6.1
Case . I ..k:~ .. :··'')l~k::+....... ·. . . . . . . . . . . . . . . . . . . . . . . .
4.5.6.2
C~f:~L~ >'>~tbk; ,,~\f~[:J:::-.. . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Locks Mechadis.ros >~%IL•.... ·.,~.·... . . . . . . . . . . . . . . . . . . . . . . . .

4-24
4-26
4-27
4-27
4-27
4-28

B<;(@.lUf'R$.ii Tranijlction (Private Read Operation)........
W'.ite Pjpjli°n,:\ ... ·.... . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
,. B¢aehe.tWrite·:a&ansaction (Private Write Operation) . . . . . . .

4-30
4-31
4-32

4-15
4-15

!i:· Cac~:f~;o~e;::~::~=~~~~~~~~~~-f~:: :·~·:::::::::: E~!
!:~:;.1

wn~:i:~e~~~:~~~~~~~e~

·:::::::::::: !=~~

.. ·. .

!:~.1 211~!;!;t,~"~~~~.:::::::::::::::::::::::::::

4.7.2
4.7.3
4.7.4
5

:=~:

::~· 1ritl'::I~~:e~p~':s~~ti~~~ :::::::::::::::::::::: ~

.,,::::;J14M. ····:::::ritREAD MISS-No Bcache . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-38

t~f!11w~HJI ,,,,,~~~~~~d:~~~~:::::::::::::::::::::::::::: :: E;
····:::::fl~tl::t::,~Hf~3..
. ,=:::::t4.m..3 .1
. ,'.¥)$.~$.:~2
4.8)iHit>

READ MISS with Victim . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ MISS with Victim (Victim Buffer) . . . . . . . . . . . . .
READ MISS with Victim (Without Victim Buffer) . . . . . .
WRITE BLOCK and WRITE BLOCK LOCK . . . . . . . . . . . . .

4-41
4-42
4-44
4-46

4.8.5
4.8.5.1
4.8.6

1:::~·

SET DIRTY and LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
When to Use a SET DIRTY and LOCK . . . . . . . . . . . . . .
Memory Barrier (MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

/\. 4-48
·:\::::::M. 48
·:::IM50

FET~en. ~~ ~~~ ~-~~-~~~~ ~~~~~-~~~~~~::: :,L~~~;::~t~:::::::t:tmm:::::!~L

I!"i s~i;fi~~~~!!~!~£ii:::: ::::~;$~~;1: ,~1~4tlk Eil11
4.9.2.1

::~:~:~
4.9.2.4

~~=.:~~~~s.e~.t~-~~~-I~~~~~~~ ~~,t:. AfJ~~\}@WJ;'" H4

~dri!r1i
-~~-~~ ~I~~:;1'~~~~-tt1tf~jl~ : ~~
SET SHARED .............. ··:•·:·:• ... ···•:·:·:.:·:·:•···........
4-60

Flush-Based Cache Coherency Protq~~J.:::comm~=ff~i:k:~......
21164 Responses to Flusli~)lased ·PfiiQ~ol Comtrt~nds . . .

4-62

::~~.1 Da~~::i:~~~:i:::.!'1~~1'~~\i:~~k~::::::::::::

::=:

4.9.3
4.9.3.1

1:~:~:~

ii-:~. ::::::::::::::·: :':~:~: :~ : : ~: : :it~. ·: : = :r: : :~: : ~: : ~:< : : : : : : : : : :

4-63

4.10.2

Read/Write Spacing-DQ:~\\\pus C~rl-p#pn . . . . . . . . . . . . . .
1

1:~~:~.1

Tris~~~o;t\VR1T:n:fg~[:fli1:i · :··:~=~=~~:::::==:·::::::::::::::::::::

4.10.5.2

BCAQl,~._vt°'=l~J....to1~~I~,, . . . . . . . . . . . . . . . . . . . . . . .

::~~:~:~

~i~~~:7~;~:.~C:!i1;~~t!I~~e~~ti~~-::::::::::::

:=;~

4.11
21164 lnterfaee.::R.estriitlo.ns. ··::....... . . . . . . . . . . . . . . . . . . . .
4.11.1
FILL Qpif~ti~ns afiM{pther Transactions . . . . . . . . . . . . . . .
4.11.2
Comui4.fld 4.'Jliowledge for WRITE BLOCK Commands . . . .
4.11 .3
Sy~teiU§:. without"\!I:: Bcache . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11.4
WRITEtSE.bCK::LOCK..............................
4.12
2 ll.§~yste:~iPidfo®~:c~nditions . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.~:l?.~mt::::':·. ···:mgi~t for 21164 and System Use of External Interface . . . . .

4-79
4-79
4-79
4-79
4-79
4-80
4-80

4-69

:: ~ ~:! g:ro: :;-~:;!1;:;,;~~ ,~tJii:~ :::' :' : :::::::::::::::: :=;~

A\-~~~:~i!fl• ~ir~n;::~~~a;:!i~i~ ::::::::::::::::::

<iln~;;:4.12.4 ;::::~~l~~l READ MISS with idle_bc_h Asserted Example . . . . . . . . . .
···::::~=~t4M:,2,ifi?:·· READ MISS with Victim Abort Example . . . . . . . . . . . . . . . .

~l~¥1~B.;::..
Bcache Hit Under READ MISS Example . . . . . . . . . . . . . . . .
4.1 ~f\{f~Q~ta Integrity, Bcache Errors, and Command/Address Errors . . .

4.13.1 ··::\~lil=Data ECC and Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.2
·.·Force Correction.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi

:=;;
4-73

!::
4-85
4-86
4-87
4-89
4-89
4-91

Bcache Tag Data Parity ............................ J\
Bcache Tag Control Parity .......................... '}{lll\:.

4.13.3
4.13.4

4-91
4-91

::~H ~!JL:ori:~::~~:~~:i~:::::::::::::::: :~ri:~~1~~)li~~~ltt!~
4.14

Interrupts ...................................~bSJ. . . . . . ... .:·::::::::::4fil~~

!: ~!:~

~:~::~! ~!=:: ~::: ~::~;:ratio~·

:;;,; :':{~-!{@;:_: : ::SJ

5.;~::alI~:;:~~:~e~;;=~~:mt ~d BraQC~~!~2l~l;:tf- ::
0

Istream Translation Buffer Tag Reg!§l~;·:ti~~TAGf<" . . . . . .
Instruction Translation B_µffer ~~g@./l'able Efi(b:::HTB_P'l'E)
Register . . . . . . . . . . . Ffk . . .. "::9:~fal~k::~ . . . . . ~":?. . . . . . . . . .
5.1.3
Instruction Translation BllffermApdre:iij!~§p.~ce Number
(ITB_ASN) Register ...... ~'.?lfat~:. ~ .. ":5Wlk~ ............ .
5.1.4
Instruction Translation ,Dl«~r. Pagi~lW,@le Entry Temporary
(ITB_Pl'E_TEMP) Remit~r":::::~qtt:~.,....."?Tt ............... .
5.1.5
Instruction TranslatiortFBuffer "ffiialidate All Process
(ITB_IAP) Registettfo:l:~m:[j~bL~ . . . . ~:::::y~:.-. . . . . . . . . . . . . . . . . ..
5.1.6
Instruction Tra11~iition Bfit.e.r:. Invalidate All (ITB_IA)
Register{!k~· ... ;:::q~~:jjk:...... ~"::~tt\}>. ..................... .
5.1.7
Instivctioh 'frAJlsfatiijb:::J.;Juffer IS (ITB_IS) Register ...... .
5.1.8
Fonri~~.d FAUJ~j:qg VirtWM. Address (IFAULT_VA_FORM)
Regist~f.:l{fa:b....>J@t:~:·... >?·.......................... .
5.1.9
Virtual PagijMf.~ple "'.B~~ Register (IVPTBR) ............ .
5.1.10
Icach~t:l?:~.~,rjt~/E&lQr Status (ICPERR_STAT) Register ..... .
5.1.11
Ic~~JM:::Flij~) CoiifiPI (IC_FLUSH_CTL) Register ........ .
5.1.12
Ei:i.eptiqi.j}Addtess (EXC_ADDR) Register ............. .
5.1.13
,: . E~¢.~Ptl~h Su#.itnary (EXC_SUM) Register ............. .
5.1.14 .-:. :~~!jl~l:fEx·~~P\\~:~i:LM'=,k (EXC_MASK) Regis~r ............... .
5.1.15 ·{J)(:. PAL Based\ddress (PAL_BASE) Register .............. .
. :::::t:§~:l4.~ ·-":\:t11P.rocessor Status (PS) Register ....................... .
5.1.1
5.1.2

t&J!7';:~:\1
tflttlit1tb~;~J~'
""\fifi~!l.:21

"5N[j~g?...

5.1 ~23,l(
5.1 .24 . .

~~;~:~Si:~~~ g;f;~~s~rR). : : : : : : : : : : : : : : : :
~~~~!.:~!~~~ ~~;~q~~st·R~~~i:e~·cASTRRi:::::

Asynchronous System Trap Enable Register (ASTER) ..... .
Software Interrupt Request Register (SIRR) ............ .
Hardware Interrupt Clear (HWINT_CLR) Register ...... .
Interrupt Summary Register (ISR) ................... .

5-5
5-6
5--8

5-9
5-9

5-9
5-10
5-11
5-12
5-13
5-13
5-14
5-15
5-17
5-18
5-19
5-20
5-23
5-24
5-25
5-26
5-27
5-28
5-29
vii

5.1.25
5.1 .26
5.1 .27

~!:
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10
5.2.11
5.2.12
5.2.13
5.2.14

5.2.15
5.2.16
5.2.17

Serial Line Transmit (SL_XMIT) Register . . . . . . . . . . . . . . .
Serial Line Receive (SL_RCV) Register . . . . . . . . . . . . . . . . .
Performance Counter (PMCTR) Register . . . . . . . . . . . . . . .

~::: b~1~ti~~. Bi&~;~ "cDTB~TAG) &~l~ti~o:·':~~~'" ~~ ififl
Dstream Translation Buffer Page Table Entry JJiTB__lf:'-):~::::::...·:':·. · :·
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . ~~fa~::· i@t . >~~~~F~FV
5-41
Dstream Translation Buffer Page Table Entry Tem.}Wraryjjf
5-43
(DTB_PTE_TEMP) Register ....... ·.Al\~~Mh::,.: ... 3Wb~::::~dl/ ..
Dstream Memory Management Fault $f.(hii{(9.M_STAT)
5-44
5-46
5-47
Formatted Virtual Address (VA_~Q.R.MfRiki~ter ........ .
5-49
Mbox Virtual Page Table Base Reglit*-r. (MViftBR) ....... .
Dcache Parity Error Status ;:(QQ4pERfi!§gf.\Tf Register ... .
5-50
Dstream Translation Buffe.fflhviitdate AIUProcess (DTBIAP)
5-52
Register .......... ~-:::~::::;.\\\~t .... _-·::5H%fab................. .
Dstream Translation Jlijft~ifJpyalidat~\(11 (DTBIA) Register
5-52

::~:; virl~i Md..~~~ <VA\~~~fll1~,~ :::·:'~:~~~ ::::::

D~ir"e~ T;.~~ti~&itf~; =~~~·si~~i~ CDTBiS) .....

~!~:~i&!.;iJ•i:::::::::::::::::::::::

Dcache Mo'd~))lP..C_MQ:Qi) R~ki.ster .................. .
Miss Address. l~il~~J~~od·~~~tfn:AF_MODE) Register ........ .
Dcache Fl~lt..(Dd!i:tb.USH) Register ................. .

Hi~ &.~li'i~~J~T::::~;:::::::::::::::
~:~:~~ sZ~::•·~~~i~~~TI~~~~~rRe~~~~. :::::::
5.~?~~t:::=:::.. ··:"jj~~~he Test Tag Temporary (DC_TEST_TAG_TEMP)

Att~:'"''''{Li:~·~~e· c~~~i (Che;~)· iP& :: :: : :: : :: : :: : :: :: ::

tCii::~;;iJii]i ~~:~:: ~:'!':~~~~s~~ ~:::: ::::::::::::::::::::

5-53
5-54
5-56
5-58
5-60
5-60
5-61
5-62
5-63
5-64
5-66
5-68

5.3."4:~~l[lt\. . Bcache Control (BC_CONTROL) Register .............. .

5-69
5-72
5-75
5-78

5.3.5 ··:::\{@mcache Configuration (BC_CONFIG) Register .......... .
5.3.6
·.· Bcache Tag Address (BC_TAG_ADDR) Register ......... .

5-84
5-88

5:::a~[a)l)[(..

viii

/\.5-31
.\\ljjjj\~t-32
·:::h33

Scache Address (SC_ADDR) Register ................. .

5.3.7
5.3.8
5.3.9
5.4

5.5
5.5.1

5.5.2

External Interface Status (EI_STAT) Register .......... AL
5-90
External Interface Address (El_ADDR) Register ........ 7tIL. 5-93
Fill Syndrome (FILL_SYN) Register .....................\~1lt: 5-94

~~::;::=-:::t~c~~~~:

::::::::::;,~,If'. : ~'.~tm~li!
11

PAL Restrictions-Instruction Definitions ....... -~\MIL~ . . . .

6p:'.~ileg=~~:eh::s::o~i~~~~ -~~~~ ....... J/t;:J~\~!)li\"111'. .
'''"

+lft\~1{};

5-t(JO

¢11
&-1

H ~~~;!eE~::::-t::::::::::: :iJ~:1~t~~;,~~'~\~~~~:::: E
n~ Req~~;~!~ifo~~~~~:~t!~-1~;~,: ~,~~*: ::::::::: E
6.6

il~

6.6.4

Alpha 21164 Implementation of tiiM$.t.~}litectil$ally Reserved
Opcodes Instructions .....,)~#Mk:~... ··:;'\Hllk~. . · . : . · · · · · · · · · · · · ·

=
1!!~!::.;~i4(:~':ii~(~,'.~\~~~~ ~
HW_M.
1

~dq"'t:TP1'\1,~ctions

6-7
6-8

::::::::::::::::

............... .

6-10
6-11
6-11

7 Initialization aqit.~ont'-1:4_ratitiflh:::.
7.1
7 .1 .1

7 .1.2
7 .2
7 .3
7.4
1 .5

1.s

Input Si;~H~lijjj~@ys~dl@1~~J ~~~d::,dc_ok_h and Booting ........ .
Power-U1>""l~~tw.J.relli~$.ts . . . . . . . . . . . . . . . . . . . . . . . . . .. .
Pin S.:t.~~:::witlHit-.~ok:h Not Asserted ................. .

Syscllqpitiff~'~U Detii} ............................... .
Built-1$.. Se~f4J;\~·si{~(f3iSt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S~r.iait~~OfOnlyINJemory Interface Port .................. .

sifiaI W.tl.iinaLPol-t ................................. .

.:::::~diche 1riJHiliiilion .................................. .

1 li!'. lt\11 '~~1~~~~~~~~~~et:Sta~::::::.::::::: . ::.:
1

'".'.j"'')\'~j;~EEE 1149.1

Test Reset ........................... .
Port

7-1

7-6
7-6

7-6
7-6
7-6
7-7
7-7
7-8
7-8

7-9
7-9
7-13

7-13

8 Error Detection and Error Handling
8.1
8.1.1

8.1. 7
8.1.8

Error Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
lcache Data or Tag Parity Error .................... +:::~·:·.·..

Dcache Tag Parity Error ................ @!~; ...jff ::·::JM~k/l:·
lstream Uncorrectable ECC or Data Parity Edits (Qtachill:pi?.

8.1.9

~=:~ U~c~~~t,;b1~ "ECC" ~r· D~~ i·~~;'W~· .

8.1.10
8.1.11
8.1.12
8.1.13
8.1.14

~~:~:: ~ ::~ ~~~;:=~~:;;;;~~-~h;:: :::·:t'.v: : : : : : :
~~:!:: ~:dm~!~~~:s:f~:~!lkh:·:''~!~\?'. ::::::::::
Istream or Dstream Correctibiid.UC.C Erlil.\.(Bcache or
Memory) ............ :...;I~r .. :·:-:>~~i::~h:::~:·-" .· : : · . ....... · · · · · ·

8.1.15
8.1.16
8.1.17
18

or Memory) . . . . . . . . . . . . . . . . . . .·''~·. ~!~f . . . . ··::::Tmt=k~.. . . . . . . .

Fill Timeout (FILL_EJUi.QtflJ:D ........Y{J· ............... .
System Machine Ch~qgr·~ . ··~:===#fat~....................... .
Ibox Timeout::,...... dbl\...... ··==;=::Tb\:,.................... .

~:~· MC::l~o:i: ~~ :ttrt:~~;~~}ffat.: :::'''.:::::::::: ::::::::::

8.3
8.4
8.5

Processor-C~~itQ.pl~·==Eth~r Int'JMktpt Flow (IPL 31) ......... .
MCK_INTERR~:l~tJ~w··===5@!~::b:::.......................... .
System-Corre~.~ble ·EaP.r Int~frupt Flow (IPL 20) .......... .

9 Electrical Data

·\lb1

8-5
8-5
8-6
8-7
8-7
8-8
8-8
8-9
8-9
8-10
8-10
8-10
8-11
8-13
8-14
8-14

tl{W'.::-J11..•,;·wi}f}

9 .1
9 .2

Electii-0al 'Cbaf.acterist.ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
de . Gfi!~act;H~m~wttWF~ ..................... · . · · · · · · · · · ·
9.?~t·.: . ··=====n&W.~r Supply·~· ................................... .

;;ff~%i¥t[·; ~:1ca1~~~-::::::::::::::::::::::::::::::::

.-:Att=9.3
.·:at::=characte.rlstics .................................... .
·=t:~~[l9~~.1 :=:f!JF=.. Clocking Scheme ................................. .
··==9~i:e~2.tt==··
In put Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 .:r=aat:::.,..
Clock Termination and Impedance Levels ........... .
9.3.2 ..2\til:t,.
ac Coupling .................................. .
9.3.3
. ====::::::·Signal Characteristics ............................. .

'il.!:j·~·: =.:.:~.:~:~.: : o:·:·:- 1

9-1
9-2

9-2
9-2

9-2
9-3
9-3
9-4
9-5
9-5
9-6

9.3.4
9.3.4.1
9.3.4.2
9.3.4.3

Backup Cache Loop Timing ......................... j \
9-6
sys_clk-Based Systems .......................... Tlllh.
9-8
Reference Clocks .................................:=\/\,. 9-11
Digital Phase Locked Loop .................. o;:~@k:~%:==·='·· . \ljjjjjjM~-13

!:!:!:i Cloc~~~~1~~D T~s ~

:::.::.,t1v1~~~,l,-~;:I1m1111~~
•r:

~:~:~· 4 Testc6:~fi:;:~e~ ~~~~:::::::::::: ;,1111:I~li&ww,:':
7
9
~:!· Pow~~~~p~~ Jo=::;i~;:'J:n':.:::::: :;;$Jif@j:':: :(ll~~;fJff:::::
~:::~

~::e~p~~;pi; s~~~~~~~~:::: ~;;,,I:':: :':~~1i1:~:':'':':::::::

1O Thermal Management

Al'.f

'tt~-:~\~\\;f> "'

~E~ ::~~?.:~f&~a~:~~~~1;:;1r1~,~ ~: ~ ~ ~:: ~ ~ ~:: ~ ~ ~ ~
10 .3

Thermal Design Co11~!feratio'fiijh+... . . . . . . . . . . . . . . . . . . . . . . .

~=~:
t~~
t~~
10-1
10-1
10-1
10-3
10-4

11 Mechanical D-~~d'~:~!fimag 1,:~:rmation
11 .1
11.2

~~:~:~

Mechani~!1~lll~~£.ifl~it~qn~.. :=·==~{~?. . . . . . . . . . . . . . . . . . . . . . . . . . .

: : : ::: ::: :::: :::: :: :

Signal Descrip'tiij~:~tand4fb1 Assignment .................. .

1~):'1i:''1::·::

11-1
11-3
11-3
11-8

12 TestabiHlY ildllllDiagQ.pstics

12. 1 ·=id'-t Po;i~~~Piii1:mr~1:~'''. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

,:~tjji~jjfltl~~i~l1::: "1ij!~,~~~rt. ~ : ~ : : : : ~ : : ~ : : : : : : : : : : : : : : : : : : : : : : : : : : :

./{:::F~r 12.~;~1,:~\
.:){(:,..
12.2~3'
····=:::~~\\jj~l:::\l:~t::,,.lg~2'~4

s~M~l=·Terminal Port .............................. .

IEEE 1149.1 Test Access Port ....................... .
Test Status Pins .................................. .
··===:tt1~2:~.;3
Serial Instruction Cache Load Operation .................. .
·ya~ltt:=: .. Boundary Scan Register ............................... .
12.!f{f}Timing of Test Features ............................... .
12.5.1 ·.·
Icache BiSt Operation Timing ....................... .

12-1
12-2
12-2
12-3
12-3
12-6
12-7
12-8
12-11
12-12
xi

12.5.2

Automatic SROM Load Timing

A Alpha AXP Instruction Set
A.1
A.1.1
A.1.2
A.2
A.3
A.4

A.5
A.6

A-12

B
··t:::t:\:::::.

: ::~::i::e::pport, Ordering, an4~!,~:Ji;:::~ture
::: E~fJiiZ{Z~;i::;;\~~~~ ~: ~~~7~~~ :~~
0 1

D.3
D.4
D.5

::::a~

Ordering Digjtaf}3emi~ondtii~r. Sampie Kits .............. .
Ordering Ass®.j~te<f't.Umt~l S~-}~nductor Literature ....... .

Ordering AssoE~l}~~-t~'Literature ............... .

:::::::::::::

'1i[j~'1(:,:L ~~~~gf~~;:::::~~~=:~~'. ~O~~: ::::::::::

xii

D-2
D-3

t(~~;t~~'.:J;f!l~fl?

F::;t!]kJl)lt;~~!~.~~~~:~;:::r ~I~~ ~-i~~.
2-6

D-1
D-1
D-2

. ,,\l~::tcacheless Multiprocessor Configuration ................ .

2-3
2-15

2-37
2-39
2-40
2-41

3-1
4-1
4-2
4-3
4-4

4-5
4-6
4-7

Alpha 21164 Microprocessor Logic Symbol .............. .,/\
3-2
Alpha 21164 System/Bcache Interface ................. -:?~lh:.. 4-3
Clock Signals and Functions .....................·~·.·.~ ... \j~lll\. 4-6
Alpha 21164 Uniprocessor Clock ............... l::/:~:f@l~~WM:\::::.:::'.J]l\:4-7
Alpha 21164 Reference Clock for Multiprocessor Sy~lhis . ·:··-:,~=::::f::::ftil!ts

:!:::::::: :!:~!; ~:::!:: ~~;,::::::: ~~,.:·~~~,·~};~:: !t
Full Scache Duplicate Tag Store . . . . . . . ...,~tflF~t~~~l~fft;:,~ . . ·.·>~tt}:Duplicate Tag Store Algorithm .........
,~df~j:{~j~~fjk:<b····.

4-16
4-17

Write Invalidate Protocol _.$yste~As Stat;:Jq~~~~~}b~ . . . . . . . . .
Flush-Based Protocol 21fi~i' Stat~=~tll1~b::)...... ~··:::::=. • • • • • • • • •
Flush-Based Protocol System!fib.~. s~i~fat:L· . . . . . . . . . . . . .

4-24
4-26
4-26

=:~~~~~:~~~~~.::::::::::::::
::=;lt,:~~:.:=~~~~;;)D= ..

:::

!=~! ~l-~~~~e~:~gc~~:::~ ~~ ~h~ ·;1~~~. ::::
!=~ ,h~~J:;:; ~= :s.c~~~ ~~). .::~~ ·i~j{;~~~:=!~fC::~0 Hi~i ::::::::::::::::::
AWyffil~1 "\k~=~o~:;:;:e~ B1::>. : : : : :: :: : :: :: : ::: : :
~''ltt:if{y ~=p:.:~::~~~~~ ~~ ~.

!=:~
~~

READ MISS Completed First-Victim Buffer . . . . . . . . . . . .
READ MISS Second-No Victim Buffer.................
System Command to FILL Example 1..................

4-74
4-75
4-76

4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22

£V...

~!~~:s~!!~:E:~:e~~~~ ~~~;@~\\~::: :~\~~~l~~'.: : Ei~

:::~£~~!~~~~~~~~~'.·~,~··:::::::::::::: ~!
.. . . . . . . . . . .. . . . . . .. . . . . ..

rnawit'.i:::\::~ .. ·-=~\j~fo:t::~ .. ·>ns~
WRITE ]J.J.{ rfihijbg Diagram. . . . . . . . . . . . . . . . . . . . . .

:::::::::::::

··::::::::::~~-

4234.~~jjjl}:·

4-35 · ·

4-43
4-45
4-47

!=:
!=:

:::::::::::::::: !=~!

xiii

4-36
4-37

4-38
4-39
4-40
4-41
4-42
4-43
4-44
5-1
5-2

System Command to FILL Example 2 . . . . . . . . . . . . . . . . . .
FILL to Private Read or Write . . . . . . . . . . . . . . . . . . . . . . . .
READ MISS with Victim Example ....................•...

UTB. .

5-5

~~~~~~: ~:s~:o~. B4ii,~;;J~t$i.:;!!:~~. :::::::

5-7
5-6

5-9

~~~
~~~
~~:

~:~~(~~:!~=~'::=~~~~"!~~-:~~~~~)...
Formatted Faulting V\f.t£'.;1=~AAdress (IFAULT_VA_FORM)

~!:rP~~~e~-~~:!4~BR) (NT_M~d~~o): ::
Virtual P~~. Tabiij~~i~se ftijtfi~t~r (IVPrBR) (NT_Mode=l) ...

~:::ti~:rl!li~~~~:~=;~~~)-~~~~~-::::::
::~~1s~~~e:~;t~.::::::::::::::
~Jtti:I~~!:~) ~~~t~~.: ::::::::::::::

5-16
.,:{!M~ Co~tffil~:~;ti~Pstatus Register (ICSR) ............... .
~i:rtl~\:::.. ·.·Mi~in.µpt Priority Level (IPL) Register ................ .
,,J§Pfa····::::q~ii~: In~~ptJD (INTID) Register ...................... .
. :::Jjf$-19 AI~jf Asynch;'Jhous System Trap Request Register (ASTRR) .... .

't1{1\f;j~\·fY ~=:;::!;~::: ::::er~:i:~ (~~~~:

:::::

s-22~\~jjjj~}\:. Hardware Interrupt Clear (HWINT_CLR) Register ...... .
5-23 ··:::?fj~~~~}Interrupt Summary Register (ISR) ................... .
5-24
Serial Line Transmit (SL_XMIT) Register ............. .

xiv

~!::!~6!i!~::~!;;a~· ~~s~~r· (1IB_(G~·~-:~~Wl ., 4-s:

5-4

5-6

···2

Et~ft;~k~?\I~;:tttt&t~~::~~1:::,: ~~1,
Instruction Translation Buffer Page Tabl~iJ.iptry
P.atii)
Register Write Format ............ j~~~:~~p:;::::~~HI*:\.,.~ . ·51:mmrr-·.. .
Instruction Translation Buffe~ Page .T.J.b~e Entrjtti:f£;P._PI.'E)
Register Read Format . . . . Jlh . . . ·>=N{t~~=!-:·.. . . . . . ··>r'. . . . . . .
Instruction Translation Buffe;:··A44.r~ss ··:spij~J~famber

5-3

/\.. 4-77

·:::\~l!l!ftc78

5-6

5-7
5-8
5-10
5-11
5-11
5-12
5-12
5-13
5-14
5-15
5-17
5-18
5-19
5-20
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-31

5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38

Serial Line Receive (SL_RCV) Register ................ A\
5-32
Performance Counter (PMCTR) Register .............. ·=%jjj!jj~:h: 5-33
Dstream Translation Buffer Address Space Number .·..
·==\I:h.
11

~!~~!:fa::~ B:rlr~; C~..;.~~~ M~d~· cITTB~c• 1tittt%1ti1~a

~EE i~~~~~~~;~ ~;~<~;~~~!~~!~~; :~
Dstream Translation Buffer Page Table Erltbr ~~;ip~-~~f·
(DTB_PTE_TEMP) Register .......... :·=:::=·· . . :J¥ ... &\ ... .

:;~~;::ryz::::;2:~~:~~'.:::

Formatted Virtual Addr~-~k=(y4_FOI,J):)legiste~
(NT_Mode= 1) . . . . . . . . . . :=:y~~@t:~.,... . :·,·==~t}b~==':·~ . . . . . . . . . . . . .
Formatted Virtual Addr~=~::::(yA]~'=l\M) :Ri~ster
(NT_Mode=O) .......d:~FY9Wh~:==·~ .. ··=·~<tb~ ............... .
Mbox Virtual Page ~~ijj~ Bas~=''l'-m§.te;·· (MVPTBR) ....... .
Dcache Parity Errgf~~~Sti\u~. (DC_PERR_STAT) Register ... .
Dstream Transl~tJi~ ButrJf:~jjJ.pyalidate Single (DTBIS)

~ 5i~=:~~-l~-~:r:~>::::::::::::::::::
5-41

Miss Addfi~~:)[il~=::l\{~g~ (MAF_MODE) Register ........ .

~~~~~!t~~~t~:»~~~~r.:::::::::::::::::

5-44
5-45

c;l)e G:@Jhtetj:pontrol (CC_CTL) Register ............. .
/~::::::.D~i~h~)f~st
Control (DC_TEST_CTL) Register ...... .

'fig

,~~ i~l";~~::~~: ~:;~~:-~~T~:~~~G~~P)

..... .

!'J*ijl '"!ff~~~~;i(it~~~~:::::. ::::::::::::::::::::

t®f

S*" :~:;: ~::~:I~~~g5TI~f:;s~; ::::::::::::

'"%\'

5-53. =::\r

Bcache Tag Address (BC_TAG_ADDR) Register ......... .

5-43
5-44
5-46
5-47
5-47
5-49
5-50
5-53
5-54
5-56
5-58
5-60
5-61
5-62
5-63
5-64
5-66
5-69
5-72
5-76
5-78
5-84
5-88

5-54
5-55
5-56
6-1
6-2
6-3

External Interface Status (EI_STAT) Register . . . . . . . . . . .
External Interface Address (EI_ADDR) Register ...... ·..
Fill Syndrome (FILL_SYN) Register ................ ·-·~---~

/L. 5-91

''il;'t.j~.: ._: 9~
~-:·:·.

6-4

9-1
9-2
9-3
9-4
10-1
10-2
11-1
11-2
11-3
12-1
12-2
12-3
12-4
12-5

Tabl~s

~-1
2-2
2-3
2-:1\::::::::::::::.:..

sys_clk System Timing . . . . . . . . . . . . . . . . . . :%~k ..jD/. .. '.~~~~p~~r:·

:::t::~Et~:::: :,: :::~,;,1~~~~~~~1~:~~: '.~f:

9-10
9-13
10-3
10-4
11-2

::E2:i'E~i!ili2~~
!~<:::::: ::::::::
>%f................... .

11-9
12-4
12-5
12-12
12-13
12-14

~;~~l~:::;i~:w· (~~ -;:~1t1;;,::t~~~\l\i;;k,: :::·:: ::::::
~~: :1~:.~ ~=o=:~:w}>~J~t~:~:~~!1?,f].,;:'':::::::::::::
1

Serial ROM:::149ad TiiriiUs\!.......

.:~f_;~ -~:-~ ~-~:.: .: _:·.·. <t : .~ ~- ~-~ .:~_: _: . . ": : : \~j~i: ~:"-'·::t{f
t: : : : .

~~~~.:~:~!tn

........................ .

!:!l'~2;e~'c~~~s· ::::::::::::::::::::::::
~jp~li~~:::di~pl~l-Integer Add ..................... .

. :ftiP:~lin·~~:j~4mP.J.ji~Floating Add .................... .

·:t'-~'ine E~;riiples-Load (Dcache Hit) ................ .

. a#.5::}:\lJlt: Pi~:~lm~. Examples-Load (Dcache Miss) ............... .

1~\~ii,11; r:::~::E::::~~~!~~;~~ ~i;~

:::::::::::::::::

2...:9tf{:t:::... Floating-Point Control Register Bit Descriptions . . . . . . . . . .
3-1 ··::\::\1ttAfpha 21164 Signal Descriptions ..................... .
3-2
··::::;:::'Alpha 21164 Signal Descriptions by Function ........... .

xvi

11-8

xxvi
xxvii

2-14
2-14
2-16
2-16
2-17
2-17
2-20

2-24
2-37
3-3
3-13

4-1
4-2
4-3

~:s~~~~::::~~~ ~-o~~~l.::::::::::::::::::::: :~\%"
1

~~2:~:::;:~~;~t~:1~~~i~~ ~~~L~~: :,:ti~'. ~~~~t~;a~
4412

4-4

4-5
4-6
4-7

Bcache States for Cache Coherency Protocols ... ·=J)~ll!ML. . . . .
Components for 21164 Flush Cache Protocol Sy§:t~m~\~f~~l)~~~b:==···.
Bcache Options ...................... i!!~)!i!F?tk+==~ .. ···:===~Ftk·

4-8

21164-Initiated Interface Commands .... ~ ! ! ~'.'.= .. ·.Jll!~~~~=}tjjl~jl)ktl=·--··.
System-Initiated Interface Commands (Write= Iqjalidaif'='=·=··
Protocol) ........................,~====!'====~=····· ....Ml .../)ff.... .

4-9
4-10

;!!~~~~~:!:i~~ ~~~~~~~;1r.~:{~i'~:~~~~e

4-11
4-12
4-13

21164 Responses on addrj)9es_h<Q\t:9 21164 Cbmmands .. .
21164 Minimum Respons~·=·TI,m~Lto WfileJ.nvalidate Protocol
Commands .............. ·:====JtkL,.... :·===;=~t@t~ ............ .
System-Initiated Interf~¥.IP9.w.~:fiiJ.\~~(fldsh Protocol) .... .

4-14
4-15
4-16
4-17

~~~: :::~::::: ~I!i•t!'ik~~l~~==~~: ::

Minimum 21164 ;ai§'p·~;{~ij)fi.me to Write Invalidate Protocol
Comma~g~~. . . . l)~jjj~j~j~h;. . . . .·-=~\f)ljj)p· · · · · · · · · · · · · · · · · · · · · · ·
Minimu:rif2U~4 Re.ipP::p~e Time to Flush Protocol
Com~mi?.s >N)~)jjjbt:::::... :·==~,=~tqj))lr ......................... .
Data Cln~i\J3it C®t~sporl'dence to CBn ................ .
lnterrupt··=Pfltf:icy L~~~l Effect ....................... .
Ibo~~M~N.P:~t-:. ri"~M~B.~~. a~d PALtemp IPR Encodings ........ .
Gi:~~larliYll!~nt...ffits in ITB_PTE_TEMP Read Format .. .

4-18
4-19
4-20
5-1
5-2

~ t1¥3itC7~s:::te~~:~;: F~~ ~~. : : : : : : : : : : : : : :

5-5

·=:ttll. Ibox. =c&fiti.8P~nd Status Register Fields ............... .

{-1~~'.~~- '{f~!!~i?~~s;gg~~l~:::::::::: ~:: ~:.

';\fill~~,, ~:~~n!::c~~!::e~:~~~!~d~ :::::::::::::::::::
5-1·2::tt>

5-13

:=;

PMCTR Counter Select Options ...................... .
Measurement Mode Control ......................... .

4-f:i.S
4-33

4-35
4-53
4-54
4-55
4-55
4-62
4-63
4-63

4-64
4-64
4-90

4-94
5-2
5-9
5-13
5-15
5-21
5-27
5-28
5-30
5-31
5-32
5-34

5-35
5-36
xvii

&-14

~~~::'.". ~~1'.1~:'. ~~~~e~~~t-~~~~t. ~~~~~ ~~~~~ . . . . . . '~\J;-.w

5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31

Formatted Virtual Address Register Fields ............ ~ .

5-34

Loading .@Pd Lo~Mpg Rrii@.~~~f-Qr External Interface

5-35
5-36
5-37
5-38
6-1
6-2

5-67
5-68
5-70
5-73
5-74
5-77
5-79
5-83

:~:~:: ~nfi~:~c=:~~::::::::::: :::::::: ~~
:~~;':!~1:1Ja~;~,:''.~1'.j: :: :: :: :: : :: : :: : : :: :: : ::

5-91
5-92
5-95
5-99
5-100
6-6
6-7

6-:Y:::::::::::::::::..·.

6-8

7-2 ··==::::~~t~~l~~~~t:Jntemal Processor Register Reset State ................ .
9-1
··=::\~::·Alpha 21164 Absolute Maximum Ratings .............. .

6-9
6-10
6-11
6-12
7-2
7-10
9-1

1•1~~~;~~ ~~~;~~~~~~~~~;;escnp~on:::::::::::
xviii

·::~

CMOS DC Characteristics .......................... d:~\.
9-2
Input Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . ~\lt..
9-6
Bcache Loop Timing ............................·~.·.~ ... ·\~[j:jlll\. 9-6
Output Driver Characteristics . . . . . . . . . . . . . . . . . /::,/::~:i@[[~fa&t:::::,.,:::::~[[:ll\9-7
Alpha 21164 System Clock Output Timing (sysclk=,Ti)l ... ·~···=·~==:::::::t::{ltjij~~9
Alpha 21164 Reference Clock Input Timing ..... ·==Jfalk:. · . . . .
91%11
ref_elk System Timing Stages . . . . . . . . . . . . .·~=':=~= :=~. •• ··=:\Jln::::~:=:·.· .
9+:i1ja

9-2
9-3

9-4
9-5
9-6
9-7

9-8
9-9

~f;::;::o~~::~~~:;~:;r~?::;:~rt!:>i;~:l\:' :::

9-10
9-11
9-12
9-13

Bcache Control Signal Timing ... ~:===~===·· • ···=·~==:=~=====~·..• •• ...:,:,~====~=··· • • • • • •
Test Modes . . . . . . . . . . ...,.: . . ...\:t~!~i!!f . . . _-·==::::::J~~::jl~k:::::: . . . . . . . . .
IEEE 1149.1 Circuit Perf.@nance=:::$:i&.£.ificatioriif:'. . . . . . . . . .

10-1
10-2

~:::~:~~:s a~:a~::~ ~~!\\J;;,::{~;~\1!1': ::::::::::::: ~ ~~

Alphabetic Signal Pin y~i~Mk:~:==·~.. ·:·===~::::nt1k~. . . . . . . . . . . . . . . . .

11-1
12-1
12-2
12-3

12-4
12-5

~~~
~~=:

Mod~ffpr.maNt$.Y:§~e:ntGy¢.les) ...................... .

12-12

:~;e~!~C{~~:i:~m. ~'.~c~. ~~~~·. ~~~......... .
....

Cypl~s) . )~l< ~::::~
5:: ............................... .
1
SOOl\t$i~d .l)ning for Some System Clock Ratios (CPU

12-8

/[}}CY~l~~}.:r .....::£/ ................................... .
A-1 .·::t:J]f Instrif~t.1~ti/Fbrmat and Opcode Notation . . . . . . . . . . . . . . . .
. :::::tfmITft=:·. ··=::=:\rnj:~!:::~.~hitect~re Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

:.~.;_;.:i.·i.•._•.:.l ~:~~~~~l~i;~~;:~Ef:~c~:~:~ : .::. ::::

%c:;;1i1.
M

:1.::

A~ftl:::ljl>
B-1

12-13

S~Qt.JfUit4. rlfl@g:.for Some System Clock Ratios (System

12-7

11-3

~:!;1:1! E'1::!1:d£ • :': ~'l~;!t®i·:·:":::::::::::::::::
:::::;~~&~:~~~t;~~::::::::::::::::::
BiSt ]}:r~ihg:::f9.r. s~iliijj[[§y~tem Clock Ratios, Port

12-6

9-17
9-18
9-19

Opcode Summary ................................. .
Required PALcode Function Codes .................... .
Alpha 21164 Microprocessor Specifications ............. .

12-14
12-14
A-1
A-2
A-7
A-7

A-8
A-9
A-11

A-12
B-2
xix

C-1

Document Revision History ......................... .

/\. C-1

411

tlit'~~·ac;

design~~(2l7~:: use the

reference manual is for system
Conte :pha
microprocessor. , , tflc~::~101ll\\f1;~:~;mw

Audie'::

21164

This reference manual contains the f6:1l~wjng . 'chipwrs and appendixes:

• ~;c::~!r:.troduces the ~r'4~::~~~"~ overview of Alpha
•

AXP

Chapter 2 describes th.~Jjjjp.r hardwl..:,.functions and the internal chip
architecture. It inclu<J.ii'.'i).EHi~Qt:m.ance measurement, coding rules, and
design exampJes. /l]i.
···:::ti{:::t:::.:-.

: ~::::: i~::i~'.~:~i:;:::~:o:::et::::::::~~~ bus
: ~::~~;i~~~it~iE::~::::li~:::s:::::::::::
• ~l$~l{i~:~tn:;,~::~~es involved in, and states after,

~~~SOOL

%{[·-~~~;*b~;~~;i!lli~;;_vides mechanical data and packaging information, including
•·:::::::~:::--chapter 12 describes chip and system testability features.

xxi

: :::: ~ ~::::;:s::::~:i:::::::::::~
•

1
,,\\

;@t\,,,

Appendix D provides phone numbers for support and lists .~iJa~;~::::fi~lbiti!i!i!i!~l::i:\.
publications with order information.
·(}\fL
··.··::\f:t

~e:::::~~::::'1~ ::~:7.s~:s::~:~-~~~
~rmi

n~s

<lt\1]i•L

manual.

'\{~{p

Numbe~~~umbers are decimal unless other.wi~=,~~,1~ere there is ambiguity,
numbers other than decimal are iqm¢i~tl..~itlFW.~::,.name of the base following
the number in parentheses, for exa&iple. li~fi::~(bexf::::::::

Securit~e:~~;holes exist .when um1;:;::!~~~:~ (that is, software running
outside of kernel m<id~) can:·-.:'t\l:l:\.,..
•
•
•

.. \/

Affect the o~t@,t~ori::::b~::~nP~~~f:::Pr~cess without authorization from the
operating systeit~l::::::t:::\::. ··::::::{ll:l:::::::lllt::::.. · : : : :·
Amplify its privileg"EF\lithouf::authorization from the operating system.

Communi~t~1-Jan-~iRif:::·process, either overtly or covertly, without
authoriza;$.pn f~Q.jf tlj~:: operating system.

UNPREDICTAB:te:'lha::~j~:Nol~INED

Through.41.t thi;::::!ifitttl:::::~he terms UNPREDICTABLE and UNDEFINED are
. ::/:kU.iml~. TfMUhmeanings are quite different and must be carefully distinguished .
. /t::iij~::::r:·:·i~:::~lfticul;;;:il:attly privileged software (that is, software running in kernel
:::it?' mo.d:'i):':can trigg~i- UNDEFINED operations. Unprivileged software cannot
··:::::qilt:::::.. trjgger UNDEFINED operations. However, either privileged or unprivileged
··:::::\[jl)::iQfiware can trigger UNPREDICTABLE results or occurrences.

'''htlliJtt\1~'
xx ii

,lft1

UNPREDICTABLE results or occurrences do not disrupt the basic qQ~ration
of the processor. The processor continues to execute instructions in lti.\µormal
manner. In contrast, UNDEFINED operations can halt the processor. :'&t~J;ause
it to lose information.
.): :;:;:t~[~[l l l [:l l:t: ·:=: : '.! :![l ~ i:.
The terms UNPREDICTABLE and UNDEFINED can be fuither descrl1%dfis

lfi;lt;h,

follows:

·q~t•

~i:::~::ences specified as UNPREDI·'~!m~:{Jly from Tt

moment to moment, implementation to imple$.~nta~t~W;:::~~9.Atistruction to
instruction within implementations. Software ·:I.an n$ier ditMhd on results
specified as UNPREDICTABLE.
.:::f:lfttt:.. ~:~It:: :::J~f:
An UNPREDICTABLE result may acqtUfe aHtltb..j~;~f§%~~lue subject to a
few constraints. Such a result may oofr#i arbitri!f&tfunction of the input
operands or of any state infoi$.iation . lliit:::i.s accessili1e to the process in its
current access mode. UNPREDIQf:@LENf~µlts may be unchanged from

....

•

~;!::~:: :a:a!:::~ce lJNP~;~-~t)!:ults may also produce
0

•

exceptions.
..·:·: : : J!!!!: : :-" ··::::ql~~~~l~[[)\.......::::/
An occurrence specifie.df~tFUN.J>REDieTABLE may happen or not based
on an arbitrary choi~~llfilnctidij}y;r.he choice function is subject to the same
constraints ~~A;l.re UitR:BEDICTAQ.PE results and, in particular, must not

~:::::Ai.!1'~~·
re~ults must not depend upon, or be
a function
of memory locations or registers that are
Bf.\t.h~. coriteb.t~.

inaccessible t()°:::tl~g)~µrr~Rt~[:process in the current access mode.

Also, o.p@fit(P,Q§:. thitl[mf.J.Y produce UNPREDICTABLE results must not:

- W:li~ or,,::iib'dfy th:::· contents of memory locations or registers to which
:·. tH~U¢.1Jibfot pf.d~ess in the current access mode does not have access.

sk11'mJl\!l!t~ltite system or any of its components.

. l~!q\fa~xample, a security hole would exist if some UNPREDICTABLE result
deis'ii.d~.d on the value of a register in another process, on the contents
of pr()°~~~or temporary registers left behind by some previously running
process, or on a sequence of actions of different processes.

xx iii

~o:=
specified as UNDEFINED may vary from moment m;~t,
implementation to implementation, and instruction to instruct.i9.:P. withlU\.
to

implementations. The operation may vary in effect from notP.Jng~[]».t::::==·=·:J{\\[\
stopping system operation.
.. ll~f'
··.··=:=:=::=:ftt{\~l\lll~\.

•

UNDEFINED operations may halt the processor or causJ{1ijjl!!~.. lose
··.··==:l~!~!lt,
information. However, UNDEFINED operations must. JM>t catt$1.AJie
·=tffF
processor to hang, that is, reach an unhalted state frtirlI\t:b.i.ch tHit~b.is no ·.··
transition to a normal state in which the machine/~lecutiiHnstructions.

~e~~~~;;:~s:;e~~::~:: software runnin'" reiJ-> may
.:==::~=rttt==:·

:=t::~:tm\:~tf::~t==

Data Fi:~= where is one o(~, 8;ilt':::~~!,_\,efers to a
Ranges=~::::fi:::::filr of ~t~~~::~;~l~ furee periods (... )
INTnn,
nn
4,
data
field of nn contiguous naturally aligrtett ~ytes?~tlf:f.r. exampl~=; INT4 refers to a

and are inclusive. For exampl~~t~~~dt~ge o:fll\J.~gers 0 . . . 4 includes the

~~::: :;e ::~~~=::·a A1::':::!\\m.m ~gle brackets separated by a
1

colon ( : ) and are in~tlisiy~. :F6iWi.1~mple, hits <7 :3> specify an extent of bits
including bits 7 /§k§, 4;==:q~l:::?.· ··==::::{\~It:::::..

ALIGNED and UNALl~::~la\,:. ···:=::nt\~l\lllll\tt:==·· · =:=: :===:

::t!::i::w•C1~-~!~c=~h~~;s~~~!,°sf::. ':d

ALIGNED d~\P.m ~t~\jize:i[g~*N is stored in memory at a byte address that is a
multiple Qf 2*:!N,JBit is$9.P.e that has N low-order zeros. Thus, an ALIGNED
64-byte ~ick ~g_ h~-~tihnemory address that is a multiple of 64.

xx iv

.){:.

This manual contains· illustrations that show the format of various ;1~~ters.
Some registers are followed by a description of each field. The.Ji~lds otk\P.e
register are labeled with either a name or a mnemonic. The Jl~ii.qpt.j9µJitl~ach
field includes the name or mnemonic, the bit extent, and th~[[[iwe. ··.·-:,:::::::\f)l]tf\.
The ''Type" column in the field description includes both tH:ijl!!lttual type of·::£1.i:~:
field, and an optional initialized value, separated from."'Jpe typ~[l:by a commaj:E?
The type denotes the functional operation of the fi~Jdfliu~i:J;na)/Bijb).Jle of ·.··
the values shown in Table 1. If present, the initialit~d v~lU.~tin.dic~tes that
the field is initialized by hardware to the specifiedH~~~lu~f~t ~t~w,flup. If the
initialized value is not present, the field is not initfifiiz.~~f at Pi~er-up.

::t1::::::titi~Jr·

xxv

Table 1 Register Field Type Notation
Notation

Description

A read-to-clear field. The value is written by hardwar.~-::iij~~~~m.¢ilh.

A read-only bit or field. The value may be read by . .Sijfi\v.{lre. It is

;:;~~~1 ::,.~d~n;; ~:! ~~17n:a~~;Q{'ff~1'~t,

written by hardware. Software write operatio:r.Htwe igMfjkl~..
A read-write bit or field. The value may l~t::tiia~~l~:~t_wrl~-llhy
software.
il?
/t==\f~h:-:·. .·:·. ·

A write-zero-to-clear bit. If read operationli:ik-e ·b~~J:!l:i~t~ register,
then the value may be read by software. Ifl.t i~~~j writA~bnly register,
then a read operation by software .rffimii.~. -.an Uli:B.iPICTABLE
result. Software write operationsJ$li' (fcijij~_ th~ftiif'to be cleared by
hardware. Software write oper~ijps of a Pdi.~J~pt modify the state of
the bit.
-4l) ·=====~t::~~:::::~h:::==··
·.:,:===tr
A write-one-to-clear bit. "If l~~ operil.t~~p.s are allowed to the register,
then the value may be read··=hjt~Qftwaii~H!fJt is a write-only register,
then a read operation 9Y.,.~~ftwMff:~)~~turns%m UNPREDICTABLE
result. Software wriW:)}imf..tjons ·O(~~ikJ..cause the bit to be cleared by
hardware. Softwarejjfite 'opif.aj;ions\l.f a 0 do not modify the state of
the bit.
.-:ill~::::::\~==··
·-:·=::\{j~~l~>·
A write-anythii;ti~fo~thmt~gister-tO~clear bit. If read operations are
allowed to th~t.i.iwster;·:thiAJhe value may be read by software. If it
is a .:W:P.te-onlyfr~gister, then@~=· read operation by software returns an
UNPREDIOTABQ!hr..esult. S6ftware write operations of any value to
th..~. regis•h~~uselhiJ~i.t to be cleared by hardware.
A~=~-w~o~l;;~~l~t~~~9.r fi;raf''The value may be written by software
and fEFlhd by . Hijfdware. Read operations by software return an
UNPREfil&l'ABLENfesult.

WOC

WlC

;tlff!~:;~\~d :~:.:: ~;~w~::= ~~e and is used

::::::::::

xxvi

..:::::::::::··

·::::::::::::

\It

·{lf
..

In addition to named fields in registers, other bits of the register ~@;y be
labeled with one of the five symbols listed in Table 2. These symbonfj[ij~note
the type of the unnamed fields in the register.
··=:::li\:.
./\:\:::::=:::::::·:·.. \:th

Table 2 Register Field Notation

}t![i =;.;i_i;.:,_:_l=,;_1.;.: ·:!:i,:.~.=.=.~:f:~-~.: · .: : .:

:·:·.. ·. ·.:::;::::(:@f
·===·.:[:1:1::r·

Notation

Description

IGN

Register bits specified as ignore (IGN) ar~:::UmQreci.\ti~n:,,~tten atUF
are UNPREDICTABLE when read if m~#[9-tlieoo~e spe86~d.

MBZ

RAO
RAZ

SBZ

Register bits specified as MBZ (must 1.:::~erot$:tl~)~~Y.~=·=be filled by
software with a non-zero value. If the=:~p.r.:oc~§jOr en~#Unters a non-zero
value in a field specified as MBZ, an UND$.FINE:Q)>peration may

result.
./JfJi[i~l~lt::::.. 'tiii~ttt{:fiif
Register bits specified as RAQ:[~(tead·~~(i.n~) rehirn a one when read.

Register bits speci~~:~ ~~)3BZ::lit9.Y.:Jd be ze~o) should be filled by
software with a zero valij~btlon~i~~\y;{llues in SBZ fields produce
UNDEFINED resul~~- and·=~i:Y::::Prodifoa· extraneous instruction-issue
delays.
,::f~~~l~if?l~[[[\[h::=:·. .··==t(lll:t:=·

xxvii

.·:·.

A:flJfu{)!t: '.:~ 1~1

f?f:

.····:·::::::tf~:~:~:~:}~:}f:·.

1111:11>.du ctl.'Olh

This chapter provides abrief introduction to the ·~~,,;:~~re, Aj)i
Digital's RISC (reduced instruction set computing) "''ircbitectll:ti: designed for
high performance. The chapter then summ.~f:lij~>t~e s~~mtW'eatures of the
Alpha 21164, a microprocessor that imple$.ihts . 't1\t#\lph]fXXP architecture.
Appendix A provides a list of Alppa AXlMifi~tructiorl~~llt:::For a complete introduction to t~l?AJpJ1~:::~A1J.tJ!:rchite~;~re, refer to the
companion volume, the Alpha Archit~Wt}Jr~. Refi-'ff."f!(;f! Manual.

1.1 The Architecture

s1Wt1ltb \f{{;l?lJ.1 v

architecture.dJ.ll\I~ 64~~{~\\\\i.ad.and

The Alpha AXP
store RISC architecture
designed with particular ~tJP.Hi.~l~ton speJa: multiple instruction issue,
multiple processors, an<lt@ftwar~:::~tij,}gr.ation from many operating systems.
All registers aril~4 l?:!t~:::'{a\\jl®.gth ~:d::lltn operations are performed between
64-bit regist~:~ AlY~~t.ructJ&q~\~re 32 bits in length. Memory operations
are either lo8'.tfl9.J:t~tor~'~~ti:h~ratiofiit All data manipulation is done between

~:~:~.~~t~)!!:::rts the fol offing dam fypes:
•

I~~R=@g:~WW:and if-bit floating-point formats

AMMb;n1t:=~qt!~~:::~ :::::::~!::::::a::ch other only

.:::l\J\F:::-:·:·:·:·::::::~~\\§y:: one. Trtij#,tµction writing to a register or memory location and another

,,,Jl[F:·
ifi~tructiort'Hfa.ding from that register or memory location. This use of
:{[lJ[(:::..
.::Jre~ources makes it easy to build implementations that issue multiple
··::')\\lU[jjjjj\\\\ll\::::!l·!!!'th1structions every CPU cycle.

''"fil\t{ilf'
Preliminary Edition-September 1994 1-1

The 21164 uses a set of subroutines, called privileged architecture librf!ty
code (PALcode), that is specific to a particular Alpha AXP operating sysl~i.@
implementation and hardware platform. These subroutines provide opera:ti@g
system primitives for context switching, interrupts, exceptions, an!.bm~wocyf\:::
management. These subroutines can be invoked by hardware odf!ALifa,.1~1L.
instructions. CALL_PAL instructions use the function field ofA§i instructfoift:::::~~tt:
to vector to a specified subroutine. PALcode is written in staifrlijt~l_machine
·=::{)
code with some implementation-specific extensions to proyjg~ dir~!M!~9.~ess to -tm:t
low-level hardware functions. PALcode supports optim~titiiitfor IliiWple
··
operating systems, flexible memory management imp\i~·ent~#&b.~,,. ~a··

::::~::na::::::u;:::,s byte shiftiPg,,~1~Lnl:normal

64-bit, register-to-register instructions; it does ::~Finil.µ4e si'.$.gJeilibyte load and

A:;::::~tions.

. 1.1.1

ii•h,·-l,\b,""~\1~\1j}'

The basic addressable unit in the Alpha -~:Jtrchltij~\µre is the 8-bit byte.

:;:r::::;:sas::~b~::7:tf!l~.::~lfm~=d physical memory

into
addresses by the memory man~d~nt meeB®.i~m. The 21164 supports a

:;:

1n~:::;::ruT~=\:· t~\::""'.~it\\tw·

1.1.2

Alpha AXP archj~_ct~~e:::mwpo;f:Mf:~m:r integer data types:
·::::::nt::i::::::,,._

Byte

Word

..,,:::::(:::::L::::::,..

··:::'<t~>

l\J~Yt.~ti~...8··~:6ij~jgµo~; bits that start at an addressable byte boundary.
Ji./hytEfli!!$18-bit!Walue. A byte is supported in Alpha AXP architecture
:!IPY th~MiX'f.lk\.CT; MASK, INSERT, and ZAP instructions.
\~~:-~fA:'is 2::iantiguous bytes that start at an arbitrary byte boundary. A
itt ·w;4fg)s a.J@;hit value. A word is supported in Alpha AXP architecture
.·:':·. tl' b§':tliftatTRACT, MASK, and INSERT instructions.

_.,:/f~ID.V~;a~~l!lllllb:::::·:·. A longword is 4 contiguous bytes that start at an arbitrary byte

. /!t:r:=:,:,,,,,:,:::q!lh,

. Alff
. /!{/'

\Il

.JfF

·t{lll~l\t,:. . QY.i,d~ord
··=::\f{:(:tr··
··=·'=(:!{\:\,..

··:·:·:·:·:·:·:·:·:·.

··':'?:f\b.~mndary. A longword is a 32-bit value. A longword is supported in the

. .\i\l@ha AXP architecture by sign-extended load and store instructions
arid by longword arithmetic instructions.

A quadword is 8 contiguous bytes that start at an arbitrary byte
boundary. A quadword is supported in Alpha AXP architecture by load
and store instructions and quadword integer operate instructions.

1-2 Preliminary Edition-September 1994

~~~~~~~~~~~~

Note ~~~~~~~~~~,;~=~~....--~

Alpha AXP implementations impose a significant performance ~~·-ty
when accessing operands that are not naturally aligned. ~@f.~r to tl!~L
Alpha Architecture Reference Manual for details.
.=:::::.::'.' ' f{@1Ht:t::,:;.,. Jll::.
-::::::::::::.illl!lr·

· · : : : ;: : : : :\:rnm~ ~ ~ 1 _;,:'.=:_:_:·_:1_ :_.:~_~_.:
..

•_:.•·.:·_;i
__

:!:!._,:_:.::
__

' '&It]q\%);¥

1.1.3 Floating-Point Data Types

•
•

•
S_floating

.:::tJ::·

. v:;::::oint formats tlitl-f\t\\\{p
:~:::::: ;;#ff1M(~fit,¥,\lt>
1.2 Alpha 2:~fl;~~r:=1~:;;i;~eatures

The 21164 ~I~•9.C~:::~StU~:-.a -~d6~rscalar pipelined processor manufactured
using 0.5 micron. ::Ct\tQ.~ teMi[n9Jogy. It is packaged in a 499-pin IPGA carrier
and has rempy~pJe ~PRli~tioH~specific heat sinks. The 21164 is designed so
that maximlirtf'p~tfprmMii~ is achieved in high-performance systems while
offering cj#ipetid.Y.~· .P.~rl'ormance. A number of configuration options allow its
use in a tib,g~:::afsystihi designs ranging from extremely simple uniprocessor
syst~#.!s W:ifb.ltP.iniII):~ component count to high-performance multiprocessor
sy~P:ims with''¥-lliigh cache and memory bandwidth .

. :::iJ1Hl\MfP.;::::2IltM. can issue four Alpha AXP instructions in a single cycle, thereby
. J:]\\\j:F::.-·

. ,/[\ff..

. . :::::WinimizlHglJJ?:e average cycles per instruction (CPI). A number of low-latency
.a.fid/or high~tilroughput features in the instruction issue unit and the on-chip

·lllt:::·:·.

..:t:]ffimponents of the memory subsystem further reduce the average CPI.
··::=::{\j[\i!:jj~!i:::r::j:!l!~[:'/~e 21164 and associated PALcode implements IEEE single and double
··:::\{]hn~ecision, VAX F_floating and G_floating data types, and supports longword
··:::t•®.~bit) and quadword (64-bit) integers. Byte (8-bit) and word (16-bit) support
is . .provided by byte manipulation instructions. Limited hardware support is

Preliminary Edition-September 1994 1-3

provided for the VAX D_floating data type. Partial hardware implemenw.tion is
provided for the architecturally optional FETCH and FETCH_M instrucfi.l:v.s.

~th: ::::::.::n~~=:~on rate of four times the input cl•'ltf~\Tu\
0
: :eo~:::. ::=d~:a:~ :e::::a:::::::~~=~tion'''Wl!J

buffer, which when used with PAI.code, implementi:H@l[lif.1$;ty of
table ··
structures and translation algorithms. The unit c4.#sists)§.fWit§.~-:~~ilry
data translation buffer (DTB) and a 48-entry instti~tionl::ii-aiiilitibn buffer
(ITB), with each entry able to map a single 8K-byt~::··P¥. or ~~llkroup of 8,
64, or 512 SK-byte pages. The size of each t.tjiiJ~tion :~bff~rl::~ntry's group
is specified by hint bits stored in the entr»lIThe·::»T.i.tar1<Prr'.B implement
7-bit address space numbers (AS~), (~lli~N=12.7Jl1t::-

•
•
•
•

Two on-chip, high-throughput pi~~iil).~~ ~'~N-ig:.:point -~~its, capable of
executing both Digital and IEEE floatiqg~poinl/il!:W. types.
An on-chip, SK-byte virtual instmt.M.9..~··,~:g&ij~~~:wi~~::-·7-bit ASNs (MAX_
ASN=12 7).
.·ljll!!ll:~r·,.·.·.·.:,::t(:l~~~)~~ll~th:::.:-. ··:::=t@?An on-chip, dual-read-por~~P.USK::J:>yte dafaU~ache.
An on-chip write buffer .~J·.·~~,~~:a~ffjyte en~ries.

• :t:~~~· =~~!~~~fu!;~s~:iiltive, write-back, second-level mixed
• !.~:::t da;~t:~t{~!~~i~;~lnty and error correction code
(ECC)

•
•

Support fo_!\Phtlfil:w1ar,.~.mal third-level cache. The size and access time
of the ext~ifial ~b.Wd-!~vefHache is programmable.

An int~Jij}4~JP:il~:::~e~lfator providing a high-speed clock used by the 21164,
and '-~~pair-:::iflPh~~mµgfuable system clocks for use by the CPU module .

.·.-. ~:-:-:·.·. 01f~Wi1 perf~~l~~;·· counters to measure and analyze CPU and system

-:::tl~:::::~rn:~:m:tl~~~<>BH'f: ~.-

,:,t:~1r·

•

Qpip and rrfijaule level test support, including an instruction cache test

fll~}lht@~!~:~::w:::::;l;~~~=~::::::::e~te:-~~gic supported.)

. ,.,\ft~f.t:Jo Chapter 9 for 21164 de and ac electrical characteristics. Refer to
the::'A.lpha Architecture Reference Manual for a description of address space
numbers (ASN s).

1-4 Preliminary Edition-September 1994

Internal Arllb.itectu::re

This chapter provides both an overview of the 2111:~l:,;;::~e and :JF

system designer's view of the 21164 implementatioifo(Alpha:AX.P architecture.
The combination of the 21164 microarchite~tm~mA:n.d pfinl~!t9d architecture
library code (PALcode) defines the chip's ii@plenieh.t#.Mort:Otlhe Alpha AXP
architecture. If a certain piece o(hardw~dK seems fiWim/'architecturally
incomplete," the missing functioriijlity is"Hbfil.~,µiented.ih PALcode. Chapter 6
provides more information on PALco(:gL,,.. '"''tl~~\\,.,.

This chapter describes the major..fµ.p.c;~dHihha;dW~~e units and is not intended
to be a detailed hardware descriptM~tpf thi~tM:p. It is organized as follows:

::~=~==~:i~~~lt1,;;,:~i%>
1

•;

: :::a:d!l~~:t~~~.S~d merging rules
•
•

Mbox store e~·~=~dtiO.n.

"':::':\~~~[~!>

Write trfilfJF:[~~fia t~::~[.B instruction

: Ai~~:~:::;:::pport
'%lt\:t11···

Preliminary Edition-September 1994 2-1

2.1

2-2 Preliminary Edition-September 1994

Figure 2-1 Alpha 21164 Microprocessor Block Diagram

SROM
Interface

Instruction Cache (!cache}
Branch
History Table

Tag

Data

=--i

Instruction
Fetch/Decode
Unit (lbox}

Integer Execution Unit ..
(E_b_o_x_>_ _
Integer
Execution
Unit 1

Integer
Execution
Unit2

Adder

Logic Box

Shifter

Branch/Jump

Instruction
Pre fetcher
lnstructtDf:l.
BuftEff\?

Multiplier

{~ ~ -:~~-.

Instruction

Integer Register File

Adder

i5~: ~:

Data
Cache
(Dcache)

]h Floating-Point Register_F_i-le_ __

Dual-Read
Translation
Buffer

Write
Buffer

Data
Tag

1/0 Control
Board-Level Cache Tag
Board-Level Cache Control
Data
Address
Second-Level Cache (Scache}
Set1
Tag

Data

Set2
Tag

Data

Set3
Tag

Data
LJ-03559-TIO

Preliminary Edition-September 1994 2-3

The Alpha 21164 microprocessor consists of the following internal secti~tn~

•
•

•
•
•

Clock generation logic

1nstE~i~~s~:::::::;;~::::d~:1udes: '*;~(\,\\-;~

::~~~~~;~:i:::~~:OOx>, '1!~!7.)4\W~)
~~!:!~:~~~ti~~~=) (DT~\\; ''~\\th., A(i{l
ij7~~~Z!~;ro1

. , , : \~ji:t: : : j ~= =·

;:::~ :~:~:~:~:~: ::::~:~::=:·:·.

•
•
•

Data cache (Dcache)

: ::::id:::~~=ei~:==~-\:~:~ace
Fetc~<lria:::::~:~a&de. ~,~it

2.1.1 Instruction

The primary fuJt~t.t~.)tl:::Pf lHij\jnt;;~:~tion fetch and decode unit (lbox) is to
manage and t.~l~tie. Ih'.~ituc;.tioififto the Ebox, Mbox, and Fbox. It also manages
the instructidif cachel~fTli~tibox contains
•
•

Prefetehe·l~!ini~jji~stnlion buffer
Insftlltion . =::i~tj~liffiajjjji:~ue logic

.ttipf1f~~,:::~£:~:c~::i:::~;::::s~ogic

kfltdlflxnt logic

fli\@1

"'1:%1\~:tc:~i::::t:on
··::::::::·

2-4 Preliminary Edition-September 1994

logic

2
·1·1·1

•:::::nd:~:::"! :s;~nstructions in parallel

and checks thal\\e

required resources are available for each instruction. The Ibox issue~==~jqbJ.y
the instructions for which all required resources are availab~~~fmh~:::ll?.oii~ft9es
not issue instructions out of order, even if the resources ar~j]ivamlblitf.9.if!i.t:.
later instruction and not for an earlier one.
..:?}{{
··.··:·::::::::~\@:\.

:n °:::s::::~ are available, and multiple issue i~j~t}!~%:~!l\i1 four :41J

instructions are issued.
~~:11~::lr _,;J::!liJ=~~:%:lll~!l::~~tnt> ·.·
If resources are available only for a later instriidiQjifand jpffor an earlier
one, then only the instructions up to the.J~te.~t onell!f.Q.r. wffl~h resources are
available are issued.
. ~::::l!!lll:::~:r:::::?lilltl~ll!!J~::::·:·.·:::tilt:t:::··
The Ibox handles only NATu~iY ALJ.Q:NED group~jj~pf four instructions
(INT16). The Ibox doe~ not advaifoe ¥> a·li~wtgroup or"four instructions until
all instructions in a group are issued~]Jf:..a btitQAA:. to the middle of an INT16
group occurs, then the lbox attempts fifi~§.q.~ thK~~structions from the branch
target to the end of the current461:!9., th:~hl!!it.::_proceeds to the next INT16 of
instructions after all the instr~ioii:~qb~Jpe tifget INT16 are issued. Thus,
achieving maximum issue ~At~faµ1d opfifu'-hperformance requires that code be
be scheduled properly an<UtlUitfQ9.~ting or··:ihteger NOP instructions be used to
fill empty slots in the s@.Muled ifis\m.~tion stream.
•

For more infonrltloq._ o:==~iWil.N.ction··::;~~heduling and issuing, including detailed
rules governi#.g__multip\~)nstfi(itign issue, refer to Section 2.3.
2.1.1.2 Instruction
··:·::::t:!!~llllill~t:k:-.. ····::::tr

P;:iiiatt::.

The Ibox contains ··:iffi![!iib.~tr~~Hbn prefetcher and a four-entry prefetch buffer
called the re.fi1Ub.Uffer."·::::Eith instruction cache (Icache) miss is checked in the
refill buifJti?'"}f tb.i:\i:fefill btifrer contains the instruction data, it fills the Icache
and instrU¢tioq/ijfiff~tI~imultaneously. If the refill buffer does not contain the
nece~~~ryt~tiFa fe~~lj= and a number of prefetches are sent to the Mbox. If
the.~~:Ufeque~df:tw~iwl.FScache hits, it is possible for instruction data to stream
.·.·.·:·:·:·:·:·.. int&!\I~. Ibox afl}iE(rate of one INT16 (four instructions) per cycle. The Ibox
:dlffllHfoou s"li~mµ up to quad-instruction issue from this Scache fill stream, filling the
. fii\:f..
··:::l®..che siihil~eously. The refill buffer holds all returned fill data until the
. /:j}f"
Alita is req.iif.ed by the Ibox pipeline.

·: :\:! l~l~ l :I: ~=: : :·..·:=~J~j~!l[l!~·~ch fill occurs when the instruction buffer stage in the Ibox pipeline requires
···-:::::n\\l~lj~~L:::. a new INT16. The INT16 is written into the Icache and the instruction buffer

····::::::{:)tj,pmltaneously. This can occur at a maximum rate of one Icache fill per cycle.
··::iij~:- actual rate depends on how frequently the instruction buffer stage requires
a new INT16, and on availability of data in the refill buffer.
Preliminary Edition-September 1994 2-5

Once an Icache miss occurs, the Icache enters fill mode. When the leach~
is in fill mode, the refill buffer is checked each cycle to see if it containstfb.~
next INT16 required by the instruction buffer. When the required data i~~:in~.t
available in the refill buffer, the Icache is checked for a hit while.J~)!W:Wt~\l~h:
the arrival of the data from the Scache or beyond. If there is aiti:lca~K~lijltt~ith.
this time, the Icache returns to access mode and the prefetch9.r:~~tops sendirirFl:l::\
fetches to the Mbox. When a new program counter (PC) is loiai~i:Jthat is,
\l}
taken branches), the Icache returns to access mode until the firs.Ftiit&~. The ·<lf
refill buffer receives and holds instruction data from fewb~ianitiatedlttfiefore
·.··

· · ·
2113

::::::::~=ed to access mode.

,, l\%%,fytf''v

When a branch or jump instruction is fetched fr9.lt-:ktb~ Ica~lt~,..Ji¥ lbox needs
one cycle to calculate the target PC before it i~Uf~·a:a~Ut~t.fefMflhe target
instruction stream. In the second cy~le after:4R¢ fetcli~·:::tiji:J~ache is accessed
at the target address. Branch and PQ}precirnt•ih,,. are nece'~:~ary to predict
and begin fetching the target iilstructioQ@~t.~ea1ri\$.).f9re the branch or jump
instruction is issued.
..,,'\[[}[:>;,,..
..,'''\[/[:::::::.

The le ache records the outcome of .;ljt~~\,,,.i~::ifG¢.tj9~:::··in a 2-bit history state
provided for each instruction locati~h in:-=='tnl:::~.~cli.JF This information is used
as the prediction for the next ~~$.;.qtjon of tfM::ittranch instruction. The history
status is not initialized on Ic®,lfo·'·'Rtl~ttb.erefore:. it may "remember" a branch
that was evicted froJ!! the I~be ancf:su~~.quently reloaded.

The 21164 does not.''t~fui~:Jh;:::R·,~r of b;:~ch predictions outstanding to one.
1t predicts branch:~~:-. evetHW:rule -W£l:tY.lg to confirm the prediction of previously
predicted branche.~f:Jl.h~re . :8~\b.e oii~:::branch prediction pending for each of
pipeline stages 3 and?4{ip\µs ufftU.tfour in pipeline stage 2. Refer to Section 2.2
for a description . .Q.f::pipeHf.i~:::~t~gelf
When a pred~ttia''''6;:1:€h:. i~::::{~;hed, the Ebox or Fbox checks the prediction.
The branch li~tory::jihM:::i~ updated accordingly. On branch mispredict, a
mispredi9~::,triiiR9@hrs aqg: the lbox restarts execution from the correct PC.

The 2ul{~ro~d~§t,Htif:·~try subroutine return stack that is controlled by
. ::::::4\~~Q~iiig{ib.~. opcode (BSR, HW_REI and JMP/JSR/RET/JSR_COROUTINE),

J]~ifP:s~:i:!~1C.!~ :~~~~{ i~i~~~~1:~?~s~~:!:~s::e:at
8

.f~H~t;:.

wr~prl around in. . the overflow and underflow cases.

····:::t::~l:I~:~t/EH~:::;1164 uses the Icache index hint in the JMP and JSR instructions to

··'t{~pf~gict the target PC. The Icache index hint in the instruction's displacement
trn1QU3.::.:U.sed to access the direct mapped Icache. The upper bits of the PC
are f&ifued from the data in the Icache tag store at that index. Later in the
pipeline, the PC prediction is checked against the actual PC generated by the

2-6 Preliminary Edition-September 1994

Ebox. A mismatch causes a PC mispredict trap and restart from th~\correct
PC. This is similar to branch prediction.
\~[[~[~))h.

The RET, JSR_COROUTINE, and HW_REI instructions predic.t....the ~:~ltJ>C
using the index from the subroutine return stack. The upp~r,,;~itMhf4h~f[RC
are formed from the data in the Icache tag at that index..J1fi.~se pr.e'dfeii.i.l~t.
are checked against the actual PC in exactly the same wa}.f~Q}~t JMP and..J$.g

predictions are checked.
.. ,.,.,.,.,.,.,.,.,......,,tl1~jj~ll::\..
-t! ! ! !j )~
Changes from PALmode to native mode and vice v~d~F«f:..::::predfotitl on all
PC predictions that use the subroutine return sta~J( In .iUl~,~~'-·· if the PC
prediction is correct, the mode prediction will als&ll[~ c~tfect¥llJP.1;truction
stream (!stream) prefetching is disabled when a P(fprMl.ictiorHis outstanding.

4
·1·1 ·

·:~:~~':n~:=~at~c:-~=:. assotjJ: :::!.:!1!!~slation

fully
buffer
(ITB). The buffer stores recently.fused Isffi.lm addres'~tfranslations and
protection information for pages r~gg frM'il~ bytes to 4M bytes and

;:::d: :~:s::;:7:::~~:::=:rw~t;:pports all four granularity
0

hint bit combinations, permit~@'.g tr~fifi\tlt~on···:t6r up to 512 contiguously
mapped SK-byte pages, us~ru[:ibY singlEPlt:P entry. The operating system,
using PALcode, must ensUf~''ll.fi:ttrirtual addresses can only be mapped
through a single .JTB e:q1I, or sU:pijtp~e mapping at one time. Multiple
simultaneous mapping did[[[~µse UN'DEFINED results.

While not ex@tµti~g/iij))~f~:1l~kthe 43-bit virtual PC is routed to the ITB
each cycle. If'.lh~)p,~ge."'ti'§l~,,. ent}1f (PTE) associated with the PC is cached in
the ITB, the profifoiW.n. bifi~:::(..t\.the page that contains the PC are used by the
Ibox to do t~,~:,Jl.~,~~salYtf..~Ce~'~ checks. If there is an !cache miss and the PC
is cached iriJthtFifill}, th"Efp~ge frame number (PFN) and protection bits for the
page tha#)[i<}ntajg[~?tn~t PC . .are used by the Ibox to do the address translation
and accesimicheils. 'ttl~

Th~ ,!tl6~~~~~~~il~:::ilU~-~ts

.
128 address space numbers (ASNs) (MAX_ASN=127)
..... by:::i'~~s of a·'''7~lHfAsN field in each ITB entry. PALcode, which supports
. ,/lJ[]]~f~tw.rit(foi.e.t.~tions to the architecturally defined TBIAP register, does so by using
. :(\\}?'". ·.·.\tfie hard*ite..:-specific HW_MTPR instruction to write to a specific hardware
. /:\1~?'"
.tl~ster. Tiiii""has the effect of invalidating ITB entries that do not have their

ltltJ;-•t(~: bit set.

Preliminary Edition-September 1994 2-7

The 21164 provides two optional translation extensions called superpag~.
Access to superpages is enabled using ICSR<SPE> and is allowed only -W.b.~~e

:xec~;~~;;,e;;~~;f~;:~:~:~=~ ~~~9~~t::s),';f:~~~il\t
2. This maps the entire physical address space four time~~ll~r to the

·-·-:·:=t{~ll~t

• ::d::: :u:e::;::~~=u:::~ress <29;~t~;~tl;{@ddress z\f
0

bits
bits <29:13>, on a one-to-one basis, and forces phy~l~Kl acUF~§~J~it~·-=<39:30>
to 0 when virtual address bits <42:30> equal 1FF$i~~ 'Q!jJ~ ea;,-liely maps
a 30-bit region of physical address space to a singl(frempn o(il:ihe virtual
address space defined by virtual address bit~J1i~;~_O> #~ttEFSfo.

Access to either superpage mapping is allow~4.!!~~i;··=:~Rq'~J~;=::~:;ing in kernel

4\'} {\'.' \w;_~-~:~-~:~-=,~.=,:_=,:.-,-.,.,. ··:t{}t-{~l~~~lh:=:::..

2.1.1.5 l

mntedrrue.pts

The Ibox exception logic supports thr~~- so-df;$.:::Qf iritihupts:

•

;ff

Hardware interrupts
4 ®M)~~\}1\"°,''\i{\\;;
There are seven level-sensit:h~~~fipardwareFmt.errupt sources supplied by the

rono;::::::~,

it~l:'"%\i-Ot111> , ,

::~::.~~<llt1~:::::::. · : : ql~: t~i: : :l~:~ ~ : : : .

· :-·

sys_mch:eq~ ~ui::::ii::ti:,,, ·-·-=,==: /==-

• :.~::eini:=~}lt~!:e

sourced

interrupts
by the software
interrupt,~'que~.t~~jtim§ter-=tsIRR) (see Section 5.1.22).

•

Asynqiroijiµ~:~i''~~eJ:j!traps (ASTs)

Th~rij~j~re "fJl~;A.s.T.~::ljfbntrolled by the Asynchronous System Trap Request
..... <AS$~) regisU@F'Mid. the Asynchronous System Trap Enable register

.·:=A~}!Jll:@(~TEB):j,~ternal processor registers (IPRs) (see Section 5.1.20 and
. /i)):~rr:--· . . \$g~tion . 51\~IJ.). Most interrupts can be independently masked in on-chip
.-:=:~{}?..
.iihble regi~'U"rs. In addition, AST interrupts are qualified by the current

'~Z!t\\\\l;('~~ssor mode.

2-8 Preliminary Edition-September 1994

Interrupts are masked by the hardware interrupt priority level (IPJil}·egister
(see Section 5.1.18). In addition, AST interrupts are qualified by thtWiY:rrent
processor mode. The serial line interrupt, the internally detected cori®.t~ble
error interrupt, the performance counter interrupts, and irq_U.S.3;Q.?. ati.l:\
all maskable by bits in the Ibox control and status register:{(JCSRY~{$~~~:~:::~it::..
Section 5.1.17). All interrupts are disabled when the proc;~§i9r is exec"i!tHigl\.

·.·:·,·:·:·:·:·~.~.:·:·~.-:·:.:·~.-~.l.:_:_~fl:.~,·-~.':~:

·.·.·.·
..·.J::::::::~:tI:::::i:::::::h
.

PALcode.
2.1.2 Integer
Execution Unit

. .:._:_: _.: _.:'.:·.·:·_:.'._:.·._.:·_.:_:.

~l~J

The integer execution unit (Ebox) contains two 64.ffipit i:n,~gijf}~.~~ution
pipelines, EO and El, which include the following:{{:::: ./ff \@?tW'

• Two adders

~,,

"' (lt;;+1+Tu'

~ ~:~~g;~;~~:~i::~c ~j; '%\~: :.:.!.!.:_:_:_:_:_: : ~\ ¥;
.~::f~~~t~~~I~~~~~=:::::.

The Ebox also includes the 4Qf;hfey;t~Atb.i~·:·:iRmger register file (IRF) that
contains the 32 integer refil.~t:f~. definea:::ijy4he Alpha AXP architecture and 8
PAL shadow registers. T"Q~{f~:gl~it.r. file ha~::"four read ports and two write ports
which provide operands,:::M:l:~oth irit~kf.r execution pipelines and accept results
from both pipes/}fhe reg\~r. file alstPaccepts load instruction results (memory

2.1.3

F::~::.::~ti~C;!if
pipeiifiittftpatirij~point

The on-chip,
unit (FPU) can execute both IEEE and
VAX floatiq.gfpijh\t::Jnstf.®.M~ms. The 21164 supports IEEE S_floating and
T_floating¥fata typ~fs,:. an(Fill rounding modes. It also supports VAX F_floating
and G_flqj,\:ing4{~t·a ·f.&pes, and provides limited support for the D_floating
format... Tiii~::FPU cori&ins:

A@-~!§i~t,;~S~~~=:g::~::~~st&

file.

t\~l\\!i>&:ff0 ~~~~~~~:!;';g~::~:~~~n:ip~:efl~:::g~~~i;~:~::~.unit
9

is associated

":::::;::tll!~~t:~Qlie FPU can accept two instructions every cycle, with the exception of floating...:::::p;iJ1t divide instructions. The result latency for nondivide, floating-point
in.structions is four cycles.
Preliminary Edition-September 1994 2-9

The floating-point register file (FRF) has five read ports and four write _p9rts.
Four of the read ports are used by the two pipelines to source operands5tJJie
remaining read port is used by floating-point stores. Two of the write po~lt.
are used to write results from the two pipelines. The other two wclY.t:P:9..rts::::~~

2"1"4M~:=~=~~~~::=::::~~:~u~:~x) conWns fur~~\::::~l\l\~\t

~e;:;~;i~r;~;;:~:~a:~::int 1ols£!,!~~;~~:::\md

floating-point fills from the Cbox, m~jng ceiMip. that oiilJt~ne register is
written per fill port in each cycle. Flhati:qg-ptiiitj49_ads tpatTconflict with Cbox
fills for use of these write ports are forceq}t&. mis¥:[~k::t.he Dcache so that the
Cbox fill can occur.
..:::::::?t=:::::.... ··:::::::\~~~:~llt::t::::,.. .·.'\{f>
The Mbox receives up to two virtu.;t.Uaddi~~~es ·evijey cycle from the Ebox. The
translation buffer generates the .~4rresporilUtUtPhy.sical addresses and access
control information for each vidi!U~(ldress."···::Th'e 21164 implements a 43-bit
virtual address and a 40-bit .P.lJ.ysidl'.U4.gg_ress.

2 ~~ !:~:::'.:~:~::~·~::~:rted trmslation buffer (IYrB)
1

.1.4.

data
stores recently u~ighj~ta . 'stf~~Jll Cilstfeam) page table entries (PI'Es). Each
entry supports all £Hiij:::m;~urdilfi$y hint-bit combinations, which permits
translation for up to 5i2(~~ntigliffiisly mapped, SK-byte pages, using a single
DTB entry. TlwtJfaq~}@:tioii\ij9.tfer uses a not-last-used replacement algorithm.

For load and :lil~re id~~~m,io~::: and other Mbox instructions requiring address
translatiop, th~::,.~tf.~tive WW-bit virtual address is presented to the DTB. If
the PI'E ~:if::th~:~::$.Ujp_li~-~kvil-tual address is cached in the DTB, the page frame
numb~:6{E;FN) ailiPP.f.St~ction bits for the page that contains the address are
. ,:/t~OO.. b}/\ij~:)~box to complete the address translation and access checks .

. Jt~l)l:f~r:;~~l~lli\r;rB ;}~g~~ti@pports the register-enabled superpage extensions. The DTB
. :ilt:r·· suptfpage map~:::provide virtual-to-physical address translation for two regions

<t{f{{'\1~1r

virtual address space.

' 'Z4t--f.,
2-10 Preliminary Edition-September 1994

PALcode fills and maintains the DTB. The operating system, using J~~code,
must ensure that virtual addresses be mapped either through a sinm~~JJTB
entry or through superpage mapping. Multiple simultaneous mappingifo~
cause UNDEFINED results. The only exception to this rule is/lb@tJ~:rie''~ti.ttual
page may be mapped twice with identical data in two differ~ht.'iYrBl~tttdi.$.:~
This occurs in operating systems, such as OpenVMS, whi.Qb}i;tilize vi~trlhllyj~\.
accessible page tables. If the level 1 page table is accessel.ftfttµally, PALcod~}
loads the translation information twice; once in the d<n.ible-mli$1~dler, andJf
once in the primary handler. The PrE mapping th~tJ~~~ll!::.pag~=~~~le must·.··
remain constant during accesses to this page to m.@f"thi~l¥i§ajr~µlent.

42
·1 · ·

~a: :~:::s8=e :e:::nA:::: ~~~~~~:~o,{~l:~::ting the
1

virtual address and by accessing the·data,:~-~h~::~=tt.l~a.cli~)}Jfranslation and
Dcache tag read operations occur .in par~Ui.1.. If the:::~il.i.n~ssed location is found
in the Dcache (a hit), then the d8:bt fron{l)i.(iJ)cache i~'=~formatted and written
to either the integer register file (IR@H?.! flaitjpg~point register file (FRF). The
formatting required depends on the :Pif:m~µlar . lH.i.'d:· instruction executed. If
the data is not found in the Dc~~h~t(~ n:lii~}bt.J.ien·::the address, target register
number, and formatting info~ltfofHQ;'bt.ent~f~ in the miss address file (MAF).

The MAF performs a load-mmflpg f~~B~#.~~::· ~en a load miss occurs, each
MAF entry is checked to $.i~::Tr:lt~~~mlQ.tains ~i" load miss that addresses the same
Dcache (32-byte)J>lock. ,,:tf~it does;=·::M!~k~.ertain merging rules are satisfied, then
the new load mi~iNs merg~ltw.ith an. \~~Hsting MAF entry. This allows the Mbox
to service two..,.or modbload . :tffii:ses with one data fill from the Cbox.
There are s~~~~~. ~~fM~$.~~:for. :i~la misses and four more for lbox instruction
fetches and pref~t~¥!~~·. L~iidjj~~filisses are usually the highest Mbox priority.

:4~:)\,:;~}~ti:nal information on load-merging rules.

• • • ::
2143

The Q~.~cn~tfgl}ows ajfrite-through protocol. During store execution, the Mbox
checlfi~lo s:~~Ut:d.a.t~d~ in the Dcache. If there is data in the cache, then the
Dc(~H~: is updatmfP'Regardless of the Dcache state, the Mbox forwards the data

&")tff\ff,'}~~!'1~::
~:ti:::s~::::c::: :~~ store instruction in the
. ::mpeline crea'.tes a conflict if both the load and store operations access the
0

::f~t?:'
. :::\~l~lll~t:..

,,:Jll9fo.me memory location. (The store instruction has not yet updated the location

. :::::'t]tfIV:" when the load instruction reads it.) This conflict is handled by forcing the load
·-.::t{]~~j\j.pstruction to replay trap; that is, the lbox flushes the pipeline and restarts

. . :\ei'.t~ution from the load instruction. By the time the load instruction arrives
··::::::::·

Preliminary Edition-September 1994 2-11

at the Dcache the second time, the conflicting store instruction has writW.P the
Dcache and the load instruction is executed normally.
.,=t:Jh.

Replay traps can be avoided by scheduling the load instruction to i§!.§.~e t~fi~,,.
cycles after the store instruction. If the load instruction is scheqy)~a:::tPti~~P:~l\
two cycles after the store instruction, then it will be issue-stall..~~Utor oii.t?EJil~E~\,.

44
·1 · ·

20105

~~e==~ontains

e~,,~te

a write buffer that has six 32-byte
buffer provides a finite, high-bandwidth resource for r~ji\HWB.:::~tpre cUii.k to
minimize the number of CPU stall cycles. The write liiffer ,@a~::@,~,~jated

a::and

c:~ i~::~n ~::::~~:::~~ ·

\}''

,,:19

c~~t\ry

(Ch(>,;:!~ft.11

The cache control
bus interface unit
accesses sent
by the Mbox and implements all me.@9:ry-re:Jij;mij externaPiP:terface functions,
particularly the coherence protocol fllrictipps fotlW:iite-back caching. It controls
the second-level cache (Scache) and the bp\jQ.pal tMt\td.::Jevel backup cache
(Bcache). The Cbox handles all instr.µ,£t~on. ''&hftmrim'~cy Dcache read misses,
performs the function of writing d~fiiltii.JR. the.''\vft.te buffer into the shared
coherent memory subsystem, and tt~s a rihiJ.@:r,):·ole':''in executing the Alpha AXP
memory barrier instruction. 'lb~:Jllw.x also E&aJi-ols the 128-bit bidirectional
data bus, address bus, and IIQr'cori~lk,. Chapter 4 describes the external

4}j'*);, '%\-!'

interface.

2.1.6 Cache Organiz.@tion -<:)~:::::,..

··:·:::::::?:::::.,..

The 21164 has thf~:)~p-~}iij:~:®.~h·:=~~{t:§ primary data cache (Dcache), a primary
instruction cache (Ici~ij~),. andq~}~cond-level data and instruction cache
(Scache). All mew,9;ry c.e'li~UB. th({hn-chip caches are fully static, 6-transistor,
CMOS structj,.~~r=~::n:'.!![!!!!~[}'· .·'.·. ·.·.,,,,~l\J:·
The 21164 aljq prqynles·:J~ptrol for an optional board-level, external cache
(Bcache) ;:~: i: ~ : :

·: : :~[![!1! 1~: :~[:! !:·! i': =:,· · .....,: :~ : Ii ·! !:~:

2 1

· ·~::1•*i•7~\f~;;;~~~r:~~~7i:!r:,~!~:;:~~~~;Z! :!h~th

ij•t;~~:\\:t~ block8:''%)'

2-12 Preliminary Edition-September 1994

62
"1" "

•:::::::~ache (Icache) is an SK-byte, virtual, direct-mapped\~he.
Each block tag contains:

• !.:h~:!::!.:ess space number
•
•

..:}::::::::.:·.·.

(ASN)

\:~~]\,

·:·:·:·:·:·:·.

field as defined :;~flt~-,i@L

A 1-bit address space match (ASM) field as defined by···:tli~h~lpha AXP \ft
architecture
.·=·==:=:=:=:=:=:·. ··==:::0::::~~~[~!!::1::tt:=·
·<ll
A 1-bit PALcode (physically addressed) indicatQt:!:[~lfI\::::'.!!!!!!~!It:::::::..
· =:=·

~!:~~· rather than Icache hardware, maintain~lcac:~~r~ with
2153
· · ·

~:!~:;~~~~~he (Scache) i§ a96~'.i~:!J\\t.associative, physical,

write-back, write-allocate cache ~th 32- ·lffffi4::-byte blocks. It is a mixed data
and instruction cache. The Scache i81~li.J:Uy i)iji.ljp~d; it processes read and
write operations at the rate of one INTifttl?:~r ci.y:=·cycle and can alternate
between read and write accesse,~tfiith~mfBU.bble cycles.
If configured to 32 bytes, the S,j:;h=:::~{il~~~~tg;:~~~d as three sets of 512 blocks,
with each block divided inyf~iW.~t.~2-byte':':~:qbblocks. Otherwise the Scache is

2154
· · ·

;::~~;~::::1~::~::onal, external, dire~map~d, physical,
write-back, ww~~llo.~it~b~.~ch~'\fith 32- or 64-byte blocks. The 21164 supports
board-level cacii~t~!~~.s or=:ii:e,.:,. 4, 8, 16, 32, and 64 megabytes.

2.1. 7 Serial Rea~~Qnl~''.'''llino.~n:=~terface
The seriall:tt;a::·~#.jy' me~afy (SROM) interface provides the initialization data
load path~[l~ft~n~d¥'sys'P.i SROM to the Icache. Chapter 7 provides information
abouMthe.''S.RO:M: inteitace.

2~,aj1ije.;1'~0~:~~~1~=~ion

. J:~ll~!jff='·=······. .====::::lbe 2!i~illlfi~~ a 7-stage (or 7-cycle) pipeline for integer operate and memory
. ,:/l]t=··
Jfiference instructions, and a 9-stage pipeline for floating-point operate
·====ttit:::::::,.. .,::dllllilstructions. The lbox maintains state for all pipeline stages to track
···:::;::{[f~lfi~lr·outstanding register write operations.

' W%\{\\\y
Preliminary Edition-September 1994 2-13

Figure 2-2 shows the integer operate, memory reference, and floating-p9,.j,pt
operate pipelines for the lbox, FPU, Ebox, and Mbox. The first four sta~~)ire
executed in the lbox. Remaining stages are executed by the Ebox, Fbox, iqlg.;K,
and Cbox. There are bypass paths that allow the result of one ins.#m~t.iR!l tqU~~
used as a source operand of a following instruction before it is ~tt~H=:ta~~f.l!~~l~I::::..
register file.
<it~~;[!!!!!!!i::..
.····:·:::::t::t~[t!!~jj~~~h
Tables 2-1, 2-2, 2-3, 2-4, 2-5, and 2-6 provide examples of evetilMit various )ll

::s2:1Pi:::.::

:::::~:::cution.

Pipeline Stage

Events

Access Icach e tag and data.

-:=::::::::::::::::~::::::=:::=:=:=:·~·.

/JV. ··::::::k{\::..

··===t~;~f JI~f~::=:··

Buffer four instructioqs, check:::(~\. branch~:~~ll~l~ajculate branch
displacements, and ch®k for I&jfi~)rit.
···:::;:::
Slot-swap instructions·.·ar~Q.. so·.:,fhiJh~;re headed for. pipelines
capable of executing them ....Sf#.lt_precedl#g stages if all instructions
in this stage cannotJ~~Wt~imiilijjb.~.~usly because of function unit
conflicts.
{[j~}:::::::::::::=:::tlth:::::.. ·.·.\flt?
Check the oper~pJJiLof each:lijitf:P.ction to see that the source is
valid and availaNitand that no'\#ite-write hazards exist. Read the
IRF. Stall pr~~filti:g'':i. .~s if any instruction cannot be issued. All
sour~e ope~p~ must li(iY.¢lable at the end of this stage for the
insduction lO.Hisue.
..,.\}'.

1
2

····:::--

Table 2-2

ifl:)%;,;:\j; '~r

.·.

···::::::::::::::::::..

Pipel~,~=~~!\~ Add
··:·:·:·:·:·:·:·:·.

Pipeline Stage
4

5
6

2-14 Preliminary Edition-September 1994

··:·:·:·:·:·:·:·:·.

Figure 2-2 Instruction Pipeline Stages

Instruction Cache Read
Instruction Buffer, Branch Decode,
Determine Next PC
Slot by Function Unit

:::J:l::!f!P

-10.._c....,.-1~---s2._L.._-~._c...,.._4_1n

...te_g-:-r"""R""'e_g6-is-ter

Integer
Operate
Pipeline

First Integer
Operate Stage

gQ.:ffip.~re instaj~U~ns ..~plete in pipeline
,:/~~jg~::~J~-cycf~::!~'@.9y). C-MOV completes
J:fin stag'f:::~d?.-cycte::tafency). IMULL has
,:::.Ji an 8- or'9'~ey~~~ latency.
-: :t:tt:A DependetitQ.:MOV or BR Can
··::::::::trn~~ue in Parall~l" (O-Cycle Latency) with a

If Needed, Second Integer ------,~··:·~·~
Operate Stage
·\:@J
Write Integer Register File _ _ _ ____.,..::-.::::::;,;,.:·.,,...
..

··::::::~~~~~~~t~~~::::::..

FloatingPoint
Pipeline

IC
0

IB
1

SL
2

··:::t~M~f:t~r Logical rnstruction.

··=:::~t~~~~t~~~:::::·

AC
3

Floating-Point Register
File Access
First Floating-Point
Operate Stag~:::::..
Last Floating~#int
Operate ~J~ge
Write F1riltllisi::Point
Register Fil~\{/\:.:·.

··:::'t:J\~lt::::::.
Memory
Reference
Pipeline
Dcache:..

Real!l~P.~f.i~~::::B~Jll --___.

ocac;~i.ii[~~ad··:al~,~~~,::§m.j~:::: _ _ _ _ _......

{l11t!:~1;f]f\l::J~~!~~~~-D-B-~t_;_m_s

_ _ _ _ _ _ ____,

··::::t::::[[~j~[l::::f\~j[l\}::::·Fill Dcache

····:::lFl:\.use Scache Data
· : ;: (\ \: ~: : :~: : : : :·

LJ-03560· TIO

Preliminary Edition-September 1994 2-15

Table 2-3 Pipeline Examples-Floating Add
Pipeline Stage

Events

5
6
7

8
9

;:::::::::::::::=·=::::::::::::::::::::..

Table 2-4 Pipeline

··=:::~:~~~~~~~~~t~~=r=··

Exampl~oa~!;1pca~t;t) "'11\,\k

Pipeline Stage

Events

Calculate the effective add;~:~i~lB..~gin. 'tH~l"Dcache data and tag store

:::·the Dcache\''\"')~\~3''access.
in anticipatio~;(pNti~~ble missY'

Dcache

Derect
hit.
Format the da~::~~~~j;'equired-:"\$.t'.~~he arbitration defaults to pipe EO
Write the JRE[~[~r FRr~~~~~~~ is available for use by an operate

ful\fWon in"''flij![[fl:cle.

2-16 Preliminary Edition-September 1994

·.''\{[t

Table 2-5 Pipeline Examples-Load (Dcache Miss)
Pipeline Stage

Events

Calculate the effective address. Begin the Dcacl).~:::fi~H~~4. t~t\~tore

:::·the Dcache arid sOOre aceess,jtitt ;::!:~11L

data
tag
Scache arbitration defaults to pipe EO in antiCip@.~jpn of a possibHfl
miss. A load in pipe El would be delay~-~L~~ leasf@~~:-.more cycl~F:T
because default arbitration speculativ~J.yf~l.~t~ EO~. '\(}:\.
·
Begin Scache tag read.
j~~::::::r.... _:;;:::::f~~ttt:::::

Finish Scache tag read. Begin detec$ijg $~l~he

. . .: : :·.· : : : :.

Finish detecting Scache hit. ij~m~tJ~lc~es&..th~:{~brrect Scache data
bank. (Bcache index at interf.ieif?:U.~che. :a~~fbegins.)
Finish the Scache data b~qj:~1~ccess·::::;:B~:~t.s~~ding fill data from the
Scache.
ilf' ·::=ttt::t:b::..
··::::qp:·
Finish sending fill. da,t~Jrom . th~fS.~ache. Begin Dcache fill. Format
the data as required. ··::::t{Ih:::.. .··:::f:J:\:::::.

8
9

:::~.t~~,i~~~~=:u:c::~:gi:::e~e.

.;.: : : : : : : : : : : .

Table 2-6 Pipeli!:'E!

$.W:Fr.

··=·==tt~~}::-

Ex~~Jpcache Hit)

'{E\:::::. Cal~tlliw. th~·::-~¢.tive address. Begin the Dcache tag store access.

···::t:::~~~mnJsh··:itti~~~b.f;~ch;:::~ store access. Detect Dcache hit. Send store to

thefwri~e bul(~ simultaneously.

. ::tdflfJWri~::::t~itP..c~he data store if hit (write begins this cycle).

:::::::::::····

··.··=::::::::::::?

···=:::::::::·

2.2.1 PipeliQe

L9'! ~;1 Instruction Issue

Th~,. ~fl64':~11im~JJttldes instruction processing into four static and a number
..... or-tly:d~:µ1ic stag@'%t execution. The first four stages consist of the instruction

A@YP111~(1£~~~~~i:to!:c;:,:~ ~~=~:~ ::ec~=el::u:e8s~~~s:U~~~:c

. ){}?.

tl~~~b::::::.:..

Jytles whiie'\~aiting for a resource or stalling for other reasons. Dynamic
..::::::N~iages (Ebox and Fbox) always advance state and are unaffected by any stall in

··:·:::(::f\}t(:~[{f'the pipeline. A pipeline stall may occur while zero instructions issue, or while

. ::::\%}\':::. some instructions of a set of four issue and the others are held at the issue
"·:::l{~i~ge. A pipeline stall implies that a valid instruction is (or instructions are)
ptisented to be issued but cannot proceed.

Preliminary Edition-September 1994 2-17

Upon satisfying all issue requirements, instructions are issued into th~i.\
slotted pipeline. After issuing, instructions cannot stall in a subsequeri=iftL.
pipeline stage. The issue stage is responsible for ensuring that all resou~i\.
conflicts are resolved before an instruction is allowed to continue ../W:b.~=:=:9~1§{:~k::

==~i:~~~P~~;j~~~~::;e::: :~si~~~!8f: :~;;,,:g,:~·},lk

2"2"2A::::::=::::~snumber of causes. gener''.e~;:~~:uped i•
1n

into two classes, exceptions (including interrupts) and{h()n~*-Eeptjifii/ The
difference between the two is that exceptions reqaj:re tha~:jlie p41¢line be
drained of all outstanding instructions before ~~§tiftiqg tiU.hP:it@line at
a redirected address. In either case, the pipelUle nilii\ttu1 fiU'.shed of all
instructions that were fetched subseqµent W:ii:tJi~ instrU:ai~~=-that caused the
abort condition (arithmetic exceptio:tMfar~ an:==:=~i'-~ption to this rule). This
includes aborting some instructions of a'lftP.Jtipl~~l~~~:~M~d set in the case of an
abort condition on the one instruction in tifrl:$et.. .. \f{>

The nonexception case does not n~~{i:~i~fgl::a.t.m~==:=fh~b).ipeline of all outstanding
instructions ahead of the aborti~gjj¥1structU.mh:.The pipeline can be restarted
immediately at a redirected a49.:ri§~~=·=·· Exampli$='· of nonexception abort
conditions are branch mispr~d~~tiolHWll$.-u.Proutine call/return mispredictions,
and replay traps. P;!!.~ cacnfiahJsses c·~fi.Hlij~use aborts or issue stalls depending

;::: :::~::-~~!::;r,t~::;~ ~'arithmetic exception, the processor

aborts all instructiBHJki~.sued?iw.w.r tli'e exceptional instruction as described in
the preceding paragraph~~~:::::Pue=::Qfjj:the nature of some exception conditions, this
may occur as l~~~l@f:tt.be ·1H\~g~.! register file (IRF) write cycle. In the case of
an arithmetic~/~iEei>lii.#~ the··=·p.:tbcessor may execute instructions issued after
the exception:iJ ins.t.6ifti4.h:~

After abqttind~l!!thilll~ddi:J.~i of the exceptional instruction or the immediately
subseqµ@.~ inst~it.t.#~tklatched in the EXC_ADDR internal processor
.·.·=====r~gjsteF~:ftpJ.t). In tlie... case of an arithmetic exception, EXC_ADDR contains

3fjJJfi:;11d:!!1\t :~:i::eifa:e::~ti~:::c:!:t!:t::::e:ie:'e~~d.

===lit=·

Fo~\~~chine ch~bk and interrupts, EXC_ADDR points to the instruction
··====tt~:l:t:':·. i:gt.fii~diately following the last instruction executed. For the remaining cases,

··==:\lll:$ltC_ADDR points to the exceptional instruction; where in all cases its
···=:::i*-~~µtion should naturally restart.
····::\{llll}=·

2-18 Preliminary Edition-September 1994

When the pipeline is fully drained, the processor begins instructionJ~~ecution
at the address given by the PALcode dispatch. The pipeline is drain~~Uwhen all
outstanding write operations to both the IRF and FRF have completet\Ju:id all
outstanding instructions have passed the point in the pipeline{~µ~lt:thJt~i~tpey
are guaranteed to complete without an exception in the abs4lee·'·:br::im:m~¢htne
check.
·: : i:t[~!I! ! !;: .
··.··:·::::::::::::::::::::::::!:ij:[:::::.
Replay traps are aborts that occur when an instruction reqllifli:. a resource )\l
that is not available at some point in the pipeline. Tb.:i$.~t:,~re ··a;~UY Mbo:X:\J'
resources whose availability could not be anticipat¢.id.>icffiitlwly at)];sue
time (refer to Section 2.4). If the necessary resou:i~¢ is µ,:~f':K~M!@le when
the instruction requires it, the instruction is abort'd ~a·· thellHHx begins
fetching at exactly that instruction, thereby . rnPl~ying ~t.l\~ iQ~thiction in the
pipeline. A slight variation on this is the l4.#dtfiih~:::and~U$.t:¥eplay trap in
which an operate instruction is issued ju§.~i~i~s a :DMi~b~thit is being evaluated
to determine if one of the instrw~ti9n's oP.iBµids is vdM&~ If the result is a
Dcache miss, then the operate in-S:thi,£t.~on ·Ist@P.prted and replayed.

2"2"3N:~:s:: ;~~~!!~:~~or non·l·;~~-1••;:: first is pipeline stal
··::::~~~~~~~~~~1~~~~~::::. ·.

··~·::::~;~~~~~~~~~~~~~~::::·:·.

a
wherein a valid instruction od$.~t of iHi.ftµ~tions are prepared to issue but
cannot due to a resource ~9.Emt:Cregisteit@inflict or function unit conflict).
These types of nonissue ~yt,fos dill~. minimized through code scheduling.

The second type{if.noni';il.:::J.~ondi~~:~Hi%onsists of pipeline bubbles where there
is no valid i~§,tnic.tiqbjp. tli~t:~p}p~line to issue. Pipeline bubbles result from
the abort corlt.iti9ns ··a~~¢.rjpecfln1tlie previous section. In addition, a single
pipeline bubbl(?i$,~i~P.r~du8&}})yperi.ever a branch type instruction is predicted to
be taken, includiniF~vfpr.outih'i}calls and returns.
Pipeline bµi,bl~it*-t~ ·;!:aG~d directly by the instruction buffer hardware and
through Qijbble ~QU~.$.b.ing:::··but can also be effectively minimized through
careful cdiJigJ;'itKcd~i~. Bubble squashing involves the ability of the first four
pipel_i·~ st~~Wlo aqy~ce whenever a bubble or buffer slot is detected in the
pip~ll~fo stag~kl~mm~ffiately ahead of it while the pipeline is otherwise stalled.

g;;i1llf§,;~31Jf!g a~~ Issuing Rules

,::/::::!:\:~?:··
. :::Be followi~~:'"sections define the classes of instructions and provide rules for
·-=::::<Iilt:::::... :::::tilhstruction slotting, instruction issuing, and latency.

.'?~1'\\l~li\t\t
Preliminary Edition-September 1994 2-19

2.3.1

•::~=~~~~~a:::::~:~"!~~~:~:::
h~=:~rformani1\;\
related only; that is, there are no functional dependencies related tR. ~checil:tJ~pg

or multiple issuing. The rules are defined in terms of instructi<m;'.'.=et5i~~~====:·=·.'.'.:~l~~~~h
Table 2-7 specifies all of the instruction classes and the pipelin~~~jthat ei~ttttii~l\.
the particular class. With a few additional rules, the table pf:i.\i4es the
'···=·==:\jlt:
information necessary to determine the functional resource co:iifft~:. that
)11
determine which instructions can issue in a given cycle._.,,;:::::}~~@)::::.. ····===t~~~!j!~}\,:..
·==tf'
Table 2-7 Instruction Classes and Slotting

C*yl"'\1w~i/l'

Class Name

Pipeline

Instruction List

E0 1 or El 2

All loads except lf¥2'.t='=t\~jj~~jjjj~J\. . ··=::lffij@f='··

MBX

~~1;;:;s~_C, ;;~tD-lock, HW_Sl'-cond,
FETCH

MXPR
IBR

~~~:~on =~~~~

FBR

=(j~j!~[:::rJoatin~:~&§~::eonditional branches

.....

<I}=· . /:\....

1{\1L.
EO

@Jnt.eg$J~~ditional branches

JSR

IADD

·{jl~t\::=:·:·. "\:\l~tm:~::=:=:·

··=:=:JfiM:tk~-sub;~utine instructions: JMP, JSR, RET, or

<l!Q:;r:.r;;~~~l~\~~:-=L~:i:;,

~i=~j~~jj~t~jft:::\..

SWBQ, SUBQN, S4ADDL, S4ADDQ, SSADDL,

··==::\~~~th:=:·. S8Al:>DQ, S4SUBL, S4SUBQ, S8SUBL, SSSUBQ,

::r <~!;tj'\l\{fiiii~~~ia~~L,

{,\~{(\\$\;,
@f(:~J~~~::: ~: "
·"""""

., ¥1!'-~:;~

pipfiline.

2-20 Preliminary Edition-September 1994

~:~~~1zE:'gf;'•

INSBL, INSQH, INSLH,

(continued on next page)

Table 2-7 (Cont.) Instruction Classes and Slotting
Class Name

Pipeline

CMOV

EO or El

ICMP

EO or El

IMULL

IMULQ

IMULH

FADD

FDIV

FMUL

FM4

FCPYS

FM or FA

MISC

UNOP

none

Instruction List

4Fbox multiply pipeline.
5UNOP is LDQ_U R31,0(Rx).

Slotting

'11,I\];\,, '\~~if·

The slotting ::AwctiorHib:::.the ffiit:J;J.etermines which instructions will be sent
forward to attil.pt. to-.T~~µ~,~- Til=Milotting function detects and removes all
static functionaf'~$.Pyrce. 'Hl:$.flicts. The set of instructions output by the
slotting functiw.i wiIPl$.$.µ._e i{tfo register or other dynamic resource conflict is
detected i:qt~ii~#~tQf thi\l~pipeline. The slotting algorithm follows:

Start~hkfrq~~l~th~~j~fjrs~:,:Cfowest addressed) valid instruction in the INT16 in

s~ge ·'1fa~.f:W~ 21t.§• lbox pipeline, attempt to assign that instruction to one

o.flthe fdU.t[~;PiP~liui·s (EO, El, FA, FM). If it is an instruction that can issue

-:t\m}~ither E(Pif.FE"i, assign it to EO. However, if one of the following is true,

_.,,:fill@~~\::.. ..ili@gp it to E 1:
..::f[\\jj[\\\?'.,.........,,\~\\jj\j\jjj} • ·.-.,~~d\\iknot free and E 1 is free.

tl\lll~,%.,i:~::,,· The:~t integer instruction in this INT16 can issue only in EO.
1

·.:,:ln this context, an integer instruction is one that can issue in one or both of EO or El,
but not FA or FM.
Preliminary Edition-September 1994 2-21

If the current instruction is one that can issue in either FA or FM, .~sign
it to FA unless FA is not free. If it is an FA-only instruction, it mustj~~
assigned to FA. If it is FM-only instruction, it must be assigned to FNl@L.
Mark the pipeline selected by this process as taken and resm~'-twith. tli~f\
next sequential instruction. Stop when an instruction cannQ\j;jbttlitliijateil~\.
in an execution pipeline because any pipeline it can use i~J!l~ady takeri=~<f![i!It.

The slotting logic does not send instructions forward out of l~~~-~~}n~truction :]j j j j~
order because the 21164 always issues instructions in o~g~t~t{f.he 816\tmg logic · : : :;: : :
also enforces the special rules in the following list, stopnJHgl~~j!j~J.pttifigj;process
when a rule would be violated by allocating the next jjj~tru~!l6ii\i\t@ecution
pipeline:
.. \{} j~iiilllr· Jil i!~ : : : : : : ·
•

:at::;:~t~~ncl~s~l~~ LD cannot be sim~~f"~q:[~~:. rs'~~~i:Fith an

•

All instructions are discarded a~J@e slo~l::,.stage- . :¥~tJa predicted-taken
IBR or FBR class instruction, or ii?J$R. claS:~mb.~.truction.

• ~~ea s~~:;!::O~~t~~en IB:@i1¥~~~,~~JBR, FBR, or JSR class
•

The following cases are detect¢.tf by tli,tm~1tti~~:·logic:

From lowest address W.fHtlh~i.t wit~~~[[[jfui INT16, with the following

arran~eme~!:~\.. . At~:~lil!lj~: ,.

"::::\(~jii~iitlt .
.
.
.
I -instructio.n, F:;j;j;trts..tructioh, I - in st ruction, I - in st ruction
1-instrucqg.µ . is &tyj:ps~:d~~9.!l. that can issue in one or both of EO or
El. F-insttU~Q!I I~q.~PY:Jnstrtfotion that can issue in one or both of FA
or FM.
·.:,:\tlt:,..
····::\\kt:.

!';::.j!~-~~\1,i~:~est within an INT16, with the following
F4ibst.tcllb:~J$:~ I-instruction, I-instruction, I-instruction

Wheii:!:Jhi~::;tl~:,,Q[&@~i:· is detected, the first two instructions are forwarded

to -:W~l~l~ssue i)'riirif.JUfone cycle. The second two are sent only when the first

2-22 Preliminary Edition-September 1994

2.3.2 Coding Guidelines

/\.

Code should be scheduled according to latency and function unit a~~t~bility.
This is good practice in most RISC architectures. Code alignm.~nt anclH~h~

;:::;:o:li;~~s::l ~~:: :h~ef:;::;e:mple are slottmtll:~:=:'!lilt,.
1

stalls (split-issue), thus preventing [c] and [d] from advan'gifi.k::::to the issue ·\~I}

st:::: example showing bad ordering
mm:h ~:~~:
( 5)

[ d] ADDL

NOTES:

R4, R8, R9

Code

ex~1f!l,~:~ 1:!J.orderi~!F
1

mJ~Jf!~41~:~Jt!:

::::[~i:~~:::::::~~!:~[[[::,~f=~=::~:M:~::~:~: ~~

(~~e~i~::~~~o~x:=l~i~~ a!~iit.~o b;~¥4}hn an INT16 alignment.

Eventually [b] issues when the resulf::::if:i~J ~=;\}~~grn.ed from a presumed
Dcache hit. Instruction [c] is d~l~~Q.. be~iij,~;:Jt cannot advance to the issue
stage until [b] issues. Instruct.:!9.ffS::l~l}~d [dlWJdvance together to the issue
stage, but [d] stalls due to aqQ.tl.i.er spUMi$iµe. ·
In the improved code ord~jll[iil~p~~' a ~d:P· (or independent) instruction
prevents the split-issue,,,¢.d$~s and-:tll~~~=~-~quence executes in one less cycle.

233
• •

·n:~:!:ti:r~:s::~!-ij\go:::ed the availability of registers for

by
read or write op~fi.ti9p.s, ··:ffii(l4)'ie availability of the floating divide unit and the
integer multiply u.IllfufJf.here:=::ite producer-eonsumer dependencies, producerproducer ~~P.~h'Utn~Jei{(ij;J~P.. known as write-after-write conflicts), and dynamic
function qi.it avaj1ibjlj.ty "d~pendencies (integer multiply and floating divide).
The Ibox :jpgic JriWitagii:,3 of the 21164 pipeline detects all these conflicts.

The l#ten~yi[j[~l!!:~r~~bJ!~' a valid result for most instructions is fixed. The
ex~t:d\!.ons ai¥~~i&itt~''lhat miss, floating-point divides, and integer multiplies .
.·:=/~tr:tt:T.abIMgb§. gives the latencies for each instruction class. A latency of 1 means
. :/\\\\\}~::=:==:=·=·==::::=\\tb;,it tli~\if~~iµlt may be used by an instruction issued one cycle after the
.=:iI[:t=pfpducing-:'ih~truction. Most latencies are only a property of the producer. An
.ftff~;;=··
,,/iJ=ception is integer multiply latencies. There are no variations in latency due
···==t\]}\=='=·· . Jlffo which particular unit produces a given result relative to the particular unit
··=·=='{\ltt:. that consumes it. In the case of integer multiply, the instruction is issued at

· : : : ~: : :tj~: : ~ t~: : : .
1

·.:,::Split-issue is the situation in which not all instructions sent from the slotting stage
to the issue stage issue. One or more stalls result.

Preliminary Edition-September 1994 2-23

the time determined by the standard latency numbers. The multiply's l~~ncy
is dependent on which previous instructions produced its operands and \\b.:~n
they executed.
·\~~l~l:l:t:.
./~~~~~t~t~::::::::=:·:..

~:~~°::~,~~~~:'.''llt

Table 2-8 Instruction Latencies

MuJY:elil~lMR~.~1 ··:::::q~::::~:~t\.

Latency

Class

~::t~~~t:;

===:::~:~:":~.or longer. ;#fal,le·!··:,i:l:.i.:i.1.:·.:·j:•_:=·:•_:•.._:=.:!:.:•..:.:\,.:~~t} ,,

LDx_L always Dcache misses, latency depen<\~f:Pf.f=\t;;;~~):::.

MBX

~;~~;'1!~::%;~~:~~~n memory,._.~ubsy~..1:·::
state.

·\@)

··::\Hft::..

· : : : : : ~: : : : : : : i: ~: : :·
..,,,.·

:·~~:::~TCH produce n:,:~\t\f1}::*'.{\'fi\wc1es

MXPR

HW_MFPR, latency=!, 2, or long~pQ!P.fpdinifcm:\::. 1 or 2 cycles

::~~ :::~;~-·i§§::j::!!t'Y
~;.ie~'.i = 1i;:· br~ct::pr~~:"'1ty =

IBR

Produces no _r~sult. -'~en bf.iji~b issue latency
minimum =':':~:~y~le, bf.@.~h mispi!:©.Pt penalty =
5 cycles.)
···:::::::::::::::~::~}:::=:::.. ·.''\l:~:::::}),,.,.. . , , , ,.·
All but HW_REI, Iat@A~y=l. ··:::::;{{)
HW REI roduces mt~Sult. ··.

FBR

JSR

2 cycles

(Iss~e lat~iyiliij;mmU:riiHf.~:~ycle.)

Larency11~ Al'pr

IADD

ti , ,

2 cycles

d¢4i'-.

1 Th.e multiplier is undl=~Jto
~at~vt&b Ebox bypass paths. The instruction issues at the expected time,
but its latency is iA~!~d by th~W~~:~~iftakes for the input data to b~come 8:vailabl~ to the multiplier. Ifor
example, ~.JMULL:ti~ct1on 1ssue'd one cycle later than an ADDL mstruct1on, which produced one of its
operanc\~.(lm!if~Jatericy::~f:JO (8 + 2). If the IMULL instruction is issued two cycles later than the ADDL

::l1t~::,:;i1::~i~~~'rP.~~~cts

a load miss in EO. If a load actually does miss in EO, it is sent to
tM::$cache imn:i.~Wately. If it hits, and no other event in the Cbox affects the operation, the requested data is
a~.@.~J?.le for ~@.Jn eight cycles. Otherwise, the ~quest takes longer (possibly much longer depending on ~e
staie:::~lHhe ~he and Cbox). It should be possible to schedule some unrolled code loops for Scache by usmg
a data\~~]fattern that takes advantage of the Mbox load-merging function, achieving high throughput
with lar ···e:Jiata sets.
g

"'T' \11

2-24 Preliminary Edition-September 1994

(continued on next page)

Table 2-8 (Cont.) Instruction Latencies
Additional Time Bif.«e
Result Av8:U@.~~e to 't.,ger
Class

Latency

MultiplY,:MP.liMll~hkt::::;:II::h,.

ILOG
SHIFT
CMOV
ICMP
I MULL

IMULQ

IMULH

1 cycle

FADD
FDIV

FMUL
1 Tl),~t~#.l!jp~ie~·"i~f~~9le to receive data from Ebox bypass paths. The instruction issues at the expected time,

h~j~~~~t~N~~ is iri~~.d by the time it takes for the input data to become available to the multiplier. For

~~ifu.ple, a'ijJ~ULL ill~fu¢ion issued one cycl_~_later than an ADDL instruction, which produced one of its
.:Jijperands, h;~~~a latency ·arJt> (8 + 2). If the IMULL instruction is issued two cycles later than the ADDL
,:}{~~ijlstructio~ltlie latency is 9 (8 + 1).
··::\{~1&~~~pecj~d:ih>ass provides an effective latency of 0 (zero) cycles for an ICMP or ILOG instruction producing
th~ft#.~t9.l'.ferand of an IBR or CMOV instruction. This is true only when the IBR or CMOV instruction issues
in th~~~~me cycle as the ICMP or ILOG instruction that produced the test operand of the IBR or CMOV
instructi#.~}Jn all other cases the effective latency of ICMP and ILOG instruction is one cycle

····:\t~::~~::l::·

(continued on next page)

Preliminary Edition-September 1994 2-25

Table 2-8 (Cont.) Instruction Latencies
Additional Time Befor'ilt.
Result Avallab~'-:J9_ lnteaft~:=:
Class

Latency

FCPYS

Latency=4.

MISC

RPCC, latency=2. TRAPB produces no result.

Mu Hi ply

UNOP

UNOP produces no result.

i cycle

u:1fi\@${111,t;}ilfl_![:~:_:~ :~_.=::~-'.
[=:=:.=~·.:_:~.=~

'%1'lqw_ .=:_=:_.=:_=_.=·=.·:_·:.:_ :_=:·
.itiJtt:::t::·:·.

1
Th':' multiplie:r: is. unable to receive .dab~ from Ebox byp~ss paths. The instru~t~'issu~~:~[l~~1~mt~~~d time,
but its latencx ~-!Jlci:eased by th~ time it takes for the mput data to ~come a;rm~abl~~~~ th~::mi~plier. ~or
example, an IMULL instruction issued one cycle later than an ADDL mstructr@r wW.eJ. pro(\~~d one of its
?peran~, has a latency .of 10 (8 + 2). If the IMULL instruction is issue~-~~o cycle~]f:ter t~@ the ADDL
mstruct10n, the latency is 9 (8 + 1).
::f{lltl~\=:·.
)j)!lttiJ~f

233
" " "1

p;::::~:::~:: ii::!:~~~also knO!i ~~ :!L~~~~:onflicts, cause

issue-stalls to preserve write order. If t:W~Hn~trufa~:PJ!. write the same
register, they are forced to do so in . W::fI~reiiM~x~!~s by?the Ibox. This is
necessary to ensure that the corre~#~f~~t:Js l~R[[[i.!l· the register file after both
instructions have executed. For niijst instla.t:ti.ons/'the order in which they
write the register file is dicta~d[:[tiiit~sue ord~tt=- However IMUL, FDIV and
LD instructions may require
=Ha\~:Jhan other instructions to complete.
Subsequent instruc~!pns th4.t~~~W!ite tli·~t~ime destination register are issuestalled to preserve -&ate prd~Hi.ltP.t the r&kister file.

m6re.

Conditions that iu!9Jve -::Mt[inte~~rl~g producer-consumer conflict can occur
commonly in a multmJ.~.:-iss.iii[\~\~itµatfoh when a register is reused. In these
cases, producer-consuM~tJate"li&li$ are equal to or greater than the required
producer-produc;_~Jtl3.:t~ncyii[~$.dletermined by write ordering and therefore
dictate the ov.~filflilbcy. ..=::\{}·

==~~=0!'t::,1::sot:a:o:he folloMng code:

ADDQ\Mj~:.R3, R4

··.··:-:-:,:::y-··wr-rd conflict stalls execution waiting for R2
; wr-wr conflict may dual issue when ADDQ issues

_.,:(i~~i~1lf1\[l[~tli~. -~~~~\~~f~\~:!:,~
. i:tt=·· Proqf#.er-prod@.~r latency is generally determined by applying the rule that
:::dhf' reID:iter file writ~ operations must occur in the correct order (enforced by
··:=:\@:@:\:::. lb6iFhardware). Two IADD or ILOG class instructions that write the same
...\t:\lliriiBster issue at least one cycle apart. The same is true of a pair of CMOV···==::~ll$.~. instructions, even though their latency is 2. For IMUL, FDIV and LD
in~tfUttions, producer-producer conflicts with any subsequent instruction
resulf~:''in the second instruction being issue-stalled until the IMUL, FDIV, or

2-26 Preliminary Edition-September 1994

:. ._:;:t_._ . .

=:_:.=:.:. _

··:!..
:1_·
__ ::
......::__

LD instruction is about to complete. The second instruction is issu~d::.as soon
as it is guaranteed to write the register file at least one cycle after th.~JMUL,

:r:~::;
:::~~::r,
and within two cycles a subsequ~t\~?l~,
writes the same register, the subsequent instruction is
.
issµ@f'speculitii~}y[:\

assuming the load hits. If the load misses, a load-miss-aiig:f:use trap is . . .'\[{\,
generated. This causes the second instruction to be replay·~a::[~).L.the lbox. ..J[\1:
When the second instruction again reaches the issu~:J@i.nt, it "ik:~~~H~:e-stalle(f::':
until the load fill occurs.
.J[h:::::::·:·····:,:::::tlrt:.... ··:·:::::g?

234
• ·

l~efo~~::g is a list of conditions that prev~~~! 2{c:2i;:suing an
instruction:
•

,:[jl:l:::::::::::::::::::::::::\:[ll::::::,. ··::::::::r:r:::::::::::··

No instruction can be issued .µptil alk9.fjts sourEt#@.;id destination registers
are clean; th.at is, all outstaridihg. wrife:[[~p,~rations "lo the destination
register are guaranteed to compl~kdn is~l\iM~rder and there are no
outstanding write operations to th~r®v.:rce ·;~sters, or those write
operations can be bypasse~t\\\\\[\[I::::\:[\\\[[:::::::t:,. ··:·' \:{\\ltt
Technically, load-miss-and~#.Se replajfat.rapif are an exception to this rule.
The consumer of the 1Q$d~'-mi~~sult issiie~k and is aborted, because a load
was predicted to hit a@.f-;~§[j[jfti~.covered to miss just as the consumer
instruction i~~ued. f:PJP.ractice}:tij~,k9nly difference is that the latency of
the consum~f.fhi8:Y b({lqpg~r than.'':it would have been had the issue logic
"known" Jh~ load@w9uld . tti(~$jn time to prevent issue.

• =t:c:~'•l,i:~~~=lot be issued in the second cycle after an
•

•

No LD.~::::§IW~R . t•U~P. Mbox register), or MBX class instructions can
be issdi'd aft~if~n. Mlf:fostruction has been issued until the MB has been
ackn6=Wledg~~fhy:::lbe Cbox.

ijjij}L{i~:\\j$f~:'.'.~u~pj\:ho an Mbox register), or MBX class instructions can be

.:fi$.[~fo.ed aft~KiN3Tx_C (or HW_ST-cond) instruction has been issued until
. ,::f:t:L\::::,.,.. ..l:li~bMbox writes the success/failure result of the STx_C (HW_ST-cond) in

..;{;JJWI' ' %:11 ::'~\:::~:::::·can be issued if the integer multiplier is busy.

·:':::\l:::j:[\[l:t:::. . ,/[[[\:!!j\::z-· No floating-point divide instructions can be issued if the floating-point

''WQ•t.,b~~::t:~::·
can be issued to pipe EO exactly two cycles before an integer
. ,,\?filultiplication completes.
Preliminary Edition-September 1994 2-27

•
•

No instruction can be issued to pipe FA exactly five cycles before a ~tingpoint divide completes.
\~f::h.

No instruction can be issued to pipe EO or El exactly two cycl~:§..:. P.efo;Jilli.n
integer register fill is requested (speculatively) by the Cbox, ,~t~Blfl~,.
IMULQ, and IMULH instructions and instructions that do.
prodlie~m~lt.~=Ylt

qif

•

result.
.
<:l;;~ll!!!!!~t:=:·.
.· · = t: 1! l j 1:~
No LD, ST, or MBX class instructions can be issued ~-~LP.~Pe EQIP:r. El
·={tf
exactly one cycle before a integer register fill is reqq,ift&f~:f~pecU:Ut\\yely) by ··

the Cbox.
~;:! ! Il :/ ./~i!!jl:FHllj:lll~~ttJ@=· · ===·
No instruction issues after a TRAPB instruction ufi:til •rpreW.pusly issued
instructions are guaranteed to finish without===g~p_eratitfjK~ tr'P other than
a machine check.
:i!:l:lll~llii~F=====<Jiiiil;l::~~::~\... ·====t@!i@@t===-All instructions sent to the issue stag~ (stag~til by the . slit.\µig logic (stage 2)
are issued subject to the above rule~~::f1f issti~t~~:::preventecPfor a given
instruction at the issue stage, all logically!~~~µpseqtt!*-tinstructions at that stage
are prevented from issuing automatically~·=·==Tij~==-~nlUW~nly issues instructions
in order.
. -=·=·=·=·=-:. .
"==:===\{[: =: :=:.
.
•

204

Re!~~~:::~:Is the,jf~;:~'.:::::'in the pipeline. some

after
ill
situations, an Mbox(jp.stru~ti~b.t~annot...hi:l:~xecuted because of insufficient
resources (or so~e other::]~.easoHWWfbese instructions trap and the Ibox restarts
their execution f~~n..the=:=•ning{~llt.he pipeline. This is called a replay trap.

~p:et:: ~::~,,~!3::r:~struction is executed and there are
0

already si~::Jtfltj]).µ:ff~p:~ht.ries allocated. The trap occurs even if the entry
would hav~::==merg~:=tR.the=t~rite buffer.

•

A load in~l~µ~fiBh. is\~~~ued in pipe EO when all six MAF entries are valid
(not ~hll~bl~l~~;::9! .~Jjld instruction issued in pipe El when five of the six

Mi\E}i,.-itries"·=wHf¥i1id.. The trap occurs even if the load instruction would
. :=::::J:fttJ~.av&:~:lij\jn the Dcache or merged with an MAF entry.
. /ii!!illlf/=:==:=====::{[l\pha .Al.1iil'-b..ared memory model order trap (Litmus test 1 trap): If a load
. :il}Y
. }h$truction Is=sues that address matches with any miss in the MAF, the
\{!!il[::t:=:·. .::::::![j[i:lhad instruction is aborted through a replay trap regardless of whether the
...==ttitt:]t==· newly issued load instruction hits or misses in the Dcache. The address
··:·=\Jf\:\tpatch is precise except that it includes the case in which a longword
··==:=:::tlt~ess matches within a quadword access. This ensures that the two loads
eit~eute in issue order.

2-28 Preliminary Edition-September 1994

•

Load-after-store trap: A replay trap occurs if a load instruction .i~;:;issued in
the cycle immediately following a store instruction that hits in tlt~fopcache,
and both access the same location. The address match is exact witti1r.~spect
to low-order bits of the address, but ignores address bits <4Mt1a?.:~ ·\::th:

When a load instruction is followed, within one cycle, 9ill!~;===:~~!liaillit..
that uses the result of that load, and the load misses=::mJUie Dcache, ··.··:=\:ft:
the consumer instruction traps and is restarted from tillH-nning of . J]j::
the pipeline. This occurs because the consumer j;p:~gµ~tiolitii.}i~~ued . \::::::
speculatively while the Dcache hit is being evajftited~l:If:::the i(iiili misses
in the Dcache, the speculative issue of the cotj:i!ime#ih§tf~tj~m was
incorrect. The replay trap generally brings th~¥bn§:jfuer W:~fiuction to the
issue point before or simultaneously witlJdlut avail@hility/if fill data.

2.5 Miss Address File and

Lq~d-f4§,C~~:,.;:®P"

The following sections describe
~i~s ··:ddfg§~ file
and its loadmerging function, and the load-mergihgfg~les.lH@k?.-PPly after a load miss.

tR!:'

25
" "1

(MAF)

~~:n~1:~1:ss occurs, eac!$lel~;~~?e~:ed see
to

contains a

if it
load miss that addresses tb.~Mi~h\~ 32-bytiflllcache block. If it does, and certain
merging rules are satisfi.~it°thelFth~tJi.ew load miss is merged with an existing
MAF entry. Thi.~:J~.llows@~S.~:. Mbox HVii.~rvice two or more load misses with one
data fill from th~:::cbq~. ffi~:)p~rging rtiles for an individual MAF entry are as

follows:
{jltj):t:. ·. ·:f{jl~:~jl~j!Ih:=:=:·. ···=:t~'.tt:~~::::t:·
• Merging orilyf§~urs . lf\ib.~ new load miss addresses a different INT8 from
all loads previ<ltii.lYJmt~t{.~l or merged to that MAF entry.
•

Mergiqg'.:gfilyj:jg,~~:~:jj:iflthe. new load miss is the same access size as the
load in:~tructJ.@is..:::previ"8usly entered in that MAF entry. That is, quadword
load iu$.trw.ftfons\merge only with other quadword load instructions
0:6.t4 loalf.'.~~fd lo~afinstructions merge only with other longword load

·:{:ll~ructi8~l~lf{'.lf:f··

./: : :~:~l l j j]l:j: : : : :~l!~ : :'.: : ~~ttiij:::~:~e~f~:~~~~o~;e:;;~:~t~:~~;!~!~n: !t~d!::sa~~:e:~:t
0

.i'.J::r=-·

=tI}fo:::.

.llf~ merge . dily with other even longword load instructions, and longword load

..Jl/::: instructions with odd addresses merge only with other odd longword load

··::::::~tElljjl~:~ii:!!l·!j:~:::··

instructions.

··::::t@ttt The MAF does not merge floating-point and integer load misses in the
····:''t\lljl:l~jj'.::~mme entry.

Preliminary Edition-September 1994 2-29

•

Merging is prevented for the MAF entry a certain number of cycles_J~~er
the Scache access corresponding to the MAF entry begins. Merging=~~l~h.
prevented for that entry only if the Scache access hits. The minimuntfft..
number of cycles of merging is three; the cycle in which the fit.~td9.J!.d "\ll~:\
is issued, and the two subsequent cycles. This corresponds :Ubth~:::iii.lt.t~~~fllh.
optimistic case of a load miss being forwarded to the Sca~b.~5yithout deltiy{!i!i!i!t.
(accounting for the cycle saved by the bypass that sends iMwIJQad misses \}k
directly to the Scache when there is nothing else pemljµg). ···==::~~~l~lk::=:·.
<]lf

2.S.2R::n:::o:~:::;:~:new entry is alt~l~~;:,load
MAF

miss. Merging is done for two load instructions i~_§:i:ied··=~iiqiftan~psly, which
both miss in effect as if they were issued sequ~qtJiQl\w.ith~~ltl\~MJ9fd from Ebox
pipe EO first. The Mbox sends a read request i1fthe···cJi!:~tJor'·=e=ach MAF entry
allocated.
·'=lt~:· -4~t:[l!!!ll!~~t::·:·.
··=:=:=tti~tr·
A bypass is provided so that if the load ~g§tructiijj4~sues in Ebox pipe EO, and
no MAF requests are pending, the load irtitm~tion~il:[~d request is sent to the
Cbox immediately. Similarly, if a lo~~ljn_stni~Q.n..froih Ebox pipe El misses,
and there was no load instruction :!filpip'-!::i.:9 t()°'=fi~gin with, the E 1 load miss
is sent to the Cbox immediately. Jpf eithef:~:CD.~~ the bypassed read request is
aborted if the load hits in the ;Qii~b.~t. or meriti$==in the MAF.

2.5.3 Load

lnstruction~-:::l.~ Nool·c~=~Blt}§pace

Merging is normanit~ilQwed·:=rJthQ.ad ins.ti~ctions to noncacheable space
(physical addres~th.!t <3:~t~:::.1)..lFi~mrevented when MAF_MODE<03>=1.
At the external intitt\we, the~iltr.ea<f'ihstructions tell the system environment
which INT32 is addr~'~i~d and\i.hich of the INT8s within the INT32 are
actually accesse.4<-:::::M.~rgiftgi!:1:tpP~==:=r~r a load instruction to noncacheable
space as soon _,,@~~~llUNQpox 8'.eijipts the reference. This permits the system
environment :lt. acc~i3hmfy those INT8s that are actually requested by load
instructiops. =~gp,rJi!~fuorJftnapped INT4 registers, the system environment
must re~qrh tfiijfa~i~ult 9f[ifeading each register within the INT8. This occurs
becau~~ttbe 21i(ftm;.@J.f:Hfidicates those INT8s that are accessed, not the exact
. ,:::::::l~p~h ·.'ihg[~~:Qffset of the access within each INT8. Systems implementing
. J~[[f=~=ffi=t;mP,ey-Iliii.m~ registers with side effects from read instructions should place
./~[}ff eac~jlj!ij4ch regi~ir in a separate INT8 in memory.

t•i\\\%1t\~~Tu\e

2-30 Preliminary Edition-September 1994

2"5"4M~~:::i:

::sF~:'i:::::~:na:d four for Ibox instrucj'hfetches

and prefetches. Load misses are usually the highest Mbox priqf:ity req~i~t-

If the MAF is full and a load instruction issues in pipe EO, Q.r!;;j}f~~ii!!~ftthijl!i$.ix

MAF entries are valid and a load instruction issues in pip~JJ.1'1, an MAF''~ffi.:U\,.
trap occurs causing the lbox to. restart execution with the.'lij~@)nstruction tfii.t.
caused the MAF overflow. When the load instruction a.r.riveitit}th.e MAF the[?
second time, an MAF entry may have become avail.w.J}ij~fiilfJ~ot,. 'lh~}).dAF ru1r

2.5.5 F:la~::::i:;·

, , ~1: ifWtj\1Mf ,

Eventually, the Cbox provides the data req~f.~tie.ij}fQr a·'m¥#.:riJMAF entry (a fill).

·Cb'ox

If the fill is integer data and not floating-pQ~fi.t da'.t~~d;be
requests that the
lbox allocate two consecutive ''bu.P.ple" cy~j~~- in the . Et@~. pipelines. The first

bubble prevents any instruction ·fl.Wm . .issQiikt:J1he secoiid bubble prevents only
Mbox instructions (particularly load 'fiW:. storM1m§tructions) from issuing. The
fill uses the first bubble cycle as it progf4.~~~.s dci'W.it=- the Ebox/Mbox pipelines to
format the data and load the r~mimt:Jile:·'·'''H!~!µ~_~s the second bubble cycle to fill
the Dcache.
.. . . J!!!lt='··· ···=::::?!liiittt:,. ··:::::qr
An instruction typically wD.~tth~ register/file in pipeline stage 6 (see
Figure 2-2). Because th~fj''. is dfi1Y,tppe register file write port per integer
pipeline, a no-in,.$truction}bubble cy~\itis required to reserve a register file
write port for tfMHm~. A rn'ai.tP:r store . 'ihstruction accesses the Dcache in the
second half Qf~~$..tage·::ijf~n~ th:~tit~t half of stage 5. The fill operation writes the
Dcache, makihg~!lt.,,.:unaVlimP.le f~tfbther accesses at that time. Relative to the
register file writ~'~'~Q.pm:~tidHWt!\~ Dcache (write) access for a fill occurs a cycle
later than th~. -.P.~acH~:!j@~~.ess. 't6r a load hit. Only load and store instructions
use the D~ib@Hhm:t.be plptljne. Therefore, the second bubble reserved for a fill
is a no-Mliui-insttliction bhbble.

The se.coJli:~buQ;\': i~~jljl subset of the first bubble. When two fills are in
cons~l'.tiv~~1:1¢.i~.~.,,J!~i!!fn an Scache hit, then three total bubbles are allocated;
twtj}pQr,instniHfof.Fbhbbles, followed by one no-Mbox-instruction bubble. The
.,,:tJ:tt:~tb.ubHlij$~~:w.e requested speculatively before it is known whether the Scache or
.;::{@t==':'.,.,.,.,.::::'t\j~ optiHfi:~t~xternal Bcache will hit.
. ,,,la~ fills f;:~?the Cbox to floating-point registers, no cycle is allocated. Load

,::iiijjil:i!F' '

:i:~!Hhstructions that conflict with the fill in the pipeline are forced to miss. Store
. \\f!ltf~?'. instructions that conflict in the pipeline force the fill to be aborted in order

··:::\{fh:=:::..

····:::t{!iltt9 keep the Dcache available to the store operation. In all cases, the floating··:·''\p~jµt registers are filled as dictated by the associated MAF entry. The Fbox
hits separate write ports for fill data as is necessary for this fill scheme.

Preliminary Edition-September 1994 2-31

Up to two floating or integer registers may be written for each Cbox fill\
cycle. Fills deliver 32 bytes in two cycles: two INT8s per cycle. The MAIL
merging rules ensure that there is no more than one register to write for··=:Em~Jl
INTS, so that there is a register file write port available for each l[bl.\l~~=·=··~t\

::~~:::::~~::~:::::::~7~:::::t~c::- '\i,
1

between new load instructions and previously issued stqr~tilt!?.trucliii!~~='=·· Refer ·\t::=to Section 2. 7 for more information on write operation~#}:::==·=·····=:=:::::l:lb::'=·· ··=·====~@?
LDL_L and LDQ_L instructions always allocate a ne~l!l~~~!~:~:il~~jj::lfi> load
instructions that follow an LDL_L or LDQ_L instructi6K ai~tanoj¢d to merge
with it. After an LDL_L or LDQ_L instructionjMi~i3.µ.~d, t)i~~bJhQJF does not
issue any more Mbox instructions until the l\q$i·il;:~f~~ce·s=Mfiliy sent the
LDL_L or LDQ_L instruction to the Qbox. 'lb~i.: guararifil~::::eorrect ordering
between an LDL_L or LDQ_L instnilthm an:a=~:ij)~µbsequeiiFSTL_C or STQ_C
instruction even if they access different ~gg,ess~=~i~!j!H>:-:-.

Execti~~\\l;i;k:ti{>

2.6 Mbox Store Instruction
Store instructions execute in th.~Ja~~x ~~~~(!jj:t:::t:\... ····::::::=:'
1.

Reading the Dcache tag sti.f::~=::~Rlt~~tion -~:::=·~he pipeline stage in which a
load instruction would r.~d the Dcli&ie,.

:: ~;:;!::ri!~,=~,~=on l there is ahit in the second

(following) pipeiiH~:::~~~:_e-~'==~=tlt::::::!\>
Load instructio:Q.,i:J~X.~. . nof'=a]l9wed . to issue in the second cycle after a store
instruction (oµ¢.IHuB6l~}cycIJ'51]0ther instructions can be issued in that
cycle. Store itt$.trm;tjphs/i;µi issue at the rate of one per cycle because store
instructions itfath.eID'stre"iin do not conflict in their use of resources. The
Dcache t@lf' st6~!jjlQg __ p,91¢he data store are the principal resources. However,
a load.Jb.$.\;ructiorflisi~flhe Dcache data store in the same early stage that
. ;:/:41tP.:~-~s "liittP.J!ache tag store. Therefore, a load instruction would conflict
. /i!]f\;Wf:ij}a, stoi&tuh~truction if it were issued in the second cycle after any store
-:J!f?' instfii.hion. RM~r to Section 2.2 for more information on store instruction
::f:jj]~;:::.. ex~ltion in the . .pipeline.

··.:'t{jljlj:jj\jj!~it#.jljlb~d instruction that is issued one cycle after a store instruction in the

. ,.;?P.!:P~l~ne creates a conflict if both access exactly the same memory location.
TlH$Gm~urs because the store instruction has not yet updated the location
whe:rt=the load instruction reads it. This conflict is handled by forcing the

2-32 Preliminary Edition-September 1994

load instruction to replay trap. The lbox flushes the pipeline and re.$.:tarts
execution from the load instruction. By the time the load instructiom1:~rrives
at the Dcache the second time, the conflicting store instruction has wXl~n the
Dcache and the load instruction is executed normally.
.,{@}:::::::::::,.,... ·\::11t

Software should not load data immediately after storing it~ jja~·-:,;::~tKyll~\ii.it.
that is incurred "costs" seven cycles. The best solution is ·(i:~~ithedule the fo'ag}
instruction to issue three cycles after the store. No issue sfii11i:::pf replay tr~p~!:
will occur in that case. If the load instruction is sch.~#JM. to Is:sU.~t:t.wo cyci~f
after the store instruction, it will be issue-stalled f.gf:/6n:W1~!l~· TBl~''.is not
an optimal solution, but is preferred over incurrinifia rep)lji\j'-p)m the load
instruction.
.. \l} ::::[!!!!:!:? /jjjjjjf::::::::v
For three cycles during store instruction exAAfi'figp,. fillsj)frm.P.ithe Cbox are not
placed in the Dcache. Register fills are u:qNfe.ct"MlM£JieiKlife conflicts that
make it impossible to fill the Dca~;lie in ~~ai of thes·~::::eymes. Fills are prevented
in cycles in which a store instruci),pn is ilf:H!P.~Jine stagtf 4, 5, or 6. This always
applies to fills of floating-point data. tmfU~ offi~~r data allocate bubble cycles,
such that an integer fill never conflica{~ft\b. a ·stiie instruction in pipeline
stages 4 or 5. Instead, a store i;g~tt9.:~tio:ri''''tti•t,. would have conflicted in stage 4
or 5 is issue-stalled but an int,mf~r]Hl~j\}.!ill cdfitiict with a store instruction in
pipeline stage 6.
.. ,:,:::::)It
··=-::::tftt:,. .

If a store instruction is sti.Jt::=J\lt\::tb.~ iss~:==~:~oint for any reason, it interferes
with fills just as_Jf it had~Jk.en issti~ij~)J.bis applies only to fills of floating-point

data.
.·:·.. ·=tt}· ./)::,:,. ···==t:t:~l~::111ift::::..
.. \r
For each stof.~@iqstructi~m,. a seii~J.i of the MAF is done to detect load-beforestore hazards:··'tiNk~~r~=:=in~~r.uctiB'n is executed, and a load of the same address
is present in the -~::,.twc>"''l}ijpgs happen:
1.

Bits ar.~~~:$ei{ib.t~.~'~g~\11amtli~~ing MAF entry to prevent its fill from being
placeq\j~:~h th~]pf~~he *hen it arrives, and to prevent subsequent load

~~:!\11~t::;:i.:i::~:=~=: the write buffer prevent

to
.,/\I~. store. "lHi&tietion from being issued until all conflicting load instructions

_.,:,:::\t:t:'.'.'.'.'.::·:. . . . ·.·R~-\m~::.~n issued to the Cbox.

,~l\W"""N'.I: :~~o:::h:~:t:b:o~!~e~oad instructions and prevents incorrect
· ·: : r: ~ j~:Jt: :,..../tj~j![~~!}{" check is performed for each new store against store instructions in the write
····:::lllf(. buffer that have already been sent to the Cbox but have not been completed.
'''%1{t&~on 2. 7

describes this process.

Preliminary Edition-September 1994 2-33

27
.

W~~ r!~!;s:~~n:~:c:~! ~~rb::~o:d the WMB instructi:•\

7"1T:e::b=:ntains six associative 32-byte entries.,~,t,;:~!til/fa,
ilf=t=:====·=··· \f}L

2
"

fully
the write buffer is to minimize the number of CPU stall cycl~~~~~b!::Providing . \l~l:;,
a finite, high-bandwidth resource for receiving store data ...·=·=T.'1is Ii~j~µired
·=t]f
because the 21164 can generate store data at the peak rt!t~Haf::w1e INtt~lJwery ·.·.·
CPU cycle. This is greater than the average rate at '!:i:ieh. tljgjl~3'@~4.~··=tan

:ta

;:::~::n ~~~h:::;:r :: instructi°'rw.,d.!sl_~~JZ_c,

FETCH, and FETCH_M instructions are also wfftWtJ!jjjpto tnit\Yfite buffer and
sent off-chip. However, unlike store instructi..QU~, the~~twrite-hu.ffer-directed
instructions are never merged into a../write-bi#.f~r entry ~Qf·other instructions.
A write-buffer entry is invalid if it d6~:S IJ:Q.t cort'$.in.. .one of these commands.

7. T:e~: :~:~:~~as aspeciaW~~~J~k~~='buffer. When it is

2 2
.

executed, a bit is set in every wri4fhuffef:~[~gkY c6iitaining valid store data
that will prevent future store Jriifikcyions fr&iij~:='merging with any of the
entries. Also, the next entry tjfbe ··itlitated is marked with a WMB flag. At
this point, the entryJ~larkedfai\lth the W\\tB.. flag does not yet have valid data in
it. When an entry iHitkQ._d ;ii~~)~JVMB flig is ready to issue to the Cbox, the
entry is not issu,~d::.:u.ntffjijy~:ry ptiW.,9µsly issued write instruction is complete.
This ensures corf&~tM~rderHiitb.~twe=~fi== store instructions issued before the
WMB instruction ail~U$.tore iliiductions issued after it.
Each write-bufr.~:~t~Ptr;>~tbh:~.;~=::~;;::=·content-addressable memory (CAM) for
holding physid.lPil<Idf.¢.~:s bit~'\!;39:05>, 32 bytes of data, eight INT4 mask bits
(that indicat~Mvhicld~r· t!i~: eight INT4s in the entry contain valid data), and
miscellan~9ui~~lfam(f61 bitijll Among the control bits are the WMB flag, and a
no-merg~~l~jit, W.1.i¢.h..J11di~tes that the entry is closed to further merging.

2.1 .3 .,mt£Y

Plltt@r ~~=~::
1

:::/JJf=:=~:6!i!i.v.try ·-=~6ibt~r queues are associated with the write buffer: a free entry
. :ff~t=·· quedi.ll:and a p~rlding request queue. The free-entry queue contains pointers

·lll:i:::::...

to.AtYKilable invalid write-buffer entries. The pending-request queue contains

··==:\ll~thdi~~fiiters to valid write-buffer entries that have not yet been issued to the Cbox.
··==\{fib~. pending-request queue is ordered in allocation order.

.· = :tl~ : [~ : j j: : }=·

2-34 Preliminary Edition-September 1994

Each time the write buffer is presented with a store instruction, th~fphysical
address generated by the instruction is compared to the address in fji.tli valid
write-buffer entry that is open for merging. If the address is in the s~m~
INT32 as an address in a valid write-buffer entry (that also c<#.j~aj.n.§. a'::~~re
instruction), and the entry is open for merging, then the n~#.tsfo:t:~~~~-~;;J.$[\.
merged into that entry and the entry's INT4 mask bits ar:~J!pdated. "if':rt\Ml:]:\.
matching address is found, or all entries are closed to meiiifig,,_ then the stoi;~[[:~
data is written into the entry at the top of the free-e11:trY. qued~f:/fpis entry4§f
validated, and a pointer to the entry is moved from_.::ti.i~~fi~~::.enti1Fi,µ.eue to the
pending-request queue.
/I/'' _Jj[j:F:[[j}b::::...·:':·. · : :·

274
" "

w::.=~~=:: !o~!~n:;:c::~"!e pendJ~~:: q(~l: :ox
1

requests

that the Cbox process the write-buffer entii:::'at tH~th@:!!d ·oflhe pending-request
queue. Then the Mbox removes t.h.e entr.Y~ilf.t.~m the ]j~{i:g.ing-request queue
without placing it in the free-entey' q~eu~~\:lfu.~n the dbox has completely
processed the write-buffer entry, it riQiW,~s tH~:[[MQox, and the now invalid
write-buffer entry is placed in the free:~kY.. qu-~ij=~· The Mbox may request
that a second write-buffer entryffi~b.~rpces.si@.tw.;hile waiting for the Cbox to
finish the first. The write-bu«e.F. e:rilHi~t:~re IfiValidated and placed in the
free-entry queue in the ord~!.Wtb~t the ·riqy~~ts complete. This order may be
different from the order iQ{[W:hiitiHb..e requ~~-ts were made.

The Mbox requ~.~t.~ that:[ll!!!lbite-~3~~h~ntry be processed every 64 cycles, even
if there is only oH~:- v'-Jid ~H~nh. This elisures that write instructions do not wait
forever to be)».T.itterift~bw.eniof:M){J'his is triggered by a free running timer.)
When an LD~~ftll\~:::L~ltki~s~;~~tion is processed by the Mbox, the Mbox
requests processiii:g4,#\t.lie rt~~:·pending write-buffer request. This increases
the chance~::::Qft~b~-.wrl~[J~µ.ffer being empty when an STL_C or STQ_C
instructioriH~:-Ts~llift
··::::qmr

:~,:~\jf=t:=~~t that write-buffer entries be processed as long

A4jlf,ff®iil'.fij't~!5~==:~~;:=~~:~

: : : : r FETCH_M mstruction

tj·~-\t;t(:;~ ensures that these illstructions complete as quickly as possible.

Preliminary Edition-September 1994 2-35

Every store instruction that does not merge in the write buffer is chec~fp
against every valid entry. If any entry is an address match, then the wNt.l:.flag
is set on the newly allocated write-buffer entry. This prevents the Mbox ff:-iro
concurrently sending two write instructions to exactly the same bl®.J.~An. th'~[l[lt:
Cbox.
-:':·. j~i! l! !l: :· ...,., :=:=: : ~: : : :t:l:[:[t[t~l l !l! l!l! ~ ~lt,.
Load misses are checked in the write buffer for conflicts. The:::gr@1mlarity of "\jfh.
this check is an INT32. Any load instruction matching any writ~M~Mtfer entry's J1l
address is considered a hit even if it does not access an.,,::!lf!1:f:h:.:rmui~~l:f9r
''\:?'
update in that write-buffer entry. If a load hits in the wfite bilfm.-~ a conflict bit
is set in the load instruction's MAF entry, which prev~s tl\~Hdii.jJq;~truction
from being issued to the Cbox before the conflicting Wfae-ljjffer @~tcy has
been issued and completed. At the same time, tb.:@:J!Q-mergj[J;>it. ,;ij::::set in every
write-buffer entry with which the load hit. A wSWib.1#.[~r fli$ftdl~ is also set.
The Mbox continues to request that write-bajf.~f' entri~'S:l[~Wt.Processed until all
the entries that were ahead of, and indudilig~[![ih~ conflicting write instructions

;::ee=~ ::::::::~::: :e;r!~!ih! ~,.he without external
1

environment involvement. To suppQdtt.bJs, tHitMl>ox .retransmits a write
instruction at the Cbox's request. Jfhi's.'''Mtmtio~':::tttises when the Scache block
is not dirty when the write instrn@fi.on is i'ss:li.~~- or when the access misses in
the Sc ache.

. ,:,. :~ii!!l[~[)Ht:f[llll~[ll~~lll[[):::::.,..

··:::::t:··

2.7.5 Ordering of Nonc,1g_heabH~l[::$pacEf\Vrite Instructions

Special logic ensµ:re~''lli.~t::::wrl~:[j~tn~t.ructio~s to noncacheable space are sent
off-chip in the o:tdij!\~µ ~M~lt::their'':~b"esponding buffers were allocated (placed
in the pending-reqrtiitH;i:ueti~%l)t;,,... . ,.,.

2.8 Performan~-:~;~~ Support-Performance

jll![-l:l[ . :t:[ll~~~~lllf" ., :~! ![l[l: . ,.
The 211Qt.4!orltjijjs'' a p~:tf.-Ormance recording feature. The implementation
of this f~i£U.re Pfa.md~$.::[~?ffiechanism to count various hardware events and
. . .~.~µse~t:lllli!.1terrupt\i{fon counter overflow. Interrupts are triggered six cycles
,/:dl~t:::the"'·'~~:Q:t, and therefore, the exception PC may not reflect the exact
. :f!If':" instfll.~tion catl'ti~g counter overflow. Three counters are provided to allow
. :=::j\~\[/:" accµWJte comparl~on of two variables under a potentially nonrepeatable
·=::::\It:::::::::. e!p~fimental condition. Counter inputs include:

Counters

<\f(•l~~!~sues
• ··:-:'\Nonissues

• ;:f~l cycles
2-36 Preliminary Edition-September 1994

•
•
•
•

Pipe dry
Pipe freeze
Mispredicts and cache misses
Counts for various instruction classifications

external events at a rate determined by the selected sy§t._~m ·aii.h:J~peed.

·4HF

For information about counter control, refer to the.::f4.lt~~-~t~Iritag~'eriptions:

: ::::te

:::
8

:::::~:~:::iltfu:r;5_1.23)

•

Performance counter (PMCTR) registet~jj(l~:=:=~~§ij~ti9.~''~g~~~f~~~~;)

•

:~c~~n~l1 (BC_CONTR~ :;~~l~i\\~'.·' 5.3.4)

2"9Fl~!~~::s :~~=~ 4!!C~'ht

:ontrol

··::::q:f\:·

Table 2-9 describes the fieldafol\..

bits
register

<24:19>

(FPCR) and

Figure 2--3 F~g-Pdi•r.:::~ft~lst:r (FPCR) Fonnat
..;:;....

;t~~~~~~}

: ::··:;:::;:::
:·. -::}\::::..
.. .: . :·: :·...

· :·: 'tl\lt\l.~ -;: ·:~.:~:~.:~.:~=_.:· '.:·

63 62 61 60 59 58 57 56 55:$.(~l}..:;2 5~-:~~~1~ii~~h-...

:. ._: :._·.:.·.:.·._.·:·_.: :._. .:_:

·.·

RAZJIGN

:jl!!lljl' .v·

.:)t: ?' : : :.
1

··::::v

ML0-011301

Tabl~l;..g'tt~:i;i,1,int Control Register Bit Descriptions

Preliminary Edition-September 1994 2-37

Table 2-9 (Cont.) Floating-Point Control Register Bit Descriptions
Bit

·=tk~:::.

Description (Meaning When Set)

Underflow disable (UNFD). Subset support: Suppress UNt\&ifi~Jt.rY?roi~t,

::::

~~:r11::
~:~:i::n~:;:,:~;:::~tn
un:::::,rt'
\t
the hardware places a true zero (all
bits zero) in the
register Jtk

<59,58>

M~~~tion

rather than the denonnal number specified by theJi.i~ staiitiit4..
<tV
Dynamic routing mode (DYN). Indicates the roqrt~h:~=~m.,. to b:ti~ed by
an IEEE floating-point operate instruction wh~fi#he i~Hi1J9.P.:r!- function
field specifies dynamic mode (ID). The assignmej~ arjf
{ft?:::·

·==::t~J~~r~~~~}~~)::-:.
· ·

DYN

..,,;.-

IEEE Rounding Mode Selecttif
·. ·:·:·:·:

~i[.·,[!,~_,-,[_:~:~,~-:~,\_,·_,'·',.:'.:·_.'.'.·'.'.'·'.'·'.'·'.·'·'·.·_,_,','.=,_,=.~,-_,~j,=,:~.~-.[F
__

··~·:·:·:·:····.

00
01
10

<57>
<56>
<55>
<54>
<53>
<52>

Integer overflow (Ioy$d)nt;ege:''!!ifuetic operation or a conversion
from floating to in~~r oven@w~d the destination precision.

Inexact r~µJt (INm~~~j~A. floati~:~~~,~hmetic or conversion operation gave a
result tha:f=di~~:red rr$.ihijie mathematically exact result.

Undefit~w. (UNi)hA fl~SijgHnithmetic or conversion operation
underflO\.V:~i:,.the de~iµ~tiori.''exponent.

Overflow ("Q-k4 fi~J~~g arithmetic or conversion operation overflowed
the de.stinatiori'l-P.!nent~·
~§.i~~~=~=gjljlj~r9 (d~ih. An attempt was made to perform a floating divide
opijfatioqjJi.'thjj(divisor of zero .

. ,:~: :,:,. I~Vli~~~l~rat~I (INV). An attempt was made to perform a floating

<i\l\;?::!~~~~~~:::::~ration, and one or more of the
·.·"j:'.jt~~Wl by zero disable (DZED). Not supported.

Inv~ll~· operation disable (INVD). Not supported.

Reserved. Read as zero; ignored when written.

2-38 Preliminary Edition-September 1994

2.10

21164

Mdr/cmd

~gu(fil.j~f~~~•::~}multiprocessor:::, each proressor IDili a

bo~4.ilevel clfoniiilKch interface controller must employ a duplicate tag store
. ,:,:::t?t:::,:,.to IHiihtain cache coherency. This system configuration could be used in a

Preliminary Edition-September 1994 2-39

Figure 2-5 Typical Multiprocessor Configuration

21164

Pddr/cmd

External
Cache
Tag

External
-------- Cache
Data

Data

as
Interface

Duplicati

Tag
store

2-40 Preliminary Edition-September 1994

Figure 2-6 Cacheless Multiprocessor Configuration

MLQ-012977

Preliminary Edition-September 1994 2-41

Hardwarli!~ll~ll,nterfa·ae.

~!;~~=~te{s~:~:;~'::,!~;:i,~1!:;;';::::~:::'1=~~;:~d

4$T

3.1 Alpha 21164 Microprocessor Lodl! 1fm~81m;!P'

Figure 3-1 shows the logic

sym~fo~ thi;·\~fj;_.: :;~\~p

ll\1~l@fW!tr

Preliminary Edition-September 1994 3-1

Figure 3-1 Alpha 21164 Microprocessor Logic Symbol

21164
addr_bus_req_h
data_bus_req_h

SystemJBcache
Interface

cack_h
cfail_h
dack_h
fill_h
fill_error_h
filljd_h
fill_nocheck_h
system_lock_flag_h
ldle_bc_h
shared_h

irq_h<3:0>
sys_mch_chk_irq_h
mch_hltjrq_h
pwr_fail_irq_h

c:-:~k~~;;~

··:·:::\{[[::::iii::::::¢1ocks

.;z·

ref_clk_in_h :.""::::::,....::::·_·- •

dk_mode_h<1 :0> :j,i;;;;:t;;;...::;_:-..,;;wi

'I
·····

:-:.:.-_-_~~ ::~==:=:~1~h
o--- sys_clk_out1_1

---

sys_clk_out2_h

-:·:·:-·:·:·_:·.~~l--.-:,:,:,:,:0'-----------~n..._-----_--_-:=:::~rn,

.P.~rt_mode.J~~~:~?'

Test Modes and

...___ tdo_h

Miscellaneous

- - - tms_h
---trst_I
- - - srom_dk_h
srom_oe_I

a---a.--- srom_presentj
MK145506

3-2 Preliminary Edition-September 1994

.·:=/~{}::::....

Signal Type

Definition

Bidirectional

Input only

Output only

· =:t~ -~-~:~-~-.:~:~_=_:._:'_.:= .:· .:._: _:·_.·:.·:.:_.:_:_: :.

.:::~:~:~:}:~::::::~:~:~:~:~:~::::·:·.

t1l'.
..:::=~=~~~~Jt~i~~~: : :·.

~:1:1_:·:_:1:•.:1•:_:•:·.:·:.~:;~:·:.,~:t:l·::·:~=:::·:~.~:··.·.:·:.·.:·:·.:j.:: 1·1·;*®~!
••

The remaining two tables describe the fqrill:~··;f ~ ~®.h::.;::~:~:~:~ external signal.
Table 3-1 lists all signals in alp~umeriijll[itder. Thi~''''table provides full signal
descriptions. Table 3-2 lists sign~tS PY. fun~'Qip,)md provides an abbreviated

Wi'ftfl'tt,{;:~t%]>

description.
Table 3-1 Alpha 21164 Signal
Signal

addr_h<39:4>

addr_bus_req_h

addr_cmd_par_h

Descr1i>tl!'t\1\\;iik.

Type

36 . : :. t:f' AddtW:~nw.s. These bidirectional signals provide the
ttlt\.. addresetQfjijie requested data or operation between the
··:::?1fi[~!J.64 and..lhe system. If bit 39 is asserted, then the
·<t:::t\::·:· . . M.f.•~~nce is to noncached, I/O memory space.
·liftL:-:.. t<\lt:::. .
bus request. The system interface uses this
B

Addf~~s

Afitll::::l\j~l~\@~:l~:::::~~~;:::::~:::~::~:::1:!\j !j t.

..:::d!:i[!:l~f <t\

ll\. -:::/?'::.. fl
·: :~ 11l:jjj[[j:i[iit1l@tt:::!!j!}''.

· : : : :- ~~e:u~:iO:c~:~~~~k~~: ~:'!I:;se~:~e:~ J!:c~~~~e
system should do the same if it detects an error.

(continued on next page)

Preliminary Edition-September 1994 3-3

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

addr_res_h<l:O>

-:=:::::·:·.·..

·:·:·:·:·:·:·.

Address response bits <1> and <0>. Fqr::J~yi$.•t::::=::::.::::J::I:\
commands, the 21164 uses these pins ~§)ndicaUfth~flllh.

·(t~ i l!l!l!l:L.

state of the block in the Scache.
Bits
Command
Mearwut

addr_res_h<2>

cack_h

cfail_h

.·:·..

Address ~oru!</i\t>. ;::i•m commands,

the
21164 usei\ft~. pin ..t&Jhwcate if the command hits in.
the Scache of:Q#.%.JriP fokil[J~k register.

Comma:r~4JW~~$1~~~.· Tji~f~ystem interface uses this
signal yfijiJW:9wledgr(~4y one of the commands driven
by 21~r·~ ··::==tt::tnk=:·=·· · · :::::::::
1
CQmf.iib..d fail. Tm~Nngnal has two uses. It can be
~~rl~tit®.ri.ng a cack cycle of a WRITE BLOCK LOCK
.:J;~M.hmand:::tWi~P-icate that the write operation is not
·::::=~·:~ssful. nrttus case, both cack_h and cfail_h are
. : :. assif:oo.p together. It can also be asserted instead of
·tf)t. ~ac:k!ll~:w..force an instruction fetch/decode unit (lbox)

<llli111t;h '\\';'.11.,!~~ ~.=~!~~.!ci~:ct&i ~=..\{ff:\::.. entr:WP.oint, which indicates a serious hardware error.

clk_mode_h<l:O>

cmd_h<3:0>

1f1)&%ltt,::~,~~1~~~~:;{:rEr:r~~:=:~
•;tzf~:1~11tlf ~:'! ~ ~:":o::!d t1~~ Th~ }:!1~~·

+itl\,~~t\;;>
Ah

3-4 Preliminary Edition-September 1994

:i.:~·:;:I:!:.::

·-.:·: \:.: : · :·.: · .=:·. :.·\:.;.·

···:=t::\~ilt::::.

~:;~:~s~::z~!!~~?E:TE~::.)

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

21164 Commands to System:
cmd h
<3:0>

0000
0001
0010

Command
NOP
LOCK

FETCH

(continued on next page)

Preliminary Edition-September 1994 3-5

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

0100
0101
0111

cpu_clk_out_h

dack_h

J@!

Read a block; set
shared.
Read a block;
invalidate.

(~,:::~~t. This signal is used for test purposes.

··:·:1 . : ,.

.iiiti.t~knowi~'~e. The system interface uses this

'\19!@;., •'lllij;~:•ntrol data transfer between the 21164 and
data_h<127:0>
data_bus_req_h

'"f~ifa+!!~1ii;"4, '!7.1::,::;:1!,,':;"~':':~h';:~ve data between

't~:;;;~:)'\~~~~~~~I~~~~:~~k
refer to the sections on bus transactions in Chapter 4.

Data check. These signals set even byte parity or INTS
ECC for the current data cycle. Refer to Section 4.13.1
for information on the purpose of each data_check_h
bit.
(continued on next page)

3-6 Preliminary Edition-September 1994

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

data_ram_oe_h

data_ram_we_h

dc_ok_h

fill_h

fill_error_h

fill_id_h

··
' ~l ~i~: : : :.

Data RAM output enable. This sigw.~Jjjt~jll~~~:~j!jfQ!
Bcache reads.
.: : . jjjjjj[jl?
.····:·::::::::::\~jjjfl~:ltj:j:[:\:.
Data RAM write enable. This sigiji,[js asserted for·~.
Bcache write operation. Refer to Becfi:OO.. 5.3.5 for timJik
details.
:.::/~lfk\::::..
····::::q::t:>:...
·:;:::{:::de voltage OK. Must be .~Wi~~~i\ia~~::µ;ntii":::d~ll~toltage

::~::rper

operati1rtlPf·

dc_ok_h ;.

Fill warning. If tw~h~!gnal i~:)!~seJ;tjp at the rising
edge of sysclk n,:tftlit(t\~. 21f6Jfpf:{Mdes the address
indicated by filfi)d_h l&$lt~. Bcache in sysclk n+2. The
Bcacqe begi~~~:jhwrite in. :t'iij\t~ysclk. At the end of the
rising:j~ge ohyj~~ n+ 1, the::::21164 waits for the next
sysclk'al\~Jhen ..bem~~ the write again if dack_h is not
asserted.··=:::~=ttl~tt\... ···:::tt::::::t~::·
1
Fill . ~ITW.: If tfflKfilgnal "is asserted during a fill from
m~.@.9ryiJ~jµdiciiti.i4o the 21164 that the system has
d~@cted atfmyalid . address or hard error. The system
;;:::::~#:ll:.provides:::iif.fa~pparently normal read sequence with
/@fo&f.t~. ECC/parlfy though the data is not valid. The
. : :. ll 21164t~ps to the machine check (MCHK) PALcode
<tk@\. entry p"&ifflh'1nd indicates a serious hardware error. fill_
··::::\@~r:ror_h should be asserted when the data is returned.
<llk::. ·. ·.·.Ei~h. assertion produces a MCHK trap.
r=tt~t::.. FiiFt~htification. Asserted with mi h to indicate which
1

.\i\f;\\]b,,"9't\ftr::~~~"';!•.1i}et~1;~~r.rt..fse~t~!-=~~.

OO_nocOOck_~jft ·t~~:~~:;t~j{~\j}~~~~~i~~~:~~~:~~~~~
idledi~;h 4\il\1~Jil~\ {1c

=~~:;r~=~!::!~:=~;tif~EE\.

deasserted. Systems must assert this signal in time to
idle the Bcache before fill data arrives.
0

Index. These signals index the Bcache.
(continued on next page)

Preliminary Edition-September 1994 3-7

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

int4_valid_h<3:0>

INT4 data valid. During write operatio~;4K~MM~mtlM~L

~su;:~:~r!~%~a::c:tr~t~~;.;r:l~~~t:i=::!l~:ll!llll~~~~::,,
been merged in the write buffer.
int4_valid_h<3:0>

..,,,\~:~~~~ll~~llllt:=:::::..

Write. :MtMl!M=:·.

· ====\fltt·

xxxl

xxlx
xlxx
lxxx

:r&ia ope~;11.~:.:

·:~::lkis

During
. these
indicate which
INT8 bytes o()h.~2-b~l:~k need to be read and
returned to th~tft9.~esscifA~Ubis is useful for read

operati~:&:mMt~~iic~ft!~===~em:ory.

3-8 Preliminary Edition-September 1994

·: :;~l !l l l~:

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

irq_h<3:0>

System interrupt requests. These sj~Mi~lb~Y.~t~ilvple

~~~~:e~s~B::a!;~~~~en~~~W:l~~~~!:!,~!!l~~:h::

requests. During initialization, tnijm.K~ignals are use·cut
to set up the CPU cycle time ..m.visor=::r@:::~ys_clk_ou~~~iJ:
follows:
:Ji::~:;i:fI::~:::::::::::tt=:·.. ··=:==t@t:J>
· :·:·

Low

lrq_:~I iltfv:~1,~:11 Ratkl
3
Low ..::::::?l?High '::\:::tm•h

E:A[~} 4j~t;;;:~\l1)'· E~
Low

·=::~~~t::t::\::..

' 4i1tti;:!'.!!i

V!il;1b,

mch_hlt_irq_h

High-

High

Low

High

Low

High

Low

High

Low

High

Low

14
1

(~l} ,.
. :::::.:·.

@f)'.~1~·;:-~il:f-µ. ~~:terrup~r:uest. :as
'1\11t!:: 11~) ~~:~~E!:~~o!~~:!E~~~
Machlne

I
I

1
1

: : &gnW

Oscillator clock inputs. These signals provide the
differential clock input that is the fundamental timing
of the 21164. These signals are driven at twice the
desired internal clock frequency. (Under normal
operating conditions the CPU cycle time is one-half
the frequency of osc_clk_in.)

(continued on next page)

Preliminary Edition-September 1994 3-9

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

perf_mon_h

Performance monitor. This signal provi@'.~l[~WP.!U~4R:iii.L

port_mode_h<l:O>

:~~~::r:a:':i: ::~bi!f'S!a:~-:it

pwr_fail_irq_h

ref_clk_in_h

scache_set_h<l:O>

shared_h

srom_clk_h

o i\l\;%}J; ' 'W%tCtli~ft:1~:c~:pplies the clock that causes the

srom_data_h

··=·==t::@)\... SRO:Mbto advance to the next bit. The cycle time of this
··'='=tj]}:,~Jock1s 128 times the cycle time of the CPU clock.
..::Jl[~flitlj~if::: . ,.:\S~f,ial ROM data. Input for the SROM.

~~~~!n::!~:~ rs~1!h1!ab1~: :~~1;~~~!!lfrdwar(f'lli!:lI~~ll!~~~:~t:

set low.
.)j::[~:lJf:=:=::\j[~~~~~::llit=:·. ··==::(@)·
Power failure interrupt reqq~t. Thf.~···=Si~/!J.as
multiple modes of operation#P.utjjg ini~fliiation,
this signal is used to set up sj"s_f$.._outlih,I delay (see
Table 4-3). During nJ~tmijb9peratih.Jlwf signal is used
to signal a power f;1,=r0·:·=·==t:lilt::t\::... ··==\}{{:::··
1
Reference. . clock iP.P.it Optiorial@]l~ed to synchronize
the timirig)>f multiit~hpricroprocessors to a single
·reference Cl~~l\,.:.. ··====::::jj~ttmk=:·:·.
Secondary cache:]~M~. Durlflg)1 read miss request, these
2
signals ~µQj~~te thithche s'et number that will be
filled ~l~tftb~:Jlata..U(~tumed. This information can
be usejl:by thetijy§.~m i<fmaintain a duplicate copy of
t~:~:ii~lte.~ tag st~11ml>·
1
~p bl~it~tatus shared. For systems without a
;::::~~che, whe~i::~. WRITE BLOCK/NO VICTIM PENDING
··:::=&W}YJUTE BLQCK LOCK command is acknowledged,
../\... tms::jp~~_}!an be used to keep the block status shared or

::~~sentJ ,,,t~::;,}4; :: !~~M~=~:::~::P:::
S::::::r:::e
1 1
sys_cuti.~-jp(\~':k,O
;:i:~~.: =~~~- ::-ammable
1

sy~zrr:out11lll~:\

··=::;:::{~t>

syst..m clock

~~:~:~=1:::1~~~!~~ ~~e':lro~~~ 3 to 15) is used

t\:1!,,,f\t~::;~i'

3-10 Preliminary Edition-September 1994

(continued on next page)

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

sys_clk_out2_h
sys_clk_out2_1

0
0

1
1

sys_mch_chk_irq_h

System clock outputs. The value o(:Jll•.h~~tfl~,l

~~~:~~yed by a programmable aj[;Jft from:,:u:+.cf!i:~l~ffi:~

:1;hii:::.i:~·;
~;,~::B~91~:u~~~Ji
it is used to set up
deliy:Xsee
sys_~•±ou\lr;;}l,l

Table 4-3). During non:jijl ope1#ti.ib:r.Jt js ··used to
signal a machine interrtii\. ch~)freq#,~tf"
sys_reset_l

~~e r3~~~~~~:-~U;l!1~4..sr:~d

until de ok h ufissef.Wd. Afte1ftnat it is deasserted
and the 2116~:-.lW~ns a -:J~~pce of r~set instructions.

Syst~)ock fill:~:Quring filjgfihe 21164 logically ANDs
the value.:::~f the··::Siit~J;Il copy with its own copy to
produce tR~mtme va1ii.ij[~9(._the lock flag.

system_lock_flag_h

tag_ctl_par_h

tag_data_h<38:20>

19d;of1!!~&da::~~~~- This bit range supports 1. to

tag_data_par_h
tag_dirty_h

Tag_-:9.9.P:H:ol ·;Ja~~:::::pri~t~jgnal indicates odd parity for
tag[,filiQ,t);, ta!!J.w.n-ed_h, and tag_dirty_h. During
fillif the sji.~ shotild drive the correct parity based on
:':::::~b.ijh~tate of trnfy~lid, shared, and dirty bits.

odd for
fB'l\\(1\[ilt~:~J{~\t;~i?~~~.~::?.::.:J=:1ss
B'liJ .;w&h:Wll\=t£~rs-:~.Tlris signal indicares

parity

-::tHf:@lfiit:':-. ···::::~:\}~\-.. Table 4-6 for information about Bcache protocol.

tag_ram_oe_h

j/?'·· 0 ")tJ? J ··=:::::~{iJ Tag RAM output enable. This signal is asserted during

tag_ram_we_~fa,
!Jfi\il~~~~'AJ'
; ~~~:;~:~ri~i~::t~~ c~~n;f
.-:::::Jl~(
..
%f1'i;;{{f~t•i•··
E~?::t;:E~£~!c~~~~~i'?on,
,:::::t(r:=::::::,:··

a write operation, the write pulse is deasserted. In the

WE_CTL<8:0> control the shape of the pulse (see
Section 5.3.5).

(continued on next page)

Preliminary Edition-September 1994 3-11

Table 3-1 (Cont.) Alpha 21164 Signal Descriptions
Signal

Type

Count Description

tag_shared_h

tag_valid_h

tck_h

tdi_h

tdo_h

temp_sense_h

test_status_h<l:O>

tms_h
trst_l
victim_pending_h

Tag shared bit. During fills, the syste~:::~~Mtal4.ri:;,~![~~!~~l:t,
this signal with the correct value to m4fj(.. the ·afoh.~Htl~l~h:
block as shared. See Table 4-6 for inf-0-f.fuation abouc=::::q~Jt.
Bcache protocol.
··=:::::\@j~1!!~i~~~b::::..
: :'.! ! ! ! 11:
Tag valid bit. During fills, this...~ilool is ~~d to
·:=t?'
indicate that the block has validNlitibSee TaD.Ut4-6 for

~~~~::~:~:tfO?t~,,"

~~Z~i~!~~~t:::~·

Icache test statuttrofomiatiij~ from the chip. test_
status_b,~~-. is assij. .9 if ICSR<39> is true, on Ibox
timeo~~faiFfl:~ns ·1i$~;¢ed if the Icache built-in
self-te~t::'(BiStYfiliU~.· Also~ test_status_h<O> outputs
th~4~@l\\~ writteif.y;J>ALcode to test_status_h<l>
AF'li.~ess>For additional information, refer to

~ '1i·t~:;~ ~\W;;i!i::.:~:c:::z:=~ indica~s

· ·= : : : : \:j \ [j [ j~: : : : : : : . ~~~l~i: ~=~~ia~e~:q~;::~:~::~~:!::n~ :c~:l:i~ess

. ::ffjjf{}H::\:::.. ··.'=\{\\~~:-until the victim is removed.

3-12 Preliminary Edition-September 1994

Table 3-2 lists signals by function and provides an abbreviated des~ption.
Table 34 Alpha 21164 Signal Descriptions by Function
Signal

Type

Count Description

_&,,.,_.

'1'{,\

Clocks

clk._mode_h<l:O>
cpu_clk_out_h

osc_clk_in_h,l

ref_clk_in_h

sys_clk_outl_h,l

sys_clk_out2_h,l

sys_reset_l

~t~~}:

Bcache

data_h<127:0>
data_check_h<15:0>

B
B

.i~i-littttP~Uii,~¥
{ff16

····==tD.ata cMck.

~g~f ·t\~:~~:~'.ilit\11£~17~~=~·
:*t}

tag_data_h<3&,0i>::,..
···=:tll\..
HF
tag_data_par_h ·:.:,~\t~lt\.. ~\\~ll~t~k:.1

Bcache tag data bits.
Tag data parity bit.

" : ::::u~:~le.

=~ittt:»\;~::~l~{J• ~

=(~:1::t®i{J' : ~ E=~~ ·~:~tinued nert ~)
00

Preliminary Edition-September 1994 3-13

Table 3-2 (Cont.) Alpha 21164 Signal Descriptions by Function
Signal

TYpe

Count Description

System Interface

addr_h<39:4>
addr_bus_req_h

addr_cmd_par_h

addr_res_h<2:0>

cack_h

cfail_h

cmd_h<3:0>
dack_h

data_bus_req_h

~::::::

Address command

fill_h

fill_id_h

=~~z:~~O>

i J~iti11tE:!~~:

<~t.',::_',',_:,::_·,:··:·':·-:·:·~:~-~.F::!j:~l:;:~j:I1.~,_::~_·,:~_·::.·:·:_:·-·:·.·:·-: ~e: :~e~:bp:~hbdlaryockcsactahteus8esth.ared
..

•;t:

,r_ ·'!...__

.=!_
..
·='--.... ..
__ -=1__.. .':
__..
__

~=::~:J~(~)*·''

fill_error _h

shaca:::-shet_h<l:O>
S
.:t~~t~t::::..

·t\i~
'
'
%
~
%
:
;
;
~
i
l
_
{
,
~
,
l
_
:
_ :~: .:~,·=~_,·.=~_.=:_::.-,'
m~. ''tlttt1~\\)

:::·request.

llj

:::~:::~hW{!{j~,_.·:.:.·:·_,•.

=_.·_,:·:.·:_,,:_:··,·_:':.·.::,:,:::::·:_,{J;•.

..::::::~~~~~~~~{~~~~~~~~~~~~~::::::.:..

't':-=::::·

Interrupts
irq h<3·0>

\tL .JMf:

.:~![!j:~

mc~s~{'''l&rnw:@f'

System interrupt requests.

Machine halt interrupt request.

Power failure interrupt request.

System machine check interrupt request.
(continued on next page)

··:::=::r·

3-14 Preliminary Edition-September 1994

Table 3-2 (Cont.) Alpha 21164 Signal Descriptions by Function
Signal

Type

-:·:·

t[fh.

Count Description

Test Modes and Miscellaneous

dc_ok_h
perf_mon_h
port_mode_h<l:O>

~ ~ ::::::::~::;~\~.~(:~::1

srom_clk_h

srom_data_h

srom_oe_l
srom_present_l

0
B

1
1

tck_h

1:::::...

tdi_h
tdo_h
temp_sense_h
test_status_h<l:O>
tms_h
trst_l

;e:~r;:~~,,~1)!;:1>
serial ROM data.jjjjjjr : :j j j (.,.,.·.·
SeriaJdJ.QM. outptlt!!~m~l~~
setjm[:~Ji0tr:ijr,~~~t?~~1=r==,..

~ ~\1f ti{~!it\~::
I
0

:d~t~~j{[f~~~th::~ci~l~rr;= sense.

fl2

B . ::ttf:l:li..

=::~:t.

J,4.QJ><>unda;~t~n clock.

··:·=:=t1~-che ~st

status.

JfAtiHest mode select.

.:/~.l~lt''·:·······:·::::ylll~l:ll~l:[[::[}\,.~TA~ test access port (TAP) reset.

Preliminary Edition-September 1994 3-15

Clocks Cache and Externajlil!llll~l~,nterface
'

This mapWr desfflbes the

··=:::::::::::::::::..

..:::::::::::::

Afpha::~::::'-:25~~:::.0n

which includes the backup cache (Bcache):~arta··sYi@~w. iiiWftaces. It also
describes the clock circuitry, lock~, inte~:NPt signal§fll~~ ECC/parity

:en::::~;o: ::~:::!~"~'Wt:;\)~

• Clocks
' """"'" '%41,\\{p
: ::::~:a:t::: :;i:.;f:44%tt\\\t,,
• Cache coheri?' 4'll, ' l\\1Jl"

: ~:~:::c:vr.::~:t~w.¥
•

21164-ini ti:~~~~jjjj~t..~-~~llti#.us~:tions

: ::10f~fa::ess bus conwntion
•

\(f}k=='=·· . /UPhapter 3 lists and defines all 21164 hardware interface signal pins. Chapter 9
··=·==ttft>il)lf'describes the 21164 hardware interface electrical requirements.

"Wt't1@4!~>

Preliminary Edition-September 1994 4-1

4.1 Introduction to the External Interface
A 21164-based system can be divided into three major sections:

•

Alpha 21164 microprocessor

: ~;:~:~::::~=~:store

~:=:~ ~~::::s

./Itt::::==·=···

'*\'i{{ti\}

ti'''1J

The 21164 external interface is flexible and m!@ji@1::Je~~~l,~li-~~~~~les,
allowing a wide range of prospective systems. Jfhe iritefft~e iiiCludes a 128-bit
bidirectional data bus, a 36-bit bidir~tionakkdk:ress bu~}~jib.d several control
.signals.
.':\j\f' tl~\... ··::::qt~~jlllj\\jj~~\::...
··===--

Read and write speeds of the optional Bdi~J~tJtrray{ij@p. be programmed by
means of register bits. Read and writ~t§PeedM~~r~. ind~pendent of each other
and the system interface clock freqpifticyW\\.. .. .:=ttlt

The cache system supports a s~Jootl.ple a~2H~H>r -~4-byte block size.

~.:::e~: ::~w:~J~l!~??~:;~al interface. The function and

411
. .

s:~e:c~~~e:~~4:~\~;\~,\~te:al bus interface. The system

interface is made up ·.:MU~idirecliijh.l.ll address and command buses, a data bus
that is shared wi.tlktb.e B~~~b~ inlerface, and several control signals.

The system igt~~=~;.;!j~~}qpd:;~~lthe control of the bus interface unit (BIU) in the
Cbox. The sYi~m Jnij;rfl.~~ is a 128-bit bidirectional data bus.

The cycl~\[~~~~j~jj~f[t~h:~ sy§llin interface is programmable to speeds of 3 to 15
times tb.i.R::Pu cy&1ett.biK All system interface signals are driven or sampled
. :=::t:PYA!ie .
on the rising edge of signal sys_clk_outl_h. In this chapter, this

21114..

4-2 Preliminary Edition-September 1994

Figure 4-1 Alpha 21164 System/Bcache Interface
21164

idle_bc_h
int4 valid .~:0>

Optional

-::{)}\.

r---..,

Lock
I
I Register I
I~--···········-~
Victin
I
I Buffers I
r-·············1
I Duplicate 1
I
Tag
I
I Store _J1
I

1.-____

Bcache

> Interface
....

MK-1455-04

Preliminary Edition-September 1994 4-3

4111
· · ·

=:::=wo

~:~~:::

commands from the system at a time.

1'..\t

Scache or Bcache or both are probed to determine what must be done witHitbe

command.
,:{~ : ~;:l l : : : : : H: :l~lt; : ; ! ! l! !1t.
• If nothing is to be done, the 21164 acknowledges receiving:J.ij~· comman8Ittllh
If a Bcache read, set shared, or invalidate operation is r:•f~d, the
21164 performs the task as soon as the Bcache becom.e.$:...free:;:\Wb.e.

•

"\ilj!!!!~t

~::::a:t~:~~wledges receiving the command at thJ:ll~~jiffa;•::~~~~':. ~:~~e
There are two miss and two victim buffers in the BIJ~~~l!th¢!~::~~~·::1~t!?one or

two miss addresses and one or two Scache victiIJM@dd.resse~19r.v.:1(JO two shared
write operations at a time.
. ~::~~!!lt~r::::::::t:~!i\!l::lll:::llHh::::.:·:::ttft?:.
•

•

412
. .

A miss occurs when the 21164 searchesdit~fcaches btitidoes not find the
addressed block. The 21164 can ·'ijij~11:~ tJ&:::w.~.~es to th~ system.

An Scache victim occurs when the 2 £t$t::Jl~~ll~di~ijk~ a dirty block from the
Scache.
.. ,.;.,.;.,.;. .
.. ==:::r:t:!:i!l::t:-:......==: :-·

:::~1!:~:::: hlterf~1'::::~1f
an

,.:'optional backup cache

(Bcache). The Bcache interf'.~~~fis :rii:iQ~}gp of the following:

: ~~::-::~::::~:'~~§;:~1th
•

4.1.2.1

the system mterfacel

Tag and stat~::=:6~m:j)f9!_ ~:ftit.mwi:::=·hit and coherence

;c:::ct~~~!:11~ttit}~;6J

signals

A Bcache victifu i~tlhe;t~d when the 21164 deallocates a dirty block from the
Bcache. E*ch=:qg)~f'a Bc;.3.ibe victim is produced, the 21164 stops reading the
Bcach~:Jjntil th~==:~'i:$.te.W.ltakes the current victim. Then Bcache transactions
.·:=::t~t:iii:)~·~x:::::::!!l!:::t::\..
.. . -..;. . . ..
:::Jlf"'.Eit~pal logi'<fam~Y help improve system performance by implementing any
. :tlF:=.. nunib.er of victHfifbuffers. The victim buffers hold cache victims and enable
t::::tL:::.. the.d~i~he location to be filled with data from the desired address. Data in the
. :::::::::::i:t::t::::::v.i~~ buffers will be written to memory at a later time. This action reduces
":t\fM.~. time that the 21164 is waiting for data.

'%{}'~}

4-4 Preliminary Edition-September 1994

·:{\If

Signal

Description

cpu_clk_out_h

A 21164 internal clock that may or may not~\~&~ the system··~l®.\..

sys_clk_outl_h,l
sys_clk_out2_h,l

A clock of programmable speed supplie<!.J~ th~ti~:rp.al interf~~~~~~
A delayed copy of sys_clk_outl_hJ.~fpMi!~i®.l?:-Y i~:::~·ammabi;··
and is an integer number of cpu_cJICoutJUl*ri.9~·.·
:-:·:·:·:·
.·:·:·:·::· ··:·:·:·:·:·:·:·:·...•:·:·:·.

The 21164 may use ref_clk_in_h as a reference ~i~a~~k,~~dhen .JJ~~:=~ating

4.2.1

c;~-~::tt_h,l and sys_clk_~:~Jt.~~it?tii!t;\\tj:lct;t~ffe1

The 21164 uses the differential idput clockOm.es osc_clk_in_h, I as a
source to generate its. CPU clock. Th~tjppu:f=~s~lm.~ls clk_mode_h<l:O>
control generation of the CPU clock a·it1-Qk,d i1{:Tijble 4-1 and as shown in
Figure 4-2.

.jtlt;'tw,\ttm;:~~\lt ·

Table 4-1 CPU Clock Genetitk>n ControU~~)·
.··:··
;::::::::::::::·:·=·=~=::::::::::::::;:..

Mode

Normal

Usual operation-CPU clock frequency
is 1h input frequency.

Chip test

CPU clock frequency is the same as the
input clock frequency to accommodate
chip testers.
4

CPU clock frequency is 1A input
frequency to accommodate module
testers.
Initializes CPU clock allowing system
clock to be synchronized to a stable
reference clock.

A clock source should always be provided on osc_clk_in_h, I when
signal dc_ok_h is asserted.

Preliminary Edition-September 1994 4-5

Figure 4-2 Clock Signals and Functions

21164
osc elk in h, I

.....

clk_mode_h<1 :0>

CPU Clock
Divider
(/1, /2, or /4)

-...,

ref_clk_in_h

Digital
PLL

_:;·:·.:.•_·.:.:~.-:.:_:· :~·:!·:~-'~:~·,i·:·:· :'•Slyrs~~~\~\cfli~k:·

1..
.-------------j-•-l-;;,_'
.
_•-·.:
•
:
w
1

irq_h<3:<h

System Clock
Divider
(/3 through 115)

__,

. h
mch- hiUrQJ
-pvvr_fail_irq_h
_..
_Sl:_s___
m_ch___
ch_k_i_rQJ..._h_ _ _ _....,_

sys_reset I

_..

dc_okay_h

4.2.2

,,JJi\\\t\~\\\\\\\}::::.

.:· : .:.. :... ..:·:·: '..

out1 h, I:...

s yste~mtMW\\
~~~» ..,:r~ 1~ :~l: ~.:-.:.~_.·.~:~,~.:~_:~_.: ,_:._:_:·:·:.·._:.'.:_.·:·:·:._..:_.·':.:__:.:· ·:· :<{~1>·
...

Df:~W

···::::t@f"""::::-::,.. -~-----+-s.....y__
s___c_lk=_o_u_t2_____
h,_I,.

(~JWJ~.gh 7)

····: =~H\\\\\\\l>

{ijc::Wi\{4' '

s:;~;.~~;:~~~~:;:~~!rs~::e!!::;~~!~~U::;~~~
1. The divisoiV~ to_.,,t.~r h{~~~:Ptained from the four interrupt lines irq_h<3:0> at
power-up_J!.S iiit~d~~ijii" Talj}~ 4-2. The system clock frequency is determined by

divi~i;\\\:~'';Jf'CPU clock frequency.
··:·:'\{\\\\\\\):·

4-6

Preliminary Edition-September 1994

Table 4-2 System Clock Divisor
irq_h<3>

irq_h<2>

Low

High
High
High
High

Low
Low
Low

High
High
High
High
High
High
High
High

irq_h<1>

Low
Low
Low
Low

High
High
High
High

::ri:.4--3

shows

the 21,JF~;\~,:·em

clock on a uniprocessor

Figure~ 41p1t'~ta:~~~,Clock

1j%l;~i~~~:~ft%1 ~~~~~

rt!!:!~rri' :\1ft@, -A-S-IC--

:~~ 11'i'.Jt::;wt~-'-~--

Bus
ASIC

4tt&,\\),if>
LJ-03676-TIO

Preliminary Edition-September 1994 4-7

4.2.3

°:!:Y:te:v::m~~~=_outl_h, Iis the source clock for the delayed ~m

clock sys_clk_out2_h, 1. These clock signals provide flexible timi:qg.Jor syg~
use. The delay unit, 0 to 7, is obtained from the three interruptJ?.!gn~uu.~•zt,
hlt_irq_h, pwr_fail_irq_h, and sys_mch_chk_irq_h at power;~[P.p as ii'§~d{nilh.
Table 4-3. The output of this programmable divider is symm~ftJ~:, if the divisoill~l~=:
is even. The output is asymmetric if the divisor is odd.
··\:~{\llltt::..
.JlW
.·:·::/lf\::::..

Table 4-3 System Clock Delay
sys_mch_chk_irq_h

pwr_fail_irq_h

Low
Low
Low
Low
High
High
High
High

Low
Low
High
High
Low
Low
High
High

····::::~~~~ltt.~.:[:~:~.·: :~-~.= =-

il: !l:l ~ ~r= :=·:·: : '.'.'.:l!l!l! jl l:lt t~t : : :.....:::=:·.

4"2"4n::r:l~: p~:: ar~:!'~~:~;;"so that other CPUs and system

·::t?'

devices can be sYH¢.hr9niz.~ltdh1:. mu1Uptocessor systems. If a clock is asserted
on signal ref_clk_iri!Qtt.J.ie:ri>tij@d~YS_clk_outl_h, 1 signals are synchronized
to that reference clock.··=·:1$1~1tr.efetMice clock input should be connected to Vdd if

:ei;:~~sJt::i:t~~-clk_outl_h
frequency with the
P.tlif

ref_clk_in_h

signal by Jne~~.
dim.M.1 phase-locked loop (DPLL). The DPLL does not
lock the i\Vb fr~d\i.i:n~i~.~lJfo.t rather, creates a window. To accomplish this, the
frequetjs).%9f sigilif:i§.i±blk_outl must be slightly higher, but no greater than
. ::::JJ,M~:Q,% higfit:r.:1 than that of signal ref_clk_in_h. This causes the rising edge of
. :::~f~@?\~Yill~-oiit~ll~~W.. drift back toward the rising edge ofref_clk_in_h. The 21164
.::flt~? detejfi when tK~Pedges meet and stalls the internal clock generator for one
.:~j]lL::..
os.q£,1k_in cycle. This moves the rising edge of sys_clk_outl back in front of

"WQfl;\c:~:~in_h.

4-8 Preliminary Edition-September 1994

Figure 4-4 shows a multiprocessor 21164 system synchronized to a.:mference
~~

Figure 4-4 Alpha 21164 Reference Clock for

ref_clk_in

211 s4

1_.!,!';·'~.~=:,··'=',~.',=!.·,=1·!.·',··.1~',:.·.,:~.:
Multiproces1~~~,
---il~,lt

sys_c1k_out H_=,f,i.~:.•;_=;,=!,•l=· .:fi~;\ {\~;3;+

--'~.~. . .~. . .w0li:

Reference
Clock
---

A\-(:::.·.:,•.

ref_clk_in

A(;\{Wi:~:\:!~~ut

,.'_!::.i.:-@t'}

Memory

ASIC

Bus

ASIC

<l}·
t\)tlJb #@;h

4.2.4.1 Reference

LJ-03675-TIO

Clock===e~-;~i!l~~~t::::~t==··

This section ~qn.t.ai~W:~i~Q.J~1prnt~alculations of setting time in systems using the
DPLL for ~yjMi¥4mr?!atH~nbt-

. .o#ti. h;'~ stabilized (20 cycles after irq_h<3:0> have

After sy~!lik

settl~.dJ tli~r~MWilI be}~: delay before sys_clk_outl_h,l comes into lock with
ref_G.Ut_inJlU:f:th.~.JA\M cases for this event are described in Section 4.2.4.1.1
andl::siction 4:=2~ijfi~~2=~

'ttl'\i11r

Preliminary Edition-September 1994 4-9

4.2.4.1.1 Case 1: ref_clk_ln_h Initially Sampled Low by DPLL Whe~~::the
DPLL initially samples ref_clk_in_h in the low state, as shown in Figilii~~~+-5,
it slips its internal cycle repeatedly until it samples ref_clk_in_h in the ·ajgp.
state. After it samples ref_clk_in_h in the high state, the DPL~.:i\iy~jp idf\,

: : : : 4-5

r~_clk_in_h

o;tt{,,~:::tWt~I~,,

Initially sampled Low

CPUClock
(lntemal)

sys_clk_out 1_h

ref_clk_in_h

I __
4

A\%%

ilq:qy

__!

----------i~-~~!~~~-~t~-:l.,.,.,t;;!11_iii::~~-t~l_l~~-.~~====_·

Ml.0-012303

----------

The timing diagram sho.w.ima sys:C.Ut,;;;.9utl_h,l ratio of 4.
-:{~~~}::.

::::~=t~~~I~~\=:·.

r·

···::==~=tr

(~faw.:st)fjh~~!li®tte

The worst case
at which the DPLL will slip its
internal cycle (the."f¥~~ncy==~it\J~hase:··slips) is calculated from the lock range
specification of 0.35%. ··=::lq~)dfect>'i@· average of 0.35% period is added to each
sys_clk_outl_h:tkP.~r.4.Qd lifii.UJock mode is reached.

(*'") (~!..•.:.t· =· :·=Z· ·=.· .=.·=·j=·: .~.n.:· · ·=:· ·=.:· ·;·~ ' : Re/C:::•wR0.~3f'/Clo•kPeriod

.£/illlllllll~lb,e··:=;Jf&f:~q.~e clock low ratio equals the portion of the reference clock

.·=/~IJf.

l~~fiod tllat~~~f_clk_in_h is low.

<C\~)-fitl~g w~rst
the

case ref_clk.._in_h duty cycle is 60/40 to 40/60:

· : : : :~ i~l ~ ~ ~j: :~:~)

SettlingTime = 0 · 6 *Ref,i~aEPeriod = 171 * RefClockPeriod

4-1 O Preliminary Edition-September 1994

Depending upon the sys_clk_outl_h,l ratio, the DPLL may come i_g;\p lock
much more quickly. The DPLL may insert phase slips more frequeii\'b. at
smaller sys_clk_outl_h,l ratios.
'\}%:::..

4.2.4.1.2 case 2: ref_clk_in_h Initially Sampled High by op,;::et[[lm:Wb.;hll~lbe
DPLL initially samples ref_clk_in_h in the high state, as ~ijj~n in···mgaf~[ji.ts,
it will not slip its internal cycle until it samples ref_clk_ifitlli in the low sta•~
After it samples ref_clk_in_h in the low state, the DPLL saii~Jp lock mod~i~ljil~
. ./f}{\:::...

Figure 4-6 ref_clk_in_h Initially Sampled High

.··::::~~~(jjj[::::ti>

··:::;::::::=

~r'.•t;\i'~-i\\f;il

CPU Clock
(Internal)

sys_clk_out 1_h

__r

ref_clk_in_h

ML0-012394

The rate at whi~h sys_qVf4.outl~H~\lllgfilns on ref_clk_in_h depends on the
difference in freq#.ency of%g~;t_two sigifils. Assuming that:

:!~~::~~~~~~~:~e~~i~:~c~0=g:~an

and thatjyfil:;:~l-1~!t~n of 200 ppm from the specified frequency for

ref_c,;JB2~jjjf ~::::~SW4.~Ik_in_h,l,

Then the j~fiprskiase ·:\i!nallest) frequency difference is calculated to be,
o.0017J,L- :~bP.i.fu - 2@ppm = 0.00135 = o.135%

··"'°'""··

4;\·~t.t~.-~.: .:_.:._:_:·:_._•.:_:·:·:.·•.:.·._ :=:_.:_:·~'.:~_ ~:_.: ·;: :·:l_:~i.lt~: : : gTime

3j,jfHt%t,,

:=..:__·:.:·
._.:. ._. •••••••

= Re/ClookHigh1J1Mi;:•fClockPeriod
Note _ _ _ _ _ _ _ _ _ _ __

,jj[jj~\\J::/ The reference clock high ratio equals the portion of the ref_clk_in_h

''lit'.lqTu{l'i;'\iJ{j\~eriod that ref_clk_in_Ji is high.

:(::ff::..

Preliminary Edition-September 1994 4-11

~sumffig :~t::::i:e=~f:::::;::~ ~:i~ :::l::k::::#he~~'h

3Ph!:j~=!i~~~::::d:~ri~~~::r:=::~address r~-:~~I!::,:::'~~i,

wrapping characteristics of physical addresses are als~f[pescr~~h=====·· .·===· ··:·=

4"3"1P:~;~:I :a:::~ ::~~~;45is divided mto U#Jj~:~sltl*T
pq;xl~~l addf®'=~~~==~;:~~::~::o~:::o:::~~-:::nd ~~:~~ a:~:ess space except
1. The first region is the first half of the

It is treated

for a lM-byte region reserved for Cbox:'lf~.~ Ifrn:[::treated by the 21164 as
noncachable.
=:@[~:::~~::ll:t!:j[jj}t:=:·. ··:·===\::[~:t:::::J:·
3. The third region is the lM-byfifregiorF=tj~~;rved for Cbox IPRs.
In the first region, write invaltaitU:::~bing, ·-~~te merging, and load merging
are all permitted. All 21164},lcesse·s===~~Mpis region are 32- or 64-byte
depending on the pt@gramiiiii9l~:::!>lock sii~f

The 21164 does tj:9t.._c~cfiij,ti?...t~·:=:~l~~§~d in the second and third region of
the physical addr~sij)~pace:;<~)l§.4 r'iiid accesses in these regions are always
32-byte requests. Loltdim~rgfitgi[~i~t:Permitted, but the request includes a mask
to tell the syste~.-.~P.vir~im~p.t vilHch INT8s are accessed. Write merging is
permitted. W~imPiief.~~s -~f~[li3.2-byte requests with a mask indicating which
INT4s are ac$lil1ly tP,gdifi~d. The 21164 never writes more than 32 bytes at a
time in nonc~ft!.eq:~~~ilace~t:i:i:~

The 2116.lfao~=~:::ij~~:,b..rw..dl~~st accesses to the Cbox IPR region if they map to a
Cbox IQBfAccess·e=§tttFlh"is region, that are not to a defined Cbox IPR, produce
. /flUNllEFI~P.. results. The system should not probe this region .

. :/l~::::~::i~::r=·:·~;611!::H ~~dW~:~:the 21164 physical memory regions.

'111\' *'1,,:::f

4-12 Preliminary Edition-September 1994

Table 4-4 Physical Memory Regions
Region

Address Range

Description

Memory-like

00 0000 00007F FFFF FFFF16

Noncacheable

80 0000 0000FF FFEF FFFF16

IPR region

FF FFFO 0000FF FFFF FFFF16

Write invalidate cached, l~~alJt9~l~.~h.
merging allowed.
. :~j:l:::?· ··.-·=·====:=::tf@t:i::jjj~:ii::::i\..
Not cached, load merm~blJimited.
···--==t@\.

not ;m~ :~f~it~uterface . ;111;

Accesses do
unless an undenneff'lbeation iifa&essed
cwhich produqiij:''UNJ)DFm~P::xesults).
::::::::::

432
""

..::::::::--

··:::::::::::::::::::::::::··

D~~ ::::~;!res that wrapped read op,,:~\~,~~t~:"~n INT16

boundaries. READ, READ DIRTY, and Wh.USH comffii~ds are all wrapped on
INT16 boundaries as described lii.fe. Th~tf:3)id wrap otders for 64-byte blocks
are selected by addr_h<5:4>. They ~t@i,.. ···==::~:~~(\l~\,,.

~: ~: ~
::

For

.@,.

'%tft1mt,~i:qr,·

~2~~~~hlocks, xJr~~;:~:;::: sele~d
the

=~~ BL~!;~:~~~::CK

by addr_h<4>. They

commands from fue 21164 Me

not wrappe~kdfb~Y. ;fW~y~t_wrlte INT16 0, 1, 2, and 3. BCACHE VICTIM
command~f~pfOvll{ij\\:th~ <iiijf with the same wrap order as the read miss that

produ~ed :!l:~A\~~~j~jj:l~f::=· ·=:j!:l·l 1!1~

4.3.3 Noncjf:hedMl~.a~.,,::IJ>erations
Rea@~jjj§perati'~rl~~lfij{~hysical addresses that have addr_h<39> asserted are

;:jft)j'@~{l:r~~-~.,:: ~:::~d~:=~~ie (~~h;;, ~";e::~:~;;i~e:~eo~i;,.:~:~~d
0

. J~\Jf'..

t~Unoncacli~HVinemory from being merged into a single 32-byte bus request,

ttltl!\Tu> dllrr~~~eu~:~i;:~~-e;:i;~m:,:;;!~~~=:~~~:r:~e~~p!~?o!.
--=:::::~\ifl:::,Jogether as it can and sends the request to the BIU through the Scache.

···==t~l:!ijjjj:\\jlj:::>·

Preliminary Edition-September 1994 4-13

Rather than merging two 32-byte requests into a single 64-byte requestf~the
BIU requests a READ MISS from the system. Signals int4_valid_h<3:0.f::::.
indicate which of the four quadwords are being requested by software. Thi~t.
system should return the fill data to the 21164 as usual. The 21lft4td9.:~-~ n=6t~:L
write the Dcache, Scache, or Bcache with the fill data. The req1',,$te~flli~ti~IIh.
written in the register file or Icache.
··.··=·===~=t~~~:~:llL.

/tJi'.
Note
At'f\\ih
A special case using int4_valid_h<3:0> occurs dutiff,~::9l~llt-~:h:==:Ait~>1n

this case the entire returned block is valid althou.drmt4liMiU~3:0>

indicates zero.
.·.·:·:·:=:=:·:·.·•.

·=tmt· :_·~_..:_~_l.l.l.!.1.1.1.:_v . .·.·.=.~:_~.!_li_·~.: _;!t= = = = =·

··=:===~==:::::::::::::~:::::~:~:==:·.

434
" "

::·

·::t~~~~t~I~~~~~~f

N::~:~:ti:i: ~~=~:i:~=esstw>iqpt~,~~::!r~>
asserted are
Wfi:w

not written to any of the caches. These
op~fi:\tw1s are merged in the
write buffer before being sent to the .~Y.~tenEllJ.fi§.oftVJite does not want write
operations to merge, it must inserij\{B!],~t)\11\fB{~Mtructions between them.

When the write buffer decides ~~t=l~te d'!tAlllt~hP.~:~ached memory, the BIU
requests a WRITE BLOCK Q•f-lngb~~ch datiFtycle, int4_valid_h<3:0>
indicates which INT4s with~p{jhe INTJ~tJvere actually written.

44
"

B:~~~16~~~~!;~'~:~\~~t{~P. , 32M-byte and 64M-byte Bcache.

The size is under pto~µi cafi~l.. and is specified by BC_CONF<2:0>,
(BC_SIZE<2:0>_>.::::\:/:t::::==·=····:::=\:::tllli!!lht::.......\}/·
The Bcache b}gjk::·:Siz-~flbiay coiji;ist of 32-byte or 64-byte blocks. The Scache
also supports:~~W:ther:~:32~b!t.e or- 64-byte blocks. The block size must be the same
for both apd i§fa~_eJ~pted 1'~i:ig SC_CTL<12>, [SC_BLK_SIZE].

Off-the:::~l~if ~i~lt~~;;;~il!:~(SRAMs) may be connected to the 21164 without
.. ID.!IDY -~l. compo.IMHfJ( although fanout buffers may be required for the index
·:illiih~~~k Th1~~~:$.i.AMs are directly controlled by the 21164, and the Bcache data
,::/n~r·· lin~idire cori1Hfoted to the 21164 data bus.

{-1~;1L,!llb.
P;a~~~:i:;~:~t=~~J=~~d!~><=~~:.:;~;~~~d:d
··:·::::tlHie
Bcache interface.

''~t\1,(@i

4-14 Preliminary Edition-September 1994

llj

The system designer uses the signal lines needed for a particular si~~l Bcache.
For example the smallest Bcache (1 MB) needs index_h <19:4> to 8'.qgress the
cache block while the tag field would be tag_data_h<38:20>.
··:\fl:t..
Only those bits that are actually needed for the amount of c~~~@aH~Y~~l!!11wain
memory need to be stored in the Bcache tag, although the ..~l~f64 us·Ern:::~MJith~.
relevant tag address bits for that Bcache size on its tag cQmp~re. A large:?\lt::

::c~;::::::s:d: ::::'1~::7:;8~~:::;~:;~:::,.\}ransacJ!
requires two data cycles for a 32-byte block or fouff~~~ata .4f.il~~::for.. ~{ 64-byte

4.4.1

o:::~ate Tag Store

AffJfo¥&t;:: *

(\:+f};tff)Y

In systems that have a Bcache, it is possiijJ'=· to bmUb~. fwrcopy of the Bcache
tag store. This data can then be JJ:~ed tQ:~::likr requestl~)?oming off the system
bus to the 21164.
·\{:? /)\. ··=:::q:~tj1~j~~~~~~}::=:::..
· : =·
In systems without a Bcache it is pos=slbl~L~o bfilltt~ full or partial copy of the
Scache tag store and to model t~Uh!.Qpteritij~~jg(Jhe. .=scache victim buffers.

4.4.1.1

F;:~~~~=~ ~::c~~o:P~c::~!l~:! contain an entcy each

for
Bcache block and each vi¢J)fulititt'.~r~. Each ·entry would contain state bits for
the VALID, SHA.llED, add~~~l.?IRTY . =:a~~ bits along with part or all of addr_
h<38:20> for a Beach.e bfoal:t/;L'he patf of addr_h<38:20> stored in an entry

::::::~:'!ti:~l'!~;~ Scache duplicate

tag

store may be

maintained. The . :ftt{!@§J!ach~{gµplicate tag store should contain three sets
of 512 entrie~n.e :f&Haach the three Scache sets. It should also have two
entries fot~:#lk:tW.i:~~!$caclMtV!ctim buffers. Figure 4-7 is a simplified diagram
showing W~ sigq,flip!s of interest.
1
1

t\,111:::,;;,~&t,~

<tl'~*itl;\ji
'

%@W'

Preliminary Edition-September 1994 4-15

Figure 4-7 Full Scache Duplicate Tag Store

scache_seLh<1 :0>

addr_h<39:15>
(Tag Data)

,, '

' %'.

.·.·:·:-:::::.··...

_:_:.:_;,_.;_::_._

{\--l'®,

t :~.'~-~_~· [~
1

tag_shared_h,
tag_dirty_h,
tag_valid_h

··_.::_1.•.•.•1.r_1r1

victim_pending_h
ML~012395

4-16 Preliminary Edition-September 1994

The system should use the algorithm shown in Figure 4-8 to maintAjn the
duplicate tag store.
.,\~~}\.
Figure :

Duplicate Tag Store Algorithm

AlJliiMJW;;~~ilJt~lt

Preliminary Edition-September 1994 4-17

4.4.1.2 Partial Duplicate Tag Store

.Jl\.

System designers may also choose to build a partial duplicate tag store··:·
as that shown in Figure 4-9. This store contains one or more bits ~f tag dij~
for each block in the Scache, and for the two victim buffers insi~elll®:utw..!. \:]~~\:.
If a system bus transaction hits in the partial duplicate tag st~ii~· th:~:if=~-~~:ldililit:.
block may be in the Scache. If a system bus transaction mis~~§Iw. the partiaf=={~1h,
tag
''"*Jt\\~\l;>
.~Ji

duplicate store, then the block is not in the Scache. . . .
Figum H

Panial

Dup:~me Tag Stom -

~~~:~::

SetO

•

.{jj~j}·

t4?~l'ff)Y

~ t)~~ !'111} ~
··:::::::::::::::;:::~

:::=::::::,..
··:·=:::ttil
··:::::t:~~l~i~ilk:
. ·.

addr_h<m:n>

ti~:.t.:l,~.:::.:.:

Set 2
~

.:=..,=.,',::,:·.:··::.....:·.:·::..::···:::..'·::·

(Part of <39:15> Tag Data)

·{f~~}·

Victim
Buffer
1

MLCHl12397

systems ~. tli~t~ .Jfihy be}~veral caches on a processor module and several
more in j~ltii)tgl§.~~!.:::~Jitems .

.
Aiffei!~~~r:~!;!;~:i~:a~~:di::t !~:::::~e~u!t•~:~i::: !:che
.
lM)J
:J:1~f::·· an
(PAL&Qij~) instruction. The 21164 maintains coherency between the
Dca~I~ and the··:l~foache.

. /:ff?

'=t::~iljj~j~~~~~~j~\%::::::Jr~1~·· system does not have a Bcache the system designer must create

····:::=ttli~:~hanisms in the system interface logic to support cache coherency between
lit~~l~~.~che, main memory, and other caches in the system.

··::::\llt:·

4-18 Preliminary Edition-September 1994

If the system has a Bcache, the 21164 maintains cache coherency b~tween the

Scache and the Bcache. The Scache is a subset of the Bcache. In tliij~l£~Se
the designer must create mechanisms in the system interface logic to ·,~§pport
cache coherency between the Bcache, main memory, and other{~~flV~~ iH}\be

4.5.1

c:;::~oherency Basics

<{tt'~WEW{tf~ll\1

Alpha 21164 systems maintain the cache coherency a.pJJ.::J1ieraf¢hlt:.~hown irf{f

~:~e::O).Cache Subset Hierarchy

w:¥:,Jtl\'\\fk~:Qf<

.::::~ti~~I~I~t~\::. .
. . .-.-. .

System

~: :.:_,:.::._:·.:·.:.:.:_:.=:.:.:.:.:.:·-:·.:_:_:_:=:~:~: : :.:.f
..:.::.::_::::..

····:·:::::::::·:····

Main Memory

MK-1455-01

Preliminary Edition-September 1994 4-19

~si;:~:~: ~eP:~::;~:=n::r:::e~o~:;:c~:n:~ kee:ltt!iB
•

a subset of the Scache.
.·..,/~hl\t::,:,.,.,. :·: t: l !l ~:t:.
If an optional Bcache is present, then the 21164 maintains th• Selfohita~tij}:,_
subset of the Bcache. The Scache is set associative but is ..!~~p~ a subsef'df{~:~:~j~\.

•:;~:;:;::s~!e~::~:~el:::=~::Pm~:~:a~:::=:!l~main :11

•:~;.;~~~:rac:::t~f::y :::~d ::::,:&'~·~~:rt=:
8

with

The 21164 requires the system to allow only oqjichiijg~. . tO.''aiftlock at a time.
This means that if the 21164 gains the bus ~Q:~~ad 01~'::wlnW. a block, no other
node on the bus should be allowed t<t:access'q~hat block uiiilfthe data has been
moved.
.. =:::::::::: -t!:t: : : :,:. . ,.,::::tlllj:t:n:::::::,,..
.
The 21164 includes hardware mechanism~ft(k$.µpporfj~everal cache coherency
protocols. The protocols can be sep~m~4.. inttFi.W~tclasses: write invalidate

::~ ~:::~::: ~:~:::=t::3<'4~cy}protocol.

The write invalidate cache c9ljj;~~:~Yh1t2tocol i~ best suited for shared memory
multiprocessors.
-:@~!:::1:111::~~~:::\...
"'''\f~!::)::·
The write invali<late prqtQ:~ol aH&\¥$.Jor shared data in the cache. If a Bcache
(optional) is usedlth~.P. a.'.'dii.PJ.i.cate.''tik::~tore is required. If a Bcache is not used
the duplicate tag slH(~bi~ noFf:@gµ~recf but the module designer may include an
Scache duplicate tag st&f@h,.. ":::'\f}·
Requiring the.,,qi[p]iij~t~!t ~~~::iW..;re if there is a Bcache allows the 21164 to
process system(commifi~,. in the Bcache without probing to see if the block
is present (sy$~n~/Jjwc tbpws the block is present). This results in higher
perform~~ f~~:tft~·se t~~sactions.

If a Bc'-~Rt is ~~i:::~ffiia::~the module designer may include an Scache duplicate
. ::f::lmit§tor~:::t;ijMw.prove system performance.
_.,:::l!~l[:jj:f:':··"Fi.~i§[:jcach~:::C@berency Protocol
.J:!IE::· Thi~jj~jprotocol is . best suited for low-cost single-processor systems. Flush
. ,.,,,{:{jt~~::::::.,. ptqtocol does not allow shared data in the cache.

. :,::\Jjj:[lt~~h protocol does not require a duplicate tag store. Because the duplicate tag
sfu~~U~. optional for this protocol, the Bcache is probed for each transaction to
detei%Une if the block is present. If the block is present, the requested action
is taken; if the block is not present, the command is ignored.
4-20 Preliminary Edition-September 1994

Section 4.5.2 and Section 4.5.3 describe the write invalidate cache ~Qberency
protocol in more detail while Section 4.5.4 and Section 4.5.5 provid~~jj[~);nore
detailed description of flush cache coherency protocol.
\llt.

4.5.2 Write Invalidate Cache Coherency Protocol Systern§j:::~t:L:t:l~lt@j~.:·:=;:··~.lll!)ii:t,

All 21164-based systems that implement the write invaliq~(ij~'.'cache p;~fij~~&tjjj:t,
must have the combinations of components listed in Table'===•k For exampleHm~
a system such as that listed in write invalidate (3), }µ\yjng ali\S.'-~~he and ·<:ff
Bcache, is required to have a Bcache duplicate tag . $.@fe:~:S\d. a loek[[[jegister.

Table 4--5 Components for 21164 Write Invalidate Systemi\:

1i;!f' !!\f.wJt' ,

Cache Protocol

Scache

Scache
Duplicate
Tag

Write invalidate (1)

Yes

Write invalidate (2)

Yes

Required

Write invalidate (3)

Yes

Required

~r:e:s::~:s

Lock
Register

1!llh::~~:!t':

: 0 exter4f
store, or lock register. The
21164 must be ~~de aw.:#.i~ of alfii.mw;>ry data transactions which occur on
the system bus:{$ysterrtl~~tuses aiF~iNvALIDATE, READ DIRTY or READ
DIRTY/INVA.LJDAT.:$.ttrans.itfi9µ to the 21164 to maintain cache coherency

::i~=l~~:!'1~~;~:'&\i;~~-

This syste~.JH!§:d!~ eit~rpal Scache duplicate tag store and lock register.
System log!JHrn~~j:~~e dtipijcate Scache tag store and lock register to filter out
unneedecltii-ans.aiti.od~,, to the 21164. System logic only initiates transactions
whic~. aff~tt ~~he t~berency and maintains the lock mechanism status.

writJil~i6v~~:iaii~:::3:::::tt~~r::::

. . ,:,: : : : : : :,:,. . 'Tiliij~j)l~.~em h·:~:::::h='. ~xtemal Bcache duplicate tag store and lock register. An

,,/~lf~ttfI$.~acli~4lµpJicate tag store is not needed because the Scache is a subset of the
. ,,{~@?..
·.'J)i~che. ·Tl}$.}$ystem operates similar to the write invalidate 2 system, except

,,+if,,..

..,JWnt the cache is larger.

W't'j't~:;,iJli·

'Wff

Preliminary Edition-September 1994 4-21

4.5.3

w:!!~ ~~::::~ ~~c=~te: !7~:~~:Sead and write data as ;l,
transactions were going onto the system bus to memory or 1/0 mqqµJes. "\\{!\.
!';~:'!:~~he system bus is the point at which cache cohere:;:ir{fi~-Jt~t\lli;
0

Table 4-6 describes the Bcache states that determine cache coR§'ft.µ.cy protocol \It
for 21164
.,,.,,%...
4)~1'

'%''\\·+
Table 4-6 Bcache States for cache COherency Prot'~;]lf\%\\'td?

systems.
Shared 1

Valld 1

Dirty1

_J~~J

State of cache Line

Not valid.

Valid for read

..·.·.·.·.·.·.·.

..::::~t~:~:#i\..

:-:·:·:·:·:·.

.....

.·.·.•.·.•.·

"\\\\\\\j\\}}\\\ff'

OI\·=··,:::¥il~~- This cache line

contai~:J~e onlj@~hed copy:-::6t1!!~he block and the

copy ir{mempry fif1$m~ical to thls line.

Valid for reii::~mL~~~\\~dPtr~tions. This cache line
contains the onli{~~~hed·::oopy of the block. The
conte:q.jfijfJ~b.e biooi{!~ye been modified more recently

This block
.ilUrufother CPU's fifohe.
1
/:t~lf.~d ;~;::~,,~:.Pr write operations. This block may
<H:~>
·.:,:::q~j_n anoth~#PPU's cache. The contents of the block
.·:':' ' ' "·· hi'fltp.een modified more recently than the copy in

~~t~~~~ations.

··~:::::::fI:::::tt:em~~1~~}

..,.\f~\ \:_~-.~-,~.r,~:,
. ::t~;f..,.,::::::::t:::=::::::::,.,._
~::::::·:·=·:;::::::==~~~~~I~~~~~::

..:,..

,=:=,.=_:..
::_..
:: :'
...
.. :: ..
:·:·
..: ·

Note

Unlike sJI~ Qt.ff.t;''s~ltems, the 21164 will not take an update to a
sharedtblo:iitSfit ins.teid will invalidate the block .
. :::::::.'.tl
··:::::::tt\tttHf:::::::

'"ttti~4\r'*j
··:::::::::n:~):·

4-22 Preliminary Edition-September 1994

may~

4.5.3.1

~:~=~~~o~r:!:°~1~:::h~~::s that can occur as aresult,;~1164
transactions to the system.

./~~~~~}}::::::::·:·.·.

Figure 4-11 Write lnvalldate Protocol 21164 States

\~ltlf\

··:::::::::::::.

..""ii.1%§:4~.,J.)

¥;';~::,l~J

(CPJ Read Operation)

..,.,:;::::::::::::::.,..

s~~pf\Y~l~:}k::·:·.

:[ [ lj ji .:_[_l.=_:·_: :·f: :_.: ·: :.:_;_~_: :f[~l[l~ jJ

(CPJ 'f.t.t~ OperattO~lk:::,.

... Wite Block"* (S)

(CPJ Wite Operation)
* OptiOMQ!W:Jhis trdrlJ:mro. can be configured to occur wthout

a SET DIRlttq::nmafiaf~~ing issued.

[~;i;~~~e~::e

_______

M!_0-0_1_29_34
_ _ __

Preliminary Edition-September 1994 4-23

Figure 4-12 shows the 21164 cache states changes maintained by the 2.M,,64 as
a result of transactions by other nodes on the system bus.
·=t~:lh.

[f)itf$\fit ~\1_~.l.:·.= ·=!~_ =~:_~:'_

'
*
•
'
~
~
.
~
,
~
:
~
:
~
_
.
=
~
.
:
~
_
.
=
'
=
'
,
_
(Il Readivi1~f'

Figure 4-12 Write Invalidate Protocol System/Bus States

(Il ~attoo)
INVN.IDAlE

REN)

v.fite

.
DIRWJ~lt::::::;
..

.='.='.=,_·=.·_.=.-= _.=·. :·_:_.·'·,.=:·

INV1'4~ '1\:1:Jfi'tij~ifzyp
(BlJ; Wite

SETSH.ARED

~~iik:::::, ··=·.:·:tllll::::::::::::::t::\:..

. REPD DIRIY

REffl~PlffiX l~l:::::t:b:t. . ··===::::t =· (BlJ; Read Q)eration)

(Bus Read Operation)

,;~~~~? (Ill=~~:
4.5.4 Flush Cache

c9w.;~,)'b2;:ta1 Systems

All 21164-based syst~iifi.:::l.l~t .iAfftJement the flush cache protocol must have
the combinatioq~j~~f)WP.J.POOtb:t.~ listed in Table 4-7. For example, a system
such as that li~t~cfii'.EDu~p (3)f'having a Bcache and a Bcache duplicate tag
store, is requif~d tqfff:iivEd.. lock register.

\'~11\~-,;:itfw111

4-24 Preliminary Edition-September 1994

. .='.·. . ..·.'.·_.':.=_ .:·_'t=.:_.=.='.=
·'!,···:!
,·_
__ ......

{~:l::\l\.

Table 4-7 Components for 21164 Flush Cache Protocol Systems

Cache Protocol

Scache

Scache
Duplicate
Tag

Flush protocol(l)
Flush protocol(2)
Flush protocol(3)

Yes
Yes
Yes

No
No
No

Bcache

No
Yes
Yes

'::l(tj.·1_1,:_:_l•.1,1,l:}:l:~::l::l~:::

:: 4t,\\\
_
_,,,::::&tfm>::'%.{,fl$_:_:_·,[_:,.::::,:_,:
·.

:·.:_,_.::_:_:_.:·:·:··:·_=.=:::_==:·

Requ1·f~a

~~h:=~s external cache, duplicate s~[{r~:~)::~~er. System
no
Wg
logic notifies the 21164 of all memory data :di.a.i!iip.~radi.h~AUlnit occur on the
system bus using the interface READ com@Kn.d:·:::::Tl!:::~if6~f'retums data if the
block is dirty.
.{tt·
·<~!1l!!!!l!li!t.,.
··:=:=\{\~jj1j!?
System logic notifies the 21164 of"alkw.emoij}q~ta write operations that
occur on the system bus using the inl®.tf.3-ce :Fli~S.l.l command. The 21164
provides dirty data, then invaliq~@.§. the'':b:\~~ in·:·:eache, and updates the lock

;.::=~tus.

A#ll~t>W!f!J/$4-~:itlJ¥

This system has an exteajjr. di=tij•:J?ut no duplicate tag store or lock register.
System logic and__ 21164J~piratiortii~Jll~ntical to operation for the flush-based 1

::::~ditt~~jc 4~jQ~:~'.\\\1{ij~~lfo '<?

This system hast~. exteftial. cache, a Bcache duplicate tag store, and lock
register. System l&i.~J!Otifi~$1the 21164 of all memory data read operations
that occur o.:~l:::t-h~...sy.~tijib:J:>Us. lo addresses that are valid in the Bcache
duplicate -~~pnSi;i~)Systiijl· Iogic uses the READ command and the 21164
returns d:3.ta if tbWbM}i:~k is. dirty.

Syst~P,tl~lt:Jt~~:: thJl!lfLUSH command to notify the 21164 of all memory data

writ~l!ltrans·ii~Q:n~dtUft occur on the system bus to addresses that are valid
.........·.·.. in ·tli~~jj~cache 'dtiptic.ate tag store. If the block is dirty, the 21164 provides the
.:::JtJtlltP.!ocltdij~. and invalidates the block in cache in any case.

:=flj~:::::~J?.. ..-::::ll~tem ·i~~~h1pdates its lock mechanism status.

tli:li'i•t•lc:::*}

.
Preliminary Edition-September 1994 4-25

4.5.5

F~::e:_~:c::a:t~:o~l~=:=:~~:::.at can occur
transactions with the system.

as aresult o~t\\,

./fit\t::::::·:·.. \:~th:::

"
t
%
f
;
\
l
,
'
i
j
~
l
1
:
_
~
.
f
.
i
:
.
:
i
·
:
·
:
~
.
:
'
:
f
·
·
·
:
j
·
·
·
:
l
·
·
·
·
:
·
~
·
:
~
.
:
:
~
\W(''ftt~,,

Figure 4-13 Flush-Based Protocol 21164 States

,,, ,,,

~=~~on) c~tz:>'lfr

RE.AD
(CFU Read Operation)

SEf DIRfY"

A(~J

•

• ~ordty th~ Ira=:e::::G<tkt;""'ilz)\{(j\'th

occur wthout a SET DIRTY command bei~Jssoo~hmterncii"jfl{lt

§t}lit

''SJ{--]29;;

Figure 4-14 shows the 21164!~ifichEt:stAW.s changes maintained by the 21164 as
a result of transactiQQS by 6.tbir nodes·:::Hdttlie system bus.
Figure 4-14

Fl~~ie::~{$yst::,Bus

JJ;iff::::~l\1;";;~::~~}

FLUSH Jtf

.,::Jf'·· .:·: :·.

~Wlt:~c!:;@\,;11

States

. ,.·

~'1;l~ -t 1 "

RE.AD
(OMA Read Operation)
Ml.0-012936

4-26 Preliminary Edition-September 1994

.....
::
::_
... .........
: :....
::::
: ..
: ::,·.,·.
.

4.5.6

~::~
~:::::;:!~:~n=~~~=:n::: system operation ar,~cribed
here. Systems should be designed to avoid these conflicts.
.
./;~it~~:~::::::::=:·:·..

4.5.6.1

1
'i:':e 21164 requests a READ MISS MOD transaction,

\~lll\

·.·.·.·.·.·.·

ilJ;c: :~~l\,,,

to be returned SHARED, DIRTY. However, if the system r~til#nfJ the data °I[l[:
SHARED, DIRTY, the 21164 follows with a WRITE B.L.QC;K c6Mm@d. This\ff
might cause a multiprocessor system to have live-~®.J(?p=fibl~pis, "1f¥bndition
that can cause long delays in writing from the 21~iJ to m~fiiitt~:/:\·

4.5.6.2

~e2

clean/privaid,~l:lJ.t::~ends

21164 attempts to write a
a SET
DIRTY command to the system. The syst~W?'~oli18~1~h:::.~eri'dihg a SET SHARED
or INVALIDATE command to the:. 21164ddtth.e sam~:::~&hie for the same block.
The bus is the coherence point ilitt)ie _sy~Ml;.~~:tP.erefor~:;:::if the bus has already
changed the state of the block to sha.:. settli#jj~~t.P.e dirty bit is incorrect. The
21164 will not resend the SET DIRTY"H~mwandtwhen the ownership of the
ADDRESS/CMD bus is retumedt%8te. writiIW.ill be restarted and will use the
new tag state to generate a ne.f~~=~y:·;t®:W.tr~qtiiit:

Another possibility is for tjtjl~[lil~wm ~":::~!Ht'· an INVALIDATE instruction at
the same time the 21164. iifatt~mP.t:i11g to do a WRITE BLOCK transaction to
the same block. Jp this::aiie the 2ti6.lt~borts the WRITE BLOCK transaction,
services the INVALIQATEf~!it'-t.!llction:;:::'then restarts the write transaction,

~h::::~::!~~t~,:i:~
or WRITE BLOCK transaction is
started by the 21i&l)w.. d
by the system, the 21164 resumes
tiU~u#nterrupted

the same ti:.™-l§~tj9n:·:iiijl~.~ the system request was to the same block as the
request tq~f~2fi6'4l$:ad stiffed. In this case, the 21164 request is restarted
internall:il[$y tQ.gj)[C'Pl}}~d it is UNPREDICTABLE what transaction the 21164
presents a~!k@==lhe ~y~tem.

4~~\~::~4\UWi~f"

Preliminary Edition-September 1994 4-27

406

Lo~~~~:~~:=:~s

Scac~

forced to miss in the Dcache. When the
read, the-BIU's lock IPR is loaded with the physical address and ~h~J9.~k fiijg:,.
set. The BIU sends a LOCK command to the system so that it qyfliiQmit~t)Ilt..
own lock register. The system lock register is used only if the;::}.ed blocfFiitIItL
displaced from the cache system.
<t:~tlt..
··==::n~~\

The lock flag is cleared if any of the following events OCCl!fk::::::.,.. ·.:,:=\tl:i:::~il::t:..

•

~~::A!;~:~:E~mD~~~~~resses the lt7';~¥Jk,

•

An STx_C is executed by the processor.

• ::;:ted

block is refilled from

..::::::~:tt~:~::::::..

tt:
.·.··:·:··...

·4ii::if

.Jf'

···:·:···:··

:,~mo~\t'.'§~~~ll}6l{_FLAG_H is

The system copy of the lock register-===nr r~_quiredhm: systems that have a
duplicate tag store to filter write traffic. <@h~. direc\im~pped Icache, Dcache,
and Bcache; along with the subsetting_:rulelVipf:@:flcl{=pfediction, and Istream
prefetching, can cause a lock to al}!.jyij~~~f.@Jl be:C~iw.~ of constant Scache
thrashing of the locked block. Ea4p/tim~t@tb.!.~ck:lf loaded into the Scache,
the value of the lock register i§dgi~ally ANQffl;l with the value of signal
system_lock_flag_h. If the l@.t~'d=l~l9.~.~ is displaced from the cache system,
the 21164 does not "see" bu~tltite op~fitj9ns to the locked block. In this case,
the system's copy ofi.e Iocit'iijti~ter cortAas the processor copy of the lock flag
when the block i~,Jilled .mW. th~::::~~h.~, using signal system_lock_flag_h.
Systems that do·''i{a\:~~h~~;::::di.1:11~.~~·::::ij~ stores, and send all probe traffic to the
21164, are not requiiMU:W:. implim~.;nt a lock register or lock flag. Such systems
should tie signal..§Y.~-~e:Di!l~_flig_h permanently true.
When the ST;.$C:::{~:;~Btetj~:iili~:::J.ssued, the Ibox stops issuing memory-type
instructions. i3'ie ~@..f~ 1'-d.ates the Dcache in the usual way, and places itself
in the wiit~ bliI~tiJit is nit merged with other pending write operations. The
write bd~f is -:=ffiiih.e.d..,.,:/J/

_.,.,::J.Yb.~m ·:ifil!llwrite ~:if~;I::rives at an STx_C instruction in cached memory, it

./~~lf~Jpt:alm~ th({$~aj;;he to check the block state. When the STx_C passes through
. ifii}?. the ·-$.i~che, aBffNVALIDATE command is sent to the Dcache. If the lock flag is

cle~filhe STx_d'':fails. If the block is SHARED, DIRTY, the write buffer writes
·.:,::\lf}t\.. tb..f~l~STx_C data into the Scache. Success is written to the register file and the
··=::=<:i:rn~lllQ~~ begins issuing memory instructions again. If the block is in the shared
··==:~~~-the BIU requests a WRITE BLOCK transaction. If the system CACKs
the=t\VB..JTE BLOCK transaction, the Scache is written and the Ibox starts as
previJ&sly stated.

A:f:f:'.'

4-28 Preliminary Edition-September 1994

When the write buffer arrives at an STx_C instruction in noncacheqfµ1emory,
it probes the Scache to check the block state. The Scache misses, tliijI~tate
of the lock flag is ignored, and the BIU requests a WRITE BLOCK Lt),QJ(.
transaction. If the system CACKs the WRITE BLOCK LOCK@~~§~~t1oib::.the
Ibox starts as stated previously. If cfail_h is asserted along$jitlf6i~j:jjb.en

4.7 21

~;:~;~~~::~he Transactions

~.:.·;.:~.·:;.;j·_-t\.:.:·.~=:=:.=~=~.:·=:· "<t~-1

=:====~~m111~~=====:·.

·.·.·.·.·.·.·.····.·.·.·.··=.:... ..

..:=..==.:.=·..: : =.·=·=·...:=·.. :'..=.==:·.

When initiating an !stream or Dstream data tran~4,ijfiori;ttJ.!lt~ 116"4Hirst tries
the Icache or Dcache, respectively. If that access ~iiunsyiteg~f:tiCthen the
Scache will be tried next. If that fails, then the 2ii64 t6~s tli~f1%ache.

The 21164 interface to the system and Bca~liitl~d:P th~i!!!!b.P.9.i~j/The Cbox
provides address and control signals for trahsaciiihl:::to ·mnr&om the Bcache
and the system interface logic. ~e CboJ.b!l~o transf~~t~ata across the 128-bit
bidirectional data bus.
·'\}}
··::t~\t\::::..
··::::=·
The 21164 controls all Bcache tr~s~~Ubns ·~aj:~~ll. often be able to read and
write to the Bcache with no ass~:§.tml.ce 1¥i'mttP.e ·~y~tem. When system logic
reads or writes to the Bcache, JttsWP.P.~i~s ot===i•~s data from the Bcache but
only under the direct control of~~he 2IiQI:.;:=:·:·. · : :·

471
" .

e::~:: ;!:~!,~Y hl}t:~;~,~:~~

or slower than, that of the syselk.
If the system is 1H\ro\yed ifi{@t§~ache tfansaction, each read or write. operation
starts on a sy'-~lJt edm.itJ.t is lhgtr~sponsibility of the system to control the rate
of Bcache trali=~i.Mt~m~tby~:P.~Jngllfo dack_h signal. Read and write operations
that are private l&tb~. 21l~tm:id Bcache may start on any CPU clock. There
is no relatio:q.:.P:~:t)Ve~Ht~i-~lk ··:ind private Bcache accesses.
Bcache timihi:''f~:'.!!lh~~~·-::~~8Htrol of the user through the BC_CONFIG and
BC_CONTBOL.:::~tHe~l processor registers (IPRs). Section 5.3.5 and
SectiQ!t 5:~~lA~JO:w tl~~~~)ayout of these registers. These registers are normally
con~~fed ··syj!:~:J::!:§4t!.Ritialization code .

.·:·: : : : : : : : : : ;.;. Bcagll.\r.ead ~~~r==~;rlte timing are programmable. Read speed is selected

Preliminary Edition-September 1994 4-29

4.7.2

data_h <127:0>
•.:::.;..

tag_ram_oe_h

·=:~ttt:-:·.

_J
_J

. :.::::::)~}.

··:::

: t~:.:~_·.~.~=: :~.:~.':·.:=:.:

•.: : _:·.·..:'.:.:'.:.:::·:·.

···=:::\i~il~~)··

Th::::e~~~!!;~!iC:;~:::'addresses, ea:: asserred for

four CPU cycles~(llb.~ Bc~Bh¢.Jogic:':U~J:3ys one CPU clock cycle before returning
the data associated?With ea.~hdndex. ·.:,::=··

The 21164 always...d~~:,~~I~n~ ·~~~j~::·before asserting the tag_ram_oe_h and
data_ram_oe.•;.b.{Hi~$.t<rli~'lfu'es are deasserted after the fourth index address

is deassemd'~ft::::l) '"'

<41~\tr•lt>

····:::·

4-30 Preliminary Edition-September 1994

.Jl\.

4.7.3 Wave Pipeline

The wave pipeline is implemented to improve performance for systeirli.[~lthat use
64-byte block size. It is not supported for systems with 32-byteJ;?~OCk si;.~~-The wave pipeline is controlled using BC_CONFIG<7:4> [BQzktl~Siti]tj~l~P?]

:~~~;~~~~~: ~~~~:::~'.::~·

laten~·lb~ Bea:::~•

is set to the
transaction. BC_CTL<18:17> [BC_WAVE<l:O>] is se.;kto4be rilliij:kr. of cycl~:~/
to subtract from [BC_RD_SPD] to get the Bcache i:.¢.~tifi&tib~f!te. ··::::\l~::·

For example, if BC_RD_SPD is set to 7 and BC_Wi.VEc:;l~b~t{ij~~j$~~j::to 2, it takes
7 cycles for valid data to arrive at the pins, but a H~wllad d~~ts every 5
cycles.
.iJtll~l~l~~~lllt~1tk:-.. \~j~[~~:::t1~t:ljf
The read repetition rate must be greate~. @.im 3. ··:1~:@.t;~xample it is not
permitted to set BC_RD.,..SPD to,,~h~d BQz\YAVE<l:d5.ftt> 2.

Figure 4-16

Arrows indicate when 21164
clocks Bcache data into the
·(~j~}·

I 4jt::l~'jj\J f:%lfli:i:tl\J I I I I I I I I I I I I I I
kKlmLh <25:~\~i\t~;"e;;llbl~~~~
12
13 )l-o---

CPU Clock Cyd@J..

x x

00Xo1Xo2Xo3)-

MLQ.-012430

Preliminary Edition-September 1994 4-31

4.7.4

e::~e:i~i~::::sa::::.e(~::::mi:::r~:=~ ~te

operatilte

Bcache by the 21164. The write speed is 4 because BC_CONFIG La.C_wR§th:.
SPD] is set to 4, defaulting to the minimum write speed of 4 CPy;J;y~)~~:~::::::::·:·:'.:f~}:L

Figure 4-17 Bcache Write Transaction

' f-'--\:%1\W®;\,

c~::' '~I I ','.I I I 1~ I I I I I 1C~if~!::1\@?
data_h <127:0>

Th~~~~ernen~'.thro~c~~~:::~:esses, e:::ng asserted for

four cycles. The -:~:!164 ~l.W.~ys (f=&l~Y§. one cycle then drives the data associated
with each index:==\~::::j::ll:t:::::.. ··=:tl:j~jj::tl~t::.. ··:::?t:::>
Signals tag_ram_we'.:lthmd daij!4:ram_we_h are asserted high for two cycles
because the BC....CQNFI~Bi~-~o:>::=::~ [BC_WE_CTL<8:0>] is set to 6. BC_
CONFIG<22:~:i~~~'HMqg::~et 'dilq~s the write-enable lines to be asserted during
the second ~?fthird:fP~!hcycies. BC_CONFIG<20,23> being clear causes the
write enable lliu~iv$Fnot ::fii asserted during the first and fourth CPU cycles.

The Be~~~ ~-l~m:J~j~~ or write speed is 15 cycles. The minimum read or
write spijid is 4 cyM@'''ixcept that in 32-byte mode the minimum read speed is
. :::::tHil~liM:m.es>''SAttb.e index and data can be asserted from 4 to 15 cycles. The write
,::J}?::--·endq)le. signdnUb.w.;i be asserted from o to 9 cycles. If BC_CONFIG [BC_WE_
. /If?'" CTIJlJs set to d'Pthe write enable signals will not be asserted. If the 9-bit field
=t:l~t~~~:\:-:.. is_.::~lt:::to 1FF16, then the write-enable signals will be asserted for 9 CPU cycles.

<1&;11t\tC;,tt11>

4-32 Preliminary Edition-September 1994

4.7.5

s::~ 1::-~~ev~~:~: consider when designing and imple~\~g a
/[~iltt::::::·:·....\~~~~it:

Bcache.

.t.I}" ., "%il@t~\\\Tu.

Table 4--8 Bcache Options
Parameter

.
Selection

Preliminary Edition-September 1994 4-33

4
.S

=:~:!:!:~ri:~~!:::~=~=~~: to move dattransactj9n.:.wh~ri~l:~~h.
a and out '&be
in

21164 and its cache system. The 21164 starts an external

: ~ ::~:::;:::::~~ at ashared block.
•

A WRITE command is directed at a clean block in

't\(~~:lt%~.,~,\~

:S~f~i! ~l!: :~t:\: :.

~~~

&~e

:s~§~:~~i;~!~::!!~~~~!::::eili~g2::4:s
•

an external READ MISS tran$IEtion?tff$.t. telM~lhe system logic to access
and return data.
.t:f:~ ~ i~l !l !l: ~i:t: :. .··::t{~\jj\\\j}:'·
System logic acknowledg¢j{accepQ~.~ of the command from the 21164 by
asserting cack~~t> . <l:::~!!!!~t:\:...
··:·::tit:}:·
If the transag;t.~on isd:kr.~ad ··=o:pj,r~tion, requiring a FILL transaction, the
transaction i:~~:$.tQ)ten·::lP.~ndedfWl\Ue system logic obtains the FILL data.
At a later time··::~tt®:\\jy§t~~:::1..~rt;· fill_h.

•

The 21164 wiU/3.:~i-~;fi~ih~bt~~::::~d tag control bits, and will control the

•
•

• ;~~ii2~J:~ett;:a::g ~Jes in

whlCh dack_h

Interfa~~j~pmmands::::ffom the 21164 to the system are driven on the
. ::f~l@Rd.hc£3~::J:;ignals. Table 4-9 lists and describes the set of interface

4-34 Preliminary Edition-September 1994

Table 4-9 21164-lnitiated Interface Commands
cmd_h
Command

<3:0>

Description

NOP

0000

The NOP command is driven b~i!~h~::::JwfiifHtt1i[tht.
cmd_h bus when it has no t~J.[~(queued. ··.·-:,::::::::\]@\.

LOCK

0001

0
~~s~!Ji
~e":~:k~:::~:a:S~:'~'
of the system lock
is
each fill
rem~t~Wfi~--

usea#~~

to update the 21164'r;(:~opy otth~Jock fl~. Refer to
Section 4.6 for moreanform.itiond)\,/:\

FETCH

0010

FETCH_M

0011

MEMORY
BARRIER

0100

SET DIRTY

0101

~~1!~!:".'tl:~E~!trtio~~e:!~.t

The 21164 ~~~~=;=~~i!lif.Ercif!MN~struction to the
system wh~ifthe FE.Tt}Jt}.d: instruction is executed.
rffi~, 2116l~::~j~le.s the M~MORY BARRIER command
when:::an Mlfirthr.uction is executed. This command
syncl1ft$.~~ re;iH~4 write accesses with other
pr.Q_(!_~ssor§~:ijt;t;he sy'Stem. The 21164 stops issuing
. Aiifti~zy refei~:P~. instructions and waits for the

;#f1:~-~==:w~:t~:1:or;,7~~::~~s

/t?'':-:-:-:,\:~_ SET DffiTY command when it wants to write

~t=~lmHh private block in its Scache and it wants
the diljy- bit set in the duplicate tag store. The
·-::::::~llt':-. 21164 doos not proceed with the write until a CACK
-:dk::-:-.
···::::~\l~~ponse is received from the system. When the
·-:-::::~@\!!lt::..
·-::Q$CK is received, the 21164 attempts to set the

.,:::::,:{f

<tlH\..

·· ··

·=\/::\::,..

··c;\\l{\\\\\~;:~\~}~~~~f~i~~1rii~~~1TJj~~~e
1

WRIT&ill1~;1 :i ::~~!~!=::::.:::~~:~:=~:~
<t\;-\1~!;::ki:l@f\ff!

~~±~~~i~!t~~~~f~m
and address from the bus and begins the write of
the Scache. Signal cack_h can be asserted before
all the data is removed.
(continued on next page)

Preliminary Edition-September 1994 4-35

Table 4-9 (Cont.) 21164-lnitiated Interface Commands
cmd_h
Command

<3:0>

Description

WRITE BLOCK
LOCK

0111

Request t.o write a block with lock. /bif;:::gma•nat:t,
is identical t.o a WRITE BLOCK ~Rfil~and except(t@{h,
that the cfail_h signal may be a~~~d by the
. \@\:.

~~:;~~C:~t~~go!~;~!~~.1.~§.r~~~b.~=~~d ·(lllli!J

READMISSO

1000

READMISSl

1001

space.
.illlll:rw=::::::~(lllllllltt:::::.. ··::::\l{>
Request for data. This cifumand.Jrttli..._~=· that the
21164 has probed its cacij~ a®fthat%Jifiddressed

:::::t~= ::•W:Jlul:res that the

21164 has pro~lllts camtil:Jllldlhat the addressed

::ft~=
s~fy plans
;:~~?:toThis
command
indicates
write to the

READ MISS
MODO

READ MISS
MODI

BCACHE
VICTIM

=ih~t.. the··:2~\§4.

returned cach.iJ?Jock>:?f:mmally, the dirty bit should
be s~tw.4.~n the*i~~:. statUs is returned to the 21164.
~qji~Plifl~AAta;:·:::ffiij&ry intent. This command
1011
~.n:m~tes tn~m~lw. 21164 plans to write t.o the
.J@it-Atm~d cache:=lij~k. Normally, the dirty bit should
~@fbe ·se[wb.en the tag status is returned to the 21164.
1100
4llIL.Bcach;::~t!itim should be removed. If there is a
·::tlJ=···::tt)jjj~¢.im buff~f in the system, this command is used
· ·.
·tl!\t::..
·.:ti:]}:@:-§.S the address of the victim to the system. The
{(\:·.:·.
"::t@\\,.,.. REAQJ\USS command that produced the victim

'%l~]!\j\ib, ''%l!l;!'~~~ :;;~~ ::;h~
··:::::)\\...

MISS command to indicate that a BCACHE VICTIM

.J:J!jflllftjj'.~!l[l[~l::l· .·. ··:::::(jjjj:::::::::i~:·~~:::~~}st~ai:~~a:t!~at the Bcache is starting

' •t%1{,i~:,t,;tl

d~'~\{\ft{i)

4-36 Preliminary Edition-September 1994

~~~~~~~~~g~d

~~:m~~~·· the Bcache i:oo:::::::xt:~)

Table 4-9 {Cont.) 21164-lnitiated Interface Commands
cmd_h
<3:0>

Command

Description

1101

READ MISS
MODSTCO

1110

READ MISS
MODSTCl

Hll

<I}:·

i\ftiq\\j-~~::~:ft;,

(\:;!::j,

<r~;1:r~-1\i1,
·.:.:

:::~ t~~ ~~~~::.

Preliminary Edition-September 1994 4-31

4.8.1

R:~~
~;==~~ ~':~~a~he misses causing a read operation to the ~e,
which also misses. After the Scache miss there is no Bcache probe::;::::::-the 211'4:

sends a READ MISS command to the system. The system ack1wwi&it¢~=:=:====·=·:J~~~1L

: : ::

:~ READ MISS by imm~arely asserung cack_h'1\~:~,snwt,

sys_cllLout

fill_h
fill_id_h - - - - - -

:1 l

MLO-o12401

4-38 Preliminary Edition-September 1994

4.8.2

R!~~l~~s;:s:sdaF!~ MISS command if it encounters a cache 1 as

described in Section 4.8.2.1. The system acknowledges receipt pf.the cdWm.and.
Later the system asserts fill_h and asserts data<127:0> on ,:t.JfiPP:r9P#.:f.:.:~~les
and sequence as described in Section 4.8.2.2.
:fi[f' . . .:,:,'=\:~tiJfFl!\.

4.8.2.1

;~~s~~~:;i:;:oa::!::~~:n°:ro~:r ~i.;~~~ti~~~:ltt

of 4 to 15. The tag is accessed at the same time. A'f the ,4'tfdtP.f::tb..=e first read,
the 21164 latches the data and tag information adQ.[ij:begfffs thi[i:f.~:Kd operation
of the next 16 bytes of data. The tag is check.~d.Jor. . a lilt~ If.there is a miss, a
READ MISS or READ MISS MOD commru1dHiiijP.g:. with[::tM~Niddress, is queued
to the cmd_h<3:0> bus. It appears on th~f~hterf&ti.mAt. tli'e".next sysclk edge.
Figure 4-19 shows the timing o(A:J3cach~::i~.ad andlHij)·esulting READ MISS
MOD request.
·"===tr ()\:. . "====::l{:il\ilt:<...
..
Figure 4-19 shows the READ MISS MQQ,}!onimijb.d being acknowledged on
cack_h as soon as it is sent. TQi§@!!J~w~f:i\l:~k~ 1164 to make additional READ
MISS requests. It is also possilltff61fotb,~ systi;\th to defer assertion of cack_h
until the fill data is returned. . Jfhis al18W'-:=:tP.e system to use cmd_h<O> for the

~~l:.~t_~-id_Ji. The ~~i~i~;{;~:~;Should arrive no later than the last
<I}=·

"====<tt\.:..

Note _ _ _ _ _ _ _ _ _ __

~~Wtmari~==::!!Ubint4_valid_h<3:0>

A READ{M.iss
of zero is a request
for Istream:·===a~-==·:whil~::[[JtJ:~_valid_h<3:0> of non-zero is a request for

Dstream data. "=====t:l i l =.:[.\[.[:,.:.,:=:·,:= = ·=.·,·.=·.=:=:·:·.· =====t{?=·
..::::::::~:~~~~~~ttt:::::...

Preliminary Edition-September 1994 4-39

Figure 4-19 READ MISS Timing Diagram

sys_cllLout1 _h

addr_bus~req_h -i----t--r'--t---r---+---i---+----i~--i---t-----·~A~t~l~f~~·+1
::::::1~:===m====1=RMM:::o:1::::f ' ,,fif~~q~~::1tt\t}
cmd_h<3:0>

~::~:: ~:~~~:1'"'"•_-9900_-_-_. .;~~~-x;. 1,..~:~~::~-=-~~-5C~:..h---:~--:~::~--=~:~--. . . - il~:~ ~iL; ; ..h-.;,. !-= =;:-i~i! ,; ; ~l~li~:;:;:;lj.:; ;' : :; ;:;\;:;:;:;!;:;:,.i~'
....

caclLh

i ~ rh
!,_:

addr_res_h<2:0> _..,.._ __,.
:

=
=
•. r-n=:

;j~ ~irnt~ ili l~l~t:=:=:. I=~li~i:j! !jilt~ ~tli lJr

,,·','=_:_:_·.:,':,:;:,;
••

l .
. . . . .:.=. -· : : \i~ l.~.~-~-·=.i~:..:·_,~.':_.=·_.:'._.·.='··.'·.:·._.·':.·: :. -:·:·:·=i=:····.
..
_---;~-+-i---+---f-..;;''~(:~L___!_·/;.; ;lf; ; ; ~ljlj~j jfi,.,.,.~...;...-__.,.;;;;;;;..__j,
_

.r,=:'.~

··::::r:··

:·::~::::::

_,.j..

· · : :\~.1.~ -~.t_;_~-~.~-=.:.:_:.·.·.....

fill_h -:----+----+----+----+---4J

fill_id_h ~--r;.....--.+i'--;..._-+---.+-11
idle_bc_h _ _

__.,___...,I1

index_h<25:4> ";.;;+;=-.l'~r~::.::.=...l!:j'.....,::".f..:.\,~J~:..=...~~..j;...:==4l.i;j;j
___ :,:~t""'~t~:J1....·=~-=-:.:l"'"-=~'-==l\.!=2"
data_h<127:0> -':"--'"-+-__,.._·.·._,,,.~~-+-~'::::;;;;;;:::::::~:::::~··~+---~..::.::.~...::.:.,.r...-=:.f"-==-1\.-=:.+
.::::::::~
!·:::::::::::::::::.. !
· ~,.:=:= t.~ -~ .~ -~ -=:-.·:.: .~.

~ . · : : J~.~-~,~ ,.;_,·=.: : :_:~·=,·_,:_,',..':·_,·:·,··'.'::..

. ··:.:·.·:.:·=·:.

dac1Lh----;,..--"'::~::r_mm~>~,:=,..~:.----1,,.;;;.;,;,;,;~;..._-··.~:::::,~:'_
::: ::::::::::::... .

. :· ,

_._.

=~=~ T l&ttW~~;t1~1-f~1~~-:-~-+[-:l_~="-+---------------;..-~
i ..:::::::::::-i .,::::::::::

Ml..0-012402

4-40 Preliminary Edition-September 1994

4822
" ' "

F~~~als fill..h, fill_id_h, and fill_enor_h are used to control the r~~ of

fill data to the 21164 and the Bcache, if it is present. Signal idle_bcJib~mst
be used to stop CPU requests in the Bcache in such a way tliaitt.h~J~.cl~b.~
will be idle when the fill data arrives (but not the FILL coiUljla.Il"d:)~t~S.~t:.
fill_h. should be asserted at least two sysclk periods befor.~tt.fi~ fill data affiv!.~
Signal fill_id_h should be asserted at the same time to ind:i~W.. whether th~!!j~j!!i:
FILL is for a READ MISSO or READ MISSl operatio.P:~::/fhe 21164. uses thislf
information to select the correct fill address. Figur~dP.19.i!i~llQWS.lh~:~:timing of a
FILL command.
it? . fft:~l:t::·:·. .·:·:·. ·.·
If signals fill_h and fill_id_h are asserted at the ~~ingjjf~ge··:·1r:~~;~clk n, then

the 21164 asserts the Bcache index and begip~fa~::. Bcacti~:::=':~T:!if at the rising
edge of sysclk n+1. The system should drii~FtR~tg~t.~ ofilWtfie data bus and
assert dack_h before the end of the sysc;l~ii~~ycle. Xtlt'b.~. end of the write time,
the 21164 waits for the next syse.J.k:::edge~=:ttlh!a.ck_h h:i~Fnot been asserted, the
Bcache write operation starts agaIIl a.t.::.~he ·.Mim~Jndex. If dack..:.h is asserted,
the index advances to the next part of%h~t:filfMiftt~e write begins again. The
system must provide the data 8.9:9dl~ck2Q!Jugnaf~t the correct sysclk edges to
complete the fill correctly. ForJ~itiffiil~i. if tfii}Dcache requires 17 ns to write,
and the sysclk is 12 ns, then ..~W.o sysd:l!i~~Jes ··are required for each write.
The 21164 calculates and,~i~Ri::~t@:g_v~ta~h and writes the Bcache tag store
with each INT16. of dat~K]fhe sy~t=imds required to drive signals tag_shared_
h, tag_dirty_hAlilld tagfft3ta_par:BNvith the correct value for the entire
FILL transaction::·· ./\::·:·. ··::t~Fth:':·.
At the end ofifbi~dfI.~E!j:lt~. ~~~fl~BH', the 21164 will not assert data_ram_oe_h
or begin to drivEt=tij~H;lata:'l$i$.::Jmtil the fifth CPU cycle after the sysclk that
loads the last.P.t\CKMQ}~ysteth"s require more time to tum off their drivers,
they must. :~$~Fi$.e1.l>c:Han. combination with data_bus__req_h to stop 21164
requests, ,~@d nqt!:!~~~Q:@. an§:.-system requests.

4.8.3 READtMtlkAf-i~i~

Jibtim

Th.~~~:!lx=~64 ··;~tl~fijJi~\iit~o models for removing displaced dirty blocks from the

.·:-:::::::::::::::::::::·:·.Bcd8ij~~::::. The first. assumes that the system does not contain a victim buffer. In
. :A!Iift====:ttrnhjs ca=§@~}tb.e victim must be read from the Bcache before the new block can
-::d!~f:r·
·iji~\request~4.k·In the second case, if the system has a victim buffer, the 21164

.J:\ff'.:

.)~quests the·.·new block from memory while it starts to read the victim from the
·-:·::q:::\i!f::t::... .::=::f}Bcache. The VICTIM command and address follows the miss request.

tt'tlii:t'llii'
Preliminary Edition-September 1994 4-41

In either case, the 21164 treats a miss/victim as a single transaction. !fit.he
assertion of addr_bus_req_h or idle_bc_h causes the BIU sequencer tati~.set,
both the READ MISS and BCACHE VICTIM transactions are restarted ff.Om
the beginning. For example, if the 21164 is operating in victim fir~t.tmg:d.e;·=il.9
it sends a BCACHE VICTIM command to the system, then the :~f:sfufiP~lW~]~:h:.
an INVALIDATE request to·the 21164. The 21164 processes ~h:@f{NvALIDAT,Yfl\:.
request and then restarts the READ operation and resends tlii~~~~HCACHE
\l}

:~;o: :::::::::~:~::::b::::~s= ::s:~Ji\i~;z;li~ssing.¢1¥

~ l! ! ! !;: : .:Jj~ l ~ ~r·=:=: \~!l! !l ~ :~ tj~}·
4.8.3.1 READ MISS with Victim (Victim Buffer)
When the miss is detected, if the system has a -y!gtjpi h~flif.i. th~:~~il164 waits
for the next sysclk, then asserts a READ MISS.f~fitb..\wid/:\a.t\\\\t~'~d miss
address, the victim_pending_h signal, and . i4.~exes . lh~fJ~.~ache to begin the
read operation of the victim. When th.~ syst~mtflsserts cli&t._h, the 21164
sends out the BCACHE VICTIM coilifiiand a.Illfithe victim . address. Each
assertion of dack_h causes the Bcache irll~. to "ri:dt~~e to the next part of the
block. Figure 4-20 shows the timing .9.f. a ItE!&I.t.MIS'S/~ommand with a victim.

+>.. <!ttL
··==:===:\tli::,,,.,..

"'itttr

·=·= ,=t L: : l.~:.:=~·=.'.:~.:~.:=_.:~.:=.=.=..·.·=··

'<'\%11~,-;;

c:;(:~::~,,,
4;i-~1~1l l\;t

4-42 Preliminary Edition-September 1994

Figure 4-20 READ MISS with Victim (Victim Buffer) Timing Diag~m

:~:~:: Ii
cmd_h<3:Coe

vk:lm__pendng_h

addr_h<39:4>

8*8

;'(!~l[ ''ft: ;~lli~ \lh

+
b ~"'~m 'fi%,J
I ! i ! ~,,,'''[tt,

I
1

FFFOI

,~111

; _...;;l~l""':::·~~---:..:;;.;i;;...;.;._+---~~--

addr_res_::::::~:~~~~i:;~~~:l~~~~:t:/:~::::. :!:_-::_{~~t~~~~~\~,~-~-_..~-~--+----:.---+

~~~~:

::;,;,;::::;,;,;:1j:,;,;,;:,i,.,~:_: _:i:_l: +-'t: :i~t: ~ ~;:tl:;: : :J: :~i ~r: \:~>:l: :~l_r-n_. . ;I~

: -:
..
: _-::_:
..
: _-::_:
...,.......
:

_ _;__ _. . _ __. .

Ml.0-012403

Preliminary Edition-September 1994 4-43

4.8.3.2 READ MISS with Victim (Without Victim Buffer)
dl::.
If the system does not contain a victim buffer, the 21164 stops reading
Bcache as soon as the miss is detected. This occurs while the second INTlG\

ltih:.

1
:a:c:~;~~: ::~:~::s::::~:~ sysclk wl!1:!!1lt;;,
2

victim address. A Bcache read operation of the victim is also4¢.i!ted at the . \fflt.
sysclk edge.
· ==:==([[[[:[[\\. .
·=':Jl[}
When dack_h is received for the first INT16 of the vi~Q~[~l[[lth\t:2.1~=~¥~[~~ns · :=:====·
reading the next INT16 of the victim. cack_h can be =~~ht a.P.Y=~tbn~. . lwfore the

;~~~=s~~~:;~~;;:i;;!:iJ:ek_h

Notice the wrap sequence ofth*$tran~,\Q;;~~DO, and Dl.
data

.'"' zz11ritt•11\1w

4-44 Preliminary Edition-September 1994

Figure 4-21 READ MISS with Victim (without Victim Buffer) Timi"g)Jiagram

\"'\&..

:::::::::::::.

}

1'~~-+-!~---1--~-+-~--t-~~~
....
1

;;,._~...+-.;.;,;,:,:,;,:.:.1;~~-+-~~~~..._~_,,i~~

<- •

. ·:f~t~f~(~~~~jjjjj~d::!:~~~?.9> -+-!_ _,__ _,,__+--+-____.;~__,;-----+-----+---+---+

~~-~-~-~-~-~-~-~-~-~-~____.;~~

'AtJ~tl(~: ;#'· :::~:-+--+--+--+---+--+---t----t----t----t----t----+---+-

MLC)..012404

Preliminary Edition-September 1994 4-45

4"3"4W~~!:"~;~~;~o:=~~ i~~~~~ ~~~l~te writes to shared da~~
::::;;::~~:h~~~;:::and follows the same proto~t1h! ~lit\);\jlh
remove Scache victims in systems without a Bcache, and to compl~t~ wriiQlt.
1

qualifier allows the system to be more "conservative" on intetl-~.4 write
operations to noncached memory space.
···::t{\~lh:::..

regiq_nj~\:th\ltl\\lqµr~~tdlta

<~IF

The WRITE BLOCK command to cached memory
from .
the Scache sends data to the system and also causes th~ dat.i:liP~:::W:ritten in
the Bcache.
.. \1} :~ :[!il!l!f. Jllllllt::=::::::··
The 21164 asserts the WRITE BLOCK commaq4.Wi.l9.n.g WiQtJJl.iNiddress
and the first 16 bytes of data, at the start of ~~\~iysc11El:lfJhE{~y:stem removes
ownership of the cmd_h<3:0> bus, tq.~ 2116:4.tl."tains tli:MWBITE command and
waits for bus ownership to be returrieit If thM&l~wk in quel~tion is invalidated,
the 21164 restarts the write operation. 11bi:~. resfrlt$.dp the READ MISS MOD
request instead.
·.:-:=tm::::::tt::·:·. ··:=\:tt>·
When the system takes the first p~g#Mt:::~~ d~tilbi~ asserts dack_h. This
causes the 21164 to drive the nextfi6 byfii}pf. dat~f.on the same sysclk edge.
If the system asserts cack_hlih~ll\~)!(>4 ou;~Ht~ the next command in the

next sysclk. Receipt of sign~}I~ack_)i\md.icates to the 21164 that the write
operation will be tal@.p., ancF~t it is sM~\\fto update the Scache with the new
version of the bl~:~:..···:·::::: <\ltt:::. ·. ····::::\~\\\\\\\::\\:)\::.:·.
·
During each cycle'Nt.b.~. int4Uy!J.id_li~3:0> signals indicate which INT4 parts
of the write operatfoH:l~r:~ re~ltif:P.:~ing written by the processor. For write
operations to cached m~~pey, a1Fit the data is valid. For write operations to
noncached memqf.Yf~§!:lY. tfM~tJNT4 with the int4_valid_h<n> signal asserted
are valid. Setil!lrhe ~,rJ1-ff~~i~ fof int4_valid_h<n> in Table 3-1.
Figure 4-~2 sl\b.w~fithe titi~ng of a WRITE BLOCK command.

<!lt~ltt~::ltn#tif!lf

4-46 Preliminary Edition-September 1994

Figure 4-22 WRITE BLOCK Timing Diagram

sys_clk_out1 _h
addr_bus_reg_h

~-w-R-,t-~-e-e-1.;-+~-c-K---....---+--1----+---+---4~-+:t;;;:;::~~~:;;:;:;!J~l~W~::~::-::.,.-_..;:.__ _._

cmd_h<3:0>-:---'::---~'---!------t-----!-----+----'i"'..__,;.__,\i'----i;.,.,;··~··:':~:::~~:~·.~~o:.__~··~~\~~8~:t:~:::..~i---i~

victim_pending_h

-T-~t----~---t-----t----!-----+---+----~-.:.;:::i:i:i:{~:~\1~_:f_f_''''!~(:~l!l[..,.![~~~;;;;;1.~~t~~J~..·.~·~·: '.:·~q+~1~[-)_·--i~
~

addr_h<39:4>
cack_h

~-----::---+-i

.;;.0.;.;:190:.:..;.:_ _

l ln,. .______
:

.,..l_

·:·:·:·: ·:

~__,,t"""_-l-_--+.....:i:i~....-~~--+--~

_ _ . _ _. . . ,

addr_res_h<2:0> ±d--!!"'"---~-----t:j,':':':=::::-:::. -f-~~~--+--j;:.;i;j;j;i~-f--~---J~-.i.fill_h
fill_id_h

1·-----::------:----+-~!*":::~:-·~+-~~~--+--+-..;;,;;;_-+----+------l~-~

':.·

! !

~-t---+-~~~~-+---.;;;;;~---+--.:i---~___;;..-~i---~

--j:-:

idle_bc_h -=--'

··:r:··
~

l'. .-~---!'---"t---+---+--i!---+.----;;..----4--+---4--.....;_
ML0-012405

Preliminary Edition-September 1994 4-47

4
.S.S

s:,:~~ ~~~sl~~:ming of a SET DIRTY and a LOCK operation.\,,

The 21164 uses the SET DIRTY transaction to inform a duplicate/m•A~.Y>;J~ll!j~~~1L
that a cached block is changing from the SHARED, DIRTY sta~@ttcttH~Hi:ttJH~~~\,.
SHARED, DIRTY state. When cack_h is received from the SY:ltmh, the 2if6¥%~]~b.
sets the dirty bit. If a SET SHARED or INVALIDATE commhlii~l~i~. received ·\~[~l1:
for the same block, the 21164 responds with a WRITE B~QC.K oifJliAD MISS ·<Hf

4.8.5.1 ;:~::::::ET DIRTY and LOCK

t~)~it\~~:tj;t

The 21164 uses the LOCK command to pass the addres=s qf1a Ll)fl.L to the
system. A system lock register is required in 8:ij_MfJ.Y~-~m \f-!~t.Ji~rs write
traffic with a duplicate tag store. If the locke4.tB1oc1H1lHJispliimtt from the
21164 caches, the 21164 uses the val~e of t~Jtlstem itia~tt~gister to determine
if the LDx_USTx_C sequence shoul&~p~ss or==:f@iL..
··:·==tf
The system may use BC_CONTROL«;>;{fmLC~HlGR~2], to modify operation

~or :~e;~:~~=~~ CEI_CMD_Ga)t:~,£~::~ is allowed to issue

SET DIRTY and LOCK co~.m@ds to"lfil\\~fystem interface. The system
logic acknowledges receipt.d~tH~'ij~~ commands.

•

If BC_CONTROL [EI_G.~GR~~j[::l~d~Jear, it is UNPREDICTABLE if the

SET DIRTY andmJX)CK··=aibnands wlifbe driven to the interface command
pins. Howev~r~ th·~ ~Y~t.~m"'=~R~klP never assert cack_h for the command
when BC COffmROLTEJh.CMtF:GRP21 is clear.

''''1;1{\ifl\~~~)f~ ,,

c~;;~~:~''
\~{1~,t{;f;
4-48 Preliminary Edition-September 1994

Preliminary Edition-September 1994 4-49

40806

M~~~~6~::!e:n~~!~r amemory barrier (MB) instruction when exe~g
the instruction stream. The action taken by the 21164 depends UP9P.. the

sti:w

:fB~;~;~~~~~~=~~l~ =~!':y!~1!\=r1d~:!~ltt

logic must empty its buffers and complete all pending...tr.;µisaett~~ before +~if

• ;~;~~:::;~c:~~~:::_~:a;::::~~t is Qfl:l~!'if the

MB command will be driven to the interface comiriijhd .:f..lhs. ff.pwever, the
system should never assert cack_h for the c9m;mand •H~n RC'....CONTROL

Whe~E~~: ~:i;;~::::~RIER Commanal%%l"'\'11:~:Y&WV
0

U6.1

If the system interface buffers invalidttte.J>et#iibhthe du~if~ate tag store and
the 21164, then the system interface mu~tht.pabM'''tq~J\ilB command and drain
all invalidates before asserting cack..,.,~. in t~p9.pse HHfui MB command.

48 7
" "
4.8.8

F!:e~~164 passes a

F:;::·

FETCH

co-t!~t~~!\~: when it executes a

FETCH

{\)'~~-""~tlf\\1\~p . .

The 21164 pass~$.}~ FETQfl_M':''(t~t~!t.with modify intent) command to the

system when it eli\\\~~~-~~Anstruction.

,,;\;(:::~,,
<'!ti,~1 *t1 r,
4-50 Preliminary Edition-September 1994

4"9 Sy:~::-~o~=:::sdto~~~~::~!:"d:ven on the cmdJi<3~ si~Ytt\nes.
;:::~~:::::~:::a:: :~;~ss:::::dd~:S:::o:~~,:~:;:'.t+l\~h
III
The algorithm used by the 21164 for accepting system comm~q~.:. to b:g~[\,_

group of commands used by write invalidate protocol systeii¥~:i~t listed and .
described in Section 4.9.2. The group of commands u§:~dJ~y fl.tlshtbQ.sed protdtMl
systems is listed and described in Section 4.9.3.
:d~~:f>'::;:::::~:{~l\t:,:...
..,,::\{~>

491
""

Se~:=~s:~:~y ~~ c:xt:~ 2:~cess c9mJ~sl:;lt~· system to
8 5

the 21164 are listed in Section 4.12.1.

:::~~:~!!:~~j@::t::::flll:t[)t:::. ::q:::jjftfJt·

The algorithm used by the systeqi to segg}i.ommaridij:jt:q,:.the 21164 without
overflowing the two Cbox BIU cdiQmand . Bfi{w.s is sho:wh in Figure 4-24.

· <tt\\t;~::~zz, ·

4i1ltk"

+t'q1iq*it.·.~-~=.: ~:~.:~.:~_.'=

9\~&tf~t;~~f·

:=_.'...
: ::·_..
:·_.·'::·:.:·_::.

··::;::::··

~:(:~:)

t li,~-*~1>
···:··

Preliminary Edition-September 1994 4-51

Figure 4-24 Algorithm for System Sending Commands to the 21164

Start

ML0-012407

4-52 Preliminary Edition-September 1994

4.9.2

Description

Command

NOP

The NOP command I~Hmi:ih by '.ti~f:6~ner of the
cmd_h bus wq~;pj~ has 4#!l~as~J!ueued.
0010
Remove the,J~~]li~fli\W.wn =ltii@J§tem issues the
INVALID4'fJ. comm~ibt:Ile 21164 probes its
f?.~~he. IfUi~:-_block is ftjij.ijd, the 21164 responds
With ACK/S&ijhe and invruidates the block. If the
block:~~b;~pt fotli\tt:~d the system does not contain
a Bcacnltmth~ 2lt6*-jjjtesponds with a NOACK
JHli'==:=:~sUl~[!~m~tai~s a Bcache, the block is
_,{j~:Ssrlfi\i~l::.t<> be=lijHhe Bcache. The 21164 responds
.lfWith A~che, and the block is changed to the
..Jftlllm:vaiid statibvithout probing.
0011 .·:·. i~~jj~f::·······.··::::Bi®\=.,goes ~ the shared state. The SET SHARED
{@t@L
coriffitAA~ is used by the system to change the state
·(j:j}=··
··=:ttl\,.,.. of a bl&k in the cache syst.em to shared. The shared
)::,..
..,,,,tt\J~jt in the Scache is set if the block is present.
0000

INVALIDATE

SET SHARED

wi:;Ql~t;,, 't'i:te~c.fi::2~!•.::.::,~ :!:~~~~~~.:ct,

·wzttr%t\\{~~;:~1\1·;:~~~~!fE:~;~:t ::~:mTY

4b..

,~,::~,, !~~{{~if~t~~~~!~

'%t;li$4!@,

with NOACK.

(continued on next page)

Preliminary Edition-September 1994 4-53

Table 4-10 (Cont.) System-Initiated Interface Commands (Write lnvancflte
Protocol)
·==tlll\\.

:.=.~-~= .~-=·.:.=.-.·.=.=.=.=.=.·.=.·.·.·.·.·. . ··:t~~It._
,:~it·· ····====:=:?H{\llh:;;'.~~~~~~~~t\

cmd h

..... ...

Command

<3:cb

Descl'.iption

READDffiTY

0101

~~~1~~~~11§~;!~''
21164 responds with AClflS.Ca~l~f ari"E[~i.ijwes the
data on the data_h bus. =tt t~~(plock,:!~ ·not found in
the Scache, and tl;W:::~Y:~-~m C~J?:-~Jf' Bcache, the
block is assumed:~~f!mNfu::,.the "fkmtilf The 21164
responds with _.t\gk!Bcacl@Mp.dexes the Bcache to
read ~e bloc~*N~b.~ change's::~. block status to the

shar~)li~!. sfu~~l\\i::::,....

READDffiTY
/INVALIDATE

· ==:==·

Read a bl~t!nvalidiW:~. This command is identical
to the REAffQ1B.TY colifnand except that if the
~:j-4\"i~!~-} c8ches, it will be invalidat.ed

0111

lnv•lml~~RJ'.~to;:~:::~\S~mmands

4.9.2.1 211 &4 Responses to Write
The 21164 response~,. on a4.4.f£res_h~t$:~.Jo write invalidate protocol

commands are listedUn TablMlb:ll.
Table

· ==\}'.

4-11 211.St~~-;::~_res_h<1 :Cl>

to Write Invalidate Protocol

command~~kmt:,=·=·· ··=·==:q\:l~\l:=·
_.,:{~::ttJMY.~LJb4JK_and SET SHARED Commands

No Bcache
No Bcache
~/~t}

:\~ l! ! !:r· .·==~~~li~lrMi~'~

%1\•t::;Hit

··.··=·=·scache_Hit/Miss

4-54 Preliminary Edition-September 1994

NOACK
ACK/Scache
ACK/Bcache

READ DIRTY and READ DIRTY/INVALIDATE Commands

{~[~[~1\

No Bcache

Scache_Miss

NOACK

No Bcache

Scache_Hit,Not Dirty

NOA.OK:::::·:·.·.

No Bcache

Scache_Hit,Dirty

Bcache

Scache_Hit,Dirty

Bcache

Scache_Miss

systel·wii6~::n~licate

The purpose of addr_res_h<2> is to allow a
tag
store to determine if a block is present in tll~:::i~J1che 4!iJ.oc\jt.kgister. The

~::::::::::::::~:::::~\C1b::::d_h
and READ DIRTY/INVALIDATE coidmandfrtil~}addr_res_h<2> as listed in

Table 4-12.

.·.·.·.·.·.·······

·.·.···:.·,:·:·.:·:·:·.1·1·1.[lljj~_:_[.1_[.:_·::_._:_.:=.:=..:__:=:._..:·:._:.·:_.·._=·.=.:.: _.'._.:,:_:=.\~l/:·

/1[~ft:~:[lt:b:·:·.

Table 4-12 21164 Responsesu;·n
addtltes h<2> to 21164 Commands
..... ·::::::.
~::=:::::=::::::::-

a8dt_res_h<2>

Scache

Miss

Hit

4-l~;::::P.:f~i~lt.;.:::::~11jl~M.;:=::~est-case response time to sytem commands in

Table
a write iqjJ1idaW.j~jp~9tocof=system.

1J,~!~ lmum Response Time to Write Invalidate Protocol

Tab11fJL

-4~l~~:::~li1iI,

·commands

Response

Number of sys_clk_out1_h,I Cycles

NOACK

8 CPU cycles rounded up to next
sys_clk_outl_h,l cycles

ACK/Scache

12 CPU cycles rounded up to next
sys_clk_outl_h,l cycles

NOACK, ACK/Scache,
ACK/Bcache

10 CPU cycles rounded up to next
sys_clk_outl_h,l cycles

Preliminary Edition-September 1994 4-55

4.9.2.2

~~DR~:~~;~~::!::~~·::~L~~::d modified data from the ca~lih

system. The block status changes from DIRTY, SHARED to DIRTY,SHARil.~
Figure 4-25 shows the timing of a READ DIRTY transaction. TPJ~~~@~b.~ ii.I~\.
probed, the data read (if it is found), and the state is set to SH$BED>lWtlUdH1t.
data is not found in the Scache, it is· assumed to be·in the Bc.@h.i. The 21i6:4::~=\jf\.

:;s~~B~:;;:,:;::;sc:~:~:i~=::=~~::\wmRTY ll
command except that the block is changed to VALID r~vr~·;··:li~tt.o S.HXRED.

,, c::,,wtt

,4•t:::~~tr

4-56 Preliminary Edition-September 1994

data_h<127:0> ------·-·==::::-::::::-~:{_::,____,~__,__,,,__,, ___, __
~
i¥?:::::::::{::,t:-:·.

dack_h_....~---~~~-+----~;,;,;,.,..~:-~.;.--~.;.--~--~.....,~L_J
..:::::=:..
·=:::!,11/

i r0
$

~~~-----~~l--~~~-+-~rJ

.....,_-;:i:~~1---+~-r-----1:1i:-~---------~-~
:
ll

--~--~--..~--..~--~~.....
iI

•

~
<

I I

tag_valid_h
ML0-012408

Preliminary Edition-September 1994 4-51

4.9.2.3

4-58 Preliminary Edition-September 1994

Figure 4-26 INVALIDATE Timing Diagram

sys_clk_out1_h

addr_bus_reg_h -+-_....,!;...ii

i.&1r~

··\:~~,~ll~::·
.·. :·

...·:.·:.·:·.).:.·:.·:.·. . ··:·10

,:~.:
~·:; :~1;:
:~:
)l.~: .l: :;: :·.:1.:.:~.:. : :~: .:~: .~·.:~=.·.:;:
cack_h-+---€-;----;~F.---~~--...~-~i~/~d_f_W~F_-t~®~~t~L~.
-..;---....:---;..
::·.::.:=·..:·.,:.:.:::...::.::::·:.:...

•

. =~:i=ir·

··:·=:::~~~mm~~~~t:=:·. . ~

addL~~~~~:~~~:l:~~~:~~~:~~~~:,~~,:<~~~m_r_l_~m~~~t~=~~*~·~=-·~._:~:J~l"----=---l~i

index_h<25:4>

--i----+l-...-:ii=;..-.~~~~~--~~_..,.;:;OOOO.;+l:;;.;:;...---;~-+---+-

data_h<127:0>

-+---+-'-~~~.......

dack_h-+---+-..,;,.,;,;,~--+_...~..,.__..,

data_rarn_oe_h
..:::·:·.

_..,_

_..,_~

·t_~~+l,~l_~::·~~-_...~~~_.
j

~:t~t~~::::::.. ~

data_ram_we:M~~t~~~~;~it,.,..):-::. ·-+J_.;.;;;~~-ii---+--,..;.._-...:---.;...-~-----+
tag_ram_oe...b. ..., , ,+l-....;;;;;~-.;;.--~-. . . ...1n. . ...;-_-+-~--i----!--~

---~--!l---.......__.n;"'"--'"--.....---:------------l-

.·:·:·:·:·:·:·:··....
:·:·..,,:+.:,:,;.

·~~~_..j~---~r:~-+-~..;-____;;.---;..~~~-l-

tag_valid_h

i
-+---+----"1--+--p~·!'---;..._-.;____..;__..:.-_....:.-_....:,.
!~
~~
M.0-012409

Preliminary Edition-September 1994 4-59

4.9.2.4

~e~H~~~~164 receives a SET SHARED command, it probes the Sea.,,

and changes the state of the block to SHARED if it is found. The ~1164 \{~~~t:
"assumes" that the block is in the Bcache and writes the state ~f:tq@t~K.~{fk.
SHARED, DIRTY. Figure 4-27 shows the timing of a SET SHA.f®D ·caifi•i.D@~}~::.

<~1)t\\\\\v ,,~4,

t(~;1\{$

+ft

4-60 Preliminary Edition-September 1994

,~,,::::~''®'

Figure 4-27 SET SHARED Timing Diagram

sys_clk_out1_h
addr_bus_reg_h
crnd_h<3:0>
victim_pending_h

addr_h<39:4>

~---+.iiI I I1...____,.~-------+---+i-~i~; ; ; k; ; ;!l~I_!=·

---1--rSET+6EDtr--------;1-.{:-\i-:i;;;~-;:;;;_+:;:i.~:·!.::-:._:::_
=•::.-·.:.:~.:-.:~.;.:=,.:~::.!:_:~.::_·~.;~:_:_::;:~:~·:;.:;~;+-;i':'.~_:~.i.i.·_:::.:_:._}
! ! !
I 8 Jo k o~l'· ll ·:rr1rn;1
.: _: .=·:·-.·•.:·,· :.;·:.

cack_h

0000

!~
!

addr_res_h<2:0> --!-_
!
idle_bc_h

!!
i,

___,._

·rt\\,...:

j[[jj[?===··

:i/l?:::::·r=t!!~lt:L.
. :::d~tit\::.. l l.!.!.:_~.:~· =~·.==.~._::':·:·_.:_:=_.='.:'_:·_:·:·.:·.::·:·.=·_.:·.:_,::_·.::f:i._:=;/..:~.
1

~.;.

··:·:::i:::J::::..
:·:·:::::::::::::::.... ::

..,·.=,·.·:·:::!',:'_:·,:.:=,..:.:_:·

___,_ _........--

-+1----i----+----r---+-~,:,;,;,.,;,--~:,;,;,;,;,;,.,.__ _.__--:.._ __. .

inde><....11<25:4>

1_______. . ._

data_h<127:0>

daclLh

_ __..

-h~~~~~__..~~.....--t-~-+-~-i-~+-~+--___..

·=(!~~}

data_rarn_oe_h .......f"_.....,. ___~,....,...._.....

4~~~~t~::::::. l,

...

~-~~,....+--~-~ nL-..;_ __;;,...-_;..-_.;...-_...__~
........,.,..._.....,. __,
....~~:
_.,.

_ ______ ______ ___________
;.,._

---__;;;;~--+.~-+---~~:~-;.-~:----+~~~:---+
!~

~-+l---+-l---+-l--+--'~1---i---4---+--+---+---iMLC-012410

Preliminary Edition-September 1994 4-61

4.9.3

NOP

'!"ij?~.::he~i~ ~T!~l\iii.:;'$ilf the

0000

FLUSH

0001

READ

0100

Remove block from cach~\it\·e.~ di4y:::&ta. The
FLUSH command.J~Wl~S a bl~ tqJ•. removed
from the 21164 9.@:He~=~~m.·===tt\l§~fblock is not
found, the 2116~Ufesporitl~j\j\tj.~h NOACK. If the
block .js found{~itld the bloekJt~~A!lean, the 21164
respaij• witli''iSl~QA~K. The hl&k is invalidated
in the l>c~he, SC'ful~,. and Bcache. If the btock
is found atHUµt. dirtYt~~:k~ll64 responds with
ACK/Scache . oflACKIBcache. If the data is found
dir~J.ftiftP.~. Sca~htfit. is driven at the interface in
the.H&me''l~~k m•t'tlle ACK/Scache. If the data is
fqq~d dirty.'Uf~h~ Bcache, the Bcache read starts on
:=::fili.~:::~~e syscilfits ACK. The block is invalidated in
f/fthe . Uiwbe, Scache, and Bcache.

t:l~~~::::~~:Ju~ad ~:::Bl~,. The READ command probes the

·.:,:=tt~~che and"''Bcache to see if the requested block is
·:fl=t=:·.
..pr~~D:t. If the block is present, the 21164 responds
·lf:::::....
..\t)\,... witlflA.CK/Scache or ACK/Bcache. If the data is
· : : :=t{:[ [I[·.: .: : :=.: : .: ,:.:=,:.: : _:·,·.:,·.==:·. ·::''\\@kin Sc~~he the data is driven on the data h bus
................. ····::::~:ii.M~he s~e sysclk as the ACK. If the da~ is in
··'=\@\\\\:\:,.. the Bcache, a Bcache read operation begins in
·===it=·

tt::)'"',,:<'E=:i~~:~~~~~~~:~:e~~i~g~CK

4-62 Preliminary Edition-September 1994

.J~h.

4.9.3.1 21164 Responses to Flush-Based Protocol Commands

The system responds to flush-based protocol commands on addr.....re.si\~1:0>
as shown in Table 4-15.
\Jj1\.
.)~~)~~~:~::::::::=:·:·.·.

Table 4-15

21164 Responses to Flush-Based Protocol

Bcache Status

Scache Status

No Bcache

Scache_Miss

No Bcache

Scache_Hit,Not Dirty

No Bcache

Scache_Hit,Dirty

Bcache_Miss

Scache_Miss ./)~:::,

:::{:::::::.

ecd)~:::~'\\1\f~'''b

ti: t(~~c~e
NOACK

Bcache_Hit

ACK/Scache

Bcache_Hit,
Not Dirty

NOACK

Bcache_Hit,Dirty

ACK/Bcache

addr_res.i!i-~w al;:~!~

The purpose of
system without a duplicate tag
store to determine if a b.ld~~ is pt~S.~~J in the Scache or lock register. The
system logic coulij/then."ll~ij~j[this info.trii~tion to correctly assert tag_shared_h

~: :~=~,~~"':a'FLUSH, READ DIRTY, SET SHARED

and READ DIRTY4.ti¥.ALID.'[;E commands on addr_res_h<2> as listed in

Table 4--16. ··'"@'""·
Table

''"t:f~fi('.j;. "'

4-4F::J~onses on addr_res_h<2> to 21164 COmmands
··:·:·:·:···

:·:·:·:·:·:··

-:-:·:·:·:·

addr_res_h<2>

Preliminary Edition-September 1994 ~3

Table 4-17 Minimum 21164 Response Time to Write Invalidate Protocdl\
Commands
·\l:~l~t:.
cache Status

Response

No Bcache

NOACK

No Bcache

ACK/Scache

Bcache

NOACK, ACK/Scache,
ACK/Bcache

Table presents the
aflush protocol system.
4-18

21164

best-case respon!!,fL~~~ l.m;~~~ands in
d\'J.tr'"V'\\\ti{\~'.WNW

ib.

Table 4-18 Minimum 21164 Response'T~_me toJflMSh Protocol Commands
.·:·:-:-:..

4.9.a.

····:·:·:·:·~·:·:·.

Cache Status

Response

No Bcache

NOACK

No Bcache

ACK/Scache tlj\lf~~Y~ffeit,;J-ounded up to next sys_clk_outl_

Beache

,:f:Jl. 10··02\L~ycles plus [BC_RD_SPD] rounded up to
;~~t~\4,,fj;:,~ ~i'clk_outl_h,l cycles

;;~~~;~deci up to next sys_clk_oatl_

NOACK,

~s;LUSH co~::::{~=:~!~':iremove blocks from the

cache
0
;;::e~l~f;~~~~ti:!e ::a~:H~::::::d written to
:e:::.e.;\1(~4t Figure the cache block state changes
. . .ftQ:m
in

21164

4-28,

Df&WY,SHARED;·VALID) to DIRTY, SHARED, VALID. When the block

,:/~[~~Mt~~4~hart9~:::t~ VALID, the state of SHARED and DIRTY do not matter.

4-64 Preliminary Edition-September 1994

Figure 4-28 FLUSH Timing Diagram (Scache Hit)

~~~-. . .,.,;,;o; i; :,:j;i.~,;,;o!~[- .· ·~,...[\j\\;;;;;;t~~t;~-;::-!i----+!--~--+

addr_res_h<2:0> --;;---r----:i----+-l

::::;;it: ,:·.,':·.,·.-'_,.:--'·_.-=.-'_.·=·.=.-,_-'.:.==:·.·.=:--:,:,:,::::::::::.. :
:
:
idm_bc_h--t-~--t-~--t-~--t-i~--+~~~l-"<_~~-0+~~b~t:~:--.~j~--i-j~--i-~~~~
,:!·.,:._

!.1..

index_h<25:4>

~- -l- +-·o~-, .:_ !i~:~;~;. ,i ;:; ,oi i :~:~:~:~L'"·~·: : :-~=i1\{:.:):~: :~;~;\:'"h~!. - -'=_: : :_~t., · j~.:.:~~=-=,,~=-=iiF,\--
··:·::::~~r:

dack_h

-:-/1"-~h-, ._.......,~~--:--""';;;;;;, :;:;:; :~ ~j:~j~ l-t-1-:·=·~-~;I
..

data_ram_ss:. -.. :,+:r_:'_,.,;,;,;,.;,...---+........~

:_:i

LJi!:i.•

.......:!= ________....__ _..___;,..._----'

.........;.;._~~--...__..........

~~-~~~-

tag_valid_h
ML0-012411

Preliminary Edition-September 1994 4-65

4.9.3.3

~~DREAD command is used by the system to read DffiTY data from tft\'k

21164. The tag control status does not change. Figure 4-29 shows. the timmg
and tag control status of a READ transaction.
.·../1l~lHt:::::::. ·.. \(~:\.

t\\\\~~:~t&i,,

Ci(!:r~~i'

4ltt,

"'~{#f\t\iey,~~j~: : .: .'.'\ w,
!tf

··:::;::(~:::::::::

tt;~~)l

t\•lt;~if \fo
····:::··

4-66 Preliminary Edition-September 1994

Figure 4-29 READ Timing Diagram {Scache Hit)
-:=:·:·.·••

sys_clk_out1_h

addrJ>us_reg_h
cmd_h<3:0>

-1l I il..__rl--+---ii---t---+--~~ffl:i:---+--~
~

--:;....-~~'--=-R=Eft=i-=D~-4'k.'---+---;---;--......;..~~~-;..~~~~

~:::: =:io:= :l-: _-Of"',_1_40-~- -~-+l!"-: : : : : : : -o. .; ;~·~ ~i-:l~f_:-w_~,_~= ~'-:~;. :i:;,. .1.;.:i;_.!,. .\[ -\ . . ;t. . ,~:~'~:~ ~ =~ ,: : : :l

ad •~-: : :~:~ ~:1~ ~ :1~ ~:i~=~ : ~ ~,1~ ®~*:*:~:J:~: ~:~ -:~ ~'.~'.~ -~ ~-~_;_i_ru_1_1_1~r_·
tt:..

·.:.::::~~~~f

_____-Iii

l ·-:·::::( ~

index_h<25:4> :t=:t=r:Ll2!ES:~~iillC::J(~mj(~~~~~
·:·:·:·:§··

~~~~~~~~~~~__.rr

I I
tag_valid_h
ML0-012412

Preliminary Edition-September 1994 4-67

4.1 o

o;:~d~::~2~o:~:~::~~~!::san~:~:~::::~~~:\u~.
The command/address bus is composed of cmd_h<3:0>, addr_h<39.;4.>. anid\\\,
addr_cmd_par_h.
==~l:;;;'.===:=::=tt~{\\l}t~~t:::;;tll~t:.

!::af~~~:n!~:~:~~ ~:;:0;i:=~~=i!:~:~~~e~~ni:~~,1,~se ;:;;it'{']
0

410 1 Command/Address Bus

. . Figure shows the

""'"''·

'"9'tv}

and the system altemJe~*'

4-,30
21164
command/address bus. If signal addr_bus_;req_h is di~erti.d at llM::::~nd of
a sysclk 0, the next cycle on the command/addr~§§::::ln1s belj~s -W.l\[fhe system.
The 21164 turns off its drivers at the start of ~y~ik~\\J~t=)Vhil~))Jbif.system must
tum on its drivers during sysclk 1, it must ~Aiure tliititb.~ drivers do not
tum on before the 21164 drivers turJ!J~ff. Tht\~IJ.164 sairtpl~·s the state of the
command/address bus at the end or"s'yscl\. 1. . ,"ff:~k.4t--busJ.-eq_h remains
asserted, the system should continue to aa.v~ the·:::OO.lnmand/address bus.
4
Figure 4-30 Driving the

Comma~ ~11;1ii''Y'

sys_clk_out1_h

_ _ , ,- : ~.;~/L 4!~-:~\t-@k\t~~f;,tp . \____/---\__

addr_bus_req_h

\_____

21164 Drive

AtiAM~~ill of the command/address bus back the the sy:::-00
to

21164,

,::/\[}~::==··· sli"<ittll tum·==:mt~it.{; drivers during a sysclk and deassert addr_bus_req_h. The

. /~)ff'.. 21HM~l~does not>iiinple the state of the bus if addr_bus_req_h is deasserted.
<~~{i~h:-:·. Tqg\~~2h64 drives the command/address bus at the next sysclk edge.

' %-lt(,fmt·
4-68 Preliminary Edition-September 1994

t'fP

4.10.2

:::a':~!:, :ai:_:;127~:~~a~~~ ;:v~~e=i:~ 21164, the Bca;l\1t@rray,

or the system.
./)\\::=:=··=· . \{ji~==·
In the case of private Bcache write operations followed by pmy·arntnt~~b.ilil~d
operations, the 21164 stops driving the data bus well in a.4.Y.~1.ice of the·=·=eMi'-lw
turning on.
··==\{ljljj~:\~i!t:t::,..
.·:=;:!l!i!l! i:
For private Bcache read operations followed by priv.;~!J$/§,~achtFWQt.e
· ==: :=:==
operations, the 21164 inserts a programmable null!P.~Fof\ft~UJ cyclikbetween
the read and the write operation. This allows tim,Ifor t)t~fB¢i¢.h~t· drivers to
7

turn off before the 21164 data drivers are
- - - - - - - - - - - Note

turned~' ,11.::. ,.:~.: =:.:~=:~.:.f!i.l'j'
. .

&ffafil1\t;;l{t+,

This rule also applies to WRll'E BLQ$.l{, WRITFUBLOCK LOCK,
READ, READ DIRTY, READtQ.IRTYJij{y~Jmd FLUS.H commands.
•

.i~~~~)::...

··~·::::~~~~f~}}::...

Preliminary Edition-September 1994 4-69

4 10 3
" "

~~~~l=·:~:cfu: :::~~hand

fil _h

fil

BJ~.

signals to data into the
The system asserts the idle_bc_h signal early enough to ensure th:~t the 2:1.lP.4
completes any Bcache transaction it might have started while ~aj'.ting~[~f.9.~tt.ff.ij~~~[\
fill data.
..J~:J!\!l!!t.
··.·-:,::::::::~:fl\t\\\\~\j\j\\\ll!!tt.
Signal fill_h is asserted a fixed number of sysclk cycles beforEfUitJill data to \th
start the fill transaction in the Bcache.
. . \f~lt::...
.:/lF
At the end of the fill, the 21164 waits five CPU cycles ~8fJi~~itArt~it!~~~\fead or · :,:,:·
write operation. This time should allow the system t~Hirrn 9.1·n~~~~qf:Wers. If,
in practice, this is not enough time, the system may a·~il;rt~lfita_JiUs:req_h to

:::i::;~~.:;:e:ssert idle_bc_h

t&flJ~ffft\'v;J&A 'ltwm;@f?

The equations for calculating length .9.f time:::t.~[\[..ssert iditi[bc_h are:

read_hit_idle ~rts~~~~:~~=~~~~~i~:~ ~,1{~~1!\~,eli:':ng;
::::~m~::~idle ::: ::~~~s::.:/~~=~~,~~~f:t:::~:::~t~::~:f:~rn off;
=

Take the largest of the thre~ ,,t.!llifltt~g th:~==~~fg~d up to the ~ext s;sclkboundary.
:::::::Jll
. :,:::qi~~tt:=:·.

When determining
t~js~!{~@!tltb.m:i off ;~Ji~s, if the system will not turn on its
drivers for some4HJ.mbe1{9.f:J~.ano~~p~s after the 21164 starts driving Bcache
index_h<25:4>; . thl~~tJJ.me''''&itt::b.e us'Mf'to reduce the tristate_turn_off time.

tRk

For example if the ~i~~~IHtr~t;~tii~~~§:· (64B block), Bcache read/write speed is 5,
with no wave pjp@liajpg;·=·2q•'§l~s .for tristate read, 0 cycles for tristate_write,
then the equa:.t!ofi'S"\~i:Utd. wof:khmt to:
read hit

i9l~l!.:lliil=~..:i~~!itJ~jr;:·~~'tl~) * s + 2 - 3 * o = 24
1 11

,},,t;~~\~~~: : : ;~'. :2:~:; ~: 24

;;t1~~~\t(~;;,

'"\Ji'

4-70 Preliminary Edition-September 1994

If the 21164 receives asserted idle_bc_h at sysclk edge N, the FILl/~pmmand
can be received at sysclk edge N+3. The 21164 drives index_h<25:4$kto fill
the Bcache on sys elk edge N+4.
..\ljlt.
./~~~~~ftt:::::=:-=·.·. :=::~:r~::::

Figure 4-31 Example of Using idle_bc_h and fill_h

i
l
,
l
·
_
i
,
~
_
i
:
!
.
:
'
~
_
.
'
:
'
_
~
:
_
.
,
f
_
.
'
:
~
_
:
·
,
[
_
:
i
<14'll1~1111w··
. . t&+ ' •<tttt\\f

N+1

N+2

N+3

N+4

,!_

,.=,:_,:=
,i_!
__ __ ...

sys_clk_out1 _h,I

lndex_h<25:4>~
data < 127:o> l l l l l l l l l l l l l l l l l l l l l~l l l l l l l l l l l l l l l l l l l l l l l l l l l l l l ~l l l l l l l l l tl l l l l l l l l ~l l l l l l l l l l l :·

"\1);•~1;*\1t '

ML.C>01Z413

ik. ''1 ;fa,.
Minimum idle±@e+~_ . i'iffil::::~tt,.,
If the sytem contMP.~k~ Bca$.l~2 and the write ratio of the Bcache is greater
than or equaLtR. ~wfo~jllj•~- sy.~flk ratio, then the minimum idle_bc_h assertion

::ee::i~=·W~!:f~rite
speed is 10, and the sysclk ratio is 4, then any
asserti.9n
be for two or more sysclk cycles.
'&tti4Je'.:_bc_U.~limust

<il'~~l;;::ft11n11'i;ttr

Preliminary Edition-September 1994 4-71

4.10.4

:~~::::.!~:;:_:~h can be used along with the idle_bc_Ji si~'\9

prevent the 21164 and the Bcache from driving the data bus. In g~p_eral ff.tit.
system should not need to use this feature but it is useful if theJ~~i\WtPMl~~§L

:h:::e==~~:;~ed:::s, the system must ensure that id1tpi~:,::~~i~\}

by asserting idle_bc_h for the required time. It can the~J!~serflti.t@_bus_ -::{J/
req_h. If data_bus_req_h is received asserted at the ri~JHg~l~~gge of.;IM~Ik N' ·.··
the 21164 stops driving the bus on the rising edge of ~y~tlk Jif.:ttt::,.,...·:·..., , .
To return the bus to the 21164, the system should deJler#P~~Jal~req_h
and then deassert idle_bc_h on the next sysclk._,.,:,::::::~::':·..
llL . /Hf
Figure 4-32 Using data_bus_req_h

N+4

sys_clk_out1_h,I

data_bus_req_h

Ml.().012414

4-72 Preliminary Edition-September 1994

41
. 0.S

:::ii:..~:~==~, cmdJi<3:0>, data_Ji<127:0>, and tag_data;~
buses must be operated in such a way that no more than one qf!yer ni'i.!tP.rive
the bus at a time. This section describes the 21164 features.thitfowLhe\ised
to pre~ent tristate overlap.
../:~::::~'tll:··t ··.··:·:::::=:::tik{l!t::i:lil!l!!::l::::
The "owner" of each bus must drive the bus to some vahi-e:::f.qt:}~ach cycle. \lt
Tristate drivers in the 21164 turn on and off very fast . H:P. th·~:::o~fl::J~s to 1.0 ~f':
range). At the other end of the range, SRAM memgf&ilf~\ti~.~s tllfijbm and ·.··
off slowly (in the 7 .0 ns to 10.0 ns range). Gener~jJy, sy~futdriv.efs fall

4.10.s.1 s~;;:::::.: 1::~·

A¥1tt.:lt c:: 4~;rir

The time required to tristate the 21164 ddveri''1ittthe endVi)f a WRITE
command, or the the Bcache drivers at ~h4~:)¢nd or"°~{lft.BAD command is part of
the idle_bc_h equation.

4.10.5.2 BCACHE VICTIM to FILL

.(:tt \i~l~:):\,.,
.·.·. ·.·:··:·:·:·:·:·:·:.~.J..i·~..i~.'~)._~,:.:_:_,'._,_,:_,:'_.::_,'.:_.·':.·._.·'.·:.··'·:.·._.:._:._:_.'.:_,_,. ..,'\f'.

The time to turn off the Bcache .drivers atft.he en"d. of a BCACHE VICTIM is
fixed by the 21164 design. Th~tW~ti:tlb@u~f'::iJl~w for this time before starting
a FILL.
..:::t(:;!i!!i:i;:,..
.. '\(l:[j!:i:~:~tt:,=- · :There are two READ MI&$.fMtlK\?..~tim carfos to consider. In one case, the
READ MISS operation wilt°be cortiP.l.t:t.~d first because the system logic contains
a victim buffer. -::Jn:-the ol·i~u~ase th~'4JEAD MISS operation will be completed
second becall:.~-~ the ~t1t.em . 'i&m~Aloes not have a victim buffer.
READ MISS ''eim.P..~~;:a::i~J.r~

. .,\liil1m Buffer

The final dack_if::WilJ>e·.,~,iffipJed by the 21164 on the rising edge of sysclk. If
the correspoqQ.ipg r1si~gJ)PlJ':Hock edge is labeled N, then data_ram_oe_h

MU deas(;t~,,~~~e of clo~ N~.
CPU

<tl ~litw1;
Preliminary Edition-September 1994 4-73

Figure 4-33 READ MISS Completed First-Victim Buffer

N+1 N+2 N+3 N+4

CPU Clock Cycles

sys_clk_out1_h

dack_h _ _ __

13
index <25:4> - - - - - - -

data_h <127:0> - - - - - - -

data_ram_oe_h ----~~--~~--.......

. : : :.

READ MISS

tltt..

····:<%[~}::·

~Nlf~~~\~r

2415

The final dack_h witlHM~ sailiP}~q by.. 21164 on the rising edge of sysclk. If
the corresponding risirtg#~f.U cfoi}t edge is labeled N, then the READ MISS
command will ~rdt'=~hQ:ti iHiWP.~~t sysclk edge, and the data_ram_oe_h will
deassert at tl)~}Hsing~jijdge of:dpu clock N+S+ 1, where S is the sysclk ratio.
If the sysclk fitio i~[:[~:~ i~[~[\yill take an extra sysclk to send the READ MISS
commanq~,,.,~o 'ifl~AJ.ifta_._oe_h will deassert at N+2S+l.

q~l~\\::littt11\i~tW

4-74 Preliminary Edition-September 1994

Figure 4-34 READ MISS Second-No Victim Buffer

CPU Clock Cycles

sys_clk_out1_h

~l~\~~TA1ss

and_h:
index <2s:4>

dam_h<127~

i~~=;;~:?~~~1~= =: :.

·:{!~!!>

data_ram_oeitt)\:::::..

..................··:i

~,,,~,~{~~~::oc\ttt.......
·:::w~))liii)1\...

·{)lt:::..

":·: : ~@~j~j j )j j j jl.~ .J:·

"ilql\t~.~.~.·.~-~.~:~· ·)·
'"i'.t{\!t11~1'.lt\i'

' ' ,,

· : : :{'.; i1~1 l1l1 jl1l 1 1l 1iljl1 1 1l1l 1l~1l1j1 ~l1 1 I1 1l1~1 1 1~1 1 ~1 1 1 1 I1f

ML0-012416

··:::::

Preliminary Edition-September 1994 4-75

4.10.5.3 System Bcache Command to FILL
./~\.
At the end of a system command that uses the Bcache, the system mu~)tt.
provide enough time for the Bcache drivers to tum off before retu~ing aii:Y:~~fill

data.
,:)t~;::tl~~iit~}\lt:t::;::::;!!!!!l!!l:~::.
The final dack_h will be sampled by the 2116.4 on the rising ~q.ge of sys"CllfklFJh:
If the corresponding rising CPU clock edge is labeled N, datalltiiQi_oe_h will ··:=tlt.
deassert at the rising edge of CPU clock N +5.
··:::=tj{~\ht:..
·:=:J~\}

··:::::::tt::\t>

_.,::f::@fj\::::.

t:":.~:,:';_,:i_: :=.=~.:=:~_.:=:i_:=:~_.:·;_.:.=_.=:,=.=:.:~ ;wtt'

Figure 4-35 System Command to FILL Example 1
N N+1N+2N+3 N+4N+5 .::Jtf@\@~\:...
CPU

Cydas

1111t

dack_h _ _ __

:<:=-=-: @-:t: -; l_;_\ ,-.:.-~ : : :_j _·

4-76 Preliminary Edition-September 1994

:_.:;::::.!:;·::::·:·:=.:_:···.:_:·;
..

...
=:=.'j.::•:_::•_::·:·.:···'::·::···'::·:_···:···.i::
__

t ti\i J·~,(;b,'\)~~~rw1 1 , , 1
'\%\:::::::..

sys_cll(_out1_h

•. :·:·:!.:.:l

··:::::{\\\j\:t~::::-·-· - -

"' ,, ''\ttf\;11;1

;~\{.,i::~~i!Q1-l1~l>

___DO_ _) (

· : : : :·

If the system command was a SET SHARED or an INVALIDATE cg:tµmand,

the system must allow time for the 21164 to complete the Bcache tdglwrite
operation and then for the drivers to tum off before driving the tag_s-@r.ed_h,
tag_dirty_h, and tag_ctl_par_h lines.
)~[l/Jt::::::. ·. \~l1:~\

The 21164 begins the tag write operation one CPU cycle aAjF th;:::;~~~~~~i~l\.
is sent to the system. The write transaction will take ·BC±\N.\lT_SPD cycfoM[l\
to complete. During the write transaction, data_ram_oe_if\®.ILbe asserted.{}~
but not tag_ram_oe_h. At the end of the write tra:q~J.jp_n, tailtipn_oe_itt::::
will pulse for one CPU cycle, then both will go off. /S~feF~tqJEigur~::~ijt_g6 if the
response is driven at the rising edge of CPU cloc~m~~, t4.~i:f":lfi!J@:Jr.am_oe_h
will fall at N+2+BC_WRT_SPD, or N+6 for a 4-cy~W\vn~ sp~i~'t:::··
Figure 4-36 System command to FILL

elffill;~h l\w1tf)W

.·{~t~:·
N
·.·:::::::::::::·:·.

CPU Clock Cycles

sys_clk_out1_h

~
··:·::::>

..:J}::..·.

___n____
ML0-012418

Preliminary Edition-September 1994 4-77

.J[L.

4.10.5.4 FILL to Private Read or Write Operation

At the end of the fill, the 21164 does not begin to drive the data bus untlJ[~!\!le
fifth CPU cycle after the sysclk that loads the last dack_h. The 21164 do~[[h.ot
assert data_ram_oe_h until the fifth cycle after the sysclk that J~mhth~. tnit::.
dack_h.
!jj)\11!\t .· · =·= = :=: : ~: ~:k\~\ '.\ \})\~]~jl!l !l !l j~t: =:
Systems requiring more time to turn off their drivers must n6ifiepd any more . '((\
requests and must use idle_bc_h and data_bus_req_h at the ~H~lt:pf the fill to . )![J::
:====··

:::l::e:::~t:~ Pri~e

Read or

Wrl~

t(::,~:!'}\1<

CPU Clock Cycles

sys_clk_out1_h

dack_h

index <25:4>

Ml..0-012419

4-78 Preliminary Edition-September 1994

4011

:i~e~~o~::':s::~!:i~:i:~=se of

21164

interface features.
\
_,
h
.i~ :jt: : : : : :·:·.·. \j~~f

4.11.1~:~~ ~=:=t~:~~e:::d~:~:=~:a=:~::th any.ett:~:;~9,h
\ ..

commands, or removed a Bcache victim from the Bcache, .,,~iil\wants to follo~~fa
either of these transactions with a FILL, then the earli~-~t polfiimth.e system .¢.i.iJ.
assert the fill_h signal is at the sysclk after the lasM~ii~ftJpn of::da¢.k_h. . ,.,.

4.11.2

::!1t::!tf~~~e!r~:1~ ~~: ~:~:~:~~Flb~sf bil~b:ck-to-back
Command Acknowledge for

WRITE""81~ Alm.Ands
'*filTE.

When the 21164 requests a WRITE BLO:d.tf or
BLOCK LOCK
operation, the system can acknoW:l,~dge ~'-j~jli~ta by a.ting dack_h before
asserting cack_h. The system mftst.,,3$serFijl.~}t_h no later than the last

4"11"3~~~:~:::::;c~:e::i:~~;~~' s~e.

If systems without a Bca~ttilmjii~~tw.i Sc~~R~· duplicate tag store, they are
required to main~ain tag§;j(9r the.l\ig~J?.Jocks in the 21164 Scache victim buffer.

4.11.4 WRITE BLOc=i@>LQ.C~~~t~~~jjlth,.,..

·.:,:,==tr

A WRITE BfiQQK Ld8.Jibt:r~:~·on is caused by a store conditional
instruction to I7C:n~P.~~e.··.,1WQ.:,::9ctawords of data are provided by the 21164,
each requiring the··:~it!rn to\is·sert dack_h. If the system asserts dack_h for
the first octAWQtft~:::3Ss.~$tg~ck_h and cfail_h together, and the sysclk ratio is
three, thlj~jll'i6j;;;1~:%~,· ···:\/
If dae.k_liU~~ql[:,b, iijiu cfail_h are asserted for the second INT16 of data, the

. . . . . :~~-~'::~~:::~;any time without asserting

.::Jf{~lt]lw.;rite''hi~r~tion will be failed correctly.

,(~ j ~j j~jf: : ·

:illt.

dack_h,

the

.··::::tlllthe s;':~m~~~f.atio is anything other than three, any legal combination of dack_
,/fN cack_h, and cran_h causes the write operation to fail correctly.

'~'t?{t\1,~:;~~\

Preliminary Edition-September 1994 4-79

4012 2

!!~:~~!:~:u=:~f ::~~!~:~~cur on fue interface between 1~}\

21164, the Bcache and the system race conditions may occur. TheJmJg.~ fo:PU.~

:~P::e:a;:c:c:~i:~~~
=~
~:o:~:::;;e::~~n~:::1~=~~~ttlltllt,
Section
through Section
··ii::
4.12.2

4.12.6.

··:·::::~n::ft::,.,..

4.12.1 Rules for 21164 and System Use of External . lnfiMl.§:~::::::~~t:\:\\\::\\\l::>

<t?

This section goes over the rules for determining the o.r i:qJWHltbt2~l164 and
system requests are allowed by the Cbox BIU. In gen~f.l, Ph~ ordifqillowed is

~~te=~::;~s :o::~~~::::~~::~,,-=~!l\W!
the
aii'.yl::fl1J64
0

command buffer, then the BIU is ..free t~.J*fform

BIU
request.

2. If a FILL transaction is pending:::iitt~,J~~d~~::d~htProdu~·::· another READ

MISS command, with a possible BCAQU:E vfd$U4.. command. The BIU
will not attempt any other com~_@.:Q. ·.:,::\:{h~:\.. ··:::\/.

3. The assertion of idle_bc_h, or:JtR!:~::~iimP.~:::~r::i~=· system command other
than NOP to the 21164, cau.s.~$.Ithe Blffl~tidle. If the BIU has a command
loaded in the pad ring, it .ttlhii:~~=·.the coilifu:.and and replaces it with a
NOP command. The st~t~%f ciiid!b.~a:O> is unpredictable until the idle

4. ;:~:l:nc:::~on ~:~,\~,2::! receives adeasserted

idle_bc_ll,
and the 21164{$.~~- res:P&bd~d t(j::'.:=ijJ the system commands that were sent.

5. The system m~;i:::Hat~~~~~~·:ilf:i~k_h during the idle condition.

6. There is o~J#~l~~Pt.i~~Iiij::)'.µl;; 3, 4, and 5. If idle_bc_h or a system
command~~ii:hive.~IWhil.~ th~{ 21164 is reading the Bcache, and that read
transactiQU:. tm1\W1nt~b1 READ MISS transaction, and it does not produce
a victjm, tij~~(::the 2~,f.fj4 loads the miss into the pad ring. The system may

Atf11~1lt'9!f~~~;:~;~!;~;~~:~~ :y:e!.8~=

.i::::i:v·

~~k_h sfi&q)d not be asserted if idle_bc_h has been asserted or a valid
0

'f¥'{ifolff1f,'!5=
:i=:~::~~~a~E VICTIM transaction is treated as an
··=::=t::t~l~tJttomic pair. The command order, READ MISS then BCACHE VICTIM or
··'=\tBG.t.\CHE VICTIM then READ MISS, is programmable. Either way, if the
fitit command is acknowledged with cack_h, then both commands must be

4-80 Preliminary Edition-September 1994

acknowledged with cack_h and all the data acknowledged with::~!\ack_h,
before the 21164 responds to any other request.
·==tlf\.

9. The cack_h acknowledgment for a WRITE BLOCK or BC.t\QJIE ~Qx.IM
transaction must be received by the 21164 with or befort:t::t.H~4~$.t~:::d#~k_h

acknowledgment of the data. For WRITE BLOCK and ..llCACHE===v.tQlftM;
transactions, it is possible to acknowledge all but the 4~i.1Ldata, and tii"~tfat

must be;t#~~-~before t:
:.=:a::::::~::::::: =a~';''~ti~~~~~~~~o~::::e
~::i~e~ ~7;;h:~::c:on, cackJi
8

10.

last data acknowledgment (dack_h) for the reg~=~ste~~ll,t~M-. ~.pefation.

11.

by the original 21164 reqqest. .:dk~lt\
··==:::\l~\jt:=·
For example, if the 2116~Fli~~ !~.q~~alijg:. -~ WRi~E BLOCK and the
system sends an INVALIDATlttq.;mni'M\g)tQ the same block, then the
WRITE BLOCK command will 'lfi.tlj~~be restifted.

b. If the system does not hJey~ll~lii~~B~.~~~~Jl~tijnd a WRITE BLOCK command
to write an Scache vi.c.tihi bacli=:l~finterrupted, then the WRITE BLOCK
command will not .:MiJff:~krted i{d?fhgher priority request arrives in
the BIU ~./: : .
4~t·l~lll~[. .. ==t:~~jjj~llllltbt·

4.12.2 READ MISS With .::Yictit@tJ;.xample

In this examtt1~~:=.~h~t~iii4 a·~M~a!::a READ MISS command with a victim. The
system assertit=ftBck._h"li!h~two d:iita cycles received from the Bcache and then
asserts idle_bc_ii:{~il cadi'=,=· the 21164 to remove the READ MISS command
with victim_.:~AQ.ipg.""Tb~t:~1164 reasserts the READ MISS and BCACHE

~CTIM w;z:Jn~ed,

at alarer time.

z4~1; -i\ 1r,
Preliminary Edition-September 1994 4-81

Figure 4-38 READ MISS with Victim Example

sys_clk_out1_h Cycles

cmd_h<3:0>

READ MISS

.·:-:::::::::::::.

.::::~:~;~~t~~=t~~~~~~~~~~::::..-.

····::::~f.:·.~.=.: [.:~: ·:=.=~:·:=.:·
..

..::_:=..=·:·.:.=..'.:.:::..

idle_bc_h

cack_h
_ _h

g[f~_.\)_::·_·: : _'" ----------

lndex<25:~fa~,,rl~'~l"L ~:z11X
··:::::::::~t:t~t:=:·.. ··::::::\::::::::t:t::·:·.

---

··:::=:::::::::::::·

ML0-012420

4-82 Preliminary Edition-September 1994

4.12.3

Preliminary Edition-September 1994 4-83

Figure 4-39 idle_bc_h and cack_h Race Example

sys_clk_out1_h Cycles

READ MISS

cmd_h<3:0>

addr_h<127:0>

victim_pending_h _ __
addr_bus_req_h

----------,;i··:..:~: : ~j~ ~ ["'" ~ ;:· _ _··::....:q_\i~ j~ .; ; ;~l~i\t..: ,....__ _ _ _ __
··-.::::~::::

.-:·:·:·:·.·.
.::::{~~?:

idle_bc_h - - - - - - - - -

.,.,,__________,!-i______

x x x
01

•
L

ML0-0124.21

4-84 Preliminary Edition-September 1994

4.12.4

:~~i~ e::l:~~ ~~~~~:~~=::c~:~:~l:peration tha~ses.

The signal idle_bc_h is asserted, but no victim was created, s.Q. . the R'.$.4.P
MISS request is loaded into the pad ring. The system then ~~ii[[[th¢:4~~gq~~t.
Figure 4-40 READ MISS With ldle_bc_h Asserted Examd:

sys_c11<_out1 _h eyc1es

,,4$1~4~\\1~::~~1;;~

I ~[ j j l! > I j~j[!!!jf:'1 . :::;l!!!l!!:ltJ? I

cmd_h<3~

,,t*)~\,i~:-lA1ss

~:-;::: ~~.
addr_bus_req_h

''%li!fllfllfu1

.·.·: : : : : : :·:·.

··:::?i{~.~.~.~. :.;: :-~: ·~:=·.:·.·.·.·:· -:·.·.

..::~~~~~~~~~;~~~~J~~~~~~~:~::::..
Jlt
··:::?~fj~~j[[i[t:::::..

~~_be~ ,%,,::~~\l)J.t\¥¥
~i.i;!~~{ffaL ' '{)}'

'WW

''W

tif:'
I

·=:-

.· : :;: :-

n __

·-··::\~~tt~~~::-

ML0-012422

Preliminary Edition-September 1994 4-85

4.12.5

4-86 Preliminary Edition-September 1994

Figure 4-41 READ MISS with Victim Abon Example

1
sysclkl

victim_pending_h _ _ _ __.

addr_bus_req_h _ _ _ _ _ _ __.

~t~~~~/

.:::::&:n2.6 ICache.Mtt~::Under READ MISS Example

1
16
11f&h,4-!~\~~a:~
:;,!~':..~
l ~::::~: :,~~ r!~ ~~=::~~e~~;:ici;::!s
. the fill. The system then returns the requested data in two bursts, asserting
··::::~q~~ffL::

··'q%v-11 at the same time as the last assertion of dack....h.

Preliminary Edition-September 1994 4-87

Figure 4-42 Bcache Hit Under READ MISS Example

sysclk

I I I I

I I I I I I I

READ MISS

victim_pending_h

A\r "''· ' iW1l1\\;-l1r

addr_bus_req_h

'~,~;'.1.l~~:4t;;·
..

fill_h - - - - - - - - - - . ....

- (~ -l=-:·;%,{•t::::'.®\;4%fc ~+'

idle_bc_h - - - -..-:::-..-.
cack_h _ _ _

......

__,,~-__....,~,.,.._-~.....,.__ _ _ _ _ _ _~ll___
· : : : : : : : : : :.

··:::::(:)::::..

"'=\q~~}

· _·=<_:t~_~t_t~ ~t~t~ ~ q~n_1t_:m: :~:~1_=:-_ _ __

dack_h _ _ _ _ _

.·==::::ftttr

:=:=:=:·..
::{~~:?:=:·=·······:·=·====t~~~~r;~~~-

· : : =t.~.~,~-~.:~,~.:~.=~_.,=.·.:

..,= ·_,· .:·_.=·..,·.,·...'=·

Ml..0-012424

4-88 Preliminary Edition-September 1994

4.13 Data Integrity, Bcache Errors, and Command/Adqr.ess

E~:~::isms

~'t(i4,,::1}Jie

for ensuring that errors on data received by the.
Bcache, the system, or both are described in this section. Tmt~:·d·atiV~Mi@tfi.mt..
control errors are described. Command/address bus parityfpfi:>tection iitiH~,P\.

'"%lt\\\i;-}

described.

4.13.1

~~l~~~:p:~!: error correction code (E,~1!jlif~a1
Bcache
\fNT8
and memory system. ECC is generated by the CPll)fodi;~ch
that is
written into the Bcache. FILL data from the.J~~ach.e t'i%he .~y$tem is not
checked for errors. The receiving node de~d$~~~ift~fa~Cdjjiirt~f.s.

Uncorrected data from the Bcache or sy~t¢.lris s~~f:l:qt~th;···Dcache, and register
files. If a correctable error is de~ted (siig&J>it error}lhe machine traps and
the fill is replayed with corrected aa~::::.. ··::::\:\]::~~\:.
Double bit errors are detected. l(tli~·==::J\~ttm.. i~dl~dtes that the data should not
be checked, then no checking 01ti-9.if~ting==:ii1~:rf'ormed.

9.ir

Each data bus cycle deliver~ . .
1m_;'t~l:l:ft9rtht~f data. ECC is calculated as
ECC(data<063:000>) and B.Ci.(u{lta<127:"CfiR~>). Figure 4-43 shows the code.
Two IDT49C460 or AMJ?~lb66(f~~P..~ can be cascaded to produce this ECC
code. A single IQT.~9C46§:l:f:pip als(F~@:pports this ECC code.

The code proY:i.d;:~/slpgl~ b{£::\ij~tr~ct, d~uble bit detect, and all ls and all Os
detect.
'=\~lll::::ltt~\..... ··==t~t:t:lllt:=:=:·. ··=tt\\l:::}·
If the 21164 is i1i===pitity nio&'-tit generates byte parity and places it on data_
check_h<15;Q~.Jor 'W6.te.::. opeHitions. Parity is checked for read operations.
Parity for ,mi~iW!ij$g:o;:;>Ji:l\iriven on signal data_check_h<O> and so on.

' i,,;11t:::;J\; '

(~tt~ttt'®'

Preliminary Edition-September 1994 4-89

Figure 4-43 EC: ::1111 2222 2222 2233 3333 3333 4444 4444 4455 5555 5555

!ii;&t;~~~J;,,

CBO
CB1
CB2
CB3

0123 4567 8901 2345 6789 0123 4567 8901 234S 6789 0123 4567 8901 2345 6789::0123 ot~}W:ttth
. 111 . 1. . 11 . 1 .. 1 . . 111 . 1 . . 11. 1 . . 1 . 1 . . . 1. 11 . . 1 . 11 . 1 1 . . . 1 . 11 . .
1 1 . . . .·.·.:-::::;::?tt~lh
111. 1 . 1. 1. 1 . 1. . . 111. 1. 1 . 1 .1. 1. . . 111. 1. 1. 1 . 1. 1. . . 111 . 1. 1. LlQ@h.. . 1. . . . . .
\@~\
1 . . 1 1 . . 1 . 11 . . 1 . 1 1 . . 1 1 . . 1 . 11 . . 1 . 1 1 .. 1 1 . . 1
11 . . . 111 . . . 1 11 . . 11 . . . 111 . . . 1 11 . . 11 . . . 111

CB4
CBS
CB6
CB7

.. 11
.. 11 .. 11 1111
.. 11 .. 11 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111 1111 1111
1111 1111
1111 1111
1111 1111

:KJU .

.. 11 1111

CB2 and CB3 are calculated for COD parity (an odd number of 1s counting :dJtf~)t\.,._
the cB).
_ ~~ir=·:· ··==\t[[~j~[[~~~t=='=-cBo. CB1, CB4, CBS, CB6, and CB7 are calculated for EVEN _parity (ar:!JM~~
··:·:::f~l\:·
011

number

of check bi:;~,,~~;\,~ :le 4-1~~'6Hlo

::·~:::::~dence data
Table 4-19 Data

Check Cor~,~~:r..~'T
Bit

CBn

it/..
Upper 64 bl.•
.-:~::::::

CBO
CBl
CB2
CB3
CB4
CB5
CB6
CB7

<89{}

-:·:·:·:·:·:·:·:·:·.

/k9>
··::~fbk\

Lower 64 bits

<0>

<1>

<2>
<3>
<4>
<5>
<6>
<7>

:·_.:~:· ·_:~:~.=: :~-~-~ :.:[{1:_~.~-~:~:~.:':.::_.:·=~.'~.:~_.:·: : : : :{l~ l lt··::::::\t~j~ljlj[l~~::·
: ~\: .

:. .:·,=._.:=_.:_.:=,.=_ .
:::.. :
..:.:.:. . . . . .

· :·: : t\.~.~- -~:~.:~:~.:~:..~:=:.:·.:·_:._:·.:·_:·=.::..

. . .·'··.':.=_.:.': .·:·.·=.··.'.:.·:.· .

{--~tt11t!~:

4-90 Preliminary Edition-September 1994

For x4 RAMs, the following bit arrangement detects nibble errors:
CBO
CB2
CB3
CB7
Dl
D9
012
015
024
026
032
033

CBl
DO
CB4
D2
D6
014
D16
019
025
028
034
036

CB5
04
07
D3
DlO
D18
017
020
027
029
035
038

CB6
05
08
Dll
013
D21
D22
023
D30
031
037
040

'%\~1: : :~) t'¥'}'
:::E;~:~~~~:~:co~:,£~:\~;!,;:~:
Ii! !l! !l! i!!

4 32
"1 •

,i{\¥

fin da~

211s4 w rouw
from the Bcache or memorytM~~~BP throughlj~~~rror correction logic before being
driven to the Scache or D~i~h~'J{lfJJ1e error is correctable, it is transparent to
the 21164.
/Lti
····:::::1n:t::.

ri!litig,:il1'\;h"

4.13.3 Bcache Tag
\lW
The signal lirlMjt@g_ddtttiP..~Ji:jlm:,used to maintain parity over tag_data_h<38:20>.
A Bcache tag dad(jp@pt)/iiWP.r..is usually not recoverable.

A Bcache h~.t::i~JJ.~.~:Xi~b.~:d ·b~;·ed on the tag alone, not the tag parity bit.
The CboxJ@.~foH1~i1lfpe Brii~Jie probe address and the tag value read from the
Bcache. i:\~~tag <l'Ji P.ltity error causes a trap to privileged architecture library
code (P.~~P~t~N'vhicij~i~~andles the error condition.

4.13.4

Bq1.l~'e ~JjlJ!!i:$.ot1tf~1 Parity

. :::fj[@lllf[~;::::§ii.@~! line tag_ctl_par_h is used to maintain parity over tag_shared_h,
::::ff:/_.. . ····:·:=tfiJg_vafit@;.lh. and tag_dirty_h. A Bcache tag control parity error is usually
.::/@/'
iii recoveribte.

-(~j j~!ji\ijljl\t:. ,:::::t~~OC:::~cache victim is processed according to the tag control status alone, not the
··:::?{lt::JlF' tag control parity bit. The Cbox records the Bcache probe address and the tag
···::t(Ift9.?ntrol value read from the Bcache. A tag control parity error causes a trap to
. . :\{f.~code, which handles the error condition.
··::::::::·

Preliminary Edition-September 1994 4-91

4.13.5

:ed:::l ~:: ;.c::~:?s used maintfiln odd parity over,~,\%\
00

addr_h<39:04> and cmd_h<3:0>.

4.13.6

:! ~::~

fill_error_Ji

.J::!:tt::::=:·:·..

..\j~{\.

is asserted by the system to notify thlk.:1~:t:~!:!1t¥

error has occurred.
..·:=:=:?/::::.,.. ··=:::tt~:~~jjj~I:~~)\...
Systems in which a fill error timeout is not expected, ~µj:JFa~:l:l'-::J~maff:ijystem
with fixed access time, it is likely that the 21164 intedil1 Ib.~i!=!•m~.Q.p.flogic
would detect a stall if the system fails to complete a fi~~l~~tran~Wicti"@1:nr

Systems in which a fill error timeout could occu-,;\:mQµjd cdbLu~klBbc to detect
fill timeouts and cleanly terminate the transa~fi6ff=~tlt.the==!iii64.
To properly terminate a fill in an err.Q:r caselitlt.. :6.11_~3f:JJ.i line is asserted
for one cycle and the normal fill seqtiihc~. inv&lnpg lip.es fifi_h, :6.ll_id_h and

~~!:5§~:::::~!~\-~~,Ffue

MCHK

entry point

4.13.7
Assertion of cfail_h in a SYf?.:~S cyclEPibt:w.hich cack_h is not asserted causes
the 21164 to execu~{~. partili:F~ntemaf'N$~t and then trap to the MCHK entry

::t::~::ti~t::d~-\~~;\\~~to ~store itself and the system a
00
consistent state aft~i{[@.gimaHtlb>.t.. address parity error or a timeout error.

. ·~ <f;Q{!\1111t;1:'\U'

,,;~e!::,,

<\1 (\ti~t~t;:

4-92 Preliminary Edition-September 1994

·:tii:i:F

4.14 1

':~r:~~:~as

seven interrupt signals that have different uses dJth
initialization and normal operation.
./Ett:=::::::,.,.__ "\~lh.
Figure 4-44 shows the 21164 interrupt signals.

•kif' "'"WW@jjf,il~-

Figure 4-44 Alpha 21164 Interrupt Signals

%\%'*'W;>

irq_h<3:0>
sys_mch_chk_irq_h

21164

pwr_fail_irq_h
mch_hlt_irq_h

. :::=~=~~~~r~I~~\..

·:::::::::.

' fl'V'"¥tf{\t;:,~.._;;:pw
4.14.1 Interrupt SigQl.~.s Ddl~H)g lnitial~i.tion
The 21164 i:qt~r~pt~~~~ign~}'~~{-4.d~ in t~ndem with the sys_reset_l signal to

set the valu~Mt~tr_martyfpf:_ the . lt~~r-selectable clock ratios, clock delays, and
interface timin~FP.~ame~t:.Puring initialization, the 21164 reads system
clock configuration'::~P~§.~et~ii='from the interrupt pins. Section 4.2.2 and
Section 4.2_!,iJltMf.ipe--:B~\k::t.he interrupt signals are used to set system clock
values wlt~'''"the·':'.i!it~:m l"Mfoitialized.

4.14.2 lnte~.n~~t:~ll§!d.-:C;s-::_!luring Normal Operation
Durtl':no;Mijf~JIM~t*tl~n, interrupt signals indicate interrupt requests from
extitiial device.k':stich as the real-time clock and 1/0 controllers.

411,,1:1)~:1,~?~!f::r:~~:~:~errupts

-::::::{:i:ilt:::,._

are enabled for a given interrupt priority
,,/[l~vel (IPL). An interrupt is enabled if the current IPL is less than the target

\\[\•l~tt;; of the interrupt.

Preliminary Edition-September 1994 4-93

Table 4-20 Interrupt Priority Level Effect
Target
Interrupt Source

IPL10

Software Interrupt Request 1

Software Interrupt Request 2

Software Interrupt Request 3

Software Interrupt Request 4

Software Interrupt Request 5

Software Interrupt Request 6

Software Interrupt Request 7

Source

Software Interrupt Request 8
Software Interrupt Request 9

-(ljj~)}

Software Interrupt Request 10
Software Interrupt Request 11
Software Interrupt Request 12
Software Interrupt Request 13

10· :·=·=·=·=·=·:-:·.

Internal

i!iJ@1.'"" 1't;:9.,rnt.erna1
"i!l{\\Jit\i :::::

Software Interrupt Request 14

Internal

Internal
Internal
Internal

Power fail interrup~i(\lll!!lltt~::::'=·. · : :;: ~ 11t!l~~lL!\)::::,.. · ==: : :==
1

System machine check infu~~ , :l:ii&hially
detected correc~R.l!fit:f9.r..inteiti!p~ pending
External intertl~{"2o~:::at.b i.9-teri®~t at

:~~~~~~=:it)
IPL 21 ?.,,t:J~~)f'

pwr_fail_irq_h

sys_mch_chk_irq_h and
internal

irq_h<O>

irq_h<l>

··=::filf\lttfl~:::=

'.ie;:.~;~:,~~~~::~~'. ~= ~~ ~.~=~~nt~~oo. ~
m

•.

····==ttftJgp;.QR of multiple mterrupt sources at the same IPL to a particular pm.

·qit\l}\@;
4-94 Preliminary Edition-September 1994

(continued on next page)

Table 4-20 (Cont.) Interrupt Priority Level Effect
Target
IPL10

Interrupt Source

Source_.)\:::::,,,.,.....

·:\: ~!.!_!,[:[::_:_::~_-.:'_:_,'·.'·'·'·
__

External interrupt 231 (110 interrupt at
IPL 23)
Halt1

1
'fi?.ese interrup~s ar~ from external sources. In some cas~~· th~:'~ys~~W..en~re~ment provides the
logic-OR of multiple mterrupt sources at the same IPL ..~}~:1~~rt1cula:ltP.P-~~-.-::::::::::r

;::::::::::=:::::::'.:::::::::::::::::·:·.

··=::::::::::::::::::::::::::::··

ipj;errui>'t:~tues:';!\~t

When the processor receives an
request is enabled,
an interrupt is reported or deliv~i%d J9 tli'M~J.:t~ption lo~c if the processor is
not currently executing PALcode. B~f4.nt.vectb\ib.g__ to the interrupt service
PAL dispatch address, the pipeliI_l:~_is c6$.pJ~tely'::afained to the point that
instructions issued before entermg:~:lb.~~t.B.~E~a4.~,. cannot trap (implied TRAPB).
The restart address is savect.Jlll:~he ;~~lj\jg~···::ddress (EXC_ADDR) IPR and
the processor enters PAL~idi~:Hrf:b.e causEFif the interrupt can be determined
by examining the state qf:ifie INTJIL~nd ISR registers.

Hardware interf.Qpt reqITi~~J~lre 1~:~1:~:~-ensitive and therefore may be removed
before an int.~p-upt i~b~~rvic~U~h:J?A.Lcode must verify that the interrupt actually
indicated in ·t~J.UP is''::~~~b~. sertfiij~d at an IPL higher that the current IPL. If
it is not, PALco"di.::~$.h(mld''liQQre the spurious interrupt.

' ' '\(j~i%1q!J''4t~

,,~;i;:~::J:

4f;llt,,t,;r,

Preliminary Edition-September 1994 4-95

Internal Processot11l1@giste-ra

~~;~~~~r0~~;:; :~0~::::

...:::::::::::1:::::,,..

microprocessor

··:·:?H~llll\tl[[llt:·

'~'!'1Wi$f

•

Instruction fetch/decode unit and brancfHllhlt~Klbo~j~lljpgiF::

•

PAL storage registers

·:\J::-·

registers

: ~::::o:::~e::::1::r~;l;~~::\t~w
~ox~:~:=~

\%\f'lit~;'}'''

(D~f)~'~P

cache
IPRs are accessible to PALcode
by means of the HW_MT!184iHa:j:HW_MFPif instructions. Table 5-1 lists the
IPR numbers for these inJt~uctioRi.I\:,:·.
Cbox, second-le.JjJ::·ca~h::::~tl.i.3.~}le), ::;a:~:backup cache (Bcache) IPRs are
accessible in::::tb.e phy~ml.!~ addt~~~.,. region FF FFFO 0000 to FF FFFF FFFF.
Table 5-25 slii\m~riz~:Mthg_ Cb&i~~::scache, and Bcache IPRs. Table 5-38 lists
restrictions on tHM~lPRs ...:t:::n:t:::':·.
· ::::::::::::::::::.

··:·::::~@~?:·

..:::f:I?tt::::::. ·. · : :ql .~.·.~-~:.: .:·.:.~.: .=.=..· ·.·.·..
.. ...

Note - - - - - - - - - - -

Unle~i!!!!:PU~tfl~.:::itat;d:: IPRs are not cleared or set by hardware on
cltjp o@;ttmiout r~i¢t.

:@rr:

·:t~~~~1~lt:~.

..·::/~tr·

Preliminary Edition-September 1994 5-1

·::j~~j~~~~\.

Table 5-1 lbox, Mbox, Dcache, and PALtemp IPR Encodings
IPR Mnemonic
Ibox IPRs

Access

lndex1a

lbox Slots to Pipe
_/jj:j:t:::::::,:,.,....

::::::::::::,.

~==

h ~~ ~~ &1iTub::'~~:::\%\U;l\\l

:=::_TEMP

~= =~ ,, c!:~r1*'

ASTRR

.,~:d~

~~s

:w ~= : : \: . ··{~cr~-1fql*j\f

ASTER

EXC_ADDR

EXC_SUM

WWOC

··=::::::::::::::·:·.

EXC_MASK

PAL_BASE

PS
.ft:::::....

IPL

·(~:-.

~CLR ,,,,,~!~:~t

115
116
117
118

119

WWIC

llA
UC

El
El
El
El
El
El
El
El
El
El
El
El
El

(continued on next page)
··==:=::r·

5-2 Preliminary Edition-September 1994

Table 5-1 (Cont.) lbox, Mbox, Dcache, and PALtemp IPR Encodings\.
:-:·:·:·:·:·.
IPR Mnemonic

PALtemp IPRs
PALtempO
PALtempl
PALtemp2

PALtemp3
PALtemp4
PALtemp5
PALtemp6
PALtemp7
PALtemp8
PALtemp9 ·
PALtemplO
PALtempll

Access

lndex16

lbox Slots to Pipe

140
141
142

El
El
El

143
144
145
146

El .,/J\\\fl:t::::::::ll\::\.

WW
WW
WW
WW
WW
WW
WW
WW
WW
WW

::::::~~
PALtempl4

:;el[ ~'-if> ,.:~

. &:·······:·:::::\\t1Ltl4E

·.·

:::::~: ·(~[::::tit:t:\,...
<f;\+ .,f~11:)11it1th~'?:
151

PALte~p2"j!!::\ .;:Ji::ll~jl}?:· ·: ~! :!Il : : WW

155

P~~tfJ>22:\:[t:jjj:i:~~;;::::::::::::::::::(:[[:::::\F WW

156

157

200

201

PALtempl 7

···-:·:·:·:··ruw

...,.,.,.,.;.:--

::::~~tf~Hfo\'~~:\:l~:fti· " ~:: :~

£1 @~ .: :_'.:'.:.~:.:.:.·:·.:·:·'o.;'.~x, IP,2Rfj~.:.·.: _:~ .:_: ·:

1t11!~p· ·~,~

ASN

'~'$,\lt;~lt~=CM

·~

:..: :·..'·:·.: :·.,·.·.:·:·.·::::::::::::::::::::::::;::····
..

(continued on next page)

Preliminary Edition-September 1994 5-3

Table 5-1 (Cont.) lbox, Mbox, Dcache, and PALtemp IPR Encodings
IPR Mnemonic

Access

lndex1a

lbox Slots to Pipe

DTB_TAG

DTB_P'I'E

R/W

DTB_P'l'E_TEMP

R
R
R
R
W

EO
EO
EO

202
203
204
205
206
207
208
209
20A

DTBIS
ALT_MODE

_,~gr

CC_CTL

MCSR

R/W

MM_STAT
VA
VA_FORM

MVPTBR
DTBIAP
DTBIA

EO
EO

DC_FLUSH
DC_PERR_STAT
DC_TEST_CTL

~f:M:

·2~'=lt\
~:~t~~l~~ll\~:::,,,._ 213 . ,,''tf''·

~~-~::~-~~~ TtMlt::,.. -t:.::~~:}:,. ··:·::::~~l~llt~ii:

~~~~~E ~;:#tt~:~~~~~ttw' ~~~

5-4 Preliminary Edition-September 1994

EO
EO
EO

ti:l:~~~\.

5.1 Instruction Fetch/Decode Unit and Branch Unit (l~px)
Ip Rs
. \i: ~ !~l !l~ j\:
The lbox internal processor registers (IPRs) are described in. $~~9.:R..5.l~:l::,
through Section 5.1.27.
..::\.'.i~!!!I!!? ····=·====:=\fi~ii)i)!l{!;ii1i1!1!1!!!1!!11t\

··q:i:l:

5.1.1 lstream Translation Buffer Tag Register (ITB_TAGE]\,..

ITB_TAG is a write-only register written by hardwar~:JUh~ .i1tft~s11Acc\ib,
with the tag field of the faulting virtual address. 'l)i!!!irfa~~!t::t.he Hi~grity of
the instruction translation buffer (ITB), the TAG @P.Jd pagWl4-hl~:J~ptry (PTE)
fields of an ITB entry are updated simultaneously'~~!py a.$vfite ·=9pifation to the
ITB_PTE register. This write operation caus~.~. . the . 'co:qilnts 9.l~the ITB_TAG
register to be written into the tag field of t4!i!!lfift[~lQcati~fiwW.Hich is determined
by a not-last-used replacement algorithm. ~iWhe :PT$.ti~ld'TS"'.obtained from the
HW_MTPR ITB_PrE instructiol!f.::,.,.rigur4.:[ifik.~ show~flij~=-ITB_TAG register

format.

4®~tt,:'%%!,,¥k ,

Figure 5-1 lstream Translation. ,.,P.wV.er Tagffl.~giiter (ITB_TAG)
31

,,blp;nq~-\~~~'

I : : : : : :,; :+¥f:'.''"~;'11•lt:.": r1 : : : : : : H: : : : I
1

r: :::d: ~:1~ :;:~ :;~ -;~ : -;y : : : :Y: ::H++ :::~I
\\.,~:::~1•1
W-03473-TIO

<~\~~*'

··:::::t::-·

Preliminary Edition-September 1994 5-5

5.1.2

:~~~;~~::~:::~~:~~~~:~ ::~~~:t;::~l\t,

ITB location determined by a not-last-used replacement algoriliitit:J'he TAG ·1i\j:
and PTE fields are updated simultaneously to ensure th~.:::itlkgrityt6.i&he ITB. ·tj?
A write operation to the ITB_PrE register increments :tD:tfifoglMt-u~Ml\:(NLU)
pointer, which allows for writing the entire set of ITB:afrE da:~WAG.:J~.ntries.
If the HW_MTPR ITB_PTE instruction falls in the slii.tiowfit a @~p~ing
instruction, the NLU pointer may be incremente~J..:Jp.ultipl'-\i\Jime.~@}The TAG
field of the ITB location is determined by the c~\tit\1.$.J~f tii~\\\lWBETAG register.
The PTE field is provided by the HW_MTP~ lfB_PTE\i\iP.:§_triic:tion. Write
operations to this register use the Ill~.m1ory ·ft\ihat bits 8'.tma~scribed in the
Alpha Architecture Reference ManudfiFFi~re::::5f::3.t§.hows tli.e ITB_PTE register
write format.

<t:it:iii::ii[iil:t::·:·.··:::,?t[t[iiiii[i>·

::gura 5-2 ~:=~~~~~~;11~~~;:~:::
-{\\.IGN

:::: (~~~:PTE:0
5

IGN

....__---ASM
~----GH

'---------IGN

'--------KRE
....__-------ERE
~-------- SRE
'-----------URE
32

I : H.;ti ;1t:Wl,z,,:.":irr: : : : : H+H : :: : : : :: : : I

.ditJfJlt\'fa. i&lt...

4\l\W Reiil[ori:Jl\'f>

.:tIIL.

. "'"

LJ-03474-TIO

A r¢.id of the ITB_PTE requires two instructions. A read of the ITB_PTE

··:::\l~ilt::::... ~~jster returns the PTE pointed to by the NLU pointer to the ITB_PTE_
··:::::;~ltii$ffMP register and increments the NLU pointer. If the HW_MFPR ITB_PTE

··::Uilib.µction falls in the shadow of a trapping instruction, the NLU pointer may
be . Mif.~mented multiple times. A zero value is returned to the integer register
file. K·second read of the ITB_PTE_TEMP register returns the PTE to the

S-6 Preliminary Edition-September 1994

general purpose integer register file (IRF). Figure 5-3 shows the l'~!t..PTE
register read format.
\\f~\:.
Figure 5--3 Instruction Translation Buffer Page Table Entry
Format
31

29 28

22 212019 18 17

...........,..............-.........

RAZ

.......

~..._.._

(ITB_Pl]§f:!~.~~~d

,;til[ .. ,,Wtfll!f)\j:i;
"-·.::<:~ft~~([\:::..

14 13 12

RAZ

...,.....~~...-~..._.._...,...__.._,_

RAZ_:.:~.f.: .:/l}i: !:it: : _i!.[\_: _: :.·: .· .

:··:·:=tf?·
: : :::.

_._~--~i.....J.~~~~

.::::::::::·

:\~~}:

.·:'::;:;::::·:::::;::::;:;:;::::::::·:·:-::ASM

ji/

i~~7::::::::~~~

:;:::::::::

........

\}~:~::::·.·...-.-:{:~:~:?·

.-::::::;:;:::::·:···:·:·:::;:;:::;::::::::..

(3: H :ST: : : : : : : : : : :

-: : i! ~: :i t

··:::;:::::::;:::;:;:;:::::--

SRE

URE
GHD<2:0>

:+Hil,;:!~ :~,:;,z;~: :::1
32

W-03475-TIO

ttt:b"

<lq\ 't@1 z;1_i.~ -*· ·w·

: : : : : : : :·:·:·:·.: : : : %: : :\ 1Q:;1~ili{\'.\ 1~·

Preliminary Edition-September 1994 5-7

5.1.3 Instruction Translation Buffer Address Space Number (ITB~A~N)
Register
. t~H~~h:

ITB_ASN is a read/write register that contains the address space.JM~w..be;~~lt!t~}::,
(ASN) of the current process. Figure 5-4 shows the ITB_ASN r~~ffmtmi.$.~h:.

Figure 5-4 ~:~:~n Translation Buffer Address Space N'\;i_B_::~·:·:~.::.~:~!;\~ll
a1

1110

i~tfW:J~~t,dt

I : : : : : : : : H+: : : : : : : : : L: t~4#: 11~1+ I
63

W-03476-TIO

5-8 Preliminary Edition-September 1994

5.1.4 Instruction Translation Buffer Page Table Entry TemporC¥¥.
(ITB_PTE_TEMP) Register
. t~~~~~l~~L=
ITB_PTE_TEMP is a read-only holding register for ITB_PTE r~~d.. datd~~j~j~A. read
of the ITB_PTE register returns data to this register. A sec.®.~l¥$l.dtQ.f.;th~,.
ITB_PTE_TEMP register returns data to the general purp_9$.~~:=:integef===f~iiir
file (IRF). Figure 5-3 shows the ITB_PTE register formatM~tifa:..
.. \~~~j~j~}:.

:::: s:::u::::~~::: ::::::~:'~,,:;\\;
··:·:·:·:·:·.

:·:·:·:·:··

=:::/.. &::~l~:f

.J~f

···

Name

Extent

Type

Description

GHD
GHD

<29>
<30>

RO
RO

Set if griiJUiHi~i~m~t-:Mt~~Nh, 10, or 11.
Set if gµili:Ularity . ffiitJ~quals 10 or 11.

GHD

<31>

5.1.5 Instruction Translation
Register

<JJ

:-:·:·:·:·:·:·:·:·:·:··

·''~tj~et·:-~f ~l~ty hi~t~j~tuals 11.

Buff@t1~~~;:;;ll\' Process (rTB_IAP)

=~~\\~\jl1~i=~=~=\~~~~~l:l\\\\\\\~h=:=:·. ··====tfl[\?
ITB_IAP is a write-only re~~- Any ·w.qut operation to this register
invalidates all ITB entrie~(\jKit~~\@~ye an address space match (ASM) bit

5.1.6

,;:;:;::~ z;~ft~l@t!;;\u::·~,~lidate All (rTB_IA) Register

ITB_IA is a W6.w.~o~IY~~~tffil.st;;~l4.twnte operation to this register invalidates
all ITB entries;=::=an~l:J·eseti@tlu~ ITB not-last-used (NLU) pointer to its initial
state. RESET PAL&il=e:. musM\execute an HW MTPR ITB IA instruction in
order to ini_tj;:tij~~:::tb.~:-::NG\Lpointer.
-

'~(:::,Ji

«('~lif~\t

''W

Preliminary Edition-September 1994 5-9

5.1.7

ln::~~t!~~ :i::~~i~e:~::~~~~ vi!~1~:::~~ this regis~\\i~
8

"\llft.

invalidates the ITB entry that meets either of the following criteri~.;....
•
•

An ITB entry whose virtual address (VA) field matches
0

ITB4t6~~~¥li3.~n~ah.

: ;B:::e::::~~:::B::::~:::~S<42:13> an~l\ll, ASM"::7W\\)
is set.

: ::

.-:·:=t~\f\::..

""===t\jl: l: :i: r>

::::~:~:~:~:~:~::: (ITQ~l~)•:2~1~\tf

!~it®tt\%$l,\~1~~%t1WW'

W-03478-TIO

(~(!~)
<t\(lt\\]%1\b

··:·:::::

5-1 O Preliminary Edition-September 1994

·==t)'

5.1.8 Formatted Faulting Virtual Address (IFAULT_VA_FORM) B.tgister
IFAULT_VA_FORM is a read-only register containing the formatted·:=fi~Jting
virtual address on an ITBMISS/IACCVIO (except on IACCVIQ~t_generl~
by sign-check errors). The formatted faulting address gener.~t.ei.11ij~p~m:4~\1L
on whether NT superpage mapping is enabled through ICSftil>it Sf>Eijb.ij\~i~:f:\.
Figure 5-6 shows the IFAULT_VA_FORM register formafaihi~:P.on-NT mode>{[L

~rtual (IFAULT_~1:~,~i;~~~r
I : : : : : : : : : : : : :+H> : : : : : :,~11~1'h~ : .,141iri I
::gure

~ ::!~r

Faulting

Addrass

(NT_,,

:++il:;~1•:r~;t:::w~ir: :
IFAMlf}lc~:~~ster
::::~"
~~:~~
t1-t,::•
33

1M: : : : : : : : : : : : : :
Figure 5-7 shows the

Figure 5-7

F.ting

11A<42:13>

format m NT

(IFAULT_VA_FORM) Register (NT_

1
l;T: ::~z: :~;~; ; ~:i::;;:::~~:t~:H+: ::::::Tr(1
31 3

t1t,4Jt1i); ·11;

.
32 VPTB<M.30>

I : : : : ~1l1: : ;-'\\}ttiti*@;,·: :++++: :::::::::::I
LJ-03480-TIO

Preliminary Edition-September 1994 5-11

I : : : : : : : : : : : : H+~ : :t~ltt:. : : ;~, ;w~; : : : I*I
1

Flgu~ 5-:~::::;~:~::=::z::SS~::de=1) ·~~
31 30 29

5-12 Preliminary Edition-September 1994

5.1.10

DPE

<11;\f~t /::::..

w'fclttt::... Datifparity error

~i\~g:'.'l\1~:\J\f{;!::::::rror or cfaiLh/no cack_h error
5.1.11 lcache FJV§Wi~~''"fa~:~LUSH_CTL) Register
TPE
TMR

IC_FLusl[c'I]#.~:i§==··~BYrl~·-only register. Writing any value to this register

flushes. tlilUelltlf~ Icaihe.

{\\1\,,;:~)Mntffelr

Preliminary Edition-September 1994 5-13

1 12
S. .

=~::~; :~~~~Xr~;i:~D:~'!o~!::: the system airer eJ\wns
or interrupts. The HW_REI instruction causes a return to the instr.µction\l\ .

~t!:~!°:: !~ ~~:.n~:~~::·.!'!8 :;!!~:nC::~i:~tt=~~llt\

exceptions/interrupts and CALL_PAL instructions. Hardware::~~Rte operations==:{[I~L
that occur as a result of exceptions/interrupts take precedence ··~Htf.t:Jµl other )}J

~~z~;:;:~o~n:~~t~~~~:::e;:::.a,Fsl~;'}

value of the instruction that caused the exception. In ·=:t=asgfpf im»fecise
exceptions/interrupts, this is the PC value of tl}.~t@•jnsti®.Mt.#.Ahat would
have issued if the exception/interrupt was not:~i~i>orl&i~~k:=:·. · : : : : : : : : : :,:·

:e~~~p~:;~:::~~~~{~,~i~~;:;"• instruction afrar
Bit <00> of this register is used to indicate::J?.~moa~~}· On a HW_REI
instruction, the mode of the systenvi'=:];\~~miiil~J>y bit <00> of EXC_ADDR.
Figure 5-11 shows the EXC_ADDilWei?tit&tfoniiilf
Figure 5-11

·=t~t==·
31

.·:·:·:·.

./~~~~t::::..

LJ-03483-TIO

S-14 Preliminary Edition-September 1994

'%"

5.1.13

RAZ/IGN
~;,:,;,;,.,..~~~=~~E~~;~~;~t:-::~·~~~swc

.___'_:~:~~M~.~:~~:~,..-------INV

::'!'!';----····=_,,::::::~::::::~:::::.'!-:-.- - - - - - DZE

-~;,:,:,.,----···:~~~~~::~~~~------FOV

. ,_,_____·~:~-'----~UNF
INE

.__~··~~~=~~~~~=·

····

.::::::::::::::...
63

··:::~::::::::::::::..

· ::::::::::::::::::. .

IOV

~wi!~~;::t~::;s~: ::::::::
32

Tab~~ ~o{\~~~~=:r
·-:·:·:·:·:·:·:·:·.

····:·:·:·:·:·:·:·..

···:·:·:·:·:·:··

LJ-03484-

Fields

Name

Indicates software completion possible. This bit
is set after a floating-point instruction containing
the IS modifier completes with an arithmetic trap
and if all previous floating-point instructions that
trapped since the last HW_MTPR EXC_SUM
instruction also contained the IS modifier.
The SWC bit is cleared whenever a floating-point
instruction without the IS modifier completes
with an arithmetic trap. The bit remains cleared
regardless of additional arithmetic traps until the
register is written by an HW_MTPR instruction.
The bit is always cleared upon any HW_MTPR
write operation to the EXC_SUM register.
(continued on next page)

Preliminary Edition-September 1994 5-15

Table 5-4 (Cont.) Exception Summary Register Fields
Name

Extent

Type

INV

<11>
<12>
<13>
<14>
<15>
<16>

WA
WA
WA
WA
WA
WA

DZE
FOV

UNF
INE
IOV

c;~~:@;

+ql ~l1•1 *\ 1i
··:::::\~l~~~~:::·

S-16 Preliminary Edition-September 1994

Description

5.1.14

the destinations l\\

=~:=~
::s!ac::~~~~~! ~:~=~~s
instructions that have caused an arithmetic trap between

EXC.;;.;..~K~;~WP.te

Figure S-13

'W\\1%J!~\\};

operations. The destination is recorded as a single bit maskjp?thiH~~d?.lJ~l~WR
representing FO-F31and10-131. A write operation to EXCi.$tTM ·c1Mii$ttUt:.
EXC_MASK register. Figure 5-13 shows the EXC_MASK:;rmi!,ster format~···:·::\]l~\

~j
00

1+++:--:::
LJ-03485-TIO

Preliminary Edition-September 1994 5-17

5 1 15
. .

:!:.:ss:i::~~=J=~~gi~~:~:!~::

PJ~.

base address for
The register is cleared by hardware on reset. Figure 5-14 shows tb~ PAL2!li~::.
BASE register format.
,::::::.;:'.:::~tF~{~~~l~~t:::::::.,.:'.'.%~lh
Figure S-14 PAL Base Address (PAL_BASE) Register

,,;,,\\\\:ilQ;\\,

H-H+H : : : : :T: :{:}~#:t:::·..
:::'~).'i~lfht':
I
{~~~~!!~1~~~\l~J\f~l~~~f:
1

1
:

. ·. j~~~~!!l!f:::::::·::::::t~~li~~f~\:,.

LJ-03486-TIO

S-18 Preliminary Edition-September 1994

5.1.16

W-03487-TIO

Preliminary Edition-September 1994 5-19

5.1.17

Figure 5-16 lbox Control and Status Register (ICSR)
31 30 29 28 27 26 25 24 23

20 19

10 09 08 07
RAZ/IGN

63
RAZ/IGN
CADE
SLE
FMS

,__--FBT
'-----FBD
'------MBO
,____ _ _ _ _ ISTA

,____ _ _ _ _ _ TST

LJ-03488-TIO

5-20 Preliminary Edition-September 1994

Table 5-5 lbox Control and Status Register Fields
Name

Extent

Type

Description

PME<l:O>

<09:08>

R\V,O

~~~>~':!~~~>"!~·~.a:~
counters in the PMCTR IPRfafre
disabled~:,::::lfif:\

IMSK<3:0> <23:20>

R\V,O

TMM

<24>

RW,O

TMD

<25>

RW,O

FPE

<26>

RW,O

HWE

<27>

RW 0

SPE<l:O>

<29:28>

either PME<l> or PME«B@W.~. set, the countJifi~
enabled according to the settlfiI~::pf the PMC'rjif
CTL fields.
.:f:::::~J::t~~tt:::=:.. "\:::{i:~t::t::·
"\:::::·
If set, each IMS~i?:O> s~~}lisables the
corresponding IRQtH<3.~Q, irlW.fr:*-pt.
If set, the timeouim~:6unl~ coJ.i~::::5 thousand
cycles befo~~::~M-~rtingUJ.mew~th·eset. If clear,
the timeoµ.JfoouP.kr coiinMJlJbillion cycles before
assertiJ.?.g@.imeout::f:!~~t· ··· ·

/:hU set, ·::~ijih1es the iJiJ~:limeout counter. Does

"\:no~:::~~ect=ijttMs~no cack_h error.
If ~~Mi9.~ting~Jtimt instructions may be issued.
. . . .lf cleatffl,~ting~point instructions cause FEN

./:~~:JH~~!fg~on~Mll:i:ttt·

If se~f:aUows 'PALRES instructions to be issued
ke;riiti:wode.
R\V~~r
"''\{mffJ3PE<l> is set, it enables superpage mapping
.(\il.
"ottJ\tf.eam virtual address VA<39:13> directly
""::\tfk::..
to 'pnysical address PA<39:13> assuming

:::t:lll:~j!!ll~~::h::,.~n

·(::t}

'~{l®ti,,~:::~!~:::\\~~~~~~~~::!
~'.;_:.•.·:~.·:·:·!:•.::: •~.:,•!.:•,:,,·':·1··'~w,o ~~;~1g:i;>~·t~~~~~,~~~!d":i~i:~~:~r

Afil@t!~~~"

. :••:.•.:':•. .

:!.:!·'.!.:l·:..

<32>

RW,O

. :t::~j~~~:::::::::::=·:·:·:·:·::;:::::~·~

"''\kl:::::[:~.~>

R\V,O

,~,I~~''"~:

~4>

mv,o

~~ =~ ::~:: ::;:::::.:~::~pts.
If set, enables serial line interrupts.

~~~~;:a~~ on Icac::::::::·n::e)

Preliminary Edition-September 1994 5-21

Table 5-5 (Cont.) lbox Control and Status Register Fields
Name

Extent

Type

Description

FBT

<35>

RW,O

FBD

<36>

RW,O

If set, forces }?ad !cache tag pari~y~'.'.~~~~Qi.tkh:-:-.'.'.Jl:h
normal opera~on.
,::::. :l~lllllt.
.. . ,,:,:::::\n::{~~~::::~llll:::i~t.
If set, forces bad Icache data pijri~y. MBZ in
. \1\.

Reserved
ISTA

<37>
<38>

RW,1
RO

TST

<39>

RW,O

.·:·.·..

5-22 Preliminary Edition-September 1994

-:::::::::::::.

;,,:::::;~. Ml!l!A~:~'l'fy{{ftt{1b
t$ff
:~~~t~r:rf!"!AlJ!:bitus.
Writing a 1 to this bit ass~fl.s the.:fi~-~st_status_
h <1> signal. _,J:~~:~~:~~~~l~~~:tk:::,.. '::llj\~tt~f~l:lr

5.1.18

Preliminary Edition-September 1994 5-23

5.1.19

!::~~~~
~a~:l~!e:~!!s!: is written by hardware with the tarl\
interrupt priority level of the highest priority pending interrupt.
har<h!.@re
1

T.b.~

recognizes an interrupt if the IPL being read is greater than thEkJPilmwut:~!h,
IPL<04:00>.
.At=:l!!!!l!!::::
··.··=:====\:\g~~~\\~~:::I~~1!ll::k~==·
Interrupt service routines may use the value of this register WtQi~~rmine the \Ml
cause of the interrupt. PALcode, for the interrupt service,_mµst eH~;r~ that the-=tlf
IPL level in INTID is greater than the IPL level speci~.tdBhYl\\ltw IPfi~gister. . . .
This restriction is required because a level-sensitive ~4.fttwa~i\~~~~p-µpt may
disappear before the interrupt service routine is enter@l==(p~~ivE?lfftl~ise).
The contents of INTID are not correct on a H~1\m~~~ji.[be~~l~e this
particular interrupt does not have a target IPI4.JtF~whi~Ji if\~tiWb:~ masked.
When a HALT interrupt occurs, INTID indi~Ws the··==rt~J1ighest priority
pending interrupt. PALcode for int~rrµpt sef:W~~ must cHi~k the interrupt
summary register (JSR) to determine=q=f ~=JIALT~~\iP.~rrupt has occurred.
Figure 5-18 shows the INTID register fofiUM~. ..,,\~fl~t:==·=··
Figure 5-18
31

05 04

W-03490-TIO

5-24 Preliminary Edition-September 1994

5.1.20 Asynchronous System Trap Request Register (ASTRR).Jl\.
ASTRR is a read/write register containing bits to request asynchronJqj~::.~ystem
trap (AST) interrupts in each of the four processor modes (U,S,,~,.~). In\ljf.per to
generate an AST interrupt, the corresponding enable bit in th~:::~Tl!t@y§,t be
set and the current processor mode given in the PS<04:03> :il.i:ould..'fi~q~~q\ts.}to
or higher than the mode associated with the AST request~~EK~re 5-19 sii"<Nt~:,:

·:·:·:·:·:·:·::·::·:.t:~::j::.:.:::_::~_.:_:_.:_:,.:::_:·:·:·_:·::.':·.:·:·.:·:·

the ASTRR format.

-: : l l ~l: : :

.·::·::·::·:~·:~·:~· ~ ~....
f~~~~\~{~~):: . .

Figure 5-19 Asynchronous System Trap Reque~IJ=legi@~t::(~_ST.RR)

tlll:::)

/~l li!: :~r 0Jl·'~~:::~:1 oo

I : : : : : : : : : : :H+~i1: ::i1l:(~~::::::~;t~rmf1~t;'1

m~g

_1+J:J;: ;:~ !1r~ ;,~ : : : : : : : :

1·: : : : : : : : : : : : :

l\j,;:::::::{tt'.Jir ~w

:321
l.J-03491-TIO

Preliminary Edition-September 1994 5-25

5.1.21 Asynchronous System Trap Enable Register (ASTER)
.,f\.
ASTER is a read/write register containing bits to enable corresponding. : ~ ~ :~ ~ j[ \.

asynchronous system trap (AST) interrupt requests. Figure 5-20 §.lw.ws tht[l~t:.

&jf<Niffftq~il;,\,

ASTER format.

Figure 5-20 Asynchronous System Trap Enable Register (ASDifl)

,)~J~M:¥h. ~':=~~:ij~:g~[lt\..

~
1 : : : : : : : : : : : : : :

++Gr :<!i!l~i~: ~l lt:, :. :·.,,,,,:t!!i f:tt;,,,,. : : : : : : 1
-.::;:(j[~[[~~:j~l~[ll~:t~:· ·.

5-26 Preliminary Edition-September 1994

W-03492-TIO

·\lih

·:t~]W

5.1.22

~=::er!~:::~e~:~~:dR=~~:~~:l

(!:1w'! e inter upt req~,~~-

A software request for a particular IPL may be requested by s.~t.ting ttlfk.
appropriate bit in SIRR<15:01>. Figure 5-21 and Table 5-6J;l~§$~b.!tlb.~t$JRR

: : :5-21 Software Interrupt Request Register

19 18
1
( : : : : rHN: : : : : 1 : : : : :
i63: : : : : : : : : : : : :

(Slf!f!;t~l~!\];;b,, "lm!ffft,,
11 1

:,~,~,~! ~ :2 ~'.'.i,tr; :IG~

:'!~ :1,t,~ }%: ~-:!t!~,:' '~i';' :: ::

·'·' '"""'·· •;q~t{ft$\lt+·;qv

Table 5--6
Name

Sottware

lnterr11P.t,:::;;~U1ter Fields
.·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·..

:321

Ll-0,.,... TIO

····:·:··

Extent

·lnijthest software interrupts.

Preliminary Edition-September 1994 5-27

5.1.23

::::~~~!e:r~:::e~:!~~;t~~:e:e:!::~nsitive hard~\_

interrupt requests. Figure 5-22 and Table 5-7 describe the HWl1'f.f._CLI{\l\.

Al)*Wf~tt.;tffill\\t,
\1\

Figure 5-22 Hardware Interrupt Clear (HWINT_CLR) Reglstetttt\..

·.·.·.·.·.·.· .·.=_·.=·.?t~ ~t~ ~-~.~.~.:~: .: ,: ~

.,..:::::;:::::..
.At)F~:t~~{I~:\=:·.

31 30 29 2a 21 2s

............

·(~ ~ ~/

.: : :· .: .':·:':.· :..·_"".:._:.: :"·

HNlllll,I::::::::::: :+: :0~i;E:!,::;t~::]J1ft: I~~

Tmle H

Haro~~•lm~4!~;;::;:::
··:·:·:·:·:-:··

·-:·:·:·:·:·:·:·:·.

PCOC
PClC
PC2C
CRDC
SLC

5-28 Preliminary Edition-September 1994

··:·:·

u .•

;~,.

1
24
S. . ~~:~:~~!~o:;::s::~::~:~ormation about pendin;jltdware,
all

software, and asynchronous system trap (AST) interrupt reque~t.~. FigijJf~. 5-23
and Table 5-8 describe the ISR format.
.,:?ttttLt:,:,.,..... ·\~fi\.

'qHlTu\i\ft:1!

Figure 5-23 Interrupt summary Register (ISR)
04

31 30 29 28 27 26 25 24 23 22 21 20 19 18
RAZ

oa,:<~tI!~~o\.

SISR<15:1>

CRD
SU
HLT
W-03496-TIO

Preliminary Edition-September 1994 5-29

Table 5-8 Interrupt Summary Register Fields
Name

Type

Extent

ASTRR<3:0> <03:00>
and
ASTER<3:0>
SISR<15:1> <18:04>

ATR

Enabled AST requests 3 througJ1·=til~Y.lit.E,~)l::@.

IPL 2
RO,O

<19>

lffir '""Wt\\Wk&:l\\1

~:!:;:n!-:I~rr~~Lei~:=o~:Rtj\:~

Set if any AST reqm~~ll:1Htt~~kr~s~~H'1g

==etobi.!/b;~:'·t~\~::~

120

<20>

121

<21>

122

<22>

123

<23>

PCO

<27>

PCl

<28>

PC2

<29>

PFL

<30>

:::o~~:!~

Eltemal·===Hlflw~re inte~~t at IPL 23

E~tetimtJ1~dW~~::Jnterrupt-perform~ce

l.iil:~~~terrupt-perfonnance

. /~{f@Jf;:xtemal··~ware interrupt-performance

. j~~~j~p=::·:·:·:,::t~,~~r 2 (IPL 29)

<ltl>

RO/tit.
Exmfjaj. hardware interrupt-power failure
·.·.:=:tf l jf~ j [lh: : :. (IPL 80.)""

MCK

<31~\\~[+4~~-ilifh,''<l\t:'r(~M~~)are interrupt-system machine

CRD

<32>

SLI
HLT

5-30

External hard'Y.~ iriten&.Pt at Jf:L 20

··::\tnBO ··:·:=:t:tt::.. Correctable ECC errors (IPL 31)

;j~aw,1~~;1%1i;''W' ::a:,::;;=::nterrupt-halt

Preliminary Edition-September 1994

·=:; 1 1 1 1 ~jf
.

5.1.25

=~:~~;a::~::: ~~~~~M:!d :e;~~:it bit-serial

data o!lt the

microprocessor chip under the control of a software timing loop:~-:-. .'.fhe ~}:µ.e
of the TMT bit is tr_ansmitted off chip on the srom_clk_h s~m#i1ftntJM~.fm.@.l
operation mode <not in debug mode), the srom_clk_h signal:l~ overtHil~~W.tQd
serves both the serfal line transmission and the Icache serifilKROM interfafiili\.
Figure 5-24 and Table 5-9 describe the SL_XMIT register""fJfm.a.t.
J::::::::

.-.-::::::~?f\::=:..

-.·.::<~(t::::::::::~::·

·<:~/·

::gum s-24 serial une Transmit tsL_xM1~,,::r:,!~Jfm};

I : : : : : : : : : : :+: :,: ::,~1!*''.';~t,t1\~tJ:T ~': H: : I
0

:.:··:~.~:[:i~: : [: :.~: : :_:~:_._.~_.:
I : : : : : : : : : : : : :,~ifii•,;,_ :,,,_,%: : : : : : : : : : : I
·\(}

Table
Name

5-9

.·:-:.... . ·.·.···.·.·:_:.. ...

-tt;::::tt::::..

Serim~1ne J:~~~:!::lds
··:·:·:·:·:·:··

··:·:·:·:·:·:·:·:·.

J;~tefit .::::::\::'
:·. Typili~::::::..
-:-:-:-:-:-.
··:·:·:·:·:·:·:·:·.
....:·:·:·:·:·:·:·.

:_ :_ :_ ._.:.·_-:·.:_:·:_.:·_.: ·.:.: : _.:_.:_:.: .

TMT

-.:::::·

W-03497-TIO

··:·:··

Description

Preliminary Edition-September 1994 5-31

5.1.26

:e!!::r

1
=~:~vl:~~
r~::!:
r~:~te~~s~
bit-serial data under th~ -fwo1
of a software timing loop. The RCV bit in the SL_RCV register is
fuµction~]ly

connected to the srom_data_h signal. A serial line interrupt i~d:~~ti4!:~~~t.'.'.\~lh
whenever a transition is detected on the srom_data_h signal al.if the ·s'EEllfl\iFL.
in the ICSR is set. During normal operations (not in test mot{ij~:~ithe srom_ .·-·-:·:::l[tt
data_h signal is overloaded and serves both the serial line rec~pfi~n and the )Ifj
Icache serial ROM (SROM) interface. Figure 5-25 and 'rab.W.A$-16"''8'-kt.ibe the-'?~?'

(V]''''}f)\~q;;;

SL_RCV register format.

Figure 5-25 Serial Line Receive (SL_RCV) Register ·::::::=-:
31

Jtf

·.: _,:.,~_~:;,·_-~_,:.,~_,~.[i~i i:lm··:-::::I,1,.os
ti:[ji lt: ;._ \i~ill!iittrf
o!r·:··-·· [iJ?

I : : : : : : : : : : : :+::'j1! ,~;,,,:''~til1:~"": :'tt;r : H : : I
·::·::·::.~:~-j:j·l:j: i·;.!'.flfJ.:.:~,.-:~:~ : _: _: :·:::'.:({tr

.,d[;~Jrtrtt;,_,,,.,__
.·.···-·.·.·.. ._·..

RC V

__.':_:':',-._:.-'-•:._,_.

....-.....

I : : : : : : : : : : : : '.f¥tti~: :-,~;11 : : : : : : : : : : I

Table s-10 Se~;~:!~~!,~:~;~~s
·-:-:-:-:-:-:-:-:·.

RCV

<06>

.·.-:::::::::::::::::::::::::·.·.

····:-:-:-:-:·:·:·.

···:·:·:·:-:-:-:

.., \~.:_,_,._;,:.: ,·=. =,-.'.__::','.,--.,......\%?Serial line receive data

5-32 Preliminary Edftion-September 1994

LJ-03498-TIO

5.1.27

::~~::~:a;::t::~:=~~!o~:~::!::

three on-chip pe~Lce

counters. Figure 5-26 and Table 5-11 describe the PMCTR fi.~;r:µiat...\\\lt.
Performance counter interrupt requests are summarized in S..e&tiiht~h:l.:24b
Cbox inputs to the counter select options are described in 't$.ble 5~=:fiflf{l\1\\\.
Section 2.8 describes the performance measurement suppQtt!)\f~atures.
····:·::::\It.
~~~~~~~~~~~~

.· : : ~ ~ l:tj\ \ \ \ i:i: : ~ : : : .
-: ~; :1 1 ~\ \:
Note ~~~---···:-::::~:-:::8-:::·..--~...-...,._,_,~~-

The arrangement of the select option tables is .:#~t~:::::lttt.9 i;~i; any
restrictions on permitted combinations of sele~t.~pns.~~frfhe::~if.tj;tcases
in which the selection for one counter influenc~s· adi.ther'.sfcount is
SEL1=8 (SEL 2=2, 3, other).
,J\ j jl\!) \) ~l\l) ) )\ \)j\ \ \lt: : . l\\~ll~\\t\{l]\\rr

Figure 5-26

Pertonnance eou~i!; ~:~\J~.::;rw
sm!&~:~*)t'\~,,~:~~l~g oa

313029
K

04 03

CTR<13:0>

/::ljj~~rt~:n\tr:\. .

'--~~~~~~~~-.;,;,;,---~~~~~~~~~~~~~~~~~SELO

163: : : : :

,~,,~,1fi,: ;!t:*'.i~1?1' : : : : : :++++ :::::321
'Wiltfj~~i\jl/;

MA-0601

Preliminary Edition-September 1994 5-33

Table 5-11 Performance Counter Register Fields
Name

Extent

lYpe

CTR0<15:0>

<63:48>

CTR1<15:0>

<47:32>

SELO

<31>

<30>

RW
RW
RW

CTR2<13:0>

<29:16>

CTLO<l:O>

<15:14>

RW,O

CTLl<l:O>

CTL2<1:0>

Kp
Kk

5-34 Preliminary Edition-September 1994

Description

Table 5-12 shows the PMCTR counter select options.
Table 5-12 PMCTR Counter Select Options
CounterO

Counter1

SEL0<0>

SEL1<3:0>

O:Cycles

Ox2: PC-mispredicts

Ox3: BR-mispredicts

Ox4: lcache/RFB misses
Ox5: ITB misses
Ox6: Dcache LD misses
OxC: stores issued

Ox7: DTB misses

OxD: Icache issued

Ox8: LDs merged in MAF
(continued on next page)

Preliminary Edition-September 1994 5-35

Table 5-12 (Cont.) PMCTR Counter Select Options
CounterO

Counter1

Counter2

SELO<O>

SEL1<3:0>

SEL2<3:0>

OxE: Dcache accesses

Table 5-13
Measurement Mode Desired
0
1
0

0
0

1
1

. }W.. this·Tj"~ce, Kk ~~~~-·kill kernel only. The combination Ku=l, Kp=l, and Kk=l is used to

4'-t:::;.~·:~:::d~~em:::;Y;;~ c~ mtle PAL subroume

. ,.,'\{Iku~.~lls that put the machine in PALmode. The "OS only," "user only,"
. ,,,,:q~4.. "executive and supervisor only" modes do not measure the events
cHifing the PAL subroutine calls made by the OS or user. The "OS +

5-36 Preliminary Edition-September 1994

PAL" and "user + PAL" modes should be used carefully. "OS + f.4.L"
mode measures the events during the PAL calls made by the usin\
whereas "user + PAL" mode measures the events during the PAL··:ciUs
made by the OS.
./lt~t:::::::·:·.. ·\~~[h:
1

.fai1

%@l!';!ff

".!!{jftti\t111;¥

:~:._.:_:_:~_:·~_ .:~.:~:~.~

t·;::;·'i.:[·l:. . . . .

::._:i._.::
__

Preliminary Edition-September 1994 5-37

2
S.

M:~x~:~~:~:ro~~:::~:~:: (~~~ !r~~:~b~~=:ection ;~fti
through Section 5.2.23.

./:lt:::::::::·=····

·:=t]llh.

Traps are factored into Mbox IPRN:re operations unles:t'::~Z'll\Wr''.;
otherwise.

.·:=~ : :il l~1l l:l lt1t t: :. · : \~:r~ ~j ~jlj tmt=·

5.2.1

LJ-03499-TIO

5-38 Preliminary Edition-September 1994

5.2.2 Dstream Translation Buffer Current Mode (DTB_CM) Reg:t§~er
DTB_CM is a write-only register that must be written with an exact:~~ijbplicate
of the Ibox processor status (PS) register CM field. These bitsjpdicate~~~~tb.e
current mode of the machine as described in the Alpha Archit.ftfi4.f:l{B.f#f.~t~lJ:Ce

::::::gu::::s:::::o:~~~:~~:r?;i~~~~~~~::~tj
163: : : : : : : : : : : : :

:,;~1 :, : {~~':::1,(~~tt1~:~*~ljT~l H g~~
321

I : : : : : : : : : : : : : : :11~7:1~~" :~'~1+, : : : : : : : : : I
W-03500-TIO

Preliminary Edition-September 1994 5-39

the
;:s:::~::h:::-:A:::s:r:e::::~the DTB_TA(}'te 0;:::~:: ttn
::~T~:~:~::0:1:~:~!~a~~~T~:~:::d con~
of the DTB_P'I'E register to the DTB. To ensure the integrity of
..

5.2.3 0

tlv~ PTBs%l~L.

the DTB's PTE array is updated simultaneously from the inter~4J'.'~:fiijtD.uET~~:~:~~h,

by a not-last-used replacement algorithm implemented in..b..3rdwdii~t:A.. write <if:
operation to the DTB_TAG register increments the traq~t.)litijl!J>uffef.~jj~r-f;B)
....
entry pointer of the DTB, which allows writing the en.d.fe se~~~~ilt»T.B.J?TE and
TAG entries. The TB entry pointer is initialized to en~ z~:fqtan:~\~ft*.~fTB valid
bits are cleared on chip reset but not on timeout reset:::::l•'igqre ~I~ shows the

::~:~gi:::::nslmion ~WJer Taitt!:~~!\)=~;::~
91

''t

;1it~: %i~Wt;it;>

I : : : : : : : :+++: ::~t~iijt-wi~~~tf\' : : : H: : : : I

IM: :::::

f1m}}::w

:,~ ~ ~;: :; %:u':'t~ I~: ::Y+H :: :~I

·_., ._,_,~.,_1 1 1 ,l;i@~;~ ;-j ; .

··=·=·=·=·=·="·....

5-40 Preliminary Edition-September 1994

LJ-03501-TIO

5.2.4 Dstream Translation Buffer Page Table Entry (DTB_PTE)-:::fl.egister

DTB_PTE is a read/write register representing the 64-entry DTB ~dML.
table entries (Pl'Es). The entry to be written is chosen by a ngt::last-li~jq
replacement algorithm implemented in hardware. Write ope:tciUa.n$:4~t_''.\\lL
DTB_PTE use the memory format bit positions as describe4.I~h thE{Aipl.@.\]\]\\.
Architecture Reference Manual with the exception that so$.~\]lields are igfiof.~4~
In particular, the page frame number (PFN) valid bit is noE=iwre.d in the nT.B.~:

To ensure the integrity of the DTB, the PTE is actu,a.JJy[\[Wtit~~~:::f&[\\j3.4~empor:;;
register and not transferred to the DTB until the QWB_TAQ\[\Jf:~gi~.tel is written.
As a result, writing the DTB_PTE and then readi@.g::wi-~buf=®.Mntervening
DTB_TAG write operation does not return the datEl?pr!jiousljJwritten to the
DTB_PTE register.
.:/:[[\):\1[\\\\\\l\[\l)::\... \\t:[\\t:J\]\\}f
Read operations of the DTB_PTE requir~. i."70 instf.ij~t.:jpns. First, a read
from the DTB_PTE sends the P.fE.:. data:=:ij.f\ibe DTB~J*tE_TEMP register. A
zero value is returned to the inte:g~r . wgist~W\i.l~ (IRF) on a DT:B_Pl'E read
operation. A second instruction readi:Wg4';rom. :'lh~fP.~B_PTE_TEMP register
returns the PTE entry to the refil§.t~r fiU~W\tR~adHig. the DTB_PTE register
increments the TB entry point~f\\\iftib.g,._DTBf\y;pich allows reading the entire
set of DTB PTE entries. Figuil/5-acfiij9W!3 thE DTB_PTE register format.

4h;/titecuA:!~3~::l
~~~:;::~~m[[[[[[\\\\\:::::.:·:·::tfj\][[:t:\[\\:\\:t:::,..

The Alpha
fields of

provides descriptions of the

·.·

Preliminary Edition-September 1994 5-41

Figure 5-30 Dstream Translation Buffer Page Table Entry (DTB_PTE) Reglster:/\Write
·:·.·..

31
IGN

:'H+'--__,::"*j~~-~;;;;;_;~~~J!:.~M:=:·. ·-::;:::=-::::::;:::=::
,:::::::::=·
liN':·:··

.___~-..,;,;-':',;,;,;.::::;::_·_··::~Gifii~~~(»

.::~:::;r

/{:f:;:::::;:{:~:\::::..

,:;:::::;:::·

··-:::::::::::::::::,..

-~·

: : :··::;:::::::;::::::::::::::::··sRE
: : : : . . . . . . .::jli~~

URE

.·: : :. .
·<\~i!i!i!iL
··==t=tj;!ii~!h==·
KWE
.____,.,~.\~::~~,~,-----=-.;;,;,;,;,;;;;,..----~--EWE
.____...,..._.._ ____,,~;.,-------SWE

'-----~·:=~~=«~··,-----~-----UWE

+-"~~*~1~;~:;::~1:;:, ::::

(3: H:ST: : : : : : : : : :

:32I

dtflr11~41%;_::.~4tt;r

<%;1'1\;t .:~t.~:~:t.:·:~:

tit\;t,,
.
'''+Zl\tt"i\\;;

<:~ I: : i'

4tC-,,\\\;r¥

5-42 Preliminary Edition-September 1994

..:·=....: _:_.:.__: _..=:_.:·.·.:.::.

W-03502-TIO

5.2.5 Dstream Translation Buffer Page Table Entry Temporary.{\\\.
. :\~1h,

(DTB_PTE_TEMP) Register

DTB_P'l'E_TEMP is a read-only holding register used for DTB...J~T.~ d~ii.l~\.Read
operations of the DTB_P'rE require two instructions to return'.'.Hfi.]Rf:E.Jl.i'u.t
to the register file. The first r~ads the DTB_P'I'E register .W~~\Jhe DTB:Pf:B.ft:.
TEMP register and returns zero to the register file. The -Sj.¢,{iQ.d returns th&}\.
DTB_P'I'E_TEMP register to the integer register file (IRF). ··Pih~ 5-31 sho.wi~~

Figure~: :~:::.:t~::::~:::: Ent~ll'~=~TE_T~:P)
Table

13 12

affei\iit~:sotL~~t

.::::::::::··

··::::::::::::::::::..

. ....

PFN<39:13>

LJ-03503· TIO

Preliminary Edition-September 1994 5-43

5.2.6 Dstream Memory Management Fault Status {MM_STAT) Reg:l§~er

•.

MM_STAT is a read-only register that stores information on Dstream f~dl
and Dcache parity errors. The VA, VA_FORM, and MM_STAT regj$_t.ers afij~~~h.
locked against further updates until software reads the VA regi§t.~Wlmt\~k:::.:·:'.'.:~~l!j!jl!jL
MM_STAT bits are only modified by hardware when the registef!!I~~ noffo'&liQi]!!!L.
and a memory management error, DTB miss, or Dcache paritjf~b-or occurs. ····:·:=til~k.
The MM_STAT register is not unlocked or cleared on reset. Fiifitt:J~-32 and . '.ttl~
Table 5-14 describe the MM_STAT register format.
...:/::ljJ\::.. ····::\{ll~l!l~~lii~i!l>
·:::::::=::::

::gura ~2 omraam ~o~7 :anageme:,::~:!l~Reglsmr
RAZ

<%t b, '''tll[{'\i;,-~.1.~,>

Ff~
~l&:~iss

'f"{fl\t\iJ&\!f

13: : : : : : : : : : : :

:Jw~ei::~i: ;~,:

::::::::1

Tab~ om~~~~~~~:: Fault &mus Reglmer Flel~m
5-14

5-44 Preliminary Edition-September 1994

Table 5-14 (Cont.) Dstream Memory Management Fault· Status ReQJ§ter
Fields
\~\\\j\j\\\\.
Name

Extent

Type

<10:06>

OPCODE

<16:11>

RO
RO

Description

Preliminary Edition-September 1994 5-45

5.2.7

F:~ :!:gr~~~~~ ~~~=~~:)n~:~!:~:ults, IYrB misses, or Dcaca~
1

parity errors occur the effective virtual address associated with thg_.fault, . tf[ih:.
miss, or error is latched in the VA register. The VA, VA_FORMt-JpUtf~-=::::J~RL
STAT registers are locked against further updates until softwar@)))teads. l1i~fi1f.i)!I\.
register. The VA register is not unlocked on reset. Figure 5--3.lii~~ibows the vK=·==tflt

'%"'~'%$,,

,1\,

Figure ~3 Faulting Virtual Address (VA) Register
31

W-03505-TIO

5-46 Preliminary Edition-September 1994

S.2.S F::~= a~:~~n:~~~:~~ ~:w:~::: ::~:i:ge table en,{PfE)

address calculated as a function of the faulting virtual address.::@d th~tiirtual
page table base (VA and MVPTBR registers). This is done a$.JitpijtfQrro~fft.e

~~t~;G~::~;:(~::;:~~: ;t;:~ ~~~~~1r~;;;1~11,
fault, DTB miss, or Dcache parity error. The VA, YAUlAlD.M, ari(it~_STAT.
registers are locked against further updates until_::ipftw8:dWig3.J~s. Jhe VA
register. The VA_FORM register is not unlocked di.fares.¢~/' Fimif:t/5-35 shows
the VA_FORM register format when MCSR<Ol> is·:::~ie<d'.f
.lf

Figure 5-34 Formatted Virtual Address

i3Tf9: :

(VA_FO~·"~!~·~\!tf~1)

:+: ::2T: : : : : : :,,;1~!t::~::!l:1;·":tt!TH\PTB<63:30>

W-03507-TIO

Figure 5-35

W-03506-TIO

Preliminary Edition-September 1994 5-47

Table 5-15 describes the VA_FORM register fields.
Table 5-15 Formatted Virtual Address Register Fields
Name

Extent

Type

VPTB

<63:33>

VA<42:13>

<32:03>

VPTB

<63:30>

~s:;.fl~'~Ci!Bt~ stored in

VA<31:13>

<21:03>

Su~t of thi~~§tiginal faulting virtual address

NT_Mode:O

NT_Mode:1

Preliminary Edition-September 1994

··:··

··::::::::::::::::..

5.2.9

W-03508-TIO

Preliminary Edition-September 1994 5-49

5.2.10

:•Y

~~:=~:;:
i~r:~:a:!':
r:~te:!~~~!!~
~:!~s~::che
error status. The VA, VA_FORM, and MM_STAT registers are
agaH{it..
locl~~d

further updates until software reads the VA register. If a Dcac~~t;filalit~ni.™l~t,
is detected while the Dcache parity error status register is unlqi)fed, ttrn:::::tWfflll\.
error status is loaded into DC_PERR_STAT<05:02>. The LO~~~§~t is set amf·::t::~lh.
the register is locked against further updates (except for the SE(Ub.it) until
. ll@:
software writes a 1 to clear the LOCK bit.
.AH:Jll:~t~~llt:::::,:.. ····::t\l)::::::...
·:q::::::'
The SEO bit is set when a Dcache parity error occurs .:While tb.i.ll[)k~~b~:ll~arity
error status register is locked. Once the SEO bit is s~j~jt ~~[Jhcii@.U~ainst
further updates until the software writes a 1 to DC_PER.Jt!STA'lti:OO> to
unlock and clear the bit. The SEO bit is not se~MWR!n. Pcaib!d~•f!fty errors are
detected on both pipes within the same cycle. :~Uf'tliiWjfi.artictiUlF.situation, the
pipeO/pipel Dcache parity error statq.~ bits irull~ate the::::~§tence of a second
parity error. The DC_PERR_STAT r~@ster fa:tttq\:::µnlockecf%r cleared on reset.
Figure 5-37 and Table 5-16 describe ~h~:l:Qgy~ftfis&T.AT register format.

::gum

H7 Dcache Parlt'.,,~;i(~i~~~:TA: ::~::

01 00

I::
W-03509-TIO

5-50 Preliminary Edition-September 1994

Table 5-16 Dcache Parity Error Status Register Fields
Name

Extent

WIC

SEO

WIC

LOCK

DPO
DPI

TPO
TPl

Type

<02>
<03>
<04>
<05>

RO
RO
RO
RO

Description

~;::;~2i~~:;q~~Att
'\ih

occurs within the same cy~lf(i.~. the first.
Set if parity error de~~W.d f~~~!l$~AAP.e. Bits ·(jjjjj~f
<05:02> are locked ,~jiij~::furthiHf\ijP.;4ates when
this bit is set. BitS]i205:02lilit~e cleared when the
LOCK bit is cle~!I;, .i\\ll~j~F"'''\11\\\\\\jj~\\H\\\j\}
Set on data parity':~rrc#Jn Dc@.he bank 0.
Set on dat~:1iift~y errJ~\jlnJlil~he bank 1.
Set on u@.jjlt~~~:lifmr.i~:=:s~;che bank o.
.d\§et orl$.ij~parity e~Jfljri Dcache bank 1.
··:::::::::··

·-··:::::::::::::::::..

Preliminary Edition-September 1994 5-51

5-52 Preliminary Edition-September 1994

5.2.13 Dstream Translation Buffer Invalidate Single (DTBIS) Rfl:D..~ster
DTBIS is a write-only register. Writing a virtual address to this reJi~t~.r
invalidates the DTB entry that meets either of the following CJ":it.~!ia: \{It.

~ ;~:=~:<~:::: :::::::::::::::if~~~~~\

==~: s:::::::::::re~:::uJt:'.:t.!~):;:l
31

<i1-l~~rrtttJ'-%~:101w

Regimer
00

: : : : : H42'+ :::v: 4/h~ ':'1J\\h:, : :·: :IGr : : : : : 1
111

H'*i1 1l'.t: ~~;:~~w~;::: :::+++: ::

(3: : : : : : : : :

,;_~:_:.j_,~.,~,~.'~.~:_.':., ,~:~,~.~,~.~.t!Itq;,f - - - - - - - - - - - -

W-03510-TIO

4lt
;:}~::::::..
·

4lf
<:j:;_i:_::.:::.:.::.=:.·...

.'.,'.·.:··'.·'··'·:·,_.'=_.':..'=

Note

The DTB~'~:;:fim§t;;~:!l;~:j;jWnt.~::r~efore the normal Ibox trap point. The
DTB invalidatit..pgJ.e o"{n~fation is aborted by the lbox only for the
followiqgJ~tillJ~pndittRilf?:

<tl~i:~i;,~R

DTBIS is exeruWd in wer mode

Preliminary Edition-September 1994 5-53

2 14
S. .
:::

~:~!:~_:~::~:t~!~!ntrols features and records statu:tJ&.,

the Mbox. This register is cleared on chip reset but not on timeout. reset.".'\lt:.

Figure 5--39 and Table 5-17 describe the MCSR format.
Figure 5-39 Mbox Control Register (MCSR)
a1

os os

t'il~, W;_~:_: ~,~-~.= ='~-.'~:= ._.= _.-' _.-' _

04~~m!~~g~~~~ibso.
@•'

.=.!=!_.:.·'·._. . ..-·:.·:__._. ... .= _.=::·_.·

.-'·.'_..:·,_ ·.-'·' ·

:+H ,;~w@~i1!;:~t~:.,wi;1 : : : : :321
+f,~,~:~_:.:ilt11"W&ft\;

t-b.

1'-WMi:}JAU:W~, ,t_=:=t.i,=~_=:· =~_=-~.:~_.:~·:~·_.=~_.:

' " ~' ,~'~'lJ::_ENDIAN
+)fJ' 4\{t;:~:::~ii;~~;:~;ii#~;"ij~~ENDIAN

RAVIGN

(3: : : : : : : : : : : : : :

4¥t\1- -~-~- ~-~:,·,~:'.:

"'W'!W,l\t;\\t·

't:t~:}Jl
<t\ tlt~ltqr,
··-:··

5-54 Preliminary Edition-September 1994

::=,·..-' :=.=..:=_..='_..:':·.,.·,.=:·

LJ-03511-TIO

Table 5-17 Mbox Control Register Fields
Name

Extent

M_BIG_
ENDIAN
SP<l:O>

<02:01>

Type

Description

RW,O

Mbox Big Endian mode enable. Wh~ri:~~¥.~tP.U. .i=:~~f%J:ie

RW,O

~~;;;e:;;;;.~:!t::::>

SP<l> enables superpag~:~miP~ltm)vh~ri'~V#<42:41> ~· 2.
In this mode, virtual ad~sses .Y~{'=@.,~.~9,?.' are mapped
directly to physical ad~!.~~s .:Jl.$<39~1:;}$/ Virtual
address bit VA<40> is igh:Oreqfiii thi~:#anslation.
SP<O> enables op~~t@9.µe sulro.~~lnapping of
Dstream virtuaJ.Jjndres~~t.:M.ilfV.A<42:30> = 1FFEJ6.
In this mode, xlf:tuaI addf.imw..s VA<29:13> are mapped
dire~~Y. to phjffl~l address~:J?A<29:13>, with bits
<39:.3US o:f phySii.it~ddress set to 0. SP<O> is the
NT ModEfbit. thafiWbsed to control virtual address
fomattinif'iih,~.,..read'''~t-ation from the VA_FORM

re~,~~f~h::::,.. ··::::~:~l~~~~ltt...

Reserved
E_BIG_
END IAN

<03>

RW,O

<04>

RW,O

Reserved

<05>

.,·

JJ;:~,~~;;;~::;!~!:e~~~he
.·:-.lF

MSK.l~fam..d INSxx byte instructions. This bit causes the
<tttL.shift amiiht to be inverted (ones-complemented) prior

4QbRW!&IJ!@:\ijf"~~~;::=~=~st zero (MBZ).
be

Preliminary Edition-September 1994 5-55

5.2.15

~~:=~~:~~e
~~i~'":e r~!!!8!~~::ntrols diagnostic and test mo,,in
the Dcache. This register is cleared on chip reset but not on
rese'f!N\\.
0

time~HJ.t

Figure 5-40 and Table 5-18 describe the DC_MODE register fo~pfitfiEHtt::::::;.;.:'.:fit:,

.&~If'

- - - - - - - - - - - Note

'"' .%%\t;}ff,

DC_ENA= 1
DC_FHIT = 0
DC_BAD_PARITY = 0
DC_PERR_DISABLE = 0

'%%\t1fp

,!Ir

Figure 5--40 Dcache Mode (DC_MODE)

Regltr&. <q\•{1,,{j~,

\%\!

I": : : : : : : : : : :

,j-,~~~::~\\tw,,

: ~'.'.~ 1~;~:1t~,f: :::::::::

'~~;t~!:::;

,;1C~~%\1;.

OC=PE~_DISAB~

:321
W-03512-TIO

"W'

5-56 Preliminary Edition-September 1994

Table 5-18 Dcache Mode Register Fields
Name

Extent

DC_ENA

Type

Description

RW,O

Software Dcache enable. The~!!D.e::::ENA::ht\,
enables the Dcache unless Ale. bljHi§!~\h~i.[\[\h.
been disabled in hardwar~{tbc_DOA ·i~t~Mt)th.
(The Dcache is enabled if::ti1:. ENA=l and Dtf\

~~~;~t::r~; ~~~i1:1~~E!11Jtj;:~:: 1fJ\[:
}fus~1:a:~~n(k8jj~6[!).~,~~;~i~:n~cache.

DC_FHIT

RW,O

DC_BAD_

RW,O

PARITY

Dcache force hif~j~jjjWl;@j?~t~·:'.li.~&:[:bC_FHIT
bit forces all Dstreamfrefereriees to hit in the
Dcache. J(-~~~ zer&\\b.}~~$iial operation.

, ~eJ:l~~w~}j~~ct! :::.'7~r

·.·

·?[} stores):~-~ has the effect of putting bad data
·-~Y i:ri'OOMb.~. Dcache on integer stores that
hl·KfttJpe Ik~h~· This bit has no effect on
...,.,.,.,.:.,. the taijjjp~rity "Written to the Dcache during

+mfl:*WSi!b~ °Ja~·b~n! ~!;~~re
..

st:r:::::::::ttl~\ Floatirig~point store instructions should not be

<\1\f.·

4;.ll'l&th~'~!~l~~:E~~~~~~~g:lt

gfgf:~- \#~-~::~\);f:''llfj ~~'.~f:~~~~@;~~J;
,.,. . •1~#::::,,f>.,

:~!~~~-set.

Must be zero (MBZJ in norm&

Preliminary Edition-September 1994 5-57

5.2.16

=-:~~::Sa ~!'.:!°:!ere~s~~!~~~ro~:~::stic

ni~

and test
in the Mbox miss address file (MAF). This register is cleared on cqjp_ resel~Ij~jj~\.
MAF_MODE<05> is also cleared on timeout reset. Figure 5-41 mjd?,:@Mt.Jtfl~,

,~,k

describe the MAF_MODE register fo::

' '<ti!:?@,!tl

The following bit settings are required for normal o~·· '""l\{{.}

~~:~;~2

c: .~:>1$t'

~c~~D~~~~==oo

<1tl%.~&\~fi

-=~.~~1~::~1\>

Figure 5-41 Miss Address Fiie Mode (MAF

·fu~lf\lWltfJm,;~~

02 01 oo

RAZ/IGN
DREAD NOMERGE
WB FLUSH ALWAYS
WB-NOMERGE
....__ _ 10 NMERGE
.....__ _ _ WB CNT DISABLE
._____ _ _ MAF ARB DISABLE
~---- DREAD_PENDING (Read-only)
.._____ _ _ _ _ WB_PENDING (Read-only)

W-03513-TIO

S-58 Preliminary Edition-September 1994

Table 5-19 Miss Address File Mode Register Fields
Name

Extent

Type

Description

DREAD_
NOMERGE

RW,O

WB_FLUSH_

RW,O

Miss address file (MAF) DREAD M~.r,:!r».~1~Jlfmien
set, this bit disables all merging in{fje DREA'flfjl§fiipn
of the MAF. Any load instructiono:::tbit is issued.\vnij.n\..
DREAD_NOMERGE is set is fo!i~i}!"P. allocate a ne~!I\
entry. Subsequent merging to thaf·eijlt-Y._is not allo~@:~:
(even if DREAD_NOMERGi.Hi~~::~leared)@Mµst be ze:NV
(MBZ) in normal operat~3i~f:::=:=:::::::~~'.llllll~~:It::::::.. ··==:\j:f>
When set, this bit force~@he wdtetb:U«~~tto flush

ALWAYS

WB_
NOMERGE

RW,O

<02>

IO_NMERGE

RW,O

;~~)~~ :~~:{~;~;~:~!,!j!fhtry::il!llFU~t be zero

When set, this m\lllffiltn~,~ aiflii~@hg in the write
buffer. Any stot~tinstnicij.§:~t.that is issued when WB_
NOf\WRGE ~::~A\ is force(fijk~llocate a new entry.
Subsijlnent ni:efdhg to that entry is not allowed (even
ifWB_:_NQ.MERGEd$:::deared). Must be zero (MBZ) in

=Jl!t~~;!~tsmerging
loads from YO space
in the MAF. Should
(afjjf.~sS:~Mk~39:>~l¥from

hE(jero (SBa}.Jn_ typfoal operation.

WB_CNT_
DISABLE

RW,O

<04>

·:{~l~\}·

MAF_ARB_
DISABLE

5
<0 >

if:li.~t.set, thl:~:Mt" disables the 64-cycle WB counter in
ilJl. at low. =p:ijgpcy only when a LDx_L instruction is issued
ff. the.'NtAF.. arbiter. The top entry of the WB arbitrates

····=?fJ\9r a secorid~WB entry is made. Must be zero (MBZ) in

-4tt~?:llrt;1;lf:~~i~r:S~!~1~:S:~!i:

;#}1\WL1'.IJ\lit? '"'1:~-!~i• ~,!,~\t:.i~~~=~:=.~!. and chip reset. Must
DREAD_
PENDING

<0$.i

. /}t;O -df\

\~1~== . ill'

\fkt:r==·

'tF

../If

··==t\ilit:nit~J~f='

R,O

Indicates the status of the MAF DREAD file. When set,
there are one or more outstanding DREAD requests
in the MAF file. When clear, there are no outstanding
DREAD requests.
This bit indicates the status of the MAF WB file. When
set, there are one or more outstanding WB requests in
the MAF file. When clear, there are no outstanding WB
requests.

Preliminary Edition-September 1994 5-59

5.2.17

5.2.18

W-03514-TIO

00
01
10
11

5-60 Preliminary Edition-September 1994

52 9
" "1

~~!ea~:::~c:~!=r~~::r1164 supports it as described in Ji~pha

Architecture Reference Manual. The low half of the counter, wh.~;n enal)l¢.d,
increments once each CPU cycle. The upper half of the CC :r:¢.'gisit.t:J:§,,,.t~~\
counter offset. A HW_MTPR writes CC<63:32>. Bits <31:QQ'W:·are wfofi-q_.
CC_CTL<32> is used to enable or disable the cycle counteii:JEJ1e CC<3l:009~J§:

:::

;::~~ :~~~~:~ ::~::~:i:::::n a~~i~;~:t.Wpha ili•

Architecture Reference Manual. The RPCC instru.~tfon r~t-~t.aJ>4~bit
value. The cycle counter is enabled to increment S:;:IY thf.~e ·cyr.~J~i'" after the
MTPR CC_CTL (with CC_CTL<32> set) instructioii<isJ!i~ued/itrhis means
that an RPCC instruction issued four cycle~AKtj~t_~ H}.¥Jif.PPR CC_CTL
instruction that enables the counter reads:~:ifV:aiii~~:~t]w..t ik"6he greater than the
initial count.
..J:Jmt
. \{]\,,:·:·.
The CC register is disabled on chi~' r.:~~-~;~:t;li•r~ 5-4;::::~~ows the CC register
format.
"\{@:::::::..
..,.'=ttl::\. .
·::::::~:~:tf:::::...

Figure 5-43

LJ-03515-TIO

Preliminary Edition-September 1994 5-61

2 20
S. .

~:~;:~n=te::~:~~~~;~~=~~!:~:: 32 bits of the cycle ~l..ter
to enable or disable the counter. Bits CC<31:04> are written with . :the vafilh.
8

~C~~3~~~,!!=~=n w:'~!!~!i~~s~~~~~ :: ~~t-Z~!t'-l\\~

CTL<32> is set then the counter is enabled, otherwise the co®.W.r is disabled~---::\~fit.
Figure 5--44
5--21
!?riri~\1{~,lf
1

::gu~

&44

and Table describe the CC_CTL register
Cycle Coumer Control (CC_CTL) ::~~:~t'~JW&i

JJ1

I : : : : : : : : : : : : :+H++ :_filt'':'7t'1~",;~vr :+:I
00

r: :::::::::::::;i ; ~ t~ : : : !~)i:
Tab~ 5-21 Cycle ~merJ:!~\~\~~·~:

5-62 Preliminary Edition-September 1994

';!(;;' : : : :

CC_ENA

L.J-03516-TIO

5.2.21

~~:;::r~~~ ~:~ :::::~(~~~!::d~:~~s::i:!e~sting,.
diagnostics. An address written to this register is used to inde~Jpto th~~lll~ache
array when reading or writing to the DC_TEST_TAG regist~rt==~F:·~L~~?.,
· and Table 5-22 describe the DC_TEST_CTL register format~lJSectfoti?5m2~$.~b.
· describes how this register is used.
<tt~lL
··.··=·==\\~\~}~,,

R~tlt:"1\l}\\tzft\]t
ill~,; "'~?·\~!)
I : : : : : : : : : H+: : : : : : I : : ::~~;:f~:{l:t~
Figure 5-45 Dcache Test Tag Control (DC_TEST_CTL)
31

<If

13 12

)tit
63

.·_=_=_=.~.~.-~.~.;_:~_:_i_i,l_l_•_•,_=~- = :r·==~·:=.:_=_.=_.= .=._.=_.=.=_.=~.=~.=~=~-*t1"
_

·(\~:::~lI>====··

. .=.=_..=·_·_•.:=.·=·.=·_.:_=

~E~t

I : : : : : : : : : : : : : : :+~1rf~h: -~%'1'1: : : : : : : I
1

Table &-22
Name

BANKO

D~~e Tes\' ~~-::~er
··:·:·:·:·:·:··

··:·:·:·:·:·:·:·:·.

··:·:·

W-03517-TIO

Fields

. :... Extenkt::==··
Ty~ill::::::,..
Description
··:·:-:-:·:·:·:·:·.
····:·:·:-:-:·:·:·.

-:·:·:·:·:·.

··=::{~00>.

··::::::::::ltw

''"''"' '+t{1~jf·

'\1\f\;f&l-¥

B~;) tt:;f

INDEXd2:3> ·\~l2~US>

'"WJ{t,ft!t\"

":='=t@:Dcache Banko enable. When set, reads from DC_
TEST_TAG return the tag from Dcache bankO,

RW
RW

E~~~J:~bw;~~~~h~~=o.

~~i;f!=:.!l~~=~l~sst~
Dcache tag index. This field is used on reads

':~~!"~c~~e~~:-TAG register to

f::.'x

··:·::::~

Preliminary Edition-September 1994 5-63

5.2.22

~~:=:r~;~~
~:~ !:~~~S:;~~~~~=~:::ively for testing an~\\.
diagnostics. When DC_TEST_TAG is read, the value in the DC_TEST_CT(it.

register is used to index into the Dcache. The value in the tag, ~~:pi!!W.:>.:::YJ.li.4
and data parity bits for that index are read out of the Dcache aftff Ioacii~fiiiMi1i\:.
the DC_TEST.;_TAG_TEMP register. A zero value is retumed:::fAi]pe integer ····=·==\Ii~L
register file (IRF). If BANKO is set, the read operation is from ·D$.tbe bankO. JtI

::;:~~;:;;~~::;~~~:,:: :~::h::::l~{.,,,.~,\!t!

written to the Dcache index referenced by the value itUjt}le_JjC_Tlif:JtcTL
register. The tag, tag parity, and valid bits are affecte&by,~jJis write operation.
Data parity bits are not affected by this write Qpjfi.tiw1 (ti~~JJQ$MODE<02>
and force hit modes). If BANKO is set, the WJilfop~ri;.1.9.Jl i·~=::i~fbcache bankO.
If BANKl is set, the write operation js to :O,~~~e bankT~{jJf:J>oth are set, both
banks are written.
·<{}· ::='.\=.·. ··=:t\jjiii~ilt:::::,:..
· ·=: ;: =
Figure 5-46 and Table 5-23 describe the==:q;~J_'ESTfilT.AP register format.

::gu~

µs

Dcache Te~ Ta:fil~;(~~~~;;~::er ro omo

i : : : : : : : :T~:i :t\(i\;~l:; ':'.'l'ir1 : : : N: : : i~TAG
1f

PARITY

1~: :::::1¥1;:~: : !;~;: ~ ~: :;-; : :~1~: +H+ :..Ig:~=~ t:g
1

:.: : :

"' · '11t::~tlf;;

<l\jl~\ ' *lti

5-64 Preliminary Edition-September 1994

LJ-03518-TIO

'<?

Table 5-23 Dcache Test Tag Register Fields
Name

Extent

Type

Description

TAG_

<02>

Tag parity. This bit refers to_.Jhi1tk~~h~==:~:.
parity bit that covers tag bi$\~~~8 throiii.lbt.~M\.

<11>

PARITY
OWO_VALID

::3!~:= ::~::r~~)~~\llrers to ::1i'Jll!!1

Dcache valid bit for the.Jow-otditNJCtaword -({f
within a Dcache 32,J.:ttiW~lw~k. "=:='\\l}t,.
. ,. .

OWl_VALID

<12>

TAG<38:13>

<38:13>

Octaword valid bilJ]i":". TIJi~\bibrefe~~/'~o the
Dcache valid bit ~~,,.th~::~'gh.~'ijfi.J.:f.::'0ctaword

~~~~·~=-~;;!the field in
tag

. ,,,._Note:.Jlj#~;39 is not"'s@:t~d in the array.

..:::::::::::::.

··::::::::::::::::::.

··::;::··

Preliminary Edition-September 1994 5-65

5.2.23 Dcache Test Tag Temporary (DC_TEST_TAG_TEMP) Regist•r

DC_TEST_TAG_TEMP is a read-only register used exclusively for testi~j!j!ip.d

~~::~: ~::h:::::a;::q:~:~;:;:;::::s:~:;l~~::~;~,ft,
parity bits and loads them into the DC_TEST_TAG_TEMP··:tilif~r. An
UNDEFINED value is returned to the integer regist.~.rdile.. (IRF)~{f}::·:·.

:e~:::~: ::::.:~r::;:e~~:~~?e-;!~~;fi~~~J-.tf1~ms

Figure 5-47 and Table 5-24 describe the DC_T:mS.T.~TAG....::6M6\~lf~gister
format.

.·.

At'VfKf4~Wsicy/£:~%fa'iff/

Figure 5-47 Dcache Test Tag Temporary (DQ!TEST.S~Af.t_TEMPfRegister
31

13 12

·-~-1 1=ijib:::..
~}~\g~~~5.:J)4
03 02 01 00
"'·:::::::::::::::·:·.
····:::::::::::::::::..

TAG<38:13>
TAG PARITY
....___ _ DATA PAR0<0>
....___ _ _ DATA-PAR0<1>
~---- DATA-PAR1<0>
....___ _ _ _ _ DATA-PAR1<1>
......_;;;,;;,;.---------- owo VALID

....___·.. ;. : :;:_
: _ _ _ _ _ _ _ owCVALID

163: : : : : : : : : :

::f;;~:~!=;~i,t;j :::::3T: H++:321

c;;~c~:(;; '''if'
4{'-lt:;1;1>

5-66 Preliminary Edition-September 1994

LJ-03519-TIO

. J~~l~
..\::::::

Table 5-24 Dcache Test Tag Temporary Register Fields
Name

Extent

TAG_PARITY

iype

Description

Tag parity. This bit refers to the D~Jb~111~~::'P.;ijty._

::;::~::::::::;c:::~,,\j

RO
DATA_PARO<l>

<04>

DATA_PARl<O>

DATA_PARl<l>

OWO_VALID

<11>

data parity bit that covers t!wJ.ower-:l&i.S.Word of dat~f/
indexed by DC_TEST_C~!ii2m~?.'.-~
""\fl~t:.
.
Data parity. This bit ref.~f~(~ ~i\~1ll-~~.9:::P~~che data
parity bit that covers tlifaµpp~fnon~~t~rof data

Dcache

~:xe;~~~:=:c:tkl
data parity bit tllff covt@::Jhe"lmver longword of data

indexed by DQ.Jt!EST_CTUii2.:.03>.
Data~~ljarity. ·:ilillki~ refers ·-:~ffhe Bankl Dcache data
parity.hiM~_at ciM~f'=:Jhe upper longword of data
indexed bY:=~QC;:;..TEST!.~<12:03>.

Octaw.c:m.d_ vJnflfit::O. This bit refers to the Dcache valid

OWl_VALID

<12>

TAG<38:13>

<38:13>
. :::·:·.

'tffRo

~·'t'f4\"~~~~word within

aDcache

32-byt.e

:dHP.&lbv.prd vali&=bit 1. This bit refers to the Dcache valid

f~1f. bit"tbf%b.~ high-order octaword within a Dcache 32-byte

t{(,;;:;:;;.

·t1l::::nt::::..

These bits refer to the tag field in the

··~AAb.~ array.

\l[:l l l: : :tl~t: : :. ····:::;~~1{::lllt~~~t:f1~Bit 39 is not stored in the array.

Preliminary Edition-September 1994 5-61

53
"

E:~~~2~~::rf::fi~:::~:I c~:~:~ =~:. Bcache, system ,,\

configuration, and logging error information. These IPRs cannot b.~t::rg~d \11]~~\.
or written from the system. They are placed in the 1 MB regiop}p/='211§1.~:t}~~~I:t.
specific 1/0. address space ranging from FF FFFO 0000 to FF :rn{PF FFFF~:-:;''Ati~Nlii\
read or write operation to an undefined IPR in this address sp•§t,,.produces
--=::::]~\
UNDEFINED behavior. The operating system should not ~~p arty~~1!\9.~ress in .JI:f

:: ~~::~:~:c:s:Yre:s:~s are described ht~~,,.~:!~

::::::· ~box lmernal Processor Reg~e"t.9Jt*?'tW'
9

:·:·:·:·:·

Address

SC_CTL
SC_STAT
SC_ADDR
BC_CONTROL

5-68 Preliminary Edition-September 1994

··:·:·:·:·:·:·:···.

Preliminary Edition-September 1994 5-69

Table &-26 Scache Control Register Fields
Field

SC_FHIT

Extent

Type

RW,O

SC_FLUSH
SC_TAG_
STAT<5:0>

5-70 Preliminary Edition-September 1994

Description

Table 5-26 (Cont.) Scache Control Register Fields
Field

Extent

fype

SC_FB_DP<3:0>

<11:08>

RW,O

Description

sr:~~:tif~~:ciii:t
Scache. If any one ottliii~t bi ts is set to
then the correspogwng foiitt~wrd's compU:!Wi

~~%e~alue :,;1f,,£;~~)\~ting

the '

~~:~!:l~T~:~

longw.ijl~~~f.fili~ biti~~i~tVM from the Mbox.
Thei.M.hre, ··tn~)~~me l6ngword parity control
bi~Jire used 'ffiih~r.iting both octawords .

.(jjjj~~~~'
SC_BLK_SIZE

must zero

FriWi~mple, Sd]~13_DP<0> corresponds to

~~· ~r!!~~eld

Tlll~~J~U. seleets the Scache and Bcache block
:/l~~~f:~\@~~h::.~ize tt(jilt:either 64 bytes or 32 bytes. The

<12>

RV'1.!::::::::::::::..

,{,;~(\!f.&i:~]i7i~1~:::~~;me,

-ilfi

<~!' . ' W{l'.W/ih.

. :,:q\~Lthis bit is set and the default block size

'i,~2~~~i: :i1::·i!!':.,~1~h~zd!red

'*·tt\\11,t,;~~*' ~gEEif~;.t~~E

This field is used to enable the Scache sets.
Only one or all three sets may be enabled
at a time. Enabling any combination of two
sets at a time results in UNPREDICTABLE
behavior.
··.·.··=·:·=·....<:18:16>

RW,O

Reserved to Digital. Must be zero (MBZ).

Preliminary Edition-September 1994 5-71

5-72 Preliminary Edition-September 1994

Table 5-27 Scache Status Register Fields
Field

Extent

Type

SC_TPERR<2:0>

<02:00>

SC_DPERR<7:0>

<10:03>

Description

When set, these bits ir.?..di~lt~~4b~t:::~#.t.
Scache tag lookup res:flted ·nfrf~ikiiti~Y
error and identify tb.~if~t that had. lhE(~~
parity error.
·\:{~lllljjjjjl~k::...
\'.l l l l [:
When set, the~J?.its indiiji.~. that an (ff
Scache read triinsrfotion resulted in a data

:~ ~~:1f:~~~l,,ili~!~~~n::~rd

<15:11>

SC_CMD<4:0>

parity erroHJTh~$.{bits:[[#.tPioaded if any
longword withinWwo oqtijwords read from
theJii.il~t.f:lurirlg\Jdjp had a data parity
eq.ijCit=SQiEJHT::=(SC~CTL<00>) is set,
tbli'. field hi"u$id.:Jor loading the longword
. : :.
.:::pifi:~y bits reacfijht from the Scache.
{::::::.
indicates the Scache transaction
··::t\ttb.~t retiil:k4 in a Scache tag or data
. :·:·::::'.·:·:::·:·t eriO'E This field is written at the
.Af}I}lt::::.. ~~~~-.actual Scache error bit is written .

R6~lJ
.·.·:-=·j\\lllt:··

TIJ~::~Sld

··:::::\\Il\\\\i;X:,c!\~:l,;c::~::%d1:!R~h~'

~:~l l\il lft~:~: :l\l\l [ l\}~: : : . =~8c'::i:a~~t~~~r:~~~d~r~~=r to

SC_SCND_ERR

'{1;

'i\\~:~-,\4:'t%{f; ~~~~g~~~~~i=cache

41' tit; W14~!.:_:.:_ :_~.::·

•.•:.:_:.:·.'•:·.:.:.· :...

·::tJ~:::~::::::::r:~::i::1:ltl·

:l l l l l: . :f~[jlllff"

=:_=·.:.=:·,l.li%;i'

:tr:an~s=a~ci~ti~o ~n:.a~Z~Z~:t~ ~ :, e

·=tlfa:,

\'~111;\lwtllfl*

if~1l\\~-;;)
h

··==t{?"

Preliminary Edition-September 1994 5-73

Table 5-28 SC_CMD Field Descriptions
SC CMD Source<15:14>

SC CMD Encodlng<13:11>

110

101
100

001
001
001
011

5-74 Preliminary Edition-September 1994

Description

·==t~~lh.

533
""

s~::D~~~~:~d~~!;;~~~=!. ~~~i:::leared

or unlocked J·~ The

by
address is loaded into this register every time the Scache is ac.~~.ssed itllb.:ve
of the error bits in the SC_STAT register is not set. If an S<;~~®l]\:ijgJ~x:)l~ta
parity error is detected, then this register is locked preventifig. furtn~f4il.mt~s.

::s:::~::e~d::::ti:::~::::e:~~~:A~a:o:::~~~\~ntify ~~·

address being driven to the Scache. Address bit <04.~J[jtiijb:tJfies ·whl.~lt octaword
was accessed first. For each Scache lookup, there .:ii/one ,~g\l1t~{!e.~.s··:,~d two
data access cycles. If there is a hit, two octaword~\j\ir.e r~~a oqf.\\!W~'.consecutive
CPU cycles. Tag parity error is detected only whiM:::'re~$.ng tb; first octaword.
However, data parity error can be detected . ,..ttfa~l.t.her d£\\fh~M4lo octawords.

~C;~;~:::: i;s

:a:r:r:::t mqde), J::::~l{~:,:: the

storing
Scache tag and status bits. For eiEh. ,~g iiFtlt~t~cache, there are unique valid,.
shared, and dirty bits for a 32-byte s'&•'.P.lw=k, ··autmodify bits for each octaword
(16 bytes). There is a single tag .~ml a l>lif!~yJ>it . f&f two consecutive 32-byte
subblocks. In force hit mode, qpjytf&"!W; aiia1\1b~pbes load tag and status into
the SC_ADDR register. In thi$.j\jiiode·:·:::Ei:g~~ppd
parity checking are disabled
and the SC_ADDR and SQ4§iAf... registefij1\j.re not locked on an error.

·aata

In force hit mode, to Wii~!!!lh~··::~~~l~~. and .read back the same block and
corresponding 4*:::statU:s{Jit~, a miiHiijum of 5-cycle spacing is required
between the Scacfie .write ··ati.utr.ead of the SC ADDR or SC STAT.
Figure 5-50 ':IA/!)1~i~t~-3.~ ~:~~\~tlbe the SC_~DR regis~ format.

¥t'e1\:\~-

C:(!~)

+$\$!®}

Preliminary Edition-September 1994 5-75

Flg~;m:e

2t!~t~J)t;:~\t,

Scache Address (SC_ADDR) Register

I::::::::::::fH+++ ::::::::&tt\•t»: :%~ \ ~l~ ~ l:~ [l,{,f**ltit1
[~ \~):\
-(l !l l!~li~
40::dlih:.

:. 32

I::::::::::::+:::::::: :1:H;~~~~~:1
~o:-

Hit Mode

15 14 13

1i{~~:Jiwl~~

00 RAZ

I::::: :i+++:::: ,~%:I 1~iH~;~;:+~ :+:I
3

i" : : : : : : : : : : :

+: ,~m~ ,~ :!t ~;:;:~l r 1:r: TtGrH :

W-03522-110

5-76 Preliminary Edition-September 1994

Table 5-29 Scache Address Register Fields
Name

Extent

Type

Description

<38:04>

Scache address.

Normal Mode

SC_ADDR<38:04>
Force Hit Mode

::: :~

::~:i.m:~:~1't1tr;,:+r
SubblockO ta.g·· sh#.~d biVJ

<06>

<07>

Vl
Sl

:::

:~ !i\ft !£~ ::::s:~t.

MO
Ml
TAG<38:15>

Suhj1,kd\\i:~~:~iij\~f:!j~l\\jj\l~F

:~:;1> :~ %f~~t!'! ~~:·
.-:-:::::::::::::::::..

····:·:·:·:·:-:·:·..

subblockO.

<14,13> RdfF?\~Jf\Oc~W6fas modified for subblockl.
<38:15> ;:::::::ii::·:·
··:::::{~&~ ·:~.

Preliminary Edition-September 1994 5-77

&-78 Preliminary Edition-September 1994

Table 5-30 Bcache Control Register Fields
Field

Extent

BC_ENABLED

Type

Description

wo,o

:i;~
::·B=~~.!1=~~$~
disabled, the BIU does not
extemafMfol!ij:\
p~r(qffe.n

\f\.

read or write transactions. ·===:tffk.

When set, the issue uni~A!~s ~~~~j~~l~~ate a
-{i! !i!ijl~:
cycle for noncacheable Jilltqi~-~-- Wh&i@l~ar, the ··
instruction issue unW@r0caqm~:~:::9ycle
returning
noncacheable fill daufato be Mittetkto:~the Dcache. In
~!~::rc~~~,d~:.cle i~:[~flwj,~==anjii~f for cacheable

wo,o

ALLOC_CYC

for

Note: This 9.iilllM$.!:::~ ci~it.n'J;e reading any
Cbox IPR. lt]~an oo··==sijJkw.:hen>reading all other IPRs
and noncaiili&ible LDsY=l%::::::,.

wo,o

EI_CMD_GRP2.

-J.ltn .-~~:-===tfii~~~ponal c~!~ands, LOCK and
SET DIRTY ar~tffi!i:ven to the 21164 external
interra:~Mf©.mmaria::~mns to be acknowledged by
~mt~~tenf:1ij!!ef.ace~·=· When clear, the SET DIRTY
_jjjfu. . .d is ri"&i]~fiven to the command pins. It is
'lUNPRED.IC.TABLE if the LOCK command is driven
.::::ftlbP. the piriMflJ.owever, the system should never

<03> w2Jl '"~'X~~ :'!=:::::::i:c~~:~1164
1

EI_CMD_GRP3

·:{l\\\\}·
)ljjt\:=:::..

CORR_FILL_DAT

··=·==:'l{\\jj\\j\~~ll[l::~~~~i1;!;::-~~~~:~~~~l~:r~t~~~o;ledged

·=fl\j\\ljt~h-. _ ··=·=\h,_mand is not driven to the command pins.

<0491t_1,1\:~\lit11'~::~~~r~::;::~~r;:~~n

f;;?:;~•;''t~1;
~g~~~g~1g~~
1
~(,\ti\\t
trap is taken.

(continued on next page)

Preliminary Edition-September 1994 5-79

Table 5-30 (Cont.) Bcache Control Register Fields

Field

Extent

VTM_FffiST

Type

W0,1

Description

~~~:it~:~E!~E~~?!li:.~,

~~~~~i~:~~=tc~:~. i•
out the read miss followeg/jy . thEflfi~tim address and

El_ECC_OR_

W0,1

PARITY
BC_FHIT

BC_TAG_
STAT<4:0>

:::::the

genL~l"e'll~uadword

21164
ECC on the data c4.~._pins. When _gjiar, the 21164
generates or exp.~lf.@~~J:>ytEf~~§t.:'bn the data
check pins.
,:,. ~jjjjjjj?
····====~H\\j[[j\j\}:}. · ·=·=·=·=·=· ·

wo,o

Bcac~~:::force htUIWhen set;·'iijJ the Bcache is
enabfodf alJ refeNit®~ in cached space are forced
to hit in the.:::Bcacilifb\.. FILL to the Scache is
forced to ~===~ijy~te. ·SJliware should turn off BC_
CONT&QL<029l~t~}low . blean to private transitions
wit~,tri@mt~ "t'fii[[!1stem.
Foifwnte tiaijj~:tions, the values of tag status and
. Jili.~Y. ~its arEt~fied by the BC_TAG_STAT field.
fIBca~h,i.lJ,~.g and index are the address received by
/:}fl the BlU#Tb~ Bcache tag RAMs are written with the
·={\[j[(
·==:::q\\\\\b~:pdress rrtH~jjis the Bcache index. This bit must be
..:/\,....
···===t@P-. during normal operation.
<12:0l~)::::,. wcVl!\lt::,. . Tltl~~j\j§tt;,field is used only in BC_FHIT=l mode to

··::::::t\[j\[l[[[jj\\l1t::,.. ··::::::~lt:[g~~a~~~~~b~:~~~~t s:!u~a~!a~~~s

~~~~~:)~t\1=~~~~E;t~;:§!~=~~)

+1~Jtlt~l {jf'

5-80 Preliminary Edition-September 1994

Table 5-30 (Cont.) Bcache Control Register Fields
Field

Extent

Type

Description

Bcache Tag Status
Bit

BC_TAG_STAT<4>

1?:4#.tt~:for 1iJ$j~4ag

::~:::~:::::: C~l~i~!}:~

·:'\?'

smtus

BC_TAG_ST4.W~iW:t~:::::;. BJiJ.~j~~ijF~hared bit

BC_TAG_~!:44<o;:·::::w~~~~~lm~h;:::~~ dirty bit
BC_BAD_DAT

<14:13>

wo,o

El_DIS_ERR

Preliminary Edition-September 1994 5-81

Table 5-30 (Cont.) Bcache Control Register Fields
Fie Id

Extent

Type

Description

BC_WAVE<l:O>

<18:17>

wo,o

~:::.;~~;~'!,;~~:~~IL'!!~k

E!:~r=~~:!:::~f:~:'(l;

should be set to the late~d:~~~~6f;\U!:::P.caclfi;;@~k=·
read. BC CONTROL<18.~11> sMlD~khe set··=·'
to the n~ber of cycles 'U~ubt;ri¥t.."liP.itBC_
CONFIG<07:04> to obtaif.tl;fh~:;~Deach~mfepetition
rate. For example,j[QC_CO:tf.fJG<9J~4>=7 and
BC_CONTROL<~@l1$.i~.it t4.i~J@.ven cycles for
valid data to
at tn~fintenaMrpins, but a new
read ~11 start'-;f.'ry five ~~I~~'=··
The
re~tlli~:::r.ate mu~t::lk greater than
3. For ·ex~JipJe, iFnfnQ~ permitted to set BC_
CONFIG<07l'-4>.=5 ari.6dlC_CONTROL<18:17>=2.
The .v.~ht~. ~r .ijdl\lo~rrltoL<Is:11> should be

ar:nv.e··

::1;:~~Qli~~~:~it:~! ~~acf~F!!~ 4 :l 2>

. :&d~tions. ··=T;~::prevents a write transaction from
jfst1ri'tij.gJ>efore the last data of a read transaction is
. ::,. tt.receiv~dN\::.
<24:19> <f}vo,o :t;:tjjj[!lllWb..e bi~·:·~~:l~ifus field are used for selecting the BIU
·.· . /\:·.·.
··=:p~eters to be driven to the two performance

PM_MUX_
SEL<5:0>

<2S>

'{\-l\\~:fifitenr::;~n the lbox. Refer ro Table 5-31

Reserved
FLUSH_SC_VTM

<26?.:ftltttW.O:&ri~th:::,::. Fl~sh Scache victim buffer. For systems without

:t~ltl l !: r= · · · · : :; ; ;il !l l~lf:·./1; =: ··:·::::t;;:~h:c::~iri;~:i~hibu~!:~rcJ:~:1: ~!:b!~~h:Y

tl l! l l~lt/[~j~ j[ [~j~ [}. .Jltl l l~l

.;f// "<lt&t;tt\1W'

411,~~%\i

WO,O

:~!1I1t~m!~~=fy ~~~:~t;;,:~:%~!i~~: ~!tim
buffer as needed.

~:~::=~pa:~:·;!f~:at:~s!o~~uebeof
(continued on next page)

5-82 Preliminary Edition-September 1994

Table 5-30 (Cont.) Bcache Control Register Fields
Field

Extent

Type

Dl_S_SYS_PAR

<28>

wo,o

Description

Table 5-31 describes the PM_MUX_SEL fields.
Table 5-31 PM_MUX_SEL Register Fields
PM_MUX_SEL<21 :19>

Counter 1

OxO
Oxl
Ox2
Ox3
Ox4
Ox5
Ox6
Ox7

OxO
Oxl
Ox2
Ox3
Ox4

··:=::::fr~::::..

"::O:\j)\::·:·.

·.·.·.·.·.·.·.·.·.

··:·::=:====::::=:·

..:::::::~~~_he misses

··:·::\{~::t~:tt::. s~~::-read misses
·-::\fScache write misses
··::~~tche shared write operations
Scache write operations
Bcache misses
System invalidate operations
System read requests

Preliminary Edition-September 1994 5-83

Preliminary Edition-September 1994

Table !>-32 Bcache Configuration Register Fields
Field

Extent

Type

BC_SIZE<2:0>

<02:00>

W0,1

Description

(continued on next page)

Preliminary Edition-September 1994 5-85

Table 5-32 (Cont.) Bcache Configuration Register Fields
Field

Extent

Type

BC_WR_SPD<3:0>

<11:08>

W0,4

BC_RD_WR_

<14:12>

W0,7

SPC<2:0>

Reserved

5-86 Preliminary Edition-September 1994

Description

Table 5-32 (Cont.) Bcache Configuration Register Fields
Field

Extent

Type

FILL_WE_
OFFSET<2:0>

<18:16>

W0,1

<~!:~~~\.

Description

Reserved
BC_WE_CTL<8:0>

At power-up, all bits in this field are
cleared.
<63:29>

Ignored.

Preliminary Edition-September 1994 5-87

5.3.6

e::::G~~=:~::a!~~;::!~:.D~n~!s~:~!=~~e BC_TAG_Ati\.

register is loaded with the results of every Bcache tag read. Wheq:J!.. tag d~i\.
tag control parity error occurs, this register is locked against fu~:itfbd@t~~f\
Software may read this register by using the 21164-specific 1/0 !ilface adttf.i$.iHl\.
instruction. This register is unlocked whenever the EI_STAT<f.~~ter is read~···:·::\J:t:
or the user enters BC_FHIT mode. It is not unlocked by reset. ··::::~=\~l~~l\k::::..
.Jl~l\

.·.-: : : ~ ~;t~t: :~:-.

. Jlf:::::::::::tl\h::::.

- - - - - - - - - - - - Note

· · : : ~1t~ -~-~_;.~_: ~-~:_:~:..~·:·_.::'_:·_.:.·_.:·:.·.:· .:.: .

The correct address is not loaded into BC_TAG_JLR w!l::::!l~~ifity
error is detected when servicing a system comman(ffrtjpf the J)'cache .
..::::~~~~~~tt~~t~::::..

~=~@t~~~::::::·:·::::t@~1~f

Unused bits the TAG field ofby"'tb!s
rewJ":r~'~'i.;:::, based on the
tn=e
tag
in
size of the Bcache as determined
~C_Sf0.li.Jield of the BC_CONTROL
register. Figure 5-53 and Table 5-33 de~ttiP.e tiUflQQ....TAG_ADDR register

·:.·: ·:·:·:·.~.:l : :~:.~l.~:.: : :.: _:

format.

·.·.·.·.·.· .·:·:·:·:·:·:. . ·.·.·.·.· ·.
,:/~]1[%\:ft:::::::.

:._.:.·:·.::tq}:·

::_:=...::_.:: .::_
__..:::·_:·_:··.. .:__ :____

Figure 5-53 Bcache Tag Address (BC_TAQ~ADDR}~::@~glster

201e. 1a 111~~t::~,,-\A '\W{;,,.

..:::::::=:·.

··::::;::::::::::::::..

··=:~::::::::::::·

TAG<38:20>

39 38

W-03526-TIO

5-88 Preliminary Edition-September 1994

·=:{f:::

Table 5-33 Bcache Tag Address Register Fields
Field

Extent

Type

Description

HIT

<12>

TAGCTL_P

<13>

TAGCTL_D
TAGCTL_S
TAGCTL_V
TAG_P
BC_TAG<38:20>

<14>
<15>
<16>
<17>
<38:20>

RO
RO
RO
RO
RO

If set, Bcache access r~~tilW44RJ~ .FU!Jn
the Bcache· .
.. :\~jjjjj}· .··--=·::::::::::::::~:{lj~~~~~j\jjjjjjj~jj\\~\.
Value of the· pari ty.Jij#f.9r the Bcache ··um\.
status bi ts.
····::::::::::~~j\jlltt:::..
_Jjjljjjjlj:
Value of the :Qg@.b~:. TAff=di@yJ>it.
· =: : : :=·

Value of th~::s~=:~li:~~tlTA.G sh:f~:a bit.
Value of th@j~bcacli~FTAftjjWJi"d bit.
Value ..9.f .th~::ji~:ji~rlty_,l.~['. .·
Bc~l::::~::bjts :j([jfjja:::trom the Bcache.
Utiu~d bibfa'r.e. read as zero.
.::::.. ::::::::.
··::::::::::::::::::...

.{\~~J:::

Preliminary Edition-September 1994 5-89

5.3.7

~:;:
~:~::::~:!~':!!~li:~~i== access of this regis!iL
unlocks and clears it. A read access of EI_STAT also unlocks the

~LAIJf.fq~:L.

BC_TAG, and FILL_SYN registers subject to some restrictions. XJi&~::sJtS~~t:

:~:~srr:: :::::::::::r::::s::~ld have correctabfJ'i{or ""'~%\\ffi\\\

uncorrectable (u) errors in ECC mode. In parity mode, fil.L~ta ·p=iqgr::._ errors <IlF
are treated as uncorrectable hard errors. System addr~~W.:00.mmancfpijtj:ty
··
errors are always treated as uncorrectable hard error.i~fJhesdii.Uv~. of the
mode. The sequence for reading, unlocking, and cleadfig EJ§\DQIJIP:C_TAG,
FILL_SYN, and EI_STAT is as follows:
·: : : :· Jif
.Jf
1. Read EI_ADDR, BC_TAG, and FILL_SYN iJ.~Jllyjl[~tg.e;~l[~~j~--l~\f~ot unlock or

::;;~;:~ster. Reading't\li s r~~Lµn1::!!\tADnR,

2. : :
BC_TAG,
and FILL_SYN°registers. EI_STAT i$l::~l~o Uril~k~d and cleared when read,
subject to conditions described in TabrnN~tta.4. ·.:,:\{[~[[?·
Loading and locking rules for ext~malfffmt.~~=d~::!~s~rs are defined in

Table

5-34.

,),Ctt%~,.;:m_t!!_::!!~~:_~~t_)·_··:-::::. _ _ _ _ _ _ __

If the first error:4~tcorreetib.J.~, the rejj:Sters are loaded but not locked.

On the seconc;l coti-e~t~J>le·.·~r,,. registers are neither loaded nor locked.
Registers ar~l~ll~~k~ctalt!!llt.lw fi:;=~t~!!Wicorrectable error except the
second hard ert8fl[lP.it. Thill[)t.f;ond. hard error bit is set only for an
uncorrectable errot::f.q}b?.:~ecftiy:· an uncorrectable error. If a correctable
error follow§t~#.f.{Q;QJ!ortiij~t!P.le error, it is not logged as a second error.
Bcache t~Hiarityijh-9.rs "d'h uncorrectable in this context.
~~tJ
. ::::i~J~f:· ·t~t\

5-90 Preliminary Edition-September 1994

Table 5-34 Loading and Locking Rules for External Interface Registers
Load
Register

Correctable
Error

Uncorrectable Second Hard
Error
Error

Nat possible

Not possible

Yes

-{\ljl:h.

Lock
Register

1 These are special cases. It is possible that when El..:;.;t\DDR ~~bi~~, only th:::~~ctable error bit is set and
the registers are not locked. By the time El_STAT iit~ad, an ffii~tr.ectable errot· is detected and the registers
are loaded !!gain and locked. The value ofEl_ADDR ..rea<l::~arlier==jjj(ij.Q.Jonger valid. Therefore, for the (1,1,x)
case, when EI_STAT is read correctable, the error bit is cl~d and==tij~i!\rogisters are not unlocked or cleared.
Software must reexecute the IPR read sequence. On the ~~~::.read Cfp@~tion, error bits are in (0,1,x) state,
all the related IPRs are unlocked, and EI_STAT is cl~.~f.~d. ···==:ttt=:·.
· ·====·
.::::f}~:;:;{:~====·:·.

··=:::~:~:r~=~====··

r~,::l;t~·:::d

The EI_STAT register is a
to control external interface
registers. Figure 5-54 an~i.NbtiH~::::-35 desctibe the EI_STAT register format.

313029 28 27

'~\,;.:.'.·:·=·:.i.=81:.=·.=·.=:=·=;:·.~=·:==~·=:=~.=.f=·=:·:.~.;~ ?\ti

23f{~\ltt{1tL

Figure 5-54 External.

.=··=·.=··=·=·.=·. .='..-·.=.=;_.·.=·:. .=...=-.:·.=::·.=.:.·.=. . .

Reglmer

· === \l:.:=:=_=:.=:=..=:=.=:.= .-=·.=·.-= ·.=.=.=:- ~·~o

..·.·=·=·=·=·:. . . .

.·==::~~~·~~~~~~~=~:=:~;~~~~m=~1~~~=: =:·•
....._~.=:;;;:::::,...r_--.;·;;,;·{'""g_:::-·-;··,...=··--·-·=:=·_·- - - - - - - - - - - - - - - - C H I P 10<3:0>
=

L---~~~~~~=~~~---,;,··~::::::~~~-=··~·}:~:t~:~~~~~~~~~~~~~~~~~~BC TPERR
'--~~-,-~~·:::~;::~:~---&.. ~%~::}_·~~·~~=~~==~~~~~~~~~~~~~~~~~~BC-TC PERR

...._-~--."~{=;;;=~··-=~=t~:{m~~;;;~:~r=--~==:~t:-==------------------~---EIES

.___~~~~~=:~~:~~="~-··~~~:~~:~:::::~:
...,...,.,,.,~.~A~:~~=~/~~~~-~~~~~~~~~~-~~c6R_ECC_ERR

·::~:::~:~~~~~tI~ ~~~~~ =~:::·.

36 35 34 33 32

111

UNC_ECC_ERR
El PAR ERR
FIL IRD~--- SEO_HRD_ERR
Ll-03524-TIO

Preliminary Edition-September 1994 5-91

Table 5-35 El_STAT Register Fields
Field

Extent

Type

CHIP_ID<3:0>

<27:24> RO

BC_TPERR

<28>

BC_TC_PERR

<29>

El_ES

<30>

Description

" "
..
{:::::::::.. ..•
~::::::~:}:::
Read as 2. Future update revisions to_:J:fi.e.{¢mJbWJ.l1~:f~:\
return new unique values.
.. )j[ji[!j[?" ··.-·:·:::::::::t~@)lt~l~[jj[i[[!i[[[[lk.
Indicates that a Bcache read transa~itibLencountered ··.-·::=tt\

~~~~~~~~b~ ,,
~~;~:r;!; !.'3'!!Cf!f~~~~ache.
UNC_ECQ_ERR,A)'dEI_PAR_ElU't~ set.

This bit ·'i[A10~. d~~fi~l:~{~r a B~~h~ tag error
(BC_TPERRH§\t~. Bca1~h:i.tW.£ control parity error
COR_ECC_ERR

<31>

UNC_ECC_ERR

<32>

<ll>

~~~~::~~~::!•hU:~[~~it indicates that a fill data

~~:&r~\~~'Q'CPU contained a correctable
Utli6i+~le Ecc-=·ert-or.

This bit indicates that

.nlfdata . fi&i:v.ed from outside the CPU contained

4lmh:incorre~ti$.~. ECC error. In the parity mode, it
fo$.~~s data Jfarity error.

El_PAR_ERR

<33>{!ltJW ·:f~[~~~ltJ~~x~@..:4pterface command/address parity error. This
··:::::qf\::::..
·.·.:\]}~;Jndicites that an address and command received by

FIL_IRD

<34>

;~l{it{}\)l;:"fi'.::~==:;~hen one of the ECC or

tljfil'm:~jft',$~''!;!==:;;,:YJ~::r~tt~~!~eg::~
ib \fll•tt\:~<@\f,'. ~~:i~o!/:lina:1c~~ ~B::,1~;':rror

@;'~'iig,
t\c::::,:;;;

SEO HdbR

~~;;=n~~ !~ai~~!':;. 1:::!n::

:~:Z~F~::! ~t~~~~uE~~~~~=

5-92 Preliminary Edition-September 1994

5.3.8

addres *}Liated

~:::~~::~:C:o~:~::::~~~~~c~::~=~i=::ical
with errors reported by the EI_STAT register. Its content is m.~,@ingf&l~~P..P.ly

when one of the error bits is set. A read of EI_STAT unlock$,.,tlii~~~~BbAPQB
register. Figure 5--55 shows the EI_ADDR register format. lIF . . .,.,,,,:t::t~lt~l~E\.

Figure 5-55 External Interface Address (El_ADDR) R11gi:!1ttL

:1t:"~~,~-ft;~tt
:4~¥~,;·: (t\.:..;mtf I :+: I
00

I : : : : : : : : : : f1H+{4~
63

"'ill

&•c

<~l' "ttt~.;8"'

Preliminary Edition-September 1994 5-93

5.3.9

F~~~~:o:~ ~=-~~~;!":~1:::::~ It is loaded but not locked on',&,

correctable ECC error, so that another correctable error does not re.l.Qad it~?Jtjs

l~aded and locked if an uncorrectable ECC error or parity error J§'.:~Mm,im~-~:~l~[[:h

during a FILL from Bcache or main memory as shown in Tabl~!))~4. ···11n~@fl!!llh.
FILL_SYN register is unlocked when the EI_STAT register is:It~ad. This
··.··:·:=tf~[L.

;;:~:1~~~: :l;~~dm~d:e:: an ECC error is rec~~:}\~e fin't'

transaction, the syndrome bits associated with the bad]iiiad~Pfg)lre.Jdaded in
the FILL_SYN register. ·FILL_SYN<07 :00> contains t\i~t sY!i!lio~j~[[~sociated
with the lower quadword of the octaword. FILL_SYN.21"5:~ coq~s the
syndrome associated with the higher quadwor4Jt.fl[th~:-.~cta'.\f.~qd~X. syndrome
value of 0 means that no errors where found ijf[the···HIQ~at~lfl}tiadword.
If the 21164 is in parity mode and 8::::1?:@,rity -ell~, is rec::d~M during a cache
fill transaction, the FILL_SYN regisWt ~!lQicaUijbvbich of the bytes in the
octaword has bad parity. FILL_SYNDRONIJ£s07:-0o$.ti§. set appropriately to
indicate the bytes within the lower qµ3~woHIJ~tb.~t w~fe corrupted. Likewise,
FILL_SYN<15:08> is set to indicatf[~~tHi{\:AArruli~d>ytes within the upper
quadword. Figure 5-56 shows theJflLL.:S¥N:::.regiUer format.

lt\i~:Jc. 4'1~~'.l~~:::~-1i[{t"\ ¢;'
'''lltt4\Wt\~;~\\zy,

(~(?::;

4\l~~1tt;w.

5-94 Preliminary Edition-September 1994

::gure 5-56

Fill Syndrome (FILL_:~:) Register

,,~~iio
08 07

I :·: : : : : Hz: : : : : : : I : : H+: :I :.f1~~~.tY11~l\1,
t3: : : : : : : : : : : : : : : H: : : :

~zl;Ji:i,1t:~:1 ~;f~1~ :

321_,_;i!

:~ ~!l l: : : : : ~ : : [:~ : : :· · : : ;l l l : :~ : ~: f:L-oas21-T10
Table 5-36 lists the syndromes associated w\U:\:J~9rrectiij!~ ~.i#.gle-bit errors.
Table 5-36 Syndromes for Slngl!!-Blt
.·:·:·:·.·.

Data Bit

~WWW!JJt,\B,l;~,:~4.t!fNV
···:·:·:·:·:·:·:·:·:·.

····:-:·:·:··

Syndrome1s

01
02
04

08
10
20
40
80

(continued on next page)

Preliminary Edition-September 1994 5-95

Table 5-36 (Cont.) Syndromes for Single-Bit Errors
Data Bit

Syndrome1s

18
19
20
21
22

13
15
16
19

24
25
26
27
28
29
30
31

E3
E5
E6
E9

Check Bit

Syndrome1s

EA
EC

Fl
F4
4F

(continued on next page)

5-96 Preliminary Edition-September 1994

Table 5-36 (Cont.) Syndromes for Single-Bit Errors
Data Bit

Syndrome1a

47
48
49

53
54

98
9B

<I):· ::e. .

Check Bit

Syndrome16

SF
SA

Preliminary Edition-September 1994 5-97

5-98 Preliminary Edition-September 1994

5.5 Restrictions
The following sections list all known register access restrictions.

Condition
Store to SC_CTL, BC_CONTROL, BC_
CONFIG except if no bit is changed other

Must be pr~~e<kb§ Ma~~~:ffifi~t be followed
by MB, musfhaij(no cQ#.~urrent cacheable

i~~~~a~~;,<;·~c_ ::Jf''l~~~\\twficurrent system
Store to BC_CONTROL that only .{tb
M-mw.J~e precede·<rby MB and must be
changes bits BC_CONTROL<ALLOc::·· .:::t:::.. folloW4.\:J~y MB.

~~~~:~~~~cl:~~~~~=\~~~i;l:i,DR

and SC STAT.

:de:I:~:::~~- Jt~''ltti;::::~~~!:~~rST~, F~L_SYN,
Any undefined C~JPR adctfi~.

Scache or Bc8:~ht~·~:·f~i~l~~~·-~&-m~k::::::..

··::\~:fNo store instructions.

No STx_C to cacheable space.
Must be followed by MB, read operation
of SC_STAT, then MB prior to subsequent
store.
Must be followed by MB, read operation
of EI_STAT, then MB prior to subsequent
store.

. ::::::Jtr

··::::~~:~~~~llltrtttll~?..

BC_CONTROL<Ol> (ALLOC_CYCLE)
must be clear.

'*'1111,\1~\,(;!f;

··:·::::~

Preliminary Edition-September 1994 5-99

Y if checked

by Pvc1

The following in cycle 0:

CALL_PAL entry
PALshadow write instruction
HW_LD, lock bit set

~~~~~~!'!~·;,,
No other Mbo~:-::\f.1ction ..itili~t~~\..
No other virtuiltife.rence in O. ··:::\?.

HW_LD, VPrE bit set

y
y

·.·

No Mbox .d[~~j~j~~iffw_MFPR in 0.
JN.9 HW_Mmm. MAF_M01):$.~:in 1,2 (DREAD_PENDING
·-:~y n,_ot be\ipij~~d).
· ::;::
..:::.,.. No JUY~)fFPR':J)C.A:.f.ERR_STAT in 1,2.
\{:\J,'fo HWtMf..PR DOl1$.ST_TAG slotted in o.
···:::{It~l:aw33$.}{D.C_;~~-STAT in 1,2.
N({Q:;:J.AFP'l'.f~_MODE in 1,2 (WB_PENDING may

Any load instruction

Any store instruction

. ::::::~:tltt\!.. ~(;:~';t::~). · :·: ·

y
y
y

y
y

Any virtual Mbox instructio~l?::····· ··.·.,.f(:ij]JW_M~ DTBIS in 1.

Any Mbox instruction or

if it traps
Any Ibox trap

wi~, . :/-~·R ~y lbox IPR not aborted in 0, 1 (except that
\~~::11::~~)~~~~:~~~J~•:J~~l~a!~~ =~~1:~,i~ulting PC).

exce@J~ ''~tWjiii\if~ DTBIS not aborted in 0,1.

~;~\;f\j) ~~':'o~

_REl_BTALL in an aligned block of four

(continued on next page)

5-100 Preliminary Edition-September 1994

Table 5-38 (Cont.) PAL Restrictions Table
The following in cycle 0:

Restrictions (Note: Numbers refer to cycle number).~\::::::·:·.·..

v]i::c.hecked
bf~ffl(p 1

HW_MTPR any undefined IPR
number
ARITH trap entry
Machine check trap entry
HW_MTPR any lbox IPR
(including PALtemp registers)
HW_MTPR ASTRR, ASTER
HW_MTPR SIRR
HW_MTPR EXC_ADDR
HW_MTPRIC_FLUSH_CTL
HW_MTPR ICSR: HWE

HW_MTPR ICSR: FPE
HW_MTPR ICSR: SPE, FMS

y
y

HW_MTPR ICSR: SPE
y

y
y

(continued on next page)

Preliminary Edition-September 1994 5-101

Table 5-38 (Cont.) PAL Restrictions Table
The following in cycle 0:

Restrictions (Note: Numbers refer to cycle number):

HW_MTPR CC, CC_CTL

No RPCC in 0,1,2.
No HW_REI in 0,1.

HW_MTPR DC_FLUSH

No Mbox instructions in 1,2.
No outstanding fills in 0.
No HW_REI in 0,1.

HW_MTPR DC_MODE

No Mbox instructions in 1,2,3,4.
No HW_MFPR DC_MODE in 1,2.
No outstanding fills in 0.
No HW_REI in 0,1,2,3.
No HW_REl_STALL in 0,1.

HW_MTPR DC_PERR_STAT

y if ~hicked
/::::::=:=~.Y. PVC1f:~h,

··

::~~D~~~t;\;\\tt>.

No HW MFPR DC_WT_TAh:~j(j~b 3.
···==t@ft
No HW=MFPR DC_TEST..;:.Q'.fL is.siimi.::9.r slotted in 1,2.
No outstanding DC fills ~~~:M~jl:t:=:·. ··=:=::{tjj~~:l:::::=·
No HW MFPR DC TEST TAG4~tl 2 3. · ·==:.

HW_MTPR DC_TEST_CTL
HW_MTPR DC_TEST_TAG
HW_MTPR DTB_ASN
HW_MTPR DTB_CM, ALT_
MODE
HW_MTPR DTB_PI'E

:~ ~Jfl't;:°kf.._l11~~i1t

y
y

No virtual Mbox]:nitructions in. 1=:2-.
No HW_REfji(o,i?t~U:::::::::..
'

N~ virtual:~:&x inst~:d~~fuNn 2.

y
y

·==m=·nw_MTPftD.TB_ASN,"f)TB_CM, ALT_MODE, MCSR,
.·===·:·. MAFi"-ODE, .b¢.JMODE, DC_PERR_STAT, DC_TEST_

Y
y

?tt~~mg;_L,··nQt~:~T_TA~~~p- 2 .
HW_MTPR DTB_TAG

. . N:ihirtual Q~jnstructions in 1,2,3.
No===iUtJ.dTPR=::nT:B_TAG in 1.

;1,tf\11iilim~ t.1,2.

HW_MTPR DTBIAP, DTBLVl

/~]'io viijfb.il Mbox instructions in 1,2,3.
0

'~11•iiE !~~: ~~~.-

No Mbox instructions in 1,2,3.
No WMB in 1,2,3.
No HW_MFPR MAF_MODE in 1,2.
No HW_REI in 0,1,2.

y
y
y
y

y
y
y

(continued on next page)

5-102 Preliminary Edition-September 1994

Table 5-38 (Cont.) PAL Restrictions Table
Wi:~Qheckect
1

The following in cycle 0:

Restrictions (Note: Numbers refer to cycle number>.fa::::::=:·:·.·. _ bf:6Jp

HW_MTPR MCSR

;~ifi[M~~ :2~~~·2,3,4. t\{l(~;:::tfrf11~111~\)

HW_MTPR MVPI'BR
HW_MFPR ITB_PI'E
HW_MFPR DC_TEST_TAG

HW_MFPR DTB_PTE

:: :==:~~-=~·in 1.i·~;lfl~,\-ltk ,::\]}~
S:1:::!~:::~1tll~:_·1',;a,J;w
No HW_MTPR DC_TEST....cttt betwe~if$.w_MFPR DC_
TEST TAG and.HW MFPlt~DC TEST TAGtTEMP.
No ~ox inst~~i~n~Jp o·:=i:~:tj:~::~t:k.,.. ··~
No HW MTPR DC TEST:. CTL~-=nc\TEST TAG in 0,1.

m:=-~'~or
No virtual M]Wx insiffi@.ly.ps in 0;1,2.

HW_MFPRVA

Must be . . •J.::~

sloto d in

y
y
y

ARmi·::::ltcHINE CHECK DTBMISS

SINGI.$.fUNAQQN., DFAULT traps and ITBMISS flow after ..taij: VPTE fo~.dL:=:·.
::~:~:~:~=~=~=~=~:~:.

·.-.::::~:}~:~::::.:·.

Preliminary Edition-September 1994 5-103

Privileged Architecture uttl@cy cO~I
.·:'::tlth::==··

····::\~ii~~iil~ii~~J::·

This chapter describes the privileged archi1::i~.1~de
flt

·::tr'

21164

(PALcode). The chapter is organized as follows:

: ::::e:::~:=ent

qbt

· : : :·

i~f

4®'~::::.::.:.l'fq;)i,J,fl

: ::::~:~:;:::i:~~~~urruly reseNed opcodes

PA~:~:==,~~~;;~::e) is macrorode that provides~

architecturall)/=ttQ.i:rt~d 6{jibiting~:~ystem-specific programming interface that
is common acrositil{t\A.lpha?Qq~roprocessors. The actual implementation of
PALcode ditf.~!~tf9r eifo$.lii~p_erating system.
PALcode •=::·:·;;,1~~~j~ri~I!~l~s enabled, instruction stream mapping disabled,
and inter@.pt~::Jjf~fab1jp. PALcode has privilege to use five special opcodes that
allow/f.:µnclib.d~Vimchjij physical data stream. references and internal processor
re'1f (IPRU~a!P~jli.fiiation .

.·:ft@Ilt:fALcol!lJ!an be invoked by the following events:
System hardware exceptions (MCHK, ARITH)
Memory-management exceptions
• · :·::::' CALL_PAL instructions

Preliminary Edition-September 1994 6-1

PALcode has characteristics that make it appear to be a combination ~fi\
microcode, ROM BIOS, and system service routines, though the analogytiQ~}lllY
of these other items is not exact. PALcode exists for several major reasoriiHt:.
•

There are s~me necessary support functions that are too cow.~lltj~jjgb~t::::::::'.'.~!jl!l~jjj\.
implement directly in a processor chip's hardware, but th~V!ilnnofbettfil!!lt.
handled by normal operating system software routine. Riutines to fill th~\f~t
translation buffer (TB), acknowledge interrupts, and dispatMU..ceptions .-l~!f
are some examples. In some architectures, these fw}.~b.§. are·::h~gJed by ·::t?'
microcode, but the Alpha AXP architecture is care&iJHiot=~~finmandit~- the
use of microcode .so as to allow reasonable chip impl~mertiK6'h'-~=~@~:·

•

There are functions that must run atomically, yet .fR~oJflFionJ!l!t:~uences of
instructions that may need complete access.Jfij!fi.l!::tJle dQAt.tJJihg computer
hardware. An example of this is the sequ4.fi& ·tHiHtr~tUHii::trom an
exception or interrupt.
.{~ii~~k ·<~1l1~ !l!l l!liL.
· : : ~:~l1 ~l 1 1 jf
There are some instructions that ··are_:::n.~ces·safY:::for backward compatibility
or ease of programming; however, th'.~i~tQ;re ti&Mtm~d often enough to
dedicate them to hardware, or ar~L$..9 coffii.l~~ th.iifthey would jeopardize
the overall performance of the ,:®.iiP.it&.r. :F&f~~~ipmple, an instruction that
does a VAX style interlocked nt~mocy:::if.®.$.s :rriight be familiar to someone
used to programming on a..JJ,1$.S:::µiachin~~j~~fiut is not included in the Alpha
AXP architecture. Anoth~~¥xaffip}~L~S the emulation of an instruction that
has no direct hard.ware,:~ppport in. ::~:UJmrticular chip implementation.

In each of these ~a~:!i~i~:-1!.AL~~d~lj~~tiutines ··:~e used to provide the function. The
routines are nothing. moMUill~ i)f81rnms invoked at specified times, and read
in as !stream code::::bi@t.he sdhiibw.ay l1iat all other Alpha AXP code is read.
Once invoked, howe~~tHjl.~cc>"d®~j~bms in a special mode called PALmode.
1

6.2 PALmode E_njfi:f8:1~::: Rl~~~J~:- ·.-.,
PALcode
•

run'-111~ ~(jjf;i~ijj~nvironment called PALmode, defined as follows:

Istre. ~&-l~}!MJ~tl~ng is disabled. Because the PALcode is used to
imp:\!~fuent trAHiiitfon buffer fill routines, !stream mapping clearly cannot

At\¥l\}~\i~~;:e:vi~:;:d~~~:s:ti~ :~a::d~mputer hardware. Most of

.::dHP'

. ::ti.~ functionkhandled by PALcode are privileged and need control of the

-::::\liht:-. :::dilowest levels of the system.
· :t~ (~[~l\j l~il l ! '.'.:'.:· Interrupts are disabled. If a long sequence of instructions need to be
. ,.::\{j~j~~:J.:~cuted atomically, interrupts cannot be allowed.
·-:::\if~f:·

6-2 Preliminary Edition-September 1994

An important aspect of PALcode is that it uses normal Alpha AXP ilt.$..tructions
for most of its operations; that is, the same instruction set that nonpfiyi.leged
Alpha AXP programmers use. There are a few extra instructions thaFi.t~ only
available in PALmode, and will cause a dispatch to the OPCO.l.,kP.AUaa~.
entry point if attempted while not in PALmode. The Alpha 4¥.if::ifil\t~iW.~~
allows some flexibility in what these special PALmode in~trS.ttions do~····:·nrttt~:-.
21164 the special PALmode-only instructions perform the··=r&JlhWing functioniMfa

•

Read or write internal processor registers (HWJV!IRB.,. ~WlllTP.R).

•

Perform memory load or store operations

with:tff:::~~illtng:':-~4.;:~~:h:~rmal

·:trnir

• :::ry=:::::;:::::~:~~~=Jtt' .:lfllfF

When executing in PALmode, there are c~fifil~~:~~filtri~~~~8wiJt~~ using the
privileged instructions because ~~mo4~tifiyes the··:p.ammer complete
access to many of the internal d~Wtils of lR,:~~:2J.164. Refer to Section 6.6 for
information on these special PALmod~:4p.stnii$.Qq.~.

----------A.,;,;,:ji~,:,:,;,:;;1'1:•1,.,.,.,:;~~~~~:--~-:1_N:l_>·________

It is possible to cause uniritended··::S:td.~t.~ffects by writing what appears
to be perfectly acceptaQ.!g:j~R~code. XM::~ch, PALcode is not something

that many u~-~rs wi~:~jj~if"tltil'I:;=~·
·:::t~~}:··

6.3 Invoking

.· : : : : : : : : : .

Pi~~,,t\~~::•t>

····::::?·

PALcode is invokea::~~it~:J~pedfii.Jentry points, under certain well-defined
conditions ...:ll!!M!A:~.ntzy:~jpgjp.ts provide access to a series of callable routines,
with each.::fHlitfri'.:~Iffi:dexed~~j~fs an offset from a base address. The base address
of the P.Ai.iodEt!~~::~prQ.lrammable (stored in the PAL_BASE IPR), and is
norm~UY :i:i\J~jfthe ~·tern reset code. Refer to Section 6.4 for additional

"''" "'• :c~:~!f~~:::::~:

both to the hardware and to PAkode

/~:[J:f=f@li~elt . ::::\Vhmi the CPU enters a PALflow, the Ibox sets PC<00>. This bit
. /~fjf..
·.:filnains ·-~~tlas instructions are executed in the PAL Istream. The Ibox

Jifjff

. ::hldware igtl~res this and behaves as if the PC were still longword aligned

·::::::q~flt::.. ::/~}for the purposes of Istream fetch and execute. On HW_REI, the new state of
··::::::(\\[\\\\\\t\\I~:::::. PALmode is copied from EXC_ADDR<00>.

''9®-lt~~·
Preliminary Edition-September 1994 6-3

When an event occurs that needs to invoke PALcode, the 21164 first dr.•s
the pipeline. The current PC is loaded into the EXC_ADDR IPR, and thgl\.
appropriate PALcode routine is dispatched. These operations occur undei~lflh.
direct control of the chip hardware, and the machine is now in P4&m9.:d.~. "\lil~i\.
When the HW_REI instruction is executed at the end of the PAJ.®od~::::f6U:\m~Mih.
the hardware executes a jump to the address contained in the)~l.;(!_ADDR.lPH~;fl~t.
The LSB is used to indicate PALmode to the hardware. GenetiUi:Jhe LSB is \it~
clear upon return from a PALcode routine, in which case,_._tb.~ hard:\V~m~ loads ·(Jf
the new PC, enables interrupts, enables memory mapp!mrFMilJPSP~t..~s back ··
to the user.
~ l l!I! !'.'.: '· /~~jjjjjft{~~~llll~~~itf}· · :·:
The most basic use of PALcode is to handle complex haf.dwlte evij:ijts"~ and it is
called automatically when the particular hardw~~:::~yent iil~l~~n§:~f~ This use of
8

:::~ s::::r:::h::~::::;::::t:lVi:::~ns of

PALcode:
-+tf:= : : : : : :... ··::t{j~~~~jj~tllt:::::..
.· : : : '
• When the 21164 is reset, it enters P~mQ.4e aHQt~J.:ecutes the RESET
PALcode. The system will remai;gjJ), PAmhM.e u.Rtii a HW_REI instruction
is executed and EXC_ADDR<qqf.@iM~!t~red:\ll:)tthen continues execution
in non-PALmode (native mode)f as jtisti~~l~:~cribed. It is during this
initial RESET PALcode e~~f.i\{qp_ that tlUf~[t.est of the low-level system
initialization is performeq~\~jfocltiflWi. any modification to the PALcode base
register.
<lt=· <t~~l!ll!l!t\.. ··:t(l~~~l::• When a syste~ h"tirdw.~re e¥&'t::Js detected by the 21164, it invokes one of
several PALcijg~t_roti'.tiij~~~- dei)ai!ftjp.g upon the type of error. Errors such as
machine check:~W~ithmeti~~=:~;x:ceptlons, reserved or privileged instruction
decode, and data . f~l.k~rroftf~llre handled in this manner.
•

•

When the a1~164~l~$~Q;:~1l;~~~d.n~rrupt, it dispatches the acknowledgment
of the int~tfupt .tf:Vl' Jl.~cMle routine that does the necessary information
gathering~l~lt;h.eg{Jfuu1~ the situation appropriately for the given interrupt.

Whej~j~~ D~ Q:t>fltream translation buffer miss occurs, one of several

Af.)f~1!~~~=~:~~;~~=~;~~:;~~~~~~,t:~l,

.-i~l}?
Rl~~fftt,13, R14, ··:Khd R25 when the CPU is in PALmode and ICSR<SDE>
·t\JE~\::.. i~Jii~~forted. For additional PAL scratch, the lbox has a register bank of 24
·-·-::q~~~ll\l:ll~\:ll1£'~:fo~=~sters, which are accessible via HW_MTPR and HW_MFPR

·-: : \~l l~l :lj~ l~ ~: -

6-4 Preliminary Edition-September 1994

PAP~C:~eeis~~v~?ed~~:~=fic entry points. The

604

5" C~~~=~e~=~oints

PALcode entry points: CALL_PAL and traps.

~;if

21164 has two
../:::~t:::::::·:·... ·:{~)f\

are used whenever the Ibox

encOwl.~,:~~!~}

instruction in the instruction stream (lstream). CALL_P.AL 1H@.tµ~tions stati/
at the following offsets:
.:(~~j~~\~)\jj~~j){lj~!!lllllt~t::::::. ··::\:fi~lljt~>
· :·:·
• Privileged CALL_PAL instructions start at off~lt 2oqq:y::::::t]\\/l:·

;,,e~=~~;!g:e~~~~:~ ::~::;1;-~: l~f:or the
0

minimum number of cycles necessary to p~ftorm ·~n~ampliCit TRAPB. The PC
of the instruction immediately f<~lJq:wing:::\ti.@\CALL_PAQHs loaded into EXC_
ADDR and is pushed onto the reti&n. ;:predMt.19.v... . stack. .

The Ibox contains special hardware .,fg~lj'-iP..~~~~ijlltb:e number of cycles in
the TRAPB at the start of a C.t\bbi.f.A.L.'·:::Sif\ware'. can benefit from this by
scheduling CALL_PALs such tP.~tlBi!:~:pp ri()f:~t,all in the shadow of:

Af$1-~~h "1l\if;,

•
•

IMUL
Any floating-point op¢fiite, esp~lly FDIV

Each CALL PAE~jlinstn::~uiidnclu~·::!j~lli:·function field that will be used in
the calculati0;n or"°thetnext .PC~)rhe PAL OPCDEC fl.ow will be started if the
CALL_PAL filitl~t~:- fi'~l~ljjltj~:~::::. ··::::::(~jI}
• In the range 40(:::·.~:::to 7F::::=::tinclusive.

~::i~t:~;~:~~:lusive,

k,~j4e~!!i!!:~j~:=~t:~lll~f

::::=

Jl! ! !l~

and ffi<CUR_MOD> is not equfil to

If n_p'~jl).PCDEflA~tJl~te'cted on the CALL_PAL function, then the PC of the
..·.·:·:·:·:·:·.. insiMition to ei~Mite after the CALL PAL is calculated as follows:

PC< 12> = CALL_PAL function field<7>
PC<11:06> = CALL_PAL function field<5:0>
··:·::::~

Preliminary Edition-September 1994 6-5

•

PC<00> = 1 (PALmode)

The minimum number of cycles for a CALL_PAL execution is 4:
Number of
Cycles

1
1

=: ~s
0

ror empty ¢pe. 1Y¢caliy thls

Issue the CALL PAL instruction.
_,,/:~:~:[~\\ll{~~t:::.. ··==::::::\\!i\ltt,.
The minimum l:ngth of a PAL flow. Howev~~Bri ~'~ii.t~s. ,~h~fe will
be more than two cycles of work for the C~~i:-PAMJ:=· ··=·====~:~l!ItiJ=·

4.P~::::i!~~:~:~ ::~~::tart

/1!~'!!'1~~:~

vn1i~c-:::~~\~•.

PALrode.
required
for replay and mispredict type trapsJ... EXC.:;;..6.tf.J>R is loiblitl:· with the return
PC an_d the lbox performs a TRAPB'':itf tqe sh~w.: of the tfap. The return
prediction stack is pushed with the PC o~\\tlw tra'.Pfi.gg instruction for precise
traps, and with some later PC for imprecis'&::~fifps. ···===tt>
Table 6-1 shows the PALcode trap::~\dt~faN.i~;~t~~ their offset from the
PAL_BASE IPR. Entry points ar~tisted ·ffi.ut:bigh.est to lowest priority.
(Prioritization among the Dstr-i\~\n1ps wotl~l='because DTBMISS is
suppressed when there is a ~fgh ch~il~tw:ror. The priority of ITBMISS and
interrupt is reverseqjf ther~t\!iJm Icacn~\[[~iss.)

Table S-1 PAL~:;rat~ )l~ "
1

Entry Name

0200
0280
0300

6-6 Preliminary Edition-September 1994

Reset
Istream access violation or sign check error
on PC
Interrupt: hardware, software, and AST
Istream TBMISS
Dstream TBMISS
Dstream TBMISS during virtual page table
entry (PTE) fetch
Dstream unaligned reference
(continued on next page)

Table 6-1 (Cont.) PALcode Trap Entry Points
Entry Name

Description

DFAULT

0380

MCHK
OPCDEC

0400
0480
0500
0580

ARITH

FEN

6.5 Required PALcode Fun~!~'Wf"

Table 6-2 lists opcodes reqwrl. for ~}j=~~~MP.na AxP implementations. The
notation used is oo.fllf, wqi.f~tH;~~~i~:-.the hexid.ecimal 6-bit opcode and :fHf is the
hexadecimal 26-bit functi&i code·>=~hlt:=:·.
Table GC-2

f\tA:.~~~::
··:·:·:·:·:·:·:·:·.

··:·:·:·:·:·:·:·:·.

Codes

Mnemonic

6,::§i~~t~!!?:s~~~::~~o~ the Architecturally
.:d~i:i~~J~r=··

{~f~:r:..

··=:l.J.Lcod~·=:=d~-$>the Alpha AXP instruction set for most of its operations.
,/Wable 6-3 lists the opcodes reserved by the Alpha AXP architecture for

···===t{~llt::::..../~~~]Hmplementation-specific use. These opcodes are privileged and are only

····===tttlL available in PALmode.

<('\\ll~l&'

Preliminary Edition-September 1994 6-7

Table 6-3 Opcodes Reserved for PALcode
Mnemonic

Opcode

Architecture
Mnemonic

HW_LD

PALlB

HW_ST

PALlF

HW_REI

PALlE

HW_MFPR

PAL19

HW_MTPR

PAL~:ij}

21164

Function

OPC]JfJQ";•:;i,~ecuted

These instructions produce an
while not in
the PALmode environment. If ICSR%:lfW@.? is·:::~ih~hese instructions can be
executed in kernel mode. Any soflifare ~ii®..ting··:~th ICSR<HWE> set must
use extreme care to obey all r~.dili~ms list~d~l~ill this chapter and Chapter 5.
Register checking and bypa_~~l~-. i~~~:::~~t:Provided for PALcode instructions
as it is for non-PA14.~d.e im~t~u~t~ons, wH~rfusing general purpose registers
.. • ; .AL. ..,%%\it{_::.::_:~:.::_:;.
·till:::::i::::::::::.. ··====<1::tt:,...

(GPRs).

··:=:=t:)\...

·.·

··:Note - - - - - - - - - - -

Explicit softwar~·:::ilMt#.gj~::::;!ijiiired for accessing the hardware-specific
IPRs and ~h~m114#..;;;:;1.'EM\l[:t~gisters. These constraints are described in
Table 5411'.r· .::d:i:ii:~ll~llp::·<::~l\ · : : r
.-:.=....
l~~t?

t~-~-~:~:~-~: ~.=~-~-·.: =:.:.: ': · ~:~.:·,~;_:·-~-.:~=_:·.r: -

. :;~~~~t~:
: : : :·

6.6.1 Hw LDt:lnstructionmtJfr·

. ,/:::JV.:4.kPJ::~:G~,. the _LD instruction to access memory outside of the realm of
::::::::ltf',. . no~W Alphi[~:HJ> memory management and to do special forms of Dstream
. :::fl/.. loaq'-~f Figure 61f and Table 6-4 describe the format and fields of the HW_LD
(::]~\:::=:... in.~tftiction. Data alignment traps are inhibited for HW_LD instructions.

'"tll,'''\\jt
6-8 Preliminary Edition-September 1994

Figure 6-1
31

HW_LD Instruction Format

26 25

2120

16 15 14 13 12 11 10 09

Table 6-4 HW_LD Format Description

00_.:·.·..

11;" ;_:_J:l:.1:.•.=•_.=·.=·=·:·.=·-=_:·=.=·1_:•_=1.=·._=:.=.:\.=j·.:·.=·_.=:.=·_.=•=.. ·==·.=·_.=•_:·,:_: :=·•1_.r:

,(j:\:\\]\\tt\th:::·:·.

Field

Value

Description

OPCODE

1B1s

The OPCODl~hfield cdtl·~ IB1s. ··==:::=:t?

Desti~ation r;~s$t;::r1u~-~l\.:.
Base register_.fo.r ~~~:-.add;gij~·.

RB
PHYS

iJ::
:::3~;\!t~~ti ~~ ;::~. Translation
and
access checks are inhibited.

0
1

m~ro.~-manag~'ffi:i.~!;

ALT

Me:m.~~:£~~~pient ~~~cks use Mbox IPR DTB_CM for access

0
1

:=::t:,..

<Ik=·

c~~P.:·

···==ttil:::::.. .

Me~::::managemijrit checks use Mbox IPR ALT_MODE for

·=t\\~~~ess·==el@~!~·

··==t:~l\lllttt::=:·. ":!~~::!;:::~~ ~~=~~: ~g~' a;g;,~~a~r:d~~!i~~~~ss

WRTCK

,@Pt~::~*C;7iongword.

QUAD

i\l:j\\:f==·=··"l:'''.'.'.'.~::j:jjj\)=' ='~rlg@f is quadword.
VPTE

f~l

kt?=.. {l!ags a virtual PTE fetch. Used by trap logic to distinguish

=.;;'= .·_j/,,,;;:'_: _: :_:~_:r·j.·:~ - 'W_Jt41 it~{~ :~i'lfl,;w1tJ!~ ~g:~ ~ ~ ;:~:;:~t~: : ·
·.

. : :.:

·: : : : : :

··:::f(\}:·

W\t{lii%111;i~\l}ji

Preliminary Edition-September 1994 6-9

6.6.2

Field

OPCODE
RA
RB

PHYS
ALT

Holds a IO-bit signed byte displacement.
HW_ST<l3,11> must be zero.

6-10 Preliminary Edition-September 1994

6.6.3

H:;:_~~:=:on is used to return instruction flow to the P~~jpted to
by the EXC_ADDR IPR. The value in EXC_ADDR<O> will be q§.~d as ·tfi~:. new

value of PALmode after the HW_REI instruction.
Jj~~::~;?~l[ll}t~t:::::tt;;:l!!!l!l!!!jl~\.
. The Ibox uses the return prediction stack to speed the ex~~#.:\:l.on of HW:IU~Jt.
There are two different types of HW_REI:
·::t~l{j]lh:..
\]~~j[[:
•
•

Prefetch: In this case, the Ibox begins fetching tb~t~~:W' 1·;fN~».1.as soon:::~;~:
possible. This is the version of HW_REI that i~t:ti:Orih~@.Jy:J1sed?H>
Stall prefetch: This encoding of HW_REI inhil.{~ I~tfl::~!!~f.~tih until the
HW_REI itself is issued. Thus, this is the metiihd. ~=ed tqj:j~~ynchronize Ibox
changes (such as ITB write instruction~)tfi.itb.Jhe :f.tW~I. There is a rule
that PALcode can have only one such H)l/JiEitl:lm. a.If=fiUgned block of four

instructions.
./[[~\:· .,::t::l:!!!!!!!lb,.
"::::~{lljl:ljf·
Figure 6-3 and Table 6-6 describe. th~. formijjJµid fields -of the HW_REI
instruction. The Ibox logic will slot H\ta.&.EI l&P.i1u~ El.

·"';""*· "qt\'1{1J ''.Y"

::gum~. :W_REl2:~:;i~:~i{%·

I :+++ : I : -~:ilW. : I,=~ l~: : l!l! !r . : IT~w1:llll:t·: : : : :Mrz : : : : : : I

Tabte

6--6

. . dbc

'i(¥%lq@

LJ-03471-TIO

~::-~~-~rlptk>n
···:·:·:·:·:·:·:·...

OPCODE i~!l !l l:'.v·

··:·:·:·:·:··

lE~l}f /fhe OPCODE field contains 1E16•

~J' y 1~f$1;;:;~:~~ should be R31 to avffid unnecessary stalls.

Ai,ffet\1'W_j,J}'~tvlifJk

HW_REl<13:00> Must be zero.

/ft6.6.4 HW MFPR and HW MTPR Instructions

''\\f;-\ifti~~~1:-:~:,~~.1:d~:C~e~~~~~:;P~~: ~:s:~:!e:a~:tare
··"\f{]~t~ncy of one cycle (HW_MFPR in cycle n results in data available to the
"li~hg instruction in cycle n+ 1). HW_MFPR from Mbox and Dcache IPRs has

Preliminary Edition-September 1994 6-11

a latency of two cycles. lbox hardware slots each type of MXPR to the <;frrect
Ebox pipe (refer to Table 5-1).
·'\lf\.

Figure 6-4 and Table 6-7 describe the format and fields of the 11\V~MFP~l~~·d

::::i:::::: ~nd
8

26 25

HW_MTPR

21 20

.,d~;j~ ~i~:~ l~l l~l ~ Ii;! ~ ~ ~fL:,.
I : : : : : :Infex: : : :~li i i ~ : :.d~t~~r:: · · :1i:~1 1 1 1l~ltl ~l}·

Table 6-7 HW_MTPR and HW_MFPR
.·:·.
Value

OPCODE

1916

lD1s
RA/RB

Index

•:_.:·.:_··.:.·_

16 15

I :+++ :I : :+:I : :+:
Field

ln~~bn Fonn~ +'lt~.:.·•·.i:·.,· : _.:·_.:j.:•·:· :i:~l.!Iy{l\t
'"'~"'

·.· ''ii

Fonn•,t=!~•'L
·:·:·:·:·:·:·:·:·:·:·:

··:·:·:·:·:·:·:··

Description

The OPCODE field criH~!$ 19~l=(c)}:JIW_MFPR.
The OPCODE fiel.d. wntairifolD1s f&f'.HW_MTPR.
Must be the d~~~:~l~~b.f:~e ;!~~l' for HW_MTPR and
destination relfister fof:~U.,.,.MFPR.
Specifies tn;tla~J~efer t~:~Tihle 5-1 for field encoding. Refer to
Chapte~ 'l:for m8ijbq~tails about specific IPRs.
·:::::::.::::::::

6-12 Preliminary Edition-September 1994

··:::::::::::::::::..

Initialization and ContkJ,uratfd,I

This chapter provides information on 21164-speJ::l:~;~~em
i[J

't?

initialization and configuration. It is organized as fh11Q:}¥~:
•

Input signals sys_reset_l and dc_ok_lj[l~lla[llfi~mti~1:i::::[lff[[[f?

•

Serial terminal port

:::::::::;~:=~ (SROMi~~~\~l-i~)'
,,:JlJt\::::..

··::::::t\:ll~ltr .

: ~:::ii:~:~:~nitMn{:,w;~l•ii;;,,

Internal pr~'~sor r~l'-Lr (I;ijlllf.ijset state

::~;::st~·~~~~~;:tnr
•

7.1 Input Siggp.IS.t§¥$··::::'r"=§et_I and dc_ok_h and Booting
The 2116f~l~l~es~k~~~~U.~'P.ce ·~ses two input signals: sys_reset_l and dc_ok_h.

Whe11:::. traij$it.idrRng fiM.m a powered-down state to a powered-up state, signal
dc_Qil[h IH\ii.l(b.~ .d¢.is.serted, and signal sys_reset_l must be asserted until
po\f~tl~:tias re·A~liiaflhe proper operating point. After power has reached
. {:/fittt4P.e·.··:pfi]M~r operating point, signal dc_ok_h must be asserted. Then, signal

4)\jfP''"''8;i':te~lf;~b:c~:~~~~~o~!!~~~s~:~ :;~..;se:~ff:~~~;wered
.(]:lK:::..

.:f~i.~:serted internally. After sys_reset_l is deasserted, the 21164 begins the

'Wt\lqtlC~~no~::::~:;:: ::i::::~:~;:i

··:::\{~~j:~j}An optional automatic Icache initialization, using an external serial ROM
· (SROM) interface
Preliminary Edition-September 1994 7-1

3. Dispatch to the reset PALcode trap entry point (physical location O)./h:
a. If step 2 initialized the Icache using the SROM interface, the c;li.t..
should contain code that appears to be at location 0, that i~h.JP.e c~ijfi~
should be initialized such that. it hits on the dispatch. '1:'YP.i~iliJ.ttlu~'.'.:~~lt\
code in the lcache should configure the 21164's IPRs 8:~ [\fi~cessaey=H~~{{\\\l\\\\\.
before causing any off-chip read or write commands. lldi:: allows the ··.··::l\ft
21164 to be configured to match the external system implih.\~ntation. ..11\j
b. If step 2 did not initialize the Icache, the Icach~tfiiij\\~.n ··~J~l=t.~ by ·:::tf
reset. The reset PALcode.trap dispatch misses3¥f"theJfijb.~. @d'Scache
(also flushed by reset) and produces an off-chipfa~eac;lj~~jh~ili.i.it The
external system implementation must be compatiblf:hvitll~jjhe 21164's
default configuration after reset (refer w~~~$.®.ti9n 7Y$)k{JJl.tif code that
is executed at this point should compl~W:''tlil=lJ.l64 -~hhfiguration as

4. Afte:e:::::~g the 21164, conf1i gw'~~~e~:! ? code anywhere in

memory, including the noncacheable.:'fiijppps ...,tf:jj\!Mt SROM interface was
used to initialize the Icache, theJ~@:~he ··'eqtb..~ flushed by a write operation
to IC FLUSH CTL after controiHit&ansferti~b:. This transfer of control
should be to addresses not loadid in:·''lfiiju~~ch'i'' by the SROM interface or
the Icache may provide ~-~;~d instrile$ons.

5. Typically, PALbase and .,Jf:,:-~·~;i!\\~tiqµired by PALcode are initialized
and the console-::j~:::·start~Q}(~witching=~~}lt of PALmode and into native
mode). The c~msole .c.P.d.e inltlalizes and configures the system and boots an
operating sy~m frofiU[~. IJ<f'a~ti~e such as a disk or the network.
Signal sys_reset3~~fdf~mtt~~tQBY. i~~ a known state. Section 7 .8 lists the
reset state of each IPR>T@W.~ 7~tlprovides the reset state of each external
signal

pin. itW~'Jf;,~~'%l~J'

Table 7-1,.·:·:·:·:·.
. AIP.h~.,:1Jl64
$fgnal
Pin Reset State
·.·.:·:·:·:·:·:·:·:·:·:·:··
·:·:·:·:·:

(continued on next page)

7-2 Preliminary Edition-September 1994

Table 7-1 (Cont.) Alpha 21164 Signal Pin Reset State
Reset State

Signal

Clocks.

osc_clk_in_h,l

Must be clocking.

ref_clk_in_h

NA (input).

sys_clk_outl_h,l

Clock output.

sys_clk_out2_h,l

Clock output.

sys_reset_l

NA (input).

Bcache

Tristated.

data_h<127:0>

Tristated~~tJ:

data_check_h<15:0>
data_ram_oe_h
data_ram_we_h
index_h<25:4>
tag_ctl_par_h
tag_data_h<S8:20>
tag_data_par_h . : : : :.
tag_dirty_h
·::t{f

,;{!~titt;;ft'' '4'
·:i~~~;::::::.

(continued on next page)

Preliminary Edition-September 1994 7-3

Table 7-1 (Cont.) Alpha 21164 Signal Pin Reset State
Signal

Reset State

System Interface
addr_h<39:4>
addr_bus_re~h

addr_cmd_par_h

(continued on next page)

7-4 Preliminary Edition-September 1994

Table 7-1 (Cont.) Alpha 21164 Signal Pin Reset State
Signal

Reset State

Test Modes

port_mode_h<l:O>

NA(input).

srom_clk_h

Deasserted.

srom_data_h

NA(input).

srom_oe_l

Deasserted.

srom_present_l

NA(input).

tck_h

NA(input).

tdi_h
tdo_h
temp_sense_h
t~st_status_h <1:0>

tms_h
trst_l

=~ ~:::~ (31~:::~%%l%r
:~~:::i\1,zy
····=:ttf:::·

Miscellaneous

perf_mon_h
spare_io

signal~~,£~~,,.::!d,

While
the 21164 provides its own internal clock
source from an on'.::&-~P:}:ing~'~ii~mator. When dc_ok_h is asserted, the 21164
clock sourc~J~4b.~. diffi.ntiai . clock input pins osc_clk_in_h, 1.

: :~ !~! l~l:~ : : : :=·:·=·:,:·:.:;:·;· ~l! ~ :~l: : ·: ~ i: . · : : : ~ : : l: : ·

Caution _ _ _ _ _ _ _ _ _ __

1\{~Jo~l!!j~P,~¥:e sh.ll1d always be provided when signal dc_ok_h is

-:(11·~rtedYfl~t:tt@fF~:::::

Alf}i[il!.flf~~t::,Dseu must remain asserted while signal dc_ok_h is deasserted,

,:ff:(:'.:

.A#fd for somi{period of time after dc_ok_h assertion. It should remain asserted

··::::::~t(~h:k:... .,J::1tor at least 400 internal CPU cycles in length. Then, signal sys_reset_l may

":=:=:::tHtII?. be deasserted. Signal sys_reset_l deassertion need not be synchronous with
"::\{]tr~spect to sysclk .
."\=~w::::I>

Preliminary Edition-September 1994 7-5

When the 21164 is free-running from the internal ring oscillator, the intimal
clock frequency is in the range TBD. The sysclk divisor and sys_clk_odW=.j;,.x
delay are determined by input pins while signal sys_reset_l remains ass-. . .~.
Refer to Section 4.2.2 and Section 4.2.3 for ratio and delay values.{~l:~t::::::::::·:·.. \f~~:t

70101

70102

P:e:;~ :Pq~~=~:.~~ de power supply. This 3.3-V powjt:~:f:~:~\)

p~~=~:~:~~~=;~~:::;:::s:1:.1~;::and

'@!

bidirectional 21164 pin is tristated and pulled w~.MJY to 6mt~iY a small

7.2

S;::;;;:s::~ Delay

;tjp

,qc::U\%\\\~:{ijlF

While in reset, the 21184 reads sysclk CQgpgu.ratiq!tparameters from the
interrupt signal pins. These inputs shouittf&.t:-~riviiW~th the correct
configuration values whenever signJ!k§.¥:§....reSQk\)s asserted. Refer to
Section 4.2.2 and Section 4.2.3 for:tiMeWl.!1tJµpuf::3ignals and ratio/delay
values.
..t:t:[:~[~;llll!l!ib... ": : t: ~ ~ j lj I}: :·
If the signal inputs reflecting#~oiin@lf:lt.ion parameters change while sys_
reset_l is asserted, ~'low 2:Q:::MternaftJ8\L.cycles before the new sysclk
behavior is corre~~~ ·<t/· -:f}:::::::..·. .:::::::::tl:jljjt~::t:::=:::.. "'·: : : : :--

7 .3 Built-In Self-Te-tt(Bi:St)t:::::.. ":::::::::{}:

Upon deassertion of==:{iijit.~;:~et_l, the 21164 automatically executes the
!cache built-in ~~lftk.~.t (Bi$.t}~. Tli'e Icache is automatically tested and the
result is mad~ti:V~Ufli&.l~ in tlMhCSR IPR and on signal test_status_h<O>.
Internally, tht~l[CPlkfi=setttontinues to be asserted throughout the BiSt process.
For additi~naU}.µf~Phati~W.~ refer to Section 12.5.1.

·~,.;~;~1!i~~;~;~;i;:;;;;;~;~: ~:a:~~:O~fo:n~ta

.::::::{[[):"

initjfipzation, thf~ interface can function as a diagnostic port using privileged
0

'\tt\1ti1(C:=: :~:::::)~ROM interface:
sMin_data_h

7-6 Preliminary Edition-September 1994

Du:::;~eset, the

samples the

Jlign:'L

21164
srom_present_l
the presence of SROM. If srom_present_l is deasserted, th~=::$RQltd9.aaa~
disabled and the reset sequence clears the Icache valid bits~HU'his c;·;HHil#Ji~.
first instruction fetch to miss the !cache and read instructihfii from off-chlpfllt,

~i;~~aS:~~fo~~:asserted during setup, then ,,1,.~~'~s an ·r'

~: :: :::~~;a~:~::~:e:t:::~;! t:l!~ses
it
Is''''i2.6±
advance to the next bit. The cycle tim~f1l~f"tli1§j¥l9.~k

to
times the CPU

:~;::~ta.Ji signal in;9£s !h~''')l.!la~~%1'

Every data and tag bit in the Icache ·=i~j~jjl~!4.~d. ,:6yll~@is sequence.

~::~~i. of the Icache ~~:(~~~~timing is described in
7.5 Serial Terminal Port~tw==·········====\tl~t:::::..

After the SROM#]ata iE{llg~d in;::jjfft~=· !cache, the three SROM load signals
become paraU~l ilb .P.m~ tii:'it~l~@P. drive a diagnostic terminal using an interface
such as ·Rsd~tlllllllllt:::::,.:=·====t1~~lltl1llltltt:::.:···::qllll~~l)

7 .6 Cache lnitializatibn . \'tll=·

Regardles§j~jj:WK~tb,~:::jj{Wijl~jJc~:he BiSt is executed, the Icache is flushed during

the reset ,j~'queq¢.tlprj9r t<{the SROM load. If the SROM load is bypassed, the
!cache wi\Ut>e.JpJth.e . '@ished state initially.

The '~ondltl:.L~a.¢.Sl ''(Scache) is flushed and enabled by internal reset. This
is t:igijjred iflli~tsR:bM load is bypassed. The initial !stream reference after
0.
will
1

Ai•'*\j]ifQfl;;i--;:n Because that is acacheable-space reference, the Scache
.,/II?
··:''\{]}=::::,...

. /lie data cache (Dcache) is disabled by reset. It is not initialized or flushed by
,,fiiikset. It should be initialized by PALcode before being enabled.

'"qzi'~~e::~~o!':~:~;:~!~~~e is disabled by reset. It should be initialized by
··:·:::=~~~mJ~==·

Preliminary Edition-September 1994 7-7

7 0601

•::h:a~~:·:·:~~:: coherent with memory. When it is necessary to ~

it coherent with memory, the following procedure is used. The C~~PAL "ll;e

~!~§~:::::::~::::e::7!::s the ~;;~:t!\l\)
m

: ::::~:~~~~~2:::7:~~~l~=\~e

prefetch buffers and lbox pipeline. The 44:~iBd'fil~)nictfoiffmust start on
an INT16 boundary. Pad with ad~tion~kNPP instifiijii~lns if necessary.

70602

F~:n~;~ ::f:~:ek:covery, dJ::~~.~:::~11~$us:: out of the Scache
and backup cache (Bcache), if pres~nj@jtt:::.. ":·:'\llbt:...
Systems Without a Bcache
.=~~![![!~?:. ··. "=·:=::~~~q::l:\tj~\=:.. "':\@?

To flush out dirty blocks from::::lt@:~che oti'':::p5wer failure, the following

sequence must be used to gg.i.fante·~ttb@:t all the dirty blocks have been
written back to mavtJnemoey~:kThe Bd2Q@NFIG<BC_SIZE> field is used
for this function in sys~:W.S WitflP.;µ~ a Bcache. When powering up, this field
is initialized to ~tY:~lue·==t.~p;:r~sentiqgH! IM-byte Bcache. During system
configuration flow/thi~_field:~~ji\µ~t b(fehanged to a value of 0 for normal
operation.
"::::qj~~:i::i:::::th:\... "'::=tt~::::::~:)·
To flush out th.~:Jtit1~).\J~.locR~mf.rnm all three sets in the Scache, perform the
following taslrr:. · -_:::;;~;i1!!l!~:r=:=_:{j\ ·:. :\r'
1. Set BC_CQ~:f:l.P<B0fil$IZE><2:0> = Oxl; do loads at a stride of 64 bytes
throqgp l~ft]~Ytes..J!J==continuous memory; guarantees all dirty blocks from
setoJife fluslU~dtO.uJDf"

Af¥1}•1t:!.;~~~~o~~~~~::~~=m°:~;d~r~::saa~~~o~::~::::m

./j{lf:"

Sitl are flu§ffod out.

·=tl :~ l !~i~l kh: ... ~A~l~ll!jj§~:t BC_CONFIG<BC_SIZE><2:0> = Ox4; do loads at a stride of 64 bytes

"::::::\tllt?" through 64K bytes of continuous memory; guarantees all dirty blocks from
··:::\lktset2 are flushed out.

~~t~tll~r values of BC_CONFIG<BC_SIZE><2:0> are undefined in this mode.

7-8 Preliminary Edition-September 1994

.J~\.

Systems with a Bcache

To flush out dirty blocks from the Scache and Bcache on power failuf:i1. the
following sequence must be used to guarantee that all the dirty blockstb.~ve

been ::~::~a~~::::::~ache block s~e 2x .~l~~~l:::;l\,h
=

77
.

Ex:~=~e~~=~:~~c!~~~~~ab~~~terface J1,:;J~;:~:\defaul~:'.lli

configuration dictated by the reset state of the IPR?bit~fthat)i¢Iect the
configuration options. The Cbox response tQ:J~:yjw:µi cow-~ and internally
generated memory accesses is determinedjbJ'='lll1il~l\~fauit\Mhfiguration.
System environments that are no.t comp.@tmJe with=l'ij.~4Jefault configuration
must use the SROM Icache load-'(e~ture·"'f=ijj~ftijtially loatPand execute a PALcode
program. This program configures. tqfk~~terit~lI!J~terface control (Cbox) IPRs

as needed.

dt;).,,:~\j'jq\lh, ' W,\}>

7.8 Internal Processor Regi§tel(~jle~et~:jj$tate
Many IPR bits are not ini~j~J~is. by r;=::imHlJlliey are located in error-reporting

registers and other IPR s~t=e·s'>=~~y must""°be initialized by initialization
PALcode. Table 1-2 list~dJhe state'=='if)yJ internal processor registers (IPRs)
immediately foU8Wi.ng re-~i\~tT..he tabUP°also specifies which registers need to be
ifiltialized

~wr~;~~~;:q1>

<:t~:~;1

4{-~ilt i-f,

Preliminary Edition-September 1994 7-9

Table 7-2 Internal Processor Register Reset State
Reset State

IPR

Comments
:=:::::::::·:·.·. ·

:~:::~ p~~if~;~:::~tWfl~-

lbox Registers

ITB_TAG
ITB_PTE
ITB_ASN
ITB_PTE_TEMP

uNDEFINED

ITB_IAP
ITB_IA

UNDEFINED

ITB_IS
IFAULT_VA_FORM

UNDEFINED
UNDEFINED
UNDEFINED /:::,,,._
UNDEFINED·:·:\?' ={}\,. ,.

IVPrBR
ICPERR_STAT
IC_FLUSH_CTL

Pi\Ikode must initialize.

UNDEFINED
····=tfJ~\P~~Wktnust initialize.
UNDEFINED:f\Wkh

''tf4tw . .

EXC_ADDR

UNDEF~~·/······.··::q~~~::t\\\\\\[~\[~b\,...

EXC_SUM

UNDE~f.NEQ\,,:,..

EXC_MASK

··"\flt:,..
.{\l~~~~~j\:,..
··:::::q~tlt>
UNDEFINED
. ,.·

PAL_BASE
PS
ICSR

tmt

~011i1111tt~\j)1
..::::::t{~fa~t::::::,..

IPL

INTID

·=:\~I~~~~t:

J\t

ASTRR,{::,Jl\l=

.··=:t~{\1t::::l:·

<;;~!::!:::~

··:::::PALcode must clear exception
summary and exception register
write mask by writing EXC_SUM.
Cleared on reset.
PALcode must set processor status.
All bits are cleared on reset except
ICSR<37>, which is set, and
ICSR<38>, which is UNDEFINED.
PALcode must initialize.
PALcode must initialize.

UNDEFINED
UNDEFINED

PALcode must initialize.

UNDEFINED

PALcode must initialize.

UNDEFINED
(continued on next page)

7-10 Preliminary Edition-September 1994

Table 7-2 (Cont.) Internal Processor Register Reset State

t~~!~~~h.

IPR

Reset State

Comments

SL_XMIT
SL_RCV
PMCTR

Cleared

:::::~r~::~1t,,h::fl

UNDEFINED
See Comments

on reset. Aii""Jtlm1t.bits are

J~~~;'.:'

Mbox Registers

DTB_CM

UNDEFINED
UNDEFINED

DTB_TAG

Cleared

DTB_ASN

··

DTB_PTE
DTB_PTE_TEMP

:Jjj~~~jffP~f::~e ::l:e,f~~~m'tialize.

,: . rnf

ValfiF§t~.. are cleared on chip reset
·(fft:.. but nof=if.ftimeout reset.

::::!<-1~~'~11,,,. .,

···:::t\\J~\¥ust be unlocked by PALcode by
··=:\J~~ading VA register.

MM_STAT
VA

Must be unlocked by PALcode by
reading VA register.

VA_FORM

Must be unlocked by PALcode by
reading VA register.

MVPTBR

PALcode must initialize.

.:fr~~==:~·-·.
DC PERR STA'Di\::·:·.

····:UNDEFINED

DTBIA

...\JJNDEFINED

D~IAP -

····::::::::ilij~jjjj\jj~~\\\\:::::~-f:JNED

PALcode must initialize.

::: &t.p.tWJf&L
Cleared on chip reset but not on
timeout reset.
Cleared

Cleared on chip reset but not on
timeout reset.

Cleared

Cleared on chip reset.
MAF_MODE<05> cleared on
timeout reset.

UNDEFINED

PALcode must write this register to
clear Dcache valid bits.
(continued on next page)

Preliminary Edition-September 1994 7-11

Table 7-2 (Cont.) Internal Processor Register Reset State
IPR

Reset State

ALT_MODE

UNDEFINED

CC_CTL

UNDEFINED

DC_TEST_CTL

UNDEFINED

DC_TEST_TAG

UNDEFINED

DC_TEST_TAG_TEMP

UNDEFINED

Comments
:::::::::::::.

ili~IOO :t(,~::~~tlt~0

CC is

.::~~1I~t~::::::::=:·=····

::/~~~\J}~~~)k::-:-.

Cbo:x: Registers

SC_CTL

See Comments

SC_STAT

UNDEFINED"4~tJ

··-:?tP.A:Lcode m~;t':~ead to unlock.

:~==~S•m i*\4-~~~ft:raoL<Ol:OO>,

SC_ADDR
BC_CONTROL

<07>,

i:~;::::lf\~~~~~~~~!~i?:

BC_CONFIG

See

\fab. <th ··+1(\~-1t•· ·.·
BC_TAG_ADDR
·-:,t:~\~~~~~~~~:tR~:rl-1~~

~o:~~~ego:i ~;ti:~ of

EI_STAT

·-::UNDEFINED

PALcode must read twice to unlock.

=~~~~ il11~w:~~I~~~
.::...

}ft

<t1l\\

\t_:_~:-~_:_~=_:_~-~-~-~_[:_;_~_r.~_~:_~ _mr·

·-: \_:~.=-~:=-~_:=-~

Jrt

: : : .: :~-~-~.-~-~ :f

__: : _: _: ·_:._:,_: _:'·: _: :__: _: -_:·_: _:,_:__:

~::), BC_RD_SPD (read speed),

Jtil,.j.lfilf'e sC::tt:ilarameters BC_SIZE

.::/II:'.:

·-::::::::t~It::::::...

. A3.C_WR_SPil (write speed), and BC_WE_CTL (write-enable control) are

_,,,Jta11 configured to default values on reset and must be initialized in the
'"%(.~~it~~~CONFIG register before enabling the Bcache.

7-12 Preliminary Edition-September 1994

79
"

Ti::~~::;:e!tch/decode unit and branch unit (Ibox) contains a1~

that times out when a very long period of time passes with nqjn.~:tructif.h
completing. When this timeout occurs, an internal reset ev~P:t:::H~iuritJtffi[~t
clears sufficient internal state to allow the CPU to begin ~ii.~uting agifiifillllh
Registers, IPRs (except as noted in Table 7-2), and cache·ffl~tt._not affected5{Ih
Dispatch to the PALcode MCHK trap entry point occurs imliM~ely.
_)}[f

71
0

l~=:l:~~·!u~::ta:~~d~:=:~_resetJ 11::l~1~:: dc_o~:
is deasserted. Continuous trst_l assertion dl!-ring no~J op~f~tion is used to
guarantee that the IEEE 1149.1 test port cJgSfhQ.t:J~.ffeHt2l164 operation.

qf'

At~\U\(\::.•.::'1i\f]ty

;\t&,,_t__lt

tf~\,~i:~w~m1
··::::::::·

Preliminary Edition-September 1994 7-13

Error Detection and Erro~1M.~ndlfi\g

pro~des

'~~l~~~:~gy.

This chapter
an ovefflew of the 211Ms
TY
Each internal cache (instruction cache [lcache], data caihe [Qi8,che], and
second-level cache [Scache]) implements pa1Hi{\\l\tgtectiq\'t:ftr\\fug and data.
Error correction code (ECC) protection is itfipleriie~!J.. f&f=memory and backup
cache (Bcache) data. (The impleIY.entati.9bi\¥rovides":H~~tion of all double-bit
errors and correction of an singldf:~it errdHi.}\J)orrectaSle instruction stream
(!stream) and data stream (Dstreaml@E.CC eH$..t.$. . are corrected in hardware
without privileged architecture_ libracy==~~Q.g~JP~pde) intervention. Bcache
tags are parity protected. The ~Af:D~~ioit(~~bfdecode unit and branch unit
(Ibox) implements logic that da~=fots:::Wle.P nc{ptogress has been made for a
very long time and forces a ...m.@@iine ch~ii.d?.ap.

PALcode handles all errotl~~if:~~~t{.achin~·::::~hecks and correctable error
interrupts). Wh~r._e pos$}°b.Ji., the addt@m;. of affected data is latched in an IPR.
Most of the lstrmin. ~rrot=M~n be retri~d by the operating system because the
machine che~k::. occu~\\~~lwfore::::~'.)\part of the instruction causing the error is
executed. In·.,~tim~,. othMf~~es, lRe~:'system may be able to recover from an error
by terminating -~1[\firp.ces~~ij\\\)b.~t had access to the affected memory location.

8.1 Error Flopfi\\~: ~\1'¢·%W
11

The folloWjhg fl~WS 4.i~cribe the events that take place during an error, the
reconµµei{l.~:9{f.¢§ponii$ necessary to determine the source of the error, and the

EXC_ADDR contains either the PC of the instruction that caused the
parity error or that of an earlier trapping instruction.
...:,::~~~~{~~'=~l[::ll}:ICPERR_STAT<TPE> or <DPE> is set.

"'''?{%\:::,..

Preliminary Edition-September 1994 8-1

•

~;~~~::~~s: ed:~~;ti:eu;:s~:e!;c~~~~~I\\\·°'')
'tt\if&;th

point, an infinite loop may result.

. .::::f~llt:-.

.-.::t{ll~ll~ll\\\\):·

8~~ S~a~
•
•
•

executed.
.·.
../}:~!!!!!Ir·
··::==~=~~l:i::ittt::::. ·····
Bad data may be written to the 1ij.che of~ta.k}le refill "miffer and validated.
Can be retried if there are no mui~ipli.ll[~rr.~;::~:\\\jljj~lllt~:\...

Recommendation: Flush the Icache:::to ;~Md\e.. b;d/data. The Icache refill
buffer may be flushed by execy\frig=~~iqqµgh·=·=ifii:tructions to fill the refill
buffer with new data (32 in~_tdi~tions)"::::::11!~P flush the Icache again.

•

SC_STAT: SC_DPERR<7:tW~lllf;mll~'-tt~SC_S:~D_ERR> is set if there are

•

multiple errors. -:{lllt:.
<t::i!l!!!l:h=:·.
· ,·====t:l[lllll\l}=·
SC STAT: CBox-===cMD is TRD~:-.
.

•

SC=ADDR: ditt~n~{lW~)l~~d~;~:~[~~\~9.f' the 32-byte block containing the error.
(Bit 4 indicates.\'f:tiJd.i octiWO.:r4 was accessed first, but the error may be in
either
If the .

octawo~~~? · : :?l lili\lil jl :\.f_l.~_.=_,:l.l_=~-=·.='·.='.=.:.·:._=·.=:.·:·.:.:·.·\(f:·
.·
·==~J\\[fl~Jll~llljj\~l\[[[)

Note - - - - - - - - - - -

Istfl:n:tBl~tY'.'1!lltror occurs early in the PALcode routine at the

maclY.P.e cR~l.~:'.:entry:~~Ifuint, an infinite loop may result.
..::::~===J~mr

··:===::~~~t~~~~~1~~~r~tr~~}:··

J{ifW'{f-·=~tion: On data parity errors, it may be feasible for the

.::/\l}f'
.fJlf;;:..

~P.hating . =sy~tem to "flush" the block of data out of the Scache by

,(~'questing a block of data with the same Bcache index, but a different

···=:=t~lt\ln~~=:=:::..../llilMag. This may not be feasible on tag parity errors, because the tag address
····:\l~lll~~l](. is suspect. If the requested block is loaded with no problems, then the
":::::tlmtrP.ad data" has been replaced. If the "bad· data" is marked dirty, then when
"::ll~il~=new data tries to replace the old data, another parity error may result

8-2 Preliminary Edition-September 1994

during the write-back (this is a reason not to attempt this in P4.L,code,
because a MCHK from PALcode is always fatal).
·=\~lh.

8.1.3

~ac;;;~.:::~t:c::o:efo::t::::struction causing ~·~::~~~tit~
•
•
•

•

Bad data may be written to the Icache or !cache r~fiR.bu.ffef:i~ihn.d validated~
Cannot be retried. Probably will not be able tqfti~~~~J~l[Dlh~~I:fih·g a single
process because the exact address is unknownfll .Jf/ . . \:lttfk·
Recommendation: Flush the Icache to remove ==f;~d ,ar~a. 1=:====~cache refill
buffer may be flushed by executing enqmftHm§:t.ructi~tMflJ~f fill the refill
buffer with new data (32 instructions)~1fheri. l'ltgJ.t.th€tlcache again.
SC_STAT: SC_TPERR<2:0> il.}~et; <illSGND_~•~ is set if there are

multiple·errors. 8 "' ith. "".%;1'~~ij;c
:~~:~~0~~::! a·l.~:~!f~te block containing the error.
either octawo~d.) ;fot$J;\\~-~:41-)==_·-----------

(Bit 4 indicates which oct~W.ord waM\1.~~essed first, but the error may be in

If the

Istr~~~?~.¢.rit.y··==:lrbw.curs early in the PALcode routine at the

machine :::Uf!ti:::::.iit~::W~t~t}:1'}infinite loop may result.
· ====tt}=·

8.1.4

1
•t::;:%tfl;! :~~~~~~~::!s~::sn;:::~-~:b~~D=~ng the error.

···==t@t::\... (Bit 4 indicates which octaword was accessed first, but the error may be in
· ====:=:tliii\:::. either octaword.)
··::tt?'

Preliminary Edition-September 1994 8-3

8.1.5

S~ac:c::~ ::~~c::~~=:e:=e :~::h:::~nds ,,\k
•

Cannot be retried. Probably will not be able to recover by d~l~tiiig)t§i;.lli::,

. !;.~!i;~:=~0:d:r:::;i::;~:_ERR>~~l~~'\\~::::~Wt-lJ
•
•

8.1.6

SC_STAT: CBOX_CMD is DRD, DWRITE, READ_pJRTf;@IE.T_SHARED,
or INVAL.
~1 1 1 1! ; :,. Jj\~jl~~\~f:::::l~\!!!l!l1j\t~~~::t·
SC_ADDR: records physical address bits <39:04> of]0<~ition With. error.

D~a:c:a::h::i::~:~:chine ml/;t:~:~~&ttff?
.&te

•
•

Cannot be retried, but may ~nly ·:~etf.)%9.. d·:il~ft.b.e process if data is
confined to a single process and no sec'<lfil.~j:~xro:t6~~rred.

DCPERR STAT: <DPO> or <Dldjgtj~}iet. ":·~:LOCK> is set. <SEO> is set if

fuere are-mcltiple erro~::r1it~;:_~_~ij:ii_tiii_i>·_·_·::;::·_·--------For multiple parj!y errofsdb:Jhe satriif~f!ycle, the <SEO> bit is not set,
but more than ori.e erir:o.r biFwill..be set.
-:~~j~~l~~~~~~~=:::::..

··::::::~~tI~~~~:~::::..

"::\:}}:...

•
•

··:·:===~W~I~~~~~~:::-

··::<:tji~:tt::.;.

;;~~~t,~'a::::~:::::a:: ::~::~n causffig
:fuer instruction in same cycle may be lost.

Fa~•:~ml~1fji1%f

8-4 Preliminary Edition-September 1994

8.1.7

D~ac~::=~ c:::~c=:~~achine
•

state may have changed.

'®'

~~;eE:-::~l~~;:r <rPl>~::et. <LOCK> is :;~;~-l\~

~~~ :::~:!:?e:~::i~::~.cycle, ti"1j~~~;\¢ set,
•

VA: Contains the virtual address

• :::STAT

locked. Contents

ofthe,£!).l~'~loU~ord) with the

#Jwtairi',ma:~~~:struction causing

parity error. <WR> bit is set ff' e!wQr oceift~,~ on a store instruction.

------------~····~··.··==:~!li~t~::::::~···,-.· : : :_.~\_t~ -~l_: ·- - - - - - - - -

Fault information on anotJi.'f~~~~~~t~t~:~~j~m~~'the same cycle may be lost.
..·:·:::::::::Jl.

•

Probably will,. not

....::::tt~~t::::...

bEJoJ1:::*~r. ~,,:eleting a single process, because

exact addregi}Js unldiijttn~. and ~t1Mid may have falsely hit.

UndQrr~ctl1'=ttt.~~6jff~Rr Data Parity Errors (Bcache or
<ttfl\t~tt.~"%\"(')· · · · ·

8.1.8 lstream
Memory)
•
•

•
..-:·:·: : : : : :.:. .

Machin~:J~h!:·~*·..ocdifj~J.~.efore the instruction causing the error is executed.

Bad qi~~==·;;t!llb~/W.ri~tl~ to the Icache or Icache refill buffer and validated.

C~p Jll!~r~tff~~ if:lere are no multiple errors.

• . J~l~t ~alii~i~J.~'-@{~~~=~o remove bad data. The Icache refill buffer may be
·::::~=f[JB.ped by executing enough instructions to fill the refill buffer with new

+f,ffeiiitf' :;~1re:::~~;~~-:i:fii:~e::;:::i:~~ is set if there are
4Htb==··

. tt~r== multiple errors.

····~,,\~\. . ~!~:~T: <El_ES> is set if source of fill data is memory/system; clear if
"e:t{WEI_STAT: <FIL_IRD> is set.

Preliminary Edition-September 1994 8-5

•
•

•

EI_ADDR: Contains the physical address bits <39:04> of the octawgt!i
associated with the error.
·=:ti\.

failingJ!~.taw=~lf.h:.
:~;:~::;::::;:n: :~::::::::;::~~Jf:1!~4!!ltr+
FILL_SYN: Contains syndrome bits associated with the

"'~lf~~l.l.r_.:.:=:·:_.=':_:=·:.:_.=:_=·.=.:·.=.=.'=.:==·

was enabled for this transaction.

. /Jflll~lt::,. .

- - - - - - - - - - - - Note

~lib:· P.JJJ~ai~m@~;:~e

If the Istream ECC or parity error occurs early in
at the machine check entry point, an infinite loop miiy .:t~ult.I\l'::::::::::··
.·.·:·=·=====·=·:·.
~;mnt . A~mr

•

Recommendation: On data ECC/parity

~~~t:~;*~!::ble for

the operating system to "flush" tb.~, bloctitiil~data out "6lHhe Bcache by
requesting a block of data with tlii· SJ;~~me :BMiih~,. index, but a different tag.
If the requested block is loaded with "=MUP.:.r:pbleffii.kt:hen the "bad data" has
been replaced. If the "bad data~·==:~:::markhll1Wf.ty, "then when the new data
tries to replace the old data, anit1i~W\ICC/p:£fjt:y error may result during
the write-back (this is a reaso.ifnot to==::ithw.pf°this in PALcode, because a
MCHK from PALcode is ahvi#:it~f@.~D. ··:·:=\{}=·

8.1.9 Dstream

Memory)
•

Uncorrec;t~ble ,::El~ ~;:tBitt@:::.Parity Errors (Bcache or
•Ah'%.f "~fa, '%1111\Tu;t\h

Machine check~li'-~.µrs:===:11~~JlinEt'S:tate may have changed.

•

Cannot be retr~;J:~lt~~\;.,~:;~~[~ly need to delete the process if data is
confined to ~J~Uml~ :PH~ij,~§~. aild no second error occurred.

•

EI_STAT:.&ilJNc1lbc_:E!t is set; <SEO_HRD_ERR> is set if there are

•

=~•ti:il~~jlet
Bcaeti,.
····:=:=t:tt~trrr··

if source of fill data is memory/system, is clear if

Ai\',f-}~ttl~c=>~:=~;:~cal

.{@?~;;..

·w

:ia~:sociated with the error.

address hits

<39:04> of the octaword

··"\l~l~:~j~~:~~t@::f:l~!~jj~J~ILL_SYN: Contains syndrome bits associated with the failing octaword.
··=·=:'t{{t/fhis register contains byte parity error status if in parity mode.

··====\~lI:j[[jj~~:)=·

8-6 Preliminary Edition-September 1994

•

BC_TAG_ADDR: Holds results of external cache tag probe if ex~!wal cache

•

Machine check occurs before the instruction causing tlu~{ifror is exeeit.19~

Bca::;~:~e::;i:~:::ctil:·ream

8.1.10

•

At·~tt1g1~~!-~.

Bad data may be written to the lcache or Icache refiI{~Bfit.e.r and valid~t'i~

: ~:th:::~~~c~:~:e::v: b::::: e;::~Jt: ~S\ft~==i?ay be ·~tw
1

flushed by executing enough instructions to filVlbe .:f~flll Jl#ff& with new
data (32 instructions). Then flush the Ica~h~ ag8i~fif
. j~f

•

EI_STAT: <BC_TPERR> or <BC_TC_PB.Jl§lllt~\i~t;~~\\~S:id:HRD _ERR> is

:• ~~~:~~~z~~~ ~~:~~;:~:~::>probe. oc~woro
or the

~~:::~~;::R~~o::~~ ::~:t.~~:~che tag

#Ir '"ttltit_,e __________

Bca~ll~ -:~Ii ij\\Jl~~:lis•d

The
based on the tag alone, not the parity bit.
The victiii1i~t_proe~~!4 acC'&#.ijng to the status bits in the tag, ignoring
the controf'H~l~ik,parify.J~:tr.~·o.de can distinguish fatal from nonfatal
occurrences by'\i'ij~~ing':fqr· the case in which a potentially dirty block
is repla~~twit.boliMthtt.victim being properly written back and the case
of fal~~:j:liif\\}j~ri the.lig parity is incorrect.

Jmr

8.1.11 B<;tll:e

. )fr~:::- ·=t~I~t.

li~~'\IErrors-Dstream

,~@f'ii#fff{j,;'!~\;h:::;.::~ :::::;Ys::~d:::i:::::::::ss l da~ is

W-i-lh &.~j ~:tetU:~:is:~~~Po~':: :da~:n~:c:~:;,:r;;~~:.d~:~~!i!s
·.·.:'\tilt::...

processed according to the status bits in the tag, ignoring the control

··::\~fl~t~::::. . field parity. PALcode can distinguish fatal from nonfatal occurrences by

··:::::q~~~~!lehecking for the case in which a potentially dirty block is replaced without

Preliminary Edition-September 1994 8-1

the victim being properly written back and the case of false hit wh~!tthe
tag parity is incorrect.
·\~ll\.
•

EI_STAT: <BC_TPERR> or <BC_TC_PERR> is set; <SEO_HRP.:....E~;tjijlk.

•

EI_STAT: <El_ES> is clear.

•

EI_STAT: <FIL_IRD> is clear.
.

.·~·:·:·:·:·

•
•

8.1.12

BC_TAG_ADDR: Holds results of external cache Uiifl>i:~e.

tr=:=:=:=·=·

~Y::hl~:==~~:~::n~;: =~t:~~~t1MJ1lf
: :~:i;~;!!{AR_ERR> s-·e· · ·t·.· ,;(~s~.~.~.P.=.:·.~:.: ·;·.j·j·:.~.~.i.'.·:·=·.:=r.=·_=:.:'.=:~.:.=.~ :·:~-:~:~:.t%1):
•
•
•

is
.• •:·._.:.·.:ERR
·..=.··:.=.. .
is,:et if there are
EI_STAT: <El_ES> is set.
./~i:::~~~f~l:j:lt::::.
EI_ADDR: Contains the physj'ijijl add~~hb.its <:39:04> of the octaword
associated with the error. l:::j:J:~~~llj:jjj~j:: ~h:::::..
··:·=:t{}:==·

BC_TAG_ADDR: _Holds x~iilts ofi~~*t~r.nal cache tag probe if external cache
was enabled for<tbis traHsihtion.
··:::=tf/

When the 21;!§4·-~etil.~:J:l··~~lffl.@d or address parity error, the command
is unconditioiiliilY:::~OACl@Q......\f}

· =: : :~t:i: : : :th:=:=:·. ·.:,:::::tlt:> Note - - - - - - - - - - For a

SYS9.~~f&;~~e., <::.~:~1:::fatio of 3, if the 21164 detects a system

command{@ddr~~~:=:panty error on a NOP, and immediately receives a

valid . £2nifl.@P.f}from Jite system, then the 21164 may not acknowledge
the d.~ttimaArulT.h.e:·:2~ll64 does take the machine check.
-::~~tI~~:~~I~~:..

···::~:::;t?f~f~~~f::::::··

s.1,iidjt::\\~~-;pperations of the Bcache
t ~j~ ~j~: ~'.: .

Th¢.~j~'h64 does ··~ot check the ECC on outgoing Bcache data. If it is bad, the

···::t{lf:h::..r~i~ng processor will detect it.

<wt'li\wr;r
8-8 Preliminary Edition-September 1994

8.1.14 lstream or Dstream Correctable ECC Error (Bcache or fl.@mory)
•

•

~Jlll\l~ache.

The 21164 hardware corrects the data before filling the Scache
The Dcache is completely invalidated. The data in the Bc~:f.h~:&Qµtil~ the
ECC error, but is scrubbed by PALcode in the correctab1f.iJ~rt(fF~~·P.t
routine. (Using LDxL, STxC. If the STxC fails, the loc3t~i.h can be·--a:~=~ttme.d
to be scrubbed.)
-::::~=~tilllll!~\[\tt::-.
: :'.;j j j j !j!
A separately maskable correctable error interruptd~i.¢.µrs aFlft.:b:. 31 (sa:rriff
as machine check). (Masked by clearing ICSR-c;;Q.RD.E?:~lh:':-. ·-:·\@/

:::~~==~:5:~~:::;s::am~~!~,;'~'®lf

: ;:;~;~~;:e:;:~~~~~,;:::;:: :~~::::·
•

FILL_SYN: Contains

synddt~~f~ltti.t.~ ··:;~!it@te~ with the octaword

• ;~:;::~:=~i~~!Jae:,on cor ectable er ors).

There wUlJ>::::~~eftq~-~j~~\~q~grad~tion in systems when extremely
high ratel~i@f~=~~rre:et@b!~ ECt%~rrors are present due to the internal
handling oftlitl.t~rror::={Qb~Jmplementation utilizes a replay trap and
automatic Dcaclieml.m:sh Hflf)revent use of the incorrect data) .

. ::::t~~~rmimt~;~:~::::=:-. ··::::::;~~~~~t~;;;:=:==··
. /ff · ·
·-: : : :·

:1~~llljjj~r-

lJ~EfllJJ.lill\fp;:~-ERROR~H)
• _./tff: sy:!l~~Wtt~WK~-ch fill timeout can occur, the system environment should

8.1.15 Fill

.-:-: : : : : : : : : : :-:-. ·-:::=fti.i.twt fill timeout and cleanly terminate the reference to 21164. If the
_.Ji!]~11f}:{{i\l!h. syS~d~nvironment expects fill timeout to occur, it should detect them.

i\fV' 4,ll ~;~~~?c=s:~n~~': ~:sli;:!fy'~i!::t ~r: i:~:~l :i~:e:~!ied

·-:-:::(i1~@t\.....Ail}:::· eventually detect a stall if a fill fails to occur. To properly terminate a
·-::::::~\{~l]f':-fill in an error case, the fill_error_h pin is asserted for one cycle and the
·-::::\1~]~~1\::::.. normal fill sequence involving the fill_h, fill_id_h, and dack_h pins is
··-::ttll~:generated by the system environment.
····:::··

Preliminary Edition-September 1994 8-9

•

A :fill_error_h assertion forces a PALcode trap to the MCHK entry J)pint,
but has no other effect.
·::WJ\.

No internal status is saved to sho:O:at this happened.

I(,;;;:~~i~

systems must save this status, and Include read operatioqld.~f the

appropriate status registers in the MCHK PALcode.

8 1 16
. .

.-;~·:::~(@~~~~~~\:::.

··.··:::{lt

· : t i~ ~ ~ ~ ~=.: _;=.:=.t: .: :_: : _: ·: _: : .: : ·:·:·.: :.· .

:::::::::~:::le machlne Check ~'!:~il~:~ed by
•:~~~::;i:~::~e.
·01~\14i\l{_:+_
system environments to signal fatal error~tUfifliii.hn.ot ":MWfotly connected
to a read access from the 21164. ~t is m.~K~d at IPU~~Bl:. and anytime the

t\p "''

"%{~\t\f4\)>

8 1 17 lbox Timeout
. .

•
•

•

"'W'

::i: :;;,~ox detects a. 4l~(~~:~~ti PAI.code trap 00 the MCHK
Simultaneously, Jl parti~ldb.ternal ··:t~~~t.. occurs: most states except IPR
state is reset. TIU§ s}lou1iflnQt.. be depM1ded on by systems in which fill
timeouts OCCY.f)n t~i~J US·~:::(~~p as, Operating system Or console code
probing locatMh~ttP d~t~rmJne If\t~rtain hardware is present). The purpose
of this error det~it:~P.:!l me~h~i-~m is to attempt to prevent system hang in
order to write a ma~hine.. cheHlfstack frame.
ICPERR sTAT~@QpM~;::::\~~:~~~~et.

anJllllLot:ill:~it!:l!ll~h . .
• Asd~n ·:1~;f' asysclk cycle in whiCh cack.)i is not asserted

8.1.18 cfail h

. . : : : : : : : : : :·.·. cads'-i~:P.ie 21164'.lo immediately execute a partial internal reset.
::fi~\11\\~\1~~~:i;::t:l~4.Lc~:d:i~~lf P. to the MCHK entry point.

(4;J!tfa:%,f1:1::::~~}y, apartial internal reset occurs: most states except IPR
'"W;~'-~\;ERR_STAT: <TMR>

is set.

8-1 O Preliminary Edition-September 1994

<i~_:j:_;jl f~i

•

This can be used to restore 21164 and the external environmenK:to a
consistent state after the external environment detects a commiffid. or

address parity error.

+:;t)\~illiH&~~\\1

Note .

4~h/no ~::~1j:!1:111::it.

There is no internal status saved to differentiate the
case from the timeout reset case. If necessary, systems rii~t:. save this .JHf
status, and include read operations of the approprj@µh.~tatlls@~gisters ": :;: :;: :

: i: ! ! lj:~r: : ·'"· ·: : :.:1·1.: j:l lj:l l: : : l: : :~: : ,:,: :;.;: , : t: : ·

in the MCHK PALcode.

·=t~~lf::· ,':~-.:~:_,~:l-~_,~·.l,:_,:_,;·_,i:_,:,~=.:.:·
8 2
"

M~~ol~~~

recomiq~nded J:~:~::,,

I~~J:::::::=:==··

'WW±f/;J.W

flow is the
source of a machine check.

·' \@?

. :,::::::1::1h:,,..

to determine the

..,,:.

b~dt~lta:J>:::::f.am

•

Must flush Icache to remove
errors. The Icache refill
buffer may be flushed by ex~gqt:tµg . ~ifi~}!gJi i~~tructions to fill the refill
buffer with new data (32 iqjffrli~tttns). "Ti\~Jl flush the !cache again.

•
•

•

Read EXC_ADDR.
IfEXC ADDR=PAL th~n haltf\::.
..
Lhtt
. :,'?ft::::...
Issue MB to:::ijJ.ear outtllb~x/Cbo:it'before reading Cbox registers or issuing
DC_FL~,~~:....,. ·:tttlt:::::. "::::::t:llll:lit:::::.
Flush Dc~icn~t:to remiv~.. ba&=tlata on Dstream errors.

•

Read IlCPERR STAT.

•

t}i&l~b. '%~-lf}!> ,

:::: ~;~~1,~;;~~!}
:

. ::::::f\Hi:::t:::..

41~~~~!encies

or MB to ensure read operation of SC_ADDR
HrtQb.~s before subsequent read operation of SC_STAT.

. :::fll!!~::~?:::·:.........:,:,'tli!!!t Re~d:~:§QiSTAT (unlocks SC_ADDR).
(j::!:l!l!:t:::::.

..t:llfj}' Read E~=~DR, BC_TAG_ADDR, and FILL_SYN.

. : : =t: ~l l l: : :l l lJl l:! l! lW: '~ Use register dependencies or MB to ensure read operations of EI_ADDR,
"':'?lfh:-:.. BC_TAG_ADDR, and FILL_SYN finish before subsequent read operation of
. ,.,,,{qj:::lll:,EI_STAT.
•

Read EI_STAT and save (unlocks EI_ADDR, BC_TAG_ADDR, FILL_SYN).
Preliminary Edition-September 1994 8-11

: ~::kE:a~::s::c:::::e:~e:'.1 :::· o~:c:::ae;:l:wing al~e,
./~~lK::::====·=···· "\{~~\\.

then skip retry:

=~=~:::~RR>

+\(~~:::!@;il\

:~:::~:~:::and not EUTAT':l)j''

SC_STAT<SC_SCND_ERR>
SC_STAT<SC_TPERR>
ICPERR_STAT<TMR>

•

.{~~~t:·

n~:::M~::revious conJ~ :~:~,!then there is either an that
1

IRD

•;~;~~~!~~~;~~~;:::
:f:::~~::t::e(:d
:d
EI_STAT;dNQilt;~"(~=k~
EI_STAT<FIL_IRD>
SC_STAT::~S.C.--~pjjBR?' ·:d (SC_STAT<CMD> = IRD)

~~:(~!ftl
• UnJpfl the ·roUq~id~~~lPRs:

ttl(~:::~~;~i~~~~O:re Wready nnlocked.
' %\,,}Read

EXC_SUM.

8-12 Preliminary Edition-September 1994

Check for arithmetic errors and handle according to operati:qg:systemspecific requirements.
\tIL.

• Rep~;:::~:::_:~::::~-=~~ccording to~,~\-

8.3 Pro;;:::~:~:::::~le Error Interrupt ~,~~,,.~l)~w:?t
The following flow is the recommended way to rep.~ff:::~~;Jiijll~l~ _ ;;;~rs:

: =~I::i:::hFI:~;;;.~outine becaus.\s(j\1[
set.
1
• Use register dependencies or to &?! ~\~gp,erations of

MB
EI_ADDR
and FILL_SYN finish before .::$.\U>seqtt~i1hread opefiiji·on of EI_STAT.

•
•

Read EI_STAT. (Unlocks EI_S~A'id~~~~lfilJB.~,. and FILL_SYN.)

Scrub the memory location byJ!§~~imEQ~L/s¥Q_c to one of the quadwords
in each octaword of the Bc~jii:~~&l9J~;k W-Hij~,. address is reported in EI_
ADDR. No need to scrub IiQ. spacMi.ddress'~s as these are noncacheable.
ACK the CRD lnterruP.tJByjjj!fai.ting ~=::ift''.to HWINT_CLR<CRDC>.

No need to tij!Jock an~!llkegis~:;;~~:,~yiuse conditions that would cause a lock
would also didse .a MORK VA witFnot be locked because DTB MISS and
FAULT :e.ALcodeifQytin~'~:~~WUlnot ever be interrupted.
-

• ::c:!!~!'~le
....,:,:::::::::::::::::::,:,.... -·-:=t t.r.~.~=~=~·,:,~,:·,=.'.·'.=':=,·
./:J?========:=:=::tflt==

MCHK

according operating-system-

Note _ _ _ _ _ _ _ _ _ __

~l~d 1f§T'1

..........

Only
once in the CRD flow, and then only if ISR<CRD>
i~d~~t.\jf:::t#funcq~ctable error were to occur just after a second read
A~~ratiO'ifff:P:mtP~STAT was issued, then there could be a race between
·=ttu.i~:}mlocklng'=-0-r the register and the loading of the new error status,

Preliminary Edition-September 1994 8-13

M~K=:::~::;'::rrupt routine because
•

ISR<MCK>

bi~ set. ''~
..

Report the system-uncorrectable MCHK according to operatjn:~i91tlm~:~:'.!!!l!l!l[iit,:

8-14 Preliminary Edition-September 1994

•

Electrical characteristics

•

de characteristics

•

ac characteristics

•

Power supply considerations

{i\-,,,)'

9.1 Electrical Characteristil!%Wilw%,yih

::::: li:::~~:(~~·:.::s
Ratings

Storage temper~t~}t:...

··::::::~llltt:::.

-55°C to 125°C (-67°F to 257°F)

~::~;::,~~%~~~,~VF

Vss -0.5 V, Vdd 3.6 V

Input or otfimt ~@liecf}k

3.3 v to 5.5 v

~:t:'C~SP45 v

15°C to 85°C (59°F to 185°F)

TBD W typical
TBD W maximum

Preliminary Edition-September 1994 9-1

9.2 de Characteristics
The 21164 is designed to run in a CMOS/TTL environment.
tested and characterized in a CMOS environment.

921
"" Pi~s~~!~~e

connected ro 0.0 V, and the Vdd

ln:e~!l:i~~=P=:~:,als are

92 2
. .

pins are co~,,:.3

CMOS inputs J*j!\fiL

ordinary
levels (see Table 9-2). (See Section 9.3.2 for a des¢.pifon J~f· an •eption-

°~!~=:~!:acy cMdi)oqtp:1C:~~~::~,:~als are

9"2"3

3.3-V

rail-to-rail, timing is specified to standaftf!~WTL I~v41*-~:::.

Bidirectional pins are either input Q!\gµt.p~f::~~~mh~~~~~ding on control timing.
When functioning as output pins, tg~j?iff:~wrdiiiii:j:· 3.3-V CMOS outputs.

inil\.

After power has been applied,
and b~:fil~µo~al pins can be driven to a
maximum de voltage of 6.3 V,(f~:g::::Vt(4.r:.,. 1 ns) Without harming the 21164. (It is
not necessary to use .~tatic . s with\ij\~3:::Y outputs.)
Table 9-2 shows th~:\~tji\ims·::dfl::~pµt and::::dhtput pins.
Table 9-2 CMOS DC

c.i:!:~~t\~~:~\t~~}
··'c:&;~'ftq.;.~Uirements

Parameter
Symbol

Description

J::~~:rr:::::::::::::'.:'.;:li!!!!!J} ,::::.

vi,,,

High-leV'iflnputWib~-~::J:f:? 2.0

.•.••·.·•·.·•

...·...

Vil

::/t~~~fai~-IJ~i!!~~g~~t v~l=~~::;:::::·:··

;:i:iff¥''3::~r:3~~=e
::tl:lt\L..

Max.

.fiJr

0.8
2.4
0.4

Units

v
v
v
v

Test Conditions

f ok = --8.0 mA
fol= 12.0 mA

Power/Leakage
-50

9-2 Preliminary Edition-September 1994

µA

--0.5 V < Vin < 5.5 V

Most pins have low current pull-down devices. On most pins the paj}::;down is
to Vss. However, two pins have the bleeder to pull up to Vdd. The bt@~pers are
always enabled, even when a pin is in the high-impedance state. Thi~~l:luM~ans
that some current will flow from the 21164 (if the pin has a pl@.lf::im.J~le=~g~r)
or into the 21164 (if the pin has a pull-down device) even wh:¢ri"'"liUMiitkl~flh.
driven to the high-impedance state. The pull-up sources :\:&dl:P.A max frofiltV.49
through the signal pin when the pin is at 2.4 V. The pull~diWQ}levice sinks :::ijl1~
least 10 µA from the signal pin to Vss when the pin i~.J!t.. 0.4 ··VJ:::t1h:=:·.
·={ff

All pins have pull-down devices, except for the pin1"'f!j~_;~lable: .
Signal Name

Notes

tms_h
tdi_h
osc_clk_in_h
osc_clk_in_l
temp_sense
:::::::::::::::::::::::::::::::...

··:·:::t~~t~::::=:·

~~;::::;~r~~!;~~!~:o: :: :~r:1164.

93
• ac

Timmg
parameters are gi\reQ:Jor tH~{bwninal .speed 21164 operating at an internal
frequency of=~A. MHiU1~4 ns)9:~~~~::11\.

9.3.1 Clocking Sc~:iff«:::~~:\. · = = ={t~l l~[~l:l:~ )t:,. · : : : : :-

The differe9Ji~kiP:P~f~:::i@!k ~i~als osc_clk_in_h,l run at two times the
internal ftt&U:eH~y~~~pf _thtttihie base for the 21164. Input clocks are divided
by two o:ri.N:hip . t&::~geri.trate a 50% duty cycle clock for internal distribution.
Signaj~ 0$@~~~)n_ij3 are delayed by some propagation delay and have no
relati@p to ===aqt.P.vtJ~~j@fal cpu_clk_out_h.
..·=·=·===========·=···

Sy~:iijlt~esi~:~;~~::~;~e a choice of two system clocking schemes to run the

::::~es out a
4{il:If:=:·.4,,fi%lt\\1~:!\tn;:e:~:e
/:::i:ift
··====~=~:t~~lt:~~::::::. .J:~:It==··

sys_clk_outUi,l.

sysOOm clock,
It
runs synchronous to the internal clock at a selected ratio of the internal
clock frequency. There is a small clock skew between the internal clock and

·'iIJ%\'qtysys_clk_out1Ji,l.

Preliminary Edition-September 1994 9-3

2. The 21164 synchronizes to a system clock, ref_clk_in_h, supplied Ql':::
the system. The ref_clk_in_h clock runs at a selected ratio of the 21.[l§4
internal clock frequency. The reference clock is synchronized to the iritlµal
clock by an on-chip digital phase-locked loop (DPLL).
./[l\t:::::::,.,... \[~[}\

9.3.2

·~~:!::~::::re:::::::_:: ::~t~::~~~;;::tmtl~-i
chip when dc_ok_h is asserted. These pins are self-~i.lilng;::[i.@'-::Jnust=~~be
capacitively coupled to the clock source on the moduI~Ibr tl\~y cii[[b.i.Mirectly
driven. The terminations on these signals are designeaft~o :~:' con\pillible with
system oscillators of arbitrary de bias. The oscilJ.@tP.:f::. mustI@@:Y..~=~~~:ilduty cycle
of 60%/40% or tighter. Figure 9-1 shows the i@pttf=fi~tw2r1t===iitt=~the schematic
equivalent of osc_clk_in_h,l terminations. ..::::,JI:
··:·:=tt~~l~\:. .

Figure 9-1 osc_clk_ln_h,l Input Network

Module Circuitry

osc_clk_in_h

a~~~.:::•h" ''\¥

o~:ChiP c~~-!~-,~~~\~,4~:=~ ------.

*~~~~~~.~i--::DHUl.alt&J~~~~~--i--+
Jf\..
n'f'
A~::\. I

Vi!\'\}{Wt

\~ilk ''

~~?u~or ~::~f:::i:::
&#ifit\ff;tt,;;.~,l_J

3 .3 pF

\$5

3.3 pF

50 Q

o~~~al
oo n

~Plfi~

"i'""

: .:.:·,:_:=:~: _·,~_:[~,:_:[l,[:=-~-~l~Njfo·=te:

}}}

,::Jl[}/

··::\{_:i.[l_.>

6 nH
•------------------------------

"''%('''(~::::::: :::::P:e internal ring oscillator when the 21164~::ing
offt··~[j~scillator, just as they would when an external clock. is applied. The
frequehcy of the ring oscillator varies from chip to chip within a range of

9-4 Preliminary Edition-September 1994

10 MHz to 100 MHz. This corresponds to an internal CPU clock fr~µency
range of 5 MHz to 50 MHz. When signal dc_ok_h is deasserted, th~1\~\~ystem
clock divisor is forced to 8, and the sys_clk_out2 delay is forced to 3 . .\\]b.

A special on-chip circuit monitors the osc_clk_in pins and d~~i~~lwb:lll~t\
input clocks are not present. When activated, this circuit s-W.ltches...thi¥121Ui!.
clock generator from the osc_clk_in pins to the internal ·tipg}>scillator. THi~~},_
happens independently of the state of the dc_ok_h pin. The{®....ok_h pin Jif
functions normally if clocks are present on the osc_~J.MlliP. pin·~=J{\f\,,..
''\=:/

1i7r '::Jff.1t,]bf.;;+P

9.3.2.1 Clock Tennination and Impedance Levels
In Figure 9-1, the clock is designed to approximaijpa ij(fD t0:flriination for
the purpose of impedance matching for those.. ,.§y~tems tfi~t q.jfe input clocks
across long traces. The clock input pins apP.@tF1fi~dil 50¥1.t~ifies termination
resistor connected to a high impedance v:~\f.lge sdttt@.~:-. The voltage source
produces a nominal voltage valu~\Qf v ddft~l~1'he sout~\\}las an impedance of
a few thousand ohms. This volta~' i~:}!alM=aI~tb.:~ self-bias voltage and sources
current when the applied voltage at 't1U.~:M;locltiijpyt pins is less than the selfbias voltage. It sinks current wh.~.n..th(:t=ippJ!ed ~Mtage exceeds the self-bias
voltage. This high impedance b.:mM~v.~r 8'.11i.w§. a clock source of arbitrary de
bias to be ac coupled to the 2~j~4. TKi:}p~ak:tS~peak amplitude of the clock
source must be between 0.§jM\iP.:d 3.0 v:=:::•tth.er a square-wave or a sinusoidal
source may be used. Full~f~HfHijD.~. may
driven by testers. In any case, the
oscillator should _ pe ac ~mJ.p,led to..'.tl~mw~c_clk_in_h,l inputs by 4 7 pF through

'.'·&·'·'.·'.·~.:~.1.:·

· :.,.=_=.~.~.:.~.:.=_,~.~.~.@\-.:~.-1.',,:1,_~,:~· , , \~?

220 pF capacit·o····r.····.'.
. ,::=:::... · · ·.
.'=_.'.·'.,'.·,:.·.:·.'·..·'··.'.·'·' .
9.3.2.2 ac Coupling <ltt::::.. "'''\l{~~~~}J,,,.,.
using series coupligg (blooi.iqg) capacitors renders the 21164 clock input pins
insensitive to the 6i@U.~tor'~t@,c level. When connected this way, oscillators
with any d~A~tf.$~t,::r.efatl!t.::.to Vss can be used provided they can drive a signal
into the ~:cikjjjt_~,l ·phis with a peak-to-peak level of at least 600 mV, but

:~;:•t•~~l:~ca::;:·

critical.

is not overly
However, it should be
suQ!gfntly 18w~~\imt¥.ilance at the clock frequency so that the oscillator's output
. . , , , : : : : : ,:,. ._sigrl~~lMwhen measured at the osc_c1k_in_h,1 pins) is not attenuated below
,i1lf?=tf{th~ 6dtHmY. peak-to-peak lower limit. For sine waves or oscillators producing
. ,J~l]f:..
"l~i~rly sfritiig,idal (pseudo square wave) outputs, 220 pF is recommended at
,,,J\\1?
. ,:#.$0 MHz. .khigh quality dielectric such as NPO is required to avoid dielectric

'Z1\l,}4·~:es.
···:··

Preliminary Edition-September 1994 9-5

Table 9~ shows the input clock specification.

Table 9-3 Input Clock Specification
Signal Parameter

osc_clk_in_h,l symmetry
osc_clk_in_h,I minimum voltage
osc_clk_in_h,l Z input

:::::::::::.

9.3.3

:·:::·:::

S!!~~i~:1~:: ~~ec~~b~la(~~~:~:: the
All output signals are TTL compatible.

'tl[l[~jjj~jlh:\. ··:::'\l[l[[j~~j~j:Ih::·

_.,::f?tt:,.,.. . · : : : q[j [j~j.~;_.=,'=~.'~.~- .'~.'~.
9.3.4 Backup Cache Loop Tl.m1·ng .AF?'::::::::?fit::

,==..'.·''.,':,·:,·:··'··_,,.

··=:·

The 21164 can be configured to . :.§Jj~ort ;Atii.tipnal off-chip backup cache
(Bcache). Private Bcache readd~f.I(idite (Scach~P~ictims) transactions initiated
by the 21164 are independ~;q~jjjpf th~==~=ifikm clocking scheme. Bcache loop
timing must be an inwger iiultiple of tRM[JU64 cycle time.
Table 9-4 lists tb.~t.~~~c.~49.~;:~~tltiing.

·.·

Signal

Value

Table 9--4 Bcac::1~,;~;~l1i<t}
Name

Tdsu
Tdh
Tiod
Tioh
Tdod
Tdoh

9-6 Preliminary Edition-September 1994

Outgoing Bcache index and data signals are driven off the internal .¢\pck edge
and the incoming Bcache tag and data signals are latched on the saM.i~::~ntemal
clock edge. Table 9--5 shows the output driver characteristics.
··=:~~t:l:\h:
·===~~~t@t~:::::::::·.:·

,.;. Itr

Table 9-5 Output Driver Characteristics
Specification

40 pf Load

Maximum driver delay

2.6 ns

Minimum driver delay

1.0 ns

·:::::::::::::.

==:=: :·=· ··-:-.,: := = :r~ ~ l\ \ \ \ ti;:.~1 .:!_:!:.: .:-.r_: _:·_:.:._t.~.~-~-~:_._=.··

~a~:u~~i~~:'1!!~ ::~~::::~:!e!:;G~1rii&~l~1!1:a::i;~rive

higher loads provided the average chargingfor drnib~lrgifl'g===~-Urrent from each
pin is 10 mA or less. The followi;p.g eq~t\=jp can b~::::Ull¢..d to determine the
maximum capacitance that can ~\\:safely. :=&ij&~P by eaclfpin:
Cmaz (in pF)

=3t, where t is the·=~W:it~fo;~\::~9d (measured from rising to

rising or falling to falling edg~~~An ii'Mlh~.~onCik
For example, if the waveform i!~~~~~}.i~J>~:::::~\\:~ven 110 pin has a 20.4-ns
period, it can safely drive upjgfamd incftigmg 61 pF.
Figure 9-2 shows the Bc~~1:=~=~~~R@);tpd w~i:· timing.

~.~:_.j_"'filt \i

·Slit · . )%i\\1\i1.

4
(
t
[
j
,
l
\
t
_
:
~
.
~
.
:
.
~
.
~
=
'
·
:
~
.
:
·
=
.
:
=
:
·
'
.
:
·
.
:
=
_
"11\\;qi_Jl_llJi·

'\lliL.

:. : ·:·,:·

ti:;;~::;,
il(C~m''*
··:==:~:rr·

Preliminary Edition-September 1994 9-7

Figure 9-2 Bcache Timing
Bcache Loop (Read)

CPU Clock

DataOut~~~~~-~-~~~--~~~~:~~~v~~<~m~~~J~~--'~:t~~~~~h--~~~-+-~~~~~~::::::..~~~:---~~~
·•·..

41
.3. .

'"!;V .(f<t,..

-~,~~le

~:'';!S::~~;:;~ltk

LJ-0"409-rn

sys_clk...outl_h,1 output timing. All
timing is sho~HB?&iroµncti6~j~j:with the rising edge of the internal CPU clock.
This allows t@if setq:p~~~ln:4~J10Id" times to be specified independent of the
relative c~paqtjy~Mliildirig\l\9f sys_clk_outl_h,l, addr_h<39:4>,
data_h~07:0>:Hi6d c:rqft[h<3:0> signals. The ref_clk_in_h signal must be
tied to.::X'.4if for :PK.P:tdlilforation.

''\lf\\'11~\p

9-8 Preliminary Edition-September 1994

Table 9-6 Alpha 21164 System Clock Output Timing (sysclk=T0)

-:=:j[!l}::..

Signal

Specification

Value

sys_clk_outl

Output delay

Tdd

sys_clk_outl_h,l

Minimum output delay

Tm.dd

data_bus_req_h,
data_h<127:0>,
addr_h<39:4>

Input setup

1.1 ns

data_bus_req_h,
data_h<127:0>,
addr_h<39:4>

Input hold

0 ns

addr_h<39:4>

Output delay

Taod

addr_h<39:4>

Output hold time

Taoh

data_h<127:0>

Output delay . : :...

Tdod2

data_h<127:0>

Output hold

iJfil\ Ai&+..

Tdoh2

Tabrsu
Tabrh
Tntacksu
Tntcacksu
Tntackh
"==:==tt\...

··::::::~=~=t~::::..•

· = = : q·~-~-~=r: .: : =:.·..=_= = .=.· =·. =·.=: : .

3
··=Ti·:"urbo Mode

1.1 ns

Ttacksu

0 ns

Ttackh

1 The. iIDhe o:¥¥1M~w.d~~~for on-chip driver delay and clock skew.

2 Fc>f~j~i.~j~rite tr~Jiaifiri~ initiated by the 21164, data is driven one CPU cycle later.

Allure ~'''!~ws

sys_clk system timing.

===t~~r:::··

. :·::::~t~~~~~~~::.

Preliminary Edition-September 1994 9-9

Figure 9-3 sys_clk System Timing

Relationship of CPU Clock and sys_clk_out1

Memory Read (Turbo Mode)

CPU Clock

dack
Data In

------------11

: ~l:l:~l~: :l:fil~:1:i: :1:1:1:i: :1~r: i: :1:1:~rJ.:l: t.J.:?.l:l*l:M:~: l*: ~:~l=fil~ =l~=l~$.;,:~?.l~ i;~i~; ; ; .;~ ~li ~ ~i~i1;i ~i~: :;~:l:~ :l:l?l:l:=:~:i: :i:~ =~ : l:fil:j:

CPU Clock

Tntackh
LJ-03410-TIO

9-1 O Preliminary Edition-September 1994

9.3.4.2

~~:=~:::~~;:erate their own system clock expect the 21164 to ~·ronize
its sys_clk_outl_h,l outputs to their system clock. The 21164. uses 2{4.jgital
phase-locked loop (DPLL) to synchronize its sys_clk_outl s.i~!il~~A9.:...tH~tt.
1

:~:p~c:c~:::sr:::~:: ::~=~~:o::; ~l~L~;:·c;:::''''1k
.ill

than the clock that is applied to the ref_clk_in_h signal. Ph~~tJocking is
accomplished as follows. The internal CPU clock is f900@.JJ0 sbin:::t.:o.r. one phii~e
whenever the rising edge of ref_clk_in_h occurs jµiFbef9.tiMID.e ri"sihg edge of
the internal CPU clock that triggers the rising edg~[.of sy,:_~-].qptl_h.

;;~:iti:~.ws all timing in conjunctio:,/\li;i~~:~~l~;i;~f'
Table 9-7 Alpha 21164 Referenqe:~:Cloc1flf@.8H~ Timing'':\/
Signal

Name

Specification

Tdsu

Tsdadh

Traod
Traoh
Trdod2
Trdoh2
Non-Turbo Mode

1.Jf'.. ·rijput setup

addr_bus!hq....

Afli\f1iMti~t~~~tMffi~l:: :::

3.8 ns

::;

::cle

Tntrabrsu

::::u

./ff/

}$he value 0.9 ii.s accounts for on-chip skews that include 0.4 ns for driver delay and clock skew,
.iJµid phase detector skews due to circuit delay (0.2 ns) and delay in ref_clk_in_h due to the
··:::::{{\:,.,..../}{package (0.3 ns).
·.:,::::t::{~i1:i~if·: 2 For all write transactions initiated by the 21164, data is driven one CPU cycle later.

''\fk~\...

' \l\\1i!(t\[i••

(continued on next page)

Preliminary Edition-September 1994 9-11

{~~j~~~~h.

Table 9-7 (Cont.) Alpha 21164 Reference Clock Input Timing
Signal

Specification

Value

Non-Turbo Mode

cack_h,dack_h

Input hold

(0.5 x Tcycle)

®.! ~ -.: :~:;.:;· ':~_.:;~:.·__.:~.-.=1:·.1 .:·.~_::_.:~.:j:_j
··:::\j~~~\\~j~ht:...

Turbo Mode 3

addr_bus_req_h,
cack_h,dack_h

Input setup

1.1 ns

addr_bus_req_h,
cack_h,dack_h

Input hold

0.5 x Tcycle

9-12 Preliminary Edition-September 1994

:i:J.._
...

.J~h.

9.3.4.3 Digital Phase Locked Loop

Figure 9-4 and Table 9-8 describe the digital phase-locked loop (DP~Bl stages

:::~~=n.

;'-1,l~\tz~fyt~\{)f!tl®@\il;¥i,{_·.!·!.= .'i·i· ·:·:':·,··~::····:~·:~_:.'~
1

ref_elk System Timing

. .. . . .·::.···:···.':'_:.=._.=. =.·

Relationship of CPU Clock and ref_clk_in

CPU Clock
ref_clk_

CPU Clock
ref_clk_in

LJ-034 11-TIO

Preliminary Edition-September 1994 9-13

Table 9-8 ref_elk System Timing Stages
Stage

•
•
•

Description

The internal CPU clock rising edge coincides with the risip.gl[iWm:Ji.... \tl[[h.
ref_clk_in_h.
.·. :j j j j }" ··.··:·::::::t\fl~\[[[;[;jjjjjjjjjjjj[j[\.
The DPLL causes the internal CPU clock to stretch for.:4.Wftphase (1 cycle. . \lt\.
of osc_clk_in_h,l).
····::qt;ll\~lllt::..
. : : \lj j j l:
The stretch causes ref_clk_in_h to lead the inteD~bC.:PU cl&\H.~·Y. one
· : : : : :·
phase.
.J[;j!ll[J::::,:-:-::::::~:111\llllt~:~::::.. ··::\~{}
The CPU clock is always slightly faster than tliii:exte.d..lriJL.~-in_h
and gains on ref_clk_in_h over time. Eventual}y· tqj:Jiain liifils one
phase and a new stretch phase follows. .·: : : : : : : : : :·:·. · ~llllL. ../~ll~:

ref_clk_in.Jlit!'::;t• .;;_;~outl_h,l,

Although systems that supply a
a relationship between the two sigm~}§:, exisf;~mb.§.~ as in ilit{sys_clk-based
systems, because the 21164 uses sys_:cu149ud!filA:ntemally to determine

" f:i.Jl.\i!Jj_[;_~:.: :.i_:~:.:·_.::_:_.:_:':._·:.•._:.'._:.'_. :~:~.:l t:·
./l[fllht::

timing during system transactions.

9.3.4.4 Timing-Additional Signals

::=_:=
. . .:=
__.'__=..

:n::::::~t:n:::~g::~f~iC~;:~\tt,
1

~~=;g ~t~;:!~~!':o~J kput s~:on_h
is

sys_mcb,_chk_ir~blb~,. ··~r-i(Jrq_h

MlscellaneoJt:~?t{

mch_hlt_jrq_h

Table 9-aj[;.nJWiiiJ~ 9~.!Uhist the timing for miscellaneous input-only and
outpukt.UJY sigfi=aIMit~M1Itiming is expressed in nanoseconds.

''1l1('!it~-f'

9-14 Preliminary Edition-September 1994

Table 9-9 Input Timing for sys_clk_out- or ref_clk_in-Based Systems
Value
Signal

cfail_h, fill_h, fill_error_h, fill_id_h,
fill_nocheck_h, idle_bc_h, shared_h,
system_lock_flag_h

Input setup

1.1 ns

Testability pins:
port_mode_h, srom_data_h,
srom_present_l
cfail_h, fill_h, fill_error_h, fill_id_h,
fill_nocheck_h, idle_bc_h, shared_h,
system_lock_flag_h

Input hold

Tsdadh

Testability pins:
port_mode_h, srom_data_h,
srom_present_l

...<$eking

.·:·:·:·:···:·:·:·:·:·

..:::::::::::::::::::::::::::::::..

Signal

Specification

SJ•. .Value
····:·:·:·:·:·:·:·
··:·:·:·:·:··

sy~4#f(_ollHl~~~~t:::.. ref_ci.k_in

Clocking System Name
sys_clk_out

ref_clk_in

Unidirectional Signals

addr_res_h,
int4_valid_h, 1
scache_set_h,
srom_clk_h,
srom_oe_l,
victim_pending_h
addr_res_h,
int4_valid_h, 1
scache_set_h,
srom_clk_h,

Tmdd

... :~ ~! ! !f

;~,~-~~put

dehy

Tdd+Tcyc:le+0.4 ns

Tdd+l.5*Tcycle+0.9 ns

Tdod

Trdod

Tmdd+ T cycle

T mdd + Tcycle

Tdoh

Trdoh

(continued on next page)

Preliminary Edition-September 1994 9-15

Table 9-10 (Cont.) Output Timing for sys_clk_out- or ref_clk_ln-Based Systems.jl\
.
:·:·:·:·:·:·.
Clocking System Value
Specification

sys_clk~out

ref_clk_in

addr_cmd_par_h,
cmd_h,
data_check_li, 1
tag_ctl_par_h,3
tag_dirtyJi,3
tag_shared_h3

Input setup

1.1 ns

addr_cmd_par_h,
cmd_h,
data_check_h, 1
tag_ctl_par_h,3
tag_dirty_h, 3
tag_shared_ha

Input hold

0 ns

Signal
Bidirectional Signals

Input mode:

.{l~~?::

Output mode:
addr_cmd_par_h,
cmd_h,
tag_ctl_par_h, 4
tag_dirty_h,4
tag_shared_h, 4
tag_valid_h4
data_check_h2
addr_cmd_par_h,
cmd_h,
tag_ctl_par_h,4
tag_dirty_h, 4
tag_shared_h, 4
tag_valid_h4
data_check_li2

Tsdadh

Output delay

T..

+0.4

;f,{1~:::!!\i:9

····::ttllll:Jrmdd

&tt*w:~~,~:tir~,;:1r1r;,, ,

Out41;::~o~~l~~jjjjl~l:J;4fTcycle

Taod

Traod

Out~t d~l:q>T~t;:(:~ ::~;~::1.+0.9
Output sM~\\: T:!~lt:L:::::..

T mdd+T cycle

Tdod

Trdod

Taoh

Traoh

Tdoh

Trdoh

4{C::,,,. s~~: in Tahl:'~11 are used to control Bcache data transfers. These signals
..rW driven off the CPU clock. The choice of sys_elk_out or ref_clk_in has no
"::::\ifi!p{).ct on the timing of these signals.

····:=t~~llt

":::::\l\ll~~jj~~j~~~~j}·

9-16 Preliminary Edition-September 1994

Table 9-11 Bcache Control Signal Timing
Specification

Signal

Value
./~~t~~f::::::·::·:·.·.

Input mode:

tag_data_h,tag_data_par_h,
tag_valid_h
tag_data_h,tag_data_par_h,
tag_valid_h

Input setup

1.1 ns

Input hold

0 ns

·=::;:::::::::..

t~: '\'ft\1 1~-_r_i· .:!i.:·.:;_:..'·.·:_j.····'~._·:~_:~_-:~:-_.:=

+%\,ft\1§)

.............
__ ..
::_·
___ ..
__

:=..
,··

Output mode:

data_ram_oe_h, data_ram_we_h,1
tag_ram_oe_h,tag_ram_we_h1
tag_data_h,tag_data_par_h,
tag_valid_h
data_ram_oe_h, data_ram_we_h,1
tag_ram_oe_h, tag_ram_we_h1
tag_data_h,tag_data_par_h,
tag_valid_h

Output delay

Taoh

Outpui~.t.~.r.~.~-.=.=.~.=.=.=.=.·.·. .

Taoh

.-.-:::::::::::=:·:·•

..·:·:=::::i~~t

935
" "
935
" " "1

· ======tI\ }:·

C~:ks~::: ~==s tlm1::: !!~~st modes.
~::•:::~:J.;:~~,lns
:~e
not
asser
W
d,
t
h
e
2>==wm§.
frequency is dividi.td?.Y

osc_clk_in.)i;l
is the normal operational mode of the clock

' W\' ®1'- . ,""

circuitry.
··'·"'"''''"'"···
9.3.5.2 Chip Test .:11:==:=::;:::11!l!l!j~~} J::::

To lower tb~ tWBlmum frequency that the chip manufacturing tester is
requi.t~P ~I'-4'.Pi)ly, ~j\@J.vide-by-1 mode has been designed into the clock
gerw~i.tor d.g(~~W'hen the clk_mode_h<O> signal is asserted and
...........·.. clkfttiib.de_h<t>='==t~fnot asserted, the clock frequency that is applied to the
:dli~Hl}i~JppuC=M~. signals osc_clk_in_h,l bypasses the clock divider and is sent to
.i~lf]~f'
··:::tfi~ chip··:Mi.b.k. driver. ·This allows the chip internal circuitry to be tested at full

,4g~$l~~::d with lfbne-half frequency (up to 294 Mhz) osc_cJk...inJt;I.

Preliminary Edition-September 1994 9-17

9.3.5.3

'::~nle~:s:::::,de_h<O> signal is not asserted and clk_mode_h<l;~\\\,

is asserted, the clock frequency that is applied to the input clock signals.\f~t:.
osc_clk_in_h,l is divided by 4 and is sent to the chip clock driv~.rd\1!.b.~t:diii(i.l
phase-locked loop (DPLL) continues to keep the on-chip sys_ct¥.ioutl!li~l\lil~lh.
locked to ref_clk_in_h within the normal limits if a ref_clk"*JP.[Ji signal i·i;-=:=:::::::~=\I\t:

j·:·}·:·:·.'.Vw.\~.: [:[·: ·=.:·.:=.: _:.=:=.::.·:.·.:.·:._.:·._.:._:..:.

applied (0 ns to 1 osc_clk_in_h,l cycle after ref_clk_in.·:·:--:·:·:h.,.·). ·.;.· · · ·.: ·.: ·:.:·.:

.fi\~~\1\~~j~j~~}}::·:·.

9.3.5.4 Clock Test Reset Mode

When both the clk_mode_h<O> and the clk_mode_~j.-·> sigjiJi.M!!~t asserted,
the sys_clk_out generator circuit is forced to reset td~\ll:::kl\9.ifu ~Q:W.@? This
allows the chip manufacturing tester to synchronize tlfo. clfip to ti:e tester

:~: =~e ::=~he test modes. ,;J.:_\: · [.: ·:r_:i:i:.:;: _:,: :;.~;:_:;:,:_:·'.· ·: :.:~.-~.;.?Itf~\{\}_%;· · :'.:.:filfl1JY'
.{~tt~·

g.a.&

·Mode

clk_mode_h<O>

Normal

Chip test

Module test

Clock reset

T:\:p:~~:!~=~:!:cif~:=~)~~::~th the crossing of standard TrL

input levels of O.~fV[~\~4 2.lf~}Q:utp\it timing is to the nominal CMOS switch

::::~::::::~\~;,~:of
microprocessors has increased
lf

substantially ::iWer tbi~~[y~~rs, is necessary to change the way they are
tested. Tradi§.Qn8:kiisuiiptions that all loads can be lumped into some
accumul~ti9n·::QJ~:¢.iifacit~~e cannot be employed any more. Rather, the model
of a tr@i.fuissidHifib:~M-th discrete loads is a much more realistic approach for

. ::::::::JfjME:::.riM\'~:::~chno!O~:··
. /j){f:::·:·TYP~i~lly, pnt\~4 circuit board (PCB) etch has a characteristic impedance
. :::fF?' of app}oximaW1y}75 n. This may vary from 60 [J to 90 n with tolerances.
:flt:;::.. If tJHFline is driven in the electrical center, the load could be as low as
···::::~{lI\ll:=:::::. &d~::n~ Therefore, a characteristic impedance range of 30 n to 90 a could be

'%'1)_,~~ced,

9-18 Preliminary Edition-September 1994

.:; ;:=1 ~l!i ~j

The 21164 output drivers are designed with typical printed circuit 99.=8-rd
applications in mind rather than trying accommodate a 40-pF test 1~~9
specification. Ai; such, it "launches" a voltage step into a characteristith.
impedance, ranging from 30 n to 90 n.
.,:{@j:~t::::::,:,.,... \{:tL

To prevent signal quality problems due to overshoot or ri~dk, ,::=~~j\[\~filt\\::\,
terminated transmission line design rules are used. By co:$.P!~ing the soui~it,
impedance of the driver transistors with an additional 20-ti'i~i~tor, a sourc.ifj
impedance of approximately 40 n is achieved. Addit!9.fii.lJY', a·lM...byalue of°"\:f
10 pF, when added to the PCB etch delays, provid~$.[j::iitr~i.n$.tjc estHhate of
actual system timing. When employing this test ciifiNtI&~~mtb~ signal at
the end of the line will transition cleanly through ·,w=e
inpµ'F'specification
range of 0.8 V to 2.0 V without plateaus, or r~;ygr.sal inti(:th~t\i:hnge.

'llfL

9"3"71~e1~~~-!s:e:~:::c: m®dated'.i::~!~j~~:tions for
IEEE 1149.1 circuits.

Table 9-13 IEEE 1149.1

. , , ,. . , , , ,.

"'t~~\l\t;,,,,,.

·:·:·:·:·:·:·······.:·:·:·:·:·:·:·:·.·.

··:·:·:·:-:·:·:·:·

the

Circuit;~~\1~:;:;,ications

Item

SpecHication

=i!,=~~:"r:=•~~{~~sse;u\I

TBD

Maximum accep~J?:!~ tck~H[~:Q~~ freq~!Hi§~·

16.6 MHz

tdi_h/tms_h ~t.u~"'ti~::{:r.ef~;~Hijijj:J;o tck_h rising edge)

~§~~~~!::~::~:~~~

4 ns

4 ns
14 ns

20 ns

(referencecffP tckJj}falli~g edge)
::::::::::

9.4

..:::::::::::··

··:::::::::::

Povvo.l'S~'''-~siderations
1

AlfJ]ffilt#•il~~:~t=
~d:i~~! !!'s:~:~!!e';::::::':~ib:S~~~=~!ce.
..Tfiis
should be guaranteed (even under transient conditions) at

. iJf?.

''\{}\,,,.,..

source"\~hltage

../J~h:e 21164 pins, and not just at the PCB edge.

"'·\:~:jj[[::~1:::::1[[::~~lll1~;?'Plus 5 Vis not used in the 21164. The voltage difference between the Vdd pins
"''\ltbim.d Vss pins must never be greater than 3.6 V. If the differential exceeds this
":''UM~t, the 21164 chip will be damaged.
··-:··

Preliminary Edition-September 1994 9-19

9.4.1

::~!=!ness
of decoupling capacitors depends on the amount of ind~ce
placed in series with them. The inductance depends both on the c~p-~citor·:::~JyJe
(construction) and on the module design. In general, the use ofJ?.P.iil]~j~jpjgb.:'.'.flih
frequency capacitors placed close to the chip package's power mj~!fgrouna==:pitii!t!!\.
with very short module etch will give best results. Depending:j~P::fitthe user's ··.··:·::\ijf!\
power supply and power supply distribution system, bulk decoiiplfug_ may also JtJ
be required on the module.
..:ttJj~l~~j~~~mb:':·. ····:::::nft::::·:·.
·:::tr
Each individual case must be separately analyzed, bU:tl~~gene~Jlitd~si~:rs
should plan to use at least 6 µF of capacitance. TypiciQ}y, ~:gi~~ 69.N~wi:in, high
frequency 0.1 µ.F capacitors are placed near the chip's Vd.dlVss P~i~. Actually
placing the capacitors in the pin field is the be~t.A\i.BtQach!l$.~wgfi1 tens of µF
of bulk decoupling (comprised of tantalum anq~~jirarlil~);~pa'.M&fs) should be
positioned near the 21164 chip.
../:)fl
. \{\\\}::::::::.

Use capacitors that are as physicall~j~\f~fu~U ~:~::jj.il>le. C~~~ect the capacitors
directly to the 21164 vdd and vSS pins cS.i:l\:t9....theiFiiW:n down by way of the
power and ground plane) by short (O~,§A. cni.''tf~g§)nftW.Iess) surface etch. The
small capacitors generally have bet.WJN~l~~tric~Fmaracteristics than the larger
units, and will more readily fit cloj~fto th~flgQA.pin field.

9.4.2 Power Supply Sequencingjjj)l:lJl~::llll:tn::::...

· : : :(i\~\j ):·
Although the 21164_JJ$eS a ,3;~i:~lY (n~:itHW.l:.power source, most of the other

logic on the PCB probab~y reqfiit~~- a 5-V . power supply. These 5-V devices can
damage the 211~§1/0·:ilrtJPts ·n~::q~L~-V power source powering the PCB logic
and the Vdd supplyi\(~~din:g{:tbe.. 21i6ijfare not sequenced correctly.
··.'\{:\fjj::::itt:t:,. ··:::?(\fflfjjjjt='·caution _ _ _ _ _ _ _ _ _ __
To avoid 9@:m~'ijkll~~-;':':~:ltG4's 1/0 circuits, the 1/0 pin voltages must
not exceedJ4 V _tjijtll -:the Vdd supply is at least 3 V or greater.
-:·. ·~~~~f1::. .-::/~~~r::::-- JJ~;~

~L ;;t11ff! :fthe Vdd and the 5-V supplies come up together,
1

This

_.,:J:fii:#if:::the.''Vdd:Jmpply comes up before the 5-V supply is asserted. Bringing

,::tjI!t=:=-··"t11·~=~~1~wer vditik~ up before the higher voltage is the opposite of the way that

. iif!l:.. CMQ$ systems':'\fith multiple power supplies of different voltages are usually

i~,\\m~t~:~::: ~:l~~m:~:~::::~sed to make 3.3-V Vdd from the 5-V
··:::m)jpJy, provided the output of the regulator (Vdd) tracks the 5-V supply with
orify:~~jjjj~mall offset. The requirement is that when the 5-V supply reaches 4 V,
··:·:::::

9-20 Preliminary Edition-September 1994

Vdd must be 3 V or higher. While the 5-V supply is below 4 V, Vdd -:~ be less
than 3 V.
"\jJ\.

tl\~tpow;;~~~~hpply

All 5-V sources on the 21164's 1/0 pins should be disabled if
sequencing is such that the 5-V supply will exceed 4 V befor~;'.'.~He~~~MmlJ~~~~lt,
least 3 V. The 5-V sources should remain disabled until th~ \Mdd pow~f.~~~iqppJ.y

~i:::;a~; :a:::~~V~e very difficult becaus~,!Q!~~~Q many ,:,

possible sneak paths. Inputs, for example, on bipol~:tt¥J;tJ.9gic ·.2i'Q.Jl;>e a source
of current, and will put a voltage across a 21164 I(Q}pin HmG.bm.Q.pgh to violate
the (no higher than 4 V until there is 3 V) rule. 'l!ti o."1Put~~fi~f:j?specified
to drive a logic one to at least 2.4 V, but usually dtive :Y.91tag@j: much higher.
CMOS logic and CMOS SRAMs usually driw.1.\\ff.µR . rail~\\\iigQgfa that match the

:::::::::~: :::::i~:ip::~) ~ina~::r::i,.:::ected between the

21164 and the 5-V supply. The Vd:d ~ypply=\iljQ.µJd ·be used to power parallel
terminations.
··====~~~~\~~~l~~~llll~~\~}\::.. ··=·====~ttllt=·
Disabling the non-21164 5-V o-qtpj~,J>f POlhJ.egic is generally possible, but
raises· the PCB complexity anc;U'Kn.''Ha.4.~.e sy~:OOm performance by increasing
critical path timing. If the .§:::M~\)ogic d~Wi~tbas an enable pin, circuits (such
as power supply supervisq#f:RitiitJ>n the PCB can monitor the Vdd and 5-V
supplies. When the sup_~ifision df:imt. detects that 5 V is increasing from zero
while the Vdd sqpply is'':bimw 3 V, tlMtl»ower supply supervisor circuit produces
a disable sign:al i6'fqn;~ aIPPGtl..logic With 5-V outputs into the high impedance
state. This ~i\.qiqti'.~t\fiJ.J...nofp,~y~nt bipolar TTL inputs from acting as a 5-V
source, but it cfilbtw.. us~:tll&t:disab1e sources such as cache RAM outputs.

"{ttl&tt\1~,~];,

((~~)
i\(~,,

Preliminary Edition-September 1994 9-21

Thermal M&1'1geme11t
.,.:::::()\:,.,..

··:·:::::ttt~::t>

~~=i~::::~escribes the 21164 thermal manag,:~(~~\\titl design
10.1

10.1.1

-::t:f·

T;;;~~~;f~~~~!~~=~Jhe 211(~~;~\\ttmperaWre and
~:=~s~:::::0u:e~.:::11~::ture at the center the
of

heat sink (Tc) is 82°C. Temp~rlture ('f~:)jj~lb.~>nld be measured at the center of
the heat sink (between th~Aira.[jp~~kage stftds). The Grafoil pad is the interface
material between the pa~tifge ahllttb.~ heat sink.

10.1.2 Thermal Resiifanc~H::tllllll!!t[~j~~\,,,._

. ,,'=tttl}'·

The following~~ooµati6~tdefl~:~~l:tk~junction-to-ambient and junction-to-heat-

O;hs = (T;; Tc)
O;a = O;hs + Ohsa

T; = Ta + P * +o;a

··:::'\ffli:::,..
Ojhs is the junction-to-heat-sink thermal resistance (°C/W) .
...,,t:~J)::::::.,. Ohsa is the heat-sink-to-ambient thermal resistance (°C/W) .
. ,,,,==tmt=Tj is the maximum junction temperature (°C).
Ta is the ambient temperature (°C).
Preliminary Edition-September 1994 10-1

Table 10-1 Oca at Various Airflows
Airflow
(ft/min)

100

1000

Oca with heat sink #1

2.30

0.41

(oC/W)

Oca with heat sink #2

1.25

0.35

0.32

(oC/W)

Frequency: 266 MHz

Airflow
(ft/min)

400

600

800

1000

Ta with heat sink #1

50.5

58.2

61.8

63.6

60.4

64.0

66.3

67.6

(oC)

Ta with heat sink #2
(oC)

~"!~~\~66 ~!''

10-2 Preliminary Edition-September 1994

1 2
0.

H:~::~~~~~~!~~~~-o;=t

~~\ne

sink type #1 mounting holes are
with
the cooling fins. Heat sink type #2 mounting holes are rotate<Jd!Q~.Jro~~j~~t.be
cooling fins. The heat sink composition is aluminum alloy 6,Q§~:Y~1JP.@@#:l.~ljfit.at
sink is shown in Figure 10-1, and type #2 heat sink is sh'n~lf" in Figlif~:::~Uf?.3.,

'lfltl\'1, t\tqb,

along with their approximate dimensions.

Figu~ 1:1 Type:~:: sink ·I

lll

c;ff(~::>~fi'

~~+W~L+1+1+1+1 =-~ i:'
I

I
I

lt
I

I•

,,,

I·

Iii : '~ \ tfe,
1

'%'

dk ,, '"%1~-~-~.t.~~-·}

%
1
~
~
~
·
:
,
:
~
_
:
.
·
~
.
'
~
.
:
~
_
.
:
.
:
_
,
·
_
.
:
'
_
.
:
:
%\%\"t:.

"4fatL ''(
: :j i: i :::~ i~ :j: ~l:
: ~ ~ ::

. -::

..· '··.'·....'··'· :·:· ' : _:;.

3.25cm
(1.280 in.)

l
Ml.0-012428

Preliminary Edition-September 1994 10-3

Figure 10-2

TYpe #2 Heat Sink

.I.

7.59cm
(2.990 in.J

t\'~X1~w
C®4:~:)~w

&..\
v... ~, 'II_Lh_

r-.{!-")
r-

I \ 'µ')
..... ~

3.80cm
(1.495 In.)

_j_

1·2.54 crn1
(1.0 in.)

'%(<::.:.: \tw

T . . . '1m1.t.j.[·i.i=1.=~.=i·.= .=:=·:=.=.'.=·.·=·.=·.=.·.=.·=·:..·..::._:·
44

4.45.cnfaH:f:::::::.

~ CF~~!~+ /ii\:\q~:--~·
-:::~f~~J··

1
O.a

··:t&.QQ~2429

·.·

T:~:::~s~:?:!f:!'!:~:ard (PCB)

component placement:

•

Orient the.::;IJIG'-ll[P:n ·;~ij~~\~B -~ith the heat sink fins aligned with the
airflow ~lhi~fi~jj~~~F':::·. jj~\ · : : :.

•

Avoi4,,:preij~JJtm ami.j~nt air. Place the 21164 on the PCB so that inlet air

is noj[~prehJ~i\i.~tP>.kmtY other PCB components.

Do4~iij~place ~ih:~;~::high power devices in the vicinity of the 21164.
,,,Jl~jj~j~~::lll!flil~:\~\g9 n~i:jiH'm~t the airflow across the 21164 heat sink. Placement of other
...:-:-::!::::':·:·..

,flf':=·
:{jj]llfo:=:..

diYi.ces mtls\ji'allow for maximum system airflow in order to maximize the

..ii)p~i-formance of the heat sink.

' '41\,t(\,\\
10-4 Preliminary Edition-September 1994

Mechanical Data and ~kagfft)

.J:t~~~:nl:nf a:rloati d:n

This chapter desmbes ilie Afpha

21164

mi~~~:At~::t:':ack~g

including chip package physical specificati,!j~,:·=·ari=itj]k§igliiViWn list. For heat
sink dimensions, refer to Chapte~ 10. ..,,t,JI.
···==t:~{~~~k::=:·.

11.1

M::ea~~~~o~~:~i::::o:~~~~-~ ~::out aheat sink.

Preliminary Edition-September 1994 11-1

Figure 11-1 Package Dimensions

R
N

G
E

A~~fEil~~r~w~~:ilt'~tti>~~~~~~Ql~Tuw~~~r~w~~ll'l'~~~~L

D
D
D

Capacitors (12x}

25.40 mm
(1.000 in} Typ
38.10 mm
(1.500 in} Typ

11-2 Preliminary Edition-September 1994

LJ-03457-TIO

PGA

Signal

Location

addr_bus_req_h

E23

BB14

addr_h<5>

BC13

AV14

addr_h<8>

AW13

BAll

Signal

BC09

J39

addr_h<16>

AW09

addr_h<19>

AVOS

addr_h<22>

BC39

AV36

addr_h<25>

BA37

AW35

addr_h<28>

AV34

BC35

addr_h<31>

AW33

BA33

addr_h<34>

BC33

AV30

addr_h<37>

BA31

BB30

addr_res_h<O>

C27

E27

cack_h

G21

AU21

clk_mode_h<l>

BA23

cmd_h<l>

Al9

cmd_h<2>

Cl9

cpu_clk_out_h

BA25

dack_h

B24

data_check_h<O>

J41

data_check_h<l>

K38

data_check_h<3>

G43

data_check_h<4>

G41

(continued on next page)

Preliminary Edition-September 1994 11-3

Table 11-1 (Cont.) Alphabetic Signal Pin List
Signal

PGA
Location

::=~:: ~o~

PGA
Location

Signal

::===::: :: ==:=~~ :t\%;*~11\\\

: ::~~~~'") ~11

==:=:~:: =~ :::::~:::

~~;~ ~j ~~I~: ~;$11~~~¥~;~~
L

:~=

:~ :~:: &::~:;~~~~?'~~~

data_h<40>

AJ41

data_h<42>

AJ39

~];~ ~~ 0ttt:;~,~~::!~f;;~I~ ~
data.Ji.<43>

AIA3

data_h<45>

AIA 1

data.Ji.<46>

AL39

data.Ji.<48>

AN43

data.Ji.<49>

AM38

data_h<51>

AN39

data.Ji.<52>

AR41

data_h<54>

AP38

data_h<55>

AU43

data_h<57>

AU41

::;;\1l1k*ll-~,1f:,::~=

AU39

data_h<60>

AW43

AV38

data_h<63>

AW39

L05

data_h<66>

M06

LOl

data_h<69>

N05

N03

data_h<72>

NOl

=c;:JdJi

.::...

I.113

dataJidlS>

dat.i~i(--\f roG

data_Ji<'ll>

11-4 Preliminary EditiorrSeptember 1994

(continued on next page)

Table 11-1 (Cont.) Alphabetic Signal Pin List
PGA

PGA

Signal

Location

::~:::

:~ :==::::

data_h<79>

Signal

Location

::: : ~=~&;,~· '"%?*~.- !':i:i:.:_: 1.:.-!jlj

data_h<80>

V06

Signal

U03

da~;;l~:~:~

··::\:tt}t::·:·.UOl

~~~~ ~ ~~I~ ~1i*~~~:> ;~w~~
da~qt@s>
- ...

AE03

data_h<98>

data_h<lOO>

AG-03

data_h<lOl>

·{ll~~~~j\idJlllll~lllll~li::t!~ta_h~l'02>

AG05

::~:~::

~:~

::~:~:;,t.i\ti:?J•-tt'"~::::

::~:~~=

=~ :~~\m\wtw::!· ,~::~:

data_h<l21>
data_h<124>

AYfl~:·.:·

AP06 ·t}f:· ~ta:_ll,~~::..

data_h<l18>

·
.t~l>

d.I::..
..... .

data_h<97>

AGOl

..,.\fAR05

data_h<l20>
data_h<l23>
data_h<l26>

AU05

AW03

data_h<127>

F22

data_ram_we_h

A23

dc_ok_h

A25

fill_h

G23

G25

idle_hc_h

A27

C29

index_h<6>

F28

:~::

C33
A35

index_h<15>
index_h<18>

F32
C35

fill_id_h
index_h<4>

,.; , , .

~~=~
~:ffflffif~<ll>
i~~ ' {\ \1~.·~-~-·-~,:,_:,_.~,_~_: :_-.,:
. :d&!:-~:'i:Jl\\:
..:..

%~\~t;

'%i\*&,'~%l;J•

;c,.-,a

index_h<14>
index_h<17>

=~:::

AUOl

AV06

:: ::;:: ::
(continued on next page)

Preliminary Edition-September 1994 11 ;...!)

Table 11-1 (Cont.) Alphabetic Signal Pin List

PGA
Signal

index_h<25>
int4_valid_h<2>
irq_h<l>
mch_hlt_irq..Ji
perf_mon_h
pwr_fail_irq_h
scache_set_h<l>

Location

PGA
Signal

Location

Signal

::7 S:?~: =~~ ~=d~?~C~~~\wi\

~~~ §:Jd> ~~: "~!~)*~~

::~:~ ~~~ =~~=:~ ~@c:~t-~~
sys_reset_l

tag_data_h<21>
tag_data_h<24>

~~=;9t$11~~~\--;~:: ~:

tag_data_h<27>

C09

tag_data_h<30>

F12

tag_data_h<32>

All

tag_data_h<33>

El3

tag_data_h<35>

Cl3

tag_data_h<36>

Al3

tag_data_h<38>

E 15

tag_data_par_h

C15

Ell

E17

tag_ram_oe_h

C21

tag_ram_we_h

Al5

tag_valid_h

Fl6

tck_h

BC17

tdo_h

BA17

BA15

test_status_h<l>

AV16

BC15

victim_pending_h

E21

E05

spare_io<250>

AV28

temp_sense
tms_h
spare_in<438>

AW:ftf

'tdt=··status ·.ti.<0>

,,,,A1L+f~Jt@ -

.::f::::;!lll~!\l:;E39 ·===tf~l\~\\j~i~tm~i@J¥o<002>

(continued on next page)

11-6 Preliminary Edition-September 1994

Table 11-1 (Cont.) Alphabetic Signal Pin List
Signal

Vss-Metal planes
21 and 52

Vdd

Metal planes 4 and 6

PGA Location

A03, A41, AA07, AA37, AC07, AC37, AD04, AD40, AF02, AF4:3,.J\QiffAG~f~[~~04,
AH40, AL07, AL37, AM04, AM40, AP02, AP42, AR07, AR37/A:f04, A"T'4U.fAW.flL
AU13, AUl 7, AU31, AU35, AV02, AV22, AV42, AW21, AYQt/AYos, AY12, AY16[)::.
AY22, AY24, AY28, AY32, AY36, AY40, B02, B06, BlO, BlSfjifffi, B34, B38, B42>~Jh.
BAOl, BA21, BA43, BB02, BB06, BBlO, BB18, BB26, BB34,"·~•. BB42, BC03, )ft
BC41, COl, C43, D04, DOB, Dl2, Dl6, D20, D24, D28,,.D.~2. D36~·::Uj~~:..F02, F42, GQ9·,
Gl3, Gl7, G31, G35, H04, H40, J07, J37, K02, K4~:tMb4fM-t.~. No7ftf.&7, T04, T40,
U07, U37, V02, V42, Y04, Y40
/J/. \l/t:::::..
· : ;: ·

AB02, AB04, AB40, AB42, AE07, AE37, AF04,
l\ll#[.Ki.j~j~~k.Jo7, AJ37,
AK04, AK40, AM02, AM42, AN07, AN37, AP04, .AP40~:~J.iT02, .t\f42, AU07, AUU,
AU15, AU19, AU29, AU33, AU37, AV04, A.Y~Q., AY02, :i;tos, A:Yio, AY14, AY18,
AY26, AY30, AY34, AY38, AY42, B04, BO,~jjp1~Ri.J6, B2tfl;J/B32, B36, B40, BA03,
BA05, BA39, BA41, BB04, BBOS, BB12/lJBt6;·Bl~~.BB"32;:::BB36, BB40, BC23, C03,
C05, C39, C41, D02, D06, DlO, Dl4, .!liff; D22, D26:ljlft~p, D34, D38, D42, F04, F40,
GU, Gl5, G19, G29, G33,
H02/lH~~:,.K04, K40,··tq1; L37, M02, M42, P04, P40,
R07, R37, T02, T42, V04, V40fW97, Watt\::::..
.

At."-9,

mw,

···::::::::::::::::::..

.:::::::::::..

1Metal plane 2-Seal ring connection tied to Vss

··=:::::l]\:::::..

2 Metal plane &-Heat slug braze pad connections ~i~Ji~::Yss.
-:=~=?~:r::::::::tf~:~====····

··::::\:!I[l::=·

··==ttll:k::::.

····:=::~:~ft=:=:·

Preliminary Edition-September 1994 11-7

11.2.2

~~:~~ns~:\he 21164 pinout from the top view with pins facing;L.

./tft\::::::·:·.. --t~tl~t:.

;:"~
AW
AU
AR
AN
AL
AJ

AG
AE
AC
AA

w
u
R
N
L
J

G
E

c
A

AV
AT
AP
AM
AK
AH
AF
AD
AB

o0o0a0db0o0o~o0o0o0o0o~o0o0o0o0o~a~;:b~69.o

.(\\\~~\}

v
T
p

M
K
H
F
D
B

···==tt\~t>

o~o~o0o0o0o0o0o0o0o0o0o0o0o0o0o0o9.ePo~d!G.\\\ ~: = = · · ·= := · ···

0
0
o0dl9.a~o~6~o9o
cl~a~cPo~o~o0o~o0o~o~o~o
o
0
0
0
0
o~o d'&~a?o
o\?@9cPd'c:Po~o~o~o~o~o
o~o~o
··..
··.·:.::::··:
:::::·:;..

11-8 Preliminary Edition-September 1994

Figure 11-3 Alpha 21164 Bottom View (Pin Up)
BC
BA

AW
AU
AR
AN
AL
AJ

AV
AT

AP
AM
AK
AH

AG
AF
AE
AD
AC

w
u
R
N

L
J

G
E

c
A

AB
y

v
T
p

M
K
H
F

D
B

Preliminary Edition-September 1994 11-9

Testability and DfttgJ1ostiCi
..;.:::(~\?:::·:·.

The

··:·::tt~::t:::::::l:·

·:::::~~}:'

awide variety user-initiated tesc::Jt::-w: This

21164 has
of
chapter covers only those testability features that afe @Vailaltl.~ to the user.
The 21164 has several internal testability f.Witllt:~. thaif~~dafplemented for
factory use only. These features are beyonA:~the···sH)p~t,o:ft1Hfdocument.

1201

T=~e ~~s::rraes fue test ~:~,.;:~tl~:::on.
Table 12-1 Alpha 21164 TestlfJ~:::\\iq~ft ~w

Preliminary Edition-September 1994 12-1

T:\ 1~:::~:terface supports a serial ROM interface, a serial di~\~

1202

terminal interface, and an IEEE 1149.1 test access port. These P9..f:ti.Jl.re ·=tjlllL
available and set to normal test interface mode when port_mo4.•2Hiji~QQ.Ilt.
Driving these pins to a value of anything other than 00 redefWf:i:··.all otlieF=t~~jflliiill:,
test interface pins and invokes special factory test modes noei@f.~red in this "\jllh
document.
··:::qjj@j\::::..
..Jlf
. ::::)~j@fk::::..

12.2.1

··::::~:~lljjjjjj~)·

~~~~~~=~::::::~:~Jl~':~d
down on the board. The 21164 samples this Jutf durffig~l~th~ system reset.
If the pin is pulled down during the/'-ystemtf:f.~t, then lB~I:21164's reset

sequence automatically loads its leach~ frgm Stt.Q.M,s before executing its first
instruction. If srom_present_l is pulle<H4itJJuriHgij!~y§.tem reset, the SROM
load is disabled. 1n this case the 1ca~lw vatUUmts a:t@rc1eared by the reset
sequence, causing the first instructjpnff.~ to:::hi3.i. the Icache and seek the

::::::ss~~:~:~~-chip
•

•

;;i\\;,,'%\\

Signal srom_oeJ supp:}jdj~:.the oufP\WJ~nable to the SROM, serving both
as an output en:i,le and··::a:~i~:l~t.reset. !&fer to the SROM specification for
details.
·{}\::.:-. ·<:ll!t1~~::::::.. ··::=:::~tlt~ljlt\.
The 21164 ass'e•::,this . ''siiJn:3.l Iow=~=for the duration of Icache load from
SROM. Once the·':ltii.~Js c6iitU!te, the signal is deasserted.
Output siggruib~=~-lli:. s~~plies the clock to the ROM that causes it to
advance t~diile'"ri~t~:'b.!t. "TR~ cycle time of this clock is approximately 126
times theljlt.JPU..:tli&k=!i:hte.

The §Boll!!nil:''·~rivllj input signal srom_data_h.

The snbl.s c~::::~~glHIIH~~~=:nough Alpha AXP code to complete the configuration
. ,:f~@j@\~~~ eitifi.w.J interface (for example, setting the timing on the external cache

Afi,fV!:J:d;~::o:e~~::::nd::s~:~~:

s:::::::te::O=:).

·.:,::::~{lf:~~t::,... c.9.1!~1usion of the Icache self-test. This gives the code loaded into the Icache
··:::\{J\a.i~ess to all of the visible state within the chip.

···::::lif•t49 Section 12.3 for details of the lcache fill operation from SROMs.
·-:·::::~;~~tr:·

12-2 Preliminary Edition-September 1994

· : : : : :·

::!a~~e:a::~~O~OM has been loaded into the Icache, the t~\,

12.2.2

SROM port pins turn into a simple serial 1/0 pins that can be JJ.~ed to. :=afiye a
diagnostic terminal through an interface such as RS422.
_::::,,,:''.'~'lfltm:t~::':::::'=·=·>t!\\L.

When the SROM is not being read, the srom_oe_l outpu~}~,~Jal i~····r!t~~\~\\)\\lfi~.
serial diagnostic terminal port is enabled if this pin is wir=mtN9.:. the active h1'ia:
enable of an RS422 (or 26LS32) receiver driving onto _§jgp.al ·sfqm~data_h afil
to the active high enable of an RS422 (or 26LS31) 9-mvi*lirivert'tfQ.w signal··
srom_clk_h. The 21164 allows srom_data_h to q,!/fea4;l!tfi8M~r9p:i:c1k_h to
be written by PALcode. This supports a bit-bange(U~~ri•J.finW:tf.i!ijK
IPRs associated with this interface are desctib£p)~:::==ciilt.~~J~~!i'

12.2.3

~~E~~~~~:~tc~~:.:~:d ul::~!~::~~\:~EE 1149.1

test

access port. This port accesses tli'K 2U94 chii(~JJoundary scan register and
chip tristate functions for board levefiijl!!µfactufiqg test. The port also allows
access to factory manufacturing..f~itµre·s===nP.ltdesetibed in this document. The
port is compliant with most regfijf~·g:gJs of~J6JlE 1149.1 test access port.

Compliance Enable lnput~t~tt;llllll\i;,,,._

· ·'=t~ l\ \ \ \ !j !i\ :· · =·

Table 12-2 shows the colllili'aneij)~qable in"imts and the pattern that must be
driven to those i1wuts iQtAt.der to·'·ii.tw~te the 21164 IEEE 1149.1 circuits.

Tab~

12-2

~:;i~~~~!ftp::'

port_mode_h<J;9> . . \lftJ>O ····='=tf' .
dc_ok_h .::~t!::~~::/l1Eit\:~!!!~l~~:l== .·. ··::::q::j]~jt:::·

ExceRQoll!tf!:~lnce

Th~L~~ll64 ."i'§l::ij~mpljijht with IEEE Standard 1149 .1-1993 with two exceptions .
. . . ,.,.,.,.,. . BotlU@k~eption~{pfovide enhanced value to the user.

,.11\f'l~MMitffil' ;:fj•

. ,fl/..

JfJ The optional trst_l pin has an internal pull-down, instead of a pull-up

=tlltt,,,.,..

..,,,{~ff" as required by IEEE 1149.1 (non-complied spec 3.6. l(b) in IEEE 1149.1-

··:·::::~fl~:::tt::/I@/

1993). The trst_l pull-down allows the chip to automatically force reset
to the IEEE 1149.1 circuits in a system in which the IEEE 1149.1 port is
··::::\:~~fht:,._unconnected. This may be considered a feature for most system designs
...'?\/that use IEEE 1149.1 circuits solely during module manufacturing.

··:::\{\\I\:::,..

Preliminary Edition-September 1994 12-3

2
.

~:e:;~~:::~::1:::;:~::,u:!'.:lk_in.)i and osc_clk_~'~o

not have any boundary scan cells associated with them (non-c~mplied·==iim.~
10.4.l(b) in IEEE 1149.1-1993). Instead, there is an extra il}pfit@Q§lt~.~lJj\=
in the boundary scan register in bit position 33 (at pin dc_qJjth). ··THfsH$lU\.
captures the output of a "clock sniffer'' circuit. It capturesJ~[[[~J" when the:·=====tt\:;.:
oscillator is connected, and captures a "O" if the chip's osciititQ\\~onnections 1I1
are broken.
.=:·:~:fJllllht=:·.·. ··======~{[[:iit:itt==·
·(}?
This exception to the standard is made to permit ~hneariJijjfµJ test===bf the
oscillator input pins.
~lj! !l! !} .J~ljlj~jf= ····=q[!!!!!!!lll~\til/·
Refer to IEEE Standard 1149.1 A Test Access Por.t.and Bqfb.idar:j}Scan

:=~=-~ ::o:~~ed:::_:::1:fr::u::cl~~~:~l~V
Figure 12-1 IEEE 1149.1 test

Acc!?'~;;::~:li!-t ''W
i~1ii%tf;i_,lft;j} 'ff

TRST_L

~~tec:~fi®'.,. .: :~ ~ \);,;,; :=:= · ~- 'I•

TMS_H

~~:: o14~h '%l&\r

TCK_H

CONTROL

TDO_H

TDl_H

====/'.=:~: ====tnst~fmt.ion Rii:,ter (IR)

. fff.. .J[t=

, \tt4~=~}~~ter

,d)if;\'.itlft\ \;(~j\~% :e::::~: :ter
\!''.:

tl\'l~,t,Cf:ntroller ,:

(BPR)

(BSRJ

LJ·••••3-TIO

Thil~:WAP controller contains a state machine. It interprets IEEE 1149.1

protO~Bis received on signal tms_h and generates appropriate clocks and

12-4 Preliminary Edition-September 1994

:~~~=iJ;"~~= i~~:!:'~~ features under its jurisdiction. T\\l~~

'*fc:::lttt~Jfaili~:ll:~I!•

Figure 12-2 TAP con1ro11er State Machine

Values
shown
are for
TMS.

r·-·-·-·-·-·-·-·-·- -·-·-·-·-·

1~zy{l\ i:.l.•.

&fi•&l\\!;;l!l;~,~
Ah

·.·.· ·.:· · ·:•.:.==.-.:_:.=:_.::•_j$ll!

Scan Sequence/

'-,Scan Sequence

MK-1455-08

··:me 5-bitz@:j.~ instruction register (IR) supports IEEE 1149.1 mandated
. /:l]:?..
..P.iblic instrllfftions (EXTEST, SAMPLE, BYPASS, HIGHZ) and a number of optional
=t:l})\,:=:·. _.i:l~~~)hstructions for public and private factory use. Table 12-3 summarizes the
····::t:(:tt:t:~f:tpublic instructions and their functions.
.:::::::\ff..

'"%1ijl1'11';;9.

Preliminary Edition-September 1994 12-5

During the capture operation, the shift register stage of IR is loaded w\lb: the
value 00001. This automatic load feature is useful for testing the integl1j.}t_of

:::~l~::::h:;~~::e. ~eratlon i\\(:::&it~~:-~
00000

EXTEST

~~ BSR

~~~~~

::::

00100

CLAMP

BPR

00101

HIGHZ

BPR

00110

Private
Private
Private

IDR

00010

00111
01000
through
11110
11111

!~~e~1-~~tfi,Itt~;J6ijpect test

BSR

Prel~S-···.1:._::.',:_:.:!=:·:·:·:·:•-·.:~.:.·.~.•.:_•./.Jf/I'

.O!ttt.h.
.,:{~):

{j~j~~l~t=:·.

Default.

Bypass Registerlfttg"" ,;fit\-1ih:' t,1\\)tillr
The bypass registe:r··:ii~~~~lJ-bifsb.ift. register. It provides a short single-bit scan
path through the port "t~tqpl!. ··:·:\}}
Boundary Sc@d~:~:Fi@iJiittr ··==:\il[~~ltl·
The 288-bit ~Pnd~w!Jt-~®.: reiister is accessed during SAMPLE, EXTEST, and
CLAMP iµ~trijl~j.gtts: Ref.4-r to Section 12.4 for the organization of this register.

12.2.4 Test sili~s ·:~fK~:tnmt~~~~~1}f

. :::f@ft~tt;:f~~~.tµs si~~l-·test_status_h<l:O> pins are used for extracting test

::::{~~~r:==····shiiG.i.)nforifil\\iw1 from the chip. System reset drives both test status pins low.

.:t::rt::··

tlii~::::...

The.~ltefault op~fition for test_status_h<O> is to output the BiSt results. The

d~f*fllt operation for test_status_h<l> is to output the IPR-written value.
··=::=t:fll1llj:ll~ltrll!l!~~}:~uring Icache BiSt Operation

··:ttj~~j[jj[t•~t_status_h<<O> is forced high at the start of the Icache BiSt. If the

··::i&.\~he BiSt passes, the pin is deasserted at the end of the BiSt operation,

otherwise it remains high.
12-6 Preliminary Edition-September 1994

•

IPR read and write operations to test status pins
t\tL.
PALcode can write to the test_status_h<l> signal pin and can fij~q. the
test_status_h<O> signal pin through hardware IPR acces~-~--- Refer\mt.

•

Timeout Reset

In either of these conditions, the CPU signals :~1~ tjf:~outli~ti~~~t event by
outputting a 256 CPU cycle wide pulse ~p,:JJ.u~ test!i.tatY.i!.h<l> pin. The
pulse on test_status_h<l> pin is cloc~~;::ey%~f>.w~Ik':qi~~ltlierefore appears
as an approximately 256 CPU cycle p_~JJe thaf::tf!~~~ and falls on system

clock rising edges.

0}t ,;l)fa,:\f%1it\1;t,,

V\\P

12.3 Serial Instruction Cache LoaCf.tQpe'rqtion

All Icache bits, including eachJl1iitt~i~~:t.~~:==:~:iaar~s~ space number (ASN),
address space match (ASM), v@jid ail=ttl111ftt~c11==:history bits can be loaded
serially from off-chip seriB:klQM.~. Onc~==::lij~ serial load has been invoked
by the chip reset sequenc~#lhitl~@@r~ cache is loaded automatically from the
lowest to the higb_est ad4~ses. ·-===:\:~~fl:\::.

~i:::i;::,~!1~?1s~t~1!l
~==~~ ;:::~~=;,~::ei:':eates
synchronizatiofN..,tp
. Hocks, consecutive access cycles to SROM
tli]H~Y:t.t.em

may shrink or str~&PtPY a'==;n~m cycle. For example, for a system with a
system cloc\.,::f:Qiti9.. . ofi5.~l~:tbe thne between the two consecutive SROM accesses
may be a~lrnt~HP: the'='f.ijfige 111to141 CPU cycles. The SROM used in the
system mft~t b~J,llle::tQ support access times in this range.

The ~@j.al~\\il~jj\t;e r~li~ved in a 200-bit-long fill scan path,· from which they are
wtjt.W,P. in :Pif.tU@kJPfo the Icache address. The fill scan path is organized as
.-.·.·:·:·:·:·:·.-. sh8\f:Y.1iP. the text'tollowing this paragraph. The farthest bit (<42>) is shifted
4JlflWii;1fi:~Ji~ :~~s!!!t~!~~~~~-is shifted in last. The data and predecode

1t~41,1t::~

Preliminary Edition-September 1994 12-7

srom data h
BHT Array
Data
Predecodes
Data parity
Predecodes
Data
Tag Parity
Tag Valids
TAG Phy.Address
TAG ASN
TAG ASM
TAGs

serial input ->
0 -> 1 ->
->
127 -> 95 -> 126 ->
19 -> 14 -> 18 ->
1 -> 0 ->
9 -> 4 ->
8 ->
63 -> 31 -> 62 ->
b ->
0 ->
1 ->
b ->
0 ->
1 ->
->
b ->
13 -> 14 ->
->

b = Single bit signal

12 4
"

7 ->
94 ->
13 ->

->
->

3 ->
30 ->

->
->

6 ->
42

96 ->

t(~~)\il'

e;~~!:4~=~: s~=~::~:: (.)is ;lc\~=~~le 12-i provides
the boundary scan register organizationA::lb:~ BSH::l~l:J!onnected between the
tdi_h and tdo_h pins whenever an instru<¥iQb.:J;eleatf:it (Table 12-3). The
scan register runs clockwise begin:qmi\::\@t:Jhe°\iP.lmr.. left corner of the chip.

There are seven groups of bidire~m~:~a~··=~IH~~::)~~~h::::~oup controlled from a
group control cell. Loading a Y:i.lP..i.nif.."1" in lffij}control cell tristates the output
drivers and all bidirectional . ri!Ps il{:tij~tgroup are configured as input pins.
The bidirectional pi~tgroupin~@m ident:Ht~J1s groups gr_l through gr_ 7 in the
Control Group colurifrfill:. TabU~tl.2.::.:4.
·:::

·(l\~i! i t: : : :·:·. ·::t::::il!iitt:::::. ···::t:::\t:!iRbtes - - - - - - - - - - - The following n~:~j\!lijppJ;:::i:J:[[~ble 12-4:
The di.aWtififi~j\Af::,~~~Hj\~~~::fr~m top to bottom, and from left to right.

•~r\~,-~;:f
•

gn;ls appear first at the tdo_b pin when

• . ::::Qiyen arF•=fnW:jtt='signal of the form signal<a:b>, signal<b> appears
··:::::"Mtbe tdo_h".pl.n prior to signaka> .
..·:::=~~~;~~f~}::::.:.

12-8 Preliminary Edition-September 1994

Table 12-4 Boundary SCan Register Organization
Signal Name

Pin
Type

BSR
Count

BSR
Cell Type

TR_ADL

Control

io_bcell

1:18

io_bcell

addr_h<21:4>

temp_sense_h

test_status_h<l:O>

trst_l

None

tck_h

None

tms_h

None

tdo_h

tdi_h

srom_oe_l

srom_clk_h

srom_data_h

srom_present_l

port_mode_h<O:l>

clk_mode_h<O>

Control
Group

None
19:20

io_bcell

Compliance enable pins.
in_bcell
Analog pins.
in_bcell
io_bcell
io_bcell
none

For chip test.

in_bcell
in_bcell
in_bcell

Compliance enable pin.

in_bcell

Captures 1 if osc is
connected, otherwise
captures 0.

in_bcell
in_bcell
in_bcell

(continued on next page)

Preliminary Edition-September 1994 12-9

Table 12-4 (Cont.) Boundary Scan Register Organization
Signal Name

Pin
Type

BSR
Count

BSR
Cell Type

:irq_h<3:0>

37:40

in_bcell

SPARE_I0<.250>

io_bcell

perf_mon_h

in_bcell

TR_ADR

Control

io_bcell

170

in_bcell

171

in_bcell

172

in_bcell

173

in_bcell

174

io_bcell

175

io_bcell

176

io_bcell

Control
Group

addr_h<39:22>

TR_DDR
data_h<63:0>
data_check_h<0:'7>

(continued on next page)

12-1 O Preliminary Edition-September 1994

Table 12-4 (Cont.) Boundary Scan Register Organization
Signal Name

Pin
Type

BSR
Count

BSR
Cell Type

tag_rall1_oe_h

177

io_bcell

victim_pending_h

178

io_bcell

TMISl

Control

179

io_bcell

addr_cmd_par_h

180

io_bcell

cmd_h<0:3>

181:184

io_bcell

scache_set_h<l:O>

185:186

io_bcell

TTAGl

Control

187

tag_ctl_par_h

188

tag_dirty_h

tag_shared_h

TTAG2

control

tag_data_par_h

tag_valid_h

tag_data_h<38:20>
SPARE_I0<002>

int4_valid_h<2:3>

TR_DDL
data_check_h<15:8>

;:::}\...

·:c~o~l li:.1~1 · ·: ;~ i :1 1 .~.~·.:·.r.J

..·:·:=:::::::::::::::=:·:·..

nt1.~.:=r·~.·.:.~_·.: .•=-=,=· :· .·=·1·=·-: .r41,:

<ll}-

gr_6

Lower left corner,
unpopulated.

::·

· : : :qi: :i: : it: .l.l: ·~·:.: _: :.:B:·.: · = · ·=· ·=· · · =: :;:;:;:;: : : :.

io_bcell
io_bcell

gr_7

....

io_bcell

gr_7

data_h<64:127>

~c.•:.•·.·.:.·.~.:1~3~.~ 2t~1: :4~l:~o;~:_~:nbce~;~l : :

Control
Group

u.-i;w

gr_7

T~:!i1oli~~2=~~:~s depends on fue sysrem cloa and the

rare
tesf:tW.irt's opefiting'=·mode. This section provides timing information that may
. :f:tfHttJ~.~ n~iti~d. for most common operations.

Preliminary Edition-September 1994 12-11

12.5.1

~t1

In mgure 12-3 (see

as~ri~), tinri~:~:\~~:~ o:"mt&nfil re:~~ ~

(time t 2 is valid only if an SROM ij?D.ot··:i)f:i~.;nt Cirtdicated by keeping signal
srom_present_l deasserted). .Ml@fi\~ROM ·11~~!iliesent, the SROM load is
performed once the BiSt comP.l~te·~y~~W.h~ internal reset signal T%Z_RESET_
B_L is extended untU the end\fof the ·sRQM load (Section 12.5.2). In this case,
the end of the time ·:tibe sh~:Wfi\j\in. FigurEtf2:._3 connects to the beginning of the
time line shown .¥.!. Figu@kl.2-·=i?:q\\l\\t:...
Table 12-5 and ~IBl~t!~]~~\}i$.t:Jj~~d~::, shown in Figure 12-3 for some of the
system clock ratios. Til.!::::h is:::~!tymred starting from the rising edge of sysclk
following the de~.~~~nioii?4t.tthe sys_reset_l signal.

Table

12~ 04~~e System Clock Ratios, Pon Mode=Nonnal
•

····::::ri~ll~lljjf:·
7
7

22644+21h 22645
19721+21h 19722
13291+141h 13292

12-12 Preliminary Edition-September 1994

Table 12-6 BiSt Timing for Some System Clock Ratios, Port Mode@Normal
(CPU Cycles)
'\\]\\.
··:·:·:·:·:·:·
Sysclk
Ratio

12.5.2

679341h

67935

788861h

78888

105

1993791h

199380

<~t:~ l! !~1i!L.
:::f~[[[fj }: : : : ~1j1~t:·=::·.:·.<t\ \l t .:~_:._:.~:~:~.;=·.=~

. ·.,.,,,,

'=\_~,.:.~=l_.='~! ,!,:;_,.~_.:.:~
..

.=·.:·=.=
'.: ..=,..J
!_,,:__

.=:,_:_.='_.=.·':·.,'.=·_,·_:,.

:::~~~!~o~:~~~:: !:r:~~nclusi9itif•!:t t:l!sentJ is

asserted. The SROM load occurs at the iD:tifilaf:~~l~ tiriitf'Bf' approximately
126 CPU cycles for srom_clk_h, . .but t~-~t;"Qihavior ··at[::tb.~ pins may shift
slightly. Refer to Chapter 7 for rii~te infofiij@ti_on on inPht signals, booting, and
the SROM interface port.
· · (}\,,.... ··=·==(\[t\,,....

Timing events are shown in Figqrn. ~~!\l\l~m~ i~:tia in Table 12-7 and

,,,Jrtmmt\~it:::~r~)q

Table 12--8.

Figure 12-4 SROM Load_i(dlhD.,,J:vent-Tiitte Line

(~ah 'Vi:'.;~~1~:4~:~t1cy. ~-~h ~~-~ =_I
r: .··=::{{:\::..

,...__ .:~J:)ii~tt; ;;~ft· · =: : : : ~t: t}·

··=::;:::::··

.t5

.....
-

.....

MK-1455-10

Preliminary Edition-September 1994 12-13

Table 12-7 SROM Load Timing for Some System Clock Ratios (Systetft~:::
Cycles)
·::\lii~L.
Sysclk

System Cycles1

Ratio

4408090

4408216+1h

3306099

3306193+21h

881627

881651+91h

13224270

132246.481h ··::13224651

192

195

Sysclk
Ratio

Figure 12-ii is a timing

13224396tJHf3224 ;=11~:~~~\... 1~;~4776
132244().g~:?:.,.·.··;::~~iu~n 4~:::=t:fia224780
.. ,.. ;::::::.

···::::::::::::::::::..

diagriz:,.)mo~,~::d sequence.

-::~~~It=·

sys_reset_I

::~if' •,1,t:::t '
1

.-.-: : : : : : : : : :..·. - ··:qj{ll~l~~l~lljjj)\:;...

t\(!::Jt-h ':!!~~~~~+1.1m
··::::qmb.~. minimum srom_clk_h cycle

·~•mT~ MK-1~

=(126 - sysclk ratio) * (CPU cycle time).

~6~lj~~imum srom_clk_h to srom_data_h delay allowable (in order to meet
the reqllired setup time) =[126 - (5 * sysclk ratio)] * (CPU cycle time).

12-14 Preliminary Edition-September 1994

Al h AXP I

p a

A.1

1·

ns ...._,~~;~
· =========-:=======.

g~lnl

A:~saa:~~·~0::~i~:=~n:~;~12-i:%~nstructions.
All values are in hexadecimal radix. Table.~~1.=r·=aijjer.ihek=~arn· contents of the
Format and Opcode columns that. are in)fi)Ie A-2·:===~~~~lllt='=··

Table A-1 Instruction Format

a!'~~\~n ~,w
··:·:···:·:·:·:·:·.

Instruction
Format

··:·:···:·:·:·:·:·

Format
Symbol

oo is the 6-bit opcode field.
oo is the 6-bi t opcode field.
ftf is the 11-bit function code field.
oo is the 6-bit opcode field.
oo is the 6-bit opcode field.
ftlf is the 16-bit function code in the
displacement field.
oo is the 6-bit opcode field.
his the high-order 2 bits of the
displacement field.
oo is the 6-bit opcode field~
ff is the 7-bit function code field.

oo is the 6-bit opcode field; the
particular PALcode instruction is
specified in the 26-bit function code
field.

Preliminary Edition-September 1994 A-1

Qualifiers for operate instructions are shown in Table A-2. Qualifiers {9.t
IEEE and VAX floating-point instructions are shown in Tables A-5 and·==~,
respectively.
\{ifa~==··
./~;rt~:======:==·=····

Mnemonic
Opcode
18ble
A-2 ArChitectureFormat
Instructions

Opr
Opr
F-P

A-2 Preliminary Edition-September 1994

10.0F
10.2D
15.0A5

Description ·==tt~~~lllill\,
,,_ , ..

~==:::t~===··

, , _~Wf%\~1~_i_i_;_=:~_.':=~_:~-··'·~_:·

Compare byte
Compare signed quadword equal
Compare G_floating equal
(continued on next page)

_ _:. .·:;··_.:.:_.···.=1t.·=. =:.··.:·._·.:_

.:i·_
...

_.=............

Table A-2 (Cont.) Architecture Instructions
Mnemonic

Format

Opcode

CMPGLE

F-P

15.0A7

CMPGLT
CMPLE

F-P

CMPLT

Opr

CMPTEQ
CMPTLE

F-P
F-P

CMPTLT
CMPTUN
CMPULE

F-P
F-P

CMPULT

Opr

Description

Opr

F-P
F-P
F-P
F-P
F-P

16.0AC
15.083
15.0A3
16.083
16.0A3

Convert T_floating to S_floating
Divide F_floating
Divide G_floating
Divide S_floating
Divide T_floating
(continued on next page)

Preliminary Edition-September 1994 A-3

Table A-2 (Cont.) Architecture Instructions
Description

Mnemonic

Format

Opcode

EQV
EXCB
EXTBL
EXTLH
EXTLL
EXTQH
EXTQL
EXTWH
EXTWL
FBEQ

Opr
Mfc
Opr

18.0400
12.06

Logical equivale:q~~[~~ttlt\=:=:=:·:·.. \~[llh:.
Exception barri,f~J·· .....=·=======:t:{{lltiIIt:.
Extract byte !t:~ll. ·
. . ·====:==?@I\.

g~~

~~:~:

~=~: ~~~:;~!!~~--~:·:·.

Opr

12. 7A

!~:~

El~iitw

Bra

Floating bfirich ifi~ zero

FBGE
FBGT
FBLE
FBLT
FBNE
FCMOVEQ
FCMOVGE
FCMOVGT
FCMOVLE
FCMOVLT
FCMOVNE
FETCH
FETCH_M
INSBL
INSLH

5
::
Bra
Bra
F-P
F-P
F-P
F-P
F-P

11.48

.,:;:;111!!!!!\:

Extrac~JiJ~lwerd h1!l(tt:.

~i\¥i ;•~l4:i~~!E!l!~
tlk::....

..·===:@-ting branch if< zero
"=====:ttbt:... Fl~g branch if =I zero
1.1~&.2A
··===:tt@:::::FCMOVE if= zero
Alltmmlt:::::.. "=·====tibMOVE if > zero
t~i7.o2F"===t\t[:~~~\=·=·· FCMOVE if ; zero
;:itJlf~ll~~l}::P2E "====:::tll}==· FCMOVE if ~ zero
::tr l'Ul2C
FCMOVE if< zero
32
35

Prefetch data, modify intent
Insert byte low
Insert longword high

.......,.:.,...... Mbr
Mbr
Mem
Mem
Mem
Mem

lA.1
lA.3
08
09
20
21

Insert longword low
Insert quadword high
Insert quadword low
Insert word high
Insert word low
Jump
Jump to subroutine
Jump to subroutine return
Load address
Load address high
Load F _floating
Load G_floating
(continued on next page)

A-4 Preliminary Edition-September 1994

"=·="

Table A-2 (Cont~) Architecture Instructions
Mnemonic

Format

Opcode

Description

\ltt.

LDL
LDL_L
LDQ
LDQ_L
LDQ_U
LDS

LDT
MB
MF_FPCR
MSKBL
MSKLH
MSKLL
MSKQH
MSKQL
MSKWH
MSKWL

MT_FPCR

MULF
Multiply G_floating
Multiply longword

MULG

MULL
MULi.JV

MULQ

Multiply quadword

MULQ/V
MULS

Multiply S_floating
Multiply T_floating
Logical sum with complement
Read and clear
Return from subroutine
Read process cycle counter
Read and set
Scaled add longword by 4
Scaled add quadword by 4
Scaled subtract longword by 4

MULT
ORNOT
RC

RET

:~:J!lllllt

S4ADDL

Opr
Opr

10.2B
10.12

Scaled subtract quadword by 4
Scaled add longword by 8
(continued on next page)

Preliminary Edition-September 1994 A-5

Table A;._2 (Cont.) Architecture Instructions

\jll~lh.

Mnemonic

Format

Opcode

Description

SSADDQ
SSSUBL
SSSUBQ
SLL

g:g~~

~~:!i

E:i :1=1~!1'~\t\,

Opr
Mem
Mem
Mem
Mem
Mem
Mem

12.34
24
25
26
2C
2E
2D

Shift ~l#.mllfj,g~l

Mem

2~~~jj~J

Mem

SRA
SRL
STF
STG
STS

STL
STL_C
STQ
STQ_C

STQ_U

STT

SUBF
SUBG
SUBL
SUBUV
SUBQ
SUBQ/V
SUBS
SUBT
TRAPB
UMULH

~~::~

1r.;~:~*t1:C1~flfi:::

.tl.·o.09 ··::::~=~tlt:,,,:.. Subtract longword

Opr

Subtract quadword

XOR

...

~j:l~~~~l~\ ,J~t~ff <;lj~

A.1.1

A-6 Preliminary Edition-September 1994

..,.,,=ttt~\,.

{\k:·:·.

Opr

WMB
ZAP
ZAPNOT

~~~ ::~~:~~!lti,~::::::..

12.31

Subtract S_floating
Subtract T_floating
Trap barrier
Unsigned multiply quadword
high
Write memory barrier
Logical difference
Zero bytes
Zero bytes not

.,: ~1 ~,~ l ![j
..

Table A-3 Opcodes Reserved for Digital
Mnemonic

Opcode

Mnemonic

Opcode

OPCOl

OPC05

OPC02

OPC06

OPC03

OPC07

OPC04

OPCOA

Mnemonic

Opcodi~ih
·:·:·:·:·:·:·.

A.1.2 Opcodes Reserved for PALcode

Table A-4
21164
Mnemonic

Opcode

HW_LD

HW_ST

lF
lE

HW_REI

Performs Dstream stores.
Returns instruction flow to the
program counter (PC) pointed
to by EXC_ADDR internal
processor register (IPR).

HW_MFPR

Accesses the lbox, Mbox, and
Dcache IPRs.

HW_MTPR

Accesses the lbox, Mbox, and
Dcache IPRs.

A.2 IEEE Fl':'~''•:~~structions
1

TahlEf~A1:~~lJitl:~:~he hiladecimal value of the 11-bit function code field for the
IEBB11Jtoati~gilijtiint~~ihstructions, with and without qualifiers. The opcode for

Preliminary Edition-September 1994 A-7

Table A-5 IEEE Floating-Point Instruction Function Codes

ADDS
ADDT
CMPTEQ

CMPTLT
CMPTLE
CMPTUN

CVTQS
CVTQT
CVTTS
DIVS
DIVT
MULS

MULT
SUBS
SUBT

None

/UC

080

000
020

040
060

oco

180

OEO

lAO

100
120

03C
03E
02C
003
023
002
022
001
021

07C
07E
06C
043
063
042
062
041 .
061

OFC
OFE

OAO
OA5
OA6
OA7
OA4
OBC
OBE
OAC
083

OA3
082

OA2
081

OAl

ADDS
ADDT
CMPTEQ

OEC
OC3

lAC

OE3
OC2

~~t:r=, .·. ~~::~::!!!!:Jt\. ~~~ ··::::==t:~::~

~~~

OEl

161

lEl

740
760

7CO
7EO

77C

7FC

77E
76C
743
763
742

7FE
7EC

i'i~}b''i\\lr
700
720

CMPTLT

CMPTLE
CMPTUN

CVTQS
CVTQT
CVTTS

73C
73E
72C
703

DIVS
DIVT
MULS

723
702
722
701
721

MULT
SUBS
SUBT

7C3

7E3

762

7C2
7E2

741
761

7Cl
7El

2AC
(continued on next page)

A-8 Preliminary Edition-September 1994

Table A-5 (Cont.) IEEE Floating-Point Instruction Function Codes

CV'ITQ

None

/SV

/SVC

OAF

02F

lAF

12F

5AF

52F

ND
lEF

/SVD

/SVID

5EF

7EF

06F

OEF

CV'ITQ

.::·:·:·:·:····

::::::::::~

·..

_ _ _ _ _ _ _ _ _ Programming Note j!llllllL.

/SVI

":·:·:·:·:·:·:·:·.
.·.·=.:

~-~-~- ~-~.~ ~t.~. ~:. :.:_~:.·.~_:.:.:.·.·.·.

..::::::::?'

.·.· .

··:::::::--

\:::::::~:~?:~~~r-

Because underflow cannot occur for CM~~-~ ~:~r~l!li~ nwjl~~erence
in function or performance between CMB.fii:l~k~n<f=Q. .xx/SU. It is
intended that software generate CM1'-1$flSU "iifill~~e-·of CMPTxx/S.
-:f:::~:..
-:{~~;~~@~@~L..
.··:=::~~tif·

A.3 VAX Floating-Point

lnstr~~j~~-~::\'-l&)

Table A--6 lists the hexadecimst!~!~:'.INQht:,.th:=~~jfjJbit function code field for the
VAX floating-point instructl.~.n'-KThe opM.j~tfor these instructions is 1515.

Table

A~ VAX Floatlng~folnt 1.l::~1o:"'~es
.·:·:·:·:·:·:·..

~~iia
=EQ
CMPGLT

g~~#E

CVTGD

····=·=·=·=··

~~~ ··:===t::~~jj!j\\~\~~~:-..··=::===~~:t\\j\~I~=:=:·:·. ··=====:~~ir~~~

480

~~Jiww~~*'~1a!.m* 120

4AO

0§,:,:··

.: =:·.·.

···=·=·=·=·=·=·=·=··

··::;Jff' .·:==·

...\(''

~-'-=·.::ft~~\!jj~~~;~==:111111111i lAC

lAD

49E

400
41E
420

580
59E

5AO

500
51E
520

4A5
4A6

12C

4A7
4AC

42C

5AC

12D

4AD

42D

5AD

52C
52D

103

483
4A3
482
4A2
481

403
423
402
422
401

583
5A3
582
5A2
581

503
523
502
522
501

CVTQF

s~4\\,~i

183
1A3
182
1A2
181
os1

001

123
102

122
101

(continued on next page)

Preliminary Edition-September 1994 A-9

Table A-6 (Cont.) VAX Floating-Point Instruction Function Codes

SUBG

CVTGQ

None

/UC

/SC

OAl

021

lAl

121

4Al

421

None

/VC

/SC

OAF

02F

lAF

12F

4AF

42F

AA O~~d:_7~~:::;ha

(.;._~1>:::(BGT).

AXP opcodes from oo
In the table, the column headings that appea~~ji}fer·===tl.~biPstfiWffons have a
granularity of s16 . The rows beneath. the o~~t: columiP~qpply the individual
hex number to resolve that granular!@~
··,·====~t~~~[~h===··
··=·\~/

If~ instruction column has a 0 in th~ rilh.=thO~-=)j~j~JJigit, replace that 0 with
the number to the left of the backslash in tRMbffset ·ailhmn on the instruction's
row. If an instruction column has ~nNi~~~~ttJh~··==snt.Oow) hexadecimal digit,
replace that 8 with the number t<£Jhe righ.1t~f thEFhackslash in the Offset
column.
/j~~~fl~l ~ ~l ! !~j~ h~: : .
··==::~:~lt}:=.
For example, the third row {g{.$) undefAhe lOrn column contains the symbol
INTS*, representingttlie alllifij~ger shlftflb.structions. The opcode for those
instructions would t'fMn . b.~ 121~f1*(!ause the 0 in 10 is replaced by the 2 in
the Offset colum..bJike~~"·· the===t;ij~h!. row under the 18 16 column contains
the symbol JSR* ~·=·=fi.@ttt~endhlt@Jl juthp instructions. The opcode for those
instructions is 1A be~i·=·.the. ==~f~bt.the heading is replaced by the number to
the right of the b.~~k$las'.fitbktJ:ie Offset column.
The instructi~'fi~~~t~~lj~~~fs.Ji;f!~a~=·under the instruction symbol.

\'•·t~:lf;

,t,11\\Wtw,

A-10 Preliminary Edition-September 1994

Table A-7 Opcode Summary
Offset

0/8

PAL*

LDA
(mem)

INTA*
(op)

MISC*
(mem)

LDF
(mem)

LDAH
(mem)

INTL*

\PAL\

(op)

LDG
(mem)

(op)

JSR*
(mem)

LDS
(mem)

INTM*

\PAL\

LDT
(mem)

(pal)

Res

1/9

Res

2/A

Res

3/B

Res

INTS*

LDQ_U
(mem)

(op)

4/C

Res

5/D

Res

FLTV*

6JE

Res

FLTI*

7/F

Res

STQ_U
(mem)

FLTL*

Res

(op)
(op)
(op)

S~bol

FLTI*
FLTL*
FLTV*
INTA*
INTL*
INTM*
INTS*
JSR*
MISC*
PAL*
\PAL\
Res

A.5

Requ;1eJWt~J Function Codes

Th~~~~~jl~ode~:::::j~f~-~~~~1g=··Table A-8 are required for all Alpha AXP
. /~Jhlitjpipbi!iK~g.~tions. The notation used is oo.ffif, where oo is the hexadecimal

t!lti(~~~~t~~~ oP~rd ffff is fue h~adreimal 26-hlt ~Won rode.
··::::::}·

Preliminary Edition-September 1994 A-11

Table A-8 Required PALcode Function Codes
Mnemonic

Type

Function Code

DRAINA

Privileged

00.0002

HALT

Privileged

00.0000

IMB

Unprivileged

00.0086

A.6 Alpha 21164 Microprocessor IEEE
Conformance

-:=~~~~rt~::::::=:=:·=····

·::::::::::=:=:·

,11i~,''"%lt411i1~,

FloaliPf~~~~\f,
\~iiik· i~l!llljf? .]llll!l~~~nrr

The 21164 supports the IEEE floating-point op~mt.i9.V..S as=:jg!fi:A~g=='by the
Alpha AXP architecture. Support for a compl~tjji==trifplem~ntiiiiffof the IEEE
Standard for Binary Floating-Point Arithm~li~~~l(ANSI/tQj.1.:._Standard 754
1985) is provided by a combination ofJlardv~il~\)ipd soft~ite as described in

:::!:::;::~== :::::::!\lrt1~!!t;pr~se exception

handling (necessary for complete c9nf4hnce. ==tQttb:~ standard) is in the Alpha

~~~~;;i§~C~:$~=~~':ilie Uap oc~s, then the

destination ~gpster·'ti.tU.NPREQ!P.TABLE. This exception is signaled if any
VAX architecttif~b9peril\g::i~ noliililhite (reserved operand or dirty zero) and
the operation caiP:a.~ aiCii~ption (that is, certain instructions, such as
CPYS, never tajte aHI~i~-~ptfoH). This exception is signaled if any IEEE
operand is.J\~iUltmt.~ (NAifa. INF, denorm) and the operation can take an
exception~{)frhis .tf.ap j~ alsh signaled for an IEEE format divide of +/- O
divided bJflt/-J}f?if tfii exception occurs, then FPCR[INV] is set and the

u:~~;~;;~•Ubox.

A-12 Preliminary Edition-September 1994

•

:,~~!~:~~~z~;~~ap

is always enabled. If the trap occurs, u!ltthe

destination register is UNPREDICTABLE. For VAX archit~.~~ure t&ftµ._at,

~~~o::::!~~si~:!.1~:; I~~;~:!!~,e~~n:::~:~ ~tfti'S~er
the numerator is valid and non-zero, with a denomin~J~~~pf +/- 0. Ifl1i~~[[\.
exception occurs, then FPCR[DZE] is set and the trap . iW:i~gpaled to the J]@
Ibox.
./~~~ll[\l[:tt\.... ··:·::::t~[ll~llltt,.
·\}?.

•

:a:::::;:~~v;:~:::l::se:::~ ~:~t:'.:t:s:'then the

destination register is UNPREDICTAB:i-F1$.~.fo~xc~liti.Da==1s signaled if the
rounded result exceeds in magnitudeJt~~ larg~itj~llID.Jte number, which can
be represented by the destin.a.tjpn fofij)i.\! This app}ies only to operations
whose destination is a floatin~Fpqjpt dat~\j[~ype. If the exception occurs,
then FPCR[OVF] is set and the itafijjJ~ sigrl~}e.d. to the Ibox.

•

::::=:ap ba}t:!~;~\e:~w occurs, then the

can
destination register is f9.t~A. to a tnli[~[~,ro, consisting of a full 64 bits of
zero. This is done eve.#.IiftH~\~jp.f:pper IEEE result would have been -0. The
exception is ~jgnaleg@iilthe rotliQj!l_result is smaller in magnitude than the
smallest fini(i~:'numb~H\\b~t can H~Pfepresented by the destination format.
If the exg~ption -®!µrs, lKib~::FPCR[UNFJ is set. If the trap is enabled, then
the trap.li:[~[Mgp.al~tf[j~~kthe "IB@~t The 21164 never produces a·denormal
number; uridiftlQ..W oc&jt~jnstead.

' ''itiQ\\t~,}'''t't*

~;t:~:;

'~*'~~\1;;

Preliminary Edition-September 1994 A-13

• ~::::~:rap can disabled. The destination register always c~Lns

be
the properly rounded result, whether the trap is enabled. The J~?'cepti~h.
is signaled if the rounded result is different from what would..:=fii:\#t~-~#l:l:h=··
produced if infinite precision (infinitely wide data) were avajllible:··=·==pg~H:lH~Il\l:h.
:floating-point results, this requires both an infinite precislitU~xponent ari:a'.=ti:Jh.
fraction. For integer results, this requires an infinite precf~ii!tJpteger and :J~l]
an integral result. If the exception occurs, then FPGB.f!lU~~] is·==:$~\tJf the ·=ttt
trap is enabled, then the trap is signaled to the Ib~~~iit=========:t'.!!!l!ll!l~ilt\... · ====tt?=·
The IEEE-754 specification allows INE to occur ccii~~~tly=~ifiti}either
OVF or UNF. Whenever OVF is signaled (if the m~factlJ~ap Jifenabled),
INE is also signaled. Whenever UNF is sigqftl•~l:..(if t:hl:i:im~~a trap is
enabled), INE is also signaled. The inexacfl.~)JfiptijliQ.. oc=&fi§ffoncurrently
with integer overflow. All valid opcodes th.it enablMQi~. also enable both
overflow and underflow. .
.{itt . ·=====~t::~~[[jjjj~~:k::=:·.
··==:=tJ?
If a CVTQL results in an integer ov~iftp_w (10¥\~;=·=·~en FPCR[INE] is
automatically set. (The INE trap is ri~'i@N~,!gnliliij~=to the Ibox because
there is no CVTQL opcode that ,,@:#ibl.~s tnW]D.~~aci trap.)

• =~::e:::~::~:~~rap ~t:::::l~~:f:estination register always

contains the low-order biti/C<64§Kb.t:::<32>) ·of the true result (not the
truncated bits) ..:JP..tegef@~g~r.flow ~~i:l~i,~cur with CVTTQ, CVTGQ or
CVTQL. In conv~fsi9~s &Mi0fl9ating to quadword integer or longword
integer, an iri:.\tger d~tfipw o:8ifit~:-. if the rounded result is outside the
range -263 •. 26'-&h. . In...Mih~~-rsiortlfrom quadword integer to longword
integer, an integ~f.Hb~~.#lowm(~!;~urs if the result is outside the range
-231 .. 231 -1... Jf:::tbe ~it£pt.ion. ='8ccurs, then the appropriate bit in the FPCR
is set. If ~b.~H~Hiiil\i.l~:,enabl'=•, then the trap is signaled to the Ibox.

• :~~tz:~J:~~al
is not recorded the
th.tilt

The state

in
FPCR.
of
sign8'.Pi$~i~mwiys sent to the Ibox. If the Ibox detects the assertion
.·.·===::::::::::::=='=·.·.of.miy~~~~f the listed. exceptions concurrent with the assertion of the SWC
,:::~J~:~::~~}Jl~~t~ll\~~rai/~t~-~~::!~ sets EXC _SUM[SWC] .
.ii~@?"' lnpqlli~xceptionslaiways take priority over output exceptions. If both exception
=tf:~i~::::... cyMJ:::=occur, then only the input exception is recorded in the FPCR and only
··==:=\f~t~~h:tbif'lnput exception is signaled to the Ibox.

' %'%!iiw,w,.

A-14 Preliminary Edition-September 1994

Preliminary Edition-September 1994 B-1

Table s-1 Alpha 21164 Microprocessor Specifications
Feature

Description

Cycle time range
Process technology
Die size
Package
Number of signal pins
Maximum power
dissipation (typ)
Clocking input
Virtual address size
Physical address size
Page size
Issue rate
Integer instruction
pipeline
Floating instruction
pipeline
On-chip Dcache
On-chip lcache

1 :Pi\iit\~ns~4ilf~n scales linearly with frequency over the frequency range 225 MHz to 312 MHz.

····::::::::::::::::::::....::::::::::::::·

B-2 Preliminary Edition-September 1994

Eff' '-:hef

Table C-1 lists the revision history for this
Table C-1 Document Revision History
Date

docum('.~_: .:;: : _: •!.:.:

,l~ j ~ ~\) j)\)\t)\)\l l ~ ltmt: : :.

•.

=:_.:1•_.:•.:. :·.:···:··:.:_::::.:,·='.:'···'·Wf}
:J·.:·_.:·.:··
..

Revision..:::::..-.

July 20, 1994

September 12, 1994

Preliminary Edition-September 1994 C-1

8n,I
Associaidlt:::l.Jlaratu re

Technical Support, Ordfl\.tpg,

.:/j)))l\\Ilttjb:::.

D.1 Calling the

Semiconduct~~J~?tfon Line for

Information and Techni,galNllH:PPli~itt

Call the Semiconductor lnf9~ltion Li~~\\{c~~tj~formation and technical support:
United States and Canadlj?::::::::::~1~~32:2·717

Outside North ,tp'e:cit(\?ffi,:1~68--6868
D.2 Ordering Df:l!~al':===5.1!!1iCd@§Juctor Products
To order the Af~H~~~jiJ~s4jj).WPP;~cessor and evaluation boards, contact your
local Digital sales o~gh_.Wh~tf working with your sales representative, you
may be ab}gj~Sllk!tad'V~t~ge of discounts and volume pricing. ·
You can Qfl~r tbj~::~f~ll~bv~;·· semiconductor products from Digital:

. ,: :,.,. '=l~jt:,,.,,::t~~:~f,:,:

·::~I:~jl

Order Number

,g!Jffe@1{,:::ll:::.::=~:uation &mrd 266 MHz

.,,/j)J?

'.Ji.~ (Supporta:j~pSF/1 and Windows NT operating systems.)

tiii®ittllitljlfl~n64 Microprocessor Evaluation Board Design
··:::::(tlt:,. Heat Sink Assembly Type 1

.··::t:t~j~~~j::jj~~~~j~>

21-40658-0x
21AOI-xx
EB164--xx
xxxxx-xx

Preliminary Edition-September 1994 D-1

Product
Heat Sink Assembly Type 2

Product
Alpha 21164-xxx Sample Kit
Alpha 21164-xxx Sample Kit
Alpha 21164-xxx Sample Kit

D.4 Ordering Associated

Digi\tf1~i{'f>~:~tor Literature

The following table lists some .9.t~J.ltAiph;==~A-l. literature that is available.
For a complete list, and for idt6fffiifip.q abouf.ordering, contact the
Semiconductor Information ,:tiie.
.. :::ttt~\:.

<It:·

"::::\lll~~~tt:::::..

Alpha Architecture mfi/fe..~e Mai@.!.~.

··::\t>

"=:=: :="

~:~;;;::~7-;:7

EY-L520E-DP-YCH
EC-QAENA-TE

Alpha 21164 },{..@..ropr9!iffesozjJf!.ardware Reference Manual

EC-QAEPA-TE
EC-QAEQA-TE

Alpha 211f!4. P.d~j~Syste#ijjDesign Guide

EC-QAExx-TE

DECchip.. ft;pr:i:mfhtl..~'f;(glwlett-Packard Logic Analyzer
-::::~:::::::::::::::.

EC-X2454-72

····:·::::::;:;::::::::·:--

. :{:JJW.t~:r.~e~··:fili4[~pµrchase the Alpha Architecture Reference Manual, call l-800-DIGITAL from

./tt=::th~HJl.$.. or C~~~ or contact your local Digital office, or technical or reference bookstore where

D-2 Preliminary Edition-September 1994

Title

PCI System Design Guide

Preliminary Edition-September 1994 D-3

§wr*1111~t:~~~~sa;

The glossary provides definitions for specific term~~~kµdJtroriiffl~Passociated
with the Alpha 21164 microprocessor and chips in g~n~fll .if
abort

:f¥fA1~t&1ht\\stifl

The unit stops the operation it i~.:::Perfomfii.g, withoutN~@ving status, to perform
: ; other operation.

'~~~~~¥Zz~~:~l~jqt{?

::=~=:~::~:(::r~t,r:l:,:'1'

An optionally implemente.d~~~f~~~§e~tµsed t~::·~educe the need for invalidation
of cached addres.$.. transtidlbns for":pf:~.~s specific addresses when a context
switch occurs. ASNs . are"::Pif:f¢.~.~sor s:(i'~eific; the hardware makes no attempt to
maintain co4.~r.~ncy·::4'-tR~S iiifittip!e processors.

:~::c::n:.!3~~~~i~:~m

one address space to another.

ALIGNE~·jf\t.f~!i\1$\'"%\f'

A datµm :ijf~~:~i~~f2**N.ft$ stored in memory at a byte address that is a multiple

"=:::\@~lk::. .il}American National Standards Institute.

An organization that develops and
...::t~\\\\j\)l)\IL::. Publishes standards for the computer industry.

····\tt:lmc
····:::·

Application-specific integrated circuit.
Glossary-1

ASN

See address space number.
./~~tr::::::::;.;....

assen

:::~:::::s::::g::.its IoWcfil kne smre.

'4l($~ $t,

4
:~:::::~::a:~m~=~::~ auser-defined rouJ&l{llt auser
process to be notified asynchronously, with res1lt.d.@tP.:. that=~~fit9~~~~ of the
occurrence of a specific event. If a user proce~$.~Ji[s.lfiftu~d. lo¥AST routine
for an event, the system interrupts t~e proc.~~:~~~~~d e~e:~4:lt.~. the AST routine
when that event occurs. When the •
routifii~::~pts, the·:·::§Jstem resumes
execution of the proces"s at the point ~he:t.!Jt ~ji~l~mterrupted.

~~~~~:::t::e:s:d~~~::~~~~\::::~:h~b:::::
110 channel. This u~age as~fii:~§. that a:·==tWd.e bandwidth may contain a high
frequency, which_.J~.an···ac.~~tm.modit~b~. high rate of data transfer.

===~mru
ca~~:t\\\t:~;::.·..::'_:_.::'.~_:.l.: : '._r~:f t[}
transaettb~~tf~l~~l~~))
'"!~=:i:~~\t!!~,ru inrerlace ~ aresult of an (memory bamer)
1
barrier

.{t~l~:~:Bipijffl:r/CMQ§:::technology.

ttl@~F

e1s:Js

%\\)}

·-.:::t~~~l~~\::.,. :Q:ipolar/CMOS. The combination of bipolar and MOSFET transistors in a

··:::=t{~~~~~l.P.imon integrated circuit.

"'tt\1!\,t·
Glossary-2

Glossary-3

:i~oup of signals that consists of many transmission lines or wires. 1~\\

interconnects computer system components to provide communica~i._~ns palti.f.:.
for addresses, data, and control information.
. : :. :::%fl~ltt::::=:·:·.·..··::l1t.

:1;t contiguous bits starting on an addressable byte
numbered right to left, 0 through 7.

bound~l~:='~{~\
.·:=:::(}@:\:::..

=~=:~::s

...::::~:~tl1jjjjt}:·

t::J'!lti

. :::;:::::=:

are said to have byte granularity if
be
written concurrently and independently by diffe_r~nt::Proce~j.~§.. Q.!~~p'rocessors.

cache
See cache memory.

.{jjjj~}

·=\~~1j11jtt::~h:...

cache block

cache coherence
Maintaining cache coheren~~t:t~quire·s:::~tb3.t when a processor accesses data
cached in another p'-~essoi;titbnu.st no{f.ij~eive incorrect data and when
cached data is ~-q~fi"ed,d!U otiMij~~~ltrpcessors that access that data receive
modified data. Sal!w.ies . f6f:bn~nt°Mi\.ipg consistency can be implemented in
hardware or softwiif~~bAJso··:mQ}~d cache consistency.
cache fill

. :=):/t@l/t==·=··

.;:::·.·.

..Ali opef.4W.9.n that marks all cache blocks as invalid.

At}l\Jl1:{\h:Wii%1f¢\;;
:AfiI?

Th~fi~tatus returned when a logic unit probes a cache memory and finds a valid

~%£'\it((~~~try at the probed address.

Glossary-4

:.:h:e::::;::eration that adversely affects the mechanisms J&t\

procedures used to keep frequently used items in a cache. SucJ.!.. interf~~ce

=~=:~ ~e'!~::~:;::!i:!:~:o~:;:~:;:~t~:ul~s~a~{j~~'!laiI't

~::ae;i~erformance.

<i--Qfl{\\{(>

;~:::~::~:rsrore ablock of cache mem~4h\1~:)%\~~)W;Ji'

"~11

:::1~:;~peed memory pla. bet$':~~:~:-~k memory and the

processor. A cache increases effectiv¢\]~1~m~fY\\\trpnsfer rates and processor
speed. It contains copies of data receiiilJty_sed . B)fthe processor and fetches
several bytes of data from mem.20:1:dn aritf~lP.~.Jiort that the processor will
access the next sequential seri.@fBf:iioo:~· THij\\jAJ.pha 21164 microprocessor
contains three on-chip interq~:~Jl;l~aches:?~&~:. also write-through cache and

::~::~ach:~ili> i\1_,~%\{-~lt;r' 'WP

The status re~urried. ::w.J1en "Caf.htt memory is probed with no valid cache entry at

the probed a~f;:;,·:''%-j~f~k,"\%'()\f;
CALL PAL lnstructib.ns

···:::rnt:::.

Speci~ ins~r~~ti9.P.~··:~~lttP ~~~oke PALcode.

:~t.eJ:i!:i~:~~l logic unit. Provides the microprocessor

21164
witQ_:jii infua.a.~~::::Ut~tlfo external data bus, board-level Bcache, and the on-chip

Glossary-5

~~~plex instruction set computer. instruction set consisting of al~,f~t

An
number of complex instructions that are managed by microcode. C(;trJ-traslll.J.t!t
RISC.
. :. ·:fJJt~~t:::::::.:..... "::\@\.

;~e:e cache of asystem bus node, refers acache line that1~\l~::::~~·~,,
to

.·:':ti~if\,,..

not been written.

·"::t~i:::ljj~~\\~~!>

~:~al used synchronize the circuits in acompujl\'.'~4\\\\~1}\\fJ'
to

..::::::::t::::::::::..

lj~lllj~ji!P!l!:llj)jjj~f.

~~=ementary
metal-oxide-semiconductor. ,.te::::~~Jonned by a
process that combines PMOS and NNf()S seiiiii.ia.~uctor m1ilerial.

==~:~sb::::~:~:::t:: for,~~~~:!!for zero/non-zero. They
can also test integer registers for '=y,gnJBdij~\:h:':·.

control and status register (~)iililllj\\\t:,:::..

··=::?tf

··:·''\f!!ii~tt>

A device or controller regis~t!l\that ·;Jmij~§.._in the processor's 1/0 space. The
CSR initiates device\\!3.ctivit§=~~~l.record~{iU status.

~:~~lex progra!~~~::~~f~:~~f

CPU

See central

,,,

' Z\{1\\1\f:'TW

Ptj~!~::i:ll!lHajt.

CSR

. ttl~t~-!l:.
Also

. ,,<~itr==·

Glossary-6

· : : ~: ;: :

~c::~:che. A cache reserved for storage of data. The Dcache does !\'tontain

instructions.

·::J~~t~t~:;::::::::·:·.

~:l inline package.

·•·•·.!If

"'{]\,

·:::::::::::::.

'%1{~1)\~Jllt:11

~=~~==~z:::n which only one address co~!~,~~=:!,. locate
to

any data in the cache, because any block of main m~mori.Fd'.l~~h~• be placed

only one possible position in the cache. . \W ~!'ltfj;)i;r···
::s::::o:~:::~~A~evice that J!::7:•processor intervention.
~=status item for acache bloc:~;J'~:i1~is,:d and has been
in

written so that it may differ fr°'mnm@,,._copy\ij}t~ys~m main memory.

~:!::ct::erence to aca.J~~~;!~~::;of
asystem bus node. The
Mt..

cache block is valid butj$\\\l.bout
t,replaced due to a cache block resource
conflict. The da~[~~must.'=t'.6\;t~.fore be"\ijfitten to memory.

:::ic
ra~:,,~~:=!~~\f~ead/write
memory that must be refreshed
(read from or
pefi&lically to maintain the storage of information .
writt~*\\\)9)._

..::::::~({@)~(:::::..·.

··====<lii::::llf:·

~::ie-tr1::~1~.i

du,!fu~\)]ll~iffjf;\t.ifl
..·=·=·===========-=· · TWcKi$.tructions are issued, in parallel, during the same microprocessor cycle.
,,,f]}llHMf.he iti'§tfuctions use different resources and so do not conflict.

,cre~rr

···==tit~~\...

"J164 ·1rt1w*'

.ilJAn evaluation board. A hardware/software applications development platform

··==:==q\[\\j\\%\l\t.

for the Alpha AXP program and a debug platform for the Alpha 21164

'l~l'li;oprocessor.
···:··

Glossary-7

;~::::::~ :~::::~~:~::e~: : :·ro r~~~t!~'~\
dEeCteCcteiro~0rand
1

·.·.·.·.·.·.·.· · .·.·.·.· =.=.~.j.-~.~.~.~.~.~.l·'·J.~=.~·.~· =~ .=·.=

correction. See also ECC error.

::::;f~~f~@~~~~t;::::.

.=··.= .= .= .:=·.= .=·=·=·=·.=.=. .=.= =·

••••

An error detected by ECC logic, to indicate that data (@f:Ahe··=pfik!!ted··=~~ntity"
has been corrupted. The error may be correctable (sotfli~rrorl~~br==tfi!'-qvectable

(hard error).

. %'f \itffef""'

~~:~::::::::c~rowammable ~:d!~~~::~~:mozy de~ce iliat
can be byte-erased, written to, and J~~!Ut:fr.om5~~Qq~Jrast with FEPROM.

::-s~le programmable logic ,t'1t~:~'~%{frt\-fy~'~$

:x::::• ::~zy,w~~~,~~~tf.~f=~processor chip, usual y located
on the same modite~:-.Als&~=~illed bcMNi:-level or module-level cache.
Fbox

Flash-~fg~ble Pf.88.t~mable read-only memory. FEPROMs can be bank- or
. . .bulk-efai.id. Contrasf"with EEPROM.

a1t•1-*!~t~==~!isror.
''\{~-\\,:are

Miihine instructions stored in hardware.
··::::::{it~~}·

Glossary-8

·;

: :::~=~~:tem in which the position of the radix point is indicaJL the

exponent part and another part represents the significant digi~~ or fraeti.9.nal

~~;:ache flush.

tf,;~i~:::::Wt;\lltt11!

::pro~ammable ~te IDTay.

4t\t\:i!::1ff}}

~~~i:~:::::l:~:ea::~~s ~!!t:~~~:~t of that

dare
can be read and/or written with a singU('-P$tni.diijn, or read and/or written
independently. VAX systems h~y{M~ olli.yJt.ibyte granularities, whereas
disk systems typically have 51:#.fhYt~:Mij!~t:gream\fgranularities. For a given
storage device, a higher gr~µJi.rity gehit@!Jy yields a greater throughput.

:::::e::a:r.~::~.1'd~=~e.
~~~~::ri~:'!,!:?t::~~e current flow, which makes the de~ce
to

appear not physicaUJfa;;9pmi;:~d to the circuit.
. :::f~tflt\::·.·. ··::::~?t~i~~~:~J:·

=~~~i~J,;;(!~)t

.·.·:=:=:::::::=:=:::==·.·.A l~j\µnit within the 21164 microprocessor that fetches, decodes, and issues

,,,{~\\\fK=tt\\\\!b~truHthn~. It also controls the microprocessor pipeline.

4,~~~t1c!:$ "'1t\i>
····:::·

Glossary-9

~::c;ction cache. cache reserved for storage instructions. One of

A
of
three areas of primary cache (located on the 21164) used to store i:.q~tructiiB.~.·
The Icache contains 8 Kb of memory space. It is a direct-mapped. :ii~h~t:J.~~~~
blocks, or lines, contain 32 bytes of instruction stream data witljl~l~·ssociittm:i:l.l:h.
as well as a 6-bit ASM field and an 8-bit branch history field .P.@ff~lock. Icacii~?~l~\.
does not contain hardware for maintaining cache coherency wlt;Rlli!b.e.mory and Jmt
is unaffected by the invalidate bus.
··====t@t~~~~~\...
<Jf
··=:::::~~t~~~~::·

IEEE Standard 754

IEEE Standard 1149.1

==~level manufacturing test procecfur~\f\\;;;::~i\)j-J;•

=='f::1~:~:i~~:::a~=··~::m::§•~}or

The term INTnn, where nn is one
.64, refers to a data field
size of nn contiguous NATURAL.L.X(ALIGNl;l.hbytes. For example, INT4 refers
to a NATURALLY ALIGNE~~jk
'Wf'

internal processor f@gister==~llRB>

··=·====tt~~t=·

=~;.::~:i~~~~~::;,;p~~

21164

nricro~ocessor.

~=:on fie1&f!::it~~~i' .

::~: ;:~~{lli~:s the ~stem respond an event.
to

,&'iJfWf.~t! "\ftt\t\tt1¥

<Cl1-,\~'!ss chip earner.
. Eti~r feedback shift register.
.··===t~~t~~:i==·

Glossary-1 O

~:~::::~::t:;:u:achine architecture where data items are fir:'9aded
into a processor register, operated on, and then stored back to . :s;nemo~l\:=.
No operations on memory other than load and store are prori:d~dtb.Y.hfu~i~i~tt.

<i,,fuk~"%R1ft1%$'~lf

:::::n set.

Four contiguous bytes starting on an arbitrary byte . P.9.®.d~ry. ··=Tq~:J;>its are"==:::=:==·
numbered from right to left, O through 31.
. :/f:r==·. ·. ·=:==::~tfl:::==·=..
"=·====tr·

~:t ffignificant bit.

~,, c::::tlMP

:e::r::;~stem action trigg..dbYL~j;~1fhardware-detected

errors that can be fatal to system"=op~mtion=:==t•~.~ triggered, machine check
handler software analyzes the error. "=:::\f~~::t::=:.. "====\flt
MAF

A!MiL.

''%~'-'ft

:::!:::?:: ~te'':'~;~:~essor, used for holiling most

instruction C9.:4e an4::i~d@:ta. "uijq=@.!ly built from cost-effective DRAM memory
chips. May fie~[[µ~.~d fiF~i1u1ectiiij:bvith the microprocessor's internal caches
and an optionaf~t.e..rnafi.i.t:b.e. "=·=.

:::JJ:S~;~,~~~ asubset of anomffial data block.
~e~At~t !~},t::,~;j;,tt

1®fll1lt\r'1'$\1h ·'"""' .
. /fff

:=d~~f?.

WAis sectiO~i@f the processor unit performs address translation, interfaces to
..:=:W~ Dcache, "Knd performs several other functions.

"\f.{\\t;;i!*:ez
"==\Jl:S.ee must be zero.
-.··===t(j~jiii!t·

Glossary-11

See ALIGNED.
Glossary-12

~:~u::~~vi:~:=::

:::

that the address of the data is evenly i&ible hy
the size of the data in bytes. For example, an ALIGNED long'Y_prd is ·;;r_ed
such that the address of the longword is evenly divisible by 4~:::\tllt?t::::·:·.·. . \~lk.

<t\t\,f\:~:tWl%fl~'

: : metal-oxide-semiconductor.

::::a:tile

random-ac~ss

memory.

(1:tf(!:l\Jiffei

th~~~h~'-·:.~.·.:.~=::~:-.:~:~

~The~~

numbered from right to left, 0
.:=_:•_.:_.: : _: ·_.:' %4'
OpenVMS AXP operating sy~-~t~l~~~~~1l~~11ii1!ilt::.
Digital's open version of th~:::Yl1$ operall@.it:SYStem, which runs on Alpha AXP

:::::s. 4tt::::~'*4t''"*' ,,
~:~!~~~,\~?';; ~~:~~d~~:=~~~~ows
<W.}' .•.

The data or r~giste1\ftppn wnlt.b.::Jm operation is performed.

individual~~fuses . ti.Mre.ate ·1r circuit.

''*-~?*( ,J

PALwe
Alpijijf!\XP Pfltil~~a architecture library code, written to support Alpha
. . : : : : : : : : : :. . mfof(iptpcessors:··--i>ALcode implements architecturally defined behavior.

sw&•1iwt11L~=atw1~11,
./J~t::.

.:d\Jspecial environment for running PALcode routines.

''1tl!\1~uJ[~rameter

····::'t%fa\sariable that is given a specific value that is passed to a program before
··::~li,eution.

Glossary-13

:s:thod for checking the accuracy of data by calculating the sum of

ti'i\~

number of ones in a piece of binary data. Even parity requires th~:-. .~orrecti~Jlk~.
sum to be an even number, odd parity requires the correct sum t.~tfi~fa~<l.h9.:4<l~~1t:.

<b(~,:::Wtt\J1~J

: : : : &Tay.

~!f!T::;i:i:::!~:~

whereby multiple

instructiont(i)r~usly
··:::t~~~f U~@~~;:::=··

PLA
Programmable logic array.

PLCC

<t:~r

~t:::::ii1tt:.

PLO
Programmable logic device.

PLL
Phase-locked loop~:·.

<J::}
../\...

'\~l{q\:_:'.1~ifh"
P-type metal-oxide-se:rill~:'l\>

PMOS

:::c quad l7'1$' 11~,i~t\t
pr1ma2~\fchi1'i\~~itwflf;r

.·:·::dfh.~. cach~Hthat is the fastest and closest to the processor. The first-level caches,
./~~~1Fla~~e.9 o~::lij~tCPU chip, composed of the Dcache, Icache, and Scache.

~1i1::~, ~Jp~rlic::!e

CPU that contains the

~rtual

address of the next

··:·:::::~lI~.truction to be executed. Most current CPUs implement the program counter
"tPOl~:Q.S a register. This register may be visible to the programmer through the

inslf4.tion set.

Glossary-14

~;~;:;::~:~:e:~e:: If ie and anegative vol~ t~lf\!fil:~!~l1, filL
~:~:~tor:s;:~:d between asignal line to apositive W!~~l\t{~;\{fj;

;Ill

:~: :=uctions are issued, m paral el, during th,,~~,i~l!e!cessor
cycle.
®.n:flic.tF
The instructions use different resources andd~~Kdo. not

:~::::::guous bytes starting 6\tan a;£':~;~\~::. The bits are
numbered from right to left, 0 througttd~.;3. ···:::::\~~~h:\.,.
RAM

·"'

"%\4\tJ~,~T~)

~::~~~:w:::~Ij!!~~;::~::: an external l~c uffit read
feWh

;::m~=:;;,~:~;:::!~:\;~emory il tency by al oMng read data

cycles to differ the 'iii4.1l:l.Jow~tb~high sequence. Requires cooperation between
the 21164 anilMitemaYlkroware.
read streaE:,:·budi~;:·.,t:::t:

· ·: : : : : :

ArraqgeJl~tfWh.er~:p.j~i~~ach memory module independently prefetches DRAM

day~}pfior ta=:::lijtl'-t#al read request for that data. Reduces average memory
. . ;: :,: : : : : : :;. . lat~i\i.ib~hile improving total memory bandwidth.

r?ic::%:;~~~~:~:::~:ec::t::t::a:~ :~::::r:e:~: its intended
··::funetions during a specified time interval when operated under stated
conditions.

Glossary-15

.::'ction that causes a logic unit to interrupt the task it is performing. go
to its' initialized state.
·\th,.
-:4~~~~rt~=:::::::=:·:·.·.

·:=:::::=======·

~~~~p!~;::~;l~~~~~!f~~:~::=~~:::~iit~il\\,
least frequently used instructions by breaking them dg:}yift&\!~~~3;iplpieHf'·
instructions. This approach allows the RISC architecWfe tq:JffiplJm~pt
a small, hardware-assisted instruction set, thus elimifijti~lihe ~'~lffor

microcode.
:?-only memory.
Register-transfer logic.
SAM

Serial access memory.

Glossary-16

"'""''''·

'kl'

'\j;)lff

ct:::::*\\,,

'®'ti~%{'%tw

:;~::~·::: organization in which the location of a data block J~

memory constrains, but does not completely determine, its loc~t~on in:::~~
cache. Set-associative organization is a compromise betweeJ\::.~ii,lnn~.PP.ffl.J
organization, in which data from a given address in main njJ~hioi)/}fa~fl~nBl\.
one possible cache location, and fully associative organizafi2fi~. in which d8'.tit.1t
from anywhere in main memory can be put anywhere in th'.:Mi§:£pe. An "n-W:jyj
set-associative" cache allows data from a given addr~§~jJ!:. matrllfu~piory to S~f
cached in any of n locations. The Scache in the 21l6.~PfuicyQ.p:roce~$9r has a

:::way set-associative o~anization.

::::: ::::

~:c::.modllie.

(@;

:::e inline pin package.

.(:)jgft
<){':::::,.:~f-$,
j'I;

•i%~q\i :ql!Q;~1

SMD
Surface mount device.

SAAM

·::t~~}·
.:i~t:::~:·.

SROM
SSI
Smal}t,~~alij~j~i@te'grat~@ij:.

iJ1fW1~~~,,~~=:~t~:dom-acress

@if

memory.

···:::tj~{t:::::.,..../I:}An area of memory set aside for temporary data storage or for procedure and

··:::::\lfaJI:. interrupt service linkages. A stack uses the last-in/first-out concept. As items
··::\{fhQ.re added to (pushed on) the stack, the stack pointer decrements. As items are
···:::¥®.tieved from (popped oft) the stack, the stack pointer increments.
····:::·

Glossary-17

~;~:::::~::::::t has al~r numOOr of pip~ae:~\lh
more complex scheduling and control. See also pipeline.

<ff{\

··.··::\l:t:

.,::tHlitt::.

superscalar

tag

. /:tttt=:.

if a memory operation is a hit or a m~ss on t.bi!J.~. cache . bl~~:.

(tJ '""· "Z\tj'''{ijlW.> ..,y·

Translation buffer.
' ii%1lftzyfyt\t
to abused line that has~~:~:\~gp, low, and high-impedance.

:::e

~=~istor~rans~i~~o~il:~~~;:;~::~f¥{jj> ""
Universal asynchrori&~hr~c~iV~tf:tfansmitter.

~~~~~:N;~tif'~!:~~:)!lt~: address that is not amultiple of

2**N.

unconditlon~:~!!~~mh~:~ i~J~ctions

,,¥.\j}ia;;i;~~-tttJll~tum address into aregister.
.:t::tr:· An <ijiration tHijt· may halt the processor or cause it to lose information. Only

.{~\[\\::..

ptjdJ~ged software (that is, software running in kernel mode) can trigger an

'Wjf%1,c,;~ED

Glossary-18

operation.

::~t~:~~::.~nces
that do not disrupt the basic operation of th::i..cessor;
the processor continues to execute instructions in its normal n;uumer:==:t]l\
Privileged or unprivileged software can trigger UNPREDICTABIJit:r~§.µifjM>r

~=:~e:s:erasable) pro~ammahle
:~:ated.
~=~in

read-only

mem~n,:~1•t%;\\;::~lWMi/ll11

wii~:Ai!:J!;
tli~,c:l~:Jj~~:i::s

Valid cache blocks have been loaded

cache hits when accessed.

lIL.

.·.·===::::=:======····

reference to a cache bioeirm

return

../f/

node. The

cache block is valid but is about to ~tr:.epla=~~dblµe to a cache block resource

conflict.

.w.w..

''1fi1tltm1i1~~::iif

~~~=~::::is addressed 'Y!Jt:~,.sses. The

tag of the cache is a
virtual address. This pro~~~4i1lb.w.s direcFliddressing of the cache without
having to go through th~Jmanslati!@t:\ruffer making cache hit times faster.

·:={!\}·

VHSIC
.·.·..

.::{t:::::..

VLSI

VRAM

x&t\h~i;, .,,%!t\%;1!1f1P
.ilf\ft=====t{{l\yo configµous bytes (16 bits) starting on an arbitrary byte boundary. The bits
··if.~ numh~ffill. from right to left, 0 through 15.

.Alff..

t:~l l ~i[: ;i; ~t= · .:::::~tl~~te data ~;apping

···:=tt::\[\\\\\\\\\\\\l\l\\\'.'.' .:'· System feature that reduces apparent memory latency by allowing write data

··===::::t{}~ycles to differ the usual low-to-high sequence. Requires cooperation between

··===tq,)21164 and external hardware.

Glossary-19

Glossary-20

A
Aborts, 2-18
Absolute Maximum Rating, 9-1
ac coupling, 9-5
Addressing, 1-2
Address regions, physical, 4-12
Address translation, 2-10
Alpha AXP documentation, D-2
ALT_MODE register, 5-60
Architecture, 1-1 to 1-3
Associated literature, D-2
AST, 2-8
ASTER register, 5-26
ASTRR register, .5-25
·(l}

As:~h;;;u•
B

sysoom

./j\:::,

1ith.\if\lWVf$L.
tli;ti{tl.~-.j~.;j:.:.:.'::'.::·'.:·:_

:. .·:·.·:.·:.·_.·.:··:·..··':·:·_.::..: ·: ·

c
Cache coherency, 4-18 to 4-27
basics, 4-19
flush protocol, 4-20
flush protocol state machines, 4-26
flush protocol systems, 4-24
transaction conflicts, 4-27
write invalidate protocol, 4-20
write invalidate protocol state machines,
4-23
write invalidate protocol states, 4-22
write invalidate protocol systems, 4-21
Cache control and bus interface unit
See Cbox
Cache organization, 2-12

lndex-1

lndex-2

Ebox, 2-9
registers, 2-9, 5-98
ECC, 4-89 to 4-91
EI_ADDR register, 5-93
El_STAT register, 5-90
Entry pointer queues, 2-34
Environment instructions
PALcode, 6--7
Error correction code
See ECC
Exceptions, 2-18
EXC_ADDR register, 5-14
EXC_MASK register, 5-17
EXC_SUM register, 5-15
External cache
See Bcache
External interface
rules for use, 4-80
External interface introduction,

Heat sink, 10-3

./)~:~=::::::::::..... ··=t:t\

~;~~~:::J~;~<iM1m1f~\ll11·i:1_:_!.:-~_:1 :_=~.-·--:~-=~_:~:.:-,:_:-~
=~ ~ ,.:=·=i=:n:· =·i•.;:.: ~.1-~:.~.~.~:=:·:=·=3·:·.=.~·.=·:•:1.t.1;;1
HW_MFPR Ins~~~!on~·::\-\:...
HW MTPR Instmcfaon &-.:.S::::::::::::::.

:_=_-=1.-_=_I_=:

.•:i:•..

..::::=:::f~::::::::~:·.

2-7

:~:~={~~\1~} -~tflt1t1\~i11 ••\~:1~~;~:r,5-~:3
A

Fil~2;!!Ji:;:nsaction:*'\~=<\%:,j~J~.:i.

i'"::,~hor":'.'!uon, 4--70

using, 4-70
IEEE floating-point conformance, A-12
IFAULT_VA_FORM register, 5-11
Initialization
role of int.errupt signals, 4-93
Input clock
ac coupling, 9-5
impedance levels, 9-5
termination, 9-5
Input clocks, 9-4
Instruction
decode, 2-5
issue, 2-5

lndex-3

Instruction cache
See lcache
Instruction fetch/decode unit and branch unit
See Ibox
Instruction issue, 1-3, 2-17
Instructions
classes, 2-20
issue rules, 2-27
latencies, 2-23, 2-24
MB, 2-12
slotting, 2-20, 2-21
WMB, 2-12,2-34
Instruction translation buffer, 2-7
See ITB
Integer execution unit
See Ebox
Integer register .file
SeeffiF
Interface restrictions, 4-79
Interface transactions
21164 initiated, 4-34 to 4-50
system initiated, 4-51 to 4-67

IPRs (cont'd)
BC_CONFIG, 5-84
BC_CONTROL, 5-78
BC_TAG_ADDR, 5-88

1
9~~_: l~-\V.+,
··:::::··

fH:3

IC_FLUSH_CTL, 5-13
IFAULT_VA_FORM, 5-11
INTID, 5-24
IPL, 2-9,5-23
ISR, 5-29
ITB_ASN, 5-8
ITB_IA, 5-9
ITB_IAP, 5-9
ITB_IS, 5-10
ITB_PTE, 5-6
ITB_PTE_TEMP, 5-9
ITB_TAG, 5-5
IVPTBR, 5-12
MAF_MODE, 5-58
MCSR, 5-54
MM_STAT, 5-44

lndex-4

. /~}::::::::::·:·.·..

IPRs (cont'd)
MVPTBR, 5-49
PAL_BASE, 5-18, 6-3

~~~l~s

]i~~.:,4;:'.tim,;il~!._.•,_1._:_I

~t=~iT, ~:~1

:;:~::!:l~~~~-~:~~ili:o

MB instruction,_.,,::::g&.!:R
····:::t{~l~::::·.·.
Mbox, 2-4, ~il~::::,:·:·:::\l~]l~h:=:·. ··::\{)·

SC_STAT, 5-72
SIRR, 5-27

~~f:~~;

7
A\j}

~~~-';'1es, 2--19 ro 2--28

4i!i~~~2 W3
ro

Qt~!l;t.11!. file, 2--34

ITB_ASN register, 5-8
ITB_IAP register, 5-9
ITB_IA register, 5-9
ITB_IS register, 5-10
ITB~PTE register, 5-6
ITB_PTE_TEMP register, 5-9
ITB_TAG register, 5-5
-{~~~t==·

(i~lj~~~t.:_f:~:._:~.=:··:':_:'::·.:_:

IVPTBR
register, 5-12,f\h.,..
L
··::::q:~{~lt~t:..

.::=_
:_
••:··_
••• :_
•••••
:·_:·_.:·:
•••• •.···: ::_
••• ::·_:_
•• :_
••:·.:_.·'
•• :••:_::::
__
•• ·•

-L-a-te-n-c1-.e-s,-2---2-3,-2---2-4---.:..:.;,._;,;,;,::::::;,;,;,::::::.,.,..::::::... --..~.:-:::~:l~~f·

Literature, D--2

·"' ' 1fa'··· ''"\{{-}·

~§~~~~)'

· : : :·

rules, 2-29
Microarchitecture, 2-2 to 2-13

2_30

Mi~eead=• file

=~~=:7~E;. ~
N
Noncached read operations, 4-13
Noncached write operations, 4-14
Nonissue conditions, 2-19
NOP command, 4-35, 4-53, 4-62

lndex-5

PMCTR register, 5-33
Power supply
considerations, 9-19
decoupling, 9-20
./~~H~t:::::=:·.·
sequencing, 9-20
)t;}
Private Bcache transactiorn~Jrt
21164 to Bcache, 4-29:::f4~~jt.;33

0
Operating temperature, 10-1
Ordering products, D-1

p
Page table entry
See PTE
PAL
restrictions, 5-100
PALcode, 1-2
environment instructions, 6-7
invoke, 6-3
PALmode, 6-2
environment, 6-2

:~;.:;::

:;::~:~r'

At~~~

~~\i;•1t?-a4

5-98
8

5-l
Pending request queue, 2-34 ·:(~~~}·
..}:::..

1
f{,_~_j:'·=·=l··_=l_:l_.:l:._:·_:··=::·_:.:l_:·_.:~.:~_:~:[:[·~.[~. :t~e.~_: ubc~_);h·fan~ydstecamck,_h4-,

80
4-83

..\f)tREAD DIRTY command, 4-53
··:::::::READ DIRTY/INVALIDATE command, 4-54
READ DIRTY/INVALIDATE transaction,
4-56
READ DIRTY timing diagram, 4-56
READ DIRTY transaction, 4-56
READ MISSO command, 4-36
READ MISS! command, 4-36
READ MISS MODO command, 4-36
READ MISS MODl command, 4-36
READ MISS MOD STCO command, 4-37
READ MISS MOD STCl command, 4-37
READ MISS no Bcache timing diagram,
4-38
READ MISS timing diagram, 4-39
READ MISS transaction, 4-39

lndex-6

READ MISS transaction (no Bcache), 4-38
READ MISS with idle_bc_h asserted
example, 4--85
READ MISS with victim abort example,
4-86
READ MISS with victim example, 4-81
READ MISS with victim timing diagram,
4-43,4-44
READ MISS with victim transaction, 4-41
READ timing diagram, ~6
READ transaction, 4-66
Read/write spacing
data bus contention, 4-69
Reference clock, 4-8, 4-9
example 1, 4-10
example 2, 4-11
examples, 4-9

Re~:::so IPRs

~~;,

Serial read-only memory
See SROM

4f~~'~ll, 2--32

A4\tl~l\\ttii!~;4-~

5-9B

==;E~EV=2-~;,\, , i\·~~" '"%ry~~\-§;,=~~~troduction,
load instruction, 2-q~:. 2-32 ·={!}t::.. ··:::\i{llll:.i!.i.!:i:i_: :..:_.:.·:::.:::·:·.=·.:'
load-miss-and-use, 241\h:..
"=:\if:\::-.·.

;fil;:.:t:~,
S

<\]j\$-1!\j~~::t{j;;

inOOrlBce, ~~:(i~:;;~~;:,j,;

Scache 2 iaf)):.

·-.:::::::::::::::::::::::::::·,.

.~~!''•,.tn 2-28

,.,;~,::~:\;:
s;~ii_fu.f~vel cache

s~l:s'ft~t::....
··::::::~{

4-2 00 4--4

-~-~-h-;1-~~-al-t-:r-:-~p-o_t_0-_'l_D-_1_ _ _ _ _ _ __

~31S~~~~:e,

1:1

Thermal resistance, 10-1

~~':;1ru":;!";ti<ms, 1~1

~;i~~

4-58

READ, ~6

:~~ ~~~r' 4-4;;6
lndex-7

Timing diagrams (cont'd)
READ MISS-no Bcache, 4-38
READ MISS with victim, 4-43, 4-44
SET DIRTY, 4-48
SET SHARED, 4-60
WRITE BLOCK, 4-47
Transactions
FILL, 4-41
FLUSH, 4-64
INVALIDATE, 4-58
LOCK, 4-48
READ, 4-66

~~~~;~~

SET DIRTY, 4-48
SET SHARED, 4-60
system initiated, 4-51
WRITE BLOCK, 4-46
WRITE BLOCK LOCK, 4-46

overlap, 4-68, 4-73
READ or WRITE to fill, 4-73
system Bcache command to fill,
-:l~~~~~t~::::::::=:·:·.··

z\~~~\=~~denci~aM
·.WRITE BLQPK. command, 4-35

wRi¢llJJLOCI{[:~:µimand acknowledge,

. ,.,: =:=:=:=:=:=:=:. ?1.Q[j[[f~=:=:....

"=·=: :;: "

/~!JffWfU.~ BEQ~ LOCK command, 4-35

'ff

WR~J~LOCK LOCK restriction,

4-79

irs:.:~~=~~ <Ilk 01l~ ''ti}fg!~~~~
1

Tri~t~~CHE VICTIM to fill,(\[lt;73 ·(jjj:::jt:t:::. "\{[[jj[j~:i:~~~i::~=:::W~~~Li::::si~:a6 -3
2

FILL4-~rvate Bcache rell&flt~W(\;:::-(t Y

c:~t~::1
t,1\~t~t\r
lndex-8