Alpha 21164 Microprocessor Hardware Reference Manual

This document is the Alpha 21164 Microprocessor Hardware Reference Manual, marked as a preliminary version from September 1994. Handwritten notes on the cover indicate it's the "EV5 external spec, turned into the HRM by tech writers" with "some bugs but not major ones."

The manual serves as a comprehensive technical reference for system designers and programmers, detailing the architecture, functionality, and interfaces of the Alpha 21164 microprocessor.

Key areas covered include:

1. Introduction and Internal Architecture (Chapters 1 & 2): Provides an overview of the Alpha AXP architecture (RISC, 64-bit, multiple instruction issue) and the specific features of the Alpha 21164, including its superscalar and pipelined design, on-chip caches (Icache, Dcache, Scache), instruction/data translation buffers (ITB, DTB), and floating-point unit.
2. Hardware Interfaces, Clocks, and Cache Coherency (Chapters 3 & 4): Describes the physical hardware interface, signal definitions, clocking schemes (system and reference clocks), memory address considerations, and detailed cache coherency protocols (including write invalidate and flush-based protocols, and associated timing diagrams).
3. Internal Processor Registers (IPRs) and Privileged Architecture Library (PALcode) (Chapters 5 & 6): Catalogs and describes the various internal processor registers used to control, configure, and monitor different functional units of the chip. It also explains the PALcode, a set of privileged subroutines that provide low-level hardware control and bridge the hardware with operating system functions.
4. Initialization, Configuration, and Error Handling (Chapters 7 & 8): Details the procedures for chip initialization and configuration, including power-up, reset states, built-in self-test (BiSt), and SROM loading. It extensively covers error detection and handling mechanisms, such as parity errors, ECC (Error Correcting Code), interrupts, and machine check flows.
5. Electrical, Thermal, and Mechanical Data (Chapters 9, 10, & 11): Provides electrical characteristics, power supply considerations, and thermal management guidelines (including heat sink specifications). It also includes mechanical data on the chip's packaging and pin assignments.
6. Testability and Diagnostics (Chapter 12): Outlines the chip's various test modes, including serial terminal ports, IEEE 1149.1 (JTAG) test access port, and boundary scan register organization, crucial for debugging and validation.
7. Appendices: Offer a summary of the Alpha AXP instruction set, detailed Alpha 21164 specifications, document revision history, and information for obtaining technical support and related literature.

Overall, the document serves as a comprehensive technical guide for understanding, implementing, and debugging systems based on the Alpha 21164 microprocessor.