Digital PDFs

EC-N0648-72-PRE

November 1993

424 pages

Original

30MB

Document:	DECchip 21071-AA and 21072-AA Chipsets Data Sheet
Order Number:	EC-N0648-72
Revision:	PRE
Pages:	424
Original Filename:

OCR Text

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INTEROFFICE MEMORANDUM
INTERNAL USE ONLY

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FROM:
DATE:
DEPT:
LOC :
DTN :
ENET:

TO: APECS Spec. distribution

Sam Nadkarni
5 November 1993
SEG/HPC
HL02-3/Cl2
225-7162
RICKS: :Nadkarni

SUBJECT: APECS Datasheets are available.
The latest APECS specification is available and will be mailed to all
of you by interoffice mail.
The specification represents
functionality corresponding to the second pass of the chip set. This
document is different from the previous revision of the APECS
specification (rev 1.1) in that it is a data sheet for the chip set
which will be used for internal and external customers. The names of
the chip set (APECS) and the chips (Comanche, Decade, Epic) are not
used in this document, instead the respective external DECchip
numbers. The correspondence betwen the internal names and the
numbers is given below:
APECS chip set,
64-bit memory
APECS chip set, 128-bit memory
Decade chip
Comanche chip
Epic chip

Along with
documents:

the

data sheet you

will

DECchip 21071-AA
DECchip 21072-AA
DECchip 21071-BA
DECchip 21071-CA
DECchip 21071-DA

receiving

the

following

Major

List of passl bugs and their workarounds.

Pass2 specification erata or additions.

Two clock specification sheets showing internal skew requirements on
a per-chip basis.

softw~re

and Hardware differences between passl and pass2.

List of Major Differences between passl and pass2

-------------------------------------------------

Rev 0.0

11/5/93

Because the Data Sheet was written for pass2 of the 21071-AA and
21072-AA, the following list has been compiled to point out the
most important differences between pass2 and passl for those
customers using passl parts.
1.

21071-BA response to itself on PCI
In passl, the 21071-BA PCI Base Register has the requirement that
the PCI Window Address MUST NOT be programmed such that a CPU
initiated transaction from the 21071-BA gets mapped back into
system memory by hitting in the PCI BASE.
In pass2, this
restriction has been removed as the-21071-BA chip will never
respond to the PCI addresses it drives out on the bus.

21071-CA pinout changes
Passl

------PIN 19
PIN 20
PIN 21
PIN 22
PIN 72
PIN 77
PIN 80
PIN 81
PIN 198

MEMCASL 4
MEMCASL-5
MEMCASL-6
MEMCASL-7
IODATARDY 0
SYSDATAAEN 4
SYSCACWR
SY SWEEN
IODATARDY 1

Pass2

------OUTVDD
SYSDATAWEEN
SYSDATALONGWE
OUTVSS
SYSREADOW
SYSDATAALEN
SYSDATAAHEN
SYSTAGWE
IODATARDY

To correspond with the IODATARDY 0 change for the 21071-CA, the
21071-BA changed the name of its-IODATARDY pin to SYSREADOW.
Note that this is a name change only.
3. CSR Differences Between Passl and Pass2.
21071-CA Error and Diagnostic Status Register - EDSR<13> specifies
which version of the chip you have. In passl, EDSR<13> reads as a
zero and in pass2, EDSR<13> reads as a one.
21071-CA General Control Register - GCR<13> is an unused bit in
passl and forces bad Tag address parity in pass2.
21071-BA Diagnostic Control and Status Register - DCSR<31>
specifies which version of the chip you have. In passl, DCSR<31>
reads as a zero and in pass2, DCSR<31> reads as a one.
4. 21071-CA Bcache Pal Interface and Equations
In pass2 the Bcache control logic consists of one OEPAL and one
WEPAL. Passl requires three PALS for Bcache control logic.
The three Pals consist of the OEPAL and two WEPALS. The following
equations should be used for the three Passl Bcache Pal
Equations on Passl EB64+ modules. (Note that the OEPAL equations
are identical between passl and pass2.)

MODULE
TITLE

OEPAL
'EB64+ Evaluation Board Bcache Output Enable Pal'

DATE

AUTH

REV

COMMENTS

2-Feb-93
12-;Feb-93
06-May-93
03-Sep-93

DDD
DOD
ODD
WPS

0.0
.1
.2
1.2

INITIAL IMPLEMENTATION
ADDED WE AND DATAA<4> FUNCTIONS
Change DCOK to SENSE DIS (note polarity)
Prepared for publication

OEPAL
DEVICE 'P16L8';
DECLARATIONS

"============================================================================
" INPUTS -

sysEarlyOEEn
sysTagOEEn
sysDataOEEn
cpuDataCEOE
sysDOE
cpuTagCEOE
cpuCReq2
cpuCReql
cpuCReqO
" GND
senseDis

" vcc

PIN 1;
PIN 2;
PIN 3;
PIN 4;
PIN 5;
PIN 6;
PIN 7;
PIN 8;
PIN 9;
PIN 10;
PIN 11;
PIN 20;

" OUTPUTS -

bcTagCEOE
Pin13
Pin14
bcDataCEOEO
bcDataCEOEl
bcDataCEOE2
bcDataCEOE3
cpuDOE

PIN 12
PIN 13
PIN 14
PIN 15
PIN 16
PIN 17
PIN 18
PIN 19

ISTYPE
ISTYPE
ISTYPE
ISTYPE
ISTYPE
ISTYPE
ISTYPE
ISTYPE

'Com, Invert';
'Com, Invert';
'Com, Invert';
'Com, Invert';
'Com, Invert';
'Com, Invert';
'Com, Invert';
'Com, Invert';

" 4 copies

EQUATIONS

"============================================================================
" Tag and Data Output Enables

"
bcTagCEOE

& cpuCReqO
& cpuCReql
t sysEarlyOEEn & cpuCReq2
(sysEarlyOEEn

•

# sysEarlyOEEn

t cpuTagCEOE
t sysTagOEEn );

bcTagCEOE.OE = (( 1 ));

& !cpuCReq2 & cpuCReql
& cpuCReq2 & !cpuCReqO
t sysEarlyOEEn & !cpuCReq2 & cpuCReqO
t cpuDataCEOE
t sysDataOEEn );
bcDataCEOEO.OE = (( 1 ));

bcDataCEOEO

bcDataCEOEl =

(sysEarlyOEEn

# sysEarlyOEEn

( sysEarlyOEEn & !cpuCReq2
# sysEarlyOEEn & cpuCReq2

& cpuCReql
& !cpuCReqO

sys~ar~yu~~n

t cpuDataCEOE

:cpu~Ke~L

~~u~~~~v

t sysDataOEEn ) ;
bcDataCEOEl.OE
bcDataCEOE2

bcDataCEOE3

((

1 ));

(sysEarlyOEEn & !cpuCReq2 & cpuCReql
# sysEarlyOEEn & cpuCReq2 & !cpuCReqO
# sysEarlyOEEn & !cpuCReq2 & cpuCReqO
# cpuDataCEOE
# sysDataOEEn );
bcDataCEOE2.0E = (( 1 ));
(sysEarlyOEEn & !cpuCReq2 & cpuCReql
# sysEarlyOEEn & cpuCReq2 & !cpuCReqO
# sysEarlyOEEn & !cpuCReq2 & cpuCReqO
# cpuDataCEOE
# sysDataOEEn ) ;

bcDataCEOE3.0E = (( l

));

"============================================================================
" CPU Output Enable, must be tristated when 3.3V is not stable.

"
cpuDOE =
cpuDOE.OE =

(sysEarlyOEEn & cpuCReq2 & cpuCReqO
*
sysDOE );
!senseDis;

"============================================================================
" Spares

"
Pin13 = ( 0 );
Pin13.0E = (( 0 ));
Pin14 = ( 0 );
Pin14.0E = (( 0 ));
END

MODULE wepalckl
TITLE
'EB64+ Evaluation Board bcache Write Enable PAL, Uses CLKl'

"
"
"
"
"
"
"

DATE

AUTH

REV

COMMENTS

2-FEB-93
12-FEB-93
06-May-93
01-Sep-93

DDD
DDD
DDD
DDD

0.0

INITIAL IMPLEMENTATION
ADDED WE AND DATAA<4> FUNCTIONS
Change DCOK to SENSE DIS (note polarity)
Created from WEPAL.ABL, but uses clkl not clklx2

.2
CKl

"============================================================================

we pal
DEVICE 'P16L8';
DECLARATIONS

"============================================================================
" INPUTS "

cl kl
clk2
sysWEEn
cpuTagCtlWE
sysCacWr
cpuDataWEl
cpuDataWEO
sysDataAEn4
cpuDataA4
" GND
longWr

" vcc

PIN 1;
PIN 2;
PIN 3;
PIN 4;
PIN 5;
PIN 6;
PIN 7;
PIN 8;
PIN 9;
PIN 10;
PIN 11;
PIN 20;

"
"

" OUTPUTS " A ViewPLD bug requires active high outputs to be inverted in the EQUATIONS
!bcTagCtlWE
PIN 14 ISTYPE 'Com,Invert';
!bcTagAdrWE
PIN 13 ISTYPE 'Com,Invert';
!bcDataWEl
!bcDataWEO

PIN 15
PIN 16

ISTYPE 'Com, Invert';
ISTYPE 'Com, Invert';

bcDataA4 1
bcDataA4-0

PIN 12
PIN 19

ISTYPE 'Com, Invert';
ISTYPE 'Com, Invert';

!palWRLat
!palRDLat

PIN 17
PIN 18

IS TYPE ' Com, Invert' ;
ISTYPE 'Com, Invert';

"============================================================================
" DataA4 Macros, these terms appear in both dataA4's, palWRLat and palRDLat

RdEqn MACRO {
( (palRDLat & cl kl)
t (palRDLat & clk2)
t (sysDataAEn4 & !clkl & !clk2) )
}

WrEqn MACRO {
( (palWRLat & !clk2)
t (palRDLat & clk2)
}

"============================================================================
" WE Macros, this produces a write pulse with proper timing
" This is the basis of the 4 other write enables

WEEqn MACRO {
( (!clkl & sysWEEn & clk2 )
# (!clkl & bcTagAdrWE )
# (!clk2 & bcTagAdrWE & longWr)
}

EQUATIONS

"============================================================================
" Cache Data Write Enables
" The cpu provides four different wires, one per copy
(WEEqn & sysCacWr
# cpuDataWEl;

bcDataWEl =

= (( 1 ));

bcDataWEl.OE
bcDataWEO

(WEEqn & sysCacWr
# cpuDataWEO;
(( 1 ));

bcDataWEO.OE =

"============================================================================
" Cache Tag Control and Address Write Enables
" The CPU cannot write the address cache ram
bcTagAdrWE =
bcTagAdrWE.OE =
bcTagCtlWE

(WEEqn);
(( 1 ));

(WEEqn)
# cpuTagCtlWE;
bcTagCtlWE.OE = (( 1 ));

"============================================================================
" Cache Address Bit 4
" These are 4 identical copies
(RdEqn & !sysCacWr)
# (WrEqn & sysCacWr)

bcDataA4 1 =
bcDataA4 1.0E =

# cpuDataA4;

(( 1 ));

(RdEqn & !sysCacWr)

bcDataA4 0 =

# (WrEqn & sysCacWr)
# cpuDataA4;

bcDataA4 0.0E

= (( 1 ));

"============================================================================
" Feedback terms.
" These are internal feedbacks used to generate dataA4
palRDLat =
palRDLat.OE

palWRLat =
palWRLat.OE =

"
END

RdEqn;

= (( 1 ));
WrEqn;

(( 1 ));

List of passl bugs and their workarounds
Rev 0.1

11/4/93

The following is a list of passl 21071-AA and 21072-AA chipset bugs that
need workarounds for the system to work successfully. The workarounds are
described below the issue.
Some are Hardware work arounds and some are
software workarounds. Some of these bugs will be fixed in pass2 so these
workarounds are only temporary.

21071-DA Masked DMA Write Causes Unmasked Write to Memory - Fixed in p2
21071-DA has a bug with OMA Writes where a 7 longword PCI burst that
starts on a cache-line boundary will cause the 8th longword to be
corrupted in memory. This bug is present because 21071-0A incorrectly
does an unmasked OMA Write on the SysBus instead of a masked write.
Software Workaround:

Software must provide a mechanism to guarantee that
a OMA Write to 21071-0A never ends with a PCI
burst of 7 longwords.
One method to insure this would be to have software
check the ending address of all OMA transfers to
memory. If the address ends on anything other than
an aligned cacheline boundary, the last longwords of
data can be transferred using single longword PCI
bursts. This would guarantee that the OMA transfer
never ends with a 7 longword PCI burst.

2. 21071-DA CSR write followed by a MB could result in OMA
Scatter Gather PTE fetch Data being corrupted.

- Fixed in P2

When an 21071-0A CSR Write is followed immediately by an MB instruction,
there is a possibility that a OMA Scatter Gather PTE
fetch could be transferred from the 21071-BA to the 21071-0A incorrectly
The problem is caused by the internal OMA Read Bypass mux switching
incorrectly. This results in 21071-0A using the wrong LW pointer bits to
transfer the data from 21071-BA to 21071-DA on the epiData bus.
Software Workaround: During OMA operations, any 21071-0A CSR writes
must be followed by a 21071-DA CSR read to the
same address to insure 21071-DA CSR writes are
never followed immediately by an MB. Since the
TBIA register is the only register that software
should be writing to in the 21071-DA in the
presence of OMA (in the absence of errors), a TBIA
write should be followed by a read of that same
TBIA CSR address. Data returned from this
write-only register is garbage.

3. DCache not invalidated on no-BCache systems

- Fixed in P2

On NO-Bcache systems (or systems with the BCache off) the following
situation will cause the CPU's internal Dcache to become
incoherrent.
The EV4 reads a memory location into its cache. The
21071-DA then writes that location. Because the DMA Write does not hit
in the BCache, the 21071-CA will not invalidate the CPU's Dcache line.
The EV4 now has the stale version of the data, not the new DMA

Hardware Workaround:

If you don't have a Bcache or if you are doing
DMA with the Bcache off and Dcache on,
tie the 21071-CA's sysDataA4 pin to the 21064's
dinvReq pin.

4. 21071-CA spec change for RAS Precharge Bug

- NOT Fixed in P2

With the fastest allowed timing values, an entire octaword write
or serial register transfer can fit in a ras precharge interval if
the precharge interval is programmed to a large value.
Software Workaround:

Because there is one Ras Precharge counter for
all memory banks, the system designer must insure
that the RAS precharge time is longer than the
minimum possible time between the assertion of
RAS and the assertion of a different RAS.
This can be ensured by meeting the following
rules for the programmed value of RAS precharge.
(all values in the equation below are programmed
values, not desired values)

GTR RP
GTR-RP

<=
<=

ROWHOLD + COLSETUP + WTCAS + 4
ROWHOLD + COLSETUP + RTCAS + 4

This equation has to be met for all timing bank programmings.

5. Configuration Write Data may get corrupted

- Fixed in P2

If the 21071-DA loses its grant on the PCI in the first cycle
of the address (21071-DA does address stepping on configuration
transactions i.e. address is driven on the bus for one cycle prior
to assertion of FRAMEL), the configuration write data gets corrupted.
Old behavior:
cy 0

cy 1

cy n

cy2

DA_gnt

DA_Req

cy n+3
I

DA_gnt

DA_gnt
removed
addrl

cy n+2

cy n+l

I...I

bus High z
DA_Req

addrl
DA_Req

addr2 bad data
f ramel

DA_Req

Hardware workaround: In the PCI arbiter.
Solution 1: Make the 21071-DA the highest priority
Solution 2: When the PCI is granted to the 21071-DA, the
arbiter should not take away the grant from the
21071-DA if it has a request asserted, even if the
21071-DA has not asserted FRAMEl.
e.g. In the example shown above the arbiter would

sampJ.e t:ne U.B._ r<.eq in cyc.l.. e v o.uu uec .i. ue u.u '-- 1_.u
away the grant from the 21071-DA in cycle :.

L. a.K.e

Suggested new behavior
cy 0

cy 1

DA_gnt

DA_gnt
addrl

DA_Req

cy 2

cy 3

addr2
f ramel

good data

DA_Req

6. 21071-CA Video Support

- Fixed in P2

21071-CA Video functionality was not verified for passl and has
a number of bugs which will prohibit it from working correctly.
Memory read and write accesses to Bank8 are bug free.
7.

21071-DA Error Logging

- Fixed in P2

21071-DA Error detection and reporting was not fully verified for passl
and has a number of bugs which will prohibit it from working correctly.
Software should not depend on 21071-DA Error handling and error handlin
g

code should not be developed with passl APECS parts.

Rev 0.0

11/5/93

Changes/additions to the DECchip 21071-AA /21072-AA Chipset Datasheet

pg 3-24:

Table 3-7, Row and Column Address decode for BankSet 8

10,10 Row ID bits are not supported.
supported by the 21071-CA.
2.

RAMs

are

After Read (WAR) condition takes effect after any Read, CPU

pg 3-26:

Only 9,9

and

9,8

3.2.4.2, 3.2.5

Read Decision Pending (RDP) has been removed.
Wait
DMA.
3.

pg 4-24: Add New equations for GTR RP.
(all values in the equation below are programmed
values, not desired values)
GTR RP
GTR-RP

<=
<=

ROWHOLD + COLSETUP + WTCAS + 4
ROWHOLD + COLSETUP + RTCAS + 4

This equation has to be met for all timing bank programmings.
For the example timing shown ion Fig. 4-18 and Fig 4-19, GTR RP cannot
be programmed > 7 cycles.

pg 10-11: PCI Configuration Space Address Translation changed
The type of the access is determined by two register bits in the host
bridge.
If these bits are 00,
the access is a type 0 access, if
these bits are 01,
the access is a type 1 access.
10 and 11 are
reserved values.
The translation of the rest of the address depends on the access type
and is shown below.

Type 0 Access Translation (access to Local PCI)

-----------------------------------------------Programmed Address:
33

29128

21120

16115

13112

716

+--------------------------------------------------------------+
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:
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IConfig
I Space
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IBus #
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!Device #
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!Function !Register lfor
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#
lbyte
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!enable I

+--------------------------------------------------------------+
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PCI Address:
31 v

- - - -I

decode

I
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from register
v

11110

817

211 0

+----------------------------------------------------------+
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!Function !Register 100 I
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#
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Only one '1'

+----------------------------------------------------------+
Device#
[20 .. 16]

decoded value
(31 .. 11]

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0100
0 0000 0000 1000
0 0000 0001 0000
0 0000 0010 0000
0 0000 0100 0000
0 0000 1000 0000
0 0001 0000 0000
0 0010 0000 0000
0 0100 0000 0000
0 1000 0000 0000
1 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000
0 0000 0000 0000

0000
0000
0000
0000
0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0001
0010
0100
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

\ Type 1 Access Translation (access to remote PCI)
Programmed Address:
33

29128

21120

16115

13112

716

+--------------------------------------------------------------+
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IConfig

IBus #

!Device#

I Space

!Function !Register lfor
I
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#
!byte
I
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I
!enable I

+--------------------------------------------------------------+
PCI Address:

from register
v

24123

16115

11110

817

211 0

+----------------------------------------------------------+
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I
I 0000000 I Bus #

I Device #

I Function I Register 1.01 I

I
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+----------------------------------------------------------+
5.

pg 9-8, pg 10-22

Parity Checking Disable added

Bit 3 of DCSR which was reserved will be used to disable parity
checking on the PCI (OPEC bit) . When the OPEC is set, PCI address
and data parity errors are not detected by the 21071-DA.
When OPEC
is cleared, PCI address and data parity checking will be in effect.
6.

pg 6-6, Table 6-4
pg 12-7, table 12-4
pg 17-7, Table 17-4, 17-5
All the AC specification numbers are passl numbers, and will change
for pass2.

pg 6-3 section 6.3.1
pg 12-3 section 12.3.1
pg 17-3 section 17.3.1
All sections replaced with accompanying handouts

DECchip 21071-BA, 21071-CA
sysClkOutl

Internal Skew Requirements (insert on page 6-4,17-4 of the spec)

__/

cl kl

clk2ref

Internal edges:
Internal memClk:
clklx2

Tsu

J ~ J\SS\S\\\\\\\\\

C2R
MCR

ClR

/Oll/////OI

C2F
MCR

.5*c - 0.50 ns min
.S*c + 0.50 ns max

ClR

.5*c - 1.25 ns min
.S*c + 1.25 ns max

.75*c - 1.60 ns min
.75*c + 1.60 ns max
These are only the requirements to make the internal logic on a single chip function.
There are
no chip requirements specs for clkl or sysClkOutl. clkl is constrained by external paths to/from
the PALs.
The phase error between sysClkOutl and clklx2 is constrained by external paths to/from
the CPU.
These numbers include 0.1 ns of skew due to the different input edge rates at the ASICs.
The skew
numbers are at 30.0 ns, if a larger cycle time is used these numbers may be increased as long as
the minimum time between clocks is not violated.
Parameter

Min

cycle time (c)
clklx2 period
clklx2 duty cycle
clklx2 rise time
clk2ref setup to clklx2 rising
clk2ref hold from clklx2 rising

30.0

30.0
15.0
50.0

ns
ns

Parameter

Example Transfers

Max

Unit

Note

Rising to same clock rising

ClR ClR, ClR ClF, ClF ClR,
ClF-ClF
-

0.50

at c=30ns

Falling to same clock falling

C2R C2R, C2R C2F, C2F C2R,
C2F-C2F
-

1. 25

at c=30ns

clklx2 rising to clklx2 falling,

ClR C2R,
ClF-C2R,
C2R-C1R,
C2F=ClR,

1. 60

at c=30ns

clklx2 falling to clklx2 rising

0.8
1. 7

Norn

Max

1. 0

ClR C2F,
ClF-C2F,
C2R-ClF,
C2F-C1F

Unit

Note

ns
ns
ns

Tsu in Figure
Th in Figure

C2R
MCR

DECchip 21071-DA
sy.sClkOutl

Internal Skew Requirements (insert on page 12-4 of the spec)

clkl
clk2ref

Internal edges:
clklx2
.5*c +
• 75*c - 1.60 ns
• 75*c + 1.60
.5*c - 2.85 n.s
.5*c + 2.85 ns
.75*c - 3.35 n.s min
.75*c + 3.35 ne aax

------Internal edges:
PClk

2 .10 ns min

+ 2 .10 ns max

PCR

ZZf

.5*c - 1.75 ns min
.5*c + 1.75 n.s max

These are only the requirements to make the internal logic on a .single chip function.
There are
no chip requirements •pees for clkl or sysClkOutl.
clkl is con.strained by external paths to/from
the PALs. The phase error between .sy.sClkOutl and clklx2 is con.strained by external paths to/from
the CPU.
These nU111bers include 0.1 ne of skew due to the different input edge rates at the ASIC.s.
The .skew
numbers are at 30.0 ns, if a larger cycle time.is used these nlllllber.s may be increased as long ae
the ainimum tiae between clock• i.s not violated.
Par-eter
cycle time (c)
clklx2 period
clklx2 duty cycle
clklx2 rise tiae
PClk period
PClk duty cycle
PClk rise tiae
clk2ref setup to clklx2 rising
clk2ref hold from clklx2 rising

Min

-30.0

NOlll

-30.0
15.0
50.0

0.8
1. 7

Max

-1.0

30.0
50.0

1.0

Unit

-ns

Note

n.s
~

n.s
ns
~

ns
ns
ne

Tau in Figure
Th in Figure

Parameter

Example Transfers

Max

Unit

Note

Rising to • - e clock rising

ClR_ClR, ClR_ClF, ClF_ClR,
ClF_ClF, PCR_PCR

0.50

at c-30n.s

Falling to .same clock falling

C2R_C2R, C2R_C2F, C2F_C2R,
C2F_C2F, PCF_PCF

1.25

at c•30n.s

clklx2 rising to clklx2 falling,

ClR_C2R,
ClF_C2R,
C2R_ClR,
C2F_ClR,

clklx2 falling to clklx2 rising

ClR_C2F,
ClF_C2F,
C2R_ClF,
C2F ClF

1.60

at c-30ns

PClk rising to PClk falling,
PClk falling to PClk rising

PCR_PCF,
PCF_PCR

1. 75

clklx2 rising to PClk rising,
PClk rising to clklx2 rising

ClR_PCR, ClF_PCR,
PCR_ClR, PCR_ClF

2.10

clklx2 falling to PClk falling,
PClk falling to clklx2 falling

C2R_PCF, C2F_PCF,
PCF_C2R, PCF_C2F

2.85

at c-30ns

clklx2 rising to PClk falling,
clklx2 falling to PClk rising,
PClk rising to clklx2 falling,
PClk falling to clklx2 rising

ClR PCF,
C2R=PCR,
PCR C2R,
PCF=ClR,

3.35

at c=30ns

ClF PCF,
C2F=PCR,
PCR C2F,
PCF-ClF

at c•30ns
at c•30ns

.<.=~.··.:.~- ~ '.~.~~.~ ~ - ~~))::::;:;.
..=

...

Data Sheet

<;: .·.;.;. :·:-:-:-:·····.

./{\~/}fff }\{~~

:.:

·. ·::::::.:=:-:=:·:·.

:-··=······-:-:·::..·

·:·::::~=~=~=~=~\:;:;:;:>;:);:;:·.

-:-:·:·:·:·:.·
.·.:·:··

· Order Number: EC-N064$;72::::::?t::tt:@ <:·:· ...
··:·:·:·:·:·:·:·:·

<=~=~~~~~~~/(;;:·:·rn~~~=:=:=:-

·'.·'.·:::::::::::::::·::;::;:·:·:·

Revlsion1uM;t.te.JQformatli6~j: /\$bis is a preliminary manual.
··::::··

.:::::::::::=-::::.-:·:·.

-·=\i)t \\i:~r~~==-:.

-: ·-:-;.:-::-: :::::::::\}:..·.

Digital Equipment Corporation
Maynard, Massachusetts

·::\:{::r::\\\:{:r::-:;:.·

First Edition, November 1993

thcti~~~--~t~~1~:~:~~c~'~::t\m\::t1=F·

Digital Equipment Corporation makes no representations that
manner described in this publication will not infringe on existingj~~ffiitunf:p~~#.~\tjghts, nor do
the descriptions contained in this publication imply the grantiI%.§fJfoenses tefl#.:i.libY:~:~' or sell

::=~::::n:::;ro::
:;~;
p~llhPigjtal ~:;!:t
Corporation.
/):}:}.. ·.··..
··:-:::::::::::::,:/::::::;:<:_ ...

©Digital Equipment Corporation 1992, 1993. All Ri;ht,:.:·f:~~

·:-: : : q: ;~:.: ,.:}: : ·,.

The following are trademarks of Digital Equipment Corpo;~tfu.;~:jHAfP.AA AXP,.the AXP logo,
DEC, DECchip, Digital,the DIGITAL logo,Open\TM§:::~~4
. VAX DOQ~N'f.
-:-:-··-::········.·.·.·.···
···::::::::::::::::::::::::-:-:-·
.. :-:-:-:-:;:;:::::;:;:::::;:: ·.·.·

<t .: ;:/~ }~\ :~(_:~.~ -~ -.=~·.;~=.:~=.=~=.:~-.:~.~ .}~=:-.·::::::::
.

·.·.:·:·:·:·

}\'.;'.::

·:::::()}}\ .. ·..::~;~::::::::-.

.·.:-:.:-:·:.:-:·::;::

Preface ............................. .<:f\\~::::~··:;:~::~h::::•........

vii

.·:·:·:·'.·:·::;::::::::·>:::::;r:::.:. ._::::::::::::~·:::·.

1 DECchip 21071-AA and 21072-A'\,,,Qh~~set .

.,O:ViiJ@w

DECchip 21071-AA and 2107~ffiiA!i:i~P$.~t. Feat~~:~·s ......... .

1.1

~:~.1 Sys~:c~~~~i;4·Mi~4~r·6:¥,llll1J;;'.::::::::::::::

Bcache Dat~tib4 Tag1b\J.l~#t::~:,....... :·. :y: ...............•
Bcache Coritf.ofPALs .....'.'.:\%@\t:f+,:..................... .

1.2.2
1.2.3

gicg~~iig~~!'~~l!llli,.~r'~;~i~:i~~ :::::::::::::::::::

1.2.9
1.2.1 o
1.2.11
1.2.12
1.2.13
1.2.14
1.2.15

Serial ROM....... ~'?UUddA;;............................ .

~:~:~

~:s~::.i~~~~l!ii~;. :':::~~::::::::::::::::::::::::

Interr#.P:t.::·q·P,n~J'ql/CPU:i:Q~hfiguration PAL .............. .

Memi:!Y':'"StN.t.M~f. i> .. . ·~ ........................... .
PCj~:\jptern;tfp1fCqgJ,f:pner ........................... .
Pc~:::tr.~r!P.b:~fals :Vi@~} •..•••..••••••.••.••.••.•.•....•

J@:p.cf&ml:&.fo.........,,,:JI:Df ...•............................
i::\j\\\~ysteiiFft.l,l:\jl\:.:::\~j@<:. · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·
.·:=::::::

1-1
1-3
1-4
1-4

1-5
1-5
1-5
1-6
1-6

1-7
1-8
1-8
1-8
1-8
1-8

1-9
1-9

:-:·.·=·:·'.-'.·'.·

iii

2 -DECchip 21071-CA Pin Descriptions
2.1
DECchip 21071-CA Pin List ................ .
2.2
DECchip 21071-CA Signal Descriptions ..... .
2.2.1
CPU/Bcache Signals ................ .
2.2.1.1
sysData <15:0> ......... .
2.2.1.2
sysAdr<33:5> .......... .
2.2.1.3
sysTag<31:17> . . . . . . . . . . . . . .: : :-: : '"' -="":=•-=·-·
2.2.1 .4
sysTagPar ................. .
2.2.1 .5
sysTagCtlV . . . . . . . . . . . . . . . . .... .
sysTagCtlD
~= ' il.!\~]-~-:~\.! ~\!l!~)\!-~.-:;: : ~: : :
sysTagCtlP .. .. .. .. .. .. .. .. .. .. .. . :n
cpuCWMask<7:0> .... .
cpuCReq<2:0> .... .
cpuCAck<2:0> ...... ·:=::ttt:W?
cpuDRAck<2:0> ..
cpuDWSekl> . ···==:t:=:=:t:=:::t:====~:===~cpuDinv~q.....
cpuHoldff.iq? ..·f==--· ••••

2.2.1
2.2.1 ..67
2.2.1 .8
2.2.1 .9
2.2.1.10
2.2.1 .11
2.2.1.12
2.2.1 .13
2.2.1 .14

Bca:::~~~~-l~iW~: ... ..::::::::::::::::::
:~:~~lt:::::!!~l~!i;;.:: :::::::::::::::::::::
:~:g:~~~!l\1;;:: :'.::: :::::::::::::::::::::
~~-·'..::w'.'.l'!'.:::::::::::::::::::::::::::

~:~:~·
~:~:~:~
~:~:~:!
~:~:~:~

2.2.2.1
2.2.2.8

~:~:~·

J)!lba~!!PEn:::::t ................. · · · · · · · · · · · · · · ·
·:::::~Y'-P~t~~ong"Wm: ....................... · · · · · · · · ·

i·!.~c;1\ll1~fJi~· Si;;.;tl De~~ri~ti~~~: : :: :: : : : :: : :: : :

2.2.3.1_/)t:}f!t

ioRequ~:st<Eb> ................................ .

2.2.3~2@%!?J?!%:=:-. ioGrant ...................................... .

· = Jt{=?J.~_;:_.~:_.~:=.=;:=:r.:~.>:.~·;· ·-.=.· ·-= :=: : : ~: : : : ,:· =!\l:1:1i1.!:_;l!_:!1!.:.:=:~.P.:.·:=!_1_.=·~.dk:~?;>
:
::::::::::::::: ::::::::::::::::::::

::::::::::;}{'.;'.:

.. ~ U

~VA~

: : : : : : _:,; .·=-===-=· ~f2~i:~it::

·=-=mo~t~Rdy ................................... .

-·:=:::::::::::::::::~\)\:~:::?~(2.~f~t2

drvSysCSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
drvMemData ................................. .

<!i i~

~~;II j Da~~~!~:~l. ~i-~~~ -~~s~~~~-o~~. :::::::::::::::::

==:=:+n::::t/g~'2~4.3

<~!~ill.;r/·
2.2.4:s;::c·

::~~~~~- :::::::::::::::::::::::::::::::::::
subCmdA<l:O>, subCmdB<l:O>, subCmdCommon

2-5
2-5
2-5
2-6
2-6
2-7
2-7
2-7
2-7
2-7
2-8
2-9
2-9
2-10
2-11
2-11
2~11

2-11
2-11
2-12
2-12
2-13
2-13
2-13
2-14
2-14
2-14
2-14
2-14
2-15
2-16
2-17
2-17
2-18
2-18
2-18
2-18
2-19
2-19
2-19

·.·:.=~-~_:_: ~;_l.:_: _:.!~il l l~!* '(%•.•. .
.

·-;.:-:·:->:·: .......... .

/tr:mt

:::::::}}=\~~:)Jf~~rr~~\;.·.

.·..:~~~/({
·.·.·.·.

.......

t~~\\J?'

··:::::;:::"

2.2.4.7
2.2.4.8
2.2.5
2.2.5.1
2.2.5.2
2.2.5.3
2.2.5.4
2.2.5.5
2.2.5.6

sysCmd<2:0> ........................ .
memCrnd<3: 1> .................... .
Memory Signal Descriptions ............ .
memAdr<ll:O> .................. .
memRAS_l<8:0> ............... .
memRASB_k8:0> ....... .
memCAS_l<3:0> ........ .
memWE_l<l:O> ......... · · · · <<::~U%f'tr<
memPDClk .................. .

~:~:;:~

::::~t~~d~ .::::::: >i:::i_:@:~,:::~u~,,,,:. .:: .. .

:::::::::::::::::

. .··::::::::t::::::::l::·~=~~

Video Support Signal Descriptjpn~FFli\\\~::::~::\:~::++.~ ........... .

2.2. 7
2.2.1.1
2.2.1.2

Miscellaneous. Signal::D~i.~,ptions -~-=::~<iMl\\\~ij)j~f: • . • • . . . . . . . • • •
wideMettiLL~:,..... ·-~'\'\blUUt::.,....... ~-··'T ............... .
c1k1x2 ' '?Iii}:::;·
...--~·,:yim:·~,:i:&,,~=-· .................. .
clk2r,~f . . ·.
. . . ·-~:- -~=::: ... ~·.······ . . . . . . . . . . . . . . . . . . .

~~ig

2. 2. 7 .3

~:~H

11 1 1

1
1
§i~~~l: ~ ~ ~ ~ :;1IP~!l~l!l1~ 1,~,~: :'. ! ~ ! f '. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

E!~'''~.; . ~; :::... ..:~~ ::::::::::::::::::::

~:F~ DECchi~~-l~~;;:111il~e~~:::::::::::::::::::::::
~:~:~

2.3.3
2.4

:::::::::::::

..· .. tllltt:£ti9

2.2.6

~-~ii~f:o~i:ii~h~ti~~l Ph; ~~i~~~t· List: :::::

. DEQ~pjp::lg:ion-Ql·lNumerical Pin Assignment List ...... .
D~~:!pip:~:~lilll~[:~~::i~,~hanical Specification ............... .

2-24
2-24
2-24
2-24
2-25
2-25
2-25
2-25
2-26
2-26
2-26
2-26
2-27
2-27
2-27
2-27
2-27
2-27
2-28

2-28
2-28
2-28
.2-28
2-28
2-29
2~4
2~7

3 DECct1;i;,ig71-CA ~;~hitecture Overview

~jk~,~~~r:=~~~r~. :::::::::::::::::::::::::::
Afbffration CSRs .............................. .
DECchip 21071-DA Requests ..................... .
Arbitration Cycles ............................. .
Grant Mechanism ............................. .
Releases ..................................... .

\'._:=,: ,;·.~- -~.·~,:_: ,:~_: ,:=,: _,':.~.-~_: , :_:_:_~,-',:~_:'.?/

3-1
3-2
3-2
3-2
3-4
3-4

3-5

3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
3.1.2.4
3.1.2.5
3.1.2.6
3.1.2.7
3.1.2.8
3.1.3
3.1.3.1
3.1.4
3.1.4.1
3.1.4.2

Bcache Control ............ ~ ............. .
Bcache Width, Size, and Speed ....... .
Bcache Allocation Policy . . . . . . . . . . . . . .
Bcache Write Granularity ......... .
CPU-Initiated Bcache Operations ..
DMA-initiated Bcache Opera~ii.n~t ....
External Logic Requirement /@~f?~
Tag Compare Logic ........ -~ . <+>::O:C?:
CPU Primary Cache Invalidates ..
sysBus Controller . . . . . . . . . . . .. -~:·=-~ .. . . . .
Wrapping . . . . . . . . . . . . . df:;rn:::~J~lfa+. -~ . . . .
Address Decoding ......... ~::!1M:Vfffa::;:\\I]:++.~ ........... .
Cacheable Memory Space.. +XfOOO<fOQQQi]fo:~l. FFFF
FFFF . ·. . . . . . . . . . . .::::Hilid:lk\.. . . . . . .''Y~/\UUC . . . . . . . . . .
Noncacheable Memotji::'$..Pi;::@::!tQQOO oooh .. 1 7FFF
FFFF . . . . . . ~ >. /!!~}{ . . .·-:>ft!~!~fif~~~!~~~~~>:·.. . . . . . . . . . . . . . .
o

•

• •.

Hi. ~dE~l~~~l~.~~~~ ~~ : :~~ 7:~::::
3

3.1.6.1
3.1.6.2
3.1.6.3

~: ~ :~

Writ~. Buffert~qifi¢~.~ CoiliPimi.9.h ................. .

W.nt~t~µffer F1u$b.~fi;~t. -:.· .....'Yf ................... .
Write.:::~~"r,,Full°C6~ffi:~~P1:1:..· ..................... .

~~~~::!lt1~1~=~~o·r·t~-:·:~:-'':··: ::::::::::::::::::::::

3.1.8.1
CPU.,Transactforiikdk>........................... .
3.1.8.2
p~,\lli!,ctiori~t1·:::.rnr........................... .
3. 1.9
En:Q.tWf:landJ@lgr . i\ ............................... .
3.2
Memoif&H4.hntmll~r. iMY, ............................... .

HL .... :ir·i~ti!~::::~~~~::::::::::: : ::::::

3.2.2.2:/ff:I\l BankseULJfankset7 ............................ .
.,.,3.• 2.2:3::::::::1::t::t:::::>::::::.Bankset8 .................. ~ ................. .
_, , ,:, ,:,:,. :::~~:g~?lf . ,,,,,,<:::::::]i:::$.µpported Memory SIMMs ...................... .
.-:·:·;:;:~:;:;:;:;:;:;: · :::3~~~~~~iI~llt..

Metij9i}{~•ddress Generation

)II! i~:i1fI! Perf:il~~J~::i~:· ::::::::::::::::::::::
:': ::UJ.:;::·:-.:··.·..

::·,>>a~J2j5F

•

••

•

Transaction Scheduler ....... : : : : : : : : : : : : : : : : : : : : : : :
Programmable Memory Timing ...................... .
·=t£g~£·,:\,)\,: .. Presence Detect Logic ............................. .
3.2]1(\:/lf' Video Support Logic ............................... .

'==-:::t.\··'\J~~\g.9,,__

3--8
3--8
3-9
3-9
3-9
3-9
3-10
3-10
3-10
3-11
3-12
3-12
3-12

3-13
3-13
3-13
3-13
3-14
3-15
3-15
3-17
3-18
3-19
3-19

3-19
3-20
3-21
3-22
3-22
3-23
3-25
3-25
3-26
3-26
3-27
3-28
3--30

4 DECchip 21071-CA Programmer's Reference
Register Descriptions . . . . . . . . . . . . . . . . . . . . . .
General Registers ...................... .
General Control Register ............ .
Error and Diagnostic Status Regi~t~r .. .
Tag Enable Register ......... d~:!:!~!i!!P:
Error Low Address Register .... :\<. Y??FT:?t
Error High Address Register ...... .
LDx_L Low Address Register ......... .

4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.4
4.5
4.6

Me~~-~e~~;~r~d~~~~s. ~ ~-s~ r<~: =:~! !~IJ!JtJ Jl~Jl·J~i:\][!: I:m;: : ~.: : . ·
~:::c:a;;i:i:c~i~~; ~::~&;; :::'.!IJll~~;j ::::::::::
Presence Detect High Datf.a'.f..mn'-~t:'===·.'. .... ·.:TC .......... .
Base Address Registers=-. J::Wt=:···:··=~'\dW!fa):k:~=-.· ............ · · ·

~:!::~:::::~tlli!Wd ~:::~!~fl~'.::::::::::::::

Global Timi#iHRegj.~ter . =5%~\@#T>==~= .................... .
Refresh TimiHg --~t~r .. ·:=yg~::::~tt@>=· ............... · · ·
Programm~pg:JY.IemocyHJ.i.m~ng== .... ·:>SU< .................. .
Configuring/Mifu9JY . .· ·-~::::~t!~~~;~~;!{~t!;~c~::::~-.·.· . . . . . . . . · · · · · · · · · · · · · · ·
Bcache Initialfaitid.h:::::...... :·==yu:u:UUt>...................... .

5 DECchip

21071-~~~;;~~lli~g§:~: Timing Diagrams

lntroduqti9.ri?/'Y:J::.'.:::.~:-C=·...=. · . .·='>? . .......................... .

5.1

H~ sy::;:&~Jlll ::::::::::::::::::::::::::::::::
.1

5.2.1.2 :t::JI>- R.iiaJB.ibck!:i)fa!U''"................................ .
5.2.1.2/t\ ·=:=:=;===;·
d~ih:~ibt~ With Victim ....................... .
5.2.1 ~2~:g\t\::i1>==·.·
Cacheable Without Victim .................... .

.d ~ rr

1llliJ~::'Ai(Jll!1ll;J\i~Qn~~=a~~~:::::::::::::::::::::::::::::::

~:~J;11~
l ·=: '=tn:sn;m
t~illlr:~
.3.4

~~~!~:~1~ 'Aii~c~i~ With -.Vidi~ : : : : : : : : : : : : : : : : :
g:~~==~~=
~~o~~=t~~~~ ~c-~~ ·::::::::::::::
Noncacheable .............................. .

5.2.1)kf

Cacheable Hit ............................. .

\~'.~~~I~;~}

LDx~~ ~~~e.::::::::::::::::::::::::::::::::::

4-3
4-3
4-5
4-7
4-10
4-10
4-10
4-11
4-11
4-11
4-12
4-13
4-13
4-14
4-17
4-20
4-22
4-2;3

4-27
4-29

5-1
5-1
5-1
5-1
5-1
5-1
5-5
5-8
5-11
5-14
5-14
5-18
5-21
5-23
5-23
5-25
5-25

vii

..·.·:-:.:·:·.·.·.
··:·:·:···:·:·:-:-:·:·:·:·:·.·.

.·.·.·.·.·.;.·.··

;.;.;:~'.~:?~}f {:~:~\}~:({'.:'.:'.: : . . . . . .·
:·:-:·:-.·::::·.·:::::::;:;:;:::::;:;::-:-:·::;::.. ·.

.........

. <:?t ··::>:ttfI]=t

tttt
.:::::::::::::::::::::.
'.:'.:}~~}:··

5.2.1 .4.2
5.2.1.4.3
5.2.1 .4.4
5.2.1.5
5.2.1.5.1
5.2.1 .5.2
5.2.1.5.3
5.2.1 .5.4
5.2.1 .5.5

Cacheable Miss ................... .
· Noncacheable .................. .
1/0 Space ..................... .
STx_C ........................ .
Cacheable Hit ............. .
Cacheable Miss ...... .
Noncacheable ....... .
1/0 Space .............. .
Fail .................... .

. .: : .: : :

.:~;~:~.·:~.:j:~;.::~·': :~.:~:~{ ..

;:~:~:~
;:~:~:~:~

~:! ~:d:::::::: ::?i~!~l1.;:: :::~~;'Jl.~!;:r:::::::::
g:::::: :~S'· j'~l!'. 1'. 1 '.!~l!lilfilt!l;; ::::::::::::::::

\illl'I~

5.2.2.5

nl\tN.~:~"1d w~iPP.i.~:·:1:µrst. ~':>=t................... .

;
!:ii;:: ~J~!i;;1~~,~;!~~11:1l1j;.:·::~!Jii: :::::. :::::::::
;:~:~:~.1

P~!llP~··M1t:''.m'.:llll1:::::::::::::::::::::::

~:~:~:~·

:=:nlltllffi~~k:~,·:::::::<: ::::::::::::::::::::::::::

Cacheab.l~:::~i·§~::,.: ... ·:·~· ....................... .
. N9.n:~~~heabl~UHl:l>::· ......................... .

;:~:~:~:~ . '1li!!~ligz::~R~s·:::::::::::::::::::::::::::::
;:~:~:;:: tlllll iII\!lltliJ~~:::::::::::::::::::::::::::::::
5.2.2.sttt>Jt.

nMA

<·'.·'.·'.·:·.

. ~:;:. . :1tl!l\::::::5&i§

!:H~ nJ=E:::~~~ :::::::::.~~1!~~~~~i1t1j~: ::.......... .

5.2.2.6.2
5.2.2.6.3

. . . . . .........

·nush·· .................................. .

·-:.;.:.:.:-:-:·

5-29
5-29
5-33
5-36
5-36
5-36
5-38
5-40
5-40
5-40
5-40
5-40
5-43
5-46
5-46
5-48
5-48
5-48
5-48
5-48
5-50
5-52
5-52
5-52
.5-52
5-55
5-55
5-55
5-55
5-57
5-57
5-57

5-59

5.2.3.3.~1

viii

'l'ransitions ................................... .
CPU to DMA .............................. .
DMA to CPU, Cache not Released .............. .
DMA to CPU, Cache PreviQusly Released ........ .
DMA to DMA, Cache Previously Released ........ .
Preemption ................................... .
1/0 Write Preempted for DMA Write ............ .

5-62
5-62
5-64
5-67
5-69
5-71
5-71

5.2.4
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
..

...
·.::::;:::::::;::::::::: ...

6 DECchip 21071 ·CA Electrical Data
6.1
6.2
6.2.1
6.3
6.3.1

6.3.2

7.1
7.2
7.3
7.4

t-:\·J:jj!jj\!l\lii\l!!!i!l\ll\!\llj!jjjj:·:_::n::::::::..

~g~~::ic~i D~~ : : :: : :: : ::i•••i ;!~I~[: ::::~;!!!l~!!:f ::::::::::

Absolute Maximum Ratitjg$.%t:::=U]\\\:~::,1++. ~ .... -~,< .......... .
AC Electrical Data ..... ...=~,.. YLf . .. ">T:tmm:@::~::::................. .
Clocks . . . . . . . . . <~-=:ii:~::;;~,-::~'==-~- . . . . ·:·" >~:;:=~;;::~\!!:/'~ · · · · · · · · · · · · · ·
Signals . . .
. . . .- =~=\:u:tL~:=:=•=... . . . . . . . . . . . . . . . . . . . . . .
·.·.·.··:·:·:·········:::::·····:;'.·.·.

Power-up '.: =: ..·i!.l: :_j li. .rnP>:=.,... . .===~t::-.:·.il.l.1!·1.111~:.J: ~> . . . . . . . . . . . . . . . . . . . . . . .
Internal ReseC<::UH:::t:.:>:~> .... ' '.\}{:_.-{(...................... .
State of Pins on :Reii.~·:.l§~rtion ==~= ....................... .
Configurat~pp,,~;t,~r Res~~l:R~~~$ertion .................... .

6-1
6-1
6-1
6-3
6-3
6-5

7-1
7-1
7-1
7-2

Part II

8.1

.APECehip 2fiiiffiD.i?Pin List ........................... .

{\i!::P~~ml~d sysBus Signal Description ...................... .
:::f?]~~g. 1 · ·<::rn:'~~l\9.r<33 :5> .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2

.;;1; ;;Ri:mt
8.2~4.ff:t?:
17

/}ff/

I :JI~
.'
1 ••. . .
::tf'/?'6~2~7

~-~:1:0;·:::: :::::::::::::::::::::::::::::
cpuHoldAck ..................................... .

!~g~t:~?o»
::::::::::::::::::::::::::::::::::::::
ioDataRdy ...................................... .

· ' <:"a{a~S>=:=:::. ioLineSek 1:0> ................................... .
8J;i;~,=,,i· . \:\} ioRequest<l:O> ................................... .
8.2. f(j}}? ioGrant ......................................... .

8-1

8-5
8-6
8-6

8-7
8-7
8-8
8-8

8-9
8-9
8-10
8-10

8.3
Detailed PCI Signal Descriptions ............... .
8.3.0.1
MemReql ........................ .
8.3.0.2
MemAckl ........................ .
8.4
Detailed epiBus Signal Descriptions . . . . . . ..
8.4.1
epiData<31:0> ................... .
8.4.2
epiBEnErr<3:0> ........... .
8.4.3
epiAdr Signals ............ .
8.4.3.1
epiOWSel ................. .
8.4.3.2
epiLineSekl:O> .............. .
8.4.3.3
epiSelDMA .............. !.·.·~=-=·~...... .
8.4.3.4
epiFromIOB ........... ~=J!::~!Mii~i!~::::t+. ~ ... .
8.4.3.5
8.4.3.6
8.4.4
Miscellaneous Pin Descrip:ti9.ai.Ifa::=~=··· ..... =~<J:WtC ......... .
8.4.4.1
intHwo .......... /~:tummHrn:rn::=t~=··· .... ~<

::~~~~e:a~~~.

.......... .

resetL .......... =:+:-.Xlf ••• ··=~\frili%fW:t::+==-· .•..••••.•••.••

8.4.4.2

8.4.4.3
8.4.4.4
8.4.5
8.4.5.1

Hi:!

:::::::j(jl::i:<:\:';~~lll~l!ii;i :::::::::::

clktx2 .......•ddff:t:K., ••••• ·:·===?U:lUt:?: •••.•••.•.••.•
clk2ref .<}>~==-· ...·==:<y:~j\!I:l\[ll\l:b.,._ ..... ·.>?'.~ .............. .
Test Signal~<:~::}<.~&>:=·~ ...·-=:~'\@~:m::~:::j~h=>=-.· .................. .
testMode .•tbt~::::Uk:+:-.· ... >+<:urn:r·.................. .

~1i1li1~1i~:!:'.w!~!~il;lilii···'.'.!~::::::::::::::::::::

8.5

DECchip 21071-DALJ?.l.n::~~H~.ignmeht ..................... .

8.6

DECch!:p:::~:f671~.Q~='M,~~hanfoal
Specification ............... .
.............
.•...•.•.
.·:=:=:;::::<·.

::~:~

~:~\ilij~~!~1lfr~~~~tl;:i~~~~i Li~t· :::::::
:-:=:=:::;:)~(

·:-::···.·

8-12
8-12
8-12
8-13
8-13
8-14
8-14
8-15
8-15
8-15
8-16
8-16
8-16
8-16
8-16
8-16
8-16
8-17
8-17
8-17
8-17
8-18
8-23
8-26

9 DECchip ,aio71~~18.·:-~rcl)it;;ture
Overview
....
····.··-··:.

9 .1

-.::;::::::::··-:-:-:-:-:-:-:-:-

-:-:.;-:-:-:-:-:-:.;-:-·

.-~Yi.Sh~ Int~if.l#.iil.t¢liitecture . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1.1 _,,Jiti=lA.ddress 150cBae· ~ ...............•..................

. !liilli11:'.ll\jji/li~~ .~~ ~~~ ;~~~c:~~n:s::::::::::::::::::::
J

;

~:~:~;!lfCI~rl'!:!:~~:i:~o~· :::::::::::::::::::::::::::

't.UY·]_-···_:t>::. 9.,~:g~g)t=·

DMA Write Buffer ................................ .
DMA Read Buffer ................................ .
· '>:{/:J~~?A::
PCI Burst Length and Prefetching .................... .
·::'9.kz~s:t\t=:.. PCI Burst Order ................................. .
9.2' .ar::::=-:·U·· > PCI Parity Support ............................... .
9.2.7 ·.····
PCI Exclusive Access .............................. .

·=::=;:::y·+·?f·:O:~t\g~$:

9-2
9-3
9-3
9-3
9-4
9-4
9-4

9-5
9-6
9-6
9--8
9--8
9-8

9.2.8
PCI Bus Parking ........................ .
9.2.9
PCI Retry Timeout .................... .
9.2.10
PCI Master Timeout .................. .
9.2.11
Address Stepping in Configuration Cycles .
9.3
Transactions ........................ .
9.3.1
sysBus Transactions ......... .
9.3.1.1
CPU-Initiated Transactions
PCI-Initiated Transactions ..... '""' ' ' "' ::,::>:'::;::::.
9.3.1.2
9.3.2
PCI Transactions . . . . . . . . . . . . . . . . . ,. ·::::~q::.:~Jfl!~Jil!~:li~:-[:;rn:\:
9.4
Miscellaneous Architectural Issues ·. .:.:/':':~::-.:.....
9.4.1
::...........
9.4.2
9.4.3
Guaranteed Access Time Mod~:i$~ppotFf~r:::~nt~l 82375EB
and 82378IB ISA/EISA Brjglg~~illL:~......··::~<Ji:'(F( ......... .
9.5
Interrupts ............. Ai@lX@GOW:::t,..:. · .....·'"~ ... ·. · . · · · ·
9.6
Error Handling ....... :.+:2:~:mf ... ··:::::::n~::;1::;1ttt::~::.- ............. .

~:!~1~::~:::futi~~

~:~:~ .1

:::::::: : :t:i:!~iJj[jJ[!~· :!~!l.i[:\J\~j: j~j!: ~H;: :~.

cPuN~n~:~:~::~::~~~~lr~iH:L:::. :: :--:~:::::::::~::::~:::::r::::::::: :·:::::

9. 6.1 .2

Target .AbQ.ft J~rr,prs .··::~'<U:::~::::~::::~::::~t~:,... . . . . . . . . . . . . . . . . . . .

9.6.1.5

wrrne.:::m*'t~t::J~:>ant:Y>Ef:t<l.r~f>::~

~:~:~:!
~:~:~·G
~:~:~:~

~:~:~:!

~!il~'!:a~•,~l!·::i~;!i~i::::::::::::::::::::

....................... .

DM~~~,;~~;;.;: :·::;:!::::::::::::::::::::::::
~i.e:tfiit~!~~~*llb'.;s·:::::::::::::::::::::::::

.;1l:o~T~!at: .~~~~ :::::::::::::::::::::::::

9.6.2.4.1
:\I?tlaead· Correctable Data Error .................. .
9.6.2.4.2 •·:=:::::::::::· <:t]tfild.Uni6.tfectable Data Error ................ .
7
1
1

~:~:~:~;. i\~ ~!~tl!!~~:~d ~: !~:a~\: Dai~.E~~~::::::

· • t !j·~;.~T i\)il(lilll!t~r/~~~~ ~~ .~~~~~~~~ ~~ .~~~~~~~e
tgl. 6~2i~~h
-:-:::<$.4.a.W¢r/Gather Errors . . . . . . . . . . . . . . . . . . . . . . . . . . .

.....

:::::-:Ji.=::·;_.!':

9-9
9-10
9-10
9-10
9-12
9-13
9-14
9-14
9-14
9-15
9-17
9-17
9-18
9-18
9-19
9-19
9-19
9-20
9-20
9-20
9-21
9-21
9-21
9-22
9-22
9-23
9-23
9-24
9-24
9-24

i i;

10 DECchip 21071-DA Programmer's Reference

~ ~: ~ Add~;~'Z::e~::a~~~~ ~ PCi s~~~ :::::::.~111,~1~~l~1~iil!·ff{k
.1

10-1
PCI Sparse Memory Space - 2 0000 OOQQihi\::[g FFFF .."''<@:'])}}'"
FFFF ...................8:,..••••• 'Y:tl\tWb:::.:......... ·-~'<:?
10-3
PCI Dense Memory Space - S%QQOO ,Q_ooo···:,~'\a:::'JIEJ.f:..
FFFF ...... •·• .......... >'?. .,::}]%>.::...... ··::::vunnrn:::L., ..
10-7
10-8

10.1.1.1

10.1.1.2

~~~~=~e1~~1-~~c~S~ ~~~~e ~?~§~llr~.,F~~ ·

10.1.1.3
10.1.1.4

FFFF . . . . . . . . . . . . . . . . . ·L::':dt:>::+. . • . .·>>turnrnt:+ . . . . . .
PCI Interrupt Acknowledg,~$~@.~~:]ey~le Sp'~!i6~( 1 BOOO
0000 .. 1 BFFF FFFF .. J@\{:( ..-,,~<Jt#U&+,.•...........
10.1.1.6
PCI Configuration Spa~~r+·i)1$.000 OOOtiMrn:·j}FFFF
FFFF ............/dQWd/i/t:t:•...... .>?( . ......... .
10.1.2
PCI To Physical Mernocy'·~a;J'~~ini::@:+,,~,.· .............. .
DECchip 21071-DA Interp@[:D~gisters''~'T::\[))):~::j):[~(; ............. .
10.2
10.2.1
Register Ov~fv~-~w . >>t::~:)@@}t::~,,._. . . . . ."'.:\{( . . · · · · · · · · · · · · ·
10.2.2
1
10.2.2.1
10.2~2.2
Dfagg9~tic Cdrtt,f:Q)Viin~J. Statiis(Register CDCSR) - 1 AOOO

10-10

10.1.1.5

::::::

Regi~:i~:te&,:11: ~i!ll!~ill!;i;;:::::::::::::::::::

10-11
10-13
10-20
10-20
10-21
10-21

OOOQ@HEx) .. ~ ·:~<rnlWH@L>::· ....................... .

10-21

10.2.2.3
10.2.2.4
10.2.2.5

~:!~1 a!"i1Jl:i~:~~~~r-·/fo~~o ~~4g, ~~ciO ···

10-28

10.2.2.6

_,~Q~{B'is'=:·:~~~ters·T~2 - 1 AOOO 0100 and 1 AOOO 0120

10.2.2.7

\)J{QJ..Mg~k Rem~ters 1-2 - 1 AOOO 0140 and 1 AOOO 0160

PCI.Eft~~%\\.¥i4ress :Re~~~~~fr:~ 1 AOOO 0020 (HEX) ..... .
8

10-29

:}(ff:EX) .A/\/:' . if# . . . . . . . . . · . · . · . · · · · · · · · · · · · · · · · ·

10-30

):'-"'·:· ·tasxmr....::antr ............................... .

10-31

10.2.2.8 .,,,.,.,.:-,••··· Ii&$:t)!A,1.qf:i.~~i:()E~tension Register 0 (HAXRO) - 1 AOOO
. : : : : : :\:,::f 01sO'tMEXf''''~ ................................. .
10.2.2'~S:{_J{\:::::::::... Host Address Extension Register 1 (HAXRl) - 1 AOOO

·. ·.·u:nunnn:olAo<HEx> .................................. .

10 .2.'~a.A::1

10~2-~2uf2

xii

10~27

OQEQ}('HExt .. :<<U.'·}3< ......................... .

. '.'.'.' .~Jf!~;\~0 'ii%!fi~~~~s. ~~~~s~~~ ~e~~~~ ~. :~~ ~ .1. ~~~~ .. .
; ; ; 1!

10-11

~IJ~'.~.13
' ~;~;~J~!ilt·

PCt' Master Latency Timer Register - 1 AOOOO 0 lEO ... .
TLB Tag Registers 0-7 - 1 AOOO 0200 - 1 AOOO 02EO

10-32
10-32
10-32
10-34

~~b~~ Re~~t~~~ o:i : i ·Aooo 0300 ·_. i AOOO. 03EO ...
~!i~ti~~ ·B~~; i~~~idat~ "Afi (TBiA) : i.AOOO 0400 ..

10-35

(HEX) ...................................... .

10-36

11 DECchip 21071-DA Transactions and Timing Diagr.1m,'-.

1 111 1 1

~u~ CPUf:~~t~~1~::rg ::i!·::::::::: :,~ i;t1!~~l ~ ~ ~ ~~llit1u1v

11.1.3
CSR Space 1/0 Read. . . . . . . . . .
. : .. )ii\i.:i:;~::::~:;;~:+;. \~ ..... ·:· · :· · ·
11.1.4
CSR Space 110 Write . . . . . . . .
........ ~····x~@:'<lfr:·:~\\ ... .
11.1.5
Memory Barrier . . . . . . . . . . . . . . . . /f:Lk:.......... ." Yt\N%\\•· ..
11.2
PCI-Initiated Transactions ........... ··~\<~:=:m:::W%~:>. . · ... "'>T=·for·.. .

:g ::::~~ ~~~:t~ ~~;i:•~~~~~ 1;~;;.; ::: :::

~~ :~:~

11.2.3
PCI Exclusive Access to Syste1~#il!M.~m9.f.Yfot.......... ··=:=:::t:t ...... .
11.2.4
Scatter/Gather Map Read .. /J.:{c· .. "'Yf.::b~::::~rn:::t.~............ .
11 .3
epiBus Arbitration . . . . . . . . ~. x:@{:~\:\:ffi>~.. • • • . ·:···=~q@:\l\'~.\)•· · · · · · · · · · ·
::::::::;::::::::::::\~::

11-1
11-3
11-4
11-4
11-4
11-5
11-5
11-7
11-8
11-8
11-9

::::{:: ...

12 DECchip 21071-DA Electrica.hJ.lt; · · · : \,•: : : : : : : :'.,'.\·\: : :·:"· ·: :
.·.·.·.·.·.;.·.·.·.·.··.·.

·.·.·.·.·.·.··:;:::;:::::

12.1
Introduction . . ....(·~···. . . . .<t:fa@l&llib::. ~. . . . . . :""~<:<'··. . . . . . . . . . . . . . .
DC Electrical nijfit.:f· ..~:·.• .. ·.::'?U@UI~fab::::,........................ .
12.2
12.2.1
12.3
AC
12.3.1
Clocks<:].=i:.::.=~d::L~.. . . . ."··~<J:{::.:··t"t>.:~ .. . . . . . . . . . . · · . · · · · · · · · · ·
12.3.2
Signals ·.··yx~:::~·]·:\%::".... ~··'; n~m·.:.:.~Ut·...................... .

::~~=l~!~4!•~~.~~:''.'.1!1l~lli'.:::::::::::::::::::
·.·.·::/~\\~\~}}:\:::::..

12-1
12-1
12-1
12-3
12-3
12-5

"<:\~~~>::··

7Q,A::·P.~:~f4;:P==@f:ld Initialization

13 DECchip 21071.

.·:-:-:-:-:-:-:.:-:-:-:·:·:·:·:·'.·:·:-:-:·:·:-:.;-.

Part Ill

··:··-:-:-:-:-:;.:.;.;-:-·

Power-GP..rnmy:y:;n:.:~.\.·~. :·t=. . . . . . . . . .<.,.. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intern~l:].~teset.;=::::::::::~=:c . A>fa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1
13.2
13.3
13.4

~a.~:art::~;rt;~~:::::::::::::::::::::
-:.:.:-:-:-:·:·:····

:-:·=·./~\)) ::=:::::::: .)/ }}}'.:'.·

......

·.·.·.··.·.·.·.·.·.--:: ··.·.·.·····

13-1
13-1
13-1
13-2

.....

;-:-:-:.: ::;:;:·:;:-:;::;::·.
··.·.-.·

::::::::'./:·····

····=::::::::;::::::::::::::::::::;::::.

::1:4.~f. ·q·§gphip ..21:i(lj:B.~. A Pin Descriptions

............

.):.:'::::=:::=:::: •·

1
1

·-:-:-:-:-:-:-: ·····

<::::::-:-:.:-:-:····-·.·.·

14~'1:i'i t\:Jntroductibif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

·r ~~;II ~~~~~t ;i~;j-~!~~t~~~· ::::::::::::::::::::::::::::

< i;j ~~=:~. 1

CPU:S~~=<~~~~a:s~!1:i~o~.::::::::::::::::::::::

14-1
14-1
14-4

14-5
14-5

xiii

14.3.2
14.3.2.1
14.3.2.2
14.3.2.3
14.3.2.4
14.3.2.5
14.3.2.6
14.3.2.7
14.3.3
14.3.3.1
14.3.3.2

Cache/Memory Data Path Control ........... .
drvSysData .. ·.................... .
drvSysCSR ....................... .
drvMemData ................... .
sysIORead ................... .
subCmd<l:O> .......... .
sysCmd<2:0> ........... .
memCmd<3:1> ............. .
epiBus Signal Descriptions ........ .
epiData<31:0> ........... ~-~=-=·~--· ... .
epiBEnErr<3:0> ........ ~:=:@:~:]:]!:j\\}:::..:. .~ ... .

H:H: :=E:~~::~;: :::::; m~1il~ li'.;c~:;~ '.[. ·~1~....
1~1 ~1 ~1~:i· ::::::::::
14.3.3.6
14.3.3.7
14.3.3.a
9

epiOWSel ........ s:~\i\l\Wtij\:,:;::::~::++
~==~ .......... .
epiLineSel<l:O> .._.)==)ml° ... =~==+::~mUt{\=:==~=--· ............. .
ioLineSek1:0> .•::trn:rnm:t. ..... ~--==~==vrn:rnu~ ............. .

~!:~:!· Mei:~~~S1n.~;:!lll~i~lir~
..:.:: ::': :::::::::::::::
mem.Pata<a-t;()$iW\m~mPat~O$FW\f·.................. .

14.3.4.1

~::~:~.1 Mis~-IN~.'.~~~~J:l~Jllif•;,.:::':::::::::::::::::::::

14.3.5.2

~::~:~:!
~::~:~:~
~::;:~:~

c1k2rer\tUt:·D\:h:==· ....-=·yu.mur·...................... .

:::t!d~·:\:'~!lli!!Ji;i'.:.: :·: ::::::::::::::::::::::::
.•,,,l~!;~!j: ;. ;:'.;:~::::::::::::::::::::::::::::

::\illl\~~11?:: Il.lililll~r:::::::::::::::::::::::::::::::

1
~::~
~-t~
111tfllf ~:::;:t~ ~. : : : : : : : : : : : : : : : : : :
14.5.1_=J\\\:\\]f\i$ignal 'IYP=e~f?=~---~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1

Ali!!,~!~ ; jjr1111=~~i~~~;~:,S;.~~:t~:i~~~t i:.i~t· :::::::

.,.: : : : ;:====: :=:==· · :=14~§:\JI\\DECClii#'!~:~g11-BA Mechanical Specification ............... .
-:::t:.:::::.:::·:u:::-·

\(/:::=::;::::

,ijj:j!\.!:{'
··:·:-.::::::::::::::::::::::::::::::·::::::::::::::::::=::::::::

xiv

14-6
14-6
14-6

14-7
14-9
14-10
14-10
14-11
14-11
14-12
14-12
14-13
14-13
14-13
14-13
14-13
14-14
14-14
14-14
14-14
14-14
14-14
14-14
14-15
14-15
14-15
14-17
14-19
14-20
14-22
14-26
14-29

15 DECchip 21071 ·BA Architecture Overview
Introduction ............................ .
15.1
Bus Widths .......................... .
15.2
15.2.1
sysData ......................... .
15.2.2
memData ................ .
15.2.3
epiData ................. .
Description of 21071-BA Architecture .
15.3
15.3.1
Memory Read Buffer ............ .
15.3.2
1/0 Read Buffer and Merge Buffer ..... .
1/0 Write Buffer and DMA Read;:::Bttffer..... .
15.3.3
15.3.4
11 1
15.3.5
15.3.6
15.4
15.4.1
:::::::::::
15.4.2

:;~:£J~~i~~~~ ;;l ~il!'.'~ ~ : ~ ~l~,l lI1i1~1i· ::::::::::
Da:Fsi: ::~i ~~~~~f~;(l~!fj:i~l~l~l~~,,~l~ii%': :'~t~
:.::'.:{({\~~. ·-~-~-;.;-:·:·:···:···

.. :::::::::.

.·:::::::::=::.·.·

15-2
15-2
15-3
15-3
15-3
15-4
15-4
15-4
15-5
15-5
15-5
15-6
15-6
15-6

.··:::;:;::::::;::··

1a DECchip 21011-eA'::1t-aqa9.~ion's("nl::::~f:lr!1ing Diagrams
.·:-:-:-:-:.:-:::·:-:-:-:-:-:-:-:·

···.-.·.·.·.;.·.·.:-:-:-:-··:-:-·

:~::.1 sysBc';J~Ei::~\~i~f~'~!i;;.;;::'.%'.::::::::::::::::::::
16.1 .2

:~:::!

16.1.5
16.1.6

~~:~:~

CPU Meirioeyj:'t{g~q with"Vi~~~m< ..................... .

gg :::~~·,•rJ~:::;:bi.;Mo~i1~~~ie.::::::::::::
..
......................... .
sTx_Qe:Hit:'rn~rn:++

-~'''>1.Mi:~:m.<

s~1Jt:::~rnst:H{::r. ~::..·

.. >t........................... .

t~111:::~~~~·!1:::~::::::" J:i![llil~\:,::::::::::::::::::::::::::::::::

:~:::~o ;!'1t~~·11irt&g:1~~~:~f~.::::::::::::::::::::
:~:~.1Illllt ~~~!'!~~s!:)!:~c~~~~. ::::::::::::::::::

.:::::<HW1:$.~?:~.2 '"\\[tlQliW.~ite to System Memory ....................... .
:UJ:::tHkt:&~a~t\:::: epiBtt$:lf.iih$.actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
,:::::.::::::m:t::::-· 1·6~3'Hil
DlMA}Reid Buffer to The 21071-DA ................... .
_,,::-\\.\:)\\_if:'·

<· -{·\·:::'",,

16.3.:.at:'\::
1§~~:~~'[/'

':%·/.:\,'%.\Ht:J§tl\~4

110 w~iie Buffer to 21011-DA ....................... .
21071-DA to DMA Write Buffer ...................... .
21071-DA to 1/0 Read Buffer ........................ .

16--1
16--1
16--1
16--1
16--2
16--2
16--2
16--2
16--2
16--2
16--2
16--3
16--3
16--3
16--4
16-4

16--6
16--6
16--9

17 DECchip 21071-BA Electrical Data
17.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2
DC Electrical Data ..................... .
17.2.1
Absolute Maximum Ratings .......... .
17.3
AC Electrical Data ............. .
17.3.1
Clocks .................. .
17.3.2
Signals .................... .
:::::::::'.'.:'.:;:::::'.::: ~:::::::;:.-

:: :

·:::::::::::::·:-:::::::::{:~>···

18 DECchip 21071-BA Power-Up and lniJ!,@Jll!.atioH::::-_···:.·::::::::.·i:=::t::-··
18.1
Power-Up ...................Arn·:]'.::~:::.~::::~~:.·~,:.!~HL~. · .. ··.>?t:X"~ . . . . . .
18.2
18.3

Internal Reset .............. /V@( . .·''~'\HQ:Uili:l\:,,.... . . . . • . . . . .
State of Pins on Reset assertion:t@==~i',L~ .... "~'''::y:g~:"·~:i':~:\+. . . . . . . . . .

18-1
18-1
18-1

.:}}~ ·:-:-:-:::::.:-::::::;:;:>:-;.:--..

A PALcode Equations

··:::\~!~)~=~~~:~:~:}{}:::.

··::::::::;:::::}:::::
····:::;:;:

····:::::::::::·:-:-:-:-:-·-·.·.·.·.·.

Figures
1-1
2-1
2-2
3-1
3-2
3-3
3-4

3-5
4-1

DECch!tt:g).071 ~n:::jtjijfpf!Cchi~!"~l072-AA System Block

~~~:1 1!1~1~·;:~:~~,i~~~~- :::::::::::::::::::

DECchip 21011;¢1N:::l?~~kaging' Dimension Information .... .

21011~.oAJ}lQ~k ni~l~m'\:.......................... .

Cac9~,ji§U1b.$~~~pt for '~:':5..12 KB Cache ................. .
Mem9!Y S~#Q.fg@.~~ation .......................... .
PrJ.~~~~~:)Jft~ct ij~c Operation ..................... .
J:fV.id~)\\$giY.~te..mi::ij)$ing a DECchip 21071-AA Chipset and a

,,~::=;:::P:umHlt.rwm~:::B!#f~r

............................... .

./':'t:::1:::rnP.eneral d'HHtr6lRegister ........................... .

""''${[l[[\::ltt9.r and Diagnostic Status Register ................. .
"\''Tig[$lb.~ple Register ............................... .
Eri6fil[$.~w Address Register ......................... .
Error ifigh Address Register ........................ .
LDx_L Low Address Register ........................ .
LDx_L High Address Register ....................... .
Video Frame Pointer Register . . . . . . . . . . . . . . . . . . . . . . . .
Presence Detect Low Data Register . . . . . . . . . . . . . . . . . . . .
Presence Detect High Data Register . . . . . . . . . . . . . . . . . . .

xvi

1-3
2-29
2-38
3-1
3-7
3-20
3-29
3-32
4-3
4-6
4-8
4-10
4-10
4-11
4-11
4-12
4-13
4-13

4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
5-1
5-2

BankSetO Base Address Register ............ .
BankSet 0-7 Configuration Register ....... .
Bankset8 Configuration Register ......... .
Bankset Timing Register A .......... .
Bankset Timing Register B ... .
Global Timing Register ..... .
Refresh Timing Register ........ .
Memory Write Timing ............ .
Memory Read timing .........~::f:?::~:::::r.:-:-~ ••••

5-3
5-4

Timing of CPU Read
......... .
Timing of CPU Read Bio¢i.:~::::·~~~tUO Spac~::O: .......... .

5-5
5-6

~=== :~ g:~ :::: :!:~~:
gd!lllt~tj~
........
.
Bloc~@~19~~~heab1J<~:::::~::![~:w:t
~=== :g~. ~:. 11~:::~1~1:::. ~~m ... .

4-18
4-19
4-21
4-22
4-26
4-27
5-3
5-6
5-9
5-12
5-16

Victim ... ·.·.·.·:·
:it)f}
·.;>+arn:mt+::.:
....... ~· ............... .
...·.··:·:·:·· .....
.·.
··.·.··:::·'.·'.·:::::::::::::::::::·:·.·.
Timing of CPU' W.P.~:J;~Iock~::1(ijp~i.~beable or No Allocate .. .
Timing:::9~':9:fU writ!·.[\~~9,~~ R~rii6tjf°I/O Space .......... .
Timin~fdri:g~lhkDx_t';':''i\;iRR~~' Cacheable Hit ......... .
Timing of C:Rl)U$~...C Su(fo~~q,s:~ Hit, Cacheable, Allocate .. .
Timing of CPU's~J.CJ:)._ucce~ds, Miss, Cacheable, Allocate,
Victim.-:·•"''''''"'>•.·· .. ?t@H.%//L.......................... .
TimtP:Ji.:·-~£-:cg{jJ-:::$Tx_C"TF.~ifis ......................... .
Ti•~f'of q:py':B~rfier or Fetch or FetchM ............. .
Tiri}lg:::!>.f:\QMA IJ."1:~, Cacheable, Hit ................. .
:dt>.U.nil~gl\l9~tP~L.t\Ji~~d, Cacheable, Miss ................ .

5-19
5-22
5-24
5-27
5-31

............................................ .

5-49

Timing:::bf DMA Write Masked, Cacheable, Hit .......... .
Timing of DMA Flush ............................. .
Switch From CPU Read to CPU Write ................. .
:.:s;a.2,
Switch From DMA Read Hit to DMA Write ............ .
: 54.aa:::_::->:: DMA Write Hit To DMA White ....................... .
~~4::::-':):j·jHC:: Switch from CPU read to DMA write .................. .

5-51
5-54
5-56
5-58
5-60
5-61
5-63

5-7
5-8

5-9
5-10
5-11
5-12
5-13
5-14
5-15

~~~ ,..f11;liif::: ,~I~;!, ~~~:~~e:~~>F~1i~~~d ii; ·nMA .. .

·.·.·.·.·

··::::::::n::ti:1.~1d

·=·==-:· :::u::$¥1's:::::..
··==:=::~mli't:9.f DMA Write, Cacheable, Miss, Followed by CPU
.::::::::::::=::
................. .
:._,-:_:,~-~:~:~=~,.~:~- _~:~-~:~:~=~:~=~:~:~-~.r: : . ···=::::::::::;::::=::::::=::::::.
Wrlti@dhh
.................. · · · · · · · · · · · · · · · · · · · · · · ·

.·:rm: .:.

5-34
5-37
5-39
5-42
5-44
5-47

xvii

5-25
5-26
5-27

Switch From DMA Write Hit to CPU Write .............. .
Switch From DMA Read to CPU Write ..... ·-=i:~::m:~::m:t:b~,.... .

5-28
5-29

Switch From CPU Released To DMA Write\d}i\lT\>~-....... .·"'?t?
Timing of CPU Write Block to yq:::st)a.c~, Pr~'Jffi~~ij/py_ a
DMA Read Hit .............. ":'+'·~ .A](:t;,,,,.
.... ··:<%~%%\:@:>:.,
.•
·.·.··.···.·.·.··.·.··:····
···.·.·.·.···.·.·.·.·.;.·.·.·
Timing of Regular Writes ......... :·"'?T\\~I~t~::::~:\::,~.... '.""?Uk .. .
0

~';!~h. ~0.~ .~~~. ~1~~~~ ~ ~~~ .':~~~'. :tf~~~'lllll1!,h, 5-68
.·.·.-.·.·.·.·.·.-.·...·.·.·

5-30
5-31
5-32
5-33

5-34
5-35
5-36
6-1
6-2
6-3

8-1
8-2
9-1
10-1
10-2
10-3
1Q-4

10-5

·.·.··.·.·.·.··.:·:.:·:·

~=:~ ~1::gF:~:d·b; ~·p·,l•:;::!llii~:::::

Memory Read Followed by a 11*niP~l.il.~tMem~ey
Write .....................
,,JWt ..... ·-,,~<@?ibl+......... .
.··.·.•.·.·.···.·.·.·.···.·
··.·.·.····.·-:-:-:-:-·
Memory Write Followed l.JY:=:~::\Jl.*-gidMode Memoi-y Write ....
Memory Write Followe4.. }}l:ji"'N'6ri.f:pjg~LMode Memory
Read . . . . . . . . . . ...-.·.·.··.·.·.;.·.·.··:·:·······
..idlflh ..... "';'\t&Ufl\
. . . . . . . . . .....
..............·.··

~:~~r;p~-C4;Q;~;~111a~·::,: ::': ::::::::::::::::
DECchip,_,~1071"'CJ\!\Q\l.tp~t D~t~i,:\!l~asurement ......... .
DECch~pi:\gJ::(lfl-CA'''sit.tjP,:::.fm.p. Hofd. Time Measurement ... .
DECchi.~\2J;qi,tt:Pf.\ Pi~Jfiij\.lp~am .................. .
DECchip 21Cf'llf.P:~i'Jbickaif'rig''nimension Information .... .

''?//:/(f\:::.JQ4lf

xviii

5-85
5-87
6-3
6-5
6-5

8-18
8-27

: : : : : : : : : : : : : : : : : : : :

lflt:•;/:,,;=s:~: ~~%~to~:~:

........ .

8e~rst0er0
-:' \fps':-:Y;:~s,:;l_~:~-~:'.;,.'.~-.:.:_:.:~:"°.:_~-: .·-.·._:'.·_._·r.·rAorddArdedssreRssegiR·
··
I:)~
0

.._',·:'_'..', :,..m : _ ·

•

••

:::::::

1o21'4rn<:.:!:f'· Master Latency Timer Register ...................... .

10-15 .·

5-81
5-84

9-2

~~l~I' i:c7~=~
i!;:~1::~~;e~s. ~-~.::::::::::::::::::::::::
PCI Mask Registers 1-2 ............................ .
11111111~., :::: ~~::: ~::::::: ::::: !~=~

. . •·•·• 1!';:,.

5-73
5-75
5-76
5-79

~~~:~iitj~~=l~i~a~i~~·::::::: ::::::::: 10-6
0
10-10
10-15
~1151~i-~:!:~l~~. ~.

.,/l:::/{~ddress"'''flt%'\?'"'~ ................................. .
10-6 ., t:::rnrn:~:j:pj~gnostic Control and Status Register (DCSR) ......... .

.: : :_.:,.:,,/: ::::t::-_j:\::ji!Ozj?t.
:'.: :'''1t>f4h%\ ..

5-70

TLB Tag Registers 0-7 ............................. .

10-18
10-19
10-22
10-27
10-28
10-29
10-30
10-31
10-32
10-32
10-34
10-35

10-16
12-1
12-2
12-3
14-1
14-2
15-1
16-1
16-2
16-3
17-1
17-2
17-3

TLB Data Registers 0-7 . . . .. . . . . . . . . . . . . . . . . .·~·.·:-~:-:-~.·.. . . . .
DECchip 21071-DA Clock Signals ......... ~-::i!~%!::~!iliiifo+.:~ ..
DECchip 21071-DA Output Delay Measureme6.\!:!~f~::::>~t~rn:=:~:\::~\::::;tt:.;..
DECchip 21071-DA Setup and Hold Time M~~~q~ement·:::Y~%\l:\~i!]):: 12-6

:::

~~~~~~: ~~~~~::~:~~~~~~~;~~~~!I•~~,: :nr
DECchip 21011-BA Block Diagra~::::'. -~=:m=.•:.::~:::\:>,,.~ ... :,:y~::irnm::.:t ..

~=~:: :!~~l~~:t:~~ ~~~:::wm::,:;.:::::

Timing of 21071-DA to 1/0 Re~q)::JiU.l~t:}J!~sf~t::Y:~:::!/~ ..... .
DECchip 21071-BA Clock Sigrii.}$.::::·:·:···:::::~<:}·~:·::~:i:\~:!1>:::~:·.· .. ·....... .
Output Delay MeasuremeP.tJ?:~:\:I!!L.......·-::~<t~:rnrn::t· ......... .
Setup and Hold Time Me~ wi~ l.:'._it_: _i.: .i:_·=_t_.·:.:·:_:j_[_: _:"_:·_: _:f_: _: _: ~:·.· .. -: : :~ .......... .
-:::::::::::.:::=::

14-21
14-30
15-2
16-5
16-8

16-10
17-3
17-5
17-6

·::::::wm::::I:!t>

Tables
·:·:-:-:-:-:·:::::::::::::::;:::;:-.

2-1

2-2

~::!
2-5
2-6

2-1
2-8
2-9

~=~~

DECchip 21671-q#::::pjp List::::::::w~::::~::]:::t\:• ................. .
CPU-Iqjt.i~ted 'rf'iin$.~¢tj~m. Enco'di~gs ................. .
1

~:~:!Ritl:~i:'.1 '. !~~1111·;: ::::::::::::::::::::::
cpuCReq EffecFii]!-:J:?~~gOE_l and bcDataOE_l .......... .
ioReq~~~t~;t;Q?... Ent6ijj(ig$.\· . . . . . . . . . . . . . . . . . . . . . . . . . .
ioCm4.~~:~oj·!:_$.ijcfoding~''%f~ .......................... .
ioQA¢.J~ l:Q*\:!$hc9Wµgs ............................ .
Suij@ltl.JP.iririeci.l~n~ .............................. .

·•·•·. j~'l!~iliilit~~;d~~:~.~~~ .~~~.:::::::::::::
0

2-12.:::: ·.;.· t{f)~Cchip 2io7i-CA Signal Types .............. ·....... .
·-::::::n:{\:i!lipfiQ~pip 21071-CA Alphabetical Pin Assignment List ..... .

~~ll6~ ~~~;~:o~~;~~~a:!8:!~~~~~ ~~t. : : : : : : :

sysBus Address Map .............................. .
Longword Number to memCAS_l[n] Correspondence ...... .
Supported Bankset Sizes and DRAM Configurations for
Different Memory Widths ........................... .
Base Address Comparison .......................... .
Row and Column Address Decode for Bankset<7:0> ...... .

2-1

2-8
2-9
2-10
2-12
2-15
2-16
2-17

2-19
2-20
2-22

2-28
2-30
2-34
3-4
3-11
3-21

3-22
3-23
3-24

xix

3-7

3-8
3-9

4-:-1
4-2
4-3
4-4

4-5
4-6
4-7
4-8.

4-9
4-10
4-11
4-12
4-13
4-14
4-15
6-1
6-2
6-3
6-4

6-5

Row and Column Address Decode for Bankset8 ..
Memory Transaction Scheduling ......... .
Supported Presence Detect Shift Registers
DECchip 21071-CA Register Summary ..
General Control Register .......~::::h~..... .
Error and Diagnostic Status Regi$.~jf.:''
Cache Size Tag Enable Values ...
Maximum Memory Tag Enable Values .
Video Frame Pointer Register ..~''':<://:~:,.;.~ ••.•

4-1
4-4

4-6

:::~:~osc~:!!;::!~:n~:if ~i~\!l~'l~\!lii~;;.,; :......... .

:=::::::::::::~i!Jlll~l\lit;.~ :::: ~!!l~ :
1

::::: :: ::

Global Timing Registei.r:::::. :;:~~·ijf. . .·.;.'.''\%\:::~·:l:::t.]::t:+,,~ . . . • • • . • • • • • • •
Refresh Timing Registir::::=,rn:::i>::. ~ .... ·~-::::<]:m:c=·~ ............. .
Read Timing$.:;::::)~qµatiori'~::::[~f:il:~amm~d Values ........ .
Write Timing~'{ ~gµ~\!9.ns f~Pl!tP.~mmed Values ....... .
Progra:¢jp~µg MeifiMat:i11mJngs . ,?§f'~ .................. .
DECchii}:,:z.ie7J,JJA M:iOOl~mJ~~atings ................ .
DC Para~J:tf.i¢.::¥.~Jµ~s . ~··:.<@.:jj~),):~< ......•.•.•...•.•••..•
DECchip 2107fl()R:,iQl9~~ AC.·Characteristics ........... .
DECcb~PJ~)tJ~f:kCA'::AQ!l·QJ)a.racteristics (Valid Delay) ..... .
DEQ¢.bip:::2:1q7:jJbA. A<fCharacteristics (Setup/Hold

4-9
4-12
4-15
4-16
4-18
4-19
4-21
4-22
4-24
4-24
4-25
6-2
6-2
6-4

6-6

Tirlii.J.}~ . . .~d/ff( . /Mt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-8

DEQ¢.biP::l:tfr71-d@Jjlpin List ........................ .
J}Q.f,i#J.niii~.~t·~action Encodings ................. .
.:=: :-: . :·'.j\j~~JCmd·~2:~qi:jj:lrt~'dings ............................. .
8-4 ··· t'::j):j)\:~9pAck< 1:0> Encodings ............................ .
.: : : : : : J::lt§:,:-. :'\{jj(j~g-~u;1est<l:O> Encodings ......................... .
=-=<··> ::tm=:::a+s@J:::::.
·ni.ti.iJ.itiQn of 21071-DA Pin Names to PCI Pin Names .... .
.::::::::::::;::::::y:::· 8~5PUtit
epiBErl~ri- Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.-:-:•:•: : : : : : : · ·
~::\l!l!ili!!il!li:··:: Longword Selection ............................... .
<::,,,:::::::::::::===::::::::::::..
a. ~.:.:.:.=.:s.:.·•.·.:.:.:.:.: .·:.:.:.:t'" 21071-BA epiBus Interface Function ................. ~
·::::::;:::::::::::::::::::::::::::::::::.
<n::::::s:rn=:s.+aoDECchip 21071-DA Signal Types ..................... .
.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.
·:-=-:<rnns+.ii== ::.
Alphabetical Pin Assignment List .................... .
821:~·:=:::::::-:.::\:J:: DECchip 21071-DA Numerical Pin Assignment List ...... .
10-1
. sysBus Address Map .............................. .

8-1

8-1
8-2
8-3

8-6

8-8
8-9
8-10
8-11

8-13
8-14
8-15
8-17
8-19
8-23
10-2

.,<lI::i::;·;::

.:::;::::;:;::::::~··.
·:·-:·::::::;:·:.·.:·:;:;:;:::;:··

;!:l:!-l:_:_:_:!:_:l_!·..·'.=.::_.:_:

:_,_:._:.~-·;_:~_.i~-~~.:~

:_. :.: =.· =·.· .

}~:}~{{:}~{{:}~:::- .

-:::::::;::;:·:···:·: -:·:·:·:·:-: .. :.

:i~i\~;: •lilll;::,;t~i~i'

10-2

PCI Sparse Memory Space Byte Enable Generation , .

1Q-3
1Q-4

~! ~~:~~~:~;a!~~!:S:~:~~e.r~~~~¥11l!l~J~ll~'l(Jll~;~:li\)j\''~

10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
11-1
12-1
12-2
12-3
12-4
12-5

~! ::: :i~~:: ::~;:ti~~ ·_·p~~~ Miil}.;.;· ... >WiiH!l:I> 10-14
1
~:::~:::r:.:::r~i:~~ ~!'.'.;:1j/\;i;o~::''.\i'.)~\!~l!l~lii•; :: ~ ~~ ~
DECchip 21071-DA Register Summari'===::;m::~::l:M:i~h::::~'"··· ...····~<?C. . .
Diagnostic Control and Status R~g!§.t~.r ..··..:,::Yrn:.~:::·~::·:ifr>:.:•~ . . . . . .
PCI Error Address Register .. ,,{~:i:W~\j'\!:~:.fat+.~ .. >'';t;:\\i::,f~·. . . . . .
sysBus Error Address Registet:]]i('':':'·''>'~{l.::;:::-~::::~b:+,.~. . . :·:··. . . . . . . .

10-20
10-22
10-27
10-28

Host Addre,~f:J$.~µ.si~ri:::IW,1Ji~!\2 ... -~:... . . . . . . . . . . . . . . .
PCI Master . .Lit~6¢~f:[J;imer·"'·R~gj$.~¢.t>:,.. . . . . . . . . . . . . . . . . . .
TLB T~g=::Jw.gist~f§::::qfil:rn··:·fa~:\.•· .. ~::'?t@<" . . . . . . . . . . . . . . . . . . .
TLB nitt~:.:~m~ters ·ofrh:rn.·:rn.>h:~ . . . . . . . .. . . . . . . . . . . . . . . .
epiBus kbitt"t!P~l:~orieyli·~::::.-my·...................... .
DECchip 2107121)-~_:MM,~mum Ratings ................ .
DECcl)..jpA~J:Qfl:l~D.A\D.;q=:.J?.~rametric Values ............. .
DEg¢b~pt2:J:,(>:7·!8DA. Cld~k AC Characteristics ........... .
D&Q~FJip ~io7l-Q~{/\C Characteristics (Valid Delay) ..... .
DEC¢.bi.P=~:i=io71-Q.l.::j\c Characteristics (Setup/Hold

10-33
10-34
10-35
1o-36
11-9
12-2
12-2
12-4
12-7

~;~::~1::e1:~~:~0IB~ll!,lll1i,i;~:: ::'.;~'.'~!~!:·:::::::::: ~~~
~~~:!:e1!:~::s!i;il;~:!i~il!IJ~lli:: ::::::::::::: ~~~

ttr:n.niliMfa\'lW<..... . . ,.:i:Mflf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-1 , ~::.~:i:l)Ec~hipi-igi()~btfBA Pin List ........................ .
14-2 ,;:::: ::::rnl[:$.ysCmd<2';o~·=·:~d subCmd<l:O> Encodings ............ .

\I'::hfilttt.Cmd<3:1> Encodings .......................... .
··:::::~Ptli9.~rr Functions ............................. .
2Hfifii§X epiBus Interface Function ................. .
DECchip 21071-BA Pin Assignments for DECchip 21072-AA
With Parity ..................................... .
DECchip Pin Assignments for DECchip 21072-AA With ECC

12-7
14-1
14-7
14-10
14-11
14-12
14-17
14-18

14-9

DECchip 21071-BA Pin Assignments for DECchip 21071-AA
With Parity1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DECchip 21071-BA Signal Types ..................... .

14-19
14-20
xxi

14-10
14-11
15-1
17-1
17-2
17-3
17-4
17-5
17-7
A-1

A-2

A-3
A-4

A-3

·:<::::::::::::::::::::::··

xx ii

Purpose
This document is a support and refer~tj.¢.l::::d~:~iil~ti~tt:::.
..·.;:::::::::::::::::::;

...-.·:-.· .;.:.::::::}::..
·.·.· :-:·:· :::::::::::::;: ....... .

Audience

"'.-:·:-;.:-:-:·:-:-:;:·:-:-:

··=·::\\H~~~w====

-:-::~::\~{J~Ift·:·

For those who are designing 9.tiiPtPcess~t'':i&$.t~m~- using a DECchip 21064
Alpha AXP microprJ~~~'~or. =::::tt:::::\:I\::::i:.j}:\......
.,.'?\{>

Organization

... .-:-:·:·:··

..
..:::~:::~:}~:~=~:/t=\-:-.

··:·::::}/f{jf~~?:::>.:-:·..
··.·.··:::

·-:\lt(~\~~/\~~r-

This documen.M~·l=myided.'iri~::::tbr~~:::-Parl·~=::fuid one appendix.
•

Part I, co~-~h~::::~rt}qy~rvi·~,w::Sti!~i'::DECchip 21071-AA and DECchip
21072-AA and thK.=]:)IG¢hi.P 2107i~CcA.

•

Part II, con.W:n~tirif~iffii'tj~ijfr~out the DECchip 21071-DA.

•

Part IIkl¢~h·ii1ii~!l!lroqn;~lSh:''about the DECchip 21011-BA.

Appeni,:·~ c9ii:l~s:::~iicode equations.
The fql\p~{al:!:}i.~~i:i~:hmmif~~:s the contents of each chapter:
•
•

J;fl.i~l~r i{~¥.41.ai~:-.jj:[jbrlef overview of the DECchip 21071-AA chipset and
;:::f:j~f:~pbes the features of the three chips .

.,:/:fI:tf:\:,. ~ ···dfl.~i.:l.t~:-.describes the DECchip 21071-CA pin signals.

i \\!ii Fi('j'j~j\\Ch~~-ill~cribes the DECchip 21071-CA architecture.

·· !ii:.. Ji ~'I ;:::::: :·::::~: :: :::::=0:: :~~~~::::: ~:~~~:::::~:-~A
0

·<::: :.: .:_: : . ·:.:·:-·:.::·_:'!::: ii"·t··t==-

on the sysBus and memory interface.

>::y:.·:·::::·::.···:·:~::.:·'-:':::'".Chapter 6 describes the electrical requirements of the DECchip 21071-CA.
. ·::::::<W:i\\l1!:!j[[{Thapter 7 describes the behavior of the DECchip 21071-CA chip on power
-:u.p.
vii

•

Chapter 8 describes the DECchip 21071-DA pin signal~~:-:-. .·.

•

Chapter 9 describes the DECchip 21071-DA archit~i\µt~~Fl!]}::::::. .

..::::::::::::::::::::::::::::::-··

•

Chapter 10 describes the translation between t4.~. :l~tr ~dal~j;·:~:::tb..e PCI
address.
,::j::!l[![[i(:[:l[l[[[!j!j;\:,:.
"··:::::::::m:::::f("

•

Chapter 11 describes the transactioqdti.W f.or tl{~\2.iliii.¥.P.A from the
sysBus to the PCI.
.... _._._._... :t>>
···-.::::::::":.::<::":.::·_::_::_·.::_·.::_.::_:._:_:_.:"

•

Chapter 12 describes the electrical requir~rli~ijt~li:9,f&pe ri.ECfohip 21071-DA.

•

Chapter 13 describes the behavior of:::t.b.~\Q;ECchip\g!~rti~nA on power up .

•
•

Chapter 15 describes the DECdim·:·j:fo11-BA:::.fut¢cture.

.·.··.···.·.··:·:·

·.·.:::·:·:·:·

Chapter 14 describes the DECchipj::~·tbf.:j~l~:[:p~p__ si;ii1::·.

•

Chapter 16 describes the floW,:i·~1-~ai\l:::~tbin th~::::b:ECchip 21071-BA for
various transactions on th~t§nBus;:·m.~m9.:f.JY:JJ.~ta bus, and PCI bus.

•

Chapter 17 desctjp:~-~ the':'~li:~tW~1Lreq~~;~lijh'ts of the DECchip 21071-BA

•

Chapter 18 des'~rl.ij~·s:::#.h~ beha\).i~fHP:ff~l.l~ DECchip 21071-BA on power up .

.·.·.·.·.·.·.·.=:-:::.:·:·:·:-:-:-..

.·:·:·:·:·:·: :::·.·.·.·.·.

-::::\

....::::::-:-;.:..

Conventions us,jl:::::in. th:la:::::l!llde

Note
Caution

·:-:-: }))/ ):::.i~tid~s g;fMt~ information that could be useful.
_-_:::/?::/ .Jfo.[?f~v:i.:i~, information to prevent damage to equipment.

:3g ',l;l,lili~Jlf:::21::o:a:::::::: :,7;1~!::.ted.
.·.·.·=::;::;;:···

. :{i[I:JL@]))t

NumOOrs

"\(Jilkfiith.iflhan decimal are indicated with the name of the base
":-::::::::;::::¥6ii~wing the number in parentheses. For example: FF (hex)
Ranges are specified by a pair of numbers separated by a( ..) and
are inclusive. For example, a range of integers 0..4 includes the
integers 0, 1, 2, 3 and 4.
Extents are specified by a pair of numbers in angle brackets
separated by a (:), and are inclusive. For example, bits <7:3>
specify an extent of bits including bits 7, 6, 5, 4, and 3.

viii

.':._.:':·_.=~-·:~.-.·:··:·_:~_:_=~_ :~•

-:,Jtir=·::=:::'+>?J:t=::::::::::

.:-:.:·:·:.

.. .·__
·:. . . :. ._:.···::·
_. .!.:._.:=;.;_.:i· · · =.:...
_· -_:·-·==l!.• .=•._. -'.·.=..-:·:
_-= • .=•.__. •__: -=::.=._·:.;::1.!11111,i!!il;;
...
),

Convention

Meaning

.._·:·: .: :-~_·~:·-~_: :- ~_=: .~_·- ~.: '.: :·:~~:-'.: =- .

·\_j~_J:_::]l\>
• ;';

.}~)}:

..::::::~:~:t~~~}:~::::::·:·.

Clock edges

Signal edges

References to the asse~pjfaQ.4. deas~~\i~W;).fJ~Jgnals are defined
by using the (I\) and (vfch~?.r~ to iridi®.:fiJ~gp.al rising and
falling edges. For example/:tljj#@.#.!iJ.~ertion "'of\iji~mRAS_l is
referred to as memRAS_ll\. ··:=<?\tffi}::::::·. ·
·.·.·.·

sysBus

Refers to the DECchipJ~$.QfuLpin brtM(4.(~~t~ddress and controls)
and the control signtlj~=Ji).ij~~t:u:ind the\l)ECchip 21071-BA,

~~i~k~~071-CAf;,~tlii\'~~;~.,21011-DA

(or other
any

~=a~
~!l···~e!::.,e~i~~e!oJ,~e;~:
or falling
cyclt{lff#.h.i.hJ,he signal is defined as occurring

memClk cycle

egg~j~f

i~- cycle li~:::::::::::::,:::::::i::'):::;..

GCR

····:::::<:t,i::::i::::,:r=· .
./~f:,rs to gen~11:iego1 register

Bcache

·.·.:mw~0~:':r1tf:~ckuir:c~e~~t>:·..
'lb oo'''®tennined

TBD

·-:-:-:-:-::-:-::·

TBS

TBL

C~h'~~))~::\~~~~-

Byte
Word
Longword

· .· ::::::>contain~\i:64~fts.
·<r::::::=r= :::n:::--:¢.6.ahups ~~<6t~s.

Quadword .<'.:'.'. ::::>··
Octawo_,.._d \::Jy·:-:
·~.

: -:-:-: -: 'con4'.~
_ n:_:_'_,:_.'_,_.:_~:_.i:·: 128 bits.
. .~
<\\_:_l.\_·:_''.~.Il@t:cdtihs 256 bits.

::::::=:·:-::/=\\}~~~~~/·

HexaAfa>·
•.·.·.··.·.·.:·:-·

C~ntalrl~ 64 bits.
__ ,.,._:_'.:'_:_:_:_,_'_s_:_::'

··::::::\r~~rr~tt\~~}=

··:·::tg\~:~:=·\::·;:::\:··· .

·:::;:;::=: :-:::-:·:-:.;.;.·.·.·

DECchip 21071-AA andil2~I~~~~-tr:r~::
:=::::i:..' ·'.-: .::: ::::::::::::: .
-:-'.:::::::::::=::::

•..•::::::::::::::::::::::•.•·.·•

<: : : : : nm:-: .1:.:.1: ~·:.·.:.~.:.:.:.~.:.~.~.:.·.[·:.'.:'.[.~./.:[)

···-::;::::::-··· ·=·:::::::::::;:;:.:::::::::;:;:;.

1.1 DECchip 21011-AA and 21c~lZii~A:.;:'cn:,l@@t Features

i!AXP0d~!;:;
!~~~!!=~~~f!ll1=J~!~2~~:!tf:i~:~
~~U:~on
microprocessors. The
cache and memory
c}\jp~~§:;.includ~:s\'-::i:~m:.ondary

controller, PCI interf•~~' and:''&)fr~~PQ.P..ding dahfpath functions. They provide
ample flexibility to:::qj~}sy~,tem d~iiiniiJn. building the memory and 1/0
subsystem and require WJ).iljmf.!~ discfit~[[J~gje on the module. The DECchip
21071-AA and.~:t~l72-AA':&hlP.ii.t~A~.ontaitkthree unique gate arrays:
•
•
•

DECchip ~ir61\~SQ~::(Qach:/l~~~bt.controller) - 20s PQFP
DECchip 2107·~:~fiwii!(l§1A-0tetf~~~r208 PQFP
.-.·.·.·.·.·.·.·.·.··.·.·.·.·.·.·.
DECchip ~J97Jd~l~. <D'~ti,!jj~i~) - 208 PQFP

The followi.P:g...ji:~t{~-#i'~rj~s th~>major features of the DECchip 21071-AA and
the DECcq~p·~l~iO?:~t.f:lA ~~pset:
•

Suppo~::::tn~I~l.{tire t~mily of the DECchip 21064 family of Alpha AXP
m}R~~roiij~!~tlt:::::mi~:i:~:):::):)::::~::~:::·

• .-:·:·:·:·:·:·:·'.·:·:·:·:·:-:·:·:··
:::PP:IP:Chip 21.07-itAA'''chipset:
·>:;:::q4i::::\i[:i:S#.pports 128-bit cache/64-bit memory

~II~:: :~~~~~~~ :::s
-

One DECchip 21071-DA chip

DECchip 21072-AA chipset:
Supports 128-bit cache/128-bit memory
Four DECchip 21071-BA chips

Digital Confidential 1-1

•

One DECchip 21071-CA chip

One DECchip 21071-DA chip

System clock frequency up to 33 MHz

•
Write-back cache
Size from 128 KB to 16 MB
Bcache SRAMs, 15 ns and faster

32-bit parity/32-bit ECC on Bc·:·a: ·: :.:.~.:'.':hi:.!·l j:j.:.1·::::::::::::::::::::;:::::::::;::-:.
: :1.f:i.:.: m: : : : : :-.
:
'
o
.
'
·
.
·
:
.
·
.
:
~
.
:
·
·
:
.
:
·
.
:
.
:
.
:
·
·
.
:
:
e
·
.
·
d
:::;:::;:::::::ft\?\.,
.
8 MB to 4 GB Of memory Supp :J.'.:t;,
··.:-;.;-:-:-:·:·:·:·:·:-:·:;>'.·'.-:··
267 MB/s CPU

write ban.i!lli;~~i~t!':'1~:·(;1fj read bandwidth

32-bit parity/32-bit EG.QJ~ij?mem6fiti.@tf::JDECchip 21072-AA chipset
.,: ;: : : : :;: ;: : : : :·
.:.:<\:.·~.::.::.:\.:/://'
Only)
:::/'.{}~:}:/:}~::.
RAS/CAS

~l*:. ~UJ··i.~~cfurd SIMMs

DRAM c.qntrolleifff!Uhf'1lly proifi.wmable timing with 15 ns
granul. a. .·. ·.'.n.:.:.:.:.:~.~::
f.:.: .:~:
··.·.·.·:::=::::::,::::·.·.·.·........
····:::::;:;:,,.·
·'.·'.·'.·,'.:'.:'.:'.:::::::::::;::::::::·~·.
..•.

•

. ·.i'::.:. :..':.·."····..

Option~i\6ij~W,~:·}~:Upcat;~<rJf:::·gitir writes
High-performan~~<P,p~:il~mqge ··· ···

=~~~fl1E:~•data
Noil'li~. l.·~/~eettl to connect PCI-compliant chips

-}!!i!ii:l~J)'\~l~.~]:pMA:~:·~width, 70 MB/s DMA read bandwidth, 82 MB/s

/J,£iillt~~p!fSlWrite bandwidth, 22 MB/s programmed 1/0 read
. . : :': : : : : :'.:'.\: : : : : :· <:::::Ziilti@~r/gather map support

. :t:::n::iui::::::::t::::::::::::::·~:~t1~:·:·t\Gr~~hi~~·::·~iP:Port
.. ::::::;:::::::::::;:::
·:.:-:·:.:-:-:·:·:·:·:·

::+::::;:1::;:1::;;:[1:::::·:n:>,:::: ...

/:\<::::J~- High b~dwidth memory data path to video RAM (VRAM)
Provides support for direct connection to VRAM frame buffer

1-2 Digital Confidential

Figure 1-1 DECchlp 21071-AA and DECchlp 21072-AA System

sylOata cl 27:114>
84

sysData c83:0>

DECchip
21064

82
cache

DRAM
SIMMs

memMr cl 1 :0>

NOTE:
-

- -

Remove !or 64-Bit Memory
Connect tor 64-8~ Memory

LJ·03081-TIO

.-/~}}} ::::;:::=;:{{{
.:{~~}\{}~~~/ :\'.{{:}} ;.;.·.·
·.·.·.:-:;:···

1.2 System qy@tvi@Wy· r;:!.l.~iii

Figur~:=::k-lhi.ji,\\.i='.·~==··blo~~~i[liagram of a system built using the DECchip

210711:4$~ DEQ#,).i1)if:~:t.pf.t;1AA chipsets.

Th~:::j~m is l>:iit:::;figiii'; the following components:
.,,,,..,;.. ==·•=: .·:::::=::bQlh!lt.~1064 microprocessor
.:=:=: : ;: : ;: .: : : ;: : ; ;: _: : ·.:·: : : ,:~=·: , :pEd'~Etl=l!~!,971-BA
·::;:;:::::: [bECchip .2'fo71-CA
...:: :\~:~ :~: ~: ~ :~: ~ :~: ~:>::~: : : : ·.·. .:: :}'~ :~'<:~{:~v: :." DECchip 21071-DA

•:::: ::<<<=>:r:c::;

..: :::<i:i;!!~~!:; :ii!tW:lii)i:~i; ~;: ::._._

Bcache data and tag RAMs

.,,:::-::=~-:- >B~ache control PALs

•'' \Cache address buffer

Digital Confidential 1-3

•

System clock generator

•

Serial ROM interface

•

Interrupt contro1/CPU configuration PALs

•

Memory SIMMs

•

PCI interrupt controller

•

PCI peripherals

•
•

PCI arbiter
System ROM

. ·.·:::::::::~/}\:.
1.2.1 DECchip 21064 Microproce~qr:::lli·ll=::::::::-.
1

·.::::::-:-:;:;::::;:;:·:

...

·:::~:)>~~~=~t~\r·

.;.;.: : ·: : ·

~~~~~:
~ 1r:h~~d·=e~!=~~lltJ:~=:'s~~ !: !:c:~P
cycle times which rirurt.:·betwe.~ti\\3,~\?:\\[qfJmd 10 "tis.
The DECchip 2106~:''ffii~mi~9~~ss~;::\~~~ln:~::-two on-chip 8 KB direct-mapped
caches-one for/µ~~ as ah\(~~h~t:.the otlieF:as a Dcache. For details about
the DECchip 21.(')§~fa>.rQcessor~lt~f~~fotR.the DECchip 21064-AA Microprocessor

Hardware ReferefiFe.:?Jf/li!NN!'l. ........................

1.2.2 Bcache Data and -f:§-:::S~M~t
The DECchip{gJ.i!pz,$.f.~::•chi~'~ijtj:.$.tlpports an optional write back secondary

cache (Bcac.fit)}>THi.::::~ygtew wiifsee a performance improvement if it is
included. }.1)ij~(siz~t@ilh«t:l¢._ache can range from 128 KB to 16 MB and the

;::~~-1£!~~1~.!n~:!:~:~:08!8 ;;~~:: i:!:its.
~~ez:~~'·'~O~ee:is:::O~~~:~·

module routing delays

...:-::-:-:-:/:=::>:::::::.'fh~\\j\blJi~[it~§triction that the DECchip 21071-AA and DECchip 21072-AA
.:t[]:::::rn::Jji]\:\~\!!i!!:pJ,ces·-:Mi:::m~:::~p~_ed of the Bcache is that a read from the cache RAMs must be
. . . . . .·-:.:::::·:.-···-:::::::=u::1mpleted'·nr::9p,~h:;ystem clock cycle .
:-::·:··:}:"'

.:::::::::::..

:::::;:::::
'·'<;>:· ..

1-4 Digital Confidential

-:-:.:·

:;::::::::;::;....

:1l l! ; ; ;~'.i1~ ~,l\!il i!i:IJ\W
·.:-:·:·:-:··

1.2.3

::::::;:::::;:;:·

.·:·:-:·:·:·:

e:;::s~=:e~~~7~-CA (cache/memory controlledi.lmPa~•IJJl\!i
::::::::\:~I=·

.-:/?I~~tr

Bcache need to implement two control PALs which supplf.·tlitfi},~grn@P.4...data
RAMs with output enables, write enables, and low~t\~®,ress bit'sftHl~Il~>
The control PALs are used to implement JID.:~:tfollo~ih=i=!t#.D,);~j,9ns: ·==\J?
•

The NOR function between the proc~~i6~-,g~~r.at~d<Eiilji·!'i~~mtrol signals
and the system cache control signals.
.·.·. : : .:;·=·: : : : : =· : ;==: : =:;:
· .· ·· ·.·.·..·.·.·

•

To generate timing of system cache control sigrtaiiQ§~:::t.hat the cache' access
loop by the 21071-CA can be bettei:,=:~9n~f9U9::9.:· · =:::::t//=:::::::::::=:

•

To generate some of the control sigg@is·=·-r&f.Ht}l@::prw~essor data bus .

.:-:::::·:·:;'.<·'.·

-.·.··.·.··'.·'.-'.·'.·'.·'.-'.·:-:.:;:·:-:····

1.2.4 Cache Address Buffer

...':'.:~:}}

.·::~t\r==

.::::::;::.::'.-'.-:-:-:::::;:;:;:::t::;:::;.
::::::::;:;:;:;:;:;:;:;:;:;::'.::::::::::::::::::::::::;:::..

... ::::;;;:\i:i:;:)\}'.:::-:·
····:=:=:::=::::::::::::==-·

·-:-:-:-:-

The cache address buffer is req~fitfto=:a~~tnbµt.~ the cache address to all the
data and tag cache RAMs.
· ·:·=-=·:·: ·:·:·:==·:
··==:\{j]{)l'\.

!1jjj~[l'll·1·~;f!ili•\> <;t
0
;:~
~~~~~::~,~!~;llE
.
;~~'t:o!:n~
~!~o~~~:=:~ath
functions:
. :.:=:=::_=ii:i/\ . .
===t:@:]:y-- .·. ..

1.2.5 DECchip 2107Hlllii' ·'·

Error Correcti~~~l¢tiQn L~i{ij~==Hrhe DECchip 21071-BA supports
longword (32 bits) paritji::iP,:]:l~b:P:~t and 128-bit memory mode. ECC mode may
be used with ~$~bt1t~de·"'=mEffi.iqcy:=- by using some of the unused higher order
CPU data bj,:t.~::·:~$Vi~lj;~j.~i::bits. Ei¥Br checking/generation is done only on DMAinitiated tr:ih$ictiQ#~I?~rt;Qf= checking/generation on CPU-initiated transactions
is perform~ij;:ii~Y
t.Jt!iiiCPQ~:j]::,
.
·.·.·.·.·.·.·-:::::··· .....·.·.·.·.-.:.·
·.·.:·:·:-:-:;:·:·

~:n;afi~,~1)Jti:=:: ;V::;e1::f::!::Ss~°:ro~~~i:~ ~~;:~z
chjp~:=:{t\Vo or fout=''Miip~Y in the system. Data stored in this buffer has been

....·.·...

thfoqgff:~ml the cache coherency checks and is written to memory in the order

.·: : : : : :·j:[t:1.: _: ·.:~'.:·:_:!.1.'.:i'_:f_: _W_:i·.~.: _f_: -_: :_=~.=.· .a~Fitte_;'._=:=_:~_.·~'._=.·_.i:_~_=: _.: .:.t.: -.=.:=_.?.=.·.·~- the sysBus.
...:::::?i::::::·::::
.:/tt:=:r·· ····=·====:::tMiJnory Reij,q\Jluffer: The memory read buffer is a one-cache-line (32 bytes)

<\;;j\li

.lt~~t::1!:g!'!:::J~o~ ::~~u:~!t~;trr!.':is~PU on memory

=-=· -=-=·:::::;:)::::::::::.· >>= J)::·\il:!ifJo Write Buffer: The 1/0 write buffer has two entries - one entry acts as a
'<:(fiJitfwrite buffer for CPU 1/0 writes to the DECchip 21071-BA or PCI bus, the other
··-==tt\()'~~t,~}lS a holding buffer.

Digital Confidential 1-5

1.2.6 DECchip 21071-CA

r!:c~o~~~1;te2~:iio~?n~ ~?:i cfe~'!:'Jl~1·~~~,fr~i?e ~~~~ip

21011-CA:
.·•-:=: : :<'.i[: : : :t
··:·::::::::::t:::ti::tt>·
• Provides control· for filling th.~:::[Q¢i¢.b~(AP..d extr~ai'itg victims on CPU:/ff'' ·•"'•'•.'•·-::::::~:\}~{/:~:~::::::::·.
'•: : : : ·. . . .
l.n10t1·ated transact1'ons.
...

··:·:::::·:·:·:::::::::··.·.· ·.·.·

•
•
•
•
•

~::~:~:~fC~'i::~:::::c::::1::
control of tH,~::::~¥.sBus~<t::::Irn::):j::[\\:::. .

for

·::::<r·:::::·

Stores addi~~iijifff9.Jtthe f~:hff~i.i.n~Jine deep memory write buffer.

Controls the lo·:ai~~ji.~~::tv&
110'''~¥.ff~ buffer and the DMA read buffer.
. ................. .

Uses fast P.~~t:m2(ie··:~H:il~~:·l~P.R.A.Ms to get improved performance on DMA
burst rei.ld.$:::~:aNni.Piory Writ~s.

• Suppo~i.i!i/du~~:ilt;am~\buffer on the memory data bus.
·:-:.:·····:·:·:····
:.: ......·.·

.·

1.2.7

.·.·.·.-.:-:<·'.·

. ...

\{ill=l:i:::::JlEl::.ii:i:::.·:·

.·.
.·.·.·.·.

......:::ir·=.:......

DEG,F.q~p/21 d71\!l,li::\j):l:lj:}::r··

TQ~\)\:QJi:Q~hip 2107i~t>A chip functions as the bridge between the PCI and the

·· illll!iCDllK~h:U:c~~=:~u~~!~:i:C=!~!:~ !1}~~~:i:::~:~rs

.•·•·•<••···::•::•:•······..·"'·'•\{:)M.lc:J: the p8:nt){jff.~e, all the data path functions required to support the PCI
.....,.,.....
"'t~~ide in the DECchip 21071-BA chip .
.::./(//((

,./·.·JB~· following list describes the major features of the DECchip 21071-DA:
::~~~~~~~~~j~;i~~j~~~:~~li~~~j~~j~
·-·:::::~~~~;~;~~~~~~~~~~:~:~~~~~~)~~~~~~~:}~;~
:::::::::~ Scatter:·'gather
mapp1·ng .crom
the 32- b1't PCI address to the 34- b1't phys1·cal
· ::::::::;::•::;:::::::::::::::::::::/.
I
li
··'=·:·:.]:/·.%·:'/:• . , address, with on-chip 8-entry translation lookaside buffer (TBL) for fast
·· '\H.?":_'-i'°)\::@ddress translations. To reduce cost, the scatter/gather tables are stored
···:::::··.-:Jh memory, and are automatically read by the DECchip 21071-DA (PCI
bridge) when a translation misses in the TLB.
1-6 Digital Confidential

~~.·~:.:

:.::.: : .·: :l: .:: .: :=!::::. ::1:;\.=::::::::i::::::::::::::::.:.·:.·.
.
··::;::::;:::::;:;:::::::·

:f@{/

{{/}~~--

.::.:::t::.::.:>:::;t@f:\:::-

tt/l/ :i]:]r

:;:;:;:;:;:::;:;:;:;:;:;:;:;:;.;·

·1111:=t·
• Supports a maximum PCI burst length of 16 longwor4.~t.Q.n ~bl IJ.fu9ey;·\·!:··!·:\\\
reads and writes.

•

./ft::t::::::\:·

"·:::\/\::\(:;:;;:;::···

+.~ll~f~ll.111~~~~~~:~::;· to

Supports two types of addressing regions on CPU
PCI space.
./\\itm:;l\1\\::t

...\\}:~:::~:;::::;:;:::;:

Sparse space for accesses with brlit~:nd ~cif.a::\li#.w.~rities, ~hd a
maximum burst length of 2.
.,:=: : :; ,;.:=.,: :?"
...=::::::fl'f:}:\::::,.
/'.()(}::;.;-

·::::::;::.:.;.:.:.:.:.:::::.::.

Dense space for burst lengths from 1 l~ii)$.i=:@#:~s ari(lqi(:,J).ti~st length of
2 on reads. This region can be used for Ili!lij)ijl1:Uf.:e structures such as
frame buffers, which require hig}'r;Q.4.n4.:widtff;~~~i~~~·

~:O~:s ~~e~:r~~:!i:!oal;~~,Jl~&:::;,'&i~trols the loading
. ::·:::}:~~~~\:;:~:;:.

·.·.·:::~:;:;~;~(···:::::;::::::::·

Stores address informatiorltfoiffthi:d/O writEr'bhfrer and controls the
unloading of the 110 writijilib.filt~i:::ina::JlMA read buffer.

Peripheral chips can pe conn¢.-·'!iw.. the .ij'geli~==·21011-DA chip without any
glue logic, howeverd~Qmc extetH~\\\ilii:\b:~. DECchip 21071-DA is required for
interrupt arbitratfon#1ht~tn.ipt veetqjffgin~ration, DMA request generation,
and interval tim.:~r impiemi#.t3.t:i?n. '"'.:::::::w:::::trnrr·
:-:-:-:-·-··:·
::::;:·:::::::::::::::::::

21o7!f

··:-:-:-:-:::::::::::::::::::;:::::::;._

··::::::::·

"<'\{})\:'.....................................
Im·H:@::Note - - - - - - - - - - - -

The DEC chip
PA::i~ not=,~:\ec1 peripheral; it is a bridge between
the PCI peripherals==::~(tit.b.~=:,.CPU/system memory. The DECchip
21071-DAAmP:l~m~mts.llWi\=:~Hions of a host bridge which are not
sufficieQ#}#~drltmi:~~ the DECchip 21071-DA as a PCI peripheral
compon::···,·.':~n~~·
)){{' .. ·:. .
:::::::::\:?· .:-:-:-:·:·:-:-:-:
·-:-:-···

. . ~lilt>............ if~: s:;;:i:s~::~!~~:~!~r.;;::i::!h:1~1 ;~:~~~og!~~~=sg~~~:ated
:::;:::,: /:§t::::W::>Hocks from the sysClkOutl_h signal, which is supplied by the DECchip 21064

···:: \::t:t :mi~roprocessor.

Digital Confidential 1-7

1.2.9 Serial ROM

.::::::::::::;:;:::::::;:::::..

The DECchip 21064 microprocessor provides an interf~~:mtp::\:irn~m.~l
which can be used to initialize the instruction cache (JeaMiel?tl&etiietails for

!1;;c:;!::~J::~~ai:~!{:~~~! :i':J,ound lll;~ECchiPi~.,AA
.·.·.····.·

·-:-:·:·:·:·:<·:·:·:·:·:·:·:·:-:-:·'.·.

;:::::~:~:~=>~=~::-:

1.2.10 Interrupt Control/CPU ConfiguradO'rf~~b.;.

·-·:·::~;~;:;::r:=:;:::=··=:=::::\:::::..

"":"·:::::::::::::::::::::::::?:

The interrupt control/CPU configuration PAI>l>i»ti~~'-:':-~ystertF~dhfiguration
information to the processor and six hardware int'iijfqpf$.:;:::-The PAL outputs
connect to signals irq_h<5:0> from the ·.·.·.·.···.·.·.·.··:·:·:······.:::::::::::·
PIQ~b~P 2106:4{m!~f:9processor.
·-:.:·'.·'.·'.;'.;'.:'.::::

When reset_l is asserted, the PAL prd.W.4MP$Y~ti.mr::::~lock.dmfiguration
information, and data bus width infQr.~tion t(ftf.J.i!rnP.f:P.~essor on irq_h<5:0>.
When reset_l is deasserted, the ed'-llll::t~txeflec~·::'iliii/~alue of the system
hardware interrupts (intHw<O;J>%).#b'iHM:P.rP:~~'-~~-~ on irq_h<5:0>.
··:::·

1.2.11 Memory SIMMS ::/}:\:

:::::::::

;:;:......;:;:;: ;: : ;:;: ;:;:;: : ;:

·.:·:·:::·:·:-:-:-:-:-:-:.:-:··

··:·:;:;:;::;::::::;:;:;:;:.:-:-:.·

.......... .

The DECchip 2107l'fQA'· (~~hef~~l,i.fy\[J~~uitroller) can directly control up to 16
banks of DRAM. memo~t);)~¢.~l_banlt':m~)d~~:· composed of .either DRAM parts
or SIMMs.
.:-= .::.....
. \:\{_::_::_::_::_:::_::._:_:.:'_:" ••
"":::)::;.·:::::: ::::::::;::::::::::.
Each DRAM ~~:~P)l~t~:4_MB,:4/:Nj~·:·jq~::J6 MB addressable locations (1Mbx1,
1 Mb x 4, 4 Mb x i,::::4::·~:=,~::,~, 16 Nfrf~?l DRAM sizes supported). Each location
consists of either a quadiV:9r9}Pr. octaword of data, for 64-bit and 128-bit data

::i~ei;i~IJJBJll;~~IJAM me~ory

6 GB

and minimum

DRAM

The DECcf.djf:~lO.f'i~A pW,yides support for a single video bankset of dual-port
RAM <VRA.Ml:hTm~fbanl~tmhy have 128 K, 256 K, or 512 K locations. Each
locati9Q;:::~orii~Mf9.f.:~itb.:~r:]~fquadword or octaword of data, for 64 bit or 128 bit
dat~ ~4.lffi, reiP.~myj.Jy~:}Maximum VRAM memory is 16 MB and minimum

'111·11:~mory fiF1TM1f

.lm~~~j~i]:::e:~f'lrill!~:R~. Controller

<lF\\:f~:<:\:f::J~:::~xterrlaf]g~rrupt controller is required to handle the interrupts posted by

· .......... ·

·\mf:::J>CI (and:::~ipansion bus) peripherals.

": ":':': :';': :\lj\j!;l)~· 1~):.i!!.:I Peripherals

1-8 Digital Confidential

Digital Confidential 1-9

·.·.·.·.·.·.·.·
<·>:·:·· ·:-:······..

Part I contains information about the

DECchip 21071-0lli'iji,[l 'fl!l1r!Ptions
··.:\:~~~~[~~~:~~~\~~~~~~~\~j~~~\:

<·:=\~~ij~frnY··

·.·.·.·.· ... ·-:-:;>"··.·.·.····

This chapter describes the DECchip 21.Q.~lfQ~fopW.. sig!Hd.~~.-:rn:>
.:-::i;\\:\??/:{/{/?}~::::.:<<·>.

··:·:·:·:-:·:-:·:·:·: -:·:·:·:-:-:·.

Function
··.;.;.:-:-·-:-·-:-:;:;::::::::::::

CPU/Bcache Sign'''-:m=·H>::: .

(85 Total)

·..·.·.·.· .·····

·.·-::::::}\~/:

-:-:-:-:-:-.

·:-::::::::=:-.:::::::::::.:::::::··
··.:.:.:-:-:·:·:-:.:-·

. ····· ·······.

sysData<15:0>

H>tl?/ ===:=:,

1/0 ·

J::t::t:L.

sysAdr<33:5> .·.·==: : = =-=-=-·=-=-=-= '.·.·,:_=_:,·._·._.,•2.=.9s·.==·
tagAdr<31:17?'.//? ::::=:::::::: 1
=<tf:lfJo
·=-=-=== =-==-·
:.:::~.-=:_v·
···=-110
tagAdrP
tagCtlV
}lf =============
1/0
tagCtlD
:/::=::::)\ ...tl\f? 1 .,: ·.· :--:-:
1/0
tagCtlJ.h======·· :::::;::,,,}::::::,/tL.. ~.,=:=:::\:::.:~~:>
110

4ma
4ma
4ma
4ma
4ma

~:;@31~~-~~~·==:::::=u:m:m:nj·!i!l!ll:!:l·:-~j:ilfJ>'·

cpqp~!;~2:0>

4ma
4ma

1
1

o
I

t :)·{

:tt··:;:·i-;;:j::::_i::::::::,;3:4~0~:~~:

_,:=}~=::t=-t>==·: ···=:=:=::lWiMPlnvReq .....

y_::::1:::![ii:pr

4ma

,,:~i#JioldReq
=Ji,uHoldAck

4ma
4ma
4ma

Data pins for CSR data
Address bus
Bcache tag
Bcache tag parity
Bcache valid bit
Bcache dirty bit
Bcache control parity bit
Cycle request
Command acknowledge
Data read acknowledge
Cycle write mask
Data word select
Dcache invalidate
request
Hold request
Hold acknowledge
(continued on next page)

Digital Confidential 2-1

....

···:::::::::::::::::::::::::::-:·

.:·:·:.:-:·:·· ..

Table 2-1 (Cont.) DECchlp 21071-CA Pin List
Number

Buffer

In/Out

··:::;:;:::;::::::::::::::::::::::::::::

Bcache·PAL

·-::::::::;::~:~:~:~:~:~:~~~:~:~::::··

Signals (9 Total)

,J·t:::f::::1n~

sysDOE

sysEarlyOEEn
sysTagOEEn
sysDataOEEn

1
1
1

0
0
0

. . ,/.:·:::'~:}~~a

sysDataWEEn

.:::i::::1:::? :'i:im~if}}>

... .........

sysTagWE
sysDataALEn

1
1

·0nab.let'\,:,,.

,,4 fu~.: =·.:.1J:
E~iy:::@t.tj:~t enable
4 ma·' </::r::::::: />Bcache. 'h1g output enable

::::::

sysDataLongWE

,.,,:\}l?..i!tA~ru data output

0:::<

·=:::::::::J.[lJillfee data output

··::\}} -:-:-=·: :-:.:.:.:.:-.:..

j:j'Ji~he data short-write
WE enable

8 ma ':':''<<it!t/'Bcache data long-write
:·:·: ::::·:::: ·· \\.
··.·.·· ···.· write enable
'::()::::}:: <H:!i!ij: ·===g::·:.
Bcache tag write enable
j(f
.··::::)::j:3[jl~t\:::::.
Bcache address bit

s~(
:\})\\

'.i:!llc

sysDataAHEn

··::::::::::::::::::: ·:·:

1
=:
:;.:.,~it
enable high phase

'·'.·'.<·'.'.'.·'.·'.·'.·'."·"

PCI Bridge lntert~~~\\,, .
Signals (9 total),,,,, ...... · ·

''\$.}\

ioRequest<l:O>
..::::: ··.·.·

ioGrant

:::·:·:::: li!·1l!!!11l!l

ioCmd<2:0> .,,. :'.:'::}:/:'
.:::;::;:;:):}·

I . .,::-, ..
'.U.:.::::::::11::11::::1@::0.

\j/.

·:··.. ~:\?'

I
.:::::;:::::::::::

ioCAck<l:o:@:tH\·.
;:::::{Ff:'
2 :''\/{
·.·.:·::::::::·:·.·
·.·.··:·:··
ioDataitJ:::' ·:::tI[[\[i::i.\!\[i.il. t:\rntr~::\i:;li.ii.it·
-:·:·:-::::=:::::::·:··

2-2 Digital Confidential

8ma

21071-DA sysBus cycle
request
21071-DA sysBus cycle
grant
21071-DA command
request
21071-DA command
acknowledge
21071-DA DMA read
data ready
(continued on next page)

Table 2-1 (Cont.) DECchlp 21071-CA Pin List
Number

In/Out

12
9

0
0

Buffer

Memory Signals
(39 total)

memAdr<ll:O>
memRAS_l<8:0>

:::::l\:::.J·.:s.
.;)'mm'<i::,'.:._·._,·.·=.·:.·.

8 -:-:-:·:-·:<-::::;::
,;+

··:.:::::::::::::::·~~b.ozy address

M~ffiif:Y}mw
·bi·········· address
stro ··· /=t=t=··
.. :; : : : :. ?%J\'1emocy: second subset

·:::::::;: :=::::::': -,:::;::::::::.··

memRASB_l<8:0>

8 ma

memCAS_l<3:0>

~::=m.~:.

memWE_l<l:O>
memPDClk

2
1

memPDLoad_l

··::::::::::::t>::RAS

''\::q~~iftbry column address

-: :·: ;: : : :;:;: : : : : : .: ·:· .
strobe
<\\.. 8 ma{}·.··,.,::;::::;:,.,:... Memory write enable

0:::::/ .. ~/.. .4.. ma ·:::::::::t:i:\\,,:!\i{r'Mclocemkory presence detect

/(( {\\ -:-:-:-:·:·:

U():{?' :.:''<?t?\ihna
::::::::;::

:-:·:·:·:-:;:·:-::-:-:·:·

, memPDDln

·-=·:=\) '???:,:,..

{1\t\\fQ\,,,.

,. .1

... .,-=·:·::,:,:,:,:.:·:-:.·.·.·.·.·
·.·.·.·.

.......·.·.·.·.·.·.·.·'.-.·.·......

4·:=Afil/'..
·::::::'

Memory presence detect
load enable
Memory presence detect
data in

·.·.· ·:·:-:-:-:-·-·.;.·.

Video Support .:::
Signals (4 total)}:::'::::,:.::..

vFrame_l
vRefresh_l

: :t:::.::·].::·l: :·:. ::-: :·.

.··::}{::::::::/ :;:,, .

1 ::::.:.::.::·::,If:::::: :·. I
. .::::::~:~~~~~)~j~:~:~~~~~~~j~~~~:~:~ ::::.·.

··::+u:=o

8 ma

Sma

Video request for full
serial register load
Video request for split
serial register load
Dual function data and
output enable for VRAM
bank
Special function output
for VRAM bank
(continued on next page)

Digital Confidential 2-3

.. :::::::::::::::

;:::::;::·:-:-·.·

..·:·:-:;:::::::

·.·.· ...... ::::;:;:::::·:··

{)) ...

Table 2-1 (Cont.) DECchlp 21071-CA Pin List
Number

Buffer

In/Out

Data Path
Signals (16 total)

-.;.:-:·:;:·····

sysCmd<2:0>

subCmdA<l:O>

subCmdB<l:O>

subCmdCommon

··-=:':''\1¢9.m~nds for sysBus
"814!Jffi:~:~Q71-BA chip
4 hi.a.'.·.·'.'.'.,;.' ./.,:'././ ::::::::
,,, · ··.
Sub'''oonimands
for
-· .. · ..
·'":':::;::::::,:,:, /:\\,,~ysBu~ :;:::::···-·.··fhpia ··:,::':'::t·t·:\ff$.t~mmands for

-'' lii.f:::ma
:/:/\:-

· ·.· ).i:'.)\.\.:i. iu_'.:.:.,:.'a,':··.:.\l:: ....:;::.
?)\t·

sysIORead

drvSysData

drvSysCSR

drvMemData
memCmd<3:1>

···:::::::::::;::::::::::::::.

sysReadOW

Sub-commands for

.,,,;:::::::::: \\.,:,:;.,.,.,. sysBus

0::: .·.·.·. \?'?.

8 ma {{/'}{/Selects I/O read buffer to
::-:·:-=·:-::>:::' .""' \(\.
.,,.,.,,.,.,.,,.. sysBus
i\:(Ut>
!i\!Ia::m~
Turns on the 21071-BA
.... ,. '\/'
.· . ::::;:::::::::::,./::::\
sysData<l27:16> drivers
<i\{llo\
~ftiiJY'
Tums off the 21071-BA
··.''\\,,,,)/:'. ,:,;, , , ,.
.. ,: : :,
sysData<15:0> drivers
···tw::\\[lj\i:\il/ . . · 8 ma
Tums on the 21071-BA
·>:·::,:· '''''''.\'.:::.:-memData drivers
·''\(}8 ma
Commands for memory
side of the 21071-BA
chip
Selects octaword to be
8ma
returned on sysBus

Mlscellaneousic16ilt~fj{(\ ··

Signals (8 T::~!!tf

· ., , , , , , ,: : , .,:,: : :

wideMem

I
I
I

···.·.·.·.·-:::;:;:-:-:-·.·.·

"•·. · · lifI;==~lll1!Jiilih .
. .; '.; lti\illl:i:~fMM@ . .

.·.·:.·.·.·:.·.·:.·.·.·:.·::.

·--::;::;:::::::::::::::::::::: .....

2-4 Digital Confidential

1.
1
1
1

I
I
I
I

4ma

If true, indicates 128-bit
wide memory
Clock input
Phase reference for
clklx2
Reset
'Thst mode select
Scan enables
Tristates all outputs
/bidirects of chip
Parametric NAND tree
output·

(continued on next page)

··.·.·.·-.·.

·:::::}}f~{)~}:}~{:}~{

Table 2-1 (Cont.) DECchlp 21071-CA Pin List
Number
Total signal pins:

170

Total input pins:

Total output pins:

115

Total power and
ground pins:

Total pins:

205

In/Out

·:···:·:-::::::::;:;:::;::::::::::::::::

Buffer
·-:-:-:

·.·.·

·-;.:-:·.:·::::::::::;::::::

·>>:·:-:::.:::·

·.·.·.· :-:-:-:-:-:-:····
·-:::::-:;::;::;:::::;:: :;:::::;.

. ·.·.· :::::::::::=:::.. :·:::::::::::::.·
-'.::::::::::::::)~(~;;:-:···
.-:;::~:~i:~:~:~:~:~::::::::::::::::

2.2 DECchip 21071-CA Sign"':"::·:.p.e'l~i[ilUons:::;::::
This section provides pin sigq~}:::jj{ormati6ii~:~l"ltJ*1ding a description of the

~~n:1~ :~:!:~;!11?~~!!!i11;~!'."1gllii)!ind rules about signal usage
For simplicity, .~~?, si:atl:lll:IP~ti:fi::=:-~J,.:=be treated as clklR.
.:'.::..-.

·-:-:;:;:;:-:-:-:-:

.:::::::\:::..

·-::::::}}/~

·-:-:-:-:-:-.-.
. ........ .

.;;.:·:·===<<:/\Note - - - - - - - - - - -

··"<::::::::::::::::::·:::·::>:·:·:·.
0

The DECchip '~:f:blll~~9!:9.J>ro~'~:~j~~f does not use clklR, rather, it uses
sysClkOut_h to gener~~~:·:@n~tsample signals .
::

..:::::: ::: :::::~::........
-:;:::;:·:·:·:··

2.2.1 CPU/Bcacfli~!iflii~ <ili;

2211

. . .

.. ·.·......

sys

o8 ta 1s·mr ·········

/:~)~\?

JH?t,:.· :;:,~: :-_;·:i~.i!i\: l:i\:!·!: :;: .: :.:.:.:.:.:.: :t: ~: :rnt'

,§.igpru ~}QAY.feetional - (21071-BA, CPU, Bcache, 21071-CA)
. ,/):jjljjppt SamplfojfClock Edge: clk2F
··-:::::::Q§l:!~::::~lock Edge: clklR

·:•:- ::::i:rni:liij;ij!i[jj)i·i=:JY.~;oatft@ili~~?i.~ta bidirectional }>us which provides data to and from the
···:::::\21\071-CA chiP.a#id
the CPU. The default driver of sysData<15:0> is the CPU.
·-:·:··
'.;'.:'.;'.;'.;'.:'.;'.:'.:::'.·.

.Jit$.Data<15:0> is used to read and write the CSR data for the 21071-CA chip.
;..;.<:.:.;;;:.:.; =>=:::::,,. .,:/}The 21071-CA chip does not support error checking on its CSR transactions,
,,,,,::;.:.;.·. :;.:_-:i..-::.;:}s'o corresponding sysCheck signals do not go to the 21071-CA On a CSR read
;..,, .·.:u:.JU\tr~nsaction, the 21071-CA chip drives sysData<15:0>. The rest of the bits are
.'<'''t::.rn·~y~p by the 21071-BA data chips.

Digital Confidential 2-5

2.2.1.2

sysAdr<33:5> is driven by the CPU on CPU-irltti~~~q:4;ran~-;~ti~ri~, and by the
21071-DA chip on DMA transactions.
·-:-:::::?tt:?:L:. :;. -:-: .
.
.··.··:::

·.-:···:·

•

On CPU-initiated transactions, th~<~~~t~!$$d~ hei'd::::6~:):.the bus from the

~:=:
t7::a:::t
~
:~;:Jr!:,lfa~::::;:::·
internally
so that the cache can be
the c:Ptf
releas&Uba~ltto
:i%~i[i~~/Y·:.

:-:::::::::::::/\{·:-· ·.·. ·.·.·

...

. ..

::::::::-::::;::;:::·

··:·::::~:~:}~~~}~~}~~\}:·.·:.:::·::::;:;::-:·:-:

2.2.1.3

sysTag<31:17> c;ff.iijj\l:\aij4.c.he t;~::iijrri.f.fuation. The only addresses that are
cached are those witft'Bii;~:::g:M:;$2> ~::bo. Bits <33:32> of the tag are assumed
to be 00.
· · .···. ·.·
The tagAdr.sa~-~~;;..::~~ij~::of th'~<tJ~Cchip 21064 microprocessor should be tied
to 00, and ::Q@JY bit.(.(li$3i:Ji? are variable. The number of significant bits of
the tag dep~qq_s .P:~fitlie diP:th of the Bcache RAMs, and the maximum memory

::1':1l~a.1t. the tag address is driven onto
t9;:·~~~lli:~_-CA chip::lHcf\vritten into the tag data store.

sysTag<31:17> by

::::t:?t.>::J~YsTi~~{lti;:i7:> is read by the processor during a cache probe. The processor
.. ::. J{:liI:l:J\ii.P:~s noPd,f:i.jj~::tb.~se signals at any time.
::?:)\}?:·
"'.:\:'"li::Bcach;:::fH~-:~~o~e drives sysTag<31:17> with the assertion of sysEarlyOEEn,

0
<ii~·:::>?Y??!!!'
~ c::}> :?JU\store
.. lt~.da:
~;~~~~g~r:~a:o~~U
;~~~~:a~=~
~~
:da~i!:~ag
drives sysTag<31:17> when the 21071-CA chip asserts sysTagOEEn.
:.:::;:::::::;:::;:::::::::;:::::::;:::::.

::::::::~:.rn:\:!.!.:::\\i!\"'Jg:nµsed sysTag bits should be pulled down on the module.

2-6 Digital Confidential

2.2.1.4 sysTagPar

.. ·::(\~~))}:::::.

Signal Type: Bidirectional (21071-CA, CPU, Bcac.b~lif\::1:::::l:::\:li:tt::::.
Input Sampling Clock Edge: clklF
: : : ": : : : : " ·· . ;.;.:::tt:ttt\:"
: :·'·:.·.::..·.·.·.:.'.·.:.: ·:.: .\.:':.'·.'.: :/
"""";··:·:::::::::::;:·:·>:·:·:·:·:·:·:··
.;.;.;.:·:·:·:·: : : :;:;:;:;.
.
:
.
Output Clock Edge: ClklF
. ··:·:·'.·'.·:.::;.:-:-:·:·:·:···
·::::::~{==:~{:}=

sysTagPar is an even parity bit over the . $~gpjfica~t:::fiil\l::Af)~y~Tag<33:~i 7>. The
number of bits that participate in the paHt:Y:"c9pmutat16iiW1~P.~nd. on the size of
the Bcache.
·· . . ···:·:·:·:·:·:·::::;:::::::/;}::.:·.
... :::\(:\:·" ""·::::;;;:::;;:::/Jt·
2.2.1.s sysTagCtlV
Signal· Type: Bidirectional (2107 l.f:ol!i!¢.itkJ~c~~h~:j:-j\;j:\·[:·>
Input Sampling Clock Edge: clkl:F:.;. .· "·::::;::::;:;:;:;:;:;::::::·::<:.;.;.
·
Output Clock Edge: clklF .;/:::::::':)::::,;:;::::.
·:-:;:::t:::::.::;. :::.:l::,:;:r·
-:-:-:.:::::.;:; ..

sysTagCtlV indicates that the ca#.1,~!:iiht*if~$.::::Y.alid. The 21071-CA chip sets
this bit during cache fills, and . ~l~f's th11F6.*1fA:qri.Pg DMA writes that hit in the
cache.
..::;:;:;:;:::::\):!\..
··-:,\:t:t\t:>
·.·.·.·.·.·.

··:·:::::::::::::::~:~:~:~:~:~~~~~~~~~~::::::.

. . =:::/~.~.~.~.>:··

2.2.1.s sysTagCtlD
Signal Typ.@;. Bidit~fl~hal<~107'iI:al!,:'CPu, Bcache)
Input SaJ#.pJ~pg;. CloclFi14K~k~Ikllt:;:
Output CI66i.]t)t.(lg~; clkiF< ::((:/\:

2.2.1.7 sysTagCtlP:j]l/

Signai\L~.l:i:Bidireij~nal (21071-CA, CPU, Bcache)
~9.~· Sa!iil.J~gg:JJJ.g,.k Edge: clklF
J)ijJ,j).ut
Cl~IU~4fe!"
clklF
·.·-:.·.·.·.·.·.··:·:··
··.·.·.·.·.·-:·:·······

.·.· .·. ~::'.:'.;'.::::;:::: ·=·

syWf.~iQJlP. is an even parity bit over sysTagCtlV and sysTagCtlD.
.-:·:::;:: :;:::::::::::::::::::::-:·:·.

. ,::ln~,j~!J:::::!i!Q:pCWMi.1~?:;9?

•• ····•·•ili!l!~:=·~1~1tCA

Input

:::t.:t. m:>' Input Sampling Clock Edge: clklR
:::::::::::.::.:i:i\jj\:\jj\i\j;::::.:.:ljl\\jilj·j.::::·~puCWMask<7:0> is used on CPU-initiated read block and write block
:::::::y:=:.:.:m··:-=:..tt~psactions.

These signals carry different information on both these

·.·:=::+::~r4i:i§~ctions.

Digital Confidential 2-7

.-:f: l!il: : 1:1:~: ~:t : .. ·.·

;;;;;;• :Jll}l1 ll!!l;k +•v

rntII\ '.·:.-:-:-:-:·:·'.· ·\.,.·:~:'· :~:=:,·=.:.:~:~·.'·':'··:~,:.;::.:.:=,.:;=.:.:\·'·.~=r=:
<t!::r=:'

•

On CPU write block and CPU STx_C transactions, ~i«•JiJmia1slll1111

longword mask for the whole cache line. An asser:t.~dJ~pti:Qb~~k "'$lgfhil
indicates that the corresponding longword from "'t:~i!:jtache""Hiii[:i!@::[Y:l:J.id, and
should be written.
..:ft}/:::::
"'":::t=ttlf"

~P~~~:~~~~=!~c~!~.isc~~•:Q.i!!la~>o3i;rih:;e
combinations that correspond to a single
or fortgwptd.
49.l@i!W:9.r~

•

On CPU read block and CPU LDx_L trans~~traa~,::::·th~L~P~CWMask<7:0>
signals carry additional informatiop/i.~µt::Jhe reaar::#r~saction.
cpuCWMask<l:O> carries addressJj~iii!'!~;f.~aM:4nµicatlfig':the address of
the actual quadword that missed.~?\}~~/· ····::::\~~}@{;~;~;~;;~~~~:(~:==··
<·>'.·:·:.··

·:·::;::·:·:·::;.;.;.;'.·'. ..

2.2.1.9

Whenever tq~Jpf~¢ij$~&t,.w;'~f~:l!lt~l::initiate an external transaction, it puts a
transactioq:::~YP~fcoijij:::P.ntqwpudReq<2:0>. Table 2-2 lists the encodings for the
different titl~'act~9fi[a:YP~~f: \: :
·=:r\~t:~:~t::·:-:·;:~{:}:·=

.~~}~:}~~t

Table::I~:: cP:~"'"'''~j~wlansactlon Encodings

·-··::::::::::::::::::::::::::::::.o;::.:::-.,..:-. , . - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

l\llliransaction types are held on cpuCReq<2:0> until the end of the
transaction. Therefore, there is no need to latch these signals.

2-8 Digital Confidential

2.2.1.10 cpuCAck<2:0>

Signal Type: 21071-CA Output
Signal Destination: CPU
Output Clock Edge: clklR
··.·.·.·.·.·.·.·.·.-.·.·

The 21071-CA chip provides transactiont~~kpmvledge:::lfif.~ltation to the CPU
on cpuCAck<2:0>. The 21071-CA chip#~:::~Jiij!::9@lltn\fi.ver. .'dflhese signals. On
CPU initiated transactions addressed\tiQ:::the 2".iOf.f~tDAJ>r the PCI, the 21071CA chip receives transaction ackn.,9.Wli4.i~. informat1q@m\from the 21071-DA chip
on ioCmd<2:0> and forwards it ~~Wtb~::\:QltUA~P. cpuCAtk<2:0> in the following
cycle.
:·:... ·;2:::::?· · .": : : : : : : : : : : : : : : : :·: ··

"::;:\\litt:J>:=:::,.

Table 2-3 lists the el).:~.odings::(®:::¢.pµQAck<2:d>.@?:
.-:::::::::::::>:::-.. ;.< }I:1.: .:r.: .i.:.i.:.1t.~ .t.:~.=:.: .: . . . .
·-·
·::;::;~:}\~::::··
Table 2-3 cpuq~ck ·en.~~l,~~l!.. ·":::::;:;:y:::;;:::;;...:::::::::;:;.
·.·.: ::~:~~~{U~~~ffil!t:: : :.

000
001
010

:Jiit°' . !-;~~=~:c::i:: :: :h°.."!:!:1::~:=~as
1

corrected. (not used)
CPU STx_C transaction failed
Transaction completed successfully

011

100
101
110
111

=:::::~:~:~:~:~ :~: ~:~:~~~~~~~~±· ·

:;;:::~:=:=:·.;.

Digital Confidential 2-9

Table 2-4 cpuDRAck Encodings
cpuDRAck<2:0>

Acknowledge

000
100
101

Idle
ok_NCache_NChk
ok_NCache

110

ok_NChk
ok

111

D~~i::&ijjjml)J9p.'t ca~h«\ti4.,6ti.'t check
D~m?JiH~\\}!~~~t~~che,:8heck ECC or parity.
~~rurused) ·.·.':'<t:::t@fi}t,,::,.

_,:):]Qjfj\yalid, cache{ijjri't check. (Not used)
::t:I:{u~mf!f.9.4.~ cache, ··:&heck ECC or parity
·.·.··:-:-:-:-:-·-:-:-:-:.:-:-:·····

.}}}~:

2.2.1.12 cpuDWSel<1 >

·\{)\)X?t

.tr:··

··=::::::=:=:=:=:::=:=:::::::======:: ..

Signal Type: 21911,QA. Outpti,jl:lj!::m:::::::i::::

~~~t~~:;~:!!ll~>······
-:.:-:-:-:-:-:-:-;.:·:·:·:::::::;:·.·.

-:-:-·-:::;:::

. .,,.,,,

During a CPU ~t~~::.tfi:~:':~107TiC.i:,~f.µ:p uses cpuDWSekl> to indicate to the
processor which datiF\y~~~[l:~~~~ld b~?driven on the sysBus.
When the sysBµ~j~jdle,'BP,µ:QWS.~kl> is asserted by default so that CPU
write data Cf.l.f.:fi'l~:!'it~~~p:,,as Q.tH~ly as possible. When the 21071-DA chip wins
bus arbitra.t.j9.#.f"cp4.Q)VSel~1> is deasserted during the same cycle cpuHoldReq
is asserte~_~.:_.:,~_:,::_}H/ .·.·.·.·.·. . .
-:'::::<:::::;,
.}'.\:;.. -::::::;: ..
:;\t:=:'.~·:::t:~:/~·:;::::::::

:::::::;:;:::::::·

__,.:::.~·''''''~':·:....,.__.,...~~..............................~~..

···:·: :;::::::/::::::::;:::::::::::;:;:;::::.:-.·.·:·:·:-

Note ~~~~~~~~~~~-

. ffb\i::)·ate af''W.HiihtCPU write data is available on the sysBus is

.,:::iH:i~qnfi!QHed by the 21071-CA chip with cpuDWSekl>. The 21071...,D~/!(UQ:J~tjdge) chip is always capable of accepting all the data on a
CP04h!fi3t~d 1/0 write transaction on the sysBus. The 1/0 write can

stal1ed:\:\Q.#lhe sysBus by delaying cpuCAck<2:0> after all the data
::::::::::::=:::::Jui~ been fafched.

2-10 Digital Confidential

2.2.1.13 cpuDlnvReq

Signal Type: 21071-CA Output
Signal Destination: CPU
Output Clock Edge: clklR

···:·····
.·.·.·.·.·.·-::::::
.. ;:::::::::::::-·.·.·

~:t~~~~~~E:z~~~~EJ:!i~ii~~~!!l~tb~:~~~~
version of sysAdr<12:5>. This signal should beliidHt~ii~h~ c:Ptr~· dlnvReq pins.
~

2.2.1.14 cpuHoldReq

.-:::::::::::::::::.::.·}::::::.
.... :-:·.

:.:-:-:-:-:-:.:-:-:-: .. _'.:=:\ :}}::-

··:::\{/}:}::::-···::;:;.

·.·.,·:::::::::::::::::::;::::::::::
··-::::::\}}/'

Signal Type: 21071-CA Output :i·i. »»>;·.·· .··.·::;::t::·».i::;jJ%:::
Signal Destination: CPU
·:': : : :. . ·.·.·.·.·.·.·.·.·
··::.::;:::::\: :::·=··
Output Clock Edge: clklR J:::::(\:l:f:f{it:>
·: :;:,: : : :-

The 21071-CA chip asserts cp.~~ia&~\£ij,f:gi,~:::~rw..nership of the Bcache
when the 21071-DA ~hip ha~vW.iP.Jijµ~bitrati(itflf.9.r:=:the sysBus. If an external

::;::;:i~~;!!i1~!&i~~~i~ i:s::~t~!;hp:::!;!!:~t
2.2.1.15 cpuHoldAck ::. n:I:I>::::. ,.

·=-:::::n=u:::::.Jl/:>===··

Signal Typ·:::t.~!f~~t·8b.A In;~fu:::::111111::1:=··
Signal Source: C:ro:::-::=:.0::·:.:+=:::=::::
.
Input Sa:m.eJ~:~n1\plock(~~ij:9: clklF

The proces~4t:-=.i§'~~f.tijrnpuffolaA~k to indicate that it has given up control of
the cache @jij\lie ~JAJ'i-Qt.\:j[~hip. The minimum delay from the assertion of
cpuHoldR~:jl~':Jg!:)isser#:~9.f, of cpuHoldAck is two sysBus cycles.
The dfii~ertiijfi::.!ifJmµJ.lijJdReq causes cpuHoldAck to deassert in one sysBus
cycJ~~.JlVhen th1FP.r~isi6r asserts cpuHoldAck, it will have turned off its
exttrn~li:drivers on
before clklR. When the processor deasserts cpuHoldAck,
jt d&~i,:i:~'Jj\)~}:t~ on its drivers for two CPU cycles after clklR.

. =·· ...

::::'·:i~i22=~:::=>\gl,@phe/PAL.·.··:·ntrol Signals

·!iliar1yoeer1'"t?
;I ; !;. . . .;! II i ss~gnall TypDe.: 21?71-CBA Ouhtpp~:
.:::::::::::::2.2.2.1

1gna estination: cac e n.u
' ':@: ..:%<E+:::: . Output Clock Edge: clklF
:= ::: ....[j\. .\»:i.·[:!J::pput Sampling Clock :Edge: Not applicable (flow through)

'':/:':::::=::::.::::

Digital Confidential 2-11

. ·-:::::;:;:::{:\~:}}}::·

Table 2-5 cpuCReq Effect on bcTagOE_I anc:ffi.p@b•Q-=_I . , , , ,.,.;-:-:-:-·
····:·:-:-:-:-:-:-:····-·.·.:-:.;-:.:·.

cpuCReq<2:0>

cpuDOE_I

Command

011

F
F
F
F

100

101

T
F
T

000
001
010

110
111
··:-.-.·.-.·:·.·.·.

2.2.2.2 sysTagOEEn

·..: : : : : : :;: : : : : : : : .

:::::::::::::r::·.·.

··:::::::::::::·:-:-:-:-·-:·:··

signal rr:'~f._:::~:~91::kPA"aa~~~~:::·1:-·:m>·
Signal Destinati9id%~~~che PA$?

~~~:~:~~:l3W• c:o~~pplicable (flow through)
:·:·:-:-:-:-:·:·:·:·:·:·:·:-:·:·:·:·:-:·:·:·:·:·:.:-:·.·.

·.;.:-:-:-:.:-:-:··

sysTag0E$.n:·:.j$Wi~'~~~icfqy,th~''2io71-CA chip during DMA transactions after

the proces~9#]1as.,mv~n P.Wb.ership of the cache by asserting cpuHoldAck.
sysTagOE~f\.:=:~~,,,@~~fass~r\!:4 during CPU-initiated non-cacheable transactions
to avq!,q:Jpng[:~p["Ji,~~-:-:~Y#!f:hm sysTag<31:17> and sysTagCtl.
·

sys.~-~En i~/i~i~ttitfU~n clklR in the first cycle of a DMA transaction (the

cy'-l~\\:\wb.~.n ioCmd<2> is driven). During all other cycles it is asserted and

.·.·. :)::(}:t :::::.9eassin:::9e.. c1k1F.

················

... :-:·.

·.·.·-:-:-::::::::::::::::: .·.

.:-:::.::.'!:!~~~2:~3n:::~l!Pataol~en:::it:l::r:::-f\l:.:\i.\:\[Signal ~:e: 21071-CA Output
::<::::::::::;::::::·Signal Destination: Bcache PAL
··: :': ::::::::::::::::;:/)\/:/{> Output Clock Edge: clk2F or clklR
Input Sampling Clock Edge: Not applicable (flow through)
.'<:' 'fl··:::::::::i. ::::·:n:t:::-.

. ::::::::::r::=:=::···

@.\[\:!·\[[\\·\:\\!·l'rn:\::::::::·

2-12 Digital Confidential

::··:::::::::---::..

Ag·;Jt\l !-!!1
!;1111 i!l;t·h

itP.~!l!:~J[LJV

sysDataOEEn is asserted by the 21071-CA chip whenever
from the Bcache. This occurs during a victim read, durjpgj#tJ.)~,_L Bf=i:$~.i~lf

~:n~:::::!a:s~!:! ~t=~hd~:: ~~~g all Djl'AW~iJJJ!~~i\Ge

sysDataOEEn is asserted on clklR in the .fir.st cycl~:·i~t=:itP~A tr~~':iffilion (the
cycle when ioCmd<2:0> is driven). Duritjg[![AJl
.,~Y~l~l:f:!~A~ asserted and
deasserted on clk2F.
..,.,'\'.?
··'''\/{{//i::::;,,.
·.·.·.·.·-:::::::::::::: -:·:··

2.2.2.4 sysDataALEn

~::: =:n!~Z~;cit~~?~k 11;1;·;. . \ .
Output Clock Edge: clk2R
':{/(
Input Sampling Clock Edg~;n:.~,.
·.·.·.·.·.

':'::::::::::::,.,.,.,.,:.//\,.,.
·-:-: :':': : : : : : -: : : ·
. ...

sysDataALEn and sysDataAHEq;;,~~:;~:~~iji:·:t~(tb.e PAL:··to generate the lower
address bit for the Bcache da~~kPs. Tlii!Jqw@~taddress bit must be toggled
to the Bcache duringJ;_ache filli#f:i~tjJil reads/=f@ids that hit the cache, and
during LDx_L and . •tC}1its."·'·''''ffl!=::illl\\::::,.,.
·.·
The PAL receives th~·''';y~PitM.iEn·.,,~i=•:;;~p· enable bcDataA<4> for the period
when clk2 is lowf:t
.... ······.····: . ,.
·-:·: : : -: : : :·
·:···:::<-:·:-·-:

2.2.2.5 sysDataAHEn

...

·-:-::::::::::;::.::::::::::::::\\.·.

·'.·'.:::~:{~~~~~~?/ ~~i~}~~:::: . .

:-,,<t' [:j:,::::::::. :_:·>t:. _ · ., , <rn·::::::::. ::>' '
Signal Type: 2167-l~Q~:-\Qµtput .··

=t~•t~r;::~lf?AL

Input ,:~~pipliiji'.::i¢1~9::1f Edge: clk2R

:~dr•lfs~Jf~~eg:;:;;:~i~':~~~::~~~\!0::Cf;:!.~C:.e

for th,m,riod'\ylj!!~l!\!ll:~l:J~:: high.
/}\:··.-.·

···-:·:::::::::::::·:·:·····

2.2.2.s sy'=J@IW.t;

.,.... ·.. .-.-., .··=:::!Iit'::.:·.··.,,,~~•1:~!~_e: 21071-CA Output

._,_·,:_'_.•_:_·_:_:=,:_:_._:_•.·.:_=,·_:_·:_.:_
.:
· ·••-:-::-::

_:_' .::_:_>:

f:•:@j]\_Sig:nat•:=1Qijt!nation: Bcache PAL
tJf]Putput
Edge: clklR
}:/{]Input Sampling Clock Edge: RAM We

·aock

!fhis signal is asserted when a write to the tag address and control cache RAMs
'"'"'::::-::.,,,,:';is needed. sysTagWE is NORed with the CPU write enable pulse to generate
:•• f :::-".\I.·~\\.§,,:,tag control write enable which is then inverted to generate the tag address.

Digital Confidential 2-13

2.2.2.7 sysDataWEEn

~!:~ ~::n!!?!!;c:C~~?;k,

;~flj)~l,ilc'i )j!jli1!l:_ 1_.·,:._:,.:_,:·'.,i_:_,··,·.~_,.:_:·::.~_,:·:,.:_,::,.:_,'·_.'::,._:

i)ftill

Output Clock Edge: clklR
Input Sampling Clock Edge: clklF,/t:=:::::. ·

·:''f\[i[::::.~::'ti[_j[~\f})::=:...

l_!,1.:_.'..·_..

. :,.:,:_:,.:,.:_·.:::·
.

·.:::::

!:!~:!~s~a::::
~~ ~::~J.:::!~~9~~--~.~
~~e
actual write enable pulse is generated by the
WEEn
J?Aij=[:py\~N.Ding."''sysData

with an inverted clkl signal, it is then ~lQR~~ withH~ij.~fJJ.:PY. write enable
signal to generate the data RAM write,::~P~§J.~~=!?>·':·-:,::t(:]:f/'

ff:}?'''
' '<\.':ts::;'·:·,:,}\:.::
:\{;'.:::

2.2.2.8 sysDataLongWE

............ .
·-=·::::{~:}::;.:-

~:= ~tln!!?Z~;Cit~~lll ! ii\!\,
~~i::=!~~~-lIVW·;;;r1:~llii>
!!!~:!~~s~a~~~~·[~f;:!lll~~ ~:i~e.~;; =~:.~s ~te
enable pulse i~::=N(l:Red witfi?th.~f!P.:PU wr:mr enable pulse to generate the data
RAM write eri:~Bl¢.)~:,j·?:\::,
··:<\={ ,: : : : : , , , _.
·ww·•

-:=:::::::=::::::::::..

2.2.2.9 sysDOE

···::::::::::::::::::::::::::·:::::;::·-:·.

·-:·:::::::::::::::::::::::.:::::::::: ..

Signal Type.;:::g1011~'CA.·:Qhtpµt

=irt~i~:,

sysDOE ertib.l~~-:::i~>pro~~j$.6r data output enable during CPU external write
cyele~~:l~ysDQfi:[!l9.w.~ ..t.Ar9Ylgh the PAL, and causes cpuDOE_l to assert.
::;:=:;::::::::::::::··

····::::::::::::;:::::::;:::::::::::::::::::::::::::::::;:;:::;::::··

2.2.3 PCk@rli·9elntiff.lc~Psignal Descriptions

2._3,~:f::~J,,,,,:=:-~oRiei.!:l.:7,~>
.
..
··:-:·:·:-:.:-:·:

· · · · · · · ·•~'./"' lif\j\'fll::::~l~i~;~~D~put
·• ;i:.i;iilru . . lll!)~~~~~=:d~::i~:re: clktF
. :::;::::::=::::;::::::;:::)?}The 21071-DA chip asserts ioRequest<l:O> to request ownership of the sysAdr
·::<Ut=?}.·%Jines to perform a DMA transaction. ioRequest<l:O> is acknowledged using

.. '''::\-[j~()G.t~nt.

2-14 Digital Confidential

loRequest<1 :0>

Function

00
01
10

Idle

11
~=~~I~~~~~~=~=~::=:

·:·=::::~::::~:~:~:::=~~~~~~~~jt~~::::=·

::i::rn~:s2~t7ol!:~,:;Pu:i:•~:!l~~:d!:!e~~Y~!sa:te~s
and programmed p@~?ty._:=:=··
·:;:::::nit::)jl~:_!·=·!!\.::::;:;:>:=:=::-:-.
The 21071-DA c.b.ip usesU~i.~::il~MA atoml.~::::tequest encoding when it needs
to do multipleJ~l.MA:_trans1fot~9.µ~')m,_ the ·sysBus without the intervention of

5:~EE~~~St~~!~l;:!;::~i::~Ea;~:ec~fo~~~~A

=~~::#illlmar;:~'R:ns~:ig;~
~=s ~~~:; ::i:ry
address space. Preempt request forces the
0

::::

addressingi)iQ)~= 21Q1\llDi\/~bip

21071-DA =9.tftP:-.t~d#:ih ar;lj~~ration and causes the 21071-CA chip to assert
cpuHQ.ldP,eqi)]b.ttb~::=·1nidQ.l~)i'pf the CPU transaction. The 21071-DA chip can
keep
pteimP:Mtm.Jq'-st up for consecutive DMA transactions. For example,
wq~:]!.iJ~PU reqtieifaiieed.s to be preempted by a DMA write transaction to
flti.$1)/ib~LPMA write buffer, the 21071-DA chip should keep DMA preempt
. .:.:_: :.: ..::'JUttJ~.eqti~$tiii~i.~rt.ed through the entire flush of the buffer until all DMA write
;.;.·::;:::;:;'i!!!!':U'Hil?t:\:_\:::::~rt:Psactnif:!~)··¥~~- been completed.

:P•

,::t<.:::2~2.a.2

·10.sr.ant
...

::•::@=\·\{)j!iJ!!!\J:iil!:.:·::+:+!!!!J!!!!i!j!\!t· y<· ~:::: ~:In!!?Z~;c:i~~~~~
·::'f:{:!··.n=:::::-=: . ·:.: : ; Output Clock Edge: clklR
· : ::::::::::\){/\::Jpput Sampling Clock Edge: clklF

Digital Confidential 2-15

!Ifill;,,· s11tl'

~"111,:11+

'!!3,~ w~K ofltmµ.,

The 21071-CA chip indicates to the 21071-DA chip that it
the sysBus by asserting ioGrant in response to ioReque.~~~iJ~~b:Qn a$:~fii.~9.~¥fof

:~g=~ !~ ~::Ji~i~~hi!eU::i1:~:~~ :~ ~~~1il!~~-~~en

new DMA transaction. If the 21071-DA chip sarnpl,~$.:::~P.G.rant as <rn&$.$.erted in
any cycle, its sysAdr drivers must be tri~tj;t~4 on th~:::~ij$.:t:::d.Jc1R. The:·· 21071DA chip uses the ioGrant in cornbinatiotFW.lth)~p.uHoldA~i]:::t.~:::d.~termine if
cpuCReq<2:0> should be ignored.
··.·· :::i;::j:iJlJiilJ![lil!.]:)\>:. :. ·.·<:>f\::i:::::i::I.:2.2.3.3 ioCmd<2:0>

-:-:::::::::::.::>?n::::::::·

·.;.·.··'.·:·:·········:·:·:·:·:·:···:·:·:·:··

The 21071-DA asserts chip ioqffiij\$2:o>>tQ:::Rµ~~~ an action by the 21071-CA
chip. When the 21071-DA chU?:UbJ!~\the sysBt@.W~§.Crnd<2:0> is used to request
a bus transaction. ,/\\::::-.
·.·.··::::r::::;):;;;::::;:i:::::·
........·.··.·
When the CPU ha~<th~: gq~tJoC,~d~i.~l~:\:i~::::µsed to request assertion of the
cpuCAck<2:0> ~Hl4.. cpuDqi,~~:~9> sig&am,~r··
·. :::::::::::::::::::·:::::::;:;::~: :::.

There is no en~~:d:ih~\ijf.~J.\~p~DitA.~k<2:0> ok_NChk. The 21071-DA chip
never return~::W~~heable~:::#§tbs!ieckable read data.
.··.·.·.·.··.-.·.:-·-:-:::::;:;:.·.·.-.··· :-:-:-:-:·

. ::::::l~!i]\::::\~\\ilhJP.C~d~j~c.§j:::::m~P.P.U Owns sysBus
i:i~;:w ;y~I;; ······<;;iit_k

:\\)\:

. Joto/

::::+r;:.:=::.:':}:\f\:>..

t\:UdT

-: :-:·: --: -:-:-: -:-:-:-:·.:· tHUfoo
···:::=:::::::::::::·_:·::··::_:=·:. J}fao1
::=\/tt?iilL.

··:·:::::\ij'J2]'):

cpuDRAck ok_NCache_NChk
cpuDRAck ok_NCache
cpuCAck ok
cpuCAck Hard_Error
cpuCAck Soft_Error
cpuCAck STxC_Fail

2-16 Digital Confidential

21071-DA owns sysBus
Idle
Flush
Write
Write masked
Read
Read burst
Read wrapped
Read burst wrapped

The 21071-CA chip asserts ioCAck<l:O> t~''"acltiwl~dge ~'''])NfA!.!ti•ansaction.
ioCAck<l:O> indicates that the DMA transactiort?ijj.~:)~~~-n com'.pieted. If any
error occurred during the transaction, a:n.J~IT:Qr resphii$:~:'!\Willbe sent. Table 2-8
lists the encodings for ioCAck<l:O>. ,:/,:;,._···.-;.:;.:;)·(>=.... :::..
·:·:::<i:ij}t·
··:-::::;:;:;::;::::

Table 2-8 loCAck<1 :0> Encodlng,~ttl:t::\
.
.-:·:·:-:-:-:-:·:·:·:··-·.·.·.·.·.·.·.·.·.

:;:::;:: ···.

·:::;:;:\~::·:·:·::::: ..:. -:-:·:···

Function

loCAck<1 :0>

00
01
10
11

2.2.3.5 ioDataRdy

···::::::::::::::::::::::::::::::::·>.·.

Signal Typ~h:?.JQ7 i'~t£~~i:fi#.tpµt
Signal :g~§~;t4§J;i: 21<Yt1.~DA
Input §l.!li>liijgjJ2lt1:@lf Edge: clklF
OutpU.ti::QJocJ.¢.j:Bdg~;Jl.lklR

During\~.n~£IWJ~:jf~·ad 1j~JlktaRdy is asserted when read data is ready on
the sy~l#s. loij\i.ly\]~N1sed by the 21071-DA chip to get an early start
ge~tmiUfead dafa:Firoin/the DMA read buffer without having to wait for
io©~~~i\;O>. When the 21071-DA chip receives ioDataRdy, data will be
:(f{}]l=:d!vailit).:\~i::9fp~piData<31:0> in the next cycle.

· · .·:······-· ····=·=::::::==·=·::::::::~:~\:;._

···=:;:::::t~'.r=:::=:::::::::::::;.

·...·.·.·==··:·=·:·:==:=:::::::::=mt=)>~--··.,=_'==:':~==':=:=...,,:-'==·-'"'·=·------- Note - - - - - - - - - - - -:-:-:.:-:-:-:.:::::=·:

····.·.·.;.-

The number of ioDataRdy assertions may not correspond to the number
{)::'':::; _,/:~::):,:li\\\:·:1> of octawords loaded into the DMA read buffer. The 21071-DA chip
· : :+m.·::\[\l\l.·:_:[.::!·j\_:j:l::::'.....
must ignore ioDataRdy if a DMA read is not in progress.

Digital Confidential 2-17

2.2.4 Data Path Control Signal Descriptions
2.2.4.1 drvSysData
..::::::::=::...

··=::::::::;::::::::::::::::.·.:·::::::::-.
··:-:;:::::;:::.
·.· ..

Signal Type: 21071-CA Output
.·..·.·.· .·.·..·.·.··.···..
· ·-:,: : : : : : : : : : : : : : =: :.
Output Clock Edge: clk2R assertion, clk2itj!t.Je;.$.~~rtion>::{/>.
Input Sampling Clock Edge: clklR..·.·.·.;.;.-.·.
~ssertiOH~W~llitltdeassertion
.
··.·.·.·.·.·.-.·.·.·.·.·.·.'.:-·-·.·..

:-::::::::::;::: -:-:·:·:::::::·:::......:::::;::;:::;:;:;.;-

{:\}\?"

2.2.4.2 drvsyscsR

·:-:;::\:)\\.·. ..

··::::::~=r=:::::};.;):=:=::·

Signal Type: 2tQ7J-CA ·'rlti.it.L:=:=:.
Output c1ock'''~4.fe;:::£~k2R:::::::t:':,::::rn::::r:1::::::::::. .

Input Sampling·:ctpi,¥::::§pge: dk~Jf~:::\I:::-·
drvSysCSR is . :~~$-~rt~.d b)/tif~::\.glQ7J:-CA ri}{ip to indicate that the 21071-CA

chip is driving."'sy$Jlitt!<s..i5:0> :Mf:,:tP.~Hg~~t clklR, and that the lower order, the
21071-BA chips, shht)J~;f:[i#~t~rive. "tHi.$~flines.

The drvSysCSR siw.ial::f~:\ij~IJrulY de.asserted, except during CSR reads. When
drvSysData i~::j~~~~q~:'"and''difY.$ysCSR is not asserted, the 21071-BA chips
will drive aJtl:$ysDif;A~')27_;P> Hri~s.
On a CSR!:~-~ t9/:~h~?2tt1it-CA chip, both drvSysData and drvSysCSR are
assert~µ. 111.Y~{jmlf)fesu\t\:j~p\' the 21071-BA chips driving sysData<127:16> and
the 2tU7:i.~cx:::~fu.P.:::4riYi~g)~ysData<15:0>.
::::;::::::;:;::===

2.2.4.a drv.,Nl'-miata

r=·: ·

····:::=:::::::::::?:?::·:-·

·.,:·:· · "'"'"'"'"': : :. ·:-::::§iiltfype: 21071-CA Output
Input:::s@mpJ~ngEdge:
ClockmemClkR
Edge: Flow through
:-:::f:if1J>utpu1/QJ®k

·••.·::···:,::_·:_:_,:::::::··.·•. ':_,:
..
,:::_,:_.:::::_:_.::::_::::··:::::_·.::=:_.:·
..• :_.:_.'.:(··\:

::::::::.

· ···:::::::::=: :.:.::}~//:::;····tm

._. . .

_:}:\::::::.

:,:!4.f&.i\1emData i;'asserted by the 21071-CA chip to indicate that the 21071-BA

'/:::::-:::-::':?:% >•::::-.. _ ,,)··'.."~l)ips should drive memData on the next memClkR.

2-18 Digital Confidential

2.2.4.4 syslORead

Signal Type: 21071-CA Output
Output Clock Edge: clklR
Input Sampling Clock Edge: clk2F

2.2.4.5 sysReadOW

Signal Type: 21071-CA Output _,. -:-::':'·'· ..
Sl.gnal Dest1"nat1"on·. 21071-BA ::::::::}: \{\ _:l~.·~.-~,~.-~,·;_: ;:::/?:::.·
Input Sampling Clock Edge: cll(~f
····.::;;';'.'.'.:;':.;:;·;i_._.,.:.::
Output Clock Edge: clklR . . _. __.: :, , .:.:.: : : : .
····::''\{'.}}}/.
=·=·=·=-=

sysReadOW is asserted by the 2t.of::l{i.el.::liP:,,.~o indi·~~te to the 21071-BA chips
:~t ~~e r~~~e~:;!~;ord of da~fhj!puld hM"l~l::ifr.om the memory read, merge,

2.2.4.6

subCmdAc1 :«», subila~1 :~,J~eom:n
:·:\r
··:·:::::::

. }~:~}?\:::..

·..

··\II~~/\:~::::=>

Signal 'IYP.!:t._210712(),~:]P:µtput '''<\/\?
Output CJ~~~jj~~ge: Clkt.l~i~)}\~\\:~::::-...
· · :·
Input Sanipligg:;.(:JJ9ck Edg~#:[-~~iF

The subCmd<l:O> ~'{~.fiii~:::~r~t.~ss~'l°t;~a' to further qualify the sysCmd<2:0>
signals, as describ~d in Tilb.J~:i:z+:i.Q.. Connection of the various subCmd pins on
the 21071-C~:.£JYpt:-~q·:t~h~ 2i61Wt.jpA. chip are described in Table 2-9.

,:::::-:-:-:-. \'iWl]f!}!}21071:fl.4':Pin, 64-bit memory
21071-BA Pin, 128-bit memory
21071 te~MPln· -,:,<i:?:rn1P~9qfi~lf 21071-AA Configuration DECchip 21072-AA Configuration
subCtrtdA<O>

,>';=-~'

··-:,:::::::2=fh7i-BA 0 subCmd<O>

21071-BA 0 subCmd<l>
21071-BA 1 subCmd<O>
::>>t>=:>=:=tn 1~µ,µomdB"<1$.it= -:-:-:-:-. 21071-BA 1 subCmd<l>
·-:\@,i~¢.mdCommo#.I?. Not applicable

21071-BA 0 subCmd<O>
21071-BA 2 subCmd<O>
21071-BA 1 subCmd<O>
21071-BA 3 subCmd<O>
21071-BA 0-3 subCmd<l>

Digital Confidential 2-19

2.2.4.7 sysCmd<2:0>

~~;;;~;.;~~;~~A~~!C~~~~f:

general, they echo the actions taking place ofi{tfii~:::~y~Bus dtbini(the previous
cycle. The bits are decoded into various action~i'=Ba.$.eq\\\gpJhe iiiformation in the
following table.
.·.·.· :=:=:=<?: ..·.
·======:==::g;;:;):~\:::f,;::::\':·.
":·::;::-: :-···:;:::;::::-·

Table 2-1 o sysCmd<2:0> and subCnj#,$f:o;nj$'giJ.Jggs
:-:·:·:-:.:·:
···:-:-:-:-:············
000
000

001
010

RESET

:f{lllf\p_ad latches4i\:'held (to save power).
<~PP
··==:=::~lt\l\\\l\l\l~::=4~ta in the pad latches is held in the
·= = = = = - ··.··:.
··=-===tli?.i:ijijt~d new data will not be clocked into
·= = = ==-==·= ::=:::::
themtlU$ed during reads, or to hold the first
·-====: :=:t . : =: : ;: ;=- transfeFof write data due to a full write buffer.

l.i1+·······: lts:~!~!:i~::!~~:~~~:.'."

xx . ;;
xx

ilf]Ii'!' ···· :io~~~=r:~tf::'~1:i:e:e!i~i!:;

; .. •

-: ; : : : -:.: ::::::::::::~:\~{/(~)::
:~~\;:>-:-:-·
. :-:-:-=-=·=-=·:-

011

. :[\[\][JTM~:::~~-J~!ts in the merge buffer are cleared.

,,,f\Jtf All sysBijijHi®ters are reset. The data in the

I/O write buffer. A counter is incremented so
that the next RDDMAS will load data into the

~ii11lt1I\:;; ;i~~~i:i~~~;J;:~~!~
the next sub-cache line of the buffer.

(continued on next page)

2-20 Digital Confidential

.....·.·.·.·.·...

. )}{~~~t"

: ~:l:~:j:~·-~:~-~:~-~:~-~:~-~-~-~-~.:.

·:-:-:-:-:-:·>:·::::::::::::::-:'.:...

..: : .: ·_.: : _·_.:~-.:;.: .: ·_: : : _: ·:_:.: ': .~:~:}: }~:~: : :. ......

·: \~ -.:_·~: .:.;: : ' :_:_;:~:.:.:_ :.::::/·
:::::::~{::::;::::> :{~(~\~{:·
·.·.·. . :··.:_·::_·.~_:·_:. :.::·:·.: :~: .: :_~: _:·: :·: ·:· :·. )f}} .
\.~j_~-~-~.r.:_~.r.:~~
Table 2- 10 (Cont •) sysCmd<2·0>
and
subCmd<1
·o
Encodings
.·.·.·:;:;::
·=:=:=::;-:===:=::;:;:
•
• > . /::::::::::::;:/:::::::,. ·>.
)}:)?(??
................. ·.................. -..

-::::::::;::::;:

•.:_.:...

.•:::.:.:_:._::..._::_'..:

sysCmd

subCmd

Mnemonic

100

MERGEOO

Function

Nothing is loade~f:~tjtti{ the m~;~,)!'il~f.~· A
counter.. is incremented:,,so that the. :hext
MERGEnn will foM:kliikinto the next subcach~~j~wf o,f:~~e buftJ£tt:r\]\\::::::-

~~~~ge~:~!l1i:.~~:~~~~1~!:!':!:;et~:ffer

is loaded twice:·:::'O.ifoe(With the CPU write
dats~d#i.f.#g:J4ERGE'f°ttb~¥]$~ MERGEOl), and
on~#\a.fiW.tJ.ij~f:~~~he dat~)ising MERGE with
inyj.rj;ed.en~~~t:~aj.led an overlay (that is,

OVLYlO).

100

MERGEOl

·:::::: .·.· ::/:::::::>:.

;i!l~l•:~~~h!!~~~'!d.,~~t! ::a~~the

./::,))}j'"/merg't~(tfit'f.~jfm;id longword O's merge bit is set.

100

~~RGE1&i'i'l):i!i::l!\i·l:::!ll:m~ in MERG$.oo, but longword l's data in the

<::i:::>x· : : : : . ·:-:,::::\{\i!l:filf.~~;.:r1:~3~~~~~~:etsi:~r~~eb~:~~ set.
~:::1rifaijERGEOO, but longword 0 and l's data
'"' ·"";;:::'.::::::>::'\\:::::Jn the\fysData pad latches is loaded into the
<:::::::::::/::::?:::~~~merge buffer and longword 0 and l's merge
· "'':\(ijj~~':are set.

101

Data in the sysData pad latches is loaded into
the memory write buffer representing cache line
0. A counter is incremented so that the next
WRSYSO will load data into the next sub-cache
line of cache line 0.
As in WRSYSO, but cache line 1
As in WRSYSO, but cache line 2
As in WRSYSO, but cache line 3
WRDMASO

Data in the sysData pad latches is merged
with the DMA write buffers and loaded into
the memory write buffer representing cache
line 0. A counter is incremented so that the
next WRDMASO will load data into the next
sub-cache line of cache line 0.
(continued on next page)

Digital Confidential 2-21

sysCmd

subCmd

Mnemonic

Function

110
110

WRDMASl
WRDMAS2
WRDMAS3

As in WRDMAS.q~jljt~~\i'.~che linEFft:~::l\:\;\.\:::J==·

110

01
10

:·:·:·:·:·:·:·:

~ ~~~-:::~!llrui~::
········

.(\?){

111

10
11

111

WRDMAMO

··:·:::::::::::::::::::::::::::::::::::..

····:-:-:-:-:-:-::;::-:-:-:-·.:-:-;.· .

.·-:::::::{):::::::=::::::::

~~.ih~~t!\i,liE~:i ~~~~

thet#.i•m9.f.Y\W::J;ite buffef:@epresenting cache
liniJk\A\countet\.is incremented so that the
neiMWRDNfAM(fwm load data into the next
·==<f9™~che line===MM;l.1~ line 0.
WRDMAMl ;.:.iii\jj\.li:~:\:~~i.ili~AMO~====b~t cache line 1
WRDMAM~::O:=:::Jt/ As in.'Wff.P.MAM.:O, but cache line 2
~MAM$::j\.:.:\l!:.[::jl·'l~. in wROM~O, but cache line 3

The memCmds?::;:l?!:::§j~!j:~:::[6.4.!~~te to the 21071-BA chips the action to take
on the mem:Q~t,i:(f.:.)µl~~U\:fu.emCffiu~3·:1> is driven by the 21071-CA chip on clk2R
and latche9lmFthe
.. 3.\~p7 l~Ji,A
chip on clklR.
·.·.·.·.·.·.·.·.·.·
.-:··-·.-.;.·.·.:-·
..:.;.·.·.·.·.The bits a*f.l\:i~.c9ql.°==. int~illv~rious actions. Table 2-11 provides complete a
descriptjpn==:~j:J.b.~i)j~1em.Q#)j<3: 1> encodings.
:::::·:::i!.,\\)==·

T@Pf.it1±~1
····:·:·:·:·:·:-:·:·:·:·:-'.·'.·'.·:-:·:·:·

.·:::::~::::::::::::::::::::::t~::=·;:::::::':<::::::::::::::::

mem-C:md;<3:1 > Encodings
Function

No operation.
All memory pointers in the 21071-BA chip are
reset.
(continued on next page)

2-22 Digital Confidential

Table 2-11 (COnt.) memCmd<3:1> Encodings
memCmd

Mnemonic

000

RD IMM

001

RDDLY

100

WRIMM

Function

Read data is loaA!J.:::~~to the ·;~l'fu.e
buffer . on the n&XtdnemClkR. A count.er is
increrrtfuited so thif./tKimnext RDxXx will load
data''ii'ifthe:::next a~%iili.bil'-Hsub-cache line of
the read. l).#.ff'#.f~t:::-.
.···...://;/:::;:::;:?:·
Read data 'i~::'}lili4P.:to th~:::~kdlmerge buffer
on the memClkR:::lif&Eit.he next memClkR. A
coun:tiRis}incremerit&Fiifthat the next RDxxx
will:::l~amdiitd.nto th~''hiit available sub-cache
liri~k6t'th(ffMM/buffer. ·
)ff)
. :::::=:\:::;:'.\:}~: ...

: :_ '_ljlljlll!ljl-:\\~~11i~i:~1:. t1:::~:~ =c~::.e~i:o~~;:;is

_ (\(if\ increniented?so::-that the next WRxxx will drive

_-: :-: -:.

''\f[:t::tlJhe next stib.~¢iche line to memory.

WRDbXff 7 . ;.;. . ·.·. ''i)i;!.tr.;: ~: fu::~= =e~~= ~~en

101

--"-:-:-:-:::-:.:"'-:-:-:

memQl)ffi. A counter is incremented so that the

····=:=::=\:~'.~/:???~:!:?:-:-:..next WRxxx will drive the next sub-cache line

.·-:::;::':::]\':·:·':._---:~Jpemory.

110

.......

·-::::::::;::-..

:::/]{!{.:_: ...

.::::::::::::::::::::::::-·

==::::::::::::~:\:::::\.

··:·:;:;:::;:;:;: .·.··:-:-:-:-·

·-:;::::::::::: :·:·:·:··· ..

Data from the memory write buffer is driven
to memory on the next memClkR. After the
write, the quadword pointer is reset to 0, and
the cache line pointer is incremented so that
the next WRxxx will drive the first sub-cache
line of the next cache line to memory.
Data from the memory write buffer is driven
to memory on the memClkR after the next
memClkR. After the write, the quadword
pointer is reset to 0, and the cache line pointer
is incremented so that the next WRxxx will
drive the first sub-cache line of the next line to
memory.

+·~ 1~·~:2.s ilory SI~::; Descriptions

Digital Confidential 2-23

2.2.5.1 memAdr<11 :0>

2.2.5.2 memRAS_l<8:0>

Signal Type: 21071-CA Output
=:=:=:=: : :;: :;: .:.
Signal Destination: Memory =-=:;:;=: ;:;:=-=:.: :.=.:/L,: : : -=/\t.==-·
Output Clock Edge: memClkR (lr.t~J'gra=mmi§.l•L.

memRAS_k8:0> is asserted on II).~m9.i~iit~-~dl~i-£&~:~~irisactions, and video
serial register loads to indicate ~b.ifoP.reji#.~~:J>f a valid row address on
memAdr<ll:O>. Each memRA,SJga:o>··=Sigpij)}~rresponds to one of the nine
banksets as determi~_ed by tQ~~)n@fu~ry addfei.i~]lecode logic. memRAS_k8:0>
is asserted on mem9tY\r.eads ifiq[)[-~§. _ only ifthe subbank number is zero, or
if subbanks for thaf:b:~hl~A;J..:r.~ disab~XB~SUBENA=O). On memory refresh
transactions, m~giRAS.J~!ffi~l%~~::.:~sseft~~fu·[~ilji}'=·
·-======: : :=·.·.·.·.:-:-:-:-:-:-:-:-:-:;:;::;::-:..
:=:==-=-· ==:===:===:==: : :,.
2.2.5.3 memRASB-1<8·~.':o=.=:\L_: _:_[_:.=\_:_:_:_:_:_: : : := =-·
·.·.·.·.·.·.·.·.·-:-:-:.:-:-:-:·::;:=:~

Signal Type: 2tQ7lM'OA Output<}>
Signal Destination]:,[:·mti:m9!Y ·
Output C.19.:@kH~gge:metij;Q~ (Programmable)

::~:SJfl~:..~1:i!:!~ t;.!:;;e;:~;,~s~~t~;:~~~ ;cept

the subbarilhiumbef is &.ne.~= If subbanks for that bank are disabled (Bx_

•· •
2254

;lir·s

;;J~!;!litf

memRASB_l line will assert only for refreshes.

•:'. ,;jj/j~~j[j\i:£9E~~:l!::~iR
.·.·.-.·.·.·.·.·.·.·.·

(Programmable)

·-:-:·:·::::;::::

.=<{]:=:/>
·=m~i)iCAS_k3:th~ signals are used during memory reads and writes. to indicate
tiif·It=>•·.
.,,J=::~'Qat a valid column address is on memAdr<ll:O>. During memory writes,
=:==:=t:.u::.m:=.:irn=m:=:::>t.=·:::1:fatiemCAS_k3:0> asserts if the respective memory longwords are being written.
·===:::+::::::::::rn\:1\%\:Pn memory reads, all memCAS_l bits are asserted. memCAS_k3:0> is also
====:::=@f:_fa\~~~r.ted during refreshes and video serial register loads.

2-24 Digital Confidential

2.2.5.5 memWE_l<1 :0>

·:·:::::::~:~:~:/::::::: ..

.·:::::;:;:::::::::::::;:;:::;:::::;:

Signal Type: 21071-CA Output
. :::::'.;::';\::::':'\,_,,,_,,,,';:::::':;::\,,,,,._
Signal Destination: Memory
.·. : : ;: :;: : : ·.' ::::Of\.-,:,·.....-t....
Output Clock Edge: memClkR (Programmab.J~).:J}l
·<\/1{\i>·

memWE_l< 1:0> signals are asserted on ~{PJ~Jnory'';H~ii.\~t@ni:;action t~· indicate
that valid write data is present on the rtiijijfb~t3.J>utptlts%:\m~mWE_k0> and
memWE_l< 1> are identical copies provided. tcf:\f,,i.Y.~~t.loadihg{\[. !\\_.:·:.::::>
<:\;{::;:;:;::::::::: ·.·.·

·-:·::::~rrr:~:~:~r·==-:·:·:·.--

2.2.5.6 memPDClk

·.:.:-:-:-:-;-;.

. ::::~:~:~:~:{{\~~\:::-.

·.·.:::::::::\:::::::::::::::=:::::

Signal Type: 21071-CA Output _.,.,:;:;:;:;:;:::;:;:;:;:;';'.;'}:Jt\::::,,.,._
··.··::':::::;····
Signal Destination: Presence Deti:¢t'. sliif\.::\B~~§,t.er
Output Clock Edge: clk2F _.,,::;::f?i:\:!\\\\L.
.. .,,,,\:?'\':::)(''\,.
memPDClk provides a clock at ~~pf.Jall.l::j,b.~. clkl &'~quency. This clock
is connected to the presence ~.!t~9t'''shift''ii~@M"t~,~ memPDLoad_l and the
sampling of memPDI;>In are Witfi.If(.e.,~pect t0"'''tldirnptock. The clock starts as soon
as reset 1 is deasserii.dhand dU~eont)nues after·::Kll data has been shifted into
the pres-;nce detececijhtr9l:$tatti'~\-~t~r.s
(CSRs) .
.
.;:;:::::::·-·.·-:-:-:-:;>.
···:::::.:.:.:.::::::::::::.:;::::::·:·.
2.2.5.7 memPDLoad_l _.J/::':':::::

signal ~:~i::::~:to1:kOA··aaii~t.·::':=::::::::::,:

=~t~:!:li:flliE~c~

fiiiiect

Shift Register

0 1
::e~~~till,f
4f
J:!'!~~:S~~r;;,:~
!::~J~~ti
~ !s~:rtec1,
at least
w1ll occur. This enables the use of either asynchronous
on~HnemEDPik

or synchro#.q#.§Jq@ijfog
S:bi.ft
registers.
..
..:::::::=::::::::::::::::::::::::::::·
-:=::::::;:;:;::::·

2.2.s.s m~.'1,n i11!\Jj,i(lif ;;A'!l\~?

,Jtl!~ Type·~"':':'~'f61'1·-CA Input
··:::::S:~IP.#.bS.Ource:

Presence Detect Shift Register
hiiJ~i~\\Cl!l~Jt Edge: clk2F

me~~BD~#%~ignal contains the data from the presence detect shift
/teltis1ter. The value of memPDDin is shifted into the 21071-CA chip presence
.,)Jt:ete~c:t registers one sys Clock after memPDClk deasserts (which is 3 sysClocks
<@';:-:_:;;::_:\··;,:·U::t/?iiii~~ftE~r memPDClk asserts). The data is loaded Most Significant Bit (MSB) first
the registers (a shift right).

Digital Confidential 2-25

2.2.6 Video Support Signal Descriptions
2.2.6.1 vFrame_I

Signal Type: 21071-CA Input
Signal Source: External logic
Input Clock Edge: Asynchronous

......

·.·.·.·.·.·.·.·-:·:::::-:-:;:-:·:

!8:::~:no~~;r~::-~:::e;o::e;~:~!!~lllts~~~~'L':d27o~1~~~
chip. A full serial register load to the video bankq~f:jfffl}µ~~ted at the video
display pointer address.
.. . .:::;:}} :::::::'>..
"":::/:\:;:·L.::::::'.::.

:~ :fo::.ei~i=~:s;~::~\t~~:l1!~-£;:::e~h~!:;o~~~~lk
.:r::!i:!:!:i'.[.i:::i;:::~·:;;:::\t......

before being used.

.. ,:::::.:: ·: : : : :

vFrame_l has a weak internal p@.J~p:"lb?~qppQ.r~. systems that do not use the

video support
2.2.6.2 vRefresh_I

functi~:ality Pf;·~!: th~'!(~l~fCA
. : ;: : : : ;: : : : .
"'.::::::::;:;:::::::·· ····:··... -.

chip.

":::::::::=::::::::::::::::;::::::..
·:::::;::=:::::::;:;:{{~:::\::..

Signal Typ~: 21071*=¢:4:\\~put ""::::::::::c·:;;::;;:\;t:. . ·

::~c~-~~fl~•~

Assertion of vRefr:~:~hdlii:i~jij;~~s th~>~:ddf~mented value of the video display
pointer to be latched illf&~b~::,:n:9:~o display pointer. A split serial register load
cycle to the vi,:9.~9:J?4:P:§..js reqii!§~d at the video display pointer address.
The vRefre.§JtllU~{li.}.jj~~?~:9ge ;~~:sitive and asynchronous with the 21071-CA
chip clock$~\%A$sert1~#fof:#R~fresh_l is detected and synchronized with memClk
before .~eirtg\i~M:~M\i!\t:·
. :'.'.'.>:':t:

~~to~~~f::vi~~~: ~!'iio!r~-~::;. that do not use the
.·:-::\:=\?~ff~f{:.

2~.~::B~~:::::::::mem'q~lm't':::::.
. :;:): }:)\": :·: ;: ·:· mlI\:::Sipil/f.MP.~n- 21071-CA Output

. ;!ii ii

\) l) ~=t~~~:~: ~:':i~iR

'>m.\:\\_:.\i\\·\·\. \\i:_\\::=::·· <:i···:Wh~ memDTOE_l signal has two functions and is intended to be used
::: '<tm\{\j:\.:I\m.::rn:::.::%nly by the single video bank. During random access reads and writes,
"'::<\\]::(::·:{m~mDTOE_l is held deasserted before asserting memRAS_l. For random
···::::::+:Hir~id$,. memDTOE_l is asserted with the first column address. During a serial
"':regj:Ster load, memDTOE_l is asserted with the row address. This signal is

2-26 Digital Confidential

2.2.6.4 memDSF

Signal Type: 21071-CA Output
Signal Destination: Memory
Output Clock Edge: memClkR

:-:·:·:·:·:·:-:-:·.·.·:····:::·:·.

··:::;.;-::;::::;:;:::~:~:~:~:~=~=ji~~==::~::·.

·-:-::~:~\:::::::·:·'.·'.·:::·:
·.·.·.·.·:.·.··:·:;:-:-·-··:·.

The memDSF signal is used at memRAS_ks;<ij$.~¢.df9p by th~:@·ingle video
bank to choose between full and split seri~J.regisU¥::J9@l~b}llemDSF is driven
with the row address in order to set upJ#.~ID~-k8=;t()i{::m~mRASB_k8>.

2.2.7 Miscellaneous Signal Descripti~ili+ .)i ;;: ;ii ff , . <r
=.=:.=:.:.: .·.: _·_: .:;:.;,.==_:=_:·===:=-:;:::;:;:;:;::-.·
:·.t>==·

2.2.7.1 wldeMem

Signal Type: 21071-CA In.pq~:::v=-=-·· . :\\{\\ :=: ='": -: : : : : :.
Input Clock Edge: Stat.1.~-=~. . ·_·:=_: .:_:_i_·:.: .: .: _: .: .: .: =: _:.
·=::::::=ttt?tt==
·.;.;.:-:-:.:-:-:-:-:;:-:

!!'~c:~:~:~:~fli;:~~?1!l~~,~id81::~~~:~;~-!~:~!!!~t
t::::~!eW:~~~I'i '!:!11Ji'fi;;:;~1f!~;;;i~~Aw;~:)~m is tied iow to
wideMem has ~==:w;~~~::j~q,~~;rnai·<~dll:i!~~Wn and a Schmitt trigger input.
2.2.7.2 clk1x2

.. . . . . . . .. . .. . . . . .

elk lx2 is a clg~l~Jjijpµ~,=)vhrnh.:=:~qpplies a clock at twice the frequency of the
~!~eC::~!~1~:;mj!futl
with a
15
a 50

sigiiill,

::::;:::::::::::::::.

2~2.7.3

clk2ref

::/::}::::::-·

\\%:> =======: : : =·==

minimum period of ns, and

::::\}~{::

=:=:=:=:=

clk2ref\:~~ka -~ili~li!~µ.pµt•-~hich is low when the assertion of clklx2 corresponds

to ~lM~:·•~sertioii>Hr::$y$¢1kOutl. The received signal must be set up to the
as$.i:f:tioh:-of clklx2 .
.2~~"~4i=i=(tt.setJ<t[:[.·:·=::[:[:·::[j:f\=::::.

·=-: : : : ///.. ·\=:{=/1$.~~rtion"'.'Slt~S.it:J sets all internal logic and state machines to their initialized
·:::~ti.\es. Duririg)feset, the memory data bus is driven, and the sysBus data and

<.Y.·[:=··=:=:·.·=;:='.=.=.':.·:=i:=·= :·•':=;:•.:= =.:.•:.=:.•:=..•.:=.

_)§ig}buses are tristated. All signals which are sent to the DECchip 21064

§)::. ::::H'.m-.P.f.ocessor are guaranteed to be tristated or held low, so as to prevent more then

<:•;:::} ><@l:H\/'}3.0 volts from entering the DECchip 21064 micro processor during reset.

Digital Confidential 2-27

.·: :/\ \ l[\ [\·l:-·=1~l1·l·.\!.!:· .i: : : ; ; ;: : : -

·:·.·:·::::::::=···

·2.2.7.5

•:s::

~\~ !1C~f
1

of testMode places the chip into a mode for

...

......·.·.·.-.·.·.·.·.·

!lll!'.JF

:0:~I i~~::::;:r~~=~d during chip testing, and,,jfi'.llif1.i\,llM'i~:frig
testMode has a weak i~temal pull down @..Q a Sch1·1~-~er inp-~f::::J:::::
:·:::::;::::;::::=:::-:

··-:;:···:::;:::;:;:;:;:;:;:;:;:::;::.:·.

.·:·: : : ..;: -:-: · .{~:)'.::;..
··::;:\\'{]tl>::::::
..
·.·.·.-.·.·.·.·.·.·.·.···· ..
2.2.7.6 Scan Enable
Assertion of scanEnable places all internal tt6j$.:::·~\tj)eir ·;~i~[j:j$t~te.
scanEnable is only intended to be used during CliiiUt~i.t.ing, and must be
tied iow during norma1 system operatio:w:ttt=\:\+>.
··:::::::<L·;tiL:::::::::-

scanEnable has a weak internal pull ~"ff~l~li~!!1itf 'filigger input.
2.2.7.7 trlstate_I
.·.· .· .·.· ._..-_..-_.:.:·_:·_.·.:·_.:·'.·':·:.::_=_.=. = .: =_.: _.:..
·:::::\:ttt
·:-:·::;:::::::;:;::··
Assertion of this signal tristates J~)~::\Q.ii;~pgt\mi..d bidire:ctional drivers. tristate_!
is intended for use only during:£q~jftestihg:]~il.9:::p_ower-up.

tristate_! has a weak.dµtematl-:6.itJ~pJ.md ~:::$i&\i'f:hltt trigger input.

-:/f{~[f/:·

··:·:::{~~~~~~:~}~}~//:~:~:::. . ·.

·.·

2.2.7.8 pTestout
··::::::<:=:?. :?::=:\::..
·-::::::::=tt:=::?t/'::::-:The pTestout sigpal con~l:::tb~ . . outp&t:i:j!i.hi the Parametric NAND tree, as
required for t~~p:qg~:::J'he t:Hs~ij'.~g\ajgnal . must be asserted for pTestout to be
valid. pTestoutiM#i.ti~ged
for::US.~~##!Jy,during
chip or module testing.
·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.
··-:-:::·:::;:::::::-:-:-:-·····

2.3 DECchip 21071-CA::::l\l!~!IJt~.s;i'g:nment

Section 2.3.2 and Sect.jpµ:"::g~~~~dj§t th~:::~~ij:Mssignments for the DECchip 21071-CA.

2.3.1 Signal TYP:!i:j\:t::::=::::::::::::::::::-:-:;·:--:. .·. :-:-:-:-:

···.··.··

Table 2-l~:[')ij~~crjp~$Yn~p~l)ip 21071-CA signal types referred to in this
section...
··=·?:{/:\:·
..: : : : : : : : :.: : : : : :-:.: ·:·=·=-::..
··::::::::::::;:;:::::::::::::;:;:::::·
.::~~ttff

T~-~r; ~:lllllf~1-CA Signal Types

I>:Ht?
.:::rn.:\·V.tf"

·::::::~:~:~:::~:~\~~~~~~~~~~~~:~~~~~::~~:~:~:~:~:~:~:::::~:=:

Power
Bidirectional

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

··::::;::::::::::::::::::::::::::~:::::::::::·

Fi~~~\l!g.f.~}~p-~ws the DECchip 21071-CA pinout locations.

2-28 Digital Confidential

Figure 2-1

:::::::.··
outVSS
oulVDO
memRASB_l<O>
memRASB_l<1>
memRASB_l<2>
memRASB_l<3>
memRASB_l<4>
memRASB_l<5>
memRASB 1<6>
memRASB-1<7>
memRASB=l<8>
outVSS
memCAS_l<O>
memCAS_l<1>
memCAS_l<2>
outVSS
outVOD
memCAS_l<3>
oulVOO
sysDalaWEEn
sysOalaL.ongWE
oulVSS
memRAS_l<O>
memRAS_lc1>
memRAS_l<2>
oulVSS
outVDO
memRAS_l<3>
memRAS_l«il>
memRAS_l<5>
memRAS_l<6>
memRAS_l<7>
memRAS_l<8>
memWE_lcO>
memWE_lcb
memAdrcO>
outVSS
outVDD
memAdr<1>
memAdr<2>
memAdr<3>
memAdr<4>
memAdr<5>
memAdr<6>
memAdr<7>
memAdrc8>
memAdr<9>
memAdr<10>
memAdr<11>
oulVSS
inpVQD.
inp~:::

:::~:r:::::::::·

155

5
150
10
145
15
140

135

130

125

120

115

110

105

inpVSS
inpVOD
lagAdr<22>
tagAdr<21>
lagAdr<20>
lagAdr<19>
tagAdr<18>
tagAdr<17>
tagAdrP
tagCUP
tagCtlD
tagCllV
sysAdr<33>
sysAdrc32>
sysAdrc31>
outVSS
sysAdrc30>
sy1Adrc29>
sy1Adrc28>
sysAdr<'Zl>
inpVSS
clk1x2
teslMode
trlllale_I
clk2rel
outVDD
scan Enable
sysAdrc26>
sysAdr<25>
sysAdrc24>
sysAdr<23>
sysAdrc22>
sysAdrc21>
sysAdrc20>
sysAdrc19>
sysAdr<18>
oulVSS
sysAdr<17>
sysAdrc16>
sysAdr<15>
sysAdr<14>
sysAdrc13>
sysAdr<12>
sysAdr<11>
sysAdr<10>
sysAdrc9>
sysAdr<8>
sysAdr<7>
sysAdrc6>
sysAdr<5>
oulVOD
oulVSS

.·:··

U.03"'-Tll

··<·• ;~~-3.2 dlfhhlp 210;1-CA Alphabetical Pin Assignment Lls1

··<=:r::::::::t<:tt=:=:./{:. '.::=[T~ble 2-13 lists the DECchip 21071-CA pins in alphabetical order.

Digital Confidential 2-29

... :;:::;:;:;:;:;::·.·.

_::::::::::=:·:·:··

~=.:~-~i.~:.:_~:.:_:._:_: _:.:~:~: .

·:}:~{:}~:}'

.::)):;:::·.:·:-:-::;:;:;:::::;:::::::-:
.·:·:·'.·'.·'.·:·:··

.;:;::::;:;:::::··
.::::;:;:;:::;:-:·

Asslg~mimt~: 11!!1111 ;;t!!';;i
1

Table 2-13 DECchip 21071-CA Alphabetlcal Pin
Pin
Number

Pin Name•

Type

Pin Name

cl.klx2
135
clk2ref
132
cpuCAck<O>
180
cpuCAck<l>
181
cpuCAck<2>
182
cpuCReq<O>
184
cpuCReq<l>
185
cpuCReq<2>
186
cpuCWMask<O>
168
cpuCWMask<l>
169
170
cpuCWMask<2>
cpuCWMask<3>
171
173
cpuCWMask<4>
cpuCWMask<G>
174
cpuCWMask<6>
cpuCWMask<7>
cpuDinvReq
·::::\( l~R~quest<O>
:.::'i~ftE,quest<l>
cpuDRack<O>
cpuDRack<l>
memAdr<O>
·.:-::::}\:}:}}}\c- memAdr<l>
cpuDRack<2>
cpuDWSel<l>
memAdr<2>
cpuHold.Ack
memAdr<3>
cpuHoldReq
memAdr<4>
drvMemData. :/:/)
memAdr<5>
.· :::::::::::-:-:.:· 7"4""· ;: .: ,·'_,':.: : ·:.: :·:.: :·:.: :.:_:':'_:'.·:.: :·
drvs ysCSR ifrt>::>
memAdr<6>
0
····.··:.Q
drvSysData(//)
'?.~{}:/
memAdr<'7>
·:·:·:-:·:-:-:-:-:-:

*nc-D~J~ot ~!#./~se pil),~:l~#°board.
}~{{ :-:·.·.

·-:·:·:·:-:·:·:·:::::.:.:-:·:-:-:-:-.-.·.-.·:-:-:):~:~::::::::::::=·

:::::.. :-:-:-:-:-:-:

2-30 Digital Confidential

::::/::::::::::}'.;::::;:;:

p
p
p
p
p
p
p

194
195
36

39
40
41
42
43
44

0
0
I
I
I
0
0
I
I
0
0
0
0
0
0
0
0

Pin Name

Pin
Number

Type

memAdr<8>
46
memAdr<9>
47
mem.Adr<lO>
48
memAdr<ll>
49
memCAS_l<O>
13
memCAS_l<l>
14
memCAS_l<2>
15
memCAS_l<3>
18
memCmd<l>
65
memCmd<2>
66
memCmd<3>
67
mem.DSF
56
mem.DTOEJ
55
mem.PDClk
58
mem.PDDin
57
mem.PDLoad_l
59
memRASBJ<O>
3
memRASB_l<l>
4
memRASB_l<2> -:·..5
memRASB_l<3> . ){ij
memRASB_l<4> ·:;::::;:::q ···· ·.·
memRASB_l<o>
·a ::O:I::::::::'r.U:::::::,..
memRASB_l<6>
9
· :-:-:·:-:-:-·-:-:-:·:·
memRASB_l<'7>
10
memRASB_l<8> ::::<:11//\:=:-.·.
memRAS_l<O;f/ it/@£::::-:::.@J):-·
.:-:-:-:-:-:-:-:-·

-:;:::;::::;::::::··

Pin Name

0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0

~:ff :::::i!!\i!!\:[:> ·::::::::::~!tll~t:+:·.
O} ·· ·· · :·:· ·

outVddt:::>
0 ::::;:::::: '.:·<;/:: :::;::: : ... outVdd ·.·
·-:-:::_:::;::•.·:· :.::·.•:.::_:-:·:-:-:-:·.
..

l\~~Vdd
·~utVdd

?<:{:··:::·:-::-::.::·::}:;:::::... outVdd
outVdd
outVdd
outVss
outVss
outVss

78
188
27
79
183
17
38
54
158
106
131
2

1
37
120

p
p
p

p
p
p
p

p
p

p
p
p
p

.-:-:-:-:-:
.:.:-:-:-:-:-:

Digital Confidential 2-31

Pin
Number

Pin Name

outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
pTestout
reset_!
scanEnable
subCmdA<O>
subCmdA<l>
subCmdB<O>

16
68
22
50
12
172
105
89
157
141
26

193
53
203
206

130

62.:/U : : : : :

Type

Pin Name

P
P

sysAdr<t9>
::\1:\\!:\\f/'i22:<{il::-il:_._!_1_!:j::;:::_.':;:i_:··::,:::_::_:_::!·::_·.:·:_·::_::_··:::·::_I'_1::·:::_:'::_::_..·:'.:':'_::.:.·.·
sysAdr<20>./\i(J 123

P
P
P

. ::fimif\t:>

sysA~!1~H\ :-··

'\]\::n ::·::::1:::11•;;: · .· .· ·

~!!

~~~

~
I

'\'\(,~11::

~[~

0
0

.:_\::_',.:!,._!,·_:: .. :_\

:s; 1t11,111r1~i!l' ) 11;, g

2-32 Digital Confidential

I
I
I

108

n:t"'::::-·-: i\Ji:J>>P.

····.·::::::::;:::::;:·:·:=·:·

:=srr

\~/

O ·>\:\{::C:://:\:: sysAdr<6>

sysAdr<l2>
114
\J:t:ot::::::::•.
sysAdr<l3>
.:-::-:-:\Um/\:::. ··:: Q:}:t\>:
sysAdr<14>
/iiij:t> ?/
0--::,::, ,.,
111%1?'':sysAdr<is> .......·.·.
.·.·.·.-.·.·.·.·.· .:-::-::::·: o

·:;:;:::::::::::;:;.:-:·'.·:·:-:·:-:-:·:·:· :::::::::::::;:::::·
......·.:-:-:.:.:.'
..

i2~ft[){ .·.·

sysAck<2i.)?::: :\:'.:::\.... 128 ·:·:::::;::::--

-~:i:. 1 1:1 1 : : : 1::;\::.

. ~o

:::~:~:~on :·:::\~~i\H>:::::.

···sy~~!~~

j , 1 1 1(1i;;;:l)!!'tl:~

63..::::::::::t

sysAdr<lO>
sysAdr<ll>

;1::%!'l!ff·-::::::4:26:/:::=:::·
;l'.1;,

sysCmd<O>
sysCmd<l>
sysCmd<2>
sysDataAHEn
sysDataALEn
sysDataLongWE
sysDataOEEn
sysDataWEEn
sysData<O>
sysData<l>

70
71
80
77
21
84
20

102
101

0
0
0
0

0
0
1/0
1/0

Pin Name

sysData<lO>
sysData<ll>
sysData<12>
sysData<13>
sysData<l4>
sysData<lfb
sysData<2>
sysData<3>
sysData<4>
sysData<o>
sysData<6>
sysData<'7>
sysData<8>
sysData<9>
sysDOE
sysEarlyOEEn
syslORead
sysReadOW
sysTagOEEn
sysTagWE
tagAdrP
tagAdr<17>

Pin
Number

Type

Pin Name

92
91
90
88
87
86

100
99
98
97
96
95
94
93
85
83
76. : ::{:~)\:;.

Digital Confidential 2-33

2.3.3 DECchip 21071-CA Numerical Pin Assignment ~l§t;. .

Table 2-14 lists the DECchip 21071-CA pins in numetj~i.}l~l~tlit&t:-.·.
Table 2-14 DECchlp 21071-CA Numerical Pin

A~= ~~!fllJ!ti;!!\!>
...

":·:-:-:-:·:···········:·:······

Pin Name•

outVss
outVdd
mem.RASB_l<O>
mem.RASB_l<l>
mem.RASB_l<2>
mem.RASB_l<3>
mem.RASB_l<4>
mem.RASB_l<5>
mem.RASB_l<6>
mem.RASB_l<7>
mem.RASB_l<8>

Pin
Number

Type

outv;;\U?t:::=::::
2~<:mI:]>'
outVdd ·:·::::; :)fj:,)H:f:[j):::::,.,,. 27

1
2
3

1... ;, 111111;;:::;:

6
7
8

~ilk ;

Ot{// !~ilt: .·.·.·.

''\}{t']).G..•Vdd

memCAS_l<O>
memCAS_l<l>
memCAS_l<2>

outVss
outVdd
memCAS_l<3>

outVdd
sysDataWEE11: :I:rn::
sysDataL0 ngWE/':::: ''''21/\%/
outVss
{··:,::.:\[:::,.:r· 22\\\:?

'·:~=I:.::.
../)\:-:···

me4J<2~::=::r::i[~:;\i:g~/\::·=·:,.::,:.:::::····

.'?Jij,~mAdr<l>
meDIA.dr<2>
:,:_,::::;,::::;:::::::;:;::::,:::. meDIA.dr<3>
meDIA.dr<4>
meDIA.dr<5>
meDIA.dr<6>
meDIA.dr<7>
meDIA.dr<8>
meDIA.dr<9>
memA.dr<lO>
meDIA.dr<ll>

·~~fo.9t
connect thesE{pins on board.
·=···:-:-:-:-:-·-·.·.·.·.·.·.·.·.·.·.·.

2-34 Digital Confidential

mem.Adi<O>

P ..,.,,t\?ilif)~µtvss

outVss

mem.RAS_l<O)d:\: )~?
memRAS l<i:i{::;:::=:: \\\24

meii!f§*l>

outVss

~
35
36
37
38
39
40

41
42
43

44
45
46
47
48
49
50

p
p
0
0
0
0
0
0
0
0
0
0

p
0
0
0
0
0
0
0
0
0
0
0

Pin Name•

Pin
Number

Type

"\)\}?::·. . ::):?~:~:::;::·
··==1¥pj:iiicr·

Pin Name
·:·.-.·.··:·:·:·:·:·:·:·······:-:::::;:·:·····: ·<·.·.·.·.·.

inpVdd
51
:
outVdd
:;\: =: =:=:===· 79 ==\{j\f:=~i1l:rn1i·1ii:.:i~)==·
inpVss
52
outVss
53
p
qf
outVdd
54
p
.,J)'.f~gOEEn ·=·====+:::j]{}~~\
0
memDTOE_l
55
. . =_.·.;E. .E_.. :._:.
_• .
memDSF
56
·:;:;:::::::::;.::memPDDin
57
0
sysooE==:\/:t ?:::;::;==·=·· 85
O
memPDClk
58
0
Sf.E.J.P.ata<l59 ::\)\::::::\§6
1/0
0
.,);Y:~Pi.!~,.::14> :-::::\((/87'=
1/0
memPDLoad_l
59
60
0
subCmdB<O>
subCmdB<l>
61
subCmdA<O>
62
0
.:::::::=:tJUJ•ysDatad~/:
90
1/0
0
·::):::::::· @:::::::•'f•P.ata<lt>·-=··=:=-:-::=··
91
1/0
subCmdA<l>
63
{f : : : :-:·:·: ·.·.·.·.:.·-·.·.·.-. .· .·.·.·.
drvMemData
64
memCm.d<l>
65
.o>=.=·>
&\:\::~:':::@:\:}:~
~-~
94
memCmd<2>
66
0 =: : : : :========== ==+:;:::::::=:;. . ·=·sysData:C7>
95
1/0
memCmd<3>
6 {:\\\l:::=i :i::::::::·
outVss
68'\t/
·::==:=::::::::::1::!11:11t::::
sysCmd<O>
sysCmd<l>
sy~Data<4>
98
1/0
sysCmd<2>
sysData<3>
99
1/0
sysReadOW
sysData<2>
100
1/0
drvSysData
sysData<l>
101
1/0
drvSysCSR
74
sysData<O>
102
1/0
subCmdCommon=/ )7~k:\=:::
inpVdd
103
P
inpVss
104
P
syslORead . f::l\.:t:::: :Hfo?f\')/
sysDataALE#f{/
7.£Qi:f==·
0
outVss
105
P
.·.·.·.·.·.·.·.·.
:=:::::::::::::::
<·:-:;: ·'.·>:·:·
.:/t.&t=..
.....
nc
outVdd
106
P
~{I}//

:;;.~il!ili1>~

.·:;~la.1_,_=_.Y_:_:o_:_.'.o_.·.=_.·_u_

·-= :=: : t~4:!:!:>: ,·=: : : : := ·

lii!C!fq~

<!::

~-·=·=·=· · ·-·.·.·.· =·=· · =·= =t?s; :Y ;:;: s•· ·~·;.=,=·;=.:=· ·_;:.:=_:_= _.=·'.= =._-=_,_:=·,:=· ·.:=_=.= · _.=·_.=_:8~.-=·.:

~l/gO

·:·:::-:-·.·.·.····
··::::::}~}:}~::··

Digital Confidential 2-35

·.·

.._}~:.~:.·~:.~_=.·~_:_:· ··:::: . . . . :·: .....

:::/\/jf~t~~r=·

Pin
Number

Pin Name•

sysAdr<5>
sysAdr<6>
sysAdr<'7>
sysAdr<8>
sysAdr<9>
sysAdr<lO>
sysAdr<ll>
sysAdr<12>
sysAdr<l3>
sysAdr<l4>
sysAdr<l5>
sysAdr<l6>
sysAdr<l7>
outVss
sysAdr<l8>
sysAdr<l9>
sysAdr<20>
sysAdr<21>
sysAdr<22>
sysAdr<23>

107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122 ..:=::=::::.
12_~'ill>==·
124·=::::::::;r
125

./tt~g~.

:~:!:::::

=====:::::::i;!.:::::>>>
129
130

Type

Pin Name

$1~li1llli:':~'\li.;i,l~l1;]l~i;1r

:::ff~;u> ····::=::=\~{!:\l:!!j~~:::Ht:::

:~:~•~:::.::::::::\::::::::... ~::+_::_:::./:.··

t,lf..~V .. =.:::::tYAtt!%!45

I/O

~ y;li!!!lt1~1';,:gE~

~ =_:_::_:·_;:=_:_·=_; ><.:!!IE;!:: .........· ~:~
~iirJI!,.
.
~::
.
154
:::::!_:::!-_::_:·:':.::.·:}:

<w11[~I?:

\'?>.:i·:(x::1:::=~: .

sysAdr<26>
scanEnable
outVdd

}}_L\ fai\::

clk2Ref

...

tristate_l

:{:!!!;'/?.

::de

-=::i:i)!\\. iliff

·::<t<:<t>

·=·::::{,fo }:'}>··

iaf.f\ ·: : :.:.
I .· .
~~-!ii!:.:/::.. :-:· .. _. I
]!j:j\!\\·jjjjji!:

-: ·:-: . ..<,::::E:Ela36.. . ·.·.·=-::::::{}}} p

ms·y~~--.-~.-.
~. : :_'_:_: _·_~'._:!_:_:!: .: _'.-:_,~.:-_=.: :_-:>:/
aa~~

................................. .

.·:.:::::::::.:-::::::·:·:::::

·-.·.·-:-:-:-:=:-·-·.··

·-.··::r:::::i;i!t}Itt::r·· r

·~-J!\il!t_~nnect these pins on board.

;}\/:-:,..

.-::(}~: ·.·.·.· : -: :·.'

-:-:-:-:-:-:-:-:·:<·:

::::::::.::::::::::::1:::1:··=·%:::

...

outVdd
tagAdr<23>
tagAdr<24>
tagAdr<25>
tagAdr<26>
tagAdr<27>
tagAdr<28>
tagAdr<29>
tagAdr<30>
tagAdr<31>
cpuCWMask<l>

158
159
160
161
162
163
164
165
166
167
168

I/O
I/O
I/O
I/O
I/O
110
110
110
110
I

-----....--------------------------·.·\~}fit~\{?:::::...

.·:-:-:.:-: ...·.·.··:·'.·'.·'.·'.::::::-:-: :{::·.

_:::::;:-:-:.·-:·

-:-:-:-:-:-:-:·:-:-:-:-·
.·>:-:-:-:-:-:·:·:·:-:.·
.-:-:-:-:-:.:-:-:-:-:-:-·

!:9

:..
.· ....ta-..t...1-~>
I ·=::::t::::_.::_.!:.:::_.'.:_.'.....-:-:::::;'.:'.;'.:-·
~-"'"

~~
~
IfO

:-:-:-:-:.:-:
-:.:-:-:-:-:-:

·:-:-:-:-:-:-:-:-:-:·:··-·.·.·.
·-::::::::::;::::·:;:;:·:-:-·

I!~ i

; II !; ~Ii Ill;. >···

. ::\'.{{:~/:?}}}:::

2-36 Digital Confidential

Pin*

Type

Pin No.

cpuCWMask<l>
169
170
cpuCWMask<2>
cpuCWMask<3>
171
172
outVss
173
cpuCWMask<4>
174
cpuCWMask<5>
175
cpuCWMask<6>
176
cpuCWMask<7>
cpuDlnvReq
177
cpuHold.Req
178
cpuHoldAck
179
180
cpuCAck<O>
181
cpuCAck<l>
cpuCAck<2>
182
outVdd
183
cpuCReq<O>
184
cpuCReq<l>
185 ..:::·.·.
cpuCReq<2>
1sijiiji:ji::::[::r·
cpuDWSel<l>
1sr:::;::::=NC
. ::-J88
cpuDRAck<O> .J::\:ft'89:.

:::==: ·w~lli;. . .

ioGrant
192 ·:-<<\{\/\O..
outVss
193
.<<?/f.\p) ..;..
ioRequest<O> ...:::::::rd~4t\
:¥12/?>
ioRequest<l~f ::::·:-:-:-·fa&?:::::.·
I

·: :

::::::::::::::::::-·

Filf,jiil'-~··· shows packaging dimension information.
··:: ~-\}rf=\t::;:;.;.·.·

·:·:·:::·:::::::::::::::::::::::::.··

·:::;:;:;:;=-;.)~:}:::::·: ...

Digital Confidential 2-37

Figure 2-2

DIM 1---y--~~.__T-""--.;,"f:::::::::

30.50.< =~QWt: ]~~01

..Ja:.:.. 21.90 ~aa~t

1.211

mo.S.$:: 1.106

\~:y M:~~o. 3o.tt' m~~i: :t~J1
\Q\ ~=MM ~8.1 o 1:ooe.:: :JdQ~t :::.
. G
H
J

:o~?~::: {~p3 0.009. :'Q;~r$: :/
-~®.J:i$.P
0.0197 asd'

9Aff

)0.62
K dM~t : 3.85
0.23
{~:} :JM3
:::::~:::: j)~25
0.35
/fi}: :)~$~$: REF
S : \:?~~$.F{af:.

0.018 0.024
0.1 36 0.152
0.005 0.009
0.010 0.012
1.004 REF
1.004 REF

2-38 Digital Confidential

LJ-03666-TIO

DECchip 21071-CA Aroli\l~~a·r~ili~.erview
<::::::::;::\:
....:-:.:·:·: :::::::::::::::::::::::..:;.
-:-:::::::·>.·

This chapter describes the architectur~:::~·\t.b.~@P:~Cchifi2\}Q7l-CA. The

~~7i~~~l~,{'. :~~~:~ ~~!1:r~~:o::i~ ~l~~~-~~m;!Ihcf:C~~df:c~:ns.
21071-BA chip. Figure 3-1 show,::~~:::g~llh4.iagratif:&r\:~ne 21071-CA chip .
.:::::::;:;:;:;:;:;:: ::::::::~{:~{:'.:~/~(~~::::

::::·\~/::::·~·

Figure 3-1 21071·CA Block Dlagram_.J:~:i:):ji~~ 0

:t(?t?M~~"s

;}'.{{::-.

·····•t\\.) :::::=::·
··:···:·::'.:'.'.;~;~;~~·:::

sysTag <31:17>

memAdr <11:0>

sysAdr <33:5>

memRasl ,memCasl, memWel
sys8us Control
82 Cache Contro_I

syJ$.W.d\

" " - - - - -..•.-....... 02 c~~~c·~;;;.._-.....;;;;;;; ;;;;.;-..-------1~
Datapath Contr~{ (}~ontr6f/f

1-_.;..--.;;;;··;;;;a·· •.•. ·.·.

·.·.·.·

---

;:;:.-.
.•...;;...-....ir·•::::::•:•
_.;)}}{~}ff);.

U-03351-TIO

:::{:}::: .·.·...

.·.··:·:·:·:-.

.::a:~:1,:::·:1::·1v§.~us<l:[ll@.r:fpce Architecture

.,):!!!ll-i!li!/t•· : ·::iiij:: CPU, 2'io7i:~DA chip, cache, and 21071-CA chip communicate with each
. J~~ber via the sysBus. The sysBus is essentially the processor pinbus with

.............

. < ::.::-:-;-:· )\: . :::-:-.·.::l!d.ditional signals for DMA transaction control, arbitration, and cache control.
··%.:..-:·. :::···The sysBus interface contains:
·· .. ::':=::: •.

:).@{.·.·~ :::n·~r.sBus arbiter
····:::::::;::1 H}Bcache controller

Digital Confidential 3-1

3.1.1

•

Write buffer address and control ·

•

Read/merge buffer control

S~B~:k;:i:;:tion

.·:·>t::Ii:t~):::::
.. ·
·:-:-:.:-;.;.······
::::::::::;:;:::::::·:····

.·:-:-:·::::::::'.:'.:::;.

ill~1r11;{)t; Q\))-i'i,\i!!':;'

The 21071-CA chip arbitrates between tti,!!!~c:etL~nd 2'fo't::lf.JJ)!AJ:.hip, which
requests use of the sysBus and the Bcache wfi:¢.)){th~Y have<~;i{\tf~saction to
perform. The CPU node has default ownership:'httjij~::::fl':~Bus '"sh" that it can
access the Bcache whenever the 21071-Df\J;MP is ri6t,:j~~'.Q:t§ting the bus.

::::Yftt ?m ~/\~~-·..

·-:-:-:-:-:·:·:-:.:·

3.1.1.1 Arbitration CSRs
. . .. ........:.:.: :.
The arbitration policy of the 21071-Ci.\l)i¢,hip . ~iffii:lli:li,r9grammed by setting up
the DMA_ARB CSR field to select:)\i/:bith.~r the CPUtmFthe 21071-DA chip has
highest priority. There are three:::pg~iib.l.!::i~eAP.ty encodings:
:·:::::::::::::;: ::::::::::;:::::-.
• CPU priority:
.:::::::::;::::=:::::::::
.. -:.:......::""::.::::"

- ~~P\1;~s9flr~~J!ll11~~~~6:is1y requesting the sysBus,

•

DMA prio.n
._. :·.:.~.·.'-~.._:_· .

_:.=.....

•

. .:;//::::::···· · : :. .·.:-:·.
-:-:·:·:·:::::::::::::::::::::::·:..

····=:::::::::::::\~~:::::::::::;::<·'.·.

.··::::::)\i:i:/j{~}~>-:·:::::::::-:·:"

DMA rn:tmV::¢.~{pporit)>'6#.¢,f:=:'iht~tCPU, and the bus is released to the
cache on :01\M.Mi#i~h~.
miss:M~:~:::l91Fnoncacheable DMA transactions .
.............. ....

DMA Strong pri~rlt~t·::::·.f}:::,:;.

DMl\.:j~::·lti#:/pr:jo~~j,ff~~if:: the CPU and, if another ioRequest<l:O> is
~~dll~~:~f~f~;Jli:i:!ts~~~~~~-to the cache on DMA cache misses, or
····-.;.····:·.

3.1.1.2

.·.·.·.·.·.·.·.·.
.·.·.·.·.·.·.·.·.·

······.·.·
·.·.:-:-:·:·:·:··

DECc~:!f:l::~.1·'0.i·t~lj:'.:~~Mll~

The.. 2:1171-CA\affijtijf:ijiohitors requests for the sysBus by decoding the
cpµ{J;R~g<2:0> arid::"i&Request<l:O> fields. cpuCReq<2:0> is not a bus request,
it"is:Wi.!¥&~l~. command indicating that the C?U has started a transaction on the
:-:-:·: 'mli\!}\fY.sifo'.i~l\!1::::[\\tJ:t::::.. .
:i:i=:i:.·:::. "·::.,.::;::::~l\:::::m~m the":2'1Qz~:WCA arbiter detects the assertion of ioRequest< 1:0>, and DMA
]~iji~\::won arbittation, it makes a request to the CPU for control of the Bcache
); !)\)!!. ) (Pi\)li.sserting cpuHoldReq to the CPU.
}f,rhe 21071-DA chip can make three types of requests for the sysBus:

3-2 Digital Confidential

::~.:·:·.:~:'.'.:.:~: ·:~:· ·:~·1: 1:·:·:1.: Jtt:\::;.

..:·.·.:.·:.'·.:.'·.:·..:·.'.: : .'.·':.·: . .
::
:.:. . .

..
·-:~:~:~:~:~:~:~:~:~:~:~:~:~:~::::::
..

::::::::;:;::::\::=::;:;:::::::::;:;::::.;.

(:}}}
+:.::.:rn:/ ··::;:::;::::;::;:;:;:/{\ .·.·
:~~i.:I~?fi\.
<::~/~~;~;~;~~~;~~~;)::::
.::::::::::::::::·

This request is used if the 21071-DA chip wants to do .m:ulti;l~ tf~$a~tiijij~
without interruption from the CPU. When the 2101:1±1.#.l!#hiP alf~~IY:I:::::Hlt:
has a DMA transaction in progress, the assertion rit1::~Miq~faf~qµ~sfWi11.
override programmed priority. If the 21071-DA :~b.1pfdoes ii@H@lf~~Q,y have
a transaction is progress, the assertion of atow!~:\fiqµest is eqtii\t#'ent to
sending a plain DMA request.
.·:-:. ·. ····:::::n:::t:·i:!.!:ij:·:·j.i.:It>
·.·.·
:::\\

. ·:;;~;~;;::::(
....·.
·:·:·:-:-:-:-:-:-:·:<·>:···

··.:-:-:-:·:·:·:-:-:-:·:_.:::::

• Preempt Request

.:::::>:::::

.·:·

This request should be us~gJ~j::::t~: .:~iQ..l·ifDf\.chip for deadlock prevention.
A preempt reque~t cause~tm!WW.biter td::::f~qti,~st the CPU to suspend a
transaction in P:t9kress. If::tij~::::;tQ7..1-DA chip must do multiple DMA
transactions fo:Fd~adJ.~~ prevenf..i##.~Mt:.. must keep preempt request or
atomic asserj;ed uiitif::il.l::s~~-dlockMt:gmisactions have completed.
When the .:g\~p7:'lhPA chi~:i:¢lj~ijg~,~ ioR~~uest< 1:0> from preempt to idle or
plain DMA.Hi(iµi~$.tt#1e arhi~r6vi:Rallow the suspended CPU transaction
to resume.
··. ·...·.··.··..
·.·...·...... ·
·.:-:-:·>:·:·:-:-:.:-:-:.;.:-:.:-:-.·.

·.·.·

A preempt r~qll.est . rii:m~~j!i~~:µ§ed only on CPU transactions addressed to
the 2107!d?~:[\yJ.jjp:J/0 t~la~fflJO writes, fetch, fetchM to 21071-DA space,
and bar:mir~y::p.r~~ifpt::_musFhot be asserted when the sysBus is idle or on
anytr@!~'-cti~µ!~:::pbtJ;i.il:Qressed
to the 21071-DA chip.
·-:-·-:-:-:-··:·:·:·
.·.·.·-.·.-... ·.·
·-:-·-:-:·:-···.·.
.,:;:;:;.

·: {\~: I:~: : :~: :~: \ :i:i: :.:t:=:

. ::::::::rn::r

Note ~--------------------------------------------:U.~¢.j.ii~e ·:::::1~l.l.i.i!l¥~:~~est suspends the CPU transaction in progress,
,J?!~t.:::~J.9.:uld be us.e'(f.only if that transaction cannot complete without the
'::•::i~#nP.l~\t.9n of the requesting DMA transaction.
·-··:<=~\lf~~IIJtt=:=:·.
. . ::::~=l~~~r::{:f}:::-.· --·-:-:=·--.-..:-:..

,:::::,.,.,...,.1...,.-..i~ Request

is the ordinary DMA request. No special priority is given to DMA
request unless it is programmed.

Digital Confidential 3-3

.. :}}}}

: -j·:.:_: ._·=_;"_\i=.,-.-_=il>
··.·

3.1.1.3 Arbitration Cycles

.....·.··:·:::··

-:;:::::;:::::;:·

/:~:}:::.

tt~J:f.

·=-=-=========-=·=·tt=:=:rt=::::fFfif'
The cycle in which arbitration occurs depends on whet.hir::::tJ.~kC:P.U di{tbi]!If'"
21071-DA chip has control of the bus. Arbitration wilJl:\[q¢Cuft•t.Ilij:::f.9~lowing
times:
-·=-- -::::::::::::=
""'='=<ttftl\>. .
•

progre.~~,,.,, arbitrill!!:~U occur--~~::!:{~-

When a CPU transaction is in
.
two
cycles before the assertion of cpuCAe\igl.fO::;.,..to the''''QF:W.%'§~~ Table 3-1.
If the arbiter receives ioRequest<l:O> at tfi.i~;::tj;m~, th;:::2'lQXl8DA is granted
(independent of programmed priority), ancf'&pµff~ldB.eq ii{'isserted to get
control of the Bcache.
·:<\/?\:::::====·"·.·.·-:·= ::::::::::::::\;'.::.::.
::::::::::: ::;'.:\}::::

Table 3-1 Arbitration Cycles of

·.:::::{:~((:}}:.·

CPU::~~i~;ib.tr~M.:::::=::: .
.:-:.:·:-:-:.:

·-:-:.;-:-:-:-:-:->:

l'Wo Cycles Before cpuCAck

.. :;;.·.·.·.·.

• When a n~IJ!\t~~~:~tio:<{~::-,){~jl!~fijgress, arbitration will occur one cycle

before ioCAckd'':'O~::i~S.i·.[$~nt to the\:21071-DA chip. The result of arbitration
depends on programffi~j.\::P.ti9rity if both the CPU and the 21071-DA chip
are reque~;~ng\th~:P.us~<==:'t_:,:':O::::'rn:t:=

•

When tbi-!!~J:~~:~i\i:~;)idJ~, a;bftration occurs every cycle. When a sysBus idle
cycle is:::f.Q.llow~d.:::ijy r¢.quests from both the CPU and the 21071-DA chip, the
CPU ~)J:\:b.~:tgf:~Hited.i:()Anependent of programmed priority or the ioRequest

~\\s~~-•lt~;-~u
!8; c=~~~~:;!t!1'~~~~:~ :ion
·-.·.·-.:-:·: : : : : :·:·:":-:- ·
0

.:/~l.J:gqgh.

~At1:~f::::::::<i_ranf:'"~~!f'=:i,_sm

,.,.,.,.,.,.,. ?/tf=A\ft~r th&=:=~\Utl::l1:DA chip has made a request, and the arbiter has determined
.::if]}:::=:= "''\['t.h~t the 21671l~J)A chip should be granted the bus, the 21071-CA chip asserts

/ i:i;·•
1

·• ll~!~~~~ ~!~D~e~~s:~i~::: ::0;i~!~~~~O~l~~s:~;s %~:t
0

! ·; ; 11~=:.f)u~~~~:l~~ ~= ::s~~~:~e!:e':i'.mplete

3-4 Digital Confidential

(ioCAck<l:O> has been

>'.·'.:'.·'.·'.·:·· •.

::::::::::::

After the 21071-DA chip detects that both ioGrant and cpu.U.9ld.Ack ==l~J:)~efi}V
asserted, it will drive its command address and data liq~~{!~~(!~pproprii.lt]::::rnrr
=:=\1::.·:~_::.:::.::·_:::::::r:::::;::::::::::;:::::;;;>::>::·

···-=::::::::::::::::::···

Note ~~~-.....:~:::::::~~:::·~~-·::::~+~:i~:::~~~::Vi~::\:~~·.....__
.·::::::;:::::::::::::··

ii!1ee

··:::=\\~:r:::::::::;::::::··

~:?.md<2:0> encodings change 'dt!f'0~ 'as ~~tl~i;t;~A chii\Has
····=::::::;··

.·:·· ~/:\::.....

·.·.··::;:~;(/;;;;;~;;;;::::;.;.;;:::::.

After the 21071-DA chip has received cpuHolclA~k:~:::.j·t::,~~:)~l.fpect~d to take
away ioRequest<l:O> in the cycle it driy~$.:il9.Qm.d<2:l)>.~:::j#l.).~ss it has another
transaction to do. The 21071-DA chipxm~\\'.~f.l.[99~~:4~ withdtaw ioRequest<l:O>
without doing a transaction; in this ~if it sh4#.l.ij}ij;jye IDLE on the

:~~;~~o:i::i:ii:~>r:: ~i•:~~~Jt~:!!?::~~!~~~'
0

performance may be affected, Qµl{:U.~rotH~if\lqv~r.se behavior will occur.

During DMA transac:t.~ons, th~i·.1-¥.lt:!-DA ~~l~liltldrive the DMA address on
the sysAdr lines ~tu:::tpe 2107UQ«::~mP. has cofu.pleted the Bcache probe and
latched the DMA a:aaw·s.~Q:Af.ter th~kiddf.~~:i;;. is latched by the 21071-CA chip,

!:si::~~:gi::•;:~,~::!~1;5fi;:!::~~: :e~~ :a!~ ~~?~i

will be deassert:&f::·fil.m¢.Ating t&::tll~:::g')Q:71-DA chip that it needs to tristate its
address lines. The :'al-1$.i~r:r~leases\tfi~fcache on DMA read or masked write
transactions which doNt)y~~-::th~ cache, or DMA full write transactions if the

::~:ri;;~f~li~f~~!~-~~e~:~s~h:i:!;::::~1:1'.~~~~~:;:i;::~~le,

or if the 2l:QZ~VbA.~tpps ~9Bequest<1:0> lines are driving DMA atomic or DMA
preempt. :\:Im::::/
;::;:::::-=:/
::::,::;:::/
·
..

5
·1·1 •

::;:::;::=

··:::::;:·:·····

':i3~ c~k~·!Q~jl;:leased (during a DMA transaction in progress),

a~ljJ.$.t~tipn occur~{omr·cycle before ioCAck<l:O> is sent to the 21071-DA chip .
.. If:~o#.Jd:Git.l~9 occur up to one cycle after ioCack<l:O>, if ioCack<l:O> occurred
=-:-::::····:-:-:···-· _··::_W:hile . tli~-j~ysaus was being released. The result of arbitration depends on
..-...·.···.·.-.·..·.··-=::,:q··:i~ramirl~q:l:p§grity if both the CPU and 21071-DA chip are requesting the

Digital Confidential 3-5

3.1.2

3-6 Digital Confidential

Figure 3-2 Cache Subsystem for a 512 KB Cache

TAG Control
D

TAG RAMs

C
Cache Con1rol
Cache Index

Tag, Tag V,D,P

5 x AS805

DEC chip
21064

Address

Tag, Tag V,D,P

2 x Sns PALS

CPU Cache Con1rot/::::::·:-:-·-·.· ·

__::·_::_)_:_(_@?·
.

..__ ___.;-··-J;;.:.··;;;;;;\:;;;;;;/.-.__,;;;~.;;...__,;;;;;;.=------------..__--w
Data

_<·::::::;:::····
.·::;}//
··:::::::\{:::::: :::::::·
.. ::::::;:::;:::::::
··:-:·:::::::::::::)~~{\:-:-. .. ·.·:;:;::::::::::;:::::::·:··
. -:==·~:~t:::::·;-:.:-:-:-:-:·. :-:-:-:-:-:···· ·.·.·.;.·

............

..:::::::.
:::::::::::::~:..
··.;.·.·-:-:-:·:·

2(4) x Data path
DECchip
21071·BA
LJ-03428-TIO

Tµ~:!\if.~U~~ng ar~:lW~rn~;l~ent features of the Bcache controller.
··.·.·.·.·.·.;.·.-.·.·.·.·.·.··:·:·'.·

·-:-:·:::·:·:·

~4~lmJ:~:f_acfii:::11nL~lze, and Speed
-<flt :::::?\{{}Ill~ 2107'1~Q4.):~bip supports only a secondary cache width of 128 bits. A 64-bit
:'d-H\:_}?::·
"'\l~f cache i$\1)Jot. supported.

. !ll!ill ) . · ,' l'~!~~h!e:fst:l~oC:~~:1;fc:~h:c:~:~t:~:~~= a1~~!~!~e~~-tfe'e

·--::::::/:·{:t::-:::·:.:}:-(kppropriate bits. The 21071-CA chip uses a register to enable the appropriate
. .,,,<=:_]'5]jj.\/bits of the tag address. Software is required to program this register based on
··:::':tf#}i.~-{~;i:,;e of the cache. Refer to Chapter 4 for additional information.

Digital Confidential 3-7

..::::::::;::;:::::=:=:=:·:·.

.·:::::::::::::::::::::::·::::::::::::\.

·.·:·::~:~?:~::::-.:·:/~~\(\{~if
~~t::.·
.-::::;::::::::::::·
.·.•.·.·.......... .
::~{=~==:}:::
f \\:~:~r:::···.

_j?{I?f

The only restriction that the Bcache controller places on ~e :;1~: l[:;;11~[j,\#
::i::.sClk cycle. Bcache writes can be programmed tip@i"~!i~~l;'.~,~Y~Clk
Bcache is that a 21071-CA initiated read from the cach,~{~~d?.~ coffiP.lit~Q.Hn

<ilt:~::!!i:j:t

···::::::;:::::=::::::::::::::-·

3.1.2.2 Bcache Allocation Polley
.·=-=·=-:·..
·=::::\tftiJtt:::,.
=::::=The 21071-CA chip supports a write-bae~i!!i$.~~oµQary di¢ij;.~::::::m~u~ Bcache is
allocated on CPU memory read misses. The =:®=~Qf=kPA chipi:::M)pports an
optional allocation policy on writes. Allocatioif':Q.~i\]i.Bt.Lmemdf.}F\:vrites can
be turned off by setting a bit in a register'. ...~efer·.;.to\@IJ.tP.t.~r 4 for additional
information.

··:::::=.·.·: ··.·. ·· · ·.·.

)f!? -:·: :;:;: : : : ;'.: -:-

···:.:.;:~:~:~:~·:·;<?;~)::::

· · .· .-.:.:-:-:-·

=?i!l!: : . ,: : ·:.....,: ==: : : \, :'. .:~;: :· :·: : : .:=: : , .,. · : : :=:==.

3.1.2.3 Bcache Write Granularlty

!!10:!1~~; ::::0~::!:e~h~!~~;111:;:~!'1!~:;~~it

transactions are handled. STx..d::[#rfuisi~i~9.U.~t:~e either quadword or longword
in length. Since less than anJ~m;i).Vord ca!M~iji)),g:=,written into the cache, the

!~°!\c~~i

::...•~z~;:~i·~~fy-~e transaction on the Bcache
·.:::::;::::::;: ·-·.;-:-:·:-:-:-··

On partial writ~$.. or STiiQ.lm~w.actiofis::::#ij~t miss in the cache, the 21071-CA
chip has to me,tg~::=\tb:~ writfir'ijj~~'?W:it.h data from memory and write it into the
cache if allocad6ni:l~H~~~pled. IfiOO[j(~~~t.j9n is disabled, the write is sent directly
to memory via the'.'m~m9r~t:».7rite.
huif¢E
·.·.·.·.·.·.·.·-·.·.·.·.·.·.·.·.·.·.·.

3.1.2.4 CPU-Initiated Bc~c.h.~ o~iltij!I')$,,
For CPU req~g$.·t.$:~:·:.tl~\~1oiflc~Ub'.hip performs the following operations on the
Bcache da~::!!P'ffl~~::'~~;.
.·.

.·.

.\'.:rni[;,::·!111:!:1:;
•

Extract$iii[ifi.ctint:l\blockj::J:tom the Bcache into the write buffer when the
Bcaehe·=:=1•1j:::tWbe allot~ted.
-:·:::::;:::::::..

··::;:::::::::::::::::):}:=:-~-. ·.·.·.-.-.·::.../{\:}~=-

J)-~ ~::~,•ri:~:~~!~~ i::~:~:~=~ returning it to the CPU

)(:j;

:i!~cei:~:~! ~~:~~! ::ed::~e~rite block w

tll)~il!; / i];;~t:::s~=~r:::b:::c:::::e~:r~:~:~~~::::::::·that hit
·=·=-::=:=+<<>>==,,:J:tt=:r=.. in the cache.
: :y;:::::::::::.!l!!!l:::::::::::·:::;,, Writes the Bcache tag store with the appropriate address and control bits
<==: =t:,:·mnn:.·il.t9:+1ring the above operations.

3-8 Digital Confidential

.i~ttf?:
...... ·::::::::··

-:-:-·:·:·

\~}:)}}:

:::::::::::::;:;::::::::::::::::::::::····

.:Yffr -:::::{i~f~~?Iji;::=;~:=:·:-:::
....

:/{f)'

\{t_~=_{r·· : : : : _;:_: : ·:·

. ...

\}\.

·.·.·.·.·.·.·.
't\:':t:\,,:,::::=:::::::::::::::::::.·.·-:·:;:::·:·

3.1.2.5 OMA-Initiated Bcache Operations
. _,. .·.·.·:··..
During DMA requests, the 21071-CA chip performs th~~=:(q},jp~J);g:}>Pef~tjpg~Nfo
the Bcache after it has received ownership of the Bca¢.ij~ftiS1hgjjifM.i:);pµ.FfoldReq
or cpuHoldAck mechanism:
.:t:=::J/:X
·.·.·.·.··:,::::t:_j:_:_:1..i=_, : _:_:.'.:_:_'.'_:',: _:·,:·_: _: _:_·.: _:'.t'"
:-::::·:·:·:;:;:;:;:;:-::;..
•
•

Performs a tag probe to determine if th~. DMA'':hiQ.il.))!~,,Jn the Bc.2ifohe.

Reads a block of data from the Bcach~[i'~l~ddoads.,,~f:::~dlSi)·£he,. DMA read
buffer if a DMA read hits in the Beach·~. <)\\?\:,..
·.·.·,: : : :·-:·::::::::::::;::::::::-·
: : : : : : :;: :;: · · . .
·-:-:-·-·.· .·.·.·.·.-...·.··:::·
..

•

Reads a block of data from the Bcache, merge'~/~~?witlt.DMA write buffer
data and loads it into the memory .wri.t~:=::pµffer 1f'''a/)p~ write mask
transaction hits in the Bcache.
, , , ,.. . ·..·.·.··::::::::=:::::'/;\=-=-·.
·:,::=;:::::::;:;:::
··:·:·:·:-·.;-: \}{~):::: ..

•

D.1\Df

Invalidates the cache block if a .·.··:·'.·'.·>:·:·:·:·:·:···. writ~''''Hiti,i[iWJthe
Bcache .
···.·.··.·.·.·.·.······

.}: : : : : : : -.

3.1.2.6 External Logic Requirement

:::=--.-:::.

····::::\t~~l~f

:::::t::<;::::ftL:::::....

~ee !~~!l~~~ift ~~~~:~ m:!~~~t~-~~ =~e::i :.;,~-:~~~ :~R
them with the CPlL~~®e coritf0.1::::~~-~- The. "f!cache PALs clock the system
cache control signaliHicc9fd~.ng to.'tbJ~):):i~~µic timing requirements of that
system before ~QRing Wijlj[i):th~tCPU'''MgpAJS'~ The 21071-CA chip sends data
and tag RAM .9#.tpµt. enabl~WWflt~.. enables, and lower address bit signals to
the Bcache PA1NJ9.~@::>,..
·':':':\J:UU:H\\>,,,. ·
·-::;:;:;.:-:-:::::::-:-:::.::;::::·.·.

-:·::::::::.::::::;:;:;.;:;:::::;.·

3.1.2.1 Tag compare Logi~:: <:mrn:::::::j:J!l!l!:l.n+>,,.
' </:-;>
As part of its f~I?&tipn 'sltnP.:9tt<~. system with a backup cache, the 21071-CA
chip is respoµ$iPl~@f9.r\¢9mp.iiH'.Qg)the upper bits of sysAdr<33:5> with address
bits stored<:#l·l.Jhe''t~g:::~~- The 21071-CA chip does this tag comparison
during LD~lll an9/$.f;FX_Q::]$..PU requests, and during DMA transactions to
cacheable #.\~m9r-Y:l:wace):@llie number of bits which are used in the address
comp~~pn·':'i.#.~lCm.~. . Pf!riW:)foheck is controlled by the tag enable register in

~:«Uifsc:i;efllll~'~C:~~1°:-~;;:~:c~':~ :ri::~~:Ii~:a ~~1;e:; ~~:he

.·..... tS:gA.af'$.3.:t;.17> bits read from the tag RAMs. In the other extreme of a 16 MB
.:·::::,. ::·:·:·:·:·
: : : : : : :=:~::1lti~acfM~:[:if.!f.ii:g:!Q71-CA
chip would only perform the comparison on bits<31:24>.
··.:.:.:.:.:.:.::::::::>·
····:::::::::::-:;:::::;:;::::::::::::.

,,+·rn~~i'~£if<P:etl Prtmaf~t=gf.che 1nva11dates
,(=.::<>>
::::::<:\f\).

·'·g~:i21071-CA·.,,~hip Bcache controller is responsible for ensuring that the

::.\;Q}?tJ Dcache is always a subset of the external Bcache. Maintaining system

<:\){}})})::·
· .-:::::::::::::::ca:-=·>:· che coherency 1·s accompl1'shed by assert1"ng cpuDinvReq to the CPU at the
·;.;.;.;.:-:-:·:·:-:-:-:-:·:·:·:-:- . :-:·:-:-'.-:-:--:.:·

_,:/:::))}{\:>:following times:

"' <H::!\\!\!!!::;::: 5.:When a valid Bcache block is replaced during a fill of the Bcache with CPU

..,,.,=<t:·-:[I~-tream read data.

Digital Confidential 3-9

.;::::::::::::~}\:: .

.:::~:~:::~:~:~:~:~:::~:~:~~~~~~~~~~~~~~~~::::::.
...... .:::.·.···

·:·:::::::::::::::··
::::::::;:::::::::

·.·.·.·.·.·.·.·.·.·.

··:-:-:.:·:=:·::··

·::;:\:}}}~:!:::::::::::::;:;.

./~;(==:.:-·

\E[lil[lli?' _:,::::::::::::=-·

·-:·\\t/ftt~~r=·:·:::,:;:;::·:::,:,.·

•·::~ :u~ Bcache block is replaced during afill•~jilHl~~~:J''tiid'
•

During a Bcache invalidate due to a DMA write ofiW.rite . 'ffii!liikt~at hits
in the cache.
. :/:':1\H;: \ \j \ t'.
·-:·::::~:::t:::\t\:1]\:}'"

•

During all DMA writes when the Bc~~A'-Js disabf~~\!:~bw.:hen no ..B,~ache is
present in the system.
.-:·:<'.'.'.'.'.' .'.'.:'.:::::-- _.,_::._::_::_::_\:;.,.
·······-:-:·:::::;:'.'.'.)\(\:::·.
·-:·:::·:·::;::

:-::::::-

The 21071-CA chip assumes that sysAdr<l2:59.lmi:l'-H9~cally':::~M~hected (either
directly or indirectly) to the CPU cpulnvAdr<1~'::5~HP.i:i#t:~P that the correct
Dcache block is invalidated.
./:)}:}:::::::::
··::::::::<??;:;::::::=::=:::: ...
·:.:-:-:.:-:-:- .·:-:-:·:·:·:::::: ·.·
·:·:-:-::::::::::::;:;:-::

3.1.3 sysBus Controller

;.;.;

. ·-::::::~:}~~}~/

:::)\~{/ .. . ·-::::::::::::}~. :=::"· .......

:::::;:;::::::·

·.-·:·'.·'.·'.·'.·:·:·:\{{t'

~,:~u~efci~t::~l~::::e~i~~~§illl:~:~~'l~::~o~~~a:~~~

from the memory controller logicf}fiie"':$ijqij~~r supplies state which is used
to generate Bcache control, r~Al@riluests t6<ttiifaj}emory controller, and loading

~ck~::;8t:c~~-~~~-l~Tn!~%.and write buffer, and
·:.:.;.:;

-.·.·.·:::::::::;...

.;.:·:·:;:-:::·.:·'.·'.·'.·'.·

··:·:-:·:.: .. ·····:.::::::::;:::·
·>:·
··:·:-:-:·.

3.1.3.1 Wrapping
:-:-:-:·:·
··/}\\: t::\\:-.
·.·
The sysBus corltfAll~r.supp.6Mi.)~~pping on the sysBus. On read transactions,
the requested oct~iw9:#.i:::~~:.:eturH~:.j~g!·j~he CPU or the 21071-DA chip first.

Wrappi,gg)ij~::::ri:J:~.::~i~tiog~l in.'fhe sysBus controller. The processor must

be con~·~~::::19!· :-~~ping enabled.
....

3.1.4 Ad~di

\::::}:::::::::::::t~{::

.·:=:=:::::::::::;:::·

oe::9tlltl}if];

....·.... Th~\:!gi.QtkOA sysBus interface logic decodes the sysBus address for both CPU
:I:rnt:]!Htm:id til@.Afaf:ffllµ~sts in order to determine what action needs to be taken. It
. ::·:·:··-::::\\'ifffi#.P:Ports·::ca~i.Jiil>.le and noncacheable memory accesses, as well as accesses to

.. j

l';l'~i,iW 'll::~:=:~~s an exact mapping of this address space.

"'.;:·:;:.::::::::::::::::::::::::::::::-..

3-1 O Digital Confidential

\~:}~/?~f~r··

1::ttL

Table 3-2 sysBus Address Map

·=·:·=- ... :\}:::

::{:\/(.... ·.·. ::::::::;:::;:··

sysAdr<33:32> sysAdr<31 :28> Address Space

:xxx

··:·:::::;:;: :-:-:·:·:-:·:-:-:-·.·.

o:xx

N oncacheabl~JA~W.ory spfui~/
·::::,::///)(:.:.::·:

,,,,:,::;:/='
... :::'::\})...=·-·.·.· ··
·······.·.·-:::::::::

:access .
cesse y
DMA; can be used for
·-:-::-·=·::::::::;:::::
a frame buffer on the
···.··.·.··:·:::}:::::-·
DRAM bus.

··=-:·'==r==:::..

\Ct. . :.:

100

·:·:: ..
·.·.. ···

lQl

·<I:;::::'::::=:~~rved"''r6i:::·1)971-DA

.{(;;111\; . \· · · · · · · · •·•·•·•·•·•·.·.

The 21071-CA chip
will respond to all
addresses in this
space. Dstrearn access
only.
The 21071-CA expects
the 21071-DA to
respond to addresses
in this range. CPU
Dstrearn access only.

Sarne as above.

Sarne as above.
-:-:-:-:.:

3.1.4.1

h\c.cessed by the CPU

'<f:J(J.~trea)m/DAcstrearnd b

nu: : : \.;.·.·.·.·.·..·.

-::::;::::::::::::-·

::::::::::::::::::

Cache-~,~- itle1::.:~e.f~;:_:~::'Q 0000 0000 .. 0 FFFF FFFF

The.. 2il071-Ck:emP.m'ii.®.iri1zes the 4 GB of quadrant 0 (corresponding to
sy~Bij~I~ddress<a=3:~:32;r=--~ 00) to be cacheable memory space. The 21071...·.·.·... CAiimP.}t~-~ponds to all read/write accesses in this space. If the Bcache is
. rn::rnrn1:::)i@:P.abiedE~ii.h~tProbes, allocates, deallocates, invalidates happen according
.:::::=:::\,::::::::--:=::=r:tm:~~f:t.he pr6ti:iilit~escribed in Chapter 5. Some or all of main memory can be

11:::·,

~,ammed~be m this cacheable space.

Digital Confidential 3-11

··:·:·:·:-.·.·.

-:::::::::::::=:· ·.·:·:·:·:-:·:·:·:·:·:·.· .

3.1.4.2 Noncacheable

Memo~

.. ;:;::::::;::::::::::::=:::::::::::::~~~~~:::::::::::::::·
;.·.·. :::::::::}:::::::'.;:;:;.;..

.)~:\~}~'./

Space • 1 0000 0000 •• 1 7FFF FFff

lljfj;t

·i! l1[ ~.: :.: !lf1Jj\lf'

;:s~!!0:J;!s~i::~~!'1~~st!11i:e ~::;a!h~!~! ~':~11111\s~!"~~A
chip responds to all read/write accesses in this spa<;.t:~::?The Bcacb~:[\~$.:\\lOO>assed
by the 21071-DA chip on accesses to this ~pace. $qm~[[]i.tJtll of maith#iemory

:!~~";::! ~=:~,~i::o:~~·~~:~~~~flt;~tffer is
-:::;:;:;:::::::::;:;:::;:::.

3010403

~:~~~~~: :::;s:=to~~a~;s:::::r~~~-ji;~::;~SR addresses
are defined in Chapter 4.

·,j:.'J\i,!i! :'/:\,,::,,,,,,,,,,,,,,,,.

··

·==:=: :':\: : : : :=: : ·

3.1.5 Lock Address Register and Lo~.~:i:.lht · -======t i[' ·f.\·i,.· . '·l :=: :m: : : : ...
The 21071-CA chip implements t.b~[\:iJtj¢J.fa~Q.dress ·-i~gj]jt~r and lock bit

:;~~~;~5~Y!ie:ti:~;I:-~:; ~f~;_~o=~ctions.

The 21071-CA chip lQ.~ks 32 t)y~~fi~f..data aCi~kti.me. All LDx_L transactions
also set the lock bi~::l~ciated'''Wl1·[.l~==Jl.ddress'='·register.
The conditions whici{=::~1ddhe···:·:. lock
follows:
-:-:·:·:-:-:::::::::-:·
::::{/)t~:

'btMiimas

•

Chip reset_,.::'.).·.:.:.,[_=.'i·'.:.=:.:',=.:.='.=:,:. =.t.: =.,.:·.·.:'.·>·

•

A DMA writ~/i~i.1$.~:Jnat~h:gi.:itb.ij:Jock address

•

A CPU w.r!t~=::\#9.:0 l:~Y:,.Vb:::'~d_af¢~fa (to provide PALcode resetting of the lock
flag.)
.:. ·.:.:.:.;.;:: ···.: ···-.:,: :,:,:,:,:.:,.:.
········

•

The

,.,.,.,.,.)\)'
=\,,,,,,._
·::;:;::::::::·:·>:·:·:·:········

a~~ii~on:::dil~~f~=e=:ibblrLock command from the 21071-DA. This

:£m11f~l~la2d~~!~~! !:ek~1 .the

.·:-. <t:.:.::.

lock clear as long
flag

·-=:::::::::tl\::::11:Jt>:::=··

-:::~~~~~:~:~:~:::::::~::::::::

.;::::~~~~i~~~~~~~j::::::::::::::~~~~~:;:;.

.·.·. .:,: >: : :=: -: {=: :==-=· ··==='='=tntntt,,,,,._
Note - - - - - - - - - - ..========}fll··::!l:!!!!\i!\"·:]/rhe ·~fifi;:~if\'the lock bit is unpredictable after STx_C and LDx_L

( I!ll!I:;: ;. ..d!!l! "~-·r_an_sa_c_ti_·o_:s_s==_th_a_t_h_a_v_e_t_a_g_p_a_n_·t_y_o_r_n_o_n_-e_x_is_t_en_t_m_e_m_o_ry_er_r_o_rs_._ _
·-:::-:-:::::::::::::::::::-:.:-:->:·:- ·.· .-.:-:-:-:-:::::-·

3-12 Digital Confidential

·.·'.·'.·::::-·.-.

3.1.6

•
•
•

DMA writes
Victim data from the Bcache
CPU noncacheable memory write data (wffieb.Hu~lµ.des aiFCPU writes
when allocate mode is disabled)
····.:\::::::::::;i;·,::::=::
.·.···... ·.··:·: .·.·.··.

·.·.··:;:· :.:-:.:·:-:-:.:·:·:-::::..

The 21071-CA chip stores the cache Hni:i\ii.ijm~~~JongW6tt1Fmasks, memory
bankset bank numbers, and a cache-1~1.ji/valid:JJ).!tffp~r.. entry of the memory
buffer.
.....: : :'.": : : .
·.·.: :':":,: : : : : : : ··
. :)}~~~ff{((;:;:;:

·.·.·.· :·:;:;:;:;:::::::;:;:

3.1.6.1 Write Buffer Address Comparlsoil,\\\\l\\#<t::::!·ll\jli.-::f:\):::::...

·-:·: : :·

The 21071-CA chip architectU:db~Jlbws ~~l,.;tyfa7~:ad requests to bypass writes
as long as the read a.d4ress dQi,i#~P.t:. match ·aa::J.ddress in the memory write
buffer. The 21071-Qlii\$tip comp•r~~::::t.b.~. incoming memory read address
against the address:~~N)f.Jl~>yalid -~htjl~j\:\p~Jhe memory write buffer.
If there is a m.~~b,. . ther(th~:/fil~mpry ·-~~h:ttoller will continue to dump the
contents of th~+wri.t~fpµffer ttFm~m:Qey,_ one cache-line at a time, until the write
buffer tit conditioiV#.9::.l't)bg~r exiStMi(:'Xlie memory controller is then free to start
the original memoey'h~i.9::::~~n~actiotFwhich resulted from the CPU or DMA
request.
··················

~~~~i~aPJlil;~~~=:~:i::~~~ ~1;'~: :i:~~; ~fCi;~
:!!ti:t~il!~:li~~~~e~~~~d
.}~::::::::::-

.....:.. _:.;:·.·.·.-...

write transaction, or apartial

. .·.·:{~~(:}'.:::~{

Wr,,~_:'Hffer :Ftfil~9~::f[?ii?'"-

3.1.6.2

Thi%1107.1-CA chip·.·allows the 21071-DA chip to flush the memory write buffer
:::-:-._Witlk!\::ji!S~fl DMA command.
··.··.·.·· -.=.=-:-:-:::.:.:.::=:::::::::::..

··:::::;::=::::::::;::::=::·:·.· ....

:ia~fGs~3::=:nrlme e1..i"ntifaFti~LCond1t1on

:/··:::l::.J?.

m! ~'jj) lo>

·:::::·J.f::t.°be memoeyA,;rite buffer is full, then the 21071-CA chip accepts the first data

Ifi!~~ ~~~:~ :1'!.i~::.;,.it~eas~:'::~r:i'a :~:i:e~l 0°:~h~~s~~~::ion
1

'<{.%\%.:{:\:{:{%,that time. The write buffer full condition can happen on CPU memory writes
·::::::::;m.;;·:::::.:.:·::·:·("!:-,(p()ncacheable or non-allocate), DMA writes, and victim reads from the cache.

Digital Confidential 3-13

:::::::::;:::::::-:::::::::::::::::::::::::::::::·.

./??~~~r:·:-·· ·-:-:·:· · · :;:;:;·_:;'.;'.~'.:'.: : :
·::;:::::;:::;::\~~tr

r ){/}{

. ..
-~ _: ,:·_,':~=_,':~·', ·,:_,~·,:·_,;·, _:.=,:,=.~.{

3.1.7 Read/Merge Buffer Control

_,.,., , , , ,., , . .

···=·==::::::::·

·.:-:·:·:::::<·'.·:·
·.;=:=:====:====:

.·.. .......

_:;:.:.:-::

=/~;irt:::i?

.
::}~{{{:}:··
::=\=~r·-·.·.·

,:!'·:·::i:!!\!l.It::=<::=:=::tJr

The 21071-CA chip controls the read merge buffer from:([itb~i::l.(lQiA::.BAq~ffiP.Ff'

~:~erge

buffer is acache-line buffer whic:;!iird flW'41.

•

Buffering read data from memory un~!J.k~be
sysB#:~aw::t.~!l.dY to red~ive it.
-::.::::::::::;.::::·
··-:::::::::::::::::········.

•

Supporting Bcache write allocation i)y>p:~9yigj:Qg a irt~¢ij~=~:m to merge
CPU partial writes to the cache with the<f~~~[t:1~~::[~~~ cachijt:l#ie from
memory.
. . , , :, , , ., :-/\\:-:·. .
Supporting STx_C transactions whj9~j::~jj!!i~~t:Fhe ckJh.!:~!li>'

•
•

Supporting LDx_L transactions wij~fi'''hif:;~ij,,"j~~~:&~~he~,.

:ei:;~~9l:r~~; :;;i~~.fA,.:~~~~f~:;e:a~a~:~:':~e
merge buffer is used to store wri~~f'data·t+Q.#.f\tb:~t_CPU or data read from the
cache.
.:::·:·::::::=::::::::-:
· ···::.;.::,;,;,;;:;:r>

~::ear:~uin::~i~~J~¥t·~~~~:;;B'::'::bi:~e~J~~!r.

The read buffe1\~~s as ··~Fthnlrm>~tage ·fif:pffase align the memory timing to the
sysBus timingi{M~t:Jhe ni~fiWQ\@9µ_troller has loaded an entry of memory
data into the reatUb#f.t~r,::Jt sets'lh.:i.j::.~titry's valid bit to indicate to the sysBus
controller logic thaf'd8.~a~tr:~ady fff:l)e returned to the sysBus. During these
memory read transacdJn~@::~b~A;~,µ.ffer is also used for storage, because the
sys Bus could_ p~'}J~\~~~yf:r1;1nsf~-~'Victim data from the cache.

[Mtfte

During a c~~h.iji.lj'fJ.
J>.lock.,t;ansaction with allocate mode enabled, the
valid lonmris of\QPU ,dij.i~ are loaded into the merge buffer while the
memory cd~[tt~n~:::ls· fet4ljijig the rest of the cache-line. Because data could
returr#ll-9..µl"''w~m9.J..x,J;>,@fqr~?all of the CPU data has been loaded, the read and
mei;geil~#ffers'.''ei!UP.i!ll~M simultaneously.

nutfu~j:\i,iv~ speci~}""~:;,;;·· of a STx_C transaction that hits in the Bcache, the

.· :·:·:·:·::::::::::.?:..,,µierge{@i#t:m:Js used to merge the valid longwords of CPU write data with the

. ; ;i mi\(i~iBi.;::~·c~~~= ~~::~7:':i!!e~:!eba~~ ~: ~!:c~=~ been merged in
.:=:H!·:·:::·::·:·f/

'\'"H::i/:.;::.U::::, .

.::::R~ng a LDx_L transaction that hits in the Bcache, the 21071-CA reads the

,::JC4.~ta from the cache into the merge buffer, and then drives the requested data

. . '"':::::=:m:· ::·\::[-:=\3:-[:)::]:0n the sysBus.

3-14 Digital Confidential

3.1.8 sysBus Transactions
....::::::::::::::::-:.:· ··.;.,

3.1.8.1 CPU Transactions

.. :::-._ .=:::::::::='.=:-·

:·:·

::::::;::=:

··::::::r~~\?tf\/}::
·.--:::::: :-::::;:;:::::i(<

•

Read Block, Memory
.,: : : :;: : : :. .
.,.,.,.>:;::<;::·!'~][\::::::.....
· ···.·
A read block to memory can be to caehii:ble,J>r norica¢biiijbl~ memory space.
Data is read from memory and return~'& tg:::~b~:':,,GPU~·-:,O.&~::~¥::~~heable read
transaction, a victim, if any, is extracted ·wom::::m~t:~ache~'\i#t then the
cache is filled with the memory data. Qnly on'tf~&!w9r.d is transferred on
noncacheable reads. The Dcache isjqy~ji~ted on<1@,ri~m reads.

•

Read Block, I/O Space
::·:':'.}}·· · , , :;: ,: : : :_: : : : :;: :.....
A read block to I/O space may Q~t,a.ir¢cted t0<th.i.:::2:1~)7 l-CA CSR, or to the
21071-DA chip. On a read bl9.¢.k:[~9,:]i.i~t~1071-CAW:¢'8R, the data is returned
by the 21071-CA chip.
."':'.'.' ':?'t:·:-::-:::'\/)\Jit:·
A read block that does no.t::;f.i.\j:i!'~thi~:::tHi.,·l~D· address range is assumed to

-:·:::::::::::::::::::::::::-: :-:.:-:-:·:::::::::..

~:~~~~~:i1)~~!!lll\~ye :=: command request, take

:¥:£iii~~lii~!~!:!!:~~~:1~~;~~:~

-----------·-·:::::-::::rn:::·,l~te -----------·.·-:·::::::::::::::::::::::::::::.:::::-:-.

The 2107!r:P.~/¢hiP: c~rlh~t.:i4trectly respond to the CPU with

~i~f4t~~~,~.l.:::.:il.f.l:_::_::_,CA1ilf<2:0>. It must respond through the
-:-:::::·:·:·.·:·.:'.·

·:::=:::::::=:::::::::::·.. =::::-:::::::::·· '

.}}~tt=

~j,i·{tp ;~ia~li~i.a~~jijfto the 21071-DA chip can be preempted by it for

.J4.¢.~ock re'sMiiS.un/hr any such reason.

::::::::=:=:::=::···:.·-:.:-:··

.. ......... e'' Wrlte·=·filock, Memory

(\\fj~!!!;!!; ,!~-~~~==~ :~ =~e0~::8!:. i~ :~~:a:l~~~~c~~

"''\l%f))data receiv~d from the CPU if the whole cache line is being written. In the
I.lt1base of a partial write, CPU write data is merged with memory data before
.//:t·:::/:· writing in the cache. In either case, a victim (if there is one) is extracted
before the fill.
··:::::n:::\j:j!jlj:!Jjl:)\l!lj!j!.!ir:::::,•. If allocates are turned off, or if the write is noncacheable, the write data
·:::::<t+:::::t/fr.9m the CPU is loaded into the write buffer from where it gets written to
:<t :_::-:memory.

Digital Confidential 3-15

•

Write Block, 1/0 $pace
·-=·=·=·=·=-·
&t:::1:::::::::===::=::::/J:::::::D
A write block to 110 space may be directed to the 2.!Qt:tf:OA:::OSR>'ijf:'::~:~qii
DA chip. On a write block to the 21071-CA CSR, JiJil.~PiMwr~t.t.~n to':lHK.
CSR and the transaction is completed.
·:;;::;:~::::····
···:::::;::\ff/tt:::::.,.
..

::::::::::·:/(}

. ··:::::{:}\~{:}~):::·

range

An 1/0 write block that does not fall W,thin th~:::g$.l\Jlddress
is
assumed to belong to the 21071-DA .~P~P'V The 210.7'19.J.AJ!.hip is expected

~~~~?i~;1~~l ~~~ ::::sh:u~~at~:;:~•T•~n=~
1

addressed_ to the 21071-DA chip can be pre~'mpt~ij::::l.?Y. it foFdeadlock
resolution or any such reason.
··:=·=·:::or=:::===::=::~)\))}\:::=:

•

.:::;:::;::::·: }~~\}:}~::::::::::·.

LDx_L
·=:=: : : -: : :· · : : : .:=:::::::::::::::::::::::::\:::.
The Bcache controller performs a '¢.l¢h~ pfobg{JJf:jITT,e address is a miss,

!~=P~~~::~~~c~ee1::tl~-,-~:=,~~=~:::s:::~ :~ lock
0

:fa~~s ==~r:ei::::t:s:J~lt~!~f~~:ri:~ the merge buffer
::t::r:~. :::!If'~~~,,,~~;~~

mlSs case, the address is
lock

A LDx_L tc.vMQ spac:g:\\\i~:j:~!9.9J~d ;;:::i:::f~;d block to 110 space.
:-:.:.:.:-:.:.:.:.:.:.:.:<..
....:::::::::::::::::::::::::::::::: ..
STx C
···=::::::::::::::::::::::::::::::=::;...
·-:-:-:-:-:·:-=·:-·-·.·.·
··=-::::::::::::::::::::::::::::::::::::..
· :-: : : : : : : =: :=: : : :=: : :=: : .·
The 21071-CA'ch.jp:)9qly responq~\to STx_C transactions addressed to
memory space or.fo/lt.$:/(%$~ spadt On a STx_C transaction in memory
space, the sta.t~::J~f the<t(fol(i.::f.J~g is checked. If the lock flag is clear, the
~::::::

•

~~~¥1'1~,,rtt;;=!c~!~ ~::!~~!e!s=Ii~!~~;~! CACK If

A cach~jfi)r~b~ti!~$.Fd.on'-::a4 detect a hit or a miss. If it hits in the cache,

~~flt{C~t:: !:r:~r:t~':·~! ~=~~~::~~=n

.49.,:::\)ie cach.e?Hljy~!::ls:::'hecessary because a STx_C transaction is always less

_,,{::::mi.ii\~ octaword, and the write granularity of the Bcache is an octaword.

·.·.'"{f::li\:t®.b.e probe failed, the remainder of the flow looks like a write block.
=·>=·=·=·=·>=·>=·=· ___ ifr:\tb.\~:::=~te block flow, the write data enters the merge buffer if Bcache
··====:=:=====:=:=======:==tu...~+ 0 a1l00~~- is enabled, otherwise it is stored in the memory write buffer.
STx_C to the 21071-CA chip CSR space is handled as a write block.
Error checking takes precedence over checking the lock flag.
Barrier

1 terminating the transaction right away, it allows the 21071-DA chip

\HU\H\l .~barrier transaction has no effect on the 21071-CA chip. However, instead

·,

3-16 Digital Confidential

to respond to a barrier. The 21071-DA chip therefore .ha..$ to
21071-CA chip when it wants the barrier terminate.41.:):ij)j)tiltlVit\::,,._
- - - - - - - - - - - - Note

:::·:,·:1).-.::::::::::::::::::::::::::::::::::::[.l!i.:.:.··:·:=:::::::::::::::::;.,..

The 21071-CA chip requires the 2107kPA chipi::1::l~~~p.9nd to·-=:~:::BKfiier

:~~:n~=i:!!~:::~~~~li+ti'\~;~\~piy~,i~!;i;;;ndition
··.·.·-:-:-:·:-:=:·:·:·:·:··-·.· .

•

.···:::::::~:~~~~~(:~.~- .. -:-:.· .· ..
·.·.· ...

····:·.

Fetch, FetchM
_.,,,,:;:::::J?\:::;,,:,/>:::..
· -=::::;:::::::, :/::::::::::::·
A fetch, fetchM transaction has noJ.~W.~t{Q.6tth.~ 2107l~CA chip. If the fetch
or a fetchM is within memory or tij~:&10"7:f$.p*@~SJi space, the transaction
is simply acknowledged as 015..4;.j~[::g1071-D:Akm.~1Pmust decode and
request acknowledgment of f¢.t.ID.1.JH.ID.9.!.#:~t~hM if they are within its address
::::::::/.::::·:·· .. ">:·:·:·'.:t::··=:~:~:;:;:;:;:;:;:: ·.·.
space.

3.1.8.2 OMA Transactions

:.:::::::::·::':":":"=·
.·:;:::::-:;:::-:-:-::;:::

: : : : : : : : : : --···

·-:·::'.{{/:({{{\:-:-.
·-:·::;:::;:::::::::::;:;:;:::::::-·
··=-:·>:=:=::::::::::=·

After DMA wins ar:WJtfati9_n, -~~/mi.~:-ltmw~st a:~;ansaction with the 21071CA chip. Unlike the:'tjpJi::::~sactlbni~lt.h~.b9nly unit of transfer for DMA
transactions is t!:le. cach(ftip~~:lllm:):::,...
"''·'+:::;::://
.·:·:·:-:.:·:· .::::::::::=:·.

•

·-:·:-:-:-:.:-:·::;:::::::::;::-:-:-:-.

DMA Rea<f<\:tt/tt=::::,..
·<:'<:/=l?/l'>::,.
. A DMA read cotnim~Q:js sen'ifb.y:::)he 21071-DA chip to indicate that
it wants the lowe·F~tiwPrP. of the cache line first, followed by the
upper octaw9rd~':·:-..'rhe\V.h9.:l¢)e~he line is always returned. A DMA read
transacti.9#.rnw::::¢~¢b.~~ble "'sp~~g:' causes the Bcache controller to do a cache
probe. :ltnt.li~' ·aaar~:ss bits in the cache, data is read from the cache and
return~ij{tb t11~:\l!~i07:t.f:i.)A chip. If the address is noncacheable or if the
adf:lres~[)ll,!.~:~~§{in th~::[g..che, the data is read from memory.

• nli~:R~dal=~lt~P.P.!~··l:!lrr·

.,AJ&jijii)pnly difrefenee:::f)etween a DMA read and DMA read wrapped is that

-=<Ytbi#f.~:quested data in this case is the upper octaword in the cache line, and

·1Hatfsfihuld. be returned first .
.·:::::::::::::::::::::;:::::::~\: :::I~i:=~:t,. DMA'ltiad?B.urst
:J:_::.:.[::_:::rnr··
·=-:::::::::: ·:)'jjThe DMA4t~-~d Burst command is similar to the DMA Read command. It
.·:·:·····:·::::::::::::::

·.·.

··:.::::~:~:}~:~:~t{}):;:;.·

!II ~~~:e:J
~~; !;~~;~~ ~::~~::t~fi:;eoom::!::n~!! !~~~l~?~e
end of this read transaction.

':<:: ?{:{)):})):':'/

Digital Confidential 3-17

•

DMA Read Wrapped Burst
.·.·.·:·:·:·:·.·. .
The DMA read wrapped burst command is similar"J9)~j!ili~t:P)~IA
wrapped command. It is used by the 21071-DA cIY.ii]if'jq~@!h~~ge
hint to the 21071-CA chip, and will cause the ~";r.#.pfy contfiUSff~~t::remain

:=~=~;::the end of this read ~~;sacti~~~'~!l1jfil']Jk

"'.iF'

This command indicates that the whole·· caibeJine has\t6.k&twritten to
memory. If the address is in cacheable sp'ii~~K~b~~tJ~ache·:u::::IJbed. If there
is a cache hit, the corresponding location is IHV:i!nal~d in the Bcache and
Dcache. The write data is loaded int.<f:th:e.:. write:::HtiftMHfrom where it is
written to memory. Except for thEt~~HiJ.~i):·~~V@Jida~·,::::tfi~?operation is the
same on noncacheable writes or caihi:"·m1$iHf:Htes..

g:: !~h~~~ :!~:1:d~Vp*t,;$~!!t:~i:~~ystern, every

•

.·'.-'.·:· ·

····:::{({/ {~~\~::::=::·

DMA Write Masked
/{:':·.\'{
·-:-: : . :-:-:-:"""·:-: : : :.
The 21071-DA cqjp requei~U~:::P.MA. writiP~tfsked when only a subset of

:~~:o: ~-~~?It•~~~= !~OJ~C: i~hir!c~::sr!,:
::: !:=~·j,:~Jlll~:~'fias°~=~t~s8::i~~~i~~~d~to

g:: :~h!~~llL1lL1c~J1'Jllt~n~af;~fe~sent on the system every
.. :-::::;:~:~{:~: ~:/~~~:~~}~'.::

•

DMA Flush... :-:·. . .
·-:,:,::::::y:::::::: ::::::;:-:;.
This coiµm~a:::·$.J.~P.Jd be:::ti~~d' by the 21071-DA chip when it wants to
flush t1·#~:::gi~in9rx:)Vrit~':buffer. The 21071-CA chip will acknowledge the
transa&~~fo
aftirHill qPffered
writes have been written to memory.
·-:·····:······.·. .·.•.·.·.·.·.·.··
:·:-;.:-:-:·:·:·:·
·::;::;:;::;::::;::::·:·..:::·::::::::::::::

3.1.9 Error @ggdfig:g:)):I::;:::=:::::::::::::::t:mi:l:::.'.·:l':
D~rjp.g):f;l>u ;raMJl#Jtf~sactions, the 21071-CA chip detects the following
er#,#.~!~:::?\

. ::::::::tt::=ntt~:· ":s~iil~:::~g address parity error
····:::::::::::::::::::::::::::::;:;:::-:·
. ;::::::::,:,;:·:>·
.·.·:::::::Jl:)':!:::j::::t'3cachEFt~l~::,htrol parity error
..

:::-:·.·<·:-:::..

-:·:;:;::-:-:-:-:-:-:·:·:·:·:-:-:-:-:·.

:1~11!!1\.\\\:):Non-existerit memory error

'lI~illlil ;lil~l!'::iso:eo:!~e~~~s ;~~d::e::i2~~7~-~~:~:i:~, t~: ;;:~~-&~ chip
::::;:::::mt:Utl:bp.nsaction by acknowledging Hard Error on the cpuCAck<2:0> or ioCAck<l:O>
·:'<)}:jfi~ldk:The current sysAdr<33:5> is logged in the error address register and
'eff.q-Fstatus is logged in the error and diagnostics status register. These CSRs

3-18 Digital Confidential

; ;:ill''llt!~llil:.\)}:;.

·.·-:::::·:·:·:-:-·

jI)Jt

._.:·.:~_~:.·_.l_.l _~·li:j:t<:t: : ; :; ;:f :. .·.·.:·:·.·

· :·:·:·:-:-:-:-:·:·:·: .·:::-:-:-:·:·:-:

by_:JY!i~i~~

··::\}{@~/~(:·

are locked until the CPU clears all the error status bits
ti.i:.:Q§gJ\:li-l=l.:l
Refer to Chapter 4 for additional information.
. trn:i=[j)=j=j· ,·:j ·j·jij \=j·l j: ·l1: :=: :. . ·. ··==:<1\~lilJ:l\;:,;=;=;:jJ\f
If errors occur on a transaction while the error addre$.iH,thd s=tat.#.$.:J~re. locked,

e~kr:~~:i~~:=~:~:!~~:~s~:~,,~'I~ a1tu~~s~~:s

~:::~~:~:!e;e~::~!~tnd neither the eq~!=\\~dg~ess.ifot[~~l~]mf!?r status of the
·:::::::::::::::;:::::;.;:·.;-::·:-:·

The hard error indication overrides STx_C fi~ii~<mb.¢=.iJ9.~k bit="f~Uahpredictable
after LDx_L transactions that have error_~~:. .·
"":\\ij=i=,:~~r·.··.·
.·.··:::::::::::·

3.2 Memory Controller

:::::::::} ·:::::?::: ·.·.·.·.-.:·=-····

·:·:·::::::;::·:·:;:-:-·· ··:::::::::::::::::;:;:::::::::::

:-:;:;::;::-: :::::::::;..

This section describes memory or9:~~!i?.n. an~:fffiim!t:Y controller features.
.·.·.·.·:·;·.··:·:····-·.·.···::::::;:;:::...·:·:·:·.·.

··::::::::::·

3.2.1 DRAM and SIMM Require~:~1pr==::::::1:i::::\.::\l:i,·,,.1:~:::11t=:::::.,.

~~~~C::~:r! ~:e ~.:~tr.~l~~tl~lil:sti:'!,~l~~~lc:i::i:!~~~s.
0
:~~ !~~!~'~il:. ~~~:~llii~I:~~: S:~8n~~i!~:u~~ t:e

grounded. A s~p~r~te cAS:l)~f,i[:iJ.9.ngwor(Fmust be used at the RAMs. CASbefore-RAS reffe~h::::m~t be slippg~9,.=~=- The eXJ)ected RAS-access time is 50 ns
to 100 ns, with pag~tm9:4Y:===CAS~aeC,~~,:·:;time between 10 ns and 50 ns.
·:::::::::::::::::::::::::::::::::::::..

3.2.2 Memory Organizatiot.U=@m.:.nu:=t=--·
The 21071-Q~:::¢.ljij·!-~µpport~\b~tW~en 8 MB and 4 GB of dynamic random

access meIJ!qf.Y?O::>ltiMYam~ an ·=additional 1 MB to 8 MB of dual port random
access mem9.f:Y CVB.NM)~ A!!{!!\
Memoa. c~j,:jl}if~t=~seq:jilj.:1ltwo widths-64 bits and 128 bits. The actual
numbijfJ~f bl't~fafgijµj~~9:mFhigher depending on the mode of error detection.
Lonmf:9td parityrfequnM's. 66 or 132 bits, and longword ECC requires 78 or 156
co.ififil?Q.h~ing to 64-bit and 128-bit wide memory respectively.

:;·;;\\illli/li!l[\~,-~l:~~=: ::: !~!:t~r0:!o~k~i~:~e~~~ory
\ri.f.~rs to one.\vidth of DRAMs. It may be implemented using SIMMs or by

: =: :;: =:=======·=· ·

{ ~~11:... A.ii·~~! :~!e:!i~~~ ~ef=~~~ !e::ib:~~e~::~!~::~~~!r
8
. ;; j (jj

;c;;~ ~~:ri!O~b~~~!~:h::~~~~J=~~:~di!°c~:r;~r~:~,~i::d 1:p ~e~e

...:\\{=!:_=::wn~:t~1071-CA chip has a pair of RAS signals corresponding to a bankset<'ijj~j#.RAs_l and memRASB_l. Each bank in a bankset should be connected to

Digital Confidential 3-19

.·.:/\:}~:?;:;://}:: .

~:}:·:·::::::::::::.:-:.::::·::::::···::::'.\~}·.·.

:):~~~?:::::;::·. .··::~(If(:::::==:-::=::=====:
.. :::;:;:;::

one of these RAS pins. If the bankset has only one bank

.::::::::::::=·

.:·:·:-::·: ...

QfJf:\JLii;

should be used, and memRASB_l should be left unconq~~~~\~[\\::\:::-.. ····:·:::;:::;:~t::\:~:::t::::··.·.
Figure 3-3 shows the memory organization.
'i~: : :~ :;~;:;: : :-: :t\[: : [·\_[· · :.\)\ :)~)[t:~ ~.\: :.
:
..
..
·
;
:
.:_:~-.~.-.:_..~ ·-~-~:·'.::~-..~
·.;:::::rr::\t::itt
..:::
__:···

.::·:.· _:: .: :;_:

:;:

:_::.

:;:

<i)ll!!;l;ll'f)fo.·.

Figure 3-3 Memory Set Organization

-:;:;:;:;:::;:;:.·.·

1) Each Bankset has a pair of RASes, memRAS_l<B:O> and memRASB_l<B:O>.
2) With 64-bit memory, only memCAS:<1 :0> are used.
With 128-bit memory, memCASl<3:0> are used.
3) memAdr and memWEL are shared by all sets and subsets.

.:.·.:.;; ·····
.·.·.·.·.·.·-:-:-:-:-:·:····
.·.·.·,·.··:·:····

·.·.·

:;:;:;:;:;:;:;:-:-:-· ::::::-·-·.·

memCASl pin that corresponds logic~W// :-:-·-:-::::;:::::::: :::;:::
t I
rd . D
d
"dth f t.......
.::::::::
··· ··
o ongwo <J>. epen s on w1
o ·.:~_r_::.~:_(t<
.. :::::)\/}:
memCAS<1--------

·.·.:·:·::}~:'.:~-:-:-

.·:-:-:-:
·:-:-:-:·:·: ::::::;:;:;::: ... ·:·:-:

:/:::::;::.:···· .:.;~'.:'.:'.<:~> ;:;:::::;. ·.

memCAS<O>------.
Longword CASes

~~~~:!<>:ci~~A-Sed---1.._.__,..__,......__......:)w...::j...:~i...i:(~.illl\~m;;i• i~ s·;:~~~i;:.l:r'" ·
together by memRASI

memRAS_i<n> - - -

memRASB_l<n>---t

memRAS_i -----4r--~~~
memDTOE, memDSF ~L.£'.Ullfil2[t

Bankset 8, VRAM only

...

W-03289-TIO

Bai.i.ltl~\Qff,racfin~1cs

3.2.2.1 Memory
Each l~niotY:\:li.i.~~t.4nu$t conform to the following.

• ::&W.iat.h: All"':~H~;i;blhk~:;ts in a system must have the same memory width.
.·:-:·:.:·:·:·:·:·::::::;:;:::;:;:;:

...

• · :::;:::Bmiltst:::.The banks in a bankset should be identical in DRAM size and

.-:<: : :\;\:_.!:\: ~(. :::::'.:'.::'.:::'.:"_::..... sp~Mt~\.::·\ll:·l\:1·:\::::~t::::::

:;:'\\\,::\J::Longwotd\Wtltes: Each bankset must support longword write capability.
]§]fThe 21071~CA chip generates longword CASes for writes. For banksets

+; \]; +·· .. ii V~i:f~~::!~~:f !!~· i:bi: ~b:!!~::· ~~h!!=ti~::~ld receive a

3-20 Digital Confidential

Table 3-3 Longword Number to memCAS_l[n] Corres~P!~!n~e
Memory

'<:t::~:it@?ltt>:

mamCAS_I

Width

<0>

<1>

<2>

LWO
LW2
LW4
LW6

LWl
LW3
LW5
LW7

NC 1
NC
NC
NC

128

LWO
LW4

LWl
LW5

LW2
LW6

1NC: Unused

•~!!;!i:e:i::~~l=:!t!i~b:~~~~!:ary.

A detailed descripti~H::::~f:::tb~J~~~k;~£~,:~~ij·:·mv~n in the following sections .
.·.

3.2.2.2 BanksetO.. Bank.$.b\,.

··::::::::::::::::::::··-:·:::::::·.

·::::::::I>·:i:= :::::::::::: ..

······.:.-·······

· :•::::::::::::-·

~:!:::~ thro;:gw·~~t7 ai~fr!I~~ for DRAMs, and have the same

• ~::s~i~i;;;:~!ljtt,:;,,!!>af
cii,i~~ ;.:;:~!t!':.tci2, 10)
J?RAMs

addres~jng:?foF'\~:::~s
are supported. Typical expected RAS-accesstime is/5.tfns t6.{iOO .:riil CAS-before-RAS refresh is used to refresh all

banksJt~:ll!fim~l,~fuieoj~~f·

• ~-:t~-TllJ!b_:i;,s:t=:11:=!~ ~~ :i ~~fre1::~~ fo!~o~s
./{JJ~pding on the depth of the DRAMS used.

Each location consists of

. :::stm~;t:w· 16 bytes in case of 64- or 128-bit memory. Table 3-4 lists

supPQrM:Qtbw.ikset sizes, and the possible DRAM configurations that can be
tcFg~j~j~fiiese sizes.

Digital Confidential 3-21

Locations
In Bankset

Bankset Size
64-blt
128-bit

IM
2M
4M
BM
16M
32M

BMB
16MB
32MB
64MB
128MB
256MB

16MB
32MB
64MB
128MB
256MB
512MB
... ..•

:::::::f

·.·.·-:·::

. ::/\:::::'.::/\~\/{~~~>
.·:·:·:-:-:;:;::;::·:;.··:-'.·'.-:·:····

...

<·:··

3 2 2 3 Bankset8
A single, fixed bankset location f.O.tYVRAMj::::ijnJplifies the support logic and
reduces CSR bits. As bankse~[i)PrQYides ffM'.tt))))J.::[ltB to 8 MB of VRAM, more
than one VRAM b/:lj~~ is rii~:::~~~ltt:~.~..
·-·-::::::::;::;:··

":·: : : : : : :;: : :·

•

VRAM Type: 128WJ(b .:J.b!., 128 "kl8#)$f::@.?.6 kb x 4, and 256 kb x 8 VRAMs

::.!~~.}~~,~~~!,-~~;;:;,~~: =::~1:~e~~ ~:~

expected RMlWa~~~¢~~.-time·l~Vitn~URAM port of the VRAM is 50 ns to 100 ns.
CAS-before-RAS)fefresh is used@<??.

•

~~hU~~~:/~AP. h·:~e

Bankset 8 Size:
1 or 2 banks giving a total of 128K,
256K or 5..l?.ftHi.4.4r.~ssabl~~FJ.9.~iltions. This provides 1 MB, 2 MB, or 4 MB,
of ~::j~~Hf&irg~~:)nepioeyF2 MB, 4 MB or 8 MB, for 128-bit memory;

3.2.2.4 Supponed ::l~<>,l·!!§1MM!!:i:j·j::
The 2l.Q7VQ4.J~ijjjfsuppif:ts industry standard 33-, 36-, 40-bit SIMMs. 33and a§&'.M.t s'fivJ.M.~[)in~~Ji~~if when longword parity is the error detection mode,
anc:Jn49.fgit SIMMi@m~Fised when longword ECC is used. The organization
of}f~Q.J.~F~.-4 allows for a number of DRAM sizes and widths to be supported .

. . · ;'.~i!f '.l;l;\!t;~-~!~o~~~'::!h~d~e !ls~~;-~~1;M~~!n~e~=~=ave

.................:;::::::::){@q$idered:;:liflii.]iankset with two banks, and the corresponding memRAS_l and

+;11!1~~~ :: di~~RASB_l C~ be used to select between either side of the SIMM.

3-22 Digital Confidential

3.2.3 Memory Address Generation
.::::::::::;::::.·-.

The programmable base address of a bankset m.µ$,tii!~e aligrti@.:::m;:Jm~
natural size boundary. For example, an 8 MBJ;l.·~~t must stiirl.%:9\h an

!r:a::i~~~d::e~~ware allo~&?ifhole~ii!i)il!W?' with badly
.)~~~~~~\(~~~::::. ·.

·.· :-:-::::=- ::::::)\;:;::::::;::

This section describes the generation of :r9W:J;tnd ~Jiii;ijjij.i'~d.d.resses from the
address originating on the sysBus, thatd~~m'tb¢\ppysicaFaijijf~ss PA<33:5>. The
21071-CA chip sysBus interface decocl~~::::~lfo&i$~i.i\:t.9:Jnemofy space and the
21071-CA chip 110 space. The physi.~.~l:]iddres-s'ei.Ut~~~hf:ed by the 21071-CA

:::::~~:r::s:ll~-~O=:~r<33:5>. For memory

;~;

writes, the write buffer provid~$ttbe initiaPiimi.mof PA<33:3>. For video serial
register loads, the agqr_~ss
is':'di:fl!~4::Jp.temaityh/.
···:·:·:-:::;:·:·
·:-:-:.:-:-:· ·-·-:-:·:········
.

Each bankset has iFP:tbgt.~.:mabrn>b.~i!::@d~ress and size. The incoming
physical addres~js com~ig}jp'"·parall~UW:lth the memory ranges of all
banksets pres~#t~:yp~pendihg::9p.rnb.~ size "of the bankset, a variable number of
PA and base addf~~~4~it~ froni:'tq~·iQ$8.>are compared. Table 3-5 describes the
base address bits ahttHt.b:~\::§µbbankbi#tor the allowed bankset sizes.
····:::::::::::::::::::::::;::::::::::-.-

Table a-s

e.!!~i:A9~!!:!.~:'e8p!rison

Compared

Digita! Confidential 3-23

:::::::::\::\:::\:::::·.
,:::!l!l::::::11::·:.

Note ----~~--~~~<{\/
BanksetO through bankset7 have a minimum size_ ,:4$:.l!.:IH~IM~;:;:::·\;\\;\:rni·:_f}?
bankset8 has a maximum size of 16 MB.
_.):::J\.:·:ll·jy::········:·::<\:i:~[j:::.\::.:.·il!:::j·\:][:::it>·

The row address is designed to be

inde~l~tm~!fai9fme~:~ and

the selected bankset. The path from PA.2:l:J:a?:i:mt.(fat}le row4i.daf:~$~ is flowthrough to minimize RAS assertion delay and<fiijnf:p4g~ modMl~tency. Row
· ::::;:;:::· ·:::::::;:::;}).:.
..
address<ll.o> always equals PIA<22.•ll>.
fi
··:·:::::::::;:::;:::;:::::::;:·:
:::::::;:-.

;.:-:······

The column address depends on the wjqtlj::::~t\m~m1ory ·.filii.Hthe number of row

:i~~u~~~~s &::i~:~~~3;8~e~lfJ:1al~f~: :r:~a:i!':
0

per bankset.

..:-:.,::.:.:::.ii....···:·:·. ·.·.·

.,.,,,,::::::;:::::•::•:··

\:;'.:}/~; ::::::::{\:::.

::::;:.;.:::.:-:-:-·

Memory
Sn_ColSel

Width

000
001

64
64

011
000
001

64
128
128

011

128

.-:·:-:-:-·-·.· :-:-:.:-.

J~. 12

,/::::ix1J0~r.·_:.1_:;·i~-~:_:._:_
_

-·<l.'lU:l:>'•

. ·: : : •':':':::::::::•:=:::::::::..•

,::{_:·:.::ff:~o.~:~p>:::::\:{}

:~A~,22:13>

PA<x,24,12:3>
PA<XX,12:3>
PA<27,26,23, 12:4>
PA<x,25,23,12:4>
PA<XX,23,12:4>

~/{\

:::-:·:-:.:·:'.:·:·:·:·:. ··.·.·

·:::::::::::::··

·:,,,,,~6•~a~t:=:81i;·

S8_Co1Sel

:'::::o::::::::::::~i.:Ii>,:,.

··:6:::;{:::: . :.:.::::::;:::::....

:::::;<·:·:·•'.·.·

. . . . .. . .

, di10.tt ,.,. <It\,,·

,: •:%\:;:i!i !:i!l!±6~
<: : l lil!lilil!i!l! :~i~t: : .

;~~ii~r~

·:."\:\,,, PAdi;~i~!~k
12,12 '''" /{{j:\\PA<25:13S/
12,10
'"\)fl:\jjpJ.\~~~:13>
,.:,_:·',:_.o·'_·,.:,'·:_:':,r·',:.:,·.:,=::··

Row,,~n<t:::i1H~\R:=:~d~t!!8 Decode for Bankset8

Table 3-7

11\;
.. ·:··1:·_',::_.',:'_,_:::_.::_::
1 V:

•.

·.·.;-: ·.·.·.·.·

100.....

·-:·

....,.,.,.,.•:-:::a~A<24:13> '''<:t:Jr:A<26,25,12:a>

:,:,·,··':_,:':_.'·,·':_,'·,·':_··:·:·'·,_.•·..:_.,·_,•._.,_.:·.:··:.,.·•.,:_._.,·.•.,_•:·:

~:::::

10,10
99

'.\\{:'.}?:·... '

64 .., ,'\{_['_[:_:_m_\·_:[:_:.?_!:_: _., _._·~-~
128
128
128

3-24 Digital Confidential

·· 10,10
9,9
9,8

Row
Address<11 :0> Column AddresS<11 :0>

xx,<22:13>
XXX,<20:12>
xxx,<19:11>

XX,<12:3>
XXX,<11:3>
xxxx,<10:3>

xx,<23:14>
XXX,<21:13>
XXX,<20:12>

XX,<13:4>
xxx,<12:4>
xxxx,<11:4>

.....::::'.:'.:'.:?:~~}\\\::;:-··

.. :::~:~:~:~:~:~::::::::::;::::::::::::::::::::::::::::::::.
·-:-:·:·:·:·:·:·:·:·:·:·:·:·.·.··

.;.;.;.:.:·:::.. :.... :.;.:-:.:-'.·:-:·:::.............

3.2.4 Performance Optimizations
3.2.4.1 Memory Page Mode Support
·"' ' ' ':' ' ' ' ' "' ' ':':':':':·.·.
·":':': : ,:,:,~,:, , ,:,: :,:.:
The 21071-CA chip supports page mog~(9.il.f:~hi:Hm~morY:::b.inks within a
transaction. Page mode between trani§A~tfoihhi.~i!ii~qpp.9rted on DMA read
burst transactions and on memory.-:w:ritJf:~ransactiiji.li~:::ft

The following are the features of::~lii:!li.~~:::~µppo~':a''.by the 21071-CA chip.
·'.-::::::-:.:-:;:::-·.-.; ·:-:-:-: ..

;.;:·:·:·:·

•

A refresh transaction nev.~i.k~l.rts in·":pagi.l\:l@gde. If any memRAS_l is
asserted when t4.~t.:refresh\tm.P.~~~.tion is ·s'&l~tted, the controller waits for
the duration of.:~ji::~ pre~Hi!m~i]~~fore doing the refresh.

• A video traq.~acti~~··'4.~~·!:::~tai1;~·:ifi;ii:j~g~" mode. If memRAS_k8> or

::m=Ji1~;~f!!~SIJl~~~~it~d~:::~:; i~}:~:~:~g the
transaction. ··' <::::::::::::?:/::::'::..·

··:·:::::::::::::::::::::::::::::::::::...

•

:· ::::::::::'::::: ;::::,,,,,.
·-.::;:::-·

A memory read tr;A~~¢.t~P:ik:Yvill start in page mode if the preceding

!:~:c~11111fh~:'j~ft:::si~~::et~ !~:::!~u:;~~i:=::t

transa¢Sijp are{tbK' sam~ as that of the previous transaction. Furthermore,
a mem9r.Y::l:re~d::]nitia~id: by a CPU transaction (read or partial write) will

~iJii:Jll&:lt·d:~e~ =u;~i::;;~:~~~ni!~~e;~:~:~he

.::tY.PUf:" after ii"''DM!D~'iid burst.
' ' "'"· ... • :::::,:\i.:]iji.mqry write transaction starts in page mode, only if the previous
... ·•·•·•·•·•· •·•· ;jj \
=~=:8t:,.r;~ ~:;::~i:~si:~::ibank

ill!!; =•:ea

·'·"'"'"".""". ··

; i i

of the

<~ij;llj~n the ab~~~::--cases, the transaction will not start in page mode if the

\m~mum RAS width counter has overflowed. The RAS has to be precharged

~=a:s:::ni::a:::~~t start in page mode may or may not have the extra

''''?H~~~~WY of RAS precharge. If the current transaction is to a different bankset
'''th.!nH~he previous one, the RAS for the previous transaction is deasserted, and

afthe same time the RAS for the current one is asserted.
Digital Confidential 3-25

...
··.-.·:::·.·.·:·:·.·.·.·.;.·.·.·.··
......
..
··.·.·.·:·.·.·'.·.

.·:::::::::::::::::::···

·:::::::·:-·:·.:·:·:·:::::-:\:::;:;:···

-:·:·:·:·:·:·:·:

-=:::t:If' ..:·:·,.:·:·:-:·

....
··:·:::::::::::::::::::::::::;:::::::··
·:;:;:::::::::::::;:;:;:;::··

: : : : : : ·-·.,.·

3.2.4.2 Read Latency Minimization
·.·.·.;.:-:·:·:· ·
f?t::::;::::' :-:-:-:-:'\_,:i;::;::
In order to minimize the read latency seen by devicesJi#j:j{lg:::=~Y§l.~us<~::::~l~:::::t::r
memory controller performs certain optimizations in tti~!)ii§ttr~~l~.!ion:s'.;are
selected. In general, because writes can go into a q~~iCWrite biift~fflr¢.3ds

:;::I~;~£tE:::~:~E:h;~~s~i2~~-;,~u::~~::~he
.....

•

··:·::::::::::::::::::::::::::::::::::::~·

Following a memory read initiated by a CP'QU~n.~~ctioi{:'()ij/the sysBus
(CPU read, or a partial write), the 21071-Ck'clWP.:]i.9~§. not service a
write from the write buffer for 12 111~m¢~k:J!ycleif'al,ijijijit}.le last read data
has latched, unless the write buff~ii:i$.:::mlU:Ulb.~ reashi¥for doing this is
that there is a delay between the 'jq#.}pletii:nj:i~it:th~ read by the memory
controller and the initiation of>mf:l9.m:~r read ··Bt.(::mi?sysBus. Servicing a
write from the write buffer ~qq}4:::~~~:J@t~ncy tct'the following read. This

~~:.it~ti~fil;t~~-f~1~~~i:~e::~~~!::
·'.·'.·:-:-:

•

.......:.......

····.=:;:::::;:;:::;...;:::;:;:;:-

The second $ituatio&Dwb.mt~1Jhe m:&~it§>"controller holds off servicing
writes frow/jt'h~Lw.rite HUft~r·]$,twhen Hie sysBus controller knows that a
memory reid'i:~~:iJ~lt,~~y to b~':::n~AA!~:::PY the current sysBus transaction. This
happens on Dl\ifAPf.~•d~tduring'fili:Efcache probes, or on CPU reads while a
bank address compat~:::~:~:,.}~tprogress. This condition is called Read Decision
Pending (~Q:Jlk:'::::·. . ... . . ·
.-::::::::::::::::::::::::::::::::::::::::::::;:;:;..

··:-:::::::::::::::::::::··

~i:;:~~: :1s~:1i,~4 pr~'iii~usly,

the writes are only held off the write
if

a.2.s Transactidn::::scfiii°du1eE:1::

The.. J.libry::'161f(~¢.~:::aiii:· memory refresh, cache-line reads, cache-line writes
W1d:]~b.ltl registet'::load~fto VRAM bankset8. · The memory controller has a
s~Hi.iiili*-tthat prioritizes transactions and selects one of them to be serviced.
t11:':'si.ll1~~lJransaction is waiting for RAS precharge, and in the meantime
nQ1tnE~r-hli:h'i#::priority transaction comes along, the scheduler deselects the
·.:·-·----· cfib~eh transaction, and selects the higher priority one.

;:;::::::~:~µ.te 3-8 the priority scheme.

3-26 Digital Confidential

.·.-:}~~:~~(~~)~:::::·

.·::{i]l//}tf)::\:::.:-:·:·:·

·"'.·::·.·.·.·.·

.....·

:·:·::::::::::::'.:~:~:~::;~:~:~:~:~:::::· .

Table 3-8 Memory Transaction Scheduling
Ref.
req.

Read
req.

WBuf
hlt2

Write
req.

WBuf
full 3

0
0
0
0
0
0
0
0

1
1

x
0

x
x
x
x
x

~ . :::t:U:::}~t>::.:-.

0
0
0
0
0
0

x
x
x
x
x
x

Video

req.

:=:=:·.x

./!tt:J::

:::::::;::::::::::::::=::···

x
x
x

x ... ""\t7TQ.(l}}\:
0 ·:'}}\·

<f:\})\

:=::)L/:))::\f:\::· .

1x : Don't care

x":Refresh
xRead
"x<\)r:JH~"
·::::::::::::::::i\r: ...... x Write
x Video
x Write
0 Write
xNone
xNone
x
1 None

"::::::':Jt\0/::0:::\::.. x

·=-::)/"

WBuf hit: Read address matches bufferijailwriiMttt:tlt::=:=::.
3 WBuf full: Write buffer full.
·::/::<):::-'."
"====\tt=\:c:::\. .=.
4RB: Read burst. Hint to

5
6

~~~y in rea4l\li..llm<.>de.

"=:::=t:t::::::~it:>

RDP: Read decision pe~~ft ffi.nt to\M~~j~@)t~ad.

WAR: Wait after read. iJ~M~:.:'.:~.::. . :·~.=.:.:~.: ..·:.:.:..~:·.. =s.. =.".·i.·gn. ~f5lil\:iillt=::::.
·.:·:·:::::::::;:;:::;:::;:··
.......;.;.;.;.

...
·:::::::;: :-:.;

...........

3.2.6 Programmat>fe::>l,!mer.Y iffr.t:gg]:>::::

The memory contr~J't~ti.ti-?m~chin=~::::iij4uences through all the memory
transactions. On memofy.Uf:~ID!\~d write transactions, it has to communicate
with the 2107Jdij#(¢.}Pp.s so::th.=itWd.ata may be latched from the memData bus or
driven onto,=:#bij.@MMAP,~ta pus 'H@pectively. All memory signals are generated
on memCllU{#How¢.y~F c.Qm~ands from the 21071-CA chip to the 21071-BA
chip are s4nt:i:P:r. -~~C'iocl®.li:~clk2R). Since the sysClock cycle time is half that
of the Jµen1QJJ.fatn~· 210.1~tf:DA chips have to be informed which memClk the
data ij~tto tM:i)~~W.J!~g:j~nW=This is done by sending immediate and delayed
co~mi.ijps. lmmmiUiti4fommands require that data is latched (or driven) on
th~faji:fihpemClk rising edge, and the delayed commands require that data be
.: : : : =: : : : :\:=:::JatcHiaN6.i%drl.ven) on the second memClkR.
·==; '.;=·";.: '.'.'.'.: : : :::=:::.;·;;;ll!:l.@. m::{ij)··l5ntrol state machine is actually made up of two separate state
. ./{')//"
\mi~hines ---OfieH.s the master, which does all the RAS, CAS assertion, and

!~1·~;>. · i•:~~e~!~~~h~o~~=[i ~~~=:e~=~ ~~~!~:t~:nts !:i~~~~e~te

··-::::::::?:;!;~;};~;~;}!;:}\;!/~~\jj\61- write metnory data. The read/write state machine is started by the master,

·===:·m:t:T\\!:I%::~1.1d then it sequences independently. Each state machine uses some of the
·==::::t=. ::·=;:·pf:9.gr:~mmed timing parameters to generate the corresponding memory control

·"<s~ij#ils.

Digital Confidential 3-27

Since memCmds have to be sent to the 2107iiitJ.l:i:¢.b.jp§_ on ~Ik2).i~:. the memory
controller synchronizes the start of all transactioifiKtc{:¢lk2.lt This way, the
memory control signals track the memqeyfg~t~•t.accordii!g::i~~:fothe programmed

=~:ie;~ ~:=~~:~;!': ::~~!11' ~!1•r,1~=~:y~~:c~:a~~ or
1

writes do not have the extra delay,::::p~iji.P,~e the ~6rr~~ponding requests are
generated synchronous to sysClo~~~;,::1:1;:]\[!JUt::::::..
· ·::;::::::::·
-:-:::::::::;:::·

3.2.7 Presence Detect Logic

.:::::~\.;.:J:}::

:·:-:::-:.:····..

·.·-:::::::::r::'.:':·:)::::'.;}\:::;:·.

The 21071-CA chip .§µpports·'Y&w.mitt.b..e statri~\br 32 presence pins into a

:~s~!n~fft:4;~:.:1~~~~ITl~~~~:~~u;h~~ster

the module

As soon as thEf~~t@rm1l syri~fitP:fi.~~~:4.. ver~I~n of reset deasserts, the loading
process begins. ·::Fil$.t~::':tm.~. data''i$::JQ.i.a,~9 into the shift register by asserting
memPDLoad_l ancf:P.U.J§mg::::m.emPDQi.k. Then a bit is loaded by toggling
memPDLoad_l. Either::;&ai,~::;·gf:::m_emPDClk may be used to shift memPDDin, as
memPDDin is::$.ampl~d wherhmi.mPDClk is stable. Once all 32 bits have been
loaded, me~:Pl.).Q1k.:::$t~P.s ancftli~fpresence detect registers may be read. See
Figure 3-4_.·~_.::_:_::_.::_.iif ·· ···::::::::
······::.:. · ·
·····.·.·

3-28 Digital Confidential

Figure 3-4 Presence Detect Logic Operation

Clk2R
int_reset_I
memPDClk
memPOLoad_I

-':;:=: = :::::::::::::..:::~:::· ~:\\:::::.

··::::=t:ur·

;______j.r~~~~.....,L..~__;,~~J-~~:~:::;::t::}B::·:-,......·~:·:·::~::i4\_4:::::;4:::::4:::::4:·:~:~:::-·::·.~_t~~~~~'--~__;:.__~_,1
..

Load Bit 30

int_reset_I
memPDClk
memPOLoad_I

Load Bit 28

Load Bit

a
LJ-03564-TIO

Digital Confidential 3-29

Part

Blts 1

/load 2

clk3

74Fl66
74Fl94
74F195
74Fl99
74F299
74F322

8
4
4
8
8
8

/PE
*Sl
/PE
/PE
*Sl

CP
CP
CP
CP
CP
CP

74F323
74F395
74F674
74F676

8
4
16
16

: : :::

SIP

/CE
/CE
/RE,S
/OE
/OE

CP
/CP
/CP
/CP

*Sl

*PE
R/W
*M

/CS
/CS
··. .·.·.·.·:·:·:··

1 Number of presence detect pins suppo~~-- ·:.

·.. · · · ...·· .:..,.,.

=~~~_!,. mm:;w,~~t b;~i)'."°dule.

4 Pins to daisy chain data.·.J..n:'.'".·=.to
...·.•.

-:,::::::::::t\f::::t::::::::,::·.:·:···· . . . ·.·:···

:Pins to daisy chain to ri~#.ii'~::mrste~··:&i~\~fi~~pDin.
Pins to be tied hig~1:.,..
.. .·.··<t/{:':':,.,.,.
·. ,,., , , ·.·.·.·
7Pins to be tied lowl\{\:·.
.,.,.,,':':':::=:.::::::::::-:-:-:·:··..
:·:::;or:::·::::;:}~/:}::~:::::::::::·.:·.

·-:-:-:·'.·'.·:::::·:::-:;:·:-:::·:·:· .

.·.:::::{(\:}}:::::::::-:.

3.2.8 Video Support LC:l'g·i:C,)i ,:::,:::H:::::,.,_

.,//?tt:.

'\t}::·f::·\rn::t>>··

·:;:J.ijl:.li full seri~P:fegister load, the entire RAM row specified by the row address
't:~§:Jatched into the serial register. In a split serial register load, only half the
!Iif:O"w is latched into the serial register. The MSB of the column address specifies

.• , ::+m:::rn·:rn-::\_l··J·'.: \?whether the upper/lower half of the row is to be latched.

.,.,.,.,.,,,J:··:.=::·1ij,':'wrms of timing, a serial register load is identical to a memory read
''''to:::ili?:inkset8, with the exception of memDTOE and memDSF. The data on
memData<31:0> is ignored during serial register loads.
3-30 Digital Confidential

··:-:-::::·:·:·

·::::~\~:~:~:}::::::::::::·

. )}}{{\{\){{{=:·.
/:(::::~:'.::::-:

.: =': : : ;:;:;~;·_

.. :::::::::::::::::::;::::::::·::: ..

ji:1=1:::=;r:t:·i·:'.:i1~.---=.ij:tr===

:\r:::::::::::::: . ::?\!/:=..

·::::::::::::::~t}·

The 21071-CA chip provides the logic and control to perf<~.rm. . f~If anal(l~kli~::fi!\:l::::?
serial register loads to the VRAM bankset8. The Videc~tJ:?.i.i.mi~\1?9infi~iBJ$ft}:?

~~r:!d;1~i:h:~~a~~r:~: ~:: ~~~~a~~~-~~}'B::
subset, row, and column addresses for video shift r~m~t~r..loads. · · ======\{\;: =-=·

Following a vFrame_l assertion, the Viq~ij·:l£raipe P~lf.ilf,1li:j$.4;;ltched i~to the

~~a~~~ :~~t=~l=d~~-~::! :i1!Jlli~~~l•ii°; ::;:~~,
0

the row address in the VDP is incremented (moa=::5j[:g)::l\(.)::=POint fo the next row.
In case of overflow, the subbank is incre.m:~b,~P,. Th~qf~lµm:q,MSB in the VDP
is toggled.
=<=;~:~;::;=::}'?:::i:iJ~\liiilt:====··.
· =·==-: : : :;: : =·=·
Following a vRefresh_l assertion, a spl.jj!i:~eri;Ff.~li~lr=Joad is performed at the
subbank and row address indicatedi!llFtne.VDP. Thi%otUmn MSB in the VDP
is toggled. If the increment over#.~wja\\:(i~:::n~w coluriin MSB equals 0), then
the row address in the VDP is.Ad.~mentii.!l!9:mY:Af bankset8 has two banks,
and the subbank is n9t toggl~9.W\J.fiijle row ·a:aQfiis overflows (mod 512), then
the subbank bit in W~#Y.DP is"''loggl@ljf..the subbank is enabled.
The memory contr~jj:~f::==c,~!\:~e ~~:::ib.jl:!f.~i::::~ysCik cycles to complete a serial

: s~~:!:Jll,~~P~~·-~~~t:~ :01:~~=~~: !e s~:!:~s;e~uest
8

may either overrilii,@ljimfirst reqiie.~#:)),f:dt may be ignored.

Simultaneous assertiafi~l=·~~-l~Jfr~IneJ':i~d vRefresh_l can cause one of the
requests to be
whil~:'k~h~n~ther is lost.

Digital Confidential 3-31

Figure 3-5

DECchip

21064
128

Cache/
_Addi_.._.__ Memory
Control
DECchip

21071.CA

• RamDAC is a trademark of Brooktree Corp.

3-32 Digital Confidential

LJ-03427-TIO

DECchip 21 on,l:&,Pfll11111mer's
<<::;:i:·;:·:::::::::::::\,:::.

R:eference

··::::::;::::::::::;:;:::::::::::

...
··:·-=:::::::: ~/}?/}·

.::)f\{:)~t}t:·

:J:mti~\t {._l:_,_:~_,_:;: ·_:·: :_r_:.·_:.:_:.:,_:.:,_:_: _:_:_;,_·_:.: .·.:·.
::::::\:?·

4.1 Register Descriptions

:!s1t:f:~~e;=~:e~s·,~~\!~&1:~~~s<~~t:>V::~=~CSRs

read-only registers :'l~iij:ld J~~~ult iiFijlqpf:@.j~_table behavior reads that are
nondestructive. 9nly ·.zet.~~jjj:ib9µ.ld be''\vflt#itl to unspecified bits within a CSR.
Only bits <15:Q;:!H\9.fJ~ach ·c:Sld~ntd.efine&fbther bits are undefined. CSRs are
initialized as sii'it~P.i:::~P. the->del~l,~9:::g~scriptions.
'·'.·:::::::::::::::::::::::;:;:;:::-·

·-:-.:::{{:~:~:}}}}~\-:-.

····:::/:~:~:}:··

Table 4-1 DECchip 21d71ijQ.\:J~egister Summary
Address

1 8000 0000 . .:::::::::::::::-:::::·>
\/// /\.General control register
1 8000 0020.i·i·:::i:.f
' :::':.
(fltl:leserved

! :~~;;tij[;~j;!tll!;: " ';!iii'~.,,:,~e::~c status register
1 800<tQ().80
1 ~)QQAO
1 ·'~j\)9:9.§:9..

.· .·.·.,.,:.:.:.:.:,;,;::.;,;

. ,., , ,. .

800Er:Q~l~j\jr:::~::::':?:. ..
...
·.·. :·:-:-:-:-:··

:::::::::=::=--

Error low address register
Error high address register
LDx_L low address register
LDx_L high address register
Global timing register
Refresh timing register
Video frame pointer register
Presence detect low data register
Presence detect high data register
(continued on next page)

Digital Confidential 4-1

./~~:f~(t?t~f~}~:::-.:.. '

.·:·:·::::::·:::::::.·.:.:.:=:·:=:·:::·::::::::::::·

..::~:}{}/:·

Table 4-1 <Cont.) oeech1p 21011-cA Register summary_··.·.·.··_:_·.::_,_,_.:_:_·:_:-_:_:_._,:_.:,_:_.,_._, _:_::_·.··!···.····.111.
Address

Name

·.:.:.:::.;:;:;:;:;.:-:-:-:·:·'.-:·:·..

i!l l: : '.l lr'~JV
·-:::::::;.;:::::;:;:;:;::.;-:-:·: ...

18000 0800
1 8000 0820
18000 0840
1 8000 0860
1 8000 0880
18000 08AO
1 8000 OSCO
1 8000 08EO
1 8000 0900
1 8000 OAOO
1 8000 OA20
1 8000 OA40
1 8000 OA60
18000 OA80
1 8000 OAAO
18000 OACO
18000 OAEO
1 8000 OBOO

..:·: !{~}\:-:-.

.. .· :·:· · t:t) ..
:\:{j§\%\:j:?>::-.
1 8000 OCOO
··::::::::::)::;::::>,\":::,•. Bank·::'ff'f;jh)irig register A
1 8000 OC20
?t\:~Mk 1 ti:&Hng register A
1 8000 OC40
·.·.:·••··
<'t)3.iQ.l(2.. 'liming register A
1 8000 OC60 . -::;::}?/ t=>:
13m)ij'::s:: timing register A
1 8000 OC80/\}\/? :::::=(_ ···· · .•. Bailk<4 timing register A
1 8000 OCAO·· · :
J'ffBank 5 timing register A

~ ~go~ ~g~lll,Jl&uii; t{iJi\\/
Jtll,t::
;~:: :::~ !
Bank 8 timing register A

1 800Q\i:pgoo ·:.::;::::::::;:::,:::::;:::::,.:.
:;::::=:=:::=:=::-

(

.. ::=:::::::: ;'.)~f

·.·'.:=:t\tt?t?r.. .. ::::::::::::;:;::=··
·.· :-:-:

l-:$!mt:q~po

.,,,,:r:i::::.::::1j:.:::1:::::1::i:,,:g::::~ll·:Itt:=t:,.
.,.,., , , ,;,;: :·. ·.·.·.·.·.·:::::::\jiJ.1i=jpoo oE66{{\1tlii:r
..:{~~}:::::::::=:=·

'\l\8000 OE80 ··:::::::::::::::

.,dJa®o OEAO
\(://)))::::::..... ·.· ::=::::)Hfooo OECO
·::::::::::::;:::y:::::::::::• •:-: t/{f' 8000 OEEO
:::)':_::-::=::·.::_=:::::

-:-:.:.:.:-:-:-:-:-:-: ::::::::;::::;:;::::·

Bank 0 timing register B
Bank 1 timing register B
Bank 2 timing register B
Bank 3 timing register B
Bank 4 timing register B
Bank 5 timing register B
Bank 6 timing register B
Bank 7 timing register B
(continued on next page)

4-2 Digital Confidential

Table 4-1 (Cont.) DECchlp 21011-CA Register Summarxu=Jtt\,,.
Address

Name

1 8000 OFOO

Bank 8 timing register B

··:::::::::::·:;:::::::·:·:

·-:::;::::: .•.· ...

:·'.·'.·'.<;:·.

··:·:::;.·:;:::::;:;:·.··:·'.·'.·'.<···:-.

4.2 General Registers

·'.·: ·.·.·.·.- ...... .

The following registers are in the 21071-CA ~hfP~:::f:ii~~Y conti:6fithe sysBus
state machine and associated logic.
.. ,.,., , , , ,
·:=::::==\:/::=:'(?:/ ....
"'.:\'.}'./{:~){:'.·

. . . .. ·.·.·.··:::;:::::;::::..

,,,,,,,tin::fl>fti:':\,,.
.,,:::::?'.
The general control register containsJtltus "irirl,14.t.i~m which affects the

4.2.1 General Control Register

::::a::n~::~e:_i:~e·Jl;lftlilii~~j~V
1

Figure 4-1 Genera•

eon1ro:ir. =.i;.:=, [=~=~.:=.iP1st.: l!l l l l1 t';t>:. .
.-:::::::::·.·.

..J~t .. 09

...:/~=.;~.~j.~ :.:tr.~ :.:~.~ :.=~:. :=:-:-.

··::tf{~·:;:;:·'.·'.·'.;'.;'.;'.:-:·:·.

"BMW}:R~i~ ::t:gs

·+

:::::}=:::·.·.·-:·:·:;:;::-:;:;::=::·.·

os"''\{ij4

$1 8000 0000

Reserved
----sysArb
------Reserved
..___ _ _ _ _ _ _ wideMem

._____ _ _ _ _ _ _ _ _ be EN

-_
- bc::::LongWr
bc-NoAlloc
..._____________
: - - - - - - - - - - - - - - - - - be_lgnTag
- - - - - - - - - - - - - - be_FrcTag

~;:zcrzz:==============

A
be-FrcV
be Frco
--.........,~~~---------------be::::FrcP
i:;;;;;;;;;;;~;;;..----~;;;.;.:...--------------- be BadAP
~--------------------ReseNed

: - - - - - - - - - - - - - - - - - - - - - - ReseNed
W-03094·TIO

Digital Confidential 4-3

Table 4-2 General Control Register
Field

Bits

Type,
Reset

sysArb

<2:1>

RW, 0

Description
DMA Arbiti$tiffiihnode. DetJfiiiri~s arbit:r:~Piw1
sch~ffi~/(qf~~~us
transEl'.ctions.
·: :;:-:-:-·-:::: ::::::-:::
.;-:·
'·-:-:-:-:-:-:-:-:-:- _./?~:::-..
.·-=:\} ~\\} /'.-:-:·.
Value :<\&:Y~~m1
~~~----------------------------------

.Ali Iii;;·.R~~!it

<id!:f': ""<:+::::::mr~f\~trong priority
..

......

;.:.:-:.· ::::

·-:·:·:-:.:-=-:-:-:-=·:Refer to SeCtitii{ 3.1.1 for a detailed
· -· ·:::::· ::::::q::qj~pp_on of these fields.

MB-..

Reserved

<4~:?\::·

wideMem

Z.::·:·_:·_:_::_._::_._:.:::_::::_i·_:_,,_..:::_:'___:_:_··:.:

· : : - : : : : : ' \ / \ : : : : .....: ........

-··:::::::;:::::::·:;::::;:;:;::-:··

RO~:\\~\i:i]ftt:::::. . Wide\~J~ Size. Reads the status of the

.::nrn:t>". .::::-:::::::::::t:::. ·-.:::::::e:::ii')\jllj·jjjlljlilllf.t~~~ i~lsu~i~~n~~~~~~ i} ~4tt7ts
"·:::·<it\:'.::: :-: .
''.•\\flij~ .
... ·.··

RWsjQf:\: .. ·.

bc_En

Bcache Enable. When clear, the Bcache is
·::::::?t?t:{\:-disabled and the cache state machine will
not probe the cache.

bc_NoAlloc

Bcache No Allocate Mode. When set, CPU
writes to cacheable memory space will not
be allocated into the cache.

bc_LongWr

Bcache long writes. When set, two sysBus
cycles are required to write to the cache
data RAMs. See Section 5.2.4.

·:·····:·:-:-:-:·:·:······ .:::::;:..

··.·.·.·.-··.-.-:-:-:-:-:-:-:-··

···::::::::::;::::-:-· ...

Bcache Ignore Tag. When set, Bcache
probes will act as if the valid bit was
invalid. All tag results will be ignored,
(and any victims will be lost.) Tag and
address parity will be ignored. May be
used to fill the cache with valid data.
(continued on next page)

4-4 Digital Confidential

Table 4-2 (Cont.) General Control Register

l'Ype,
Reset

Bits

Fie Id

Bcache For¢~f:fmi.-.. When se~A~J.;.mtacache
'V:iUJ>e probe'l.\\fW.fYt¢.ims, and the line will

RW,O

bc_FrcTag

:·g~,li=~:~~~-lii.~~~~~ ~~l~;

used ·aij\tlj~~f~ contTOI~f#\lthough the line
is invalid~W.4X~.uming"'bc_FrcV is reset), ·
th.~ . data is. :fo~de.~.[tP,t<> the cache, and will
./P~mi~itW;µed to.'tli~\)lf:P' as cacheable. Used
:/if.9.J.f~Y.§~c testirijfof the cache RAM,
)'/Jirid foi:]l'@.:lijpg the cache by setting this
.·.:-::::)l{l,>it, cleariijj]jfaJ.rrcV, and cycling through

bc_FrcD

<10>

bc_FrcV

<lb:.:-.

!ll!ll~ll1B;:;::~=:
i:t~:;c;~
mt}W11Ube.:J:iet on the next cache fill.

RW,O
.·.·. ·· : : -

R'Wtpi\j\]\ \ \ t: :=: :·:·. Bc~~hJ\\~g;~e Valid. When set, the valid
···-::;::til\)(\\:bit will be set on the next cache fill.

. }}?\::·

<;~r d\ tty~.?

bc_FrcP
bc_BadAP

~lilt;J;~ ::.m:t~~; ~~~:.,~~ ~r. parity

<t;:;ti:tS>..

::::;::fi.WJ.6ll: ··:.:
Bcache Force Bad Address Parity. When
. ,,.,.::-:···:?]\>::set, the tag address parity will be loaded
··::\U(t?it:::\:,
:,:,: :-: :· · as bad. Independent of the bc_FrcTag bit.

·-::-:·::::::::::;:;::;::,::::

.·.·

<15:14~U:.·\::·:llZ:::::.

Reserved

4.2.2 Error and

.IJ§fillil! §yrt~~

The error· ~~\pi:~bstic::::ii,j.tus register contains read-only status information
for di~gnos'.~¢,;~N~ti~'r·ror ~ttif analysis. The occurrence of an error sets one or
more :~m#~t. hit~:::(P.~liT.4.1$.f.f, bc_TCPErr, nxMErr) and locks the address of the
err.:9t-.}4.fter the. '.:ad.df~Wls locked, any additional error will set lostErr and will
not\]iff.~&.,. the address or other error bits (bc_TAPErr, bc_TCPErr, nxMErr) .
.·.·.·. f:ll:t::::;:;,Ple.2iriig!\ii:!i:J!f the error bits (not the lostErr bit) unlocks the address.
:::::::;. : :;:·:;: : ·: ':': ;:;: : ~i'!,_i :\;i !§~:. Fi~;~::::11~:·\.iJld Table 4-3 .
.. :{({}\~/

:-:-:.:·:-

·.· ::'.:::·:··

::::{:::::::::::::::::::.::::.
.-:-:-:.:.··:-:.:-:-:-:·
.::::::;:::-:.:::::::::··

Digital Confidential 4-5

Figure 4-2 Error and Diagnostic Status Register
15

03
02

./:\

\' - - - - - _ _ __.J

1&~1!111'\'''ll!ll~\'i··h
...............
~
_

?>=:·

$f:=:~~:::!~9-40

_..,....be

TAPErr

·-:=<i·:)::::):::~~ile~~Err

,___·=·.....
=·===·~=·=·==~=-===·~=====,;,;,;=·:···~=·=-~--"="':::~::=::=jfufaCause
....____..·_.·::;:;.;,;;:'::::~:::::~:::=,;;;.;:;:::.~=:~=-=·:·~-..·==:vlccause

L----------··::::,..:::::·~=:~-:::::.-;,;:=:=-:~·:-:-:~:-.~- cReqCause

,____ _ _ _ _ _ _ _ _ _~...,_-_ _"....
.:-:-:..,..·:-:·..,.:-=<..,.::::::....,::::::...,::::::""":::._Reserved

::::;;\;~;;;;;;;;;;;;~;;<\~;~
··:::::::::::;:::::::
pass2
' " - - - - - - - - - - - - - - - -.....:,""":·:·:...
·:·:·:...
::·="""·:·:·:~-~,,__-__......__ ldxllock
, . - - - - - wrPend
W-03095-TIO

FieId

<0;:::::::::· . ::::,)._j.jli::·~~:~?,o ·.:,::::::1:::::::::::::11~:a~=~~~ :i:~!~t~~!c:~::r~~t

lostErr

·:·::t{{:L:::: : : : ;: . ··

ad'dress was already locked. No address or
cause information is latched for the error.
''\fj\}. Cleared by writing a 1 to lostErr.

·=:::::::;} =:::::: ::-:-:-.

bc_TAPErr

Bcache Tag Address Parity Error. When
set, indicates that a tag probe encountered
bad parity in the tag address RAM. Set
only when address is unlocked.

bc_TCPErr

Bcache Tag Control Parity Error. When
set, indicates that a tag probe encountered
bad parity in the tag control RAM. Set
only when address is unlocked.

··:·:·:·:-:::·:·

4-6 Digital Confidential

Nonexistent Memory Error. When set,
indicates that a read or write occurred to
an invalid address which does not map to
any memory bank, CSR, or 1/0 quadrant.
Set only when address is unlocked.
(continued on next page)

~ .·:··.··'·.· •.Jti 1 111 t1~1i1; ·

::. :. 1.:1•;.: i·.;1:· · :· · ·=· ·=· =·i·..-· '

.•.·.:•.•.

i1.·.•..

.·: =t~~:::: :': :':~;~:i::·;.·.:.:: :·~.:,',i,i·,~·.:~:~: =.:.·.·.,. .
Table 4-3 (Cont.) Error and Diagnostic Status Reglste~ttt?t\t=:..
Type,
Fie Id
Bits
Description
Reset
dmaCause

<4>

RO,-

vicCause

<5>

RO,-

:::::::::::::·::::::=··

:: : :: : : : :

:·:·::::::::=/}f{}

\=tt!tttt?l/

DMA Tranda~ah:::Caused E~&J~:[1:~en
~~J:pdicate~:::t;~~~~:~)i~J>c_TAPErr, be_
='1$.fEm::=:Qr nxMEiifW.i.iw~used by a
DMAAiinsaction. Look&bWith the error
addre~iF].Ji.l}kv~lid .WlijijVii error is
indicated"=oijJitlT:A.P.Err, bc_TCPErr, or
memErr.
·>:=::::;}//\:/:,
.·.;-:-:-:-:·:-:·:·:·:·:-:·:·:·:·.

··:::::;:;:;::::::::::::}~~?

./!Wvi¢.wii!i~~ Cau§i~VError. When set,
ttdndfoatea/that=:a NXM error was caused
.-.·=-====j}}J>y a victiii#vnt~==·transaction. Undefined

:!illlii~l!;~~!~!~~;,:

,(f::::1[:[::rn:::~\..
cReqCause

meffi·i~:::)=·

RO;:;:..::::::::. =·{;:>""· Cycle Request which Caused Error.
·==:=::tlllfllp..dicates the DMA or CPU cycle request
"=" ....:.f/pfi).~::which caused the error. Copy of either
·=-=q~b.jfopuCReq or ioCmd lines depending on
the DmaCause CSR. Locked with the
error address. Only valid when a error
indicated on bc_TAPErr, bc_TCPErr, or
memErr.

Reserved
pass2

Chip version reads low on passl, and high
on pass2.

ldxlLock

LDx_L Locked. When set, indicates that
the lock bit for LDx_L is set, and that the
next STx_C may succeed. Writing to any
CSR or I/O space location clears this lock
bit.

....
.·.·.·
:-:-:-:-: ::;::::::::::::::;:;.

<15>

··- ~@}}~j)"

RO,O

Write Pending. When set, indicates that
valid write data is stored in the write
buffer.

·-::::::;:;:::;:::::::
·-:.:·:-:-

:-:.:-:-:-

·· · :t4.2.3 J@g:}Enable Register

: ':/:jC~-.>t":: :======..:::{\·\~i·,\r:f.he tag enable register is a read/write register, this register indicates which
"=\:::::rn·!·l!li![jj!::::. ::=::·'{bits of the cache tag are to be compared with sysAdr<33:5>. If a bit is 1, the
·=·::=:::=X::J¢9rresponding bits in sysAdr<33:5> and sysTag<31:17> are compared. If a
·.··:::/'ffi'~{\~~:::O, there is no comparison for those bits, and the sysTag bit is assumed

Digital Confidential 4-7

j;~i!\1~! i'i~1.i_: ._-'.i :.:~.~.:·:~:.:.,·.~.-':~:_.i.·,·:~'·_:~i_,·_:_:~

. .;1Ji!1lf
~.~:_.:;_~.:-.:~_-.~ :~:}.·_::':~:~:~_:·~_:~_:.:~: ./t~~~~{/
:....::· .. ..:: ...:. . ... ... :?.::_:_.::.:.·
__

_ ·':.l.·.::_ ·.'.[·.:·._:_,.:.
.'·.i_:···
.. ...

.·',:_.·::_:i
__

:.i.:'..

.{}}}

to be tied low on the module (through a resistor). Bits <lJ>.:;.!? in-:thJ!l:lm§.tAf\:))::);'

::::tn~=~::· t:: t~:gi:;:::sb::: :;i::41J~!!llf.!'lii:::i\]J]!)jlJW
8

implementation which does not allow the ·full 4 Gij{Qi]~~cheablcr'1*t:m9.h'
to be installed may choose to mask off upp~r bits dttf.~ln,. and save4faving to
store a bit of the tag address in the tag ~a.ares~. R.AM?mrn:t:j!iilil\::::-.
To construct the tagEn bits, refer to . Th·J::·~~ff.\v~.lue.Tibi~::jii2:4 and
Table 4-5. is the value shown in Table 4-4 (ba~eiUontthe caclUFsize) ANDed
with the value in Table 4-5 (based on the maximtirtF:~a¢h~ab.le system memory.)

~::h::Pi!:;i:0~s~:i::o:r!~~ .;!~~l~1\~ nii&il,W\i
.. : :~: :~: : : : -

of 1GB of

··::::::::J::::::1·1:1.::::::tt:\):::.

.. ::::::::::;::~i}?~:-:{;'.:.

1111 1111 0000

ooox ANDed:::l~Lu::rn,:~:::::::i:t:::

:~~ ~~~~ ~~~ ~~~~•lµt i~~~;-;;
See Figure 4-.3, Tal!fl,' 1(l;lld'lbl~•k
'
.-:::::;::::::;=:;:::::::::..

... :;.;:::::::;:::::;:;:;:;:;...

··::::::::..

·-:::::;;:::::::::'.;'.;'.-:::::·:.·

Figure 4-3 Tag Enabl~ri!AJster · :·: : q:J:t[\[li i: \ l [\i:m: >:,._
·-:·::;:::~::::;::::::::::=::::::::::::.

1f·:::::J:(f/{osL:.
oa
·:-:::::::::::::::::::::::::::::::::::...

·.·.·.·.·. ·.·.·. :::::;:;::::·.·.

o/':\::~f:\&L,. 04

W-03096·TIO

4-8 Digital Confidential

.. ..

m::::

ilW~l i ·':·~ =~.=·.:=.=:.·~:=·:'.=~.~:~:.=~

;;t1 •. li.1.l t,=: .i.:.=: .=· .=l.·.=:·.:·.:,·.'.=.:,=.;..=;.=.=:.=.:.=:.:·=..:=..·.:.. . ....=.·..,..·.:=..:=.=.='.=·.:'.:.:'·.=.·= ·= ·= =}
i!lli· : : }11t
/JY
: :· : : : : : : : : : . /if}/
·.::.,.1..

Table 4-4 cache Size Tag Enable Values

: : :1: =: ·: : : ·: : : : : : : :1: : : : : : :1: =·

Compared
Cache Size
tagEn<15:0>
0000 0000 0000 ooox
1000 0000 0000 ooox
1100 0000 0000 ooox
1110 0000 0000 ooox
1111 0000 0000 ooox
1111 1000 0000 ooox
11111100 0000 ooox
1111 1110 0000 ooox
1111 1111 0000 ooox
111111111000 ooox
1111 1111 1100 ooox
1111 1111 1110 ooox
1111 1111 1111 ooox
1111 1111 1111 lOOX
1111 1111 1111 llOX . <31:18ifJ}i\.,.. 256 Kifcifu}if
1111 1111 1111 111x . ::::::jlt> <31:t7';f'i[\[\:]\1f][i]g,~ KB c~~he
·:::::::::::::::::::::·

··:·::::=··

····:;:::::::::::;::::::::::::::::::-:-.

. _:::::~:::::::~::::·. -. . .

·-:::::\/??'.~'.'.'.'.'.'.'.'.'.~'.~~::._._ ..

.-:-:-:•.
.·:::{~/t?ff{(}::::.
'·'.·'.·'.::t/:(\:=··
Table 4-5 Ma!,m9m==-Meniof:Y~lt~m~~ablEfValues
tagEn<15:0>
··::::::+%::·::··::::::.: r:M~:Ptnpare'd)( ?::'Memory Size
1111 1111 1111 lllX

<:·:Sc23.ih1>

4 GB memory

~~ii iiii iii~:::~ii~= =-=-= -=-= >==::~:~~~~llii1m>· i g~ :::~~

00011111 nii?iiix : .:i:i=. [j /? <.g~:11;;.==:=..
0000 llll llti:fa11Xftt> i27·17>
0000 0111 i'ififa.iiX:if/ 'i*~th 7>
0000 00111fiiiitfx==·
. :Je25:17>

1 !¥~:~~ ~~
~;~l~~f~'~11lli!
OoQUJ)Q()(tOlll lllX
<22:17>

.::::f':::1it:i·1:..

:1:.: : 1 :t1b:~:::~~~l.l~~dl}~~i
oooo. '-060.oFiil:x

.·.;-::-:-:·:=::::::::::·:::·=~t:loooo

,:/}//?

·\9999,0000 oootFohx

!; ;\·~~~~~~~~~~

··::::::=:::=:::=:

: :ili ;.:·:.l.:·: :.: .=/:=:==·

~~~~~~~

<19:17>
<18:17>

~~~! >
7

512 MB memory
256 MB memory
128 MB memory
64 MB memory

=:::
=

8 MB memory

~1 MB :::~~
memory

512 KB memory

~:~::::;

Digital Confidential 4-9

4.2.4 Error Low Address Register

.-:·:·: : : : -.·.·.

The error low address register locks the low order bit~;:::Q.f·:tJli:::~y~µs
that caused the error that set the bc_TAPErr, bc_TCEEft~".o'i~:::hi.MEXT::. bit in
the error and diagnostic status register. If a victind~id cause(f=tf;;:::¢.rror,
then the victim address is not latched; ra~h~r, the<a&?tti~~:. of the tra'.fiiaction is
latched. Bits <15:0> represent sysAdr<~Q.;$~k This i~mitird~:. read-only. It is
not initialized and is only valid when a e'ffof}~\~~~~~:cated?t:::::::::l:::=:n:r:::::.
·--: : :. · : : : :. -.. :. .
·::::::::+u::t:"
See Figure 4-4
··:·::::~:~:~:~:=:~=~~;:;:;:;:::~:~:~::::.:·.

Figure 4-4 Error Low Address Register
15

10 - 09

-::::::::-:-:-:·::::-:·:::::i/?\:t::-:.
06

\~{ o~:-:·:::1:1~::::1.[::1:,~:e~t::.-- 01

W-03097-TIO

4.2.5

~1~~%~.~llltilR ;'\ddress Register
. . J! ))'jWJ!l'\• lle~:rtllll~itre: ~~::s:r:P!:e:~;!~~~:;!.t~:s;e~~~:: is
}fi.®.-only, and"it is not initialized.

4-10 Digital Confidential

Figure 4-6 LDx_L ·Low Address Register
15

: :
.

4.2.7 LDx_L High Address Register

··:-:.:·:·:·:·:::::::::::·:·'.·'.·:·····

The LDx_L high address register stores the high?Jf:aiitb.it~ of .the locked
address. Bits <12:0> in the register repr,~~~Qk§ysAdtl<$.~:~g}?. This register is
read-only, and it is not initialized.
. :.:· :::::::::::.·<=:=:::::;·='<>=
·-.·.· : : ;=;=;·
·.·.·.·.·.·.·.·.

See Figure 4-7

<::::{~/}~~ :::::::::::{:::::.

::\:}

·.·.·.·.·.·.·.··:;:::;:::;:;::::::;·

·.·. ::::~:~:~:~:~:~t=::::::::;~}::.· .

.:-:-:-:·

....·.·.·.·.·...·

·-:.::::/\~:~{:~:::·

.·.-..:::::::::::::::::.-

·.·.:::::::::;:::::::::::::::::::

......... ........ .

··:;:::::;:::::·:::::::::::::::::::::::..

4.3 Memory Regi;tlf:l!!!!li!li.::.:-:m>::=-.
The following r~gi$~rs ··~=iFfili~-:ig:}Q7.1-CA chip control memory configuration and

timing. Eac\glj~p}i~~l.MiJ.f.memoey}has one configuration register and two timing
registers. T.b.\~{::gfob~Ctiining regl'ster and refresh timing register apply to all
banksets. ?.m.i:·
viq~q:\)frai#.~\!:pointer
is used for video transactions to bankset8.
·'.·"'.·'-'.•:.:::···
·-:·:;:···:·:-:-·
·····.·.·.··

4.3.1 Video :::l~~.rflll!llll!b!~~\\\[IPgister

ThEt:Yl'lio frameA19.iit~th~egister contains address information which points
tq:JID.:~:::liginning oflhe" video frame buffer. The video frame pointer is loaded
·.·.·.··.··· ·====-=· infiktb.~f!Jd~o display pointer at the beginning of each full serial transfer to

. : ; ~n1111 r~:!'iltii:::: :.initialized.

Digital Confidential 4-11

Figure 4-8 Video Frame ·Pointer Register
14

·:::::::;::::::::::::::::"'·'::::::::;.
-:·:·.·.·:·:·:-

Table~ Video Frame Pointer Regl~lil; Vi
FieId

Bits

vfp_Col<4:0>

vfp_Row<8:0>

~{(}::

'. ··•·•·•··, ''.(%"
.·.·

D~~i.l~ta~

<4:0> . ~\.ftW;:::::q · . : .:.:. ·\}\lj~eo Frame Column Address
..
"':'<ftte<.>.mter. vfp_Col<4:0> are used as
.....
··.;.···
:-:-;.;
. ::::::eoltimn address <6:2> for all serial
. ::::;:::::_;;;;::-::::· :.-:·: : : : : i-JIPster loads.
j~J~;P.> R.W/@\ :\\\:::::::. Video Frame Row Address Pointer.
.·.·-.:::::::::::::::::·
··:::::::::::::rn:=r·· Row address of the start of the
·::::::::=....:.:...· .·.··:::::::-:-: ·.·.·
frame buffer.

vfp_SubBank

Video Frame Subbank Pointer.
Subbank for the start of the frame
buffer. If the subbank is enabled by
setting s8_SubEna in the bankset8
configuration register, setting the
vfp_SubBank bit causes the 21071CA chip to assert memRASB_l<8>
instead of memRAS_l<8> on full
serial register loads. vfp_SubBank
is ignored if sS_SubEna is cleared.
··::::::~:~::;~~~~~{~~:~:~:~{{~~~~~~~~~~::::··

4.3.2

Prei.ldlt:. Dete~t-:'"[~;, Data Register

-::/{l::::l:~J)Jf.~~::::~f.i~l~J~.etect low data register stores the low order bits of the presence

iiit66f.#.i.il9Jl that was shifted in after reset. Bits <15:0> in the register
·'.:\fipresent datil~its <31:16> that were shifted in.

.-:/}}\{~ I\{~j~\~~}q~t~ct

After deassertion of reset, it takes 148 system clock cycles for this data
to become valid .

__________________________________________________

.:·:::::::::::~!~~:!;:; :~~;!;!:~; ~j!~ '.:i'....,.....
~:~::-:·:·

4-12 Digital Confidential

See Figure 4-9

~il lfif\;·1 1 '.jiJl\l_.:_=:_i._._!_:_·_: _·.·_.:_.l_J_.:.~:_:.i_i_

Figure 4-9 Presence Detect Low Data Register
15

-: : :~:·~ \i [j· 1:1 ~-g~-

'._::_:_::.::·_y·

·-:::;:--

: 't:il.!i':.+> : t)\l1il~llt•;\'.h.l~1
·>:

8000 0260
W-03102-TIO

.. .··.·.·.·.·

··:·:·:·:·::;:;::::-:-:-:· :{~~=:::::·.·
··:::::::::::·:·:··.·.·.·.· :-:-:-:·.

4.3.3 Presence Detect High Data Regist1r:r : : : : : : :

·-·-: : : : : : : : : : : : :;: -: -

The presence detect high data registe£l'~~¥i~_,:\th~dtjgh -~iJa~~ bits of the
presence detect information that waS.:~b~tted frP~iif:?r~:~et. Bits <15:0> in the

-----------:==...r=:-=v Ndti]:;;,;,;,:1,...mt.,.·:t,..::::::....,._ _ _ _ _ _ _ _ __

~c~=:~~~l/;J':~:~t''"iil'!;.,~lii'~1ock cycles for this data
.;::::::::..

See Figure 4~fq!:[:ij:::·:·:: ····

·.·.·.·.·.·.·.·-:-:-:-:-:-:-:.:;::::.:·.

·.·.·.·::::::::::;:;:-:.;.;.·.·.·

.·<hitffog}: :-._08

·-:-:.:-:-:-:.:-:-:-:-:-

or::: :m~·

:. ;!~i!F :;i;i'1~:\Wlr1 .+:

$1 8000 0280
W-03103-TIO

Eil\::m~m~ry bankset has a corresponding base address register. The bits in

.-:::::(\!]i:\\:\[\1\it41.:tis·.;.tem\~litHH·e compared with the incoming sysAdr to determine the bankset
8

· ·•·•· · : )\JHilB~.b8;t~ll6~:~~:t:e:s~ o~:!~~~s=li~~:!;.i:!~fn:ethat

.;:::\:I?l:'"
i

}iJf.iHcompared depends on the size of the corresponding bankset. Banksets 7

i,lll~ :~~~5~i~ t~!tr!~~!~~:~;::d~n=~~=~~:~:s~:. ~~!B.
1

f d

·:- \:.;·::}:j·:·?::.:::.:::-;.,::·~~n contain video RAMs, and has a minimum size of 1 MB, has the same 11
·..'">/@llP:it>f~eld, where bits <15:5> in the register correspond to sysAdr<33:23> and
:::::+iY:!~r<22:20> are compared with zero.

Digital Confidential 4-13

···-:-:;::-:-:·.

·::~:~:~:~:;:;.::tfi. ;.;:-·...
..::;:{\~:~::::-:-·-··.·.·· ..:·:-:-:·:·:-

:f/f:/
. f ttf\.

.-:-:-:-:-·-

·::::::t::=::::t?ktt\::::::::::::

_./~{~[(/

· : -: : {:}: ;: : : : : ·

The base address of each bankset must begin on a naturaJ!y itl:~:d;i,Ldf'/
(so for a bankset with 2n addresses; then least signifi~~~'tP.~ti4nusfb~\\:J.~fi)l?
Bankset8 must be placed on an aligned 8 MB boundr!!:.f.J¥:::blk::.i~~~tl~;:;::::~h·an
or equal to 8 MB.
::::::\\)dLI'..
":·:-::::::\:///\\:·
.··::::::}~~j~}:):::

~~:;:!~i!a~z;;dE~~ :~!::4f1ed ci,!11~~;~~;:!~;.n
··-:-:-:-:-::::;:-:: ::;:-:::::;::..;.

See Figure 4-11

": : :-: :-: : : '.:;: : . .

Figure 4-11 BankSetO Base Address Register :J:t:\:.:l::\jl_:\::\;\;j)::::::::.
1s

!t I r::~:::::1::::~. [·11~~-·:r

.~:::::::::A·:\i:~..

,o_e.,eM 133=23r

I :

. ::::::::.:...•...::::::::::::::::::::._.::-:::;:;:· ...
os :/~:}::··03 ":o-:i:::;:::;:~f/:'.:QIL ...

0 ..

0800

!l[lll; iitii;\'/;lii;~':...

.}~\:;:;._.

4.3.5 Configuration Re,9,~er_s

LJ..OS1~TIO

·.;'.;:::;:·:·:::;:::::::;:;:;.;:;::;:;.

··:\~:}:::;;;::::::;:;:;:::··

·=·:;:;:;:::;:;:;:·:

::\/):}:{::;:::::

. . :-:::;:;;:::Jti\ . .

. :·:-: : :.

a~~E.i~l!!iii~~;~~~t~~r~;:~rl~~~:Wr
these. bankset8 is fiie:?VRAM. banlt''i'i:lid supports different minimum DRAM
sizes and configurationsY~~r~f.9.re, its configuration register is different.

With the ex<;~ptj~ij·l.lij£:.#b.~ ~;11a]:ih~f,:· this register is not initialized.
See Figur~::ilt~";;:.,!_9!~_::_'.!_J,_~_:::
7...
·.·.·.··:;:
... :·:·;.:.·

\:f~}.;.··

····:·:·:·:·:···

·:·:·:·:::::·.·:::::::::·:::::·:

Figure 4-12 ,~,:set::\lf):l:Sg,~!~~g~~tlon Register

·.· : : : : : : : :

t~t::;1~:ji\::.. 11

.. ·.~:t~~j@ff {~)~~{:::··
10

W·03105·TIO

4-14 Digital Confidential

Table 4-7 BanksetO Configuration Register
Fie Id

sO_Valid

sO_Size<3:0>

Bits

"fype,
Reset

Description

RW,O

<4:1> RW, -

··:::::::<f::\\'t::::t\:::::::.?OOO
··-:,:::::::::i~::::::i·lill~:::·
boll.

O111

lXXX
sO_SubEna

PA<33:28>
PA<33:27>
PA<33:26>
PA<33:25>
PA<33:24>
PA<33:23>

Subset

set Size

PA<29>
PA<28>
PA<27>
PA<26>
PA<25>
PA<24>
PA<23>
PA<22>

1024 MB
512MB
256MB
128MB
64MB
32MB
16MB
SMB

Reserved

Enable Subbanks. When set, subbanks are
enabled, and determined according to the
previous table. When clear, subbanks are
disabled and the memRASB_l pins will be
asserted only during refreshes.
Column Address Selection. Indicates the
number of valid column bits expected at
the DRAMs. Used along with memory .
width information to generate row or
column addresses. Memory width is
determined by the wideMem pin. See
Table 3-6 for more information.

) :.:]yri~pecified ColSel values are illegal.
.

.. . ·.·.·-:-:-:-:.:-:-:-:-·

-----------------------------------------------------------------

Digital Confidential 4-15

W-03106-TIO

:-:-:···

fliii~ittr:liJj:J:lii::]t. . . ·.

Table 4-8 BankSet 8 Configuration ···.·.·.·.·.-.·.

·.·.··:::-·-·.··.·.···
··:-:-:-:-:-;.·

·.·.·.·.·.·.·.·.·.·.·.·.·.:.y-·.·,·.

FieId

s8_Valid

<0>
.·.·.·.·.

s8_Size<3:0>

RW,,._O{J::r ::::::;:::::v.~mi.tJ.f.set, all parameters are valid and
.·:·:·:
f}' ':.:::::17:::;::::-._::-.

aceijijfi.t9:~kset8 is allowed. If cleared,
no acc~~s to bankset8 are allowed.

::(~~~b:::::: -~W,<f<~'{\\j\\\.:iJ\IJl-Jl-1-\\.:~id:~ ~~~:::J~: :~c~f~: :~~:~in
·-::::<i.j/j6mparing the base address with the
·::-:·:·:-::::::::::::: ·:·:-:-::·.
physical address and for selecting the
··..;.:-:::·:·:-::·:·:· : :;,._ subset (if sS_SubEna is set). CoITesponds
··-=··:·:·:-:::@}>to the total size of bankset8, including
:<.=t\·\:\\i\j\\\jl\Jjj:j\\j\\\i·,..}\::
··· subbanks, if present.
::::::::_::·=::\:::::::-: ·-::-:·

s8_

Compared

Subbank

PA<33:24>
PA<33:23>
PA<33:22>
PA<33:21>
PA<33:20>

PA<23>
PA<22>
PA<21>
PA<20>
PA<l9>

Size<3:0>

o:xxx
1000
1001
1010
1011
1100
1101
1110
1111

RW, 0

bank set
Size
Reserved
16MB
BMB
4MB
2MB
lMB
Reserved
Reserved
Reserved

Enable Subbanks. When set, subbanks
are enabled, and determined according to
the table above. When clear, subbanks are
disabled and the memRASB_l pins will
only be asserted during refresh.
(continued on next page)

4-16 Digital Confidential

Table 4-8 (Cont.) BankSet 8 Configuration Register
Field

s8_Co1Sel<2:0>

1Ype,
Reset

Bits
1

<8:6> RW, -

Description

Column AddtM~ifSelection. 'tHdi&ites the

'lt~~~'"'~~~~at

row m\@.l~~:i.address~~mm~emory width
is detenruijij~]b\the wid~Mem pin. See
Table 3-7 fordnorednformation .

s8_Check

RW, 0

<9>

.tt$.li1i,u~cc~~Ml·:!¢.h~king. When set,

tHticce-~f~~tmmksetifwill have their parity
ECtf~h.ij~~~~..as with other banksets.

{b}pr

····:·:·:·:·:·::;::·:
·-:.:·'.·>:·:··

. /://{{{When clearWP.ifity or ECC will not be
/IlfkFlH~~}ted. Wheifclear, bankset8 must be
}ifi:t====·=-=:==::=:tmi.PP.M. into noncacheable space. Only
··· . . . . ·.·.·
banuetS:=has this feature.
=(l: ~lil:\ ij:~: : :~!:l\= = · DMA:::mit~es to this bank should not be
··==:=:::fttlfIJ\::====perform;d when error checking is disabled.

_:::::::::::~..

···::::::::::::::::::::::::::::::::::::::..

....

iunspecified Col Sel.. value~. ~mf:~i#.k

..:::::::;:::::::::::::::::::::::::.. -.

Each bankset has t;J<tjm@~itr~gist~f~ associated with it. These registers
contain the ti~iµg:::P:~raniet~f§fif:~qµired to perform memory read and write
transactions~::J:flj:~=::f.tjrffi~t of theHtHning registers is identical for all 9 banksets.

~ ;::;r·=~·-~i:~·:::~a:~;:::::i::~~e:S!:r~ho:~~ ~I
~r:~!!q\G;ifore setting the corresponding bank.set valid bit in
, .!lr£!!~~~~~~e:s:~!tt1:;~
~:~~!'~:~:~~:!~~~ch is
value. The programmer should be careful to subtract

.:::::=:::: Irn:Iill!)l.4ded:=:tQ!~:~J.Jibm:>grammed
··==ft?= ..-:. \:~::::=\:9#.t:,.this V'il#.~flft9.m the desired value before programming it into the register.

-==<:'.:=:i!'{:i':·
<·: : :=: : : : : : : :
:::=::t.::?:?:\'!\>:,,.

·:=::IA!i: descriptlMithf the parameters also indicates the corresponding DRAM
:t!i~~,meter.
.
0
ffi: B~fer to Section 4.4 to determine how the timing register should be

\ i!l jj'~:@ii)>rogrammed for particular memory transactions.

Digital Confidential 4-17

See Figure 4-14 and Table 4-9
Figure 4-14 Bankset Timing Register A
15

. :::::<<;:;;·)"i_~=~~~=~~}~P
.___ _ _ _ _ _ _ _ _ _ _ _ ___,,,.,..·.·.·.,...
·:::·:.:·:··:·· ..

~,;,;,;.;,;,.;,;,;,;.;,;,.;

··"'sa=ColSetUp
Sa ColHold
SS=ROlyRow
_ _ _.....,...,....__ sa_RDlyCol
- - - - - - - Reserved

'::j:::::::::i::::··
·:·:::::~::~:~:~:~:~:~:~:~:~:~::

.t~~t~f?f~~}~~t~t}~:~::::.

W-03107-TIO

:'.::::::::::::::::::::·: ·.·.·.·.·:·:·:·:·:·:-:

Table 4-9 BankSet Timing Rf:$.:"!J,,r ~-'?\~\\i:\:l.l·i:I:j._'·:\!i~t:r,,
FieId

. ,~i::()~~]t):i.W, l~:"'::::::::f':j:'::rn lkow Address Setup (tAsa). Used to

s8_RowSetup<1:0?.:

. . :::::::::::::::::;\}::. . ·
.,,,?:/\\??':::":...
s8_RowHold<1:0>

,.,, , , , , ,:::--· · ·
·.·-:-:-:-:-:.:-:· /;~;}/:-·- ::::::::::::::::::::::::r:::;:::-.

··::<:::@::::::~~;j$.: ': .:R~,'''i'~:·j,.:/>
'"\'::

······

/)
.,., , ,., ·:·: : : :;: -:-:-

)? >t? j\\j:jjjj\!ljlj\\! ::::::;:::-

s8_Co1Setup~g~ij:;
·.·.·.·. ·.·.·._.;:_~·.:-. .
·:·::::::::....

./\\]\\:)f.6:4~[}
.·:;:;:;:;:;:-·.-.

...:=_::.ii.~~-:~-.i}f?"

.·.·.·.·.·.·.-.·.·:-:::·:;:;:::-·

4-18 Digital Confidential

Row Address Hold (tRAH). Used to
switch memAdr from row to column
after memRAS 1 assertion.
Programmed VRlue =Desired Value - 1

RW, ls

Column Address Setup (tAsd to first
CAS assertion and write enable setup
(t.cwd to CAS assertion. Used to
determine first memCAS_l assertion
after column address, and memCAS_
1 assertion after memWE_l. The
maximum of the two setup values
should be programmed.
Programmed Value= Desired Value - 1

RW,ls

Column Hold (t.cAH) from memCAS_l
assertion. Used to determine when the
current column address can be changed
to the next column or row address.
Programmed Value = Desired Value - 1
(continued on next page)

-~-~~-~}'.}}~

<8:7>

:?'generate memRAS_l assertion from row
address .
Programmed value= Desired Value - 1

Table 4-9 (Cont.) BankSet Timing Register A

FieId

Bits

l'Jpe,
Reset

s8_RDlyRow<2:0>

<11:9>

RW, ls

s8_RDlyCokl:0>

<14:12> RW, ls

···············.·.··

oescrlpt1~~:illl!f!·f·l!::::flt:\[\:li1:i:~: !,!.l:l.j·i: -rn1: :it: : : :.:· :-:·:·:·:-:·:·:-:.

Reserved
.·:·:- ::::::::::::::-:· ""':fH?\iii%>:=:·.

See Figure 4-15 and Table
.;::::::::-

4:f~t
. =.·1.:~r· .
·=t

tf~{}}}~~\:·
-:;:;:;:;:;:::::::;:·:·:;:;:;:;:::::;..

":·: ' 'lJ.:!:.:.:.:.:,f.'~.': ~· .,:.:.: .:'.::~.·

. .:\· ': .:[.'..,\:\,:.::.'r

Figure 4-15 Bankset Tlmlnti[1ae.:;
.;.·:::·::,g·"'-ter
Ef<\i i\)l.!.il!·::,i·.·l·.:·,.'i.\i:.::·.::.::.:::.::.':.::.·. . ·.·
::::::;=::;::::=:·
1s
14
13
12
11
1:0:.. og "'o~tt?~i\: .. os . ::J~i:t\ii\\)*->
0

oo
$1 8000 OFOO

- - - - sa RTCas
- - - - - - - - - - - s8-WTCas
::i;.;..,,,.--------------------s8-TCP
___,.;£tWJillJJ4::~2 +;;.:...--------------- s8-WHoldORow
- - - - - - - - - - - - - - - - - - - s8-WHoldOCol
'------..:,;,;,~..._.........-~;,;.------.------------Reserved

L__

--------......--,;~;;,;.::::_:-:-.,.;;·",;,;;····~···-~--------------Reserved

.1~;~'';!!,~•t~
.;:;:;:;:;:::;:;:;:;::::;::::;:;:::::;..

W-03108-TIO

Reglmer e

· :·":··.:>.:.:.field··:·,. .'.:{:}};:~~;'.\>.,,..

Bits

l'Jpe,
Reset

tl-.:·lv.:· :::::\{[\:;~~J.B.TCas~2~ij~!=l!\!li\\j\\)

<2:0>

RW, ls

··::::::::}~:::::;:;:·:·::::::::::::·.

Description

..... .;.;.;.;-:.:;:;:::;::::-:·:-:·:·:~··.-~
.. ~-~~~~-----------------------;:::::::;::::-=-:··>

"\::"

Read CAS Width (tcAs). Used on reads
to generate the memCAS_l deassertion
from the assertion of memCAS_l. Note:
RTCas and TCP should be programmed
such that their sum is ~ 5..
Programmed Value= Desired Value - 2
(continued on next page)

Digital Confidential 4-19

Table 4-10 (Cont.) Bankset Timing Register B
Field

Bits

'fype,
Reset

s8_WTCas<2:0>

<5:3>

Rw, ls

s8_TCP<1:0>

<7:6>

,:;:::}}Jq9~amrrieijUY..f#W:t= Desired Value - 2
RW, ls ,J\]\\\\\\\\l\QA§9ff:~cha~gJ:::(l%p). Delay from
)\:,:,;=:··· rri'effl.QA.Sll..deassertion to the next

s8_WHold0Row<2:0>

<10:8>

,.,. Write

c&.$.iilath. <t<:As). J~ia:::~~ writes

;\;'[~~i~~f~:n

m¥~;;~~111~11111~e!~::~::~::::-· 1
.·. ·.·~::::~:~:~:=

. .,,,,,,,,,,,

·-::::::fiHOldftime of first write data from first

tdW.Hi.ddress. The first write data is
vali'&\vith the row address, and is
··.''\fjJfl\\:;:,. held valid s8_WHoldORow + 2 cycles
":\}bt\/{after the row address. Used when not
.··::::::::;::::::}i\:~'tarting in page mode .
. ,.:,:·Programmed Value= Desired Value - 2

'"' ' ' ' ' §:'.:'.·'.·':\:::::::·:·:·:-....

:·:·:·:-:-:-:.:·:-:-

s8_WHoldOCol<~::b§l\
··:::\t.··:·::'jj!jj\lj!j::1111.:::1::::::,..

Reserved

::~::{~)::;:::
:·:·

Write Hold Time from Column address
is used only for the first data when
starting in page mode. Write data is
valid with the column address and is
held valid 88_WHoldOCol + 2 cycles
after the column address.
Programmed Value = Desired Value - 2

· :·:·:·. ttt ::{);}/.

::11111.·.lttt:·

. :::~i~~~jl~~:~:::::::::::::;:

4.~,~Z,,,,,.,.~16b@t,\:~:mt.m.i..ng Register

.· ;i~lllfflfil~jlile;~~;i:;:::;:~~:~~l:.a~8f~:;:~o::.!°:!~~mory
:,/{$.~ Figure 4-16 and Table 4-11
····=:::::::::::::::::::::::::::::::::~::::::._:f}:::::::::::::::··

4-20 Digital Confidential

Figure 4-16 Global Timing Register
15

o 1o

\___________ _________) 4,IiI!if
Y

~::]:\t6~~::::::~:·::\i::~:i:1t::::: :.
'l11~1p 0200

r, , : :

···

Al,! lili;f,~: ·~.· ·-·.·:.·\.·..,.-·.·\. ::-.:-,:--::·:-:·. ~!~=~~x_Ras_Width
Reserved

::::::+r:::::::}::

.:::::·=-=-·

.. ::·=-.-:._ ::::::::·
W-03109-TIO

::::::;

··.·

.. <·'.-'.·:.:-:·:

·-·-·.·.·.· :-:-:-:-:-:-:- •.·.·.·.·-·.:-:-.·.

···::::\}}}~ ..
·.·.;.:-:-:-:-:. ..
··:·::::::::::;::-:::··

Table 4-11 Global Timing Register ·>>:·:::::-:-:·
.:::r::·
Fie Id

gtr_RP<2:0>

····::::::::::::::::::::::·

RW, ls

Minimum number of
RAS precharge cycles.
memRAS_l deassertion
to next assertion of the
same memRAS_l pin.
Corresponds to DRAM
parameter tRP.
Programmed Value=
Desired Value - 2.
Maximum RAS assertion
width as a multiple of 128
memClk cycles. When
this count is reached, the
asserted memRAS_l is
deasserted at the end of
the ongoing transaction.
This value should be
programmed with sufficient
margin to allow for the
timer overflowing during a
transaction. Corresponds to
DRAM parameter tRAs·
When programmed to a
0, page mode between
transactions will be
disabled.

Digital Confidential 4-21

,,(::::t:::::::=::·:.:11:-::1)\,-:.

·=\frr=·:·
·.·.·.·.·

4.3.8

=·:===·=::=:=:··-·.·.·
·:·:-:·:·:·:;:;:;:-:·:·'.·'.·:·:····

R::e=~re:":~n:::::rconWins refresh timing i~{-~:~e,1,i;;;;;1~~; ;' .F
1

simultaneously refresh all banksets using CAS-RAS rif.fesK'.:)'f:h~fitqr~, these
parameters should be programmed to the most con.~@Y~tive vaHii)::~~s all
sets.
.. f?'.::::.....
-=:t!Et\:t;!:\:::i:t:\.:\:;\\\/:::-....
.·-=:=::::tr

:~!h: ~:::i:r~:;:~~h~;~ ~~ :i~!T!!~~~~lf~!::!!lll'~ ~:meters
programmer should be careful to subtract thiitvi4,p~:::fnnn th~::::de'sired value
before programming it to the register.
: : : : : : . :. :.:.· /::=:··
.·.:-:-:-:-:-:·.

See Figure 4-17 and Table 4-12

.. :::::(?

Figure 4-17 Refresh Timing Register
15

00
$1 8000 0220

dis Ref
.....___ _ _ _ ref Cas2Ras
.;:::;:::;::: ·.·.·.·.·

- - - - - - - - - - ref-RasWidth

.__·:·:-.::::::-:=::.. ·.·-.:. . . ·.·.-·.___· . . . . , . · · · - - - - - - - - - - rennterval

·.··
'---------;,;,;;:-:-:;,;,;;·:·.···'""'···~:;,o,;,=::::·~··.,,----~~

Reserved

;,;o,,.,..------------ force_Ref

::::::v::::::.l\·:-:-::.·:t>:,,::;.

W-03110-TIO

·.·.:-::' '>::::::.:.::::::·:.:t:\\:....

Table 4-12 .·>:-:-:-:-:-:-:-:-:.:.:-·.·.·.:.:-:-:-:-:-:-;.·.·.·.·.·.·-·
a1tr"-tU1nm.1~g::::R;1•~er
····.-.·.·.·
··-:-~\:\;:;:;::

Field

-:):):y:·

disRef ::=::::

=·:·=-::'.'.':·:'.'.'.1t:\l\\j)\f?'

·:::::::::::::::::=
··:·:·:·:-:-:

::•t•

····.·.·. ·.·.·.·.·.·

4-22 Digital Confidential

Description

3~oj

RW, 0

Disable Refresh. Refresh
operations wiII not be performed
when disRef is set.

<3:1>

RW, ls

Refresh CAS assertion to RAS
assertion cycles. Corresponds
to DRAM parameter tcSR·
Programmed Value= Desired
Value - 2
(continued on next page)

· : : : 1~1:=! : :·.·.::::::::::::::::
·:· · : ;:; ;:;' .:<: _;:_.· _: !li=t~:v

re.tf$~~<2:0>

Type,
Reset

Table 4-12 (Cont.) Refresh Timing Register
Type,
Reset

Fie Id

Bits

ref_RasWidth<2:0>

<6:4>

ref_lnterva1<5:0>

<12:7>

force_Ref

.::'.::::::.:::::::::: '.:::::::::::~:::: ..

···:·:::;:;::::: }\):=:=:·.·
... :.:-:::::-:-:-:.:····
:-:-:-:-:.:-:-:.:-:-: ·.··.·.·

::::::\:

-:·:·····:-·.·.·.·.··.·
··:-:-:·:·:·

4.4 Program~,9=im§'''''l\fllm'q:fY Tfming

::n=~•&t.t!fa~ll:~:a::~:.s~;:~:~:;=~~~cle
ti~:,;,.,··=::j.!:[:!l.@\:::·

· : : : : : ) )!ili!i:!)l:1 · 1:·,·!':1.~)·)1\~:1:.l·): : ): : \ : : :

• .Jifml.it§ystem designer should develop a timing diagram for memory reads,
··=====:wnt'-ihr~freshes, page mode reads, and page mode writes for the chosen
nieHi~f:Y:i[~fmtiguration and sysClk cycle time.

~:if)flt~ti~· is to count the number of cycles required for a particular
?baLrmme1ter.·.,,,This is the desired value that is referred to in the description
the various parameters. For each parameter there is an equation to
generate the programmed value from the desired value (generally by
subtracting a constant from the desired value).

Digital Confidential 4-23

- - - - - - - - - - - Warning

~:i~:~i:!: !~;1:eS::a~a~:::i::~~~!l~-~jP
and the other controls. The two machines stat]:::li~:[i~e same:::ti~iili\jpd
then use the programmed timing to cy~!_e throtigJUW.~t.~ransactiOrit
Arbitrarily programming RDlyRow, J.ljJ.jyCQl, WH6199.8.9.W::. and
WHoldOCol could result in illegal meffio~::::trmi~actiohs~I(··:::_::-·-:-:'"'"
;::::::::;::::{ :;}:::

·-:::::::::::::-:

Table 4-13 and Table 4-14 provide equ.~l~#.~ttP.at rii&q:::~:::~pplied while
programming the memory timings. ..:::::::};.::j>:;,;,;,:::::t<:
···· ··· ··· ·
:::: ::::::::::
.. ..

.·.:·::::~(~~?::~:. .:::::::::\\:.::.

·.·.·.·-:-:-:-:.::}:::: :-:-:.:-:·:·.

Table 4-13 Read Timings: Equ~~,1,99•.·)f:9,~:::f.»rogramriitd" Values

RDlyROW =RowSetUp :ti\\J.w.wH~ld + C~ISitW~::+ Taccess 1 - 1
RDlyCol = C<>:ll~fPP ; Th~~ii:li~!lll!l.li\iit::::::· ·: : : :RTCas ~ Taccestf-~:J?lf>·
RTCas +/f¢P. ~ 5 ·.·.:-:·':'.:'.:'.: : : :,:::::;:::::::::..
·=~=-····

.. ·::-:-:·:.:-:-:·:·:·;.·.·.·

····:·:-:::"'-:,.::::·:-::>:·:·······
<::;:;:;:::::::;:::;:::::::-.

·.·.·.·.·.·.·.·.·.·.·.·.··· ..

.. ::::::::::::;::::::: .·.·.·.··:·:-:-:-: ·:·:-:·:·:.:

Table 4-14:ltllllll;1t~JD.ffllng$.~JEquatlons
for Programmed Values
·.·.·.:-:-:-:-:-:-:-:
.-:-:-:-:-:-:·:·:··
.:-:-:-:-:·:-:-:-:
·.·.·-:·:::-:-:·:·:-:-:-..·:··

..,)mD~taHold is th~::aata hold time, in memCik cycles from CAS assertions, determined by module

<:::::;::::;::::::::::::::}}:
'-'.:\~:}}'./{

/~i#.al integrity and DRAM timing.
.-::::;:::::::::::;:::::·

. ::/)~
...

:-:·:-:-: · -:·:-:-:··

mLF.igure 4-18 and Figure 4-19 show the timing for a memory write and memory
:t·f~~9. respectively. Assume that the two timing diagrams shown are for
-:::'<th~:::\ijame bankset. The programming for these transactions is as shown in
Tii6te 4-15.

··: .. ::::::i.\:·_j:.•.·.:._•·:;·::;:_•.·: :_: :;:_:·: : _:.:

4-24 Digital Confidential

Table 4-15 Programming Memory Timings
Parameter

Desired
Value

RowSetUp

Row Hold

ColSetUp

ColHold

RTCas

TCP

RDlyRow

WTCas

WHoldORow

gtr_RP

,:)\\ila.9., Write

111

!;lJ; ,'.'

·-::::<tilf'

!111;k

Digital Confidential 4-25

Figure 4-18 Memory Write Timing
CYO

CY1

CY2

CY3

CY4

memClk

Col~old---111'(

memRAS_L<O>

memCAS_L<O>

memWE_I

___ ______________
.....,..

.;.;.;.;.:-;.:-:·:..,____.

-I;---:------__,.,.,.,.;.,:;-:::::::::)~ffii.1~0Row-·._''';<_::f:_tn_:1=:_nt._:"---------·f

memData :!:}::;:::::::::::::::::::::::::::::::::;:;::::i:l(

CVS

.·.·.·.·.:·:·:·:·:·:·:·:·:·:·<·.-.

<tL.
CY9

::::::::::::~:~:~

CY10 . .;·· · ::'.!i1.,."(¢v11 .,.,,:,:::::::).ii!iij!9iit::-.

CY13

CY14

CY15

memClk
·-:::;:;:::::::;:;:····

·------------·::::....,:::_--..·
·::::...::::: ...\\ ....·.·.·,·.·..
:
.
.
:
Cg!
· · · · ·.·.·.·.·.·.· · · )(:::::%:::::::::::;:;:;:;:;:;:;:;:;:;:;:;:;:;:;;;:;:;:;:::::::::;:::::~::~::::;:::;:;:::::::::;,;:;:::::::::::;:::::;:;:::::::;::::::::::::::::::,;::::i:::;::::::::::::::::::::::::::::::::::;:::;,::::::::::::::::::::::::::::::::;:::::::::::;::::!:
....
·-:-:·::::::::::;:;:;::-:·:··
:

memAdr ~

memRAS_L<O>

memCAS_L<O>

.....-----.--~<l~t:
.·.· · '_____......i\ii1Ri :it'tt. w

f= =i-----.-·-:::;:::::::::-:·;::'_::::·:::://.:;'..:'.:;.:..:.:-::;.'..,,·.:;'.:·;·',:·'.:·.:·
::t:::<>
..
t""•f-----. .
.:. .------·---·-·..
TCP

memWEJ

i.......---

,."""

~-----.,.,;,;,;,.:::~:\~:?~?:~:(~:)~?:~i:::~::-~·--...;.;.;,;,;,;.,;.:,~----'!
:.:.·.=.:.:·.=.: ..:.:.:::-

:=:::::::::: .·.·.;.;.;.;.;.

::~::>Wte;~ii.rcw:

next DO

W-03269-T!O

4-26 Digital Confidential

Figure 4-19 Memory Read timing
CYO

CY1

CY2

CY3

CY4

CY5

memClk

memRAS_L<O>

memOata

f:;:.;::e:::·::~::::::~:::::·~:::::·~::::::~::::::~:·:;;:~::::::~:::;::~:::::·~:::::·~:::·::~:·::::~:::
!··::::~:·:::·~::::::~:·=====::t:=::=EJ:t:====±5f!:e~~~~~~~~:;l
');,.____________________
~~~!¥::::

:c.::?:. ....: : : . .,: : :.....~: f. ,.: :;'.~I=.:\,.. .,: -:·. .,.,.__'":,_: : : _: : : _'"_________x

1a1ched_c1a1a _ _ _ _ _
in1s
___________
: _,::.....
):....

CY9

CY10

~i}:::·

.....

.·.::::::::::;::: :;:::;::-:: ::::-:·.

··::::::::::::::::·:·:{:~::::::::· .·.·

CY11

memClk

memAdr

COiumn 1

memRAS _L<O>

W-03171-TIO

4.5 Config.~ril.litl.iHlil·o~ltl·i[iili:

The ~iip'f1-dxl:li)fi9ti:::*-9.rt'figuration and timing registers have to be set
up_.,,~J~ memoey{catkb~· read and written by the CPU. Firmware needs to
dei~rmin:~. the number of memory banks in the system and the speed and size

.#ii)~llJil'::~r-~u::s~;~
methods for determining memory configuration.
·yµr~~ng the 2rn7:=i~CA Presence Detect Registers

.: :l~lj[:j[: i: :jl\f:r:'·'
. ···.·.·.·-:-:-·

<::::::::····.··

\j~ \i•C· . . j'\I!~ ~~s:iv~~;n;rt~:~~~!:ci.!'~~i:~~e~~s~~te:i :~!~:; ~~~s :~io~! to
<

'<@:,::·:·rn·:.:.:::m.:·{~he deassertion of reset. Refer to Section 3.2. 7 for the details of this operation.

·: : >:u::tU'<>Wng Memory

Digital Confidential 4-27

n9tJl.:tt~~,;~f;v

This method can be used if the presence detect pins are
21071-CA presence detect registers. The following is tlu~:J~Jgif.!tb.m t'.ii~t)Jij~µ}be

~e~;!;;:;::: ~::: ::~~c:~;-1:~:;91111~::,

2. Read the general control register to 'd~tifm.m~ whethif?m~m.ory is 128-bits
wide or 64-bits wide. The procedure
d~t..t~µing t1MN~().pf.lguration is
the same in both cases except that the Mlr':~~Rt~9n~.d in lh~· following
steps should be halved for 64-bit wid~.-:m~_moey/:t:::H\{:11
.·.:::;:::;:-:.·.··:-···
............ ·.·.:.:·:·

for

~~:~~n~; ~:u~~~~=b~=-~,~~mrilifu. 0,,:-~t size of 512 MB,

4. Write 55555555#16 to addressJ)=::::=:})::::·::,llJ..

·>::::::::;:::::::\\::::-·

.-:-:.:-:-:.:.:·:·:.: ;.;.:-:-:-:··::::-:-:-:-

··:-:::::·

5. Write AAAAAAAA#16 to addti.~=~>fiJ#J._.~_'.
. :=: .: =: : : ·_:.:_;.:.: : : ·: =:.: : :·: : ·.=·: :_/\: .·.
:-::::·.·.. ·::::::::;:·
6. Read address O; if the dati.li~~i.J[)g:Q..t 5555i5'5&§#:i6 bankO has no memory.
Go back to step.J3@~d stait\~\ni:=::tb.e next bilnk. If the data read is
55555555#16, lifill~:::?:::8t~-- memilf::==:i:::::t<:::-..
7. Write AAAi;\MAA#fG)[lti.::li,iu.r.ess 1'28113. (row= 000#16, column=800#16)
8. Write 555gg$~~i.lf.tto
~ddf~i.~liJP,::n::::\..
··.··:::::::::;:::::::::::::::;:-:-:;.·.
9.

Read address 12'8$Jt$~::::if:::the daHHreturned is 55555555#16 then the
bank has wrapped b~eti::tq{~qdress 0. Go to step 10. If the data is not
55555555_:ff:J;§=Ptb.gJtJhe.;&~nl::::~$· a 12,12 bank. You need to determine
whetherdUniM$Ub.banks. ::-::-

• W,lll~~~~~'~lr

with AAAAAAAA#16;
• ::::<WritiWilifess Ojfith 55555555#16;
}~ :[·i:··[:·iead::~~dd"i$[i,!ji~jiijB; If the data is AAAAAAAA#16, then the subbank

,,\llJl!1[iJ;:~:1!:th:::;:::::: :~:eb:~:~wn, go to step 3
··anatsiart. with the next bank.
·:·:·:·:;:: :;:;:::::::::::::::'.:··

b~k<irtder investigation is not a 12,12 bank.
AAAAAAAA#l6 to address 32MB (row=400#16, column = 000#16 for
12,10 DRAMs; row=000#16, column=400#16 for 11,11 DRAMs).
Write 55555555#16 to address 0

4-28 Digital Confidential

Jl ~i~1i1r,J1li• =:=.=·=·:~.:=• =:_=·=:_:.~_:·.=:·=:_=:.=:~:'.=\.=:.:_~=~-~f?

Al'f

111JI';; t ::;iv

.=·,.=.·=.':. =..[.=.:_.=:=··.=:_.=:.:·.

.13. Read address 32MB. If data returned is 55555555#16,. . th~n the blJk::J~,(:Mt

~~~1~~~~~~~~~~:~~C:;~ii~r
•

Read address 64MB; If the data is ~#16,lh~fl.}the subbank
exists; if not then this bank does not have<S.ub.P.~s.
··
··:::::::·:·:-:·:·:-:-·.·.·.·.·.··:·.::..

At this point, all the informatiQf#f.~ti['th:i~ . . bank==:i~\il(ahwn, go to step 3
and start with the next bank. :[:j·,=_! j. [.·:wr=:nm: : : :·:·!j[!j!·:\. '.[:[::t:t:::::,=· ·······
14. The bank under investigation ~-~tn9.tm~ 12,10..-0ifftlil.l· bank.
15. Write AAAAAAAA#l6 to addr~i~::ii.:::(t9w = o~6J=l6, column=200#16)
16. Write 55555555#16 to ad9i!~~.!!p · =·= : : ;,:,:<:~: ·;: : :;~: (: ~ ~: [)·
•

17. Read address 8Mftt:lf daiJqjl~tl.tn~,Q is 55SSS555#16, then the bank is
not a 10,10 bari1U{An.4J.J~gal fiifi.:[J!li.~=J;.>..een inserted. If the data returned
is 55555555.f:,~6, theri['i!!!mp~µk is·===tt::}g~:to bank. You need to determine
whether it_:=b.iit'}§µbbarild#lt.... :::::::::::::::::::::::;.·
-=-==· ==·'=·
· =-:·>=:=
...................

•

. ........ .

Write addre~~===:o[=i\ltlkP:§555SSS#16;
··.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.
·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.··.

Read -~qgf~~$.\\(:)MB;:::}f.:\tl'J.e:: data is AAAAAAAA#l6, then the subbank
existij;:::uHfot.Jm~n
this
Bihk does not have subbanks .
.·.···.··.·.·.··
·-·-:·:-·.;.·.·.·
.·.· ..
• At :=tlt.i$. pojpj~@;114lj¢., information for this bank is known, go to step 3
and]dir.tPWitb. thedfoxt bank.
18. wiitlrt~~:,:[~~liu~ji{~ of all the banks are known, set up the base
-==::Ji·llt:::~:~:e~:!1!:~· The largest bank should be mapped to the
•

...11Jli1il.:~:1fllli11zation

......:::; ..:..:..
~.:

: :: :

. :: ::: : ::: :... ~: ~:;: ~:

..::::::::::;. ..:.:.:......

. : : =: : =: :=?:/
::llltware has.'t~ initialize the Bcache and memory before booting the operating
==t1Jl\l l!li!1!i!!\l !\i\ i:k: : : :.· -:d::·.i\(l(lfl~:.n;;e~~~ following two methods to initialize the Bcache and memory are
··=:=:<=}. .:::::·::::::::X·!!:!)¥.~mary Method

·"'<t. ·:. :!.i:::·::.::~Jtable the Bcache - BIU_CTL<bc_En>=l & 21071-CA GCR<bc_En>=l,
"':::::u=ocR<bc_IgnTag>= 1

Digital Confidential 4-29

----------J::n::::::
..... .::..::u~.?::::e<=:
·.·.·.·.;,;,;,;,;·.·.·.·.··

·-:-:::::::·

:::::::::::::\:-·.

·.:·:-:

----------

.::.::.>=:::...
·~~.·-:·::·:'"""':-:;:::-:::::::.-·
...

·:-:

····:::{~\~b~;~;;):::::·:::::::·

Alternate Met~:!~:::t::\:':·. ·.·-:::r::(=:i;:::·:;;:;··:i:it::::::.. · ::::::::::::-!. Disable the::::Beaelie:::·:o'. BIU ''CTL<lir::En>=O & 21071-CA GCR<bc En>=O
,GCR<bc_IgnTrt~#.Q:.H\>. :. . :::::::::::::::~:
2. Disable machine ch:~bk~:::•QX_CTL<MCHK._EN>=O

3. Write sqm~tl~~~.
i:~~:i~i.6ifs throughout the available memory. This
will PU.ti\:gq:bd diJIH)atjey in the memory SIMMs.

!tq};ill

Enab1Ji.:l~~b.i·'~i\f2 lij~~"-CA only - 21071-CA GCR<bc_En>= 1, GCR<bc_

1 ~s~P91j:!··l:!:·.·1···111i.::.:::=:::::::::t:J~,·.ffi··i.:,;;;··

5. Jl.~i~f some·:'lo@;\i§i.fin. each of the 64K cache blocks. Since bc_lgnTag is set
.::tI\f.M!:\:P.ECchip 2ItPii-CA will fetch data from memory and put it in the cache
·-::::::iiiiiittw.i block with correct tag parity.

.::::I{:;:::::::=:::::::::::::::::::::..

···=:=:::::::::::::::::=:=:=:=:::=:=:·••

./}~i\il\\\\J'i{(j]\]il~\:::. Cl~::f:i:l.j\[\Qi.Ochip
21071-CA bc_lgnTag - GCR<bc_lgnTag>= 0
.·:;:;::::;:::::;::·>:·.
.. ·.·.·.·.·.·.·.·.·.·.·.· ....
·-=:::::;:;:~::::::::=:;::::::

. . ::·: :·:. . . -:.·

.::::;:::::;:::::::::-:-:-

:::::::::::::::::::::\t\:::·.

>z~ltEnable B~iiche in DECchip 21064 microprocessor - BIU_CTL<bc_En>=l
-:-:-:-:-:.:::::::::::

.:::J:,~~:i\? Enable machine checks (if desired) ABOX_CTL<MCHK_EN>=l

4-30 Digital Confi.dential

DECchip 21071-CA,l;rt;;11rliWQIQJlS and
fiifl!~·:e:e.. rJ:iag rams
...·.;.··
.·.·-:-:-:

····:·:·· ...·.·.·.···

...... .._:::·)·.::.::·.:::::;::::::::::::::::::::·:-:~tr·.:~.::·.-:.::.::.·:.·.
·:·:·::::;:

··:·::::·:·:·:·:·:::{\:~({\:::·.

5.1 Introduction

5.2.1.1 Idle

When the CPtf''iil:i~ijj¢:t:the 2io718Q.~::~p,ip prepares for the next CPU transaction. The cache dhii.tf91~t~e disiibl~d'~ with the exception of sysEarlyOEEn,
which will enable the ·caeij~·rn~~ on CPU read or write, and enable the cache
data on a read..·.<·°'· -: -:-:-:·=·:-:-:·.·.
·-·=: : : : : : : : : : :>: : : =:=:-.
.. : : : : : '.: .: =:-:· :<::::::::::::::::::····
=====: : :====:>=<·.
====<<UH:?==
5.2.1.2 Read Block/ttt:=::::=="'·..·. · .·=·=·=·=· =· · ·

-·=:::::=:::::::::=··

.-:.:-:-:::=:-:-.

':::::::::;:::::::::::

. ··:=::::::::::=-:·.··

}\)f}

:{~rtr

5.2.1.24.. Ci.Cle.it~ Wt1t¥!Vlctlm

Figure 5-1 shows a read block transaction

···· ~:i~i«i~:~~~!~;~~=~~:cle by the address being v~id due

..... \}ti~\::::-:·.

.................. .

.·= :~:rn: :~·:·l=il: rnrnti]\: :!l!li)~\= = Th~tdQUjl!imqµests a read block with cpuCReq<2:0>. Because sysEarly.:-=: ====<=: =: :=-= . =\{{}))]:0EEn wffifai$=serted, this triggers the assertion of bcDataOE and bcTagOE .
.:::J\·[··:·:·:jjj)f?
-::·::.:::::\i\ji\jjfj.::\]J:::.:.

:=:!~~l:l.\j:\\:The 21071~CA chip decodes sysAdr<33:5> and finds it in cach~able memory
·==•:•·;:.:.;.;.:··space. Also, the cache tag is available and indicates a victim must be

\ '.1111.

i: ;:~~~~

:e!~!e:~;~r: :c~::i~':Y~~~~~a~i:~e~!~,a~:l~;;~~>.

··=:::::::::H:::i[(f:llA cycle later by sysDataAHEn. These will produce a one cycle pulse on
·. =:t{:.:;=.:JfoDataA4 beginning on clk2F. To maintain the data output from the cache,
· ·==sysEarlyOEEn is left asserted and sysDataOEEn is asserted.
Digital Confidential 5-1

. :+:::::i::;i:~:::::;.~.:!:t;· ::·:·:·.

Q'.?!it~~f~:ifil[.~V

The second ocUtword of the victim is received. The 21
!;si~':~~~~s by deasserting the cache controls,,~1111:i:~~~,Jjf

4. The read of the victim is complete. The cache ,Jilf:l)ue driveif].~y:::~li:e
21071-CA chip with the tag informati9p.for the:::filUi.~~ (valid aritf clean).
If the CPU requested a wrapped retlo~a?.eD.~taA<4$.%w9.i.Jd.. be asserted

~~:=:k~::b!n~:a1r::~=d~ej~!!ill~:~:llt:::. ~~e

CPU internal Dcache is invalidated using cpuDJuyf@q. Figure 5-9 shows a
wrapped LDx_L read.
..,.,.:., :::::;::;:<·:-:·····.
....·.·.
·::\:+?::·::::::tt}.'
:. :.:.:,:·
.·.·.·,·.:::
.... :.;.:-:-;.

5. The system may stall for any nu•f:/tif\ey~)~~\W.aitin~ffor the read data
to be available, although in this ~:i~~f the ·fi~ii~l:::a@t.~Js ready now. It is
~::n~:~~:.daUt bus, an!\~·~'.;.!s
OK

acklilii!lidged as

using

··.·.·.·.·-:-:;:;:;:·

sysTagWE is asserted, w~j~::'g~ner~t~~!\!ij¢TlgctlWE and bcTagAdrWE to
write the tags intR the caa!~Mi?:>,. .
., : : : : : : : : : : : ···

.·.:·.·:·.·

•.·.·.·.·

SysDataWEEn .:f~l::·;~'smed, iiFtlP.:::g~perating bcDataWE, which writes the
data into the cacli~. Jfq[!iP.r~.pare ld\wnU.tthe second octaword bcDataA<4>
8

~~0: =~111i.~~,.ii~~j!!~~':~s ~u:~: ::::e~; t:::~at
duration. See\$~~~l9~1J~.2.4 '"' :t:::u:rr:: .

6. The second octa;afd'·.)i~::i!W:nt.ten ·~th sysDataWEEn, and again acknowledged as QJ.¥.:::µ~~pg cpiiDM~R'~2:0>. bcDataA<4> is deasserted once we are
done with'::t.Ili.5¥6.t~( The"'"'~ffpiter could decide that DMA will be granted
the bu~W,:i:~$./fodi~~~'d .PY, the unknown (X's) on cpuHoldReq and ioGrant.
For mqf:~iliPifo.rii~tioq:''~bout arbitration, see Section 5.2.3.

1\~:::,gy~:fi::.~~:::l~ov.dil~d with cpuCAck<2:0> and the data drivers and

cai'P.J~Vcoritii'@.Ilri:::f~\ffined to their default state. 1t is not possible to
/:~$.eft cpuCA&k@.2:m;· sooner. As the CPU data bus drivers could have

·</:\¢.f:~~t~4 a bus contention with the memory output buffers.

Tli~i[~·~fa$a~tion is complete and the next transaction is ready to begin.

··:::;:,:,:,:,:-:::,,,,,:,:,..1.J.

the''ctf:u!:\:W,on arbitration, sysEarlyOEEn will be asserted in the next
in preparation for the next transaction. If the 21071-DA chip won
this cycle is used for bus turnaround.

5-2 Digital Confidential

Figure 5-1 Timing of CPU Read Block, Cacheable, Victim
CY1

CYO

CY2

CY3

ctk1
clk2
:::::::::>

cpuH~dReq

+---------.....;----------~--------..;.-~·~}~\~:::~~::~·~:··_...._;.---·-·::::~;:::~::;::~:;:::~:·:·~·····~r.~::~:·.~----~'=
···:-:.;

:::·:-·

··:,,·.·.·

cpuH~dAck ~~=~~~::~:~~:::::~~~~:~~==i...------------------------------··-~~··~°';,;,;,;...,._----_.-::'..\~f~:::,.~:. :.::~'. .: .~:::~:::~::-.,.._
·
___
-::::::::::;:::~:'.~::::::·:···

ioCmd

...----------.-------.--------...----------,-..r;,;:.,.:::::~::::~::::-..,.:,..,.,.,---....--~·-·----?·.·,· ··.;.:.·.·.··.· ·· · ·
idle

cpuCReq

~=--~~:~~:~:x-~:·:·~:·:·"-lXlli!'-J.'11:1:.:.:.:.:W:w:.:t\--:r~ea~d~b~lo~c~k-----..;...,~·~::::~:::::~::'~::.~·::::~:::-~··~-----·-··~··:-~:c:~·=-:~·:·:-~•·~···:~:·:~·--------

ioGrant

i::::::::::::::::::::::::::::::::::::::::::::::::~x::::::::::::::::::::::::::::q(
~tream
not wrapped:::::,::; '.;'.:'.:'\:::::::\:</_::_:_._:_;_:._' '".
•
.
.
.
·'.·>'.·'.·:·.

cpuCWMask

::~:;:;:·:-:-:-·.·.·.·.·

cpuAdr
cpuData

drvSysData
sys DOE
cpuOOE_I
cpuDWSel

cpuCAck
cpuDRAck

··:::===~n?~:I\r::~;~:>·=··

.
~::::::::::::::::::::;:;:;:;:::::::\:'.:'.::·:

ioDataRdy

··:;:·:·:···:·:······

'"·'.·'.·'.·:::.:

.....

/::::;:;:;:;:;:;:;:::::::::::;:;:;::~

·:·:::::~::::::::::::;:::·:···:···:·.

/:::::::::::::::::::;:;:;:::;::::::/

ioCAck
sysEarlyOEEn
sysTagOEEn
. .·.:·:->:·.·

bcTagCEOE_I

.. ·.··~· ./:}}:-·.
\:::::::\ .. ··::::::::\::::-:,:-:,:·.·:-::-;.·.

/,::::;:::::;:::::::::;:::::::::::;:/

-:----7t···+''±':::f>4:~+~::p·f··p···+:::1:c~::::!::~:J::~]::~::~~EPE:~;i:~;:;Jxx·~:-YQ::;5!··:::::::::::::::~.._-V~.~"D~·--------"""'

sysTagVDP

}} :::l}/ :\\:}\{:{. .:·. .

sysDataOEEn

f:::i:::i;:~:::::::;:\/

\;::::::::4:)\
i:::::::q

bcOataCEOE_I
cpuDinvReq

.· ··. {:/fl~~E_I ~.-.~:::;:,;,;,·:~-~--~:::::~:::::~::
----------------------'---...Q___,l
:{{:'.::::::;:.:.
·'.·'.-'.·>:·'.·:-.

··:·:::·:..:·:·:::·:·:·:::::::--

.·.·-=-···:-::::,:;:;::::::::==::::tw#~e

bc~~~IL1
,:::{)Y.~¢1nd

+--·-:=:;:~:::::~::::·~·::::~::::::~:::::~r_ _ _ _ _ _ _ _ _ _ _~-------!-------'l~.·:::~=>~~x=:==~-:::f
··-:::::::.:;:::;::·

:~:::::::::::::::::::::::::::::::::::::::::::::::::~ ::::::::::::~:::::

~:.·

~\:::::::::::::::::::::\
reset

:::::::::::::::::::::.

load

Idle
Start Trans
Tag Probe
Victim Read O
Note:
ioRequest is not important during this transaction.

::::::::::::::::::::::

wrs s

Victim Read 1

:::::::::::::::::::::.

BUS
Turnaround

Cache Fill
and ARB
W-03134-TIO

Digital Confidential 5-3

CY6

CY7

CVS

clk1
clk2

cpuHoldReq
cpuHoldAck
ioGrant
ioCmd

idle

cpuCReq
cpuCWMask
cpuAdr
cpuOata
drvSysOata
sysOOE
cpuOOE_I
cpuOWSel

bcTagCEOE_I
sysT.~!!YPf>

·-;;:::::;::::::;::::-:-:·::;::... ·.:-:-:-:-...

:J!v~rio~·::z:::::g:::J-··!··t··:I"·::-::::::E-~~--<~

. :~r:~~~~ :-:·"': ~:...·: . . ---""*:::;.;,;::::;.;,;:;:__: : -_:- - - - - - - - - - -

:::O::~taceoitif/{.

'..I;-

::j_j:j·j::\:\::::fpuDin:~~"::{··-·:_.:,..::::,..:;::.~:-:-+o:·:--------------:::\:~:~~l~

•·• i!W
.. /:::;:::::::::\.::::::::.
··.·.·.-.:~:::·==::::=-:· }/:::::::..
.""""""""""··

.··1::::;:;::::::::'.;:f

sysOataWEEn

\ 1<1: :,:,: :~" '.;'.;',;.i·'.'.;'.,;.i: \ -. . .,_ _,~""::::""'.;'.;""'.~;·"".;:::...~~....
: : ,.~: : .:.o:~:

"*~. .t...,i\....______....:
1=:..

~.,.·::::;,::;::;:;.::;::;:":::::.:tl::;:"":\~-....:.-------

bcDataWE_I

····:::::::::::E::_~:\\~~\:\~:t\:::~r.sTagwe Wimm
.: .: ~::. .~: ..,: : :.,.: :.:..--------------·:::::\[j~f:M~~we_1

·:::;:;:"sysCmd

':.JJ!i,'jj}J}J
, _·"':·:·,. :·:·...
:·:·..
:·:·:..
·:·:"-=:;.__~=""'~r~es-e~t~"=..
·:·:..
::·:,.·:·:·.,.:·:·...
:::."--r~es-e~t~
Cache Fill
Terminate
Next Trans
Note:
ioRequest is not important during this transaction.
W-03135-TIO

5-4 Digital Confidential

itl]! '.':~1 11~tltil lif
1

•Y

:::{t/

5.2.1.2.2 Cacheable Without Victim

::::::::::::;:::

.:::::::;:;::

Figure 5-2 shows . .~-:-:r.~ad·-:bl~l.I:\:\::::J[:::\[=[:[:!i[:;·

transaction in cacheahle space without avictim. ;J!!~'i'~i!:\t\l'lilil!lll\[~;:::lli';,),rf\l

0. A read block begins during the idle cycle by tqf:iJt~gt~ss being·=v.aimr due to
the CPU doing a probe of the Bcache~Jt\\.;
·::==::::\tlif\}::>=-=··
·.·.·
1. The CPU requests a read block withtf~hQtW.:q5.2:~-~'~lllilU.~~tsysEarly-

:::1:;:.~::~::·d::sd::::::;;~~~,-~::~~:::~:~:~
6t~~i:::~P~~::h:d:: ~:~:~·--~:\tt~s~d~~~~h

deasserts bcDataOE and bcTa~i]lll:l\::l[
·:·:::::n:::t:::;::\. \.::l\ill[ilt
3. The cache tags are driven byJf.UM2llt:l~PA chi1f\fith the tag information
1

:eth~= d~:i:~:::~11:::r;!!ill1aata bus, and the data

is acknowledgec;Jti~tOK usffigii!P.P.9.iP:RAck<2:t». If the read was. in the
instruction streaiijl.fa.~/m.dicat~'d:]~@fa~pµ.CWMask<2> being false and the

Dcache is invalidaOOd using
~~e~~ni~~-L~~~1Jt. sysDataWEEn, and again acknowl~~~~:~~,;;:: vQtifJ'.~;~~iifflfr!il

6. The cycle i~.J!<.;~J1,9wi~'ai~i.::. w~t.P. cpuCAck<2:0> and the data drivers are
returne4:::\g:::mi~j\::9!f.aulf'sti!f,e';· in this case for a DMA transaction.
:;:;:;:--

Digital Confidential 5-5.

CYO

CY1

CY2

clk1
clk2

cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuCReq
cpuCWMask

-:-:·:·······:·:::-·

cpuAdr

:~::::::::::::::::::::::::::::::~ read cac addr~ss:::::::

cpuOata

::;:::::::::::::::::::::::::::::::::::::::::::::::::::;:

'."·'.-:·:::::::::·:·:~-:-:-:-:::··.

·-::::::)::::::::::::::::::::.

drvSysData
sysDOE

··:·:·:-:::::::::::::::::::i:::;.;.·

cpuDOE_I

··:·:-::::::::::;:;~:;::

cpuOWSel

.·.·.·.·.·

:·:·:·.•.

··-==:\~??'

cpuCAck

<:\:};:~:::::::;: .....

cpuORAck .. .

ioOataRd,~: :\Ji:;:,::::::::::::::::::::::::::::\
ioCAck
sysEarlyOEEn

· -: : : : : : : : : : :

·.·.:·:·:;.

· ;-:·:·:·: -:·:-:-:-:-::::::;:::::::::-.·

: : : ~: :;:;: ;: : :·: : :;: : : ;: ;: : : :;: : : : : : j: : . . . . :.::.,.1d.,..j•.,..::_,..'...\:,,,....._ _ _ _ _ _ _ _ _ _...'
'f:::::::::::::::::::::::::::::::::::::=:;:::::Xi$illJ

.. :.:/;

\::::::::::::::\ :

sysTagOEEn
bcTagCEOE.,;;U' ,. .,: •: . .,.-:·""'·:·:·"'"':-:-:""'-:-:--:·:··-.--""...
:::::,_.•:;...
;:::.-.::::,~\:...:::::,.....;::{·;::sysTagYP.:e: .::::~::::: :'::::::::::::::::::::::::::·.·

sysD~~~f .
bc0at~¢~~~~1. :..·:':·: .'... '...

,:::::::::::~:P.u~:j~~~j\\\:::l\\j,:~::::::··

. /.:::::::::::::::::::::::<::::::::::/

···:::::::::::::K:::::::::::::::::::¥=:::::::::::::::x no&::::::::::::::::::::::::~

"·"··

·;:,::\/;::~

.: : : : ·,:;:~·

:rnMroataArn~:::t,..r;,;,:::::;,;;::::,..t;,;,to;;::::,..=::::o;;:::::;.;.;t.-::::_:::·..,...._ _ _ ___,_ _ _ _ __,__ _ _ ___,.
/::j]):]\\ij~DataAHEn

<:\.:.·-

.·.:-:-:·:·:·:·'.·'.·'.;.:-·

· "":·:·:·:-:·:""·· ·

·:-:::::::::ttii::::::::~~m~< 4>
...::::~9.@W~~:~.
b~~~. :_:::_e_;·_J(
,,,, ....
.-:·:·:-/}'
w_,:,'_;_
..

sysTagWE;)'..,....------..------.------1"""------ibcTagCtlWE_I
sysCmd

:~:::::::::::::::::::::::::::::::::::::::::::::::::::;:

:::::::::::::::::::

reset

·::::::::::::::::::::::.

load

Idle
Start Trans
Cache Probe
Note:
ioRequest is not important during this transaction.

5-6 Digital Confidential

::::::::::::::::::::::

BUS
Turnaround
W-03156-TIO

CY4

CVS

CY6

clk1
clk2

cpuHoldReq
cpuHoldAck

~: : : : : : : : : : :=;:= : : : : : : : : : ; : : : : : :;:;:;:;:;:;:;:;:;:;: : ~:~=: = =:~= ~:~:\:;:~:t:;~;:;: : :;: : :;:;: : : : : : :;: t}~:i1%J: ~: : }:·

ioGrant
ioCmd

·1rn;;;;;\fi:i;1;r.i~1;i;i;~

cpuCReq

cpuCWMask
cpuAdr

cpuData
drvSysData

sys DOE
::::::::::::::::::::::·:·:·,;:::::::::;:::·:·:::::;:::;.;.

cpuDOE_I
cpuDWSel
cpuCAck
cpuDRAck

·'.-'.·'.·'.·'.· .

. ::;!;!;:::;:;:)t?
.:::qt1~1::11:::=:::::.:-l:::i:i:i:l:i:i:i:::::l:::i:i:i)(§@;j;;;;4:;:;:::;:;:;#::¥\
iwii;fiiII1~:i:i:l:i:i:i:l:i:};);f11&~;!;ii:i:i;M~=i=i-:i:iW:i:.:i=l=w:!:l=...;:::i"':;:i\...__• - - - - - I

•• :::::::::..

;o0=&t~7ciii(; , . .·.·.·.·.·.·.. ; !i!~4---·,j
:::::::::::;:~::·

sysEarlyOEifi((;.;:'.t.,.:_.,;,·.,;,'"'";,;,.:·:-:;;,;,;,;,.,._-__,,_....·....
·.· .,. ·.·.·.,.: :~/,;,;}'. ,;,: : .,;,: :..,. ~------------...
··.·-:·:·:.:-:.;-:-:·:·:-:-:-:··.·

sysTagOEEn
. ··::. ::;.:-:::: ::: . ::::::::::::::::::-~ ·.

bcTagCEOE_I
sysTagVDP

=vZD)noE=····:··:··::
....'.:;:'.'.'.:::;::;::=::·:·::::z======:E--+---(~

sysDataQ$.~j/ ..:...·",..."'·'",..'·...,·=·=...,·:-:....·:·,...·.·.,...·.·.,..·._ _ _..::_:=::...:::...::=:...,::O;.;.(.../ _ : · · - - - - - - - - - - - - - bcData®~J(::,..':;,..,:,:,:..,-:""":-:-:,. .,-:""'
....""'
.. ......__ _ _ _...__ _,,,,_._ _ _ __,__ _~

~~i~~~ ~ : ;:'.;i;i;i;'.;:; ; ; ; : ;:;:;:;:~;: ~:~i~i~i~ :

.t!1:at;1:;;;rn1,1:::\;~~~:-~,..::..:... .

====_====\_.___,,_·:::-::=:-:::;:-:::=:_:

'.:}}\ij.sDataWEEn

-··· - .·.·.·.·-:-:-:.:-:·····

#@EiF

-.,.,,,,:\ili~i:I:1~~,~~~e_1

·-:;::;~;!filli:f::::~
.·:..,;;., -.· ;,;,;:;::·. ___~.&·:..:~...;:;::...:::...: :;_:;~,
sysc'it~t::· .;.;:;.;:;::·:·:·:·:·:·

rese

Cache Fill
Cache Fill
Terminate
and ARB
Note:
ioRequest is not important during this transaction.

Next Trans

W-03157·TIO

Digital Confidential 5-7

u.1.2.3

No~c~• ~~e ~ reoo bloc~ kJtr~if~: ~1\il f!l~v
shows a

. : :.

noncacheable Space.

:·::.:::::.::::·.::::::::·.:=:.:·:.:•.::::·.:·.:....:.:....:.::·.:.=....:;:.:·::·.:.:.:.=·::·.:·::·.:·::·.:::·::·.· ..•.

·-:::t\/\?/?:::t
'.·::::\~(jf ~f:}:::::··

OOdr~]~1i~::::~!l1lts one

O. In read block to noncacheable space, the
CPU cycle before clklR, which for fa~t.:::e,pus niiyi!iti.~m\9P.Jy 4 ns.
·>:·::;:::::::::::::=··

··-::::::::::::;:::::::::;::::::::::·.·.

·-:.·

l. ~~~~::;~:~:d: :~dt~=r:~::~-~f~~~~~s~~E.

2. The 21071-CA chip decodes sysAdr<3.;l;:§?. ~:d:=::~6,~~::i:~tA~. in,.~oncacheable
memory space. The 21071-CA chip{pf~P.~r~§. to dHvi.Ithe bus so
sysEarlyOEEn is deasserted, whicb.rnliisS.~f#.~t\:}.l.~PataOE and bcTagOE.
3.

~~:?!!~a;:::~ !keilfli;~.ill!iJrn floating. The 21011-

4. The read data is ready. It..J~Aliiven····oilti{th~Jlata bus, and the data is
acknowledged as .noncacll-l~h~,.sing ci>ul>:R$tk<2:0>. CpuDlnvReq does

~!:::::d:&\l!'.::!~:!IJl~~Y!::e~~! ;::d~ore than a

5. The cycle i~:::A~!mowi~d~~~il:*j.:t~ ~~~eli~·<2:0> and the data drivers are
returned t&:th~ibdefauU>st.atiH>::
·
·::::~:}}}{{ :-:·:.:-:-;..
-:-:·:-:;;:: ::::::::::::::.·

A read block.with th~\~i:~htkdisabled is similar to a noncacheable
read. HQW~Y¢.t~'::.~:!Jlt.ll h~~iw~td is returned, and OK will be sent on

~:c~!,~172:~~~!\i~~~;~e bPU will place the data in
::::::::::;:;::::;::.

.::::;:::

·:·:-:-:;;

.. ::::: ·'.·:-:-:·:·:-:·.·.·.·.·.· :·:;::::\{\..
·-:-:-:-:;:::;:;'.·'.·.

·.·.·.·:·:·:·:·::~.;.}(::::·:

·'.·'.·:·:-:·::;:;:::;·::;:::·:.:.:

5-8 Digital Confidential

its Dcache or

Figure 5-3 Timing of CPU Read Block, Noncacheable
CY1

CYO

CY2

ck1
clk2
cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuCReq
cpuCWMask
•

cpuAdr

•

·>~:-:-

:h:::::::::::::::::::::::::::mm read nocac addt~·

·::;:::::::::::::::~::::::

::::::...

.
cpuData &:::::::::::::::::::::::::::::::::::::::::::::::::&:>---m::::::::::i::~:i:i::::::::::::::::Xi:::::::::::::::::::::::::::;:::;:;:).
drvSysData

··:::::::::f::::::::::::::::::::::::.

·.·.:-:·:-:-:-:-:-:·:-:-:·:·:·:·:-'.·'.·

·.·.·.·;.:-:-·

/}JtIF@tFit\::.,.

·..... :-·

. i;;;;;;;;:::::::::::::::~;:::::::i

sysDOE
cpuDOE_I
cpuDWSel
cpuCAck

cpuDRAck.

ioDataR~:: ·::~:;;;;;::::::::::::::::::::::::::::\ :::::::yr:::::::::::::):::::·:·

...-•... j .../...;: :...__________...

ioCAck '''''+i:?:;;;;;<~;i::;:::w::::::::;:;::~::::m ;a;.;.;·,&...

sysEar~OEEn

:~::::::::;:;:;:;:;:;:::;:)::=;:::::;j:~

sysTagOEEn

··.·.·-:-:-:-

·-·-:-:-·.

. ·. :::::::~:

.. >j):j:j:::.

llJfri\.
....::. . .- - - - - - -

··:·::::::::::'(::::::;::::::::::::::{::::;::::::::::::::::::::~::::::{::::::::::::::;:;:::::::::::::::::::::::::::::::::~:

sysTagW$.):..,....._ _ _ ___,,_ _ _ _ _ _ _ _ _ ___,_ _ _ _ _...,.
bcTagCtlWE_I

Idle
Start Trans
Cache Tum Off
Note:
ioRequest is not important during this transaction.

BUS
Turnaround
LJ-03160-TIO

Digital Confidential 5-9

clk1
clk2

cpliHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuCReq
cpuCWMask
cpuAdr
cpuData
drvSysData
sys DOE
cpuDOE_I
cpuDWSel

~il~~~~tw.ioOataRdy ··:·h::::::::::::::::::::::::;:::::::l.

.::::J~ck

l:::::::::::::~:~:~:M:M:::::~:~:N=~:~:~:~:~~:::::: .

.~;~::;:;:;:;:;::\':':'.:':':: ':~:i:::::::i:::::::::\:::!:;/:;;;:;:;:;~J~~;~:::::::;:l:i:l:::::::::::::::l:l:::::i::::::l

syJ~~~it>;j,..----····_-::
..:<;: ; \; ;.,;·.·];.;.1.·.·.··
,;\,;,;,: : ;·.·.·.·.·.·.·.·.·
;,;' '"'.-.· · ~·.,.,._
_ _.....·- - - - - - ; . ·
.
.
•
·.~·

sysTagOE:$~: \i :::::::::>•

-:::/'////

bcTagCEOE_I · ··.,:;-:_,-:···~:···..,:····_,·~;,o;,.,.,.._....--------£iii5

sysT~9.v.op :i:::;;/:;:;/;\i:;:;:i/{}::::::~::::::::::::::::::::::::::::::::::::::::::::::::::i:::i:::::::::::;::::::::::~
~~~¢.$.W::

. ..,..

,:,: -·

..., , .,_-----·.;·:...,-:.;.·. ----. . . . --~
•.. ,. :::::::::~puDin..v......~
· .:.·:· ·".·.·: : ;:;: ...
· , _. ,;.;· :-,;.;:-:·:. ,·:·:. ,·:----------1:£""0::.:0: : :; :;,: : -; :;:·: :. : : : _,.: : " ": ~:.:o: : ·; :;,·:~:; :;,: : " '": :~:
:{:::
·=':':::::m::w,B:~w~
, , , , ,., ,: : :
.(:::;:::::i:::::::i:i:::i:::::::i:t
:~~~Mrn6~m ':';,;,:~,

.@\\:::,.· <\:~~~~~~H.~-~- ·+.i.r.-~·=·';!I;,' °~.;..._ _....__ _ _ __.__ _ __

· ·:-· . =·=-:-·

.;:;:::;:;:,, ··:·::;::::::

.,::tJ~i:::rnrn::::::::::,,

'tiijD.~~WlI/fmr=..

sysDataWEEk' :-....
·;::_-:··-------------------'"

·<;;1;1111''i~t!ti;;~~7=~
·::;:::::'::¥.t,~9.~E_I

Return Data
and ARB

Terminate

Note:
ioRequest is not important during this transaction.

5-1 O Digital Confidential

Next Trans

W-03161 ·TIO

5.2.1.2.4 1/0 Space
space.

Figure 5-4 shows a read block tran~.~cyio:}~n 11.Q~~{flQ
.;:::t:m::::m:m:m:t::::::::::..
· : : : : : :t\[[i:l i: : ; :;: : : : : : :·

0. As 1/0 Space is noncacheable, the address is place1:~:~hffhl~::ljl\li).}Q~U cycle
before clklR, which for fast CPUs ma~. be onl~:::~lii~'~\::...
· :·::t{[\[\i!\\l\·l:::l\\l![\/
1. The CPU requests a read block with ,:~P.µCReq<2~WMfJ,~:~~.ause sysEarly-

:::1:~-~::::·d:~~:~:::~!~ll1~~~1it:c:~:;·
the cache off the bus, while preventing the
sysEarlyOEEn

for

·s deasserted and sysTagOEEn 1·s as~
. £.:lit:U..J..

tagiftpmlifl9~ting;

..;,j;:...

·::::=:::::.::. :·:.:. :::::::::':
·::::=::···:·:·:·::::::::::::::::.

~o~s~~!~i?:v~i:e:i~ts ~~t·--tii;~ji~e 21071-DA

chip

4. The 21071-CA chip could ret"Q:\tdiii.t.~::m.. this cycte; but the data is not

ready for two more cycles.,.;:::. ;.:. .;!:!':! ;!?: : ·:·: : : ;: : :i {l :l:l l1\.~i- :1l:l1:i:L: : : :.

5
.

:~~~:~~i~;:!;Wtt;?;~}5it~~:::!c

~~~;;;:~~~~::J'8ii~~:!9:!~fe~~;:~· ::g:;:ke:~:!:t.

6. The read d:fi:i:\~~i!1!t~@gy a~:J.Ht·~li.i4Hv~n onto the data bus. The 21071-CA

chip receives thg:::tpij:J4Mck<2:l)5ffequest on ioCmd<2:0> and asserts
cpuDRAck<2:0> as fhin~i.~h~a.ble. A CPU cycle acknowledge is requested
using ioCmP:~~~·~l.?V: -' '<t:).;°-:i.:·Hm:t
7.

:~~•:;!-f.:i~~~~:;o;~s~~~!~~:~:a!:i:~~;i;
·:·-.··
.·.·:·:::·:·:·:·.

::::::::::::::.. :.:.:•
:::::::::{~:?

.::::::::::::}~:\}:

··=::::=}~:}~{{:~{{

..:;:::::::;:;::::::·

::::.:.:.:::::::·'·.·:.::::·:.···.-=·>:·:-:·:·:·.·
........ ;:::;:::::::::::.. .
.•.•..·.·.•.• .•.•.·:=:::::::::::::::~: ~ ~ ~:::: ..

.·.·.·.·.·.·.·.·.·......... .

.....:\{/f\f~)::::::··

··.:-:·'.·'.·'.·'.·'.·'.·:·:·:·:·:·:

.·:-:-:-:-:;:::::::·:::::::::::·:·:

Digital Confidential 5-11

Figure 5-4 Timing of CPU Read Block, Remote 1/0 Space
CYO

CY1

CY3

CY2

cl.k1
clk2

ioRequest
cpuHoldReq
cpuHoldAck
ioGrant
·-:··-:·:·:·:i· ..........·

ioCmd

Idle

·····.<·.·.·.·.·.·.:-:-:-:····

sysEart~::: :\::::::::::::::::::::::::;;:;::::::::::::::::£....

idle ·•:•:::

.: : : .·:.: : , :·,\~:; ;

...
;;::::.:.:::::.:.i:\...._:_ _ _ __..._ _ _ ____..

·--:<:•::.;.::::;:•:•:>:·:···=···

sysTagOEEn

/;:::::::::::::::::;:::f.

::::::::=:::::::,,•,
bcTagCEOEJ
sysTagVDP

'=::::::::\; :-:-:-::·:··:•:•:::::-.

C'::::::{;jtf.::t:'.:'.:i:'.:::::::::::m;::i:::?. : : '.; : : : : : : :'.;'.: :'.: : : :'.: :'.: : : :;~.: : :.:·: : : : : :'.:·: :·: : : : :t:{: : '.:

:,/): :;:::::;:;:;::; ())•:,.

.:~:~~r~:~::::::::::: -... ·-:-=::::::::::/:~r·

sysDataOEEr!• ·•·•·•:·::-·.·.·

/fR\,..5_._:-----'-----~

:•:•:•:•:•:•:•:==;

·· · ·

bcDataceoejJ\;:ii. :•:•:•:•:•: ;: :

ij...·; :..; ; . ,:\_____....A;.,.::::.,.:::::,..:::::..::::·.,.·::?.,..:::::-:::::f

~.Ri.~vRe~k::::l~~!i:.:, ::;:;:;:.:;::<)•

... ·•:•:-:-:·:

.::.i1: :"•·•·•·:::. · ·.'.}: : : : : : : : : ~·l·: :.:> ·
..

. .. ..

···:·:·:::::::::;:-:-:

. .;:\?~~4> .·.-----------------------------

. . .~~P:@m~:::... . ~--------------------------.
bco~W,f,4,::\\)::::1: ).): :j:j: : : : :
______________________
•••

-~.,_.;.;,;.;;;....,....._

.._

__..

:•::;.;::::::::::·:·:·:·:::::·:·:·::;:;.;.;.;::·:· :·:=:·:::·::;.;:::

reset

;.;.;.;:;.;:;.;:;.;.;.

::::::~::~::::·:::·Z$::::~::::::::::::::::::::::•::::::::::::::::::::?::::·:::::::::::::::::::::::;::~::;:•:;:·:::;:::::::::::::::;:;:::::::::::;:::;:;:;:;:;:;:::·:;:;:::::::·:;:;:;:;:;:;:;:;:;:::;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:::·:;:;:·:
I

•

: BUS

•

Idle

Start Trans

Cache Tum Off ' Turnaround

Wait RDR
W-03158-TIO

5-12 Digital Confidential

CVS

CY~:{!::::::l:.~ll.lli!il·);):))i)li): :-:· ·

CY7

CVS

clk1

·.-.·.·.·.:::::·:::·.

clk2

ioRequest
cpuHoldReq
cpuHoldAc:k

......------.------.---~-..,....-·::..,'::>'""·:,......,..____. . , ·:·:-:-:::::::::: ·: . ,.
j;:::::::::::::::::::::::::::::::::;:::::::::::::-:::::::::::::::::::::::::;:;:::::;:;:::;:;:;:;:~:·.·.

loGrant
ioCmd

:·:·>'.·:::·

..:::::::::::::::::::::

cpuCReq
cpuCWMask
cpuAdr
cpuData

•!•:O!•!•!•:•:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:.·

drvSysData
sys DOE

cpuDOEJ
cpuDWSel

;:: ;:::;: ~~~
.......

..::::::\:::{¥;;;\:::::::::::::::::::::;:?

loDataRdy

'•'.-:•:.:-~:·

.·.;.,

sysTagOEEn

:•:•.·.

··:t>:o:\o:.:;;;:.:.;:;;:;.,.:;:;.,.:;:;,..:;;;._.:;;;::o:o;;;;""'.\.___ _ _ _ __
I

·-··::::::::::::::::::: ;:};:~:> :-:.

~
em!S

~;:::::::.

bcTagCEOE_I

sysTagVDP,. .JN:i=i:::itfi:i:i:i:i:i:iii:ifff:;fff{{i:fr:ifi:i:i:i:i:·:!:i:!:i:i:i:i:i:::i:;:i:i:i)1

sysDa.t~f>j~M/ :•., :}....
} ....
?.,../..,.:O::..,.•:::.,.:•:••.,.·..__,___.....,.____....,._ _ _ _ _......._ _ _ _ _.,.
bcOa~~(j"

...,.____._____...____...__________...___

---:.:-·~
:~."'

...,~

~~~~eq """"'"""""·~"·--<~}~:/~.%......____.....______,_____--;..

sys~.:'.·.:'.~'. ~.:·.·:'-tl:,-. ·':

.,. •: .,. : : ~). ,:-:~'" :

.
...
n_r_·:•"_ _::::::::;:::;:;:;)' - - - - - - - - - - - - - - - - - - .
..
:':\::'.::::'::JysDai•M::::::,;,.:~:..
:: ............,....,...,...
,:::..
':::'""·' ::. ,::·_
: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..,.

<.' :.·:.:. .:.:.:'.:.:::_::::_:::-·-----------------------.

:::::::::::::::::'bcDataA~~:::::::.;o;.:~:...::::...::::...

jit::f]:~ysDataWEEn

··.•.·.·.·.·.·

.. :t::x:::w:~~P:~taWE_I

"':''\;:{:i)i#tt"Wf·E
ba~~~lit,.
·.·.·.·.·.···:·:·:·:·:.···
sysbi~if ~"-""""~::::=-_,ir.P.':>:m:i:~--==-;.":·:·:"::::"·:·:~.:-::"'::-.re==s:::eo:-t~.::'":::.'":·::":·:··".·:·::iu.'"'"":re=s:-::eMi
i
:
i
:
epiData ~:i:~::::::::::::::::::::::::::::::::::::::::::::::::;:::i:::::::::::::::\:::::::::::::::::::::::\::::~:::::::::\:::::\:::::::::i:::i:::::::::::::::::~:

Data over EPI ' Read Data RET ·
DACK Request CACK Request

Terminate

Next Trans
W-03159-TIO

Digital Confidential 5-13

5.2.1.3 Write Block

Figure ~If!!lllBti;!>Iock

s.2.1.3.1 cacheab1e Allocate With v1ct1m
transaction in cacheable space and a victim. Write:Aij:Ji.Q~tion is ehaQ.}~p~'·
.·:· . . .
:\{\j\j\tl\!1itt:;.;..
·:-:;:;:-:-;.:
::/{@{{?:·
··::;::t{{f'.J)tt:::::::. .
0. A write block begins during the idle cyCle,J)y!!\tjw. adcfi~gs!~]?mpg valid due to
the CPU doing a probe of the Bcache. S§s-mMm:~Y rely<fu.j)cacheable
address being set up for the time it takes tlie\¢.RWttQ:. .do a· probe (a
minimum of 10 ns).
.·:::::t>>=:= ..
.·.·.·-:·=· ·:=-·:::.__;]!\;\:::.
.:/({:}/}~:~:}~://\:::·.

··:::::::;:::::;:;:;:

1. The CPU requests a write block Wi.!tb.JCJ)ii¢.Beqi!c;2.:0> .....Because sysEarlyOEEn was asserted, this trigger§..;.m.;~· assertiol-J./:i.t.f:'~TagOE and cpuDOE_
I.
::f:::ijiiit?=:::.
·=-::::::{}}/
.::::::;:::::::::::::;:;:::::::::::;:::;:::::::;:;:

2. The 21071-CA chip decodes.. ~y$Adr<31~§~:)md finds it in cacheable memory

~::iis ~:c;~q::: !:tflf~;!d~~'-~thd:efi~~~~~~i~~ ;:~

21071-CA chip =4tls'se.rts sysE~f:}yQfi~n, and asserts sysDOE to ensure
that deassertion . df ~#.i~f:lyOEEh{~lVhot race and deassert cpuDOE_l

:~o:~~tiili'~~~~'ill!lt~!!Y!~~~J's':~v:On!;!':i,~;!:!d

octaword of Wiiti=')q~P:~h The 'di~fi,i_Jag indicates a victim must be processed.

3. The CPU sees th~:::jig~-~tf.i9.rt.of c;iinwSel and places the second octaword of
write data .9~l:::fu~,,~puDati?bu$. The data is latched by the 21071-CA chip.
The 2101:t,$§1¥.t\£h~P:.:~easseft$A~ysDO E, and cpuDWSel.
4
·

~:a6lf~~1! lllf:::e'fu ~:~~p~!; !1~~;~~!.i~;~:'::~i~n

is Jls.serl.&fionfolklF/fiiher then the normal clk2F to allow additional cache

5,•\&ll::ri:!lf!~:~ data is on sysData<15:0> and is latched

···':\tij~:\:#.~Qll-CA chip. 1b prepare for the rest of the victim, bcDataA<4> is
ass~~,dlt:::::;.
•·.·.·-:::·:···=::::.;.·.

sec6fi'dfa~fotaword of the victim is received. The 21071-CA chip prepares
drive the= bus so that sysTagOEEn and sysDataOEEn are deasserted.

The read of the victim is complete. The cache tags are driven by the
21071-CA chip with the tag information for the fill data (valid and dirty).
···::::<.U.-i\j\!j!j\_\\j\\!\'.\i>:=tt:s~:ysDataWEEn and sysTagWE are asserted to write the cycle data tags.

5-14 Digital Confidential

f~~~i!r'l[F

s. The fill data is ready and.is driven on sysData<lS:O>,,Jf:f

full cache line, the fill data is simply the same as thi:Jii.~mwrittehtm!\!1cyiie
2. Otherwise, the 21071-CA chip reads a line fron.i.{liffiolM:\l@lq,Jnefg~i.it
with the write data to create an updated line of:,:di!fii. The''''CIW.?m~mal
Dcache is invalidated using cpuDlnvReq. To pfiPAt~,. to write·.·"tHil\[j~cond
octaword bcDataA<4> will change o~,::#.~F, bec'iq~~\:\Wri~ timing·:·ls being
used.
.,: ~t: : : : :t'·:_, ~: : i:i:I: ~:~=~: :,: . .··::::::':::t[[![jlj![l::_::1·:·:::::::}:::::::::::·
9. The second octaword is written with sysDatiD.~.P· bcDE(tijA.<4> is
deasserted after the write is done.
·.·.\{):/:t(\,.
.. .,
··:·:-:;:-:·
10. The cycle is acknowledged with
returned to their default state.

~'a:l\tll:.:fttche
controls are
···::::{?"

Digital Confidential 5-15

Figure 5-5
CY1

CYO

CY2

CY3

ctk1
clk2
cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuCReq
cpuCWMask

idle
:~:::· ::::::::::::::;.

:¥:i;::i}:i:::::l:l:i:::::::\:i:::::::::i:::i:}:~.......w
...:n_.te...m.-a""s...
k __--,;.,..,·~-:-,..,:-:::..,:::::..,"':,..,·::.,,::::.;;,;:::,,..Ji,;,::::;;,;.. - - - _ _ . . . , ...,_·_ _ _ __....

cpuAdr

ti:i:f:l:l:f:f:f:f:f:i:i:i;f:i:=E!iJiX.__w,..nt.-e...
ca_c_a...a.,.4r-.es...s...__ _ _...,::::.,.:::::""4·,.·...
:""_:-_ ...

,:_·: :_\. ,.<,. . : : ~" 4~l: ,.,._;1:·,. . i:'.: " '·:·!" ;: ~;'°";:

cpuOata

:..::::~:::::::::::::::::::::::::::::::::::;:::::::..

•..:;:;:;:;:;:;:;:;:;:;:~::· wD. :;. ..:::::;:;:;:;:;:::::;.;:;:;

·""·- - - - - - - -

"":·>::::::::-. :;.;:;:::::::;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:::::

.;:;:

drvSysOata
sysOOE
cpuDOE_I

_,___ _ _ _....._ _ _ ___.,i;w,\..;:;:...
: : :" :i_=.i_:_..

_,_*'l<';i_:_·i.·"":·;_:_i_;:wi_;_i_:_r..

.,.

·l.t. ..:;:;:...::;:;~r~w~rn~:;:;~:::~~'::::~. ~-----+------=L:;;;;:;;;;;;:::::::;:::::%::::::f-.

cpuOWSel
cpuCAck
cpuORAck
ioOataRdy
ioCAck
sysEarlyOEEn
sysTagOEEn
bcTagCEOE_I
..;.,...,.,:,:•:::::.·;: :::::::::-~I:tt+==::::::::::fiJ::~;Sb=:=::::::;+:::==:::=t+:::::==+::::::::;::::::}:=:=::::=:::;:::::::::::::=:::::::::::::::::::~::::::::::::::::::::;:::::::::::::;::::::::::::::~

sysTagVOP

·:···:·:·:·'.·'.·'.·'.·::::::>~·: ·:::=:::::::

sysOataOEEn
bcOataCEOE_I
cpuDinvReq

.,.,.,_ -: ,. '. ,.,;,;,:·;,;,;: ,: ,. :,:,·,;,;,_,:. , :~:...t..,. ...,.._. . :,;,;,/;.;,t;;,;t.-t..,.::·-----;...------0-----..-;,.....,.f....:i:iow:Vi:...,::::l"":i::""":;:/
_____...._______.__________.tmi
..·:·:""·:·: .,.:.'.

sysDataALEn .:::;;j:t,;,;,::::;,;,;:::..

sysDataAH:.·:·E_,.,._.,!'1. ,... '.f_:,_':..,;:~,;.~: : ·~:_:__·i:;:_:,..::::::
_ _ _ _....:_\...:m.,./:~f"'"-{~f~J~{~}~{~}._/_::::--·
·-~:::::::::::::::::\::::::·:···
bcOat~~h/~=~::;;;;:=:::.,.__ _ _-;.._ _ _ _ _;.-_ _ _ _....,__ _ _ _.....;_ _ _ _ _..;.-_ _ __,,.fiiwi·:·:·
....
:·:::~:;
.... :-:-:....~ysOa~~~~~\j.~f;,;,;J,..,.''::..,:.;,;,;.- - - " - - - - - - . . . . . __ _ _ ___...___ _ _ __.__ _ _ ___.._ _ _ _ __

. . ...._:r::::::::\~. : _.:o_.:_;~_.:~_WEJ... <:;:-:·:-:-:·:.-·· ..
··:;::::-:-·
..... ..

·::';}::: :-::;::·:· ::::::\:\Vi_·~_:'.''.-~.:$_.::.:~.::_::_''. °t'.:._E

:::::/:}:::

bcTJi~W#,il1

··:;:;:;:::;:;'.:'.·

..,.__.......,.::;o..:::::,...::::*:::::.._:::::""'.:""'}_ _ _ _ _; . . . - - - - - . . . ; . . - - - - - - ; - - - - - . . ; . - - - - - . . . . ; .
·.·:::::::::::::::::::

Idle
CPU Write

CPU Write

CPU WriteOO
Tag Probe

Note:
ioRequest is not important during this transaction.

5-16 Digital Confidential

CPU Write01

BUS
Tum around

Victim Read 0

W-03140-TIO

···.·.·.·

.....

.·::::~:~:;:;.;.;.;.;:;:~:~:~:~:~:~.;.;:::·.·.

·:·:-:-:-:-:·:·:·:·:·:·:·:=::;:;:;:;:;:;:;:;:;:;.;..

!!:~!!o~hc:~:aCi:~:!'e~i:~'!~·::m.Fi:~ J!;1:11[j~W
0

~~~~:~;e:::o~~~~~:!~~t~~~~,~~!!tr!~~~
for the time
(a
~~=!!e!;~;~s~P

wqlij.f>;~ . .?Pt111:i·fi~i~;;?~obe
···::::::::::::::::::::::::::::}:::·:·.

·.··=:{t:.:.:::··

1. The CPU requests a write block with cpuCR~q~g;(§L)3eca:iise sysEarlyOEEn was asserted, this triggers th.~A$.~~rj;ion 6/:J~if.•i.OE and cpuDOE_
I.
' :'>':':T?/\::::\t:t,.
..,,,<??' '".
2. The 21071-CA chip decodes sysAc1*~~3:5>.'iffi~J])ni.~Jt in cacheable memory
space. The CPU sees the ass~r!t~mMJ~~puDOE2t;:!:Uie first octaword of write
data is placed on the cpuDat~fJ)ui{m#f\\J~t.~hed by.,.·the 21071-CA clrip. The
21071-CA chip deasserts sy~~@flyOE~:~::::~~:t~sserts sysDOE to ensure
that deassertion 9f sysEat).YQgn will ri@Virit'e and deassert cpuDOE_l

~Zmso::~ti~~ illtii~!~,• •s:::!:~E!~o~~~v~n!!':ii~e~U:d
octaword of.write ·daQM!lmh~t.cache'''~g:::~pdicates no victim.

3. The CPU s:tl~l:\th.~,. ass;~{1iijlll~f\~p,µDW§'el and places the second octaword of
write data o'iNt.1.l,i:::~P.µPata 6u$~[:[}:flj~· data is latched by the 21071-CA chip.
The 21071-CA chi:rl::Q.,~~~~rts systJbE, and cpuDWSel. The 21071-CA chip
prepares to drive th~Pb.U.$}$~:::t}lat sysTagOEEn is deasserted.
4. The sysQ~t~\:lf]i$-:·~i4ri~~~f~ij\!ll"J;the CPU. The cache tags are driven by the
21071-G.Aii!~lHp''Witlftq~,
tag Information for the fill data (valid and dirty).
.........
·········
.·:;:·····

s.••

i!Wli.,~Z~~~~~~:~;:;g;~;~E~

/:\)Jillin~]:iw.as valid the CPU internal Dcache is invalidated using cpuDinvReq.

·"'syi.i~*=W.EEn and sysTagWE are asserted, in tum generating bcDataWE
an<fb•W=~, which write the data and tags into the cache. To prepare to

' =' ' '.1:ll7·Pi+o tlfifJ~~¢6nd octaword bcDataA<4> is asserted.

second octaword is written with sysDataWEEn.
The cycle is acknowledged with cpuCAck<2:0> and the data drivers are
returned to their default state. cpuDOE_l is reasserted because we are

"'?@::::::::::1![[!:::11:\[[·\\(jj··~:c~ne with the data bus.

5-18 Digital Confidential

Figure 5-6 Timing of CPU Write Block, cacheable, Allocate, No V.l~lm
CYO

CY1

CY2

CY3

clk1

iJ,1;111111~11lili~'ih

clk2

c:puHoldReq

cpuHddAck

/Jlj\:

~~·~:""x~
....~....~""~~----------------···_::::_:\_:j_J_:~::~/~)~\::~:~........---.. :_.:::_\_l~t~k~l~J~t.,..}.

·'\}{:@JJ\::::.;.

ioGrant
ioCmd

.•....·.·

cpuCReq
cpuCWMask

. . ::::{\l{t?:

.·.·.···.

:h:f:::::~::i:::;:;:;:;:;:;:\:;:;:;:;:\:::h:~ ~nte maSk.:::::;;:f:::;:{::(:;;;;;::;::;;:::::::::::::...
•

•

·····,:;:::::;:·:-'.·r.·.·.·,·····•·,o,•.·.•.·.•,.,

cpuAdr

:~\:i:i;i:i:i:j:i:i:!:l:\:i:i:i:\::mm<-..::w:.:.:.m::.:::e.;::c::ac;..:a=d:;ar~es=s:...--."·;,;,:"·::;;,;·:·:~·:·:·_·--~~~~.,.,__ _ _ __

cpuData

:· :::::::::::::::::::::::::::::::::::::::::::::::::"

drvSysData

\;i;\~;i~l;...;;;;~r...@~tw!M~i;i@~j~i~~l}~iH~.*~~:i:..,.:=:::"':i:i::a\--;;.----__,.

sysOOE

,..__ _ _ _,..__ _ _ _..""""'l+z:...

cpuDOE_I

~----~.....,""'
..::""::;::,...,:=:::""::=:"""'====={tttrr

a\ ·-==:=,;r.;:~;~;~~~=.-~~~;. .~;~;~. . ....;~;~:.~;~;. ..-..:;;::""i::t--+-----......
....

::::=:~::::::::~:.;~::;:;:;:;~:~~~j~;:~:~:~~;~;;;:;:~

cpuDWSel

: ~;~" -~ ~;~;~;~;~:~;:.:.:~;~;~ ;= :=:\_______

r;r.:.·:::.... ........ ........

cpuCAck
cpuDRAck
ioDataRdy
ioCAck
sysEarlyOEEn

l:::::::::::::::\:;:;:;:::::::::::\

:;.::::::i:/{/;j;l(;\;:::::::¥~_.
. . ""'10~&1..,·::,.i;};;;;;:;.,; ; .: : :. ;,;:;.,....::·.-·._ ___.__ _ _ ___..._ _ _ ___...

.
·.·.·:.·.·.·.·.·.·.·.·.·.·.·.:,.·-·..
f:l:i:\::::::::::::fJf{}j:*®#..

sysTagOEEn

:-:-:~::::::-

-----r-----..;.

"::\\}m;;:::"":::::"":::::""':/.-;-;---c;;-::·::""::.:.:.:::""'::.:.:::::""':o.:i::\r......:_ _ _ ___...

""'.:/:;::::::·:.:.·.·.· .... ·

·:::vtx:><' ''.\:~,.

bcTagCEOE_I

:.:-:-:.:-: .......

·:·:::;::::::::::::;\\:!l/,../:.:.:(.,.::(\._._:

.................

gm\ :

·······.··.·.·.:.:·•·:-:···:··

sysTagVDP

/;::::;:;:;:::;:;:::::4

;:;:;:;••;::;;:·:·:·::;:;.:::-:::-:-:::::::=:-:-:::::::-:-::::.;::.

sysDataOEEn

bcDataCEOE_IJji;.;::~::.,;;:::::;,;,.::;'-'-""'....,;;
..~:.:·:~
....;,;.;:::-;__,.~::'.:~::::..,:::·-------------------

cpuDinvReq:{~iVil\.. .:.:.;...) /

:\'fj~ji[[j

load

sysCmd
Idle

CPU Write

CPU Write CO
Tag Probe

Note:
ioRequest is not important during this transaction.

.;:::::::::::::::;::::.
CPU WriteQ1

BUS
Turnaround
W-03165-TIO

Digital Confidential 5-19

CY5

CY6

CY7

elk1

c~t!l~llf.....t1111r11~tlr

;!ilm>

elk2

cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
idle
cpuCReq $:::::::::::::::::::::::::::::::::::::::.;:::::;::<:::::::::::::::::::::::::::::::::::::::::::::::::~::::::::::::::::::::::::::::::::::::::::::::: ·~:::::::::::::::::::· ::::::::::·
cpuCWMask 14k::::i::::4::~i:::::::::::::::::::i:W:::}:::::\:::::i:::::::\:i?:?;::{\:::4:;:::::::!:::::::::::::::::::::::i:::::::i::::::~:::i:::i:J;\;\ij{l:i;);1;\t1Hit:::
cpuAdr
cpuOata
drvSysData
sysDOE
cpuOOE_I
cpuOWSel
cpuCAck
cpuORAck
iooataRdy (:=====:=::)t:;~==::::::::?::::::::::~::::::::::·:·..
. . ,:::::::::::,;~;;;;;=;~;:;;;:=:::::::=:::======\ .
.
....,.,,,,.,.,......,..,.,..,.,,,.,.,.......,,.,..,.,,,.,.,...,,.,......,,.,.,..,.,,.,.,.,.-..,.,..;~~~~

ioCA~:~::1rn:;t:=:::::::::i:::::i:::::i::::;:;:{)=}/:)?}::=j:::::::::::::::i::~::;:;:;;{;)/M:::::::::::i:::::i:i::?=:t:::i:i:;:i:;:i:::::t:i:::::::::::::!:

sysEarlyOEEi{ . .,,.:. .··
bcTagCEOE_I
sysTagVOP

··-::::>::::::::: ::::::·::::::::::-.·. •

···:-::·.:'.·:·:-.. .;.;.:-.;;-.·.

'·'.;'.',

\iliiili1iliill

:;::::=:·J:'t~:;~a.z>~·:::m·::.::=:·:·:s:::::::::::::::~-+~--<~

sysDataOi;:~W<...,:>;,;;::::;,;;:":. . . .,.
...,.........,__......._.,.....________________
bc0ata¢.ifu@f/ ,. .,·.,..:.,...,.,..·

i.,..::::;;,.;::::..,. · - - ...
-_ _ _. . . . , . . . __ _ _ _ _ _ _. . . . . , -_ _
\ilililiti!i""·:::"":::::""::::"'::::·"'.::::"""::;:

c~mM~~ t=====J;j\;=:=:=i=?:=:x:::::::::~

.:·: ·: : : .: ·:·:·.:l':s.ssDOat:'t.:.': ·:· :·;·:.:.::.:
. . :· :· . j.: :·:.: · : :.': : .': ·:.f.'::·:::.:.1·?/" .\:/j:j /:=::::::::::::::::;:/
t,,.}:,;w::::""::::.._:::::..
::::.,:\.__..;---l'l..:=:..
: : . ,: i;:" : : " : : . _: ~..::::::.;.:::::..,::i:
\~?:~~=:=~:~~::x~~:~\_______..._______.~
: ~ """"'~~ ·~.,.,.,.._,.,.,....::::~·1~;;:~:~:~~~==~..,x/
::::ii1[i1i~o.t~t~J.)rnmnm:m:::::mt%fo::::::::::::·
f:::::w
t,. ·==·"'·: :="': \. _________
)\:::::::;:::::~~sDataWEEn ."¢j]filllf::·:"
~..=:=:..: : ,. : :...: : ...:::::~i\.___ _._ _ _ _ _-.:.

;;;)\~'iltt~ ¢ao !~·: :,;.:.: : ~: : :.,.: : .,.: : o:.: i\: : : :

_____.;....______,,

bcT~9.¢.ffl~tJ

/twmfm\
.·:.·:. ,: ·:·. .,: :·,. : :·:.·:·:·~-.
............,,

~;=<;~~/ ~·:::::;;;::.::::::::;;:;:::::::::~:2~:~::;;;::;;:;~:;:2i[:;;;:;;:;:::~::::~re~se~t:~·::::::;;;;::::::::::;;;r::::::::.~:~~e~seg:t::;:.
Cache Fill
and ARB
Note:

Cache Fill

Terminate

ioRequest is not important during this transaction.

5-20 Digital Confidential

Next Trans
W-03166-TIO

;
~
!
l
'
~
'
.
"
'
j
'
;
'
t
\
l
1
1
;
·
•
?
wtjt~ b;~~~ til~~~rti~I.'
1

5.2.1.3.3 Cscheable No Allocate

Figure 5-7 shows a

~t~~~;;~:;:;,~;:~;~=~ill~~~a!":J~~,~-~:~;;
<tt\f

the address is only set up for 4 ns.
~::·:,J~1tt:::::::-. ···:::::::t\i\\\\\\\ll\,\l·\ij_l:~j\j\ttt,:,
The CPU requests a write block with cpuC.8.~di.2;Q_>. BecaP.s:e sysEarlyOEEn was asserted, this triggers the assertiCM}~f\~T.~gOE·.,.and cpuDOE_
1.
.;:;:/}~~/~\:-:·:
.. :):)::::::.:.~.:-~.::::::~~~'.::'.::.
-:::::::::.:.:.:.:.:.:... ·.;.·.·
:;'.:::::::::::::::::::::::::::::::::::::::::::..·

Digital Confidential 5-21

Figure 5-7
CYO

CY1

CY2

CY3

clk1

ctk2
cpuHoldReq
cpuHotdAck

~~
1""'====~=~:=-x:~x'.""'=~:..~._________________._·::'_<:~n-·:·_,...;,;.;,;;~....,..------.-.;,;"~:::::~::''~'''''~'~·

~:\iif;;;;;:;?F:\{;;::::::::i}i::-.~:i:\:::::\:\:\:\};;;;;JJV:f?

ioGrant
ioCmd
cpuCReq

cpuDOE_I

. ,.,.,:':::':::::::;:::::::K\:::::=:=:=:=:=:=:=:=:=:=:::::::::=;;:;:~::

idle
:;;:::· :::::::::::::::.

id e

·:::::::::::::::::::::· wnte

~- - - - "l!',':'.': : :~;:;:~:=:=:°"= =:'"'&li r5:i Jt#lt!~;!;r~ !;!;:. -.1;1;i~ ;t;1~;1;t:~:'.: : o;o: ., - .....- - - -.....
. ,,,,:::::::::,~[~!:j=~'.::;~J=M/?4

cpuDWSel

;'.:~:;:;:.:::~;:;t:~::·

cpuCAck

~ ·: :,.: :="'~#.w¥~;,;,;f~..li"'.i"":\;a.......;..-----•

:::::::::.::;:::;::: :·:·>:·:.... f:::l:i:i:l:\:i:\:!:l:i:i:f:i:l:f:~:l;l:l:\:i:=:i#t:i:i:\:i:f\

cpuDRAck
ioDataRdy
ioCAck
sysEartyOEEn

·.·.;·:·:·,

:m:::;;;;;;;;;;;;;;;;i;;;;;;;\:::::::J::~'"":,..,:,:;~@~;:""'':-: : :,. .: : ""': : :""": ,:-:.---------...:~-n}""i:i:.""-:M""'::::·""¥:""::::·"".:::i""::::.,.,:::::""::\:,.,.,...:::::~

:~:::::::::::::::::):)tt;;:::;:~:···.·

bcTagCEOE_I
sysTagVDP
sysOataOEEn

""\:):::::::::::::::::::::i

:~:::::::::-:-:-:·:-

... ~~}~)::··

\...,·:::~:;:::-::::~::::;""'::::..
:\_ _ _ _ _ __

~;,;,;.;: : ;~: : : : : :;_:·:.: :.: .:.;· _-_;: : :·~:;,·.._:•~.:.:.:t: : ;:;: ;: : : : : ;.: : : : : : : : : : : : : :~: : : : : : : : : :r: : : :~: : :~.:.:

-.-.,.,:,-::::;,-:,:::-,:,,,,-:>-::::::-:·. . .•-....·........
:\..
.~::::::·:.>:·:-:-:·:{/(fj
~

··:}·'

sysCmd

· · :·:•:·:::•.:::.:::::::::.::,!"";::;"";::::...::::""'::::..,:\-;.~-----...;--------;.

. "•::,: ;.::;.::::;.:::=.-::·:'.'.

sysTagOEEn

.;:::::::::::::::::::::::::;:;:;:;:;:;:;:::;:;:;:::;:
Idle

CPU Write

is not important during this transaction.

5-22 Digital Confidential

CPU WriteO
and ARB

CPUWrite1

Terminate

W·03170·TIO

·.;:-:::::::::-:-:

j:.l·i:·_···:•-:•·j··-~ :.:_:~ .:~_:=~.:·~::~_ .:~.:_.:':~ :~_:~

:i:.!:!;tl:l'.l l l!l ~:~:- ::I:::::.•.·_:
!ilii"i!lI'::::

!J.1:.:·::i·.::··::::_::·
.. :__:_: .·.:__: __ ..:::_::. . ::.__. __ ..__ ... ..::::_..·:: __ ..::_......:'_.:··_... ..:'.:··_.. ..:::·__ ..:·.::·::_.:':·.·::_:·
....
.. :·:·_,:.::.:.=::

.;::=:::::::::=:::::·

n~.m~-~ch;:hbl~llll~f;!(\j~[:::l[i:

5.2.1.3.4 Noncacheable A write block transaction to
identical to a write block with write allocation disabled. /:Si~FSection·::5~2MMJ.~3?
for a description of the transaction.
J:::rt:tttttt/>:::.... :-:-:;: : : :.=·:· .·. . . .
~t~t~r:=:-·

·'.='.=\t~~l{tt\~~~t::::::.

'.'.~::::h:::re ~~:::: :s::;~~~iii;~~::::O1/0
0

~~eP:~=~:i~;i:~~s:i!'"~~~~=;:~.blht41\f:ii~~~.nMA read and
·-:::::;~:~:~~~~~:~~~~~~~~~:~:::=·

1
1. The CPU requests a write block wi:l~:~ iulli4$.g:0>~·:::::13=~cause sysEarlyOEEn was asserted, this triggers.. ~i" asserii9.g#ifJ~~TagOE and cpuDOE_

I.
.J\~lil: : !:j·j:·!·: !: \:j ,=l·,: t:=:t,: : .
-"=::::=t:t::::1i::r·
2. The 21071-CA chip decode~ slfi!Adr<aa;t~:i~}Md finds it in cacheable memory

:':ite1!:~!':1p:=;:cit~dlftpa~Slt~ ~:.,e~:::;;;:.~:~e

!~~i:i;~~,:Jti-~~-C!:s ~~::~:~:~:,te:u~ a:V:!!1ts
0

::~~~ ~-~:1t~'-~n;~~,r~6:r!~~E!~e;;!1 s~~~E~:

to prevent tlie::':tlg:]~µ~ fron{flq~t!,qg. The 21071-CA chip also asserts
cpuDWSel to geFtljJ(!~~¢.9n.d ocfaW.ord of write data.

3. The CPU s~~~:::tb-~. ~;~ifu.£.{~ij!:\~f:::.cPuDWSel and places the second octaword of
write dat~=\\~#.:::ti.~@pµDafiilijijk The data is latched by the 21071-CA chip.
The 219z):~cA·:~JApfde:~serts sysDOE and cpuDWSel. The 21071-DA chip
is read)%t9.. ef\~M@e tf.@i~action next cycle, so that cpuCAck is requested

us,~g:~ 1Q11~1:ib -:t!.]!:.[·ij-_J

4. Ttj:j)):~1071%Q;l.@b4.fir~ieives ioCmd<2:0> and acknowledges the cycle with
. /tp#.QAck<2.:d5d}Jffi~?&.ache is turned off by deasserting sysTagOEEn. The
·<\[l.\fQZkDA chip is free to unload the data using the epiBus .

. :=::::l)\\\\t\\ttit:=:::::. "}f.i:ifi.jl~l®.l9:7...~-DA chip did not request a cpuCAck by this cycle, then
.: <;:;:=;·;·:_;:;:·:·: ......-;-:-_-_=.::_..·-_:_:. sysllatiiOEEn will be asserted to prevent sysData<15:0> from floating.
·. ·······=::::::::

-.·.-.-.·:-:-:-

··-:-:-:-:-·

Digital Confidential 5-23

Figure 5-8 Timing of CPU Write Block, Remote 110 Space
CYO

CY1

CY2

CY3

clk1

clk2
ioRequeat
cpuHoldReq
cpuHddAck

ioGrant
ioCmd

~~·~~=~~=~~~:~~·:·:~:=~~·--!-------;..-----!-----~)~}~/f~·:::~/~:~·~..~··..--~_........~.. ~"~·~.......;.
. :.:})t~~\~~~~~~i~i~i;i~i:::i:·:M:f.·1·:i:·:.:·z·:·:-:·:·~~;~1¥;~:~;~;:i:!:·:·:<i
1
+-----;.---=dl=e---;,..._---~:::1i::::::j:'.::::::::::.;.;.
•

.. :-:::::::::::::::::::::::::>>:·~.

cpuCReq

">:::::::- :·:·:·:·:·:·:·:·:·:::

i I

cpuCWMask
cpuAclr
cpuOata
drvSysData

1y1DOE
cpuDOE_I

cpuDWSel
cpuCAck
cpuDRAck
iolineSel
ioOataRdy
ioCAck
sysEarlyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVOP
sysOataOEEn
bcOataCEOE_I
cpuDinvReq

: :~: ~1;-.l\ •:$~;,;.:1:; ,.:_: .-: . .;·-: : :/i:.;,:_: :;,:.:. .;·.-:; ;+l;,;.;: : ; ;+:,;,;! ,·;...:;·:,·;f;.;,!i:i:.;,.;.,;..,:::~ ..:~ :...:~::"'...:::,;,;;;.;,:;:::::::i:.;,·;..::;:io'!:-:::;,;.:-:::::·::::::::::::::::::::::::::::::::::::.ll'-~"';_:::
"
..._: : :*;,;i:'_*;,;i:'_.*"':~I:W~:;i.:;,;":'!:
...

bc~P.~~J::...
::: _ _ _ _
...:_::::.;..(_t_t_:::::_::::_ __,__ _ _ _...;-_ _ _ _..,__ _ _ _.;..-_ _--.i:Jfi,..:·::;;w;;::·:=~:.

· · · · . ••.

1!;! i!l:~2~; ,i; ,i,;,;i\: '"'": \.\.l:::"":\]]-::::-:::::----------------------------:-:-:-:.·
.

::::::;::::;::::;::···

.·.·.· . . ;;;~~;~;\:

··.:-:-:-:-:-:·:-:::::::::::::

-:\#:t~WE_I
\{:}~Cmd
:·:·:·:·:::·:·:·:·::
oad ·:·:·:·:·:·:·:·:·:·:· iowr
·:·:·:·:·.·:·:·:·:·:· 1owr
":·:·:·:·:·:·:::·:·. reset
........ :rn::~piData ¥=:i:i:l:=:=:l:l:=:l:l:i:=:i:::::::::;:::i:=~==:=:=:i:i:i:=:i:=:=:=:l:=:'.:'.:=:f:=:=:=:::l:i:::::::;:::::::.:=:i:·:=:l:=:l:=:=:=:::::=:b;:l:'.:i:l:l:i:l:i:;:=:i:=:=:=:=:=:=:i::==:=~=i:i:i:=:=:l:l:i:l:i:=:i:i:i:!:=:·:·:·:·:·:·:·:M:~

;:(~~~fa:;:::::.:-·

Idle

·-:::::::::::::::::::;::::::;::::::·:

5-24 Digital Confidential

CPU Write

CPUWriteO

CPUWrite1
CACK Request

Terminate

Next TRANS
WOO on EPI
W-03167-TIO

.::::;:::::::~:::::::::.:..

:_._·::::·j·~.:~.:.'.::·.:•: l f~l!:t . .
bloclv/!ll@;~~ JlllJI'/
1

:· .-.::_::. .: : ·:·.:_.: _:·_.·.:;·:.:..;::,
: ..••_::••.::··•..:··.:···::•:..:·:·_..:· ·:·...
_
.

·:::::::;;::·

5.2.1.4

~~xie:eral a LDx_L transaction looks like a read

.::•·.t,

..: : :· •.:_.:._:..··•
· ..:·:·:·.·:· ·.:.•.:·.:· :·

"·'.·:::::::::::f]:[\[::::::·

{}:))

){\{ ·.·

:i~~!c:~ ;!~ ~~t ::!~t i~:im~~:~=lt ~~Jl~&='•i:~:.

the cache must be probed. (The DECchip .~1064 d9,i!i]!9.tprobe ori""LQi(_L or
STx_C).
\\:-.
... <}\iii:>·
.·:}'.:\}}'.=··

·.·.··:::;:::::;:::::::·:·:·:·:·:·:···

...

.
·
-:::::::::::~}:>f:Figure 5-9 shows a ··uo~fil~:::tr~nsactfon in cacheable

::;:~r;~:~:~:::t~~~~:}:·

5.2 .1.4.1 Cacheable Hit

·'.·'.·:; .-

space that hits. Data is not returned· dir~~~lY. from::::tb.)~::::~h~ to avoid an
address-to-data race through the cachEt~~~~l\\(\::.:..
·-:;:;:::::?:~:~:~:~:~'.~~::··.:.·

Although the CPU should not issue otl~~·J:i::::~~:ld.:~l~~k>whi.~h hits in the cache
will be treated as a LDx_L hit wi~~~~~.l~'~:lock B1ifJ~f:~ set.
:::~:j~j~~j~~j~~~~~::::::::::::::;::·:·:·:·:·'.:~~=~=~:~:~:;:;.·

... ·-:.:·:·:·:··

.....::}~~:::=::::::?:\·::·:·:·::·

~~~!:~~~=:u~11tG:Jl~1r!lt:e::::~~e~alid one CPU

1. The CPU requeil[~i[~J~P~....L .,~~tfi:illq@;Req<2:0>. Because sysEarlyOEEn
was asserteJ!,:-. this trifi'~t!\the as·se~pn:' of bcDataOE and bcTagOE.
Wrapped r~~·:Jlata fiffig#.~~~-d by asserting cpuCWMask<l>.

2. The LDx_L ··m~k.®.::"'P:it:Js set~::::jij:·M'.ie LDx_L locked address is loaded from
sysAdr<33:5>. lt'th.~m·2l:(J71-DA>chip is sending ClrLock on ioCmd<2:0>,
then the lockbit is ri6tW~~t;::"~mi it is forced to remain clear for as long as the
ClrLockJ~::::~~~i"!·~~:~· ·::::::::r.::.·!!!!i.![U>
The caqij,ij:::fag ·16.mcat~~t a hit. SysDataAEn is asserted as the data must be
return~4.:::n.i wt.@pped::9f4er. If the cache line is clean, data will be wrapped

~i1:!.~Bt:: :towr~:P::o~:~~~P:~i::rge buffer.
1

To
./P.i:iP.are to r·ea<Utlie::::first octaword (since it is wrapped), bcDataA<4> is
-:+:Nti:asserted.

;;;:''\I;I:.jl'~~j·t~;i:~~!::P~~e~oi:~!1'~!~~sl~~~~~Yi:::;:iy=~· is
i 11J! ii
);:!:: ::s;::~~~A chip waits for the cache data to tristate.

: <u:.:1:.;'::,::_::·.m->:::::..

::-:·:-:.;-::-:···

.·..·.::-:::·: :-:,:::' :::: ?/6. The merge buffer data is driven on sysData<15:0> and acknowledged with
. :::: ?{/))((.

cpuDRAck<2:0>.

.< i ~~! @';!;'!ie second octaword is driven and acknowledged.

Digital Confidential 5-25

8. The cycle is acknowledged with cpuCAck<2:0> and
returned to their default state.

5-26 Digital Confidential

Figure 5-9 Timing Of CPU LDx_L, Wrapped, Cacheable Hit

CYO

CY1

CY2

CY3· ·.·' .·.:_:.:_:.:_,_· . .

1_:_1:illi~~ i!i~!Ji+

=.!'_;_1..

clk1

-:-:-:-:,:}=tmr
·.:-:···:·:···:-·

clk2
cpuHoldReq
cpuHoldAck
··:·:······

ioGrant

·:·:-:·:-: ..
··.·.:.·.·.·
·.·.·

idle

ioCmd
cpuCReq

cpuAdr
cpuOata

cdO

drvSysOata
cpuOOE_I
cpuCAck
cpuORAck
ioDataRdy
ioCAck
sysEarlyOEEn

:;:::::::::::::i/:::::;::~;::;:;;::;;:::t:fp · :·:-:-:-:·:· .·.:-:,:~: •: : : : :,.,: : : ·
'/}}}::::/:'"'\:'"'::::;""'::::·"".;:;:"';::::,.;,1--------------

.. ·.·.· ... ···i:•:-:·

sysTagOEEn

·.·-:::~:::::::

bcTagCEOE_I
sysTagVDP
sysDataOEEn
bcDataCEOE_I
cpuDinvReq

sysData1h~n

-~-:-:-:·

::~:::::::;::::::::·
:~:/it'>::;:;~::::,....:::::~~··:~-·,;,;,;;;.---:·,;.;;··"'"!':::::~:;::,...:::_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

·'.1:·:·:·:-:·:·

.·.·.·.;.·....

::::::::::::::::::

.;.~:~;,;,);.;,;:O::.,.:... ;,o,·==:.,...:::;,o,?;,;;(o;.}_:' "--;..__..,.::.,.:::::;,o,:::::;.;,;:=::_::--.;.-_...l....
: : ,.: : ;...:::::....,::::.,,:;:1

\ ....
·::::....,::::.,.:::::...
:::::....
::::....
\..._.;.------..;.

_·'_' ' . .,\~X'" J;,;,;I-,. /~\;,;,;:, , ;..,;,;..,.' ' ;,;,<;,;,;J...t;,;,;H,.t_r_______ .1~•: : .:.: : :·"'·: :l.,.: : :. _: : : f
<?\:::+:/;/···
t:i :

sysoatamM>·-:

b~P.•~,~~

t\:i:·: : "': : :w: : : ·w:.·: :=:w: : \~·
\;....·:\. . . .:.______

----

::::::-:-:;::::

sv.~~w~~~t:=""=....- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

1
. . .• ;, il !!1£:ili;°..3~l.:~!f:·;,;,;!.:1·:·;,;;·i.:,~:::::;,;;:::;,;,;··.----;-------;.---------------"'------;.
.

.. ,::;::/:::>..

"'\}j~~J~~CtlWE_I
·::::~:}'

··:·:·: :-: )( sysCmd
Idle

Probe Wait

Tag Probe

Cache Read 0 : Cache Read 1 :

Note:
ioRequest, sysDOE, and cpuDWSel are not important during this transaction.

LJ-03138-TIO

Digital Confidential 5-27

CYS

CY6

CY8

CY7

clk1
clk2
cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuCReq
cpuCWMask
cpuAdr
cpuOata
drvSysData

:.::::·

:::::::::· ·:::::::::::;.
/,::::::::::::::::::::::::::::::::::::1

cpuDOE_I
cpuCAck
cpuDRAck

·.;-:-:-:-:-:-:a:-:-:-·-·.·

........ ·.·.·•·.·.·.·.·.·.·•·.·.·

•

----....;::::;.;!i'l~;~-,
.~'.~'.·" ";-~: : :;: ;:~: :;: :;: : ;:......
·.m::;i;i~~~i;:~;}~~;t~'.:::;;:;::::~-;;;;;;...;i; ;. ,./~,;,w; i;i....
;·i; ;:. ,. : ;: :. .,:),._______
.::;:~:}fj.:::::::::::~:~;::-;~!:::~:::-;::/

ioDataRdy

·.-·::::;:::~::=··

.-:=::::-..

J. :::::::;::::::::::::::::··. ..
··:·:·:·:::::::::::::.:-: ::::::::::::

~: ; ; :•i: . ,.: : ·. ,.-: : ;:;:;: : ;:;:;:•:•"a.·_ . . . . __ _ _ _ _......

t""'•:•;:;:;:•:•;:;:;:::::....

•

ioCAck
sysEarlyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVDP
sysDataOEEn
bcDataCEOE_I
cpuDinvReq

itJJ1
...

.... :·:·'.·'."' '.:} :-:·:-. .
-::·:·:-:-:-:-:·:· ..
·'.·:·:;:·:-:·

sysDataALEn
sysDataAf:l_En
.-:-=-=·:-.

~:.-:r . :r:_::--_...,.-:;,;,;;\\,..t~.....
~: - - - - - - - - - - - - - •
\~};,;,;);,;,L;,;,;: ;: ;,;,:>. ,: : :;,;,;: : :;.;,):; ,;,;:;:;:. ,J;,;,;.J,. J...f_.--....-------.------...-----

__,:::::..,.:'.f......;,;,;,/....,?'....
·

bcDataA#.f)· .._"_'\....

.·.·.·.·.·.·.·.

..................
-.-. ...·.·.
···.-.·.·.··.:-:-:-:-r:-:.-.;

.-:-::::::::·.:::::~:::;:::::::::::~...

sy~-f~::

··:·=·=·::=:ttmtmrt~rr~?=··

. . .:-:-:-:-:- ::::::tr.. : : : :. ~; n,1: : : .;,;,: ~:.,;,;: ~:.,; L" ': : " :..-.---~------;.--------------..,.________

:::::::: :;:;:;:;:::;:::::: :::::::::::;:: :J~~t-lJgCtlWE_J ::\:~ :::-:::;:: -::;::

""· ?::·: :·:::::::·:-

"·:::;::{}} : :':'.:'.: sysCmd 1111"·!:'.:-:!:'.·:·:·-.i::-::'":·:~r=:::=~im:o:"""~r.::=:--W"-~"'"v-==--""'·:::~::::i:i:::::="":::='"::::~:::,-::::no=""-W""'~'""~~-v
::::::::::::::::::::::
:-:-:-:.:-:.:-·-···

-:::@)::::~:::

:-:.:-:.:.:·:-:-:-·

·.·.·-:.:.:;:-·-·.·.·.·-;-:.:··-··

.·:-:-:-:·:}:::::·:··

BUS
Turnaround

Data Return o:
and ARB
.

Data Return 1 :

Terminate

Note:
ioRequest, sysDOE, and cpuDWSel are not important during this transaction.

5-28 Digital Confidential

Next Trans

LJ-03139-TIO

i~[! :tlf

::1::,'.,:.:.·:,=:,:._::,::_'1,:.:,::.:,,::,::.)

1.1111_:. .'·,·.::_.:·.'::-.':.:.:·.·'::·.:_,:._:

1.·•.

_:····:.·:_:····1.:..· ..

.·'·.:,._·.:·_,·_'_:~.:.=_,~-·.:·_.'~.:;_:~-=.~,:\/'

· ·':., =_.'...::__
·

tf/ff

!~~!~!·:n~:h::: ~·~~mi~L~l~:!1;:2~~!11V::ii~::~:J1111l,i\!
Figure 5-1.

f;lli.!li:~w;ug;;fi,,!~!'IJ~ilii;: ,,,

5.2.1.4.3 Noncacheable A LDx_L tran$ie.tion t<i"'rfoni.i.eh.e.able space is
identical to a read block to noncacheabl~~1iijpic.~~d~~cepfq~~'-i~iiitb~Jock bit and

lock address must be set.

· ·\f•l@litJJ!iHit, 'M!)]If>

~fO~i~~A ·~~i:~:c:r~:;~dt:ii:8\~:!~1Jt:~te~t~~ :::).

implementation may choose to treat J§f.t\)tnx_:ttiii]ii\ir~gular read block in 1/0

5.2.1.5

;~;:~ flag an error, or implem:J~'"''il@b, tijJF'
In general, a STx_C transactj§.f#J9.9~s like 'iCfi.i..fblock. Also, the transaction
may be aborted by .tb~:Jock Sit{~~~flkH:.Jeared.·::'The 21071-DA chip may
insure that STx_C:'tij:Jhem9ey alwKJii\if.@lJ~y using the ClrLock command
on ioCmd<2:0> .. For Clr:P.iil~?t9.. affecttafQBJJ STxC transaction, the Clr Lock
command must:;titJ~~sertelUin~i~iq!f:::=P.~fore~:'''t1fo first cycle of the STxC transaction
flow. (For exaffip}~~:]~N)MA r~iq)Jr#~=~t:transaction that needs to clear the lock
flag must do so befHitj.::·9.li~::::~ycle.af.t~r\::tfie ioCAck<l:O> for the DMA read. This
is because a STxC m~yHij9,~!P:tj~lly shirt in the cycle after ioCAck<l:O>.)
.. ·.:.:-:-:-:-·.;.:·.·....

5.2.1.5.1

C@¢.hlbJ-·[iJ1:iJ:" Fi~f:~/5-10 shows a STx_C transaction to cacheable

:~a: :ril~JCli~e idle cycle. address is placed on the bus
An

Cffil::::f:Y i:\!~li1i~::::~lliji''

1~:(\\.·:l!ll~!~;!l1!~i~~~:;:-;ct:e~s;~~~!e~~~J~c:~ec~~~;~~1~EEn
0
;:;fl!ij,ll!lllIIJl;,.:::~•l•!:;::::~n
a:dcf~:-~
t~~e
fi
~
~~~
;!;~ ~:2~~~!s
2
:::::::/://"
·::::::l!\!ll\CA
the transaction, and tests the LDx_L lock bit, which
chip"''H~IOgnizes

.:::/!:l'.!!!!·l:\i\\f?.
::::-::•••:::-::-:-:...

_.,:,;:,::::··:;::ls set (success). The cache tag indicates a cache hit. The 21071-CA chip
': deasserts sysEarlyOEEn, and asserts sysDOE to ensure that deassertion of
. ·:::::r-::::',:I'.:·,!i,:itt::{\.:]H:.>'· sysEarlyOEEn will not race and deassert cpuDOE_l too soon. The 21071- ·

·:::::::::m-:=:::::::::!mj\[!in\:i!il\\\\·:-=:::=::::::i~~~~blsc~i~ 8a;;:~~;~~sE~P!~~~:~~! :~ ~~: ~~:o:J:1c:aC:~~~g~l:~te
··-: ' <->_:.:tdata.

Digital Confidential 5-29

.:::::·::::::;:;.·.·

!':1: I!~= ~:i.:s: ~:i:ao~ ~ ~: ! y;~:.iH~\,;'.Z!2J11iw
deasserts sysDOE and cpuDWSel.

. :[j:,'\:.·...::Jf'/f[[[[::::,[i\,==il!·.:i\jjl:::\:tt\. : · ========:=: : : : =· ·

4. The sysData bus is tristated by the CPU. The ,,3J)Q7~~-CA chf{Vii~tts
sysDataOEEn, causing the cache to b~~ driviijg[[il~J;lata bus ...''\)/
5. The first octaword of cache data is oR:::jJ~i?At~< 1~'~fii!i.J.lim!itJatched by the
21071-CA chip. To prepare for the resfof::th.~Fdat~, bcDatii.&.<4> is asserted.
6.

!!'~~!:~: ~:~~t~s~:=:~~~=~~!il;=~~~~:. prepares

7. The cache read is complete. The ~#.lji)ll:ll~:::!~nt.~ri~:a}by the 21071-CA
chip with the tag information for...............
..@.:~tfill
dit~i#(vi.i~~tand dirty) .
·::::::·:
·-.:.:-:·:·'.·'.·'.·'.;'.:'.·'.:'.·'.·'.""

8. The fill data is ready and is .4nvl::::~rk~ysData~'i5'~(». The fill data is

:r'f::::~t:n'!:e~ ;a~~-~~'.'--~~~:=~;:~

invalidated, as th~t CPU 'filjQg}~i.Lthis cas~4~elf. sysDataWEEn and
sysTagWE are @.~irte.Q., in.turn::\~@~r.ating bcDataWE and bcTagWE,
which writes the=:=aawrn:ib.~t tags·-=tnf-4.:::m:~1t:cache. To prepare to write the
second octa,,y9f~.' bcDa~$~~\.~.s a~is:i~'d.
9. The seconcf:d~~~l~j~:::~,~ ~tt~l:!:ll:rh· sysDataWEEn.
10. The cycle is acknowJfflig~,4 with'':'cpuCAck<2:0> and the data drivers are
returned to their defii#j#:,'~t~:t~.

5-30 Digital Confidential

Figure 5-10 Timing of CPU STx_C Succeeds, Hit, Cacheable, All.QG@te
CYO

CY1

CY2

;;:~'llf!lll,ltlf~1!li•h

CY3

clk1
clk2
cpuHoldReq
cpuH01dAck

~
....
;z;:.....
::::""':·:·:.....
·:::...
·:~·....::::....__ _ _ _ _ _ _ _ _ _ _ _ _ _·._::::_'<_f_:··-·:=..,\.....::::~.;.;!:~:;.;.>..,.,::---··-:-:::_t...,t:..,:t..,f.....%
..1..,t.,...:::::..::..·...._ _
..:.. \:j:j)\:;:::::::.·.

ioGrant
ioCmd

.:.·:·::::::=::-·

Idle

idle
··:·:::::;:::::·:::::::::;:;:;:;:::.

cpuCReq
cpuCWMask

:~:::· ·:::::::::::::::·

idle

··;.·::·:·:·:·:···:·:::::::~:::'.·

:~.·:::::::::::::::::::::::::::::::::::::::::::::::A.::::~__w
. ·n_te_m
. . __a_s_k_ _ _....,:t:.,...:'"::. .

:::::,...J..,::::-..,
... _____·_
....._..........
::;_ _ _ _ __..

:'.:'.:..,..'.:=·...
:::;:_:::::...,::::.,...:::::""':::::..,...:...

cpuAdr

:>.::::::::::::::::::::::::::::::::::::::::::::::::::>.~......,s...T...
x_,e,_c....a-.c..,.Ad..,d-.res
......
s_.,.J.....

cpuData

::.::·:::::::::::::::::::::::::::::::::::::::::::::;.

··.··:·:·:·:.:-:-:=:!':::::::::::::::-

·-:··:

---··=...
= : :~: :!=.,.:=:=.....
= '=:~=: : .,.:=:=.....
:·.~.., . , , . . . . - - - - - - -

:::=:;,;,;====,...=

drvSysOata
sysOOE
cpuOOE_I
cpuOWSel
cpuCAck
cpuDRAck
ioOataRdy
ioCAck
sysEarlyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVDP
sysOataOEEn

..,:/:{': ::?;;:::=:::;}_ .

-.: \)})!!$*\ :

.-::::::::::::::::::::r ·::::;:;;~=i\=Vi=i=i=:=~::;:;:;:;:;:::::::r=:::::::~._;.__
.
- · .____
...---- - - - - - - ..__
- -____
- - - . . . __...
..
_...-_____
·.·.·.··

.·.·.·.·. -~

bcOataCEOE_I
cpuDtnvReq

Idle
STx_c Write : Write Data o
Note:
· Tag Probe
ioRequest is not important during this transaction.

Write Data 1

BUS
Turnaround

Csche Read 0
W-03130-TIO

Digital Confidential 5-31

clk1

clk2
cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuCReq

---~~~~--~~~~--~~~~--~~~~----....;,;,;~·~::;~:;:;:;~:;::...,.:-.~

cpuCWMask

.. -:-:-:-:-:· ::~~;:l:::::::::;:::::::;:::::::::::::::;:::::;:;:;::::~

cpuAdr
cpuData
drvSysData
sysDOE
cpuDOE_I
cpuDWSel
;·::·.·.

cpuCAck
cpuDRAck
ioOataRdy
ioCAck

idle

sysEarlyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVDP
sysOataOEEn

nop
: Cache Read 1
BUS
Cache Fill
Note:
Turnaround
and ARB
ioRequest is not impo"ant during this transaction.

5-32 Digital Confidential

reset
Cache Fill

Terminate

Next Trans
W-03131 ·TIO

.;ru\1Ji!l~;[1,~~'.iihr

.(t(r:::···

}~}:~:::::::

~: =.: :·:.: .:~: :·.=:'=~:.: -:. :~:·=:;·:·:.:=.:':·:·:·.:·.·.:.:·
=.::..
::
. . ..

:·::=:::=::===:====:========:====:=:::::::-.·

jff.~f::·::::~~~~:~;'.;~:~:::::~:~:=:~:~::::::::::::::.

.. ~~r
.-d\}f

:.·\~\~~Ut~~~~r=··
:.:.:·:-:.:.:.:-:.:-:.:.:.:.:.

Figure 5-11 shows a STx_C . trmis:~~io#.·.~!til:t:::::==:f:'·.,=:.::·:.:
cacheable space which misses the cache. Only the cas~J~f?i6.i~~:Jilloditl9nktlt'·

5.2.1.5.2 C8cheable Miss

=~~~~i~~o;i:;_~~:::e::!~m, or no wfiiliilii,lti~.Sirtill8r
::::;:<:n:::.::.Jf/"

. ::\{/=:==:::=
-}~?::::·

·.:~

:.: .~~.~ .=:.:

\ :::.: :.::.::..::.:::.::.':.:::.!

=
..: ·...··.

0. A STx_C begins during the idle cyclE~~{ft\h . ~4flres·;=:=:~~:::~li.~~~t~m the bus 1

CPU cycle before clklF.

···

'.':':'::::;'.;:?'"
· ·-:-·-:-:-:-:-:-:-:-:.:-=-=

.·.·.::::::;:::::::::::::--=-:··-=·=··.:-:-:·:·:::::-:;::·

1. The CPU requests a STx_C with cpuCReq~·2:~0$m:::1~~@::use ·~:;sEarlyOEEn

was asserted, this triggers the asser.tiQffi.t9.f:.bcTagQ$.:']ind:::cpuDOE_l.
·······',:-:;:·:-:-:-:.:·:·:;:·:··
······:::::······
0

2· 'f:1;1~c~~ 0~~~;1'~~:::s :nci:i~l~~~;-llj~~~~~~e~~7t1~
chip recognizes the transactiqgM..
lock bit, which is set
n~U~.~ts the·'L~2t

:~~::::~~:~~:1:1iE~J!r11ii.~?.;~ ~~~~:.;.~:~!if

there is a victiif~;f'victiDlf~\-~;~locaifon is disabled, respectively.
·-::'.\/{~ .::::)::::::;::-

Digital Confidential 5-33

.. :::::····

····:·.·.·.-\::::::::::==:::;:::::~:/:::::·

Figure 5-11 Timlng

CPU STx_c

CYO

su~Hds,

CY1

Miu,

1
cachN~e. ~! ~t!~a!'.;:;: :1!1 ; w'

CY3

CY2

clk1
clk2
cpuHoldReq
:-1

.... :-:.:·.·.

cpuHoldAck

-·-:.:-•-:·

}~:};:~ .. :-:.:-:-:-:-:-.

ioGrant

-:-:-:-:::-:-..

idle

.. ·.·.··:::;::::: ~~~:::::::!::::::::::::;:::::~::::.

ioCmd
cpuCReq
cpuCWMask
cpuAdr
cpuOata

·.·

drvSysData
sysDOE
cpuDOE_I
cpuOWSel
cpuCAck
cpuORAck
ioDataRdy
ioCAck
$ysEarlyOEEn

:~::::;:::::::::::::::::::::::::::);;;;<;WB......1a""'1e_.....·.....-:··...
-=:::...
::::~.....\ ...
:::::...
::~:~...;:;::....~;=--::""'. : - - - - - - - - - - - - - - - - -....

,~:::::;:::::::'.}::\:i:\:'.::;(:::\:::::\:;1¢illl···•···;••.•,.,,,.,.,,.,,.==·:.

·=·==w:rJ~:i,:::~::::==··
h::;::::::::::i:··:

$Y$TagOEEn
bcTagCEOE_I

.·:· . ;::::::'::;::=='~:· ·:··:·:i:J::=:::;:::::j:'.:\::::::::::f::::::::~;::}:::::::'.:::::::\:::;:,:::;:::::::::::::::::::+:::::::\:'.:\::::;:::::),:'.:::;:::::::::::::}:i:'.:::::::=:;:::i:::\:::::::::;:::::\:::::;:::~:

$ysTagVDP

:<::O::':'.:':'::::;::::. .:· ..:.:::;:::::::::::=::::>

sy$0ataOEEn

J::::::::::;::::::::::1

bcDataCEOE_I
cpuDinvReq

--·-=.i.,.).,.f..,.?.,.?.,,.I..,.(_..,.,.,.,.,..·=..,t.,.i...I,..t....:-----r-------t-------.. . . .A....:::::...: :...·: :....: : :., : '/

sysDataALEn /.,;;;t.,.::,...,.
..
D taAHE

/'.f\)'"

·=-==tJ){\ .:=:=:'.::.:-::::\\%/

sy:co::,mri~:;ill\ll~i!~\l\:::..

·-:~:. :::::::::::;::::::::-:

... ·.~ysDataWE~W'.:=_,.:_.:_.'>"4_: ~.....
=:::.:=..,.=
:' .'.'..,.::'::""'::~.:...
·=-=-·_ _...___ _ _ __.__ _ _ _ _ _.___ _ _ _...__ _ _ ___,_ _ _ _ _.,._
..·.·.-.· .

. ·.·

..·.i~:.~-::~-~:\-.~:-.·:?-· .:;::::::-·
.. ~~~t•we_1 ·-=~::::r~:t~r==:===.
::::::::::

.·.·.·.·..·.·-:·:-:·:··

:-:-:-::-:-::\)~~~t~E

-:·:·:

·.=.·=··

··=·=:=:=:::':~·
~-..-...~~;,;,;,;.-----;-------;-------;;-------;-------..

bcT~~I
-:.:·:-:·:.:.·.·. ·.·.··
....... :·:·:<::;:::-:-·
··-.:-:-:-:-:-:·:;::::::::::::::;::::;:::::::::<:'.·:<·

Idle

STx_C Write

WriteOataO

.. ·.:. ::::::~:}~:~:~:::~~~\~~~~~:~(}~::·

Note:
ioRequest is not important during this transaction.

5-34 Digital Confidential

Write Data 1

BUS
Turnaround

Cache Read O

W·03128·TIO

CY6

CY7

CYB

CY9

clk1
clk2

cpuHoldReq
cpuHoldAck
ioGrant

idle

ioCmd
cpuCReq
cpuCWMask
cpuAdr
cpuData
drvSysData
sys DOE
cpuDOE_I
cpuOWSel
cpuCAck
cpuORAck
ioDataAdy

idle

ioCAck
sysEartyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVDP
sysDataOEEn

-:::::::::::::?\:::):-:··.··
~
:(:::::i;::::i:i:i:::::::::::i:J:::::=::::j:\t--<C=:z.~..-,:.;:>::::z::::2:Y~}~~o[_===========)---+--~~
/);;;;;;;;;;~;;;;;;;~:;f /=
.: ::-: : -: :-: :-:-:-: :-:-:-·
J.:::::;:;:;:;:::::::::4

: t:,:.:.~:.-=:.:.·:.~::'_~.';.·!.!.:.-:·~.-~j.:.': ';~.·.·:

bcOataCEOE_I

,,;,;,,.:;:}::'
°::::':' !::.1-1.ii
.
.•:.::.•:.:•.\.',.·.. ...:...:._...
,,.:, ·.·.· ..
...
.. O::~;.;,!'· i)t.ll';:,.\;;:i,,..:i:(,,..:'.:(..
:::(:..
t ..::;:,.i:::\,.:\.___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
..•

cpuDinvReq

\j:;;;;;;;;;;;;t\ .,:f: : : : : : : ·

sysDataALEn
sysoataAHEn

-:-;·:·:·:·:-:-:·:·:·:· :::::}:;:;::··

· : : : : : : :}

t00f( · : <i ~'. ~;~.-r.~"'')httf}:::::::-:..
1.~.'.'. :{'._;~_:'._i~;_:'._·;.:=_:~_: _: _._: _·_:·.:=.·'.:.: _:.·.:.:=_:.: _'=.:._:.:,_'·.:.:·.:.:·.:.: _:.:=_/: :'
.

bcOataA:;~.\!JV

J.,:::::::::::::::::::::j

.}~~~~~~{~}

sysDatawertn:::::..::~:::::::

f: : : : : ~: : : : : f

f: : : : : : : : : : /

~:::::::::;::::~:::::(\

'"' = -= : :·-=·= :~w: : :w: : :;:;:.: \. ._

,(::::::::::::::::::::::::::::::q

________

1,,J=:"'=M='l'!li/.----~\l~·=i...,=.,;,;!==""'=Wli:~...__ _ _ _ _ _ __
~:::::::::::::::::::::(\

bcoai~W@~j!~ij~-;~:..,;: ;...t>-.,,
. .-.. ------------~"":::"':::::~:::::;::::::::::::!:

. . tt:if::1r:::1:!1Iw1~~~~''<. .

: :~~t;,;,;-: : ~: : :" ',.:,.-....__ _ _ __ .,; :o:= -=: : :w:,: :=.:0:0:=:=:~= : :1

:::::::::

·===::::t:qy:J}

1.,.:::i:...
i:::·...
::1::;;,;:!:!:......

.......... '..
::::::::::::::::::::;:

,:,:::::~~T~~~l:-1

:vHKH=i=\

··::;::{~~~~~d W!:",,......-,,......-,v-~~~....m,......-,-.v-~w~rs=s"""'.:...,.::::...,.:~:,...::::·"".::::"":::...--==---.......,....,.....u-"'=~"""'.......,.....,..~..,.re'"'s.,.e""t'"Yr.::""::::""::::""::::"":::::""::•.-""re'""s-et..-.
-:·:·:····::::::

:.:.:::: }~:~:~:~::·:

Cache Read 1

BUS
Turnaround

Cache Fill
and ARB

Note:
ioRequest is not important during this transaction.

Cache Fill

Terminate

Next Trans

W-03129-TIO

Digital Confidential

5~5

.l::1:iif/f'
····:::::::::::::::::;:···

0. A STx_C begins during the idle cycle. An addressd~!fplac'ed{~#.WJ.h~tbus 1
CPU cycle before clklF.
..
.,J[i!l jl[[li l[::!tl:i::!\....
"'·':'::::(\\\:l [i l l ijlil\[1}··
1. The CPU requests a STx_C with cpu~,q<2:0$}\1,i~i~~ sysEarlyOEEn
was asserted, this triggers the assertioJ):?o(JW.~ag(fEmijff.ijj~l[~pµpOE_l.
·.·.·
.·.·.·.···-'·>:·>:·.
....:;:;:;:;:;:;:-:;:;:;:;:;:;::::::::...

A STx_C .9~gjtjij:)4.µr.i::i::lh~l![~We cycle. An address is placed on the bus 1
CPU cy~l~mhetdf~[:~i,l}tlF,
as ltfo CPU did not probe the cache.
..·.·.·.·.·.·.·.·.·.·.
.·.·····.·.·.·
·.·

. 1. The cpg:[:~eqµ'-~t~'' tij~::~:·ti-ansaction with cpuCReq<2:0>. Because
sysEarJYQJUi.f.1@was ~~~irted, this triggers the assertion of bcTagOE and

c~B9Eil~11:::i:1:~::1::::\t:::::::tf[~::::::::1:,,,·

2...ADli~!!21011~6W::~~hi~:4~·cognizes the transaction and tests the LDx_L lock bit,
.:)]!wlii.ll. is clear (fail). The latched write data is discarded. The 21071...,,c~:::9.l.l~ik4.easserts sysEarlyOEEn, and acknowledges the cycle with
cpuCA.#i~)Q?.. CpuDOE_l may still be asserted after the CPU receives
cpU:d~;f;k'.2:0>. This is not a problem, as the CPU will tristate its
''''''rl·..~·u.0~ 0 before accessing the cache.

5-36 Digital Confidential

Figure 5-12· Timing of CPU _STx_C Falls
CYO

CY1

CY2

clk1
·-:•:\:~::::::::::;:::·

dk2

...

cpuHoldReq
cpuHoldAck
ioGrant

~
....
w....
·:·=·=·.-=·=·=·....
:·:·:=:--------·;,;,;...··--.,;,;,;····:.,..:/;:..,.:
.... _ _........,._...
f:::::f:(;;;;::;p:1:::;;::::;:::{::::::\:::\::::::::::~;-:

ioCmd
cpUCReq
cpuCWMask
cpuAdr
cpuOata
cpuOata
drvSysData
sysOOE
cpuOOE_I
cpuOWSel
cpuCAck

·-·-:-:-:-;. _.;.;.·
.-:-:-:·:·.
··-:::::::::::::11i:t:t\:;:;:::;:::m:::;:\:::i:::::::i:;:::!::::===::i
:+.
- - - · - ·.....,.~;,;;·:-~::•::,;,o::::.,..::-.---..-,..~:::~:::_;_."'::::l,IO::.::;.;.;.::~::::~;::::::::·

cpuORACI!.::: ..·.

. . ·::: :;::;:::::::::::::::-

... ·.· ·~

... :::_::;::.::::::::-·--.·.·.· ·.

ioOata_l~:•l.WUW;;::::;'.:;:'.i:!:'.i:!::::::::{\-:· "·:·:··· ·:::-:·:·:··-: :-·-::···

ioc~ ~:·: : : ~>I~ :=: :/:= : : : : : : : ;: = = := [: :;-~:1~,;,;: ~,. :_:;~: :•"'": ;.-v.*" '=:= "':= = " =: :"':=: :" ': =:"'=: : " = =;"'=:=: " ': =:"': = " =: :="':=: ." '·=:=:"': :i" =: : " :=: :" ': =:" ': :~:
y;;;;;;;;;;;;;;;;;;:;;;/;/:\:1#lliJ

sysEarlyOEEn

:: '.;:;:::'"··

\:;:::::::::::;:;\ :

···.··.·.·.;.·.

·-:-:.:-:-:::::::::::::i:·::

sysTagOEEn
bcTagCEOl;,;J: ·.·.•.·.·.·.· ·

))/{::~:}:::-.·.

7. .

SYS!!liNP.~f: ·:*•f:.,.;.f•.. ±:.:·:*-:·:f.;.·.f·---:-.....:;;·{::[::::·).::[::::[::::[::::]:::::[::::]l:~::[::::]:::::[:::;}(:·]::::]::::)(.:[:::::]::::[;:;:;~::.~{j·::]::::[:::::]::::[::;::[::::[:::::[::::!:~:
sysq~~En

bc0#~~~-1 . _:~::/?::··

;.)}j

·.·.·.·.·. .:·: •

c:P~,w~JF:?''
.;.:.:::.:-.-:-.

·.·.·.·.·.··et.j··-·.·-:!-:-.

-:=:/{}{~~?:

A:;:·:·:·:i:i:·:·:·:i:·:·:;:;:;:;:J

:·.:i :!!..l!·:~::::::@::::i:.:~~::""'\;\\;,;;i;,;,::;:f~:;:::""'::::""n;,;;r~r""'·~-----------.......i:.:.:.:. :.:.:.:.;.:.:.:.:.a:.:.:=: : w:;: :"=~:

. /{j{@)f\ bcOataA<4> ·_:-=:-:::::-::::-::·=-_:···_··-------------------""•""·::::..,:·:·"":'.:·
·::::::::::::::::::'JH!~ll~(;
·-="':MMW:~\t:

..,: ______________________

bcTagcuwE:J"
sysCmd

:~:::::::::::::::::::::::::::::::::::::::;:;::::::~ nop *:;:;:;::::::::::::::~
Idle

CPU STx_C

Note:
ioRequest is not important during this transactio.n.

Indicate Fail

Next TRANS

LJ-03164· TIO

Digital Confidential 5-37

5.2.1.6 Barrier_

Figure 5-13 shows a memory barrier transaction.

o. ~~r;~~e~~:e~~n:£!: :~~~~~~di~ ad~-~•:;;;;:: ~!lltl•tus
······

··::::::::::::::::::;:::;:::::::::::::·.

:~~~~o~i~e!~s ~:s!;:;1:,8:!~nmW::ril\9~Qi~~-U:~E to

tum on. (This is done to avoid having the datah~g\::~_ buses float, because
the CPU does not drive the data or J@g~(gµring the~~)tf.~sactions.)

2
·

~:e~~o~~J!>gAc~~g:~r~e~~•!!IJll;;,~i~~~~:C~~~~~
also preempt the barrier at tb.!lfam!#.~:::_The 2f0f:\Ji.CA chip deasserts
sysEarlyOEEn and asserts syi.QitiQ$.fi~APld sysTagOEEn.

3·~:i,::g~~~~~~:~:!1tll~:~~:!,lfe::2:e·c::1~::
cpuCAck<2:0>. ::f:::::Jf?

·:·:-=:::::::::;:::::':::t:I\::-.

··:::::::::::tt·::1ii·:1tt:::.:-.

5-38 Digital Confidential

Figure 5-13 Timing of CPU Barrier or Fetch or FetchM
CYO

CY1

CY2

·.·:;:;::::.:··

jll''~"llt11t111111i:

CY3

clk1
clk2

"·:::::::+/rrnltt>.

cpuHoldReq
cpuHoldAck
!oGrant
loCmd
cpuCReq

cpuOata
drvSysOata
sysDOE
cpuOOE_I
cpuOWSel
cpuCAck
cpuORAck
ioDataRdy

sysTagOEEn

bcTagCEOE_I

:/;:::::;:;/

\iliilllliilli

-~/:....
::::::'""':::::::-.;,;t:~::::;.-\::-:::.::_·.·.··~:~~;:;;;;::~;;:;:;:;:::::;:::::;:::;m::::::::::::::;:;:::::::::::::::;:::::::::::::::;:;:;:;:;<:;:::;::::::::::::::::::::~
sysOataOEEn
.·.·...::::?::::::.:.
.··::::::r
J::,,,,,,,:::~=:=::::;:f
\::'===}:'='='=:\
.
bcDataCEOE_I )??
.;:i?::::··, ,\.~/i>Mt+,;;:\~-------------..1i:l:.;,;.::::O,;,/f:::;:f ~
sysTagVDP

. .: : : : : : :

:::::;:::;:;:;:;::.

sysDat~!=n ··tt:::/:ifa::'::::::;;:::::··

:::::\(:{::

cpuDlnvReq

:\f}::
·.·.:.a;-·.·.·.·.

:::::::::

k:::::::::::::::::::::::::::::::::J

: : : : : : : : : :·.·. :·:::::t:tt:]:::t::.::::::::::::tI:t=:/r::··

sy~~:ir
0\:\,,.,.,.,.,,,,,....

;;

~;;·
...: ;,-:;:;-:;.;.-.- - - - - - - - - - - - - - - - - - - - - - - - - .
.

..·:::::::::::::?~~~~~~~~~~;}~=~::::::;::::::....
.·.·.·...·::·:·:·:

·:·:r:id\)::.·:

··::::~:;::::::;:r::;::::::=:\:;

·:::/jff\~sTagwif\'.~:~:-.?.,.,;:;:.,..;:!:'-.?.,.:}.,._;:::....· - - - - - - - - - - - - - - - - - - - - - - - :{/ sysCmd
Idle

Stan TRANS

CACK Request

. ·'·::::::.;:/~((:}:::}:}:4ote:
· · :::::::::;:::::;:::;:::::;:J~uest and cpuCWMask are not important during this transaction.

Terminate

Next TRANS

W-03144-TIO

Digital Confidential 5-39

...::::;::::::::;:;:::.

5.2.1.7

F~h.

.·>:·:;:;:;:·:·:-:·:·:·:··· :-:·;.,

FmchM

,, ,,

1l l~ l l!~'.'.'.~:1 1'~t-(r

These CPU transactions are not shown in a figure, buk~#.i)faijj\~:µppofilg@M?.
desired by a particular implementation. The simplest.:\\).J#ple~!lti.t.i9P fooks

\\fat

like a STx_C fail:

1f(~!l11i1fJtb Wj11f~!flitjc

0. A fetch or fetchM begins during the =1anFcy¢.l~~- An adq'ffijjj§:_ placed on the
bus 1 CPU cycle before clklF, but is igiloti~~:\!ill\i\.:=:::\>:=···.·.·.·::::;;;;:;i·i·i...·::i·>
1. The CPU requests the transaction with cp~CR~q~g;Q?.· Be.cause
sysEarlyOEEn was asserted, this ttjggi.#$.d:>.cDafaQ~(:::~'1 bcTagOE to

tum on. (This is done to avoid hayw.J.g!\lttti\!\9.1.t.~:-.~nd fag{buses float, because
the CPU does not drive the data df::::~gs dug~\)\~b.~.se transactions.)

2. A wait state is performed.
3. The 21071-CA chip

5.2.2

.·:;:::;::::/:f~:}.

":::::\?t~ff~f{>

:=({:::=:=::::::::::::: .. ....

"'.·:::{{::::··

recogni.~Ji.1:\~hj;:\\[fl.ii¢tj9n, deasserts sysEarlyOEEn,

DMA~:a:::::~;fj;e ~i--1~;;:~·!9>·

After DMA wins arbitratii#;.:::it:..may . 1tdi~it~t:a transaction with the 21071-

~Zn::tio~:!~--~~~"~~~~s, tlil{ only unit of transfer for DMA
··.;.:.:·:·: :'.:'.:::::::::;::::::::::;:-.

····::::::::::;

5.2.2.1 OMA Idle
When DMA has the b~~,U·tij~::·OJ.?:lJ is isolated by holding cpuDWSel and
sysEarlyOEE:~ni$:1]"4~~§~~;rte"dJm~~Vcache is prepared for a probe by the 21071CA chip as~~tl~rlif:':sy~J.)ita9EErf.and sysTagOEEn in the first cycle that a
DMA tran§:49.~fon m~)lb~@p. The cache also drives the data bus in case a
DMA rea&g{l(\~~:-~_'._.'._:'._;[:)ilts 1$.e{cache.
:_::_::·. :.::.::_::.::.· ..
.
-:·:·:·::::::::·:-:-·

·-:::::::::::::::::::;:::::::::····

5.2.2.2 DM_~L~ICI
·.·:-:-:-:;:::::::;:~;}~;~

./:}{~}
<·:·:::::::::::·:·

·.·.·.·.·'.·>.·.-. :-{~~f~t~~:?{(:::::::::::::.:-:-:·

..;:;:;·:··;:;:;:;:;:;:;/:~:\~:~::·:.

di•i'.!Jtii@ls;:~'!lil!~eable Hit Figure 5-14 shows a DMA read transaction in

. ::::::::/·.·::::::··. .·.. ···:::=:::::{[[·\1ll~~eabl~=:=:,PfoE~l!·:~hat hits .
.. . . .·...
· : : : : :;: : : : : : . .

J.MlJrhe transaetion begins with the DMA having the bus, as indicated by the
:fi]l}lassertion of ioGrant.

. "::\U;\-\j\!llj)j; :; :,_. :::::::: /t!l!\[. \ill[r.==-· The 21071-DA chip requests a DMA read with ioCmd<2:0>, places the

::;:<@:.=:::rni?Il'=:::::-. address on sysAdr<33:5>, and points to a line to be loaded in the DMA
<:=::t:t/t)><r.ead and 1/0 write buffer with ioLineSel<l:O>.

5-40 Digital Confidential

:·:·:·:·:·:·:·:.. .

1,.:_:1,d~.•l:1,.•.:I;J:..:.::.I_~>-;.:;:· ·:~ :•·:··:.:•:~:l(:\.•·.•·;i.:;=.:j:.:_.:· =~_=:.=:~:_-:~::'~.=·:~:~::_::.:~=~.:~·;.:=~:~.-.·:·:.:=:~.=·

A
;1.::.;·•.

.:.:··_:.·:.•.

=:··.:.:•·.··..
:.•:•::•:.::·
: ...
..

.{:}~{/

..: ,f.=..:' . . . .. .. .... .. . . ::.·.. . ::·.. ..==_.=·: · : ·: :=:=.: : :

-::::::::::=~:

2. The 21071-CA chip decodes sysAdr<33:5> and finds it. ..it.t. ~acheab.]ij!::m.~@~I
space. The 21071-CA chip waits for the cache prob.:~Gwhi.i\tJ~didi~~::::~#!)?
cache hit. The first octaword of data is already or#t~ifd4f@fmµ~t.:·.so . 'itfi's..
loaded into the DMA read buffer. (If the read w~~\wfapped;\tb~!)lJ~tA would
be invalid, and would have to be loaded in th~/Q~t\l\cycle.) T1i£V2$.p71-DA
as it sees the assertion of ioDataRdy~,JW~;t.prepafi:):f.9.rfaf~~(iing the ·.second
octaword, bcDataA<4> is asserted. :{JI]/.../\::...
.. ::::t:t?=:=::::t::n:::::::. :·.
3. The 21071-CA chip loads the second o~~aWb.ta·::ir::r~.ad:;::dlHM:!:iiito the DMA
read buffer, and indicates data ready with ioD~~l.9.)h_The.lransaction is

£~~:~~~1t:cr:~f!:~:tia~-~~!ffr:ea~~ra!:'
..·.·.·

·· ..·...:..·.·.·.··:-:-:·::...·.

··::::::::n:::lliif:.

······.· ·::/}:1:..
···:·:·'.·'.·'.·:::·-·.·.-.·'.·:::::::::....·.·.·.·.·.·.
.·.·-;.·.·.·.·.·.·.·.·=:·::::::::::::::·:·:·:·::···········:··

::::~=i~~~~~r:--·
.)\::::::::::::::

::/{{}ft{\.

·-·-- - ·- - - -- - ·- - ·- -- -· - - ·.

· : : q: t.~=.~ - .~_: : : ~=.: .:,~.:=.':~-:~::·:'.:=·~:~ :~_:.:·.·:_.~_.:··:.:~:·.:~: :~:.::.:.·,·.:··:.:.·.·
..

...

:'.•::•. •.• .• •. • :'.••.

· :·: :t :t:·: .:~i\:=:[=: i:t:\:t: =: : : -.
···:::::=}\~~If~{\::::...
·-:-:=:=:-:-:-:::=:::-:

Digital Confidential 5-41

Figure 5-14 Timing of OMA Read, C&cheable, Hit
CYO

CY1

CY2

CY3

clk1
clk2
ioRequest
cpuHoldReq
cpuHoldAck
ioGrant
ioCmd

cpuAdr

drvSysOata
sys DOE
cpuOOE_I
cpuDWSel
cpuORAck
cpuCAck
iolineSel
ioOataRdy
ioCAck
sysEarlyOEEn

~_,.\:j~;,;,:{;..;.;\_.::':...:- .,.,___·_·.·, . ·:_t...f_.\...f;,;,};.;.)_:'"·-.....,.------.------.,.

sysTagOEEn

~::i:i::::::/:::::(:(:::'.:i::;:;:;::i:'.::/:?:

bcTagCEOE_I

t::::::::::::::::::::::::::::::::::::::::;:;:::::i::

sysTagVOP

:b:::::):::?;)\;/;/)~~:;:;:""'::::~>;;;f~:::;;,....;===,....:=:=:~x....h:'."!'it:- - .- - " xn:=:'": :;.,. . ·:=:=:i:o:~= o.':':=:=:'"=: :·,. . ·= = ,. . : : o.':':=:=:'"= = =,. . = = " -: : :o.':'=:=:'"=:=:="°=~=
. ·-:.··

:~:::::::::::::::;::::::>>>::::::'.:'.:'.:'.::::;:;:~::::::.·

sysOataOEEn

bcOataCEOE_l::::::J:~i{:::::::::i:i:i:::::::;:'.:=:!~::i:Ik~::i:::::/:i:\:::::i::::::\
cpuOi~vReq ...:~:/:::-::::: :::::::

~======~:=i=:=:=:=::::i:i:::::::N:::::\:i::~:

::::;:::;::::::;:

syso~~t;~. :t\r:):\?\::-.·...... <:::::/§:)>
;:::;:::::::::::::;--

s~,g~fmEn

·:::::::::~~~~>

···::::::::::::;f{f

:::ftff=··

.·. ·>:::::::;;:;::·:·:;.-.

:~;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:-

~y~ti~W.M~> . . .

tfmm\...,::·=
...
==·=·-=:==....
=====...
=:=·...- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

bcoa~WJ4.~j~:.:.: .i:.,:·:.·~.~.:.·:·:.·:.: .: ;\: :

· •: : : - ::?;'.;_)(•

+.;.;;,~~----=--------;..------~-----i--------~
···.·.···

.
: OMA has Cache : OMA Address , Tag Probe
'

: Cache Read 0
ancl cpuC1NMlask are not important during this transaction.

5-42 Digital Confidential

rddmas ·.;::::::::::::::::::::. rd mas·
Cache Read 1 : Next Trans
: epi Data Valid
Next Cycle
W-03147-TIO

s2.2.22

~hnble m~ ~15
Mn

cacheable space that misses.

shows a DMA

1
r~ 4 :t'l~~:111 irv

kiif'i(if:}\!l~,,Jl:lll!;;:;::\jjl) ;&r

0. The transaction begins with the DMA having Jih.~?bu~ as indicat~u:::by the
assertion of ioGrant.
., j:~: .\i\~[~!i}=· ===·.. . · = :=<: \ !i i!:i =i.·1.:1).:j1~[i\[ i~it= = ..
· =·=-·
1. The 21071-DA chip requests a DMA fead,=:iHtb-: . ioCni'd{g~:~l:places the

:::Je:do~~y~~:~:;' ~~ r:~7!:~~1 !'~9~~1·1·:~~it!,:acrna:::~i{ the DMA
2. The 21071-CA.chip decodes sysAdr~aa~i.~kMP ~::a~li!~t:.ii::==cacheable memory
space. Also, the cache tag is avail.~l~ftH~IiiJ.~.,. and"''ihdicates a cache

::s~ad data could be ret~l~i~~::;~~IJJ~ip in this cycle,

::~:;"ru!~ ~::::i:: ~~l~J~Ntc~=~:~o~~::y be
8

released to use tb.~tcache?tJf!:ijQ:ktb:e 21071~¢.A chip deasserts cpuHoldReq,
sysTagOEEn, ad.4!!!$.yspatadE~n@:iai~.~arlyOEEn is asserted so that if the
CPU starts an eifornl.1Htr~sacti()#.ial¥t:tag and sysData buses will not

~~~a~C:~l'l°:·~·~·2'.4i'~I!:~ r9f~hg from a released CPU to a DMA
··.·:.·.·.·.··:·:·:-:.:-:::::-:-:-:.

4. The 21on-cA=:=:6il~p.,!W:~it..~ ro~''i~t{.ij.\:a=ata to return.
5. The first octaword.''dt::f~idhiata is=·=-loaded into the DMA read and 1/0 write

buffer. Tl}~r:g:it:1+.t:G.A ·~hipi::iP.4.icates the transfer by asserting ioDataRdy.
6. The 21gzJ.l~eA:::¢!\~\:'~~..!.ts f~:~::;:the second quadword of read data to return.

7. The seiih.a. ocUJ.W~rdi!li·i.itoaded into the DMA read and 110 write buffer and
is JwJuii.wJ~dgfd wi~b.!j!\~gDataRdy. The transaction is acknowledged with

::!:~~·k<fH\1~l;,;·.ll!it··.l:\.[···111·it·=.11·:.=:::::m::=:··

..:::::::;:::;::::::::::..:::..

Digital Confidential 5-43

Figure 5-15 Timing of OMA Read, Cscheable, Miss
CYO

CY1

CY3

CY2

dk1
ctk2
loRequest

'\!::

cpuHoldReq
cpuHoldAck

·:·:-:·.
....

$iilliJ'

·.·.· ...

·>-:::;:::::::::· .. ,.·.;.·.·.;:;, ..

~=:=:=:w:::Jorm:::[i:::~:i\[:{::::

ioGrant
loCmd
cpuAdr
cpuData

:i:::::::;:;:::::;:;:;:::::::::::::;:;:;:;:;:;:;:~;:;:;:;:;::::j::::;:;:::::::;:;:;::::::;'.'.;;:~~:=:;;;;;;;;;:::~;:;t;;;;;;;;;:;;::~=::'.;;;:;'.;'.~
.• . '. .: '. j _ .: _:~ ~:.: '. '.'. = ,:=•:.• :
.•

drvSysOata

:::-:-:-:·:·.

sysOOE
4;.·.;.···

cpuOOE_I

:-:-:-:-·.;.·.·· :-:::::::::;:;:;:;.,
.·.·.·.· ...¥.·.·.·.·.·.·.

cpuOWSel
cpuDRAck
cpuCAck
ioUneSel
ioOataRdy
ioCAck
sysEarlyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVOP

+:\::;::;:;:::::::i:::::i:i:::::::::;:;:)~:::t:i:;{;:;:::;::::~ .·.·.·.·... ·
:~:;:::::::::;::::::::::::::::::~;:::::::::::::::

·::::;:;::::::::::::::::::::. :::::::::~::::;:::::::::::·

miss

sysDataOEEn .•• =di=J:'.{:;f::/{;:;:i:::!:!:i.mmJ . ··•:•:•:•:•·.=•:•:•:•··

bcOataCEOE_/]=F=/~::;:;:;:::::::::::;:;:;;:;;;~;;:kF:;:::::::::::?::::::\
cpuDinvR~:}(k\•

· · :•:•:•:•'.•:•

·.·.··:1······

sysD~LEn •:::;:<::::::/::=::::::;::\:/
.. . .

sys6'~n

·:•:•:•:•:•:•:•:>:
·.·.·.·.·.· ..

./)\:)

... \.~.~ ~-~ ~ ~-~ ~-~ ~-~ ~-~ ~-~ ~-~ ~-~ ~-~ ~-~ .: .: .•:.·:.· :.· •.·:.· :.· .....·•.·•.· ;_: ..:--:......:::.
-.:

.•:'\['-~<4> =~=======:+:M:iwKi.i,:[:::::·=·
···<#•~~ '"Sm:m\..,:::;:.:.:.::;:;:.:.:::::..,:::;:.:.:.::.~------------------------

: OMA has Cache :

OMA Address

Tag Probe

:. CPU Release

Note:
cpuCReq,cpuCWMask are not important during this transaction.

5-44 Digital Confidential

Wait ROR

W-03142-TIO

CY5

CY6

CY7

clk1
clk2
lo Request
cpuHoldReq
cpuHoldAck
loGrant
ioCmd
cpuAdr
cpuOata
drvSysOata
sysOOE
cpuOOE_I
cpuOWSel
cpuORAc:k
cpuCAc:k

o@:W Buffll' Une

loUneSel
ioOataRdy

~:1::::::::::::::::::::::::::::::::::::::::::::1:

··:·:::::::::;:::::;:::;:::::,:;::::::...

l::::J;Jit::::::;:1::::::::$i:i:l:::i:i:::i:i:i:::i:iiI{:::::::¥:::rt;;::;:::;:i:f;:W
I

•'

-.•.',•,·,·.·~,· • • •

~:#:i:i:::::::i:\:!:#:4

·-:;::::::::::::::::::::::::::::'

ioCAck}:::,._·---.....!:~:;;;;:::::~::;:;;;;::::;;;;·;;;;··4··4··...,_--~~~~~~Jl':.~;;l\.l.l~le1:...._ _..;.

•••• \i+it....·::::....----··..;.·.::·~-:?. .: :.,.: : ._.: :..=:::..::::..

= ; ; , ; , ; . . - . . . . . . ; - - ; . ; . ; . ; .. . . . ._

sysEartyO~ \}:>·

. ·.· .. :-:·:-:-:-.

\:::::::::::;:;:\ f;:::::;:;:;:::::::::::::::::;:;:;:::;::::::::::::

sysTagOEEn ···=·.,=·=·.,=-=-.,=-·,;,;.,;.;·,;,;.,;.;,;,;,;,.,..,....---....;.;,·. ...,.,·.,··,;,;.,;.;,;,;,;,.-----""l..
·:=:..
::::..
: : ;,:.: : :;,:.: : :.:.: : :.:.: : : .:.: : :.:.: : ...
::::...
::::;.:.:.:::h
bcTagCEOE_I

·.: ::::::~:;::::::::::::::::::::::::t~:t:i:::;:;:;:;:;:;:;:;:;::::::t/;::,f<:;:;:;:::i:::;:;:;:;:;:;:;:;:;:;:;:;:;:;:~;:;:;:;:;:;:;:i:::i:::;:;:;:;:;:;:;:;:;:;:;:;:::;:

sysTagVDP

-!---(jf;:;:;:;:;;;:;:;;~:;:::;:;;:;:;:;:;:;:;:::;:;:;:::;:;:;:;:;:;:;:;:~;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:~;:;:;:;:;:;:;:;:;:;:;:::;:;:;:;:;:;:;:;:;:;:;:;:~:

sysDataO~t(: =;.; =~=....
=:::=....
==-=....
·.· ....,_ _ _·._·.··...
··;=.,-=··;;;;.·;;;..·...=
..
-=·=,..-=·=,.-=-=....
·. ·---i-------cf;:o:'.i:'.;:;;:'.;'.i:i:::::"°':'.::"°':'.::.:;;;:::::;:;:::::;:;::::::;:;i:::;,:.:::::;,:.:::;:i:.;i.'.:i;i

bcDat8:rgB~ff :: .;:;.;:;,= :x::,:;;=;=:;;:;:;:;:;:;:;:;:;:;~:;:;:;;;;:;;;;;:,:;;;;;;;;;;;;=::;:;:;:;:;:;::=:~:;:;:;:;:;:;:;:;::=======:=::;:;:;:;:;:;:;:;::=:~::=:=:=:=:=::;:;:;:;:;:;:;:;:;:;:;:;:;::=:===:::'.:
c~~~~$q

.·.

svslijM~en ~:: /tt=..
:-:-::=:-.

-<'.t: : :;:--

::/::. sys~~~ft;:::'..

-:=::::::.:

•

=::::tit
/Jitf
.·.·.· .·.·.·.·.·.·

•

&::::::::::::::::::::::::::::::::::::

"2,ll!i!IC~l!~'m.Wm<r'"'"'4*'.~*"'.
.::{f::}}j{\~DataWE_I

: \::::::::::::::::::i:i:::i:::::i:::i:::;:,:::i:::i:i:!:::i:::::::::::i:::i*!:i:::i:::i:i:f::::i:i:::::::i:fa:::i:i:i:::;:::::::::::::;:ID:::::::::i:::i:::i:i:::::\:i:\:i:::i:::::::i:::f

eplData
: Read Data RET :

Wait RDR
RDOonEPI

: Read Data RET

Note:
cpUC::Req and cpuCWMask are not important during this transaction.

Next Trans
RD1 on EPI

LJ-03143· TIO

Digital Confidential 5-45

~2 .2.a NoOOKhUb~

uoosa~on to no~~~~c~:J:]lljllliF

A nMA reoo
similar to the cacheable miss shown in Figure 5-15. D.JW.ItP.d#.t~.~naFq\ijp'.qg~f:"
issues, the probe cycle still exists, but the probe resultf.:j~f~4gj:9ftdt:::·. · · : : : : ;: : : : : · .

transactions.4!1Lnot ~fllla4o : :::~:. ood

522.2.4 110 Space DMA
should be responded to as an error usingml=Q.CA.~k:<l:o>.Y'~'-~~I).:~k~.hown in the
left half of Figure 5-16.
··· :::<:::>:::>:::::::..
..:::::::::::::::::::::::::::<::>·
··:·:.::<1:::::::::::::::::::::):::t::::..

·-'.:::\(/:

·.·.·...·.·.·.·.·.·.·'.·.::::::::{:·.

0. The transaction begins with the DM¥.¥:[~j}.1pg th;:::btt~:·:i~::=:indicated by the
assertion of ioGrant.
<;:i:;:i:;::::::.· ·-::::t:::t[[:·[:![.·. .:!:::ll:t:::::.. ··::::::
1. The 21071-DA chip requests aJ)l~ti}read With/ii.Qbid<2:0>, places the
address on sysAdr<33:5>, anq::::®.int~::::t~L~ line t<Fbe loaded in the DMA
read and 110 write buffer witl£l6tJhe8.eb~l~:O>.

2. The 21071-CA chjp deco44,[:!IAdr<3:;:;g~::!lla::·finds it is in 110 space. The
21071-CA chip tdtn$ on it~::::Qi.Slta.. drivers:%r this one cycle to prevent a
floating bus. .::\:::::j}Y ··Y>.. . ··:::?\J:I:t:ii:::::::=::::::,..
3. The cycle i~/i:~Jmowl~:dl4J:::~~:J~n e;i16f::!iWith ioCAck<l:O>.
:::::::::::::::;:-.
..<·:·:-:-:-:-:-:-:-::; ...

·-:-:::{/({ ..
·.·.:.:;:::::::::::::::::::::.:;:::-:·.

5-46 Digital Confidential

. ···:::::\~:)\:::;:;:;::·:: ....:.::.:·:·
. ..... .

Figure 5-16 Timing of OMA Read, 1/0 Space (error)
CYO

CY1

CY2

CY3

dk1
dk2
ioRequest
cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuAdr
cpuOata
drvSysOata
.·:·:-:.:·:·:-:·:-:·····:::;:::::;:;:

. :-:-: ..... :::::::::;::::::::::::::'.:::::.'.

sys DOE
cpuOOE_I
cpuOWSel

····=:::::::::::::::·

cpuCAck

··:·:··

cpuORAck
ioUneSel

i:l:i:i:i:i:i:i#i:i:i:i:i:i:i:i:i;;~;Ii

ioOataRdy

):!:::::\::::::::;t;;:;:;:::t\

ioCAck
sys Early OE En
sysTagOEEn

3=!:i:i:M#i:i:i:l:l:i:\:i:;:i:i:i:i{i:i:i:

···:-·.;-:.:::::;:::::::::::;.,

;.;.;:;:;:;.;:;.;.;:;.;.;.;:;.;.;.;:;.;:;:;.;:;.:·:~·::;.

:;.;:;.;.;:;.;.

:·:·:=:·:·:·:=:·:=:

error

·:·:::·:·:·:·:=

idle

.·. ::~:;:;:::;:>;:>>::'.:-:.
~~%'~:/~\:.~:·....,.,..~__.·~:-:::=·:-·~.-·~··...._~.........~~~~'--~~~-';;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;;/;!JG[filil]i(:::.
:'(::::::::::;:::::::::::::::::::::::::::;:::::~::::::::::::::;:::::::::::::::::::::;:::::;:;::::~:

~;:;:;:;:;:;:;:;:;:;:;:;:;:::;:;:;:;::::=;:;:;:;:~;

-Error Wait
and ARB

Error Return

Next Trans

W-03148-TIO

Digital Confidential 5-47

5.2.2.3

5.2.2.4

5.2.2.5

5.2.2.6

1. The 21QlW~D1-\?~litWfeque~f§+a DMA write with ioCmd<2:0>, places the
addre$$.~\\i.i.f sy~ijf=<aa;$~, and points to the DMA write buffer cache line

with wni.¢.l=:9@ti.l~l:hsing:!i9LineSek 1:0>.

2.
· .·=·=· · · · ·

TJii:::g:iJ'1f.~ql.i:;.hi1t~jj6des sysAdr<33:5> and finds it in cacheable memory

==~Pi~~ AlsdNtb~:l\i@C.fi~ tag indicates a cache hit. The 21071-CA chip

. /idJ.i.ti:b.ially transfers the first octaword of DMA write data to the memory
··-==::::~Wfl:\'i!i:pµjfer~ To prepare to invalidate the cache sysTagOEEn is deasserted.

j:\\lii!l~t:~:::,.Th:\\~l§~l[:it~gs are driven by the 21071-CA chip as invalid. The second

tt.:iiilj\jlil·l·>:.-i:.:ll\.

< jj!li

;;:~:::!~~:::b: asserting sysTagWE for one cycle. The cache data

.·=: : : : :=:::::::=:=:= is not written. bc_LongWR does not affect this transaction.
·-:-:-:-:-··:··:::::::::::::::::::::::::...:::::: ·.·.·

·-====t:>=ttt::::tUI5. The 21071-CA chip tristates the tags. The transaction is acknowledged

<\ij\!I ,~;::~::!~:e~s(~a: ~~~~:~:=~td:o~! :;a~~=~ in cycle 4

5-48 Digital Confidential

:·._.:~:·_,~_ .:_.:~:·_

,f:i: ·:l?':t: : : r_: :,:_·.!:1_: ·.:,=._: ·.: ·~.: :_,::=:_;:.:·.:.·_:,'.:~.:,:.:~.-:_,=_:= >
. it~f~r

,;·.::··':···[.::_111111111.1;;,\fa.....

::.:::_
...
..:::=_.:'__:, ...
::··_.'i
...
:·.:·.:_
..
::_:i::_.:!_:.·_
__ ..:•_···':.•··...··:·:..:••.:::_:__

\ff:r :tt\: .A]]j:
Figure 5-17 Timing of OMA Write, Cecheable, Hit, Followed by QMA Reild \~ill~'ll[l\.lJf;f
CYO

CY1

CY2

CY3

CY4

dk1

·•·

~111tl'''lltf!!!~b .

clk2
ioRequest
cpuHoldReq
cpuHoldAck

.·-:::::::;:;.;:~;::·

·-··:::::;::}})}}~;~:~:::~·..

.·: :·:.: : : :i: :~:i:i: ;~ ;:t: : : : :;:;:;:;:;:;:;:;:;:;:; ; '.~'.; ;~ ; :;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;: :

ioGrant

cpuAdr

:~::::::::::::::::::::::::::~;:::::::::;:;:;:::::~;:;:~ OMA Write
i¢:1:l:l:@:l:)#:l:l:l}l:i:W:i:::!$i:l:i:@D QMA Pac address

cpuOata

:f::::;:;::=:1:::::~:;:;:*:;:;:;:;:;:::;:;:;:~.;::=:=::;:;:~:::i::;:;:::::::::::;~:;~::::::1:=::;:;:;:;::::~:;:;:;:;:;~::'.'.'.'.'.'.;:::=:=~:::[:;:::::G;;;;~;:;;;;;;;;;;~;;;;~~~~~~:~~j;;;:;:~:;;:;t[;[.::-

ioCmd

.·:·:·:-:::::::;:.:-:::::::..·.

.,:::::::::::::;:;::::::;::/:::t::t:::,,,,:,...

.{.,:,.:.:-:·:·:·:·:· ·.·.·-·.·.·.·.

*:::::::::::::::::::::::::::;:;:;::::::::::::::::::

····::::::::;,,,:,::::::.·

t=:\:i:J:i:i:i:\{i:\:ifl:i:i:::i:i:r.

•:i::;:~::::;:;:;:;:;:;:;:;:;:;:;:;:;~:

drvSysData
sys DOE
cpuDOE_I
cpuDWSel
cpuCAck
c:puDRAck
iolineSel
ioDataRdy
ioCAck
sysEartyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVDP
'tfUX:\:::i:::;:;:;:;:;:\:;:;:;:\:::;:;:;:;:;:::\:j::

sysOataOEEn

~:i:i;::\;i:=:i:i:i:::;:::i:::l:i:\:::i:i:i::i::

bcDataCEOE_I
l::;:;:;:;:;:;:::::;:;:;:::;:;:;:::f

cpuDinvReq

.: : : : :· ·

)::::;:;:;:;:;:;:;:::;:;:\

. . A:Oti1;:::;:;4
\. ,·:=:,. =:=:...
=:=: . .,: :...
:::=\..._______.._______._ _,4,.,..:::::...: :=. .,: ;:;. ,:;: ,. =: : . .,: :.......
::\:t
<::'.:::\/. : :=:::::ttttttrmmtr>:· ti:Mw=ww
==='--------------. ..a

sysDataALEn
sysOataAHEn

-.:::~tthIIIt

:~::://;;:)t;Jtm;i

bcoataA<4>

.· : : : : : : : : :;:; .

'1\:r;·:::,.:H...
m.w·.::::..

·i:·:·=-·.

j:::::::::~

\:::::::S

sysoa.~.~~En
fiffiijkJ\:::...
;
..... :--...:.:::-·
•
···::::::::::::::::::::::::::::::::::-!·•
. ·::-:-

..::::::::::

:__i_._;_J_._i_J
..

bw._j_:ife.:_;_'._~_:_:·:J.!.·:.!.:.;_:.·~.:_=.:_·
..

..·

...

.;,::::)!::::rn:::~TagCtlWEJ:@@t

}/@{·.

··.

: \@jlj[:l l~l j[:l~: : : t?: :.·
·;::::::::::::::::::::::··

·??

sysC~!!!\f;:/(

: :;:::::::-=--:.:::::'.:?:·:::_:;::::::\:, /\: :1:1111:1i:

·::':\:(:m:i·:l[·l)lll!.[l ...

r~MA Has Cache : OMA Address

:1::t,~~~Req

:\):l:i;::W#\
:h:i:it:::;:;::::y
~load*:::::::::::::::::::::Tag Probe

i!:~ l~~around

Tag Invalidate , OMA Terminate :

Next TRANS

•

and cpuCWMask are not important during this transaction.
W-03153-TIO

Digital Confidential 5-49

__:::;_-.::.:_r

..:

5.2.2.6.2 C&cheable Miss
1

Figure 5--18

:~ch:: :r::ion b~ns the
wifu

assertion of ioGrant.

shows a

DMA

:,=·.:.'.,·.~,~ ~ :.l.·:: ~:
;·;.',:'...· ::·:.:,......
'. ...:.:.·

:\.1\i:[.

i·:::: :::':::·;.

·::::::~:::}::::{ =:::~{::

!i)1t; .i!i In \'.\jl,lfI~! r

DMA writ!!

tninJ:~,Jlll'

hamg ~~tlf''.~~~!I~;~:'.'

,/ll:·\!.:[:),: :':·.·. ··::\t{j\\:\:ii·j::[j\j:j\.\j:itl:\,:...

·-=··

1. The 21071-DA chip requests a DMA Writ~?M.t.b. ioCriidij,~~Qik:Places the

::e~~: ;::::~;~!>u:U:!~:.to tHi!,,ii;'.:~~f

cache line

::c:.l~!~~~:h!~~:c:;si~~8!'1J19f&1~~~~~,~~~~~~~ec::::mory
internally transfers the first octaw9ia of DM#.JHfmt.~. data to the memory
write buffer.
.: : ?: ·.: · : \· ·i:·.: ·:.:.'.'.·~:,:...:-:.·.·.·
···:' '\{[i\\:\jj}t
If the cache is disabled (bc_~ft)f'OXl~i\:::t~g. probe results are ignored

~;~:~q~ss~:,~d th,1jJll}:;:teriillf/~'11e

is invalidated

wifu

If the memory Wftt~f qµffer ~a$mm11~4b.e probe is completed and the write

data is not transf~M;t.Qi~]:J;f:::the pf6ti)ifa#.iised, the arbitration may release

~~~~~~~~I~: trllW'llI~'.I ~ue

when the memory write buffer

3. The transacti~a:\::iil.iiinqwle·d~~a.:l\with ioCAck<l:O>. (The acknowledgment
could not be done ·fri/#;i#i~:::~J:ls the tag results were not available yet.)

5-50 Digital Confidential

Figure 5-18
CYO

CY1

CY2

CY3

clk1
clk2

loRequest
cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuAdr
c:p.iOata
drvSysOata
sysOOE
cpuOOE_I
cpuOWSel
cpuCAck
cpuDRAck
1ounes.1

~:::::::::::::::::::::::::::::::::::::;;;;;;;;;:;~:::~~=:=:o=:__ M:"T_.AT":':.;,~r1~te-=a="-"·fa;;;·:fi.:~.:::~:o;,;9~=:~;,;:;~~;;:::~::;:""';,,,-:·:·-----.~:~:::::.....: : ~: : : -.o: : :. .,: : .....: : :~: : : -.o: : :'": : .....:::::o:-..:;:

ioOataRdy

):::::::::::::::::::::::::::::~::\
•

' ···::::::::::}:'[:::::::::::{::::::::,.:..

.·:·>.<:::::;::=;:::...

··:·::;;::::=:[/:[:~/
·-·-:.·.

·.:-:-:·:·:-:;:;:::::::::::::~:::::-:·.

ioCAck
sysEarlyOEEn
sysTagOEEn
bcTagCEOE_I

\flP(:i:::i:i:::;:::(:i:i:::;:::::::::::::;:::;:~:

-:::::::::::::::;:::::::::::::;:;:::::;:::::~;

'!Ii.:.!_.~_:=_--~.

:::==::=:=::::~;:::::::::::::::::::::::::::::::::::::::::::::::::::
:·-:::::::::::::::·:

;~:;:;:;:;;;::::;::::::;:::~:::::::::::::::::::::~

: OMA Has Cache : OMA Address

..
:

Tag Probe
and ARB

: OMA Terminate :

Next TRANS

Note:
cpuCReq, cpuCWMask and cpuAdr are not important during !his transaction.
W·03155·TIO

Digital Confidential 5-51

5.2.2.6.3

No~~b~ wri~ t o s~tion in nqq~~~~::l,!IJ:t'JW
A DMA

similar to a DMA write miss as shown in Figure 5-18..AMl!~ml the·===tijig\[pf!lfo
results do not matter, the timing of internal transfers4~1@!f=tKij[:iAf.Jm9)Vledgfiient
are the same. The acknowledgment cannot be doneAr#[cycle 2 ··oof.iµJ~~kpf the
time required to determine if the transaction is tc>.A~Iti.J~d memor)?10.i.ition or
not.
.· : : :\{~\[\~i : :i1·1:1 :_:1~_:l:·:r.ir.: : _i:~.:it:=:
· : :-·
.·::{}:·.

·····.·:··=·:·:·:·:·.

·.·.·.·.·.·.·.·····

······:·:·:·:.:·:·:<·:;:;:;:;::..·

1
~h~!i:·!e
~?s::i:d t~~::::rctii::g~~!~llr~~d;!'?h~~ein
and
Figure 5-16.
. : : :=: =:=: : : :=: :=·=·=·=-.
· ·-==: : : : : : :='===: : ;: : ='===
o.

~!!i:s~:!ts with ~~1&:;~~,-~:!:~ inIDcated the
by

: ~~:f~:~!ii!~l;~::~~~i~~:~~::~e~:e

cycle is ac~n9=w!~dged··=:isU~:j~~9r wit1PfoCAck< 1:0>.
.. . . . . :..
.... :::. ·::;:;::::::;::::::::::.:-.
5.2.2.7 OMA Write Maskidf)){ ::\:;._
~

::::::::::::::~::·

.:-:-:-·.:-·

5.2.2.7.1 di.Qh.e-W:::Hit{t:ligure 5-19 shows a DMA write masked transaction

in cac9~_abi~\:~~Pf:!~\lhat .P.J!fi:[
::;::::::-::::/::.:

··:·~\\·:····

.·..

.·.·=·:·:·:·:·:·:-:·:·'.·

.: : : =: . . . . .
·:<tI: : : :"···:::;::::·:·:·:
i: ti: m=.:· .~·:_:.;,:=·:. :=·:_.:~.·l:::::rr=
. ·:{\\(
O.)\lmft~li:transaction begins with the DMA having the bus as indicated by the
: : :=: :':':'='=:. .·.·.·.·.·.· ·.· ···-==isli!¥g~::::~f ioGrant.
:=:J:I:::::·[ji:::i:::tr::·l·iiil:j·\~fat:Th;=::~jjiji1f:Qt\ chip requests a DMA write masked with ioCmd<2:0>, places
;:;::::·:::.:· ·
. =\=:::t\Ythe addreii.N>n sysAdr<33:5>, and points to the DMA write buffer cache
.: : :.:; ; ·;,;';
·-=:-··:··.::···:i::iine with write data using ioLineSel<::l:O:>.
·:::::::<:?\{ ·:-:-:·:-:-:. :=::){[.:~/·The 21071-CAchip decodes sysAdr<33:5> and finds it in cacheable memory
··:.:·:·:.:.:.::+:>>:·······
space. The 21071-CA chip waits for the cache probe, which indicates a
··=<=::::"'<iii/]:: \::. cache hit. The first octaword of data is already on the data bus. The data
···:::::::~~fb:;~~~~;;~)l~~:: merge.d (based on the byte enables) with the DMA write buffer and
·:::::t{:Joaded into the memory write buffer. To prepare for reading the second
··octaword, bcDataA<4> is asserted.
...

5-52 Digital Confidential

;;;·i~•:;11,11i\l11;[f

3. The cache tags are

driven the

chip

inyajjd~,1~llfmzi4ar

by
21071-CA
as
chip reads the second octaword of cache data, merg~~iifi~fM!ib4.. PlaeiiH~Mi.#~·
the memory write buffer.
. ::1\.:j:!j~jji:ff:t\!li[\jjl:j:\:,\jj:\:\!l:]}\:::,. .:· : : : : : : ;: : : "·

: ::;!!~!i?~::~~~~s('!:
:7;~~::::::~::::gi:::~::llt:~~·ac:::!\!~d
:~~~:~~~\:~4,,~,.;!Jfli~~~
cycle 4

···:::::~\~:;}:-:~i~i{(\::::·:·.
·::::::/~::.~::::{:~:~{:
-.·.·.;.·-:-:-:-:-:-:.·- ::::·

Digital Confidential 5-53

Figure 5-19 Timing of OMA Write Masked, Cacheable, Hit
CYO

CY2

CY1

CY3

CY4

ctk1

dk2
ioRequest
cpuHoldReq
cpuHoldAck

ioGrant
loCmd

·.·.·.·.·.·.:,.·.·.·.·::;::::::::::::-.·.

:~:::::::::::::::::::::::::::::::::::::::::::::::~::::l(ii!(..-:.D~M~A""'W~ri~te-----...;..----;.;.;,;,;.;,;.;,;,;,;,;,..---···-····,..:;::...
:::·.,.·.·.·..,.·.·.;.;;·,;,;·.,.:::::..,:::.....-~~:....
::::....
::::.""'·::::...
::::....
:::::....
: : · :.:.·: :...
::::...
·::::""::::.:;:.::!:

cpuAdr

t::::\:\:\:\:\:\:\:\:i:\:::::::M:i:\:i:i:i:\:i~:i:\;\:€il!X.....:b~M::;:A..i::fa:.:c:..;;::;ad::.re:;,:s:::.s_ _ _ _ __..; .;,: : ; ;,:..: ::.~...

cpuData

...-----~;,;...--1"'x"'i:::i,..:i::;.;.::i:i:;.;.;i:::"'i:i:i,..:i:i:.;,::::i:..i:i: ,.i: : ,;w;.: :t:

:~::::::::::::::f:::·:::·=:=:=:=·=·::=·=:=:=·===H=i:i=i=:=:=·=·=·=·===========·=·=·=:=:=:;;::::·:::::·:::::::~iCi)ijjt~~:Z-·Z:::::z:tt<Z\tlzl:/~@::l)~~::-::::.---~~::.:::::::::·:·:::·:·:::::::::::::::·1:

,';::8"·1;;;.:::::;,;o::::...
:::-:;;.;,·:·:;;;,·.:'"°::::,;.,:

drvSysData
sysOOE
cpuOOE_I
cpuOW5el

···:::::{:'.:::::::::::?'

cpuCAck

·:-:-:·::::;.

cpuDRAck

ioLlne5el
ioDataRdy
ioCAck
sysEartyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVDP
sysDataOEEn
bcDataCEOE_I
cpuDlnvReq

\Jb]\ .·:\{:/

sysoataALEn
sysOataAHEn

bc0ataA<4>
sysDataWEEn

:"j;;;~;;;;;;;:::::::;:J

-:mttfJJ\::-:-.-.-.-.-:·:~}:;:::/::·:-:.=i========:==/}\t• -:)~'~ttttttte>:=-·
)\}\-:.

\..,5::..
:::::....
::!:.,.:::::...
::::...
\ _ . . __ _ _ __.__ _ _ _ _o!--""""A:""'::::.:::::...
::::...
:::::..,::::.:::::,..::::'!":j::

J:i:i:t%:i:(:J
f:::=:===r

'l:lj:;:\"':i:i.w:t,:_.'.:\:,;i;\;i:\,;a.·- - - - - - - - - - - - -.......

\=:=:=:=:)

-: ~:~" ': : :" ·;:;.li!'l~:;:·~;:;: ,.,. : :'." '?)~l=:.'"'.

-----------------------------------

Next Trans

.•. := ::

::~~~~~~~~~~~~~~~~)(~~~\}:;:::::;.·
····:::::::·::::::::::::::::::::::::::::

5-54 'Digital Confidential

W·03154·TIO

Any DMA transa9ti9tkt9. 110 ·spi!iia~k~ error, and is
described in Section 5.2.2.2.4.
JlfilfflIIh\.;.. ..,,,'''l'{:r

5.2.2.7.4 1/0 Space
5.2.2.8

~~~~::.a;:r::~i~u:=a\~!f!!~~i~! :!~:;i:ccess
time required by ISA and EIS.Adi.W.Vices. ··::~i}§:.-20 shows a DMA flush

transaction.

<[ti!> & .•. t\i!l!;lllt'fW1b. %jif

0. The transaction begi#.idfith the ·n¥.:tVb.aving the bus as indicated by the
assertion o,f_·:.:j_iMlrant.
··:·:::?{\\l_::.::_::_]\:ll::::::,...
··:::::;or:;:::-·
·:···=<·:::-····

1. The 2107l:oA;:::liikr~que;t~::\:l'.::fiM4 flush with ioCmd<2:0>, and places an

arbitrary addre's=M:~9:'\:i¥;,f}.dr<:faf~>.C
2. The 21071-C.A. ~hip·.,,:~hijll:-::tQ,,,,~ee if its write buffer is empty. In this
diagram J#:~mn9#:::~mptie'd/fqt\¥wo cycles, so the 21071-CA chip waits.

3. If the v.fl~J:::b:g,f:~\'~~)~mp~;, ioCAck<l:O> would be in this cycle. It is not,
so the '$.~Q71~QAlfohipfa~i.*1tinues to wait.

1ll~J6'\lll:it~~i·Lues

4.
ro wait.
5. .At.hiJ21071~0Ai:#b.ii#d'etermines that its write buffer is empty and the
-A!Ilt~~~ction is acknowledged with ioCAck<l:O>.

····<tf !l~'~llli'hb.

··=~::::{ff}}}(::

Digital Confidential 5-55

Figure 5-20 Timing of DMA Flush

CYO

CY1

CY3

CY2

CY4

ck1
clk2
ioRequest
cpuHoldReq
cpuHoldAck

).]fililli1

ioGrant
ioCmd
cpuOata
drvSysOata
sysDOE
-~::::::::::::::::::::::::::::::::::::::::::::;:·:·:.:·:·.

cpuOOE_I
cpuOWSel
cpuCAck
cpuDRAck
ioDataRdy

-:\:i...,::::..,\_.._____._"' _: : :...~· ,. ,.,: ;.; f;.; l;.; t;.; t.,.,: : ,. : ..:;.;,. .,.......__.._..:::_:=::...t ...(;.;;f.,.,{,..+;.;,r;.;,.::;;;t,...-----~------------'-

*...,:::i...,:!:[,...::::,..::::...
i:::..,::):\...

::::::::::::::::=:::::=:=:=:::·:·.

·:::::::::::::;:·

ioCAck

~M=i:i=t=l:i:l:l:i:l:i:i:(:i:l:=:l:i:i:i:i:i=Wie:ix.,..=···;.;;la..,ie..__.__. ,_. ,. .,.,....:',...' ' ,...' =:.,..=' '....'''=.,.'''.,.
.. _ _ _ _._
.. ,,...,.,....
,.,._
.. _ _ _ _ _ _~=i=i:i:i:i=i:i=i=i=i=t=i:i=MH\:i:i=i:N=

sysEarlyOEEn

~..__~'~\,~,~~~'''~"':~. . .~,.. --~·-·.:,,_~\_t~:+~T~<~>~,..............~-+-~~~--.;.--------;....--------;.
··~:::::·:·.

·>.·.·~·

.... .;-:-:-:-:- ..

sysTagOEEn
bcTagCEOE_I
sysTagVOP
sysDataOEEn
bcOataCEOE_I
cpuDinvReq

+=============:==============::=:===:==========:H====================:===========:=========h===;=;;/:;;;:;;;;;;:;:;;:;;;:;;;;;;;;;;:;::i:========:==========::::;::=:=::;::::=========:;=========:=======::;:;::=:=:::=:=:::==============;·=======::;::===::======:==============:H=:=:::=:=:=:=:::::=====:::=:=:=:::::::::::::=::::i=:

,;;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:~:::;·:·:·:·:-:·:·.·.'

·:·::::::::::.':.:=.··:::~::::::::·

i::::::::::::::::::::::::=i=i=:=:=:=i====~=:=:ff(J;:;j;;;};;;x>:j)jy:·

tit:mrr

Q:::;:;:;:;:;:;:;:;:;:::;:;:;:;:;:;:;:;:;:::::::::
A=#'4=i=i=i:i=i=====i===i=i=i=::i=:=:=:=:=:::::::=====i=i

. ::~:;=;=~;~;~r~ _:/}It.

sysOataALEn
sysOataAHEn
bcOataAc4>
sysOataWEEn

sysCmd ·:::::::~:::::::::::=:::::::::::·:;:::::::=:·:;:·::::::::::~ ·:::::::::::::=:::::

reset

:·:::::::::·:::::::::: reset

.::::;:;~:::::::;:;::·

·.··
··.· .·.:·:·::::;

{}{))MA Has Cache

OMA Request

Flush Waiting

OMA Terminate

Next TRANS

:·'.· :-:-:-:-·

·:·:.:.;),,:,:, .......,.::::;:;:::::::'Note:
cpuCReq, cpuCWMask, and cpuAdr are not important during this transaction.

··){~{ :.;.:-:-:·'.·: ·:·:-:-.·.

··-:-:.:-;.;.:-:-::=:::::::::;::::::·:···

5-56 Digital Confidential

W-03132-TIO

5.2.3 Arbitration
2

s. .a1

':.;~
~
e:::::,c~•on~gure
shows the actiol.\l!!!ll\1£iui!!cl<-toback
transactions. This figure shows a
by a
1
CPU

5-21

CPU ~tlii$ble read>tO.i.l~Hved
CPU write, although this description is appUcable::''i£\\\li!4t~saction3/
O. A

cacheable read block transaction i:):ll:.~:==~11;i in cycle 6 of

Section 5.2.1.2.1.

···==\){ftt\=:··

1. In the cycle of cpuCAck<2:0> beingAibf4l:l\l:@J~a~~~Ig~·6ls are set inactive,
with sysEarlyOEEn, sysTagOEEn~Hb.dP'$Yi.B\i:fAQEEri'ill deasserted.
2.

::np~~~::::::on is •11\~~:!!JI? next CPU transaction,

sysEarlyOEEn is ·asserted>:t::,111-.·!.i.j!F' '"·.··:·::=:::::n;:!!\i!i·::111!_!j:l!::::!ilJ:t:=:·
3. To prepare for wrjte data#mUQWSel is asijifted. A CPU write transaction
is next, as desctjfi~d:-in cycUkJ,~fri,(j!$.~~tion 5~2~·1.3.1.
"'===:=:=:=:===:=: ;: ·
····==:==:::1::rn::=,:-.:-·:1=~:::::::tr·

Digital Confidential 5-57

Figure 5-21 Switch From CPU Read to CPU Write

eve

CV7

CV8/CVO

clk1
clk2
lo Request
cpuHoldReq

·.········:·:

cpuHoldAck
ioGrant

··:·:::::·:·:·:·:::::::::::·'.·:·::·::.

foCmd
cpuCReq

write

c urea

cpuCWMask
cpuAdr
cpuOata
drvSysData
sysDOE
cpuDOE_I

.:··

cpuDWSel

..::::::::::::::::::~;!Hi:\:\:ViHl:f:f:i:i:i:~
.....
ll~~ih~li;~l;l~l;,...i;i;i;_\\
_ _ _ __
····.···i··········· ...·.
'
···-:-:····-···

cpucAck.,...
.·.· ... ·.-..

---+-----...;.

cpuDR~~:::::::t::;=:::=tt:::::::::}:·~i.;.;:;:;:.;.o;:;:~;:;:;'lol:;:;:~;:;:,..,::;::_.:::::,;.a}.,._.;---·-:·:·:-·:
ioDataRdf. ··.·.·.·.···

}~:~:~:~::{:'./:::·.

~" ·: :;" :; ;:i:i:i\:o ; ; ;-:-:-:-:-:::::::::::::;:;:!:::::·:·::.:.;\~\~; ; ;:.:.i\~}. ,:,. :·.·.;. ,·- - - - - - - - - -

ioCAck
sysEarfyOEEn
sysTagOEE11.

bcTagC.~Q~j\

~..-..,.,..__·.·_·-=::_,:),~~~i:,.,.,\~._,{:,;,o~<.;..,{;,o;;\,;,o.·. , . , . _ - - - - - - - - - - - -

:::::::::.:.:.·-·.· ·.

·:-:·:·:-:-··:····

sv,~t~W~''''' ':ltl#l{ifli:::::i:!:fKM::::::::::::::ii\::)

sy~ijij,~En ..~::::,.,.,{;,;.;)::_(_~~-----....------.------....
...
:::;:;:;:::::::·'.;

bcTagCtlWE_I

sysCmd

no
Read Block

Read Block

Idle

Write Block
W-03145-TIO

5-58 Digital Confidential

52.aU

OMA

ro OMA The amons between two

1
O ck-ro,o ~!lf~!~ :!l !''jl'

transactions are shown in Figure 5-22 and Figure 5-2.3~tjl~~ht.5-22::::~htjw~\:::/
a DMA read hit foll~wed by a DMA write, and Figur~j]if.2a':~:~b.@l~u~. r>:M:X::::"·
write hit followed by a second DMA write. This des~r.fP.Jfon is 'ifpfiJtii.b:l~. to any
back-to-back DMA transaction.
. : : :•: :·:·.
<:j[\\:\j\\:l:!::l!.!!!:,[::tt::.;..
""\:::::\l\l[l[l'.·
0. A DMA read miss transaction is in p8es:~' as ·dei,&q:Jn cycle 5 of
Section 5.2.2.2.2. If not already in theWi>r.t:®tJ~.tate,'·::sY:ili.J~QEEn and
bcDataA<4> are deasserted.
''::::ttWtttt:::::..
··-:··:·:::;:;:;;i:> .
1. The DMA read miss transaction is

finj_~p~d ·:~t#!:[~IAtk:o::=l:~> being sent.

Digital Confidential 5-59

Figure s-22 ·switch From OMA Read Hit to OMA Write
CYO

CY1

CY2

RDCY2

, RD CY3JWR CYO ,

WRCY1

ck1
clk2
ioRequest
cpuHoldReq
cpuHoldAck
ioGrant
ioCmd
cpuAdr
cpuData

··::\~f}j{~~J?.

drvSysData

····::::

sysDOE
cpuDOE_l
cpuOWSel

,J:::::~~fm\:\.+::.-._ ...•-d-e~: : :.; ;,: : ~.'.'.'~'.';~ ; ;,;~,;='~:=: :~: :'.~: :'.:~: : ; #':·.......:::.:.:..~i;w;w;:w;.:i;;"'-.-'d•le:;....~
sysear1yt.1~~~{{~::::~:;:::!'.<",.~---·-:·...
=·=-;...
·.·~··!'.<":-:·..,.:·:.:...,.:-:~.:::·!'.<":·::_
... _ _ _ _ _ _ __

sysTagOEEi'i:::'.:\{f
bcTagCEOE_l

,~r:#.~!P:~<::I:t::=:=:=:====;:;;;;;;;;;;;;;;;;::;:=:=:;:::=:f:=:::::::::::::::::::=:::::::::=:=:::::::::::m::::::::=:::::::::::::::::::::::::::==:•:

::J~W:~~~o~~~=: ?f?

......

=:i\ll!l.lf:~:l.I::=_:r-,,,., ,;.,.,: ·;.:;,.~;.:_-------------.

...

'\!\j\ll~fi;.~~

:\:·::·[j_:::I:>

·'+?:)tft

0 "" .....

../£:;:;:;:;;:::::::;:/

81bc"'i.;l:~a:; ;t:;ili]:"~: I]·.~'. ='.:'._=:.i.lf.;:[= \.; !.!~ J?.

<:11il fill\,!iw:~~

i,..;'::o:.::::::.:.;,::::.,.:::::;,:,:::::o:.:i:\~------

:= =. :.o=:= =~\

h====m====::::I

', ;o:===:.:.:====..
==•=....

kVi===?

Wihi

......_ _ _.,.

-------·

··:·:::::::::{\:\:M~~rflgwe
t>ci'.#.gCtlWE_I
sysCmd
: OMA Read
·Hit

: DMARead
· Hit

: DMAWrite

Note:
cpuCReq and cpuCWMask are not important during this transaction.
W-03151-TIO

5-60 Digital Confidential

Figure 5-23 OMA Write Hit To OMA White
CYO
OMACY3

CY1
OMA CY4

CY2
OMA CY5

clk1
clk2
ioRequest

cpuHoldReq
cpuHoldAck
ioGrant
ioCmd

oMAWrite

cpuAdr

oMA w~te address

cpuData
drvSysData
sysDOE
cpuDOE_I
cpuDWSel
cpuCAck
cpuDRAck

sysEarlyOEEn
sysTagOEEn
beTagCEOE_l

\,..·:::"":::::....
:::::...
::::....
::\...__ _ _ __..

sysTagyp~: :\::;a,..\.: :.·.·.- "': -: : :_. : '.;.'.::~..:'~.: :.:__f_.·______,H:::::::::::::::::::::::::::::::::::::::::::::;:;:~:
.·:·:<·:·:·>:·:·...•.. ·:::;:::::·:·:·:·:.·.·.·.··.··

sysDa~,~~~t

bcData~~4.1

·:-:-:·:?l/ · ./%h
.·:·:-:.:-:=:·:·:··

cpuoE~ffl~\::~t::~::~:i::::::··

::::::::::::::~:::.

. :~:i: : !: : ,lil!:;~: i: "'H"':f:i:~: : :"':i:i:"°i:i:~: : :" ?-.!...~·="':;"':;:~: ._i:....·":'i="°:i"': ..
:\~;;:i"'...=::.'"'·i"':::I\--;..------;.
:

:{li~t.At~wr~::::::::::::,::·.·.· :-:::::::=:ytt~

.... .. ..

. ·::::::~:. ·:· .... :-.=::::::·~(~{~>:··

. ,,JtiH.1.·=1:::::·=,::::..,.t..,.?....:o::...:;:;:....} ...?:...---......----------------..
···:·:::::::-:-:-:;:·:·:;:;:-:·:-:·

·:::\:\:{:~~it~~:~.~ -·_.--------------------·~~e~mi:[:::::::~::··

sysTagW.~~?:...
::.-_·_ _ _ _ _J....
~::....
::;::...;::...:::~..,,,::::/

\::;:;:;:;:;:~;:;:;::;\

·:;:;:··,

bcTagCtlWE_(: . . . . . - - - - - - :
\""~·::~Z:::::"";~:::;""':"'::::.:.:o:""'::\~-...;;i:.:t.:.:.::::;""':::::""'::::....
·::::·.,,,,.;:/
sysCmd
: Wait for ACK
'. Tag Turnaround : Tag lnval
: BUS Turnaround
Note:
cpuCReq and cpuCWMask are not important during this transaction.

OMA Write

W-03152-TIO

Digital Confidential 5-61

5.2.3.2 Transitions
5.2.3.2.1 CPU to DMA

. ::=:::::::::::::;::::.

When the arbiter decides tha:t/t1t.e/~Y$.~:us
be granted to DMA, several signals must change the*-r~:!IMitilt\~::iJ.i.t~~.
preparation for the DMA transaction. This is showrn:!i.Cf'igure . 54$\%1\t\:·

O. ~e~~~e= ~:f: 5~~h;!!:~~~-~~-~~'!''·.;;;;s~e

ioRequest<l:O> signals for a request or atoffii-O.tm1Htbi~ cycM}?(This diagram
represents the earliest possible samplj;pg;-:...two . cyel.~'-it\lj~f9re a transaction is
acknowledged on ioCAck<l:O> or cpji·jt~~.O>.) . ,,:,::<@mff' '.

1. The arbiter decides that the 2107l~QA::::~hlll·'W~J}\::pg,. gr:.ited the bus. While
0

:e~:::.:~~~g~:::s :11&:~~::!.e:~s any CPU
transaction to its space, aqdJvlits foF'eiU.ftbld.Ack to assert.

3. The 21071-CA aP.~~L~1071:illjjj'iP.~ wai~·':/Jf,i,f~uHoldAck to assert. In the
fastest case, cpuff9.1dt.\~lc asseHj,:JiJ.u~L~Ycle.

4. !:i::pen::;i{t ~~ ~-~!!¥,e::~~llJA.ck and tristates its buses in this
~5

describedjf.fa~y~Jij/+.::,.9f S~t.i.~i?5.2.2.6.3. The 21071-CA chip receives the
commaqgfa).iiff';l#f:9.~sse.~ it.···::;:·:;:·

······:·:·:-·.·
.·:-:-:-:-:·:·:-:-:·

{/tt).

_.;::;/:{.i;;::·
·.·:.·.·.·:..··,.·,.·.··,:·..·;·::··

·: :\ \tli: : :tl:mj:[il.·:·\j?'.

::::::{:·
.

:·.:~.:~.:~=.:.;.=

'.:=..'.:".:·.:.::.·.·

m:=t\f

iiilJ{'ll!l!!iJJft'lllf

5-62 Digital Confidential

Figure 5-24 Switch from CPU read to OMA write
CYO

CY1

CY2

CY3

clk1
clk2

i0Reque1t

t-=========i======:::=::~:i:=:==w

cpuHoldReq

· =======

.=:=::::::::~=======··.

...-----------......
---------·==_t..,t~.~::1.'i!i~;:!'!'::~::'!'!:~;:;~.~:;;~t~::~f::::.,..
.
,
ioGrant

·-:===tt}}Fit====::·

.. '.:=:\}/

cpuHoldAck

ioCmd
cpuCReq

1 1

ffiO
....:...n-.ot....w-.r..,.aee.....,e.-.d_......_ _ _ _

....__ _ _...,lds...,
: ....
ea
...

__.mi~f ;;7 6~,3Jt:::
~=::::... ·.•.•,•.•...... •,•,•,•,•,•,•,•.::::~:::::;:;:.: ... ·,

cpuCWMask

·r

readblOCk

cpuAdr

.l:::::~:=~::::::::::::::::::~.

cpuData
drvSysData
sys DOE
cpuDOE_I
cpuDWSel
cpuCAck
cpuDRAck
ioDataRdy
ioCAck

idle

·.··.·.·-:-:;:
·-·-:-:-:.:.::

..
·.··
·-:···:··-:-:-:-:·:::::::::::::::::!:·..

sysEarlyOEEn

·-.:-:-:-:-:-:-:.:+
·-:-:-:-:-:-:.:.:-:-:-:-:-:-:-·.:.:-.

sysTagOEEn

~:::::::::::::::::::::::::::::\

bcTagCEOE_I
sysTagVDP

l:::;:;:;:;::::=:=::;:;:;:;:;::m

sysDataOEEn

f::;:;:;:;:;:::/:;:;:/

bcDataCEOE_I

'.=====:~:/t=:::=e:::=:=:=:4M~l!H~iv··:

,.,...;:;=....
w""='=1=1...
q:;;..,1:\......., _ _ _ _ _ _ _ _ _ _ _ _ __.....

:;;,;,;,_ _ __.1...: ;" ':;:;:.,.;:~...
:::::...~::_:]!):/:==:\. :.:. ,: : :,.: ;:" ';: :...
::::\...· ---------------------

IA#'I

CPU Read

CPU Ignored

CPU Ignored
Wait for ACK

CPU Write
LJ-03146-TIO

Digital Confidential 5-63

1. One cycle before the cycle ioQ~i.~:i~P?:J1sserts>Uie 21071-CA chip
2.

::::::;:~::~S&:!l1B·sysTugOEEn.
cr
n
t
h
e
f
i
g
ur
e
,
sysTagOEEn wa${W.ready . .
for thtFinvalidate.) The address buffer
d~$$eft~d

direction is togg.lij( Tb.~. 2107tiQ.#.i]~h~P. detects the deassertion of ioGrant,
tristates itsJt?.dress. 'b:"!'f!~}:md.°Wi~~~j:jf.or cpuHoldAck to deassert.
3. CpuHoldAfi.:::ij~pp~ns tcFa~~i~~tt.:Jhis cycle, which is the earliest case.
4. The 21071-CA::'6K.i~:[,:~~~~.rts. =;~:~~~~lyOEEn, changes ioCAck< 1:0> to idle,
and may begin prd~e:~~jpg:::t.;tie
CPU transaction.
·.·.·.·.·.·.·.·.·.·.·.:;:;:·:-:-:-·-·.

5-64 Digital Confidential

Figure 5-25 Switch From OMA Write Hit to CPU Write
CYO
DMACY3

CY1
OMA CY4

CY2
DMACY5

CY3
CPU CYO

dk1
clk2
loRequest
cpuHoldReq
cpuHoldAck
loGrant

DMAwnte

iocmd
cpuCReq

;J::;:;:;:::;:;:;:::::;:;:;:;:;:;::::::::::::::::~ read bioCk

cpuCWMask

~::::::::::::

··:::~:::::::::::::::::::::::::::::=:·.

)zm4;].:lrr:~.~te ad~~~~::~;/<~~>/

write

cpuAdr

OMA
address
t:i:i:i*i:l:i:i:i:fa:i:i:i:i:i:i:i:i:i:i+:t:i:i;;:i:i:i:i:fa:i:i;i:i:i:i:i:Ei\E-,;~:::;:~:·::~;:;:;~:;'.;~:....~
....,;,;.;,;..,;,;.;,;...,,..._______~~

cpuData

drvSysData

ttF..

==t~~~III1Iilt:L

sysOOE
cpuOOE_I

-=~i ~:~[li~:;i: : = =· _:,:;. . ····====<~iilii::ij:E:~:ti::i:=:=:·.

cpuOWSel

.<~trnr j\\=:·:·.

cpuCAck

------f-::;:-;:;:-;:;:;-:;::-:;:;·-,---

··::::::f/=r~~~jftI\::·

cpuORAck
ioOataRdy
ioCAck
sysEarlyOEEn
sysTagOEEn

.·.·.·.·.-.·

bcTagCEOE_I

-~::::

sysOataOEEn
bcOataCEOE_I

··:-::::/f?f?"

.. :-:·:·:-:-

~~'.~!'.':'.(::··. ·.· '·::-::::<:,:,::O:rw

sysTagVOP

,_ •

i\!~\!;\L . /~!!Jji ,,i.;:;·,,;;:;:~!...---~-----~----~-----~
.
.:-: ·-:-.-:: :-:-:-. :-. : . ~. :-·

.-::::::::::;:::::.

,:_:;_:·.~.:;_:[_.:.:~}: · · : : : : :t~.:~;~:\:·~:~:~; ;i; ~; :'.; ; ; : : : :;: !: ;:;~\[:f:-~:i:·: =;:;:i:M:i:·:·: :·:·:·\

sy:::_.R_L_·_.:_._:.'i:_:'._;'_i!_:'.:__

sysoau.~~~i'i/'.;:,..:;::.,.::_ _ _ _..=_= :...::~:_t_(_f_\_t_::::_:':"_·- - - - - - - . . . - - - - - - - - - - - - - - - - ·

.AEIJ!1f!~~J..;..~!.·.;·.,"~:~.;~:.~ ;:.; \,;.-.:,=,""===·.----------------------------..

==::::/?i::::/:::=:=::===:=::=:::::::=i•~:~

:}ft>
.. :::·=······
:::::::::::::::::\:}\}):..

1>ct~~~We_1

.<Ht.L_<::::~md

· · =: : : :j: j: : : :i i:i l~:it~=1., .: :·" '.: : " : : . .,;: : " ': : :" /__.,,\. . .:..·".:.::." :.: : : ...:-::. ,:\___________________
.,., ;t.:.:::::....::;::...::::...:::l:""::::\~-~:::::,------------------reset

·"!7'-

··.· :: :::;:;:; :_; .:::;::<;::;.::.: :_::;ili!il!lliil/>

TAG Turnaround

TAG lnval

Wait for ACK
OMA Terminate
Bus Turnaround

CPU Adr Late

CPU Write

:::::::::::·:::;:;:;:·

load

CPU Write
W-03149-TIO

Digital Confidential 5-65

Figure 5-26 Switch From DMA Read to CPU Write

.·.·.·.··:·::::: ..

.·:::if~:::::::::::::::~:::::::::::.;:·.

CYO
RDCY3

CY1
RDCY4

CY3

CY2

c:lk1
ctk2
loRequest
cpuHoldReq
cpuHoldAc:k
ioGrant
ioCmd
cpuCReq
cpuCWMask
cpuAdr

cpuOata
drvSysOata
sys DOE
cpuOOE_I
cpuDWSel
cpuCAc:k
cpuDRAc:k
ioOataRdy
•:-:;:.:::·:·:-·.·.··.·.·.·.·.·.·

ioCAc:k

idle

sysEarlyOEEn
··:.:-:<·>:::-:::::::::;:::::

sysTagOEEn

:-:·:-:·.·.

··:,:-:::: .·.·

:iii8~·:;::..
::::...
:;:;:""': : ..
:::\______________

"':;::~;t2:,:;:1~~!···
:::::::::.:::::::·

,.;:;:::::::;:;:;.· • .·:=:::::::::::

~::::::i[_:_:::,...,~:...:;:i~...:m:...: : . ,/,. };:.,. ~; ;·'" ;\:[ _?_'.·
~: :
~~ffl.~q ·:::~,~~Jittt\L:::.;. . . . .,.i:<tt>·

::1·...: : ...:~: :---------......
...:
-----

_ _.,..}...
) ......
::'.:_t_-=:_=:::...

,~~d..~:eri

B
.·.:·

......

..\:.;:.;:. .

·-=zt~~~~~~~~~~~~~~~:~::i~~;~;:r~

=====..
==:==...
===\
...._ _ _ _ _ _ _ _ _ _ _ __...._ _ _ __

•+xiiff,i;;o:f!le1~\!L·»,. !::;'""' :"'~:.~ .

::::.11.i_==:==_=:\
_ _ _ _..___ _ _ __,__ _ _ ___._

""'"':·::. ·:·:::::\:::,bcOatawe_r .. ,,~.

..:-:):::'

<{\ _[{ sysTagWE
.;:/:/))icTagCtlWE_I
sysCmc:t
I

OMA Read
Hit

5-66 Digital Confidential

OMA Read
Hit

BUS
Turnaround

CPU ADA Late

CPU Write

W-03150-TIO

;:~~~%~e:!1!t~!~~~~:;~!S~1J(j~l1111w

~:~::~:T:jsd:=;~ ~~:;_n~~~~·!!;liif~~s:_,;~ttf cPu,

read miss transaction is in :!tlii~:,~:~!lltiteycl: of
~:n~h~~~:;°i?e~~;~:es~:~1•'i\lti;!~\!sserts sysEarly-

0. A OMA

Section 5.2.2.2.2. One cycle before ioCAck<'l~l>!i!i.1$.~_rts, tlh¥21071-CA chip
decides that the CPU has won arbitration. · ·=·======================:=:=:=:====-=·
1.

2. The CPU transaction is processem1iiiii1:[1i\=··

····==:::::=itiiii[i[!:![:i!·![il'=·

: !~}=·

;;; ' '%\l lll!1'111it1t_i;_;:_1_:_=_

{,l,!ll\!111~b

·'.;:::;:::::::::;::::::::::::::::::·:·.

...

Digital Confidential 5-67

.::::=:t:}//:;:::::1·:.:·!::lllll!::·:1i1'.:i@i::::::..

.Figure 5-27 Swttch From CPU
CYO

Re~ cPu wme, ro o~AJI!;, 1iill[, ijjfflilV
to

and

·=:::t{f?t\f .:-:-:-

CY1

CY2
CPU CY2

OMA CY6/CPU CYO CPU CY1

CY3
CPU CY3

ctkt
clk2

,: : t: :f i~:i: \

ioRequest
cpuHoldReq
cpuHoldAck
ioGrant
loCmd

cpuAdr

________. ._____________·" "· " ·.,;.,;~.."'..,.__, "::_1ljfll1llti1i11~1(1t;

= ::: '.;: ; '
.

OMA read

mrx1dle

.-:::::::::::::::::::::::::::::::::::::::::•.

CPO ~rite adliess::::<::::::;;:;:;:;:::::>..

ii:i:i:::i:i:i:::i:i:i:f:i:::::!:i:i:::i:fE!)C

;;~1111.:_

~== r-;Wh{,~$+W-h~~.:·.::,:_:·,:;.·::.:::_.~:::.:.:::::.~::::.·-:.:.:!.:::_;_:_:':_,:.:,::_,:_::-,::.
.. )~f

sysDOE

cpuDOE_I

i:i:):i:i:i:i:i:i:i:i:i:i:t:i:i:i:i:i:i:i:bt:itfm

cpuOWSel

·=/jf~{~ff'

{\f}{.

·:·:::::mm::::::::::i:i:l:i:i:i:\:l:i:i;;:;:i:i:i:i:i\1

·.:··

\·;··:y(~f-:·:·:y·:·:·:·.r

.::::::::~-::i::i:~:::'.:'.::::'.:::::::j:::;:;:·:w . :::::::::~:::::IJI1I:::;:::::\

cpUCAck
cpuDRAck
ioDataRdy

'.;:;:;:::::::::::::::::::!::::::.

sysEarlyOEEn
sysTagOEEn
bcTagCEOE_I
sysTagVOP
sysDataOEEn

bc::::~R:~:::::;;:: ·\: : :i:l1l1lti: : : :l\l: :~: i: : :·
sysDataALE~i:::n:>·

"-::\tttf?/::::}:{}:{:}::· :

r. .

sysOa~~ij~::t~t.,.::----····-::::_\_fi.-.t,..f..t...?_}_::::'_.·- - - - - - - - - - - bcO~~t}~fa:,..

•..,...,.__ _ _ _ _ _ _ _ _ _.._._ _ _ _ _ _ _ _ _ _--!o

··-:-:/)flt:::,,gata~~~:i:.,;,;:~:~.: : :., : : ;,;,;: : :,.,.: :.: : .:" ': : " :.:-.------------------

.·.·.·.·.·

. . :-:·: mm:mt~.:.:::_:,~~.WE_I

....

··:\::~Y:~~WE

........

·=<:: ...•
·:-:-:-:.:-:

····:·:·:·::: ..

··:·:::::::::::·:-:·:·:·:·:·:·······

··=:::::~~~~~~~~~~~~rj~~r~~~:::.;

----------------------

:·· :::·:::::::·:::::·

-:-:-:.:-:.:-:-:;:::·::

reset

OMA Read
CPU Write
CPU Write
Tag Probe
Note:
ioRequest Is not important during this transaction.
·.·.:-:-;-:-:-:-:-:-:-:-:-:-:-·
·-:·:-:.·-:-:.:··

5-68 Digital Confidential

.. · · · · · · · ·· · · ·

.---....-,;.,·.,-,,----;,;,'';,;,::;:;,;,;:::::,..::::..,:::::,..::::~::::~;:;:::..,::::,..::;:.........···.·..

wrs s

W-03162· TIO

·-=::::(\~~~}·

.:1..1,:_J,!__l_:\..1,:.l,.:,:_.:.:_.:,:_.:.:_:_:::-

........·.·

oM~ Previous~

gmn~t~tl~ilWW'

s.2.:u.4 oMA to
cache
Released To
to the 21071-DA chip after a release the CPU must be.:::f.9f~!)~fffroiffrib.it%/?
cache. This is shown in Figure 5-28.
..:::tt\t\l!i]i\I]Jt\:::;. .. : : : : : : : : : :-·

qfa~l.~~b~ibed "iii:::i~~l.ja;·

0. A DMA read miss transaction is in progress,
of
Section 5.2.2.2.2. The 21071-CA chip .9:~~des tfiA~\:!tID.tgl071-DA>t.hip has
won arbitration and asserts cpuHolcU;J.jql:=an..d ioGHiritWflt:::::.,
1. The DMA read miss completes.
·.:::::\?" ./l::ll·lll··':jl:'[l\:}t:·. "::::::::=t:i ::,·l:·jl·)·ji···i:"'l):
2. The 21071-DA chip sees ioGrant asserted afi:a':wt.\it$.:::for cptiHoldAck. ·In the
fastest case, cpuHoldAck asserts thi.i;t¢Y~l~~·.
·:::::::<:;::::;;:::::;:;:;;;;::;::::\

3. The 21071-CA chip asserts sysDat.ill~a:.!:l~m~ysTa~~En. The 21071-DA

~~:

~=~~~s=~illl~~' write. The 21071-CA
bfff

'\!~llllll>

<!{flilll!!~!!;;;' .;' .

·.:.:.:=:·:·:·:-:-:·:·:·:<·:·:·:-:·
···········.
·.•.·.'.:-:·:-:-:-·

Digital Confidential 5-69

Figure 5-28 Switch From CPU Released To OMA Write
CYO
RD CY6

CY1
RD CY7/
WRCYO

CY2
RD CVS/
WRCY1

CY3
WRCY2

clk1

clk2
lo Request

cpuHoldReq
cpuHoldAck
ioGrant
ioCmd

rea

cpuCReq
cpuCWMask
I

.-:::

}}}~{::; ::::::::::•.

··:•::::;::'.:::::::,"

cpuAcr :~::::::::::::::::::::::::::::::::::::::::::::::~:::::::::::::::::::::::::::::::::::::::::::::~:i::): . ·.·.· ·.· .·.-... ::::::::::::::::~OMA a!@tess
~:i;;;;~;;;;;::::::::::::::::::::::::Z.:::::,.:::::::::::::·::::::::::::::::::::.:::::::::::i::

cpuData

dnlSysData
··:·:·:·:·::.:-:-:-:-:-

sysDOE

cpuooe_1 :~:·:·:i:·:·:!:!:i:i:·:Wt:/::=::i:N:!:!f:·:!:!:!:!:N:OO!i!iliW ..;:\{\ :::::::::::::::::::..
cpuDWSel

····::'./(:'"°: ..::::::::::;:;::::.

: ·-:·::: .;: : :'.:'.: ···· ::;:::;::::-.

cpuCAck
·.·-:···:-:;:·····:-:·

.... ::::::::::::::::.....

cpuORAck

ioDataRdy
ioCAck

id e

···:-::::::::::: .;.:::::.::;.;.;:;:;.

··.·,:::~Kt:?K'::,,::::::::::: . .

sysEartyOEEn

·.::\}}}} ~{{;:~\.·.

sysTagOEEn

l:;::::;:;:;::i::::::f

bcrageeoe_1_.,::::ti}!fI:{:H:::::{:IrnI::;::::::::::::::::::::ii:Ui:;:;:~'.''':·

sy:~::~:il-ll.llli·::r::·:·.. . ;..:·: .: : : :.: : : :~: ..

~:Wt:::i:::i:i:::i:i:::i:i\
~:::;:i:i:i:i:/:i:i:i:i:::i:i:Ji:i:i:i:r.;:\:i:i:i;#~

':i:i:i:it:i:i#

bcDataceoeSi::::::rn:i:::::::i:M::rntt:::::=:::=:i:::i!kmk::::::::;:;:;::::::::k

t:;:;:::;::{i{::i:::::::),

.·.·(tftf)ft... _ ;)~~trtr
·
Cffi~~~eq ~--~~~~~~~~~~;...-~~~~.;-~~~~..;.-~~~--~
_sy~mr.LEn •:::::::rt>tI\t/Y)f.
... =:=:=:-.

. ·:::::m~HEn
.···:·:::::::'.:::::::::::::::::::::::;..

·-:-:::'.;:::::::::::::;:::;:=::::···

··::::::::::::;~~fm:tir.:.;._: ::::=:=:=·:;:·::::::=:=·:::::1=·=::::·=·=·:::{::·:·:;:::::::::::i:·:·:·:;:;:;:::i:::i:i:1:~

sys~i~Jt\::::::...

bcDataWE2f:)i):t::::::::::::::::·:·:·:·:::·:·:::::i:::i:\:&:J:·:·:'-·:·:·:·:·:·:·:·:·:·:i:::::::::::~

sysTagWE ·.~::•:'~·:·:·-:··~~~-.--~~~--.--~--~~--~~~~---~~~~::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::1,

sysCmd
OMA

Read

OMA Read
Holdreq to CPU

OMA Write

OMA Terminate
W-03163· TIO

5-70 Digital Confidential

5.2.3.3 Preemption

.. -·:·: ;:-:;:;.:-:...
Reads and writes to 110 space, and all barriers may ~fmf:~~P.t.~d

:~~~~~!et~:rf~'::!~~:::~thi: ::~r.a'~

transactions are complete, the suspended GPU tran~i.i\9..ll is resuIHl«F'
5.2.3.3.1 110 Write Preempted for OMA

"!?~1t~;!1.s awrite

block transaction to remote 1/0 space that requifi.ii\iP.t®.:µiptioii/" This section
is concerned with the details of the pree:m-p:QQ:rt· FSHg~t@J~t.about the write
block to 1/0 space, see Section 5.2.1.3.gf:fqf:i)!it~Us ab~iil,iilb~ DMA read, see

'~!!IF 'V!f,i~lll!lllll~> "

Figure &-14.

The is idle, is ownec(llll,.L
bus

and

~: :: ~::;::•:::i1~~:!1t:::~:q:~:~lock.
condition, and r&iuet!~~~=Jt.Preeiiipj:::q:~·g··ioRequest<l:O>.
·:=::}:::::::::\{}::::..
.
··=·=::::;::::::::::::::::::::::;:::::.·.

_ _ _ _;,;.;. ,::::;,;,;,;:::::::.,. :,.;._ _ _-::....
::x.;,;,;,:::;::~;;;.:r:,...<:~.,..,>=-:::::
...

·-:-:::{~·.'.~,~-.=.,~.:..,: ~· .=.,=,~-,=,~:~..:~:.·._:.·_::~-~.?:·

Note':::: ____________

Preempt c:~aii£·j·ih~~que~~:~:a::·a~rl~g a 1/0 write until the CPU data
has been latched;tb.~tm§~ that°data will be lost.
' . . . ::: :::::::::::::::: :::::;::::::::.. .

.;:;:;::=;:: :::::::=::::::::::::::·:::;:::-:-:-:-:·.

·-:::::::~(.::.·~ .~:.·~ -~ -~ .:.· =:·~·:· .:.: :·~.-:.·~?

3. The 21QZtf:(lif\;IP,%e~iv~~<tl1e preempt, asserts cpuHoldReq and ioGrant.

: :;,.~lli1~:~1: :i:::~t:::r;~~oldAck.

6. 3Qij::;~:~o7·i~i(.JWJ:illij::\i~'~eives cpuHoldAck and turns the cache on with
:{\:t[~i\~Q~taOEEn
sysTagOEEn. The 21071-DA chip places its transaction
"":Bnltne\bus. It also determines that another DMA transaction will not be
re~Gif~ab.:~i~e the preempt, and returns ioRequest<l:O> to idle (or request
a regtit4.r!:jfjMA is desired after the 1/0 write).

and

2101{:~bA chip detects a cache hit, and loads the DMA read and 1/0

write buffer with the data.
The 21071-CA chip loads the second octaword of data and acknowledges
·::::::9\))(/\:::::. _the DMA transaction on ioCAck<l:O>. It samples ioRequest<l:O> and finds
'"::\\.::)}}@J~at the preempt no longer exists, and deasserts ioGrant.

Digital Confidential 5-71

.4\f J•&,J')ifliib

The 21071-DA

1
chip sees the deassertion ioGrant an4,,gi~!!s~l~! Jf

;:::i,~;~71-CA

chip deasserts cpuHoldAck and :i'WQl~'"·~:tptit

It also sees ioCAck< 1:0> and knows that the DMA . trmi.i~ti9..n is"='C9mi!!jK

The 21071-DA chip sees that the DMi\. transacfiib.?W:~ complet"Eflist cycle,

s~~E:~r:;:~~:?o!!i~!tii~l~~r

next cycle.
..·.·=-=·=·.·. ··==:===~~Hlllijjji:.·:l·':·1::=::tt\=::. · =:=: .
10. CpuHoldAck deasserts, the 21071-04?¢.mPA~:~es cpulJjJQ.Ack deasserted and
deasserts sysDataOEEn.
::):::;::::::::~r:::=::\:;,:ii:r:::iht>=··
. . ==:=:==: : ==-·
The 21071-CA chip enables its d~~::lbus drlV~IIU\~ 1/0 read was
preempted. The 21071-DA cqjp:\\li.ii~~. ioGranF~'d cpuHoldAck both
deasserted and continues the.:::pf;emP:ti:gd~J?U transaction. The remaining
cycles are the same as the,/r~gµ'.lar ri."CM!4.&mpted transaction, resuming
where the preemp.t intenqp~q~it.
····:::::::::::f]t=.
11.

~:~%ec!1::P:1e'l!c~?:r11Ked earlier, the ·transaction is
:·::;~\::::::·

... :.;:;.;.· ";:::;:::::::\~\::::::-.

::-:::::::::::::::::::;::-:-.

=::::::::::::=::=::::-:::.:::=::.,.:::::

=::=::::rnt.,:l.l:: ... }"=:
.-=.:

- .. ::=: =-.

···::=::=:::>.::/:::::::=::=:\:::::.;.
·-·.:-:-:.:-:-:-:-:-:.

5-72 Digital Confidential

·-=::::::}:}::=:

:::::::::·:- ·:;:-.

<r.-~.~.~.~.~~.~~.::::

:-'.::<tr=···

Figure 5-29

CYO

CY1

CY2

CY3

ctk1
ctk2

loRequest
cpuHoldReq
cpuHoldAck

~~»
....
:·:·.,..
..:·: ,. ·:·:....
·:·:·,..:·:·--...-----.....- - - - - . . . - - - -......_..,..,....,..·:...,:::::...,::.*::--:·:--.-~""""~

ioGrant

i:;:::::i:::::::::::::::::::i::::::/

.. -.·.·.··:·:·:-:·:. ....

idle
ioCmd

cpuAdr
cpuData

r::::::::::

}:i:i:i:i:::::::i:i:i:i:i:i:i:i:i:::i:(:(:i:i:i;@m writet§ address

:~: : : : : : : : : : : : : : : : : : : : : : : :i

drvSysOata

":::::_·-.··· . ..............

~----------.:~

::::::::;;::::::·

T'"'.)if{'}\=:::....

~~>~::::~«:~~~~;~;;~;;~~\~\~:~~)~\~,. ______...__________..
\jj/J:\
,:;::::::::::::::&:·. iW:i:i:i:i:i:i:i:i:i:i:i:i:f..::::::::~:::::::··
cpuDWSel ~--------~-,;,;,·;,;,;"-..";,;,;;..-.,......f""·:::...
: : .·: :.;. ,.; ; ;...\ ...:; ; ~):(: : .: :.:_'.:.: , !~\~: : :~;: : ~:;: ...: : :""';: : ""':;:....:\..._-!-_ _ _ _~----------!sysDOE

-------------------....1~~:~~~~:~«~;~;:~:~:~~;~0;;,;,,_1;;:?

cpuDOE_I

"'·:-:-:·:·:·:-:-· _ .·:?tt...

cpuCAck

::•:=::·:

:::::::::::·

cpuDRAck

sysTagOEEn
bcTagCEOE_I
sysTagVDP
sysDataOEEn

-:-:-:-:-:-:-:-:

bcDataCEOE_I

_f .:;::-:-:-:

.·.-.·~}l

·:::::::::td::r:·

.:i::::: 2

-:·:·.·.·

cpuDinvReq . •

sysOataALEn!f:f!i!=~::::=::::=:=· '":\:t:§:::'~:::::}::: :-:· .-:-:-:·:· ::':':':/:
. .-.·.-.v.·.·

"' w3j:+j-..;j.:;.: -:,:~:-:~;: -:

·-:-:J\::::;::::;:·:::::-:-:-:-:::::-·

::-::<:--:••- -......._ _ _ _ ___,.___ _ _ _ __,__ _ _ _ _ _......________.___ _ _ _ _ _...a.

::rnmrn.l} :·:· :rn:P~~B.~'~Y'E_,
-:-:-:-:-:-: ·:;:::::::::

: : : ;:;: ;: :

:-:-:- ·- -

":·:-:-:-:-:-:-:-:-:·>.....

":·::::::::1:::::\<:\ t>~
·-:(~j~if~!'E ------.-...,;,;.;,;,-------------------------------------

bcf:-~_I

<\t#~emc1
:-:-:-:-:--

l ~\!; !i :r.

""'.:'./~){)\{ :-:·:-:-:-:-:-..

:;::::::;:i:;:::::i::::::H::::::::::;:i:::::::f
•

•

Idle

•

CPU Write

•

CPU Write
Preempt ARB

•

Request Cache

•

Wait for ACK

•

OMA has Cache

Issue Grant

W·03168·TIO

Digital Confidential 5-73

CY6

CVS

CY7

CY9

clk1
clk2

ioRequest
cpuHoldReq
cpuHoldAck
ioGrant

cpuCReq
cpuCWMask

cpuAdr

:fi:i:i:::J:i:;:i:::i:i:!:l:NI OMA cac address

cpuOata

·:::;:;:;:;::::::· :;:;::::::::::::::::::::::: ;:;:;:::::::::::~·

drvSysOata

...

~::::::::::;: ;:;:;:;:;:::;:;::::::::::::::::::~:;f::::::.··.

sysOOE

.·>>>.-.;-:-:.:-:.:
······.:..:·······

cpuOOE_I
cpuDWSel
cpuCAck

i:::=:=:=:;~:=:=:=:=:::=~::;:;::m

·.·.:-:-:.:-:-:.:;:;:;:;:;:.:;:-::::•:-.

··:<::::·'.
..
•
··.·.·.·.·.·.·.·.·.·.·,·.·.·.·.·
-:::;:;:::::::::;:;:;:;::::::::::::::::-._f.l::;:;:;:;:;:;:;:;:;:;:;:;:;:;::i
········.·.··.·.·.·.·.'.;.··
·.·.:-:·,

))t'.'o':;..·;:;:. ,: : ._;:;:._;:;:..::::..::::...::::...\ _ _.______...

ioDataAdy

·idle

ioCAck
sysEarlyOEEn
sysTagOEEn

... ········,·.·.·.·.·.·.·

cpuDRAck

.·.·-·.·.·.·.·.·.-·r.·.·.·.·.·.·.

~·-:::::;\~\f::::::::

bcTagCEOE_I

~:;:;:::i:::;:;:::::::::::::i:::~::::::rtt=::::::::::x ~t: :. : : : : : : :·: .
sysOataOEEn ::l.i$l4/::::: .·.·.·.-.-.·.·-;:· · ·

Efil[[

sysTagVOP

bcoataceoef: ~:=:;::t:;:;:,::::::::=):.!!:::': Y?
:-:-:.:-:-:

cpuOinvReq};;,;:~.;,;:::::.;,;-:·,..._...,.·:-'"':-:·'"':·.;,;:·:-.;,;:· ---.....-·,;,;·,;,;··-.·- - - - - - - - - - - - - - - - - - - -

sysO~'ALEn ·': : +!~'...·:. .,·:-:,. -:·...

--;---~==~~\.:I. i;i;..,h.,.i:i:i...,:9
.

::::...,::::...,/.._-=:::_·

systj;~~~f!n

·:":-::::.:"::::::::::;:::::::::::::::

:;::Q!:;p~~4>

···.:::·:-<<~??+::.::.:·

··-:::::····

:.:·· ..
·.·
:-;.:-:-.
;.:.:.:-:.:·.:-:-:.;:::::}':.:.::::::::-:··-·
;::{: .......·.·.·
·.;.:-:

.·:-:-:-:-:
.-:-:-:-:-:.:-:

·-=· ..:-:-:-::::::::::·

:\.__-;------.;-------+

i.,.·:i:,..i:i:..,i:i;:..,f"':i::...

J!::::::::::l:::::::::::;:f

\""·:=:..
:::::""'::!:""::::"":::::.,.\_ _ _ _ _ _ _ _ __

/;'.:'.:'.:iJ.

•@:%

··:~#W~it :::-.~

sv~Wijw_:s_·::.::_: ?...f,.,.>,.,.>,..·:·....,.._ _ _.__ _ _ _....,_ _ _ _ _......._ _ _ _ __,__ _ _ _ _....
:::::-:·:·:

sysCmd
OMA Address

Tag Result
Cache Read

OMA Read Hit

BUS Turnaround

CPU ADA Late
CPUCYO
W-03169· TIO

5-74 Digital Confidential

5.2.4

··.· .·.·.·.·.·:-:-:.;
·.--::::::;:;:::::::::::::::~:~ :}}:·.

The normal speed allows one octaword.dffi~'.d~t~:::tR.be WHt~~~:::each cycle. It is
the default, and indicated by the bc_~pfi:gWf?t.l.1~\\\lAk\h.e ge"Iforal control register
being clear. Figure 5-30 shows the tim#ig of tW(fpl,~..tto-back writes. This
mode is also used as the base forJMl.~::9.r~:m~ttransacUO.ijH:.iming diagrams in the
previous section.
:0::::// ::>:::::¥(:\,:"··:::>· ·
·.·.··:·:·:··

-:;::::::::.-·.·.·

.·:::::::::::;::::··-·.·.·.·

Figure 5-30 Tlml.ng of Regu@f:,_,_!'rltes:J:[\\~\\:['\[\!\:\\\}>:·
clk1

\ :,:,;,;:::r?" lt?:\... \"' ' ' .' 't::::::i::::' ti:m::::::::... , ___i

clk2

:/':' :::::,. \

-:~::=::::;:;:::::::::::;::.

. ·::::::::::::::::~·:i:.i@:\ . . \

·.·.·.·.·.-.•.;.;-·.·.·.·.·.;.·.·.·.·.

··-:::::::+:rn::~::~1-::-- - ,____,

'---

.;::::::::::::;::-:·:·:··-·.·.·.·.

cpuData
sysDataALEn

·
··,:.·····

sysDataAHEn

_ _ _ _,..............~--·-·:-:-:,_:=-:~·:::~·-·.·.···-·....._
.
__
t_::::~~-n-::~:~_:t:_~w

-:::::~!~~:(;~~}~~~~~~~~~~~{ :-:.:·:-:-:·. -:-:
bcDataA<4> ---~....-..-·~,·~·:·:···-····~··_,..,._ _ _ _ _ _ _ _ _ _A_::::~:,__:m/
:-:-:·:-:-:·:-:-:-:

sysDataWEEn

. '•': : : : : :•: : :

...

\_p_+_N_rn_m_:\_______
\_w:_m~:='~---

.,,,:::·:::::)fit::;:~:;:;iiii:;:;:#::gt

LJ-03287-TIO

·.::::{){{:;.;:·::~:~:~·:·.:...·

Digital Confidential 5-75

Figure 5-31 Timing of Long Writes

clk1
clk2
cpuData

. ·::::.:;:::::::: ·.·.·.·.·.·:-.:~;. .

.. ::::::=:::=:·::~:::'::t:>l::;:~;:;:::;:;:::;:;q :

sysDataALEn
sysOataAHEn

bcDataA<4>

_:::~:r~\~~~{:::;.·.

l~:~:;~::l::~~:~:~:~:~:~::t~:.:

:::·:··

sysOataLongWE

\:::;:;:;:;:;:;:::::::;:::\
\:::::;:~::::;::::::::::\

·-:-::=-,-:;::::-:::4-··--------,"""::;:;:"""'::;:\

;:=::::::=?// ?{:::::;:;:;:;:::::::::;:::/ ·:::::::::;:::_,~;t~;2~;;>~::::::,..\___t.-:_::;::-:...,.:::::::::;:;:-:.,,_:::::-:f--\l'll,;i;':-::;:o;,;;;;:""";:;:o;,;;;;:;""":;:o;,;;;;:;"":;ip;.1!\----....

bcDataWE_I +-------io--··..,:-=···;,;,;,:/~:§;~:::::;""=::;:;:~;;/-::::\

·-::::;:::;:::=:;::f::=::: .;....

j~:;::::~):"':;:;::;~-:::;~"":1---\m::::::~::::::~:::::~~i:::::\

/:::::::::::::::::::Al

-=~-----=-

LJ-03288-TIO

5-76 Digital Confidential

5.3 Memory Transactions
5.3.1

:-:.··:·:·:·:·::::;:::;'.;:.

0. The transaction starts when memclkR coiii'eide~Jwith clk2R/'The row
. address is sent out on memAdr<ll:O>.
.,,,,'?' C7' ':':':'/'·· ..
.·.·.:-:·:·:·'.·'.·'.:.··

··.·.·.·

1. The appropriate memRAS_k8:0> i~rn~$~fi¢.9.:::~fte~·:,:W~i*ihg for the row

:i~~~!t:e~~~~~~et~;oc~:r~~~:Jl!~:~11ii~~p·· is 0. Turn off the
-:::::::::::::::::::.:;:::;:··-·:.

. ~
dd
h Id
=·:·=·=-:-:·:·:·=·:- :{::::::::::::::::::=·
2. W:mt 1or row a ress o . <:t'l/': ,,, ' ' ' ' '>??::::.:

. . . ..:-:-:
... .

!'.i:ea!t:!~~:~:~~ col@f;t~· AciJ~,,~ges to column. Programmed

m0feR~CCAaSs_1~ls~3l!.•~_.'__o:_'__. ; i_ ~sS~Hij~~!~!~~ ig deassert CAS. Programmed value
:_:,:_>_,:_:;
__

·:_l_.:·_;j

.J.

.. :-:.:.:.. .:.:-.-: .:-: .: -:::::.:.:-:.

memCmd<3:1~'''~h'li\i~~$tfn>m Nd:fJ'''to RDIMM, indicating to the 21071-BA
chip that me~9.TY cl8'.ta\n~~?t9. be latched with the memclk.R of cycle 6.
Program_m~~':'x!!9~t9f RDly!{ijw is 2.

6. memC~£1Q:'3:Q~::::j$?dE}.. sert~d, and kept deasserted for the CAS Precharge
durati~!~\tTh~::_ijf:ogra,ffiW,ed value of TCP is 1. mem reverts to NOP.
Cqlµµiifl~44ti~'~ ch.~~I~ to point to the next address after the Column
a<J~r~ss lf&lq\~:~f.~@,~p/satisfied. Programmed value of ColHold is 1.

';';'~'![•();;;; 111-~,;:~~;;:~S'kept deasserted until TCP counter expires.
... : : : : : : : -· '''\'\\1lM'\:\.Similaf::tgJ$ele 5. This is the last transfer, so memRAS_k8:0> deasserts.
/:\'i.ll\jjllll\jl:f>

. ,.jfit~.lli·arvMemD~f~ asserts a cycle after memCAS_k3:0> deassertion, causing

1
1!:,I . . • ;;;•. ;::

~;~!~~:~:r~Ef~~?;~£fo~:~~:eE::~~~~~s~!?Ed

.. ,.,,,,:::::::;::·:'.!'.:':··,!''~':-.'!!!':::\,:::,;pointer is switched to row.

''::''1'i..\rn'the state machine is in idle, but clk2 is low in this cycle. Wait until clk2 is
·::;:high.

Digital Confidential 5-77

........

.;:;:::::::::;:;::

··:·:·:·:·:-:-:-:-:-:·

···-=:}\I @i~{f/

5-78 Digital Confidential

Figure 5-32

·.·.

wlcp

·.·.··:::::@1:::: :::::

......

... ·.·.;.;.:.:+ .
·-:-:·:·:-:-:.:·•· -·-:::

.p---..:..:----;------;...----....;..----~.....,;,;.........;,;,;;;··~)~.:'l.l&~.:.":.;~::....,_---..·~)~>.....:~::::~11~·1~1--+~--1~11~1_ _.x
memCAS_L<l>
mamWE_1

.-:-

..:-·:::::::::~::::::::::: ..

ca_drvmd
mamData

:jlft]ihi::::f::·:·:·:·:·~:·:·:·:·:·:·:·:·:·:·:·::::;:;:;b§:::):·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:~·:·:·:·:i:·:i:f:;:·:'.:·:'.:'.:'.:·:J:'.:'.:'.:f.'.
.·.·.·.· ·. -·.:-:-:-·~·-:.: .::::~:rik~mm:= ::::::::;._
nop
x

:·:'.:'.:·:i:i:i:'.:·}:'.:\:.:\:'.:'.:·}:'.:'.:i:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:·:J

nop

ca_mamcmd

nop

latchad_data

CY13

CY14

CY15

waitO

wfcaslo

wfcashi

··:<:-:-:-:-:

CYB

CY9

wfcashi

wt~(

clk2
mamClk

.,,. ......wfidle
.

·-:.:-:.:.:-:·:;::~f

memAdr

~:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:;:·:;:;:·:;:;~:;:;:;:;:;:·:;:;:;:•:;:;:;:;:;:;:; ; ; ;: :i: :·::=-=:::·::@;::::..

4
••• :

:.:-:-:-:

~~~~~~{\.·.

•

Idle

··:·::::::::~~~-F-:i0~;~!::~~~~:::::::::::::::·:::EJrm.....----.c,..,OI-------.
··.:·:::~::

mernRAS_L<O>
memRAS_L<1>
memCAS_L

memCAS_L<3>

0000

memWE_1
ca_drvmd
mamData
ca_mamcmd
latched_data

;.;.;.;.;.;:;.;:;.;.;.;.;::·:·:·=·=·=·:·::=·=~·:=::;:;:;ifi;:;~.~::;::[::::;m:::;.~;:;.]:·:·=:·:::!Jli]·;;;:!:tr,.·:j,-----~-~'·:[·:·:~·:·:·J::;.~:·:.;. :.;[.::::;;i.;.;:;:·:·]:·:::[.;::[::::.[:·:·2:::::[:::::=E·::;.[::::.]·::::~·:>~---7--{mrm[:·:=:J::::[::.;;.::::[::::m:::.~:

x~·--r-d~·m~ffi~\~:::~:·:·:~·;,.....·_:::::~::::~·:"~····~··.·~::.:~::::~::x~-......~~e~j~_it:.:~::::~=:=:-~/:_:. ______~~-------_,,;n~op~------~...:..-----~
:

... :: .. . -::)~:}
-::::····:.:.:-:-

No~{):/:

'·-:-:;:::~::::;:;::::;::::::::·:·

.....
W-03172-TIO

Digital Confidential 5-79

5.3.2

5-80 Digital Confidential

Figure 5-33 Memory Read Followed by a Non-Pagemode MemoryJf.frlte
..:::::;::::::::::::~:~:::~:~:::::·

CYO

CY1

CY2

CY3

CY4

idle

wfcol

wfcaslo :})\\:

clk2
memCk

memAdr

·.·.·-:-:-:·······.·::::;:::;:;::::::·.·. ·)(:;:::i:\:i:::::i:::::i:::::i:::::i:::::::i;::;::

RowAddrey 1

)

memRAS_L<O>

··.·.·.·.<<:.:-:-:::::::·.·-:-:-:,.

memRAS_L<h
1111

memCAS_L

memWE_I

1111

memCAS_ L<3>

l!J

ca_drvmd
memData :;::::::i:::::::::::::::i::;i:{:::::::::::::::::H:::::::::.>
ca_memcmd

nop

~
jnk

latched_data

;;:;:::::::~:~:~:~:~::::::::;i~~::
..
-:·:::::·:::- ·.·.·.·.·.·.·.·.·.

CY7

CVS (:rn:[\iilJ· CY9
·.·.··:·'.·:::-~·=··

·: : :;:~ : :tb.¥-~\~}>
··:::::::

CY11

CY12

CY13

idle

waitO

wfras

·•·

clk2
memClk
wfcashi

.:,:~~~%i(\ : : : ;.,.

·· · ··•:-:

')~I!)

··.·.··:•:•:••_:•:•:::::)K====::;::::::::=:=:::::::::::::::=====i'.:;<;:/::::::::::::::i:::::::i::::==?'''=::::::,:,:::::::::::::::::::::::::::::::::::::;:;:;:;:,::::::::::::=:=:=:::::::::::::=========,::?::::::::::::::::~

memAdr
memRAS_L<O>

------....-----·-·:::::·.'.:;:~:~:~:~:;:;:;:;:;:;:~:;:;::·:·.·

memRAS_L<1>
memCAS_L
memCAS_L<3>

x...._____.:.1000~~·:'~··~··-··~-·~·~···~·~~:~:~·-~.----·~·~··~···~-1~1~1-1___________________________...,.

.··-:·•>.·:-:·:-·..•

.<·:-:-:·:·:·:-:-:-:-··· · :-:·:·:-:-:-:-:

··.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.··.·.·.·.·.·.·-:.:-:-:-:·:.?-:-:-:-·-:-

·""·_______.........,..,___ _ _ _ __,__ _ _ _ _ _ _ _,___ _ _ _ _-..._ _ _ _ ____,_

:-:.;-:.:;:;:-{'

memWE_I
ca_drvmd
memOata
ca_memcmd
latched_data

LJ-03173-TIO
-:-:- ..

_:_:_:_ ..

,:}'./

.. \::::::::::::.·
·.·.·.·.··:::::;:··-·. })}::.

Digital Confidential 5-81

:-:-::::::-:·:·::::;:=>

.·.·.·.·.
:::::::::

5.3.3 Memory Write Followed by a Page Mode Memo!:YtMf.rite ::::::::r:::::=·ttft><:::Figure 5-34 shows a memory write followed by a page./tqij~~i::~"W.9.!Y'\fii.ti~i!ff.

o. The default address sent out on memAdr is for a. Jl~i'. Th~:i::a~i.i~xon. to do
the write is taken in this cycle.

·===il1:iI:li1=··

·-====t\ibIF·.·

Wait for the address muxes to swit~!d~g[:th_~ w~tii~·i:::[i~l[jW:4~. time,==:=;he

21071-BA chip is already driving the. . fih~=:=:Writ..e dat~f()jfi~~JpemData

lines.

.·.·

\\\·

·:;::::.: ...... :·:·:-::..

. .-=-==:=:=:=:=:- ·

·-:\~}i~~;::-

memWE_k 1:0> asserts and is held as~_erted.\in~~::[)tb:~:Jmd of the
transaction.
.·.·.·.· =-== ·======· ·.:::;/\ ::;:::::::::;:;:;:::::
...
..

2. The appropriate memRAS_k8:0> =:i~:::;iji:§ift.~t~f!·~~r waiting for the row
address setup. The programmeg=:YAlµe of R6\V$~tYP· is 0.
... ::::::::::: ·:-··

3. Wait for row address hold.
4.

J{]:[ tmt?:':/H>=-

Row address hold wait cotrtpl~~~=.·· ~Ja;~~-)!!¢n@ges to column. Programmed
value of RowHoldjs 1. =>>< ,.:.:.:::.:.;:•. ..
··.-·::::::::::::::=:::::::
.·:·:-:.:-::;.,

5. Wait until coluffi~Niddr.~ss ~=~'ttipj:j:h~htJ~een satisfied before asserting

rnernCAS_l·=··<·=.·=.:_:=:=3=:·:=:.=·:°.>:··===tq!~f~IP._::_::_:f.:·.r_·.·.oifim~!p· value is 0.
.·.·.·.:·.·.

··:::<::·:::;::

··<=nm::. : : : :.: .'.:=:=:'+:>. ·

5-82 Digital Confidential

~~:= ~:::~s:s C:e:~:~~~••IL;:~:!;:C~~~~~; i':i~mn

9. ::~~-;;~a;.,:s:.i:·lf~t:.i~~!,,t:i~t0~~~!~::.emCmd<3:1>
10. Similar to cycle::':t1!i~::t·· .:-:-.

··-::':<:\,;:;:;:::::;:;:Lft> .·..·.

11. Address m~~~- swit~H-~i~i-~~kP.9~nt·-:~~:::fi~d; memWE_k 1:0> deasserted.
:::::::::=:"······

..:-::::::::::;::::;:;:;:::::::::-:·:;.

13. memWE_k1:0;'''''~~$.~l·~'\):~~dre;~tffi'.rix switches to point to write column.
14. Write colm1mAM~Al'es·~:"'i'$:.:~]!qJ1t the pins.
15. memCA$zt;i.:fi~lj\\i$.j'erts ·:n~1Y~nowing for appropriate column setup time .
..:·:-:.:-:-:
.·:-:-:-:.:-:.:-:·
······.·.

·.·.·.·
·-:-:-:-:- -:-:::::=::::::;:;.

·.;.·'.·'.·'.·'.;'.-'.

::::-:'.:::::::-:-·

.·.·.·. :.:-::::;:;::::;::::)\}:~:\~('./:=··

···=:::::~:~r~tz:t:?(=-·

Digital Confidential 5-83

memRAS_L<b - - - - - - - - - - - - memCAS_L _

·• :;::::::·•·: :-:•··

:\:{f:[f\:.

__..11...,1.-1- - - - - - - - - - - - - _ . . . ,
. ::~•·"-.;;''".-""--·_.·o::_,.:::,:,...:::·,._::-:~•""o,;,;"·,._·;,;,.,.--..X--0-.00....0_ _ _ _ _.....
·-:.·-:-:-::::::::;::::::-:::-:.;.:..

::::::::-:

memCAS_Lc3>
memCAS_LcO>

memWE_1
ca_drvmd

~_rnemand --"-o-P--.----~~--"-~..___,....,.-:·~:-:-:-~·-·.·~·..~··...-~~----no~P_·.:~--·.:~:J~.;;~;;~:~::·~·---~~---~-•m-m....__ _ _ _ _ _X,
memOata :j:·:·:i:·:·:·:·:·:·:·:·:·:·:·:·:·:i:·:·:::·:·:~:X
DO
·.·.·.·.·.. ·.·.·.·. ··.:.· ... ·::<:..... .
~
:

eve

;::~:

CY9

.. _:::>·

·-:-:·:·:-:-:-:;:;:::;::;::::: ..

.,cv1~(;:~>'""'' ':J;:v11 ..,,.:::::::::: ::'9¥1~><·:;::::~=·

cv13

CY14

CY15

waitO

wfcaslo

wfcashi

:::::::::::..

memClk
wfcp
memAdr

wfcashi

wtiClie)

{Ht:/'"

idle

···•:::;:::::::::::::::::;:/:~..........,.....
':'".....,Re.,.ad....__..-J'X....
:.:::...
::::;.....
::::::.....
:.:·:....
::.:·.....
:·:·::.....
::;::....
:::: .,:.::x.__..w.,,.r11,..,&'"'"co.._1- - - - -

co1

memRAS_LcO> _ _ _ _....__ _ _ _ _ _
"':'....;\.;;;../;;;;;,:u.;;+u;;;;,c:...,(;,;;;:::,.,...
.. _ _....__ _ __,__ _ __,__ _ ___..,_ _ __

.·.·.·.·.·.· ·:::/:?:?}}:::-....

memRAS_L
memCAS_LcO>

m&mWE_1

x__i-.ii.....i _

····· ······· ·

:-. .,.: ~:. ,.,:.,....': .-.---.__.x"-:_'\-').-..'.A-.'',\._''·---------------'*;>--..-oo=oo:...-_

_.X"-·_._:,:""')""":@;..,.' .":....
' , _,
...
::::::::::::;::/

:.::;::;::::::::-·

.. :::::::::::.

. . . . . . . . . . ___,......,·~-....;,;,;,;~
·.·.".·'....:~_·:..._: .'_.:.~:.~ :}"
·----,....::~;::::,..:;:;::..,.·:::::,,_':
..

~--,.,.,-_,:_'..,.:;:::o,;,;,:,:,,.._.:-:·:;;;,·:·:-o,;,;::.-.,.._:.:::;;;,::
•.;.:-D_''"_~·:::;;;,2-.,;L.;,o;:·:._ _ _----:(
.-:-::::.
.-:·:-:-:·:·:·:::···

:i\l5'~3.4 N@iory wrliEiVl=ollowed by a Non-Pagemode Memory Read
.,,,,{:~~- write portion of the transaction is the same as in Section 5.3.3. The
Because the default
··:::::'{:){ifllfl{~ddress sent out on memAdr<ll:O> is the read address, no extra cycles are
···::::::>::_'_]j~~µ.ired to switch the address mux, when a read is selected. The memRAS_
...,,,,,\:1$,~;q;> for the read can assert as early as cycle 13. Figure 5-35 shows a
meriiory write followed by a non-page mode memory read.

..,,.,,,.,,...,,,...,

.,.,:::t':E:·::·:::_y;_:.;::::=:::_ ..:JiJiI:µifference is in cycle 12 when the write is completed.

5-84 Digital Confidential

.·.·.· :-.·:·:·:·:·:·:'.;.·.
.·.·.·.·'.-:·:;.;.::::::::;:;:·

clk2
memCk

memRAS_L<h
memCAS_L

1111
.·:-:::::::::::{:::::::=:·.·.

memCAS_L<3>

0000

..-----...;-----.....;.-----.;----_,;,.:~:.~:.~:.=.'.'.:.~:.:.:.=.·.~::. •.:.~.~,,,:-.... ---...,..._,.....,.....~-~\_______
.:-:·:·:<::::·:-

<<·:·:::::::::::·.

memCAS_L«>>

memWE_1

·.·.-.-'.·

.·-.·.··:-:-:.:-:-:·:-'.·'.-:·:·

~~
ca_memcmd

:;x___n_.op_ _...-_ _ _ _ _

·~7~
_.'l."'"'_ _n_,op.._____...............
,.•. ,.,...
...·....
·.·._:::_:::....
:::::....
:::::....
::::...
::::,x;oi....
::: ......
,: ..,,.._nop..___....,..._ _ _ _
~:::::::-:-:··

memData :i:::::::::;:;:;:::::::::;::::::::::::::::::::::::::~\l(

·.·::-:·:.;.;.;-;:;.:-·:·.·.- ...

.·.·.·..............·

_,x.•__wr-1m_m_....,.
60

:·:•:•:•:::::-:·.

-:·:::;:::::<:)=··

CY7

CY11

CY12

CY13

wfidle

idle

wfcol

clk2
memClk

..;:- ?:?: wtcashi

wfcashi
memAdr
memRAS_L<O>

.·-::;:;:;:::;:::::;::::{:;<~:~::::

memRAS_L<1>

x 1h;:::::::. >>: X.,.,.:,···----·;,;o··~>~oo~.-.w.·~1~. - - - - " \ ' < x . - - - - : - 1 1 : " " : 1 " : " " 1 - - - - - - - - - - - memCAS_L<3> -----~,.............
...• ,......
,......,....._......,,..._
>tr , ,._----------memCAS_L

•.-::::-:-: .....·.· . . . .... ·. ·. -.: .;-:-:-:

,.,...

memCAS_L<O>

·:::;:(\ ..

:·::·:·:·:::·

'.:'.·~::::: :-::::::.. ::::: ?~:}?'

memWE_1

..J...

·:·~;:::-:-

_________________________

:.·

:)(\;\
}}~(:}

\...._

ca_drvmd

nop

ca_memcmd
:-:-:::;.... <; •..•.

next DO

_____
~

LJ-03175-TIO

Digital Confidential 5-85

5.3.5 Memory Refresh

5-86 Digital Confidential

.·.·.·:::::-:·.··

Figure 5-36 Memory Refresh

CY1

CYO

CY2

CY3

clk2
memClk

memAdr<11 :0>

invalid
Address not r~levant for CAS·~S refresh

memRAS_L<8:0> ~~~·~11~1~~.;.-~~~~....;..~~~~__.x~:~·=il~o:....-~~-r-~~.....;;··~"~·""4
"·~::;~,:,:,~:,::~:~
.. .,.,_~---'X
memRASB_L<8:0>

--~-a_11_1~~.._~~~~--~~~~__.x~·-ru_1_0__,~··-:':~.:;:~;::::~::::;~,:::.~...-.... ~.~~·-'_'''.':~_:;:::~::~t_:)~'./~:,,:_=-~__,X
1111

memCAS_L<3:0>
memWE_1

iµ

drvmemData

0000

.·.:.·.·.·<·····.

memData

CY11
ctk2
memClk

.....

::::::::::::::::::::::.

i.;.;.·.· .... "·"""""""'"""·

memAdr<11 :0>
memRAS_L<8:0>

8111

memRASB_L<8:0>

all 1

Row nl!xt transaction

X some RAS

memCAS_L<3:0>

. ... ·-:·: ........ .

1111

memWE_1

·.·)} .:.:_:_.'

.·.·'.

drvmemData

.·.·.·.·.·:·:·.·.·.·

memData

W-03174-TIO

·.·.:-:·:·:·.:=:=·"·····

··.·..

Digital Confidential 5-87

-:·:·:-··

6.1 Introduction

:··-·.·-:-:-:·:· ·.·....:.::::::·::::;::;:::;.;:·:::·:·:·:·:-:-:-:-:-:;:;:::::·:·:-:-:-:-:-:-:-:-:-:-:-.
;:;:;:;:::::::;:·:···:·::::::::::::::::;:;:::;:;:;:·:·:···

This chapter includes the following in.((,fqnatiorfa~l'-!:::,~e DECchip 21071-CA:
•

DC Electrical Data

•

AC Electrical Data

6.2 DC Electrical D@Jl.:t

.. -~:'.:~:'.:'.:~:?:;\~)\::..

.·.:-:-:-:-:·:·.·

-'.·'.;'.·'.;:;}:;: :·

·-:-:;:;:·:-:·.·
·-:-:-·-·.;.·.·.·.·

..::}:::.. ·.

This section con_!filns lh~?i:qq:::;~P,~ractetiip~~(for the DECchip 21071-CA.

s.2.1 Absolute Maxtl9:m,,,,,~~;''ri:§l.j)l!/l11iii!!·n:t::::.

Table 6-1 lists th.J\ffii.~imµµi radrt;mr'·the DECchip 21071-CA.

Table 6-2 lists the DC'~:ifl~~tj£ val,~es of the DECchip 21071-CA.

Digital Confidential 6-1

.•••)){
..

Table 6-1 DECchlp 21071-CA Maximum Ratings
Characteristics

Minimum

Maximum

Storage temperature

-55°C (-67°F)

12s 0 c (257°F)

·-:·::'.({~f ~~~::::::::::

..
. ....
..::::::::::::::··:-:-:-:

····:·:-::.:::::::;···?~t:···

·.·.·.·.·.·.·.·.·.·.·:;::::

40°C (~:9:4°F)

Operating ambient
temperature

.·:·:·:·:·:-:-:·:;.

-:::~:~:~:~:~:~:~:~:~:~:~:~:~:~:~:::: ..·

-::;::;~:~:~:~:~:::::::::::::::::;:;.

.·:·:-:·:·:·:·:-:-:.:.:··

··::::::::::·:::·:·:·:·:·:·

...
:;:·:·:·:·:·:·>:·:·:·:·:··

OLFM 1

Air flow>

··.·.·

Junction temperature
Supply voltage with respect
to Vss

-0.5V

Voltage on any pin with
respect to Vss

-0.5V

Maximum power:
@Vdd = 5.25 V
@sysClk = 33 MHz
1

LFM = Linear feet per minute

Symbol

Descriptio.tH{}.·

,})\Minimum Maximum Units

Input _pigh':t~l~~-=i::!:?'.

_::::::::::::::::;:·

lnpu~=:~~~:=·volt~~[:=.::::ij::l:::!!t:::::::::=:=::==·
0~~9~]ngh voltage==tt?'/:···

0.4

v
v
v
v

2.0
0.8
2.4

-5

-20

-120

-10

Test Conditions

1 .Eihli~fuih»:~J.Il.PDDin, scanEnable, vFrame, vRefresh, wideMem, testMode and tristateL.
OV < V~:?S::M'~~\:::.
2 For triststij~{:y,rame, and vRefresh.
3 For memPDDih, scanEnable, testMode, and wideMem.

6-2 Digital Confidential

-~:::\}{}}:;::::::}}}~{:.:·

Alilllllllllilf,\]fa \cs.
This section contains the AC characteristics for the::::Dl¢:~hip 2'i'fi1it*05.t
·.· Al\ii!il'.!lJl;i\mt. ><T

6.3 AC Electrical Data

::}}~\::::.
·.·-:::::::::::::::;:::.:::::....

The following AC electrical data is relative.ttf'tlk\~~=::with i{.1 ns edge
rate. All outputs have a 50pf load.
·-=·<:=-=::::::\'./\/;:
·:;::;;\~);~;~;~\{~~{: ....·.
:::'.;:::::::::::::;:;::.:-:-···::::::::::::=:::;::::;..

6.3.1 Clocks

··:·:·:::::::::::.:::···

::::::::;::::::::::::::::::::::::::::::::::;.:-.

The DECchip 21071-AA and DEQ~fiilf=~}Q~M. chipsets all use one clock
(running at twice the nominal)$.y)~~m freiju~fi~):=::plus a synchronous phase
=[:~signal to .~!~:rate 4lii\;;1~r;:al C1~'edges.
6-1

See Figure

·.·

.-:::}: :·:-:-:·:·:·

and

:;:;:)~{}::··

·.<:::::::::;:;:::: :;:;:;::;:;:;:;:;.;.

-:·:·:·.
:-:·:-:-:-:-:
-:-:-:-:-:-:-:-:-:

::::::;:::::::::::

·'.::::::::::/:

:::::::;:::;::::::-.

,.-,..........-.---···:-4.:-: ::::::::::::::::::::::::::.~.

sysClk0ut1 /::::: ::::=::::=:s::::=:=:=::

\ ::;

::-::::;:!·

i
I.

'
1

..-:-::;:::::::;:;::

··::'\\li~~\j\}.....
:::.:-.,___..,.._____

.:<?t:@>=================:f\\t::::]ittmem~·~rnt::=:;·=!·:=::?======··
··=·=·:-;.:-:-:-:-:-=-:-·

_.:::::::::::::::::::::::-

:{:}::;:::;::::::::·:·:-:···.
··.·

·.·.;.:·::;::::: ••
·:;:;:·:-:

,···:·:····

I
~

-----\

(
. ::(/t==\/)i':/:(=:·.

i
I

·:.;.:.:_._ {})Internally generated clocks.
···.·.·

LJ-03455-TIO

··:·:·:::::::::{::::::::-:-:-:-:.····.

Digital Confidential 6-3

Table 6-3 DECchlp 21071 ·CA Clock AC Characteristics

Parameter

Minimum

clklx2 period
clklx2 frequency

clklx2 high time

TBD
TBD
TBD
TBD

clklx2 low time
clklx2 rise time
clklx2 fall time

Maximum
.. ))\:::...

33: :::::::::::;:::::::·
·-:-:::;:::::::-·

-:.:·:·.

TBD
TBD

·:::4\.·.·.·

T,RR·:\,:::\:t>·
~nr< <:>;::r:·:::'_t_,::::~s
·.·.·

clk2ref setup to clklx2 rising

0.74

clk2ref hold from clklx2 rising

1.70

6-4 Digital Confidential

6.3.2 Signals

··:::::::::::::····

.·.:·::::'.-'.·'.·:·:·:·:·:;:;:·:·:·

See Figure 6-2, Figure 6-3 along with Table 6--4 and ]~B~iMf:*1:~i[[t:
.•

.·.:.:-:-:-:·::::::::: ;:::;:;>'.·:·

·-:·:-;.:.:-:.:-:·:·:-:-:-

Figure 6-2 DECchlp 21071-CA Output Delay Me~gti.fuent
··:;:;::::::;;:;:··········
·-:·:·:··

·:-:::::n:rnmit:::'.::::,. .
·.·.;-:-:-:-:

:'.{{:f:-.-.

····:·'.·'.·:-:·:·:·:-:·:-:-:·:;:;:·:

Digital Confidential 6-5

·:-:·:.:

;.··

:·:·:·:·····.·.·.·.·
:·:·:·:·:·:
·.·.-.·.·'.·:::::·

··::\~?:

Table 6-4 DECchlp 21071-CA AC Characteristics (Valld,,,Hf:@¥l
Slgnal

Minimum

Maximum

sysData<15:0>

6.8

19.2

tagAdr<3l:17>,P,
tagCtlVDP

7.0

20~.~:t::\::m'::,,,

cpuCAck<2:0>,
cpuDRAck<2:0>,
cpuDWSel<l>,
cpuDinvReq,
cpuHoldReq

4.8

sysDOE

4.5

·:·:·:·
:;:::::::::::::::::::{:;.:-:·:·:·:·:-:-:-:··

clklR

sysEarlyOEEn

clklF

sysTagOEEn

clklF

sysDataOEEn
sysDataWEEn
·:+~s<wc>,,

· :::::t::::=:::::+t>rBs

clk2F

TBS

sysDataALEn

::::;::TBS

TBS

sysDataAHEn

TBS

11.9

clklR

5.4

memClkR

4.5

12.l

memClkR

4.8

12.8

memClkR

4.9

13.0

memClkR

·-·-:-:-:·:-:-:-:-:-:-:-

me~AA%.~t:O>
:-:::::· ·-:·:·:-:-:-:=:-:··

(continued on next page)

6-6 Digital Confidential

.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.

Signal

Minimum

memPDClk,
memPFLoadJ

5.2

mem.DTOE_l

4.8

mem.DSF

3.8

sysCmd<2:0>

5.0

subCmdAB<l:O>

4.9

subCmdCommon

4.9

Maximum

Unit }@{r· Edge?\}Jif{\~9:,~s

12.8

···=:::::rhi~:nclkR

::ii~:

.::::ttili'tl\:,

clklR
~~ ......

sysReadOW

: .:·: .:.: :.: ===ti~iitil\::::: ns
4.5
4.5 ..:il\::=r:
11.8 '·:·:·:-:-: .. )1s

drvSysData

5.1 '·:=:::::\?\" \13.3

sysIORead

:.:.:-:·:··

drvSysData

··:::;:;:::::::::::::::::··:.:-:::::::.
...

clk2F

clk2R

4.5":::;:::::::: .. ::::::::::. 12.0

memClkR

:::::::::1::12.9

clk2R

.... iilili?>==:.

·.;.....

·.:-:-:-:.:-:-:-:-:-:-:

·-::::::=:::::::::::::::::::::::::::::;..

memCmd<3:1>

clklR
clklR
clk2R

/{~~(;L

drvMemData

clklR

·<=::t:~~:it

drvSysCSR

·.·. >\\@)i: >>~~8

··:::::::::·:·:·:·:·:·:::::::::-·

JJ't::[fi&t!irii!:::=:::- . ·. . . . . . . ·

:=:::=:: (:,:::

1. Two cycles, M¢..:.ifr~~~fJ,4.iif.Jt. r~~-µrning 'csR read data.
2. For CPU tf'#:~~cti°:~=::?,riiy.
3. For DMA ttj#.~~~tM~:"only..

f: .: : :\

...

·'.:'.:'.·'.·:;:::::: ···.- ·.·.

:!':1{/

..:::::::::::::·:·:··

...

·.·.·· ...
··.:.:-:.:.:-:-:-:-:-:-:-:-:-:-:;:::::::..

Digital Confidential 6-7

:::::::::::: :;:;:::::::;:::::::: :::::::::.._.

::.::. .,Ji·::::·t·
·-::::{::::

.Ji<?'

-:·:·:·:···:·:-:;:::-'·'.··

.-:·:·:·:····.·

Table &-5 DECchip 21011-CA AC Characteristics (Setup{~9~~,,!lme}:ll:j:·':':':,rn:::,:::::'::":i:::::::t·
Slgnal

Setup

Hold

sysData<15:0>

0.0

5.4

sysAdr<33:5>
sysAdr<33:5>

13.5
6.1

tagAdr<31:17>,
tagAdrP,
tagCtlVDP

0.4
-0.1

.·:-:-::::;:;:;;;::::::::

:: ::::

.::::::::: : :;: : : ~: ~: ~

..................

memPDDin, Se~~~:::t~l~[)!,j. ,f\=: ..

·:·:-:·:-:-:-:-:..

~~{//{:}'.::

.........

6-8 Digital Confidential

clklF

clk2R

...

,~l:@.~~~ijJ9r ;:~J!mii.:@R read data.

3. For DMA ~ffi~~actio9~(:@ly. .:::::::'=<

ns
·-:-:-:·:-:-:·:·:-:-:-:· ...

·-:·::::~/{{{{:}~\:·.·:-.

2. For CPU tr'#:'i#~illri~=:(~p~¥)

. .·.·.·

Note 2
Note 3

clklF

""<:?}~:

~,,,,.,

Note 2
clki'EtJ( .>::: Note 3

clklF

ioRequest<l:O>,
ioCmd<2:0>

.:-:::::/:}~:}}~:~::··

·-=:''<F¢.ll~i.f

cpuCWMask<7:0>
cpuCReq<2:0>
cpuHoldAck

1. Two cycles are.

·)i]]jt:]ljJfil~F

. ., :,::,.::,:-

oecchip 21 on~~1- ~ ,:~TrBW:a:~~
·:·:·:-:-:-:·:··

:{:~:}~:~:}::::::·:·..

·.;-:.:.:-

··:<:=::~:~~~~\~:;::·:·:·:·:·:·:··

This chapter describes the behavior ofl)~!~ill_gi9;:~~A chip on power-up

::::::=o~:::::~~~tl~=~:~rl&r=l~:!:!Jei~t:i:s:::.ud

7.1 Power-up

.::::::::::::){Ii

·-:-:t'\l!::~:::i.::[. l:;;:,,::::;,,:

On power-up, the r,¢~1.D iJlp~i~::8~--thJ,l1:piGchi;<~-1071-CA chip should be
asserted. It should B~fk¢.Pt::::A§~ertea=:::un§}11ilhe system clocks are up and
running for 20.J$$les. ·-: : : : : : : : : -:-:-· ·: : :. :-:·. ·
.··:::<iii~:::::··
. ·-:::;:{{:\\ {~~(::::.

The assertion and ~:~~j~~lt9~t:Qf t~~\f~,set_l pin on the module is asynchronous
to the DECchip,,,~:19:7J~CA'>l\P.{int~rnal reset signal is generated from reset_l
which assert~j~~Y#~pif:9.ti.ousl.Y'a~Vifoon as reset_l is asserted, but deasserts
synchronoqjiy{fbu~\;l~:'lh~)~ynchronous deassertion of the internal reset, the
DECchip ~1Jl71-CA.i)fequif¢$, that no external transaction should start until 10
system cloei.l\]~y~U~$.Hifter::ltJ.#~ deassertion of reset_l.
-}t\:::..

··=::::::tr~:~:~/:\/::

.;.;:/\~If{

1 .3 State:. ifFPin:S.n111:::::'.R.eset Assertion

'rhi.-l·(J.)\l~_ng is ~::;:::~al rule for the behavior of the DECchip 21071-CA chip
ifs::::P.miNJ.µr.ing reset:

~~:~tttl·i~ft)y· control signals (except the clocks and reset_l) should be in
deass~ft~d state as long as reset is asserted.

output only signals are deasserted.
All bidirectional signals are tristated.

Digital Confidential 7-1

The exceptions to these rules are as follows:

_., .,.,...

..........·.;.··

• ::~~~~!:~:~1,s:~a;?ee!:a::r:~e=~~~jil!~9/r~fts

(without waiting for the deassertion of synchroqQ.UJ$.i!iiintemar'f.~i,¢,~)~i}These
signals keep sysData<127:0>, sysChec.~,~7:0>, ·'t~gllJt$.~2:17>, anH?the tag
control signals driven during reset. ,::t::_j:_,::_'i"_:~lll:[/
·.·.,,:?::::f:~t\:lt:>:::: .
.-:;:;:::::;.

•
•

The presence detect logic activates on the::]J;~~l~~rtion.Br::~µt~fnal reset. For
details of the operation, refer to section SeCtiq~i::a:~~~T
·.· .··.·.··.
drvMemData is asserted by the DEQ¢}1.;~p,,,~1~·4:f:Sd~:::~~tthat
memData<127:0> are driven by th~'::;:iqzt·f:fi.A.Jluring%e'set.
f.·.·.·.·.·.·.·
:rJ:~:r·· ····:·::=·=:::::dWt~~f
~t~:=:=:·.
·.··.·.·.-.:::::::;:;:;:;:;:;:;:;:;:;.
.....
·:-:·:::::::~~
-.:;::::-:::::::::::.:- :-:::::··

------------_.:

In all cases, the assertion of l~fi~JWt,i·'m~r: overrl'des the assertion of
reset_l. That is, if tristate,,J,:i~Iasserl'ediiii4.y:Q.pg reset, all the outputs of
the DECchip 21071-CA g9:::!ij:'-~A~:~r High~z::=jt¥.te.

: :~~~~-~~,;~!!-~~~~f;.serts, the signals return
·'.·'.·'.·'.·'.·:·:·:;:;:;:;:::;:;:·::::..

··:·::::::::::::~:~:~:~:~:~:~:::::::::: ..

1 .4 configuration ·arll'~:::i:m@~et,.,,,owassertion
Software must initj~Jiz~'"ftiij!i:td.tI~wjng registers in the DECchip 21071-CA after
the deasserti9nrn~t:::f¢.$~t1L

··· ··· · · ··

• GeneraJJ·!\#~h~;~:i:.)fij~s.t~h

• Ta~ eni~J~::=:rd.Jl~r. -:::-::'::\;:;:
• B~~kset . :ri6nfi~t~~~~~:l:fegisters, to determine memory configuration refer
:::t9'''§iction 4:sn:=::n:=:ur=:=t:,:-·

• <ttf:i=fii~~t base address registers.
··:·:::::·:·'.·'.·'.·'.·'.·>:;:·:::.;:::~:::-.

Barikiij#ififil.i~g registers A and B, to determine the programmed values of
'\::;::::::::::::::::tne~;e r~gi$.~fS refer to Section 4. 6.
''"" .. v ...n .....

timing register.

Refresh timing register.

7-2 Digital Confidential

.. :::::::::\~~:\::::: ..·.

,.):jg::t::::[~.·~:.·::ijttt{\::.

t?..

:.: .~ .~ .~~.~~.~i.~..
.

'::'·'.:.=:.

: .:':~: ·.:.:.:.·:::.::.::.·.

::\}~~}::· ·.::::::::::::;::::=:·
.. . . . . . .. .

·.·:·'.·'.·'.·'.·.·

. :-: . ; . ; : : :

: : '.:::::::::

i!il!fl ;iffy :;t

The deassertion of internal reset causes the DECchip 2107.l.:-.CA to cci\M.m~ncij::t
doing refreshes. Most DRAMs require that they be refr..§.b.¢.ij[i:[~tJjmes:::~f.~t~i?/
any write or read transactions are addressed to them./i1Ji~FD.fiq~J#P::. 2f01I~t:A
does not guarantee this. Soft.ware has to ensure th~tm~inory . rel.~ii]~b.4.. writes
are not performed until the eight refreshes are compli:i.@.. The re°frij~lj%ate can
be increased using two mechanisms:
. /{:][}:==
·=:'='t\\ti:\l1i>t=:.
··.·
1. Software can use the force_Ref bit in lb~ r,¢,f~§P. ti~i:fig·j~~t~r to generate
back-to-back refreshes. In this case, soft.wifid#¥.t:to wr1tettll~ force_Ref
bit, wait 10 cycles for it to be cleared (indicatingiiit~tJ~ne refresh has been
completed), and then set it again fot.'.dm~tn~xt
reftii)#fiiitt
-::;::::::::;:::::::;:::::::·.·.·.·.;.·.·.·.
··.;.:-:-:-·.·.·.·.·.·.·.·
2. Software can also choose to set retfillJf.ifit.ijji. :jg\t.he refresh timing register
at its minimum value of 64 memQm/cycles<t~fim~~rval = 1). This will
cause refreshes to happen ev~=r1Il:~!\:!¥:~~em clo'Cli::"~Hes.

~r~~:~:::o~r oi~~ ~:f~~?!!~-!~v:.~m~~e:U:;ei:=~ten
:-·.:·:·:::::::··-·.·.·.·.·.·.·.·.

: :. .

·-::::::::::::;::;:;:::;:-:·;.::~:\:···

·.·.·.·.·.·.·.·.·.·.·.·.

Digital Confidential 7-3

Part II contains information about the

··:::::::;;.:::::::·:~~/:}:

·.:·.·.·.·.· ·:-:-::::::::::::--·····
::::{\::::-

··::::::;-·

The 21071-DA chip has three major hU.E.(:~·tiffQ;~~.s: ' ' >:'\;:\,,,,:·;;_,/:\,
.·.·.·.;.;.:·:·:·:········ >::::;:;:::;::::::;:::;:.:..

•

··::::;:~~){/"

•

sysBus
)fl?
·.'"'</. :.'.,·.·.·.·.·.·
·.·.·.·.·.· :\}:;.:..
Peripheral Component Interc9ppj¢tl.l(p91)
., , , , , ::;::,::::::::::·

•

ep1"Bus i"nte...c.ace
r1i

.·,,.··,,.,,,::.'.'.':.·,:/:>·: ..:::::::::::::/'''''\:,,,:,::-:·.
··:-:-:.:.:·::::::::::::::::::=::::::::·

This section provides;. a listing::@#.l.i)~~scrip.tidft:f[iji:Pin signals for the 21071-DA
chip.
:::::tt·
·-===:\//:Lt\:>. .
·····
;f~~:.:~.~ .·.;.·:,:.f~=,'.~.··.// .·.··:·:·······
..

··:-:·::::=: .... :::::::::=::: ...

. :-:;:;::::;:;::::::::::: ::;:::

8.1 DECchip 21 OZJ-DA<,'.i.ilm:::b,i.st · :::::·::::::::::::::.:.:.:,,,::::,=·
Table 8-1 desefilj~~\t.he. niiC:bfijj,lj®.:+.Qfl-D,A signals.

Buffer

Function

4ma

Address bus
Cycle request

Cycle write mask

Hold acknowledge

1/0

0
2

8ma

Command for DMA
transactions
Acknowledgment from
the 21071-CA chip on
DMA transactions
(continued on next page)

Digital Confidential 8-1

·-:·:·:··

Table 8-1 (Cont.) DECchlp 21071-DA Pin List
Number

In/Out

sysBus Signals
(50 Total)

ioDataRdy ·

··.· ::::::::;::::::.:·
.·.·.·.·.·.

}~~}/:'.:;::::::·.
:::~~~jj~~\{?~?
·:=::;:;:::::;:;·::::::·
..

Buffer
..
.. ::::·'.·

.{/~{~(
.::::::::·::::::::

·.--:-:-:· ·:·::::::;::·>:::-

·::::;:;.;.:-:·>
.·+rr~~~}}}(\..
<l::\~\::.~\):::
··:::?{\[iridi~te.s that the
;}} /\::r~qµ!~~t~ta is loaded

···-=:::/::::=)::::::=-:·: ... into.th.ij}~1071-BA chips
··:·:::::::c::::··::::·i::::::::[t~g~ ca1i"'be extracted

ioLineSel <1:0>

ioRequest

ioGrant

8-2 Digital Confidential

···:::::=t/Belects which cache line
. ,,,~b:~hld be read/written
froin the sysBus
::::::::::::::::·w~u.n.oat- for DMA
transaLctl~ons on sysBus
Indicates that the sysBus
has been granted to the
21071-DA chip
(continued on next page)

Table 8-1 (Cont.) DECchlp 21071-DA Pin List
Number

Buffer

In/Out

::;:::::::::·

PCI Pins (47 Total)

.;:::}}::::::::}~.

AD<31:0>

1/0

CBE1<3:0>

1/0

Par

1/0

FrameL
TrdyL
lrdyL
. StopL

1
1
1
1

PerrL

. =tt.h

. '"\{f:yq::t}: ...

Parity error
Indicates an atomic
transaction that
may take multiple
transactions to complete
Device select
Bus request
Bus grant
PCI clock

.. :::::::::::::::::::::::::::::::;::::::;:::::::::;:-:

::::::::::::::::::
.::::::::::::;::::

Mem~,~}::'· . \'}:\i\!::\:\}[:!:!J:t:y!)\:\\\[:\\i\:\:}'
·:-;.·.·.··:-:-·.-.·.·...

12116'.'ma

12116 ma
12116 ma

PCI SldebaridfPins -: :-:-:-:-:·:·=·
(2 Total)
.:,:,:,.,.,., )<\.:.:,:·

byW

: iJl~1·1:! !·{·1: :;: : :i

DevselL
ReqL

.;:;::... :;:·:

:~11111112~~d and

1/0 ::::{::::,.::::,_:::~ZtlltT,a .... :.;.::;,,Qi~ie frame
1/0 . ::::,:,:,:, r···· i~t6[::ma\:::.. Target ready
I/O···,_}})f 12116':'ffiii[:],(.i(finitiator ready
:::12/16 ma . ' ' ' ' "'" Stop tqe current
·.·.,::::/'/':'.''\:(:\:,..
transaction

LockL

GntL
pClk

' :;:16. nili\f ;\;Ii~~;:. andiddress

·-:-::::;::;:: {{:}::::::·.·

12116 ma

Clear path from PCI to
memory
Acknowledgment that
path for PCI to memory
has been cleared by the
21071-DA chip
(continued on next page)

Digital Confidential 8-3

Table 8-1 (Cont.) DECchlp 21071-DA Pin List
Number

In/Out

epiData<31:0>

1/0

epiBEnErr<3:0>
epiOWSel

1/0

Buffer

eplBus Pins (48 Total)

)\4 ma -:::t::;:tE:tIJ#.~~chip data'tor both
-:
,
:
: : ; : : : ,:,: :·
..,,<fiQ:-M4.:::~J1d 1/0 operations
···::::::::::::::::::=
·:<i m~::

··;~1D.i~i\§y.te enable

4 ~~::::::::;::::::ji·:[\.jjjjljij.i::~·)[j::i£~~~:~:~i:t:i~rd

···::\{fi£irnransferred on the
.,iptbata bus
epiLineSel<l:O>

epiSelDMA

Selects which cache line
be transferred on
the epiData bus
Selects which buffer
(1/0 or DMA) will
be transferred on the
epiData bus

epiFromlOB

epiEnable<3:0>

4ma

8-4 Digital Confidential

Selects the next epiData
transfer from the 21071DA chip to the 21071-BA
chips
Qualifies epiData control
signals and enables
output drivers
Clears all byte valid bits
in the current line of the
DMA write buffer
(continued on next page)

Table 8-1 (Cont.) DECchlp 21071-DA Pin List
Number

In/Out

intHwO

resetL

clklx2

clk2ref

Buffer

Miscellaneous/Clock
Signals (4 Total)

Test Slgnals(4.Total)

===========··

cf<t:!.:=i[il[:=::i!ft=A. ma

PTestOut

·.·.:-:-:-:-:-:-:-:-:-:-:·

Parametric NAND tree
output

Tristate_!

Tristates all output
/bidirectional pins for
chip and module testing

testMode

'Thst mode select

scanEn

..·.;.·····:::: :\:;::l
.. .

.<~~{j :;: :;:;: :

-:.:-:-:·:·:-:-:·:·.

·-:-:·: -:-:·:-:-:.:·

Scan Enable for chip
testing

Total Slgna~::lif!~E=::=t,-_\=Jf.1 s5J::.[\l\:.i\.[j:
1
::_:=·
_ .
<·:·:·:;:-:-·
TQ.$.(ipf.~$:
::::::=:2os

~~:u_._._n\._.°_: .:; ;._:;Ms~ij~!=!\! \!l ! l \l\ji_:,_=i:_: _: :=: : ~:!\~\.:\_~j: : : =·
"·:·:======

Jlli!~-2 o@•il1ed sySBus Signal Description
....

Digital Confidential 8-5

8.2.1 sysAdr<33:5>

·:·:·'.·'.:::::::::::..·.

Signal Type: 21011-cA Input, CPU output, 2107$.f:P.A?&~a~r~9.tjpnar:::::::::::::-.
Input Sampling Clock Edge:
·.·.·.·.· :·:·:·
···':\{Jftt:t::::.,.
Output Clock Edge: ciklR
ilHiH\
·-::\::ttrtr··
·:::${/$~}::::·:-.

.........

·:::::::=:

sysAdr<33:5> signals contain the cache Jfq~:::ad~ress'.''h(:)~y$,Qw.;,. transactions;
bits <33:32> of sysAdr<33:5> indicates thedid4.m~:~. quad'fag#~I\ft>

sysAdr<33:5> are driven by the CPU on CPU~l:h~tj~t~4.4r.an;:~~ftb~s, and by the
.. :. . . :\~~~~/:=:>
21071 -DA ch1"p on DMA transact1"ons.
.-::::::::::::::::::

;::::..

: : :; .·.·-::::);;}jt ..

......... ··.·-:-:::::-:-:-:.

•

·.·.:·:\(_~I.~.!_:_: .':·-.·.··:·:.···
::::::-

·'.;: : : : : : : : :·

On CPU-initiated transactions, thJ.::!~che lM~::!iaar~~s is expected to be held
on the bus from the commanq:J~Yil~:]:n.:rough t<Ptlj1~)terminate/acknowledge
cycle.
.,::::::::<:::::::::::;::::::::::::·:·':"' ' ':·
......·
-:;::\\'.\:} ::::::;::::::·.·.

•

On DMA transactions, th~/~J.:Aftl-DA':'6fijj:.::~gy.es the address from the

!~~~~~~j;;~:!§t~&}~~=lai~~~~~~==:~.
····

.·:-:-.·.·'.·'.-

a.2.2 cpuCReq<2:ol!~ll\iil!l\l!\\.::::r:=:::::,:.. ·:-: : : : : : :,: .;/:' .?it~.: : :.:_: : : .:.....

Idle
Barrier
Fetch
FetchM
Read block
Write block

LDx_L
STx_C

8-6 Digital Confidential

The transaction types are held on cpuCReq<2:0> until th,.~.J~.µd
transaction. Therefore, there is no need to latch these .~ilm~liV\::::.

Transactions on cpuCReq<2:0> are ignored by the 210~)~bA=::&hlj::.Wb~P. the bus
is granted to 21071-DA chip, that is, from the cycl~:::f.:qJJ9.wing ioGfaP.t/\i.$sertion
to the cycle after cpuHoldAck and ioGrant,.9.easset!Q.n:::~~4h.e end otHie DMA
transaction.
./f:\l}>
····:-::::::::t\/t::\:
:::·:::::::;::::::::=:::::..
··:::::::

::::;::::·:·

8.2.3 cpuCWMask<7:0>

cpuCWMask<7:0> signals are usia\:·itN~QWf:iµ.itiated=-::;ead block and write
block transactions. These sign$.l$J~rry ·dift,~1tipformation on both read and
write block transacti<ms.
·-::):\\j::::.l·:ij:\:i\l:::::=:::::.
.·:::::vw::r=· ..

EZ:~t.i~~1!1ti~!1i:;:~:~~!';;~~f~.c=w
should be writti.n#l:

··:::=<:n::n:rnrt:;::

On CPU read bl~=~uUitji:,·ppp Ltiisfi:.:if~nsactions, the cpuCWMask<7:0>
signals carry additioniiV1#f'qrm~tion ·about the read transaction. cpuCWMask<l:O> caqy4~4.4.r~ss bit$\\::~4@&>, thereby indicating the address of the

::iU:!!~-~Sf¥Qrri!~;.11!: :!r:'::sa~o;r~:d~e;:;::::"!::i::~
space.

:-:-:·=-= =-=·=·

-~}{{. ::::~

::::?\?:

:;::::::::::·.-::::::::;:;:;:···

\\ft

........·.·.··:::·
·.·.·.·.·.·.·.·.·

8.2.4 cpuHqid.Ack.:::]l:lll:::.::======-==·=·:=::'=< .:::i::;:::::t=
::=:=/=~=~={= ·

···::::r~/{:\}f?\\~:r: }:=··

. ::il.il#a1 Typef:=:::2:itfii"~DA Input

~;lllilt~gc~k Edge: clklF
cpuHolqa~k is sampled asserted in conjunction with ioGrant, the 21071-

driveiFsysAdr<33:5> in the following cycle and may send out a valid
command on ioCmd<2:0>.

Digital Confidential 8-7

8.2.5 ioCmd<2:0>

·:-::::;:;:;:;:·:···:·:·.·.

:/!t[![:[\)j: : : :i~.l !l .l l=l:!1l··lktt:=:=:·

Signal Type: 21071-DA Output

5!~~El=;~~Yl~~~clkl~kk

• ;111,1t1:;;h

'<1 1 1[~f;~! t

··:·:::{;::::::::::::::: ::~\:·

.;:::;:::::::::::::::;:::··

The 21071-DA chip asserts ioCmd<2:0> .fif't°eqq~$.:t. an actii.ij:::ljy}tb,e 21071-CA
chip. When the 21071-DA chip owns the sysBu~'~:[!~9Qm.~<2:0;:::=$.tgttals are used
to request a bus transaction. When the CPU oWiik\th~H:>.~, ioCfud<2:0> is used
to request assertion of the cpuCAck an<:l,JrP~~:§Ack ·Sigp!J!=i\}?
:::::;:{ .. .. :;:··-·...·
.·.;. ~:f}:::;:-:··· .·.·.·.·.·-:.:.:-·-:;:·· ·'.·'.·

Table 8-3 loCmd<2:0> Encodings
loCmd<2:0>

CPU Owns sysBus

··:::::::::::::··

·.·.;-:-:-:-:.:-:;:;:· \?:::.

.. :·:::::::::::{:):~~{~}:;:;.

...:::::::::::::::::=:::··:·:·:
:-:-:-:-:.:-:-:-·.·.·.· . ·.·.·.·······

Th4if2i[071·DA Chip Owns sysBus

·.··.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.

· ·==: : =: :t.: .·:.: .:.,:·..,'=,. ..,.·.'.:,':=.:.:,',:_:·,:,•.'.•,'.=:·:,•.:•.:.m:i::=s.
_._J_'.~,·.,·uesh
· ,·
··=::::\Write
cpuDR.4~13JK...NCACH~]![!H:}t=>:...
Write masked
=:=:·-:::::::::::::::::{{"
: : ;: .·.:\:.:·
Read
cpuCAclt'OK. . =::•.=.: =.: =.: .: .=i.': ."'·. ,.·,. . .
cp9§f:}ck HARl.J.~J'DM?R
· :=::/::::=:::'
Read burst
cpµq~'¢.~>SOFT.::EQRQft.\,:-:. _
Read wrapped
cpii(l~W:f:::§!AC_FAIV{'Hfo:?\J>:::.
Read burst wrapped

000
001
010

Idle
ClrLock

·=-.

\}f

.-::::::::::::::::::::::=:;:,:.

cpuD~~:::9K_NcA.Q.amtN(JHK

011
100

·=.

101
110

111

··:·:·:·:-:-:-··:·:::::::·:::::::::::::; ..

.-:-·.-:-:-:-:-· :::=:::::::<··..

8.2.6 ioCACk<1 =~1::.::>n ' ' Hf%-:.:.,f/

Signal·:l•~K!gionjg~ Input

si@lal'''§mm,: 2191=ifcA

In.lit· SaJiP.U.@1\QJ~k Edge: clklF

. JJqJPut Cldel(::fi@g~:· clklR

THe::®.t.Q:7:i:::.cA chip asserts ioCAck<l:O> to acknowledge a D,MA transaction .
.,...·.-=···:.·:.,.}\i9CAcl<=i.=;o>.dn.dicates that the DMA transaction has been completed. If any
/i::/\(.. t::::=:l:i!h~r occdti-!:~::.~µring the transaction, an error response will be sent.
·-:::::;::::::::::::::::~::

.·.·-:·:-:-:;:-:-::::·
··:::::{:::::;:::::::::::::'.·'.·'.:'.·

·-:::;::::::::::=::::;::. :}\::-.
····:::::::·:;:-:-:;:::::::::::·:;:-:-:·

8-8 Digital Confidential

·-·-:-:-:-:<·

Table 8-4 loCAck<1 :0> Encodings

. ::::/{ff/:}:::::·.·.·.

loCAck<1 :0>

Function

00
01
10

Idle
Reserved/unused
DMA 1 kn I dg
.·:·:·:-.
eye e ae ow e e ,:{il\J/
OMA cycle error
··<? ,,:,::.:)':::::-

·:-:·:-::::::::::;.;;.·.·.·

.......

8.2.7 ioDataRdy
·······

··-~\.}\\\:·:;:;.:.

::::;:::::::::=:-:·.
·-:::::::::

Signal Type: 21071-DA Input :·=-:·: :::::::::\~:::::::=:\,,,:;:>>:::::..
··:·tt?
Signal Source: 21071-CA
:':::::::::}'::· · ·-=:'?'/\<:\:\::::-.
Input Sampling Clock Edge;:,:::~ut.:tf
··</}{:}I>:··
Output Clock
clklR ,:::t~·::rn::rn::t::i~::::tt::::...
··:::::::

Edge:

:;i:~si:~~~;: :~~~::._ie:::!t~,~~~:. assumes that read

=nm

If the 21071-DA cltjp.!!l~jHnples···:i:~al.~~*:i;P.:.>
cycle acknowledge without
a prior assertion of ldt>a.:ay,_ it as:Mim~~:::=tb.,at all the data will be available

:~ri'~:a~~7~1!t-~:orf ~~l~~d siib~Uent cycle and does not wait for
··-::::::::::::::::::::::::::::::::::·.·.

Signal Typ~;::::gJQ? l~DA=·:g·µ.~pµt
Signal :g@~~m!f:~9P: 21071~BA

~i:~ll°:.\~#'(l~i1~:ge: clk2F
...

·-:-. .·.·.·.·-:-:::::-

:·:·····

ioLine.~J.<MQ*=)::jj::·d~ve.p{bYtthe 21071-DA chip to the 21071-BA chips. During

DMA :i~itl trmlii#.tl~#~~;.:::!btineSekl:O> indicates the DMA read buffer line
th@ij:::i~:::~ be loaded}/Ourlng DMA write transactions, ioLineSel<l:O> indicates
thi\Pn:::wnte buffer line that has to be written to memory.

:::=:':/:' :::::rn::::i·i:::~·::~i:twµ;~::::£w~l,·~:~Q7l·DA chip does not have the bus, the 21071-DA chip uses
.<<:t:t:?' . . . :.:.:::;:::HotineSel<UO.>Vitcf select the cache line of the 1/0 write buffer that should be
"\16.~ded with CPU 1/0 write data.

··:·:·:·:·:·:·:·:::::::::-:::·::::::=::::::::::::::::::··
::::::::::::::::=:::::::::}:::=::::;
... ::::/{'.}~/{ ..

Digital Confidential 8-9

8.2.9 ioRequest<1 :0>
Signal Type: 21071-DA Output
Signal Destination: 21071-CA
Input Sampling Clock Edge: clklF
Output Clock Edge: clklR
.·:}}~{}}:=

·:·:·:·:·:···:·:·:::;:·:·.·.·.·.

····:'t:t@f:{\t:::::::-

:·::::::::::::::;:::;::::::·

·: : : : : :l ]····:;:;:;::i!i lt.~ .·.·:~-=.·.·~_:,:_·._:.·,=.·.·.

The 21071-DA chip asserts ioRequest<i":oj/'t9/f:~qµest 'riw#it~hiP. of
sysAdr<33:5> to perform a DMA transactionY'fQR~qµ~_f;t<l:O~k!~~:)foknowledged
by the 21071-CA using ioGrant. When a DMA."'tf~~~~P.9n is ·started,
ioRequest<l:O> is returned to idle in th~k¢.Y~l~. aftet'''ioQm\9.}:jf no further
DMA transactions are required.
<+::\.::'.:'.:':':':::':'.. \/:::::,,..
.·' '/\:::> .
The 21071-DA chip uses the DMA req#~~t··~~~da~lti\9.~l}nost DMA read and
write transactions except in the f<~UP:~n~t.~ituatioHsttJ'?°
•

The 21071-DA uses an atom1¢1\lt~'ijh~~tl!l~:\:P~r.form·=~
DMA read prefetch.
.. ......
·.·.·.·.:.:;:··.-.·.·.·.:.:-:·:·······

•

The 21071-DA uses an at9~¢.::,J;~quest.'f6til~¢.ff.hrm a DMA read or write
transaction follcnw\gg a sditti.rlP.itJ1~r map'fgad.

•
•

The 21071-DA ~h~~'''µ;$~~\tJle ;;~:~ii.fl.for~quest in order to flush the DMA
write buffe1.:==:9n mernor)dtlirri~rs. ··:::::::::::+:'.:::::·
The 21011ifil:·#.bbt.\1Se~'''fli!iii\~fij~mpt request to prevent deadlock situations
when an 1/0 ifii~~~~tj~m is staH~aN>n the sysBus and a memory read
targeted to the 2i67:1ffi.~J'.lappell'S on the PCI, or the write ·buffer is full.

loRequest<t~>.f Fuo®bn ,/?\

00
01
10 .· . .;.;.;.;.: :;:;:;:-·

:}:··::·:::·:·]_\·_{>
===-========:,,,,,::;:,.,., .... ·

::=::::::::::,):'''Signal Type: 21071-DA Input
\]j> Signal Source: 21071-CA

····•·•nijjj(l]jij t ~~:~!!°;':n!d~':c~\:~e: clklF

8-10 Digital Confidential

.·.·.··:·:;:-:;:;..

8.3 Detailed PCI Signal Descriptig\g§.!"'.i.i.i[![i:·:,::11r:::::.,.. ..,,,,,,,::::::::::=:::·::::::.
For a detailed description of PCI int~ff~be pin:sl\\~~~Fth~. PCI Local Bus

~f:~:!::n~~i8;;!:c~a~:lfllll:~:tiori~peen
:::::::?:::··

the

21071-DA chip

.::.::\i(~)tf~j~~{):::.
·-:-:·:·:::....:::::;:;::::::;:::::::·.

· ,:[:\:]:l[=JrAD di~~:}::t====·
···::::::::j:::,P:m§1.<a:o;

AD<31:0>
CBE1<3:0>

Par

·=:':PA'R:.I)t::

FrameL

FRAME#

TrdyL

··:-:-:-:-:·:·:-:-:-:·:·:-:··

·-::=::tRDY#

IrdyL
StopL
LockL

... i ;;
.·.;-:-:;:-:-·-·.·.·.

1
i'.)!i\~1 1:;1!1!1;>
. ·.·:·::::::::·:;/}~~~\

<l·:·!li:;:!l!ij.';.0.1 MlmReqt

STOP#
LOCK#
DEVSEL#
REQ#

GNT#
CLK

....:::::::::::::::::::::::::::::
"':':'::::='.=:::

::·:-....;:;:;:;::·:-·

.·.·.·.·.·.-:-:-:·:·:·:··

:::}:==:=:%:Ji[\\:::.
.:'\:(:.:.,]t:.::,~

:i1:[:·[·:1:=:j[j}' ' Signal Type: Input
·=><::::::.:·

Input Sampling Clock Edge: pClkR

. :::t{illil!:[i[i.:Jl~='·Wbi$.. signal is asserted by ISNEISA bridge chips to indicate that an ISA/EISA
·=:=::::u~~~i~ requires guaranteed access time (2.1 µs) to main memory. Refer to

Stfoti"on 9.4.3 for details. This. is a PCI sideband signal.

Digital Confidential 8-11

8.3.0.2 MemAckl

Signal Type: Output
Input Clock Edge: pClkR

8.4.1 epi Data<31 :0>

··:-:·:·:·:·:·:·:::::·

:·:·:···:·:·:-:-:-:·:···:·:·:·:·:·:·:·:·::::::;:-

Signal Type: Bidirectional <®l-07''.NB.~~:::[g!Q.71-DA)

~~:~!!°:i~!~~~il;;~J~; . . , ll!;;

~~~~'f !~;si,:~~H~•t~~:#1111;nhic~~~:n~~ti: ~:!~~l~~~1::.
···-::::::::;::::;:: .·.·.;-:.;-:.:.:-..

8.4.2 epiBEnErr<3:0~::: :UJ?t:..

:,::::+>:.:·::\:·::..:·: :·~: : : : : : ..

Signal Type: aldff~¢tl9.R~l c2J.(}1:t~BA, 21071-DA)
Output Clock Edgcifo.£~~~~;:,,.,.
Input Sa.mP.Jipg::Gl.ockE.qg~:
clk2F
.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·
·.·.·.·.·.·.·.·.
epiBEnErrga(:ps'''i~'''.'titjiid with ;~iData<31:0>. During epiBus transfers to the
21071-BA ¢.b.l.P.:s, t.J#~Hielq:::~~dicates which bytes of the longword on the epiData

e::.Jib:~--~=i$1t:~!r:,:.
i~~:e::~~~ :'J~::~~:t!nbro !:ad
··":=<i:::::/=:·::::::=\t)\?:"
transter~L
:::::::=:·.::::=::;::;:::::

·'.::::::::.·.:·:·:·:-:-·.·.··

Dt.inng\\[ip~Bus transfers from the 21071-BA chip DMA read and 1/0 write
.. :::::=\' ....::J:~u.ff~f.S[~d~P.~Q.EnErr<O> is asserted if the longword being sent on epiData

.:=<t::,::::rn:m ===>==: ..oontairi·s:"=a::.parj~ error or uncorrectable ECC error. epiBEnErr<l> is asserted
·:=<:!~fi~pe long-WdrQJ.J>eing sent on epiData contained a correctable ECC error.

:?)\)}?'..

<1f;

l!~i ; .

{{f}/
::}~{

··:-:·:-:-:·:·::::;

·-:::::·:··.·.·.···
··:-:·:-:-:-:·:·:
·:-:-:-:-:-:·:-:-:-:-:-:·>:·:

·.··

8-12 Digital Confidential

Table 8-7 eplBEnErr Functions
Signal

Transfers to 21071 ·BA

epiBEnErr<O>

epiData<7:0> byte enable

epiBEnErr<l>
epiBEnErr<2>
epiBEnErr<3>

DMAhiad 110'\~tifa~rt~or
:r.4¢.~l~:-.error (thi~llrimt\'Vord)
nM:x:::~ii4ato writ.e c·~rrected

epiData<15:8> byt.e enablcf:)~:\.::
·:::\@}::. ,:::::\)\\)::::::~rror (thl:'i~W,Rp~d)
epiData<23:16> byte enable
:\ft:~~rved
-·-::''Ri~~wed:.
epiData<31:24> byte enable __ _
·=·=·:·:....·...·.·.·.·.·.·.-.·.·.·.·.·.

:::::::::::::::=::: .:-:-:-:-.

·:.::-;.;.·.·.·:·.·.·.·

8.4.3

e~;~~s~!~:P~~~neSekl:O>, epiSe~Jf
::::~i-i;••jmd
ep4\.##li:#.i.NiAU.

epiEnable are

collectively referred to as the
these signals are set up one cycle
prior to each epiData transfer ,t.ofa:,ddre:~s:::l?P.Articular longword within the
21071-BA chip. A detailed d~~~gp~~on of eielfi~gpal follows.
. ··:::::{:~:?'

·::::::· ·:::::::=:::::::::::::::::::=:·.

8.4.3.1 eplOWSel

<:'.\)~{~/' ::::}\:=:·.

:~_:·,:·_: :.:.~_-_:.:_'.~:t.~,~:~:~·,': .,: :.: ·.: ·.·:·.·

··:;:;:::' <l:::._:r_:._:_:.:·_i:.=·_,_

Signal Typ_~_;_ 21071t,P,~']?H:~Put'·-::::::::\::::t:!iiiJ/·
Signal D~J.!imtion: ·21Q::t'lfP.A, 21071-BA
Output Cl~]!:,~4.g:~: clkil/I:l]l.')\>:.
Input Sampl1hg·!§Jp9)f. Edgef]~~2F
epiOWSel is driven by.°lh~:::2·l.Q7l:DA chip to the 21071-BA chips on epiBus
transfers. It i~'.K~~~~~d to'."'si:l.~¢.ti:ithe upper octaword within the current
hexaword c~¢h~4fi1~Hru1d i~ to b~f read or written using the epiData bus.
Table 8-8 l.1$,t.ij: the,Jpp~:9t9 selection.
--::::{{~:\~::.::;:)~{·

:ilt\:· . \{)\}}\::::::::.:_::::::i:-:-:·:·
~-:::-~:-:-:·::,;,;..·:·:··_ _·_. .:,:;: ~' ' ':',;,;,;,: :~~,..___ _ _ Note - - - - - - - - - - - -

./I··•lb~ble<3:0>, epiOWSel, epiLineSel, epiFromIOB, and epiSelDMA
. ,cblJi~t!Y!lY address the contents of the 21071-BA chips. In a

syrich~ini.Y~tfashion, these address signals select data to be transferred

the suQ~f:quent cycle.

Digital Confidential 8-13

Table 8-8 Longword Selection
Longword
Desired

21071·BA
Chip Number

eplOWSel

LWO

LWl
LW2

1
0(2)1
1(3)1

LW6

0
1
0(2) 1

LW7

1(3)1

LW3
LW4
LW5

~Ththen:yi::!.in parenthesis indicates:::t~!!i~107:Cq::.11~ff:::.hen four 21071·BA chips are used
·-·

····:-:-:-:-:·:·:·:···· .·.·.·.·.·.

8.4.3.2 eplllneSel<1 :0>

·-.::::::=::::.
··:::::::::::<·>:·:··
·-:·:::::;:·

·-:;: ·:.:-:-

<>{i!J::-·:<:;:::::::::?fff \·:

epiLineSekl:O:::.,J~:::dr.~v;:atfi&l!l~:~::,gJ07l.-DA chip to the 21071-BA chips on DMA
transfers. This:mfi'itdfs&lects whlclf cache line is sent from the DMA read and
1/0 write b#f.~t:'l~::::t.b.¢.::::2·197:1-DA chip, or from the 21071-DA chip to the DMA
write buffe.r'::~ing,::tle:. eplJQ~ta bus. This signal is ignored on 21071-DA to 1/0
read buffel{~trans.t.ers·.
:.:.:.:.:.:.:.:.:.
..
......·.·.·-:-:-:-:-:-:-:-:-·-·.-.··
.-::\~{:}

8.4.3.3 ep1::~r

'1ljjjjj\i\{iillli~J)j!ilV

-/%:$.ili.:@l Type: 21071-DA Output
.:.:·:-:.:·:.:·:-: -:-:·:-•:.:·.·. ·.·.'"Slli!fikP.estination: 21071-BA
.::::::f\::t::I\:\::\[\::1::\t:t[:::\\\\:: OutPq~[\§J~M~k Edge: clklR
::'?'.:'::'''/·····.,.,,'t\tJ:l@Input ·sampling Clock Edge: clk2F

:;I)~: epiSeIDMA signal is asserted by the 21071-DA chip to indicate to the
i:%1:l071-BA chips that the 21071-DA chip is performing a DMA transfer (to
'\?}\L.}!?>::· ....Yl}ttie DMA write buffer). When epiSelDMA is driven low, the 21071-DA chip is
''\t:J:::'.~'..''.'.. YY??;.performing an 1/0 transfer (to the 1/0 read buffer). epiSelDMA is used to select
··:::::t@\UUtbEhtransfer
as shown in Table 8-9.
······.·.·.·.·.·.; . ·.·.·::::::::::.

· ·.· · ·

"'"}}'.;/\

8-14 Digital Confidential

8.4.3.4 eplFromlOB

8.4.3.5

Table 8-9 21071-BA epiBy~):tn1!~face Function
Function

No action except for possible line
invalidate; epiData tristated.
The DMA read and 1/0 write buffer is
driven onto epiData.
epiData is loaded into the 1/0 read
buffer.
epiData is loaded into the DMA write
buffer.

Digital Confidential 8-15

epiLinelnval is asserted during 21071-DA to 21071-BA tr~~.fers· to :i#i!~~~~f}:t
that the cache line being loaded should be invalidated~.::AUUPY~::,enabl~$.?f.4iff?

:!:!r!1:, :~ :;i~~:::·is~;~d'.n::!~t~!~e~Ti~!SI~::

21071-DA chip when the first longword of data is .h~il:d~Jnto a ne°W\C.$.the line
from epiData.
··:·::·::~\@iII~1:=::\..
·-:·:·

8.4.4 Miscellaneous Pin Descriptions
··:·::::::::::::::::::::::::;:::::;:···

8.4.4.1 lntHWO
.:://{.:::::::.:::::::::::::::·:._.
The intHwO interrupt pin is an outpu.t}ff.omAtlbe~l:071-Dlt"°chip, and is
connected to one of the six irq<5:0> P.~t!$Fof tlle<I).fiq¢.b.iP 21064 microprocessor

;~~~D~~~PJe~~:~~:~:gueJ~,lti::s!!!:i~t;::!:.hi:~:o

is kept asserted until all such . ~rif&r'° con.dlU.0.:n$.fa:~t~ cleared. intHwO is asserted
and deasserted async_hronou~l~:if!}{.
...:·<th/h .. ·.
.. {)}f:·.

8.4.4.2 resetl
·- : : : : : : : : : : : '·-·
Assertion of res~tL "';:~f~_.:~J}~:~:~nk:rnatfaii~·-.igp state machines in the 21071-DA
chip to their injtia:u.~ed stiti$~{f([}:::-.
<.. ::::::;::;::-·
8.4.4.3 clk1 x2
clklx2 is a clock i~~'fit·:jiwh~QJ.k~up~I'i~~>a clock at twice the frequency of the
DECchip 21064 ~y~Clkdu£~~tm1;lta minimum period of 15 ns, and a 50% duty
cycle.
.·:::,:;:;::::;: ::::>:';::>> :-·
::::::::::::::: ::::::::::::'
8.4.4.4 clk2ref
clk2ref is J.::~~i,paj::::ijjp:ut 'Wb~ch is low when the assertion of clklx2 corresponds
to the:::~~sef:ijijij{qf::sysCJJjQ.jltl. The received signal must be set up to the
asser~!:!'~:of C1k.~!~~j._,'i!!·j:·:_:j!ll1:j:J:·. : \ :\~;~: :·

8.4.5 Te-1·:!:§,gig_als

~~4~§+1t>tt.stNIOd.!::::llt::::::::.

:-;;.;.;.-.::::·.,:::::}\~$ertiolFiiii~~ode places the chip into a mode for chip testing. testMode
°'\:!~~::pply intende(f:to be used during chip testing, and must be tied low during

J:t\}~?

:/.:J\J!JJJJJ\ljJ:Jl lJ; ; : _

:::PPP.rial system operation.
·.·.;t::O/tF/t\::.- :::::rn:JJ.:!JJ~i~tMode has a weak internal pull down and a Schmitt trigger input.
·::::v:::::n< -::·:;:i;>

.;.::::::: ~ j~:::::::::::::::::.:.; i; ~i::::::::.:..

8-16 Digital Confidential

8.4.5.2 scanEnable

Assertion of scanEnable places all internal flops in tl\~ii\:\\~l.Ah~t.~te.
scanEnable is only intended to be used during chip t~~tJ.ng/ligl\\\ffi,µ~t
tied low during normal system operation.
/{\:il;j:il::f
····<t:\l\\\\\\\\l\lI>·
scanEnable has a weak internal pull dowgaµ1d ·a Sbbml~PAr.igger i~~:fii:'
:iil:\:'f?' : : : : ·
.·. ·. <:::::::::iii::::~~!lllto:::::,.

8.4.5.3 trlstate_I

-=·:::::::::::

·.:,::::: .. .,.,.,.,:::::::::::::::::::::::.'"

Assertion of this signal tristates all output artdi:bl~~~~ionaPdrjy~rs. tristate_l
is intended for use only during chip testing and."'Pd.wiJ.M~P~.
· .·
tristate_l has a weak internal pull up ~,~ijll:i:l,Stbrnit;'''tfil~i::::tnput.

',i:=i\0l!.:·,·:i: : : : , , , ,: : : : : : : :[\!·: : : 1·.l!: ~:~:; :;~: : , , , , .

8.4.5.4 pTestout

~q:f!s~;~:~~:~~s!:tlla&~!'l~::11b9e:ei:d~~Tei::~t~
be valid. pTestout is intended .fR#liffe.~fo o"IHY.m'!Bi.. chip test.
··-::::;:::::;:::::;:::::::;:;:;:-·.·-

·-··:;:;:;:;:;:;:;:::;:·:

.-::::::::::::;:;:;:;:::::;:···

a.s DECchip 21011:,~~,. ~-iri<:l.ll~:~~:~eat:=t'.
Section 8.5.1 and se·etio~(:\~~?~~ proVi'(\lflp~f.k~~signments for the DECchip
;~i~7;~~!~~a~}%!~-~-10 d&i~l~~~!::':~::~ciiilf:~f071-BA signal types referred to in
·.- ...:-:-:-:-:-:-:-:-:-:-:;:·

··:::::;:::;:;:::::::;:;:::::·:::::::::..

Signal Type

:<:>' ='>'s~#lid .i:.nput' Jh1y

·.·.·.· .........

0
p

1/0

-:.:-:-:-:-:·:-:;:·:

·· ···

:,:'.'·,:.~ ,=.~: : _: :[·:·:·:·.~.~-·.:,l: ·
.·.· ...·.. ·.·.-.·'.·'.·'.

!_:_~'.i_:.:_.,i'.:;,=.·_·,' !.·!,-:,'.D.1UI.1:~W
:,!n,;s_.;._:;:_·~,_-='.:~m_'·.·.· ' .~·.·' _.'

\[[:j\!llll.1.

...'i=·_;,'.,_,:..

..,,:_.::
...

.. ''.'"_·::::_'i·.::n::i:::al:::'

··:::::::::::::::-::::::::::::::::::::::::::::::···
·.·.:·::::::::::::::::=::::·:····

Ff11111,Ji~:ws the pinout locations.

Digital Confidential 8-17

Figure 8-1 DECchlp 21071-DA Plnout Diagram

=g .,t

.::;::{:~\\:~~~~\~..:·:·. ·.

1i1=~g •• t ..Jg=~=~· g~ 4 -~i =~=~JIJ::~~~tR;lt~·/

iMi I ~nil: i ~i ~~ii~~ ~ii h ~~ i.B ~i ~ li ~l~~~~jl~:~ i~ ~ nh ~'.!/~:1i·
..----...,-..-.rw'W"lrr'W"l,......,.,........_....
....,_,w.;.;,;,·····

oulVSS
oulVDD
lrdyl._I
cpuCWMask<3>
cpuCWMask<4>
cpuCWMaskcS>
cpuCWMask<6>
cpuCWMask<7>
Trdyl._I
DevseL_I
ou1VSS
Slopl_I
LockL_I
oulVDD
PerrL_I
oulVSS
Par
CBE_l<1>
A0c15>
oulVSS
AD<14>
ioLineSel< 1>
ADc13>
ioUneSelcO>
oulVSS
AD<12>
oulVDD
ADc11>
epiEnablecO>
ou1VSS
AOc10>
AD<9>
oulVSS
ADc8>
epiEnable< 1>
CBE_l<O>
oulVSS
ADc7>
epiEnable<2>
AD<6>
epiEnablec3>
ADcS>
oulVSS
ADc4>
outVDD
epiLineSel<O>
epiSelDMA
epilinelnval
epiFrornlOB
AD<3>.

····:-:-:·:-:.:-:·:::::::::'.::::::::::.

155
5
150
10
145
15
140

135

130

125

120

115

110

::~~t
··:-: :·:····

105

inpVSS
inpVOD
ioRequeslcl >
ioRequeslcO>
oulVOD
cpuCReqc2>
cpuCReqcl>
cpuCReqcO>
ioDalaRdy
ioCAck<1>
ioCAckcO>
ioGranl
sysAdr<33>
sysAdrc32>
sysAdrc3b
oulVSS
sysAdrc30>
sysAdrc29>
sysAdrc28>
sysAdr<27>
scan_En
clk2ref
lrislale_I
leslMode
clk1x2
oulVDD
oulVSS
sysAdr<26>
sysAdr<25>
sysAdr<24>
sysAdrc23>
sysAdrc22>
sysAdr<21>
sysAdrc20>
sysAdr<19>
sysAdrc18>
oulVSS
sysAdrc17>
sysAdr<16>
sysAdrc15>
sysAdrc14>
sysAdrc13>
sysAdrc12>
sysAdr<11>
sysAdrc10>
sysAdrc9>
sysAdrc8>
sysAdr<7>
sysAdrc6>
sysAdrcS>
oulVDD
OUIVSS

·.·.. ::;:=::=:'.:'
:=:=::::::::::::::::-:·

.-...;.;.;.;.:::;:::: ;:;:::::::::,.i;·...-_ _.................................................................................................................................................................._ _ _.J
··:... ){\ :::::
.
en Q " :i " A .!\ A A " A ...I\ 0 A A en A A A A I\ A A " A A Q UJ " " I\ " " I\ I\ A en A A I\ A A A A A " A " c Cl) Q f/J
"::="·=·:· .. .. .. - 0 0 'V 3: ~ 'V ·v "3 ~ 'Y ~ ·v c "3 v 0 ~ l 'e 'e 'Y 'e ~ ~::: ~ c 0::? ::! :2 ~ t:: !! !!? ~ (/) - ~~~~.nu:; 0 °';-a 0 c (/)

- ·· :--...-.=:li~oiiii;;;~1;~1~;;;;~~111ll11~11~1JIJ~~lllJJJ~11111
... ....i·a.in .iii inee e
P
PP PP eP ClCl Cl Cl Cl ~Cl Cl 11 "'Cl Cl '"'"Cl ClCl ClCl ClCl Cl
··:::::=)(!{::~t'i tiit t~ t tttt~t-n·g. n:n-g.jj·g. ·g.}'hiHH·H
0

·--

·-:::::::::;:

..::::;:::
:-:-:-:.:-:-:
.-:-:-:-:-:-:·:··

········-:·:·:.··

:::::?8.5.1 ,~[Pft:abetical 21071-DA Assignment List

·.·-:-:-:···;.;.:;.::;:;:;:····

·-:·:::::::::::::;:·'.···

: : : : :· ....._. t>\Jfable 8-11 lists the DECchip 21071-BA·pins in alphabetical order.

8-18 Digital Confidential

~TIO

Table 8-11 Alphabetical Pin Assignment List
Pin Name•

AD<O>
AD<l>
AD<2>
AD<3>
AD<4>
AD<6>
AD<6>
AD<'7>
AD<8>
AD<9>
AD<lO>
AD<ll>
AD<l2>
AD<l3>
AD<l4>
AD<l6>
AD<l6>
AD<l'1>
AD<l8>
AD<l9>
AD<20>
AD<21>
AD<22>
AD<23>
AD<24>
AD<26>

Pin
Number

69
67
64

50
44

42
40
38
34

32
31
28

150
151
178
194
201
4
5
6
7
8

164
10
57

I
I
I
I
I
I
I
I
I
I
I
1/0
1/0

Digital Confidential 8-19

Pin Name

Pin
Number

:=:::!: :
epiBEnErr<3>

:::::::~:

epiData<2>
epiData<3>
epiData<4>

Type

Pin Name

1
:::::;.k~1
: %¥;\il !ll'1l+·
ep~Data<28$.\):ill@::::::~7
1

"':\]JO

: ~eJ:"P,.:.:!°1~D">:a.~.- _·_,·,~-.:,•.·.·:,_:,:·_:_G'_:-,',·,·.·,·=~·.·:,'_·.,·.·_""·.=.-.:
..

..,..

,:.··,··.,,.,,·_,,.,,.,',',tttt..

;w.;:...,~ .,.
,a_:·::,'.,
..

63
66
70

1/0
1/0
1/0

epiData<lO>
epiData<ll>

76
77

1/0 ':':':'::::;:::::: :-::-:,:,: ..........LmeSel 1
IIQ(_./·:-:-:>

epiData<12>
epiData<13>
epiData<14>

78
~0::.:;1·:i_.:_:_._:.:;_:_'.:_:.:'.i_:_·.:_:_,_,:·:,:_:_:_.,:_:_:·'.,:_:_,:
epiSelll!fA
81,,/]{):):>
JI'
...:-:-:·:·::=::::i> .FrameL ·
82 "\}'./ ........ 1/0
:':'::Gntl

J\!l:·f:...
iOo/}//'./:
·-:::::::·······.·

epiEnabl.~9~F _: ;: : .

29
ep~nabl.;~i~Q) :.:. :::::~.

§~~ !l ~ 11111~~,;i'. <E·
<.

=~:!:: .{:....

'l:f~~':\(:'.:::::::,.
86:/:/:/:/:"""

:::::::~:

.:. . •. . . 111;.;

epiData<22>,:: :;::::::,:: :'9:t :_,_:_:_,_:_,:_:_:_.•
epiData<23>:)::
9~:

epiData<24~l
9~\\}/.
epiDat,~>f.:.:.:.......:::/Al.f'.

8-20 Digital Confidential

0
0

~O
I

'". .,.,.,.,.,.,..,.,,,,. inp:Vdd

155
207

:
P
P

i; > E:~:

208
203
146
147

p
0
I
I

•

\;{:m'.;:P• ·•~:V;:·

. .:d:d

uv.

1/0

J/Q't?

_:_:,,:_,:_::_,:_.r:'

47
200
166

/}:11_:_·_,_::·_·.:_·.:_·_:_:_._:_-_:·:.·:_:_;_:_::_:,

epiData<l 7>
epiData<18>

:;:;/:~:~:~:~:~:::··

::::;1~'!~t<

55
56

·..

1/0
0
0

_)(, 1/0
1/0

<%Ji

_:);:;:::i;;:· yo

inp:Vss
intHWO
ioCAck<O>
ioCAck<l>

~!3

Pin Name

ioCmd<O>
ioCmd<l>
ioCmd<2>
ioDataRdy
ioGrant
ioLineSel<O>
ioLineSel<l>
ioRequest<O>
ioRequest<l>
lrdyL
LockL
MemAckl
MemReql
outVdd
outVdd
outVdd
outVdd
outVdd
outVdd
outVdd
outVdd
outVdd

Pin
Number

160
161
162
148
145

Type

Pin Name

outVss
outVss
ou:tVss

0
0
1

22
153
154

13
159
163
45
183
106 ...

<ti::=··1=.,1.r. .: '.:·:.:·.;.=:·:·;·;=.: :.· .: :.: .::.:.::.:'. ·..·PP
: : .:·: .: ·:· .: : ·.·:"

·-::/\1\\t,l\:i!i!~~:::g)\::..
::::Jtlvss:::>
···=:::=::::~!!?ill:::::::..
o~tvsi.Jf:\J . . .
168??:::::::::::::=:::
.cfutVss

:\i/}\:::/i99

S\::/f/ 180
. ::::::::;...:::::::::::::..-:·. 188

":::\p"
P
P
P

.· ;ii~<i!l~l;lill11:11'········ :

I/O
.t::ii;iii.#tVi~:+:. ·=-=·:-:..
. "=::30·
I/O
=::::::)\,utVti\/ ......... =·=-=-=-:··
89
. . . . .....
""::::::::::=::;:=::::.::: :::::;:;:::.. 177
0
.::.:::..... :(j),)utVss ">::-:-:-:·> .·:-:.:-:··
1 -:::::::{:}: ttti>.uiv
ss
120
....

P
P

:::<;:::!:11:::t::t::.,
·~.:,!i\.!.:i.·'.lji:li!+. .. outV~k:\?:

~~:

141
53
37
16
1
25
20
68
157
33
175
130
205
17
206

P
P
P
p
p

{)?:·

P ·=·::=•:\)::.:::::::::::::: .......outVss
..... :::\9W;Vss

•Jtitvss
-::::::::::::;:;:;:::•:::::::=::::::..

oµtVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
Par
pClk

p
p

p
p
p

p
p
p
I/O
I

.·.·.·.:.:-:·:.::::::::{
.·'.·:::;.~.::/~({:}~~~:\
·.·.·.·.·.·.·.:)}}~::·-·.

Digital Confidential 8-21

Pin Name

PerrL
pTestOut
ReqL
resetL
scanEn
StopL
sysAdr<5>
sysAdr<6>
sysAdr<'7>
sysAdr<8>
sysAdr<9>
sysAdr<lO>
sysAdr<ll>
sysAdr<12>
sysAdr<13>
sysAdr<14>
sysAdr<15>
sysAdr<16>
sAdr 17>

.·.·.·.·.·.·.

...... ::::::::·:·:·····

Pin
Number

15
202
165
204
136
12
107
108
109
110
111
112
113
114
115
116

···":·:·::~{{\.:.··:····-:-

111/?>:>::,
yef\i.L··;:;:;:t:;;,
118:\:::J/': :·==-=·=:·=· :-.·.IIO ·-=··=·:·:-=-=::=:-:-=:=
·:-::::::::::::::: ::::::::::·;:;:::;:·:·
119

:~sAdr:18>

::t!hii.

sysAdr<ls>
sysAdr<19>
sysAdr<20>

'ffaiU

.::::=:::::::::::::: ::·ltO

·. :::::::::::::a!rll>::::::.
.fkf:\/J:>::-.

·::r22)t/\::

IIO .

123··::::::::::::::::: \}/:J/O

sysAdr<21>
124
sysAdr<22>
·: i::t\mf*~><>•:•:..
sysAdr<23> .::::t }{f42<F>> : : :

:J: : 1:1:1: ~· · · ·0.~:·o·.· ·:· · .:

-:-:-:·:·

. :.:.:· ·:....· : ·.·:·'.· ·:· :.:· · .:. ·. ·.·...· ::

Iltft':

.{i[{{}

8-22 Digital Confidential

Pin Name

Type

··:·::::/

::=:::::=::::::::'"·

8.5._2 Numerical DECchip 21071-DA Pin Assignment .L.~J§t,.. .

·'.·:;:;:::::::::::::·'.·'.·'.·'.·'.

Table 8-12 lists the DECchip 21071-DA pins in numert#.ijl\:~#f.9.~rfa:\. .
ijf: : : - . . ·.·.:·: : : : : : : : _I_: :_:~_: :_.:·_:l:_: :_,: _: .~ :_t:. _~.:_.'·.·.·.·.·.·..
-:::: ... =:::::::::::
Table 8-12 DECchlp 21071-DA Numerical Pin As~~gmfit.nt List ·::::::::::::{]fit'.
··:·:·'.·>:·:·:-:-:-:-:-:-:.:-:-:···.

Pin Name•

outVss
outVdd
lrdyL
cpuCWMask<3>
cpuCWMask<4>
cpuCWMask<5>
cpuCWMask<6>
cpuCWMask<7>
TrdyL
DevSelL
outVss

~::~

Pin
Number

1
2
3

P
P

4
5
6
7
8
9

10
H:{\\::..

~;:.,:. ;::::::/

Type

AD<i~f]\} ·:·:·.·.
outVdd
·:·:-::-:-:·: :·:·:··

.·-:-:-:·:·:::::;};\/}2s.

IIO

il'!I;.&:: m:·

)\)\D<lO>: tr ···.·.·. . .

··,;;u!ili; ······

1/0. '\'{?'"

...AJ).<$).f

ud])]i
. .,e~iW~~\;~l>
·p{:i\:ltL.,.,.,.,. :-:·:·. CBE<4b~:/
1/0 ··:::::::::::111.1.:.:··1::::1:.:;:

outVdd

.·:-:-:·:·:·J4

==:;~.
~;-E<l>

>I fil:~ ·i !:H: : : :,._.
: : : : : : : : : : : :,: : : : : . !~:hle<3>
~:Ft l1i~.
::~

AD<l5>
-19
outVss
.::-:··:·:-:::: :::20
AD<14>
···2i
ioLineSel<l}i;}((Y
~iti?.
AD<13>
... ·.·.·.· /ji/

. ::;:::::::,t#E:.Wble<2>

.·.::/){Jj():)\::..

. ':p@/%}:

IIO..
:: 0
:·:·:·:·:-: I/O

!:.=:ir'11~!1\t1~i:11r1~ll!lfr~

2(f :. , :::::·
27

AD<4>
outVdd
epiLineSel<O>
epiSelDMA
epiLinelnval

:,~mIOB

:-:-:-:-:-:

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

IIO
p
IJO

0
p
IJO

IIO
p

IIO
0

IIO
p
IJO

0
1/0
0

IIO
p

IIO
p
0

0
0
0

IIO

Digital Confidential 8-23

Pin Name•

Pin
Number

Type

Pin Name

::!~~

~~•

~:~:~.· p~D: :a'.C.ta~.:·

inpVdd
51
1
<. )\j-]W : '1'.llllll1
inpVss
52
outVss
53
P
e~Data<13~%ffl\::=:=:·. 81
· ===: : 110
outVdd
54
P
:=:'i~Dita<14~1>'\l\\]\j)]\\:\§~\.:..
1/0
epiLineSel<l>
55
~
···:::1~~,~t=::·.. ·==:\F~~·j·j·jjJ,::::tt=== ~~
epiOWSel
56
1/0
epiData<~f%Jl/ .·.· 85 ·.:· ..····
1/0
57
epiBEnErr<O>
epiBEnErr<l>
110
epj:Qata<lS> ·== ==·=-=-= ?=:=t~~
110
58
epiBEnErr<2>
59
110
.:::tl~~"'~.~9> =:::=:=::::t:::n~t:
110
epiBEnErr<3>
60
~~
:::il·J.JJJ:·:!!!~11~t\:\... =====:
~o
epiData<O>
61
epiData<l>
62
110 ::::::::}::/t/:~piDa~dl~l(Jk:> 90
1/0
epiData<2>
63
AD<2>
64
outVdd
65
/ .·=·= ·= ·= ·= ·:= ··}. \.=·.=.· :=.:·:=:·\·:.:l·i·: .: f
. ·.=:'.•=<2·.= :=·:.•·= ·.=:.'.=:6:=·· ..
epiData<3>
66
UQ[)J'
ua--u
94
110
AD<l>
6J{::::=:::=: ···
ll<Y= ···
95
IIO
outVss
6s::::=:::::::: ····· P
···:::.;==?J?\~u>ata<27>
96
IJO
69
.=:=ittllto..
··===tt=\ii~f)ata<28>
97
110
AD<O>
epiData<4>
7Q
.. ==<(=::\::yoi\
epiData<29>
98
I/O
epiData<5>
p: ;:·.=.= .,=.:.: .=: = .': ,'·i:7:'.=:·:·1.:=.·.:'.:=.'.:.:·::.=:.::.::
·=uo.r :-:-:-:::::::::::::::.:::-:-:·:·. ep1·na ta<30>
99
110
::!ri::::~:
·.·~;::=:-··:: .... :::='=tt:~~ .·.· ..·. ·.·.········=· ::!~::'<31>
~~~
~o
epiData<8>
74
=t:J.J:. ··J):pQ\::::.
epiData<9>
-=== \/7:€t =======· · 'tr9%>/='
epiData<lO>
\/if~::=======·
110==: : : :=epiData<ll::•(:!:!J!\!\j!!!!f'= 1·t:=::::::=:::-- ::;:::::: I/O
epiData<12:())} .::::::::::::::::··
==7$': : :=- 'ttt\ 110
.·.--:.:.:-:

~{~{::

·.·.:-:-:-:·:·:::::-:·:-·

·.·. ..

8-24 Digital Confidential

outVss
inpVdd
inpVss
outVss
outVdd

iliv

102

1oa

104
105
106

P
P
P

Pin Name•

Pin
Number

Type

Pin Name

sysAdr<5>
sysAdr<6>
sysAdr<7>
sysAdr<S>

107
108
109
110

1/0
1/0
1/0
IIO

sysAdr<28>
(j[jJ>i38 :::::::·:.:;::::::;:::=:;;:;::=:::::.. 1/0
sysAdr<29>.J\))fi 139 ··::::::r11::1::::l::-.:.l::i{p:·
sy~dr<30>'}}]J]=:t::J40
··::\110
··::\t::::::@:\\::\!:1=f::::::,:..
P

== m

·.·.·.·.·.·.·.·... ····:·:-::::;: .......... .

Ari#:!.., . .

::31;111% <;'! 1;\ ~g

~g
1/0
1/0
1/0
1/0

11
;

iQ~ant ... ·.-.:::,::::;:;:> "'::::-'\145
./i'MJA.<0>
"':)i:/ii~r

sysAdr<12>
sysAdr<13>
sysAdr<14>
sysAdr<15>

114
115
116
117

sysAdr<18>
sysAdr<19>
sysAdr<20>
sysAdr<21>

121
I/Q\:1?(
,:~:UU
122 :.
ioaeqti;,t<O>
12;t:{]\}:::·
1/0:? i:"'_::.:.:.:::_:. :_.:::_:::_}_f.: :=:::JoRequest<l>
124: :<:t:· :::>:::. IIO
:t~Ydd

;;!:: ~:
sysAdr<22>
sysAdr<23>

:~:!:::>

·.·. . : : : : : : ··o

./.

130

\{\P(\::

/:J~Xt'\==::::::.
'\i3if:?:::::=:::- :·:: :=::J'Fflf\:·
I:::::;:::::::·

=: :< ...·.·. . 13_$?/t= -::(_.::[\ I
@W d•• F w
I
::··= I
scanE"!f\fl?::=:- ··· · J?:~~~~b::/·:::::::::::\::;:- I
sy&A.,f;li4,1>
··::\)131:\:j:j!j}(/ 1/0

:\if::·:

...

.·.·.·.·.·-:···:····M

... ... .... ......

129. :-:-::· ..··.·

·: :_:_ :.·:':_::_:.':'·=:·.:·.:='·.

:-:-:147

148

._: :·:_:.:;·:•.· .

:<:1v:
\_·.·:,:\[~}\::-:.
··128.tU<>> : . ~~%.L:i·i:{;:;:i:it+· ;i::!kl
:nt:\110 .·:::;:::::;::::
··:·:·:·:<:::.::,:,~rfir

125

outVss

. .:.:.:. . .

~g <. ;:; ; ~1 1ro·~u·=t':~:.u:c·~.:~.:.:.:~.:::.=.:·:~.·.·:~·'l \:f m :

·UQ::]t]\\::.

sysAdr<26>
outVdd
clklx2
testMode
tristate_l
clk2Ref

/HiHRik~J>.:::.

::::rn:::::J~D~tM:\41II

I
I
I
I

152
153
154
155

156

~~~

0
P
P

ioCmd<O>

159
160

ioCmd<l>

161

ioCmd<2>
MemReql
cpuHoldAck
ReqL
GntL
AD<31>
outVss

162
163
164
165
166
167
168

0
I
I
0

0
1/0
P

.-::::::::::::::::::::::::;:;

:::::;.
.-:.:.:-:-:·: '.·'.·'.·" '.-'.·'.·'.·'.

·'.·'.-:·.

::::::::t:~]:!I!.:.i

·.·.· ·.·.

·-··::::~:~:~~j~~~~~~~~~\:~~r:~~}::

Digital Confidential 8-25

Pin
Number

Pin Name•

169
AD<30>
170
AD<29>
outVdd
171
outVss
172
173
AD<28>
174
AD<27>
outVss
175
176
AD<26>
outVss
177
cpuCWMask<O>
178
179
AD<25>
outVss
180
AD<24>
181
182
CBE<3>
outVdd
183
184 :.
AD<23>
18
AD<22>
186"\'.{/
outVss
AD<21>
.·:..187
outVss
:::;::;::=: iaa
outVdd
""''\\::1'$1).) ::::=:::.
AD<20>
"1'90//) .. :;: -:·.

?H:il[:tt

::~::

~:!

t ,7

··· :1
··n3· ·

OU .Y 88

Pin Name

Type

1/0
1/0

p
p
1/0
1/0

p
1/0

p
I
1/0
p
1/0

.·::·:::

1/0 ::::..-:~;'.~'.::-:·:-:·

~.'~.=:

Licf'tit::ll:t::::::.

·:·::::~:~:~{:(:::;:;:;:::;::::;:
·'.·'.·'.·;·:-::;:;:;:;:;:

··.·
.·.:.····:::.·

1/0

:-::::\p::::. .::.::_:i.:j_::_::.::_:::_:::_::.r

~~k"~%F ~= jll> + ~:t>
-~~;~\:::::

.){::-;.:-:··

··-:-:-:-:-:'.;.;.·
······.·.;.·.·.·

./:\}\\~~~?·.

:(\)iii?

:: : ::::::::

:: : ::: ::: : : : : : : ~::::::::::.:.
·:-:-:-:-:-:-:-: :-:<::::;:;:;:;:::::

·-:-:-:-:-:-: ·:-:-:-··:-:·:::::::::::;.

..... .

··:;:;:/):::··

::::::::+rn::.:.im:::? >::::::
.......
·-·.:::;:;:-:·:

:;:;.;.-.·.

8-26 Digital Confidential

·-:-:::::::::7:··::::=((~\??
:::;:::::::: :-:·:

.• . :.: : : :.: .: .: ,: .: : :.: .:_: :·:}: : .: : :.: }:.: ,.· .:.: .:·.
..tl~

· : : :/ ul![.::::::11:::~6:::::

-: :f) \:~:):

·.· ..... . .:·.·-:-:·: ::::}:·.

./:)~;}:::::.

Flgure s-2 DECchlp 21011-DA Packaging Dimension

·-:::=:::::::::;:.:.:-:-:·:·:·:-:·::·.·

ln(g~~!~ ·l l i l:t'~'.'.;~i~.'.!JW
.-::;:;:::·:;:-:;::::::::::::·.·

:-:·:;}{:(..... :}}}:::::·
··:::::::::::::::: :::;::: ..

"'D

DIM t---r---:.~~-r---"""'I::::::
A

30.50 .. :~Q~tt $~01

1.211

..Jh.: 21.90 ··2amr mo.s.$.: 1.106
?¢.)~«AA.

3o.rt X~Qf J:~ti1

tnt: t7.<~::: :aa.10 1;oo~t ::q9~: \,.
. G . i)';~:t: }~.33 0.009 ·:o:;:o.r~:: /
.5®.)l$c 0.0197 ese:·
QA~t )0.62 0.010 0.024
. K :AM~t:;.·3.85 0.136 0.152
'?'4.J m~mr 0.23 0.005 0.009
:;::M:::: }~;25 0.35 0.010 0.012
'<Rt t:?~~f;J~EF 1.004 REF
s•: :::::2~~K~r:f::. 1.004 REF
H

LJ-03666-TIO

Digital Confidential 8-27

DECchip 21071-DA Arcli~l:~~~'~i\tl,¥erview
·.·.·.·.·...··.·.·.·.·.·.·.·.·.·.·.·

··:::<)fj~~~f~f~~~:~:}:.··

This chapter describes the architecture/9fi'l~i[[g:M>71-DA.i.¢.blii. The 21071DA chip is a bridge between the PCI li~FHU:~9~Q.~.hthe D'ECchip 21064
microprocessor, its Bcache and mem9ey~[!i![lThe 21()1li&:B!\.:::~hip contains all the
control functions of the bridge as .,w~llJ~i.:::~9me datifp~th functions. Other data
path functions reside within the .:~[~c]ti#.Jl.#.il:@!jp.
... .
.·.·.·.··:;:::

The 21071-DA chip can be diW.i."i;\)nto t\~tVm~Jqt:·sections--the sysBus
(processor, memory).,int~rfactf:~4:=:m~t.PCI intefface. The following sections
provide an overvie,;.f[Q.f\lh~. archit~\U.Hihfeatures of the sysBus and PCI
interfaces.
. , , : : : · .:dfk::,,.,..
.. ,,,,,,::::::':::::':::::::::::::::,.,.
.-:::;:;:::·:···

....

·.·.:-:-::~/:~:;:;:}}:=·

Figure 9-1

Digital Confidential 9-1

Figure 9-1 DECchlp 21071-DA Block Diagram

sysAdr c33:5>

epiData <31 :0>

Addn1ss
MUX& Merge
Logic

CS Rs
and

Error logging

·.-:-:.:-:.:.:-:-:·
.-:.:-:-:-:-:-:.:-:-:.:.:-: ·.·.·.·.·.·.·..

:_:·~.·.:_;_::.~:.~:·~.:_:_:.·.~.:-~:·;_~:·~..·:··> ·:·":.: _:··:.: .

:j: : :•: : : :·: ~.:.

f/ : :} t

./f )f?> {: _;:•._
{?}'./::::···

····················· :~Cl_A0:_.•_·:.•'.~.·:.:~.·:.:.·:_.1.: .: _:~_.Cb

··=::::::}::::::::::::::::;::::::::;··

PCl_PAR

PCl_CBE c3:0>

:-:;:.:.:·

LJ-03078-TIO

··· ~~I?t{ -·-:::::\:._.:::::i=i::::::::)=:

9.1

sys.:1:e:li\lilnterfaci>Jt:rchitecture

. iil\l!'i\i;t:~~1rc~~~::~1~::s!1:i::a~:;:~!;~o~~t;~=ti~~.ti~~:::ns,

.. ?:~_:;/>:·

···:<\\~~'::the coiitt~U~d status registers of the 21071-DA chip.
~:~~~~~:~:~::{::·

.:::::::::::}::::::::·

.·:<·. ··.·.··.

::::::::::::-:::;:;:::::::;:::::
·:····

9-2 Digital Confidential

9.1.1 Address Decode

The 21071-DA chip provides logic for translating and .~:lll~~gUJ:w
21064's 34-bit physical address space into 32-bit PCI i4.4fes.s<spg~ij[]~pd vice
versa. The address decode in the 21071-DA chip u~il~iiitJ>e addres:i:::mID}.ping
and translation scheme described in Secti9p 10.1 tO.]i.in~~~te PCI addresses on
CPU-initiated transactions. All systemsJ~$!J:ig ~he ~ito~:ttD».k~PiP are required
to follow this address mapping scheme. ··:;::\:/....:t{i1t:::.;..
· :;: : : : : : : : : '_: _.'.:~_'_,:_ :_:~ -:.:~.:.:·.:·_: _: _.t:·
:_.'_i.:'_::_::__

...:.::::::;::::;:::::::..

9.1.2 Buffering for 110 Write Transactions

·\\~:::~:::lli:jj]jjjj})t::::..

. . ::::::r

The 21071-DA chip supports write-and~rt!ifL.l!:Q. writ~\:'tf:i.b.i.~ctions and

!:!~:~:!: i~ ~:~:~io~~~g;:~P~d!!IMt~S~~! ;::i:~~r;>~ the
21071-BA chip.

· ·: _: _: . '......
..·.............
·::.:_:'_::_:_.:_:\'.·:_;:_::_;:_::_:!_.'.i_:\.'_:.::_:.·..

··::::::\@}~~)~j}'

·.·.··:·:·:-:;:::::;:::;::::::::::::::;.

As soon as an I/O write transactt.~#.}i~fi:'fi.¢.~it~Q. on the. sysBus, the data and
address is loaded in the write
an"<'f:di'iHi$~$action is acknowledged on
the sysBus. Subsequ~nt I/O tti.ni~ions to;:;'th~i:if~io71-DA chip are stalled
until the previous l!Qbvrite trart..~@iinJs completed. The I/O write could be
directed towards tlii¥2101:bDA CSfGfa)i%he. PCI bus.

.bUffer

The 21071-DA.J~).ijp alsoti114,~d~ h~idlW~[[ibuffer to store write data for a
subsequent wd~:rnr~~actioiE{f~HM~tJ/O write buffer is occupied, and another
1/0 write to the ..2l'Ql·lfJ.?A...chip lpp~ij!~::'"on the sysBus, the data of that write is
captured from the sys:aW:J:::·ijpg loadeHHnto the holding buffer. Even though the
data is loaded into the h&lgID.g\]~µffer, the sysBus transaction is stalled until
the 1/0 writeJ~#f.l'~f)i.~:::fr.ee.::Th.~::]jhlding buffer is required so that all the write

write transaction for deadlock

~!i~:n~{il!!ii;l~i;~~g~~~~e~~=·
The de.~criP:lin4),f::the hglmhg buffer and 1/0 write buffer is a conceptual one.

In th~:::i:¢t.uiiUltipl~m~@.:ii.6n there are two data buffers, and they alternate as
wri~~.:~n~ ho1dlfig~l~lfl~rsr
.·:::;:::::::::::::::::::::::::

9.1_.;~-~-:·:-. . ~h.lifel"'nlkf~r 110 Read Data

:/t:i:-:iji::j:::::::::::::i:::::::::~e 2'fo1:1sl8n*ip provides data buffering for one 110 read transaction
:;:· ····::::::::::;:·:·::·:::::;\iHimtjated by(~ij~#JPU. The I/O read buffer resides in the 21071-BA chip, but

1
,~!;
;11i::;~!:e~~:;
i!
;~:~?!t:f
~t
:: !~ ~:~:;r~ i:e:~1~r:n~=~~:.~e
·::=:::::;;/~~;~;~;~;i~~~~~;\;~;)\::::::....·:::/:~di~UO read buffer is loaded with data received from the PCI or the 21071-DA

·<

iiif)j(\! !il;li~~~. d;h:n~~:~ ~::~e~8 ~!:;~cti:.~: ~~::~s~:stoin~:~:~I ;dt~~I

·:::::::\fhitilfaces independent of each other. It is possible that the 1/0 read completes
:-hii\\j.He PCI, but the sysBus interface is busy flushing DMA writes to memory.
(Th1s is done by suspending the 1/0 read transaction using a preempt DMA
Digital Confidential 9-3

:/~~f}~}(~:t:. .·

.:::;:::::::>;:~

. ····:·.·.·...-.·

··:·'.-:·:·:·:··· .·.··.··:·:<::::::::::::<:. ·:·:·

:/?f?/

request to the sysBus arbiter; refer to Section

:}:::::::::::::: :}?f}}

~~~Jlf'.4~i[, :;'.,~;l ' '- f

9.4.2 and
· details.) The I/O read buffer allows the PCI transactio:m:t&itef.tninate''\i$tliii.f
waiting for the read data to be returned to the CPU. Jilt:::r<<{:::t:::rn::::::t::::::::. · :·: : : ;: : : : : : : --.

9.1.4

w£{g~!~: ~k!:~:!~::!:!~~~-i~t\1i~~h:
wrap mode for I/O reads to function correctly...::::::::::::::::::·:trn:::li l:t:::::

··.··:-:··

······

.... ~~::~:~~;:?ue=.

9.2 PCI Interface Architecture

The PCI interface of the 21071-DA chip:::~~.. a ·ffii~::~P!lpJiant PCI host bridge. It
behaves as a master on the PCI oi.:rJJ.flUHnitiated:':ttin$actions, and is a target
on memory space transactions i11j:§~t~~f:jjl.)y::::J?CI mastefs. The architectural
features of the PCI interface a~~
::g~scrlh~Q;:mji:J~b.~
following sections.
..
·.·.·.··.··.·.··.-.-.-::::······-·.
;:;:···.·.·.·-:·:···

;::=;:::::} :-:-.

..... :·:·:·:/:::::=--

9.2.1 DMA Address Trag1.l.atiori'.:: ::'It:{:\:. .·
The PCI interface stiti.jt·r~Jlire~P:id.1:::1~~tt.er/gather mapping from the 32-bit

PCI address to t.he 34~bitfa~b&~i.f;al addf~~$::::~pace. It provides two windows
which can be ~~P~.d to ·.;~~g~Ww:ithin t1Uf PCI address space. Each address
region can be IfiQ)~p~pq~ntly "liHigr~#tm~d to be direct mapped or scatter/gather
mapped.
·::::<Ct?J?:\..
'.·::::;:::;:::::·::::::·:

If the address region::i:~flj~g:):p~pp;d, then the PCI address is directly sent

out on the sy~D:µ$./Uf~jg}ler 'dfqi;fi~ysBus address bits have to be obtained from
the PCI bas,~:.:~9.af.e~i·.·it~s~ers:itf the 21071-DA chip.

If the add!"¢.~$:.:'~egj(>:tj:ff~ ~¢~tter/gather mapped, the PCI address indicates the

address of':iiHP.~g¢.::::t~ble e#.tey, which contains the physical address of that page.

::ii~~!ltill!f:s!::1:S :£~i:~!:i:I~~!i:~~;::~~:

·:· · '"'" . ot'li~~~f/g~ther mapped DMA transactions, the 21071-DA chip implements an
. , <:0 ·,·
:/:\\?:
./:-::·::::l\:::?..

~111;~!?-i: ~~~~s~~ i:i::rg:~~f ~=~:~ ~:. ~::r:r::i::~atter
. <)~:::a.~.me withih?the 21071-DA chip. If there is a miss, then the 21071-DA

/¢WP reads memory (via the sysBus) to obtain the required page table entry.
./!}This is loaded into the TLB; a round-robin replacement scheme is used. The
·.·.:·:::::::::::,:(:\!tt::::it:\:)translation is done by the 21071-DA chip and the transaction is completed on
·:,:::<<::\::\:\lj·\.:1::::\\::~:Uie sysBus.

:.::::::::):'ti..

·.·.,::<>Jr9ifg~tails about the actual mapping scheme, and the page table entry format,
fef'.~f to Chapter 10 and Section 10.1.

9-4 Digital Confidential

····::::f:·:-:·:·
.·:·:-:::::::·:·:-.

-:':t'tlt:::t/::::::..

9.2.2 OMA Write Buffer

<::::::

··:-:::=::::::

r&lll~~!ll·t·QM.f\

.. ······ .. .

... ····

The PCI interface has a write buffer
wrlte data. The DMA
write buffer is made up of four en.t:rii~i:\i~~ch enti1W#9.#truns the cache line
address, 8 longwords of data, th~(§il:::i.nib~~.~ corresponding to each longword,
and a valid bit for the entry. T:)l~:]ijhtriirtij.)i.WdtfCI address is stored in the
DMA write buffer. Address trah$lition is petfP.nijed when the particular entry
is unloaded from the:::DMA WHti:::lifilf.e.r. The addfess and valid bits are stored

:et~~;;~i:i\°~i:'Jl~~~)~~pij~l!t~t~ and byte enables are stored in
.···:·;·.

-:·:·:;::::-:.:

'-'.·.;:;:;::::::::;:·

Data is receiv¢.dll![~h.4Jie Pdi?iijdJ:j$::::transfJh-ed to the 21071-BA chip over
the epiData busYYW$.~tt::the trhlii,~¢.t~<t~tis completed on the PCI, the entry
is marked valid aiid(~~Vi.:vmlable f&Kµfiloading. A subsequent PCI write
transaction to the samEPC.~,Qlj~Ji1.1e will consume a separate write buffer entry.
The 21071-DAJ~biR:9.9~.s ribt:':~ypp9rt merging of write transactions.
DMA read~{i,f~,!·'ifialjif''bt.b~ii.g'~ the writes in the DMA write buffer
depending)PtCthe $.tii!te o.f\tbe dByp<l:O> bits from the DCSR. This improves

:i:i!ii,~il~:£~:1!~~~::5o:::::~i!Ee~1~e

buff.°'~ri.gf writes. ····tt''thiH{ is no match, the read is serviced ahead of the writes.
wi~mnfi~AJByp<l:O> mode indicates partial bypass, read bypass only happens
/(:\: f?tdf the':+mMiIP.Age offset does not match the write page offset; only address
,:::·::::.::··_:,',::!.>>:
_J::::§t~ <12:f6~:::!§ii!)~9mpared. This mode can be used if comparing virtual (PCI)
··::::mi.U.afesses h~'ti{een reads and writes is not desirable or could lead to coherency
::::::::;::::=:::::=:·
/pf:9~lems. In the No_Bypass mode, DMA reads are stalled until all the DMA
-: tl~:-:-: :-:
·-· · rnWf.1tes have been flushed out of the write buffer.
'.=.:.=,:.=.:=.:

. . . }::::::::~::::::::::::::.,<!l-:ijl-\.-·.¥iiere are two situations when read bypassing is disabled independent of the
·=='\[[}f!UU!ffrntwpgrammed value of dByp<l:O>:

''''\'f{_.:~:-~-l:lli!:.1-:·Whe 21071-DA chip does not allow DMA reads to bypass buffered DMA
·-:,:</~rites if any of the buffered writes were locked by a PCI master.

Digital Confidential 9-5

.·.-::::::::::::::::::::::·:·
·.·.·.·.·=·:·::·:·:·:·:·:·:·:::::.··

9.2.3 DMA Read Buffer

~= ~~~~-~t!~~~pc~t~l~o~:w~:~:ll•~:\1e::c~::i!~. c~p.
valid bit is implemented along with e'-~tflorigW,9~i}p;;ita received from the

:::~:c~~::i
~e :::~~~~~~~--~.~~~~'1!~
:i:io!::db~B:e
PCI interface.
::\::::;:::::-- ·'.'.··::::\:.\?<::\::
0

n~t::·f:il.ve ~<:~~li.~i:

The DMA read buffer.. does
to be stored, because the
contents of the buffei%are invaUdated\at. the end of the current PCI read
transaction. There ·1~::::;t~1?:¢.it@Y
stlfiij:::a~t~=jp._
the DMA read buffer.
.·.·.·.·:::::::·.·.·...·.·.·.
·-:·:-:;::::::::::::::::::::::::::;::·

9.2.4 PCI Burst Legltti:Jmd ·:Pr@titetJJng·:::::·:·:::··

:~~~~::1-.r;;.~!~l\t :::!:;.~;~~ 1;J;::~:a::~a~!n
starts on an even cach~<li#.~:::lmµndary with PCI Address<5> =0 and PCI
Address<4:2> aAM:~:JqJl biiH~t.:::Ar:);6 longwords is supported. The transaction
will be tertl):jq~ted#l.~}ijg a PdtGiisconnect after the sixteenth longword
has been r.m.i.tV:ed. /:Ju{:fillJ'.¢.her cases, the actual burst will be less than 16
longwords/'i°flb~s~)¢.~ses @jili:~escribed here:
:;::;:::::;::{:{;::--:::::::::::::::::·
·····.·.··.·

•

Wb~m. ~{:ljijf.@ii)rr4~~{Pth:er than linear incrementing is specified by

:/~·~:s:~:::~Tht=:=:~-~iction length is kept to one transfer. Refer to

;@l~~ i!i;JJJi i: !rl~•~i;.n:~:o1:i~:S : :se;::e ~~~:~!~~:::ii:~:7isb:~=~~l

.·:-<:::::::::··-·.·.·.·.·.··:··-·.·.··::::'\\l\tttwrite. ··::'<H:t:IF~t
::::-:: .'.'::::::::::;:>,
····:·:·:··

.Jei\rn\When the t~ansaction starts on an odd cache line boundary, PCI address
(\!illI>. <5> = 1. The burst length is this case is ~ 8 longwords.

:·:·:-:·::::.: .){:}~:f~(·

·.· ·.·.:-:-:· ::::::-:-::::\/@(• If there is only one cache line entry available in the DMA write buffer,
::::'\:lt:::::::::=::t:t::,.__ the burst is terminated after ~ 8 longwords of data have been transferred,
·-::::::~{\jtJlfa~yen if the transfer started on an even cache line boundary. This is because
····:::\f}!ifter that cache line has been loaded into the write buffer, the buffer is full.

9-6 Digital Confidential

_.J:{::::::,:!!:l-l:l:::::-::iu/:::::.
:)~fU~~~~~~?==·

On DMA

read transactions, a

mWmum

-::::::::::::=::::::: · :::::::::::::....

burst length of ~J9j!:J1!ll~:::,:::I:lf :i;t
1

~~:x=~:i~:!~~~1:~!: ~~!::b~: :q~:s:~illll,ti:Jll1

burst length of 16 longwords is supported if DMA P!~~fohing.''iifff[i.p~QJ.~9
in the 21071-DA chip, or a PCI read multiple com.mM.d::,.was use<f'hyfftlie
requesting device. The following describ~~!ifth.~ varfou~f:f¢.~$.~:J>f DMA read burst

~=:::s~=~ ~r~::~~=et::s~::!'•~liJm;i~:;,!\1~~d by the

master. The burst length is kept to l longwof&.lf.$.f~r:.to Se.ction 9.2.5. No
prefetching is performed.
__., ,:,: ;: : , , ,.
·.. , , , , , , ,: .: : .: :.:.:. . ·.

•

~~!!i~h:il.lll#.~mwg i:>df:''-~ommand

When prefetching is not enabled
is not a
read multiple, and the PCI trans~~t#>n starli¥!mtltJ>CI address<4:2> = 0,

e:n~!'.:ite:!a::edi;~~~~:~--~~:~:!r:.

•

longwords have been

When prefetching is not ~~lid and::::fH~!jil¢9.Jlling PCI command is not
a read multiple, . 3P._d the 'P.QUtVm:~action··:·s=qHs with a non-zero value on
PCI address<4:~M:!th~;._PCI ·mt~ff~~Jiisconnects the transaction after~ 7
longwords have·H~'~n.dtt@m;.ferreWii.ijt:tb~)?CI. No prefetching is performed.
When pre(~~@!iqg is·'-'!ai~~it:l~:)?:~t.a r:'i!"aliifuultiple command is specified on

~~I ~~1=~•11;:.:;:~\·\!;~c:ndi:::~::~:et~~~:~~~!

16 longwords have':'~fi::O:~~@sferred on the PCI. The odd cache line is
prefetched...,. :::::::: :.:.: _... __ ':\{}i-]::_i.-:·:. @\,,.

When Pt~f.'-t~liiijg,jj~>enabl~tl?br a read multiple command is specified on
the PC~~i':[gnd tb!::::thu~J~4.ction starts on an even cache line boundary with
a non-zi.r9Lv~l#.eVim 1¢1: address<4:2>, the PCI interface Disconnects the
tr~_~ac:t!P:!!:))~~r ~ _.;l.§::j}ongwords have been transferred on the PCI. The
oqq:::?.ch~:::~pij~f:::p_:
_ _ ·'tched.
-:-:::;.·.·.·=
::::;:::;:;:;:;:
• . J)ib.i~ prefetchtrlg':Is enabled or a read multiple command is specified on
,:;: ':-:-:-.-. ·-·-:::<t)i~J:PC:l., and the transaction starts on an odd cache line boundary, the
.: : : : :;: : : :::I::tit:::::::. PlJI[i!\!ntitf.~~e disconnects the transaction after ~ 8 longwords have been
·.·· _ :::::;:::::tt}\]{\transf&Ti~U9.~ the PCI. No prefetching is performed.
•

:r_;::_::e_::_:.:_::::11_,:
__-_: ..

.<·:::~;···:::::\.·.·.

·······.·.·.·.·.-...

-.·.:;::::;::::::::::··

·::@n:::\CPU-initiated read transactions, when the 21071-DA chip is a master on
ft.b.~:::·PCI, a maximum burst length of 2 is supported.
)J_--i'O-n CPU-initiated write transactions, when the 21071-DA chip is a master on
·•::::::::\:\}::: f%4pe PCI, a maximum burst length of 2 is supported in sparse memory and 1/0
··:'?/{(~p~~:~' and a maximum burst length of 8 is supported in dense memory space.
··=:::;:::;::-:-:-

{)?

Digital Confidential 9-7

9.2.5 PCI Burst Order

Bits <1:0> of the PCI address are used to specify the Q.qti~.l~fd~ti.ng
7

:e~~~:r1 ~~~~;si:::~ ~':::!?:c~!:~fl~ o~,~-~:e~ ~~
1
~n
:~~:a:::i::s::;::~l-DA
suPl¥fskµ:::
11~o!llY::en
a
linear incrementing burst order is specified.
a burst
:fff:\tff~::JJJ.aster''';p~S,ifies

order other than that (AD<l:O> is non-zero), t1Mif::the\:PCI ini°efface disconnects
the transaction after one data transfer.
.. '?::::::::::=:::-'
/f" ' ' :·
··:··::{f( ;j}?~:{::\::.
·.·.· :::::::;:::;:-·

9.2.6 PCI Parity Support

All PCI devices are required to gen~r~f.#.l':'parit;Ai~f:§ij~f:4J)<31:0> (data and
address lines) and C/BE#<3:0> (c,9mml.P.Q4.>yte enib1~$). The 21071-DA chip
complies with this specification. ::::,::::rnu:u:·::\)\}'('·:
·

::;!:~::::i:e:~:ni:ic:a~~:~!!fll~~~i~!~a;;.~s~~ 1/0 reads,

When it is a target0:::6~,\\·fh:!4lQI, ·i~}~fil~ja>.P.rity during the address phase, and
during data ph~§:~s on rii~mi.!Y::::w.rite lf~i~etions.

9.2.7 Pel

Exclusl·v·eJ: :. _i=.~.;_:,:_,:_";,:_·c'.'.':_' .:_:.c:,'.'.: _,:.e·

. . ". .. s·.·
..s.

""'.:·':,'::;-:::r:::::-::>:::::...........

···::;::::\:::::::::::;::::::::·:·..·

··:-:,:,:;

The 21071-DA chi~''::§li.pp~t~:..the.':PdJ.::·E~clusive Access protocol using the
LockL signal. A locked'''bf~~~¢t.jon to main memory on the PCI causes the PCI
interface to lo.~~:J:).P:t.J~U noihe~~l~ive main memory accesses initiated by PCI
masters. Tl}~~:[:~~:jfijq~::J)y· disconne.cting the PCI transaction without completing
any data tr~~ers.~/lifitil/tbe Lock is cleared on the PCI, only the PCI master
that lockeCJi!\:m~n.Jp~fu.orj\:\~~:: allowed to complete transactions to main memory.
Refer t9 the,~::eat:ZPbal B.:W§fSpecification for details.
On thi\::~sBtt$!:!@1~:~~4ht:JiRCI lock causes the system lock flag to be cleared
by .µ~jijg(the ioClf#.9.~\fohinmand encoding on the ioCrnd signals. The system
Io*-i:\flig!J.s held cleared until all locked DMA reads and locked DMA writes to
-:-::· : ,.:::.,.;;.,.,memijflflg~y~ been completed on the sysBus, and the Lock is cleared on the

.. - .. · ·..... J.?CI.

.·:{::::.

.::::::::::::=:

< !~1;;ih

:· ·.·.·.·:·.·.:·::::::::::::· :·.

..,.:\::::::r:;::::::;:::· -:':::...

··::::::::~:i?t~~~~::f:;:;:;:: . .·

"'\~::\\' master'.'Bij/the PCI, the 21071-DA chip does not initiate locked

l'sactions. .

9-8 Digital Confidential

92
. .S P;!.:u: =~!:~e

requesting bus mastership, it is

PilJli!~!l

system arbiter grant default bus ownership to the 21q7~:iliD:A'''eh.~IEIYL@.~serting
its GntL signal. This will reduce the latency for Cl.!YtitP.tiated trilj~f'.~f$· to the
PCI when the bus is idle. Granting the PQJ to a di.Vi~iiAvben no re4ii~sts are
pending is referred to as parking in ·the::RGfLqcal iifl8J$.j).'g'qjfj,cation. If the

~~~~1~::~3 ~~~~~~~<~~>~::;

:! 1t1;eSffii~i)~;~P1·

it will

The 21071"'DA chip also supports PCI bu~:·::P.~~king'ltt\ii.:$~set. If the Gntl
signal is asserted by the PCI arbiter (~~qlJ~(\i~lw.ays tHi.~t~d by the 21071DA chip during reset), the 21071-DA ¢.gJphvifflgfiv~. AD<3l:O>, CBE<3:0>#
and (one clock cycle later) PAR. Whel'.)}Qntl is·':'dijl.$.~tk:~' the 21071-DA chip

9.2.9

p;.s:::;;::::;s.

rn!!il~l!l'jllli~l!i>. .

'.'h

;:!;:~~~7;~~a:!~~,~~:ie~tlT~:i~=:~!s;'c~b~=~~a~ ~~any
disconnects or retri~s~}'\Vh~n. it iniflati$!:i~t:CPU transaction on the PCI, the
21071-DA chip .~Qunts th~:)jµ)ng~r ofliii:i~~~::It gets retried or disconnected,
and if the nu.#:~ceedit2r1\i\j\l:f@~gs art'~rror to the CPU and aborts the
transaction. ··:.:::\:):}:(. : : .;.;.,
":::\:/ \/::: ··: ..
·.·.::\{

.. ...

···::::::=:'.~'.:'.;:;::'.::;::'.:::-.···

9.2.10 PCI Master Timeollt:[.[I: : : : : :.:

The PCI protq99}}$p~jfie~::::~[=:·m~b,;:.tnism to limit the duration of a master's
burst sequeµ:tjg~/}Xh:~m.m~chanism)requires a PCI master to implement a latency
timer that::#9.P.hts tl#'i)Aut.P.Per of cycles since the assertion of FRAME#. If
the master::·l@~n~:i%~iinef:i::J~s expired and the master's grant has been taken
away, J!ie tii~i~~f::~~::·reqlJ.iri.a to surrender the bus. This mechanism is intended

!:Silt1'11111~1!~~!"i8o:7a~"!:: ~ee;~~~~~l~~~~!~~!:i:
p•~mW,able master latency timer.
····:::·:·:·::::::::::;::::::::::::::::..·.

:~l~"~\:::[\\::\A~dreQ~:\j§t1pping in Configuration Cycles

·:<·:;:l\]:>':::::::;:;:·::\,:~~lih~:: 2107'i::ni.l·¢.}np does not have dedicated IDSEL# pins for use in PCI

"' }:Y>

,'.[g9,g(iguration cycles. Because AD<31:11> are not used during configuration
.:':}#y¢les, they are connected to the IDSEL# pins of the various PCI devices.
··::::::::::::/ ...... . . ::::···· :]{Jfhese devices can then uniquely be selected during configuration cycles by
. . . . :.:.:. . ::::.}l:)1sing addresses which assert only one of AD<31:11> at a time. By doing this
"·:::::::rurn:::']]kt~dded load is presented to those address lines that are connected to the
··:::::::::::[:~p§~L# pins of PCI devices. This load can be reduced by resistively coupling

•.:::::!:[{:)~\::(;.

Digital Confidential 9-9

.·.· ~:~=@r:·:··· ....

:·:<·=-=·

:=:t:t?

.;:;:=: .:=:·: ;:=·=: : : : : : : ;: .:-: :·

.:·/:i(;:;:;:;:::ii=it::=:·..

··=-··::;:;:::i(<t:;j/. .

the line to the pin; but in that case, the time for the sign11,LW :!!!:alL~illf;,r
the IDSEL# pin is increased.

~:a~:~=~ t~eP;~~7;~~1~~~;t~e~~:d~~~r~:~i:e~;~•'~;;11r.ti~:~~~s
and write transactions. For these transactions, th.~:f:jgjQJ,J-DA chipAiint'"d.rive

~~~=Sr~; !~~~O~~?'J!:c:~n;el)~~1~§i!llli;:er rot the

The 21071-DA chip does not perform address:''dti::ji:~:J~.teppiNg:[:jfi::==any other
<<:-:-:-: ;::::::::::::::::::::::.•
case.

9.3.1

9.3.1.1

When the CPya~}m~ster ··itm~lj~f::$y~J.3us, lhe sysBus interface monitors the
commands and:<aaqm$.$~s sent?6q1f:'j;)y\the CPU. If the addresses are within
the 21071-DA chip=liddreS.~::range>'ii1.dH~he command is valid, the 21071-DA
chip responds to the ttifi.~~~~j9p~ The'"21071-DA chip does not acknowledge the
CPU directly..A~mrw.ledgmijp~\4~re communicated to the CPU through the
21071-CA cltjp~·:-~qq\ig~~ is coriiJ#unicated through the 21071-BA chips.
The followjjj~[-[i~--t~~-=-lj~f C?:f::'kansactions supported by the 21071-DA chip sysBus
interface. '{{)}. .: :=: .:. .·.·.
"'='==: : =:=: :

• ~;Plii:lli1;f'~kn

Space

. J%1.J.i!~(~1071-DA ..chii> responds to the transaction by notifying the 21071··:===:=:e.w.;::ibbt.when data is ready in the 1/0 read data buffer. The 21071-DA
·=i: : : : : : = ;:~mt:::::\t\L===·· chi}i:\m\ijy}P.P..oose to preempt this transaction if a DMA read transaction
·=: : : : : : =: : : =· · ===::::::q:::i:::J:il\is in pfii.!!~$-- on the PCI, and needs to get on to the sysBus (deadlock
_.,.,.=: = ·='.:'.:\(>
·:::J[l[]:l:]lresolutiori)}f·
,,{=\\\.:~:'\\·
:::::::::·::!=:=·:.]\:\}The 21071-DA chip supports longword or quadword reads in PCI space.
:=:=====·=·.·.

·-:::::::::: ..

... ·.··.

<·:-:·:·:·:···
.:::·::::::: ..
.

....

=:===:::=:::::\_:\::=::::)\,~ Read Block to Local (CSR) Space
:-::::/ff ;}~; ·'.·:·:-:-:-:-.

'=</{\\.\'.i\]'~IT:his is treated similarly to the read block to remote space. The only
·=-=-:;::difference is in the conditions for preemption. This transaction is
9-10 Digital Confidential

•

Write Block to Remote or Local Space:
The 21071-DA chip acknowledges the tr.ansa~tiinHvb~m. all previous 1/0
writes have been completed on the PCJ.f:f:lhi:~ traiig'i#.t##f is preempted only
if it is stalled on the sysBus, and qy~tiiil\t\~P.M~ an "1/tf write transaction
which cannot be completed until iift)MA tfii#.m.~tjpp on the PCI can get
onto the sysBus (deadlock res9l:#.ti9.#.)~:-.
.. ··::::\{ii:i::;.:·
The 21071-DA chip supports.:t&#,\j{}4ijl{9y,4 write·~==·in CSR space, and Ut> to
quadword writes in sparse/RQl\''spac.e'/aq~fajp:J;o 8 longword writes in dense
PCI memory spa.~:~,~=(\l):jt.·ii·ll!1i.l:.!::rn1it\,.:..
·-==tt'\::t::···
:.=.~.~·.~:j:~:~:~:~:~:~:~:~.·.~,: ~: ::=::.

............................... .

.=.=

Spif~,j\\\:i\\\)t:tt,:,..
• LDX_L to 1/0
·{\:=:::.:..

··=·=::~::::::?:::;::·:·:-·· :-:-:·.::..

:::\{\)\:<:':i\::··.:-:-:-:-::::::;::::-:

·.·.·.·.·:'.:'.:::~:::~:::···:::;:;::.:.·-.:-··

This is tre~~~:=J.p~,~-. lik~·'=':tfl.4.\~\~!9~k t~· 1/0 space.
·-:-:-:-::;::<-:::::::::-:-:-:
·-:.:.:.:-:-:-:-:-:-:··· :-::;:::-:-

• STx_C to 1/0 Sp~ci~ ' .·:·,:.: =·.\: :

::::::-:-:-:-:-:-·.·.·.·.·.

·-:-:\\{~iii::::

···.·· :::::::;:::::;:;.
. ··::'.\{{{{:~::::::;:::::;.

This is ~f:~j.~4.:.j#.~~::Jike ;=:=:Wfit~ block to 1/0 space.
-:-:;:···:-·.·.···

.::::::::::::::::;:::;:··

·:·:-:·:·:-:-:-:-·

,/j:f:II?Fetch, FetchM to 21071-DA Space

·-:-:-:.:.:-:·:·::}:

·:::::-:::::::::::::::::::::::::\\::

:-:-·.·.:.-::·:·:-·
··:::·······-·.·

· · ···=·=-=·:·
The 21071-DA chip does not do anything special on a fetch, fetchM
.·. \=;::::)?i' .'.:.,,'.'.·,. \.,. transaction to its address space. It sends an acknowledgment to the
·' =:::<mU\l·.: ::=Itj\~:f:071-CA chip as soon as it sees the command on the bus.

=-============:':' :'

Digital Confidential 9-11

><<>.

..J::i::i::r--·:::::,:::::·:·: .->,<:::::=::::

~~:::~:~~!!=::e~o:rn~:1~s~~~o~,,-~~il11i~~ . .

9.3.1.2

DMA transactions on the sysBus always start witlti~-il:l~bitrat~~a\iili~~tj\vhere
the 21071-DA chip asserts one of the thre_~;rp9ssibnPtiii#.i$.~,.codes to Ufo arbiter.

~~:;~~~~e~~l~~~c;::~~~~laifl!ifi;ii~-:~~~s
prior to the start of a DMA write or as data is refiimi.(t:P.n.DMA reads.

The sysBus interface uses the atomic rfflt#i.~~j:,iwb:~n·,.i'itH~~i[\~, prefetch read
data or when it needs to perform a sc~tt~flgitlj~#J99Jtup.··=1t does at most two
memory read transactions during sq~b}a· request%)lJtli\P.~'-s the preempt request,

:,h: !!ci~~s~oi!~~~~!~~JSlltl'~j~::!h!~:.!~.~~:~~~~=ards
~ee s;!~:~g is lij~jllf DMA~~1i~~s peif6hned the 21071-DA chip

times it uses the normal DM4,:ff~"pest....,,,:::::·:::::i.::,;·:::::.,i:··!:)f:,

•

.,.,,::':'

>Ill::-:::.

·:-:::::::_:_·_:_:_·:,_.-_:_:_·_,_·_·_-_·:·_:

::_-_:,:,:,_,:_:_:,·:_'>

··-::::\\'/: }:}':>::.
Pel DMA R.e. .:.a.d
On a PCI :QBnr~~d t;:~ri!~~¢tj9~1.:,:,._210~fr-DA chip could use one of four

sysBus DMA:fi~~j·_~9ffi~an&b{::.:·::!'.,.)f·
DMA read

...

-···

Tlt~rw.~ip@i4H1~~-m~r::'}~ used to indicate whether the lower octaword of

9~ta\:fi-oni.'lq~[:[~\~Jii.t]ihe is requested or the upper octaword ·is requested.
t:Wbi.favrapped.""'coffiftiand is used when the upper octaword is requested.

i1'i!!\\jj[il)li•b !lk~':!:::! li~:i;!o~~: 1t:i:~':ie~~r;. ~!h:!!ec!':!1:/

-,·:,'_j_._::_:_·_~,_'j.:·::'·:,·~,_j_._::'.j_:j:i.>''''''':'::?::f:.:::~::i::::)use~ wii'-g:d:il~pt:e 2tlh07tl-DAbchip ifis tlikheldy ~o prefehtch .data from memory.d. The
\(//)naximunf'. ·a a

_-;.:-:.:-:-·.:

a can e pre e c e is a cac e 1me; a memory rea on

;:/~~~n~~Ul~~H~he PCI can be at most 16 longwords (Section 9.2.4). The 21071-DA chip

::=::t:tt :ll}::::.. .,JO:::ilt?'. uses DMA read burst on the first cache line read indicating that it is going
. <\\f ···· ·::::::JL:'.:'/·.·- to follow it up with another read. The second read uses the DMA read
· .: : : : : : )}{/}\~~\/:::.... command because that cache line is the end of the burst.
.....

·.·.:-:-:-:-:·:·:-:.:;:;:::::::·.·.

····.·.·.·...::::::???:::::~::

• <\scatter/Gather Read

9-12 Digital Confidential

•

9.3.2 PCI Transactions
The 21071-DA chip supports the f9M91~~:::~ransacli6!:~)()n the PCI.
··:::::..:·:-:·:····........
..
•

•
•

Interrupt acknowledge: PC,~ mf.~t~fJt:::::::\l!lt:
·::::::::::::::::;::::
::::::}::::::::::::::·
Special cycle: PC,!. . masterj\::·,·\.[.[.:\\,::[·:·:1:,::-.
1/0 read: PCI ttjaer. : :· ·-=:;: : \': ;: : : ~:; .[.[·: : :!~!\,: , :-.
1/0 write: PCI ma~t,Ji!I:l\!\}t::::,.:-.

::::: :

..:: : ::::::~:'.:::::::: ......

-=·'=':>: : : :/: : :=· ··
•
• Memory r ..~:~:::)j\~:':~Jav~''''~-h~;:'·tb:~t,,t.ran~~ction is initiated by another PCI

device acce$f;'frlg!:i~Y$t~µi mefuarY.J.\l~i:=·master when the CPU is accessing an
address in PCI m~wBl::,~g~ce ....,,<er·

•

re:::~~~:;:~•t~ ~:::!~ ~~~:::~~~~sa~:::s:~!?i!n
0

addres~]n:/PClJni#ion\
space.
···.·.·.·.·.·.·.·
.-:·:·:-;-·.·.·.-.·
. ··::::::

•
•

Configqif:\~,?.W'F~d: Im~: master.
Cq~µgufi.t~~iji)l.writ.~~IFCI master.

• ./:~f:l~ry ~~tillila:::lH~~lidate: PCI slave; treated just like a memory write.

·••••ij!

!l~Ji'iliilll!,;·l:~!i•f~~~!;: ~~~;;~;~~~;;;;e:~:i:a~
·.·.·.·.·.·.;.·.·.·.·.·

done

···:::::··

.t't::j:.;::.:)\bual address cycles: Ignored; only the lower 32-bits of the address are
=?'/\,:,·'used.

:.:.:.:-:-:-:-:·:·:-:·

:: ······.·.·.·.···:·.

:·::\:}).
::::::::::::;:::·

··:·:::::::::::::::::::::::·:-:-·

Digital Confidential 9-13

9.4 Miscellaneous Architectural Issues
9.4.1

.
A remote PCd
I evice

··:·:;.·:··-·.·.·.·,·
.-: : : : ;:;:;:;:;:;: ·:
·--: : : :;:\+\=·=·=·=·===·
·-=-=-=:=: )@?
The 21071-DA chip maintains data coherency a~at.¢.b.t9.Jtization between
these two agents using the following m=~BiB~~m.~: ··-===:=::<}:::·~:;:=:·:-=;==>

•

The 21071-DA chip preserves stri~#.::~f.at'fu1g!i~f\p=:fy1A -~tes initiated on the
PCI.
·.: =.
· · · ·=·=·=·./·::\::==·=·=·
..

·.·.·.··:-:·:····

. ~a1: r:! ;::~:~:n:~411!11~;;~!~::~sa!!~e:n~:~~e
same address.

•

··-=:/:\··:.

.:::::::::::::·:::::::;:::;:;:;::;..

·-.·.··::·:·:::···::'
t<t·=
·.·:.:-:·:·:·::::::;::;:

110 transfers ·fr~i!ithe CPif'i(j.::!tfiij\pQI or ~=::=21071-DA CSRs are performed
in order. This poliey_.:$.J.;@:rantees%\~(~b~r~nt view of PCI 1/0 space from the
CPU viewpo_ ._j_.=. .P._t.
. :.:.:.:-·-:·:·:·:-::::::;:;:::::::;::·:-:::·:·.
: ... ·: :;: : : =·=·=·
... =:=: : : :=: : : :;: : :-.

• :!'!'k:~;~::;!tl'~~~h!~\la~: ~!ac~u~~1:~s!r:~ii°cit ordering
commands are aHse~.M~n=:the Pdf:/the software MB instruction is used to
order CPU and DMA?ii¢¢esises.

•

The 210=71J.8pl!J'.#,}ijip:;::a1s~:=:Ad~h:~~ the 110 write buffer to the PCI before
acknowJ~ggfng_:=i~Hwh-ri~r command. This preserves the order between CPU

• ~lJ~IRIGiltm;~s;::::el:ck flag on exclusive reads and
PCI

9.4.2 Deadlock. Resolution

. ·':l~f!l. 1:1.~;~.~~·,~~d!~~:~si:!:fe;:e~ea;s~:s 1:n~~1:8~1~~~:~ata

<?; ; =_:_;:; =:==-==

·=vw.~P.sfers reqffif.~· the use of both of these buses to complete. In particular, CPU

.:::UO{transfers to or from the PCI require ownership of the sysBus followed by
:/t:pwnership of the PCI. Similarly, PCI DMA transfers to or from the memory
=====::::f:l:l:l:[::::::.::?;t::_:-:;:,::-_.il~ubsystem require ownership of the PCI followed by ownership of the sysBus.

<\:. . . .·.·..-:.: : . .\.,..

·-:-::::::::::::::::::::::: ~=~={
·-::::::::::::::::::::::: :·:·:·:-:.:
..·::::::~~~~~~~~~ ~~j\::~~:~~~~{~~::. :-.

9-14 Digital Confidential

·:·::::::::·:·:·:::::::::::·:·.

.:})~~}}~~~~~{~)~\\?\:.:.. /{:/~;~·:····

.::::=:::}~}

...::::;::·:.:-:-:.-.·

:-:-: :;:;:;::::

::::::;:;:;:;.,

.~:~~-~:.::_.:~.: ::~::~_::'_.::~_:~.-.:';_.~::'·,'_::_.~_:_:.~:. .i/J} : : :\_l_: ·:·~_:r,\_: _: :._,~-:_~: :l,~_,_:l·: ~_: :'_~_,: ·_~_,l_:l_,:_:~,·-~-:~-~.1~ /./~~If~? :-: : : : : · ·.·. ·
Because of the non-pended nature of these buses, during rnAQ tr~sf.HXJ/t.l::Af
__ :,'__.

:_,:._;

::::::::::;::::.

~1:~:ii1fy~u~~s~':t:!~~:~~e;a~:.t~~e~:l1'1fla~Q~,,,:

£;~f:~:=:~:l?m~!Er~b~,:~:~ii;~~!!t£~

For any transfer requiring the use of both btlsij(~W\m~:)210'ifililtl~i~hip is
responsible for acquiring the second level bus oiFb.i.b.iU\Qf the . "Initiator.
Deadlock occurs when the CPU and a i-~m9.~::,.:PCI ag~t::fi~ye initiated
transfers (acquiring the first level bus,:A:tln~:\\P,fl\Lt.he syM3,lis, the PCI device
the PCI) which also require the secong:]~Vefn~@tfi~J;JPU the PCI, the PCI
device the sysBus) to be held at t~~L~~m~ time~···:n~~ngg:the 21071-DA chip
unable to acquire the second lev~lJ~#.i\\!~h~ither agehtf
The 21071-DA chip resolves ~~:4,\~~k:,:byillirJ.lj~g>the CPU to relinquish
ownership of the sys~us the~~p)famyjng pridHtyfffer the PCI agent. By giving
priority to the PCI . ~ipt, the. . 2lq1:l?iA. chip ifVes the system designer more
flexibility in choice':'otr?CJ\g~vices:~::;:~Ui~µg_ devices which resort to the use of
PCI disconnect W. the1r-nln@lmg of d&i(ll9@t situations which arise on their

~~:;m~er:!~lf~-~j~.:~~=~'''k~~Msy':::~uish

9.4.3

~~:7~1~~«!t~~~::;11ar:~~iSupport

for

the sysBus by using a

Intel 82375EB and

The Intel s~a-ij.EB.i:[:~dt8237EffBtEISA/ISA bridges (EIB) provide three
sideband s&ls tr:t:ltt~ivi.4.'t.::,mechanisms for flushing system write buffers and
to allow a '~rag;~i~d ac~~~~ time of 2.1 µs to a master on the ISA/EISA bus.
The t~t~~--s1g:!~~:)[~~~~-:.:-:-:·}:.!_ i:l·l:.f

• .,:fJtJ{~HREQ!Il?l:)::_~.-!:_i:}lr··
······· ..·.·.·..

•.,::t:. 1.~Q#

·-:-::::::;:::::::::

M~~QP

first ··£wa~::l,i,i:::outputs from the EIB and the last one is an input to the EIB.
'·'.·::::~:?·

EIB asserts MEMREQ# and FLUSHREQ# when it requires
guaranteed access from memory. It expects the host bridge to assert
MEMACK# when it has cleared the path to memory. This is accomplished
by flushing any posted writes and disabling the posting of any further
thereby guaranteeing an access time of 2.1 µs on the bus.

Digital Confidential 9-15

.-:.:·:·:·:·:·:-:·

·:·:·:· ·-:-:·::;::·:·:-:-::::::;::·:

t1·1i~·1.1.1·1:\ .:::ii::::::t:

·:;:;:;:;:;: : : }//

· ~~~~~ ~e:r:o1!!!1:~! !:i:s:~~~di::~~CQ2f•I~

the CPU be flushed to prevent deadlocks betweenji:\]PM!Aifaf:~q@~t frMff:an
ISA master and an ISA bus access from the host:J$gdge. Irf:ttiji\\::~~ too, it
expects to see MEMACK# asserted when the ~ppfipr.~ate buffefS:\iJYive been
flushed.
./)\:::..
·-=:<%Jll]}::=::::..
·.·.·
.-:::::~:}~:~:::::;::::·

. ·-::;:::::::;:::::;:::}~::;~\::-:-

The 21071-DA chip provides its own mecb.\Mlimn\fQr de.adl4¢.k'\)pt~yention,
by preempting CPU transactions to allow D~\i~b.~A~tion°S"''toieomplete. It
therefore does not need to support the deadlock . 'iif~Y.:inti.9.~ mec"hanism of the
EIB, and does implement the FLUSHR~~'=:PF:2toc0Lt:t:i~~i\rnt>

Because the 21071-DA chip &i.ij~)ri'dt.\iijji)l~m.ent FLUSHREQ#, external
logic must force the asser,t.j.pg\\j~f MEMAQffJ![?to the EIB upon the
~~s;::~lt !L!i~~fo~~~:f:)l~:-,7~~ation ·rar,:::t\fEMACK# going to the

EIB_MEMAC~::::;::·N-\\\fa(~E~l~l1:::¥.\Nn

(NOT FLUSHREQ#) ) OR
( (NOT M~~ft~Q#) ANg:[JIQT
.
DA.)VIEMACK#))
....::;::·:::-:-:-:.-.-.··
:-:-:-:-:-:-:-.

·-·-:·:·::::::::;:::::::::::::::::··
'"'.:::::;::;:;:;:;:··

The following is a des:SriP:tt.~fk9f the -~fotion taken by the 21071-DA chip when it
sees MEMREQ#,::a~~~rted:;tr:r:t:t:=:::.
1.

;;!': !~ll~!!I~~~!!: l~~~~s~r!;~~:~~~~=s~~:~:city
directe9/t9:w~t:a:::the 2.itQJl-DA chip will be retried by the 21071-DA chip

~4'1:J~lllr@i!l~JIB'er is

empty. Read-bypass-write flows remain

2. (°:~l::\~1071-DA:,:~Hfl{"~equests t~e sysBus (ioRequest =regular or preempt).
·::<ofi¢.i\jlirAA.ted the sysBus, the 21071-DA chip holds the sysBus grant
(iolleqdist):;,:;.~tomic) until MEMREQ# is deasserted.

t~!\~~~~us grant, the 21071-DA chip flushes all DMA write buffers
non-empty) and then performs a flush transaction (ioCmd =Flush) to
ensure that posted writes in the 21071-CA chip have completed. At the end
of the flush transaction, the 21071-DA chip asserts MEMACK#.

;::::=::::::::w,i·h

9-16 Digital Confidential

5
·

::::~:e ~~~~':s~ct~n:s~e:~ri~~a~~~£~jf~:Jn,..,:

E::~~i~~~;?.;fi~o~~:~;ar~:if::!fltt:~~:A
chip is holding the sysBus grant. (DM'A::Jvrites''\~iJlUil~w.ys start on the
sysBus before a DMA read is far endug}f~J.qµg on.lhijii[ff:QJ:49 bypass the
DMA write.)
··· ·::.:. .::::::::::::::. .
. . ,,<tttt+:r

Upon deassertion ofMEMREQ#, the 210;i!8lliJ!K~as;~fu MEMACK#,

returns DMA write-and-run bufferil}gJ~~PA~ity t('ff4#.r'm~awords, releases
the sysBus grant CioRequest =regµmff:Bmpt, or.ldl~)'~ and no longer
performs flush transactions followipg/fiMA;::wmt~f.~.·
.-:-::/~:::ilil:..

9.5 Interrupts

....·'.·.·.·.·.............

···:::o::::ttJtt::::-·
-::::::r::--

/::>1:1::::::1::1\:::\]:t:),,::::.

::::::::;:(?

·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.··

The 21071-DA chip interrupt~t:thlj!jppu -~§itigjjjl~::-intHwO signal when it
has errors to report..-::::T:Jie 216'-tl.f:O.&rnbip doeiPrijt distinguish between hard

:: :!:::~~::S~f~t;:~~-~1sioii:~oa~:;;::i!~~ ::~~
disabling error_.,f.P:rrectioiFr,pqfi.@g
usfrig:!lQfCSR
bit.
···:-:-:-:-:·:·:-::::-:-.
··:·:;:::;:;:-·.·.·.·.·.·.:-:-:-:·:<·.
.

The 21071-DA°''6h.iP.:!iit~~ not·. 'Jjft).iijd;~)~ interval timer internipt. This
functionality is expietj.jij::::t9,,._be proVfd,ij(l'''to the CPU by some other device in the
system. In addition, ·mt¢.!ffi~t~,:from'hther PCI devices or from a PCI interrupt
controller mus~J?:~A~P.t dife@~yj::tP::Jhe CPU without intervention.
The 21071-:Q,&.::.¢.hip):p~H;icipatJ~fih the interrupt acknowledge process by
responding::i9::!CPlJ.)r~id .P.J9ck commands directly to the interrupt acknowledge

~;~ii!il~::~~~~~~~~i~~~~~~~~~::~e

PCI

9.6 Errdlllndti~~nw;wi>

·· .. :.::::;;;;::··:·!f'}/f.be·.,.rci'iibRJg:~j~ction describes how errors are handled by the 21071-DA chip .

.·.,.,., ::::::? ''::::O?\]}W~. settirtg(pf]4$R error bits and the locking of the relevant error address

-://:::;//.

··

\f~m~ter, assuffil that another error that locks that error address register is not

/~tf If another error occurs, then only the lost error bit is set and intHwO is
<tl\j"[jjjl\iJillli!ii!llj_ ,., , , , ._.:::, , , , .l_lis'~erted to interrupt the processor when necessary.
1!!:::l:j.!::·:·::.'j::1,.!ntHwO is kept asserted as long as the corresponding error bit is set.

Digital Confidential 9-17

..::-::/(}~'.\(}\. . .
.-:::::::::::::::::::\:~\~~~~~~~I~~~~~~~~~~t}:::-.
,Jll:::::::::t::::·· :::;::;:;:;::::;:::::::::::;::::·····:·

The PCI error address register (PEAR) logs addresses

se~tp}~'j:tl:Jil!!'Y

the PCI. The sysBus error address register (SEAR), log~/tb.im@ddress':tljithviJf

~:~~:~c=v~~~~~0~sBus. The error logging;llt!l~,,,;:li'lli

9.6.1

c;~~~:!;o;;~s;7~~~~':s~ ~!'Ji~~~~~llls:~!~~i!~

the microprocessor has been notified that the reio?b.idJl:m errof}?Jn no situation
does the 21071-DA chip assert SOFl'_E8.R.QB on IltY¥i.ld\tr~nsactions since
it would be interpreted by the micropr9~~$[ij~f;(:~~tJnean'':th~tNi failure occurred

transaction is always acknowl~p~9'':oii''tli~(:(:~Y;.i.,µs before it is even initiated on
the PCI. An interrupt (intHwOlhvUI asserftijfajijfify the microprocessor if an

alfi::::~11~~ :: occur on a CPU-hlitiated

::ra:7:: :::e

transactions are,,.descrlbGdi:\)ijio.w.:
.· :·:-:-·

·.·.:-:;:::. :.:.:.:.:-:-:.:.::

. .,,,.,,::::::::'::;:;:/:. :-.
·-:-:<~{}~~~/==·

On an 110 trans~~:ti6.~:::·imtj~tedb:Yftij~f2ion-DA chip, if DEVSEL# is not
asserted within 5 cyCl~~fl~p~{g,l071-DA chip assumes that no PCI device is
going to respori.9:J~tUi.is tHiQ$.~~~i~W·· The following action is taken:
1.

Thpro~!~.·:.O:l.•,:_._:_1_:,:.i:,:~_l,1.•·.·.··:~'~!.~'.te:fi~~~;
:,'
the PCI transaction using the master-abort
...

:::=:::::::::::>

2. The nD:i.#!::hi'j::~::::'set i)i!i!the DCSR. The pci_Cmd field is set to the
apptQPrl4.f;.~1::y~Jµ.~L@~p,pding upon the transaction.
3. __,4pj.j\\.~c1 ~;;bf.t:llaf~~~:·· register (PEAR) contains the address sent out at the
·'.<)P.im~:ping of the PCI transaction, and is locked.

·.'{)'Mll@l~tbintHwO signal is asserted to interrupt the processor.
r;~a~l~i::ilJt· 21071-DA chip forces the value 101 (cpuCAck HARD_

:-:,:::::::::::::::::y,,..,.T.. ,.,.,,...,

orfioCmd<2:0> to end the sysBus transaction.

To clear the error, 1 must be written to the nDev bit in the DCSR.

9-18 Digital Confidential

.Jf!j[j![l:iili·l'·:1·111,::.·1·1:ii]\\::.

J:i :::::::::r:· : ;.1;:,: i'·:·:i: : : ,li: :1:,l': ;:;:t:>=: :=:=:=:=

}~)>:t.Jr··
f {~}· /:}~t{
: : : : : : : : -- .":'.:.':;.:.:_=.:!.::~.:._ :~:;_: : ~·: : j: : J>
_.::.::.:;·:··:f:..

9.6.1.2 Target Abort Errors
.·.: . /::::::::::::.:..
:;:·.'·:l ·. !li·!itt:t:lii!il/
On an 1/0 transaction initiated by the 21071-DA chip~Af:\it'.i.itti.iget def:j~{:jlf
terminates the PCI transaction using the target-abor\\jpf()tHMU;:t,J.!~tf.9~lowihg
action is taken:
. :d:lt-i::!l!l·(
· :·:::?i{[[i[ij[!.l!:·:!;i!:!:li)::·
1. The 21071-DA chip, as master, terminates thet2Qf\ttQ.P.saction ·1fr
accordance with the target-abort pro~lt .;::. .
···::::qlEi\itl::\. .

2. The tAbt bit is set in the DCSR, and:·=:fheJllmG:m~ fi~ia!!il~:l·:~lt to the

:::::::::d::e::~e:~;:l;:~!lt~::'sent

beginning of the PCI transaction, :dl\[\~jji~!~ll~:It:::::.. ··:$:):?
4. On writes, intHwO signal is ass~r~Qij:to inteTiij;jl,$t.b~ processor.

out at the

5. On reads, the 21071-DA chipi)!if.41.~i:l).i.h!hYalu~=-::fdff(cpuCAck HARD_
ERROR) on ioCmd<2:0> to.;.eqq/thitiYJ.Bil~ttransaction.
6. To clear the error,...a 1 m~t·;1:·=~tte~-=::i'tiii\lji!:iAi,t bit of in the DCSR.

9.6.1.3 Address Parity Erro~:~.~'\·· . . . ;: : : : . :. . ·. ·-=:::::::tI:=:=::::::l!li·lill·\::lltllkt:=::. · : :·
On any 1/0 tra~~action -th.~~:::!~·:·_no waj(f.'.().f{the 21071-DA chip to determine

::t2~61ai;rA~1i;l:~~~Rl'~~~!~!:.s~~~~ ~~:::!: ::~~ey

:;~:~~s parity errdi'::W,f:,.:etionJ<A.,f::::Wresult, the 21011-DA chip can take no
···=:::::::::::::: ·:.:-:-:·:··.·.·.··-

·-:-····:-:.:·:-:-:-:-·.:-;.:-::'.·::::..

9.s.1.4 Read oata Petr~wa;ttq'1§=:. :-::::::=u:rn:.r:>·
On an 1/0 .~$.if/fj~~$~¢tioµ. initf~ted by the 21071-DA chip, if the parity
generated :AW\\~he j#.~pfuiqg!'!Q.ata sampled from the PCI AD lines (data) and the
byte enabl~iWP.tv~ijpby tli.~f:g107l-DA chip are different from the value sampled
from V.ti? a\f:~~q\\!4~t.t\J~@lty error condition has occurred. The following action
is ~1~i:::=:·· · ·: : : : : : : : : \l!j: =:l.:l:\l :'\.\ j :~j j: Ji\ i:~: : ·
1.))Tft~tlransaction continues normally.

.: -:·: ::\\]i\}tg~ ····::¥fi~=::gJ.01::t.~DA chip asserts PERR# on the PCI.
·==>::':::>= :-=·:·:·=\:fri~;::,::.:~:~j·.t:h~e :ia~lj::~jj::·is set in the DCSR, and the pci_Cmd field is set to the
:;: :-·

\f:j{i\)i~pproprial~\1alue depending upon the transaction.

:::!}:!!~!!.fI:.\:,..

.·::~~''.'}\I'he PCI error address register (PEAR) contains the address sent out at the
: :·=-:==: - {::\) <<)·.· beginning of the PCI transaction, and is locked. (Note: If an error occurs
·=::::::::::::::>
... ,.. ..,·.:-::-=· on both longwords of a quadword transaction then the lost bit will be set.)
-.·.·.·.·.·.·.·.· ... ·.·.·.·.·.·.·.·.·.·.

-=-:=::::::=::=-:::l§~::i·f\TP.e 21071-DA chip forces the value 101 (cpuCAck HARD_ERROR) on
···<\]j:fibCmd<2:0> to end the sysBus transaction.

Digital Confidential 9-19

~lIII~~~\..
\{J?: . :·.:...:. ·.' ·.',.:~.:·:'.:~...:·:~:·~:'·~:·';:~'·~.:;.=:,f.:/ ·.·,·:::::::tt?:::::::::::·
' \/(::;::::i. . . ... . . .

9.6.1.5

~~;~~~e=s~~=u::::~: ::::1:;•1!~-·~l!f'lillill)
::~:!b~a~:c:~~::e~: ~~i:k:~=:!so~;\l\ilfu!~

daili. error

1. The transaction completes normally :'a~::lth,i:::~81~. ··:-::::::t:::::}::m·::;::;;!.:::·::;;;;:;::J>

2. The iOPE bit is set, in the DCSR and th~':::P~iLWmd. field":'iSdfot to the
appropriate value depending upon the ..~ransa"Cti~l.:#t::t::t::::,.

3. The PCI error address register <PE.41.):·:ii.rttmns th~:::'£aaf~ss sent out at the
beginning of the PCI transaction ~f.@.{fs.;'10¢1~1.~t(Note: . ,If an error occurs on
more than 1 longword of a singJ.~,:J~?.1te
burstttM~ni.$.t
bit will be set.)
.
,.,:·.·.·.·.·.·.·.·.·.·.'.",','.·.·..
···::::::::::::::::=::::··
4. intHwO signal is asserted to #tt~61im{:th.~. processor.

5. To clear the error, a 1 mu.~t::Pi:l:.:.nt~R\!,~i:.!b,APPE bit in the DCSR.
··::::::::;:::::::;::::: ...

9.6.1.6 Retry Timeout

.: : : : : : : : : : : :'"

-:,:<tr .-:·:·:·:-:- ·:-.

··:·:::{:~:}::::··

E!::~~Eti,~9.\~?~l:ft~:Pb!:r:~!J2~m:!s
···:···:-:-:-:·:;:-:-'·"··········

·-:-:-:.:.:;:·:·:··-·.·.·······

1. The 21071-DA}:¢~p[::4.w~s n~t'''tijt,eyi'!iPie transaction on the PCI again.

2. The ioRT bit is ;~£:'ii·b,ij!j~h~\D.CSR''':!nd the pci_Cmd field is set to the
appropria~~ ::Y~hMtPepe'tid.ivifa~pon the transaction.

3. The PCUia.,6¥:\:!1iai~~s1e~:~f~; (PEAR) contains the address sent out at the
beginn~qg\:br
ttl~::;pcI:::t.t~saction,
and is locked.
·.·.·.·.·-:-:-···:·
···.·::::::::-·
···.:-:-:-:-·-::::::

int.J.IwO::;~~gpAt.:!ij~ assf~d to interrupt the processor.

s. Ja~~~~lllt! ~!!o;;::ss~~::1~:;s~~:~cAck HARD_
.·::::::;:;:::;:;::::::::·-·.·.·.·.·

6. T~:~·cl~~r. the error, a 1 must be written to the iORT bit in the DCSR.
. . :~:/{' /~~~\~}~~~~i\::::::..
.· .;: : :·: ;: : :;:;:;: :;:.·.·.·.·.·.·.·.
;: : : :;.·
··-:-:;:·'.·'.·'.-'.·'.·

/::\.'·l~$~2'':'tll• Tra:nslotJ.:pns

.,:'l}:::pMA tra~~:i~tion errors will be flagged by interrupting the processor

,{(~:Q[~HwO asserted) when the error occurs.
· · =: {\.~.-~.~.-~.·.·.~.[:.· ·.:,·.= :..:.:..
. . . :~:~:;:;.:.:_:.
:.:- :.:::::;:::::;:~::.; :::::::::: .
...

··-::::{~{::-:-:.:-:-:-··

·······.·-:-:-:-:-;.:-:-:-:-:-:··
'.·'.·'.·"·

·-:-:;:;:;:;:;:::::;:;::;::::;:··

9-20 Digital Confidential

_._•.,•_:,.•i_,._•.:•-•.:._•.;J:.11~1_:•_:·_.:l :.·:i':~_:·_:·_:··~_.,:_~.:·:,:_·_~:-_::_.:·:·'.:_:·_:~--~_:'.~,-.:~-~.-.t:-·

:A
:':·:·i:ti!,jiil
·: j·: ~:): : il,._.,•

. ·•, :.:•_.: :__:;

•lllf,mwt~i[!

.. '"·· ·w
On any DMA (PCI-initiated) transaction address phas~f:jf:th~fat~m.erategd_~ifity
of the incoming address and command sampled from #.b~}Pcr!~i:J\~4 CJBE#
lines is different from the value sampled from PAR{~#iddres·s:::::p@f:it.Yt~rror
condition has occurred for that transaction.:.~ The foU9W!@g._ action i~ftaf~~n:

9.6.2.1 Address Parity Errors

The 21071-DA chip does not respond to.,,,tfii:::[tra.psa~~i:6H~:[\:~i·•~4~ the parity
2 0

~~~) : d i~ ~!~~!r~h:h~~ ~~! ~:=~e~'·!~j$flflt~~:~!ll~~~o~e:!s~r

(PERR# is not asserted because it is only intendetflf.~f\:}:i~l;t@:. parlty errors on the
.... .-:·:·:·':...
·.·.·.·::::::tn:1;:::-···
Pel).
.·::}~:~:~}~}::;::::·:·:·:·
·························

/:t\:trn1::n:::s?\:::....

9.6.2.2 Read Data Parity Errors

·-::::;:::;::·...

\\}/
· :;:,: : : : : : : : : : : : : :
On a DMA read transaction data PAl<~~~\[:if therEi?'i$i![j.iip.rity error it might be

~~~;c~g~:e~~s'!:S::=~••{llf
tl::s::t~e~~o:~ri!.~h~':tie
./;>:/?/
· ·: :;: : : : ;: :,:,: ':\:\ .·.·.·

the error condition.

9.6.2.3 Write Data Parity E~·:;. . ,.

<::::}~::::::::::::::::::::\:·.

·:-:-:=::::::::::::

·.:,::::··}f::;:::[:,1::.i:1:t:n::::::.....

· .:·:·•·
.
On any DMA write .. thin,_§j~tj9n data?pb.)~~~jf the generated parity of the
incoming data a.;.q9 byte····~ijill~$.::::§amp1&d:\:fi0fu the PCI AD and C/BE# lines is

error condition has
~:r2t~:~~~!ll~-~~!?i~Sf~i:\~:~!~~~~two

:::::~. ~;1111~ ~~t!·•~:AR,
1.

parity

the PCI

2. The dDPE:.:61£.iim:
. l~~tAn .th!:':nd~R
............
············

adata

cycles

~ee :c11~1e~~:~~e~f(~~~~::::~~ :~ ~~fo:~:ihat came off

iQ#.ff.wo'J~l~t-·_J$4\.§~~j~d to interrupt the processor.
5..f\1~i:1!~te ~i1?~6HBh~e normally on the PCI.

·::::::;:;:::·:·:·:·:·:···'·'.·'.·'.-'.·'.;.:

·.·"'·Tijji\iiip~¢icular cache line entry will not be written to memory.

···;t~Kfi::l,~:]~:rror,
a 1 must be written to the dDPE bit in the DCSR.
. ::: ;: ::
.:: : ~: :: : :::::::::'.·.

···=t~>:

Digital Confidential 9-21

.·. . ·. ...

:::::::::::::::::·

IIII\.
\

9.6.2.4 Memory Errors

l.~.~:~.·-~:~_.·.~_:=_: ~_.:~:_:.~~}.

. ;>L

·~~tt~~~~~tj~{. :'.:}\_·~:.::_:·

_;::::~:~:f~:'.·'.:;:;:::::;::;:·:

.:r_:_::_
__ ..

...

1lfll}lfrrn@il,ii

On a DMA transaction, if the 21071-CA chip detects a.P.Uiffifi(n9µ-exiij*-~it@>:
memory address, tag address parity error, or tag contiim:pafilj@ifrgr). it\vill
will log the address and the specific error bit, and . tt.fb.!1nate tli~:miY.ilµs
transaction by driving 10 (DMA cycle error) on ioQA.iji.g:i_;O>. The.'f8U9Wing
action is taken if data was to be transferr&bon
the-:-:P.C.JffHkt::·:·.
··
·····.·.·.·.·.···
···=:::::::::;:;:::::::::::::::::;:::::·.
·::::::;:::;:::;:;::::::::\{\:;.

_.;::::::::·.

·.·.·.·.·.·.-.:::...·

~--~-------------------Note ___::::~::::::~::::::;~=:/~>=:~:::-.·~·____··:_\=-=+~m~:::m:~::>_'______

Prefetched cache line data may not be req:~=;~=a.!l~:,[~!,,P~:i\~evice. If
there is a tag address parity error ~mrnti:g4~9ntrorj#,~P.ixiJ~rror on an

:i;:~:r~~=~;~ :~:o~~~ !1:~11?.:Ji!t~~~~~D~~~~71-CA
.·.·.·. :-:-:.)/j}\

·::::::;::;){({('

.·.:-:-:.:-:- :-:-:-:-:::::;: ::::::;:·····

·-:-:;:::-

·.·-:;:

1 Th
E b. t .
t
:::::=:::::::>.... ::,::::::: .. ·:::/:
.
em rr 1 is se .
.... :::::)](
·· ·<t/
....
2. The sysBus Error:A\ddress::j:~m:~:t.~r (SEAR):::'~6ntains the address that
caused the me1"~l!:'err.or, artdm~!i:. ~!f*'~~·
3. intHwO signal is ass~l.i.9t:t9. inte'tfiipt:\:tpe processor.
4. On reads, -::tb~:::g:+,Qn-ti:A1::&1ii:::·t~mni~:f~s the PCI transaction using the

. ·

target-aborFpd~~9§9~t::..

::::::;:::=:::=:::::=::::;::::
·.:.;·:·:-:::::::;:-:-:-:-

On writes, the 2io7~f:J.)~:J~pip di~ftiisses the write buffer entry (single cache
line). Note tb..~tif a Mti.gl~UPCJ write burst crossed a cache line boundry
and ther~Q.r~::'tl)l~4wo W.H~fbuffer entries (two cache lines), each entry is
handleq::::~~ifi~~,ifon,&he s§sBus.

;~;11;11~~:!;::;c~~;~r:~~2;~;;;:! are
. .. ..

. . ·.·.·.•.•.•.

{ ;1~! ?

coµfigqr~d in ECC:::ifiocfo·, t~e 21071-BA chips will correct the longword with
the\mpg}!';P.it error before sending it to the 21071-DA chip. If and when this

1 1'!1 ~1r~f!!'I~ ~r*~~E:~~;:~~~;:t~~:~:2:~~=:
~

·:::::::::::::::::::::::tL-:::: ··:·.

.
to be trallsferred on the PCI. (Note: In some cases not all longwords of a
.Jt=: iehe-line will be transferred)

·:::::\tjt ::'l\\tj':j'\\j\!/:L intHwO signal is asserted to interrupt the microprocessor.
':::::+::]:.:=:::1[.!=!.2t r!So error occurs on the PCI and the transaction completes normally.

-: : : : =: :~:.: Hii\fhe cMRD bit is set in the DCSR.

9-22 Digital Confidential

·:·:·.·.·.···

.={~t\r ·:·:\_·_.:~·_:'·::_._:~·_.:~::_:~-_.:·.r_:: :~:~_.:~:~ _.:~-.:~:·:~_.:j:~_:r_:~_-_(.~J?
__

1!i~l~l'lllilf1l!;l~lilfr;b,.

The sysBus error address register

(SEAR)

contains th~ ?,!J,:!!: 411:1;)!)?
..

the correctable error, and is locked.
.
,:ft:i::::[\\,j:::\::iiiil[::1·. ::i:l[J\t::::::,.. ··::<'t]:j]\j[:j:jljj[l[jl]}/
5. If the Disable Correctable Error Interrupt bit (dCgUls set#thidnformation

~~~t!7i~:i t ~:.~d ~eae~S:::i~~:•I~.:~~~:=·~~-

::6.~.~e;;; ~:~:e~:~:t:::::::i'~tli~{~~\tti~:~=~.

if there is an uncorrectable error (parity error o¥4JijU.fil~J~it EC:C error) in
memory (or cache), the 21071-BA chips . wiUMnf.orm lh~::j:g).:P,7:~-DA chip when it
sends this data over the epiData bus. _,/J}{\J]\\l\\mft:::::,,,._
··.::\{:\/'.

If and when this longword is sent to ~t~:!:~:~~;=I:lDl]:[~!P, along with the data on
the epiData bus, epiBEnErr<O> w,j;J.li:~ihl.W.~ inforiiiattqh whether this longword
had an uncorrectable error or no~~:::f!tl$~!f'@.ll~W:,jpg action is taken if the longword

;;a: ::!:-~n~e..!~F::~~:•l!~I. (i(#~!lb some cases not all longwords

~: ::::n~~t~:11;~··;~~op~~ssor.

3. The sysBu~}ijftP!::!J:ddres:iiffigj~t~r. (SEAR) contains the address that caused
the uncorrecfiihleimettor amfls=m>.eie.d.
,
4. If the bad data :~:~Hf-~~$.t~4 by":'ij{~:PCI, the 21071-DA chip terminates the
PCI transa~:ti9BJ~-~ing::'t)!~:::~tg~t-abort mechanism.

5. To clear,:::tti.ii.il~~::_jp1 lll~';f,lif,!~'" written to the uMRD bit in the DCSR.
·······:::::··

9.6.2.5

...:.::::::::::::···

..:::::.

Scatter/Gatbit···En.!rJ]:::thvtd~l::,Errors

On sc~t~er/lt.l.~t,]]iiiappil!jpMA transactions, the scatter/gather entry being

S~il~'!!!::i:.:l i~~::be written to or read from memory
ri{~j)j·~::~:~tn~.r address register (PEAR) contains the address that caused
errM{mi~~='is locked.

•·;·.11111.JL•VV••

si;al is asserted to interrupt the processor.

On reads, the transaction will terminate on the PCI with the target-abort
protocol.

·::::::t::·::strnI:i \:} clear the error, a 1 must be written to the iPTL bit in the DCSR.
1

Digital Confidential 9-23

9.6.2.6

9.6.2.7

9.6.2.8 Scatter/Gather Errors

~:s:s!~:~~!lf.~.::!~k~~~) contains the address that

3. intH wQ:',~i,l!IP~j\[\i,1~:~$d ~~/~~terrupt the processor.
4.

If the ~#:t\_er.(g~th~r 'd~µ was for a DMA read, the 21071-DA terminates

th~,,,.;PCl~:-:~$.Etion .:PJ~g the target abort protocol.

.Ifith~'''.sc;il~ti~mif:i~*~~d was for a DMA write, the 21071-DA dismisses
. d\th@Fwrite buffe~F'~Mtcy (single cache line). Note that if a single PCI write
''\\gqf3.t:::~rossed a cache line boundary and therefore filled two write buffer
ehttji'-@tw9 cache lines), each entry is handled separately on the sysBus.
ci;ii\j~tlj:'-~rror, a 1 must be written to the mErr bit in the DCSR.

9-24 Digital Confidential

··:=:/rr==tff I~t?

.-:;::::::}~}:::::::;. -.

!l,1!.lliii'i!lJl}1'11~!8fa>,, W
This section describes the mappqlj)•~l;'•IW;:bit ;:s;r~or physical address
space to 32-bit PCI address
of the 32-bit PCI

10.1 Address Translation

sp~cl~tilld.:"th.i.tt>.f@p~lation

addresses to 34-bit physical mimt!Y space><t~rnti::f}=·

10.1.1 CPU Address M@IPh1g ;~l~l,l·:!:§P.l:Pe ·-=:==::::::r
The 34-bit physi~al ~i;:a~ii:i'1g4.r.ess··~p:i~iiil~~ij:divided to form:

~0:: ;0~!Ir1;~;~ ::~~[j•~~::for cs in the
0

21071-DA chips)::=::::::::::::=::?' I:t\>::::::.

•

PCI space::t<?>

•

PCI m~l&ey.Jf4W::hie~ijfy residing on the PCI)

21011-CA

and

The PCI de.d~~)£f{f.~!~l:!jhy§jc~!"''!~dress spaces:

:Jl'ilf~:11111!?~i

liFam.µ§:§Jt_to these three address spaces on the PCI, the sysBus 1/0 space is
iis~~l:i~\g~perate PCI interrupt acknowledge cycles and PCI special cycles.
l021@jJi#w~· the sysBus address mapping required to generate these
spac~i.Wt

Digital Confidential 10-1

Table 10-1 sysBus Address Map

··::::}~:~::;~·:·:·:·'.·:-:::::::::::::::::·

sysAdr<33:32> sysAdr<31 :28> Address Space

xxxx

. /\:Tlj~ 2101i~n#.~!*-ir#does not

Cacheable memory
space

./:?ltffjp~nd to addtege·s in this

··:<:::::t:·~:!::::::t:\. .·.·.
01

ox:xx

lOOX

~~~heabl~,:~~~1,111:i1t1~~~E:e~!'e~~·thl~

21071-CA\;l!~f~'!)~;jjl~i'.jjij;:~~!~71-DA chip does not
···:-:;:;:;:··

::::::t\l\{::j~~IL.

··-:'\f}:i\j'~.-~_'..=°_·'.·_:~_'<:sapocen.d to addresses in this
~.t"

............... ;.;.:::::·:::::·

··:·:·:·:::::;.;:;:;::-:-:.:·:··

1010

21011.~uK·t~~i~.·.·'.:_;_::_.·,::_'·,'
.
,J%n1II

!::::_::::;_.·.:_:_.'.':.'..
! ::.:.=_·,.:,_·_:_=.:.::_·.·.

·:·:·:.:::::::::::·.·.·.·.·.·.·.·.·.

· :·:·:-:-:·:-:-:·: : : : :·:

1011

··====·:·:.::~-;::::=::::=.

·..:-..:·

4~11111i~~if-1towl·-:.:-::: -:;::-:-:.: .·.·.·.··:::;.

The 21011-DA chip will
respond to all addresses in
this space. Dstream access
only.
A read causes a PCI
interrupt acknowledge cycle
a write causes a special
cycle. Dstream access only.
16 MB of PCI space. Lower
256 KB of this space must
be used for addressing PCI,
EISA, and ISA devices.
The rest of the space can
be used for other devices.
Dstream access only.

··.·.·.·.·.··-:::..··

.-::::::::;::::::: .·.·

PCI configuration space

Refer to Section 10.1.1.6
for details. Dstream access
only.
(continued on next page)

10-2 Digital Confidential

Table 10-1 (Cont.) sysBus Address Map

:·:·:···

.-:=:::::::::::::::::::::::::::=:::::..

sysAdr<33:32> sysAdr<31 :28> Address Space

xxxx

ii~}::;l~~ MB of':pfi}!i iBe
1

PCI sparse memory

space

·{flJiddressable. Thedower
. .:::O:\i'ddi~as. bits are used to
.)}\.... d'.JU#."':'P.yte masks
,: :i i:)i,[i :i·.i![j!l .1\:::[i::i::1:::::r~!!~l~~n~~n~~ 4
<·':f/·>.·.

·. ,,'\{f{§.l.l:~pace is reduced to a
..,,,,ttg~:::M!l sparse space. Must

._. .::;:~:~~t~t?~~t@ftt::·:::-..

USi~~~~bffS space when byte

,::=:t:mt=:=:::::':===tt:t:mtli>==:·.. or word access granularity
"'='==·:=:=:====·
.. ,., ,=:/. .: .:. .: .:·.=.:.: .:.:.:.:.= .=.':.:·_:=_.=.,=_,_:=_,:_,:.-.:1._· .s. .·.-.required. Read or write
. . ,.. . ·.-.·::::t~I
,.·.·.·.·.·.·..
··:·===?t?dirlgth is no more than a
{:t!j:[:i:ii}\:i:i}:.:.:,..
··''\quadword. Reading more
=·'-'\(tt
than the requested data is
···· ·: ==:=:=:=:=: .
·-::::;::::::=::::;:::::::{\::;:,...
harmful. Prefetching read

{~llfi\t\;t •·. '\i\@(ijf !,~,!"!fy~bited. Dstream
den~]#,!ffi:R9' space

··.·
... :-:.:.:-:-:;::::::::;::::::::;....

_:/} :::::::::::::;:;:;:::::::;:::::-:-:-:-:-:.·-·.·.·.·
;'.::;:;:;:.:-: ..

4 GB of PCI space. Used
for devices with access
granularity greater than
a longword. Reads do
not have side effects;
prefetching of data from
PCI devices is allowed.
Typically used for data
buffers. Dstream access
only.

.·.···.·.·-:

10.1.1.1 PCI Spars&,:::w~··splix- 2 0000 0000 .. 2 FFFF FFFF

~:~lt.~ir1f~:~::~:1d:S
:~~~::w~· ~~.?a.~t:
gr~#lin.ty, which the PCI requires. Therefore to provide this granularity, the

Al· jjj[jjjj:}\~~~-~Jfr:s!e:!\~~:n:::!i~~e~:o:n~~e:~:. ~7~r<8;1~~s:;:ts
1

,.,,=;=:,","}'?'==·=·:·="'=\=~::=faiii4 to gertef~~hiuadword addresses on the PCI, thus resulting in a sparse 4

·,::§l.M~pace thaf'hiaps to 128 MB of address space on the PCI. An access to this

.-:-:-:-:-:-:-:-:-:-:-:-·
::::::::::::::::::;::::::::::::=:-.

·.·. {it~#~e causes a memory read or memory write access on the PCI.

.,.,.: ,:=··-:::::::::::;:::::::::::::
:': :=: : : :=: .: ·: ·=·=·=·= :i.·:.-._:=.·:.:._:~.':_:._: _:=_'.Th.=.':=·:·'"'· e mapping is as follows:
··.·-·.·.·-:-:-:- -:-:-:;:-·
·-·-:::::::·:·:::::::::::::::::::::
··:-:-::;::-:-;.;.;.:- -:-:-·.;-;.·.

·-:-:::::::::::::\{\::::: :-:-:-:-.
····::;:::::::::::::::::::;:;::;:;:-:-::

Digital Confidential 10-3

.;;illll;\!;lilii'iF
::r~:One:~l:~ a;!;!~s~~Itsa~!:~e~!~ :!:l1~';~,-~;,~;f:s>

during the address phase on the PCI. AD<31:27>)Uii{ijb.tained frohi)~tie of
two host address extension registers, ~,and·~~;tJIAXRO (which is
hard coded as 0) is used for sysBus addte$.$~'s .l*.tweeii''''2~:iijQQQJ)QOO .. 2 lFFF
FFFF, that is, when sysBus address <31:2.9>3$.i:'(k:tHAXRT~=i$.?u$.~d to map
sys Bus addresses between 2 2000 0000 .. 2 FF~ii:IFIFi. that"'Mf when sys Bus
address <31:29> is non-zero, anywhere iri.-:.tb.~ PCt''id.&~~~:J~pace. HAXRl is
a CSR in the 21071-DA chip and is fuJ.:lyfa?,r9.mt~HJlma6M~!{WJ)is allows EISA
/ISA devices that require memory to lif:hiapP.~Uh~:::the lower 16 MB to coexist
with other devices that do not have thitlrestrmtiiiUHTh.e lower 16 MB have a

:;~:;~P=i~~~~ to 0, an{iS\!~~~:'.,ng li~(PJ can be programmed
Figure 10-1 illustrates the sy~~~{to Pcl<ffi.~mP:t:Y address translation.
Table 10-2 shows th,~t:generatiqq:::9.r:1file byte -~ii~bles, and PCI address <2:0>
from sysBus addre~~!:\\~'!3=,it.,.. .,.,.;.··.··:::·::::::::::····~t;:;:;:\:'/:·
·:·:·:·:···:·:::·:·.-.

10-4 Digital Confidential

·.·.·•·....·.·.·.·.····.·.·.·.·

::
...

·'~,.:~:~:~:,:~ ·:~ 1~Jri11m+

Table 10-2 PCI Sparse Memory Space Byte Enable Geim,.19.n
.·:·:-:-:-:-:-:-:.:-:-:-:·:·:·:·:·:·:·..
CPU

CPU

Address

Length

<6:5>

<4:3>

Byte

00
01
10

Word

00
01
10

'Inbyte

00
01
10

00
00
00
00
01
01
01
01
10 ··.·.

. J: l!li! l:l t· : : : t:·): :i:~li\i\:'. !!":lt

.:·..· ·':· ... :'··
. . . ·'. .:. ··.:·....: ·. ...· ·,: ...· · ·'·.='...
...· · : ·...
····=' ·'.·::•.· ·.· =...· ··=•..·=· ·;=:...·'•::•...:·.··'==···=:=.=:··.'..,:.,!!l,'il'f
...

illfllhwi:t\liJ
...................·.·,·.·.·.-.·.

CPU Address<7>, 00

Longword

09:}tt\.. . ·.

CPU Address<7>, 00

Longword

Illegal

Longword

Illegal 3

Quadword

0000

000

Byte enable ~f#{~hfil~~~W.hhat hYtkline carries meaningful data.
spa~:::@.bory::~jjJ;,
Address <1:0> are always 00
3 These combi#i~i>.:nsJ~i.nk~hi~i~rally illegal. H there is an access with this combination
of addre~s<6:3;:KJh~jt~he 210'l'liQA will respond to the transactions but the results are
1

2In PCI

OOl

unpre4~~~~··=::::::~lti!:l!:)f?;.,._·.,.,.,.....,.,.,.,.:::~;/:;:>:

Digital Confidential 10-5

Figure 10-1 PCI Memory Space Address Translation

HAXRO

.::-

•

{

•• :=

Longword· Atl&&Ss ..
·(Refer to raol~=f.Or::J'ranslation)

:-:·:·:-:-;.:-: ·:·:·:·:·:::·:::·'.::>:;::'.:-:·.

27
: 0

.·.

:_:_._: ·: _,_: : :_:_:_,_:,:_:_: ~:'·~.:)0: : 3: = : : : (\/:}t: :t: : .

·a=an::::::::~tJtwe..

.:·:::::=-

·......
:·:·:·:·:·:··:_-·:-:>m:r
:-:-: : ·:·:·: =·=== :_=:_·:=.:=._:! 1- -~=:::::=t:nr
! -t

30 ::\g9

·=:::=:::tilf' 07

Longword Address
(Refer to Table for Translation)
HAXR1<31 :27>

•

W-03123-TIO

·· ··
_,)~\\:important point to note is that sysBus address<33:5> are directly available
_,: : ;·: =: :=: ·:. . . :·:·:=:=:=:=:·. .d:f:froin the DECchip 21064 microprocessor. sysBus address<4:3> have to be
ii[j[j:J]jF<JlI::derived from the longword masks, cpuCWMask<7:0>. On read transactions,
·· ··llt::::=::{J:tb.e DECchip 21064 sends out address bits <4:3> on cpuCWMask<l:O>. On
··=·=·=·::=::;:;:;::::]Wfit~t_transactions, the relationship between cpuCWMask<7 :0> and address
··====li)t:t~:::~4:3> is as follows:

10-6 Digital Confidential

If cpuCWMask<l:O> is non-zero, then address <4:3> i~ . .QQ.
If cpuCWMask<3:2> is non-zero, then address <4:3.?:(~~)[[Q$.b\::::.

~ :~=:~~~~:~ ~: :::~:~::

::: :~:::: ::~ll'!'i~Gl!!~!~lliinh

- - - - - - - - - - - Note/>':·.

-:{\[:·i·\j:.!l l!.j j!![. .::t=:,..

·.·.:,:,>=:i~tr.

t~~ht;,jft~gw~;J~!l§,I\¥¥:~

Accesses in this space are no more
has to
ensure that the processor does not merge'=''e6n~g~q#ye wrHeiflh its write
buffers by using memory barriers after eacli'°'\vn•t\architecturally,
if a byte, word, tribyte or longword J~~~/$9::.be Writ~iWi.~:: the PCI,

:!!!"o~~~';::~;:i~t ::d::~l~,.,§~s:!~on

to the upper longword is not ~!9Wffl!.. The ·.·Mily!i]igal value on
cpuCWMask<l:O>, <3:2>, an.9{~9;.~#:H!!~!k§.Parse spaee is 01. Similarly,
if a quadword has to be writ~J:f''fo':':t}l~!)=pQ.1,=. ·software must do an STQ
instruction to the corresp9qg;jpg addr~is~]Wbl.:· only legal value on

~:ii:!i~,,t~~;;;1;~:~

one

correspondiiig::J1P.~d:word 'adij~$it:::f.\n LDL instruction to the upper
longword or LDQ:=jl.i~tn1ction\W1t.:::return the wrong data. If a quadword
has to be read fr6ih?th:~KPCI, software must use an LDQ instruction.
An LDL in~.~IH9.F~<>n·.·Wjj}:!:r~tmro. wrong data.
<}'.:::::::

··.·.·.;.······

.·.·.;.:-:·:·:·:-:-:.:.:-:·:-:-·

·:::::::::::::::::>

10.1.1.2 PCI Dens~::(Mf!.mqg::(Spa~:!:+ 3 0000 0000 •• 3 FFFF FFFF

PCI d~mse "'i~i,jp9eyl~pac«!:j~:!typically used for data buffers on the PCI and has
the foJ:]~)Ving==~~ll~~!~i§is:
• ./}¥h~~ is a orieit64)ii:::·mapping between CPU addresses and PCI addresses.
...........
·:'?\~Jib.ID.vord address from the CPU maps to a longword on the PCI. Hence
.;/:l\I\I\lII\l==t=:·. tifikpgm:~t4.ense space (as opposed to PCI sparse memory space).
.':·:::'.:'.3.;'.;'.:::::=·:·:·::;:::;~\j:·\i:l:i;:;;\l::Byt~··=:~f;:;i~fij::='accesses are not allowed in this space. Minimum access
. ..:"'\:::]?::-:lti:J:E:kranularityi::'is a longword. The maximum transfer length implemented by
.:;: :<:=:=
.i!Ullfthe 21071-AA and 21072-AA chipsets is a cache line (32 bytes) on writes,
·,:::::::::'::·'..'.'.'.:'.;.:J/f\::,..;::::::::::'<::::::.:.:.·· and a quadword on reads.
:::~~~~fj~~\;::=;:::::::;::: :>:·:

·-·.::::}:)~\-:.:-:-:-:-:

·:·:·:·.

····:·:·:·:::::::::::·:-:-:-:-·-·.·

Digital Confidential 10-7

=:.l.=.:.:~·;.:.~.:.1.:1:.'l~111!Ii ~·; :>··

......

·-:-:~::))}(((:::· ....

• Read prefetching is al owed this space; extra reads h@yel!!~i1li]lfltJF
in

::!:i:~=~ i!~~~ !;°~~=~rad::~:::,::~Ze~!:·-=!~~•Afl~
:~a:e~1~Iways be done as aquadw=~ read;•j1itt;:ur8t\1~-i\ef two

•

Writes to addresses in this space cru.di~Mbajfered::=hit~b.i:~p~Cchip 21064

;::;;;~~:::~~arr:: !~ ~tt!:~P!~~~~rl!i=!~:11-.~~aximum

.................·... ·.·.·.·.·.·..

The address generation in dense space is .~f.tfoll~~~=~::i::::[:\:[:![l[li=>:::...

·.·.;.

~~s=~~:~~
;g~~:e~!r~:ts~n~1t!t~::~!!~~2~~~I
address <2> is always 0.
··
··==<%?\f}\:.
addr~$.~·[i.Jii4~g*:::m~::g~nerat;d

On write transactions, PCI
from cpuCWMask<7:0>.
If the lower longword is to be .-:di.ten, PCtNl.ddt~f;S <2> is O; if the lower
longword is masked Qut and .#bg:::t.t.pper loniW~ttCis to be written, PCI Address
<2> is 1. The numq~\f)~f long\¥ofd$%Written on. lhe PCI is directly obtained
from cpuCWMask<:7::q$( ~y conibiQ#.§.9.!t:Qf cpuCWMask<7:0> is allowed by
the 21071-AA oi:. 21072-~:::~h;i~~.ets. ··::\:)jj@<>
.<}::::;::·:·:-'·
::{{{\:;:-.

·-:::::::::··::::::::(•'.·'·. ..

...

. ............... .

__________......,.._ _._."'='....
=<:..,.,.<..,...::t....,.<>:\Note - - - - - - - - - - - ·.;-:-:-:-:-:-:::::::::·:·:-:··-·.:--

If the cache lin·~<WHtt~itPY th~<tjf,J'~essor has holes, that is, some of the
longwords have beetF~~~~~4.. out, then the corresponding transfer will
still be p~rl'4~tii.~dA~·n the<P:Ol:=?with disabled byte enables. Downstream
bridges ::m~$F6e=W~hl~ to deS'.FWith completely disabled byte enables on
the PCJ:i:4#ring)Wf.lte.,::~r~nsactions.
·.·.·.·.·.·.·.·.·.·.
.·.·.··.·.·.·.·.·
-:-··:·····::::::::
=::::/{:}::.

·:::::::::::::::;::::::::::::::·:·:··
·.·.·.·.·.·.;.·.·.·.·.·.·

::;:;:::::::::::::

..::::::·:-:::::::::·

10.1.1.3 PCt ~pltie
0000 .. 1 DFFF FFFF
Tb'l:[ipQ.J.tsparse IJ(f=gpace is sparse and has similar characteristics as the PCI
0

iJO:\\lli.9@1\if:Ij>cooo

.·

·miJl'!l;1 1:ftlT!1fi~:!:~~f:~;:i~:::::;~~~!iiZ~d !r

-: : : ~: : :~: : : : : : =:=·

"'"''.la4.ress <33:~:§;· are used to identify the various address spaces on the sysBus.

<>:::.:.
.-:/:::Address <7 :3> are used to generate the length of the PCI transaction in
··'":::O\t ···· :\:}::. . ·.·. :/\I=t6§tes, the byte enables, and address <2:0> on the PCI. Refer to Table 10-3.

·"':\\f]U[[\:t:Urnm::::Address. <28:8> correspond to the quadword PCI addresses and are sent out on
:-: <:::.,.:.:.::=::laP.~23:3> during the address phase on the PCI. AD<31:24> are obtained from
"'"'::<'U[\'ijij~\J».f two Host Address Extension Registers; HAXRO and HAXR2. HAXRO
(W.h.ich is hard coded as 0) is used for sysBus addresses between 1 COOO 0000

10-8 Digital Confidential

:::\{:::::·

d]:i:rnr·

:·:<::::::-:····

·=::::::::::::::::::~::

·.\)f/"

;~(\{·.·.·.·

~~~: c~~:s:ii: :~~~-~~:~i~e:~~;;~I~~·!3111hi!.~~~~
9

EISAIISA devices that require their 1/0 space to b.~difiih.e lower ~2'5t£:$]3, to
coexist with other devices that do not have\tbat restf.ifti~ht::..'l'he lower 256 KB

~~~::i'!n'::::h=~c~ s~a:.dif~1:;~~!-\~! ~;:to

PCI 110 address translation. Table 10-3 descrihej.::::m!:{g~neralfofi of the byte
enables, and the PCI address<2:0> from ~y~pus addtiij~)it>.,;~>.
·:·:;\~;:;:;.//?~::::::·:··.
·::::~{fit .-: ·:-:.:·:·
.:;:::::::::::::;::::=:::::::::::::::::::::::::=::::::::..

··:·:-:·:-:··

Table 10-3 PCI Sparse 110 Space eytf::::~natili::.~!~!f:~tlon
CPU
·:=:=::::{{:}::..
<:::::::;:: -:::::<~~~~:=-:·
CPU
Length

Address
<6:5>

Byte

!:::ss

' 't::::t\:.:1_.i:!:lll!l·:j)Jtu.

\f)ji~f)"[ \b , 'ifQ~J;iJ\\...

· :·:·. : :.:. ,, 011f'<'\t'·

11
Word

CPU Address<7>, 10
CPU Address<7>, 11

00
01

··::'\d]@i

CPU Address<7>, 01

0011

CPU Address<7>, 10

JI\::>:::01
·······

······

~.:ii·<_~·!\m

q!::.:_!.:,t,. _;,,::\:;,JJ> 1

~l'.~~~!illl!~i~'ij),~11;tt?l'ff
.·.·.·: : : :. (}{\,::~ii~~!ii'ii~l:::=::::...

. : : : ·=: :=·=-: : ., ·J:]~:::::!:+tpgwor<lll:!::::l:::tt::::.··=\g.lpword ii' ·::::=tg/?..

CPU Address<7>, 00

Illegal2

O,Q{).ii>=-: :\:.:,_.':,:i.:.:I<>
.-'·'.-'.·'.;'.·'.·'.·'."·

· -· ··· ··

··:·::::::::CPU Address<7>, 01

...,,,,<I.'U,::' tfa:10.o

u,,::

Tribyte

PCI Address <2:11>

. t:t/\\{ 1110 .,.,,,<tt:::!i:ij::ct>u Address<7>, oo

oo
.:(/too

j\lllR'liifrL

1000

CPU Address<7>, 00

0001
Illegal

CPU Address<7>, 01
2

Illegal2
0000

Illegal2

11
11

Illegal2
0000

CPU Address<7>, 00

000

. :/M~Yie enable set to 0 indicates that byte lane carries meaningful data.

''':\j{/l){J: ..·.

:m::,'":::~ese combinations are architecturally illegal. If there is an access with this combination of

·::':''\:;:>>t''{ \t/address<6:3>, the 21071-DA will respond to the transactions but the results are unpredictable.
.·.·.·.·.·-:::-:-·.·.·.-.

Digital Confidential 10-9

Warning

:::::::::::::::;::\

..·:::::::::::::·

~i;lili!M:w~ ;;~ifili t

Quadword accesses to this PCI sparse 1/0 space
;
longword burst on the PCI. PCI devices cannot supppffl)fii~§@gAµ_ 1/0
space.
..:::L<,>t
·-:·:<t.:_t.:_::t::·:::.·::.:::__: ·_: ·: : : t: : -: .:..__::::.::,-::·:.:_:·_::::·

.-:=~~~{:~;}~{}{:.

·.;:.:-:-::;:;:::::;:::;::::;:·

··:::::··

Figure 10-2 PCI 1/0 Space Address Translation

Length in Bytes
tt>ngword Address
(Refer to Table for Translation)

HAXRO

.-:·:·:..

.;;:::::::;::: ···:·:·:·····

·.:-:.:-:.:-:-:- :-:-:;:····

.... :::;:::;:::;:::: 03

~ ..... , .....

;"...,~ .......

~·-~Tohle fo<T<M•-)
03

Address Translation for Remaining 16 MB to 64 KB of Pel 110 Space
W·03124·TIO

.-:::::::::::{:::::=:=:
:::;:;:-:

"\}\?

.·.:-:-:.::::::::.:-:· ··.·.·.·.·.·.;/::;:;:••••.·.•.·.·

·:-:·:-:···.·:·:·:·:·:-:·.·..
·<:=:::;:;:;:;:·:-:-:-:-::;:;:::::;.

::::lI1b~1.1.4'\\])ECchlp 2107:1.:'bA CSR Space • 1 AOOO 0000 •. 1 AFFF FFFF
:::::::::::::::}:
<{> ::=:::::::;::.
·::::::::1:::: ;:::::{:t

.:.~l\.the 21071-DA CSRs are mapped in the DECchip 21071-DA CSR space. The
;:;:::}}21671-DA chip responds to all accesses in this space.
:.:. "}}/.

··:::::::::::::;::::::

10-10 Digital Confidential

.:::::::i:ii:i::::!l!:l\[j\:j!·::::::::::::::::::::::::·.

. t::tt? ·: : : : : : : : :;:;: : : : : :;: :;.

10.1.1.s PCI Interrupt Acknowledge/Special Cycle Space • 1 BOOQ

®~'*i1l::::111~;i!W
1

!'::d access this space causes an interrupt ackno~jlji;·f~~!,IB~i.

to
The byte enable generation mechanism is based on..J~,ggfess<6:·3;@U#J\j1'" the
same as that of the PCI sparse 110 space .. :Refer tcdtfibl~:J0-3. Thetaddress is
a don't care during this transaction.
.:/f:i:m>=
·=-=:/:\ji1\!]!\i\lt:,...
..

A write access to this space causes a sp~~iif 9.Y¢l~t9.P th:~:::Pi~~:·:Wh~ address and
byte enables are don't care during this transa8tH,9.P.ll\t,:,..
· :-:::=:::::;ur=.

···::::::rr~~If\j~t~}::-==·
·:::·:-:-:-:· .·'.·:·:;::::::::::;:·
NQ.t'-:::t:::}\::.
.: =: : : : =: =: : ;:;:;: : : :;:=: :
Software must use an STL instruel6~Ft6fanitiate. th;·~:~{transactions.

~i~~ ~~~on will resul\:!I!~;: lori~~tJrst on the PCI,
..

=:::::.·.·.··:::::::::::::~{)\::: .·.·.·.

f'e&::QQ(lo ..

··:;:::;:::·

·.·.·.·:·.·

10.1.1.6 PCI Configuration $.P.@Ce 1 "FF.ff FFFF
A read or write accij~~!iiit6 .this s.p,~~iji!:~~g~~:~ a configuration read or write cycle

~~::ea~~~s~4&:!!~11ti~~:ra:~~~n-;!~:; :~~~s a:i~:ss

transferred (ref~fi:t~WJ.'~ble 1023)~\i(ijp~:tAik31:24> are forced to zero during the
address phase. AD~}\;PiM1cr.e obtm~!~::fjom HAXR2< 1:0>.
There are PCI configrif~ti.ijtj!i.~~d a~~f write commands. There are two classes
of targets-deyj~g~t9.n,.the:::pftm~W::· PCI bus and peripherals on hierarchical
(buffered, s~f;i.).#9.iify)::::~PI bus:~s}that are accessed via bridge chips. The
usage of tl}~filddre.~~:::~liiri.gg PCI configuration cycles varies depending on
the intendi~Ut~rg~tj)f thi:::i®.nfiguration cycle.

Peripl\.~r.~1Ji:::1f~\[\ii~l~cteq:::l#.fing a PCI configuration cycle if their IDSEL# pin

:i~lt1is~~••r.~:e~:~~~a~~2~ ::~!f;~=~:wi::: ::i!~i:nd

th~{P.inP.h.~ral's 256-byte configuration address space. Accesses can use byte
..,Ji/li\~il\::W.aski(\\]?:~npb.erals that integrate multiple functional units (for example, SCSI

•. '.;;[i1j!!iJi l\il!li:~:tlilo~~v;;e~:n::~;:i :a::i~~:~:c~ :;~:~!!::~s~~~~

::¥.\4.Qress bits <:h:ll> are used to generate IDSEL#s. Typically, the IDSEL#
': : .;.: :.: : : : :;=;: :=:;.,.,.;.
:::Ja~~rf of each PCI peripheral is connected to a unique address line. This requires
"'':\l\\\j\\f{}\:\):::/J::n::j~hat only one bit of AD<31:11> is asserted in a given cycle. The 21071-DA chip
...·..··.-.:-.:.:;;::;;;··;:,/\Htf9rces O's on AD<31:24> during configuration cycles; therefore, only AD<23:11>
t\=]t!ean,.be used to send out IDSEL#s.
::::,: ===:=:::::::===-·

··.·.·:.:=::::::::::::-::;:::;:;:.
·.·.·

Digital Confidential 10-11

.·.·::::::::::::::::::::::::·

: : ·~-=-~.'-~-'-~-'-~-=.)>?
.··tf=t=:::::::·::-.
f ~f~(~}:;:;..

·:·:·:·:·:-:-:-:-:
.·:·:·:-:-:-:-:-:-·
.-::::::::::;:;:::·

···-:-:-:-:···-·.·.····
·:·:·:·:····-:-:-::::;::::;:-:.:-:-:·:···
'•'.•"·'.·'.·:-:-:-:-:-:.:;'.;'.;'.

:!:.'~_-.:_:,.~,::·_::_~:·:.:':.·:_':.~:~_-:·_.::,.:_} _Jttf
:\:Jt "::t:=:.,:::i:i·::::::-=-..

...

:;:>:·:-:-:

If the PCI cycle is a configuration read or write cycle but . .~:d.Qress blt,~::::@.!;.Q>i!j.::i:::::
are 01, then a device on a hierarchical bus is being sel~mg\[?~iA:Jl Pdi!IQJ~]}?
bridge chip. This cycle will be accepted by a PCI/PCI J~!ljgef(9.~fa~tPP.ailitiMi. to
its secondary PCI interface. During this cycle, AD<~:~l~> sele=H/:ifafigqµe bus
number, AD<15:8> select a device on that bus (typi~~-~y\P,ecoded h}Htl:~:--target
bridge to generate IDSEL#s), and AD<7:~i?t§:~lect ~Flqnmv9.rd in the device's
configuration register space.
=<=<::?/" ,.,: : : : : : .,.,.
.. ,,':'\::::J:li:::l::i[.i:i:@tt=

Each PCI-to-PCI bridge device can be configtit~ij!:i@.~kPOI cortfllit.ation cycles
on it's primary PCI interface. Configuration paramiU.r~t:iµ the·=-=PCI-to-PCI
bridge will identify the bus number for it£.;./f.m~p~daey'=:P.gJ[::mterface and a range
of bus numbers that may exist hierarcffif:@).Jy::~W,d it~"====<{\:?"
If the bus number of the configuratiQJ,:.j~~le. riiitlii.ttb.~ bus number of the
bridge chips secondary PCI inter(~~i.~:@h~Q. it will lfitijfb'ept the configuration
cycle, decode it, and generate a eQ~:}i~ii.fim.!t~tion cycle with AD<l:O> equal to

::ii:,;~ ::~n!i~! ~:::lit1:~:~1£~d:h~~:::~!:e~ri:~~

the bridge passes tl)~~{ICI corifiguf3.t~~n.. cycle oii?unmodified (AD<l:O> =01). It
will be intercepted ''anij''''d~¢9ped l)ytQ):JiqW».:.~~ream bridge.

;:!~~o!1r•teJ~,li8l~~ :f;}liluring
··::::::::::::;:::::)::;:::::::::-:-.

. . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . .

:::: : (

the address phase of a

.~ :~ .~ ;~.!_'.: :;~ .~. :~-~-=~ .~. :~-~ :~ .~ :~ .~ -~
[ ·.' ,;

,: :.:

i,_=.'

,' ,=.=,: .= ·" .

··,===/=:\\?\))=Definition
Local

Forced to 0 by the 2i071-DA chip.
Can be used for IDSEL# or don't cares. Typically,
the IDSEL# pin of each device is connec1:ed to a
different address line. This requires that only
one bit of this field is asserted in a given cycle.
Function select (1 of 8).
Regis1:er select.

..·.;.::::;:::::._.
.. ;:::::::::::;::::;~~}: :::::::··:...·.

.·::::::::::::::::::::: .·.-.:_::::::::::.:-:·:-:-:-:-:-:-:-:·.

:::::::::= ····· .... ": ''\{fUij,o1:e

Don't cares will be forced to 0 by the 21071-DA
chip.

.-:-:-:-:·:::::::::::·:

<23:16>

Bus number.

(continued on next page)

10-12 Digital Confidential

Bus Hierarchy

AD bits

Definition

<15:11>

Device number.

<10:8>

<7:2>
<1:0>
··::::;::;:;:::::;

10.1.2 PCI To Physical Memory Addre~jggii@t::::::,.. _ .:::3::::i}!i :i>
Incoming 32-bit PCI memory address~ji:i~iv~:::~:::)it~m.app~'d to the 34-bit

physical memory addresses. The 2tQ1:it.;pA chipf~J.iaw~ttwo regions in PCI
memory space to be mapped to sy~J.~m}]fu.~piory With:(ttvo programmable
address windows. The mapping f.i9.jiFtH~?IC!J~.ddress to the physical address
can be direct (physical mappi~g~:}#:ith an::;:e~t.@ii.~!9.P. register) or scatter/gather
mapped (virtual). Th.~~e two::~(jg~$~twindovvs\'fe referred to as the PCI target
windows. Each wi~di!f":ha..s thi~:i)t~m~W.:rs ass<>"ciated with it. These are:
• PCI base regis~;~:::::?· :.t~?~?-,-:::_:.
··:::?)J::J:itiikt,.:.
·::::::::··

•

PCI mask.:,;~~!~[.

•

Translated

··::::::::/)!lm::!·i!!f):::::_t. ·..e
. . .r.

hi§'ij_::_·,_::_:r_::_·._:;_:_:e_:_:,_:__:·g,_:_
_
.._·::_s_··
...

t:t.0

·=:=:;:::::::)~}}?'

·.;.·. ·.·.·.

·.):/:)//:
. .··
··::::'.\(({/

Digital Confidential 10-13

Table 10-5 PCI Target Window Enables
pcl_Maskc31 :20>1

Size of Window

0000 0000 0000

1 Megabyte

0000 0000 0001
0000 0000 0011

2 Megabytes
4 Megabytes

0000 0000 0111

8 Megabytes

0000 0000' 1111

16 Megabytes

0000 00011111

32 Megabytes

0000 0011 1111

64 Megabytes

;::::::;:;:;::::.·.·

0000 0111 1111
0000 1111 1111
0001 11111111

0011 1111 1111

0111 11111111

111111111111

Note - - - - - - - - - - -

10-14 Digital Confidential

Figure 1o-a PCI Target Window Compare

I n-1

I 19

PCI Address

PCI Base
Register

PCI Mask
Register

~I) ....L ;J\ii\)!lili~l·'8Jmines n)
-:-:-:-·-;.:-:-::::;::::·:
-:-:.:.:-:-:-:-:-:- ::::::;::::::.

:.:-:-:-:·:::.:-::;.

LJ-03126-TIO

When an ad4.r~$$:l]it~~b::-oc~J.f~:::\With a PCI target ~indow, the 21071-DA chip
translates th.~i:i32:bi.tHec·1 ~<!dress to a 34-bit processor byte address (actually
a 29-bit h~~word/~adre~~l~\ The translated address is generated in one of two
ways as dJti.nmd~~ifby th.ifrfoatter/gather bit of the window's PCI base register.
If the:\~~~~ltt~;}l~ltrbitl-~i:l::6Ieared, the DMA address is direct mapped, and

the.ttr~n~lated addies~Ht generated by concatenating bits from the matching

wfi!'i~\W~\translated base register with bits from the incoming PCI address.

· •·•· · · :. ·11li'l\'£f~9';:;,~:!e:s::te~~:S,.:::ib!!::!1~i:dtraTd:-::iasm:~:~ster

::<:>>>':: ·--::::::n~_:'.h_;:_;~_::J_.:
__._e 10-6~\:'{ttJ>
·-:·:·...
:.::::;::··

Note - - - - - - - - - - ··:::::::::::?!?' ' ·· ·:·: : : :·
The unused bits of the translated base register as indicated in
·.·.··::::~;/~;/~;~;~;:::{:=::::/:=::·: .. Table 10-6 must be cleared for proper operation. Because system
····::::::;::jf:: }{\:m_emory is located in the lower half of the CPU address space, address

:\{f:{{f/j~~~(\t::..

Digital Confidential 10-15

:-::=::;:;:·=·

·,_·.=·.·,·_.=·-~·,:,~_=:~:i_,·~.=·.=~:_.=·:'.::=·::.=:·:= .'=;~_,i:~_.='_.:=:~:.':·_,:~:.
-.: .:.

rr!~~~~~~:::::-

·.·<~i~trr

.:'.::··:·==\(r~~{:=·
::::::::::::::.

Table 1Q-6 PCI Target Address TranslatjpJ:t~ Dlre(~FM~. (Scatter/Gather
Mapping Disabled)
==: : : =t-.: : =·
··: : :.:.:.: :.:.:.:.-,:,:,:,:,.,.,.
··-:::;:::··

:}'.:'.'.:;'.:)::;.,

pcl_Mask<31 :20>

0000 0000 0000
t_Base<32:20> :pci_Aq9r.~ss<l9~'5$\]I:=:tlH:t
t_Base<32:21> :pcM4tl--~11frR~5> .. '::{{{:} tt=
0000 0000 0001
0000 0000 0011
t_Base<32:22> :1>4f3ddr~~igi!~l~L
.
···:·:·:·:····
···.·.·.·.···.-.·.·.·.·.·.·.···
0000 0000 0111
t_Base<32:23.rH:P:fil~~dress<2'2~~ij!\:~rnr=·
0000 0000 1111
t_Base<32:~~*!\,~lkii.4~"~~~-<23:5>··=·=-·
0000 0001 1111
t_Base<~r1m!i::•=pci_XJaf'l11~s>
0000 0011 1111
::::~"'~ase<S~ffi"f:a:lre~-Address~J5:5>
0000 0111 1111
·=·===.)¥1B~~<32:275:!it~ill44.dress<26:5>
0000 11111111
. . ,'t_B.@~~f:g~,~~> ;~ilij~f:ess<27:5>
00011111 1111 /. -·· ==-=· t_B~~~$g~~t;pci_Address<28:5>
00111111 1111 ·====::r::::::]::]::th~e<a2frJo~::-~~faAddress<29:5>
01111111 1111
·-====:=<'£]t\g~$~g:31;=\ffej_Address<30:5>
1111 1111 1111 . -===-==-= ==::.-_.t_B~ij~jg~k:~i_Address<31:5>
If the scatt~flf~ti;.f: ::·b~i ~~("~et, then the translated address is generated by
a table lool#P:~. Tfi~Hncom~ng PCI address is used to index a table stored

:::i11i~11f~!: ~~e:u~ga:.i~:::t::t~:t::r~::

map
taql'-~:::O:J.ltts of tii~Pitfojmhig PCI address are used as an offset from the base of

theft.ib.t.~~==··
The map entry provides the physical address of the page.
····:·:·:·:·::::;:;:;:::::::::::::::::·.·.

. ,.,:;:;:,:=·:=·= ::::::EI:::::;~~ch====§di,Jt~f.lg@ther map entry maps an 8 KB page of PCI address space into
·=·= = = ==: :-:·=·=· · =:'<:${)j~fit~ KB ·pa:gj:)?f::~he processor's address space. Each scatter/gather map entry
<::'\t:.:'t'=
\~i$~\quadwordJ}Each entry has an valid bit in bit position 0. Address bit <13>
-:· :==-==·: -:.
Jl$.iJ~i bit position 1 of the map entry. Because the DECchip 21071-AA and
==: : : : =: : :==: : : ===-= . <f:!:QECchip 21072-AA chipsets implement only valid memory addresses up to 6
· · =·=-=·=-=·==·=· }::J!]§fGB, bits <63:21> of the scatter/gather map entry should be programmed to 0.
-====t::::,=:::::::::··::::::::1:::Q~ts <20: 1> of the scatter/gather entry are used to generate the physical page
··==:=:=:= .:[:[\2\\\\i.a.dr~ss. This is appended to the bits<12:5> of the incoming PCI address to
-·=·==:::-~fate the memory address that needs to go out on the sysBus. Figure 10-4
sliMvs the scatter/gather map entry.
10-16 Digital Confidential

.;::::=::::::=::::·:·.

·:::;.: ..
.·:::::::::;:::::::::;:;:;:::::::::::::::·.·
.. :;:::::~:::~:~::::::::~:~:~:~:~:~:::::::::::::i:~:::::: ..

The size of the scatrer/gather map table is determined

byJh~ :~!~:"rlll w
11

::ti:n::;:;g::::~1:i~e1!~~'::ks;:::e::i:~1l'8i:lli!•!:~
:!>~~ ~~:~~J;e!'1:::~:;:: ;:1:~~~~d frodJ;,~lslated'tlf,'jlfster
Table 10-7 Scatter/Gather Map Address
pci_Mask<31 :20>

Scatter/
Gather Map
Table Size

0000 1111 1111

t:Base<32:18> :pci_Address<27:13>

~:~ ~~~~ ~~~iii! ;t;!'llll~K.IJv '

t_Base<32: 19> :pci_Address<28: 13>

01111111

t_Base<32:21> :pci_Address<30: 13>

tiHmr

.<::::::][!~ M.ti>
:-:·:·:.:·:-:.:.:·:·
'.·'.-'.·:;:;:;:::::
'"·>:·:<:
1111 l~:E 111.i:iht:::::'.:::::::/:::- 4 ~:::/

t_Base<32:20> :pci_Address<29: 13>
t_Base<32:22> :pci_Address<31: 13>

:\)·\:··:-=-=·=·
.. :::::::::=;::: :::::::::)~~{:;..

Digital Confidential 10-17

Figure 10-4 Scatter/Gather Map Page Table Entry In Memory

'----------)

.-:/:(\:'\\:·.

-= = = = = -= = = = = = = = = = = = =/= = · ·.

:::<+?:?\\::::;::::;.

..,=:=:=:=: :=:=:=·:· Reserved

~=:~~::1~=:::1:::~::~~·i1.1~;,:~::~~:~
I I I I I I I I I I I I I I I I I Igf:~::1:~:1i~:1i~lRIPI I°F:l:i.·1::6l I I I
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

33 32

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

. ,.:-: : : :

··- == . ==:3c: .:.: : : \=:==='=.·.

0 0 0

;

---------------=lfl.~J_::~:i!_:,:.:=-~=.=;=_<•. .,,___ _· _-====:-=/-(: _:=:_:=:=·_______ ReMrved
·::::;::::;:;::::}}'.;'.;}'.;::::.
...:,::;:;::::::::::::::::::::::\::::..

.·::::::::::::::·:·.
.·:=:· :·:....

W-03290-TIO

~~!!~s~~i~;~~\1fi~~~!!~~~~:.dress physical address
to

The process is ·:~mrJllaw$k.

<====: : : : =t .·. :===: =:· · =·===. ·

th~:::P.l~l-=#.~9r~s:=·=~;~:::~sed directly to generate the page offset.

•

Bits <12:2> of

•

The relevm·i.#l~i:M/9.f.. th~\P:¢.!Ji::=i,ddress (as specified by the window mask
register~:rn4.'-P.~rl~~g:;=On . the "'sfae of the window) are used to generate the
offset i#.t.9-iJ;he .§#.~iler.f.iAther map.
-::::::::::::::;::-:

:::::::::::=::::::·.

The rel~viht{b~ls of tb.i);ranslated base register indicate the base address
of::ib.'-:·=·seijt~tfifo~th~ri!im~p.
• _.,Jthi.·,:~ap b~~it:tii.\~ti6~~:~ded to the map offset to generate the address of the
-=<?iP.fri.~ponding scatter/gather entry.
.··?==::'. ;;:7y~~\}:)t. ··-=~~:ij:~j:~~Q.;:!?. of the map entry are· used to generate the physical page
.. /)\::::::==·=·:-= ==:==:=;::::rnt::\::::t,,addre=~;KwJM~h is appended to the page offset to generate the PCI address .
•

.. ::::::::::::::::::::::·
.·/~~:):;:::::::::::
........

:::·:······

··.·.·.·.·.·.··:·:-:·:·:-:.:-:;::::;:::::;::··

··::::::;::::::::::::::::::::{:=::

10-18 Digital Confidential

Figure 10-5 Scatter/Gather Map Translation of PCI to sysBus A~~J!~S
I 31

PCI Add-

Pe•~•••:~ N•-

I 12

Offs:]f'li!~~ll,1~1lJltl~iltr

Compare

33
sys Bus
Base Address
(Translated
Base Register)

~Niii~l'~fl!lt

t_Base

~----....,...----_,.._···~-==·=:.::::::::::\>

. :-:-

~:{~f~\\ .~:~::.:.

:~:\}}~::--

...

33
Scatter/Gather
Map Address
Driven on
sys Bus

01 I

::::::::::

::::::::::::::::

:::::::::::::::::::::::::::::::
::::::.:::::::::::::::::::::::::
::::::::::::::::::::::::::::::::
::::::::::::::::::::::::::::::::::::

sysBus Page Number ::: :::

Offset

W-03127-TIO

Digital Confidential 10-19

10.2 DECchip 21071-DA Internal Registers

=~~:::~=d~::
Registers ccsRsl addresse~;Ji!!:~~llltlt~'.•;J~.
All registers are longword, and are
on
boundarie$Xaddress

10.2.1

addres~_ed
c~~~~Iim~
<4:2> must be 0). Writes to read-only re.m!~t¢rs do ·ii&tt~m:ii.•~J~rrors and are
acknowledged as normal. Only O's shout<Fl).e' wntt.~n to'.Ui.~p~~m~d bits within

a register. Registers are initialized as specifi~d.{!P.\\:th~-- detrul~:::q~scriptions in
this chapter. Addresses in CSR space which ar~''''ni.t:Ui~ified H~re should not
be read or written.
...
· =·==t t=r=:=: : :=:==··.:-;-·}:\=~=tt}::=:·

Address (hex)

Name

·. ·. ·-:·:·~-=···:·.
·:::;:.:-:

~~lif:j!!lr~ster

1AOOO0000
(DCSRJ
1AOOO0020
1AOOO0040
=})}~ysBu~=-=~t-i!.~4r~.ss regi;fu~ (SEAR)
1AOOO0060
··::::=:{ti_l,_ :_µffimy regi~fitt:l1itt::::.
·:·.·:·:·:-:.:.:·.·::::::;:;::·:··
bui.m¥@~_ster2···=:::=====·=·=·=-=
1AOOO0080 .-:.:·:::.
=: =: :=:=: :=: :=:=:=: : : ==: .= -.·=.· .D
.. um~ri'y' \t_·_: .e_- .=_: _·._6.i_._:·_=_'ste_.:.·,_:.-,_-.=_.'·:_.··.=.r.·. .3. . ..
1 AOOO OOAO -===·=·:-:::::::::;:::::::::;::::::
.·=======:==:·=:=.·):j:~fflt:~!ated':M~~:\:P-register
1 AOOO OOCO
1 AOOO OOEO
·-=~~~~~'fthase 2 register
1AOOO0100 :,·,:_. :,:,:,:,:,:i,l_:_:_.:. :))!:1-J):> ,pci.'Biiffl_::-~::+egister
1 AOOO 0120.//
.===:=====:=::::n::::):::J?~f:=:base =2· register
1AOOO0140=:1:=](
.(}\t' P._C.:_=.·_:_:_r_·_._.=_:: ··,_,·,:_mask 1 remster
.......... ·.·.·.·.·.
:-:-:-:;::;:::::·
Ct ...
o.~

~ ~~~6Jii:i\l:lil11ll\\,gi;;;;l:S!::::::on mgister o <HAXROJ

1 AooJ.:\ij[Ao.

·-=·===::::::r:/L Host address extension register 1 (HAXRl)

_. .. ..... _ t"'Ah4~-i~i@R::=:.,., , , :; :·:·: ~ : '@}fj\\l::AOO<ftfii}.q::\::jl:l::=:\t::::,.
..... .. ·.·.·.·==:::::tmEilooo 020H ::-:-:-:-:-:-:-:-:;:;:-:
···· t:u:r=
.=j:\:Aboo 0220 ·-======:=====
<:tt_.J:i!lll:I;;: :/> .-==<\=il:_i)::}(ooo 0240
· =======:··::::;:;:::::;:::>:·:
: : : =:=: : : : .. _:_: _ : _W_: _:_:.-_:_:_~.: _:_·: 1= = · AOOO 0260
:::::;::::::::

...:::::::;::::::

·····.··.·.·.·.·.:-::::~:}:...;.

·-=::;::~~\~~\\}~\~:=::·

10-20 Digital Confidential

Host address extension register 2 (HAXR2)
PCI master lat.ency timer (PMLT)
TLB tag 0 register
TLB tag 1 regist.er
TLB tag 2 register
TLB tag 3 re~ster
(continued on next page)

Address (hex)

Name

1AOOO0280

TLB tag 4 register

1AOOO02AO

TLB tag 5 register ./\\:=:·..
TLB tag 6 registet=:@l\i\J?.

1AOOO02CO
1AOOO02EO
1AOOO0300

··=::::::::::::::::::::::::::::··

TLB tag 7 register
TLB data 0 register

1AOOO0320
1AOOO0340
1AOOO0360
1AOOO0380
1AOOO03AO
1AOOO03CO
1AOOO03EO
1 AOOO 0400
.. -:·:·:.:-:·:·:·:·.·-:-:-:-:·:·:·.·.

Dummy registers are CSR$.:i!:th~tJ1ave no side effects on writes, and return O's
on reads. Wtj:tj~\'=~&::::tb.~~e r~gf$t~fs· can be used to pack the DECchip 21064
write buffer$.\!:~t~i/pf'(iy~p-t'=m~_rging<of sparse space 1/0 writes. Software will not
have to useIMBs
insf.ihctfohs
between writes if this mechanism is used.
:-:;:;:;:::::::::;:·
.. ::::··.·.·.·.·.·.·
:::·········::::<
'.::::::::::::::::;:;.

10.2.2.2 01agnost1C.~]lontrofand::\$tatus Register (DCSR> - 1 Aooo 0000 (HEX>

~-~ t!!rdtl~. ~e?~::;:~~:!~~::~~~~es, and reports
.·.·.··.·.:-:·:::::::::::::;:;.,

c;m~l;l:l)l,l!l;lD,11t

Digital Confidential 10-21

Figure 10-6
31 30 29 28 27 26 25 24 23 22 21

tEnb

Reserved
pEnb
---dCEI
~--- Reserved
~;;;;;;---ioRT

lost
_ _..__ _ _ Reserved

....____..~...---~,__

....,.....-----dDPE
~,:,:------ iOPE
::::,."----~,;,;,;.o.----- tAbt
~~---"'--------nDev

··t:::;;;;4444~,--------------cMRD
~~------------uMRD

1
t.=:=:=:=:· - - - - . . - . . . ........

~---~;;;;:;; ;;;.:;;,:.;...__------ iPTL

~~-----.;,;,;,;;...-------- mErr
~~~-------------dByp

~....,....,,---~~~ o;,,--------------~pCmd
~---------Reserved

.__ _ _ _ _ _ _ __.,.,,.,.---~~~;,.,------'~~----------pass2
·>:····· ·:·:·:-:-:-.

··.·.·

.·.·.·.·.·.·.·.·.·.·.··

W-03084· TIO

Table 10-9 Dlagnostlb::qpJ'ln9tancfStatus Register
Description

Chip version reads low on passl, and high on
pass2
The pCmd field indicates the PCI cycle type
when a PCI-initiated error is logged in the
DCSR. This field is only valid when iPTL,
nDev, tAbt or iOPE errors are set
(continued on next page)

10-22 Digital Confidential

-:Jt]I:llt:::=::::,.

;;iti 2·········:!!!l~1llll!~tl&r

Table 10-9 (Colli.) Diagnostic Control and Status

Regi!tttf}clil~lllli t1~i!;H;• •)•_:[·_i_1.•.ry
.•_. .

.·:·:·:·:·:-:-:·:·:·:·:·:·:·:·:·:·:-:·.

Fie Id

Extent

'fype,
Reset

dByp<l:O>

<17:16>

RW, O

··:·:::::::::::'.:.:-:.;.;.·.;.

Description
The <ljsable re4.li~ilAAs bits ar~'-\iijia to
conttf.kt-;he orderitig)}f::;gpJ. Initiated memory
read~fWitltx~_spect l&PP.l*W.tiated memory
writes~ ThlSUi~ld has tnreidnooes:
Value ··:::MiJl·,:.\·jj'!\j)j\\ji::::::P~s;~ti6n
.~~~~~~~~~

1I~l!'!1 11·'1ii1;1::'.'.!~;:§~Jr~k

.::::::::::i{:JI}\

··-:::::::;:/:)(/hexaword address of the

.·-:-:-:-:·: :-- read does not match that
of the buffered writes.
The address comparison
is done across address
bits <31:6>.

No
Bypass

In this mode, DMA reads
will bypass buffered
memory writes if the
address within the page
does not match that
of the buffered DMA
writes. The address
comparison is done across
bits <12:6>.
In this mode, DMA read
bypassing is completely
disabled. DMA reads
will be ordered with
respect to DMA writes
originating on the PCI.
(continued on next page)

Digital Confidential 10-23

Table 10-9 (Cont.) Diagnostic Control and Status Regl!!!!\t>:::.
Field

Extent

Type,
Reset

Description
.::::::::::;:::::::::::::

mErr

RWC,O

The irt.emory e@9#:(m~rr) bit is . ·~~~:::*hen
the . ,gJQf:l-DA chij(f.~tM:V~.s an error code
in tfofiOOA~)t<l:O:>·:::fiijli.J#.\~~~ponse to
a memocyj~~#~~:~· sysAdf:~i?:;?:> for this
transactforf#(J9gg~:~ in tfaf~ysBus error
address regi.sti:ti.$.U~~"· This bit is not logged
if t_h~4ty~~us erroi%i®t~~ register is locked
byf~dit~fl9:µi.;. error~"?f:h.~/fost error bit is set

i#.ijtijadY/?{l])::

......

Iffth.e mErFBtkiria::either the cMRD or the
::::::Jijja,p bits a~~:::•m:::this indicates that the
..... :t:Jaddremt.for the niErr is lost.

iPTL

<14>

RWC,Q):\!ii~i. i./. ~::::l*li9.UJ.age Table Lookup (iPTL) bit

:.:.: :-:-:-:·:·:·:. is set wh~n/the longword scatter/gather
"":./(l:ifH\m.ap entij?being accessed is invalid. (See
· :::::;:lJJ:Jnkµr.e 10-4). AD<31:0> is logged in the the
"::;::;:pq~W~r address register, if it is not already
lock~~r·

":::::::t\:::;::::{"" \>,Jf the iPTL bit and any of the ioRT, iOPE,
<)(:/?})~pev, tAbt and dDPE bits are set, this
·::::\\indicates that the address for the iPTL is
·":fost.

uMRD

10-24 Digital Confidential

The Uncorrectable Memory Read Data
(uMRD) bit is set when an uncorrectable
error is encountered by the 21071-DA chip in
the data read from the DMA read buffer
in the 21071-BA chip to the 21071-DA
chip on a DMA read or a scatter/gather
read transaction. sysAdr<33:6> for this
transaction is logged in the sysBus error
address register<31:4> if the SEAR is not
locked.
(continued on next page)

Table 10-9 (Cont.) Diagnostic Control and Status Reg1$.J•r:t:::::::
...
.·:·'.·'.·:·:·:·:·'.·'.·:·:·:·:·:-:·:·:·:-..
Fie Id

Extent

"fYpe,
Reset

Description

cMRD

<12>

RWC,O

~e~~k:~~!~RD)
enc~&r~4.J:>y th~t219~iUDA. chip in the
data readdrmn:,.the DNb\)r~a::buffer in

;~:l!~~i~,.tl\~~~OJ!!~~r~~s:C~~

sysA.4.~9.:~:6> fof':tm$.M~t~saction is logged in

nDev

<11>

,::t;i:~titii~~iNbd,)eVice (rifiev) bit is set when

:':·. l\lf.. DEV.$$.Jii#~. not asserted in response to

./)}}}\ an IIO':f~dhm:·write transaction initiated on
\{jJ{l{t:Jhe PCI by{~he 21071-DA chip. AD<31:0> for
. . \{@Jll~b.i~. transaction is logged in the PCI error
88
31
.. /}}\,,:,..
.
:_:i:r)g'
.
reetgiAbosterrt< (tAb:O>t.) bit •s set when a PCI
. ::R.\Yq~(i:\t:·:-.
:4~
.. ..
· -:·:-:-:-:.:-:::::::::·:-:,::::::::\.,.:,._ slave:·:aeVice ends an 1/0 read or write trans·::::::v:::t\1\)~.~.tion using the PCI target abort protocol.
··.·.·
"'.\{{J:iD<31:0> for this transaction is logged in the
··::::::::::::·:.. :::=:=::::::::=::·:·.
··:·<Pel error address register<31:0>.

·-: :\:{:~Th;·;'.:'. ,: ~et·_·.:.i~.·.·~.: .~·.'.'·.':

tAbt

iOPE

RWC,O

~l.l~l.IY.~k:td~T:'f:fJ!~r~!~: !~!e
,:/:::)~1:~~~!'l~lr.rts::n:e::te~~EI (Disable

u:::.::::::::::::jj\.j::i:::::::::::. .

:,.i): : \: ;:>~w¢·-::'"":\)\(.
.i,~:\:m :.:-:· · aTheparity
1/0 Parity
Error in
(iOPE)
bit isphase
set when
error occurs
the data
of an

1/0 read or 1/0 write transaction. AD<31:0>
for this transaction is logged in the PCI error
address register<31:0>.
The DMA Data Parity Error (dDPE) bit is set
when a parity error occurs in the data phase
of a DMA transaction. AD<31:0> for this
transaction is logged in the PCI error address
register<31:0>.

MBZ
(continued on next page)

Digital Confidential 10-25

Table 10-9 (Cont.) Diagnostic Control and Status Regl!MMtf::\:,...
Fie Id

Extent

lost

Type,
Reset

Desc.rlptlon

RWC,O

~~"1\~:Y?!
coridifiih
.W.b~n the'='a'd.iti~.~br.~gister

correspoµmr.i49.. that ·enmf:]~Jocked
because of\ijfatMflm~s errort]Jnder those

~~r:,~::;~:~~-Ll~~~~~/e~~~~~~:sto
~illllli#::P:191·?~fr!:Z:~sa!~:::r still

riffihlns valid?fO'flthe initial error condition
. ::=::=:=t:J~i.~ated by'lfulf'~~r
bit already set.
····:·:·:·:····
0

.·.;.-.·.-.····.···········

Jl.!lll:·)··[\~f!l~~itc.Pb~~~a:e~e~!1!: ::a~rror

ioRT

<5>

Reserved

<4> :::::))t.[!:[:j[\i:)\:::::·~,~

dCEI

RWC, °,. :.
.JfJiF\ transifutj~ij:]~n the PCI. AD<31:0> is logged
..
?\@Flllt:Jn the PCl:ifror address register.

· · : :=: : : ):) :\1\l .l ! j:·:-.~1i·.i.!(\:~ :\:j: : : :,.

.4\19:):::

·>=:=::·:-:-:::':'):(::.,.

Wijj.ij\~he Disable Correctable Error Interrupt
(dCElfbit is set, correctable errors on DMA

·::::\{\:::::::::=·= \~~(\=:=r~ad data are not logged in the cMRD bit

·==:::::n::=/.\i(P.CSR12) and the address is not updated in
···==t:ttlie sysBus error address register. This bit
·only determines whether the error is logged
and if the processor is interrupted.
If the prefetch enable (pEnb) bit is set,
the sysBus master machine wiU enable
prefetching on DMA reads. This bit should be
self cleared following system reset and should
not be changed while DMA operations are
going on.

pEnb

RW,O

··:·::>:::::::::

.··:::{f)~~~~~~~~~~~~~~{\:::·.

10-26 Digital Confidential

When the TLB enable (tEnb) bit is set, the
entire translation buffer (TLB) is enabled.
When this bit is cleared, the TLB will be
turned off and subsequent scatter/gather
reads will not result in allocation of TLB
entries. Entries that were valid when the
tEnb bit was cleared will remain valid. To
invalidate valid entries, software must write
to the TBIA register.

10.2.2.3 PCI Error Address Register. 1 AOOO 0020 (HEX)

Figure 10-7 PCI Error Address Register

LJ-03086-TIO

Field

Extent

pci_Err<31:0>

<31:,Q.>

Th~===iamf~~s sent out on the PCI
··=='\Fftttl======. bus (AD<31:0>) as a result of an 1/0

ltQtg::\:\\:\lt:=:.

··=====t@l\llk~saction is stored here. This field logs
··=·==t'{Jt.bi)~ddress of the errors indicated by the

···=='n'J)ev, tAbt, iOPE, dDPE, iPTL, and iORT
bits in the DCSR. This register is valid
=·=·=·>=·=·=·=·=·.~·AH_. when one of these six error bits is set.
one of these six error bi ts is set, then a
subsequent nDev, tAbt, iOPE, dDPE, iPTL,
or iORT error will not update the address
logged in this register, and the lost bit in
DCSR is set.
pci_Err<31:0> are valid for nDev and
iPTL. Only pci_Err<31:5> are valid
for ioRT, tAbt, and iOPE errors that
occur during dense memory writes. For
ioRT, tAbt and iOPE errors on any other
transaction pci_Err<31:3> are valid. pci_
Err<31:6> are valid for dDPE errors.

Digital Confidential 10-27

Figure 10-8 sysBus Error Address Register
31

Field

Extent

sys_EIT<33:5>

<31:.4>

RQ~fQ]::U:fo::::.

Th~::iid~~s sent out on the sysBus.

i 11111i11;t1E;!:;~:~~:i:~J~:d

·-:-:::l)y:::the mEIT, uMRD, or cMRD bits in the

. '.· :::t~:~:~:)~:~:~~~~\?\)\::
···:::::::::::::::;:;::::: -:-:·:·:

Reserved

10-28 Digital Confidential

DCSR. This register is valid only when one
these three eITor bits is set. If one of
these three error bits is set, a subsequent
mErr, uMRD, or cMRD eITor will not
update the address logged in this register,
and the lost bit in DCSR is set.

10.2.2.5

Figure 10-9 Translated Base Registers 1·2
31

Field

Extent

t_Base<32:10>

<31:~>

If sditli#i~ther mapping is disabled t_
··-====\:ftflft:::=:·. Base speCifies the base CPU address of
··=====):f:ttf'the translated PCI address for the PCI
··====::::q1:rn~¢g~t window. If scatter/gather mapping
····===tsU~nabled t_Base specifies the base CPU
address for the scatter/gather map table
=:=:;::::::::;::::::::;::;::::::·--- the PCI target window.
-

RW-;p]1::::\,..

Reserved

Digital Confidential 10-29

10.2.2.6 PCI Base Registers 1-2. 1 AOOO 0100 and 1 AOOO 0120 <HJ;~)

.·::::::::;::::::;:;::::::::;....

.,<:::::>:,:tHf.::::Il'./.~~.~r.~I.~~=~::::. .
::::::'.:::::;:::::::::::·:·:·

;ttiliiil: '~'fQ[i,l!Ji>
· .·.·:·:·:·:-:

Figure 10-10 PCI ease Registers 1-2

20 19 18 17 16 15 14 13 12 11 10 09 :~-.07 08 05 04·:~~#.i~f ~{~::::;:..

·.-.·.·.·

\'.:~,,.·TIO

::'.'.~~~'.~~~'.~~:'.::·:::::: -·-:::::::~:}){\{:~{}:;.:.:-:

Table 10-13 PCI Base Registers 1t~::J::::::::{
Field

Extent

pci_Base<31:20>

<31~0>
::::{{::::-:-.

R~p:::::::l\.:-

<t9~il{/" .JJ@\§}Y,O

wEnb

pci_B~~::'$pecifies the base address of the

·-:=::::::::::/:::::::::::::= :;:-:;.;-. PCI tatjtet window.

:·:·:·

···:;:::;.;'.::;:·.·.;:_:_:

"'.::;:::::{::l:i:::lvb.~n the Window Enable (wEnb) bit is

"'.":\@jijijfed, this PCI target window is disabled

:·:·:·:·.

and will not respond to PCI initiated

transfers. When wEnb is set, this PCI
··:::::::;:::::::=:::)\>target window is enabled and will respond
to PCI initiated transfers that hit in the
address range of the target window. This
bit should be disabled by the processor
(software) when modifying any of the PCI
target window registers (base, mask, or
translated base).

"""":::::::::t;:::::::::::::;: . · :.. .

When the scatter/gather Enable (sGEn)
bit is cleared, the PCI target window uses
direct mapping to translate a PCI address
to a CPU address. When this bit is set,
the PCI target window uses scatter/gather
mapping to translate a PCI address to a
CPU address .

sGEn
.·.·-:-::;:>=:-.

::::::;:;:;:;::::::··
<·-:.::::::::;:-

..:==::::::: ..
.-:·:-:-:.·.

·.···· ..

·.::\{) :::::'.:?~f~t
.. :-:-:-::::;:;:;:;:;:;::

MBZ
:::=::::::::
·.·.:-:-:-:.. ·.·.·.·.·: ..::;:;::· ..

·:::::::;:;::::::: ·····.··:··· -::::::::::::::::::::=::-·

·:·:·:·::::::::::::::: .. ::::::·:-:-:-:-·

·-:::-:.:::;:;:;:;:;:;:::~-:-:-:·:·····

10-30 Digital Confidential

Table 10-14
Fie Id

pci_Mask<31:20>

.;;S1:20> ··='='ftW'D

·= '"':==·.
·.·.·.·.

=:=:=::\::um:":::i:;:~:::J=?:·. .. .

:PciJ!M.i~k specifies the size of the PCI

targ~t window and is also used in the

··====tJ)t:Jt\:::,. translation of the PCI address to the
·=:'\}}:}::··:}pPU address.

Reserved

Digital Confidential 10-31

W-03011CJ.TIO

··=···

Table 10-1 s Host ,8!1res.s e:d~ijif9~\H~glste·r:'1
Field

R~O:i:::'::::: : : : : : . :-:. For CPU-initiated transactions to PCI

eAddr<4:0>

··:···:···:.:-:-:-:-:-:-:::::·:·:·:·:·.
···.·.·.·.·.·.·-:-:-:.:-:.:-:-:-:<:;.

·:·::::::\}{() memory, eAddr<4:0> are used as the upper
5 PCI address bits (AD<31:27> ).

Reserved

10.2.2.10 Host Ad(#.

=11:~1iif!e;::er 2 (HAXR2) - 1 AOOO 01CO (HEX)

This regis-f,::·~- ll.~~~Fto i.1~¢rate AD<31:24> on CPU-initiated transactions
::-:111i';tl!!~ also used to generate AD<l:O> during PCI
·'.·:::::=::::::·:·:·.·.··.·.·.·.·:·:·:·:·

;::;::::::::::::::::;::::::::::

.·.:-:-:;:::::'.:::·:·:····

Flg~m;a.__ 1~1::a,:1:MP.lt.Address Extension Register 2(HAXR2)
Jt:\::J::J~\.:::
"'::::::wrtw::j4::2a 22 212019 18 111a 15 14 13 12 1110 09 08 01oa0504 03 02 01 oo

;:!:;i'.'.'f 'l'.'ll'!H:: ~; ~iil'0 1°l 0 I I· I l l 1° I 1° l l I 1°1°I 1° I I
0

.:::-. :::::.::.:~:::-;.;.;.

::::::::;:;:::::::·>:··
-:::::::::::::::::::::::··

··=:\}=): :: : :::::
-:::::'.::/;'.:'.:::=:=:=··
··:::::::;:;:;;;;;:;t~>::::::::::::::::::::;/:".

10-32 Digital Confidential

0 0 0

vLI _ _ _ _ __

conl_Addr<rn>

Reserved
W-03091-TIO

Table 10-16 Host Address Extension Register 2
Fie Id

Extent

'fype,
Reset

eAddr<7:0>

<31:24>

RW,O

Reserved

<23:2>

MBZ

conf_Addr<l:O>

<1:0>

R\V,O

Description

Digital Confidential 10-33

10.2.2.11 PCI Master Latency Timer Register • 1 AOOOO 01 EO

Figure 10-14 Master Latency Timer Register

·>:::::::::-·.··

:;:::: ..
313029 28 27 26 25 24 23 22 212019 18 1716 1514 13 12 1110 09 08·:oit?'\:=?t~.;.:·.

I· I· I·I· 1·1·1·1· I· 1·1· I· l·I· l·l·I· I·I· l·l·l·hhl.. : :;~~t~~~~,t~>l
·:·:·:·:-:-::;::

W·03429·TIO

Table 10-17 PCI Master LateJ.jpy;,~[lmer
Rei~i@tt=·
.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.
··:·:.:-:-:-:-:-:-:-:-:·:
Fie Id

Reserved
pMLC<7:0>

.....,,<a1:s>··<=::tmMlJ.z,.
·-:-:-:.::::;::-: :-:.:-:-:-:-;.·.·.

·-::::::\?} .·.··:·:-:·:··-·.·.

10-34 Digital Confidential

pMLC<7:0> is loaded into the master
){l'}{):=:::Jatency timer register at the start of a
···=:::::=::::=::::::::===· PCI master transaction initiated by the
21071-DA chip. 1

. R\WQ}J>===··

These registers are read only.

Figure 10-15 TLB Tag Registers O·7
31

W-03092-TIO

FieId

Digital Confidential 10-35

10.2.2.13 TLB Data Registers 0-7. 1 AOOO 0300. 1 AOOO 03EO (H.g.x1

These registers are read only.

.f!I':\·11:::1:·:!.=!·!!:i=:::j.ii=:iilht==· ·
::=:=:::::::=:====··

·:-:·:·:·:::::·

·:·:=::::t.·~.~I.t.~t~.r~~~~r:::.
·.·.·.·

· :::::::::::tlj!\t:=.:1:.j:.:::\\\::::·

Figure 10-16 TLB Data Registers 0-7
2120

W-~TIO

..........

.·:-:.:·:.:..

Ext~.nt

Fie Id

Reserved
<~i.@.j; .=\::.:MBz==:\/@:::\\\:!\\\:·:\i\\='"·
cpu_Page<32:13> <20'a~.{!]}:B(M).
···=:f\{\B.t'ti:::<32:13> of the translated CPU
=========='=.
· ===:;: : : =: :==:==: : : ;: : =:=·.·
··==jd,dfess can be read or written through
.:{{ =;:;:;:;:\·:·.
·::::=:=::::::::::::::::::::::::::=:=-this bit field.
Reserved

. ··====:<~iji:[·lf::>==·. MBZ <::: :\il!Jl:.: .'J,:.=,·:·1.:.'.!.= ':·:·:· ·:.'·,·.:·.=: : :
·:·:·:·:-:.::::::::::::::::::::::::-..

·.·.·.·.·.:.;-:-:-:-:-:-:-:.::::...

10.2.2.14 Translation au.trer:Jnvaliaali=:::Att(TBIA). 1 Aooo 0400 (HEX)

10-36 Digital Confidential

DECchip 21071-DAfi't11.~llliQJlS and
rl'1J1in_:j_:_:_:_:_·_[=:~-::_::_:·:~-:.:: ,,,iag rams
__:_=. :,.:_:',;_,:,:'_,·_,_::_'._.'_._,,._._o_
•.., ·.·.:,:·
..
..

.. :::::~~~~::~:~:~::::::.

···-:;:;:·::·:·:·:·:·:-::;:;.;..

.,:::ltlttrn~~~IIl=t,,,:..

··:·:::·:·:-:-:-:.:-... ·.·.·-·

·.·. ·

;;i:~!::ed;~t~~ ~:e ~:~~iil\~:. t6ffe~~ij~¥71-DA chip from the
Throughout this chapter, the terfflj:=:'frii~#.!9..1J...and command are used
interchangeably. In general, 'b.ilb.~f leveflf.$.~i~.ons are composed of lower
level transactions, 01\pus comtn~'-i~~:,.,. For example, a DMA write transaction

~:s:~s:c~:.~;:::~~'llit~coffimand)

and asysBus DMA

11.1 CPU-lnitiated[@1fransacticH1s,. .
·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·

·.·.·.·.·-:-:-:-:-:-:-:-:-:-:-:-:-:-.-

The 21071-DA c:frifflt~~pppgs to CPQf,jf.Htiated transactions addressing PCI
space or the 21071-DA\Q§B:[:fil)~ce. tK addition to this, it also responds to
barrier, fetch, a.ndJ~~tchM'Yt.~W.niJmd fetchM transactions are acknowledged
immediatelyJ:,)yi:'g~~Wpg,,,cpuCA¢.i~fOK on ioCmd<2:0>; no further action is
taken.
.,:::;:::::>::::::::::-:-·.····.···;;;;;;;::;;;: ·.·
·.·.·
:-:-:-:-:

11.1.1

·-:-·-·.·.;.·.··

.·:}}:::::

Remote (ilu)§Pace'.-~!J.tJ> Read
• 11.i:\~\~ys~i~·~\ll.rr@~-::'~i~tinuously monitors the command and address

/\9.u/tlie sysBuM<Wh~h it detects a read block command and the address

=<t:!~i:t:~ni:l?,91 space, it generates the PCI address, byte enables, and the PCI
d~ig:fgih~:l:::.(PCI memory read, PCI 1/0 read, PCI configuration read, and

PCf'ffi•®.t. acknowledge), and notifies the PCI master state machine.
····:::::::::::::::::::::::::::::

PCflfiister state machine asserts the ReqL pin on the PCI, and waits
the bus to be granted to it. If the bus is parked with the 21071-DA
chip, that is, GntL already asserted, then the 21071-DA chip does not
assert ReqL.

Digital Confidential 11-1

·==: Jifj[ :[:·: :!:.:1.: :.:·:.·.:.: .:.:.::.:.:.n::::o=-..

. ttf)~?=··

•

aread system memory happens on the

::::=:::}: .·.

.}f:)~\::·:·:·::::::}:: ..

befo~ t)i~11~;1~:1i;;;~~?

If
to
PCI
machine has gained ownership of the PCI, the YO .r~i(t\j~iiftbe syi)J#.~H\~:mr
preempted by the 21071-DA chip. This is done tori.mveHti[\i.i.i.\m.9.cks''tfhm

;;;;~;,s=~e!v~:q~~si:~s ~~~()•~:~~~~1':;~~!~l:ent

:~C:s°:r~t:ei:~!~~!°~:1';e!~~~~r~&lf'~t;:,~ii~~~~;PA chips. The

•

The PCI master state machine waits f.9.r>.a r;~:~hh~j.::=ft9:m th.e PCI target
device.
. =.=.=: .=.:.:.:.:.:.:.:.=.,:
··=::::::::::::::::::<··::: ·
.;:{\{~\/}:·:;(/\)\:::-:-.

•

·:·:·::;::::·:··

When the target responds, the tr~jJhti6riltl:@~[\:y9mplet~ in different ways:

!~~~::~~~~:~n:!~~;-~'. th!ll~1'Pc1 master terminates

2. If the target aborts tq,¢\:\~tmisactiolF\\1$.ljj:ll.::·error, or a parity error is
found by the.,:gJ071-D1\rnff.~pJ~>.P. the r~MUdata, then the PCI master
terminates =:tu~#tr~saction;.f~ilt~~s the PCI, and when the data is
returned. to tli~· qgpJ:::m.i
err&P~$j:[ij~ged.
.·.·.·.·.:-;.·.·.·.·.·.·.:-:-:;:-·-·.
·.·.·.·.·.·.··:::<;:········
3. If the ~~g~t..., disc~rifi~¢f,$.:!:).p~ tra~'§i~tion, indicating that the master
should':fiijeyfr't!w, transiet.i~##~t,.a later time, then the PCI master
machine tef.~~$~~~~. the tf~~~etion, gives up the request for the
epiBus, goes bat~::.t9::jdl~, and"'"retries the transaction after the PCI bus
becomes..idle_._
··:=====: :'='"'"'"'_,.,.. -.·.· ·.·.

•

If, wherr9.~1£··l~J:l~~~ilabl::=:ff~~the PCI device, the epiBus has been granted
to the PPl?rnaste#in~C.b.ine, data is sent across the epiBus into the YO read
buffer 'i.AdLtl).~:::f:~que@il:f.or the epiBus is cleared. If the epiBus has not been
0

~lt!ll~~tt~~~~P1:~h::~!8"!1r::;~e~ ::! 2~;~gA

. Jth.lPf

A subs~quen~FPCI transaction addressed to the 21071-DA chip may
-=<Ii!f:!J~l{rdyL until the YO read data has been moved.

···;<(,!:11111f1lr.:r.:li.:·.~~.:·.i:~Ji'1.r.m:si:~~~n completes when the read data has been returned to the

·._·.·. -.
. ::;::=::~:?·

.:::::;::::.

···:·:-:::··

.-:-:-:-:·:.:.:. :::::::=:;:.
·-:-:.:::::::::·:·::;::·:::::·'.·'.·'

·.:-:::::::::::::·.<·:···· ..·
.·.-.·.·.·.:-:-:-·.·.·.··

...'.:::::~<:?-:·:··
:-:::·:::::·······

··-::::::::
···=::::::;: :-··::::::::;::::'.:
·-:·:·:·:·:-:·: :'.{{{::

11-2 Digital Confidential

. ::::}~rrm~~t~\::=:·.
/~~~j~~~~~~~~f)}f)\{)\:::::.
d\:::;il::::(' '

~~{~}}~~:\.

:.~.}/

\}_::_::.·_..

11.1.2

: \j.i : li:· :~: :j: : : :t> t: :·.·

.:::::::::::::::·

.,('.'.)'.{

}]lt

· :·=t_;: : .~.~.:_:,: : _.:·: ,:_::::1:1.·.j\:i:t:·
:::::::
..

~e:: :c~~:~:I/~~::: is detected on th~11llltirm~,!l~i!'.:sw
¢h!i>.

loaded into the 1/0 write buffer by the 21071-C1.\,.
The':'~).qg:t,fDf.\ chip
always has room to accomm_odate the data forJi~#.i!J/Q. write triih$i~ilon.
One transaction is queued to go out qzj::J-Oe Pdl~::::~4::jtb.~tsecond stalls on
the sysBus until the first is complet~qflj~~::::4ata fbit\tb~F~~~.Qnd write is
~°:::~.into the second entry of the I/O\vti~i!::~~):~.::.:whi~j:J!Ws as a holding

•

wrlt~Ma4d;:=~:~:;:=11~rk~

The address is loaded into the 110
1/0 write
request is posted to the PCI mast~r\!:$.~At~M~~~~J.;iine,".·"lnij)the transaction is

:;:io;~e::~

::e1!1C:::ise~s~~:flJ1.fldi)'1'!;~11 Stall on the sysBus,
:;::::

•

The PCI master state machi~jj:jji)$$¢.i@.l::\b.~ ReqL .iHn on the PCI, and waits
for the bus to be granted t9.:::.l.~i:/At thJiF~~~4i.me, a request is sent to the
epiBus arbiter to_._set the ::~t~~9.~ of th~'''i.p~Bfi.s from the 21071-BA chips
to the 21011-D4t~mP·
· ·-=:=::::=::r:=:=:rr:=:":::::····=::::::

• ~!!!=s:i:!~dllf~~~,.rl!;~~:s::,a:;~:::.~r a

CSR read-=ii:i!):~~l~:4 on the':'j~»,µ§ behind this write, it will be preempted
to allow Dl"A?r;i&:transaciforli/B.b:one DMA write transaction if the DMA
write buffer is rrili=i=t~:l"~Qmplete.'::::n:i>:

•

When the ~Gl:m~s~~:f),~ij_iijr~~:t ownership of the epiBus, two longwords of

t:!an~l!~~-~~~~fe\i:~:~~e!!~m~::~e!:~~1.!~:::~i°~~~e

PCI, th.!~#.=:::theJii:\ta iqJfie holding latches is lost and the arbitration has to
be _ perlQ.9¥'9\'\ighln ..:·.: :.):):!l : ji'

• wJ.iiP.==·t1~Mii.~gJ.!limQi$.ml{f~ceives the grant on· the PCI, it drives the address,

_.,J~9m#iand, iilid%ii~ifts FrameL on the PCI if the 1/0 write data is ready to
"''''{!jg:Q::::i9.l on the PCI in the following cycle (if the epiBus has been granted to
lhif\jfmbwaster for transferring 1/0 write data).

=·=·=·:·,,·=·=-=·=·:·=·.,._ ...

d~V,i.-l:ilh<al:O>, CBE1<3:0> and asserts FrameL. This allows the device
decode:':UMind acknowledge (assert DevselL). Data should be ready to be
on the PCI by that time.

As write data is sent out on PCI, subsequent longwords are unloaded from
the 1/0 write buffer into the PCI output latches through the epiData bus,
:===:=:::=::::::, ..........
the transaction is terminated.
& . .& &

Digital Confidential 11-3

.. ...
.·.· :·:·
·.·.·.·· . :-:-:· ·'.·'.·:·.·.·.···
.:::::::::}\:::::.:

··-:·:::::/(\:::::;. ·.;-:...

:-:-:-:·'.·'.·'.·

.::;::-·.;.;'.;'.·

/f t~~t?

•

·.·.-: : : :;:

.. ..,.,,,:::2:::tt\:::::' .
:.::::;::{:}:::::::.·

!;~:§~;tJ.~~;f~ii[:: ~Ii!;F~f4ili~1lir1!1·······
:c~e entire data transfer completesilfli,tran41~. ~rmin8Ud on the
··::::::\~?·"

.:::::~/

·.·.·.·.·.·.·.·.·.·.-.·.·.·.·. '.'.;.

· ·:~: : : :>.: : : : : :

11.1.3 CSR Space 110 Read

··<>]!'..;:,:;:>'"

!:~~:~~n:i~t~!?~~~~~~S!s
oi:h::::~=tif!~11~'11'.:i:t:ar~a;~::~:~
the 21071-DA CSRs.
,}f'<?X}?\'{)>·.

.,.,: : : : : : : -

~.-,i~!~''''~:~;.;iiJ.it.iP.cy,

Because CSR reads complete with
a CSR read
transaction is not preempted unl.~j~:::j~t:j:~$\qµeued 6eli~#d an 1/0 write to
the PCI which cannot complete Q.~j~ti$~))p(:]~)MA transactions on the PCI
directed toward DA No errorsJ!t~\)\detecied:\:~p,gpg
this transaction.
·····.·.:-:-·-·.····
···:.:_:·:.:::::::::::::;:·
<::::;:··.-.·. .·'.-'.·'.-'.·'.·'.;'.:~.;.

11.1.4 CSR Space 110 VVti.t'
'o::::t:t:::::::::: ::t:'\,:.
A write to the 2107'tin4JJ$.R.s b~hiVij$::~:mmHarly to the remote write, except
that the transa~tjpn doek:fl.9:J.:::gq:J~ut oli"'th.~}PCI. Instead the data is written to
the 21071-DA,(;$.Jl~b:,Pata ·rr6W.(!:m.~,,,g107f~BA chip still has to be transferred
to the 21011-DA%J:i:!i:1:!mt>'"··'"''''":°:}·::'.':-~;,::<>>·
CSR writes, like 116''\vti.#~$~:).l:r.~ oni§>p'~eempted if they are queued behind an
1/0 write to the_ .PQJ, wliibh:.:'®.mn9t.. complete because of DMA transactions on
the PCI.
_,,:\:<<::<:>:::::>::·
.:::::::::::::::~:~:~:~:~:~:~=~~\~~~~~~~~i~~~~~~j~~~~~::··

11.1.s Memory ,@~r'rier:t~:-:l·!·'r'· , , ,:,:,:.·,.: :.

;;:c=-l~::Jll~ ;~o~::n:;~s~~~~t~:~~eans of

Ory~t:lfii~ory'·'};Jlfjj[:!tf~~action, the 21071-DA chip flushes the 1/0 write

buffitdihd those entries of the DMA write buffer that were valid when the
., , , : ,:,: : }: : :':· · ,.,,,tra;rni¢.t.i~i.>h:$t~lled on the sysBus. It preempts the memory barrier in order

•· :; '! ff l i~l'l£~~:J!f~lle:::~w~r':~1::~1~~~~~i:h% :hri:~~~~~-~~;~
8

<r··

.. ··:-:;:::
.... ....

···.·

.:iw@Jing to unfo'ad its 1/0 write buffer on the PCI.
·:·:-:··· ··:·:-:·:··

··:·:···· ·:-:·:-:-:.:-:-:-:-:·.

11-4 Digital Confidential

.J~t~•\Ji!iltltflth. .
tit~i\\i !!11\l

11.2 PCl-lnitiated Transactions

..-·}f~tf~f~~~~}::·: .

and command to determine if there is a t.f:M.sactiotittm£tt!~ towards''''system

~~i':ir:~:
~~'::::i':i'":n:1!!ec~==t!7'£:!•~:l~~c~:ses
start of prefetch sequence).
·:·:::t'tlllit=\::..
··:·:·::::::/:}.
11.2.1 PCI Memory Read, Read Line,ang::::ft@@~ ·~:~:jiiltlii!tt

• Whenever the slave machine

s~~E:~ 1aa;:: :ecks for a valid
1

PCI command and for a hit inJoniU6itits.. address'\~Undows. If the address or
command is a hit, it asserts fil:viMniimitm1x9ceeds with the transaction. If
the address or command i.~J-:]#.iss, it··=au~ii!:#.:ijkdo anything.

•

The slave mach.~@!:::posts .::~::::t)la:::r~~d re~~!i~ to the sysBus master
machine.
-=:= ,:,:,:,;: :;: : ./{It\::. . ·. ·::=:=:n=ti:i:·i::,.1.·i::li:Ittt:·

: ~:::i•~~=~-i;~~~!~~:~::::·

with addresses queued in

the DMA write4)*#.firt:Jf thered!::::~i'hit, writes are serviced until the write
that matches the.rei.~U;lj~~:J:>een retried on the sysBus. If Bypass mode is
turned off, the:-:P.MA"feijd(d().e~t.not proceed until all buffered DMA writes
are comBl~~~(Jt:\]!'It=>.. · · : : ,: =: :=: :=: : : : .
:-:.:·:.:===::tr\)t=:·· ...
.... ....
~~--·:::_
..._.-.-.·~.........
·::::.-::::::=-:::=--.....-·:-:--:-=·:·~=~~- Note ~~~~~~~~~~~~
.·.·-:::-·.·.·.·
····:·······:·:··

T4.~:. co~p~~ijii is o.tf:f#.itranslated PCI addresses, not on physical

,ry

·.:·.~.·.,:'.· ·.=:·=e·:_:_,:_,'.:.==.,m.:,=.'.::,;,:,·':..:,;:.__ '.idqfi~~r~!t~il[i:![![lft'·
..:.:.:.:.:=:::::::::;:~: ~:::::::....

jfl(aiooie time, the sysBus master does a lookup in the TLB in order to
dete~in~tif:J~, scatter/gather map read is necessary. A scatter/gather map

is . '.iierf.ohned if the PCI window being addressed had scatter/gather
ina.DDJLDf? enabled, and there was a miss in the TLB.

The scatter/gather read is performed (described later) or the TLB is read,
and a translated physical memory address is generated.

Digital Confidential 11-5

·:·:-:-:·:.:.: ·.-.·.···.··· .....
··:·:·:·:::::::·:::::::::::::...·.·.·.·.;.·
......·.·.·.··

··········

•

·:-:-:-:-:·:·:··

When
grant is received on the sysBus, the sysBus ma~~r ~lf~L.,Jii~;;
fetch and will also perform a prefetch, if the
li#\ii.i.\\Jij{?
prefet~bJ.~]miP.!~tl:>it

:~: ~~!U:.'!i!~ei~::::~:':ii~~:~:;~!°:J~?:~ll4~~~~i~

the even cache line. If prefetching is to be perf.qfmj.4., an atonmi:lf~quest
is posted on ioRequest<l:O>. The sys!l.Y.,,.,mastEHifi.!P:~tr1.t.es for the epiBus

~~::~n~ec~f~~ction

•

of the epiBus iifrftl>fu~: ~~<i7li~!f ~?•s the
to

The address and command are sent out o~''''£g~.·:.l'-i.µ§. Ir"°the sysBus
master is prefetching, two DMA rea.4.4f:~§.actioifiifi:i.fiH4Pne one after the
other on the sysBus (guaranteed by~¥b.~~Hi~M~m~<.t.req1ie'si)t A DMA read burst
command is used on the first rea&tirld
~fDMALread
command is used on
:~:-:·:<·:·
··:·:-:-:-:·:·:-:-:.:-:·:·:<-:·:·:<·.
the prefetched read. If the reqµ~~i.~.J:: data is:::t0,~::m.'i~':second octaword in the
cache line, then the wrapped::*~#iimi!®.ig::Js used;'·:Htprefetching is enabled,
then the first command used{l~/DN.b\':!!~3&.Jiurst wrapped, but the second
command is always DMA.-::f:!•ij~::.
·.·······.··:-:::::::.:::::::::)>

;:a':i~:~e~a!;Jr~BQ:;:!~JJI)~, ~~~~Z~i~~;d;t!n!ne:I ~i:als
to access th~... approi»1iW.~::~~he HJMfiin~iHongwords within it are set up
when the ~y~§µ~ masterrnr~t~iy~s ownei-ship of the epiBus. As the data
is loaded iii~HM~iP;M:A r~idf6:#.f!~r, valid bits are set to indicate the
longwords thaF'af:i:·:·r~!9Y. to bt¥t~~ttrned on the PCI.

• ~.:,:~~:~~..are ifi~l~~::tio~

conditions of aPCI memory read

The(ifilfli'~tJf::::f~hninates'':'the transaction.

Pr-~pi9,g:::is· not:::~pabled and a cache line boundary crossing is

·-:-:·:·:<·=-=:-

..::::::::;::::::··

,:/:,~tte~P:i~m:t:'.·

.·:-:-:-:-:-:-·

. ::::::ts::'"

. 7 ::::·:·:.1:::bu;:£:::i~tmi.t$i:'t~ cross an odd-even cache line boundary, even if

:{:::· .· .·:]. :j'·.:::-.if.~fetching''ls''':enabled.

ll'.)j··~:::: :::::ti::se::o:~e:~::t::: by the
21o·iUC.A chip.

the sysBus transaction completes before the PCI transaction (this will
usually happen on a long burst), the sysBus is released.

11-6 Digital Confidential

•

ilie transaction rompleres OOfore fue
PCI

~sBm t~~~~';:J~~llf

;J@t

::::::i::.e::i:~~~~;i;;:r;~:ncJ:c:~e:~nfll(Jflt~"i,l!lJJF
completes before the prefetch has started on th~tJJ!ijBus, ihii:iP.!if.t~~h
transaction will not happen.
::::Jti[iti\[[[i\iL,.
·"::::::::r::ii[i}/

11.2.2 PCI Memory Write/Write and lnva1ll•t~:::::,,.. . ,.: : :'<\:i:i[':·:·,.·: ).:·~i ;j!lt ,:,.

• The transaction begins jmt like aread. ~:t!ll't.:'.::=jf::. DevselL is
• :s:: ::~;:::::::::t4111tllffi~~i:;'t ThePCIdefault
::~~n; !':: :::B:i~su~:e•-~~:t!lfs~ !:~ ! 2s!!!r
• :~e:h:e~~::ep:CJ1ll~:;l:~!lt::~_:::~:: and
path of the epiBus is in the dire~Uih of th~::':)f~-iiW:Jite. If the

slave

1 7

the DMA write::fij:mre1>;t}lrou.glfi\th!i::~!J.3us, the 21071-DA chip does not
stall data transfefs .../Jf:\Jh~:. transtifai::::~talled by the PCI master, the
correspondjpgj~piBut't6.ffil~r:Js alsbtS[talled.

•

Ttrhane

sfoalclto1.w0n'Ihsf.j,(l~:M1% re~~1l\'~9nditions
··:·:·::::::::::::::::::::::::::::::::::-.·.
·.·.·.·.·.'.:-:.:;:::::::::;:::·

-:·:·:·:·>

of the memory write
PCI

The initiator t~rifiifiitis::::the transaction.

The ,~W:i\\tl#.t$#:atte~p~:Ft~ cross an odd-even cache line boundary.

OnlY::·tjfi~· QjA:::~n~ buffer entry was available at the beginning of the

traniM.ti®.~Nind ·~rnlche line boundary crossing is attempted.

•

lf:!~K!:::~l!111f~!k~-:~:tull at the beginning of the transaction, or the

Aiill!~~k,!r!!; ~~

!::';!.PCI bus masrer the PCI slave

&l!lliJ•i,lllif;);,:;!lrr~ ~~ei~:~ ~::~:~~=!!e:t~: ::a:~ ::~t on

.... ::."
:::::::"

<l:!)!)!J!\: 1: 1: :-.:·:

·'.:\{f!J?ihe sysBii$Wltff a write data parity error is detected on any longword of that
)Jllfoache line, lhe valid bit is not set and data is not written to memory. The
"·I::::JY:::'PCI burst continues normally.

·:::::,:/Hllr:: :'im-i\::;

The sysBus master is always monitoring the state of the DMA write buffer.

.,,,:,r:lil:).[!)!illllll!!i!j·!:\::t::::~~~~=:~:rar::~~f:~::~;::;,~~:n~~:::e~~:~~:s s~:::~a::I:iid~~a
"'.:':t:=::i::::fequest.

Digital Confidential 11-7

Ai !~il~!~l,_l_I,;_:!_.·._:!_.._:_:.:.:·_: :.~ .i~.~ -=:.~: ;

/}~t~f?

•

The address of the transaction is sent out on the

~B~~!tl::~ijif;

write full or DMA write masked command dependiqg~~ii.lwb.~,t.her'::tll~Ei#.~fre
cache line has valid data.
. :;\.:j.!·,\i\\~~Jftt:t:~-11:\j:!:.:::::!\j\j!lt:=::::,. . ·': : : : : : : : : · .
•

11.2.3

The transaction completes when the 21071-CA:::t.ru:tt'.retums . . ar(\QB::=on

PClio~~::::: ::~:o::-::~::~ 11~.~li!IJJlli!l:ll)J;])J'.:':•e... w··
·.·.:-:-:-}:=::::~:?::~::::·...

··:·::::::::::::~:::::~:~=~=~=~:~:~:::;:::..

•

·-::;::\fi.~_ : '-~=_:}..
..:;·_;_:::=.:..

The PCI slave machine monitors the,.,JJ.p<;~L ~iji)::::ijlggg: with FrameL.
It uses the value of LockL in. the cy~li.IQlJ!r.~.µieL ·.ii$i.#fon, and in the
cycle following the assertion of Fr~#.}~tfti.:::A~t~tm.ine whether the access is
locked or not.
..···:_::_::J:?:?·
.· ·: : :+: t:i,._: ._: :_:~'.'.~-.:~:_)_.:=_.>
.. :·:-'.·..
If LockL is asserted during th~::l~)i'-1~:[:9.f:JframeL>'tiie PCI slave machine
does not accept the transacticm/ruicPW.Hmn~tes it with a target disconnect
(retry, no data transfers)._.,'.:'·_=:._: _:~_:_:[_~-=-~:·:_:·:~ -~:·;_·[_~-~- - ~;_:j:_=\:_: :.~_·:_:
..::::::::::::::::

·-:-:·::;::\::·:·····:-:·:::::.:.,.:-

~::::::

•
•

•

If LockL is dea~~ibed durlrl:g:::l~}gy~le of .FfameL and is sampled
deasserted in tli~kf6ll9.wing cycleWli.:i~ktJ.ie transaction proceeds normally
as described.J.~ the pii:waµ~::,.f;ectioii$FJI\?'.

If LockL is::~l~i.}$.~rted'"JJ.fiijl!!th~tJ~Yci'::of FrameL, and is sampled asserted
in the followifig[)\lii:~Lthen the[:\tt~saction is treated as locked.

Locked transacti~ii~t~~{ijp:t,_tre~£~d specially on the PCI by the PCI slave
machine. Th~Y:J:.l~ar thi.\.\:~y$;J.~µi lock flag. The system lock flag is held
clear untiltth~lPCI/slave mi.fo'hine finishes a non-locked transaction to

~~~::11f~~12~~~ass is disabled as long as there are locked
.::::::::;:;:::::-·

•

::{{}'.;::

Tll~::=:~Y~~m:))}p~~ fl~g~j)~~::::eleared by sending an ioClrLock encoding on
.,. j1w.:2!~Jlll~an Idle encoding when the
chip does not

1
_.J::~:m~m~lf~~att@ftl!~,~-~r

21071-DA

Map Read

.:/Ftf{?'?t=:=:%[i\?:'-f!atter/iithii:tead is essentially similar to a PCI-initiated DMA read on the
/}?:·::::·······
--::<!;~us. DatiF$.it's to be loaded from the DMA read buffer into the TLB .
.·:-:-:-:-:--: :-:-

t i\i\

_::fJ!]frrors (uncorrectable data errors, memory errors, and invalid scatter/gather

.jjlifii;ry errors) are found on a scatter/gather read, then the transaction that

·:::=:\.'itlEi:=:]f~aused the scatter/gather read is not performed. On PCI read transactions, the
··=:t::{:[[[[[i:[_.[i:~::ili.~r~?;:~action is aborted by the 21071-DA chip; on writes an interrupt is posted.
··:·:;::::::

:::::;:;::::

11-8 Digital Confidential

!~l ;j;[:mi; ;it~ ~l r!i,i>

11.a epi eu s Arbitration

servicip'li"iJ~;k~~~it~hs

At any given time, the 21071-DA chip could be
(CPU-initiated and PCI-initiated), all of which have_-:-~<fl#se th(fijpjl\#.~. ,:,._The
21071-DA chip cont~ns a central epiBus arbiter 'Vlli~f#~rbitrate~ffq#[Ufe bus,
and appropriately sets the direction of th.~{!,piBus~'''41J.~\::gG,J.. master -~iiid slave,
and the sysBus master and slave all req#ii~:ll)~ bus "-t6.if&in9P..~ transactions.
Table 11-1 lists the priority of the variou~ffe,qq~~~~,. and ·lHij:::j~!@*tion of the
epiBus.
· ·: ;: :;: : : : : : : : : : : : : :;:. .
.. . .·.·---: : : : :,:·
· : : : : : : : ]: : : : : : : : ~!:': : : ..

Table 11-1 epi Bus Arbitration PrlorltyJ:t:rnlI:!i!I?t::-..

·.·. ::,::::=t:::::.:::'"::::·;:·:::-

>>:·:·:-=·:·:·:·:·=·=·:·=·=·· :·:·:·:-:.:-·.·.;.·.·.·.

1
2

3
4

5
6
7

PCI I/O reads
:/:i\/FlI\:. 21071-iiAttri:::2io71-BA
oMA writes <dera~1i)}lI:::::::!i:::::aion-oA t~:::~1011-BA
OMA reads :': . . t\? ··-:,::::::~tdiitfaJA
to 21071-0A
......... .'
.-{~~~{if~:}~:;._

~~1:~;;;;~1!~f'lllli1'2+::~:~: :~~~~:~~

.·:-. .CSR reld~:[[[/:\:_:\\::>·. ·.·.,.,.,\}:::~:::::1·?t07l-OA to 21071-BA
./·lt:~~wr/gatliJf::).;.!~t::,._
21071-BA to 21071-0A
··.··:-:-:.:.:::-:::·:·:<·:·:·:<·:·

Digital Confidential 11-9

DECchip 21071~.:~ll!~,~111,~i!ll Data
·:·=::::ti~~-::}::;:'.:;;:;:::

12.2 DC Electrical Data

·::::::::r:tt:ttt:~::::::-.

This section contai~:'&i~B·•·~IRw••for the DECchip 21071-DA
12 2 1
· · :::!~~ :!i'i•~~:!111r~::~e DECchip 21071-DA
Table 12-2 lists the n(fi'~i.1#.i~pc v~lues of the DECchip 21071-DA.
··:::::::::::::::::::::::::::;:::;:::-

Digital Confidential 12-1

Table 12-1 DECchlp 21071-DA Maximum Ratings
Characteristics

Minimum

Storage temperature
Operating ambient
temperature
Air flow

-55°C (-67°F)

Maximum

100 LFM 1

Junction temperature
..::::::~~~~~~~~~:::::::~:~:~:::~:I:~~:::::::::::·=·

Supply voltage with respect
to Vss

-0.5 V

Voltage on any pin with
respect to Vss

-0.5 V

+6,·.':+u..' :.'~.' ·'.:,.:.v:,:.'·'"

.....

..:\\}t
.....:·:·
····::·-·.-.·.·:::·····

. ·-:·:·:·=·: ··==)\{~~I\:::-

.. ,.,. \?'. vdJ<~Fa~i::u:::::::,.
.::::=::::::

Maximum power:
@Vdd = 5.25 V
@sysClk = 33 MHz
..

1 LFM = Linear feet per minute

·.·.;.;.:-:-:.:-:-:-·-:-:

·.:::::::;:::::::-:-:-:-:-:··-·.·.·.

Symbol

:;'.:'.:-:-:.:-:-:-·
:·:-:-:-:-

Minimum Maximum Units

? 2.0
lnput.Jpgh::t~lw:.:::1f'''·
Inpu~i:!~V-==·vof~~::::::[:jij:j::::::::::::::::[:::::t::[\[::::::::==· qM~~t]ngh voltage?\?/'/"

vol

ditj9~j9,w,. voltage

.;:f:!::::j\\l·l·!:jjjj\ijj\!j:::,,,_\:::]\j\JP:.P~f:'ii•:\f¥r.rent

. . . . . )\~put leakiig~::£ij.ffent2
]f:.%Hlpd
:·:lput leakage -~G~ent3
;:::}.:::[[\~~ph

· · · · · •·• ~II; /c••·;\j .;f,,~:.~"f'

cur-

~~jt~il~il!c@~~' testMode and tristate_!
2 For tristaMUlft'·

3For scanEn, artd testMode.

12-2 Digital Confidential

0.8

v
v

0.4

v
v

2.4
-5

µA

-20

-120

µA

-10

µA

Test Conditions

12.3.1 Clocks

·.·.:·:<-:·:·:·:·:·:···:·'.·'.·.

:~~!~~;!:it:i1;3 s~~,:n;e!!:lll~~~l~!r:~~~:c:e~~==~i:!ia1
to generate four or five intem,d~\~~fk ed~f:~l!~·::~~,,~gure 12-1 and Table 12-3.
·.·.··'.·'.·:·:·:;'.·'.·:······

··.·.·.··:·:·::r=:::::::::--·=:::.:-:-.

sysClkOut1
clk1x2

·>~ :::::/::::: ::::::::::\

. ,.)::::~:·,./:::;:::::;:::> I· - - - - - - - ·\ _____!.

:.:.:·:-:::::::::~::·::

·..;,:<<tl:;,;,o;i:::,;,;,..::::,.....·:;:;:;.-.\ _ _ _,

clk2ref ..:'' ::/::J:/}~?f ·:;: -.·

<·:: ·:-:.,.;;.,·:\....
:· _

__......__

·c1k1~:l2:::·:/''''' .·::,:::;.~,....'.::::::!_mf_:,:··........,..,,,,,._ _.. _ _ _ _),
:::;:::::::::~:::::

•ctk2~~1~+::,, .·:-: {)/.

.+. .

., ,:,: : : : ~:':\i i'·!\l.li~l,0: :, =,- , ~_ ___,i

_,/

\ _ _ _/,
\..___

_...

\ ...._ _ _ _ _ _ _/

.-:.:-:-:-:~-:

i::::.[:*~)i'-~-------?

~-----

,_____i

'---

·Jlif~'\~!lll\iiii~Blliiili~lf
.

·:·:;:::::::;:;:.:::::· ..

\ _ _,

·-:-::i;:;::::::;:;::::;:; .;-:-:-:-.

~---~=====.·.- _-_-___,_:____;-----,

·.··=:::::::::=:=:=:=::::;:;::::::::::-••••

lnter~~fl;:ifflw~
. :. .·'.}~d clocks.
···::::=::;:
LJ-03456·TIO

Digital Confidential 12-3

Table 12-3 DECchlp 21071-DA Clock AC Characteristics
Parameter

Minimum

clklx2 period
clklx2 frequency

clklx2 high time

TBD

clklx2 low time

TBD

clklx2 rise time
clklx2 fall time

TBD
TBD

clk2ref setup to clklx2 rising

0.6
2.0

clk2ref hold from clklx2 rising

Maximum

ns ·.;.·.·.·.··
·-·.:-:-:-:-:-:-:=:·.

12-4 Digital Confidential

12.3.2 Signals
See Figure 12-2, Figure 12-3 along with Table 12-4

Flgu~

12-2

DE~hlp

21m1-DA OUtpm Demy

a.J.tdi::IJl\ii:\:t~.

M~-~;:::'.~l\lllt~J>

.·:::::::..

Output 2

.::=:®'-k~:::::,.

Digital Confidential 12-5

Figure 12-3 DECchlp 21011~0A Setup and Hold Time

Hold

Valid SigrJ:f:f}>:·.
........·.·

12-6 Digital Confidential

Table 12-4
Signal

Minimum

Maximum

sysAdr<33:5>

4.8

12.6

ioRequest<l:O>,
ioCmd<2:0>

4.3

lO'.~ttt;1~

AD<31:0>,
CBE1<31:0>,

2.0

Par,
FrameL,
TrdyL,
lrdyL,
StopL,
PerrL,
LockL,
DevselL

MemAckl

pClk

ReqL

pClk

epiData<31:0>,
epiBEnErr<3:0>

clklR

clklF

18.4

;;j ;'ii

··.·.:-:::::::-:-:·:··

_::'.{ ·'.·:-:.:-;.·

l1;ilifu~~l'!1il111;§phlp
··.·.·.·.·.·.·.··.-.·.·.···.

·-··:·:·:-:-:-:-:-:-;.:-:-:-:.:-:

21071 ·DA AC Characteristics

·.·.·.··:::::···

Setup

Hold

Unit

17.1

3.8
2.6

ns
ns

7.5
.. -:-:-:···:·:·::::::;:;:-··· ..

(Setup/Hold Tlme)
Reference
Edge

Notes

clklR
clklR
(continued on next page)

Dig ital Confidential 12-7

Table 12-5 (Cont.)
Signal

Setup

Hold

cpuCReq<2:0>
cpuCReq<2:0>
cpuHoldAck

0.2
19.2
-0.2

4.9 . .

ioGrant

o.o

ns <i[l\.[. j.j[l.l.!.lt1=hl!..

1.S{i.:_.:_'.:.: _·:.:~_: .:_'.:.: :t: IJ.:S
3.5

"::::::~lld'.R:::::.

/~} ·: .:. "~l~iiffi'l:!'"!:l!.j'ji:ilfij{-

··"\:::{:t:i::]i:t:::::\.

·:::::qf}?

ioDataRdy

AD<31:0>
CBE1<31:0>
Par

FrameL
TrdyL
lrdyL

StopL
PerrL
LockL

DevselL
GntL

MemReql

12-8 Digital Confidential

.. .:::::;:·

-::::;:;:::::;:;:··

···:::::::::x>

. :-:·:·::·:~i~~F .

ioCAck<l:O>

epiData<31:0~(?.Y\i)\.·[\[j~j[\jj\:_j\l.J_::?>·

. . ::::r::{i\[[l:::r.

5.5

clk2F

1 11

] ;1i111r~11~:t\ ,

DECchip

·:·:::.:::::::::-:=::::::::·

210711~~~11,~~·w:a~~~

This chapter describes the behavior oJf!ilU.~~~~: on power-up and
assertion of reset_l. It also descripg~iiiltn!}~ystem ·1~'=l:ir~quirements and the
various registers that have to be::imUi!Ui~iA~:fier rese(J is deasserted.

1301

p:~~:~!. the ~i~l iµp!~llL~::~:~!~:71-DA shoWd be asserted.
It should be kept as.seft~{j.~ilitl.nt~l the'\~y~fl.imtqlocks are up and running for 20

cycles.

.-:·. ·

.. )~.~~r~~t::::.. .

·:=:=:~:~:::~:~:~:~:~:~:~:~:~\:::·.

·:·:<tf}/

. .=::::::::::;:::::::::::::::::::::::.:·.

13.2 Internal Reset::l:::i=t:l·t=>:•-

=
. :=·.:.: ·.·.=·.·
·==:<x::~:=-··::
.. r==::::::.
·. :-: ::~: ~~~~~~{~}}}:··

·=::::\.:.::.::·'..·.·=:.:·:·:.:.::...:"'.·.::••:.:::=.·::=••

The assertion and de~§:l~l:~f:t=9f th~·===+~set_l pin on the module is asynchronous
to the DECchip.2.::l:Q1.:l-DAY1\Pf~nt~rnal reset signal is generated from reset_l
which asse~~j~~yn.~JJ]jf§pousi§'::a;~Fsoon as reset_l is asserted, but deasserts
synchrono~Jylf:Du~:::J.9}th~/§Ynchronous deassertion of the internal reset, the
DECchip 2l.Q11-D.A\f.equg~$. that no external transaction should start until 10
system clo&li]~Y:~li.~:::ifter:::m~ deassertion of reset_l.

13.3 Stateilllf11=:· ~:~;~iili\·~:n::li\:FJl~et assertion

nii![j·f.~~l~W,Jng are··:·;;::~al rules for the behavior of DECchip 21071-DA pins
.· : : : : l=l:l:lil1:.:l !. ll.::l\:.·::l:\l~:~t,ririgi\{!!~~~[l:\::::::::::::-:·.

-·-:·yp:r===:::·:·:·:·===::::tF!\l::~~ll inputmfi:mt· control signals (except the clocks and reset_l) should be in

{)·······•.1.·i.1.,•.•. • .·.· •· • · ·

iliill~~; :::~:~!~s=a~: ::gd::s::::~ asserted.

:::::;::::::::·

'" "':': : :;=: i!: lj!l:=: \ ·:·:1 :1: 1:m:;: ~:. All bidirectional signals are tristated.
··::\}}{{{ :::::::::
·.·.:\~~{/\~i

·.·

····::::/~~~~~;:::.

Digital Confidential 13-1

tftf~~f":·:-:···
fJt)r=:·.

.{::·:::·:<·>
}:::::::::::::·

: : : ;:~ i:{\:.

::::::::::::::::: ,._:;:::::~:}:::-.-

.::::::::::::::=: ::=::::::::::::::::::::::::::::::::::::::::

•

'it!~j)f ·i~,1!;'.·,,dli{f'
:~~~3!~5:o:ea~~:::t~:~:;:~~':~~~;Jffllit~!!!!e

•

of synchronous internal reset).
..
=j\j\:i\): i!i !\ji\.: j \L=-.
· =·:===t \I\i!:=:i: l!i}='"
epiData<31:0> and epiBEnErr<3:0> E.l.:t'.~Jlriven:·=-=a~d9i.iJ!$ reset is··asserted,

The exceptions these rules are as fol ows:
to

• :::::~::::::n~:::s:::s::::!:t!11S~~::!lll&ted until the
··=-==<t\\ilt}\J\~:=:-.:...

deassertion of reset_l.

•

·.·.·

1
g~~h~
2~o~~~Jf"~~~~;~tii~1'Lllr~~~
!1~~~e::i~:et!;
on the assertion of reset_l, and
later. If the PCI
P~iH$ triscli~~Ui.i);y~le

~::e~~~~~ :: !:e~~~~~ili\lt~, !.!~~~s :~~~~~ring
3

• memAckl is tristated on tldki.~~erti~:::;,Bt;1f.i~tiJ and remains tristated until
the deassertion 9f::r:~set_tfjl:\::::::.\j\=Iit::::=

.·.·. : : ; ;:; ; :- .

···:::· ":'.;:;:::::::::::::;::::::-.

----.·.·.--·.·--.---.-.·-·-·--.- ...·

_______·.·-·::::=·~·,..,·:=:::.~=::::::...,_:·. . . ,____·=:=:::•:::=.,.,.____________
In all case.~:~\:it~::J1ss;;f~:ah.l.i~~i\#.ti~ta~j=:=h~errides the assertion of reset_l.
that is, if tH~ti.~JiliJj,.s ass~fti,q}q#f:µig reset, then all the outputs of the
chip go to theii?Qj~&Z:===~tate."'"'=ttnr~s'et_I is still asserted when tristate_I
deasserts, then th~F~Jgp~J~===returif to the normal reset state described
above.
"':=':/{?/{/\,.
-::/){ ::::::::::-:::;:::::::-:::::·.·.
::::::::::;: -:-:

·-·-·-::::;~~{/~~((.

.::;:;:::: ::::::

::::::: :(~~?- -::;:~:?~:;;1~:

/:'./{

····--

···-·

13.4 Confi.gurllj@:m.·:=:afte!·lll.Jfteset Deassenion
The rd.}}i:Wi~~:::ititi.\~\n ~:i~!iliibe initialized by software in the DECchip 21071-DA
~~tli~f deassertfofPbt=feset_l.

.,.: =: :/=: : : : :===:==·=-· .-=<:=:::q.9!t~c control and status register (DCSR)

,df~ll~lft~lfi.!l..r.:;.:1:.1=.\.: .:\.~:.: .rot 1t1.1~.: ·.: :.:..: :.:~.: i.les registers
1

·. :>

~~?~f \[~~~?-

::\i!'.\=)·f:=:::::rc1 mask=registers
==t)f: :==:==== .-=·=-=·=-=-·=· .i:l:flf. Translated base address registers
--:-:-:::::::::·::;::::;:-:-:-:-·-;.--"'"'=<@[ :::rnrnt=:=:r::r::.~?t Host address extension registers
::::::::==

-:::::::::::\~::::::··

.. ====:=: : mmrn=-=li\i.:\.:.:.::.:.!i~l::::::=:tt~I
.
master latency timer register
:-:-:-:-:·:-:·:-::::::::;.

-·-:-:.::::=·::::::::>

13-2 Digital Confidential

Part III contains information about

14.1

•

Memory data bus

:;::=\)):::::-:·:-:·: ..

:.: .: : :

·.·.... .......

.:;:;:;:;:::::::;.·

"':::<%\%lit}:::,.

·.=:?{~~~:}::=:::{:{:>

• epiBus
.·=·=:;:;:;';:;'.;.: ;.;.
=(: :i !l:\i:[l.11111111111!:\[:\:\:\t: : : : . .
·=·=:=t@>:·
This chapter provide~(:~ bri~f descfriptjijfi\Qf the pin signals for the 21071-BA
data chip follow~d by."'detltl~AJ.l~scriptiij~\i\Pf::the 21071-BA data chip interfaces.
A connection l~f::l~~t,given."'f'=~:l:qj'im~Ml71-IlAtd.ata chips in different bus width
modes, and fof'':i~l:l·~:;gz_1-BA/i~~~~f:~:-.~21011-BA 0,1,2,3).

14.2 oecchip 21011:s11:-:::1un _List-:r·
Table 14-1 ·····.·.···,J\·g~c6hJP==:i~foi~
.-:-:-:-:-:····-·.·
-:-:-:.:-:-

-eA'''li1n List
In/Out

Buffer

Function

1/0

4ma

sysBus Data.
In ECC mode,
sysCheck<6:0> appears
on sysData<39:32> and
memCheck<6:0> appears
on sysData<57:63>.

1/0

4ma

Parity pins for sysBus
data.
(continued on next page)

Digital Confidential 14-1

Table 14-1 (Cont.) DECchlp 21071-BA Pin List
Number

In/Out

110
Ifo

Buffer

Memory Signals
(33 Total)

memData<31:0>
memPar

<:::~~~i:~:llhn~.

·.·

·-=·:::r::::::~:tlttn!fl. data.

·.·....·.·4. .W,~::U]fo:\,:-.
.. . . . ·.·.·.·.·.

1're:' 'm:' ' .' .',~_"',·.:.'_~~:¥.::
·.·:rv.·'.:..'.',.·_'. : ~:~
,'°.....·ty
p1·ns.
.

iu1

·. ·:::{:}f~{f~t~~\:\. .

'.'.'_.':·.·.'.'.':··::··'.:n.'_:
.._·.·..

··:::\{('

Cache/Memory
Control Interface
Signals (13 Total)

sysCmd<2:0>

subCmd<l:O>

.··::::::::::::::::::\j:[·~:·!j!\!ljj!:·[[::w:·~~~~~~'!52f~~1sl.:;.s
.·:·:·:·· ·.·.·-:·:·:

Selects 1/0 read buffer to
sysBus.
Turns on 21071-BA
sysData<63:16> drivers.
Turns off 21071-BA
sysData<15:0> drivers.

sysIORead
drvSysData
drvSysCSR
drvMemData

I
I

14-2 Digital Confidential

Sub-commands for
sysBus side of the
21071-BA.

Turns on 21071-BA
memData and memPar
drivers.
Commands for memory
side of chip.
Selects octaword to be
read.
(continued on next page)

Table 14-1 (Cont.) DECchlp 21071-BA Pin List
Number

In/Out

1/0

1liif

.·:=tt~/fI~t~~}::::...

!f:.:.·:;::.:;·:···:::•:.•:••

,·:1.1~li:W

:.·.•:.1.::!·.:•!.::•.•:·•.,.·1:.:·-···.:·;=·-:·:·_:]:
••:..•
:'•.:····:·_·::!_::;_=::·:·•-•..
i•_:••
: .•

Buffer

eplBus Signals
(46 Total)
epiData<31:0>
epiBEnErr<3:0>

1/0

<~:::)!)!'._;11.j.::hl~

J:f!i\\::..

·-:::V\]~lf#.t~P data for both

·nMA\and- I/O operations.

rililititf;tt1;,!,:~I~~:~:

··::::::::::::[\[j\!:jill~~~:e~feeJ~:~:s and
foF'epiBus to 21071-DA
operations.

epiOWSel

Selects which octaword
of the cache line will
be transferred on the
epiData bus.

epiLineSel<l:O>

Selects which cache line
will be transferred on
the epiData bus.

epiSelDMA

Selects which buffer
(1/0 or DMA) will
be transferred on the
epiData bus.

epiFromIOB

Selects the next epiBus
transfer from the 21071DA to the data chip.
Qualifies epiData control
signals and enables
output drivers.

Selects which cache line
should be read or written
from the sysBus.

Clears all byte valid bits
in the cUITent line of the
DMA write buffer.
(continued on next page)

Digital Confidential 14-3

Tabl~ 14-1 (Cont.)

DECchlp 21071-BA Pin List
Number

In/Out

·.::::;::::=:::::.··
.·:·:·:·:·:·:·:·:·:·:-:::::::::::::::..

Buffer

. /::::::~:11=
·==:t\EI1Il:::::.:.

Mlscellaneous/Clock
Signals (8 Total}

eccMode

wideMem

clklx2

clk2ref

reset_l
testMode
tristate_!

· =·=:=: : : 1\: .=.:.\.~.:=: ·: :·='.~:.=t:.·:'.::=. .=:~...=~·.=:.;.=:..t.'.·::~_-'.=~.:.:.=.=:.=·t.=:=:= ~·.: : ·

'lest mode select.
Tristate.

1
1

Parametric NAND tree
output.

pTestout
.·:::::::-.·.

Total Power and
Ground Pins:
Total Pins:
:-:.:.:-:-:-:-:-:.:.:-:-:-..

..::: ::::::;::::::::::::: ~~~~~~~~~~~~~~~~~~~~~)}):~.
:-:-:·::;::::-:.;::··

):}{{t~

::::::··

<:;::::::.

:(~{j(~~~

14.3 Detai l,~d \1!:9.@il:::==·DElipriptions
This ~l,i=on"==~l:l.l!i\\\filil descriptions of the 21071·BA data chip, the clock
edg~~A~¥which they/cairchange, and rules about their usage during various

trinsietions.

===::::f:i::::j'[)\\I::~:::~:::~::::\:jf9r-=:::i!ill~t:§ysClkOutl_h is treated as clklR.

=<:i~C"':=:

<:}'<\/"

·'.::::::·::::~:\::--

. . . · = .=.= ··.::t<r:r:::::=

··-=t(\\\(ft'\\\\]:=.

::::=:::::=:<>,....·_ _ _._=·::::.....
:t=_·- - - - - - ···::::·:::::-:-

Note - - - - - - - - - - - -

.:/(}
=·=-=·=-=-=-·
. ::::'/}/The DECchip 21064 microprocessor does not use clklR, but uses
.. \~(i}~~~\:::. . ·... .:::::::::::::}:::::··
'"='=: ;=: :==: :=t\t\: : : :=-=·"=-=·=-""' sysClkOutl_h to generate and sample signals.
.·.·.·.··:·:··.·.·.·.·.·.·.·

. ·.;.;.:(/?·..
·.·.:·:···:·····

.;:··-

··:-:::::::::::::::: -:-:·:··

14-4 Digital Confidential

14.3.1

14.3.1.1

sysData<63:0> is a bidirectional bus w~j~b.tpr.ovicfo~:\:4~§.i::::tR and from
the 21071-CA chip and the CPU. sysP::4f:;gl)~I~r~ thttp~pty bits for
sysData<63:0>.
'i:j\:il:t:jj·!:\::::::::::·::::::::::\}j:j:i~.il·-:::::.:::ltt:::::.:·. ·-:·
0.:.. a..
dn·ver of s:-~::'Q.
µ:·: .·a·.-·D
. ~
u
···::/I{(?:::::·
The CPU l·s the de.c.ault
=.'...
· :· -.'".·t.'.·_:_:.·n_·:····
....·.···.·.

···:::·:·:··-·.·.-...-...·.·.·.·.·.-

When the system is configured i~·[i)ifilllji!p~rj.ty mode:
•

sysPar<O> is the even p~nii~::1~~oss ;i;lllgal:O>, and is connected to

•

sysData<38:32~\ij:::_th~h~QC ~~t6$~?sysData<31:0>, and is connected to
check<6:0> of the pf&i,~~~~~~'::'.....

• :::::l>o:sth~-~i~~~&!lltf•pa::63:32>, and is connected to
Wh::::::;a~'.::~;!l~1~::!';:cc mode:
··.·:::::-:-:;:::::::::···

·:-:-:.:-:··-=··-·.·

• ~~i~t.r~--h~~~~O;f:i:~ i,:::0~c~:.cross memData<3l:O>,
:::::::::::::::::::·

..::::::::::;:::::::

.-:::::::::::;:

14.3.2 cache/M•le.~yl'.pata:j,·re•th control

d::tr!!~lll1tt!:

14 3 2
• · •1

Input

:jj-~=~ ~~~~dge: clklR assertion, clklF deassertion
2

;•di!f@·

-:d::l\!.,!.:\ii:!I?li\\1i11.:\i\'j\[:\i:\\it\.OutifiJ~1!11r~ Edge: clk2R assertion, clk2F deassertion
:::: -:-::·
\)yji.~n drvSysDita is sampled asserted, the 21071-BA chips drive sys······.:::::;:-:·
,,}Qita<63:16> and sysData<15:0> (only if drvSysCSR is deasserted) on this
-:-;.;.;.·

·.;.;.;.:-:·:-:-:-:-:-·

.J/HieUhR.

····:;:

-:·:··

··:·:::::::::::: .. :::;::=:::::: :-:····
·.·.:·:-:-:-:-:-:-:-:-:-:-:-:-:-:

- ·.·.·· ·:;::::::·..;.,

Digital Confidential 14-5

14.3.2.2

sysIORead is assertelby:::t.mMiaon-dA chip along with drvSysData to indicate
that the cont~p~\9fi':~h:~. Ild'':'H~~~]~uffer should be driven onto the sysBus.
sysIORead ,J~[:)j,~~atlj~lt[th~ _3,10~/i.iaA chips to drive the contents of the 110 read

buffer ont~;I! s~.
14.3.2.5

l~ili!

s:;i~il!"''!!~~put

·.·.·.,.·.

·.''''''hjppJ\S.Jimpling Clock Edge: clk2F

_,: : : : : ;: : :;, :.:; :!A[j\ -i-.l\·l:lh~ ~]ela~:l#>.? signals are asserted to further qualify the sysCmd<2:0>
..;.,.,.,., ··:,::::=:::::=::···

·-::''\ll:als, as "d~$@ibed in Table 14-2.

::=::::::;;::::::;:-:-:-·
,)OOQ.~:· subCmd<l:O> in conjunction with sysCmd<2:0> are used by the 21071-BA
'"':\.:;,:i'\):t!\::::_... _,,fI::::~}:ifps as commands for operations on the sysBus data buffers.

·-:-:·:·····:.:::::::::::.../):~ ~{:~}~:}::=··

14-6 Digital Confidential

14.3.2.6 sysCmd<2:0>

::= ~~l~i~7~~!1put

{~)'i'i')[tli[ltl Jl !J ~;[•>

:~i~;;~;o;f~~~;~;~a1t~~'lr~h:f.fns

general, they echo the actions taking place orif[tJ.;t.~::::~y~Bus dtd1pgflhe previous
cycle. The bits are decoded into various actions::li$i~if))n.
the fdlfowing table:
··:::;:;:::::::::::::·:·:·::::::::····
··::::;:::::::::;:;:::;::::::::::::::::..

Table 14-2 sysCmd<2:0> and subCnJ!llll!b!!Rdln~iitfW
sysCmd

subCmd

000

REsmml:\::t~::::::i:t>:::-:·.

Th~==fufu.ge bits in the merge buffer
!tfWf::::::::::::;::::ttFJl=\::=:·. are cleared. All sysBus counters
.-:·. ·: : : : : :
··::?\lilt:~~ reset. The data in the pad
.Jf}({{
·:::\(j:::]rtches is held (to save power).

if1 1 1~;1t1 1 1i 1 Et;l~E~Ef~¥~:ld
:11,+

001

010

RDDMAM

transfer of write data due to a full
write buffer.
No write action is performed. Sent
when waiting for write data to be
ready. Data from the sysData bus
is loaded into the pad flops.
Data in the sysData pad latches
is loaded into the DMA read
buffer, which also serves as the
1/0 write buffer. A counter is
incremented so that the next
RDDMAS will load data into the
next sub-cache-line of the buffer.
Data in the memory read buffer is
loaded into the DMA read buffer.
A counter is incremented so that
the next RDDMAM will load data
into the next sub-cache-line of the
buffer.
(continued on next page)

Digital Confidential 14-7

sysCmd

subCmd

Mnemonic

100

MERGEOO

·::::::::::::::::::::::::::::··

NoW,:~jl~~~ loade-~!"~tHlll~J.•tmerge

buffef.l/Afoounter is iricr&fuented
so thlbhtliihtext MERGEnn will
.}:load ch1fiUfiii.]he.. next sub-cache
<~_::.:!:!~~B! the l~tif!~~::i\i'!~::::::."':rw.fl#.i::@:ix_c transactions that
...·.·. ..
hif'¥(i.)~l.;l~f!¢@:~e, each sub-cache_.::(jf/}}t:::::)ine of:tb:i#ii.tge buffer is loaded
.Jftlttttt:t:wice: oricefaVith the CPU write
)t::::;:/:;:·:··:·:::::;:l]!~~H~fring MERGE (that is,
··=·=·=-:····
·.;.'.MEl«l.E:Ol), and once with the
ti??\...
ca~hii]lita using MERGE with
:??:{:::=}(?:
inverted enables, called an overlay
\!:fa/::--···· · :·:::::::/::-::::;:;:, · · :::{that is, OVLYlO).
·:.:::<fj]:~::"in MERGEOO, but longword O's
'•'.•'.·:·:·:-:::;:·····::::·-·.·.·,·
··:::qfuta in the sysData pad latches is
-.·.··.:-:-:·:·:·: :::::::::::::=:·.
·'.·'.;::::::::;:;:;:;:;:;:;:;:;:;:;:·
loaded into the read/merge buffer
. /::·.·.
··:·::::<:t:i:::::::·~1??
and longword O's merge bit is set.

100

MERGEOl

il'ii1fl~E10·,+!;!i

100

·-.::::\{ ..
··.:·:·:-:-:·'.·'.

·.··

··::;:;:;:: :-:-:·:;:;:-:-:·····:·

100

101

·>::<t:::ttMERGEll

WRSYSO

WRSYSl
WRSYS2
11

WRSYS3

As in MERGEOO, but longword l's
data in the sysData pad latches is
loaded into the read/merge buffer
and longword l's merge bit is set.
As in MERGEOO, but longword 0
and l's data in the sysData pad
latches is loaded into the read
/merge buffer and longword 0 and
l's merge bits are set.
Data in the sysData pad latches
is loaded into the ;memory write
buffer representing cache line 0. A
counter is incremented so that the
next WRSYSO will load data into
the next sub-cache-line of cache
line O.
As in WRSYSO, but cache line 1.
As in WRSYSO, but cache line 2.
As in WRSYSO, but cache line 3.
(continued on next page)

14-8 Digital Confidential

Table 14-2 (Cont.) sysCmd<2:0> and subCmd<1 :0> Ert,S~~9P~
sysCmd

subCmd

Mnemonic

110

WRDMASO

Dat.~t~:::~~e sysn!lliijl![J~tches
is ·tij!fi'-IJYith the DMA\vrite
bufferifanddoaded into the
. /Jp,emory\i,ff~j]:).µ~er representing

<~ilil!:.lti~~~~e~~,:~'::ar~: ~ext

· tvitb.'MAso. will f~ad data into the

.-=<::fi1]It:t===·~ext"'~~~f~~=-line of cache line 0.
110

110

::Jt::rm11111111;:::: ::: :: ::::

110

WJ..U).MA83"==:::=:tthtt/tAs in WRDMASO, but cache line

111

=:t::1:.::::::1::::::::::::1:::1:1::11::f/\:::..

.:::::::::::i:::i:::::11::::1:1::::.:..

2· .·-::::::::>"'

· ·:;: : : : : : : : : : : : &~: : :·

~MAM,Q

""==nata in the memory read buffer
is merged with the DMA write
"====:t?t?h/?:::.:.. buffers and loaded into the
...:::\{[[tJ?. memory write buffer representing
"=·===·
cache line 0. A counter is
incremented so that the next
WRDMAMO will load data into the
next sub-cache-line of cache line 0.
As in WRDMAMO, but cache line

'"::O:\{lllllt::::::..

111

As in WRDMAMO, but cache line

2.
111

As in WRDMAMO, but cache line

3.
··:::::\~{@}}~~}~~~J}:}:··

14.a.2.1 memCmd<3:1 >

;)!;i\~:;i;:~~l~llti'Ji~!!l~l~i~7~~~put

===:;: :;=: ==:~:~:~:> =·
:-==: : :=:=: ==: - ../:::::.=·=.

:.:~::i::::::.:::ll~·ptPut Sampling Clock Edge: clklR
.i{Wh~ memCmd<3:1> signals indicate to the 21071-BA chips the action to take
. . :==:\fliiilli]rn:::ittJ::=:ilj:lli9ii the memData bus. For the encodings ofmemCmd<3:1>, see Table 14-3 .
.":?{\@({ :::::::/ . . . . .
·-::\}{~: :::::::'.\:::::::::

..........
·:::::·:-:.:-:·:·:·
·.·.···:·:::.:·······
·-:::::····

··.·

Digital Confidential 14-9

Table 14-3 memCmd<3:1> Encodings
memCmd

Mnemonic

Function

000

RDIMM

Read data is loadedJntJ.il:¥he readfffiil.~ll:§µtrer on
the next memClkRLAfoiiiinter is incremirited so
that the
RDx~dFWilUi&d data intolhe next
availabl~k~ib~cache·linM6Kt!itr:ead
·-:-:::::::::::··
.·.·.·.·.
··:-::::···-·.·.·.··:-:·:::::-:::..··: ...•. buffer.

.next

001

~:~~:i~1~llt.W.:.n!~~,,,:l~r~~k~~:~~~

RDDLY

is incremented so'.thi.ifthe:::next RDxxx will load
data intoAihemext aV'ili':tih1tk~ub·cache·line of the
Read Bi~'=~i:,\:~i:::tm>:,,.

···<<ii;··

010

NOP

011

RESET

100

WRIMM

;~j1~:~11}Teset.

{Q~/f#~mH~h~. .memoey write buffer is driven

_/:::fm::\l:~~~~-tfill~e~e~:~c~
'''<:t:::t#!i~J~ub·cach~:::nhe to memory.

./?:\.,.

:if:::

the

WRDLi)):;jfjj) •\.. . !!llw~e~':ici~.:..~i::r~'!::~~kR.

101

·:::\tt?tI:\\:A couriteifis incremented so that the next WRxxx
·.''''\{::::i\\]ill.,~rive. lhe next sub.cache.line to memory.

'·'.·:·'.·'.·'.·'.·:·:·:·:;:·:·:·:·

·-:·=::{:}f~:=:::::: :::::·.

WRIMMU? .. .

110

··:.:.:-:-:-:·:: :·:·:::;:;::::-:-.
·-::::;:::::::::: ::;:::::::::;:::>

o~Hfrrom the memory write buffer is driven to

···:::\\:.:.:.:-Ht~:i:~{<::::.memory on the next memClkR. After the write,

·:-:''<l@@Urnhe quadword pointer is reset to 0, and the cache
::\/line pointer is incremented so that the next WRxxx
will drive the first sub-cache·line of the next line
to memory.
111
·:·:·:·:·::·:=·

-:·:=:=:::=::·

..::::::::::=:::::-::}}'.=

··:·::::;:;:;:;:~(}tt.tt:::·
<::::::::<:;:;:::::::::::::;::::•.,..::::::..,,
.. --~.;,;,;.;.;,;~..,._

Data from the memory write buffer is driven to
memory on the memClkR after the next memClkR.
After the write, the quadword pointer is reset to 0,
and the cache line pointer is incremented so that
the next WRxxx will drive the first sub·cache·line
of the next line to memory.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

, i·J~4.3.3' liJJus ~i~;Ij Descriptions

-<<><: :::;-l1·3.3._lf:::!p1bata<31 :0>
····::::;::::::.::;:

.. ·:·:·:····

. \i i;)~~:I,!,': ' ~=t16fC:kB~<!;:Uc~~~(21071-BA, 21071-DA)
··--:'.<@i!tfil)J:pput
Sampling Clock Edge: clk2F
··::::::::::::::;::::::::::::::;:;:··
·'.·:-:·: .·.··:·:··

14-10 Digital Confidential

1
epiDa~·is a32-bit hlilireclional b~ oonnecls the 2-lQ71!f i~l!~l l i!f!Y
whlOO

143 3 2
· •

:~~:~:::: Bidirectionru (21071-BA.. 21011iJ'l«i(~illl\'l'l~l!'~'lf{;1; ; \:\j~}\)iW
~~i::~=;n!d~~:~~e: clk2~[Wf :;;tf;'j;;;b:''<i\Mi;(~'l!l~i!!.\i>
epiBEnErr<3 :0> is timed with epiData. During:¥ml.µ§: . transfers from the
21071-DA chip to the 21071-BA chips, thi~.J:ield fridi~~~§tw.hich bytes of the

~~:;~:::o~:s;~~~: ~e8fsev':!~Jt:IPl1~~~ll£:l=~; ~~ ~U!
transfers and ignored on I/O read tranii~rs. ·.:,:::\}Jj]}l::\. .

During epiBus transfers from th~r:g~lU~tf§A. da~·:::~hl~~)~o the 21071-DA chip,
epiBEnErr<O> is asserted if the:]qpgwodU@!mg sent on epiData contains
a parity error or uncorrectabl.~N~C.P erroi9{ijp~QEµErr< 1> is asserted if
the longword being ~:~·pt on eP.iP~~d~ontaineH?~N~'orrectable ECC error. See
Table 14-4.
./Fll>
··:·:=::::{tftfl':=:::...
·.·
.. :·:<. :· ::~: ~::::.. .•:::::::::::::.•
....::::~=\}·.~ ~-.~.~.' ~. ~ ~.:.~:.:.~.'.:.~.·.~.~ :.'.~-.~ -.~ /:: .

. J~lf]:~\\::..
Table 14-4 e~~@§n,~rr Fdri¢119g!:::::,..

·:-=\(}'·

Signal

Transfers from 21071-BA

epiBEnErr<O>

DMA Read I/O Write
U ncoITectable EITor (this
LW)
DMA Read I/O Write
CoITected EITor (this LW)
Reserved
Reserved

.·.·:·:·:-:·. :-:-:·-:·.··.·.
.. >:·:·::::=:::::::::::::
.·:·..

····::::;:::~:::::::::::::;:;:;:::·

epiBEnErr<}§f::{t::r: :)',pj~ta~15:8;if\;yte enable
:::(~f j}.
.·:·:-:-:-:·:-:·:·
..

::::::Jtl11i111lt~:::I!::: :: :::::
:::::::::·:·;:;:::::···

·.·'.::::;:::::::::::::::::::::::::::::::;:::::::::::::::::::::::;::··

..,J:\\i~pjFromIOB indicates the direction of epiData to the 21071-BA chips. When
·.·..·.·.·..·. )} ,..,J]i]\jpiFromIOB is deasserted, only the 21071-BA chip selected with epiEnable
: ·::+:f.:f':::C ::@/'drive epiData<31:0> and epiBEnErr<3:0>. When epiFromIOB is asserted, the
.,,,.<::t.rn::1::'[,:~tW.:-BA chips receives data on epiData<31:0> and epiBEnErr<3:0>.

}'::!'L :'::.\:<,..

··.···
·.·. ..

Digital Confidential 14-11

14.3.3.4 epiSelDMA

~~!~!~Ei;= c~~@fr, t 1 1 1il!: '.'. ~l' ' r1 ~-;
1

11 1 1

:i::~~!swu;:!:; :ee ffe~~in1~:~nc:~J;;\1)\'.~;:~~lk:s~:!

(epiSelDMA =high) or the 1/0 read buffer (epiS~lllMAt~Jow):··::::/·
·.·.·: : : : -·
.,,,<<:l:l:]l\:\Iltt_:.:_:::
.::::·:;::::
14.3.3.5 ep1Enable<1 :0>
···.;.;.:-:-:-:·::;:;::::..
:/)~~{@{{\(~{:::::::;.:::::::::·.·.
. ,.,., , , ,.,.:, .
Sl.gnal Type·. 21071-BA Input ::::;~:?~~/
Signal Source: 21071-DA
_.,.,.,., J]UL
···'<{}\j:\\Jt?t
..,.,,,.,,,,,,,,_:_:_:_:_:_:_=_=_:_'. :_ :_.-_::,_.:.=_:,_::'
.
. :·_.,_.,_.._

Input Sampling Clock Edgf.#:~)l.~t::::.,.
Output Clock Edge: clkl~i:jf[[(}>':: · ... :.(~~:~:;;;;;:::,:,. ::

::::::::=-

.::::;:;::::-.:::::::·:·

The epiEnable<l:O> ~ignals ~~Hii~grted by'''tni:::?.I071-DA chip to the 21071BA chip to indicate . :t&•t.:- the 2lO.Z:i.4DAJs perforfuing an epiBus transfer. When
epiEnable is drive1fiijW~
~~::,.~piD.ati\:\~fi.ij}~p~Bus
control signals are ignored .
. .·.··:·:·:·:·:-:-:-:·:·:·.
··.···.··:·:·:··-·.·.·.·.·.·.·.·.·.
epiEnable is us.,~::.t.<> detEH4i,pg~~::wJ.1:ich . idhiJ~rd within the octaword has to be
driven onto antUri~tiy~d
froffiHiJ:i~}~PiPata
bus in the following cycle.
····::;::::;::::::::::·-···.·.·.··,
....... ·.......................
_

The "command" i·s:''MW.4Y~A~~nt lcye).~:::prior to the corresponding data.
Table 14-5 indicates ~~gi:::rl¢t.i9xt perlormed by the 21071-BA chips based on
the values of...·.-.;.:"~i.~#i.91~,. epl'~mlOB and epiSelDMA.
...;.:-:-;-:-::::::::::;:::::::::::;.....
-:-:::::;:;::::
:·?:\t~/:=·

.· : : : : : : : ;: :·

· -:-.

Table 14-s!'[iElfo11EIJfep:1'IP.s
Interface Function
:-:-:-:-:-:·:·:·'.·'.·
. :-:-:-:-:-:-:·'."
·:-:-:-:-:-:-:-:-:
Function

:3:j~?t '<:xl:.i:~=-·_,:_:·.:_:_:_: _,:_.~_: ;_: _.~_:=.f_:l _.\l [:_.\i: :F>' x

-:·:;:;::::·.·::::;:
·'.·'.·'."·

.A;r,~(:~; ! ~!l _.•:_._i)_:·_~_: _:_i.•_; ;ni;gl ff111!;•~>
.;::::::::::·

.-.-.-.·.-.:...::=·:-:-·

.-:-:-:-:·:-:-:::::... ·.·

··.·.-.·.·.

:-:-:·:·: '.·'.-'.·"-'·

x
0

""·<:::::="

14-12 Digital Confidential

No action except for possible Line
Invalidate; epiData tristated.
The DMA read or 1/0 write buffer is
driven onto epiData.
epiData is loaded int.a the I/O read
buffer.
epiData is loaded into the DMA write
buffer.

14.3.3.7

14.3.3.8

ioLineSek i:D.$\:]:g::::ii~ia:l:l~ s.ele~t:::fhe cache line of the DMA read or 1/0 write
buffer, tha~\:jlj~:~ to.::::b.~\::lo~dgd: from the sysBus.
'.·>:·:·:::;::::.:.

14.3.U

...:::;::::::·~)·:

(;:;:;:;:'.:::::

:;,11?!!~1~?,~~put

.·.·.-. . . .-.. . .·.·.·.·.·.·.·. . ··::::::QgliS~:::Plock Edge: clklR
.·:-: : :~:rn;: :=~: _:l l\ j\ \ l \: 1:·:j.~:!: : _: : '.!: '.: :... Inp~!j::~!l~~ing Clock Edge: clk2F
··::\J\l:h.~m epiLirielhval is asserted all byte enables for the selected cache line will
.)H\::~teared in the DMA write buffer.

::::+?.:!·l:l:i:\:\:-:~:4:;3.:~4i·:·:i·!i.lfemory Signal Descriptions
·:.::::::::::::;;::::··:::\::::·····:;:·::·

. ·-:=:=::t:. ·.-.::{::::.. ~?{::: .·.·
. ·-:::;:::::;:::::;:::::::- ~~~}
·-:-:-:·::=·::::;:>>

:-::::r

Digital Confidential 14-13

14.3.4.1 memData<31 :0>, memPar<O>

Signal Type: Bidirectional (21071-BA, Memory)
Input Sampling Clock Edge: memClkR
Output Clock Edge: memClkR

is driven during all transactions except memocy>feijQl~ktP:uring reads,

=-~:~~~!i~:;;!;~i::'!n:n~::cilfiMl~~=!!Jt~P~:~r:!~~;or

driving out write data or latching in r~~~. -dafii::j~\]~P~trolled by the 21071-CA
chip using memCmd<3: 1>.
. ·.·.· :·:·
":::'t\ltJl?

<{f}/l\ltL::::

·.·.·.·.·.· ... ·.· ":::'.:'.( ::::=:=::;:::·:-:-:.:-:·.

14.3.5 Miscellaneous Signals

::~:r·\~{

·: : : : : : :·

.:·:;:::)~::::: :::::;::::::::-.

·:·:·:::::::::::::::::..

14.3.5.1 Clk1 x2

Clklx2 is a clock in.P.~t:::;which::::~®.P.Ji...~:Jl clock·:::&f twice the frequency of the
DECchip 21064 sysClJO~U,,.. witli:::iflm~mµm period of 15 ns, and a 50% duty
cycle.
· . :t:tt::;:::::::\:::;.
··::::;::::~\i!i\\,:\:!;_:!:\:j:f·

./}>

··:·::::::;ft't\\::::·.

14.3.5.2 Clk2ref

··-:·:::::::::;:;:;:;::::.:·:-:···

Clk2ref is a si~~Fiiji.Jit.Hw}lich I~/1&,w::lwhen the assertion of clklx2 corresponds
to the assertion of sysdll.f):µ:g:,_ Th(t':teceived signal must be setup to the
assertion of clkb2..
"""'<>HY@\:>:::;.
.-:::::=::;:::::

14.3.5.3 reset_I

····::::::::::::::::::::::::=:;:::

·····

....:::=:::::;::::;:;;::::: \L:]. :i.i.:iiiiv

~~:~ion 111~e~.r~!i~£~ i~lintemal iogic and state machines to their initialized
14
4
.3.S.

\t::::::11:ttr

-:J:\@l/

::3 0r:~•ltfl~es the chip into a mode for chip testing. testMode

is4~~1J.4.~~ to be used only during chip testing, and must be tied low during
. ::::::::tiht~::\:Poriiiijj:~:iyit,~:pi operation.

<!l~\] (;i)';\)l,jjl~pod:'•l•~~eak internal pull down and a Schmitt trigger input.
-=-:-:.:·.-·.·.·.·

....·.··:::::··-·.·.

.. ><1'4.3.5.5 JtrJ$ate_1
::;::::::::>> :;._.

··:·:=::rr·

,:J\~\\\~~ertion of this signal tristates all output and bidirectional drivers. tristate_}
0

' "' :i~lli~llli~~~;:d~sf: ;:: :::::n:~~:pt::n::::::~input.

14-14 Digital Confidential

pT~om

1u.5.6

,,, ,

: 1!:~ '.:!l!i~l t;w'

fjli'.'

The pTestout signal contains the output from the Parf\mit.ti~NrfAND :·ti:~fi~>
required for testability. The testMode signal must be ,@i~~d[j::f.4f:\:eT~st0ufto
be valid. pTestout is intended for use only during c}!jp{~sting."'''\{:}fFJlt:,:·

<ll!'i'lili~\lt . <@?

14.3.5.1 eccMode

!::~;!~;;~~:~~!~!~: ~a:~'!l!,.;~;;~~;;~;re
!~;:~:;::~~!es~!~:~~.~~~J!IF~~-~~!di.:~~~::~:rd
21071-BA chip performs data ch~g~~1:[11J:5prrectiorts~[:[i}:/·

eccMode should be used only in ¢qujlliiiti~tt.\::W,i.~}1 a 128-bit memory data bus

(using four 21071-BA chips). ,j[j[1~_il.·.J_;· 1.)_:l.:!l_;l!.l!_:i:.>.:'.:·_.,_.,·.·.
.,}::::i::tk./=·

·-· : : : : : : : :'1'.~'.·'.:·:;.·1:1:1·;:;: :, ..
·.·

-------~~......---'''''_...t?t§IP.t,._·
.:',·..:i.P" - - - - - - - - - ·.·-:::::::
eccMode tie<}, higlt" v4tli::WJq~MeriFt1~\::}pw will result in undefined
behavior aµJ:Jj:':ffi~y
caus'e:::-~g~ to system hardware
··:-:·:·:···:···········:;:::::::::-:·.
·.·.:::;:::::::::;:::····.·.·.·.·.·.
··:-:·:·:;:-:))}~:}~:::-:;.

·:;:::::;:::::::=:::::: . . . . . . . .

··.·.· ::::;:::::;::::::::::>:·.

eccMode has a weW:.'Yri~~l~~;:;pp,!ld~~~·· and a Schmitt-trigger input buffer.
.·.-:-:.:-:·:-:·:··

·.·.··>:·:.:.:···:·: :::::::=:=:--

~~---...~/~':':'.'~<:~''.':::'~~'.·":~'·.. :~.: :·: ~:,·.:~.~~....;.;;,;,.__ Note ~~~~~~~~~~~-

Changj\jg:·:¢:~c~l~''''af#.¢r reset is deasserted may result in undefined

t. . :.,;:::_:;:;,_:

behaviQ,;_ . \1[.[[_it{:_:jj:-..
.::::::::::..·.

:t::::\:::\:::::::·

14.3.5.8

Y!(«I:.

.. :-:-:-:-:-:-:-·

·.·.::::t::::l:\\li:l,l!ll-ll...il::,.ij.l.::\j.l:i\:::::w::':'

Siifiilrn:WY.Pe: 21011-BA Input

.-:-:::::::<:nr:::o::>:·..

/;!1l;!J¥!iMfi\(l•1:~~,~~~::~7n::t to the

21071-BA

chip that indicates the width

<Ut??'·

/]ffi::the memory data bus. wideMem tied high indicates a 128-bit wide memory
''\?tt:: ;: : :-: :·:-:·.....J:?fQ:afa bus (DECchip 21071-AA); wideMem tied low indicates a 64-bit wide
. . . """"' "'.:' J:\{[':::·i]:fuemory data bus <DECchip 21072-AA) .
·.::::::::::::::::;::

.:::::-.

:-:-.

.·-::::?~~~~~~~~~?W~:-· ·=-:-=-:-·-·-::::::::::::···-·.·.·.·

····.····

Digital Confidential 14-15

·::~):}::;::::::.

Md~em

·:J%((:::::::::·:·:·:·::::::=::::\{~\:::: ..

has a weak moornru pulldown and a

Schnritt-ttjmr~~!:~t:::111'j;\,,!lf
: : : :)i: i: :·l \.lj: : )j ·.: 1~·i:1.~: ~:i:1:i: : : : ~: : : :.. · : : ~:':)l\j\j: : i:.: : : ~: ! I\~\: : = ·

- - - - - - - - - - - - Note

Changing wideMem after reset is deasserted D}fY:~:~~~ult i~::~:~li.l#fd
behavior.
.. ..
<::tI:.:·:.::\l'!j::~::::~r\::::..
·:::::::::::<
. . .:~::~rn~~~\}::·
.·.;.:. .·.·.·.·.·.·-=·:·:·'.·'.·.·.
:::::::::~:~:~:~:~::::::::;:::::::::;.

'·'.\f'.·:::::::{\~J\:·
·:::;:·:;:·:;:::::;:;:::=::::::::::::..

14-16 Digital Confidential

14.4 DECchip 21071-BA Pin Connection TablEt:/t>::::=:·.

·= =<:;~: i: : i: : :i: i:j-:): : : :i: : : : : : : =: :.· .

Table 14-6 ::;htp 21011-BA Pin Asstg~ments,!l:l\~ht~ll._r With
M&fillj=rrace
Na'Mi/Httl=>,=··
···=:::::;:=:;=:;:::·
..
···::::::::::::::::::::::::::;:::=::::::-.
21071·BA

21071·BA

21071·BA
Chip #3

Pin Name

Chip #2

.=::)tl}:i1911-eA==\(}]j{}}· 21071-BA
.··=:=::=t'\'fP"!~tf.1
=tqg=:: Chip #0

vss

wideMem

vss
vcc

vcc

epiBEnErr[3..0]

ep~~m~rtl3 ..0] ··:·:=::tj:~ii.ll~rr[3 ..0]

epiBEnErr[3 ..0]

epiData[31..0]

::ata[a1.

eccMode

;...i,.r!l~llfill'i11;:at•[a1. 01
epiE~iJ3] i\~'l\iiiii:.:.. qr epiEnable[l]

epiEnable[ 1]
epiEnable[O]

memDatafti.f~~iil=::::-. memD~ti_ijj~~M]

memData[31..0]
memPar[o1

=:'J·m~Wf'-tj:a1 ···==:=:=:::{il·:i:l\_:·::l:i#.wm?.arl;=]::::t·

epiData[31..0]
VSS

epiEnable[O]

memData[63 .. 32]

memData[31..0]

memPar[l]

memPar[O]

vss

drvSysCSR

drvSysData

subCmdComnion

subCmdCommon

subCmdB[O]

subCmdA[O]

··:·::::::::=::::::::::::::::::::::
·:::::::::::::::

·'.·:-:-:;.·

.:=::::::::.:-:-:- ·.·.···

.··· ..

·.·.:·:·:-:-:-:·::::::::>:·:;:::::::::;.•
vss
.·.·=,,.W:Y§y~pat~=<\\/:\\:= :::::rn::::4.zysysData

drvSysCSR
drvSysData

{.l!:.:::.#i'-mi~o~ ===<tMtibCmdCommon

subCmd(l]

::::~fll\l!lil
sysz~~~~:.il!!::::··

·:·::::::::r::::::::::::::l:l\:11:11:11i:i::::i::::i:::::=··

syiit'~'l!\j\ltt:=:·.

sysCheck[21]

subCmdA[l]

Ti.e off to vcc or vss with resistor
sysData[95..64]

sysData[63..32]

sysData[31..0]

7ie off to vcc or vss with resistor
sysCheck[14]

sysCheck[7]

sysCheck[O]

. ................. .

··:·:;:·:·:·:·:·.·.

: =: : : : : :1\.·!\l!, ,: ~: : : ~=: !·!.'·: i.:[: :i :=:= :.._._·. .· =: : \@ji~: : :.!1lil_~·.·.. l_l_:.l::_:~.:~-=.~:~_.:~:_t·
1:_::_:_=:_;·_1_1·...

:·:·:·::::::::

··:-:;:;:::;:::;:;:;

.......

...

..
.........
·-:-::::::::::::::::::::::::::}}~:/

..
··.·.

.. ... \}~ :-:·:-:-:::::::·.·

.·.·.·.·.:·:·:·:·:·:;..

··:<::/~}\) ...·..

Digital Confidential 14-17

·:·:·:·:·:·:·:::::::::::·:·::::::·:·:·:·;:;:.

Table 14-7 DECchlp Pin Assignments

::::=:dtr:=-:::::\!j\[]ItI>:::jf{:?· /tt?·· -.·: : : : : :. . .: :·:. .

210Ji~:;:: ml,jl(;I;;1111r t'
1

DECchlp

~011-a:odule :9M~f!t..
~'l)@[\jf\]il1(1 .·l_1=:='.·_:_: o= ~.=: ·_._!=_=.=~··~I!!'
:· =· :·,:_~:

21071·BA
Pin Name

21071-BA
Chip #3

Chip #2

eccMode

vcc

:::::1::::··i!!:l:[::j:::::

wideMem

vcc

VCC

--:::;:::·

epiBEnErr[3 ..0 J

epiBEnErr[3..0]

epiBEnE'!f.~,,q;t/·:1·11t11m~,.::@

Trace

.•.;
flV

~ 2: : : : : : : : : ·:\: :=: il'['i:i: : : : : :·.
""·:·:". \Y~C

vcc

·">:::{: ;:;:;:::i:;:>="· vcc
epiBEnErr[3 ..0]

epiData[31..0]

epillata[31..0]

epiDat~fu,:f':~g~i=.:_::·!:::!!:::::::::::::::~piDai'J[i{~fl-Oj

epiData[31..0]

epiEnable[ 1]

vss

epiEnable[0]

epiEnable[3]

':Utt' ··==:::::::r:n::\l\t::\:-.
e,,ffl~-~ltf.l
·=e~J.jble[l]

memData[31..0]

memData[127 .. 96]/\:::$.~mDatat95M:Wf:f\: p1emData[63 ..32]

memData[31 ..0]

memPar[O]

N/C

epiEnable[O]

_·.=·::=.·.:_:.::·_r,=.~.u:r::t:yttH::
..::·:::::.i~f~\:::..

::._:_:_:.

t\:j_j!.!iil~t\Ht::::...

-.··=::<(\\ll>N/C

drvSysCSR

vss

drvSysCSR

drvSysData

subCmd[l]

subCmdCommon

subCmdB[O]

subCmdA[O]

memCheck[7 .. 13]

memCheck[0 ..6]

subCmd(O]
sysData[63 ..57]

sub~~l(ij.:·]/:>;:,... subCfudA[l]
.m~mChec~tii1~~[~$1. ·=: ::::m.~mCheck[ 14..20]

sysData[56 .. 39Jt: ?? ;.:,.(.: : ;,: : ;:;: . ':{:/·

'''?@I?ne off to vcc or vss with resistor

sysData[ 38.. 3~j:l\~,j\\)'"
~ysQb~~kl2.1#~J]
.·.·.-... ·.·.·.·.·.·
.·.·.·-:-:-:.·.·.·
·.·.·.·.·.·.·.·.·.

sysCheck[20.. 14]

sysCheck[ 13.. 7]

sysCheck[6 ..0]

sysData[95..64]

sysData[63 .. 32]

sysData[31..0]

'lie off to vcc or vss with resistor

14-18 Digital Confidential

Table 14-8

21071-BA
Pin Name

eccMode
wideMem

21071-BA

Module Trace Name
21071-BA

Chip #1

Chlp#Oj\\::\. .

vss

VSS

vss

.. ··.·

::::~~;OJ ===~~;OJ ::4;11,1t\ti,'ill•;fa
::::::~~:

epiEnable[l]
epiEnable[O]

1tK~~ ··w;;·111;;v

...: : : -:·: :~ : : : : : ·:· · .· · : :\t~: =: :=,_·.i·l.l-! !.i : i:i:i:=: ~: : : ·

memData[31 .. 0]
memPar[O]
drvsyscsR
drvSysData
subCmd[l]

mem..Data[ 63{4.i1:)~)'j~;:fuemData[31Mff:

~ll
<i~\1,_:._;_i.'.Pa: ,:;: :;_;._=_.=_: : :.: ;·.:[:!l·:.:_:_: : ..,_; ~
. :::::t'::,=::::t:\:;:,..

-=+: :1·!1 -!1~ ' ' : -.

···:::.
··=·==::::=(:l.~~~p,~ta
s~bc~iB[U

p:~:::rnrntt::drvsi~cs'k

:m:::(.!R~¥sData
subCmdA[t]

subCmd[O]
:~~?~.m:dBfQ~jJ!:: :>\> subCmdA[O]
sysData[63 .. 3~1': :~Y#.Q~t~[127J}~}:f'': sysData[95 .. 64]
sysData[31.tf:fi?.. ;;;~p#furn~-..32]
sysData[31..0]
·.·.·.·.·.·.·.·.·.·

sysPar[l]

·.·.·.-......... ·

<::-:.:-:-·-·.·.

:t1:1L.. .::::~Jicbecl((~J]

sysPaf:~~l~::::::· ·:::::::::::1···:.l.::::·.ij:.:\j~~:2h~l11

·.·

·-:-:-::::::::::::·

.·.·

sysCheck[14]
sysCheck[O]

:::::::::::}~:~t
·---:-:-:-:'.:::\::·

Digital Confidential 14-19

14.5.1 Signal Types

::tif.i~~l.~\j:4t::i;n
f(;~11r·······c4;;m;,1111·111;>

Table 14-9 describes DECchip 21071-BA signal types .
section.
Table 14-9 DECchlp 21071-BA Signal TYP!:!:
Signal Type

Description

Standard input only.

Standard output only.
Bidirectional.
Power

1/0
p

·:·<t::~::iFl\tt::
.·:-:.::.::::::::;:;-:::·:-.

.. ·::::::/{fff :·~:::::. .
.. -:;:;:;:·:::;:;:::;:;:;:··

··:·:·:·:-:.:·:·:·:·:·:;:.:·:··
..

Figure 14-1 shows the chip signals.

14-20 Digital Confidential

·.·.·.·.

Figure 14-1

:-:-:-:-:-:··

outVSS
oulVOO
epiEnable<O>
epiEnablec1>
pTeslOul
lrislale_I

155

150

leslMode
reset_I
ec:c:Mode

wideMem
lnpVSS
memOalacO>
mem0alac1>
mem0ala<2>
mem0alac3:>
outVSS
mem0ala<4>
mem0alac5>
mem0alac6>
mem0ata<7>
memOataclb
mem0alac9>
mem0alac10>
mem0atac11>
mem0alac12>
oulVSS
oulVOO
mem0atac13>
mem0atac14>
mem0alac15>
mem0atac16>
mem0atac17>
memOatac18>
mem0alac19>
mem0atac20>
mem0atac21>
outVSS
mem0alac22>
mem0ata<23>
mem0atac24>
mem0atac25>
mem0alac26>
mem0ata<27>
mem0atac28>
mem0atac29>
mem0alac30>
mem0atac31>
memParcO>
inpVSS
oulVOO.·.
inpVott::

145

140

135

130

125

120

115

110

105

inp~I

inpVSS
inpVOO
outVSS
outVDD
sysOalacO>
sysDatac1>
sys0alac2>
sys0alac3>
sysData<4>
sysDatac5>
sysDatac6>
sys0ala<7>
sysDalac8>
sysDalac9>
sys0atac10>
oulVSS
sysDatac11>
sysDatac12>
sys0atac13>
sysDalac14>
sysDalac15>
clk2ref
inpVDD
clk1x2
inpVSS
outVDD
outVSS
sysDatac16>
sysDalac17>
sysDatac18>
sysDalac19>
sys0atac20>
sysDalac21>
sysDatac22>
sysDatac23>
sys0atac24>
outVSS
sysDatac25>
sysDatac26>
sysDalac27>
sysDalac28>
sysDatac29:>
sysDatac30>
sysDatac31>
sysParcO>
sys0atac32>
sysDalac33>
sysDatac34>
sysDalac35>
sys0atac36>
oulVDD
outVSS

ll)
0)

.·::::::::.;...

. ., '.~il l 'li frb".'· •g :e
··-=::::::::::::::::::::::::::::::::::!~

•

'"' ':

:~ 11Al~8•11
• •

. .• 8 •

•m 4u '411•H I u
0

·~~A •Hugg•
11

l! 'e'e~ 'e 'e'eCI v -i< v cl! v v v Q 21 ~ v v v > g v 'e'e~ oe 'fJ'fJ 1>"S11111111 '3 '3 '3 >> !e
···:::::::::::=:::::=:::=::=::::ii.:!!!!•!!.!!.!!.!! i 1 i1.l!-s111~ ~~11:i-s:.!!.!!.!! •!!.!!.!!.!! s!!.!!.!!.!!.!!.!!!!.!! !!!!.!!.!! i.~.~
··=:::::::::::::::::::::::::=:::'.:!.:§a aa a 21a 11 ~ ~ ~ ~ ~ ~ ~ ti!~ <g ~ ~ :!!
:!! a a a ~ 21 a a a Cl 21 a a 2121 2121 21 21 C! C!

··::::::\:('l@~E-Ha.Hi~ee" ::-u:u~ii

'.iHHHH :~HHHHH

·-··::::?'

Digital Confidential 14-21

W.O~TIO

14.5.2 Alphabetical 21071-BA Assignment List

.-.-::;:}~:::=:::::::.··

Table 14-10 lists the DECchip 21071-BA pins in alph~b.¢.tj¢.i.}i]~td~.r.
Tuble 14-1 o Alphabetlcal Pin Assignment List
Pin Name*

Pin
Number

di![~!lfJJ~ 'Wll,~flttl~Jt{J>

Type

I/O
I/O
I/O

IIO
I/O

IIO

3
4

204
203
201
200
199
202

51
103

14-22 Digital Confidential

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I

p
p

Pin Name

Pin
Number

Type

Pin Name

Digital Confidential 14-23

Pin
Number

Pin Name

outVdd
outVdd
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
outVss
pTestout
reset_l
sysCmd<O>
sysCmd<l>
sysCmd<2>

Type

Pin Name

183
205
1
16

:::::: iil;fllt~!!<!ii'il:llllill

.;:1~::!;::t:::::~::1:_111-11 1 ·1i: ·i ~: : : ;.

:
:

··:::1~litt::-:-. :::::::lill.!!llll:l-11-j'::lr ~g
;:~;;::~!1:··:.:::_:111:1·[.::il~;,~. · ·: :; : ~g

.<'!~"!im~-~3>

37
53
68
78

105
89
120
130
141
154
157
172{

: ,p,;ii'l:!=~i~11111' IE
P

:Jt::::1:::=:I:i:::!t!P.1lta<l7>·:::;;:::;::::--

)?\::··· ····-:·:;::q~tj9'~:~18>

!ll1ll!;lt11i1t

:::::::::-

70
. ::/)tj) ..

:~:~::::~: .:?·:;:; : 1:;:;_} i~=~1:1: :1~1:1i1: ./ .</'::: JJO
sysData<2> ·.·.···..:-:·

imr::::-- ]]f? IJO
.·:·:-:·:·:-'.·'.·~

::".!£ ·~1~(1!!lll=, ,.4;il1iif ~

14-24 Digital Confidential

128
127

:E!!E :

<<i~:::::::::mpata<22>

··:-:-:·:·:·::;:::

/(J~-~r

.·.:;:::::nwiP8ta<23>
··;y;Data<24>
sysData<25>
sysData<26>
sysData<27>
sysData<28>
sysData<29>
sysData<30>
sysData<31>
sysData<32>
sysData<33>
sysData<34>

·-:;:::::~g

E
E
vo

1/0

12s
122
121

110
110
J/O

119.
118

IJO
J/O
J/O
J/O
J/O
I/O
J/O
J/O
J/O
J/O

117
116
115

114
113
111

110
109

Pin Name
sysData<35>
sysData<36>
sysData<37>
sysData<38>
sysData<39>
sysData<40>
sysData<41>
sysData<42>
sysData<43>
sysData<44>
sysData<4&b
sysData<46>
sysData<47>
sysData<48>
sysData<49>
sysData<50>
sysData<Sl>
sysData<52>
sysData<53>
sysData<54>
sysData<55>
sysData<56>
sysData<57>
sysData<58>
sysData<59>

Pin
Number

Type

Pin Name

108
107
101
100
99

98
97

96
95

94
93
92
91
90
88

Digital Confidential 14-25

14.5~3

Numerical DECchip 21071-BA Pin AssignmentJ,J.§l
Table 14-11 lists the DECchip 21071-BA pins in num~dl}:i:i.f:l~tt:. ·.
Table

14-11

DECchlp

Pin Name*

21071-BA

Pin
Number

Numerical Pin

A~:~-::!illlll!:tt'
'·'.·:····

···:·'.·'.·:·:·:·'.·'.·'.·'.·'.·'.·'.·'.·'.·'.·'.·.·.

Type

p
p

IJO
IJO
IJO
IJO
IJO
IJO
IJO
IJO
IJO
37
38
39
40

41
42
43
mem.Data<28>
mem.Data<29>
mem.Data<30>
mem.Data<31>
memPar<O>

inpVss
outVdd

14-26 Digital Confidential

45
46
47
48
49
50

IJO
IJO
IJO
IJO
IJO
IJO
IJO
IJO
IJO
IJO
IJO
p
p

~.:,:.1,:.:,:.:;.,:.:_,·.·.·=,• ~~:·=::;·i:_:·;:::_;_:_:_::

.=:.=.'=•:.:.=;,_·•.,:·:·= ·:·=
._': •.:_.•:_,:. _.=.=· =·=· · ·:.jl l;,1111: ;:·=· :·;· :,:i: _:r:.:!:i.·_.\.: .·:\.:: : ·:.: : :=.:·.:i) .
1..=::.::'.::.:r=:

:::
.. .

::
.

Pin
Number

Pin Name•

inpVdd
inpVss
outVss
outVdd
sysPar<l>
sysData<63>
sysData<62>
sysData<61>
sysData<60>
sysData<59>
sysData<58>
sysData<57>
drvMemData
memCmd<l>
memCmd<2>
memCmd<3>
sysIORead
outVss
sysCmd<O>
sysCmd<l>
sysCmd<2>
sysReadOW
drvSysData
drvSysCSR
subCmd<O>
subCmd<l>

ioLineSel<l~JI:::}:...

outVss

.........
ft\(

·:})))'.::

51
52
53
54

55
56

57
58
59
60
61
62
63
64
65
66
6]::\\::::!::::[j::::::·

ss·::::qr.

Type

Pin Name

;.:'~1~!b!!ili9':Wi{j,\i'-'ll;l!ik

~ '~i:::~:~'. 1!1~1 ~,!;l> ' E
~f:,p~ta<5i~ii{:{]JJft~~-

1/0

~~ ;;511~!1'1~!;;1:~'.(t~

91
92
93
94

110
110
110
1/0

I . ·.::::::'lH:::\j:\·\\illil"!l"·i.~·l~i~~~::::

····==\(q~p&ta<41>

97
98
99
100
101
102
103
104
105
106

1/0
1/0
1/0
1/0
1/0
P
P
P

1/0

I
:=:J:]::::liiilil:i!Jf~ta<47);'""\/:..
1 .·.
··=·==:::=::tt:Ml1'~46>
~i:lhiti
sJSJ.NW.11'>

rrmr·:·· ··

t{\IIl::\l:=\.,..

sysIM.f44>

·-·~y,Data<40>

7•(:=::::::::=·
.:.=.=":(.,,=.= _·=a=·_·: :_,·:.:=_,:_:·.:,:_:,_r=·

.;::::\:)~::··

/~ft~

sysData<39>
sysData<38>
sysData<37>
outVdd
inpVdd
inpVss
outVss
outVdd

P
P

Digital Confidential 14-27

.-:::::::::=:;::::...

:::)~~f ~~:?··

:_.·:~·_.:~.;_:'.= :~_-.:·~.~_:~_:·:~ :~.-_:~.::.~:_:~_::~:~:~·:·:·
..
::·;_
__ ..
::·_
... .. ...
=:_... ..
..
::.:;
::
.... ........ ... .. ::
........ ..

:.:'
.. : ·

~_i·.:.t:_~.: _:~.:.: .}_: .:~.·:.: _/

. · . · ·.··.··.··.··.· . .
·..

:=...
.

Pin Name*

Pin
Number

Type

·•![~~t_connect these pins on board.

·=:::::=::;: ..

:(}:} ·:·:·:·:··

:::::::::{::

.):}:;::: ··...

...

· :·:·:.:-:.:·:· ·.·.· :-:-:-:-~\)=·
··.·.·.·.:-:-: :-:-:.:-:

..
·:-:-:-: ...

14-28 Digital Confidential

Pin Name

.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·..

.Jl~::jj!f!f:??tll\=::.

_.,:;.:-:-:-: : : ·

. : : \

~ -~ ~./.~=.'.~-~\~_j:_J.:~~~- ~ ~-~~~?:
=.;

·::::::,:_·::·,'::.:·.'.·.'::::.:::::.=:.:_:.::::·

::::::::::;:::

Pin Name•

Pin
Number

Type

Pin Name

epiData<21>
epiData<20>
epiData<l9>
outVss
epiData<l8>
epiData<l7>
epiData<l6>
epiData<l5>
epiData<14>
epiData<l3>
epiData<l2>
epiData<ll>
epiData<lO>
outVss
·outVdd

-:-:·:-:-:.:-:-:-:-:.·.·-:-:.:-·-·
...
·-:-:-:-:-:-:-:-:-:-:-: ..

·.·.

···:::::::::::

·-:-:::::::·:::::·:·:::::::;::::·:::::::..
·-:-:-:.:-:-:-:;:::::::::::::::::::

Dig ital Confidential 14-29

··:-:-:·:·:<;

...~:.:,.. .27.9o ·~~a~=:

:tose.:: 1.106

rct. ~9=~$Q.. 3o.77:' a~~gf m2:11

:::::a::::: ~=·M~~r: :~s.1 o 1;ooit :MtQ~=: >.
. G .tM!~:: \~.33
H
.5Q(t~$.C
J
9A~:: :JS.62
. K :::@~~(' 3.85
:::::~ : : n,:;:t:l
0.23
:::::-.:::: /Q~?5 0.35
:\~:} :)~$JtREF
S :: :)~$~~f~$.:::

0.009 "(}:1:}.t~: /
0.0197 BS(f
0.018 0.024
0.136 0.152
0.005 0.009
0.010 0.012
1.004 REF
1.004 REF

14-30 Digital Confidential

LJ-03666·TIO

DECchip 21071-BA Arclill;i!~iQlllierview
··:·::::::::::::::1::ij[\[::.:::::.:·[l:i::::::::::::..

··:::::;:::::::::·

15.1

Digital Confidential 15-1

Figure 15-1 DECchlp 21071-BA Block Diagram

NOTE:
lWS • lang-(32 Bill)
LJ.QSHO·TIO

15-2 Digital Confidential

•

21071-BA data chip #0 connects to longword 0.

: :~~~~~:~ :: :::: : :::: : ~:•:: ~~ii,\;l(ltillith
•

15 2 2
""

21071-BA data chip #3 connects to lo~~Q.tilitQ:{\::==·.

· =-==t:{\ j\ \j: i: : : :j\ j\:)): :

~:~~=r of 21071-BA data ~tifii;:::!!1l1t~::~ the
chips

width of

the memData bus. If the width of thefab.iffilli.ti:\:hh~t.is 64.:bits, two 21071-BA
data chips are required (DECchip 2lQV\ftAA). tt-:=tlj;.\\j\fiqth of the memData bus
is 128-bits, four 21071-BA chips ~:::f~q~~d (DEd=eli!jf21072-AA).

!8.!~!~J~~:ta :hip co~11;:•._,,emData In 2-chip
•

21071-BA #0 connects to 10n?:t=])fdHl.(memData<31:0>).
"'<Lt> ./\.:. ~=tittttk=:=:·..

;n 82::~~~B:~:e:!il1i;;:~di,~1rnata<63:32>).
•

21071-BA ;~@66l!~~:=:P> 1~~:11~1::i (memData<95:64>).

•

21071-BA #3 con~~ritii'!tp:\,~qpgwo;d 3 (memData<127:64>).

Each 21071-1}.f\f(lii\~~)~b.~P ri'&id,l!:!ttlknow the width of the memData bus for
proper ope~ti9ht==~nW.{i's 9btafrMd from the wideMem pin. The 21071-BA
data chips/jg:lJiot .~a· t~t!i.iow which longword they are connected to. The
proper latci!P.k. ~9.::an0.pg:\-Of data is achieved by appropriately connecting the

· · :~~~lf 8ll~-ili'V1mand signals (see Section 14.4).
15 2 3
E=acl'(:~IQ!J-BA data chip has 32 epiData pins .

.::::::Jl:.i[..

:::!i!~l=i[.,j,=i~j::\:\:j!jf:h~·;~ifiali~P.im~ of all the 21071-BA data chips are tied together to form a

-=··::J::.:\:=:]!f====·=········-====t:ti~?f:!?it wid(f~~~,ita bus.

<l!!fli~?-3 {ltcription of 21071-BA Architecture
·-:.:·:·:·:·

::::::.:;:.::·.::::·:·.

··.·.·. ::·::::::-::;::::::

·::::::{;}}:::::·
... ;::::=::::··

··.··:-:·· ;-·.·
·-:·:::::::::/:.
·:::~:~=/:.: . . . .

·:::::::/}\::·:·::::=}:::-:-:-:·:··

Digital Confidential 15-3

15.3.1 Memory Read Buffer

~or:1~~~~e~:!e~°!!:e~: ~;~~~'!i:: =~~u~~: :11ilfliiM.'\ read
buffer.
.: : i \: :·:.\j\j: : !\:\ \!.·.;:, .__
· =:=: : : : : :!i \ \i!!!l:·:!: il!\l: : :·
Each 21071-BA data chip stores four lof1:1.W9rds wormtJ~f:lq@ta anq . ,.
corresponding check bits in the memory==:f~~!(f qµffer. ··==:\ffiiif:t:::·..
•

In a two 21071-BA data chip designed.,.,.sy~-~t\i\tb.~ to~:Pi~fiige is 8
longwords or a cache line.
·.·.·.·:,::;:::::::=:r:c:t:...,.
·.·.·.·
····:·:·:·:::::::·:::::::::::::::::·:·..

•

A four 21071-BA data chip design~g'i:!§Y~t~m,. .~on"t:ffi$.illl1f'additional 8
longwords of storage; however, thi,~:::~itf.at~#-$f.•g~ is not/usable.

15.3.2 1/0 Read Buffer and Merge Qy~ji

'<i'.f!Jll!\\iib

On CPU-initiated memory trans'-~tiijri~\~\!\tWi~::J~µffer·.·;:~rlorms the merge buffer
functions described in Section.:3:•.iit. ori>dltMhitiated 1/0 reads addressed
to or through the 21Q'.71-DA 4tiP.ll\\\~ls butr~'f<i¢.t$/ks the 1/0 read buffer. The
loading of data intcrtb~l buffet'''iifm~t~fare controlled by both the 21071-CA
and 21071-DA chipi~l\i\t'·:.j)i:i!·l.::rnt::t=::... ·.·.:===:=::f:;:::::\t\:j.j·_.·,.j:::ttr·
Each 21071-Bl\{d=ata chitr=@ntai~.$ four.'''l()tigwords worth of data and

~:7a~s;~~d!~=~~~111.:~~~:~ui1:~ll~,~~~~ef:e~~i~~~ ~~~. for merge
:::::::;::::;:;::: ···:.:<:::::-

···:<<::::;:·:::·:;:·

:;s2~:~~i•lfl• tQ!:rf:!:s0~::·isE:!t :~~~::e4e;t;f:~~!s.
System de~i.m.ters . m~'.Y" cQ®.§e to allocate each entry of this buffer according to

::.~~;Sfo!filt£:,:~~,\~hip

may use the full cache line available in each

In tJi~K~:io71-AAf4!Wl.lQ72-AA implementation, two entries of this buffer are
alJpiji)ti.gJor 110 wnte data storage, and two entries are allocated for DMA

_ ,,f::tlI::1:r1r:8a:::a.~1[:i~~~~,~ge.
;;:1!!i;iiMW(jl• t;~~\11t~!:Pe:~~ :i:o:~~~~;l~~:~~e s~~:::t~~:~~;d~:
. :<:\){/

.::::::::::::::::;:::::::::::·

./9.f:Y~Jte four longwords of each entry, but the extra storage is not accessible.

·':=::::::='=\:/' ,:\:::)\}::::.:.,. ,i\t:\:iWfi~ loading of each entry can be controlled separately, thus allowing maximum
· -:,: : :;: : :\\]illl}]%\?flexibility in allocating the buffer entries to the 21071-DA.
·= = . >t:::,,.\jl.·:·l!\ll'l!Wb~:Joading of this buffer is handled by the 21071-CA chip, with the address
··=:::::t:pfi:nded by the 21071-DA on ioLineSekl:O>. The 21071-DA chip ·controls
uiifoading of this buffer.

15-4 Digital Confidential

.: :=:=: :~\il1l\l :1i!f:.·.·.·jl1:..=1: \[: : : :::::::::
: : :.

.·.·.·-:-:-:-·-:·.·
){~{:{=··

15.3.4

····

··=tr. : : ·.=-.=-.:.-:·. :.::_::.=:.::_-=·.-:-.:.·.·.

~~~:~~~~~::o~~~~s~!:~:. ~tr;rX8~:i~~~l~;tj~;v
system, only half the storage per entry is used. Tl)~kiitra storag~\:jJ.jj\jppt
accessible.
:./f\:::.:-:
.: {:\li[i: i: :i ! 1i!~li-:\[\j\il: : : :·=·
.· ·=:=: : : : : :·
The DMA write buffer is loaded by the 2:t.n1t-:PA. chip·===mta::J$.\)Jploaded by the
21071-CA chip during a DMA write transacti9g::~4pe sys:Bqj:~IW\he byte masks
are used to merge the valid bytes of data writter#lu:::itb~. DMA\Write buffer
with the background data from the cache Jine wh"ithfm~'.Ym~ obtained from the
Bcache or memory.
-;.·.·.·.·.· =-· · · · =·
·-=-=:=·=·:-:-:-:·:-=-:·=-=-=-=-=·=-·

15.3.5

=:::~:=~B=~: has fourt~~~'.l!~~~f!IJj~::ns longwords
4

of data per 21071-BA, and corresP.9#.diag\\in~k bits. The memory write buffer
is loaded by the 21071-CA sys.l~Ifoterfacijf:'®-4.::J~.nloaded by the 21071-CA
memory controller...:t:::~lt=.·
: :l~1j[ ~[j! =:l l·.l. !j.·\·lt:=:::. . ·. ·=-:=t\=:ti:\!il'.

15.3.6

!:
:1;7~~::~~!~1t~: !!lllbkinglcorrection
on DMA
transactions..
dala is read because of a DMA

~i.iJ.;:JJiemoeyHQ.fi'::».~~~~e

transaction (DMAif¢i~:l.:::9r a DNM.MW.nt~. masked), the data is checked for
parity/ECC errors." ?\\ll\=f=:::\=:::,.
·.· :::0:::)/.

If ECC is enabl~Q.,...?1.lld. °lh~i:ji#.}i.~~/memory data contains a correctable. error,

then the 2101:lf:l~ij:j~t~,.:chip<$~q(tS corrected data to its destination CDMA read
;:r~;J:ll~~j~~Jli'~~~ry Wri~ buffer MUXing with DMA wriOO data

for

If the . d~tat¢§#.t.~j~>an ~~Srrectable error (dual-bit ECC error or any parity
error)ffQ}~n . t}i~[!:!l!.Q7=ltlt~as notified (for a DMA read), or bad ECC/parity is
wtjt~f.H~ack int&!l.imbf.Y (for a DMA write).

;!h\\'Jll~fi,\i~~4ll~em~:=~k~~~;i1ty/ECC is calculated for the merged data
jf{:)?:-=·········:::==tg)Wj~ 21071ill~Nlata chip uses the same ECC code as the DECchip 21064

· : :· ·:::;;;:('?
=-::::::::::=-:>}(.
····=:::::::::::::::::::::: ·.·.·.·.·.

·.·.··:·:~~:~:~:~:)::::::::::::::'.~~=

\m~9.roprocessofl=t·Refer to the DECchip 21064 Hardware Reference Manual for

.·:{i:9~ruls.
.·:=: : :.:;: .: :.·.:.:.: .=.: :.

. :!~~~itt:}}~:}~:{;.

Digital Confidential 15-5

15.4 Data Path Logic
15 4 1
· ·

:!~~:us may used load the read buffei;;&,,~ !!111)buffer.
be
to
YO
In addition to write data, byte masks are ~.tored in:iitni.i~:D.:MA write ·:bti[tfer.

The epiBus may also be used to unload
as the 110 write buffer).

ttti.:J>:M.A r~·:aj[jh• •tXw.:hich also serves
· : : : :-- .;: -: : : : -.·.

···:::::t:::m]:]m:::::;::::-

.:<t\i[[[!:]:El:t::::::.:·.

--::::\tr

·=:::::: :;:;:::::::::;:::::::::··.-.

15.4.2 sysBus Output Selectors

··::::::::;:::~~~~~:~:~:~;~:~:~:~:~::~:··

Two levels of muxes select the output f~jff~h~\~y~Dat~4ji!~:~:::::[The first level

~=!~ee~:::c; r:~:~~:~:r:n°&f:!lli.E:l~~s~d

the second

!!;e~0:: !:o~~s:!~e~ ~8!>~fAlll~~~~=1~~ ::::~~:~~:~~:;;~
the other 21071-BA data chip_d~~li:~ts longW,'9.HQl:Jtand 3), and 4 and 6 in the
second cycle (while tb.~. other::2i!QZltij.!.\ data . ch~p?selects longwords 5 and 7).
:t:~:::::1:1:::r::·
·-·-:,\:t:;:;mr:::t\:::::·::..
·
Table 15-1 sysBus dutpUtil:l.o.:µrc;~t!:::\l:l\l:::l:::1:[:[::::t:;::··-·.·.

····:·:·:·:·:·:-:-:-:-:-:·:-:·:-:·:·:·.

·-:·:·:·:·:.:·:-:-:··

Buffer

Memory read
Merge
Merge and memory·read
. cP.uN~4ite:allocates
.·:-'.·'.·:·:-: .. :::::.:-'.:;.:::-:-:::-:.-:-.
.....·.·.·.·.·.·.·.
.

JJO read

.-:C:t.rn::[.\)i\!l_·i)\.:::·::.j::·:.t:·c_;.u. IJ(f~pace reads

t?::·. .. ..)){}?" :{~/}(.
The lower :tli:fiiU:\\\!f'lhe $Y~pata bus are controlled by a special signal to enable
the 2tQil~C4.:J;b.Uf::t.Q. . dri¥i.~H;he lower 16 bits on CSR reads from the 21071-CA
chiP.:.·.·-:·:;.;. W:'ml:~
the:'.:iiliiliil.m#tata
chips drive the remaining data lines .
.. ·-:::::::·:;:
·.·.:·::::::::::::;:;::::;:·:····
·:·:·:·:-:·:·:·:·:::::::::::::

.'H!,~fl!(lllJfliJ~;;

15-6 Digital Confidential

DECchip

•1
16

21071-BAt~l~it~fg~~:~~

S;:~:~;:;~:::~:::~:j;Ci!~~,~-i~~:U~ip

16.1.1 CPU Memory R~

1
Read data from memifY

on various

4!1111:1,\Jf;b, <tlt\fW

j~t;l9aded"'1ht~Fb.b.t:Jnemory read buffer by the memory
control machinejn the 2lPiltC.f.\. Thismij~tjif:ts available, by default, when the
sysBus control.l~#i~µ.ables··=t;~:::2:t.f:il·BA ·chips to drive the sysData bus.

The sysbus co~°flbtii~::=~~wis ~;~11.i.();w to indicate when the 21071-BA chips
must switch to the 'fH~ffi~J~~t::,?ctaWdrd.

16.1.2 CPU Mem~,!:¥[:::.:l~~~:::::~'itfi:l.l!l~IJ.im
The victim J».i.J~ifts:::=~9ijged from . 'the sysbus into the memory write buffer
through a lioloJ.ngJ~t~h. ,,,{f::the write buffer is full, then the data is held in the
holding lat~biW.1~iU~fiere'\[i~§:::room for it in the write buffer (the control for this
is proi~~?-''6.~1::1~1!)~,G~l::f]W~ chip).
Reivl. '~ta frorii\@.im9.fYVi:an be loaded into the memory read buffer

jjlJf;)~j~1i~!l•:I:;~:~~~:e::~:7:: :e:to ilie merge buffer

.. ·:\:\\{?
\thfQ.ugh the h6lCling pad latch. The merge buffer can never be full, so this
,/] ' ' ....,,.
,J)q~ing does not stall. If the write is partial, then read data from memory is
··::::::=:::' )\I:\t>:.,. ,JJfJ.~faded into the memory read buffer. If there is a victim, then the victim data
··::-:-:··i.::::::j\i~IiI:\:Ils written into the memory write bqffer through the holding pad latch.
:/\::::i:i!i·:::::.:-:·Mt:n~11 all the data is in place (memory read data, CPU write data, and victim
·:::::;:::::4~t,.i:)f the appropriate longwords of the memory read buffer and the merge
biilter are merged and sent out on sysData.
Digital Confidential 16-1

: : : : : : : .-'.:.i: li·:l·l!l :l : : :>: : : : : : .·~·

-::::::::::::;:;:-·

.... -

:~{{:ff\:::::;:;:~~~\:;:;.·

-:····-·.·.·.·.·.·

t:::j:]:I .. .t::1>
:.:[:.:i:·:~:::·.:i.·;.:·.·:i.·:~.:.::;:·:~.:·:.~.:~:·::=:=~.:~:=~.::·=~=~.:·=~:·:i.·:.::.:-.:.ir=;.
. . . . . .·
·::::::m:i;.

:\::::::::::t:'

16.1.4

:uda~::ryth~:~!~=~:~=~~e~:e~~C:!::~-~tP!J.lf'!
holding latch. If the memory write buffer is full, the <fit~{ha¥:tjfiitiU~:.

Data from the Memory Write Buffer is unloaded py:'.thi:}nemo~>~BllBi
sequencer from the 21071-CA chip when itd:~. . readf:=:tijMB~.~ the wrile.
:'\f::fv:. ./:= ::::::::::,. .. <=:w:::::::~=::~::i::::j::::::tt
16.1.5 STx_C Hit
.t}/tt:.·
....... :::::;:;:::::;::::...
-:-:;:::-:-:-:-:-:
The write data from the CPU is loaded into the"<rri:im~fpµffer...If. the address is
a hit in the cache, then the remaining d~ta.J$. read':'trQ.m:::tb~t.cache and loaded
into the unwritten longwords of the m~#g~!iiJiiQift'~r.•. DatiF£t~#f the merge buffer
is then sent out on the sysBus.
,[[:il]::tr····".::::,,::::.m\:.:.:i.\.i.:.·.i·\H;itt::::,.. ...:::::
-.-:-·--.::;:::;::;:;:

16.1.6 STx_C Miss
:::::\t/t/t\.
This is exactly like a CPU memo~::.j*fi:l~·:j··:::j:j::\:}:\:':·.
.;::::::·:-::....· . .

16.1.7 LDx_L Hit

··::::::::::::~:

·::=:ii:~;~;~;;;~>;::>:

.:.:.;:::::;::3::c..

:=:::::::::: .· -: ..

...:,..:-: : : :,:·:-:-:·:

~~ta~:Br:sadr!":i~htj~ l.: .: .:l.,~t:.: : i·,:'.(·:.: ·:n: i: ..•:.·~.·:d.:.·.: ~l;flll~···th~ merge buffer.
::.··:···:::,.1.::·'.·:·r.:····.·.'.·.·:a.··::
...

...•

16.1.8 LDx_L Miss:t:::::::=:in:::::::,.
......
'·'.·:-:-:::::::::;:::::::::::::·:-:-.·
This is exactly iik'~[:=~:::m:ew
. . me~dfy\0·.·.·.·.····.·-·
\~~a·.
·.·.:-:.:::::::::::::::::::::::::-:-..

It is

sent out on

1s.1.9 cPu Read 1rom1th:;aullt1rn~=l971::·0A
The 21071-D.f.\t~b.jji:.~i~~:::th~::::ditiition of the epiData bus to be from the 21071DA chip to.,,t.J.ii~fi2'1'61fl.f:JJA q)lips.":'It sets the epiBus controls to indicate the I/O
read buffe#'\~$.\:'theJli~iin~t*9n of the data. When the 1/0 read data is available,

~;i~l,ii1J~~:r:ta~e2~~7~~~!~::r~~e~::::a~:e3ius

16.1.10 c:aP.MIVrite to/through 21011-DA

Afililfl;fj'l'l!lj£~~-l!~:::~~!:1ot:
;;~~~~:a1~u~U: ~:!!-~~~!:i
\\ijfi[ftie appropriate entry of the 1/0 write buffer. The loading of the data is

...:»»:::::::-:::·:·..

./{\=l\\.)\::t=..
/:}~:}}} ·-·-:.:-:-:···

..Jli~rolled by the 21071-CA chip.

-:-:-:-:-:-:;:;:::;:;:

· :·:-:............: : :.:.:·==:·:....J\\:\:]\gJhe 21071-DA chip sets the direction of the epiData to point from the 21071-

.·.-:-:·:::;:::::=::::\;]\\%\\\]:EIJ3A chip to the 21071-DA chip, and extracts the data as needed by controlling
. ,:::\{:\'[\:E:1:\:tb~)ongword select bits and enabling the appropriate 21071-BA chips using
·-.::'?\\\~~lpable<3:0>.

16-2 Digital Confidential

16.2 PCI (or Any Other 1/0 Bus)
Transactions_.::::::::::/'t::,,,,
..
.
..::::::;:::::::;:;:;::::::::::::::::::=:·:-.
16 2
1 1
· ·1 :::

:i:~~:oc~pS~~=~s
~=!ead
transact~mt111
::
!f
ill~,!~d
set
s
up the controls of the DMA read buffer to "'point
. 'entey of the
to:::m1.::i~Pp.ropriate

DMA read buffer.
<[l\::~:.)l:li\J> ..::\:,.. . , , ':t:t:i~: \ ~:,:1,1~!j~\ )~!\: \ \: : : , .
The 21071-CA chip gets the data from mefuq;@{ijtJ";~.cache'J:'if'ftli~bdata is to
be read from memory, the memory read buffet4ia9.i.id~9. as ditiFJ.s received
from memory. Data from the memory rea~.buffer''''i$i[J~i4~4Jnto the DMA read

~'!:~e~::'Ji°: ~~::~!';!!i~~~!e~••:tii~~41\t:;~:~=~h::ito
the DMA read buffer, after error checIQng ha~''''n~P.P.~h~(l.

~~f~:~~;~:~p:~t~~aff!l1~!~~:~:;~:i~;~~:s

16.2.2 :;.·Write to

Sy.,M@:!!JJIJ;fJlli:tb ;; ;r

~;7~~~~~1,:P~~;111,1;:t:,::~:!~2;~~t~:!?:r~;;:a~!~ethe
correct write buffe~f~nf!rx. are setflWb."\write data and the corresponding byte
masks are loaded iiitb.Jmi'm~~lected.'erltfy as it is available. If for some reason,
the write is not valid, "theU:::::tb~;t;g_1071-DA chip can overwrite that entry by
using the epi~iq~J.#.~L.signil~{:\~pf.Linelnval should be used at the start of any
DMA write ·:·:·::;::-:-:-:···:-·
,,wWClkdoesdfot
us~''lhe full cache line.
·::::;:-:.:.:·:·:·:··
.

Whenever::ii\~/21Qrl~SDA;::~~jp is ready to do the transaction on the sysBus, a
DMA writeiflMirntiated. Utt.lie DMA write buffer contains completely unmasked
data, ,m.~n. th~\\~i4.~,.fr.9.mJ:i\lie DMA write buffer is moved to the memory write
bufi~1{:#.jer th~kP.f9Pi!fa~f.for bits have been generated.
m9li·I~ writ~·"'i';·:·:;;~ially masked, then a read-modify-write is performed.

,{i~ll~ll'1llill1~~~-£'b: :~;11~ ~~i:~~:s~!~t~~~:~~: :~:1n~e~~fr~~a

:t::::tt?::'··· ·····:·'\ifp~~d on tH~kDMA write byte masks. Error checking is performed on the read

:;: {:'.,., ., .,.·

·::di.ti. If there.ls· no error or a correctable error (error is corrected in this case),

_.:;::::::tb~h error bits are generated for the merged data and written to the memory
, , ...<iit!Wfite buffer. If there is an uncorrectable error in the read data, then the merge
'"'=':<:::::[\[\·':::.::,):trn::E\::::Js performed but incorrect check bits are written into the memory write buffer.
···:::::t:?@::ItlA>read from this location will result in a hard error later.

.,.:,:.;.,., ., .. ,.,.
, .,.. '"'"'"' ·'"' "'"'

....:::;::::::::::~:: :<.:.:. :-:.
··:::;:;:;::::::::=:=:=::::::::·"'

......

Digital Confidential 16-3

16.3 epiBus Transactions
16.3.1

~~~i~;;::~i:t~;~~~;.~~~::~m !-fl't~~!!littto the
0. The 21071-DA chip may read data frjijij}th~·:-.DMA"f.ejg{Q.µffer after the

~!~:: :e:!!:~~! ~~ea i~~~;~~;~Jtiir~::e~~~1~:::1::~i:
2

sysReadOW for the octaword to be read. ioC.A&k.~\~Q>,j:n this cycle of the
diagram indicates that data is ready\P.y:::¢tc.;1~ 2. ·.·.,::::\?lil\l!t:::

If ioCAck<2:0> was not sent in cyg~ij:[~b~im£Hil·i·~:::~y~R~~dbW indicates that
the first octaword of data may l>.~t:i!\~4 out lhfa@gl~}g.

:e!~~~~:::t>~:i::e1tt\ill~t:::l J~~e~~8!ff!~ ~i::rts
which was indicated on ioL1ne.Bel whetFtne)f.ead was started. The 21071DA chip places ~dr.'-_quest'':f.qfi\\l'=Ai.rst Iong#ijj(i of read data by deasserting
epiFromIOB (a:::f:~d),Jleass~ffmg[\i!P:~QWSel (with first octaword), and
asserting epiEmible-sQ~f(M.}V O Witljm:]li.~t~t octaword). If the 21071-DA was
driving epiQ.,qi, thelFiij:[!m#.$.t:::.tristat~\the bus by clk2F.

2. The 2107f~Dji]~ij~ltrece~~~il::tlj~:,:~p~J3us control signals, and begins driving

i~t;;~ii:!~f~~:i:tt~ii~;;;,~~:;'.;:::~e::~
~~7~~1~~,~e11:~~e~~o~~~st~~~:::::~~:m°:a~~~F~~e
e~~ll!'i~ll:~~~:::g~~~\:~·F.

3. ::'S.iWiar to cyijnHg#jhe 21071-DA chip requests LW 2, and 21071-BA chip
.:ifdrlYi$ LW 1. Epifiata<31:0> and epiBEnErr<3:0> are always one cycle
. ::::::b~~~lljj:~:~:-.·EPI control lines.

··21ftllf:DA chip requests LW 3, 21071-BA chip drives LW 2.

21~;=il]\b~ chip requests LW 4, 21071-BA chip drives LW 3. Since LW
is in the second octaword, epiOWSel asserts and epiEnable<O> is used.
The read continues. There is no constraint on the order or number of times
that a longword may be read out (as long as the LW is ready, as described
cycle 0.)

16-4 Digital Confidential

Figure 16-1

CYO

CY1

CY2

CY4-

CY3

clk1

clk2
••••·

epiData

·.·.-.··

··:·:·:·:·:=::;.;.

epiBEnErr

epiUnaSel
epiOWSel
epiEnable
ioCmd
and
ioOataRdy

or
loCAck

dk1

clk2
epiOata
epiBEnErr
epiFrornlOB
epiUnaSel
/::·:::::::::·:::::;:;:::;:::::/

epiEnable

i:·:·:·:·:·:·:·:·:·:i:·:·:i:-:d·:·:·:·:·:·::]:tt:Xfj:;:;:;/;:;:;:;:;:;:;:;.:·:ID:·:·:l:·iWf-:-:l:x::ti·:i:·:·:·:·:·:·:·:·:·:·:·:·:·:i:·:Wd
I

·.-.·.·-:·:·:· ::::;:=:::~:>:·

epiOWSel

.:::;"'.::::::::::::·

'.::;::::::•••••

·.;.·.

•

\::::::::::::::::::::::::;:;:;:·:::::;:;:::;:;

loCmd :::::::::::::::·:::::::·:;:·:·:::·:::::::·:::::::::::::::::::::::::::::::·:::::·:::::::::::::::::::·:;:::::::::::::::::::::::::::::::::::::::::::::::::::::::;:·:::::::;:::::::::::::·:::::::::::::::::::::::::::;:;:·:::::::::::·:::::::

iooata~~ t:·=·=·=·:·:·=·=·=·=·:·:::::·=·='=·=·:·=·:+·?·J3'.t'.b::::::::'.:'.:~m1;~;tt:1:·=·=·:·:·:·::~lI]·:·:·:·:·=·=·=·=·=·:·:·:·=·=·=·:·:·:·:·=·=·:(=+=·=·=·:·=·=·:·:·='=·:·=·=·=i:::::1:f
ioCAck

:=-:::::::::::·:::·:::·:::·:·:::·:·:::::::::::::-:·:::·:::·:::·:i:·:·:·:·:::::::::::::::::::·:-~:::::::::::::::::::::::;:;:·:·:::::::::·:::·:·:::·:·:::·:::::::·:::::::::::·:::::::::·::!::::::::::::::::·:::::;:·:::::·:·:::::::·:·:::·

.~~11,r1=1~llll;lf!~· ='t~s.

-LW

•

W-03177-TIO

Digital Confidential 16-5

.<t:::._::_J:-:::::i::::!:]jt:
··-=:~((\:::::::::::::~:~::::::·

16.3.2

~ e~~= ===~~: ! ~c~1;:sfers from ilie utJ!~~!jl:~111lll!V
data

~~~!!:b:r:~si:~~:~~~ ~o=eJ;t;:d~a:;~~;;;,~-~~:~~~::

is that a different buffer line will be requ~~.ted usirtg\:(i.P.~t4.~eSekl:09F. (The

16.3.3

~~~~~~:::::: :;:t~n~:::~O> ~.i;~.,.~O~-·lli;ed.J
~~~:::tll.:l~l.ill.:7.J·~A/~hip

An epiBus transaction which transfers data
into the
DMA write buffer is shown in Figure ~~~J~:~:::,::·::liitm\.:-:·. ··:·::\{ff::i[:_·:.·;:::J·[l}
0
0
·
epiSelDMA (DMA transfer), 4.~i§~~rlmg epiOWSil:twant first octaword),
and asserting epiEnable<O> (#\Vt'o\WJm~nJirst octaword). The 21071·DA
chip asserts the epiLineSe.b;,l.;Q> lin~~¥W:anm.~~te an empty line in the
DMA read bufferJine. Be&u;kthis is tHMtfirst store to this DMA write
buffer line, epiYniJ.nval i;::::~[$-~tto cle~;:':'~n of the byte enables left over
from the previoliiWis~g~J~f the'''Bi.~P.l@:::us~.
If the 2107kB..f\ chi~twjj[i14.riving··:~Pin~t~<31:0>, then it will tristate the
bus by clk~::\\{1t:::::,.
.·.·.·.··::;:;:;:;:>:::::::"'":
.·.·

:~;~~~;·~Aa~!!~r~:c:;i~:iallll~':::!l.:l~l~~l:.! ~ ;:r1v;~~~~fa~:'!ing

1. The 21071·DA::::~ft.~~:j\j~~n.4s th~::::d)i,~iiilo be stored on epiData<31:0>. The
21071·DA chip drfvi.~:::·~mi~NEri<a:O> with the byte enables for the 4
bytes in th.~"'J9pgw.ord~'t(~p!l§fipErr<3 :0> is on if the byte is valid.)

The 21QTl;lj;A.:ij~ip:::tecei;~~:!:the epiBus control signals, and latches LW 0
into th~rnio re~~:::P,iif\~tt
The 2i(:J71.~P4.!:!~hip ~#,ests that LW 1 be stored in the next cycle by

c1if!Iig\:1:.,l~~~~::=:l~~fflable<l>.

·.·.··.·.·

2. ,,§.il.lilar to ·cy~lil~#t.he 21071·DA chip requests storing LW 2, drives
. Jt~t~tfor LW 1;··and' the 21071·BA chip latches LW 1. epiData<31:0> and
··:,;::::i.P.!llµE.rr<3:0> are always one cycle behind the epiBus control lines.

. ):~ll~!llll(lll11I::*!~!,l1~ :::: :::::: :::: ~: :~ :~~~~~~~ ::: : :: Because

··· ···. :.: :.
,,,:{{)ftwd4 is in the second octaword, epiOWSel asserts and epiEnable<O> is
:-:· ·:·:·:·:·:·:·: ;: : : : : : : :.
.·:·:·:·'.-'.·:·:·:·:·:·:·
·"'=\:'<!:?%/' ?' '· ··-::t!i]/f:/· use .
·-:-:,=tt:::\1I1:1tf~.

The 21071·DA chip requests storing LW 5; the 21071·DA drives LW 4.

·.,,<l\f\·\\\l\\\l\1.!ti::l:\W:Pe 21071-DA chip requests storing LW 6; the 21071-DA drives LW 5.
···:-:· ::{:}:::::::··

16-6 Digital Confidential

.·: : : : : : : .: :l:=: : :lj[j.[·: ':l: : : : : : :.

.~imt S~a(f'.: 1~'lilIY

If the 21071-DA can ensure that the last data will be
it may request a DMA write transaction with the ~~Ai:l~P.A.:::. By thij\\\\gfijg?
the 21071-CA requires the DMA write data, it wi1J\i\\fi3v@•n::]Q.~de(f'ihfo
the DMA Write Buffer.
.dii!it:·li::j::.ilr·
···:;'<i\li:j\j::·:::l,l:l:·::llr
7.

The stores continue. There is no constraint oritthi/d.tder or nuriiber of

:~:
~!: ::ei:;::::::. :e~~r:tt•~~~~'ll;;:if~;~~!
~
enables that were not loaded to off.
iilli:W,f an 21071-DA
(This:'''ftin®.~9.q~lity

chip aggregate writes.)

· :·: ': :\t\jij,j[j!!j!j \:jli\ :lt=: =: . ·.·.,
·.·.: : : :;: ;rn: :i :l: : :t=:

Digital Confidential 16-7

16.3.4 21071-DA to 1/0 Read Buffer
An epiBus transaction which transfers data from the gtnl:f.~l~:ttb.Jp

~-~t~~::a!::e:i=ts:~-:::::=I/~6::~ 1'~li:~~ :~!ll!la that

~~~i-~l-~Pc~c::C:~~:!s~ ~·'Tth~~~~!Alla~?:e:l~~ta~;
~~1!1!s;!f::!?e!~:gw;~~~e~~!~'14,~t:!~ :~~~~

epiEnable<O> (LW 0 within first octaw9r.d). Ifth.i~!i\)g~Q7J-BA chip was
driving epiData<31:0>, then it will,::tn~~~4p.e h1is4~y\i:~}k2F. The 21071-CA
chip asserts sysIORead to select tl#~tfl/(Y¥ijA~l!\l.,µffer ortfu the sysData bus.

1. The 21071-DA chip sends the 4.~J

.ll be s~~¥iai:·l,::::~piData<31:0>. The

values to prevent the
~~ ~~~OB!ajiJ:eC:.i~C11!iTu:i~ut~p signals, and Iarehes LW o
:~i~Afl:~ves epiBEP~JIJ11:: arbitfiiry
··. ·.·.·.-.·.·.

·:::::::::::::::::::::::::::::;::::::..

The 21071-DA "Cliijf r.,®.iµ~sts tha~n4-\Y\l);>e stored in the next cycle by
changing to.Jissert eplJ~;P:iP.l~< 1>. ··:·:::<w:t:mrn:r·
:·:-:-:-:-:·=:·:·.

··:·:;:;:;:-:-:·:·:-:-:-·.·-:····:::::.

··:::::::::

2. Similar to::~ijy~l,~t!ii:;t:r.:Jhe 2I0.7iJf:PAJ!hip requests storing LW 2, drives
data for LW1fJJ.ijiji:::tb.g_ 2101:Hl'-$.:¥tiip latches LW 1. epiData<31:0> and
epiBEnErr<3:o>·'.::ari:\:I$~¥.:~ omr'cycle behind the epiBus control lines.

: :: :~:~tilll,;::!I!~:::epiO~=WSel:~ :~~~~~~~
:::::
~= : Because
asserts and epiEnable<O> is
~=d~ 11;:~11Pnliltaword,

~J.ltrl:,:11~1JfQ\l~~~7;~~AW:~i::i~;r;!~n :~;:i;~~f~:~;PO~-

.
. /(NQACHE_NdHK;:h:;quest through the 21071-BA chip to the CPU.

.. ,:)$.·::::<1'.iillltn7J-DA chip requests storing LW 5; 21071-DA drives LW 4.
.<><:1··~:::\:;::::::::: ::;::.<:::'..- ·_. _Th;::::~tq7l~¢• chip receives the cpuDRAck<2:0> OK_NCACHE_NCHK
:-:-:-:-: :-:::::=:::-·::::::mt:tlrequest,··:1a~r·sends the OK on cpuDRAck<2:0>. The 21071-BA chip sends
.·:-: <t. :·
. . ::·:::::::l~~[~the first octaword on sysData<31:0> to the CPU.
..

-/}'··: .::.:;:::::·=::::::: :·:-:·:·..

: : ':l: :~w: : - The stores continue. There is no constraint on the order or number of times

.·.·-:-:-:·:·:··

. :.:. . . . . . ·: : .:.: : : }Ht

that a longword may be stored. There is also no constraint that an entire

·::::::::t::::::rr:::::::::..... octaword be sent on epiData<31:0> before requesting a cpuDRAck<2:0>.

\ J,,

\iil!tc~:~~ :0 :~~::2~~:nc:;ia:o~~;;;5uested

before all of the data

Digital Confidential 16-9

Figure 16-3 Timing of 21071-DA to 1/0 Read Buffer Transfer

1'
_
·
,
·
~
·
,
.
_
:
_
:
'
.
:
•
.
:
·
,
;
_
·
i
c
,
·
.
:
_
:
l
·
:
.
~
'
;
l
1
--1

CYO
clk1

CY1

CY2

.,----..

./~.:~:_: ~i~.:.:.: ._'1~J: :
.....

_.•.

c4ft_

i_.•

:;·:_'=··;=···.:··= ·,·.:.:,:·._·.:··:.:•,.·•:_.•.

•.
:._••
,_
. ,••
.
:.;······::i_·
•._._,._.•:_:•::•·:,,

=.·.!···['·,··,_ ..

··::::·.::;:::-:····· ·:·:· ::-::. :-.

.':\::::.:t=·

·-::-::}}{{,:-,:,.,.,-- -

clk2
epiData

:~:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::i:-

epiSelDMA

\M\:!:(:l@JM¥\#;\:\\

epi From IOB

4:::m:::::::::::::::::@:::::::::::;:/

epiOWSel

\;M:::::J:::l;!t\:::::::::::::;:\\

epiEnable

:*::;:;:;:;:;:;:;:;:;:;:;:;:::::;:;:;:;:;:;:;:::· 1

ioCmd

:~: : t;: : : :;:;: : : :;: ;:;: ;: :;: : : :;: : ;: ;:;: :;:;:~: : : ): : :;: : :!: :!: : : : : : : :;:~:;: : : (: :;:;:;:\: :ili i{ilf: : : : : \: : : : : :!:\: ; :; ; ; ;:;t; {i\i;i;i:i: :~: :%: : : : ~;:\:;: :;:\:i
I

Set-up Lw o

-:::~ :-:•:<:::•:•:•:•••:•=:::::..

:=:::::::::::::;:;:::::::::::;..
·:;:::;:::::::;::::::·.~··:·.

4
Request DACK

····::::

:-:::::::::::::::::::::::::::~::::.

clk1

dack cpu

-~~;; :<;!l\,_:F_:r.:r,=-.:·.:.·_:.:_[.=_.:_,_:.~,.=,·.·_:.':- ~=~~t~~ a . ~=~~t~~

·;·.:>:::..,::::: CV6:'''\i~!:['l·.~;:;'!i!t::=::,..CV7

CVS
----

•'•::::::\)?

\':'/

CVS

__.

clk2
epiData
epiSelOMA
epiFromlOB
epiOWSet
epiEnab1e
iocmd

·,::ftf?::dl\it::::-·

X=:=:=:=:::}i;;;:f:\:\:\:::=:~:tmth:~::::::::::f:::Ui~{i;:~Ql¥#i=l:::t:=:\:::::::\:::=(:x:::i:)::::)=:::::::::=;t::=:::=:::=:\:=:=:::::\:%::M1:
·.:,:::::?::;\;::I::::i:~~~~:::::::--

;::::::::::;:)::(;;:(·

·_:_·:_,:.=4'_=~.·:_,:_,:_i_,~_:~.:_,:_:=_,=.,_:=:_(_=_:_:,l.:_,_=.-~=~~t~~

..;;;;'!\ii!.%1rn.
;1r1f!IJr.=:_,:_==;r. . ..·.·.:~~t:)f~~~?t.
.. })/:"
\\F:'~~te:
.:, .
::=::}:::::::::::'.:·:····

.:::::::::::;:;:::::::::·

:::::;::::=:::::=·

:::;;;:>;;;:'..'.:=: :::::;::::::..

\:::m:):;J\:\:!:\:t:i:::M:\:l;\:(#4

::;:::_.;;.:;;j:_::·

··=:;::\\~}(?.·

aack cpu

~=~~t~~ ~=~~e~~
7

rJAcK .

}}}~:}~piBEnErr ,epilineSel,epilinelnv and ioDataRdy

..:)\:'~j~j·\~j\\}are not important during this transaction.

·::J:::::::i:t:·'
;'.:'.:-:/::i)}/"
·.·.·.::::::::::::::;:···:·:··

16-10 Digital Confidential

LJ-03187-TIO

DECchip 21 ontS~-;~:~~ifil Data
-<~J:::[~:)~::)~)\:):~11~}::·:·.

17.1 Introduction
This chapter includes the following

•
17 2

..,:,,:,,,,,\:::'?:F:'·

int!E::iJl!i.:l\ii.ktP.e:-:;~ECchip 21071-BA:

~c :::~:: ;~ #fl l lt: :~:l~l f'l f:'l~f i
r

This section contains th~{QQ}¢b.~racteni.fiij~ffor the DECchip 21071-BA.
::::::::::::.

.·-::::~:}~'.}~{:::::::::::==·

·-:-:::::::-:-:-:-·

11.2.1 Absolute Mifd~~\l!nt. Ratiffg~==:·:=iit=>:·.
Table 17-1 lists tirn:::1!Bme.m r~tiri;,:::thr the DECchip 21071-BA.
·.:-:::::··-·.·

:-:::::-:-:-:·:·
.·.·.·-:-::::::::::..

····::::~:~t~~~~)){~f \::·

·-:-:::;::::;:;::-

Digital Confidential 17-1

Table 17-1 DECchlp 21071-BA Maximum Ratings
Characteristics

Minimum

Storage temperature

-55°C (-67°F)

:·:·:·:·.·.:·
..::::::~'. ::::;:~: ~: ~:::::::::::::::·.

Maximum

Operating ambient
temperature
100 LFM1

Air flow
Junction temperature
Supply voltage with respect
to Vss

-0.5 V

Voltage on any pin with
respect to Vss

-0.5 v

Maximum power:
@Vdd = 5.25 V
@sysClk = 33 MHz

:::=::::...:}:::::::::.:....

·-:::::::::::::::::;:;:;:::·:::::;::::-.

·:.·.·.:-:-:-:-:-:-:-:-:;:::: ...
·.·.·.··:·:·

~\:::::..

Table 11-2 DECchip:::l1lo71lfll:::pc P~tlri~trlc Values
...........

··-:-:-:-:-:-:-:-:-··

Maximum Units

0.8

v
v

v
0.4

5
-120
24

~~f~-!~%~~,:~m, eccMode, drvSysCSR, testMode and tristate_l
2For tristat~jjf(:/·
3 For drvSysCS~,· eccMode, testMode, and wideMem.

17-2 Digital Confidential

uA
uA

Test Conditions

Digital Confidential 17-3

Parameter

Min

clklx2 period

Max

clklx2 frequency

clklx2 fall time

TBS
TBS
TBS
TBS

clk2ref setup to clklx2 rising

0.8

clk2ref hold from clklx2 rising

1.7

clklx2 high time
clklx2 low time
clklx2 rise time

TBS
TBS
TBS
TBS

...:.:.::·:·······

17-4 Digital Confidential

:{:~:··

17.3.2 Signals
See Figure 17-2,Figure 17--3 along with Table 17-4 81!4.?if.~l.J~\j\\tlft:i>.
Figure 11-2 OUtput oe1ay Measurement

t!t1ll'lr ,W\illill\lllt'

·::::::::n:tt:::)/>::::.

··:·::::\:@:1:=::t:\t)~::::::.

Output 1 1 4 - - - - - : - - -. .:::::::
..

.;.·.·.·.·.·.·.··

Output 2

./~~#~\::-

Digital Confidential 17-5

Figure 17-3 Setup and Hold Time Measurement

17-6 Digital Confidential

Table 17-4
Parameter

Minimum

Maximum

sysData<63:0>,
sysPar<l:O>,
sysCheck<6:0>

TBS

19.6

memData<31:0>,

TBS

17.0

:::::: :::::

..:: : ~ :~:~ ~::::::::.

memPar<O>,
memCheck<6:0>

epiData<31:0>,
epiBEnErr<3:0>

-:::~t~~~r~~~{~:~:~:~:::::::·

A!iJJ, wi~ !Jil.i!_.:_:_.:_i_: : : '.i:·'.r: : : :r: i: : : : : ~·:_=: : ~: :_: .: '.: :.:·: _·_: _·

.1:!_:_: : : : : : :'.: '.:;·: ·: .:_: ·: .·.: ·-:_:·: .'_: :'.:·: : : ·:.
1v1:::_.••~

TBS

·.:~:;:;:;:;):;~);{~;~;f}:;:;:;.

··:riijJ/lf·· cJklR
·.·.;.;.·

~:-~:-~:-~I-:. ~f?===~:}{f{t~=?I?
. .·.·
·'.·'.·'.·'.;:;:;:;:;:;:;:;::::::::::::::.

..
~t
.::::;:;:;.:-:-:·:·:-'.·:·

Table 1Hi

~arameter

1
oeechff1¥iQ11~::
Jl'[Bt@!;t~:;~:s
··\f
..
·.·.·

./:::i::·):::~l~P

·.·.·.;.·.·.·.·.·.·.·.···.·.·.·.·.·.

.·'.-'.·'.·'.·'.·'.·'.-'.·'.·.·.

~JJittr··

:·>=:== :::==:===·=·===-:·:··

··:\\):::t\:)~~)~-Jtp1d ····::t{O~it

sysData<63:0>, ··:·:::%2{2:~\]\It::t::.·.
sysPar<l:O>,
sysCheck<6:0>

·:::TQ~·:f::::::·ii;::-· ns

(Setup/Hold Time)

Reference
Edge

Notes

clk2F

·>::::;;:

·TBs

memClkR

TBS

clk2F

.... :·:·: ::::::}~}:
··:·:·:

·.·.

(continued on next page)

Digital Confidential 17-7

.·.·:·:::::::=:·:·:·..

Table 17-5 (Cont.)

1
DE~hlp 21W1·BA AC C~raciMlm.~;~J~jl~iJi! ; }

Setup
0.7

Hold

Unit

TBS

drvSysData,
drvSysCSR

0.7

TBS

drvSysData

0.4

memCmd<3:1>
epiFromIOB,
epiSelDMA

-0.1

Parameter
sysCmd<2:0>,
subCmd<l:O>,
sysIORead,
sysReadOW

Note 1

Note 2

-1.4

ioLineSel,
epiLineinval
epiOWSel,
epiLineSel<l :0>

TBS
TBS

'"'''

1.'~lll~AyrSysData asserting.

clk2F

Note 3

clk2R

Note 3

clk2F

Note 3

clk2R

Note 3

;}l\ll~l~\(i'ill'.l!i~~!-~~=~t latch (closing on clk2F) before reaching a clklR
-:-:·:···· :-:-:-:·:·

17-8 Digital Confidential

oEcchip 21011!4~'.- ,,,~~iWfa:~~
<:::::;:~:?~r···-:::::::::··

····::::::{?'

18.1 Power-Up
On power-up, the re~~t.J inpu\j)frthe..:. 21071-BA/ehip should be asserted. It
should be kept ass~tl!funtil th~lif.i.nt:~locks ·are up and running for 20
cycles.

'~"'

18.2 Internal ReS.ll:·::l:t::..

111\lff~[\)lh '!\\]ll'!!i)>

· :;.;: ·:·:·:-: "'=\:':'ft;,,,,,.

·-:-:-:·:-:-::;:;:;:::;::::::::::::::·.

The assertion ancf'dij~i~~m9n oftli~:::t:~s.et_l pin on the module is asynchronous
to the DECchip 2107DBA]~:['')~d.11ternli reset signal is generated from reset_l
which asserts ~~yn~bronotis)@i!i'.S.\§pon as reset_l is asserted, but deasserts
synchronou~bf.~Ipµ~::::w.:::tp.e syniljfonous deassertion of the internal reset, the
DECchip 2JQ7[['.Cft.L\}ki~iillr~ that no external transaction should start until 10
system clo~Wi~!~ycl~~::::~fkr(th~ deassertion of reset_l.

18.3 State?O.t:~i~l:§llil£:~.,,,,,Rllet assertion

Tq~ff~il~~ing··=:;&:::)l~H~¥ii'''~les for the behavior of the 21071-BA at its pins

dfiiil!·~1!~!.:.

AlFiii:PifdmJy control signals (except the clocks and reset_l) should be in
deis$.~tt~d state as long as reset is asserted.
outp~~=:::~~ly signals are deasserted.
All bidirectional signals are tristated.
wideMem and eccMode should be stable before reset_l deasserts and should
change thereafter.

Digital Confidential 18-1

. : :t1:i: : : :1: :i: ~i: i:it:\:-

1t~::' .;;~fijtliii1iii1by
The exceptions to these rules are listed below.
•
•

....

;\ll~:,;.•dl't;V

The value of memData<31:0> is unpredictable; th~~=:41~J1::!~iit~,,._pe~~rlUi.[i::@ii'.
the state of the drvMemData input.
..:=t=J.:il~_:!f:=:==······.··==<{i[\\Il:i·'.,.\l::.l::i::[[[ltt,.
drvMemData is asserted by the 21071-CA dutjjg@j§~t so metriDi91<31:0>
are driven by the 21071-BA
··=='?\\lIIl\\\):\.,..
. ,.
··-=:=:=t=~=r~t~{f~?:::::·.·

0
1
8
!~a~
!s~8:re~!:t:~l
~;t!~~e~e~~:e;~
.•~7!~1-;::r ~e~~~;·
go to their High-Z state. If
Whth tristate_!
resetj:::Jl:~:=~j!J.~\:\@i.$!rted

deasserts, the signals return to thi!]j6niiafifi.iit.:::~tate described above.
..-:-::::::;)}~{(.
····:::::\fff }fft?·

18-2 Digital Confidential

P9t;s,~CJll11i1~ations
·-::;::::::::::::;:::::::::::··

:·:·:·:·:·:·:·:-:·:·:·:·:·:-:-:·:·:.

:~~~t~=~~~:1':n~a~~~~n11aiiit~11~~;~:a~n8:d
.;illl1!llll!1n;·>
tt'.tif
41

'W!Jt(.\ll,_,;r

!lillf·:1 1 1~t~J!t1H>
·.·. ::::;:-:;:-

Digital Confidential A-1

Table A-1 Equations for Cache Data Write Enables

bcDataWE31 =

~"r.~~~: ~~ik1JtlgWr) <tf!llflliJ

bcDataWE3.0E =
bcDataWE21 =

<>;

# cpuData~:1m\::::fjj)l}::
··::::=:::t:l\\j\j]j]jl~]jjjj)\j)j1\:::::=::::.
.·-==:-: =t=:===- .=<L>====·.
··=:=:t{}} .. :.. :=\=·
..=.··.-..·:·:··:r..·.·
.. .../.\
.. ·.·.=.·.·.·.

· · ·::::::::::::······

~s~)s)D;n::: *': :,'.clkl\~11~~;.
...

1
(sysData.Lo;i.\l::::~l\!11,ij~ft!l:::::..

:((

bcDataWE2.0E =
bcDataWE1 1 =

::;:;:::;:;:::::::;'.:\}\;

-===: : r

~ ~iJlfiit;t:::~ti~iFWr)

bcDataWEl.OE =
bcDataWE01 =
bcDataWEO.OE =

(sysData.LongWE &40.'.·.::.=.·in.··.·:.=·.·=.>:tt=:.~w.·
:':~
:z

Ct;YMPi~ngWFf.l)~fogWr)
#·:=(iy~Pit~WEEn &.follfl & !longWr)

:.=.:·::·:;·=.:f.:::.:.:~=.:].:!:..(;..·:·:.:..~·..·.·~.
;;' :'·~!;;

··:-::::::::::=:::::=::::-·

!bcDataA4_3 , =;,~!; ••;,, 'i'~~! ~I~iJ)
1 2

·-=====: : : : : t: [JYHt: ·.·. # ( sysl?j~En & sysDataAHEn )
· ·-=·:-=·: : : : . .:::::·:I::::.::~=:=~~uDatat\4;
bcDataA4_3.0E =

··.::::::::vxnl')>;"

.·~Ci~~~ address bit 4, these are 4 identical copies

A-2 Digital Confidential

··:::::;::::=;::=·

Table A-2

~~E~:En&&":~~j)[

bcTagCEOE 1 =

'4¥il;1l\\1t

!EE3:~~:~;~~t~lll!ISttt
...<<titth\::;..

(( 1 ));

bcTagCEOE.OE =

..::\}(}{.

(sysEarlyOEE~:/~~).~pucill~. l~\\:~P.~9~:1

bcDataCEOE0 1 =

!~il:~:~tl~~~uC&qO

# sysEarlyO@i.t#~@pµCReq2::::&fJt.P.#CReqO

bcDataCEOEO.OE =
bcDataCEOEl 1 =

:·:·. ~~lf£~~::~fl·~~~2~~~~~~!o

:·:::r•1~~~~ & fopiiCReq2 & cpuCReqO

.,.:::I][:::l:::~(snaeae,~m~:::~b·
·::::<U[J9JH)L
···:::::tl?:

bcDataCEOEl.Oi.1);.;.;.

(sy$~~tlyQ.E,En & !cpuCReq2 & cpuCReql
··:;:<t:ttl\l>:: .. # sysEijtljQ~En & cpuCReq2 & !cpuCReqO

bcDataCEOE21·::'J(:ii\i\:{i\}frt:::::..

··:·:::::::::::1:::.:::::::::::·l\[>j\:\:~:=:tg:~~ & !cpuCReq2 & cpuCReqO

..:::::::: .........·.;.::·:·

bcDataCEOF}~-llM,!fill~if

bcDataCEO.m~\fa~

·::\@[:::1::;[:}:::::l::·:.·.:[i1?::::-

··::::wt:\.t~~BraoEEn );

((rm
./()(sysEarlyOEEn & !cpuCReq2 & cpuCReql
:@11~ sysEarlyOEEn & cpuCReq2 & !cpuCReqO

2Jllf 'fi';'ll\lfltl~fi1111l1:1tJ:

·:·(\/:;}.·:.~'. ; :.~.;;"lii.:·!.t.t.::.•;.~.:\:.'.\.:::.·~:.:.:.·.

./r:::::::::::::r)(:·

{:}\:\:?

)\!=.:\.::.)
..

··:::\\i~~OE.OE /~:;:;::::>

581;:

2
)~ !cpuC&q &cpuCReqO

~~~)~En cpuCReq2 cpuCReqO
&

!senseDis;

-:=::}~'.}}:::::··

...

:· · ·: : : '.:.:. . ::i::::::<?\::::. .::::::::::~PU output enable, must be tristated when 3.3V is not stable.
··::::::;:::::::::::;:::.:~:::: ·::·:-:·:··
:-:-:-:-:-:.:·:·:·:-.
··:::::::· ...
..
.·.. .;.·.·.;'.;.: ·:·:·'.·:·:·:·:·

Digital Confidential A-3

· ·-: : ;:;:-· . /}\....

Table A-3 Equations for Bcache and

..-:===t=mttillt

NO~ ~::lll'tJ\,]Jj;;h '<Y
··:·:·:-:·:·:·:·:<-:·:·:·:·:-:·:·:·:·.

tagCtlWEJ 1 =
tagAdrWE_l 1 =
1# = OR, & = AND, ! = NOT

A-4 Digital Confidential

! ( cpuTagcitlW~====~:::iY..~.)
! ( sy8=]1···!~:~\=:·

··=·==::::{:~\\\~:j:~=~\·~j:".::?>