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Document:	TMA11-M DECmagtape System Maintenance Manual
Order Number:	EK-TMA11-MM
Revision:	PRE
Pages:	248
Original Filename:

OCR Text

TMA11-M
DECmagtape system

maintenance manual

digital equipment corporation - maynard. massachusetts

]

. .,.//

TMA11-M

DECmagtape system
maintenance manual

EK-TMA11-MM-PRE

digital equipment corporation - maynard. massachusetts

1st Edition, May 1975

The material in this manual is for informational

purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this

manual.

/Pri»nted in U.S.A.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

CONTENTS

PART I SYSTEM INFORMATION
Page
CHAPTER 1

INTRODUCTION

1.1

INTRODUCTION

e e e e e e e e e e e e e e e e

1-1

1.2

SYSTEM CONFIGURATION

. ... ... .. S

1-1

1.3

APPLICABLE DOCUMENTS

. . . . . . o

1-4

1.4

MAGNETIC TAPE FUNDAMENTALS — DEFINITIONS

. . .. . ... ... .......

1-5

1.5

RECORDING METHODS AND DECmagtape FORMATS

. . ...
.e

1-6

. . .

1.5.1

NRZI RecordingMethod

1.5.2

Tape Format

s e e e e e e e e e

. . . . . . . . . . . . . . .. ...

. ... ... ... .......... e e e e e e e e e e e e

1-7

. . . . . . .. .. ... ........

1-9

1.5.3

Cyclic Redundancy Check (CRC) Characters

Longitudinal Redundancy Check (LRC) Character

1.5.5

Data Files

1.5.6

Track Assignments

. . . . . . . .

. . . . ... ... ........ 1-10

. . . . . . . . . .

CHAPTER 2

INSTALLATION

2.1

SITE PLANNING AND CONSIDERATIONS

e e e e e

. . . . . . . . . . .

Space Requirements

. . . . . . . . . . .

L L

2.1.2

Power Requirements

. . . ... ... .. e

e e e e e e e e e e e

2.1.3

Environmental Requirements

e e e 1-10

e e e e e e e e

2.1.1

UNPACKING

1-6

e e .

1.5.4

2.2

e e e e e e e

e e e 1-10

2-1

e e

2-1

e e e e e

2-1

e e e
e

. . . . . .. . .. ... ... ... .

... -

2-1

. . e
e e e e e e e e e

2-1

2.2.1

Cabinet Unpacking Instructions

2.2.2

Device Unpacking Instructions

2.3

INSPECTION

2.4

INSTALLATION

. . . . . . . . . . . . .. ... ... .. ... ...
. . . . . .. . .. ...

. . .
. .

...

e
e

L 0oL,

e e e e e e e e e
e e e et e e e e

2-1
2-3

e e

2-3

24.1

Cabinet Installation

. . . . . . . . . . . .. ...

2-3

2.4.2

Device Installation

. . .. ... PR e

2-3

2.4.2.1

TSO03 Mounting Instructions

... ... ..

2-3

24.2.2

TMA11 Controller Mounting Instructions

. . . . . .. ... .. ........

2-4

24.2.3

H720 Power Supply Mounting Instructions

. . . .. . ... ... .......

2-4

243

I/O Cable Connections

24.4

Power Connections

CHAPTER 3

. . . . . . . . . .. .. .. ...

. . . . ... ... e e e e e

e e e

2-4

e e e e

e e

2-5

. . . e
e
e
e e

3-1

. . . . . . . . . . . .

e e e e e e e e
e e e

SYSTEM OPERATING INSTRUCTIONS

3.1

SCOPE

3.2

CONTROLS AND INDICATORS

3.3

OPERATING PROCEDURES

e e e

3-1

. . . . . . . . . . e
e

3-1

. . . . . . . . . . . . e

3-1

3.3.1

Tape Threading

3.3.2

Tape Loading

3.3.3

Placing Tape Unit On-Line

. . . . . . .

. . . . . . . . . .

3-1

...

3-1

. . . . . . . . . ... .. ... ... ... . .. ....

3-3

. . . . . . . . . . e

3-3

3.3.4

Tape Unloadingand Rewind

3.3.5

Power Shutdown

e e e e e e

. . . . . . . . . . . . . . . . . .

1i1

. .

CONTENTS (Cont)
Page

CHAPTER 4

CUSTOMER EQUIPMENT CARE AND OPERATION

4.1

SCOPE

4.2

REQUIREMENTS

. . . . . . eT

4.3

CARE OF MAGNETIC TAPE

4.4

CARE OF TS03 TAPE TRANSPORT

4.4.1

General

4.4.2

Preventive Maintenance

44.3

Materials Required

CHAPTER §

4-1

. .. ... ... .. ... .. ... ....... P

. . . . . . . . . .

4-1

4-2

. . . . .. . .. ... ... .. ..... .

4-2

. . . ... ... .. ... e

e e e e e e

4-2

e e

4-2

. . . . . . .. ... ... .. ... ..., P

4-3

. .. ... ... ...... e e

5-1

. . . . . . .e

e e e e e e

SYSTEM MAINTENANCE

5.1

SCOPE

5.2

MAINTENANCE PHILOSOPHY

5.3

TEST EQUIPMENT

. . . . ... ... ... ....... e

e e

. . . . . . . ... ... .. .. ... .. ....... e

5-1

e e

5-1

5.3.1

Standard Test Equipment

. . . . . . . . . . .. ... ...

5-1

5.3.2

Special Test Equipment

. . . . . . . . . .. .. ...

5-2

5.3.3

General Tape Kit

. . . . . . . . . . . . . e 52

5.4

PREVENTIVE MAINTENANCE

5.5

TS03 DECmagtape TRANSPORT ADJUSTMENTS

5.5.1

Photosensor Adjustment

5.5.2

Magpot Adjustment

5.5.3

Capstan Zero Adjustment

5.6

TESTPANELUSE

. . . ...
. e

e e e

e e

5-2

. . . . . . . . . .. .. ... .. ... 5-10

. . . . . ... ... ... ... e 5-11

. . . . . .. .. .. e e e e e

e e

e e 5-11

. . . . . . . .. . ..o 5-11

. . . . . . . e
s e 5-11

5.6.1

Operations

. . . . . . . . . . . . ee

5.6.2

Indicators

. . . . . .. L

e e e e e 5-12

e 5-12

5.6.2.1

SKEW Indicator

. . . . . . . . .. ... ... ..., e

5.6.2.2

DATA Indicator

. . . .. ... ... ... ...... P 5-14

5.6.2.3

LOAD POINT Indicator

5.6.2.4

EOT Indicator

5.6.3

Utilization Procedures
Speed Adjustment

5.6.3.2

Ramp Time Adjustment

5.6.3.3

Rewind Speed

5.6.3.4

Read Level Adjustment

5.6.3.5

Skew Adjustment
TAPE PATH ALIGNMENT

e e e e e 5-14
e e e

e e e e 5-14

. . . . . . ... ... ..... [P 5-14

5.6.3.1

5.7

. . .. ... ... .. ..... e

. . . . ... ... ...... . e

e e 5-12

. . . . ... L L. 5-14
. . . . . . . . . . . . . . ... 5-14

. . . . . . . .. L. 5-15

. . . . . . . . ..

.. Lo 5-15

. . . . . .. ... e e e e 5-15
. . . . . . . . . .. . 5-16

5.7.1

Alignment Procedure

5.7.2

Tape Path Alignment Without Use of Alignment Tool

. . . . . . . . ... ... ... ... e

5.8

HEAD FACE SHIELD ADJUSTMENT

5.9

CORRECTIVE MAINTENANCE

5.9.1

TMAI11-M Diagnostics

59.2

Corrective Action Flow Diagram

59.3

Maintenance Block Diagram

e e 5-17

. . . . . . .. . ... ... .. 5-18

. . . . . . .. .. . ... ... ... .. ..... 5-19

. . . . . . .

. . . . . . . .. ... .. ... .. e

e e e e e e 5-19
e e

e e .. 5419

. . . . . . . .. . . ... ... 5-19

. . . . . . . . . ... ..o 5-19

CONTENTS (Cont)

594

TMA11 Controller TroubleshootingHints

5.9.5

TSO03 Transport TroubleshootingHints

. . . . . . . . ... ... ... ... .. ..

59.6

TS03 Transport Troubleshooting Tables

. . . . . . ...
.. .. e

5.9.7

Troubleshooting Procedure

5.10

PARTS REPLACEMENT

. . . . . . ... ... ... .... e

. . . . . ...
.e

e e e e e e e

e e e e e e e e e

. . . . . .. ... ... .. ... ..... e

5.10.1

Supply Tension Arm Roller Guide

5.10.2

Takeup RollerGuide

5.10.3

Tension Arm Replacement

. . . ...
.. .. e

e e

e e e e e e e e e

. . . . . . . . .. .. ... .. ... ...... e
. . . . . . . . .. ... ...

5.10.4

Reel Motor or Belt Replacement

5.10.5

Capstan Motor Replacement

5.10.6

Supply Hub Replacement

5.10.7

Magnetic Head Replacement

5.10.8

Photosensor Replacement
Magpot Replacement

5.10.10

Tape Cleaner Replacement

e e e e

L L.,

. . . . .. . ... ..................

. . . . . . . .. .. ... ... .. e

e e e e e e

. . . . . . . . .. .. ... ... ...

5.10.9

.... P

. . . . . . . . . . .. . ... ... ... .. . ...

. . . . . . . . . . . .. ...

. . . . . . . . . . .. ... ...

. . . . . . . . . . .. .. . ... ... ... ...,

APPENDIX A

TMA11 INSTRUCTION TEST (MAINDEC-11-DZTMA-E)

APPENDIX B

TS03 SUPPLEMENTAL INSTRUCTION TEST (MAINDEC-11-DZTSF-A)

APPENDIX C

TS03 DRIVE FUNCTION TIMER (MAINDEC-11-DZTSE-A)

APPENDIX D

TMA11 MULTIDRIVE DATA RELIABILITY EXERCISER (MAINDEC-11-DZTMH-A)

ILLUSTRATIONS
Figure No.

Title

1-1

TMA11-M System Configuration

1-2

Major Assemblies

1-3

- Reference Edge of Tape

1-4

)

[

ooooooooooooooooooooooooooooooooooo

Track-Bit Weight Relationship for Nine-Channel Transport

1-5

Data Recording Scheme

1-6

Tape Format

...................................

. . . ... ... . . ...

2-1

Space and Service Clearance

2-2

Cabinet Installation

ooooooooooooooooooooooooooooooooo

. . . . . . . . . . . . . . . e

2-3

I/O Cable Connection Diagram

2-4

Power Connection Diagram

3-1

Controls and Indicators

3-2

Tape Threading Diagram

4-1

Opening Head Shield

5-1

Opening Head Shield

................................

ooooooooooooooooooooooooooooooooo

ooooooooooooooooooooooooooooooooooo

[

ooooooooooooooooooooooooooooooooooooo

ILLUSTRATIONS (Cont)
Title

Figure No.

5-2

Use of Alignment Tool

5-3

Roller Guide Adjustment

5-4

Magpot Position Sensor Assembly

5-5

Page

. . . ... ... ...... e
e .e

e e e

. . . . . . . ... ..o Lo e

e e

5-5

e e e e

5-6

Plug-In Module and Test Point Locations

. . . . . . . .S

5-8

5-6

Adjustment SEqUENCE

. . . . . . .. e

5-7

Test Panel Installation

. . . . . . . . . . . .

5-8

Model 9900 Test Panel

. . . . . . . . . . . . . . .

5-9

Ramp Time Adjustment

. . . . . . . . .. . L

5-10

Head Skew Adjustment

. . . . . . . . .

5-11

Skew Adjustment Waveforms

5-12

Capstan Parallelism Adjustment

5-13

TMAI11-M Corrective Action Flow Diagram

5-14

TMA11-M Maintenance Block Diagram

5-15

Reel Hub Adjustment

. . . . . .. ..o o0 e

e e e

e e

e R 5-10

e e

e 5-13

e 5-14

e e e 5-12

L e 5-16

. . . . . . . . . ... Lo 5-17

. . . . . . . . .. .. .

.. oo 5-18

. . . . .. ... ... ... e

e e e e e e e 5-20

. . ... ... ... T e

e e 5-21

. . . . . . . . . . . . . . e 5-29

TABLES

Title

Table No.

1-1

Applicable Documents

.. . . . . .. . L L L

1-2

Five-Character Record

. . . . . . . . . . . . . .

1-3

CRCC In Register When Writing

1-4

TSO3 Track Assignments for Data and Parity

L L

e e e e e e

1-4

o e

1-9

. . . . ... ... .. e

e e e e

BCO8A-10 Cable Connections

2-2

Power Harness Color Coding

4-1

Customer Equipment Care Operations . . . . . . . . . . . . ..
Standard Test Equipment Required
. . . . . ... .. .. e e e e

5-2

5-3
5-4

5-5

5-6

e e e e

. . ... ... .. ... .. ......... 1-10

2-1

5-1

Page

. . . . . . . . . . . . .
. . . . . . . . . . . . .

v
o

vt i ittt

v i v i it

v
v .
e e e e e e e

2-5
2-6

43
5-2

Special Test Equipmentand Tools . . . . . . . . . .. ...
o 0oL 5-2
TSO03 Preventive Maintenance Procedure . . . . . e e e e e e e e e . 5-3
TS03 DECmagtape Transport Troubleshooting Hints
. . . . .. . ...
.S 5-22
High Error Rate Troubleshooting
. . . . .. ... ... ... ..... e e e e
e e 5-25
Control Malfunctions Troubleshooting . . . . .. ... ... .. ... ... e e 5-26

CONTENTS
4

PART Il TMA11 CONTROLLER

CHAPTER 1

INTRODUCTION

1.1

GENERAL DESCRIPTION

. . . . . .. . ... ..

1.2

PHYSICAL DESCRIPTION

. . . ..

1.3

SPECIFICATIONS

CHAPTER 2

PROGRAMMING INFORMATION

2.1

SCOPE

2.2

DEVICE REGISTERS

... ...

e e e

. . . _ . . e

. . . .. ... ... .. .. e

Status Register MTS)

22.2

Command Register MTC)

. . .. ...
.. e

. ... .. e

Byte Record Counter MTBRC)

e e .

e e e e e

e e e

. . . . ... ... .........

Current Memory Address Register MTCMA)

2.2.5

Data Buffer Register MTD). . . . . .. .. .. ... ........

2.2.6

TSO3 Read Lines(MTRD)
INTERRUPTS

. . .. ... ... ..

. . . ... ... ... ... .......

2.3.1

NPRRequests
BRRequests

2.4

PROGRAMMING NOTES

. . .. . .. ... .. ... ...

. ...

...

. . .. .. .. . . .. ...

...

Rewind Operation

. . . .. ... ... ... ... .........

24.2

New Drive Selection

. . . . . .. .. ... ... ... .......

243

ErrorHandling

24.3.3

. . . . ... ... .. ... ... ...

......

Write Operations

. . . . . . .. . .. ... ... .......

Read Operations

. . . . .. ... ... ... .........

Write End-of-File Operation
. .

. . . .. ... ... .......

2434

Spacing Operations

2.4.3.5

Write-With-Extended-IRG Operation

24.3.6

Rewind Operation

. . . . .e

e e e e e e e e e e

. . . . . .. .. .. ...

ooooooooo

PROGRAM EXAMPLE

CHAPTER 3

THEORY OF OPERATION

3.1

INTRODUCTION

. . . .. .

. e
e

3.2

FUNCTIONAL DESCRIPTION

. . . . ... ... .. ... .......

3.2.1

Parity

3.2.2

Gap Shutdown

ooooooooo

. . ... ... ... ... . ... ... .....

. . . . . e
e

. . . . . .. ... .

FunctionCommands

3.3

SYSTEM RELATIONSHIP

3.4

ADDRESS SELECTION

ooooooooo

. . . . . .. ... ... .. ........

2.5

3.2.3

ooooooooo

.........

. . . .. . .. ..

24.1

24.3.2

ooooooooo

. . . . . . . .

2.3.2

24.3.1

ooooooooo

e e PP

2.2.4

2.3

ooooooooo

... ...

. . . . . . . .

2.2.1

223

.. . ...

ooooooooo

. . . . ... ... .. .. ...........
. . . .. ... ... .. ... ........
. . . . .. . . .. ... . . ... ... .....

3.4.1

Address SelectorModule

3.4.2

. . . . ... ... ... ... ... . ...

. . . . . .. ... .. ... ... .......

Vil

oooooooooo

ooooooooo

CONTENTS (Cont)
Page

3.5

3.5.1

BUS CONTROL

. . .

NPR Transfers

3.5.2

Interrupt Request

3.5.3

Slave Response

3.6

3.7

Initialize Logic

Command Register MTC)

e e e ee

e e

. . . ...
.e e e e e e e e e e e

Density Bits (14and 13)

3.7.2.3

Power Clear Bit (12)

Parity Bit (11)

. . . . . . . . . . . .

. ..

3-15

... e 3-16

Unit Select Bits (10,09,08)

. . ... ... ...... e

Control Unit Ready Bit(07)

. ... .. ... ....... e

3.7.2.7

Interrupt Enable Bit (06)

3.7.2.8

Extended Bus Address Bits (05and 04)

3.7.2.9

Function Bits (03,02,01)

3.7.2.10

GOBit (00)

. . . . .. .. .. e

e e e

e e 3-16
e e e 3-17

e e
e e 3-17

. . . . . . ... .. ... ... .... 3-17

. . . . . . . . . . . ... o 3-17

. . . . . e 3-18

Status Register MTS)

. . . . . . . . . ... .. ... ... B 3-19

Illegal Command (15)

. .. ... ... ... . e e e e

3.7.3.3

Cyclic Redundancy Error Bit (13)

End-of-File Bit (14)

. . . . ... .. ... ... e

3.7.3.4

Parity Error Bit (12)

. . . . . . . . . . .

3.7.3.5

Bus Grant Late Error Bit (11)

3.7.3.6

End-of-Tape Bit (10)

3.7.3.7

Record Length Error Bit (09)

3.7.3.8

e e

. . . . .. ... .... P e e 3-16

3.7.2.6

3.7.3.2

e e 3-14

. e 3-15

. . . . . . . . . . . . . .

3.7.2.5

3.7.3.1

e e 3-12

. . . . . . o e e 3-15

3722

3.7.3

3-12

e e

. . ...
... ... P 3-13

. . . . . . . . . . o

Error Bit (15)

. . . .o oot e . 3-13

3.7.2

3.7.2.4

e e e e e e e e e 3-10

. . . .. ... ... .. ... ..., L

3.7.1

3.7.2.1

e s e

. . . . . ... .. .. .. ...... e

BUS DRIVERS AND RECEIVERS

CREGISTERS

. . . . ... ... .. ... ...... e

e e e 3-19

e e 3-20

. . . ... ... e I 3-20
... ... e

. . . . . . .. e

e e e e e e

. . . . ... ... .. .. .

e e e e 3-20
e e 3-20

... ... . ...

..., 3-21

. . . . ...
.. [ 3-21

Bad Tape Error/Operation Incomplete Bit (08)

. . . . . .. .. .. ... ... 3-21

3.7.3.9

Non-Existent Memory Bit (07) . . . . . . e 3-22

3.7.3.10

Select Remote Bit (06)

3.7.3.11

Beginning-of-Tape Bit (05)

3.7.3.12
3.7.3.13

7-Channel Bit (04) . . . . . . . . .
e 3-22
Settle Down Bit (03) . . . . . . . . ... 3-22

. . . ... ... .....e

3.7.3.14
3.7.3.15
3.7.3.16
3.7.4

Write
Lock Bit (02)
. . .
Rewind Status Bit (01) . .
Tape Unit Ready Bit (00)
Byte Record Counter MTBRC)

3.7.5

Current Memory Address Register MTCMA)

3.7.6

Data Buffer Register (MTD)

3.7.7

TS03 Read Lines(MTRD)

3.8

3.8.1

3.8.2
3.8.3
3.9

TAPECONTROL

Unit Selection

e e 3-22

. . . . . .. e e e e e e e

e ee
e e 3-22

. . . . . . .

e 3-22

. ... ... .. ... ... .. e e e e e e e 3-23
. . .. ... ... .. e e e e e e e e e e e e 3-23
. . . . . . . .. ..

...

.. . ...
.. ..e

.. ..., 3-23

e e e e 3-23

. . . . . . .. .. .. ... ... ... O 3-24
. . .. ... ... .... e

e e e e e e e 3-25

. .. ... ... ... ........ e e e e e e e

. . . . . .. ... ... . .

.. ... e

Function Control
. . . . . . .. .. . ... ... .. ..., e
Ready and Start Control . . . . . . .. e
e e
e e
e e e
TIMING DIAGRAMS
. . . .
e e e
e e e

Viii

e e e 3-26

e e e e e e e e e e e 3-26

e e e e e 3-26
e e
e 3-26
e 3-26

CONTENTS (Cont)
Page

CHAPTER 4

MODULE DESCRIPTION

4.1

INTRODUCTION

4.2

DEC LOGIC

4.3

MEASUREMENT DEFINITIONS

4.4

APPENDIX A

MASTER TAPE TRANSPORT SIGNALS

A.l

SIGNALS FROM TS03 to TMA11 CONTROLLER

SIGNALS FROM TMA11 CONTROLLER TO TS03

......................................

. . . . ee e e e e e e e
oooooooooooooooooooooooooooooo

oooooooooooooooooooooooooooooooooooooooooo

.....................

....................

4-1
4-1
4-1

4-1

A-1
A-2

ILLUSTRATIONS

Figure No.

Title

Page

2-1

Status Register (MTS) Bit Assignments

2-2

Command Register (MTC) Bit Assignments

2-3

Byte Record Counter (MTBRC) Bit Assignments

Current Memory Address Register (MTCMA) Bit Assignments

Data Buffer Register (MTD) Bit Assignments

. . . . . . .. . .. . .. ... ... .......
. . . . . . . . . . .. ... .. ....e...

oooooooooooooooo

Relationship Between Tape Characters and Memory Byte Characters

TS03 Read Line (MTRD) Bit Assignments

2-8

New Drive Selection Flowchart

3-1

EOF Record

3-2:

TMA11-M System — Simplified Block Diagram

3-3

M105 Address Decoding

3-4

Derivatives of GO Signal

oooooooooooo

oooooooooooooooooooooooooo

...............................

. . . . . . . . . o e
e e e e
e

oooooooooooooooooooooooooooooooooooo

3-5

Start of Tape Operation

3-6

Spacing Forward Three Records

. . . . . . . . . . . . . .

3-7

Spacing Reverse Three Records

3-8

Spacing Forward Three Records, Bad Tape Error Appearing in First Record

3-9

Reading Record of Three Data Characters

3-10

Writing Record of Three Data Characters

2-11
2-14
3-6
3-8
3-18

e 3-27

e e e e e e e e e e e e

e e e e e 3-28

. 3-27
.. . . . ...
... e

ooooooooo

oooooooooooooooooooooooooo

TABLES
Table No.

Title

2-1

Standard Device Register Assignments

3-1

Controller Functions

3-2

M797 Decoder Selection

3-3

Gating and Select Line Signals

3-4

Bus Control Functions

oooooooooooooooooooooooooooo

. . . . . . . . . . . . . .
. . . . . . . . .. . L

e e
e

e e

oooooooooooooooooooooooooooooooo

. . . . . . . . . . . . ..

Device Register Functions

2-11

.......................

...................................

Module Utilization

. . . . . ... ... ... ... ....... 2-10

2-7

3-5

2-6

. . . . . . ... ... ... .......

2-6

4-1

2-2

ooooooooooooooooooooooooooooooooo

oooooooooooooooooooooooooooooooooooooo

3-28
3-29
3-30

CONTENTS
PART III TSO3 DECmagtape TRANSPORT

Page
CHAPTER 1

GENERAL INFORMATION

1.1

GENERAL DESCRIPTION

. . . . . . . .

1.2

PHYSICAL DESCRIPTION

. . . .. . . .. ... . .. ... ...... e

1.3

ELECTRICAL AND MECHANICAL SPECIFICATIONS

CHAPTER 2

THEORY OF OPERATION

2.1

INTRODUCTION

2.2

TRANSPORT OPERATIONS

2.2.1

Write Operation

. . . . . . . . . . . L

2.2.2

Read Operation

. . . . .I e

2.2.3

Rewind Operation

2.3
2.3.1

e e e s e

. . . .

1-1

..................

1-1

e e e e e e e e e e e e e

2-1

e e e e e e e e e e

2-2

e e e

e e

2-3

e e e e e e e e

. . .. ... .. ... ... .....

2-4

e
o

FUNCTIONAL BLOCK DIAGRAM DESCRIPTION
Adapter Logic

1-1

e e

. . . . . .

. . . . . . . . . . . . .

e e

e e e e e

. . . . . . . .

e
e

. ... ......... e

e e e e

e e

2-4

e e e e e e e e

2-4

2.3.1.1

Control Logic

2.3.1.2

Write Logic

. . . . . . ... ... .... e

2.3.1.3

Read Logic

. ... ... e e e 2-13

2.3.2

Transport Control Logic

e e e e 2-12

. . . . ... ... ... ...e 2-13

2.3.2.1

Functional Operation

2.3.2.2

Transport Control Logic Operation During a Wnte Sequence

2.3.2.3

TestPanel

2.3.3
2.3.3.1

2.3.3.2

2.34

Servo System

. . . . . . . o . . . .
e

. . . . ...
.e

Capstan Servo

. . .. .. .... 2-15

e 2-19

. . . . . .

Reel Servos

Data Section

. . . . . . . . . . . . . . .. e 2-13

e e e e

e e e e e e e e e
e e

e e e e

e e e

e e

. . . . . . . . . ... e

. . . . . . . L L L

e e

e e 2-19

e e e 2-19

e e e

e e e e e e e

Write Electronics

. . . . . . ... e e e e e e e e e

2.3.4.2

Read Electronics

. . . . . . . . . .. Lo 2-23

DETAILED LOGIC DESCRIPTIONS

2-20

2.3.4.1

CHAPTER 3

e e e

2-20

e e e- 2-20

3.1

INTRODUCTION

3.2

NOTES TO TRANSPORT SCHEMATIC DIAGRAMS

. . . o oove e e
. . . . .. . .. ... ... .. ...

3-2

3.3

TYPE M8920 ADAPTER CIRCUITDESCRIPTION

. . . .. ... ... ..........

3.3.1

Clock Logic

. . . . . . . . . . . .

3.3.2

Read/Write Control Logic (ROM/Delay Counter)

. . . . .. ... ... ... ....

. . . . . . ... ... .... e .. ...

3.3.2.1

Write Operation

33.22

Rewind Off-Line Operation

3.3.3

Shutdown Logic

3.3.4
3.3.4.1
33.4.2

Write File Mark Circuit

e e e

. . . . . . . . . . . . .. . ...

. . . . . . . . . .

Write Strobe Generation Logic

. . . . . . . . . . . .. ..o

3-6

Write Data Circuit

e e e e e e e e e e e e e

e e

3-6

. . e

3-6

. . . . ... .. .. .. e

3.7

. . . . . . . . . . . .

Record and File Mark Detection Logic

3.3.5.1

File Mark Record Detection

3.3.5.2

Data Record Detection

e e e

3-5
3-5

3.3.5

... ...,
e

. . . . . .. .. e

e e e e e

3-1

. . . . . . . . . . . . . .

. . . . . . . . . . . . . . ..

3-7

CONTENTS (Cont)
Page

MODEL 9700 POWER SUPPLY CIRCUIT DESCRIPTION

3.4
3.4.1

Primary Power

3.4.2

Secondary Power

3.4.3

3.4.4
3.4.5

3.4.6

3.5

.. . . . . . L L

3-8

-10Volt Regulator

. . . . . . . . . . .

e e

3-8

e e e e e e

3-8

. e

3-8

Short-Circuit Protection

. . . . . . . . . . . . .

e e e e e e

. . .. ... ... ... ..

3-8

. . . . . . . . . . . . .. oL

Rewind Flip-Flop

3.54

End-of-Tape

. . . . . . . . . .

3.5.5

Output Status

. . . . . . .

. . . . . . .. ... .o, e

. . . . . . . . . .
.

e e e e e e e e

3.6.2

Busy

39
39

e e

e e e e e

3.6.3

Write Ready

3.6.4

Test Panel Control

e e e ee

. .. ... ... .. 3-10

e e e e

. . ... .. ... ... ......... e
. . . . . . . . . . .

. . . . . . . ...

e e e e e e

BOT, EOT, and BKN Sensor Amplifiers

3.8.2

File Protect Circuits

3.8.3

Write, Erase Drives

e 3-12

e e e

Capstan Servo Amplifier Stage

3.9.2

Reel Servo Amplifiers
Servo Adjustments

. .. .. ...
.. 3-12

e e e e

e e e e e e e e e

TYPE 4306 SERVO PREAMPLIFIER CIRCUIT DESCRIPTION

3.9.1

e 3-11

. . . . . . . ... . ... .......... 3-13

. . . . . . . . . . . . i

. . . . . . . . L

. .. ... ....... 3-11

TYPE 3844 SENSOR AMPLIFIER DRIVER CIRCUIT DESCRIPTION

3.8.1

e e e e e 3-10

e e e e e e e e 3-11

e e e e e e e e e e e e e 3-11

TYPE 3194/3645 RAMP GENERATOR CIRCUIT DESCRIPTION
Adjustment Procedure

e e e 3-10

....................e

. ... ... ........ e

e eS

MODEL 9000 TAPE MOTION CONTROLS CIRCUIT DESCRIPTION
Front Panel Pushbutton Controls

e e e e e e e

o e
.

3.6.1

3.9.3

TYPE 3842 ADAPTER CONTROL CIRCUIT DESCRIPTION

3.5.3

e e

. . . . . . ... ... .... e e

Write Select

3.8

34T

3-7

3.5.2

3.7.1

e e e e e

3-7

. . . . . . . . . e
e e e e

+5 Volt Regulator

e e e e e e e

+10 Volt Regulator

Tape Motion Controls

3.7

e e

3.5.1

3.6

. . . .. ... ... ... ...

. . . . . . . . . . . .

e 3-13

. . .. .. ... ..... 3-14

. . . . . . . . . . . . ...

. . . . . . . . . . . L

e e e e e

e e e e e e e 3-13
e

e 3-14

e e e e e e e

e e 3-14

. . . . . . Lo L L L Lo

e e e

e e e e 3-14

3.10

TYPE 3631 READ PREAMPLIFIER CIRCUIT DESCRIPTION . . . .. .......... 3-14

3.11

TYPE 4218 MAGPOT TENSION ARM POSITION SENSOR CIRCUIT DESCRIPTION

3.12

TYPE 4845 DELAY TIMING CIRCUIT DESCRIPTION

3.12.1

Crystal Oscillator Divider

3.12.2

Skew Gate Generation

3.123

Skew Lamp

3.124

Write Mode

. . . . . . . .

3.12.5

Test Mode

. . . . . . . .

3.12.6

Gap Detection

3.12.7

Start Delay

. . . . . e e

3.12.8

Datalamp

. .. ... ... ... . ...

3.12.9

Adjustments

3.13

. . . . . . . . . . .

. . . . . . . . . . L L. .

... 3-15

. . . ... ... ... ...... 3-16
e e e e e e e e e e e e 3-16

e e

e e e e e e e e e e e e e e 3-17

. . . . . . . L e P 3-17
e e e e e e e e e e e

e e

. . . . . . . . .

e e e e e e e e e e

e 3-17

e e e e 3-17

e e e e e e e e e e e e e e e e e
0

L. e

. . . .. ... ..o
L L.e

TYPE 3848 WRITE AMPLIFIERS CIRCUIT DESCRIPTION

e 3-17

e e 3-17
e e e e e

e e

e e e 3-18

e e e e e e 3-18

. . . . ... ... .. .... 3-18

3.13.1

Write Data Strobe Generation

3.13.2

Write Amplifier Stages

. . . . . . . . . . . L L L. 3-18

Write Amplifier Reset

. . . . . . . . . . L L

3.13.3

. . . . . . . . . . . . . ...

e e 3-18
e e 3-19

3.14

TYPE 4178 QUAD READ AMPLIFIER CIRCUIT DESCRIPTION

3.15

TYPE 4179 READ AMPLIFIER/CLIPPING CONTROL CIRCUIT DESCRIPTION

. .. ... .. ... .. 3-19
. .. .. 3-20

CONTENTS (Cont)
Page

CHAPTER 4

PARTS IDENTIFICATION

APPENDIX A

TRANSPORT SIGNAL DESCRIPTIONS AND INTERFACE INFORMATION

A.l

INPUT SIGNALS

. . .
e e s e e s e s e e

A.1.1

Setup Commands

A.1.2

Tape Motion Commands

A.1.3

Write Commands

A.1.4

Read Commands

A.15

Shutdown Commands

INTERFACE OUTPUT SIGNALS

A2.1

Status Outputs

A22

Read Qutputs

. . . . . . . . . L L

e e e

A-1

ooooooooooooooooooooooooooooooooo

A-2

ooooooooooooooooooooooooooooooooooooo

. . . . . . . . . . . . .

e e

A-3

. . . . . . . . . . . . . . ... e

A-3

[

¢«

A-3

. . . . . . . . e
e e

SUMMARY OF INTERFACE CHARACTERISTICS

APPENDIX B

DEC/VENDOR TS03 TRANSPORT PART NUMBERS

---------------------

ILLUSTRATIONS

Title

Figure No.
1-1

TS03 Transport and TSO3 Adapter Module (M8920)

1-2

TS03 Transport Physical Dimensions

2-1

TSO3 Block Diagram

2-2

Adapter Block Diagram

2-3

Control Logic Functional Block Diagram

2-4

Commands Processing Sequence Flow Diagram

2-5
2-6

oooooooooooooooooooo

oooooooooooooooooooooooooooooo

. .. . . . . . . . .

. . . . . . . . L L

. . . . . ... .. ... ...

Write Operation Flow and Timing Diagram

2-8

Write File Mark Operation Flow and Timing Diagram

2-9

Read Logic Functional Block Diagram

2-10

Control Logic Block Diagram

[

Reel Servo System

2-13

Typical Write Amplifier Channel (0—7), Fixed Channel P Delay

2-14

Skew Characteristics

¢+

ooooooooooooooooooooooooooooooooo

Write Data Section

oooooooooooooooooooo

2-12

. . . . . . . . . .. . ... ... ... ...,

2-11

.. ... .....

oooooooooooooooooooooo

2-7

e e

. . . . . .. . . ... ... ... .....

Control Logic BOT Write Operation Flow Diagram
- Write Logic Functional Block Diagram

e e e

e e

. . . . . . . . . L L

e e

e e e

4«

e e e e e e e e

e e e

ooooooooooooooo

ooooooooooooooooooooooooooooooooooooo

2-15

Read Data Section

3-1

Clock Logic Timing

3-2

Differential Transformer

4-1

Front Panel Parts Identification

4-2

Tape Transport Parts Identification (Top View)

4-3

Tape Transport Parts Identification (Rear View)

A-1

Summary of Adapter Characteristics

oooooooooooooooooooooooooooooooooooooo

. . . . . . . . . .« o o

. . . . . . . . .

e e e e e e e

e e e

e e e e e e e e e e

. . . . . . . . . . . . ... ...

..o

........................

.......................

oooooooooooooooooooooooooooooo

Xii

A-5

TABLES

Title

Table No.

2-1

Operations Versus Commands Required

2-2

Commands and Corresponding Delays

2-3

Adapter To Transport Signal Name Cross Reference

Page

. . . . . . . . . .. .. .. ... ...,
. . . . .. . .. ..e

e e e e e

e e e e

2-7
2-7

. . . . . ... ... ... ....... 2-16

2-4

Transport Status

4-1

[llustrated Parts Breakdown for Figure4-1

. . . . ., . ... ... .. ... ... .....

4-3

llustrated Parts Breakdown for Figure4-2

. . . . . . . . .. ... . ... ... ......

4-5

. . . . . . . . L

e e

e e e e e e e e e e e e e e 2-18

4-3

[llustrated Parts Breakdown for Figure4-3 . . . . . .. ... .. .. L. e e e e e e e

4-4

Replaceable/Spare Parts

Xiil

4-6

PREFACE

This manual provides a complete description of the TMA11-M DECmagtape System. Included are installation
instructions, operation and programming information, functional block and logic level descriptions, preventive and
corrective maintenance procedures, and removal and replacement procedures. The manual is divided into three parts:

Part I — Contains a general description of the system and complete system installation instructions.

Also contains maintenance information including customer care and operation, preventive maintenance,
corrective maintenance, and removal and replacement procedures.

Part

—

Contains

complete

description

the

TMAI11l

Controller

including

specifications,

programming information, and functional block, logic level, and flow diagram descriptions.

Part II1 — Contains a complet.e description of the TSO3 DECmagtape Transport including specifications,
operation, and functional block, logic level, and flow diagram descriptions.

rrrrrr

PART 1

SYSTEM INFORMATION

Part |

7461-10

TMA11-M DECmagtape System

Part I

CHAPTER 1
INTRODUCTION

1.1

INTRODUCTION

The TMA11-M DECmagtape System is a magnetic tape storage system that interfaces with the PDP-11 family of
processors and peripherals and provides storage for digital information. The system reads and records digital data in
|

parallel in a nine-channel, industry-compatible format.
1.2

SYSTEM CONFIGURATION

The TMA11-M DECmagtape System is composed of the units shown in Figures 1-1 and 1-2 and listed below.

VAN
RS

)

WRITE DATA

—

DECMAGTAPE

READ

DATA

(TMA11-A/B)

DECMAGTAPE
TRANSPORT
-

STATUS

STROBE

WRITE

DATA

)

COMMANDS

MASTER

CONTROLLER

SLAVE
DECMAGTAPE

READ

STROBE

(TS03-MA/MB)

nwCco

-C

CONTROL

WRITE

TRANSPORT

(TSO3-SA/SB
)
K

READ

DATA

STATUS

- Tac

Toc

Tac

~ bC

POWER SUPPLY

PRIMARY AC

POWER

(H720-E/F)

11-3067

Figure 1-1

TMA11-M System Configuration

DECmagtape Controller — The TMA11 interfaces the DECmagtape system to the PDP-11 Unibus. It
controls data transfers, issues control commands to the TS03 master, and monitors system operation.
Each TMA11 can control two TSO03 transports:

a master and a slave.

Slave DECmagtape Transport — The TS03-S consists of a tape transport only. In response to inputs from
the adapter, it controls tape motion and records and reads data on magnetic tape. The TS03-SA requires

115V, 60 Hz primary power and the TS03-SB requires 230 V, 50 Hz primary power.

1-1

Part I

TS03

MASTER TAPE
TRANSPORT

M8920
ADAPTER

MODULE

746 1-2

Figure 1-2 Major Assemblies (Shéet 1 of 2)

)

TS03
SLAVE TAPE

TRANSPORT

TS03

MASTER TAPE
TRANSPORT AND
M8920 ADAPTER
MODULE

TMA11

CONTROLLER

H720

POWER SUPPLY

7461-15

Figure 1-2 Major Assemblies (Sheet 2 of 2)
1-3

Part |

Power Supply — The H720 provides switched ac and dc operating power for the TMA11-M system. Two
models of the power supply are available: the H720-E, which requires 115V primary power and the
H720-F, which requires 230 V primary power.

Master DECmagtape Transport — The TS03-M consists of an M8920 adapter module and a tape
transport. The M8920 processes commands from the controller and issues motion and read/write

commands to the master and slave transports; the M8920 also monitors status lines from the master and
slave transports. Any status changes at the selected transport are reported immediately to the controller.
In response to inputs from the adapter, the tape transport controls tape motion and records and reads

data on magnetic tape. Two models of the master DECmagtape transport are available: the TS03-MA,
which requires 115V, 60 Hz primary power and the TS03-MB, which requires 230V, 50 Hz primary
power.

1.3 APPLICABLE DOCUMENTS

Table 1-1 lists PDP-11 documents that are applicable to the TMA11-M DECmagtape System.

Table 1-1
Applicable Documents

Title

Number

H720 Power Supply and

EK-H720-TM-003

Description

A theory manual that provides a functional and detailed
circuit description of the H720 power supply.

Mounting Box Manual

PDP-11 Processor and

A series of maintenance and theory manuals that provide

Systems Manuals

a detailed description of the basic PDP-11 system.

PDP-11 Processor

A general handbook that discusses system architecture,

Handbook

addressing

modes,

the

instruction

set,

programming

techniques, and software.
PDP-11 Peripherals

112-00973-2908

A handbook devoted to a discussion of the various

- peripherals used with PDP-11 systems. It also provides

Handbook

detailed theory, flow, and logic descriptions of the
Unibus and external device logic; methods of interface

- construction; and examples of typical interfaces.
DIGITAL Logic

Presents functions and spécifications of the M-series

Handbook, 1973-74

logic modules, accessories, and connectors used in the
TMA11 Controller and the TSO3 DECmagtape Trans- port. Includes other types of logic produced by DEC but

Edition

not used with PDP-11 devices.
Paper-Tape Software

DEC-11-GGPB-D

Programming Handbook

Provides a detailed discussion of the PDP-11 software
system used to load, dump, edit, assemble, and debug
PDP-11 programs; input/output programming; and the
- floating-point and math package.

* Applicable manuals are furnished with the system at time of installation. The document number depends upon the specific PDP-11
family prccessor.

1Use the processor handbook unique to the actual CPU.

Part I

1.4 MAGNETIC TAPE FUNDAMENTALS — DEFIN‘-ITIONS
.

Reference Edge — The edge of the tape as defined by Frgure 1-3. For tape loaded on a TSO3, the
reference edge is toward the observer

BOT (Beginning-of—Tape) Marker — A reflective strip placed on the nonoxide side of the tape, against the
reference edge, 15 ft (1 ft) from the beginning of the tape.

EOT (End-of-Tape) Marker — A reflective strip placed on the nonoxide side of the tape, against the
nonreference edge, 25 to 30 ft from the trailing edge of the tape.

Nine-Channel Recording — Eight tracks of data plus one track of vertical parity. Figure 1-4 shows the
relationship between track and bit weight for a nine-channel transport.

Tape Character — A bit recorded in each of the nine channels.
Record — A series of consecutive tape characters.

File — An undefined number of records (minimum = zero, no maximum).

Interrecord Gap (IRG) — A length of erased tape used
to separate records (0.5 in. minimum for
nine-track; maximum IRG is 25 ft).
Extended IRG
— A 1ength of erased tape (3 in. mrmmum) optlonally used to separate records It must be
used between BOT and the first record.

10.

Tape Speed — The speed at which tape moves ‘past the read/wnte heads; normally stated in 1nches per
second.

11.

Tape Density — The density of sequential characters on the tape.
It is normally specified in bytes per
inch (bpi), which is equivalent to characters per inch.

12.

Write Enable Ring — A rubber ring which must be inserted on the supply reel to allow the transport to
write on the particular tape. This safety feature helps prevent acmdental destructron of previously

recorded data.

REFERENCE

EDGE

TAPE
LEADER

OXIDE
SURFACE

SUPPLY
REEL
i10-1265

Figure 1-3

Reference Edge of Tape

1-5

Part I

BIT WT TRACK _~
— —"/E:FEEDR(SEENCE |
22—
— D — — ——
RD
7
20—2

—p— — — —-

—p—

RD
6

— — —

—4—pD—
— ——

29 —— 85

—pDp— —

RD-5

RD
4

— — 1

RD3

25——6———>-—;-~————1

RD 2

2T — 7 — P — — —— 1

RD1

RD
&

—8

—p —

— — —1

22— 9 —Pp——
——1" heap
CABLE
READ HEAD

RDP
READ AMPS
11-3091

Flgure 14

Track-Bit Welght Relatlonshtp for
Nine-Channel Transport

13.

Tape Mark (TM) — A record written on the tape to designate the end of a file; sometimes referred to as a
file mark (FMK). In the TMA11-M, the tape mark is always preceded by an extended IRG.

1.5

RECORDING METHODS AND DECmagtape FORMATS

The DECmagtape system is an on-line mass storage system for programs or data. Data
is recorded on tape in vertical
TOWs, termed characters. Each character consists of eight data bits and one vertical parity bit. The vertical parity bit
is program-selected as even or odd. The odd parity bit guarantees that each character records at least one 1 bit.

The parity bit is generated according to the rule that the number of 1s in a character (parity bit included)is odd or
even. For example, if odd parity is used and the character contains an even number of 1 bits, the parity bit is
generated as a 1 bit and an odd number of 1 bits are recorded; then, if an even number of bits are read back from
tape, a vertical parity error is generated to notify the program that the data is in error.

The data characters are recorded in blocks of characters, termed records (Figure 1-5). Each record contains a
specified number of characters determined by the word count. The minimum record length is 3 characters; the

minimum word count is the 2’s complement of 3 or 7775g. If a write operation is attempted for a record with less
than 3 characters, the controller will force a minimum of three characters to be written.

Records are separated by interrecord gaps (IRGs). The IRG is 0.5 in. (approximately 0.6 in. in normal operation)
minimum, but may be extended to 3 in. by performing an extended gap operation. Tape IRGs (unrecorded areas)

provide areas on the tape for the transport to start or stop and also separate data records.

1.5.1

NRZI Recording Method

The TSO03 employs the NRZI (non-return-to-zero change on one) recording method. In the NRZI method, a 1 bit is
represented by a reversal in the direction of tape magnetization on a track; a O bit is represented by no change in
tape magnetization.

1-6

Part 1

OF
TAPE

GAP

BEGINING

FILE

RECORD 3

IGIP

RECORD J

GIP

FILE MARK: 235

—

[E RECORD 3

13A

'RECORD 3 GAP

GIP o GIP

(IRG)

‘

(IRG)

END

}

OF
TAPE

FILE MARK =23 g

il
i

v
le————APPROX 3.8"—i
|

o> o
CRCC

LRCC -

LAST DATA

CHARACTER

OF PREVIOUS

0.6

foex—f

]

|||

FILE MARK

RECORD

‘

DATA PREVIOUS—

le—1RG—ele— DATA NEXT

;

]

LAST DATA

FIRST DATA
‘
—
CHARACTER

oF PREWOUS
RECOR

CRCC

CHARACTER

LRCC

‘

| FIRST DATA

CHARACTER

OF
NEXT
RECORD

OF NEXT

FILE

RECORD

{

|[1] |t %+

LRCC

l"""O.G"—“

‘

FILE
IRG

FILE MARK AND GAP FORMAT

FORMAT

¥ =4 CHAR.SPACE
% %= 8 CHAR.SPACE
-

Figure 1-5

1.5.2

11-3069

Data Recording Scheme

Tape Format

The format (Figure 1-6) is composed of from 18* to 2048 nine-bit characters spaced 1/800 in. apart, followed by 4
character spaces, a CRC character, 4 more spaces, and an LRC character. This unit of data is called a record. At 800

characters per inch, the record
is between 1/32 in. (minimum) and 5 in. (maximum). Between each record is a gap of

at least 1/2 in. The tape structure consists of a number of records followed by a file mark (Figure 1-5). Since data is
recorded and read at high speed, IRGs are used to provide space for starting and stopping the TSO3 transports. The
TS03 transport accelerates from standstill to full speed in approximately 0.2 in. of tape and decelerates from full

speed to standstill in 0.2 in. of tape; thus, the 0.5 in. IRG provides adequate space for starting and stopping the tape
transport.

)

The CRC character (Paragraph 1.5.3) is generated in the TSO3 during a write operation and written at the end of a
record. The check character performs the same function to a record as the parity bit does to a character.

The LRC is the final character in the record and is generated so that for each track the sum of 1 bits (CRC character
included) is even. The LRC character is written on tape by clearing the write buffer in the tape transport after the

CRC character is written. The LRC strobe resets the write buffer, causing a 1 to be written on each track containing
an odd number of 1s;a 0 is written on each track containing an even number of 1s.

*USASCII program standards, not a hardware limit.

1-7

Part 1

LRC

0.005"*10% (NOTE 3)

CRC 0.005" * 10%

—»
—

REFERENCE EDGE

LNTERBLOCK GAP

(FRONT FLANGE
OF

REEL)

——t——

0.50 MIN

(NOTE 2)

/
—

0.00125"+ 3%

BLOCK ————*

WRITE TRACK

‘

TRACKS ‘ I'

}.z 048 MAX USASCII CH
18

800 CPI

MIN

USASCII

0.043" MIN

LOAD POINT

L I SO B

TTTTUITTTTEITTTITUE

STTT7TUE7

INNUVI/)

[T
ss
e o -

Lot
)

P -+

R
JE 207
A
4t :HLH?

3(RD3)

TAPE

fiH*rH

+—t

4(RDP)

—PARITY (0DD)
BEGINING

END

HH-

————————— .-

HH%HHHHH1 ‘

- H%HT

5(RD2)

Attt

6(RD1)

f—t—t

8(RDS)

MM
‘
'
{

_______t\ |

SIDE OF TAPE

7(R0O)

- TAPE

%—H+H—*————————————¢——&——+H—é—%—4+&-&—0++¢-¢—0—z - 9(RD4),

\ REFLECTIVE

END -POINT
END OF TAPE

STRIP ON NONOXIDE

(SHINY) SIDE OF
TAPE -

[

3 MIN =

INITIAL GAP
"

(NOTE 2)

TAPE MOTION

—

LEGEND

8E-0500

NOTES:
|

BP1

Tape Bits per Inch

BOT

Beginning of Tape

Tape is shown with oxide side up, read/write head on

same side as oxide. Tape shown representing 1 bits in

LRC

Longitudinal Redundancy Check

all NRZI recording;

CRC

Cyclic Redundancy Check

flux polarity, tape fully saturated in each direction.

1 bit produced by reversal of

Tape
to be fully saturated
in the erased direction in
the interrecord gap and the initial gap.

3. An LRC bit is written in any track if the longitudinal
count in that track is odd. Character parity is ignored

~ in the LRC character.
4.

CRC — Parity of CRC character is odd if an even

number of data characters are written, and even if an
~odd number of characters are written.

Figure 1-6

Tape Format

1-8

_ POT MARKER <—sTrip
ON
NONOXIDE (SHINY)

Part 1
1.5.3

Cyclic Redundancy Check (CRC) Characters

The CRC character provides a method of error detection and correction on TSO3 DECmagtape Transports. The code

has nine check bits that form a check character at the end of each record. To perform a correction, a record in which
an error has been detected must be reread into memory with the LRC and CRC characters for program evaluation.
Errors involving more than one track can be detected but not corrected.
The CRC character is generated as follows:
1.

The CRC register, located in the TS03, is cleared at the beginning of each record. As each data bit is
written on tape, it is exclusively-ORed with its corresponding bit in the CRC register.

2.
3.

The CRC regiSter is shifted one position to the right after the exclusive-OR dperation has taken place.
The bits entering CRC 2, CRC 3, CRC 4, and CRC 5 of the CRC register are inverted if the bit entering

CRCP is a 1. Data is shown in Table 1-2; the resultant CRC character is shown in Table 1-3.

Table 1-2
Five-Character Record
Characters
Bit

Data

‘Data

Data

Character 0

Character 2

Character 3

Character 4

Character S

Table 1-3
CRCC In Register When Writing

CRC Register

- CRC

.
Character 1 | Character 2 | Character 3

Final

CRCC

CRC

On Tape

-0

CRC Bits

Cleared

CRCP

CRCO

CRCl1

CRC2

CRC3

CRC4

CRC5

CRC6

CRC7

1-9

| Character 4

Part I
4.

Steps 1-3 are repeated for each data character of record.

At CRC time, all positions of the CRC reglster except CRC 2 and CRC 4, are complemented and the
resultant CRC characteris written on tape.

1.5.4

The CRC register is cleared for the next record.

Longitudinal Redundancy Check (LRC) Character

The LRC character is written four spaces after the CRC character. The vertical parity bit is always written on the
LRC character; the vertical parity of LRC is never checked. The LRC character makes the longitudinal parity even
for the entire record, 1nclud1ng the CRC. The LRC is generated in the TSO3 by the LRC regrster in the following
manner:

1.
2.

The LRC register is cleared at the beginning of a record.
As characters are written on tape, corresponding 1 bits complement the LRC register at the time data is
written on tape.

At LRC time, the LRC strobe clears the Write‘ buffer and»ls are written on tape in only those channels
for which the write buffer is set prior to clearing.

1.5.5

Following thrs method the LRC character forces an even number of brts to be recorded on each track of
the tape. The CRC characteris includedin determining the LRC character.

Data Files

As previously stated, a record is a group of characters preceded by an IRG and terminated by four spaces and an
LRC character. A file is a group of records separated by IRGs and terminated by a 3 in. gap followed by a file mark.
The file mark is a record consisting of a single data character [the end-of-file (EOF) character] followed by seven

blank characters and an LRC character. The CRC character is not written on an EOF record. The LRC character
with a file mark is a duplicate of the EOF character (235).

1.5.6 Track Assignments
The track assignments for read, write, and parity bits are shown in Table 1-4.
Table 1-4

TSO03 Track Assignments for Data and Parity
Write

Read

Track Number

Transport

Data Bits

1 (1nsrde)

WD5
WD7
WD3
WDP
WD?2

3
4
5

WD1

7
8
9 (outside)

WDO
WD6
WD4

1-10

RD5
RD7
RD3
RDP
RD2
RD1

RDO
RD6
RD4

Part

CHAPTER 2

INSTALLATION

2.1

SITE PLANNING AND CONSIDERATIONS

2.1.1

Space Requirements

Figure 2-1 illustrates the space and service clearances required. Adequate space must be provided to slide the
equipment out of the rack for servicing and to open the front door on the TS03 DECmagtape Transport.
2.1.2

Power Requirements

The TMA11-M DECmagtape System can be operated from a nominal 115 or 230 Vac, 50/60 Hz power source. Line
voltage should be maintained to within 10 percent of the nominal value and the frequency should not vary more
than 3 Hz. Ensure that primary power is compatible with the H720 power supply.
2.1.3

Environmental Requirements

The operating environment should have cool, well filtered, humidified air, a temperature range of 15° to 27° C, and
relative humidity of 40 to 60 percent.
2.2

UNPACKING

The TMA11-M may be shipped in two different configurations: with the system installed in an equipment rack or
with each device packaged separately.

2.2.1 Cabinet Unpackihg Instructions
To unpack the cabinet, proceed as follows:

Remove outer shipping container.
NOTE

The container may be either heavy corrugated cardboard or
plywood. In either case, remove all metal straps first, then
remove any fasteners and cleats securing the container to the
skid. If applicable, remove wood framing and supports from
around the cabinet perimeter.
2.

Remove the polyethylene cover from the cabinet.

Unbolt cabinet(s) from the shipping skid. The bolts are located on the lower supporting side rails, and
are exposed by opening the access door(s). Remove the bolts.

Raise the leveling feet above the level of the roll-around casters.

Part 1
5.

Use wood blocks and planks to form a ramp from the skid to the floor and carefully roll the cabinet

onto the floor.

Roll the system to the proper location for installation.

"SWINGING

DOOR

R.H. OR L.H.

SWINGING MOUNTING
FRAME DOOR R.H OR L.H.

;\Zf<'

/;9
74

\\\\AN

\\\
\

/7
i/

PANEL \\.

'
CABLE

ACCESS e

—y

'\7\
i

/ |

1l
21 /e

-—

(54.87 cm)

TSO3 EXTENDED

FROM CABINET

19"

(48.26 cm)

LEVELER
4 PLACES

(4) CASTERS

% hw

RADIUS 2 13/3,

(76.2cm)
-

//l

)

PORTS

]

FAN

)

2
7

| ~—-

(122.47¢m)

SWIVEL

" REMOVABLE

/ END PANEL

CASTER

(46.35¢m)

END

\‘\

REMOVABLE

187

e e e

CABINET 717¢(182.28cm) high
(floor line to cabinet top)

1-3092

Figure 2-1

Space and Service Clearance

2-2

Part I

2.2.2

Device Unpacking Instructions

Before unpacking the equipment, check the shipping list to ensure that the correct number of packages have been
received. Then carefully remove each device from its shipping carton. Note that the side mounts are already attached
to the TSO3 transport(s) and the mounting hardware is packed in a bag in each shipping carton.
2.3

INSPECTION

After removing the equipment from its container(s), inspect it and report any damage to the responsible shipper and
the local DEC Sales Office. Inspect as follows:
1.

Inspect all switches, indicators, and panels for damage.

Remove equipment covers where necessary and inspect for loose or broken modules, blower or fan
damage, cable damage, and loose nuts, bolts, screws, etc.

Inspect wiring side of logic panels for bent pins, broken wires, loose external components, and foreign
material.

Check TSO03 transport(s) for any foreign material that may have lodged in the tension arm, reel hubs,
and other moving parts.

5.
2.4

Check power supply for proper seating of fuses and power connectors.

INSTALLATION

2.4.1

Cabinet Installation

If the equipment is already mounted in the‘ cabinet, proceed as follows:

Lower the leveling feet sd that the cabinet 1s resting on the fler, not on the roll-around casters.

Use a spirit level to level the cabinet; ensure that all leveling feet are firmly on the floor.

Remove the shipping screws which secure the equipment to the cabinet.

4 :Plug»the H72O power supply ac power cord into a receptacle having the correct voltage and frequency.
2.4.2

Device Installation

The equipment should be mounted in a 19 in. by 20 in. equipment bay. Figure 2-2 shows a recommended cabinet
layout. The equipment should be mounted from the top down.
2.4.2.1

TSO03 Mounting Instructions — To mount the TSO03, proceed as follows.
NOTE

If two TSO03 transports (master and slave) are to be installed,

the slave (the unit without the M8920 adapter module) is
installed at the uppermost position.

Remove the outer portions of the guides from the TSO3 chassis by actuating the slide releases and mount

the guides to the cabinet in the 19th hole from the top of the cabinet using the eight screws provided.
Ensure that the guides are level and parallel to each other.

2-3

Part I

"MOUNT GUIDES IN
‘
19th HOLE FROM THE TO
OF CABINET

TSO3

{3~ 34th HOLE

SLAVE

MOUNT GUIDES IN

MASTER

[

MOUNT

H3~" a9th HOLE
TMA11

MOUNT IN
3~ 69th HOLE

H720
SUPPLY
1]

POWER

113090

Figure 2-2

Cabinet Installation

Lift the TSO3 up and slide it carefully into the guides until the slide releases lock.

Carefully lift the slide releases and push the transpbrtfully into the cabinet.

If asecond TSO3 transport is to be installed, repeat steps 1 through 3 above, but mount the guides in the
34th hole.

2.4.2.2

TMALI11 Controller Mounting Instructions — Using the hardware provided, mount the TMA11

at the 49th hole position.

in the cabinet

2.4.2.3 H720 Power Supply Mounting Instructions — Using the hardware provided, mount the H720 pdwer supply
in the cabinet at the 69th hole position.

2.4.3

1/O Cable Connections

To install the I/O cables, proceed as follows (Figure 2-3).

Install one end of the BC11A cable assembly into slot 03 of the TMAI1 backpanel and install the other
end into the M8920 adapter board edge connectors.

2.
3.

Install 7010570 master/slave cables betWeen the M892O adapter board connéctors J1-J6 and the TS03

master and slave transport connectors as listed in Table 2-1 and illustrated in Figure 2-3.

Install one end of the remaining BC11A cable assembly into slot 01 of the TMA11 backpanel and install
the other into the PDP-11 Unibus.

Install either a Unibus terminator module or a second BC11A cable assembly into slot 02 of the TMA11
backpanel.

Part 1
TSO3

MASTER

TSO03 SLAVE (TS03-S)

(TSO3-M)

TRANSPORT (REAR VIEW)

TRANSPORT (REAR VIEW)
J2 WRITE

Ji CONTROL

—

J2 WRITE

J1 CONTROL

/; J3 READ

EO
@

J3 READ
00 ®

)
S

J5) J %)

Lmsszo

BACK

TMA11

SLOTS

r[fi:::fi l rl

'
B

J| L1
i

2|3

PANEL

4 «—28

CHA

UNIBUS

CABLE

(MODULE

SIDE VIEW)

29 30

BC11A

UNIBUS
CABLE

11-3082

Figure 2-3

1/O Cable Connection Diagram

Table 2-1

BCO0O8A-10 Cable Connections

2.4.4

From

" To

M8920 Adapter Board

TS03 Master

Connector

TSO03 Slave
|

Connector

Power Connections

To make power connections, proceed as follows:
1.

Install the power harness (7009742) between the H720 power supply and the TMA11l power end
assembly panel in accordance with color coding listed in Table 2-2 (Figure 2-4).

Install the power harness (70-10832) between the H720 power supply and the M8920 adapter module.

Part [
TSO03 MASTER (TSO3 -M)

TSO3 SLAVE (TS03-S)

TRANSPORT (REAR VIEW)

—

M8920

E@@Q
|

TMA1! POWER
ASSEMBLY PANEL

oo Lo

- |

+SV

SWITCHED AC P

POWER HARNESS
(70-10832)

+ 5V

S5V

ADAPTER

‘ACI(O

LTC
ey

‘

\\/

‘

POWER HARNESS

(7009742)

H720 POWER SUPPLY

AC LO

PRIMARY
AC POWER

=@3
11-3083

Figure 24

Power Connection Diagram

Table 2-2
Power Harness Color Coding

DC Voltage/Signal
+SV

Wire Color
Red

Gnd

Black

-15V

Blue

DC LO

Violet

AC LO

Yellow

Plug the TSO3 master and slave transport ac power cords into the H720 power supply switched
receptacles.

Plug the H720 power supply power cord into the site’s primary ac power outlet having the proper ac
voltage and frequency. Check the label on H720 power supply for power requirements.

Using tie wraps, néatly dress all cables and harnesses. Leave service loops so TS03 drives can be extended
from the cabinet and the M8920 adapter can be swung down on its hinges.

Part 1

CHAPTER
3

SYSTEM OPERATING INSTRUCTIONS

3.1

SCOPE

This chapter covers operation of the TMA11-M, including a description of controls and indicators and all operating
procedures.
3.2

CONTROLS AND INDICATORS

Figure 3-1 describes the controls and indiéators. |
3.3
3.3.1

OPERATING PROCEDURES
Tape Threading

To thread the tape on the transport, proceed as follows:

Raise the latch of the quick-release hub and place the tape file reel to be used on the supply hub (Figure
3-2) with the write enable ring side next to the transport deck.

Hold the reel flush against the hub flange and secure it by pressing the hub latch down.

Thread the tape along the path as shown in the threading diagram (Figure 3-2).

Holding the end of the tape with a finger, wrap a few turns counterclockwise around the takeup hub.

3.3.2 Tape Loading
Pressing the LOAD pushbutton energlzes the reel servos and initiates a load sequence. Tape advances to the load

point marker and stops. If for some reason the load point marker is already past the sensor (as, for example, in

restoring power after
a shutdown), tape will continue to move. Under these conditions, press LOAD and then
REWIND and the tape will rewind to the load point. Once pressed, the LOAD switch is illuminated and is inactive
until power has been turned off or tape is removed from the machine.

3.3.3 Plaéing Tape Unit On-Line
After the tape is properly threaded and has been loaded and brought
to the load point, press the ON LINE

pushbutton and check that the ON LINE indicator illuminates. (The REWIND pushbutton is disabled when the tape

unit is on-line.) On-line status enables the tape unit to be remotely selected and to perform all normal operations
under remote control.

3-1

Part 1

dilgli tal
WS
x!

UNIT SELECT Plug — One of two plugs can be inserted,
~designating unit as O or 1.
UNIT
SELECT

NOTE

In a single drive system, the drive is always

designated as drive 0. In a dual drive system,
WRITE

either drive can be designated as drive
0.

WRITE ENABLE Indicator
— Illuminated whenever a reel

LINE

LOAD

REWIND

ON LINE Pushbutton/Indicator — A momentary pushbutton, which functions as alternate action. When first

activated, the tape unit is placed in an on-line condition;

when the tape unit is on-line, it can be remotely selected
and will be ready if tape is loaded to or past the load point.
When

activated

again

takes

the

unit

off-line.

The

indicator is illuminated in the on-line condition. The load

with a write enable ring is mounted on the supply hub.

function must be performed before the unit will go on-line.

LOAD Pushbutton/Indicator

—

The momentary push-

button activates the reel servos (tensions tape) and starts
the load sequence. The indicator is illuminated when the

- reel servos are activated and tape is tensioned.
POWER

REWIND Pushbutton/Indicator — The momentary pushbutton activates a rewind operation. This control is enabled

OFF

only when tape is tensioned and the unit is off-line. The
indicator is illuminated during either a local or a remote

rewind operation.

POWER Switch — The ON/OFF switch applies ac power to
11-3045

Figure 3-1

the tape transport.

Controls and Indicators

3-2

Part I

SUPPLY REEL

TAKEUP HUB

11-3060

Figure 3-2

3.3.4

Tape Threading Diagram

Tape Unloading and Rewind

Provision is made in the TSO03 transport for rewinding a tape to the load point under remote control. However, this
operation may also be performed manually. Proceed as follows.

If the ON LINE indicator is illuminated, press the ON LINE pushbutton. Check that the indicator
extinguishes when pressure is removed.

Press the REWIND pushbutton. The tape will now rewind to the load point marker.

After the tape has been positioned at the load point under remote or local control, press the REWIND
pushbutton to rewind the tape past the load point to the physical beginning of the tape.
|

- NOTE

The rewind sequence cannot be stopped until the tape has
rewound either to the load point or until tension is lost at the
physical beginning of the tape.

3-3

Part I

3.3.5

Power Shutdown

A tape transport should not be turned off when tape is loaded and is past the load point marker. The TS03 transport
is designed to prevent physical damage to the tape in the event of power failure, and to minimize operator error
which could destroy recorded data. In the event of power failure during tape unit operation, manually wind the tape

forward several feet before restoring power. When power has been restored, press the LOAD pushbutton, then the
REWIND pushbutton. This will rewind the tape to the load point. If desired, the tape can then be advanced to the

data block nearest the point at which the power failure occurred by initiating the appropriate control commands.

CAUTION

In dual drive systems, when one driveis on—lme and running,

do not turn power off at the unused drive, i.e., do not set the
TS03 POWER ON/OFF switch to OFF. To do so can resultin
data errors on the drive thatis running.

Part

'CHAPTER 4

CUSTOMER EQUIPMENT
CARE AND OPERATION
4.1

SCOPE

The information contained in this chapter will assist the customer in carmg for hlS equipment and ensure the highest
level of performance and reliability.
4.2

REQUIREMENTS

The customer is directly responsible for:
1.

Obtaining operating supplies, including disk cartridges, disk packs and filters, magnetic tape, DECtape,

paper tape, cassettes, printer paper, printer ribbons, plotter paper, etc.

Supplying accessories, mcludmg disk storage racks, DECtape storage racks, carrymg cases for disk
cartridges and DECtape, cabinetry, tables and chairs.
NOTE
Users

Digital

obtain

the

Equipment

Corporation

equipment

may

proper operating supplies and accessories by

contactmg

Digital Equipment Corporation
DEC Supplies Order Processing
146 Main Street

Maynard, Massachusetts 01754
Phone: (617)897-5111, Ext. 5218, 5907

Boston Area: (617)890-0330
TWX: 710-347-0212
Cable: Digital Mayn

Telex: 94-8457

Maintaining the required logs and repbrt files consistently and accurately.

Making the necessary documentation available in a loéation convenient to the system.
Keeping the exterior of the system and the surrounding area clean.

Turning off the tel‘etypewriter and/or line printer when these devices are_:‘not in use.
Performing the specific equipment care operations described for the various devices at the suggested

frequencies, or more often if usage and environment warrant.
Ensuring that ac plugs are securely plugged in each time equipment care operations are performed.

Part I

4.3 CARE OF MAGNETIC TAPE
1.

Do not expose magnetic tape to excessive heat or dust. Most tape read errors are caused by dust or dirt

on the read head; it is imperative that the tape be kept clean.

Always store tape reels inside containers when not in use; keep the empty containers tightly closed to
keep out dust and dirt.

Never touch the portron of tape between the BOT and EOT markers; oil from fingers attracts dust and

dirt.

Never use a contaminated reel of tape; this will spread dirt to clean tape reels, and could have an adverse

'—

effect on tape transport reliability.

Always handle tape reels by the hub hole; squeezing the reel flanges could lead to tape edge damage in
winding or unwinding tapes.

Do not smoke near the tape transport or storage area; tobacco smoke and ash are especially damaging to
tapes.

Do not place magnetic tape near any line printer or other device that produces papér dust.

Do not place magnetrc tape on top of the tape transport or in any other location where it might be
affected by hot air.

4.4

CARE OF TS03 TAPE TRANSPORT

4.4.1

General

Digital Equipment Corporation tapé transports are highly reliable precision instruments which will provide years of
trouble-free performance when properly maintained. A planned program of routine inspection and maintenance is
essential for optimum performance and reliability.

4.4.2

Preventive Maintenance

To ensure continuing trouble-free operation, a preventive maintenance schedule should be kept. Only a few items are

involved, but they are very important to proper tape transport operation. The frequency of performance will vary
somewhat with the environment and degree of use of the transport so a rigid schedule applying to all machines is

difficult to define. The recommended periods apply to units in constant operation in ordinary environments. They
should be modified if experience shows other periods are more suitable.
Before performing any cleaning operation (Table 4-1), remove the supply reel and store it properly. All items in the

- tape path must be cleaned on a per-shift basis. In cleaning, it is important to be thorough yet gentle and to avoid
certain dangerous practices. It should be remembered that the tape cleaner is a strong cleaning agent and should not
come in contact with painted surfaces or plastic.

CAUTION

Do not use:

acetone or lacquer thinner; aerosol spray cans;

rubbing alcohol; excessive cleaner.

Be extremely careful not

to allow the cleaner to penetrate ball bearings, tension rollers,
and motors.

4-2

Part I

4.4.3

Materials Required

DECmagtape system and magtape cleaning kit

Lint-free wipers

Table 4-1
Customer Equipment Care Operations
Device: TS03 DECmagtape Transport
Freq

Once

Operation

Clean tape path according to th/e-'following procedure. (Time required = 5 min.)

per Shift

|
a.

Remove tape from transport.

Using head cleaner and lint-free cloth, clean the following (Figure 4-1):
Head and head shield

Load point/end-of-tape sensor
Missing tape sensor

Both tape guides
Tape cleaner

Tape tension roller (not shown)
Capstan (not shown)
Using a clean, dry, lint-free cloth or wipe, once again go over each
surface listed above to dry and remove any residue.
NOTE
Do not use any cloth or wipe that has come.in

contact with the tape path as it is probably
contaminated.

Using
a clean, lint-free cloth or wipe, dust the inside and outside of

the plexiglass door. If dirt and dust have accumulated, a mild soap
and water solution or antistatic cleaner may be used.

Ensure that

the door is dry before returning the tape transport to service.

4-3

Part I

LOAD

POINT/
OF TAPE
SENSOR

END

TAPE CLEANER

MISSING TAPE

SENSOR

- HEAD COVER REMOVED FOR CLARITY

11-3051

Figure 4-1

Opening Head Shield

Part 1

CHAPTER 5
SYSTEM MAINTENANCE

5.1

SCOPE

The chapter provides a complete description of TMA11-M preventive and corrective maintenance procedures.
5.2

MAINTENANCE PHILOSOPHY

The TMAI11-M DECmagtape System is highly reliable and will provide years of trouble-free performance when
properly

maintained.

planned

program

of routine inspection

and maintenance is essential

for

optimum

performance and reliability.

The preventive maintenance required on each unit differs in accordance with its design. The TMA11 Controller,
M8920 adapter, and H720 power supply are total solid state units with no moving parts; therefore, no preventive

maintenance is required on these units. The TS03 transport, however, requires daily customer care consisting of head
and tape path cleaning (Chapter 4). Otherwise, the transport requires very few adjustments and these should not be
performed unless problems are encountered in transport operation. See Table 5-3 for the recommended preventive
maintenance procedure.

Corrective

maintenance consists

of troubleshooting at the system level using system diagnostics and visual

observations to localize the failure to a particular unit, whether it be the TMA11 Controller, the M8920 adapter, the
TSO3 transport, or the H720 power supply. Once the faulty unit is determined, unit level troubleshooting will be

performed using unit functional block diagrams, engineering flow diagrams, timing diagrams, and detail logic

diagrams to localize the failure to an electrical module or mechanical part.
NOTE
In the case of the TSO3 transport, troubleshooting tables are

provided

(see

Tables

5-5

and 5-6) listing the symptoms,

possible causes, indications, and recommended actions.
Once the faulty module or mechanical part is located, it should be replaced. If the faulty part is a module, it should

be returned to the depot for repair; if a mechanical part fails, it should be replaced and repaired only if the cost
warrants it.

5.3

TEST EQUIPMENT

Test equipment required to maintain the TMA11-M falls into two categories: standard test equipment and special
test equipment.

5.3.1

Standard Test Equipment

Maintenance procedures for the TMA11-M require the standard test equipment and diagnostic programs listed in

Table 5-1, in addition to standard hand tools, cleaners, test cables, and probes.

Part 1
Table 5-1

Standard Test Equipment Required
Equipment

Multimeter

Oscilloscope
X10 Probes (2)

Diagnostics (MAINDECS)
5.3.2

Manufacturer

Designation

Triplett or Simpson

Model 630NA or 260

Tektronix

Type 453 or equivalent

Tektronix

P6008

Digital

See Paragraph 5.9.1

Special Test Equipment

The special test equipment and tools required are listed in Table 5-2.
Table 5-2

- Special Test Equipment and Tools

5.3.3

Equipment

Manufacturer

Designation

Test Panel

Digital

General Tape Kit (Paragraph 5.3.3)

Digital

Tape Path Tool

Digital

29-21904

Transport Module Extender

Digital

29-21925

29-21922
|

General Tape Kit

The kit consists of:

Item

Part No.

Skew tape (7 in. reel)
Head cleaner

29-19224
|

Capstan cleaner

Magna-’See® (also renew solution)

—

29-16871

Magnifying glass

29-20273

Reflective tape marker

90-91777

Write ring

—

Lint-free cloth (Kimwipes)
Scotch tape
5.4

PREVENTIVE MAINTENANCE

At 6-month intervals, it is advisable to peak-up and check the TSO3 operating pararheters. This is done to ensure that
progressive degradation will not cause customer outage. The PM procedures (Table 5-3) should be performed in the
sequence listed for maximum efficiency and to reduce the interaction of adjustments.

®Magna—See is a registered trademark of Columbia Broadcasting System, Inc., Danbury, Conn.

5-2

Part [

Table §-3

TSO03 Preventive Maintenance Procedure

Device

TSO03 DECmagtape Transport

Freq

Sheet

__1of 7

Operation
1.

Clean the reel hubs according to the following procedure (time required = 5 min):
a.

Remove O-ring from the hub.

Clean with a mild solvent. Ensure that there is no residue from the solvent.

Lubricate the O-ring with Dow Corning 4 compound or equivalent silicone grease. Wipe off as thoroughly as
possible, leaving a thin film.

Replace the O-ring on the hub.

Align the tape path according to the following procedure (time required = 10 min):
NOTE
For proper transport operation, the items in the tape path must

be accurately aligned. Tapes in the area of the head are not
e

)

shimmed or adjusted. The tension roller guides must be set to

two criteria: they must be aligned to the tape guides and they
must have their axes at right angles to the tape. These two
steps are necessary to ensure that the tape passes over the

head correctly.
e

Turn transport power off.

Remove the head cover.

Remove both tape guides (keep each assembly together) (Figure 5-1).

LOAD POINT/
END OF TAPE

SENSOR

\‘

TAPE CLEANER

MISSING
SENSOR

TAPE

HEAD COVER REMOVED FOR CLARITY

Figure 5-1

Opening Head Shield

5-3

11-3051

Part I
Table 5-3 (Cont)
TSO03 Preventive Maintenance Procedure

TS03 DECmagtape Transport

Device

Sheet

_20f 7

Operation

Freq
d.

Remove the operator control panel.

Mount the tape path alignment tool on the deck per Figure 5-2.

NOTE

The screws need only be finger-tight.

Figure 5-2

Use of Alignment Tool

Pull each tape tension arm into the notch provided on the ends of the tape path alignment

tool. Check that

the roller guide is parallel to the tool and that the reference edge of the roller guide (outside

against the outer edge of the tape path alignment tool. If the roller guides do not require

to step 3; otherwise, proceed to step g.

edge) fits snugly

adjustment, skip

Loosely clamp the roller guide in the tape path alignment tool (Figure 5-2).

Loosen the roller guide split clamp screw (item C in Figure 5-3) and remove the roller shaft from the

tension arm. Do not loosen the adjustment lockscrew (item A, Figure 5-3).

5-4

Part 1

Table 5-3 (Cont)
TS03 Preventive Maintenance Procedure

|
Device

TS03 DECmagtape Transport

Sheet

Operation

Freq

3of7

ROLLER GUIDE
(®

TAPE TENSION ARM

ADJUSTMENT

LOCKSCREW

REFERENCE

EDGE

—

ROLLER GUIDE
CLAMP SCREW

)
DJUSTMENT

NUT & WASHER
(D)
11-3054

Figure 5-3 Roller Guide Adjustmvent
S

The shaft end is threaded to allow use of a nut for fine adjustment. The thread does not enter the clamp area.
Place several No. 10 flat washers over the threaded end and install a 10-32 nut as shown in Figure 5-3.

jk.

_—

Push the shaft so that the roller is too far forward. Tighten the nut lightly.
Tighten the adjustment nut until the reference edge of the roller guide just touches the tape path

alignment tool.

Parallelism can now be set by looséning the adjustment lockscrew (item A, Figure 5-3) and retightening
after the adjustment is made.

NOTE
o

Ensure that the reference edge of the roller guide is still set
per step k.

Remove the adjustment nut and washer (item D, Figure 5-3).

Check the magpot (Figure 5-4) according to the following procedure (timé required = 5 min):
a.

Release the left tape tension arm from the clamp on the tape path alignment tool.

Place a short strip of magnetic tape on the head to disable the tape broken sensor.

Remount the operat‘or control panel, power up the transport, and press ,thg.-z LOAD switch.

With the tape tension arm relaxed (pulled to the left), the supply reel should be turning
counterclockwise.

5-5

Part |

Table 5-3 (Cont)
TS03 Preventive Maintenance Procedure

Device

TS03 DECmagtape Transport

Freq

Sheet

_4of 7

Operation

MOUNTING SCREW (2)

CONNECTOR

r—-—

MOUNTING SCREW (2)
TRANSFORMER SECTION
pam—

ROTOR SETSCREW
MAGPOT COVER

TYPE 4218 MAGPOT
PRINTED CIRCUIT BOARD

—_—

7 —.\/
/

~ \‘

—

TN\

S e

BUFFER ARM

—

| REEL DRIVE PULLEY
Figure 54

Magpot Position Sensor Assembly

Pull the arm into the V provided in the tape path alignment tool. The motor should now be null (no
rotation). If the reel rotates in either direction, go to step i.

—

Release the right tape tension arm from the clamp on the tape path alignment tool.

With the tape tension arm relaxed (pulled to the left), the takeup reel should be turning
counterclockwise.

Pull the tension arm back into the V provided in the tape path alignment tool. The reel motor should

be null. If the reel motor rotates in either direction, go to step i; otherwise, proceed to step k.

—

NOTE

The following procedure is for the reel motors that continue
to rotate while in the V-groove of the tape path alignment
tool.

5-6

11-3061

Part 1

Table 5-3 (Cont)
TSO03 Preventive Maintenance Procedure
Device

TS03 DECmagtape Transport

Freq

Sheet

Sof7

Operation :
i.

Hold the tape tension arm in the V provided in the tape path alignment tool. Loosen the set screw holding

the armature on the pivot shaft. Rotate the armature until the reel stops rotating or has minimum rotation.

Press the armature firmly against the transformer section and tighten the rotor set screw.

Turn off the transport.

Remove the tape path alignment tool.

Restore the tape guides and head cover.

Adjust the photosensor in accordance with the following pro_cedure (time requirred =5 min):

Connect a dc voltmeter between test pomts E and F of the sensor ampllfler drlverin slot 11
(Flgure 5-5).

)

NOTE

If a scope is to be used, it must not be grounded. The probe
may now be used on a test point and the ground lead for the
probe on the other test point.

b.
5.

Adjust the sensor adjustment potentiometer (R_l 6) forO V.

Check the eapstan per the following procedure (time required = 5 min):
a.

Turn transport power off.

Mount the servo preamplifier in slot 13 on the extender board.

Connect a scope to test point A of the servo preamplifier.

NOTE
Test point A is accessible only while the module is on the

extender.

Turn transport power on and load a scratch tape.

Adjust potentiometer R56 for O V.

NOTE

—

The capstan must remain stable and not rotate at all.
f.

Turn transport power off. Remove the extender board and reinsert the servo preamplifier in slot 13.

5-7

Part I

Table 5-3 (Cont)
TS03 Preventive Maintenance Procedure

Device

TS03 DECmagtape Transport

Sheet

60f7

Operation |

Freq

CONTROL

|<¢——READ

‘ INDICATES TAPE CHANNEL NUMBER

FOR

13
12

4306-002
3844-001

3645-002

3841-001

10
9

—

——>|@— WRITE —8

3843-001
3842-001

SERVO PREAMPLIFIER
SENSOR AMPLIFIER/DRIVER

RAMP GENERATOR

PUSHBUTTON CONTROL
INTERFACE CONTROL

Figure 5-5

4845-001
4179-004

TIMING DELAY
P CHANNEL/CLIPPING

4178-004

QUAD READ AMPLIFIER

3848-001

4178-004
3860-001

3849-001

Plug-In Module and Test Point Locations

——

5-8

TRACK

7
6
4
3

CONTROL TERMINATOR

QUAD
DATA

READ AMPLIFIER
TERMINATOR

4 CHANNEL HEAD DRIVER

CHANNEL HEAD

DRIVER

Part |

Table 5-3 (Cont)

TSO03 Preventive Maintenance Procedure
Device

__TS03 DECmagtape Transport

Sheet

Operation

Freq
6.

Using the instructions included in Appendices A, B, C, and D, run the TMA11

Instruction Test

(MAINDEC-11-DZTMA-E), the TS03 Supplemental Test (MAINDEC-11-DZTSF-A), the TSO3
Drive Function Timer (MAINDEC-11-DZTSE-A), and the TMA11 Multidrive Data Reliability
Exerciser (MAINDEC-11-DZTMH-A) (time required = 25 min).

-L

pospnnsnn

pree——

Return the tape subsystem to operational status for customer use (time required = 5 min).

5-9

_70of 7

Part [
5.5

TS03 DECmagtape TRANSPORT ADJUSTMENTS

Figure 5-6 illustrates the recommended sequence for performmg all adjustments on the TSO03 DECmagtape
Transport. References are made to paragraphs describing the adjustments.

UNKNOWN MACHINE |
(PARTS ASSUMED
'

GOOD)

SUPPLIES

Figure 5-13

“TAPE SPEED
‘

ADJUST

- Paragraph 5.6.3.1

ADJUST

Paragraph 5.6.3.2

\
TAPE PATH

READ LEVEL

Paragraphs 5.7, 5.8°

Paragraph 5.6.3.4

REEL SERVO SETUP

READ SKEW

(MAGPOT ADJUST)

ADJUST

Paragraph 5.5.2

Paragraph 5.6.3.5

PHOTOSENSOR

WRITE SKEW

ADJUST

CHECK/ADJUST

Paragraph 5.5.1

Paragraph 5.6.3.5

CAPSTAN SERVO
ZERO ADJUST
Paragraph 5.5.3

11-3084

Figure 5-6

Adjustment Sequence

5.10

Part 1
5.5.1

Photosensor Adjustment (Figure 5-5)

Photosensor elements used to detect the load point and EOT are cadmium sulfide photoresistive cells. Their

characteristics sometimes vary with time and light history. An adjustment is provided to ensure their proper
operation. Need for adjustment will be indicated if the load point or EOT is not observed by the sensors. To adjust:
1.

Verify that both lamps at the photosensor are illuminated.

Connect a dc voltmeter from test point E to test point F on the sensor amplifier/driver module.
NOTE

These points are both off ground. If a scope is used
instead of a voltmeter, it must be isolated from ground

or the two inputs added with one channel inverted.
3.

Adjust potentiometer R16 so that there is 0 V between test points E and F.

5.5.2 Magpot Adjustment (Figure 5-5)
Magpots that provide position feedback to the reel servos should not require adjustment since only passive
components and their geometry determine their zero settings. If one is moved by severe damage to the machine or if
replacement is necessary, refer to the detailed circuit description in Chapter 3 of Part Il for adjustment details.

5.5.3

Capstan Zero Adjustment (Figure 5-5)

The capstan must not move, even slightly, when at zero speed setting. A zero adjustment is provided on the servo
preamplifier to remove effects of component tolerances. To determine if adjustment is required, observe the

following:
1.

If the capstan rotates slowly when it should be standing still, grasp the capstan with tape loaded and turn

first clockwise and then counterclockwise. The capstan will show a reluctance to turn. If turned gently, a

small dead zone can be detected. This dead zone should be approximately the same for both directions
of motion. If adjustment is required, connect a volt-ohmmeter or scope probe to test point A of the
servo preamplifier module.

5.6

Extend the Type 4306 Servo Preamplifier module.

Load tape to the load point.

Rotate zero adjustment potentiometer R56 to bring the measured voltage to zero.

TEST PANEL USE

The test panel is packaged in a box and supplied as Model 9900 for use with TSO3 transports (Figure 5-7). The
controls and indicators, together with brief descriptions of their purpose, are shown in Figure 5-8. Note that the box
allows tape to be moved in either direction at normal or fast speed. Motion is interlocked to prevent running off
reels at either end. Additionally, the 9900 allows writing an all-1s pattern on the tape and provides indicators for

skew, data, load point, and EOT.

The test panel is intended to be used in checking the TS03 transport when offline or when completely isolated from
the operating system. The controls provided are useful under these circumstances but under normal operation they

would be confusing and invite possible operator error.

5-11

Part [

Figure 5-7

5.6.1

Test Panel Installation

Operations

The test panel becomes operational only in test mode, selected by pressing the alternate action TEST MODE
pushbutton. For the TEST MODE button to be operational, the machine must be off-line and STOP must be

depressed. Test mode is terminated by either pressing the alternate action TEST MODE button or pressing the ON
LINE pushbutton.

A characteristic of transport electronics is that when LOAD is pressed, the machine feeds forward to the load point.

If tape is already wound on the machine and the load point marker has been passed, the search will continue to the
end-of-tape unless REWIND is pressed. This characteristic is sometimes troublesome when servicing the machine.

Under these circumstances pressing TEST MODE will terminate search and induce an ON TAPE status in the control
electronics. If ON LINE is subsequently pressed, the ON TAPE status is retained. This feature can be adapted to
allow power turn-off while tape is loaded.

When using tape motion pushbuttons, the STOP button should be pressed between changes in speed or direction. No

harm will result if this is not done, but on occasion switch bounce will cause the command to be unrecognized and
the last motion signaled will be retained.
5.6.2

5.6.2.1

Indicators

SKEW Indicator — This is an LED indicator which flashes if skew is being encountered. Logic in the data

section detects skew to two different criteria and lights the indicator. The skew gate in the NRZI read electronics is
normally open for 50 percent of one character time. If pulses fall outside the skew gate, they trigger the indicator. In
test mode, the skew gate is narrowed to 5/32 of a character time. An all-1s pattern on a properly adjusted machine

should fall inside the shortened gate. A tape with random data suffers from pulse crowding effects and will not, in

general, fall inside the gate. Thus in test mode the SKEW light indicator is valid for an all-1s data pattern only.

5-12

Part I
NOTE

Tape

transport

must

off-line

and

STOP

pushbutton

depressed before test panel can become functional.
TEST MODE pushbutton and indicator.

A momentary pushbutton selects

test mode and activates the test panel. When the indicator (LED) is
illuminated, the test panel is active. (Tape unit must be off-line and the
STOP pushbutton depressed before the test panel will function.)

O TEST MODE

O WRITE TEST

WRITE TEST pushbutton and indicator.
programs

written on all

A momentary pushbutton which

channels

to facilitate write skew

adjustment. WRITE TEST remains active in FORWARD RUN mode only.

LOAD

POINT
O
EOT

SToP
FORWARD
RUN

sY e

(STOP pushbutton must be depressed and TEST MODE selected to

actuate this feature.) The indicator remains illuminated while the unit is in
this mode.

STOP pushbutton. An interlocked pushbutton switch that terminates all
tape motion.

RUN

SKEW

FORWARD

FAST-

FAST
REVERSE

e e

DATA

FORWARD RUN pushbutton. An interlocked pushbutton switch that
REVERSE

allows the tape unit to proceed forward at normal speed. Depressing the
STOP pushbutton or an EOT marker terminates this operation.
REVERSE RUN pushbutton.

An interlocked pushbutton switch that

allows the tape unit to run in reverse at normal speed. Deprssing the STOP

pushbutton or a load point marker terminates this operation.
FAST FORWARD pushbutton. An interlocked pushbutton switch that
allows the tape unit to run forward at fast speed. Depressing the STOP

pushbutton or an EOT marker terminates this operation.

TEST

FAST REVERSE pushbutton. An interlocked pushbutton switch that
allows the tape unit to run in reverse at fast speed. Depressing the STOP
pushbutton or a load point marker terminates this operation.
MODEL

9900

SKEW TEST point. The SKEW TEST point measures total character skew
11-3064

of all nine tracks by means of a sample-and-hold circuit. The calibration of
this test point is 10 us of character skew per 1 V of output. To measure

skew, set the scope for 0.5 V/div vertical and 100 ms/div horizontal and

e
IHEdE NN
I-BIIII

observe skew waveform as shown.

.".

EEEE

Figure 5-8

Model 9900 Test Panel

5-13

Dynamic Character Skew

Part
5.6.2.2

DATA Indicator — The DATA indicator is illuminated when the tape being read has data written on it at a

level sufficient to activate the read electronics. It blinks when reading gapped data.
5.6.2.3

LOAD POINT Indicator — This LED lights when the load point is sensed.

5.6.2.4 EOT Indicator — EOT is indicated when the end-of-tape marker is sensed in the forward direction and
remains true until it is passed in the reverse direction.
NOTE

All indicators operate whether or not TEST MODE is selected.
5.6.3

Utilization Procedures

5.6.3.1

Speed Adjustment — Normal speed of the unit is determined by the setting of R14 on the ramp generator

card. This control is set at the factory and does not normally require adjustment. To check speed:
1.

Mount a skew master tape on the machine as in the read skew adjustment (Paragraph 5.6.3.5).

Observe the waveform at one preamplifier test point.

Set the time for one complete sine wave cycle (two bits) at 200 us by adjusting R14. Note that the
waveform will not be entirely stationary on the scope due to small, rapid speed variations. These should
be visually averaged.

4.
5.6.3.2

If a speed adjustment was made, check the read preamplifier gain settings (Paragraph 5.6.3.4). |
Ramp Time Adjustment — Tape is brought up to speed at constant acceleration. To control tape velocity, a

ramp voltage is generated by the ramp generator which rises linearly to the required running speed and falls linearly
to zero at stop (Figure 5-9). Ramp time should accelerate the tape to running speed in 0.19 in. of travel. This timing

is of utmost importance in gap generation on tape and must be accurately set. Ramp time is 15 ms at 25 in./sec and

varies inversely with speed. Thus, at 12.5 in./sec
it is 30 ms and at 37.5 in./sec it is 10 ms. This voltage may
be

—

Q-

observed at test point A of the ramp generator card.

roo.

’

START

RAMP

vT=l'5—2-S-5—-MSEVC

STOP

oane

11-3057

":Figure~5-9 Ramp Timef Adjustment

The test panel may be used to make ramp time measurements by starting and stopping the machine via the

FORWARD RUN and REVERSE RUN pushbuttons. This is difficult, however, because the buttons must be pushed
as the scope is observed. Measurement under rapid start/stop commands fed to the synchronous forward input is

much easier. In reverse operation, timing is the same as in forward but the polarity is reversed — the ramp is
negative-going. To adjust ramp time:

Establish rapid start/stop motion.

Observe waveforms at ramp generator test point A. Synchronize on run command; be sure time is long
enough to produce a flat area between ramps.

5-14

Part I
3.

Set the start rise time at the proper value using R3 on the ramp generator module.

Set the stop fall time using R4 on the ramp generator module.

5.6.3.3 Rewind Speed — Rewind speed is not adjustable. It is determined by fixed values on the ramp generator
card.

5.6.3.4

Read Level Adjustment — This adjustment sets the gain of the read preamplifiers to the correct level. Too

much gain will introduce noise and too little will aggravate dropouts.

Load a reel of scratch tape on the transport with the write enable ring in place.

Press TEST MODE.

Press WRITE TEST and FORWARD RUN.

Observe waveforms at the test point for each channel on the read preamplifier.

The signal observed should appear as an approximate sine wave. Noise introduced by crosstalk from the
write head will be present but the waveform should not be badly distorted by this.

Measure peak-to-peak amplitude and set for 9 £+0.5 V using the channel gain control on the read

preamplifier. Repeat for each channel. Note that the read level is about 10 percent higher when the
machine is operating in the read-after-write mode than when in the read mode. This effect is caused by
small, unavoidable magnetic remanence in the write head and the erase head. Skew master tapes should
not be used as amplitude reference for this reason.

5.6.3.5

Skew Adjustment — Skew is one of the most important parameters in reading NRZI data. Since, in a

read-after-write head, data is read with one gap and written with a second gap, read and write skew are, in general,
different and must be compensated separately. The machine is deskewed only when both are properly set. In TSO3
transports, the read gap is deskewed mechanically while digitally controlled delays are used to deskew the write gap.

Read Skew Adjustment — In deskewing the read gap, the head is mechanically tilted to have its gap at an exact right

angle to the tape. This is accomplished using a skew master tape (Paragraph 5.3.3).
a.

Load askew master tape on the transport. Be sure the write enable ring is removed.

Press TEST MODE.

Press FORWARD RUN.

Observe the SKEW indicator and adjust the skew-adjustment screw on the head mounting plate (Figure
5-10) until the indicator does not come on.

For greater precision, a scope probe may be connected to the TEST terminal on the test panel. At this point, the

pattern will be a grouping of nine pulses as each channel “reports in.” The optimum skew setting is the one at which
these pulses occupy the minimum spread.

If the test panel is not available, this signal is available at pin 8 of the test panel connector on the pushbutton control
module.

5-15

Part I
SKEW

ADJUSTMENT
SCREW

HEAD

COVER

SKEW

ADJUSTMENT

ACCESS HOLE

11-3049

Figure 5-10

Head Skew Adjustment

Write Skew Adjustment — TSO03 transports feature a unique digital deskewing arrangement for deskewing the write
head. Since write-read skew is a function of head geometry and does not change, write deskewing delays are
determined at the factory and each head has a deskewing chart showing the appropriate write amplifier deskew
switch settings for that head. All channels are referenced to the P channel.

If for some reason it is necessary to deskew the write head in the field, the procedure is as follows:
1.

Proceed as in a read level adjustment (Paragraph 5.6.3.4).

Connect dual channel scope channel 1 to the P channel test point on the read preamplifier. Set alternate
sweep and trigger channel 1 internal.

Connect scope channel 2 to the test point for tape channel 5 and observe the pattern (Figure 5-11). Set
the sweep to display 1/2 sine wave cycle.

Observe separation
of peaks displayed. Note that because of small variations in speed and skew, the
pattern will not be entirely stationary.

Set the skew switch for channel 5 for minimum peak separation.
6.
5.7

Repeat for each of the remaining seven channels.

TAPE PATH ALIGNMENT

For proper transport operation, the items in the tape path must be accurately aligned. Tape guides are fixed in
location and are not shimmed or adjusted in any way. The tension roller guides must be set to two criteria:
1.

Roller guides must be aligned with tape guides.

Roller guides must have their axes at an exact right angle to the tape.

The more convenient and accurate technique for alignment uses a special alignment tool, Part No. 154-0035-001,
shown in Figure 5-2.

5-16

PERIOD

T=100

:
ustc

SPEED(IPS)

11-3056

Figure 5-11 " Skew Adjustment Waveforms
5.7.1

Alignment Procedure
1.

Loosen the roller guide clamp screw (both rollers) (item Cin Figure 5-3).

Loosen the roller guide adjustment lockscrew (both rollers) (item A in Figure 5-3).

Remove the tape guides by removing the mounting screws (keep together as sets).
Remove the head cover and control panel.

Using the guide mounting screws, mount the alignment tool. Tighten the mounting screws finger-tight.

Clamp fhe roller guides to the alignment tool with the guide portion approximately centered in Vee.
Tighten the adjustment lockscrews and snug roller guide clamp screws. This sets the angularity of the

roller guide axes.

Loosen the tool clamp screws one at a time.

Holding the roller guide against Vee, press the roller guide toward the panel until the outer edge of its
guide area reference edge touches the tool’s outer surface. This sets the roller guide height.

10.

Tighten the roller guide clamp screw.

11.

Remove the tape path alignment tool and replace the tape guides.

517

Part 1
With roller guides aligned as described above, only one critical item remains in the tape path — the drive capstan. Its

surface must lie accurately at a right angle to the tape surface. The capstan motor can be tilted slightly by the action
of two set screws in the front panel. To determine if adjustment is required, run the tape forward and reverse about

1 ft each way and observe whether the tape maintains the same position on the capstan for each direction. If the
tape moves more than 1/32 in., adjustment is required. To adjust (Figure 5-12):
1.

Loosen slightly outboard motor mounting screws 1 and IV, and loosen inboard screws II and III.

Run tape forward and reverse, observing motion on the capstan.

Tighten left-hand set screw A slightly; If motion decreases, adjust for minimum motion.

If motion increases, loosen set screw A, tighten inboard mounting screws II and III snugly, loosen
outboard mounting screws I and IV, and repeat using right-hand set screw B.

When minimum motion has been found, tighten all four mounting screws.

If set screw A has been used, tighten mounting screws I and IV first, then II and IIL. If set screw B has
been used, tighten mounting screws Il and 11l first, then I and IV.

Observe tape motion through the tape guides. When properly aligned, tape will have a slight tendency to
follow the spring loaded (inside) guide edge when it is depressed manually. If tape runs hard against
either guide, surface alignment is not correct.

Observe and adjust skew using a skew master tape. (See Skew Adjustment, Paragraph 5.6.3. 5) Skew
should be about the same forward and reverse.

O !

111 ©

0O v

|
Figure 5-12

5.7.2

11-3055

Capstan Parallelism Adjustment

Tape Path Alignment Without Use of Alignment Tool

It is possible though somewhat tedious to adjust the tape path without using alignment tools. Most difficult is setting
squareness of the roller guides. A procedure is:

Remove the roller guide to be aligned and replace it with a length (4 in. approximately) of 0.1875 in.
stainless steel ground stock. Clamp in place.

Loosen the roller guide lockscrew slightly so that the moderate pressure rod can be rotated.

5-18

Part I
3.

Thread tape over the rod.

While holding the rod, run tape forward. Tilt the rod back and forth until a position is found at which
tape runs with equal tension on the inside and outside and tape enters the tape guides correctly, or in the

case of the takeup roller guides, winds correctly on the center of the takeup reel.

5.8

When the position is found, tighten the lockscrew securely.

Replace the roller guide and adjust height (Paragraph 5.10.1).

Check alignment as described above and revise if required.

HEAD FACE SHIELD ADJUSTMENT

A shield is located over the magnetic head surface to reduce write-read crosstalk. Its spacing, determined by a spring
stop, is important. The spring stop is adjustable as follows:

Loosen the stop screw with tape removed from the machine.

Insert three thicknesses of tape (0.006 in.) between the shield surface and the top surface of the head.
Do not use feeler gauges, since they may scratch the head surface.

5.9

Press the shield against the tape firmly and tighten the stop screw.

Remove the tape pieces by lifting the shield.

CORRECTIVE MAINTENANCE

Corrective maintenance information is provided to guide and aid the maintenance technician in isolating and
repairing faults. The information consists of five troubleshooting aids: the TMA11-M diagnostics, the corrective
action flow diagram, the maintenance block diagram, TS03 transport troubleshooting hints, and TSO3 transport
troubleshooting tables.

59.1

TMA11-M Diagnostics

Diagnostics, consisting of a paper tape and documentation, are provided with each system. The documentation

includes instructions on loading, running, and 1nterpretmg diagnostic printouts. The diagnostics provided with the
TMA11-M are listed below:

TMA11 Instruction Test

5.9.2

MAINDEC-11-DZTMA-E-D/PB

TMA11 Data Reliability

MAINDEC-11-DZTMB-B-D/PB

TMA11 Multidrive Data Reliability Exerciser

MAINDEC-11-DZTMH-A-D/PB

TSO03 Drive Function Timer

MAINDEC-11-DZTSE-A-D/PB

TS03 Supplemental Instruction Test

MAINDEC-11-DZTSF-A-D/PB

TS03 Utility Driver

MAINDEC-11-DZTSG-A-D/PB

Corrective Action Flow Diagram

Figure 5-13 provides sequential procedures for troubleshooting the TMA11-M.
5.9.3

Maintenance Block Diagram

Figure 5-14 functionally separates the circuitry comprising the four major units (TMA11, M8920, TS03, and H720)
into functional blocks and depicts signal flow between those blocks within each umt it also depicts interfacing

between each unit and interfacing between the TMA11 and the Unibus.

5-19

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Figure 5-14 TMA11-M Maintenance Block Diagram

5-21

Part 1

5.9.4

TMAI11 Controller Troubleshooting Hints

If problems are encountered with the TMA11 50 us clock, it may need adjustment. To adjust, proceed as follows:

5.9.5

Scope pin A31H2 on the TMA11 backpanel.

Set the scope for sync positive slope, internal trigger, and 10 us/cm sweep rate.

Adjust the bottom potentiometer on the M307 module in slot A31 for 50 us wide positive pulse.

TSO03 Transport Troubleshooting Hints

Table 54 suggests possible causes when problems are encountered with the transport.
5.9.6

TSO03 Transport Troubleshooting Tables

Tables 5-5 and 5-6 list transport symptoms versus possible causes, indications, and corrective actions.
5.9.7

Troubleshooting Procedure

When problems are encountered in system operation, the technician should

Discuss the symptoms with operation personnel to determine the exact nature of the failure.

Refer to the corrective action flow diagram (Figure 5-13) and proceed as directed.
Table 5-4
TS03 DECmagtape Transport Troubleshooting Hints
Problem

General

Hints

Problems in the TSO3 transport can usually be classified as either mechanical or
electrical but often the classification may be confusing because a basically
mechanical problem can cause what appears to be an electronic malfunction and

vice versa. In any case the problem should be thoroughly analyzed before
adjustments are made.

Electronic troubleshooting is greatly facilitated by the modular construction — a

new card may be substituted and the effect observed. Most difficult, of course,
are subtle problems and those of an intermittent nature.

Visualizing

solution

(Magna-See)

useful

under

certain

conditions

for

troubleshooting. At high densities the data cannot be satisfactorily resolved but
such problems as a dead track, improper gap length, etc., can be isolated rapidly
by its use.

If a tape has had visualizing solution applied to it, do not reuse that portion of

the tape as it will contaminate the head. Cut the visualized portion off and
discard.

To use visualizing solution, shake the can thoroughly, remove top, and pass
portion to be visualized through the solution. Snap the tape vigorously to
remove excess solution and let dry. Iron powder will be left in magnetized areas.

This can be picked off using Scotch tape and applied to a sheet of paper for a
permanent record.

5-22

Part [
”

Table 5-4 (Cont)

TS03 DECmagtape Transport Troubleshooting Hints
Hints

Problem

High Error Rate

Usually the more difficult problems involve a higher than permissible error rate
for which there is no obvious reason. If operating properly with good tape, the

transport should make very few errors in writing and, if rewriting is included in
the program, it should make no read errors.

Useful clues are:

In what mode (read or write) are many errors occurring?

At what point in the block does the error occur?

What is the nature of the error: VRC, CRC, LRC?

Are the errors pattern related?

Do errors occur only on certain sets of commands?

The first thing to be done is to inspect the head and other items in the tape path
for dirt accumulations. Be sure everything is clean. Check the tape being used

and try a new reel if tape is doubtful. Check interface connections for broken
wires or bad contacts. Table 5-5 is a troubleshooting chart concerned with high
error rate.

Compatibility

" The TSO3 transport accepts and produces tapes conforming to the ANSI
standards. Occasionally compatibility problems can arise:
1.

Tapes written by and acceptable to the TSO3 transport are not

acceptable to another transport.

Foreign tapes cannot be read by the TSO3 transport but its own
tapes can be.

Three items may be involved: skew, speed, ramp times. These should be
checked as described in the adjustment procedures.
Other Malfunctions

Normal

troubleshooting

procedures

are

involved

finding

malfunctions. The first things to check are the supply voltages:

electronic
|

+24 V nominal unregulated will normally be about £26 V under light load.
+10V+05V
+5V+0.25V

5-23

Part 1

Table 5-4 (Cont)
TS03 DECmagtape Transport Troubleshooting Hints
Problem

Other Malfunctions

Hints

Convenient test points for measuring supply voltages are:

(Cont)

+24 V — Case of Q9 (MJ802) on heat sink
~24 V — Case of Q10 (MJ4502) on heat sink
+10 V — Sensor amplifier/driver TPA

-10 V — Sensor amplifier/driver TPB
+5 V — Sensor amplifier/driver TPC

Voltages are measured to chassis (ground).
NOTE

Turn power off when removing or inserting cards.
If the voltages are not correct, the trouble is in the power supply or the

malfunction is loading the supply excessively. Pulling cards from their sockets
can help isolate an overloaded condition. The power supply is short-circuit

protected on the regulated voltages. A short circuit on +24 V should blow the
fuse.

Assuming the voltages are correct, Table 5-6 should help in isolating

malfunctions.

5.10 PARTS REPLACEMENT
In most instances, assembly methods for parts replacement are obvious. Electronic parts are nearly all on plug-in
modules. Items in the transport tape path may require machine realignment if replaced. If only one item in the

transport tape path is replaced at a time, the complete alignment procedure may usually be avoided. Examples of
transport parts replacement follow.

5.10.1

Supply Tension Arm Roller Guide

If an alignment tool is available, follow the procedure given in tape path alignment (Paragraph 5.7). If not available,
the following procedure will generally suffice.

Loosen the roller guide split clamp screw (C) and remove the roller shaft from the tension arm. Do not
loosen the adjustment lockscrew (A).

Insert a new roller guide shaft and clamp lightly by tightening the split clamp screw (C).

The shaft end is threaded to allow use of a nut for fine adjustment. The thread does not enter the clamp
area. Place several No. 10 flat washers over the threaded end and install a 10-32 nut as shown in Figure
5-3.

Push the shaft so that the roller is too far forward. Tighten the nut up lightly.

Load tape on the transport and feed it forward.

Tighten the nut pulling the shaft back in the clamp until the tape runs just inside the outer guide surface
with the spring-loaded side manually pushed in.

Tighten the split clamp screw.

Remove the adjusting nut and washers.
5-24

yE9S

| Part I

5-25

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5-27

Part I

Takeup Roller Guide

5.10.2

The takeup roller guide is adjusted in the same way as the supply roller except for steps 5 and 6, which are:
5.

Load tape and cause forward and reverse tape motion — about 1 ft each.

Tighten the adjusting nut until tape feeds to the center of the takeup reel. Then apply fine adjustment
until tape moves only slightly or not at all on the capstan surface on reversal.

5.10.3

Tension Arm Replacement

Tension arms are replaced by removing roller guides and disassembling. Do not attempt to remove the pin holding
the arm to its shaft; replacement assemblies are supplied pinned. Reassemble the arm mechanism.

It will be necessary, if tension arms are replaced, to perform the complete tape path alignment procedure (Paragraph
5.7).
Reel Motor or Belt Replacement

5.10.4

Unplug the motor and remove the motor and mounting plate.

Remove the motor from mounting plate. Replace with a new motor.

Hook the drive belt on the motor pulley and replace the screws holding the motor mounting plate to the
deck assembly.

Hold tension against the belt and tighten the mounting screws.

Check belt tension by squeezing between thumb and forefinger. The belt should deflect about 1/4 in. If
not, loosen the screws and move the motor.
Plug in the motor.
5.10.5

Capstan Motor Replacement

Remove the capstan lockscrew.

Remove the capstan. The capstan fits a taper on the motor shaft so it may be readily removed once
loosened. It may require considerable force to break loose, however. Pullers are available for this use but
a screwdriver properly protected to prevent marring may be used to pry against the panel.
Remove the four capstan motor mounting screws. Unplug and remove the motor.

Install a new motor. Note if a red dot is present on the motor housing. If a dot is present, the motor
should be oriented to place the dot as near as possible to the outside end of the deck.
5.

5.10.6

Adjust by procedure given under tape path alignment, Paragraph 5.7.
Supply Hub Replacement

After long use, components in the quick-locking mechanism may become worn to the point that adjustment of
locking pressure cannot securely hold the tape reel. It is not necessary to replace the hub in its entirety; a hub repair
kit is included.

5-28

Part I

Repair kits consist of a replacement lock lever, thrust washer, and O ring. (See Replaceable Parts List, Part III,
To install:
Chapter 4.)
1.

Remove the lock adjusting nut.

Pull the lock lever out.

3. | Rerfiove the thrust washer.
4.

Replace the thrust washer.

Instafl a new lock lever and replace the adjusting nut.

Install a new O ring.

Adjust the hub for proper holding force. Verify using several different reels. Refer to Figure 5-15 for
more detailed adjustment procedures.
HUB

DECK PANEL
0 RING

BEARING CARRIER

HUB

AL dld
A1
A
i

HUB /

REIFINETE1B1

dl,

}

IR I T TE T I

ADJUSTING NUT

\ I

Attt thhtutaltwhwn

DRIVE

PULLEY

HEIGHT SHIMS

BELLEVILLE
PRELOAD SPRINGS

HUB

<«— .305(REF)
11-3052

NOTES:

Loosen hub adjustment nut.

Open hub, install tape reel.

3.
4.

Close hub. Tighten hub adjusting nut until O ring presses firmly against reel.
Check for slippage under torque by holding hub or drive pulley. Reel should not slip on hub.

Open and close several times and recheck for slippage.

Try several reels, checking for slippage.

Figure 5-15

Reel Hub Adjustment

5-29

Fart |
5.10.7

Magnetic Head Replacement

Replacement heads are supplied as complete assemblies together with mounting plate and face shield. A write
deskewing chart is supplied with each head.
1.

Unplug the head connectors.
Remove the head mounting screw and remove the head, passing connectors through the panel hole
provided.

Be sure the adjusting screw on the replacement head is almost completely unscrewed.
Mount a new head with the mounting screw fairly loose. Screw in adjusting screw until point protrudes
enough to engage its conical locating hole. Tighten the mounting screw.

Plug in the head.

Deskew the read head as described in the deskew adjustment procedure (Paragraph 5.6.3.5).
Set the deskewing switches on the write amplifiers to correspond to the chart supplied.
Place the chart over the old chart to record switch settings.

5.10.8

Photosensor Replacement
1.

Remove the photosensor assembly by unplugging and removing the mounting screws. Since it will not
pass through the hole provided, the connector must be removed by cutting the cable. Retain the
connector.

Replacement sensors are provided with connector pins crimped to wires but with no connector shell
installed.

Replace the assembly, passing the wires through the hole provided. Replace the screws.

Snap pins into the connector shell in the same color sequence as in the shell just removed; plug in the
assembly.
5.

5.10.9

Adjust as described in adjustment procedure.

Magpot Replacement (Figure 5-4)
1.

Unplug the magpot assembly from its cable.

Remove the rotor by loosening the set screw.
Remove the screws holding the magpot PC board and remove the assembly.
Install a replacement unit.

Consult the magpot circuit description (Part III, Chapter 3) for realignment procedures.

5-30

Part [

5.10.10

Tape Cleaner Replacement

Remove the circular snap-in plug cover.

Remove the mounting screw and tape cleaner.

Mount a new cleaner assembly with the mounting screw finger-tight.

Adjust the cleaner surface so that it just touches the tape and is parallel to the tape surface.

Tighten the mounting screw and install a snap-in plug cover.

5-31

I
Part

APPENDIX A

TMA11l INSTRUCTION TEST

(MAINDEC-11-DZTMA-E)
ABSTRACT

THE TM11 INSTRUCT]ON TEST CONTAINS A SERIJES OF BASIC

CHECK

TM11

REGISTERS

FOR

PROPER

QPERATION

NQTF

IESTS TWA?

INVOLVING

DATA TRANSFERS,

TAPE MOTION, ALL TAPE MOTION FUNCTIONS,

MEMQRY,

yHMILE

EXTENDED

AND MANUAL INTERVENTION TESTS OF THE TUL@ TRANSPORY SWITcHES,

REWUIREMENTS

EQUIPMENT
“DFml11

WITH

TM11

2,2

STURAGE

242,1

PRUGRAM STQRAGE
THE

RQJTINE

CONTROL

REQUIRES

UNIYT

AND

TUL1®

TAPE

UNIT,

MEMORY,

LUADINGS PROCEDYRE
METHOD

N+

PRUCEDJRE
'

»
v

FOR

NORMAL

BINARY

TAPES

SHOULD

FOLLOWED,

ABSOLVUTE LOADER MUST BE IN MEMORY,
PLACE BINARy TAPE IN READER,
LOAD ADDRESS #7500 (# DETERMINED BY LOCATION OF LUADER)
PRESS "START" (PRQGRAM WILL LOAD),

STARTING PRQCEDURE
CONTROW

SWITCH

SETTINGS

STARTING AT SA 2¢@ ALL SW]TCHES SHOULD BE DOWN UR ZERU,
STARTING

ADDRESS

210
PRUGRAM
LOAD

PLACE
SE)

LOAD

AND/OR

PROGKAM

ONE

SWITCH

QPERATQR

[NTO

ACTION

MEMORY,

Tyl@ TAPE yNIT,
REGISTER

ON«LINE,

STARTING

LOAD POINT

ADDRESS,

PRESS START,
PROGRAM WILL

TYPE

"SET

IF APPROPRIATE SET SW@
THE PROGRAM W]LL BEGIN

SW@si

AND THEN
TESTING,

A-1

7 CHANNEL",

PRESS

CONTINUE,

(BOT),

yNIT @ SELECT

1
Part
UPERATING

PROCEDLURE

UPERATIQ0'AL

SWITCH

SETTINGS

WITH ALL SWITCHES DOWN THE PROGRAM WILL PRINT OUT ON ERRORG ANS

CONTINJE

IN TEST,

(BELL

WILL

RING

SWITCH

SETTINGS

SW15

,,,

HALT

SWl4e

SW1¥

..,

SCQPE

,,,

INHIBIT

SW12

,,,

INHIBIT

SUB-~TEST

SWlg

,,,

INHIBIT

MANUAL

SWe

,,,

TEST

MANUAL

COMPLETION

PASS,,

ARE!

INTERVENTION

ON ERROR
LOOP

PRINTOUYT,

INTERATION,

INTERVENTION

CHANNEL TAPE

TEST

UNIT,

TEST

THE

TUY10

TRANSFORT

AS DIRECTED RY MESSAGES PRINTED ON THE

TELETYPE,
SUBROUTINE

ABSTRACTS

SCUPE

THIS SJBROUTINE
SECTIQN,

RECORDS

TWE

SUB=TEST

HEING ENTERED,
START
-

IJF

CALL

IS PLACED BETWEEN EACH SUB=TEST
THE

STARTING

ADDRESS

EACH

REQUESTING,

IF A SCOPE LOOP 1S REQUESTED,
THAT

THE

SCOPE

LOOP

IN THE

SUBR~TEST

INSTRUCTION
AS

TH1S

SJBROUTINE

SUSTEST

AND

THE

CALL

PRINTS

CONTENTS

THE

ADDRESS

ALL

THE

TM11

THAT

T WILL JUMP Y0 THE

TAGS THE
REGISTERS,

FAILING

t
ParI
ERXQRS

ERKQR

PRINTOUT

FORMAT

CWlIH SW13=2 (OR nOWN) THg FOLLOWING PRINTQUT WILL APPEAR 0N AN pRRORI

“C

STATUS COMAND BYTE

DATA B

CRC CAL

XXXXXX XXXXXX XXXXXX

ADDKESS OF

STaTuUs

CONTENTS
OF STATUS REGISTER AT TIME OF ERROR

4YTE

CONTENTS OF BYTE COUNTER AY TIME OF EHWROR

JATA B
READ L

ERRQR OCCURED

CONTENTS OF CURRENT MEMORY ADDRESS AT TIME OF FRROR

=
=

TEMP

XXXX¥X XXXXXX

CONTENTS OF COMMAN® REGISTER AT TIME UF ERROR

COMAND

WHMERE

XXXXXX

TEMP

XXXXXX

TEST

XXUXXX

READ L

WXXXXX

CONTENTS QF DATA BUFFER AY TIME OF ERROR
CONTENTS OF READ LINES AT TIME OF ERROR

- CONTENTS QF ADDRESS "TEMP® USED BY SOME TESTS

CRC CAk =

CRC CHARACTER CALCULATED (USEFUL ONLY Fon 8RCc TEST)

NOTE THAT NOT ALL OF THE INFORMATION PRINTED 1S INTENDED Tg BE
JSEFUL FOR EVERY

TYPL OF

ERROR,

THIS

IS SIMPLY A STANDARD ERROR

THE OPERATQR MUST REFER TO THt PROGRAM
REFPORT FOR ALL ERRORS,
THE ERRQOR FOR A DESCRIPTION OF THWE
OF
ADDREbs
THE
LISTINS AT
|7 IS THEN UP TO HIM YO DETERMINE WH]EH
CAUSE JF THE ERROR,
OF THE INFORMATION IS USEFUL,
ERRQR

RECOVERY

WllH SW1sz1 OR UP THE PROGRAM W]LL HALT ON AN ERRQUR,
CONTINJE

SW]TCH

TQ RESTART

TgST,

A-3.

DEPRESS
|

Part!

RESTRICTIONS
STARTING

RESTRICYION

ngoRg STARTING PROGKAM THE OPERATOR MUST MAXE CERTAIN THAT THE TU1®
TRANSPIRT WAS DRIVE v SELECTED, 1S "ON~LINE", AND AT "L0AD POINT",
UPERATIOVAL

RESTRICTIONS

MANUAL [MTERVENTION TEST MUST BE PERFORMED ON EACH PASS THRU
THE PRIGRAM UNLESS LNHlaxlto WITH SWig=1 (OR UP).

MISGELLANEOUS
EXECUTION

TIME*

W]lTH MANUAL INTERVENTJON TEST INHIBITED IT TAKES } MINUTE

FOX ONE PASS TWRU PRUGRAM, MANUAL INTERVENTION TEST 1S
OPERATOR DEPENDENT BUT SHOULD TAKE APPROXIMATELY 2 MINUTES

9,0

PRUGKAM

10,¢

LI3TING

DLSCR;PTION

1
Part

APPENDIX B

TS03 SUPPLEMENTAL
INSTRUCTION

TEST

(MAINDEC-11-DZTSF-A)
ABSTRACT

THIS

PROGRAM

THE

TM11/TU12

INTENDED

INSTRUCTION

COMPLETE

TESTING

THE

PROGRAM

CONSISTS

USED

TEST

ADDITION

(MAINDEC-11-DZTMA-C)

THE

TS@23 MAGTAPE SYSTEM,
ONLY FOUR (4) TESTS WHICH

CHECk THE TMA-11 FFATURES
RYTE STARTING ADDRFSS AND

OF DATA TRANSFER AT 0DD
OPERATION INCOMPLETE TIME

oUT,

REAUTREMENTS
R

oy,

AnY

CONSOLE TTY

PUP=-11
NF

TAPE

LZADING

PROCFESSOR

CORE

TMA-11

CONTROLLER

TAPE

TRANSPORTS

PROCEDURE
G

STARTING
-

R ey

WY o

FROCENUR

JSF STANDARD PROCENURE FOR LOANING BINARY PAPER TAFE

THERF ARE TWO (2) STARTING AGDRESSES THAT MAY BE USEN;
2P7(R)
A,

AND

217(8).

228(8)1 STARTING

THIS

ADDRESS

WILL

CAUSE

PROGRAM

IDENTIFICATICN HEADER TO BE PRINTEC, A
REQUEST FOR UNIBUS ANDRESS AND VECTOR AND
REQUEST

THFE
MAY

218(8):

FOR

ENTRY

THE

DEFAULT SELECTION
BE CHANGED TO ANY

TYPING

THE

SELECTED

PRINTED

STARTING
UNIT

SELECT

DESTIREDN

STATING,

THIS

NUMBER

OF UNIT Z2ERQ
NUMBER (2-7)

NUMRER

unIT

ANn

NOT

AND

ADDRESS

REQUEST

UNIT

THE

B-1

CARKIAGE

UNIT

NOT

TRANSPQORT

(2) IS DISPLAYED,
OR UNCHANGED By

AVAILAELE,

WILL
IS

(TAPE

MESSAGE

SELECT

AND

RETURN,
A

FRINT

INTENDEC

SELECT),

THE
A

wlLL

REQUESTY

HEADER

RESTART

REPEATED,

THE

ADDRESS

QNLY.

I
Fart

TN g

SETTING

SWITCH

CONSOLE
W

AR M

e
~~~~~~~~~~~~~~

ALL

SWITCHES

EXCEPT

IS DNANE WITH ALL
ALL SWITCHES
ARE
SW15:

SW14:

1=HALT

FRROR

1=LOOP

FRROR

2=CONTINUE

3-9

ARE

USED

AND

SWITCHES SET T0
DYNAMIC AND MAY

THE

NORMAL,

ZER0O (2),
BE CHANGED

DEFAULT,

ANY

TIME,

ALL

TESTS

RUN

(SCOPE)

P=CONTINUE

SW13:

1=z INHIBIT FRROR TIME QUT

2=PRINT

ALL

1=INHIRIT

SW123

ERROKS

ITERATION

@=1TERATE FACH TEST ITS
1=CONTINUOUS CYCLE
B=HALT AT FND OF PASS

SWil:

SW1@:

1=HALT

FEND

ASSIGNED

CURRENT

AMOUNT

TEST

2=CONTINUE

SW9-3:
SW2-7:

FRROR
O

MR,

NOT USED
SELECT IMDIVIODUAL

(1-4)##

PRINTOUTS
WP

THERE

ARE

APPEARS

|
TEST

THREE

STATUS

(3)

TYPES

ERRQR,

FRRQOR:

DATA

ERROR

ERROR,

ANY

READ,

RESULTS

PRINTOUTS

P)JSITION

WHICH

MAY

ERROR,

WRITE,

SPACE

SOME

BAD

STATUS

CPERATION

(BIT

OR UNEXPECTEN RUS ADDRESS, OR
dYTE COUNT, WILL BE PRINTEC,
B,

C.,

DATA

ERROR:

POSITION

ANY

ERRQR:

READ

OPERATION

WHICH

DATA

WILL

PRINTEN,.

ANY

SPACE

REWIND

UNEXPECTED

STATUS

WHICH

MTC)H,

INCORRECT

RESULTS

UNEXPECTED

OPERATION

WILL

RESULTING

PRINTED,

#
FXAMPLESe

TEST1:

WRITr

WRITE

FROM

oDD

FRRQR

MTS:

17141

MTC:

1s12¢4

MTBRCy

MTCA:

ABR3

BYTE

THIS

TEST

PARITY

SHOWS
UNIT

THAT
AT

WHILE

882

ERROR

QCCURED.

ZERO

SHOULD

ADDRESS

EXPECTED.

6223

B-2

THE

EXECUTING

HPI,

ANC

BYTE

THE

WRITE
COUNT

CURRENT

1IN

[
Part

T4HE

TEST

FOLLOWING

2¢

RpEAD

NATA ERROR
CNT 7
GC: 20270007
R

CNt

EXAMPLE

QDn

BYTE

P19202¢0

SHOWS

TYPICAL

DATA

ERROR,

THIS PRINT SHOWS THAT A SINGLE BIT WAS
PICKED UP IN ROTH CHARACTER NUMBER ZERO
(Z) AND CHARACTER NUMBER THKHREE (3).

G:
R

02020711
21200711

THE

TEST43

REWIND

FOLLOWING

EXAMPLE

SHOWS

ERROR

DURING

A REWIND OPERATION,

0PI 700 LONG
ERROR: NO BoT

OPERATION
o

WM wma gy TS ewe ww

THE PRNCERURES FOR OPERATING THIS PRNGRAM ARE QUITE
SIMPLE AND RECQUIRE ONLY A FEW STEPSH
1.
2,
3,

LOAD ADDRESS 2@ OR 219
SET SWICHES FOR DESIRFD
PRESS START

TEST

SEQUENCE

CONSOLE SWITCHFS ARE DYNAMIC AND MAy BE CHANGEC

ALL

THE NORMAL OPERATING SEQUENCE

AT AMY TIME.,

IS ALL SWITCHES

THE PROGRAM WILL TAKE APPROXIMATELY 1,25 MINUTES
DOWN (?),
TS RN} HOWEVER, IF ITERATIONS ARE INHIBITED (SWiiszl), THE
PROGRAM WILL RUN
1S

NATED RY

THAT

IN ABOUT

PRINTOUT

,75 MINUTES,

STATING END

THE END OF PASS

PASS

AND THWE

NUMBER

PASS,

SINGILE

TEST

WHEN SW@-3

SELECTION:

ARE

SET

(SWE-SHW3)

ZERQ

(2),

THE

SCHEDULAR

WILL

FXECUTE ALL TESTS (1-4) IN SEQUENCE AS A SINGLE PASS,
1F Svw¥-3 ARE SET To SOME NUMBER RETWEEN 1 AND 4,
THFN TWHAT PARTICULAR TEST WILL BFE
THE PROGRAM MAY QE STOPPED AT THE

EXECUTED CONTINUCUSLY,
ENND OF THE CURRENTY

TEST (FITHER IN SEQUENCE OR SINGLE TEST MODE) BY SETTING
YOy MAY SELECT TESY
SWITrH TEN (SW1@) TO A ONE (1),
NUMBFRS Ik ANY QROFR (UP OR DOWN) BECAUSE EACH TEST
1S

SrLF

CONTAINED,

B-3

|
Part

TEST13

FRQM

WRITE

BYTE

00D

TRANSFERREN

BYTE

FROM
BRACK

FROM

ADDRESS,

MEMORY

THE

TEST

THAT DATA MAY BE

IS TO ASSURE

THE PURROSE OF THIS TEST

TAPE

STARTING

WILL WRITE

A SIX

AN 0DD ADDRESS (WDATA+1) AND READ
INTO AN EVEHN AOUDRESS (RDATA),
NO

FROM

(é)

0DD

BYTE RECORD

THAT RECORD
STATUS ERROR

SHOULD

AND THE READ DATA SHQULD BE POSITIONED PROPERLY,

OCCUR,

THE RECORD IS SIX BYES LONG, EACH BYTE 1S ITS NUMBER (0,1,2,3,4,5)

TEST2!

BYTE

00D

READ

THE PURPOSE
OF THIS TEST
TRANSFERRED FROM TAPE TO

ADDRESS,

EXCEPT
AnD

TEST3S

QP1

THE

THE PROCEDURE

THAT

READ

THE

WRITE

PURROSE

THIS

0DO

THE SAME AS

FRQOM

TEST

ADDRESS

EVEN

IN TEST ONE

ADDRESS

(12,

(WDATA)

(RDATA+1),

8 QF MTS)

= BIT

(QP]

700 ILONG

THE

IS TO ASSURE THAT DATA MAY BE
MEMORY STARTING AT AN QDD BYTE

ASSURE

THAT

THE

0PI

TIMER

WILL SHUTDOWN THE DRIVE REFQORE TEN POINT FIVE FEET OF BLANK
TAPE

PASSED,

THE

PROCEDURE

PERFORM

WRITE

WITH

IRG, BACKSPACE, WRITE WITH JRG 32(1@) TIMES IN ORDER
ToO ERASE 1@¢.5 FEET OF TARPE,
AFTER REWIND, ISSUE A READ

COMMAND AND OPI
(17,5

FFEET

SHOULD TIME nUT BEFOQRE THE FIRST RECORD

DOWN

1S SEVEN SECONDS

TAPE,

TEN

TAPE)

(7SEC)

POINT

FIVE

FOUND.

THE

NOMINAL

VALUE

TAPE

REFLECTS

THE

FEEY

TOLERANCE FOR QPI,

TEST4:

OP1
THE

TOQ SHORT
PURROSFE

THIS

THE

TAPE

TEST

S PASSEN,

IN TEST THREE
FIRST

RECORD

(3),

MAXIMUM

= BIT 8 OF MTS)
1S

ASSURE

THAT

THE

WILL NOT SHUTDOWHN THE NRIVE RBEFQRE FOUR FEET
OF BLANK

OP]

(OP]
OF

FOQR

NR ARQUT SEVEN POINT FIVE FEET (7,5 FT)

THF PROCEDURE

HOWEVER 0Pl

FOQUNN

FEET

OPI

(4 FT)

TIMER

1S THE SAME

1S NOT EXPECTED BEFORE

DOWN

TAPE),

THE

FOQUR FEET oF TAPE RELECTS TH<E MINIMUM TOLERANCE FOR OPI,

B-4

Part

APPENDIX C

TS03 DRIVE FUNCTION TIMER

(MAINDEC-11-DZTSE-A)

ABSTRACT

THE

TS23

DRIVE

THE TMA-11
NPERATIONS

FUNCTION

TIMER

ASSISTS

THE

TESTING

CONTROL UNIT AND TSe3 TAPE UNIT,
SELECTED
ARE EXECUTED, TIMED, AND THE TIMES ARE THEN

PRINTED (IN MILLISECONDS),
THERE IS NO LIMIT OR ERROR
TESTING FACILITIES IN THE PROGRAM, THE DECISION ON THE
VALINITY OF TIMES MEASURED MUST RE MADE BY THE OPERATOR,
FITHFR

TS23

UNITS

MAY

SELECTFD,

REAUTREMENTS

FQUIPMENT
PDP-11

WITH

TMA-11

CONTROL UNIT

STORAGE
2.2.1

PRDOGRAM

THE

AND

1 OR

TS@3

TAFE

UNITS,

STORAGFE

PROGRAM

REQUIRES

MEMORY,

LOADING PROCEDURE
METHOD

PROCFDURE FOR NORMAL BINARY TAPES SHOULD.
BE FOLLOWED
1.

ABSOLUTE

©LACE

BINARY

TAPE

|.0AD

ADDRESS

#7589

O©ORESS

STARTING

CONTROL
STARTING

LOADER

"START"

MUST

(% DETERMINED

(PROGRAM

WILL

PROCEDURE

SWITCH

MEMORY,

READER.

SETTINGS:

NONE

ADDRESS

207

C-1

LOADY,

LOCATION

OFf

LOADER).

}hfif
PROGRAM

ANDAZOR

INTO

PROGKAM

LPAD
SET
SET

QPERATOR

ACTION

MEMORY,

NESIRED TS23 TAPE UNITS ON-LINE,
SWITCH REGISTER Y0 STARTING ADDRESS,

'LCAD ADDRESS.,

PRESS START,
ENTER STARTING REGISTER A4DDRESS,
THE PRNAGRAM WILL AUTOMATICLY FINOD THE AVAILABLE
TS23 TAPE UNITS TO BE TESTED,
THE PROGRAM
WILL BEGIN TIMING FUNCTIONS,
ON COMPLETION OF ALL TESTS M"END OF TIMINGY WILL
THE PROCESSOR WILL HALT.
TO

REPEAT

TESTt

IPERATING

PRFSS

BRE

PRINTED

AND

CONTINUE.

PROCEDURE

OPERATIONAL

NONE

SWITCH

SETTINGS

FRRQRS

THE PROGRAM HAS NO INTER“AL ERQDR “ETECTION FACILITIES AND,
THEREFORE, NO ACTUAL ERROR TYPEOUTS,
THE VALIDITY OF THE
TIMES

MEASURED

MUST

DETERMINED

THE

OPERATOR,

TIVME RELATIONSHIPS
A,

"READ

6APS

C.,

SHUTDOWN®

MUST

"WRITE

EOF"TM

TIME

LIMITS AND
waewa(ALL TIMES

|
MUST

SHQULD

WRITE

FROM

SHUTNOWN

WRITEF

START

SETTLE

DOWN

QRACKSPACE
READ

BAT

HEAD

SHUTDOWN

SHUTPOWN

CARS

GAP

LAP

GAP

"WRITE

UNIT

XIRG",

RANGE

MAX

MIN

SAME

593.8

537,29

15,6

35,8

17.6

13,6

37.5

33,9

33.6

30,4

33,8

69 (9

74,8

62,0

7.2

6,4

33,9

7.7

7.8

SHOUL D=B3>756>5>4>3,

SHUTDOWN".

(+0R~ 5.0).

565, 0

DELAY

ERASE

"WRITE

3z2=1

SLIGMTLY

UNIT

WRITFEF

PRINTOUT FORMAT EXAMPLE
ARF IN MILLISECONDS)ssaue

FUNCTION

WRITF

B8>7>6>5>4>3,

3=2=1

5,2
58

(+0R~

7.2

6,4

5,0)

"
"

Ha, 2

53,6

GAP

67,1

CAP

9.4

CAP

108,77

GAP

117 .4

WRITF

START

39,9

'«:RITP

XIRG

37.5

33‘531

\54908

31518

240,4

222,4

60,7

368.8

328,02

649

7.2

6,4

83,9

75,9

READ

FROM

WRI1TFE
FOR

SPACE
ONF

ROT

239,02

FOQOF

385,

EOF

TIME

SHUTDOWN

INCH

NDATA

TME

81,0

C-2

420,08

362,70

PartI

RESTRICTIOQNS

"STARTING RESTRICTIONS

AT LEAST ONE TS@3 TAPE UNIT MUST BE "ON~LINE",

ALSO MAKE CERTAIN THAT EACH TS@3 THAT
HAS A UNIGUE UNIT NUMBER SELECTED,

1S "ON-LINE"

OPERATING RESTRICTIONS
TMA-11 INSTRUCTION TEST MUST RUN WITHOUTY
T2 OPERATE THIS PROGRAM,
-

ERRORS

BEFORE

ATTEMPTING

MISCELLANEOUS

FXECUTION
NCT

TIME

APPLICABLE

PROGRAM

DESCRIPTION

WRITE FROM BOT DELAY
WRITE

FROM

BOT

DELAY

IS THE

TIME NECESSARY

TO MOVE

THE BEGINNING

OF TAPE (BOT) MARKFR APPROXIMATELY
6 INCHES PAST THE WRITE HEAD,
THE FIRST RECORD OM TAPE MUST BE WRITTEN AT. LEAST 3. INCHES AWAY
FROM THE BOT MARKER,
|
PROCFDURE

3,
¢,
D.
£,

MEASURE

TSg¢3

1S NOT

AT BOT

1S REWOUND TO BOT,

INITéALIZE 3YTE RECORD COUNTER AND CURRENT MEMORY 'ADDRESS

1SSUE WRITE FUNCTION, 802 BPI, SET "GO",
MONITOR CURRENT MEMORY ADDRESS REGISTER TO DETERMINE WHEN
°ND BYTE
THE

TIME

IS OUTPUT,

FRQM

APPROXIMATELY

9,2

TIME:

wRITF

"GO"

UNTIL

FQUAL

2ND

BYTE

"WRITE FROM

OUTPUT

BOT

DELAY",

QHUTDOWN

NRITF SHUTDOWN [S THE AMOUNT OF TIME NECESSARY TO CONTINUE
MOVING TAPE AFTER A RECORD IS WRITTEN SO THAT THE PROPER
INTERRECORD GAP WILL EXIST BETWEEN RECORDS,

PROCEDURE TO MEASURE TIME:

A.
R,
0.,

THE PROGRAM USFS THE SAME RECORD THAT WAS WRITTEN TO TIME
"WRITE FROM BOT DELAY"TM,
.
|
AFTER THFE LAST BYTE (BC=2), INDICATING THE END OF THE
RECORE, MONITOR "SETTLEDOWN"TM UNTIL 1T BECOMES A &,
THE

TIME

FRQM

SHUTDOWN",

»BC=0"

UNTIL
|

C-3

"SETTLEDOWN"

"WRITE

lhflf
START

WRITF

WRITE START

FULL

SPEED

PROCFOURE

SAME

IS THE TIME NECESSARY FOR TAPE TO ACCELERATE TO

AND GUARANTEE

TO MEASURE

AS "WRITE
INITIALIZE

B,
C.

FROM
BYTE

1/2

INCH

INTERRECORD

GAF,

TIME:

BOT" EXCEPT NOW WE
RECORD CQUNTER AND

ARE NOT AT EOT,
CURRENT MEMCRY ADDRESS

ISSUE WRITE FUNCTION, 807 BPI, SFET nGO",
|
MONITOR CURRENT MEMORY ADDRESS REGISTER TO DFTERHINE WHEN

PND BYTE 1S OUTPUT,
THE TIME FROM »GO" UNTIL
EQUAL TO "WRITE START"TM,

2ND BYTE

OUTPUT

APPROXIMATELY

UNTIL

SETTLEDOWN DELAY
TAPE

DOES

PERIOD

FULLY

NOT

ACTUALLY

TIME

AFTER

STOPPED,

COME

SHUTDOWN

ADDITIONAL

COMPLETE

STOP

HAS

ENDED,

ALSO,

PERIOD

TIME

SOME

AFTER

TAPE HAS
NFCESSARY FOR THE

TAPE AND WARDWARE TO "SETTLEDOWN"TM ANND BECOME STABLE,
THE
"SETTLEDOKN DELAY"TM IS THE PERIOD
OF TIME NECESSARY
FOR THE
AND

MECHANICAL

THAT

THE UNIT

R,
C.

QPERATED,

RESONANT,

MEASURE

THF

TS@3

T0O

BECOME

START/STOP,

TAPE

STABLE,

A FREQUENCY WHERE

TIMg:

THE PROGRAM USFS THE SAME RECORD THAT WAS WRITTEN TO TIME
WWRITE START"
AFTER "SETTLEDOWN®" BECOMES A 1., INDICATING THE START OF
SETYTLEDOWN, MONITOR "TU READY"TM UNTIL IT BECOMES A 1,
THE TIME FRGM "SETTLEDOWN" UNTIL "TU READYTM
IS "SETTLEDOWN",

WRITE T0 ERASE HEAD
THE PURPOSE OF THE ERASE HEAD

1S TO

INSURE THAT THE TAPE

THE SAME FLUX STATE AS THE WRITE HEANS.,
SEVERAL

1.
~

2.
u

9.5

CANNOT BE

MECHANICALLY

PROCFDURE
A,

CHARACTERISTICS

REASONS,

START/STOP

CHARACTERISTICS

WOULD BE POSSIRLE
WHEN USING
4 TAPE

TO
ON

VARY

AMONG

THIS

TAPE

LEAVE QLD DATA IN THE
MORE THAN ONE UNIT.

IS NECESSARY FOR
UNITS

AND

1IT

INTERRECDRD

GAPS

A TAPE PREVIOQUSLY USED AT ONE RECORDING DENSITY €OULD NOT
USED LATER AT ANOTHER DENSITY,
TRACK ALIGNMENT AND HEAD WIDTH VARY FROM TAPE UNIT TO
TAPE UNIT AND 1T WOULD BE PDSSIBLE FOR DATA TO BE LEFT ON
THE TRACK EDGES FROM QLD RECORDS,
|

C-4

1
Part

THE "WRITE TO ERASE HEAD" TEST
THE

WRITE

ROCPDURE
A,

HEAD

1S ERASED DURING

USED

TIME

BEEN WRITTEN FROM BOT,
"WRITE

FROM

TAPE 1S REWQUND TO BOT.

C.
D.
F.
F.
G.

A WRITE QPERATION,

TQ MEASURE T:ME.

-A'LONG RECORD HAS
WAS

INSURES THAT THE TAPE IN FRONT OF

BOT

SAME RECORD THAT

DELAY",

fiYTE RECORD COUNTER IS INITIALIZED FOR A 3 BYTE RECORD
AND CURRENT MEMORY ADDRESS REGISTER 1S INITIALIZED.
ISSUE WRITE FUNCTION, 802 BPI, SET "GO".
AWAIT CUR AT END OF CURRENT WRITE,
ISSUE A 2 BYTE READ,
TIME FROM GO UNTIL
FRASE HEAD TIMF,

‘H.

TIME

RACKSPACE

CUR

TOO SHORT,

THE

READ

ERASE HEAD

NRITE TO

INOPERATIVE,

SHUTROWN

"BACKSPACE SHUTDOWN" 1S THE LENGTH OF TIME NECESSARY TO GUARANTEE
IF A WRITE OPERATION FOLLOWS A BACKSPACE THE TAPE WiLL BE

THAT

POSITIONED

AND

ERASE

LFSS
A

B,
C.
D.
.

THAT

ALL

AND

WILL

THAN

"WRITE

DATA IS IN FRONT OF THF
ERASED: "RACKSPACE SHULTDOWN"

START" SO

BACKSPACE/REWRITE

PROCFDURE
A,

SUCH

HEADS

THAT

OPERATION

INTERRECORD

GAPS

INIT!ATED.

WILL

BYTE

INCREASE

MEASURE TIME:

INITIALIZE BYTE RECORD COUNTER AND CLRRENT MEMQORY
REGISTER,
TSSUE WRITE EOF FUNCTION, 8223 BPt, SET "go"
AFTER EOF RECORD IS WRITTEN WAIT FOR "TU READY",
SET

WRITE
MUST

RECORD

COUNTER

TOQ

BACKSPACE 1

ADDRESS

RECORD,

ISSUE BACKSRACF FUNCTION, SET "Go",
AFTER “EQOF"TM BECOMES A 1, INDICATING THE RECOGN]TION OF
THE "EOF"TM RECORD, MONITOR "SETTLEDOWN"TM UNTIL IT BECOMES
THE

TIME

FRQM

SHUTDOWN",
READ

“EOF"TM UNTIL

"SETTLEDOWN"

"BACKSPACE

SHUTDOWN

READ SHWUTDOWN IS THE

AMOUNT OF TIME NECESSARY TO CCNTINUE MOVING
TAPE AFTER A RECORD 1S READ SO THWAT THERE 1S ENOUGKH GAP FOR TAPE
TO BE FULLY ACCELERATED IF A READ IS FOLLOWED BY A BACKSPACE,
"READ SHUTDOWN" MUST ALSO BE LESS THAN "WRITE SHUTDOWN" TO
GUARANTEE THAT THE WRITE AND ERASE HEADS WILL BE PCSITIONED
SUCH THAT ALL PREVIOUS DATA IS IN FRONT OF THE HEADS AND
WILL

WRITE

172

ERASED IF

FOLLOWS

AN INCH,.

PROCEDURE

WRITE

READ

THE

MEASURE

FOLLOWS A READ,
IN ADDITION, WHEN A
INTERRECORD GAP MUST STILL BE AT LEASY

TIME:

A.
B.

RECORD RREVIOUSLY USED IN "BACKSPACE SHUTDOWN" 1S
;§é¥é$§ézg BYTE RECORD COUNTER AND CURRENT MEMORY

C.
D.

I1SSUE
AFTER

READ FUNCTION, 800
"EOF" BECOMES A 1,

RECORD, MONITOR

THE

TIME FROM

SHUTDOWN"

BPI, SET "go",
INDICATING THE

"SETTLEDOWN"

"EOF"TM

UNTIL

"SETTLEDOWN"

END

BECOMES

THE
A

“READ

READ.
ADDRESS

Part
I

GAP

CONSISTENCY

FOR
3E

PROPER OPERATION,
LEAST

THE

1/2

CHARACTERISTICS

EACH

ONE

TAPE UNIT

INTERRECORD GAPS ON

INCH,

THIS

READ ON

WILL

ANOTHER

UNIT

ARE

ALLOW

TAPE

UNIT

DIFFERENT,

TAPE MUST
DATA

WHEN

THE

ALWAYS

WRITTEN

THE

USING

START/STOP

MINIMUM

GAP SIZE OF 1/2 INCH IS GENERATEN WMEN A WRITE FOLLOWS A READ,
ALL OTHER GAPS SHOULD BE LARGER NEPENDING ON HOW THEY NERE

NRITTEM

PROCEDURE

MEASURE

TIME;:

UTILIZING DIFFERENT
THE TAPE IS REWOUND

cC.
D.
F.

F.
G.

MW,

GAP

TOTAL

NINE

RECORDS

ARE WRITTEN ON TAPE (FROM BOT)
SEQUENCES TO GENERATE THE INTERRECORD
TQ BOT,

GAPS,

INITIALIZE BYTE RECORD COUNTER AND CURRENT MEMCRY ADDRESS

1SSUE READ FUNCTION, 820 BPI1,
WAIT FOR "CU RFEADY" TO BECOMF

RESET

"GO"

MONITQOR
INPUT
THE

TIME

CcONTINUE,

CURRENT MEMORY
»
FROM

WILL REFLECT

SET "gO",
A 1, THEN REPEAT

WHEN

THE

ADDRESS

"GO"

SI1ZE

To DETERMINE

RFSET

THE

UNTIL

THE

STEP

AND

WHEN 2ND BYTE
2ND

GAP,

BYTE

INPUT

STEPS E, F ARE REPEATLD UNTIL ALL 8 GAPS ARE MEASURED.

WRITE FOLLOWED BY

WRITE

(START/STOP),

GAP 2

WRITE FOLLOWED BY A WRITE (START/STOP),

GAP

READ

GAP

WRITE~-BACKSPACE

GAP &
|

FOLLOWED

WRITE (START/STCP),

FOLLOWED

WRITE

(START/STOP),

SAME AS GAP 4 EXCEPT WRITE~BACKSPACE REPEATED 2
|

TIMES,

GAP

SAME

GAP

EXCEPT

WRITE-BACKSPACE

REPEATED

BAP

SAME

GAP
4

EXCEPT

WRITE-BACKSPACE

REPEATED

EXCEPT

WRITE~BACKSPACE REPEATED

TIMES.,

TIMES!

GAP

SAME

AS GAP

TIMES,

GAP LENGTHS SHOULD REFLECT THE FOLLON!NG’RELATIONSHIPSE
85>75>6>524>3,

322=1

(+0R-

5.0)
.

[
Part
WRITF

THIS

STAKT

REPEAT

(REFERENCE

TRIFT

9.17

9.3),

BACKWARDS

BNT DISARPEARS

FQUAL

"WRITE

WRITE

XIRG

ARITF

WITH

THE

WHEN

START"TM

"POWER

MOVING

COMPARED
TAPE.

MIVE

PAST

WoJLn

RECORD

ADD

THE

SPOT,

REPEAT

THE

WRITTEN

INCHES

TAPE

ISSUE

MONITOP

GAP

TWAT
GAP,

WOULD

ERRORS.

EACH

GAP

ISN'T,

"EACKSPACFE-REWRITE

UNTIL

SOON

SHOULD

THAT

CAUSES

AT LEAST 3 INCHS
THE PURPOSE IS TO

XIRG

TIME

FUNCTICN

CAUSED

WOWEVER

WILL

DEFECTIVE
BE

THE

WITH

LONG

AREA

SUFFICIENT

PROCEDURE

XIRG"

SEQUENCE

SUCCESSIVE
"GOOD"TM

REWRITE

TAPE

WAS

UNTIL

WOULD

REACHED,

TIME:

FROM

THE

FIRST

AND CURRENT

WITH

XIRG

FUNCTION:

MEMORY

ADDRESS

QUTPUT,

FROM

"GO"

UNIT

2ND

872

BPI,

RYTE

MEMCRY

SET
TO

IS OUTPUT

ADDRESS

"GO,

DETERMINE

WHEN

WITH

"WRITE

ROT

RECORD

FROM

THE

WASN'T

MET

THE

TIME

2ND

aYTE

PROCFDURE

WRITTEN
80T

STILL
FROM

TAPE

THE

MARKER,

DESIREABLE

WHEN

READ

SUPPOSED
TO

EVENT

THAT

READ

THIS

THE

RECORD,

FUNCTION

LEAST

CONDITION
READ

ISSUEL

UNTIL

BOT

DURING

"WRITE

FROM

THE

INPUT.

MEASURE

RECORD

START"

THAT

TIMP:

WAS

(KEFERFNCE

TAPE IS5 REWOUND
INTTIALIZE KYTE

TSSURE

MOMNT TR CURRENT

READ

WRITTEN

9,1¢)
BOT

RECORD

FUNCTION,

PND

3YTE

THE

TIME

FROM

GOY",

RECORD COUMTER
-

CURRENT

RYTE

READ

THE

ROT.

COMPLETED

TAPE

ISSUEC

WITH

INTERRECORD

8YTE

WRITE

THE TIME
X1RG",

INCHES

THE

FROM

1S NOT AT BROT

MAY

REWRITE

9.3,

I:MTERRECORD

THAT

PREVINUSLY

CLEAR"

FORWARND

MEASURED

WITHOUT

MFASURE

INTTIALIZE

OND

ONE

BAD

PROCFDURE

ERRORS

TEST

TO DETERMINE

OF AN INTERRECORD GAP
WITH THE NORMAL 3/4 INCY

NORMALLY

Foo

EXTENDED

WRITE

R,
H

"WRITE
PURPOSE

GENERATION

BOT

START®

ELIMINATE

THE

IT'S

OFF

USEN,

COUNTER

AND

CURRENT
:

882

MEMORY

BPI,

SET

AUDRESS

INPUT,
"GOTM

JUST

UaTIL

2N0
|

C-7

MEMCRY

ADDRESS

"gO",

T0O

DETERMINE

WHEN

|
BYTE

INPUT
|

"READ

FROM

1
Part
WRITF

EOF,

WRITE

AN END

FILE

MARK

MCVE 3 INCHES REFORE WRITING,
IN
TO WRITING A RECORD WITH EXTENDED
FOF

MARK

SLIGHTLY

NECESSARY

CORRESPONDS

LARGER

"WRITE XIRG",

PROCFDURE

THAN

MEASURE

BYTE

FOR

TAPE

THAT RESPECT IT IS SIMILAR
INTERRECORD GAP, HOWEVER, AN
RECORND,

THE

TIME

SHOULD
BE

‘

TIME:

TAPE UNIT 1S REWOUND TO BOT,
INITIALIZE BYTE RECOKD COUNTER AND CURRENT
ISSUE WRITE FUNCTION, 82¢ BPI, SET "GO",
WATT FOR "ClU READY"TM AND THEN "Ty READY" TO

1SSUE WRITE EOF FUNCTION, 87
WAIT FOR "CU RFADY" TO BECOMF

Rp1,
A

SET

1.,

|
|
MEMCRY ADDRESS
|

BECCME
"gO",

THE TIME FROM ©GO"TM UMTIL "cU READY" IS "WRITE EOQF",

CFOR TO EOF SPAGE TIME
FOR

EOF

SPACE

TIME

THE

TIMF

NEEDEND

T0O

MOVE

TAPE

FROM

THE

FND oF A RECORD TO AN END OF FILE MARK WRITTEN AFTER IT,
THE
PROCFDURE USED TURNS OUT TO BE A TEST OF THE WRITE AND ERASE HEAD

POLARITIES.
IF THE TIME PRINTED 1S FQUAL TO ZERQ IT IS AN INDICATION THAT THE FEOF WAS NOT FOUND WHEN "Ccu READY"TM RECAME A 1,

THIS

COULD

IMDICATE

ONE

FRASE

MEAD

POLARITY

FRASE
O0ONE

HEAD

CURRENT

QNF

WRITE

MORE
EQF

ATHERKWISE
THAN

WRITE

THE FOLLOWING PROSBLEMS:

SUFFICIENT

HEAD

SENSITIVE

"EOR

KEVERSED,

NOT

FUNCTION

TRACKS

READ

DION'T

FULLY

PQLARITY

SATULRATE

QEVERSLD.

TAPE,

AMPLIFIERS
REALLY

EOF SPACE

NQITE

TI“E"

"WRITE EOfF",

EQF

SHOULD

MARK,

SLIGHTYLY

LARGER

PROCFDURE TO MEASURE TIME:
A

RECORD

AND

EoF

FOF"

(REFERENCE

TAPE

REWRITE

REWQUND

RECQRD

RACKSPACE

OVER

WAS

PREVINUSLY

9.,12),

WR!TTEN

TO BOT,
OVER PREVIOUSLY

RECORD

JUST

WRITTEN
WRITTEN,

FROM

BCT

FOR

"WRITE

RECCRD,

SET BYTE RECORN COUNTER TO SpPACE 2 RECORDS.,
1SSUE SPACFE FORWARD FUNCTION, SET "no",
JATT FOR BYTE RECORD COUNTFER TO INNIJCATE THAT 1ST RECORD
HAS BEEN SPACED OVER THEN MOMITOR "CU READY"TM UNTIL IT BECOMES
A

AFTER

IN STATUS
TIME FROM
TO

EOF

"Cl}

READY"

CHECK

SPACE

TiMe",

C-8

SEE

NQT
=-1

IF “EQF"

SET THEN ZFERC TIME CCOUNTER,
UNTIL "CU READY"TM IS "EOR

Part
1

9.14

SPACE

SHUTDOWN

SPACE SHUTDOWN

MOVING

FCRWARD

DIRECTION

TAPE

AFTER

THE

SAME

FOR

MEASURE

RECORD

REASONS

RECORN (EOF),
THE TIME FROM
SHUTDOWN",

NNE

INCH

DATA

NME

INCH

PROCFDURE

OVER

"READ

THE

SHUTDOWN"

TIME:

“EOR TO

EQF

SPACE
|
THE

THE END OF
MONITOR "SETTLEDOWN" UNTIL IT BECOMES
"EOF"TM UNTIL "SFTTLEDOWN" IS "SPACE
)
|

TIME"

TIME

DATA,

SPACED

SPACE FORWARD FUNCTION USEN TO TIME
1S USED,
w
AFTER "EOF"TM BECOMES A 1, INDICATING

9.156

1S THE AMOUNT OF TIME NECESSARY

CONTINUE

PROCFDURE

883

MEASURE

BPI

WRITTEN

AND

TIMED

TIME:

INITIALIZE BYTE RECORD COUNTER AND guRRENT MEMCRY ADDRESS,

1SSUE

wWAIT

FOR

RYTE

WRITE

FUNCTION,

CURRENT

OUTRPUT

FQUAL

2ZERD,

TIME

FROM

2ND

INCH

"ONE

839

MEMORY

AND

RYTE

THEN

RP!,

SET

"GOv,

ADDRESS

INCICATE

2ND

MONITOR

RYTE

RECORD

COUNTER

UNTIL

BYTE

RECORO

COUNTER

OUTPUT

TIME"

DATA

19,
COMMAND

KEGISTER

FRRQR

NN ]
NEN 3
POWER

A2
@1

=
=

208
556

BPl
BP]

7
7

? = ODD

UNTT
UNTT

SFL.
SEL,

RIT
BIT

UNTT

SFL.

RIT

CONTROL

UNIT

INTERRUPT

2
1

12
11

=
=

820

BFI

822

BF]l]

TRACK
TRACK

1 = EVEN

2
RFEADY

ENARBLE
17
16

RBIT
31T

FUNCTION

BIT

ADPRESS
ARPRFSS

FUNCTION

BIT

FUNMCTION

KIT

1
@

28a
G831
21p

=
=
=

OFF LINE
READ
WRITE

108
121
110

=
=
=

SPACE
SPACE
WRITE

211

WRITE

111

REWIND

EQF

o
Lr

TRACK
TRACK

CLEAR

PARITY

e B e

////////

C-9

FORWARD
REVERSE
XIRG

1
Part

STATUS RLGISTER
15

ILLESAL

FND

SARITY

RUS
FND

FLLE (EOF)

ERROR

(PAE)

GRANT LATE (8GL)
nF TARE (EOT)

RECOID
N
X

(ILC)

FYCLICAL REDUNNANCY ERROK (CRE)

COMMAND

LENGTH

FERROR

(RLE)

NAN TAPE FRROR (RTF)
NINCOEXISTENT

SELECT

REMOTE

MEMORY

(NXM)

(SELR)

A
4

REGIMNING

OF TARE (BOT)
7 CHANMEL (7CH)
SETTLE DOWN (SDWN)
WRITF

LOCK

REWIND
TAPE

ENDR

(WRL)

STATUS

UNIT

(KWS)

READY

(TUR)

C-10

Part
1

APPENDIX D

TMA1l MULTIDRIVE DATA
RELIABILITY EXERCISER
(MAINDEC-11-DZTMH-A)
ABSTRACT

"THIS PROGRAM
IS DESIGNED
TO BE
/TECHNICIAN FOR EVALUATION AND

USED BY AN EXPERIENCED ENGINEER
DEBUGGING OF MAG TAPE DRIVES,

THE PROGRAM IS CAPABLE OF EXERCISING ANY TAPE DRIVE THAT CAN
BE QPERATED ON A UNIBUS PDP~1i SYSTEM THROUGH THE TMA=11 MAG TAPE
CONTROLLER, ANY TYPE OF TAPE DRIVE; 7 OR 9 TRACK MAY BE USED,
ANY NUMBER OF DRIVES, SINGLE OR MULTIDRIVE SYSTEMS, UP TO EIGHT
(8), MAY BE TESTED BY A SINGLE EXECUTION OF THE PROGRAM,
THIS

FLEXIBILITY
OR

TESTING

AND

POSSIBLE

SEQUENCE.,

OPERATING

RESPONSES

BECAUSE

THE

SEQUENCE,

TELETYPE

THE

ENTIRE

PROGRAM

TEST

DETERMINED

REQUESTS

AND

HAS

PLAN,

THE

SETTING

FIXED

INCLUDING

OPERATOR

CONSOLE

PARAMETERS

THROUGH
SWITCHES,

THE PROGRAM PROVIDES FOR TESTING OF ALL TAPE DRIVE FUNCTIONS
SUCH AS WRITING,READING,REWINDING,TAPE POSITIONING,EQY = BOT

SENSING
.

AND

HOWEVER;

DURING
ANY

THE

ERROR

GOOD

CONTROLLER

CYCLE

CONDITIONS

TEST CYCLE,
ERRORS,WORD

TMA=11

ORDER

CONTROLLER,

TESTED

PROVIDE

SOMEWHAT

FULL

FOR

ANY

PDP=11

C,
D.
E,

TELETYPE
TMA=11 TAPE CONTROLLER
1 TO 8 MAG TAPE DRIVES

LOADING
L B

USE

PROCESSER

CORE

PROCEDURE
N

STANDARD

ABOUT

CHECKS ARE MADE FOR STATUS ERRORS,DATA ERRORS,
COUNT AND CURRENT MEMORY ADDRESS ERRORS

APPLICABLE,

INTRINSICALLY

INFORMATION

DETECTED.

REQUIREMENTS (HARDWARE)
L E

TMA=11

THE TEST

DURING A
POSITION
WHEREVER

ASSUMES

PROCEDWURE

FOR

D-1

BINARY

TAPES

FPart|

STARTING

THERE

ARE

eeB(8),

PROCEDURE

FOUR

(4)

c04(8),

STARTING

210(8),

AND

ADDRESSES

THAT

MAY

USED?

240(8):

200(8)2 THIS ADDRESS MUST BE USED ON INITIAL START FROM
LOAD AS ALL PARAMETERS ARE ENTERED FROM HERE,
REQUESTS ARE PRINTED ON THE TELETYPE FOR ENTRY OF
TMA=11’S REGISTER STARTING ADDRESS, VECTOR ADDRESS,
UNIT NUMBER, DENSITY,PARITY,RECORD COUNT,CHARACTER
COUNT,PATTERN NUMBER, TAPE MARK (EOF) OPTION,AND STALL
FOR READ, WRITE, AND TURNAROUND,
ALL REPONSES SHOULD
BE MADE IN OCTAL AND WITHIN THE LIMITS OF THE PARAMETER,
A QUESTION MARK (?) WILL BE TYPED IF ANY
CHARACTER ENTERED IS NOT BETWEEN ¥ THRU 7 (OCTAL).
THE CHARACTER MAY BE RETYPED FOLLOWING THE GQUESTION
MARK,
IF THE RESPONSE IS NOT WITHIN ITS LIMITS, A
QUESTION MARK (?) IS TYPED AND THE ENTIRE RESPONSE
MAY BE RENTERED,
SOME RESPONSES REGUIRE MORE THAN ONE

(1)

CHARACTER,

RESPONSES

LEADING
RETURN

BUT

NEED NOT

NONE
HAVE

REQUIRES

ZEROS AND SHOULD BE

LESS

THAN

THE

THAN

TERMINATED BY

MAXIMUM

NUMBER

SIX

(6),

A CARRIAGE

CHARACTERS

INPUT,

204(8)2: THIS ADDRESS SHOULD BE USED ANYTIME A RESTART
OF THE PROGRAM IS NECESSARY AND THE PARAMETERS
ENTERED AT THE INITIAL START OF 2@@(8) NEED NOT
BE CHANGED,
ALSO NOTE THAT ANY DATA PATTERN WHICH
HAD BEEN GENERATED BY SETTING THE RANDOM DATA
SWITCH (CONSOLE SWITCH EIGHT) WILL NOT BE OVERWRITTEN
AND THERFORE IS HELD IN CORE FOR USE UNTIL
CONSOLE SWITCH EIGHT(8) IS AGAIN SET,

210(8)%

THIS ADDRESS IS THE SAME AS USING 204(8) IN THAT
PREVIOUSLY SET PARAMETERS ARE USED; HOWEVER, THE

PATTERN

IS RETURNED TO THE FIXED PATTERN ORIGINALLY

CALLED FOR
PREVIOUSLY

240(8):

THE
DATA

AT THE 200(8)
GATHERED WILL

START.,
ALSO
BE CLEARED,

ALL

STATISTICS

THIS IS A SPECIAL ADDRESS WHICH WILL CAUSE THE
PROGRAM TO EXECUTE A PREDETERMINED TEST PLAN ON
ALL AVAILABLE UNITS,
THE ONLY INPUT REQUIRED
BY THE OPERATOR IS A RESPONSE TO REQUESTS FOR
THE TMA=11 ADDRESS, VECTOR ADDRESS, AND CONTINUOUS
OPERATION OF THE SEQUENCE,
SEE

ITEM

11,

(PAGE

22)

FOR

FULL

DETAILS.

|
Part

1S AN EXPLANATION QF THE INITIAL
THE FOLLOWING
REGISTER

START:

VECTOR ADDRESS:

AND

RESPUNSES:

THE RESPUNSE REGUIRED FOR THIS REGUEST IS TO
ENTER THE ADDRESS OF THE FIKRST TMA=11 REGISTER
(MTS) AS A SIX DIGIT UNIBUS ADDRESS.,.
E REQUEST IS
FOR THIS
THE RESPUNS
INTERRUPT VECTUR ADDRESS USED BY

T0 ENTER THE
THE TMA=11 AS

CTHE UNIT NUMBER IS ENTERED AS ONE

(1) QCTAL

UNIT NUMBERS

REQUESTS

OCTAL)

(20®

START

ADDRESS.

DIGIT

(3)

THREE

CHARACTER AND MUST BE WITHIN THE LIMITS OF @
WHEN THE UNIT NUMBER HMAS BEEN ENTERED
THROUGH 7,
AND IS LEGAL, THE PROGRAM TESTS FOR THE PRESENCE
OF A UNIT OF THAT NUMBER,
IF THE UNIT IS

AVAILABLE A PRINTOUT QF 7 CHANNEL OR 9 CHANNEL

WILL

MADE

DENSITY

ASSIST

AND PARITY,

THE

OPERATOR

UNIT

NOT

SETTING

AVAILABLE,

A MESSAGE STATING SO WILL BE PRINTED AND A NEW
UNIT NUMBER REQUEST WILL BE ISSUED.
WHEN A
GOOD UNIT NUMBER HAS BEEN ENTERED, KREQUESTS FOR
OPERATING OENSITY AND PARITY ARE MADE FOR
THAT UNIT AND SHOULD BE RESPONDED TO ACCORDING
TO THAT PARTICULAR UNIT’S NEEDS,
AS MANY AS
EIGHT (8) UNIT NUMBER REQUESTS MAY pE USED,
HOWEVER,

AT LEAST ONE MUST BE USED., THE UNIT
AND THEIR RESPECTIVE DENSITY AND PARITY
ENTERED IN ANY ORDER.
THE INFORMATION

NUMBER
MAY BE
FOR

EACH

FOR

REFERENCE

UN1T

ENTERED

UNITS ARE REQUIRED,
UNIT NUMBER REGUEST
TERMINATE

THE

UNIT

THEN
WITH

ENTERED,
TO

WILL

DENSITY:

LEAST
IF

ONE

THE

CARRIAGE

REPEATED.

UNIT

FIRST

INTU

LESS

AND

EACH

UNIT

TABLE

EIGHT (8)

TO THE
RETURN

WILL

CUNTINUE

IT SHOULD BE REMEMBERED

NUMBER

REQUEST

RETURN,

THEN

REGUEST
IS

MUST

RESPONDED

THE

REQUEST

THE DENSITY REQUEST IS RESPONDED
CHARKACTER AND MUST BE WITHIN THE
AS

THAN

RESPONDING
A CARRIAGE

ENTRIES

70 THE NEXT PARAMETER,
THAT

LOADED

TESTING,

NUMBER

ENTERED,

UNIT

TO BY ONE
LIMITS OF
KEQUEST

OPERATING

DENSITY

FOR

THAT

RESPONSE

MEANINGS

ARE

AS FOLLOWINGS

TYPED.

(1) OCTAL
@ THRU 3,

FOR

THE

2UUBPYI,

CHANNEL

NRZ1

Ba
C.

1
2

=
=

S5%6BPI,
8UWRBPI,

7
7

CHANNEL
CHANNEL

NRZI
NRZI

BQVBPI,

9 CHANNEL

NRZI

THE

|
Part

THE PARITY REGUEST IS RESPONDED TO BY ONE

PARITYS

OCTAL

RECURD

COUNT:

THIS

CHARACTER

REQUEST

OCTAL NUMBER
ZEROS

ARE

WILL

MUST

EVEN PARITY

0ODD

RESPONDED
TO

TERMINATE

THE

HBY

177777,

ENTERED,

(1)

PARITY

REQUIRED
AND

ARE

EITHER

FROM

NOT

CHARACTERS

AND

SIX

LESS

THAN

CARRIAGE

RESPONSE,

(6)

CHARACTER

REMEMBER LEADING

THE

SIX

KETURN
RECORD

COUNT

IS USED IN CONJUCTION WITH THE CHARACTER COUNT
TO ESTABLISH A BLUCKING FACTOR FOR USE IN READ
WRITE CYCLES.,
|
|
|

CHARACTER COUNT:

THIS

RESPONSE

CHARACTERS

1S ENTERED

wITHIN

THE

FOUR

(4)

LIMITS

OF
4

THRU

LEADING
ZEROS ARE NOT
RETURN

TEKRMINATES
A

RESPONSE,
THE

RECORD

THE

BLOCK

SIZE

THE
NUMBER:®

THIS

COUNT

USED

BLUCKING

IS USED

RESPONSE

WITHIN

THE NUMBER
PATTERN TO

THAN

FOUR

COUNT

USED

(CHARACTERS

PER BLOCK)

SAME

NUMBER

LESS

THE

TWO

(4)

ESTABLISH

AND

ALL
@

AND

WRITE

CYCLES

AVAILABLE

CHARACTEKR

CHARACTER

CONJUNCTION

RECORD,

READ

(2)

LIMITS

ENTERED
BE USED

PER

OCTAL
4200, AGAIN
CARRIAGE

REQUIRED
AND A

CHARACTER

WITH

RECORDS

PATTERN

THE

THRU

UNITS,

QCTAL

20(8).

WILL CAUSE
A SPECIFIC DATA
FOR ALL READING AND WRITING.

THIS

DATA PATTERN
IS NOT CHANGED UNLESS KANDOM DATA
IS REQUESTED BY SETTING CONSOLE SWITCH EIGHT (8)

ONE,

RESETTING

DOES

NOT

CAUSE

BUT

WILL

HOLD

RESTART

THE

LAST

TAPE

READER

THE

EXTERNAL

DONE BY

BITS

377(8)

CALLED DTC.,

READ

ANY

DATA

INPUT

AND

THE

PATTERN

21u(8)

THE

HIGH

PATTERN

CHARACTERS

DATA

INPUYT,

THE

FILLED

WITH

UNTIL

0OrR

200(8),

SPEED

THOUGH

THE

PAPER TAPE
MAY

PAPER

DESIREU.

(MAINDEC=11=D2TMA=A=D)

CORE

SWITCH

PATTERN,

PATTERN ZERO (@) HAS
NUMBER ZERDO (v) WILL

DATA

CHARATERS

ULUATA

FIXcD

LOCATION

PREPARING

RANDOM

GENERATED

DONE FROM

THE SELECTION OF DATA
SPECIAL USE.,
PATTERN

CAUSE

THE

REVERSION

USEUD

IMPOSED,

ENTIRE WRITE
THE PATTERN

KEADER

WITH

ANY

AND

wWHEN

PROGRAM

CONFIGURATION

LIMIT

EXTERNAL

BUFFER IN
SO THAT ANY

SIZE

RECORD MAY BE USED,
DATA PATTERN
ZERO (@) EXTERNAL PAPER TAPE NEED ONLY
BE READ ONCE AT INITIAL STARY OF 20w (8),
NEED

KEAD

RANDOM

DATA,

BEFORE

PRESSING

SEeE
DATA

NOT

ITEM

AGAIN
SURE

UNLESS

LOAD

OVERWKITTEN
THE

AND
BY

READER

START,

(PAGE

PATTERNS,

D-4

FOR

DESCRIPTION

THE

Part1

TAPE MAKRK:S

THE TAPE MAKK REQUEST
THE

OPERATOR

WISHES

1S USED TO DETERMINE IF
HAVE

EACH

DATA

BLOCK

SEPARATED BY A
END OF FILE).

TAPE MARK (QFTEN CalLLED EOQF
1F ReSPONDED TO BY A ONE(1)

FOR

TAPE

WILL

MARK

WILL

WRITTEN

AND

WHEN

THE

KREADING

A
BE EXPECTED AT THE END OF EACH DATA BLOCK,
ZERO (W) RESPONSE WILL DISALLOwW THE TAPE MARK
OPTION,
PLEASE NOTE THAT THE TAPE MARK RECORD
INCREASES THE BLOCK SIZE BY ONE(1) KRECORD;
IN GTHER
HAVE THE

STALLS:

THE

WORDS, A BLOCK OF 100 RECOKDS
TAPE MARK AS RECORD {01,

STALL REGUUESTS

TERMINATED BY A CARRIAGE
THE VALUE ADDS ABQUT 2.6

TO BY

A S5IX

(6)

YIME

WRITE:

THE TIME DELAY BETWEEN EACH RECORD WRITTEN
TIME
TAPE
AND

PARAMETERS:
|

FOR

SHOULD
THE

NUMBER,
AS

EACH

BETWEEN

NOTED

ALREADY

AND

STORED

PARKAMETER

CHARACTER

EACH

RECORD

DELAY BETWEEN CHANGES
DIRECTION (FORWARD,TO

ALL

PARITY)
THE

REQUEST

COUNT,

ITS PRESENT STORED VALUE
IF THESE VALUES NEED NOT

OF
REVERSE,ETC,)

PARAMETERS

VALUES

READ

BLOCKS,

THAT

DESCRIPTION

DENSITY,

VALUES

COUNT,

UNIT

BETWEEN

INCREMENT
DELAY,

THE

ARDUND:

DELAY

RETURN,
EACH
MICSEC 10 THE

READ:

TURN

RESPONDED

CHARACTER OCTAL NUMBER WITHIN THE LIMITS OF 1
THRU 177777,
LEADING ZEROS ARE NUT REQUIRED AND
AN ENTRY UF LESS THAN SIX (6) CHARALTERS SHOULD

BE
OF

FIXED

ARE

WILL

HAVE

NUMINAL

PROGRAM,

(PATTERN

NUMBER,

AND STALLS)
IS
BE

EXCEPT

(UNIT

RECORD

IS TYPED.

ALSO PRINTED,
CHANGED, SIMPLY

TYPE A CARRIAGE RETURN
AS RESPONSE AND NO
CHANGE wILL BE MADE.,
EACH START OF THE PROGRAM
AT 200(8) WILL SHOW THE CURRENT VALUES OF THESE
PARAMETERS

PER

THE

FRESH

THE

PAPER

LOAD

PARAMETERS

THE

WILL

LAST

REFLECT

PROGRAM,

RECORD

Be
C.

CHAKACTER COUNT = 201}
PATTERN NUMBER = 1

COUNT

D,
E.

READ STALL
WRITE = |

Fo.

TURN

ARQUND

100

1}
=

D-5

ENTKY.

TAPE

THE

FIXED

WHEN

DONE,

A
THE

VALUES

STORED

|
Part

SAMPLE START AT 200 (8)
THE

FOLLOUWING

PRINTED

REQUESTS

SAMPLE

AND

THEIR

THE

RESPONSES,

RESPONSES AKE ENCLOSED
IN PARENS FOR
CLARITY ONLY AND (CR) MEANS CARRIAGE RETURN

LOAD ADDRESS 200(8), SET CUNSOLE SWITCHES, PRESS START SWITCH:
TMA=11

ENTER

TAPE

DRIVE

CONDITIONS

START

TEST

IN OCTAL
172520

(CR)

VECTOR ADDRESS = 224 (CR)
UNIT NUMBER=(5) 9 CHAN
DENSITY=(3)

PARITY=(Q)
UNIT NUMBER=(2)

7 CHAN

DENSITY=(2)
PARITY=(1)

UNIT NUMBER=(CR)
RECORD COUNT=1Q28

CHARACTER
PATTERN

(500) (CR)
COUNT=201 (38)72(7)(CR)

NUMBER=1

(ef2)

(6) (CR)

TAPE

MARK

ENTER

STALLS

READ=1

(CR)

WRITE=1

"TURN

(1) (CR)

(CR)

AROUND=1

(30260@) (CR)

THE PROGRAM
WILL NOw PERFORM
THE CONSOLE SWITCHES OUN UNIT

THE TEST
FIVE (5)

ONE BLOCK ON EACH UNIT PER CYCLE,

CYCLE SET IN
THEN TwO (2),

USING DATA PATTERN

NUMBER SIX (6) WITH A BLUCKING FACTOR OF 37 CHARACTERS
PER RECORU AND S0Q@ RECORDS PER BLOCK,
THE DELAYS AKE SET
FOR MINIMUM
ON READ AND WRITE, AND APPROXIMATELY .75
|
SECUNDS ON TURN AROUND,

D-G6

1
Part

DATA

PATTERNS

THERE
AND

ARE

ANY

TWENTY

ONE

DATA

CASE IS PATTERN
REWUIRES THAT A
ENTERED

DATA

THE

TAPE,

THE

ACTUAL

COMBINATION

STORED

THE

OCTAL

377

ONE

TAPE

CHAKRACTER

KEAD

THAT

ARE

MAY

DATA

CHARACTER

AND

WILL BE

ON
ON

WILL

WITH

THE

SIZt

RECORD

USED,

THE

FOLLOWING

LIST

THIS

THAN

CHARACTERS

AS THEY APPEAR
CHARACTERS ARE
CAN

READER,

DATA

BITS

FILLED

GENERATORS

SELECTED.,

FIKRST

THE TAPE,
TAPE, THE

CORE

UN]QUE

INPUT

LOADED

THE

CONTAINED

ANY

INTO

CORE

NO MATTER HOW MANY
ENTIRE WRITE BUFFER

PATTtRN

CONTAINS

THE

DATA

THAT

PATTERNS

SPEED

(2000

CHARACTERS)

ANY

AVAILABLE:

DATAL1:

ALL

DATA2:
DATA3:

ALL ZERO BITS IN ALL CHARACTERS
A ONE BIT WALKING FROM RIGHT TO

DATA4:

DATAS:

ALTERNATING

ONE

DATAG:

ALTERNATING

ZERO

DATA7:

SAME

DATAS

BUT

WITH

EVERY

OTHER

CHARACTEK

COMPLEMENTED

DATAL®:

SAME

DATA6

BUT

WITH

EVERY

OTHER

CHARACTER

COMPLEMENTED

DATAL1:

INCREMENTING

DATAL2:

DECREMENYING

DATA13:

ALTERNATING

CHARACTERS

ALL

ZERO

DATAL14:

ALTERNATING

CHARACTERS

ALL

ONE

AND

ALL

DATAL1S:

SPECIAL

ZERO

BIT

REPEATED

DATAle6:

IBM

COMPAT

DATA17:
DATA20:

IBM

ZERO

HIGH

EXTERNAL

ONE

THRU

ENTERED

DATAD:

(SEE DTC;

SPEED

FEACH
OF

ZERO(WQ); SELECTION OF PATTERN ZERO(®)
PREVIOUSLY PREPARED PAPER TAPE BE

THE

NUMBER

MAY

HIGH

PATTERN

CHARACTERS,

PATTERN

THESE

READER

MAINDEC=11=DZTUF=A)

BITS

BIT

WALKING

FROM

AND

FIELD

LEFT

ZERO

BITS

EACH

CHARACTER

ONE

BITS

EACH

CHARACTER

AND

CHARACTERS

LEFT

RIGHT

CHARACTERS

PATTERN

ALL CHARACTERS

FIELD

ZERQS
ONES,

(000-377)

(377=000)
AND

WALKING

PATTERN

RIPPLE

COMPAT

PATTERN

FIXED

(ABCDEF)

COMPAT

PATTERN

FIXED

(J)

ALL

UNE

BITS

ZERO

BITS
4

TIMES

Part |
RANDOMIZATION

THERE
DATA,
SOME

AKE THREE
CHARACTER
FIXED

CONSOLE

(3) VALUES THAT MAY BE GENERATED RANDOMLY;
COUNT, AND RECORD COUNT,
THESE ARE NORMALLY

VALUE

BUT

MAY

RANDOMIZED

SETTING

THE

SET

APPRQOPRIATE

SwITCHtS
A,

RANDOM

DATA:

GENERATES
CHARACTER,

IS SET
SWITCH

(CONSOLE SWITCH
8)
ENTIRE BUFFER, CHARACTER

OF RANDOM

DATA

WHEN

SWITCH
8

70 A ONE,
ONCE SET, THE RESETTING
OF
8 CAUSES THE LAST GENERATED PATTERN

TO BE RETAINED IN CORE,
A RESTART AT LUOCATION
2o (8) OR 210(8) WILL CAUSE REVERSION OF THE
DATA TO THE FIXED PATTERN REQUESTED INITIALLY.
A

RESTART

LOCATION

2@4(8)

WILL

HOLD

THE LAST GENERATED PATTERN IN CORE UNTIL SWITCH
8 IS AGAIN SET.
ALTHOUGH THE DATA IS GENERATED AS RANODUM,

- THE
THE

PROGRESSION
SAME

FROM

THEREFORE

THE

RANDOM CHARACTERS

ALWAYS

OQUTSETY

RANDOMIZATION,

POSSIBLE

GENERATE

OUNE

TAPE

REEL

OF RANDOM DATA ON ONE UNIT, RELOAD THE
PROGRAM TO RE=-ESTABLISH THE OUTSET POINT, AND
READ THE RANDOM TAPE REEL ON ANOTHER UNIT

FOR COMPATABILITY
RESTARTING

THE

PUINT

OUTSET

TESTING,

PROGRAM

FOR

PROGRAM

MUST

WRITTEN

READ

~ ORDER THAT

THEY

WERE

NOTE

WILL

NOT

TYHAT

MERELY

RE=~ESTABLISH

RANDOMIZATION,
BUT

FULLY

LOADED

IN ORDER TO GENERATE THE SAME
RANDOMIZATICON!
IN MULTIDRIVE
BLOCK OF DATA, WHETHER RANDOM
EACH

THEN

THE

RESTAKTED

PROGRESSIUN OF
SYSTEMS THE SAME
OR

FIXED,
IS

AVAILABLE

ENTERED,

UNIT

BEFORE

THE

BEING CHANGED,

RANDOM

LHARACTER COUNT: (CONSULE SWITCH 7)
GENERATES A DIFFERENT NUMBER OF CHARACTERS
PER RECURD TU BE WRITTEN ON EACH BLOCK CYCLE,
THE SAME NUMBER OF CHARACTERS PER KECORD IS
WRITTEN

BEING

LAST

VALUE

RANDOM

EACH

AVAILABLE

RESETTING

SWITCH

UNIT

BEFORE

HOLDS

THE

GENERKATED,

RECORD

GENERATES
FOR

READ

CHANGED,

COUNT:

(CONSOLE

DIFFERENT

NUMBER

BLOCK

DATA

SWITCH

WRITTEN

RECORDS
OR

READ

EACH BLOCK CYCLE,
THE SAME NUMBER OF RECORDS
IS WRITTEN OR READ ON EACH AVAILABLE UNIT BEFORE
BEING CHANGED,
KESETTING SWITCH & HOLDS LAST VALUE
GENERATED,

D-8

710

Part
1

DYNAMIC
LA

PARAMETERS:
X

-y

¥}

THE THREE (3) STALL VALUES ARE CONSIDERED TO BE DYNAMIC
PARAMETERS AS THEY MAY BE CHANGED WHILE THE PROGRAM IS
RUNNING

TYPING

SOON
AS THE

PROGRESS,

BUS

THE

CONTROL

RELEASED

PROGRAM

WILL

CHARACTER
BY

THE

RESPOND

MAG

THE

TELETYPE,

TAPE

OQOPERATION

THE

CONTROL

INPUT

BY TYPING A REQUESY FOR NEW STALL PARAMETERS,
THE LAST VALUES
THAT WERE ENTERED WILL BE PRINTED AS THE STORED VALUES AND MAY
BE

CHANGED

TYPING

ENTERING

CARRIAGE

NEW

VALUES

RETURN,

D-9

LEFT

UNCHANGED

PartI

CONSOLE

SWITCH

SETTINGS

THE CONSOLE SWITCHES ARE USED TO SEY UP THE TEST CYCLE
DESIRED, TO GENERATE RANDOM VALUES, AND TO CONTROL ERROR
RESPONSES,
THE SWITCHES SHOULD
BE SET IN THE DESIRED
MANNER BEFORE PRESSING THE START SWITCH BECAUSE THEY
ARE ALL DYNAMIC
AND WILL RUN THE PROGRAM IN ANY
CCNFIGURATION,
ALL SWITCHES SET TO ZERO(@)
IS NORMAL,

SW15:
Swid:

Swi3:

1=STOP ON ERROR

0=CONTINUE
1=Y0ZZLE
©=D0 NOT

1=D0

ERROR

ON CURRENT BLOCK
YOZZLE ON BLOCK

NOT

@=CHECK

ERRORS

CHECK DATA
ERRORS

DATA

Swias

1=D0 NOT CHECK WRITE
@=CHECK WRITE STATUS

SWils

1=D0C NOT CHECK READ
P=CHECK READ STATUS

SWwi1@:

1=D0 NOT PRINT ANY
@=PRINT ALL ERRORS

SW9:

SW8:

{=REWIND

ALL

@=D0

REWIND

NOT

1=GENERATE
W=USED

SWT7:
SW6 ¢

SWy s
SW3:

STATUS
ERRORS

ERRORS

AVAILABLE

RANDOM

ERRORS

TAPES

DATA

FIXED

1=GENERATE RANDOM CHARACTER COUNT

@=USE

FIXED

{=GENERATE

@=USED

SW5S 3

STATUS
ERRORS

CHARACTER

RANDOM

FIXED

COUNT

RECORD

COUNT

13Y0ZZLE ON CURRENT RECORD

W=DO0

NOT

YOZZLE

RECORD

1sPRINT STATISTICS
@=D0

NOT

1=D0

NOT

READ

STATISTICS

@=READ

SwWe s
SW13

SWQ s

NOT USED
1=DISABLE

WRITE

@=ENABLE

WRITE

12D0 NOT
PSWRITE

WRITE

AND
AND

READ
READ

RETRY
RETRY

OPTION
OPTION

Part1

SWITCH EXPLANATION
SWA+SKW3:

AND EXAMPLES:?

THESE SWITCHES ARE USED TO CONTROL THE SEQUENCE
OF MAG TAPE UPERATIONS PREFORMED ON EACH AVAILABLE
THROUGH

DESCRIBED

DATA

BLOCK

THE

UNIT,

THE RESPONSES TO TELETYPE REQUESTS AT INITIAL START
WILL BE EITHER WRITTEN OR READ FROM EACH AVAILABLE
UNIT IN THE ORDER THAT THEY WERE ENTERED,
THE SEQUENCE

OF OPERATIONS IS CALLED A CYCLE, AND WILL BE PERFORMED
CONTINUOUSLY UNTIL STOPPED BY THE OPERATOR, WHEN END
OF TAPE IS REACHED, THE UNIT WILL BE REWOUND AND
FLAGGED AS UNAVAILABLE FOR TEST UNTIL ALL UNITS HAVE
REACHED EOT, AT WHICH TIME TESTING IS RESUMED ON ALL
»

AVAILABLE UNITS,

EXAMPLES: SWO+SW3

B,
C.,

SWDQ=@,SwW3=t1
WRITE ONLY X RECORDS OF Y CHARACTERS

SwWd=1,S5W3z@

READ

ONLY

RECORDS

THEN

CHARACTERS

SW2=@,S5w3=0

WRITE
SW1is

BACKSPACE

AND READ X

RECORDS

SWITCH ONE(1), WHEN SET TO A ZERO (©), WILL
CAUSE ANY DATA RELATED WRITE ERROR Y0 BE RETRIED,
THE RETRY SCHEME CONSISTS OF REWRITING THE RECORD
IF
IN THE SAME SPOT ON THE TAPE FOUR (4) TIMES,
ALL FOUR (4) REPEATS ARE SUCCESSFUL, THE RECORD
1S CONSIDERED RECUVERED, AND A TAPE WRITE ERROR
IS LUGGED, IF ANY OF THE FOUR (4) REPEATS
IS UNSUCCESSFUL, A WR1TE WITH EXTENDED
INTERECORD GAP IS DONE, A SUSPECTED BAD TAPE
SPOT LOGGED AT THIS BLOCK AND RECORD NUMBER,
AND A SECOND RETRY OF FQOUR REPEATS 1S DONE,

IF
Bt

AFTER FOUR (4) RETRIES, THE
RECOVERED A NOTIFICATION IS

TESTING IS

RESUMED

20(8)

APPROPRIATE

WILL

BAD

TAPE

REWOUND

THE NEXT

SPOTS

AND

RECORD CANNOT
PRINTED, AND

ARE

REMOVED

MESSAGE

RECORD,

FOUND,
FROM

THE

UNIT

TESTING

WITH

PRINTED.

SWITCH ONE (1), WHEN SET TO A ZERO (@), WILL ALSO
CAUSE ANY DATA RELATED READ ERROR TOU BE RETRIED,
THE RETRY SCHEME CONSISTS OF REREADING THE RECORD
A MAXIMUM OF FOUR (4) TIMES,
IF THE RECORD IS
SUCCESSFULLY

LOGGED

RECOVERED

CONSIDERED

FOR

ANY

STATISTICS

THE

REREADS

PURPOSES

A SOFT READ ERROR AND TESTING CONTINUES
REREADS FAIL TO RECOVER THE RECORD, THE

Swd:

SWITCH

FOUR

STATISTICS
WILL

SEE

ITEM

A
(4)

HARD

READ

WHEN

GATHERED

PRINTED
1@,

PAGE

SET

FOR
THE

D-11

ERROR,
WILL

EACH
END

FOR

TO BE

IF THE
ERROR

FULL

UNIT,.,
A

THE

BLOCK

DETAILS.,

NUMBER

CYCLE,

Part
1
SW53

SWITCH FIVE (S) WHEN
OPERATION WILL CAUSE

CONTINUOUSLY

SET
THE

DURING A READ
PROGRAM TO

READ THE CURRENT

RECORD

SPACING REVERSE OVER THE RECORD AND
REREADING THAT RECORD,
THIS TAPE MUVEMENT

IS CALLED YOZZLING,

THERE

IS A SOFTWARE

DELAY EXECUTED BETWEEN EACH
‘OF THE RECORD AND IT MAY BE

SPACE/READ
VARIED BY

THE EXECUTION OF THE YOZZLE
TO THE PRINTED REQUEST WITH

AND RESPONDING
A SIX (6)

TYPING CONTROL C ON THE TELETYPE DURING
DIGIT

VALUE.,

PREVENT

SET
SWe=81

SW9:

SWip=13:

THE

A VALUE OF
TO

THESE

1000

YOZZLE

STALL

EXCESSIVE TAPE WEAR,
ANY VALUE THROUGH THE

THREE

(3)

PRESET

IN THE PROGRaAM
TU

SWITCHES

BUT

MAY BE
TELETYPE,

CONTROL

THE

RANDOMIZATION

OF DATA AND BLOCK SIZE AND MAY BE SET
THE ACTUAL CHANGE
AND RESET AT ANY TIME,
WILL TAKE PLACE BETWEEN BLOLCK CYCLES,

SWITCH NINE (9) WHEN SET WILL CAUSE ALL
AVAILABLE TAPE UNITS TO BE REWOUND AT
THE END OF THE CURRENT BLOCK CYCLE. TESTING
WILL

RESUMED

ONE

(1)

WHEN

THESE

SWITCHES

BLOCK

UNITS

ARE

USED

COUNT

HAVE

REACHED

CONTROL

DESCRIBED

BQOT,

THE

TAPE

TO BE DONE ON THE

ERROR HANDLING
OPERATION

ALL

SWITCHES

¢+3.

~SWITCH TEN (1@) WHEN SET TO A ONE
WILL DISALLOW
ANY ERROR PRINTOUTS MaDE
ON THE OPERATION IN PROGRESS,
CATASTROPHIC

FAILURES

AND

INFORMATION PRINTOUTS wlLL

STILL OCCUR.
BOT, DROP OR

IE:
PICK

SKWITCH ELEVEN
WILL

OISALLOW

(11) WHEN SET TO A ONt

THE CHECKING
FOR

ERRORS
ON READ

OPERATIONS.,

SWITCH TWELVE

(12)

WILL

THE

DISALLOwW

ERRURS

UNIT NOT AVAILABLE, ILLEGAL
OVERFLOW, AND EOT REWIND,

WRITE

SWITCH THIRTEEN
WILL

DISALLOW

DATA,

THIS

STATUS

CHECKING,

STATUS

WHEN SET TO A ONE
CHECKING

FOR

STATUS

OPERATIONS,

(13)

THE

SWITCH

WHEN SET TO A ONE

CHECKING

HAS

D-12

READ

EFFECT

Part|
Swild:

SWITCH

FOURTEEN

READ

ONLY

BLOCK

KREAD

REMAIN

TAPE

THIS
Swihs

AND

BEING

SPACED

READ

BLOCK

FIFTEEN

CAUSE

READ

ALLOWED
BE

DURING
A

SET,

WILL

THE

CONTINUOUSLY

MOVE

FORWARD

AND

DATA

PROGRESSIVELY,

YUZZLE.
(15)

THE

USED

WHEN

OVER SO THAT TAPE WILL
BLOCK, WHEN RESET, THE

THE SAME

wWILL

GWITCH
WILL

DATA

WILL

BLOCKS

(14)

OPERATION;

WHEN

PROGRAM

SET

HALT

A
ON

ONE,
ANY

ERROR DETECTED BY THE UPERATION IN PROGRESS,
IF BOTH SWITCH
TEN (1@) AND FIFTEEN (15)
ARE

SET,

NOT

THE

IF SWITCH
CONTINUE,
WILL

ACTUAL

PRINTED

TEN
THE

BUT

ERROR
WILL

DETECTED

CAUSE

WILL

HALT,

(1@) IS RESET BEFORE PRESSING
ERROR WHICH CAUSED THE HALT

PRINTED

BEFORE

D-13

TESTING

RESUMED,

1
Part

PRINTOUTS

ERROR

THERE ARE THREE TYPES OF ERROR
THE PROGRAM; OPERATION ERRORS,

ERRORS,
HEADER

BAD

RECORD

RECORD,

EACH

ERROKR

WHICH

NUMBER

AND

MESSAGE

CONTAINS

THE

PLUS

TYPE

PRINTED

UNIT

TOTAL

NUMBER,

NUMBER

OPERATION

WHICH

PKRECEDED
BY

BLOCK

NUMBER,

COUNT

RECORDS,

CAUSED

SIZE

ERRUR,

ERRURS:?

OPERATION

THESE

ARE

ERROKS

RESULT
QF A

WHICH

TAPE

CAN

OCCUR

OPERATION,

DIRECT

ERRORS:

STATUS

READ/WRITE

PRINTOUTS MADE BY
DATA ERRORS, AND CONULITION

THESE ARE INDICATED BY THE ERROR BIT
(RIT

15)

BEING

THESE

ARE

OTHER

THAN

CURRENT

TAPE

FROM

COMMAND

ONE.

ERRORS:

INDICATED

INCORRECT

ADDRESS

BOTH

ZERO

MEMORY

(@)

POSITIONING

THESE
COUNT

BYTE

COUNT

ERRORS:

ARE INDICATED BY A SPACE
OTHER THAN ZERO (@), NO BOT
A

READY

UVATA

THE

RECORD LENGTH

SET

REWIND,

THE

END

TAPE

FOUND

UNIT

REWIND,

ERRORS:

DATA

ERROKRS

BEING

READ

THE

WILL
AND

EXPECTED

OCCUR

THE

DATA

WHEN

TAPE

DOES

NOT

MATCH

DATA,

BECAUSE DATA RECORDS CAN BE UP TO TWO THOUSAND
CHARACTERS LONG, AN EKROR CONDITION WHICH WILL CAUSE
THE ENTIRE RECORD TO READ INCORRECTLY COULD CAUSE A VERY

LENGTHY
BAD

PRINTOUT,

CHARACTERS

THEREFORE,

EMPLOYED,

COUNTER

TEN

(18)

SUCCESSIVE

CHARACTERS

IN SUCCESSION ARE BAD, A NOTIFICATION IS PRINTED
(BLOOL BATH) AND THE NEXT TWENTY (20) CHARACTERS
ARE SKIPPED BEFURE CHECKING IS RESUMED.,
IF Tne BLOOD
BATH

CONDITION

RECORDL,

THE

OCCURS

THE

REST

LAST

TEN

(10)

CHECKED,

THE

ONLY BE DONE
TO ALLOW IT,

THREE

THE

TIMES
IS

CHARACTERS,

SKIPPING
ON

(3)

RECORD

RECORDS

AND

WHICH

RESUMPTION

WHICH

ARE

ONE

SKIPPED,

LONG

WILL

DOwN

BEe

CHECKING

ENOUGH

WILL

Part|

CONDITIOCN

ERRORDS?S

THESE ERRURS REFLECT
AND

BEFORE

WHEN AN EOT (END OF TAPE) IS ENCOUNTERED DURING
EITHER A READ OR A WRITE, THAT UNIYT IS FLAGGED AS
UNAVAILABLE FOR TESTING AND IS REWOUND UNTIL ALL
AVAILABLE UNITS HAVE REACHED EOT, AT WHICH TIME
TESTING IS RESUMED ON ALL AVAILABLE UNITS,.

EOTS

ILLEGAL

BOT:

WHEN

CATASTROPHIC ERRQOR,
TESTING MAY
BY PRESSING THE CONTINUE SWITCH,

CONTROLLER NOT

READY:

BEFORE

IS CHECKED FOR READY,
WILL

ANY

IF IT

(BOT)

RESUMED

NOT AVAILABLE: THIS CAN OCCUR WHEN THE SELECTED
BECOME UNAVAILABLE.
THIS IS A CATASTROPHIC
ERROR AND WILL CAUSE A HALT.
TESTING MAY
BE RESUMED BY PRESSING THE CONTINUE SWITCH,

UNIT

TAPE

THE ERROR IS
THIS IS A

ERROR

OPERATIUN

IS NOT

UNIT

ATTEMPTED

READY,

HAS

THE

SETTING
TIME,

BE PRINTED,

INTERRUPT
IN THE

RETURNED

ERROR

CPU,

WITHIN

THE

APPROPIATE

PRINTED,

EXAMPLES:

GLOSSARY:?

CONTROLLER

INTERRUPT RETURNED: EACH TAPE OPERATION SHOULD BE TERMINATED BY
INTERRUPT

A UNIT ENCOUNTERS BEGINNING OF

DURING A READ OR WRITE OPERATION
PRINTED AND THE PROGRAM STOPPED,.,

THESTATE
OF THE TAPE SYSTEM

AN OPERATION,

AFTER

NUMBER

BN
RN

BLOCK

RECORD

NUMBER

RECORD

SIZE

WRITE

ERROR

READ

SE
F

=
=

(X)

TOTAL

PER

(Y)

RECORD

SPACE

ERROR

FORWARD

COMMAND

STATUS REGISTER

BYTE

CURRENT

CHARACTER

GOOD

B =
ERR
TM

ERROR

CHARACTERS

BAD
AMT
=

COUNTER

MEMORY

DATA

ADDRESS

POINTER

(SHOWN

BIT

FORMAT

DATA (SHOWN IN BIT FORMAT
= NUMBER LEFYT TO SPACE

TAPE

MARK

AND

EXPECTED

VALUE

NUMBER

(OFTEN

CALLED

EQOF

CORE)

FOR

END

LPC = LONGITUDINAL PARITY CHECK (RECEIVED
PATTRN = DATA PATTERN (R=RANDOM)
|

FILE)

EXPECTED)

Part|

EXAMPLE 1
ExamPle

1IN

WAS

THIS

TwelVIH
COUNT

UNIT
BN

(12)

AKND

KETRY

xPATTRN

NO,

1010001111000
100Q

STAT

Q1L ERINLLRLY

1443b6=144306

EXAMPLE

VERTICAL

WRITE

RECORD

THE

MEMORY

wWAS

PARITY

OPERATION

BLOCK.

ADDRESS

THE
ARE

DISABLED,

WORD

COUNT

SHOWS

LEFT

TRANSFERRED,

REFLECTS

COUNT

THAT

THE

CHARACTERS

CURRENT

SHORTAGE

MEMORY
20

CHARACTERS TRANSFEKRED HAD OCCURRED.
THIS EXAMPLE THE STATUS AND COMMAND
REGISTERS

THE
NO,

LLPC

*PATTRN

1OxRN

¥120011111000100

uvvervYl12vRval

12466=12506

33/

]«100%RS

UNIT

2%xRN

ERR

AMT

ANY

ERROR,

BUT

INCORRECT.,

SUxRE

Fxxw

3¢ IN THIS EXAMPLE THE TAPE UNIT WAS TRYING
TO SPACE OVER THE 15 RECORDS IN
THE BLOCK IN ORDER TO ESTABLISH PROPER
POSITION TO BEGIN READING,
THE OPERATION WAS TERMINATED
BEFORE

THE

AND

ERROR

NOT

PROPER

NO.

SHOW

=147
EXAMPLE

EXAMPLE

NOT

SHOWN

LPC

WUORD

CORReCT,

2: IN THIS EXAMPLE A RECORD LENGTH ERROUR WAS
DETECTED WHILE READING THE FIRST
RECORD OF
THE BLOCK,
THE RETRY OPTION WAS DISABLED.
THE

ADDRESS

UNIT

EKROR
THE

2000 xWE

COMD
WC

TAPE
A

OPTION

12=200%xRS

DURING

CURRENT

THE

40b6xRN

EXAMPLE

DETECTED

*xPATTRN

15=15%xRS

ENTIRE

SHOWN

RECORDS

BECAUSE

POSITION

R
*SE

WERE

THE
BEGIN

TRAVERSED

TAPE

READING,

1
Part

EXAMPLE

4: IN THIS EXAMPLE UNIT NUMBER ONE (1) HAD
REWOUND VIA CONSOLE SWITCH NINE (9) AND AT

COMPLETION
THE STATUS

OF THE OPERATION
REGISTER,

BOT

WAS

NOT

BEEN
THE

SET

xPATTRN R
UNIT NO, 1
BN 3002%RN 65=-65%RS 1@
NO BOT ON REWIND=HALT
EXAMPLE

EXAMPLE

THIS

EXAMPLE

TWO

BAD

CHARACTERS

READ

FROM

TAPE

THE

FORWARD

THE

FIRST

(@)

AND

THE

THIRTEENTH

THE

TOTAL

NUMBER

IN THE

BLOCK

ARE BAD,

SIXTEEN

WERE

DIRECTION,

(13)

(16)

CHARACTER

CHARACTERS

NUMBER

ZEROQ (@) HAS DROPPED BIT NUMBER FIVE (5) AND
CHARACTER NUMBER TWELVE (12) HAS PICKED UP
BIT
UNIT

NO,

NUMBER

SEVEN

(7).

xPATIRN S
xx
3=10%KS 15%DE~F

12%xRN

10101010

12021010

V1210184

11010101

I
Part
EXAMPLE

EXAMPLE

EOT
UNIT

TESTING

WILL

ALL

RESTART

AVAIL

HAVE

FOR

UNIT

REACHED

SIX
THE

(6)
{ST

NUMBER

HAS
TIME

SIX

AND

WILL

(6)

EOT,

R
1566

AND

BLOCK

NUMBER

(EOT)

25-600%RS

UNIT

TAPE

UNITS

NO, |
WILL REWIND
ALL

*PATTRN

»RN

RESTARTED
WHEN

EXAMPLE

END

NO.

677

THIS

REACHED
WHEN

UNIT

UNE

UNITS

REACH

EOT

EXAMPLE
7

EXAMPLE

7¢

THIS

EXAMPLE

ENCOUNTERED

THE
BE

UNIT
BN

NO,

S56xRN

ILLEGAL

PROGRAM
RESUMED

HAS

NO,

1xRN

NOT

TAPE

HALTED,

PRESSING

THE

TWO (2)
(BOT)

HAS

AND

TESTING MAY
CONTINUE

SWITCH,

1200

THIS

EXAMPLE

BECOME

HALT

UNIT

NUMBER

BOT=-HALT

EXAMPLE

WILL
BY

*PATTRN

2«4%xRS

UNIT

BEGINNING

ALLOW

RESUMED

xPATTRN

@=200xRS

THE

UNAVAILABLE,

SELECTED
THE

UNIT

(NUMBER

PROGRAM

OPERATOR

CORRECTION

PRESSING

THE

AND

CONTINUE

WILL
MAY

SWITCH,

AVAILABLE
EXAMPLE

EXAMPLE

93 IN THIS EXAMPLE THE WRITE OPERATION EXECUTED
UNIT NUMBER SIX (6) WAS NOT COMPLETED AND NO
INTERRUPT

UNIT

NO.,

12%xRN

INTERRUPT

WAS

xPATTRN

3«4%xRS

100*xWE

RETURNED

RETURNED,

REWOUND,

1
Part
EXAMPLE

THIS

EXAMPLE:

THE

SHOWS

EXAMPLE

RECOVERED

SECOND

READ ERRQR WHICH

RETRY,

THIS

ERROR WILL BE LOGGED AS A RDERR BUT WILL BE
CATEGORIZED AS A SOFT ERROR,
THE REGISTERS

SHOW

PARITY ERROR

R
=*=PATTRN
UNIT NO,1
*BN 10 xRN 2=100 *RS 1117
COMD 111212011020202010
STAT
WC

THE

*RE

Fxxx

*RE

Fxx%xx

CAUSE

QOF

THE

ERROR.

pR1120000210200001

337=-147

LPC

%%
ERROR*

xxk*kORIGINAL

UNIT
soines,

WAS

*BN

NO,

*xPATTRN

*RN

P2=100

xRS

1117

1112100110000010
Q011020VR1000001Y
|

CoOMD
STAT
WC o

3537=147

LPC
READ

FAILED=-=-RETRY: 1
REREAD SUCCESSFUL»=RETRY:

EXAMPLE

11:

THIS

WAS

NOT

INCHES

UNIT
*BN

xRN

370

=461

TAPE

*RS

1110800100001
00

STAT

2011200100200

25613

R
*RS

1110V00200102@01U¥A

STAT

9211020201 00000]1

25613

SUSPECT
RETRY:

BAD

2447

=xWE

2407

*WE

ERROR*xx*

COMD
0

WAS ERASED.

UNIT NO. @ *xPATTRN
kBN 2 xRN 370 =461

~-25613
BAD

TAPE

REPEAT:

RECOVERED

RETRY:

A WRITE

ERROR

SUCCESSFULLY

=25613

*xxURIGINAL

COMD
WC

SHOWS

WHICH

REWRITTING

FOUR TIMES AT THAT LOCATION,
SUCCESSFULLY WRITTEN AFTER 3

LOGGED

NO., U *PATTRN
2

EXAMPLE

RECOVERED

THE RECORD
RECORD WAS
WILL

D-19

TAPE

THIS ERROR
SPOT,

THE

1
Part
STATISTICS

THE
THE

PRINTOUT

PROGRAM GATHERS A VARIETY OF STATISTICS DURING
COURSE OF ITS TESTING,
THE STATISTICS ARE KEPT

ON A UNIT BY UNIT BASIS AND ARE
STATISTICS PRINTQUT.
STATISTIC
PRINTED

THE

END

EACH

SUMMARIZED IN A
PRINTOUTS CAN BE

BLOCK

CYCLE

SETTING

SWITCH FOUR (4) TO 1,
A STATISTIC PRINTOUT IS AUTOMATICALLY
PRINTED WHEN A UNIT REACHES EQT AND 1S REWOUND,
HERE

DROPS:

EXPLANATION

Tht NUMBER OF
BASIS,
OROPS
CHECK

PICKS:

WTERR:

THE

STATISTIC

SUMMARY,

BITS OROPPED ON A PER TRACK
ARE COLLECTED DURING THE DATA

ROUTINE.

NUMBER

BASIS,

ODROPS

CHECK

ROUTINE.

THE

NUMBER

BITS

PICKED

ARE

COLLECTED

PER

DURING

TRACK

THE

DATA

|
RECORDS

WHICH

WRITE

ERROK

OCCURRED,
IF WRITE RETRY WAS ENABLED, WTERK
wiLL CONTAIN ONLY THOSE RECORDS WHICH WERE
NOT RECOVERED AFTER ONE RETRY,

RTRY:

RDERR:

SOFT:

THE NUMBER OF RETRIES INITIATED UNDER THE
WRITE RETRY OPTION, (SEE ITEM 8,, SWi?)

THE

TOTAL NUMBER OF RECORDS

READ

ERROR

THE

NUMBER

RECOVERED
REREADS

IN WHICH

OCCURRED,

READ

WITHIN
A

ERRORS

WHICH

MAXIMUM
OF

RECORD

UNDER

THE

WERE

FOUR
READ

RETRY

OPTION, (SEE ITEM 8., SW1:)
x*NOTE: SOFT READ ERRORS ARF ONLY CATEGORIZED
FOR THOSE READ ERRORS OCCURRING WHEN CONSOLE
SWITCH 1 IS SET TO ZERO,
HARD:

THE

NUMBER

READ

ERRORS

UNRECOVERED UNDER THE
(SEE ITEM 8., SWi:)
xxNOTES

HARD

READ

WHICH

READ

ERRORS

ARE

SCHEME,

ONLY

CATEGORIZED

WHEN

CONSOLE
|

THE NUMBEK OF DATA ERRORS FOUND FOR THIS UNIT,
x*NOTE:

RECORDS

DATA ERRUORS ARE
WHICH WERE READ

ZERD,

DTERR:

REMAINED

RETRY

FUR THOSE READ ERRORS OUCCURRING
SWITCH {1 IS SET TO ZERO,

10,

ONLY
WITH

FOUND FOR
SWITCH 11

THOSE
RESET

Part I

BAD

TAPE

SPOTS:

WHERE

UNDER

THE

FOLLOWING

LOCATIONS
WHEN

COUNT

RECORD

THE

COULD

WRITE RETRY
THE

COUNT

TAPE

SPOT

DROPS:
PICKS:
WTERR:

RTRY:
RDERR:

SOFT:
¢
HARD

xBN

10
TAPE
16

*RN

SPOTS
44

D-21

TAPE

REWRITTEN

LIST

(SEE
OF

THE BLOCK

WAS

EXAMPLE

DTERR?
BAD
{

OPTION

IDENTIFIED BY

BAD

NUMBER

NOT

ITEM8,,

THE

LOGGED,

SPOTS
SUCCESSFULLY

BAD

SWi:)

TAPE

AND RECORD

NUMBER

Part
11,

AUTO

THE

SEQUENCE

AUTO

SEQUENCE

PREDETERMINED

(START

TEST

PLAN

ADDRESS 240)

ALL

AYAILABLE

WILL

EXECUTE

UNITS,

THE

A
ONLY

OPERATOR RESPONSE REGUIRED IS TO THE TYPED REQUESTS
FOR THE TMA=11*%S ADDRESS AND VECTOR AND CONTINUOUS OR
SINGLE CYCLE,
ALL SWITCHES REMAIN ACTIVE AND MAY BE

USED NORMALLY; HOWEVER, THE INTENT IS TO LEAVE
DOWN AND ALLOW FULL EXECUTION OF THE TEST PLAN
SYSTEM CHECKOUT,
SAMPLE

LOAD

START

ADDRESS

2402(8):%

240(8),

AUTO

SET

ALL
FOR

SWITCHES

SEQUENCE

SWITCHES

ZERO,

PRESS

START:

TMA=11 AUTO SEQUENCE TEST
ENTER RESPONSES IN QCTAL

START = 172528
224 (CR)

CONT:

(CR)

(1)

THIS

EXAMPLE SHOWS AN AUTO SEGUENCE START WITH THE TMA=11
AT BUS ADDRESS 172520 AND A VECTOR OR 224.
ALL AVAILABLE
UNITS WILL BE TESTED CONTINUOQUSLY,

EACH

PASS

COMPLETED

DIVIDER

LINE

ASTERISKS

WILL BE PRINTED FOLLOWED BY AN END OF PASS MESSAGE
INDICATING HOW MANY PASSES HAVE BEEN COMPLETED SINCE
THE AUTO SEQUENCE WAS BEGUN,
AT THE START OF EACH
PASS THE UNITS BEING TESTED ARE PRINTED,
AUTO

SEQUENCE

TEST

PLANG

THE AUTO SEQUENCER WILL EXECUTE A PASS CONSISTING
THE WRITING, READING, AND CHECKING OF SEVERAL
DIFFERENT DATA PATTERNS,
EACH PASS WILL START AT
AND PROCESS AN ENTIRE MAG TAPE BEFORE REWINDING
THE

UNITS

WILL

SET

TRACK FORMAT,
ODD
TAPE MARKS WILL BE
THE

DATA

THREE
EACH
EACH

PATTERNS

FIXED

DATA

WRITE

PARITY WILL
WRITTEN,
WILL

800

BPI

USED

AND

OF
BOT

NINE

FOLLOWS:

PATTERNS:

PATTERN WILL BE USED FOR SIX
BLOCK CONSISTS OF (1@2@) 4000

PATTERN

WALKING

ONE

BIT

PATTERN

ALTERNATING

ONE

PATTERN

113

INCREMENTING

BLOCKS,
CHARACTER

AND

ZERO

CHARACTERS

D-22

RECORDS,

BITS

(0Q0=377)

[
Part
RANDOM

DATA:

FOLLOWING

THE

FIXED

DATA

PATTERNS,

RANDOM

DATA wILL BE WRITTEN IN THE SAME BLOCK STRUCTURE
UNTIL EOT 1S REACHED,
IT 1S IMPURTANT THAT THE TAPE USED FOR THE TEST
BE UF SUFFICIENT LENGTH TO ACCOMODATE ALL OF
THE FIXED DATA PATTERNS AND AT LEAST ONE
RECORD

REWOUND

HAVE

BEEN

RANDOM

UNTIL

DATA;

ALL

OTHERWISE,

THE

DATA

TESTED,

D-23

THE

TAPE

PATTERNS

WILL

[
Part
12.

PROCEDURES

TESTING

PREVIOUSLY

FIXe

STATED

TESTS,

THE

DESCRIBED

THIS

ENTIRE

THE

PROGRAM
TEST

OPERATOR

CONTAINS

CYCLE

THOUGH

NO
EXECUTED

RESPUNSES

TELETYPE
SETTINGS

KEQUESTS FUR PARAMETERS AND CONSULE SWITCH
FOR OPERATION,
THE OPERATION SELECTED wILL

ON EACH
STOPPED

AVAILABLE UNIT, ONE BLOCK AT A TIME, UNTIL
BY THE OPERATOR,
THE OPERATION MAY BE CHANGED

BE EXECUTED WITH THE PARAMETERS ENTERED CONTINUOQUSLY

DYNAMICALLY BY CHANGING THE CONSOLE SWITCHES AT ANY
TIME,
THE PROGRAM WILL ATTEMPT TO PERFORM ANY QOPERATION
SET AND THEREFORE CAUTION SHOULD BE TAKEN TO ASSURE THAT
THE UNIT 1S CAPABLE OF PERFORMING AS REGUESTED.
FOR
INSTANCE, ONE SHOULD NOT ATTEMPT TO PERFORM READ QPERATIONS
ON A TAPE WHICH HAS NOT BEEN WRITTEN AS THE DATA, IF ANY,
IS UNPREDICTABLE,
HOWEVER, IF A TAPE HAS BEEN WRITTEN WITH
THIS PROGRAM, IT CAN BE READ AS OFTEN AS DESIRED WITHOUT
BEING REWRITTEN,
THIS IS A GOOD PROCEDURE TO USE FOR
TESTING TAPE COMPATABILITY.
SCOPING OF TAPE UNITS BECOMES
SIMPLE; BY SETTING THE DESIRED OPERATION AND ITS PARAMETER,
A

UNIT

"BY

MAY

USING

THE

CONTINUOUSLY

VARIOUS

EXERCISED

ERROR

CONTROL

ANY

MANNER

SWITCHES

AND

DESIRED,

ENTERING

THE NEEDED STALL, ANY FUNCTION CAN BE SCOPED RATHER
EASILY,
RELIABILITY TESTING CAN BE PREFORMED BY USE

THE

RANDOM

RKANDOMIZATION

CAPABILITY,

TESTING

FOR

SOME

OROPS

AND

PICKS

PROELEMS

CaN

IN
A

PERIOD

MOTION
HALT

BY
IF

DATA

SOME

STALL

SEE,
BE

IT,

LISTING

THERE

AND

YUU”LL

ARE

MYRIAD

REPORTING
LIKE

IT,

SWITCH

RUN

INTERMITTANT

DESIRED

CAUSED

THE

TEN

PATTERN

OPERATION

WHILE

ALLUWING

HALT

AND

CAN

PRESSING

SHOULD

YOZZLE

SWITCH

AND

ITS

ALLOW

SCOPING

THIS

TESTING

PARAMETERS,

ARE

CYCLE
TO

COLLECTION

PRINTOUTS

DATA

THE

USED

THE

THAT

CONSOLE

ALLOWED

STATISTICAL

SETTING

ERROR

USE

CAN

PERFORMED.,

EXAMINATIUN
TRY

PERHAPS

AND

SIGNIFICANT,

PARTICULAR

ERROR,

KECURD,

YOU

THE

THEN

RESETTING

ASSOCIATED

THE

PARTICULAK

COULD

TIME,

FQUND

ERR{OR,

PRINTED

CAUSING

SET

AND DISALLOWING ERROR

CONTINUE,

13,

MIGHY

ALL

PROCEDURES

WHICH

TAPE

OPERATIONS,

YOUR

DISCRETION,

ERROR

PART 11

TMA11 CONTROLLER

Part 11

CHAPTER 1
INTRODUCTION

1.1

GENERAL DESCRIPTION

The TMAT11 Controller is the interface between the TSO3 DECmagtape Transport and the Unibus. Thus, it controls

command and data transfers between the tape transport and any device connected to the bus, such as the processor
or memory. One controller can handle two TS03 DECmagtape Transports.

Basically, the controller consists of six major registers that have been assigned standard bus addresses and can be
loaded or read by any PDP-11 instruction referring to that address. Four of the registers can be loaded or read from
the bus; the remaining two registers can only be read from the bus.

The controller has three main functions:

handling data transfers, issuing control commands, and monitoring

operation of the system.
During data transfer functions, the controller assembles the data word from the magentic tape and places it on the

bus (read operation), or assembles it from the bus and loads it into the tape transport read/write heads (write
operation)

for

recording on magnetic tape. The commands necessary to perform the specified operation are

generated by the controller under program control.

Normal data word transfers are performed by direct memory access transactions at the NPR level. If the controller is

ready to begin a new function or if an error condition exists, it issues an interrupt request so that it can be serviced
by the program.

In addition to the commands required for data transfers, the controller may issue other commands governing tape

unit selection, direction of tape travel, rewind, space forward, space reverse, write end-of-file mark, etc. The

controller also monitors various functions and provides an indication of error conditions. The status of the

monitored functions is stored in one of the controller registers.
1.2

PHYSICAL DESCRIPTION

The TMAI1 consists of the following:
Logic Assembly

H720 Power Supply*
Two BC11A Cable Assemblies
Power Harness

Priority Jumper Level No. 5

One BC11A cable assembly is used to connect the TMA11 to the TS03 DECmagtape Transport. DC operating power

for the TMA11 is provided by H720 power supply via the power harness.

*1'or a detailed description of the H720 power supply, refer to the H720 Power Supply and Mounting Box Manual, EK-H720-TM-003.

1-1

Part 1]

1.3

SPECIFICATIONS

Environmental
Ambient Temperature

40° to 110° F

Relative Humidity

20% to 95% (without condensation)

Electrical
AC Input Power to H720 Power Supply
TMALI1-A

115 Vac, 50/60 Hz at 6 A, single phase

TMAI11-B

230 Vac, 50/60 Hz at 3 A, single phase

DC Voltage Requirements of TMA11
Controller
Electrical Characteristics

+t5Vatl6A
15V at 10 A

Provided by H720 power supply

Electrical characteristics of controller meet PDP-11 Unibus
interface specifications.

Physical

Size

TMALI

5-1/4 in. high, 19 in. wide

H720 Power Supply

8-1/2 in. high, 16-1/2 in. wide, 5-1/2 in. deep

Mounting

TMAIL 1

Mounts in standard 19 in. rack

H720 Power Supply

1-2

Part 11

CHAPTER 2
PROGRAMMING INFORMATION

2.1

SCOPE

This chapter presents general programming information for software control of the TMA11 Controller. Although a
typical program example is included in this chapter, it is beyond the scope of this manual to provide detailed
programs. For more detailed information on programming in general, refer to the Paper-Tape Software Programming

Handbook, DEC-11-XPTSA-A-D.
This chapter of the manual is divided into four major portions: device registers, interrupts, programming note, and

program example.

2.2 . DEVICE REGISTERS
All software control of the TMA11 Controller is performed by means of six device registers within the controller.
These registers have been assigned bus addresses and can be read or loaded using any PDP-11 instruction that refers
to their address. The six device registers and associated addresses are listed in Table 2-1. Note that these addresses
can be changed by altering the jumpers on the M105 Address Selector module. However, any DEC programs that
refer to these addresses must also be modified accordingly if the jumpers are changed.
Figures 2-1 through 2-7 show the bit assignments within the six device registers. Except in the case of the data buffer

register, the unused and load-only bits are always read as Os. Loading unused or read-only bits has no effect on the
bit position.

The mnemonic INIT refers to the initialization signal issued by the processor. Initialization is caused by: issuing a
programmed RESET instruction; depressing the START switch on the processor console; or occurrence of a
power-up or power-down condition of the processor power supply.

The INIT sighal clears the entire system; however, the INIT signal produced by a RESET instruction does not clear
the processor. Clearing only the TMA11 Controller and the TSO3 tape units can be accomplished by loading a 1 into

bit 12 (Power Clear) of the command register (MTC).

NOTE

INIT and Power Clear deselect the current tape unit and select
tape unit 0. Also, a rewind operation in progress continues to

the load point.

2-1

Part 1T
Table 2-1

Standard Device Register Assignments

Mnemonic*

Address

Status Register

MTS

772520

Command Register

MTC

772522

-MTBRC

772524

Current Memory Address Register

Byte Record Counter

MTCMA

772526

Data Buffer Register

MTD

772530

TS03 Read Lines

MTRD

772532

*First two letters of mnemonic (MT) refer to magnetic tape control; the remaining letters represent the mnemonic of a specific register.

2.2.1

Status Register (MTS)

ILC

EOF | CRE|

PAE | BGL | EOT | RLE | BTE | NXM | SELR|

BOT | 7CH

|SDWN | WRL | RWS | TUR

11-0430

Figure 2-1 Status chister (MTS) Bit Assignments
Bit

Meaning and Operation

ILC — Illegal command bit. This b1t is set whenever one of the following illegal commands
occur:

Any DATO or DATOB transfer to the command register (MTC) during tape
operation (CU RDY bit clear). The register cannot accept a new command whlle
in the process of executmg a previous command.

A write, write end-of-file, or write-with-extended-interrecord-gap (command
register functions 2, 3, and 6, respectively), when the WRL (write lock) bitiis set.
Writing iis inhibited with WRL set, and write commands are illegal.

Any command to a tape unit that has its SELR bit clear, because SELR clear
indicates that the unit is not on-line.

Any time the SELR bit becomes O during any operation except off-line, it sets

the ILC bit, because no command can be issued to a unit that is not on-line.

If any of the illegal commands listed in 1. through 3. above occur, the command is loaded
into the command register.

In all of the above cases, the ILC bit and the ERR bit (bit 15 in the command register) are
set simultaneously.

Cleared by INIT or by the GO pulse to the tape unit.

2-2

Part 11

Meaning and Operation

Bit
14

EOF — End-of-file bit. An end-of-file (EOF) character is detected during a read, space
forward, or space reverse operation. During the read or space forward operations, the EOF

bit is set after the EOF and LRC characters are read. During a space reverse operation, the
EOF bit is set after the LRC and EOF characters are read. The ERR bit (bit 15 in the

command register) is set when the LRC character following the EOF character is detected. It
is also set during WRITE EOF command.

The EOF bit is set only by the TS03 logic;
it is cleared by INIT or by the GO pulse to the
tape unit.

The EOF character is loaded into memory during read operations.
13

CRE - Cyclic redundancy error bit. A cyclic redundancy error can be detected during either
a read or write operation. This check compares the CRC character written during a write or a

write-with-extended-IRG

operation with the

CRC

character generated

during a read

operation.

If the two CRC characters are not the same, the CRCE from the tape unit becomes a 1,
forcing the CRE bit to a 1. The ERR bit in the command register, however, is not set until
the LRC character is detected.

Cleared by INIT or by the GO pulse to the tape unit.

PAE — Parity error bit. When set, this bit indicates that a parity error exists. The PAE bit is

the logical OR of both vertical and longitudinal parity errors.

A vertical parity error is indicated on any character in a record; a longitudinal parity error

occurs only after the LRC character is detected.

A vertical parity error does not affect the transfer of data. In other words, the entire record
is transferred to the tape during a write operation or transferred into memory during a read

operation.
Both

vertical

|
and

longitudinal

parity

errors

are

detected

during read,

write,

and

write-with-extended-IRG operations. The longitudinal parity check is made on the entire
record, including the CRC and LRC characters.

A longitudinal parity error occurs when an odd number of 1s is detected on any channel in

the record. A vertical parity error occurs when an even number of 1s is detected on any

character, provided the PEVN bit (bit 11 in the command register) is clear, or if an odd

number of 1s is detected when the PEVN bit is set.
When a parity error occurs, PAE is set, and the ERR bit (bit 15 in the command register) is
set after the LRC character has been detected.
Cleared by INIT or by the GO pulse to the tape unit.

2-3

Parr 11

Bit

Meaning and Operation
BGL — Bus grant late bit. If the controller issues a request for the bus and does not receive a

bus grant before it must issue another bus request for the following tape character, a bus
grant late error occurs.

This error condition is tested only for NPRs (non-processor requests). The BGL bit is set if

an NPR bus request is not honored before the controller receives a WRS pulse for a write
operation or an RDS pulse for a read operation.

The BGL bit and the ERR bit (bit 15 in the MTC) are set simultaneously, halting the

operation.

If the BGL error occurred during a write

or write-with-extended-IRG operation, the

controller negates the WDR signal to the master tape unit, inhibiting the write operation.

Cleared by INIT or by the GO pulse to the tape unit.
10

EOT — End-of-tape bit. The EOT bit is set as soon as the EOT marker is detected when the
tape is moving in the forward direction. It is cleared as soon as the EOT marker is detected
when the tape is moving in the reverse direction.

The EOT is an error condition if the tape is moving forward. Therefore, when EOT is set, the
ERR bit is also set when the LRC character is read.

Cleared by tape transport head passing over EOT marker when tape is moving in the reverse
direction.

RLE —

Record length error bit. The record length error is tested only during read

operations. An error is indicated as soon as the byte record counter (MTBRC) attempts to
increment beyond 0.

When a record length error occurs, the RLE bit is set, incrementation of the MTBRC and the
current memory address register (MTCMA) ceases, and the ERR bit is set when the LRC
character is read.

The CU RDY (bit 07 of the command register) remains cleared until TUR (tape unit ready)
asserts, at which time CU RDY is set.
Cleared by INIT or by the GO pulse to the tape unit.

If the exact record length is desired after the occurrence of a record length error, it can be
found by setting the MTBRC to a value so large that an RLE is not generated and then

re-reading the record. Record length can be derived by subtracting the current value of the
MTBRC from its initial setting.

Part 11

Meaning and Operation

Bit

BTE/OPI — Bad tape error/operation incomplete bit. A bad tape error occurs when a

character is detected (RDS pulse) during a gap shutdown or settle down period for any tape
function except rewind.

During write, write EOF, or write-with-extended-IRG operation, a bad tape error sets both
the BTE/OPI and ERR bits immediately on detecting the error.

During both read and space forward or space reverse operations, the BTE/OPI bit is set
immediately on detection of bad tape.

During a read operation, the MTBRC increments continuously, and words are read into

memory until the MTBRC overflows. During a space operation, the MTBRC stops
incrementing as soon as BTE occurs. When BTE is discovered, the tape unit stops, regardless

of the state of the MTBRC.
Because it is not possible to artifically generate bad tape, bad tape may be indicated by

setting the CU RDY bit prematurely, thereby producing the gap shutdown period while the
data is still being read. The CU RDY bit is set by loading a 1 into bit 13 of the MTRD. If bit
13 of the MTRD is set during a record for either a read or write operation, a bad tape error
indication occurs.

Any initiated tape operation, other than a REWIND or OFF-LINE command, that does not

detect an LRC character within 7 seconds results in setting the BTE/OPI bit. This 7-second
time-out is called Operation Incomplete. Any legal size record with a legal size gap results in

detection of an LRC character within 7 seconds. During a spacing operation, the OPI timer is
restarted at each interrecord gap. When the 7-second time-out occurs, the tape unit in

operation is RESET by CINIT. The BTE/OPI bit is set and, at TUR, the CU RDY bit is set.
Cleared by INIT or GO.
07

NXM — Non-existent memory bit. This error condition occurs when the controller is bus

master during NPR transfers and does not receive an SSYN response within 10 us after
asserting MSYN.

The NXM bit and the ERR bit are set simultaneously, halting the operation.
Cleared by INIT or by the GO pulse to the tape unit.

SELR — Select remote bit. The SELR bit is set when the tape unit has been properly

selected. The SELR bit is O if the tape unit that is addressed does not exist (UNIT SELECT
setting does not correspond to SEL bits), if the selected tape unit is off-line (ON LINE
indicator extinguished), or if the tape unit power is off.
05

BOT — Beginning-of-tape bit. The BOT bit is set as soon as the BOT marker is detected.
When BOT is set, it has no effect on the ERR bit. The BOT bit remains cleared whenever the
BOT marker is not being read.

This bit is set and cleared only by the TS03.

2-5

Part 11

Meanihg and Operation

Bit

7CH — 7-channel bit. This bit is always cleared because the TS03 is a 9-channel unit.
SDWN — Settle down bit. The settling down period is provided to allow the tape to fully

stop prior to starting a new operation. This settling down period sets the SDWN bit. When

the tape unit stops, SDWN is cleared and the tape unit ready (TUR) bit is set.

During a tape reverse operation (this does not include rewind operations), the gap shutdown
period begins immediately after the first gap encountered after spacing over a record.
WRL — Write lock bit. The write lock bit is under control of the tape transport. When set, it

prevents the controller from writing information on the tape.

RWS — Rewind status bit. This bit is under control of the tape unit. It is set at the start of a

rewind operation and clears as soon as the rewind sequence is complete.

TUR — Tape unit ready bit. This bit is under control of the tape transport. Whenever the

selected tape unit is being used (such as rewind), this bit is cleared. When the tape unit is
stopped and ready to receive a new command, the tape transport sets the TUR bit.
NOTE

Status register bits 00-03 and 05 are cleared or set by the tape
transport, not the controller.
2.2.2

Command Register (MTC)

15
ERR

DEN | DEN | PWR
8
5
CLR

11
PEVN

SEL
5

SEL | SEL
1
0

o7
CcuU
RDY

06INT
ENB

ADRS | ADRS | FCTN | FCTN | FCTN

BIT
17

BIT
16

BIT
2

BIT
1

BIT
0

00
GO

11-0431

Figure 2-2

Bit

Command Register (MTC) Bit Assignments

Meaning and Operation

ERR — Error bit. Indicates an error condition that is the inclusive OR of all error conditions

(bits 15 — 07 in the status register, MTS). Causes an interrupt if enabled (see bit 06). The
ERR bit is not set for some errors until the longitudinal redundancy check (LRC) character
is read, in order to allow the current operation to be completed. Specific error conditions are
described in the status register bit assignments (Figure 2-1).
When ERR is set, it sets bit 07 (CU RDY) when the tape unit asserts TUR. Cleared by INIT
or by the next GO command (bit 00).

2-6

Part I

‘Meaning and Operation

Bit

DEN 8 — Density bit. This bit, in conjunction with bit 13, selects the bit packing density of

~ the tape. These combinations are shown below.

Bit14

Bit13

Density

- (DENS)

(DEN 5)

(bits/inch)

200

556

7-channel tape (See Note).

800
800

9-channel tape (TS03)

NOTE

TSO03 ignores bits 14 and 13; it always operates at 800 bpi,
9-channel.

DEN § — Density bit. This bit, in conjunction with bit 14, selects the bit packing density of
the tape. See bit 14 for combinations.

PWR CLR — Power clear bit. When a 1 is loaded into this bit position, it clears the controller
logic and all tape units. This bit becomes a 1 for us during a processor DATO cycle, provided
the corresponding bit on the bus isa 1. Always read by processor as a 0.

PEVN
— Even parity bit. This bit is set whenever the selected tape unit is to write or read

even vertical parity on or from the tape. The bit is O whenever the selected tape unit is to
write or read odd vertical parity on or from the tape.
A search for a parity error is made whenever the tape moves. The controller ignores parity

errors during space forward, space reverse, or rewind operations.

Cleared by INIT Or by loading with a 0.
10—-08

SEL — »Tape unit select bits. These three unit select bits specify the number of the tape unit
that is to function as the unit under program control. These three bits (SEL 2, SEL 1, and
SEL 0) are set or cleared to represent an octal code that corresponds to the unit number of
- the tape unit to be used. The TS03 master tape transport recognizes octal codes 000 and 001
only.

Cleared by INIT or by loading with a 0.
07

CU RDY - Controller ready bit. When set, indicates that the TMA11 Controller is ready to

receive a new command. This bit is set at the end of a tape operation (indicating that a new

operation can be started) and is cleared at the beginning of a tape operation (indicating that
the controller is not ready for new commands). Refer to Paragraph 2.4.1 for CU RDY
operation during a rewind sequence.

This bit is also set (indicating CU RDY) whenever ILC (bit 15 of MTS) is set or whenever
INIT is generated.

2-7

Part 11

Meaning and Operation

Bit

INT ENB — Interrupt enable bit. This bit, when set, allows an interrupt to occur, provided
either CU RDY (bit 07) or ILC (bit 15 of MTS) is set. With INT ENB set, a REWIND
command can cause two interrupts — one at initiation and one at completion.

An interrupt also occurs whenever an instruction sets the INT ENB bit but does not set the

GO bit (bit 00). Interrupts are described in Paragraph 2.3.

Cleared by INIT or by loading with a 0.
ADRS BIT 17 — Extended bus address bit 17. Used to specify address line 17 in direct

memory transfers. Increments with the current memory address register (MTCMA). Cleared
by INIT.

ADRS BIT 16 — Extended bus address bit 16. Function is the same as ADRS BIT 17 (bit 05

above).

FUNCTION — These bits specify a command to be performed by the selected tape unit.

03—-01

These functions are:

Function Bits
OctalNo.

Function

Read

Write

Write end-of-file

Space forward

~ Space reverse

- Write-with-extended-IRG

Off-line

Rewind

All function bits cleared by INIT. Table 3-1 describes each function.

GO — Loaded with a 1 from the bus to initiate the function selected. Clears CU RDY bit.

Cleared when GO pulse is sent to tape transport. Normal time duration of bit is 1 us, but this
time may extend to as long as several minutes when the bit is loaded for a tape unit in the
process of rewinding.
Also cleared by INIT or whenever ILC in the status register is set.

2.2.3

Byte Record Counter (MTBRC)

2's

COMPLEMENT OF NUMBER OF BYTES

(OR RECORDS) TO BE COUNTED
11-0432

Figure 2-3

Byte Record Counter (MTBRC) Bit Assignments

2-8

Part 11

Bit

Meaning and Operation

Contains the 2’s complement of the number of bytes or records to be transferred. The

15-00

desired value is loaded by the program on a processor DATO. Cleared by INIT. Increment by
1 after each memory access.

- The byte record counter (MTBRC) is a 16-bit binary counter used to count bytes in a read
- or write operation and used to count records in space forward or reverse operations.
When used in a write or write-with-extended-IRG operation, this register is set by the
program to the 2’s complement of the number of bytes to be written on the tape. After the

last byte of the record has been strobed from memory, the MTBRC becomes 0. Thus, when
the next write strobe signal is received from the master tape transport, the controller lowers

the write data ready line to indicate to the master transport that there are no more data
characters in the record.
When used in a read operation, the MTBRC is set to a number equal to or greater than the

2’s complement of the number of words to be loaded into memory. A record length error,
which occurs for long records only, occurs whenever a read pulse is generated after the

MTBRC is at 0. Neither the CRC or LRC character is loaded into memory during a read
operation, although both characters are checked for parity errors.

When used in a space forward or space reverse operation, the MTBRC is loaded with the 2’s
complement of the number of records to be spaced. The counter is incremented by 1 at LRC
time, regardless of tape direction.

2.2.4

Current Memory Address Register MTCMA)

BUS

ADDRESS
11-0433

Figure 2-4

Current Memory Address Register (MTCMA) Bit Assignments

Bit

15-01

Meaning and Operation
These bits specify the bus or memory address to or from which data is to be transferred
during write or read operations. Only bits 01—15 of the MTCMA are accessible by the
program, although bits 00—15 participate in NPR transfers. The MTCMA contains 16 of the

possible 18 memory address bits. The remaining two bits (16 and 17) are part of the
command register.

Before issuing a command, the program loads the MTCMA with the memory address that is
to receive the first byte of data (read operation) or with the memory address from which the

first byte is to be taken (write operation). After each memory access (read or write), the
MTCMA is immediately incremented by 1 (the next byte boundary). Therefore, at any given
time, the MTCMA points to the next memory byte address that is to be accessed. On

completion of the record transfer, the MTCMA points to the address plus 1 of the last
character in the record.

2-9

Part I1
Bit

Meaning and Operation

15—-01 (Cont)

If a bus grant late (BGL) or non-existent memory (NXM) error occurs, the MTCMA contalns
the address of the locationin which the failure occurred.
If an 18-bit memory address is required, the program loads the appropriate address into bits

- 01—15 of the MTCMA and into extended address bits 16 and 17 of the command register.
The extended address bits are a logical extension to the MTCMA register and participate in
any required incrementation.

2.2.5

Data Buffer Register (MTD)

PARITY

00
DATA
11-0434

Figure 2-5 Data Buffer Register (MTD) Bit Assignments
Bit

Meaning and Operation

15-09

Correspond to bits 07—01 ‘respectively on a processor DATI cycle (e.g., bit 15 =bit 7, bit 14

(not shown)

= bit 6).

Corresponds to the parity bit on the magnetic tape. During a processor read operation, this
bit is stored in memory; during NPR operations, this bit is read by the controller but not
loaded into memory. During operation of a nine-channel tape unit, this bit is valid only after
the CRC character has been read, provided bit 14 of the MTRD is a 1.

NOTE

The parity bit is generated by the TS03 master tape transport,
not by the controller. However, the polarity of the parity bit

(odd or even) is determined by the PEVN bit in the command
register.

07-00

During read operations, these bits are used for temporary storage of characters read from
tape pror to loading into memory. During write operations, -these bits are used for
temporary storage of data from memory before writing on tape.

During read operations, the LRC character enters the data buffer when bit 14 of the address
location for the TSO3 read lines is a 1; the LRC character is prevented from entering the data
buffer when bit 14 is a 0. Thus, after reading a nine-channel tape, the data buffer contains an

LRC character (if bit 14 is a 1) or a CRC character (if bit 14 is a 0). After reading an EOF

character, the data buffer contains elther all Os (bit 14 is a 1) or the EOF character (bit 14 is
a 0).
The data buffer can store only bytes; therefore, two bus cycles are required to transfer a

word. During NPR operation, the data bits are written into or read from alternate low and

high byte positions. The relationship between tape characters and high and low memory
byte characters is shown in Figure 2-6.

2-10

Part 11
15

5
L

R EAHDE/XIJ)RlTE

TAPE MOTION —»

Figure 2-6

2.2.6

1H-2061

Relationship Between Tape Characters and Memory Byte Characters

TS03 Read Lines (MTRD)

15
TIMER|

14
CHAR|
"B

BTE
CEN

GAP
gg\%

09
UNUSED

08
|1

00
DATA

11-0435

Figure 2-7 TS03 Read Line (MTRD) Bit Assignments
Bit

Meaning and Operation

TIMER — The timer bit is used for diagnoStic purposes by measuring the time duration of the tape operations. The timer signal is a 100 us signal with a 50 percent duty cycle and is
generated by the controller. Itis read as bit 15in the memory location reserved for the TS03
read data lines. This is a read-only bit. Sée Paragraph 5.9.4 in Part I of this manual for the
timer adjustment procedure.

CHAR SEL
— This bitis used to select the last character of a record thatis to be loaded mto

the data buffer. Thisis a read/write bit. Selectlonis as follows:

Set

LRC character

Clear

CRC character

BTE GEN — Bad tape error generator bit. Bad tape cannot be artifically generated. When set,

this bit sets the CU RDY bit. With CU RDY set, a premature gap shutdown is generated,
which produces a bad tape error indication when data
is read during this period. This is a
write-only bit.
12

GAP SHUTDOWN — When set, indicates a gap shutdown period. This is a read-only bit.

11-09

Unused.

PARITY — Corresponds to the parity bit read from the tape by the TS03 tape transport.
Used in conjunction with bits 07—00 to indicate a longitudinal parity error. After a read or
write operation, bits 08—00 should all be 0. If one or more of these bits remains a 1 after the
operation is complete, it indicates a longitudinal parity error. The bit position contammg the
1 indicates the tape channel contammg the error. Thisis a read-only bit.

Part 11

Bit

07-00

Meaning and Operation

DATA — These bit positions contain information read from the magnetic tape transport.
After these ppositions are read by the processor, all bit positions clear unless a parity error
exists.

Bits 07—00 in the read lines correspond to tape channels 00—07, respectively. These are
read-only bits.

2.3

INTERRUPTS

The TMA11 Controller uses NPR or BR interrupts to gain control of the bus in order to perform data transfers or to
cause a vectored interrupt, thereby causing a branch to a handling routine. The NPR requests are used for direct
memory access whenever it is desired to transfer data between memory and the data buffer register without

processor intervention. The BR requests are made when processor servicing is required for completed operations or
error conditions.

2.3.1 NPR Requests
The TMA11 Controller issues an NPR request whenever it is necessary to transfer data between memory and the
data buffer register. During a read operation, the direction of transfer is from the data buffer to the core memory.
The RDS pulse (read strobe from master tape transport to controller), which is used to strobe data from the tape
transport into the data buffer register, generates the NPR request. When the request is granted, the TMAI11

Controller performs a DATOB bus cycle and transfers information from the data buffer into memory.
During a write (or write-with-extended-IRG) operation, the NPR request is generated by the write strobe (WRS)
pulse from the transport. When the request is granted, the controller performs a DATI bus cycle and transfers a byte

from core memory into the data buffer register.

During both read and write operations, the address in memdry that data is read from or loaded into is determined by
the value in the current memory address register (MTCMA).
2.3.2

BR Requests

A BR interrupt can occur only if the interrupt enable (INT ENB) bitin the command register is set. With INT ENB
set, setting the CU RDY bitin the command register or completing a rewind operation initiates an interrupt request.
When CU RDY is set, it indicates that the controller is ready to perform another command.

When ERR is set, it indicates that some type of error condition exists. In this case, an interrupt is used to cause the
program to branch to an error handling routine.
If a function command is issued with the GO bit cleared and INT ENB set, an interrupt is initiated.
If the selected tape unit (as indicated by the SEL bits in the command register) completes the rewind operation

before a new command to that unit is received and INT ENB is set, an interrupt is initiated.

If the interrupt is enabled (INT ENB set) and selection of the tape unit is not changed (as indicated by the SEL bits),
then a rewind command causes two interrupts:

an interrupt when the rewind function begins, and an interrupt

when the tape unit completes the rewind function. If, however, the tape unit is already at the BOT marker When
rewind is issued, only one interrupt occurs.

The interrupt priority level is BR5, and the interrupt vector address is 224. Note that the priority level can be
changed by the priority chip on the G736 module, and the vector address can be changed by jumpers on the M7821

Interrupt Control. However, any DEC programs or other software referring to the standard level or address must also
be changed if the jumpers are changed.

2-12

Part 17

2.4

PROGRAMMING NOTES

In normal programming practice, no attempt should be made to modify one record in the middle of a file. This
practice could result in overwriting the boundary of the record and destroying part of the next record. Also, a read
operation should never directly follow a write operation without at least one intervening tape move operation. This
prevents generating a BTE/OPI if the previous operation involved the last record on the tape. If it is desired to read a
record that was just written, a space reverse command should be issued before the read command. New commands
are issued only when CU RDY is set, which is true after interrupts.

Attempting to write an all-O character with even parity causes the O character to be converted to a tape character of
20. When reading this character from tape, a 20 is read instead of a 0.

ASCII standards provide for a 25-ft trailer following the end-of-tape marker. This allows approximately 10 ft of

writing space after passing EOT. Care should be taken when attempting to write past the EOT marker if the operator
is not familiar with the tape that he is working with, because after a tape has been used, the reflective markers are
often changed, possibly decreasing the length of the standard 25-ft trailer.

A backspace or REWIND command issued while the tape is at the load point will cause an immediate interrupt
provided the INT ENB bit is set.

2.4.1

Rewind Operation

Assume transport 0 is to be rewound. The command to rewind transport O is issued to the controller. At this time,
the master tape unit asserts bit 01 (RWS) in the status register. If bit 06 (INT ENB) in the command register was set

at the start of the rewind operation, an interrupt occurs from the TMA11 Controller as soon as bit 07 (CU RDY) of
the command register has been set by RWS. This informs the program that the controller is ready to accept a new

command. By testing bit 01 (RWS) in the status register, the program can determine if this interrupt was issued as a
result of transport 0 completing its rewind operation or just beginning it.

Transport O, still moving in the reverse direction, passes over the reflective marker, reverses its direction, and
proceeds in the forward direction to the load point. Upon sensing the reflective marker while proceeding in the

forward direction, transport 0 halts tape motion, asserts bit 03 (SDWN), allowing the tape to fully stop, and then
sets bit 00 (TUR) in the status register.

An interrupt is issued coincident with bit 00 (TUR) being asserted in the status register, providing the following
conditions have been met.
1.

Bit 06 (INT ENB) in the command register is set.

The drive has not been deselected by changing the status of bits 10—08 in the command register since
issuing the REWIND command.

If multiple transports are used, it is not necessary to wait for

a REWIND command to be completed on one

transport before switching to another. After a REWIND is issued, another transport can be switched to as soon as
RWS is set.
When operations on the second transport have been completed, a switch to the rewinding transport can be made as

soon as SDWN or TUR is true on the second transport (so the status bits will be from the rewinding unit). Only the
unit select bits in the command register have to be changed to the unit that is rewinding to get its status. If the

rewind is complete when the unit is selected, TUR is set in the status register. If the RWS bit is still set, the software
can either work on another transport or wait until the rewind is completed.
to S minutes to complete.

2-13

A REWIND command may take from 3

Part I1

2.4.2

New Drive Selection

Figure 2-8 is a flowchart for new drive selection.

START NEW
OPERATION

NEW UNIT =

YES

OLD UNIT
?

LOAD NEW UNIT #
AND CLEAR INT.

ENB.

DELAY > 28 us |

ERROR

LOAD NEW
COMMAND
AND INT. ENB.

11-2673

Figure 2-8

New Drive Selection Flowchart

2-14

Part 11
s

2.4.3

Error Handling

2.4.3.1

Write Operations

Mnemonic

ILC

Error

Correction

Illegal command

If SELR (bit 06 of MTS) is not set to a 1 or WRL (bit
02 of MTS) is set to a 1, then operator intervention is
required

ensure

that

the drive to be used is

properly selected and is not write locked.

If SELR (bit 06 of MTS) is set to a 1 and WRL (bit
02 of MTS) is not set to a 1, then a command has

been issued while CU RDY (bit 07 of MTC) was
cleared. Try the operation again, ensuring that CU
RDY is set before issuing a new command.
EOF

End-of-file

N/A

CRE

Cyclic redundancy error

Backspace and try operation again with extended IRG.

PAE

Parity error

Backspace and try operation again with extended IRG.

BGL

Bus grant late

Backspace and try operation N times.

EOT

End-of-tape

The reflective marker signifying the end of tape has been

passed. Operations past this point are not illegal; however,
they

are

not

recommended

unless

the

programmer

familiar with the tape being used and is knowledgable about
the length of tape existing past the EOT marker. Con-

ducting any write operations past the EOT marker leaves
the programmer open to the possibility of running the tape
off of the reel.

RLE
BTE

Record length error

N/A

Bad tape error/operation

Regain a known tape position and try the operation again

incomplete

with extended IRG.

NOTE
A known tape position refers to BOT,
header records, or EOF marks.
NXM

Non-existent memory

Resolve the memory discrepancy and try the operation

again.

2-15

Part 11

2.4.3.2

Read Operations

Mnemonic

ILC

Error

Illegal command

Correction

If SELR (bit 06 of MTS) is not set, then operator

intervention is required to ensure that the drive to be
used is properly selected.

If SELR (bit 06 of MTS) is set, then a command has

been issued while CU RDY (bit 07 of MTC) was
cleared. Try the operation again ensuring that CU
RDY is set prior to issuing the new command.

EOF

End-of—file

The characters signifying the end of a file have been read.

CRE

Cyclic redundancy error

Backspace and try the operation N times.

Parity error

Backspace and try the operation N times.

BGL

Bus grant late

Backspace and try the operation N times.

EOT

End of tape

The reflective marker signifying the end of tape has been

PAE

passed. Continue only if it is certain that an EOF mark
exists after the EOT marker, or the tape will run off of the

reel.
Record length error

‘RLE

Reset the MTBRC to a value that is equal to or greater than
the number of bytes in the record, backspace, and try the

operation again.

BTE/OPI

Bad tape error/operation

Regain a known tape position and try the operation again.

incomplete

If, after doing so, the condition still persists, the data from

the failing point to the next known tape position is lost.
NXM

Non-existent memory

Resolve

the memory location discrepancy and try the

operation again.

2.4.3.3

Write End-of-File Operation

Mnemonic

BTE/OPI

Correction

Error

Bad tape error/operation

Regain a known tape position and try the operation again.

incomplete

2-16

Part 11

2.4.3.4

Spacing Operations
Correction

Error

Mnemonic
ILC

[llegal command

EOF

End of file

Same as read operation.

The characters signifying the end of a file have been read.
Detection of the EOF marks stops a spacing operation even
if the MTBRC is not equal to zero.

EOT

BTE/OPI

End of tape

Same as read operation.

Bad tape error/operation

Regain a known tape position and try N times.

incomplete

2.4.3.5 Write-With-Extended-IRG Operation — Same as write operation.

2.4.3.6 Rewind Operation — Once a rewind operation is started, it continues until complete, regardless of errors or
unit deselection.

2.5

PROGRAM EXAMPLE

The following program example is used to write a 1000-byte record, backspace, read the recdrd, and compare data.
MYC=172522
MTBRC=177524

203272
221294
283,418
231412

"26347

;CURPENTY

RECORD
CLR

e
uyY

TST3

MTC

.-4

171572

RUR

MYS
, "4

391152

171579

aCcC
MOV

712767

176232

171479

MOV

221234

712747

P60225

17146

MOV

H6DD75,MTC

294242
231246

1057487
122375

171454

TSTH

MYC

ap|,

.-4

221252

”12787

201295
221264

742767

177777
769013

221122

712767

WRITTEN,

793122

176232

?12747

260273

031114

125767
123375

171472

2211280

w3112
221126

712729

2211572

7127721

233122

7222?21

221134

201423

201136

XXl

221142

n27a27

031144

222772

221146

T02070

201152

TR0

7283122

231297

222070
7200721

NOW

BACKSRPACE

#el,TBRC

MOV

#62213.4M7C
MTC

3PL

;NOW

171426
171416
171476

MTCMA

#1022, ,“TRARC

Mgy

TST8

171432

231126

221132

171446

1714306

BWBUF

READ

RECOR{

INA,

WALT

IN®~,

WAlY

118 TAPE UNIT READY?

712767

118 COMTRQOL JNIT READY?

193375

2212379

ADNRESS

JSLEAR COMMAND REGISTER, A[LSC SELECTS UNIT #7

281216

221272

COUNTER

MEMZRY

=122¢
yWRITE

171516
1715172

221222
221226

125767
120375

RECQJRD

13YTF

MTCMAS172526

7312720

795057
135767
122375

jSTATYS REGISTER
JCOMMAND REGISTER

MYS=2472529¢

172523
172522
172524
172526

.~4

MOV

#RBUF ,MTCMA

MOV
MOV

#1070, ,#TRR"
W+ MTC
#6QY23

TSTB

MYC

ROL

, =4

MOV

%1
#RBUF,

cMP
REQ

(BY+, (1)+
,+4

JINMITIALIZE MTCMA J]TH BJFFER AREA T BE WRITTEN
PINMITIALIZE

8YTE CAUNTY

11S

FONTR)YL

JUNIT

INC,

WALTY

JSFLECT UNIT #2, 872 BPI, WRITE,
READY,

ISSUE GO

INDICATING

COMPLETION

WRIVE?

JINITIALLIZE BYTE CAUNTY T QATKSPACE 1 RECORD

} ISSUE BACKSPACZE CCMMAND
118 ZONTROL UNIT READY, INAIrATING COMPLETIOM 2F BACKSPAZE?
PN, WalT

JINITIALIZE MTCMA WITH BUFFES AREA TO RE REAT

INTD

PINITIALIZE BYTE C3UNTY

JSELFCT UNIT 22,
118 CONTRIOL JNIT
IN®, WALT

822 BPI, RgAD, ISSUE CGC
READY, INDICATING COMPLETION

OF REAT?

JCOMPARE DATA READ WITH DATA WRITTFN
, %2
#WBYF
JUSE REGISTERS 2,1 AS BUFFER PSINTERS FQOR CQMPARISCN
MOV
Cii

HALT

223122

CMP

7,
%Dy RABUF+122

BLT

KALT

W3UF 3

RBUF !

”

, SWBUF+12082,
¢
(END

J1S TATA WRITTEN = JATA READ?
JYES
INC, HAVE

OATA ERROR
(FINISHED COYPARISON OF RUFFER?

1N2
JYFS,

EXAMPLE

COMPLETED

INRITE BUFFER BEGINS HERE
JRFAN RUFFER BEGINS HWERE

Part IT

‘

CHAPTER
3

THEORY OF OPERATION

3.1

INTRODUCTION

This chapter provides a detailed description of the TMA11 Controller and consists of three major parts: functional
description of overall controller operation, block diagram description of major components, and detailed description
covering controller logic circuits. The discussions in this chapter are supported by a complete set of engineering

drawings located in a companion volume entitled TMA 11 DECmagtape System, Engineering Drawings.

The TMA11 Controller may be divided into six functional areas: selection logic, bus control logic, register logic,
tape control logic, read/write logic, and error logic. Parity logic is part of the Master Tape Transport and is,
therefore, only covered in general in subsequent discussions. The purpose of each of the controller functional units is
as follows:

Selection Logic

| DetermineS,if the controller has been selected as a bus slave device, and what
- type of operation (read or write) has been selected. Permits selection of one of
six internal registers for use and determines if the register is to perform an input
or output operation.

Bus Control ngic

Permits the controller to gain bus control either by means of an NPR for
transferring data or by means of a programmed interrupt to request service by

the program because an error condition exists, because the controller is ready to
perform a new operation, or because the controller is ready to make a direct
memory access transfer (NPR transfer).
Register Logic

Six

internal

registers,

addressable

by the

program, provide

data

transfer

functions, command and control functions, and status monitoring functions for
the TMA11 Controller.

~ Tape Control Logic

Cont'rols, selection of tape' unit, direction of tape travel (forward, reverse), and
function to be performed such as rewind, write, read, space forward, and space
reverse.

Read/Write Logic

Controls assembly, disassembly, and transfer of data between the magnetic tape
and the Unibus. Counts number of words in transfer and keeps track of current

bus address.
Error Logic

Monitors controller operation and provides an indication of any error condition

that arises. Stops the operation and issues an interrupt request for most error

conditions.

)

3-1

Part IT
3.2

FUNCTIONAL DESCRIPTION

The prime function of the TMA11 Controller is to control transfers of information so that digital data can either be

taken from the bus and recorded on magnetic tape (write operation) or read from the magnetic tape and transferred
to the bus for use by another device such as memory (read operation). In addition, the controller performs tape
transport selection, tape positioning, tape formatting, and system monitoring functions.

The controller contains a command register, which allows the program to specify desired operations by loading
control data (transport selection, packing density, function, etc.) into the register. System status information
- (end-of-tape, errors, tape unit ready, etc.) is loaded into a status register, which can be read from the bus.

The TMA11 Controller controls two magnetic tape transports. Although both tape units may be simultaneously
rewinding, data transfers may take place with only one transport at any given time. The basic functions performed
by the controller are: off-line, read, write, write EOF, space forward, space reverse, write-with-extended-IRG, and

rewind. Each of these functions is briefly described in Table 3-1.

| Table 3-1
Controller Functions
Number

Function

Description

'Off-Li’ne

The off-line function is used when it is desired to return
control to the tape transport so that tape can be rewound

reels changed, etc. without using processor time.
The off-line function places the selected tape transport in the

off-line (local) mode and causes it to begin a rewind operation.
The TMAI11

Controller cannot write on or read from the

magnetic tape when the off-line function is used.

‘Read

This function permits reading from the magnetic tape. During

the read operation, the data portion of the record is loaded
into the controller data buffer for transfer to the memory. The
LRC and CRC characters are read but not transferred into
memory.

Write

This function permits writing on the magnetic tape. During the
write operation, data from the bus is loaded into the controller

data buffer register. The controller then transfers the data to
the tape transport write heads. The necessary LRC and CRC

characters are generated by the master transport and written
on the tape following the data. The write function advances
the tape forward one record.

Write EOF

This function writes an end-of-file (EOF) mark on the tape.
When selected, this function erases a 3-in. segment of tape
prior to writing the first character. The EOF mark and the

associated LRC character are considered one record.

3-2

Part IT

Table 3-1 (Cont)
Controller Functions

Number

Function

Space Forward

Description

This function is used to skip over a number of records to find
a specific record on the tape. When selected, the space forward

function causes the tape transport to advance forward a
specified

number of records. The number of records is

determined by the value in the byte record counter. This value
is loaded into the byte record counter by the program.

Space forward is used for tape positioning only and, therefore,
does not affect information stored on the tape or in memory.

Space Reverse

This function is identical to the space forward function except
the tape moves in the reverse rather than in the forward
- direction.

Write-with-Extended-IRG

This function is identical to the write function except that a

3-in.

segment

of tape

erased

before

writing the

character.
7

Rewind

first

This function is used for rewinding the tape on the feed reel so
that the tape can either be unloaded from the transport or

operation can start at the beginning of the tape. When this

function is used, the tape moves in the reverse direction, at a

much higher speed (150 in./sec) than for other functions, until
the beginning-of-tape (BOT) marker is detected.

Rewind is used for tape positionirig only and has no effect on
information stored on the tape or in the memory.

Data transfers are controlled by a byte record counter (MTBRC) and a current memory address register (MTCMA).

The program loads the byte record counter with the 2’s complement of the desired number of data transfers. The
counter is incremented before each transfer; therefore, the byte transfer that causes the byte count overflow

(MTBRC becomes zero) is the last transfer to take place. The byte counter is also used to count the number of
records during space forward and space reverse operations.
The current memory address register is also incremented before each transfer and, therefore, always points to the
next higher address than the one most recently accessed. Thus, when the entire record is transferred, the register
contains the address plus 1 of the last character in the record. For certain error conditions, the register contains the

address of the location in which the failure occurred.
During read operations, the controller assembles bytes from successive characters read from the tape channels.
The
eight data bits are assembled in a data buffer register for temporary storage. The parity bit is read but not loaded
into memory. When the byte is assembled, it is placed on the bus for transfer to memory. If an NPR transfer is used,

bytes from the data buffer are alternately stored into the low and high byte portions of memory.

Either the CRC character or the LRC character at the end of a record is stored in the data buffer, depending on the
state of bit 14 in the MTRD. If this bit is 0, the CRC character is loaded into the data buffer and can be used for
error detection. If the bit is 1, then the data buffer contains the LRC character at the end of the record.

Part I
During write operations, the controller disassembles eight-bit bytes from the bus and distributes the bits so that they

can be recorded on successive frames of the tape. All tapes are written at a density of 800 bpi. There are three

possible write functions: write, write-with-extended-IRG, and write end-of-file (EOF) mark.
When a write function is selected, the program loads the byte record counter with the 2’s complement of the
number of bytes to be written in the record. Although the parity bit, which is also loaded into the buffer, is
generated by the master tape transport, the polarity of the bit is determined by the controller so that either odd

binary or even BCD parity can be selected. When parity is generated and the buffer is loaded, the controller

transmits the byte to the master tape transport, which places the byte on the read/write heads of the selected slave
transport so that data can be written on the magnetic tape.
The write-with-extended-IRG function is identical to the write function except that a 3-in. gap, rather than the
normal gap, is used between records. When this function is selected, a 3-in. segment of tape is erased before writing

begins.

The write end-of-file (EOF) function is used to indicate that a block of records is complete. When this function is
selected, a special EOF character is written on the tape followed by an LRC character. These two characters
constitute a complete record. This command causes a 3-in. gap to be placed before the EOF mark. The XIRG

command must be absent to have this gap written.

System monitoring functions are performed by the controller status register. The 16 bits in this register retain error
and tape status information. Some status data is combined, such as vertical and longitudinal parity errors, or has a

combined meaning, such as illegal command, for optimum use of the available bits. The status register only monitors

the tape transport selected by the command register; therefore, other units that may be rewinding do not interrupt
the system when ready for data.
The following paragraphs discuss parity, gap shutdown, and function commands.
3.2.1

Parity

All parity characters are generated and read by the logic in the master tape transport rather than the controller.
However, a brief description of parity is included in this chapter, because an understanding of the parity function is

necessary for proper understanding of controller operation.

Whenever any command is issued that moves the tape forward, the master tape transport transmits a CRC strobe

(CRCS) pulse and an LRCS at the end of each record.

During any write operation, the controller sends a write data ready‘(WDR) level to the master tape unit for each
character in the record to indicate that the controller is ready to transmit data to the transport. The master tape
transport then issues a write strobe (WRS) pulse that strobes the character from the controller data buffer register
into the selected tape unit for writing on the tape.

When the last WRS pulse causes the BYTE RECORD COUNTER register to overflow, the controller lowers the WDR
level and the master tape transport writes the CRC character and then the LRC character
on the tape.
Whenever a slave tape transport is handling the magnetic tape being read or written, the control signals are still

generated by the master tape transport, and the necessary characters transferred from the master to the slave at the_
appropriate time.

The parity bit can be written in even or odd parity. If the master tape transport is writing even parity, then the
parity bit is set or cleared so that the total number of ones in the character is even. If odd parity is used, then the

parity bit is set or cleared so that the total number of ones in a character is odd. The type of parity to be used (odd

or even) is determined by the PEVN bit in the controller command register.

3-4

Part 11

A longitudinal redundancy check (LRC) is also performed. The master tape transport writes an LRC character at the
end of each data record. The bits in this character may be either 1s or Os. The characteris written in such a manner
that the total number of bitsin a channel (including the LRC character)is even.

In addition to vertical and longitudinal parity checks, the tape format includes a cyclic redundancy check (CRC),
which checks the total number of data characters within a record or block. The vertical parity of the CRC character

is odd if the number of data characters within the block is even, and is‘e’ven if the number of data characters is odd.
The CRC character is generated by a nine-bit register in the master tape transport. All bits in a data character are
exclusive-ORed into this register, which shifts one position between each character transfer. If shifting causes a 1 in
the register bit corresponding to tape channel P, then the bits representing tape channels 2, 3, 4, and 5 are inverted.

After the last data character is read, the register shifts a final time. At this point, all bit positions except those

representing tape channels 2 and 4 are inverted. The register now contains the CRC character, which is written on
the tape.

The values described above are related to the physical location of the read/write heads as shown below.
Valueof CRC

Track No.

3.2.2

Most Significant Bit

0% 1

4
9

Least Significant Bit

Gap Shutdown

The master tape transport.employs_ a gap shutdown period to ensure a blank gap of tape between records. As soon as
the master transport reads the LRC character, it times through the gap shutdown period
and then sends a stop
command to the selected slave transport.

On receiving a stop command, the selected transport enters a settling down (SDWN) period’,‘whic’h is the time
between the stop command and the actual stopping of the tape. When the transport stops, it enters an idle period at
which time the tape unit ready (TUR) bit is set to 1ndrcate that the transport is now ready to accept a function
command.
3.2.3

Function Commands

The program selects the specific function to be performed
by setting or clearing appropriate function bits in the

command register.

When the program sets the GO bit in the command register, the operation defined by the selected

function occurs. Both the control unit ready (CU RDY) and tape unit ready (TUR) bits are cleared to indicate that

the controller and selected tape transport are currently engaged in an operation and cannot accept a new command
until the current operation is completed.

When the off-line function is selected, the tape unit goes off-line and then rewinds to the beginning-of-tape (BOT)
marker. As soon as the off-line command is given, both the CU RDY and TUR bits are cleared, thereby preventing

the controller and transport from accepting a new command. The master tape transport then clears the select remote
(SELR) bit in the status register; indicating to the program that the selected transport is now off-line.

When a tape reverse operatron (not rewind) is selected, the master ‘tape transport enters the gap shutdown perrod
immediately after readmg the first data character.

During a write function (write, write EOF, and write-with-extended-IRG), the CU RDY bit is set when TUR asserts.
For write EOF and write-with-extended-IRG functions, a 3-in. gap is erased prior to writing the required data
characters.

3-5

Pare 11

A write EOF function causes a character that indicates a block of data is complete to be written on the tape. This
function writes an EOF character followed by an LRC character. These two characters constitute one record. In an

EOF record (Figure 3-1), the EOF character and the LRC character are identical. The EOF character is an octal 23.

OCTAL

LRC

CHANNELS

MOST SIGNIFICANT 9

(PARITY)

LEAST SIGNIFICANT

23 (OCTAL 23) |

1-0427
Figure 3-1

3.3

EOF Record

SYSTEM RELATIONSHIP

Figure 3-2 is a simplified block diagram of the TMAI11-M DECmagtape System, showing the relationship of the

TMA11 Controller to the TS03 Transports and to PDP-11 system components. Note that all communication

between the controller and the transports is handled by the master tape transport Commumcatron between the

controller and other PDP-11 devices is by means of the Unibus.
3.4

ADDRESS SELECTION

The TMA11 Controller selection logrc decodes the address on the bus lines to determine if the control]er has been
selected for use. Unique addresses are assigned to each of the six registers in the controller and manipulation of these

registers determines whether information is to be written on or read from the tape, or if some other control function
is to be performed.

The TMA11 Controller consists basically of six registers (or bus addresses). In addition to decoding the incoming
~ address, the selection logic controls the information flow between the Unibus and the controller registers. The logic
produces SELECT line and gating IN or OUT srgnals which determme the register to be used and the function to be
performed (i.e. mput or output)

The selection logic consists of an M105 Address Selector module and register select logic (M797 module).
3.4. 1

Address Selector Module

The M105 Address Selector module (Drawmg TMA11-0- 19) decodes the address information from the bus to
provide the gating and select line signals that activate appropriate TMA11 Controller logic circuits for the selected

register. The M105 module jumpers are arranged so that the module responds only to the standard device register
addresses 772520 through 772532. Although these addresses have been selected by DEC as the standard assignments

for the TMAI11 Controller, the user may change the jumpers to any address desired. However, any MAINDEC

program (or other software) that references the TMA11 standard address assignments must be modified if other than
the standard assignments are used.

3-6

Part I
TO OTHER
DEVICES
ON BUS

MEMORY

COMMAND

|
|

TMAI1T

A CONTROLLER

DATA

TSO03
MASTER
TAPE

TSO3
SLAVE

DATA

TAPE

TRANSPORT

sTATUS | TRANSPORT

PROCESSOR

CONSOLE

TO OTHER

DEVICES

ON BUS

’

11-2672

Figure 3-2 TMA11-M System — Simplified Block Diagram

A standard M105 module provides only four select line signals and, therefore, can reference only four registers.

Because the TMA11 Controller contains six registers, the M105 is used in conjunction with register select logic
(M797 module) to provide the six required select lines. This necessitates wmng the MIOS 1n a manner somewhat
-

dlfferent from the standard wiring.

Rather than decode the entire incoming address, as is the normal method, the M105 in the TMA1l Controller
decodes all but the four least significant bits. These bits are then decoded by the register select module (M797
module), provided the other bits are part of a valid address.

Address line A0O, which is the least significant bit of the address, is decoded by the M105 to determine if a byte or

word operation is required. Address lines AO1, A02, and AO3 are grounded and are the only address bits that cannot

be decoded by the M105. Thus, the M105 decodes all but the four least significant bits of the incoming address as

shown in Figure 3-3. If the first portion of the addressis valid (77252 or 77253), then the address selector generates
an ADRS DEC MSYN L (address decoded, master sync valid) 31gnal that clears the decoders in the reglster select
logic (Paragraph 3.4.2).

The M105 Address Selector also decodes the bus CO1 and COO mode control signals to generate the IN, OUT LO,

and OUT HI signals that determine whether the selected register is reading or writing (performing an input or output
function).

3-7

Part IT

DECODED BY THE M105.

BIT CONFIGURATION

DECODED BY REGISTER
SELECT LOGIC. MAY BE

SHOWN IS ONLY VALID

ANY COMBINATION
OF

COMBINATION

1sAND Os

111

010

101

1(X

YYY

\_T_J

Indicates value of final

digit. May be any value

(0-7).

L Indicates whether next to
last digit is 2 or 3.
Figure 3-3

M105 Address Decoding

It is beyond the scope of this discussion to cover operation of the M105 Address Selector; detailed descriptions of

this module are coveredin DIGITAL’s 1973~ 74 Logic Handbook andin the PDP-11 Perzpherals Handbook
There are only two prime differences between normal use of the M105 and the use in the TMA11 Controller. Pin L2

is normally a test point, but in the TMA11 it is used to provide the ADRS DEC MSYN L signal for the register select
logic. Address lines AO1, A02, and AO3 are normally decoded by the

M105, but in theTMAT11 they are decoded by

the register select logic (M797 module).
3.4.2

The gating signal lines from the M105 Address Selector and address lines AOl, A02, and AO3 from the’ bvus are
connected to the M797 Register Select module (Drawing TMA11-0-20). This module decodes the address lines and

provides the pulses that select the appropriate register and determine whether the register is to be read or loaded.
The ADRS DEC MSYN L signal from the M105 module is applied to the register select module when valid addresses
up to the least mgmficant octal digit have been decoded. The ADRS DEC MSYN L signal gates the appropriate gating

signal (IN, OUT LO, OUT HI) to enable one of three decoders. If the M105 has provided an IN gating signal, then
the first decoder (E2) is enabled, and one of the six outputs is selected by address lines AO1, A02, and A03. The IN

gate indicates that data is being transferred into the bus master device, and the decoder output selects the register
from which the data is to be taken. Note that the decoderis actually enabled by the absence of the two OUT signals

rather than the presence of the IN signal (Table 3-2).

Table 3-2
- M797 Decoder Selection

~ Input Signal

'Fufictioh Selected | Decoder EAnz.lbled

<~OUT HI> ;Load., =

IN/~OUTLO\|

OUT LQ
~ OUTHI

[

Load even byte
| Loadoddbyte

E6
|

3-8

Output Signals
|

Remarks

One
for each ..
register

Only four of the six regis-

ters can
be loaded.

Part 11

If the OUT LO signal is supplied by the M105, the second decoder (E6) in the M797 module is enabled, and the

address lines select one of five decoder outputs. The OUT signal indicates a load operation (data from bus to master
device). The first four outputs are used for the four registers that can be loaded from the bus. Note that OUT LO
loads only the low-order (even) byte in these registers. The fifth output is used to load bits 13 and 14in the TS03
read lines.

If | the OUT HI signal is received from the M 105, the third decoder (E9) is enabled, and the address lines select one of
four decoder outputs to load the high-order (odd) byte of the selected register.
Table 3-3 indicates the functions selected by the various select line and gating signal combinations.

‘Table 3-3
Gating and Select Line Signals

Status
1
2
3
4
5

Status to bus
Command to bus
Byte record count to bus
Current memory address to bus
Data buffer
to bus

ouT
ouT
OouUT
ouT
OUT

Bus to command register
Bus to byte record counter
Bus to current memory address register

1
2
3
4
5

NOTES:

IN
'IN
IN
IN
IN

DATI or DATIP
MTS
DATI or DATIP
MTC
MTBRC | DATI or DATIP
MTCMA | DATI or DATIP
MTD

Bus to bits 13 and 14 of TSO3 read lines

DATI or DATIP

MTRD | DATI or DATIP

TS03 read lines to bus

Bus to data buffer register

Bus Cycle

Function

Select Line | Gating Signal

MTC
DATO or DATOB
MTBRC | DATO or DATOB
| MTCMA | DATO or DATQB

MTD

DATO or DATOB

MTRD | DATO or DATOB

1. IN and OUT refer to information transfer with relation to the bus master device.
. Status register and TS03 read lines can be read by the processor but cannot be loaded

by the processor except for bit 14 of the TS03 read lines, which is the CRC/LRC

- character selector bit,—and bit 13 which is the BTE/OPI generator bit.
. The OUT gating signal actually can be OUT LO or OUT HI. OUT LO loads the

low-order (even) byte; OUT HI loads the high-order (odd) byte.
. The IN gating signal is actually (~OUT LO-~OUT HI).

3.5 BUS CONTROL
The TMAI11 Controller is interfaced to all other components of a PDP-11 system by the Unibus. All control

instructions and data transfers that take place between the TMA11 Controller and PDP-11 components, such as the
processor and memory, must pass through this bus.
The bus control logic performs three main functions:

NPR transfers, interrupts, and slave response. Each of these

functions is briefly explained in Table 34 and discussed in detail in the following paragraphs.

3-9

Part 11

Table 3-4
Bus Control Functions

- Function

Controller Status | Bus Cycle

NPR Transfer

Bus Master

DATOB

Description
The bus control logic requests control of the bus for NPR

~data transfers whenever the controller is ready to send data

from the data buffer through the bus to memory (read
function). Transfers one byte at a time.
DATI

The bus control logic requests control of the bus for NPR
data transfers whenever the controller is ready to receive

data from the memory (write function). Transfers one byte
at a time.

Interrupt Request
|

‘Bus Master

INTR

The bus control logic issues an interrupt request if the
controller requires servicing by the program, because it is
ready to transfer data, is ready to begin a new operation, is
awaiting a command, or because an error condition exists.
INT ENB in the command register must be set.

Slave Response'

3.5.1

Bus Slave

DATO

Whenever the TMA11 Controller is selected for use, it must

DATOB

respond with SSYN in order for the command instructions

DATI

to be supplied by the processor or other bus master. This

DATIP

logic provides the proper slave response.

NPR Transfers

The NPR control logic circuits are shown on Drawing TMA11-0-19. The main portion of the control logic consists of

an M796 NPR Control module. This module is used to control transfers of data to and from any slave device on the

bus when the controller is functioning as bus master. The transfers are performed independently of processor control
and are often referred to as “direct memory access.”

The logic necessary to gain control of the bus is provided by the M7821 Interrupt Control module (Drawing

TMA11-0-19), which generates the non-processor request (NPR). When the proper responses are received from the
processor, the M7821 asserts BUS BBSY to indicate bus control. On becoming bus master, the controller is free to
conduct a data transfer.

A DATI cycle is performed if the controller needs data from a bus address; a DATO or

DATOB cycle is performed if the controller transmits data to memory or some other device. Basically, a DATI is

used during write operations; a DATO or DATOB is used during read operations.

The bit that controls selection of a DATI or DATO is function bit 02 (Drawing TMA11-0-07). This bit is always
clear for a read operation (octal number 01) and is always set for write operations (octal numbers 02, 03, and 06).

Therefore, by using this bit for bus cycle selection, the proper cycle is used for the selected function (read = DATO,
write = DATI). The resultant read and write signals are applied to the NPR input logic (Drawing TMA11-0-11).
Whenever a read strobe (RDS) or write strobe (WRS) pulse from the master tape transport is sent to the controller or

whenever the WRITE DATA ENB and GO STROBE pulses are present in the controller, a series of gates is qualified
to produce a signal that sets the NPR enable flip-flop, provided there is no non-existent memory, bus grant late or
overflow error condition present, or no CRCS or LRCS pulse present. This flip-flop produces the NPR ENB H level,
which initiates the NPR sequence

3-10

Part 1T

The NPR ENB H level activates the Master Control A portion of the M7821 Interrupt Control module (Drawing

TMA11-0-19), which generates a request on the BUS NPR line. When the processor has completed its current bus

cycle and all higher priority device requests have been satisfied, the processor issues a grant on BUS NPG IN. The
M7821 module responds with BUS SACK and, when BUS SSYN, BUS BBSY, and BUS NPG are negated (mdlcatmg
that the busis free), the M7821 claims bus control by asserting BUS BBSY

At this time, the M7821 Interrupt Control module produces an NPR MASTER signal, which activates the M796
NPR Control module (Drawing TMA11-0-19). This NPR MASTER signal produces an internal start signal in the
M796. Detailed descriptions of both the M7821 Interrupt Control and the M796 NPR Control modules are provided
in the PDP-11 Peripherals Handbook. Note, however, that in the Peripherals Handbook, the M796 is referred to as
the Unibus Master Control module

Regardless of the bus cycle selected, a bus address must be used to indicate where the controller is to send or receive
data. The M796 module produces the ADRS - BUS L signal, which enables the address line drivers in the current
memory address register (MTCMA) so that the data transfer is made with the location specified by the MTCMA.

When a read operation is performed, the controller receives data read from the tape by the transport, assembles the
data in the data buffer register (MTD) and, when the data is properly assembled, sends the data to the bus. This is a
DATOB operation, because only one character is read from the tape at a time and the character corresponds to a
PDP-11 byte.

When a DATOB bus cycle is selected by the M796 module, the module produces the DATA - BUS signal which,

together with a flip-flop and AND gates, produces alternate HI DATA BYTE L and LO DATA BYTE L signals
(Drawing TMA11-0-15) that enable data buffer output gating logic (Drawing TMA11-0-14); thus, the information
stored in the data buffer register is gated onto the bus for storage in alternate memory byte locations. After the

necessary Unibus time delays, BUS MSYN is asserted and, thus, a slave device is selected. When the slave device
responds with SSYN, MSYN is dropped, and the bus cycle is complete.

When a write operation is to be performed, the controller receives the data from the Unibus, holds it temporarily in

the data buffer, and then transmits it through the read/write lines to the master tape transport electronics for writing
on the magnetic tape.

When a DATI is selected by the M796 module, the module first produces the ADRS - BUS signal as usual but,
rather than produce a DATA
- BUS signal, the M796 waits for the slave to respond and then produces two

sequential pulses: DATA STB 1 and DATA STB 2. The DATA STB 1 pulse allows time for the data on the Unibus
to deskew and settle. The pulse is also used internally (Drawing TMA11-0- 16) to produce DATA BFR STB 1 and
DATA BFR STB 2, which clear the data buffer register (MTD)
The trailing edge of DATA STB 2 is tied back into the M796 module to produce an internal signal, indicating that
the data has been accepted.
As a result of this signal, MSYN is dropped, and the bus cycle is complete.

On completion of either a DATI or DATOB bus cycle, the NPR CLR BBSY signal is generated. This signal is used to
increment the current memory address register (MTCMA). The NPR CLR BBSY signal also produces the CLK 2

pulse (Drawing TMA11-0-19), which increments the byte record counter (MTBRC). The trailing edge of NPR CLR
BBSY direct clears the request bus flip-flop (Drawing TMA11-0-11), which drops at the input to the M7821
Interrupt Control which, in turn, drops BUS BBSY.

A time-out flip-flop, referred to as NXM (non-existent memory), in the M796 module is set if an SSYN response
from the slave device does not occur within 10 us after BUS MSYN is asserted by the controller. When this flip-flop

is set, the bus cycle is not performed, and the NXM error bit in the status register is set by the error logic circuits. In
this case, the current memory address register is not incremented and, therefore, the register contains the address of
the erroneous location.

Part 11
3.5.2

Interrupt Request

An interrupt request is generated when the controller is ready to send or receive data to or from the bus. Interrupt
requests are controlled by the BR (bus request) input logic (Drawing TMA11-0-11) and by the M7821 Interrupt
Control module.
The BR interrupt flip-flop is used to generate the BR INT pulse, which activates the M7821 Interrupt Control. Note
that this flip-flop can be set only if the INT ENB bit is set.

When a read, write, write IRG, write file mark, space forward, or space reverse operation completes, the transfer

done flip-flop is set (TMA11-0-06). An operation that results in setting the ERR bit also sets the transfer done
flip-flop. Transfer done is ANDed with TUR from the drive performing the operation which generates SET CUR L

and SET BR L. Execution of a rewind, a reverse motion at BOT, or some action that results in an ILC causes the

generation of SET CUR L and SET BR L (TMA11-0-06).

If a function command is issued but the GO bit remains cleared and INT ENB is set, an interrupt is initiatéd. If the
selected tape transport (as indicated by the SEL bits in the command register) completes the rewind operation
before a new command to that unit is received, then an interrupt is initiated. This logic is covered in Paragraph 3.8.

The M7821 module provides the logic necessary to make bus requests and gain control of the bus (become bus
master). The module also includes the circuits necessary for generating an interrupt. The module contains two
completely independent request and grant acknowledge circuits (channels A and B) for establishing bus control. The
following paragraphs provide a brief description of both channels. A detailed description of the M7821 module,
including circuit schematics, is contained in the PDP-11 Peripherals Handbook.

Channel A (master control A) is used only for NPR requests and is activated when the bus request flip-flop is set, as
described in Paragraph 3.5.1. The BR MASTER L signal from channel A activates the NPR control logic so that an
NPR DATI or DATOB bus cycle can be performed. No vector address is used with this channel.

Channel B (master control B) is used to generate interrupts (Drawing TMA11-0-19). This channel is activated by the

BR INT pulse described previously.
The jumpers on the M7821 module are wired for a standard vector address of 224 and a bus request level of BRS.
Note that the priority level can be changed by the priority chip on the G736 module, and the vector address can be

changed by jumpers on the M7821 Interrupt Control. However, any programs referring to that level or vector
address must also be changed if the jumpers are changed. All DEC software references the above standard jumpers.
3.5.3

Slave Response

When the TMA11 Controller is to participate in a data transfer as a bus slave device, the slave response logic provides
the necessary acknowledgement signals required by the bus master. This slave response logic is part of the M105
Address Selector and the M797 Register Select modules.

For a DATO, the master device places the address of the TMA11l Controller on the bus A lines, data to be
transferred on the bus D lines, and signals on the bus C lines to select the appropriate register and function to be
performed.

The master device waits 150 ns (75 ns to allow for worst case signal skew and 75 ns for address decoding) and then
asserts BUS MSYN, provided the bus is clear (SSYN is clear).

When the controller decodes the address, it produces the ADRS DEC MSYN L signal at the time MSYN is received.

The BUS MSYN L signal is gated through the M105 to produce the BUS SSYN response. There is a 300-ns time
delay between MSYN and generation of SSYN.

3-12

Part
11

The master device receives SSYN and clears MSYN (which clears ADRS DEC MSYN L). Clearing ADRS DEC MSYN

L negates BUS SSYN to signify the end of the bus transaction.

3.6 BUS DRIVERS AND RECEIVERS
The bus drivers and receivers provide the signal levels required for compatibility with the Unibus. The M798

Transmitter module contains bus drivers for interfacing controller outputs to the bus. The M784 Receiver module
contains inverting circuits that provide buffered bus signal outputs, which are used as inputs to the controller. The
M785 Transceiver module contains both drivers and receivers that are used for bidirectional interfacing to the bus.

The bus receivers are used primarily on the input lines
to the various controller registers; the bus transmitters are
used on the output lines. The transceivers are used on the current memory register lines for bits 01, 02, 03, 16, and

The M784, M785, and M798 modules are described in the PDP-11 -Peripherals Handbook.
3.7

REGISTERS

All software control of the TMA11 Controller is performed by means of six device registers. These registers are
assigned Unibus addresses and can be read or loaded with any PDP-11 instruction that refers to their address. Note,
however, that the status register and the TS03 read lines (with the exception of bits 13 and 14 in the read lines) can

be read but cannot be loaded from the bus. Bits 13 and 14 of the read lines can be loaded from the bus. In addition,
bit 13 is always read as a 0. Table 3-5 lists the six registers and the function of each.

The register select logic provides the pulses that activate a specific register for use. This selection is described in
Paragraph 3.4.2.
Paragraph 3.7.1 describes the initialize (INIT) logic, which is common to all registers. Subsequent paragraphs discuss

each of the registers from a hardware standpoint. A discussion of the registers from a programming standpoint is
presented in Chapter 2.

Table 3-5
Device Register Functions

Mnemonic

Status Register

MTS
|

Function

Provides detailed information on the status of the TMAII
-

Controller. Such information includes error indications and tape
unit status indications.

Command Register

MTC

This is the main control register in the TMAT1l ‘Controller.
Specifies the operation to be performed on the tape unit, selects
the tape bit packing density, and selects the tape unit to be used.

Indicates

when

TMA11

Controller

ready,

when an error

condition exists, and when the controller is cleared.
Provides the two extended address bits for bus addresses.

3-13

Part 11

Table 3-5 (Cont)
Device Register Functions

Mnemonic

Byte Record Counter -

MTBRC

Function
Counts the number of bytes in any write operation, the number

of records in a space forward or space reverse operation, and the
number of bytes in a read operation. Desired byte count is preset

by the program. When the register counts the number of specified
bytes, it prevents further transfers.
Current Memory Address

MTCMA

Specifies the bus or memory address to or from which data is
transferred during read and write operations. After each transfer
is completed, the register is automatically incremented by 1 (next

byte location).
When BGL or NXM errors occur, the register contains the address

of the location in which the failure occurred.
Note

that

this

is incremented by

and, therefore,

accesses byte, rather than word, locations.

Data Buffer Register

MTD

Contains the information read from or written on the tape. Serves

as a buffer between the tape unit and the memory.
TU10 Read Lines

MTRD

Permits storage of data read from the tape transport. A parity bit

indicates

the

occurrence

of a

parity

error and

the

channel

containing the error.

A character selector bit is used to select the last character of a
record that is to be loaded into the data buffer register.

A timer bit is used for diagnostic purposes by measuring the time
duration of the tape operations.

A BTE/OPI bit is used to set transfer done prematurely in order
to provide a bad tape error indication.

3.7.1

Initialize Logic

The TMA11 Controller logic can be initialized by one of the following methods:
Loadinga 1 into bit 12 (Power Clear) of the command register.

Issuing a programmed RESET instruction.

Depressing the START switch on the PDP-11 processor console.

Occurrence of a power fail by either the processor power supply or the controller power supply.

The controller initialization logic is shown on Drawing TMA11-0-17.

3-14

Part 11

When a 1 is loaded into bit 12 of the éommand register, an AND gate is qualified by D12 H and SEL 1 OUT HI H.
When the AND gate is qualified, the INIT H and INIT L signals are produced as before.

The remaining three methods of initialization (programmed RESET, processor START, power fail) all use external

logic to provide a BUS INIT signal input to the controller. This signal becomes INIT REC H and produces the INIT
H and INIT L signals as before.
3.7.2

Command Register (MTC)

The command register is the main control register in the system and specifies the operation to be performed. Each of
the bits is discussed separately below, beginning with the most significant bit.

3.7.2.1

Error Bit (15) — The error bit (bit 15) in the command register is the inclusive-OR of all error conditions in

the status register. Thus, if any error bit in the status register is set, it sets the error bit in the command register.
When any error condition occurs, it sets the appropriate flip-flop in the status register. The appropriate level from
the flip-flop passes through a series of OR gates (Drawing TMA11-0-18) and sets the command register error
flip-flop, which produces the ERR H signal. The ERR H signal is then applied through a series of AND gates
(Drawing TMA11-0-13) so that the bit can be read from the bus.

Because of gating shown on Drawing TMA11-0-18, the ERR flip-flop may or may not be set simultaneously with the

detection of an error condition. In the case of BGL (bus grant late), NXM (non-existent memory), ILC (illegal
command), and BTE (bad tape error) errors, the resultant error signal passes through OR gates and sets the error
flip-flop simultaneously with detection of the error.

If RLE (record length error), CRE (cyclical redundancy error), PAE (parity error), or EOF (end-of-file) occurs, the
appropriate status register flip-flop is set, and the resultant error signal is ANDed with the LRCSD signal, which

occurs only when the LRC character is detected. Thus, the command register error flip-flop is not set until the LRC
character has been read, in order to give the controller time to complete the current operation.
When the EOT (end-of-tape) marker is detected, it represents an error condition only if the tape is moving in the
forward direction. The EOT signal is ANDed with SPACE REV L, REWIND L, and LRSCD. This AND gate,

therefore, is qualified only if the end-of-tape marker has been detected (EOT), the tape is not moving in the reverse
direction (SPACE REV L), the tape is not being rewound (REWIND L), and the LRC character has been detected

(LRCSD). If these conditions are met, the gate is qualified,
and the resultant output sets the error flip-flop in the
command register.

When the error bit is set, it sets the transfer done flip-flop as shown on Drawing TMA11-0-06. The transfer done
signal is ANDed with TUR to produce the SET CUR L signal that direct sets the control unit ready (CU RDY)

flip-flop.

The output of the interrupt flip-flop (BR INT H) is applied to the Master Control B section of the M7821 Interrupt

Control module, and the TMA11 Controller initiates an interrupt routine. Thus, an error condition causes an
interrupt, provided the INT ENB bit is set.
A selection error is an illegal command and, therefore, also causes an error condition.
The error conditions can be cleared by INIT (refer to Paragraph 3.7.1) or by the next GO command.

3.7.2.2 Density Bits (14 and 13) — The DEN 8 and DEN 5 bits are used together to determine the bit packing
density of the tape. Only 800 bpi can be used. The program selects the density by loading the appropriate value into
these bit positions, according to the following table:

3-15

Part 11

DENS8

DENS

(BIT 14)

(Bit 13)

Selected bpi
200

556
|

7-channel tape (See Note)

800

9-channel (TS03)

NOTE

TSO03 ignores bits 14 and 13; it always operates at 800 bpi,
9-channel.

These signals are applied to the master tape transport by the controller but are ignored as the TSO3 only operates at
800 bpi. The controller logic is used primarily to feed appropriate bits to the master tape transport and to select the

core dump mode of operation. Controller logic is shown on Drawing TMA1 1-0-08.
When a 1 is loaded into bit 13 (DEN 5), it is applied to the D-input of a flip-flop. The clock input is the SEL 1 OUT

HI H signal that indicates the bus is loading the command register. These two inputs set the flip-flop. The low side of
the flip-flop qualifies an AND gate, provided the core dump mode is not being used. The output of thc AND gate is

the DEN 5 signal (representing binary 1) that is applied through the BC11A interconnecting cable to the master tape
transport.

If a O is loaded into this bit position, the flip-flop is not set, the AND gate is disqualified, and the AND gate output
is a low level representing binary 0.
The DEN 8 (bit 14) signal is produced in an identical manner to the DEN 5 signal.

3.7.2.3

Power Clear Bit (12) — When the program loads a 1 into this bit position, an initialize signal is provided to

clear the TMA11 Controller, the master tape transport, and the slave transport. This initialize signal does not clear
the processor or any other device on the bus. The initialize signal is generated by the controller logic as descirbed in

Paragraph 3.7.1. The INIT signal passes through a gate and becomes the CINIT signal, which is applied to the master
tape transport logic to clear all transports.

3.7.2.4

Parity Bit (11) — The parity bit (bit 11) specifies whether odd or even vertical parity is to be read from or

written on the magnetic tape. Although parity is generated by the master tape transport, the parity bit in the

controller command register is used to select the polarity. The parity bit is referred to as the PEVN (parity even) bit,

because it denotes even parity when set.

The parity flip-flop is shown on Drawing TMA11-0-08. The flip-flop is set by SEL 1 OUT HI H (indicating that the
command register has been selected for loading from the bus) and by D11 H (indicating that a 1 has been loaded

into bit 11 of the command register). With the flip-flop set, the low side passes through a gate and becomes the
PEVN signal, which is applied to the master tape unit to indicate that even parity is to be used.

The parity flip-flop is cleared by loading a 0 into bit 11 (the D11 H input becomes low) or by an INIT signal, which
direct clears the flip-flop. When the flip-flop is clear, the resultant PEVN signal is low, indicating to the master tape
transport that odd parity is to be used.

3.7.2.5

Unit Select Bits (10, 09, 08) — The three unit select bits (bits 10 through 08) specify the tape transport

that is to be used for a particular operation. The states of these three bits represent an octal code corresponding to
the number of the transport, as set by the UNIT SELECT switch on the individual transport.

The three unit select bits are shown on Drawing TMA11-0-10. These three bits (UNIT SEL BIT 2, UNIT SEL BIT 1,
and UNIT SEIL BIT 0) are set or cleared by loading 1s or Os from bus lines 10, 09, and 08, respectively. These bits
are loaded whenever the high byte of the MTC is addressed (SEL 1 OUT HI H). This results in SEL 2, SEL 1, and
SEL O signals (representing the appropriate octal code loaded from the bus), which are applied to the master tape
transport logic.

3-16

Part .‘1I

The master tape transport only recognizes octal codes 000 and 001. Any other code places both transports in the
deselect mode.

Another instance of improper selection would be selecting a tape transport that is off-line. Improper selection is an
ilegal command (ILC) error, which, in turn, causes an ERR indication.

The unit select logic also produces UNIT SEL BIT TM H and L signals, which are used by the tape motion control
logic described in Paragraph 3.8.

3.7.2.6

Control Unit Ready Bit (07) — The control unit ready bit (bit 07) indicates that the controller is ready to

receive a new command. It is set (indicating ready) whenever the previous command operation is completed, an
initialize signal is given, or an error condition exists. It is cleared at the beginning of a tape operation when the GO
command (bit 00) is issued.

The control unit ready flip-flop is shown on Drawing TMA11-0-06. A series of gates is connectéd to the direct-set
input of the flip-flop. If the INIT signal goes high (indicating initialize), the output of the OR gate goes low and
direct sets the control unit ready flip-flop, producing CU RDY H.

The gating also direct sets the CU RDY bit when an operation sets the transfer done bit which is ANDed with TUR;
when a rewind operation has started; when the unit goes off-line during an operation; and when the BOT is sensed
during a rewind or space reverse operation.

The control unit ready flip-flop is cleared by the GO BIT H signal, which occurs whenever the GO bit is loaded from

the bus.

3.7.2.7 Interrupt Enable Bit (06) — The interrupt enable (INT ENB) bit, when set, allows an interrupt to occur
provided CU RDY (bit 07) becomes set. It also permits an interrupt whenever a tape unit in the rewind mode
reaches the BOT marker at the time CU RDY is a 1, or whenever an instruction sets the INT ENB bit but does not
set the GO bit (bit 00).

The interrupt enable flip-flop is shown on Drawing TMA11-0-08. It is set by SEL 1 OUT LO H (bus loading
command register) and D06 H (a 1 in the bit position). The high output of the flip-flop (INT ENB H) qualifies one

side of an AND gate, tied to the input of the bus request flip-flop (Drawing TMA11-0-11). The other input to the

AND gate is produced by a series of gates corresponding to the conditions mentioned above. Thus, when a condition
exists that results in a SET BR L pulse, or when a tape unit has completed its rewind operation (indicated by RWS H

and BOT H), or when an instruction sets the INT ENB bit but does not set the GO bit (indicated by INT ENB L,
DOO L, and SEL 1 OUT LO H), the AND gate is qualified, thereby setting the BR INT flip-flop.

The INT ENB bit is direct cleared by the INIT L signal or is cleared by loading with a 0 (input D06 H becomes low).
3.7.2.8

Extended Bus Address Bits (05 and 04) — The extended bus address bits 05 and 04 represent bus address

bits A17 and A16, respectively. These bits are used to specify 18-bit addresses when required, because the current
memory address register (MTCMA) is only 16 bits long. Although functionally part of the MTCMA, these bits are

loaded by a SEL 1 OUT LO H signal, which indicates that the command register has been selected for use. The

current memory address register is incremented after each data transfer, and this incrementation also affects the two
extended address bits. These bits are cleared by INIT, as shown on Drawing TMA11-0-20.
3.7.2.9

Function Bits (03, 02, 01) — The three function bits are set or cleared to provide an octal code that selects

any one of eight commands that control operation of the tape system. These commands are used for reading data
from or writing data on the tape and for controlling tape motion.

3-17

Part 11

The three function bits are shown on Drawing TMA11-0-07. The appropriate 1 or 0 on the associated bus data line
(D03, D02, and DO1) is loaded into the associated function flip-flop by means of a load pulse, which is SEL 1 OUT
LO H (command register selected for loading from the bus).
The FUNCTION BIT H line from each of the three flip-flops is tied to the input of an M163 binary-to-octal decoder,
which decodes the state of the three bits and provides the selected function output signal. The selected function

signal is then applied to other controller logic to institute the function. Other logic that uses the function signals
includes: ready control logic, motion control logic, start control logic, error logic, and tape interface logic.
3.7.2.10

GO Bit (00) — The GO bit is set by loading with a 1 from the bus and is used to initiatc operation of the

function selected by the function bits.

- The GO flip-flop (TMA11-0-05) is set by the SEL 1 OUT LO L signal (command register selected to receive data
from bus) and the DOO H signal (1 loaded into bus data line 00). Note that the output of the flip-flop, when set,
passes through a series of gates to produce three derivatives of the GO signal. These derivatives (shown in Figure 3-4)

are:

GO STROBE 1, GO STROBE 2, and SET. The SET signal is effectively the GO pulse to the master tape

transport and must be present before any tape operation can be initiated.

The GO flip-flop is cleared by INIT or by the GO STROBE 2 pulse. GO STROBE 2 is simultaneously applicd to an
OR gate, the output of which direct clears the GO flip-flop, and to an AND gate which, when qualified, asserts the

SET pulse (GO command to transport).
During normal operation, the GO pulse is 1 us in duration. However, in some instances this duration may be

considerably longer, depending on the status of the selected tape transport.

GO STROBE1 ___[

| 1

GO STROBE 2

SET

NOTES:

1. All

signals are

1ps in duration

2. Go signal is normally 1ps but may be 1Oms or longer depending on what time
the bit is set (see text)
11-042S

Figure 3-4

Derivatives of GO Signal

As mentioned previously, the GO pulse cannot go low until the GO STROBE 2 pulse is generated. Before GO
STROBE

2 can be generated, these conditions are needed:

GO BIT H (GO flip-flop) set, selected unit not

performing a rewind instruction, and the selected transport is ready (TUR). If any one of these conditions is not

true, the GO pulse remains high until the required condition becomes true.
If the selected tape unit is not ready (note that this condition also exists during rewind, because RWS direct sets the

flip-flop, providing one of the AND gate inputs), the GO bit duration could be as long as several minutes as would be
the case when the selected tape unit is in the process of rewinding.

3-18

Part 17

The GO BIT H signal is also applied to the control unit ready (CU RDY) flip-flop (Drawing TMA11-0-06) to clear
the CU RDY bit. This is necessary because whenever the GO bit is present, it indicates the controller is performing
an operation and is not ready to accept a new command.

3.7.3

Status Register (MTS)

The status register is used primarily to provide indications of error conditions. It also indicates the status of certain
system functions such as write lock, settling down period, tape unit ready, and beginning of tape.

The status register error logic is shown on Drawing TMA11-0-18. Whenever one of the specific error signals is
present, it passes through an OR gate, which is the inclusive OR of all error conditions. The resultant flip-flop output

signal(ERR L) sets transfer done which is ANDed with TUR, then passes through a pulser and two OR gates in the

ready control logic (Drawing TMA11-0-06) and direct sets the control unit ready (CU RDY) flip-flop. This allows
the controller to issue an interrupt request whenever an error exists (Paragraph 3.5.2).
All error bits (15 through 06) in the status register are read-only bits. They can be read (tested) by the program to
determine if a specific error exists or not, but they cannot be loaded by the program. All error bits are cleared by
INIT or by the GO (GO STROBE 1) pulse to the tape unit.

The remaining bits (05 through 00) indicate system status and are set or cleared by the master tape transport. These
bits can also be read by the program.

Each individual bit in the status register is discussed separately in the following paragraphs.
3.7.3.1

Illegal Command (15) — The illegal command (ILC) error bit indicates a conflict in commands. The ILC

error logic (Drawing TMA11-0-17) consists of a series of gates and a flip-flop. The first series of gates is used to

direct set the ILC flip-flop. Any time that a DATO or DATOB transfer is made to the command register (SEL 1
OUT LO H or SEL 1 OUT HI H) during a current tape operation (CUR DEL L), gating is qualified to set the ILC
flip-flop, because the command register cannot accept a new command while in the process of executing another
command.

When the SELR bit becomes O (SELR H) during any operation (CUR DEL L) except an off-line command, gating is
qualified to direct set the ILC flip-flop, because no command can be issued to a tape transport that is not on-line.
The remaining gates in the ILC error logic are used to produce SET ILC H, which sets the ILC flip-flop when the GO

pulse is present (GO STROBE 2 L). There are two illegal commands that can produce SET ILC H. The first

command is any command to a tape transport that has its SELR bit clear (SELR H), because when SELR is clear it
indicates the transport is off-line

The second illegal command is any write, write end-of-file, or write-with-extended-IRG command (WRITE ENB H)
that is issued when the write lock bit is set (WRL H). Writing is inhibited with WRL set, and all write commands are,
therefore, illegal.

When an illegal command produces the ILC H pulse, the pulse is applied to the gating logic for the error flip-flop in
the command register (Drawing TMA11-0-18); thus, the command register ERR bit is set simultaneously with the

status register ILC bit. The ILC bit asserts SET CUR L and SET BR L immediately (TMA11-0-06).
The ILC error bit is cleared by INIT or by occurrence of the GO pulse. When the GO pulse occurs, the GO STROBE
1 pulse occurs immediately preceding the GO STROBE 2 pulse and is used to direct clear the ILC flip-flop.

3-19

Part 11

3.7.3.2

End-of-File Bit (14) — Bit 14 is used to indicate that the tape has reached the end of the file. The EOF

flip-flop (Drawing TMA11-0-18) is set by the master tape transport and cleared by INIT or a GO pulse. The input to

the flip-flop is the FMK (file mark) signal from the master tape transport. This signal, when present, indicates that
the transport has detected the end-of-file mark on the tape. The signal sets the EOF flip-flop to produce the EOFF H

signal.

3.7.3.3

Cyclic Redundancy Error Bit (13) — The cyclic redundancy error (CRE) bit in the status register indicates

that the cyclic redundancy check has detected a parity error. This check compares the CRC character written during

a write or write-with-extended-IRG operation with the CRC character generated during a read operation.

The comparison of the two CRC characters is performed by logic within the master tape transport. If the two

characters are not identical, then the CRCE from the tape unit becomes a 1 and is applied to gating logic in the
controller error circuits (Drawing TMA11-0-18). The gating logic sets the CRE flip-flop to produce CRE H.

The CRE output of the flip-flop is applied to gating logic associated with the command register ERR flip-flop. Note,
however, that the AND gate is not qualified until both CRE and LRCSD H are present. The latter signal indicates
that the LRC character has been detected. Thus, when a CRC error is detected, the CRE bit in the status register is
set immediately, but the ERR bit in the command register is not set until the LRC is detected. This gives the
controlier time to complete the current operation before branching to an error routine by means of the interrupt.

3.7.3.4

Parity Error Bit (12) — The parity error (PAE) bit in the status register indicates that a parity error exists in

the data. The error may be in either vertical or longitudinal parity. A vertical parity error is indicated for any
character in a record; a longitudinal parity error indicates an error in a specific channel.
The parity error circuits are shown on Drawing TMA11-0-18. An AND gate output is used to set the PAE flip-flop;
this AND gate is qualified by three inputs. The first input is RDS H from the master tape transport, which is used to

sample parity. The second input is either WRITE ENB or READ, because parity is checked during both read and
write operations. The third input is either the BPE (vertical parity error) or LRCE (longitudinal redundancy check
error) signal from the transport. Thus, both vertical and longitudinal parity errors are detected during read, write,

write EOF, and write-with-extended-IRG operations. The entire record is checked, including the CRC and LRC
characters.

Note that longitudinal parity occurs when an odd number of 1s is present in any channel in the record; vertical
parity errors may be even or odd, depending on the setting of the PEVN bit in the command register.

The PAE output of the parity error flip-flop is applied to command register gating logic in the same manner as the

CRE output, as explained previously. In the case of PAE, the PAE bit in the status register is set immediately, but
the command register ERR flip-flop is not set until detection of the LRC character.
3.7.3.5

Bus Grant Late Error Bit (11) — During normal operation, the controller makes an NPR request to gain

control of the bus and initiate a data transfer (either a read or a write). If the controller is still engaged in the NPR
transfer when another NPR request is initiated, a BGL error condition occurs.

The BGL flip-flop is shown on Drawing TMA11-0-18. It is set (indicating an error) when both the NPR ENB and

NPR SET inputs are high. These inputs are received from the NPR input logic (Drawing TMA11-0-11).
If the controller receives either a WRS or RDS pulse from the master tape transport, the NPR logic circuits produce
the NPR SET H pulse. This pulse is gated through an AND gate and sets the NPR request flip-flop on its trailing
edge.

If, however, the NPR transfer is still occurring when the next NPR SET H pulse occurs, the BGL flip-flop is set to
indicate an error. The NPR request flip-flop is cleared at the end of an NPR transaction by the NPR CLEAR BBSY
H signal.

3-20

Part 11

The BGL error signal disqualifies the AND gate on the input of the NPR request flip-flop, thereby preventing any

further NPR requests until the error condition is corrected. In addition, the BGL signal is applied through gates in
the error logic (Drawing TMA11-0-18) to set the ERR flip-flop in the command register.

3.7.3.6

End-of-Tape Bit (10) — The end-of-tape (EOT) bit is set when the EOT marker is detected when the tape is

moving in the forward direction; it is cleared by the trailing edge of the EOT marker when the tape is moving in the
reverse direction. Note that the EOT bit is an error condition only when the tape is moving forward.
The EOT bit is controlled by the master tape transport. The transport logic detects the EOT and sends the

appropriate signal to the status register to set or clear the bit. When the EOT marker is detected by the transport, the
EOT H signal is applied to error logic in the controller (Drawing TMA11-0-18). An AND gate is qualified if EOT is

high, and both SPACE REV L and REWIND L are true (indicating the tape is not moving in the reverse direction).
The output of the AND gate is ANDed with the LRCSD H signal (indicating that the LRC character has been
detected) and used to set the ERR flip-flop in the command register.

Thus, the EOT bit in the status register is set or cleared as soon as the EOT marker is detected, but the ERR bit in
the command regsiter is not set until the LRC character
has been read in order to allow completion of the current
operation prior to initiating an interrupt.

3.7.3.7

Record Length Error Bit (09) — During read operations, the record length error (RLE) bit is set if the

master tape transport attempts to load another character into the controller after the number of bytes specified by
the byte record counter has already been transferred to memory. This error bit is used for long records only and is
set as soon as the byte record counter increments beyond O.

The byte record counter (MTBRC) is used to keep track of the number of data bytes loaded into memory from a
tape record. Initially, the MTBRC is loaded with the 2’s complement of the number of bytes to be loaded. Each time

the master tape transport reads a character, it loads it into the data buffer register. After a byte is transferred to
memory, the MTBRC is incremented by 1. When the last byte is transferred to memory, incrementing the MTBRC
by 1 sets it to O.

As soon as the byte record counter goes to 0, it produces a CARRY OUT 2 L signal, which sets the overflow
flip-flop (Drawing TMA11-0-18). This flip-flop had been reset because of the INIT or GO L signal. Therefore, it is
now set and produces an OVERFLOW H pulse.

This overflow pulse is applied to one leg of a 3-input AND gate. Because the RLE error can only occur during a read
operation, the AND gate is not qualified unless a read operation is being performed as indicated by a read strobe

signal (READ STB H) and the absence of a CRCS or LRCS pulse (CRCS L or LRCS L). When the AND gate is
qualified, its output changes the state of the RLE flip- flop, thereby setting it to provrde an indication of record
length error in status register bit position 09,

When the RLE flip-flop is set, the RLE L output qualifies an OR gate in the error logic circuits. The signal from the
OR gate qualifies an AND gate when the LRC character is read (LRCSD H), thereby setting the ERR flip-flop. Thus,
when a record length error occurs, the RLE bit is immediately set, and the ERR bitin the command regrster is set
after the current operation is completed.

3.7.3.8

Bad Tape Error/Operation Incomplete Bit (08) — A bad tape error occurs when a character is detected

(RDS pulse) during the gap shutdown or settling down period for all tape functions except rewind and off-line.
The BTE/OPI flip-flop (Drawing TMA11-0-17) is normally in the clear state. It is set by the output of a four-input
NAND gate. One input of this NAND gate is the RDS H pulse, which indicates that a character has been detected.
The second input to the NAND gate comes from a series of gates that are qualified if the tape unit is in either the

gap shutdown (GSD L) or settling down (SDWN L) period. The third input is in the INH BTE signal (BGL, NXM, or

ILC is true). Issuing a new GO command or an INIT pulse causes the BTE/OPI flip-flop to clear so that it can be
ready for another bad tape error.

3-21

Part 11

When the BTE/OPI flip-flop is set, it also qualifies one leg of an OR gate shown on Drawing TMA11-0-18. The
output of this gate sets the ERR flip-flop as soon as the error occurs.
- An operation Incomplete occurs when any operation, other than

a REWIND or OFF-LINE command, fails to

encounter an LRC character within 7 seconds after GO STROBE 2. Each GO STROBE 2 starts the 7-second timer.
The timer (TMA11-0-17) is stopped (reset) by LRCS, RWD or INIT + GO. The BTE/OPI bit is a fatal error requiring
the tape to be repositioned to a known point (FMK or BOT).

3.7.3.9

Non-Existent Memory Bit (07) — The non-existent memory (NXM) error flip-flop, when set, indicates that

the controller was bus master during NPR operations but did not receive an SSYN response from the slave device
within 10 us after the controller issued the MSYN signal. The ERR bit is set simultaneously
with the NXM bit, thus
terminating all operation. If the NXM error occurs during a write or write-with-extended-IEG operation, the

controller does not send the WDR signal to the master tape transport; however, the master transport writes the CRC
character (if required) and the LRC character onto the tape.
The NXM error flip-flop is part of the NPR control circuits on the M796 module and is described in Paragraph 3.5.1.

3.7.3.10

Select Remote Bit (06) — The select remote (SELR) bit, when set, indicates that the selected transport has

been selected and is on-ine. When this bit is O, it indicates that the tape transport addressed does not exist (no

transport UNIT SELECT switch set to the number specified by the program), is off-line (transport ON-LINE/
OFF-LINE switch set to OFF-LINE), or that the selected transport has its power turned off.

The select remote logic is within the master tape transport, which supplies the appropriate signal to the status
register for monitoring.

3.7.3.11

Beginning-of-Tape Bit (05) — The beginning-of-tape (BOT) bit in the status register indicates when the

BOT marker on the magnetic tape is read. As long as this bit remains O, it indicates that the BOT marker has not
been sensed. When the bitis a 1, it indicates that the marker has been sensed, and the beginning of the tape has been
reached. The ERR bit is not set when the BOT bit is sensed, because sensing of the BOT marker does not indicate an
error condition.

The beginning-of-tape logic is within the master tape transport, which supplies the appropriate signal to the status
register to set or clear the BOT bit.

3.7.3.12

7-Channel Bit (04) — This bit is always cleared by the master tape transport as the TS03 is a 9-channel

unit.

3.7.3.13

Settle Down Bit (03) — A settling down period is provided to allow the tape to fully stop prior to stopping

or starting a new operation.
This settling down period sets the SDWN bit in the status register. When the tape unit
stops, SDWN is cleared, and the tape unit ready bit is set.
The settle down logic is within the master tape transport, which supplies the appropriate signal to set or clear the

SDWN bit in the status register. A description of the SDWN bit is contained in Paragraph 2.2.
-

3.7.3.14

Write Lock Bit (02) — The write lock (WRL) bit is under control of the master tape transport. When set, it

prevents the controller from writing information on the magnetic tape. If the write lock signal is supplied from the

master tape transport (WRL H) and the controller attempts to write on-the tape (WRITE ENB H), then an AND gate
is qualified (Drawing TMA11-0-17) that sets the illegal command (ILC) flip-flop, thereby setting the ERR flip-flop
and preventing the write operation from being executed.

Part 11

3.7.3.15

Rewind Status Bit (01) — The rewind status (RWS) bit is under control of the master tape transport,

which supplies the signal to set or clear the RWS bit in the status register. The RWS bit is set at the start of a rewind
operation, and becomes a 0 as soon as the BOT marker is detected while the tape is moving in the forward direction.

Thus, when the bit is set, it indicates the tape is rewinding; when it is clear, it indicates the rewind operation is
complete. The RWS signal from the master tape transport is also used in the tape control ready logic described in
Paragraph 3.8.3.

3.7.3.16 Tape Unit Ready Bit (00) — The tape unit ready (TUR) bit is under control of the master tape unit, which
supplies the signal to set or clear the TUR bit in the status register. Whenever the selected tape unit is being used
(such as rewind), this bit is cleared. When the tape unit is stopped and ready to receive a new command, this bit is
set. The TUR signal from the master tape transport is used in the tape start control logic.
3.7.4

Byte Record Counter (MTBRC)

The byte record counter (MTBRC) is a 16-bit binary counter used to count bytes in a read or write operation and
used to count records in space forward and space reverse operations. This register and the current memory address
register constitute the M795 module shown on Drawing TMA11-0-19. A detailed schematic and associated
description of this module are presented in the PDP-11 Peripherals Handbook.
When used in a write or write-with-extended-IRG operation, the register is set
by the program to the 2’s complement
of the number of bytes to be written on the tape. Each time a write operation is performed, the register increments

by 1. After the last byte has been strobed from memory, the register increments to 0 and produces a CARRY OUT 2
signal. This signal sets the overflow flip-flop (Drawing TMA11-0-18), which produces the OVERFLOW signal. When

the next write strobe (WRS) signal occurs, the OVERFLOW signal clears the write data ready (WDR) line (Drawing
TMA11-0-07); thus, the controller lowers the write data ready line to indicate to master tape transport that there are
no more data characters in the record.

When used in a read operation, the byte record counter is set to a number equal to or greater than the 2’s

complement of the number of tape characters to be loaded into memory. A record length error (RLE), which occurs
for long records only, occurs whenever a read pulse is generated after the MTBRC is at 0. The RLE error is shown on

Drawing TMA11-0-18. The RLE flip-flop is set by the output of an AND gate that is qualified if the MTBRC has

incremented to 0 (OVERFLOW H), a read pulse is generated (READ STB H), and there is no CRCS or LRCS pulse
(~CRCS + LRCS).

When the MTBRC is used in a space forward or space reverse operation, it is set to the 2’s complement of the
number of records to be spaced. The counter is incremented by 1 at LRC time, regardless of direction of tape
motion. A new GO pulse is sent to the tape unit during the SDWN time if the MTBRC is not yet at 0. This logic is
shown on Drawing TMA11-0-05. Either direction (SPACE FWD or SPACE REV) qualifies an OR gate to produce

SPACE H, which is one leg of an AND gate. The other leg of the gate is qualified if the MTBRC is not at O

(OVERFLOW L), and there is no end-of-file mark (EOF F L). The output of this AND gate qualifies another AND
gate, provided settle down is present (SDWN H). When this gate is qualified, it triggers the logic that produces the

GO pulse.
When the last record is reached, the byte record counter increments to 0 and produces the CARRY OUT 2 pulse.
This pulse is ANDed with SPACE H (Drawing TMA11-0-06), passes through an OR gate, and direct sets the Transfer

done flip-flop. The transfer done flip-flop output, DONE (1) H, is then ANDed with TUR H and applied to the
ready control logic to direct set the control unit ready (CU RDY) flip-flop. Setting the CU RDY flip-flop indicates
that the controller is ready to receive a new command, because the space operation is now complete.

3.7.5 Current Memory Address Register (MTCMA)
The current memory address register specifies the bus or memory address to or from which data is to be transferred
during write or read operations. The current memory address register (MTCMA) and the byte record counter

(MTBRC) constitute the M795 module shown on Drawing TMA11-0-19. A detailed schematic and associated
description of this module are presented in the PDP-11 Peripheral Handbook.

3-23

Part 11

Before issuing a command, the program loads the MTCMA with the memory address that is to receive the first byte
of data (read operation) or the memory address from which the first byte is to be taken (write operation). After

each memory access (read or write), the MTCMA is immediately incremented by 1. This incrementation is caused by
the NPR CLR BBSY signal, which indicates the bus transfer is completed.

The logic shown on Drawing TMA11-0-20 is used to carry the bus address register incrementation to extended
address bits 16 and 17 in the status register. When incrementation of the

MTCMA causes the register to contain all

1s, the next clock pulse sets the current memory address register to all Os and produces a CARRY OUT 3 pulse,

which sets extended address bit 16. The MTCMA then continues incrementing until another CARRY OUT 3 pulse is
produced, which sets extended address bit 17.
The logic shown on Drawing TMA11-0-15 is used to select the low- or high-order byte of the data register. This is
necessary because the MTCMA increments by 1 (byte addresses). Each time a byte transfer is completed, the CMA

BIT 00 flip-flop is clocked by the NPR CLEAR BBSY signal.

The CMA BIT 00 flip-flop initial condition (set or

reset) is determined by DOO when the MTCMA is loaded. The state of the CMA BIT 00 flip-flop determines which
byte is transferred by producing alternate LO DATA BYTE and HI DATA BYTE signals to the data register until the
desired data transfer function is complete. When the functlonis complete, the controller CU RDY bit indicates that
the controller is ready to accept a new command.

3.7.6

Data Buffer Register (MTD)

The data buffer register is used as a temporary storage device during read and write operations. During read
operations, it stores characters from the tape prior to loading them into memory; during write operations, it stores

data prior to writing on the magnetic tape A functional descnptlon of the data buffer reg1ster is given in Paragraph

2.2.
The inputs to the data buffer are shown on Drawing TMA11-0-16. If a read operation is being performed, data is

loaded into the buffer from the tape transport data channels. Each channel is connected to one leg of an AND/OR

gate. The other leg to the gate is controlled by a flip-flop. The read operation (indicated by READ STB L) sets this
flip-flop. The high (1) side of the flip-flop qualifies four of the AND/OR gates to produce the DATA BFR IN BIT H

signals for bits 00 through 03. The low (0) side of the flip-flop produces the signals for bits 4 through 7. Thus,
during a read operation, the data from the tape channels is gated through to the input of the buffer register and

strobed into the register by the DATA BFR STB signals. As shown on the data buffer drawing (TMA11-0-20), the

first four bits are strobed in by the DATA BFR STB 1 signal; the second four bits are strobed in by the DATA BFR
STB 2 H signal.
During write operations, data from the bus is strobed into the data buffer register. The low byte is applied to one

series of gates, the high byte to another series of gates (Drawing TMA11-0-16). Each bus line is applied to one input
of a two-input AND/OR gate. The other leg is qualified only if the appropriate byte has been selected. This selection
is determined by two AND gates. One is qualified if the current memory address is even (CMA 00 L), which

indicates a low byte. The other is qualified if the current memory address is odd (CMA 00 H), which indicates a high
byte. The data from the bus lines is then strobed into the register in the same manner as before.
The data buffer output logic is shown on Drawings TMA11-0-14 and TMA11-0-09. The logic shown on Drawing

TMA11-0-14 is used when the output of the data buffer is to be applied to the bus. Each output of the data buffer is
applied to one leg of a two-input AND gate. The other leg is qualified by either the HI DATA BYTE L or LO DATA
BYTE L signal, depending on which byte has been selected.

The logic shown on Drawing TMA11-0-09 is used when the output of the data buffer is to be applied to the tape

unit for writing. When the core dump mode is not used, one byte in memory corresponds to one tape character. In
this instance, the output of the data buffer is gated through to the tape transport write lines. Data buffer bits 07

through 00 correspond to lines WDO through WD7, respectively. -

3-24

Part 11

When the core dump mode is used, one byte in memory corresponds to two tape characters. When the write strobe
(WRS) is issued, it sets the even character flip-flop (Drawing TMA11-0- 11). This clears the EVEN CHAR L pulse,
which gates data buffer bits 00 through 03 to write lines WD7 through WD4 (Drawing TMA11-0-11). The flip-flop
then clears, and asserts EVEN CHAR L which gates bits 04 through 07 to lines WD7 through WD4, respectively.

During normal read operations, all six tape data channels are read and gated through the data buffer input logic for
loading into the data buffer register. When the core dump mode is used, however, the logic operates in a different
manner because one byte consists of two 4-bit characters. It is therefore necessary to read tape channels 0—3 twice,
loading the first tape character into the low part of the buffer register and the second tape character into the high
part of the buffer. ThlSis accomplished by the loglc shown on Drawing TMA11-0-16.

When the first tape character is read, the AND/NOR gates having channels 0—7 as inputs are all qualified by the
output of the READ STB flip-flop, and the data from the tape is gated through to become DATA BFR IN BITS
0—7. These bits are strobed into the data buffer register by DATA BFR STB 1 and 2 as shown on Drawmg
TMA11-0-20. Up to this time, data has been read from the tape in a normal manner.

When the next tape character is read, the first set of AND/NOR gates is still qualified and produces DATA BFR IN

BITS 0—3. However, these bits are not loaded into the buffer register, because the required strobe signal is no longer
present. The low part of the buffer, thus, contains data read from channels 0—3 of the previous tape character.

The second series of AND/NOR gates, which normally receives inputs from tape channels 4—7, are now inhibited
due to the CORE DUMP L signal. The other AND inputs to these gates, which receive data from tape channels 0—3,
are now qualified by an enabling AND gate having CORE DUMP L as an input. As a result, this series of gates causes
the data from tape channels 0—3 to become DATA BFR IN BITS 4—7. These bits are strobed into the high part of
the buffer and override the data previously stored in this part of the buffer. Thus, the two 4-bit characters are now
in the buffer as a single 8-bit byte.
3.7.7

TSO03 Read Lines (MTRD)

The TSO3 read lines are assigned a standard bus address and are actwated by the address select loglc When these
lines are selected for use, data from the lines is gated to appropriate data bits on the bus, as shown on Drawing

TMA11-0-14. The 16 bits that constitute the read lines are read-only bits with the exception of the character select

(CHAR SEL) and bad tape error generator (BTE GEN) bits (bits 14 and 13, respectively). Bits 15 through 13 are
described below; bits 11 through 09 are unused; and the remaining bits are described in Paragraph 2.2.
Bit 15 is the timer bit, which is used for diagnostic purposes by measuring the time duration of the tape operations.
The timer logic is shown on Drawing TMA11-0-06. This logic produces the timer signal (TIMER H), which is a
100-us signal with a 50 percent duty cycle.

Bit 14 is the character select bit, which is used to select the last character of a record that is to be loaded into the

data buffer. When this bit is loaded with a 1, the last character loaded into the buffer is the LRC character. When
this bit is loaded with a O, the last character loaded in the buffer is the CRC character.

Bit 13 is the bad tape error generator, which is used to check the bad tape error logic. When loaded with a 1, this bit
sets the CU READY flip-flop, thereby causing a premature gap shutdown period. When this portion of the tape is
then read, it produces a bad tape error indication.

Bit 12 is the gap shutdown bit. It is a read-only bit and indicates a gap shutdown period when itisa 1.
Data on the TSO03 read lines is gated to the bus by the logic shown on Drawing TMA11-0-14. When the read lines are

selected for use (SEL 5 IN L), an inverter output qualifies one leg of a series of gates. The other leg of each gate is
connected to one of the channels in the tape transport. The output of these gates are then fed through drivers to the

bus.

3-25

Part I1
3.8

TAPE CONTROL

The TMA11 Controller performs four tape control functions: unit selection, function control, ready control, and
start control.

3.8.1

Unit Selection

The unit selection logic determines which tape transport is to be used to perform the designated operation. Although

two tape transports may be handled by one controller, only one transport may be selected at any given time. The

tape transport selected is determined by bits 10 through 08 of the command register as shown on Drawing
TMA11-0-10. These bits are set or reset in accordance with program inputs on bus data lines D10, D09, and D08
each time the register flip-flops are clocked by SEL 1 OUT HI. The register outputs are then applied to decoder logic
in the master tape transport via select lines SEL 2, SEL 1, and SEL 0. Because only two transports can be connected

to each TMA11, the master tape transport decoder logic only accepts two octal codes as legal unit select line inputs.

Octal code 000 selects transport number 0; octal code 001 selects transport number 1. Any other octal codes place

both transports in the deselect mode so that no tape operations can be performed,
3.8.2

Function Control

The function control logic specifies which of eight functions is to be performed by the selected tape transport. A

description of each of the eight functions is given in Table 3-1. The function selected is determined by bits 03
through 01 of the command register as shown in Drawing TMA11-0-07. These bits are set or reset in accordance with
program inputs on bus data line D03, D02, and DO1 each time register flip-flops are clocked by SEL 1 OUT LO. The

flip-flop outputs are applied to a binary-to-octal decoder which decodes the eight functions. The selected function
line is then asserted to the master tape transport.

3.8.3

Ready and Start Control

The TMA11 ready and start control circuits basically consist of the logic associated with two bits in the command
register. The ready logic is controlled by the CU RDY bit (bit 07) and is described in detail in Paragraph 3.7.2.6. The
start control logic is the GO bit (bit 00) and is described in Paragraph 3.7.2.10.

3.9

TIMING DIAGRAMS

Timing diagrams of various tape operations are shown in Figures 3-5 through 3-10. These diagrams portray specific
tape operations such as reading a record of three data characters, etc. The purpose of these diagrams is to illustrate

overall TMA11 operation as described in previous paragraphs.

3-26

Part 11

SEL

2 OUT LOH

DOO

BIT H

GO STROBE 1 H

GO STROBE 2 H

CU READY

CUR DEL H

GEP

GED

GED GED

CED

NS G

\\
11-0382

Figure 3-5 Start of Tape Operation

TUR H

CU READY

YII

—
o

SDWN H

GO
MTBRC

[]

77775

N
777776

N
7777

000000
11-0385

Figure 3-6

Spacing Forward Three Records

3-27

Part 1]

TUR H

l Ao
*

LRC H

GO H

MTBRC 777775 |/

——

CU READY H

L
V
aun

777776

|' 777777

000000
11-0387

Figure 3-7

Spacing Reverse Three Records

TURHI

- CU READY H —L

SDWN H

s J}x
3

LRC H

etS

BTE

—

GO H __fl enfe
f
e

MTBRC

777775
]

ERR H

)

777776

1H-0386

Figure 3-8

Spacing Forward Three Records, Bad Tape Error
Appearing in First Record

3-28

Part 1]

CU READY H |

le— 10005 —|

)

le—400us ——»}e——400 us——»]

RDS H_
NPR

—

~fJ l

ENB H

MASTER H —

CLR BBSYH

MTBRC

. 777123 I 777124 P 777125 I 777126

MTCMA _

CRCS

123123 _l 123124

I .

123125 l 123126

. l.‘

~—q

CRCE

LRCS e

—

)

l
r=-

LRCE

P
L
|

r—°
VPE

71(L

r—-

’l,gl

'J’LL

r—-y

r—=

—71,’,!

11-0383

Figure 3-9

Reading Record of Three Data Characters

3-29

Part 11

READY H

WRS

"—100115—’{

GO STROBE 2H

_fl

MTBRC

777776

777775

WDR

OVERFLOW

[L([

CLR BBSY H

TM~

RDS H

|7 7 7 }
OOOOOO

‘l I /4 I | ”

CRC ERROR

I |,A

I I

I |

CRCS

)

fo—— 406;.15 ——»le——400us ——]

~—=

”

LRCS

]

P
|

LRC ERROR
=

VPC ERROR

r=-

]

r=-

]

A '

2
~==

)

] ys

‘
~— -

[

1
11-0384

Figure 3-10

Writing Record of Three Data Characters

3-30

Part 11

CHAPTER 4

MODULE DESCRIPTION

4.1

INTRODUCTION

This chapter provides information on the logic modules used in the TMA11 DECmagtape Controller. The position of
the modules within the mounting box is shown on Drawing TMA11-0-02.

A list of all TMA11 Controller modules is presented in Table 4-1. This table lists the modules in numerical order, the
quantity of each type used in the system, and the name of the module. The last column indicates the DEC document
containing the detailed description of that particular module.

Note that it is beyond the scope of this manual to provide information on any of the modules used in the master
tape transport logic.

4.2

DEC LOGIC

Except for cable and jumper modules, all of the modules used in the TMA11 Controller are M-series logic modules.
The M-series are high-speed, monolithic integrated circuit modules, employing TTL logic (transistor-transistor logic).
These circuits provide high-speed, high-fanout, large-capacitance drive capability, and excellent noise margins.

A general description of DEC logic and detailed circuit descriptions of TTL logic gates are provided in DIGITAL’s
1973-74 Logic Handbook.

4.3

MEASUREMENT DEFINITIONS

Timing is measured with the input driven by a gated pulse amplifier of the series under test and with the output
loaded with gates of the same series. Percentages are assigned as follows:

O percent is the initial steady-state level,

100 percent is the final steady-state level, regardless of the direction of change.

Input/output delay is the time difference between input change and output change, measured from 50 percent input
change to 50 percent output change. Rise and fall delays for the same module are usually specified separately. Rise
time and fall time is measured from 10 percent to 90 percent of waveform change, rising or falling.

4.4

Input loading and output driving are specified in unit loads, where one unit load is 1.6 mA by definition. The inputs

to low-speed gates usually draw one unit load. High-speed gates draw 1-1/4 unit loads, or 2 mA.

4-1

Part 11

Table 4-1

Module Utilization

Module Number

Quantity Used

Title

Reference

M105

Address Selector

Ml111

Inverter

MI112 .

NOR Gate

M113

Ten 2-input NAND Gates

M115

Eight 3-input NAND Gates

M117

]

Six 4-input NAND Gates

M121

AND/NOR Gate

M127

2-2-2-3 AND/NOR Gate

—

M149

9x2 NAND Wired OR Matrix

M163

Dual Binary-to-Octal Decoder

M203

Eight Reset/Set Flip-Flops

M205

Five “D” Flip-Flops

M216

Six Flip-Flops

M239

Three 4-bit Counter Registers

—

M304

Four One-Shot Delays

—

M307

Integrating One-Shot

—

M627

NAND Power Amplifier

—

2
2

—

G736

Jumper Module

M7821

Interrupt Control

M784

Unibus Receiver

M785

Unibus Transceiver

M7854

OPI Module

M795

Word Count and Bus Address Register

M796

Unibus Master Control

M797

M798

Unibus Drivers

REFERENCES

PDP-11 Peripherals Handbook

DIGITAL’s 1973-1974 Logic Handbook

4.2

Part I1

APPENDIX A

MASTER TAPE TRANSPORT SIGNALS

A.1

SIGNALS FROM TS03 TO TMA11 CONTROLLER
Mnemonic

Name

RDO — RD7

Read data signals.

RDP

Read parity bit.

SDWN

Tape settle down. This is the time between a stop command and the actual

stopping of the tape.
TUR

Tape unit ready. This signal is true when the selected tape unit is stopped and
SELR is true.

SELR

Select remote. This is true when unit is selected and 1s on-line.

RWS

Rewind status. This is true when selected uhit is rewinding.

7CH

‘7-channel. Alwéys false.

WRL

Write lock. Prevents writing on tape.

BOT

Beginning of tape.

EOT

End of tape.

WRS

Write strobe. Requests a character for writing.

RDS

Read strobe. Present for both read and write operations.

FMK

File mark.

CRCS

CRC strobe. Appears with CRC character.

LRCS

LRC strobe. Appears with LRC character.

VPE

Vertical parity check error. Sampled with RDS.

LRCE

Longitudinal redundancy check error. Sampled with LRCS.

CRCE

Cyclic redundancy check error. Sampled with RDS.

Part I

A.2

SIGNALS FROM TMA11 CONTROLLER TO TSO03

| Mnemonic

Name

Write data lines.

SET

‘Required to start any tape operation (derivative of GO command).

FWD

Tape forward.

REV

Tape reverse.

RWD

Tape rewind

WRE

Write enable.

PEVN

Even parity.

DEN 8

Density bit. True for 800 bpi 9-channel.

DEN
5

Density bit. True for 800 bpi 9-channel.

See Note

NOTE

TSO03 ignores DEN 8/5 input signals; it always Operatés at
800 bpi, 9-channel.

WFMK

Write file mark.

Wriie-extended-lRG. True for both write-extended-IRG and WEMK functions.
SEL O

SEL 1

Tape unit select.

SEL 2
WDR

‘Write data ready.

CINIT

Initialize.

PART III

TS03 DECmagtape TRANSPORT

Part III

CHAPTER 1

GENERAL INFORMATION

1.1

GENERAL DESCRIPTION

The

TS03

DECmagtape

Transport

a synchronous

digital

tape

unit

capable

of reading

and

writing

industry-compatible tapes and read-after-write operation. The unit is designed for applications requiring high
reliability at moderate tape speeds. Typical applications include operation with minicomputers, high-speed data
collection systems, and computer peripherals.

The TSO03 contains all the electronics nécessary to accept, format, and record data and to retrieve, check, and output
data. To accomplish this, the TSO3 performs the following functions:
Tape motion control

Tape formatting
Parity generation

Cyclic redundancy check (CRC) character generation
Longitudinal redundancy check (LRC) character generation
Interrecord gap control
Even parity zero character conversion

Status monitoring
Parity, CRC character, and LRC character error detection
File protection

The TSO3 is a 9-track, 800 bpi unit with a standard tape speed of 12.5 in. per second and a data transfer rate of
10 kHz.
1.2

PHYSICAL DESCRIPTION

The transport portion of the TSO3 is completely housed in a 19 in. wide by 17 in. deep by 9 in. high chassis; the
adapter portion is contained on a hex height module which mounts just below the chassis in a special mounting

bracket. The transport (Figure 1-1) contains the read/write and motion control electronics. The adapter module
(Figure 1-1) contains the formatting, parity, CRC, gap control, and error detection electronics.

1.3 ELECTRICAL AND MECHANICAL SPECIFICATIONS
Tape (Computer Grade)
Width

Thickness

0.5in.(1.27 cm)

1.5 mils (0.038 mm)

Tension

8.0 0z (227 g)

Reel Diameter

Capacity

To 7.0 in. (17.78 cm)
600 ft (182.40 m)

Reel Hub

3.69 in. (9.37 cm) dia. (per industry standards)

1-1

Part 1T
Reel Braking

Recording Mode (Industry-Compatible)“
Tape Drive
'

Dynamic

NRZ1

~ Single capstan

Tape Speed

12.5 in./sec

Instantaneous Speed Variation

+3%

Long-term Speéd Variation

+1%

Start/Stop Displacement

0.1875in. (0.476 cm)' | ‘

Start/Stop Time at 12.5 in./sec

30 ms

Rewind Speed

75 in./sec (190.5 cm)

Magnetic Head Assembly (Wnte to Read Gap Dlsplacement)
Dual Gap Nine-Track Read After Write

0.15in. (0.38 cm)

Interchannel Displacement Error (Measured with Master Skew Tape)
Write

150 pin. (3.8 um) maximum

Read

150 uin. (3.8 um) maximum

Frase Head

Full width

Load Point and End-of- Tape Reflectlve Strip Detection

Photoelectric

(Industry-Compatible)
Broken Tape Detection

Photoelectric

- Dimensions (Figure 1-2)

Transport Mounting (Honzontal)

Standard 19 in. (48.26 cm) RETMA rack

Height

8.72 in. (22.14 cm)

Width

Depth (From Mounting Surface)

11438 in. (36.53 cm)

Depth (Overall)

16.88 in. (42.88cm)

Weight

351b (15.85 kg)
45 1b (20.38 kg)

Shipping Weight

Operating Environment
Ambient Temperature

Relative Humidity (Noncondensing)
Altitude

Power Requirements

+2° to +50° C
15% to 95%

To 30,000 ft (9120 m)

115/230 Vac, 50 to 500 Hz, single phase
200 VA nominal; 300 VA maximum

1-2

Part 11T

7461-2

Figure 1-1

TS03 Transport and TSO3 Adapter Module (M8920

)

1-3

Part 111

(43 18)

—

LAg FegruR g vu e R

=—N00000

v v p v LPJLPJ”LrJ.LJ#

O0O0A0r

Y
NOTE:

DIMENSIONS

DINENSIONS

FIRST SHOWN ARE

IN PARENTHESES ARE

INCHES.

IN CENTIMETERS.

—_—

CONTROL PANEL RETAINING

?&gGgF(szé OUT LOWER
NEL FOR ACCESS

TO RACK MOUNTING SCREWS)

MOUNTING HOLES ARE FOR
ZERO NONTILT TYPE SLIDE

NO. C30C-14 (NOT SUPPLIED
WITH UNIT) (DIMENSIONS
TYPICAL ON BOTH SIDES)

Y‘—.

--—

)

MOUNT ING
SURFACE

——

==
-

DUST COVER OPENS
TO

APPROXIMATELY

110

DEGREES,

[

éf

¢’

]

5,06

;

]

)

]

(12.85)

(22.14)

]
—

4
S
-

N\
(§j§§);

e 3.62 ol
3.62 _

(9.19)

(9.19)°

14,38
(36.53)

(42.88)

5,75 TYp

°g

lzzs‘Z}P

(14.6)

1.48(3.75)Typ

40 g
(3.55)

l
|

~ .25(.63)

(5.71)

(.93)

2 25 Trp

;

—-a-,

DETAIL "A"

.45

(1.14)

TYPICAL SLOT
PATTERN

ota—
2.34
TR
16.88

121541\)!9

e o

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SEE DETAIL "A"

e (163)
- 25

19.00

'
(48.26)

11-3046

Figure 1-2

TSO3 Transport

Physical Dimensions
1-4

Part 111

CHAPTER 2
THEORY OF OPERATION

2.1

INTRODUCTION

This chapter provides a complete description‘ of the TSO3 to the functional block level. Functionally, the TSO3 can
be divided into four major blocks (see Figure 2-1):
Adapter Logic
Transport Control Logic
Servo System

Data Section

The adapter logic interfaces the TSO3 transport to the controller. In response to commands from the controller, the

adapter:

Formats the data on the tape.

Generates motion signals to start and stop the tape drive, to move the tape forward or backward, and to
move the tape at normal read/write speed or at a higher speed during a rewind operation.

Generates strobes to wfite daté and CRC_, LRC, and file mark charact‘evrs on tape.

Generates write strobes to notify the controller to send the next write character.

Transmits read strobes received from the tape transport out to the controller.

Generates parity and the CRC characters for recording on the tape.

Performs parity, CRC, and LRC error checks on all read data.

Detects file mark records on the tape and notifies the éontroller.

The control logic:
1.

Controls ramp voltage to the servo, thereby controlling direction and speed of tape movement.

Generates control signals to the data section which enable and disable the read and write amplifiers.

Controls the erase head.

Part 111
.

MASTER

CONTROL

SELECT
ITCH
SWITC

TO/FROM

CONTROLLER

INIT

CAPSTAN
MOTOR
POWER

X PO\

PANEL
SWITCH ES

DRIVE
NUMBER

ACH
FEEDBACK

CAPSTAN
MOTOR

s
SERVO
QUTPUT ) VsTEm | REEL

SELECT

MOTOR POWER

BUFFER ARM | REEL

ON LINE

FEEDBACK

MOTOR

REWIND

WDR

WRITE DATA

SEL

(2:9)

SEL

(SLT)

MOTION COMMANDS

REV s MOT (SRC)

(FWD, REV, WRE

WXG,WFMK,

RWND)

WRE

WRS

LTCH

‘

(SWS)

STATUS (LOAD POINT,END |

7 CH

ADAPTER |

_RDS

Logic

READ DATA

TRANSPORT |

OF TAPE,RWNDG,

coNTROL

XPRT RDY,WRLCK
)

EHREA:DE

¢« MOT (SFC)
FWD

RNN

BUSY

LP (BOT)

LOGIC

OFF LINE PLS (OFF C)
REWND PLS (RWC)

StT
WRDY

DRIVE ON LINE

~ TUR

_ SELR
_REWIND STATUS
_ BOT

_EOT

REC

L SDWN
LRCS

ACRCS

(WDS)

LRC PLS (WARS)

’

‘

)

WD (@.7,P)

~FMK

_ERRORS

WAL

RO TP}

DRIVE RD STRB (RDS)

WRITE
::D HEADS

DATA
SECTION

READ

| HEADS

1-3068

F‘igure 2-1 TSO03 Block'Diagram
The servo system consists of the electronics and electromechanical components that are required to advance the tape

past the magnetic heads at accurately controlled speeds while maintaining constant tape tension. The servo system is
composed of two subsystems: the capstan subsystem, which drives the tape at accurately controlled speeds and the
reel servo subsystem, which maintains constant tape tension.

The data section consists of read and write amplifiers, output drivers, and timing and control logic. The data section

controls the read/write heads and generates a read data strobe that is used by the adapter logrc to transfer data out
to the controller.

2.2 TRANSPORT OPERATIONS
The TSO03 performs three basic types of operations: write, read and rewind; all other operations are simply
variations. The following paragraphs explain how these operations are performed (Figure 2-1).

2-2

Part 111

Once the controller initializes the adapter logic by asserting INIT, the controller must select the transport (drive O or
1) and parity sense (odd or even) before any operations can be performed.

When the controller selects a transport via the SEL lines, the adapter asserts SEL (select) to the selected transport

and, if the transport is on-line (ON LINE indicator illuminated), DRIVE ON-LINE is asserted to the adapter and the

adapter asserts SELR (select remote) back to the controller. If the selected transport is ready [i.e., tape is loaded and
is not rewinding or advancing to the load point (BOT marker)], the transport also asserts XPRT RDY (transport
ready) to the adapter, causing the adapter to assert TUR (tape unit ready) to the controller. With these conditions
satisfied, the controller can now raise the command lines required to perform a given operation and asserts SET to
‘initiate that operation.

22.1 Write Operation
To perform a write operation, the controller raises WRE (write enable) and FWD (forward) and asserts SET. The

adapter logic responds by asserting FWD-MOT (forward motion) and WRE LTCH (write enable latch) to the
transport control logic, begins to count off a delay, and clears TUR to the controller. The transport logic responds

by asserting WRDY (write ready) and SLT (select) to the data section and a ramp-up, forward motion voltage to the
servo system. Hence the servo system starts moving the tape forward at normal speed and the data section is enabled.
The adapter then completes the delay count. (The delay allows the tape to accelerate to normal operating speed and
ensures that the heads have moved well past the BOT marker when starting from a BOT position.) Assuming the
controller will have placed a character on the write data lines and asserted WDR (write data ready) to the adapter
when the delay expires, the adapter immediately generates a parity bit and a write strobe (REC) to load the data
character with parity into the data section. The data section immediately records the character, reads it back, and
places it on the read data lines to the adapter along with a read strobe. The adapter then checks the read character
for parity errors and outputs the character back to the controller, along with a read strobe (RDS). The adapter then
asserts a write strobe (WRS) to the controller to request the next character. The controller then places the next
character on the write data lines. This process is repeated over and over until the last character is recorded and the
controller clears WDR.

When WDR clears, the adapter generates two more write strobes to properly terminate the record. REC is asserted

along with the CRC character to the data section for recording. Then the LRC PLS is generated to the data section
to generate the LRC character, which is then recorded. The adapter reads the two check characters, outputs them to

the controller, along with the CRC and LRC strobes (CRCS and LRCS), and checks for CRC and LRC errors. If a
CRC or LRC error is detected, the respective error line is also asserted to the controller.
Next, the adapter terminates the write operation by clearing FWD+-MOT to the transport control logic, asserting

SDWN (settle down) to the controller and counting off deceleration delay. When FWD-MOT clears, the transport
control logic applies a ramp-down voltage to the servo system and clears the WRDY and SLT lines to the data
section. Hence the servo system stops the tape and the data section stops writing and reading data.

When the deceleration delay expires, the adapter asserts TUR and clears SDWN to the controller. Thus the TSO3 is
ready to perform the next operation.
2.2.2

Read Operation

To perform a read operation, the controller raises FWD and asserts SET. The adapter logic responds by asserting

FWD+MOT to the transport control logic, starting the delay count and clearing TUR. The transport control responds
by asserting SLT to the data section and a ramp-up voltage to the servo system. The servo system then begins to
move the tape forward, and the read portion of the data section is enabled. The adapter completes the delay count
and begins to accept read data, along with read strobes from the data section. Each character read is checked for a

parity error and output to the controller, along with a read strobe. Upon reading the final two characters (normally a
CRC and LRC character) and checking for errors, the adapter clears FWD+-MOT, asserts SDWN to the controller, and
begins to count off a deceleration delay. When FWD+MOT clears, the transport control logic applies a ramp-down
voltage to the servo system to stop tape motion and clears the SLT line to the data section to stop reading.

2-3

Part 111

When the deceleration delay expires, the adapter asserts TUR and clears SDWN to the controller.
2.2.3

Rewind Operation

To perform a rewind operation, the controller asserts RWND (rewind) and SET. The adapter logic responds by
asserting REWND PLS to the transport control logic. The transport control logic responds by clearing XPRT RDY,
asserting RWNDG to the adapter and applying a high-speed reverse, ramp-up voltage to the servo system. The

adapter asserts RWS (rewind status) to the controller while the servo system rewinds the tape past the load point.
The transport control logic then applies a forward motion ramp-up voltage to the servo system, which moves the

tape forward to the load point and stops the tape. The transport control logic then clears RWNDG and asserts LOAD
POINT and XPRT RDY to the adapter. The adapter clears RWS and asserts TUR to the controller.
2.3

FUNCTIONAL BLOCK DIAGRAM DESCRIPTION

2.3.1

Adapter Logic

Figure 2-2 is a block diagram of the adapter logic. The diagram separates the adapter logic into six areas and shows
adapter data and signal flow.
As stated previously, the adapter logic enables software control of the TSO3 DECmagtape Transport. Referring to

Figure 2-2, note that the control logic responds to inputs from the controller by generating control signals for the

write logic and the read logic as well as control signals for the tape transport. These control signals control the
reading and writing of data, tape motion, and interrecord gaps. In addition, the control logic provides clock signals

(TIME PLS 1,0) for the adapter logic, monitors transport status lines, and initializes the adapter logic whenever INIT
is asserted by the controller.
In response to inputs from the control logic and the controller, the write logic and read logic transfer data to and
from the tape transport. The write logic accepts write data from the controller and monitors the controller

C WDR

(write data ready) line. If the C WDR line is true, the write logic generates parity, write strobes (REC), CRC
characters, LRC strobes (LRC PLS), and the file mark character and outputs this information to the tape transport

via the transport drivers for recording. The read logic accepts read data from the transport and monitors the RD
STRB line. Using RD STRB and the read data, the read logic detects data records and file mark records. In addition,
checks are made for parity, CRC, and LRC errors.

2.3.1.1

Control Logic — The control logic can be divided into nine logic sections (Figure 2-3). Each section

performs a specific function in performing the eight different operations the control logic is capable of. Table 2-1
lists those operations and indicates the commands that must be issued by the controller to initiate them.
To prepare the control logic to receive commands, the controller asserts C INIT. Asserting C INIT generates

SYSTEM RESET, which clears the command status register and resets the motion flip-flop in the read/write control
logic.

The controller then issues the commands by asserting the command lines and generating a C SET pulse. The
command processing sequence that results is illustrated in Figure 2-4. Note that different operations require that

different delays be generated by the delay counter (Table 2-2). These delays are incorporated for the following
reasons:

To allow time for the tape to accelerate to normal operating speed from a stopped condition.

To allow time for the tape to decelerate from normal operating speed to a stopped condition.

To allow time for the transport to move the tape BOT marker well past the read/write heads when
starting from the BOT position.

To enable the writing of industry-compatible extended interrecord gaps and file marks.

Note that the rewind operation does not require a delay.

Part 111

BWD

C WDR
FROM

C WFMK

CONTROLLER

WRITE DATA

WD (7:0,P)

(7:0,P)

)

B WD (7:0,P)

B LRC PLS

LRC PLS

PEVN LTCH

(D8,D9)

REC

MOT
TIME PLS 1,0

B REC

B FWD*MOT

DF::JV;;?S

"B FwD- Mo

B REV.MOT

WRITING

TO CONROLLER

DRIVER

FROM

_ c7cH

; C WRS
_ C SELR

_ cEoOT
;c RWS
C SDWN
~ CTUR

C SEL (2:0)
CFWD
C REV
C PEVN

OFF LINE PLS
SEL DRIVE |
SEL DRIVE O
WRE LTCH

B SEL DRIVE 1
B SEL DRIVE O
B WRE LTCH
B WRE LTCH

COS;T\%;:R

(03]

CONTROL
LOGIC

C WXG

(D3-D7)

RWND

*T
t
t
;

READING

MASTER SEL SWO
B DRIVE O ON LINE

;22';

B DRIVE]

TRANSPORT

ON LINE

BOT

B LOAD POINT

EOT

| B LOAD POINT

WRITING ‘VSSIOTAE L0GIC)
INHIBIT STATUS

RWS
RDY

ON LINE

RD STRB

BEND OF TAPE
| B END OF TAPE
B RWNDG

PEVN LTCH

MOT

;gégf\fgg

TIME PLS O

LRC RD TIME

RECORD ACT

INH VPE DET

SET

ENB LRCE DET

]

T0
DRIVE 1
AND DRIVEO

B OFF LINE

EOT
RWS
SDWN
TUR

) C LRCS

REV* MOT

B RWND PLS

RWND PLS

C WRE

B RWND PLS

FWD* MOT

CINIT

C WFMK
4

TRANSPORT

STRB

(D13)

| BRWNDG
B XPRT RDY
| B XPRT RDY
B DRIVE O RD STRB
8 RD(7:0. P)

DATA

FWD LTCH

CRC RD TIME

READ

CCRCS

CRC RD TIME

COMP RD STRB

LOGIC

CRDS

COMP RD STRB

| BDRIVE 1 RDSTRB

READ

EOR RD TIME

FROM

DRIVE. 1
AND DRIVE O

(
N

)

[BRD(7:0,P)

(D10-D12)

o+ CFMK

FMK

BAD PARITY

FILE MARK DETECTED

B WRLCK

| BWRLCK

EIGHT SPACES
CVPE

CLRCE

LRC REG NOT ZERO

¢ CRCE

CRCE

" JCRD (7:0,P)

READ DATA

L_cBoT

BOT

< CWRL

WRL
NnN-3066

Figure 2-2

Adapter Block Diagram

2-5

Part 111

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2-6

Part 111

Table 2-1

Operations Versus Commands Required
Controller Commands Required

Operations

Write Extended
Gap (WXG)
|

Rewind, Off-Line

Rewind

Write

Reverse |
(REV)
|

Rewind
(RWND)

1B
'

‘

X
:

)

Space Reverse

Read

Space Forward

Forward
(FWD)

Interrecord-Gap

Write File Mark

Write Enable
(WRE)

(WFMK)

Write-with-extended

Write File
Mark

Table 2-2

Commands and Corresponding Delays

Commands

‘

ROM Address

2s Complement

Delay (ms) |

Delay (in.)

20000

819.2

10.05

25000

563.2

6.85

31400

332.8

3.97

33400

256.0

of Delay

(WTMK + WXG)-BOT

144

WRE-FWD-BOT

163

(WTMK + WXG)-BOT

FWD-BOT

125

WRE-FWD+<BOT

FWD-BOT
- STOP-WRE

STOP-WRE

~
|

37230
|

245,265

20g,228

37423

37754

37t

- 23.7
|

3.01

357
20

.
|

0.256
0.117

0.025

0.001

Due to the similarities of the eight operations performed by the control logic, the following paragraphs will first
explain a write operation and then point out the differences between a write operation and the other operations.

Write Operation (Figure 2-5) — To initiate a write operation, the controller must raise the C WRE and C FWD lines
and issue the C SET pulse. Assuming the tape is positioned at the BOT marker, the control logic responds to these
inputs by presetting the delay counter to 25000 and then asserting MOT, WRE LTCH, and FWD-MOT and clearing
TUR. When FWD-MOT asserts, the transport begins to move the tape forward while the delay counter counts off
the delay period. The transport actually moves the tape forward 6.85 in. before the delay period expires. This
distance ensures that the tape has reached operating speed and is well past the BOT marker and that start-up
transients and noise have subsided. When the delay period expires (counter equals 40000), the READING line

asserts, enabling the read and write logic. When the controller raises the C WDR (write data ready) line a write strobe
(REC) is generated and the data is actually written on the tape. A write strobe (C WRS) is sent to the controller

2-7

Part 111

START )
l,

ASSERT
1

commano

WRITE, WRITE FMK, READ

SPACE FWD, SPACE REV,

LoaDDELAY

INTO

DELAY

COUNTER
|

\SSUE

WRITE XIRG

Anoser

(SEE

NOTE)

SET
MOTION

PULSE

EN-

|
-

ABLE

FLIP-FLOP

SET MOTION

FLIP-FLOP

CLOCK

’
TRIGGER

REWIND

OPERATION
e

]

DELAY

COUNTER
_

OFF LINE

ONE SHOT

YES

DELAY

COUNTER
=
40000

TRIGGER

REWIND

ASSERT

ONE-SHOT

READING

NOTE:

NOTE 1: SEE TABLE 3-2 FOR ROM OUTPUT AND
DELAYS ASSOCIATED WITH EACH

PERFORM

OPERATION

COMMAND.

11-3040

Figure 2-4

Commands Processing Sequence Flow Diagram

50 us later, requesting the next character. While the write head records the data, the read head reads the data back.

Each time the read head detects a character, a RD STRB (read strobe) is sent back to the read logic. Upon receiving
three read strobes (minimum record length), the read logic asserts RECORD ACT to the shutdown logic. The
recording operation then continues until all the data is recorded and the controller clears the C WDR line. When C

WDR is cleared, WRITING (which is controlled by the write logic, Figure 2-6) clears and the shutdown logic is
enabled.

When the shutdown logic detects a gap three character times long between successive read strobes, CRC RD TIME is
asserted to the read logic and the controller drivers. If the record was recorded correctly, the next two characters

detected by the read head should be the CRC character and the LRC character in that order. The read strobe

resulting from the CRC character clears CRC RD TIME and asserts LRC RD TIME to the controller drivers. The read
strobe resulting from the LRC character clears LRC RD TIME and eight character times later the shutdown logic
asserts RD CLR. If the CRC and LRC characters are not detected by the read head, the RD STRB will be generated

internally by the shutdown logic; however, the shutdown will wait 56 character times instead of the normal 8 before
asserting RD CLR. The extra delay is provided to ensure that the read head has passed the end of the record before
the tape stops in the event of a bad tape spot or a write circuitry malfunction.

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2-9

Part IIT

The assertion of RD CLR loads the delay counter for a delay and clears READING. In this case, because it was a
write operation, the counter is set for a delay of 2 ms. In the case of read operations, the counter is set for a 0.1 ms
delay. A smaller delay is used during a read operation to ensure that any unwanted data that may be written on the

tape by the write heads while turning off is erased. When the delay expires, the read/write control logic clears MOT,

WRE LTCH, and FWD-MOT. When MOT is cleared, the tape motion status logic asserts SDWN (settle down) to the
controller drivers to indicate that the transport is in the process of stopping. Clearing WRE LTCH and FWD-MOT

actually causes the transport to stop the tape. The read/write control logic delay counter then counts off a 32 ms

deceleration delay (which allows time for the tape to stop) and asserts DRIVE STOPPED to the tape motion status

logic. The tape motion status logic then clears SDWN and asserts TUR (tape unit ready) to the controller drivers,
indicating that another operation may be performed.

Read and Space Forward Operations — The differences between a BOT write operation and a BOT read operation or
BOT space forward are as follows:

1.
2.

The controller asserts C FWD but does not assert C WRE and C WDR.
The read/write control logic delay counter is preset to 33400 and the tape is only advanced 3.01 in.

instead of 6.85 in. before the delay expires and READING is asserted.

CWRE s not asserted so the transport write logic is disabled.

CWDRis not asserted so the adapter write logic is disabled.

The delay counter counts off a 0.1 ms delay before clearing MOT and FWD-MOT.

Write File Mark Opération — The differences between a BOT write operation and BOT write file mark operation are
as follows:

In addition to CFWD and C WRE, the controller asserts C WFMK but does not assert C WDR.

The read/write control logic delay counter is preset to 20000 and the tape is advanced 10.05 in. before
the delay expires and READING is asserted.

C WFMK enables the adapter write logic to write the file mark character and to generate the LRC PLS
which causes the transport data section to write the LRC character.

Write Extended Interrecord Gap Operation — The only difference between a BOT write operation and a BOT

write-with-extended-interrecord-gap is that the tape is advanced 10.05 in. instead of 6.85 in. before the delay expires

and READING is asserted.

Space Reverse Operation — The differences between a BOT write operation and a space reverse operation are as
follows:
1.

The controller asserts the C REV line only.

The read/write control logic delay counter is preset to 37423 and the tape is moved backward only
0.117 in. before the delay expires and reading is asserted.

CWDRis not asserted so the adapter write logic is disabled.

Because there are no CRC and LRC characters at the beginning of a record, two COMP RD STRB pulses
must be generated internally by the shutdown logic and the shutdown counter counts off 5.6 ms before
asserting RD CLR.

The read/write control logic deceleration delay is 0.1 ms.

2-10

Part I11

Rewind Operations — The differences between a BOT write operation and a rewind off-line operation are as follows:
1.

The controller asserts

C WRE and C RWND but does not assert C FWD and C WDR; thus OFF-LINE

PLS and RWND PLS are generated and sent to the tape transport, initiating a high-speed rewind

operation and extinguishing the transport ON LINE indicator.

The read/write control logic delay counter is preset for no delay and the motion flip-flop is held in a
reset condition; therefore, DRIVE STOPPED is asserted immediately to the tape motion status logic.

At the tape motion status logic, RWS (rewind status) asserts and RDY clears, causing TUR to clear and
RWS to assert to the controller. If the transport is still selected when the rewind is completed, RWS

clears and RDY asserts, causing RWS to clear and TUR to assert.
The rewind operation differs from the rewind off-line operation in that C WRE is not asserted by the controller;

therefore, RWND OFF-LINE PLS is not generated and the transport ON LINE indicator remains illuminated.

The only control logic functional blocks not fully discussed in the preceding paragraphs are listed below and
discussed in the following paragraphs.

Tape Motion Status Logic

Tape Drive On-Line Detect Logic
EOT Status Register Logic
Status Inhibit Logic

Tape Motion Status Logic — This logic determines the tape motion status and generates outputs to the controller
drivers to notify the controller. The logic monitors MOT and DRIVE STOPPED from the read/write control logic
and the RWS and RDY inputs from the tape transport. If the transport is on-line with tape loaded and is not

rewinding or advancing to the load point, the transport asserts RDY as soon as it is selected by the adapter (BSEL
DRIVE asserted). When RDY is asserted by the transport, the tape motion status logic asserts TUR to the controller
drivers.
The tape motion logic essentially operates in two modes: the rewind mode and the nonrewind mode. If the

controller issues a nonrewind command (for example, a write command), the MOT input is asserted and DRIVE
STOPPED is cleared, causing the TUR output to clear. When the operation is completed, the MOT input clears and

SDWN asserts. DRIVE STOPPED asserts 32 ms later, SDWN clears, and TUR asserts. If the controller issues a rewind
command, the transport clears RDY and asserts RWS; MOT and DRIVE STOPPED remain unchanged, i.e., cleared

and asserted, respectively. In response, the tape motion status logic clears TUR and asserts RWS. The transport then
rewinds the tape past the BOT marker, clears RWS, advances the tape forward to the BOT marker, and asserts RDY
and BOT. The tape motion status then clears RWS and asserts TUR.
The CHANGE UNIT input to the tape motion status logic merely serves to reset the logic each time a new drive is

selected by the controller.

Tape Drive On-Line Detect Logic — This logic monitors C SEL 2 from the controller,
MOT from the read/write
control logic, and DRIVE (1:0) ON-LINE and MASTER SEL SW O from the master and slave tape transports.
The MASTER SEL SW 0 input determines which transport is drive 0 and which transport is drive 1 as addressed by

the controller. The unit select switches located on the master and slave transport front panels control this input. If
an even number switch is installed in the master tape transport, it is addressed as drive 0. If an odd switch is installed

in the master transport and an even switch in the slave, the master is addressed as drive 1. If no switch is installed in

the slave transport, the master is addressed as drive 0. If the master is the only transport in the system, it is addressed

as drive 0.

2-11

Part II1
In accordance with the controller input, the tape drive on-line detect logic selects either the master or slave tape
transports by asserting SEL 1 or SEL 0 provided the motion flip-flop is reset. If the transport selected is on-line (ON

LINE indicator illuminated) the ON-LINE output is asserted to the controller drivers and C SEL R is asserted,
notifying the controller that the designated transport is on-line and has been selected. If, for example, the master

transport is drive 0, the controller must clear C SEL 2 to select the master transport. Note that the tape drive on-line
logic will not select a new transport while the motion flip-flop is set.

EOT Status Register Logic — The EOT status register logic monitors the EOT input from the tape transport and the

SEL 0 line from the tape drive on-line detect logic and stores the EOT status of each transport in a register. If drive O

is selected and EOT asserts while FWD LTCH is asserted, EOT is asserted to the controller drivers. If drive 1 is then
selected, the EOT status of drive O is stored and EOT is cleared. The REV*MOT and RWND PLS inputs serve to
reset the portion of the EOT status register relating to the drive currently in use. The PWR OK input clears the entire
register.

Status Inhibit Logic — This logic inhibits status outputs to the controller when the controller selects a drive other
than O or 1 and whenever a new drive is selected. If the controller asserts

C SEL 0 or C SEL 1, INHIBIT STATUS

asserts to the controller drivers and inhibits all status outputs until both inputs are cleared. Whenever the controller

clears or asserts C SEL 2, the EOT status register asserts CHANGE UNIT (250 ns pulse), which also causes the status
inhibit logic to assert INHIBIT STATUS but for only 250 ns. This prevents the transfer of erroneous status during

the drive select operation. Thus, status outputs to the controller are inhibited as long as an illegal drive unit is
selected and each time the controller selects drive O or drive 1.

2.3.1.2 Write Logic — The write logic generates the strobes necessary to write data, the CRC character, and the file
mark character (Figure 2-6). In addition, the write logic generates parity and the CRC and file mark characters and
converts all zero characters to 203 when even parity (PEVN LTCH asserted) is selected.

SET

C WD (7.0)

CONTROFLT.%:}
FROM

F.GU%E
2-3

PARITY

GENERATION
AND ZERO

wD(@:7,P)

L ___..:>
[

COMPILER
IMPIL

CHARACTER

PEVN LTCH

CONVERSION

(D9)

LOGIC

CRC(GZ?,P):

WD(7:0,P),

C WDR

CRC WR TIME

CONTROLLER} C WFMK
|

TIME PLS

FROM | " READING

FIGURE
2-3

SET
MOT

WRITE

muLT-

WFMK LTCH

PLEXER
(D9)

STROBE
GENERATION

LOGIC
(D8)

LRC PLS L\

REC

WRITING

DRIVERS

WRITE
DATA

WR PLS

FROM

D>TRANSPORT

710

)TRANSPORT

TO
FIGURE
2-3
TO
FISUF

—* | DRIVERS

CONTROLLER
DRIVER

11-3042

Figure 2-6

Write Logic Functional Block Diagram

2-12

Part IIT

The write strobe generation logic is enabled by READING and either C WDR or C WFMK. If READING and C WDR
assert, a normal write operation is performed. If READING and C WFMK assert, a write file mark operation is
performed. See Figures 2-7 and 2-8 for write operation and write file mark operation flow and timing diagrams.

2.3.1.3

Read Logic — The read logic (Figure 2-9) monitors the read data and RD STRB inputs to determine

whether a data record or a file mark record is being read and also checks for parity, CRC, or LRC errors.

The record and file mark detection logic decodes the characters read and generates outputs accordingly. The clearing
of MOT at the end of the previous operation and the assertion of SET at the begmmng of the current operation serve
to initialize the logic and assert FMK.

The logic decodes characters read as well as the format in which they are recorded. If a file mark record is detected

(a file mark character followed by eight blank character frames and an LRC character), all four outputs are asserted,
indicating that a record has been detected and that record was a file mark. The three outputs to the controller
drivers serve to notify the controller that a file mark record has been detected.
The RECORD ACT output enables
the shutdown counter in the control logic. If a data recordis detected (three or more data characters followed by a

CRC and an LRC), FMK is cleared, RECORD ACTis asserted, and FILE MARK DETECTED and EIGHT SPACES
remain cleared.

The parity error detection logic uses the simple generate-and-compare technique to chec_-k for parity errors. The logic
uses the character read to generate the parity bit as selected by the PEVN LTCH input, then compares the parity bit

generated to the parity bit read. If they do not match, BAD PARITY

is asserted to the controller drivers.

The LRC error detection logic uses a flip-flop register and a compare network to check the number of 1 bits
recorded on each channel of a record, including the CRC and LRC characters. If the number of ones recorded is odd,

LRC REG NOT ZERO asserts to the controller drivers, causing LRCE to be asserted to the controller. Note that
LRC REG NOT ZERO may assert several times during a particular record; however, the controller driver is only
enabled during LRC read time while the tape is moving forward. The CRC error detection logic uses the data
characters in each record to compile the CRC character; it then compares the character compiled to the CRC

character recorded. If they do not compare, CRCE is asserted to the controller drivers. Note that the CRCE output
from the CRC error detection logic is only enabled when CRC RD TIME and FWD LTCH are asserted. At the

controller drivers, the C CRCE output is disabled whenever a file mark record is detected.
2.3.2

Transport Control Logic

The control logic section of the tape transport generates the appropriate internal tape motion commands in response

to input commands from the adapter, the front panel and the test panel. The control logic receives these commands

and generates transport motion if all internal interlocks are satisfied. In addition, the control logic returns the
transport status outputs to the adapter and illuminates the respective indicators. on the front panel and the test

panel. Because the transport uses different signal names than the adapter, a signal name cross-reference is provided in
Table 2-3.

2.3.2.1

Functional

Operation — Five

plug-in

circuit

cards

constitute

the

control

section

logic

(Figure

2-10): Control Terminator Type 3841 (not shown), Interface Control Type 3842, Pushbutton Control Type 3843,

Ramp Generator Type 3645, and Sensor Amplifier/Driver Type 3844. The modules are housed in the card cage

assembly and plug into the master board. Figure 2-10 is a simplified block diagram of the control logic, showing the
signal flow between the control modules. The input signals from the adapter are supplied, after being terminated on
the control terminator module, to the control interface module, where these signals are acknowledged if certain

interlocks are satisfied. The motion commands are then supplied to the pushbutton control module. This card also
includes the interlocks for the front panel pushbuttons and for the test panel pushbuttons. If the interlocks are

satisfied, the pushbutton control module encodes all tape motion commands onto three command lines: RNN1 (run

normal), RNF1 (run fast), and RVS1 (reverse select). The three command lines are then supplied to the ramp
generator module, which produces accurate analog voltage output. The voltage output of the ramp generator is then
supplied to the capstan servo amplifier module in the servo system. The voltage output of the ramp generator in

2-13

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19HI4SDY

Part I

( ST,;T )

C WEMK

1-C WFMK

1->WFMK LTCH

SET FMK F/F

NOTE 1

W FMK F/F

(

" W FMK LTCH

READING
=1

ISSUE REC PULSE

800 us

TO SELECTED
TRANSPORT AND

REC

RESET FMK F/F

0— WRITING

1— SHIFT

LRC PLS

F, -4 - ._4_. i

READING

WAIT 8

CHARACTER

WRITING

TIMES AND
ISSUE LRC PLS

NOTE:

WFMK LTCH FORCES

WRITE MULTIPLEXER
END

OUTPUT TO 23, (FILE
MARK CHARACTER).
11-3039

Figure 2-8

Write File Mark Operation Flow and Timing Diagram

conjunction with the feedback from the capstan tachometer
is used to energize the capstan motor and to advance
the tape in the desired direction at the proper speed.

The ramp generator provides linear ramp-ups to speed and

linear ramp-downs to standstill in order
to minimize the stress on the tape and maintain accurate speeds.
The sensor amplifier driver module receives the inputs from the file protect switch, the load point sensor,
end-of-tape sensor, and broken tape sensor. These signals are amplified and supplied to the other modules in the
control section where they provide the inputs to the interlocks. The sensor amplifier driver module also contains the

drivers for the front panel indicators, the driver for the file protect solenoid, and the write and erase head drivers.
2.3.2.2

Transport Control Logic Operation During a Write Sequence — A write operation will be used as an

example to demonstrate the interaction of the different components of the control logic. The whole operation is
described, showing the flow of commands and the required control interlocks.
The front panel is used to prepare the transport for operation. After the power is turned on and the tape is properly
threaded, the front panel LOAD pushbutton is pressed. This sets the load flip-flop on the pushbutton control

modules, generating RNNI1 true to the ramp generator card. The ramp generator outputs a linear ramp voltage to the

capstan servo amplifier card, initiating forward tape motion at normal running speed. The ramp generator also
supplies TRNG (tape running) status true through the interface control card to the adapter logic. When the load

point reflector marker is detected by the respective photocell, the signal is amplified by the sensor amplifier/driver

card and is supplied as LP (load point detect) true to the pushbutton control module. LP true sets the ON TAPE
Alip-flop to the true condition, terminating the synchronous forward motion by setting RNN1 false. The tape is

2-15

Part LT

RECORD ACT

RD (7:0)

FROM

TRANSPORT

D STRE

RECEIVERS

RECORD AND

FROM
-

PLS

DETECTION LOGIC

F MK
|

MOT

.FIGURE

SET

2-3

RD(7.0,P)

|
—

(FROM FIGURE

2-3)

DETECTION

PARITY ERROR
JecTior

BAD PARITY

.
(FROM FIGURE
2-3)

— TO FIGURE 2-3

EIGHT SPACES

FILE MARK
TIME

—

FILE MARK DETECTED

CONTROLLER

—

RD (7:0,P)

SET

LRC ERROR

DETECTION

LOGIC

LRC

REG

NOT ZERO

(D12)

—p

COMP RD STRB
FROM
FIGURE

2-3

CRC RD TIME

FWD LTCH

‘
SET =

CRC ERROR

RD (7.0,P)

DETECTION
LOGIC

CRCE

(D11)

11-3043

Figure 2-9

Read Logic Functional Block Diagram

Table 2-3
Adapter To Transport Signal Name Cross Reference

Signal Name
At Adapter

At Tape Transport

B FWD-MOT

SFC

B REV-MOT

SRC

B OFF-LINE PLS

OFF C

B RWND PLS

RWC

B WRE LTCH

SWS

B SEL DRIVE (1:0)

SLT

B DRIVE ONLINE

ONL

B WD (0:7, P)

WD (0:7, P)

B XPRT RDY

RDY

B RD (0:7, P)

READ CHAN (0:7, P)

BWRLCK

FPT

- B RWNDG

RWD

B LOAD POINT

LDP

- B END OF TAPE

EOT

REC

LRC PLS

"B DRIVE (1:0) RD STRB

WDS
WARS

RDS

Part 111
FRONT

PANEL

PUSHBUTTONS

[ REWIND]

fon LINE]fLOAD]
]

CONTROL

beeq

CAL

—

[

RVS

MOT
ION I
conTRot

RNN

PLUG-IN MODULE

RUN

NORMAL

o
»
S

REVERSE

L_q.-RNN

(TO DATA

SECTION)

OFFC

RWC

CONTROL
LOGIC

ADAPTER
—

LOGIC

_
SWS

LOGIC

[

SELECT

WRITE

Lopyge

<1—

AMPLIFIERS

;

LINE

— (10 CAPSTAN
]

SERVO)

]

TAPE

TEST MODE |

WRITE TEST

-%
-

FWD
REV

FAST

RUN
RUN

FAST FWD

PANEL
PUSHBUTTONS (OPTIONAL

9900)

REV

WRITE

]

CONTROL

OUThUT

TOR

READY

#(T0 DATA

l LOGIC

SECTION)

BOARD

LINE

BUSY

—_WRITE AMP OUTPUTS

FILE PROTECT

FROM

[DATA SECTION

TAPE RUNNING (TNG)

WEN =
-

TNG =
RWDG

wRITE

‘

| pUSHBUTTTON

20y

FPT

ON_g | CONTROL|

* ]
ONL =

-VI
GENERATOR
> LoGIC &

sREWINDING ~ RUNNING

TO/FROM

L__

#BUSY

DRIVE

m———

RAMP GENERATOR|

— -

FWD

SLT

pem—

r"-l

INTERFACE

<—— REWINDING (RWDG1)
'
-

WRITE HEAD
DRIVER

‘

.4 WRDY | | SENSOR AMPL/DRIVER
STATUS
LOGIC &
[
-

ouTeur
DRIVERS

—

FILE
‘ PROTECT
FILE
PROTECT
SWITCH

LP -_

‘%Lpo1

| 0T -

BKN

CIRCUIT

FpT '

WRITE

HEAD C.T.

[

ERASE

—{>

DRIVER

L‘|

| PHoTO

SENSOR

INDICATOR

| AMPLIFIERS
1

| |op |EoT [BKa

DRIVER

WRITE

ENABLE

L___...._.f

PHOTOSENSORS

Figure 2-10 Control Logic Block Diagram
2-17

—_

11-3047

Part 111

stopped at the load point and is properly loaded. Pressing the front panel ON LINE pushbutton now places the
transport on-line, preparing the transport to respond to adapter commands once it is selected by the adapter. When

the transport is selected (input line select going true), the transport can accept commands from the adapter and
return the transport status outputs back to the adapter. At this time, the transport status lines would be in the states

shown in Table 2-4. In addition to the status lines, the front panel ON LINE and SELECT indicators are illuminated,
as is the WRITE ENABLE indicator if the supply reel contains a write enable ring.
Table 2-4
Transport Status

Status Line

~ State

ON-LINE (ONL)

True

Point of Origin
Supplied from the load point flip-flop on the pushbutton

control

module,

routed

through

the

interface

control

module.

TRANSPORT READY

True

This signal, generated on the interface control module,

combines BUSY false (meaning the transport is loaded and
~ not rewinding or searching for load point) and SLT1 true

(meaning the transport is on-line and SLT is true).

TAPE RUNNING (TNG)

False

" This signal goes true on the ramp generator when tape
motion is initiated.

REWINDING (RWDG)

False

At this time, the rewind flip-flop on the pushbutton control
module is in the cleared state.

FILE PROTECT (FPT)

This signal is true if the reel of tape mounted on the supply
hub does not contain a write enable ring. It is false if the
reel does contain the ring and is available for writing. The

signal originates on the sensor amplifier/driver module.
LOAD POINT (LP)

True

Since the tape is at load point, the sensor amplifier/driver

supplies this signal true. When LDP is true, the transport

does not acknowledge a REWIND command or an SRC

from the interface, but must be taken off-line and rewound

off tape by using the front panel pushbutton.

WRITE ENABLE (WEN)
o

|
-

This signal is equivalent to the inverse of the FPT signal and
is true whenever the other is false, e.g., whenever the supply
reel contains a write enable ring. The signal originates on

the interface control module.

END OF TAPE (EOT)

|
|

False

This sigfial goes true only when the end-of-tape reflective
marker is detected by the respective photosensor. The

signal is supplied to the sensor amplifier/driver module.

If the write operation is to be initiated, the adapter logic now supplies SWS (set write status) level true and then an

SFC (synchronous forward command). The SWS level is sampled on the leading edge of SFC. If the level is true, a
flip-flop on the interface control module is set, which generates WSEL (write select) true. WSEL is supplied to the

pushbutton control module where it generates WRDY (write ready) true provided FPT (file protect) is false
(supplied from the sensor amplifier/driver module), BUSY is false (this signal is generated on the pushbutton control

2-18

Part 111
and is true whenever the transport is searching for load point and is rewinding), and a forward motion command is

given. These interlocks ensure that the transport writes data on tape only when the tape is properly loaded, the reel

has a write enable ring, and the tape is moving forward at normal running speed. WRDY true is supplied to the

sensor amplifier/driver module where it turns on write and erase head current drivers. WRDY and SLT1 (select 1)

(combining ON-LINE true and SLT true) are also supplied to the data electronics card cage where they enable the
write and read amplifier stages.

If WRDY does go true, the adapter logic supplies the properly formatted data to be written on tape. The write
operation can be interrupted in case of broken tape; when the BKN (broken tape) signal is supplied from the sensor

amplifier/driver module, all servos are disabled immediately. Note that an EOT indication does not terminate a write

operation, but leaves it up to the adapter to do so. When the write operation is terminated by the adapter, the tape is
rewound to the load point when the adapter issues

a REWIND command. Note that the tape cannot be rewound

past the load point by a command from the adapter In order to rewind the tape off the takeup reel, the transport

must be taken off-line, either through an adapter command or by pressing the front panel ON LINE pushbutton
again. Once the transport is off-line, the front panel REWIND pushbutton can be activated to rewind the tape

completely off the takeup reel.
2.3.2.3

Test Panel — The test panel provides a means of exercising, testing, and adjusting the tape transport while it

is off-line, eliminating the need for a separate test fixture or for the use of valuable computer time. The test panel
can initiate forward and reverse tape motions at either normal or high tape speeds. It can also initiate a write test,
generating a crystal-controlled all-1s test pattern on tape. The test panel also provides indicators for load point,

end-of-tape, and data.

An additional indicator monitors excessive skew, and is used in the aligning of the read/write head when using an
800 character/in. skew master tape. When the head is properly aligned and the data is written on tape properly, the
SKEW indicator is extinguished.
The controls and interlocks for the test panel are located on the pushbutton control card. The skew detect network
is located on the delay timing module in the read logic section of the transport. The test panel becomes operational

only when the transport is off-line, with the test panel STOP pushbutton depressed. If these conditions are satisfied,
the test panel pushbuttons are enabled when the TEST MODE pushbutton is pressed
2.3.3

Servo System

The servo system includes two subsystems: the capstan SEIVO subsystem, which drives the tape at accurately
controlled speed, and the reel servo system, Wthh maintains constant tape tension.

2.3.3.1

Reel Servos — Two identical reel servos are employed for the supply and the takeup reels. A Simplified

block diagram is shown in Figure 2-11. Each reel servo includes a spring-loaded buffer arm, a magnetic position
sensor coupled to the buffer arm shaft, a servo amplifier (located on the Servo Preamphfier Type 4306 module),

power transistors (located on the chassis heat sink), and a high power dc motor.

The tape tension is maintained by the interaction of the spring-loaded buffer arms, the capstan, and the respective
reel motors. The magnetic position sensors, called magpots, produce a corrective voltage whenever the buffer arms

swing away from the center of their arcs. The magpots are rotary differential transformers with oscillator and phase
detector circuitry. The output of the magpot circuitry provides a bipolar dc voltage which has a linear relationship to
the tension arm position and a null at the center position. The magpot output is summed with a signal from the
capstan tachometer in the higher speed versions of the machine. The effect of the tachometer component is to speed

up the response of the reel servos.

As shown in Figure 2-11, the corrective voltage approaches 0 V in the rest position where the torque of the motor is

balanced against the buffer arm spring tension near the center of the tension arm swing. When capstan motion pulls
the tape, the buffer arm moves, causing a change in the magpot output. This is amplified in the servo preamplifier
whose signal drives power transistors that control the dc motor current to provide a change in torque until the

2-19

Part T

torque matches the buffer arm spring tension at the null position again. Since the system is bipolar, seeking a null
which is controlled by a magnetic core position, the adjustments are mechanical and will not drift with temperature

or component degradation.

BUFFER

ARM

SPRING

HAGPOT

POSITION

REEL
MOTOR

POSITION
OFFSET

——
PREAMPL

POWER
bt

11-3058

Figure 2-11

2.3.3.2

Reel Servo System

Capstan Servo — The single capstan drive motor is part of a high performance velocity servo system. In

addition to the motor, the capstan servo system includes a dc tachometer, coupled to the capstan motor shaft, and
the capstan amplifier, located on the servo preamplifier module. The linear analog ramp voltage produced by the

ramp generator card (in the control logic section) is supplied to the servo preamplifier module where it is compared
with the feedback supplied from the capstan tachometer. Any resulting difference is amplified and is supplied to the
capstan power transistors, located on the chassis heat sink. The output of the power transistors energizes the capstan
motor, advancing tape at accurately controlled speeds.
2.3.4

Data Section

The data section includes read and write amplifiers and interface cards providing output drivers and timing controls.
Block diagrams are shown in Figures 2-12 and 2-13.

The data section consists of eight circuit cards that plug into the master board. These include a timing delay module,
a read amplifier/clipping control card, a pair of quad read amplifier modules, a four-channel write amplifier card, a
five-channel write amplifier card, and a data terminator card.
2.3.4.1

Write Electronics — A write amplifier channel is provided for each tape channel. Four such channels and the

circuitry common to all write amplifiers are contained on Write Amplifier Type 3848, and the five remaining write
amplifier stages are located on Write Amplifier Type 3849. These cards plug into the master board, from which the
necessary head connections are made.

2-20

Part I

WRITE

CONTROL

(FROM READBUFFER)

CTM WRITE AMPLIFIER/CONTROL
|
PLUG-IN MODULE
A
|

|
|

Wps —

LOGIC

L——v T
[

WDP

WRITE

FROM

}——]

WD?2

APARIER —

GATING

—j

— GATING

__ WRITE LRCC

(ALL CHANNELS)

(PARITY

WRITE

}

(PARITY, 0, 1, 2)

o CHANNEL) |

WDO ——————| WRITE AMPLIFIERS
WD1

URITE

{

{=>

WRITE LRCCl

L o e o e —

[ "5 CHANNEL WRITE AMPLIFIER

—{=

;
f

—{=>
—{=>

WD3

PLUG-IN MODULE

L
—+—|
o

WD4
WD5

]

WRITE
AMPLIFIERS

07—t —e

e o

GATING—}

LNRITE LRCC‘

e —— — —

11-3053

Figure 2-12

SKEW

Write Data Section

ADJUSTMENT

SWITCHES

EAD
DRIVER

W0S1

INPUT |
DATA

‘
ICOUNT/LOAD

CLEAR

F1-CRYSTAL CONTROLLED

—J

Cpp———CCcCK

CLOCK

KCLRG

FREQUENCY @ 32XDATA

CK
-

KCLRG
fi)

WRITE AMPLIFIER RESET WARSI
11-3062

Figure 2-13

Typical Write Amplifier Channel (0—7), Fixed Channel P Delay

2-21

Part 11T
Each write amplifier channel consists of an input buffer, a digitally adjustable deskewing circuit, a clocked flip-flop,
and a pair of head drivers, as shown in Figure 2-13. Digital write deskewing and its advantages are explamedin the

following paragraphs.

Manufacturing tolerances in the production of magnetic heads cause deviations in the parallelism between the write
gap and the read gap of the magnetic heads, as shown in Figure 2-14. While the magnetic heads are manufactured so
that this deviation does not exceed 250 microinches, it is important to correct for it; otherwise the skew across the
bits of a character may cause errors durmg the reading of the data on compatible systems.

READ/WRITE
MAGNETIC
HEAD

—

HEAD MOUNTING PLATE

TAPE MOTION ——

GAP

WRITE J|

o x r
> m
o >

guuudd

aaaaannn

ALL-1 PATTERN
WITHOUT WRITE

ON TAPE
DESKEWING

ALL-1 PATTERN WITH
WRITE

DESKEWING

DEVIATION FROM PARALLELISM
INHERENT IN HEAD

(PARALLEL WITHIN 250 UIN,)
a. Skew Caused by Physical Characteristics of Head

REFERENCE

HEAD

TAPE MOTION —B>
l

‘.

PATTERN RESULTING FROM

MISALIGNMENT OF HEAD

,
|

DEVIATION
CAUSED BY

PATTERN RESULTING AFTER HEAD

IS ALIGNED USING SKEWMASTER

FROM PERPENDICULARITY
MISALIGNMENT
11-3063

b. Skew Caused by Misalignment of Head

‘Figure 2-14

Skew Characteristics

2-22

Part 111

The skew caused by the physical characteristics of the head should not be confused with azimuth or with the skew
caused by the misalignment of the whole magnetic head with respect to the tape path, shown in Figure 2-14.
Azimuth can be corrected by aligning the read head to be perpendicular to the tape path using a skew master
tape — a tape written by a special machine equipped with a full-width write head set perfectly perpendicular to the
tape. The head aligning procedure is made particularly simple by the use of the optional test panel, as described in
Part I, Chapter 5 of this manual.

While azimuth can be corrected by manually adjusting the position of the read head, the skew caused by the

parallelism tolerance between the write head and read head must be corrected electronically. This is done by
delaying the channels with respect to a fixed reference so that all the bits of the character are read simultaneously.

Conventional skew correction methods employ adjustable delays supplied by analog circuitry in the read circuits.
While these methods compensate for the skew of the character written on tape by the same machine, they do not
correct the character itself as it is written on tape; consequently when the tape is read on a different machine, the
skew is uncorrected. Also the delays generated by analog circuits are subject to drift and may require periodical
readjustment.

In this tape unit, the skew correction problems are overcome by write deskewing circuits, shown in Figure 2-13. The
main component of the deskewing circuit is a divide-by-16 counter clocked by a crystal-derived frequency F; at 32

times the data rate (generated on the delay timing module). The counter of channel P is preset to the count of eight,
supplying a fixed 1/4 character delay. The parallel inputs of the counters of the other eight channels are adjustable
using a set of four switches for each counter, varying the skew delay of each channel in 1/32 character increments.
Each head is pretested and the switch positions are determined to compensate for any deviation from parallelism
between the write and the read gaps, using channel P as a reference. Once the head is installed on a machine and the
write amplifier switches are set, the switch positions should not be changed for the life of the magnetic head. These
switch positions are displayed on a tape inside the machine. If the magnetic head is replaced, the replacement head is

pretested in the factory and is supplied with a new tag showing the switch positions required to compensate for the
characteristics of the new head.

The digital write deskewing method ensures that the character written on tape has minimum skew, increasing the
compatibility of tapes between different tape transports. Using digital circuitry with a crystal-controlled reference
frequency provides for a high degree of precision and stability for all skew adjustments.

The write electronics section also includes the write data strobe buffer which clocks the write amplifier flip-flops,
and a write amplifier reset circuit to clear all write amplifier flip-flops. The write amplifier reset is used to write the
LRC character. During a write test mode, initiated by the test panel with the recorder off-line, the write electronics
generates an all 1s test pattern on tape derived from a crystal-controlled reference frequency (FR), supplied from the
delay timing module in the read electronics. The test pattern can be used to test the write deskewing, as well as the
other functions of the data electronics.

2.3.4.2

Read Electronics — The function of the read electronics is to convert the data recovered from the tape into

digitized waveforms, deskew it, and supply it to the adapter logic with its respective read strobe. The read electronics
also detect the interrecord gap and excessive skew. The components comprising the read section include the
magnetic

read head,

the

Read

Preamplifier Type

3631

module,

Delay Timing Type 3845 module,

Read

Amplifier/Clipping Control Type 4179 module, and a pair of Quad Read Amplifier Type 4178 modules. Figure 2-15
is a functional block diagram of the read section, showing the general signal flow between the cards.
The low level analog signals, on the order of tens of millivolts, are supplied from the read head to the read
preamplifier module where they are linearly amplified to an output voltage (adjusted by a potentiometer for each
read preamplifier stage) of approximately 9 V peak to peak in 800 character/in NRZI read operation. The amplified
analog signals are then supplied to the nine read amplifier stages, eight of which are located on the quad read

amplifier modules while that of channel P is located on the read amplifier/clipping control module. Each read
amplifier stage includes a peak detection circuit, a filtering network, an output data register, and a pulse generator.

2-23

Part 111

The analog signals from the preamplifier are detected only when they exceed the positive or negative clipping levels

provided by the read amplifier/clipping control module. They are then rectified and peak detected, with the
resulting digitized waveforms containing negative-going transitions corresponding to the peaks of the input analog

signals, e.g., 1 bits in the NRZI code. The digitized waveforms are supplied to a filtering network which eliminates
spurious pulses between transitions. The data of each channel is then stored in a register and generates a PULSE
OUT to the delay timing module. Following the skew delay, the delay timing card supplies a DATA TRANSFER
output to clock the data registers of all nine channels simultaneously, supplying the data character and read clock to

the interface.

When an error is detected and the transport is commanded by the adapter logic to reread a block, the read amplifier

clipping levels

are switched automatically

by the read amplifier/clipping control module to maximize the

recoverability of marginally recorded data. The clipping levels are kept normal on the first reread; on the second
reread they are switched to lower levels in order to recover possible partial dropouts. If the block is still in error and
a third reread is commanded, the clipping levels are switched to higher levels to eliminate possible baseline spikes.
During read-after-write operations, higher clipping levels are used.

The delay timing module contains circuitry common to all nine channels. It includes a crystal-controlled oscillator
and divider network which produce the synchronous clocks used in the skew delay network, the data strobe

generation, the gap detect network, and are also supplied to the Write Amplifier Type 3848 module to generate the
write test pattern. The crystal-controlled clocks ensure high precision in the performance of all data synchronized

functions.

2-24

Part 111

TEST

PANEL

o
Ly
I <C

(=g fo
1>
<L <L
jany ]

[

DELAY TIMING

READ GAP l
DETECT

NE TWORK

—BSY

Frop | =L
Lp

CONTRTM

LOGIC | —
RNN

)

DETECT

l SLT?
READ
SELECT

GENERATION

‘

SKEW

NETWORK

pATA |
TRANSFER

DELAY

PULSE

oUT (4-7

PULSE

CHANNEL

CHAN

QUAD
READ

READ CHAN

6
7]

reno

< PRE-

CHAN

< AMPLIFIER
<&)—

READ CHAN 7 _

AMPLIF[ER

PULSE

OUT

=1 N .2

AMPLIFIER |

READ

AMPLIFIER

CLIPPING
CONTROL

|CHAN P _

READ

CHANNEL P {

""'l

—

CLT?

READ CHAN 6 _

READ

[=F-m—

READ CHAN 5
QUAD

a4. CLIP

CHAN 4

THAN 5

"‘T‘//

READ

SLT?2

- CLIP

INTERFACL

PEAD CHAN 1 _
READ CHAN 2 _

CHAN 3

e3 <F—

READ

AMPLIFIER
i LR

CHAN 1
CHAN 2

¢ <
\ <

ouUT (0-3)

SLT?2

READ

[

;

Logic | Fr

RGAP -

AUTO

CLIPPING

LEVEL

CONTROL

RNN

RVS 1

—1 FROM

'LT%_DT—
AUTO

- CONTROL

SECT1ON
FROM

I:"‘_ DISABLE. INTERFACE
|

11-3048

Figure 2-15

Read Data Section

2-25

Part 111

CHAPTER
3

DETAILED LOGIC DESCRIPTIONS

3.1

INTRODUCTION

This chapter contains circuit descriptions of the individual circuit cards comprising the TS03 DECmagtape

Transport. Module layout drawings are provided with each description. (See engineering drawing for module
schematics.) The descriptions are arranged by functional group as listed below.
Module Name and Type

Functional Group

Adapter Logic

M8920 Adapter

Overall

Model 9700 Power Supply

Control Electronics

Type 3842 Interface Control
Type 3843 Tape Motion Controls including Pushbutton Control, Main

Control Panel, and Test Panel

Type 3645 Ramp Generator

Type 3844 Sensor Amplifier/Driver
Type 4013 Connector Board
Servo System

Type 4306 Servo Preamplifier
Type 4218 Magpot

Read Electronics

Type 3860 Data Terminator
Type 3631 Read Preamplifier
Type 3845 Read Control Logic including Delay Timing

Type 4178 Quad Read Amplifier
Type 4179 Read Amplifier/Clipping Control
Write Electronics

Type 3848 Write Amplifier

3-1

Part 1T

NOTES TO TRANSPORT SCHEMATIC DIAGRAMS

ain conventions have been observed in preparing schematics for this manual:
1.

Resistor values are given in ohms. If wattage is unspecified, the resistor may be either 1/4 or 1/2 W.
Capacitor values may be given in picofarads or microfarads. Those values for which neither designation is
provided are assumed to be obvious from circuit function. Filter capacitors on certain supply lines do

not have logic significance. In general, they are not shown on schematics. On PC board silkscreens, they
are designated as CF.

Normally, IC power connections are on pins 14 (+5 V) and 7 (ground) for 14-pin packages, and 16
(+5V) and 8 (ground) for 16-pin packages. Some ICs (7476, 7492, 7493, for example) have power

connections on pin 5 (+5V) and pin 10 (ground). Operational amplifiers in the 8-pin package have

power connections on pin 4 (-Vcc) and pin 7 (+Vcc). Power connections are not shown unless they are
nonstandard.

Where multiple inputs are tied together only one pin may be designated on the schematic.
Unused inputs that are tied high are not normally indicated unless the connection has logic significance.
From and to designations are intended to describe inputs and outputs only. The same signal may be

connected to several other points not shown on a particular drawing.

Abbreviations used in from and to designatiohs are as follows:
CI

Control Interface

PBC

Pushbutton Control

Ramp Generator

Sensor Amplifier/Driver

Delay Timing

RA/CL

Read Amplifier/Clipping Level

Quad Read Amplifier

WAl

Four-Channel Write Amplifier

WA2

Five-Channel Write Amplifier

Positive logic is shown for all internal connections. Interface connections are zero true but the bar is
omitted.

Integrated circuit symbols contain a circuit designator that corresponds to the number silkscreened onto

the circuit module above an underlined number representing the IC type.
The IC type number is abbreviated and omits the portions of the manufacturer’s type number pertaining
to case and vendor identification. Further, since the TTL 7400 series makes up most of the circuitry, the
74 is omitted on these. Thus a 00 designation indicates a 7400 quad two-input NAND gate. Texas

Instruments’ complete part number is SN7400N. In multifunctional units in close proximity, the type

designation may be omitted. The type designation may appear outside the symbol if the symbol is too

small.
Military Standard 806C is the base for logic symbols. Additional conventions are shown below.

Part 11T

Line indicates buffer or power driver

Triangle indicates response

to edge (in this
case positive)

10.

Semiconductor types on schematics may be replaced by their functional equivalents. If not indicated,
diodes are 1N914, NPN transistors are 2N2714, and PNP transistors are MPS6517.

11.

Unless otherwise specified, light-emitting diodes are FLV102 or equivalent.

12.

Module connector pins are shown as

where no further connection is shown on the schematic, and as

when there is a connection shown.
13.

Where an input is represented by an arrow instead of a complete line, the input source is designated.
Where outputs are so shown, their destinations may not be shown.

14.

Some schematics of modules include certain external elements which aid in understanding the circuit
function. In this case, all the connections to the element may not be shown in the interest of clarity.

15.

The following symbol designates a test point provided on the module. Letters proceed from the top to
the bottom of the card with the ground test point, if present, as the bottom-most terminal.

3-3

Part 111

16.

Socket terminals are designated with numbers for component side connections and letters for circuit side
connections when a double-sided socket is used. These are the designations on the socket. When a

single-sided socket is provided, all connections are designated by letters regardless of which side of the

board they lie on the etch. Letters follow the 22-pin alphabet ABCDEFHJKLMNPRSTUVWXYZ;
numbers are 1 through 22.

3.3 TYPE M8920 ADAPTER CIRCUIT DESCRIPTION
The following paragraphs provide detailed circuit descriptions on those portions of the adapter logic which perform

unique or complex operation. Each description covers a functional block on the control logic, write logic, and read

logic functional block diagrams and is titled accordingly. The circuits described are listed as follows:

Functional Area

Circuit

Engineering Drawing Reference

Control Logic

Clock Logic

Control Logic

Read/Write Control Logic (ROM/Delay Counter)

Control Logic

Shutdown Logic

Write Logic

Write Strobe Generation

Read Logic

Record and Tape Mark Detection Logic

3.3.1

D8
|

D10

Clock Logic

The clock logic generates two 10 kHz pulse trains which are 180 degrees out of phase. See the timing diagram for
logic operation and timing specifications (Figure 3-1).

KHZ

FEY (1) H

FF1 () H
FF3 (1) H

I\
//

[
<

FF2 (@) H

}
L

]

(

TPO

:rir

FF3(Q) H

<Z(

—

» 5uS
-

100 (25) &S

—

:JL

200

L—————-so(is),us—————4

N
11-3044

Figure 3-1

3.3.2

Clock Logic Timing

Read/Write Control Logic (ROM/Delay Counter)

The following paragraphs describe the read/write control logic relative to two different operations: a write
operation and a rewind off-line operation (engineering drawing D5).

3-4

Part 117

3.3.2.1

Write Operation — To initiate a write operation,

C WRE H and C FWD H must be asserted by the

controller. When SET L asserts, the following operations occur at the read/write control logic:
1.

The ROM is addressed and the proper count is output to the delay counter. The count varies in

accordance with the tape position relative to the BOT. If the tape is positioned at the BOT (BOT H
asserted), the delay counter is set to 250005.
-

The motion enable flip-flop is set.

Theload delay counter one-shot (E27-5) is triggered and LOAD DELAY CTR L asserts.

Assuming the tape is positioned at BOT, the assertion of LOAD DELAY CTR L loads the delay counter to a count

of 250005 using the output from the ROM and RWND L. Note that zeros are loaded into the first and second most
significant bits (R3 and R2) of Part D of the delay counter due to the assertion of SET L. The load delay counter

one-shot then resets and sets the motion flip-flop, asserting MOT H. Thus READING H remains cleared. TIME PLS O

then clocks the delay counter for 563.2 ms, the second most significant bit of Part D of the delay counter sets, and
READING H asserts. The read/write control logic remains in this state until RD CLEAR (1) H is asserted by the
shutdown logic.

The assertion of RD CLR (1) H loads the delay counter with a deceleration delay using the ROM output RWND L.

In this case, because a write operation is being performed, the delay counter is set to 377545. RD CLR (1) H also
sets the two most significant bits (R2 and R3) of Part D of the delay counter because SET L is cleared. TIME PLS O

L then clocks the delay for 2 ms, the most significant bit (R3) is reset, and the motion enable flip-flop (E25-3) is
reset. Resetting the motion enable flip-flop asserts CLEAR MOT L, which resets the motion flip-flop, thereby

clearing MOT H and the FWD-MOT H output to the tape transport. The transport begins to stop the tape. TIME
PLS 0 L then clocks the delay counter for 32 ms (allowing time for the transport to stop the tape), and INHIBIT
DELAY COUNT L asserts, inhibiting the clock input to the delay counter and asserting DRIVE STOPPED L.

Assertion of DRIVE STOPPED L notifies the tape motion status logic that tape deceleration delay has expired.
3.3.2.2

Rewind Off-Line Operation — To initiate a rewind off-line operation,

C RWND H and C WRE H must be

asserted by the controller. When C SET H asserts, the following operations occur:

The ROM is addressed and a stop count is output to the delay counter.

The motion enable flip-flop is set.

The off-line one-shot (E33-13) is triggered, asserting OFF-LINE PLS H to the tape transport.

The rewind pulsé one-shot (E27-13) is triggered, asserting RWND PLS H to the tape transport.

Theload delay counter one-shot (E27-5) is triggered, asserting LOAD DELAY CTR L.

The assertion of LOAD DELAY CTR L loads the delay counter with a stop count, i.e., the counter is set so that

DRIVE STOPPED L asserts. When the load delay counter one-shot resets, the motion flip-flop is held in the reset
state by RWND PLS H. Thus MOTION H remains cleared, DRIVE STOPPED L remains asserted, and the tape is
rewound to the BOT.

3.3.3

Shutdown Logic (Engineering Drawing D6)

The shutdown logic is enabled when RECORD ACTIVE H asserts and WRITING L clears. With those conditions

established, TIME PLS 0 H clocks the shutdown counter. However, the counter is prevented from counting past a
count of 2 initially by COMP RD STRB L (composite read strobe), which is generated each time RD STRB H (read

strobe) is received. After the last data character is read, there is a gap of four character times before the CRC
character is read. During that time, the shutdown counter reaches a count of 3, the CRC flip-flop (E61-5) is set, and

3-5

Part 111

CRC RD TIME (1) H asserts. A read strobe is then received due to the CRC character and COMP RD STRB L asserts
and clears the shutdown counter again. When COMP RD STRB L returns high, the CRC flip-flop is reset and the

LRC flip-flop (E45-5) is set, asserting LRC RD TIME (1) H. The counter then counts to 3 again, but this time LRC
RD TIME (1) H holds the CRC flip-flop in the reset state. Another read strobe is then received due to the LRC
character, and COMP RD STRB L asserts again, clearing the shutdown counter. When COMP RD STRB L clears, the

LRC flip-flop is reset and the EOR flip-flop (E45-9) is set. Note that the read strobe resulting from the LRC
character is also ANDed with LRC RD TIME (1) H to load the shutdown counter with a binary count of 56

(0111000). The shutdown counter is then clocked by TIME PLS O and, at a binary count of 64, the read clear
one-shot is triggered, the counter is disabled, and RD CLEAR (1) H asserts to the read/write control logic.

The EOR one-shot (E28-5) is provided to ensure that the shutdown process is completed when the CRC and LRC
characters are not detected at the end of a record. This is always the case when the tape is moving backward, and
might occur when the tape is moving forward if there is a bad spot in the tape or the write circuitry malfunctions.

Note that when the last data character read strobe is received, the shutdown counter counts to 3 and sets the CRC
flip-flop, thus asserting CHK CHAR RD TIME H. If the CRC read strobe is not received, the shutdown counter
counts to 5, placing a low on the EOR one-shot. At a count of 6, the EOR one-shot is triggered, asserting EOR H
and thereby generating COMP RD STRB H. Thus the counter is cleared, the LCR flip-flop is set, and the CRC

flip-flop is reset. The counter then counts up again and if the LRC read strobe is not received, the same operation is
repeated. The shutdown counter then starts its final count cycle; however, in this case the counter starts from a

count of 8 instead of a binary 56, due to the absence of the LRC read strobe. Therefore the final count cycle is 56
counts long instead of the normal 8. In the event a bad tape spot is encountered or the write circuitry malfunctions,
this extended count cycle ensures that the tape moves past the end of the record before stopping.

3.3.4

Write Strobe Generation Logic

The following circuit description will cover the two modes in which the write logic can operate: write data and
write tape mark (engineering drawing D8).
3.3.4.1

Write Data Circuit — When the

C WDR H and READING H inputs are asserted, the write data mode is

enabled and WRITING L and WRITING H assert. WRITING H enables the clock pulse (TIME PLS 1 H) to generate
write strobes to the transport (REC H) and is also output to the controller driver where it enables the clock pulse

(TIME PLS 0 H) to generate the write strobe (C WRS L), thus notifying the controller that a character has been
recorded and requesting the next character. When the last data character has been strobed to the transport, the
controller ciears the

C WDR H input, causing WRITING L to go high, inhibiting the strobe outputs, and setting the

writing done flip-flop (E47-6). Setting the writing done flip-flop places a high on the input to the shift register and
the next assertion of TIME PLS O loads a 1. The shift register output then resets the writing done flip-flop so that no

more ones will be loaded into the shift register. TIME PLS O then shifts the 1 bit through the shift register and, at bit
position 3, CRC WR TIME H asserts, enabling another write strobe (REC H) to the transport to record the CRC
character. The 1 bit is then shifted to bit position 7 and LRC PLS H is generated and sent to the transport to record

the LRC character. Thus the CRC and LRC characters are recorded at the end of each record.
3.3.4.2

Write File Mark Circuit — To write a file mark, the controller asserts

C WFMK H and C WRE H, places a file

character on the write data lines, and issues a SET H pulse, thereby setting the file mark flip-flop (E44-5) and FM

LTCH flip-flop (E44-9). After the acceleration delay expires, READING H asserts, WRITING L asserts, and the

clock pulse generates REC H. The same clock pulse that generates REC H also generates WR PLS L, which resets the
file mark flip-flop on its trailing edge, thereby clearing WRITING L. Thus only one write strobe is generated to
record the file mark character. Clearing WRITING L sets the writing done flip-flop and the shift register is loaded
and shifted up. However, when CRC WR TIME H asserts, REC H is inhibited by WFMK LTCH (0) H. Therefore, the

CRC character is not written. When the 1 is shifted to bit position 7, LRC PLS H is generated the same as in the
normal write data mode. Thus the file mark record consists of only two characters.

3-6

Part 111
3.3.5

Record and File Mark Detection Logic

This logic detects data records and file marks (engineering drawing D10). File marks are detected by decoding the

characters read; two octal 23 characters at the beginning of a record followed by at least eight blank character
frames constitute a file mark record. Data records are detected by counting read strobes; three read strobes
constitute a data record.

The MOT H and SET L inputs preset the record and file mark detection logic before the first character (of
a current

record) and accompanying read strobe is detected. SET L asserts at the beginning of each operation and sets the file
mark flip-flop (E47-9), thereby asserting FMK (1) H. MOT H is cleared at the end of each operation and serves to
preset the read strobe counter to a count of 1.

3.3.5.1

File Mark Record Detection — When a file mark character (235) is the first character read, FMK CHAR L

asserts. The assertion of FMK CHAR L is ANDed with the set condition of the file mark flip-flop, placing a high on
the D input. Thus the assertion of RD STRB H leaves the flip-flop unchanged and steps the read strobe counter to a

count of 2. Now assuming the octal 23 character detected was in fact the first character of a file mark record, the
next and final character detected will be the LRC character which is also an octal 23. Therefore when the next

character is read, FMK CHAR L remains asserted, the file mark flip-flop remains set, and the read strobe counter is
stepped to a count of 3. At a count of 3, ENB FMK CTR H (enable file mark counter) asserts and enables the file
mark counter. The file mark counter is then clocked to a count of 8 by TIME PLS O L and EIGHT SPACES H

asserts, which inhibits the counter and asserts RECORD ACT H. EIGHT SPACES H is ANDed with FMK (1) H to
assert FILE MARK DETECTED L.

Note that if another read strobe is received before the file mark counter reaches a count of 8, ENB FMK CTR H
clears and RD STRB CTR = 4 (1) H asserts. Thus the file mark counter is cleared and disabled, the read strobe
counter is disabled, and RECORD ACT H is asserted. In this case, the two successive octal 23 characters
do not

constitute a file mark record because data does not follow a file mark record that closely.
3.3.5.2

Data Record Detection — When a character other than an octal 23 is the first character read, FMK CHAR L

remains cleared and a low is applied to the file mark flip-flop. Thus the accompanying read strobe resets the file
mark flip-flop and steps the read strobe counter to 2. Now, regardless of what the next character is, the file mark
flip-flop remains cleared and the read strobe counter is stepped to 3. As previously stated, a count of
3 enables the
file mark counter; however, the file mark detection logic was disabled by resetting the file mark flip-flop. Upon the

receipt of the next character, the read strobe counter is stepped to a count of 4, RECORD ACT H asserts, and the
read strobe counter is disabled.

3.4

MODEL 9700 POWER SUPPLY CIRCUIT DESCRIPTION

The power supply in model 9700 produces the unregulated and regulated voltages requ1red by motors and
electronics.
3.4.1

Primary Power

Primary power is switchable to allow either 115 V or 220 V mains. Frequency is not critical and may be from 48 Hz
to 500 Hz. These voltages were selected because 220 V mains predominate in Europe. A simple modification allows

230 V operation if required. For 115 V operation, the two 115 V primary windings of T; are connected in parallel

by S2. For 220 V operation, a 105 V tap on primary winding 2 is connected in series with primary 1. Modification
for 230 V operation requires removal of the violet wire and installation of a jumper from S2-6 to S2-3.
3.4.2

Secondary Power

Transformer secondary voltages are rectified to produce nominal unregulated voltages of 24 V (£26 V under light
load) and +8 V. A voltage of 24 V regulated is supplied to motor drive circuits and provides sources from which
+10 V regulated is produced. A voltage of +8 V is the source for a high efficiency +5 V regulator.

3-7

Part 111
3.4.3

+10 Volt Reguilator

Pass transistor Q3 is fed from +24 V and its base is driven by monolithic regulator IC2. Voltage output is determined

by R8 and R9. Q7 and Q8 control power supply tracking when powering down. As +24 V drops due to the discharge
of Cl, Q8 cuts off at approximately 13 V on the +24 V line. When this happens, Q7 is turned on, shorting out R9
and dropping the regulator reference voltage to zero. The +10 V output is cut off and drops to zero. Since +10 V is
the

reference

for -10V, -10 V also drops to zero. This action occurs before the +5 V supply has dropped

sufficiently to cause indeterminate logic states; turn-off transient motions are prevented.
3.4.4

-10 Volt Regulator

The

10 V supply is regulated by pass transistor Q4 driven by Q6. Its reference is +10 V as determined by R13, R14.

In this way, the two regulated voltages are made to track or retain a constant relationship to each other.
3.4.5

+5 Volt Regulator

Integrated Circuit regulator IC1 controls +5 V output in conjunction with pass transistor Q1 and driver Q2. Output
voltage is set by R4, RS5. An inset on the schematic shows the internal circuitry of IC1, IC2. It will be noted that it

consists of a differential amplifier with built-in zener reference together with facilities for short-circuit protection.
Q2 assures that sufficient base drive is available for Q1.

3.4.6

Short-Circuit Protection

Drop-through series resistors (e.g., R10 in the =10 V supply), provide short-circuit protection. If the drop across R10
exceeds approximately 0.6 V, QS is turned on, connecting Q4 base to emitter and cutting off Q4. This corresponds

to approximately 1.5 A under short-circuit conditions. Similar circuits are provided in IC1 and IC2.
3.5

TYPE 3842 ADAPTER CONTROL CIRCUIT DESCRIPTION

This module contains a set of receivers for the adapter control commands:

Synchronous Forward (SFC)

Synchronous Reverse (SRC)

Overwrite (OVW)
Rewind (RWC)

Select (SLT)

Set Write Status (SWS)
Off-Line (OFFC)

It also contains drivers that return the recorder status outputs to the interface:
On-Line (ONL)
Rewinding (RWDG)
File Protect (FPT)
Load Point (LP)
Write Enable (WEN)

Ready (RDY)
End of Tape (EOT)
Tape Running (TNG)

Certain controls and delays are also provided to ensure proper tape motion and transport operation.

3-8

Part 111

3.5.1

Tape Motion Controls

The motion control commands from the adapter, SFC and SRC, are translated on this card into the internal motion

commands of the transport: run normal (RNN), forward (FWD), and reverse (RVS). These internal motion
commands are supplied to the pushbutton control module, where they are combined with commands supplied from
the transport pushbuttons and internal interlocks to generate the commands that initiate actual tape motion on the
ramp generator module.

On this module, SFC and SRC are supplied to an interlocking network that ensures that the tape comes to a stop
before its direction of motion is reversed. The interlocking network includes flip-flop IC1-3, edge circuits 1C2-6 and

IC2-8, NAND gate IC3-6, and interlocking flip-flop IC3-10. Whenever flip-flop IC1 changes states due to a change in
the direction of motion (e.g., from SRC to SFC), its output generates a pulse through the edge circuits consisting of

inverters IC2 and the associated capacitors. The pulse is gated through IC3-6 to the set input of interlocking flip-flop

IC3-10. The flip-flop can be set only if TNG
is true, indicating that the tape is still moving. In this case, TNG low at
input pin W is inverted by IC18-12 and supplies a high input to the clear of IC3. The flip-flop can then be set by the
pulse on its set input, its O output going low. The O output of IC3 then inhibits run normal gate IC15 at pin 2,

setting RNN false. After the tape has ramped down to a stop, TNG goes false, clearing interlocking flip-flop IC3,
whose output then enables the run normal gate. RNN then goes true if the following conditions are satisfied: SLT1
is true, indicating that the transport is on-line and selected by the adapter; BSY
is false, indicating that the transport
is not rewind or searching for the load point; and an SRC command is not given at the load point. (This would
activate NAND gate IC15-8 and would disable the run normal gate at IC15-1.) If the above conditions are satisfied,
RNN goes true at output pin V, and is supplied to the pushbutton control module where it initiates tape motion at

the normal running speed. The direction of motion is determined by the state of flip-flop IC1. If a forward

command (SFC) has been given, the flip-flop is set and its 1-output enables NAND gate IC14-8, provided that SLT1
is true and BSY is false. This generates FWD (forward) true at output pin U. If a reverse command (SRC) has been
given, flip-flop IC1 is cleared and enables NAND gate 1C14-6, generating RVS (reverse) true, providing SLT1 is true,
BSY is false, and LPis false. No adapter reverse command is acknowledged by the transport when the load pomt is
detected.
3.5.2

Write Select

During a write operation, the adapter supplies SWS (set write status) true at pin K; SWS is inverted by IC9-4 and is
supplied to the D input of flip-flop IC7. The flip-flop is toggled provided that the transport is selected and on-line,
after NOR gate IC1-11 is activated by a synchronous motion command. This would activate NAND gate IC1-8 and

trigger one-shot IC4-1, generating a 2 us pulse. On the trailing edge of the pulse, the Eoutput of the one-shot toggles
IC7-3, causing the Q output of the flip-flop to go high and activating NAND gate IC10-11, generating WSEL (write
select) true at output pin H. During an overwrite operation, OVW true is inverted by IC18-8 and sets the D input of
flip-flop IC7-12 high. On the trailing edge of the pulse generated by one-shot 1C4-4, the flip-flop is set and enables
NAND gate IC8-12. One-shot 1C44 also direct-sets flip-flop IC11, whose Q output enables the overwrite gate at

IC8-9. If write status is true, the gate is enabled at IC8-13 and is kept activated as long as a synchronous motion

command is activating NAND gate IC1-8. IC8-8 then goes low and supplies WSEL for the duration of the motion
command only. When a WRITE AMPLIFIER RESET pulse is given at pin P, it toggles flip-flop IC11 to the cleared

state and disables the overwrite gate.
3.5.3

Rewind Flip-Flop

When a RWC (rewind command) is given by the adapter, it sets the rewind flip-flop IC5-3, provided that the
transport is selected, on-line, and not at the load point. The 1-output of the flip-flop then goes high, generating

RWDG true to the adapter and RWCT through an edge circuit consisting of inverter 1C6-6, NAND gate I1C6-8, and

capacitor C5. RWC1 is supplied to the pushbutton control module. The flip-flop is cleared when the tape returns to

and stops at the load point, or when BKN (broken tape)is detected.
3.5.4

End-of-Tape

An end-of-tape indication is set when the EOT marker is encountered in the forward direction and remains set until
the marker is passed in the reverse direction.

3-9

Part 111

A true EOT signal at pin Z if machine status is RWDG (IC10-5,8) and RVS (IC14-6) causes IC11 to be preset by
IC19-8. An EOT status is then signaled at the interface by IC16-3.

Upon passing the EOT marker in the reverse direction, IC13-3 is high and the EOT signal clocks IC11 clear on the
trailing edge of the EOT signal, dropping the EOT signal at the interface. IC11 is preset to the clear state by BKN at
pin X.
3.5.5

Output Status

The status gates on this module are all preconditioned by select and on-line being true; consequently, the transport

returns status indications only when it is selected and on-line. The READY status is generated when BSY supplied
from

the

pushbutton

control module is false and the transport is not rewinding. The

LP output is also

preconditioned by the rewinding status being false.
3.6

MODEL 9000 TAPE MOTION CONTROLS CIRCUIT DESCRIPTION

The circuitry used to carry out the motion commands issued by the adapter or by the pushbutton panels (both the
main eontrol panel and the test panel), is located on Pushbutton Control Card Type 3843 module. This module

generates the motion command lines run normal (RNN1), run fast (RNFI) and reverse (RVS1), which are supplied
to the ramp generator module to initiate actual tape motion.

3.6.1 "Front Panel Pushbutton Controls
The LOAD, ON LINE, and REWIND pushbuttons, located on the main control panel, are connected to respective

flip-flops on Pushbutton Control Card Type 3843. When the LOAD pushbutton is activated, it grounds the input to
inverter IC12-1, setting the load flip-flop which consists of NOR gate IC13-6 and inverter IC12-1. Once the load
flip-flop is set, IC13-6 goes low, is inverted by IC12-4, and removes the direct-clear from on-line flip-flop 1C10-3.
Thus the on-line flip-flop can be set only after the transport has been loaded. When the ON LINE pushbutton is
activated the first time, it toggles IC10-1 to the set, or on-line, position and the outputs of the flip-flops generate

ONL and ONL true. Inverters IC12-8 and IC12-10 are connected as a protective flip-flop on the clock input to
IC10-1. Once the on-line flip-flop has been set, ONL true is inverted twice by IC9, setting the common of the
REWIND pushbutton on the control panel high, disabling that pushbutton. The on-line flip-flop can be cleared by

pressing the front panel pushbutton a second time, or by an adapter off-line command (OFFC1), supplied from the
adapter control module.

The REWIND pushbutton can be activated only when the transport is offline. When activated, the REWIND
pushbutton sets the flip-flop that consists of gates IC8-8 and IC8-6, provided that the transport is loaded at the time

(LOAD true at IC8-13) and test mode is not selected (IC7-8 high). Consequently the transport cannot be rewound
by the pushbutton during test mode, when on-line, or when LOAD is false. When the transport is on-line, the rewind

flip-flop can be alternately set by RWCI, supplied from the adapter control module. The output of the rewind
flip-flop, rewinding (RWDG1), activates NOR gates 1C15-8 and 1C14-6, generating RNF1 and RVSI true to the ramp

generator module, initiating a fast reverse motion to the load point. When the load point is detected, the
photosensor amp driver module supplies the load point pulse at input pin H of the pushbutton control module,
clearing the rewind flip-flop.

An additional flip-flop, IC10-6, is used to locate the tape position. Before the tape is loaded, the flip-flop is cleared
by LOAD false at IC10-8. When the transport is loaded, the direct-clear is removed and NAND gate IC14-11 is

enabled. Since the on-tape flip-flop is still cleared, its Q output high activates NAND gate IC14-8, generating RNN1
at output pin Y, advancing the tape to the load point. When the load point marker is detected, LP true at input pin
21 from the photosensor module is gated through 1C16-3 and direct-sets flip-flop IC10-7 to the on-tape state,
terminating the tape motion. Similarly, when the load point is detected during reverse tape motion, the on-tape

flip-flop is toggled by NAND gate IC16-11

to the clear state, initiating forward tape motion back to the load point.

3-10

Part 111 |

3.6.2

Busy

This module generates a BUSY output when the tape is not loaded, when it is advancing to the load point, or when
the transport is off-line and not in test mode. In any of these cases, NOR gate 1C4-8 is activated
and supplies BSY
true to the adapter control module.
3.6.3

Write Ready

WRDY (write ready) true is generated in two different cases: when the adapter supplies WRITE SELECT true and

the transport is not in test mode (TM false), or when the transport is in the write test mode and flip-flop 1C6-14 is
set. In either case, NOR gate IC1-8 is activated, enabling NAND gate 1C4-5. The gate is activated provided that BSY
is false, FPT (file protect) is false, and the transport is not in reverse motion (RVS1 is false). IC4-3 then goes low, is
inverted by IC5-12, and generates WRDY true at output pin J to Write Amplifier Type 3848.
3.6.4

Test Panel Control

In order to activate the test panel, the transport must be off-line and the test panel STOP pushbutton must be
depressed. In that case, the TEST MODE pushbutton on the test panel can be activated, setting the flip-flop that
consists of inverters IC11-8 and IC11-10, which in turn toggles the test mode flip-flop IC6-6 to the test mode state,

generating TM and TM true. The test mode flip-flop is direct-cleared when the transport is placed on-line or when
the TEST MODE pushbutton is activated a second time. After the test mode flip-flop has been set, the other test
panel pushbuttons are enabled. The WRITE TEST pushbutton may then be activated, setting the protective flip-flop

consisting of inverters IC11-4 and IC11-6, which in turn toggles write test flip-flop 1C6-1 to the write test mode,

provided that forward motion is selected. The Q output of the write test flip-flop then activates NOR gate IC1-8, in
turn activating write ready gate ICS5-3, provided that FPT, RVSI1, and BSY are all false. In that case, WRDY true is
generated at output pin J to the write amplifier module, where it enables the write data strobe circuitry. During the
write test, the write amplifiers generate consectuive all-1s characters which may be used to adjust the skew.

Additional test panel pushbuttons are FORWARD RUN, a normal forward run button, FAST FORWARD, a
high-speed forward button, REVERSE, and FAST REVERSE buttons. The reverse motion buttons can be activated
only if on-tape flip-flop IC10 is set and the tape is not at the load point, activating NAND gate IC3-3, which in turn

activates NAND gate IC7-6 (when the test mode flip-flop is set) and setting the common of the reverse buttons low.

The forward motion commands are terminated when either the STOP pushbutton is activated, clearing the test mode

flip-flop, or the end of tape is detected, in which case EOT 1 true is inverted by 1C17-4, disabling NAND gate 1C7-3

and setting the common of both forward motion buttons high. Similarly, the reverse motion can be terminated)by
activating the STOP pushbutton, which terminates all test mode operations, or when the load point is detected, in
which case LP true is inverted by IC17-3 and disables NAND gates IC3-3 and IC7-6, setting the common of the
reverse buttons high. The pushbutton control module also drives the test panel indicators, lighting the data lamp

when any data is being processed by the write/read electronics, illuminating the skew indicator when the skew is out
of adjustment, illuminating the EOT indicator when the transport is at the end of tape, and illuminating the LOAD
POINT indicator when the transport is at the beginning of tape.

3.7

TYPE 3194/3645 RAMP GENERATOR CIRCUIT DESCRIPTION

The ramp generator produces the proper analog signal inputs to the capstan servo system to control the direction
and velocity of tape motion. The outputs are voltages that rise and fall linearly at controlled rates to highly stable

levels. These analog signals are controlled by digital logic outputs from the control section. Waveforms produced are
shown with the schematic.
Two similar ramp generator circuits are provided: one for normal speed operation and one for high speed operation.
IC4 is an operational amplifier in the run normal speed circuit. The amplifier output is normally saturated in the

negative direction. When its positive input at pin 5 is high, the output saturates at +10 V. This occurs when the run
normal input sets flip-flop IC7. IC4 feeds FETs Q1, Q2 which are connected in a constant-current circuit. The

magnitude of current flow in the circuit is controlled by R3 and R4. R3 controls current in the positive-going

direction, or start ramp, while R4 controls the negative-going stop ramp.

Part 111

Since C1 is charged by a constant current, its voltage rises linearly until clamped by CRI1 to a value one diode drop
below +5 V. Q3 is an emitter follower whose output rises to a value of +5 V, since the emitter can rise one diode
drop higher than the base. When the input from 1C7 to IC4 drops, the voltage fed to QI, Q2 goes to -10 V and Cl1 is

discharged linearly until clamped by the base-collector diode of Q3. Since Q3 base goes one diode drop negative, and
the emitter is at zero, a positive-going ramp has been generated.

The ramp voltage output from Q3 is fed to FET switches Q4 and QS. If forward direction has been selected, Q4 is
on and QS5 is off. The ramp is then amplified by unity gain opcrational amplifier IC3, without inversion, and appears

as a positive-going ramp at test point A. If reverse is selected, Q5 is on and Q4 is off. The ramp is then fed to the

inverting input of 1C3 and appears
as a negative-going ramp at test point A. Forward/reverse selection is controlled
by flip-flop IC6 and Q9, Q10.
Ramp amplitude and, therefore, tape speed is controlled by normal speed control R14 and output summing resistor
R15. The fast forward and reverse ramps are produced by a similar circuit involving amplifiers IC1 and IC2.

However, since rewind speed and ramp time need not be precisely controlled, resistors are used instead of FETs to
charge and discharge C4 and produce an approximate 0.5 second rise/fall time. CR9 and CR10 isolate the ramp
output from any small offsets that may be present in IC2. Rewind speed is controlled by summing resistor R16.

Operational amplifier ICS at zero ramp output has a slight bias produced by R37 and R38, keeping its output
negative. When the ramp rises above the bias, ICS switches to positive output, indicating that the tape is running.

This output is used to gate off the input circuits through 1C10 and IC9. Flip-flops IC7 and IC8 may be reset by run
normal or run fast inputs going false, but cannot be set again until the tape comes to a stop. This prevents damage
from illegal commands and reduces timing requirements.
Type 3645 Ramp Generator includes an additional flip-flop, IC11-8, whose function is to enable consecutive run

normal commands to be received without requiring the tape to ramp down to a stop following each normal speed
operation.

Following a run fast command, however, flip-flop IC11 is set by IC8, inhibiting any run normal

commands until the tape comes to a stop, at which point IC9-6 clears IC11-9, and the 0 output at IC11-8 enables
IC7-2.

3.7.1

Adjustment Procedure

The start/stop time adjustment is as follows:
.

Arrange input signals to the tape transport to start and stop the machine. The rate must allow full ramp
time.

Adjusvt the start ramp (R3) for the required time, observing with an osCilloscope at test point A.

Adjust the stop ramp (R4) for the required time. Time is measured from maximum volts to 0 V.

The speed adjustment is as follows:

3.8

Using a master skew tape, drive the transport in a forward direction at normal speed.

Observe the data rate at read 'amplifiérs and adjust R14 for correct timing.

TYPE 3844 SENSOR AMPLIFIER DRIVER CIRCUIT DESCRIPTION

This module responds to signals from photoresistive cells which sense load point and end-of-tape reflective strips,
and broken tape. In addition, this module contains the file protect circuitry and the write and the erase head drives.

Part 111

3.8.1

BOT, EOT, and BKN Sensor Amplifiers

The load point sensor amplifier and the end-of-tape sensor amplifier operate interdependently to detect the load
point and the end-of-tape markers. The active components in detecting EOT and load point are two operational

amplifiers, IC6 and IC8, and two transistors, Q1 and Q2, in conjunction with associated components. Transistors Q1
and Q2 act as current sources; potentiometer R16 is used to adjust the transistor base currents to equalize the

voltage at the inputs of IC8, the load point sensor amplifier, and IC6, the end-of-tape sensor amplifier. Resistors

R18, R19, R20, and R21 are used to bias the amplifiers’ inputs when plain tape is in front of the photo sensors.
When either the load point marker or the end-of-tape marker is detected,

the resistance of the respective

photoresistive cell is lowered by approximately 60 percent of its unilluminated value. Each cell is returned to +10 V,
and a 30 percent change in its resistance, causing a 30 percent change in the input potential, will be sufficient to

switch the output of the respective operational amplifier. Resistors R17 and R22 serve as feedback loops for noise

protection. Thus when load point is detected, the load point sensor output at input pin Y of this module saturates
IC8, causing its output to go high, and is inverted twice by IC7 to generate LDP (load point) true at output pin 19 to
the pushbutton control module. The output of inverter IC7-8 is also supplied to an edge circuit which produces a
1 us pulse on the trailing edge of LDP. This pulse is output at pin 8 to the pushbutton control module. The EOT
sensor amplifier operates in the same manner, generating
a high output when the EOT marker is detected, and

supplying EOT true at output pin X to the pushbutton control and control adapter modules.

)

When the broken tape photoresistive cell is illuminated, the resistance of the cell is reduced enough for the +10 V to
turn on transistor Q3. The collector of the transistor goes to ground, generating BKN (broken tape) true at output
pin 18. When LOAD is high at input pin U, the output of 1C4-8 is low. This causes the collector of Q3 to be low
through the diode CR3 and the BKN output will be true at output pin 18. Also, when power is initially turned on,

capacitor C9 will cause the BKN output to be high, which presets the load flip-ilop on the adapter control module.
3.8.2

File Protect Circuits

The file protect switch output is supplied to this module at input pin T. When a reel is loaded without a write enable

ring, the switch contact remains grounded; the switch input at pin T is inverted by IC2-6 and enables NAND gate
[C4-13. The gate is activated when BKN is true before the transport is loaded. Whenever the LOAD pushbutton has

not been energized, IC4-8 low grounds the clear input of flip-flop IC4-1 through diode CR14. IC4-2 then issues FPT
(file protect) true at output pin 9 to the adapter control card, while the 0 output of IC4 high is inverted by 1C2-8 to

turn off transistor QS5, disabling the file protect solenoid output at pin P.

When a reel with a write enable ring is used, the file protect switch is opened, setting input pin T high and enabling
NAND gate IC2-13. Again the gate can be activated only when BKN is high, before the transport is loaded. The
output of the gate then goes low to set flip-flop 1C4-5; the flip-flop can be set only after LOAD has gone false. This
provision is made to ensure that the write mode can be selected only at the time tape is first loaded. Once {flip-flop

IC4 is set, its 1 output issues FPT false, and, after being inverted by IC1-10, lights the WRITE ENABLE lamp
through output pin H. The 0 output of the flip-flop low is inverted by IC2-8 and turns on transistor Q5, activating
the file protect solenoid through pin P. The file protect solenoid then draws in the switch pin, and the transport is
ready for the write operation.
3.8.3

Write, Erase Drives

When the file protect switch is grounded, it also turns off transistor Q7, in turn shutting off the current at the base
of Q8. This cuts off the write head and erase head drive currents supplied by transistor Q8. In order for the write
and erase drives to be turned on, the file protect switch must be opened and WRITE READY must be true at input

pin 2. This will activate NAND gate 1C2-3, causing op amp IC3 to turn off transistor Q9, in turn enabling transistor
Q8 to turn on and supply the write and erase head drives at pins 22 and J.
The zener diode into the base of Q7 detects when power is being dropped. This turns off Q7 early enough in the
power-down sequence to turn on Q9 and remove the head voltage supplied by Q8. This avoids putting unwanted
remnants on tape during a power failure.

3-13

Part [1]
3.9

TYPE 4306 SERVO PREAMPLIFIER CIRCUIT DESCRIPTION

This module contains the capstan servo and reel servo amplifier stages. The following paragraphs describe their
operation.

3.9.1

Capstan Servo Amplifier Stage

The capstan servo amplifier portion of this module is a part of a velocity servo system which produces accurately

controlled capstan speeds with linear ramp-ups and ramp-downs. The analog linear signal supplied from the ramp
generator module is input at pin N of this module and is summed with the output of the dc tachometer coupled to
the capstan motor shaft, supplied at pin P of this module. Any difference between the two voltages is amplified by

operational amplifier IC5. The amplification of IC5 is controlled by two negative feedback loops, one supplied
directly from the output of IC5 through resistors R39, R40 and capacitor C9, and the other loop from the capstan
motor through resistor R71. The zero offset of the amplifier is adjusted by potentiometer R56 to eliminate capstan

creep during standstill, as described below.

The output of amplifier ICS is supplied to a pair of complementary driver stages, including transistors Q11, Q12,
Q17, and Q18. The output of these stages is supplied to a pair of power transistors located on the heat sink servo
power assembly, which is on the rear of the unit. The power transistors’ output then energizes the capstan motor,
advancing tape at accurately controlled speeds.

3.9.2

Reel Servo Amplifiers

Takeup and supply reel servos are provided to maintain tape tension at a constant value. Three main components are

included: magpot position sensor, reel servo amplifier, and reel motor.
The magpot position sensor measures tape tension by the position of a spring-loaded buffer arm. At the approximate
center of the arc, sensor output is zero. As the buffer arm moves off center, a positive or negative voltage is

produced which is proportional to the error.

The output of the reel servo amplifier on this module is supplied to a pair of power transistors located on the servo
power assembly on the heat sink on the rear of the unit. The output of the power transistors then energizes the

respective reel motor, returning the buffer arms to their proper locations.
3.9.3

Servo Adjustments

The adjustment given below becomes necessary when a capstan creep is detected during standstill.
1.

Connect an oscilloscope probe to monitor the voltage at output pin X, measuring
the output of the
capstan servo amplifier stage.

With the transport on-line and loaded but in a stopped condition, adjust poteniiometer R56 so that a

straight-line trace is produced. Use the 0.5 V/cm scale on scope.
3.

Observe that the capstan does not rotate.

3.10 TYPE 3631 READ PREAMPLIFIER CIRCUIT DESCRIPTION
Read Preamplifier Type 3631 includes nine identical amplifier stages which accept the analog signals from the read
head winding and supply the amplified outputs to the read amplifier modules.

The channel 0 amplifier stage is shown in the schematic; the other channels are identical. The amplifier stage consists
of high-gain operational amplifier IC1 and negative feedback including resistors R2, R3, R4, RS, and capacitor C2.
The input head signal is filtered by resistor R1 and capacitor C1, and is supplied to the noninverting input of ICI.

The negative feedback network controls the output amplitude and response.

Part 111

In NRZ-only tape units, potentiometer R4, located in the feedback network, is adjusted so that the amplified analog
output at test point A is 9 V peak-to-peak while writing 800 flux reversals per inch.
3.11

TYPE 4218 MAGPOT TENSION ARM POSITION SENSOR CIRCUIT DESCRIPTION

In the reel servo system it is necessary to produce an analog signal representing tension arm position. The signal must

be zero at the nominal resting position of the tension arms and should linearly represent angular deviations from the

center of arm travel by positive and negative voltages. A common method utilizes lamps, photocells, and a shutter to
produce the required voltage. This method suffers from the mortality
of lamps and the relatively slow response of

photocells.

The magpot operates as a differential transformer, an example of which is shown in Figure 3-2.

MOVABLE ARMATURE - ~

@
E )

fl'-h\

==
>

Z— FIXED CORE
E)
11-3050

Figure 3-2

Differential Transformer

Magnetic flux produced by current in winding 1 will produce voltages E, and E; in the other windings. If the
armature is symmetrically located with respect to 2 and 3, flux in the two windings will be equal, and since they

have the same number of turns, E, = E;. If the armature is displaced as shown, E; > Ej3 since the flux coupling E3

has been reduced. Displacement in the opposite direction produces E; > E,. Displacement from center then is
represented by Eg = E; - E5. In the configuration shown in Figure 3-2, this relation is linear only for very small

displacements because area relations are not linear.
The magpot is an adaptation of the above scheme in that there are three windings on a magnetic core. The core in
this case is a ferrite pot core while the armature is half a pot core. Windings 2 and 3 are around legs of the pot core
while 1 is around the center portion common to the two legs. Winding 1 is energized by a high-frequency oscillator

(approximately 200 kHz). The magpot is in balance and E, = E; when the armature couples equally to the two legs.
As the armature is rotated, the area available for magnetic flux increases linearly for one leg and decreases linearly

for the other leg. Thus the difference in induced voltages is a linear representation of angular movement.

_The 200 kHz oscillator is a Hartley circuit comprising Q1, C1, C2, R1, R2. It produces a 40 V peak-to-peak sine
wave across the primary winding.

3-15

Part 111

The two secondary windings are connected in series and their voltages are rectified by CR1, CR2. The two rectificd
voltages are subtracted and referenced to ground. Thus the input to IC1 operational amplificr is a dc voltage equal to
E; - E;. This voltage is null when E, = E3 and is positive or negative depending upon which is larger. Secondary

voltages induced are at all times large enough to overcome the diode drops in CR1, CR2.
DC output of the rectifier circuit is amplified by IC1 and fed from the output to the appropriate reel servo amplifier.
Voltage output for a given angular deflection depends upon coupling between the fixed core and armature at that

setting. The gain relations are such that a spacing of 0.030 in. between core and armature results in 5 V output for
full arm travel. Spacing is established by two 0.015-in. thick plastic spacer washers on the shaft.
If adjustment is required:

Remove tape from the machine. |

Place a short length of tape in front of the broken tape sensor.

Turn power on and press LOAD. The reels will rotate.

Hold the tension arm in approximately the center of the arc. Reel rotation should stop.

5. - If the reel continues to rotate, loosen the set screw holding the armature to the tension arm shaft.
6.

Rotate the armature until reel hub motion ceases. Press firmly against the fixed core to maintain core to
armature spacing.

Tighten the set screw.

Move the arm to its limits of travel and observe directions of reel hub rotation. There are two null
positions 180 degrees apart. The sense of the output is reversed for one null, causing hub rotation to be
wrong. If this null has been chosen, loosen the set screw, rotate the armaturc 180 degrees, and repeat.

Check the output at pin 4 using a voltmeter. Total output swing should be between 10and 12 V(5 V

nomijnal).
3.12

TYPE 4845 DELAY TIMING CIRCUIT DESCRIPTION

Crystal oscillator, dividers, and timing circuits associated with read electronics comprise Type 4845 Delay Timing.

Use of this circuitry eliminates the need for analog delays in forming the read skew gate, detecting gaps, etc. Since
the delays required vary with tape speed, switches are provided to select appropriate delays. Delays required are

fractions or multiples of character times; therefore it is only necessary to change the division ratio
to modify all

required. Crystal-controlled pulses generated are also supplied to write electronics in the test mode to allow writing
an all 1s test pattern. 3.12.1

Crystal Oscillator Divider

ICS together with several discrete components is connected as a crystal oscillator. The two inverter sections are
biased into the linear region by R1, R2, and R3. Positive feedback through Y1 causes the circuit to oscillate at the

crystal frequency. A series of dividers IC2 (+2,6) IC1, IC4 (= 16) are selectable by S1—-S7 to produce two output
frequencies: fr’ which is the repetition frequency of the data to be read (20 kHz at 25 in./sec) and f; which is
32 X fr and divides the bit cell into 32 increments. These are fed to counter circuits which determine delays.

3-16

Part 111

3.12.2

Skew Gate Generation

Skew gate length has three values depending upon operating mode: 1/2 of one bit cell for read, 3/8 for write, and
5/32 for test mode. The write skew gate is shortened to provide a more stringent skew criterion to reveal incipient
skew problems.

Pulse outputs from the nine read amplifiers are wire-ORed and appear at pin R. IC3 buffers the pulse input and feeds
out to the test panel for service use.

The first pulse to appear clears IC14 and counter IC15 begins to count f; pulses. IC15 has been preset clear by low

levels on inputs ABCD. At the count of 16, representing 1/2 character time, IC15 QD has been high and goes low,
setting IC14 and stopping the count. With IC14 set, IC11, a four-stage shift register, starts shifting right. A 1 has

been preset in position A and Os are shifted in, causing the 1 to progress to the right. Shift frequency is f;. At the
time IC14 is set, a 1 is in Q4 and IC12 produces a data transfer pulse to the read amplifiers, causing the data to

appear at their outputs. At the next count Qg goes high, triggering one-shot 1C10 (2 us) and producing a read data
strobe (RDS) at the output. At the third count Qe goes high as a delay, and on the fourth count Qpy goes high. If
strap ST1 is installed, a second data transfer pulse is produced, returning the read amplifier output to zero. After the
fourth shift pulse, the circuit remains quiescent until the next peak pulse.
3.12.3

Skew Lamp

At a time just after the skew gate (at RDS time), output from IC14 is inspected by one-shot IC10. If the skew delay
circuit has been retriggered by a skewed input, IC10 is triggered, producing a relatively long pulse to the SKEW
indicator lamp.
3.12.4

Write Mode

If write is selected, WRDY is high, causing counter IC15 to be preset with a count of 4 by IC12. Operation is

otherwise identical to read operation but delay is reduced from 16 to 12 counts or 3/8 of one bit cell.
3.12.5

Test Mode

In test mode, delay is further reduced to provide a marginal skew check. The counter is preset by the test mode

input (pin U) to 11 and delay is five counts or 5/32 of one bit cell. At 25 in./sec this is 7.8 us. An all 1s pattern on a
properly deskewed machine should fall within this time; however, due to bit crowding on tape, random data
generally will not.

3.12.6

Gap Detection

Type 4845 detects the space between the last data character and the CRC and clears read amplifier outputs. The

read amplifier outputs are again cleared after the CRC (if not all zeros) and once again after the LRC, leaving all
outputs cleared in the IRG. Whenever IC14 is set (between bits), counter chain IC6, IC7 counts f, ; it is cleared by
IC14 if a peak pulse is detected. Should the counter reach a count of 32, indicating a missing bit, IC7 is set which in

turn sets IC8. The next f; pulse, through IC8 pin 3, clears IC7, leaving IC8 set and the counter held clear by IC8 pins
8, 12. IC9 produces a RESET pulse at pin K, clearing the read amplifier. At the next peak pulse, input IC8 is cleared
and the cycle is free to repeat. This peak pulse may result from the CRC, LRC, or the first character of the
succeeding block.
3.12.7

Start Delay

When tape is Stopped (as indicated by RNN) or if BSY or SLT1, or at LP, RDS outputs are gated off by IC19, IC9
and read amplifiers are held reset by IC9.
Upon receipt of an RNN, input counter chain IC17, IC18 is enabled for a count of 128 f_ pulses. This corresponds to
0.16 in. of tape movement. During this time, outputs remain disabled.

3-17

Part 111

3.12.8

Data Lamp

- Drive for the test pan‘ell data lamp comes from IC6 through IC8 pin 6, which is low whenever IC4 is set (between
characters). An inverter on the PCB module actually drives the LED indicator.
3.12.9

Adjustments

No adjustments are required on type 4845. However, the proper setting of the speed select switches is essential. A

chart is given on the schematic showing crystal frequency and switch settings for a variety of speeds.
3.13

TYPE 3848 WRITE AMPLIFIERS CIRCUIT DESCRIPTION

This module generates the internal write data strobe and contains the write amplifier stages for four of the data
channels, channel P through channel 2. These are explained in detail below.
3.13.1

Write Data Strobe Generation

The WDS (write data strobe) is input from the adapter at pin N and is supplied to an edge circuit consisting of

inverters IC5 and IC6, capacitor C8, and NAND gate 1C6-8. If WRDY (write ready) and SLT1 (select) are true at
input pins 12 and 13 of IC6, the gate transmits a short pulse on the leading edge of each input WDS. The pulse is
gated through NOR gate IC5-6 and triggers one-shot IC1-1 on its trailing edge. The Q output of the one-shot supplies

a positive 0.5 us pulse which is gated through NAND gate 1C7-3, provided that the transport is not in a test mode.

The pulse then enables write NAND gates IC11 and IC15, gating the input write data to the write amplifier stages. It
is also supplied as WDS1 to Type 3849 Write Amplifier module. When IC1-13 generates the write strobe, its Q
output triggers the second IC1 one-shot, which in turn inhibits IC6 for a 3.5 us duration, inhibiting any pulses during
that time.

’

If the transport is in test mode, TM true at pin K enables NAND gates IC5-2 and IC7-10, 12 while disabling NAND

gate IC7-2. If WRDY is true, crystal-controlled data frequency f , supplied from the delay timing module, is gated
through NAND gate IC5-12 and NOR gate IC5-6 to generate the test mode strobes. These are gated through the two

IC7 NAND gates and direct-clear the write amplifier flip-flops on this module and on the other write amplifier
module, writing the all-1s characters of the test mode.
3.13.2

Write Amplifier Stages

The data inputs are supplied from the data terminator card at pins R, S, T, and U, are inverted, and then strobed
through NAND gates IC11 and IC15 by the WDSI, generated at test point B. The write channels are then supplied to
the amplifier stages, each consisting of a divide-by-16 counter, a pair of flip-flops, and a pair of drivers. The amplifier

stages are digitally deskewable, where the delay of channels O through 7 is adjusted to coincide with that of the
reference channel, channel P, when read back.

The delay of channel P is permanently set to the count of eight, equivalent to 1/4 character delay, by counter ICS.
Whenever the input data is 1, the WDS pulse is gated through 1C11-8 and direct-clears flip-flop 1C9-13. The Q output

of the flip-flop goes high, removing the direct-clear from the IC8 counter. The counter is then clocked by f; at 32
times the data frequency until the count of eight, at which point the Q y output of the counter goes low and toggles
the IC9 flip-flop to the set state. The Q output of IC9 then goes low, locking the counter and toggling the output
flip-flop 1C9-9. During the next 1 character, the same process is repeated with output flip-flop IC9-9 toggling to the

opposite state. When a O is input, the input NAND gate 1C11-8 does not transmit
the write data strobe, and
consequently the write amplifier flip-flops are not toggled. The outputs of flip-flop IC9-5, 6 are then supplied to a

pair of drivers IC10 which energize the write head, reversing the flux for each 1 while remaining unchanged for each
0, as required for NRZL.

The operation of the amplifier stages of the eight other channels is identical to that of channel P, except that their
delay is digitally adjustable. Four switches are connected to the parallel inputs of the skew delay counters of the
eight channels, as shown for data channel 0. The skew of each channel can be measured and adjusted during the

write test mode, which writes all-1s characters, by observing the analog outputs at the Type 3631 Read Preamplifier
module.

3-18

Part 111
T

Trigger channel 1 of a dual trace oscilloscope on the P channel so that one peak is easily observed. With channel 2 of
the oscilloscope, observe the preamplifier channel that is to be checked or adjusted. Set the switches on the write
amplifier channel so that the peaks of the two observed channels coincide. A small amount of jitter will be seen on
the channel being adjusted due to tape recorder dynamics. Repeat the observations for all eight channels leaving the

P channel as the reference.

Opening the switches reduces the count while closing them increases it. Thus when the switches are all opened the

counter is direct-set to 16, gating the data character to the output without any delay. When the switches are all

closed, the skew counter is set at 0 and the character will be delayed 16 counts, or 1/4 character time behind
channel P.
3.13.3

Write Amplifier Reset

WARS (write amplifier reset) pulse is input at pin P from the data terminator card, and is gated through NAND gate
IC2-3, provided that select 1 is true, to set flip-flop IC2-12. The 1 output of the flip-flop goes high, removing the

direct-clear from shift register IC3. The register is then clocked by f; at 32 times the data frequency. On the seventh
pulse, the Q_

output of the register goes high and is inverted by 1C4-8 to issue WARS], resetting the write amplifier

flip-flops on” this module. WARST is also output at pin H to the Type 3849 Write Amplifier where it resets the
flip-flops of the other amplifier stages. On the eighth pulse to the register, the Q, output goes high and is inverted by

IC4-11, clearing flip-flop IC2 and locking itself until the next WARS
is issued by the interface.
3.14

TYPE 4178 QUAD READ AMPLIFIER CIRCUIT DESCRIPTION

Quad Read Amplifier Type 4178 accepts amplified head signals from the head preamplifier module and supplies
decoded and deskewed data outputs to the adapter. Each module contains four amplifier stages, and each recorder

contains two of these modules. The channel P amplifier stage is located on the read amplifier/clipping control
module. The operation of the channel A amplifier stage is explained in the following paragraphs. The other amplifier
stages operate identically.

The amplified analog signal is supplied from the read preamplifier at input pin E. The signal is filtered through R1,
Cl; the negative half-waves are routed through diode CR1 while the positive half-waves are routed through CR2.

CRI and CR2 are back biased by the negative and positive clipping levels, respectively, supplied from the read

amplifier/clipping control

module,

eliminate

spurious

baseline

pulses.

The negative half-waves are then

differentiated by C4 and R6 and are input at the inverting input of operational amplifier IC1. At the leading edge of
the negative analog half-wave, the differentiated output of C4 and R6 swings negative, crossing zero at the peak of
the analog signal and then going positive until the trailing edge of the analog signal. Normally the op amp output is

low, since the noninverting input of ICl is negatively biased through R7 and R9. When the leading edge of the

differentiated signal exceeds the input threshold, the output of the amplifier swings positive. The amplifier output
returns to O V at the zero crossover of the differentiated signal, corresponding to the peak of the input analog signal.

A similar transition occurs for the positive half-wave, since it is input at the noninverting input of the amplifier.

Consequently the amplifier output goes high and returns low for each 1 character, with the negative-going transition
occurring at the analog peak. The output of the amplifier is limited by diodes CR3 and CR4 and is inverted by

NAND gate 1C2-3. IC2-3 output is supplied to a filtering network, consisting of C6, R11, R12, and CRS5, whose
output is in turn supplied to the Schmitt trigger input of one-shot IC3. The output of IC2-3 is normally high, and
the voltage at the input of IC3-5 is at 3.3 V. When the output of IC1 swings positive, IC2-3 goes low and capacitor

C6 discharges through R12 with a slow time constant, approximately 5 us at 25 in./sec. The voltage is clamped at
OV by diode CRS. When the output of IC1 goes low again at the peak of the analog input, IC2-3 goes high and C6

charges with a much faster time constant, approximately 300 ns. When C6 charges up to 1.8 V, one-shot IC3
triggers, generating a 300 ns pulse. The Q output of the one-shot is connected back to IC2-2, disabling the gate and

preventing the one-shot from being retriggered by spurious pulses on the input.
The positive pulse generated by the Q output of IC3 is inverted by IC2-11 and is output as PULSE OUT at pin V.
The pulses of all the amplifier stages are wire-ORed and supplied to the delay timing module where they are used for

read deskewing and read data strobe generation. The Q output of one-shot IC3 direct-sets flip-flop 1C4-4, the data

3-19

Pert 11

3.7.3.2 End-of-File Bit (14) — Bit 14 is used to indicate that the tape has reached the end of the file. The EOF
flip-flop (Drawing TMA11-0-18) is set by the master tape transport and cleared by INIT or a GO pulse. The input to
the flip-flop is the FMK (file mark) signal from the master tape transport. This signal, when present, indicates that

the transport has detected the end-of-file mark on the tape. The signal sets the EOF flip-flop to produce the EOFF H
|

signal.

3.7.3.3 Cyclic Redundancy Error Bit (13) — The cyclic redundancy error (CRE) bit in the status register indicates
that the cyclic redundancy check has detected a parity error. This check compares the CRC character written during
a write or write-with-extended-IRG operation with the CRC character generated during a read operation.

The comparison of the two CRC characters is performed by logic within the master tape transport. If the two
characters are not identical, then the CRCE from the tape unit becomes a 1 and is applied to gating logic in the

controller error circuits (Drawing TMA11-0-18). The gating logic sets the CRE flip-flop to produce CRE H.
The CRE output of the flip-flop is applied to gating logic associated with the command register ERR flip-flop. Note,
however, that the AND gate is not qualified until both CRE and LRCSD H are present. The latter signal indicates

that the LRC character has been detected. Thus, when a CRC error is detected, the CRE bit in the status register is

set immediately, but the ERR bit in the command register is not set until the LRC is detected. This gives the

controller time to complete the current operation before branching to an error routine by means of the interrupt.
3.7.3.4

Parity Error Bit (12) — The parity error (PAE) bit in the status register indicates that a parity error exists in

The parity error circuits are shown on Drawing TMA11-0-18. An AND gate output is used to set the PAE flip-flop;
this AND gate is qualified by three inputs. The first input is RDS H from the master tape transport, which is used to
sample parity. The second input is either WRITE ENB or READ, because parity is checked during both read and
write operations. The third input is either the BPE (vertical parity error) or LRCE (longitudinal redundancy check

error) signal from the transport. Thus, both vertical and longitudinal parity errors are detected during read, write,

write EOF, and write-with-extended-IRG operations. The entire record is checked, including the CRC and LRC
characters.
|
Note that Jongitudinal parity occurs when an odd number of Is is present in any channel in the record; vertical
parity errors may be even or odd, depending on the setting of the PEVN bit in the command register.

The PAE output of the parity error flip-flop is applied to command register gating logic in the same manner as the
CRE output, as explained previously. In the case of PAE, the PAE bit in the status register is set immediately, but
the command register ERR flip-flop is not set until detection of the LRC character.
3.7.3.5

Bus Grant Late Error Bit (11) — During normal operation, the controller makes an NPR request to gain

control of the bus and initiate a data transfer (either a read or a write). If the controller is still engaged in the NPR

transfer when another NPR request is initiated, a BGL error condition occurs.

The BGL flip-flop is shown on Drawing TMA11-0-18. It is set (indicating an error) when both the NPR ENB and
NPR SET inputs are high. These inputs are received from the NPR input logic (Drawing TMA11-0-11).

If the controller receives either a WRS or RDS pulse from the master tape transport, the NPR logic circuits produce
the NPR SET H pulse. This pulse is gated through an AND gate and sets the NPR request flip-flop on its trailing
edge.

If, however, the NPR transfer is still occurring when the next NPR SET H pulse occurs, the BGL flip-flop is set to

indicate an error. The NPR request flip-flop is cleared at the end of an NPR transaction by the NPR CLEAR BBSY
H signal.

3-20

Part [TT

During a read-after-write operation, WRDY at input pin J is inverted by IC7-12 and disables the automatic clipping
level control by direct-setting the IC10 flip-flops, keeping the 1C11 counter direct-cleared. At the same time, WRDY
true activates NOR gate 1C134, enabling the higher clipping level, while the O output of IC11-5 low enables the

normal clipping level. Thus the normal and high clipping levels are combined to generate a still higher clipping level
used during read-after-write only.

The automatic clipping level control is also disabled when the adapter supplies AUTO DISABLE true at input pin N,

or when BSY is true at input pin Y of the module. In either case, NOR gate IC7-6 is high, and direct-sets the IC10
flip-flops which in turn keep the reread counter IC11 cleared.
Operational amplifier

IC6 is connected with negative feedback through R26, establishing its gain at a value

determined by the ratio of the input resistance to +10 V switched by IC13 to the value of R26 (22K).
Capacitor C10 acts as an integrator, slowing the response of 1C6 to a change in input, which avoids coupling enough
signal through C4 and CS into IC1 to cause a spurious output. ICS is connected as an inverter, outputting an equal

but opposite polarity voltage to that voltage at 1C6-10. The negative clipping level voltage (TPD) and positive
clipping level voltage (TPC) are then applied to each read amplifier through a resistor dividing network to backbias

diodes CR1 and CR2. This establishes the amplitude of analog input from the read preamplifier required for IC1 to
switch and thus detect data.

3-21

Part 11

‘

CHAPTER
4

PARTS IDENTIFICATION

Figures 4-1 through 4-3 and Tables 4-1 through 4-3 show the location and identify parts comprising the TS03
DECmagtape Transport. Table 4-4 lists replaceable [spare parts.

NOTE
See the engineering drawing set for parts information on the

M8920 adapter module.

4-1

Part T

Figure 4-1

Front Panel Parts Identification

Part 111
Table 4-1

Illustrated Parts Breakdown for Figure 4-1
Item

Part No.

1-1

Description

Control Panel Assembly (Note 1)

1-2

151-0057-001

Pushbutton Switch Assembly

1-3

151-0038-001

1-4

~190-4448-001

1-5

- 291-3922-xxx

- 391-4440-xxx

1-7

Power Switch

~ LED Display, PC Board Assembly

Switch Cover (Note 1)
Control Panel (Note 1)

®o

Dust Cover Assembly

1-8

- 190-2744-001

~ Hub, Quick Release (Note 2)

1-9

- 198-0011-001

Hub Bearing Assembly

1-10

1-11
1-12

190-2772-001

ke
*

1-13

Takeup Hub

Capstan Wheel
Tape Guide Assembly

291- 1509001

- Head Cover (Note 1)

1-14

- ®

1-15

Head Assembly

1-16

Photosensor Assembly, Broken Tape

1-17

Tape Cleaner

1-18

1-19
1-20

190-4554-001
*
SR

1-21

Magpot Circuit Module

1-22

Spring, Tension

1-23

. *®

1-24

Reel Motor Assembly

1-25

Belt, Supply Drive

1-26

Belt, Takeup Drive

1-27

File Protect Switch Assembly

1-28

190-4013-001

Connector PC Board Assembly

Photosensor Assembly, Load Point, EOT

Tension Roller Guide Assembly

- Tension Arm Bearing Assembly
- Magpot Tension Sensor Assembly
-

Tension Arm Assembly

1-29

191-0805-001

Pulley, Reel Drive

1-30

Capstan Motor/Tachometer Assembly

1-31

Read Preamplifier PC Board Assembly

NOTES

Specify logo and paint color if different from standard. |

Order repair kit 198-0100-001 as spare (Table 4-4).

*Indicates replaceable part. For part number, see Replaceable Parts List (Table 4-4).

4-3

Part 111

Figure 4-2 Tape Transport Parts Identification (Top View)

4-4

Part I
Table 4-2

Hlustrated Parts Breakdown for Figure 4-2
Item

2-1

Part No.

190-4442-001

Description

Power Supply/Card Cage Assembly

2-2
23
24
2-5
2-6

. *
|
Transformer Assembly
o
Capacitor, 18,000 mF/25V
#
| Capacitor, 39,000 mF/10 V.
190-4206-001
|
Motherboard Assembly
R
~ Rectifier

2-7
- 2-8

o
%

29
2-10
2-11

*
*
L

~ Servo Preamplifier Module
‘Sensor Amplifier/Driver Module

Ramp Generator Module
Pushbutton Conttol Module
Control Interface Module

2-12

190-3841-001

Control Terminator Module

2-13

Delay Timing Module

2-14

-k

Read Amplifier/Clipping Control Module

2-15

Quad Read Amplifier Module

2-16

190-3860-001

Data Terminator Module

2-17

Four-Channel Write Amplifier Module

2-18

Five-Channel Write Amplifier Module

*Indicates replaceable part. For part number, see Table 4-4.

4-5

Part 111

3 wEEE

5
Figure 4-3

Tape Transport Parts Identification (Rear View)

Table 4-3
Illustrated Parts Breakdown for Figure 4-3

Item

Part No.

Description

3-1

Voltage Regulator/Servo Power Assembly

3-2

190-4352-001

Voltage Regulator PC Board Assembly (Note 1)

3-3

127-0003-001

Power Receptacle

3-4

Fuseholder

3-4

Fuse, 3AG, 3 A (115 V operation)

Fuse, 3AG, 1.5 A (220/230 V operation)

3-5

Switch, 115/220 V

3-6

Power Cord (not shown)

3-7

148-0122-001

Power Transistor Type MJ802 Motorola (Note 1)

3-8
3-9
3-10

148-0121-001
148-0102-003

Power Transistor Type MJ4502 Motorola (Note 1)
Power Transistor Type MJ900 Motorola (Note 1)
Power Transistor Type MJ1000 Motorola (Note 1)

148-0102-004
148-0053-001

3-11
3-12

148-0075-001

Power Transistor Type 2N3055 (Note 1)
Power Transistor Type 2N4910 (Note 1)

NOTES

Normally voltage regulator/servo power assembly is replaced as a module. These
parts are listed for reference purposes.

*Indicates replaceable part. For part number, see Table 4-4.

4-6

Part 11T
Table 4-4

Replaceable/Spare Parts

Item

Part No.

Description

Qty Spare

1-1

1984439-001

Control Panel Assembly

1-7

198-2771-xxx

Dust Cover Assembly

1-11

198-2605-001

Capstan Wheel

1-12

198-1509-001

Tape Guide Assembly

1-14

198-2399-010

Head Assembly, Nine-Track

1-14

198-2399-003

Head Assembly, Seven-Track

1-15

198-1138-001

Photosensor Assembly, Load Point/EOT

1-16

198-1139-001

Photosensor Assembly, Broken Tape

1-17

198-2747-001

Tape Cleaner Assembly

1-18

198-2647-002

Roller Guide Assembly

1-20

198-0013-001

Magpot Tension Sensor Assembly (includes Magpot

1-22

198-0017-002

Spring, Tension (package of 2)

1-23

198-2827-001

Tension Arm Assembly

1-24

198-4438-001

Reel Motor Assembly

1-25/

198-0101-001

Belt Kit (1 each supply/takeup)
-

Circuit Module)

1-26

Note

1-27

198-2641-001

File Protect Switch Assembly

1-30

198-2484-001

Capstan Motor Assembly

1-31

198-3631-xxx

Read Preamplifier Printed Circuit Board Assembly

2-2

198-4474-601

Transformer Assembly

NOTES

1. Unless specified, control panels and dust covers will be shipped with standard paint colors. If special paint
or logo is required, please specify.

2. Head is supplied on mounting plate and with face shield and connector. Specify number of tracks. ‘All heads
are read after write with side mounted erase. Deskew chart is furnished with each head.

3. Capstan motor/tachometer assembly is supplied with capstan wheel in case of damage to capstan in
removal.

4. Assembly varies with speed of machine. Please specify when ordering.

5. Delay timing module version varies with machine specifications. Consult card identification strip or
schematic section for module type required.

6. Heat sink assembly includes regulation module 190-4352-001. This module is not readily replaceable
without replacing heat sink.
7. Repair kit contains those items subject to wear.

4-7

Part 111

Table 4-4 (Cont)

Replaceable/Spare Parts
Item

Description

Part No.

Qty Spare

Note

1983625-199 | Capacitor, Electrolytic, 18,000 mF, 25 V min

2-4

198-3610449

Capacitor, Electrolytic, 39,000 mF, 10 V min

2-6

198-0108-001

Rectifier, MR751, Motorola (package of 6)

2-7

198-4306-xxx

Servo Preamplifier Module

2-8

198-3844-001

Sensor Amplifier/Driver Module

2-9

198-3194-xxx

Ramp Generator Module

2-10

198-3843-001

Pushbutton Control Module

2-11

198-3842-001

Control Interface Module

2-13

198-3845-xxx

Delay Timing Module (9-track, 800 characters/in.

4,5

standard)
198-4118-xxx

Delay Timing Module (7-track)

4,5

198-4845-xxx

Delay Timing Module (9-track, special)

4,5

2-14

1984179-xxx

Read Amplifier/Clipping Level Module

2-15

1984178-xxx

Quad Read Amplifier Module

2-17

198-3848-001

Four-Channel Write Amplifier Module

2-18

198-3849-001

Five-Channel Write Amplifier Module

3-1

198-4441-001

Voltage Regulator/Servo Power Assembly

3-4

198-0802-001

Fuse Holder

198-0133-030

Fuse 3AG, 3 A(115 V) (box of 5)

198-0133-015

Fuse 3AG, 1.5 A (230 V) (box of 5)

3-5

198-5001-103

Switch, 115/220 V

3-6

198-0068-001

Power Cord

198-0100-001

Hub Repair Kit

198-0102-001

Brush Replacement Kit, Reel Motor (4 brushes)

198-0103-001

Brush Replacement Kit, Capstan Motor (2 brushes)

4-8

Part 1T

APPENDIX A

TRANSPORT SIGNAL DESCRIPTIONS

AND INTERFACE INFORMATION
A.1 INPUT SIGNALS
All commands from and to the input/output connector are preconditioned by loading the machine and placing it
on-line using the front panel controls. The next commands set up the recorder.

A.1.1

Setup Commands
Signal

Transport Select

Pin No.
P1-J

(SLT)

Description

A level that when true enables all the adapter drivers and receivers
in the transport, thus connecting the transport to the controller.
The transport must also be on-line, and SLT must be true for the

entire write sequence (until tape motion stops). The SLT level
may be removed to disconnect the machine from the system. The

machine will remain in the last condition established by SWS.

Data Density Select
(DDS)

P1-D
|

remote position. When true, this level selects the high read

(Dual Density Only)
A.1.2

Used when the TRANSPORT DENSITY SELECT switch is in the
density (dual density).

Tape Motion Commands

Signal

Overwrite

Pin No.

P1-B

Description

A level that when true conditions appropriate circuitry in the

(OVW)

transport to allow updating (rewriting) of a selected record. The

(Optional)

transport must be in the write mode of operation to utilize the
OVW feature.

Synchronous Forward

P1-C

A level that when true, with the transport ready and on-line,

Command

causes tape to move forward at the specified speed. When the

(SFC)

level goes false, tape motion ramps down and ceases.

Synchronous Reverse
Command

(SRC)

P1-E

A level that when true, with the transport ready and on-line,
causes tape to move in a reverse direction at the specified speed.

When the level goes false, tape motion ceases. If the load point
marker is detected during an SRC, the SRC will be terminated. If
an SRC is given when the tape is at the load point, it will be
ignored.

A-1

Part 111

Signal
Rewind Command

Description

Pin No.
P1-H

A pulse input will rewind the tape past the load point and stop.
The transport will then initiate a load forward sequence and

(RWC)

return the tape to the load point marker. This input will be
accepted only if the load point output is false. The transport may
be taken offline while rewind is still in process. Rewind will
continue normally.

A.1.3

Write Commands
Signal

Set Write Status

Pin No.

P1-K

Description

A level that must be true at the leading edge of an SFC (or RUN
and FWD) when the write mode of operation is required, and

(SWS)

must remain true for a minimum of 10 us after the leading edge

of the SFC (or RUN and FWD). SWS is sampled at the leading

edge of the SFC or SRC (or RUN and FWD), toggling the
read/write flip-flop to the appropriate state. Internal interlocks in
the 9800/9700 will prevent writing in the reverse direction, when
the write enable ring is missing, when the tape unit is off-line,

when loading to a load point, and during a rewind.
These are levels that if true at WDS time will result in a flux

Write Data Inputs
WDP

P2-L

transition being recorded on tape (transport is in the write mode).

‘WDO

P2-M

Data inputs must have settled 0.5 us before the leading edge of

WD1

P2-N

the WDS pulse and must remain quiescent 0.5 us beyond the

WD2

P2-pP

trailing edge of the WDS pulse. The CRCC is written by providing

P2R

- P2S

the correct data character together with a WDS four character

times after the last data character of the record.

P2-T
P2-U
P2-V

‘The LRCC is written using the WARS signal. The LRCC can also
be written by providing the correct data character together with a

WDS. If the LRCC is written (DATA-WDS) in this manner, a
WARS should be given one character time after the LRCC to
ensure proper IRG erasure in case of data input error.
Write Data Strobe

P2-A

‘A pulse of 2 us nominal width for each character to be written.
Writing occurs on the leading edge of the WDS. WDS may be a

(WDS)

1 us minimum, 3 ys maximum pulse. Data inputs must have

settled for at least 0.5 us before the leading edge of WDS and
remain quiescent for at least 0.5 us beyond the trailing edge.

Write Amplifier Reset
(WARS)

P2-C

A pulse of 2 us nominal width that, when true, resets the write
amplifier circuits on the leading edge. The purpose of this line is
to enable writing of the longitudinal redundancy check character

(LRCC) at the end of a record. This ensures that all fracks are
properly erased in an interrecord gap (IRG).

In a nine-track system, the leading edge of the WARS pulse
should be eight character times after the leading edge of the WDS

associated with the last data character in the block (four
character times after the CRCC is written).

Part IIT

Read Commands

A.1.4

A read-after-write machine will always have read selected. When write is selected (SWS), the data just written will be
read back using a high threshold level on the read amplifiers. When SWS is false, the normal threshold is applied to
the read amplifiers.

Signal

Pin No.

Automatic Clipping

P3-6

Description
When true, this level overrides the automatic clipping level

Level Disable

electronics and holds the read electronics in the normal clipping

(ACLD)

level.

A.1.5

Shutdown Commands

The use of a given magnetic tape unit may be terminated by an off-line command. Once this command is given, the
tape unit may be returned to an adapter command only by operating the front panel ON LINE switch.

Signal

Pin No.

Off-Line Command

PLL

(OFFC)

Description

A level or pulse (minimum width 2 us) that resets the on-line
flip-flop to the zero state, placing the transport under manual
control. It is gated only by SELECT in the transport logic,
allowing an OFFC to be given while a rewind is in progress. An

OFFC should be separated from a rewind command by at least
2 us.

A.2

INTERFACE OUTPUT SIGNALS

All output signals are enabled only when the tape transport is on-line and selected.

A.2.1

Status Qutputs

Signal

Pin No.

On-Line

P1-M

(ONL)

Description

A level that is true when the on-line flip-flop is set. When true,

the transport is under remote control. When false, the transport is
under local control.

Transport Ready

P1-T

(RDY)

A level that is true when the tape transport is on tape; that is,

when the initial load sequence is complete and the transport is
not rewinding. When true, the transport is ready to receive a
remote command.

High Density Indicator

(HDI)

P1-F

A level that is true only when the high-density mode of operation

is selected.

(Dual Density Only)
File Protect

P1-P

(FPT)
Write Enable

(WEN)

A level that is true when a reel of tape without a write enable ring

is mounted on the transport supply (or file) hub.
P1-S

A level that is true when a reel of tape with a write enable ring is

mounted on the transport supply (or file) hub. Opposite of file
protect.

A-3

Part 1T

Signal

Pin No.

Load Point

Description

P1-R

A level that is true when the load point marker is under the

(LDP)

photosensor and the transport is not rewinding. After receipt of
an SFC, the signal will remain true until the load point marker

leaves the photosense area. (Circuitry using this output should
not use the transitions to and from the true state.)

Tape Running
(RNG)

P1-V

This is a level that is true when tape is being moved under capstan

control and remains true until tape motion has ceased. (Includes
forward, reverse, and rewind tape motion.)

End-of-Tape
(EOT)

P1-U

A level that is true for the duration of the EOT marker. (Circuitry

using this output should not use the transitions to and from the

true state.)

Rewinding

P1-N

(RWD)

A level that is true only when the transport is engaged in a rewind
operation

returning

the

load

point.

(Goes

true

approximately 5 us after a rewind command is given.)
A.2.2

Read Outputs

Read outputs are present at all times in tape units when a dual gap head is used (read after write). The high threshold
level is selected internally when SWS is selected. In a read/write tape unit (single-gap head), read outputs are
inhibited when SWS is true.

Signal

Pin No.

Read Data Strobe

P3-B

(RDS)

Description
A pulse of 2 us minimum width for each data character read from

tape. Although the average time between two read data strobes is

71 (sec) = [1/s+d)]
where

s = tape speed in inches per second
d = density characters per inch

the minimum time between consecutive read data strobes is less

than this figure due to skew and bit crowding effects. A
guaranteed safe value for the minimum time is 1/2 7 ;.
Read Gap Detect
(RGAP)

P3-N
,

A level that is true approximately nine character spacings after
the last data byte, and remains true until the first data byte of the
subsequent data block.
NOTE

This level will be true whenever tape motion is at rest.

Part 11T
Signal

Pin No.

Read Data Level

Description

Nine

staticisers

are provided, which act as

a one-stage read

RDP

P3-1

RDO

P3-3

appropriate state approximately 1 us before the read data strobe

RD1

P34

and remains in that state until 1 us before the next read data

deskewing buffer. Each output is a level that changes to the

RD2

P3-8

strobe. Data lines return to false condition in the IRG when tape

RD3

P3-9

motion stops, regardless of the last character read.

RD4

P3-1

RD5

P3-1

It is recommended that read data strobes and the read gap detect

RD6

P3-1

RD7

P3-1

be ignored during the first read or write operation from load
point for 7, ms after the load point output goes false, where
7, = 1000/s (s = speed of tape unit).
The read gap in a read‘after-write tape unit is downstream from
- the write gap. Thus when the write gap is initially energized, the
read gap may detect a flux change depending on the initial state
of magnetism on the tape.

A.3

SUMMARY OF INTERFACE CHARACTERISTICS

Figure A-1 shows the location of connectors and pin numbers with signal names.

A-5

[

11-3059

INPUT

OUTPUT

CONTROL CONNECTOR J1 (Cont)

WRITE CONNECTOR J2
Signal

Ground
CO~NOOOHEWN
=

Mnemonic

“~

Off-Line Command

OFFC

On-Line Command

ONL

Rewinding

RWD

File Protect

FPT

Not Used

—

Load Point

LDP

Not Used

Write Enable

WEN

Not Used

Transport Ready

RDY

Not Used

—

End-of-Tape

EOT

— Tape Running

RNG

WARS

Not Used

Not Used
WDP

WD1

Write Data Channel 2

WD2

Read Data Channel P

Write Data Channel 3

WD3

Read Data Strobe

RDS

Write Data Channel 4

WD4

Read Data Channel O

RDO

Write Data Channel 5

WD5

Read Data Channel 1

RD1

Write Data Channel 6

WD6

Write Data Channel 7

WD?7

Read Data Channel 2

RD2

—

Read Data Channel 3

RD3

WDO

Write Data Channel 1

READ CONNECTOR J3

Write Data Channel O

Write Data Channel P

Signal

Write Amplifier Reset

Not Used

Auto Disable
Not Used

Not Used

Overwrite

ovw

Synchronous Forward

SFC

DDS

SRC

Read Data Channel 4

RD4

DDI

Read Data Channel 5

RDb

Not Used

—

Gap Detect

A
A

Synchronous Reverse

Not Used

Data Density Select
Data Density Indicator

Rewind Command

RWC

Spare

RDP

Select

SLT

—

Read Data Channel 6

RD6

Co~NOOTOPdWN
=

Ground

WDS

N. C.

CONTROL CONNECTOR J1
ASITTmMmQOoO®D>»

Active

Write Data Strobe

<C-H0VWxpxpUuvZIrACIT"TmOO®>

Active

Set Write Status

SWS

\Y)

Read Data Channel 7

RD?7

Not Used

Figure A-1 Summary of Adapter Characteristics
A-6

APPENDIX B

DEC/VENDOR TS03 TRANSPORT
PART NUMBERS

Vendor Number

DEC Number

Description

154-0035-001

29-21904

Tape Path Alignment Tool

190-1509-001

29-21905

Tape Guide

190-2399-010

29-21906

Head Assembly

190-2641-001

29-21907

File Protect Assembly

190-2747-001

29-21908

Tape Cleaner Assembly

190-3631-005

29-21909

Read Preamplifier Module

190-3645-002

29-21910

Ramp Generator Module

190-3842-001

29-21911

Interface Control Module

190-3843-001

29-21912

Tape Motion Control

29-21913

190-3848-001

29-21914

Sense Amplifier/Driver Module
Write Amplifier (4-Channel) Module

190-3849-001

29-21915

Write Amplifier (5-Channel) Module

190-4178-004

29-21916

Quad Read Amplifier Module

190-4179-004

29-21917

Read Amplifier/Clip Control Module

190-4220-001

29-21918

Mag Pot PLB

190-4306-001

29-21919

Servo Preamplifier Module

190-4352-001

29-21920

Voltage Regulator PCB.

190-4845-001

29-21921

Timing Delay Module

192-9900-001

29-21922

Test Panel

190-4448-001

29-21923

LED Display

190-4441-001

29-21924

Voltage Regulator/Servo Power Amplifier

190-3468-001

29-21925

Module Extender

190-2647-002

29-21926

Tension Roller

190-2484-001

29-21927

Capstan Motor

128-0091-001

29-21928

Spring

125-0030-006

29-21929

190-4218-001

29-21930

O-Ring
Mag Pot

190-4438-001

29-21931

Reel Motor

151-0057-001

29-21932

Switch

190-1139-001

29-21933

Broken Tape Sensor

190-1138-001

29-21934

Tape Photo Sensor

151-0038-001

29-21935

Switch

125-0006-001

29-21936

Reel Drive Belt (Supply)

125-0015-001

29-21937

Reel Drive Belt (Take-Up)

125-0008-103

29-21938

Bearing

125-0040-001

29-21939

Bearing

154-0001-001

29-21940

Capstan Puller

190-3844-001

B-1

Vendor Number

DEC Number

190-4474-601

29-21941

148-0114-001

29-21942

LED Fairchild FLV-102

148-0108-001

29.21943

Diode MR751

Power Transistor MJ802

Transformer

148-0122-001

29-21944

151-0802-002

29.21945

Fuse Holder

115-3625-199

29-21946

Capacitor (18K MFD or larger)

115-3610-449

29.21947

Capacitor (40K MFD or larger)

198-0100-001

29-21964

Hub Repair Kit

148-0121-001

29-10334

Power Transistor MJ4502

29-19037

Transistor 2N4910

148-0075-001
148-0053-001

148-0102-003
148-0102-004

15-10008

Transistor 2N3055A

15-10712

Transistor MJ-900

15-108353

Transistor MJ-1000

198-0133-030

90-07217

Fuse 3 A-3 AG(115V)

198-0133-015

90-08388

Fuse 1.5 A—3 AG (230V)

B-2

Reader’s Comments
b

TMA11-M DECMAGTAPE SYSTEM
MAINTENANCE MANUAL
EK-TMA11-MM-PRE

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Organization

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FIRST CLASS

PERMIT NO. 33
MAYNARD, MASS.

BUSINESS REPLY MAIL

NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES
-

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Digital Equipment Corporation

Technical Documentation Department
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Maynard, Massachusetts 01754

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[I[JEIAEI] worLowioe sates anp service

MAIN OFFICE AND PLANT

Maynard, Massachusetts, U.S.A. 01754 + Telephone. From Metropolitan Eoston: 646-8600 « Elsewhere: (617)-897-5111
TWX: 710-347-0212 Cable: DIGITAL MAYN Telex: 94-8457

DOMESTIC
NORTHEAST

- MID-ATLANTIC (cont)

CENTRAL (cont.)

Princeton

REGIONAL OFFICE:

235 Wyman Street, Waltham, Mass. 02154
Telephone: (617)-890-0330/0310 Dataphone:

MICHIGAN

U.S. Rout
1. Princeton,
e New Jersey 08540
Telephone (609)-452-2940

CONNECTICUT

Dataphone. 609-452-2040
-

1 Huntington Quadrangle

Suite 1507 Huntington Station. New York 11746
””Tellphunn (518)-504-4’3! (212)-895-8095

ster

130

Allens Creek Road, Rochester, New Vovk

Dataphone 716-244-1680

MASSACHUSETTS

Digitat Hall
1740 Walton Road. Blue Bell, Pennsylvania 19422
Telephone: (215)-825-4200

One Iron Way

TENNESSEE

Marlborough

MID-ATLANTIC
REGIONAL OFFICE:
.
U.S. Route 1, Princeton, N-wuncym

FLORIDA
Ortando

2815 Clearview Place. Sul!e xuo
Atlanta, Georgia 03040
Telephone: (404)-451-7411
Dn-phom mzm

Dataphone: 919-489-7832

Fairfield

253 Passaic
Ave . Fairfield. New lersey 07006
Dataphone: 201-227-9280

Metuchen

Telephone: (201)-549-4100/2000

Dataphone: 918-749-2714
-

Dmonn 4|2&4¢m

LOUISIANA

6656 Hornwood Drive
Monterey Park. Houston, Texas 77036
Telephone: (713)-777-3471
Dataphone: 713-777-1071

New Orleaos

WISCONSIN

Dataphone: 312-438-2500

Telephone: (504)-837-0257

Telephone: mms« 1/5428

Dataphone: 505-294-2330

Portland

Suite 168

5319 S.W. Westgate Drive. Portiand, Oregon 97221
Telephone: (503)-297-3761/3765

UTAH

Salt Lake City

429 Lawn Dale Drive, Salt Lake City. Utah 84115
Telephone: (801)-487-4669
Dataphone: 801-467-0535

Bellevue

13401 N E. Bellevue, Redmond Road, Suite 111
Bellevue, Washington 98005

Milwaukee

8531 West Capitol Drive. Milwaukee, Wisconsin 53222

Dataphone: 504-833-2800

10200 Menual N | E Mbuqu:ruuo New Mnlcu umz
OREGON

- HOUSTON

Metairie. Louisiana 70002

Dataphone: 201-548-0144

Albuguerque

Pl
North, Suite 513
2880 LBJ Freeway, Dallas, Texas 75234
Telephone: (214)620-2051
Dataphone: 214-620-2061

Chicago

Dataphone: 303-770-6628

NEW MEXICO

400 Penn. Center Boulevard, Pittsburgh, Pennsylvania 15235

3100 Ridgelake Drive, Suite 108

95 Main Street. Metuchen. New Jersey 08840

Telephone: (3037706150

PENNSYLVANIA
~ Pittsburgh

Dataphone: 317-247-1212

Dataphone: 213-478-5626

COLORADO
7901 E. Bellevue Avenue
g
Suite 5, Englewood. Colorado 80110

Dataphone: 513-298-4724

Telephone: (918)-749-4476

ILLINOIS

1850 Frontage Road
Northbrook. Illinois 60062

NEW JERSEY

Telephone: (213)-473-3791/4318

TEXAS

Telephone: (317)-243-8341

Dataphone: 415-562-2160

West Los Angeles
1510 Cotner Avenue. Los Amlel. Cnll'oml- ms

Dataphone: 216-946-8477

Telephone: (4|2)~msm

Indianapolis. Indiana 46224

3700 Chapel Hill Bivd.
Durham, North Carolina 27707

Telephone: («s)—ssmnm

OKLAHOMA
Tulsa
3140 S. Winston
Winston Sq. Bldg. Suite 4. Tulsa, Oklahoma 74135

21 Beachway Drive, Suite G

Durham/Chapel Hill
Executive Park

Oakland
7850 Edgewater Drive, Oakland, California 94621

Dayton, Ohio 45439
Telephone: (513)-294-3323

Indianapolis

Dmbum:714-280-7825

San Francisco
1400 Terra Bella, Mountain Vllw. California 94040
Telephone: (415)-964-6200
Dataphone: 415964-1436

3101 Kettering Boulw-d

- INDIANA

NORTH CAROLINA

Telephone: (714)-280-7880/7970

Dayton

Ex 78

Dataphone: 714-979-7850

San Diego
6154 Mission Gorge Road
Suite 110, San Diego, California

Dataphone: 816-461-3100

Telephone: (216)-946-8484

1850 Frontage Road. Northbrook, linois 60062
Telephone: (312)-498-2500 Dataphone: 312-498-2500

Atlanta

Telephone: (714)-979-2460

2500 Euclid Avenue, Euclid. Ohio 44117

REGIONAL OFFICE:

GEORGIA

2110 S. Anne Street, Santa Ana, California 92704

Cleveland

Suite 130, 7001 Lake Ellenor Drive, Orlmdo Flurldim

Dataphone: 305-859-2360

Santa Ana

~ OHIO

Lanham 30 Office Building
4900 Princess Garden Parkway, Llnhlm Murylmd
Telephone: (301)-459-7900
Dataphone: 301-459-7900 X53

Dataphone 602-268-7371

CALIFORNIA

St. Lous,
Suite 110. 115 Progress Parkway
Maryland Heights, Missouri 63043
Telephone: (314)-878-4310
Dataphone: 816-461-3100

WASHINGTON D C.

Telepnone: (609)-452-2940

Telephone: (201)-227-9280

Telephone (602)-268-3488

Dataphone. 313-557-3063

Telephone: (816)-252-2300

Knoxville
6311 Kingston Pike, Suite 21E
Knoxville, Tennessee 37919
Telephone: (615)-588-6571
Dataphone: 615-584-0571

Telex 710-3470348

Telephone: (919)-489-3347

4358 East Broadway Road. Phoenix, Arizona 85040

Phoenix

12401 East 43rd Street, Independence, Missouri 64055

Philadelphia

6700 Thompson Road. Syracuse. New York 13211
Telephone: (315)-437-1593/7085
Dataphone: 315-454-4152

Telephone: (SIS)-SFMSO

23777 Greenfield Road
Suite 189
Southfield. Michigan 48075

MISSOURI
Kansas City

PENNSYLVANIA

Syracuse

~ Telephone (617)-481-7400

ARIZONA

| 8030 Cedar Ave. South, Minneapolis, Minnesota 55420
- Telephone: (612)-854-6562-3-4-5
Dataphone: 612-854-1410

810 7th Ave., 22nd Floov
New York, N.Y. 10019
Telephone: (212)-582-1300

Dataphone: 408-735-1820

Detroit

Minneapolis

NEW YORK

Marlborough, Mass. 01752

Telephone: (408)735:9200

MINNESOTA

Telephone (203)-255-5391

Telephone: (716)-461-1700

310 Soque! Way. Sunnyvale, California 94086

230 Huron View Boulevard, Ann Arbor, Michigan 48103
Telephone: (313)-761-1150
Dataphone: 313-769-9883

Long Island

Fairfield
1275 Post Road, Fairfield, Conn 06430

REGIONAL OFFICE:

Ann Arbor

NEW YORK

Meriden
240 Pomeroy Ave.. Meriden, Conn. 06540
Telephone: (203)-237-8441/7466
Dataphone: 203-237-8205

- WEST

Telephone: (414)-463.9110

Dataphone: 414-463-9115

Telephone: (206)-545-4058/455-5404

Dataphone: 206-747-3754

INTERNATIONAL
'EUROPEAN HEADQUARTERS

UNITED KINGDOM (cont.)

- Digital Equipment Corporation International Europe

READING
Fountain House, Butts Centre

81 route de I'Aire.

- 1211 Geneva 26, Switzerland

Telephone: 427850

Telex:

Reading RG1 70N. England

Telephone: (0734)-583555

22 683

FRANCE

Telex 26840

Digital Equipment France
Tour Mangin
16 Rue Du Gal Mangin

Telephone: (76)-87-56-01

1040 Brussels, Belgium
Telephone: 02139256

Digital Equipment GmbH
MUNICH

Telephone 0221-44-40-95

Telegram. Flip Chip Koeln

Telex 25297

Telephone: 06102-5526

Telephone (514)636.9393

Telephone (403) 435-4881

Telephone: 0511-69-70-95

Oslo 5, Norway
- Telephone: 02/68 34
40

Telex: 922-952

STUTTGART

Telex: 19079 DEC N

2900 Hellerup, Denmark

Titismaantie 6

SF-00710 Helsinki 71

Telephone: (090) 370133
Cable Digita! Helsinki

- UK. HEADQUARTERS

Fountain House. Butts Centre
Reading RG! 70N. England

Telephone (0734)-583555

Telex

Telex 289201

BRISTOL

Telephone Bristol 651-431

Telephone

EALING
Bilton House, Uxbridge Road. Ealing. London W 5.

Telephone 01-579-2334

01.46-41.91

Telex

Telephone. (02)-879-051/2/3/4/5

Telephone (03)-699-2888

43 Parker St . Holborn, London
WC 28 SPT, England
Telephone 01-405-2614/4067

Telex: 843.33615

Digital Equipment Corporation Ltd.

Tetex 2780

MANCHESTER

)

Arndale House

Chester Road. Stretford. Mnnchener M3 9BH
Telex 668666

printed in U.S.A.

MADRID
Ataio Ingenieros S A, Enrique Larreta 12. Madrid 16
Telephone 215 3543
Telex 27249

BARCELONA

Telex 790-30700

Ataio Ingenieros S A . Granduxer 76. Barcelona
6
Telephone: 221 44 66

(092):21 4993

Telex

79092140

(02)-439-2565

NEW ZEALAND

MEXICO CITY
Mexitek. S A
Eugenia 408 Deptos. 1
Apdo Pol}ul
121012
Mesxico 125D

Telephone: (905) 536-09-10

Stanford Computer Cotpomlcn

P O. Box 1608
416 Dasmarinas St. Manil
Telephone 49-68-96
Telex 742.0352

Australia 2065

Telephone

Telex: 011-2594 Plenty

MANILA

SYDNEY
PO Box 491, Crows Nest
NSW

Porto Alegre — RS
Telephone: 24-7411

- PHILIPPINES

West Perth. Western Australia 6005
Telephone

PORTO ALEGRE — RS
Rua Coronel Vicente 421/101

MEXICO

643 Murray Street

SPAIN

~ Management House

790-40616

PERTH

Corsu Ganibald: 49 20121 Milano, Italy

LONDON

Telex

Australia

MILAN

Shiel House. Craigshill. 1ivingston,
West Lothian. Scotland
Telephone 32705
Telex 727113

(072293088

- 60 Park Street. South Melbourne. Victoria 3205

Diqital Equipment SpA

Telephone: 52-7806/1870. 51-0912

Bombay-6 (WB) India
Telephone 38-1615 36-5344
Cable: TEKHIND

MELBOURNE

ITALY

Telex 22371

Ambriex S A

69/A. L lagmohandas Marg.

27 Callie St
Fyshwick. A C T 2603 Australia
Telephone (062)-959073

56059

SAO PAULO

~ Hinditron Computers Pvt Ld.

CANBERRA

Rua Ceara, 104, 2 e 3 andares ZC - 29
Rio De laneiro — GB
Telephone: 264-7406/0461/7625

BOMBAY

Telephone

2ZURICH
Digital Equipment Corp AG
Schaffhauserstr 315
CH-8050 Zurich. Swatzerlund

Fish Ponds Road. Fish Ponds
Bristol. Enaland BS163HQ

Ambriex S A

INDIA

Telex 790-82825

Spring Hill
Brishane. Quecnsland, Australia 4000

Telephone No. 022 2 4C
2 and 20 58 92 and 20 68 93

337.060

RIO DE IANEIRO GB

SANTIAGO
Coasin Chile Lida. (sales only)
Casilla 14588, Correo
Telephone: 396713
Cable COACHIL

133 Leichhardt Street

20. Quai Ernest Ansermet
Boite Postale 23, 1211 Geneva 8. Switzerland

29/31 Birmingham Rd . Sutton Coldfield

Telephone (08)-42-1339

CHILE

BRISBANE

Digital Equipment Corporation S A
GENEVA

BIRMINGHAM
~ Maney Buildings

Warwickshire. England
Telephone: 021-355-5501

SWITZERLAND

Telex 8483278

Virrey del Pino. 4071, Buenos Aires
Telephone 52-3185
Telex: 012-2284

Sao Paulo — SP

Digital Equipment Australia Pty Ltd.
ADELAIDE
6 Montrose Avenue
Norwood. South Australia 5067

HELSINKI

Digital Equipment Co. Ltd.

Rua Tupi. 535

AUSTRALIA

Digital Equipment AB

UNITED KINGDOM

BUENOS AIRES
Coasin S.A.

TWX. 403-255-7408

Cable: DIGITAL MAYN
Telex: 94-8457

FINLAND

Telex 385-9056

ARGENTINA

BRAZIL

146 Main Street. Maynard, Massachusetts 01754
Telephone: (617) 897-5111
From Metropolitan Boston. 646-8600
TWX: 710-347-0217/0212

Hellerupveg 66

Digital Equipment Corporation Ges mb H.
VIENNA
Mariahilferstrasse 136, 1150 Vienna 15, Austria
Telephone: 85 51 86

Telex B10-422.412¢

REGIONAL OFFICE

COPENHAGEN

AUSTRIA

Telephone. (809)-723-8068/67

6104827118

GENERAL INTERNATIONAL SALES

Digital Equipment Aktiebolag

Telex 841722393

Santurce. Puerto Rico 00912

Ontario

644 S W Marine Dr. Vancouver
British Columbia. Canada V6P 5Y1
Telephone (604)-325-3231
Telex 610-929-2006

DENMARK

D-7301 Kemnat. Stuttgart
Marco-Polo-Strasse 1
Telephone: (0771)-45-50-65

407 del Parque Street

VANCOUVER
Suite 202

Trondheimsveien 47

3 Hannover, Podbielskistrasse 102

TWX:

Digital Equipment Corporation De Puerto Rico

TWX: 610-562-8732

CALGARY /Edmonton
Suite 140, 6340 Fisher Road S.E.
Calgary. Alberta, Canada

osLo

HANNOVER

PUERTO RICO

Dorval. Quebec. Canada HOP 2M9

Digital Equipment Corp. A/S

Telex: 41-76-82

Minato-Ku, Tokyo. Japan
Telephone: 5915246
Telex: 781-4208

9045 Cote De Liesse

NORWAY

Am Forstaus Gravebruch 57

No. 18-14 Nishishimbashi 1-Chome

MONTREAL

Telephone 98 1390
Telex: 172 50
Cable: Digital Stockholm

FRANKFURT
8078 Neu-Isenburg 2

Telephone (061)-865-7011

Telephone. (4162709400

Englundavagen 7. 171 41 Solna, Sweden

Telex 888-2269

Kozato-Kalkan Bldg.

2550 Goldenridge Road, Mississauga.

STOCKHOLM
N

Rikei Trading Co.. Ltd. (sales only)

TORONTO

Digital Equipment AB

Telex: 524-226

COLOGNE
5 Koeln 41, Aachener Strasse 311

- Telephone: (613)-592-5111

SWEDEN

- 8 Muenchen 13. Wallensteinplatz 2

Telex: 922-33-3163

Ottawa. Ontario, Canada

108 Rue D'Arlon

GERMAN FEDERAL REPUBLIC

Minato-Ku, Tokyo 107, Japan
Telephone: 588-2771
Telex: J-26428

P.O. Box 11500

Telex: 32533

Digital Equipment N.V./S
A
BRUSSELS

Telex 212-32882

Kowa Building No. 16
— Annex, First Floor
9-20 Akasaka 1-Chome

Digital Equipment of Canada, Ltd.
CANADIAN HEADQUARTERS

BELGIUM

38100 Grenoble. France

Digital Equipment Corporation International

103, Southern Habakuk Street
Tel Aviv, lsrael

CANADA

Rijswijk/The Hague, Netherlands

Telephone: 94 9220

~ JAPAN

DEC Systems Compunn Lid.
TEL AVIV

Telephone: (03) 443114/440763

THE HAGUE
Sir Winston Churchillian 370

- GRENOBLE

EDINBURGH

Telex 8483278

Digital Equipment N.V.

Centre Silic — Cidex L 225

Telephone: 0811-35031

Suite

'NETHERLANDS

~ Digital Equipment France
94533 Rungis, France
Telephone 687-23-33

ISRAEL

Telex

790-20740

Digital Equipment Coarporation Ltd
AUCKLAND
Hilton House, 430 Queen Street. Box 2471
Auckland. New Zealand
Telephone 75533

VENEZUELA

CARACAS
Coasin. C A

Apartado 50939

Sabana Grande No 1. Caracas 105

Telephone 72-8662. 72-9637

Cable INSTRUVEN