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EK-RB730-TD-001

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Document:	VAX-11/730 IDC Technical Description
Order Number:	EK-RB730-TD
Revision:	001
Pages:	171
Original Filename:

OCR Text

EK-RB730-TD-001

VAX-11/730IDC
Technical Description

Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, September 1982

The material in this manual is for informational purposes and is
subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any

errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL's DEC set-8000 computerized
typesetting system.

The following are trademarks of Digital Equipment Corporation,
Maynard, Massachusetts:

Enflnan

DECsystem-10

PDP

DIBOL

UNIBUS

VAX

DEC

DECUS

DECSYSTEM-20

EDUSYSTEM

VMS

MASSBUS

OMNIBUS
0S/8
RSTS
RSX

IAS

CONTENTS

CHAPTER 1

INTRODUCTION

DA DRWN—

GENERAL DESCRIPTION ... e 1-1

INTERFACES

IDC INTERFACES ... oo
e
e e e 2-1
IDC/PORT BUS AND UNIBUS INTERFACES ..o 2-1
CONTOL WOTAS ...
e e, 2-3
IDC Control WOord .........oiiii
e e
iie 2-3
Disk Drive Control Words..........ooooieiie
e 2-3
RLO2 Get Status Command..........ooovueeneeeeeeeeeee e 2-3
RLO2 Seek Command ...........ooooouiiiie
e
e
iie 2-3
R80 Seek Command............oooiimmiiioee
e 2-3
R80 Head Select Command ............ooooommiiimie
e 2-8
R80 Recalibrate Command..............cooouioeimiiieeiieiieeeeeeaee
e . 2-8
Address Information.........
e
....oouuee
e
10-8
e
Status INfOrmMation .........oooiiiiiiii
e e 2-8
IDC Status WOord .....oooiiiieiieeeee
e 2-8
RLO2 Status. ..o
e
e et 2-8
R8O SHAtUS ..o
e e 2-8
Error Detection Information ............oooiiiiieme
e 2-8
Port Microinstruction INPuts ...........cccoouveiiiiiiiiiii
e, 2-16
PORT INSTR INPUL ..o
e, 2-16
READ PORT and SEL ACCIN INputs ...........oooooviimiiiiieiinieceeeeeeeeeee. 2-16
CPU P2 and PORT CLOCK INPULS ......oooiiiiiiniieeeeeeee
e, 2-16
IDC/RBOINTERFACE ...
e
e
e 2-16
REOTAG 3:1and REBO TAG BUS 9:0 ... 2-16
ACLO,GND, and R8O INITIALIZE ..o, 2-21
R80 WRITE DATA and RSO WRITECLOCK .....ooovviiiiieeeeeeenn 2-21
REOSECTOR COUNT 1,2,4,8,and 16.......ccoveeeeeeeeeeeeeeeeeei e 221
R80 FAULT, R80 PLUG VALID, R80 SEEK ERROR,
R80 ON CYLINDER, R80 DRIVE READY, and R80
WRITE PROTECT ... 2-21
RBOSELECT ADDRESS 1and 2 ......coooiiiiiiiiiiceeee e 2-21
R80 INDEX PULSE and R80 SECTOR PULSE.............ccccooovviiiiiiiin, 2-23
R80 READ DATA and R80 READ CLOCK ..........ccooieiiiiiiiiieieeeee 2-23

~NONDL
B W
—

N
I
I
I
E N I SIS S N
hadbadh elel
e

CHAPTER 2
NN
S
T S

Bobh

—

PHYSICAL DESCRIPTION ...ttt 1-1
POWER REQUIREMENT
S ..ot 1-3
FUNCTIONAL DESCRIPTION. ...e, FRUUPTURTRRRR 1-4
Disk Drive Select and Drive Status MONItOr ........veeeeeeneeeee e 1-4
Asserting Disk Drive Commands..................cccccciimiiiiiaeeeeeeeeee
e,
e 1-4
Synchronization of IDC Operation ...............cccuuveimooiieeee
e eeeeeean
eeeeee 1-4
AdAress LOCALION .....c.oovvi
eniiiiee e 1-4
Data Transfers ...
e 1-5
Verifying Data INte@rity ..........oooviviiiiiiiiiiiii
e 1-5
Status Word Generation .........ooouen oot ee oo 1-5

249

IDC/RLO2INTERFACE ... 2-23
RL DRIVE COMMAND and RLSYSTEM CLOCK ... 2-23
RLDRIVESELECT 0and 1 ..ot 2-2
POWER FAIL (ACLO) ...t 2-25
RLWRITEGATE and RLWRITEDATA ... 2-25
e 2-26
e ett
RL DRIVE READY oo
e 2-26
tt
e
ot
..
RL DRIVE ERROR
2-26
ot
..
CLOCK
STATUS
RL
and
RLSTATUS
2-26
t
e
ot
..
PULSE
RL SECTOR
2-26
e
e
e
e
et
t
s
e
et
e
et
e
o
o
A
T
DA
R READ

CHAPTER 3

THEORY OF OPERATION

2.4
24.1

242

243
244
245
2.4.6
247
2438

W W W
W
W
NN
.L,,)Nn—a-—-t—-

e e e e e et s semanaa s 3-1
t
e e et
o
ee
IDC FUN CTION S o
e 3-3
tt
.t
..
ON
OPERATI
IDC
OVERALL

Initiating IDC Functions ..............ccooviniinnniinin et ————————— 3-3
s 3-3
Loading Required INPuts.........cccoiiiiiiiiiiniiiii
Loading the IDC Control Word ..........ccoooiiiiiiieniiiiis 3-3
IDIC OPEIAtION .....eveeeiee ittt ettt sttt 3-4

Transfer of Information and Data

FFOM IDC 10 CPU oo

3.2.3.1

3.23.2
3.2.33

Voo~

WnaWwN—O

LbhbbbhbLwLwwww
ot ot ot ek et e et et et bt \(D OO =] N

wnhHh
W
-

(VS

WL W W W ww
wwwwbwi

3.234

‘

ettt e e e e et e e e s eta e et e e s e sbaere it e e aianes 3-4

IDC Status Information Transfer

(IDC 0 CPU) ..ot
Disk Drive Status Information Transfer

e 3-4

e 3-4
(IDC 0 CPU) ..ottt
ECC/CRC Error Detection Information Transfer

(IDC 10 CPU) ..ot 3-5
Current Address Information Transfer

(IDC t0 CPU) ..o 3-5
Data Transfer (IDC to CPU).....oooviiii 3-5
OVERALL IDC LOGIC FAMILIARIZATION ... 3-5
IDC Port Control LOZIC .....ocuumviieeiiiiii ettt 3-5
MECTOCOMETOIIET oo ieeeee oo es e ettt e e e s e et e s et e et e et ena e sra e e s aare e s esanaeas 3-6
Y - BUS T EANSCEIVETS ... evneeneeeerr et eeeeeraeeeuaeraaeesesaasaneneaeaneesaetrseriernsaiaansansasassens 3-6
Disk Address REZISTET ......ccvmvieeiriiiiiiiiiiiiie et 3-6
Data Input Register, Data Buffer, and Data
Register Control Logic, Data Output Register,

s 3-6
Read Data Tristate Drivers, and R80 Multiplexer.......c..cocoooiiiii
Control Status Re@ISter.......cuvueeeiiiiiiiiiiiiiii e 3-6
CLOCK COMIIOl . oeviiiie e eeeeee e eeeeiee e e e e seeeetee e e e e e mmait s s e e e e e e seasaan s aernn et e 3-9
e e ee et e e e ies e tiaeee s er e s sran et ee e 3-9
TAG BUS CONEIOL.....eeeeneeiiiie
P PPRPRPPS 3-9
U UROI
NS a1 V4 GRTTTUUUUUU R TS RU S U
eiiiree
ieiiimii i s s 3-9
et
Header/Data COMPATALOL........cooovi
Data Shift REGISTET ... ..cevviereiere it 3-9
sesa 3-10
s eeeeeenaeanisas
NRZ Data FOrMAtter ....ovoovveeieeeiiiiiierieeeeeteiinianerereenrssaras
3-10
eeneenee
e
e
s
e
MEIM ENCOUET ..ot eee e e eee ettt e et ee e e e teerr st
3-10
s
tite
ane
st
eiiries
tesite s sessee st
ECC/CREC LOGIC ... uuvieeeiieereie eeeeere
3-10
t
iiieeiiie
e
Read Data SEParator........ccoeuveeeeeiiiiiiii
3-10
tt
Status/Data GALE .......c.vviriereeeeieeneienie et
Disk Data MUultipleXer .......oooeiiiiiiiieiiiiiiiiiiirie e 3-10
Data SyNCHArOMIZET.......eevieii it 3-10
Sector and Index Pulse Multiplexer and Synchronmizer...........coccvveniiiiieiies 3-10

IDC FUNCTIONAL THEORY OF OPERATION ... . 3-11
Seek FUNCLIONS .......oouiiiii e
ree e ere e re e eeeees 3-12
RLO2SEEK ... 3-12
R8O SEEK .. .. i e 3-12
RILO2 Get StAtUS ...uuviiiiieiiiee ittt e e e e et e eeer et e eatra e eeaaseaerbnaesnnnns 3-13
RBO Get STAtUS ... oot
e ettt e e ee e e eeeebe e e e e eaeanens 3-14
Read Header......ooovnnieiieee
e e 3-14
RLO2Read Header .........coovviiniiii
e
30 14
R8O Read Header..........ccooiniii e, 3-15
Write Data, Read Data, and Write Check Data..............ccooooeiiiiiii
e, 3-16
RLO2 Write Data, Read Data, and Write
'
CRECK oo
e e 3-17
R80 Write Data, Read Data, and Write
CECK .o
e
e e e e eeaas 3-24
Read Data Without Header Check ..........cooooiiiiiiiiii
e, 3-32
RLO2 Read Data Without Header Check.............cooviviiiiiiiiiieiii
. 3-32
R80 Read Data Without Header Check.............coooiiiiiiiiiiii, 3-34
WIte FOrmat. ..o
et e e et e e e e e 3-37

3.4.1
3.4.1.1
3.4.1.2
3.4.2
3.4.3
3.4.4

3.4.4.1
3.442

3.4.5
3.45.1
3.45.2
3.4.6

3.4.6.1
3.4.6.2

3.4.7

N
-

IAIE MOAE ..ot
e ee e e et 3-38
DETAILED FUNCTIONAL DESCRIPTIONS ... 3-38
Disk Drive Selection and Drive
STALUS MOMILOT ..ot
e ee e
e e e et e et e ee e enans 3-38
Generationof DRIVESEL Oand 1., 3-39
Generation of RLO2and R8O ... 3-39
Gating DRIVERDY ... 3-39
Gating DRIVE ERR ...t 3-39

TAG Bus Control LOZIC .......oniiiiiiiieeieee
p—

Lo o Lo Lo Lo

Lhinnnin

3438

e 3-39

Asserting R80 Seek, Head Select,

¢ N
W
W N —

— 0V WVLoxXarR
[\)-——
S
O =

—oe

W
W
W
W
L
W
W

UJW.QA)

VRV VRV EV RV RV RV

VRV RVRVEV
RV EV VRV,

and Recalibrate Commands ...............ccoooiiiiiiiiioiee
e, 3-41
Asserting Read Gate........cooooviiiiiiiiiiiiiiier
e 3-41
ASSErting Write Gate........uvviiiieeiieiiieieceeie
e e ee e 3-41
CloCK Control LOZIC .. oevieiiieiiiiiee et
s
e naaaad3-41
|
Enable SYSCLOCK ...t 3-46
Enable RL STATUS CLOCK or CPUCLOCK.......cccoiiiiiiiiiiiiiineccninns 3-46
Enable DISK CLOCK ...ttt
e 3-47
Sync Byte Recognition LOZIC ...c...eeeiiiiiiiiiiiiiiiiiie e, 3-47
RL02 Header Comparison LOZIC........o.ouiimuiiiiiieieeeeeiiieiieeie
e
eceenens 3-50
R80 Header Comparison and Skip Sector
MONIOT LOZIC ..ottt
et e e e e e 3-52
R80 Header Comparison LOZIC .........ieviriiiiiniiiiiiiinieeiiineiciiii
e 3-55
Skip Sector Monitor LOZIC .....cevvuivmiiiiiiieiieeeiiiiiieeeee e 3-57
SKIP SECTOR CONTROL LOGIC ... 3-57
Write Check Data Comparison LOgIC .........oeeveieiiiiiiiiiiieiiiiiiiieiiii
e, 3-58
Interrupt Control LOZIC. ........iiiuiniiiiiiiiiiiiin
e 3-62
UBUSBRS............oeee. et eeeeteetti——aeeeeernnaaeeaetannaaeeeeanaaeaaeaieaernees 3-62
.
PORT XFER REQ ...t ettt 3-63
IDC Control Register, Timeout Logic,

and Status LOZIC. .....cooiiiiiiiiie i
e 3-63
IDC Control REgISter. ... ...iiiiiiiieieie et ee e eceina e e e 3-63
Timeout and Status LOGIC.........ovuiiiiiiiiiiii
e, 3-67
Serializing Data from Data Buffer

’

and Sync Byte Tristate Drivers..........ccooceiiiiiiiiiiiiiiiiiiiiiiecee
e 3-69
3.5.12

Formatting and Loading Disk Drive Read Data
N Data BUffers.......onieieieeeee
e e
e e 3-73

fened

N
W
N
OO0 ~1

paswd
et
s
ewd
et
el
et

i
e
e
e
e
[

—

.wuwwwuwwu
=S

RV
N —
W N —
R —

W 0 Lo W) L 0 Lo W W
bbhbhbhbbuhnn

L
bLbhbhbbhuhbbn

e e e e e ee e 3-90
e ettt e e e et e e e e et et
tt
ee
DESK DIFIVE. oo

Microcontroller Branching, Loops,

e e e e s ae e e are e 3-92
et t
AN SEALLS .o ett
e 3-93
iiiiiniiiiii
oooveioinier
Microcontroller BranChing ..........cc
3-93
i
Microcontroller LOOPS........coviiiiiiiieiiiiiiii
3-93
ieriirii
ooooeiii
Microcontroller Stalls..........
Read Data Separator OPeration............cooooviiriiiniiiiieen i, 3-93

Phase Lock LoOOP (PLL) ...cvuniii 3-95
Data SEPArator........c..eveeeeiiiiiiiiiie e 3-97
MFM Encoding and Write Precompensation................ooooiriiniinicirceniinnnns 3-98
MEFM ENCOQING ... . oiiiiiieiiiiieie et e 3-98
Write Precompensation............eeueeuimiiiinnaeieee e 3-100

MAINTAINABILITY FEATURES

e 4-1
et
MaintenanCe MOE ... .oeneeeeeee etett
Data LoopbaCK........viiieiiiiie e 4-1
Write Inhibit and Timeout Inhibit ..., 4-1
oo oot 4-1
Defeatable ENabIes......

o
ot
o
et
ot
et
et

O~
S W N

—

NINESISESE

PROGRAM INTERFACE

BASIC SYSTEM OPERATION. ...ttt
AN —

LWLLWLLLLWLWRNNPDPDDDN
D—

CHAPTER 5

NUANLAULULLULULLULLL
LN

Initializing/Clearing IDC and R80

MAINTAINABILITY FEATURES ... 4-1
LN~

elel
e s

CHAPTER 4

IDC/CPU Interface LOZIC ...cc.eviiviiiiiiiiiiii it 3-76
Loading CSR . ...eeiiiiieiee e 3-78
Reading CSR ....ooiiiiiiieiiiiiii i 3-79
Loading Disk Address Register............oooioii 3-80
Read Disk Address ReGISter.........uuuiiereiiiiiiiii i 3-81
Reading ECC/CRC LOZIC ......ccouviiiiiiiiiiiiiiiiieic 3-82
Loading IDC Data Buffers ..o 3-83
Reading IDC Data Buffers...........oooooiiiiin 3-86

5-1

e
PROGRAMMING OVERVIEW ..ot
e
tt
et
IDC REZISIETS ...voeeieieeeeeieiie
i
iiiiiiniii
..cccoooci
(CSR)
Register
Control Status
iiiiiii,
..ccooei
(BAR)
Register
Bus Address
Byte Count Register (BCR) ..o

5-1
5-1
5-1
5-6
5-6

IDC Initialization RegISter.......ccoovoiveimiiieeriiiiiiiiiiii i,

5-8

e,
Disk Address Register (DAR)........oovviiiiiiiiic
o
..
(MPR)
Register
Multipurpose
e
ECC Position ReGISter......coeiuiiieiiiiieciiiiiiiiiiiiiie
e
eeenneiiiiececee
....cooovvieieiiiiiie
RegIiSter
Pattern
ECC

ee e e ————tee e —————eeeeaaaeerrereeearanaeeeeabaeeeenaees
Positioning Commands ............. e
e
e e e ee e e s
t
e ettt
SEEK FUNCHION ee
e
e
ireee
e
e
ee
eeieurrriiiee
et
........ooovv
COMMANAS
Transfer
Data
et
Read Header FUNCHON ....ooovnveiiiieeiieee
Write Data FUNCHION. .....ovviiiiieeeeeee et
ee
Read Data FUNCHION ......ooivviiiiieeeiie ettt e e

Read Data Without Header Check Function............c.o.oo.

5-7
5-7
5-8
5-8

5-8
5-8
5-9
5-9
59
5-9
5-9

N
I

n
i

adiadad
i

o
b

e R B

—

B
o

o B9 B

I
b

—
N

e IR B

L
oL
o
i

APPENDIX

ee e e ee e 5-9
e
Wt CheCK FUNCUION ettt
Get Status FUNCHON.......oooiiiiiiee e 5-9
s 5-12
Housekeeping Commands.........cc.cceoeiiiiiiiiiiiiiiie
ettt 5-12
INOP FUNCHION Lottt
e 5-12
R80 ECC HANDLING ..ottt
e, 5-12
HARDWARE ERROR RECOVERY ...ooooiiiiiiiiieeccitceiec
SOFTWARE ERROR CORRECTION ... 5-12
R80 SKIP SECTOR OPERATION ...ttt 5-13
e s e anaras 5-13
R80 Bad Spot Problem ..................e eeeteeeeeteeeeeesaaeeaaaaaeebenaarteee
The Concept of SKip SECtOTING ...ccveieriiiiiiiiiii i 5-13
Software Handling of Skip Sector Errors...........ccoociiiiiiiiin 5-13
Skip Sectoring (with the Automatic Inhibit
s 5-13
t
et ettt
Bt St oo
R8O FORMATTING ...ttt 5-13
e 5-14
EXAMPLES OF SYSTEM OPERATION .....coooiiiiiiii
Seek OPEration .....c.cociieiiiiiiiiiiie e 5-14
s 5-15
Data Transfer Operation (Read /WTrite) ......cccooiiiiiiiiiiiiiiii

PROGRAMMED ARRAY LOGIC DEVICES (PALS) ..o A-1

FIGURES
Figure No.
1-1

Page

Title
Interconnections for Possible Configuration

1-2

of RB730 Disk SUDSYSLEM ...ooviiiiiiiiiiiiiiiiiii i
.. .coveoveriieiiiiiii i
IDC Signal INErfaces
IDC Control Word Data Format and

Bit SIZNIICANCE ...c.eiiereiieie ettt
RLO2 Get Status Command Data Format and

2-2

2-4

Bit SIZNIfICANCE ...c.eiiiiiieiiitiei i

2-5

Bit SIgNifICANCE......iuiieieiieriieiiiiii et

2-6

Bit SigNifICANCE ...eov ittt

2-7

Bit SIZNIfICANCE ... ..eiuieeieieitetceitet e

2-9

RLO2 Seek Command Data Format and

2-5

R80 Seek Command Data Format and

2-6

R80 Head Select Command Data Format and

2-7

R80 Recalibrate Command Data Format and

2-8

RLO2 Read/Write Data Address Data Format and

2-9

R80 Read/Write Data Address Data Format and

2-10

IDC Status Word Data Format and

2-11

RLO2 Status Information Data Format and

2-12

R80 Status Information Data Format and

Bit SIZMITICANCE .. c.eiuviiieiteteeitetere ettt

e 2-10

Bit SIgNifiCANCE ....cveiveeieieetereceect e 2-11

Bit SignifiCaNCE. .....cvieeeteiietirteeiiiert et 2-12
Bit SIgNITICANCE .. ..eiviiiiiie ettt 2-13

Bit SignifiCanCe. .....cceeieiemiiiiiiiiiei it s 2-14

Bit SignifiCaNCE . ...ooveeuiiie ettt 2-15
Vil

2-13

2-14

2-15

2-18

2-19
2-20

Port Microinstructions Format and

Bit SIgnifiCANCE. ....uviiiieeeie et 2-17
,
Timing Relationship of PORT CLOCK and CPU P2
INPULS 10 IDC ..o 2-20
R80 Write Data Format and Data Transfer Timing:
'
IDC tO R8O oottt 2-22
R80 Sector Pulse and Index Pulse Timing.......cccocooeeeeeiiiiiin. e 2-23
R80 Read Data Format and Data Transfer Timing;:
RBO 0 IDC .ottt
ettt
e e 2-24
RL Write Data Format and Data Transfer Timing:
IDC 10 RLO2 ..ottt et 2-25
Format and Bit Significance of RL02 Status
Information Transfer: RLO2 to IDC ..., 2-26
RL Read Data Format and Data Transfer Timing:
RLO2 t0 IDC ..ottt
ettt ettt s ein e 2-27
IDC Functional Block Diagram...........ccccociiiiiiiiiiiii 3-7
Disk Drive Selection and Drive Status Monitor ........cccooccccoiiviini, 3-38
TAG Bus Control Logic Functional Diagram...........ccccoocooccni. 3-40
Clock Control Logic Functional Block Diagram .................ooooi 3-41
Clock Control Logic Timing Diagram ...........e
eitteeeeee aa——earaae e naraeeeeeanaeeeennnraes 3-42
Sync Byte Recognition Logic Functional
BIOCK DIAZIam ......coooviiieiiiiiieiiieeeeeeec et
e 3-46
Sync Byte Recognition Logic Timing Diagram ..., 3-47
RL02 Header Comparison Logic Functional

3-10
3-11

3-12

BIOCK DIagram ......ccoviiiiiieiiieie
et 3-49
RLO02 Header Comparison Logic Timing Diagram ............cccooiiiinin 3-51
R80 Header Comparison and Skip Sector Monitor
Logic Functional Block Diagram.........cccoccoiiiiiiiiiiii 3-52
R80 Header Data Modification and Comparison
|
Data Control TIMING ......ccvviiiiiiiiiee ettt
e ee s ee s saane s
Skip Sector Control Logic Functional Block
D4
¢ Vo | O
OO RO O ST U
P PP SRSPRR
SKip Sector EXample.....cueeiuieiieiiiieeeteetcee e
Write Check Data Comparison Logic Functional
BIOCK DiIagram . ...ttt
ee e
e

Write Check Data Comparison Logic Timing

3-21

3-22

3-54
3-55
3-56
3-57

DRAZIAM L.ooiiiiiie
ettt e 3-59
UBUS BRS Interrupt Control Logic Functional
BlOCK DIA@ram .....ccoiiiiiiiiieee
ettt et et ce e e et
e 3-60
PORT XFER REQ Logic Functional Block Diagram ................cc.c.ccccin, 3-61
- IDC Control Register Timeout Logic and Status
Logic Functional Block Diagram ........cccccccceiriiiiiiiiiiiiiniiiicci
e, 3-62
Data and Sync Byte Serialization Control Logic
Functional Block Diagram .............ooeiveoeiiiiiieiiiie
e e 3-68
Data and Sync Byte Serialization Control Logic
Timing DIAZIAM ... .coiiiiiiiiiiiiee
et
et
e
e 3-70
Read Data Formatting and Storage Control Logic
Functional BIock Diagram ..........cooooiiiiiiiiiiiiiiiicc
e 3-72
Formatting and Loading Read Data Input to FIFO:
Timing DIQgrami.......cccviiiiiiiiieiiiiie ettt e st e s e seee e ee 3-73

viii

IDC Register Source and Destination for
Data and Information Transferred between IDC
and CPU via CPU Y-BUS ....ooooiiiiiiiiec
IDC/CPU Interface Logic Functional
Block DIagram . ..ccooooiiiiie

e, 3-74
e,

3-75

IDC Control Word Transfer Timing (CPU to IDC)......ccooooviiiiiiiieiiiieeeee, 3-76
IDC Status Word Transfer Timing (IDC t0 CPU).......ooooviiviiiiiiiiiieieeeeee 3-77
Disk Drive Control Word and Read /Write Address
Transfer Timing (CPU to IDC) ..ot 3-78

Current Read/Write Address Transfer Timing
_
(IDC 0 CPU) e

3-79

Data Error Information Transfer Timing
(IDC 10 CPU) et
ae e, 3-80
Data Byte Transfer Timing (CPU to IDC) ....ccoooiieiiiiie
e, 3-82
Data Longword Transfer Timing (CPUto IDC) ... 3-83
Data Byte Transfer Timing (IDC to CPU) ...oooovviiiiiiiieeec 3-86
Single Data Longword Transfer Timing

(IDC 10 CPU) ottt
e e eetee e e e e 3-87
Automode Data Longword Transfer Timing
(IDC 10 CPU) ettt
e a e, 3-88
Initialize/Clear Logic Diagram ..........coooiiiiiiiiiiiiiiiieee
e 3-89
Microcontroller Functional Block Diagram......................coo.oii 3-90

Rcad Data Separator Block Diagram ............coooooiiiiiiiiie
e 3-92
VCO Output at Twice Data Rate (Frequency Lock)

TIMING DIaGIami.....cooiiiiiiiiiiiii et
ee
e e e e e e e, 3-93
VCO Output Less Than Twice Data Ratc
TIMING DIAGIaAM. ..ottt
e et ae e aeeanaseees 3-93
VCO Output More Than Twice Data Rate
TIMING DIQGIam.. oot
e e e e et e e e e e 3-94
Loop Lock Settling Time ... 3-94

Data Separator Detailed Diagram ............ccoooiiiiiiiiiiiii
e 3-95
Data Scparator Timing Diagram ..ot - 3-95
MFM Encoding and Write Precompensation

Logic Functional Block Diagram .............cccoeiiiiiiiioic

e 3-97

MFM Encoding and Write Precompensation
Timing Diagram...........ccocceennn. U
UTPPRPURURP 3-98
Write Precompensation Early/Late Bit
COMDBINATIONS ..o
e e e e e e e e e e e e e e 3-99

NN BN
O

—
-

Disk Address REZISLET . ooii ittt
e eee

5-7

Basic PAL Logic Configuration............ccoiiiieiiiiiiiiie
et e e A-1
XOR Logic Function Using PAL LOZIC .....ooooiiiiiiiii
e A-2
Typical PAL SymbologY ...coooueiiiiiiie e
e A-3
PAL Plot LISUNE .ottt
e e e e e e e e e e et e e e eeneees A-5
Logic Diagram:
PALIOLS ... A-7
Logic Diagram:
PALIORA ... A-8
Logic Diagram:
PALTOROG.......
A-9
Logic Diagram:
PALTOR
S .. A-10

TABLES

Table No.

Page

Title

1-1
1-3

1-2

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5-3
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1-1

5-1
5-2

5-3
5-4

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PAL Device Types Used in the VAX-11/730.....ccccoiiiiiiii A-3

CHAPTER 1
INTRODUCTION

1.1
GENERAL DESCRIPTION
The Integrated Disk Controller (IDC) is part of the RB730 disk subsystem, a hardware option of the
VAX-11/730. The RB730 disk subsystem includes the IDC and up to four RLO2 disk drives or the
IDC, one R80 disk drive, and up to three RLL0O2 disk drives. The IDC provides the interface between
the VAX-11/730 CPU and the associated disk drives of the RB730 disk subsystem for the purpose of

data storage and retrieval. This manual presents the IDC technical description. Other documents related to the RB730 disk subsystem of the VAX-11/730 are listed in Table 1-1.
1.2

PHYSICAL DESCRIPTION

The IDC is a single hex-size module (M8388) that plugs into the VAX-11/730 backplane. All electrical
connections for interfacing the IDC with the CPU are provided via the VAX-11/730 backplane. The
electrical connections for interfacing the IDC with an R80 disk drive are provided via connectors J2
and J3. Connector J1 provides the electrical connections for interfacing the IDC with the RL02 disk
drive(s) in a daisy chain fashion. Figure 1-1 shows the electrical connections for one possible configuration of the RB730 disk subsystem.

Table 1-1

Related Documentation

Document

Document Number

IDC Field Maintenance Print Set
R80 Disk Drive Field Maintenance Print Set
RLO2 Disk Drive Field Maintenance Print Set
RLO1/RLO2 Disk Drive Technical Manual
R80 Disk Drive Technical Description
VAX-11/730 Central Processing Unit
Technical Description

MP-01278
MP-01419
MP-01332
EK-RLO12-TM
EK-00R80-TD
EK-KA730-TD

1-1

TERMINATOR

]
|

BACKPLANE F
VAX-11/730 {

]
1

[ 1

]

RLO2

DISK DRIVE

10C

—

F:"

%3
R8O

—

DISK

DRIVE

TKR-1878

Figure 1-1

Interconnections for Possible Configuration
of RB730 Disk Subsystem

1.3

POWER REQUIREMENTS

The 1DC requires approximately 55 watts of dc power. The dc power requirements are as follows:
+5Vat80A
+15Vat05SA
—15Vat0S5SA

1.4

FUNCTIONAL DESCRIPTION

The IDC controls the operatlon of the associated disk drives of the RB730 disk subsystem to store and
retrieve data. IDC operation is initiated by the CPU. The CPU loads the IDC with the information
required to initiate and perform each of the functions necessary in stormg and retrieving data from a
specific address location of the selected disk drive. Once a functionis specified by the CPU, the IDC
controls the operation of the disk drive to perform the function. After the function has been completed,
the IDC, if enabled, generates and asserts an interrupt to the CPU. Table 1-2 lists the functions that
can be specified by the CPU and describes the purpose of each one.
Table 1-2

Function Specified by CPU

Seek

Get status

CPU-Initiated IDC Functions

Purpose

Position the specified disk drive read/write head over the specified
cylinder and enable it.

Retrieve the status information from the specified disk drive and
store it in the IDC data buffer.

Read header

Read from the specified disk drive the header information from the
first sector encountered and store it in the IDC data buffer.

Write data

Write the data contained in the IDC data buffer at the specified

Read data

Read from the specified disk drive the data from the specified
read/write data address and store the data in the IDC data buffer.

Read data without
header check

Read from the specified disk drive the data from the first sector encountered and store the data in the IDC data buffer.

Write check

Read from the specified disk drive the data from the specified
read/write data address and compare this data with data contained

read /write data address of the specified disk drive.

in the data buffers.

Write format

(Used only with R80
disk drive)
Maintenance

Write new header data to each of the 32 sectors of the applicable
R80 cylinder.

Place the IDC in the maintenance mode so that the IDC logic may
be exercised by microdiagnostic routines.

1-3

When the IDC is not performing a CPU-specified function, it operates in the idle mode. In this mode,
the IDC selects and monitors the status of each associated disk drive. If an operational status change is
detected, the IDC alerts the CPU.
The IDC contains the control and monitoring circuitry for:
e

Selecting the CPU-specified disk drive, monitoring disk drive operational status, and enabling the appropriate IDC data paths for interfacing to the selected disk drive

Asserting the CPU-specified disk drive commands to control selection and positioning of the

disk drive read/write heads
e

Synchronizing IDC operation with the selected disk drive or the CPU

Locating the address (sector) to or from which data is to be stored or retrieved

Performing single or successive block data transfers between the CPU and the disk drives

Verifying the integrity of the data through the storage and retrieval cycle

. @

Generating a status word that can be used by the CPU to identify data error detection, the
reason the IDC could not complete a CPU-specified function, or disk drive status changes

1.4.1 Disk Drive Select and Drive Status Monitor
The IDC uses the disk drive select information specified by the CPU to select the desired disk drive.
The IDC also monitors the operational status of the selected disk drive to make certain that the drive is
operational and not busy before issuing further commands. The disk drive select information is also
used within the IDC to select the proper data paths, specify the data buffer storage capacity, and gate
the proper clocks for synchronization.

During the idle mode of operation, the IDC selects and monitors the operational status of the associated
disk drives and records any detected operational status change. If a change is detected, the IDC alerts
the CPU.

1.4.2 Asserting Disk Drive Commands
The IDC controls assertion of the CPU-specified disk drive commands in the format that is compatible
with the selected disk drive. The RLO2 disk drive commands are converted to a serial format and asserted to the RLO2 disk drives; the R80 disk drive commands are gated to the R80 disk drive in a
parallel format.

1.4.3 Synchronization of IDC Operation
Any one of six clocks may be selected by the IDC as the basic timing clock to ensure synchronous
operation between the selected disk drive or CPU and the IDC.
1.4.4 Address Location
|
The IDC compares the read/write address specified by the CPU with the address information read
from the selected disk drive to locate the address (sector) to or from which data is to be stored or retrieved.

1-4

1.4.5
Data Transfers
The IDC provides for single or successive block data transfers between the CPU and the disk drives. A
block of data is defined as the data storage capacity of the disk for each addressable storage location
(sector). Each sector of an RLO02 disk drive provides the storage capacity for 256 bytes of data (one
block). Each sector of the R80 disk drive provides the storage capacity for 512 bytes of data (one
block).

The IDC provides buffering for all data to be written to or read from the disk. The IDC contains two
data buffers: each data buffer provides storage for up to 512 bytes of data. Control of each of the data
buffers is shared by the IDC and the CPU.

The CPU controls the data buffers to load the IDC with data to be written to the disk drives. The CPU
also controls the data buffers to transfer the data contained in the data buffers from the IDC to the
CPU.

The IDC controls the data buffers to store the data read from the disk drives until it is transferred to
the CPU under CPU control. This dual IDC data buffer arrangement provides the capability for reading or writing successive sectors of data. While the IDC is reading or writing one sector of data using
one of the IDC data buffers, the CPU can be using the other data buffer to transfer the data read from
the previous sector or to load the data to be written in the next sector.
1.4.6

Verifying Data Integrity

The IDC verifies the integrity of the data throughout the storage and retrieval cycle. When data are
being written to the disk, the IDC generates a coded word based on the configuration of data written to
the disk. This coded word is also written on the disk during the write data cycle. When data are being
read from the disk, the IDC generates a coded word based on the configuration of data read from the
disk. After the data have been read, the coded word stored on the disk is compared with the coded word
generated from the configuration of the data read from the disk. If the coded words are identical, data
integrity has been maintained throughout the storage and retrieval cycle (the data read are identical to
the data written).
1.4.7

Status Word Generation

During the performance of each CPU-specified function, the IDC tests the results of conditions and
operations required to execute the function. The results of these tests are recorded and formatted to
produce an IDC status word. During the idle mode, the IDC records any detected drive status change.
Any recorded drive status change is provided as part of the IDC status word. The IDC status word can
be read by the CPU.

CHAPTER 2
INTERFACES

2.1

IDC INTERFACES

The clectrical connections between the IDC and the VAX-11/730 CPU (port bus and UNIBUS inter-

faces), the IDC and the R80 disk drive (R80 interface), and the IDC and the RL02 disk drive (RLO2

interface) are shown in Figure 2-1.

All connections for the port bus and UNIBUS interfaces are provided via the VAX-11/730 backplane.
The R80 interface is provided via two ribbon cables. A 60-wire ribbon cable connects J3 of the IDC

with J201 of the R80 disk drive. A 26-wire ribbon cable connects J2 of the IDC with J202 of the R80
disk drive. The RLO2 interface is provided via a 40-wire ribbon cable that connects J1 of the IDC with

J12 of the RLO2 disk drive.

All of the signal lines (except ACLO) at the R80 and RLO2 interfaces are dual signal lines (indicated in

Figure 2-1 by the dual listing of pin numbers at the interface connectors). The first pin number listed
refers to the low level signal line; the second number refers to the high level signal line. These signal

lines are driven or detected by differential line drivers or receivers.

The port bus interface BUS Y D31:D00 signal lines form a common bidirectional bus that interconnects the IDC and floating-point accelerator (FPA) with the Y-bus of the CPU data path module.

These signal lines are driven/detected by octal transceivers on the IDC and the FPA. The rest of the
signal lines at the port bus and UNIBUS interfaces are dedicated signal lines.

All of the input/output signals at the IDC/port bus, UNIBUS, R80, and RL0O2 interfaces are also
shown in Figure 2-1. The following paragraphs discuss the characteristics and significance of the input/output signals at each of the interfaces.
2.2

IDC/PORT BUS AND UNIBUS INTERFACES

The input/output signals at the IDC/port bus and UNIBUS interfaces include BUS Y D31:D00,
CSR17 and CSR14:10, PORT INSTR, READ PORT, SEL ACC IN, CPU P2, PORT CLOCK,

PORT XFER REQ, XFER GRANT, BRS, ACLO, and DCLO.

The BUS Y D31:DO00 signal lines are used to transfer control words, address information, and data
from the CPU to the IDC, and to transfer IDC and disk drive status information, current address infor-

mation, error detection information, and data from the IDC to the CPU. The CPU initiates and controls the transfer of all control words, information, and data between the IDC and the CPU via port

microinstruction inputs to the IDC. The port microinstruction inputs are asserted via the CSR17 and
CSR14:CSR10 signal lines.

The port microinstruction inputs to the IDC, together with the PORT INSTR input, are used to preset
the IDC and to cause the transfer of control words, address information, and data from the CPU to the

IDC. The port microinstruction inputs to the IDC together with the PORT INSTR, READ PORT, and
SEL ACC IN inputs are used to cause the transfer of the IDC and disk drive status information, cur-

rent address information, error detection information, and data from the IDC to the CPU. (The state of

the SEL ACC IN input identifies the READ PORT signal as being applicable to the FPA or the IDC:

a low SEL ACC IN signal indicates READ PORT is IDC specific.)
2-1

BUS Y D00

VAX-11/730

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BUS Y D16

BUS Y 023 ¢ ppy
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&—a—
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STORE (M8394)

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Figure 2-1

[IDC Signal Interfaces

The CPU P2 and PORT CLOCK inputs to the IDC are the basic timing pulses that synchronize the
operation of the IDC with the CPU.

The PORT XFER REQ and UBUS BRS signals are the interrupt signals generated by the IDC. The
PORT XFER REQ output is the fast interrupt output of the IDC. The PORT XFER REQ signal is
asserted by the IDC to signal the CPU that the read data, write data, or write check function requested
by the previous IDC control word input has been completed on the specified sector of data and that the
IDC is waiting for further instructions. The CPU uses the XFER GRANT input to acknowledge the
interrupt. The UBUS BRS output is the slow interrupt and is asserted to the CPU via the UNIBUS.
The UBUS BRS signal specifies to the CPU that the IDC function requested by the IDC control word
input has been completed, that one of the disk drives has changed operational status, or that the IDC
operation has been halted due to an error.
The format and bit significance of the control words, address information, status information, and error
detection information are discussed in Paragraphs 2.2.1 through 2.2.4. The data words transferred between the IDC and the CPU via the BUS Y D31:D00 signal lines may be in either byte (8-bit) or
longword (32-bit) format. The format and bit decoding of the port microinstruction inputs applied via
the CSR17 and CSR14:10 signal lines are discussed in Paragraph 2.2.5. The significance of the PORT
INSTR input, READ PORT and SEL ACC IN inputs, and CPU P2 and PORT CLOCK inputs to the
IDC are discussed in Paragraphs 2.2.6, 2.2.7, and 2.2.8, respectively.
2.2.1

Control Words

The control words input to the IDC via the BUS Y D31:D0O0 signal lines include the IDC control word
and the disk drive control words.
2.2.1.1
IDC Control Word - The IDC control word specifies to the IDC the function to be performed,
identifies the disk drive to be used, indicates whether R80 disk drive skip sectoring will be enabled,
starts the specified function, and indicates if the IDC is to generate an interrupt (UBUS BRS) at completion. An IDC control word input must be applied to the IDC to initiate each of the IDC functions.
The format and bit significance of the IDC control word are shown in Figure 2-2.

2.2.1.2 Disk Drive Control Words — The disk drive control words input to the IDC include the RL02
get status command, the RLO2 seek command, the R80 seek command, the R80 head select command,
and the R80 recalibrate command. The purpose of each of these commands is discussed in the following
paragraphs.

RL02 Get Status Command

The RLO2 get status command is used to cause the transfer of the RL02 status word (Paragraph 2.4.7)
from the RLO2 to the CPU via the IDC. The format and bit significance of the RL02 get status command are shown in Figure 2-3.

RL02 Seek Command

The RLO2 seek command is used to reposition the RLO2 read/write heads over another cylinder. The
RLO2 seck command specifies the direction and number of cylinders that the read/write heads are to
move and which of the two heads is to be used. The format and bit significance of the RL02 seek command are shown in Figure 2-4.
R80 Seek Command

The R80 seek command is used to position the R80 read/write heads over the desired cylinder. The

R 80 seek command specifies the cylinder address over which the read/write heads are to be positioned.

The format and bit significance of the R80 seek command is shown in Figure 2-5.

2-3

Data Format
(BUS Y Data Bits)

Bit Significance®

BUS Y D00
BUS Y DOI
BUS Y D02
BUS Y D03

(F1)
(F2)

BUS Y D06

(IE)

BUS Y D04
BUS Y D05

BUS Y D07
BUS Y D08
BUS Y D09

BUS Y D10
BUS Y D11

(F0) }

(CRDY)
(DS0)
(DS1)

Function Select. These bits specify one of eight functions to be performed by the IDC. These
bits are decoded as shown in the table in the figure.

Interrupt Enable. When set, enables IDC to generate UBUS BRS interrupt when applicable.
Controller Ready. When reset, enables IDC to start function specified. Drive Select. These
bits specify the address of the disk drive to be used to perform the function specified.

BUS Y Di2
BUS Y D13

BUS Y DI9

BUS Y D20

BUS Y D2i
BUS Y D22
BUS Y D23
BUS Y D24
BUS Y D25

BUS Y D26
BUS Y D27
BUS Y D28
BUS Y D29

BUS Y D30
BUS Y D31

(ATTNO)

(ATTNI) '

Attention bits. These bits are used to reset the attention bits asserted to the CPU via the IDC
status word (see Figure 2-10).

{ATTN2)
(ATTN3)

(SSEI)

(SSE FLAG)

(MTN)

Skip Sector Error Inhibit. When set, inhibits R80 skip sectoring.
Skip Sector Error Flag. This bit is used to reset the SSE flag asserted to the CPU via the IDC
status word (sec Figure 2-10).
Maintenance. Used with Function Select bits FO, Fi, and F2 10 select maintenance function
(see the table in this figure).

SO0
—0

v-C

BUS Y D16
BUS Y D17
BUSY D18

R80

MTN
D000 00000 —

BUS Y D14
BUS Y D15

Function Select

iDC

F2 FI

Fo0

Function
Specified

Write Check

[

Maintenance
R80 Write Format

No Operation

Get Status
Seek
Read Header

Write Data

Read Data

Read Data Without

Header Check

(ASSI)

Automatic Skip Sector Inhibit. When cleared, allows automatic skip sectoring.

(WRT INH)

Write Inhibit. When set. inhibits writing to the disk drives and disables timeout from

(R8O

occurring. Used during maintenance function.
R80 Format. Used with Function Select bits FO. F1. and F2 1o specify R80 write format

FORMAT)

function (see the table in this figure).

* - Not used as part of IDC control word.

Figure 2-2

IDC Control Word Data Format and Bit Significance

Data Format

(BUS Y Data Bits)

Bit Significance*

BUS Y D00
BUS Y DOI

(M)
(GS)

BUS Y D02

BUS Y D04

BUS Y D31

§-¢

BUS Y D03

Marker. Used at RLO2 disk drive to indicate a new command word. (This bit must be set.)
Get Status. When set, commands RLO2 disk drive to gate RLO2 status word to IDC.
Reset. When set, commands RLO2 disk drive to clear its error register before gating RL02

(RST)

status word to IDC. (BUS Y D03 must be a 1.)
:

*_ Not used as part of RLO02 Get Status Word
Figure 2-3

RLO02 Get Status Command Data Format
and Bit Significance

Data Format

(BUS Y Data Bits)

Bit Significance*

BUS Y D00
BUS Y D01
BUS Y D02

(M)
(GS)
(DIR)

9-C

BUS Y D03

‘

Marker. Used at RLO2 disk drive to indicate a new command word. (This bit must be a l.)
Get Status. This bit must be cleared for RL02 seek instruction.
Direction. Indicates direction of movement of RLO02 read/write heads. When cleared,
indicates movement toward higher addresses; when set, movement toward lower addresses.
Reset. When cleared, used at RL02 to indicate that a cylinder difference word is being
applied.
Head Select. Used at RLO2 to identify read/write head to be used. When set, selects upper
head; when cleared, selects lower head.

(RST)

BUS Y D04

(HS)

BUS Y D05
BUS Y D06

BUS Y D07
BUS Y D08
BUS Y D09
BUS Y D10
BUS Y D11
BUS Y D12
BUS Y D13
BUSYDI4
BUS Y D15
BUS Y D16

(DF0)
(DF1)
(DF2)
(DF3)
(DF4)
(DF5)
(DF6)
(DF7)
(DF8)
I

BUS Y D31

Difference. These bits are used at the RLO02 disk drive to specify the number of cylinders the
read/write heads are to move.

* - Not used as part of RL02 seek command.

Figure 2-4

RLO02 Seek Command Data Format
and Bit Significance

Data Format

(BUS Y Data Bits)

Bit Significance*

BUS Y D00
BUS Y DOl
BUS Y D02
BUS Y D03

(CA0)
(CAl)
(CA2)
(CA3)
(CA4)
(CAS)
(CA6)
(CA7)

BUS Y D04
BUS Y DO5
BUS Y D06
BUS Y D07

BUS Y D08
BUS Y D09
BUS Y D10
BUS Y D11
BUSY D12
BUS Y D13
BUS Y DI14
BUS Y D15
BUSY D16

Y D31
BUS

Cylinder Address Bits. These bits are used at the R80 disk drive to identify the cylinder
address over which the read/write heads are to be located.

(CA8)
(CA9)

(CA)

Cylinder Address. When set, specifies that this word is a cylinder address word.
Head Select. This bit must be cleared for R80 seek command.
Control Select. This bit must be cleared for R80 seek command.

(HS)
(CS)

* _ Not used as part of R80 seek instruction.
Figure 2-5

R80 Seek Command Data Format
and Bit Significance

R80 Head Select Command

The R80 head select command specifies which one of the fourteen read/write heads of the R80 disk
drive is to be enabled. The format and bit significance of the R80 head select command are shown in
Figure 2-6.

R80 Recalibrate Command

This command is used to position the R80 disk drive read/write heads over cylinder 0. The format and
bit significance of the R80 recalibrate command are shown in Figure 2-7.
2.2.2

Address Information

2.2.3

Status Information

The read/write data address information input to the IDC is used to locate the initial sector of the disk
drive cylinder to or from which data are to be written or read. The current address information output
from the IDC is used to specify to the CPU the complete address of the last sector of data that was
written or read. The format and bit significance of the RL02 and R80 read/write data address information are shown in Figures 2-8 and 2-9, respectively. The format and bit significance of the current address information are the same as the read/write data address input to the IDC.
There are three status information outputs of the IDC; these include the IDC status, the RLO2 status,
and the R80 status.

2.2.3.1 IDC Status Word — The IDC status word specifies to the CPU the contents of the previous
control word input (Figure 2-2), specifies whether the function selected by the previous control word
input was executed successfully and completed within the time allowed by the IDC (approximately 150
milliseconds), informs the CPU about changes in the operational status of the disk drives, provides information that identifies the type of fault detected (if any), and indicates if the IDC had generated a
slow interrupt request (asserted UBUS BRS5). The format and bit significance of the IDC status word
are shown in Figure 2-10.

2.2.3.2 RLO2 Status - The RLO02 status information specifies to the CPU the current operational state
of the RLO2 disk drive, the position of the disk brushes (over the disk or home), whether the read/write
heads are over the disk, whether a fault condition has been detected, and if a new disk cartridge has
been loaded. The RLO2 status information is transferred to the CPU in byte format. The format and bit
significance of the RLO02 status information contained in each byte transferred to the CPU are shown in
Figure 2-11.

2.2.3.3

R80 Status — The R80 status information specifies to the CPU the sector over which the

read /write heads were located when the status data were output from the R80 to the IDC, if an address
plug is installed, whether the drive is operational or has a fault, and the operational condition of the
drive. The R80 status information is transferred to the CPU in byte format. The format and bit significance of the R80 status information contained in each byte transferred to the CPU are shown in Figure
2-12.

2.2.4

Error Detection Information

Error detection information (error position and error pattern) can be provided to the CPU following a
detected error in the data read from the disk. The error position data are transferred to the CPU via the
BUS Y D12:D00 signal lines. These data specify to the CPU the position (location within the sector of
data being read) of the first data bit of the data burst in which the read error was detected. The error
pattern data are transferred to the CPU via the BUS Y D10:DO0O0 signal lines. The error pattern data
specifies to the CPU the correction pattern for the 11-bit data burst in which the read error was detected. During the error pattern data transfer, the BUS Y D12:D11 signal lines are set to a low.

2-8

6°C

Data Format
(BUS Y Data Bits)
BUS Y D00
BUS Y DOl
BUS Y D02
BUS Y D03
BUS Y D04
BUS Y D05
BUS Y D06
BUS Y D07
BUS Y D08
BUS Y D09
BUS Y D10
BUS Y D11
BUSY D12
BUS Y D13
BUSYDI14
BUS Y D15
BUS Y D16

Bit Significance*
(HS0)

(HSI1) {

(HS2)
(HS3)

Head Select bits. These bits are used at the R80 disk drive to select one of the fourteen

read /write heads.

Cylinder Address. This bit must be cleared for R80 head select command.
Head Select. When set, specifies that this word is a R80 head select command.
Control Select. This bit must be cleared for R80 head select command.

Y D31
BUS

* _ Not used as part of R80 head select instruction.

Figure 2-6

R80 Head Select Command Data Format
and Bit Significance

Data Format
(BUS Y Data Bits)

01-¢

BUS Y D00
BUS Y DO1
BUS Y D02
BUS Y D03
BUS Y D04
BUS Y D05
BUS Y D06

BUS
Y D07
BUS
Y D08
BUS
Y D09
BUSY D10
BUS
Y D11
BUS
Y D12
Y D13
BUS
BUSY D14
BUSY D15

Bit Significance*

Return to Zero. When set, used at R80 disk drive to initiate positioning read/write heads
over cylinder 0.

Cylinder Address. This bit must be cleared for a R80 recalibrate command.
Head Select. This bit must be cleared for a R80 recalibrate command.
Control Select. When set, specifies that this word is a control function word. This bit must be
set for R80 recalibrate command.
)

BUSY D16

BUS Y D31

* - Not used as part of R80 recalibrate instruction.

Figure 2-7

R80 Recalibrate Command Data

Format and Bit Significance

Data Format
(BUS Y Data Bits)

11-¢

BUS Y D00
BUSY D01
BUS Y D02
BUS Y D03
BUS Y D04
BUS Y D05
BUS Y D06
Y D07
BUS
BUS'Y D08
Y D09
BUS
BUS
Y DI0
Y D11
BUS
Y D12
BUS
BUS
Y D13
BUSY D14
BUS
Y D15
BUS
Y D16

BUS
Y D31

Bit Significahce*
(SA0)
(SAl)
(SA2)
(SA3)
(SA4)
(SAS)

(HS)

Sector Address. These bits specify the address of one of the 40 sectors of the RLO2 cylinder
to/from which data are to be written/read.

Head Select. This bit specifies which of the two RL02 read/write heads is selected; when set,

indicates lower head; when cleared, upper head.

(CA0)

(CAl)
(CA2)
(CA3)
(CA4)
(CAS)
(CA6)
(CAT)

Cylinder Address. These bits specify the address of the RLO2 cylinder (one of 512) over
which the read/write heads are located.

(CAS8)

* - Not used as part of RL02 read/write data address.

Figure 2-8

RLO02 Read/Write Data Address Data
Format and Bit Significance

¢I-C

Data [ rmat

(BUS Y Data Bits)

Bit Significance*

Y D00
BUS
Y DOl
BUS
Y D02
BUS
Y D03
BUS
Y D04
BUS
Y D05
BUS
Y D06
BUS
Y D07
BUS
Y D08
BUS
Y D09
BUS
Y D10
BUS
Y D11
BUS
BUSY D12
BUSY D13
BUSY D14
BUS Y D15
Y D16
BUS
Y D17
BUS
BUSY D18
Y DI9
BUS

(SA0)
(SA1)
(SA2)
(SA3)
(SA4)
(HS0)

Y D31
BUS

Sector Address. The bits specify the address of one of the 32 sectors of the R80 cylinder (one

of 561) over which the read/write heads are located.

(HS1) )
(HS2)
(HS3)
(CAO0)
(CA1)
(CA2)
(CA3)
(CA4)
(CAS)
(CA6)
(CA7)
(CA8)
(CA9)

Head Select. These bits specify which one of the 14 R80 read/write heads is selected.

Cylinder Address. These bits specify the address of the R80 cylinder (one of 561) over which
the read/write heads are located.

* _ Not used as part of R80 read/write data address.

Figure 2-9

R80 Read/Write Data Address Data
Format and Bit Significance

BUS Y D00

Y DOl
BUS
BUS
Y D02
Y D03
BUS
Y D04
BUS
Y D05
BUS
Y D06
BUS
Y D07
BUS
Y D08
BUS

(FO) }

¢1-¢

Y D09
BUS

(F1)
(F2)

input (See Figure 2-2).

(IE)

Interrupt Enable. Indicates state of 1E bit of previous IDC control word input.
Controller Ready. When set, indicates controller is ready to perform a function.

(CRDY)
(DS0)

(DS |

Y D10
BUS
Y D11
BUS
Y D12
BUS
Y D13
BUS
BUSYDI4
Y DI5
BUS
Y DI6
BUS
Y D17
BUS

(OPI)
(DCK)
(DTL)

Y D19
BUS
Y D20
BUS

(ATTN3)

Y Di8
BUS

Drive Ready. When set, indicates that the presently selected drive is operational and ready to

receive further commands.
Function Select. These bits specify the function selected by the previous IDC control word

(DE)

(ERR)
(ATTNO)

(ATTND) |

(ATTN2) ‘

(ECS0) }

Drive Select. These bits indicate disk drive address specified by the previous IDC control

word input.
Operation Incomplete
Data Check Error

Data Late Error

OPI1

Error Bits. These bits are encoded as shown in

the tabie at right to specify the type of error
detected.

Drive Error
Composite Error

ECC status. These bits define the status of the ECC comparison as shown in table at right.

(ECS1)
(SSEI)

Skip Sector Error Inhibit. Indicates state of SSEI bit of previous IDC control word input.

BUS Y D23

(SSE FLAG)

Skip Sector Error Flag. When set, indicates that the sector read contains a skip sector flag

(IR)

Interrupt Request. When set, indicates that the |DC asserted an interrupt request.
Maintenance. When set, indicates maintenance function was specified by previous IDC

BUS Y D25

(MTN)

DTL

ERR

]

ECC/CRC error in disk

0
0

0
1

0
0

1
1

Timeout error
Header not found

Disk drive reporting an error

ECC/CRC error in disk
data field

header field

Attention Bits. When set, indicates associated disk drive has completed a previously specified
function and is asserting drive ready or that the associated disk drive is reporting an error.

Y D21i
BUS
Y D22
BUS

BUS Y D24

Indicated Error

DCK

0
0

Data buffer empty during
write or full during read

When set, indicates R80 skip sectoring was inhibited.

because it or a previous sector was a bad sector.
control word input.

BUS Y D26
BUS Y D27

(R80)
(ASSI)

R80. When set, indicates R80 disk drive selected by previous IDC control word input.
Automatic Skip Sector Inhibit. When set, indicates automatic skip sectoring was inhibited by

BUS Y D28

(WRT INH)

BUS Y D29

(R80 FORMAT)

Write Inhibit. When set, indicates that timeout was disabled and writing to disk drives was
inhibited by previous IDC control word input.
R80 Format. When set, indicates that the previous IDC control word input specified an R80

previous IDC control word input.

write format function.

BUS Y D30
BUS Y D31

* . Not used as part of IDC status word.

Figure 2-10

IDC Status Word Data Format
and Bit Significance

ECSO

ECS 1

Status

— 00

Bit Significance®*
(DRDY)

0
|

No Error
Data Error

Data Format
(BUS Y Data Bits)

Noncorrectable Error
Correctable Error

(STA)

State. These bits define the operational state of the applicable RLO2 disk drive.

STA

STB

STC

(STB)
(STC)

State is encoded as shown in table at right.

BUS Y D03
BUS Y D04
BUS Y D03

(BH)

Brush Home. When set, indicates that brushes are not over the disk recording area.

000

(HS)

_—
o - -0 0

- O

BUS Y D06

Heads Out. When set, indicates that the read/write heads are over the disk recording area.
Cover Open. When set, indicates cartridge access cover open or cartridge dust cover is not in
place.
Head Select. Indicates currently selected head. When set, indicates lower head; when
cleared. indicates upper head.

BUS Y D07

(VC)

Drive Select Error. When set, indicates multiple drives responding to one address.
Volume Check. When set, indicates a new cartridge may have been mounted since the last

BUS Y D02

(WGE)

time the drive was selected.
Write Gate Error. When set. indicates that during RL02 write data mode, drive not ready to

BUS Y D03

(SPE)

BUS Y D04

(SKTO)

BUS Y DOS

(WL)

Write Lock. When set, indicates write protect condition selected by disk drive WRITE
PROT switch.
‘

BUS Y D06

(CHE)

BUS Y b07

Current in Head Error. When set, indicates write current detected in read/write heads when
disk drive is not in write data mode.

(WDE)

vi-¢

BUS Y D00
BUS Y DOI

(DSE)

read/write, drive write protected, sector pulse occurred, and/or drive was reporting an error.
Spin Error. When set, indicates spindle speed not reached within required time or spindle
speed is too high.
Seek Time Out. When set, indicates read/write heads not located over specified cylinder
within required time during seek state or read/write signal lost when disk drive was in lockon state.

Write Data Error. When set, indicates disk drive in write data mode, but no write data is

asserted within the required time.

* - Not used as part of RL02 status information.

Figure 2-11

RLO2 Status Information Data

Format and Bit Significance

(HO)
(CO)

—_

BUS Y DOI
BUS Y D02

Bit Significance*

BUS Y D00

_————_—0

Data Format
(BUS Y Data Bits)

State

Load Cartridge
Spin-Up
Brush Cycle

Load Heads
Seek
Lock-On
Unload Heads

Spin-Down

Data Format

(BUS Y Data Bits)
BUS Y D00

(SECO)

Sector Count. These bits specify the sector address over which the R80 read/write heads
were located when the status information was output from the R80 disk drive to the IDC.

BUS Y DOl
BUS Y D02

(SEC1)
(SEC2)

BUS Y D035
BUS Y D06
BUS Y D07

BUSY DOO\

(FLT)

BUS Y DOl

(PLGY)

Fault. When set, indicates dc power fault, head select fault, write fault, write or read while
off cylinder, or write attempted during read function.
Plug Valid. When'set, indicates a logic plug installed in the R80 disk drive operation control

BUS Y D02

(SKE)

Seek Error. When set, indicates R80 unable to complete seek within 500 microseconds,

BUS Y D03
BUS Y D04

S1-¢

Bit Significance*

BUS Y D03

BUS Y D04 ‘

(SEC3)
(SEC4)

read/write heads outside recording area, or illegal address detected.

On Cylinder. When set, indicates disk drive read/write heads are located over a cylinder.

»BYTE 2 (ONCY)

Drive Ready. When set, indicates disk drive is up to speed, read/write heads are loaded, and

(DRDY)

BUS Y D05

(WTP)

BUS Y D06

BUS Y D07 /

panel.

no fault exists in disk drive.

Write Protect. When set, indicates R80 is in write protect mode (write protect mode selected

using WRITE PROT switch on R80 disk drive).

* _ Not used as part of R80 status information.
Figure 2-12

R80 Status Information Data Format
and Bit Significance

2.2.5

Port Microinstruction Inputs

2.2.6

PORT INSTR Input

The port microinstruction inputs to the IDC are used to preset the IDC logic and to cause the transfer
of data and information between the IDC and the CPU. The port microinstructions reside in the writable control store (WCS) module in the CPU. The CSR17 and CSR14:10 signal lines contain the port
microinstruction applicable to the IDC. The format and bit significance of the port microinstruction
inputs are shown in Figure 2-13. Table 2-1 lists the port microinstruction functions.
The CPU outputs a PORT INSTR signal to indicate that a valid port command is being applied on the
CSR signal lines. The PORT INSTR signal and the port command remain active for an entire CPU
microcycle (270 nanoseconds). A high PORT INSTR input with CSR17 of the port microinstruction
set to a high (CSR17 high indicates that the port microinstruction is IDC specific) enables the IDC to
decode the port microinstruction input and to preset the IDC logic, or to cause data transfers between
the CPU and the IDC.

2.2.7

READ PORT and SEL ACC IN Inputs

2.2.8

CPU P2 and PORT CLOCK Inputs

The READ PORT and SEL ACC IN signals are used to cause the transfer of information and data
from the IDC or FPA to the CPU. The SEL ACC IN signal indicates if the READ PORT input is IDC
or FPA specific. (If SEL ACC IN is low, READ PORT is IDC specific.)
The CPU P2 and PORT CLOCK inputs provide the basic timing pulses for synchronizing the IDC
operation with CPU operation. The PORT CLOCK input is the basic 90-nanosecond CPU clock. The
CPU P2 input is the gated CPU clock phase 2 output of the CPU. The CPU P2 signal is normally high
during the last 90 nanoseconds of the 270-nanosecond CPU microcycle. Figure 2-14 shows the timing
relationship of the PORT CLOCK and CPU P2 inputs relative to the CPU microcycle.
2.3

IDC/R80 INTERFACE

The interface signals at the IDC/R80 interface are shown in Figure 2-1. The IDC/R80 interface signals input to the R80 disk drive from the IDC include R80 TAG 3:1, R80 TAG BUS 9:0, ACLO
(POWER SEQUENCE PICK), GND (POWER SEQUENCE HOLD), R80 WRITE CLOCK, R80
WRITE DATA, and R80 INITIALIZE. The IDC/R80 interface signals output from the R80 disk
drive to the IDC include R80 SECTOR COUNT 1, 2, 4, 8, and 16, R80 FAULT, R80 PLUG VALID,
R80 SEEK ERROR, R80 ON CYLINDER, R80 DRIVE READY, R80 WRITE PROTECT, R80
SELECT ADRS 1 and 2, R80 INDEX PULSE, R80 SECTOR PULSE, R80 SERVO CLOCK, R80
READ CLOCK, and R80 READ DATA. All of the signals at the IDC/R80 interface are discussed in
detail in Paragraphs 2.3.1 through 2.3.8.

2.3.1

RS80 TAG 3:1 and R80 TAG BUS 9:0

The R80 TAG 3:1 and R80 TAG BUS 9:0 signal lines are used to transmit disk drive control signals
from the IDC to the R80 disk drive. These signal lines are used to position the read/write heads over
the desired cylinder, to select one of the fourteen read/write heads, and to initiate a disk drive read,
write, or recalibrate function.

The R80 TAG 3:1 inputs to the R80 disk drive are used to identify the parallel inputs applied via the
R80 TAG BUS 9:0 inputs (see Table 2-2). When the R80 TAG 1 signal is asserted, it identifies to the
R80 disk drive that the R80 TAG BUS 9:0 inputs contain a binary-coded cylinder address and initiates
the R80 disk drive seek function (repositions the R80 read/write heads over the cylinder having the
address specified by the R80 TAG BUS 9:0 inputs).

When the R80 TAG 2 signal is asserted, it identifies to the R80 disk drive that the R80 TAG BUS 4.0
inputs contain binary coded R80 read/write head selection information and initiates selection of one of
the fourteen read/write heads based on the state of the R80 TAG BUS 4:0 inputs.

2-16

Port Microinstruction
Bits

CSR 17
CSR 14

Bit Significance

Port Device Select. This bit contains the address of the port device for which the port microinstruction is

intended. The address for the IDC is CSR 17=1.
Command Identity. These bits specify the function of the command bits (CSR12:CSR10): read (transfer
information or data from IDC to CPU), write (transfer information or data from CPU to IDC), or control
(preset the IDC logic). These bits are encoded as follows:

L1-C

CSR 13

CSR 12
CSR 11
CSR 10

CSR 14

CSR 13

Function

0
0
|

0
1
0

Read
Write
Control

Command Bits. These bits enable the IDC data paths that cause the transfer of information
or data between the IDC and CPU, or preset the IDC logic. The command bits are decoded in
the IDC to initiate the function(s) specified in Table 2-1.

Figure 2-13

Port Microinstructions Format
and Bit Significance

Table 2-1 Port Microinstruction Functions

Command
Identity
(See CSR 13:14)

Function
Decode

Write

WRITE CSR

Load IDC control word
(Figure 2-2) from the CPU
into the IDC.

Write

WRITE DAR

Load one of the following
disk drive control words
from the CPU into the IDC:
RLO2 get status command
(Figure 2-3), RLO2 seek
command
(Figure
2-4),
RL02 read/write data address (Figure 2-8), R80 seek
command (Figure 2-5), R80
head select command (Figure 2-6), R80 recalibrate
command (Figure 2-7), or
R80 read/write data address (Figure 2-9).

Write

WRITE DATA
BYTE

Load one data byte (BUS Y
bits DOO through D07) from
the CPU into the IDC.

Write

WRITE DATA
WORD

Load one data word (BUS
Y bits D00 through D31)
from the CPU into the IDC.

Read

READ CSR

Output to CPU the IDC status word (Figure 2-10).

Read

READ DAR

Output to CPU the current
RL02 read/write data address (Figure 2-8) or the

Function Description

current
R80
read/write
data address (Figure 2-9).

Read

READ DATA
BYTE

2-18

Output to CPU one data
byte (BUS Y bits D00
through D07) from IDC to
CPU. Usually two successive read data byte commands are used to output to
the CPU the RLO2 status
information or the R80 status information (Figure 2-11
or 2-12, respectively).

Table 2-1 Port Microinstruction Functions (Cont)

Command
Identity
(See CSR 13:14)

CSR
12

CSR
11

CSR
10

Read

Function
Decode

READ DATA

WORD

Function Description

Output to CPU one data
word (BUS Y bits D00
through D31).

Read

READ PATTERN

Output to CPU a 13-bit
word (BUS Y bits D00
through D12) that contains
the 11-bit data burst in
which a read error occurred.

Read

READ POSITION

Output to CPU a 13-bit
word (BUS Y bits D00
through D12) that contains
the address of the first bit of
the data burst within which
a read error occurred.

Control

CLEAR FIFO
CNTR

Resets the counter that controls sequential loading and
unloading of data from the
IDC data buffers.

Control

RESET BR

Resets the UBUS BRS interrupt request output of the

IDC.

Control

CLEAR IDC

Presets the IDC and R80
disk drive. This function is
also initiated by the ACLO
input.

Control

SET AUTOMODE

Presets the conditions that
allow successive data words
to be gated to the CPU
without issuing a READ
DATA WORD port microinstruction for each data
longword to be gated. However, a READ PORT signal
is required for gating each
data longword to the CPU.

Control

CLEAR
AUTOMODE

2-19

Deselects

function.

the automode

Port Microinstruction Functions (Cont)

Table 2-1
Command

Function

Identity

CSR

Decode

Control

SELECT FIFO A

(See CSR 13:14)

‘

CPU P2 H

Figure 2-14

Selects one of the two IDC

data buffers to be used in
the transfer of data between
the IDC and the CPU

CPU MICROCYCLE

(270 nsec)

Selects one of the two IDC

data buffers to be used in

SELECT FIFO B

CPU MICROCYCLE

Function Description

the transfer of data between
the IDC and the CPU.

Control

(270 nsec)

Timing Relationship of PORT CLOCK and
CPU P2 Inputs to IDC

Table 2-2

R80 TAG Bus Bit Decoding

RSO TAG 1
Asserted

R80 TAG 2
Asserted

RS0

Cylinder

Address
(Binary Coded)

Read,/Write

Head Select
(Binary Coded)

Control
Select*

0
1
2
3
4
5
6

1
2
4
8
16
32
64

|
2
4
8
Not used
Not used
Not used

Write gate
Read gate
Not used
Not used
Not used
Not used
Recalibrate

7
8
9

128
256
512

Not used
Not used
Not used

TAG
Bus Bit

Only one of the ten TAG bus bits may be asserted at a time when R80 TAG 3 is asserted.

2-20

RS8O TAG 3
Asserted

When the R80 TAG 3 signal is asserted, it identifies to the R80 disk drive that the TAG BUS 9:0
inputs specify a control select signal. The control select signals input to the R80 disk from the IDC
include the R80 recalibrate write gate and read gate commands. Assertion of the R80 TAG 3 and R80
TAG BUS 6 inputs initiates the R80 recalibrate function (positions the R80 read/write heads over the
cylinder having the address of 0). Assertion of the R80 TAG 3 and R80 TAG BUS 0 inputs enables the
R80 write gate function. Assertion of the R80 TAG 3 and R80 TAG BUS 1 inputs enables the R80
read gate function.

2.3.2 ACLO, GND, and R80 INITIALIZE
The ACLO (POWER SEQUENCE PICK) input to the R80 disk drive is low when the VAX-11/730
system is operating normally. However, when the VAX-11/730 system experiences a low ac line level condition, the ACLO input to the IDC is asserted. The ACLO input is buffered by the IDC and asserted to the
R80 disk drive as a high ACLO (POWER SEQUENCE PICK) signal. A high POWER SEQUENCE
PICK signal input to the R80 disk drive causes the disk drive to spin down and inhibits any read/write
operations. The POWER SEQUENCE HOLD input to the R80 disk drive is used to inhibit spinup of the
drive while another R80 disk drive is in the spinup state. Since only one R80 disk drive is connected to the
IDC, the POWER SEQUENCE HOLD input is clamped at ground in the IDC.

The R80 INITIALIZE input to the R80 disk drive is initiated by the IDC either in response to a
CLEAR IDC port microinstruction input from the CPU or in response to the DCLO input during initial powerup or powerup following an input power interruption to the VAX-11/730. The R80 INITIALIZE input to the R80 disk drive causes the read/write heads to be deselected and to be positioned over cylinder O.

2.3.3

R80 WRITE DATA and R80 WRITE CLOCK

The R80 WRITE DATA input to the R80 disk drive
is used to apply serially the data to be written on
the disk. The R80 WRITE CLOCK signal is generated by the IDC from the R80 SERVO CLOCK
input to the IDC. The R80 WRITE CLOCK signal strobes each data bit applied via the R80 WRITE
DATA input into the R80 disk drive.
The R80 WRITE DATA applied to the disk drive is in the format illustrated in Figure 2-15. Figure 215 also shows the timing relationship of the R80 WRITE DATA and R80 WRITE CLOCK outputs
from the IDC during the transfer of one sector of data from the IDC to the R80 disk drive.
2.3.4 R80 SECTOR COUNT 1, 2, 4, 8, and 16
The R80 SECTOR COUNT 1, 2, 4, 8, and 16 inputs to the IDC from the R80 disk drive provide

binary coded sector address 1nformat10n The SECTOR COUNT inputs identify the correct sector

from the 32 sectors of the-selected cylinder over which the read/write heads are located. The SECTOR

COUNT inputs change state at the leading edge of each R80 SECTOR or R80 INDEX PULSE. The
SECTOR COUNT inputs to the IDC are reset to zero by the R80 INDEX PULSE and incremented
by each R80 SECTOR PULSE.

2.3.5

R80 FAULT, R80 PLUG VALID, R80 SEEK ERROR, R80 ON CYLINDER, R80 DRIVE

READY, and R80 WRITE PROTECT

These signal inputs to the IDC are used to indicate the operational or fault status of the R80 disk drive. The
significance of each signal is detailed in Figure 2-12, which illustrates and discusses the makeup and bit
significance of the R80 status information transferred to the CPU. The R80 FAULT, R80 PLUG VALID,
R80 ON CYLINDER, and R80 DRIVE READY inputs to the IDC from the R80 disk drive are used to
specify to the IDC any changes in R80 disk drive status (that the operational function requested of the disk
drive was completed successfully or that a fault condition has developed).
2.3.6 R80 SELECT ADDRESS 1 and 2
These signal lines specify to the IDC the binary-coded unit number of the disk drive. This number is
selectable by selection of the logic plug installed on the R80 operator panel.

2-21

ONE SECTOR OF R80 WRITE DATA:

IDC TO R80 DISK DRIVE

{4288 BIT CHARACTER STRING)
A
—

DATA

HEADER GAP

)
L4y

DATA BURST

612 BYTESHOF DATA

)
L ¢

[ _[ 15 BYTES\&)F ZEROS lSYNC BYTEI
LY

ECC

)L
LA

GAP

——A
RS

4 BYTE‘S ECC

[ 2 BYTES ’CiF ZEROS J

L{}

L (o

——eete - TIME

(a4t

—-I lo—- 103.5 nsec

[
I
N
I
PPt

RBOWRITEDATA |

{NRZ FORMAT)

[

||
|
|
100011001
R B A
Ll|

{

I IT

BIT1I||!II|III|||IIIII||

INTERVAL IN WHICH

EACH DATA BIT IS —-I =
WRITE DATA OUTPUT

APPLIED TO R80
OF IDC

BT 136|
oI

BIT 1aa||
BIT OF
FIRST

DATA FROM IDC
DATA BUFFER)

: BIT 4241
BIT OF
(LasT

144

BIT 4272
B|T|4273

1{ g

BIT 4288

DATA FROM

10C DATA BUFFER)
TK-738%

Figure 2-15 R80 Write Data Format and Data
Transfer Timing: IDC to R80

2.3.7 R80 INDEX PULSE and R80 SECTOR PULSE
|
The R80 INDEX PULSE and R80 SECTOR PULSE inputs to the IDC are used to indicate the beginning of each sector of the R80 cylinder track. The R80 INDEX PULSE occurs once per R80 cylinder

revolution with the leading edge of the pulse indicating the beginning of sector 0. An R80 SECTOR
PULSE marks the beginning of each of the remaining 31 sectors for each R80 cylinder revolution.
Figure 2-16 shows the timing relationship of the R80 SECTOR and R80 INDEX PULSES.

—ol

I-—2.5 usec

R80 INDEX PULSE y

ISy

(

—-l

R80 SECTOR PULSE ’I

[

|-—2.5 usec

)

(

)

(

|-—520 usec*—vl

)
L

)) %

I
|

Il'—SECTOR 32-——’:‘——SECTOR 0——':"——SECTOR 1—t*—SECTOR 2
[

* BASED ON A DISK ROTATIONAL

RATE OF 3600 RPM.
TK-7363

Figure 2-16

R80 Sector Pulse and Index Pulse Timing

2.3.8 R80 READ DATA and R80 READ CLOCK
The R80 READ DATA output is used to apply to the IDC the data read from the disk. The R80
READ CLOCK output is synchronized with the R80 READ DATA output to provide a timing pulse
that defines the beginning of each interval in which each bit of the read data is applied.
The R80 READ DATA applied to the IDC is in the format illustrated in Figure 2-17. Figure 2-17 also
shows the timing relationship of the R80 READ DATA and R80 READ CLOCK outputs of the R80
disk drive.
2.4

IDC/RLO2 INTERFACE

The signals at the IDC/RLO02 interface are shown in Figure 2-1. The IDC/RLO02 interface signals input
to the RL02 disk drive include RL DRIVE COMMAND, RL DRIVE DATA, and RL SYSTEM
CLOCK. The IDC/RLO2 interface signals output from the RLO2 disk drive include RL DRIVE ERROR, RL DRIVE READY, RL STATUS, RL STATUS CLOCK, RL SECTOR PULSE and RL
READ DATA. All of the signals at the IDC/RL02 interface are discussed in Paragraphs 2.4.1 through
2.4.9.

2.4.1 RL DRIVE COMMAND and RL SYSTEM CLOCK
The RL DRIVE COMMAND signal line is used to transfer serially a RLO2 get status command or a
RLO2 cylinder difference word from the IDC to the RL0O2 disk drive. The RLO2 get status command
initiates the transfer of RLO2 status data from the RLO2 to the IDC. The RLO2 cylinder difference
word specifies to the RLO02 the data required to reposition the read /write heads over the desired cylinder and selects the read/write head to be used. The RLO2 get status command and RL0O2 cylinder
difference word inputs are in a 16-bit serial data format and are transferred to the RL0O2 by the RL
SYSTEM CLOCK. The RL SYSTEM CLOCK, a 4.1 megahertz clock signal generated by the IDC,
transfers the RLO2 cylinder difference word to the RLO2 at a rate of 243.9 nanoseconds per bit. The
RL SYSTEM CLOCK signal input to the RLO2 disk drive is used also to synchronize the operation of
the RL02 disk drive with the IDC.

2-23

ONE SECTOR OF R80 READ DATA:
{5360 BIT CHARACTER STRING)

R80 TO IDC

HEADER

DATA FIELD

CYLINDER SECTOR

SECTOR GAP

ADDRESS ADDRESS
N ——\

ral 4
Pav

CRC

WORD

HEADER GAP
-

DATA BURST
KA

ECC
Y

2 BYTES OF ZEROS

|59 BYTES (UNDEFINED)

———-—————-.ITIME

ve-C

DATA GAP

28 BYTEQF ZEROS gyNc BYTE|2 BYTES| 2 BYTES|2 BYTES| 17 BYTES‘}‘?F ZEROS | SYNC BYTE | 512 BYTES OF DATA |4 BYTES ECC|
17

—=|

|e-103.3 nsec

R80 READ CLOCK

R80 READ DATA f~

(NRZ FORMAT}

oloftol1titotoltl

TK-7370

Figure 2-17

R80 Read Data Format and Data Transfer
Timing: R80 to IDC

The structure and bit significance of the get status and cylinder difference word inputs to the RL02

disk drive are discussed in Figures 2-3 and 2-4, respectively. The data words shown in Figures 2-3 and 24 are serialized in the IDC and applied to the RLO2 disk drive via the RL DRIVE COMMAND signal
line. The bit identified as DOO in Figures 2-3 and 2-4 corresponds to the first bit of the 16 bits transferred to the RLO2.
2.4.2

RL DRIVE SELECT 0 and 1

The RL DRIVE SELECT 0 and 1 inputs enable selection of one of the four RL02 disk drives that may
be connected to the IDC. The RL DRIVE SELECT 0 and 1 inputs to the RLO2 disk drives are generated by the IDC in response to the Drive Select bits of the IDC control word (Figure 2-2) input to the

IDC from the CPU. Assertion of the Drive Select bits enables the selected drive to generate/respond to
the signals at the IDC/RLO2 interface.
2.4.3

POWER FAIL (ACLO)

This signal input to the RLO2 disk drives is asserted low whenever a low line level or loss of the primary
facility power input is detected. Assertion of the POWER FAIL signal ‘causes all of the RL02 disk

drives connected to the IDC to cycle down. When the POWER FAIL signal is deasserted (returns to a
high), the RLO2 disk drives spin up and the read /write heads are loaded and positioned over cylinder 0.
2.44
RL WRITE GATE and RL WRITE DATA
The RL WRITE GATE signal enables the write circuits in the selected RLO02 disk drive. The data to
be written on the selected RLO2 disk are applied in a serial format via the RL WRITE DATA signal
line. The data to be written are encoded in Modified Frequency Modulation (MFM) form. The RL
WRITE DATA applied to the RL02 disk drive are in the format shown in Figure 2-18. Figure 2-18 also

illustrates the timing relationship of the RL WRITE DATA and RL WRITE GATE outputs of the
IDC during the transfer of one sector of data from the IDC to the RLO0O2 disk drive.

ONE SECTOR OF WRITE DATA TO RL0O2 DISK DRIVE

(2128 BIT CHARACTER STRING)
N

)

DATA PREAMBLE
-

DATA BURST

—\r

CRC

DATA POSTAMBLE

{ C

({ C

[5 BYTES OF ZEROS (SYNC BYTE| 256 BYTES OF DATA ]2 BYTESJ 2 BYTES OF ZEROS
— TIME

|
I

_.|

MFM ENCODED

INTERVAL

I._243.9 nsec
0

RL WRITE GATE ASSERTED

=0 TO 256 nsec‘.‘ "—BEFORE DATA PREAMBLE

INTERVAL

= 0 TO 256 nsec

RL WRITE GATE__|

-l

RL WRITE GATE
DEASSERTED AFTER

DATA POSTAMBLE

|
TK-7366

Figure 2-18
RL Write Data Format and Data
Transfer Timing: IDC to RL02

2-25

2.4.5

RL DRIVE READY

The RL DRIVE READY input to the IDC is asserted high to indicate that the disk drive has successfully executed the previously asserted drive command (the read/write heads are located over the desired cylinder and loaded) and is ready to receive further drive commands or to write or read data to or
from the disk. The RL DRIVE READY signal is deasserted after receiving a RL DRIVE command. on
detection of an operational error within the disk drive, or when RL WRITE GATE is asserted (when
data are being written on the disk).
2.4.6

RL DRIVE ERROR

The RL DRIVE ERROR input to the IDCis asserted high to mdlcate that the selected RLO2 disk
drive has developed an error condition. When the RL DRIVE ERROR output of the RL02 disk driveis
asserted, the DRIVE READY output is deasserted. The type of error causing the assertion of RL
DRIVE ERROR may be determined by examining the RL STATUS output of the applicable RL02
disk drive (Paragraph 2.4.7).

2.4.7 RL STATUS and RL STATUS CLOCK
The RL STATUS and RL STATUS CLOCK outputs of the RL02 disk drive are enabled by asserting

an RLO2 get status command to the disk drive via the RL drive command signal line. On receipt of the

get status command, the selected disk drive transfers serially 16 bits of status information to the IDC
via the RL STATUS signal lines. The format and bit encoding of the 16-bit RL status word input to the
IDC are illustrated in Figure 2-19. The significance of each bit is as specified in Figure 2-11. The RL
STATUS CLOCK output of the disk drive is derived from the 4.1 megahertz RL SYSTEM CLOCK
input to the disk drive. The RL STATUS CLOCK output of the disk drive (a 4.1 megahertz clock) is
asserted to the IDC in synchronization with each bit of the status information. The RL STATUS
CLOCK output remains enabled until a new RL drive command is asserted or the disk drive is deselected.
:
2.48

RL SECTOR PULSE

2.49

RL READ DATA

The RL SECTOR PULSE signal input to the IDC is used to indicate the beginning of each of the 40
sectors of each RL02 cylinder track. The selected RL02 disk drive asserts a high 45 4+ 10 microsecond
pulse once every 625 microseconds. The leading edge of the pulse indicates the beginning of a sector.

The data recorded on the disk are applied serially to the IDC via the RL READ DATA signal line.
This signal line applies the recorded data to the IDC whenever the disk drive is selected (Paragraph
2.4.2) and the disk drive asserting a high RL DRIVE READY output (the drive is not performing a
seek function, and does not have a detected error). The read data transferred via the RL READ DATA
signal line are encoded in MFM form as shown in Figure 2-20. The data are transferred from the RLO02
to the IDC at a 4.1 megahertz rate (243.9 nanoseconds per bit).

—_— TIME

LSB

BIT NO.

MSB

STA

|stB|stc|

| HO

| cO

| HS

| —

STATE

|DSE | VC

| WGE | SPE

|SKTO|

WL | CHE | WDE

WRITE

BRUSH

COVER

VOLUME

SPIN

WRITE

DATA

HOME

OPEN

CHECK

ERROR

LOCK

ERROR

HEADS
ouT

HEAD
SELECT

DRIVE
SELECT

WRITE
GATE

SEEK
TIME

CURRENT
IN HEAD

ERROR

ouT

ERROR
TK-7358

Figure 2-19

Format and Bit Significance of RL02

Status Information Transfer: RL02 to IDC
2-26

ONE SECTOR OF READ DATA FROM RLOZ DISK TO 1DC
{2240 BIT CHARACTER STRING)
P

DATA FIELD

HEADER
ADDRESS

(SECTOR

HEADER PREAMBLE

——

HEADER

CYLINDER)}

v A

CRC

— v

DATA

HEADER

POSTAMBLE

PREAMBLE

DATA BURST

DATA

CRC

POSTAMBLE

]

—
e
———
e e

—_——

Y um e

(
ZEROS ISYNC BYTE] 256 BYTE)S‘ OF DATA lZ BYTESJ 2 BYTES OF ZEROil
ZEROS | SYNC BYTE |2 BYTES] 2 BYTES OF ZEROS l? BYTESl 2 BYTES OF ZEROS 5 BYTES’?F
F BYT!i(;F
[£¢
L4

[41

)

(44

L.__._______._.._____}

'l 0 l' 0 pogpor ooty
i
MFM ENCODED
ENCODED ___ __ __ _ : __ __
MEM
nsec

({

TIME
—

—

TK-7384

Figure 2-20 RL Read Data Format and Data
Transfer Timing: RLO2 to IDC

CHAPTER 3
THEORY OF OPERATION

3.1
IDC FUNCTIONS
The IDC and associated disk drive(s) make up the RB730 disk subsystem. The IDC interfaces
the
VAX-11/730 CPU with up to four RL02 disk drives or one R80 disk drive and up to three RLO2
disk
drives. The IDC executes the functions specified by the CPU to cause storage and retrieval
of data
from the disk drives of the RB730 disk subsystem. Table 3-1 lists the functions that can be
specified
with the IDC control words and describes the purpose of each function. It also lists the required
inputs
(disk drive control words, address information, and data) for each function.

Table 3-1
Function Specified by
IDC Control Word
from CPU*

Required Inputs
from CPU*

Seek (RL02)

RLO2 Seek Command

Seek (R80)

R80 Seek Command

Seek (R80)
'

IDC Functions

Purpose

Controls positioning of the selected
RLO2 disk drive read/write heads
over the desired cylinder track and
enables
the desired read/write
head.

Controls positioning of the R80 disk
drive read/write heads over the desired cylinder.

R80 Head Select Command

Enables

one

the

fourteen

read/write heads in the R80 disk
drive.

Seek (R80)

R80 Recalibrate Command

Controls positioning of the R80
read /write heads over cylinder 0.

Get Status (for RL02)

RL02 Get Status Command

Controls gating the status information from the selected RLO2 disk
drive and storing it in the IDC data
buffer.

Get Status (For R80)

None. (Information for selecting
R80 status information is contained in IDC control word.)

Controls gating the status information from the R80 disk drive and
storing the status information in the
IDC data buffer.

The format and bit significance of the IDC control word and the specified required inputs to the IDC are discussed in Chapter 2.

3-1

Table 3-1
Function Specified by
IDC Control Word
from CPU*
Read Header

IDC Functions (Cont)

Required Inputs
from CPU*

Purpose

None. (Information for selecting
disk drive from which header is to
be read is contained in IDC control word.)

Write Data

fer.

Read/Write Data Address.

(CPU must load IDC data buffer

with data to be written)

Read Data

Controls reading from the selected
disk drive the header information
from the first sector encountered
and storing it in the IDC data buf-

Controls writing of the data contain| ed in the IDC data buffer at the
w-specified read/ write data address
\”iéf ‘the selected disk drive.

Read/Write Data Address

"Controls reading from the selected

disk drive the data from the specified read/write data address and
storing of the data in the IDC data
buffer.

Read Data Without
Header Check

‘None. (Information for selecting
disk drive from which data are to
be re trieved is specified as part of
the IDC control word.)

Controls reading from the selected
disk drive the data from the first
sector encountered and storing the
data in the IDC data buffer.

Write Check

Read/Write Data Address.
(CPU must load IDC data buffer
with comparison data.)

Controls reading from the selected
disk drive the data from the specified read/write data address and
comparison of data read from memory with data contained in the data
buffers.

Write Format
(Used only with R80

Header Data. Performed after
read /write heads of the selected
disk drive have been positioned
over the cylinder (CPU must load
IDC data buffer with the header
information for all 32 sectors of
the cylinder.)

Controls writing of new header data
from the IDC data buffer into each
of the 32 sectors of the applicable
R80 cylinder.

Maintenance

As specified in microdiagnostic

Places the IDC in the maintenance
mode such that the IDC logic may
be exercised by microdiagnostic:
routines designed to detect faults or
verify operational status of the IDC
hardware.

disk drive)

routines.

* The f(;rmat and bit significance of the IDC control word and the specified required inputs to the IDC are discussed in Chapter 2.
3-2

3.2
OVERALL IDC OPERATION
|
The IDC operates under CPU control. The CPU loads the required inputs (disk drive control
word,
address information, and/or data) and IDC control word needed to initiate each function
of the IDC.
Once an IDC function is initiated (when the 1DC control word is loaded), the IDC operation is controlled by a microcontroller on the IDC. After the function has been completed or an error is detected,
the IDC gencrates and asserts an interrupt signal to the CPU. The CPU then takes control of the IDC
operation to transfer the desired information or data from the IDC to the CPU, or to load the IDC with
the required input(s) and IDC control word needed to initiate another IDC function. When the IDC is

not performing a function specified by the CPU, it operates in the idle mode. In this mode, the operation of the IDC is controlled by the microcontroller, which samples the operational status of the disk
drive(s) and generates and asserts an interrupt to the CPU if an operational status change is detected.
3.2.1

Initiating IDC Functions
Each of the IDC functions listed in Table 3-1 is initiated under CPU control. The required inputs and
IDC control word nceded to initiate each IDC function are asserted to the IDC via the CPU Y BUS
and arc loaded into the IDC by the port microinstructions asserted to the IDC. The IDC decodes the

port microinstructions and gencrates the control signals used to preset the IDC logic or to load the IDC
registers and data buffers.

3.2.1.1
a.

Loading Required Inputs
Disk Drive Control Word and Address Information — The required disk drive control word
(RLO2 seek command, RLO2 get status command, R80 seck command, R80 head select com-

mand, or R80 recalibrate command) or address information (RLO2 read/write address or
R80 read/write address) is loaded into the IDC by asserting the applicable disk drive control

word or address information to the IDC via the CPU Y BUS and simultaneously asserting a

WRITE DAR port microinstruction (sce Table 2-1) and a PORT INSTR input to the IDC.
(A detailed discussion of how the disk drive control word and address information are loaded

into the IDC is provided in Paragraph 3.5.13.3.)

Data — The required data input to the IDC is loaded into one of the two data buffers. Each
data buffer has the capacity to store one full sector of data (512 bytes of R80 data or 256

bytes of RLO2 data). When data are a required input, the CPU must load a full sector of
data. If a partial sector is to be loaded, the CPU must load the rest of the sector with zeros.

The data to be loaded into the data buffer(s) may be in either byte or longword format.

Before the required data are loaded into the IDC, the CPU must assert a FIFO SEL port
microinstruction (see Table 2-1) to select the data buffer to which the data are to be loaded.
The CPU causes loading of each data byte or data longword into the selected data buffer by
asserting

the correct WRITE DATA BYTE or WRITE DATA WORD port microinstruction (see Table 2-1) and PORT INSTR input signal to the IDC and simultaneously

asserting the data byte or data longword to be loaded via the CPU Y BUS. (A detailed discussion of how the data are loaded into the IDC is provided in Paragraph 3.5.13.6.)
3.2.1.2

Loading the IDC Control Word - The IDC control word is loaded into the IDC by asserting
the IDC control word onto the CPU Y BUS and simultaneously asserting a WRITE CSR port micro-

instruction (sce Table 2-1) and PORT INSTR input signal to the IDC. (A detailed discussion of how
the I1DC control word is loaded into the IDC is provided in Paragraph 3.5.13.1.)

3.2.2

IDC Operation

Each of the IDC functions listed in Table 3-1 is initiated when the CPU loads the applicable IDC control word into the IDC. The IDC control word input specifies the function to be executed, the address
of the disk drive to be used, and whether an interrupt is to be generated at the completion of the specified function. If the R80 disk drive is to be used, the IDC control word also indicates if skip sectoring is
to be enabled.

When the IDC control word is loaded into the IDC, the address bits are used to enable the appropriate
RLO2 disk drive (if an RLO2 disk drive is specified) and to condition the IDC for operation with an
RLO?2 or the R80 disk drive. The function bits of the IDC control word indicate to the IDC the function
to be performed and are used to preset the IDC microcontroller. The operational sequence performed
by the IDC is initiated by the CRDY bit of the IDC control word. (A detailed discussion of IDC operation during each function is presented in Paragraph 3.4.)

After the IDC has completed the function specified by the IDC control word, the IDC generates and
asserts the applicable interrupt to the CPU. Then, if applicable, the IDC enters the idle mode of operation.

After the IDC has asserted the proper interrupt to the CPU, the CPU may specify another IDC function or, if data or information was requested by the previously specified IDC function, assert the applicable port microinstructions to transfer the requested information or data from the IDC to the CPU.
3.2.3

Transfer of Information and Data from IDC to CPU

The transfer of information (IDC status information, disk drive information, CRC/ECC error detection information, and current address information) and data from the IDC to the CPU is controlled by
the CPU. To transfer information and data from the IDC to the CPU requires that the CPU assert the
proper port microinstruction input(s) followed during a later CPU microcycle by a READ PORT signal. The IDC decodes the port microinstruction input(s) and generates the enable signals that make
available to the CPU the requested information or data. The following READ PORT signal is used to
enable the requested information or data to be asserted to the CPU via the CPU Y BUS.
3.2.3.1 IDC Status Information Transfer (IDC to CPU) - The CPU causes transfer of the IDC status
word (Figure 2-10) from the IDC to the CPU by asserting a READ CSR port microinstruction (see
Table 2-1), followed during a later CPU microcycle by a READ PORT signal. The IDC decodes the
port microinstruction and generates the control signals required to make the IDC status word available
for transfer to the CPU. The READ PORT input to the IDC port control logic is used to assert the IDC
status word to the CPU via the CPU Y BUS. (A detailed discussion of how the IDC status information
:
is transferred from the IDC to the CPU is provided in Paragraph 3.5.13.2.)
3.2.3.2 Disk Drive Status Information Transfer (IDC to CPU) - The two bytes of disk drive status
information (Figure 2-11, RL02; Figure 2-12, R80) read from the disk drives by the IDC during a get
status function are stored in the IDC data buffer. The CPU causes the transfer of the disk drive status
information by asserting two READ DATA BYTE port microinstructions. Following each READ
DATA BYTE port microinstruction, the CPU asserts a READ PORT signal. The IDC decodes each of
the READ DATA BYTE port microinstructions and generates the control signals to cause the transfer
of a single byte of data from the data buffer to the data output register, where it is available for transfer
to the CPU.

Each of the READ PORT inputs to the IDC control logic is used to assert the byte of disk drive status
information to the CPU via the CPU Y BUS. (A detailed discussion of how the disk drive status information is transferred from the IDC to the CPU is provided in Paragraph 3.5.13.7.)

3-4

3.2.3.3

ECC/CRC Error Detection Information Transfer (IDC to CPU) - The CPU causes the transfer of the ECC POSITION or ECC PATTERN from the IDC to the CPU by asserting the applicable
READ POSITION or READ PATTERN port microinstruction (see Table 2-1), followed during a later
CPU microcycle by a READ PORT signal. The IDC port control logic decodes the port microinstruction and generates the control signal required to make the ECC POSITION or ECC PATTERN
information available for transfer to the CPU. The READ PORT input is used to assert the ECC POS-

ITION or ECC PATTERN information to the CPU via the CPU Y BUS. (A detailed discussion of
how the error detection information is transferred from the IDC to the CPU is provided in Paragraph
3.5.13.5))

3.2.3.4

Current Address Information Transfer (IDC to CPU) - The CPU causes the transfer of the
current address information to the CPU by asserting a READ DAR port microinstruction (see Table 21) followed during a later CPU microcycle by a READ PORT signal. The IDC port control logic de-

codes the port microinstruction and generates the control signals required to make the current address
information available for transfer to the CPU. The READ PORT input to the IDC port control logic is
used to assert the current read/write data address to the CPU via the CPU Y BUS. (A detailed discussion of how the current address information is transferred from the IDC to the CPU is provided in
Paragraph 3.5.13.4.)
3.2.3.5 Data Transfer (IDC to CPU) - The CPU controls the transfer of data from the IDC buffers to
the CPU. The data contained in the IDC data buffers may be transferred in either byte or longword
format. The CPU causes the transfer of a data byte or single data longword by asserting a READ
DATA BYTE or READ DATA WORD port microinstruction followed during a later CPU microcycle
by a READ PORT signal. The IDC decodes the port microinstruction and generates the control signals

that make available for transter to the CPU a single data byte or a series of four contiguous data bytes

arranged in a longword format. The READ PORT signal input to the IDC enables the data byte or data
longword to be transferred to the CPU via the CPU Y BUS.

For transferring a series of data longwords, the CPU presets the IDC using an AUTOMODE port mi--

croinstruction, followed by a single READ DATA WORD port microinstruction. Presetting the IDC
with the AUTOMODE and READ DATA WORD port microinstructions allows a series of data long-

words to be transferred with a series of READ PORT signals (each successive READ PORT input

signal causes the transfer of successive data longwords). (A detailed discussion of how the data are
transferred from the IDC to the CPU is provided in Paragraph 3.5.13.7.)

3.3

OVERALL IDC LOGIC FAMILIARIZATION

Figure 3-1 is a block diagram of the IDC. Each block represents a grouping of components having the

operational characteristics identified in that block.

3.3.1

IDC Port Control Logic

The IDC port control logic operates under CPU control. The CPU uses port microinstruction inputs to

get control of the IDC. The port microinstructions are applied to the IDC port control logic via the
CSR17 and CSR14:10 signal lines. When these signal lines contain a valid port device (IDC or FPA)

instruction, the CPU also asserts a high PORT INSTR signal. When the PORT INSTR input is high,
the IDC port control logic decodes the port microinstruction and generates the control signals to preset
the IDC logic, to load the required input(s) or IDC control word into the IDC, or to make information
or data contained in the IDC available for transfer to the CPU.

3-5

3.3.2

Microcontroller

3.3.3

Y-Bus Transceivers

The microcontroller, a combination of conditional addressing logic and associated PROMs, generates
the proper sequence of microwords that control the operation of the IDC in causing the function specified by the IDC control word. Branch condition inputs from the control status register (CSR), data
buffer and data register control logic, header/data comparator, and ECC/CRC logic determine the
sequence of microwords generated by the microcontroller. Timing for the sequence of microwords generated is controlled by the sequence clock output of the clock control.

All control words, address information, error detection information, status information, and data are

transferred between
the CPU and IDC via the Y-bus transceivers. The READ IDC input to the transceivers is used to control the direction of signal flow. The READ IDC input is generated from the
READ PORT input from the CPU. A low READ IDC signal enables the signals at the IDC bus 1/0 to
be asserted on the CPU Y-bus. A high READ IDC input enables the signals on the CPU Y-bus to be
asserted on the IDC bus I/0O.
3.3.4

Disk Address Register

The disk address register is loaded under CPU control with the required disk drive control word or
read /write data address. The read/write data address of the disk address register may be incremented
by the microcontroller to update the read/write data address information as additional contiguous sectors of data are written or read. The contents of the disk address register may be transferred from the
IDC to the CPU under CPU control.
3.3.5

Data Input Register, Data Buffer and Data Register Control Logic, Data Output Register, Read
Data Tristate Drivers, and R80 Multiplexer
The data input register and the data buffer and data register control logic operate under CPU control to
cause loading of the required data inputs into the IDC data buffers. The data output register and the
data buffer and data register control logic operate under CPU control to cause the transfer of the disk
drive status information, header information, or data contained in the data buffers from the IDC to the
CPU. During a write function, the data buffer and data register control logic operates from microcontroller inputs to cause the transfer of data from the data buffers into the data shift register. During a
read function, the data buffer and data register control logic, read data tristate drivers, and R80 multiplexer operate from microcontroller inputs to load the data buffers with the proper header information,
status information, or data from the applicable disk drive.
3.3.6 Control Status Register
The control status register (CSR) is loaded under CPU control with the IDC control word. The CSR
also operates under CPU control to cause the transfer of the IDC status word (the current IDC control
word contained in the CSR and a summary of the current status of the IDC and disk drives) from the
IDC to the CPU.
The CSR asserts the initial branch conditions (FO, F1, and F2) and the start signal (CRDY) to the
microcontroller. The CSR also controls selection of the applicable disk drive and enables the appropriate read data paths of the IDC. Status information from the disk drives and from the IDC header/data
comparator and ECC/CRC logic is asserted to the CSR, which makes this information available to the
CPU in the form of the IDC status word output.

When the function specified by the IDC control word is completed or has been halted due to an error,
the CSR operates from microcontroller inputs to generate and assert the applicable interrupt (UBUS
BRS or PORT XFER REQ) to the CPU.

3-6

RL DRIVE RDY
le— RL DRIVE ERR

¢— R80 SEL ADDRESS
0

l«—R80 SEL ADDRESS 1

RLO2

PORT

XFER
REQ

R80 STATUS
-

PORT XFER REQ

PORT XFER REQ
XFER GR ANT

CONTROL

gsg\f RDY
Fo-

UBUS BR5

T3R80

WRITE

[—RL DRIVE ERROR

R80 COMB SECTOR PLS

SYNCHRONIZER

(512
X 64 PROM)

[*—RL SECTOR PLS

PLS

MICROCONTROLLER

FORWAT

R80 SYNC INDEX PLS

MAINT, ASSI

SECTOR

STATUS

RL DRIVE READY

RL DRIVE ERR @

RL SECTOR PLS
SYNC

DRIVE ERR

ON_LINE

RL DRIVE RDY =

[*+—R80 SECTOR PLS

R8O INDEX PLS

[+—R80 INDEX PLS

R80

INH SSE

BUS 1/0

SSE

| —» DRIVE SEL
O

- DRIVE SEL
1
> RLO2

”

CRC/

MISMATCH

»R80

ECC

le— CRC/ECC ERROR

WRITE/READ REGS

INIT =
L

20
Y

JAM

READ I1DC

DATA

INPUT

DATA BUFFER
(FIFO A)

(512 X 8)

CONSTANTS

SYNC BYTE
<':‘:
8 | TRISTATE <:
8

DRIVERS

DATA
BUFFER

AND
aM—s]

80—s{

(FIFO B)

CONTROL

CHECK

DATA IN

}

ECC POS/PAT

[READ

[ggg

READ DATA

TRISTATE

DRIVERS

R8O

READ

SELECT|

WRITE

POS/

CPU P2
DCLO

RL DRIVE COMMAND

STATUS/

DaTA

GATE

=R80 READ DATA
STATUS

l¢— RL STATUS

RL READ DATA

baTa | DATA
READ

=R READ DATA

SEPARATOR

IQSR 0

DS CLOCK

RL WRITE DATA

DATA IN

]

WRITE DATA
NRZ

4.1 MHz

FORMATTER

DSR 0

NRZ
DATA

BUS

;

CRC/ECC ERROR
<

STAT 0 =

STAT
1

> RL WRITE DATA

MFM
ENCODER

RLO2/R80

4.1 MHz

DRIVERS

WRITE INHIBIT
———

R8O WRITE DATA

AND
RECEIVERS

SYSTEM CLOCK

(4.1 MHz)
[~ R80 WRITE DATA

—

R8O STATUS

ECC/CRC

LOGIC

ECC POS/PAT

R80 SECTOR COUNT

CURRENT SEQUENCE

CLOCK
IDC PORT

RL L DAT Al

CONTROL| paT
|

CONTROL LOGIC

)

¢R80 STATUS
<F%8?SECTOR COUNT

SEL POS/PAT

CLOCK

SYNC

RLO2

SEEN

> INIT
—— PORT CLOCK

P2 CLOCK
—*CPU CLOCK

DS CLOCK

INIT——
RL STATUS CLOCK

INIT =t

[—>P2 CLOCK

PORT CLOCK
ACLO

MUX

SERIAL

SEL ACC IN
8

DISK

SYNC SECTOR PLS

READ PORT

BUS 09:00

(SERIAL DAR)

R80 READ DATA

READ DATA IhATA

DATA

R80 SECTOR COUNT

R80 TAG

RLO2 —

SEEN

]

PORT INSTR

CSR17, CSR14:10

—R80 TAG 2
—» R80 TAG 3

SYNCHRONIZER

MUX

Ripo

—+R80 TAG
1

HEADER/

SERTAL Dan]

R80 STATUS

wRiTe/l |
REGS

SERIAL

), g:ITF/;

LOGIC

WRT

—»FIFO MAX

—+RL DRIVE SELECT 1

RECEIVERS

|READ TAG

RLO2

{512 X 8)

DATA

DRIVERS
AND

SYKIC

8
8

SEEN

" géf\j;lfiARATOR MISMATCH

LOAD

DATA BUFFER
FIFO CONTROLS

8
T

)

AND ADDRESSES

SYNC

ENABLE

—RL DRIVE SELECT 0

SERIAL DAR
SERIAL DAR

INPUT REGS

[<—R80 SEL. ADDRESS 1

RLO2/R80

WRITE TAG

BUS

HD/CY
/CYL TAG

OAR 14:00

o
IN

[+—R80 SEL ADDRESS 0

@—

BUS

REGS

CNTL TAG

READDATA

DRIVE SEL 1—#

TAG

CONTROL

ADDRESS

OUTPUT

ouTPUT

%
S

SERIALIZER [N ODIFIED READ DATA

DATA

LOAD

MISMATCH

SIGNALS)

DAR15, , 01, 01, 00

DAR15:DAR00

TRANSCEIVERS

{CONTROL

SERIAL
DAR
SYNC SEEN

READ REG

m Y BUS

MICROWORD

> JAM

FIFO

OVFLW

ERROR

WRITE INHIBIT

—

ADDRESS

DRIVE SEL 0—

DISK

WRITE/READ REGS|

FIFO

MAX

fe—STAT 0

la—STAT 1

SEL

R8O SEL ADDRESS 14—

R80 READ CLOCK

CLOCK CONTROL

R80 SERVO CLOCK

—»R80 INITIALIZE

[*—RL STATUS CLOCK
[+— R80 READ CLOCK
[+—R80 SERVO CLOCK
—» R80 WRITE CLOCK

ACLO

[—* R80 POWER SEQUENCE PICK
* R80 POWER SEQUENCE HOLD
TK-6740

Figure 3-1

IDC Functional Block Diagram

3-7

3.3.7

Clock Control

The clock control synchronizes the operation of the IDC with either the selected disk dI‘lVC or the CPU.
Selection of the proper clock for use as the CURRENT and SEQUENCE CLOCK outputs is caused
by inputs from the microcontroller.
3.3.8

TAG Bus Control

During an R80 seek function, the TAG bus control operates from microcontroller inputs to format and
assert the disk drive control word from the disk address register to the R80 disk drive. During an R80
rcad or write function, the microcontroller inputs to the TAG bus control enable assertion of R80 read
gate or write gate, as applicable.
3.3.9

Serializer

During an RLO02 seek or get status function, the serializer operates from microcontroller inputs to for-

mat and assert the disk drive control word from the disk address register to the RLO2 disk drives.

The serializer is also used during the read and write data functions to serialize the read/write data
address contained in the disk address register so that the address can be compared with the address
read from the disk drive. The address comparison is performed in the header/data comparator.
During the R80 read and write data functions, the serializer is also used to monitor the skip sector flag
(bit 13) of the R80 header data and to assert a skip sector error (SSE) input to the microsequencer if a

bad or displaced sector is encountered.
3.3.10 Header/Data Comparator
The header/data comparator operates from microcontroller inputs. During a read or write data function, the header/data comparator is used to locate the disk drive sector to or from which the data is to
be written or read. During a write check function, the header/data comparator is used to perform a bitby-bit comparison of data read from memory with the data contained in the data buffers.
3.3.11
Data Shift Register
The data shift register operates from microcontroller inputs during the read data, write data, and write
check data functions. During the initial phases of the read data and write data functions, and during the
write check data function, the data shift register is used with the header/data comparator to locate the
header sync byte of the data read from the disk drive. Once the header sync byte has been located and a
header match found, the operation of the data shift register depends on the function (write data, write
check data, or read data).
During the write data function, the data shift register serializes the data bytes input from the data

buffers and the sync byte input from the sync byte tristate drivers. The serialized output (DSRO) is
asserted to the NRZ data formatter.

During the write check function, the data shift register serializes the data byte input from the data
buffers and asserts the serialized data to the header/data comparator to allow a bit-by-bit comparlson
of the data containedin the data buffers with the data read from the disk drive.
During the read data function, the data shift register converts the serial read data input from the disk
drive to a byte format for storage in the data buffers.

3.3.12

NRZ Data Formatter

The NRZ data formatter operates from microcontroller inputs. During the write and maintenance functions, the NRZ data formatter converts the DSRO output of the data shift register into NRZ and

WRITE DATA pulses. The NRZ data output is the write data input to the R80 disk drive and the data
sample input to the ECC/CRC logic. The WRITE DATA pulses are input to the MFM encoder to
produce the RL WRITE DATA pulses for the RLO2 disk drives. When the CRC portion of the RL02
write data is to be written, the NRZ data formatter converts the NRZ output of the ECC/CRC logic to
WRITE DATA pulse inputs to the MFM encoder. The CRC and ECC portions of the R80 WRITE
DATA are written directly from the ECC/CRC logic by way of the NRZ data bus. During a read
function, the NRZ data formatter converts the SERIAL DATA IN to an NRZ format for use in the
ECC/CRC logic.
3.3.13

MFM Encoder

The MFM encoder converts the WRITE DATA inputs from the NRZ data formatter to MFM-encoded
RL WRITE DATA. These data make up the write data inputs to the RLO2 disk drives. During the
IDC maintenance function (testing under microdiagnostic control), the RL WRITE DATA is applied
to the read data separator to simulate the RL READ DATA output of the RLO2 disk drives.
3.3.14 ECC/CRC Logic
The ECC/CRC logic operates from microcontroller inputs during the write and read functions. During
both the write and read functions, the ECC/CRC logic generates both CRC and ECC data. During the
write function, the ECC/CRC logic outputs this data, as applicable, to be written on the disk drive.
During the read function, the ECC/CRC logic compares the CRC or ECC code generated with the
ECC/CRC data received to validate the integrity of the data read from the disk drive. If an error is
indicated by the comparison, an error signal is generated and the status of the error is indicated. The
ECC/CRC logic may also be controlled by the CPU to cause the transfer of the ECC POS/PAT data
from the IDC to the CPU.
3.3.15 Read Data Separator
The read data separator operates from microcontroller inputs to convert the MFM-encoded RL READ
DATA to a format compatible with the IDC logic. The read data separator also generates the DS
CLOCK, which is used to synchronize the IDC operation with the timing of the RL READ DATA
input.

3.3.16 Status/Data Gate
'
The status/data gate operates from microcontroller inputs to enable either the RL STATUS input or
DS DATA output of the read data separator to be applied as the RL DATA input to the disk data
multiplexer.
3.3.17 Disk Data Multiplexer
The disk data multiplexer enables either the RL DATA or R80 READ DATA as the READ DATA
_input to the data synchronizer, serializer, and header/data comparator.
3.3.18 Data Synchronizer
The data synchronizer converts the READ DATA inputs to pulses having a pulse duration equal to the
time interval between synchronizing clock pulses. [The applicable clock pulse used for synchronization
(current clock) is selected by microcontroller inputs to the clock control.] .
3.3.19 Sector and Index Pulse Multiplexer and Synchronizer
The SYNC SECTOR PLS and R80 SYNC INDEX PLS inputs to the microsequencer are controlled
by a multiplexer and synchronizer. The multiplexer enables either the RL SECTOR PLS or the R80
COMB SECTOR PLS from the disk drives to be asserted as the SECTOR PLS input to the synchronizer.

3-10

The synchronizer conditions the SECTOR PLS and R80 INDEX PLS inputs such that the pulse duration of these inputs will be equal to the synchronizing clock pulses (current clock) asserted from the
clock control.

3.4 IDC FUNCTIONAL THEORY OF OPERATION
Each of the IDC operations in causing a CPU-specified function is initiated by loading the IDC control
status register (CSR) with an IDC control word with the CRDY bit reset. When the IDC control word
is loaded into the CSR, the function bits (FO, F1, and F2) and the CRDY bit of the IDC control word
input are asserted to the microcontroller (see Figure 3-1). The function bits specify to the microcontroller the function that is to be performed and are used to provide the branch condition inputs to
preset the initial microword output of the microcontroller. The CRDY bit is the start command for the
microcontroller. When the IDC is not busy performing a CPU-requested function, it operates in the idle
mode of operation. While in the idle mode, the microcontroller sequentially enables and samples the

operational status of each of the disk drives. After sampling the operational status of the disk drives, the
microcontroller monitors the CRDY input from the CSR. If the CRDY input is reset, the microcontroller branches on the function bits (FO, F1, and F2) to preset the microword output of the microcontroller to initiate the CPU function specified.
The disk drive address bits of the IDC control word input are asserted on the DRIVE SEL 0 and

DRIVE SEL 1 outputs of the CSR. The DRIVE SEL 0 and 1 outputs of the CSR are asserted on the
RL DRIVE SEL 0 and RL DRIVE SEL 1 outputs of the IDC to enable, if applicable, one of the RL02
disk drives. Also, the disk drive address bits are used within the CSR. These bits are decoded to determine if the selected drive is an RL02 or the R80 and to enable the RL02 or R80 outputs of the CSR.
Internal to the CSR, the RL02 and R80 signals couple the applicable RL DRIVE RDY, RL DRIVE
ERROR, R80 DRIVE RDY, or R80 FAULT inputs to the CSR on the DRIVE RDY or DRIVE ERR
inputs to the microcontroller. (Refer to Paragraph 3.5.1 for a more detailed description of disk drive
select and drive status monitor.)
The R80 output of the CSR is asserted to the microcontroller, serializer, and data buffer and data
register control logic. The R80 input to the microcontroller is used to control the sequence of microwords generated. The R80 input to the serializer determines the sequence in which the contents of the
disk address register (DAR) is serialized. The R80 input to the data buffer and data register control
logic is used to enable the FIFO MAX and FIFO OVFLW outputs after either 512 bytes of data (one
full sector of R80 disk drive read data) or 256 bytes of data (one full sector of RL0O2 disk drive read
data).

The RLO2 outpfii of the CSR is asserted to the clock control to enable the proper clock to be selected

for synchronizing the IDC operation with the selected disk drive, and to the IDC multiplexers to enable
either the RLO2 or R80 data and sector pulse paths. The RLO02 output conditions the read data separator.

The interrupt enable bit (IE) of the IDC control word input is used within the CSR to enable the
UBUS BRS interrupt signal on command by the microcontroller. The UBUS BRS signal is asserted to
the CPU to indicate that the function specified by the IDC control word input has been completed, or
that the IDC operation has been halted due to a detected error.

The attention bits of the IDC control word input are used to reset the registered attention bits within
the CSR.

The maintenance bit of the IDC control word input is asserted to the microcontroller to enable the IDC
maintenance function.

3-11

The following paragraphs describe the operation of the IDC relative to each of the functions that can
be specified by the IDC control word input (see Table 3-1). The functional operation of the IDC in the
idle mode is also discussed. The following discussions are keyed to the functional block diagram in Figure 3-1. Where applicable, reference is made to more detailed discussions.
3.4.1
Seek Functions
Each of the four seek functions listed in Table 3-1 may be initiated by the CPU by loading the disk
address register with the correct disk drive control word and loading the CSR with the IDC control
word.
'

For the RLO2 seek function, the disk address register is loaded with an RL02 seek command (Figure 24). For the R80 seck functions, the disk address register is loaded with one of the three R80 drive commands (seek command, Figure 2-5; head select command, Figure 2-6; or recalibrate command, Figure
2-7).
Since the sequence of IDC operations in initiating the seek functions and asserting the applicable drive
commands depends on whether an RL0O2 or R80 disk drive is selected, the seek functions are discussed
separately as follows.
3.4.1.1

RLO2 Seek — When an RLO2 seek function is specified by the IDC control word input, the

microcontroller branches on the FO, F1, and F2 inputs to preset the microcontroller microword output.
The microcontroller then checks the DRIVE RDY input to determine if the selected disk drive is ready
(the selected disk drive is operational and not busy performing a seek). This check is performed because
it is possible that a previous seek was issued to this drive and the seek has not yet been completed. If the
DRIVE RDY input is present or when it is asserted, the microcontroller enables the RL SYSTEM
CLOCK (4.1 megahertz) to be asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control, which synchronizes the IDC with the selected RLO02 disk drive.
To avoid writing a command to the disk drive during the time that a sector pulse is present, the microcontroller loops until 50 microseconds after a sector pulse input (SYNC SECTOR PLS) from the disk
drive has been asserted and has terminated. Then, the microcontroller enables the serializer to assert,

serially, the contents of the DAR to the RL DRIVE COMMAND input of the applicable RL02 disk
drive.
After the last bit of the DAR (DAR 15) has been asserted, the microcontroller selects the P2 CLOCK
as the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control to allow the IDC
to be synchronized with the CPU. Then, the microcontroller sets the CRDY output of the CSR and, if
the IE bit of the previous IDC control word input was set, enables the UBUS BRS5 signal output of the
CSR. The UBUS BRS5 signal signifies to the CPU that the seek command has been issued to the disk
drive. The IDC then returns to the idle mode of operation.

3.4.1.2 R80 Seek — When the disk address register is loaded, the DAR 09:02 outputs are asserted on
the R80 TAG BUS 09:02 signal lines. The DAR 15, 01, and 00 outputs are applied to the TAG bus
control. DAR 14 and 13 are asserted as conditioning inputs to the R80 TAG 2 and R80 TAG 1 signal
line drivers.
When an R80 seek is specified by the IDC control word input and CRDY is reset, the microcontroller
branches on the FO, F1, and F2 inputs to preset the microcontroller microword output.

3-12

The microcontroller then checks the DRIVE RDY input to determine if the R80 disk drive is ready
(the R80 disk drive is operational and not busy performing a seek). If the DRIVE RDY input is present
or when it is asserted, the microcontroller asserts a seek instruction input to the TAG bus control. The

seck instruction enables the DAR 01 and 00 outputs of the disk address register to be asserted on the
R80 TAG BUS 01 and 00 signal lines, respectively, via the READ TAG and WRITE TAG outputs of

the TAG bus control. Next, the microcontroller asserts a strobe input to the TAG bus control. The
strobe input enables the HD/CYL TAG output of the TAG bus control, and if DAR 15 is H (the seek
instruction in the DAR is a recalibrate command), it enables the CNTL TAG output of the TAG bus
control. The HD/CYL TAG output is used with the DAR 13 and 14 inputs to the R80 TAG 1 and R80

TAG 2 signal line drivers to enable the applicable R80 TAG input to the R80 disk drive (R80 TAG 1

if
the disk address register was loaded with an R80 seek command; R80 TAG 2 if the disk address register was loaded with an R80 head select command). If the disk address register was loaded with an R80
rccalibrate command, the CNTL TAG output of the TAG bus control would assert the R80 TAG 3
input to the R80 disk drive (see Table 2-2). (A detailed discussion of the TAG bus control logic is
presented in Paragraph 3.5.2))

Assertion of one of the R80 TAG inputs loads the R80 TAG BUS 9:0 signals into the R80 disk drive.
After the specified seek instruction has been asserted, the microcontroller sets the CRDY output of the

CSR and, if the IE bit of the previous IDC control word input was set, enables the UBUS BR5 signal
output of the CSR. The IDC then returns to the idle mode of operation.

3.4.2

RLO2 Get Status

The RLO2 get status function is initiated by loading the disk address register with an RLO2 get status
command (Figure 2-3) and loading the CSR with the applicable IDC control word.

When an RLO2 get status function is specified by the IDC control word, the microcontroller branches

on the FO, FI, and F2 inputs to preset the microcontroller microword output.

The microcontroller then selects FIFO A and clears the FIFO A address counter. Next the microcontroller enables the RL WRITE CLOCK (4.1 megahertz) to be asserted on the CURRENT CLOCK

and SEQUENCE CLOCK outputs of the clock control, which synchronizes the operation of the IDC

with the selected disk drive. Then the microcontroller enables the serializer to assert, serially, the RL02
get status command from the disk address register to the RL DRIVE COMMAND input of the selected RLO2 disk drive. After the RL0O2 get status command has been asserted, the microcontroller

deselects the RL WRITE CLOCK and enables the RL STATUS CLOCK on the CURRENT CLOCK
and SEQUENCE CLOCK outputs of the clock control.
The 16 bits of status information from the selected RL02 disk drive are asserted to the IDC in synchronization with the RL STATUS CLOCK. (The format and bit significance of the RL02 status informa--

tion are shown in Figure 2-19.) The RLO2 status information is applied to the IDC via the RL STATUS

input to the RLO2 receivers. Each bit of the RL02 status information is coupled through the status/data gate, disk data multiplexer, and data synchronizer, and is asserted to the data shift register.
After the first eight bits of status information have been shifted into the data shift register, the microcontroller enables the read data tristate drivers, which asserts the parallel output of the data shift register to the FIFOs. Then, the microcontroller writes the first eight bits as a single byte into FIFO A and
increments the FIFO A address. After the second eight bits of status information have been shifted into
the data shift register, the microcontroller again enables the read data tristate drivers and writes the
second eight bits as a single byte into FIFO A. (A detailed discussion of how the microcontroller causes
writing of data to the data buffers is provided in Paragraph 3.5.12.)

3-13

After the two bytes of status information have been loaded into FIFO A, the microcontroller deselects
the RL STATUS CLOCK and enables the CPU CLOCK (P2 CLOCK) to be asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control. Then, the microcontroller
clears the FIFO address, sets the CRDY output of the CSR, and, if the IE bit of the previous IDC
control word was set, asserts a UBUS BRS interrupt to the CPU to signal that the requested function
has been completed. The RLO2 status information is now ready for transfer from the IDC to the CPU.
The CPU transfers the RLO2 status information from the IDC to the CPU as discussed in Paragraph
3.5.13.

3.4.3

R80 Get Status

The R80 get status function is initiated by loading the CSR with the applicable IDC control word.
When the IDC control word is loaded, the microcontroller branches on the FO, F1, and F2 inputs to
preset the microcontroller microword output.

Then, the microcontroller selects FIFO A and clears the FIFO A address counter. The 16 bits of R80
status information from the R80 disk drive are asserted to the IDC in parallel format. The R80 status
information and R80 sector count inputs are applied to the R80 multiplexer. After FIFO A has been
selected and the FIFO address counter has been cleared, the microcontroller enables the R§0 SECTOR
COUNT through the R80 multiplexer, writes the sector count information into FIFO A, and increments the FIFO A address. Then, the microcontroller enables the R80 STATUS through the R80
multiplexer and writes the R80 status information into FIFO A.

After the R80 status information has been written into FIFO A, the microcontroller clears the FIFO A
address counter, sets the CRDY output of the CSR, and, if the IE bit of the previous IDC control word
was set, asserts a UBUS BRS signal to the CPU. The R80 status information is now ready for transfer
from the IDC to the CPU. The CPU transfers the R80 status information from the IDC to the CPU as
discussed in Paragraph 3.5.13.
3.4.4

Read Header

The read header function is initiated by loading the CSR with the applicable IDC control word. The
sequence of operations performed by the IDC in executing the read header function depends on whether the header data is to be retrieved from one of the RL0O2 disk drives or the R80 disk drive. These
alternatives are discussed separately as follows.
3.4.4.1 RLO2 Read Header - When the IDC control word is loaded, the microcontroller branches on
the FO, F1, and F2 inputs to preset the microcontroller microword output.
The microcontroller then selects FIFO A and resets the FIFO A address counter. Next the microcontroller checks the DRIVE RDY input to determine if the selected RLO2 disk drive is ready (the
selected disk drive is operational and not busy performing a seek). If the DRIVE RDY input is present
or when it is asserted, the microcontroller enables the RL SYSTEM CLOCK (4.1 megahertz) to be
asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control. (A detailed discussion of the clock control is provided in Paragraph 3.5.3.) This synchronizes the operation of
the IDC with the selected RLO02 disk drive. Then, the microcontroller loops until the leading edge of a
SYNC SECTOR PLS is detected. (This pulse is generated from the RL SECTOR PLS from the selected RLO2 disk drive.) After the leading edge of the RL SECTOR PLS has been detected, the microcontroller loops until eight microseconds after the RL SECTOR PLS has terminated. After the loop,
the microcontroller enables the read data separator, and then loops again until after 32 RL READ
DATA pulses have been asserted. When enabled, the read data separator converts the MFM-encoded
RL READ DATA to an NRZ format. The read data separator is enabled during the header preamble
portion of the RL READ DATA from the RLO2 disk drive (see Figure 2-20) and uses the first four

3-14

bytes of zeros to synchronize itself with the RL READ DATA input. In addition to converting the RL
READ DATA to an NRZ format, the read data separator generates a clock (DS CLOCK) that is synchronized with the DS DATA output. After the synchronization loop, the microcontroller clears the
data shift register, presets the CONSTANTS (which will allow the header/data comparator to determine when the sync byte of the RL READ DATA is present), and enables the DS CLOCK output of
the read data separator to be asserted on the CURRENT CLOCK output of the clock control.
The SEQUENCE CLOCK output of the clock control is inhibited until the sync byte of the RL READ
DATA has been asserted. This causes the microcontroller to stall until the sync byte is located. (A
detailed discussion of how the sync byte is located is provided in Paragraph 3.5.4.)

When the sync byte has been located, the SYNC SEEN signal is asserted to the clock control, which
enables the DS CLLOCK to be asserted on the SEQUENCE CLOCK output of the clock control. Resumption of the SEQUENCE CLOCK restarts the microcontroller.
After the first eight bits following the sync byte have been shifted into the data shift register, the microcontroller enables the read data tristate drivers, loads the contents of the data shift register into FIFO
A, and increments the FIFO A address counter. The following eight bits are also shifted into the data
shift register, loaded into FIFO A, and the FIFO A address counter incremented. Now the two bytes of
the RL sector address are contained in FIFO A.
As shown in Figure 2-20, the two bytes of RL READ DATA following the two address bytes are zeros.
Thus, these data are not loaded into the FIFO. However, the two bytes of CRC data that follow are
loaded into FIFO A. (A detailed discussion of how the microcontroller causes writing of data to the
data buffers is provided in Paragraph 3.5.12.)

After the CRC data have been loaded into FIFO A, the microcontroller clears the FIFO A address
counter and enables the P2 CLOCK to be asserted on the SEQUENCE CLOCK and CURRENT
CLOCK outputs of the clock control. This allows the IDC to be synchronized with the CPU. The microcontroller also sets the CRDY output of the CSR and, if the IE bit of the previous IDC control word
input was set, asserts a UBUS BRS signal to the CPU.

The RLO2 header data are now ready for transfer from the IDC to the CPU. The CPU transfers the
RLO2 header data from the IDC to the CPU as discussed in Paragraph 3.5.13.
3.4.4.2 RS80 Read Header - When the IDC control word is loaded, the microcontroller branches on the
FO, F1, and F2 inputs to preset the microcontroller microword output.
The microcontroller then selects FIFO A. Next the microcontroller checks the DRIVE RDY input to
determine if the R80 disk drive is ready (the disk drive is operational and not busy performing a seek).
If the DRIVE RDY input is present or when it is asserted, the microcontroller enables the R80 SERVO
CLOCK to be asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock
control. (A detailed discussion of the clock control is provided in Paragraph 3.5.3.) This synchronizes
the IDC operation with the operation of the R80 disk drive. Then the microcontroller loops until the
leading edge of the SYNC SECTOR PLS is detected. (The SYNC SECTOR PLS is generated from
the R80 SECTOR PLS or R80 INDEX PLS input from the R80 disk drive.) After the leading edge of

the SYNC SECTOR PLS is detected (indicating the beginning portion of the sector), the microcontroller clears the FIFO A address counter and loops until 60 R80 SERVO CLOCK pulses have been
asserted. This loop is initiated to inhibit enabling the R80 read circuitry until the read /write heads are
positioned over the sector gap portion of the R80 header data. The microcontroller then enables the
TAG bus control to assert the READ TAG and CNTL TAG signals to the R80 drivers. These signals
enable the R80 drivers to assert the R80 TAG BUS 01 and R80 TAG 3 outputs of the IDC. These
outputs enable the R80 read gate and allow the R80 READ DATA and R80 READ CLOCK to be
asserted to the IDC.

3-15

After the R80 TAG BUS 01 and R80 TAG 3 signals have been asserted, the microcontroller loops until
after 88 R80 servo clock pulses have been asserted to allow the R80 disk drive to achieve phase lock.
Phase lock is achieved by reading a sequence of zeros in the sector gap of the R8O READ DATA. (See
Figure 2-17 for the R80 READ DATA format.) After the phase lock loop, the microcontroller clears
the data shift register and presets the CONSTANTS output of the microcontroller to the R80 SYNC
BYTE pattern. Then the microcontroller enables the R80 READ CLOCK to be asserted on the CURRENT CLOCK output of the clock control. The R80 READ CLOCK is not asserted on the
SEQUENCE CLOCK output until after the sync byte has been found (when SYNC SEEN from the
header/data comparator is asserted to the clock control). Thus, the microcontroller is forced to stall
until the header sync byte of the R80 READ DATA is located. (A detailed discussion of how the sync
byte is located is provided in Paragraph 3.5.4.)
'
When the header sync byte has been located, the SYNC SEEN output of the header/data comparator
is asserted to the clock control to enable the R80 READ CLOCK to be asserted on the SEQUENCE
CLOCK output. This restarts the microcontroller, which then enables the read data tristate drivers.

After the first eight bits of header information (first byte of cylinder address) have been shifted into the

data shift register, the microcontroller loads the parallel output of the data shift register into FIFO A
and then increments the FIFO A address counter. The remaining 40 bits of header information are
converted into byte format and loaded into FIFO A in the same manner as the first eight bits. (A detailed discussion of how the microcontroller causes writing of data to the data buffers is provided in
Paragraph 3.5.12.)

After all six bytes of R80 header data have been loaded into FIFO A, the microcontroller resets the
FIFO A address counter and enables the P2 CLOCK to be asserted on the SEQUENCE CLOCK and
CURRENT CLOCK outputs of the clock control. This synchronizes IDC operation with the CPU. The
microcontroller also deasserts the read gate output of the tag bus control, sets the CRDY output of the
CSR, and, if the IE bit of the previous IDC control word was set, asserts a UBUS BRS signal to the
CPU.

The R80 header data are now ready for transfer from the IDC to the CPU. The CPU transfers the R80
header data from the IDC to the CPU as discussed in Paragraph 3.5.13.

3.4.5 Write Data, Read Data, and Write Check Data
The write data, read data, and write check functions are initiated by loading the data to be written to
the disk drive into the FIFO, loading the disk address register with the applicable read/write data address, and loading the CSR with the applicable IDC control word.
The first sector (512 bytes, R80; 256 bytes, RL02) of data to be written is loaded into FIFO A. If two
sectors are to be written, the second sector is loaded into FIFO B. If several contiguous sectors of data
are to be written, the CPU loads FIFO A with the first sector, and FIFO B with the second sector.
After the IDC has transferred the data from FIFO A, and while it is transferring the second sector
from FIFO B, the CPU loads the third sector of data into FIFO A. After the IDC has transferred the
contents of FIFO B, and while it is transferring the third sector from FIFO A, the CPU loads FIFO B
with the fourth sector of data. This process may be repeated until all sectors of the cylinder (31 sectors
for the R80 and 40 sectors for the RL02) have been written.

After the data have been loaded into the FIFO(s) and the read /write data address has been loaded into
the disk address register, the CPU initiates the write data function by loading the applicable IDC control word into the CSR.
The operational sequence executed by the IDC in performing the write data, read data, and write check
data functions depends on whether an RLO2 or the R80 disk drive is selected. Therefore, the operational sequénces are discussed separately in the following paragraphs.
3-16

3.4.5.1

RLO2 Write Data, Read Data, and Write Check - When an RL02 write data, read data, or

write check function is specified by the IDC control word, the microcontroller branches on the FO, F1,

and F2 inputs to preset the microcontroller microword output. The microcontroller then selects FIFO A
and resets the FIFO A address counter. Next, the microcontroller checks the DRIVE RDY input to
determine if the selected disk drive is ready (the disk drive is operational and not busy performing a
seek function). If the DRIVE RDY input is present or when it is asserted, the microcontroller enables
the

SYSTEM

CLOCK

(4.1

megahertz)

be asserted

the

CURRENT CLOCK

and

SEQUENCE CLOCK outputs of the clock control. This synchronizes the IDC operation with the se-

lected RLO2 disk drive. (A detailed discussion of the clock control is provided in Paragraph 3.5.3.)
The microcontroller then loops until the leading edge of the SYNC SECTOR PLS is detected. This

pulse is generated by the RL SECTOR PLS input from the RL02 disk drive. Presence of the SYNC
SECTOR PLS indicates that the applicable read/write head of the RLO2 disk drive is positioned at the
beginning portion of a data sector. After the leading edge of the SYNC SECTOR PLS is detected, the
microcontroller loops until the trailing edge of the SYNC SECTOR PLS is detected. Then the microcontroller again loops until 32 RL SYSTEM CLOCK (4.1 megahertz) pulses have been asserted to the
microcontroller via the SEQUENCE CLOCK output of the clock control. This second microcontroller
loop is initiated to prevent the read data separator from trying to achieve phase lock on data that may
contain glitches. After the loop, the microcontroller enables the read data separator, clears the
ECC/CRC logic, clears the MISMATCH output of the header/data comparator, and then loops until
after 32 RL SYSTEM CLOCK (4.1 megahertz) pulses have been asserted to the microcontroller via

the SEQUENCE CLOCK output of the clock control. This loop is initiated to allow time for the read
data separator to achieve phase lock on the data being read from the disk (RL READ DATA input).
Phase lock is achieved by reading a sequence of four bytes of zeros in the header preamble of the RL
READ DATA. (See Figure 2-20 for the RL READ DATA format.)
After the loop for phase lock, the microcontroller presets the conditions for locating the header sync
byte of the RL READ DATA. The microcontroller also conditions the serializer such that after the
sync byte has been located, the address portion of the RL READ DATA input can be compared with
the read/write data address contained in the disk address register.

To preset the conditions for locating the header sync byte, the microcontroller clears the data shift
register and presets the CONSTANTS output of the microcontroller to the header sync byte pattern.
Then the microcontroller selects the DS CLOCK for syncronization.
The DS CLOCK is generated
from the RL READ DATA input and thus synchronizes the IDC with the selected RLO02 disk drive
data rate. When the DS CLOCK from the read data separator is selected, the DS CLOCK is asserted
on the CURRENT CLOCK output of the clock control. The DS CLOCK is not asserted on the
SEQULNCE CLOCK output of the clock control until after the sync byte has been found (when
SYNC SEEN from the header/data comparator is asserted to the clock control). Thus, the microcontroller is forced to stall until the header sync byte has been found. (A detailed discussion of how the
header sync byte is located is provided in Paragraph 3.5.4.)
When the RL READ DATA header sync byte is found, the SYNC SEEN output of the header/data
comparator is asserted to the clock control to enable the DS CLOCK to be asserted on the
SEQUENCE CLOCK output. This restarts the microcontroller which then enables the ECC/CRC logic. The SYNC SEEN signal is asserted also to the serializer to enable the contents of the disk address
register to be asserted serially to the header/data comparator where it is compared bit-by-bit with the
address information of the RL READ DATA. (A detailed discussion of the RLC2 header comparisons
is provided in Paragraph 3.5.5.)

The address information of the RL READ DATA is also asserted via the data synchronizer on the
SERIAL DATA IN input of the NRZ data formatter. The NRZ data formatter couples the SERIAL
DATA IN to the ECC/CRC logic via the NRZ data bus. While the address information is being compared in the header/data comparator and while the results of the comparison are being tested, the
ECC/CRC logic generates a CRC word based on the configuration of the two bytes of address information and the two bytes of zeros that follow the address information.
3-17

After. the 16 bits of address information of the RL READ DATA have been compared with the
read/write data address, the microcontroller turns off the serializer and monitors the MISMATCH
output of the header/data comparator. If the MISMATCH output is low (the address information of
the RL READ DATA did not match the read/write data address in the disk address register), the
microcontroller enables the RL SYSTEM CLOCK (4.1 megahertz) to be asserted on the CURRENT
CLOCK and SEQUENCE CLOCK outputs of the clock control. Then the microcontroller loops until
the next sector is encountered (the next SYNC SECTOR PLS is asserted) before reinitiating the header/data comparison. This process is repeated until a match is found or until TIMEOUT occurs. (Refer
to Paragraph 3.5.10 for a discussion of TIMEOUT.)

If the MISMATCH output is high (the address information of the RL READ DATA matched the
read/write data address in the disk address register), the microcontroller loops until the two bytes of
zeros following the address information of the RL READ DATA have been asserted to the ECC/CRC
logic. Then the microcontroller enables the ECC/CRC logic to load the header CRC word of the RL
READ DATA. After the header CRC word is loaded, the microcontroller enables the ECC/CRC logic

to compare the CRC word generated by the ECC/CRC logic from the address information and two
bytes of zeros of the address information with the header CRC word of the RL READ DATA.

If a CRC error is indicated by the ECC/CRC logic (CRC/ECC ERROR is asserted to microcontroller), the microcontroller deselects the DS CLOCK and enables the P2 CLOCK to be asserted on
the SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock control. This synchronizes
the operation of the IDC with the CPU. Then the microcontroller sets the Operation Incomplete (OPI)
and CRDY bits in the CSR. Next, if the IE bit of the previous IDC control word was set, the microcontroller generates and asserts a UBUS BRS interrupt to the CPU.
If no CRC error is detected, the microcontroller clears the ECC/CRC logic and branches on the F1
and F2 bits of the IDC control word input to initiate the operations associated with the RL02 write data

function, RL02 read data function, or RLO2 write check function.
a.

RLO2 Write Data

After the proper sector has been located and the CRC pattern verified, the microcontroller
checks to make certain that the data to be written to the disk were loaded into the FIFO
(FIFO OVFLW is asserted to the microcontroller) and that the selected RLO2 disk drive is

operational (DRIVE RDY is asserted to the microcontroller).

’

If the FIFO was not filled by the CPU, the microcontroller enables the P2 CLOCK to be
asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control, sets the Data Late (DLT) error and CRDY bits in the CSR, clears the MISMATCH
output of the header/data comparator, and, if the IE bit of the previous IDC control word
was set, generates and asserts a UBUS BRS signal to the CPU.
If the selected RL0O2 disk drive is not operational (DRIVE RDY is not asserted), the microcontroller enables the P2 CLOCK to be asserted on the CURRENT CLOCK and
SEQUENCE CLOCK outputs of the clock control, sets the Operation Incomplete (OPI) and
CRDY bits in the CSR, and, if the IE bit of the previous IDC control word was set, generates
and asserts a UBUS BRS signal to the CPU.

3-18

If the FIFO is full and the selected RL02 disk drive is operational, the IDC continues with
the write data function. First the microcontroller deselects the DS CLOCK and enables the
RL SYSTEM CLOCK (4.1 megahertz) to be asserted on the SEQUENCE CLOCK and
CURRENT CLOCK outputs of the clock control. Then, after a loop, the microcontroller
clears the FIFO address counter, clears the data shift register, and enables the NRZ data
formatter and MFM encoder. Next the microcontroller again loops until 40 bits (zeros), part

of the data preamble, have been written to the selected RL02 disk drive. (The zeros are written by holding the DSRO input to the NRZ data formatter low.) When the last bit of the data

prcamble has been written, the microcontroller generates and enables the CONSTANTS
from the microcontroller to be loaded into the data shift register. (The CONSTANTS specify the sync byte pattern (80¢) to be written as part of the RL write data preamble.) Then the
microcontroller enables the CONSTANTS to be asserted serially via the DSRO output of the

data shift register to the NRZ data formatter. The NRZ data formatter samples the DSRO
output of the data shift register at a 4.1 megahertz rate and generates an NRZ formatted
pulse train, which is asserted to the ECC/CRC logic via the NRZ data bus. The NRZ data

formatter also generates the WRITE DATA inputs of the MFM encoder.
The MFM encoder translates the WRITE DATA inputs to an MFM format and asserts these

data to the sclected RLO2 disk drive via the RL WRITE DATA signal line.
After the last bit of the sync byte has been asserted to the NRZ data formatter, the microcontroller enables the first byte of data from FIFO A to be loaded into the data shift register

and increments the FIFO A address counter. At the same time, the microcontroller enables
the ECC/CRC logic, which samples the bit configuration of the 256 bytes of data as it is
being transferred to the disk drive and generates a 16-bit CRC word representative of the bit
configuration.
After the first byte of data has been loaded, the data shift register serially asserts bits 0
through 7 of the first data byte to the NRZ data formatter. After bit 7 of the first data byte
has been asserted to the NRZ data formatter, the second byte of data from FIFO A is loaded

into the DSR and the FIFO A address counter is again incremented. After bit 7 of the second
data byte has been asserted to the NRZ data formatter, the third data byte from FIFO A is
loaded into the data shift register and the FIFO A address counter is incremented. This pro-

cess is repeated until all 256 bytes of data from FIFO A have been loaded into the data shift
register and asserted to the RL WRITE DATA input of the selected RLO2 disk drive via the
NRZ data formatter and MFM encoder. (A detailed discussion of how the microcontroller
causes transfer of data from the data buffers to the data shift register and data shift register
operation in serializing the data is provided in Paragraph 3.5.11.)
After the 256 bytes of data have been asserted on the RL WRITE DATA signal line (the
FIFO A address counter has been incremented to its maximum count and FIFO MAX is

asserted to the microcontroller), the microcontroller enables the ECC/CRC logic to assert
serially the 16-bit CRC word derived from the bit configuration of the 256 bytes of data on
the RL WRITE DATA signal line. The CRC word is asserted on the RL WRITE DATA

signal line via the NRZ data bus, NRZ data formatter and MFM encoder. After the last bit
of the CRC word is asserted, the microcontroller inhibits the ECC/CRC logic, and then
holds the NRZ data formatter enabled until 16 zeros (data postamble) have been written.
After the 16 zeros have been written, the microcontroller inhibits the NRZ data formatter
and enables the P2 CLOCK to be asserted on the SEQUENCE CLOCK and- CURRENT
CLOCK outputs of the clock control, which synchronizes IDC operation with'the CPU. Then

the microcontroller clears the FIFO A address counter and enables the PORT XFER REQ
output of the CSR to be asserted to the CPU.

3-19

If more data are to be written, the CPU asserts XFER GRANT to the CSR. The XFER
GRANT input resets the PORT XFER REQ output of the CSR, which causes the microcontroller to select FIFO B and then monitor the CRDY output of the CSR. If more data are
to be transferred, the CRDY output of the CSR will have remained cleared and the microcontroller will then increment the read/write data address in the disk address register and
reset the function timer. Then the microcontroller reinitiates the RLO2 write data function to
cause the transfer of the data contained in FIFO B to the next sector of the RL02 disk drive.
If no more data is to be written, the CPU responds to the PORT XFER REQ input by load-

ing an IDC control word with CRDY set and then asserting XFER GRANT. The XFER
GRANT input to the IDC resets the PORT XFER REQ signal. When the PORT XFER
REQ signal is reset, the microcontroller monitors the CRDY output of the CSR. If the

- CRDY output is set, indicating that no more data are to be transferred, the microcontroller

sets the CRDY output of the CSR and, if the IE bit of the previous IDC control word was
set, generates and asserts a UBUS BRS signal to the CPU.
RLO02 Read Data

After the proper sector has been located and the CRC pattern verified, the microcontroller
checks to make certain that the selected FIFO is empty. If the FIFO is full (FIFO OVFLW
is asserted to the microcontroller), the microcontroller clears the MISMATCH output of the
‘header/data comparator and sets the CRDY and Data Late (DLT) error bits in the CSR. If

the IE bit of the previous IDC control word was set, the microcontroller also generates and

- asserts a UBUS BR35 signal to the CPU. The IDC then returns to the idle mode of operation.

If the FIFO is empty, the microcontroller deselects the DS CLOCK and enables the RL
SYSTEM CLOCK (4.1 megahertz) to be asserted on the SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock control. The microcontroller then loops until the write
splice area within the header gap has passed the read/write heads of the RLO2 disk drive.
Then the microcontroller clears the ECC/CRC logic and enables the read data separator.
Next, the microcontroller loops until 32 RL. READ DATA pulses have been asserted to the
IDC. This loop is initiated to allow the read data separator to achieve phase lock on the data
being read from the disk. After the phase lock loop, the microcontroller clears the selected
FIFO address counter and presets and asserts the CONSTANTS output of the microcontroller to the header/data comparator. (The CONSTANTS output is preset to the bit
configuration of the RL READ DATA data preamble sync byte.) The microcontroller then
enables the DS CLOCK to be asserted on the CURRENT CLOCK output of the clock control. The DS CLOCK is not asserted on the SEQUENCE CLOCK output of the clock control until the sync byte has been found (when SYNC SEEN from the header/data comparator is asserted to the clock control). Thus, the microcontroller is forced to stall until the
RL READ DATA data preamble sync byte has been found. (A detailed discussion of how
the sync byte is located is provided in Paragraph 3.5.4.)

Detection of the sync byte of the data preamble signals the start of the data segment of the
sector to be read. When the header preamble sync byte has been found, the SYNC SEEN
output of the header/data comparator is asserted to the clock control to enable the DS
CLOCK to be asserted on the SEQUENCE CLOCK output. This restarts the microcontroller, which then enables the ECC/CRC logic, and begins converting the RL READ
DATA into byte format and storing the 256 bytes of RL READ DATA in the selected FIFO.
(A detailed discussion of how the READ DATA are converted to byte format and stored in
the data buffers is provided in Paragraph 3.5.12.)

3-20

Each bit of the 256 bytes of RL READ DATA is used in the ECC/CR
I6-bit CRC word representative of the bit configuration of the RL

C logic to generate a
READ DATA. After all

256 bytes of RL READ DATA have been loaded into the selected FIFO
(FIFO MAX is
asserted to the microcontroller), the microcontroller enables the 16-bit
CRC word from the
RLO2 disk drive to be loaded into the ECC/CRC logic. After the CRC
word has been
loaded, the microcontroller enables the ECC/CRC logic to compare the CRC
word generated from the 256 bytes of RL READ DATA with the CRC word read from
the disk. Next
the microcontroller deselects the DS CLOCK and enables the P2 CLOCK
to be asserted on
the SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock
control. Then the
microcontroller monitors the CRC/ECC ERROR signal output of the ECC/CRC
logic.

If a CRC/ECC error is indicated, the microcontroller sets the CRDY output of the CSR

and, if the IE bit of the previous IDC control word was set, generates and
asserts a
BR5 signal to the CPU. Then the IDC returns to the idle mode of operation.

If no CRC/ECC ERROR is indicated, the microcontroller clears the selected

UBUS

FIFO address

counter and generates and asserts the PORT XFER REQ output of the CSR to the CPU.

This signal signifies that the IDC has completed reading a sector of data

are ready for transfer to the CPU.

and that the data

If more data are to be read, the CPU asserts a XFER GRANT signal to the CSR. When
the
XFER GRANT signal is asserted, the PORT XFER REQ output is reset. When
the PORT
XFER REQ is reset, the microcontroller changes the FIFO selected and monitors
the CRDY
output of the CSR. If the CRDY output of the CSR has remained cleared,
the microcontroller increments the read/write data address in the disk address register,
resets the

timer, and reinitiates the RL02 read data function to read the next sector of
RL READ
DATA and store the data in the selected FIFO.

If no further data are to be read, the CPU responds to the PORT XFER REQ input by loading an IDC control word with CRDY set and then asserting XFER GRANT. The XFER

GRANT input to the IDC resets the PORT XFER REQ signal. When the PORT XFER

REQ signal is reset, the microcontroller monitors the CRDY output of the CSR. If the
CRDY output is set, the microcontroller sets the CRDY output of the CSR and, if the IE bit

of the previous IDC control word was set, generates and asserts a UBUS BRS signal to the
CPU. The IDC then returns to the idle mode of operation.

'RLO2 Write Check
After the proper sector has been located and the CRC pattern verified, the microcontro
ller
checks to make certain that the data to be compared with the data from the disk
drive were
loaded into the FIFO (FIFO MAX is asserted to the microcontroller).
If the FIFO was not filled by the CPU, the microcontroller enables the P2 CLOCK
to be
asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock
control, sets the Data Late (DTL) error and CRDY bits in the CSR, clears the MISMATC
H
output of the header/data comparator, and, if the IE bit of the previous IDC control
word
was set, generates and asserts a UBUS BRS5 signal to the CPU.

If the FIFO is full, the IDC continues with the write check function. First the microcontroller enables the RL SYSTEM CLOCK (4.1 megahertz) to be asserted on the
SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock control. Next, the microcontroller disables the read data separator and then loops until the write splice.area within
the header gap has passed the read/write heads of the RLO02 disk drive. The read data scparator is disabled to prevent the read data separator circuitry from being triggered by data

glitches at the beginning of the header gap. (The data glitches were produced when the writc
heads were tirst turned on when the header gap was written.)

After the loop to allow the read/write heads of the RLO02 disk drive to be positioned over the
valid data in the header gap, the microcontroller again enables the read data separator. After
the read data separator is enabled, the microcontroller loops until 32 RL SYSTEM CLOCK
pulses have been asserted to the microcontroller via the SEQUENCE CLOCK output of the
clock control. This loop is initiated to allow the read data separator to again achieve phase
lock on the data being read from the disk.

After the phase lock loop, the microcontroller clears the FIFO address counter and enables
the first byte of data from the selected data buffer to be asserted to the data shift register.
The microcontroller also clears the MISMATCH output of the header/data comparator, and
presets and enables the CONSTANTS from the microcontroller to be asserted to the header/data comparator. (The CONSTANTS output is preset to the bit configuration of the
RLO2 READ DATA data preamble sync byte.) The microcontroller then enables the DS
CLOCK to be asserted on the CURRENT CLOCK output of the clock control. The DS
CLOCK is not asserted on the SEQUENCE CLOCK output of the clock control until the
sync byte has been found (when SYNC SEEN from the header/data comparator is asserted
to the clock control). Thus, the microcontroller is forced to stall until the RLO2 READ
DATA data preamble sync byte has been found. (A detailed discussion of how the sync byte
is found is provided in Paragraph 3.5.4.)

Detection of the RL02 READ DATA data preamble sync byte signals the start of the data
segment of the sector on which the write check is to be performed. When the sync byte has
been found, the SYNC SEEN output of the header/data comparator is asserted to the clock
control to enable the DS CLOCK to be asserted onto the SEQUENCE CLOCK output. This
restarts the microcontroller, which then enables the ECC/CRC logic.
In the write check mode, the WRT CHK LOAD output of the header/data comparator is
enabled also when the RLO2 READ DATA data preamble sync byte is found. The WRT
CHK LOAD signal is asserted to the data shift register where it enables the first data byte
from the selected FIFO to be loaded into the data shift register. The microcontroller then
increments the selected FIFO address counter.

When the first data byte is loaded into the data shift register, bit O of the first data byte is
asserted to the header/data comparator via the DSRO output of the data shift register. The
first bit of the data portion of the first data byte is asserted to the header/data comparator
coincident with the first bit of the data portion of the RL READ DATA asserted from the
disk drive. (Because the CURRENT CLOCK used by the data shift register is derived from
the RL READ DATA input, the data loaded into the data shift register are serialized and
asserted to the header/data comparator in sync with each bit of the RL READ DATA input.) The data shift register serializes and asserts bits O through 7 of the first data byte to the
header/data comparator.

After bit 7 of the first data byte has been asserted to the header/data comparator, the microcontroller loads the second byte of data from the selected FIFO into the data shift register
and increments the selected FIFO address counter.
3-22

Each bit of the data asserted to the header/data comparator for comparison with the RL
READ DATA is asserted also to the ECC/CRC logic via the NRZ data formatter and NRZ
data bus. The ECC/CRC logic generates a 16-bit CRC word based on the configuration of
the 2048 data bits asserted to the ECC/CRC logic via the DSRO input to the NRZ data
formatter.

After all 256 bytes of data from the FIFO have been serialized and asserted to the header/data comparator for comparison with the RL READ DATA input (the FIFO A address
counter has been incremented to its maximum count and FIFO MAX is asserted to the microcontroller), the microcontroller strobes the header/data comparator to sample the results
of the data comparison. If the data did not compare, the MISMATCH output of the headcr/data comparator will remain low. If the data matched the RL READ DATA, the MISMATCH output will be set high. The MISMATCH output is asserted to the status logic in
the CSR and to the microcontroller.

The microcontroller also enables the ECC/CRC logic to load the 16-bit CRC word being
recad from the RLO2 disk drive. After the CRC word has been loaded, the microcontroller
cnables the ECC/CRC logic to compare the two CRC words (the CRC word generated from
the 2048 bits of data used for comparison with the 2048 bits of RL READ DATA with the
CRC word read from the disk drive). Then the microcontroller enables the P2 CLOCK to be
asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control
to synchronize I1DC operation with the CPU.

If a CRC comparison error is indicated (the ECC/CRC ERROR signal is asserted to the
microcontroller and CSR), the microcontroller sets the CRDY output of the CSR and, if the
IE bit of the previous IDC control word was set, generates and asserts a UBUS BRS signal
the CPU. Then the IDC returns to the idle mode of operation. [Note that if the results of the
data comparison (the 2048 bits of RL READ DATA with the 2048 bits of data from the
FIFO) did not match, then a CRC error will also occur. It is not, therefore, necessary to
terminate the write check function when a data comparison error is detected. However, if the
write check function is terminated by a CRC error, the CPU can determine if the error was
CRC related or a data comparison error by reading the IDC status word. The results of the
data comparison (MISMATCH) and CRC comparison (CRC/ECC ERROR) are made
available to the CPU via the IDC status word.]

If the write check function is to be performed on the next sector of data, the CPU asserts an
XFER GRANT signal to the CSR. The XFER GRANT input resets the PORT XFER REQ
output. When the PORT XFER REQ output is reset, the microcontroller changes the FIFO
selected and monitors the CRDY output of the CSR. If the write check function is to be
continued, the CRDY output of the CSR will have remained cleared, and the microcontrotler
will increment the read/write data address contained in the disk address register and resct
the function timer. Then the microcontroller checks the DRIVE RDY input. If the sclected
RLO2 disk drive is operational, the microcontroller reinitiates the RLO2 write check function
to compare the next sector of data from the selected RLO2 disk drive with the data containced
in the selected FIFO.

If the write check function is not to be continued, the CPU responds to the PORT XFLR
REQ input by loading an IDC control word with CRDY set and then asserting XFER
GRANT. The XFER GRANT input to the IDC rescts the PORT XFER REQ signal. When
the PORT XFER REQ signal is reset, the microcontroller monitors the CRDY output of the
CSR. If the CRDY output is sct, the microcontroller sets the CRDY output of the CSR and,
if the 1E bit of the previous IDC control word was set, generates and asserts a UBUS BRS
signal to the CPU. The IDC then returns to the idle mode of the operation.
3.4.5.2 RS0 Write Data, Read Data, and Write Check - When a R80 write data, read data, or wriie
check function is specified by the 1DC control word, the microcontroller branches on the FO, F1, and
F2 inputs to preset the microcontroller microword output. The microcontroller then selects FIFO A and
resets the FIFO A address counter. Next the microcontroller checks the DRIVE RDY input to deterif the disk drive is ready (the R80 disk drive is operational and not busy performing a seck). If the
mine
DRIVE RDY input is present or when it is asserted, thc microcontroller enables the R80 SERVO
CLOCK to be asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock
control. This synchronizes the operation of the IDC with the R80 disk drive. (A detailed discussion of
the clock control is provided in Paragraph 3.5.3.)

The microcontroller then loops until the lcading edge of the SYNC SECTOR PLS is detected. This

pulsc is generated by the R80 SECTOR PLS or R80 INDEX PLS inputs from the R80 disk drive.

Presence of the SYNC SECTOR PLS indicates that the applicable read/write head of the R80 disk
drive is positioned at the beginning portion of the header data. After the leading edge of the SYNC
SECTOR PLS is detected, the microcontroller loops until 60 R8O SERVO CLOCK pulses have been
asserted. This microcontroller loop is initiated to prevent the R80 disk drive from trying to achicve
phasc lock on data that may contain glitches. After the loop, the microcontroller enables the TAG bus
control to assert the READ TAG and CNTL TAG signals to the R80 drivers. These signals cnable the
R80 drivers to assert the R80 TAG BUS 01 and R80 TAG 3 outputs of the IDC (assert a read gate
command to the R80 disk drive). The read gate command cnables the R80 disk drive to read the data
from the disk and assert the data to the IDC via the R80 READ DATA signal linc: The R80 disk drive
also generates and asserts the R80 READ CLOCK, which is synchronized with the READ DATA input to the IDC.

After the rcad gate command has been asserted, the microcontroller clears the ECC/CRC logic, cicars

the MISMATCH output of the header/data comparator, and then loops until after 88 R80 SERVO

CLOCK pulses have been asserted to the IDC. This loop is initiated to allow time for the R30 disk
drive to achieve phase lock on the data being read from the disk. Phase lock is achieved by rcading a
sequence of zeros in the sector gap of the R80 READ DATA. (Sec Figure 2-17 for the R80 READ
DATA format.)

After the loop for phase lock, the microcontroller presets the conditions for locating the header sync
bytc of the R80 READ DATA. The microcontroller also conditions the serializer such that after the
sync byte has been located, the address portion of the R80 READ DATA input can be compared with
the read /write data address contained in the disk address register.
3-24

To presct the conditions for locating the header sync byte, the microcontroller clears the data shift
register and presets the CONSTANTS output of the microcontroller to the header sync byte pattern.
Then the microcontroller selects the R80 READ CLOCK for synchronization. The R80 READ

CLOCK is generated within the R80 disk drive from the R80 READ DATA input and thus synchro-

nizes the IDC with the selected R80 disk drive data rate.

When the microcontroller selects the R80 READ CLOCK, the R80 READ CLOCK is asserted on the

CURRENT CLOCK output of the clock control. The R80 READ CLOCK is not asserted on the
SEQUENCE CLOCK output of the clock control until the sync byte has been found (when SYNC
SEEN from the header/data comparator is asserted to the clock control). Thus, the microcontroller is
forced to stall until the R80 header sync byte has been found. (A detailed discussion of how the sync
byte is located 1s provided in Paragraph 3.5.4.)
When the R80 READ DATA header sync byte is found, the SYNC SEEN output of the header/data

comparator is asserted to the clock control to enable the R80 READ CLOCK to be asserted on the
SEQUENCE CLOCK output. This restarts the microcontroller, which enables the ECC/CRC logic.
The SYNC SEEN signal is also asserted to the serializer to enable the contents of the disk address
register to be asserted to the header/data comparator, where it is compared bit-by-bit with the address

information of the R80 READ DATA.
The format of the R80 read/write data address contained in the disk address register is not the same as
the format of the address information contained in the header of the R80 READ DATA input. In addition to address information, the header of the R80 READ DATA input contains unused bits, various

flags, and skip sector information. During the R80 read/write address comparison, the serializer per-

forms three functions:
1.

Modifying the READ DATA input to mask the unused and various flag bits containedin the

hcader of the READ DATA input order of each of the bits
Controlling assertion order of each of the bits of the read/write data address contained in the
disk address register to enable these bits to be compared with the corresponding bits of the
READ DATA input

Recording, if enabled, the status of the skip sector flag in the header of the READ DATA
input

The header/data comparator performs a bit-by-bit comparison of the MODIFIED READ DATA input
with the SERIAL DAR output of the serializer to determine if the MODIFIED READ DATA match-

cs the read/write data address contained in the disk address register. (A detailed discussion of the R80
header data comparison including monitoring for the skip sector flag is provided in Paragraph 3.5.6.)
Each bit of the R80 header data asserted to the data synchronizer is asserted also to the SERIAL
DATA IN input of the NRZ data formatter. The NRZ data formatter couples the SERIAL DATA IN

to the ECC/CRC logic via the NRZ data bus. The ECC/CRC logic generates a CRC word based on
the configuration of the 32 bits of the R80 header data.
After all 32 bits of the R80 header data have been compared, the microcontroller turns off the seriali-

zer and monitors the MISMATCH output of the header/data comparator. If the MISMATCH output

is low (the address information of the R80 header data did not match the read/write data address in the
disk address register), the microcontroller enables the R80 SERVO CLOCK to be asserted on the
CURRENT CLOCK and SEQUENCE clock outputs of the clock control. Then the microcontroller
loops until the next sector is encountered (the next SYNC SECTOR PLS is asserted) before reinitiating the header data comparison. This process is repeated until a match is found or until TIMEOUT
occurs. (A detailed discussion of the timeout logic is provided in Paragraph 3.5.10.)
3-25

ed the
n of the R80 header data match
t is high (the address informatio
If the MISMATCH outputhe
output
SSE
the
ors
monit
then
oller
rcad/writc data address in disk address rcgister), the microcontr
of the serializer.
SSE bit of the IDC control
R80 header data was set and the orINH
If the skip scctor flag (SSE) of the
aced sector, the serializer
displ
read is a bad
word is not asserted, indicating that the sector being
controller.
asserts a skip sector error (SSE) signal to the micro

t of the CSR and increments
microcontroller sets the SSE outpusecto
If a skip scctor error is indicated, the
may be encountered per
bad
one
the disk address register. (Only be flagged rbecau
the sector address contained in follow
it will have been
ing the bad sector will also each cylinder;setheref
cylinder; however, each sector onal sector
ore, if a bad
on
ded
(Sector 31) is provi
displaced. Provision for an additi d.on the curre
monitoring
t
inhibi
can
ler
ontrol
microc
the
nt cylinder,
or displaced sector is encountere g the remainder
system
ding
degra
ut
witho
ion
funct
nt
curre
of the
for further skip sector flags durin
ed before
performance.) Then the microcontroller loops until the. next SYNC SECTOR PLS is assert
reinitiating the header data comparison.

ontroller then cnables the
bad or displaced sector, the microc
If the sector being read is not aword
header CRC is loaded,
the R80 header data. After the R80word
ECC/CRC logic to load the CRC ECC/ofCRC
generated by the
to compare the CRC
the microcontroller enables the r data withlogic
the R80 header CRC word.
ECC/CRC logic from the R80 heade

cts the R80 READ
CRC logic, the microcontroller deseleCK
If a CRC error is indicated by the ECC/
and CURRENT
to be asserted on the SEQUENCE CLO
CLOCK and enables the P2 CLOlCK
with the CPU. Then the
to synchronize the operation of the IDC bit
CLOCK outputs of the clock controIncom
CSR. Next, if
plete (OPI) bit and sets the CRDY tes inandtheassert
microcontroller sets the Operation l word
s a UBUS
was set, the microcontroller genera
the IE bit of the previous IDC contro
BR5 interrupt to the CPU.

on the FO,
ler clears the ECC/CRC logic and branches
If no CRC error is detected, the microcontrol
ated with the R80 write
input to initiate the operations associon.
F1, and F2 bits of the IDC control wordfuncti
on, or the R80 write check functi

data function, the R80 READ DATA
a.

R80 Write Data

CRC pattern verified, the microcontroller
After the proper sector has been located and the
ed on the CURRENT CLOCK and
selects the R80 SERVO CLOCK to be assert
the microcontroller checks to make
Next
SEQUENCE CLOCK outputs of the clock control. loaded
into the FIFO (FIFO MAX is
certain that the data to be written to the disk were
the CPU, the microcontroller
by
filled
not
asserted to the microcontroller). If the FIFO was
K and SEQUENCE
ENT
CURR
enables the P2 CLOCK to be asserted on the Late (DLT) CLOC
CRDY bits in the
and
error
CLOCK outputs of the clock control, sets the Data /data comparator, and,
if the IE bit of
CSR, clears the MISMATCH output of the header
signal to the
BRS5
UBUS
a
asserts
and
tes
the previous IDC control word was set, genera
CPU.

3-26

If the FIFO is full, the IDC continues with the write data function. First, the microcontroller
disables the read gate signal output of the TAG bus control, which deasserts the READ
GATE signal from the R80 disk drive. Then, after a loop, the microcontroller enables the
TAG bus control to assert a write gate command to the R80 disk drive. The microcontroller
also clears the FIFO address counter and clears the data shift register. Then the microcontroller again loops until 120 bits of zeros (header gap) have been written to the R80 disk
drive. (The zeros are written by holding the R80 WRITE DATA output of the NRZ data
formatter low.) When the last bit of the header gap is written, the microcontroller generates
and enables the CONSTANTS from the microcontroller to be loaded into the data shift register. (The CONSTANTS specify the sync byte pattern to be written in the R80 header gap,
that is, 19;6.) Then, the microcontroller enables the NRZ data formatter and asserts serially
the sync byte data from the data shift register to the NRZ data formatter. The NRZ data
formatter samples the DSRO output of the data shift register and generates an NRZ formatted pulse train that is asserted on the R80 WRITE DATA signal line and to the
ECC/CRC logic via the NRZ data bus.

After the last bit of the sync byte has been asserted to the NRZ data formatter, the microcontroller enables the first byte of data from FIFO A to be loaded into the data shift register
and increments the FIFO A address counter. At the same time, the microcontroller enables
the ECC/CRC logic, which samples the bit configuration of the 512 bytes of data as they are
being transferred to the disk drive and generates a 32-bit ECC word representative of the bit
configuration.

After the first byte of data has been loaded, the data shift register serializes and asserts bits 0
through 7 of the first data byte to the NRZ data formatter. After bit 7 of the first data byte
has been asserted to the NRZ data formatter, the second byte of data from FIFO A is loaded
into the data shift register and the FIFO A address counter is incremented. After bit 7 of the
second data byte has been asserted to the NRZ data formatter, the third data byte from
FIFO A is loaded into the data shift register and the FIFO A address counter is incremented.
This process is repeated until all 512 bytes of data from FIFO A have been loaded into the
data shift register and asserted to the R80 WRITE DATA input of the R80 disk drive via the
NRZ data formatter. (A detailed discussion of how the microcontroller causes the transfer of
data from the data buffers to the data shift register and data shift register operation in serializing the data is provided in Paragraph 3.5.11.)

After the 512 bytes of data from the FIFO have been asserted on the R80 WRITE DATA
signal line (the FIFO A address counter has been incremented to its maximum count), FIFO
MAX is asserted to the microcontroller. When FIFO MAX is asserted, the microcontroller
enables the ECC/CRC logic to assert serially the 32-bit ECC word derived from the bit configuration of the 512 bytes of data asserted on the R80 WRITE DATA signal line via the
NRZ data bus.

After the last bit of the ECC word is asserted, the microcontroller inhibits the ECC/CRC,
holds the WRITE GATE output of the TAG bus control logic asserted to the R80 disk drive
and the NRZ data formatter enabled until 16 zeros have been written to the data gap. After
the 16 zeros have been written, the microcontroller inhibits the TAG bus control, which deasserts the WRITE GATE signal from the R80 disk drive. The microcontroller then enables
the P2 CLOCK to be asserted on the SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock control, which synchronizes IDC operation with the CPU. Next the microcontroller clears the FIFO A address counter and enables the PORT XFER REQ output of
the CSR to be asserted to the CPU.

3-27

If more data are to be written, the CPU asserts XFER GRANT to the CSR. The XFER
GRANT input resets the PORT XFER REQ output of the CSR, which causes the microcontroller to sclect FIFO B and then monitor
the CRDY output of the CSR. If more data are
to be transferred, the CRDY output of the CSR will have remained cleared and the microcontroller will then increment the read/write data address in the disk address register and
resct the function timer. Then the microcontroller checks the DRIVE RDY input. If the R80
disk drive is operational, the microcontroller reinitiates the R80 write data function to causc
the transfer of the data contained in FIFO B to the next sector of the R80 disk drive.
If no more data are to be written, the CPU responds to the PORT XFER REQ input by
loading an 1DC control word with CRDY set and then asserting XFER GRANT. The XFER
GRANT input to the IDC resets the PORT XFER REQ signal. When the PORT XFER
REQ signal is reset, the microcontroller monitors the CRDY output of the CSR. If the
CRDY output is set, indicating that no more data are to be transferred, the microcontroller
sets the CRDY output of the CSR and, if the IE bit of the previous IDC control word was
set, generates and asserts a UBUS BRS signal to the CPU. The IDC then returns to the idle
mode of operation.
R80 Read Data

After the proper sector has been located and the CRC pattern verified, the microcontroller
selects the R80 SERVO CLOCK to be asserted on the SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock control. Then the microcontroller checks to make certain that the FIFO is empty. If the FIFO is full (FIFO MAX is asserted to the microcontroller), the microcontroller clears the MISMATCH output of the header/data
comparator and sets the CRDY and Data Late (DLT) error bits in the CSR. If the IE bit of
the previous IDC control word was set, the microcontroller also generates and asserts a
UBUS BRS5 signal to the CPU. The IDC then returns to the idle mode of operation.
If the FIFO is empty, the microcontroller causes the TAG bus control to deassert the read
gate command from the R80 disk drive. The microcontroller then loops until the write splice
area within the header gap has passed the read/write heads of the R80 disk drive. Then the
microcontroller enables the TAG bus control to reassert the read gate command to the R80
disk drive. Next the microcontroller clears the ECC/CRC logic.
After the read gate command is asserted to the R80 disk drive, the microcontroller loops
until 88 R80 SERVO CLOCK pulses have been asserted to the IDC. This loop is initiated to
allow the R80 disk drive to achieve phase lock on the data being read from the disk. After the
phase lock loop, the microcontroller clears the selected FIFO address counter, and presets
and asserts the CONSTANTS output of the microcontroller to the header/data comparator.
(The CONSTANTS output is preset to the bit configuration of the R80 READ DATA header gap sync byte, that is, 19,¢.) The microcontroller then enables the R80 READ CLOCK to
be asserted on the CURRENT CLOCK output of the clock control. The R80 READ
CLOCK is not asserted on the SEQUENCE CLOCK output of the clock control until the
sync byte has been found (when SYNC SEEN from the header/data comparator is asserted
to the clock control). Thus, the microcontroller is forced to stall until the R80 header gap
sync byte has been found. (A detailed discussion of how the sync byte is found is provided in
Paragraph 3.5.4.)
Detection of the sync byte of the R80 header gap signals the start of the data segment of the
sector to be read. When the R80 header gap sync byte has been found, the SYNC SEEN
output of the header/data comparator is asserted to the clock control to enable the R80
READ CLOCK to be asserted onto the SEQUENCE CLOCK output. This restarts the microcontroller, which then enables the ECC/CRC logic, and begins converting the R80
READ DATA into byte format and storing the 512 bytes of R80 READ DATA into the
selected FIFO.
3-28

After the data shift register has been loaded with the first eight bits of R80 READ DATA,
the microcontroller enables the parallel output of the data shift register to be asserted to the
input of the FIFO(s) via the READ DATA tristate drivers, loads the data byte into the seiccted FIFO, and increments the selected FIFO address counter. This process (converting the
R80 READ DATA to byte format and storing each byte) is repeated until all 512 bytes of
R80 READ DATA have been written into the selected FIFO. (A detailed discussion of how
thc READ DATA are converted to byte format and stored in the data buffer is provided in
Paragraph 3.5.12.)

Each bit of the 512 bytes of R80 READ DATA is used in the ECC/CRC logic to generate a
32-bit ECC word representative of the bit configuration of the R80 READ DATA. After all

512 bytes of R80 READ DATA have been loaded into the selected FIFO (FIFO MAX is

asserted to the microcontroller), the microcontroller enables the 32-bit ECC word from the
R 80 disk drive to be loaded into the ECC/CRC logic. After the ECC word has been loaded,
the microcontroller enables the ECC/CRC logic to compare the ECC word generated from
the 512 bytes of R80 READ DATA with the ECC word read from the disk. Then the microcontroller clears the FIFO address counter and monitors the CRC/ECC ERROR signal output of the ECC/CRC logic.

If a CRC/ECC error is indicated, the microcontroller initiates an ECC correction routine.
At the completion of the correction routine, the results of the correction computation are
indicated in the STAT 0 and STAT 1 signals that are asserted to the status logic of the CSR.
On completion of the correction computation, the microcontroller deselects the R80 READ
CLOCK and enables the P2 CLOCK to be asserted on the SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock control. Then the microcontroller clears the selected
FIFO address counter, sets the CRDY output of the CSR, and, if the IE bit of the previous
IDC control word was set, generates and asserts a UBUS BRS signal to the CPU. The 1DC
then returns to the idle mode of operation.

If no CRC/ECC ERROR is indicated, the microcontroller deselects the R80 READ
CLOCK and enables the P2 CLOCK to be asserted on the SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock control. This synchronizes the IDC with the CPU. Then
the microcontroller generates and asserts the PORT XFER REQ output of the CSR to the
CPU. This signal signifies that the IDC has completed reading one sector of data and that
the data are ready for transfer to the CPU.

If more data are to be read, the CPU asserts an XFER GRANT signal to the CSR. When
the XFER GRANT signal is asserted, it resets the PORT XFER REQ output. When the
PORT XFER REQ is reset, the microcontroller changes the FIFO selected and monitors the

CRDY output of the CSR. If more data are to be read, the CRDY output of the CSR will
have remained cleared, and the microcontroller will increment the read/write data address in
the disk address register and reset the function timer. Then the microcontroller checks the
DRIVE RDY input. If the R80 disk drive is operational, the microcontroller reinitiates the
R80 READ DATA function to read the next sector of data from the R80 disk drive and store
the data in the selected FIFO.

If no further data are to be read. the CPU responds to the PORT XFER REQ input by loading an IDC control word with CRDY set and then asserting XFER GRANT. The XFER
GRANT input to the IDC resets the PORT XFER REQ signal. When the PORT XFER
REQ signal is reset, the microcontroller monitors the CRDY output of the CSR. If the
CRDY output is sct, the microcontroller sets the CRDY output of the CSR and. if the IE bt
of the previous 1DC control word was set, gencrates and asserts a UBUS BRS signal to the

I
C

CPU. The IDC then returns to the idle mode of operation.

R80 Write Check

After the proper sector has been located and the CRC pattern verified, the microcontroller
checks to make certain that the data to be compared with the data from the disk drive were
loaded into the FIFO (FIFO OVFLW is asserted to the microcontroller).

If the FIFO was not filled by the CPU, the microcontroller enables the P2 CLOCK to be
asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control. Then the microcontroller sets the Data Late (DLT) error and CRDY bits in the CSR,
clears the MISMATCH output of the header/data comparator, and, if the 1E bit of the previous I1DC control word was set, generates and asserts a UBUS BRS signal to the CPU.
If the FIFO is full, the IDC continues with the write check function. First, the microcontroller selects the R80 SERVO CLOCK to be asserted on the CURRENT CLOCK and
SEQUENCE CLOCK outputs of the clock control. Next, the microcentroller disables the
READ GATE signal output of the TAG bus control, which deasserts the READ GATE signal from the R80 disk drive. The READ GATE signal is deasserted to disable the R80 disk
drive read circuitry from being triggered by data glitches at the beginning of the header gap.
(The data glitches were produced when the write heads were first turned on when the header
gap was written.) Then, after a loop to allow the read /write heads of the R80 disk drive to be
positioned over the valid data in the header gap, the microcontroller enables the TAG bus
control to reassert the read gate to the R80 disk drive. After the read gate command is asserted, the microcontroller loops until 88 R80 SERVO CLOCK pulses have been asserted to
the IDC. This loop is initiated to allow the R80 disk drive to again achieve phase lock on the
data being read from the disk. After the phase lock loop, the microcontroller clears the FIFO
address counter and enables the first byte of data from the selected data buffer to be asserted
to the data shift register. The microcontroller also clears the MISMATCH output of the
header/data comparator, and presets and enables the CONSTANTS from the micro-

controller to be asserted to the header/data comparator. (The CONSTANTS output is preset to the bit configuration of the R80 READ DATA header gap sync byte, that is, 19¢.)
The microcontroller then enables the R80 READ CLOCK to be asserted on the CURRENT
CLOCK output of the clock control. The R80 READ CLOCK is not asserted on the
'SEQUENCE CLOCK output of the clock control until the sync byte has been found (when
'SYNC SEEN from the header/data comparator is asserted to the clock control). Thus, the
microcontroller is forced to stall until the R80 READ DATA header gap sync byte has been
found. (A detailed discussion of how the sync byte is found is provided in Paragraph 3.5.4.)
Detection of the R80 READ DATA header gap sync byte signals the start of the datc segment of the sector on which the write check is to be performed. When the header gap sync
byte has been found, the SYNC SEEN output of the header/data comparator is asserted to
the clock control to enable the R80 READ CLOCK to be asserted on the SEQUENCE
CLOCK output. This restarts the microcontroller, which then enables the ECC/CRC logic.
In the write check mode, the WRT CHK LOAD output of the header/data comparator is
also enabled when the R80 READ DATA header gap sync byte is found. The WRT CHK
LOAD signal is asserted to the data shift register where it enables the first data byte from
the selected FIFO to be loaded into the data shift register. The microcontroller then increments the selected FIFO address counter.

3-30

When the first data byte is loaded into the data shift register, bit O of the first data byte is

asserted to the header/data comparator via the DSRO output of the data shift register. The
first bit of the first data byte is asserted to the header/data comparator coincident with the
first bit of the data portion of the R80 READ DATA asserted from the disk drive. (Because
the CURRENT CLOCK used by the data shift register is derived from the R80 READ
CLOCK input, the data loaded into the data shift register is serialized and asserted to the
header/data comparator in sync with each bit of the R80 READ DATA input.) The data shift register serializes and asserts bits 0 through 7 of the first data byte to the header/data
comparator.

After bit 7 of the first data byte has been asserted to the header/data comparator, the micro-

controller loads the second byte of data from the selected FIFO into the data shift register
and increments the selected FIFO address counter.
After bit 7 of the second data byte has been serialized and asserted to the header/data com-

parator, the microcontroller loads the third data byte from the selected FIFO into the data
shift register and increments the FIFO A address counter. This process is repeated until all

512 bytes of data from the selected FIFO have been serialized and asserted to the header/data comparator for comparison with the data portion of the R80 READ DATA input. (A
detailed discussion of how the microcontroller causes serialization of data from the data buffers is provided in Paragraph 3.5.11.)

The header/data comparator performs a bit-by-bit comparison of the data portion of the R80
READ DATA input with the DSRO input to determine if the data stored on the disk match
the serialized data from the data shift register.
Each bit of the data asserted to the header/data comparator for comparison with the R80
READ DATA is asserted also to the ECC/CRC logic via the NRZ data formatter and NRZ
data bus. The ECC/CRC logic generates a 32-bit ECC word based on the configuration of
the 4096 data bits asserted to the ECC/CRC logic via the DSRO input to the NRZ data
formatter.

After the 512 bytes of data from the FIFO have been serialized and asserted to the header/data comparator for comparison with the data portion of the R80 READ DATA input
and to the ECC/CRC logic for generation of a 32-bit ECC word, (the FIFO A address
counter has been incremented to its maximum count, FIFO MAX is asserted to the microcontroller), the microcontroller strobes the header data comparator to sample the results of
the data comparison and enables the ECC/CRC logic to load the 32-bit ECC word of the
R80 READ DATA input. If the data did not compare, the MISMATCH output of the header/data comparator will be low. If the data from the data buffer matched the data portion of
the R80 READ DATA, the MISMATCH output will be high. The MISMATCH output is
asserted to the status logic in the CSR and to the microcontroller. After the ECC word has
been loaded, the microcontroller enables the ECC/CRC logic to compare the two ECC
words (the ECC word generated from the 4096 bits of data used for comparison with the
4096 bits of R80 READ DATA with the ECC word read from the disk drive). Also, the
microcontroller enables the P2 CLOCK to be asserted on the CURRENT CLOCK and
SEQUENCE CLOCK outputs of the clock control to synchronize IDC operation with the
CPU.

3-31

If an ECC comparison error is indicated (the ECC/CRC ERROR signal is asserted to the
microcontroller and CSR), the microcontroller sets the CRDY output of the CSR and, if the
IE bit of the previous IDC control word was set, generates and asserts a UBUS BRS5 to signal
the CPU. Then the IDC rcturns to the idle mode of operation. [Note that if the results of the
data comparison (the 4096 bits of R80 READ DATA with the 4096 bits of data from the
FIFO) did not match, then an ECC error will also occur. Therefore, it is not necessary to

terminate the write check function when a data comparison error is detected. However, if the

write check function is terminated by an ECC error, the CPU can determine if the error was
ECC related or a data comparison error by reading the IDC staus word. The results of the

data comparison (MISMATCH) and ECC comparison (CRC/ECC ERROR) are made

available to the CPU via the IDC status logic.]

If no ECC comparison error is indicated, the microcontroller clears the selected FIFO address counter and enables the PORT XFER REQ output of the CSR to be asserted to the
CPU. The PORT XFER REQ signal signifies to the CPU that the write check function has
been performed on the requested sector of data and that the data comparison was valid.
If the write check function is to be performed on the next sector of data, the CPU asserts an
XFER GRANT signal to the CSR. The XFER GRANT input resets the PORT XFER REQ
output. When the PORT XFER REQ output is reset, the microcontroller changes the FIFO
selected and monitors the CRDY output of the CSR. If the write check function is to be
continued, the CRDY output of the CSR will have remained cleared, and the microcontroller
will increment the read/write data address in the disk address register and reset the function
timer. Then the microcontroller checks the DRIVE RDY input. If the R80 disk drive is operational, the microcontroller reinitiates the R80 write check function to compare the next sector of the data from the R80 disk drive with the data contained in the selected FIFO.

If no further data are to be read, the CPU responds to the PORT XFER REQ input by loading an IDC control word with CRDY set and then asserting XFER GRANT. The XFER
GRANT input to the IDC resets the PORT XFER REQ signal. When the PORT XFER
REQ signal is reset, the microcontroller monitors the CRDY output of the CSR. If the
CRDY output is set, the microcontroller sets the CRDY output of the CSR and, if the IE bit
of the previous IDC control word was set, generates and asserts a UBUS BR5 signal to the
CPU. The IDC then returns to the idle mode of operation.

3.4.6

Read Data Without Header Check

The read data without header check function specified in Table 3-1 may be initiated by the CPU by
loading the CSR with the applicable IDC control word. Since the operational sequence of the I1DC in
performing the read data without header check function depends on whether an RLO2 or R80 disk
drive is selected, the read data without header check functions are discussed separately as follows.

'3.4.6.1 RLO2 Read Data Without Header Check — When an RLO2 read data without header check
function is specified in the IDC control word, the microcontroller branches on the FO, F1, and F2 inputs
to preset the microcontroller microword output. The microcontroller then selects FIFO A and resets the
FIFO A address counter. Next the microcontroller checks the DRIVE RDY input to determine if the selected disk drive is ready (the disk drive is operational and not busy performing a seek function). If
the DRIVE RDY input is present or when it is asserted, the microcontroller enables the RL SYSTEM
CLOCK (4.1 megahertz) to be asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control. This synchronizes the IDC operation with the selected RLO2 disk drive.
The microcontroller then loops until the leading edge of the SYNC SECTOR PLS is detected. This
pulse is generated by the RL SECTOR PLS input from the RLO2 disk drive. Presence of the SYNC
SECTOR PLS indicates that the applicable read/write head of the RLO2 disk drive is positioned at the
3-32

beginning portion of a data sector. After the leading edge of the SYNC SECTOR PLS is detected, the
microcontroller loops until the trailing edge of the SYNC SECTOR PLS is detected. Then the microcontroller loops until 32 RL SYSTEM CLOCK (4.1 megahertz) pulses have been asserted to the microcontroller via the SEQUENCE CLOCK output of the clock control. This second microcontroller

loop is inititated to prevent the read data separator from trying to achieve phase lock on data that may
contain glitches. After the loop, the microcontroller enables the read data separator and then loops until
after 32 RL SYSTEM CLOCK (4.1 megahertz) pulses have been asserted to the microcontroller via
the SEQUENCE CLOCK output of the clock control. This loop is initiated to allow time for the read
data separator to achieve phase lock on the data being read from the disk (RL READ DATA input).
Phasc lock is achieved by reading a sequence of four bytes of zeros in the header preamble of the RL
READ DATA. (Sec Figure 2-20 for the RL READ DATA format.)
After the loop for phase lock, the microcontroller presets the conditions for locating the header sync
byte of the RL READ DATA.
To preset the conditions for locating the header sync byte, the microcontroller clears the data shift

register and presets the CONSTANTS output of the microcontroller to the header sync byte pattern.
Then the microcontroller selects the DS CLOCK for synchronization. The DS CLOCK is generated

from thce RL READ DATA input and thus synchronizes the IDC with the selected RL0O2 disk drive
data ratc. When the DS CLOCK from the read data separator is selected, the DS CLOCK is asserted

on the CURRENT CLOCK output of the clock control.

The DS CLOCK is not asserted on the SEQUENCE CLOCK output of the clock control until the sync
byte has becn found (when SYNC SEEN from the header/data comparator is asserted to the clock
control). Thus, the microcontroller is forced to stall until the header sync byte has been found. (A detailed discussion of how the header sync byte is located is provided in Paragraph 3.5.4.)
When the RL READ DATA header sync byte is tound, the SYNC SEEN output of the header/data

comparator is asserted to the clock control to enable the DS CLOCK to be asserted on the
SEQUENCE CLOCK output. This restarts the microcontroller, which then loops until the 48 bits com-

prising the address information, the 16 bits of the zeros that follow, and the CRC word of the RLO2
header portion of the RL READ DATA have been bypassed.
After the header portion of the RL READ DATA has been bypassed, the microcontroller checks to
make certain that the selected FIFO is empty. If the FIFO is full (FIFO MAX is asserted to the microcontroller), the microcontroller clears the MISMATCH output of the header/data comparator and sets
the CRDY and Data Late (DLT) error bits in the CSR. If the IE bit of the previous IDC control word
was set, the microcontroller also generates and asserts a UBUS BRS signal to the CPU. The IDC then
returns to the idle mode of operation.
If the FIFO is empty, the microcontroller deselects the DS CLOCK and enables the RL SYSTEM
CLOCK (4.1 megahertz) to be asserted on the SEQUENCE CLOCK and CURRENT CLOCK outputs of the clock control. The microcontroller then loops until the write splice area within the header
gap of the RL READ DATA has passed the read/write heads of the RL02 disk drive. Then the microcontroller clears the ECC/CRC logic and enables the read data separator.
Next, the microcontroller loops until 32 RL READ DATA pulses have been asserted to the IDC. This
loop is initiated to allow the read data separator to achieve phase lock on the data being read from the
disk. After the phase lock loop, the microcontroller clears the selected FIFO address counter and presets and asserts the CONSTANTS output of the microcontroller to the header/data comparator. (The
CONSTANTS output is preset to the bit configuration of the RL READ DATA header preamble sync
byte.) The microcontroller then enables the DS CLOCK to be asserted on the CURRENT CLOCK
output of the clock control. The DS CLOCK is not asserted on the SEQUENCE CLOCK output of the

3-33

the header/data comparator
clock control until the sync byte has been found (when SYNC SEEN from
until the RL READ DATA
is asserted to the clock control). Thus, the microcontroller is forced to stall
header preamble sync byte has been found. (A detailed discussion of how the sync byte is located is
provided in Paragraph 3.5.4.)

segment of the sector to
Detection of the sync byte of the header preamble signals the start of the data
output of the headSEEN
be read. When the header preamble sync byte has been found, the SYNC
be asserted on the
to
er/data comparator is asserted to the clock control to enable the DS CLOCK
the ECC/CRC
enables
then
SEQUENCE CLOCK output. This restarts the microcontroller, which into byte format
and storinput
logic, and begins converting the data portion of the RL READ DATA
how the
of
on
discussi
detailed
(A
ing the 256 bytes of RL READ DATA into the selected FIFO.
ph
Paragra
in
provided
is
buffers
READ DATA are converted to byte format and stored in the data
3.5.12))

in the ECC/CRC logic to
Each bit of the 256 bytes of the data portion of the RL READ DATA is used
READ DATA. After all
RL
the
of
generate a 16-bit CRC word representative of the bit configuration
MAX is asserted to the
(FIFO
FIFO
256 bytes of RL READ DATA have been loaded into the selected
DATA input to be
READ
RL
the
of
word
microcontroller), the microcontroller enables the 16-bit CRC
roller enables the
microcont
the
loaded,
loaded into the ECC/CRC logic. After the CRC word has been
DATA with
READ
RL
of
bytes
256
the
ECC/CRC logic to compare the CRC word generated from
enables the
and
CLOCK
DS
the
deselects
the CRC word read from the disk. Next, the microcontroller
the clock
of
outputs
CLOCK
T
CURREN
P2 CLOCK to be asserted on the SEQUENCE CLOCK and
C
ECC/CR
the
of
output
signal
ERROR
C
control. Then, the microcontroller monitors the CRC/EC
logic.

if the IE
"1f a CRC/ECC error is indicated, the microcontroller sets the CRDY output of the CSR and,
CPU.
the
to
signal
BRS5
UBUS
a
asserts
and
bit of the previous IDC control word was set, generates
The IDC then returns to the idle mode of operation.

counter
If no CRC/ECC ERROR s indicated, the microcontroller clears the selected FIFO address signifies
signal
This
CPU.
the
to
CSR
the
of
and generates and asserts the PORT XFER REQ output
that the IDC has completed reading a sector of data and that the data are ready for transfer to the
CPU.

XFER
If more data are to be read, the CPU asserts a XFER GRANT signal to the CSR. When theREQ
is
XFER
PORT
the
When
reset.
is
output
REQ
GRANT signal is asserted, the PORT XFER
the
If
CSR.
the
of
output
CRDY
the
monitors
and
selected
reset, the microcontroller changes the FIFO
CRDY output of the CSR has remained cleared, the microcontroller resets the function timer, and
reinitiates the RLO2 read data without header check function to read the next sector of RL READ
DATA and store the data portion in the selected FIFO.

the CRDY output of the CSR and, if the IE bit of the previous IDC control word was set, generates
and asserts a UBUS BRS5 signal to the CPU. The IDC then returns to the idle mode of operation.

3.4.6.2 RS0 Read Data Without Header Check - When an R80 read data without header check function is specified by the IDC control word, the microcontroller branches on the FO0, F1, and F2 inputs to
preset the microcontroller microword output. The microcontroller then selects FIFO A and resets the
FIFO A address counter. Next, the microcontroller checks the DRIVE RDY input to determine if the
3-34

disk drive is ready (the R80 disk drive is operational and

not busy performing a seek). If the DRIVE
troller enables the R80 SERVO CLOCK to

RDY input is present or when it is asserted, the microcon

be asserted on the CURRENT CLOCK and SEQUENCE
CLOCK outputs of the clock control. This
synchronizes the operation of the IDC with the R80 disk drive.
The microcontroller then loops until the leading edge of the
SYNC SECTOR PLS is detected. This
pulsc is generated by the R80 SECTOR PLS or R80 INDEX
PLS inputs from the R80 disk drive.
Presence of the SYNC SECTOR PLS indicates that the applicabl
e read/write head of the R80 disk
drive is positioned at the beginning portion of the header data.
After the leading edge of the SYNC
SECTOR PLS is detected, the microcontroller loops until 60
R80 SERVO CLOCK pulses (9.677 megahertz) have been asserted. The microcontroller loop is initiated
to prevent the R80 disk drive from
trying to achieve phase lock on data that may contain glitches.
After the loop, the microcontroller enables the TAG bus control to assert the READ TAG and CNTL
TAG signals to the R80 drivers. These
signals enable the R80 drivers to assert the R80 TAG BUS
01 and R80 TAG 3 outputs of the IDC
(assert a read gate command to the R80 disk drive). The read
gate command enables the R80 disk drive
to read the data from the disk and assert the data to the IDC
via the R80 READ DATA signal line.
The R80 disk drive also generates and asserts the R80 READ
CLOCK, which is synchronized with the
READ DATA input to the IDC.

After the read gate command has been asserted, the microcont
roller loops until after 88 R80 SERVO
CLOCK pulses have been asserted to the IDC. This loop is
initiated to allow time for the R80 disk
drive to achieve phase lock on the data being read from the disk.
Phase lock is achieved by reading a
sequence of zeros in the sector gap of the R80 READ DATA.
(See Figure 2-17 for the R80 READ
DATA format.)
After the loop for phase lock, the microcontroller presets the
condition
bytc of the R§0 READ DATA.

s for locating the header sync

CLOCK is generated within the R80 disk drive from the R80 READ

DATA and thus synchronizes the
IDC with the R80 disk drive data rate. When the R80 READ CLOCK
is selected, the R80 READ
CLOCK is asserted on the CURRENT CLOCK output of the clock
control. The R80 READ CLOCK
is not asserted on the SEQUENCE CLOCK output of the clock
control until the sync byte has been
found (when SYNC SEEN from the header/data comparator is asserted to
the clock control). Thus,
the microcontroller is forced to stall until the R80 READ DATA
header sync byte has been found. (A
detailed discussion of how the sync byte is located is provided in Paragraph
3.5.4))

When the R80 READ DATA header sync byte is found, the SYNC SEEN

output of the header/data

comparator is asserted to the clock control to enable the R80 READ
CLOCK to be asserte
on
d the

SEQUENCE CLOCK output. This restarts the microcontroller, which then
prising the address information and CRC word of the header portion of

been bypassed.

loops until the 48 bits comthe R80 READ DATA have

After the header portion of the R80 READ DATA has been bypassed, the microcontro

ller selects the

R80 SERVO CLOCK to be asserted on the SEQUENCE CLOCK and CURREN

of the clock control. Then the microcontroller checks to make certain that

T CLOCK outputs

the FIFO is empty. If the
FIFO is full (FIFO MAX is asserted to the microcontroller), the microcontr
oller clears the MISMATCH output of the header/data comparator and sets the CRDY and
Data Late (DLT) error bits in
the CSR. If the IE bit of the previous IDC control word was set, the microcontr
oller also generates and
asserts a UBUS BRS signal to the CPU. The IDC then returns to the idle mode
of operation.

If the FIFO is empty, the microcontroller causes the TAG bus control to deassert the read gate command from the R80 disk drive. The microcontroller then loops until the write splice area within the
header gap has passed the read/write heads of the R80 disk drive. Then, the microcontroller enables
the tag bus control to reassert the read gate command to the R80 disk drive. Next the microcontroller
clears the ECC/CRC logic.

After the read gate command is asserted to the R80 disk drive, the microcontroller loops until 88 R80
SERVO CLOCK pulses have been asserted to the IDC. This loop is initiated to allow the R80 disk
drive to achieve phase lock on the data being read from the disk. After the phase lock loop, the microcontroller clears the selected FIFO address counter, and presets and asserts the CONSTANTS output
of the microcontroller to the header/data comparator. (The CONSTANTS output is preset to the bit
configuration of the R80 READ DATA header gap sync byte.) The microcontroller then enables the
R80 READ CLOCK to be asserted on the CURRENT CLOCK output of the clock control. The R80
READ CLOCK is not asserted on the SEQUENCE CLOCK output of the clock control until the R80
READ DATA header gap sync byte has been found (when SYNC SEEN from the header/data comparator is asserted to the clock control). Thus, the microcontroller is forced to stall until the R80
READ DATA header gap sync byte has been found. (A detailed discussion of how the sync byte is
found is provided in Paragraph 3.5.4.)

Detection of the R80 READ DATA header gap sync byte signals the start of the data segment of the
sector to be read. When the R80 READ DATA header gap sync byte has been found, the SYNC
SEEN output of the header/ data comparator is asserted to the clock control to enable the R80 READ
CLOCK to be asserted on the SEQUENCE CLOCK output. This restarts the microcontroller, which
then enables the ECC/CRC logic, and begins converting the data portion of the R80 READ DATA
into byte format and storing the 512 bytes of R80 READ DATA in the selected FIFO.
After the data shift register has been loaded with the first eight bits of R80 READ DATA, the microcontroller enables the parallel output of the data shift register to be asserted to the input of the FIFO(s)
via the read data tristate drivers, loads the data byte into the selected FIFO, and increments the selected FIFO address counter. This process (converting the R80 READ DATA to byte format and storing each byte) is repeated until all 512 bytes of the data portion of the R80 READ DATA have been
written into the selected FIFO. (A detailed discussion of how the READ DATA are converted to byte
format and stored in the data buffer is provided in Paragraph 3.5.12.)

Each bit of the 512 bytes of R80 READ DATA is used in the ECC/CRC logic to generate a 32-bit
ECC word representative of the bit configuration of the data portion of the R80 READ DATA. After
all 512 bytes of R80 READ DATA have been loaded into the selected FIFO (FIFO MAX is asserted to
the microcontroller), the microcontroller enables the 32-bit ECC word of the R80 READ DATA to be
loaded into the ECC/CRC logic. After the ECC word has been loaded, the microcontroller enables the
ECC/CRC logic to compare the ECC word generated from the 512 bytes of R80 READ DATA with
the ECC word read from the disk. Then the microcontroller clears the FIFO address counter and monitors the CRC/ECC ERROR signal output of the ECC/CRC logic.

If a CRC/ECC error is indicated, the microcontroller initiates an ECC correction routine. At the completion of the correction routine, the results of the correction computation are indicated in the STAT 0
and STAT 1 signals that are asserted to the status logic of the CSR. On completion of the correction
computation, the microcontroller deselects the R80 READ CLOCK and enables the P2 CLOCK to be
asserted on the SEQUENCE CLOCK and CURRENT clock outputs of the clock control. Then the
microcontroller clears the selected FIFO address counter, sets the CRDY output of the CSR, and, if
the IE bit of the previous IDC control word was set, generates and asserts a UBUS BRS signal to the
CPU. The IDC then returns to the idle mode of operation.

3-36

I no CRC/ECC ERROR is indicated, the microcontroller deselects the R80 READ CLOCK and enables the P2 CLOCK to be asserted on the SEQUENCE CLOCK and CURRENT CLOCK outputs of
the clock control. This synchronizes the IDC with the CPU. Then the microcontroller generates and
asscrts the PORT XFER REQ output of the CSR to the CPU. This signal signifies that the IDC has

completed reading one sector of data and that the data are ready for transfer to the CPU.

If morc data are to be read, the CPU asserts a XFER GRANT signal to the CSR. When the XFER
GRANT signal is asserted, it resets the PORT XFER REQ output. When the PORT XFER REQ is

- reset, the microcontroller changes the FIFO selected and monitors the CRDY output of the CSR. If
morc data are to be read, the CRDY output of the CSR will have remained cleared, and the microcontroller will reset the function timer and reinitiate the R80 read data without header check function
to read the next sector of data from the R80 disk drive and store the data in the selected FIFO.

If no further data are to be read, the CPU responds to thc PORT XFER REQ input by loading an IDC
control word with CRDY set and then asserting XFER GRANT. The XFER GRANT input to the
IDC resets the PORT XFER REQ signal. When the PORT XFER REQ signal is reset, the microcontroller monitors the CRDY output of the CSR. If the CRDY output is set, the microcontroller sets

the CRDY output of the CSR and, if the IE bit of the previous IDC control word was set, generates
and asserts a UBUS BRS signal to the CPU. The IDC then returns to the idle mode of operation.

3.47

Write Format

The write format is used only to format R80 disk drive hcaders. When the write format function is initiated, the IDC checks to make certain that the R80 disk drive is ready (that it is operational and not busy
performing a seck). If the R80 disk drive is rcady or when it becomes ready, the IDC waits until the R80
INDEX PLS from the R80 disk drive is detected (waits for the beginning of sector 0).
After the R80 INDEX PLS is detected, the IDC then
e

writes a sequence of zeros (224),

writes the header sync byte,

writes four bytes of header data from the data buffer,

writes the header CRC word, which was generated in the IDC from the header data written

to the disk drive,
e

writes a sequence of zeros (136),

writes the header gap sync byte,

writes a sequence of zeros (4096),

writes the ECC word which was generated in the IDC while the sequence of zeros (4096)

were being written, and
e

writes a sequence of zeros.

The IDC then waits for the leading edge of the next sector pulse. After the next sector pulse is de-

tected, the IDC repeats the write sequence just specified. This process is repeated until the R80 INDEX PLS is again detected. Then the IDC generates and asserts, if enabled, a UBUS BRS5 interrupt to
the CPU, which indicates that the specified function has been completed.

3-37

3.4.8

Idle Mode

The IDC idle mode of operation is entered automatically after the completion of a CPU-specified function. The IDC remains in the idle mode until another IDC function is specified by the CPU (the CRDY
L input to the microcontroller is set to a high). When the idle mode is entered, the microcontroller
generates and asserts the UDRV SEL 0, UDRV SEL 1, and UDRYV SEL signals to the CSR (see Figure 3-1). These signal inputs are used to generate the DRIVE SEL 0 and 1 signals, which select which
one of the disk drives is to be enabled. These signals also enable the operational status signal inputs
from the selected disk drive (RL DRIVE RDY, RL DRIVE ERR, R80 DRIVE RDY, R80 PLUG
VALID, R80 ON CYLINDER, and R80 FAULT) to control assertion of the DRIVE RDY and
DRIVE ERR signals to the microcontroller. (A detailed discussion of how the disk drives are selected
and the status signals are asserted to the microcontroller is provided in Paragraph 3.5.1.) The DRIVE
SEL 0 and 1 signals also enable the appropriate ONLINE signal output of the CSR to be asserted to
the microcontroller. (The ONLINE signal contained in the CSR is set and cleared by the microcontroller to provide a record of which drives are currently in use. A discussion of the ONLINE register contained in the CSR is provided in Paragraph 3.5.10.)

After the disk drive has been selected, the microcontroller branches on the DRIVE RDY, DRIVE
ERR, and ONLINE signals asserted and generates the control signals (USET ATTN L, USET ONLINE L, and UCLEAR ONLINE L) to record the disk drive status. The USET and UCLEAR ONLINE signals are asserted to the CSR to record the sampled disk drive status during the monitoring
period. The USET ATTN signal is asserted to the CSR to record that the enabled disk drive has
changed operational status (has gone off-line, has come back on-line, or is reporting an error). (A detailed discussion of the function of the ATTN and ONLINE registers contained in the CSR is provided
in Paragraph 3.5.10.)

After the operational status of the selected disk drive has been sampled and recorded, the microcontroller increments the address count (UDRYV SEL 0 and 1) and reasserts USEL DRYV to enable the
next disk drive. When the next disk drive is enabled, the microcontroller again branches on the DRIVE
ERR, DRIVE RDY, and ONLINE inputs and records the status of the enabled disk drive. After all
disk drives have been sampled, the microcontroller checks the CRDY L input from the CSR to determine if the CPU has requested the IDC to perform a function. If no function has been requested (the
CRDY L input is L), the microcontroller repeats the idle mode routine.
3.5

DETAILED FUNCTIONAL LOGIC DESCRIPTIONS

3.5.1 Disk Drive Selection and Drive Status Monitor
The disk drive selection and drive ready monitor logic is used to enable, if applicable, one of the RL02
disk drives, to condition the IDC logic for operation with either the R80 disk drive or an RLO2 disk
drive, and to monitor the status of the selected disk drive.
The RLO2 disk drives are connected to the IDC in a daisy chain. Each RLO2 disk drive is preprogrammed with a specific address by installing an address plug. Each RL02 disk drive is enabled by
the IDC by asserting the configuration of DRIVE SEL 0 and 1 bits which matches the preprogrammed

address. When an RLO2 disk drive is enabled, it asserts to the IDC its operational status information

(RL DRIVE RDY or RL DRIVE ERROR). The RL DRIVE RDY signal is only asserted if the selected disk drive is operational and is not busy performing a seek. When an RLO2 disk drive is enabled,
operational, and not performing a seek function, the selected RLO2 disk drive enables the read data
from the disk and the sector pulses to be asserted to the IDC via the RL READ DATA and RL SECTOR PLS signal lines.

3-38

The R80 disk drive is enabled at all times and continuously asserts its status information (including R80
ON CYLINDER and R80 DRIVE RDY or R80 FAULT), R80 SECTOR PLS, and R80 INDEX PLS
outputs to the IDC. Unlike the RLO2 disk drives, the R80 disk drive asserts its address information to
the IDC via the R80 SEL ADDRESS 0 and 1 signal lines. When the configuration of DRIVE SEL 0

and | bits match the address of the R80 disk drive, the IDC generates an R80 signal. The R80 signal
conditions the IDC logic for operation with the R80 disk drive. Again, unlike the RLO2 disk drives, the
R80 does not assert its READ DATA output to the IDC when it is selected. A separate command from
the IDC TAG bus control (read gate) must be asserted before the R80 READ DATA output is asserted
to the IDC.
A functional block diagram of the disk drive selection and drive ready monitor logic is presented in
Figure 3-2. Figure 3-2 shows the maximum number and configuration of disk drives that may be connected to the IDC: three RLO2 disk drives and one R80 disk drive, or four RL02 disk drives.
- The disk drive selection and drive status monitor generates the appropriate DRIVE SEL 0 and 1 signals
that are used to enable, if applicable, the appropriate RL02 disk drive, to control generation of the

RLO2 and R80 signals, and to enable the appropriate DRIVE RDY or DRIVE ERR input signal to be
asserted to the microcontroller.
3.5.1.1

Generation of DRIVE SEL 0 and 1 - When performing a CPU-specified function, the IDC

generates the DRIVE SEL 0 and 1 signals from bits 08 and 09 of the IDC control word input that is
loaded into the control register of the CSR. When the IDC is operating in the idle mode, the DRIVE
SEL 0 and I outputs are generated from the UDRV SEL, UDRV SEL 0, and UDRV SEL 1 outputs of
the microcontroller.
3.5.1.2

Generation of RL02 and R80 - If the configuration of DRIVE SEL 0 and 1 signals asserted to

the R80 address compare logic match the R80 SELECT ADDRESS 0 and 1 signals asserted from the

R80 disk drive, and if an R80 PLUG VALID signal is asserted (the R80 disk drive is installed as part
of the RB730 disk subsystem and an address plug is installed), the RL0O2 output will be a low. The
RLO2 output is inverted to produce the R80 signal. If the address does not compare or an R80 disk is
not installed, the RLO2 output will be high and the R80 signal will be low.
3.5.1.3

Gating DRIVE RDY - The RL02 output of the R80 address compare logic is used to enable
either the R80 DRIVE RDY or RL DRIVE RDY input to be asserted to the DRIVE RDY input of the
microcontroller.

3.5.1.4 Gating DRIVE ERR - The RL DRIVE ERROR or R80 FAULT output of the selected disk
drive is enabled on the DRIVE ERR output of the disk drive selection and drive status monitor by the
RLO2 output of the R80 address compare logic. The DRIVE ERR output is asserted to the IDC micro-

controller and to the IDC status logic.
3.5.2 TAG Bus Control Logic
The TAG bus control logic operates from microcontroller inputs to assert the following commands to
the R80 disk drive via the R80 TAG and R80 TAG BUS signal lines.
R80 seek
'R80 head select

R8O recalibrate

Read gate
Write gate

3-39

——
— ——
e
—_———————

[oc — — — — — —

R80 SELECT ADRS 0

R80 SELECT ADRS 1

R80 PLUG VALID

PART OF
CONTROL
REGISTER

D 1

PAL

ol | =

)
R80 Aoonesél
RLO
COMPARE

LOGIC

Ds1

R8O FAULT
RLO2

UDRV SEL 0

UDRV SEL

—_—

FROM

MICROCONTROLLER

UDRV SEL

DRIVE

STATUS

DRV ADY

> RLOZ H

# DRV ERR

| DRIVE |
|
——

———=
Ruzr |l
o DiSK

MICRO-

DRIVE RDY

TO STATUS
LOGIC

I DRIVE

RLO2

ORIVE

OLLER

CONTROL

DISK

_.I

DRIVE

—

DRV RDY

UDRV SEL 1
E

DRIVE ERR
0

DRV ERR

LOGIC

Oisk

RL DRIVE RDY
sEL 0|
DRIVE
DRIVE SEL 1 !

RECEIVERS RL DRIVE ERROF\{

Reo*

)

RLO2
of DRIVERS/

RL DRIVE ERROR

DRIVE SEL 1

TO RL02/R80 MUX'S,

- CLOCK CONTROL, AND

STATUS LOGIC

RL DRIVE RDY

\ ' ;
TO STATUS

RLOZ

DRIVE SEL 0

TO MICROCONTROLLER

SERIALIZER, AND DATA
BUFFER AND DATA REGISTER
CONTROL LOGIC

R8O

'
t
l

PART OF CONTROL STATUS REGISTER (CSR)

|
ov-t

{

R8O FAULT

BUS

)

RECEIVERS

R80 ON CYLINDER

=
o

I
|
I

R8O

R80 DRIVE RDY

J—_"]

Lof

“—=|

RLO?2

DISK

RLO2

Disk

DRiIVE

* MAXIMUM DISK DRIVE CONFIGURATION WHICH MAY BE CONNECTED TO I1DC
1S ON R80 DISK DRIVE AND UP TO THREE RLO2 DISK DRIVES: IF AN R80
DISK DRIVE 1S NOT USED, UP TO FOUR RLO2 DISK DRIVES MAY BE CONNECTED.
TX-738o

Figure 3-2

Disk Drive Selection and Drive Status Monitor

3.5.2.1

Asserting R80 Seek, Head Select, and Recalibrate Commands — When the appropriate R80

scek (Figure 2-5), R80 head select (Figure 2-6), or R80 recalibrate (Figure 2-7) command is loaded into
the IDC disk address register and an R80 seek function is specified by the IDC control word input, the
microcontroller controls gating of the appropriate command to the R80 disk drive. A functional block

diagram of the TAG bus control logic is shown in Figure 3-3.
To assert the appropriate seek, head select, or recalibrate command contained in the disk address register, the microcontroller asserts a USEEK INSTR signal and a UTAG STROBE signal to the TAG bus
control logic. Timing of the USEEK INSTR and UTAG STROBE inputs to the TAG bus control logic
is shown in Figure 3-3.

3.5.2.2

Asserting Read Gate — The read gate command input to the R80 disk drive is initiated by

holding the R80 TAG 3 input high and asserting the R80 TAG BUS 1 input. The read gate command is

terminated when the R80 TAG BUS 1 input is deasserted.
To initiate a read gate command, the microcontroller asserts a UTAG STROBE, which enables the
R80 TAG 3 output (see Figure 3-3). Next, the microcontroller asserts a UENB LOOP LOCK signal,
which enables the R80 TAG BUS 1 output. The microcontroller may terminate the read gate command
by deasserting the UENB LOOP LOCK input to the TAG bus control logic. Figure 3-2 shows the timing relationship of the UTAG STROBE and UENB LOOP LOCK input signals.
3.5.2.3 Asserting Write Gate — The write gate command input to the R80 disk drive is initiated by
holding the R80 TAG 3 input high and asserting the R80 TAG BUS 0 input. The write gate command
is terminated when the R80 TAG BUS 0 input is deasserted.
To initiate a write gate command, the microcontroller asserts a UTAG STROBE, which enables the
R80 TAG 3 output (see Figure 3-3). Next the microcontroller asserts a UWRITE GATE signal, which
enables the R80 TAG BUS 0 output. The microcontroller may terminate the write gate command by
deasserting the UWRITE GATE input to the tag bus control logic. Figure 3-2 shows the timing relationship of the UTAG STROBE and UWRITE GATE input signals.
3.5.3 Clock Control Logic
The clock control logic is used to synchronize operation of the IDC with the CPU, the R80 disk drive,
or the RLO2 disk drive, as applicable. It is also used to inhibit the sequence clock output and thus stall
the IDC microcontroller until the sync byte of the read data input is detected.

A functional block diagram of the clock control logic is shown in Figure 3-4. A timing diagram showing
the periods of the input clocks and the controlled gating of the clocks to the CURRENT CLOCK and

SEQUENCE CLOCK outputs is presented in Figure 3-5.

As shown in Figure 3-4, the RL0O2 input to the clock control enables the appropriate RL02 or R80 disk
drive clock inputs to be asserted as the SYS CLOCK or DISK CLOCK inputs to the CURRENT
CLOCK and SEQUENCE CLOCK gates. The P2 CLOCK L and the RL STATUS CLOCK inputs
are asserted directly to the CURRENT CLOCK and SEQUENCE CLOCK gates.
To change from one synchronizing clock to another, the microcontroller asserts a UCHANGE
CLKSRC H input and the applicable clock select signal (USEL SYS CLK, USEL STATUS CLK,
USEL CPU CLK, or USEL DSK CLK).

3-41

)

FROM

MICROCONTROLLER
e A,

)

USEEK INSTR

TAG BUS

CONTROL

LOCK

DAR 01

0 Reap TAG
1

—3,:75“

UWRITE
GATE

0\|wmre TAG

DAR 00

STROBE

h CNTL TAG
1

DAR 15

STROBE

FROM
DISK

® GATING SEEK, HEAD SELECT, AND RECALIBRATE COMMANDS

——-—‘

]rso TaG BUs 0

USEEK INSTR

TM.

J—.—‘

Horevt

TAG

f1 SEL

::j>

—-‘

[|r80 TAG 3

l‘— CONTENTS OF DAR 00:DAR 03,
DAR 06 AND 07 ASSERTED ON

ASSOCIATED TAG BUS OUTPUTS.

CONTENTS OF DAR 13:DAR 15 DECODED
AND APPLICABLE TAG OUTPUT ASSERTED

RBO TAG 2

(SEEK = TAG 1, HEAD SELECT = TAG 2,
RECALIBRATE = TAG 3).

CONTENTS OF DAR 04, 05, 08
AND 09 ASSERTED ON

ASSOCIATED TAG BUS QUTPUTS.

RB0 TAG 1

DAR 13

TO R80
DISK

USEEK INSTR

DRIVE

GATING READ GATE COMMAND

TM\

Irso TG BuUS 07

DAR 06

Irso 1AG BUS 06

DAR 03

R80 TAG BUS 03

DAR 02

\ R8O TAG BUS 02

DAR 09

R8O TAG BUS 09

UTAG STROBE

DAR 08

RBO TAG B8US 08

UWRITE GATE

DAR 05

lrso 1ac Bus 05

DAR 07

}G—ONE CPU MICROSTATE (270 nsec)

UTAG STROSBE

DAR 14

-t

[N\__Irso 1aG BUS 1)

1 SEL

UTAG

ADDRESS

DRIVERS

1 SEL

UTAG

13
SEEK
HEAD SEL 14
15, 06
RECAL

R8O LINE

|EN/

UTAG STROBE

UENB LOOP LOL__,—" “'_l—__

{

__.‘ R80 TAG 3 ASSERTED b.__.
| R80 TAG BUS 1 “_
ASSERTED

® GATING WRITE GATE COMMAND
I

€C

i 1

—-" R80 TAG 3 ASSERTED ‘Q——
»

R80 TAG BUS 0

ASSERTED

DAR 04

R8O TAG BUS 04
P

1K-1374

Figure 3-3

TAG Bus Control Logic Functional Block Diagram

TO MICROCONTROLLER
—

FROM DISK DRIVE
SELECT AND DRIVE—DL02 H
READY MONITOR

FROM MFM ENCODER

FROM READ DATA
SEPARATOR

FROM

RBODISK

4.1 MH
4

CHANGE

USEL
SYS

CLK SRC H
INIT L

:L JLSYNC
ENDCLKCLR i
CURRENT

DS CLOCK

SYS CLOCK

R8O

SERVO CLOCK

{—
——

gt&

DISK CLOCK

STATUS SSEL

CLK L

[CLK H

° C?OCKSELEgT
REGISTER
:

)

END SYNC

ofCER L

CURRENT CLK

)

[USEL

USEL

CcPU

CLK H

CLR

CLK H

°
1

TO HEADER/DATA COMPARATOR
—————

JAM L

SEL DSK CLK

SEL STATUS CLK

RL STATUS CLOCK
SEL CPU CLK H

D .

CURRENT CLOCK

P2 CLOCK L

FROM RLO2
DISK DRIVE
FROM IDC/CPU

gL §TATUS CLOCK

SEL SYS CLK
SYS CLOCK

>
P2 CLOCK L

INTERFACE LOGIC

SEL SYS CLK

tv-t

INIT L
FROM SYNC

BYTE RECOGNITION
LOGIC

SYNC SEEN H

CURRENT CLK L

o 1
SYNC
CLK

ENB S

!|
tg

>ENB DSK SEQ CLK

SEL CPU

SYS CLOCK

CLK L

P2 CLOCK L

SEQ CLK L

RL STATUS CLOCK

SEQ CLK H

DISK CLOCK

END SYNC CLR L

ENB SEQ CLK L

INIT L

UCHANGE
CLK SRC

+3 y————u{D SEQUENCE 1
CURRENT CLOCK

CLOCK

DELAY (+4)

ENB SEQ CL K H
OL.ENB SEQ CLK L

TK-7372

Figure 3-4

Clock Control Logic Functional Block Diagram

270 nsec
45 nsec

P2 CLOCK L

|<—244 nsec-bl

DS CLOCK*

4.1 MHz
RL STATUS CLOCK**

R80 READ CLOCK
R80 SERVO CLOCK

ENABLE
SYS CLOCK
CURRENT CLOCK H

UCHANGE CLK SRC H

USEL SYS CLK H

vyt

SEL SYS CLK

SEQUENCE CLOCK H
(ASSUMING RLO2 INPUT H)

ENABLE . STATUS Crocx

I‘IF—LJ74|1||J’1I‘

UCHANGE CLK SRC H

USEL STATUS CLK

END SYNC CLR H

/
END SYNC CLR L

SEL STATUS CLK H

ENB SEQ CLK H .

SEQUENCE CLOCK H
Figure 3-5

\J
\
\\]

Clock Control Logic Timing (Sheet 1 of 2)

—

| 1

l—

CURRENT CLOCK H
UCHANGE CLK SRC H

-t

L°L_J

—__J‘__I

ENABLE DISK CLOCK (RLO2)

L
r

USEL DSK CLK H

SEL DSK CLK

[

ENB SEQ CLK L

4 F

r C

SYNC SEEN H

[

{ €

b€

SEQUENCE CLOCK H
-

DS CLOCK ALTHOUGH SHOWN TO OCCUR AT A 4.1 MHz RATE
(NOMINAL) MAY VARY SLIGHTLY WITH DISK DRIVE SPEED.
4.7 MHz CLOCK AND RL STATUS CLOCK OCCUR AT THE 4.1 MHz
RATE SHOWN FOR THE DS CLOCK; HOWEVER, THE PHASE
RELATIONSHIP OF THESE CLOCKS VARY,
R80 SERVO CLOCK OCCURS AT THE RATE SHOWN FOR THE
R80 READ CLOCK; HOWEVER, THE PHASE RELATIONSHIP
OF THESE CLOCKS VARY,

NOTE:

[

l._’

PHASE RELAT!ONSHIP OF CLOCK INPUTS TO THE IDC
SHOWN ABOVE MAY OR MAY NOT BE AS ILLUSTRATED:
THIS DIAGRAM ILLUSTRATES THE VARIOUS PERIODS
OF THE CLOCK INPUTS ONLY.

R8O SERVO CLOCK OCCURS AT THE RATE SHOWN FOR THE
R80 READ CLOCK; HOWEVER, THE PHASE RELATIONSHIP
OF THESE CLOCKS VARY.

TK-7364

Figure 3-5

Clock Control Logic Timing (Sheet 2 of 2)

3.5.3.1 Enable SYS CLOCK - To enable the SYS CLOCK to be asserted onto the CURRENT
CLOCK and SEQUENCE CLOCK outputs of the clock control logic, the microcontroller asserts
UCHANGE CLKSRC H and USEL SYS CLK to the clock control (sec Figure 3-4). The UCHANGE
CLKSRC H input enables the CHG CLK flip-flop to be set with the following CURRENT CLOCK
input. When the CHG CLK flip-flopis set, it asserts an END SYNC CLR signal to the clock gate of
the clock select register, which initiates loading of the USEL SYS CLK signal. The resulting SEL SYS
clock output is asserted to the CURRENT CLOCK and SEQUENCE CLOCK gates to enable either
the 4.1 megahertz clock or R80 SERVO CLOCK inputs, as applicable, to be asserted on the
SEQUENCE CLOCK and CURRENT CLOCK outputs. Figure 3-5 illustrates the timing relationships of input and output signals for changing the synchronization clock from the CPU CLK (P2
CLOCK) to the SYS CLOCK (4.1 megahertz clock).

3.5.3.2 FEnable RL STATUS CLK or CPU CLOCK - To enable the RL STATUS CLK or CPU
CLOCK to be asserted on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock
control, the microcontroller asserts UCHANGE CLKSRC and USEL RL STATUS CLK or USEL
CPU CLK to the clock control (see Figure 3-4).

The UCHANGE CLKSRC H input is asserted to the CHG CLK flip-flop and to the reset gate of the
sequence clock delay. The UCHANGE CLKSRC input together with the END SYNC CLR L output
of the CHG CLK flip-flop resets the sequence clock delay.

When the sequence clock delay is reset, the ENB SEQ CLK outputs are deasserted from the sequence
clock gates, which inhibits the currently selected clock (with the exception of the SYS CLK) from
being asserted on the SEQUENCE CLOCK output.

When the UCHANGE CLKSRC signal is loaded into the CHG CLK flip-flop (when the CURRENT
CLOCK input goes high), the END SYNC CLR H and L outputs are enabled. The END SYNC CLR
H output initiates loading of the applicable clock select input (for this discussion, the USEL CPU CLK
or USEL STATUS CLK input) from the microcontroller into the clock select register. The END
SYNC CLR L output removes the reset signal from the sequence clock delay.
The applicable clock select (SEL STATUS CLK or SEL CPU CLK L and H) outputs of the clock
select register are asserted to the sequence clock and current clock gates. The appropriate SEL STATUS CLK or SEL CPU CLK H output enables the selected clock input to be asserted directly on the
CURRENT CLOCK output.

The selected clock input RL STATUS CLOCK or CPU CLOCK (P2 CLOCK L) is not enabled on the

SEQUENCE CLOCK output until after the sequence clock delay asserts the applicable ENB SEQ
CLK signal to the sequence clock gates.

As noted earlier, the ENB SEQ CLK outputs of the sequence clock delay were reset when the UCHANGE CLKSRC H input was asserted from the microcontroller and was held in the reset state until
- the UCHANGE CLKSRC input was loaded into the CHG CLK flip-flop. After the reset to the sequence clock delay has been removed, and four positive transitions of the CURRENT CLOCK have
been asserted, the ENB SEQ CLK H and L outputs are enabled. These outputs enable the selected RL
STATUS CLOCK or CPU CLOCK (P2 CLOCK L) inputs to be asserted on the SEQUENCE
CLOCK output.

The timing diagram of Figure 3-5 illustrates the relationships of input and output signals required to
change the synchronization clock from the CPU CLOCK to the RL STATUS CLOCK.

3-46

3.5.3.3
Enable DISK CLOCK - To enable the DISK CLOCK (R80 READ CLOCK or DS CLOCK)
on the CURRENT CLOCK and SEQUENCE CLOCK outputs of the clock control, the microcontroller asserts UCHANGE CLKSRC H and USEL DSK CLK H to the clock control. The DISK
CLOCK is enabled on the CURRENT CLOCK output of the clock control in much the same manner
as discussed for enabling the CPU CLOCK or RL STATUS CLOCK (Paragraph 3.5.3.2). However,
an additional input (SYNC SEEN) to the clock control is necessary before the DISK CLOCK is gated
on the SEQUENCE CLOCK output. Gating of the DISK CLOCK to the SEQUENCE CLOCK output is delayed until after SYNC SEEN is asserted (see Figure 3-4). The timing diagram of Figure 3-5
illustrates the relationships of input and output signals required to change the synchronization clock
from the SYS CLOCK (4.1 megahertz) to the DISK CLOCK (DS CLOCK).
3.5.4

Sync Byte Recognition Logic

The sync byte recognition logic is used to locate the sync byte of the READ DATA from the selected

disk drive. There are two sync bytes in each sector of READ DATA asserted from the disk drives; one

directly precedes the header portion of the READ DATA, the second directly precedes the data portion
of the READ DATA. The process for locating each of these sync bytes is similar; thus, the following
discussion is keyed to locating the sync byte that precedes the data portion of the READ DATA input.
This was selected because, when the sync byte has been located and if the IDC is performing a write
check function, the SYNC SEEN signal is used to initiate loading the data shift register with the first
byte of data to be compared with the READ DATA input. (The SYNC SEEN signal is used to load the
data shift registers because the microcontroller, which normally controls loading of the data shift registers, remains in a stall condition until after SYNC SEEN is generated, which would result in misalignment of the data to be compared.)
To locate the sync byte of the READ DATA input, the sync byte recognition logic converts the serial

READ DATA input to a parallel format and compares the parallel formatted READ DATA with the
sync byte pattern expected (CONSTANTS input from the microcontroller). When a match is determined, a SYNC SEEN signal is generated. A functional block diagram of the sync byte recognition
logic is shown in Figure 3-6.
The microcontroller presets the conditions that enable the sync byte to be located. First, the micro-

controller generates and asserts the CONSTANTS to the eight-bit checker. For locating the sync byte
in the RLO2 READ DATA, the CONSTANTS asserted are preset to 80;¢. For locating the sync byte
in the R80 READ DATA, the CONSTANTS are preset to 1916. (CNST 7 of the CONSTANTS input
is the most significant digit of the specified sync byte pattern asserted via the CNST 7:0 inputs.) Also,
if the IDC is performing a write check function, the microcontroller asserts a UWRT CHK H signal.
Then the microcontroller selects the DISK CLK to be asserted on the CURRENT CLOCK output of
the clock control. When the DISK CLOCK is selected, the clock control asserts its SEL DSK CLK,
CURRENT CLOCK H, and CURRENT CLOCK L outputs to the sync byte recognition logic. Because the DSK CLOCK asserted on the CURRENT CLOCK outputs of the clock control is derived
from the READ DATA asserted, the CURRENT CLOCK H and L input are synchronized with each
bit of the READ DATA input.
The READ DATA H input to the sync byte recognition logic is asserted to the eight-bit checker and
read data synchronizer (see Figure 3-6). The READ DATA H input to the read data synchronizer is
sampled at the midpoint of each data bit interval by the CURRENT CLOCK L input, and the condition of the READ DATA H input (a logical 0 or 1) is loaded into the read data synchronizer. A diagram showing the timing relationship of the signals and events discussed in the following paragraphs is
presented in Figure 3-7.

3-47

(uwrT chk 1|

PART OF HEADER/DATA COMPARATOR

CNST 7

CNST 6
CNST §

PChOcoNTROLLER

NTROLLER

| T2
CNST 3
CNST 2

(PAL)

]

WRT
TO WRITE
DSR
LoADCHK
DSR L__ cHECK

COMPARISON

LosIc

CNST 1
CNST 0

FROM

SERIALIZER

READ DATA H

CURRENT =] ReAD DATA

CLOCK L

SYNCHRONIZER

SERIAL DATA IN

DATA

DSR 7

SYNC

FF 0

SYNC SEEN L *_ TO
SERIALIZER

SYNC H 10 cLock
SEEN

CONTROL

TO RLO2 HEADER

M—-

COMPARISON LOGIC
AND WRITE CHECK
COMPARISON LOGIC

DSR 4
REGISTER |psR 3
DSR 2

SHIFT

FROM
CLOCK
CONTROL\

BYTE

COMPARE H
8 BIT
CHECKER

8-t

DSR 1

CURRENT CLOCK H

SEL DSK CLK H
.

TK.7387

Figure 3-6

Sync Byte Recognition Logic Functional
Block Diagram

DATA INTERVAL

OF FIRST BIT

OF READ DATA

BIT3 | BIT4

7+
|

SERIAL DATA IN H

OF DATA

SHIFT

psm 5
DSR 4

DSR 3
DSR 2

DSR 1
CNST 7

CNST 6
CNST 5
CNST 4

CNST 3
CNST 2
CNST 1

CNST O

0
0
0
1
1
0

1
0
0
0
0
0

o}
1
0
0
0
0

—

I__”_r 1_4 ,_J_‘__‘

|
1

0
0
1
0
0
0

1
0
0
1
0
0

0
1
1
0
0
1

1
1
0
0
1
0

» 0
0
0
1
1
0

0
1

—»

0
1

BYTE COMPARE H

SEL DSK CLK H

SYNC SEEN L

o6v-t

0
0
0
0
0
0

DSR 6

Jgov

DSR 7
CONTENTS |

~in

CURRENT CLOCK L

]

BT7 | miTs 1

WRT CHK LOAD DSR L

Figure 3-7

Sync Byte Recognition Logic Timing Diagram

oy,

BTs | BIT6

= =2000

awmmentowon

ZERO |r BT1 | BiT2

READ DATA H

OF HEADER
OR DAJ\L

R80 SYNC BITE PATTERN

OO0

INPUT FROM
DISK DEWE

TK-7377

When the read data synchronizer is loaded, it asserts the sampled condition of the READ DATA H
input to the data shift register via the SERIAL DATA IN signal line. The CURRENT CLOCK H
input to the data shift register loads the SERIAL DATA IN signal asserted into DSR7 of the data shift
register and shifts the current contents of DSR 7:1 to DSR 6:0, respectively.

The parallel outputs DSR7:1 of the data shift register are asserted to the eight-bit checker where they
are compared with the CONSTANTS (CNST 6:0, respectively). When a match is determined and the
READ DATA H input matches the CNST 7 input, the BYTE COMPARE H output of the eight-bit
checker is asserted to the input gates of the SYNC FF and to the write check load DSR gate. The
BYTE COMPARE H and SEL DSK CLK H inputs to the SYNC FF input gates enable the SYNC FF
to be set with the next positive transition of the CURRENT CLOCK H input, producing the SYNC
SEEN H and L output signals. The BYTE COMPARE H signal enables the WRT CHK LOAD DSR
L output. The WRT CHK LOAD DSR L output is asserted to the data shift register, where it is combined with the CURRENT CLOCK H input to load the data shift register.

The SYNC SEEN H output of the SYNC FF is asserted to the input gates of the SYNC FF, where itis
combined with the SEL DSK CLK H input from the clock control to inhibit the SYNC SEEN output
from being reset until another clock is selected by the microcontroller. The SYNC SEEN L output of
the SYNC FF is asserted to the serializer.

3.5.5

RL02 Header Comparison Logic

The RLO?2 header comparison logic enables the IDC to locate the sector to or from which the data are
to be written or read. The address to or from which the data are to be written or read is loaded into the
IDC disk address register by the CPU. The parallel output of the disk address register is asserted to the
serializer where it is converted into a serial format and asserted to the header/data comparator for
comparison with the READ DATA input (the address portion of the RLO2 header data). A functional
block diagram of the RLO2 header comparison logic is shown in Figure 3-8.

The microcontroller disk drive select and drive status monitor and the sync byte recognition logic preset
the conditions for performing the RLO2 header comparison. The disk drive select and drive status monitor asserts a low R80 input to the bit select gates of the serializer to identify the selected drive as an
RLO2. (The R80 input identifies the order in which the parallel output of the disk address register is
serialized). With the R80 input low, the bit select gates enable the DAR 00:15 inputs to be asserted
sequentially to the SERIAL DAR H output (DAR 00 is asserted first and DAR 15 is asserted last).
When the search for the sync byte preceding the header data is initiated by the microcontroller, the
microcontroller asserts a UENB CLR BC H input to the serializer binary counter. The UENB CLR
BC H input and the SYNC SEEN L input (a high until the sync byte is found) hold the binary counter
reset to the count of zero. While the binary counter is reset, the bit select gates continuously assert the
DAR 00 ontput on the MUX DAR H output. (This enables the SERIAL DAR H output to provide the
first bit of the header data to the header data comparator coincident with the first bit of the header
data asserted via the READ DATA H input.) Before the sync byte is located, the SYNC SEEN H
input to the header/data comparator is low. The low SYNC SEEN H input holds the compare flip-flop
set until the SYNC SEEN H signal is asserted high. The UWRT CHK H input to the header/data
comparator is a low when not performing a write check function, allowing the READ DATA H input to
be compared with the SERIAL DAR H input once the sync byte has been located.

3-50

PART OF HEADER/DATA COMPARATOR
FROM

MICROCONTROLLER

UWRT CHK H

FROM SYNC

BYTE

SYNC

SEEN H

RECOGNITION

LOGIC

MODIFIED READ DATA H*

READ

SERIAL DAR H

FROM DISK _DATA H

DATA MUX

‘—" SERIALIZER
DAR_15

FROM

16-¢

DISK ADDRESS

FROM DISK

DRIVE SELECT

AND DRIVE

DAR 00

—R22

GATES

BINARY

SYNC

UENB
FROM
y
CLR BC HI
MICROCONTROLLER
FRO v
CLOCK

PAL)

CLK

comr

COMPARE L

—

]

|MUX

DARHIL

{PALS)

]

FROM

COUNT

Jl>°

UCON 1 H

)

MICRO-

SEQUENCER:

L | :DO— ?OUNTER
RECOGNITION LOGIC SEEN

BIT

SELECT

STATUS MONITOR

FROM SYNC BYTE

w‘

UCON 0 H

MISMATCH L

FF .

(PAL)

CURRENT CLOCK H

CONTROL
TK.7368

* FOR RL0O2 ADDRESS COMPARISON,
MODIFIED READ DATA H QUTPUT QF
SERIALIZER IS THE SAME AS THE
READ DATA H INPUT,

Figure 3-8

RLO02 Header Comparison Logic Functional
Block Diagram

When the sync byte has been located, the SYNC SEEN H and SYNC SEEN L signals to the compare
flip-flop enable gates and the reset gate of the serializer binary counter are asserted. The SYNC SEEH
H signal enables the comparison of the first bit of the header data asserted via the READ DATA H
input and the first bit of the read/write address from the disk address register (DAR 00) asserted via
the SERIAL DAR H input to the header/data comparator. The SYNC SEEN L signal input to the
serializer binary counter presets the binary counter to the bit count of 1. When the binary counter 1s
preset by the SYNC SEEN L input, DAR 01 from the bit select gates is asserted on the MUX DAR H
signal line.

With the first positive transition of the CURRENT CLOCK H input (following the assertion of the
SYNC SEEN H and L signals), the results of the comparison of the first bit of the header data and the
first bit of the desired read/write address are sampled at the compare flip-flop. Also, the first positive
transition of the CURRENT CLOCK H input increments the serializer binary counter and enables the
second bit of the read/write address to be loaded into the serializer flip-flop and asserted to the header/data comparator via the SERIAL DAR H input. (The binary counter is always one bit count ahead
of the header address bit being compared. This enables each of the read/write address bits to be asserted to the header/data comparator in sync with the corresponding address bits asserted via the
READ DATA H input.)

The SERIAL DAR H and READ DATA H inputs to the header/data comparator are compared via an
exclusive OR in the enable gates of the compare flip-flop. If the SERIAL DATA H and READ DATA
H inputs match, the output of the exclusive OR remains low and the compare flip-flop remains reset.
However, if the inputs do not match, the compare flip-flop is set and a feedback loop from the compare
flip-flop holds the compare flip-flop set for the remainder of the bit comparisons.
After all 16 bits of header have been compared, the microcontroller tests the comparison results by
setting UCON 1 H at a high and UCON 0 at a low. This configuration of UCON signals inhibits three
of the four enable gates at the input of the mismatch flip-flop. If during the bit comparisons all bits of
the header data and the read/write address compared, the COMPARE H input to the fourth enable
gate will be a low. Thus, when the other three enable gates are inhibited, the MISMATCH L output of
the header/data comparator will be asserted high. However, if the bits did not compare, the
COMPARE H input to the fourth enable gate holds the MISMATCH L output at a low when tested
with the UCON signal inputs. The MISMATCH L signal output is asserted to the microcontroller. A
timing diagram showing the relationship of signal inputs and events for the RL02 header comparison
logic is shown in Figure 3-9.

3.5.6 R80 Header Comparison and Skip Sector Monitor Logic
The R80 header comparison and skip sector monitor logic enables the IDC to locate the sector to or
from which the data are to be written or read and to determine if the sector is bad or displaced. The
address to or from which the data are to be written or read is loaded into the IDC disk address register
by the CPU. The parallel output of the disk address register is asserted to the serializer where it is
converted into a serial format and asserted to the header/data comparator for comparison with the
header portion of the READ DATA input (the R80 header data).
The R80 header data is not asserted via the READ DATA H input in the same bit configuration as the
read/write data address contained in the disk address register. Also, the R80 header data contains
unused bits, and various flag bits that are not significant to the R80 header comparison function. Therefore, for the R80 header comparison and skip sector monitor operation, the serializer is used to mask
the unused bits and various flag bits of the R80 header data, to control assertion of the read/write
address from the disk address register, and, if enabled, to record the status of the skip sector flag of the
R80 header data. A functional block diagram of the R80 header comparison and skip sector monitor
logic is shown in Figure 3-10.

3-52

FIRST BIT OF HEADER
DATA ASSERTED

LAST BIT OF
SYNC BYTE

I¢

SYNC SEEN L

READ DATA H
| I

BIT COUNT

SERIAL DAR H
€6-¢

[

CURRENT
H
CLOCK

|
UENB CLRBCH_

T+ T2[slalsTelrJeJofrolnlwjnluln]me]

l‘

1w ][n][1n2]13]14]15]16]

[ 7] 21 3] 4 [ 5] 6789

DARO0

4 ] 01 ] 02 ] 03 | 04 | 05 Jos J o7 J o8 [ oo J 10 [ 11 [ 12 [ 13 ] 14 ] 15|
FIRST BIT OF READ/WRITE
ADDRESS ASSERTED

COMPARE L

e e e ee

MISMATCH L

UCON 0 H

[

UCON 1 H

NOTE:

DASHED LINES INDICATE SIGNAL CHARACTERISTICS |F

COMPARISON 1S NOT VALID. COMPARE L SIGNAL INDICATES THAT
BIT 11 OF HEADER DID NOT MATCH.

Figure 3-9

RLO2 Header Comparison Logic Timing Diagram

TEST

%7 matcH
P

TK-7380

TO SKIP SECTOR

CONTROL LOGIC

FROM
MICROCONTROLLER

SSE

UWRT CHK H

]

SERIALIZER

FROM SKIP

SECTOR conTRoL INH

SSE

LoGic

CURRENT

~—f SSE

SSE

—e] DETECTOR [

PART OF HEADER/DATA COMPARATOR

CLOCK H

FROM DISK

READ

DATA MUX

DATA H

FROM

(PALS)

MODIFIED READ DATA H

UWRT

MICROCONTROLLER CHK H

READ DATA

FROM

—_— MODIFIER

SYNC
BYTE

FROM DISK DRIVE

YNNG

RECOGNITION

SELECT AND DRIVE
STATUS MONITOR

FROM DISK

ps-¢

ADDRESS REGISTER

R80

DAR 19-

BIT

SELECT

AND BIT
ASSERTION

R 0.0

CONTROL

DAR

MUX

o
aIT

COMPARE L

parul

seriaL

COMP
EF

——»{ GATES

BIT

COUNT

FROM SYNC BYTE
RECOGNITION LOGIC

SYNC
SEEN L

FROM

UENB CLR

MICROCONTROLLER

BC H

BINARY

COUNTER
{PAL)

MISMATCH L

)
.

f——
>

MiS

FROM

MICROCONTROLLER

(PAL)

CURRENT

FROM CLOCK CLOCK H

CURRENT CLOCK H

CONTROL

FROM
MICROCONTROLLER

UCON 1 H
| UCON O H
TK-7369

Figure 3-10

R80 Header Comparison and Skip Sector Monitor
Logic Functional Block Diagram

3.5.6.1

R80 Header Comparison Logic - The microcontroller disk drive select and
drive status monitor and the sync byte recognition logic preset the conditions for performin
g the R80 header comparison. The R80 input to the bit select and bit assertion control gates identifies
the order in which the
parallel output of the disk address register is to be serialized and enables
the ASSERT BIT output with
specific bit counts to mask the header data bits within the R80 header
data that are not significant in
locating the desired address. The R80 input is asserted also to the read
data modifier.
With the R80 input asserted and the UWRT CHK H signal not asserted, the read
data modifier masks
out the header data bits that are of no significance in locating the desired
address, by asserting the
MODIFIED READ DATA H output to a high during the bit count interval
in which these header data
bits occur.
When the search for the sync byte preceding the header data is initiated, the microcontro

UENB CLR BC H input to the serializer binary counter. The UENB CLR BC H

ller asserts a
input and the SYNC

SEEN L Input (a high until the sync byte is found) hold the binary counter reset to
the count of zero.
While the binary counter is reset, the bit select and bit assertion control gates continuousl
y assert the
DAR 09 output on the MUX DAR H and the SERIAL DAR H outputs. (This
enables the SERIAL
DAR H output to provide the first bit of the header data to the header data comparator
coincident with
the first bit of the R80 header data asserted via the MODIFIED READ DATA
H input.)
Before the sync byte is located, the SYNC SEEN H input to the header/data
comparator is low. The
low SYNC SEEN H input holds the compare flip-flop set until the SYNC SEEN
H signal is asserted.
The UWRT CHK H input to the header/data comparator is an L when not performing
a write check
function, thus allowing the MODIFIED READ DATA H input to be compared with the
SERIAL
DAR H input once the sync byte has been located.
When the sync byte has been located, the SYNC SEEN H and SYNC SEEN L signals

the compare flip-flop enable gates and the reset gate of the serializer binary counter. The

are asserted to

SYNC SEEN
H signal enables the comparison of the first bit of the header data asserted via the MODIFIED
READ
DATA H input with the first bit of the read/write address from the disk address register
to be asserted
via the SERIAL DAR H input to the header/data comparator.

The SYNC SEEN L signal input to the serializer binary counter presets the binary counter
to the bit
count of 1. When the binary counter is preset by the SYNC SEEN L input, DAR 10 from
the bit select

and bit assertion control gates is asserted on the MUX DAR H

signal line. With the first positive transiCURRENT CLOCK H input (the first positive transition following the assertion of the
SYNC SEEN H and L signals), the results of the comparison of the first bit of the R80
header data
tion of the

(modified READ DATA) and the first bit of the desired read/write address (DAR 09) is sampled
at
the compare flip-flop. Also, the first positive transition of the CURRENT CLOCK H input increments

the serializer binary counter and enables the second bit of the read/write address (DAR 10) to be
loaded into the serializer flip-flop and asserted to the header/data comparator via the SERIAL DAR H'

input.

The sequence in which the read/write address bits (DAR 19:00) are enabled on the SERIAL DAR H

input to the header/data comparator is controlled by the bit select and bit assertion control gates. Also,
the bit sclect and bit assertion control gates enable a high to be asserted on the SERIAL DAR H signal

linc coincident with the BIT COUNT associated with the unused and various flag bits of the R80 headcr data. During the data interval (BIT COUNT) in which the unused and various flag bits of the R80
header data are being asserted on the READ DATA H signal line, the read data modifier forces the

MODIFIED READ DATA H signal to a high. This allows the unused and various flag bits of the R80
hcader data to be masked from the comparison of the address information.
The timing diagram (Figure 3-11) shows the format of the R80 header data asserted via the READ
DATA H input, the corresponding BIT COUNT output of the binary counter, the intervals (BIT
COUNT) during which each DAR BIT is gated, the intervals during which the ASSERT BIT is en-

abled (L), and the intervals in which the READ DATA H input is modified to produce the MODIFIED READ DATA H output. Figure 3-11 also shows the resulting MODIFIED READ DATA H and
SERIAL DAR H outputs.
3-55

;_____1

UENB

CLR BCH

R4 S —

Btn
orcown

READ DATA

i " cAo Jcat [caz [ cas [ cas [ cas [cas [ car [ cas [cas [ 7 [

9G-¢t

e w w w]w]wnlnw]

RSN AT S I C I
m w

T 7 ] 7 [ v ] R0 [ oA [ oAz [ as [sas] 7 [ v | v [vso [t [wse [ wsa |

[-T-T-T-T Jwlolelolul-T-T-TeJelofel-]

D T NN N NS

S S NS

e e wlw e nlwl [T

D S SN B A AU BN

[ wloJulelwl

CURRENT
CLOCK H

* FMT (1) = 16 BIT DATA FORMAT

Figure 3-11

R80 Header Data Modification and Comparison
Data Control Timing

Jelelolel

The SERIAL DAR H and MODIFIED READ DATA H outputs of the serializer are compared in an

exclusive OR in the header/data comparator. If the SERIAL DATA H and MODIFIED READ
DATA H inputs match, the output of the exclusive OR remains low and the compare flip-flop remains
reset. However, if the inputs do not match, the compare flip-flop is set and a feedback loop from the
compare flip-flop holds the compare flip-flop set for the remainder of the bit comparisons.

After all bits of R80 header have been compared, the microcontroller tests the comparison results by
sctting the UCON 1 H at a high and UCON 0 at a low. This configuration of UCON signals inhibits
three of the four enable gates at the input of the mismatch flip-flop. If during the bit comparisons, all

bits of the header data and the read/write address compared, the COMPARE H input to the fourth
enable gate will be a low. Thus, when the other three enable gates are inhibited, the MISMATCH L
output of the header/data comparator will be asserted high. However, if the bits did not compare, the

COMPARE H input to the fourth enable gate holds the MISMATCH L output at a low when tested
with the UCON signal inputs. The MISMATCH L

signal output is asserted to the microcontroller.

3.5.6.2 Skip Sector Monitor Logic — The SSE detector of the serializer is enabled during BIT COUNT

4 if the INH SSE L signal is not asserted L. When the SSE detector is enabled, the state of the
READ DATA H input is loaded into the SSE detector at the end of BIT COUNT 14 by the CUR-

RENT CLOCK H input. If the READ DATA H signal line were high during the interval, indicating
that the sector is a bad or displaced sector, a high SSE signal is asserted to the skip sector control logic.

3.5.7
Skip Sector Control Logic
The skip sector control logic (Figure 3-12) enables the IDC to skip a bad or defective sector when writ-

ing or recading from the R80.

SECTOR 27

SECTOR 28

SECTOR 29

SECTOR 30

DATA FOR

DEFECTIVE

SECTOR 27

DATA FOR

SECTOR 28

SECTOR

SECTOR 29

SECTOR 31

(RESERVED

SECTOR)

DATAFOR
SECTOR 30

SSF

TK8672

Figure 3-12

Skip Sector Control Logic
Functional Block Diagram

When the skip sector flag (bit 13 of the header word) is detected during a write operation, that sector is
skipped. The information is then written in the next sector. Each following sector is displaced by one.

Figure 3-13 shows an example of the last five sectors of a track. In this example, sector 29 was found to
be defective during the formatting process. The skip sector flag was set in sectors 29 and 30. Notice
that the data for sector 29 were written in sector 30. The data for sector 30 are written in the reserve

sector 31. The skip sector flag is set in all remaining sectors of the track. This is done in case a data

transfer begins at a sector that is beyond the defective sector.

3-57

ASS |

BUSY D27 —

SSE |

BUSYD22
SSEFLAG]
Y 023
BUS

ASSI H

—® TO CSR

INH SEE L

con
CONTROLLED

SSE FLAG L

USET SSE L

INHIBIT

TM o 10c sTATUS

___| WORD DRIVERS
-

INH SSE L
r

LA
J

SERIALIZER

RD DATA H

SSE
DETECTOR

ASS! H

MICROSEQUENCER

CONTROLLED
SSE INHIBIT

’

]

|M'CROSEQUENCERL——e UINCR DAR L

csse y
>

USET ISSE L
TK-8663

Figure 3-13

Skip Sector Example

During a read operation, the same type of process takes place. When a skip sector is detected as being
set, the data are then read from the next sector.
When a skip sector error is detected by the skip sector monitor logic (Figure 3-10), it asserts skip sector
error signal SSE H which is sourced to the skip sector control logic. Inside the skip sector control logic
the skip sector error signal SSE H is ANDed with the microsequencer inhibit skip section error (USET
ISSE L). Provided that the microsequzncer has enabled skip sector errors (USET ISSE L deasserted),
skip sector error signal SSE H is sourced to the microsequencer as CSSE H.
Provided that the CPU has disabled automatic skip sectoring (CSR bit 27 (ASSI) set), the microsequencer aborts the operation immediately. This results in the assertion of USET SSE L to flag the
CPU (SSE FLAG L) that operation has been terminated due to a skip sector error and in the assertion
of UINCR DAR L to increment the disk address register.
The driver software then sets CSR bit 23 (SSE FLAG) to clear the skip sector error, sets CSR bit 22
(SSEI) to inhibit further generation of skip sector errors, and clears CSR 7 (CRDY) to set the GO bit
which continues the transfer.

‘The SSEI bit allows the IDC to finish the transfer without an interrupt from the skip sector flag. It also
sets up the IDC to read sector 31, if necessary. The SSEI bit is cleared by the IDC at the end of each
track. Therefore, the driver software must clear SSEI at the beginning of each data transfer.
3.5.8 Write Check Data Comparlson Logic
The write check data comparison logic (Figure 3-14) performs a bit-by-bit comparison of the data portion of the R80/RL READ DATA input with the DSRO input to determine if the R80/RL READ
DATA matches the serialized data from the data shift register.

3-58

PART OF HEADER/ DATA COMPARATOR

FROM

MICROCONTROLLER UWRT CHK H
FROM

READ DATA H

DISK DATA MUX

DATA BYTE

FROM
FIFO

ULOAD

MICROCONTROLLER
.

WRT CHK

FROM SYNC

LOAD

> DATA

SHIFT

DSR O

”

SYNC BYTE

LOAD

RECOGNITION

— ol CLK

D 1

sw:c SEEN H

conp

—

COMPAR

BYTE

RECOGNITION
LOGIC

65-t

FROM

UCON 1LDC

MICROCONTROLLER

UCON 0 H

L
l

MISMATCH L 4
MICROCONTROLLER

(PAL)

FROM

CLOCK

CURRENT CLOCK H

CONTROL

TK8712

Figure 3-14 -Write Check Data Comparison Logic
Functional Block Diagram

In the write check mode, the WRT CHK LOAD DSRL output of the header/data comparator is enabled when the R80 READ DATA header gap/RL02 READ DATA data preamble sync byte is found.

The WRT CHK LOAD DSRL signal is asserted to the data shift register where it enables the first data
byte from the selected FIFO to be loaded into the data shift register. The microcontroller then increments the selected FIFO address counter.

When the first data byte is loaded into the data shift register, bit O of the first data byte is asserted to
the header/data comparator via the DSRO output of the data shift register. The first bit of the first
data byte is asserted to the header/data comparator coincident with the first bit of the data portion of
the R80/RL READ DATA asserted from the disk drive (READ DATA H from the DISK DATA
MUX). (Because the CURRENT CLOCK used by the data shift register is derived from the R§0/RL
READ DATA input, the data loaded into the data shift register is serialized and asserted to the header/data comparator in sync with each bit of the R80/RL READ DATA input.) The data shift register
serializes and asserts bits 0 through 7 of the first data byte to the header/data comparator.

After bit 7 of the first data byte has been asserted to the header/data comparator, the microcontroller
loads the second byte of data from the selected FIFO into the data shift register and increments the
selected FIFO address counter.

After bit 7 of the second data byte has been serialized and asserted to the header/data comparator, the
microcontroller loads the third data byte from the selected FIFO into the data shift register and increments the FIFO A address counter. This process is repeated until all 512/256 bytes of data from the
selected FIFO have been serialized and asserted to the header/data comparator for comparison with
the data portion of the R80/RL READ DATA input. (A detailed discussion of how the microcontroller
causes serialization of data from the data buffers is provided in Paragraph 3.5.11.)
- When the sync byte has been located, the SYNC SEEN H signal to the compare flip-flop enables gates
is asserted. The SYNC SEEN H signal enables the comparison of the first bit of R80/RL READ
DATA asserted via the READ DATA H input and the first bit of data of the serialized data from the
data shift register asserted via the DSRO input to the header/data comparator.
With the first positive transition of the CURRENT CLOCK H input (the first positive transition following the assertion of SYNC SEEN H), the results of the comparison of the first bit of the R80/RL
READ DATA and the first bit of the serialized data from the data shift register are sampled at the
compare flip-flop.

The DSRO and READ DATA H inputs to the header/data comparator are compared via an exclusive
OR in the enable gates of the compare flip-flop. If the DSRO and READ DATA H inputs match, the
output of the exclusive OR remains low and the compare flip-flop remains reset. However, if the inputs
do not match, the compare flip-flop is set and a feedback loop from the compare flip-flop holds the
compare flip-flop set for the remainder of the bit comparisons.
After all bits have been compared, the microcontroller tests the comparison results by setting UCON 1
H at a high and UCON 0 at a low. This configuration of UCON signals inhibits three of the four enable
gates at the input of the mismatch flip-flop. If during the bit comparisons, all bits of the data shift

will be a low. Thus, when the other three enable gates are inhibited, the MISMATCH L output of the
header/data comparator will be asserted high. However, if the bits did not compare, the COMPARE H
input to the fourth enable gate holds the MISMATCH L output at a low when tested with the UCON
signal inputs. The MISMATCH L signal output is asserted to the microcontroller. A timing diagram
showing the relationship of signal inputs and events for the write check data comparison logic is shown
in Figure 3-15.

3-60

READ DATA
H

LAST BIT OF

FIRST BIT OF

SYNC BYTE

DATA

| # 1+

SYNC SEEN L

[ 2]

a]s ]|

788

l10] 11

[2) []aoss]4o0se] 4087

4088 ] 080 ] 4090 4091 | 4092 T 4003 J 2094 4005 | 4006 |

( -

WRT CHK LOAD DSR L

Je—=

]

FIRST BYTE FROM FIFO

(—

LOADED INTO DATA SHIFT REGISTER

ULOAD DSR L

COUNTER

19-¢

UINCR FIFO CNTR H

DSRO

2134

INTO DATA SHIFT REGISTER

1
s

FIFO MAX
UCON

U‘LLOAD SECOND BYTE FROM FIFQ

INCREMENT FIFO

6 [

]88

]

{

I_."LLOAD LAST BYTE FROM FIFO
1

INTO DATA SHIFT REGISTER

[10] 11

120 )aoss]aoss]a087]
4088 Ja0se ] 2090 | 4091 [ 4092 T4003 ] 4094 [4095 4006|
|

FIRST BIT OF

TEST

DATA FROM FIFO

MATCH

UCON 0 H

MISMATCH L

H IF MATCH

IS VALID
TK-7381

Figure 3-15

Write Check Data Comparison Logic Timing Diagram

t Control Logic

Interrup
generates two interrupts: UBUS BRS5 and PORT XFER REQ. The UBUS BRS interrupt is
IDC
The
generated, when enabled by the CPU, after the function requested by the CPU has been performed or
in the idle mode of operation if a drive status change is detected. The PORT XFER REQ is a special
interrupt signal that is used during the read, write, or write check functions. The PORT XFER REQ
signals the CPU that IDC has read, written, or write checked one complete sector of data and is ready
3.5.9

to read, write, or write check the next sector of data.

3.5.9.1 UBUS BR5 — The UBUS BRS5 interrupt control logic is enabled by the CPU by setting the
Interrupt Enable (IE bit) of the IDC control word input. When the IDC control word is loaded into the
CSR, the IE bit'is asserted to the UBUS BRS interrupt control logic (see Figure 3-16). If the IE bit of
the IDC control word is not set (the IE signal input is low) the generation of UBUS BRS is inhibited. 1f
the IE bit is set, the UBUS BRS5 interrupt may be generated by the microcontroller by asserting a
USET INT L signal, or by the IDC status logic by deasserting any one of the attention bits (ATTN3:0).

PART OF CONTROL STATUS REGISTER (CSR)
(PAL)

FROM
MICROCONTROLLER

USET
“[inT L

gg} INT

TN 3 R

]
H

FROM IDC | ATTN 2

STATUS { ATTN 1 H

Locic

REQ

nM |
“tno
ATINO

LOGIC

(PAL)

DIN H

LOGIC
RESET BR L

LOGIC

BR5 L

cPU

FROM IDC/CPU
INTERFACE

70 I1DC

.STATUS
"

P2 CLOCK L
TK-7379

Figure 3-16

UBUS BRS5 Interrupt Control Logic Functional
Block Diagram

When the USET INT L signal from the microcontroller is asserted or one of the attention bits from the
IDC status logic is deasserted, the SET INT REQ signal goes low producing a high INT REQ DIN
signal input to the BRS flip-flop. The high INT REQ DIN signal causes the BR5 flip-flop to be set with
the next P2 CLOCK L input, producing an INT REQ H output. The INT REQ H output of the BR5
flip-flop is inverted to produce the UBUS BRS L interrupt signal. The INT REQ H output of the BRS
flip-flop is also inverted and asserted to the control gates of the BRS5 flip-flop to hold the UBUS BRS L
interrupt signal asserted until it is reset by the CPU.

3-62

The CPU resets the flip-flop by asserting a RESET BR port microinstruction to the IDC/CPU interface logic. The resulting RESET BR L signal causes the INT REQ DIN H input to the BRS flip-flop
to be deasserted, which enables the BRS flip-flop to be reset with the P2 CLOCK L input. When the

BR5 flip-flop is reset, the UBUS BRS L signal output to the CPU is set H.

3.5.9.2

PORT XFER REQ - The PORT XFER REQ L interrupt signal output of the IDC is set by
inputs from the microcontroller (see Figure 3-17). The microcontroller initiates the PORT XFER REQ
L signal output by asserting UCMD2(H), UCMD1(L) and UCMDO(L). The UCMD inputs enable the
PORT XFER REQ flip-flop to be reset. When the PORT XFER REQ flip-flop is reset, the low signal

output is coupled back to the input gates to hold the flip-flop in the reset state. The low signal output of

the flip-flop is inverted to produce an XFER REQ H signal. The XFER REQ H signal is inverted and
asserted to the CPU as the PORT XFER REQ L (interrupt) signal. The PORT XFER REQ L signal is
reset when the CPU asserts an XFER GRANT L signal or when the IDC is initialized (INIT L asserted).

PART OF CONTROL

STATUS REGISTER (CSR)

(PAL)
UCMD 2 H

FROM

MICRO-

UCMD 1

ll> O

{>o——_____{ >O-————>
XFER REQ H

PORT XFER

REQ L

TO CPU

CONTROLLER

UCMD O H
FROM CPU

XFER GRANT L

INIT L

FROM IDC/CPU
INTERFACE

LOGIC
P2 CLOCK L

TK-7360

Figure 3-17

PORT XFER REQ Logic Functional Block Diagram

3.5.10
IDC Control Register, Timeout Logic, and Status Logic— The IDC control register, timeout
logic, and status logic is contained in the control status register (CSR) shown in Figure 3-1.
3.5.10.1

IDC Control Register — The IDC control register portion of the IDC control register, timeout

logic, and status logic registers the IDC control word input from the
inputs (See Figure 3-18) are used to provide the following:

CPU. The registered IDC control word

Branch condition inputs to the microcontroller

Drive select information to the disk drive select and drive status monitor
Skip sector data to the skip sector control logic
Interrupt enable signal to the UBUS BRS5 interrupt control logic
Presetting the IDC data paths for maintenance
Resetting the IDC status timeout, OPI, and DLT control registers

3-63

IDC CONTROL WORD

0‘

06
08
09

WRITE CSR L

P2 CLOCK L >

(PAL)

¥9-¢

FORMAT | CRDY L

QUTPUT BITS

MAINT H

(PAL)

INIT L

o NIT L

RLOZ

FROM UBUS BRS

INT REQ

INTERRUPT LOGIC

CRDY L

TO RLO2/R80
DRIVERS

FROM DISK DRIVE

DRIVE —————0Q
SELECT AND
MONITOR
STATUS
SSE FLAG L
oA

TO DISK DRIVE SELECT
MONITOR

WRITE INHIBIT L

P2 CLOCK L

CRDY L

CRDY
CONTROL
REGISTER

URESET
TIMER

FROM
N TIMEOUT H
OPI
OPI L
CONTROL

—

B'NMEE:HOT
(330 msec)

MICROCONTROLLER ~ NT.L

OLT
o] CONTROL

INIT
CONTROL
m'
H

DLT L
FROM DISK

DRIVE SELECT .

AND DRIVE

SEL CSR L

STATUS MONITORL

(PAL)

TIMER H TIMEOUT
CONTROL
REGISTER}

DRV ERR H

DRV ERR L

06 |
o
09
26
TM

24 |

29
o

ol!0¢ 28 |~
g;,?;;s 07 |3

TO MICROCONTROLLER |nRIVERS
YJAM H_| AND DATA BUFFER
JAM L | AND DATA REGISTER

TIMEOUT
H

CONTROL LOGIC

TO CLOCK CONTROL

—0

COMPOSITE
ERROR

DRV ROY H

i
ECC/
CRC

LOGIC

0
10,
2
—
15 |

ECC/CRC _| 0

14
0
"
1

L O—
STAT

J———-’

FROM HEA%F;R; >MISMATCH L
DATA COMPARATOR

o1M

02 )
03
25
27

___.} AND DRIVE STATUS
»SSE FLAG | CONTROL LOGIC

0.3, 2
Frow |_UcD
ROLLER
MICROCONT

oPl L

1IDC STATUS WORD

> RLO2 READ ‘ DATA SEPARATO

CONTROL LOGIC

mflITBE‘T

—P2 CLOCK L

TO NR2 DATA FORMATTER AND

TO UBUS BR5 INTERRUPT

R8O FORMAT H.

R80

R8O FORMAT

TO MICROCONTROLLER

FiH
F2 H
MAINT H
ASS! H

02
03
25
27

Y BUS 1/0

— ‘

—1F0 Hf fi

INPUT BITS

ERROR L
Ece

TAT 1

I e

A
TK.d7t4

IDC Control Register Timeout Logic and Status
Logic Functional Block Diagram (Sheet 1 of 3)

Figure 3-18

OOOO
FROM

MICROCONTROLLER

M
19

FROM DISK DRIVE

USET ATTN L

SELECT AND

DRIVE SEL O H

DRIVE STATUS

DRIVE SEL 1 H

MONITOR

BUS 1/0 19 H

(PAL)

ATTNS
CONTROL
o

BUS 1/0

r—

ATTN2

CONTROL
REGISTER

BUS 1/0 18 H

?é’i 110

BUS 1/0 17 H

?;JSLI/O

G-t

ATTN 1
CONTROL

—1

ATTN O

BUS 1/0 16 H

CONTROL

WRITE CSR L

BUS 1/0

16 L

P2 CLOCK L
INIT L

SEL CSR H

SEL CSR L

Mu‘r L

2 cLock L

FROM 1DC/CPU

INTERFACE LOGIC

[WRITE csR L

TK-7392

Figure 3-18 IDC Control Register Timeout Logic and Status
Logic Functional Block Diagram (Sheet 2 of 3)

(PAL)
ONLINE

ONLINE H

GATE

FROM DISK DRIVE

—» TO MICROCONTROLLER

SELECT AND DRIVE
STATUS MONITOR

DRIVE SEL O H
DRIVE SEL 1 H

FROM
'
MICROCONTROLLER

USET ONLINE L

ONLINE 3

UCLR ONLINE L

CONTROL

ONLINE 3 L

ONLINE 2

ONLINE 2 L

99-¢

CONTROL
REGISTER

ONLINE 1
CONTROL

ONLINE 1

ONLINE O
CONTROL
FROM

IDC/CPU INTERFACE

LOGIC

{

INIT H

ONLINE O L

P2 CLOCK L

TK-7352

Figure 3-18

IDC Control Register Timeout Logic and Status

Logic Functional Block Diagram (Sheet 3 of 3)

All registered IDC control word inputs are asserted to the IDC status word drivers and form part of the
IDC status word output of the IDC.
'
There are four unregistered IDC control word inputs (BUS 1/0 19:16). These bits are used to clear the
attention (ATTN) control registers of the IDC status logic.
Each of the IDC control word is loaded into the IDC by the WRITE CSR L and P2 CLOCK L inputs
from the IDC/CPU interface logic. Bits 01, 02, 03, 06, 08, 09, 25, 27, 28, and 29 are loaded directly
into registers. These registered bits are asserted to the IDC status word drivers to provide (as part of the
status word output) a record of the specified IDC control word input. These registered bits also provide
branch condition inputs to the microcontroller (FO, F1, F2, MAINT, ASSI, R80 FORMAT), an enable
bit (1E) to the UBUS BRS5 interrupt control logic, disk drive select information (DS0O and DS1) to the
disk drive select and drive status monitor, and, if a maintenance function is specified, a write inhibit
signal to the timeout logic and to the R80/RLO02 drivers. The write inhibit signal inhibits writing to the
R80 or RLO2 disk drives and inhibits timeout from occurring during a maintenance function.

Bits 22 and 23 are registered bits also. However, these bits are discussed as part of the skip sector

control logic (refer to Paragraph 3.5.7).

Bits 16 through 19 of the IDC control word input are used to reset the attention control register associated with each disk drive. The attention control registers are discussed as part of the timeout and status
logic.

Bit 07 of the IDC control word input is asserted to the CRDY, OPI, and DLT control registers. Bit 07
(the CRDY bit input) is registered in the CRDY control register. When registered, the CRDY output is

asserted to the microcontroller where it enables the microcontroller to branch on the branch condition
inputs and initiate the specified function. The CRDY output is asserted also to the timeout logic to start
the timer. While bit 07 is being loaded into the CRDY control register, it is also being used to reset the
OPI and DLT control registers of the status logic to clear any error information that may have been
generated during the previously specified IDC function.

3.5.10.2 Timeout and Status Logic — The timeout and status logic of the control status register limits
the time in which the IDC may attempt to perform a specified function (other than maintenance), registers IDC fault status (OPI and DLT), keeps track of the disk drives currently in use, and, if the IDC
did not complete the specified function within the time constraints of the timeout logic, registers the
reason for noncompletion. The status logic also formats and asserts to the IDC status word drivers the
status information from the disk drive select and drive ready monitor, skip sector control logic, UBUS
BRS5 interrupt control logic, header/data comparator, and ECC/CRC logic.

The timeout of the control status register is enabled when the CRDY L output of the CRDY control
register is set to a high (when an IDC control word is loaded). The low-to-high transition of the CRDY
L signal triggers the timer oneshot (see Figure 3-18). The duration of the timer oneshot is set at 150
milliseconds, which allows sufficient time for the IDC to perform the function specified by the IDC
control word input. After the 150 millisecond time limit, the timer oneshot output goes low producing a
TIMER H signal input to the timeout control register. (If a maintenance function is specified, the
WRITE INHIBIT L signal from the write inhibit register inhibits the generation of TIMER H). The
TIMER H signal is asserted to the timeout control register where it is combined with the CRDY input.
If the CRDY input has not been set to a L indicating that the specified function has not been completed, the timeout control register is set producing a high TIMEOUT H signal. The TIMEOUT H
input to the OPI control register causes the OPI control register to be set, producing a low OPI output.

3-67

The TIMEOUT H signal is also asserted to the jam control and to the OPI control register. The TIMEOUT H input to the jam control initiates generation of the JAM H and JAM L outputs. The JAM H
output is asserted to the microcontroller, to force the next address to 1FF and to the data buffer and
data register control logic to inhibit reading and writing to the data buffers. The JAM L output is asserted to the clock control to deselect the clock selected and to select the CPU clock. When the microcontroller is set to 1FF, the UCMD 0,1, and 2 outputs from the microcontroller set the CRDY control
register producing a low CRDY L output. Also, the microcontroller generates a USET INT L signal
which causes a UBUS BRS interrupt signal to be asserted to the CPU (Refer to Paragraph 3.5.9.1).

If the function specified by the IDC control word input is to be extended (for example, if the current
read function is to be performed for reading more than one sector of data), the microcontroller retriggers the timer oneshot by asserting a URESET TIMER L pulse. Retriggering the timer oneshot inhibits the timeout from occurring as a result of extended operations by extending the timer cycle an additional 150 milliseconds.

The IDC fault status registers include the OPI control register and the DLT control register. The OPI
and DLT control registers are reset when an IDC control word specifying a function to be performed is
loaded (where the CRDY bit, bit 07, is low and WRT CSR L is asserted low) or the IDC is initialized.
When the OPI and DLT control registers are reset, the OPI L and DLT L outputs are set high. The
microcontroller causes setting of the OPI L and DLT L outputs. The OPI control register may be set
also by the TIMEOUT H signal from the timeout control register as discussed previously.
The microcontroller causes setting of the the OPI and DLT control registers by asserting the proper
UCMD 0, 1, and 2 codes. If the IDC does not locate the proper header before timeout occurs, the
microcontroller asserts the UCMD code to set the DLT control register. If an ECC/CRC error is found
in the disk header data, the microcontroller asserts the UCMD code to set the OPI control register. If
during a write function, the requisite data needed has not been loaded, the microcontroller sets the
DLT control register. The OPI and DLT L outputs are asserted to the status formatting logic where it
is encoded to provide error information to the CPU via the IDC status word output. The format of the
IDC status word output is presented in Figure 2-10.

The timeout and status logic of the control status register also keeps track of the disk drive status
through the attention (ATTN) and on-line control registers (See Figure 3-16). One attention control
register and one on-line control register is provided for each of the four disk drives that may be used
with the IDC. The on-line registers record that when last monitored, the applicable disk drive was in
use (performing a function) or not in use. The attention registers are used to signal the CPU that the
associated drive is currently in use, has completed the function it had been performing, or is reporting
an error.

During the idle mode of operation, the microcontroller samples disk drive status. When in the idle mode
of operation, the microcontroller generates the UDRV SEL 0 and 1 and UDRYV SEL signals used by
the disk drive select and drive status monitor. The resulting disk drive address bits (DRIVE SEL 0 and
1) from the disk drive select and drive status monitor are asserted to each of the ATTN 3:0 control
registers, the on-line 3:0 control registers, and the on-line gate. The disk drive select and drive status
monitor gates the DRIVE RDY and DRIVE ERR signals from the appropriate disk drive to the microcontroller. The DRIVE SEL 0 and 1 inputs to the on-line gate enables the appropriate ONLINE signal

to be asserted to the microcontroller.

The microcontroller, after asserting the UDRV SEL 0 and 1 and UDRYV SEL outputs, branches on the
DRIVE RDY, DRIVE ERR, and ONLINE inputs to control the on-line and attention control registers
associated with the addressed disk drive.

3-68

If the selected disk drive is not reporting an error and DRIVE RDY is not present (the disk drive is

performing a function), the microcontroller asserts a UCLEAR ONLINE L signal to the on-line con-

trol registers. The UCLEAR ONLINE signal clears the appropriate on-line register to provide a record
that during the monitoring period, the disk drive was busy.

If the selected disk drive is not reporting an error, DRIVE RDY is present, and the appropriate ONLINE control register is set (indicating that during the previous monitoring period the disk drive was
not busy), the microcontroller enables the next sequential UDRV SEL 0 and 1 address and UDRYV
SEL signals.

If the selected disk drive is not reporting an error, DRIVE RDY is present, and the on-line control
register is reset (indicating that during the previous monitoring period the disk drive was busy), the
microcontroller asserts a USET ONLINE L signal to the on-line control registers and a USET ATTN
L signal to the attention control registers. The USET ONLINE signal sets the appropriate on-line control register to record that during the monitoring period, the disk drive was not busy. The USET ATTN
L signal sets the applicable attention control registers.

If the selected disk drive is reporting an error (DRIVE ERR is asserted), the microcontroller asserts a
USET ATTN L signal to the attention control registers. Also, if the associated on-line control register is
presently cleared (indicating that the disk drive had been busy performing a function during the previous monitoring period), the microcontroller asserts a USET ONLINE signal to the on-line control
registers.

The USET ATTN L signal sets the applicable attention control register. The USET ONLINE signal
sets the applicable on-line control registers to record that during the previous monitoring period the
drive was not busy or was reporting an error.

As indicated in Figure 3-18, the on-line control registers may be cleared and set by the microcontroller
or when the IDC is initialized. However, the attention control registers may be cleared only by the CPU
through an IDC control word input or when the IDC is initialized.

3.5.11 Serializing Data from Data Buffer and Sync Byte Tristate Drivers — The sync byte tristate drivers, data buffers (FIFO A and FIFO B), and data shift register are used to serialize the sync byte and
data to be written to the disk drive during a write data function. During a write check function the data
buffers and data shift register are used to serialize the data from the selected FIFO such that it may be
compared with the data portion of the READ DATA input from the disk drive.

When a write data or write check function is specified by the IDC control word input to the IDC, the
microcontroller selects the FIFO to be used by asserting the appropriate USEL FIFO (A or B) signal tothe data buffer and data register control logic (see Figure 3-19).

During the write data function, the inputs from the microcontroller cause the assertion of the DSR 0
output of the data shift register to the NRZ data formatter to control assertion of a series of zeros and
sync byte (data preamble), and the sector of data contained in the selected data buffer. After the proper sector has been located (header found and ECC or CRC pattern verified), the microcontroller asserts
a UCLR FIFO CNTR H pulse to the data buffer and data register control logic. The UCLR FIFO
CNTR H input causes the ADDRESS asserted to the selected FIFO to be reset to zero. The microcontroller also clears the data shift register by asserting a UCLR DSR L pulse. After the data shift
register is cleared (the DSR 0 output has been reset), the microcontroller loops until the data intervals
required to write the series of zeros to the data preamble have been asserted to the disk drive.

3-69

FROM

FROM DISK DRIVE
SELECT AND DRIVE

MICROCONTROLLER
~

READY R80 MONITOR ,FIFO MAX L
]

FIFO OVFLW D
[

FROM

MICROCONTROLLER

PART OF DATA

( USEL FIFO A H

Y CONSTANTS
(CNST 0:CNST 7)
UENB CONST L

BUFFER AND
DATA REGISTER
CONTROL LOGIC

—

JCLR FIFO CNTR H

COUNTER AND

UINCR FIFO CNTR H

CONTROL *

UENB FIFO H

(PALS)

FIFO

SYNC

FIFO A ADDRESS>

ADDRESS

TRISTATE
BYTE

FIFO A

ENB FIFQ A

FIFO B

DRIVERS

FROM

MICROCONTROLLERY

USEL FIFQ 3

0L-¢

CLOCK CONTROL

FIFO B

MAX L

OVFLW

FIFO B ADDRESS

FROM

FIFO

FIFO B ADDRESS

COUNTER AND

CONTROL
N

CURRENT CLOCK L

ne FiFo 8

BUS OUT
UCLR DSR L

FROM
MICROCONTROLLER

* CONTROL OF FIFO A AND FIFO B

FROM SYNC

ADDRESS COUNTER AND CONTROL

BYTE RECOGNITION

IS SHARED WITH THE 1DC/CPU

LOGIC

INTERFACE LOGIC.

\74

ULOAD DSR

]
L

B(S):DH

WRT CHK LOAD DSR

DATA SHIFT REGISTER

FROM CLOCK
CONTROL

CURRENT CLOCK H
.

MTO HEADER/DATA

COMPARATOR
AND NRZ DATA
FORMATTER
TK-7267

Figure 3-19

Data and Sync Byte Serialization Control
Logic Functional Block Diagram

As the last zero bit of the data preamble is being written, the microcontroller asserts a UENB CONST
L signal to the sync byte tristate drivers that enables the CONSTANTS output of the microcontroller
(which has been preset to the appropriate sync byte pattern) to be asserted to the parallel input of the
data shift register. The microcontroller also asserts a ULOAD DSR L pulse which causes the sync byte
pattern to be loaded into the data shift register with the next positive transition of the CURRENT
CLOCK H input. When the data shift register is loaded, the first bit of the sync byte is asserted on the
DSRO output. Then, with the leading edge of each CURRENT CLOCK H input, each successive bit of
the sync byte pattern is asserted on the DSRO output.
During the interval that the last sync byte bit is being asserted, the microcontroller asserts the UENB

FIFO H signal and UINCR FIFO CNTR H pulse to the data buffer and data register control logic and
a ULOAD DSR L pulse to the data shift register. The UENB FIFO H input to the data buffer and

data register control logic is combined with the USEL FIFO (A or B) input to generate the ENB FIFO

(A or B) output. The ENB FIFO output is asserted to the selected FIFO where it enables the data byte
stored at the current FIFO ADDRESS location specified (ADDRESS 0) to be asserted to the parallel
input of the data shift register. At the data shift register, the ULOAD DSR L input enables the data
byte asserted from the selected data buffer to be loaded with the next positive transition of the CURRENT CLOCK H input.

Coincident with the loading of the data byte into the data shift register, the UUNCR FIFO CNTR H
pulse and CURRENT CLOCK L inputs to the selected FIFO address counter and control are combined to increment the FIFO ADDRESS. When the data byte is loaded (directly after the data interval

in which the last bit of the sync byte was asserted to the DSR 0 output), the first bit of the data byte is
asserted on the DSR 0 output. Then, with the leading edge of each CURRENT CLOCK H input, each
successive bit of the first data byte is asserted on the DSR 0 output.

During the data interval in which bit 7 of the first data byte and bit 7 of each successive data byte is
being asserted on the DSR 0 output, the microcontroller asserts a UINCR FIFO CNTR pulse to FIFO
A and B address counter and control and a ULOAD DSR L signal to the data shift register. The
ULOAD DSR L signal input to the DSR enables the data byte from the current FIFO ADDRESS to
be loaded into the disk address register with the next positive transition of the CURRENT CLOCK H
signal. The UINCR FIFO CNTR H pulse enables the FIFO ADDRESS asserted to the selected FIFO
to be incremented. When the FIFO ADDRESS has been incremented to 256, if an RLO2 disk drive is
selected, or 512, if the R80 disk drive is selected, the FIFO A address counter and control asserts a

FIFO MAX L signal to the microcontroller This signal signifies that after the next seven bits are asserted, the entire sector of data has been serialized and asserted on the DSR 0 output of the data shift
register. A timing diagram showing the relationship of the control signals used in serializing the data
from the data buffers and sync byte tristate drivers is presented in Figure 3-20.

During the write check function, the inputs from the microcontroller cause serialization of bytes 1
through 255 (RL02) or 511 (R80) of the data contained in the selected FIFO in the same manner as
discussed in the preceding two paragraphs. However, byte O of the data contained in selected FIFO is
loaded into the data shift register and the FIFO address counter is incremented as discussed in the

following paragraph.

The microcontroller is in a stall condition until after the sync byte preceding the read data to be com-

pared with the data from the selected FIFO has been located. Thus, before setting up the conditions for
locating the sync byte, the microcontroller asserts a UCLR FIFO CNTR H pulse to the data buffer and

data register control logic. The UCLR FIFO CNTR H input causes the ADDRESS asserted to the
selected FIFO to be reset to zero. The microcontroller then generates and asserts a UENB FIFO signal
to the data buffer and data register control logic. The UENB FIFO signal is combined with the USEL
FIFO (A or B) input to generate the ENB FIFO (A or B) output asserted to the selected FIFO. The
ENB FIFO signal enables the data contained at the current FIFO ADDRESS specified (ADDRESS 0)
to be asserted to the parallel input of the data shift register. At the same time that the microcontroller
asserts the UENB FIFO signal, it stalls until after the sync byte is found.
3-71

CURRENT CLOCK H

USEL FIFO

ULOAD DSR L

[

UENB CONST L

UCLR FiF O CNTR H l

AND SEQUENCE CLOCK H

{ L
1 F

{

Ly
BA
{

UENB FIFO H

UINCR FIFO CNTR H

1 |

CURRENT CLOCK L

}0— SYNC BYTE LOADED INTO DSR

l+— INCREMENT FIFO ADDRESS TO 1

|Q—— BYTE O LOADED INTO DSR

INCREMENT FIFO ADDRESS TO 2

HICREMENT FIFO

BYTE 1 LOADED INTO DSR...

BYTE 255~
LOADED

SERIALIZED BITS ASSERTED

ON DSRO OUTPUT OF

DATA SHIFT REGISTER

INTO DSR

TIOI1|2|3'4|5|6|7I0|1|2|3|4|516‘7l8‘9]10[11[12|13|---|2041|-~--|2048
~

LAST ZERO

SYNC BYTE BITS ASSERTED

—

DATA BITS ASSERTED

£ &

7’

BIT OF DATA
PREAMBLE

FIFO MAX LTM

* ASSUMES WRITING FULL SECTOR OF DATA
TO RLO2 (I.E., FULL SECTOR EQUALS 256

BYTES OF DATA): FOR R80, FULL SECTOR
EQUALS 512 BYTES OF DATA; THUS, FIFO
MAX L 1S ASSERTED AT ADDRESS COUNT

OF 512.
TK-1382

Figure 3-20

Data and Sync Byte Serialization Control
Logic Timing Diagram

When the sync byte is found, the sync byte recognition logic generates and asserts a WRT CHK LOAD
DSR L signal to the data shift register. The WRT CHK LOAD DSR L signal together with the next
positive transition of the CURRENT CLOCK H input loads the data byte asserted from the selected
FIFO into the dat. shift register. When the first byte is loaded, bit zero of the first data byte is asserted
on the DSR 0 output. With each successive positive transition of the CURRENT CLOCK H input,
each successive bit of the first data byte is asserted on the DSR 0 output.

While bit I of the first data byte is being asserted on the DSR 0 output, the microcontroller is again
started. When started, the microcontroller asserts a UINCR FIFO CNTR H signal to the data buffer

and data register control logic. The UINCR FIFO CNTR H
(A or B) and CURRENT CLOCK L

signal is combined with the USEL FIFO
inputs to increment the selected FIFO address counter, which

enables the second data byte from the FIFO to be asserted to the parallel input of the data shift register.

While bit 7 of the first and each successive data byte is being asserted on the DSR 0 output of the data
shift register, the microcontroller generates and asserts a ULOAD DSR L pulse to the data shift regis-

ter and a UINCR FIFO CNTR H pulse to the data buffer and data register control logic. These signals
cause loading of the data shift register and incrementing the FIFO ADDRESS as discussed for serializ-

ing the data from the data buffers during the write data function. This process is continued until the
FIFO MAX L signal from the FIFO A address counter and control is asserted to the microcontroller.
The FIFO MAX L signal indicates that the full sector of DATA contained in the selected FIFO has
been loaded into the data shift register.

3.5.12

Formatting and Loading Disk Drive Read Data in Data Buffers
During a read data function the read data tristate drivers and data buffer (FIFO A or FIFO B) are used

to convert the serial READ DATA input from the disk drive to byte format and to load the formatted
data into the selected FIFO. When a read data function is specified by the IDC control word input to

the IDC, the microcontroller selects the FIFO to be used by asserting the appropriate USEL FIFO (A
or B) signal to the data buffer and data register control logic (see Figure 3-21).
After the proper data sector has been located (header found and ECC or CRC pattern verified), the

microcontroller asserts a UCLR FIFO CNTR H pulse to the data buffer and data register control logic. The UCLR FIFO CNTR H input causes the address asserted to the selected FIFO to be reset to
zero. Then the microcontroller stalls until after the SYNC BYTE preceding the data portion of the
READ DATA has been located.

While the IDC is looking for the sync byte and after the sync byte is found, each bit of the data read

from the selected disk drive is asserted on the READ DATA H input to the read data synchronizer.
The READ DATA H input to the read data synchronizer is sampled at the midpoint of each data bit:

interval by the CURRENT CLOCK L input, and the condition of the READ DATA H input (a logical
0 or 1) is loaded into the read data synchronizer. A diagram showing the timing relationship of the
signals and events discussed in the following paragraphs is presented in Figure 3-22.
When the read data synchronizer is loaded, it asserts the sampled condition of the READ DATA H

input to the data shift register via the SERIAL DATA IN signal line. The CURRENT CLOCK H
input to the data shift register loads the SERIAL DATA IN signal asserted into DSR7 of the data shift
register and shifts the current contents of DSR7:1 to DSR6:0, respectively.

3-73

’

FROM

DISK DATA Mux HEAD DATA H_J gi/T\R

SERIAL DATA |

SYNCHRONIZER

SHIFT

CLOCK

CONTROL

T oRC

READ DATA

DSR7:0

TRISTATE
DRIVERS

CURRENT CLOCK H

MICROCONTROLLER

FIFO A

DATA

CURRENT

CLOCK L

FROM

BUS IN 7:0

BUS IN 7:0 >

TO MICROCONTROLLER
FIFO

FIFO

UENS DSR L

O\ZFLW L

Hro

-—:>

IWR!TE FIFO A L
FIFO B

PART OF DATA BUFFER
WRITE
FIFOB L

AND DATA REGISTER

CONTROL LOGIC

FROM DRIVE

vL-t

SELECT AND
DRIVE READY

MONITOR

(

R8O

USEL FIFO A H

UCLR FIFO CNTR H
UWRITE FIFQ H

FIFO A ADDRESS

COUNTER AND CONTROL®

FIFO A ADDRESS

UINCR FIFO CNTR H

(PALS)

FROM

WRITE FIFO A L

FIFO 8 MAX L

MICROCONTROLLER $

FIFO B ADDRESS

“*| COUNTER AND CONTROL*
FIFO B ADDRESS
USEL FIFO B H

WRITE FIFO B L

FROM CLOCK CURRENT CLOCK L

(PALS)

CONTROL

* CONTROL OF FIFO A AND FIFO B ADDRESS
COUNTER AND CONTROL IS SHARED WITH
THE IDC/CPU INTERFACE LOGIC.
TK7371

Figure 3-21

Read Data Formatting and Storage Control
Logic Functional Block Diagram

BIT 8 OF SYNC BYTE

4 BIT 1 OF READ DATA

BIT 8 OF READ DATA

" —y—t—

READ DATA H

SYN{C SEEN L

DSR 3

o
DSR O
~

e
|

]

e
B
1

I-“l

l_‘

—

N
:

CLOCK

UENB DSR L

IP={==—0sr 7.0s8 0 ouTPUTS
ASSERTED

TO INPUT OF FIFO A AND B

FIFO H

UINCR FIFO CNTR H

WRITE

I
|

e S

SEQUENCE

UWRITE

——

et I

BIT 16 OF READ DATA

—"

FIFO L

WRITE

FIFO—-""I

WRITE

[

FIFO'—:LI_-

CLOCK TO FIFO

ADDRESS COUNTER H

T—'NCREMENT ADDRESS

INCREMENT

E ADDRESS

TK-7389 -

Figure 3-22

Formatting and Loading Read Data
Input to FIFO: Timing Diagram

After the sync byte has been found, the microc
ontroller is restarted. The microcontroller
is restarted at
the same time that the first data bit of the READ
DATA H input is loaded into DSR7 of the data
shift
register. Once the microcontroller is restart
ed, it counts the number of CURRENT CLOC
K H pulses
asserted to control assertion of the UENB
DSR L, UWRITE FIFO H, and UINCR
FIFO CNTR H
outputs. (The
CURRENT CLOCK H pulses are derive
d from the read data input

chronized each data bit interval.)

and thus are syn-

During the data interval in which each eighth
data bit of the READ DATA is being loaded
into the
data shift register, the microcontroller genera
tes and asserts a UENB DSR
L signal to the read data
tristate drivers, and the UWRITE FIFO H
and UINCR FIFO CNTR signals to the FIFO
A and FIFO
B address counter and control of the data
buffers and data register control logic.

3-75

el output of the data shift
data tristate drivers enables the parall
The UENB DSR L input to the read
buffers. The UWRITE
input of the FIFO A and FIFO B data
register (DSR7:0) to be asserted to the
ss counter and control are
R inputs to the FIFO A and FIFO BL addre
FIFO H and UINCR FIFO CNT(A
to generate the WRITE
and CURRENT CLOCK inputs
combined with the USEL FIFOloadsortheB)data
drivers into the
asserted from the read data tristate the
FIFO (A or B) L signal, which to the selectbyte
ADDRESS
ment
FIFO address counter to incre
selected FIFO, and the clock input process (sampedling
sampled
the
ng
shifti
the READ DATA H input,
asserted to the selected FIFO. This ng and loading the
register
shift
data
the
parallel data output of
data into the data shift register, enabli ng the FIFO ADDR
eight
each
with
ed
ESS counter) is repeat
into the selected FIFO, and incrementi
read
being
are
has been incremented to 255 (if the data When the FIFOfrom
bits sampled until the FIFO ADDRESS are
adbeing read from the R80 disk drive).state of the R80 signal
an RLO2 disk drive) or 511 (if the dataa count
of 255 or 511 (depending on the
dress counter has been incremented to ), the addres
r and control asserts a FIFO MAX L siginput to the address counter and controlMAX L signals counte
tes that the data portion of one sector .of
nal to the microcontroller. The FIFO byte format and indica
has been loaded into the selected data buffer
READ DATA has been converted to
disk address register, and
s the CPU to control loading the CSR,
The IDC/CPU interface logic enableand
r, data buffers
to control reading the CSR, disk address registe
data buffers (FIFO A and FIFO B), logic.
data, or informa(Figure 3-23 defines the type of words,
(FIFO A and FIFO B), and ECC/CRC IDC regist
ace logic
ers and buffers.) Also, the IDC/CPU interfinterr
tion that is loaded into or read from the
upt
and R80 disk drive and to reset the UBUS BRS5
3.5.13

IDC/CPU Interface Logic

enables the CPU to initialize the IDC logicIDC/CPU interface logic is shown in Figure 3-24.
signal. A functional block diagram of the
LOAD

IDC CONTROL WORD

CONTROL

ISTER

IDC STATUS WORD
LOAD

e DISK DRIVE CONTROL WORDS

(RLO2 GET STATUS COMMAND)

(RLO2 CYLINDER DIFFERENCE)
(R80 SEEK COMMAND)

(R80 HEAD SELECT COMMAND)
(R80 RECALIBRATE COMMAND)

DISK

ADDRESS
REGISTER

e RLO2 READ/WRITE ADDRESS

e R80 READ/WRITE ADDRESS

DATA AND

READ

INFORMATION
TRANSFERRED
BETWEEN (DC
AND CPU VIA

CPU Y BUS

e CURRENT RLO2 READ/WRITE ADDRESS
e CURRENT R80 READ/WRITE ADDRESS
READ ONLY

e RLO2 STATUS INFORMATION
e R8O STATUS INFORMATION

e RLO2 HEADER
e

DATA

OUTPUT

R80 HEADER

e DATA (BYTE OR LONGWORD)
DATA

LOAD ONLY

e DATA (BYTE OR LONGWORD)
e R80 HEADER DATA

READ ONLY

e DATA ERROR INFORMATION

(ERROR POSITION)

(ERROR PATTERN)

]

FIFO A

FIFO B

INPUT

ECC/CRC

LOGIC

TK-7359

Figure 3-23

IDC Register Source and Destination

for Data and Information Transferred between
IDC and CPU via CPU Y-bus
3-76

TO/FROM

v BUS

MODULE < CPU Y BUS ,3L> TRANSCEIVERS
DATA PATH
IN

CPU

WRITE

CSR

i
I0C L

IDC

PORT CONTROL

PORT

CSR 14

CSR 13

IFN:J':UCTIONS

CSR

WCS MODULE
IN CPU

LL-¢

UBUS

PorT

(PAL}

MODULE

READ PORT]L

READ

PORT

SELECT

l"‘

FROM
WCS

CPU P2H

N CPU

CLOCK T
NOTE:

DATA INPUT
REGISTERS

REG BO:B3]

BUFFER AND DAIQNFZEEI%IS% g%NTROL

LOG
(SEE FIGURE

STROBE DATA H

BVTE

poalie

FORMAT
CONTROL

LOG!C

4
;

gg&%fio}g&gss

PINCR
[reo——#l

CONTROL®

ADDR%

PENB

{SEE NOTE)
(PALS]

ENB

FIFO

CPU

‘

PLOAD OUTREG|PSEL |PCLR

CLOCK

EAD

FETT

\’Q/'!::IJEA

FIFO

3-33 }

e ENABLE OUT REG L

READ

LOGIC

PWRITE _
INITIALIZE/CLEAR

mlé Si? LL

SEL WORD

SELBYTETL

—JEELACC IMH

DATA

PENB IN -

B0:63

FIFO

AUTOMODE H

PORT

DCLO

IN CPU

MODULE

DISK

CLEAR IDC L

__JDCLO

STROBE

DAR

ADDRESS
et

INSTRUCTION | WRITE DATA L
] DECODE
READ DATA L

SEL

BUS

PORT
MICRO

FROM
PATH

DAR

DATA

INSTR H

DATA

WRITE

CSR

RESET BR

CSR M
CSR 10

FROM

1/0

CONTROL L STATUS
L

LOGIC

CSR 17

MICRO-

BUS
SEL

ENABLE OUTREG

1DC L

PSEL FIFO B

SEL CSR L

[FIFO

DATA BUFFER

{FIFO A)

FIFO A

|PORT

(SEE NOTE)

|CLK

CNTR L

BUS

;

SUT
LOAD

OUF

ENABLE

8
ST

REG BO:83

OUTREG

SEL DAR L

REGISTERS

DATA

OUTPUT

[PSEL FIFO A H
PCLR FIFO CNTR H

(PAL)
[}

SEL POSITION L
SEL PATTERN L

PORT CLOCK L
CPU CLOCK H

:ggéCRPUACE
F

SYNCHRONIZER

SEL
PATTERN

P2 CLOCK L

» P2 CLOCK L (CPU CLOCK)
TO CLOCK CONTROL

ECC/CRC
LOGIC

SEL
POSITION
BUS 1/0

FOR SIMPLICITY, ONLY FIFO A ADDRESS COUNTER AND CONTROL AND FIFO A

DATA BUFFER IS SHOWN; IDENTICAL CIRCUITS EXIST FOR FIFO
B.

TK-7376

Figure 3-24

IDC/CPU Interface Logic Functional Block Diagram

For simplification, only the signals and control logic used for the control of one of the data buffers
(FIFO A) is shown (the FIFO A address counter and control and the FIFO A data buffer). Identical
logic exists for the control of FIFO B. Control of the FIFO A and FIFO B address counter and control
is shared by the microcontroller and the CPU. This allows the microcontroller to cause loading or reading of the data buffers while the CPU is loading or reading the other data buffer. The microcontrollerinitiated signal inputs to the FIFO A address counter and control are not shown in Figure 3-24. (CPU
control of the data buffers is discussed in Paragraphs 3.5.11 and 3.5.12).
The IDC/CPU interface logic is synchronized with the CPU by the CPU timing signal inputs (CPU P2
H and PORT CLOCK L). The P2 CLOCK L output of the IDC/CPU interface logic is the basic CPU
CLOCK signal used by the clock control to synchronize IDC operation with the CPU.
3.5.13.1 Loading CSR - The CPU causes loading of the CSR by asserting a WRITE CSR port microinstruction and a PORT INSTR signal to the port microinstruction decode register, and simultaneously
asserting the word to be loaded via the CPU Y BUS (see Figure 3-24).
The port microinstruction decode register decodes the PORT MICROINSTRUCTION input and generates and asserts a WRITE CSR L signal to the CSR. The low-to-high transition of the WRITE CSR
L signal input loads the word asserted on the BUS 1/O via the CPU Y BUS and the Y-bus transceivers
into the CSR.

Figure 3-25 shows a timing diagram illustrating the relationship of the PORT MICROINSTRUCTION, PORT INSTR, and CPU timing signal inputs to the IDC and the resultant signal
(WRITE CSR L) that loads the CSR.

__.’ (C2P7% ?‘nsfil):zocvcw l‘_

|Po|P1|P2‘|P0|P1|p2|PolP1|P2|Po|P1|

P2 CLOCK L |

wus v oar000 2222278900 ~sserten 7
B

o 1

s 0
PORT INSTR H

A T SR
|

WRITE CSR L

]__J‘LWORD ASSERTED VIA
CPU Y BUS LOADED
INTO CSR BY
POSITIVE TRANSITION

OF WRITE CSR L
TK-7355

Figure 3-25

IDC Control Word Transfer Timing (CPU to IDC)

3-78

3.5.13.2

Reading CSR - To read and transfer the contents of the CSR to the
CPU, the CPU asserts a
READ CSR port microinstruction and a PORT INSTR signal to the
read port interface select register,
followed during a later CPU microcycle by a READ PORT L signal
(see Figure 3-24). The READ
CSR port microinstruction is loaded into the read port interface select register
during clock phase 2
(CPU P2 H asserted) by the CPU CLOCK H input.

This conditions the read port select register such that a SEL CSR L output
signal will be enabled by
the READ PORT L signal input. When the READ PORT L signal
is asserted and the SEL ACC IN H
signal is not asserted (indicating that the READ PORT L signal is applicable
to the IDC), the read port
interface select register generates the SEL CSR L and READ IDC L outputs.
The SEL CSR L output
is asserted to the CSR where it enables the contents of the CSR to be asserted
on the BUS I/O. The
READ IDC L output is asserted to the Y-bus transceivers, where it enables
the word asserted on the
BUS 1/0 to be asserted to the CPU via the CPU Y BUS.
Figure 3-26 shows the timing relationship of the PORT MICROINSTRUCTI
ON, PORT INSTR,
READ PORT L, and CPU timing signals input to the IDC, the resulting
IDC control signals, and the
period during which the contents of the CSR are asserted to the CPU.

ICPU MICROCYCLE l
(270 nsec)

rorreroec

o |

| Pt

| P2

po|

P1|

L L ML L LML ML LU

cPu P2 n |

[ L

P2 cock L_|

(csn 17, csmcsn
10

I
R

A0 or

PORT INSTR H _
|

READ PORT L

READ IDC L

]

[

SEL CSR L

?;LSJS YY B$J3S1 :D00) ///////////////////////%‘ _W///////////////////////
CONTENTS OF CSR
ASSERTED TO CPU
TK-7361

Figure 3-26

IDC Status Word Transfer Timing (IDC to CPU)

3-79

3.5.13.3 Loading Disk Address Register — The CPU loads the disk address register by asserting a
WRITE DAR port microinstruction and a PORT INSTR signal to the port microinstruction decode
register, and simultaneously asserting the word to be loaded via the CPU Y BUS (see Figure 3-24).
The port microinstruction decode register decodes the PORT MICROINSTRUCTION input and generates and asserts a WRITE DAR L signal to the disk address register. The low-to-high transition ofthe
WRITE DAR L signal input loads the word asserted on the BUS 1/O via the CPU Y BUS and the Ybus transceivers into the disk address register.
Figure 3-27 shows a timing diagram illustrating the relationship of the PORT MICROINSTRUCTION, PORT INSTR, and CPU timing signal inputs to the IDC and the resulting signal
(WRITE DAR L) that loads the disk address register.

| po | p1 | P2 | po | P | P2 | po] Pt |P2]| PPt

|P2]Po]| P

]

CPU CLOCK H

PORT INSTR H

WRITE DAR L

L_l

L_]

.
—

P2 CLOCK L |

WORD ASSERTED VIA CPU

Y BUS LOADED INTO DISK
ADDRESS REGISTER BY
POSITIVE TRANSITION OF
WRITE DAR L
TK-7353

Figure 3-27

Disk Drive Control Word and Read/Write Address
Transfer Timing (CPU to IDC)

3-80

3.5.13.4

Reading Disk Address Register — To read and transfer the contents of the disk address regis-

ter to the CPU, the CPU asserts a READ DAR port microinstruction and a PORT INSTR signal to
the read port interface select register, followed during a later CPU microcycle by a READ PORT L
signal (sce Figure 3-24). The READ DAR rort microinstruction is loaded into the read port interface
select register during clock phase 2 (CPU P2 H asserted) by the CPU CLOCK H input. This conditions

the read port select register such that a SEL DAR L output signal will be enabled by the READ PORT
L signal input. When the READ PORT L signal is asserted and the SEL ACC IN H signal is not
asserted (indicating that the READ PORT L signal is applicable to the IDC), the read port interface
sclect register generates the SEL DAR L and READ IDC L outputs. The SEL DAR L output is asserted to the disk address register where it enables its contents to be asserted on the BUS I/0O. The
READ IDC L output is asserted to the Y-bus transceivers, where it enables the word asserted on the

BUS 1/0 to be asserted to the CPU via the CPU Y BUS.
Figure 3-28 shows the timing relationship of the PORT MICROINSTRUCTION, PORT INSTR,
READ PORT L, and CPU timing signals input to the IDC, the resultant IDC control signals, and the
period during which the contents of the disk address register are asserted to the CPU via the CPU Y

BUS.

CPU MICROCYCLE

(270 nsec)

P1|P2|POIP1|P2|POIP1|P2|PO|P1|P2‘

lPO

rorrcocke |
cruP2H

L LML L L LWL L L Lo

[ L

[

P2 cLOCK L_|

PORT INSTR H_|
READ PORT L

i
l

READ IDC L

‘ I

SEL DAR L

wusv 31000 222728

777777

CONTENTS OF DISK ADDRESS
REGISTER ASSERTED TO CPU
TK-7357

Figure 3-28

Current Read/Write Address Transfer Timing
(IDC to CPU)

3-81

3.5.13.5 Reading ECC/CRC Logic — To read and transfer the contents of the ECC/CRC logic to the
CPU, the CPU asserts a READ POSITION or READ PATTERN port microinstruction, as applicable, and a PORT INSTR signal to the read port interface select register, followed during a later CPU
microcycle by a READ PORT L signal (see Figure 3-24). The READ POSITION or READ PATTERN port microinstruction is loaded into the read port interface select register during clock phase 2
(CPU P2 H asserted) by the CPU CLOCK H input. This conditions the read port select register such

that a SEL POSITION L or SEL PATTERN L, as applicable, output signal will be enabled by the
READ PORT L signal input. When the READ PORT L signal is asserted and the SEL ACC IN H
signal is not asserted (indicating that the READ PORT L signal is applicable to the IDC), the read port
interface select register generates the appropriate SEL POSITION L or SEL PATTERN L and
READ IDC L outputs. The SEL POSITION or SEL PATTERN L output is asserted to the
ECC/CRC logic where it enables the contents of the ECC position register or ECC pattern register, as
applicable, to be asserted on the BUS 1/O. The READ IDC L output is asserted to the Y-bus transceivers, where it enables the word asserted on the BUS I/O to be asserted to the CPU via the CPU Y
BUS.

Figure 3-29 shows the timing relationship of the PORT MICROINSTRUCTION, PORT INSTR,
READ PORT L, and CPU timing signals input to the IDC, the resulting IDC control signals, and the
period during which the contents of the ECC/CRC logic are asserted to the CPU.

CPU MICROCYCLE l__
(270 nsec)

|'P0|P1|P2|P0|P1|pz|po|p1|p2]Po|P1|P2|Po|P1|P2|

PORT CLOCK
L

| |

CPU P2 H

CPU CLOCK H

2 cuooeL_|
(Gon 17, COR 14.CoR 10

| |

| I

| |

| | I

| I

| | |

I
| |

| |

|
l

l |

l l

READ PATTERN 1

ZZLREAD POSTION

PORT INSTR H_|

READ PORT L

READ 10C L

[

SEL POSITION L

SEL PATTERN L

o S

| |

CONTENTS OF ECC POSITION
REGISTER ASSERTED TO CPU

CONTENTS OF ECC PATTERN
REGISTER ASSERTED TO CPU
TK-7356

Figure 3-29

Data Error Information Transfer Timing (IDC to CPU)

3-82

3.5.13.6
Loading IDC Data Buffers - The CPU to load the IDC data buffer(s), the CPU
selects the
data buffer to be used (asserts a SELECT FIFO A or SELECT FIFO B port microinstru
ction and
PORT INSTR signal) and clears the FIFO address counter and control logic
(asserting a CLEAR
FIFO CNTR port microinstruction and PORT INSTR signal). Then the CPU
asserts a WRITE

DATA BYTE or WRITE DATA WORD port microinstruction and PORT INSTR
signal while simultaneously asserting via the CPU Y BUS the data byte or data longword to be
loaded. The CPU must
load the data buffer with a full sector of data [256 data bytes (64 data longwords),
one full sector of
RLO2 data; or 512 data bytes (128 data longwords), one full sector of R80 data].

The read port select register decodes the SELECT FIFO A port microinstruction

and generates and
asserts a PSEL FIFO A H signal to the FIFO A address counter and control (see Figure
3-24). The
read port select register decodes the CLEAR FIFO CNTR port microinstruction and generates
and
asserts a PCLR FIFO CNTR H pulse to the FIFO A and FIFO B address counter
and control.

The PSEL FIFO A H signal and PCLR FIFO CNTR H pulse initiates resetting
DRESS asserted to the data buffer (FIFO A).

of the FIFO A AD-

The port microinstruction decode register decodes the WRITE DATA BYTE or WRITE
DATA
WORD PORT MICROINSTRUCTION input and generates and asserts a STROBE
DATA H pulse
to the data input registers and a WRITE DATA L pulse to the data format control logic.
If the PORT
MICROINSTRUCTION input was WRITE DATA BYTE, the port microinstruction decode
register
also generates and asserts a BYTE L pulse to the data format control logic.

The STROBE DATA H pulse loads the data longword or data byte asserted on the BUS

I /O via the
CPU Y BUS and Y-bus transceivers into the data input registers. THE WRITE DATA L and
BYTE L
inputs to the data format control logic enable the proper sequence of control signals required
to load the
data byte input into the selected FIFO, or to convert the data longword input to four data
bytes and
load each of the four bytes into four contiguous storage locations of the selected FIFO.
If a data byte is to be loaded into FIFO A, the WRITE DATA L and BYTE L inputs
to the data
format control logic are used with the CPU CLOCK H input to enable the PENB INREG
BO,
PWRITE FIFO, and PINCR FIFO CNTR outputs. The PENB INREG BO signal enables
the contents of INREG BO of the data input registers to be asserted to the inputs of FIFO A and FIFO B. The
PWRITE FIFO and PINCR FIFO signals are asserted to the FIFO A address counter
and control
where they are used with the PSEL FIFO A and PORT CLOCK L inputs to produce a WRITE FIFO
A L signal. The WRITE FIFO A L signal loads the data byte asserted from the data input register. The
PSEL FIFOA and PORT CLOCK L inputs also produce a clock input to the FIFO A address counter
to increment the ADDRESS asserted to FIFO A.

Figure 3-30 shows the timing relationship of the CPU timing signals, PORT MICROINSTRUCTION,

PORT INSTR, and CPU Y BUS inputs to the IDC and the resulting control signals that are generated
in loading FIFO A with the first data byte of the sector of data to be loaded.
If a data longword is to be loaded, the WRITE DATA L input to the data format control logic enables
the series of PENB INREG B0:B3, PWRITE, and PINCR FIFO CNTR signals that enable the data

longword input to be assembled into four data bytes and loaded into four contiguous storage locations
within FIFO A.
Figure 3-31 shows the timing relationship of the CPU timing signals, PORT MICROINSTRUCTION,

PORT INSTR, and CPU Y BUS inputs to the IDC and the resulting control signals that cause loading

into the data buffer the first data longword of the sector of data to be loaded.

3-83

‘.’cpu MICROCYCLE "‘
(270 nsec)

'IPO!P1|P2lP0|P1|P2|PO|P1|P2|P0|P1‘P2|PO|P1|P2|PO‘P1|P2‘P0‘P1'P2|

PORT CLOCK L | |

| I

cPu P2 H |
cPU CLOCKHl

P2 CLOCK L |

v8-t

esw 17, csmarcsn
101

| |

I |

[

|
1

| |

1
|

| |

l | |

[

| I | | |
f
|

| | l | | |

[
|

| | |

| |

J—L__
|

LSe<ecT feo I
A e vivo TR
A e onA BT

PORT INST W |

PSEL FIFO A H

]

V
DATA BYTE LOADED INTO DATA INPUT

STROBE DATA H

FZ:},—REGISTER

WRITE DATA L
AND BYTE L

PENB

INREG

DATA BYTE ASSERTED TO FIFO A

BO L

l_-l

PWRITE FIFO H
AND PINCR FIFO CNTR H

]:jz— DATA BYTE

WRITE FIFO A L

LOADED

INTO FIFO A

U“Z—FIFO ADDRESS INCREMENTED

féglggséNggJNT‘l'oE;)lFo A

TK-735

Figure 3-30

Data Byte Transfer Timing (CPU to IDC)

CPU MICROCYCLE
(270 nsec)

|P0|P1|P2‘P0|P1IP2|POIP1|P2lP0|P1|P2lPOlPIIP2|PO!P1IP2IPOIP1IP2|

cPuPzH
]

P2 CLOCK L _]

[ L

[

wusv o31.000 o
P
o T
O

R 1

st FiroO
cieas i v 7222222777
e e onra worndlll

PORT INSTR H _ |
PSEL FIFO A H

]

PCLR FIFO CNTR H

¢8-¢

FIFO A ADDRESS COUNTER
T
R o]

ESET

TO zE

DATA LONGWORD LOADED INTO

STROBE DATA H

Zf DATA INPUT REGISTER

WRITE DATA L

BYTE CONTAINED IN INREG BO ASSERTED TO
FIFO A

PENB INREG BO L

BYTE CONTAINED IN INREG B1 ASSERTED TO FIFO A w_

PENB INREG B1

BYTE CONTAINED IN INREG B2 ASSERTED TO FIFO A N
PENB INREG B2 L

BYTE CONTAINED IN INREG B3

PENB INREG B3 L

ASSERTED TO FIFO A

PWRITE FIFO A H
AND PINCR FIFO CNTR H

[

LOAD FIFO A

{CLOCK INPUT TO FIFO A

A DDRESS COUNTER)
NTER

[;

INCREMENT

FIFO A ADDRESS
COUNTER
TK-7383

Figure 3-31

Data Longwood Transfer Timing (CPU to IDC)

by selecting the data
The CPU reads the IDC data buffer(s) nstruc
3.5.13.7 Reading IDC Data Buffers — FIFO
tion and PORT
A or SELECT FIFO B port microi
buffer to be used (asserting a SELECT
FIFO CNTR
R
CLEA
control logic (asserting a
INSTR signal), and clearing the address counter .and
BYTE or
DATA
Then the CPU asserts a READ
port microinstruction and PORT INSTR signal) PORT
microCPU
later
a
INSTR, followed during
READ DATA WORD port microinstruction and
cycle by a READ PORT L signal.

and clears the FIFO address counter, the CPU may
After the CPU selects the data buffer to be read
by asserting the applicable READ DATABYTE
read a single byte or data longword or a series of themPORT
signal, followed during a later CPU
or READ DATA WORD port microinstruction and byte INSTR
or data longword to be read. For reading a
microcycle by a READ PORT L signal for each dataCPU interfa
ce logic to the AUTOMODE, which
series of data longwords, the CPU may preset the ng only a READ
PORT L signal for each succesenables a series of data longwords to be read by asserti the AUTOMODE
function by asserting a SET
sive data longword to be read. The CPU may preset
AUTOMODE port microinstruction and PORT INSTR signal.

FIFO A PORT MICROINSTRUCTION input and
The read port select register decodes the SELECT
A address counters and control (see Figure
generates and asserts a PSEL FIFO A H signal to the FIFOCLEA
FIFO CNTR PORT MICRO3-24). The read port select register decodes the FIFOR CNTR
H pulse to the FIFO A and
INSTRUCTION input and generates and asserts a PCLR
FIFO CNTR H pulse
PCLR
the
and
FIFO B address counter and control. The PSEL FIFO A Hthesignal
data buffer (FIFO A).
initiates resetting of the FIFO A ADDRESS asserted to

port microinstruction is decoded by the port miThe READ DATA BYTE or READ DATA WORD DATA
L and BYTE L outputs or READ DATA
croinstruction decode register to produce the READ
DATA WORD port microinstruction is
L output, respectively. The READ DATA BYTE or READ input
enable the SEL BYTE L or SEL
oning
also loaded into the read port select register as a conditi signal istoasserted
during a following CPU
L
WORD L output, respectively, when the READ PORT
microcycle.

microinstruction decode register are asserted to
The READ DATA L and BYTE L outputs of the portand
or BYTE L inputs enable the data format
the data format control logic. The READ DATA L
that cause gating of a single data byte
sigrals
control logic to generate the proper sequence of output
or cause gating of a series of four
registers
from FIFO A and loading the data byte into the data output
loading the four data bytes in a
and
FIFO
the
within
s
data bytes from four contiguous storage location
longword format into the data output registers.

3-86

If a data byte is to be read, the READ DATA L and BYTE L inputs to the data format control logic
are used with the CPU CLOCK H input to enable the PENB FIFO, PLOAD OUTREG BO, and
PINCR FIFO CNTR outputs. The PENB FIFO signal is asserted to the FIFO A address counter and
control where it is combined with the PSEL FIFO A input to produce the ENB FIFO A output. The
ENB FIFO A signal is asserted to FIFO to enable the data byte contained in the current address location (specified by the ADDRESS input) to be asserted to the input of the data output registers. The
PLOAD OUTREG BO output of the data format control logic is asserted to the data output registers to
cause loading of the data byte asserted from FIFO A into rcgister BO of the data output registers. The
PINCR FIFO CNTR output of the data format control logicis asserted to the FIFO A address counter
and control where it is used with the PSEL FIFO A and PORT CLOCK L inputs to generate a clock
signal to increment the ADDRESS asserted to FIFO A.

If a data longword is to be read, the READ DATA L input to the data format control logic is used with
the CPU CLOCK H input to enable the PENB FIFO, PLOAD OUTREG BO0:B3, and PINCR FIFO
CNTR outputs. The PENB FIFO and PINCR FIFO signals are asserted to the FIFO A address
counter and control. The PENB FIFO signal is combined with the PSEL FIFO A input to produce the
ENB FIFO A output, which is asserted to FIFO A to enable the data byte contained in the address
location specified by the ADDRESS input to be asserted to the input of the data output registers. The
PINCR FIFO CNTR signal is combined with the PSEL FIFO A and PORT CLOCK L inputs to gen- erate a series of four clock pulses to sequentially increment the ADDRESS asserted to FIFO A and
thus enable the data bytes from four contiguous address locations to be asserted to the data output
registers. The PLOAD OUTREG B0 through PLOAD OUTREG B3 outputs of the data format control logic are enabled sequentially to enable the data bytes from the four contiguous addresses to be
assembled into a data longword format in data output registers.
When the READ PORT L signal is asserted, following the READ DATA WORD or

READ DATA
BYTE port microinstruction, and the SEL ACC IN H is not asserted (indicating that the READ
PORT L signal is applicable to the IDC), the read port select register generates the applicable SEL

BYTE L or SEL WORD L and READ IDC L outputs. The SEL BYTE L or SEL WORD L output
- produces an ENABLE OUTREG L signal. The ENABLE OUTREG L signal is asserted to the data
output registers to enable the contents of the data output registers to be asserted onto the BUS I/0.
The ENABLE OUTREG L signal is also asserted to the port microinstruction decode register. The

READ IDC L output is asserted to the Y-bus transceivers to enable the data byte or data word on the
BUS 1/0 from the data output registers to be asserted to the CPU via the CPU Y BUS.
If the AUTOMODE function had been preset by a PORT MICROINSTRUCTION input to the read
port select register, then the AUTOMODE H and the ENABLE OUTREG L inputs to the port microinstruction decode register will initiate a WRITE DATA L output signal. The WRITE DATA L output
reinitiates loading of the data output registers with the next data longword to be read.
Figures 3-32 and 3-33 show the timing relationship between the CPU PORT MICROINSTRUCTION,
PORT INSTR, READ PORT L and timing signal inputs to the IDC, the resulting IDC control signals
and the period during which the requested data byte or data longword, respectively, is asserted to the

CPU via the CPU Y BUS. Figure 3-34 shows the timing for data longword transfers to the CPU using
the AUTOMODE function.

3-87

‘

CPU MICROCYCLE

[*(270 nsec)
+|

lrolpPtipP2lrolPtiP2lrPolPIIP2iPol
PrIpP2lpPotl PrIpP2IPOlPILP2IPOlPIIP2IPOlPIIP2IPOIPIIP2IPOlPY] P2I

eort cock L LM
oz

U U U U UV U UUU U

[ LT

coccockw [LMTUU U U
P2 CLOCK L

SELECT FIFO A

U U

U U U
4

VUL U UV
U

CLEAR FIFO CNTR

vuuUL
rr_rn_r11

UUUUvuuuuwyr
u

READ DATA BYTE

PORT INSTR ”_J—l___’_l__l——_l
PSEL FIFO A H

88-t

FIFO A ADDRESS COUNTER RESET TO ZERO
PCLR FIFO CNTR H

READ DATA L

AND READ BYTE L

AND PINCR FIFO H
PLOAD OUTREG

]

‘LJ+—Lo0aD

fiégcf X\IJDFI,Z)URTE;-SOCOUNTER)

READ PORT L

ouTREG

WINCREMENT FIFO A ADDRESS
I

READ IDC L AND

ENABLE OUTREG L

L__'I
DATA BYTE ASSERTED TO CPU

CPU Y BUS

(8Us v 007:000 2

.
e
TK-7391

Figure 3-32

Data Byte Transfer Timing (IDC to CPU)

CPU MICROCYCLE

|o(27o nsec) |

lpolpPt
PIP2lPOl PIIP2IPOlPI|P2iPOlPilP2
ip2irol
lPol PIEP2IPOtPIIP2IPOl P1IP2I PO PIIR2]POlPTHE
P2I
PORT CLOCK

eorw|

P2 cLock L |

PORT MICROINSTRUCTION
(CSR 17, CSR 14:CSR10)

SELECT FIFO A

PORT INSTR H I

L
.

PSEL FIFO A H

CLEAR FIFO CNTR

rn.rn.ro

READ DATA WORD

e\
I

l
FIFO A ADDRESS COUNTER RESET TO ZERO

PCLR FIFO CNTR H

READ DATA L

PENB FIFO AND

PINCR FIFO CNTR H

PLOAD OUTREG

BO L

PLOAD OUTREG

B1 L

PLOAD OUTREG

B2 L

PLOAD

1_4=—=Loa0 FirsT BYTE

L_J == oap seconp ByTE
L_}=—= Loap THIRD BYTE

OUTREG B3 L

"= 1oaD FouRTH BYTE

ENB FIFO A L

(CLOCK INPUT TO FIFO A

ADDRESS COUNTER)

| { I ! l £ | é

INCREMENT FIFO A ADDRESS WIiTH

EACH POS TRANSITION

READ PORT L

ENABLE

OUTREG

I___J

READ iDC L

(BUS Y D31:D00)

it R

—

DATA LONGWORD

ASSERTED TO CPU
TK-7393

Figure 3-33

Single Data Longword Transfer Timing (IDC to CPU)

3-89

CPU MICROCYCLE

fo-{270 nsec)|

Irolprlir2lpolpiip2irolpilp2lpolPile2zirolPilezleolpile2lpoleilpzlprol Prilr2lprol
Prlp2ipol
eilp2ipol
Piip2lpol P11 p2l
PORT CLOCK

curznl

P2 CLOCK L |

SELECT FIFO A

oan 1 cenvacso|
poRTNsTRHS

PSEL FIFOAH—

[TL_

CLEAR FIFO CNTR

.
|

SET AUTOMODE

[

j_[

READ DATA WORD

|
FIFO A ADDRESS COUNTER

PCLR FIFO CNTR H

[
Jo—=—RESET TO ZERO

AUTOMODE H

[

READ DATA L

(

L_J

PENB FIFO H AND
PINCR FIFO CNTR H

PLOAD OQUT REG BO L
PLOAD OUT REG B1 L

LOAD

PLOAD

ou OUT RE G B2 L

PLOAD OUT REG B3 L

l LOAD FIRST BYTE

LOAD FIFTH BYTE Lfi'

ILOAD SECOND BYTE

LOAD SIXTH BYTE
{

LOAD THIRD BYTE
LOAD
U.V,
L-LS/EVENTH
BYTE’

ILOAD FOURTH
BYTE
v

ILOAD
.EI/GHTH

BYTE

ENABLE FIFO A L

(CLOCK INPUT TO FIFO A
ADDRESS COUNTER)

READ PORT L

ENABLE OUT REG L

READ 1DC L

[

l__r_—U

s v o31-000) 2.
.
)

FIRST DATA LONGWORD
ASSERTED TO CPU

Figure 3-34

SECOND DATA LONGWORD

ASSERTED TO CPU

Automode Data Longword Transfer Timing (IDC to CPU)

3.5.13.8
Initializing/Clearing IDC and R80 Disk Drive — The IDC and R80 disk drive may be initialized under CPU control or initialized automatically following an interruption of operating voltages

from the VAX-11/730 power system. A logic diagram of the initialize /clear logic is shown in Figure 335S.

When a CLEAR IDC port microinstruction is asserted to the IDC, the resulting CLEAR IDC L signal,

a 270 nanosecond pulse, is asserted to the initialize/clear logic. The CLEAR IDC L input is loaded into
flip-flop 1 by thc P2 CLOCK L input and transferred to flip-flop 2 by the second P2 CLOCK L input.
The output of flip-flop 2, a 270 nanosecond positive pulse, is the initialize signal for the IDC and R80
disk drive.

3-90

POWER
INTERRUPTED

P2 CLOCK L

P2 CLOCK L
l

DCLO L

CLEAR 1DC L__L_f

| I

U
U u
je—— -~ 100 usec ———o]

FF1

FF2

INIT H

R8O INITIALIZE H

FF1

16-¢

R80 INITIALIZE H

POWER
RESTORED

INIT H

FROM CPU

UBUS DCLO L

q\/DCLO H

DG
D

i> O

—

INIT L

FF2

FF1
]

CLEAR IDC L

R80

FROM 1DC/
CPU INTERFACE
LOGIC

DRIVER

R80 INITIALIZE _ TO R80

DISK DRIVE

P2 CLOCK L
TKE713

Figure 3-35

Initialize/Clear Logic Diagram

The UBUS DCLO L input to the initialize /clear logic is asserted when dc power to the VAX-11/730 is
interrupted or goes out of tolerance. Following the power interruption, DCLO L is held asserted until
approximately 100 microseconds after dc power has been restored. During the period between restoration of dc power and deassertion of DCLO L, and for two CPU microcycles following deassertion of
DCLO L, the initialize/clear logic holds the INIT H, INIT L, and R80 INITIALIZE signal outputs
asserted.

The timing diagram in Figure 3-35 shows the interval of assertion of the INIT and R80 INITIALIZE
outputs relative to the CLEAR IDC L and DCLO L signals asserted.
3.5.14 Microcontroller Branching, Loops, and Stalls
The microcontroller consists of eight 512 X 8 PROMs, branch enable multiplexers, loop counter, and
microfunction decoders (see Figure 3-36). The eight 512 X 8 PROMs are addressed in parallel, which
provides a 512 X 64 PROM with 512 addressable locations. Each address provides a unique 64-bit
microword output. The microword output is made up of the following:
e

Nine “next address” bits (NAD 8:0)

Two loop counter control bits (ULOAD LOOP CNTR and UINCR LOOP CNTR)

NAD 0
NAD 1
NAD 2

NAD 8:NAD 3

JAM H

NAD 8:NAD 3

NAD 2
o
MISMATCH L

DRIVE ERR

)

OP!

MAINT

NUA 1
NUA 0

BRANCH

3 EnABLE

ASS|
R80 FORMAT

]

. Mux
6

6
7

UINCR JULOAD
LOOP |LOOP

BEN2 SO, St, S2

CNTR

NUA 1

g BRANCH |,
©

g
z

ENABLE £

s MUX

FIFO MAX

EIFO OVFLW

ONLINE

Swa 0

”

[eT

MICROWORD

XFER _REQ

CRC/ECC ERROR

o
&

[CNTR

NAD 10

SYNC SEC PLS

512 X 64 PROM

NUA 2

MICROFUNCTION

| pEcoDERs

L, |

)

BEN1 SO, St, S2

12 BIT

MICROWORD

[a]

NAD 0
DRIVE RDY

CRDY

RS0

RB0 SYNC INDEX PLS
CSSE

CNTR OVFLW

BRANCH

>3 ENABLE
¥1?
>

]

MuX

CONSTANTS
BENO SO, S1, 52
FLW
CNTR OVFL

SEQUENCE CLOCK H

LoOP
COUNTER

UDRV]

SEL

JUDRV

SEL 0

[UDRV

|SEL 1

47 BIT

MICROWORD

(CONTROL SIGNALS)

\V
TK-7353

Figure 3-36

Microncontroller Functional Block Diagram

3-92

An eight-bit selectable constant (CNST 7:0)

Nine branch enable bits (BEN 2 S0, S1, and S2; BEN 1 SO, S1,
and S2; and BEN 0 S0, S1,

and S2)
e

Four microfunction bits (UFUNC 3:0), a 47-bit microword

The 47-bit microword output is made up of a 32-bit microword from

the 512 X 64 PROMs, the UDRV
SEL, UDRV SEL 0, and U DRV SEL 1 bit outputs of the loop counter,
and the 12-bit microword
output of the microfunction decodes.

The nine “next address” bits are used as the base address in formulating the

next address for the 512 X
64 PROM. The nine branch enable bits specify which (if any) branch conditions
are examined to modify the three least significant bits of the base “next address.”

The two LOOP CNTR control bits are used to load the loop counter with
cnable the loop counter to be incremented by the SEQUENCE CLOCK

The eight-bit CONSTANTS output is used to present the loop counter and
patterns.

a selectable constant and

input.
to generate the sync byte

The four microfunction bits are decoded in the microfunction decoders to provide

a 12-bit microword.

The 12-bit microword output of the microfunction decoders, the drive select bit
outputs of the loop
counter, and the 32-bit microword output of the 512 X 64 PROM provide a 46-bit
microword output of
the microcontroller, which provide the control signals for the IDC.
3.5.14.1

Microcontroller Branching - The microword output from the IDC microcontroller
is determined by the address input to the 512 X 64 PROM. The address is derived from
the six most significant “next address” bits output from the PROMS (NAD 8:3) and the three “next
microaddress” bits
output from the branch enable multiplexers (NUA 2:0). The next microaddress
bits are derived from
the next address (NAD 2:0) or any one of the conditional inputs asserted to the
microcontroller branch
enable multiplexers. Each of the three branch enable multiplexers may select any
one of the inputs to
be asserted on the associated NUA signal line. The signals selected allow the three least
significant
address bits to enable an eight-location multiway branch.

3.5.14.2
Microcontroller Loops — The microcontroller may be made to loop on one or a series of addresses until a specific branch condition is satisfied.
3.5.14.3

Microcontroller Stalls - Microcontroller stalls are caused by interrupting the SEQUENCE
CLOCK input. Once the microcontroller is stalled, it remains in the microstate initiated
before the
clock was interrupted until the SEQUENCE CLOCK input is reasserted.

3.5.15
Read Data Separator Operation
The read separator (Figure 3-37) converts MFM-encoded RL READ DATA into an IDC compatible

format (NRZ). It also generates the DS CLOCK used to synchronize IDC operation with the timing of
RL READ DATA inputs.

The data stream transferred from the disk (RL02) to the IDC consists of composite clock and data bits.

With single density, a data bit is decoded by a data window that is generated from the clock bit. In
double density, the lack of consistent clock bits makes it impossible to generate a data window in this
manner. Instead, to separate clock and data bits the data separator circuit must first determine their
nominal position and then generate a clock and data window that is centered around the bit positions.

3-93

PHASE-LOCK LOOP

UMAINT H
WRITE

DATA L

(V8

UMAINT L

ERROR

v6-¢

RLO2H

COMPARATOR

SHAPER

DATA L

UENB LOOP LOCK H

PHASE

PULSE

RL READ

INTEGRATOR SIGNAL

VOLTAGE
CONTROLLED
0SC.

8.2 MHZ

VCO H

|__FAST

DATA

LOCK L

SEPARATOR

——DS CLKH

DS DATAH

SEL DSK CLK H
CRDY L
TK-8670

Figure 3-37

Read Data Separator Block Diagram

To determine the nominal bit position around which to center the window, the data separator
must
track data bit frequency changes. It uses the phase relationship between a bit and its window
to vary
the position of the window. In this way, even if an unpredictable bit shift occurs, the read data
separator
can adjust the window’s position to compensate for the change.

Since a data pulse may occur at either the center or boundary of a bit cell, its location remains
unpredictable for random data patterns. The only consistent pattern that may be used as the basis
for data
separation (MFM to NRZ) is the fact that MFM encoding guarantees that there will be
at least one
flux reversal on the disk for every two bit cells. This fundamental frequency makes it feasible
to use
phase lock loop techniques to form a self-clocking read data separator.
3.5.15.1
Phase Lock Loop (PLL) - The PLL is a closed loop circuit that locks onto the basic frequency of data bits (RL READ DATA L) read off the disk, and provides an output (8.2 megahertz
VCO H)
that is in phase anad frequency locked with the input data. Its output frequency is twice that of the
incoming RL READ DATA bit rate. A simplified block diagram is shown in Figure 3-37. The input
data to the pulse shaper can come from two different sources. The WRITE DATA L line provides a
data path between the write precompensation circuit and the pulse shaper. This data path is
used during the maintenance command as a means of sending write data back into the read circuits. The PL
READ DATA L line is the data path followed when reading data off the disk. The RL READ DATA

L pulses are standardized in the pulse shaper to a uniform 60 nanosecond pulse width and applied to the
phase comparator and data separator. The other input to the phase comparator is the inverted output of

the voltage-controlled oscillator (8.2 megahertz VCO H).

In the phase comparator, the phase of the RL READ DATA L pulse is compared with that of the VCO
output (8.2 megahertz VCO H) as is illustrated in Figure 3-38A. The phase comparator then generates

two signals (pulses) equal in duration to the phase difference: UP L if the VCO output (8.2 megahertz

VCO H) is less than twice the data rate (Figure 3-38B) or DOWN L if the VCO output is more than
twice the data rate (Figure 3-38C). If the VCO output is less than twice the data rate the VCO should

speed up. Hence UP L is asserted and its width represents the magnitude of the speedup required. The

same is true for slowdown if the VCO output is more than twice the data rate, (DOWN L asserted).
These phase error outputs (UP L and DOWN L) are applied to the integrator, which generates the
small error offset voltages required to control the VCO frequency and maintain loop lock.

RL EEASD Ds/:m’EORUTPUT—I_I

PULSE

PRESET INPUT TO UP

&8.2DOWN
FLIP FLOP
MHZ
VCO H

AT TWICE DATA RATE

RL READ DATA INPUT —‘

TO PULSE SHAPER

RL READ DATA OUTPUT

1_"—

OF PULSE SHAPER
PRESET INPUT TO

, |

j I 1 I
TLLM L

"
DOWN L

Figure 3-38a

LOW

]

U
|

1_11:—
l

L_1

INTEGRATOR OUTPUT __/—
TK-8669

VCO Output at Twice Data Rate

(Frequency Lock)

—

Tx 868

LOW

DOWN L

__]

suzp :HDZO\V/V:OF: AT LESS
mantwicenata
RATE

RL READ DATA INPUT '—I_J

TO PULSE SHAPER

Timing Diagram

Figure 3-38b

_
VCO Output Less Than Twice

Data Rate Timing Diagram

3-95

RL READ DATA INPUT

TO PULSE SHAPER

RL READ DATA OUTPUT

OF PULSE SHAPER

l I

UP & DOWN FF

PRESET INPUT TO

|]
J

—

8.2 MHZ VCO H AT MORE

FLALSL
|f
rian rwice oata rateLFLFLFLFLFFLFL
HI

uPL

DOWN L

] r

INTEGRATOR OUTPUT _—_\___
TK-8667

Figure 3-38¢

VCO Output More Than Twice Data Rate
Timing Diagram

The integrator converts the UP L. and DOWN L signals to an error voltage. The output (errror voltage)
of the integrator is raised or lowered proportionally to the area under the UP L or DOWN L pulse (the
integral of the pulse). Since the amplitude of the UP L and DOWN L pulses is fixed and the duration
represents the amount of phase error, the change in error voltage due to the area under the pulse is also
proportional to the phase error. The integration time constant (the rate at which the error voltage is
allowed to change) is chosen such that the system will track long term frequency variations of the input
but not respond to individua | peak-shifted bits.

The voltage-controlled oscillator generates an output signal (8.2 megahertz VCO H) whose frequency is
proportional to the voltage (error voltage) applied.
Figure 3-39 illustrates the relationship between the read data and the phase lock loop settling time. The
phase lock loop is designed to lock onto read data frequency within four byte times.

— SECTOR
e |,
e

e
s}+—

SYNC
BYTE

ADDRESS —]
(SECTOR

HEADER
BYT I CYLINDER)

)

ZEROS

jg———— SETTLING TIME —»i

)

ERROR
VOLTAGE

|
|

4 BYTE TIMES ALLOWED FOR VCO FAST LOCK

TO VCO
TK-8666

Figure 3-39

Loop Lock Settling Time

3-96

3.5.15.2

Data Separator — The data separator examines the incoming data stream and separates the
pulses into DS DATA or DS CLOCK. A detailed diagram of the data separator is illustrated in Figure
3-40 and its timing sequence is illustrated in Figure 3-41.

When a read header command is decoded and the SYNC SECTOR PLS is detected, the header preamble from the selected drive appears on the RL READ DATA L line. The assertion of RLC2 H and

UENB LOOP LOCK H allows the header preamble to enter the phase lock loop. The phase lock loop
performs a fast lock using the first four bytes of zeros to synchronize itself with the RL READ DATA
frequency. This fast lock is enabled by the assertion of FAST LOCK L from the enable flip-flop.

SEL DSK CLK H——
D

READ DATA

— FAST LOCK L

DS CLK H

ENABLE

WINDOW

FF1

FF2

— ¢

*3‘|’ H

1 5

DATA

giTA

FF3

0 O

1 »—o—DSDATAH

FF4
1] o)

— C

RLO2 H & UENB

) o/

CRDY L

LOOP LOCK H

8.2MHZ VCOH
WINDOW
GATE
TK-8673

Figure 3-40

Data Separator Detailed Diagram

8.2MHZ VCOH

SEL DSK CLKH

FAST LOCK L

wnoower

(WINDOW FF)

| LT LT LT LILILIL
l

DATA WINDOW

RL READ DATA

oecaveoeonss

DATA FF

[

H (NRZ)
DS DATA

A DATA WINDOW
TK-8665

Figure 3-41

Data Separator Timing Diagram

3-97

After synchronization (fast lock), SEL DSK CLK H is asserted to enable the data separator. The enable flip-flop will set on the detection of the first data pulse and remains set until the data separator is
disabled by the negation of SEL DSK CLK H.

The window flip-flop is now allowed to toggle under control of the 8.2 megahertz VCO H input producing two outputs (normal and inverted) at 4.1 megahertz each. The normal output (DS CLK H) is synchronized with DS DATA H and is asserted on the CURRENT CLOCK output of the clock control.
When the window flip-flop is set, the inverted (low) output indicates a window time during which data
pulses are interpreted as cell center pulses (data ones). When reset, it indicates a window time during
which data pulses are interpreted as cell boundary pulses (data zeros).
The data flip-flop sets only when a data one occurs during the assertion of the window (window flip-flop
set).

The window gate generates a pulse that simultaneously clocks the DS data flip-flop and clears the data
flip-flop.

The DS data flip-flop is set by data ones (data flip-flop set) but is synchronized to the window gate.
3.5.16 MFM Encoding and Write Precompensation
The MFM encoding and write precompensation logic (Figure 3-42) performs two major functions:

Converting serial digital data (DSRO H) to a modified frequency modulation (MFM) format
(MFM DATA L)

Preshifting the MFM data pulses to precompensate for magnetic peak shift phenomena
(WRITE DATA L/H)

Figure 3-43 illustrates the timing relationship for the MFM encoding and write precompensation logic.
3.5.16.1 MFM Encoding — The RLO2 uses a modified frequency modulation (MFM) encoding technique to magnetically record digital data on the disk surfaces. With this technique, each logical one
produces a flux reversal in the center of its bit cell. Two successive logical zeros produce a flux reversal
at the boundary of each bit cell containing a logical zero following a logical zero. This technique has the
advantage of putting at least one flux reversal on the disk for every two bit cells, making it feasible to
use phase lock loop techniques to form a self-clocking data recovery system.
During the write (UDISK WRITE H) or maintenance (UMAINT H) functions, the NRZ enable logic
allows the DSRO H input from the data shift register to appear as NRZ WRT DATA H.
The write data shift register converts the serial write data (NRZ WRT DATA H) input to parallel write
data (WRT DATA (3:0) H) using the 4.1 megahertz L clock. This allows the write data to be viewed as
follows:
WRT DATA3 H (next bit to be written)
WRT DATA2 H (bit to be written)
WRT DATAI H (least significant preceding bit)
WRT DATAO H (most significant preceding bit)

The ALLOW 1 logic, using both 4.1 megahertz clocks, monitors the present write data one (WRT DATA?2
H) and the previous write data one (ALLOW1 H). If either signal is a one, ALLOWI1 H is asserted or
remains asserted to the encoder, creating a window for the generation of an MFM-encoded logical one. The
LOAD REG L output is used to clockin write data (WRT DATA (3:0) H) for use within the ALLOW 1
and the write early/write late bit comparison logic.
3-98

I- MFM

TWRITE PRE COMP

ENCODING

1 Mz

82MHZCLK H|

LOAD REG L

DIVIDE

ALLOW

BY
2

4.1 MHZ L

!
LOGIC
ALLOW 1 H

5 NSEC
.

DAW

TIME

20 NSEC

DELAY

figec

WRITE

ENCODER

(NOMIN

AL)

DISK
WRITE H

——

UMAINT H| NRZ

—

DSROH

EnaBLE

LOGIC

NRZ

WRT

WRITE
DATA

SHIFT

66-t

REG

DATA
H

WRT DATAOH
WRT DATA 1 H

I
'|

WRT DATA 2 H

WRT DATA 3 H

—_——— _l
WRITE

COMPARISON
LATE BIT

LOGIC

WRITE
LATE

StL

WRITE DATA L

‘ l> WRITE

DATA
H

WRITE

EARLY

WRITE

EARLY BIT

COMPARISON
l

soL

LOGIC

S S
TR 862

Figure 3-42

MFM Encoding and Write Precompensation
Logic Functional Block Diagram

8.2MHZ H

H”I””“H””””||||”|||||H||

41MHZ L

||||

|||

4.1MHZH

III

|||

Ill

DATA3H

patarn 4

O I

TK-8664

Figure 3-43

MFM Encoding and Write Precompensation
Timing Diagram

The encoder monitors the following write data (WRT DATA (2:1) H) conditions:
e

Logical one (ALLOW1 H)

Two successive logical zeros (the complement of WRT DATA (2:1) H)

The encoder, in synchronization with the clock inputs (8.2 megahertz H, 4.1 megahertz L, 4.1 mcgahertz
H), will assert MFM DATA L in the center of its bit cell for each write data logical onc (ALLOW H). For
two successive write data logical zeros (the complement of WRT DATA (2:1) H), the encoder will assert
MFM DATA L at the boundary of each bit cell containing a logical zero following a logical zcro.

3.5.16.2 Write Precompensation — One of the problems associated with double density magnetic recording is a phenomenon called peak shift, in which flux reversals written on the disk tend to repel one
another. Because of this, the flux reversals appear displaced from where they were written. This can

“cause pattern sensitive data recovery problems.

The write precompensation logic offsets the harmful effects of peak shift. This logic displaces the
MFM-encoded data pulses (MFM DATA L) by 15 nanoseconds in one direction or the other (early or
late) before they are written on the disk. This allows the peak shift phenomenon to displace the flux
reversal to the desired position.

To determine if an MFM-encoded data pulse is to be displaced from its nominal position (20 nanoseconds), the following rule is used. A pulse is preshifted only if:
e
e

It is bounded on one side by a pulse that is not more than one bit cell away, and
It is bounded on the other side by a pulse that is more than one bit cell away
3-100

The direction (carly or late) of the preshift depends on the write data bit combinations that precede (WRT
DATA (1:0) H) and/or follow (WRT DATA3 H) the bit to be preshifted (WRT DATA2 H).

The write precompensation logic is concerned with only four write data bit combinations, as shown in
Figurc 3-44. All other bit combinations preclude the need for preshifting by 15 nanoseconds and, therefore,
the nominal position (20 nanoseconds) is used. The write late and write early bit comparison logic monitors

the four write data bits (WRT DATA (3:0) H) looking for one of the four bit combinations that require
preshifting. After monitoring the bit combinations, the logic causes one of the following to occur:

e
e

Leave the pulse to be written in its nominal position (S1 L, SO L deasserted, and the 20-

nanosecond tape asserted)

Write the pulse 15 nanoseconds early (20 nanoseconds minus 15 nanoseconds) (S1 L deas-

serted, SO L, and the five-nanosecond tape asserted)
e

Write the pulse 15 nanoseconds late (20 nanoseconds plus 15 nanoseconds) (SO L deasserted,

S1 L, and 35-nanosecond tape asserted)

Thus, for the write data bit combination 1000 as shown in Figure 3-44, the MFM-encoded data pulse
must be preshifted 15 nanoseconds to the right (late) to compensate for a peak shift to the left. For the
bit combination 0001, the MFM-encoded data pulse must be preshifted 15 nanoseconds to the left

(early) to compensate for a peak shift to the right.

The MFM-encoded and write-precompensated data (WRITE DATA L/H) are made available to the

RLO2 disk drive.

PRECEDING BITS

DISPLACEMENT BY

| WRT

PRECOMPENSATION

WRT

DATAOH

| DATA1H

WRT

BIT TO

|BEWRITTEN|

BIT

DATA? H

DATAS
H

PS @

PRE

PRE «—}—Ps

DELAY

WRT

0
A

(WRITE LATE)
0

ADVANCE

{WRITE EARLY)

ADVANCE [ 7 7

PRE

(WRITE EARLY)

DELAY | = 777”7

(WRITE LATE)

PRE

I———- D

TIME —»
NOTES:

(1) PS - DIRECTION OF PEAK SHIFT
PRE - DIRECTION OF PRESHIFT TO COMPENSATE FOR PEAK SHIFT

{2) SHADED AREA = DON’T CARE
TK-8662

Figure 3-44

Write Precompensation Early/Late Bit Combinations

3-101

CHAPTER 4
MAINTAINABILITY FEATURES

4.1

MAINTAINABILITY FEATURES
The circuitry of the IDC contains several features that enhance maintenance. These are:

Maintenance mode
Data loopback
"Write inhibit
Timeout inhibit

Defeatable enables

4.1.1

Maintenance Mode

When bit 25 of the CSR is set, the IDC is placed in maintenance mode, where it is used to redefine

instructions and to allow initiation of diagnostic software.

4.1.2

Data Loopback
When testing the IDC with microdiagnostics, the IDC provides a simulated RL READ DATA input

(See Figure 3-1). When a maintenance function is specified by the CPU, the microcontroller selects the

RL WRITE DATA output of the MFM encoder as the RL READ DATA input to the IDC read data
separator. This allows the capability of performing testing of the IDC using known data configurations.

4.1.3

Write Inhibit and Timeout Inhibit
During microdiagnostic testing of the IDC, the timeout logic is inhibited and writing to the disk drives

is inhibited. The timeout inhibits prevent the IDC from terminating diagnostic operations requiring
more than 150 milliseconds to perform. The write inhibit enables the IDC to be tested without corrupt-

ing the data stored in the associated disk drives.
4.1.4

Defeatable Enables

The enable input to each of the PALs (the GND input that enables the output of the PALs to be as-

serted) is applied through a resistor. Thus, the enable may be manually defeated by asserting a +3 Vdc
level at the enable input of the PAL.

4-1

CHAPTER 5
PROGRAM INTERFACE

5.1
BASIC SYSTEM OPERATION
Five basic decisions are made by the CPU when a data transfer occurs:
D=

The drive to be used (drive number)

Where on the disk the desired data are located (cylinder, sector, track)
The direction of data transfer (read or write)

Where in memory the data to be read from or written to are found (starting memory address)
The amount of data to be transferred (number of words)

The commands generated by the CPU to make these decisions are applied to the selected disk through

the IDC.
Up to four RLO2 disk drives or one R80 disk drive and up to three RLO02 disk drives can be connected
to the IDC. However, since all of the drives have the same bus address, the CPU must designate (to the

IDC) which drive to select. Once selected, only that particular drive can decode and respond to the
operational commands.

Once selected, the drive starts its mechanical positioning after receiving the cylinder, sector, and track
values plus a seek command containing a GO bit. The drive notifies the CPU, through the IDC, when
the desired position is located. If no error condition exists, the CPU initiates the data transfer sequence.
When the heads are at the correct location and the command is a read operation, serial data are read

from the disk, converted to parallel in the IDC, and then transmitted to the CPU. At the completion of
a read or write operation, the IDC interrupts the CPU (providing the interrupt enable is set) to indicate
that the data transfer is complete.
5.2 PROGRAMMING OVERVIEW
The communication of control commands, status data, error conditions, and maintenance information is
accomplished through registers contained in the IDC. The IDC contains eight registers required for
drive operation. Table 5-1 lists these registers, their mnemonics, their address, the type of register (read
only or read/write), and their basic functions.
5.2.1

1IDC Registers

5.2.1.1

Control Status Register (CSR) — The control status register (address F26200) is loaded under
CPU control with the IDC control word. The CSR also operates under CPU control to cause the transfer of the IDC status word (the current IDC control word contained in the CSR and a summary of the
current status of the IDC and disk drives) from the IDC to the CPU.

5-1

Table 5-1

IDC Registers

Address

Type

Function

Control Status
(CSR)

F26200

R/W

IDC control and status interface.

Bus Address

F26204

R/W

(BAR)

Contains the UNIBUS virtual
address of first byte to be

transferred.
Byte Count

F2608

R/W

F2620C

R/W

Contains 2’s complement of number

of bytes to be transferred.

(BCR)
Disk Address
(DAR)

‘

Contains disk cylinder, sector,
and track address (head number)
where transfer is to occur.

Multipurpose

F26210

R/W

RLO2 get status.

ECC Position

F26214

Contains the starting bit position
of a correctable ECC error
encountered during an R80 read.

ECC Pattern

F26218

Contains the bit (11) pattern to

(MPR)

be used to correct the error.
IDC Initialize

F2621C

R/W

When written with a negative one,
causes the entire IDC to be
initialized.

The CSR asserts the initial branch conditions (FO, F1, and F2) and the start signal (CRDY) to the
microcontroller. The CSR also controls selection of the applicable disk drive and enables the appropriate read data paths of the IDC. Status information from the disk drives and from the IDC header/data
comparator and ECC/CRC logic is asserted to the CSR, which makes this information available to the
CPU in the form of the IDC status word output.
When the function specified by the IDC control word is completed, is waiting for a data transfer to or
from the CPU, or has been halted due to an error, the CSR operates from microcontroller inputs to
generate and assert the applicable interrupt (UBUS BRS or PORT XFER REQ) to the CPU.

Table 5-2 provides a description of each bit of the CSR.

5-2

Table 5-2

Control Status Register Bit Assignments

Bit Position

Name

Description

Drive Ready
(DRDY)

Indicates the drive is ready to receive a command. It is cleared
during a seek or head select operation and is reasserted when
the operation is completed.

Function
(F2:F0)

These bits are set by software to indicate the function to be
performed when CRDY is cleared. Cleared by INIT.

03:01

Commands are as follows:

O—O—O—=0O—O

No drive operation
Write check data

O~ — OO = —0O0

Command

— OO OO OOoOoOO

FO0

Or—r———o
oo o

RS0
FMT F2 F1

Get status
Seek
Read header
Write data
Read data
Read data without header check
R80 write format function

Commands are described in detail in Paragraph 5.3.
05:04

Not used

When set, the CPU is interrupted at the normal or error
termination of any function.

Interrupt
Enable (IE)

Any asynchronous condition, such as a drive coming on line or
completing a seek or asserting error, causes an interrupt due
to
the setting of the attention flop associated with that drive. This

bit is set and cleared by the software writing the register. It is
cleared by INIT.

Controller
(IDC) Ready
(CRDY)

This bit is cleared by the software to indicate that the function
contained in bits (03:01) is to be performed. It is set by the
IDC at the completion of the requested function, at the

detection of an error, or by INIT.

09:08

Drive Select
(DS1:DS0)

Selects one of four drives (3 through 0) connected to the

controller. Cleared by INIT.

Table 5-2

Control Status Register Bit Assignments (Cont)

Bit Position

Name

Description

Operation
Incomplete
(OPI)

When set, indicates that the function did not complete within
the OPI timeout or that a function was stopped because of a
header CRC or skipped sector error.

Data Check
Error (DCK)

If OPI is cleared, the ECC error occurred on the data (DCK).
If OPI is set, the error occurred on the header (HCRC).

Data Late
(DLT)

Indicates on a write, if OPI is cleared, that the CPU did not
respond in time with accepting read data or passing write data.
When OPI is set, the same bit indicates header not found
(HNF). This indicates that the OPI timeout occurred while the
IDC was searching for the correct sector to read, write, or
write check.

Nonexistent
Memory (NXM)

Indicates that the IDC was unable to access the memory
address shown in the BAR. OPI and DLT are usually set when
this error occurs.

NOTES
In bits 13:10, the CRC check is performed on
both header words, even through the second
header word on the RL02 is always 0.

Bits 13:10, if caused by DRIVE ERROR, are
cleared by INIT or by initiating a function.
CRDY is set by INIT.

Drive Error
(DE)

Indicates that the selected drive has flagged an error. The
source of the error can be determined by performing a get
status function. This error can be cleared for the RLO2 by the
RST bit during a get status function. DE will not cause ERR
and CRDY until the normal occurrence of CRDY.

Composite

Indicates that at least one of the error bits 14:10 is set. When

Error (ERR)

ERR is set, an operation will terminate and interrupt if IE is
set.

5-4

Table 5-2

Bit Position

19:16

Control Status Register Bit Assignments (Cont)

Name

Description

Attention

(ATTN3:ATTNO)

An attention bit is provided for each drive to signal that a seek

has been completed or that the drive has changed status. A

status change is defined as asserting Drive Ready and
removing Drive Ready while not doing a seek. These changes

in drive status are scanned by the IDC whenever it is not
occupied with performing a function. These bits are cleared by
writing a one to the appropriate attention bit.

21:20

R80 ECC Status

(ECS1:ECS0)
,

These two status lines are encoded as follows:

00 — No Errors. This is the initial state of the status lines. The
00 state is maintained unless a read data error is encountered.
01 — Data Error. The 01 state is entered following the check
field of a read operation if the data is nonzero. This bit

indicates that the correction determination is in progress.

11 — Correctable Error. The 11 state is entered at the
completion of the correction computation if the computation is
successful.
10 — Hard Error. If the correction computation operation is not
successful, the 10 state is entered.

NOTE
The 01 state indicates that an error has occurred
(ECC or CRC mode) and that a correction computation is in progress (ECC mode). STAT 1 serves
as a “correction computation complete” signal.
22

R80 Skip
Sector Inhibit

This is a read /write bit used to inhibit skip sector errors. When

(SSEI)

until the bit is cleared. This bit can be cleared by writing it to a

written as a 1, skip sector errors are inhibited from occurring
zero or by INIT. It should not be used when in automatic skip
sector mode (bit 27 cleared).

R80 Skip
Sector Error
(SSE)

This bit can be read or written and can be set to either a O or 1.
It is set when bit 13 of the R80 header is read as a one,
indicating that the sector being read is a displaced sector
because it or a previous sector contained a bad spot. This error
can be cleared by writing a 0 in the bit position or by INIT.
This bit should not be used when in automatic skip sector mode
(bit 27 cleared).

5-5

Table 5-2

Control Status Register Bit Assignments (Cont)

Bit Position

Name

Description

Interrupt

Indicates that it is the IDC that has asserted BRS and is

Request (IR)

Maintenance

(MTN)

R80

Automatic Skip

Sector Inhibit
(ASSI)

requesting an interrupt. This bit can be cleared by writing a

one to bit 24.

Places the IDC in maintenence mode, where it is used to
redefine instructions and allow initiation of diagnostic

software. It can be read and writtentoa 1 or 0.

This bit is asserted when DS 1:0 has selected the R80 disk
drive.

When this bit is cleared, the IDC automatically handles skip

sector errors. During this state, CSR bits 22 and 23 are

undefined and should not be altered by software. Setting this

bit disables the automatic handling of skip sector errors. Bits
22 and 23 assume the meanings just described and are used to
control SSEs in software.

28
29

Time Out

When set, this bit disables the IDC on-board timeout clock.

Inhibit (TOI)

This bit is primarily used by microdiagnostics.

R80 Format

This bit, in combination with a function code of zero, selects

(R80 FMT)

the R80 format function to be performed after clearing
CRDY.

Not used

Mask Attention

(MASK ATTN)

When set, any writes to the CSR are masked, so as not to clear

the attention bits.

5.2.1.2 Bus Address Register (BAR) — The bus address register (address F26204) is loaded with the
.
UNIBUS virtual address of the first byte to be transferred. Bits (31:18) are ignored.
5.2.1.3

Byte Count Register (BCR) — The byte count register (address F26208 is loaded with the two’s

complement of the number of bytes to be transferred.

5.2.1.4

Disk Address Register (DAR) -The disk address register (address F2620C) is loaded under

CPU control with the required disk drive control word or read/write data address. The read/write data
address of the disk address register may be incremented by the microcontroller to update the
read/write data address information as additional contiguous sectors of data are written or read. The
contents of the disk address register may be transferred from the IDC to the CPU under CPU control.
The format of this 32-bit register is shown in Figure 5-1.

The DAR must be loaded immediately before seek or data transfer commands. Since the R80 and

RLO2 have different geometries, the drive to be commanded must be selected before loading this regis-

ter.

[

16 15

CYLINDER

08 07

TRACK

SECTOR

]
TK-9278

Figure 5-1

Disk Address Register

5.2.1.5 Multipurpose Register (MPR) - The multipurpose register (address F26210), when used with
the RL0O2 get status function, is loaded with a get status command. The RLO0O2 drive status word is
obtained by loading the MPR with a get status command and then loading the CSR with a get status
function. The IDC must be ready (CRDY) before loading the MPR. With the R80, get status is initiated by simply loading the CSR with the get status function.

Table 5-3 provides a description of each bit of the MPR.

Table 5-3

MPR Bit Assignments

Bit Position

Name

Description

Marker

Used by the drive to tell when a new serial command word

Get Status
(GS)

Must be a 2, indicating to the drive that the status word is
being requested. At the completion of a get status command,

15:4

(M)

has arrived. Must be a 1.

the drive status word can be read from the MPR. With this
bit set, bits 15:8 are ignored by the drive.

Not used

Reset

(RST)

Not used

If set, the RLO2 drive clears its error register before sending

the status.

5.2.1.6 ECC Position Register - The ECC position register (address F26214) is a 13-bit register that
indicates the starting bit position of a correctable ECC error encountered during an R80 read function.
5.2.1.7 ECC Pattern Register — The ECC pattern register (address F26218) is an 11-bit register indicating the bits to be used to correct the error. It is valid only during an R80 read that contains a
correctable ECC error.

5.2.1.8 IDC Initialization Register - When written with a negative one (-1), the IDC initialization register (address F2621C) will cause the entire IDC to be initialized.
5.3

COMMANDS

Program operations are initiated by the combination of the actions listed below:
e

Selecting a drive

Setting the GO bit (CRDY)

Loading the CSR with a function code

The function code identifies a specific command. On assertion of the GO bit (CRDY), the drive proceeds to execute the command. The commands can be divided into three categories:
1.
2.
3.

Positioning
Data transfer
Housekeeping

These commands and their corresponding function codes are described in the following paragraphs.
5.3.1

Positioning Commands

Positioning commands direct the logic that controls the amount of mechanical movement required to
position the heads over the recording media. These commands assert the ATTN bit after their normal

completion.

5.3.1.1 Seek Function (F2:F0 = 3) — A seek is initiated to a drive by selecting it via the CSR, loading
the DAR with the desired disk address, and issuing a seek command.
RLO02 Seek — When a seek command is encountered, the IDC will set CRDY as soon as the drive receives
the command and interrupt if IE is set. On receiving the cylinder address, the RLO2 drive will seek and/or
select a new head as indicated. Other combinations of DAR (0,1) will cause undefined results.
If a cylinder address is provided that attempts to move the head past the innermost (track 511) or outermost (track 0) limits, the head will come to rest on either track 0 or 510.
If software discovers that a seek was unsuccessful or that the RLO2 is not selecting the proper cylinder,
the execution of a read header command followed by a seek to the desired cylinder will resynchronize
the IDC to the proper cylinder.

R80 Seek - The DAR must be loaded prior to the start of the seek function. The clearing of CRDY will
then initiate the desired operation. As soon as the transfer is complete, CRDY will be set and the IDC will
interrupt if IE is set.

,
NOTE
When —1 is written to the DAR, the microcode will
issue a recalibrate command R80. This command
positions the heads over cylinder 0.

5-8

5.3.2
Data Transfer Commands
Data transfer commands involve the transfer of data to or from the disk. This also includes the transfer
of status information.

5.3.2.1

Read Header Function (F2:F0 = 4) - When a read header function is decoded with CRDY
cleared, the IDC will read and buffer in the first header encountered on the selected drive. The IDC
will set CRDY and interrupt if IE is set. Software can then read the two header words and the CRC
word from the MPR with three successive reads to determine the current cylinder, head, or sector loca-

tion of the drive.

5.3.2.2

Write Data Function (F2:F0 = 5) — When the write data function is decoded with CRDY
cleared, the IDC begins reading successive header words and compares them to th¢ DAR. When a
match is found, the header CRC is checked and, if correct, the sector is written with the words provid-

ed by the CPU. For partial sector writes, the remamining sector area is filled with Os. At the end of the

sector, the DAR is incremented and the next sector is written if there is count remaining. At the end of
the transfer, CRDY is set and an interrupt made if IE is set.
:

3.3.2.3

Read Data Function (F2:F0 = 6) — When this function is decoded with CRDY cleared, the
IDC begins reading successive header words and comparing them to the DAR. When a match is found,

the header CRC is checked and, if correct, that sector is read and the words requested are buffered for

transfer to memory by the CPU. Data ECC (or CRC for RL02) is then checked and the DAR incremented. If the desired number of words has not been transferred, the next sector is read. Otherwise,

CRDY is set and an interrupt made if IE is set.

5.3.2.4

Read Data Without Header Check Function (F2:F0 = 7) — When this function is decoded with
CRDY cleared, the data portion of the sector following the next sector pulse is read and the words
requested are buffered for transfer to memory by the CPU. The header is neither compared nor checked for CRC errors. Data ECC (or CRC for RL02) is checked at the end of a sector. If the desired
number of words has not been transferred, the next sector is read. Otherwise, CRDY is set and an
interrupt made if IE is set.
'
5.3.2.5

Write Check Function (F2:F0 = 1) - This function is used to perform a bit-by-bit comparison

between data in main memory and data on the disk. When the function is decoded with CRDY cleared,
the IDC starts reading headers and compares them to the DAR. When a match is found, the header
CRC is checked and, if correct, that sector is read and the data are compared in the controller with
data that has been fetched from main memory by the CPU. At the end of a sector, if a data comparison
error or a data CRC/ECC error has been sensed, the Data Check (DCK) error bit will be set in the
CSR.
5.3.2.6
~

Get Status Function (F2:F0 = 2)

RLO2 Get Status - If the Get Status bit (bit 1 in the MPR) is set, the RL02 drive will send its status word
via the status line to the IDC. When the drive status word is received, the IDC will set CRDY and interrupt
il IE is sct. The CPU can then read the RLO2 status word by reading the MPR. This function may be
performed any time the controller is ready, even though the drive is not (during a seek or when in the load

state).

The operation is undefined if the Get Status bit is a 0. If bit 3 in the MPR is set, the drive will attempt

to clear its error bits before sending the status word.

The contents of the RLO2 status word are listed in Table 5-4.

‘

Table 5-4

Bit Position

2:0

RL02 Get Status

Name

Description

State

These bits define the state of the drive:

(ST)(A, B, or C)

1
1
1

0
0
1

0
1
0

0
0
0

0
1
1

Load State

1
0
1

Spin-Up
BrushCycle
Load Heads

SpinDown

Seek Track Counting
SeekLinear Mode
UpLoad Heads

Brush Home

Asserted when the brushes are not over the disk.

Heads Out (HO)

Asserted when the heads are over the disk.

Cover Open (CD)

Head Select (HS)

Reserved

Drive Select

(BH)

Error (DSE)

Volume Check

(VO

Write Gate

Spindle Error

Seek Timeout

Error (WGE)

(SPD)

Asserted when the cover is open or the dust cover is not in

place.

Indicates the currently selected head.

Indicates multiple drive selection is detected.

Indicates the transition from a head load state to a head on

track state.

Indicates the drive sensed Write Gate asserted when the

sector pulse is asserted.

Indicates the spindle is not reaching speed in the required

time, or is overspeeding.

Indicates the heads did not come on track in the required

(SKTO)

time during a seek command.

‘Write Lock (WL)

Indicates write lock status of the selected drive.

Head Current
Error (HCE)

gate was not asserted.

Write Data
Error (WDE)

Indicates Write Gate was asserted, but no transitions were
|
detected on the write data line.

Indicates write current was detected in the heads when write

5-10

R80 Get Status — The R80 sends its status word to the IDC in parallel via the interface lines. When the
drive status word is ready, the IDC will set CRDY and interrupt if IE is set. The CPU can then read the

R80 status word by reading the MPR. This function may be performed any time the IDC is ready, even
though the drive is not (during a scek or when in the load state).

The contents of the R80 status word are listed in Table 5-5.

Table 5-5

R80 Get Status

Bit Position

Name

Description

4:0

Sector Count
(SEC4:0)

Sector count will change on leading edge of sector or index.
Timing integrity is maintained throughout seek operation.

7:5

Not used

Fault (FLT)

Plug Valid

(PLGV)

Seek Error

{SKE)

On Cylinder

(ONCY)

Signals fault condition. The following types of faults are
detected: dc power fault, head select fault, write fault, write
or read while off cylinder, and write gate during a read
operation. May be cleared by INIT or FAULT CLEAR on
the operator panel.
Bit indicates that a logic plug is installed in the operator

panel.

Indicates that R80 was unable to complete a seek within 500

milliseconds, that the carriage has moved to a position outside
the recording field, or that an illegal address has been
detected.

Indicates that the servo has positioned the heads over a track.

The status is cleared by any seek instruction causing carriage
movement or zero track seek.

Drive Ready

Indicates that the unit is up to speed, the heads are loaded,

(DRDY)

and a no fault condition exists within the drive.

Write Protect
(WTP)

Signals that the write protect switch has been enabled.
Attempting to write at this time causes a fault to be issued.

15:14

Not used

5.3.3 Housekeeping Commands
Housekeeping commands are used to place the drive logic into a known or initial state. ATTN is not
raised at the completion of the housekeeping command unless there is a persistent error condition.
5.3.3.1
NOP Function (F2:FO = 0)
This function is a NOP, except in the case of the R80 bit being set, and an R80 selected by the CSR. In
this case an R80 Format function is performed.
5.4 R80 ECC HANDLING
The IDC has the ability to detect errors that occurred while reading the data field and to provide information for software to recover the data. The ECC code that will be used, called burst error correcting
fire code, will locate an error that falls within an error burst of length 11 bits or less. Any errors outside
the specified burst length are guaranteed to be detected, but not to be correctable.
The IDC logic will do the following:
e

Find the 11-bit burst within which the read error is included.

Determine the exact location of the burst within the data field.

This information will be provided to the software via the following two IDC registers.
e

ECC pattern register: will contain the actual error burst

ECC position register: will contain the address of the first bit of the error burst within the
data field

5.5 HARDWARE ERROR RECOVERY
If an ECC error is detected, the IDC will simultaneously clock the ECC shift register and increment
the position counter. When the counter overflows, the correction computation enters a second phase
searching for a correctable error pattern. This is done by clocking the shift register bits (20:0) and
simultaneously keeping a count of the number of shifts in the position counter. When an all zero condition is found, shifting and counting stop and ECC STAT (1:0) is set to 11, which indicates a correctable
error pattern has been found. The error pattern and the error position can then be read via the specific
registers.
»
There is one condition under which a correctable error pattern cannot be computed: an all zero condition is not found within n shifts, where n equals the number of data bits plus check bits: 4096 + 32 =
4128. Under this condition, STAT (1:0) is set to 10, indicating a hard error.
5.6

SOFTWARE ERROR CORRECTION

Error correction is accomplished by the software as follows (not necessarily in this order):
e

Software reads the position register.

Software counts from the beginning of its data field the number of bits as specified by the
position register and extracts 11-bits, which represents the burst within which the error oc-

curred.
e

Software reads the pattern register.

Software performs a logical “exclusive OR” of the 11-bit error burst with the contents of the
pattern register. The result is the corrected 11-bit data burst, which is now put back into
storage.

5-12

5.7 R80 SKIP SECTOR OPERATION
5.7.1
R80 Bad Spot Problem
The advent of the 3350 type high capacity drives has caused an increase in the number of bad spots

appearing on the media. It is projected that the R80 could have up to 350 bad spots per head
disk
assembly (HDA). DEC STD 144, which is currently the only specification covering bad spots on disk

drives, falls short of handling this large a number of defects. The R80 thus uses a skip sectoring ap-

proach that presents bad block information to the driver level software.

5.7.2 The Concept of Skip Sectoring
On each track of the disk, one sector is reserved that will be used as a replacement sector in the event of

a bad spot on the track. This replacement is done by sliding each sector down by one, starting at the bad
spot, such that the last sector at the end of the track is now the reserved sector. If more than one error

occurs on a track, the second bad spot will be logged in the bad block file described in

DEC STD

144.

The IDC automatically handles skip sector errors and continues the data transfer if the Inhibit bit (bit
27) in the CSR is cleared. Following is a description of software handling if the Inhibit bit is set.

3.7.2.1
Software Handling of Skip Sector Errors — The responsibility of the IDC is to notify the software that it is trying to read a sector that has been displaced. The responsibility of the software is to

restart the transfer at the next sector (n + 1).

5.7.3

Skip Sectoring (with Automatic Inhibit Bit Set) - When the IDC driver receives a request for

data, a logical block number and extent is supplied to determine where the transfer will take place on

the disk. With skip sectoring, the transfer is initiated as usual by converting the block number to a

physical address, loading the word count and address, and initiating the transfer. If no errors occur or
an error other than an SSE occurs, the transfer is handled as in the past. If an SSE occurs, as indicated

by a I in bit 23 of the CSR (MSB of byte 2), it indicates that a sector has been encountered that is
physically displaced by one on the disk. This error could occur immediately at the beginning of a trans-

fer, if it started after a bad spot on a track, or in the middle of a transfer if the operation was started

before a bad spot and continued beyond it.

The software must first set SSE Inhibit (bit 22) of the CSR. This inhibits further generation of SSEs
and allows the operation to continue without further interrupts from SSEs for the rest of the track. The
software must then restart the operation. When the operation was aborted in the IDC, because 13 was
sct in the header, the disk address was incremented by 1. This is exactly where we want to start the
operation again when skip sectoring occurs, so no modification of the disk address is necessary. Also,
since the IDC aborted the operation as soon as the SSE bit in the header was detected, no data from the
sector that generated the error was transferred. This means that the word count and address for the restof the transfer are correct. So, to restart the transfer, all that is necessary is to set the GO bit (clear

CRDY).

5.8
R80 FORMATTING
Provisions have been made within the IDC to format the R80. The following procedure is required to

format the disk, one track at a time.
a.

Select cylinder and head.

Set up registers as in a write data function, supplying four bytes of header for each of the 32
sectors on a track (128 bytes).

Initiate the write format function.

The IDC will:

Search for the leading edge of the index pulse (sector 0).

Immediately bring up write gate and start writing zeros.

Write all zeros for head scatter and PLO sync areas (27 bytes).

Write a sync pattern, four header bytes, and check word.

Write all zeros for write splice gap and PLO sync field (12 bytes).

Write a sync pattern, the data field, the four-byte data ECC word, and a two-byte pad at the

Wait for the leading edge of the next sector pulse and repeat steps a through f.

Continue until the index pulse is detected once again.

Set CRDY, interrupt, and return to idle.

end of the check word.

59 EXAMPLES OF SYSTEM OPERATION
-

Seek Operation

5.9.1

The following is an example of the sequence involved in a seek function.
a.

Select drive and function.

Load DAR with desired cylinder, track, and sector.

Issue seek function to drive and wait for interrupt. Seek will cause two interrupts, one when
the seek has been issued to the drive (CRDY sets) and one when the seek completes. The
drive doing the seek asserts DRDY when the seek is complete. The controller, when it is not
busy performing functions, checks all drives that have been issued seeks to see if they have
asserted DRDY. Respective attention flops are set by the microsequencer for those drives
that have done so.

Check error flag to complete the seek operation.
NOTE

Since the controller becomes ready and interrupts as
soon as a seek is issued, it is possible to issue seeks
to additional drives while the first is seeking. An attention interrupt is provided for each drive as each
drive completes its seek. The software must know
which drives are doing seeks so that it will know why
the Attention bit has been asserted.

5-14

5.9.2

Data Transfer Operation (Read/ Write)
When the seek is completed, the CPU can issue

a data transfer command. One drive can be doing

a
is issued to another drive. Once a data transfer
has
started, no further commands can be issued to a
controller until the transfer is completed either normally or by error.
seek at the same time a data transfer command

The read data operation is as follows:
a.

Select drive and function. Load byte count, bus

CSR.

address, DAR, and issue read function via

DAR is compared to disk headers until a match is

found.

The CPU will transfer data into memory using the

BAR as a UNIBUS virtual address.

The controller will interrupt when the transfer is
CSR.

completed. Software will check error flag in

Select drive and function. Load BCR, BAR, and DAR
DAR is compared to disk headers until a match is

and issue write function via the CSR.

found.

The CPU will tansfer data from memory to the drive.
The controller will interrupt when the transfer is complet

ed. Software will check error flag in

CSR.

5-15

APPENDIX
PROGRAMMED ARRAY LOGIC DEVICES (PALS)

A.1

INTRODUCTION TO PALS
Programmed array logic devices (PALs) are logic arrays that may be programmed to give a custom-

designed chip unique to a specific requirement.

The basic logic configuration used in PALs is shown in Figure A-1. The circuitry consists of a programmable AND array connected to a fixed OR array. Note that the AND array shown in the basic logic

configuration has only four programmable (fusable link) inputs and two fixed OR outputs. In the PAL
circuits used in the VAX-11/730, up to 32 programmable AND inputs and up to eight fixed OR inputs
are used per output.

INPUT 1—{§—
F1

Fé

:D—OUTPUT

INPUT 2—-{:8
TK-6630

Figure A-1

Basic PAL Logic Configuration

An unprogrammed PAL has all fuses intact, as indicated in Figure A-1. A PAL is programmed by
“blowing” the links for the unused AND inputs to give the desired AND before OR logic configuration.
For example, the top half of Figure A-2 shows the links “blown” to implement the XOR function AB V

AB in the basic PAL logic configuration. This same logic function may also be represented as shown in

the bottom half of Figure A-2 where an X represents the links that are left intact to perform the logical
AND. This last method of showing an AND array configuration is the convention used in the PAL plot
listings provided in the VAX-11/730 microfiche set.
,

A-1

Y
o\ o—

—

ABV AB

TK-6627

Figure A-2

A.2

XOR Logic Function Using PAL Logic

PAL DEVICE TYPES

The four types of PALs used in the VAX-11/730 are listed in Table A-1. Logic diagrams for each PAL
are given at the end of this appendix.

It can be seen from the logic diagrams that the four PAL devices all use the basic AND before OR
logic configuration discussed in Paragraph A.1. However, outputs from the 16L8 are inverted and six of
the eight outputs feed back to the AND arrays for added functionality. In addition, the output inverters
for these six outputs may be turned on and off by the AND arrays (programmable I/0). This provides
added logic capability. It also allows the corresponding output pin to be used (when the inverter is
turned off) as an input to the AND array just like a designated input pin.
Also note from the logic diagrams that the 16R8.has register outputs (D-type flip-flops) and no gate

outputs. Again, outputs are fed back to the AND array but not directly by way of the output pins.
Instead, the O outputs of the flip-flop drive the array. As a result, the output pins cannot be used as
input pins as for a 16L8. The other two PAL types, the 16R6 and 16R4, have varying combinations of
both gate and register outputs on the same chip.

A-2

Table A-1

PAL Device Types Used in the VAX-11/730

PAL

Type

Device

Inputs

Outputs

| (0]

Program

16L8

Outputs

Description
AND-OR gate
array

16L8

AND-OR array
with registers

16R6

16R4

AND-OR array

with registers

AND-OR array
with registers

A.3 PAL SYMBOLOGY
A typical PAL as represented in the VAX-11/730 Engineering Print Set is shown in Figure A-3. Information within the symbol includes the device type, part number, and location. For example, the PAL in
Figure A-3 is a 16R4 located at E50 with a part number equal to 010K3. The PAL part number distinguishes one programmed PAL from another.

Inputs to the designated PAL input pins are shown at the left of the PAL symbol. Outputs appear at the
right. When an output pin is used as an input pin as discussed in Paragraph A.2, the input signal is

entered at the left of the symbol and a dotted line (drawn across the PAL symbol) is used to show the

connection to the output pin on the right. Pins having both input and output capability are labeled as
I/0O on the PAL symbol. Gate outputs not having both input/output capability are labeled with an O.
Register outputs are identified by an R. Finally, designated input pins are specified by a D.

PAL 16R4

010K3
)

E50

BUS 1B D06 H—2{D0

.
R DL DAPH 0S
6 H

R DHEDAPH 05 4 H
2H
R 2 DAPH 08

BUS I8 D04 H—D1
BUS 18 D02 H—{D2

BUS 18 D00 H—{p3

R DHL0APH 0S 0 H

BUS Y D06 H—-{D4

BUS Y D04 H—{ D5
8US ¥ D02 H-2{p6

BUS Y D00 H—-D7
DAPH LOAD Y TO 08 Lo — — ——— 10 p}2

1/0 DS
. DAPH RMODE B L
DAPBOSCTL1H—— — — — 10 Db
DAPB 0S CTLO H—— — — — 10 DHE

DAPB CLOCK REGS H—cLock

olenasLE
TK-6629

Figure A-3

Typical PAL Symbology

A-3

READING THE PAL PLOT LISTING

A-4. The part number and PAL device type (ais
An example of a PAL plot listing is shown in Figure
or output associated with each PAL pin
16R6 in this case) are at the top of the listing. The input
es the +5 volt power source.) A low assertion
given next. (NC indicates no connection; VCC indicat
level for input/output signals on the listing is indicated by a slash ( /) immediately preceding the signal

A.4

output signal names on the listing are somename. If there is no slash, the signal is asserted high. Input/the
Engineering Print Set.
in
times abbreviated and may not be exactly the same as
An X represents the fusable
The rest of the listing consists of the AND array plots for each outputofpin.
line in a plot is the list of
each
links left intact; a dash (—) represents a “blown” link. To the right
individual AND terms
these
Because
signals selected by the intact links that make up the AND inputs.
) result in an easily
together
(ORed
are ORed by the PAL logic, the list of AND terms in the listing
, output pin 12,
example
For
d.
read Boolean expression that represents the logic function performe
has the following
listing,
the
in
plot
last
the
which is a gate output (refer to the 16R6 logic diagram) and
input:

vVCC

START__8085__CYC*IO*A14* /RAS
/RAS*STATE

r) in the signal name.
The underlines in the expression above only represent a space (a blank n.characte
ing the enable level
Discount
operatio
AND
An asterisk (*) between signal names specifies the logical
for output pin 12
n
expressio
input
this
asserted,
for the output inverter, which in this case is always
(/UART—CHIP_SEL) may be read as follows:

UART CHIP SEL L = START 8085 CYC
RASH V STATE H

HIO H A14 H RAS H

the output signal just as for
For a register output, the Boolean expression read from the listing specifiesflip-flop
is clocked. Flip-flops
register
the
until
negated
or
a gate output. The output pin is not asserted
are clocked by the positive-going transition of the clock.
A.5

PAL LOGIC DIAGRAMS

The logic diagrams for the 16L8, 16R4, 16R6, and 16R8 PAL devices are shown in Figures A-5
through A-8.

PART

NUMBER:

DEVICE

TYPE:

NUMBER

23-004K4-0-Q

PAL16R6

SYMBOL

TABLE:

CLOCK

ALE

REQUEST

Al4

6=
7=

REFR

OUTPIN

FUSE

INTACT

REFRESH

DONE

19=/LONG_CYCLE
20=

FUSE

vCC

BLOWN)
vee

————

XXXX

XXXX
XXXX

STA
8085
RT_
CYC*Al4

XXXX

---X

————

XXX
X

XXXX

X---

ALE

XXXX

----

_X__

XXXX

----

STATE

18=/STAR
8085 T_
CYC

-—=X

-—-X

OUTPIN

17=

XXXX

OUTPIN

OUT

---XXXX

OUTPIN

GROUND

11=

13=/9300
600_
BAUD
14= REFRESH CYC

PLOT:

OUTPIN

19=

15=

16=/RAS

12=/UART
CHIP SEL

9600 BAUD
300 _BAUD

FUSE

SEL_9600 BAUD
RESET

REFRESH_CYC*STA
8085 CYC*Al4
RT

/REQUEST REFR
/REFRESH_DONE*/REFRESH_CYC

—_———

————
-X

————

.._...x

-_X_

——

-X-=

X-X-

RAS*STATE

==—==

——e-o

START_8@85

/RAS*REFRESH

CYC

CYC*/RAS*/I0*Al4

RESET

XXXX

—-—--

—X-

/START_888
CYC
5

Figure A-4

PAL Plot Listing (Sheet 1 of 2)

A-5

RAS

/Al4

OUTPIN

START 8085

CYC

RAS*REFRESH

RAS*STATE

CYC

/REFR
_CYC* ESH
/REQUEST

REFR

/REFRESH CYC*REFRESH DONE

/REFRESH CYC*/RAS*ALE*/STATE
RESET

OUTPIN

SEL 9600 BAUD*9600_
BAUD

BAUD
/SEL_ 9608 BAUD*304
XXXX

XXXX

X XXX

XXXX

XXXX XXXX
XXXX XXXX

XXXX

OUTPIN

vee

12
-—-X

START 8885 CYC*IO*Al4*/RAS
/RAS*STATE

—_X-

XXXX

XXX
X

XXXX

X
XXX

XXXX

Figure A-4

PAL Plot Listing (Sheet 2 of 2)

.2___{}———4

—

o
3_{:?

—

|
17

:
5

%‘L-—@

_
15

.6__{;3‘

<—

14
Z—{Z

—

[

{4‘

TK-6624

Figure A-5

Logic Diagram: PAL16L8

>—

51—

I
0

—{26

‘D—:l‘

3l
13

s
12

> I3

L
TK-6623

Figure A-6

Logic Diagram: PAL16R4

A-8

,2_{}——«

B 18

‘3

f
0

§_{2

a 15

]

‘EWM
0

5t
|

|
12

TK-6621

Figure A-7

Logic Diagram: PAL16R6

A-9

TK-6622

Figure A-8

Logic Diagram: PAL16RS8

A-10

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