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Document:	MXV11-B Multi-Function Option Module User Guide
Order Number:	EK-MXV1B-UG
Revision:	001
Pages:	81
Original Filename:

OCR Text

g
g it

CONTENTS
CHAPTER1

GENERAL DESCRIPTION
i

1.1

General ....i . i

1.2

Read/Write
MemOry . ...ovote i
ee

1.3

MOS RAM Battery Backup ........ e

1.4

Read Only Memory ....... ..o

1.4.1

Direct Addressing Mode ........oooeriieinaaann..

1.4.2

ROM WiIindow Map .. ocoiiii e

1.5

Serial Line Units ......... e

e et

1.6

Line Time CloCK ...t e

e e

1.7

LED Diagnostic Display Register .................... e

1.8 ,

MXV11-B2 Bootstrap/Diagnostic ROM Option.............

1.9

SpPeCIfiCatioNS ...t

1.8.1

Physical Specifications ...,

- 1.9.2

Environmental Specifictions .............
... o

1.8.3

Random Access Memory Specifictions

.................

1.9.4

Electrical Specifictions ...,

CHAPTER 2

FUNCTIONAL DESCRIPTION

2.1

General ... ...

2.2

PROM Addressing .................... feesrtimveannennns...

2.2.1

Direct Addressing .........ccoiiiiiiiiiiiiiiiiiiineee..

2.2.2

I/O Page Addressing .....cooviiiiiiiin

2.3

2.3.1

i, 10

RAM Memory Functional Description...................... 12

Read/Write ACCESS .....vvnveei e, e 12

2.3.2

Refresh ACCeSS ...t
e
et
eiee e 14

2.3.3

Arbitration Logic ........... ... i 14

2.4

Crystal Oscillator ... e 15

2.5

Line TimMe CloCK .o
e e
e e 16

2.6

Diagnostic Display Register ...........ccoiiiiiiiiiinn... 16

2.7

Serial Line Units ...
e 17

2.7.1

Address Selection ... 17

27.2

Interrupt Vector Selection .........coovviiiiinininn... 18

2.7.3

SLU Register Addressing ............ccoiiiiiiiiiiinnn.. 18

2.7.4
2.8

Baud Rate Selection .................... e 24

Cables ... e e .. 25

2.8.1

Interface ConnectorPins ..., 29

2.8.2

Current LOOD .o i i

e e 30
iii

CONTENTS

JUMPER CONFIGURATIONS

ww
N =

HAPTER3

APPSR 31
A
N Y=Y a =] - L
o 53
.
.
Jumper Configurations .......
ROM Configurations . .......cooiiiiiiiiiiiiiieiienn..... 54
User Mode (Direct Addressing) ...t 55
Boot Mode (Page Addressing) ...........ccoveeveiieinnn, 55
Boot Mode (Direct Addressing) ..............coovinnnnt. 57
e, 57
SLU Configurations ........cooeiiiiniiieiiiiiiiiiie
Line Time Clock Control ........ccoiiiiiiiie 58
s 58
nne
sanenne
icei
et
LTC Fre@QUENCY ..o e iteeiiii

MAINTENANCE AND DIAGNOSTICS

*HAPTER4
1

1.3

.4
1.5

1.6

1.7

1.8

4.9

4*10
1.11

1.11.1

1712

et e e 59
et
GENEIAl ittt
e 59
Data TeStNG . .ovvriiiiii et ei
n 59
iiiinans
riii
i
ovve
....
Testing
Serial Line Unit
60
e
....
.........
Program Options and Defaults
63
nns
nasncana
EXeCULiON TIMeS .ttt e ittt it i reiesesnaeaanraa
it ee ettt . 63
PoOWEr Fail oo oo
it 63
i
...oviin
.
Error HanAling
... [ PP 64
........
Device Registers ........
Summary of Tests and Special Subroutines ............... 64

System Requirements .........coovviiiienniinnn. s 69
~ Operating Instructions AP 70
Loading and Starting Procedures .................ooues 70
Operational Switch Settings ....................i 71

APPENDIX A

PROGRAMMING SUMMARY

FIGURES

MXV11-B Simplified Block Diagram ...............oovnnne 2
ROM Window Map Addresses ..........cciiiiienenieennnes 3
Page Control Register ..........ooviiiiiiiiiirniiienneenns 4
Direct and Page Addressing Block Diagram ............... 10
_Page Mode Addressing .......coovvnruirirciaeianes 11
RAM Memory Functional Block Diagram .................. 13
XTAL Oscillator Block Diagram .........ccoviiiiineneneinns 15
Line Time Clock Diagram .....ccoiiieinieiiiineennns 16
MXV11-B Diagnostic Register ...........ooiiiineiennees 17

SLU Vector Address Bit Format ...t 18
s 23
SLU Register AAdressing .......oooveriieninieireaeen
MXV11-B EIA Cable Configurations ........... e 26

MXV11-B 20 mA Cable Configurations .................... 27
BC21 B-05 Modem Cable ......e 28
BC20 N-05 Null Modem Cable .............cccviviiennn 28
MXV11-B Connector PinS . o vviiiiiiiiieniannneniens 30

3-1

3-2

3-3
3-4
3-5

CONTENTS

Default Configuration of Push-On Connectors .............
MXV11-BJdumperlocations .........coooeeueu
i
nnnn
...
Jumper Configuration Flow Diagram

......................
F-"ROM Chups .........................................e

TABLES
1-1

2-1

2-2
2-3

2-4

2-5
2-6
2-7

3-1

3-2
3-3

3-4

3-5
3-6

3-7
3-8
3-9

3-10

ROM Window Addresses for 16-, 18-, and 22-bit Q-bus.. ...
ROMWindow Map ...

Receiver Status Register Bit Assignments (RCSR)

........
Receiver Data Buffer Bit Assignments (RBUF) .............

Transmitter Status Register Bit Assignments (XCSR) ......
Transmitter Data Buffer Bit Assignments (XBUF) ..........
Definitionof Cables ...........ooov v ..

Jumper Connections for MXV11-B .............. s
Miscellaneous Jumper Configurations .....................
Jumpers for PROM Starting Address ......................
Serial LineUnitBaud Rates ............o.covvuenenn

Serial Line Unit Starting Address Jumpers ................
Jumpers for SLU Vector Addresses .......................
RAM Starting Address Jumpers ................. e

PROM JUMPEIS ...t
e
Jumpers to Configure PROM Size .................
... ...

Jumper Connections for PROM Sizes in User Mode.. ... ..

3-11

Jumper Connections for PROM Sizes in Boot Mode
(Page Addressing) ...,S

3-12

Jumper Connections for PROM Sizes in Boot Mode
(Direct Addressing) .........coooiiiiiiii
i, ;

GENERAL DESCRIPTION

1.1

GENERAL

The M71985 module, designated MXV11-B, is a dual-height, multi-function
option module compatible with LSI-11, LSI-11/2 and LSI-11/23 processors.

The module can operate on the 22-bit Q-bus (up to 316K words), the 18-bit

Q-bus, and the 16-bit Q-bus. MXV11-B features include:

Read only memory (ROM)

ROM window map logic (page control register)

Two asynchronous serial line ports (SLUQ, SLU1)

5 V battery backup for MOS RAMs

Multiple line time clock frequencies

®*

Read/write memory capability (MOS RAM)

LED diagnostic display register.

NOTE:

The page control register, line time clock register, and diagnostic dis-

play register are user options and can only be selected if the MXV11-B is

strapped for console port and bootstrap mode. Also, the Halt or Boot functions
may be optionally selected in this configuration.
The following paragraphs describe these features. Figure 1-1 is a simplified

block diagram of the module.
1.2

READ/WRITE MEMORY

The MXV11-B read/write memory consists of 128K bytes of dynamic MOS RAM
without parity. The MOS RAMs operate off the system's +5 V supply or from

the +5 V battery backup via a jumper consisting of a 0 ohm resistor. On-board
memory refresh is included and is transparent to the user.

The read/write memory is configured from 64K SIPs (single in-ine package).

Four SIPs provide 64K 16-bit words or 128K bytes. RAM starting addresses are
from 0 to 252K words on 4K word boundaries. This memory does not respond

to addresses in the 1/O page.
1.3

MOS RAM BATTERY BACKUP

The MXV11-B provides battery backup for the MOS RAMs. The battery backup
must be jumpered to be functional, and battery backup power must be supplied

by the system. A green light emitting diode connects across the MOS RAM
power supply and ground to show that power is on to the RAMs.

GENERAL DESCRIPTION

)

Q-BUS

r MXV11-B

l
128K BYTES

. l MOS RAMS

SERIAL LINE

UNITS

NITS

0,1

R
|

apDRESS

|
'

gig}?&%fl‘c

LINE TIME

S eR

CLOCK

8K BY 8

Rorx@,

AREGISTEoLR

" MAP LOGIC

‘

PAGE

ROM BOOT

l
DC LEVEL
CONVERTER
(9636, 9637
CHIP SET)

Figure 1-1

‘

MODULE

CONTROL
LOGIC

INTERFACE

)

TRANSCEIVER

a8 583

MXV11-B Simplified Block Diagram

1.4 READ ONLY MEMORY

Two 28-pin sockets on the +5 V read only memories (ROMs) contain bootstonrap
of

“code, diagnostic code, or user routines. Wire-wrap posts allow the inserti
2K by 8, 4K by 8, or 8K by 8 PROMs/ROMs in these sockets.

le
The PROM/ROM devices used may be ultra-violet Eraseable Programmab
Or
ies,
Memor
Only
Read
le
Read Only Memories, fusible link Programmab
masked Read Only Memories.

-B2 ROM set. If user
The 28-pin sockets can house user PROMSs or the MXV11
0 through 077776
(0000
area
user
the
in
d
PROMs are installed and arebelocate
PROMs are locatuser
the
If
" octal), the PROMs may only directly addressed.
be directly or
may
" ed in the boot area, 773000g, 765000g (18-bit address) they
indirectly addressed by a window mapping technique. (Refer to Paragraphs
1.4.1 and 1.4.2)

only reside in the
If the MXV11-B2 ROM set is installed in the sockets, it can ng
boot area and may only be addressed by the window mappi technique.

GENERAL DESCRIPTION

Any size PROM (2K by 8, 4K by 8, or 8K by 8) can be addressed directly or

indirectly via window mapping. One exception to this is the 2K by 8 UV (ultra
violet) PROM which may be addressed only through direct addressing.

NOTE:

To prevent wraparound, the PROM 1 and PROM 2 jumpers must be

set to the correct PROM size.
1.4.1

Direct Addressing Mode

In direct addressing, ROM will reside in main memory, with starting addresses

on any 4K word boundaries under 16K words (000000-777776 if 18-bit
addressing is usec). If that word bank is selected, only the space containing

ROM is enabled, preventing '‘wraparound.” Any read request made to ROM,
where no ROM exists, results in no response from the module.

- NOTE:

All addresses specified in this manual are 18-bit.

Direct addressing can be used to access ROM in the I/O page when the ROM is

used for bootstrapping. The bootstrap area consists of a 256 word block in the

address range from 773000 to 773776. If an access is made to the ROM outside
the bootstrap area, there is no response unless it is the address of an actual
device in the system.
1.4.2

ROM Window Map

The ROM in the MXV11-B uses two windows in the I/O page. Each window
points to 32 256-word blocks in ROM. This method of pointing prevents the

whole 1/O page from containing ROM code. Through this technique, any 256
word block of ROM can be transferred to the appropriate window area in the

I/O page (Figure 1-2).

BYTE

777777-END OF /0 PAGE

///////

773717

/ ~

765777

////// 4 123000
|

Ml S
//////

765000

76000-START OF 1/0 PAGE
Ma-0209.82

Figure 1-2

ROM Window Map Addresses (18 Bit Q-bus)

,,,,,

GENERAL DESCRIPTION

the addresses used by the 18-bit
The ROM window addresses in Figure 1-2 areaddr
esses are shown in Table 1-1.
Q-bus. If the 16- or 22-bit Q-bus is used, the is confi
gured for bootstrap mode.

The window map is used when the MXV11-B
is used for the mapping feature.
A page control register (PCR) in the MXV11-B, rts
OB and DATOB operThe PCR is a read/write register which suppo DATI
.
ations. It resides at location 177520 in the /O page and is two bytes in length
s to one of the 256 word
The PCR which holds the window address fields point
winone
blocks to be accessed. The CPU reads the ROM via * of the two ROM
dow maps.

pointed to by a five-bit address
" Each of these window maps (bootstrap areas) isare
n in Figure 1-3. Bits 0
in the PCR. PCR format and bit assignments ROMshow
(8K word space). The 256through 4 point to 1 of 32 256-word blocks in
gh bootstrap address
word block pointed to by bits 0 through 4 is read throu
ord blocks in ROM. The 256773000g. Bits 8 through 12 point t0 1 of 32 256-w
through bootstrap address
read
word block pointed to by bits 8 through 12 is
765000s.

ROM Window Addresses for 16-, 18-, and 22-bit Q-bus

Table -1

Window 1

Start Addr

Q-bus

Window O

End Addr

Start Addr

End Addr

(octal)

16-bit

165000

165777

173000

173377

18-bit

765000

765777

773000

773377

22~tgi¢t

17765000

17765777

17773000

17773377

13 12

UNUSED

WINDOW #1

08 07

05 04

UNUSED

WINDOW #0

MA-D290-82

Figure 1-3

Page Control Register

GENERAL DESCRIPTION

1.5

SERIAL LINE UNITS

Data between the CPU and a peripheral device is serialized by an asynchronous
serial line unit. The MXV11-B uses two of these lines, SLU 0 and SLU 1.

Each SLU contains a DLART which is a Universal Asynchmnous Receiver/
Transmitter (UART) that has been modified by Digital Equipment Corporation.

SLU 1 can be used as a console terminal port but SLU 0 cannot.
The serial line interfaces are configured so that SLU 0 is electrically closer than

SLU 1 and therefore, has the higher interrupt priority.
The MXV11-B module also configures the SLUs so that SLU 1 tracks SLU 0.
That is, SLU 1 is assigned to the next higher starting address over SLU 0. This
is also true for the vector address assignments. An exception to this is when

SLU 1 is assigned as the console port.

If SLU 1 is selected for console, the Halt and Boot options are normally enabled.
These functions may be enabled under other conditions also. Either function is
invoked when SLU 1 detects a break character. If the Halt option is selected, a

break character halts program execution and the processor enters console

ODT microcode. If the Boot option is selected, a break character initializes the
system, then restarts the processor with the selected power up mode.
The baud rates for each serial line can be software programmable or can be

strapped to 300, 1200, 9600, or 38,400.

The SLUs transmit and receive EIA-423 or RS 232 signal levels at 300, 1200,
9600, or 38,400 baud. A 20 mA active or passive current loop operation may be

obtained with the DLV11-KA EIA to 20 mA converter option. The MXV11-B does
not support the reader run portion of the DLV11-KA and does not contain
modem control lines.

Break generation and error indicator bits the DLARTs provide overrun parity
and framing errors. These errors can be read via the status registers. No parity
bit or external baud rate clock logic is provided.

1.6 LINE TIME CLOCK

The line time clock (LTC) is a one-bit register (bit 06). When bit 06 is set, the

clamp is removed from BEVENT thereby enabling the LTC. The address of the
LTC is 777546. The LTC is derived from a 20 MHz crystal oscillator on the
MXV11-B board. The crystal oscillator is also used for memory refresh.
NOTE: If a customer uses the LTC feature of the MXV11-8B module, the module and the processor should be mounted in the same backplane.
A frequency divider connected to the oscillator provides a frequency of 617.4
KHz which is applied to the DLARTs of SLU1 and SLUO. The SLU1 DLART provides selectable line time clock frequencies of 50, 60, or 800 Hz. The desired
frequency is selected by wire-wrapping the frequency to a common wire-wrap

GENERAL DESCRIPTION
&

jost. The LTC can be enabled or disabled from driving the BEVENT line on the
)-bus by appropriate wire-wrap. The BEVENT line is used by the system for the
eal time clock (50 Hz, 60 Hz, or 800 Hz). The MXV11-B also provides a
3EVENT clamp which holds BEVENT low at power-up 1o aid system

liagnostics.

~AUTION: There should be only one source driver on the BEVENT line in any
system. In most systems, the system power supply supplies the BEVENT sig~al. This source must be disabled if the MXV11-B is used to drive the line clock.
1.7 LED DIAGNOSTIC DISPLAY REGISTER

The MXV11-B contains a four-bit LED diagnostic display register (DDR) used

but generates a reply on
for system diagnostics. The register is write-only

DATIO and DATIOB accesses. The DDR resides at location 777524 on the 1/O

page, and is enabled when the MXV11-B has its boot and console functions

enabled.

1.8 MXV11-B2 BOOTSTRAP/DIAGNOSTIC ROM OPTION

The MXV11-B2 bootstrap/diagnostic ROM is a plug-in option for the MXV11-B.
It performs bootstrap loading of programs (operating systems, for example)

from mass storage devices and also performs diagnostic tests on the memory

during power-up or when manually invoked. To install this option and configure
the module and system it will be used in, refer to Chapter 3.

The bootstrap function is automatic on power-up if the CPU is configured for
this feature. But an operator can intervene with a console terminal and boot
devices at nonstandard |/O page addresses, select a secondary system device,

or invoke a diagnostic utility.

Turnkey operation can be supported so that operator intervention is not needed
to start the bootstrap function.

Some of the MXV11-B2 ROM features ate listed below:
¢ Special standalone RT-11 volumes can be loaded and run.

. * A system can be configured to down-line load via a DECnet link without
operator intervention.

+ o All system devices currently available on the Q-bus are supported.
e Full 22-bit mapping support is included.

To use this option properly refer to the separate MXV11-B2 ROM Set User
Guide (EK-MXVB2-UG) supplied with it.

NOTE: In order to use this ROM’s examine/deposit command, the MXV11-B
module must be contained in a 22-bit Q-bus system and must be configured to

large systems (J37 jumpered to J36).

GENERAL DESCRIPTION

1.9

SPECIFICATIONS

The following paragraphs describe the physical, electrical, and environmental
specifications for the MXV11-B module. The module is designed to the Q-bus

specification.

1.9.1

Physical Specifications

Module:

Double height

Height:

5.187 inches

Width:

0.5 inch single layer

Length:

8.94 inches (bottom of fingers to top of handle extended)

Weight:

7.50z

1.9.2

Environmental Specifications

Temperature

Storage Temperature Range: —40° C to 66° C
Before using a module with a temperature beyond the operating range, bring
the module to an environment within the operating range and then allow it to
stabilize for a reasonable length of time (five or more minutes, depending on air

circulation).

Operating Temperature Range: 5° C to 60° C
Derate the maximum operating temperature by 1.8° C for each 1000 meters of
altitude above sea level.

Relative Humidity

Storage: 10% to 90%, noncondensing
Operating: 10% to 90%, noncondensing
Altitude

Storage: The module will not be mechanically or electrically damaged at altitudes up to 9 km.

Operating: Up to 3 km.
Airflow, Operating, Sea Level - Provide adequate airflow to limit.the outlet tem-

perature rise across the module to 5° C when the inlet temperature is 60° C. For
operation below 55° C, provide airflow to limit the inlet to outlet temperature rise
across the module to 10° C.
1.9.3

Random Access Memory Specification

Address Selection - RAM may be positioned on any 4K word boundary in the 0
to 252K word memory area. If bank select seven (BBS7) or bus refresh (BREF)

is asserted, the memory will not respond.

GENERAL DESCRIPTION

1.9.4

Electrical Specifications

Power Requirements — The following voltages are used by this module.
Voltage

Tolerance

+5VB

+5%

+5%
+5%

+5V
+12V

Pins

AA2, BA2, BV1
AD2, BD2
AV1

Power dissipated in each power supply configuration is as follows.
'No battery backup
+5V

17.25W

Typ

2457 W

Max
+12V

0.67W
0.71 W

Typ

Max

Battery backup configuration
+5V

12.90 W
15.95W

Typ
Max

+5 VB

4.35W
8.60 W

‘Typ
Max

+12 V-

Typ
Max

0.67TW
0.71 W

Data retention mode

VCC =0V, +12 V supply =0
+5 VB

Typ
" Max

4.35W
5.54 W

FUNCTIONAL DESCRIPTION

2.1

GENERAL

This chapter describes the following functional areas of the MXV11-B.
ROM addressing (direct mode and page mode)
RAM memory

Line time clock

Crystal oscillator

Serial line units

The registers and bit formats are describedin this chapter and are summanzed
in Appendix A.

2.2

PROM ADDRESSING

The PROM memory in the MXV11-B can be directly addressed (direct mode) via

the Q-bus or indirectly addressed (page mode) via the two windows in the I/O
page. Each window can specify 1 of 32 blocks (256 words per block). In direct
mode or page mode, bits 14-15 (16-bit bus), 14-17 (18-bit bus) or 14-21 (22-bit
bus), are used for address selection and are not used by the PROM.
‘2.2.1

Direct Addressing

Bits 9-13 (BDAL 9-BDAL 13) of the Q-bus are applied to the PROMs via tristate drivers, bits 1-8 (BDAL 1-BDAL 8) are applied directly to the PROMs and
bit 0 (BDAL 0) serves as a byte pointer. Figure 2-1 is a simplified block diagram
showing how direct addressing and page addressing are implemented.

To directly address the PROMs you must leave the PG L/DIR H jumper disconnected. This turns the tri-state drivers on and address bits 9-13 are directly
applied to the PROMs. As previously mentioned, bits 1-8 are wired directly to

the PROM.

When the page control register (PCR) is initialized both windows of this regzster

point to the first location in window 0 which is 773000. This is the PCR default
and allows all PROMs (whether 2K by 8, 4K by 8, or 8K by 8) to point to the
same location. The PCR is primarily used in |/O page address mapping and is
described in more detail in the next paragraph.

FUNCTIONAL DESCRIPTION

Mrace

CONTROL
REGISTER

rlK1ByTE-{

l
BDAL 8-12

‘

gyte

—

L _J

2.T0O-1

MUX

- ‘

WINDOW O

NORMALIZED

’

1
WINDOW

lM+5 L

~—A

BDAL 0-4

S‘

1 .

WINDOW

ADDRESS

BDAL 13
1, 2 —
BDAL

AL13

ADDRESS

BDAL 11 =1 LATCH

BDAL 10 —

BDALO

—

AL12
|AL11

Alio

ALD

PROM

|__EN |

AL12

CD—-

JUMPER * 0
ENABLE
(PAGE MODE) g
N

MAPPING

ADDRESS

>
-

EN
|

TRI-STATE

| BUFFERS

- 0 +h
o
L—o BA12H

>\ PROMS

BDAL 1-BDAL 8~

*ENABLE JUMPER DISCONNECTED FOR DIRECT MODE

Figure 2-1
2.2.2

Ma-D286-82

Direct and Page Addressing Block Diagram

1/O Page Addressing

To use page addressing you must connect the PG L/DIR H to GND jumper (J17
to J16), and BOOT L/PROM H to GND jumper (J44 to J45). Also, the boot ROM
used must reside on the MXV11-B module. Then specify 1 of 32 256-word
blocks of boot address space. The address space is selected by the read/write
page control register (PCR). The PCR holds two window address fields, designated window 0 (773000-773776) and window 1 (765000-765776).

The CPU reads the 256 word ROM through one of two windows in the 1/O page.
The windows are pointed to by a 5-bit address field in the PCR. Bits 8-12 of the

PCR point to window 1 and bits 0-4 point to window 0. The address of the PCR

is 777520.

The
-Figure 2.2 shows an example of how the page mode addressing is used.block
rd
256-wo
the
result,
a
As
window O field of the PCR is set to 30.
addressed as 30 is read into the window 0 field (773000-773777) of the 1/O
‘page.

The window 1 field of the PCR is set to 2. The 256-word block addressed as 2is
read into the window 1 field (765000-765777) the 1/O page.

FUNCTIONAL DESCRIPTION

UNUSED

©O07

00010
,

UNUSED

11000

)

1/0 PAGE

———

773000

28
27

o~
4

WINDOW
#1

765000

)
ROM
THIRTY TWO

256 WORD BLOCKS
MA-0313-82

Figure 2-2

Page Mode Addressing

The window 1 and window 0 address are applied to a 2-to-1 multiplexer which
multiplexes the window 1 or window 0 address to the output depending on the

state of address line 12 (BDAL 12). The 5-bit window address is applied to a
mapping PROM which is enabled by the PG L/DIR H jumper (J17) being connected. This jumper turns off the tri-state drivers causing the output of the tri-

state lines to be high impedance. Note that the tri-state drivers are turned
on
during direct mode addressing and are turned off during window mapping.
The mapping PROM normalizes the window address - the normalized address
is derived from the true address via a mapping matrix. Table 2-1 shows the true

addresses (window block) and the corresponding normalized (ROM)

addresses.

' ‘W\r “

‘The 5-bit normalized address is connected to the tri-state output lines which are
now high impedance. As a result, the normalized address is applied to the

PROMs.
The 32 blocks of memory may not be contiguous. The mapping function takes

care of this and its operation is transparent to the user.

FUNCTIONAL DESCRIPTION

ROM Window Map

Table 2-1
|

Normalized
0O ROM
Address

Window
Field
0

00000

01000

02000
03000

3
4

04000

05000

07000

06000

6
10
11

13
14
15
16

20
21
22
23
24
25
26
27

31
32

Maximum address for 2K by 8 PROM

Maximum address for 4K by 8 PROM

20000
21000
22000
23000
24000
25000
26000
27000

30000

" 30

13000
14000
15000
16000

17000

33
34
35
36

10000
11000
12000

31000
32000
33000
34000
35000
36000

37000

Maximum address for 8K by 8 PROM
.....

2.3 RAM MEMORY FUNCTIONAL DESCRIPTION

’P

Figure 2-3 shows a simplified block diagram of the RAM memory. The memory

consists of 64K by 4 Single In-line Packages (SIPs). The following paragraphs
.describe read/write memory access, refresh access, and the arbitration logic
-

for memory access.

2.3.1

Read/Write Access

The address from the Q-bus is saved in an address latch through a set of Q-bus
transceiver interfaces. The address is then separated into high and low bytes by
a 16-to-8 line multiplexer. These bytes are then applied to the RAM address

lines via a second multiplexer which selects between the bus address or a

refresh address. The second multiplexer is formed by the tri-state outputs of
the refresh counter and the 16-to-8 multiplexer. Refresh has priority over RAM
read/write request and peripheral 1/O (PIO) requests.

[

C S 3Ha v

WVH1SLUVaV'Yy——— 0SN8HADX

§OLVI1IS0e~¥3QIAIGAtH3INOJgWvd
FUNCTIONAL DESCRIPTION

av3ay

Z9LHMB

177]

—-

FUNCTIONAL DESCRIPTION

However, if a read or write memory cycle is in progress, that cycle completes
before a refresh cycle starts. On a read cycle, the read data from memory is
applied to a data buffer and then to the transceiver interface for transfer to the
Q-bus. On a write cycle, the data from the Q-bus is applied to the transceiver
interface and then directly to the memory.
2.3.2

Refresh Access

The RAM memory is refreshed at a 76.8 KHz rate. This rate is obtained from a
19.660 MHz crystal oscillator which has been applied to a frequency divider.
The divider divides the frequency by 256 to yield 76.8 KHz. This frequency is
applied to a refresh counter which refreshes each row of the MOS$ RAMs at the
-

76.8 KHz rate.

2.3.3

Arbitration-Logic

" Bits 13-15 of the 16-bit Q-bus address are applied to the decode logic. For the
18-bit Q-bus, bits 13-17 are applied to the decode logic, and for the 22-bit
Q-bus bits 13-21 are applied to the decode logic. This address is the address
the CPU wants to access.

The SLU start address, the PROM start address, and the RAM start address
are selected by wire-wrap pins on the MXV11-B module. These addresses are
also applied to the decode logic.

Finally, BWTBT (Bus Write Byte), BBS7 (Bus Bank Select 7), and BREF (Bus
Refresh) are applied to the decoder via bus receivers. The decode logic
decodes all these inputs and outputs a RD REQ, WR REQ, or PIO REQ.

If the BBS7 signal is asserted at the input to the decode logic, memory will not
‘respond and the system can only access the 1/O page. If the BREF signal is
asserted, memory will not respond. If the BWTBT signal is asserted, it indicates
a DATO(B) operation will occur. If BWTBT is negated, a DATI or DATI(B) operation will occur. In order for the DATO or DATI operation to occur, BREF must be
negated.

If the CPU is doing a write operation to memory, BWTBT is asserted and the
decode logic asserts WR REQ. If the write operation is to the 1/O page, BBS7 is

also asserted. Conversely, if the CPU is doing a read operation, BWTBT is

" negated, and the decode logic outputs RD REQ.

PIO REQ is asserted when access is made to a boot ROM, SLU, or 1/O page

The RD REQ, WR REQ, and PIO REQ signals are mutually exclusive in that only
one of the signals can be asserted at any given time. These signals, along with

the REF REQ signal are applied to the arbitration logic which arbitrates between

REF REQ and one of the other requests (RD REQ, WR REQ, or PIO REQ). The
first request is the one that is serviced first. But, when a REF REQ and RD REQ,
WR REQ, or PIO REQ occur almost simultaneously, the arbitration logic
decides which request gets serviced first.

FUNCTIONAL DESCRIPTION

When this decision is made, the output of the arbitration logic starts the clock to
initiate the memory access via the memory control logic. If the memory access
is a write word, the WRITE HI BYTE, WRITE LO BYTE, RAS and CAS signals
are all asserted by the memory control logic. If the memory access is a write
byte, the appropriate byte signal (WRITE HIGH BYTE or WRITE LO BYTE), and
the RAS and CAS signals are asserted. Data from the Q-bus is fed to the RAM
via the transceiver interface.

If the memory access is a read request, the WRITE HI BYTE and WRITE LO
BYTE signals are negated and the RAS amd CAS signals are asserted. Data
frcm memory is applied to a data buffer, the transceiver interface, and then to
the CPU via the Q-bus.

The memory control logic also provides control signals for the MXV11-B registers, PROMs, serial line units, refresh circuit, transceivers, and the data buffer.
2.4 CRYSTAL OSCILLATOR
The crystal oscillator (Figure 2-4) in the MXV11-B oscillates at 19.66 MHz. The

oscillator's output is applied to an 8-bit frequency divider. The divider divides

the oscillator frequency for the various system functions described below.

The DCLK signal is derived from the oscillator and clocks the DLARTs. The

DCLK signal is 614.4 KHz (19.66 MHz divided by 32). There is a DLART for each
SLU. The line time clock for the MXV11-B is obtained from one of three selectable frequency outputs of the DLART. The DLART has outputs of 800 Hz, 60
Hz, and 50 Hz. One of these frequencies is chosen by wire-wrapping the appropriate pins.

The PCLK signal of 307.2 KHz (19.66 MHz divided by 64) clocks the —12 V
charge pump circuit. The REF CLK of 76.8 KHz (19.66 MHz divided by 256)
clocks the refresh counter. Each row of RAM memory chips is refreshed at the
76.8 KHz rate.

19.66 MHz

DIVIDER

REF CLK

(8-BIT)

v
Q

[

DLART

| 60H:

cons

|
,8
76.8KHz | REFRESH |[
MALO7

COUNTER

CLOCK
DISABLE

PCLK

307.2KHz

CHARGE

ol pump

CIRCUIT

}—e —12v
Ma-O287.-82

Figure 2-4

XTAL Oscillator Block Diagram

‘

FUNCTIONAL DESCRIPTION

aEnEnEE

{(BDAL 00 RESET)

‘

55+

16.7msec

DLART

SLUY

800H2z

60H2

50Hz

@.7

\®)
+5

e
LTC 1

BDAL B

B EVENT L TO CPU

LTC 2
LATCH

)

LTCCLKH
3

MA-0311-82

Figure 2-5

Line Time Clock Diagram

2.5 LINE TIME CLOCK
Figure 2-5 is a simplified block diagram of the line time clock logic. The DLART

associated with SLU 1 has selectable frequency outputs of 800 Hz, 60 Hz, and
50 Hz. To use one of these frequencies as the line time clock, the appropriate
post must be wire-wrapped. Figure 2-5 shows the 60 Hz frequency selected. In
addition, bit 6 of the LTC latch must be set and the LTC 1 to LTC 2 jumper must
* be connected. This allows BEVENT L to be driven at a 60 Hz rate by the MXV11B. In most Digital systems, the power supply drives BEVENT.

" CAUTION: There can only be one source of BEVENT in a system.
2.6

DIAGNOSTIC DISPLAY REGISTER

The diagnostic display register (DDR) resides at location 777524 in the |/O
page. It is a write-only register but generates a reply on DATIOB and DATOB
has its Boot and Console
accesses. DDR is only enabled when the MXV11-B
functions enabled.

Only bits 0-3 of the 16-bit word are used. These bits correspond to four red
LEDs on the board (bit 3 is the MSB and bit 0 is the LSB). Figure 2-6 shows five
* LEDs - the four red LEDs comprise the DDR and the green LED indicates
-

power-on.

FUNCTIONAL DESCRIPTION

2.7.2

Interrupt Vector Selection

Vector address selection covers the vector address space from 010-376.
NOTE:

Be careful - some addresses are reserved.

Bits 3-7 of the vector address can be pmgrammed (via wire-wrap) to select

independent vector addresses for each of the serial line units. Bits 0, 1, and 8
are always 0 for the MXV11-B (Figure 2-7).

The vector assignment for SLU 1 is the next higher vector location over SLU 0.
The exception is if SLU 1 is selected as the console port. In this case, serial line
unit 1 has a vector address of 060 for the transmitter and 064 for the receiver.

. Each of the DLART transmit and receive registers track each other. Bit 2 of the
vector address automatically selects a zero for the receiver and a one for the
transmitter of each serial line interface.

0 FOR RCVR
1 FOR XMTR

VECTOR
.

ADDRESS

(SELECTED VIA

JUMPERS IN
TABLE 3-6)

Figure 2-7

MA-03 10-82

SLU Vector Address Bit Format

2.7.3 SLU Register Addressing

The MXV11-B has four registers associated with each of the two SLUs. The
Receiver control/status register
Receiver data buffer
Transmitter control/status register
Transmitter data buffer

(RCSR 0) - Table 2-2
(RBUF 0) - Table 2-3
(XCSR 0) - Table 2-4
(XBUF 0) - Table 2-5.

u'm

registers for SLU 0 are:

The registers for SLU 1 are:

Receiver control/status register
Receiver data buffer ~
Transmitter control/status register
* Transmitter data buffer

(RCSR 1) - Table 2-2
(RBUF 1) - Table 2-3
(XCSR 1) - Table 2-4
(XBUF 1) - Table 2-5.

Both SLUs have the same bit assignments and are located in the 1/O page.
BBS7, when asserted, specifies the 1/O page and bits A3-A12 specify the
peripheral device in the 1/O page. SLU 0 can be assigned one of eight address-

es (Table 3-5). SLU 1 can be assigned one of eight addresses and may be
assigned as the console port (777560).

" FUNCTIONAL DESCRIPTION

Table 2-2

RCSR

Receiver Status Register Bit Assignments (RCSR)

UNUSED

RECEIVER

ACTIVE

DONE
»

INTERRUPT

a0306A.53
s

ENABLE

Bit

Description

15-12

Unused

Receiver active
read only

A logic one indicates that the receiver is

active. Set at the center of the start bit of
the input serial data. Cleared at the
expected center of the stopbitatthe end

of the time prior to the leading edge of
RCV DONE. Also cleared by power up

sequence.

10-8
7

Unused
RD

Receiver done read
only

A logic one indicates that the serial

interface has received a character. If
enabled by bit 6, receiver done requests
aninterrupt. Receiver doneis cleared by
reading the receiver data register or by
power-up sequence.

IE
interrupt enable

read/write

5-0

A logic one enables receiver interrupts;
a zero disables interrupts. Cleared by

Initialization.

Unused

FUNCTIONAL DESCRIPTION

20
L

Table 2-3

Receiver Data Buffer Bit Assignments (RBUF)
13

UNUSED

RBUF

DATA

FRAMING | RECEIVER
BREAK
ERROR

ERROR

OVERRUN

UNUSED

ERROR

MA-03068
82

Description

Bit

15
.

ER
Error read only

A logic one indicates that bit 13 and/or
bit 14 is a one. Cleared when the bit is

OE
Overrun error read
only

A logic one indicates a word in the
receiver buffer had not been read when
another word was received and placed

read or cleared by power-up sequence.

in the receiver buffer. Cleared when read

or by power-up sequence.

FE
Framing error read
only

A logic one indicates that a start bit was
detected but there was no corresponding
stop bit. A framing error is generated
when a break is received. Cleared when

read or by power-up sequence.

Unused

RB
Receiver break read
only

This bit is set when serial-in (Sl) signal
goes from a mark to a space and stays in
the space condition for 11 bit times after
serial reception starts. This bit is cleared
when the Sl signal returns to the Mark

condition, or by power-up sequence.

Unused

10-8

7-0

Data read only

- These eight bits hold the most recent

byte received. When a new byte is transferred to the data buffer, the RCV DONE
inthe RCSRis set BitOisthe LSBandbit
7 is the MSB. Cleared by power-up
sequence.

FUNCTIONAL DESCRIPTION

Table 2-4

Transmitter Status Register Bit Assignments (XCSR)

XCSR

1110

UNUSED

TRANSMITTER| PROG.
READY

pmlas*

BAUD

RATE 2

PROG.
BAUD

RATE 0

RATE

ENABLE
INTERRUPT

PROG.

ENABLE

BAUD

MAINTENANCE

BREAK

RATE 1
’

Bit

Description

15-8

Unused

A logic one indicates the serial

Transmitter ready

interface is ready to accepta

read only

character into the transmitter data
register. |If enabled by bit 6, transmitter

ready requests an interrupt Transmitter
ready is cleared when data is writteninto

the transmitter data register. It is set by
power-up sequence.

5-3

A logic one enables transmitter

Interrupt enable

interrupts. A logic zero disables

read/write

interrupts. Cleared by initialization.

BR2-BRO*

When PBR-bit 1 in XCSR is set, these

Programmable baud

bits determine the baud rate (set by

rate select

software if SOFT jumper connected to

read/write

GND). If SOFT jumper is connected to
OPEN, baud rate is obtained via wirewrap. Bits BR2-BRO are cleared by PBR
Inhibit (SOFT EN) or by power-up
sequence.

MAINT

This bit facilitates a maintenance self-

Maintenance

test When the bit is set, the transmitter

read/write

serial output is connected to theseceiver
serial input and the external serial input

is disconnected. This bit is cleared by
initialization.

Read onlyasazerowhen PBRI(programmable baud rate inhibit) is asserted low.
- PBRI is asserted low by connecting the SOFT ENto OPEN jumpers(J14 toJ15).
In this case, the baud rate is determined by the wire-wrap jumpers (J7-J11).

Otherwise, with SOFT EN to GND (J14-J13), the bit is read/write. This bit is
cleared by power-up sequence or PBRI(SOFT EN to OPEN jumper-J14-J15).

WMA-Q306C-82

FUNCTIONAL DESCRIPTION

"Table 2-4

Transmitter Status Ragi‘amr Bit Assignments (XCSR) (Cont}
Description

Bit
P

PBR"

This bit selects between internal and

Programmable

to GND jumper); else
read only as O

to OPEN Jumper connected (programmable baud rate inhibit (J14 to J15).

BK
Break

When this bit is set, it causes the serial
output signal to go to a space condition.

read/write

A space condition longer than a char-

Read/write
when software

programmable baud

rates enabled (SOFT

external baud rate selection. When set
(enable), the baud rate is determined by
the PBR2-0 bits in this register. When
clear(inhibit), the baud rate is determined
by the J1, JO wire-wrap pins. This bit is
cleared by power-up sequence or SOFT

baud rate enable

actertime causes aframing errorwheniit
is received and is regarded as a break

Cleared by bus initialization.

Read only asazerowhen PBRI(programmable baud rate inhibit) is asserted low.
PBR!is asserted low by connecting the SOFT EN to OPEN jumpers(J14 to J15).
In this case, the baud rate is determined by the wire-wrap jumpers (J7-J11).
Otherwise, with SOFT EN to GND (J14-J13), the bit is read/write. This bit is
cleared by power-up sequence or PBRI(SOFT EN to OPEN jumper-J14-J15).

Table 2-5

Transmitter Data Buffer Bit Assignments (XBUF)

XBUF

DATA

UNUSED

MA-00080-82

Bit

Description

15-8

Unused

XMIT DATA BUFFER
read/write

Transmitter data buffer- this byte

register holds a copy of the most recent
byte written into it. When a byte is written
into this register, the transmit ready (TR}

bit in the XCSR register is cleared. This
byte is copied into the transmitter serial
output register whenever that registeris
empty and the bit is clear. The TR bit is
set when a byte is copied from the transmitter data buffer into the serial output
register. Reading the contents of this

m‘..

7-0

FUNCTIONAL DESCRIPTION

The SLU registers for both SLUs are addressed via addres
s lines A2, A1, and
AQ from the address latch (Figure 2-8). The addres
s latch and decoder are the
same as shown in Figure 2-3. A2, A1, and A0 are

applied to both SLUs. The

SLU selected is determined by the chip select (CS) input

function of the decode logic.

to the DLART and is a.

The chart in Figure 2-8 shows how A2, A1, and A0 select
one of the four DLART
registers by determining the least significant octal
digit of the address.
NOTE: All bits in the SLU registers are reset
by a power-down/power-up
sequence which causes signals BDC OK H and BINIT
L to go low and then go

These bits are also reset if the operator presses
certain systems. There are certain bits (Interrupt

a restart switch contained in
Enable, Break, and Maint) in

the SLU registers which may be cleared by bus initialization

and by the power-

up sequence (refer to Tables 2-2 through 2-5).

REF REQ
ADDRESS
BITS 13-21

BWTBT

DECODE | RD REQ

BBS7

WR REQ

BREF

PIO REQ

SLU ADDR SE L&CT?

ARBITRATOR

TOSTART/STOP

= CLOCK

SLU 1
L SLU O

OLART

XMT CHARACTER

SLU 0

FROM

RCV CHARACTER

|[—ed{A2

PERIPHERIAL

fi:—?& —edAD

—ad
A 1
|

DLART

‘

FROM | A2~

' XMT CHARACTER

RCV CHARACTER

PERIPHERIAL

SLU1

ADDR < A1 —#»

DATA

Q BUS VIA

LATCH

AQ —

-»—-%-—-

XCVR
INTERFACE | 4

DATA
)

[nsers*rw A2 | a1 | ao- 110
[ L350 OF
OF
RCSR

RBUF

XCSR
.

XBUF

*AD0= BYTE POINTER

Figure 2-8

SLU Register Addressing

FUNCTIONAL DESCRIPTION

2.7.4

Baud Rate Selection
|
The baud rates are the same for transmit and receive functions of the same

DLART. The baud rates can be set via strapping or by software programming.

Strapped Baud Rates - Each of the SLUs can be strapped to one of four baud
rates (300, 1200, 9600, and 38.4K) when the SOFT EN to OPEN jumper is connected. This disables the software programmed baud rates in both SLUs.

Each SLU has a set of two wire-wrap posts strapped in various combinations to
select the desired baud rate (Table 3-4).

Software Programmed Baud Rates - The software programmed baud rates
are enabled if the SOFT EN wire-wrap post is strapped to GND (J14 to J13).

Software then has to write the XCSR (Paragraph 2.7.3) of each DLART to set up
the baud rates.
In order to enable software controlled baud rates, SOFT EN must be jumpered

to GND (J14 to J13) and the programmable baud rate enable (PBRE) bit (bit 1 of
XCSR) must be set. If this bit is not set, the strapped (hardware controlied) pins
(Table 3-4) determine the baud rate. With PBRE set, the programmable baud
rate bits (PBR 2, 1, and 0 in XCSR) select the baud rate in accordance with this

chart.

PBR

Octal

Baud

PBRE

Data

Rate

002

012

600

022

1200

300

032

2400

042

4800

052

9600

062

19200

072

38400

At power up, if SOFT EN is connected to GND (J14 to J13), the software baud

rates are enabled. PBR 2, 1, and 0 are reset to 0 which defaults to 300 baud. If

the PBRE bit is set to 0, the DLARTs monitor the hardware selectable baud

If the operator sets PBRE to 1, the DLART disregards the jumpers and uses the
baud rates determined by PBR 2, 1, and 0. Those bits must be set to their prop-

ef baud rates.
If the SOFT EN jumper is not connected to GND at power up, the baud rate is

determined by hardware selectable baud rate jumpers J7-J11.

rates (jumpers J7-J11).

F‘UNCTIDNAL DESCRIPTION

2.8

CABLES

Table 2-6 lists part numbers, options, applications, and cabling lengths avail-

able for the MXV11-B module. Digital offers the BC20M-50 cable for MXV11-B
to DLV11-J operation. Because longer cables usually require routing without

connectors attached, the user should make cables for lengths greater than 15
meters (50 feet). Cable material must adhere to EIA RS-423 specifications. The

connectors on the MXV11-B module are AMP-87272-8 (2 pin X 5 pinon 0.1 inch
centers). These connectors can mate with a wide variety of low cost cables
including 10-conductor flat cable. Note that a pin 1 baud rate clock is not used

on this module.

Pin 10 carries +12 Vdc “"{o supply power for the DLV11-KA option. Therefore,
pins 1 and 10 should be unterminated if the DLV11-KA option is not used. Cable

retention in the module is provided by locking clip contacts (AMP PN87124-1).
The locking clips hold the receptacle (AMP PN87133-5) in the module connector
when the cable is pulled. To remove the cable from the connector, pull back the

cable receptacle to disengage the locking clips.

Table 2-6

Cable

BC21B-05

Definition of Cables

Application

Length

EIA RS-232C modem cable to interface with

1.5m(5 1)

modems and acoustic couplers(2 X 5 pin AMP
female to RS-232C male)

BC20N-05

EIA RS-232C null modem cable to directly
interface with a local EIA RS-232C terminal

1.5 m(5 ft)
~

(2 X 5 pin AMP female to RS-232C female)

- BC20M-50

BCOS5D-10

BCO5D-25

EIA RS-422 or RS-423 cable for high-speed
transmission (19,200 baud) (2 X 5 pin AMP
female to 2 X 5 AMP female)

15 m (50 ft)

Extension cable used in conjunction with

3m(10 ft)

BC21B-05

Extension cable used in conjunction with

7.6 m(25f1)

BC21B-05

BCO3M-25

“Null modem"” extension cable used in
conjunction with BC21B-05

7.6 m(25ft)

Note: “Strapped"’ logic levels are provided on data terminal ready (DTR) and

request to send (RTS) to all operation of modems with manual provisions(such as
Bell

B auxiliary set).
A data set with 804
103

FUNCTIONAL DESCRIPTION

The MXV11-B may operate with several
peripheral device cabl es and options
for flexibility when configuring systems.
Figures 2-9 and 2-10 show the variety

" of cables and options used with the MXV11B

the primary application of each.

MXV11.B TO MODEM OR ACOUSTIC COUPLE
R
A
e
o

MXV11-B [

ggmm

BC218-05

{"T ] acousTic

1.5M (5 FT)——
o COUPLER

46 M (15 FT)——d

)

]
:

(NOTE 1)

MODEM
R

ACOuUsSTIC |

COUPLER

Mopem
ACOUSTIC

COUPLER

DL11-D, DLV,

MXV11-B TO SLU CHANNEL INTERFACE

Py—"

DLV1Y-F

MXV11-B

(EIA MODE)

BCO1V-25

DL11-D, DLV 11

BCOSC-26

| DLVII.F

(EIA MODE])
BC21B-05

Mxv11e L]

Per

BCO3M-XX (NOTE 3)

4.2 M (14 FT

(14
FT)
Nos L
BC20N-0
27 M (9 FT)—

(NOTE 2}
gT

11
M 8
(39 FT)

NOTES:
1. MODEM USED IS A “MANU
AL TYPE"

(9 FT)

SUCH AS BELL 103A WITH 8048,

2. DEC EIS RS-232C TERMI

NALS (VT52,
LA36, LS120, ETC.) COME EQUIPP
ED

WITH A 9 FT CABLE. NON-D
EC EIA

RS-232C TERMINALS ARE CONNE
CTED
SIMILARLY EXCEPT 9 FT OF LENGTH

MUST BE DEDUCTED FROM
THE TOTAL

CABLE LENGTH.
3. XX = CABLE LENGTH WHICH
MUST BE
SPECIFIED WHEN ORDERING.
&

3270

MA.BDITA

Figure 2-9

MXV11-B EIA Cable Configurations

FUNCTIONAL DESCRIPTION

MXV11-B TO 20 MA TERMINAL

DLVI1-KA
N

g
|

_—

BC21A.-03

{:]:

DLV11-KB

DEC 20 MA

TERMINAL

(LA36, VT52
LA35, LS120

DLV11.KA

r
-

BCOSF.X

MXV11-B

(NOTE 3)

a.;
BC21A03
-

mxviis

LA1B0S, ETC.)

- 1’

DLV11-KB

}

|
(NOTE 2)

D |

LT33-DC/DD/DE

OR ASR33

WITH LT33-MD
MODIFICATION

KIT.

DLV11-KA

S
:]

PR/SO1

2 BC21A-03
*

DLV11.KB

I::}__ (NOTE 1)

BCOSF-XX

MXV11.R

1
MXV11-B TO SLU CHANNEL INTERFACE

?
D r
MXV118

e
A

DLV11.-KA
A
BC21A-03 [I

TERMINALS
(LA36, VT52

LS120, ETC.

DLV11-KB

I DLV11.KB :]—_':}aczwma j,m oviiy C
BCOSF-XX

(1%

OLVI1.KA

DLV11-KA

2 ——

]

Mxvns

BC21A-03

r-—-r—

Iacoap.xx{:D_scow.oa

DLV11-KB

1
NOTES:

1.PR/SO1 IS A SERIAL LINE PAPER TAPE

2. MXV11-B WILL NOT SUPPORT DLV11.KA
READER RUN CIRCUITS.

3. XX = CABLE LENGTH WHICH MUST BE

SPECIFIED WHEN ORDERING.

g&‘l{&:m.wh

LOADER.

L’égg;m

I
MR .32

MAEOIRA

Figure 2-10

MXV11-B 20 mA Cable Configurations

FUNCTIONAL DESCRIPTION

When designing a cable for the MXV11-B, consider these several points:

1. To connect directly to a local EIA RS-232C terminal, you must use a null
modem. To design the null modem into the cable, switch Received Data
(pin 2) with Transmitted Data (pin 3) on the RS-232C male connector as
shown (Figure 2-11).

2. The receivers on the MXV11-B have differential inputs. Therefore, when
designing an RS-232C or RS-423 cable, you must tie Receive Data (pin 7

on the 2 x 5 pin AMP connector) to signal ground (pins 2, 5 or 9)in order

)

to maintain proper EIA levels (Figure 2-12).

EIA

RS-232C

MXV11-B

{3 (MW}CLEAR TO SEND (CB)

GND

395

RCV DATA

> 7>

{ 4 &—- REQUEST TO SEND (CA)

[

< 6 (w}oAm SET READY (CC)

555

]

+12VvDC

20& -~ DATA TERMINAL READY (CD)

/2 Wi ot

F1—ene—310>

RCV DATA

> 8>

«{ 3 €— RECEIVED DATA (BB)

XMIT DATA

GRD

{ 2 é—— TRANSMITTED DATA (BA)
< 7 é—— SIGNAL GROUND (AB)
—{ 1 é— PROTECTIVE GROUND (AA)

@CABLE |
EIA

CONNECTOR

MODULE

RS . 232C

CONNECTOR

Figure 2-11

BC21B-05 Modem Cable

MXV11-8
3
~ XMT DATA + >

TM
-

EIA RS-232C
3

- RCV DATA

|
)
- 2 - XMT DATA
—

RCV DATA+ -8

->
RCV DATA
N

i L
o

RO|

CHASSIS

|
<

IMPORTANT: GRD TO
Figure 2-12

)
-

]
[
L

'R
LY

SHIELD

7
1

GRD
rd
Y

MA-0393-82

BC20N-05 Null Mcrdem Cable

MODEM
MA 036282

»
~*

FUNCTIONAL DESCRIPTION

To mate to the 2 X 5 pin connector block, you

Cable receptacle (1)

need the following parts.

AMP PN 87133-5
DEC PN 12-14268-02

Locking clip contacts (9)

AMP PN 87124-1

DEC PN 12-14267-00
Key pin (pin 6) (1)

AMP PN 87179-1

DEC PN 12-15418-00
2.8.1 Interface Connector Pins
Two 10-pin connectors (one for each serial line)

are provided on the MXV11-B
ons are described in Table 2-7 and

module. Connector pins and signal functi

shown in Figure 2-13.

Table 2-7

MXV11-B I/O Connector Pin Functions

Signal

BRCLK

Function
Baud rate clock This output provides a clock

signal at a

frequency of 16 times the selected aud rate. This
used as an output from the MXV11-B and does not

external clock inputs.

Ground

XMIT

Ground

Key, pin not provided

RCV-

Receiver input most negative

RCV+

Receiver input most positive

Ground

+12V

Transmitter outpuf

Power for the DLV11-KA option

]

pin is

FUNCTIONAL DESCRIPTI

TYPICAL INTERFACE

CONNECTOR
10F 2

NO PIN

(FOR CABLING

INDEXING)

TOP OF MXV11-B MODU
LE

Figure 2-13

MA.0308.82

MXV11-B Connector Pins

2.8.2 Current Loop
The MXV11-B module can inte

rface with 20 mA active or pass
ive current loop
devices when used with the DLV
11-KA option. This option cons
ists of a DLV11KB (ElA-t0-20 mA current loop
converter) and a BC21A-03
interface cable. The
MXV11-B cannot Support the
reader run portion of the DLV
1 1-KA option. The
DLV11-KA option is placed bet
ween the MXV11-B serial line
output and the 20
mA current

loop peripheral device. Figu
re 2-10 shows the cables
and devices
which may be used with the
DLV11-KA option.

JUMPER CONFIGURATIONS

3.1

GENERAL

This chapter describes how the user can configure the MXV11-B module to
function properly in his system. The jumpers used with this module are of two

types - push-on connectors and wire-wrap. However, sometimes the user has
to wire-wrap certain jumpers (for example, line time clock jumpers). The push-

on connectors are associated with grouping of pins where one of the pins is
open. These connectors allow two adjacent pins to be jumpered. If the jumper

relating to a function is to remain disconnected, one pin of the push-on connector is placed on the pin associated with that function. The other pin of the pushon connector is placed on the open pin, which is not connected to ground, +5 V,

or any logic function, and merely serves as a holder for the push-on connector.
If a push-on connector is missing, a wire-wrap jumper may be substituted.
When installing jumpers, arrange the wire runs so that no more than two wires

are on each post and there is no level jumping between posts.

MXV11-B modules shipped from the factory have a 0 ohm resistor supplying

the MOS RAMs with nonbattery backup power of +5 V; 8 push-on connectors;
and no wire-wrap jumpers connected. Figure 3-1 shows the default configura-

tion for the push-on connectors designated W3-W10. There are two 0 ohm
resistors used for battery backup connections: W1 and W2. Only one of them
may be inserted at a time. For nonbattery backup applications, W2 is inserted.

Paragraph 3-2 summarizes these default conditions and the defaults for the
wire-wrap jumpers.

- 32

JUMPER CONFIGURATIONS

—

EEREEEE N*

W10

ML
%3‘1”—":?5—
# e

B DSJD I

""*”lr‘-fl:u _wa

)

_
o
J
L

—

L‘E‘.‘;

MWES‘{

NMMWr'W.’n
a¥s

}mD___J

\vn

uWWW"wB
U

- JJJMJM%*J%#E;

22
= RS RV

m___ij___}_____j

__J

_J_"JIM “'m-.-i[—

|
]

Figure 3-1

Default Configuration of Push-On Connectors

.
MA.0353-82

JUMPER CONFIGURATIONS

Before trying to configure the MXV11-B module, complete the following checklist. The checklist, jumper locations in Figure 3-2, the flow diagram in Figure 3-3,

and the tables in this chapter should be used when configuring a system.

User’'s

Shipped

Configuration

Do you wish to connect the

system console to this
MXV11-B? If no, disregard

following questions marked
with an *. If yes, the

console must be connected

to SLU #1.
2)*

Yes

Do you wish system to halt
on break from console?

3)"

Yes

Do you wish system to
reboot on break from

console?
4)

;

Whatis desired address/

vector for SLU 07?7

Whatis desired address/

vector for SLU 1?

6)*

Will this MXV11-B contain

MXV11-B2 ROM?
7)

776500/300

777560/60

"No

Wil this MXV11-B contain

user ROM?
If yes, at what address?

No
r~N/JA

*Are user ROMs to be

addressed via page mode?

N/A

What is ROM size?

N/A

Whatis ROM type?

N/A

8)*

JUMPER CONFIGURATIONS

User’'s

Shipped

Configuration

Do you want software
control of line time

clock ()?

Does this system have
“Q" or "Q22" bus?

10)

QBus

Do you wish this module

to be source of line
time clock (BEVENTL)?

11)

Ifyes, at What frequency
(50, 60, or 800 Hz)?

12)

Do you wish software
control of baud rate?

13)

What hardware controlled
baud rates are desired?

SLUO/SLU1
14)

‘

300/9600

s battery backup

desired for RAM memory?
-15)

What is RAM starting

address?

000000

A series of tables in this chapter describe the jumpers on the module. An asso-

ciated figure (Figure 3-2) shows the physical location of the jumpers with

s e gt
s st i

‘Qm» -

respect to the ICs on the module.

JUMPER CONFIGURATIONS

SOCKETS
XE19
HI

BYTE

/)]

J34 J35 436 J37

J30 J31 J32 433
T

Figure 3-2

MXV11-B Jumper Locations

(S Y —

LO BYTE

PROM

_3[]] L3

(xe28

MA-88548

JUMPER CONFIGURATIONS

( START )
Y
COMPLETE CONFIGURATION

QUESTIONNAIRE
IN BACK

J16eTM J2
JUMPER

J1 o o J2
JUMPER NOT

CONNECTION

CONNECTED

% INDICATES SHIPPED

CONFIGURATION

SLtu 1=
SYSTEM
CONSOLE

J62 TM J63

Je2e -s63

HALT

ON BREAK

EROM SLU 1
{

J3e o4

}'—’

SELECT SLU O AND
SLU 1 STARTING

YOU WANT

THE SYSTEM TO

TABLE 1

‘

REBOOT ON BREAK

ADDRESSES FROM

FROM SLU 1

NOTE
3

SLU 1 VECTORS
ADDRESSES FROM

SELECT SLU O AND

J4e ©J5

]

TABLE
2

MABBES

Figure 3-3

Jumper Configuration Flow Diagram (Sheet 1)

JUMPER CONFIGURATIONS

SELECT ADDRESS
FOR SLU 0 FROM
TABLE1

SELECT VECTOR FOR
SLU 0 FROM
TABLE 2

INSTALL JUMPERS:
.

INSTALLING

MXV11-8B2

J4a e J45

YES

J16

v J17

J50 ¢ J51

J27 o~ 428

(NOTE 6)

;

Jag ¢ v 51

vES

AND ADDRESSED AT
773000

J19 v J20

144 o J45

}

J20 - - J21 N

AND

765000

THESE ROMS

YES

TO BE ADDRESSED
VIA PAGE
MODE

USER ROMS

TO BE INSTALLED
AND ADDRESSED

NOTE &

*
[

J16 o o J17

s34 ~J36

*
l

NOTE 7

[

e, o5 ]

)

]

J38 o o J36
l

PER TABLE

J8e~7

SELECT ROM SIZE

SOFTWAR

2 4

FROM TABLE 4

028

YES

)
(SEE NOTE 1)

327 o~ I28

NOTE:

REFER TO NOTES IMMEDIATELY FOLLOWING THIS DIAGRAM,
MA-BASE

Jumper Configuration Flow Diagram (Sheet 2)
4

Figure 3-3

JUMPER CONFIGURA

TIQNS

SELECT ROM TYPE
FROMTABLES

Q-22BUS

SYSTEM

N\ YES

‘

JBeuz7

L NO

L__Js6e esa7

DO You
WANT THIS

|
|

MODULE TO SOURCE
NoTE

Y ES

BEVENT L TO
NLHE SYSTEN

322

J220

oJ24

J22

0425

INSTALL

50Hz

22~
23

B0Hz

224
124

800

22025
|

NOTE: REFER TO
NOTES IMM

EDIATELY

_FOLLOWING THIS DIAG

RAM.
Mases7?

Figure 3-3

Jumper Configuratio

n Flow Diagram (Sheet

JUMPER CONFIGURATIONS

SOFTWARE
CONTROL OF BAUD
RATES OF BOTH-

J13e oJ14

[

N3en1a

'
SELECT BAUD RATES
FROM TABLE 6

FOR BOTH SLUs

BATTERY
BACKUP SUPPLIED
FOR RAM
MEMORY
NOTE 11

REMOVE RESISTOR
w2

INSTALL RESISTOR
Wi

W1 AND W2

ARE 0 OHM

INSTALL RESISTOR

RESISTORS

REMOVE RESISTOR
W1

SELECT RAM
MEMORY

STARTING ADDRESS
FROM TABLE 7

MAKE SURE

CONFIGURATION
CHART REMAINS
WITH USER'S
MXV1it-B

( FINISH )
NOTE:

REFER TO NOTES

IMMEDIATELY FOLLOWING THIS DIAGRAM,
MA-BBSE

Figure 3-3

Jumper Configuration Flow Diagram (Sheet 4) |

JUMPER CONFIGURATIONS

'FIGURE NOTES
1.

If SLU1 is not selected to be the system console (jumper installed from J62 to J63) the
following features cannot be selected:

Halt on break condition from SLU1 (never available with SLUO)
Reboot on break condition from SLU1 (never availabl e with SLUO)
Console address (773000)
MXV11-B2 ROMs or user ROMs addressed at 773000 and 765000
Software control of the LTC (BEVENT L) (address 777546 does not exist)
Page control register (address 777520 does not exist)
Diagnostic display register (address 777524 does not exist)

A framing error or continuous spacing (break) condition from SLU1 will cause the BHALTL
signal on the bus to be asserted by the MXV11-B causing the system to halt

Aframing error orcontinuous spacing(break) condition from SLU1 willcause the BDCLOL
signal on the bus to be asserted by the MXV11-B and will cause the system to reboot if the
CPU module is configured to do so.

MXV11-B2 ROMs are 8K X 8 UV PROMs and must have access to the page control
register, diagnostic display register, and LTC control register.

User ROMs may be installed and addressed at 773000 and 776500. If more than 256
words are to be used in each address space, page mode must be enabled and addressing
- will be controlled by the page control register.

If control of LTC is selected (jumper installed from J27 to J28) the BEVENT L signal may be

controlled by bit 06 in the LTC control register. If bit 06 is set, the BEVENT L signal on the
bus will be driven by the source (usually by the power supply in Digital systems) allowing
LTC interrupts. If bit 06 is reset, BEVENT L will be held low by the MXV11-B thereby
inhibiting LTC interrupts.

CAUTION: Bit06 isreset on power up. If another control registerisincluded in the system(e.g.,
CPU module) and jumper J27 to J28 is installed, LTC interrupts will never be enabled because
the LTC control register on the MXV11-B will not be accessed to set this bit.
7.

User supplied ROMs are installed and addressed as memory residing in low memory
space.

The MXV11-B may be installed in a Q-22 bus system or a Q-Bus system. If a jumper is not
installed from J36 to J37 the RAM starting address is limited to 64K or below.

The MXV11-B can be configured to be the source of the BEVENT L signal for the system.
Power supplies normally are the source of this signal in Digital systems. Do not have two
sources in a system.
10.

Baud rates for the serial lines may be software controlled or fixed by jumpers. If software
control is desired, both SLUs will have this feature enabled and the fixed jumpers will have
no effect.

11.

Battery backup for the RAM memory and support circuits via pin AV1 on the backplane.

Installing W1 and removing W2 removes normal system +5 V from the memory csrcmts
only. Digital systems do not supply battery backup voltages to the backplane.

JUMPER CONFIGURATIONS

Table 3-1 summarizes all the jumpers on the MXV11-B module in numerical

Table 3-1

Jumperr

Jumper Connections for MXV11-B

Name

Connector for

Function

Connection*

= he b b SR L

order. The jumpers are categorized by function and the connecting type is
denoted by POC for push-on connector or WW for wire-wrap.

SLUO

SLU connectors
e

i
o

SLU1

HALT
GND
RBOOT

J3
J4
J5
J6
J7

Halt and reboot functions

POC (W3)

Serial line unit baud rates

OPEN
J1B

J1A

J9 e
J10 e
J11 e

GND
JOB
JOA

J12 e
J13 o

TP2
GND

For engineering use
|

J15 o

OPEN

baud rates

J16 o

GND

Ji8 e

OPEN

J1G e

AL12H

J21 e

+5V

J14 o

J17 e

J20 o

J22 e

SOFT EN

PGL/DIRH

NA12H
LTC COMM

J23 o

50 Hz

J24 e
J25 e

60 Hz
800 Hz

J26 e

OPEN

J28 e

LTC ENOUT

J27 e
*

LTCENIN

POC (W4)

Software programmable

Enables or disables direct

POC (W5)

PROM size and type in

POC (W6)

mode addressing

direct mode addressing

Line time clock frequency

Software control of line

time clock

WW
..

POC (W7)

PQOC = Push-on connector
WW = Wire-wrap

Note: W1 and W2 are 0 ohm resistors associated with battery backup option. Either
one may be inserted but not both. The module is shipped with W2 inserted.

JUMPER CONFIGURATIONS

Table 3-1

Jumper Connections for MXV1 1-B (Cont)

Jumper

Name

Function

J29 e

TP3

For engineering use

- J30 e
J31 e

GND

J32 e

SLUAZ2

J33 ¢

SLUA1

J34 e
J35 o

OPEN

J36 e

GND

J37 e

SM/LG

J38 ¢
J39 o

JU2

J4a0

SLUA3

JLT1

JL2

J43 o

JL3

OPEN

J47 e
J48 e

CLOCK IN
CLOCK OUT

J49 o
J50 o

PROM
1
PROM 2
GND

GND

J52 e
J53 ¢

BSK2

J54 o

AJ13

J56 o

AJ15

J57 o

GND

J58 e
J59 e
J60 ¢

AJ16

AJ18

J61 o
J62 e

GND

J63 o

CONSOLE

J55 o

Direct mode boot and
small or large system

Serial line unit vector

address

BOOT L/PROM H

J45 e
J4g e

J51

address

JU1

J42 e

J44 o

- Serial line unit starting

DIR MODE BOOT

GND

J41

Connection®

BSK1

Boot ROM or user ROM

Master clock

PROM size and PROM

start address

POC (W9)

POC (W10)

wWw

AJ14

RAM starting address

WwW

Console mode

POC (W8)

AJ17

OPEN

POC = Push-on connector
WW = Wire-wrap

Note:

W1 and W2 are 0 ohm resistors associated

one may be inserted but not both.
The modu

with battery backup option. Either
le is shipped with W2 inserted.

JUMPER CONFIGURATIONS

Table 3-2 contains the following jumper configurations.

Console mode

Reboot

MXV11-B2 Boot ROM set

Line time clock

System size

EVENT line

Boot and diagnostic ROMs

Software programmed baud rates

Clock

Battery backup

Halt

User-supplied ROMs

Table 3-2
NOTE:

Miscellaneous Jumper Configurations

MXV11-B is shipped with jumpers disconnected unless otherwise specified.

Connector

Connection

Description
Enables console mode. SLU1
is fixed at address 777560

J63 ¢

CONSOLE

J62 ¢

GND to OPEN

GND

J61 ¢

OPEN

(J62 to J61)

and vector address at 60.

Select SLU 0 Address from

Table 3-5 and vector from

Table 3-6.

J63 ¢
J62 ¢

CONSOLE
GND

J61 e

OPEN

CONSOLE to GND
(J63 to J62)

Disables console mode. For
SLU addresses, refer to

Table 3-5 and vectors from
Table 3-6.

J46 ¢
Jds ¢

OPEN
GND

BOOT L/PROM H
to GND

J44 »

BOOTL/PROMH

(J44 to J45)

Inserted when MXV11-B2
Boot ROM set is installed in
sockets XE19 and XE28.

Enables the following
registers to be addressed
if the console GND to OPEN
jumper (J62 to J61) is

installed:
Page control register
Line time clock control

Diagnostic display register.

J46 o

OPEN

J45 e
J44 «

GND
BOOTL/PROMH

GND to OPEN
(J45 to J46)

J37 ¢
J36 e
J35 ¢

SM/LGSYS
GND
OPEN

Inserted when ROMs are for
user code (not bootstrap
code). See Table 3-3 for
addresses.

SM/LG SYS to
GND
(J37 to J36)

Instalied when the MXV11-B
is connected in a Q22 bus
backplane. Recognizes BDAL
<21:00> L. This jumper must
be installed if RAM is
addressed above 128K words.

JUMPER CONFIGURATIONS

Table 3-2

Miscellaneous Jumper Configurations (Cont)

Connector

Connection

Description

J37 ¢

SM/LG SYS

J36 ¢

GND

J35 ¢

OPEN

GND to OPEN
(J36 to J35)

Instalied when the MXV11-B
is connected to a 16-bit or
18-bit Q-bus. Recognizes
BDAL <17:00> L only.

J36 ¢

GND

J35 ¢«

OPEN

DIR MODE BOOT
to OPEN

DIRECT MODE

(J34 to J35)

J34 ¢

BOOT

J36 e

GND

J35 ¢

OPEN

J34 ¢

DIRECT MODE

Module not wired for direct
mode boot.

‘

DIR MODE BOOT
to GND
(J34 to J36)

BOOT

Module enabled for direct
mode boot. This jumper must
be installed when the user
boot ROM is directly

addressed.
J18 ¢«
J17 ¢

OPEN

PGL/DIRH

Ji6 e

PG L/DIRH to
GND

GND

(J17 to J16)
|

Ji8 ¢

OPEN

Ji7e

PGL/DIRH

Ji6e

PG L/DIRH
to OPEN

GND

(J17 to J18)

Enables ROM boot map option
and page mode on the

MXV11-B. Disables user
PROM addresses below 16K.

Enables PROM sockets XE19
and XE28 to be used for user

defined PROMs. In this case,
these sockets can only be

addressed in memory
locations below the 16K word
boundary.

J4d8 e

CLOCKOUT

J47 ¢«

CLOCK IN

CLOCKOUT to

CLOCK IN

(J48 to J47)

Factory test. Do not remove.
This is the master clock, and

provides on-board refresh and

the charge pump to generate
-12 V.

HALT

Jé

GND

RBOOT

OPEN

HALT to GND
(J3 to J4)

Enables SLU 1 (console port)
to halt the processor upon
receiving a break character.

HALT

OPEN

GND

RBOOT

Jé

¢«

HALT

'GND

NOTE: HALT to GND (J3 to J4) and RBOOT to GND (J5 to J4)
cannot be
simuiltaneously jumpered.

RBOOT
OPEN

NOTE:

HALT not con-

Disables CPU halt function.

nected to GND

RBOOT to GND

Causes a system reboot when
a break condition is received
from SLU 1. Forces BDC OK-H
iow on the bus.

HALT to GND (J3 to J4) and RBOOT to GND (J5 to J4) cannot be simultaneously

jumpered.

A,
e
s so %

JUMPER CONFIGURATIONS

Table 3-2 Miscellaneous Jumper Configurations (Cont)

Connector

J3 o
J4

J5
J6

¢
¢

HALT

GND

RBOOT
OPEN

Connection

Description

GND to OPEN

Disables reboot function.

(J4 to J3)

CAUTION: LTCENINto LTC EN OUT (J27 to J28) should not be connected if the CPU

has an LTC control register.

LTCENINtO

Allows LTC to be software

LTCENOUT
(J27 to J28)

of BEVENT L on the bus via

J26 ¢
J27 e
J28 e

OPEN
LTCENIN
LTC EN OUT

J26
J27
J28 e

OPEN
LTCENIN

Prevents bit 06 of the LTC

LTCENOUT

LTCENIN
to OPEN
(J27 to J26)

J22 e
J23 e

LTC COMM
50 Hz

LTC COMM to
50 Hz
(J22 to J23)

When installed, the BEVENT
line is driven from a 50 Hz
crystal derived clock. If the

controlled. Enables control

bit 06 of the LTC register.
When bit 6 of LTC register is
0, BEVENT L will be asserted
constantly low. This inhibits
LTC interrupts. To address
the LTC register (777546),
the MXV11-B must be in boot
mode (BOOT L/PROM H to
GND) (J44 to J45) and SLU1must be the console port
(CONSOLE to GRD removed).
register from controlling the
BEVENT L line.

line time clock jumper is
installed, the clamp has to

be turned off by the software

for the clock to drive the
BEVENT line.
J24 o

60 Hz

LTC COMM to

60 Hz

(J22 to J24)

When installed, the BEVENT
line is driven from a 60 Hz
crystal derived clock. If the
line time clock jumper is
installed, the clamp has to

be turned off by the software
for the clock to drive the
BEVENT line.

J25 e

800 Hz

LTC COMM to
800 Hz
(J22 to J25)

When installed, the BEVENT

line is driven from a 800 Hz
- crystal derived clock. If the
line time clock jumper is
installed, the clamp has to

be turned off by the software

for the clock to drive the
BEVENT line.

NOTE: One of these jumpers (50, 60, or 800 Hz) should be installed: 1) If no external
BEVENT source is provided in the system, and 2) If the user desires this source. Power
supplies manufactured by Digital normally supply BEVENT L to the backplane.

.
“

T
Y

‘G

Table 3-2

Miscellaneoy

Connector
Ji5 ¢
J14 ¢

J13e

OPEN
SOFT EN

GND

s Jumper 00nf

igumt§ons (C

ont)

Connection
SOFTEN to

(J14 to J1 3)

Description
GND

Enables Soft

ware
ile bayg ra

Programmab

tes for
g SLUO via th
e

both SLU1 an

JiS e

Jid o

Ji3 e

oOpeN

gOFT EN

GND

CSR. The ba
ud rate jumper
s in
Table 3-5 haye
no effect if th
e
PBRE
bit is set.

SOFT EN to

(J14 to J15)

OPEN

e selected fr

)

connected

- W1(0ohm resi
stor

“

Baud rates ar

Table 3-5,

Battery backu
+5
p8. js

Supplied by

pin AV1. DE

user on back

C does not

battery backup

W2 (0 ohm re

sistor)

Connected

J21 e
J20 e

J1G e
|

L5y
NA1DH

BA12H

NA12H to +5
v
(Normalizeg

address 12)

(J20 to u21)

plane

supply

No battery ba

ckup.

Specifies 2K
user UVROMs
(2716) instal
led ang direct
mode addres
sing,

(Buffered Addr

line 12)

J2t e
J20 e
Ji19 e

5y
Na1oH

BatOH

ess

NA12H to BA
12H
(J20 to u19)

Specifies 4K
or 8K
USer-supplie
d ROM in di
rect
mode addres
sing.

NOTE: Ther
e are cases
where none
of these Jjum
be connecteg.
pers (+5 V. NA
In these case
12H, ang BA
s, the push-o
12H) should
n connector
must pe comp
letely remove
q or

JUMPER CONFIGURATIONS

Tables 3-3 through 3-9 contain the following jumper configurations.
PROM starting address

Table 3-3
Table 3-4

SLU baud rates

SLU starting address
SLU vector address
RAM starting address
PROM address mode jumpers

Table 3-5
Table 3-6
Table 3-7
Table 3-8

PROM size

Table 3-9
Table 3-10
Table 3-11

PROM size in user mode

PROM size in boot mode (page addressing)
PROM size in boot mode (direct addressing)

Table 3-12

Table 3-3 Jumpers for PROM Starting Address

J51
J52
J53

»
*
e

GND
BSK1
BSK2

BSK2 to

BSK1 to

User PROM

(J53 to J51)

(J52 to J51)

(See Note)

R
|
R
|

000000*
020000
040000
060000

GND
R
R
|
|

GND

Starting Address (octal)

R = jumper removed

| = jumper inserted to ground
These addresses are for user supplied ROMs only.

Jumpers BOOT L/PROMH to

ed.
GND (J44 to J45) and PG L/DIR H to GND (J17 to J1 6) must be remov
notin
* Shipped configuration. Remove all jumpers from BSK1 (J52) and BSK2 (J53) if
Note:

user mode.

JUMPER CONFIGURATIONS

Table 3-4

Serial Line Unit Baud Rates

SLUO (See Note)

JOB to

JOA to

GND
J11

J0B

J10 e

JOB

GND

(J10 to J9)

GND

(J11 to J9)

Baud Rates

300*

1200

9600
~

38.4K

SLU1 (See Note)
JiA to
o

Jg
J8
J7

e
o
e

GND
J1A
J1B

JiB to

GND

(J8 to J9)

J7 to J9)
|

R
R

'
R
|

Baud Rates
|
9600"
38.4K

300

1200

R = jumper removed
I

= jumper inserted to ground

Note: SOFT EN to GND jumper (J14 to J13) must be removed; otherwise
these
jumpers have no effect. If the SOFTEN to GND jumper(J14 toJ13)isin
stalled and
PBRE bit 1 is set, baud rates are software controlled.

Shipped configuration

Table 3-5

Serial Line Unit Starting Address Jumpers
,a:

SLUA3
to GND

1 J33 ¢

J32 ¢

SLUAT

(J30 to

SLUA2

(

J31)

SLUA2

SLU1

to GND

Starting

SLU1

(432 to

(J33 to

Address

(See

J31)

SLUO

Note)

776500°

776510"

776510

776520

- 776530

776530

776540

776550

776560

776570

776600

H
.
i,
i

L
3
.

R= iu‘mpar removed

i
-

= jumper inserted to ground

Note:
~

If the GND to OPEN jumper (J62 to J61) is installed (console enabled), the SLU1

address is fixed at the standard console address of 777560 and this column does not

apply.

4
Yo,

Shipped configuration
3
w.

JUMPER CONFIGURATIONS

Table 3-6 Jumpers for SLU Vector Addresses

Jut

Ji3

Ja3e
Ja2 e

JL3 | (3910
JL2 | ,40)

(J3Bto
J40)

(JA3to
J40)

(J42t0
J40)

(See
(J41to
SLUO Note)
J40)

Jag e
J39 e
J3g e

GND | g
JUZ g
JUT g

R
R
R

2
R
R

R
R
|

R
|
R

Jat e

toGND

R
R
R
R
R
R
R
R
R
R
R
R
R
|
|
|
|
|
|
s
|
|
|
|
|
|
|
|
|

toGND

R
R
R
R
R
|
l
|
|
|
|
|
I
R
R
R
R
R
R
R
R
|
u
l
|
|
|
|
l

toGND

toGND

|
R
R
|
l
R
R
l
I
R
R
s
|
R
R
|
l
R
R
|
v
R
R
1
a
R
R
|
z

toGND

|
R
|
R
|
R
|
R
|
R
|
R
|
R
a
R
|
R
|
R
|
R
|
R
|
R
|
R
|

SLU1

300° 310"
010 020
030
020
030
040
050
060
070
100
110
120
130
140
150
160
170
200
210
220
230
240
250
260
270
300
310
320
330
340
350
360
370

040
050
060
070
100
110
120
130
140
150
160
170
200 210
220
230
240
250
260
270
300
310
320
330
340
350
360
370
Undefined

jumper inserted from specified pin to ground. Where muitiple connections are
made, they are daisy-chained.

R= jumper removed

Note: If the GND to OPEN jumper (J62 to J61) is installed (console enabled), SLU1

vector address is fixed at 60 and this column does not apply.
* Shipped configuration

JUMPER CONFIGURATIONS

Table 3-7

RAM Starting Address Jumpers

AJ18

AJ17

AJ16

AJI5

AJ14

1 JB0 o

AJ1S8

toGND

to GND

to GNC to GND

Starting

J59 ¢

AJ17

(J59to
J57)

(JS6to

(JS55t0

(J54to

Address

AJ16
GND
AJI5
AJ14
AJ13

J57)

(Words)

|00
|01
|02

(J60to
J57)
'
R
R
R

(J58to

J58
J57
J56
J55
J54

R
R
R

R
R
|

R
|
R

12K

16K

20K

06
07

R
R

|
l

a
|

R
7

24K
28K

32K

36K

12"

40K

44K

48K

52K

56K

60K

20
21
22

R
R
R

z
I’
|

R
R
R

R
R
|

R
I
R

64K
68K+t
72Kt

23
24

R
R

l
|

R
R

R
|

a
R

|
R

76K+
80K+

25
26
27

R
R
R

r
n
l

R
R
R

z
!
s

R
l
z

|
R
|

88K+

30
31
32
33
34
35
36
37
40
a1
42
43
44
45
46
47

|
:
I
l
|
|
t
x
R
R
R
R
R
R
R
R

I
r
i
s
l
r
:
|
R
R
R
R
R
R
R
R

R
R
R
R
s
s
r
n
R
R
R
R
|
1
t
|

R
R
l
n
R
R
1
a
R
R
s
|
R
R
i
|

R
n
R
|
R
|
R
s
R
l
R
n
R
l
R
:

96Kt
100Kt

50
51
52
53

|
|
|
|

R
R
R
R

l
n
l
I

R
R
R
R

R
R
|
I

R
|
R
|

160K+
164Kt
168K+
172K

¢
¢«
¢
¢«
o

AJ13

RAM

0*
8K

84Kt
92K+

104Kt
108Kt
112K¢
116K+t
120K+t
124Kt
128Kt
132Kt
136Kt
140Kt
144K+t
148Kt
152K+t
156Kt

jumper inserted from designated pin to GND. Where multiple connections are

R =

jumper removed.

made, they are daisy-chained.

* Shipped configuration

t To use address above 64K words, SM/LG SYS TO GND jumper (J37 to J36) must be
installed

JUMPER CONFIGURATIONS

Table 3-7

RAM Starting Address Jumpers (Cont)
CAJ18

AJ17

AJ16

AJ15

AJ14

toGND

AJI3

toGND

RAM

toGND

to GND

(J60to

to GND

(J59to

Starting

(J58to

(J56to

J57)

(J55tc

J57)

(JS4to

J57)

Address

JS7)

J57)

JS7)

(Words)

toGND

176Kt

180K+t

184K+

188K+

61
62

|
|

1
[

R
R

63
64

|
|

R
|

|
I

|
R

192K+
196K+
200Kt

65
66

n
|

n
R
R
l
|

|
R
|
R
I

220Kt
224K+
228Kt

204K+
208Kt

212Kt
216Kt

71|

232K+

236Kt

240Kt

244K+

248K+

252K+

I=jumper inserted from designated pin to GND. Where multiple connections are
made, they are daisy-chained.

jumper removed.

* Shipped configuration
T To use address above 64K words, SM/LG SYS TO GND jumper (J37 to J36) must be

installed

NOTE: Be careful when configuring the MXV11-B RAM when ROM is used in the USER
ROM address space. USER ROM address space is defined as bus addresses 0-16K,
(00000-100000) on 4K boundaries. The RAM start address must be higher than the last
location of the ROM or dual responses from both the RAM and ROM will occur. The

chart below shows several examples of right and wrong ways of assigning RAM memory

start addresses.

+ L

ROM

RAM

Size

Start

End

Comments

8K
8K
4K

OK
4K

4K
OK

68K
64K

Wrong, 4K overiap (4K—8K)
Wrong, 8K overlap (4K—12K)

68K

Right, no overlap

12K

76K

Right, no overlapt

12K

76K

Right

1 Address space gap usually not recommended but up to user to decide depending on

application.

JUMPER CONFIGURATIO

Table 3-8

PROM Jumpers
NA12H to

J1S e«

BA12H

J20 ¢

NA12H

J21 e

NA12H

BA12H

to+5V

| (J20to J1 9)

45V

R
]

(J20 to J21)

Description

‘
- Page mode - Boot ROM for

2K by 8 non-UV PROMs,

]

by 8 or 8K by 8 PROMs

Direct mode - for 2K by 8,

non-UV PROMs, 4K by 8,
&

8K by 8 PROMs.*
Direct mode - for 2K by 8
UV PROMs.
|

or |

R = jumper rémoved

Shipped configuration

jumper inserted

Table 3-9

Jumpers to Configure PROM

PROM 2
To GND

J51

GND

JS50

J49

PROM?2

¢«

PROM1/|R

(J50 to J51)

Size

PROM 1
To GND

(J49 to J51)

PROM Size

No ROMs*
2K by 8
4K by 8

8K by 8%

R = jumper removed

= jumper inserted

* Shipped configuration. Addit
ional
mode and direct addressi

jumpers are required dependin

ng page addressing. Refer

1 If the MXV11-B2 Boot Diag

nostic ROM set is installed,

GND jumper (J50 to J49 to J51).

g on user mode/boot

to Tables 3-10, 3-11, and

3-12.

install PROM 2 to PROM 1

******

(O 4 N

Boow

JUMPER CONFIGURATIONS

3.2

JUMPER CONFIGURATIONS

The MXV11-B module is shipped with jumpers connected in the default condition listed below. The default configuration generally has no jumpers installed,

and push-on connectors are connected to the open pins.

SLUO
Address

776500

Vector

300

Baud rate

300

SLU 1
Address

777560

Vector

Baud rate

9600

Halt on Break from SLU 1 - enabled
Reboot on Break from SLU 1 - disabled

Line time clock (LTC) control register address 777546 - disabled.
Page control register (PCR) address 777520 - disabled.
Diagnostic display register address 777524 - disabled.
ROM size - no ROMs
ROM starting address - 000000

BEVENT L - not driven by this module

Q-22 Bus or Q-bus - Q-bus enabled
Software controlled baud rates for SLU 1 and SLU 0 - disabled
RAM starting address - 000000

The following jumpers use push-on connectors and are listed in the configuration in which they are shipped from the factory. All other jumpers_are wirewrapped.

* CLK IN to CLK OUT - J47 to J48 (W10) - master clock, —12 V and onboard refresh

e GND to OPEN - J45 to J46 (W9) - user mode
e PG L/DIR H to OPEN - J17 to J18 (W5) - page mode disabled

¢ SOFT EN to OPEN - J14 to J15 (W4) - baud rates under hardware control

JUMPER CONFIGURATIONS

* RBOOT to OPEN - J5
to

J6 (W3) - no boot or halt

* LTC EN IN to OPEN J27

to J26 (W7) - no line time

B does not control BEVENT.

* BA12H to NA12H - J19

e address 12 supplied to

8 ROMs).

* GND to OPEN - J62 to J61 (W8) - SLU

Figure 3-3 is a flow aiagram

clock clamp; MXV11-

to 20 (W6) - direct mod

ROM sockets (4K by 8, 8K by

on break

1 acts as System console port
/

which provides a detailed math

odfif configuring
~“the jumpers on the MXV11-B
module for the user's specific
application.
Asterisks on the
diagram indicate the jumper
configuration of the module
when
it is shipped from the factory.
Sometimes, the flow diagram
refers to tables in
this chapter whic
h indicate the shipped configur

certain jumpers must not be

ation. It is important to note

connected for specific func

that

tions.

The flow diagram contains para

graph references. These refe

reader to additional informat

ion. The diagram includes

rences point the

a series of numbers in

parenthesis and preceded
by the word *'note.” These
numbers refer to a set of
notes immediately followin
g the diagram. The notes prov
ide further information.

3.3

ROM CONFIGURATIONS

The MXV11-B contains two 28-p
can support 2K by 8, 4K

in sockets to house the ROM

by 8, or 8K by

code, diagnostic code, or

user code.

s. The sockets
8 ROMs which may contain boot
strap

The 2K by 8 and 4K by 8 PRO
MSs each contain 24 pins

contains 28 pins. Figure 3-4

INTEL 2716: PIN CONFIGURATION
2K BY 8 ROM

Figure 3-4

while the 8K by 8 PROM

shows the Intel configuratio
n for each

INTEL 2732A PIN CONFIGURATION
4K BY 8 ROM

size PROM.

INTEL 2764 PIN CONFIGURAT

ION

8K BY 8 ROM

Ve [J1 A 28 V..
A2

27[JPGm

26 JNC

Hal

25/

As[]5

2[JA,

ALLl6

23“ 11

Al)7
A.C]8

A.Oe

Ao[ho

o.On
0.0
O.[313

GND[J14

227G
210 A

200)CE

1910,

1870
170J0
16[J0
«

15[30,
MA-0381-82

PROM Chips

JUMPER CONFIGURATIONS

Use this configuration or equivalent. For example, the Intel 2716 PROM chipis a
2K by 8 UVPROM. A similar PROM chip, compatible with the 2716, may be used

as a 2K by 8 PROM.

NOTE:

The MXV11-B supports INTEL 2716, 2732, 2732A, 2764 UVPROMS.

When you install a 2K by 8 or 4K by 8 PROM in the 28-pin PROM sockets (XE28
for low byte or XE19 for high byte), you must install the 24-pin PROM in the
28-pin socket with the notch on top, pin side down, and bottom justified. This
means you insert pin 1 of the PROM chip in pin 3 of the PROM socket (Figure
3-5).

For the 28-pin PROM chip, pin 1 of the chip is plugged into pin 1 of the socket
with the notch on the top and pin side down.

~
NS

O
=

Y ©

OO0 ~D U H WA ~

28 PIN PROM SOCKET

Ma-0307.82

Figure 3-5

3.3.1

Insertion of 24-Pin PROM Chips

User Mode (Direct Addressing)

Table 3-10 shows the jumper connections for the various PROM sizes in user
mode. The MXV11-B module must be configured for no PROMs if PROMs are
not inserted in the sockets.

Table 3-1 summarizes all the jumpers on the module. Blank lines sébarate the

jumpers functionally.

NOTE: Page mapping is not available in user mode.

3.3.2

Boot Mode (Page Addressing)

Table 3-11 shows the jumper connections for the various PROM sizes in boot
mode using page mode addressing. The MXV11-B module must be configured

k
R
e
Bl

P
.

ggfy
E ]

*ge

Ea s

for no PROMs if PROMs are not inserted in the sockets.

JUMPER CONFIGURATIONS

Table 3-10

Jumper Connections for PROM Sizes in User Mode

J16 o

(GND)

J17 o

(PG L/DIR H)

JiB e

(OPEN)

J19 ¢
J20 o

(NA12H)

J21 e

(+5V)

(BA12H)

J44 o

(BOOT L/PROM H)

J4s e

(GND)

J46 o

(OPEN)

J49 e

(PROM1)

J50 e
J51 o

(PROM2)

Note:

NoPROMs

2Kby8

JI7t0J18

J1710J18

J17t0J18

J1710J18

J1910J20

J20toJ21

J19t0.120

J19to J20

JAE10J46

JA510J46

JAS10J46

J45 to J46

J49t0JS1

J50toJ51

J49 to J50

4K by 8

8K by 8

to J51

(GND)

Jumper connections are indicated. For example, in the
2K by 8 PROM, J17 is

connected to J18, J20 is connected to J21, J45 is connecte

d to J46, and J49 is connect-

ed to J51.

Table 3-11

Jumper Connections for PROM Sizes in Boot Mode (Page Addressi

J16 «

(GND)

J17 ¢

(PG L/DIRH)

J18 «

(OPEN)

J19 ¢
J20 ¢
J21 ¢

(NA12H)

(BA12H)

ng)

NoPROMs

2Kby8°

4KbyS

8K by 8

JI7t0J18

J1610J17

J16t0J17

J1910J20

J19t0J20

J4410J45

Jad to J45

J19t0 J20

(+5V)

J44 o

(BOOTL/PROMH) | J45t0J46

J45 ¢

(GND)

J46 *

(OPEN)

J49 ¢

(PROM1)

J50 *

(PROM2)

J51 ¢

(GND)

;

J4d10J45

¢
-

J4910J51

”

J50t0J51

J49to J50

to J51

2K by 8 UV PROM cannot be used in page mode.

Note: Jumper comections are indicated. For example, in the 8K by 8 PROM, J16 is

connected to J17, J18 is connected to J20, J44 is connected to J45 and J49, J50 and J51

are connected.

JUMPER CONFIGURATIONS

3.3.3 Boot Mode (Direct Addressing)

Table 3-12 lists the jumper connections for the various PROM sizes in boot
mode using direct addressing. The MXV11-B module must be configured for no
PROMs if PROMs are not inserted in the sockets.
3.4 SLU CONFIGURATIONS

If you want to use one of the SLUs as a console, you must connect the console
terminal to SLU 1 since the halt on break, reboot on break, console address,
and vector functions are only selectable for use with SLU 1. To halt on break the
HALT to GND jumper must be connected. When connected, the CPU halts on a
break from the SLU. The break could be the result of a framing error or an operator request. To reboot on a break condition, connect the RBOOT to GND
jumper.

in console mode, the SLU 1 address is fixed at 777560 and the SLU 1 vector
address is fixed at 60. The SLU 0 address is selected from Table 3-5 and the
SLU 0 vector is selected from Table 3-6.

Table 3-12 Jumper Connections for PROM Sizes in Boot Mode (Direct Addra&aifig)
NoPROMs

2Kby8

4K by 8

8K by 8

J17 to J18

J19t0 J20

J20 to J21

J19 to J20

J19to J20

‘JM e (BOOTL/PROMH) | J45t0 J46

J44 to J45

J49 to J51

J50 to J51

J49 to J50
to J51

J16 ¢ (GND)

J17 »
J18 ¢

(PG L/DIR H)

(OPEN)

Ji19 « (BA12H)
J20 ¢
J21 e

J45 ¢
J46 o

(NA12H)
(45V)

(GND)
(OPEN)

J4g e (PROM1)
J50 ¢ (PROM2)

J34 ¢ (DIR MODE BOOT)

J51 ¢

J35 ¢
J36 ¢

(GND)

(OPEN)
(GND)

J3410J36

J3410J36 ~ 7 J34 10 J36

e, in the 2K by 8 PROM, J17 is
Note: Jumper connections are indicated. For exampl
connected to J18, J20 is connected to J21, J44 is connected to J45, J49 is connected to
J51, and J34 is connected to J36.

JUMPER CONFIGURATIONS

With the SOFT EN to OPEN jumper (J14 to J15) connect
hardware controlled (strapped) by inputs to the DLART

ed, the baud rates are

(Table 3-4). If the SOFT

EN to GND jumper (J14 to J13) is connected, the baud

rate selection from Table

To use software controlled baud rates, software must

write the XCSR register

3-4 is disabled and software controlled baud rates for both SLUs

are enabled.

of the desired SLU in the following manner. First, the program
enable bit (PBRE-bit 1 of XCSR) must be set. If this bit is not

mable baud rate

set, the fixed hard-

ware inputs will control the baud rates. Second, the
programmable baud rate
bits (bits PBR 2, 1, and 0 in the XCSR) must be set in the
proper configuration
for the desired baud rates (Paragraph 2.6.4).

If SLU 1 is selected for console mode, it uses the hardwar
e inputs to select the
baud rates. Since the SOFT EN to GND jumper (J14 to J13)
enables software
baud rates for both SLUs, PBRE bit 1 in the XCSR of SLU 1
must
be reset. It is

possible to have SLU 0 operate with software controlied

inputs by setting the
PBRE bit in the SLU 0 XCSRtoa 1 and configuring the PBR bits
in that XCSR to

the desired baud rate.

NOTE: If a power-down or power-up bus reset or initialize occurs,
the XCSR
registers are cleared and the baud rate is reset to 300 baud.
So it is necessary
to reset the bits in the XCSR registers to the previous configura
tion.

3.5 LINE TIME CLOCK CONTROL

Line time clock (LTC) interrupts can be enabled or disabled by the
LTC IN and
LTC OUT jumpers and by the state of bit 6 of the LTC control register.
If the LTC EN IN to LTC EN OUT jumper (J27 to J28) is connected,
BEVENT L is
asserted constantly low on the bus provided bit 06 of the LTC control
register is
reset. This disables LTC interrupts in the system. When bit 06 is set,
BEVENT L
(if selected as the source) is allowed to be driven by the MXV11-B at
a frequency of 50, 60, or 800 Hz. Digital power supplies and backplanes normally supply

a line time clock for the system. Do not have two sources in the system.

To address the LTC control register, the BOOT L/PROM H to GND jumper (J44

to J45) and the GND to OPEN jumper (J62 to J61) must be connected. If
the
- BOOT L/PROM H to OPEN jumper (J44 to J46) is connected or the CONSOLE

to GND (J63 to J62) jumper is connected, the LTC CSR cannot be accessed

the system.

If the LTC EN IN to OPEN jumper (J27 to J26) is connected, BEVENT L is not

controlled by the LTC register.

3.6

LTC FREQUENCY

The LTC can be selected to operate at 50, 60, or 800 Hz by driving the BEVENT
L line at the desired frequency (refer to Table 3-2).

MAINTENANCE AND DIAGNOSTICS

4.1

GENERAL

This chapter describes the maintenance and diagnostic for the MXV11-B mod-

ule. The MXV11-B CVMX BAO diagnostic tests the module. It verifies:

Operation of the two serial line units
Read only memory option (ROM)

Clock option

Page control register (PCR)
Diagnostic display register (DDR)
Random access memory (RAM).
The diagnostic runs on any Q-bus PDP-11 with 16K words of memory. It runs

under XXDP+ and APT monitors and on processors with no hardware switch
register.

NOTE:

CPUs without memory management (LS! or LSI/2) cannot test all of the
MXV11-B’s memory. These systems can only verify/test the lower 32K words

(actually 32K words minus the I/O page, i.e., lower 28K). CPUs with memory
management can check up to two MXV11-B modules minus the 1/0 page, i.e.,

124K words.

The program tests whatever options the device map ($DEVM) is set to, prints
the contents of the device map for operator verification, and also prints a sum-

mary of significant differences from the default conditions. For example, differ-

ences might be channel(s) dropped from testing, using channel 1 as console, or
bypassing ROM and RAM testing.
4.2

DATA TESTING

Data testing of the DLART is done by internal wrap. This checks out'the DLART
only and not the complete functionality of the SLU. To check out the SLU, external wraparound connectors are required so that the receiver and transmitter

chips may be tested.

4.3

SERIAL LINE UNIT TESTING

Serial line unit testing is done in two distinct phases:
1. Each of the two MXV11-B channels is tested individually.

2. The MXV11-B module is tested as a whole for channel interaction problems. This diagnostic is designed to test and detect errors to the logic level
and not the chip level.
59

MAINTENANCE AND DIAGNOSTICS

The addresses and vector ranges are as follows.

Channel 0

776500-776570

Channel1

776510-776600

Vectors

004-376

PCR

777520

DDR

777524

LTC

777546

777560 (as console)

The default addresses and vectdrs are as follows.
Channel 0
Channel 1

776500-776506
. 777560-777566

Vectors 300/304

Vectors 60/64

For any other device addresses the operator must change the default locations.

(See program options and defaults in Paragraph 4.4.)
4.4

PROGRAM OPTIONS AND DEFAULTS

The MXV11-B diagnostic needs the address of the first RCSR of each SLU and
its interrupt vectors to be previously stored unless the default address and vec-

tor is. desired.

NOTE:

The test can be run with one MXV11-B in which case channels 0 and 1

apply; or it can be run with two MXV'11-Bs and channels 0-3 apply.

Diagnostic

" Channel0
- One

Location

Address/Vector

1254

776500

RCSR 1

- 1256

300

Vector

1260

777560

1262

1264

776510

1270

776520

1272

320

MXV11-B

Channel 1
L

Two

Channel2

1266

310

MXV11-Bs
|

Channel 3

RCSR1

Vector

RCSR 2

Vector

LOROM

1274

773000

Low ROM address

1276

773776 -

High ROM address (256 words)

LOROM2

1300

765000

2nd low ROM address

HIROM2

1302

765776

2nd high ROM address (256 words)

1264

776510

Channel 2

BASE3

1270

776520

Channel 3

VECT3

1272

320

Channel 3

VECT2

;

Vector

HIROM

BASE2
~

RCSR 2

1266

310

Channel 2

MAINTENANCE AND DIAGNOSTICS

Location ‘$DEVM’ (default = 000000) is a bit map that shows which options are

present and to be tested.

The operator is prompted on initial program startup.

"$DEVM’ can be changed anytime by typing Control-G and Control-C. The pro-

gram will resize and restart at the beginning again. The $DEVM can be

location 1252.

found at

Each bit of the device map ($DEVM) is briefly described below.
Bit 15

0 =test channel 0

= default

1 = bypass channel 0 test

= 100000

Bit 14
Not used

Bit 13

0 =test 1 MXV11-B module

= default

1 =test 2 MXV11-B modules

= 020000

Bit 12

0 = CPU has memory management

= default

1=CPU has no MEM MNGT (LSI11/2)

= 10000

Bit 11
|
0 = break detection disabled

= default

1 = break detection enabled

= 4000

NOTE:

Break detection is tested on channel 0 only.

Bit 10

0 = do data wraparound tests

= default

1 = bypass data wrap tests

= 2000

Bit9

0 = do data wrap external tests

= default

1 = bypass wrap internal tests

= 1000

NOTE:

This bit selection is only used if data wrap has already been selected

via bit 10 or 3.

Bit 8

0 = bypass channel 1 test

= default

1 =test channel 1

= 400

Bit 7

0 = enable PCR register test

= default

1 = bypass PCR register test

=200

MAINTENANCE AND DIAGNOSTICS

4.5

EXECUTION TIMES

Execution times for an LSI-11 processor with the MXV11-B module at shipment

configuration are listed below.

F-11

LSI-11

(LSI-11/23)

First pass

17 sec

08 sec

with one MXV11-B

Additional passes

45 sec

23 sec

with one MXV11-B

Channel 0

at 300 baud

Channel 1 (console)

;

at 9600 baud

The test time is baud rate dependent hcgher baud rates result in shorter pass

times.

The RAM tests require the. additional times shown below for all passes.
LSI-11/23

LSI-11

(64K words)

LSI-11/23

(124K words)

1st pass

4 sec

10 sec

19 sec

2nd pass

16 sec

10 sec

33 sec

4.6

POWER FAIL

Auto start from power fail is used in this program. Upon power up, the program
restarts from the beginning.

4.7

ERROR HANDLING

Since this diagnostic was designed to fitin 16K of memory the error typeout IS

very brief. The format of the error typeout is as follows:

Test #

JError #

PC=_____ Address=

Vector=

where all values typed are octal. The address and vector refer to the failing

channel. For further information the listing must be consulted. After an error is
found, bits 15, 13, 10, and 9 of the switch register (SWREG) control the

sequence of events as shown below.

Bit 15 set- makes the program halt in the error routine. If the prwgrarfl is continued, it proceeds from where it halted.

Bit 13 set - disables printing of the error message.

Bit 10 set - rings the bell on error.
Bit 9 set - makes the diagnostic loop from beginning of test to error.

MAINTENANCE AND DIAGNOSTICS

The error routine supports the control G <*G> functio

n. Refer to Paragraph

4.9,

The only halt in this diagnostic is in the error routine
15 of the switch register (SWREG location 176)

, and is executed only if bit
is set when an error occurs.

The error numbers have been updated to reflect

the test they are called from.

Error # 35 = Test 3, error number within the test

is 5:;

For example:

« Error # 237 = Test 23, error number within the test is 7.
NOTE: All tests conform to this format except
test 21. That test numbers its
tests from 1 to 13 (octal).
- 4.8

DEVICE REGISTERS
The MXV11-B device registers and bit formats

4.9

are shown in Appendix A.

SUMMARY OF TESTS AND SPECIAL SUBROUTINES

This paragraph briefly describes the various diagnos

tic tests.

PHASE 1 TESTS
Test 1 - RAM Address Test - writes the entire first 32K

with the address of the
location. It then checks the memory to be sure the write was correct.
If an error

“occurs, and the program has been set up to halt, the failing address
register 0.

is in CPU

This test also checks for the presence of the DDR register.
If the register
“"READ" creates a timeout an error will be generated.

Test 1 has errors 11 (data not = address) and 12 (LEDs not there).
Test 2 - RAM Data and Volatility Test - Write all memory to

pattern).

all 1s (background

1. Test location for correct pattern.

2. Float Os and complement through word.

3. Reset location to all 1s.

Repeat above three steps for each location. When all locations
are tested,
check entire memory for background pattern. Repeat all the above for
back-

ground pattern of all Os and floating 1s. This test uses the memory

management

- option. If a failure occurs examine CPU register R2. This register contains
failing 4K (octal) page number.

the

MAINTENANCE AND DIAGNOSTICS

Test 2 has errors:

21 print “MEM BAD",
22 print “MEM BAD",
23 print *“MEM BAD", and
24 print “MEM BAD".

Test 3 - ROM Tests - This is a two-part test. The first part checks the presence

of addresses X73000-X73776. The second part checks the addresses of
X65000-X65776.

This test also checks for the presence, if SDEVM selected, of the PCR register.

it checks for a write of all 1s to the register. It then
If the register is present then

floats a one through a field of zeros.

”

Test 3 has errors:

31 bad address

32 RAM instead of ROM
33 bad address

34 RAM instead of ROM
35 trap occurred
36 PCR cannot hold all 1s
37 wrong bits appeared

Test 4 - Clock Tests - The clock test, if selected via the $DEVM, simply
enables the clock and checks for an interrupt.

Test 4 has errors:
41 no clock interrupt, and
42 unexpected 2nd clock interrupt

NOTE: The following tests check both SLUs except for the case where the
’
'SLU is used as a console.

Test 5 - Addressability — Verifies that all eight registers of the channel under
test respond to their addresses.
Test 5 has errors:

51 timeout on channel address
52 RCSR has unused bits set
53 RBUF has unused bits set
54 XCSR has unused bits set
*

55 XBUF has unused bits set

Co R Yegod B
R

.‘l;s;

The following three tests test all ‘read write’ bits

MAINTENANCE AND DIAGNOSTICS

Test 6 - Break (BK) - XCSR 0 reset, set, clear, reset
Test 6 has errors:

61 BK remained high

62 BK did not set in XCSR
63 BK did not clear in XCSR
64 BK did not reset in XCSR

Test 7 - Interrupt Enable (IE) - XCSR 6 reset, set, clear, reset
Test 7 has errors:

71 |IE did not reset in XCSR
72 |E did not set in XCSR
73 |IE did not clear in XCSR
74 |E did not reset in XCSR

Test 10 - Interrupt Enable (IE) - RCSR 6 reset, set, clear, reset
Test 10 has errors:

101 |E did not reset in RCSR
102 IE did not set in RCSR

103 IE did not clear in RCSR
104 IE did not reset in RCSR
105 TR not set

Test 11 - Transmitter Ready (TR)- XCSR 7 - clears when TBUFis Ioaded with
a character and checks that it sets a reasonable amount of time.
Test 11 has errors:

111 TR did not set in XCSR
112 TR did not set in XCSR
- 113 TR did not clear in XCSR

Test 12 - Receiver Done (RD) - outputting a character from XBUF (with
wraparound connected) results in RD setting a reasonable amount of time.
Test 12 has errors:

121 RD did not set in RCSR
122 RD did not reset in RCSR

MAINTENANCE AND DIAGNOSTICS

SRR TG

WL
S RY -

citE

Test 13 - Receiver Done (RD) - cleared by reading RBUF.

CSEER

WTTOS

Test 13 has errors:
131 RD did not set in RCSR

132 RD did not clear in RCSR

Test 14 - Overrun (OE) and error bit (ER) - RBUF 14
Test 14 has errors:

141 RD did not set in RCSR’
142 OE did not set in RBUF
143 ER did not set in RBUF
144 Reading RBUF cleared OE

- 145 RD did not set in RCSR
146 OE did not clear in RBUF
147 ER did not clear in RBUF

Test 15 - Transmitter interrupt logic test - checks transmitter interrupt logic by

setting CPU priority to 0 in processor status word with interrupt enable (IE) set.
Test 15 has errors:

151 TR did not set in XCSR

152 interrupt flag did not set

153 XCSR sent second interrupt (unexpected)
154 interrupt flag occurred with IE disabled
Test 16 - Receiver interrupt logic test - covers all of the receiver side of the
interrupt logic in character mode.

Test 16 has errors:
-

161 TR did not set in XCSR
162 interrupt flag did not set
163 RBUF sent second interrupt (unexpected)

164 interrupt flag occurred with IE disabled

Test 17 - Test data wraparound binary count: flag mode.

Test 17 has errors:
171 TR did not set in XCSR

172 RD did not set in XCSR
173 ER bit set in high byte of RBUF

MAINTENANCE AND DIAGNOSTICS

Test 20 - Test data wraparound binary count: interrupt mode.

Test 20 has errors:
201 Hung, no data transfers

202 overrun error (OE)
203 framing error (FE)

204 not used presently

|
205 data compare error (received data did not compare with transmitted)

Test 21 - Test break logic: transmit known character - a) Transmit known

character with break bit set and compare received character with 0. Received
character should be 0. b) Test for framing error on break.

-t b

- O~NOOOL
S WN -

Test 21 has errors:
'RD did not set in RCSR
BK failed to clear in RBUF

RD failed to set

Reset did not clear OE, FE in RBUF
BK error

Framing error (FE)
BK did not set in XCSR
RD did not set in RCSR

CHAR after BK not received correctly

Test 22 - Not a test - send back to loop.
PHASE 2 TESTS

Test 23 - test that channels interrupt at assigned priority

Test 23 has errors:

;

’

231 No RD

232 No RD

233 Did not interrupt at assigned priority
234 Did not interrupt at assigned priority
235 Did not interrupt at assigned priority
~ 236°Did not interrupt at assigned priority

237 DONE failed to set after transmission of word

M‘

éfm’f
M

ey
§r e

G
9

#on

£y

o
F

e
Tr
e

MAINTENANCE AND DIAGNOSTICS

Test 24 - test data transfers with all active lines interrupting.
Test 24 has errors:

241 RD failed to set after transmission of word
242 ER flag after transfer
243 data compare error

244 ER flag up after transfer
245 data compare error

Test 25 - test that channels interrupt at assigned priority. This test is executed
only on the second MXV11-B'module (channels 2 and 3). Any failure is related

to the second MXV11-B board.
Test 25 has errors:

251 No RD
252 No RD

253 did not interrupt at assigned priority
254 did not interrupt at assigned priority
255 did not interrupt at assigned priority

256 did not interrupt at assigned priority
Test 26 - test data transfers with all active lines interrupting. This test is execut-

ed only on the second MXV11-B module (channels 2 and 3). Any failure is relat-

ed to the second MXV11-B board.

Test 26 has errors:
261 RD failed to set after transmit
262 ER flag after transfer

263 data compare error
264 ER flag after transfer
265 data compare error

4.10 SYSTEM REQUIREMENTS
The hardware system requirements are:
o KDF11, KDF11-B, KD11-HA, or KD11-F processors

~* 16K word memory — minimum. A special data wraparound connector (PN
3270-A) is required if data wraparound tests are desired
e |f channel 1 is the console, tests 11-14, 16-21, 23-24 are bypassed
(bypass is for channel 1 only)

* |f data wraparound tests are bypassed, tests 12-14, 16-21, 23-24 are
bypassed.

T
[

yody
gy
c’i@g;flw’i*"‘
S
B
denl
A
ot

MAINTENANCE AND DIAGNOSTICS

The software system requirements are as follows.

This diagnostic can run in the following ways:

{“ with APT monitor
2. with XXDP+ monitor (chainable if renamed to .BIC extension).

This diagnostic is not designed to run with the diagnostic supervisor.
It is assumed the operator must perform the following settings:

1. Set the software switch register (SWR) if not defaulted (Paragraph 4.4).

2. Set the device map ($DEVM) if not defaulted, (Paragraph 4.4).
3. Set the serial line addresses and vectors if not defaulted (Paragraph 4.4).
4. Set the ROM HI and LOW ADDR if not defaulted (Paragraph 4.4).

eB T

If channel 1 is configured as the console and the VT100 is the console device,
“SETUP B must be set for the following:
Disable XON/XOFF

New line OFF

4.11

All other options per system requirements.

ADL R
YSALE
|B
A Lo ‘;;g"\‘.‘f“ffi( PR R

Jump scroil ON

OPERATING INSTRUCTIONS

T
AR i T A
il
L e Na et gFrn
bt
i & Sk M T
{i;"
29

4.11.1 Loading and Starting Procedures
Use standard procedure for PDP-11 absolute binary formatted media.
All normal starts and restarts are from location 200.
There are two starting addresses to be used off-line only for interrupt vector
troubleshooting:

1. 1412 Start - loads addresses 0 to 400 with the address of an interrupt routine that just does RTIs allowing looping in that part of the test where interrupt vector problems are occurring. Normal testing will then begin.

2. 1334 Start - load addresses 0 to 400 with trap catcher code. Any interrupt

[

to this region will halt. Normal testing will then begin.

MAINTENANCE AND DIAGNOSTICS

As soon as testing starts, the operator can change the switch

register only by a
‘BREAK’ and manually loading location 176 (SWREG) with the desired
contents:
then doing a ‘P’ to proceed.

The user can select a specific test to be executed by setting bit 8 in SWREG
the test number (in octal) in bits <7:0>.

NOTES:

and

All tests previous to the selected one are executed without iteration

except test 22 which cannot be looped.

This diagnostic follows the star{ard procedure for running under APT:XXDP+

monitors as described in their respective procedures manual and
SYSMAC

package.
4.12

“

Operational Switch Settings

The software switch register (location 176) is used for all operational switch

tings as follows.

1. Type Control G <" G>. This allows the TTY
at selected points within the program.

set-

to enter data into location 176

2. The machine then types: ‘SWR=XXXXXX NEW=' (XXXXXX is the octal
contents of the software switch register).

3. After the 'NEW="has been typed the operator can do one of the following
atthe TTY:

a. Type a number to be loaded into location 176 followed by a <CR>. (Only

octal numbers from 0 to 7 are accepted.) Leading zeros need not be
typed, and if more than six digits are typed only the last six are used. Ifa
<CR> is the first key pressed the software switch register contents

does not change.

b. If a control U <®U> is pressed, the program sends you back to step 3.

c. If the input character is not one of the characters mentioned .above, a
question mark (?) is typed, followed by a carriage return and a line feed

sequence. Then proceed from step 2 (erasing all previous input).

4. The diagnostic continues running <CR>.
NOTE:

Because of the frequent bus resets in the program, multiple control Gs

may be required. If necessary, 'BREAK’ into the program and load location 176

(SWREG) by ‘ODT’ to the desired contents. Do a P’ to proceed.

MAINTENANCE AND DIAGNOSTICS

Software Switch Register Options (SWREGQG)

Bit 15 set

100000

14 set

40000

Halt on error

Loop on test (to be used only while
~

13 set

20000

12 set

11 set

10 set

testing in progress)

Inhibit error typeouts

10000

Enable performance reports

4000

Inhibit iterations

2000

Bell on error

g set

1000

Loop on error

8 set

400

Loop on test in SWR<7:0>

7:0

Number of test to loop on (used with

bit 8) (all tests previous to the
selected test are executed first with 1
iteration only)

NOTE:

|Ifbit 14, 9, or 8 is selected the LEDs on the MXV11-B module may give

false test number indications. If a test has a UNIBUS reset command, the LEDs

will light fully every pass through the reset instruction. Thus, test 7 appears as

)

;

©f

test 17 (all LEDs on).

e
¥

i«

%
”

PROGRAMMING SUMMARY

A.1

INTRODUCTION

This appendix summarizes programming the MXV11-B regardi
trol register, diagnostic display register, line time clock

ng the page con-

line unit (SLU) registers. Figure A-1 shows the bit assignments
of the MXV11-B
registers. For additional details, refer to Chapter 2.

A.2

PAGE CONTROL REGISTER
The PCR format and bit assignments for the page

control register (PCR) are
shown in Figure A-2. Bits 0-4 point to one of 32 256-word blocks
in ROM (8K
word space). The block pointed to is read through bootstra
p address 773000g.
Bits 8-12 point to 1 of 32 256-word blocks in ROM. The
block pointed to is read

through bootstrap address 765000g.

The PCR resides at location 777520 in the 1/O page, and is

MXV11-B has its console and boot functions enabled.

A.3 DIAGNOSTIC DISPLAY REGISTER
The diagnostic display register (DDR) is a four-bit write-only

enabled when the

correspond to the four register bits shown in Figure A-3. The

DDR resides at

location 777524 in the 1/O page, and is enabled when the MXV11-B

has its console and boot function enabled. At power up, the DDR is cleared and
all LEDs
are lit. The LEDs turn off when a logical one is written into that bit.
A.4 LINE TIME CLOCK REGISTER
|
The line time clock register (address 777546) is a one-bit register (bit 06).

bit 06 is set, the clamp is removed from BEVENT enabling the line time

When

clock
(LTC). The LTC resides at location 777526 in the I/O page and is enabled when

the MXV11-B has its console and boot functions enabled.
A.5

SERIAL LINE UNIT PROGRAMMING

SLU 0 may be assigned to any one of eight starting locations in the 1/O address

space range from 776500 to 776570. SLU 1 is automatically assigned
by the

MXV11-B module to the next higher starting address over SLU 0.
The /O
address assignment for SLU 1 is from 776510 to 776600.

When SLU 1 is assigned the console port, it assumes address 777560. Default
addresses are 776500 for SLU 0 and console port for SLU 1.

APPENDICES

RCSR

UNUSED

RECEIVER

ACTIVE

DONE
INTERRUPT

ENABLE

RBUF

UNUSED

ERROR

FRAMING

ERROR

OVERRUN
ERROR

XCSR

DATA

RECEIVER
BREAK

UNUSED

TRANSMITTER|
READY

PROG.

BAUD

PROG.

BAUD

RATE 2

RATE 0

RATE

ENABLE
INTERRUPT

PROG.

ENABLE

BAUD

MAINTENANCE

BREAK

RATE
1

XBUF

039

UNUSED

PCR

UNUSED

DDR }

DATA

WINDOW #1

UNUSED

WINDOW #0

UNUSED

LEDs

(4)

15
LTC

12
~

UNUSED

ENABLE

CLOCK
MA-QG06-82

MXV11-B Register Bit Formats

waoihy bt R ye,

Figure A-1

APPENDICES

UNUSED

WINDOW #1

UNUSED

WINDOW =0

Ma-D280-82

Page Control Register

Figure A-2

|
MXV118B

MODULE

GREEN LED
(POWER ON}

DIAGNOSTIC DISPLAY REGISTER
DY 14-BT
MA

Figure A-3

MXV11-B Diagnostic Register (LEDs)

A.5.1 Interrupt Vector Selection

Vector address selection covers the vector address space from 010 through
376.

NOTE: Be careful - some addresses aré reserved.

Bits 3-7 of the vector address can be programmed (via wire-wrap) to select
independent vector addresses for each of the SLUs. Bits 0, 1, and 8 are always
0 for the MXV11-B.

APPENDICES

isters for
s. The regow.
for each of 1,theandtwo0, SLU
four registers res
The MXV11-areB has
bel
as shown
addressed via add s bits 2,
,

A.5.2 SLU Registers

both SLUs
status register
Receiver controbufl and
Receiver data troferl and status
Transmitter con
Transmitter data buffer

— base address +0
_ base addresss +28
- base addres +48
- base address +68

les A-1 through

Tab
The bit assignments of each of the registers is described in
A-4.

ESSING
A.6 DIRECT MODE BOOT ADn DR
boot ROMs in direct addressing mode should

ow
mming their are
that
Users progra
rd blocks ide
-wo
256
2
are
re
The
d.
ize
mal
nor
not
ses
res
add
the
t
tha
e
res
realiz essed in the 1/O page on the MXV11-B. One o56-word block s
can be acc-773776 and the other at 765000-765776. The actual PROM location
at 773000 sed depends on the bus address and the PROM size used. Bus
being addresincrement by two while PROM addresses increment by one. For
addresseswith a bus address of 765002 the corresponding PROM address is8
example, 2K by 8 PROM; 2401 for a 4K by 8 PROM, and 12401 for an 8K by
2401 for a
|
ow).
PROM (see chart bel
Bus Address

Actual PROM Address

2K X 8

4K % 8

8Kx8

00-12477
0-2777 124
0-2777 240
765000-76577 6 - 240
1400-1777 5400-5777 15400-15777
773000-77377
increment by 2)
nter (bus addPRresOMses
is @ byte poises
Bit 0 of bus address res
s
s addres 2K X 8

(256 words) 6

Bits 1-11 of bus add ress addresses 4K X 8 PROMs
Bits 1-12 of bus add s addresses 8K X 8 PROMs
Bits 1-13 of bus addres

,,,,,

APPENDICES

Table A-1

Receiver Status Register Bit Assignments (RCSR)

Bit

Description

1512

Unused

}-R&ceiver is active (logic 1)

Receiver active read

only

10-8

Unused

Receiver done read

’

SLU has received a character

(logic 1)

only

Enables receiver interrupts

Interrupt enable’

(logic 1)

read/write

Table A-2

Unused

Receiver Data Buffer Bit Assignments (RBUF)
Description

Bit
15

ER
Error read only

Bit 13 and/orbit 14 isa 1
(logic 1)

Word in RBUF not read when another

Overrun error read
only

word was received in RBUF.
(logic 1)

FE
Framing error read

Start bit but no stop bit
(logic 1)

only

Unused

Receiver break read
only

and stays for 11 bit times
(logic 1)

Unused

10-8
7-0

S| signal goes from mark to a space

Data read only

Holds most recent byte
(logic 1)

APPENDICES

Table A-3

Transmitter Status Register Bit Assignments (XCSR)

Bit

Description

15-8

Unused

SLU ready to accept character

Transmitter ready

(logic 1)

read only

ES—— g

Enables transmitter interrupt

Interrupt enable

(logic 1)

read/write

BR2-BR0
Programmable
baud rate select

Determines software programmable
baud rate (when PBR = logic 1).

read/write

MAINT
Maintenance
read/write

Connects serial output to serial input.
External serial input disconnected
(logic 1)

PBR
Programmable baud
rate enable/inhibit

Selects hardware or software baud
rates (logic 1 for software; logic 0
for hardware).

PBR read when
programmable baud

rates enabled (SOFT

to GND jumper); else
-~

Table A-4

read/write

Break
read/write

Causes serial output to go to Space |

condition (logic 1).

Transmitter Data Buffer Bit Assignments (XBUF)

Bit

Description

15-8

Unused
,,,,,

7-0

XMIT DATA BUFFER

read/write

Holds a copy of the most recent byte

written into it. (logic 1)