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Document:	MSV11-C User's Manual
Order Number:	EK-MSV11-OP
Revision:	001
Pages:	44
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OCR Text

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EK-MSV11-OP-001

MSV11-C

user’'s manual

digital equipment corporation - maynard, massachusetts

1st Edition, December 1976

Copyright © 1976 by Digital Equipment Co'rporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment

Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP

RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION @

INTRODUCTION . . . . e
GENERAL DESCRIPTION
SPECIFICATIONS . . . .
Electrical
. . . . . .
- Environmental . ...
Mechanical
. . . . .

1.1
1.2
1.3

1.3.1

1.3.2
1.3.3

2.2

2.2.2
2.2.3

224
2.2.5

2.2.6

1-1
1-1
1-2
1-2
1-3
1-3

. . . . .. . ... ... ..... e
e ee

e e e e

1-3

GENERAL
. . . . .
e e e
e e e
CONFIGURING THE MSV1 l—C
.......................
|
General
. . . . L
e e e e e e e e e e e e e e e e e e e e e e e
Address Selection . . . . . . ...
oo
e e
Refresh Mode Selection . ..
... ... .. e
e e e e e e e e e e

2-1
2-1
2-1
2-1
2-2

e e e e e e e e e ..

- INSTALLATION

CHAPTER 2

2.2.1

e e e e e
e e e e e
e e e e
e e e e e e
e e e
e e e e

REFERENCES

1.4

o e e e e e e e e e e e e e e e e e
...
.. .. .. e
e e e e e e e e
. o
e e e e e e e e e s e
o o e e e e e e e e e e
e e e e e
..............0.0... e
... . .. ... ... e
e e e e

- Backplane Pinning Utfllzatlon

1.3.4

2.1

Battery BackupPower
Bus Grant Continuity
Bank Select Enable

. . . .. ... ... ...............
. . . .. . . . o i i e e
e e e e e e e
. . . . . . . . .

. . .

24
24

e e e e e e e

...................

2-4

2.3

INSTALLING THE MSV1 l—C MODULE

CHAPTER 3

TECHNICAL DESCRIPTION

3.1

GENERAL
. . . . .
e e e e e e e e e e e e e e e e e e e e
3-1
MEMORY ARRAY
.............................. 3-2
ADDRESSING LOGIC
. . . . . o
e e e e e e e e e e e e e e e e e 3-3
TIMING AND CONTROL LOGIC . . . . it i i i e e e e e e e e 3-5
|
General
. . . . . L
e
e
e e e e e e e e e e e e e e e e
3-5
Memory Read Operation
. . . ... ... ... ... ...
.... 3-5
Memory Write Operation
. . . . . . . . . .t v v i v v i e e e e 39
Memory Read-Modify-Write Operation - . . . . . . . .. ... ... .. 3-11
MEMORY REFRESH OPERATION
..................... 3-11
General
. . . . .
e e e e e e e e e e e e e e e e e e e e e e e e
e
31
Internal Refresh . . ...
.. e
e e e e e e e e e e e e e e e e e e e 3-11

3.2
33

3.4

3.4.1
342
3.4.3
3.4.4
3.5

3.5.1
3.5.2
3.5.3

External Refresh

3.6

CHARGE PUMP CIRCUIT

CHAPTER 4

MAINTENANCE

4.1

GENERAL
. . . . . o
e e e e e e e e e e e e e e e e e e e e
CONFIGURING JUMPERS W4, W8, Wl12,and W16
... ... .......
Configuring the MSVI1I-CB
. . . . . . . ... ... ...
...
Configuring the MSV11-CC
. . . . . . . . . . . . v,
Configuring the MSV11-C . . . ... ... ... e
e e e e e e e
e

4.2

4.2.1
4.2.2
4.2.3

... ... ... .. e
. . . . .

e e

e e 3-14

ot e e e e e e e e e e e e e e e e e 3-15

4-1
4-1
4-1
44
4-5

\«\“_,,//‘

ILLUSTRATIONS
Figure No.

Title

Page

1-1

MSV11-CD 16K by 16-Bit Read/Write Memory

. . . . . . . . . . . . .. ..

2-1

MSV11-C Switch and Jumper Locatlons

e e e e e e e e e

2-2

Module Installation

. . . .. ... ... .. ...

MSV11-C Block Diagram

Memory ArTay

3-3

Addressing Logic

Timing and Control Logic

. . . . .. e

80 ns Delay Circuit

3-7

Write (DATO or DATOB) Sequence

3-8

Refresh Logic

e e

e e e e

e e

. « v v v v v o e e e

. . . . . . . . o 0 o i
. . . . .e

Charge Pump Circuit

3-2

et e e e e e e e e e

e
e e e e e

e e e e e e e e e e e

e e

e e e e e e e e e|

. . . . . ... ... .... S

- External Refresh Signal Sequence

3-11

. . . . . . .. e e e e e e

- Read (DATI) SEQUENCE

3-10

e e e ee e

3.5

Internal Refresh Sequence

e e

. . ..

. . ... ... .. e e e e ee e e e e e e e

. . . . . . . .

3-6

e e e

e e

e 3-10

e e

3-12

e e e e e e e e e e e

. . .. . . . e

. . . . .. ... ....... e

e e

3-13

e 3-14

e e e | 3-15

4.2

Normal MSV11-C Operation
. . . . .. e e e
e
Reconfiguring MSV11-CB Bank Jumpers . . . . . . . . v v v v v v
...

4-3

Reconfiguring MSV11-CC Bank Jumpers

. . . ..
. e

e e»

4-5

Reconfiguring MSV11-CD Bank Jumpers

. . . . .. ...

... .......

4-6

4-1

TABLES

Title

| Table NQ.,

1-1
- 2-1
2-2

Backplane Pin Utilization

. . . . .e

- MSVI1-C Addressing Summary
-

Refresh Mode Selection

. . . .. . ... .vvvin

.. |

. . e R

4-1

4-2

)

CHAPTER 1
- INTRODUCTION

1.1

INTRODUCTION

This manual contains all user 1nformatlon requlred for 1nsta111ng, operating, and using the MSV11-C-

series dynamlc metal oxide semlconductor (MOS) read /wrlte memory optlons Four memory options

Model
MSV11-CA
MSV11-CB
MSV11-CC
MSV11-CD

are coveredin this manual

Description

4K by 16-bit read/wrlte memory .
|
|
8K by 16-bit read /write memory
12K by 16-bit read/write memory
B
‘16K by 16-bit read/wrlte memory (Frgure 1 1)

All MSV11-C models are LSI 11 bus- compatlble and can be 1nstalledin any backplane locationin the
LSI-11, PDP-11/03, or PDP-11V03 system

1.2

GENERAL DESCRIPTION

The MSV11-C consists of a single ‘““quadTM (four sets of backplane pins) module (prlnted circuit board)
that plugs into any standard LSI-11 backplane. Memory contents are volatile; thatis, when operating
power is lost, memory data is lost. In addition to the basic 4K, 8K, 12K, or 16K memory capability
(depending upon model), all MSV11-C options feature:

On-board refresh circuit that eliminates its need for refresh signals on the LSI-11 bus.

The system memory address space to Wthh the optlon will respondis user-configured via
switches contained on the module. An address can start at any 4K bank boundary.

It will perform DATI, DATO, DATOB, DATIO, and DATIOB bus cycles akccording to

Jumpers allow the module to be configured for using external bus refresh s1gnals and d1s-

LSI-11 bus protocol.

abhng the internal refresh function.

No special power is requlred. Only the normal +5 and +12 Vde voltages are necessary. An

‘on-board charge pump circuit provides the necessary -5 V operating voltage to the memory
chips.

Jumpers allow the user to implement,batt’erybackup power.

1-1

8173-4

Figure 1-1

1.3 SPECIFICATIONS
- 1.3.1 Electrical
g
|

MSV11-CD 16K by 16-Bit Read/Write Memory

o
|

Power Requirements

System Power

Operating

+5V £ 5%
+12V £ 5%

1.1 Atyp. (2.0 A max.)
.54 A typ. (0.56 A max.)

1.1 Atyp. (2.0 A max.)
0.16 A typ. (0.2 A max.)

Power

12W typ. (16.7 W max.)

T W typ. (12.4 W max.)

+12V + 5%

Standby

0.8 Atyp.(1.4 Amax.)

0.16 Atyp.(0.2 A max.)

Battery Backup Power
+5V -+ 5%

Operating Speed - The operating speeds stated below are based upon the bus not attempting a memory
cycle during a refresh operation and that an arbitration was not necessary.
Access Time:
Bus Cycle Type

DATI,DATIO

S
@

)

Access Time

300nstyp. (350 ns max. from RSYNC H)

DATO(B)

300 ns typ. (350 ns max. from RDOUT H).

Cycle Time:
Bus Cycle Type
DATI
v
DATO(B)

Cycle Time
|
650 ns typ. (750 ns max. from RSYNC H)
650 ns typ (750 ns max. from RDOUT H)
'NOTE

If a bus cycleis being done as a result of wmmng the

'synchronization arbitration, the bus cycle will be
~ delayed or increased from 0 to 80 ns. If a refresh
“operation is in progress when a cycleis requested, a
delay from 0 to 750 ns will occur before the bus cycle
starts

1.3.2 Envrronmental
Operating Temperature - 5° to 50° C (41° F to 122° F) with a relatlve humidity of 10% to 95% (no
condensation), with adequate airflow acrossthe module. When operatlng at the maximum temperature (50° C or 122° F), air flow must maintain the inlet to outlet air temperature rise across the
modules to 7° C (12.5° F), maximum.

1.3.3
Size
-

Mechanical
Height - 26.6 cm (10.5 in)
Length - 22.8 cm (8.9 in)
Width - 1.27 cm (0.5 in)

/‘/

NOTE
Length as stated is approximate and includes metal
handles. Actual module length is 21.6 cm (8.5 in).
1.3.4

Backplane Pmmng Utilization

MSVI11-C backplane pin utlhzatlonis shownin Table 1-1. Blank spaces indicate pins not used by the
MSVI11-C.

1.4

REFERENCES

Additional DIGITAL publications that will assist the user in installing and maintaining the MSV11-C
memory option include:

Microcomputer Handbook
PDP-11V03 System Manual

1-3

Table 1-1

| B Connector

A Connector

Side 1

Backplane Pin Utilization

Pin | Side 2

Side 1

'BDCOKH|A

[+5V

C Connector

|Side
2

Side1 |Pin | Side 2

[+5V

BADI6L

|GND

BAD17L

|D
E

|BDOUTL

D
|[+12V
E |BDALO2L

D
E

|BRPLYL

|BDINL

|BSYNCL

|BWTBTL

GND

|BDALO3L

|BDALO4L

GND

|BDALOS
L

]

-5V

| K

|BDALO6L

-5V

|BDALO7L

TMARGIN

GND

|BIAKIL .

GND

|BDALOS
L

|BIAKI
L

N
P

|BIAKOL
|

N
P

|BDALO9 L
|BDALIOL

N
P

|BIAKOL

BREFL

|[R

|BDMGIL

|BDALI1
L

|BDMGIL

+12B

|BDMGO
L

|BDALI2 L

|BDMGO
L

GND

|(BDALI3L

|DBALI4L

|{BDALIS L

~|U

45V

GND
|BDALOOL

v BDALOI1 L

+5V

1-4

\'2

~Connector

Szt
N

CHAPTER 2

INSTALLATION

2.1

GENERAL

This chapter contains 1nformatlon requ1red for configuring and 1nsta1hng the MSV11 C in the LSI-11
system backplane. Configuring the module involves selecting the module’s address range via switches
and other functional operations implemented or disabled via jumpers. Proper installation will ensure
normal MSV11-C operation in the system and eliminate the possibility of physrcal’ damage to the
MSVI11-C module or backplane in Wthh it is 1nstalled Detalls are prov1ded in the following
paragraphs

2.2
CONFIGURING THE MSVII-C
2.2.1
General

)

Configuring the MSV11-C w111 alter 1ts operatlon for a spe01fic system apphcatlon The followmg items
can be configured:
|
|

Select the startin‘g‘ address for the contiguous memory contained on the mooule.

Refresh mode: on-board or external refresh,’ and reply to external refresh signals.

Battery backup power. |

Bus grant (BIAK L and BDMG L) signals.

In most applications, the user will simply configure the starting address and install the module. Refer
to the following paragraphs for procedures for configuring each item.
2.2.2 Address Selection
The MSV11-C’s address can start at any 4K band boundary. The address configuredis the starting
address for the contiguous portion of memory (4K, 8K, 12K, or 16K) contained on the module. Set the
switches, located as shown on Figure 2-1, to the de51red starting address as listedin Table 2-1. Note

that the moduleis designed to accommodate a 128K system addressing capability; however, the pre-

sent addressing capability of the LSI-11 system, including all PDP11/03 and PDP11-V03 systems, is
32K. By PDP-11 convention, the upper 4K address space is normally reserved for peripheral device
and register addresses. Thus, with the present LSI-11 maximum addressing capability of 32K Bank 7
(addresses 160000-177777) normally should not be used for system memory.
.

2-1

—

S12

s3
s4
S5

OFFe—sON

w14

w1t

w16

w12z

ws.

‘

W56

w7
81734

and Jumper Locations
Figure 2-1 MSV11-C Switch
2.2.3

Refresh Mode Selection

The MSV11-C module is factory-configured for 1nternal (on-board) memory refresh and no reply
(assertlon of BRPLY L)in response to refresh cycles on the LSI-11 bus. Factory-installed wire-wrap
jumpers W6 and W7, located as shown in Figure 2-1, provide these functions. W7, when installed,
enables internal refresh W6, when removed, enables the MSV11-C to reply to external (SLI-11 bus)
refresh cycles. External refresh cycles can be controlled by the LSI-11 microcomputer module (M 7264
or M7264-YA), or by a DMA device, such as the REV11-A and REV11-C options. W6 must be
installed if W7 is installed to prevent erroneous assertion of the BRPLY L s1gna1 A summary of
refresh modejumpers is providedin Table 2-2.

The reply to external refresh cycles is normally enabled when the module is deemed the slowest dynam-

ic MOS memory device in the system. The slowest device (in this application) is generally the device
located the greatest electrical distance from the LSI-11 microcomputer or DMA device generating the
refresh bus cycles. Only one device should be permitted to reply to refresh bus signals.

2.2

‘p yoeygAIowawJueqU=0YsaIpe"soeds

SAION

Arewuing 3uIs aIp y D-ITASIN 1-T dIqEL

2-3

NO=1 A410=0

Jumper
|
Wé
W7
in
in
out
out

Refresh Mode Function
|

in
“out
in
out

Factory configuration. Internal refresh; no reply.
External refresh; no reply
Illegal-do not use.
|
External refresh; reply enabled.

2.2.4 Battery Backup Power

MSV11-C modules are supplied with all power jumpers (W1, W2, W3, and WS) installed. Thejumpers
connect normal system power to battery backup power pins. If battery backup power is to be used with

the MSV11-C, cut or remove jumpers W1 and W5; the module will receive DC operating voltages (+5

V and +12 V) from the battery backup power source, only. If battery backup power is available, but
battery backup power is not desired for a particular MSV11-C module, cut or remove jumpers W2 and
|
W3; jumpers W1 and W5 must remain installed.
2.2.5

Bus Grant Contmulty

2.2.6

Bank Select Enable

Bus grant continuity jumpers W14 and W15 are factory installed and normally should not be removed

Bank select enablejumpers W4, W8, W12, and W16 are factory-configured for the partlcular MSV1 1-

C model ordered. They are wire- wrappedjumpers that normally should not be changed. Thelruse is
describedin Chapter 4.

2.3

INSTALLING THE MSV11-C MODULE

MSV11-C modules must be installed or removed only when dc power is removed from the backplane
The PDP-11/03 contains a control/indicator panel on the front of the power supply; the DC ON/OFF
switch allows the user to turn off dc power for safe module insertion and removal.

Modules must be installed in the backplane with components facing row 1, as Shewn in Figure 2-2.

HANDLE
FINGERS

—METAL
HANDLE

CARD
CAGE

FINGERS

BACKPLANE
CONNECTOR
BLOCK
11-4591

Figure 2-2

Module Installation

2-4

Table 2-2 . Refresh Mode Selection

MSV11-C modules are equipped with metal handles that facilitate module installation and removal.
When installing an MSV11-C into the H9270 backplane (or the DDV11-B backplane equipped with
the HO341 card cage assembly), carefully start the module fingers into the backplane connector block
while inserting the metal handle fingers into the card cage as shown in Figure 2-2. Once the module has
been started into the backplane in this manner, insertion can be completed by pressing downward on
the handles; both handles must be pressed simultaneously. Module removal can be accomplished by
simultaneously raising both handles until the handle fingers clear the card cage. The module can then
be removed easily.

CAUTION

The LSI-11 modules and the backplane assembly
mounting blocks may be damaged if the modules are
plugged in backward.

DC power must be removed from the backplane dur-

ing module insertion or removal.

2-5

- CHAPTER 3

TECHNICAL DESCRIPTION

3.1

GENERAL

e’

The basic functions thatcomprise the MSV11-C are shownin Figure 3-1. All srgnals 1nterfaee with the
LSI-11 bus via bus receivers, bus drivers, and bus transceivers, which contain both receiver and driver

functions. The receiver function of the bus transceivers shown in the figure distributes the 16 1nput
data/address lines (DIOO—IS H) to the memory array and to addressing logic.

DIP@-15 H

<:%DAL¢¢ 15';:’ XCVRS |
———

aus

{

MEMORY

DOUT@@-15
H

ARRAY

——

RDIN L

FRPLY
(1) L

BSYNC L
__BDIN
L
0

2
2

"
5—

BRPLY L
BDCOK H

BDOUT L
’

TIMING AND
CONTROL

LOGIC

o ——

BREF L

GND

ADDRESSING

Logic

LOGIC

+12V

—

REFRESH

CHARGE

PUMP CKT|[
> — 3V
-

‘

11-4592

Figure 3-1

MSVI 1-C Block Diagram

Timing and control logic receives BSEL H from the addressmg loglc whenever the bus address recelved

is within the range configured by the operator. Thisis the signal that allows the timing and control
logic to communicate with the bus and generate appropriate t1m1ng and control signals from the
opnon

3-1

The memory responds to address and control signals by storing (wrltmg) an 8-bit byte or 16- b1t word,
or by outputting 16-bit (word) read data to the LSI-11 bus.

Additional functlons include refresh logic and a charge pump circuit. The refresh logic is capable of
responding to LSI-11 bus (‘“‘external”) refresh signals, or it can produce refresh signals (including row
address) independent of the LSI-11 bus (“internal refresh”) Memory chips are refreshed by forcing a
read cycle at all 64 row addresses once every 2 ms, maximum, The MSV11-C refresh logic refreshes one
row address every 25 ,us

The charge pump circuit elrmlnates the need for backplane power other than the standard +5 V and
+12 V. It contains an inverter circuit that receives +12 V input power and produces a negative voltage
output. A Zener-diode regulator produces -5 V for the memory integrated circuits.
3.2

MEMORY ARRAY

The memory array (Figure 3-2) consists of 16 4K by 1-bit 1ntegrated circuits per memory bank four
memory banks are included in the option. Hence, 64 integrated ClI‘CLlltS comprlse the array Each

integrated circuit provides one b1t by 4096 locatlon storage |

;

CAS@, 1L

MOS MEMORY ARRAY

cS@. 1L
AQ@Q —@5A, BL
RASA

RASB

RASC

RASD

;

BITS @@ -@7

DIG@ - 15H

D’

BITS @@ —15

—Y"

>88L—J1T5H

WB@L
WBIL
,

11-4593

Figure 3-2

Memory Array

The memory array is arranged so that one bank out of four can be accessed at a time. The row address
strobe (RASAL, RASBL, RASCL, and RASDL) 81gnals select the desired bank. During a write operation, control signals WB0 L and WB1 L enable writing in the “low” byte (data b1ts 00«—07) or “hlgh”

,byte (data brts 08-15), or full word (both bytes accessed s1multaneous1y)

Duphcate drlvers are used for certain signals. These signals include column address strobe (CAS) ch1p
select (CS), and address lines 00-05.

3-2

The duplicate driver output signals include:
Output Signals

DriVer_s
CAS
CS
Address

~
|

CASOLandCASIL
CSOLand CSIL
A00-05A L and A00-05B L

Each memory integrated circuit has six address input pins and contains a 12-bit address latch.
Addressing the 4096 locations is accomplished by multiplexing the 12-bit address in two 6-bit segments. The low-order six bits (bus address bits 01-06) are first multiplexed onto A00-05A L/A00-05B
in the addressed sixteen integrated circuits by the active row address strobe
L, signal lines and latched
signal. This is followed by multiplexing the high-order six bus address bits 07-12 onto the same six
address lines; the column address strobe signals latch the address bits in the memory integrated circuits. The memory array is ready for the read or write operation once the addressing sequence has been
completed. A detailed description of the complete addressing and read or write sequence is included in
Paragraphs 3.3 and 3.4.

3.3

ADDRESSING LOGIC

)

The addressing logic (Figure 3-3) decodes a memory bank within the user-defined address space,
latches the word or byte address within the selected bank, and routes time-multiplexed 6-bit address
segments to the memory array for one of 4096 word addresses within the bank. In addition, it routes
the refresh address to the memory bank during a refresh cycle. The following paragraphs describe
addressing logic functions in detail. Generation of the control signals and how they relate to a complete memory read or write operation is described
in Paragraph 3.4.
-

‘A memory read or write cycle is initiated by the addressing portion of the LSI-11 bus cycle. (A detailed
in the Microcomputer Handbook, Section 1,
description of LSI-11 bus cycles and timing is contained
on BDALOO-15 L and BAD16 and 17 L.
address
the
places
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Chapter 3.) The
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system
LSI-11
by
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and
(BAD16
The bus master then asserts BSYNC L indicating that a valid address is on the
‘system configurations.)
edge of BSYNC L, latching the received address bits RAO-17 H
bus. LATCH L occurs on the leading
and the received bus write/byte control signal, RWBT H, for the duration of the bus cycle. Note that
RWBT H is active during the addressing portion of DATO or DATOB bus cycles, indicating that a
memory write operation will follow.

- Start address switches S1-S5 are configured by the user to select the address space that the 16K
memory will occupy. ADDR OFFSET 13-17 L signals are the encoded starting address switch bits.
The bits are applied to the adder and decoder logic, where they are added to the latched address bits
LA13-17 L. One decoded output (ROWO-3 L) goes active (low) only when the latched address is
within the 16K address space selected by the user. When the latched address is not within the assigned
address space, the decoder outputs remain passive (high). These signals are applied to the BSEL H and
bank select OR gates. Any active output (or an active LAT EXT REF L signal) produces an active
(high) BSEL H signal; BSEL H enables the timing and control logic to start a memory cycle.

Bank select OR gates receive one active ROW signal via jumper W4, W8, W12, or W16 or an active
REF L signal and produce one active BANK A-D H for normal memory cycles, or all active BANK

A-D H signals during a memory refresh operation. The activeBANK A-D H signal is ANDed with

TRAS(1) H for proper timing during the memory cycle. The appropriate row address driver then
produces one active RAS A-D L signal that enables one memory bank; all four signals go to the active
state during a refresh operation to allow all memory banks to be refreshed simultaneously.

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The 3:1 address multiplexor and address drivers select and apply the 6-bit address to the memory
array. During a normal (non-refresh) memory cycle, MUX H and INT REF(1) H are passive (low);
and low-order six address bits are applied to the memory array and latched in each memory integrated
circuit. MUX H then goes high, selecting the high-order six bits which are then latchedin the memory
integrated circuits to comprise the 12-bit address. During an internal memory refresh operation, INT
REF(1) H goes active, selecting the refresh address bits (RAO 5 H), which are applied to the memory
array. If the external memory refresh mode of operation is configured by the user, the low-order
address bits (LA1-6 H) are used for the refresh address.

During a write operation, the bus I /O sequence can be a DATO (word) or DATOB (byte) cycle. Bus
signal BWTBT L goes passive during the data portionof a DATO cycle, enabling writing in all 16 bits
of the addressed word. RWBT H goes low, inhibiting the byte inhibit gates and HBWINH L and
LBWINH L go passive (high) enabling WBO L and WB1 L memory array drivers. The drivers are
enabled only during an output data transfer (BDOUT L is active) and a non-refresh operation. The
active MUX H signal gates the drivers on at the proper time during the bus cycle. During a DATOB
bus cycle, RWBT H goes active, enabling the byte inhibit gates. Latched address bit 0 (signals LAOO
H and LAOO L) inhibit the WBO L or WBI1 L signals, as appropriate, to enable writing in only the

addressed 8-bit byte within the addressed 16 bit location.

When backplane power is abnormal DCOK H goes low. Th1s s1gnal 1nh1b1ts WBO0 L and WBI L,
preventing erroneous write operations.
3.4

3.4.1

TIMING AND CONTROL LOGIC
General

Timing and control logic (Figure 3-4) 1nterfaces the MSV11-C to the LSI 11 bus and produces the
internal control signals required for memory operation. This function produces timing and control
signals for three types of memory cycles: read (DATI), write (DATO or DATOB), and refresh. In
addition, read-modify-write cycles (DATIO or DATIOB) can be executed according to LSI-11 bus
protocol. The MSV11-C will also respond to externally generated refresh cycles if that refresh modeis
configured by the user.

3.4.2 Memory Read Operation

The control signal sequence for a memory read operatlon is shownin Figure 3-5; also refer to the logic
functions shown in Figure 3-4. All bus transactions involving the MSV11- C are initiated by the
addressing portion of the bus cycle. The bus master first places an address on the BDAL00-15 L (and
optional BAD16, 17 L) lines and asserts BSYNC L. BSYNC L is received and distributed on the
MSVI11-C as RSYNC H and LATCH L. The leading edge of LATCH L latches the addressin the
addressing logic and the address will remain vahd for the duration of the bus transaction (during the
active state of BSYNC L).

Initially, NO DIN L and LOCKOUT L are passive (high) enabling two inputs of the Read Cycle
Initiate gate. RSYNC H enables a third input to the gate. When the latched address is within the
MSV11-C’s address space configured by the user, BSEL H goes high, producing a low (active) Read
Cycle Initiate gate output. The low signalis ORed producmg an active GOTIM H signal. Thisis the
signal that starts the memory cycle.

GOTIM H is then applied to the 80-ns delay circuit. The delay cireuit inserts an 80-ns delay only

during internal refresh operation, as described in Paragraph 3.5.2. The delay circuit is shown in Figure
3-6.

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MULTIPLEXOR/
DRIVER LINES
AOD-0O5A L, AOD -@258B L

BSEL

GOTIM

LOCKOUT

START

W oo

BSYNC

LADDRESSJ

ADDRESS LATCHED
LOW BITS

(BUS BIT51 6)

HIGH 6 BITS

(BUS BITS 7-12)

]

TRAS(1) L

RAMP
VOLTAGE

MUX

CSoL, CS1 L

CAS

CAS@, 1 L
LATCH HIGH 6
- ADDRESS BITS
SRPLY

FRPLY (1) L

BRPLY

BDIN

-11—-4596

Figure 3-5

Read (DATI) Sequence

3-7

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GOREF L

L
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If an internal refresh cycle is in progress when BSYNC L is asserted, the memory read or write cycle

cannot be executed until the refresh cycle has been completed. However, if an internal refresh cycle is
requested after GOTIM H is generated for a read or wrlte cycle, the read or write cycle is flrst

executed.

START L is the active (low) delay circuit output and it sets the Row Address Strobe flip-flop. Active
TRAS(1) H and TRAS(1) L signals are produced. Active TRAS(I) L is ORed with OFF L and the
Lockout flip-flop to generate LOCKOUT L. LOCKOUT L is ANDedin the Read Cycle Initiate gate,
the Write Cycle Initiate gate and the Internal Refresh gate to inhibit the GOTIM H signal from
occurring until the present cycle is complete. The Lockout flip-flop is used to generate a delay from the
reset of TRAS(1) L to ensure proper memory timing. TRAS(1) L is gated with passive (low) SRPLY H
and INTREF H signals producing a high signal that clocks the Go Inhibit flip-flop to the set state;
note that the high (active) RSYNC H signal applied to the data input of the flip-flop when clocked by
the leading edge of TRAS(1) L enables the set state on the positive-going leading edge of the clock
input to the flip-flop. The resulting high flip-flop output signal is ORed to produce an active (low)
NODIN L signal that inhibits the Read Cycle Initiate gate to prevent multiple DATI cycles from
occurring without RSYNC H being reset

TRAS(1) H enables column address strobe drivers that latch the high-order 6-bit addressin the memory array laterin the read cycle

TRAS(1) L activates an R-C ramp Voltage generator that applies a rising voltage (Figure 3-5) to the
voltage comparator circuits. Four voltage comparators, each having different reference voltage inputs,
produce the four control signals: MUX H, CAS H, SRPLY H, and OFF L. The reference voltage
applied to a comparator determines the point along the ramp voltage at which the comparator’s
output will change logical state. Hence, the reference voltage, relative to the ramp voltage, determines
the time delay produced by each comparator circuit.

The first active signal produced by the comparator circuit is MUX H. MUX H selects the high order
six address bits that are applied to the memory array. MUX H is ANDed with the passive REF L
signal producing the active chip select (SCO L and SC1 L) signals.

3-8

Figure 3-6 80 ns Delay Circuit

11-4597

The next voltage comparator output signal that goes active is CAS H. CAS H is ANDed with the

active TRAS(1) H signal producing the active column address strobe (CASO L and CAS1 L) signals.
These signals latch the high-order six address bits in the memory array integrated circuits, completing
the 12-bit address within the accessed 4K bank. Read data is then available on DOUTOO-15 H.

The next voltage comparator output signal that goes active is SRPLY H. SRPLY H is applied to a
pulse generator circuit whose 30 ns output pulse is ANDed with the passive REF L signal; the resulting
low pulse sets the Reply flip-flop, and

FRPLY (1)

H FRPLY(1) L signals go to their active states. The

BRPLY L bus driver asserts the BRPLY L signal and driver portions of the bus transceivers, enabled
by RDIN L (received BDIN L) and FRPLY(1) L, place the memory read data on BDAL0O-15 L.
The last voltage comparator signal produced is OFF L. OFF L clears the Row Address strobe flip-flop
and TRAS(1) H and TRAS(1) L go to their passive states. The passive (low) TRAS(1) H signal inhibits
the column address strobe drivers and CASO L and CAS1 L go to their passive states. The passive
(high) TRAS(1) L s1gnal resets the ramp voltage and MUX H, CSO L CS1L, CAS H, SRPLY H, and
OFF L go to their passive states.

The 'bus master responds
to the active BRPLY L signal by reading the data from the bus and terminating the BDIN L signal. BDIN L (passive) is received and inverted producing a negative-going
trailing edge on BDIN H. RDIN H is ORed with RDOUT H producing a positive-going transition at
the clock input of the Reply flip-flop. This transition clocks the flip-flop to the reset state. FRPLY(1)
H goes low, inhibiting the BRPLY L bus driver and FRPLY(1) L goes high, inhibiting the
BDALO00-15 L read data bus drivers. The bus master responds by terminating BSYNC L, and the
memory read cycleis completed

‘~\ H

3.4.3

Memory Write Operatlon
A memory write (DATO or DATOB) cycleis somewhat similar to the memory read cycle describedin
Paragraph 3.4.2. However, during the addressing portion of the cycle, the bus master asserts BWTBT
L, indicating an output (write) operation is to follow. The signal sequence for the timing and control
logic write operation is shown in Figure 3-7. BWTBT is received (RWBT H) and latched by the active
LATCH L signal; the address bits are latchedin the same manner, as previously described. The latched
signal (LWBT H) inhibits the Read Cycle Initiate gate and prevents immediate generatlon of the
GOTIM H signal. However, the latched row address bits LA1-6 H are routed via the 3:1 address
multiplexor to the memory array.

The bus master then places the write data on the BDAL bus and asserts BDOUT L. BDOUT L is
received producing RDOUT H. RDOUT H is gated with passive (high) LOCKOUT L, FRPLY(1) L,
and active WRITE ENBL H signals to produce the active GOTIM H signal.

Operation of the timing and control logic continues as described for read operation generation of the
MUX H, CAS H, SRPLY H, and OFF L signals. However, the RDOUT signal enables WB0 L
and/or WBI1 L signal generation in the addressing logic, as described in Paragraph 3.2, and the
received data is written in the addressed location.
The bus master responds to the BRPLY L signal by terminating BDOUT L and removing the write
data from the BDAL bus lines. RDOUT H, which is ORed with the passive RDIN H signal, goes low,
and the low to high transition resets the Reply flip-flop. BRPLY L then goes passive (high). The bus
master responds by terminating BSYNC L and the write operation is completed.

3-9

BDAL @0-15 L
BWTBT L

WRITE DATA

| aboress |
I

ASSERTED= DATOB. NOT ASSERTED= DATO

BSYNC L

LATCH L

LA Q@O-17 H

ADDRESS

BODOUT

[

’

ADDRESS LATCHED
T

LOW 6 BITS
(BUS BITS 1-6)

HIGH 6 BITS
(BUS BITS 7-12)

MULTIPLEXOR/
DRIVER LINE

GOTIM H

START

7
/
L

TRAS (1) L

LOCKOUT

RAMP

VOLTAGE

MUX H

CsSoL, CStL

wWBO L, wB1 L

CAS

CASO L, CAST L

SRPLY H

FRPLY

BRPLY L

OFF L
11-4598

Figure 3-7

Write (DATO or DATOB) Sequence
3-10

3.4.4

Memory Read-Modlfy-erte Operatlon

The memory read-modify-write operation is produced by the DATIO (or DATIOB) bus cycle. The bus
master first initiates a ‘“‘memory read” operation at the addressed location. However, instead of terminating BSYNC L after the read portion of the cycle has been completed, BSYNC L remains asserted,;
the bus master places the write (modified) data on the bus and asserts BDOUT L. The MSV11-C
responds by writing the datain the addressed word or byte location. The BWTBT L signalis asserted
with the write data to indicate a DATIO bus cycleis in progress, when appropriate. Except for the
addressing portion being omitted for the write portion of the DATIO (or DATIOB) bus cycle, operation of the MSV11-11 is as previously described for memory read and memory write operations.
3.5
3.5.1

MEMORY REFRESH OPERATION
General

Dynamic MOS memory 1ntcgrated circuits compnsmg the memory array require periodic refreshingin
order to retain stored data. Thisis accomphshed by forcing a memory read operation on each of the 64
row addresses; one read operation is required for each row address. Each row address must be refresh-

edin this manner once every 2 ms (maximum).

MSV11-C memory refresh can be accomplished by using the on-board (internal) refresh logic signals,
or by using refresh signals present on the LSI-11 bus (external refresh). The internal refresh circuit is
most transparent to the LSI-11 system since it automatically refreshes one row address every 25 us;
neither LSI-11 microcomputer-generated refresh cycles nor DMA arbitration is required when the
internal refresh mode is selected. When other memory system components in the LSI-11 system require
LSI-11 bus memory refresh signals, such as the KD11-F’s resident memory and the MSV11-B 4K
memory option, the MSV11-C internal refresh mode can be disabled and the refresh operation can be
controlled externally by LSI-11 bus signals.
Normally, external refresh is controlled by either the LSI-11 processor or by an intelligent DMA
device. Processor-generated refresh signals consist of a series of 64 successive bus transactions. Each
series of bus refresh transactions takes approximately 135 us to complete and occurs at approximately
1.8 ms intervals. The REV11-A and REV11-C DMA refresh /bootstrap options are intelligent DMA
devices. They execute one DMA refresh cycle with one memory row address every 25 us (approximately). Note that when the external refresh modeis selected, all system memory components are
refreshed 31multaneously
3.5.2

Internal Refresh

The MSV11-C refresh logic circuit is shownin Figure 3-8. The sequence of 1nternal refresh operation is
shownin Figure 3-9. When the internal refresh modeis selected, jumper W7is installed, producing the
active (high) CLK EN H signal. This signal activates the 25 us clock and places a high level at the
Internal Refresh Cycle flip-flop’s data input. The positive-going transition of the 25 us clock clocks the
flip-flop to the set state, causing GO REF L and GO REF H to go to their active states (low and high,
respectively). GO REF H conditions the data input of the Internal Refresh flip-flop.

When the MSV11-C is not involved in a read or write operation,

FRPLY (1) L and LOCKOUT L are
passive (Figure 3-4). These passive signals are gated with the active GO REF H signal, producing an
active GOTIM H signal. The leading edge of GOTIM H clocks the Internal Refresh flip-flop to the set
state and INTREF(1) H goes high. INTREF(1) H is ORed with the passwe LAT EXT REF H signal
to produce an active (low) REF L signal.

3-11

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INTREF (1) H

X
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8¢. nsec DELAY

START L

LOCKOUT L

TRAS(1) L

H
'MUX

cS@ L, CSt L (PASSIVE)

CAS H

CAS@ L, CASIL
SRPLY H

OFF L

11-4600

| Figure 3-9 Internal Refresh Sequence

GO REF L is applied to the 80-ns delay dircuit (Figure 3-6) forcing the 80-ns delay to occur. The delay

provides settling time for the Interrupt Refresh flip-flop. After the 80-ns delay has completed, START
L goes active, setting the Row Address Strobe flip-flop, and TRAS(1) L and TRAS(1) H go to their
~ active states. TRAS(1) L produces an active LOCKOUT L signal, inhibiting the GOTIM H signal.
Operation then continues as in the memory read cycle, except the active INT REF(1) H signal selects
RAQOO-05 H refresh address (row) bits, which are routed through the address multiplexor and applied
to the memory array; passive (low) column address bits are applied to the memory array during the
active state of MUX H, but are not significant during the refresh operation. The active REF L signal,
applied to the reply circuit via jumper W6, also inhibits SRPLY H from setting the Reply flip-flop and
generating an erroneous BRPLY L signal.

- SRPLY H is gated with INTREF(1) H, producing a low clear signal for the Internal Refresh Cycle
flip-flop, and GO REF L and GO REF H go passive. GOTIM H goes passive and the 80-ns Delay
Circuit START L signal goes passive. OFF L then goes active (low) clearing the Internal Refresh and
Row Address Strobe flip-flops; REF L TRAS(1) L, LOCKOUT L, MUX H, CAS H, SRPLY H, and
OFF L signals go to their passive states.

3-13

The internal refresh counter is incremented by the trailing edge of REF CLK H prior to the next
internal refresh operation. Hence, each successive internal refresh operation uses the next sequential
row address.
e
|
|

When a memory read or write operation is initiated just prior to the refresh operation, and the read or
write cycle is still in progress, the leading edge of GOTIM H clocks the passive (low) GO REF H signal
into the Internal Refresh flip-flop; INTREF(1) H remains reset for the duration of the memory cycle.
The refresh operation will not be enabled until LOCKOUT L and FRPLY(1) L go passive (high) at the
end of the read or write cycle, enabling a new GOTIM H signal. If this condition occurs, the leading
edge of the new GOTIM H signal clocks the active (high) GO REF F signal into the Internal Refresh
flip-flop, and the refresh operation continues as described previously.
|
3.5.3 External Refresh
When the external refresh mode is selected, jumper W7 is removed. CLK EN H goes low, and the
Internal Refresh Cycle flip-flop cannot be set by the 25 us clock signal. CLK EN L goes high, enabling
one input to the LAT EXT REF L gate.

An external refresh cycle is initiated by the bus master asserting BREF L; EXT REF H goes high. The
bus master places the refresh row address on the BDAL 1-6 L lines and asserts BSYNC L. BSYNCL
produces the active (low) LATCH L signal that latches the 6-bit address in the address latch (Figure 33), and the EXT REF H signal (Figure 3-8), producing the active (high) LAT EXT REF H signal. This
signal is gated with CLK EN L producing the LAT EXT REF L signal and forcing an active BSEL H
signal in the addressing logic. Thus, the MSV11-C is addressed and enabled for the refresh operation.
The external refresh signal sequence is shown in Figure 3-10.

’

BDALI-6 L

| apbaess |

BSYNC L

LAT EXT REFH
Lags-gen
- LAT EXT REF L

/(‘J\
\l )

T TT
o

——
— —

11-4601

Figure 3-10 External Refresh Signal SequenCe

BREF L

3-14

The refresh operation continues as described for a memory read operation, except the active REF L
signal (produced by the active LAT EXT REF H signals) inhibits a BRPLY L signal, as described for
the internal refresh operation. If the MSV11-C must reply during the external refresh bus transaction,
jumper W6 is removed; REF L will not inhibit the reply circuit and BRPLY L will be generated. Only
one MOS memory module in a system is required to reply to the refresh bus transactions. The module
that should reply is the module with the slowest access time relative to the bus master device. This
module is generally the module located the greatest electrical distance on the LSI-11 bus from the bus
master device controlling the refresh operation.
3.6 CHARGE PUMP CIRCUIT
The charge pump circuit (Figure 3-11) provides the -5 V power for the MOS memory array integrated

circuits. The input power source for this circuit is +12 V. An oscillator circuit, running at approximately 40 kHz, produces a square wave drive signal to the rectified circuit. Q2 switches the ground
alternation for the charge pump capacitors, reducing the switching current requirement for the
oscillator circuit. The rectifier output is -10 V (approximately). The -5 V output is Zener diode regulated. Note that this circuit eliminates the need for backplane power other than the standard +5 V and
+12 V. The circuit remains active when battery backup power is used and normal system power fails.

+12V

SWITCH Q2
L,

> -5V

), 5V

[

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—

11-4602

Figure 3-11

Charge Pump Circuit

3-15

CHAPTER 4
MAINTENANCE

4.1

GENERAL

Diagnostic programs are available to thoroughly test the MSV11-C memory. Memory diagnostic programs are included in the ZJV01-RB paper tape software option and the ZJ215-AY floppy disk software option. Detailed operating instructions and program listings are included with each diagnostic
software option. Operating instructions involving the general use of system diagnostics (paper tape
and floppy disk) are included in the Microcomputer Handbook, Section 1, Chapter 9.
When running diagnostics for testing the MSV11-C, “worst case’”” timing can be forced through the use
of a “margin node” signal pin. This pin is located under the module at AL1. Normally it is not
connected. However, by first connecting it to +5 V and running diagnostics and then connecting it to
GND and running diagnostics, the worst case timing of the timing and control logic is forced. The
MSV11-C should pass diagnostic tests under these conditions.

If faults are detected by the diagnostic program, either the module can be returned to DIGITAL for
service as directed in the Microcomputer Handbook, Section 5, Chapter 3, or repaired by the user. A
flowchart describing normal MSV11-C operation is included in Figure 4-1 as a troubleshooting aid.
Also, refer to the troubleshooting chart (Table 4-1) and diagnostic symptoms to isolate faults.

A faulty module in which one or more 4K memory banks remain operative can be reconfigured and

used, less the faulty bank. Wire-wrap jumpers W4, W8, W12, and W16 provide this function. A
procedure for this operation is provided in the following paragraphs.
4.2 CONFIGURING JUMPERS W4, W8, W12, AND W16
4.2.1 Configuring the MSV11-CB (Figure 4-2)

If one 4K bank is faulty and one bank remains operative, proceed as directed below. The MSV11-CB
will then function as a 4K memory and its starting address can be configured as directed for the
MSV11-CA in Table 2-1.

First Bank Faulty

Remove jumpers W4 and W8,

Connect (wire-wrap) a new jumper from W4 to W8A.

Second Bank Faulty
1.
Remove jumper W8. No additional configuring is required.

4-1

BSYNCL IS

ACTIVE

BSEL H

‘DO NOT RESPOND

ACTIVE

OR START ACYCLE

(WAIT)
l

YES

BDOUT L

ACTIVE

(WAIT)

MEMORY BUSY

(INTERNAL

YES

(DATIO CYCLE)

REFRESH)

’

BSYNC
L
PASSIVE

L STARTCYCLE

YES

]

(INTERNAL

READ MEMORY

“MEMORY BUSY

(WAIT)

[

REFRESH)

BDOUTL

N ACTIVE

AND SET

REPLY E/F

Y ves

START CYCLE

;

WRITE DATA

:MEMORY AND SET

(WAIT)

REPLY F/F

" PUT READ DATA

(WAIT)

ON BDAL BUS

BDOUT L

PASSIVE

[:RESET REPLY F/F ] |

BDIN L
PASSIVE

BSYNC L

(WAIT)

REMOVE READ

PASSIVE

DATA FROM

BUS AND RESET

REPLY F/F

YES

EN LATCH ADDR ESS—I

!
MEMORY READY
FOR NEXT CYCLE
11-4606

Figure 4-1

Normal MSV11-C Operation
4-2

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g. | @

?3 Gt: E Té

€S

|olR

|85 | % | 2B

22|

|Ea|E|lS|S|S|8|E8|Es

|22

= wn

|E|E€|2|z2e|le8|28|2|g|e

A|ala|R|SE|SE|EE|A

MSV11-C Troubleshooting Chart
Table 4-1

SI9ALIP T [SVD T OSVO

|83

o | —]= E

o | ST

|5825

|=g2(=|lo|=

(|33

E2|E|E|E

or multiple memory integrated circuit failures.

pu® 1oA1021 snq T Jqud|

*NOTE: Memoty array failures consist of shorted or open circuit board etch

JI30] Ysaljal [euIdluf

W4o0—oW4A

W8 0—O0 WBA
OWi2A
wWi2o

(A) NORMAL JUMPER CONFIGURATION

o W4A

w80

TMM WSBA

Wi2o0

OW12A

(B)

FIRST BANK FAULTY

A
W4 0—0 W4

W80

OWSA

Wi2o

OWI{2A

o
Wi

OWIi6A

Figure 4-2

11- 4603

Reconfigurlng MSV11-CB Bank J umpers

4.2.2 Configurmg the MSV11-CC (Figure 4-3)

If one 4K bankis faulty and two banks remain operatlve, proceed as directed below. The MSV11- CC

will then function as an 8K memory and its starting address can be configured as dlrected for the
|

MSVll CB in Table 2-1.

Flrst Bank Faulty

Remove jumpers W4 and W12.

Connect a new jumper from W4 to W12A.

Second Bank Faulty

1.
2.

Remove Jjumpers W8 and W12.
Connect a new Jumper from W8 to WI12A.

‘Third Bank Faulty

Remove jumper W12 No add1t10na1 configurmgis required.

4-4

W4 0=—0
W4 A

W8 o—0 W8A

Wi2

=0 W1i2A

Wi 0O

OWIi6A

(A) NORMAL JUMPER CONFIGURATION

W40,

OW4A

w8 ;fi L

Wi2o

YoWwi2A

Wi6o

OWI6A

| R

(B) FIRST BANK FAULTY

W40—0O W4A
ws

wizo

O W8A

Wi2A

wW40—0O
W4 A

w8 o—0 W8A

wi2o

oOWi{2A

Wi6o

OWi6A

(D) THIRD BANK FAULTY
11-4604

Figure 4-3

Reconfiguring MSV11-CC Bank Jumpers

4.2.3 Configurmg the MSV11-C (Figure 4-4)
If one 4K bankis faulty and three banks remain operative, proceed as directed below. The MSV11-C
will then function as a 12K memory and its starting address can be configured as directed for the
MSV11-CCin Table 2-1.

4-5

W4 A
W40—0O
w8 o—0O W8BA
Wi20—O Wi12A
wieo—0oW1{6A

’

(A) NORMAL JUMPER CONFIGURATION

w4q,

OW4A

WB8BA

wi2

Wi2A

wi6o

wieA

(B) FIRST BANK FAULTY

W4O0——-0OW4A

oWS8A

w12%w12/.\
wWico

Wi6A

’

W4 A
W4 0—0

w8o—0O WS8A

wiz2

OW12A

w160

W16A

‘

(D) THIRD BANK FAULTY

‘

W4 A
W4 0——O0

wW80—0 W8A

Wi20—OW1{2A
Wi60 OWIi6A

’

(E) FOURTH BANK FAULTY
11-4605

Figure 4-4

Reconfiguring MSV11-CD Bank Jumpers

)

First Bank Faulty
1.
Remove jumpers W4 and W16.

Connect a new jumper from W4 to W16A.

Second Bank Faulty
1.
Remove jumpers W8 and W16.

Connect a new jumper from W8 to W16A.

Third Bank Faulty

1.
2.

Remove jumpers W12 and W16.
Connect a new jumper from W12 to WI16A.

Fourth Bank Faulty

Remove jumper W16. No additional configuring is required.

4-7

_MSV11-C USER’S MANUAL

JEK-MSV11-0P-001

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