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Document:	MM11D/DP Core Memory Manual
Order Number:	EK-MM11D-TM
Revision:	001
Pages:	76
Original Filename:

OCR Text

MM11-D/DP
core

memory

manual

dlilgliltiall

EK-MM 11D-TM-001

MM11-D/DP
‘core memory
-

manual

digitalequipmlent corporati’on - maynard, massachusetts

Ist Edition, February 1976

The material in this manual is for informational
purposes and is subject to change without notice.

Digital

Equipment

Corporation

assumes

responsibility .for any errors which may appear in

this manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

- MASSBUS

DECUS

11/76-14

CONTENTS

Page
CHAPTER 1

INTRODUCTION

1.1

INTRODUCTION

1.2

GENERAL DESCRIPTION

. . . . . . .

1.3

PHYSICAL DESCRIPTION

. . . . . . .

CHAPTER 2

INSTALLATION

3
CHAPTER

LOGIC DESCRIPTION

3.1

CORE ARRAY DESCRIPTION

. . . . . oo,S

General Core Description

3.1.2

MM11-D Core Array Description

MM11-D BLOCK DIAGRAM

3.3

VOLTAGE MONITOR CIRCUIT

Address Selection

3.6

MAR LOGIC . . . .

3.7

3-1

. . . . . . .

. . . .

CONTROL LOGIC

3.7.1

3-7

e e e e

e e e e 3-10

e 3-11
. . . . . . . . . ...
... ... 3-11

L L

e e

e 3-13

e e 3-16

. . . . .. .

Read Control Logic

. . . . . . . o o o

. . . . . . . . .

3.7.2

Write Control Logic

CURRENT SOURCES CIRCUIT

3.9

VREF CIRCUIT

3.10

DRIVER/SWITCH CIRCUIT

. . . . .

3-20

. . . . . .. .. ..

e e

e e e

... P 3-20

e e e e e

e e, PR 3-26

. ..,
. .. PRe

X Driver/Switch Circuit

e 3-17

o oo A 3-17

e e e e .. 327

. . . . .. .. 3227

3.10.2

3.11

SENSE/INHIBIT CIRCUIT

... ... e

3.12

STACK CHARGE CIRCUIT

. ... ... ... ... .. e

CHAPTER 4

MAINTENANCE

4.1

Y Driver/Switch Circuit

. . . . .. .. .. e

e e e e

PREVENTIVE MAINTENANCE

e e e

e e L. 327

e e 3-30
e e e

e . 3-33

. . . .. ... .. ... ... ... ...

.......

4.1.1

Visual Inspection . . . .. ...
... IR e

4.1.2

Voltage Measurements

4.1.3

SSYNDLY Check

. . . . . .. . . .. e e e

. .. ... ... e

4.14

Strobe and Drive Current Margins

4.1.5

MAINDEC Testing

4.2

4.2.1

4.2.2

4.2.3
4.3
4.3.1

4.3.2

4.3.3

APPENDIX A

3-2

. . . . . . e
e e s AU - 3-16

3.8

3.10.1

e e

. .. oo

. . .. .. e b e e e e e e e

. . . . . L

CONTROL
BIT LOGIC

e e, A

. . . . .

3.5

1-1

. . . . . . .. .
.
Memory Organization and Addressing Conventions

3422

e s, PP

. . e

"ADDRESSDECODING
LOGIC

3.4.1

. . .. . . . .

3.2
34

. . . . . .

3.1.1

e e

e e e e e e

4-1
4-1

e e L4

e eT

1 |

4-2

CORRECTIVE MAINTENANCE
. . . . . . . ...
.. .. ..., P
Voltage Adjustment Procedure . . . . . ... .. P e
e e
Sense Strobe Delay and Drive Current Adjustments
. . . . . . . . ... ... .. ..

4.2
4-2
4-2

- Troubleshooting Aids

e e e

e e e e e

. . .. ...
. e e

MAINDEC TESTING

. . . . . .e

e e e

&4l

. . . . . .« . o L

. . . . . . .

e e e

4-2

et e e e 4-10

0—124K Memory Exerciser . . . . . e
e
e ... 410
0—124K
Memory I/O Exerciser
. . . . . v v v v v v
e
4]
Combined Parity Memory Tests
. . . . . . . . .. ... .. . I
IC DESCRIPTIONS

ii1

ILLUSTRATIONS

Figure No.

Title

Page

1-1

G652 Module

. . ... ... ...
L.

1-2

H222 Module

. . ... ... ... ........

------

-----

1-3

MMI11-D/DP

3-1

Core Windings

3.2

Core Hysterisis Loop . . .. ... ... ... ....
Core Current/Voltage Output Relationship
. . . .
. .. ... ...
3-Wire Configuration
. . ... ... ... ... ..

3-4

3.5

. . . ... ;

oooooooooo

----------

Mat Sense/Inhibit Windings
MM11-D Block Diagram

3.8

Voltage Monitor Circuit

Voltage Monitor Timing (DATI Operation)
Memory Organization

Address Assignments for Three Banks of 16K Words Each

3-14

3-16

. . ... ... .. .. ..

3-6

3-8

e e 3-11

. .. .. .. ... .. ....

Address Decoding Logic

3-5

3-10

. . . . ..
...
... e

3-10

3-1

3-4

. . . . ... ... ... ..

3-11

1-5

3-1

3-3

. . . . . .. ... ...
. . . ... ...
...
..
... . [P

3-9

3-15

--------

.. .. ...

. .. ...

3-6

3-12

------------

MMII-DMat

1-3

-----

oooooooooo

. . ... ... e e

3.7

3-13

----

-----

3-12
.

3-13

3-14
... ... ..... [ e 3-17
MAR Logic . . ... ... . ... ... .... e
e e e e e
3-18
Read Control Logic - . . . . . . .. ... ... . ...
3-19
Read/Write Timing (DATI and DATO)
. . ..
. ..
3-22
Write Control Logic
. . ... ... ... .. ....
3-23
Current Sources Circuit
. . . . . . P
3-24

Control Bit Logic

e«

. ...

------------

--------

320

-----

Phase Selection
Vref Circuit

. . ... .. ... ... ... ... .

. . . . .. . ... ...

3-21

X-Driver Circuit

. . . . .. .. ... ... ... ..

3-22

Y-Driver Circuit

. .

323

3-24

Sense/Inhibit Circuit

. . . . ..

... ... ....

. . . . . ... ... ... L.

Inhibit Current Timing

. .

325

X Stack Charge Circuit

. . . . . . .e e

4-1

Troubleshooting Chart

. . . . . . .. .. .. ....

MM11-D Waveforms (A)

4-3

. .. ... ... ......

MMI1-DWaveforms (B)

. . . .. ... ... . ..

MM11-D Waveforms (C)

. . . . .. ..., ... e

4.2

4.5

-----

()

---------

------------

--------

------------

--------

[

¢«

Waveform Key A (Sense/Inhibit Circuit)

3-33
-

4.5

. . . . ... ... ... O

. .. ...,
..

. .. ... ...

------------

--------

------------

---------

TABLES

Title
MM11-D/DP Specifications

DD11-F Backplane Pin Assignments

3-1

Unibus Data Transfers

3-3

. . ... ... ... ..

Jumper Assignments for MM11-D Starting Addresses

(Interleaved-Memory Operation)
3-4

. . ...
. .. .

. . . . ... .. ... ... R

Jumper Assignments for MM11-D Starting Addresses

Operating Mode Selection

. . ... ... ...

. . . . . .. ... .. .

4-4

4-6

Waveform Key C (X-Driver Circuit)

1-1

4.3
a

e e, P

Waveform Key D (Y-Driver Circuit)

2-1

3-29

. ... ...

4-7

Table No.

3-28

3.32

. . . ... ... ... ... . ... ..

Waveform Key B (Current Sources Circuit)

- 3-26

3-31

. . . .. .. .. .. ..

4-8

3-2

3-25

------------

--------

-----

4.7

4.8
4-9
4-10

3-18

3-19

3-17

Snesezmgzi

TABLES (Cont)
Title

Table No.
3-5

Read Control Signals

3-6

Write Control Signals — Name and Function

Page

. . . . . . . . . . ..

3-7

Core Location X/Y Control Signals

3-8

X Driver/Switch Enable Signals

3-9

Y Winding Signal Relationship

3-21
. . . .. .. ... ...

... ... ... ... 3-25

. . . . . .. . ... ... ...

L. 3-26

. . . . . . . . . .. ... 3-29
.

. . . . .. .. .. I

T T 3-30

———

CHAPTER 1
INTRODUCTION

1.1

INTRODUCTION

This manual describes the MM11-D/DP Magnetic Core Memory, manufactured by Digital Equipment Corpo-

ration and provides the information needed to install and maintain the memory; in addition, it presents the
detailed theory of operation of both the logic circuits and the 3-wire, 3-D memory configuration.

The manual is intended to be used by DEC Field Service representatives and customers having PDP-11 training.
Readers who are familiar with digital computer theory and who have some knowledge of the PDP-11 Unibus

principles can also benefit from this manual (a detailed description of the Unibus can be found in DEC manual
DEC-11-HIAB-D).

1.2

GENERAL DESCRIPTION

The MM 11-D/DP core memory is a low-cost, low-power, high-reliability memory designed to be used with the
PDP-11 family Unibus. It assumes the role of a slave device to the PDP-11 processor or to any peripheral device
thatis designated bus master. The memory provides storage for 16- or 18-bit data words (two parity bits are
includedin the 18-bit word), and has a capacity of 16,384 (16K) words. The startmg address of the MM11-D/DP
can be set on any 8K boundary within the 124K Unibus address space (112K is the highest possible starting
address); a special feature of the memory allows the user to assign part of the 1/0 page (124K-128K) to the

- interleaving- permits the user to decrease the effective
MM11-D/DP. Another feature of the MM11-D/DP
memory cycle time. Two memory modules are used, one being assigned the odd addresses within a 32K block of
Unibus addresses, the other being assigned the even addresses within the same block. Thus, for consecutive word
addresses, the memories are accessed alternately; hence, memory cycles can partially overlap, reducing the effective cycle time.

1.3

PHYSICAL DESCRIPTION

The MM11-D/DP consists of an 8-1/2in. X 15 in. hex multilayer motherboard (G652)and a hex stack (H222)
thatis attached to the motherboard. The G652 motherboardis inserted into a Unibus backplane; it contains the
Unibus interface logic, the timing and control logic, the X and Y driver circuits, and the sense/inhibit circuits.
The H722 stack contains the core plane, stack diodes, stack charge circuits, and temperature-sensing circuitry

that facilitates compensation of core driving currents over the operating temperature range. Figures 1-1 and 1-2
show the separate memory modules; Figure 1-3 shows the two modules joined.

A Parity Control module (M7850) is used with the MM11-DP memory and must be inserted into the same
backplane as the memory (the MM11-DP can be used as a non-parity memory). Refer to the M7850 Parity
Controller maintenance manual for a description of the controller.

I-1

Table 1-1

MM11-D/DP Specifications
Memory Type

Magnetic core, read/write, random-access

Core Configuration and Size

Planar, 3W-3D, 18 mil O.D.

Capacity

MMI1-D:

16,384 16-bit words

MMI11-DP: 16,384 18-bit words

(2 byte parity bits)
Maximum Access Time

MM11-D:

425 ns

MM11-DP: 560 ns

(when used with a Parity Control module)
Maximum Cycle Time

MMI11-D:

1 us

MMI11-DP: 1 us
Voltage Requirements

Current Requirements

»+’20 Vdc,

+3%

+5 Vdc,

+5%

-5 Vdc,

+5%

dc Supply

Active*

-MMI11-D/DP +20 Vdc

Standby

4.0 A

0.8 A

+5 Vdc

4.0 A

40 A

-5 Vdc

0.5A

05A

dc Supply

Active

Standby

MMI11-D/DP +20 Vdc

Maximum Power Dissipation

80 W

16 W

+5 Vde

20w

20W

-5 Vdc

2.5 W

25 W

X—Y Current Margins

+59,

Ambient Temperature Operating Range

In accordance with DEC STD 102, Class C

Relative Humidity Operating Range

In accordance with DEC STD 102, Class C

*Active is defined as running all Os at 1.0 us repetition rate (worst
case).

) N ey

Figure 1-1

G652 Module

Figure 1-2

H222 Module

"
-

Figure 1-3 MM11-D/DP

CHAPTER 2

INSTALLATION

The MM11-D/DP can be installed easily. After removing the memory modules from the shipping cartons, use
the procedure that follows to prepare the memory for system operation.
1.

Select the starting address. Jumpers W1 - W8 on the G652 module are involved in this process.
Paragraph 3.4.2 discusses the startmg address determination; read this paragraph before mstallzng or
~

removing any of the jumper wires.

Check the backplane assembly to ensure that the correct dc voltages are present (Table 2-1 lists the
DD11-F “modified Unibus” backplane pins and the signal available on each pm) The voltages and
their limits are listed below; if they must be adjusted, use the procedure glven in Paragraph 4.2.1.
Voltage (dc)

Backplane Pin

+20 Vdc 3%

AlU, A1V, A2V

+5Vdc +5%

A2A, B2A, C2A, D2A, F2A

-5 Vdc 5%

B2V

. Ensure that the H222 module is firmly attached to the G652 module. Insert the G652 into the DD11F backplane; any one of slots 2 - 7 can
be used. If a parity controlleris used, it can be insertedin

connectors A and B in any of slots 2 - 8 (p yand non-parity memory cannot bemixed onthe same
backplane)
-

Connect the BC11-A Unibus cable to the memory. 'If thisis the last device on the bus, terminate the
Unibus by placing a 9302 terminator in the BUS OUT slot. If the memory is not the last device,
continue the bus by placing an M920jumper module or the BC11-A cable connector in the BUS OUT
slot.

If the system uses an M7850 Panty Controller, refer to the controller manual for mformatlon concerning the installation and adjustment of the M7850 module.
Load and run the MM11-D/DP diagnostic programs. Verify that the program printout agrees with
the total memory in the system.

2-1

Connect the Unibus Voltage Margin Tester to the memory at connector
J180 on the G652 module.
Run two passes of the 0-124K Memory Exerciser Diagnostic (MAINDE
C-11-DZQMB) with the
margin tester switches set at each of the four possible “on” positions:

XY CURRENT HIGH - allows high (+5%) memory drive current;
XY CURRENT LOW - allows low (-5%) memory drive current;

STROBE EARLY - allows an early sense strobe (~15 ns);
STROBE LATE - allows a late sense strobe (+15 ns).

NOTE
Only margin the memory with one parameter at a time.

Even good memories may fail under some combinations of
drive and strobe margins.
'

Disconnect the margin tester. Run the DZQMB diagnostic

to verify normal operation.

Table 2-1
DDI11L-F Backplane Pin Assignments

| INITL

~+5V

|DATIPCLR

+5V.

|PAUSEL

[INTRL

| TP

C | DOOL

GND

BR5 L

GND

DO1 L

BATTERY

BR4 L

DO3L

|INT

PARITY

SSYN L

DETECTL | VREF

ACLOL

DCLO L

[( DO2L

E
F

D06 L
| DOSL

| pioL

|DI2L

L | Dl4L

DO5S L
-

| AO1L

A0 L

"DO9L

|[AO3L

A02 L

DIIL

|AOS5L

AO4L

- DI3L

[AO7L

AO6L

|
| PAL

| PARITY |
PIL

DISL

| A09L

+5V

GND

|GND

GND

STACK

BUS G7

PBL

A0S L

BUS G6

AlOL

|AI3L

BUS G6

OUTH

Al2L

BUSGS |

SO H

SACKL

|[AI5L

Al4L

NPRL

|[Al7L

Al6 L

BUS G4
SO H

GND

ClL

BUS G5

BR7 L

BUSG7

SOH

AllL
|

OUTH

| PARITY | BBSYL

GND

+5V

PO L

DO7L

|
M

| DO4L

GND

GND | BUSG4

|GND

GND

|
OUTH

| +20V

BR6L

|[SSYNL

COL

| ¥20V

+20V

|MSYNL

-5V

.
.

CHAPTER 3
,
LOGIC DESCRIPTION

3.1
3.1.1

CORE ARRAY DESCRIPTION
|

General Core Descripticn

The ferrite core memory consists of 16 memory mats (18 for the MM11-DP) arranged in a planar configuration.

Each mat, representing a single bit position of a word, contains 16,384 ferrite cores arranged in a 128 X 128
array. This planar configuration provides a total of 16,384 16-bit word locations (18 for the MM11-DP). Each
core can assume a stable magnetic state corresponding to either logic 1 or logic 0. Even if power is removed from
the memory, the core retains its state until changed by apprepriate control signals.

Each core is threaded by 3 wires, which provide the means for selecting and switching the core. X-axis read /write
windings pass through the cores in each horizontal row; Y-axis read/write windings pass through the cores in

" each vertical row; sense/inhibit windings pass through all the cores in'a given mat.

Figure 3-1 represents a single core with an X winding,a Y winding, and a sense/ inhibit winding passing through
it. If a current of magnitude Im/2 flows in both the X and Y windings in the direction indicated, a magnetic field

is produced in the core. The flux lines of the magnetic field encircle the core in the direction shown by the arrows.
If the direction of current flow is reversed, the magnetic field also reverses direction. This change in flux induces a
|
voltage pulse in the sense winding that can be detected by a sense amplifier.

y SENSE/INHIBIT

11-3552

Core Windings

€]

Figure 3-1

INHIBIT

—_—

11-3553

Figure 3-2

3-1

Core Hysterisis Loop

Figure 3-2 shows a hysterisis loop that relates the magnetic flux in the core to the magnetizing current in the X
and Y windings. The point designated “0’” on the ® axis represents the magnitude and direction of the flux for

logic 0. If current is passed through the X and Y windings in the “write” direction (the direction indicated by the
arrows in Figure 3-1), the magnetic field reverses direction, and the flux assumes the magnitude represented by

point B. When the currents cease, the flux decreases to point “1” and a logic 1 is now stored in the core. To
“read” this logic 1, the magnetizing currents are reversed and the flux assumes the magnitude represented by
point A. When the currents cease, the flux decreases to point 0 and the core now holds logic 0. The hysterisis loop

must be traversed in the direction indicated by the arrows. Thus, if a core has logic 0 stored in it, no significant
change occurs in the magnetic field when the core is read. Figure 3-3 shows waveforms that represent the core
voltage output and the current through the core. If the core is in the logic-1 state, full-select read current (Im) will
produce a core voltage output of approximately 40 mV. A half-select read current (Im /2) also produces an
output voltage, approximately 2 mV (the 0-output waveforms in Figure 3-3 represent the sum of the outputs
from the half-selected core and all the unselected cores); however, the core does not change state and the voltage

output is not detected by the sense amplifiers.

3.1.2

MM11-D Core Array Description
o
|
|
Figure 3-4 illustrates a typical portion of a 16K core memory; X and Y wires pass through each core in the
mat.

The current passing through any one winding
is such that no single winding produces a magnetic field strong
enough to cause a core to change its magnetic state. Only the reinforcing magnetic field, caused by the coincident

-current of both an X and a Y winding, can cause the core located
at the point of intersection to change states. It is

this principle that allows the relatively simple wiring arrangement to select one (and only one) memory core out
of the possible 16,384 contained on each mat. The current passing through either an X or Y winding is referred to

as a half-select current.

A half-select current passing through the X3 Winding from left to right pr»odu.ces~ ‘a magnetic field that tends to

change all cores in that horizontal row from the 1 to O state. The field produced by the current is, however,
insufficient to complete the state transition in any core. Simultaneously passing a half-select current through the

Y2,winding from top to bottom produces the same effect on all cores in that particular vertical row.

Note, however, that both currents pass through only one core which is located at the intersection of the X3 and

Y2 windings. This is the selected core, and the combined current ._fvallue‘s are [sqfficie_nt to change the State of the
core. The arrows in Figure 3-4 show current direction for the read cycle.

In the MM11-D/DP, the X3 windings in all 16 (or 18) mats are connected in series, as are the Y2 windings.
Therefore, whenever a full-select current flows through a selected core on one mat, it also flows through
an
identical core on the other 15 (or 17) mats. The X3-Y2 cores on all mats switch to a logic 0, causing each of
the 16
cores to become one bit of a 16-bit storage cell, or word.

Because of the serial nature of the X-Y windings, a method must be employed to set certain cores to the 0 state;
otherwise, every 16-bit word selected would be all 1s. The method used in the MM11-D /DP is to first clear all

cores to the 0 state by reading. During the write operation, cores on particular mats are inhibited by an inhibit

winding. The inhibited cores remain Os even when identical cores on other mats are set to 1s.

The half-select current for the inhibit lines is supplied by one of two transformers, driven by an inhibit current

driver, which consists of a pair of switches and a current source. The current in the inhibit line flows in the
opposite direction from the write current in all Y lines and cancels out the write current in any Y line. Each mat,

representing one bit position of a word, has an inhibit current driver; thus, selected bits can be inhibited to
produce any combination of binary 1s and Os desired in the 16-bit word. Remember that the inhibit function is

active only during write time. (The inhibit winding interchanges in the Y direction for noise cancellation: this

interchange is shown for illustrative purposes only as occurring between rows X4 and X5 in Figure 3-4. In the

MM11-D, the actual interchange occurs between rows X63 and X64 — see Figure 3-6).

"1" QUTPUT SWITCHES AT THE
CORE TIME CONSTANT AND IS

PRIMARILY DEPENDENT ON

SWITCH FASTER AND GROW AS

AND IS A FUNCTION OF IT AND CURRENT
AMPLITUDE.

"0" OUTPUT OC A ~ OR O g7

RISE TIME IS INCREASED.

READ CURRENT

DOTTED LINES SHOW HOW
OUTPUTS WOULD BEHAVE
WITH DIFFERENT RISE TIMES

11-00888

* THE @-OUTPUT WAVEFORMS REPRESENT THE SUM

OF THE OUTPUTS FROM THE SELECTED ANTI- COINCIDENT
CORE AND ALL UNSELECTED CORES

Figure 3-3

Core Current/Voltage Output Relationship

The sense/inhibit lines are also used to read out information in a selected 16-bit memory cell. The specific core is

selected at read time in the same manner as during the write cycle, with one notable exception: the X and Y

currents are in the opposite direction than they are for the write operation. These opposite half-select currents
cause all cores previously set to 1 to change to 0; cores previously set to 0 are not affected. Whenever the core

changes from 1 to 0, the flux change induces a voltage in the sense winding of that mat. This voltage is detected

and amplified by a sense amplifier. The amplifier output is strobed into the data register for eventual transfer to
-

the Unibus.

With a core array of 128 X 128, the 128 X windings and 128 Y windings can be used to select any one of 16,384

cores on a mat. However, for space economy, the MM11-D/DP makes use of the principle of coincident and
anti-coincident cores; hence, although 128 X windings are used, only 64 Y windings link the cores in the vertical
direction.

3-3

INHIBIT CURRENT DRIVER\.,‘
o

—

FERRITE
N, CORES

—

SELECTED

/\/CORE

Ims2 X3

—

SENSE/INHIBIT
LINES

TO SENSE AMPLIFIER
AND SENSE TEF\’MINATION.

Figure 3-4

3-Wire Configuration

11-1790

Yea

Yz ————— ']

"
|

|
|

Yo7 —— —

B PU

_Y66

|
I
|

I
|

X
I

127

LOWER HALF
Figure 3-5

UPPER HALF
11-3554

MMI11-D Mat

Figure 3-5 illustrates a portion of a mat in the MM11-D /DP. The mat is divided, for descriptive purposes only,
into an upper and a lower half. The cores in column Y0 and those in column Y64 are linked by the same winding;
in
the same is true for columns Y1 and Y65, Y2 and Y 66, etc. If magnetizing currents flow in the X1 winding andthe
However,
B.
core
and
A
core
through
pass
currents
both
the Y1-Y65 winding in the directions indicated,
The currents in
currents reinforce each other— they are coincident - only in core A; hence, this core is selected.
core B
reversed,
is
winding
5
6
Y1-Y
the
in
current
the
If
selected.
not
is
core B are anti-coincident; thus, core B
becomes the coincident core and is selected, while A is not.

o
e
et m—
e
e

T
-

/ oo/

oo, oty
otts

AN
AN

A
e

\
-

LOWER

HALF

UPPER HALF

11-3555

Figure 3-6

Mat Sense/Inhibit Windings

Consider the X winding current to be a write current. Thus, current
in the Y winding can flow in either direction
during a write operation. If the X winding current is reversed,
to flow in the read direction,
Y winding current
can again flow in either direction. Consequently, Y axis current is not termed
read or write current in the MM1 1-

D logic description. Rather, it is defined in terms of its source in the

discussed subsequently.

Y Driver/Switch circuit; these definitions are
~

Because it is possible to select either of two cores in a mat during
both a read and a write operation, two

sense/inhibit windings are required for each mat, one for the upper

half, another for the lower half. Each winding
d in Figure 3-6 (for clarity, X and Y windings are

not shown; the sense/inhibit winding interchanges between rows

3-6

X63 and X64 for noise cancellation).

N ——

passes through all the cores in its half of the mat, as illustrate

3.2

MMI11-D BLOCK DIAGRAM

A functional block diagram of the MM11-D

is shown in Figure 3-7. The blocks are described brlefly to relate

each to the others; each blockis describedin detailin a subsequent section.
Voltage Monitor Circuit

The Voltage Monitor circuit checks the status of the BUS DCLO L signal and the +5 Vdc supply voltage. If BUS
DCLO L is negated, the circuit generates MSYN H when BUS MSYN L is asserted on the Unibus, and provides
a voltage (+20SW) that is used in the core selection process. If the +5 Vdc voltage drops below a minimum

value, the +20SW voltage is removed to prevent unwanted switching of core states.
Address Decoding Logic

Each Unibus address thatis placed on the bus by the master is examined by the Address Decoding logic; if the

address 1s one that has been assigned to the MM11-D, the logic decodes bits A<17:11> L and generates the
BANK SEL H signal. This signal allows MSYN to start the timing chainin the Read Control logic and a read or
write operation is carried out.

Control Bit Logic
The bus master places Control Bit information on the Unibus along W1th the address data. The Control B1t
signals - AO L, COL, and CI L - specify the type of data transfer thatis to be carried out. The Control Bit logic
decodes these three signals and asserts WRITE BYTE 0 L and WRITE BYTE 1 L in various combinations.

These two signals direct the Read Control logic to assert the signals needed for the specified type of transfer.

Table 3-1 lists the type of Unibus data transfers that can be made and relates the control bit logic levels to the
data transfers.

Memory Address Register (MAR) Logic
While address bits A<17:11> L are being decoded by the Address Decoding logic, bits A<14:01> L are applled
to the MAR logic. If the BANK SEL H

signalis asserted, the Read Control logic will generate the LOCK MAR
I L and LOCK MAR 2 L signals; these signals will latch the 15 address bits into the MAR. The MAR outputs

are applied to the X and Y Driver/Switch logic to select the appropriate cores for the data transfer.
Read Control Logic

During the read half of a t1m1ng cycle, the Read Control loglc generates 51gnal(s) that:
Turn on the read current generators in the Current Sources circuit;

Control the X and Y driver/switches so that read current flows through the selected windings in the proper
direction;

Conditions the Sense/Inhibit circuit for an input or output data transfer;

Latches the memory address into the MAR;
“Starts the Write Control logic.

3-7

*5VDC

BUS MSYN H

VOLTAGE
| MONITOR

BUS DCLO L

| circulT

LOCK MAR H

MSYN H

\ .__|

{

READ

+20 SW

|OUTPUT EN L

CONTROL | STROBE 0, 1H

LOGIC | ¢cLr MDR L

BUS ABi L

BANK SEL H

INPUT MDR H

LOGIC

X127

|
NOT BUSY H

—»

{

X READ SINK T L
X READ I

BUS A® L

CONTROL [wriTE

BUS CO L

BIT

LOGIC

BUS C1 L

cn9

|BYTE o, 1L

R
SOURCE
T H

o CIRCUIT

« READ 16

SRT WR L
& NOT BUSY H

—# SSYN H

WRITE

CONTROL
P

—

> LOCK
}——% NOT

INH RT L

INH

7O,

CURRENT

MAR
BUSY

128 X 128

DRIVER/

CORES

SWITCH

CIRCUIT

1, 2L

BUS D (15:90)
L

Y63
T

SENSE/

INHIBIT

CIRCUIT

32 SENSE/

INHIBIT LINES

CIRCUIT Iy piopE END 16

T L

X WRITE SOURCE T L
X WRITE I SOURCE T H

AD7TH-AI3H, A13L
‘

WRITE SINK

Sing

X0 o MODULE
I

SOURCES | Y COMMON END IG

SSYN H

X y WRITE 16G

= LOCK MAR 1, 2L

X READ SOURCE T L

BUS SSYN L

.| gF\:IIIYrECF:-l/

DECODING

UNIBUS

ADDRESS

BUS A(17:11)L,

‘

|
|
|

——

Y STACK CHG

—
®

STACK CHG -

STACK

CHG CKTS
P/0 H222

BUS A (14:01) L

AQ7H-A13H,
A13L

ADDRESS

AQO1H-AGEH|

A14BOH

LOGIC

X DR/SW

LOGIC)

LOCK MAR 1,2 L

SOURCE T L

SINK

'Y DIODE

SOURCE

'Y COMMON

Y DIODE

A14BOL

(TO

mWp

MEMORY

T L

SINK

T L
T L

NOTE:
Logic is part of

G652

Module unless noted.
11-3571

Figure 3-7

MM 11-D Block Diagram

3-8

Table 3-1

Unibus Data Transfers
Control Bit Logic Level

Type
of Transfer
Data in (DATI)

COL

CiL

AOL

Operation Effected

Data transfer from memory to master:

memory performsread/restore
operation.

Data In Pause {(DATIP)

Normally different from DATI, but
in DATIP mode the MM11-D

performs a DATI operation.

Data Out (DATO)

Data Out, Byte (DATOB)

Data transfer from master to memory.

Data transfer from master to memory;

the 8 most significant data bits are

transferred via the D<<15:08> lines.

- Data transfer from master to memory;
the 8 least significant data bits are
transferred via the D<Q7:00> lines.

Note: X represents “don’t care” state.

Write Control Logic
During the write half of a timing cycle, the Write Control logic generates signal(s) that:
Turn on the write current generators in the Current Sources circuit;

Control the X and Y Driver/Switches so that write current flows through the selected windings in the
proper direction;

Latches the memory address into the MAR;
Enables the Sense/Inhibit circuit to generate an inhibit current, if necessary.
Current Sources Circuit

The Current Sources circuit contains the X and Y current generators, which are turned on by control signals
from the Read and Write Control logic. The Current Sources circuit generates control signals that direct current

through the Y windings in the direction that reflects the selected core’s location in the mat. (Because the Y
winding passes through 2 cores, one in the upper-half of the mat, the other in the lower-half, coincident current in
one core is anti-coincident current in the other core; thus, current can flow through the winding in either direction during each half of the timing cycle.)
X Driver/Switch Circuit

The X Driver/Switch circuit decodes address bits a<13:07 to select one of the 128 X windings. Read and write

currents supplied by the Current Sources circuit are applied to the selected winding and flow (in the direction
specified by the Read and Write Control logic signals) from the X Driver/Switch circuit, through the 128 X
16(18) cores on the selected winding, and back to the Driver/Switch circuit.

3-9

Y Driver/Switch Circuit

.
|
The Y Driver/Switch circuit decodes address bitsA <06:01> to select one of 64 Y

windings. Read and write

currents are applied to the winding and flow through the 256 X 16(18) cores and
back to the circuit.

Sense/Inhibit Circuit
|
The Sense/Inhibit circuit is an interface between the Unibus D<15:00> lines and the stack cores. During

half of a memory-read timing cycle (DATI), differential amplifiers sense the output
of the

the read

selected cores (1 core

on each of the 16 mats). Logic levels representing the core outputs are strobed into
a Memory Data Register
(MDR) and gated on the D<15:00> lines. During the write half of the timing
cycle the cores are restored to their
original states; selected inhibit drivers might have to be turned on to accomplish the
restoration correctly. In a
~memory-write cycle (DATO), the cores are also sensed, but the differential amplifiers
are not strobed during the
read half of the cycle. Instead, data on the D<15:00> lines is gated into the
MDR. During the write half of the
cycle, the data in the MDR is written into the selected cores: once again, selected inhibit
drivers might have to be
turned on to accomplish the write operation (a DATOB operation is performed in the
same way as the DATO
for the selected byte; however, the unselected byte is handled as a simple read-restor
e operation).

Stack Charge Circuits
The Stack Charge circuits - one for the X diode matrix, one for the Y diode

matrix - are located on the stack
module. The circuits help the stack capacitance to recover, shorten the rise time of the stack
current, and reduce
unwanted currents in the unselected lines associated with the selected driver.

3.3

VOLTAGE MONITOR CIRCUIT

The Voltage Monitor circuit, shown in Figure 3-8, monitors the BUS DCLO L signal and the +5

V supply line. If
the +5 V supply drops below a specified value, transistor Q1 is turned on, bringing the +20SW
voltage near
ground. If BUS DCLO L goes low, indicating a problem in the dc power supply,
Q1 is again turned on. In
addition, after the on-going timing cycle is completed, the circuit prevents BUS MSYN
L from asserting MSYN
H; thus, no new timing cycle can begin until the system is powered again.

jf—q

525\ 14

R@ H

E26

BUS

MSYN L

+52

E36

+20V

E26

—O

}——MSYN

o— +205W

N
o

MAR H

E26

H—MA———A——

LOCK

BUS DCLO L—O

11-3556

Figure 3-8

Voltage Monitor Circuit

3-10

Figure 3-9 is a timing diagram that illustrates how BUS MSYN L is locked out and +20SW is turned off when
BUS DCLO L is asserted on the Unibus. The BUS DCLO L signal is assumed to be asserted after the memory
cycle has begun. Because both RO H and LOCK MAR H have been asserted by the Read Control logic, the

timing cycle will proceed to completion. When LOCK MAR H goes low, however, NOR gate E26 (output pin 6)

is latched high. This level disables NAND gate E36, preventing BUS MSYN L from generating MSYN H. Note

that if BUS DCLO L returns high before LOCK MAR H is negated, BUS MSYN L is not locked out and the
+20SW voltage is not cut off.

The circuit shuts off the +20SW voltage to prevent any of the cores from accidently changing state when BUS

DCLO L is asserted because power is removed. Such an accidental change of state might occur when the +5V
power supply is turning off and spurious timing signals are generated. The +5 V line is monitored so that, even if
the BUS DCLO L signal fails, protection
is afforded to circuit components, which otherwise might be subjected

3.4

3.4.1

to excessive power dissipation due to spurious control signals.
ADDRESS DECODING LOGIC

Memory Organization and Addressing Conventions

Prior to a detailed discussion of the address decodmg logic, PDP-11 memory organization and addressing conventions should be con51dered

‘

RO H

200

400

600

800

1000ns

I‘

~ LOCK MAR H

—

]

BUS DCLO L

E25-14

E25-2 __-1

\\M -

E26-3

_
|

—

| 1
[

|
.

4A[

E26-8

**1_45'—___—_

E25-3

+20 SW(=+20)

BUS MSYN L

MSYN H

Eée-11
E26-6

‘

1
11-3578

Figure 3-9

Voltage Monitor Timing (DATI Operation)

3-11

Memory is organized into 16-bit words, each consisting of two 8-bit bytes. The bytes are identified as low

high, as shown below.

{

l‘

HIGH BYTE
—

]

MSB

]

and

LOW BYTE
|

DATA

BITS D<I5:00>

LSB

11-1174

Each byte is addressable and has its own address location; low bytes are even numbered -

high bytes are odd
numbered. Words are addressed at even-numbered locations only; the high (odd) byte is automatically
included.

For example, a 16K word memory has 16,384 words or 32,768 bytes; therefore, 32,768 locations are

assigned.

The address locations are specified as 6-digit octal numbers. The 32,768 locations
are designated 000000 077777, as shown in Figure 3-10.
o
The address decoding logic responds to the binary equivalent of the octal address. The binary
equivalent

017772 is shown below as an example.

0]
0

(13

0O0]O0]O

|12 | 11

|10

(09|08

|07

BYTE

SELECTION

|06|05|04]|03

|02]|01

|00

O | BINARY

-3

\\—‘“/

ADDRESS BITS A<17:00>
17116 [ 15[

BIT POSITION

OCTAL

WORD
=173

Each memory bank requires its own unique device address. F or example,

assume that a system contains three
16K memory banks, as shown in Figure 3-11. The device selector for the 16K
non-interleaved memory decodes
five address lines, A(17:13). Examination of the binary states of these lines for
the three memory banks shows
that the changes in the states of bits A15and A16 allow the selection
of a unique combination for each bank. The

combination, which is the device address, is hardware-selected by jumpers in the

[15

8|7

-—

16 BIT WORD——»

l
HIGH BYTE

000001

LOW BYTE

000000

000003

000002

000005

000004

077773

077775

077777

o77772
077774

077776

11-1789

Figure 3-10 Memory Organization
3-12

device selector.

1ST ADDRESS|
000000

077777

BANK 1

16k WORDs | BANK 14
LAST ADDRESS|

0
f

1ST ADDRESS|
100000

177777

BANK

—

1
2

16Kk WORDS | BANK 2¢
LAST ADDRESS|

O©

)

1ST ADDRESS|

200000
277777

LAST ADDRESs|

3
16K WORDS | BANK 3{

7
11-1788

Figure 3-11

3.4.2

Address Assignments for Three Banks of 16K Words Each

Address Selection

The Unibus address space assigned to the MM11-D depends on what address is selected as the MM11 starting

address. This starting address can be any one that begins an 8K block of addresses; for example, 000000s (0K),
0400005 (8K), 1400005 (24K). The starting address is assigned by inserting jumper wires at specified locations in
the Address Decoding logic (Figure 3-12). When the starting address appears on the Unibus address bus, the
Address Decoding logic asserts the BANK SEL H signal. If both the Unibus and the MM11 timing logic are not »
busy, the BANK SEL H signal enables BUS MSYN L to start the timing chain.

The BANK SEL H signal can be asserted when either NAND gate E27 or E28 is enabled. However, during

normal operation, wherein the uppermost 4K of Unibus address space is reserved for peripheral devices, there is
no jumper wire installed at location W8; consequently, only NAND gate E28 need be considered. This gate is
‘enabled whenever an address from the assigned 16K block appears on the Unibus address lines. The starting
address of this block is determined by the arrangement of jumpers at locations W1 - W4, Jumpers are inserted at
these four locations in such a way that any assigned address causes the outputs from adder E6 to be high. Two of
these outputs, 3.3 and 3_4, go directly to NAND gate E28. A third, 3_2, goes to multiplexer E16; during nonto
interleaved operation, the 32 output is gated through the multiplexer to NAND gate E28. The fourth input
the gate is from NAND gate E7, which is enabled only for addresses within the 4K reserved area.,
Table 3-2 lists the possible starting address for the MM11-D memory, the ending address (plus 1) corresponding
to each starting address, and the disposition ofjumper wires at locations W1 - W4. For example, an MM11-D
memory can be assigned address space beginning at address 0400005 (8K) if a jumper is inserted at location W3,
The ending address will be 1377775 (24K - 1). Each addressin this 16K block will cause NAND gate E28 to be
enabled, resultingin the assertion of BANK SEL H.

3-13

BUS A7 L —O

BUS A16 L —+—O

A7 H

TM\

A16 H

BUS A15 L —+—O|

TM\

BUS A14 L —4—0O

TM\

A1S H

+3V

E27

RAW

—

A14 H

‘

W8 o

__q_/
BUS A13 L —+—of

RAW A13
H

BUS A12 L —+—O

RAW A12 H

RAW A1 H _

)

BUS A1l L —+—O
|
L

E27

-o

|
B4

‘,

¥
z2
Ee

—l—
‘

[

]

74153

sTBo, 1
DO

S1|S@|fn
fQ "

RAW AQ@1 H

__l
=

—

|Addresses Assigned

LO|LO|An

RAW AQ1 L

“":L
_o
Al

7483

‘

BANK SEL H

A— +3Y

%
V"‘A’Q—‘

:B_

BUS AQ! L ——O

LO|HI

74153
E16

B1
A1
51

A 32 K- BLOCK

ODD ADDRESSES IN

|HTLOICn | A 32k — BLOCK

ALL

IN
Hi [HI |Dn A 16 ADDRESSES
K - BLOCK |

+ 3V —Nv\ri
w5

{Bn

‘
'
EVEN ADDRESSES IN

LOGIC

)

+3V

1 -3557

Figure 3-12

Address Decoding Logic

3-14

Table 3-2
Jumper Assignments for MM11-D Starting Addresses

Starting

Ending

Address

Address +1

24K

16K

ouT

OuT

OUT

16K

32K

OuUT

ouT

24K

40K

OouT

48K
56K

OUT
OUT

ouT

OUT

32K
40K

48K

IN
IN

OUT
IN

IN
OUT

64K

OUT

56K

72K

OUT

OouT

OuT

- 64K

80K

OuUT

OUT

72K

88K

OuT

OUT

96K

OuT

104K

OUT

120K

124K

80K

88K

96K

112K

104K

112K

OuT

OUT

Note: OUT =logic
1, IN
= logic
0.

~ As mentioned earlier, in normal operatio‘n' the upper 4K of memory addresses is reserved for peripheral devices
on the Unibus. In special applications, where the number of peripheral devices is small, some of these reserved
addresses can be used by the MM11-D. Thus, if a jumper is inserted at location W8, Unibus addresses from 124K

to 126K-1 (7600005 — 767777s) will cause NAND gate E27 to be enabled and BANK SEL H will be asserted. If a jumper is inserted at W7, in addition to one at W8, addresses from 124K to 127K-1 (7600005
- 7740005) will be

assigned to the MMI11. Note that for systems without Memory Management the useful address space can be
extended from 28K to 30K-1, or 31K-1.
NOTE

If use of the reserved I/0O page of addresses is being con-

sidered, check carefully to ensure that, first, no peripheral
et

devices (including bootstrap ROMs) are assigned any of

the reserved addresses, and second, all DEC software is
compatible with the reduced peripheral address space.
Two MMI11-D memories can be interleaved, i.e., one memory can be assigned the odd addresses within a 32K

block of addresses, while the other can be assigned the even addresses within the same block. Interleaving is

accomplished by inserting jumpers at locations W5 and W6 of each memory’s Address Decoding logic and
‘assigning each memory the same starting address (the starting address for interleaved memories is assigned
differently thanis the starting address for a single memory; Table 3-3 relates interleaved startmg addresses and
the disposition ofjumpers at locations W1 - W4). For example: to interleave two memories so that they cover

Unibus address space from 0K
- 32K, first insert a jumper at locations W3 and W4 of each memory’s Address
Decoding logic, thereby setting the starting address at OK; then, insert jumpers at locations W5 and W6 to assign

one memory the even addresses (W5in, W6 out) and the other memory the odd addresses (W5 out, W6 in). Any

addressin the assigned 32K block causes adder outputs }"3 and Y "4 to be high. However, the 32 output is not
gated through multiplexer E16 to NAND gate E28; instead, the fO output of the multiplexer represents the state

of the BUS A0l L signal. Thus, an odd address (BUS AOl L is asserted) causes fO of the odd-address-memory
multiplexer to be high; BANK SEL H is asserted by this memory. Alternately, an even address (BUS AOI L is
negated) causes fO of the even-address-memory multiplexer to be high and BANK SEL H is asserted by this
memory.

Table 3-3
Jumper Assignments for MM11-D Starting Addresses

(Interleaved-Memory Operation)

3.5

32K

ouT

40K

OuUT

ouT

16K

48K

OuUT

24K

56K

OUT

32K

64K

OUT

40K

72K

»
|

OouT

OUT

OuUT

48K

80K

OUT

ouT

56K

88K

ouT

64K

96K

OUT

72K

104K

ouT

IN
OuT

IN
-

Ending

Address +1

0OuUT

80K

112K

OouT

88K

120K

OuT

96K

124K

Starting

Address

CONTROL BIT LOGIC

The Control Bit logic is shown in Figure 3-13. Table 3-4 relates the control bits and the write byte bits to the data
transfer modes, viz., DATI, DATO, and DATOB (DATIP and DATI are the same in the MM 1-D).

Table 3-4
Operating Mode Selection
Mode

BUS COL

BUS C1L

DATI

HIGH

DATIP

LOW

HIGH

DATO

HIGH

DATOB

LOW

LOW
LOW

BUS AQOL

WRITE BYTE OL

- -

HIGH

- -

HIGH

LOW

HIGH

LOW

HIGH

HIGH
LOW

3.6

WRITE BYTE 1L

|
|

MAR LOGIC

The logic shown in Figure 3-14 latches the memory address throughout the memory timing cycle. Address bits
A0l L - A13 L and A13 H are used to select the addressed locations. Bits A14 BO/1 H and A14 BO/1 L are used

throughout the

MM 11-D logic to specify the upper and lower halves of the mats.

Note that the signal LEAST BIT H is derived from either BUS A0l L or BUS A15 L. In non-interleaved
operation, LEAST BIT H reflects the state of BUS A01 L. However, during interleaved-memory operation, BUS
AOl L is used to generate BANK SEL H; consequently, it cannot be used to specify the 14-bit address. In this

case, BUS A15 L is selected to generate LEAST BIT H.

3-16

rE38 _‘ | I f—Mzs"/
8641
l
BUS A L

°[>jl

BUS CI L

7475

E37
] E37
N

S g

— DI

E42 N
(1)

)
X

. Do‘

BUS C@ L

. 8

IRAW ' ADH|

E37

WRITE

~BYTE 1L

WRITE
EgL
RO (N ——RYT
2
ENB1.

IRAW CO@ H

LOCK MAR2 L

LRAW C1 H
i

PARITY _[D‘ |

DETECT L

SSYN H

—

BUS SSYN L

‘

INT SSYN L
11-3568

Figure 3-13

3.7

3.7.1

Control Bit Logic

CONTROL LOGIC

Read Control Loglc

The Read Control logic is shownin Figure 3-15. Central to the logicis a 250-ns delay line, E9. A positive edge
applied to the input travels down the delay line; when the edge appears at the output, 250 ns later, it is returned to
the input circuit, causing the input signal to go low. Hence, a 250 ns positive pulseis available at each output tap,

the taps appearing at 25 ns intervals along the line.

When the Address Decoding loglc asserts BANK SEL H, the read control tlmmg begins, providing that four
conditions are met:

The BUS MSYN Lsignal must be asserted

The MSYN H signal must have been generated by the Voltage Monitor c1rcu1t indicating that the dc
voitages are within the specified tolerance

The NOT BUSY H signal must be asserted, indicating that the memory is not currently executing a

SSYN L must be negated, indicating that the SSYN flip-flop is clear.

memory operation

3-17

slv

'STBQ,!
Dt

E16

LEAST

+3v-v\~i

L——va—'+3v

WST

BUS A¢g8 L

BUS A@6 L

BUS A@5 L

BUS A@7 L

BUS A@9 L

BUS A19

BUS A14 L

BUS A13 L

LO
LO

CHI
HI

A@1 H

R@ (1)

AQ4 H

R2 (1)

A@3 H

R3 (1)

A@2 H

7475.
E30 Rrgu)

~AQ8
H

R1(1)

— A@6
H

R2(1)

A@5 H

R3(1)

AQTH

ENBI

ENB2

LOCK MARI1L

LOCK

ENBZ2

]

7475

E41

Rrgu)

R1(1)

R2(1)

R3(1)

ENB1

ENB2

7475

BUS A1l L

Rri)

ENB1

BUS A12 L

E39

IS it

BUS A@2

VAV,

BUS A@3 L

IWG

7475

BUS Ag4 L

BIT H

o s

BUS AI5 L

74153

E42

BDa
BDa

ioid

BUS A1 L

A14B0Q H

A14B1 H

R2(1)

R2(@)

R3(1)

—A13
H

R3(@)

A13
L

ENB1

ENBZ2

MAR2
L

LO | c1
HI | DI
11-3559

Figure 3-14

MAR Logic

3-18

BANK SEL
NOT

H—

MSYN

BUSY

H-——

SSYN

E28

+5V

SRT RDL

RDL

+3V

?—5@

\13

50 100 200
/

SRT WR

EV7

X READ SOURCE T L
{,

+5V
|

Pe
>

X READ SINK T L

—T-

wawiown

X READ I SOURCE TH

)

STROBE EN L

DO—OD

r’ T

‘

E10

74121

|
.

CLR MDR L

BYTE @ L

1 po—

o—

1)}

WRITE

[

STB
I L

‘

J180-2

. Do—-[j E32
,

STROBE @ H

INPUT MDR @ H

E18

WRITE

BYTE 1 L

lJ‘i___./

—D

SSYN

@O—LOCK MAR 1 L

Do—fi E32

STROBE 1 H

|
E58 1 |——SSYN
H

,»

;

INPUT MDR 1 H

}

D— SSYN L
ol

_D— LOCK MAR 2 L
ES58
NOT BUSY

EN
C

MSYN

10— OUTPUT EN L

—1D

LOCK MAR H

|
00—

H
11-3560

Figure 3-15

Read Control Logic

3-19

With these conditions satisfied, the BANK SEL H signal enables

Read). Transistor Q14 is turned on and RDL IN H (Read Delay

NAND gate E28, asserting SRT RD L (Start

Line In) goes high. In approximately 250 ns, the

delay line output, pin 13, goes high; the output signal is returned
to gate E19, disabling it. Thus, Q14 turns off
and the delay line input goes low.

The Read Control timing signals are derived from a number of

gates and flip-flops that are contolled by the
various delay line taps. Table 3-5 lists the significant signals by name and
briefly describes the function of each
signal. Figure 3-16 is a timing diagram that relates not only the Read Control signals,
but also the Write Control
signals, which are described in the following section. The timing is shown completely
for a DATI operation. For
a DATO operation, most of the signals are the same as the DATI; only
the exceptions are

heading DATO. A DATOB operation differs from a DATO only in the WRITE BYTE

and INPUT MDR 0/1 H signals; these differences are explained in Table
3-5.
Note that the timing of the STROBE 0/1 H signals is variable. These signals
one-shot (the trailing edge of the one-shot output asserts the STROBE 0/1

shown above the

0/1L, STROBE 0/1 H,

are generated, in part, by the STB
H signals). The one-shot output is

controlled by a current generator, Q5, which can be varied for margining of
the memory by connecting J180-2 to
ground or to +5 V. Jumpers can be inserted at locations W9, W10, and W11 to compensate
for stack differences
and, hence, to achieve the coptimum STB one-shot output pulse width. When the
optimum pulse width is

achieved, the STROBE 0 H and/or STROBE | H signals will be generated at such a
time that they strobe the

sense amplifiers very near the maximum of the voltage output. The Jumpers are inserted

the factory and must not be tampered with in the field,

3.7.2

at W9, W10, and W1l at

Write Control Logic

The Write Control logic is shown in Figure 3-17. This logic also features a 250 ns delay

line, E31, that operates
like E9 of the Read Control logic. The SRT WR L (Start Write) signal begins the write-signal
timing; the write
signals are derived from a number of gates that are controlled by the various delay
line taps. Table 3-6 lists the
significant signals by name and briefly describes the function of each signal.
3.8

CURRENT SOURCES CIRCUIT
The circuit shown in Figure 3-18 contains the X and Y current generators

; in addition, the circuit generates the Y
winding Driver/Switch timing signals. The Driver /Switch control signals
turn on the appropriate drivers and
switches, enabling read and write currents to flow in the directions that produce
coincidence in the selected cores.
In the X windings, read currents flow in one direction, write currents
flow in the opposite direction. However,
because the memory has coincident and anti-coincident cores, the relative
direction of the Y currents must be
reversed to select the upper 8K of addresses. This reversal of Y current
is controlled by multiplexer E72, a 74157
IC. The X read and write timing signals are multiplexed by signal
A14B0 H to turn on Y currents that are
coincident in ““A” cores (lower 8K addresses) when A14BO0 H is not asserted,
and to turn on Y currents that are
coincident in ““B” cores (upper 8K addresses) when A 14B0 H is asserted.

Figure 3-19 illustrates this concept. Figure 3-19(a) represents two cores, A and B,
with both an X anda Y
winding passing through each; Figure 3-19(b) depicts relative polarities of the currents
in the two windings. If the
arrows shown in Figure 3-19(a) represent positive read currents Ix and Iy, there will be coincidence
of currents in
core A and anti-coincidence in core B. Write currents have the opposite polarity for X and Y
and occur later.
To address the upper 8K of memory addresses, the read and write timing is
interchanged by the multiplexer. At
read time, the source-and-sink combination that had previously been turned on
to write into core A is now
turned on to read core B. The relative Y current polarities (Iy) are shown
as dotted lines in Figure 3-19(b). Once
again, write currents for X and Y are opposite in direction from the read currents
for the selected address, and
occur later.
Two identical sense/inhibit windings carry the inhibit current when data zeros are

being written. The reversal of

relative polarity indicated for INH B in 3-19(b) is determined by core stack wiring connections

memory system,

internal to the

Read Control Signals
~ Function

Signal Name

These two signals turn on the selected driver/switch pair in the X

X READ SOURCE T L

~ Driver/Switch circuit, enabling read current to flow thru the selected

XREADSINKTL

X-winding; in the Current Sources circuit they help generate the Y

- Driver/Switch control 31gnals

X READISOURCETH

Turns on the X read current generator in the Current Sources circuit; the X
read current generator output is named X READ I G Turns on the STB

shot in the Read Contlol Signal logic.
STROBEENL

Instrumental in generating the STROBE 0/1 H signals; when STROBE EN
L
is high, the STB 1-shot output and the WRITE BYTE 0/1 L signals will assert

either, both, or neither of the STROBE 0/1 H signals, depending on the type
of data transfer. The trailing edge of STROBE EN H is used to terminate

STROBE 0/1 H.
STROBE O H

These signals strobe the output of the sense amplifier in the Sense/Inhibit

STROBE 1 H

circuit into the Memory Data Register (MDR); STROBE 0 H is used with the
8 least significant data bits (0—7), while STROBE 1 H is used with the 8 most

significant (8—15). For a DATI operation both signals are generated;
for a

DATO neither is generated, while for a DATOB one or the other is asserted

depending on which data byte is to be simply read and restored.

CLRMDRL

(Clear Memory Data Register) — ThiS'Signal is applied to the MDR at the
beginning of each timing cycle. The signal clears the MDR for a DATI
operation, setting the internal data bus (DATA XX H) to logic 0; for a DATO
or DATOB operation, the CLR MDR L signalis over-ridden by the data

gated to the MDR from the Umbus data lines.

These two signals gate data from the Unibus into the MDR; INPUT MDR 0 H

INPUT MDROH

is used with data bits 0—7, while INPUT MDR 1 H is used with bits 8—135.

INPUT MDR | H

For a DATI operation neither signalis asserted; for a DATO, both are

asserted, while for a DATOB one or the other, dependmg on which data byte
OUTPUTEN L

isto be wrltten s generated

When this signalis asserted during a DATI operation, the output from the
MDRis gated onto the Umbus D<1 5:00> lines,

LOCKMAR 1L

(Lock Memory Address Register) — These signals are applied to the MAR in

LOCK MAR2 L

the MAR logic. When the address is one that has been assigned to the nemory,
these signals latch the address on the A<14:01> lines into the MAR. the
address remains in the register throughout the timing cycle until the signals
are negated.

SRT RD L

100

200

700

800

900ns

]

[

MDR O/1 H

BYTE

O/t

X READ SOURCE TL |

XREADSIN.KTL_IA_‘k
Lock MAR /2L

—
|

—

OUTPUT EN L

|8
—|—

SSYN.F/F-CLK .
|

STROBE 0/1 H

BUS MSYN-L

| BU»S»SSYN}‘_V

]

‘_ |

XREAD-[SOURCETH

_ v

STROBE EN L

LOCK MARH |

600

- |

NOT BUSY
H
|

WRITE

500

ROL INH _|

INPUT

400

R H |

CLR MDR
L

300

SRT WR L

W@ H.-

WDL IN

.XWRI;FE"S‘INK"FL
X WRITE [

‘

SOURCE T H

"X STACK CHG H
X WRITE

SOURCE TL

INH T@/ T1L

INH RT L~

DATI

WRITE

BYTE

O/1

STROBE O/1 H

INPUT MDR O/t H [
_
]
SSYN F/FCLK

SSYNH

[
1

BUS SSYN L

BUS MSYN
L

OUTPUT EN L

|
|

DATO
11-3561

Figure 3-16

Read/Write Timing (DATI and DATO)

3-22

WDL
+3V

E17-6

SRT WR

E19

E 31

150

200/

Q15

ofelo/elcBilolol

E9-13
—

+5V

INH

T@ L

INH Tt L

WRITE SINK T L

X WRITE I SOURCE

STACK

CHG H

WRITE

SOURCE

INH

RT L

LOCK MAR H

E29

E57

LOCK

MAR 1L

LOCK

MAR 2 L

NOT BUSY H
11-3562

Figure 3-17

Write Control Logic

3-23

'
|

J>c

X WRITE SINK
TL

X READ SOURCE TL

{82

74157

——

;—JB1

DIODE END T H

N
T

o
fol—Y COMMON SOURCE T L

STB

Y-COMMON END I.G,

+20
l
%

{

\4
,

|
N

HI | B@ | B1 |B2 | B3

BO
H

74157

X~READ I.G.

SQJf@Ifi[lef?)

Q10

Y DIODE SINK TL

B@
514

COMMON
" YI SOURCE
{{::>>l—-END
TH

+20

Y1 SOURCE

E72

Q13

Q03

:
fol—Y DIODE SOURCE T L

A14

Y COMMON SINKTL

AAA——

‘

X WRITE I SOURCE T H

STACK Vger

+20

;

X READ I SOURCE T H

X WRITE SOURCE TL

Q12

[

+20

~X-WRITE I.G.

Q11

HI IS LOGIC 1

'A%

LO | AO | A1 | A2 | A3

Y-DIODE END I.G.

;

Figure 3-18

Current Sources Circuit

3-24

11-3563

| l-éf.—ONE MEMORY CYCLE

|
|

—

|
X

’

[

-—

l WRITE l

—

“EAD

READ A

| WRITE B |

}

" INHA

LOWER HALF: UPPER HALF

INH B

] -

b wm e em w—m

11-3564

Figure 3-:1.9 “Phase Selection

Table 3 6

- Write Contrdl Signals — Name and Function

Signal Name

X WRITE SOURCE T L
X WRITE SINK T L

X WRITE[ SOURCE T H
INHRTL

Function

- These two signais turn on the selected driver/switch pair in the X

Driver/Switch circuit, enabling write current to flow through the selected

- X winding;in the Current Sources circuit they help generate the Y .
Driver/ SW1tch control signals.

Turns on the X write current generator in the Current Sources circuit; the X

write current generator output is named X WRITE L.G.

(Inhibit Rise Time) — Whenever a logic O must be written into a selected
core, the INH RT L signal conditions the Inhibit logic so that the current in
the Inhibit winding exhibits the needed characteristics.

INHTI L

(Inhibit Time) — These signals turn on the inhibit drivers in the Inhibit
circuit, enabling current to begin flowing in the Inhibit winding. INH TO L
is used with bits 0—7, while INH T1 L is used with bits 8—15,

X STACK CHG
H

on the Stack Charge circuit associated with the X diode matrix.
Turns

LOCKMAR1L .

See Table 3-5.

INHTO L

LOCKMAR 2L

325

Table 3-7 indicates which X timing signal is transmitted to the Y selection circuitry
via multiplexer E72. For
example, when A14B0 H is low, indicating the addressed word is in the lower-half
of the memory, Y read current
flows in the selected Y winding from the common source to the diode sink. Write
current for this address flows
from the diode source to the common sink (common and diode refer to the common
and diode sides of the core
stack; the meaning will become clearer in Paragraph 3.10). If the memory address is in
the upper 8K of addresses
(A14BO H is high) the timing signals are interchanged for Y, and the relative
current polarities in the selected Y
drive lines are reversed for read and write.
|
|
The four current generators are turned on by the X and Y current source signals (the

multiplexer outputs include

the Y I SOURCE DIODE END T H and Y I SOURCE COMMON END T H signals). Each
signal

transistor (Q10 - Q13) that applies a temperature-compensated reference voltage (Vref

base of a constant-current source (Q6 - Q9).
3.9

turns on a

- Paragraph 3.9) to the

VREF CIRCUIT

The reference voltage (Vref) is derived from the circuit shown in Figure 3-20. Although

Ql,

the output is taken from
the reference voltage is generated by the operational amplifier (El) that is biased
by a temperature-com-

pensated resistor network.

Table 3-7
Core Location X/Y Control Signals
Al4 L

A14BOH

Lower Half

(Addresses X000003—X377775)
|

Low

X READ SOURCETL

X READ SINK TL

| UpperHalf

High

(Addresses X400005 —X777775)

X Control Signals

Y Control Signals

Y COMMON SOURCE TL
Y DIODE SINK TL

X WRITE SOURCE TL

Y DIODE SOURCE TL

X WRITE SINK TL

Y COMMON SINK TL

X READ SOURCE TL
X READ SINK TL

Y DIODE SOURCE TL Y COMMON SINK TL

X WRITE SOURCE TL

Y COMMON SOURCE TL

X WRITE SINK TL

Y DIODE SINK TL

+20

b
1

V-

A A

AAA

Low

High

Core Location In Mat

VREF

XY LO XY HI

NOTE: Logic is P/0 H222 module
11-3565

Figure 3-20

Vref Circuit

3-26

Temperature compensation is provided by thermistor T1. The bias voltage for El is adjusted at the factory for

the proper stack current using jumpers at location W1 and W2. The XY signal is used for external control of
Vref, only by factory test equipment. XY LO and XY HI are brought out to the Field Service connector (J180)

and are used to margin the XY stack currents.

3.10
3.10.1

DRIVER/SWITCH CIRCUIT
X Driver/Switch Circuit

The X Driver/Switch circuit is partially illustrated in Figure 3-21. The circuit consists of 7442 decoders and

75325 memory drivers. Each decoder output connects to two memory drivers; for clarity, drivers are shown only

at output f0 of each decoder. Part of the diode matrix is also shownin the figure; two X windings, with their 128
ferrite cores and 2 diodes per data bit, are represented.
When an assigned memory location is addressed to take part in a data transfer, the timing logic generates Read

Control signals, followed by Write Control signals. During the read half of the timing cycle, current must pass

through the addressed core in one X direction; during the write half of the cycle the current direction must be
reversed. Figure 3-21 shows how the direction of current flow through the core is controlled.
Any MM11-D address that has bits A<13:07> L negated (logic 0) causes output fO of decoders E88 and E82 to

go low. During the read half of the timing cycle, control signals

X READ SOURCET L and X READ SINK T

L are asserted; thus, NOR gates E89 and E104 are enabled. These two gates turn on the transistors at their
outputs. Current from the read current generator, represented by signal

X READ IG, flows through source

transistor “A”, through the cores in the direction indicated, through diode “B”’, and through sink transistor ‘“B”’

to ground. During the write half of the timing cycle, control signals

X WRITE SOURCE T L and X WRITE

SINK T L are asserted; thus, NOR gates E107 and E81 are enabled, turning on the transistors at their outputs.
Write current, represented by signal X WRITE IG, flows through diode A and to ground through the transistor

at the output of E81.

Assume that an address having bits A<12:07> L negated and bit A13 L asserted is decoded by the MM11-D.
Now, output f0 of decoder E97 goes low. Drivers E106 and E103 become part of the read /write current paths,

operating exactly as E89 and E81. However, the current now passes through the upper winding and includes
diodes C and D, rather than A and B.

The memory drivers, 75325, can be describedin relation to their functions (for X-drive selection, only). Thus,
driver E107 is designated a positive write driver, while E81 is designated a negative write switch. Conversely, |
E104is designated a negative read driver, while E89is termed a positive read switch. There are 8 positive write

drivers and 8 negative read drivers; there are 16 negative write switches and 16 positive read switches. Each pair

of drivers connects to 16 X windings of 128 cores, and to 16 pairs of switches; consequently, 128 X windings can
be addressed by the complete X driver logic shown in logic drawing D-CS-G652-0-1. Table 3-8 relates the read

and write functions to the various driver/switch enabling signals.
3.10.2

Y Driver/Switch Circuit

The Y. Driver/Switch circuit is partially illustratedin Flgure 3-22. This circuit is similar to the X Driver/Switch
circuit, i.e., it consists of decoders, drivers, and switches. However, since there are only 64 separate Y wmdmgs,

only two decoders are needed to accommodate the 6 address bits, A<06:01> L.
Remember that the MM
1 l-D has coincident and anti-coincident cores on the Y windings. Each winding, such as

that illustrated in Figure 3-22, passes through 256 cores per data bit (one group of 128 cores is labelled A, the

other B). When current flows through the cores in either Y direction, a single core in one group will experience
coincident X and Y currents, while a single core in the other group experiences anti-coincident currents.

3-27

= /0 STACK CIRCUITS
|

B
|

5
et

128 CORES
‘"—69

I READ
]

——

WRITE

X WRITE

I.G.

128

CORES

AN___ 7TM

READ

]

—

lWRITE

J——D?)

X READ SINK TL

LO | LO|

HI | LO

LO | LO|

HI | HI

LO|

|LO|

LO |HI | LO | HI

LO | HI | HI[LO

LO | HI | HI | HI

LO IS LOGIC @

Figure 3-21

X-Driver Circuit

3-28

A12 H— D2

LO|

AItH——DI

LO|LO

LO | LO|

E97
A13 L— D3

A1l H— D1

LO | LO|

At2 H——D2

AlIO H—— D@

D3 [ p2 | D1 I DY l PIN OUT LO

0O 0

A13 H
7442

7442

X READ

SOURCE T L

X WRITE SINK TL
{

X WRITE SOURCE TL

[75325

A7 H— D@

I.G.

A@8 H—— DI

X READ

A10O H—— D@

0O O

AZ9 H—D?2

0O O

E88

74472
4

- Table 3-8
X Drnver/Swntch Enable Slgnals |

- Function

Current Source =

Read

| N Enable Slgnals

XREADIG.

XREADSOURCETL

Write

D_river/Switch Enabled |
|

XREADSINKTL

~ XWRITEIG.

Positive Read Switch
|

X WRITE SOURCETL

Negative Read Driver

Positive Write Driver

X WRITE SINKTL

Negative Write Switch

Y DIODE END I.G.

I—P/oSTACK CIRCUITS

_L..__,

,
o

7442

E49

.
A4 H—— D2

’

- _ .I_N__

128 CORES 128 CORES

N )

' READA

[

—

SN
I
5T

EAD
B

f2 D

fzlo

.
.

b
|

Ag2 H— D1

AGI H—] D@

fslo

Y COMMON END 1.6,
e e— c——
fisszs

felO

fzlo

Y DIODE SOURCE T L ———

Y DIODE SINK TL

‘

7442

-[.

E64

fo 0

A@S H——D2
|
:

f3 D

fap

A@S H— D1

ts o

,
A@3 H— D@

'Y COMMON

]

fe P
<

SOURCE TL —m——

Y COMMON

SINK TL
-

Figure 3-22

Y-Driver Circuit

3-29

11-3567.

The direction of current in the Y winding depends
on whether the core to be selected
lower-half of the mat. If the core is in the lower-half of the mat, i.e., the core

is located in the upper or
address is between X00000; and

X3777Ts, current flows from right to left (in Figure 3-22) during the read half of the
timing cycle; current flows
from left to right during the write half of the timing cycle. Conversely, if the
core
is located in the upper-half of

the mat, i.e., the core address is between X400005 and X77777,, current flows from
half of the timing cycle; current flows from right to left during the write half

left to right during the read

of the cycle. Table 3-9 summarizes

not only the relationship between core address and current direction in the Y winding,
but also the relationship
of the read and write functions to the various driver/switch enabling signals. The relationships
expressed in the
table are developed from the Current Sources circuit, which was described in Paragraph
3.8.

Note that the 75325 drivers have been designated drivers and switches, as were those of the X Driver/Switch

logic. Each pair of drivers connects to 8 Y windings of 256 cores, and to 8 pairs of switches;
consequently, 64 Y
windings can be addressed by the complete Y driver logic, shown in logic drawing
D-CS-G652-0-1.
Table 3-9
Y Winding Signal Relationship

Core Mat

| Function

Current Source

Location

o
|

Read

Write

Read

Lower Half

3.11

Write

Driver/Switch Enabled
|

Y DIODE SOURCE TL

Positive Diode Driver

Y COMMON SINK TL

~Negative Diode Switch

YDIODESI

NKTL

YCOMMONENDIG. | Y COMMON SOURCE TL
Y DIODE SINK TL

YDIODEENDIG.

YCOMMONENDILG. | Y COMMON SOURCE TL

Y DIODE END I.G.

Upper Half |

Enable Signals

SENSE/INHIBIT CIRCUIT

Y DIODE SOURCE TL

Y COMMON SINK TL

Positive Common Switch
Negative

Common

Driver

Positive Common Switch
Negative Common Driver

- Postive Diode Driver

Negative Diode Switch

The Sense/Inhibit circuit is shown in Figure 3-23. The logic transfers informatio

n between the selected core and
the Unibus data lines. The logic illustrated is fc')r. data bit D0O; all other data bits have
identical circuits.

Consider a DATI operation
- the logic state represented by the selected core must be gated to the BUS D00
line.
At the start of the timing cycle, the timing logic asserts CLR MDR L (Clear Memory Data
Register); this signal
disables gate C of the 7520 sense amplifier, which provides one input of gate B.
Since gates A are disabled until
the STROBE 0 H signal is generated later in the cycle, gate B is disabled and the DATA
00 H signal is latched
low.
'
-

When the read currents are generated, the selected core may or may not change state.

If the core represented logic

1 before current coincidence, it switches state at coincidence, a voltage is induced in the sense

Sense Amplifier (SA) output goes high (depending on which half of the mat the core

winding, and the
is in, either SA A or B

DATA 00 H signal. Because CLR MDR L is now high, gate C is enabled and one input

of the 8641 NAND gate

provides the output). When the STROBE 0 H signal is asserted, gate A is enabled, causing gate
A goes high. When OUTPUT EN L goes low, the BUS D00 L signal is asserted.

330

B to assert the

DATA

@@ H

+20

°E1os>

L —O

(E)

|
INH

BACK
T18

LaAA—

—w—
1

A
.___.1

CLR MDRL

—9 £108)

A4 BO L

__ STROBEOH

D97 ¥

¥
D99

641

OUTPUT EN Lj:
:

A14 B@ H-

“W%

INH T@
L

—db—l—
:
.____....J

INPUT MDR H

Figure 3-23

11-3568

Sense/Inhibit Circuit (Bit 00)

3-31

When the core switched state at read current coincidence it was left in the O-state. During the write

half of the (
timing cycle, current coincidence will cause the core to switch back to the 1-state, restoring the information.

However, if the core had been in the O-state before read current coincidence, write current coincidence would

cause the core
to be restored to a logic 1-state, rather than to a logic O-state. Hence, in this situation an inhibit

current must be generated during the write half of the cycle; the inhibit current will oppose the Y winding

and thus prevent the core from being switched to the I-state.

current

If the DATA 00 H signal is low at the start of the write half of the timing cycle, indicating that
the selected core
was in the O-state before read coincidence, the INH RT L (Inhibit Rise Time) signal will enable
inhibit driver

E108A. None of the other gates - E108B, C, and D - is enabled as yet; hence, no current flows through the
transformer windings. When the INH TO L (Inhibit Time) signal is asserted, E108B and either E108C or D
are
enabled. (If the core is in the upper half of the mat, for example, A14BO0 H is negated and E108D is enabled.)
Current flows through the transistor of E108A, through diode D99, through the lower primary winding of T17,
and through the transistor of E108D to ground. No current flows in the upper primary winding yet, even though

E108B is enabled, because the transformer voltage characteristics result in diode D97 being
reverse-biased. The
lower primary current (I1) increases, as illustrated in Figure 3-24.

When INH RT L is negated, D97 becomes forward-biased: current 12 starts to flow through the transistor
E108B, through D97, through both primary windings, and through the transistor of E108D to ground.

12 flows
until INH TO L is negated and reaches a maximum of approximately 350 mA. The secondary current (I13)
flows
as 1llustrated in Figure 3-24, attaining a maximum of approximately 700 mA. The current that flows in each
half
of the inhibit winding is about 350 mA, enough to counteract the current in the Y winding, thus, preventing the
net current through the selected core from exceeding the switching threshold of the core.

The technique used to generate the inhibit current results in a desirable balance of fast current rise time and low
power supply drain. That is, as long as INH RT L is asserted, the 1:1 transformer ratio produces a rapid rise time

of the secondary current to near-maximum value; when INH RT L is negated, the 2:1 transformer ratio produces
a secondary current twice the primary value, obviating the necessity of drawing the entire current from the +20 V

power supply.

INHTQL

-L

Jre

INH RT L

~350M
— — —
A
—

11-3569

Figure 3-24

Inhibit Current Timing

3-32

(

If a DATO operation is programmed, CLR MDR L is asserted at the beginning of the timing cycle.-However,
INPUT MDR H isalso asserted,; consequently, the data placed on the BUS D00 line by the bus master is gated to
the MDR and latched onto the DATA 00 line. The selected core is sensed by the SA-but STROBE-0 H is not
generated hence, the state of the core before read current coincidence has no bearing on the DATA 00 H signal.
If the BUS D00 L signalis loglc 1 (low), the DATA 00 H signalis asserted. The core will be switched to the logic
1-state at write coincidence; if BUS DO0O L is logic 0, the inhibit current must be generated to prevent the core
SRR

from being sw1tched

A DATOB operation is 51m11ar to a DATO The byte spec1fied by the BUS AOO L srgnal is operated on as
|
o
descrlbed for the DATO;‘the other byteis handled as a simple readrestore operatlon -

‘,

3. 12 STACK CHARGE CIRCUIT |

The. Stack Charge c1rcu1ts are located on the H222 module Thereis a separate c1rcu1t for the X drode matrlx and
the Y diode matrix. The X Stack Charge circuit is shownin Figure3-25, along with part of the X Driver/Switch
circuit (jumper WS is removed for in-plant testing; it should not be removedin the field). The Y Stack Charge circuit
|

is similar and is not shown.

The Stack Charge circuit assists the stack capacitance in recovering and shortens the rise time of the stack current
[the effective stack capacitance associated with each line is shown as C (STACK)]. It also reduces unwanted
currents in the unselected lines associated with the selected driver.
+20V

+5V

1;5

UF—)

2 2
o

F‘
[2S]

r—|<

18]

PULL UP H

‘

/J7

—AM—

X STACK CHG H

128 CORES
'

rp/o X DRIVER/SWITCH LOGIC
X WRITE

_/Zt

I.G.

WRITE DRIVER

READ DRIVER

11-3570

Figure 3-25

X Stack Charge Circuit

3-33

The output of the Stack Charge circuit is taken from the

emitter of Q5 and goes to the junction of each X
n, the emitter voltage [V(E)] of Q5 should be approx-

read/write switch pair via a resistor. During a read operatio

imately 20 volts. During a read operation, X STACK CHG H
is low, turning on Q4. V(E) is held low by the
parallel combination of L2 and D8/D10. Current flows through
L2; thus, QS5 is off, since its base-emitter junction is reverse-biased.
,
o
|
|
—

‘During a write operation, X STACK CHG H is asserted, causing Q4 to turn
off. The current floW’ing through L2
is forced to flow into the base of QS5, turning it on and taking

The Y-axis charge circuit operates in a similar way; however,

V(E) to near +20 volts.

the phase selection of Y addresses requires that the
charge circuit operation be interchanged for half the addresse
s, the interchange being controlled by multiplexer
E72 and address bit A14. Thus, the stack Y common end
will be pulled toward +20 volts during write for
addresses in the lower 8K (BUS A14
L not asserted) and will be pulled toward +20 volts during
read for
addresses in the upper 8K (BUS A14 L asserted).
o
.
o
-

3-34

CHAPTER 4
MAINTENANCE

PREVENTIVE MAINTENANCE
s that could lead to
Preventive maintenance consists of specific tasks, pcrformed at mtervals to detect condition
preventive mainteed
consider
are
tasks
g
followin
The
ion.
subsequent performance deterioration or malfunct

4.1

APl

nance and are recommended to be performed every six months.
Visual Inspection

Voltage measurements

SSYN DLY check (for parity memories)
Strobe and Drive current margins
"
MAINDEC testing

memory are the Tektronix
The two pieces of test equipment recommended for checkmg and troubleshootmg the4443
Digital Voltmeter (or
453 Dual Trace Oscilloscope (or equivalent) and the Weston Schlumberger Model
equivalent) with 0.5 % accuracy.

CAUTION

Make sure all power is fo before mstalling or removmg
mmlules

4.1.1

Vlsual Inspection

Visually inspect the modules and backplane for brokfin wires, connectors, or other obvious defects.
|

NOTE

All tests and adjustments must be performedin an amblent
‘temperature range of 20 to 30 degrees C (68 to 86 degrees
,

Turn on the primary power and measure the +20 Vv, +5 V and -5 V voltages at the option backplane. All

4.1.2

Voltage Measurements

voltages must be within +5% tolerance.

4.1.3 SSYN DLY Check (for parity memories only)
Refer to M7850 parity controller manual.
4.1.4

Strobe and Drive Current Margins

A Field Service connector (J180) is provided on the front of the G652 module for margmmg |a given memory
,

while running a diagnostic program.

4-1

31eloem(qog19L]JS1O3/3jYN1oqQwIsj1qodoi(1ds)uoryesor
Respond To MSYN

XSS

ASS

XX XX

Memory Does Not

0A7+

dax

pHlOoB)ySsaJiIyQ|IYou]/)asUIS dUI'T _

AT1O THAN

AX38eNO0A gy ymox)

gAdaeJioujpajrqy JsAInILDgIY(] 19qIAyuL] YAaou-BrIXyS XdEIoN0b§zu., /SLputeMwaiy]

Symptom

Memory Hangs Bus

X|X]|

DATO Fails

Co1
XX

XXX

Many Bits Fail

Picks Bits

X (X |LO

X [ X HI

Drops Bits

HI|

XIX|LO|

Byte Failures

X |X|x|A0

2 Bits Fail

I1X IX |X

1 Bit Fails
Fails All Addresses

XX XX

Al, A2, A4 Common
A3, A5, A6 Common
[

A7—A9 Common

Ix|x

A10—A13 Common
No Inhibit

X: Circuit Not Operable

LO: Measured Parameter Too Low or Early
HI: Measured Parameter Too High or Late

Figure 4-1 Troubleshooting Chart

4-3

XX XX

5V/Div

1V/Div

GND —

—— GND

1v/Div

SV/DIV

1V/DIV

‘

'GND -

NOTES:

1. Horizontal Scale: 100 ns/div.
2.

Top Waveform in each view is BUS

1V/DIV

MSYN L, shown at a vertical scale of
5V/div; scale of all other waveforms
is as indicated.

——GND
'

Figure 4-2

MMI11-D Waveforms (A)

Mi 0285

5V/DIV

1VvV/ DiV

- GND

—

5V/DIV

GND

v/DIV

- 5V/DIV

GND-

GND

——GND

BV/DIV -

5V/DIV

—

GND ——

GND

NOTES:

Horizontal Scale:

100 ns/div.

2. Top Waveform in each view is BUS
MSYN L, shown at a vertical scale of

5V/div: scale of all other waveforms
is as indicated.

M1 0286

Figure 4-3 MM11-D Waveforms (B)
4-5

5V/Div

5V/DIV

GND ——

—GND

5V/DIVv
4
5V/DIV

GND

——GND

5V/DIV

GND ——

— GND

NOTES:
1.

Horizontal Scale:

Top Waveform in each view is BUS

100 ns/div.

MSYN L, shown at a vertical scale of

5V/div; scale of all other waveforms
is as indicated.
MI 0287

Figure 4-4

MM11-D Waveforms (C)

4-6

)

DATA @O H

INH RTL—\\d

STACK

CLR MDR‘\A?
E108

L STROBEOH

A14 BO L

’

D99
Y

T E2 |

OUTPUT EN L

INH T@ L

A14 BO H

BUS D@ L —

|
|

INPUT

MDR H

"W-3572

Figure 4-5

Waveform Key A (Sense/Inhibit Circuit)

- 4-7

STACK

-;_

REF

{

"X READ I SOURCE T H

{

{>¢L

A
?

X WRITE

I SOURCE

T H

$—

Qi3

{

X-READ

L.G.

Y COMMON SINKTL

183

X WRITE SINK T L

{A3

X READ SOURCE T L~

{B2

X WRITE SOURCE T

YI SOURCE

X READ SINK T L

L———r

DIODE END T H

Y STACK

754;527

‘
)

ylx

Y DIODE SINK T L

\4
.

fol—Y DIODE SOURCE T L

CHG H

{ A2

—

+20

‘

SOURCE

ENDTH

COMMON

Y-COMMON END .G

+20

B@
Ag

fol—Y COMMON

1*'

A4 BO H

SOURCE T L

STB

‘l‘

’ ‘—I >SO— AAA

%’;

}

Q12

»
§

'z‘

X -WRITE I.G.

+20

Y- DIODE END I.G.

'y
11-3573

Figure 4-6

Waveform Key B (Current Sources Circuit)

4-8

/0 STACK CIRCUITS

I
!

128 CORES

I
i READ

AN AN

. —

[

X WRITE

1.G.
1

{

—_—

WRITE

;

128 CORES i READ " B4

S, |2

IWRITE

= [T~cy

\55

7442

—1 03

E8S8

f10

X READ I.G.

f210

AG9 H— D2

filo
f4

AG8 H—— D1

A7 H— D@

6 [0

E89

| °

f-lo

75325

fs O
f

r;5325

)

E106

7442

X WRITE SOURCE T L

X READ SINK TL

Ege

At3 H

fg P
f

A13 L

f2 D

A12 H—D?2

A11H—— D1
A10 H— D@

fz o

f4 0D

5 o

fe O

f7 0

|
|

7442
D3

‘

A12 H—]D?2

:
|

=37

‘e

75325

l[ —O|

f4 0
A1l H—
D1

A0 H— D@

E103

f110

f4 |0

]
I

fsp
fe 1O
f7 0

X READ SOURCE T L
X WRITE SINK TL
1n-3574

Figure 4-7

Waveform Key C (X-Driver Circuit)

4-9

Y DIODE END L. G.

Cé

[P/0 STACK CIRCUITS

128 CORES

T
128 CORES

7442

—103

fg
f1C)
f2 D

fio

AG2 H— D1

‘

fap

510

f- 7 10

Al H— D@

Y COMMON END L G.
55325

SINK TL

—34—0

‘

Y DIODE SOURCE T L ———
Y DIODE

AG4 H— D2

|
|

7442

f() O—

£E64

fi1 o

AQ6 H— D2

AG5 H— D1

fe O

fe P

AG3 H— D@

f7 D

Y COMMON SOURGE

Y COMMON

T |

7;;-25——-—[

—-I——O

T —O E74

L _T-I — -r'"
:
I

|
|

l
|

|
.

—

SINK T L
11-3575

Figure 4-8

Waveform Key D (Y-Driver Circuit)

MAINDEC TESTING

Certain DEC programs can be used to test various memory operations as an aid to troubleshooting. The purpose

of each of these memory-related test programs, as well as the program abstract, is given in the following paragraphs. Each program contains instructions for use.
4.3.1

0-124K Memory Exerciser (MAINDEC-11-DZQMB)
|
The purpose of the 0-124K Memory Exerciser program is to test contiguous memory addresses from 000000

to
757776. It verifies that each address is unique (address test) and that each memory location can be read or written

reliably (worst case noise test). If Memory Management is available, all testing is performed with memory

management enabled (unless disabled). This program may be used to adjust/margin memory.

4-10

4.3.2 0-124K Memory I/O Exerciser (MAINDEC-ll-DZQMA
|
|
The purpose of the 0-124K Memory I/0 Exerciseris to test sequentially all locations of core memory, or any

4K
section of core memory, using any NPR device specified. The program checks bank selection, effectlve address

bits, and memory. It can run alone or with a Memory Management device to access extended memory. Worst
case noise patterns are used with the NPR device to test memory. Printouts of NPR device errors are provided

and include designation of the device under test, the content of its control and status register, and the content
of
its error register. Data error printouts 1nclude the address of the bad data, the true data sent, and the bad data received.

4.3.3
Combined Parity Memory Tests (MAINDEC 11- DCMFA)
The purpose of the Combined Parity Memory Testsis to locate the parity memory registers and pcrform a check

of the bitsin each. A map showing the memory controlled by each parity register is created by the program. The
parity registers and memory are tested using the informationin the map.

Several bit patterns are written into each parity memory location to ensure that no parlty errors are »reated Each byte of parity memory is written W1th both good and bad parity to ensure that the parity b1ts can be toggled and
sensed.

4-11

APPENDIX A
IC DESCRIPTIONS

This appendix contains descriptions of several integrated circuits (ICs) used in the MM 11-D logic. Only those
ICs of an unusual nature are described; the more common types, i.e.,
familiar to the reader.

NAND gates, inverters, flip-flops, etc., are
|

A-1

7442 4-LINE TO 1-LINE DECODER
The 7442is a BCD-to-decimal decoder consisting of eight inverters and ten 4-input NAND gates. The inverters
are connectedin pairs to make BCD mput data available for decoding by the NAND gates. A logic diagram, a
truth table, and a pin locator are shownin Figurc A-1.

TRUTH TABLE

BCD Input

Decimal Output

| c

| B

oli1l2]31alslel7

(819

ofj1i1¢111111

tfolt

]

| 1

1191111

10]1

110

011 :

0 .

110

{11

1111

1
1

0
|

1
0

|
0

1111111141
1
1
|
I
|
1

1
1

|1
|1

1
1

|1
|

111

]

¢1

A
)

INPUT A

b——oourpuro

}y-——oouwur 1

INPUTS

OUTPUTS

INPUT BG_DC

NERERS

Vee

15|

|14

i3]

Ji2]

L_>> ¢

D=BmB = =
3

OUTPUTS

1-0733

INPUT

2 —

HES
c

OUTPUT 3

4
OUTPUT

E}ouwurs

g })——oourpm 6

[

}—-aompura

o——-D&

Eol
B

A
B
C

))——oou‘rpur 7
.

j )

OUTPUT

D
11-0734

Figure A-1

7442 Illustratlons

;.'

TM lo+r 2 3 4 56 7 8 s

A-2

7475 4-BIT BISTABLE LATCH

to
The 7475 is used for temporary storage of binary data. Information applied to a Data (D) input is transferred
high.
remains
clock
the
as
long
as
input
D
the
follows
the Q output when the clock input is high; the Q output
When the clock goes low, the information present at the D input prior to the clock transition is retained at the Q
output until the clock again goes high. A logic diagram, a circuit diagram, a truth table, and a pin locator are
shown in Figure A-2.

CLOCK

1-2

GND

. Q

CLOCK

Vee

3-4

IC-7475

Truth Table

(Each Latch)

n [ ‘ntl

D
1

Q
)

B PACKAGE

14 13

GND

Vcee

- NOTES:

1. t_ = bit time before clock
negative-going transition.

2. i+l = bit time after clock

negative-going transition.

\\«gns/ i

Figure A-2

A-3

7475

2 3 4 5 6 7 8

7483 4-BIT BINARY ADDER
|
‘The 7483 adds two 4-bit binary numbers and
a carry-in bit. Sum outputs are provided

for each bit and
a carry-

out bit is available from the fourth bit. A logic diagram,
a truth table, and a pin locator are shown in Figure A-3.
3

CARRY

INPUT

OUTPUT
LOGIC
WHEN

Azl/

Co=0
WHEN

WHEN

Co=0

[|A2. [1B2 /151 /152 [lea

[l [z /]y

‘

B3|/

A4/

Ba|/

53|/

o | o]

ool

La|/

Ca|/

Z3|/

ta|/

o | o

1r]e|o|o|

1]|o

e
e
e
o

o | 1

o | o | o

L
1

[

NOTE 1:

L
1

1
1

l [_—] r_l m l_—i [——i r—l I
24

CARRY CARRY
uT

GND

A1l

Vee

L
5

LOCATOR

‘

(TOP VIEW OF IC)
IC-7483

Input conditions at A4, A, By, B, and Cg are used to determine
outputs X1 and X2, and the value of the internal carry Co.

| I

DIAGRAM

WHEN

Co=0

Ay [ IB1

CARRY OUT

The

values at Cy, A3, B3, A4, and By, are then used to determine

Figure A-3

outputs X3, 4, and Cy4.

7483

7520 DUAL CORE MEMORY SENSE AMPLIFIER

The 7520 converts bipolar millivolt-level memory sense signals to saturated logic levels. A common reference

input allows the input threshold voltage level of both amplifiers to be adjusted. Separate strobe inputs provide
time discrimination for-each channel. A connection diagram is shown in Figure A-4,

CexT

STROBE

GATE

—

DIFFERENTIAL
A
INPUT

OUTPUT

-—

REFERENCE
INPUT

STROBE
B

GATE
g

\.\t-w—/

A-5

V-

DIFFERENTIAL
-

INPUT B
|

Figure A4 7520

GND

IC-7520

The 74121 Multivibrator features dc triggering from positiv
ing occurs at a particular voltage level and is not directly

e-going
or gated negative-going inputs. Pulse triggerrelated to the transition
time of the input pulse. Once

fired, the outputs are independent of the input pulses and

Input pulses may be of any duration relative to the

are shown in Figure A-5.

depend only on the timing components on the chip.

output pulse. A logic diagram /pin locator and a truth

table

TRUTH TABLE

tn INPUT [t,,4 INPUT
,
[a1]lAa2lB|

OUTPUT

t11{O11]1]¢]

INHIBIT

At]A2|

o[xX|1]o]x|0]|

INHIBIT

X{Oof{1|Xx]0o|0O|

INHIBIT

{14

NC
1

TIMING PINS
‘
A————

.
11

O|X|O]O|X|[1]|ONE SHOT
X{0[O]lX|0]|1]|ONE SHOT
t1111X]0]|1]|ONE SHOT

1]1]

INHIBIT

OIX|1

11|

INHIBIT

1T{1{0]X[{O0(O]|

INHIBIT

1]110JO0[X]|O|

INHIBIT

\
)

’ji

Q
4

in(1)

0= Vin (0) <0.8V

1. th= Time before input transition.
2. tn+1=Time after transition.

3. X indicates that either a logicai
S

INHIBIT

X{O11

ti111110[x|1]0ONE SHOTI
Xx|{ojolx|1]0]|
inviBIT
|

olx|]ol1|x|o]!]

—1

- Q

A1
.

Oor 1 may be present.
|

Figur
A-5
e 74121

A-6

GND

IC-SN74121

(’

)

.
74153 DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER

The 74153 acts as a double-pole, four-throw switch. Two select inputs, A and B, determme which of the four

inputs is chosen; the same input of both four-line sectlons is selected A logic dlagram a truth table, and a pm
-

locator are shown in Figure A-6.
E
STROB16

(ENABLE) o)

<{>

—

1CH (5)

Cfi

1
DATA

1C2 (4)

cfii

L——t:‘_‘}—

1C3 (3)

- O—

ADDRESS

B(2)
O

(14)

> -

2C0 (10)

2C1 (11)

DATA 2 <

__}_‘

‘

»<{>

L ourputs

—i

2C2 (12)

(9)

—0 2Y.

O—

o—

2C3 (13)

—_)__‘

%\/:

(ENABLE) ®

STROBE 26 _(158)

Ve *] PIN 16

GND= PIN 8

'STROBE

~
SELECT INPUT |STROBE

OUTPUT

LOW

Cco

HIGH

| LOW

LOW

LOW | HIGH|

HIGH

DONT CARE

Low

LOW

HIGH

LOGIC DIAGRAM

| OUTPUT

“ DATA'INPUT

9
10
11
12
13
14
15
16
r—'1 r_'] r““l [—-l r—l r——] [—"'"I r——]
:

«cC2

1C3 1C2

1cg

GND

| L] l_.I LG_J L_7—l
L_J L.é._l L_;J

LOW

TRUTH TABLE (EACH HALF)

1c1

STROBE B
IG SELECT

DATA INPUT

—
|

OUTPUT GND |
Y
IC-74153:

Figure A-6

74153

74157 QUAD 2-INPUT DATA SELECTOR /MULTIPLEXER

‘The 74157 consists of four 2-input multip

lexers with common input select logic and
common output disable

circuitry. It allows two groups of four
bits each to be multiplexed to

truth table, and a pin locator are shown
LOGIC

in Figure A-7.

four parallel outputs. A logic diagram,

DIAGRAM

2pol6)

(11)

3B oflo.)" ,
aA

(14)

_(12)

(13)

4B O—

SELECT

(1)

—1

B.FW. PACKAGE

“

INPUTS

——

|
|
Vcc

et
(e

——
~

TRUTH TABLE
INPUTS
STROBE

| SELECT

|
|

outpuT
v

o X

H-

A AAAAN
16

|
-

SEL

INPUTS

A-8

74157

U
O
O
Q
>
3
a
5
&
7
3
1Y

—

Figure A-7

U
,

IC-74157

—1S
|

INPUTS

GND

75325 MEMORY DRIVER

"The 75325 contains two source-switch transistors and two sink-switch transistors. Selection logic in the IC per‘mits external control circuits to choose one or more of the switches for circuit operation. A logic diagram/pin
|
|
locator and a truth table are shown in Figure A-8.

SOURCEW

COLLECTORS

_S1

S2,

S.TRO’BES‘

GND

positive logic - See truth table

IC-75325

TRUTH TABLE

AddressInputs
B

Sink
D
C

"x,lx

x x

B H

Source

| Strolgé Inputs

~Source
s1

Sink
S2

- _
W

Source

| Outputs
X

Sink

oFf

| OFF OFF
OFF

“OFF

OFF

| oFF

OFF

ON - OFF

OFF OFF

OFF

| OFF

OFF

| OFF

OFF

H
|

H = high level, L = low level, X = irrelevant
NOTE: Not more than one output is to be on at any one time.

Reader’s Comments

MM11-D/DP CORE MEMORY MANUAL
EK-MM11D-TM-001

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