MM11D/DP Core Memory Manual

This manual describes the MM11-D/DP Magnetic Core Memory manufactured by Digital Equipment Corporation, designed for use with the PDP-11 family Unibus.

Key aspects covered include:

• Purpose: Provides information for installation, maintenance, and a detailed theory of operation.
• Audience: Intended for DEC Field Service representatives, PDP-11 trained customers, and readers familiar with digital computer theory and Unibus principles.
• General Description: A low-cost, low-power, high-reliability magnetic core memory that acts as a slave device on the Unibus. It stores 16,384 words (16-bit for MM11-D, or 18-bit with 2 parity bits for MM11-DP, requiring a separate M7850 Parity Control module).

• Features:

  • Addressability: Its starting address can be set on any 8K boundary within the 124K Unibus address space, and can also utilize part of the I/O page.
  • Interleaving: A special feature allows for memory interleaving, where two modules are used alternately for odd/even addresses within a 32K block, reducing the effective memory cycle time.
  • Performance: Features a maximum access time of 425 ns (MM11-D) or 560 ns (MM11-DP with parity control), and a cycle time of 1 µs.

• Physical Structure: Consists of a G652 hex multilayer motherboard (housing Unibus interface, timing/control logic, X/Y drivers, and sense/inhibit circuits) and an H222 hex stack (containing the core plane, stack diodes, stack charge circuits, and temperature-sensing circuitry).

• Content Detail: The manual includes chapters on installation, detailed logic descriptions of various internal circuits (e.g., core array, voltage monitor, address decoding, current sources, driver/switch, sense/inhibit, stack charge), and comprehensive maintenance procedures (preventive, corrective, and diagnostic testing using MAINDEC programs). An appendix also describes unusual integrated circuits used in the design.