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MF11-U/UP Core Memory System Maintenance Manual
Order Number:
EK-MF11U-MM
Revision:
003
Pages:
122
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MF11-U/UP core memory system maintenance manual dlilgliltiall EK-MF11U-MM-003 MF11-U/UP _ core memory system maintenance manual digital equipment corporation - maynard. massachusetts 3rd Printing (Rev) November 1974 Copyright © 1973, 1974 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. - Digital Equipment Corporation assumes no respon- -~ sibility for any errors which may appear in this manual. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: PDP DEC FLIP CHIP DIGITAL -~ | FOCAL COMPUTER LAB UNIBUS 11/75-15 S 1st Edition, September 1973 2nd Printing (Rev) March 1974 CONTENTS Page CHAPTER 1 MF11-U/UP CORE MEMORY GENERAL DESCRIPTION 1.1 INTRODUCTION 1.2 GENERAL DESCRIPTION 1.2.1 o Introduction | . . . .. P P J . B | e e e e 1-1 e e, 1-1 . . ... ... ... .. .... . e ... L. L 1.2.2 Physical Description 1.2.3 Specifications 1.2.4 Functional Description 1.2.4.1 Introduction 1.2.4.2 Timing and Control Module . . . . . . .. . . . . ... . ... ... ..... 1-5 1.2.4.3 G114 Sense Inhibit Module . . . . . . . . . .. .. ... 1-5 . . . . .. . ... ... .. e e e e e . . . . . . .. L . . . . . . . . . . . . .. ... G235 Driver Module 1.2.4.5 H217D Stack Module e e e e e . v oo 1.2.5.1 Data In (DATI) Cycle . . . . . . . . . . . e 1.2.5.2 Data In, Pause (DATIP) Cycle 1.2.5.3 Data Out (DATO)Cycle 1.2.54 Data Out, Byte (DATOB)Cycle 1-3 Y 1-7 . .. .. . e e 1-8 . . ... .. . .. . . . ... . ... ... ... 18 . ... .. ... ... e e e e 1-8 16K UNIBUS TIMING MODULE 2.1 INTRODUCTION 2.2 MEMORY PROTECTION CIRCUITS . . . . .. ..ot ToL . . . . . . . . . . . . e 2.2.1 DCLO and BUSINIT . . . . . . . . . . e 222 Loss of Bias Current . . . . . . . . . . . e e 23.1 1-3 . . . ... . P £ . . . . ... .. ... o 2.3 1-1 1-2 . . . . ... .... P Memory Operations CHAPTER 2 Basic e . . ... ... ... ... e e e e 1.2.4.4 1.2.5 L OPERATING MODE SELECTION LOGIC - e e e e e 24 21 2-1 e 2-4 . . . ... . .. .. ... .. ..., ..... 2-5 OperatingModes . . . ... ... ... .. ...... e 2-7 23.1.1 Master Sync . . . . . .o o e e e 2-7 23.1.2 Slave Synchronization (SSYN) Circuit 23.1.3 Device Selection 2.3.1.4 Address Decoding 23.15 Mode Selection 23.1.6 DATI MODE (Read—Restore) 2-7 e 2-7 . . . . . . . ... 2-7 23.1.7 DATIP Mode DATO (Clear—Write) 23.1.9 DATO 2.3.1.10 DATOBMode Introduction e e e e e e e e e . . ... .. P e . . . . . . . e e e e e e e e e e e 28 e 2-10 e e 2-12 . . . ... ... ... ... ...... I .. ... ... .. ...... e e e e e e e e e e e e, 212 . . . . . . . . e e 2-12 DEVICE AND WORD SELECTION 24.1 i . . . . . . . . .. .. 23.1.8 2.4 . ... ... . . . . . . . . . . . . . . . .. ... . . . . . . . . . it et , 2-12 . . . . . . . ... 212 242 Memory Organization and Addressing Conventions . . . . . . . . .. . ., .. ... 2-13 243 Device Selector . . . . ... .. .. .. e e e e e e e e 2.4.4 Word Selection . . . . . . . . . 2.4.4.1 2.5 Word Address Register CONTROL LOGIC 25.1 Introduction 25.2 Timing Circuit e ee 2 e e e e e e e e . . . . . ... ... .. .. ... ... .., e 21T ....218 . . ... ..28 8 . . . . . . . . L. e e e e . . . . .. O e 2523 MATB START READH Signal 254 MATB AEARLY L Signal . ... .. . . . . . . .. ... 25.5 MATB LOCK MAR 1 L, MATBLOCK MAR 2L Signals 2.5.6 MATB CLEAR MDR O L, MATBCLEARMDR 1 L Signals e e 2-18 e e ... 2-19 . . . ... ... ... .. ... ...........220 11 ... ... 220 . . ... ... ... .,..22] . . . ... ... ..... 221 CONTENTS (Cont) Page 2.5.7 2.5.8 2.5.9 2.5.10 2.5.11 2.5.12 2.5.13 2.5.14 2.5.15 2.5.16 2.5.17 2.5.18 2.5.19 2.5.20 CHAPTER 3 3.1 3.2 3.3 3.4 35 3.5.1 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 MATB CLK MDR O L, MATBCLK MDR 1L Signals . . . . . e e e e e e . 2-21 MATB PAUSE H Signal . . ... ... ... e e e e e e e e e e 2-21 . . . . .. .. ... .... e e 2-21 MATC READ EARLY L Signal MATCEND STROBE L Signal . . . . . . . . . . .. . .. 222 . . . . .. .. ... ... ....... P 2-22 MATC READLATE L Signal MATC OUTPUT ENABLE H Signal . . . . . . BUSSSYN L Signal . MATC 300 NSDLY H Signal MATD WRITE EARLY L Signal . MATD STACK CHGH Signal MATD WRITE LATE L Signal . . . MATDINH TIME H Signal WRITE LOCKOUT H Signal . . MATD END OF WRITE L Signal . . . . . . . . . .. .. .. e . .. . . . . . . . . . . . . e e e . 2-22 o e e . 222 e e e e ... ... .. e .. 2-22 . . . . .. .. . . it 2-22 . . . . . .. e e 2-22 . ... . ... .... e . . . . . . .. i 2-22 e 2-23 o i i . . . . . . . o it ... . 223 . . . . .. . .. .. . . DRIVER, SENSE AND STACK MODULES e e e e e e e e 3-1 e . .. ... ..... e ek e e e e e e e e INTRODUCTION e 3-1 e e e e e e e e e e e e e e e e CORE ARRAY . . . 13 | G e e ... ... . MEMORY OPERATION . 34 e e e e e e e e e e e e e e e e e e e e e e i o o . . . . X AND Y DECODING e e e e eS 3-9 Read/Write Operations . . . . . [P P 39 Introduction X and Y Current Generators . . . . . .« v v vttt e e e e e e e e e e e e 3-12 . . . . . . .. .. e e e e e e e e e e e e e e e e e e e e e e 3-14 Inhibit Driver e e 3-16 e e . . . . . . .. L Sense Amplifier Memory Data Register . . . . . . . . . .. . ..oe e e e . . 3-16 4.1 e INTRODUCTION . . . . . .. ... ... ...... DESCRIPTION SPECIFICATIONS . .. ... ... ..e e e FUNCTIONAL DESCRIPTION . . . . . . . 442 44.3 444 4.5 4.6 4.7 4.8 4.9 | 4-1 4-1 4-2 4-3 .. . . . . . i e e e e e e e e e e e e e e e e e e e e e e e e e . . . . o o . . . . . . . . .. L. e e e e e e e e ee et e e . . . . e e e e e e e e e e e e e e e e e e e e . . o e e e e P ... ............ e 4-4 4-4 4-4 4-5 4-5 4-6 e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e ee . . o oo e e e e e e e e e . . . .......... e e POSSIBLE INTERLEAVING CONFIGURATIONS ADDRESS SELECTION e e 3-16 e e e e e s e e e e e e e e DATI or DATIPCycle DATOCycle . . DATOB Cycle . Jumper Terminals . . PROGRAMMING . . . BUS LOADING INTERNALBUS ... e e e e e .. e .. ... MF11-UP CORE MEMORY WITH PARITY 4.4 e . . ... ... ... ... e CHAPTER 4 44.1 34 Word Address Decoding and Selection Sequence . . . . . . . .. ... ... ... 3-8 ... ... .. ... 39 READ/WRITE CURRENT GENERATION AND SENSING . . . ... STACK CHARGE CIRCUIT 4.3 it et e ... DRIVERS AND SWITCHES . . . . . . . . 37 4.2 e e 2-22 e e e . . ... ... ... ... .. ... e . . . . . . . % e e e e e e e 4-3 46 e 4-6 CONTENTS (Cont) Page CHAPTER 5 INSTALLATION AND MAINTENANCE 5.1 INTRODUCTION .. ... ..........S e e 5.2 INSTALLATION . . . . . . . e e e 5-1 e e e e 5-1 . . . . . . . . . .. ... 5-1 e s e d e e e 5.2.1 Mounting Box and Power System 5.2.2 Jumper Configuration . . . .. ... .. ... ... ... .. e 5.2.3 Installation Procedure . . . . . . . . . . . . .o 5.3 PREVENTIVE MAINTENANCE . . ... ... ... ........ e 5.3.1 Visual Inspection . . . . . . . i i 5.3.2 Voltage Measurements . . . 53.3 Sense Strobe Delay Check 5.3.4 Drive Current Checks e 53.7 MAINDEC Testing e e e e e e e 5-7 5-7 . . . . . ... . ... ... ... . . . . . . . . . .. e . . .. ... ....... e 5-7 e e . e e e e e e e e e 5-8 5-8 e e e e 5-8 oo el 5-8 . . . . . .. ... ... 5-8 . . . . . . . . . 5.4.1 Voltage Adjustment Procedure 5.4.2 ‘Sense Strobe Delay and Drive Current Adjustments 54.3 PCL SSYN DLY L Adjustment Procedure 5.4.4 Corrective Maintenance Aids MAINDEC TESTING 5-5 5-7 5-8 Strobe and Drive Current Margins CORRECTIVE MAINTENANCE 54 e e e e e e e e e . . . . . . . ... .. ... ..... e e e e e e e PCL SSYN DLY Check (for parity memoriesonly) 5.5.1 e e e e e e e e . . . . . . . . o i i 5.3.5 5.5 e . . . . . . . . L. Ll 5.3.6 5.4 e e e e e e . . . . . ... ... ....... 5-8 ....................... 5-9 . . . . . . . . . . . . ..o e 59 . . . . . . e e e e e e e e e e e e e e e e e 0—124K Memory Exerciser (MAINDEC-11 DZQMB) e e 5-9 e 5-10 55.2 0—124K Memory I/O Exerciser (MAINDEC-11-DZQMA) . . . . . . . . .. .. ... 5-10 55.3 Combined Parity Memory Tests (MAINDEC-11-DCMFA) . . . . .. e APPENDIX A Al ~ IC DESCRIPTIONS | e e e e e 5-10 | 741 HIGH PERFORMANCE OPERATIONAL AMPLIFIER . . . .. .. e e e e A-2 . ... .. ... ... ........ e e A-3 . . . . . . . . . . . oo A-5 A2 ~ T4424 LINETO 1 LINEDECODER A3 7475 4-BIT BISTABLE LATCH A4 7483 4-BIT BINARY ADDER A5 7485 4-BIT COMPARATOR A.6 7528 SENSE AMPLIFIER A7 82S62 9-BIT PARITY GENERATOR AND CHECKER A8 74121 MONOSTABLE MULTIVIBRATOR A9 74154 4-LINE TO 16-LINE DEMULTIPLEXER A.10 75325 MEMORY DRIVERS . . . .. ... ...... e . .. .. .. e e e e e ee e e A-7 e e A-10 . . . . . . . . . . . e . . . . . . . ... ... ... . . . . . . . . .. ... ... o . . . .. s A-12 A-14 .. .. .. A-15 . . . ... ... ... .... A-17 A-20 ILLUSTRATIONS Title Figure No. 1-1 Module Utilization Chart 1-2 MF11-U/UP Simplified Block Diagram 2-1 MF11-U Detailed Block Diagram 2-2 Memory Protection Circuits 2-3 Bias Current Detection Circuit 2-4 Switch and Driver Selection . . . . . . . . . . . . .. 2-5 DATI Mode Timing Diagram . . . . . . . . . . . . . . . o i i e 2-6 DATIP Mode Timing Diagram . . . . ... ... ... .. A . . . . . . . . . . . . . . . . . . . . . .. e it i it e e e e e e e e e . . . . . . . . . . . . . . . . . ) . . . . .. ... ... ... ..... e 1-4 e 2-3 e e 2-4 e e e 2-4 L e 2-8 e e e . . . . . . ... . ... ....e e e . . . . . . . . . . . . . . e e e 29 e e e e 29 2-7 DATO, DATOB Mode Timing Diagram 2-8 Memory Organization 2-9 Address Assignments for Three Banks of 16K WordsEach . . . . . .. ... .. ... ... 2-15 2-10 Device and Word Address Selection Loglc Block Diagram . . . ... ... ... ...... 2-18 2-11 Read Timing Sequence . . . . . . . . . . . . o i i i i 2-12 Write Timing Sequence . . . . . . . . . . . 3-1 Three-Wire Memory Configuration 3-2 Hysteresis Loop forCore . . . . . . . ... ... ... e 3-3 Three-Wire 3D Memory . . . . . . . . . . . .. ... .. e 3-4 Simplified Y Line Selection Stack Diode Matrix . . . . . .. . . . ... ... ... .... 3-6 3-5 Typical Y Line Read/Write Switches and Drivers . . . . . . . . . .. .. ... . 3-7 3-6 Interconnection of Unibus, Data Register, Sense Amplifier and Inhibit Driver . . . . . . . . . . . . L L i i i e e . . . . . . . L e . e ... 2-10 e e e e e e e e 2-14 e e e e e e .. 2-19 e e e e e . . . . . . . . . . . . . .. . Sense Operation Timing Diagram e e e e e e 2-20 ..., 3-2 e e e e e e e e e e e e e 3-3 e e . . . . . . . . . . . . . ... .. e e e e e e e 3-5 e e e e e e e e 3-10 . o oo 3-11 . 3-8 Bias Current Supply and Read X Current Generator 39 Sense Amplifier and Inhibit Driver 3-10 Type 7528 Dual Sense Amplifiers with Preamplifier Test Points 3-11 Stack Charge Circuit 4-1 Parity Controller Internal Bus 4.2 Parity Controller Block Diagram 5-1 New MF11-U Power Distribution System . . ... ... .. .. e e i e e e e e e e e 5-2 5.2 Early MF11-U Power Distribution System . . . . . . . . . . ... ... ... ... .... 5-3 e e Sense Strobe Delay Waveform SSYN DLY L Timing Waveform e e e e e e e e 3-13 oL 3-15 . . . . . . . .. .. .. .. - 3-16 e ee . . . . . .. . .. e e e e e e e e 5.4 Troubleshooting Chart . . . . . . . .. e . . . . . . . . . . . . .. ... oL . . . . . . .. .. .. e 5.3 5.5 e e e e e e 3-17 e e. 4-1 . . . . . .. ... ... ... .. ..... e 4-2 . . . . . . . . . . . .. L 5-7 . . ... .. ... ... ..... e e 5-9 . . . ... ... ... e, e Typical Sense/Inhibit Circuit (D00) - Page 5-7 Sense Inhibit Module Waveforms 5-8 Typical Read/Write Drive Circuit 5-9 Drive Module Waveforms 5-10 M8293 16K Unibus Timing Module 5-11 G114 Sense Inhibit Module 5-12 G235 X—Y Driver Module 5-13 H217 Stack Module 5-14 M7259 Parity ControlModule e e 5-11 . . . . . .. ... . ... ... .... e e e e 5-12 . . . . . . . . . . . . .. ... . . . . . . . . . . . . . o o . . . . . . . . . . . . e . . . . . . . . .. . . . ... 5-17 e e e e e e 5-18 ... ... 5-21 . . . . . . . . . ... . ... .. .. e . . . . . . . . . . e e e e e e e e e e e . . . . . . . . . . .. .. Vi e 5-13 e e e 5-22 e e 5-23 e e 5-24 5-25 TABLES Title Table No. Page 1-1 MF11-U Memory Specifications 2-1 Selection of Bus Transaction . . . e 1-3 . . . . . . . . . . . . . . . . . . ... .. . . . . . . . . . . . . . 2-5 2-2 Generation of Memory Operating Signals . . . . . . . . . . . .. ... ... ... ... 23 Addressing Functions L . . . . . . . . . 2-4 Device Address Jumpers (Non-Interleaved) 2-5 Device Address Jumpers (Interleaved) L . . . . . . . .. . . . ... ... ... .... 2-16 . . . . . . . . . . . . . . . ... ... ... ... 2-17 3.1 Example of Word Address Decoding Signals 4-1 M7259 Parity Controller Specifications 42 MF11-UP Maximum Cycle and Access Times 4-3 M7259 Jumper Terminals 4-4 M7259 Parity Controller CSR Address Selection . . . . . . . .. ... ... .. ........ . . . . . . . . . . . . . CSR Addressing 5-1 Machine Serial Numbers for New and Earlier . . . . . . . . . o . o 4-2 . . . . . . .. . ... ... ....... L. 43 e 4-4 . . . . . . . . .. ... ... ....... 4-7 e e e e e e e 4-9 | . . . . . . . . . . ... . vii 3-8 ... ... ... . . . . . . . . .. L. 4-5 Power Distribution Systems 2-6 e 2-13 5-4 CHAPTER 1 MF11U/UP CORE MEMORY GENERAL DE SCRIPTION 1.1 INTRODUCTION This manual provides the user with the theory of operation and logic diagrams necessary to understand and maintain the MF11-U Core Memory (no parity) or the MF11-UP Core Memory (with parity). The level of discussion assumes that the reader is familiar with basic drgrtal computer theory. Both general and detailed descriptions of the core memory are included. - | Although memory control signals and data pass through the Unibus, it is beyond the scope of this manual to describe the operation of the Unibus itself. A detarled descrrptron of the Unibus is presented in the PDP-11 Peripherals Handbook. - . ~ A complete set of engineering logic drawings are shipped with each core memory. These drawrngs are bound in a - separate volume entitled MF11-U 16K Core Memory and Control, Engineering Drawmgs The drawings reflect the latest print revisions and correspond to the specrfic memory shipped to the user. 1.2 GENERAL DESCRIPTION - 1.2.1 Introduction This paragraph provides a physrcal descrrptron and specrficatrons for the memory The major functronal units of the memory are briefly descrrbed and the basic memory operatlons are drscussed | 122 Physical Description The MF11-U provides 16,384 (16K) 16-bit words and the MF11-UP provi‘des the same number of words but includes byte parity. Chapter 4 describes the differences between the MF11-U and MFll UP memory. The chart below shows the various option descriptions associated with the 16K memory MF1 l-U | - M8293 16K Unibus Trmmg Module G114 Sense Inhibit Module | G235 X-—Y Driver H217D Stack Module (16 brts) 7009295 Backplane Assembly MM11-U Module Set Includes all modules listed in MF11-U | "MF11-UP - but does not include backplane assembly M8293 16K Unibus Timing Module G114 Sense Inhibit Module G235 X-Y Driver Module | p——— H217C Stack Module (18 bits including parrty) - 7009295 Backplane Assembly M7259 Parity Control Module 1-1 | | except M7259 Parity Control Module and does not include backplane assembly If a user has a 16K memory system and wishes to add another 16K, he merely specifies the appropriate module set since the existing backplane assembly can hold 32K of memory. The mo dules are plugged into the slots designated in Figure 1-1. NOTE ~ Parity memory cannot be mixed with non-parity memory on the same backplane. 1 2 < > - 4 5 6 7 9 8 - : A wn - 1 [7p) < o - @ ) @ 2 - B D o- ] - : 3 — oz To) o ) N~ = |_ — . = C . . I E > — 1 14 P e) Z — Li uEJ =) o ‘é’ L = *a > i < > =! To) N 9] [\’ o N _ = %) ) « _ =z 2] i |« '(D - D 1 © <I <X © ' o n N~ — < o - T ® - © o = o R bz P —_ - = " W o = - s *o z — L 1p] o ~ —_ N T 2 n m — < — 2 - = ) . p4 © - - TM )} N 0 o N © ® F % For MF11-UP (parity memory )k, Memory Stack H217C is used. Viewed from Backplane. -11-2087 Figure 1-1 _Module.Utiliz:ation Chart 1.2.3 Specifications to Chapter 4 for additional MF11-UP The general MF11-U memory specifications are listed in Table 1-1. Refer specifications. 1-2 p— Includes all modules listed in MF11-UP MM11-UP Module Set Table 1-1 MF11-U Memory Specifications Type: Magnetic core, read/write, coincident current, random access Organization: Planar, 3D, 3-wire Capacity: 16,384 (16K) words for MM11-U (16-bit word) Maximum Access Time and Cycle Time: Cycle Time Bus Mode Access Time DATI 1000 ns 425 ns DATIP 425 ns 425 ns DATO-DATOB 1000 ns 125 ns 680 ns 100 ns (PAUSE L) DATO-DATOB (PAUSE H) X-Y Current Margins: +6% @ 0° C, 7% @ 25° C, 6% @ 50° C Voltage Requirements: +5V ¢ 5% with less than 0.2 V ripple +20 V +5% with less than +5% ripple =5 V 5% with less than 5% ripple Average Current Requirements: “Stand by: +5V: 538 A-5V: 041A +20 V: Memory Active: | Power Dissipation (Worst Case): | 0.5A +5V: +20V: 6.1A-5V: 0.51A 34A M8293 Control Module ~ 7 W G235 Drive Module ~ 33 W H217D Stack Module ~ 40 W G114 Sense Inhibit Module ~ 40 W Total at Maximum Repetition Rate: 120 W Environment: Ambient Temperature: 0° C to 50° C (32° F to 122° F) Relative Humidity: 0—90% (non-condensing) 1.2.4 Functional Description 1.2.4.1 Introduction — The MF11-U/UP Memory is a read/write, random access coincident current, magnetic core type with a maximum cycle time of 980 ns and a maximum access time of 425 ns. It is organized in a 3D, 3-wire planar configuration. Word length is 16 bits and the memory consists of 16,384 ( 16K) words. The memory can be interleaved in 32K increments for faster operation. Interleaving causes consecutive bus addresses to be located within alternate 16K memory blocks. The major functional units of the memory (Figure 1-2) are briefly described in the following paragraphs. 1-3 2m8ig¢-1dn/n-T1AWpaynduis3oigwrexgel(y z A \ |4OLSINHIHL 14 3 Iy 1.2.4.2 Timing and Control Module — The 16K Unibus Timing Module (M8293) contains the control and address portion of the Unibus interface, device selection, power monitor, read-write-inhibit control logic, and the memory address latches. Unibus Interface — The Unibus interface accepts address and control information from the Unibus. The address information is distributed to the device selector and the address latches. The control signals are supplied to the read, write, and inhibit control logic to initiate the read or write currents in memory. The control signals are BUS C00 and BUS CO01 and specify the type of data transfer (DATI, DATIP, DATO, DATOB). If a byte operation (DATOB) is specified, AOOL is examined and specifies the appropriate byte. Device Selection — The device selection logic compares the Unibus address with a prewired jumper configuration. If the address compares, a memory cycle is initiated on the receipt of MSYN. If the address does not compare with the jumper address, the Unibus has addressed some other device and no memory cycle is initiated. Read-Write-Inhibit Control Logic — The read-write-inhibit control logic operates the timing and control signals to turn on the read, write, and inhibit currents in memory. This is accomplished by propagating a voltage pulse through delay lines and setting and resetting flip-flops as the pulse is propagated through the delay lines. The logic also provides clocking and clearing controls for the data register and controls the time at which the data and SSYN are placed on or taken off the Unibus. In addition, a locking function is provided to lock the address and control information into address latches for use during the memory cycle. Address Latches — The address latch logic consists of 7475 quad latches (Appendix A) which store the address received from the Unibus for the device selector and stack address decoding circuits. When memory is not busy, the latches are left open and the output merely follows the input. When memory is busy, the output is latched to its previous state. This preserves the address during a memory cycle so that the processor can process other devices without being delayed by the memory. Power Monitor and Initialize — The power monitor and initialize logic is initiated as a result of BUS INIT or DC LO from the Unibus. Both conditions indicate that further memory operations are to be discontinued. A 3 us delay is provided to allow memory to complete the current cycle, then current sources are inhibited. NOTE The MF11- U/UP incorporates an M8293 16K Unibus Tlmlng Module (Chapter 4); other memory systems may employ a different timing and control module although the driver, sense inhibit and stack modules will be the same. Consult the applicable configuration chart in the logic print set. 1.2.4.3 G114 Sense Inhibit Module — The G114 Sense Inhibit Module contains the data porfion of the Unibus interface, the data register, timing buffers, inhibit drivers, sense amplifiers and threshold circuit. Unibus Interface — The data portion of the Unibus interface consists of type 380 Receivers which apply Unibus data to the data input of the data register (information register). This register is clocked under control of the timing signals from the 16K Unibus Timing Module. Also, the Unibus interface supplies data from the data register to the Unibus via 8881 bus drivers under control of these timing signals. Data Register — The data register is a 16-bit flip-flop register used to store the contents of a word after it is destructively read from memory; the same word can then be written back into memory (restored) when in the DATI mode. The register is also used to accept data from the Unibus lines to accommodate the loadmg ofincoming data into the core memory during the DATO or DATOB cycles. Timing Buffers — The timing buffers are used to buffer the timing signals between the timing and control board and the G114 Sense Inhibit Module. Inhibit Drivers — Each bit mat contains a single inhibit/sense line that passes through all cores on the mat. A bit mat in the MM11-U is a core array of 16,384 cores associated with a particular bit position in all the words in memory. To write a O into a selected bit, an inhibit current is passed through the inhibit/sense line that cancels the write current in the Y line. The core does not switch, so it remains in the O state. Cores are left in the O state at the end of the read portion of the cycle. With no inhibit current, the currents in the X and Y lines switch the core to the 1 state during write sequences. Sense Amplifiers Threshold —During a read operation, the sense amplifier picks up a voltage induced in the sense/inhibit winding when a core is switched from a 1 to a 0. This signal is detected and amplified by the sense amplifier whose output sets a data register flip-flop to store a 1. In effect, a 1 is read when the core is switched to the O state. Cores which were previously set to O do not SW1tch and are not affected. The threshold circuit provides a reference threshold voltage to ‘the' sense amplifiers. In a read operation, if the threshold voltage (17 mV) is exceeded during sense strobe time, the sense amplifier produces an output. 1.2.4.4 G235 Driver Module — The G235 Driver Module contains the decoders, X and Y drivers and switches, associated timing and control for the X and Y drivers, sense strobe control, bias source generator, and current - | sources. Decoders — The decoders decode 14 of the 18 bits of the Unibus address. Seven of the 14 address bits are used for X address selection and seven are used for Y address selection. Four of the seven X bits are applied to the X switches and three to the X drivers. The same situation occurs for the Y drivers. The four bits not sent to the decoders are used for decoding device selection and byte operation. The decoded X and Y bits ultimately spemfy one core out of 16,384 for each bit of a 16-bit word. , Switches and Drivers — The switches and drivers direct the flow of current through the magnetic cores to ensure the proper polarity for the desired function. This action is necessary because a single X read/write line is used, a single Y read/write line is used, and the current for a write operation is opposite in polarity to the current required for a read operation. There are separate switches and drivers for the read and write circuits in the selection matrix. Drivers Timing and Control — The drivers timing and control logic receives inputs from the timing and control module and combines the timing signals to derive specific timing pulses and proper timing relationships required by all X-Y drivers and switches as well as current sources. , Sense Strobe Control — The sense strobe controlis a one-shot multivibrator whose duration can be controlled by an external voltage input. The control determines when the sense amphflers are exammed NOTE A factory adjustment is made by cutting certain jumpers to determine the optimum position for the sense strobe to occur. Sophisticated test equipment is used in making this factory adjustment and changing the jumper configuration will result in less than optimum memory performance. Pin AV1 on the G235 Driver Module is designated “strobe margin.” This pin is normally left open and floats to approximately 2.5 V. However, a voltage can be applied to ensure that the memory has adequate sense strobe margins (ground for early strobe, +5 V for late strobe). Bias Source Generator — The bias source generator is a dc, temperature compensated, bias current used to control the amplitude of the current from the X and Y current generators and inhibit current sources. Current Sources — X and Y current generators provide the current necessary to change the state of the magnetic cores. The rise time and amplitude of the output-current waveform have been selected to provide optrmum switching of the core states and maximum s1gna1-to-noise ratio for a wide range of temperatures - | 1.2.4.5 'H217D Stack Module — The H217D Stack Module contains the ferrite core array, X-Y diode matrices, sense/inhibit terminations, stack charge circuit, and a thermistor to provide temperature compensation for the bias current. Ferrite Core Array — The core array is contained on the H217D Stack Module and consists of a planar array 128 X 128 X 16 mats, or a total of 262,144 cores. - - X-Y Diode Matrix — The X-Y diode matrix is usedin conjunctron with the drivers and swrtches andis used to select one of 128 X lines and one of 128 Y lines. - | Sense Inhibit Terminations — The sense inhibit terminations terminate the sense inhibit lines in order to minimize transmission line reflections. This is necessary in order that the sense amplifiers can sense core switching with minimum distortion. Stack Charge Circuit — The stack charge circuit is used to bias the X and Y drive lines to near ground potential during read time, and to near +20 V during write time. The purpose of this is to back-bias the diodes on the X-Y matrix to prevent loss of drive currents due to chargrng capacrtance through unselected diodes. 1.2.5 Basic Memory Operatlons The core memory has four basic modes of operation. ‘The main function of the memory is simply to read or write data. Additional modes are provided, however, to allow for byte operation and to postpone the restore cycle in a N read-modify-write (DATIP/DATO) cycle. The four basic memory operations are: a. read/restore (DATI) b. read pause (DATIP) c. write (DATO) d. write byte (DATOB) These four modes are discussed briefly in the following paragraphs. NOTE In the following discussions, all operations refer to the master (controlling) device. For example, the term data out indicates data flowing out of the master and into the memory. 1.2.5.1 Data In (DATI) Cycle — The DATI cycle is a read/restore memory cycle. During this operation, the memory reads the information from the selected core location, transfers it to the Unibus, and then writes the information back into the memory location. This last step is necessary because the core memory is a destructive readout device. During the first (read) part of the cycle, the memory strobes the data into a data register and then gates the data to the Unibus. Then, during the second (write) part of the cycle, the memory restores the data back into the addressed memory location. 1-7 1.2.5.2 Data In, Pause (DATIP) Cycle — Since the data is destroyed when reading from a particular memory location, it must be restored. However, sometimes it is not desirable to restore the information immediately after reading because the location is to have new data written into it. In this instance, eliminating the restore operation decreases the memory cycle time by approximately 50 percent. The DATIP operation is used for this purpose. The data is read from memory and the restore cycleis inhibited. Because no restore cycle is used, a DATIP must always be directly followed by a write cycle (either DATO or DATOB) on the same address, or datain both addresses will be destroyed. 1.2.5.3 Data Out (DATO) Cycle - The DATO cycle is a write memory cycle used by the master device to transfer data into core memory. To ensure that proper data is stored, the bus datais first clocked into the data register, then ‘the memory location is cleared by reading the cores (thereby setting them all to 0) before writing in the new data. Durrng a normal DATO, the memory first performs the read operation to clear the cores and then performs a write cycle to transfer data from the data register into the selected core location. If a DATO follows a DATIP (rather than a DATYI), the sequence is not the same. The DATIP clears core and generates a pause flag; the DATO skips the read cycle and immediately begins the write cycle. This process reduces DATO cycle time by approximately 40 percent Note that access time is the same (Table 1-1). 1.2.5. 4 Data Out, Byte (DATOB) Cycle — The DATOB cycle is srmflarin functron to the DATO cycle, except that during DATOB, data is transferred into the core memory from the bus in byte form rather than as a full word. Actually, an entire word is loaded into the selected memory location: the selected byte, which is new data from the bus; and the non-selected byte, which is restored data from the word previously stored in that memory location. During the read cycle, the non-selected byte is saved by reading it into the data register while the selected byte is transferred into the data register from the Unibus. During the write cycle, the word is loaded into the memory location from the data register. In effect, the memory is read first and then simultaneously performs a restore cycle for the non-selected byte and a write cycle for the selected byte. The mode can follow a DATIP as descnbed above. .i .| || I I FROM I | ADDRESS ADDRESS | ..\ oo MATA |A17:A13H | COMPARATOR I — _ l BUS A17:A00 L l BUS C1:CO L | l ADDRESS LATCHES _______ [ 0-250NS MAT T E,MATF MATH _______ Al4 1 AO1 L i BUSMSYN L I - BUS SSYN | L B — - I . BUSDCLOL | DELAY | I I IMATC SSYN L "Siona | wriTe evre 1:9 H GATING ' MATC END STROBE L — : MATB CLK MDR 1.0 MATB CLEARMDR 1.0 MATB LOCK MAR 24 L L L DRVC X READ SINK TIME SINK TME. oo GENERATOR _ MATC SSYN L PAUSE H H217D >_—_T MATB A EARLY L CLK{ | | POWER MONITOR MATJ DCLO L|g |NITIALIZATION MATJ 0-250 NS LOCKOUTT WRITE 0-250NS MATD l l MATD SIN A MATC STKB OuUTPUT ENABLEH l | ' — SSE:‘IISZESAOOS I — SINA:SINF DRVC Y READ SINK TIME I DRVC Y ' 11 | X 8Y DRIVE | WRITE lf 3 Y READ Y WRITE > CONTROL DRVC READ SOURCE TIME(X&Y) o —— — 5 Y X PWD 7:0 | XNRD 7:0 “DRIVER DRIVER DRVC } DRVC A04:A02, AO1 T DRVC DRVB DRVB } DRVC X WRITE SOURCE TIME I IN15:IN 0O I I I AOSH:AOTH -1 J‘ SINA:SINF : INHIBIT DRIVERs [, D15-DOOL INHA: INHF f| INHIBIT || CONTROL I I X DRIVER ADDRS DRVB BUS DATA <JD15'-DOO) 1 — —] l DRIVER : Y DRIVER 'ADDRS ' —— — | BUS TRANSCEIVERS SINA CLEAR MDR 1:0 L : XWRITE | XREAD | DRVC XREAD SINK TlMELl I DRIVER | > DRVB e — YNRD7:0 | Y PWD 7:0 SOURCE TIME |DRVC READ SINK TIME L(X8Y) GATING — BUS D15.DO0OH SINA:SINF ' SINA CLK MDR1:0 L I — xEEGTsOTg %%2) GATING | INHA:lNHF; ‘5 A‘ | - — | - | | I | * I I X&Y READ CURRENT SOURCE ‘ DRVB MATD I I I I STK DELAY LINE CHG H CONTROL GATING ] MATD il MATD WRITE MATD WRITE EARLY L l I I LATE L MAT D INH TIME H — I 'I DL3 DL4 ‘ BUFFER GATING -| | fats 7 | DELAY LINE DELAY LINE { | | I I I | CORE /:——1 stack mobuLE ]l MATC READ EARLY L MATB i Y SELECT LINES | | DRIVER MODULE I | l SENSE DRVA DRVB Y127:Y00 l |, P/0 G235 - MATC READ LATE L l I i ' | | | | | | I DVvRC D — || I | | MATC OUTPUT ENABLE - H | | l I MATC ENDSTROBEL YS15:YS00 Y gwfiTfiNT X127: X00 — —— —— — — MATB,MATC MaTH ] 27 TE MASKING 1z L ADDR SOURCE TiME CIRCUITSe a | .| XSELECTLINES STKA LINE MATS INIT L MATJ DRVA STROBE MARGIN O3H Y SWITCH ‘ STACK CHARGE | CONTROL GATING _______ I | DRVC SWITCH i | | I - waTc |.MATB CLK MDR 1:00L BUS INIT L I 3 AOSH. AN AOGH LATE L [~ T 7] MATB MSYN L MATB 0-250NS MATC READ LOCKOUT H MATE :MATF creot I | | MATC MATH I oL DELAY LINE MATB MATE REA BUS TRANSCEIVER AND I 250N/S DLY H DELAY LINE | MATB MATA MATB LOCK MAR 21 L i DLz | yumpers DRVB DRVC X WRITE SINK TIMEL | XXS15: X800 CURRENT I I CONTROL |[W7:W1 [BUs I' X SWITCH ADDR | DRVC STACK SEL L 6 &- I I PIN T T | | orvex rean source Tine | E3 e rs 114 SENSE INHIBIT MODULE N2 1 T O G235 DRIVER MODULE UNIBUS TIMING MODULE (M8293) - 16K | DRVC WRITE X8&Y DRIVE CONTROL GATING DRVC | BIAS SOURCE l DRVD GENERATOR SINK TIME L(X&Y) l > I ggg&c?%‘fl%(xafi X&Y WRITE CURRENT SOURCE | l )| ; : | r | l READ TIMEH 11-1780 Figure 2-1 MF11-U Detailed Block Diagram 2-3 UNIBUS fl —J + 5V +20V % L——_—_—- | BUS INITL MATJ MATJ 1Z TO 1Z H L BASE OF Q11 ON G235 DRIVER MODULE DCLOL _| | 8 MATJ MSYN HOLD OFF H _ PWR OK H TO | Rpo SINA I BIAS I RETURN R18 - S AN\r ~ I D2 i 2 D3 ey ' R21% -5y D4 7 R26 -5V C44 - MAT 1Z L G114 SENSE INHIBIT MODULE - — ~— — ~ opmwa rwr ok L | +5V R43 R43 ' l D1 D2 - . . Figure 2-3 FROM — — — — +20V D3 R23 c2 I | | | |l +20V 16K UNIBUS TIMING MODULE R21 I Q9 R20 6 X-Y CURRENT GEN. o } I SINA POWER FAIL L TO INHIBIT DRIVERS (SINB‘SlNF) | R45 » Q1 I Bias Current Detection Circuit 2.2.2 Loss of Bias Current If there is a loss of bias current, the current generators (G235-0-1, sheet 6) must be inhibited from turning on. If the current generators are turned on without bias current, it is possible that the saturating transformers may not sufficiently limit the inhibit current. The bias current source is applied to the inhibit drivers on the G114 Sense Inhibit Driver Module and is returned to the 16K Unibus timing module as a SINA I BIAS RETURN signal. This signal is detected by the differential amplifier in Zone C-7 (Figure 2-3). The bias current is returned to ground through R19, generating a slight voltage across R19 which is detected by the differential amplifier. If the voltage across R19 is not sufficient, the amplifier output goes high and turns on transistor Q10. This action causes transistor Q9 to turn off and also causes the X-Y current generators to turn off in a manner similar to that described in Paragraph 2.2.1. TN P U S G235 DRIVER MODULE TN P DU /—-\\ 111750 CHAPTER 2 16K UNIBUS TIMING MODULE 2.1 INTRODUCTION This chapter describes the M8293 16K Unibus Timing Module employed with the MF11-U/UP Core Memory system. The chapter is divided into three major sections — memory protection circuits, operation mode selection logic, and control logic. This circuitry is shown on diagram M&8293-0-1. Figure 2-1 represents a detailed block diagram of the memory and depicts how the 16K Unibus timing is tied into the core memory system. 2.2 MEMORY PROTECTION CIRCUITS The memory protection circuits contain the logic to detect BUS INIT L and DC LO L from the Unibus. They also contain the circuitry to detect loss of bias current. 2.2.1 DCLO and BUS INIT One of the functions of the M8293 16K Unibus Timing Module is to detect BUS INIT L and DC LO L from the Unibus. Either signal causes MATJ MSYN HOLDOFF H to be asserted (Figure 2-2). This signal inhibits the initiation of any new memory cycles. A delay circuit consisting of Q1 and Q2 and associated external components (sheet MATJ of M8293-0-1) causes MATJ IZ L and MATJ IZ H to be generated after a 3 us delay. The IZ signals are used to initialize the 16K Unibus timing module, while the 3 us delay allows the memory to complete any current cycles that were in progress at the time of BUS INIT L or DC LO L. In addition, MATJ IZ L is applied to Q11 on the G235 Driver Module causing Q11 to conduct and Q10 to go to saturation. This drives PWR OK H low (Figure 2-3) and inhibits the X-Y current generators (Q1 through Q4). Transistor Q9 is turned off so that DRVA PWR OK L is no longer asserted. On the G114 Sense Inhibit Module, this drives Q1 (G114-0-1, sheet 3) into saturation and asserts SINA POWER FAIL L which prevents the inhibit drivers (G114-0-1, sheets 4 through 8) from turning on. NOTE With DC LO L asserted, the operation occurs as described above even though the +5V and -5V power supplies are turned off. The memory protection circuits will operate even if the +20 V power supply is just above +5 V. If the +20V supply produces less than +5 V, the circuits may not operate properly; this makes no difference, however, as no substantial driver currents are generated. 2-1 NOTE | If the G235 Driver Module is removed from the system unit, DRVA PWR OK L remains unasserted and transistor Q1 on the G114 Sense Inhibit Module prevents the inhibit drivers from being turned on. 2.3 OPERATING MODE SELECTION LOGIC When the memory is addressed by the master device, one of four bus operations (DATI, DATIP, DATO DATOB)is selected. The selection is determined by control bits CO1 and C00 and address bit AOO which selects the high or low byte in a DATOB. These control signals are placed on the Unibus by the master device. Table 2-1 shows the state of these bits for each type of bus operation. Table 2‘-1 Selection of Bus Transaction Mode Control Transaction Mnemonic Data In DATI C(01:00) | 00 | Octal Control A0O -0 Function X Data from memory to master. Memory performs read and restore operations. Data In, Pause DATIP 01 1 X ’ Data from memory to master. | Restore operation is inhibited. Must be followed by DATO or DATOB which performs a write operation without the initial clear. Data Out DATO 10 | 2 X Data from master to memory (words). - Data Out, High Byte DATOB 11 3 1 Data from master to memory. High byte on data lines D(15:08). Data Out, DATOB 11 3 0 Low Byte Data from master to memory. Low byte on data lines D(07:00). X = irrelevant The logic that decodes the bus operation and byte selection is shown on M8293-0-1, sheet MATH. Bits BUS CO1, BUS C00, and BUS AOQO are supplied to three receivers from the Unibus. The receivers for BUS C00 and BUS CO1 are located on sheet MATH and the receiver for BUS AQO is located on sheet MATF. The BUS CO1 and BUS C00 signals are applied to a bistable latch and generate both polarities of MATH CO and MATH C1. These signals are combined with MATF AO0O and generate both polarities of MATH WRITE BYTE (0) and MATH WRITE BYTE (1) These signalsin turn, are used to enable the following signals: MATB CLK MDR 0 L MATB CLK MDR 1 L MATB CLEAR MDR 0 L MATB CLEAR MDR 1 L DRVA SSO L DRVA SS1 L In addition, MATH C1 L is used to enable MATC OUTPUT ENABLE H. These signals are listed in Table 2-2 which tabulates the memory operating signals generated for each of the bus operations. To avoid confusion in interpreting the transactions listed in Table 2-2, the purpose of the PAUSE flip-flop is discussed briefly. During DATIP, the PAUSE flip-flop is set during the read operation which inhibits the restore (write) operation. The DATIP must be followed by a DATO or DATOB on the same address. The DATO or DATOB that follows a DATIP is shorter than a standard DATO or DATOB because the initial clear operation is eliminated. In Table 2-2, the suffix PAUSE L identifies the standard transactions; the suffix PAUSE H identifies the DATO and DATOB transactions that must follow a DATIP. | Table 2-2 | Generation of Memory Operating Signals ~Signals Generated an ol Byte Mode | Control A00 Mode Control | State of | PP f co1 |co2 Sz |2 5 E % 5 - =| fi E | S % , =) S 5 = - - Operational Sequence |8|2|5 22|22 == SIS =) = ) |B|EIE|E|E & | & || lg | < | < Qlal|l=]1=]|1=| = | = DATI X 0 | 0 | Reset DATIP X 0 |1 = é PAUSE | = | o Flip-Flop | & | 7 | =N VIiVvIiVvIiV |ResetSet|~ | vV |V v/ | Read-restore. |V v/ | | DATO X PAUSE L DATO Read-pause. Restore inhibited by PAUSE flip-flop. 1 | 0 | Reset VAR IRV Clear-write 1 | 0 | Set VAN IRV Write. Must follow DATIP. | X PAUSE H DATOB | 0 1 1 Reset vV v |V Clear-write selected byte O. PAUSE L Read-restore nonselected | DATOB 0 1 byte 1. 1 | Set v |V | PAUSE H Write selected byte 0. Re- » store non-selected byte 1. N DATOB 1 1 1 Reset N4 Must follow DATIP. vV Vi PAUSE L DATOB Clear-write selected byte 1. - | Read-restore nonselected | PAUSE H | 1 1 1 Set | vV o byte 0. N4 | | Write selected byte 1. Restore non-selected byte O. Must follow DATIP. X = irrelevant 2.6 2.3.1 Operating Modes 2.3.1.1 Master Sync — In a bus operation, the master device always times the MSYN signal to ensure that MSYN does not reach the slave device prior to the time that the address and control lines on the Unibus have been decoded and are stabilized. Consequently, the bus receiver outputs for the address and control signals indicate the address and mode of the next bus cycle at least 75 ns before BUS MSYN L is received. This 75 ns delay is necessary to allow time for: a) device selection, b) address decoding, and ¢) mode selection. 2.3.1.2 Slave Synchronization (SSYN) Circuit — Slave synchronization (SSYN) is the response of the slave device to master synchronization (MSYN). The master places address information, mode control information, and data (if a DATO or DATOB is selected) on the Unibus. It then asserts BUS MSYN L only if BUS SSYN L from the previous slave device is cleared, which indicates that the bus transactions can be accomplished. The slave asserts BUS SSYN L when it has data to send (DATI or DATIP) or when it has received data (DATO or DATOB). The master receives BUS SSYN L in either case and clears BUS MSYN L. When the slave receives the cleared BUS MSYN L, it clears BUS SSYN L, which frees the bus. This brief statement of the SSYN/MSYN interaction is necessary to understand the operation of the memory SSYN circuit. Details of the SSYN/MSYN interaction during all bus transactions can be found in the PDP-11 Peripherals Handbook. 2.3.1.3 Device Selection — In order to select the memory, the address lines BUS A17:A01 L must indicate one of the 16K word addresses starting at the minimum address selected by jumpers W7 through W3. The 7485 IC (E32) on M8293-0-1, sheet MATA, examines the received address and compares it with the minimum address configured by jumpers W7 through W3. This address is the initial address in a 16K bank. The output (pin 5) of E32 is asserted if the received address is equal to or greater than the address specified by the jumpers. The output (pin 7) of the other 7485 IC (E29) is asserted if the received address is less than the jumper address plus 16K, which means that the address is in the specified bank. If both pin 5 of E32 and pin 7 of E29 are asserted, the device is selected and MATA BANK SEL L is asserted. BANK SEL L will also.be asserted if the starting address jumpers are cut for 112K, 116K, or 120K and pin 5 of start address comparator E32 is asserted. If interleaving is employed, BANK SEL L will be asserted if the starting address jumpers are cut for 96K or higher and pin 5 of E32 is asserted. NOTE BANK SEL L will always be inhibited for bus addresses between 124K and 128K. These addresses are reserved for hardware registers and peripheral devices. 2.3.1.4 Address Decoding — Bus address lines (A14:A01) are received by type 380 bus receivers (sheets MATE, F, and H). The outputs of these receivers feed 7475 quad latches. The outputs of the latches follow the inputs prior to receipt of BUS MSYN L. The outputs of the latches are applied to the 7442 and 74154 memory address decoders on the G235 Driver Module (sheets DRVB and DRVC). The decoders decode three or four inputs to 8 or 16 mutually exclusive outputs to decode the address as shown below. a. Bits A14, A06, AO5 and AO3 are applied to a 74154 decoder (E28) to select one pair of Y read/write switches (Figure 2-4). b. c. Bits A04, A02 and AO1 are applied to a 7442 decoder (E19) to select one pair of Y read/write drivers. Bits A13, A12, A1l and A10 are applied to a 74154 decoder (E27) to select one pair of X read/write switches. d. Bits A09, AO8 and AOQ7 are applied to a 7442 decoder (E32) to select one pair of X read/write drivers. 2-7 . X il >le Y 1 1 S le— SWITCHES —»}e— DRIVERS —s}#— SWITCHES —»}e- DRIVER— MAD N bR DORESS 13|12 (11|10 S (7442,74153) ADDRESS LATCHES (7475) ~ 14 |13 UNIBUS ADDRESS| 14|13 |12 | 11 9|8 |10 ] 9 |12 | 11|10 | 9 ' 8 |7|1a|6|5]|3|4|2]|1 71 61|65 4 13 2 1 5 4 13 2 |15 6| 8 |7 *BUS AO1 L IS USED WHEN NOT INTERLEAVED BUS A15 L IS USED WHEN INTERLEAVED Figure 2-4 11-1776 Switch and Driver Selection Selection of the appropriate X and Y read/write drivers is accomplished prior to the receipt of BUS MSYN L. The switches and drivers are not turned on, however, until a timing cycle is initiated by BUS MSYN L and MATA BANK SEL H (Paragraph 2.5.2). 2.3.1.5 Mode Selection — The operating mode is determined by BUS CO L and BUS C1 L. The four operating | | modes are: Mode BUS COL BUSCIL DATI DATIP DATO H L H H H L DATOB L L Description Read—restore Read—pause ~ Clear write Clear (byte)—write (byte) The DATOB cycle refers to byte operation and performs a clear /write cycle on the byte indicated by BUS AOO L and a read—restore cycle on the other byte. The CO, C1, and AO signals are treated similar to the address signals (received and stored in 7475 latches). The byte masking logic (on MATH) uses the C00, CO1, and AQO signals to generate both polarities of MATH WRITE BYTE O and MATH WRITE BYTE 1. These signals are used to indicate whether a clear—write operation or a read—restore | operation is to be performed on the respective bytes: Figure 2-5 shows the timing for the DATI mode, Figure 2-6 shows the timing for the DATIP mode, and Figure 2-7 shows the timing for the DATO or DATOB mode. These timing diagrams, in conjunction with the overall flow diagram of the 16K Unibus timing module and the detailed flows, should provide the reader with the necessary information to understand and repair the timing module. 2-8 200 100 0o I I I I I I BUS MSYN L _—I I * I l I I & | \ | MATB READ LOCKOUT H B 1 MATD STACK CHG H MATB LOCK MAR 2:1L I J / [ | MATC READ EARLY L 1000 900 800 700 600 500 400 300 | L MATC READ LATE L MATC END STROBE L | | N | MATC OUTPUT ENABLE H L \ | BUS SSYN L 1W BUS DATA L | | MATD INH TIME H MATD WRITE LATE L l f MAT CLEARMDR1:iOL —I___Ji NOTE: % Actual time depends on bus and processor delays. DATI BUS C@ =H BUS C1 =H Figure 2-5 0 DATIP BUS CO=L BUSC1=H followed by 200 300 400 DATOB or MATB LOCK MAR L BUS CO=L MATC READ EARLY L 600 700 800 900 1000 1100 DATO, ~ — TM DATOB | I| N i| J MATB READ LOCKOUT H BUS CO=H 500 pl BUS MSYN L __I MATD STACK CHG H DATO 100 n-1777 DATI Mode Timing Diagram \ ! l f L | | BUS Cl=L BUS Cl=1L | | J | | | | I MATC READ LATE L | MATC END STROBE L // T | i | l | 1 MATC OUTPUT ENABLE H | | | | | | | BUS SSYN L | J | | MATD INH TIME H * | | | BUS DATA L { | | 1} MATD WRITE LATE { L ! MATB CLEAR MDR1:O L MATB CLOCK MDR 110 | + I | | ] L I r MATB PAUSE H I L | NOTE: % Actual time depends on bus and processor delays. 11-1778 Figure 2-6 DATIP Mode Timing Diagram 2-9 0 | BUS MSYN L 100 200 300 400 500 600 700 800 900 1000 | I I I [ I I | | L MATB READ LOCKOUT H MATD STACK CHG H MATC READ EARLY L I | L MATC READ LATE L BUS SSYN / L//"N MATB LOCK MAR L I MATD INH TIME H MATD WRITE LATE L MATB CLEAR MDR 1.0 L %= | I MATB CLOCK MDR T.0 L % %x I l MATC END STROBE L J DATO BUS CO =H ‘NOTES: BUS Ct1=L OR 1. * Actual time depends onbus and processor delays. 2. ¥» |In the DAT1 DATOB, CLEAR MDR L only occurs in the byte not being addressed. BUS Co=L 3. x%xIn the DATOB, CLOCK MDR in the byte being BUS Ci=L L only occurs addressed 2.3.1.6 \\w//’ i 11-1779 Figure 2-7 DATO, DATOB Mode Timing Diagram DATI MODE (Read—Restore) — In this mode, MATH WRITE BYTE 0 H and MATH WRITE BYTE 1 H are not asserted. BUS MSYN L is asserted by the processor or master and generates MATB MSYN H. If the READ LOCKOUT f{lip-flop is not set and MATA BANK SEL H is asserted, MATB A EARLY L is asserted. This signal is applied to the driver module (G235-0-1, sheet 4) to start X and Y read currents flowing. | In addition, MATB MSYN L is applied to the delay line driver gating (E11 on sheet MATB) and will start a voltage pulse down DL?2 if the following conditions are met: a. MATJ MSYN HOLDOFF H is not asserted (indicating that neither BUS INIT L nor BUS DC LO L is asserted). b. MATA BANK SEL L is asserted. C. MATB READ LOCKOUT H is not asserted. The voltage pulse going down the delay line will first assert MATB START READ H which does the following: a. Latches the delay line driver gating on so that the only thing which will turn off the voltage applied to the delay line is the assertion of MATB READ LOCKOUT H. b. Causes MATB CLEAR MDR 0 L and MATB CLEAR MDR 1 L to be asserted (clears the data register so that new data read from memory can be stored). 2-10 Causes MATB LOCK MAR 2 L and MATB LOCK MAR 1 L to be asserted (this sets the LOCK MAR flip-flop) which locks the address and control latch outputs to their latest state. Causes the END WRITE flip-flop (on MATD) to be reset (this flip-flop was set by the previous cycle) Since MATC SSYN L is now unasserted this allows MATD END OF WRITE L to be unasserted — thus enabling the READ and WRITE LOCKOUT flip-flops to be set at the appropriate times. Causes MATD MSYN STILL LO L to be asserted. This signal stays asserted until BUS MSYN L goes unasserted. Sets the READ EARLY f{lip-flop. 75 NS DELAY LINE TAP — sets the READ LATE fhp-flop. 75 NS DELAY LINE TAP — sets the READ LOCKOUT flip-flop which turns off the input to the delay line and hence determines the width of the pulse traveling down the delay line. 150 NS DELAY LINE TAP — sets END STROBE f{lip-flop. — feeds the output of DL2 to the input of DLI. 250 NS DELAY LINE TAP 300 NS DELAY LINE TAP — resets END STROBE flip-flop. Sets the OUTPUT ENABLE flip-flop allowing data to be gated onto the Unibus. (This flip-flop is reset when BUS MSYN L is cleared.) Resets READ EARLY flip-flop.- 325 NS DELAY - starts the restore cycle by turning on the write delay hne driver. (ThlS starts a voltage pulse down DIA.) 350 NS DELAY LINE TAP — resets READ LATE flip-flop. Causes BUS SSYN to be asserted. (The SSYN flip-flopis reset when BUS MSYN L is cleared.) WRITE 0 DLY H — sets the STACK CHARGE fl1p-flop wh1ch generates MATD WRITE EARLY L. Latches the write delay line driver gating so that only the WRITE LOCKOUT flip-flop can terminate the voltage pulse applied to DILA. WRITE 25 NS DELAY LINE TAP — sets INH flip-flop. Sets WRITE LATE flip-flop. WRITE 1»25 NS DELAY LINE TAP — sets the WRITE LOCKOUT f{lip-flop, terminating the voltage pulse traveling down DIA. WRITE 350 NS DELAY LINE TAP — resets INH flip-flop. WRITE 375 NS DELAY LINE TAP — resets STACK CHARGE flip-flop which causes MATD WRITE EARLY L to be unasserted. WRITE 400 NS DELAY LINE TAP — clears the WRITE LATE flip-flop. WRITE 450 NS DELAY LINE TAP — resets the LOCK MAR flip-flop, allowing the latch outputs to once more follow the inputs. When the trailing edge of the voltage pulse has passed this tap and is still present at the end of the delay line, the END WRITE flip-flop is set. When MATC SSYN L is unasserted, MATD END OF WRITE L is asserted, causing the READ and WRITE LOCKOUT flip-flops to reset. This allows a new memory cycle to be initiated upon receipt of a new BUS MSYN L 2-11 2.3.1.7 DATIP Mode — The DATIP mode is the same as the DATI mode except that the 300 ns delay line tap sets the PAUSE f{lip-flop instead of causing a voltage pulse to start down the write delay lines. this memory must follow the DATIP cycle before any other bus cycles. A DATO or DATOB to | 2.3.1.8 DATO (Clear—Write) — The DATO eycle not preceded by a DATIP cycle (PAUSE flip-flop not set) is the same as the DATI cycle with the following exceptions: a. MATH WRITE BYTE 0 AND MATH WRITE BYTE 1 are both asserted. b. MATB CLK MDR 0 L and MATB CLK MDR 1 L are asserted instead of MATB CLEAR MDR O L and MATB CLEAR MDR 1 L. The clock signals are generated by the assertion of MATH WRITE BYTE 0 2.3.1.9 DATO — The DATO cycle preceded by a DATIP cycle (PAUSE flip-flop set)is similar to the DATI cycle with the following exceptions: a. When MATB MSYN H is generated it does not start a pulse down the read delay line since the READ LOCKOUT fl1p flop is set. b. As a result of PAUSE being set, MATB CLK MDR 0 L and MATB CLK MDR 1 L are generated to clock the new bus data into the data register. This also causes BUS SSYN L to be asserted. This 31gnal will drop when BUS MSYN L drops. C. A voltage pulse is sent down the write delay lines causing the same sequence of events as the write portion of a DATI cycle. This portion of the cycle is initiated by the 300 ns delay line tap in a DATI mode. 2.3.1.10 DATOB Mode — The DATOB mode is the same as the DATO mode except that AOO indicates the byte selected for the write operation. A read—restore cycle is performed on the non-selected byte. The byte masking logic on sheet MAT.1 WRITE BYTE O H or MATH WRITE BYTE 1 H depending on the value of A0O. 2.4 2.4.1 DEVICE AND WORD SELECTION Introduction When the processer or a peripheral device desires to perform a transaction with the rflemOry, the processor asserts an 18-bit address on Unibus address lines A(17:00). Fourteen bits A(14:01) indicate the address of a specific word within the memory. Address bit AQO is used to select the byte (8 bits) transaction when in the DATOB mode. The memory address is decoded by the device selection circuit on the M8293 16K Unibus Timing Module. The word address is stored in a register on this module whose output is decoded to activate the X—Y line switches and drivers that select the addressed word. These circuits contain jumpers that are included or excluded to configure the memory as follows: establish a specific device address; and select interleaved or non-interleaved operation. The device address is a 16K bank, starting on any 4K increment selected by the five device select jumpers. Table 2-3 lists the function of the address bits (Figure 2-4). i reset when BUS MSYN L is cleared. ez’ BUS SSYN L is asserted by MATB CLOCK MDR O L or MATB CLOCK MDR 1 L. The SSYN f{lip-flopis | . C. / and MATH WRITE BYTE 1 and allow the data to be clocked from the Unibus into the data register. Table 2-3 Addressing Functions Bus Address Function A0O Controls Byte Mode AO1 Non-Interleaved Mode: becomes AO1H to M8293 Interleaved Mode: goes to Device Selector A02, A04, AO1H* Decode Y Drivers AQ3, A0S, AO6, Al4 Decode Y Switches A07, A08, AO9 Decode X Drivers Al10, Al11, A12, Al13 Decode X Switches Al5 -~ Goes to Device Selector Interleaved Mode: becomes AO1H to M8293 Al13, Al4, Al6, Al17 Goes to Device Selector * AO1H could be a Unibus address bit 1 or 15 depending on the interleaving jumpers. 2.4.2 Memory Organization and Addressing Conventions Prior to a detailed discussion of the address selection logic, it is desirable to understand memory organization and addressing conventions. The memory is organized in 16-bit words, each consisting of two 8-bit bytes. The bytes are identified as low and high as shown below. T | 15 Mse [ T T HIGH (N N 1 BYTE NN T T T T T 1 L1 ] LOW BYTE S 08 07 N R DATA BITS D<I5:00> B 00 LSB H-1174 Fach byte is addressable and has its own address location; low bytes are even numbered and high bytes are odd numbered. Words are addressed at even-numbered locations only; the high (odd) byte is automatically included. For example, a 16K word memory has 16,384 words or 32,768 bytes; therefore, 32,768 locations are assigned. The address locations are specified as 6-digit octal numbers. The 32,768 locations are designated 000000 through 077777 as shown in Figure 2-8. 2-13 o] 8|7 15 N «———16 BIT WORD——— LOW BYTE HIGH BYTE 000001 000000 000003 000002 000005 000004 o7r7773 O7T7772 077775 077774 or7r777 Q77776 11-1789 Figure 2-8 Memory Organization The address selection logic responds to the binary equivalent of the octal address. The binary equivalent of 017772 is shown below as an example. ADDRESS 17116 (15|14 0] 0] 0| ) |13 0]|O 1 (12|11 |10 1 111 1 BITS A<17:00> (09|08 1 7 |07 1 7 |06|05|04(03 02|01 (00 BIT POSITION 1 0 0 BINARY 1 1 1 7 1 2 OCTAL =173 Each memory bank requires its own unique device address. For example, assume that a system contains three 16K memory banks as shown in Figure 2-9. The device selector for the 16K non-interleaved memory decodes five address lines [A(17:13)] . Examination of the binary states of these lines for the three memory banks shows that the changes in the states of bits A15 and A16 allow the selection of a unique combination for each bank. The combination, which is the device address, is hardware selected by jumpers in the device selector. 2.4.3 Device Selector The device selector is located on the 16K Unibus timing module. Address bits AO1 and A(17:13) are decoded in the ~device selector to provide the device selection signal MATA BANK SEL L that is used in the control logic. Two comb1nat10ns of these bits are decoded depending on the memory configuration as shown below. Memory Configuration Address Bit 16K Words (non-interleaved) A(17:13) 16K Words (interleaved) AO1, A(17:13) 000000 077777 17 16 15 ( 1ST ADDRESS| o 0 o | o 14 - BANK 1 é 16k WORDs | BANK1 | LAST ADDRESS| © 13 12 0 0 - 0 0 1 1 1 . 0 [ 1ST ADDRESS| 100000 177777 7 | © 0 A 1 0 1 BANK 2 g 16Kk WORDs | BANK 2 LAST ADDRESS| © 0 0 1 1 1 1 ( 1ST ADDRESS| O 200000 277777 BANK 3 16K worDs | BANK 3 J 1 0 - 1 7 0 0 2 : 0 0 - 0 _ pon LAST ADDRESS| o 1 0 1 1 1 N 2 7 11-1788 Figure 2-9 Address Assignments for Three Banks Of 16K Words Each Five jumpers (W1, W2, W8, W9, and W10) in the device selection logic on the control module are used to control interleaved or non-interleaved operation of the 16K memory. For non-interleaved operation W1 is in and W2, W8, W9, and W10 are out. Table 2-4 shows the jumper configuration for non-interleaved memory addresses up to 124K. Each memory bank must have its own unique device address field. Five jumpers (W3, 4, 5, 6, and 7) in the device selector provide this capability. In drawing M8293-0-1, sheet 2, all the jumpers are shown in place and the device selector would respond only when high signals appear on the Unibus address lines A(17:13). Some jumpers can be removed to allow the device selector to respond to a particular combination of high and low signals on these address lines. All highs at the inputs of the 380 Unibus receivers give lows at their outputs. Each receiver output goes to two comparators; one to determine if the bus address is above the minimum address of the field and one to determine if the bus address is below the maximum address of the field (M8293-0-1, sheet MATA). The other inputs of the 7485 gates associated with bits A(17:13) can be connected to +5 V or ground, depending on whether or not jumpers W3 through W7 are installed. The input is low (ground) with thejumper in; and input is high (+5 V) with the jumper removed. To contfigure the jumpers for a specific device address, find the binary equivalent of the assigned octal starting address and insert a jumper in each bit position that contains a 0. 2-15 Table 2-4 Device Address Jumpers (Non-Interleaved) Memory Bank Machine Address (Words) (Words)s | W3 Al7 0-16K 4-20K 000000-077776 020000-117776 IN IN 8—24K- 040000-137776 IN 100000-177776 IN 12—28K 16—32K 20—36K 060000-157776 120000-217776 - IN W4 Al6 W5 Al5 W6 Al4 - W7 IN IN IN IN IN IN IN OUT IN OUT IN -~ IN IN OUT IN IN OUT ~IN IN IN OUT IN IN IN IN IN IN 48— 64K a 300000-377776 IN OUT OUT N IN 52—68K 320000-417776 340000-437776 IN IN OUT OUT IN OUT 60—76K 360000-457776 IN OUT OUT OUT 420000-517776 OUT 56—72K 64—80K 400000-477776 72—88K 76—92K 80—96K 84—100K 88—104K 440000-537776 460000-557776 500000-577776 520000-617776 540000-637776 68—84K | OUT OUT IN OUT OUT OUT OUT OUT IN IN IN N IN IN OUT OUT IN IN OUT OUT "IN 140000-237776 160000-257776 200000-277776 220000-317776 240000-337776 260000-357776 - OUT OUT IN IN IN I IN OUT 24—40K 28—44K 32-48K & 36—52K 40—56K 44—60K | IN IN OUT OUT OUT ouT OUT Al3 OoUT | OUT O IN IN IN oUT IN IN OUT OUT IN IN OUT IN OUT 'IN OUT IN IN IN IN OUT oUT - OUT IN OUT IN OUT IN OUT OUT 92—108K 560000-657776 OUT IN OUT OUT OUT 96—112K 600000-677776 OUT OUT IN IN IN 112—-124K 700000-757776 OUT OUT IN IN IN OUT OUT IN 100—116K 104—120K 108—124K 116—124K 120—124K 620000-717776 640000-737776 660000-757776 OUT - OuUT OUT 720000-757776 OUT 740000-757776 OUT OUT OUT OUT IN IN IN OUT OUT OUT ouUT . OUT IN OUT OUT NOTE: The memory may be interleaved in 32K increments, using two contigously addressed 16K banks. In the 16K interleaved memory configuration the following changes must be made: W1 is cut W2 is in W8 is in WO is in W10 is cut WO is cut is in W10 For one 16K of the interleaved pair For the other 16K of the interleaved pair Both interleaved memories should be cut for the same starting address. 2-16 OUT IN OUT Table 2-5 shows the jumper configuration for interleaved memory addresses up to 124K. When interleaving, two contigously addressed 16K memory banks must be interleaved. Table 2-5 Device Address Jumpers (Interleaved) Memory Bank Machine Address W3 W4 W5 W6 W7 (Words) (Words)s Al17 Al6 Al5 Al4 Al3 IN 0—32K 000000-177776 IN IN IN IN 4—-36K 020000-217776 IN IN IN IN OUT 840K 040000-237776 IN IN IN OuT IN - 12—-44K 060000-257776 IN IN IN OuT ouUT IN 16—48K 100000-277776 IN IN OuUT IN 20—52K 120000-317776 IN IN - OouT IN OuT 24—56K 140000-337776 IN IN OouT OouT IN 28—60K 160000-357776 IN 32—-64K 200000-377776 IN OUT IN IN IN 36—68K 220000-417776 IN ~OUT IN IN OuT 40-72K 240000-437776 IN OuT IN ouT IN 44—T76K 260000-457776 IN OuT IN OouT OUT 48—80K 300000-477776 IN OouT ouT IN IN 52—84K 320000-517776 IN ouT OouT IN OUT 56—88K 340000-537776 IN OUT OUT OuT IN 60—92K 360000-557776 IN OouT ouT OouT OUT 64—96K 400000-577776 OUT IN IN IN IN IN IN 72—104K 440000-637776 ouT IN IN OouT IN 76—108K 460000-657776 OouT - IN IN OuT OuT 80—112K 84—116K 88—120K 500000-677776 520000-717776 540000-737776 OuT ouT OuT IN IN IN OuUT ouT OuT IN IN OuUT IN OuT IN 68—100K 420000-617776 IN OuT OUT OuUT IN . OuUT ouT 92—124K 560000-757776 ouT IN ouT OuT OuT 96—124K 100—124K 104—-124K 600000-757776 620000-757776 640000-757776 OUT OouT OouT OUT ouT OuT IN IN IN IN IN OUT IN OouT IN 108—124K 660000-757776 ouT - OUT IN OouT OUT 112—-124K 116—124K 120—124K 700000-757776 720000-757776 740000-757776 OouT OuT OuUT OuT OuT OouT ouT OuUT OouT IN IN OuT IN OuT - IN NOTE: If interleaving is desired, the memory must be interleaved ‘in 32K increments, using two contiguously addressed 16K banks. 24.4 Word Selectibn Word selection requires two levels of decoding. The word address bits are placed in the 14-bit word address register. Outputs from the register are used as inputs to a group of decoders (Figure 2-10). The outputs of the decoders select the proper X and Y read/write switches and drivers. 2-17 1 [Vis293 16K UNIBUS TIMING MODULE A | A(17:13) | : ' | I | DEVICE » BANK SEL L SELECTOR TO CONTROL LOGIC | | AO1 I wn | = | ' - | I | o1 A(14:02) R , ) I | | \} A14H - AOTH | TO DECODERS FOR REGISTER X-Y SWITCHES AND DRIVERS | I I L Figure 2-10 WORD ADDRESS | e Jd Device and Word Address Selection Logic Block Diagram Word Address Register — The word address register is contained on the 16K Unibus timing module. The circuit schematic is shown in drawing M8293-0-1. The register is composed of 4 quad 7475 D-Type latches. They are identified as E16, E20, E24, and E36. The word address register cannot be directly cleared or preset; its output responds only to the signal at its D (data) input. Address bits A(14:02) are picked off the Unibus via type 380 quad receivers. The receiver outputs are applied to the corresponding latch inputs. The latch associated with bit AO1 receives its input from the device selector (drawing M8293-0-1). The input signal is MATA LEAST BIT H, which is obtained from bit AO1 Unibus receiver for a 16K non-interleaved memory. For a 16K interleaved memory, MATA LEAST BIT H is obtained from bit A15 Unibus receiver. The register latches are locked by MATB LOCK MAR 1 L and MATB LOCK MAR 2 L from the control logic (drawing M8293-0-1, sheet MATB). The generation and timing of this lock signal is discussed in Paragraph 2.5.2. The outputs of the latches are sent to the 7442 and 74154 X-Y line decoders on the driver module (G235-0-1, sheets 4 and 5). Prior to the generation of the MATB LOCK MAR 1 L and MATB LOCK MAR 2 L, the address lines at the outputs of the latches follow the state of the bus receiver outputs. In this way, the decoder outputs (E19, 27, 28, and 32 on the G235 Driver Module) indicate the selected address slightly before BUS MSYN is received. Hence, the X and Y drivers on the G235 module (G235-0-1, sheets 4 and 5) are turned on after receipt of BUS MSYN. 2.5 2.5.1 CONTROL LOGIC Introduction The control logic generates the precisely timed signals that initiate, control, and stop the memory operations that are requested as a result of the decoding of the bus transaction. The heart of the control logic is the delay line timing circuit (M8293-0-1, sheet MATB). For better understanding, the read and write memory sequences are described separately with associated timing diagrams. The discussion is to detailed logic level but the signals are not traced - through each component. The text is referenced to logic drawing M8293-0-1. 2-18 N - a | o 2 2.4.4.1 I 2.5.2 Timing Circuit The heart of the memory control logic is the timing circuit. When activated, it generates a series of precisely timed signals that control memory operation. The major components of the timing circuit are delay lines (DL1 to DL4) with multiple 25-ns taps (drawing M8293-0-1). The delay line outputs set and reset flip-flops to produce the control signals shown in Figures 2-11 and 2-12. NANOSECONDS 0 50 100 150 I 200 250 300 350 400 450 500 — _1 BUS MSYN MATB START o e READ H | PROVIDES BASIC TIMING FOR ALL MEMORY OPERATIONS AS IT PROPAGATES THROUGH DELAY LINES l e MATB LOCK MAR 2:1 L MATB CLEAR MDR 1:0 L MATB cLk MDR 1:0 L STARTS READ CURRENTS IN STACK ] LOCK THE ADDRESS AND CONTROL REGISTER | CLEARS DATA REGISTER FOR DATI OR DATIP AND FOR UNSELECTED | _____ [ BYTE IN DATOB | CLOCKS NEW DATA INTO DATA REGISTER FOR DATO AND SELECTED BYTE FOR DATOB MATB PAUSE H J IS SET DURING READ FOR DATIP ONLY MATC READ EARLY L TIMES READ CURRENTS - THE TRAILING EDGE OF THIS SIGNAL ENDS THE SENSE STROBE SIGNALS MATC READ LATE L OTHER TIMING FOR READ CURRENTS ; e MATC END STROBE L MATC OUTPUT I ENABLE H BUS SSYN L lDATO ,DATOB | ENABLES DATA BUS DRIVERS ‘ ON A DATI OR DATIP -|DATI , DATM— INDICATES DATA TAKEN FROM BUS (DATO, DATOB) OR DATA ON BUS (DATI,DATIP) INPUT TO WRITE TIMING CONTROL,WILL MATC 300ns / DLY H INITIATEA WRITE TIMING SEQUENCE UNLESS MATC DATIP CYCLE L IS ASSERTED 11-1748 Figure 2-11 Read Timing Sequence 50 100 150 MATD INH TIME H l__]l__JD 0 WRITE LOCKOUT H ’ MATC 300ns DLY H MATD WRITE EARLY L MATD STACK CHG H MATD WRITE LATE L | 200 250 300 350 400 450 500 550 600 INITIATES SEQUENCE WRITE IN DATO,DATOB OR DATI WRITE CURRENT TIMING l CHARGES STACK r | 1 WRITE CURRENT TIMING CURRENT TIMING INHIBIT SET WIDTH OF PULSES I L TRAVELLING DOWN DELAY LINES ' SIGNALYS MATD END OF WRITE L - EYND OF MEMORY CYCLE,RESETS READ AND WRITE LOCKOUT FLIP-FLOPS 11-1751 - Figure 2-12 Write Timing Sequence When the system is turned on the processor asserts BUS INIT L on the Unibus. This initializing signal is received and eventually asserts MATJ IZ L and MATJ IZ H as discussed in Paragraph 2.2.1. MATJ IZ L and MATJ IZ H initialize all required flip-flops in the memory and when BUS INIT L is removed, the memory is ready to accept address, control, and data. When the processor asserts BUS MSYN L a memory cycle is begun (provided the memory is not busy as indicated by MATB READ LOCKOUT H, provided the address is within the device selection limits as indicated by MATA BANK SEL L, and provided DC LO L or BUS INIT L is not asserted). AND-OR-INVERT gate E11 (sheet MATB, zone B-7) on the M8293 module determines if a memory cycle is to occur when BUS MSYN L is received. The output of E11 (Pin 8) is buffered by transistor Q3 which drives a tapped delay line DL2. The pulse width of the signal applied to the delay line is determined by setting the READ LOCKOUT f{lip-flop at the 75 ns tap of the delay line. Hence, an approximately 100 ns wide positive pulse travels down the 250 ns (tapped every 25 ns) delay line DL2, and then into an identical delay line DL1 (sheet MATC). The leading edge of this pulse traveling down delay lines DL2 and DL1 first sets and then resets flip-flops, generating the timing pulses shown in Figure 2-11 (read cycle). A similar pair of delay lines (DL4 and DL3 — sheet MATD) are used to generate the timing and control signals shown in Figure 2-12 (write cycle). These timing signals are briefly described in the following paragraphs. 2.5.3 MATB START READ H Signal This is the buffered output of transistor Q3 (zone B-6) and is the input to the read delay line DL2. MATB START READ H is 100 ns wide and occurs at the beginning of every read or clear operation. All operations from the bus (except a DATO or DATOB after a DATIP) cause this signal to be asserted. 2.5.4 MATB A EARLY L Signal The combination of MATA BANK SEL H, MATB MSYN H, and the fact that the memory is not busy causes MATB A EARLY L to be asserted. This is advance timing to inform the G235 Driver Module to turn on the Y read current generator, Y read driver, Y read switch, X read current generator and X read switch. The X read driver is not turned on at this time and waits for MATB READ LATE L. MATB A EARLY L is only 100 ns wide, but is closely followed by MATC READ EARLY L which is ORed with MATB A EARLY L on the G235 Driver Module. 2-20 2.5.5 MATB LOCK MAR 1L, MATB LOCK MAR 2 L Signals These signals are asserted when MATB START READ L is asserted. MATB START READ L sets the LOCK MAR flip-flop. This flip-flop is reset near the end of the write cycle by MATD 450 NS DLY L. At this time, the addressis no longer needed. When not asserted, the MATB LOCK MAR 1 L and MATB LOCK MAR 2 L signals allow the output of the address latches to follow the inputs to the latches from the bus receivers. The address latches are located on sheets MATE, MATF, and MATH. The outputs of the address latches are fed to the G235 Driver Module where they are decoded prior to the receipt of BUS MSYN L. When MATB LOCK MAR 1 L and MATB LOCK MAR 2 L are asserted, the address latches are locked in their present states and cannot follow the outputs from the bus receivers until the srgnals go unasserted 25.6 ~ | | MATB CLEAR MDR O L, MATB CLEAR MDR 1L Slgnals MATB CLEAR MDR 0 L clears the data register for the low byte (byte 0) immediately preceding the generation of SINA SENSE STROBE 0 H on the G114 Sense Inhibit Module. SINA SENSE STROBE 0 H is associated with reading in a DATI, DATIP, or is associated with the unselected byte of a DATOB. In a DATOB, a read-restore cycle is performed on the unselected byte and a clear-write is performed on the selected byte. MATB CLEAR MDR 1 L performs a similar operation for the high byte (byte 1). Both signals are enabled by MATB START READ H. If MATH WRITE BYTE 1 Liis enabled, MATB CLEARMDR 1 Lis generated 2. 5 7 MATB CLK MDR 0 L, MATB CLK MDR 1 L Slgnals MATB CLK MDR 0 L transfers the bus data receiver outputs into the memory- data register associated with byte 0. MATB CLK MDR 1 L transfers the bus data receiver outputs into the memory data register associated with byte 1. The transfer takes place at the beginning of a DATO or DATOB (from the selected byte only), regardless of the state “of the PAUSE flip-flop. MATD MSYN STILL LO L prevents the data register from being clocked at the end of a DATIP cycle. When this signal is asserted and PAUSE is set, it means that the BUS MSYN L srgnal from the Unibus is the MSYN due to the DATIP and has not been removed by the processor. When MSYN L is released by the processor, MATD MSYN STILL LO L goes unasserted. When the next BUS MSYN L is received (with the PAUSE flip-flop set), the data register can be clocked, for it is known to be the correct MSYN signal. After the DATIP operation, the address and control latches are left in a locked state. Since a DATO or DATOB cycle must follow the DATIP, it is necessary for MATH WRITE BYTE 0 H and MATH WRITE BYTE 1 H to reflect the new control signals (C00, CO1, and A0O) rather than the signals lockedin the latches at the beginning of the DATIP. Consequently, when the PAUSE flip-flop is set MATB PAUSE H allows the outputs of the bus receivers (sheet MATH) to designate the type of bus.operation and the high or low byte. The outputs of the bus receivers accomplish this by modifying MATH WRITE BYTE 0 H and MATH WRITE BYTE 1 H. If PAUSEis not asserted, the outputs of the address and control latches determine the type of bus operation. | 2.5.8 MATB PAUSE H Signal When MATB PAUSE H is asserted, a DATO or DATOB operation is performed in about 2/3 the time normally required. This savings in time results from the fact that the clear operation has already been performedin the DATIP portion of the cycle, and does not have to be repeated for the DATO or DATOB. MATB PAUSE H also allows MATB MSYN H to start the write sequence timing chain. This signal is generated during a DATIP operation by MATC 300 NS DLY H andis reset by MATD 125 NSDLY L from the write sequence t1m1ng 2 5.9 MATC READ EARLY L Slgnal MATC READ EARLY L and MATB A EARLY L are ORed together. MATB A EARLY L, when asserted, turnson the X and Y switches, Y drivers, and the X and Y current generators. The X drivers are not yet turned on as these drivers are what actually switch the cores. MATB A EARLY L is generated prior to MATC READ EARLY L and turns on the appropriate switches, drivers and current generators prior to READ EARLY L time. The reason for this is to allow the transients to occur as long as possible before the cores are switched. When MATC READ EARLY L is unasserted, it turns off the X and Y current generators and the X and Y read drivers. 2-21 2.5.10 MATC END STROBE L Signal MATC END STROBE L controls the trailing edge of the strobe signal, (SINA SENSE STROBE 0 H, SINA SENSE STROBE 1 H — G114-0-1, sheet 3), applied to the sense amplifiers. The leading edge of the strobe signal is variable and is determined by a one-shot (G235-0-1, sheet 6) which is triggered by DRVC X READ SINK TIME L. The one-shot time delay is controlled by Q14 which may be altered by STROBE MARGIN, This signal is varied by either grounding AV1 (STROBE MARGIN) on the G235 module or connecting it to +5 V. This moves the leading edge of SINA SENSE STROBE and SINA SENSE STROBE 1,but does not affect the trailing edge. The sense strobe signals are wide in the MM11-U Memory to allow additional time for the core outputs to be propagated along the extremely long sense lines and to propagate through the associated signal path delays. 2.5.11 MATC READ LATE L Signal MATC READ LATE L, when asserted, turns on the read X drivers which cause the read X current to start flowmg When the signal goes unasserted, the X and Y read switches are turned off. 2.5.12 MATC OUTPUT ENABLE H Signal MATC OUTPUT ENABLE H allows the bus drivers located on the G114 module to apply the output data to the UNIBUS on a DATI or DATIP operation. MATC OUTPUT ENABLE H is generated at the same time SENSE STROBE is ended and becomes unasserted when BUS MSYN L becomes unasserted. The OUTPUT ENABLE flrp flop may also be reset by PCL MSYN DISABLE L (not presently utflrzed) 2.5.13 BUS SSYN L Signal During a DATO or DATOB, BUS SSYN L is asserted by MATB CLK MDR 0 L or MATB CLK MDR 1L or during a DATI or DATIP operation by MATC 325 NS DLY H which occurs about 25 ns after MATC OUTPUT ENABLE H. When OUTPUT ENABLE H goes unasserted, BUS SSYN L and the data are removed from the bus. 2.5.14 MATC 300 NS DLY H Signal MATC 300 NS DLY H is an input to the write timing control whrch starts the write sequence (sheet MATD) unless a DATIP MODEis selected. MATC 300 NS DLY H is generated by the tap on pin 4 of delay line DLI. 2.5.15 MATD WRITE EARLY L Signal MATD WRITE EARLY L is asserted by E10 (pin 8) at the beginning of the WRITE sequence and is unasserted by a timing signal on pin 8 of DL3 (approximately 350 ns later). MATD WRITE EARLY L turns on the X and Y write current generators and X and Y switches on the G235 module. It also turns off the same current generators and switches when it becomes unasserted. - 2.5.16 | . MATD STACK CHG H Signal MATD STACK CHG H is the complement of MATD WRITE EARLY L and is used as the input to the H217 stack charge circuit to reverse bias the unselected drive matrix diodes. 2.5.17 MATD WRITE LATE L Signal MATD WRITE LATE L is the same as the MATD WRITE EARLY L signal butis delayed by 25 ns. It controls the turning on and off of the X and Y write drivers. 2.5.18 MATD INH TIME H Signal MATD INH TIME H is generated during the write trmrng sequence. Its functronis to provide timing for turning on the INHIBIT drivers. 2-22 2.5.19 WRITE LOCKOUT H Signal The WRITE lockout flip-flop (sheet MATD) primarily determines the W1dth of the pulse traveling down the delay lines DL3 and DILA4. Itis set by the 125 ns tap of DL4 and reset by MATD END OF WRITE L. 2.5.20 » MATD END OF WRITE L Signal The END WRITE flip-flop is set at the end of a write sequence The output of the END WRITE flip- flop is combined with MATC SSYN L. As soon as SSYN becomes unasserted, which means that MSYN and SSYN have gone away, END OF WRITE L is asserted which indicates completion of the memory cycle The END OF WRITE L signal resets e the read and write lockout flip-flops at the end of a write sequence 2-23 | - ~ CHAPTER 3 DRIVER, SENSE AND STACK MODULES 3.1 INTRODUCTION This chapter provides a detailed description of the MM1 1-U Memory. The detailed description covers the core array, switches and drivers, current generation, stack discharge circuitry, and sense/inhibit circuitry. 3.2 CORE ARRAY The ferrite core memory consists of 16 memory mats (18 for MF11-UP) arranged in a planar configuration. Each mat contains 16,384 ferrite cores arranged in a 128 X 128 array. Each mat represents a single bit position of a word. This planar configuration provides a total 16,384 16-bit word locations (18 for MF11-UP). Each ferrite core can assume a stable magnetic state corresponding to either a binary 1 or a binary 0. Even if power is removed from the core, the core retains its state until changed by appropriate control signals. The outside diameter of each core is 18 mil; the inside diameter is approximately 11 mil. Each core is 4.5 mil thick. | Each core is threaded by three wires, providing means for selection and core switching. X axis read/write windings pass through all cores in each horizontal row for all 16 or 18 mats. Y axis read/write windings pass through all cores in each vertical row for all 16 or 18 mats. Through the use of selection circuits which control the current applied to specific X—Y windings, any one of the 16,384 word locations can be addressed for writing data into memory or reading data out of memory. A third line passes through each core on a mat to provide the sense/inhibit functions. There is one sense/inhibit line per mat. This single sense/inhibit line, as well as the selection circuits, are discussed in subsequent paragraphs. | | 3.3 MEMORY OPERATION Figure 3-1 illustrates a typical portion of the core memory. X and Y wires pass through each core in the mat. The current passing through any one winding is such that no single winding produces a magnetic field strong enough to cause a core to change its magnetic state. Only the reinforcing magnetic field caused by the coincident current of both an X and a Y winding can cause the core located at the point of intersection to change states. It is this principle that allows the relatively simple wiring arrangement to select one and only one memory core out of the possible 16,384 contained on each mat. The current passing through either an X or Y winding is referred to as a half-select current. A half-select current passing through the X3 winding (Figure 3-1) from left to right produces a magnetic field that tends to change all cores in that horizontal row from the 1 to O state. The flux produced by the current is, however, insufficient to complete the state transition in any core. Simultaneously passing a half-select current through the Y2 winding from top to bottom produces the same effect on all cores in that particular vertical row. X3 and Y2 Note,'however, that both currents pass thfough only one core which is located at ,theintersectibri of the are sufficient to change the state of the core. The windings. This is the selected core and the combined current values arrows in Figure 3-1 show current direction for the read cycle. 3-1 INHIBIT CURRENT DRIVER AND SENSE TERMINATIO X8 . FERRITE /\/ CORES X7 —— > X6 ——— —> J X4 — > ~ SELECTED X2 i > X1 ' "SENSE/INHIBIT LINES | | > | Imse TO SENSE AMPLIFIER 11-1790 Figure 3-1 Three-Wire Memory Configuration | All X and Y windings are arranged in such a manner that whenever a half-select current is passed through each, the resultant magnetic fields combine in the core at the point of intersection. This combined, full-select current ensures - that the selected core is left in the binary 1 state. The currents used to select the core are referred to as read or write currents. A typical hysteresis loop for a core is shown in Figure 3-2. The loop is always traversed in the direction of the arrows. | » | . HYSTERESIS LOOP FOR CORE FLUX STORED OR SWITCHED INHIBIT OR READ HALF SELECT l . - 1"UNDISTURBED p—— "I"DISTURBED WRITE FULL SELECT | { FLUX CHANGE< R FOR 1 AT > DRIVE CURRENT READ TIME { "O" DISTURBED-- @ "0" UNDISTURBED-= | FLUX CHANGE AT READ{ HALF SELECT WRITE TIME FOR A"0". NOTE NO SWITCHING TAKES PLACE. . W 1" QUTPUT SWITCHES AT THE | CORE TIME CONSTANT AND IS "0" OUTPUT COMES DURING I RISE TIME AND IS A FUNCTION OF IT AND CURRENT AMPLITUDE. 25,'#‘%2#1S,EEFTNUDDEEN.T,$“JV,LL | SWITCH FASTER AND GROW AS RISE TIME IS INCREASED. DOTTED LINES SHOW HOW OQUTPUTS WOULD BEHAVE WITH DIFFERENT RISE TIMES 11-00888 Figure 3-2 Hysteresis Loop for Core In the MF11-U/UP Core Memory, the X3 windings in all 16 or 18 mats are connected in series, as are the Y2 windings. Therefore, whenever a full-select current flows through a selected core on one mat, it also flows through an identical core on the other 15 mats. The X3—Y2 cores on all mats switch to a binary 1, causing each of the 16 cores to become one bit of a 16-bit storage cell. Because of the serial nature of the X—Y windings, a method must be employed to set certain cores to the O state; otherwise, every 16-bit word selected would be all 1s. The method used in the MF11-U/UP Core Memory is to first clear all cores to the O state by reading. During the write operation, cores on particular mats are inhibited by an inhibit winding. The inhibited cores rernain Os even when identical cores on other mats are set to Is. The half-select current for the inhibit lines is applied from an inhibit current driver, which is a switch and a current source between the inhibit line and +20 V. The current in the inhibit line flows in the opposite direction from the write current in all Y lines and cancels out the write current in any Y line. There is a separate inhibit driver for each memory mat, and each mat represents one bit position of a word; thus, selected bits can be inhibited to produce any combination of binary 1s and Os desired in the 16-bit word. Remember that the inhibit function is active only during write time. The sense/inhibit lines are also used to read out information in a selected 16-bit memory cell. The specific core is selected at read time in the same manner as during the write cycle, with one notable exception: the X and Y currents are in the opposite direction than they are for the write operation. These opposite half-select currents cause all cores previously set to 1 to change to 0; cores previously set to O are not affected. Whenever the core changes from 1 to O, the flux change induces a voltage in the sense winding of that mat. This voltage is detected and amplified by a sense amplifier. The amplifier output is strobed into the data register for eventual transfer to the Unibus. Figure 3-3 shows a 16-word by 4-bit planar memory. The MF11-U/UP Core Memory functions in the same manner except that it has 128 X lines, 128 Y lines, and 16 core mats. The core stringing is identical, and the sense windings are strung through all 16,384 cores with the interchange between X63 and X64, instead of between X1 and X2. 3.4 X AND Y DECODING The basic decoding units are type 7442 and 74154 4-line to 10-line, and 4-line to 16-line decoders. The inputs are DO, D1, D2, and D3; they are weighted 1, 2, 4, and 8, with DO being the least significant bit. An output is selected according to the sum of the weighted inputs. The selected output is low and all others are high. See Appendix A for truth tables of 7442 and 74154 decoders. Each 7442 controls eight read/write driver pairs and each 74154 controls sixteen read/write switch pairs. This switch matrix is combined with the stack X—Y diode matrix to allow selection of any location out of the total 16,384 locations (see stack drawing D-CS-H217-0-1 for interconnections). The X and Y line switches are first differentiated as switches and drivers. The drivers are those switches that are connected to the diode end of the stack. Drivers and switches are further differentiated by function: either read or write. Another differentiation is made by polarity: negative or positive, depending on the physical connection. Read switches and write drivers are connected to the current generator outputs and are con51dered positive; write switches and read drivers are connected to ground and are conmdered negative. 3.5 DRIVERS AND SWITCHES Drivers and switches direct the current through the X and Y linesiin the proper dlrectlon as selected by the read and write operations. Bach switch or driver is addressed by one decoder output. A low decoder output selects the associated read and write switch or driver. The 74154 decoders are connected to switches, and the 7442 decoders are connected to drivers. | In the MF11-U/UP Memory, 16 pairs of read/write switches and 8 pairs of read/write drivers are provided in the X axis; 16 pairs of read/write switches and 8 pairs of read/write drivers are provided in the Y axis. In conjunction with the stack diode matrix (drawing H217-0-1), this allows selection of 128 lines in the X axis and 128 lines in the Y axis. This provides a 128 X 128 matrix that selects any locatlon out of 16, 384 locatlons Figure 3-4 illustrates a portion of a Y selection matrix and shows the interconnection of the diodes and the lines from the switches and drivers. It shows how 4 pairs of switches and drivers are connected to select one of 16 lines. Refer to drawing H217-0-1, for an extension of this method which uses 16 pairs of switches and 8 pairs of drivers to select one of 128 lines. 3.4 ARROWS SHOW CURRENT DURING } READ TIME TOP VIEW OF CORE MATS XSW ) l\@ N ) w ) R W R ) P P— W R >t W P ¢ X2 > X 1 > . P \\INTERCHANGE IS FOR NOISE X0 . CANCELLATION X DR YO Y1 YZA Y3A | THERE IS 1 SENSE INHIBIT WINDING PER MAT YSW \ 4 ) YSW \ 4 X A4 | % h4 & RW RW YDR | % RW RW YDR N > LINE 7 SENSE-INH BONDING MEDIUM 3 - te— GROUND PLANE PC BOARD DETAILS OF CORE STRINGING 11-1791 | Four mats shown for a 16-Word by 4-Bit Memory Figure 3-3 Three-Wire 3D Merfiory e « a drive lines. would system having be + .—i 9] I m n |RYSOO 16 Y The MF11-U/UP contains 128 Y drive lines on an 8 x 16 matrix. - JWYSOO + |RYSOH1 + RYSO? "DRIVERS A 33W | wrsoz l@s ’ + RYSO3» - |WYSO03 A 23W 13W A O3W A32R | A22R | & 12R | & O2R ' | | A 32W A 22W A 12W A O2W A 3R A 2R A 1R A O1R A 31W A 2IW A W A OiIW A 30R | A& 20R A 10R L OOR A 308 TYPICAL JUNCTION A | & 20W & 1OW Y-AXIS 4x4 SECTION & OOW I ; i ENEENE in Bl matrix this size 10A0AE : A used = ) NOTE . YPWD3 + YNRDZ |YPWD2 | + YNRD1| - vrron N YNRDO | - YPWDO | + (16 LOCATIONS) 11-1793 Figure 3-4 Simplified Y Line Selection Stack Diode Matrix To illustrate the operation of the actual X matrix or Y matrix, a smaller, but analogous, Y matrix is shown in Figure 3-4. This matrix shows four pairs of drivers and four pairs of switches for a Y axis (16 Y drive lines). Polarities are shown for convenience. The diodes are identified to assist in associating them with the drivers and switches. Each line from a twin diode interconnection to a read/write switch pair passes through 128 cores and represents one line on each bit mat. Assume that a read operation is to be performed and the word address decoders have selected read switch RYS0O and read driver YNRDI1. The Y current generator sends current through read switch RYS00 (conventional flow) which puts a positive voltage on the anodes of diodes 03R, 02R, O1R, and OOR. The non-selected read drivers (YNRD3, YNRD?2, and YNRDO) provide a positive voltage on the cathodes of their associated diodes (03R, 02R, and OOR, respectively) which reverse biases them and prevents conduction. Read driver YNRDI1, which has been selected, turns on and makes the cathode of diode 01R negative with respect to the anode which forward biases it. The diode conducts and allows current to flow to write driver YNRD1. A half-select current now flows through this line that links 128 cores per bit mat (2048 total for 16 mats). Figure 3-5 is a simplified schematic of two pairs of switches and drivers in the MF11-U/UP interconnected with the core stack and current generator. Read/write switches YSO7 and read/write drivers YD7 are used as examples. These switches and drivers are chosen for convenience. For a read or write operation, there are 128 switch/driver combinations on the Y axis and 128 on the X axis. For a write operation, decoder E19 selects positive write driver E25 and decoder E28 selects negative write switch E14. Both E25 and E14 are turned on when they are selected and write timing occurs. E25 conducts, which allows current from the Y write current generator to flow through nH?25, the associated matrix diode, and the cores on the selected line. After passing through the cores, the current flows 3-6 J§. §)MyovisAI—LIS¥OYadmndiygx¢-¢[BoIdA],&Ul/PBISYNI9N1ILLIMSOUOMIOVLMSSPURSISAJLAII(L]ISOd1NJYI1I mONIWIL w_,fi,_ ONIWILfl)qYzNmDw_;m oL 4300234 (LYW/821) 1 a 3-7 IHM | €+a & b 0 4d3AAlHdLaOd Ol MOVLS PR o ~ 613 a_L=43TAMdAI_NOAGZ+A¥OFLLVIHMINIIONIHND +AOZAMOaLvY3NyINIINO3¥LaNHOvDLS3IAyMS — 43HLO OL8v¥032080334408923O—e—SINIT/A\IAIVOAN39HVHD gela ¢geld LOSA ILNV LOOHSY3A0 1indd1d through D43 and E14 to ground. For a read operation, decoder E28 selects positive read switch E17 and decoder E19 selects negative write driver E22. Both E17 and E22 are turned on by read timing. E17 conducts, which allows current from the Y read current generator to flow through E17, D47, and the cores in the opposite direction. After passing through the cores, the current flows through the associated matrix diode E22 to ground. Read current flow is shown as a broken line; a solid line shows write current flow. 3.5.1 Word Address Decoding and Selection Sequence This paragraph takes a specific word address through the decoding and X and Y line selection sequence. The word address is 017772 and it is assumed that a specific memory bank has been selected. The binary equivalent of the address is shown below. A read operation is to be performed. |13 oo 0O0O]O0]O 0 1 |12 | 11 |10 |09 |08 |07 |06 |05 |04|03 |02 |01 |00 BIT POSITION 1 1 1 1 1 1 1 1 0o 1 0 BINARY 1 7 7 1 7 2 OCTAL s {16 | 15|14 I-n73 Bits A(14:01) are used to decode the word address. Bits A(1.4:01) are sent from the Unibus receivers to inputs to the associated word latches. Table 3-1 shows the state of bits A(14:01) and the decoding signals generated by the word address latches. “Table 3-1 Example of Word Address Decoding Signals Address Bit Unibus Receiver Output Receiver Input o Latch State Latch A0l L H set AO1H=H AO2 H L reset AO2H=L AO3 L H set AO3H=H AO4 L H set AO4H=H A0S A06 AQ7 L L L H H H set set set AOSH=H AO06H=H AO7H=H AO8 L H set AO8H=H AQ9 L H - set AQO9H=H A10 L H - set A10H=H All L H et A11H=H Al2 L H set A12H=H A13 H L reset A13H=L Al4 H L reset Al14H=L Output Signals - The decoders, switches, and drivers are shown in drawing G235-0-1, sheets 4 and 5. Using the decoding signals in Table 3-1 and the operating characteristics of the decoders, it is possible to determine which decoder outputs have been selected for word address 017772. 3-8 \\..._.../ 17 A<17:00> ~ ADDRESS BITS Decoder E19 — D2 is high, D1 is low, DO is high; selects output 5 (pin 6) which is read driver YNRD?S. Decoder E28 — D3 is low, D2 is high, D1 is high, DO is high; selects output 7 (pin 8) which is read switch YSO07. Decoder E32 — D2 is high, D1 is high, DO is high; selects output 7 (pin 9) which is read driver XNRDO7. Decoder E27— D3 is low, D2 is high, D1 is low, DO is high; selects output 7 (pin 8) which is read switch XS07. The last step is to follow the outputs of the drivers and switches to the stack diode matrix (drawing H217-0-1, sheet 2). For the Xline, the circuit is from driver XNRD7 to diode junction E18-7, across termination 93 to switch XS07. For the Y line, the circuit is from driver YNRDS to diode junction E7-7, across termination 79 to switch YS07. The terminations indicate the point on the stack printed circuit board where the X or Y line is soldered. Physically, the wire that is connected across the termrnatron is strung through 128 cores per bit mat (total of 2048 cores in series for 16-bit memory). 3.6 3.6.1 READ/WRITE CURRENT GENERATION AND SENSING Introduction Aside from the addressing and control logic, four functional units are involved in generating current to switch the cores and detect their state. The X and Y line read and write current generators supply the drive current (via switches and drivers); the inhibit drivers allow Os to be written during a write operation; the sense amplifiers detect 1s during a read operation; and the memory data register (MDR) temporarily stores data to be written or data that has been read from the memory. The following paragraphs discuss each functional unit and their interrelation. 3.6.2 Read/Write Operations The discussion of the read/write operations shows the interrelation of the current generator, inhibit drivers, sense amplifiers, and memory data register. Details of the operation of each functional unit are discussed in subsequent paragraphs. Several control signals are mentioned; however, detafls of their generation and timing are described in Chapter 2. For clarrty, one data bit (D07) of the selected word is discussed and the text is referenced to Figure 3-6 which is a simplified block diagram. Detailed logic for the MDR, Unibus reeelvers and drivers, sense amphfiers and inhibit drivers for all 16 data bitsis shownin drawing G114-0-1. During a read operation, half-select currents flow in the X and Y lines for the selected word in each bit mat. These currents flow opposite to the write currents; therefore, cores in the 1 state are switched to the O state and cores in the O state are unchanged. Switching the core from the 1 state to the O state induces a voltage pulse in the sense winding. This pulse is detected by sense amplifier E401 as a differential voltage on input pins 6 and 7 if it exceeds the threshold reference voltage. This pulse is amplified and when SINA SENSE STROBE 0 H is generated at pin 11, “the output of sense amplifier E401 goes high. Just prior to the strobe signal, the control logic generates SINA CLEAR MDR 0 L which clears (resets) flip-flop E404. The sense amplifier output is inverted by E403 and sent to the preset input (pin 10) of MDR flip-flop E404. A low on the preset input sets the flip-flop; its 1 output (pin 9)is a high and its O output (pin 8) is a low. The high from pin 9 of the flip-flop is sent to input pin 12 of Unibus driver E407. The other input to E407 is the buffered OUTPUT ENABLE signal. When the control logic generates SINA OUTPUT ENABLE H, the output of E407 is low (logical 1 for Unibus logic). This is the readout of bit DO7 and is sent to the requesting device via the Unibus. Timing diagrams for the sense operation are shown in Figure 3-7. 3-9 3HV1NWNILS VNIS Y3IMOd 71 vd 7 13N AHOM 34&d 3ISN3S JdINdANY lO+3 2l VNIS 4v31d 10 O3 3189VN3 H 9INJI9-¢asuUoOgIIDdfAUidOuIrNyUp]ueJO}‘ISQNIQUIU[I)9ABTIR(]J‘10)SISY LIGIHNIS ERYR-1¢ Ol VNIS 3ISN3IS 380¥1S O e8LlL-1t1 ¢Ov3 1VNndI1lSNO y71d 104XV—NAIWS 3.10 THRESHOLD VOLTAGE SENSE SENSE AMP INPUT - FROM STACK LINE \ OUTPUT E401 (6-7) SINA MDR CLEAR O -~ U L SINA SENSE STROBE H J I SENSE AMP I 0 | OUTPUT E402 OQUTPUT E404 OUTPUTS ‘ { I 1 I . SINA OUTPUT ENABLE H 0 - - E407 OUTPUT TO UNIBUS NOTE : ‘ | I | 0 2 1 l I | Refer to figure 5-3 for typical circuit schematic and refer to figure 5-4 for waveforms. 11-1192 Figure 3-7 Sense Operation Timing Diagram The read operation is destructive: all cores at the specified location are now 0. The data that was read must be restored by a write operation which immediately follows the read operation. Flip-flop E404 is still in the set state; therefore, its O output (pin 8), which is low, is sent to input pin 5 of NAND gate E405. The control logic generates the inhibit driver control signal SINA INH TIME L which is buffered by E403 and sent to another input of gate - E405. The gate is not turned on (pin 5 is low) and the inhibit driver is not turned on. With no inhibit current in the inhibit line to oppose the half-select Y line current, a 1 is written back into the appropriate cores. In this example, if bit DO7 is a 0 in core, it does not switch during the read operation and the output of sense amplifier E401 does not go high. Flip-flop E404 remains cleared (reset): its 1 output (pin 9) is low and its O output (pin 8) is high. When the control logic generates SINA OUTPUT ENABLE L, the output of Unibus driver E407 is high (logical O for Unibus logic). The 0 output of flip-flop E404, which is high, is sent to NAND gate E405. During - the subsequent write operation, SINA INH TIME L is generated which produces a low output signal at E405 pin 6. This activates the inhibit driver which produces a current that opposes the Y line current and prevents a 1 from being written into this bit of the selected word. | The read/write operation which has been discussed is a read/restore operation (DATI). The requesting device wants to read a word from memory and, as an internal requirement, the memory must restore the word by writing it back in core. In this case, the MDR flip-flops are preset by the sense amplifier outputs when 1s are read from the core. The flip-flop outputs are used in the subsequent write (restore) operation to control the inhibit drivers. If the requesting device wants to write a word into memory (DATO), it must load the data into the MDR flip-flops. The 3-11 device asserts the data on the Unibus from which it is picked off via Unibus receivers. In this example, bit D07 is sent to pin 9 of Unibus receiver E402. The bit is inverted by the receiver and sent to the D input (pin 12) of flip-flop E404. At the start of the DATO cycle, the control logic generates SINA CLK MDR 0 H which clocks the flip-flop. If the D input is high, E404 is set and its O output is low. Control gate E405 is not asserted by SINA INH TIME L and the inhibit driver is not turned on. A 1 is written into the selected core. If the D input is low, E404 is reset and its O output is high. Control gate E405 is asserted by SINA INH TIME L and the inhibit driver is turned on. A 0 is written into the selected core. Because SINA CLEAR O L and SINA SENSE STROBE 0 H are disabledin this mode, the read operation is used only to magnetically clear the cores. 3.6.3 X and Y Current Generators A read and write current generator is provided for both the X and Y drive lines. The current generators and associated bias current supply are shown in drawing G235-0-1, sheet 6. Optimum core switching requires current pulses of precise amplitude, duration, and shape. The current amplitude is controlled by the dc bias current supply (which is temperature compensated). Pulse shaping is achieved by resistor, diode, zener diode, anti-overshoot circuits; duration is controlled by the timing pulses from delay lines. Figure 3-8 shows the bias current supply and read X current generator. The heart of the current generators on both the G235 (X—Y current generators) and the G114 (inhibit current generators) modules are special saturating transformers. T2 is the saturating transformer for the read X current generator. T2 is normally saturated very hard by bias current in the winding demgnated with pins 3 and 12. In order for the magnetic core of T2 to start to switch its magnetic flux in the opposite direction, the ampere turns applied by the bias current needs to be exceeded by an “equal but opposite current in another winding. As long as T2 remains saturated it is a low impedance to changes in current in any of its windings; however, once T2 starts to switch magnetic flux, large voltages may be induced across its windings in response to any additional changes in net current. That is, T2 acts like an ideal current source — low impedance with less than a specified current in winding 2-13 and a high impedance to additional current changes once the specified current amplitude is reached. This specified current is primarily determined by the bias current amplitude and the turns ratio of T2. The third winding of T2 (1-14) conducts current only after the drive current pulse has ended, and restores some current to the +20 V supply during that period. Although some losses occur in T2, most of the energy absorbed by T2 durmg the current pulse is restored to the power supply at the end of the pulse. The bias current supply provides the dc bias current required for all the saturating transformers on the G235 and G114 modules (in series). LRC filter networks are provided at intervals to ensure that the bias current does not acquire ac components and to ensure that large voltages do not build up along the series path. (L1, C43, and R17 comprise such a filter network protecting Q12 and Q13 from transients. ) The resistor network, consisting of the stack thermistor, R10, R9, R11, R12, R8, R7, R13, R14, R15, and Zener diode DI, provides a temperature compensated reference voltage to pin 3 of E1. R2 feeds back the emitter voltage of Q12 to pin 2 of El. The 741 operational amplifier uses its gain to adjust its output (pin 6) so that the voltage on pin 2 is made very nearly equal to the voltage on pin 3. In this way the amphfiér circuit causes a current to flow through R4 and RS controlled precisely by the reference voltage on pin 3 of E1. By measuring the voltage on AK2 with respect to +5 'V, a very accurate measure of the bias current can be made, since most of the current through R4 and RS finds its way through the collectors of Q12 and Q13 (Q13 base current is small) and becomes the bias current. The memory protection circuits and the circuitry to detect 2. loss of bias current are described in Chapter Module pins AN2 and AUI provide a means of changing the amplitude of the bias current. Grounding AUl through a 470 KQ resistor will cause the bias current to be reduced, and grounding AN2 through a 470 K{2 resistor will increase the bias current. This capability becomes important for margining the memory. 3-12 — ———— e — e-—e e Gy N|oovis |M Mcyldoml3an As+l _ HOIHNIOMYW ! 1y| ‘| ‘| ok 11S0HnOJHLHSVIYb1HHDI3INAIOO{4 |||_I_C |_|o6y4-AGX1a,<cA1yNAo-<vlycidU.Sey_I||n_T¥Md~MOHMO2yNIOHVIW|.Lm|<<|||_1JARYobflepYOl||¢4»3H103..0|_SIHOLIMS m_._.m_EJm,.mrwtoz_oI|31630H]NdI1.pVwYaIyddsANVIAHYLQN.OILVS.N3IdWODJANd_GIv_3y—JWILHVANQJAINA|y.I-.s__.vrizg<_,_I|N3LIHH"¥ND-oL~avay 3-13 mow! TM | _‘, :_Nol¢nSav CAUTION Jumpers W5, W6, W7 are factory cut to adjust the bias current to its optimum value and they should not be changed. In Figure 3-8 the operation of the read X current generator is as follows. The output of E7 (pin 8) will go low when the current generator turns on. Current is coupled through T1 to saturate transistor Q1. At this point, current may flow through T2 windings (pins 13 and 2 and 14 and 1), through Q1, and to the read X switches. Diodes D17 and D16 limit the voltage applied to the read X switches and thus make the read X current rise time less dependent on the accuracy of the 20 V power supply. This is the only current generator in the memory with such a control. It is needed here because the core output signal is more dependent on the read X current rise time than any other. (Read Y current flows before the read X, hence the read X current does the actual core switching.) D130, D131, and R&89 form an anti-overshoot circuit which conducts current only during the rise time of the current. Its function is to “steal”” some of the read current during the rise time so that when the current overshoot occurs, the overshoot only serves to bring the current quickly up to its proper value (and not beyond it). R61 and C47 primarily serve as a dc current limit and as a rise time aid, respectively. When Q1 is turned off by E7 (coupling through T1) current will flow through D30 until the core of T2 has been completely re-saturated by the bias current. This places energy back in the power supply. 3.6.4 Inhibit Driver A detailed schematic of the inhibit driver for bit DO7 is shown in Figure 3-9; it is typical of all 16 inhibit drivers (drawing G114-0-1). | When the inhibit driver is off, none of the pulsed currents shown in the schematic are flowing; transistor Q401 is off. The output of NAND gate E405 goes low (ground) when this inhibit driver is selected. Current i; flows into the output circuit of E405 from the +5V supply via resistor R404 and the primary winding (terminals 9 and 10) of transformer T402. An equal current is induced in the base-emitter circuit of Q401 which is connected to the transformer secondary winding (terminals 8 and 7). This base current turns on Q401. Current iy, and therefore induced current i,, is determined by resistor R404 and the reflected base-emitter voltage, Vbe, of Q401. When Q401 is turned on, current flows from +20V through the saturating transformer T403, transistor Q401, fuse F401, isolation diodes, and the sense/inhibit winding to the isolation diodes D403 and D404 to ground. The value for inhibit current is primarily determined by the bias current to T403 (winding 7-8). Each leg of the sense/inhibit sees half the inhibit current; approximately 370 mA. Capacitor C407 and D405 help reduce the power dissipated in Q401 during turn-off. - The inhibit driver is turned off when the output (pin 6) of gate E405 goes from low to high. At turn-off time, the back emf caused by the stack inductive reactance tries to drive the emitter of Q401 highly negative; however, diode D407 and resistor R409 help to clamp this voltage to ground. When the output of E405 goes high (approximately +3.2 V), its output pull-up transistor (an integral part of the gate circuit) tries to drive the turn-off current iy in the opposite direction through the transformer primary winding. An equal current induced in the secondary winding removes the forward bias from the base of Q401 and turns it off. With Q401 off, all dynamic current flow ceases in the circuit. Capacitor C410 allows the gate to pump reverse current iy into the transformer primary; it also helps to decrease the turn-on time of Q401. Diode D405 prevents reverse breakdown of the base-emitter junction of Q401. 3.14 | 98.1L-11 W Q I 0 H S I Y H L Il9 GlI1NS,I3Old m.¥oAN<(I¢VS<m. 2l LIGIHN]IAYLINOHIO | Y60t 20ty LV\\Ol 38041S HO |H;L3o¢yo _10bY i co8bl. “_obha‘ o =€ | svig | b | | | | JO2b0D+d —Pp—i A4¢ 1402 p &~ - | J 3-15 I3p1a62JosIAqyu-LnrIyd3e¢(ug]Irqy 3.6.5 Sense Amplifier A detailed schematic of the sense amplifier circuit for bit DO7 is shown in Figure 3-9; it is typical of all 16 sense amplifier circuits (drawing G114-0-1). It consists of the sense amplifier, terminating capacitor for the sense/inhibit winding, and threshold voltage network. The sense amplifier input (E401 pins 6 and 7) is across the sense/inhibit winding (STKA SA7 and STKA SB7). Practically speaking, during the sense operation, the inhibit driver connection is an open circuit through the driver transistor Q401. The effect of the inhibit driver circuit, and isolation diodes D403 and D404 can be ignored during the sense operation because the diodes are reverse biased. Sense amplifier E401 is one-half of a dual IC package (type 7528). A simplified block diagram of the package is shown in Figure 3-10. The two identical circuits are marked 1 and 2. Each consists of a preamplifier and sense amplifier. The output of the preamplifier is available as a test point to observe the amplified core signal and to facilitate accurate strobe timing. Both circuits share a reference voltage (or threshold voltage) amplifier (pins 4 and 5). In this application, pin 4 is grounded and a positive threshold voltage of approximately 17 mV is supplied to pin 5. This voltage is obtained from the +5 V supply through resistor voltage d1v1ders Operation of the sense amplifieris ~ Veet VeeTM SA1 1 INPUT SB1 DIFF-INPUT THRESHOLD VOLTAGE |tV _[re] 1 CIRCUIT fi [5] [ 15] TEST POINT 1 ____:)——~13 OUTPUT 1 14 STROBE ) [ SA2 INPUT 2 —f T H | 3—12 OUTPUT 2 SB2 10] TEST POINT 2 2 CIRCUIT B 1 CeXT 11-1103 Figure 3-10 Type 7528 Dual Sense Amplifiers with Preamplifier Test Points 3.6.6 Memory Data Register The memory data register (MDR) is a 16-bit flip-flop register that is used to store a word after it is read out of the memory, or to store a word from the Unibus prior to its being written into the memory. It is composed of eight 74H74 dual high-speed D-type flip-flops. At the start of a memory read operation, the MDR is cleared directly via the CLEAR input (pin 1 or pin 13) of each flip-flop; the clear signal is SINA CLEAR 0 L for bits DO0-DO07 and SINA CLEAR 1 L for bits DO8—D15. The operation of the MDR during a read/restore operation (DATI) and a write operation (DATO)is discussedin Paragraph 3.6.2. 3.7 STACK CHARGE CIRCUIT The stack charge circuit assists the stack capacitance in recovering and shortens the rise time of the stack current. It also reduces unwanted currents in the seven unselected lines associated with the selected driver. It is located on the H217 module. ~— discussedin Paragraph 3.6.2. Figure 3-11 shows the stack charge circuit. Its output is taken from the emitter of transistor Q1 and goes to the junction of each X and Y read/write switch pair via a resistor. This common interconnection is labeled V. It is desired that Vg~ 0V (ground) during a read operation; and Vi ~ +20 V during a write operation. The effective stack capacitance associated with each line is shown as Cg;, +20V +3V co Q1 D62 .ilf - R33 READ SWITCH (G235) & o {_ Y063 ' MATD STACK CHG H E29 R34 . +—AA— C STACK WRITE T Q2 8 Vo SWITCH L (G235) %j Q3 R35 BTO ALL OTHER READ/WRITE Refer to logic schematic STKA . I[l———:D NOTE: SWITCH PAIR JUNGCTIONS IN X AND Y AXES » ‘ . i1-1785 Figure 3-11 Stack Charge Circuit During a read operation MATD STACK CHG H is low, making the output of E29 (pin 8) high, thus saturating Q2 and turning on Q3. The output voltage, V5, of the circuit is also held low by the parallel combination of L1 and D63 (connecting to the collector of Q2). In the low state, Vy=Vpp (Q3) + Ve SAT (Q2). A current thus flows from +5 V, through D62 and R33, through L1, and through Q2 and Q3 to ground. Q1 is off since its base-emitter junction is not forward biased. During a write operation the MATD STACK CHG H signal goes high, making the output of E29 (pin 8) go low, thus turning off Q2 and Q3. Current that was flowing through L1 is forced to continue to flow by the inductance of L1 and now must flow into the base of Q1. Hence with Q1 turned on (saturated) and Q2 and Q3 off, the output VO is equal to 20V less Vg gAT (Q1). Current spiking from Q1 through Q2 and Q3 on the transitions is prevented by D63. When Q2 and Q3 turn on again, Q1 must be fully off before current can flow through D63. This is due to the fact that if D63 is forward biased, the base-emitter junction of Q1 is reverse biased. 3-17 ' R B | CHAPTER 4 MF11—UP CORE MEMORY WITH PARITY 4.1 INTRODUCTION This chapter contains a description of the theory and operation of the MF11-UP parity memory and the M7259 Parity Controller. Inasmuch as the MF11-UP is similarin operation to the MF11-U Memory, which is describedin the main body of this manual, only those areas of operation which are unique to the MF11-UP are coveredin this chapter. NOTE An M7259 Parity Controller Module must be Etch Rev D and CS Rev E or higher to be useable in the MF11-UP. 4.2 DESCRIPTION The parity memory consists of an M8293 16K Unibus Timing Module, a G235 Driver Module, a G114 Sense Inhibit Module, and an 18-bit H217-C Stack Module. In addition, an M7259 Parity Controller Module is required. The M7259, Parity Controller performs all parity generating and checking functions and communicates with memory via an internal bus shown in Figure 4-1. The signals on the internal bus are shown in Figure 4-2 and are described in Paragraph 4.6.2. The parity controller processes 16K or 32K of memory (two MF11-UPs). Bits 16 and 19 are the parity bits for the low byte and high byte, respectively. These bits are the property of the parity controller and are not accessible to the PA and PB lines on the Unibus. Bits 17 and 18 are not usedin the MF11-U or the MF11-UP. The stack may or may not contain the cores and/or electronics for these bits even though they are shown on the circuit schematic. | In a DATO or DATOB bus cycle, both the low order and high order bytes are coded for odd panty, thus for every byte containing an even number of 1s, a 1 is written into the corresponding parity bit location. A } ‘ N\ M7259 PARITY CONTROLLER ‘ S | +5V N P T 1 1 R MF 11-UP MEMORY U N (16K) N | [ E A L Y B U S S MF11-UP MEMORY (16K) +5V - Figure 4-1 +20V .' -5V Parity Controller Internal Bus 4-1 | , | 11-1781 ' F11-UP PARITY MEMORY 16K BY CORE |' _ADDRESS, - CONTROL D P 1 1 Ul N ; | . P 18=-BIT MEMORY | DATA _ BUS MSYN L v | ! :U SSYN INT| BUS L A BUS D19L| | PCL BUS D16 L | DATIP CLR PAUSE L I | - I P e BUS SSYN L | _ . BUsPAL >IBNTERNAL us I M7259 l CONTROLLER PARITY I I __BUS PB L l | I J I ° | | N 11-1794 Figure 4-2 ~ Parity Controller Block Diagram In a DATI or DATIP bus cycle, each byte plus its associated parity bit is checked for an odd number of 1s. If the sum is even, an error condition exists. When a parity error is detected during a DATIP, the erroneous data causing the parity error is saved and written back into core. 4.3 SPECIFICATIONS The spec1ficat10ns of the M7259 Parity Controller are given in Table 4-1. Table 4-2 shows the cycle and access times - for the MF11-UP Memory option. Table 4-1 M7259 Parity Controller Specifications Voltagé Requirementsi o Currefit Requirements: | | Power Dissipation: | +5 V £ 5% with less than 0.05 V p-p ripple | 1.2 A Maximum | 6 W Maximum | EnVironment: a Ambient.'Temper‘ature: Relative Humidity: | Unibus Unit Load: 0° C to 50° C (32° F to 122° F) 0*90% (noh-condensing) B 4.2 ' Table 4-2 MF11 -UP Maximum Cycle and Access Tlmes Access Time Cycle Time pATI 595 s 1000 ns DATIP 595 ns 585 ns Bus Mode DATO-DATOB 150 ns DATO-DATOB 150 ns (Pause L) 11000 ns 600 ns | N s (Pause H) | 4.4 FUNCTIONAL DESCRIPTION The MF11-UP parity memory is read/write, random access, 001n01dent current, magnetic core, parity memory with a maximum cycle time of 1000 ns and an access time of 585 ns maximum. It is organized in a 3D, 3-wire, planar configuration. Word length is 18 bits, two of Wthh are the parity bits, and the memory capacity is 16,384 (16K) | | words. The operation of the parity memory is identical to that of the MF11-U Memory except for the parity generation and checking functions. In order to implement this option, an 18-bit stack module (H217-C) is used (bits 19 and 16 being the parity bits). In addition, a parity controller module is required. The controller is a dual height module (M7259) which plugs into the memory system backplane. It contains a control and status register (CSR) and all the logic used to generate and check parity. A schematic diagram of the parity controller is shown on engineering ‘drawing D-CS-M7259. Odd parity is used; if the number of 1s in a given byte is even, then a 1 will be written into the respective parity bit location. The use of odd parlty allows detectlon of a memory failure of all Os, Wthh is a - more probable failure mode than all ls Error action can be disabled or _enabled under program control. If parity error action is enabled by setting bit O of the CSR, a parity error will cause assertion of the parity error code on the Unibus. Processors equipped to detect | Unibus memory parity errors will trap through vector 114 upon receipt of the parity error code. The error code is BUS PB L asserted and BUS PA L not asserted. (See Paragraph 4.5 in the programming section of this chapter.) On parity generation (DATO or DATOB) both the low order (D0OO to D07) and the high order (D08 to D15) bytes are coded. The Unibus data is applied through buffers to the inputs of E4 and E13 on the M7259. The outputs of these ICs will be high if their respective inputs contain an odd number of 1s, and thus cause the D16 or D19 internal parity bits to be set. The D16 bitis the parity bit for the low order byte and the D19 bitis the parity bit for the high order byte. The BUS C1 L signal to the M7259 Parlty Controller indicates whether parity is to be generated or checked 4.4.1 DATI or DATIP Cycle ~ For parlty checkmg (DATI or DATIP), the same two ICs which were used for parity generation are used; in this case, however, a low input indicates a parity error. During the memory read cycle, the signal SSYN INT BUS L is sent to the par1ty controller to indicate that memory data is present on the Unibus. This signal initiates a t1m1ng sequence 4.3 (PCL SSYN DLY L) to allow for worst case propagation delays of data through the memory data drivers, parity controller data receivers, and the parity tree and checking logic. At the end of this sequence, one of two data input pulses to the parity error flip-flop occur; PC2 PARITY ERROR H or ~PC2 PARITY ERROR H. If each byte and its respective parity bit contain an odd number of 1s, then ~PC2 PARITY ERROR H is generated, allowing BUS SSYN to be sent to the bus master to indicate that data is available and valid. If, however, the sum of 1s of either byte is even, then the signal PC2 PARITY- ERROR H is generated, causing CSR 15 to set (parity error indication). If parity error action is enabled (CSRO = 1), then BUS SSYN and BUS PB signals will be enabled. The BUS PB signal indicates to the bus master that a parity error has occurred during the current DATI or DATIP cycle. Since the restore portion of the memory cycle is skipped during a DATIP operation, provision must be made to save bad data in core in the event of a parity error during DATIP. The operation of the parity controller checking and timing sequence is the same as during a DATI operation, except that if PC2 PARITY ER DLY (0) H is generated, it will cause an 500 ns pulse, DATIP CLR PAUSE (1) L, to be generated. This signal causes the memory to restore the bad data, and also eliminates the requirement for the write cycle which would otherwise have to follow. 4.4.2 DATO Cycle During a normal DATO cycle, that is, a DATO which does not follow a DATIP, parity is being generated before the read portion of the memory cycle. The Unibus data along with the proper parity bits are transferred into a data register on the G114 Sense Inhibit Module. SSYN is then returned to the bus master via the parity controller to indicate that data has been strobed from the bus. Data is transferred from the data register to core during the write cycle. If the DATO follows a DATIP, the sequence is altered. During the DATIP, the memory location will have been cleared and a PAUSE flag set. When the DATO occurs, the read cycle will be skipped, and the write cycle begun immediately. The data and parity bits are transferred from their respective buses at the beginning of the write cycle, | at which time SSYN is generated. 4.4.3 | | DATOB Cycle The DATOB cycle is similar to the DATO, except that during the DATOB, datais Written in byte form rather than as a full word. The non-selected byte is simply restored along with the new data in the selected byte plus the parity '4.4.4 Jumper Terminéls The M7259 parity control module contains seven sets of jumper terminals. The physical location of these terminals is shown in Figure 5-14 and the functions of the jumper terminals are listed in Table 4-3. Table 4-3 M7259 Jumper Terminals Jumper Terminals | ~+ - Wi-w4 ~ Function | Discrete CSR address W5 ~ Modifies the t1m1ng _cqns_tanft for the SSYN W6 When in, data is restored when a parity error delay one shot multivibrator (always out). is detected on a DATIP (always in). W7 | | ~ When out, SSYN is inhibited and the bus hangs when in the Maintenance Mode (always in). 44 | | 4.5 PROGRAMMING The Control and Status Register (CSR) is located on the M7259 Parity Controller. There is one CSR per 32K of memory. Transfer of a 16-bit control word from the processor to the CSR establishes the operating conditions of the MM11-UP. The data format of the CSR is shown below: CSR BITS Error 15 14 |13 |12 4] 11 | 10 ’ " L 8 7 6 1‘ Error Address 5 4 3 2 1 0 ‘ R 4 | Write even parity (wrong parity) Error action enable NOTES: 1. - All bits are read/write. 2. All bits except the error address bits are cleared by INIT. Bit 15 Description Name ERROR Set when a parity error occurs regardless of whether any other response is enabled. Setting this bit will not cause a parity error trap. This bit is a flag and is not associated with the trap routine. 11:5 ' ERROR ADDRESS Contains the highest order address bits of the most recent location causing a parity error. 2 WRITE EVEN PARITY Causes the controller to generate incorrect parity on write (wrong parity) cycles (DATO or DATOB), forcing a parity error on the next DATI or DATIP cycle. This bit is intended for use as a diagnostic aid. 0 ERROR ACTION ENABLE | Enables error indication to the bus master when set. The address of the CSR is hardwired in the range 772100 to 772136. Normally, the address 772100 is factory wired for the first 32K increment, 772110 for the second 32K, etc. 4.6 BUS LOADING AnMF 11-UP represents two bus loads; one for the MF11-UP 16K Parity‘ Memory Module set and one for the M7259 Parity Controller. The M7259 Parity Controller handles the parity for 32K of memory. A second MM11-UP 16K module set adds one bus load. Therefore, the MF11-UP, expanded to 32K, would represent three bus loads. 4-5 INTERNAL BUS The internal bus (Figures 4-1 and 4-2)is the communication path between the M7259 Parity Controller and the core memory. It comprises the following signals: Name Function SSYN INT BUS L Signals the parity controller when datais avallable on the Unibus to begm parity checking sequence. PBINT BUS L (D19) A bidirectional path which carries the generated parity bit to memory on DATO cycles and from memory to the controller on DATI cycles. This is the parity bit for the high order byte (D15:D08). PA INT BUS L (D16) | Same as PB INT BUS L except that it is the parity bit for the low order byte (D07:D00). DATIP CLR PAUSE (1) L Clears the PAUSE flip-flop in the M8293 16K Unibus Timing Module if a parity error occurs on a DATIP cycle, which initiates the write-restore cycle. DATIP CLR PAUSE L Not used with the MF11-UP. 4.8 INTERLEAVING RULES FOR PARITY MEMORY a. Both of the memories to be interleaved must be parity memories. b. The two parity memories to be interleaved must cover contiguous address ranges. C. 4.9 The two parity memories to be interleaved must be in the same backplane. CSR ADDRESS SELECTION The address of the CSR is hardwired in the range of 772100 to 772136. Jumpers W1 through W4 (refer to Figure 5-14 for jumper locations) determine the discrete address. < ' 17 Hardwired 16 15 14 11111111 \ 7 o 13 Always 0 11 10 9 8 7 6 5 4 3 2 1 141110 1 0 0 0 1 0 X1 X} X }|X1]10 7 12 Always 0 | N ) . T L 0 ’ 001036 X = Bit values selected by Jumpers W4 — W1 CSR ADDRESS Table 4-4 shows the CSR addresses for all possible memory starting addresses and their jumper configurations. For example, if the lowest address memory responds to is 28K, the jumpers are cut for address 722110. If the lowest address memory responds to is 32K, the jumpers are also cut for address 772110. This is because the CSR addresses are assigned on a basis of 8K of memory. Thus, there are 16 unique addresses in the table. 46 ~— 47 Table 4-4 . CSR Address Jumper Selection for M7259 Parity Controller e Module, Etch Rev D, CS Rev E | CSR Jumpers w4 W3 W2 Wl Bus Address Line | A04 AO3 A02 A01 Lower Memory Boundary CSR Address 0 772100 X X X X 4K 772102 X X X 0 8K 772102 X X X 0 12K 772104 X X 0 X 16K 772104 X X 0 X 20K 772106 X X 0 772110 772112 0 0 X X X o) 772112 X X X el X 0 772114 X 0 N 0 o X X X X 24K 28K 32K 36K 40K 44K 48K 52K 56K 60K 64K 68K 72K 76K 772106 772110 X X 772114 772116 772116 X X X 772122 772122 0) o) 772120 772120 X o) o) o o) X X 0) X o) 0 X X o) o) o) X 0 0 X X o) 0 X X 80K 84K 88K 92K 96K 100K 104K 108K 112K 116K 772124 772126 772126 772130 772130 772132 772132 772134 772134 772136 772124 0 o) o) 0) 0) o) 0) 0) 0) o) 0 X X X 0 o) o) 0) o) o) o) X 0 X 120K 772136 0 0 0 o) O= Jumper RemovedX = Jumper Installed 4.7 o) 0) o) X X X X 0 o) 0 X o) 0 X X 0 0 X X 0 Example: Assume a starting address of 52K (3200008) is desned ‘The example illustrates how the CSR parity addressis determined. Bit 17 16 15 14 13 12 11 10 9 7 0 \ CSR Bit 8 7 — < 1 1 | Bit (Bits 00 and 05 always 0s) 0 1 05 04 O% | N | \ —~— 3 — 2 - 1 o0 - 0 0 Result — 4 1 , Add bit 01 5 0 | Add bit 13 6 1 S B 02 L 1 1 0 01 00 ~ J 6 NOTE When two 16K memories from dlfferent backplanes are interleaved, bit AQ1is set for the minimum addressin one 16K memory and is not set for the minimum address in the other 16K memory. - Address 16 is parity address 772116, since the upper four octal digits are hardwired as 7721XX8 (Table 4-4). Consequently, for a 52K starting address, the corresponding CSR parlty addressis 772116 andjumpers W4, W3, and W2 are out (Table 4-4 — W1 is left intact). | When using the algorithm to determine the CSR addresses, one point should be kept in mind. It is assumed that the addresses the memory responds to are contiguous except for interleaving. Table 4-5 shows the CSR address for each 4K increment of memory. For example, if the lowest address memory responds to is 32K, the parity register address is cut for 772110. If the lowest address memory responds to is 36K the parity register address is also cut for 772110. Consequently, the CSR addresses are assigned on a basis of 8K of memory. Thus, there are 16 unique CSR addresses as shown. The CSR addresses in the table assume the memories are not interleaved or are interleaved within the same backplane. With interleaved memories, the algorithm should be employed to determine the CSR address. | 4.8 Table 4-5 CSR Addressing Memory Start Corresponding Parity Register Address 0 o 772100 4K 772102 8K 772102 12K 772104 16K 772104 20K 772106 24K 772106 28K 772110 32K 772110 36K 772112 40K 772112 44K 772114 48K 52K 772114 | 772116 56K - 60K 772116 772120 64K 772120 68K 772122 72K 772122 76K 772124 80K 84K | 772124 | 772126 88K 772126 92K 772130 96K 772130 100K 772132 104K 772132 108K 772134 112K 772134 116K 772136 120K 772136 4-9 5 CHAPTER ‘ INSTALLATION AND MAINTENANCE 5.1 INTRODUCTION This chapter discusses the preventive and corrective maintenance procedures that apply to the MF11-U/UP Memory. | A major point in the maintenance philosophy of this manual is that the user understand the normal operation of the memory as described in the previous chapters. This knowledge, plus the maintenance information included in this chapter, will aid the user in isolating and correcting malfunctions. | | | 5.2 INSTALLATION Paragraph 5.2.1 describes the mounting box and power requirements for installing the MF11-U/UP in various equipments. Paragraph 5.2.2 describes the selection of jumpers for the desingd memory addressing and the jumper selection for interleaved and non-interleaved operation. The jumpers for the strobe margin and bias current are also described. Paragraph 5.2.3 is a step-by-step procedure for installing the MF11-U/UP as an add-on to an existing system. 5.2.1 Mounting Box and Power System The MF11-U/UP must be installed in a mounting box capable of holding a PDP-11 double System unit with the facility of 420V, -5V, and +5 V power distribution and supplies. The power distribution systems and cabinets for the PDP-11/40, PDP-11/35, PDP-11 /45, PDP-11/50, and the H960-D or -E cabinet with expander box have been revised. Figure 5-1 illustrates how the MF11-U/UP connects with the new revised power distribution system. Figure 5-2 illustrates how the MF11-U/UP connects with the earlier power distribution system. | The MF11-U/UP cannot be used in the CPU cabinet of the earlier version of the PDP-11 /45/50 and when the MF11-U/UP is used in the earlier version of either the PDP-11/40/35 or the H960-D/E, an FM11-U field modification kit must be used. When the MF11-U/UP is used in either the earlier or the new system, an H754 regulator must also be used. Each regulator can handle two MF11-U/UP backplanes. Table 5-1 lists each type of equipment and the machine serial numbers that use the new and the earlier power distribution systems. The H754 regulator is included as part of the FM11-U field modification kit, therefore it is not called out in the table when the kit is required. 5-1 5-2 v e > y06G0IPS 3LNgI¥1sIa 3AX1¥1335I7hM1oOndg*0JO0H1L%|IN7O¥D ‘(HAAOOGZI$+-S))LG-HbALGHHO4(dN/N-114W OL G3HOLIMS | £o 9966004 ¥43IMOJ S INYVH €lloooooll c2v0°aN¢no01 NiOdilgAS——LN||M 3WNQoNMIo09OYIo-—oSA0AOoGZ|Y0++¢''g0}€OoAXANgNl99°°}16L—M188— b N O I L d O ¥ 3 I M O d S H O L O 3 I N O D Y3IMOdJH1SI@NOILNE'| -S9 ‘'X98SAA1NN9D8A—189.‘ — AAGGL--‘Eb€I}NNXY1E9d——N/OILdW|SbtiaLdH P9GlqLdaH -GGbiLdH bLGi33 LdH 2SASJaLNIVNdAMd NIX010NH8—|2AM91—9AG—Ia+N'9Z‘G0l Mol01ANYObN9L10XX78 101s 10X1S 10X7s s4uazso 912-1t . <A-Ll30zax_SfldY_o\pvz_o/_m.i\3_%‘ 10-0~GE£56002 . NOILdOS3pNsY”HQ;_V~A dN/N-114W > 5-3 H33dsi7fLI1Vd'A8aIN1T3SdNsPNO0nOdSVL3TLENNHHDOIOOM3HdLHSNL/L1V'0NSa-IILL3HAISLNT4NJHWHdIND X084 S INHVH 69596004 oIndigZ-SA[FegN-1TAN1omoduonqusiqWo)SAS 3 S JIO0N € 1vIN93y40 O Q3HOLIMS 1371n0 ¥3M0d TOHLNOD AShu 310N ‘€ ‘S107S '$107S 5NiNTHd3ZGINNSASSdanNBBV/d''NX9E-3NALSSL'411XN000N8I NDINT0dvaB8NS8NS/nLssdnNBNB/dl6NSN6NSI-oL‘'aXdnI0sN8NI 310N :Z ‘B 1N0I1H8MIOSNPI/AHO0WLIY JaANWQTjHONO3aYLVIYAL4SOvAvS)HWySNIH3(LIWASI—d1ONSd3dOYWWLID4NONHPY1S'LA9d-SJNlNHJdLVII3H-O4NLMI9dlHMVH 1JOG'H2VL0-L—1&SdSA33OAHOl4ILSMLVJIA/1HANHLSVO3NJLdAHL3J3IIAH8LHILNMAI0Yd ASaaN3N3i9VAdOn89W74G13d0NYVOdWL08ON1YIAv4NSIVNSIlDdd3LY 310N ‘L 1ON B9G60L|)Y3do—>d1/N-1JWN 6v9495TYARl NOISHIANOD S INYVH 6NId 4G.800L 3Imod S 3INYVH g+ 90-¢€12 a3asn H 2t dnN/N-H4NW (SANVIdXOVE A Table 5-1 Machine Serial Numbers for New and Earlier Power Distribution Systems Equipment Early System New System PDP-11/40/35 0— 5999 FM11-U required 6000 and up H754 required PDP-11/45/50 0 — 1999 MF11-U/UP can’t 2000 and up H754 required be used ‘H960-D/E 0 — 6999 FM11-U required 7000 and up H754 required The FM11-U includes a 7009569 conversion harness that must be used between the H754 +20, -5 Vdc regulator and the backplane, and a 7009568 harness which connects the backplane to the Power Distribution Panel (refer to Figure 5-2). One 7009569 harness can power two MF11-U/UP backplanes. If only one is used, the jumpers between backplanes should be cut. One 7009568 harness is required per backplane. - The FM11-U field modification kit permits installation of up to two MF11-U/UP backplanes of 16K memory. It - consists of: 1 — H754 regulator 1 — 7009569 regulator harness 2 — 7009568 9-pin conversion harness. Refer to the field modification kit print set for installation procedures (DD-FM11-U). 5.2.2 Jumper Configuration The M8293 16K Unibus Timing Module and the G235 Driver Module contain jumper wires. Table 2-4 and Table 2-5 show the jumpers for selecting the device address and for selecting interleaved or non-interleaved operation. The address select jumpers are designated W3 through W7 and the interleaved jumpers are designated W1, W2, W8, W9, and W10 (Paragraph 2.4.3). Both sets of jumpers are located on the M8293 16K Unibus Timing Module. 54 A second set of jumpers designated W1 through W7 is located on the G235 Driver Module. Jumpers W1 through W4 (sheet DRVA) control the bias current. The cutting of jumpers on the G235 Driver Module is a factory adjustment and should not be changed in the field. The strobe and bias current are set up at the factory with sophisticated test equipment. The jumpers influence the parameters in a binary-weighted fashion. For the strobe margin, W2 has the least effect, W3 approximately twice the effect of W2, W4 twice the effect of W3, and W1 twice the effect of W4. For the bias current, W6 has the least effect, W7 has twice the effect of W6, and W5 has twice the effect of W7. 5.2.3 Installation Procedure Unpack the MF11-U/UP and remove all packing material. Locate the starting memory address by cutting jumpers W3 through W7 on the M8293 16K Unibus Timing Module (Table 2-4 and 2-5). If interleaved operation is desired, change jumper wires W1, W2, W8, W9, and W10 as described in Paragraph 2.4.3. CAUTION Do not tamper with the jumper wires on the G235 Driver Module. These jumpers are preset at the factory and any attempt to change them will result in reduced memory margins and reliability. A backplane jumper is required from B1U1 to B2U1 for non-parity memory. This jumper should not be present for parity memory. For the MF11-UP, ensure that jumpers W6 and W7 are installed on the M7259 Controller Module. Jumpers W1, W2, W3, and W4 should be installed in accordance with Table 4-4. Ensure that the H754 Regulator is installed in the H742 Power Supply, located in the 11/40 or 11/45 processor or expander cabinet. This regulator is necessary for proper operation of the MF11 -U/UP. Additional information can be found in the PDP-11/40 Sysz‘em Manual, and the PDP-11/45 and PDP-11/50 System Maintenance Manual. Ensure that the option power harness is properly connected between the power distribution panel and the backplane. Install backplane assembly in processor mounting box or expander mounting box with four mounting SCTEWS. Check backplane assembly for loose or damaged pins. 10. Perform a continuity check between the power supply outputs and ground to ensure that no output voltages are short-circuited. 5-5 11. Install modules in accordance with Module Utilization Chart shown in Figure 1-1. Ensure that the modules are firmly seated in the backplane assembly. NOTE If only 16K of memory is to be installed, the modules may be placed in the left-hand half or the right-hand half of the backplane assembly. However, the modules should not be interspersed on both halves of the backplane, except for the M7259 Parity Controller, which is located in a fixed position in the backplane. This module should also be at revision E or later. 12. Connect the Unibus cable to the memory. If this is the last device on the bus, the Unibus should be terminated by inserting an M930 Unibus Terminator Module in the BUS OUT slot. If this is not the last device on the bus, the Unibus should be continued by installing an M920 Unibus Jumper Module or the BC11-A Unibus Cable to the BUS OUT slot. NOTE If the next device is in the same cabinet, the M920 Unibus Jumper Module can be used. 13. 14. Perform steps 1 through 9 of Paragraph 5.4.1, Voltage Adjustmént Procedure. In systems with parity, check and adjust the delay of the PCL SSYN DLY L signal as described in Paragraph 5.4.2. 15. Load and run all applicable diagnostic programs listed in this chapter. Verify that the program printout agrees with the total memory in the system. NOTE The pins listed in steps 16 through 20 are located on the G235 Driver Module of the memory under test (either slot 5 or 6 on the backplane). The two resistors (470 K2 and 3.9 KQ) called out are included in the plastic components box of the MM11 -U/UP Maintenance Repair Kit. 16. Halt the machine and connect a 470 K2 resistor between pin AUl (G2350-0-1, sheet DRVA) and ground. This resistor allows high memory drive current. Load and run the 0—124K Memory Exerciser Diagnostic (MAINDEC-I 1-DZQMB) using pattern 1. Make two passes. 17. Halt the machine; disconnect the 470 K2 resistor from pin AU1, and connect it between pin AN2 and ground. This resistor allows low memory drive current. Run two passes of the DZQMB Diagnostic. 18. Halt the machine; disconnect the resistor from pin AN2, and connect a 3.9 KQ2 resistor between pin AV1 and ground. This resistor causes SENSE STROBE to occur early. Make two passes with the DZQMB Diagnostic. 19. Halt the machine, disconnect the 3.9 K€2 resistor from ground and connect it between pin AV1 and +5 V. This causes SENSE STROBE to occur late. Make two passes with the DZQMB Diagnostic. 20. Halt the machine; disconnect the resistor and rerun the DZQMB Diagnostic to reverify normal operation. 5-6 5.3 PREVENTIVE MAINTENANCE Preventive maintenance consists of specific tasks performed at intervals to detect conditions that could lead to subsequent performance deterioration or malfunction. The following tasks are considered preventive mamtenance @ e a0 o “items and are recommended to be performed every six months. Visual inspection Voltage measurements Sense strobe delay check Drive current check PCL SSYN DLY check (for parity memories) Strobe and drive current margins MAINDEC testing The two pieces of test equipment recommended for checking and troubleshooting the memory are the Tektronix 453 Dual Trace Oscilloscope or equivalent, and the Weston Schlumberger Model 4443 Digital Voltmeter or equivalent with 0.5 percent accuracy. CAUTION Make sure all power is off before 1nstallmg or removmg modules. 5.3.1 | Visual Inspection Visually inspect the modules and backplane for broken wires, connectors, or other obvious defects NOTE | All tests and adjustments must be performed in an ambient temperature range of 20° to 30° C (68° to 86° F.) 5.3.2 Voltage Measurements Turn on the primary power and measure the +20V, +5V, and -5V at the opt1on backplane All Voltages must be within +5 percent tolerance. 5.3.3 Sense Strobe Delay Check To check sense strobe delay, connect channel A of the scope to pin FS1 and channel B to pin CN2 of the G235 Driver Module. The correct delay is 160 ns +20 percent after the X read driver (FS1) turns on. Measure the delay from the 5V point on the falling edge of the waveform at FSI to the 1. 5V point on the falling edge of the - in Figure 5-3. waveform at CN2 as shown \ f CHANNEL A FS1 CHANNEL B CN2 . TT L ~160nS | A ] N BV J L . L— Figure 5-3 1.y I Sense Strobe Delay Waveform 5-7 2oV — 11-2442 5.3.4 Drive Current Checks Connect a digital voltmeter (Weston Schlumberger Model 4443 or equivalent) between pin AK2 and +5 V on the G235 Driver Module associated with the 16K memory being tested. The drive current is factory-set to provide appropriate drive margins and results in a voltage measurement of 365 mV %15 percent below the +5V at 25° C (78° F). 5.3.5 PCL SSYN DLY Check (for parity memories only) Perform steps1 through 3 of the adjustment procedure in Paragraph 5.4.3. 5.3.6 Strobe and Drive Current Margins Perform steps 15 through 20 of the InStallation Procedure, Paragraph 5.2.3. 5.3.7 MAINDEC Testing Load and run for a minimum of two pasSes all the applicable diagnostic programs listed in Paragraph 5.5. No errors are permitted. 5.4 | CORRECTIVE MAINTENANCE This paragraph describes various adjustment procedures for specific corrective maintenance. It also includes three aids for performing corrective maintenance: a troubleshooting chart, waveforms for the sense inhibit circuits, and waveforms for the drive circuits. 5.4.1 Voltage Adjustment Procedure 1. Power down the equipment. 2. Disconnect the load from the H754 power supply. 3. Power up the equipment. 4. Connect the digital voltmeter to the +20 V and -5 V outputs of the H754. 5. Adjust the +20 V potentiometer R17, located on the side of the H754, for a 25 V reading. 6. Connect the digital voltmeter between the -5 V output and ground. 7. Adjust the -5V potentiometer R21, located on the top'of the H754, for -5 V. This procedure is necessary because the +20 V potentiometer sets the overall output of the regulator (25 V from +20 V to -5V), while the -5V adjustment controls the -5V to ground output. Refer to schematic drawing D-CS-H754-0-1. 5.4.2 | 8. Power down and then reconnect the load. 9. Power up', recheck the voltages at the option backplane, and if necessary, adjust the outputs again. Sense Strobe Delay and Drive Current Adjustments Correction of any failure in either the sense strobe delay or drive current circuits on the G235 module that would require reconfiguration of the jumpers within these circuits should not be attempted in the field. Replace the faulty module with a spare G235 module and return the faulty G235 module to the factory for repair. 5-8 5.4.3 PCL SSYN DLY L Adjustment Procedure This adjustment, for systems with parity, sets a 135-ns delay from the leading edge of SSYN INT BUS L to allow sufficient settling time for the parity checking logic. Too long a delay will result in increased cycle time and access time. | 1. Load a branch dot instruction with a 000 777 format into an even address within the addressing range of the MF11-UP backplane being checked. 2. Connect channel A of the dual-trace scope to pin BO2U1 and channel B to pin A02S2 of the M7259 module. 3. The delay from the 1 V point on the falling edge of the SSYN INT BUS L waveform to the 1 V point on - the rising edge of the PCL SSYN DLY L waveform should be 135 ns as shown in Figure 5-4. 4. Adjust R16 on the M7259 module for 135-ns delay. CHANNEL A SSYN INT BUS L BO2U! \ \1VOLT «——— 135ns | CHANNEL B PCL SSYN DLY L A02S2 | ' 1 VOLT 11-2440 Figure 54 5.4.4 SSYN DLY L Timing Waveform Corrective Maintenance Aids | Figure 5-5 is a troubleshooting chart arranged as a 2-axis grid that identifies fault versus location. Figure 5-6 shows the sense/inhibit circuitry and Figure 5-7 shows the various waveforms associated with the sense/inhibit circuitry. The encircled letters in Figure 5-6 are keyed to the waveforms in Figure 5-7. The drive circuitry is shown in Figure 5-8 and the associated waveforms are shown in Figure 5-9. The encircled letters in Figure 5-8 are keyed to the waveforms indicated in Figure 5-9. Figures 5-10 through 5-13 show the component layout of the MF11-U modules -and designate the various functional groupings. Figure 5-14 shows the M7259 Parity Control Module employed with the MF11-UP. The waveforms are taken in the DATI and DATO modes with worst case memory patterns. They are representative of waveforms taken while running the 0—124K exerciser (DZQMB) with a starting location of 200. Signal MATB A EARLY L at pin CK1 of the M8293 module can be used as a sync signal for the scope. Minor variations in the waveforms may be observed between different memory systems. 5.5 MAINDEC TESTING Certain DEC programs can be used to test various memory operations as an aid to troubleshooting. The purpose of each of these memory-related test programs, as well as the program abstract, is given in the following paragraphs. Each program contains instructions for use. 5-9 5.5.1 0—124K Memory Exerciser (MAINDEC-11-DZQMB) The purpose of the 0—124K Memory Exerciser program is to test contiguousn. memory addresses from 000000 to 757776. It verifies that each address is unique (address test) and that each memory location can be read or written reliably (worst case noise test). If memory management is available, all testing is performed with memory management enabled (unless disabled). This program may be used to adjust/margin memory. 5.5.2 0—124K Memory I/O Exerciser (MAINDEC-11-DZQMA) The purpose of the 0—124K Memory I/O Exerciser is to test sequentially all locations of core memory, or any 4K section of core memory, using any NPR device specified. The program checks bank selection, effective address bits, and memory. It can run stand alone or with a memory management device to access extended memory. Worst case noise patterns are used with the NPR device to test memory. Printouts of NPR device errors are provided and include designation of the device under test, the content of its control and status register, and the content of its error register. Data error printouts include the address of the bad data, the true data sent, and the bad data received. 5.5.3 Combined Parity Memory Tests (MAINDEC-11-DCMFA) The purpose of the Combined Parity Memory Tests is to locate the parity memory registers and perform a check of the bits in each. A map showing the memory controlled by each parity register is created by the program. The parity registers and memory are tested using the information in the map. | Several bit patterns are written into each parity memory location to ensure that no parity errors are created. Each byte of parity memory is written with both good and bad parity to ensure that the parity bits can be toggled and sensed. | | 5-10 g Memory Hangs Bus co0 DATO Fails X | cot DATIP Fails X | cof X CO0 Many Bits Fail +5 X FA2 Picks Bits Lo Hi Drops Bits Hi Lo Byte Failures 4 Bits Fail 2 Bits Fail 1 Bit Fails Fails All Addresses Al—-A3 Common A4-A6 Common A7—-A9 Common A10-A13 Common READ Waveforms Wrong WRITE Waveforms Wrong No Inhibit Location C = G114 Sense Control X = Indicates Circuit Not Operable S = Stack Lo = Measured Parameter Too Low or Early D = G235 Driver Hi = Measured Parameter Too High or Late Figure 5-5 Trcubleshooting Chart 5-11 +20V +5V DC LO L Circuit x x Respond to MSYNL x x Memory Does Not Backplane D READ/WRITE Timing Signals XDR XSS YSS Y I Generator YDR Stack Discharge Circuit X I Generator Stack Thermistor X-Y Volt Reference Circuit Stack X-Y Line Stack Diode 17 mV Threshold Stack S/I Line Data Latch Inhibit Driver Sense Amplifier or Terminator Bus Receiver Driver OUTPUT ENABLE H INIT L Circuit INHIBIT TIME H CLEARMIR L CLK MIR H SENSE STROBE H > PAUSE Flip-Flop x Symptom Read Lockout Flip-Flop Failure SSYN Flip-Flop -5.1V Circuit Device Selection or Jumpers Possible DELAY Flip-Flop or DELAY Line C Loc. - +20V D520 y SIN A L POWER FAIL — SIN A INH TIME _fit ® — ES10 C515 506 @ SINA SENSE TP [ STROBE O H ES506 \_/ { E502 °- ESO7 +5V D SET E509 1 @ @0—_—4—* BUS D29 L B SINA CLK MDR OH ® 4CCLEAROj SINA OQUTPUT © ENABLE H SINA CLEAR MDR OL 11-1796 Figure 5-6 Typical Sense/Inhibit Circuit (D0O) 5-12 1V/em 100 ns/cm 1V/ecm 100 ns/cm 1V/cm 100 ns/cm Figure 5-7 Sense Inhibit Module Waveforms (Sheet 1 of 4) 5-13 " 5V/cm o 100 ns/cm 10 V/cm 100 ns/cm 20 V/cm 100 ns/cm A Figure 5-7 Sense Inhibit Module Waveforms (Sheet 2 of 4) 5-14 20 mV/cm 100 ns/cm 1V/cm 100 ns/cm 1V/cm 100 ns/cm Figure 5-7 Sense Inhibit Module Waveforms (Sheet 3 of 4) 5-15 1V/em 100 ns/cm 1 V/em 100 ns/cm Figure 5-7 Sense Inhibit Module Waveforms (Sheet 4 of 4) L-o.SH¥3AING 2Ing1y 8-G v MNIS3NIL~ I [Bo1dA],9LIM/PeoySALI(MJNJIISNOLINLYI) X JOAYdd LIYM 8e3d | 3024N0S JNIL "ll"L 113 INdd A324n0SawYiL I ‘ XAt . $ G 9 L3 -SIHOLIMS |oo\fiBm—o=o=&=|WT=V&OIW=d,A=LoQJAm=IwNG&=@IN=ITP|!LV4d0/LY~IH|I|O NH O9LHD"MOLVMLDS oAdyeS6AL2YdA_@'||©!oL¥3H10$3010 XJSLIOSMo| | 3y av S6.l-1 aXv3y T J ! JLIYM Auv,LNEr 5-17 ' J 1V/cm 100 ns/cm GND 5V/cm 100 ns/cm GND 5 V/ecm 100 ns/cm GND Figure 5-9 Drive Module Waveforms (Sheet 1 of 3) 5-18 5V/cm v 100 ns/cm 5V/ecm 100 ns/cm 1 V/em 100 ns/cm Figure 5-9 Drive Module Waveforms (Sheet 2 of 3) 5-19 5 V/em 100 ns/cm GND 5 V/cm 100 ns/cm - GND 5 V/ecm 100 ns/cm GND Figure 5-9 Drive Module Waveforms (Sheet 3 of 3) 5-20 S o0 \ Sdg 0 © 2Erws B= N‘w<<>: EDQZU O c =W0On : Ml Ju go w W =~fTrxz S O @ WwO=HSpsSz Z - L] WE=EIzvEESE .LLI<LI.L'C<_ - [ T 0OTOo00aVXE ~wWwocK We W3, W5 Figure 5-10 M8293 16K Unibus Timing Module 6705-2 Z25L20=24<Cnxru>d 5-21 L'9L6L'8L68L'oLcL'clLGL'vL L0 ec G'y L'9 ’ ‘ ’ p . sSdinysdSN3S"SnAgDSY(0HS13)NAgIY(AS)(S) LIGIHNI LigIHNI LSSHHIIWIONILVHHdA14aOHOS4NSV34dNNLVSYV.YLH ((OS)L) vivda 91SF[2I][QUnI-NYSDU§PL]O]J 5-22 d3AIHA-X d4300903a SIHOLIMS-X (8) () SHIAIHA- (8) STHOLIMSA 39041S LINJHIO c-2v9 INIHHNO $304NOS 3114MW/av3ay INIHHND eSHIA4Ng(6) MLN3IHND SNO3ANVI13ISIN m“m ONINIL . 1iNd4d1d — 430923d 5-23 dOLSINY3IHL AJVLSO dDHVH 1iNJ4HID 3ASN3S 5-24 omSrg+1-S6STLINAJredToNu0)SINPOI l-L269 NAS Avi3aININLSNrav 9LYH 174,Y] em cM ALIYVdHOHY3dOL1VIIANI (s LM 5-25 APPENDIX A IC DESCRIPTIONS A-1 A.1 741 HIGH PERFORMANCE OPERATIONAL AMPLIFIER The 741 Operational amplifier is a high performance amplifier featuring offset-voltage null capability. The devices are short circuit protected and the internal frequency compensation ensures stability without external components. INVERTING 4 PUT J’j | j > Ve t\, t’j ?\1 o - 30pF T NON-INVERTING . INPUT 4.5kQ | 7.5k VWA~ L/ 339KQ S } 1kR$ 50kQ3 31k : OFFSET NULL N1 OUTPUT 509 ] A 4 OFFSET NULL N2 250 . ,_[: | 5k & 50k0$ & & $509 & ‘C>Vcc" ' NOTE: Component values shown are nominal. NC Veet OFFSET NULL N1 INPUT INV. OUT- OFFSET NULL NON Vee PUT INV. N2 INPUT 11-2138 A.2 7442 4 LINE TO 1 LINE DECODER These BCD-to-decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. TRUTH TABLES BCD Input D C B A o1 0 0 0 0 ol 0 1 1{ol 0 1 0 1{1lo]1 0 0 1 1 1f1l1f{of1 0 1 0 0 1 0 1 0 1 11111011 |1 |1 0 1 1 0 1 |1 ]1 0 1 1 1 11111 |14 0 |1 f1f1f1r{o}1 fr {1t ]1]1 |1]1 ]o 1]t {111 ]o]1 {1111 ]1]0 0 0 1 0 1 1111 1 0 1 0 {11y 11 1 0 1 1 {11ty 1] {11111 1 1 0 0 RN 1 1 0 1 P11t 1 1 ] 0 P11 1 1 1 1 1Tl 3 2 {1 0 A C D 9 8 7) 131 |1 2 11 10 9 i — C 4 ’ 5 T 8 ‘ T l 9 E—A‘ 4 5 6 _ ¢ ‘>° GND PUT OUTPUTS ) INPUT CO———[::)S ° e s s 17 Led 3 wl B D 6 l R oot INPUT Bo———{ >0—¢ OUTPUTS B : ! lofr 0 I !T fiT i D |1]1 1|11 1 A 2 {11 ]1]1 w.orss INPUT D 0—<Dc _ Y _ D D o Py YYYIVUUL 15| {111 111 1111 o [Olwl|p o joljml>l|ojo o > oo |om 1>|]o|o o> |jol|o o] (ololm |2 joljol|o [pi|ojoljal|2 |oljol|ol] i 16 11y 1 A B ot |89 b1 0 A | 2131451617 0 Vee ' Decimal Output 0 INPUTS J.. - OUTPUT O OUTPUT 1 OUTPUT 2 OUTPUT 3 OUTPUT 4 QUTPUT 5 OUTPUT 6 QUTPUT 7 OUTPUT 8 OUTPUT 9 1-0734 A-3 Parameter MAX Unit 30 ns 23 35 ns 17 25 ns 26 35 ns MIN TYP 10 22 Propagation delay time to tde logical O level through - two logic levels Propagation delay time to tde logical O level through three logic levels Propagation delay time to tpdl logical 1 level through 10 two logic levels Propagation delay time to tpdl logical 1 level through three logic levels A4 A.3 7475 4-BIT BISTABLE LATCH The 7475 latches are used for temporary storage of binary information. Information present at a data (D) input is transferred to the Q output when the clock is high, and the Q output will follow the data input as long as the clock remains high. When the clock goes low, the information (present at the data input at the time of the transition) is retained at the Q output until the clock is permitted to go high. Truth Table ] CLOCK ] t (Each Latch) 1Q 2Q 2Q 1-2 GND 3Q 3Q 4Q 16 15 1[ 13 12 11. 10 9 | _ | Q Q Q Q Q Q Q Q CLOCK D D CLOCK CLOCK D D CLOCK I T J l_ T 1 2 1Q 1D I 1 | 3 l I 4 I 2D CLOCK 3-4 ® I1 tn tn+1 D Q 1 1 0 0 NOTES: 1. t_ = bit time before clock negative-going transition. 2. tn+1 = bit time after clock | l 9) I (S 7 Vee 3D 4D negative-going transition. 8 | 49 11-0894 16 15 14 B PACKAGE 13 12 11 10 9 5 6 7 8 GND Vcee ® < :;80.0. <L:;16K 2 3‘ 4 4K <::16K ® 4K —0 Vee 4K <L :;80 < ) [ 12K Q —o0 Q ) $13K $13K ‘1 ® CLOCK o GND oD II-0468 A-5 MIN Parameter MAX | Unit 14 20 | | Minimum logical 1 level input i setupO *hold1 *hold0 ¢ ¢ Pdl(D'Q) pd0(D-Q) tp dl(D-(-))v tde(D_‘é') D input setup time at Minimum logical O level input setup time at D input Maximum logical 1 level input Maximum logical O level input o1 1 | 1 16 30 s 14 95 s 24 40 ns 7 15 ns 16 30 ns 7 15 s 30 ns - level from D input to Q output | Propagation delay time to logical 1 level from D input to Q output | (SN5475, SN7475) Propagation delay time to logical O level from D input to Q output | (SN5475,SN7475) Propagation delay time to 10gical 1 ¢ Propagation delay time to logical O | pd1(C-Q) level from clock input to Q output tpdl(C-a) | | Propagation delay time to logical O i pd0(C-Q) | 0 hold time required at D input Propagation delay time to logical 1 level from D input to Q output 15 0 hold time required at D input ns | level from clock input to Q output Propagation delay time tological 1 | 16 level from clock input to Q output | | (SN5475,SN7475) , Propagation delay time to logical O tde(C-fi) ~ level from clock input to Q output 7 | 15 | ns - (SN5475,SN7475) | These typical times indicate that period occurring prior to the fall of clock pulse (to) below 1.5 V when data at the D input will still be recognized and stored. A-6 / setupl - ¢ | TYP A.4 7483 4-BIT BINARY ADDER The 7483 Binary Adder adds two 4-bit binary numbers. The sum outputs are prov1ded for each bit and the resultant carry is obtained from the fourth bit. A3 : A1l S1 B1 CARRY IN B3 -] | S2 ' LOGIC 16 15 B4 S4 14 CARRY OUT DIAGRAM 13 CARRY CARRY OUT IN 12 " 10 9 GND B1 A1 S1 Vee PIN LOCATOR (TOP VIEW OF IC) 8E-0I30 A-7 \4.“4// Input Output Al A3 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 1 1 0 1 -0 1 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 1 0 0 0 1 0 | 0 1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 NOTE: 1. Input conditions at Al’ A2’ Bl’ B2, and CO are used to determine outputs 2 and 22, and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4, are then used to determine outputs 23', Z4,and Cy. A-8 Parameters§ MAX Unit 34 — 40 ns s tpd1 38 ns *pd0 42 ns 50 ns thdl tde From To (Input) ~ (Output) Co MIN TYP | 1 tpdl Co tpdl tde J o 4 o C4 , — 3 55 ns 55 - ns . * tpdl 40 - ns tde 35 ns tde 35 ns A.5 7485 4-BIT COMPARATOR The 7485 performs magnitude comparison of straight binary or straight BCD codes. Three fully decoded decisions i; . J A<B, A =B) about two 4-bit words (A,B) are made and externally available at three outputs. 1 e [> Q L fiy J U@f A2 o— A<B oA=B o A>B o ’ \a.cau//l’ k (A > B, A<B o BO ‘ [ ) 1/ DATA INPUTS Vee r : A3 B2 16 — A1 B1 AO — BO 9 15 14 13 12 11 10 A3 B2 A2 A1 B1 AO A=B IN A>B IN A>B OUT A=B OUT A<B OouUT 4 5 B3 BO - A<B IN 1 2 3 B3 A<B A=B DATA "¢ INPUT A2 A>B_A>B —- N CASCADING INPUTS 6 7 8 A=B A<B GND —— OUTPUTS positive logic : See truth table f.Pin assignments for these circuits are the same for all packages. I-2136 A-10 TRUTH TABLE CASCADING COMPARING INPUTS A2,B2 A3 > B3 X X X A3 < B3 X X A2>B2 A3=B3 | A1,B1 =B A>B A<B A=B X X X H L L X X X X L H L X X X X X H L L X X X X X L H L X X X X H L L A3=B3 | A2<B2 | A2=B2 | A1>B1 A3=B3 | A3=B3 | A0, BO A>B OUTPUTS A< B A3=B3 A3=B3 NOTE: | INPUTS A3, B3 A2=B2 | A1<B1 X X X X L H L A2=B2 A1l1=81 A0 > BO X X X H L L A2=B2 Al1=81 A0 < BO X X X L H L A3=B3 | A2=B2 A1=B1 AQ = BO H L L H L L A3=8B3 A2 =B2 A1=B1 A0 =BO0 L H L L H L A3=B3 A2=B2 A1 =81 A0 = B0 L L H L L H H = high level, L = low level, X = irrelevant Parameter MIN TYP MAX Unit 90 150 ns 75 150 ns 75 150 ns 55 100 ns Propagation delay time, low-totppg high-level output, from any A or B input Propagation delay time, high-to- tpgy, low-level output, from any A or B input - Propagation delay time, low-totpry high-level output, from A > B, A <B, or A =B inputs Propagation delay time, high-totpHL low-level output, from A > B, A <B, or A =B inputs A-11 A.6 7528 SENSE AMPLIFIER The 7528 integrated circuit contains two dc coupled single-preamplifier sense amplifiers. The output of each preamplifier is available as a test point. These test points can be used to observe the amplified core signal to facilitate accurate strobe timing. Avoid coupling the strobe signal or other stray signals to the test point and also avoid excessive loading of the test point. Waveforms F and G in Figure 5-8 (schematic shown in Figure 5-7) are the input waveshapes and waveform H is the output waveshapé for a typical sense/inhibit line. ~ DEFINITION TRUTH TABLE INPUTS OUTPUT _S w_ A H H H L X L % L OF LOGIC LEVEL L H INPUT X [Vip>VT Max|Vip<VT MIN|IRRELEVANT At Vi>VIH MIN S V|<V||_ MAX|IRRELEVANT 'A is a differential voltage (V|p) between Al and A2. For these circuits V|p is considered positive regardless of L which terminal is positive with respect to the other. -1zz- OUTPUTS Von 'CC 16 1P 115 STROBE 1S TW N STROBE 2W 2S 2P GND 14 13 12I 10 S 7 8 2A2 V¢¢ 1 1" l ) 1 2 3 4 CexTt 1A1 1A2 -VRer 5H -VREF 6 2A1 POSITIVE LOGIC: W=AS A-12 Symbol Propagation Delay Times From Input To Output Al—-A2 W STROBE A\ MIN tPLH — propagation delay time — low level input to high level output tpyr — propagation delay time — high level input to low level output (D) - (S) — TYP MAX Unit A.7 82562 9-BIT PARITY GENERATOR AND CHECKER The 82562 Parity Generator/Checker has two outputs (EVEN and ODD) and an INHIBIT input that disables both outputs. A logic 1 on the INHIBIT input forces both outputs to logic 0. When used as a parity generator, the 82562 supplies a parity bit which is transmitted with the data word. At the receiving end, the 82S62 can be used as a parity checker to indicate that data has been received correctly or that an error has been detected. (1 P1 ® (2) (3) P3 @ Pa © (10) e "6 @ (1) w ' T | _ ) O '. - INHIBIT o (s | | . > . ) | ; (9) EVEN © ouTPUT L_DO_OOUTPUT (6) 0DD © Pg (13) Pg O (5) NOTES: 2. GND=(7) 3. () =denotes pin number, pin numbers shown for Dual in-line package only 4. ODDOUTPUT = | PI® P, ®P3® Py® Pg® Pg® P, Pg® Pgq EVEN OUTPUT = P1® Po®P3® P, ® Py ® Rg® P7® Pg® Pg 11-24 41 . ' AN 5. A-14 A-8 74121 MONOSTABLE MULTIVIBRATOR The 74121 Monostable Multivibrator features dc triggering from positive or gated negative going inputs. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Once fired, the outputs are independent of the input pulses and are dependent only on the timing components on the chip. Input pulses may be of any duration relative to the output pulse. TRUTH tq INPUT |t A1|A2| B t{1 o[t | TABLE INPUT |A1|A2| | OUTPUT B Vee [t ] INmBIT O|X|1]OflX|0O]| _ l1al]13 INHIBIT X|1|o|x[{O]|O]| NC INHIBIT TIMING NC n A 12 || 11 ] PINS 10 , — lolx|o]|0O|X]|1]|ONE SHOT X|0|O|X|[0O]1|ONE SHOT 114 |1]X{0]|1]|ONE SHOT| 1{1[1]0]x]|1|ONE SHOT X|o|o|Xx|1|[O]| INHIBIT X INHIBIT ofxX |11t 1] 4]1] INHIBIT 1{1]o0|x|0]|0O]| INHIBIT t]1/0]Jofx]O[ INHIBIT 1= V. in(1) 8 Q | J P INHIBIT Oo|x|Oo|1]|x]|O]| o111} NC 9 Q | — =2V = Q@ 0= Vin (0) < 0.8V 2 3 4 5 NC At A2 B H 6 7 Q GND f1-1119 NOTES: 1.t =time before 7. input transition. External timing capacitor may be connected between 2. t, 41 =time after input transition. pin (A0 pin () .With no external (positive) and capacitance, an output pulse width of typically 30 ns is 3. X indicates that either obtained. a logical O or 1 may | be present. 8. | resistor (2 k2 nominal), 4. NC = No Internal . 5. connect pin @ to pin Connection. Al and A2 are negative-edgetriggered logic inputs, and will 9. trigger the one shot when either 6. To use the internal timing To obtain variable pulse width connect external variable resistance between pin @ or both go to logical 0 with B and pin at logical 1. current limiting is needed. Bisa positive Schmitt-trigger 10. input for slow edges or level . No external For accurate repeatable pulse widths connect an external detection, and will trigger the resistor between pin one shot when B goes to and pin logical 1 with either Al or open-circuit. A2 at logical 0. (See Truth Table). A-15 @ with pin @ Parameter MIN TYP MAX Units 15 35 55 ns 25 45 70 ns 20 40 65 ns 30 50 80 ns 70 110 150 ns Propagation delay time to logical 1 tp d1 | level from B input to Q output Propagation delay time to logical 1 tpdl ~level from A1/A2 inputs to Q output Propagation delay time to logical O tp 40 » _ level from B input to Q output Propagation delay time to logical O tde _ B level from A1/A2 inputs to Q output Pulse width obtained using tp( out) | internal timing resistor Pulse width obtained with | zero timing capacitance Pulse width obtained using 'p(out) externalN timing resistor thold 600 700 300 1 6 7 3 ms 30 50 ns Minimum duration of trigger pulse A-16 A.9 74154 4-LINE TO 16-LINE DEMULTIPLEXER The 74154 4-Line to 16-Line Demultiplexer decodes four binary coded inputs into one of 16 mutually exclusive outputs when both strobe inputs (G1 and G2) are low. The demultiplexing functionis performed by using the four D "_}2 — o} o | input lines to address the output line, passing data from one of the strobe inputs with the other strobe input low. When either strobe input is high, all outputs are high. 26 o\ o/ [ : —DC"‘F°{> : — 3 184 w | N ol i slelv siels]e 'F_} | I P 16 11-0637 A-17 TRUTH TABLE Outputs Inputs Gl H H L H H H H H H H 4 H H H H H H H H H H H H H L H H H H H H H H H L H H H H H H H L H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H H H H H H H H H , H H= 11 10 G2 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H high, L = low, X = irrelevant Signal/Pin Designation N (=TMLR]o - 75] A-18 = ~—) oy o - o 12 13 14 15 DUAL-IN-LINE Vee PACKAGE INPUTS 2423224 A B OUTPUTS 212019181716 C D G2 G1 15 14 1514 - 13 rQ 0 1 S A N/ A— . (TOP VIEW) {13 12 1 Pp— 1 2 3 4 5 6 8 9 |2| 3| 445 6 7 9 o112 N ~ 10 / GND OUTPUTS i1-0636 Parameter MIN - TYP MAX Unit 22 33 ns Propagation delay time, low-to-high-level output, - from A, B, C, or D inputs through 3 levels of logic Propagation delay time, high-to-low-level output, 'PHL from A, B, C, or D inputs through 3 levels of logic Propagation delay time, low-to-high-level output, from either strobe input Propagation delay time, high-to-low-level output, from either strobe input A-19 A.10 75325 MEMORY DRIVERS The 75325 Memory Drivers contain two source-switch pairs and two sink-switch pairs. Source selection is determined by one of two logic inputs and source turn-on is determined by the source strobe. Sink selection is determined by one of two logic inputs and sink turn-on is determined by the sink strobe. This arrangement allows —_ 1 m V5 w RINT D 5 6 7 8 S2 C Y GND © Z Veed 18] Veeo x S selection of one of the four switches and its subsequent turn-on with minimum skew of the output current rise. 2 3 SOURCE W COLLECTORS A 4 S1 2 _2ey STROBES positive logic : See truth table 11-2137 TRUTH TABLE Address Inputs Source Strobe Inputs Sink Outputs - Source Sink Source Sink A B C D S1 S2 1 X Y Z L H X X L H ON OFF OFF OFF H L X X L H OFF ON OFF OFF X X L H H L OFF OFF ON OFF X X H L H L OFF OFF OFF ON X X X X H H OFF OFF OFF OFF H H H H X X OFF OFF OFF OFF H = high level, L = low level, X = irrelevant NOTE: Not more than one output is to be on at any one time. A-20 Parameterd To (Output) MIN TYP MAX 25 50 Source collectors ns tPHL Source outputs ns 'THL ) / Sink outputs ns tPHL T H _ ) 20 45 7 15 9 20 15 30 Sink outputs ns tTHL t Unit Sink outputs S tpy g = Propagation delay time, low-to-high-level output tpyr, = propagation delay time, high-to-low-level output tTLH = transition time, low-to-high-level output traL = transition time, high-to-low-level output t, = storage time A-21 ns READER’S COMMENTS MF11-U/UP CORE MEMORY SYSTEM MAINTENANCE MANUAL EK-MF11U-MM-003 Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications. What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well written, etc.? Isit easy to use? What features are most useful? What faults do you find with the manual? Does this manual satisfy the need you think it was intended to satisfy? Does it satisty your needs? Why? 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