MF11-U/UP Core Memory System Maintenance Manual

This document is a maintenance manual for the Digital Equipment Corporation (DEC) MF11-U and MF11-UP core memory systems, published in 1973 and 1974 for the PDP-11 computer line.

Key aspects of the manual include:

1. General Description: It introduces the MF11-U (without parity) and MF11-UP (with byte parity) as read/write, random access, coincident current, magnetic core memory systems, each providing 16,384 (16K) 16-bit words. It details their physical components (modules like the M8293 Unibus Timing Module, G114 Sense Inhibit Module, G235 X-Y Driver Module, and H217D/C Stack Module), specifications (cycle times, access times, power, environmental conditions), and functional units.
2. Memory Operations: The manual explains the four basic memory operations:
   • DATI (Data In): A read/restore cycle where data is read from memory, sent to the Unibus, and then written back due to core memory's destructive readout.
   • DATIP (Data In, Pause): A read-only cycle where restoration is inhibited, used for read-modify-write operations to reduce cycle time. It must be followed by a DATO or DATOB cycle.
   • DATO (Data Out): A write cycle where core locations are cleared (read to 0) before new data from the Unibus is written.
   • DATOB (Data Out, Byte): Similar to DATO but allows writing specific bytes while restoring the non-selected byte.
3. System Architecture and Logic:
   • It provides detailed descriptions of the 16K Unibus Timing Module (M8293), covering memory protection circuits (power monitor, bias current detection), operating mode selection logic, and control logic that generates precise timing signals.
   • It elaborates on Device and Word Selection, including memory organization, addressing conventions, and how address bits are decoded to select specific memory locations using jumpers for configuration (e.g., interleaved/non-interleaved operation).
   • Driver, Sense, and Stack Modules: This section describes the core array's three-wire configuration (X, Y, sense/inhibit lines), the coincident current principle for read/write operations, X and Y decoding, and the current generation (X/Y current generators, inhibit drivers), sense amplifiers, and stack charge circuits.
4. Parity (MF11-UP Specific): Chapter 4 focuses on the MF11-UP, which requires an M7259 Parity Controller Module. This module performs odd parity generation and checking for 16K or 32K of memory, communicates via an internal bus, and includes a Control and Status Register (CSR) for programming error detection and diagnostic functions.
5. Installation and Maintenance:
   • Installation: Covers mounting, power requirements, and jumper configurations for memory addressing, interleaving, strobe margin, and bias current. A step-by-step installation procedure is provided, including initial diagnostic runs with specific jumper/resistor modifications for testing.
   • Preventive Maintenance: Outlines regular tasks (every six months) such as visual inspection, voltage and current measurements, timing checks (sense strobe delay, SSYN delay for parity), and running diagnostic programs (MAINDEC series) to ensure optimal performance.
   • Corrective Maintenance: Provides guidance on voltage adjustments, and critically, advises replacement of faulty G235 Driver Modules or G114 Sense Inhibit Modules rather than field-adjusting sensitive jumpers that are factory-calibrated. It also includes troubleshooting charts and waveform examples.
6. IC Descriptions (Appendix): Provides technical details, truth tables, and pinouts for the integrated circuits used in the memory system.

In essence, the manual serves as a comprehensive guide for understanding, installing, and maintaining DEC's MF11-U/UP core memory systems, offering both high-level functional descriptions and detailed logic and timing information necessary for troubleshooting and repair.