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Document:	M9301 Bootstrap Terminator Maintenance Manual
Order Number:	EK-M9301-MM
Revision:	PRE
Pages:	88
Original Filename:

OCR Text

EK-M9301-MM=PRE

PRELIMIDNARY

M9301

BOOTSTRAP

TERMIWATOR

MAINTENANCE MANUAL

The

information

change

commltment

Digital

this

without notice

document

and

Digital

should

subject

not

Equipment

Equipment Corporation

assumes

construed

Corporation.

respon31b111ty for any errors that may appear in
this

manual,

Copyrlght <:> by Dlgltal Equ1pment Corporatlon
Written

by PPP 11 Englneerlnp

MO3Q1

MAINTENANCE

MANUAL

e
N
W
Ul £
~N O

Power

anmd

Modified
Timing

Groumd

UNIRUS

AV
IR o

Epviromrmental

Temperature

Humidity

HARDWARE

DRESCRIPTION

Imtroduction
Defimition of
Overview

Ul £
§ O

Wee

®»

Relative

Power Up
Extermnal
Power
Power

Address

Adgress

Up
Up

Rom

Terms

Bootimg Logic
Boot Circuit
Tramsfer
Clear
Deteetionm

Offset

Detectiom
|
Logic

Switch

Memory

MO3@Al

Specifications

Range

Pimouts

Pim Assiamments
,

Ul
U1 Ui

Description

Electrical Specification
Power Consumptionm
Electrical Interfaces
Extermal Electrical Imnterfaces
Electrical Prereauisites

Operatimrg

Descriptionr

Prhysical

®»

NNV
IV

Gemeral
Features

fuuf
v

INTRODUCTION

N A

B
W
W

N
N

PREFACE

L
W

W
®

e
i

@
B

Led

(AVER
AV IRV

CONTENTS

Termimator

Bank

|Logic

Page

Comtenmts
4,

MO3A1

4ol

Overview

(Con®t)

VARIATIONS

4,3

MG321=YA

ampgd

4a3,1

Physical

Differemces

43,2

Program

UegSe202

4,3,2,3

Memory

4e3,2,1

Ue3,204

CPU

MO3Qi=YR

Memopy

from

M93Qi=0Q

Maps

Dfagmostics

Display

Routine

Diagnosties

Bootstrap Programs
RX{i

Diskette

TA{l1

Cassette

PCii{ Paper
Disks

Tape

Magtape

8:3,2,5

Console

Emulator

Program

Flows

MOZI@A1

MO3@l

Be3,3

Installationm

493,3,1
4,3,3,2
4:3,3,.3

Reboot Emable
Low Rom Emable
Boot Switch Selection

4,3,3,4

Extermal

Mg}@l'YC
Memory

Gemeral

Switch

Map

Description

d, 4,4

11/79

HoldyB

Installation

Beolyb

Starting

old,7

Errors

549

EXTENDED

Extended Addressimg (Defimation)
Defimation of Virtual and Physical addresse$
Addpress mappimg without Memory Mamagement
Address Mappimg with Memopry Mamagement
Creation of & Viptual address

O
®
D

test

Descriptions

Bootstrap

Memory

Procedyre

ADDRESSING

Mamagement

Addpress

6,0

MO3pi=YD

6pl

Purpose

6o 3
6gqd

Usimg the M93@i=YD
Program Listing
APPENDIX

6o2

Registers

Agsigmnments

~ O

Diagrostic

W R

dol,3

AN
N
R Jiun

48,1

dodye

Boot

Fumctiomality

Page

1,8

PREFACE

This

manmyal

varifous

describes

versiomns,

the

M9341

Complete

Bootstrap/Termimator
umderstamdimg

module

its

that the user have a germeral
kmowledge
of
digital
basi¢
urderstamding
of
PDP=11
computers,
The
documents may be valuable as references,

amd

its

comtemts

rPequires

circyitry
following

amd
&
related

PDPil Peripherals Harmdbook
PDF1l Processor Handbooks
PDP=m11/34,
11/39, USERS MANUAL

2.0

INTRODUCTION

Germeral

Description

The M93Q01 Bootstrap/Termimator i8
which
plugs
1{into
a
termipator

a
double
elot
om

height
extended
module
most PDPI1 computers (see

Instajllation Section
4),
It
contains
a
complete
set
of
UNIBUS
terminatiomn
resistors
alomg with 512 words of Read=0Unly memoryY which
cam
be
used
for
bhootstrap
programs,
The
module
also
provides
cirecuitry
from

photo

2,8

for

inftiatimg

extermal

logic

bootstrap
level

progpams

switeh

either

closure,

See

power

ups

Fiqure

oOP

for

ore

module,

Features

Combines
double

UNIBUS

meight

Ceamn be used
{n
extended length

]

Bootstrap

bootstrap

capability

all
PDPIi
machines
which
cam
module im the termimator slots,

programs

Direct

amd

module,

termimatiem

cam

program

Jumps

{nitiated

the

memory

the

handle
|

followimg

space

meansg

occupied

the

bootstrap,

e
3,

Programmer comsole Load address amd
Power restarts (See Section 3,3)

External

Provides

Boot

switch

capability

start

sequence,

closure

emablimg

disabling

boots

power

restarts,

Provides
512
words
of
wuser
memopy
space
which
programmed
by
the
user or purchased with standard
provided by DEC,
(See sectioms 3,10 and 4,2),

¢€cam
be
pAtterms

Page

Meodule

Photo

5Li/3/9/1 ed

Figyre

Page

2.5

The

Physical

M93p1

module

which

backplame,
and

TP3)

2,4

Description

double

height

plugs

Extermal

tabs

irto

Power

Consumption

+45Y

Amperes

2,4,2

Electrical

The UNIBUS
8881

24,3

the

anmnd

1/2

are made

handle

1/2

termimator

emnd

via

imnches)

slots

three FAST

the

FLIP=CHIP

erm

the

module,

PDPL]

(TPL1,TRZ2,

tvpical

Interfaces

imterface

stamdard

usimg

8837

and

864F

receivers

and

interface consists of three FAST ON tabs

(TP1,

TP2

ard

lead

with

ohm

drivers,

Extermal

The extermal

TP3),

Specification

24,1

2,0

extended

the

comprmections

provided

Eleetrical

each

Electrical

havimng

TP1

the

followinmrg

loadirmrg

Represerts one
pull=up,

Refer

TPe

Interfaces

Input

and usage constraints,

TTL

standard

should be

Sectiomn

3,3

for

TP!

stable during a nov%er

up,

usage,

ohm
1K
a
with
loads
TTL
Represents two stamdard
pull=up resistor,
Input sigmnals should ke JTimited to
a {00ns mimimum pulse
nofse
restricted
to
that

trigogering

width with
all
a
GSms maximum

infitiated

upom

switch
bounce
duratiom.
Note

release

©f

imput

few
(logie "3%") pulse,
Om all power=ups, t"idgeping
is disabled umti]
approximately
19@ms
aftepr
power

returns

(See

available

over

alse

Section

from

the

1mportamt

voltage

3,7)

power

assuming that
supply

realize

protection

that

TP3

Section

Shoyld be

3,5

for TPE

ysed

this

capability

filteping
must
be provided when
oUtside the stamdard DEC computer

+5 VIC

withimn

27ms,

{mput

wil]

has

moO

and

aleaquate

for

eXternal

remoting this imput
enclosure,
Refep

uUsage,

groumd

return

switches attached to TP1 amd TP2,
Note that there is
{pput
no protection for large voltage spikes on this

propeP

filters should be extermally installed to

guarantee adecguate

isolation,

Page

2aldyd
Refer
used,

2,5

2ed,6

See

Electrical
to

Power

amrd

Prerequistes
4,2

for

Groumd

+5VDC3

GND g

PINS

MO9321

TABLE

2eld,7

Section

MODIFIED

system

comstraints

specific

versinm

beimg

Pimeouts
AA2,

BAZ

ACZ2,

UNIBUS

AT1,

Pim

BCZ2,

BT!

Assigmments

Timing

Figure 2 shows important
shown are typical,

timing

constraints

for

FIGURE 2
MO3Z1
TIMING

2.5

Operating

Envirormenta)l

2,5,{

Temperature

2e5,2

Relative

Specificetions

Ranmge

Humidity
=

20@0%

(with

72 ¢

95%

out

comndensation)

the

MO321,

Values

fage &/

Bvs

yNIBUS

Lo L

66—

ADDRESS TRUE

{

Bus

MSYN

UNIGuS DATA

TRUE

TM 60

{

2 40—

Bvs ssyM L

—» 60

e—290—»
i

2
FIGUVRE

masol

TiIMING

| all Times 1n hs ..

Page

TABLE
UNIBUS

ASSIGNMENTS

SIGMAL

SIGNAL

BUS INIT L
POWER(+5V)

BA1

SPARE
POWER
SPARE

AE
2

AF
|
2
AF
AH{

AJ
Y

AJ2
Y
AK
AK2

AL
¢

AM
1

TEST POINT
BUS DCO L
GROUND
BUS
BUS
BUS
BUS
BUS
BUS

D02
DO1
DC4
D03
D06
DOS

BUS
BUS

DQO8
DO7
D12
D@9

BUS
BUS

Di2
D1
D14
D13

BUS

AM2

BUS

AN
AN2

P1
BUS

1
AP
AP
2

+2@V

AU2

BUS

AVL
AV
2

+20@V

AT
¢

+2@V

BE
{
BE
2
BF§
3F
2

PARs DET,
BUS ACLO L
BUS DCLO L

INT,

SSYN,

BH
1
BH2

BUS

AQ1

BJ1

BUS
BUS

A03
A@2

BUS
BUS
BLS

A@5
A@d

BLUS

BUS

AQQ

A@7

AR6
AA9
AG8

BM2

BUS
BUS

BN{

BUS

BN2

At1l

BUS

AL®@

BMy

AT
2

AS2

BAT=BACKUP
BR 4L

BL
1
8.2

AR
{

BD1
BD2

BJ2

BUS BBSY L
BAT BACKUP +15V
BUS SACK L
BAT, BACKUP =15V
BUS NPR L
GROUND
BUS BR 7L

AR
2
AS
|

BC
2

TEST PQINT
BUS BR 8L
GROUND

3C
1

BK
1
BK
2

(+5V)

BP
1
BP
2
BR
BR
2
BS
1
BS
2
BT

BT
2
BU{

gl sl

AD
Y
AD2
AE
{

gt mlt autl sl autl

AC?2

INTR

HA2
BA
1

BUS

413

BUS

A2
A1{S

BUS
BUS Af{d
BUS A17
BUS A16
GROLUND
BUS C! L

ol putt ol

AC
{

BUS

ryrrevT
s
e rrya
e

AB
Y
AB2

MODIFIED

MO321

BUS

BU2

SSYN
L

BUS

BV
1
BY
2

BLUUS

MSYN

mhy

+5V

Page

3,8

HARDWARE

3.1

Imtroduction

DESCRIPTION

The
followimg
1s
Bootstrap/Terminals

detajled
ecirecuit
deseriptiom
of
the
medule,
Various segments of this module

amalyzed

separately for clarity,
M9331
Peferenced throughtout the descriptionm,

3,2

Defimition

3,241

bootstrap

5,2,2

Boot

PBootstrap

prPogPram

ecireuit
schematics
(CS MOG3dl=i=1),

MO3E
wi{)l be
will

Terms

Program

program

imto

computer

any

program

memory

from

meams

whieh
a

Joad

peripheral

amother

(usuallv

Yaprger)

device,

HBoot

§sAa verb which

{mritiate

execution

Rootstrap

pProgram,

3.8,59

Bootstrap

3,3

and

bootstrap

program

are

used

interchanmgeably,

Overview

Typically all
Wp
seguerece
seguence

PDPLL computers
each time power
follows}

perform what is referred te as
a
18 applied to their CPU module(s),

power
This

Page

3.3

Q0Overview

continued
+SVDC

BUS

DC
BY

BLUS

COMES

POWER

AC LO L
BY POWER

PROCESSOR

RELEASED
SUPPLY

RELEASED
SUPPLY
MEMORY

FOR

NEw PC

PROCESSOR

ACCESSES

LOCATION 26(8)
PROCESSOR
AT

TRUE

ACCESSES

LOCATION 24(8)

WITH AN M93A{
power Ups the

BEGINS
NEw PC

MEMORY

NEW PSw

FOR

RUNNING

PROGRAM

CONTENTS

BOOTSTRAP/TERMINATOR IN THE PDPi{{
computer
system,
user can optionally (a switch omn the M9321 cam emable

on
or

disable this feature) force the processor to read its mew
PC
from
&
ROM memory Jocation (unibus Locatiem 773324(8)) and offset switch banmk
en the M93ai,
A mew PSW will also be read
from
a
locatiom
(UNIBUS
Lecatiom
7730226(8))
im
the
M9321 memory,
This mew PC and PSW wil]

them direct

M93py{

I{f

ROM

the processor

(UNIBUS

bootimg on

and
be
Programs

memory

power

ups

to a orogram

leocatioms

uysed
te
force
im the M93Q1 cam

The

Power
|LO

and

jimes

status

eontrol

limes

UNIBUS

Bootimg

773776),

extermal

switch

the
START
is available

switeh
in the

feature
system,

processor
to
execute
be imitiated by program

starting
addresses
oF
through
programmer?’s switch console 1If one

3,4

thru

disabled

the
also

(typically a bootstrap)

7730¢2

logic

the

level

a boot program,
Jumps to
theip

Logie

every

PDP11l

BUS AC

relation

power

amd

the ¢5 volt

speci{ficatiens

supply

BUS

output

summarized

cdescribed

The

the

conditiom

two

the power supply

Figure

UNIBUS

these

138

two

defimed

Pacge

Fiaure

Power

the

Power

M9321,

Figure

BUS

LQO

are

Power

When

sequerces
+5

asserted

volts

low,

(Si=2)

goes higk followed by BUS
gemeratimg a low=to high

13,

This

address
300

S g

tramsition

Jimes

Seauence

BUS

on,

flip

triggers

A@9

detected

becomes

true,

both

POWER

Assumimg

switch

closed

are

first

DC LO L
cleared

fail

DOWN

Power

BUS

the

A12

flop

the

E29

wil]l

AC LO
L,
tramsitiom

one=shot

amd

circuitry

them

Bus

which

A12

shown
LO,

REBOOT

set,

this
flip=flop
om the output of

E21

BUS

the

whem

assepts

thru

BUS

anmd

ENABLE

BUS

18
then
E20 (pinm

A17

UNIRUS
L

ferp

fage 1A

AC POWER

—L

PeWER

Ae LO
pe c LO

POWER UP

DowH

PoWER

o‘

]

‘

]

;

;l
I

fi/: ¢ I

')O ‘

'2ems t
b

EPV TRAPS

i
|

FIGURE

CPU

TRAPS

Power Fail Segvence

FIGURE
POWER

Processor

Durimg

reads

the

300

pepforming

the

address

MO3@!

rom

Jectiorm

Haying

which

boot

pPead

mneéw

read

26(8),

celly
ROM

ODORed

E21,

asodress

LOGIC

the

When

address from
the ome=shot

This

location

contaims

the

<central

the

AB9,

BUS

was

Al1@,

and

status

happens

starting

new
a

from

new

location

Processor

address
gemerate the

space,

0Once

BUS

A12

guarantee

complete

the

two

memory

address

limes,

REBOOT

will
te

read

24(8),
the
te gemerate

address

speciflc

the

(see

word

chosem

POWER

attempts

memopry
locationm
are logically ORed

773024(8)3
Statys

ENABLE

thru

the

Word

procesSor

(PSK)

fpem

then
memory

bits
enabled
by
ere=shot
EZ2]
address 773026(8B)
which
is also im
this

tramsfer

is completed

of
MSYN
frem
the bus will gemerate @ ADDR
506) which clears the onme=shot (E21) timeout

Eel

processor

routime,

The
to

BOOT

counter

sequence,

773024(8),

ation

time=out

counter (PC)
enabled
by

ebtsined

attemptes

program

power

space

3,9)

280P

{ts

a new pregram
address
bits

new

BUS

enough

A17,

time

transfers

the

removal

CLR L signal (See Section
removimg address blts BUS

The

for

the

329

all

described

timeout

PDPI!

before

lePgth

processors

releasimg

the

flaj@ /1 H

EXT BooT E~AB L
ol
Buvs

pelo

pect

3°°”s.f’

ADDR ENAB (1)Y
599!
| 6 lE23

s 1 E23

8 JS Ac LOLBE
+ 5 v -‘g\:oAsr

CLEAR

ADDR L

9
0 €210
/

Fe¢g/

£ 2.3

S1-2

Al7 L

@sa

RvYS

Aib L

BJs

AIJISL

Bvs

A l&4L

BRI

BR2

Ba3

gEFTIN

—eselN,

I K

Bvs

i tj

5P/

Ers

geei

Bus 4 13L

BP2

Bvs

A1zl

B )5

‘

Bvs

AJOL

BNZ

BYs A gq L

FIGURE

_PoweR
UP

BoeT Locic

The

POWER

caic

the

REBOOT

showm

ENABLE

Figure

switch

With

(S1=2)
this

cam

switch

used

open,

to
the

disable
clear

the

{Pput

flip=flop E29 will always ke low, preventimg it
from
evepr
being
om
power
restarts,
FAST ON tab TPl
{s provided to allow switch
2 to be remoted external
to the module,
Note that whem an exXternal
teh

used,

Extermnal

D g

Si=2

Boot

must

left

the

off

positionm,

Cireyit

The processor cam be extermally activated
TP2
1{mput,
as
shown {m FIGURE S5,
This
whiech them gemerates a BUS AC LQ L sigmal

by grourding the FAST ON tab
low input sets flio=Fflop E13
om the UMIBUS.,
Upom
seeinmg

this

FIGURE
EXTERNAL BOOT

IBUS

SIGNAL

ant{cipatimg

5
CIRCUIT

EVERY

PDP11

processor

will

real

power

foilure,

After

begim

the

EXTERNAL
causing

the

BOOT
dimrput
i{&
am B ms timeout,

end

the

this

timeocut,

Section

3,4,

Pouti
2

routine,

whigh
amd 26

{
)

the
onreshot
E~Z
input to flipwf!

flip=flop

releasina
the
BUS
AC
LO L lime and firing the
mert{iomed {n Sectijom 3,4,
The processor them 1s
new
PC
anmd
PSW from locatien 773024 and 773026
deseribed

down

BUS AC LO L at
locatiom 24(8)

released,
anmd the set

ore=shot

power

completing

processor will then wajt for the
release of
it will perform a power up seaquence through
Whem

EL13

300 ms onew
force
ecti
vely
re

Page 124

X2
K
===/

R'é

30K

¢ 3l

DCEY

"
/

]

L _ . ]

EXTERNAL

5“'.,

7P3

gms [Py

3|&13

PwR vP cLr
L

SN EXT.

SwileH

FIGURE
EXTERNAL

BooT

¢c/)RcvIT

BooT £w~AB.
L

fage

8@&(’._\"\

' 4

C Closuse

—= T

Bus AL Lo L

ONE /K0T

e—

TiMeout

5 me.e-s 9&.':%552 B & DC.QS-t
\

dons
Fouwre
ExtERNAL

G
BeoT

<t <
MG

sve

Page
1,6

Power

Transfer

Detectiom

Logic

FIGURE
TRANSFER

After

BUS

AC
as

segquence

LO L ard BUS DC
described
{m

DETECTION

LO
L
Seetion

have
3,4,

LOGIC

performed
the logic

their
power
uyp
showm im Fiaupre 7

ceunts the
ne
pulse

first two DATI transfers
om the UNIBUS amd gemepates
a
75
onm the CLR ADDR L lime,
The two UNIBUS tramsfers pePformed

will

obtain

ADDR

puUlse

Figure

BUS

3,7

mew

resulting

releasimg

bus

and

will

be
address

PSw
used
1ime

previously

to clear
BUS A29,

the
BUS

described,

The

ome shot
A1@, and

shPown in
A12 thry

E21
BUS

CLR

A17,

Poewer

UUp

Clear

The eireyit shown in Figure 8 is included er the
M93R1
te
2Auarantee
that specific storage elements on the module are cleared when power is
f{rat applied the PWR CLR | sigmal will be held Tow for
apprOximately
7@
ms after the +5VDC has returmed assuming the +5Y supply hags a pise
time of less tham 22ms,
The exset period of time for heldimg PYR
CLR
L. {8 @ function of the rise time of the +SVDC power supply,

POWER

FIGURE 8
UP CLEAR

LOGIC

[ K

Apse EwaB (1)A

~
D a4 (1)H
INAB

—e£19

476

/0@72 /4 A

s 5y

R)2

24
R(ko

CLR ADLK L

T
@)

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LOGIC

Page {5
3,8

Address

M63@!

Filgure

MO3@1,
withim

Address

Logic

Space

shows

the

complete

UNIBUS

address

The
purpose
of this circuitry {s
the
address
space
of
the
M9331

7650200(8)

= T6S777(8)),

773p24(8)amd
in

Detectiom

Sectiomns

773026(8)

3,4,

and

for

3,5,

and

the

recogmize

power

detection

te detect
7732d0(8)

the

circuit

Jogic

2mn

the

LUNIBUS addresses
= 773777(8)
and

specific

previously

addresses

described

R20 é
2K

+8v

—\ N\
sBue Al7

RUS A

L
=

L —O

————{}f—'—\

t— L)

£27

Bus AlsL ——— pop
L
wmsyy

Bus

E2®

AV~

Far

B
-

Bus ci L

+5v

E2LS

+5v

ENAB DATAH

E2T

ENAB

Bus A2 | —O Fle L‘

—

—C

Bvs al) v —<f Fre) l
fCO

Fig

+5v
i

—
El7

)

/6
JFC
)

— 765XXXL

Low Rom
ENABLE

)

| E25
E7

Bus Ae9L -—-—O';_T;\‘ i

pe Lo g

Si-/

. EIE

Bus Ato L —O

DATA
L

T xxX L
5

-—-—U_.___,/

Bus AB¢ L — E/g\
—}
Bug AL

ADEH

A -—(jE/g
A\

AT H

—()

BuS

Ad6
H

Ad4 H

Ap5L—1Q £18 )

AF3H

AJdLH

Bug Ad3L—C E/S\

—C

AWL —

£
—

Bus AgzlL ——C

E2%

4o
£19)

-0

76 EXXYL
—

o7
FlG, 9
ADDRESS

DEcCOoDER

—

__29}— ENAB Jump L

E26

e Rl
BuS AP7L T4

AF|H .

LOGIC

BUS

SSYN

MO3@81

Memory

Access

Constraimts

The eircuitry show in Figure 9 determimes
space
(s being accessed,
Upon recefving
amd

BUS

iimes

MSYN,

(BUS

Comditions
returming

the

Dv@a

which

BUS
i,

ROM

data

BUS

must

SSYN

are

Detectiom

position
XXX

Lew

ROM

Transfer
L is mot

Emable

met

amd

are

emabled

BUS

SSYN

before

follows:

the

ento

emablimg

addpress
address,
UNIBUS
data

the

emabled
the

202

ROM

later,

data

and

UNIBUS

address

the of L ROM ENABLE

765XXX

switeh Si= 1)

(depermdemt

or T73%XXX

where

redumrdant,

BUS

outruts

D15

whem the M9321
ROM
a recognized UNIBUS

beinmng performed
asserted,

MSYN

econmtrol

siqgral

DATI

has

operatiomn

beer

where

BUS

obtaimed,

Switeh

LOW ROM ENABLE switch (sl=1) shownm {im Figure
9
alleows
the
uSep
to
diseble
the
M93@]
detection
of UNIBUS addresses 765208 tru 765777,
These addresses wWould normally represent the lower 256
words
2%
the

MO3B!
is set
be{mg

memory
space,
Disablimg the detection of these addresses Siwm|
to OFF posi{itiem) becomes essemtial whem that
memory
space
s
uvsed
by
other
peripheral
devices
i{m the system,
FoP M93C1

modules

comntaining

pregram

features

lecations

ROM

76500G

Adcdress

Logie

showm

First

standard

DREC

will

elimimated

thru

765777,

pregrams,

users

should

disablimg

performs

note

M93Q1

what

addpress

Gemeration

the

lower

receives

half

the

nime

Figure

address

imputs

for

twe

the

M9321

functions,
ROM

memopy

(765XXXL, amnd A@i{H thru AGBH),
Seconrd It detects
the
UNIBUS
address
173024 amgd gemePrates the offset switeh emable sigmal
gSee Sectiom 3
ENAB

JUMP

Address

(Offset

Switeh

Banmk

As
previously mentiomed
precessoPr
obtaims
i{ts

im
Sectiom
3,4,
om
all
boots,
nmew
PC
from
Jecation
773024(8)

sWwitches,

the

the
30
imstead o

ocation 24(8),
When the M93Q@1 addpress detectiom legic (Section
3,8
deeodes
the
address 24(8), it emables (via ENABL JUMP L) the addp
offset switeh banmk (Figure 108) shown below,
The
conmtents
of
the
ROM

combimed

memory,

precessor

bootstrap
imciuded
ehrough

produce

the

routine)
1im
the

the

address

with

new

contents

startimg

im the
MO3A1
offset

for

the

address

M93d1
memory
switeh

the

CPU,

specified

This

mew

speecific

address

will

program

M93d1

pOint

the
(usally a

memory,
with
amy

Several
programs
Canm
b
ome being user sei@ectab

selection

Page

Exampley

M93@1 ROM address 773024 contaimg
ODffset Switch Bank comtainms
New

read

CPU

{73000
254
173254

raqe /9

|
D}—Bu
s D/57

Roea DIE H

RoM

D4 H

pvs DAL

F IGURE
ADDRESS

| o

Rom D13 K

}5’u| 5 D/31L

OFFSET

SwITCH

[

H
Rosm D2

BANK

Bus p/alL
|

Rom

DI/
H

o
Rom

— BUs
BU

DIl
L

DiloH

—— BUS Dlo L

Rom

DgaH

_} BUS Der9)

ENAB DATA H —
Rom 0pgL ———[

)

} BUS DasL

£/-3

+5v

—A\NN—

Rom Dp7L ———[
O\

—a_

RoM DgéL ——d

}-—Bus DoéL

5
SI-

Rom

085 L ———)

— BUS Do7L

—a__/
ROM

— BUS D@5l

D4l ——[

=0
-7

RoMm D@3
L ———(

Do—-—fius D@L

Lf_—l/VV——

o—+— Bus D@3L

—e
s/-§

ROM 0¢2-L O
\
—__/

o—— BUS bgal
ENARG DATAH

ReM

ENAB
,E/VAB JumP L

DATAL

ROM Dgg H

bdL

-——“"‘Oj

Do—-——Bus DFIL

—

Y— Bus

D;‘

3.1

The

ROM

heart

Page

shownm

Memory

the

M932{

the

S12

word

ROM

(Read

Omnly

Memory)

Figure
11,
It
is
composed
of
four
512
x
4 Bit Trimstate
ergamized imn a 512 x 16 bit configuration,
Al1] four units
share
same
address
J{imes
and
produce
{6=bit
PDP=li1
i{nstructions
execution by the processgsor,
A1l four ROM
impyts
W{l)

DATA

sigmals

MO391

outputs are
result im a

Figure

compatible

ROMS,

always
change

are

emabled,
so
im the UNIBUS

ermabled,

CONSULT

THE

For

ROM

chamge
im
limes whem

further

Aaddress
the ENAR

{mnformatiom

Specificatiomrs

Appemdi X,

M9301

army
deata

ROMS
the
for

showm

{imn

the

users

programmimg

that

program

their

own

PROMS

sghould

note

the

folleowing

comnstraints,

There

{s mo address or data output

tramslatiom

UNIBUS

address

theu

When codimg PROM patterns data bits D@1 thru DVB must
always
contain
the
inverse
of the date required to compengate feor
the extra imversion
logic
available
1mn
the
MG3@1
Offset
Switeh Circuitry,
|

locations

7730002(8)

required,

773776(8)

are

located

in
the Jower 256 words of PROM word space anmnd UNIBUS address
locatioms 765208(8) thru 765776(8) are residemt im the
wupper
256 words,

page 21
-L%ME’/
SEL %X L

’

ABY H

AL
M

or 42 rom D12H

4 D

B8
c

706 |5

A3 H

— Rom DI3H
o2

3 E

H
RIS
i

STAT'F 03 ..__/_‘52_{-“ R aopn D/q +

= £ D

APl

ke H TR - 04 "'—9""-*-?0‘\4 D;SH

H
ABB

‘

E;Z

AED
M

AP H

P e

{

mp s

657/@.-

—TE
5

=27

H
DI

Rowu

Rom p@EYH

O/ =5 Rot bl

& B A

l7le |5

[
;

5’5 H TR:; o422 —— Rom 2l H

|
|

] v E6

}

L5 Hrgz- 04 b-2— Rom DE7L
y)

6&‘7’@7‘5030_/_@_ Rom DPEL

2\E

SEREL

2lg B

ozl

Rom DOSL

__ rompttL
orb!Z

AP¢ G A

17 le |5

|
|

/3
=='e V.2V

4] —14

e
Bl
S

L
1% H +RT— 04»0—2——— Rort, TO3
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s
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1

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76 |5
X SEE PARTS LIST
'

FOR PART NO.

Page

3,11

M93a1

TERMINATOR

The termimator section of the M9321 comsists
of
four
resistor
pack
eircuits
each containing the required pull=up amd pulledown resSistoers
for preper UNIBUS termimation,
Since PDPii/24 amd PDP11/34
comMputers
incorperate
BUS
GRANT
pullmup
space has beem left omn the M93Q]
8llow

the

wuser

select

whether

resistors, TABLE 2 indicates
GRANT Jumpers installed,

Cautiorn

should

(PDPL1/@25,

11712,

taken

whemn

11/35,

resistors
on the proecessor modules,
for five Jumpers (W1 thpu
WS)
whieh

which

{mclude

versions

inserting

M9301{

modules

11/4Q)

computers,

UNIBUS

furthest

gquestiom; does not have BUS GRANT pull=ups
omn
through
W5
omn
the
M93Q@1, should be inseprted

pos{t{oned

the

end on

the

BUS

the

GRANT

M932{

the

=2ull=yp

have

various

BUS

PDP11

processor

the
CPU,
JjumMpers
or the M93@AL should

from

the

CPU,

inm

W|{
be

Page

VARIATION

bo@

M93@1

4,1

Overview

The

M9301

described

Bootstrap/Termimator

differemces

the

between

followimrg

each

presertly

comes

sections,

Table

five

varfatioms

summarfzes

the

variation,
MO3@A{
=@

«YA

=YB

wY(C

=YD

EXTERNAL BOOT SWITCH RESTART

YES

YFS

YES

POWER

YES

YFS

YES

(ROM)

YES

YFS

YES

FOR

YES

¢t 0

YES

N()

YES

hNA

YES

REBOOT

PROGRAMMERS

READ

ONLY

SOCKETS

ENABLE

CONSOLE
COMPUTER

MEMORY

SUPPLIED

(ROM/PROM)

BUS

GRANT

(Wi

THRU

PULL=UP

STANDARD

WITH

PROGRAMMABLE

TERMINATOR

RESISTER

W5)

SWITCH SELECTABLE
STANDARD

RESTART

DEC

BOOTING

BOOTSTRAPS

AND

MASSBUS

DEVICE

STANDARD DEC BOOTSTRAPS
PDP

ROOTS

11/7@ USER PROGRAM

DDCMP USER PRGRAM

|
«#

INDICATES

USER

SELECTABLE

TABLE 2
MO3@1

VARIATION

FEATURES

Page
ME&3@1

VYVariatiom

Usage

Gemneral
Nome of the

fellowing

centaining

terminator
MO3@L

MG3@1

Can

M9321

UNIBUS

position
=

variations

repeater,

the

used

any

computer

PDP11l

program

available

Used

most

extended

The

wusep

M93Q{

Rom

PDP11/@4,
with

lemngth

machines

fumction

the

side

terminator,

will

unless

processor

length

compatiblie

all

emd

PDP11

havimg

CPlUs

the

that

Same

the

machimes

M9321i=YA

PDP11/24,

PDP11/7@

M3@{

FoPr

use

only

MG3@1

Can

used

{im

tekeny;

except

the

any

however,

the

machimes

at
processor,

the

(See

Program

that

BUS

GRANT

contaim
placed

imtemded

the

for

anm

other

pul]

emg

°2nd

uysep

34,

machine,

i{imsepting

the

Caution

should

M930!

some

should

placed

however,

rmot

but

eXtemded

will

If the processor im auestion
pull=up resisters on the CPU,

M9301

bootstrap

that

computers,
BUS
GRANT
on

im
o

machimes,

PDP1l
whem

and

system

space,

OEM

PDPI]l

inserted

accepts

defimes

MNote

which

1{s

repeater,

machimes

termimator,

M9321

Up resistors,
the M93421l=YA must be
the UNIBUS farthest from the CPU,

MO3Q)

inserted

end
of
Section

op,

the

the
UNIBUS
3,11),

does
mot
Jumpers “{

M93@1

furthest

PDPY{

have
thruy

should

from

the

The M93@i=0 has been created as a
unmiversal
bootstrap
device
which
allows
the
user
to proqram and install customized 512 x 4 kit ROMS,
This module version comes with four
16=pim
IC
(integrated
clrcuit)
gockets
Im
place
of
the
Roms
nmormally
I{mserted
on othep module
vers{omns,
For pinout
and
access
time
comstraints
en
Roms
used,

consult

the

Rem

patterns

bit

Rom

te
meet
the
gection 3,1@)

4,3

M93B3i=YA

Specificatiom
for

the

address

and

shown

M9301{=Q,

and

M93Q1{=YB

care

data

the

Appendix,

should

eoeutput

pirmrouts

Wher

takem

the

eoPfigurinmg
arrampde

meoedule.
B

them

(See

Versions

Two versions of the M93P{ have beem created for use in the PDP
{1/04,
and
34,
compyters,
One
version,
designated
M93@i=YA, 18 fop QEM
(origimal equipment
memufacturer)
use
and
the
other
degsignated
-

M93B{=YB

for

end

GO0»NO GO diagrostics
shown
{mn Table 3 and

users,

alomg
Table

with
4,

Both

umits

specific

contaim

sets

basic

CPU

bootstrap

ard

memory

programs

asg

Page

4,3,1

Physical

Differences

from

the

M9331=12

The emrly physical differemce between the MI3Qi=YA/M93Z1=YB modules and
s that specially programmed Tpri
described,
previously
M93@i=0
the

Stete 512 x 4 bit ROMs are inserted in the four locations occupied
{6=pin DIP

4,3,2

M930i=YA

the M93Q@1=0,

sockets

and

M93@1l=Yb

Table 5

is
a program

4,3,2,1

Basic

Program

memory map of

Memopry

the

Map

MI3@1=YA

and

and briefly liste the mature of each diagmostic test

TEST

OPERAND

This test executes all

basic
The
@,
mode
imstructions operateg

eperation
each

each

{imstructiom

~M93P]l=YB

modules

im the ROMS,

Diaanostics

CPU

SINGLE

TEST

simgle operand instructions

objective
also
it

instructiom,

the

correct

using

s to verify that all
cursory
a
provides

destimation

single Operand
the
2n
check

while ensuring that the CP!! decodes

manmner,

TEST | brimgs the test destimatiom register through its three passible
Each instruction opeprates on
megative, and positive,
zepo,
states?
the

contents

ome

will

Data

Data will

Data

arithmetic

operation,

wil)l

changed

sh{fts,

add

be umehanged,
{,e,s

clear

i{ndirect

via

but

operated

carry,

amd

unchanged

subtract

via

{m an

fndirect

operation,

1.€,y

direct

carpry,

upon,

already

incfement,

i,e,,

etc,

decrement,

clear,

wayss

four

be changed via a direct operation,

Data will

via

contaning

nmone=mod{fyimg

ZePfos,

{nStruction

(TEST),

Note that

modified

when operating upon data

sh{ft wil]
eperation,

mamner,

the state of the aporopriate comdition code,

the
of
out
move the "“C" bit into or
that
fnplies
correctly,
performed
when

eoerrectly by the previocus imstruction,

There are

the data

APrithmetic

This
destimationr,
the "C" bit Was set

nPo

checks

the

However, a check is made
date integrity prior to the end of the test,
implies
correct result
A
manipulation,
data
on end the result of the
in
Jata
the
manipulate)
not
did
(or,
that all imstructions manipulated
the correct way,

progPram
TEST

2 =

loop unti]
DOUBLE

1f the data is inmcorrect,
the machine

OPERAND,

halted,

ALL SOURCE

MODES,

the program will

hafRg {n a

Page

DESTINATION MODE @
This
test
verifies
all
double
operand
gemeral
and
logical
imstruction==gach
1n one 0f the sevemn modes (excludes mode @),
Thus;
two operations are checked the correct decoding of each double operand

imstruction,
source

and

the

correct

operatiom

each

acddressirg

mede

fop

the

operand,

Each {mstruction on the test must operate correctly im order
¢0pr
¢the
mext {nstruction to operate,
This imtep=depermdence is carried thpeough
to the Jast {mstructioen (bit test) where,
only
throuagh
the
Coerrect
execytion of @l1] previous instructions is a data field examined for a
specific bit configuration,
Thus, eaeh instructiom prior to the
last
serves

Twe

set

checks

the

GO=NO

(modificatiom)

comtaimns

comntaimed

the

pointer

the

test

data,

on instruction operation are made im TEST 2,
0One echeck,
a8
condition,
is made followimg the compare instructiom, while
is made as the last imstruction 1n the test seguence,

brameh
on
the secomnd

Simce

uUp

test

must

data),

The

withim

the

resides

data

ROM,

performed
and

ROM

memory,

1{n

destimation

addressimg

all

comstanmnts

Those

instructions

that

paritecipate

Those

finstructions

that

manipulate

the

address

regi{ster

the

data

mask

generate

for

the

fimal

expected

bit

mamipulation

nmode

used

It {8 importamt te note that two different types
of
execUute correctly in order for this test to opeate}l

data
by

test

(register
2,

operatiom®

computimg

bit

TEST

are

must

the

fimal

imstruyction,

data

within

the

pattern,

Detection of amn error within this test results im a program loon,
TEST

JUMP

TEST

MODES

AND

The purpose of
imgtPUCtion,

expected

this test 1s to emsure correct operation
of
¢the
Jume
This
test
s constructed such that omly a JumTMp to the
imstruction will provide the correct
poinmnter
for
the
mext

instruction,

There are two possible failure modes that can oceur inm this testy

The
may

The Jump addressimg
e¢ircuitry
will
transfer of execution to am {mcorrect
non=existent memory,

The Jump addressing circuitry will
as

cause

the

CPU

loop,

malfunction

causimg
seay2pnce

in such

a
orp

way

latter case is a logical erropr imdicator,
The
former,
hoOwever,
manrnifest
{tself ags am aftermthe fact error,
For example, {f the

Jump causes
the

malfumctiom
imstructiom

control

{ntermdependent

given

{mstruction

other

routines

seaquences

would

withim

the

probably

M93@1,

Cause

“age

failure to eventually occur,
Im any case, the
failimng
of
the
Jump
imstruction
wWil)
eventually
cause
am out of seaquence opr "{llogical
evemt" to occur,
This imn
itself
{8
a
meaninpgful
irndicater
of
a
majlfunctiomning

CPU,

Thies test contains a JUMP, MODE 2,
This {instruction is mot comnatible
across
the
PDP=1]
Vline,
However,
1t
will operate oen anv “DP=11,
withim thig test, dyue to the unmique
programming
o0f
the
{nAStPyuctionm

withim
TEST 3,
Before {llustratimg the operationr, it is impartanmt
understamd the difference of the JUMP MODE 2 betweemn machines,

(RY+)
¢the
vregister (R) is {mcremented
Jump,
Om the PDP=i11/7d4d2 and {1/35,
(R)
amd imeremented by 2 after execution of

the

PDP={1/20,

by 2 prior
1is used as
the Jump,

order

the

11/25,

avoid

this

and

11/1@

processor,

imcompatability,

with (R) poimting back om the Jump itself,
precessors, execution
of
the
imstruction
imeremented
te
poimt
to
the
followimg
comtimpuirg a mnormal execution sequence,

for

Jump

the

Jump

Mode

(JMP

to execution of the
the
Jump
Address

(R)+

prodrammed

Onm 1i1/220, 11/235, and 11/10
woulod
cause
(RY
to
be
imstruction,
effectively

On the PDP=1{/40 anmd 11/35 processors, the uyse of the initial value of
(R)
will
cause
the Jump to "Joop" back on ftself,
However, Correct
next
the
to
point
operation of the avuto=ircrement will move (R) to
imstruction
following
the
imitial
Jump,
The
Jump
will
¢then be
execUted

agaim,

imstructionm

TEST

This

test

T8T,

However,

SINGLE

TST

OPEAND,

focuses

(register
The

most

TSTB

then

a special

The

deferred)

destination

NON=MODIFYING,

mromemod{ fying operation,

inseruction,

the

address

will

the

pPext

instruction,

the

sequence,

TSTE
amd

programmed

significamt

byte

one

case

TEST

single

orerand

tests

the byte

will

(register

eperate

armd

TEST

the CPU execution

also

{nmnstructiomn

Mode

unigue

BYTE

zero

date

which

operation

executed

deferred,

(mot

flow since

has

auto

mnegative)

{is a

this

‘ode

incremeft]),

negative

least

value

siamificant

bytea

order for this test to operate properly, the TSTB om the LSB
must,
firet,
be
able to access the evem addressed |.SB, them set the prooer
cemndition codes,
The TSTB i{s them re=executed with the auto=inCrement
facility,
After the avutoeincrement, the addressing register should
pointing to the MSB of the test data,
Another
TSTB
1is
executed

what
set

should be

this

the MSB,

The

"N"

bit

the condition codes

be
on

should be

operation,

Correct execution of the last TSTB

implies

that

the

auto=imcrement

recognized
that
a
byte
operation
was
reauest,
therebv
only
ipcrementing the address {m the register by one, rather than twa,
I¢
the
correct
coenmdition
code
was
mot
set
by
¢the
associated TSTH
imstruction,

the

program

will

loop,

Page

TEST

These
(CMP)

DOUBLE=OPERAND,

are

two

amd

non=modifyimg

bit

source

NON=MODIFYING

test

modes

(BIT),

and

TEST

deuble=operand

These

and

two

imstructions

imstructionms

destimatiom

modes

the

operate

and

Compare

test

datsa

The BIT amd CMP
emnes
(177777),

{instructions will operate on data
comsisting
¢
all
Two
separate
fields
of
omes are used imn ordep to
Utilize the compare {mnstructioms, amd to provide a field large
ermough
to handle the auto=incrementing of the addressimng register,
Sinmce the
ecompare instruction is executed om
two
flelds
comtaiming
the
same
data,
The

the

BIT

expected

result

imstruction

another
field
eonditiom (Z),

Most

falilures

4,3,2,3

will

use

mask

arqument

all

ones,

The

expected

result

{nstruction

loop,

will

Display

true

ome

"Z"

Routime

bit,

The

imdiceatimg

equalitv,

all

pregister

onmnes

1is

display

Aagainmst

mop=zero

Poutine

primnts
out the octal contents of the CPU registers RO, R4, SP amd old
PC on the comnsole termimal,
This
sequence
will
be
followed
by
a
prompt character (%) on the next linme,

Example of

a typical

printout,

XAXXAXX

XXX XXX

XXAX XA

XXXXXX

Prompt

Character

signifies

Ré

Where

Whenever there {8 a pawér Jp Poutime opr the
released
time will

on
be

octal

the

4,3,2,5

Memory

6 = DOUBLE

rumn

OLD

and

showm

Modifyimg

OPERAND,

three

imnstructions

the

string

BOOT

SYITCH

that

diaghestics

CPU

the PC At
RS
ape

{s eperatimg,

operate

BYTE TEST

verify
|In

the

that

byte

the

mode,

doub\enbmefiand,

TEST

containrs

subetestst

Test

source mode 2,

Test

souce

mode

1is

this
them

Diagrostics

MODIFYING,

will

example,

imdicates

the processor

The obJeetive of this test

medifyimg

(@=7),

PDPi1/24
anmd PDP{1/34 machimes,
stored im RS,
The
conternts
of

The prohpting character
have been

number

Program Counter

printed

TEST

0ld PC

(Stack
Poimter)

destimation mode
destimatiomn

mode

1,
2,

odd amd even bvtes,

Page

3¢

Test

source

mode

destimation

The move byte (MOVB), bit clear
are
ysed
wWithin
TEST
6
to
deuble=operand functions,

Since

modifyimg

destimation
destimnation
SB@ 1s uUused

Note
both

instructions

respectively,

caused
to
is modified
7

The

JSR

Thus,

is a
are

the

be all zeroes
imdependentiy

JSR

byte (BICB),
verify
the

are

umder

test,

for
the
test
data,
TEST
address,
Later,
in TEST 7 and
as the first available storage

that, simce TEST 6
508(8)
and
581

TEST

mode

byte
used
word

test,
for
of

evenm

byte,

and bit set
opeatiom of

byte
(BISB)
the modifying

memory

must

use”d

4 uses locatiom S507(") as a
the Memory
Test,
Incation
for the stack,

location SWa(B)
the
bytes test

data

S2?

add

and all omes throughout
of the other,

implies
(evem and

and

the

evenm

that
odd,

bytes

are

Facth

byte

wutilizes

the

test,

TEST

the

first

gtack,
The Jump
After the JSR is

test

the

GO=NQ

seauence

that

Subroutine command (JSR {s executed in modes
executed, the subroutine
which
was
given

1| amd 6,
c¢ontrol,

Wwill examime the stack to ensure that the correct data was placed in ¢t
correct stack loecation (5@2(B)),
The routime will
also
emsur®
that
the
Jime
back
register
poinmts
to the correct address,
APy ePrors
detected im this test will
result imn a Halt,

TEST

MEMORY

Although
date

for

this

test

pattermns

MOS,

Before

appropriate

TEST

the

MOS

This test
ar{se

used

the

{ntemded
are

details

discuss

the

technology,

is
the

test

designed

the

both

core

amnd

exhibit

the

most

test

are

assumptions

MOS

memories,

taxinmng

described,

placed

upon

the

9peration

Wwould

feailure

modes

fntended to check

for two

types

problems

that

may

memoPry,

Solid

Element

Addressing

Sense

Amp

Malfumctions

fallures,

extermal

the

chip,

The gimplest failure to detect is a solid read or write problem,
If a
cell
fails
to
hold
the
appropriate
date, it is expected that the
Memery Test will easily detect this problem,
Imn addition, the ©rogram
attempts
to
saturate a chip im such a way as to cause marginal sense

amp

operatiom

sepse

amplifier,

MOS

sectiomr

storage

with,

manifest

The

data,

elements,

The

first

extermal

addressimg

{in

Each

loss

pick=up

the memory consists of

bit

objective

all

them
floated through the
and the test repeated,
Fer

ftself

chip used

zeroes
chip,

failures,

section

and
At

¢the

oene

the

tied

program

"1"

emd,

1is

bit,
the

assumed

a 64

that

This

data

uneXpected

matrix

common

saturate

"{"

bit

the

1is

compleTented,

two

oPF

Page

locations

likely

are

that

selected

both

te
writimg
amy
that there was no
will
result {n @&

the

helt,

locatioms

same

assume

time,

the

write

occurs,

correct

and

state,

Thus,

test
data, the backgroumd data is cheeked
crosstalk betweemr amy two locations,
All
program halt as do failures in tests & and

expected

switch
causimng
Address),
amd PC

the

wil)l

that

the

operatop

will

(Expected

Data),

(PC

indicating

memory

failure)

Data),
be

prier

te ermsure
failures

depress

(Received

After

the

BQOOT

(*ail%flg

displayed,

NOTE

I1f

the

expected

same,

intermittent
(1,e,

the

received

highly

failure

timing

reason

amd

opPr

can

Thus,

bpbeem

problem),

The

amd

recefved

data

be
i{dentical
i{s
program
re=reads
the
after
the
initial

detected,

are

that

has

margim

expected

data

probable

detected

that
the
test
failing
address
POR=CcOmMpare
i8S

failure

CPU

speed

detetedy,

amd imdicated by the reading
of
the
fafjling
address
omn
a
sinmgle
reference (Pot at speed) operation,

4,3,2,4
MG3Bi{=YB

MG3@1=YA
these

Bootstrap
Programs
Supported
by
the
MO3AL=YA
= Peripheral
devices
whose
bootstraps are supported by
anmd M93Q{=YB are listed im TABLE 3
anmd
TABLE
4,
Each

bootstraps

compatible

with

standard

DEC

hoots

amd

opelate

and
the

of
as

ol lows,

,3,2,4,1
RX11 DISKETTE = [oads
data
frem track ome, sector ome
8t
it

locatiomn @,
Once loaded
comtaims 240, operatiorm

locatioen @,
rpestarted,
halted

the comtents of location @ is
1s tramsferred to the routime

I+
Jlocatiom
Restarts
will

does
occur

not
2080

contaim
240,
times
before

checked,
beginminmg

the
boot
the machime

TI¢
in

s
is

automatically,

4,3,2,8,2

TA11 CASSETTE = This bootstrap Is idemtical to that n?

RX{{
except
second block,

4,3,2,4,3

tape

the first 64 words
(20¢
bvtes)
of
imnte memory location @ =177 beadinnming

f{mto

that

PC1{

the

data

PAPER

upper

TAPE

losded
'

READER

memory

from

the

cassette

beginmnnimg

Loads

Absolute

Loader

Jlocations

XXXT7H6

XXAXTT7T7

<¢the

the

formatted

(XXX

dependent on memory
sjze),
Once
Joadimg
1is
completed,
the
boot
transfers
operation
to
a
routime begimning at locationm XX¥752,
In
gsystems comtaimning am MI93Q1l=YA which {s set up mot to Pum
diagrestics

Page

TEST

thru

4,3,2,4,4
data from

TEST

S5,

= DISKS
the disk

XXX

will

record

locations

@17

nmot

the

upper

(excludimg RX11)
= Load (020@
into memory locations R=1776,

4,3,2,4,5
MAGTAPE = TM{]
size)
from
the
magtape

second

become

(200@

bytes

Loads second
{nto
memory

maximym

part

words

(2008

memory,

hytes)

record
(1200
bytes
maximum
locatiom A=777,
TJUl6 = Load

size)

from

magtape

1into®

memory

@=1777,

4,3,2,4,6
CONSOLE EMULATOR = When this routine is used
Wwith
the
Userfs
terminal, funmnctiomrs quite similar to
the programmer®s console of traditional
PDPI{
family

imn comjunction
those faumnd on
computers
are

generated,

as
shown
{n
the
summary below,
The descriptinn of the
operatiomn that
follows
assumes
that
¢the
user’s
MI93081
module
1is
econfigurated
to
enmter
the
<comsole
emulater
routime
(DIP
switch
settings for emulator are shown in TABLE(3) om POWER
UP
or
whemever
the BOOT switch {s depressed,
A

LOAD

SUMMARY

This
the

fumctionm

THE

CONSQLE

loads

the

EMULATOR

address

FUNCTIONS

manipulated

EXAMINE

Allows the
operator
to
examine
the
contents
address that was loaded and or deposited,

DEPQSIT

Allows

the

loaded

amd/or

START

ROOT

Comsole

The

operator

write

{mrto

Allows

the

bootimg

two

character

Emulator

QOperation

comrsole

emulator

the

address

the

that

was

examimed

Iniftializes
the
system
and
program at the address ]oaded
|

code

allows

and

the

starts

specified

unit

wuser

execution

device

perform

the

Simplified

Operator®s

Flow

Chart

typirg

mumber,

the

Joad,

deposit,
start,
and hoot operations by typimg inm eapepropriate
the kevybeard,
The combimation of the comsole emulator routin®
keyboard will be referred to as "The Console Emulator',

scuUssion

inmto

system

exXamime,
Code on
Apd the

Page

Intreduction
The

simplified

operator’s

flow

chart

(whieh
at thi{s

wil)l be referred to as the
point {n the text, to give

comnsole

emulator

the

coensole

emulator

routine

Flow Chart) 1s oresenmnted
a urified plcture of the

routinme,

Detalled discussions of each aspect of
Sections

the

Operator®s
the reader

following

paragraphs,

the

chart

are

presented

Symbols
Rectamgle

Reetarmgles
machimne,

indicate
There

automatic
only

omre

operations

emtrance

amd

whieh
orme

are

exit

performed
on

the

rectanaie,

Diamond

A diamond imdicates am automatic operation which cam
take
elther
of
two
paths
depending on how the question stated within the dlamond is
answered,

Cirecle

A e{rcle Inrdicates
tvyping of keys,

operator

actiorm,

and

the

movimg of

switch

¢the

SIMPLIFIED OPERATOR'S FLOWCHART OF THE CONSOLE EMULATOR ROUTINE

(FOR STANDARD M9301 CONFIGURATIONS)

RETURN OF

AC POWER

1. THE ROUTINE IS ENTERED ON POWER UP OR WHEN THE BOOT SWITCH

IS DEPRESSED (IN STANDARD M9301 CONFIGURATIONS) OR UPON THE
RETURN OF AC POWER (AFTER AN INTERRUPTION OF AC POWER)

TES BASIC CPU OPERATION o e
2. A DIAGNOSTIC LOCATED ON THE M9301 TESTS

3. IF THE DIAGNOSTIC IS PASSED, THE SYSTEM TERMINAL WILL PRINT

WAIT FOR
KEYBOARD INPUT

5. THE OPERATOR ENTERS A CODE (DESCRIBED IN THIS SECTION)

WHICH WILL LOAD AN ADDRESS OR EXAMINE (A PREVIOUSLY LOADED
START (AT A PREVIOUSLY LOADED ADDRESS) OR BOOT A SELECTED

ERROR

PRINT R, R4, SP,

4. THE SYSTEM IS NOW WAITING FOR THE OPERATOR TO ENTER e e e e e e e
INFORMATION FROM THE KEYBOARD

ADDRESS) OR DEPOSIT (INTO A PREVIOUSLY LOADED ADDRESS), OR

LOOP ON

— —— — — - owpprc$

OUT FOUR, SIX DIGIT NUMBERS

DIAGNOSTIC

INPUT

—e — — — —

KEYS

PERIPHERAL

VALID
COMBINATION

6. THE FIRST TWO INPUT CHARACTERS ARE VERIFIED AS BEING A o
KNOWN COMBINATION

YES
7. IF THE KEY COMBINATION INDICATED A START, THE START WILL BE
IMPLEMENTED NOW, AT THE PREVIOUSLY LOADED ADDRESS. NOTE THAT ~ — — — — —
START WILL EXIT FROM THIS ROUTINE; TO ENTER AGAIN, THE OPERATOR

START

EXIT FROM
CONSOLE
EMULATOR

START
PROGRAM

YES

MUST BOOT
NO

8. IF THE KEY COMBINATION WAS AN EXAMINE, THE PREVIOUSLY LOADED — e o e e —
ADDRESS, WITH ITS CONTENTS WILL BE PRINTED ON THE SYSTEM

EXAM.

YES

SUCCESSIVE
EXAM.

YES

INCREMENT
ADDRESS

ADDRESS AND
CONTENTS

TERMINAL

GO TO:

EMULATOR JUMPS TO LOAD OR DEPCSIT OR BOOT

LOAD

SEQUENCE
10. SEQUENCE 1S

ENTERED

DEPOSIT

SEQUENCE
SEQUENCE IS

ENTERED

LOAD OR DEPOSIT OR BOOT

BOOT

SEQUENCE
SEQUENCE IS

ENTERED

—_— — — — — — =~

LOAD

"DEPOSIT

DATA TO BE DEPOSITED

UNIT NUMBER IS

MOST SIGNIFICANT

IS ENTERED, MOST

ENTERED, DEFAULT

DIGIT IS FIRST

SIGNIFICANT DIGIT

NUMBER IS ZERO

UNIT SELECT

DEPOSITED

LOADED

BOOT

DATA TO BE

ADDRESS TO BE

1" . ADDRESS IS ENTERED

9. |F THE CODE WAS NOT AN EXAMINE OR START, THE CONSOLE

NO.

FIRST

12. A CHECK IS MADE TO INSURE THAT THE NUMBER WHICH WAS ENTERED

WAS AN OCTAL NUMBER 0-7; IF IT ISN'T, A $ IS PRINTED SIGNIFYING AN ~ — T~ — —

OCTAL

NUMBER

OCTAL

NUMBER

ERROR.

ENTERING (CR)

SIGNIFIES THE END
OF THE LOAD
SEQUENCE

TEST TO SEE IF THE

COMBINATION INPUT,
IMMEDIATELY PRECEDING THIS ONE

ENTERING (CR)

SIGNIFIES THAT THE
OPERATOR WISHES TO0

IF PREVIOUS OPERA-

PRIOR TO BOOTING, A

INTO AN INTERNAL

TION WAS A DEPOSIT,

MEMORY DIAGNOSTIC

ADDRESS WILL

IS RUN; IF IT FAILS,

PRINTED SIGNIFYING

INCREMENT

RUN LIGHT REMAINS

14 . ADDRESS IS LOADED

b —— —

BOOT NOW

WAS A DEPOSIT

SYSTEM IS READY

ON AND PERIPHERAL

FOR NEXT KEYBOARD

1S NOT BOOTED

ADDRESS
b

——

—

LOADED

INCREMENT
ADDRESS

MEMORY
DIAGNOSTIC

4.
“

PASSED

INPUT

IF MEMORY DIAGNOSTIC

(CR) INDICATES THAT
THE OPERATOR WISHES

PASSED, THE DEVICE IS

TO DEPOSIT - NOW

MOW BOOTED

DATA IS DEPOSITED

MACHINE EXITS FROM

FOLLOWED BY A $

THE CONSOLE

PRINTOUT, SIGNIFYING
THE SYSTEM IS READY

EMULATOR; TO RE-

FOR THE NEXT KEY-

MUST DEPRESS THE

BOARD INPUT

BOOT/INIT SWITCH

ENTER THE OPERATOR

—

—_——_—————_———

*CR = CARRIAGE RETURN KEY

DATA

DEPOSITED

¢ 2684

13.

EXIT FROM

CONSOLE

EMULATOR

11 - 3283

Page

CR 18 the symbol for the carriage néturn key,

Usimg the Comsgole Emu1ator
After

The

Orce the system has been powered uUp or booted,

have

beem

printed,

the

console

emulator

amd R@,

routinme

can

R4,

SP,

used,

PC and

Keyboard Inmpyt Symbo1§
The

discussiomn

keyboard

input

Space Bar

(SB)

Carriage Return Key 3

'CCRJi

Amy

Number

(Octal
Keyboard

format

Imput

Load

Examine

FUNCTION

KEYBOARD

Lead

Address

deposit

Deposit

(SB)

Start

(SR)

Input

Keys

118

typed

Character,

significamt

that

Conversely,

start,

A1l

(X)

represent

themselves

Character

with

the

(X)

(x)

(X)

(CR)

|
(X)

(X)

’
(X)

(CR)

will

the

most

sianmificant

the last character
that is typed
is the least
.

Zeros

Whem am address
be omitted when

Examp!e

character,

symbo)s3

STROKES

(X)

E (SB)

The finst.characfer

Leading

¢(SBY

Examine

Signrificance

following

(X)

keys
showmn
{n the following discussion
exception
of those in paremthesis,

Order

the

Number)key
Formatt

uses

Usimg

or data
loading

the

Agssume

Load,

that

word contains leading zeros, these
the address or depositing the data,

Exemime,
user

Deposit,

wishes

to}

amd

Start

zepos

Fumctionps

can

Page

power

Turm

Load

address

Examine

locatiom

72897

Deposit

777

locationm

Examine location 709

&y,

Start

740

into

TERMINAL

TURNS

POWER

L(SB)

702

(CR)

E(SB)

D(SB)

XXXXXX
5

XXXXXX

000700 XXXXXX

777

E(SB)

00a7R2

S(CR)

00777

0Omly

The console emylator
addresses

Succegesive

XXXXXX

L7009

5 E
777(CR)

DISPLAY

Addresses

Aumbered

7002

722

locatiom

USER

Evemn

routine

will

operations

are

must

always

Pot

work with

odd

used,

addresses,

Fven

(perations

Examine

Successiyve

examine

permitted,

The

address

J|oaded

for
the first examine only,
Successive examimes cause the a<ddress to
imcrement amd will display
consecutive
addresses
along
with
their
|

contents,

Example of Successive Examime Operation

Examime Addresses 500 - S@b
Operator INPUT

L(SB 508 CR
ECSB)

Termimal

DISPLAY

L. 54@
$E

200500

XXXXXX

Page
E(SB)

200502

XXXXXX

E(SB)

20@584

XXXXXX

ECSB)

PA@S26

XXXXXX

Deposit
Suecessive
deposit
operations
are
identiecal to that used with examine,

Example

Succegsive

Deposit

1{into

Location

500

1{nto

Locatjom

504

inmte

Deposit

Terminal

L(SB

S@@8

30 60

p(sB)

D(SB)

Deposit

Examine

every

the

last

Alternate

Lead address

deposit

50@,

data

Input

L(SB)

S@@

D(SB)

1@a@

(CR)
(CR)

E(SB)

2e@@ (CR)

E(SB)
D(SB)

E(SB)

not

which

Deposit

deposit

1§

the

{mcrement the
was

deposfited,

(CR)

address,

Examine

QOperations

following

mumbers

Term{mal

Display

$L. 5090
$D

Leaen

@0QS5S00

@ol@ea

$D 20020
SE pRa5e@

5420

Display

Operations

1000,2009,5428,

Operator

D(SB)

508

D(SB) éQ CR

This mode of operation will

Example

procedyre

Locatiomn 5@2

Input

comntaim

The

Operations

Operator

Altermate

Will

permitted,

Q02000

5420

$E QA@5¢0

@As420

with

The
|

examines

Addpress

after
-

Page

Altermate

I1f

Examine

examine

alternately

Deposit

Operatioms

first

instruction

the

followed

imcremented,
deposited,
exception of

deposits

amd

after

and the address will
(The
above
examele

contain
apolies

the

and

order

examine

examines,

load
the

seqguence,
address

3nmd

will

not

the
last
data
which
to this operation, with

deposit,

the

end

result

s
be

was
the
the

same)

Limits

Operation

The M9301 comsole emulator routine cam direct]ly manipulate
28K
of memory and the UK I/0 page,
See section S5, for an
of techniaues reauired to access addresses abhove the lower

Booting

Once

From

the

coemimng
lead a

Comsole

The

Keyboard

symbol

has

beer

Boot

Find the
Table 4,

Load papertape,
be

booted

Verify

{if

magtace,

disc,

<that

the

({if

If there 1s more than one unit
the
unit
npPumber to be booted
default

Type

(CR),

Before

Bootinmg,.,

Always

Remember:

Ihe

machime

powep

peady

either Table 3
to be booted,

into the

peripkeral

number

this

code

will

indicators

siagnify

obtairmed

{mit{iates

from

of
(@

a
=

the

will

routine

mot

after

¢that

the

table,

givemn
peripheral,
type
7)
{if mo number {8 typed,

the

bhoot,

The medium (Paper tape, disc, magtape, cassette,
be placed in the peripheral to be booted prior te

emulator

Character

the

system

applicable),

two

etc,

peripheral

ready

Type

system is
selects,

reauired,

resporse

two character hoot commampd code om
that corresponds to the peripheral

peripheral

1in

Procedures

displaved

uUpP, or the boot switch beimng depressed, the
bootstrap from the device which the operator

Emulator

the
lower
exolapatien
28¥,

urder

the

bootimg,

The'program which 8 booted 1m must:$

cortrol

etc,)
must
booting,
the

¢comsole

Page

self

program
after

the

The

destrovyed,

which

uWsimg

console

Actyating
PUA,

startimg

the

a8llow

CONT

wuser

emulator

recalled,

switch

will

always

boot

contents

the

There

way

Was

the

aborted,

general

Some

funmctiom
or 3)

abort

the

pegisters

conmtimue

program

Joad

amother

prestartable

prograTM

(R2=R7)

wWith

are

being

wi{ll

the

»pogram

desigmed

restartable,

Exampie:

Bootimg

the

High

Console

Speed

Reader

Using

Emulator

An operator wishes to

Joad the CPU Diagrmrostic

computer

system

system,

The

has

high

for

speed

11/39

reader,

Procedures

Place

the

e e

Obtain

HALT/CONT

Actuatimg

(RP,

the

CONT

positiom,

$Sby?

Turning

by,

switel

R4,

system

the

SP,

power

boot,

anmd

will

printed

prior

Place the absolute loader paper tape (coded

Types

the

high

speed

Remove

locader

tape

absolute

case

this

program,
Move

HALT/CONT

the

$.)

leaderp ‘saction)

reader,

will

loader

loaded,

and

place

HALT

amd

Diagmostic,

& CPU

switch

amnd the

the

them

the

machife

Jeader

preader,

return

will

the

CONT,

The
diagnostic
will
be
1loaded
anmd
the machime will halt
(normal for this programming, momediagrostic
proarams
could
be

the

(CR)

The absoluyte
halt,

self

starting),

1f program

startimg

activate

the

Using the comsole emulator, deposjt

desired

functions

switeh,

the

thies

1{s

Software

mot

will

self

restart the

Switch

console

emulator

(a memory addpess)

See the diagrmnostic for the software
location and significanmce,)

switeh

BOOT/INIT

routime,

Into

locationm,

pegistep®s

actua)

Page

Example

Usimg
start

the
the

console
program

Booting

A user wishes to
Diagmostic which

Disc

emulator, load the
startimg
as described eaplier imn this

Usimrg

boot the
the yser

the

system?s
wamts to

Comsole

address,
section,

and

Emulator

RKi!
rum,

Disk,

switch

which

contaims

the

CPU

positiomn

armrg

Procedure?

Verify
the

the

write

HALT/CONT

Jock

switch

the

RKI]

CONT

peripheral

the

position,

The

user

R&dy,

RU,

3,
Uy

turmns
SP

orn

The

user

Whem

the

and

the

system

which

nmext

lime,

placed

the

power,

disk

RKAS

1oad

light

type

ins

The

are

ramdom

pack

imto

acpears,

system
binary

drive
the

terminmal
numbers,

displays
FA"1lowed

zero,

system

readv

booted,

user

The

This
and

CONSOLE
The

causes
the

the

(CR)

l1oading

execution

that

the

bootstrap

Poutime

into

imitiate

dialogue

the

effects

eterimg

emulator

routirne,

The program should identify ftself
(which won®t be discussed here),

and

EMULATOR

followimg

informationmn

discussion

{ncorrectly

will

the

describe

comsole

Symbols

Space

Bar

Carriage

Return

Key

Amy Octal

Number

(0 =

Nom=0Octal

Number

(Y)

(SB)

(CR)

7) Key
9)

keys

(X)
(9)

Represenmpts:
le

memory

routime,

AVl

Keys

(other

tham

mumerics

which

are

umrkmrown,

Qage

Keys which are kmownm but do mot cemsitute a valid code Imn the
comtext

whiech

thev

are

Refer to previous sections for
operating the console emulator

ESCAPE

entered,

a
discussion
routinme,

the

delete

user

correct

methed

ROUTE

I{f an entry has not beemn completed
amd
the
user
{mcorrect
or Unwanted character has beem enteped,

key,

try

This

again,

aectienm

will

void

the

emtire

realizes
that
depress the Pub

entry
‘

amd

allow

an
eut

the

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—
-

m——

—

——
e

———
" —
"

—

)

Dage

show

Note

the

that

program

entry

S{=12

4,3,3

1Imstallation

various

devices

are

umiversal

can

system

shown

adapted

4,3,3,1
cam
be

are

the

Power Up
emabled

((S1=2),

the

M93(1=YA

depenmdent

mext

user

Major

each

meet

and

the

M93Q1=YR

switch

entpry,

the

"ON"

switch

positions

location

173024(8)

which

switches

§51=3

Si={(0,

The

fymnction

remoted
MODULE.,

the

must

boot

amd

MI3Q@i=YR

requiremeTMts

considered

and

dyring

follows,

DIP

thry

thpry

for

generated

M93Pi=YA

= Automatic bootimg
using
the POWER UP

1{s

set

¢the

performed

the

processor

happems

the

REBOOT

will

the

obtaim

the

PC from memory
the switeh
is
its

the

switch

the FAST=0N
SHOULD
BE

poOwer
ups
ENAR switch

position,

new
Wwhen

address

ENABLE

to
am
exterpnal
switch
wusimg
THIS
EXTERNAL
SWITCH
CLOSURE

om all
RERODT

"OFF"

processor
will
power
up
normally
obtainirg
a
locatien 2d(8) and a mew PSKk frem location 26(B),
set

Silel!

the

variety

that

respectively,

settimgs

must

which

module,

factors

Reboot Emable
or
disabled

this

Addresses

bootstrap/termimator

comfiqurations,

instaliation

for

are

module,

M9301

the

flows

points

Figure

and

and M93@1=YE = Figure

M93Q01=YA

Program Flow of

4,3,2,5

mew

BOOT

freom

SELECT

(S1=2)

c¢cam

tabs or the M930{
MADE
TN
GROUND

(ENABLING
BQOQOT) USING FAST ON tab TP3 as a ground returm,
Im the PDP
i1/@4, AND 34, when MOS memory
{s
present
with
battery
backup,
a
battery
status
f{ndication
sigral
s generated by the power Supply,
This sigmal should be attached to the POWER UP RERQOCT ENAB {mpyt (TP2)
orn the M93@1l,
If this status siamal qoes low, the contenrts of the M(DS
memory

gtorage

boot

¢he

longer

device,

powePr

up,

battery

automatically

address

4,3,3,2
range

LOW

thry

space

the

756777,

high

(logic

power

up,

and

This

occupied

thry

writtem

"1"),

some

memory

imto

memory,

the

M9321

executior

mass

fOrces

will

begip

DIP

both

switch

from
the

the

S1=1)

whem

respondimg

set

¥M938i=YA

DISKETTE

(RX11)

the

and

not

the

amd

the

UNIRUS

"OFF"

Aaddpress

M93@i=YR,

CASSETTE

this

(TAL1)

PBRoot Switch Selection = To select which device
power=m=uUps and extermal boot emables, eight DIP

Si=112)

from

the

24,

M93Q1
0Om

usually

status

bootstraps,

4,3,3,3
PUR
on

reloaded,
the

data

location

Ermable

myust

semsimg

new

inmnput
on

prevents

76500

address

status
boot

ROM

and

M93@2{,

allowing

specified

positiom

valid

The

are

provided

both

the

M932]=YA

amd

boot
will
be
switches (Si=3

M93@i=YB,

Actual

ON=0FF
selection
TABLE 3,

each

switeh

for

the

various

4,3,3,4
External Boot Switeh = A
device
car
uUsimg
the
EXTERNAL
BQOOT imput on FAST ON tab
brouaht
to

will
amd

ground,

perform

POWER

deactivate
thus

ground

bol

BUS

the

boot

returm

for

select

the

FAIL,

will

Uporm

imitiating

switches,

extermal

boot

FAST

POWER
ON

tab

shewm

be
exterrmally
booted
TPi1,
If this iPput is

activated

preturnimg
to

are

causing

logic

the

"1",

sequence

TP3

should

switch,

nrocessor
this

im
be

the

used

impput

C(CPU

MO3@A1=YC

This versiomn
If
comtains
booting from
booting imto

Phygical
The

of the M9321 has been created specifically for the 11/78G,
basic
CPU,
cache
and Memory diagmostics in arditom to
one of 9 devices,
It also
inmcludes
the
capability
of
other than the lowest bhank of physical memory,

Differences

MO93Q1=YC

used

resister

the

11/7@
U,4,1

for

Bisie

by
Bus

the
Grant

Diagnostics

Memory

Fig,

from

variation

information

See

BUS

devices

Page

(14)

Map

MO3@{
uses

11/7@,
lines

Tri=State
The

the

module

Unibus,

ROM*3

which

containm

also

reauires

oyll=yp

Page

MEMORY

CACHE

DIAGNOSTICS

BOOTSTRAP
PROGRAM

17773060

CPU

AND

MEMORY

DIAGNAOSTICS

17765020

FIGURE

MO3A1l=Y(C

PROGRAM

MEMQRY

MAP

Page

oo
The

Germeral

most

from

portion

the

the
stack
reauested,

verify
agafn

that
to

the

program

the

will

registers,

the

PDPal]

address

the

"hits"

imsure

cache

occur

that

the

used

off,
cache

the

addressing

repertoire,

After

maim

memory

will

memory

will

working

"boot"

maim

properly

CPU,

medes,

and

themn

get

7, check and turm
map,
and
check

<cache

them

basie

will

157776,

the

properly,

the

test

al]

pointer to kermnel Despace P,A,R,
memory management anmd the umibus
with

memory

branches,

fmstructioms

virtual

ver{fied,

Description

diaagnostic

imeludings

memory

omn, if
memory

hag

tested

throuahout

See

Diagnostic

fig,

TEST

Test

been

Scanmnec
the

28K

operation,

If one of the cache memory tests fails, the orerator
cam
attempt
"boot"
the system anyway by pressing "Contimue",
This wil) caugse
program to ferce "Misses" {m both groups of the cache before 2oimg
the bootstrap section of the program,

4, 4,3

to
the
to

Descriptions

THIS

TEST

THE REGISTERS
ENTERED
AND

VERIFIES
THE

UNCONDITIONA|

AND CONDITIOMN CODES
THEY
SHOULD REMAIN

BRANCH

ARE ALL UNDEFINED
THAT wAY UPQN THE

WHEN THIS TEST
IS
COMPLETIOM UF THIS

TEST,

TESTY2

TEST

CLR,

MODE

g%,

AND

HBMI",nBVS®,BHI",B8L08"

THE'REGISTERS AMND CONDITION CODES ARE ALL UNDEFINED WHEN THE THIS TEST

IS ENTERED,
AND ONLY THE

OPEN COMPLETION OF
"Z" FLOP=FLOP WILL

TESTY

TEST

UPON

ENTERING

THE

"DEC",

=141,

THIs
V=2

ARE?

R3s ? R4 = ? RS
YPON COMPLETION
N

THE
SP

REGISTERS
=

(77777

MODE

"a@a",

TEST

THE

AND

= 2 SP = UQQGEA
QF THIS TEST THE
=

AND

AFFECTED

THE

"SP"

(R6)

SHOULD

"BPL","BGE","BGT","BLE"

CONDITION

AND

RQ@

THIS TEST
BE SET,

CODES
=

CONDITION

TEST
|

ARES

ARE:

CODES

WILL

BES

ZERDQ

Page

TEST

TEST?2

TEST

THIS

TEST

TEST3
TEST4
TESTS
TEST®
TEST7
TESTI@

TEST
TEST
TEST
TEST
TEST
TEST

"DEC",
"ROR",

MODE "@", AND "BPL", "BEQ",BGE",BGT",BLE"
MODE "2", AND "BYC","BHIS",RHI",BNE"
"BHI", "BLT", AND "RLOS",
"BLE" AND "BGT"
REGISTER DATA PATH AND MODES "zn, w3n, mngn
"ROL","BCC", "“"BLT", AND MODE Ue

TEST12
TEST(3
TEST14

"ROR", "BIS", "ADDY, AND
"DECY" AND "BLOS", "BLT"
“"COM", "RIC", AND "BGT",

TEST1S
TEST16
TEST17
TEST20

TEST
TEST
TEST
TEST
TEST
TEST
TEST

ASH,

TEST21

TEST

TESTR3
TEST24

TEST
LOAD

TESTR22

VERIFIES

"CLR",

THE

MODE "@",

UNCONDITIONAL

TEST

BRANCH

AND "BMI®,BYS","BHI",BLOS"

"RLO",

Y3GE",
"ADCY, "CMP", WHRITW, AND "BNE",
"MOVYB®, ®gOB", “CLR", "TST" aND

MASR",

"BGE"

MRLE"
"BGT", "REQY
"BPL", "RNE"

MASL"

AND

SwAB

KERNEL

P,A,R,*S

AND LOAD KIPDR®S

"JSR", "RTS", "RTI", & "JMpHw
AND TURN ON MEMQORY MANAGEMENT

AND

THE

UNIRUS

MA®

TEST25
TEST MAIN MEMORY FROM VIRTUAL 1d2 TO 28K
BOOTSTRAP ENTRY POINT IS AT 17773222
CODE TO WAIT FOR TUL? TO COME ON L INE
THIS IS THE CODE 70 READ THE SWITCH REGISTER AND DECODE IT
THIS IS THE START.
QF THE TM11/TU1Q BOOT STRAP (MAGNETIC TAPE, T7'11)
THIS IS THE START OF THE TC11/TUube BOQT STRAP (DECTAPE, TC11=6G)
THIS IS THE START QF THE RK11/RK?5 BOOT ST RAP (DECPACK DISK CARTRIDGE

THIS

THE

START

THE

RP11/RPO3

THIS
THIS

IS
IS

THE
THE

START
START

OF
OF

THE
THE

COMMUN

RH7G/TUTE6

BQOT

THIS

37 RAP

THE

START

THE

RH7A/RP@A4

BQOT

ST RAP

THIS

THE

START

THE

RH7@/RS24

BOOT

ST RAP

THIS

IS
IS
IS

THE
THE
THE

START
START
START

QF
QF

THE
THE

COMMON

THIS
THIS

FUNCTION

CCDES

FOR

THE

STARTING

ADDRESS

MEMORY

TESTZ 6
TESTR
7

TEST
TEST

RH=73

CQODE

RX11/Rx21 BOOT
FOR 4 FUTURE

aLlL

THE

TABLE

TESTS

CACHE

DATA MEMORY
VIRTUAL 28K WITH CACHE

Fiaure

(15)

(DISK PACK,

RP11=")

(MAGNETIC TAPE SYSTEM,
(DISK PACK, RWPI4)

(FIXED

87 RAP (FLAPPY
DEVICE

DEVICES

ADDRESS

TABLE

DIAGNQSTIC

ST RAP

CODE

RESERVED

COMMAND AND STATUS REGISTER
FUNCTION POINTER TABLE

CACHE

BOOT

READ

HEAD

DISX,

DISK)

RWSQU)

Page

TEST4

TEST "ROR",

MODE "@",

UPON

N=1,Z = @, V = @, AND
THE REGISTERS ARE: R@ =

ENTERING

THIS

TEST

C = 0,
?, Rl =

THE

AND "BVC","BHIS",BHI","BNE",

S§P

CONDITION

REGISTERS

UPON

ENTERING

Ne0,

"BHi",
THIS

Z=09,

REGISTERS
=

UPON
N s
THE

TEST

UPON

ENTERING

Nst{,

WHEN

S§P

"BLE"

THIS

=1,V

THIS

AND

COMPLETION
Z

125252,
125252¢

TEST

THIS

OF
=

ARE
R1
RS

"RoOL",

TEST

@, Z =2 {,
REGISTERS

THE

BE3

THE

AND

WILL

BE:

WILL

BEs

THE

CONDITION
=

CODES

TEST.,

AND

THE
|

UNAFFECTED

DATA

THIS

PATH
THE

LEFT

"BCC",
ENTERED

125252,

ARE®

CONDITION CODES
BY

THE

TEST,

MODES

®gnw,

"3hn,

CODES

ARE?®

CONDITION

THE

2RBeoR,
125252,

= {1,
R2 = ?, Rl
= 977777@

AND

TEST

AND

CODES

CONDITION

ngo

CODES

ARES

FOLLOWSS

RE
SP

125252,
125252,

"BLT",
THE

AND

R3 = 125252
AND MAPLQQ2 =

MODE

CONDITION

V = @, AND C = @,
ARE: R@ = 125252,

R3S = {25252, R4
MAPLPO = {25252

ARES

"BGT"

ENTERED

CORES

CONDITION

TEST

THIS

ALL

TEST

?, Rl = ?
= Q77777

ARE

THIS

R@ =
2 SP

REGISTERS

TESTi@
WHEN

WILL

@77777

TEST

=14,

AREs
RS 8

REGISTERS
=
=

CODES

ARES

CONDITION
=1,

1, AND C = |
ALL UNAFFECTED

TEST

THE

ANDC

R?2

THE

N g
THE

TEST

3_@'

RO
R4

"BLOS"

{, Z =2 B, V = 1, AND C
REGISTER REGISTER AREs
= ?fl Ru = ?p R% g?g SP

UPON
N

AND

Z=sd,

TEST7

N &
THE
RRB

"BLT",

AREg

UPON COMPLETION
THE

TEST

1{,

V =
ARE

THE REGISTERS
R3 = ? R4 =2 ?

THE

COMPLETION
{, Z = i{s
REGISTERS

TEST6

CONDITION

TEST

THE

077777

TESTS

AFFECTED

THE
1

THE

ARE:

177777

UPON COMPLETION OF THIS TEST
N = @, Z =08, V3 {, AND C =
SP

CODES

"e"

CODES

P20A0Q@PA,

(25252,

{25252

ARE
R2

125252

125252,

Page

UPON COMPLETION OF THIS TEST
N=28, Z =28 V=1, AND C =
THE

REGISTERS

MAPL@@

WHICH

TEST11

TEST

WHEN

THIS

=@y, Z

ARE

LEFT

SHOULD

TEST

UNCHANGED

NOW

vADD®,

EQUAL

®INC",

AND

EXCEPT

FOR

THE

AND

"BCS",

CONDITION

= 1|,

"BLE"

CODES

THE REGISTERS ARE: RW@ = 125252, Rl = Q¥QAW,
R3 = 125252, R4 = {25252, RH = 125252, SP =
MAPL@Q

WHICH

TESTi2
WHEN

EXCEPT

NOW

EQUALS

2era?a,

AND

TEST

"RQR'",

"BIS",

WADD",

THIS

CONBITION

TEST

ENTERED

AND

THE

CODES

ALSO

"BLO",

CONDITION

APE

FOR

WHICH

AND

ARE:

R2 = 125252
125252,

@52524,

UPON COMPLETION QF THIS TEST THE
N=2 Z=s1{, V= 2, AND C = @,
THE REGISTERS ARE LEFT UNCHANGER

ARE:

252524,

“COM",

ENTERED

=2y, V=1,

THE CONDITION CODFES
1,

voupen

"BGE"

CODES

AREQ

THE REGISTERS ARES$ R2 = 125252, R1 = uanap@, R2 = 125252
R3 = QP3G@2¢, RU = 125252, RS = 125252, SP = 125252,

UPON
N

COMPLETION

THE

£Z

THIS

REGISTERS

ARE

LEFT

TEST

THE

@&,

AND

UNCHAMNGED

WHICH

SHOULD

MONPIFIED

WHICH

SHOULD

NQOW

EQUAL

TEST

TESTL{3
WHEN

N =
THE
R3

UPON
N =
THE

THIS

00Q00Q2@,

COMPLETION

TEST14

WHEN
Ne

THE

00Q@2%,

IS
V

REGISTERS

TEST

THIS

CQODES

@Ua2pd,

125252,

THE

CONDITION

EXCFPT

"BGT",

THE
C

ARE:

{25252

CODES

ARE:

FOR

TEST

“BLE®

CONDITION

CODES

ARES

{252%2,

@52525,

AND

177777

ENTERED
AND

FOR

Av@and,

CONDITION

wBIC",AND

V =2
ARE

EQUAL

AREs
R4

COMPLETION
@,

THE

A, AND C = @,
LEFT UNCHANGED

NCW

ARE:®

“RBRLT"

C = 2,
125252,

@52525,

THIS

CODES

@5252%5

ENTERED

"COM

TEST
=

REGISTERS
=

UPON
N

TEST

V =
ARE

SHOULD

THIS
1,

THE

{1, Z = @,
REGISTERS

WHICH

TEST

@;Z = {1, V = 0, AND
REGISTERS AREs RO =

EXCEPT

BACK

"BLOS",

AND

"DEC"

CONDITION

177777,

125252,

THE

|, AND C = 1,
LEFT UNCHANGED

WHICH

SHOULD

NOW

EQUAL

852525,

WHICH

SHQULD

NOW

EQUAL

©#52524

CONDITION
EXCEPT
AND

FOR

125252

125252,

CODES

ARE:

Page

TEST1S5
WHEN

TEST

THIS

"ADC",

TEST

N =@, Z = 6o,
THE REGISTERS
R3

Q00000@,

YCMp",

ENTERED

"BIT",
THE

B52525,

052525,

Q52525

PAAEAR,

(25252,

A52525,

125252,

"MOveY,nsOB",

WHEN THIS TEST IS
N = @, Z 3 {, V=

THE
R3

REGISTERS
=

0AQQQA,

UPON COMPLETION
N&s @, Z= 1, V
RO

TEST

R®

052525,

B52525,

OF THIS TEST
=2, AND C =

DECREMENTED
CLEARED AND

TEST17

"CLR®",

"TST"

ENTERED THE CONDITION
B8, AND C = 0,

ARE:
R4

A
THEN

"ASR",

CODES

CONDITION

gé

THE
@ q

TEST

“BGT",BEGQ"
ARES

R{ = @52524, R2 = {25252
125252, SP = 125252,

UPON COMPLETION QOF THIS TEST
N = @, Z = 4§, V 2 3, AND C =
THE REGISTERS ARE NQOWg

TEST16

"BNE®,

CONDITION

V = {, AND C = 1§,
ARE: R2 = @52525,
R4

AND

ARE?
|

QUA@OR

AND

"BPL",

CODES

00067,

952525,

THE
@,

CODES

INSTRUCTION TO
INCREMENTED ARQUND

ARE:

{25252

125252,

CONDITION

SOB

"BNE"

CODES

ARES

Q@@p000
T0O 2000230

WASL"

WHEN THIS TEST IS ENTERED THE CONDITION CODES ARES
N = @, Z s 1, V & @, AND C = @,
THE REGISTERS ARE:
R@ = 125252, Ri = Q22A@Q@¢, Re = 125252
R3 = A0p@RP@, R4 s @52525, R5 = 052525, SP = 1252%52,
UPON COMPLETION COF THIS TEST THE CONRITION CODES ARES
N8

@4,

AND

THE REGISTERS

ARE

LEFT

TEST20

ASH,

AND

RZ
Ri
Re

WHICH
WHICH
WHICH

WHEN

N&a

IS
IS
IS

TEST

THIS

NOW
NOW
NOW

TEST

EQUAL T0 R2920@@a,
@gpneaat, AND
@gpoeoa,

UNCHANGED

FOR

SWAB

ENTERED

EXCEPT

AND

THE

CONDITION

CODES

ARES

THE REGISTERS AREs RO = 000002, Rl = ©090@01, Re = Quegea
R3I = pA@Q@2, R4 = 052525, RS = 052525, SP = 125252,

UPON
N

COMPLETION

THE REGISTERS

WHICH

TEST2!

THIS

AND

ARE LEFT

SHOULD

TEST

NOW

THE
1,

UNCHANGED

EQUAL

KERNEL

WHEN THIS TEST IS
N 8 @, Z = 1, V =

TEST

Q02000

CONDITION

CODES

ARES

EXCEPT FOR

P,AsR4"S

ENTERED THE CONDITION
@, AND C = 1,

CODES

ARE?Q

Page

THE REGISTEKS AREs R = 220@0r, Rl = Q@@30¢0, R2 = 0R@EQP
R3 = 0OQ@ARA, R4 = MAS52525, RS = 3852525, 8P = {25252,

UPON
N

COMPLETION

THIS

TEST

THE

AND

THE REGISTERS NOW EBEQUAL:
R@ = {72480, Ry = @aarap, R2
R4 =2 BSe5e5s RS
{25252, SP
AlLLL KERNEL P,A,R,®S = (25252,

TEST22
WHEN
N

THIS
@,

THE
R3

TEST

£Z

AND

TEST
=

{1,

@002g0,

UPON

ARE:

ALL

COMPLETION

172380,

KERNEL

THIS

TEST

FIRST

172490,

THIS

TEST

VERIFIES

ALL

WORK

PROPERLY,

ENTRY

)

172376

THIS

THE

THAT

Q2ra0CY

p2@AQ@,
SP

CONDITION

ARE
g

AuQgee

125252

CODES

AREQ

ARE:

(172320

STACK

"JSRM,

CODES

#7746

172316)

POINTER
U"RTS",

TEST

THE

STACK

LEFT

THAT

WAY

AND

TURN

AND

125252,

THE

P, D,R.’°S

SETS

THEN

LOAD

Q@0oar,

AND

TESTed

0OF

ARE:

125252,

V 2 @, AND C = ¢
THAT ARE MODIFIED
R1

CODES

KIPDRAS

B52525,
RS

I=SPACE

BRReen,

ENTERED THE CONDITION
@2,
AND C = &,

N =8, Z 2 {1,
THE REGISTERS
RO

IS
V

REGISTERS
=

LOAD

CONDITION

AND

"SP

(172376),

"JMPV

INITIALIZED

EXIT,.

MANAGEMENT

THIS TEST Is ONLY EXECUTED IF THE
THE SWITCH REGISTER ARE NON=ZERQO,

277406

"KDPART"

NRTIN,

POINTER

MEMORY

AND

THE

UNIBUS

MAP

UPPER 4 BITS <153i2> OF
THE TEST WILL LOAD MEMORY

Qpe20G¢,

KIPAR2

906l0@,

KIPARUY
KIPAR7

= aQ720@, KIPARS = 2Q7200@,
WILL ALWAYS EQUAL 177600,

0067p@,

KIPAR|

KIPARG

@R742@,)

KIPARG

MANAGEMENT TO RELOCATE TO THE 32K BLOCK NUMBER SPECIFIED,
I7T WILL ALSO SET UP THE UNIRUS MAP REGISTER @ THRU 6 TO
RELOCATE THE UNIBUS ADDRESSES CORRECTLY., (IE, IF BITS <i15312>
SPECIFY BLOCK NUMBER 3, THEN YOU #ANT TO BOOT INTO
MEMORY FROM 96K TO 128K, THE KIPAR®S WILL BE LOADED AS FOLLOWSS
KIPAR3

p766Q0

THE UNIBUS MAP REGISTERS WILL THEN BE SET AS FOLLOWS:
MAPLZ = 00RQ0@, MAPHR = @3, MAPL1 = Q20002, MAPLL = 03,
MAPL2

24@2na,

MAPH2

B3,

MAPL3

Q60Q0A0,

MAPH3

@3,

MAPLO

10R00Q,

MAPHY4

@3,

MAPLS

(20@2@,

MAPHS

23,

MAPLG

(400200,

MAPHe

03,

TEST25

THIS

TEST

MAIN

wILL

MEMORY

TEST

MAIN

FROM

VIRTUAL

MEMORY

WITH

1@@8

THE

CACHE

28K

DISABLED,

FROM

Page

VIRTUAL

ADDRESS

PROPERLY

THE

PARPITY ERROR
THE PC + 2 ON

IN
R@
R4

@010@@

TEST

THIS TEST
= PO1@22,
= p67400,

ANYWAY,

FORCE

MISSES

BOOT

STRAP

THAT

AND

TEST

THEN

TWICE

ADDRESS

SAME

HAS

DATA

THEN
DATA

125252

CAN

BOTH

BEEN

CHECK

GROUP

AND

WITH

YOU
IN

CACHE

WILL

THE

EITHER

DATA

16574@

WILL HALT
IS IN THE

DIES

NOT

COMPARE

165756,

AT ADDRESS 165776, WITH
KERNEL D=SPACE P,A,R,"S.

TESTS ARE CACHE MEMORY TESTS, IF EITHER OF
SUCCESSFULLY THEY WILL COME TO
A HALT IN
YOU DESIRE TO TRY TO BOOT YQUR SYSTEM, OR

WILL

THE REGISTERS ARE INITIALIZED AS FOLLOWS:¢
R1 = DATA READ, R2 = @e740Q%, R3 = 201000
RS = {77746 (CONTROL REG,) SP = 172376

DIAGNOSTIC

THIS

157776

MALT

OCCURS THE TEST
THE STACK WHICH

THE FOLLOWING TWO
THEM FAILS TO RUN
THE M9321 ROM, IF

TEST26

WILL

5S4

READS
A

THE

AND

CACHE

THE

AND

PROGRAM

THE

SELECTED,

DATA

LOADS

wAS

"CONTINUE"TM
OF

MEMORY

THE

PRESS
GROUPS

MEMORY

THE

DATA,

HIT,

THEN

DTA,

INTO

THEN
THE

ALL

THE
AN

CACHE,

ADDRESS

CHECKS

SEGUENCE

CACHE

MEMORY

FIRST

GRQUP

COMPLEMENTS

INSURE

REPEATED

DATA

THAT
ON

THF

LOCATIONS

AE TESTED IN THIS WAY, IF EITHER GROUP FAILS AND THE OPERATOR
PRESSES CONTINUE THE PROGRAM WILL TRY TO BOOT WITH THE CACHE
DISABLED,

THE REGISTERS ARE INTIALIZED AS FOLLOWS FOR THIS TEST:
R@ = 1002 (ADDRESS) R{ = 2 (COUNT), R2 = 1@@@ (COUNT)
R3 = 108@ (COUNT), R4 = 125252 (PATTERN) R5 = {77746 (CONTROL
SP = 172374 (FLAG OF ZERO PUSHED ON STACK)

TESTR7

TEST

VIRTUAL

28K

WITH

CACHE

THIS TEST CHECKS VIRTUAL MEMORY FROM
TO
INSURE THAT YOU CAN GET HITS ALL
MEMORY,

FINALLY

STARTS

CHECKS

WITH

MEMORY

GROUP

WwITH

BOTH

ROOT

WITH

THE

CACHE

GROUPS

177746

THEN

TESTS

ENABLED,

MATIN

GROUP
ANY

(CONTROL

REG,),

AND

HALT AT "CONT ¢ 2", THEN
THE PROGRAM WILL TRY TO

DISABLED,

UPON ENTRY THE REGISTERS WILL
R0 = POL108@ (ADDRESS), R! = 3
COUNTER)
,
R3 = 1000 (FIRST ADDRESS), R4
RS

@P10@@ THRU 157776
THE WAY UP THROUGH

ENABLED,

THE THREE PASSES FAIL THE TEST WILL
IF THE OPERATOR PRESSES U“CONTINUE",

BE SET UP AS FOLLOWS:
(PASS COUNT), R2 = 67408

67408

(MEMORY

172374

(MEMORY

COUNTER),

(POINTING

CODE

FOR

RE,

UPON

COMPLETION

A01020

THRU

REG)

THIS

TEST

157776

wWILL

CONTAIN

MAIN

MEMORY

ITS

OWN

FROM

VIRTUAL

APLDRESS

ADDRESS,

CONTROL

Page

{11/72
The

Bootstrap

bootstap

sWwiteh
AUmber

the

portion

number
read

lower
the

and

bvte

DEVICE

the

"BOOT"

from,

switches

the

switch

switches

set

ARE

zero,

the

determine

the

dpive

=11),

prograTM

wil]

code
the

test

turmns

memory

manage~eTMt

in
ang
and

attempt

"BOOT"

aqgain,

RK1i1/RK@S

DECPACK

RP1{1/RP2Z3

NAMES
TAPE,

TC1ii=G
DISK

NISK PACK,

Then

that

the

CARTRIDGE,

DISK,

sets

service

2elect

FOLLOUWS3

RPiieC

program

field

TM11

MAGNETIC TA[E SYSTEM,
DISK PACK, RwWR@A4
FIXED HEAD
DISKETTE

uUp

TwU1lé

RWSA4

and

wil]

RKi{i=D

(OR

RWS?3)

1Imstallation

The External
avalilasble or
the

select

device

the

dpive

of a
hardware
errop
a "RESET" imstruction

REVICE

MAGNETIC

4,4,5

U@>

the

A2f

which

oreration fails as a result
device
the program will do

AND

If the bootstrap
the
peripheral
jump back to the

byte

and

DECTAPE,

memory,

can

TMI1/TU1 O

tests

reaister

lower

devices

<@2

select

These switches
device,

RESERVED
RH72/TUL6
RH72/RP4

device

TC11/TU8RE

RX11/RX21

switches

123>

the

M33li=Y(

i1,

one

the

RH7A/RS24

looks

which

CODES

Se
&,
T e
1@,

program

determine

the

7),

set

attempt

drive mnymber,
"DEFALULT BOQOTY
THE

module

Back
Switch
the M930l-YC,

(see

schematics)

and
Beot
Therefore
should

on
FPower=Up
optioms
aPe
not
Power up REBQOQT ENABLE switch on

alwavs

off,

Because it is required that the diagnostic portion
of
the
Moststrap
always
be
executed
the
LOW
ROM
ENABLE
switch on the module (see
schematics) should always be or,
The remaining 8 switches
should
be
set
depending
on
the
default
odevice type and umit number desired,
(See startimg procedure amd schematics),

d,4,6

Starting

Procedure

Switch Settings
The lower bvte of the switch
nUmber
(@ = 7)
in switches
switches

The

<@&

upper

AUumber

byte
the

set to
device

have
code

set

have

used

the
drive
(1 =11)
inm

3>,

the
32k

switeh

block

should

memory

for

the

bank

=oo%tstprpap

Rage

ocperatiom

THE

CODES

DEVICE

{7)

ARE

switches
AS

<15

12>,

FOL|LOwg

TMIL/7TULD

MAGNETIC

2,
3,

TC11/TUS6
RK11/RKB5

DECTAPE,TCi1=G
DECPACK DIS CARTRIDGE,

RP{1/RP@3

DISK

5,
6o

RESERVED FOR FUTURE DEVICE
RHT2/TUle
MAGNETIC TAPE SYSTEM,

RH7@/RP@4

1@,
11,

THE

MEMORY

TAPE,

PACK,

RWP@4

FIXED HEAD
DISKETTE

BLOCKS

ARE

TMI1{

DISK,

PHYSICAL

MEMORY

{,
3,

PHYSICAL
PHYSICAL
PHYSICAL

MEMORY
MEMORY
MEMORY

32K
64K
96K

PHYSICAL

MEMORY

128K

{56K

PHYSICAL

MEMQRY

256K

28dK

14,
15,

PHYSICAL
PHYSICAL

MEMORY
MEMORY

384K
416K

=
=

412K
444K

16,

PHYSICAL

MEMORY

4d4BK

476K

17,

PHYSICAL

MEMORY

480K

S@B8K

18,

TWU16

RWSA4

(OR

RWSE3)

FOLLOWS:

RKi{=D

RP11=C

DISK PACK,

RM7@/RS24
RX11/RXA{

28K

=
=
=

60K
92K

{24K

Starting

The

Addresses

mormal

starting

addpess

for

this program

1777650d@,

14 the diagrostic portiorn of this program fails and the operator wanpts

attempt

Set

YROQT"

agmnyway,

must

up memory mamagement

lower

28K

"BOOTING"

valid

address

memory,

24, 1f deyice is on massbuss
Set

Wwith

stack

the

pointer

memory

bamk

these

nrumber

steps:?

imto

and

would

other

1oad

put

that

into

than

the

Address

s9Witches

<{5812>,

2B,

I+ device is om unibus3

Set

memoPry

unibuyus

map

mamagement,

registers

thry

map

same

meMopy

Deposit

Set

the

switch

address

Press

device

1730dé@

code

into

anmd

the

drive

“ace

the

PC,

number

the

lower

byte

the

continue,

Examples?
A,

RPO4

SET

STACK

LOAD
LOAD
SET

@p@e7m

PRESS

RK@5

|OAD

PQINTER

2@age@ea
173@9@d

INTO
INTO
INTO

42009

ADDRESS 4220@
THE PC (1777777@7)
SWITCHES

(RPGZ4)

{732@2

INTO

THE

the

(RK25

DRIVE

record

the

Action

diagnestic

imstryction
machime

(1777777@7)

SET A@@a3a INTND SWITCHES
PRESS "CONTINUETM

Operator

DRIVE

"CONTINUE"

and

fajiled,

portion

refer

the

RNOM

fails

listinmg

find

out

what

"HALTH

portinmn
of

the

Page

4, 4,7

List

errors

ADDRESS

error

hats

indexed

TEST

DISPLAYED

(7765000

TEST

the

address

NUMBER

SUBSYSTEM

UNDER

TEST

BRANCH

TEST

17765036
17765052
17765066

TEST
TEST
TEST

3
4
5

BRANCH
RRANCH
BRANCH

TEST
TEST
TEST

17765076
17765134
17765146

TEST
TEST

6
7

TEST

BRANCH TEST
REGISTER DATA
1@ BRANCH TEST

17765204
17765214
17765222
17765236
17765260
17765270
17765312
(7765346
17765360
17765374

TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST

12
13
14
14
15
16
16
17
28
20

CPU INSTRUCTION TEST
CPU INSTRUCTION TEST
"COM" INSTRUCTION TEST
CPU INSTRUCTION TEST
CPU INSTRUCTION TEST
BRANCH TEST
CPU INSTRUCTION TEST
CPU INSTRUCTION TEST
CPU INSTRUCTION TEST
CPU INSTRUCTION TEST

(7765450

TEST

17765474
{7765510
17765520
17765530
(7765542
(7765552
17765760
17766000

TEST
TEST
TEST
TEST
TEST
TEST
TEST
TEST

22
23
23
23
23
23
25
25

KERNEL P,A,R, TEST
KERNEL P,D,R, TEST
"JSKR" TEST
"JSR" TEST
"RTS" TEST
"RTI" TEST
"JMP" TEST
MAIN MEMORY DATA COMPARE
MAIN MEMORY PARITY ERROR

(7773644

TEST

CACHE

TEST

27 CACHE
27 CACHE

17765166

TEST

(7773654

CPU

TEST

‘
PATH

INSTRUCTION

RECOVERY

POSSIBLE

TEST

FROM

THIS

MEMORY DATA

ERROR

COMPARE ERROR

TEST 26 CACHE MEMORY NO "HLT"
PRESSING "CONTINUE" HERE WILL CAUSE
"BOOT" ATTEMPT FORCING "MISSES"

17773736

17773746

TEST

PRESSING

"BOOT"

17773764

TEST

MEMORY

"CONTINUE"

ATTEMPT

DATA COMPARE ERRQR
NG "HIT®

HERE

FORCING

CACHE

WILL

CAUSE

"MISSES"

MEMORY

PARITY ERPOR

PRESSING "CONTINUE"TM HWERE WILL CAUSE
"BOOT" ATTEMPT FORCING "MISSESTM

Recovery

Most of the
there
{8

halts

AND

displaved

17765020

ErrPor

are

amother

above error
recovery

mot

32K

halts are "HARD
failures,
from them,
Especially the

recelverable,

bank

memory

vour

best

bet

appears

which
two (2)

try

main

means
that
maim memopry

"BOOAT"

memory

imte

fallure,

I¢

the

processor

recovered

halts

from,

imn

ome

o0f

pressimg

the

two

cache

"CONTINUE"TM

tests

the

erroP

oprogram

will

Page

cam

either

attempt to finmish the test (If at efter:
17773644
or
177737%6)
or
force
"misses"TM
im both groups of the cache and attempt to "RQOAT" ¢the
system momitor with the cache fully disabled (if at eitheprs
17773654,

17773746,

{7773764),

If this program falls in anm uncortrolled
Umexpected
trap to location QAQRAZA4,
If

"2PAR06"

imto

address

regi{ster

Jocatiom

THE

AQARA4d

This
will cause all traps
the address lights so that

BITS

CPU

amd

"A22200"

to locatiom Q222024
the orerator
can

imto

to khalt
examime

ERROR

ARE

=
=

RED ZONE STACK LIMIT
YELLOW ZONE ATACK LIMIT

BITAd4
BIT@S5

=
=

UNIRBUS TIME=QUT
NON=EXISTANT MEMORY

BITA6

Q0DD

BITA7

ILLEGAL

ADDRESS

EXTENDED

ADDRESSING

5.1

Externded

Addressing

DEFINED

However,

(CACHE)

possible

mormally
the
I/0

yse

allows
accesses
page
(160a2Q(8)

memory

mamagemept

emJyjator
to
access bevond 28K for the examimpe
The reader should be familiar with the concepts
im the KDil=E precessor,

The

processor

memory

Virtual

manipulates

Jocations

FOLLOwSS

(Defimatijonm)

emylator rouitme
of
memory
anmnd

QUA0e,

287227210 in
CPU
errep

ERKOR

The console
fower
28K

Definmitiomn

with
the

HALT

S.@

Jocation

to
an
load a

17777766,

BITA3
BITO3

mammep it might be die
this i1s suspmected themn

whickh

amo

Physical

lé=bit

mrumbers

oftem

uses

are desigmated virtual addresses
as
which
are
asserted
on
the Umibus

and
of

to
only
the
to 177776(8)),
use

the

deposit
memory

Comsole

fumctions,
mandAgement

Addresses
withim

gemeral

addresses,

opposed
to which

registers

These

amnd

addresses

to
physical
addresses
devices are hardwired to

respond,

5.3

Address

Mapping

without

Memory

Mamagement

With memory management cdisabled (as is the case
followimng
depPessinmg
the
boot
swWwitch),
a simple hardware mappimng scherMe converts VvVirtual
addresses to physical addresses,
Virtual addresses imn the
@
to
28K

Page

range

28Ky

into

are

mapped

Virtual

directly

into

addresses

physical

addresses

physical

the

1/0 age

iNe

the

(36P7200(8)=377776(8)),

S¢4

Address

Mapping

With

memoFfy

mamagement

In
to

With

Memory

ermabled,

addresses

the

(1600P@=177776)

range

from

different

mapping

schemes, a relocation comstant s added
create a physical opr ®relocated’® address,

5,5

The

specified

1im

this

sectiom

l¢

Create

Determine the relocation
virtual address {nto the

Emabe

a
command,

Creatiom

easiest

physical

phvsical

virtyal

way

the

Virtual

create

address

bamk

address

disable

into

number,

mapméé

128K

Mamagement

this

procedure

frpem

apre

j2dk

to
‘

scheme

the

allows
tvype

each

the

user

imto

the

with

to:

management

used,

2ddress

baPk
that

Load

constanmt to relocate the
desired ohysical address,

memory

1is

virtual

Virtual address space conmsists of eight 4K banks where
be
relocated
by
the
relocaetiom comstant associated

The

rarmae

can
bamk,

dddress

calculated

hardware,

Address

two
The

virtual

address

separate

fields

virtual/address

divide
virtual

represented

¢the

address
by

the

bit
and

Yower

13
bits amd the physical bark by the uUpper five bits,
This erates s
virtual address im virtual bank @,
The calculated relocatior coAnstant
s placed in the relocation register associated with virtual hank @,
For

example,

normal

(533720)
and

between

comsequently

memoPry

physical

All

assume a user
capability

bamk

and

efither

T60300=77T7776)

AoAReR=217776

and

28K

1imit

accessed

enabled,

25(8)

the

must

management

locations

pages

wishes
to
access
of
the console is

access

The

derived

bamk

may

#25

1600Q0=177776,

and
as

the
a

I/0

page

relocated

wvirtual

Jocatiomn
@ to 28K,

(760000=777776),

virtual

eddress

5337272,
The
This address

address,
13720(8)

with
i m

follows:

(522000=537776)

accessed

eor

through

respectively,

The

bamk

viptual

%37

(1/0

Aaddress

relocatias2n

and

“age

descriptor
registers
{n
the KDi11=E
acddresses are Within the I/0 page,

The

relocatiom

added

vieldimg

Whem

constamt

the

physical

bank

wunit

stil)l

accessikble

@S2,

the

isg

virtual

sirce

This

address,

theirp

cHDRstant

shown,

533724,

@1372@

Virtual

520222

Relocated

533722

Physical

memory

management

Instryctions
relocated

and

through

this
hamk
(see
the eight virtual
bamk
7)
are not

accesses

mamagement

5,6

for

relocation

are

the
is

Memory

address
(Table

A=1)

Address
is

data

emnabled

access

virtual

bamk

prage

all

CPlJ

asccesses

the

comsole

simce

their

Table 5,1 for
bamks),
HNote
automatiecally

II/0

mot

Constanmt

are

emulator
virtual

relocated,

rPoutime

accesses

wWill

eXits

inm

the corresponding addresses of each of
that accesses to the I/0 page (virtual
relocated with memory management while

are

automatically

relocatec

when

memory

Utilized,

Mamagement

Registers

The relocation constamt that is added to the viputal address 1s stored
im
a
relocation
register,
0OUmre such register exists for each of the
eight virtuel benks,
In additiom to the
relocation
registers,
each
bank
has
{ts
own
descripotor
register
which
orovides information
regarding the types of accesses allowed (read only,
read or write,
orp
nO

8CCess),

The

memory

agaimst

must

set

anywhere

5,7
The

Address
Umribus

leaded

intoe

Table

5,2,

provide

along
the

a8lsoc

access,

with
4K

addresses
are

the

provides
The

various

forms

correspondimg

relocatiom

prolection

degcriptor

rPregister

allow

access

bank,

givemn

the

The

mamagement

the

roytime

the
{n

data

access

relocation
Table

relocatiom

read/write

cemplete

ceomnsole

logic

Assignments

Unibus address
177572,
This

memoPy

Within

regi{sters

The
ie

mamagement

umauthorized

the

registers

8,1,

The

for

Jloaded

full

each

1{m

the

and

the

relocation

bark

i{s

oporevided

descriptor

always

descCriptoer

comrstamt

B774¢6,

renister

in
to

of the control register to emable memory mampa@gement
register is loaded with the value 22021 to emable

amd

example
would

disable

previously
as

it,

deseribed

follows:

(locatiom

533723),

the

Page

172340

5208@

172356
7604

172500

77496

172316
774086

/Setting

/bank

for

/Address
/banmnk

bank

virtual

bank

virtual

descriptor

conmtrol

virtual

/Address

|
13727

/memory

enable

management

/Virtual address of location
/The data in locatiom §53372¢

/Wwill

virtual

{77872

(examime)

relocatiom

/To access extended memopry
/Setting relocatiom register for
/To access the I/0 page
/Address of descriptor register,

tvped,

desired

Page

Table

Unibus

Virtual

5,1

Adgress

Assigmnments

Relocationm
Register

Deseriptor
Register

172356

172316

172354

172314

120020=137776

172352

172312

jeagea=117776

17235@

1723172

P60RR2=NTTT776

172346

172306

PUARRD=05TT76

172344

172324

Qe2peae=037776

172342

17232

aoeeee=017776

1723549

172340

virtual

Address

160a@u=177776
142002=157776

Banmk
7

“age

Table
Relocatiom

Phyvsical

Rank
37

Number

5,2
Comstants

Relocation

Canstant

GaTerz

aT40f

dp720@

ga7oaae

33
3¢
31

POe600
Brelan
pRe20d

39
27
26

ARAeAY7
ABSed0
ANS4RG

aeseey

U
23
ee
el
ed
17
{6
)
{d
13

geseey
ARUEAD
ABULAR
ped200
ABLQEY
pASE6ERR
FAZL@G0D
paseae
AA3paR
Qo260

Ar24ad

i1
{4
7
&
5
&
3
e

Apeean
TA2QR0
Baledw
PALU4GY
galeer
wa1eae
baReAR
REa4ae

ARAean

Qadod
e

Page

Leadimrg
virtual

mew

rPelocatiom

bamk

will

constamt

cause

{nrto

virtual

the

relocatiom

addresses

Q2@2AQ20=177776

forp

access

the mew physical bank,
A
secormrd
banrk
cam
be
made
accessiPle
by
loadira
the
relocatiomn
comstanmt
and
degcriptor
data
into
the
relocatior amd descriptor reaisters for virtual barmk |
and
acCessing
the
Jlocatiom
through virtual address 020000=0P37776,
Seven harmks ape
accessible im this mamrner, by loadino the proper corstants, settinmg up
the descriptor data, and selectinmg the proper virtual address,
Bamk 7
(I/0 page) must remaim relocated to chysical benk 37 as it is actcessed
by the CPlL to execute the corsole emylator routine,
Memory

mamagement

disabled

Comtrel Register {77572,
a ’boot® command,

should

clearima

(loading

with

alwavys

disabled

prior

9s)

the

typinmg

The start command automatically disables memopry mamagemenmt amnd the CPU
begims
executing at the physical address corresponding to the address
specified by the previous Load Address command,
Derressimg
the
boot
switch
automatically disables memory management,
The contents of the
relocation registers are mot modified,

The

HALT/CONTINUE

6,8

MO3IAL=YD

6,1

Purpose

The

M93@1=YD

betweern
lime em

switch

programmed

instructions

for

requesting

downmliime

Jysimg DDCMP

protocol,

gatellite

6,2,

1o0ad

These

REMOTE={1

provide

its

memory

seri{al

features

mamagement,

tramsparent

secondary

system,

mode

l1ime

enable

pass=thproughk

datsa

amd

for

am asynchhponous serial
all
of
<the
neCessary

program

frem

a PDP=1l

Joad

arother

Tachine

computer

to be

Fumctiomality

Normal

Bootstrap (SA=173004)

Oprdirmariiy, when the ROM code
pass=through
mode,
First,
ascertaimed,
Ther, necessary

the

effect

8 terminal on a satellite compyter amd
the same computer,
It alse
cortaims

accepting

6,2

has

O0SOP

message

satellite

computer,

"Emnter

s imitiated, the satellite comes up
the
memory
size
of
the
comoyter
communicetioms regions are set
unP,

termimal

mode®

semt

the

full

serial

in
1is
and

linme,

A1l furthep communication is in ASCII with the ROM program pollimg the
ready
flags im the four control amd status registers to determirme the
mext actiom,
XON
("QR)
amd
XO0FF
(8)
are
supported
withim
the
and

tranmnsmission

assumed

duyelex,

Page

The
a

omly

way

DDCMP

Without

that

terminal

message,

tramsfer

The

address'",

"Emter

termimal

mode,"

6,2,2

Secomdary

mode

Amn

altermate

mode"

A1l

start

message

other

should

termimal

made

17756R2=177566

program
Wwithout

6,243

Senmdimg

callable

respond

(173214)

will

the

recelipt

messages,

"Proaram

Jload

trarnsfer

address",

and

this

cause

the

secomndary

normal

message

transiemtly

wil]l

addressed durimg

DDCMP

with

this

termipal

program

bootstrap,
a

program

eactivated,

used for
Jloadimg

"Enter

mode

The

load

bug

time,

The

semd

UDCMP

loadimg programs
a scroller imto

load,"

The
So

host
that

a2ddressed

secomrdary

mode

"Boot"

mode

imr to satellites
a machire with a

Messages

within

HMSG,

{62

use

1is

{t,

ROM

call

wil)

loaded

the

M9347

mumber

0of

bvytes

date

(1f

any)

with

the

a~dress

bytes

amd

comtaim

byte

has

0SQOP

bytes

through

the

8162

PC,
has

out,

the

with

"Request

only

MSG

returmed

1{s

Location

The message
sent

load

{dentical

subroutine

MOV

Wwhere

Program

replaced

are

subroutine,

JSR

disconrtinued

terminmal,

messages,

this

accepts

Joad messaqge may be
terminals
or
for

graphics

may

only

pootstrap,

address

actions

machime

mode

ROM

the

fellowing

1s sent
the

the

message

code

have

usirg

uUser

format

the

interrupt

program

driven code,

URtI]

the

but

messaqe

has

coentrel
beer

1is

nmot

com2ietely

Page

bo2,4

The

Receiving

boot

will

im{ftialized

Messages

automatically

and

the

program

interrupt

this

receive
for

the

DDCMP
serial

messages
1ime

1{f

receive

MOV

®H154,R0E

s GET ADDRESS 0OF DESCRIPTOR RLOCK

MOV
CMP

R, R2
(R2)+y (R2)+

; sérun DESCRIPTON POINTER
g R2 Re + 4
|

MOV

R2, (RD)

RESET

MOV

Hel@,,=(R2)

BYTE

CLR

=(R@)

INITIALIZE

CLR

=(RO)

CLR

=(R@)

ZERD

MOV

#le6U,=(SP)

GET

ADD

#7176, (SP)

STATUS

BIS

#1AC,0(SP)+

ENABLE

INTERRUPT

TST

=4 (R7)

WAIT

UNTIL

BEQ

o =4

BMI

ERROR

CMP

(R2)+, (R@)+

POINT

restart

JMP

@164

the

properly

recister

177=171

fop

follows:?

emabled,

DDCMP

BUFFER

COUNT

FOR

POINTER

DDCMP

CRC

AND

HEADER

FLAGS

COMPLETION

DL ADDRESS

INPUT
FROTMM

MESSAGE

0OSOP

ROUTINE

BOOT

COMPLETE

CODE

Boot:

The M93pi=YD uUses

locatioms

150=167

temporary
date
during program
the Righ usable memory address,
to leave room for buffers anmd &

for communicatiens

and

loads,
It also loads lecatiom
54 with
The address in 54 has
been
adjusted
stack for use by the ROM,

Page

Usipng

the

M93C1i=YD

The MO3@i=YD ROM will
pum of any PDP=1{
computer,
reauired with the followimg addresses
and vectoprs:?

FUNCTION

ADDRESS

Local

177562

1775610

490

termimal

Interproecessor
The

ROM

may

Jumctien

utilizimg
awitches

activated

switch

6,4

Proegram

Listing,

T7¢@

APPENDIX

7o,

Gemeral
fully

each,

outputs,
bussable

set

Two

DL=11%8

are

VECTOR

placimg

the

address

givem

for

the

and pressimg LOAD ADDRESS,

the prower=yp bootstrap feature
of
should
all be off for mormal boot,

switehes

Bits

the

This

desired

START

the
Mm932Z1,
Secondary mode

The
DIP
reauires

meme=,

descriptiony

decoded

has

2248

TTL

Bit

Memory,

compatible

organized

imputs

amd

TTL

512

wWords

compatible

There is also ome Chip Emable
provided
to allow for memeory expansion capabi{lity,

whose

trimgtate

outouts
|

are

Memery Arrays are addressed
decoding,
An
overriding

imn
straight
binmary
with
full
On=schip
chip=select
1{nmput
1{s provided which when
taken high, will inhibit the fupctiom causing all outputs te be
1im
a
high=impedance
state
that
meither
loads
nror drives the bus lines,

Data ®s specified
Bit lecaetioms,

7,2,

APPLICABLE

D,E,C,

DOCUMENTS

are

permamnenrtly

(Latest

revision

programmed

data

ifnto

the

2048

order)?

Digitaly

A=SP=7665212=0=8,

AmPS=1900002=6S,

"Process

Compatibility

"Gemeral

Regquirements

Assurance

Specification

Integrated

Te3,

This

Test

Methods,",

DEC

Quality

aljl

©peratinmg

fop

Yipolar

Circuits",

REQUIREMENTSG?

device

shall

meet

the

followimg

requirements

under

Page

conditions

73,1

and

the

full

operating

Free

Air

Temperature

Rande,

Mechanical:

734141

Package

reauirements

7To3,

over

Comfigurationt

Digital

REQUIREMENTS

Specitication

dual

7¢3:1e3
Pim Configurationt = Shall meet
AePS=1900002=6GS,
be
of
wuniform
hRigh

1,4

©i1

Pim

and

lime

shall

meet

Sectiom

the

1,2,5,

(Continmued)

7Te3.142
Material
(Packsaimgls = Shall be
or
equivalent),
Silicome package shall
Wwritten approval
from D,E,C,

grease,

A=PS5S=1940022=GS,

other

ceramic

not

or plastic (Eroxy=B)
shippeg withoyut prior

the requirements of
quality,
delivered

Digital,
free from

contaminants,

Cornmection

Diagram:

Shall

meet

the

recuiremePts

7¢3,1,5
A,

Therma)
Junctiomn

RaJA=+78

to Ambient?
C/W maximym

soldered

{into

Junction
RAJC=+28

te (ase:
C/W maxi{imum

freon

7¢3,2

Resistances

(measured

printed

circuit

(measuyred

imn

freemair

with

the

board),

with

the

device

immeprsed

bath),

Electricalsy

7¢3,2,1

Logic

Diagrams

To3,2,2

Absolute

Maximum

Shall

meet

Ratimgss

device

requirements

Reference

Table

Figure

inm

Page
793,23

Recommended

793,24

Electrical

7o 3,25

Test

Figqure

73,3

Load

Characteristics;

and

Timing

Diagrami

Reference

Table

Shall

meet

not

11,

111,

the

Operatingy

Teg3:,5%5,3

damaged

requirfements

to
C

The

+75

+150

device

altitudes

shal)

S0,200

feet

mechanically

(9¢mm

mercurv),

Humiditvs

Operatimgl
range,

=60

Altitudet

electricallyv

Storage}

13.,3,2

1@% to 9€% R,H,

(nom=condensinqg),

OStorageil

(condensing

REQUIREMENTS

95%

R,H,

over

the

cperatihg

storage

teMpe@rature

temperature

allowed),

Prange,

(Continued)

Markinmg:

Shall comtain vendor
name
lecatiomn amd data code,

73,5

Temperature}y

7T¢3,8

Conditions

Enmvironmental:?

Te3,3,1

7.3

Uperating

7¢

Process

Compatibility

The
deviee
shall
stay
reauirements
and
shall
cosmetics when subjected

symbel,

Test

vendoer

part

number,

Pim

Methods:

withim
the
im{tial
electrical/mechanicel
moet
show
army
evidemce
of
degradatiom in
to the following methods,

Page
Te3,51

Marking?

Digital,

A=SP=7665212=0=@,

Sectior

Test

Method

10@,
"Solvenmt

7¢3,5,2

Refer

Compatibility

Te3.6
The

Shelf

device

after

Resistance®,

Digital,

A=PS=» | 90RAR2=5S

for

oether

Process

Reaquirements,

Lifes

shall
vear

meet
at

the

intial

storage

Electrical/Mechamiceal

requirements

for

regiliPerments

temperature

amd

relative

humidity,

73,7

Packaging

Markimng

the

73,8

angd

Digital

shall

conmtain

sSymbol, vemdors part
shall
meet
I1,C,C,

rajl

rPeauirements

Shkippings

packagairng

vemdors name or
avamtity,
It
ajrplame,

arnd

truck,

Digital

mimimum

infQrTMation,

mumber,

Purchase QOrder NuUmPer
requirements
for shiprment

Devices

shall

packaged

referemnced,

CONFLICT

The

requirements

amy

documents

The

for
S3ipolar
document
is

REQUIREMENTSS
of

when

this
a

document

conflict

shall

take

precedent

over

all

and

arises,

Approval:

devices

im{tially

by
the

A=PS=1000002=0(S}

7,4,

7,5,

meet

A=PS=1902¢0n2=06S,

Gemeral Reauirements DEC Quality Assuranmce Specificatiom
Integreted
Circyits
shall
apply
where
mno
other
specifically

anrd

givem

submitted

approved

omrly

progduction
requiremernts

after

Pum
as

have

uymder

by Digital
samples

been

specified,

this

specification

Equipment

representative

examimed,

shall

Corporatiom,

tested

the

amd

have

Approval

vendors

found

been

shal)

nmormal

meet

the

Page

7:6,

Construction

Approved

vendors

designmg

changes:

who

desire

materials,

Fequirement,

shall

amy

process,

submit

time

process

writtem

make

control

request

change

which

describing

the

imvact

army

detall]

the

changes
reauested,
Also,
wevidemce
to
Justify
such chamaes,
The
cognizant emgimeer
will
them
submit
this
reauest
to
the
proper
Emaineerimg
Department(s) Componrent Ergireering Group amd all oroduct
limes affected,
No
chanages
shall
be
fincorporated
until
weritten
approval

has

been

recefved

from

the

above

mentiormed

group

authorized

Failure to
Seurce's

comply shall be sufficient cause for removal as
complete requalification may be reauired before

deemed

the

Cognizant

Emgineer,

acceptable,

TABLE

ABSOLUTE

"Ayalified
the 2poduct

MAXIMUM

RATINGS

PARAMETER
NAME

SUPPLY

Irput

VOLTAGE

Voltage

SYMBOL

VAL UE

vCC

+7.0

UNTT

VIN

=1.,5

70O

+5,5

Voltage

VOouT

=%,5

+5,5

Temperature?
Storage Range

Tstg

=65

Owtput

TABLE
RECOMMENDED

4159

OQPERATING

CONDITIONS

PARAMETER
NAME

SYMBOL

VALUE
MIN,
NOM,

MAX,

“UNIT

Supply

Voltage

V(G C

4,75

525

Temperatures
Operating Free=A§r

+ 7@

5,9

GrPOUDS

i|y@A3T=ayb 3MIND BLEY[OA 01 k)YO ®v2eea=li=tT(0])(1V)up me
47691

CA2A==0R3A0A=ALAtI A AR=

111

0|MIdaNAOCNn€UdTY] |]dIaNowcKuOelAl |ANITL=RA3IMNODA
93e13%

oui
v

bIJF3uNEd4)AMu0NnN4Qdg
vH{T)

01 ) yb

w10

T3A

m.._

AG h= A

NALONTSLTI3O9ND1A

"“NXIvW

H4pIsSSNeBaaao\3JUTJp]P|JP9UYVUBAMJ8OIIITpNnUEAdNRdTuIuE]]NddUUYPe]bee9|dxOBeADBaE)J’YU]Ed|J0IAUdN2Tdung
‘%S¢ Vi 0= L+D JG
¥

H
¥

Hh#A=39GA
35(01) L0gd

1°o2uel0ioedes

Rage T4
NOTE
The aboye characteristics are
to meet the output high level

the

chip

1{s

enabled

guaramteed
state whenr

CE=8,4v)

armd

programmed
bit
{s
addressed,
These
characteristics camnot be
tested
prier
toe
programming
but
are
guaranteed by
design,

ELECTRICAL

A,C

SWITCHING

CHARACTERISTICS

(Continued)

(TA=25

PARAMETER

VALLUE

es
NAME

Accegs

(Via

SYMBOL

Time

Address

VCC=5,2V)

MIN,

MAX,

tAA

tDIS(2)

tEN(2)

MIN,

¢C

MAX,

Imputs)

Output

Disable

OQutput

Erable

Inmpuyts
Time

35
35

NOTE

Output Disable Time
for
the
outpoyt
resistance

state

high,

the

takem
time

taken

active

whem

active

output

wher

for

both

Tow,
The
high
defined
as
a
waveform eaual to

is
to

the
¢time
reach
a

either

OQutput

Chip

Emable

the

Qutput

Chip

Emables

taken
high
Emable

time

are

become

takenr

resistance
state
is
poimrt
om
the
output
@
V of 2,5V frem
the

level,

UNTT

[age 75

ARRAY

BIT

LINES

T e oo

N
-

INPUT

MULTIPLEXER
SEAE

(16

- 'HIGH ORDER

ADDRESSES
Ap

j“

1.5\/.' 4

-~ ACCESS TIME ViA ADDRESS INPUTS

Chip Enable

Input
g

tD'S an, o0

1.5V
e

\Y
15V

BN |

WIEN @é% 2o

vO
Output

ois 0|

Output

< VY
QUTPUT ENABLE AND CISABLE TIMES

SWITCHING VAVEFORMS

PACE

TOP VIEW
S

Address
- Address

TN\

AB: 1

f 161 Yce Supply Volitage
’5-! A7 Address

.Address A4y 3
Address

A3|

‘Address

~AO |

- Address-

A1 | 6

- Address

~GND |

| 14
|

13 |

AB Address
CE

Chip Enable

-;12 & 01

Output

11 1 02

Output

10 ' 03 Output
9 | 04

FIGURE

PIN CONNECTION

DIAGRAM

Output

)

?
f
f
:
é
)
;
Pf

*(12) T (11)T Hmj (Q)T
|

) :
|

)
[S S
o

,7-

e,
)

-‘
‘

‘

,
I’

)

et
a

|
.

]

X
I

RES

ADD

DECODE

)

(S)f(e)l@) @ (

FIGURE

- LOGIC BLOCK DIAGRAM

Cage

PROGRAMMING

PROCEDURE
s

Device Descriptions: This memory array is manufactured with loadie leve)
storage lncationrs,
In order to program a Jogic level ope
Zeros im all
logic
Yevel
"@"
<to
at a specified bits electrically alter a bit at
logic

The

level

There

"i",

bits

each,

device

i1s

programmed

are

2248

per

the

bits

which

Nigital

are

organized

Ecuipmenmt

5172

Corporationm

words

"attern

specification,

LIMIT

CHARACTERISTICS
Programming

COMDITION

UNITS

Pulses

Amplitude

Voltage

28.9'?9"/.'2'/;

(clamp)

+5%

m A

Constant
Voltage

Currentg
1imit

current

SOLUFCEe,

Ramp

Rate

dv/dt
Width

Pulse

Duty
Sense

max,

7.5+5%

Cycle

70%

Current

20,2+0,5

V/us

peoints,

iS5

m A

The

15@

load,

mim,

sense

current

must

imterrupted

after
each
for
12
wus
cUurrent ramp

<7édY/us,

Programming

Maximym

for

Semsed

Voltage

programmed

and clamped

e8,0V+R%=2%,

S+ H%=0R%

Vtce

a-<ddress
charge
mim,
The sense
rAte dv/dt must

TeP+B41

bit

programmed

when

siyccessive

sense readimgs 1TM us
with no imterveninmg

1",

two

apart

the
prPOogramming pulse, pass
ion
condit
thig
When
limit,
has

heen

and

the

program

met,

pulse

terminated,
Delay
of

from

program

semnsimg

trailing
pulse

output

edge

Ml".

minmg

voltage

To Electrically Alter
a Bit at Logic "@" to
LGQ‘C

Qa7

before

200

pulses

additional

are

traimn

applied

then

A
o

tnpui Conditions:

PARANMETER

.
.

‘:‘

)

:"".A

)

i
o

)

]

AN
v

[

~5ns from 1V to 2V

‘.
)

[

’

)

;

’

tEN

Graczzmm

"1 'fi

|
.

‘
.

‘.

‘

L‘

6GO

)

3004}

’

.
.

I.‘ *

hy
IR}

C
)

[

tD‘S 209 00

TAA

.ot

‘~

.«
N

.‘.

[

.
Lo

)
o

‘.

Vee

Ffequency - 1MHZ

{swnwoms

_Amplnude -0V to 3V
Lo '. Rise & FaH Tame

g e

‘

a¢

’

=
@D

SWITCHING TIME TEST CON

DITION

OUTPUT

LOAD

ctRcuiT

— 28V C!am.p

200 mA

lf’CU t

Sense "1’

Y 277

“A.)

Sense Pulse Rise Time dv/dt <70 V/is

CoL

’

~ r—-0.7 5
|

‘_J I
T

)

|
mpare Vg . and V

B.)

200

Two successive Sensa Readings where v@mflf sense *°1°”

D.J

16 Additionat Program Pulses

E.)

Sense Current interrupted during Address

Programi

and

Sense

Pulse

Train

sense ‘1°°

VOLTAGE WAVEFORM DURING PROGRAMMING

change..

———
e
L,

10 US-;

e B

fl@