Digital PDFs

EK-LSIFS-SV-005

January 1985

416 pages

Original

46MB

view download

OCR Version

25MB

view download

Document:	LSI-11 Systems Service Manual
Order Number:	EK-LSIFS-SV
Revision:	005
Pages:	416
Original Filename:

OCR Text

EK-LSIFS-SV-005

Prepared by Educational Services

of
Digital Equipment Corporation

Preliminary, April 1978
1st Edition, March 1979

1st Edition (Rev), September 1979
ond Edition, November 1980
3rd Edition, August 1982
4th Edition, November 1982
5th Edition, January 1985

Printed in U.S.A.

The material in this manual is for informational purposes and is subject to change
without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may

appear in this manual.

The manuscript for this book was created on a Digital Word Processing System
and, via a translation program, was automatically typeset on Digital’s DECset
Integrated Publishing System. Book production was done by Educational Services
Development and Publishing in Mariboro, MA.

The following are trademarks of Digital Equipment Corporation:
Micro PDP-11
MicroVAX

RSX
RT

DECmate
DECUS
DECwriter

PDP
P/OS
Professional

UNIBUS
VAX
VMS

DIBOL
LSI-11

Q-Bus
Rainbow

VT
Work Processor

MASSBUS

RSTS

CONTENTS
VOLUME | - SYSTEMS CONFIGURATIONS

GENERAL CONFIGURATION RULES ... 1
GENERAL CONFIGURATION RULES ... 1
e6
e
OO BRY oo
MEEMI
REFRESH CONFIGURATION PROCEDURE ... 11

e e 21
e
MICRO/PDP-11 SV ST EM oot
t 21
e ettt
tt
oo
L
ERA
GIEN

PDP-11V03 AND PDP-11T03 SYSTEMS ... 35
VPP PP PPPPPR PP PP PREPPRE 35
=1 3] = T RV 0 1 T
SVPPUPPPPPRSPPRRPPRREPS 43
P
T
1
10
B
I
=T ] =2

PDP-11T03-L AND PDP-11V03-L SYSTEMS ... 49
PRSP PRS PR PPREPREPPITPE 49
TN U
= I I 01
=y
PPRPPREPPRPPREEPI P 54
=3 I RV 0 1 T USRS
=Y

PDP-11V23 AND PDP-11T23 SYSTEMS ... 63
ST EM oot 63
PDP-11V23 SY
PP-11T23 SY ST EM .ottt 73

PDP-11/03-BASED MINC/DECLAB—H/M!NC SYSTEMS .o 81
MODULAR INSTRUMENTATION COMPUTER (MINC).....oooiieiis 81
DECLAB-11/MNC S ST EM oot 91

PDP-11/23-BASED MiNC/DECLAB—H/M!NC SYSTEMS ..o 101
U PP PP PP PP PP EESPPPEPPRPPEETILIIIELRER 101
TU
N TN (T
DECLAB-11/MNC PDP-11/23-BASED SYSTEM oo 112

ST EM oottt 123
PDP-11/23 PLUS SV
s s e e 123
AL oooeii ottt ettt e e e e
GENR E
t 124
t
e ss
tet
ae e e
COMP ONEN T S oo
ST EM oo 135
PDP-11/23S SY
B
KDF11- PROCESSOR MODULE (CPU) (M8189) ..o 137
KDF11-B LED INDICATORS ... 139
MSV11-D MOS RAM MEMORY ..o 141

a s 145
et
EXPANSION BULES oo ettt
280

CONTENTS (Cont)
PDP-11/23 PLUS, MICRO/PDP-11 AND MicroVAX EXPANSION ...............o. 151
R AL ..ottt
GENE

e 151

VT103 LSI-11 VIDEO TERMINAL ..o 157
e 157
e t
AL oott
GENER
LSI-11 BACKPLANE ... ooy 159
CONFIGURATION .o 160
STANDARD TERMINAL PORT ... 160
VT1X3-MM MAINTENANCE MODULE (M8208) .........ooooeiiiiiiiiiiii 162
11MDS-A MICROCOMPUTER DEVELOPMENT SYSTEM ... 165

165
AL L.
GENER
SPECIFICATIONS .. e 167
e 169
CONFIGURATION .o
SYSTEM VERIFICATION PROGRAM ... 185

COMMERCIAL SYSTEMS e 189
D315 DATASYSTEM oo 189
PSP RTP PSSP 211
72 PP
G
e 222
DIB24 ...
D B2 e e 232
D B33 e 235
D B85 . e 237
239
PPP
D IC T 1O P
DPM23 DISTRIBUTED PLANT MANAGEMENT SYSTEM.................... 243
LABORATORY SYSTEMS ..o 257
P P-T 108
257
TELEPHONE COMPANY SYSTEM ..oiiiiii

e, 269

CCT1A PDP-11V03 SYSTEM ...o 269

OPTIONS

GENERAL MODULE INFORMATION ..ot 291
BATT-M MOUNTING BOX ..t 292
BATT-N MOUNTING BOX ..o 304
CONFIGURATION Lo 306

CONTENTS (Cont)
BAT11-S MOUNTING BOX ... 325
GENERAL .. e 325

POWER SUPPLY ..o 328

FRONT PANEL SWITCHES AND INDICATORS. ..., 333
FRONT PANEL BEZEL ..., 334
HO276 BACKPLANE ... .o 335
e 338
e
e
EXPANSION ...

BAT1-VA MOUNTING BOX ...t 341
AL <. ot 341
GENER

H349 DISTRIBUTION PANEL ... oo 345
t 345
e e
R AL oott
GENE

H780 POWER SUP LY . 347

H786/H7861 POWER SUPPLIES. ... 352
SPECIFICATIONS ... ettt 352

H7864 POWER SUPPLY ..ottt 355
SPECIFICATIONS ...ttt 355
HO275 BACKP LANE . o e 358
AL ..o 358
GENER
e 359
SPECIFICATIONS et
CONFIGURATION Lot 360
INS T ALLATION e 362

e 364
HO276 BACKPLANE ... ittt
R AL .ot 364
GENE
SPECIFICATIONS .. et 365
CONFIGURATION Lottt 366

HO278-A BACKPLANE .. oot 368
R AL oottt oottt
GENE

s 368

MMV11-A CORE RAM MEMORY ..o 377

CONTENTS (Cont)
VOLUME Il - MODULE OPTIONS

AAV11-A DIGITAL-TO-ANALOG CONVERTER ..

AAV11-C DIGITAL-TO-ANALOG CONVERTER ...

CONFIGUBATION L.

PROGRAMMING THE AAVT1-CL e

/O INTERFACE ...

ADV11-A ANALOG-TO-DIGITAL CONVERTER ..o
ADV11-C ANALOG-TO-DIGITAL CONVERTER ...
CONFIGURATION oot

SR BITS oo

DATA BUFFER REGISTER ..ooovovoeoeeeeeeee ettt eane e

/O INTERFACE ...ooooooooeeeoee oot

AXV11-C ANALOG INPUT/OUTPUT ..o

CONFIGURATION ..o
S oottt ettt
SR BT
DATA BUFFER REGISTER ..o

DAC A AND DAC B REGISTERS ...

/O INTERFACE ...

BCV1X BUS TERMINATOR, DIAGNOSTIC AND
BOOTSTRAP MODULES ... e

BDV11 BUS TERMINATOR, BOOTSTRAP AND

DIAGNOSTIC ROM oo
BDV11 HALT/ENABLE, RESTART,
AND BEVNT SWITCHES ...

DEQNA INTERFACE (ETHERNET) ..o oo
AL .o e
GENER

PREINSTALLATION VERIFICATION ..o,
M7504 MODULE ...
DEQNA BOOT SEQUENCE ...

DHV11 8-LINE ASYNCHRONOUS MULTIPLEXER ...,
GENERAL ..o

MODULE INSTALLATION ..o
CABLES AND CONNECTORS. ...,
DLV11T SERIAL LINE UNIT Lo

CONTENTS (Cont)
DLV11-E ASYNCHRONOUS SERIAL LINE INTERFACE ... 483

DLV11-F ASYNCHRONOUS SERIAL LINE INTERFACE ..., 498

DLV11-d SERIAL LINE UNIT Lo 511

DLV11-KA EIA TO 20 MA CONTROLLER ..o 533
CONFIGURATION L.oeiie ettt 533

DMV11 SYNCHRONOUS CONTROLLER ..o 539
DMVTT OPTIONS ..o 539
CONFIGURATION ..ot 542
UPPPRPPPPPRPPPPS 556
O
1]2 T =1 1 < TP U

DPV11 SERIAL SYNCHRONOUS INTERFACE ..o 563
CONFIGURATION oottt 565
RECEIVE CONTROL STATUS REGISTER (RXCSR) .cccviiiiiiii 568
RECEIVE DATA AND STATUS REGISTER (RDSR)...cccoiiiiiii 574
PARAMETER CONTROL SYNC/ADDRESS REGISTER (PCSAR)....... 579
PARAMETER CONTROL AND CHARACTER

LENGTH REGISTER (PCSCR).covviiiiiiii e 583
TRANSMIT DATA AND STATUS REGISTER (RDSR)..c.coveniiiiiinn 590

DRV11 PARALLEL LINE UNIT o 595

DRV11-B GENERAL PURPOSE DMA INTERFACES ... 601

DRV11-J GENERAL PURPOSE PARALLEL LINE INTERFACE ... 605

DRV11-P FOUNDATION MODULE ... 619

DUV11-DA SYNCHRONOUS SERIAL LINE INTERFACE ... 632
DZV11 ASYNCHRONOUS MULTIPLEXER ..o 644

FPF11 FLOATING POINT PROCESSOR ..o 655
e e e 655
R AL oottt oo
GENE
ot 655
.
RATION
CONFIGU

G7272/M8659 LSI-11 GRANT CARDS ..o 659
IBV11-A LSI-11 INSTRUMENT BUS INTERFACE ... 661

KD11 LSI-11 PROCESSOR MODULES ... 667

vii

CONTENTS (Cont)

KDF11-AX 11/23-A MICROCOMPUTER ....cciiiiii 680
KDF11-BA 11/23-B MICROPROCESSOR ... 692
R AL oot 692
GENE

CONFIGURING THE KDF11-BA .o 693
FACTORY SWITCH AND JUMPER CONFIGURATIONS ..o, 716

KPV11-A POWER FAIL/LINE TIME CLOCK (LTC).oiviiiiiiiiii 720
-B 120 Q@ TERMINATOR
-C 250 Q TERMINATOR

KUV11-AA WRITABLE CONTROL STORE ... 725
KWV11-A PROGRAMMABLE REAL-TIME CLOCK ... 730

KWV11-C PROGRAMMABLE REAL-TIME CLOCK ..., 740
CONFIGURATION ..o 741
e 747
e
S ittt
SR BT
BUFFER/PRESET REGISTER ... 751
[JO INTERFACE ... 751

KXT11-A SBC-11/21 SINGLE-BOARD COMPUTER ..., 752
AL ..o 752
GENER
e 753
CONFIGURATION .o
S ittt 761
ODT ROM

VOLUME Il - MODULE OPTIONS

LAV11 PRINTER INTERFACGE ... 767
LPV11 LPO5/LA180 INTERFACE MODULE ..........cooooi 772
LSI-11/2 PROCESSOR MODULE DESIGNATIONS ..., 779
MCV11-D CMOS READ/WRITE MEMORY ... 783
GENER
AL e 783
CONFIGURING THE MCV11-D MEMORY MODULE ........................... 784
MRV11-AA READ-ONLY MEMORY oo 789
MRV11-BA ULTRAVIOLET PROM-RAM ... e 793

MRV11-C READ-ONLY MEMORY MODULE ..o 803

Viii

CONTENTS (Cont)
MRV11-D UNIVERSAL PROM MODULE ..ot 815
GENERAL oottt

e, 815

MSV11-B READ/WRITE MEMORY ....oooooooioeoeooeoeooeeeeoeoeeeee e 825

e 828
MSV11-C MOS READ/WRITE MEMORY .....coovomieieieooeeeeeeeeeereeee

MSV11-D.E MOS READ/WRITE MEMORY ....oovoimioieieeeeieeeeeeeeeeeeis 833
MSV11-L MOS READ/WRITE MEMORY ....oovmivomieieeeoeieeeeeeeeeee e 838
GENERAL oot 838
MSVTT-L POWER oot 838
CONFIGURATION oot 841

MSVT1-P MOS MEMORY ..ot 849
GENERAL oo 849
CONFIGURATION oo 851
CONTROL STATUS REGISTER (CSR) BIT ASSIGNMENT ......ccooenee 857
e, 860
AC MULTIFUNCTION MODULE ....cooiviiooioeeee
MXV11-AA
CONFIGURING THE SERIAL LINE UNITS .ooioieieeeeee e 872
MXV11-B MULTIFUNCTION OPTION MODULE ...ooovooivoeeieeceeeeeicn 884
GENERAL oot 884
RKV11-D BUS INTERFACE FOR RKV11-D DISK

DRIVE CONTROLLER ..o oo oe oo 914

RLV11 CONTROLLER MODULES ..o 930

RLV12 DISK CONTROLLER ..ot 943
CONFIGURATION oot 945
CONTROL STATUS REGISTER (CSR) oecvoeiveeeeeeeeeeeeeeeeeeeeeeeeeesseaens 949
BUS ADDRESS REGISTER (BAR) ... oeeeeeeeeeeeoeeeeeeeeeeenieeeeeeienaseeen. 952
DISK ADDRESS REGISTER (DAR) ..eoeeieieeeoeeeoeeeeeeeeese e 953
MULTIPURPOSE REGISTER (MPR) ...oeeoeieeeeeeoeeeeeienee 956
BUS ADDRESS EXTENSION REGISTER (BAE) ...oovevieceieeiceecericin. 960
RQDX1 AND EXTENDER CONTROLLER MODULE

T, RDB2)....oveooooeeveoeeeeesseeeesseeeeessessese oo 961
(RX50, RD5
LOGICAL UNIT NUMBER SELECTION ....ooivimiiiieeieeeeccie e 963
RQDX1 EXTENDER MODULE INSTALLATION ...oooviviiireiececiccisncens. 966
RQDX1-E EXTENDER MODULE OPTION ....oooimiiiieiirinieceeiecieeeceseeen 966
RQDX1-E EXTENDER MODULE INSTALLATION ..o 966

CONTENTS (Cont)

RXV11 FLOPPY DISK INTERFACE ..o 973
RXV21 FLOPPY DISK CONTROLLER ... 982
TSV05 TAPE TRANSPORT AND BUS

INTERFACE/CONTROLLER ..ot 996
996
R AL oottt et
GENE

r eeeee e ee es

VSV11 RASTER GRAPHICS SYSTEM ... 1007

R AL oot 1007
GENE
M7061-YA SYNC GENERATOR/CURSOR

CONTROL BOARD ...ttt 1009
M7062 MEMORY BOARD ... o 1016
M7064 DISPLAY PROCESSOR MODULE ..o 1019

PERIPHERAL OPTIONS

RC25 8-INCH DISK DRIVE SUBSYSTEM ... 1023
R AL ..ot 1023
GENE
SPECIFICATIONS. .. et 1029
HOW TO MODIFY THE UNIT SELECT

NUMBER PLUG ...ttt 1038

RD51 11 Mb WINCHESTER DISK DRIVE SUBSYSTEM ... 1043
R AL oottt 1043
GENE
VARIOUS CONFIGURATIONS FOR EXPANSION

OF THE R ST oottt 1046

RD52 31 Mb WINCHESTER DISK DRIVE SUBSYSTEM ... 1053
AL .o 1053
GENER
RKO05 DISK DRIVE SUBSYSTEM ..o 1064
RLO1/RL0O2 5.2/10.4 Mb CARTRIDGE DISK DRIVE UNIT ... 1070
RX01 FLOPPY DISK DRIVE. ...t 1074
RX02 FLOPPY DISK DRIVE ... 1077
RX50 FLOPPY DISK DRIVE SUBSYSTEM ..o 1082
GENER
AL L. 1082
SYSTEM AND EXTERNAL SUBSYSTEM

INTERCONNECT L. 1087

CONTENTS (Cont)
TUS8 TAPE CASSETTE UNIT oo 1098

GENERAL ..., 1098

APPENDICES

DIAGNOSTIC MEDIA AVAILABILITY oo 1105

FLOATING ADDRESSES/VECTORS ..., 1125
LSI-11 BUS SPECIFICATION .ot 1127
GENERAL ... 1127
DATA TRANSFER BUS CYCLES ..., 1137
D AT

ee
ana 1139

D AT OB

ee
e 1142

DATIOB . e 1145

DMA PROTOCOL .o 1148
INTERRUP
TS e 1151

CONTROL FUNCTIONS...ot 1157
BUS ELECTRICAL CHARACTERISTICS ... 1160
SYSTEM CONFIGURATIONS ..o 1164
FCC INFORMATION .. oot 1168
GENERAL ..o et
e e
et 1168

LAV11/M7949

LAV11 PRINTER INTERFACE

Amps

+5
0.5

Bus Loads

+12
0

AC
1.8

DC
1.0

Cables

BC11S (for LA180)
7009087 (for Centronics line printerTM models
101, 101A, 101D, 102A, and 303)

Standard Addresses
LACS

177514

LADB

177516

Vectors
200

Diagnostic Program

Refer to Appendix A.

Related Documentation

LAV 11 User’'s Manual (EK-LAV11-OP-001)
Field Maintenance Print Set (MP00306)

LA 180 DECprinter | Maintenance Manual (EK-LA180-MM)
Microcomputer Interfaces Handbook (EB-20175-20)

767

LAV11/M7949
CAUTIONS

Switching — Switching the LA180 off-line while the operating

sys-

and
tem is running a program may resuit in the computer hanging
probThis
e.
continu
to
P
type
occurs,
this
If
m.
progra
the
ng
crashi
lem does not occur if the LPV11 is used in place of the LAV11.

LA180 to LAV11 Cable — The only acceptable cable for use between the LA180 and the LAV 11 is the BC11S. The end labeledd P2
must attach to the LA180. The end labeled P1 must be attache to
the LAV11.

LA180 Modifications — On the LA180 logic board (54-11023), jumper W6 must be inserted. This ensures +5 Vdc sense will read the

LAV 11. Failure to do so will result in a continued error condition in
the LAV11 LACS buffer. W6 is located between J2 and J3 on the
54-11023 module.

Miscellaneous Jumpers — For an LA180, the following jumper con-

figuration must be maintained.

Jumper Condition
W1
w2
W3
w4
W5
W6
W7

|
|
R
R
|
R
i

Function if Inserted
Transmit parity on line
+5 Vdc sense from LA180
+5 Vdc sense from LAV 11
DEMAND is asserted low
DEMAND is asserted high
P STROBE is asserted low
P STROBE is asserted high

The field replacement for the LAV11 (M7949) is the LPV11 (M8027).

768

LAV11/M7949

STANDARD

CONFIGURATION

ADDRESS

SW3

OFF

VECTOR
SWi

OFF
OFF

OFF

SW2

OFF

g | V!

—

D~ DD
G

ON
ON
ON

ON
OFF

ON
N.A.

STANDARD ADDRESS =17751X
VECTOR = 200

w7§we
-

g
{

| la3

swi

8 |

| |A7

A2 s

| VECTOR

{SELECTION _ _ | ADDRESS SELECTION_ __

JUMPER

LA180

CENTRONICS

W
w2
w3

I
I

I
R

w5
W6

I
R

KEY:
I = INSERT

R = REMOVE
LAV11 Jumpers

769

i1~-4146

LAV11/M7949
15

] |

]

{

]

l ]

]

l |

(82-1)

(s2-3)
Ad
($2-2)

A6
(S2-4)

{

{$2-5)
A8
($3-1)

A10
($3-3)

l |

(83-2)

A12Z
{83-5)

A1l

(53-4)

(S1-5)

(S1-3)

(S1-1)

(S1-6)

{S1-4)

81-2)

VECTOR SWITCHES

LOGIC 0= SWITCH ON
LOGIC 1=SWITCH OFF
MR-0815

[E:ROR[

DONE | IE

L(me BUSY

LAV 11 Control/Status Register (LACS)

LACS Bit Definitions
Bit

Function

Error - The error bit is asserted (1) when an error condition (i.e.,
torn or no paper) exists in the line printer. This is a read-only bit,
which is reset only by manual correction of the error condition.

14-08

Unused.

Done - The done bit is asserted (1) when the printer is ready to
accept another character. This is a read-only bit set by INIT. The
done bit is cleared by loading the LADB register. An interrupt sequence is started if IE (interrupt enable, bit 06) is also set.

770

LAV11/M7949
LACS Bit Definitions (Cont)
Bit

Function

IE - The interrupt enable bit is set or cleared (read or write bit)
under program control. It is cleared by the INIT (initialize) signal
on the LSI-11 bus.

(INIT is caused by programmed RESET instruction, console start

function, or a power-up or power-down condition.) When IE is
set, an interrupt sequence is started if either error or done is
also set.
05-02
01

Unused.

On Line - The on line bit is asserted (1) when the LA180 printer
(only) is on-line. Read only.

Busy - The busy bit is asserted (1) when the LA180 printer
(only) is performing a print or paper advance operation.

PRINTER

DATA

08
NOT USED

PARITY

DATA BITS
06-00
11-3931

LAV 11 Data Buffer Register (LADB)

LADB Bit Definitions

Bit

Function

156-08

Unused.

06-00

Parity - The parity bit is loaded with the data word if the parity

jumper is installed. Write only.

Data - The data comprises seven bits, with bit 06 being the
most significant. This buffered 7-bit character will be transferred

to the printer. These are all write-only bits.

771

LPV11/M8027

LPV11 LP05/LA180 INTERFACE MODULE

Bus Loads

Amps

+12
0

+5
0.8

AC
1.4

DC
1

Cables

BC11S-25 for LA180

70-11212-25 for LPOS

Standard Addresses
LPCS

177514

LPDB

177516

Standard Vector

Done or error interrupt 200

Diagnostic Programs

Refer to Appendix A.

Related Documentation

LP25 Line Printer Maintenance Guide (ER-OLP25-5V)
LPV11 Printer User’s Manual (EK-LPV11-OP)
LA 180 DECprinter | User’'s Manual (EK-LA180-OP)
LA 180 Field Maintenance Print Set (MP-LA180-00)
LA 180 DECprinter | Maintenance Manual (EK-LA180-MM)
LPO5 Technical Manual Model 2230 Line Printer (Dataproducts
Corporation)

LPV11-V Field Maintenance Print Set (MP00467)
Microcomputer Interfaces Handbook (EB-20175-20)
NOTE

The LPV11 (M8027) is a direct replacement for the LAV11
(M7949).

772

LPV11/M8027

V3
V2

=0 V5
véa

=0 V6

=oV8

w14

W13

///w12
W11

V2 o=t

V3 0=

V5 o=
Va4 o=p

V8 o=

VG o=f

——— W10

NOTE:

i =JUMPERS BROKEN FOR CLARITY ON THIS FIGURE.
THESE WIRE-WRAP JUMPERS WOULD NORMALLY BE
& USED TO REPLACE PREVIOUSLY REMOVED FACTORY
INSTALLED (W) JUMPERS (SHOWN INSTALLED).
o

=WIRE WRAP PIN.
MR-0863

LPV11 Jumpers

773

LPV11/M8027
BITS

DEVICE ADDRESS

{

FORMAT

{(BANK7 SELECTED)
l
FACTORY

CONFIGURATION

A1l

A 10

i I N R
RER
R

Ll
|
L
l

LPCS = 177514

= 177516
LPDB

Al2

T[T T]

(W3)

(wa)

(wz)

(FACTORY INSTALLED)

1=INSTALLED=LOGICAL=0
R=REMOVED=LOGICAL=1

LPV 11 Interrupt Device Address Format and Jumpers
BITS

VECTOR ADDRESS

FORMAT

FACTORY
-

CONFIGURATION

JUMPER

I=INSTALLED=LOGICAL O
R=REMOVED=LOGICAL 1

(FACTORY INSTALLED)

l l l l l l l
l’ l l l l’ l l
|

(Wia)

]

(W13) (W12) (W11) (W10}

]

(¥W9)

L PV11 Vector Address Format and Jumpers
LPV11 Jumper Definitions

Configuration
Designation | When Shipped | Function

Jumper

Al12
Al
A10

R
R
R

Jumper wires W2, W3, and W4 are factory installed to negate address bits 4, 5,
and 7, respectively.
This sets 177514 as the base address.

V8
V7

i
R

Jumper wires W9 through W14 are factory installed to negate vector bits 2, 3, 4,

5, 6, and 8.

This sets 200 as the interrupt vector.

774

LPV11/M8027
LPV11 Jumper Definitions (Cont)
Jumper

Configuration

Designation

When Shipped

Function

W1 installed to delay BRPLY L.

D
R

Supports both uppercase and lowercase

printing. For uppercase only, remove W7
and install T.

Do not configure the module with both
jumpers W7 and T installed.
Configured to transmit parity (bit 07) to
printer.

Parity Option

Jumper W8

Jumper P

Normal parity

Installed

Removed

Installed

bit

No parity,
bit 07 low

No parity,
bit 07 high

Do not configure the module with both
jumpers W8 and P installed.
NOTE

if the LPV11 interface module is used with an LPOS printer

equipped with the Direct Access Vertical Form Unit (DAVFU), it
is recommended that the user remove jumper W8. The LPOS interface module does not support the DAVFU Function.
F_

F+

W6 is installed at F+ to enable error fil-

ter operation with the LPO5.

For operation without the error filter, remove W6 and install a jumper at F—.
Do not configure the module with jumpers
installed at both F+ and F—.
The LA180 automatically enables the error filter circuit regardless of the jumper
configuration.

775

LPV11/M8027
15

(NOT USED)

ERROR

HEEER
—
(NOT USED)

{READ ONLY)
DONE

ON LINE

(READ ONLY)
INTERRUPT ENABLE

(READ/WRITE)

{(READ-ONLY)
BUSY

{(READ-ONLY)

‘

MR-0823

LPV11 Control/Status Register (LPCS)

LPCS Register Bit Functions
Bit

Function

Error - Asserted (1) whenever an error condition exists in the

line printer. Error conditions include the following.
LPO5 errors:

Power off

No paper

Printer drum gate open

Over-temperature alarm

PRINT INHIBIT switch off

Printer off-line

Torn paper

LA180 errors:

e
e

Fault (paper fault)
ON-LINE switch (in OFF position)

Reset by manual correction of error condition if LPCS bit 06 is

not set. If bit 06 is set, bit 15 is reset by manual correction of the
error and (1) reading the interrupt vector if the interface

“ready,” or (2) after reading the LPCS if the interface is ‘“‘not
ready.” Read only.
14-08

Not used. Read as Os.

776

LPV11/M8027
LPCS Register Bit Functions (Cont)
Bit

Function

Done LP0O5 - Asserted (1) whenever printer is ready for next
character to be loaded. Indicates that previous function is either
complete or has been started and continued to a point where

the printer can accept the next command. This bit is set by the
LSI-11 processor asserting BINIT L; if bit 06 is also set, an interrupt sequence is initiated. Also set by the printer when on-line

and ready to accept a character. Cleared by loading (writing
into) the LPDB register. Inhibited when bit 15 is set. Read only.

LA180 - Asserted (1) when the printer is ready to accept another character. Done is set by the LSI-11 processor asserting Bl-

NIT L and is cleared by loading (output transfer to) the LPDB
register. If the interrupt enable bit is set, setting done will initiate an interrupt request.
06

Interrupt Enable - Set or cleared by the program. Also cleared
by the LSI-11 processor asserting BINIT L. When set, an interrupt sequence is initiated if either the error or done bit is set.

05-02

Not used. Read as Os.

On-Line - Not supported and not required by DEC software.

Busy - Not supported and not required by DEC software. The following information is for reference only.

LA180 - Set when the LA180 prints a line or advances paper.
LPO5 - Not used. Read as O.

777

LPV11/M8027

LPDB

(NOT USED)

PARITY

OR D8

(OR PAPER
INSTRUCTION
AN

FOR LPOS5)
—

(READ/WRITE)
MR-0824

LPV11 Data Buffer Register (LPDB)

LPDB Register Bit Functions
Bit

Function

15-08

Not used. Read as Os. Data written into these bits is lost.

Parity or D8 - Optional use. Read as O.
LA 180 - Optional parity bit.

LP0O5 - Optional paper instruction bit. Not supported by the

LPV11 (read as 0).

06-00

Data - Seven-bit ASCIl character register. Characters are se-

quentially output to the printer buffer via this register. Read as
all Os.

778

LSI-11/2/M7270

LSI-11/2 PROCESSOR MODULE DESIGNATIONS

KD11-HA
KD11-HB
KD11-HC
KD11-HD

KD11-HF

KD11-HJ
KD11-HU
KD11-XA

KD11-XB
KD11-XC

KD11-XD

KD11-XH
KD11-XJ

Dual-height LSI-11 processor without memory
KD11-HA + MSV11-DB 8K word memory
KD11-HA 4+ MSV11-DC 16K word memory
KD11-HA + MSV11-DD 32K word memory
KD11-HA + MSV11-DA 4K word memory
KD11-HA + MMV 11-A 4K word core memory
KD11-HA + MRV 11-BA

KD11-HA, 2 MSV11-ED 64K word memory
KD11-HA, 4 MSV11-ED 128K word memory
KD11-HA, 9 MSV11-ED 288K word memory
KD11-HA, 3MSV11-DD
KD11-HA, 3MSV11-DC
KD11-HA, 3MSV11-DB

M7270 Specifications

Size:

Double-height module

Dimensions:

13.34 cm (5.25 in) X 22.8 cm (8.9 in)

Power:

+5 Vdc =5%, 1 A

Bus Loads:

AC - 1.7 unit loads

+ 12 Vdc + 5%, .22 A

DC - 1 unit load

Related Documentation

Microcomputer Processor Handbook (EB-18451-20)
KD11-HA Print Set (MP-00495)
LSI-11 Maintenance Card (EK-LSI11-MC)

779

(Heathkit)
(Heathkit)
(Heathkit)
(Heathkit)
(Heathkit)
(Heathkit)

LSI-11/2/M7270

[
S

EVNT INTERRUPT
- INSTALLED = DISABLE
REMOVED = ENABLE

MASTER CLOCK
W1
o 4| ENABLE

(ALWAYS INSTALLED)

E34

(KEV11 OPTION SOCKET)

CONTROL

j;l

lfi MICROM 1

{Si

MICROM O

DATA PATH

]

lfi

POWER-UP MODE
— SELECT

\ NOTE

TO DISABLE WAKEUP CIRCUIT,
REMOVE CAPACITOR C1 WHEN

USED WITH SEQUENCER POWER

SUPPLIES. (BA11-M AND BAT1-N)
MR-4574

M7270 Jumpers and Socket Locations

780

LSI-11/2/M7270
Jumper
W1

Always installed - master clock enabled.

Removed - external event interrupt (line clock) enabled.
Installed - external event interrupt disabled.

Mode Selected

PC at 24 and PS at 26, or halt mode (mode 0).

ODT microcode (mode 1).

PC at 173000 for user bootstrap (mode 2).
Special processor microcode; not implemented (mode 3).

Diagnostic Programs

The following diagnostic programs are for use with LSIl-11 processors except for the limitations noted.
VKAA??

LSI-11 basic instruction test.

VKAB??

L.SI-11 Extended Instruction Set (EIS) test. This program can be
run only on LSI-11 CPUs with the KEV 11 (EIS/FIS) or KEV11-CA

(DIBOL instruction set) options installed.
VKAC??

VKAD??

LSI-11 Floating Point Instruction (FIS) test. This runs only on LSI-11
CPUs that have the KEV11 (EIS/FIS) option (23-003B5).

LSI-11 traps test. This diagnostic auto-sizes for the EIS, FIS,

and DIBOL options.

Older versions (Rev B1 and below) require the setting of a
bit in the software switch register if EIS, FIS, or DIBOL is
present.

Rev A diagnostics will not run on D322 or D324 systems be-

cause of the DIS instructions.
NOTE

See Appendix A for XXDP+ multimedia assignments.

VKAH??

Basic system exerciser. Tests serial line unit, memory, processor, EIS/FIS, clock, and both floppy disks under various conditions. Software switch register must be set for options.

*R = jumper removed; | = jumper installed.

781

LSI-11/2/M7270

Chip

Vendor Number | DEC Number |Vgg | Comments

DATA

CP 1611 B-39

CONTROL
MICROM-0

CP 1621B-173
CP 1631 B-103

MICROM-1

21-11549-01 | —3.9

21-156579-00 | —3.5 | With ECO 6

23-002C4

—3.9 | 2007 pattern

CP 1631B-073

23-001B5
23-002B5

—3.9
—3.9

CP 1631 B-135

23-003B5

—3.9

EIS/FIS

(if present)

KEV11-A

ECOQOs for Etch Rev E

CS Rev | ECO No. | Change

1. Remove blanking pulse.
2. Generate clock driver V.. from +12 V.
3. Move K1 MSTB L from E34-3 to E34-4.
4. Relayout board.

Change C31

and C32 from

10-12312-01 to

10- 10279-0.

Change Augat socket to Burndy socket.

Allow customer to remove C81.

Change R18 from 13-10317 to 13-10522.

Alternate part 19-14282-01 may be used to replace
E37.

Change part E30 from 21-11549-01 to 21-15579-00.

782

MCV11-D/M8631

MCV11-D CMOS READ/WRITE MEMORY

GENERAL
MCV11-D Modules

Memory

MOS

Model

Capacity

Chips

Module

MCV11-DA
MCV11-DC

8K bytes
32K bytes

2K X 8

M8631-A

2K X 8

M8631-C

Diagnostic Programs

Refer to Appendix A.
Related Documentation

MCV11-D User’s Guide (EK-MCV 1D-UG)
MCV11-D Reference Card (EK-MCV1D-RC)
Field Maintenance Print Set (MP-DDM8631)

783

Number

of Chips

MCV11-D/M8631
MCV11-D Power

MCV11-DC (32K byte)
Data

Current
and Power

Active
Mode

Current

+5V (Typ)*

1.23 A

Power

+5 V (Typ)
+5V (Max)

11.34W{

2.16 A
+5V (Max)*
+5VBBU (Typ)t | 1 mA
+5VBBU (Max)t | 2 mA

6.20W|

Standby | Retention
Mode
Mode
1.22 A
2.15A
1 mA
2 mA

0
0)
9 mA
14 mA

6.10W | .045W
073 W

11.29 W

MCV11-DA (8K byte)

Current

Power

1.20 A

1.19 A

2.09 A
+5VBBU (Typ)t | 1mA
4+5VBBU (Max)t | 2 mA

2.08 A

0
0]

1 mA
2 mA

9 mA
14 mA

+5V (Typ)t
+5V (Max)*

+5V Typ
+5 V Max

6.00 W

595 W

045 W

10.97 W{

10.92 W

073 W

* The +5 V current is recorded with no+5 V BBU supply
connected.

+ The +5 V BBU current assumes +5V = 4.75V and +5V
BBU = 5.25 V. In the active and standby mode, a majority of
current comes from the +5 V supply, so it appears as
though very little current is required by the +5 V BBU supply. In the data retention mode, the +5 V supply is assumed to be at 0 V. The current supplied by +5 V BBU is
used to trickle charge the batteries. If the batteries were
disconnected, +5 V BBU would be typically 20 uA.

oOhwN=

CONFIGURING THE MCV11-D MEMORY MODULE
There are five groups of MCV11-D memory module jumpers.
Module starting address jumpers
System selection jumper
Manufacturing test jumper

Memory |/0O page address jumper
Memory module battery backup jumper

784

MCV11-D/M8631

BATTERY
CONNECTION

W X
c

H
|
P ERI

]

PINSU o

—

SHERAL ADDRESS []]]
V [-]

]

(BOTTOM 2K) USED

AS MEMORY ADDRESS

)

PINS Y o

7 0

BATTERY
HOLDING CLIP

| ]

D
B

| —_
|
STARTING

| LH-NC

ADDRESS '_H:l

, B-32K

°L—1M

°D-8K

M-512K

o C—-16K

o E—4K

oN—256K

o F—1

°R-1

, TEST ONLY

°oP-128K

—J

JPINSS

A-64K

0oJ=SM SYS H]
o K—NC

ki
|

MR- 8646

MA-9595

MGV 11-D Module Layout

785

MCV11-D/M8631
Module Starting Address (MSA) Jumpers

To configure the MSA jumpers, you need the module starting address.
EFrom the module starting address you can obtain the necessary data to
configure the jumpers.

The first address of range (FAR) selects the first address of the 128K range

the starting address falls in.

The partial starting address (PSA) selects which 4K boundary within a specific 128K range the starting address falls in.

You can find the memory module starting address (MSA) by determining
how much memory the system has in decimal K words. This word value is
the MSA.

To jumper the module starting address (MSA), proceed as follows.
Known

PSA = MSA — FAR

First Address of Range

Partial Starting Address

First Address of Range (FAR)
Jumpers In (X)
to Ground (R)

Decimal (K)
000-124

128-252
256-380
384-508
512-636
640-784
768-892
896-1020
1024-1148

Octal

00000000-00760000

01000000-01760000
02000000-02760000
03000000-03760000
04000000-04760000
05000000-05760000
06000000-06760000
07000000-07760000
10000000- 10760000

X
X
X
X

11562-1276

11000000- 11760000

12000000- 12760000
13000000~ 13760000

X
X

1536- 1660
1664-1788
1792-1916
1920-2044

14000000- 14760000
15000000- 15760000
16000000- 16760000
17000000- 17760000

X
X
X
X

X
X
X

X
X

1280-1404
1408-1532

786

X
X

X
X
X
X
X
X

X
X

MCV11-D/M8631
Partial Starting Address (PSA)

Jumpers in (X) To

Ground (F)

Decimal (K)

Octal

00000000

00020000

00040000

00060000

00100000

20
24
28
32
36
40
44
48
52
56

00120000
00140000
00160000
00200000
00220000
00240000
00260000
00300000
00320000

X
X
X
X
X
X
X
X

00340000

00360000

00400000

68
72
76

00420000
00440000
00460000

X
X
X

80
84
88

00500000
00520000
00540000

X
X
X

92
96
100
104
108
112
116
120
124

X
X
X

X
X
X
X

X
X

X
X
X
X
X
X
X
X
X

00560000
00600000
00620000
00640000
00660000
00700000
00720000
00740000
00760000

787

X
X

X
X
X
X
X

X
X
X

X
X
X
X
X

X
X

X
X
X

X
X

MCV11-D/M8631

Module Starting Address (Example - 352K Words)
Names
Decimal k words

Binary address
Values

First Address

Partial Starting

1Meg 512K 256K 128K

64K 32K 16K 8K

Address (PSA)

of Range (FAR)

BDAL

BDAL bits

Jumper pin

names

Jumper pins

AtoB,BtoF

NtoR

System Selection Jumper

Small/large system selection is set by the condition of jumper pin J. Small

systems use 16- or 18-bit addressing, with pin J open. Large systems use
22.bit addressing, with pin J wrapped to pin R.
Manufacturing Test Jumper

This jumper, when installed (pin T to pin S), allows addresses to start at
128K. The jumper is installed during manufacturing test. When the modules
leave manufacturing test, the jumper is removed.

Memory |/0 Page Address Jumper

When a customer wants to use the bottom 2K of the 1/0 space as a memory address, jumper U to V.

Memory Module Battery Backup Jumper

When you receive an MCV11-D memory, there will be two 1.2 V rechargeable nicad batteries. Pins Y and Z are the clip carrier pins (no electronic
function): they should have a clip across them. Remove the clip.and connect it across pins W and X. This installs module battery backup.

788

MRV11-AA/M7942

MRV11-AA READ-ONLY MEMORY

PROM/ROM

module will

accept up to

16 customer-supplied

erasable

UVPROMs, fusible link PROMs, or masked ROM devices.

Amps

Bus Loads

W/O0 PROMs

—12

0.4

1.84

1.0

2.8

Cables

none

(0.6 max.)
With PROMs

(4.1 max.)

Standard Addresses

Module is shipped with all jumpers installed, selecting bank O addresses
(0-1777).

Vectors, Diagnostic Program, Exerciser Program
None

Related Documentation

Field Maintenance Print Set (MP00066)

Microcomputer Processor Handbook (EB-18451-20)

NOTES

14 select chip set types (512 or 256).
Jumpers W8-W

Any row not populated with PROMs must have the BRPLY L

jumper (WO-W7) removed.

789

MRV11-AA/M7942
MRV11-AA Address Word Formats
Bank Select

Bank

W15

W16

W17

0
1
2
3
4
5
6
7

|
E
|
|
R
R
R
R

I
|
R
R
|
|
R
R

l
R
i
R
i
R
|
R

NOTE

Because of addressing limitations, this module is not compatible with PDP-11/23 systems with more than 64K bytes of
memory.

512 X 4

PROM/ROM r ]
L
CHIPS
W5 | Wiy
W16

|
|
4096 — LOCATION ADDRESS

(W8—W10 INSTALLED; W11-W14 REMOVED)

] [
BYTE

POINTER

[

4K ADDRESS

SPACE JUMPERS

X 4
256

PROM/ROM
/ E

CHIPS

W15

L
L |o
|

l W17

W16

—

4K ADDRESS

SPACE JUMPERS

| _

2048 — LOCATION ADDRESS

L {

BYTE

(W11 AND W12 INSTALLED: W8-W10 REMOVED) pOINTER
HIGH/LOW 2K SELECT
W13 INSTALLED:

LOW 2K (0—-7777)
W14 INSTALLED:

HIGH 2K (1000-17777)
MR-5427

MRV 11-A Address Word Format

790

MRV11-AA/M7942

o
4

3-0

| ¢

] ce7

| e

| ces

_Je

| ces

| ¢

] e

| cea

| ¢

| ces

| ¢

| ce2

| &

| cE

| ¢

| ceo

i
=z

M7942 ETCH REV. D

M7942 Etch Rev D

791

(
MMMMMMM

MRV11-AA/M7942
512 by 4-Bit PROM Addresses
Bank Address

T
DT
T~ 3~

DIV~
T DIV

Jumpers

Word/Byte

Physical

BRPLY L

Address

Row

Jumper
WO

0-1777

CEO

2000-3777
4000-5777

CE1

CE2

6000-7777

CE3

10000-11777
12000-13777

CE4

CE5S

14000~ 15777
16000-17777

CE®6

CE7

256 by 4-Bit ROM Addresses
Bank Address

Word/Byte Address

Jumpers

R
R
|
|

R
R

Physical

BRPLY L

Row

Jumper

100000-107776

CEO

10000-17776

110000-117776

CE2

20000-27776

120000-127776

CE4

30000-37776

130000-137776

CE®6

40000-47776

140000-147776

CE1

50000-57776

150000-157776

CE3

60000-67776

160000-167776

CE5

70000-77776

170000-177776

CE7

W13 Removed

W14 Installed

W17 W14 Removed

DIV DID~
— 7~

W16

W13 Installed

W15

0-7776

BRPLYL Select

Empty Row | Remove Jumper
CEO

CE1

CE2

CE3

CE4

CES

CE®6

CE7

792

MRV11-BA/M8021

MRV11-BA ULTRAVIOLET PROM-RAM
The MRV11-BA is a high density multifunction module with two independently
configurable, asynchronous serial lines which are compatible with RS232-C and

RS-423.

Amps

W/0 PROM

Bus Loads

Cables

+ 12

0.58

0.34

2.8

1.0

(0.67 max.)
With

0.62

PROMs

(0.744 max.)

None

(0.41 max.)
0.5

(0.6 max.)

Standard Addresses
RAMs

20000-20777

PROMs

140000-157777

Standard Vectors
None

Diagnostic Programs
Refer to Appendix A.

Related Documentation

MRV 11-BA LSI-11 UV PROM-RAM User’s Manual (EK-MRV 11-TM)
Field Maintenance Print Set (MP00354)
Microcomputer Processor Handbook (EB-18451-20)

Recommended PROM Types

DEC MRV 11-BC Intel 2708

(DEC PN 23-00087-01)

1024 X 8-bit, MOS, tri-state, erasable,

ultraviolet (24-pin DIP)

793

MRV11-BA/M8021

HIGH BYTE

1K © 4TH 1K
3rD

1sT1K

2ND 1K
PROMS

PROMS

E29

E19

E14

E28

E18

E13

PROMS

LOW BYTE

PROMS

—

oo W22

W20 } RAM ADDRESS
OO0 D
ot

O—FO W18 BANK7 ENABLE

o-L_towi7

PROM
ADDRESs |\ = o W18
PROM

OO0 w14

o0 W13

ENABLE ) OO w12
oL—ro w11

RAM DISABLE OO W10
o0 we
OO W8

RAM

o0 W7

PROM

O FOwa
O 3-OW3
oL
O W2

ADDRESS § OS=0OWweé
3O W5
ADDRESS \ OO w1
oo w21

MR-0822

MRV 11-BA RAM Addressing

794

MRV11-BA/M8021

BITS —& 17

JUMPER —B» W3

W13

w20

———d

L___Y__J

el T I LTI TP P
T e
l

CIRCUITS

(2561013778] WORDS)

BYTE POINTER

FACTORY

CONFIGURATION

—

22K SELECT
1=0
R =1

4K AND 1K

256 WORD

SELECT

R=I

R=0

(DATOB BUS CYCLES ONLY)

0=WRITE LOWBYTE {(0:7)

1=WRITE HIGH

DECODED BY ADDRESSING
AND CONTROL LOGIC

NOTES:

1. Factory configured address range = 20000 — 20377
2. | = Jumper instalied; R = Jumper removed

3. W10 removed = RAM ENABLE
W10 installed = RAM DISABLE

MR-5536

MRV 11-BA RAM Addressing

BITS —& 17

JUMPER —& Wi

W15

W17

Wi6

fifif*{ll HEEEEEEEEEEEEEEEE
DECODED BY PROM

rACTORY

CONFIGURATION

|32_KOSELECT
R=1

ERRE.
’ l l |

INTEGRATED CIRCUITS

PROM SIZE (1K WITHIN 4K BANK)
DECODED BY ADDRESSING AND

CONTROL LOGIC. 1K SEGMENTS
ARE ENABLED VIA W11-W14:

PROM JUMPER CONFIGURATION
SIZE

W11 | W12 | W13 1 w14

R=0

]

4K SELECT

NOTES:

1. Factory configured address range = 140000-157777
2. 1 = Jumper installed R = Jumper removed

MR-5537

MRV 11-BA PROM Addressing

795

MRV11-BA/M8021
RAM Addressing Summary

Memory Jumper Configuration
(I=Installed; R=Removed)

046000-046777
047000-047777

o
Bt o B
o Bt
o
© Bt o Bt o B
o Bt o B
¢ B
s
v
o Eabs o B
s

oM o B

o Mo o B

o oo M

o Ao o

o Mt o M

o s o)
« oo B
s

oM o B

B
«M « so s
s
o Mo o s o s o
s

s
« ss
s
E
s s

=
=
= =
=
=
—

796

0 E= o Es &

044000-044777
045000-045777

S RSU A

043000-043777

041000-041777
042000-042777

040000-040777

036000-036777
037000-037777

035000-035777

033000-033777
034000-034777

= m otk bk

031000-031777
032000-032777

NRNNNNORONN =

027000-027777

030000-030777

o so B o B o

025000-025777
026000-026777

024000-024777

« s o B o so B

023000-023777

021000-021777
022000-022777

BY RIS Y R & e §

020000-020777

-~~~ —JPIITIIVIIVDII
———

017000-017777

015000-015777
016000-016777

TITITIIIID

013000-013777
014000-014777

011000-011777

012000-012777

TTTTTI13IIVIVIIIVIIVIIIITIIIVITIIIDDOO

006000-006777
007000-007777
010000-010777

004000-004777
005000-005777

= =

002000-002777
003000-003777

e e e e e

000000-000777
001000-001777

Bank W3 W4 W5 W& W7 W8 W9 W19 W20
2w OO000000000O0O0O0O00O

Range (Octal)

b bkt

Address

MRV11-BA/M8021
RAM Addressing Summary (Cont)
Address

Memory Jumper Configuration
(I=Instalied; R=Removed)

114000-114777
115000-115777
116000-116777
117000-117777

D
VT
VT
VT
DT
0T
T

DT DD
DTN
T I TV TV

IVIDT T IO
T
DV
T T

& i ¢
N
S § s ©
& Jw ¢
¥ R ¢ R
o o & RN

T VXV
T T T
T T
-

¢ i ¢ o ¥ i ¢
N
¥ [ 6 Bs v s ¢

VIV IDDVIDVIDD
- T T T

IDIDT T T
TN

T T T T
T
ILT T
XXV

T
T T T

DIV IDIVODIDD

797

DT T

112000-112777
113000-113777

110000-110777
111000-111777

106000-106777
107000-107777

s o B« Rhamibe v Bbs o

104000-104777
105000- 1056777

po el o lis o Bhanisle © Bw v Hbs o R ¢ B

102000-102777
103000- 103777

T T T T

100000~ 100777
101000-101777

IDDDT T

076000-076777
077000-077777

073000-073777
074000-074777
075000-075777

B s Bs s s s s s s s s s B o s s lis s lis o

070000-070777

071000-071777
072000-072777

il s B ¢

066000-066777
067000-067777

064000-064777
065000-065777

—————— — == — — —

063000-063777

062000-062777

060000-060777
061000-061777

056000-056777
057000-057777

055000-065777

054000-054777

053000-053777

|
i

052000-052777

I DT

051000-051777

WwwwhhnhhNDNDMDNDND

050000-050777

Bank W3 W4 W5 W6 W7 W8 W9 W19 W20

D H D DDLDDEDLEDDLELEDDDLELELEDDDADOWOLOOWMOLWLWWWOW

Range (Octal)

MRV11-BA/M8021
RAM Addressing Summary (Cont)

157000-157777
160000- 160777

161000-161777 | 7°
162000-162777 | 7°
163000-163777 | 7°
164000-164777

| 7°

165000-165777

| 7°

166000-166777 | 7*

— XTIV
TV
DD
W
VT D

VD
T
VDD
T
T/
DI

DD
T
T VDIV
T T T

— T

IDD
TV

VDI~ D—D
DT DT
TV
-D

155000-155777
156000- 156777

T DTV

1563000-153777

154000-154777

151000-151777
162000-152777

147000-147777

150000-150777

146000~ 146777

145000-145777

143000-143777
144000-144777

s s B « Mo Bt

142000-142777

140000-140777
141000-141777

o boB oM « B

137000-137777

136000-136777

v Jis vt v

134000-134777
135000-135777

pulie s lis o lie o e s lie v Bie s B 0 R

133000-133777

& o o e v liw » i o s » lis o s s B

132000-132777

[

131000-131777

VD VVIODVDDVDITDDIODIDDDDIDITDODIDD

130000-130777

PIDIII
D~ ——————————— — — — —

127000-127777

LDV DVDIVDIVVIVDIDDIDIOVDDITDIDDDDDDIDIDD

125000-125777
126000-126777

DN VDVDDIVDIOVDIDOVDIDIDDODVDIDIODIDIDID

123000-123777
124000-124777

VDDV VDTIVITITDDDITIDIDIDDDITIDDIDDIDD

122000-122777

OO OOt
Oor OO

120000-120777
121000-121777

Bank W3 W4 W5 W6 W7 W8 W9 W19 W20

Range (Octal)

Memory Jumper Configuration

(I=Installed; R=Removed)

1@@@@@@@@@0’)@@@@@@

Address

*The bank 7 enable jumper W18 is factory installed to allow addressing in

bank 7.
798

MRV11-BA/M8021
RAM Addressing Summary (Cont)
Address

Memory Jumper Configuration
(I=Installed; R=Removed)

171000-171777

172000-172777

173000-173777

174000-174777

175000-175777

176000-176777

177000-177777

R
fi

!
E

R
R
R

o~
0T

T T VDT
T BT

170000-170777

L0000V 0DVIVIT—

167000-167777

L IVIVIVIVDITIODIDD

W3 W4 W5 W6 W7 W8 W9 W19 W20
L0V I0DIWVWIOD

Bank

DIDVDILVIDVDIOVITVIDIDD

Range (Octal)

|
R
I

*The bank 7 enable jumper W18 is factory installed to allow addressing in
bank 7.

799

MRV11-BA/M8021
NOTE

the
The following jumper configurations illustrate configuring preaddress range in banks above bank 7 (not implemented in W20
sent LSI-11 system configurations). w8, W9, W19, and
can be configured as shown in the preceding pages to select
the desired segment within the bank.

Memory Jumper Configuration

800

=3
v B

& B

o B

o Es o B

& B

o B

e
0 HE
s
o

o so eo s B
oB oB & B & B

5U R

o His o Binniinlils o Bis s Miuuaiinnils s Bis v Miumiianails o Hiw o Hnniiianslibs v B o Bhanuli

760000-777777

59 Jis o Ml

s e w Jio v B

720000-737777

740000-757777

13
14
156
16
17
20
21
22
23
24
25
26
27
30
31
32
33
34

- ~-7ITDIODVDIVDIIDVIT

260000-277777
300000-317777
320000-337777
340000-357777
360000-377777
400000-417777
420000-437777
440000-457777
460000-477777
500000-517777
520000-537777
540000-557777
560000-577777
600000-617777
620000-637777
640000-657777
660000-677777
700000-717777

10
11
12

200000-217777
220000-237777
240000-257777

Bank

—

Range (Octal)

(I=Installed; R=Removed)

VIV
—— —————

Address

MRV11-BA/M8021
PROM Addressing Summary
Memory Jumper Configuration

Address

(I = Installed; R = Removed)

30
31
32
33
34
35
36
37

addressing in

bank 7.

801

VDT DD

DIT T DD

VDTV

T
TV
TV

VDIDIDD
T T T

*The bank 7 enable jumper W18 is factory installed to allow

T IITTITIDTID TV T

600000-617777
620000-637777
640000-657777
660000-677777
700000-717777
720000-737777
740000-757777
760000-777777

W16

540000-557777
560000-577777

23
24
25
26
27

"IV

460000-477777
500000-517777
520000-537777

420000-437777
440000-457777

T TV

156
16
17
20

340000-357777
360000-377777
400000-417777

" DI

260000-277777
300000-317777
320000-337777

I
10
11
12
13

160000-177777
200000-217777
220000-237777
240000-257777

r»TIPTIPIVITITLOD
T TV
T T T T T T T

140000-157777

NI~ ———————=———
—
— — —

120000-137777

IDIIDI

060000-077777
100000-117777

W15

VDI

=
WN

040000-057777

000000-017777
020000-037777

W17

Bank

Range (Octal)

MRV11-BA/M8021
PROM Addressing

AddressTM
Octal Binary
0
2

4
6
10
12

10 09 08 07 06 05 04 03 02 O1|Address Bits
22231 2 3 4 5 6 7 8 |PROMPins

00000OOOOOOOIL
000000000O10JL

00000000100|L
00000000110iL
0000000O1000O|L
00000001010]L

L
L

L
L
L
L

L
L

L
L
L
L

L
L

L
L
L
L

L
L

L
L
L
L

L
L

L
L
L
L

L
L

L
L
H
H

H
H
L
L

L
H

L |Actuallogic
H |LevelsRequired
L
H

(10244
|Locations)

3776 11111111110)jH

*Bus address bit O is not used. Therefore, only even-numbered addresses
are shown.

802

MRV11-C/M8048

MRV11-C READ-ONLY MEMORY MODULE

The MRV 11-C is a flexible, high-density ROM module used with the LSI-11
bus. The module contains 129 wirewrap pins and 16 24-pin ROM chip sockets that use a variety of user-supplied ROM chips. Masked ROMs, fusible
link ROMs and ultraviolet erasable PROMs are acceptable to use. The
MRV 11-C is shipped without jumpers installed.

Using 4K X 8 ROM chips, the total capacity of one M8048 module can be
64K bytes, accessible either by direct access or window mapping.

Bus Loads

Amps
+5

+12

0.8

Cables
None

(plus ROM chip power)

Standard Addresses

Recommended window starting address 760000

Bootstrap starting address: 16-bit system 173000; 18-bit system 773000

Technical detailed information is beyond the scope of this manual. Additional information can be found in the Microcomputer Processor Handbook,
EB-18451-20.

Related Documentation

MRV11-D Universal PROM Module User Guide (EK-MRV1D-UG-001)
Field Maintenance Print Set (MP-00871)

803

MRV11-C/M8048
Compatible UV PROMs (Ultraviolet)

UV PROMs

Chip Array Size

Maximum Memory Size

intel 2758
intel 27 16
Intel 2732
Mostek MK2716
T.1. TMS 2516
T.1. TMS 2532

1K X 8
2K X 8
4K X 8
2K X 8
2K X 8
4K X 8

16K bytes
32K bytes
64K bytes
32K bytes
32K bytes
64K bytes

Compatible PROMs

PROM

Chip Array Size

Maximum Memory Size
16K bytes
16K bytes
16K bytes
32K bytes

1K X 8
Intel 3628
Signetics 825 2708 | 1K X 8
1K X 8
Signetics 825 181
2K X 8
Signetics 825 191

804

MRV11-C/M8048

S
1

NEPZ:
T S O eT

127 —1 4

nze__|

XE44

J125\\i

CHIP

1124 —

SET O

23—

HIGH

12—
121 ——A

BYTE

]

250080

B ey B e O ey
XE38

XE32

CHIP

XE26

Ny WP

SET 3

181 \i o

BYTE

S L
J75;)\ L —J72

S
.

XE31
CHIP

XE25
CHIP

165~
i—1_ 63
62 AT
61

LOW

158 —AA—1—J57
156

HIGH

183
A A A

J79 —A x| -I76

J73

J117 —

J‘HG\:i
1115 ——2X

XE43
CHIP

1114 ——A

n—ta
J112/;*
A

XE37
CHIP

SETO

SET 1

SET 2

SET 3

BYTE

LOW

BYTE

LOwW

BYTE

LOW

J66__

168

160

J105

11087 gy
X

J103//’l‘

—

“09;//}\

107”7

AL JBT

455 AA——
J54

J108° A 4~

~1 70

A—— J69

/)K

J106 74 A

CHIP

SET 2

CHIP

—

g —A

J111

186

188XA 17 1ga
8o

SET 1

J120 —

19—

J110°7

189

J87\

XE42

CHIP

SET 4
HIGH

BYTE

!
XE36

CHIP

=
XE30

CHIP

—T—J53

g A—f— I51

A —— Ja9

J48 —— ) U]
1846 —— RN Ja7

42—

SET 6

SET 7

BYTE

HIGH

150

XE24

CHIP

SET 5
HIGH

J52

HIGH

AATu4s

{43

A
T4

J38Ai\§J4O

J1g;?//i

J35 AR

”00/7*

JazAfi\\JS

JQQ/

129 A

J98

XE41

XE35

CHIP

LOW
BYTE

SET 4

SET 5

XE29

XE23

939

433

124 st*A%\

CHIP

J23\)\

231

LOW
BYTE

21—

J28

SET 6

SET 7

122 A

430

120 —— —A

N9—"2

J27

18—
A
Jg97

——

J13/)\

J11

95 ———A
J94

]
J93/

192

j?g

J17/i i//
J15§i i//jlg
1

196
— |
I

134

N
A

J5—)

A
J—

A——18

—1—J6
Ja —A

J91

J—}—13

A—— 180

i——sz
——
1

NOTE:

SEE TABLE 16 FOR WIREWRAP PIN IDENTIFICATION.

MRV 11-C Wirewrap Pin Locations

805

MR-3083

7m_:ALFOVIHILNI|bytmam\wm4g6zer0ztMO1G0NI8M‘LLLrIpTL,LCPVL%
\verlYzr807037s8V3YNy3aqy¢8ALyGiir9LLr,\

\-],¥SDS},—3oYA1188Y¢L3&\’1188wo.o—mLGi[1itgitrror49vmN9Iizm}ofrr,olxmlf1ml.8,%3wS13HMH01O3I4IdAH8lIHaG_A\|GP1NHg-A—Se—Lyg43a0903gdL3?l0rIloOf—ZmAyLu_rib—)o0(30HOWaN\“
1008

%
ver

1AHIN2|34D1-01UoIBINBIUODSUO1}08UU0D481U| B
W 097¢€

\[6r96r 7&7Li188oo——17oglZergb—oTs 3LAE paVASS8 iz0—93eL0r0pZ—L=r©0093)0007
MRV11-C/M8048

aNY

WM]mv.%m16lxm380u <£os—g591—QA-vo M“WN.m8!0.Z_.Ur“m_Qctav

€ZB6r

806

MRV11-C/M8048

WINDOW

MAPPING

ADDRESS

DIRECT

MODE

CONTROL

__
“MEMORY
-

STATUS
REGISTER

SizE

16K

32K

BYTES

16K

BYTES

32K

BYTES

64K

BYTES

64K

BYTES

DIRECT

BYTES
T

ADDRESSES

WINDOW
MAPPING

ADDRESSES

YES

“MEMORY
_

INCOMPLETE

MEMORY

16K

BYTES
l

ROM CHIPS

CHIP

SIZE

’

32K

BYTES

84K

BYTES
j

ASSIGN

ACCESS TIME

STARTING

ADDRESS

l
DATIO BUS
CYCLES

END
MR-3879

Configuration Procedure

807

MRV11-C/M8048
Wirewrap Pin Identification
Wirewrap Pin

Designation

Function

RXCX pull-up resistor
RXCX optional capacitor

J3
J4

J5
J6

J7
J8
J9
J10

J11
J12

J13
J14

J15
J16

J17
J18
J19
J20

J21
J22

J23
J24

J25
J26
J27
J28

RXCX signal

LMATCH input for BDOUT control
LMATCH for BDOUT control
Window address enable ground

Window address enable
High byte chip enable bit A11
CSR high byte bit 8 chip enable output
High byte chip enable bit A12
CSR high byte bit 9 chip enable output

High byte chip enable least significant bit
CSR high byte bit 10 chip enable output
High byte chip enable intermediate bit
CSR high byte bit 11 chip enable output
High byte chip enable most significant bit
CSR high byte bit 12 chip enable output
Boot address chip enable bit A11

Boot address chip enable bit A12

Boot address chip enable least significant bit
Boot address chip enable intermediate bit
Boot address chip enable most significant bit
Boot address chip enable ground reference
Boot address chip enable 5 V reference
Direct address bit 11 chip enable output
Low byte chip enable A11 bit
CSR low byte bit O chip enable output
Direct address bit 12 chip enable output

J32

Low byte chip enable A12 bit
CSR low byte bit 1 chip enable output
Direct address bit 13 chip enable output
Low byte chip enable least significant bit

J33

CSR low byte bit 2 chip enable output

J34

J35

Direct address bit 14 chip enable output
Low byte chip enable intermediate bit

J36

CSR low byte bit 3 chip enable output

J29
J30

J31

J37

Direct address bit 15 chip enable output

J38

Low byte chip enable most significant bit

J39

CSR low byte bit 4 chip enable output

J40

Reserved for future DIGITAL use.

J41

Window address bit 15 compare ground

J42

Window address bit 13 compare input

J43

Window address bit 12 compare ground

808

MRV11-C/M8048
Wirewrap Pin Identification (Cont)
Wirewrap Pin

Designation

Function

J44

Window address bit 14 compare input
Window address bit 14 compare ground
Window address bit 15 compare input
Window address bit 16 compare ground
Window address bit 16 compare input

J45

J46
J47
J48

J49
J50

J51
Js2
J53

J54
J55

J56

J57
J58
J59
J60

1
J6
J62
J63

J64
J65
J66

J67
J68
J69
J70

J71
J72

J73

J74
J75

J76

J77
J78

J79
J80

J81

J82
J83

J84
J85
J86

Window address bit 13 compare ground
Window address bit 17 compare input
Window address bit 17 compare ground
Window address bit 12 compare input
Direct address 32K memory limit output
Direct address 16K memory limit output
Direct address memory limit input
Direct address 8K memory limit output
Direct address bit 17 compare ground
Direct address bit 16 compare input
Direct address bit 16 compare ground
Direct address bit 17 compare input
Direct address bit 15 compare ground
Direct address bit 15 compare input
Direct address bit 14 compare ground
Direct address bit 14 compare input
Direct address bit 13 compare ground
Direct address bit 13 compare input
CSR high byte bit 15 enable ground
CSR high byte bit 15 enable input

High byte chip enable window address function
High byte chip enable direct address function
High byte chip enable function select drivers

Bit 7 chip select enable input
Bit 7 chip enable decoder output
Bit 6 chip select enable input
Bit 6 chip enable decoder output
Bit 5 chip select enable input
Bit 5 chip enable decoder output

Bit 4 chip select enable input
Bit 4 chip enable decoder output
Bit 3 chip select enable input
Bit 3 chip enable decoder output
Bit 2 chip select enable input
Bit 2 chip enable decoder output
Bit 1 chip select enable input
Bit 1 chip enable decoder output
Bit O chip select enable input

809

MRV11-C/M8048
Wirewrap Pin Identification (Cont)
Wirewrap Pin

Designation
J87
J88
J89
J90

JO1

J92
J93
JO4

J95
J96

J97
JO8

J99
J100
J101

J102
J103

J104

J105
J106
J107
J108
J109

J110
J111

J112
J113

J114
J115
J116

J117
J118

J119
J120
J121
J122
J123

J124
J125

J126

Function

' Bit O chip enable decoder output
Boot address enable ground
Boot address enable

DAL 4 CSR address select signal
DAL 4 CSR address select ground
DAL 1 CSR address select signal
DAL 1 CSR address select ground
DAL 2 CSR address select signal
DAL 2 CSR address select ground
DAL 3 CSR address select signal
DAL 3 CSR address select ground
Pin 18 input for chip set 5

Chip wirewrap interconnection for chip set 5

Pin 20 input for chip set 5 (chip enable 5)

Pin 18 input for chip set 4

Chip wirewrap interconnection for chip set 4
Pin 20 input for chip set 4 (chip enable 4)
Pin 18 input for chip set 6

Chip wirewrap interconnection for chip set 6

Pin 20 input for chip set 6 (chip enable 6)
Pin 18 input for chip set 7

Chip wirewrap interconnection for chip set 7
Pin 20 input for chip set 7 (chip enable 7)

Reserved for future DIGITAL use.
ROM interconnection, ground reference

Chip enable bit bus input

Address bit A11, used as chip input A10

Chip interconnection loop (to wirewrap pins)

Address bit A12, used as chip input A11
Chip interconnection loop for chip pin 21
ROM interconnection +5 Vdc voltage reference

Pin 18 input for chip set O

Chip wirewrap interconnection for chip set O

Pin 20 input for chip set O (chip enable 0)

Pin 18 input for chip set 1

Chip wirewrap interconnection for chip set 1
Pin 20 input for chip set 1 (chip enable 1)
Pin 18 input for chip set 2
Chip wirewrap interconnection for chip set 2
Pin 20 input for chip set 2 (chip enable 2)

J127

Pin 18 input for chip set 3

J128

Chip wirewrap interconnection for chip set 3

J129

Pin 20 input for chip set 3 (chip enable 3)

810

MRV11-C/M8048
Control and Status Register
Each MRV 11-C board uses one 16-bit control and status register located in
the system I/O page to determine mapping of ROM segments into windows
in the window mapped mode. The default address for this CSR is 177000

(777000 in the PDP-11/23 system). The valid address range for CSRs is
177000 to 177036 (777000 to 777036 on PDP-11/23s).

The CSR contains a 5-bit read/write field for each window. The number
stored in this field (O to 31,5) selects the desired 2Kb region from the

MRV 11-C board to be associated with the window in question. CSR bits O
through 4 control the mapping of the low address window, window 0. The
low five bits of the upper byte (bits 8 through 12) control the mapping of
window 1.

The MRV 11-C optionally provides a window enable/disable capability.
When this option is selected, bit 15 of the CSR is used to enable or disable
window response under program control. When bit 15 is a O, the board will
respond to references to the CSR or DATI or DATIO references to either of

the windows. When bit 15 is a 1, only the CSR will respond. If the enable/disable option is not selected, bit 15 of the CSR will be read only and
will always be 0. The enable/disable bit has no effect on direct mode addressing or the bootstrap window capability. If enable/disable option is
used, bit 15 on system initializes, disabling the board.

177036

R = jumper removed.
*Default address

DD
T

VDT DT DT ITTD
DT

T
T

177034

177032

177030

O T

177026

Bit 1
J92 to J93

177024

177022

177020

177016

177012

177014

DDV

177010

177006

VDT T

177004

Bit 2
J94 to J95

DIV T T

177002

Bit 3
J96 to J97

T T

177000*

Bit 4
J90 to JO91
VIV IDD

CSR
Address

T T T TV
T T T DDV D

Control and Status Register Addresses

| = jumper installed.
NOTE

Install J67 to J68 to allow the use of bit 15 of the CSR.
811

MRV11-C/M8048
MRV 11-C Direct Addressing Starting Address

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

0
1
2
3
4
5
6
7

|
l
i
I
|
|
|
|

I
|
I
|
I
I
|
I

|
I
|
l
R
R
R
R

|
|
R
R
|
|
R
R

|
R
|
R
!
R
I
R

200000
220000
240000
260000
300000

10
11

|
E
l
I
i
i

R
R

R
R
R
R
R
R

|
|

I
R

320000
340000
360000

12
13
14
15
16
17

!
l

400000
420000
440000
460000
500000
520000
540000
560000

20
21
22
23
24
25
26
27

R
R
R
R
R
R
R
R

|
|
|
i
!
|
|
I

H
|
I
|
R
R
R
R

|
|
R
R
I
|
R
R

|
R
|
R
I
R
|
R

600000
620000
640000
660000
700000
720000
740000
760000

30
31
32
33
34
35
36
37

R
R
R
R
R
R
R
R

R
R
R
R
R
R
R
=

|
!
|
|
R
=]
R
R

|
l
R
R
|
|
R
R

|
R
I
R
|
R
i
R

Starting

Address

Bank|57 to60 | 59to 58 | 61to 62 63 to 64 | 65 to 66

0
20000
40000
60000
100000

120000
140000
160000

|
!
R
R
R
R

R = jumper removed.
| = jumper installed.

812

R
R
|
|
R
R

!
R
|
R
i
R

MRV11-C/M8048
Using Multiple Boards
Up to 16 MRV 11-C boards may be configured in a single system. When multiple boards are present, each board has a unique control and status regis-

ter address assigned in increasing order from

177000 (777000 in PDP-

11/23 systems). Each board can have a unique 4Kb area of the physical
address space set aside for its windows, but it is also possible to share

one 4Kb area of the address space among all MRV 11-C boards installed in
the system. This is done by using the enable/disable capability discussed

earlier. When enable/disable is implemented, the disable bit in the CSR will
be set automatically by BINIT on the bus or by execution of the RESET instruction. Therefore, the initial state of the system will have all boards disabled. To access a particular segment of ROM in this multiboard configuration, the programmer first enables the desired board and maps the
segment. When access to that segment is completed, the board is again
disabled to allow another board to be selected some other time.

Chip Enable Jumpers

Sockets Enabled | Chip Enable Signal |Wirewrap Jumpered Pins
XE43, XE44
XE37, XE38
XE31, XE32
XE25, XE26
XE41, XE42
XE35, XE36

XE29, XE30
XE23, XE24

J86 to J87
J84 to J85
J82 to J83
J80 to J81
J78 to J79
J76 to J77
J74 to J75
J72 to J73

CEO
CE 1
CE2
CE3
CE4
CE5
CE®6
CE7

NOTE

J40 and J110 are unused at this time.
ROM Chips

The ROM is provided by the user and consists of up to 16 chips that are
inserted into prewired sockets. The chips will be either 1K X 8 bit, 2K X 8
bit, or 4K X 8 bit ROMs. When the MRV 11-C is fully populated, the result
will be either 16K, 32K, or 64K bytes of memory. These ROMs can be sup-

plied by a variety of vendors and the basic configuration for many of the
ROMs is standardized except for pins 18, 19, 20, and 21. The configuration
of these pins will vary depending upon the size of the ROM and the vendor
who supplies them. The user should verify the vendor’s specifications in
order to determine if a particular ROM can be used on the MRV 11-C.

813

MRV11-C/M8048
The MRV 11-C module isconflgured so that the user can select the signals

that are applicable to pins 18, 19, and 21. The board provides wirewrap

pins for the user to select the A11, A12, 5 Vdc or ground. There are three

individual loops that interconnect all chips and three wirewrap pins available for each individual chip. Wirewrap pin J112 interconnects pin 19 of all

the chips and pin J116 interconnects pin 21 of all the chips; these are normally designated as the A10 or A11 inputs to the chips.

Wirewrap pin J114 interconnects wirewrap pins that are individually associated with each chip. Pin 18 of each chip is individually wired to a wirewrap pin and chip pin 20 is wired to the chip enable signal. Chip pin 20 is
also individually wired to a wirewrap pin. The user must determine from the
vendor’s specifications which signals apply to which pins and must install

jumper wires as needed to configure an operational module.

INTEL 2716

INTEL 2732

PIN CONFIGURATION

24 [J Vec

24 [ Ve

A7 [

Ag ]2

23] A8

Ag ]2

23] A8

As [ 3

22 ] A9

As [ 3

22 7] Ag

A7 [

—

Ag] 4
Az [ 5

vpp — 10 *5 VDE
217
20355/TO€E

Ay [ 7

18Z]ETE"*“"’TOE’_E

19 [] Ajp— TO ATTH

Ar [ 6

aq[ 4
A3 [] 5

21177 A1 oA
2036€/VP;/TOCE

A1 [ 7

18:]C_E/TOEE

193A1O/TOA11H

Ay [ 6

Ap [ 8

17 [ 07

Ao [] 8

17 [J 07

oo [] 9

16 [J O6

oo [J 9

16 [ ] O6

01 [0

15[ Os

01 []10

15177 Os

02 [

14 [J 04

02 O 11

14 13 04

1317 03

GND [ 12

137 03

GND []12
2K X 8

ROM

4K X 8 ROM
MR-3262

MRV 11-C ROM Pin Configuration Sample

814

MRV11-D/M8578

MRV11-D UNIVERSAL PROM MODULE

GENERAL

The MRV11-D is a flexible, high density, dual size module used with the LSI-11
bus. The module contains 41 jumper posts, 2 switch packs, and 16 28-pin memory
chip sockets. A variety of user ROMs, such as fusible link PROMs, ultraviolet
eraseable (UV E) PROMs, and masked ROMs are acceptable to use. The module
is shipped from the factory with all jumpers installed.

The MRV11-D accepts several densities, up to and including 32K by 8; with 16 32K
devices, memory capacity is 512K bytes.
Amps

+5
1.6

Bus Loads

+12

(plus ROM chip power)
Standard Addresses

Recommended page mode

Window 0 is addressed between 17773000 and 17773776
Window 1 is addressed between 17765000 and 17765776
PCR address is fixed at location 1777520

Page mode PCR is used configured between 17777000 and 1777036.

Console octal debugging technigue (ODT)
Terminal addresses used by console ODT addresses

16-bit addressing = 177560 - 177566
18-bit addressing = 777560 — 777566
22-bit addressing = 1777560 - 1777566

Detailed technical information is beyond the scope of this manual. For more
information, refer to the Microcomputer Processor Handbook, EB-18451-20.

815

MRV11-D/M8578
Diagnostic Programs
None

Related Documentation

MRV11-D Universal PROM Module User Guide (EK-MRV1D-UG)
Field Maintenance Print Set (MP-00566)
PROM Sizes and Pinouts

The MRV11-D contains 16 28-pin sockets to house the various PROMs and static
RAM devices that can be used in the module. The sockets can house 2K by 8, 4K
by 8, 8K by 8, 16K by 8, and 32K by 8 PROMs. In addition, the bottom half of the
socket array (chip sets 0 through 3) can accommodate static RAM. The 2K by 8
and 4K by 8 PROMs contain 24 pins while the others contain 28 pins.
F.

POWER JUMPERS

ADDRESS MODE &

]

XE47

XE40

XE4?2

XE43

]

XE36

XE38

XE37

XE39

SYSTEM SIZE JUMPER
READ TIMING

JUMPER

fi
E7

E21

E20

STANDARD DECODER

1~ PATTERN SELECT
JUMPERS

RoomseS 2 e0 MU TM
el

DEVICE SIZE JUMPERS
3%

[ E12 [f

E19

4
\

ENABLE BOOTSTRAP

ROM/RAM

SELECTION
JUMPERS

JUMPER

E18

XES1

E23ELE24 (f(LE25 C = aLENEJ [jza fl

_PCR ADDRESS SWITCHES

e
o

STARTING ADDRESS
SWITCHES
A

BATTERY BACKUP

[—u] 5SHUNT

S 7~ DATO JUMPER

MRV11-D(M8578)

oe— J14

Oe—

J13

* O@— J12
O

J11

Oe—

J10
MR-12877

MRV11-D (M8578) Jumper and Switch Locations

816

MRV11-D/M8578
A.

BATTERY BACKUP SHUNT

DESCRIPTION

JUMPER CONNECTION
0 OHM SHUNT

SHIPPED CONFIGURATION. NO BATTERY BACKUP ON

SYSTEM: +5V ONLY

000

gr‘v%i/ 0 OHM SHUNT
O

BATTERY BACKUP PROTECTION FOR RAMS

NOTE

INSTALL W1 OR W2 BUT NOT BOTH.
MR-12878

SYSTEM SIZE JUMPER

SYSTEM SIZE JUMPERS (W3)
JUMPER CONNECTION

DESCRIPTION

J23

J22

W3
O

SPECIFIES 16-BIT OR 18-BIT SYSTEM.

J21

121422423

O 575

SPECIFIES 22-BIT SYSTEM.

121422123
MR-12879

DESCRIPTION

JUMPER CONNECTION
C.

ROM/RAM SELECTION JUMPERS (W4, W5)

HI BYTE )
J38
WhH

J37

O J36 L

THIS CONFIGURATION IS USED FOR ALL ROM MEMORY
(NO RAM). BOTH JUMPER CLIPS (W4 AND W5) MUST BE
INSERTED IN THE UPPERMOST PINS.

LO BYTE

J32
w4

J31

|
O J30

HI BYTE )
O J38

J37

THIS CONFIGURATION IS FOR ROM/RAM MEMORY.
RAM IS INSTALLED IN CHIP SETS O THROUGH 3
(BOTTOM HALF OF ARRAY). WHEN RAM IS INSERTED.
BOTH JUMPER CLIPS MUST BE INSTALLED IN THE

J36

LO BYTE

LOWER PINS.

QO J32

i [C

J31
J30

MR-12926

817

MRV11-D/M8578
D.

DATO JUMPER CONNECTION (We6)
DESCRIPTION

JUMPER CONNECTION
W6

CAUSES BUS TIMEOUT WHEN ACCESSED BY DATO
CYCLE. NOT USED WHEN RAM IS INSTALLED.

bbo

J15J16 J17

WITH RAM INSTALLED, USE THIS CONFIGURATION

000

WHICH WILL RESPOND TO DATO CYCLES.

J15 J16 J17

NOTE

THE PCR OR THE BOOTSTRAP PCR WILL NOT
TIMEOUT IN EITHER CONFIGURATION WHEN
ACCESSED BY DATO CYCLES. EITHER JUMPER
CONNECTION MAY BE USED, BUT THE CLIP
MUST BE INSTALLED TO ALLOW ANY DATO
CYCLE ON THE MODULE.

MR-12880

DEVICE SIZE JUMPERS (W7, W8)

THE TABLE BELOW REFLECTS THE REV C AND REV D ETCH CONFIGURATION. THE ETCH AND
BOARD NUMBER IS LOCATED ON THE COMPONENT SIDE OF THE MODULE ALONG THE LEFT HAND SIDE.
5015213C — REV C ETCH
50152130 — REV D ETC

JUMPER CONNECTION
REV C
ETCH

O J14
TO PIN 41 (+5V)
(WIRE WRAP)

J13
O

DESCRIPTION

REV D
ETCH

CHOOSES 2K BY 8 DEVICE ONLY

O
:—_]

J12

J11

J10 ::j

W8 [—_—g J14

CHOOSES 4K BY 8, 8K BY

8. OR 16K BY 8 DEVICES.

J13

J12
J11

Ji10

l w8

J 14

w8 l

J13

J12

J11

CHOOSES 32K BY 8 DEVICES

l W7

J10

NOTE: A NEW ARRAY DECODER S REQUIRED IF YOU USE 32K AND 16K
BY 8 DEVICES. USE DIFFERENT QUANTITIES THAN THOSE DESIGNATED
BY THE STANDARD DECODER, OR MiX 4K, 8K OR 16K BY 8 DEVICES.
TO MIX 4K, 8K OR 16K BY 8 DEVICES WITH 32K BY 8 DEVICES

YOU MUST PROPERLY CONFIGURE THE POWER JUMPERS FOR EACH ROW.
ROWS CONTAINING 32K BY 8 DEVICES MUST BE JUMPERED FOR ADDRESS
RATHER THAN POWER. (SEE TABLE 3-6)
MR-12927

818

MRV11-D/M8578
F

POWER JUMPER CONNECTIONS
(W9, W10,W11
W12)

JUMPER CONNECTION

DESCRIPTION
-~

J41

W12-ROW4

J40

39 O

J35 Co)j

THIS CONFIGURATION IS FOR 2K BY 8 AND 4K BY 8 ROMS
AND 8K BY 8 STATIC RAM. THE POWER JUMPER MAY BE IN

W11-ROW
3

J34

EITHER POSITION FOR THE 8K BY 8 ROM. THE POSITION
SHOWN PROVIDES +5V POWER TO PIN 26. THE CONFIGURING

J33 O

IS DONE ON A ROW BY ROW BASIS.

FOR EXAMPLE, IF 4K BY
8 ROMS ARE INSTALLED IN ROWS 1,2, 3 AND 16K BY 8 ROMS

3
g
J29

W10-ROW 2

ARE INSTALLED IN ROW 4, THE ROW 4 JUMPER WOULD BE

CONNECTED BETWEEN THE TWO LOWER PINS WHILE ALL

J27

THE OTHER JUMPERS ARE CONNECTED AS SHOWN.

W8-ROW 1

J25

J24

fl\

W12-ROW 4

W11-ROW 3

FOR 16K BY 8 OR 32K BY 8 DEVICES, THE POWER JUMPER MUST

» BE IN THIS POSITION. IN THIS POSITION, PIN 26 IS CONNECTED
BY AN ADDRESS LINE.
W10-ROW 2

W9I-ROW 1

y,
MR-12888

READ TIMING JUMPER (W13)
JUMPER CONNECTION

DESCRIPTION

W13

450 ns READ TIME (NORMAL).

J18J19 420

W13

J18 419 420

200 ns READ TIME (FAST).IN THIS CONFIGURATION,
SPEED ADVANTAGE IS OBTAINED BUT THE SLOWEST
DEVICE INSTALLED ON THE BOARD MUST MEET THE

200 ns ACCESS TIME REQUIREMENT,
MR-12887

819

RV11- D/M8578
H.

ENABLE BOOTSTRAP JUMPER (W14)
DESCRIPTION

JUMPER CONNECTION
JGE :—:]

ENABLES BOOTSTRAP. ALLOWS 512 BYTES AT 17773000
(WINDOW 0), AND 512 BYTES AT 17765000 (WINDOW 1) TO
BE USED AS BOOTSTRAP. BOOTSTRAP PCR ADDRESS IS

W14

17777520.

B8O

DISABLES BOOTSTRAP ON MRV 11-D. NONE OF THE ABOVE

I g iW‘l4

LOCATIONS RESPOND.

MR-12881

STANDARD DECODER PATTERN
SELECT JUMPERS (W15,W16)

DESCRIPTION

JUMPER CONNECTION
30O

2K BY 8 ROMS, 1/2 POPULATED

W15

Jg
J8
J7

-3 g]ww

W16

2K BY 8 ROMS, FULLY POPULATED

4K BY 8 ROMS, FULLY POPULATED

W16

8K BY 8 ROMS, FULLY POPULATED

7.0
MR-12882

PCR ADDRESS SWITCHES

DESCRIPTION

SWITCH

NOTE

ORIENT MODULE WITH HANDLES FACING AWAY
AND FINGERS TOWARD YOU.

ON=DIR

OF=PAGE
PCR4

DIRECT/PAGE

TO SELECT DIRECT MODE ADDRESSING, PUSH RIGHT
SIDE OF ROCKER SWITCH DOWN (SWITCH ON}. TO
SELECT PAGE MODE ADDRESSING, PUSH LEFT

PCR3
PCR2

PCR1

SIDE OF ROCKER SWITCH DOWN (SWITCH OFF).

PCR4,

PCR3,

PCR2,

PCRI1

THESE SWITCHES CONTROL THE ADDRESS OF THE

PAGE CONTROL REGISTER.

THE SWITCHES ALLOW

ANY ADDRESS FROM 17777000 TO 17777036 TO BE

SELECTED ON EVEN WORD BOUNDARIES.
PUSHING DOWN THE

RIGHT SIDE OF THE

SWITCH PRODUCES A LOGICAL 0
PUSHING DOWN THE

LOGICAL 1

Detautt:

ROCKER

(SWITCH ON).

LEFT SIDE PRODUCES A

(SWITCH OFF).

17777036g
MR-12883

820

MRV11-D/M8578
K.

STARTING ADDRESS SWITCHES

SWITCH

[:D—* SA2Z21 MSB
D]M

SA20

Dj w | SA19

DESCRIPTION

SA1--SAT0 ROCKER SWITCHES.
PUSHING

THE RIGHT SIDE OF THE

SETS UP STARTING ADDRESS OF THE
MODULE.

PERMITS ANY STARTING

SWITCH DOWN TURNS THE SWITCH

ADDRESS FROM 0 TO 17770000 ON

ON (LOGIC 1).

4K BYTE BOUNDARIES..

PUSHING

THE LEFT

SIDE OF THE SWITCH DOWN TURNS
THE SWITCH OFF (LLOGIC 0).

EI:]U’ SATY

NOTE

MODULE IS ORIENTED WITH HANDLES FACING

AWAY AND FINGERS TOWARD YOU.

D]\x SA15

EDOO SA14
[:[:jco SA13
o

|SA12 LSB

MR-12884

The basic differences on the 2764, 27128, 27256, and static RAM are in the
functions of pins 26 and/or 27. The figure below shows these differences. For
example, on the 16K by 8 PROM (27128), pin 26 is used as an address pin (A13).
On the 32K by 8 PROM (27256), pins 26 and 27 are used as address pins (A13 and
A14, respectively).

821

MRV11-D/M8578

23
A

£ 2z 1z

O 0]

4el

bl vl

N8AMOEYHd 2

veoi[do%lo

By Sy Hy 30 Oty 39 0 °0 e ) e
r~

;

1°vv [Mlse8y

T3LNI9142NidNOILVYHNODIANOD

Ly %y Sy vy vy ¢y

Ly 9l

sedAl WOHd eiqiedwo)

ZvReAlN [e]zoz3e0[y 1J°°ovLv1 [sszols8y! b6zl¢[3z0oz2[toewzyods

op[eJlat Iz[m o8iyz

vsgyz n9ylez

BWAMOGCHd

822

Z
&)

MRV11-D/M8578

When installing a 24-pin PROM (2K by 8, 4K by 8) in a 28-pin socket, install it with
the notch on top and bottom justified. Pin 1 of the PROM inserts into pin 3 of the

socket. On 28-pin devices, pin 28 is the power pin. For 24-pin devices, pin 28 of
the socket must be strapped to pin 26 of the socket to provide power to the
device. The power jumpers strap these pins together, as shown in the following

figure.

~NOOO
D WN—

28 PIN PROM SOCKET

MR-12886

Insertion of 24-Pin PROM Chips
NOTE

If you are using 24-pin devices such as the 2716 (2K by 8 PROM) on a
revision C etch board, you must wire-wrap J13 (Vpp) to J40 (pin 26 of
row 4). It is also necessary to jumper J40 to J41 (+5 V). However, you
cannot use the jumper clip because a wire-wrap exists on J40. Therefore, you must wire-wrap, rather than jumper, J40 to J41. This procedure ensures proper read mode operation. On a revision D etch board,
you can install 2K by 8 PROMs without wire-wrap.

823

MRV11-D/M8578
Storage Capacity per ROM Chip Size and Number of Chips

Number of
Chips

(Capacity Measured in Kbytes)

instalied

2Kby8

4Kby8

8Kby8

16Kby8

32K by38

2
4
6
8
10

4
8
12
16
20

8
16
24
32
40

16
32
48
64
80

32
64
96
128

64
128
192
256

112

128

160
192
224
256

320
384
448
512

Typical EPROMs

Chip Array

Maximum
Memory

UV PROMs

Size

Array Size

Intel 2716

2K by 8

32 Kbytes

intel 2732

4K by 8

64 Kbytes

Intel 2764

8K by 8

128 Kbytes

intel 27128

16K by 8

256 Kbytes

Masked ROMS
Mostek MK3700

8K by 8

128 Kbytes

NCR 23128

16K by 8

256 Kbytes

512 Kbytes

NEC 23256

32K by 8

National 52364

8K by 8

128 Kbytes

Signetics 23128

16K by 8

256 Kbytes

Synertek 2365

8K by 8

128 Kbytes

Synertek 2365A

8K by 8

128 Kbytes

Synertek 2316B

2K by 8

32 Kbytes

Synertek 2333-3

4K by 8

64 Kbytes

824

MSV11-B/M7944

MSV11-B READ/WRITE MEMORY

Amps
+5
0.6
(1.12 max.)

+12
0.3
(0.7 max.)

Bus Loads

Cables

AC
1.89

none

DC
1.0

Standard Addresses

Module is shipped with all jumpers installed, selecting bank 0 (0-17776).

Vectors, DEC/X11 Exerciser Program
None

Diagnostic Programs

Refer to Appendix A.

Related Documentation

Field Maintenance Print Set (MPOO067)
Microcomputer Processor Handbook (EB-18451-20)

NOTES

Only one dynamic memory module in a system is needed

to reply to the refresh bus functions initiated by the processor. The module selected should be the one with the
longest access time (usually the module electrically farthest from the refreshing device).

825

MSV11-B/M7944
NOTES (Cont)

If aREV11 (M9400YA or YC) provides refresh, only theto prorecessor-resident memory (if present) should reply y,
the

fresh. If the processor board has no resident memorREV11
memory module electrically farthest from the
should reply.

3. Refer to the Refresh Configuration Procedures in the’’Systems Configurations’’ section.

W3m

mW4

ez
\/\ 1
w2 RIS

M7944 ETCH REV B

MR-5428

M7944 Etch Rev B

826

MSV11-B/M7944
BDAL

BITS

HEE
'

“

4096 LOCATION ADDRESS

—

BYTE
POINTER

4K ADDRESS
SPACE JUMPERS
/

f_——.—)b-—————\

Bank

Address

No.

Range

0-4K

4-8K

Octal Address
Range

000000-017776
020000-037776

]

8-12K

040000-057776

12-16K

060000-077776

16-20K

100000-117776

20-24K

24-28K

120000-137776
140000-157776

28-32K

160000-177776

NOTE:

| = Installed,

R = Removed
MR-5429

MSV11-B Address Format/Jumpers

NOTE

Because of addressing limitations, this module is not compatible with PDP-11/23 systems with more than 64K bytes of
memory.

MSV11-B Address Format/Jumpers
Reply to Refresh

Function

R
|

Don’t reply

827

MSV11-C/M7955

MSV11-C MOS READ/WRITE MEMORY

Module

Model

Description

M7955-YA
M7955-YB
M7955-YC
M7955-YD

MSV11-CA
MSV11-CB
MSV11-CC
MSV11-CD

4K by 16-bit read/write memory
8K by 16-bit read/write memory
12K by 16-bit read/write memory
16K by 16-bit read/write memory
Bus Loads

Amps

+5
1.1

+ 12
0.54

AC
2.32

DC
1

Cables

None

(2.0 max.) (0.56 max.)

Standard Addresses

Module is shipped configured to start at bank O.

Vectors
None

Diagnostic Programs

Refer to Appendix A.

Related Documentation

MSV11-C User's Manual (EK-MSV11-OP)
Field Maintenance Print Set (MP00259)
Microcomputer Processor Handbook (EB-18451-20)

828

MSV11-C/M7955

;

77T

W16 | w8

W14 W15

w12

W6 W2 W1 W5

]

MR-082)

M7955/MSV11-C Jumpers
NOTES

Only one dynamic memory module in a system is needed
to reply to the refresh bus transactions initiated by the
processor. The module selected should be the one with
the longest access time.

|faREV11 (M9400-YA or M9400-YC) provides refresh, only
the processor-resident memory (if present) should reply to
refresh. If the processor board has no resident memory,
the memory module electrically farthest from the REV11
should reply.

If MSV11-Cs are mixed with MSV11-Bs, the MSV11-Cs

should use internal refresh. Again, the memory electrically
farthest from the refreshing device should reply. Refer to
the ‘“Refresh Configuration Procedure’ in the ‘““Systems
Configurations’ section.

829

MSV11-C/M7955
MSV 11-C Jumper Configuration When Shipped
Jumper|

Jumper

State

Function Implemented

Battery backup power connected to system power.

W3
W5

Name
W2

|
|

Battery backup power only.

W1 W2 W3 W5
R
E

i
R

R
|

Battery backup power available but not desired for this
MSV11-C module.

W6
W7

|
&

Internal refresh enabled.
Reply to refresh disabled.
We W7

W4
W8

*
*

Wi6

W12

W14

Wi5

External refresh; no reply.

External refresh; reply enabled.

Factory configured to enable the memory banks appropriate to the memory model. These are normally not

changed except for:
1.

Maintenance - Refer to chapter 4 of MSV171-C

Configuring for 28K system: Remove W16 to disable upper 4K. See configuration rules in the
‘“Systems Configurations’’ section.

User’s Manual, EK-MSV11-OP.

Bus grant continuity provided.

*Memory bank enable jumpers when supplied.

830

MSV11-C/M7955

Module

Option

Memory

Number

Designation

Size

W4 W8 W12 W16

M7955-YD

MSV11-CD

16K

M7955-YC

MSV11-CC

12K

M7955-YB

MSV11-CB

M7355-YA

MSV11-CA

MSV11-CD Addressing Summary
Switch

Starting | MSV11-CD
Address | Banks

Address Range

Setting
S2 S3 S4

S$5

0-3

20000

1-4

O-77777

20000-117777

40000

2-5

40000-137777

60000

3-6

60000-157777

100000

4-7

100000-177777

120000

5-10

120000-217777

140000
160000
200000
220000

6-11
7-12
10-13
11-14

140000-237777
160000-257777
200000-277777
220000-317777

i1
O
1
0o

0
0O
1
1

0
0
1T
1

1
1
0
0

1
1
1
1

240000
260000
300000
320000
340000
360000
400000
420000
440000
460000
500000
520000

12-15
13-16
14-17
156-20
16-21
17-22
20-23
21-24
22-25
23-26
24-27
25-30

240000-337777
260000-357777
300000-377777
320000-417777
340000-437777
360000-457777
400000-477777

i
o
1
o
i
0)
1

0
o
1
t+
0
o)
1

1
1
0
0
0
0)
1

0
0
0
0
0
0
1

1
1
1
1
1
1
O

420000-517777
440000-537777
460000-557777
500000-577777
520000-617777

0o
1
O
1
o

26-31
27-32
30-33
31-34
32-35

540000-637777
560000-657777
600000-677777
620000-717777
640000-737777

1
1
1
0
o0
o0
o
1

1
1
1
1
1

540000
560000
600000
620000
640000

1
0
0
i
t+
0
0o
1

0
0
0
0
O
O
O
O

660000
700000
720000
740000
760000

33-36
34-37
X
X
X

660000-757777
700000-777777
X=X
X -X
X=X

831

i
O
1
0o
i

o
1
o
i
O

1
0
o
i
1
0
0O

i
1
1
0
0
0

1
t
0
0
0

0
0
0
0
0

O
O
O
O
O
O

MSV11-C/M7955
NOTES

Switch setting:
ON

OFF

Each memory bank = one 4K address space.

Switches 6, 7, and 8 are not used.

NOTE

When used in PDP-11/23 systems, the MSV1 1-C memory cannot be configured in the 56K-64K byte (28K-32K word) range
or in the 248K-256K byte (124K-128K word) range.

832

MSV11-D,E/M8044,5

MSV11-D,E MOS READ/WRITE MEMORY

Model

Memory Capacity

Module

Parity Bi

MSV11-DA
MSV11-DB
MSV11-DC
MSV11-DD
MSV11:ED

4K by 16 bits
8K by 16 bits
16K by 16 bits
32K by 16 bits
32K by 18 bits

M8044-AA
M8044-BA
M8044-CA
M8044-DA
M8045-DA

No
No
No
No
Yes

Amps

Bus Loads

+12

2.0

0.41

AC
2

Cables

DC
1

None

Standard Addresses

Module is shipped configured to start at bank O.

Vectors

None

Diagnostic Programs

Refer to Appendix A.
NOTE

DEC diagnostic will not check parity.

Related Documentation

MSV11-D, -E User’s Manual (EK-MSV 1D-OP)
Field Maintenance Print Set (MP00259)

Microcomputer Processor Handbook (EB-18451 -20)
833

MSV11-D,E/M8044,5
Address Selection

The MSV11-D or MSV11-E address can start at any 4K bank boundary. The

the contiguous portion of
forss
address configured is the starting addre

memory (4K, 8K, 16K, or 32K) contained on the module.

|__51-1

ADDRE

SWITCHES

S1-5
MEMORY / ©®®@
®®
IN_12 14 10
90
92E
_

W3 o 45y

+5B
BATTERY BACKUP Wo—rD
W2 p+12vV
POWER JUMPERS
.

PARITY/NO

}PAR'TY
OPERATIO

17 15 16

+12 B
W4—=p

ANK7

DISABLE

SEENOTE1

SEE NOTE 2

NOTES:

1. JUMPER 1 TO 2 = 30K OPTION (MINC) 1 TO 3 FOR NO 30K OPTION

2. JUMPER5TO 7 FORMSV11-DOR5TO 6 FOR MSV11-E

MR-5418

MSV11-D, MSV11-E Switch and Jumpers M8044,45

Set the switches to the desired starting address as listed in the table. Note
that the module is designated to accommodate a 128K system addressing
capability. However, the present addressing capability of the LSI-11 system, including all PDP-11/03, PDP-11V03 and PDP-11T03 systems, is 32K.
PDP-11/23

systems,

however,

can

address within

the full

128K word

range. By PDP-11 convention, the upper 4K address space is normally reserved for peripheral device and register addresses. Thus, with the present

LSI-11
maximum addressing capability of 32K, bank 7 (address
160000-177777) normally should not be used for system memory.

834

MSV11-D,E/M8044,5
Factory-configured modules will not respond to bank 7 addresses. In special applications that permit the use of the lower 2K portion of bank 7 for
system memory (i.e., MINC), enable the lower 2K portion of bank 7 by removing the jumper from wirewrap pins 1 and 3 and connecting a new jumper from 1 to 2.

NOTE
if 30K option is enabled, some diagnostics may not run.

Battery Backup Power

MSV11-D and MSV11-E modules are factory configured with power jumpers

installed for normal system power only. If the system uses a battery backup

power source, remove jumpers W2 and W3. Install new jumpers W4 and

W5. (Two jumpers are removed and two new jumpers are installed.)
Parity

One jumper is factory installed for nonparity (MSV11-D) or parity (MSV11E) operation, depending on the model. Do not reconfigure this jumper.
Standard jumper configurations are listed below.
e

All MSV11-D models: jumper installed from pin 7 to pin 5.

All MSV11-E models: jumper installed from pin 6 to pin 5.

NOTE

This memory parity feature is not supported by DEC diagnostics or CPUs.

Memory Size

Two jumpers are factory installed to configure addressing logic for memory

size (number and type of memory-integrated circuits). Do not reconfigure
these jumpers. Standard jumper configurations are listed below.

Jumpers (Two Installed)

Models

Memory Select Pins

From
MSV11-DA
From
MSV11-DB
From
MSV11-DC
MSV11-DD, ED | From

17 to
12 to
16 to
10 to

14
14
14
14

835

Memory Range Pins
From
From
From
From

17 to
17 to
16 to
16 to

15
15
15
15

MSV11-D,E/M8044,5

‘A-LASWLASW3I-LBuiseipyArewwnsg

000¥ N N N Ne N 02 1£-02 €G-02 /L-10-2

pys(AMeBos1Iu)O9jim|WulasBeWgs ON0=-2|k012 SN0-LG¥l0Y0t1

836

MSV11-D,E/M8044,5

a‘pl8AJju@ieyqn1MaebiOo)ulsjmd|nu}oyd

ojX“8=sun

'L youms:sBunes

LASW‘G-LLASW3-LBuisaipyAlewng(1uo))

p(AM8Isl}O)ob9Wu|BaesWg

837

€

MSV11-L/M8059

MSV11-L MOS READ/WRITE MEMORY

GENERAL

MSV11-L Modules

MOS

Memory

Number

of Chips

Model

Capacity

Chips

Module

MSV11-LF
MSV11-LK

128K bytes
256K bytes

64K X 1
64K X 1

M8059-FA
M8059-KA

18
36

MSV11-L POWER

Power Requirements

+5V 5% Power (Watts)

+5V + 5%
Current (Amps)

|Meas

Active

Standby

Active

Standby

Max

Meas

Max

(+5V)

(5.25V)

[(+5V)

(5.25V)

7.0

10.76

7.25

10.76

205|7.5

10.76

8.0

10.76

Max | Meas

Type | Meas

Max

140
64K
(LF)
128K | 1.50
(LK)

2.05

11.45

2051

2.05

|[1.60

838

MSV11-L/M8059
Power Requirements (Cont)
+5 V BBU 5%

+5 V BBU 5% Power (Watts)

Current (Amps)
Standby
Type|

Meas

64K | 0.9

(LF)

128K|

1.0

Active
Max | Meas

Standby
Max | Meas

Active
Max

Meas

(+5V)

(5.25V) | (+5V)

Max
(5.25V)

1.26]

1.35

1.851

4.5

6.62

6.75

9.71

1.381

1.40

197

5.0

7.25

7.0

10.34

(LK)
+5V Total 5%

+5 V Total 5% Power (Watts)

Current (Amps)

Active

Standby

Type|

Meas

Max | Meas

Active

Standby

Max | Meas
(+5V)

Max

Meas

Max

(5.25V)|

(+5V)

(5.25V)

64K | 2.3

331128

390|115

17.38

140

20.48

(LF)
128K|
(LK)

3.43|3.0

4.02|125

18.01

15.0

21.11

2.5

Meas = measured
Max = maximum
NOTE

Use the total table above for power requirements for factory configured option modules.

Diagnostic Programs

Refer to Appendix A.
Related Documentation

MSV11-L User’s Guide (EK-MSVOL-UG)

MSV11-L Memory Module Configuration Guide (EK-MSV1L-CG)
Field Maintenance Print Set (MP-01238)

839

MSV11-L/M8059

|SN
NOTE

CHIPS ARE POSITIONED 180° OUT OF PHASE
WITH TRADITIONAL DIGITAL MEMORIES.
DOTTED BLOCK DENOTES

GROUP 1

GROUP 1 JUMPERS — GENERAL

GROUP 2, 3 JUMPERS — START/CSR ADDRESS
— POWER
P
4 JUMPERS
GROU
e NO BATTERY BACKUP
e BATTERY BACKUP

WIREWRAP GUIDELINES — MAXIMUM, 2 WIREWRAPS PER PIN.

OF WIREWRAPS.
GROUP 2 AND 3 JUMPERS MAY HAVE MAXIMUM NUMBEROWN
GROUND.
e EACH WIREWRAP MUST BE DAISY-CHAINED TO ITS

MBOARD |

| POPULATION|
|
® 34

¢33

®?2
Y
e X

GROUP 2

JUMPERS

oy
U
=£-4
SYSTEM
| JUMPER

TYPE MEMORY!
— e —
201918
o o r-WRITE WRONG—:
PARITY
PN(BIT 2) |
o €=o
g
171615 |
|

eR
I
et

REMOVAL OF
|
THE LOWER

®S

®p

®N

Jad
=

—

rv-\}'lTHOUT CsRJe!
H

WITHCSR

Lo
-

GROUP3

JUMPERS

OR UPPER

BANK IFIT

A FAULT
HAS

TYPE MEMORY'

11108o

R
EARAE]

.ngRCEI

= %

. A

PERIPHERAL

PAGE SELECTION

876 ]

NORMAL OR

|
TIMING TEST

| POINT5 4

REPORT
321

e q9

®14
@31
| ®30fe13
®12
@29

28|25 ©24

®27|
-

oo,

PARITY ERROR

—_—

‘je-

GROUP4
JUMPERS

€926
§

(W1) +5 NONBATTERY BACKUP

MR 8677

MSV11-L Memory Module Layout

840

MSV11-L/M8059
CONFIGURATION
There are four groups of jumpers that alter the memory operation for a spe-

cific system application. The jumper groups are named as follows.

Group 1 -

General jumpers

Group 2 -

Starting address jumpers

Group 3 -

CSR address jumpers

Group 4 -

Power jumpers

General Jumpers
The general configuration jumpers are described in the following table, and

the normal or factory configuration is designated by being installed or removed.

General Jumpers (Group 1)
Jumper
Configuration

Function

Normal
Condition

Type Memory

Nonparity

9to 10

ouT

With parity

1110 10

Parity non-CSR

18 to 19

ouT

Parity with CSR

20 to 19

3to2

ouT

Parity Error Report

Reported BDAL
16 non-CSR

Reported BDAL
16 and BDAL17 with | 1to 2

CSR
Write Wrong Parity
Diagnostic bit for tester use:

Disable

8to7

ouT

Enable

6to7

841

MSV11-L/M8059
General Jumpers (Group 1) (Cont)
Normal

Jumper

Configuration

Condition

JioH
FtoH

ouT
IN

29 to 28
27 to 28

ouT
IN

32 to 33
34 to 33

ouT
IN

17 to 16
15to 16

ouT
IN

Small system normal operation

RtoT

ouT

Large system extended operation

RtoT

Function
CSR Selection

Non-CSR
With CSR
Peripheral Page Selection

2K peripheral page
4K peripheral page
Full or Half Memory Selection

Half memory selection
Full memory selection
Removal of Lower or Upper Bank
(with a Fault)

Lower bank has failed
Normal operation or upper bank
has failed

Extended or Normal Memory
Selection

(128K)

(2 megawords)

842

MSV11-L/M8059
Starting Address Jumpers
Each MSV11-L memory module installed in a system is jumpered for its
own starting address. The starting addresses are always on 4K bound-

aries. The module’s starting address can be found by answering the question “How much memory does the system already have?’’ The value obtained

is the module starting address in decimal k words. Module starting ad-

dresses and jumpers consist of two groups.

First address of the range (FAR) - Selects the first address of the
128K range that the starting address falls in.

Partial starting address (PSA) - Selects which 4K boundary within a
specific multiple of 128K words the starting address falls in.

The module starting address (MSA) is determined by how much memory
the system has in decimal k words. First address of the range plus partial
starting address equals module starting address.

Known

PSA = MSA — FAR

Partial Starting Address

First Address of Range

First Address of Range (FAR)
Jumpers In (X) to Ground (K)

Decimal (K)

Octal

000-124

00000000-00760000

128-252
256-380
384-508
512-636
640-764
768-892

01000000-01760000
02000000-02760000
03000000-03760000
04000000-04760000
05000000-05760000
06000000-06760000

896-1020

07000000-07760000

1024-1148

10000000- 10760000

1152-1276
1280- 1404
1408-1532
1536-1660
1664-1788
1792-1916
1920-2044

11000000- 11760000
12000000- 12760000
13000000- 13760000
14000000- 14760000
15000000- 15760000
16000000- 16760000
17000000- 17760000

843

X
X
X
X
X
X

X
X

X
X
X
X
X
X
X

X
X
X
X

X
X

X
X
X

MSV11-L/M8059
Partial Starting Address (PSA)
Jumpers in (X) to Ground (U)

Decimal

Octal

00000000

8
12

00040000
00060000

DAL

Pins £

(K)

00020000

00100000

00140000

00200000

00240000
00260000

X
X

28
36

40
44

56
60

68
72
76

84
88

100

104
108
112

116

120
124

00120000

00160000

00220000

00300000

X
X

00320000

00340000
00360000

00400000

00440000
00460000

X
X

00420000

00500000

00520000

00540000

00560000

00600000

00640000
00660000

X
X

00620000
00700000

00720000

X
X

00740000
00760000

844

X
X

X
X
X

X
X
X
X
X
X
X
X

X
X
X
X
X

X
X
X
X
X
X
X
X

MSV11-L/M8059
Module Starting Address (Example — 352K Words)
First Address

Partial Starting

Names

of Range (FAR)

Address (PSA)

Decimal k words

1Meg 512K

256K

128K

64K

32K

16K

BDAL values

156

BDAL bits

Jumper pin names

Jumper pins

K
Mto

binary address

ZtoY,YtoU

CSR Address Selection

There are three addresses reserved for the CSR. Every MSV11-L memory
module has one CSR. By convention the CSR addresses are assigned as
follows. The memory module with the lowest starting address should be

jumpered for the lowest CSR address. The remaining memory modules will
be jumpered in sequence.

CSR Address Jumpers (Group 3)
22-Bit CSR
Address

18-Bit CSR
Address

17772100

772100

17772102
17772104

772102
772104

17772106

772106

17772110

772110

17772112

772112

17772114

772114

17772116

772116

845

X
X

Note: To obtain any 1 of 8 CSR addresses,
wirewrap daisy-chain fashion from pin E,
which is grounded, to each successive pin
labeled X for that address.

MSV11-L/M8059
Power Jumpers

Power jumpers allow the MSV11-L memory module to use battery backup or

nonbattery backup power.

Power Jumpers (Group 4)
Voltage Connection

Jumper Configuration

+5 V Nonbattery backup

26 to 25 (W1)

+ 5 V Battery backup

24 to 25 (W2)
14 to 13 (W3)*
or

12to 13 (W4)*

* Availability for the +5 V battery backup.

CSR Bit Assignment

The CSR allows program control of certain parity functions and contains
diagnostic information if a parity error has occurred. The CSR is assigned
an address and can be accessed by a bus master via the LSI-11 bus. Some
CSR bits are cleared by the asssertion of BUS INIT (L). The CSR bit assignments are as follows.

TAI3

| A12 | AT

EXTENDED

v
ERROR ADDRESS

WRITE

WRONG
PARITY

CSR READ
ENABLE

USED

USED |USED

PARITY
ERROR

NOT

| NOT | NOT
OR || oRr
OR || A19
OR || a20
NOT | NOT | A47 | a16 | a15 | 251
A8 |USED |USED

PARITY
ERROR

ENABLE
MR .8644

MA-7169

CSR Bit Assignments

846

MSV11-L/M8059
CSR Bit Descriptions
Bit

Name

Parity error

Description
If

parity

error

occurs

DATI

DATIO(B) cycle, this bit will be set to a 1.
This is a read/write bit and is reset to O
via a power up or BUS INIT. Bit 15 will remain set unless rewritten or initialized.
14

Extended CSR Read

This bit is not used on

Enable

chines. It will be read as a 0. Bit 14 can

be set to a 1

128K word ma-

in a 2048K word machine

only. In a 2048K word machine bit 14 is a
read 1 write bit and is reset to O by power

up or BUS INIT. When set, bit 14 allows

retrieval

of failed

through

A21

address bits

stored

of A18

CSR

bits

error occurs

DATI

cycle,

A11-A17

through 08 respectively.

13, 12

Not used

11-05

Error address

If a

parity

DATIO(B)
stored

A18-A21

CSR
are

then
bits

05-11

latched.

The

and

are
bits

128K word

machines (18-bit address) require only
one read on the CSR to obtain the failed
address bits. CSR bit 14 = 0O allows the

logic to pass A11-A17 to the LSI-11 bus.
A 2048K word machine (22-bit address)

requires two reads. The first read CSR bit
14

sends

contents

CSR

bits

05-11. Then the program must set CSR
bit 14 = 1. This enables A18-A21 to be
read from CSR bits 05-08.

The

parity

error addresses

locate the

parity error to a 1K segment of memory.

These are read/write bits and are not reset to zero via power up or BUS INIT. If a

second parity error is encountered, the
new failed address will be stored in the
CSR.

04, 03

Not used

847

MSV11-L/M8059
CSR Bit Descriptions (Cont)
Bit

Name

Description

Write wrong parity

If this bit is set to 1 and a DATO or
DATOB cycle to memory occurs, wrong

parity data will be written into the parity
MOS RAMs. This bit may be used to
check the parity error logic as well as
failed address information in the CSR.
The following diagnostic is applicable.

1. With bit 02 set, write entire memory
with any pattern.

5 Read first location in memory. If bit 00

of the CSR is set, then a parity error

indication will be detected on the LSI11 bus and the failed address (loca-

tion 0) will be stored in the CSR.

3 Read the CSR and obtain the failed

address. CSR bit 14 = 1 implies
A11-A17 on CSR bits 05-11. CSR bit
14 = 1 implies A18-A21 on CSR bits
05-08. Bit 02 is a read/write bit reset
to zero on power up or BUS INIT.

Not used

Parity error enable

If a

parity

error occurs

DATI

DATIO(B) cycle to memory and bit 00 is set
— 1, then BDAL 16 (L) or BDAL 16 (L) and
BDAL 17 (L), jumper selectable, will be asserted on the bus simultaneously with data.
This is a read/write bit reset to zero on
power up or BUS INIT.

848

MSV11-P/M806

MSV11-P MOS MEMORY

GENERAL

MSV11-P Modules

Model

Memory

Capacity

MOS

Chips

Module

Number

of Rows | of Chips

MSV11-PL | 512K bytes | 64K X 1 | M8067-LA | 8
MSV11-PK | 256K bytes | 64K X 1 | M8067-KA | 4
MSV11-PF | 128K bytes | 64K X 1 | M8067-FA | 8

72
36
72

MSV11-PF (Multivoltage MOS RAMs) M8067-FA Power Requirements
Standby Current(A)
Measure

Voltage

Typical

Maximum

+5 V Noncritical
+5V BBU
Total +5V
+12V

1.40
1.15
2.55
0.10

2.21
1.55
3.76
0.12

Standby Power(W)
Measure

Active Current(A)
Measure

Typical

Maximum

1.45
1.20
2.65
0.35

2.21
1.55
3.76
0.53

Active Power(W)
Measure

Voltage

Typical

Maximum

Typical

Maximum

+5 V Noncritical
+5V BBU
Total +5V
+12V
Total Power

7.00
5.75
12.75
1.20
13.95

11.60
8.14
19.74
1.51
21.25

7.25
6.00
13.25
4.20
17.45

11.60
8.14
19.74
6.68
26.42

849

MSV11-P/M8067
MSV11-PK (Single Voltage, Half Populated) M8067-KA Power
Standby Current(A)
Measure

Active Current(A)
Measure

Voltage

Typical

Maximum

Typical

Maximum

+5 V Noncritical
+5VBBU
Total +5

1.65
1.35
3.00

2.10
1.80
3.90

1.70
1.75
3.45

2.10
2.10
4.20

Standby Power(W)

Active Power(W)

Measure
Typical

Maximum

Measure
Maximum
Typical

Voltage

(5.0)

(5.25)

(5.0)

(5.25)

+5 V Noncritical
+5 V BBU

8.25
6.75

11.00
9.45

8.50
8.75

11.0
11.0

Total Power

15.0

20.45

17.25

22.0

MSV11-PL (Single Voltage, Fully Populated) M8067-LA Power

Standby Current(A)
Measure

Active Current(A)
Measure

Voltage

Typical

Maximum

Typical

Maximum

+5 V Noncritical
+5V BBU
Total +5V

1.65
1.45
10

A
1.90
0

1.70
1.85
3.60

2.10
2.20
4.30

Standby Power(W)
Measure

Typical

Maximum

Typical

Maximum

Voltage

(5.0)

(5.25)

(5.0)

(5.25)

+5 V Noncritical

8.25

11.0

8.50

11.00

+5V BBU
Total +5V

7.25
15.5

10.0
21.0

NOTE

9.25
17.75

11.55
22.55

Use the +5 V table (BOLD) for current requirements for factory configured modules.

850

MSV11-P/M8067
Diagnostic Programs
Refer to Appendix A.
Related Documentation

MSV11-P User’'s Guide (EK-MSVOP-UG)
Field Maintenance Print Set (MP-01239)

CONFIGURATION

The jumpers on the MSV 11-P memory module are divided into the following

O &~

five groups.

Starting address jumpers

CSR address jumpers
Power jumpers

Bus grant continuity jumpers
General jumpers

The location of the five jumper groups, four of which are enclosed in solid
boxes and labeled, is shown in the following figure. The remaining jumpers
are classified as general jumpers. The general jumpers are enclosed in
dotted boxes.

Configuring the Starting Address

The starting addresses for each module in the system is always selected
on 4K boundaries. The memory size of the system is determined first by its
byte content. This determines the module starting address (MSA). The first
address of range (FAR) selects the 256K word range the starting address
will fall into. This selection is described under FAR selection. The partial
starting address (PSA) selects the 8K boundary within the 256K range selected. The selection is described under the PSA selection. The following
equation is used for selecting the FAR and PSA.
Known

PSA = MSA — FAR

First Address of Range

Partial Starting Address

851

MSV11-P/M8067
MBOG7-LA
MB067-KA

ROW LATCH

r—‘—'—""_“—

WRITE WRONG

PARITY TESTING

113+

ROW 1

—~

[

PO
17

ROW 0

t
IL

T //
QJ

101/

gt R .
e ST
. 11R Pausd[]
Comroon]
=
45 43 44l L
I
U v
18/22 BIT |
279,
STARTING ADDRESS
SYSTEM i l1e

LATCH /
COLUMN
_____

Rovv3t

BBBBB
ROW 2

LATEH
oWi

ROW‘{

s | jaa | jia | fr2

r-o 15,

Ve el

15l;
H
T4
LA

oML

Tre
wo

tDA

:|
|

“J/
6)

-ETZZR

nden
o
r—w_‘A‘E-—J__‘

PL 23 20

o))

. .

JUMPERS

AT
LYy

;

H o

¢ " [T;—-‘l

of Jo-b
W3

\fi_____/

16K MULTIPLE VOLTAGE DEVICES

NONBATTERY BACKUP

BATTERY BACKUP VOLTAGES

a?l

:\/\/?O

12 vDD

64K SINGLE VOLTAGE DEVICES

NO
W4
W5

WI13/W15

GRANRT CONTINUITY
W1 AND W2 IN FOR
Q/0 MACHINE Q22/Q22

MACHINE

W1 AND W2 OUT FOR

/eh AND 022 CD
MACHINE

PASS

PRIORITIES
(EDMG, CIAK)

BATTERY BACKUP VOLTAGES
w4
W5

W12

w14

DECOUPLE +5
DECOUPLE +5
+5 vDD

MMMMMM

MSV11-P Memory Module Layout

FAR Starting Address Configurations (Part 1)

Jumpers to Ground (PinY)

First Address Ranges (FAR)

PinX

PinW

PinV

00000000-01740000
02000000-03740000
04000000-05740000

ouT
ouT
ouT

ouT
ouT
IN

ouT
IN
ouT

12000000- 13740000
14000000- 15740000

IN
IN

ouT
IN

Decimal K words

Octal K words

000-248
256-504
512-760

1280-1528
1526-1784
1742-2040

768-1016
1024-1272

(A21)

06000000-07740000
10000000- 11740000
16000000~ 17740000

852

ouT
IN
IN

(A20)

IN
ouT
ouT

(A19)

IN
ouT
IN

MSV11-P/M8067
PSA Starting Address Configurations (Part 2)
Partial Starting Address

Jumpers to Ground (Pin R)

(PSA)
PinP

PinN

PinM

PinL

PinT

Decimal K

Octal

(A18)

(A17)

(A16)

(A15)

(A14)

0
8
16
24
32
40
48
56

00000000
00040000
00100000
00140000
00200000
00240000

oOutT
oOutT
OuUT
OuT
OUT
OUT

outT
OouUtT
OUT
OouUT
OUT
OUT

00300000
00340000

OUT
OuT

OUT
OUT

out
OouUT
OUT
OUT
IN
IN
IN
IN

ouUT
OUT
IN
IN
outT
OUT
IN
IN

OoUuUT
IN
ouT
IN
ouTt
IN
ouT
IN

64
72
80
88
96
104
112
120

00400000
00440000
00500000
00540000
00600000
00640000
00700000
00740000

OUT
OUT
OUT
OUT
OuT
OUT
OuUT
OUT

IN
IN
IN
IN
IN
IN
IN
IN

ouT
OuUT
OUT
OUT
IN
IN
IN
IN

ouT
OUT
IN
IN
outT
OUT
IN
IN

ouTt
IN
ouT
IN
ouT
IN
ouT
IN

128
136
144
156
160
168

IN
IN
IN
IN
IN
IN
IN
IN

OutT
OuT
OuT
OUT
OuUT
OUT
OuT
OuT

OouUT
OuUT
OUT
OUT
IN
IN

176
184

01000000
01040000
01100000
01140000
01200000
01240000
01300000
01340000

IN
IN

ouUT
OoUT
IN
IN
outT
OUT
IN
IN

ouUT
IN
ouT
IN
ouT
IN
ouT
IN

192
200
208
216
224

01400000
01440000
01500000
01540000
01600000

IN
IN
IN
IN
IN
IN
IN
IN

outT
OuUT
OUT
OUT
IN
IN
IN
IN

ouT
OUT
IN
IN
ouT
OUT
IN
IN

ouT
IN
ouT
IN
ouT
IN
ouT
IN

232
240
248

01640000
01700000
01740000

853

MSV11-P/M8067
Control Status Register (CSR) Jumpers

The bus masEach MSV11-P memory module has a control status register.
CSR is a 16-bit regis-

ter can read or write the CSR via the LSI-11 bus. The
ter whose address falls in the top 4K of system address space.

module has four CSR jumper pins (A, B, C, and D) that can be

Each memory
daisy-chained to pin E (the ground pin). The jumpers allow logic to detect a
specific CSR address that has been assigned to a CSR memory module.
The user determines which type of bus the module is being installed and
connects the jumpers for each address as described in the following table.
CSR Address Selection
Extended

LSI-11

Jumper to Ground (Pin E)

Number | Address

Address

17772100
17772102
17772104
17772106
17772110
17772112
17772114
17772116
17772120

772100
772102
772104

ouT
ouT
ouT
ouT
OouT
OuT
ouT
ouT
IN

ouT
ouT
ouT
ouT
IN
IN
IN
IN
ouT

ouT
ouT
IN
IN
ouT
ouT
IN
IN
ouT

ouT
IN
ouT

Module

1
2
3

4
5
6
7
8
g

10
11
12
13
14
15
16

LSI-11
Bus

17772122
17772124
17772126
17772130
17772132
17772134
17772136

Bus

772106
772110
772112
772114
772116
772120

772122
772124
772126
772130
772132
772134
772136

IN
IN
IN
IN
IN
IN
IN

ouT
OouT
ouT
IN
IN
IN
IN

ouT
IN
IN
ouT
ouT
IN
IN

IN
ouT
IN
ouT
IN
ouT

IN
ouT
IN
ouT
IN
ouT
IN

Power Jumpers

The power jumpers are divided into the following two groups.

16K multiple voltage devices (M8067-FA) with or without battery
backup

2. 64K single voltage devices (M8067-LA and M8067-KA) with or without
battery backup

854

MSV11-P/M8067
Power Jumpers

16K Multiple Voltage Devices
Nonbattery Backup

Battery Backup

Voltages

—5

Wit

W10

+ 12 VDD

W13

W12

+5 CR

64K Single Voltage Devices

Nonbattery Backup

Battery Backup

Voltages

W4
W5
W9

W4
W5
Wi2

Decouple +5
Decouple +5
+5 CR

+5 VDD

W14

Wi13/W15

Bus Grant Continuity Jumpers

To install W1 and W2 in your system, identify the backplane bus structure
as AB/AB or AB/CD. The jumpers are installed for an AB type backplane
and removed for a CD type backplane as described below.

Bus Grant Continuity

Backplane

Bus Type

H9270 (4 slot backplane)
H9275 (9 slot backplane)
H9273 (4 slot backplane)
H9276 (9 slot backplane)

AB/AB
AB/AB
AB/CD
AB/CD

IN
IN
ouT
ouT

855

MSV11-P/M8067
General Jumpers

The general jumper group and their functions that have not yet been covered are described below.
General Jumpers
Pin

Numbers

Function

6 to 7

In - write wrong parity

8to 7

in - disables wrong parity

2toY

2 to Y out - 22-bit machine

43 to 44
45 to 44

2 to Y in - 18-bit machine

In - single voltage MOS RAM access time (150 ns
device)

In - multiple voltage MOS RAM access time (200

ns device)

22 to 23

Not used

21 to 23

Not used

F to H

F to Hin - connected to force the starting address
to 16K

F to H out - disables force function

3to9

3 to 9 in - connected on 16K and 64K MOS chip

13 to 15

Connected on 16K and 64K MOS chip

4 to 10

Connected only on 64K MOS chip

14 to 16

Connected only on 64K MOS chip

856

MSV11-P/M8067
CONTROL STATUS REGISTER (CSR) BIT ASSIGNMENT
The control status register (CSR) in the MSV 11-P allows program control of
certain parity functions and contains diagnostic information if a parity error

has occurred. The CSR is assigned an address and can be accessed by a
bus master via the LSI-11 bus. Some CSR bits are cleared by assertion of

BUS INIT L. The CSR bit assignments are as follows.

Al4 | A13

A12

| AT

USED

JUSED

A21

PARITY
ERROR

A20 | A19 | A18

|USED

WRITE

EXTENDED

USED

Y
ERROR ADDRESS

NOT

NOT | NOT |\ A47 | A16 | A15 | OR | OR | OR | oRr | NOT | NOT

PARITY
ERROR

ENABLE

WRONG
PARITY

CSR READ
ENABLE

(CSR) Bit Assignment

CSR Bit Descriptions

Bit

Name

Description

Parity error

This bit set indicates that a parity error has occurred. The bit then turns on a red LED on the
module. This provides visual indication of a
parity error.

Bit 15 is a read/write bit. It is reset to zero via
power-up or BUS INIT and remains set unless
rewritten or initialized.
The use of this bit is explained in the error ad-

read enable

dress description.

Bit 14

Extended CSR

0, always for 128K word machine

Bit 14 = 0, first read on 2048K word machine

Bit

machine
13, 12

Not used

857

second read

on 2048K word

MSV11-P/M8067
CSR Bit Descriptions (Cont)
Bit

Name

11-05

Error address

Description

If a parity error occurs on a DATI or DATIO(B)

cycle, then A11-A17 are stored in CSR bits
05-11 and bits A18-A21 are latched. The
128K word machines (18-bit address) require
only one read of the CSR register to obtain the
failed address bits. CSR bit 14 = O allows the
logic to pass A11-A17 to the LSI-11 bus. A
2048K word machine (22-bit address) requires
two reads. The first read CSR bit 14 = 0 sends
contents of CSR bits 05-11. Then the program

must set CSR bit

14 =

1. This enables

A18-A21 to be read from CSR bits 05-08.

The parity error addresses locate the parity error to a 1K segment of memory. These are
read/write bits and are not reset to zero via
power-up or BUS INIT. If a second parity error
is encountered, the new failed address is
stored in the CSR.

04, 03

Not used

Write wrong

parity

If this bit is set equal to 1 and a DATO or
DATOB cycle to memory occurs, wrong parity
data is written into the parity MOS RAMs. This
bit can be used to check the parity error logic
as well as failed address information in the
CSR. The following diagnostic is applicable.
1. With bit 02 set, writes entire memory with
any pattern.

2 Read first location in memory, if bit 00 of
the CSR is set, then a parity error indication is detected on the LSI-11 bus, and
the failed address (location 0) is stored in
the CSR.

3. Reads the CSR and obtains the failed ad-

dress: CSR bit 14 = O implies A11-A17 on
CSR bits 05-11. CSR bit 14 = 1 implies
A18-A21 on CSR bits 05-08. Bit 02 is a

858

MSV11-P/M8067
CSR Bit Descriptions (Cont)
Bit

Name

Description
read/write bit reset to zero on power-up or

BUS INIT.

Not used

Parity Error

If a parity error occurs on a DATI or DATIO(B)

Enable

cycle to memory, and bit 00 is set equal to 1,

then BDAL 16 L and BDAL 17 L are asserted
on the bus simultaneously with data. This is a
read/write bit reset to zero on

BUS INIT.

859

power-up or

MXV11-AA,AC/M8047

MXV11-AA,AC MULTIFUNCTION MODULE

2,
The MXV11 is a multifunction option module used for the LSI-11, LSI-11/
readfor
ns
provisio
memory
te
or LSI-11/23 systems. It contains read/wri
only memory, two asynchronous serial line interfaces and a 60 Hz clock
derived from a crystal oscillator.

Detailed technical information is beyond the scope of this document. Additional information can be found in the Microcomputer Processor Handbook,
EB-18451-20.

Model Designations

e MXV11-AA contains 8K bytes of random access memory.
e MXV11-AC contains 32K bytes of random access memory.

Both models have two 24-pin sockets that provide for +5V read-only memories in which 1K X 8, 2K X 8, or 4K X 8 ROMs may be used. These sockets may also be used for 256 words of bootstrap code.

+5
1.2

Cables

Bus Loads

Amps

412
0.1

AC
2

BC20M-XX
BC20N-XX (Refer to DLV 11-KA)

DC
2

BC21B-XX

Standard Addresses

RAM - Starts on any 8K boundary below 64KB.
SLU

Channel O

Channel 1

176500

177560

To disable RAM

MXV11-AC = Remove W4

MXV11-CA = Remove W5
860

MXV11-AA,AC/M8047
Standard Vectors
SLU

300

Diagnostic Programs
Refer to Appendix A.

Requires wraparound connectors to completely exercise SLU.
Related Documentation

MXV11-A Memory and Asynchronous Serial Line Interface User Guide (M8047)
(EK-MXV1A-UG)

Field Maintenance Print Set (MP-00730)
Options

MXV11-A2 Boot ROMs for RX02, RX01, or TUS8
PNs: 23-131F3-00, 23-132F3-00
ROMs

Power:

+5V + 5%

Pins:

24-Pin DIP

Access Time:

Up to 450 nanoseconds

Array Size:

1K X 8, 2K X 8, or 4K X 8 bits

Type:

Typical PROM types:

Chip

UV PROMs

Array Size

Memory Size

intel 2758

1K X 8 bits

1K words

intel 2716

2K X 8 bits

2K words

Intel 2732
Mostek MK27 16
T.I. TMS 2516
T.I. TMS 2532

4K X 8 bits
2K X 8 bits
2K X 8 bits
4K X 8 bits

4K words
2K words
2K words
4K words

1K X 8 bits
1K X 8 bits
1K X 8 bits
2K X 8 bits

1K words
1K words
1K words
2K words

Bipolar PROMs

Intel 3628
Signetics 825 2708
Signetics 825 181
Signetics 82S 191

861

MXV11-AA,AC/M8047

—

CHANNEL 1

CHANNELO

J66 J65

JBB A

AAAAA

JB7 A

J64 J63 J62 J61 J60 J59

A J58

A J57
A JB6

A J55
A J54

A J53

A J52
A JB1

A J50
« Jag

A J4s
iJ47
J46

A J44
A J43

imz
Ja1

L J40

A J39
A J38

AJ37

AJ36
iJ35
A

J34

AJ29

A J28
A J27
A J26

N
424

A 432

AJd31
A J30

Ay23
2422
21

A J20
AJ19

ifla
J17

AJ16
AJ15
A J14
AJ13
A J12

AJ11

AJ10

A J9

A J8
J7
A

J6J5 JaJ3

—

A
MR-3266

MXV11-A Jumper Locations

862

MXV11-AA,AC/M8047
MXV11-A Jumper Functions
Pin

Function

Option

Clock L. Open collector output of the clock.

60 Hz

Connected to pin AF1 (SSpare 2). Wirewrap to J4
to implement the clock option.

BEVNT L. Event interrupt (pin BR1) used for the

60 Hz

clock option.
J5

BDCOK H. DCOK (pin BA1) when high allows the pro-

Boot

cessor to operate; when low initializes the system.

Connected to J6 to use the boot option.
J6

Framing Error. Open collector output of framing

Break

error from serial line one. Connected to pin AE1

(SSpare 1). Wirewrap to J5 to implement the boot
option. Reset by bus initialize or reception of
a valid character.
J7

BHALT L. Halt (pin AP
1) when low will stop pro-

Halt

gram execution and cause the processor to enter

ODT microcode. Connected to J6 to implement the
halt option.

GND. A ground signal that can be used to disable

ROM

ROM by wirewrapping to J21 or to disable a serial

line by wirewrapping to an address input pin (J23
or J24 for serial line 0; or 425, J26, J27, or J28

for serial line 1).
J9

A13 L. Address bit 13 asserted low. Wirewrap to

ROM

J11 to select bank 1 with the ROM address decoder.
J10

A13 H. Address bit 13 asserted high. Wirewrap to
J11 to select bank 0 with the ROM address decoder.

ROM

J11

A13 M. Address bit 13 input to the ROM address
decoder. See J9 and J10. Used only if J20 is

ROM

wirewrapped to J21.
J12

AO3 H. Address bit 03 asserted high. Wirewrapped
to the serial line address decoders (J23 or J24 for
serial line 0, J25, J26, J27 or J28 for serial line
1) when address bit 03 is to be decoded as a 1.

863

SLU

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Option

Function

J13

AO4 H. Address bit 04 asserted high. Wirewrapped

to the serial line address decoders when address
bit 04 is to be decoded as a 1.

Ji14

AO5 H. Address bit 05 asserted high. Wirewrapped
to the serial line one address decoder when address
bit 05 is to be decoded as a 1.

J15

AO09 H. Address bit 9 asserted high. Wirewrapped
to the serial line one address decoder when address

SLU

AO9 L. Address bit 09 asserted low. Wirewrapped
to the serial line one address decoder when address

SLU

AO5 L. Address bit 05 asserted low. Wirewrapped
' to the serial line one address decoder when address

SLU

' AO4 L. Address bit 04 asserted low. Wirewrapped
to the serial line address decoders when address

SLU

' AO3 L. Address bit 03 asserted low. Wirewrapped
to the serial line address decoders when address

SLU

bit 09 is to be decoded as a 1.
J16

address bit 09 is to be decoded as a 0.

J17

. bit 05 is to be decoded as a O.
J18

bit 04 is to be decoded as a 0.

bit 03 is to be decoded as a 0.

J20

ROM address. Output of the ROM address decoder.
Connected to J21 when ROM is to be used in bank O

ROM

ROM select. ROM address selection enable asserted
high. Wirewrapped to J8 (GND) to disable ROM, to

ROM

Boot address. Output of the bootstrap address

BOOT

or bank 1.
J21

J20 for bank O or bank 1, or to J22 for bootstrap.
J22

decoder. Connected to J21 when ROM is to be used
in the bootstrap range from 173000-173776 (773000~
773776 for LSI-11/23).

J23

Serial line 0 address decoder input asserted high.
May be wirewrapped to AO3 H (J12), AO3 L (J19),
AO4 H (J13), or AO4 L (J18).

864

SLU

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Pin
J24

Function

Option

Serial line 0 address decoder input asserted high.

SLU

May be wirewrapped to AO3 or A0O4, whichever bit is

not wired to J23. May be wirewrapped to GND (J8)

to disable serial line O.
J25-.
J28

J29

Serial line 1 address decoder input asserted high.
Four address decoder inputs to be connected to
address bits A03, A0O4, A05, and A09. Whether the
high or low assertion state of a bit is wirewrapped
to an input determines if that bit is decoded as a
1 ora0. See J12 through J19. May be wirewrapped
to GND (J8) to disable serial line 1.

SLU

ROM address bit 09 input. Wirewrapped to AO9 H
(J15) for normal ROM addressing and also for the
MXV11-A2 option when the TU58 bootstrap is desired.
Wirewrapped to A09 L (J16) for the MXV 11-A2 option

ROM

RAM starting address selection. These pins are

RAM

when the disk bootstrap is desired.
J30J32

wirewrapped to J33 (logic 0) or J34 (logic 1) to
select the RAM starting address (see the following).
Bank

Address

A WN=O

=m0

J30

’. O

OO0
=
OO
m
"’

. w0000
. m
J33

J31

000000

~NO

Starting

J32

140000

020000
040000
060000
100000
120000
160000

GND. Logic 0 level signal used for selecting the

RAM,

RAM starting address and for enabling some ROM ICs

ROM

+3V. Logic 1 level signal used for selecting the

RAM,

in the ROM sockets.

J34

RAM starting address and for enabling some ROM ICs
in the ROM sockets.

865

ROM

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)

Option

Function

J35 | A12 H. Address bit 12 asserted high. Used for

addressing 4K X 8 bit ROMs. Wirewrapping to J37,

ROM

J38 or J39, depending on the ROM used.

J36 | A11H. Address bit 11 asserted high. Used for

ROM

J37 | Pin 18 on both ROM sockets. Used for addressing

ROM

J38 | Pin 19 on both ROM sockets. Used for addressing

ROM

J39 | Pin 21 on both ROM sockets. Used for addressing

ROM

addressing 2K X 8 and 4K X 8 bit ROMs. Wirewrapping to J37, J38, or J39, depending on the ROM.
or enabling ROM. Wirewrapped to J33 for ground,
to J34 for + 13V, to J35 for A12, or to J36 for A11.
or enabling ROM. Wirewrapped to J33 for ground,
to J34 for -3V, to J35 for A12, or to J36 for A11.

or enabling ROM. Wirewrapped to J33 for ground,
to J34 for +3V, to J35 for A12 to J36 for A11 or
to J40 for +5 V.

J40 | +5 V. Used to power some ROMs on pin 21.

ROM

J4a1 | Used for 150 baud. Wirewrapped to J45 for serial

SLU

line 0, to J46 for serial line 1. (See following

table.)

J42 | Used for 1200 baud.

SLU

J43 | Used for 300 baud.

SLU

J44 | Used for 2400 baud.

SLU

J45 | Clock 0. The clock input for serial line O transmit

SLU

J46 | Clock 1. The clock input for serial line 1 transmit

SLU

J47 | Used for 4800 baud.

SLU

J48 | Used for 9600 baud.

SLU

and receive, 16 times the baud rate. Wirewrapped to
either J41, J42, J43, J44, J47, J48, J49, or J50.

866

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Pin

Function

Option

J49

Used for 19.2K baud.

SLU

J50

Used for 38.4K baud.

SLU

J51

Vector 0. Vector enable for channel 0. Used to
drive vector bits that pass the test: logic 1 for

SLU

channel O, and logic O for channel 1. Wirewrapped
to J53 for bit 03, to J54 for bit 04, to J55 for
bit 05, to J56 for bits 06 and 07.
J52

Vector 1. Vector enable for channel 1. Used to
drive vector bits that pass the test: logic O for

SLU

channel O and logic 1 for channel 1. Wirewrapped
to J53 for bit 03, to J54 for bit 04, to J55 for
bit 05, to J56 for bits 06 and 07.
J53

Vector bit 03. Selects how bit 03 is to be driven
for interrupt vectors. Wirewrapped to J51 if a
logic 1 for channel 0 and a logic O for channel 1;
to J52 if a logic O for channel O and a logic 1 for
channel 1: to J57 if a logic O for both channel O
and channel 1; or to J58 if a logic 1 for both

SLU

channel O and channel 1.
J54

Vector bit 04. Selects how bit 04 is to be driven
for interrupt vectors. Wirewrapped the same as J53.

SLU

J55

Vector bit 05. Selects how bit 05 is to be driven
for interrupt vectors. Wirewrapped the same as J53.

SLU

Vector bits 06 and 07. Selects how bits 06 and 07
are to be driven for interrupt vectors. Wire-

SLU

GND. Logic 0O signal for configuring vector bits.
Wirewrapped to J53, J54, J55 and/or J56 when the
corresponding vector bit(s) will be logical O for

SLU

J56

wrapped the same as J53.
J57

both serial line channels.
J58

+3 V. Logic 1 signal for configuring vector bits.
Wirewrapped to J53, J54, J55 and/or J56 when the
corresponding vector bit(s) will be logical 1 for

both serial line channels.

867

SLU

MXV11-AA,AC/M8047
MXV11-A Jumper Functions (Cont)
Option

Function

J59

Seven bits parity, eight bits no parity, channel 1.
Wirewrapped to ground (J65) for seven bits with

SLU

parity or to + 3 V (J66) for eight bits with no
parity.

J60

Two stop bits. Selects one or two stop bits for
channel 1. Wirewrapped to ground (J65) for one

SLU

Even parity. Selects odd or even parity for
channel 1 when seven bits with parity (J59 wirewrapped to ground) is selected. Wirewrapped to
ground (J56) for odd parity or to +3 V (J66) for

SLU

Seven bits parity, 8 bits no parity, channel O.
Wirewrapped to ground (J65) for seven bits with

SLU

stop bit or to +3 V (J66) for two stop bits.

1
J6

even parity.

J62

parity or to +

3V (J66) for eight bits with no

parity.
J63

J64

Two stop bits. Selects one or two stop bits for
channel 0. Wirewrapped to ground (J65) for one
stop bit or to +3 V (J66) for two stop bits.

SLU

Even parity. Selects odd or even parity for
channel 0 when seven bits with parity (J59 wirewrapped to ground) is selected. Wirewrapped to
logic 0 (J65) for odd parity or to logic 1 (J66)

SLU

for even parity.
J65

Logic 0. Ground signal used for configuring

SLU

serial line interfaces.
J66

Logic 1. 4+ 3 V signal used for configuring line

SLU

interfaces.
J67

J68

Clock in. Clock input for baud rates, memory

SLU

Clock out. Crystal oscillator output at 19.6608

SLU

refresh and negative voltage generator. Wirewrapped to J68. Not a user option.

MHz. Wirewrapped to J67. Not a user option.

868

MXV11-AA,AC/M8047
Standard Factory Configuration

Function
RAM Bank O

SLU Channel O Address 176500

SLU Channel 1 Address 177560

Wirewrap

Pins

Wirewrap

From

Level

J30

J31

J32

J33

J31

J32

J23

J18

J24

J19

J28

J19
J15

L2
L1

J25

J14

J27

J13

J26

ROM Bootstrap (TU58)

J37

J38

J21

J22

J34

J37

J33

J39

J29

J15

J53

J57

J54

J52

J56

J51

J54

J55

J59
J62

J6 1
J64

L1
L1

J60
J6 1

J63

J62

J59

J66

J63

J65

Baud Rates CHO (38.4K)
CH1 (9600)

J45
J46

J50
J48

LA
L1

Break Generation

J68

J67

SLU Vectors CHO (300)
CH1 (60)

SLU Parameters (8 Data Bits,
No Parity, 1 Stop Bit)

(Halt Option)

Crystal Clock

869

MXV11-AA,AC/M8047
Configuring the RAM

The RAM can be configured to start on any 8KB boundary below 64KB. Be-

cause of this restriction, the MXV 11 (8KB version) is not usable for memory,

above 56KB. The MXV 11 can be used in 18-bit memory address systems

but it is restricted to being assigned to the memory area at or below 56KB.
Five wirewrap terminals, J30 through J34, select the starting address. The
following figure shows the jumper configurations required to obtain the desired starting addresses.

0 @ FACTORY CONFIGURED

= CONNECT JUMPER TO J34
2 = CONNECT JUMPER TO J33
1

RAM Starting Address Selection
Configuring the ROM

Depending on the ROM type, the module’s capacity is 1K, 2K, or 4K words

using a pair of 1024 X 8-, 2048 X 8-, or 4096 X 8-bit ROMs respectively.
The user configures jumpers on the module for the ROM type being used.
The actual procedure for loading data into EPROMs, PROMs (or writing

specifications for masked ROMSs) will vary depending on the manufacturer,
and is beyond the scope of this section. The user must refer to the manufacturer's data sheets and to the chapter, “Using PROMs” in the Microcomputer Processor Handbook, EB-18451-20. The user must be aware of
the relationship of the EPROM, PROM, or ROM pins to the LSI-11 data bits,
and the relationship of the pins to the memory address bits. Refer to the
following figure for ROM socket pin assignments. All ROMs used on the
MSV 11-A must conform to these pin assignments.

The factory configuration allows for using the MSV 11-A2 bootstrap ROMs.
Configuring the Bootstrap ROM - The ROM can be configured to operate
in the 1/0 page to support bootstrap programs. The address area contains
256 words from 173000 to 173776 (773000 to 773776 for the LSI-11/23).
The MXV11-A is configured at the factory to allow for using the MXV11-A2
TU58 bootstrap. To reconfigure the MXV11-A to use the disk bootstrap, remove jumper J29 to J15 and install jumper J29 to J16.

870

MXV11-AA,AC/M8047

A08 H []1

24 ] Vee

A07
H[ 2

23—
J29

A06 H [] 3

A05
H [} 4

21—
439

] A10
H

AO4 H[]5

L
20 ] ROM

AO3 H[]6

19—
J38

A02 H [ 7

J37
[
18 F—{X)

A0t HE]8

17 ] D07H

(D15 H)

(D08 H) DOO H [19

16 L] D06 H

(D14 H)

(D09 H) D01 H []10

5[] D05 H

(D13 H)

[N
H
(D10 H) DO2

147)D0O4H

(D12 H)

GND [J12

13[J D03 H

(D11 H)

NOTE:

DATA OUT PINS SHOWN IN PARENTHESES
REFER TO THE HIGH BYTE SOCKET

XE67.

DATA QUT PINS DOO H THROUGH D07 H
REFER TO THE LOW BYTE SOCKET XE57.
MR-3267

MXV11-A ROM Socket Pin Assignment

ROM Bank Selection — If the MXV 11-A sockets are used for program ROM
instead of a bootstrap ROM, the memory must be selected by a jumper connecting J20 to J21. When main ROM memory is selected, the entire 4K
word bank is enabled. If a 1K or 2K ROM is used, it will “‘wraparound’ and
give invalid data, depending on how the address lines are configured when
the nonexisting ROM area is addressed. Main memory may be positioned in
bank O or bank 1. To position the ROM in bank O, jumper J10 to J11. To
position the ROM in bank 1, jumper J9 to J11.

Configuring the Specific ROM Types — Additional jumpers must be connected depending on the type of ROM used. The “EPROM Address Jumpers’’ table describes the jumper configuration when using typical ROMs
such as the Intel 2716 (2K X 8) or 2732 (4K X 8) EPROMs. The user must
refer to the manufacturer’s data sheets when configuring jumpers for other
ROM types.

The function of wirewrap pins J29, J38, J37, and J39 are shown in the following table. These pins are to be connected as required to pins J33
through J40.

ROM Upgrade Part Numbers
23-131F3-00
23-132F3-00

871

MXV11-AA,AC/M8047
EPROM Address Jumpers

2716 ROM

2732 ROM

Bank 1

Bank O

Bank 1|

Bank O

Function

Fromjto

Bank Enable
Bit 09 Input
Address or Enable
Address or Enable
Address or Enable

J20 1 J21
J29 1 J15
1J36
J38
1J33
J37
|J40
J39

J21
J15
J36
J33
J40

J21
J15
J36
J35
J33

J21
J15
J36
J35
J34

CONFIGURING THE SERIAL LINE UNITS
Serial Line Register Address Selection
Four device registers (RCSR, RBUF, XCSR, and XBUF) are provided for
each of the two serial lines. Jumpers are configured to establish separate
base addresses for each serial line as shown.

Serial port 0 may be assigned to one of the four starting addresses:
176500, 176510, 176520, 176530.

Serial port 1 may be assigned addresses in two ranges. The first range
starts at 176500 and covers the eight starting addresses from 176500

to 176570. The second range starts at 177500 and also contains eight
possible starting addresses, including the standard console address,
177560. Since several other standard DIGITAL devices use addresses
in this second range, it is recommended that only the console address
be used.

The format of an SLU address is shown in the following figure. Note that bits
13-17 are neither configured nor decoded by the MXV11-A module. These

bits are decoded by the bus master module as the bank 7 select (BBS7 L)
bus signal. This signal becomes active only when the I/O page is accessed. Bit 0 is used as the byte pointer.
00 = RCSR

01 = RBUF
1 = RANGE 2
BANK SELECT 7

A17

16
T

15
T

14
l

13
T

10 = XCSR

0 = RANGE 1

11 = XBUF

12
T

11
T

10
T

09
T

07
T

]

06
T

04
T

03
T

[ . i

]

01
T

00
T

NOTE:
JUMPER POSTS ARE WIRED TO A HIGH

SERIAL LINE O

J23

J24

1 =HIGH BYTE

0=LOW BYTE

)28

ADDRESS LINE FOR A1 AND TO A LOW
ADDRESS LINE FOR A 0. REFER TO

TABLES 7 AND 8 FOR JUMPER CONFIGU-

126

SERIAL LINE

RATIONS.
MR 3268

MXV11-A SLU Address Format

872

MXV11-AA,AC/M8047
Bits 1 and 2 select one of the four device registers within the addressed
serial line. Bits 3 and 4 are used to select one of four possible device addresses for serial line 0. Bits 3, 4, 5, and 9 are used to select the device

addresses in two ranges for serial line 1 (console). The following table describes the jumper combinations to select one of four device addresses for

serial line 0 (1/0).

Serial Line O Address Jumpers
Address

Jumper Posts

(Octal)

J23 to

J24 to

176500

J18 (Logic 0)

J19 (Logic 0) Factory Configuration

176510

J18 (Logic 0)

J12 (Logic 1)

176520

J13 (Logic 1)

J19 (Logic 0)

176530

J13 (Logic 1)

J12 (Logic 1)
NOTE

Logic 1

Logic O

J13 (AO4 H)

J18 (AO4 L)

J12 (AO3 H)

J19 (AO3 L)

Serial line 1 may have 16 possible device addresses in two ranges. The
following table describes the jumper combinations to select the eight de-

vice registers available in range 1. Only one device address is used in
range 2.

Serial Line 1 Address Jumpers

Address

Jumper Posts

(Octal)
Range 1

J26
to

J25
to

J27
to

J28
to

176500
176510

J16
J16

J17
J17

J18
J18

J19
J12

176520
176530
176540
176550
176560
176570

J16
J16
J16
J16
J16
J16

J17
J17
J14
J14
J14
J14

J13
J13
J18
J18
J13
J13

J19
J12
J19
J12
J19
J12

J15

J14

J13

J19

Range 2
177560

)

(See the following Note.)

873

MXV11-AA,AC/M8047
NOTE

Factory configurations use only one address in range 2 to

avoid possible device conflicts. The remaining addresses are
pre-assigned to other devices.

Logic O
J16 (AO9 L)
J17 (A0S L)
J18 (AO4 L)
J19 (AO3 L)

Logic 1
J15 (AO9 H)
J14 (AO5 H)
J13 (AO4 H)
J12 (AO3 H)

Control/Status Register

The MXV11-A has two control/status registers (CSRs) for each of its two
serial line units. The following figure shows the control/status registers
and the read/write data registers. Transmitter control/status registers O
and 1 (XCSRO and 1) and receiver control/status registers 0 and 1 (RCSRO
and 1) operate with serial lines O and 1, respectively.

Both serial line units have the same bit assignments. There are four registers for each serial line. They are sequential in this order: O, receiver status: 2, receiver data; 4, transmitter status; and 6, transmitter data. All
unused bits are read as O.

874

MXV11-AA,AC/M8047

14
¥

RCSR l 0

fon

13
I

12
1

11
¥

10
1

09
1

{

08
T

]

0 l

;

v} 1

(NOT USED)

]

RECEIVER

(NOT USED)

DONE

(READ ONLY)
RECEIVER
INTERRUPT

ENABLE

(READ/WRITE)

RBUF

{

‘

ERROR

FRAMING

(READ

ERROR

ONLY)

{READ

]

(READ

ONLY)

XCSR 0
A,

]

BBIT DATA
IS RIGHT JUSTIFIED.)
IFBIT UNUSED
=0
(READ ONLY)

ONLY)

14
T

ONLY)
OVERRUN
PARITY

(READ

RECEIVE DATA
(7,

ERROR

NOT USED

ERROR

13
H

]

)

(NOT USED)

l
4

}

(NOT USED)

l
A l

Y’

TRANSMIT

TRANSMIT BREAK

READY

(READ/WRITE)

(READ ONLY)
TRANSMIT

INTERRUPT
ENABLE

(READ/WRITE)

XBUF! 0
i,

]

{NOT USED)

}

.
&

TRANSMIT DATA
(7,8BIT DATA IS RIGHT JUSTIFIED.)

NOTE

(WRITE ONLY) ON READ =0

ONE OF FOUR CHANNELS SHOWN.

FORMAT THE SAME FOR ALL CHANNELS.
MR .5534

MXV11-A SLU CSR Formats

875

MXV11-AA,AC/M8047
Bit Assignments for the Receiver Status Register
Bit

Function

Interrupt enable, read/write. A 1 enables receiver interrupts, a 0

disables interrupts. Cleared by initialize.

Receiver done, read only. A 1 indicates that the serial interface
has received a character. If enabled by bit 6, receiver done will
request an interrupt. Receiver done is cleared by reading the receiver data register or by initialize.

Data bits, read only. Bit O is the least significant bit and bit 7 is
the most significant. If seven data bits plus parity is selected, bit
7 will always read as a 0.

Parity error, read only. A 1 indicates that the word being read in
bits O through 6 has a parity error. Bit 12 will always read O when
eight data bits and no parity are selected. Cleared when read, or
by initialize.

Framing error, read only. A 1 indicates that a start bit was detected, but there was no corresponding stop bit. A framing error
will be generated when a break is received. Cleared when read,
or by initialize.

Overrun error, read only. A 1 indicates that a word in the receiver
buffer had not been read when another word was received and
placed in the receiver buffer. Cleared when read, or by initialize.
15

Error, read only. A 1 indicates that one or more of bits 12, 13, and
14 are 1. Cleared when read, or by initialize.

876

MXV11-AA,AC/M8047
Bit Assignments for the Transmitter Status Register
Bit

Function

)

Break, read/write. When set to a 1, bit O causes the serial output

signal to go to a space condition. A space condition longer than
a character time causes a framing error when it is received and
is regarded as a break. Cleared by writing a O, or by bus initialize.

Interrupt enable, read/write. A 1 enables transmitter interrupts; a

O disables interrupts. Cleared by initialize.
7

Transmitter ready, read only. A 1 indicates that the serial interface is ready to accept a character into the transmitter data register. If enabled by bit 6, transmitter ready will request an interrupt. Transmitter ready is cleared when data is written into the
transmitter data register. It is set by initialize.

0-7

Data bits, write only. Bit O is the least significant bit and bit 7 is
the most significant bit. If seven data bits plus parity are selected, bit 7 will not be transmitted. The transmitter data register
will read all Os.

interrupt Vector Selection

Two consecutive interrupt vectors (one for receive and one for transmit)
are provided for each of the two serial lines. The interrupt vector format is

shown in the following figure. Each SLU port can be independently configured to operate in one of two ranges: 000 to 074, or 300 to 376.

NOTE

BITS 3 THROUGH 7 MAY BE WIRED

TO ONE OF FOUR WIREWRAP POSTS
JB1 {VEC 0}, J52 (VEC 1), J67 (GND)
OR J58 (+3 V)

MXV11-A Interrupt Vector Format

The following table lists the vector addresses that may be assigned to the
serial lines. Note that all vector addresses in the 000 to 074 range, except
060, are reserved vector locations. The jumper selectable bits are 3
through 7. Bits 6 and 7 are wired together.

877

MXV11-AA,AC/M8047
Serial Line Vector Addresses

Serial Line 1 (Console)

Serial Line O (I/0)

000
010
020 DIGITAL Reserved
030 Do not use
040
050
060 Console

300
310
320
330
340
350
360
370

070 DIGITAL Reserved

The following example illustrates the procedure for configuring the vector
addresses. Assume that 60 is the address for serial line 1 (console) and
310 is the address for serial line 0 (I/O). The example describes the rela-

tionship between the vector bases, vector address bits, and the jumper
posts. The jumpers are configured using the following four rules.
1. If a bit = 1 in both vector bases, it is tied to J58 (logic 1).
If a bit = O in both vector bases, it is tied to J57 (logic 0).
3 If a bit = 1 for serial line 1 and a O for serial line 0, it is tied to J52
(vector 1).

4. If a bit = O for serial line 1 and a 1 for serial line O, it is tied to J51
(vector 0).

interface Connector Pins

Two 10-pin connectors (one for each serial line) are provided on the
MXV11-A module. Connector pins and signal functions are described in the

following table and shown in the following figure.

TYPICAL INTERFACE

CONNECTOR
1 0OF
2

O
4

0
2

|
\

\\l

NO PIN
(FOR CABLING
INDEXING)

TOP OF
MXV11-A
MODULE
MR-3265

MXV11-A Connector Pins

878

MXV11-AA,AC/M8047
MXV11-A |/O Connector Pin Functions
Pin | Signal
1

Function

UART CLOCK]The baud rate clock appears on this pin. When an internal baud rate is selected, this pin is a TTL output,

When no baud rate is selected on the module, this is
an external baud rate input. The high level for the
clock > 3.0 V.

GND

XMIT +

GND

6
7
8

NC
RCV —
RCV +

GND

| +12V

Transmitter output

Key, pin not provided
Receiver input most negative
Receiver input most positive

Power for the DLV 11-KA option

Current Loop

The MXV11-A module can interface with 20 mA active or passive current
loop devices when used with the DLV 11-KA option. This option consists of
a DLV11-KB (EIA to 20 mA current loop converter) and a BD21A-03 interface cable. The MXV 11-A does not have the capability to support the reader-run portion of the DLV 11-KA option. The DLV 11-KA option is placed between the MXV11-A serial line output and the 20 mA current loop
peripheral device.

MXV11-A Interface Cables
Cable
BC21B-05

Application

Length

EIA RS-232C modem cable to interface with
modems and acoustic couplers (2 X 5-pin

1.5m (5 ft)

EIA RS-232C null modem cable to directly

1.5 m (5 ft)

AMP female to RS-232C male).
BC20N-05

interface with a local EIA RS-232C terminal

(2 X 5-pin AMP female to RS-232C female).
BC20M-50

BCO5D-10

EIA RS-422 or RS-423 cable for high-speed

15 m (50 ft)

Extension cable used in conjunction with

3 m (10 ft)

transmission (19.2K baud) (2 X 5-pin AMP
female to 2 X 5-pin AMP female).
BC21B-05.

BCO5D-25

Extension cable used in conjuntion with

7.6 m (25 ft)

BC21B-05.

BCO3M-25

“Null modem’’ extension cable used in
conjunction with BC21B-05.

879

7.6 m (25 ft)

MXV11-AA,AC/M8047
NOTE

“Strapped’’ logic levels are provided on Data Terminal Ready
s
(DTR) and Request To Send (RTS) for operation of modem
with manual provisions (such as Bell 103A data set with 804B
auxiliary set).

eral device cables and opThe MXV11-A may operate with several periph
variety of cables and opA
tions for flexibility when configuring systems. each,
are shown with the
of
tion
applica
y
primar
tions, as well as the
MXV11-A.

re, when
1 The receivers on the MXV11 have differential inputs. Therefo
the 2 X
on
7
(pin
data
receive
cable,
RS-423
or
C
RS-232
an
ng
designi
or 9) in
5,
2,
(pins
ground
signal
to
tied
5-pin AMP connector) must be

order to maintain proper EIA levels (see the following figure).
5 To connect directly to a local EIA RS-232C terminal, it is necessary to
use a null modem. To design the null modem into the cable, one must
switch received data (pin 2) with transmitted data (pin 3) on the RS232G male connector as shown in the following figure.

To mate to the 2 X 5-pin connector block, the following parts are needed:
Cable Receptacle (QTY 1)

AMP PN 87133-5

Locking Clip Contacts (QTY 9)

AMP PN 87124-1

Key Pin (pin 6) (QTY 1)

AMP PN 87179-1

DEC PN 12-14268-02

DEC PN 12-14267-00

DEC PN 12-15418-00

880

MXV11-AA,AC/M8047

EIA

RS-232C

MXV11-A

{ 5 €&

— CLEARTO SEND (CB)
1

{ 4 ¢ —! REQUEST TO SEND (CA)

GND > 9 >

— 6 €&~ — DATASET READY (CC)

—

RCV DATA > 7
+12 VDV

7500

W
1/2

10 D

204~ —! DATA TERMINAL READY (CD)

~AAA

RCV DATA > 8 >

3 ( RECEIVE DATA (BB)

XMIT DATA > 3 >

2 { TRANSMITTED DATA (BA}
— 7 { SIGNAL GROUND (AB)

GRD > 2 >

—< 1 { PROTECTIVE GROUND (AA)

(o
CABLE

MXV11-A
CONNECTOR

EIA
RS-232C

MODEM

CONNECTOR
MR-5538

B2 1B-05 Modem Cable

881

MXV11-AA,AC/M8047

MXV11-A TO MODEM OR ACOUSTIC COUPLER

46 M (15 FT)’/’!
MXVT1-A

ACOUSTIC

BC21B-05

BCO5D-10

COUPLER

BC21B-05

BCO5D-25

ODEM
OR

9.1 M (30 FT)——*] ACOUSTIC
COUPLER
DL11-D, DLVI1T,
DLV11-F

MXV11-A TO SLU CHANNEL INTERFACE

(ETA MODE)

BC20N-05
BCO1V-25

MXV11-A

BCO5C-25

RC21B-05

DL11D, DLV,

DLV11-F

(EIA MODE)

BCO3M-XX (NOTE 3)
15.2 M (50 FT)—————

mxvital_l

BLV11.

BC20M-50

M (14 FT)
42

BCQON«05£D

27 M (9 FT)—

11.8 M (39 FT)
BCO3M-25

NOTES:

1. MODEM USED IS A "MANUAL TYPE"”

]

SUCH AS BELL 103A WITH 804B.

. DEC EIS RS-232C TERMINALS (VT52,
LA36, LS120, ETC.) COME EQUIPPED
WITH A 9 FT CABLE. NON-DEC EIA

RS-232C TERMINALS ARE CONNECTED
SIMILARLY EXCEPT 9 FT OF LENGTH
MUST BE DEDUCTED FROM THE TOTAL
|95}

CABLE LENGTH.

. XX = CABLE LENGTH WHICH MUST BE
SPECIFIED WHEN ORDERING.

MR-3270

MXV11-A EIA Cable Configurations

882

MXV1i1-AA,AC/M8047

MXV11-A TO 20 MA TERMINAL
DLV11-KA

A5 A

(NOTE 3)

MXV11-A

DEC 20 MA
TERMINAL

{LA36, VT52

LA35, LS120

LA180S, ETC.)

DLV11-KA
I

BC21A-03

{:1:

DLV11-KB

LT33-DC/DD/DE
OR ASR33

WITH LT33-MD

(NOTE 2)

MODIFICATION
KIT.

DLV11-KA

N—

= T

MXV11-A

BCO5F-X

DLV11-KB |

DLV11-KB

BCO5SF-XX

DEC 20 MA

DLV11-KA

S A03

:I::}—‘ (NOTE 1)

MXV11-A TO SLU CHANNEL INTERFACE

MXV11-A

PR/SO1

TERMINALS

(LA36, VT52

—*

LS120, ETC.)

DLV11-KB

BCO5F-XX

[]
MXV11-A

)

_
BC21A-03

DLV11-J

BC21A03

DLV11-KB

]
,
[I:] BCO5M-05
O LV11.KB :D BCOSF-XX

11-C, DLV11 ,
gtvn-}:

1.PR/SO1 IS A SERIAL LINE PAPER TAPE

NOTES:

OLVIIF

LOADER.

2 MXV11-A WILL NOT SUPPORT DLV11-KA

READER RUN CIRCUITS.

3. XX = CABLE LENGTH WHICH MUST BE
SPECIFIED WHEN ORDERING.
MR-3271

MXV11-A 20 mA Cable Configurations

883

MXV11-B/M7195

8 MULTIFUNCTION OPTION MODULE

GENERAL
23 and
The MXV11-B is a multifunction option module used with the PDP-11/
bytes
128K
s
contain
memory
te
read/wri
KDJ11 processor systems. The MXV11-B
SIPS
64K
from
ed
configur
is
B
MXV11The
parity.
without
RAM
MOS
of dynamic
of memory

(single inline package). Four SIPS provide 128K bytes (64K words)
that
storage. Battery backup is supplied when jumpers are configured to enable tion
multifunc
ht,
dual-heig
This
d.
connecte
is
feature and system supplied power
module option can operate on a 22-bit Q-Bus system, (up to 316 words) on an 18and 16-bit Q-Bus system unit.
Features

W/R MOS RAM memory

5 V battery backup for MOS RAMs
Read only memory (ROM)
ROM window map logic (page control register)

Two asynchronous, serial line ports (SLUO and SLUT)
Multiple LTC frequencies
LED diagnostic display register

Electrical Specifications

Power Requirements — The following voltages are used by this module.
Pins

Voltage

Tolerance

+5V
+12 V

+5%
+5%

AA2 BA2, BV1
AD?2, BD?2

+5 VB

+5%

AV1

Power dissipated in each power supply configuration is as follows.
No battery backup

+5 V
Typ
Max

17.25 W
2457 W

+12 V
Typ
Max

0.67 W
071 W

884

MXV11-B/M7195
Battery backup configuration

+5 V

+5 VB

+12 V

Typ

12.90 W

Typ

435 W

Typ

067 W

Max

15.95 W

Max

8.60 W

Max

071 W

Data retention mode

VCC =0V, +12 V supply =0
+5 VB
Typ

4.35 W

Max

554 W

Related Documentation

MXV11-B Technical Manual (EK-MXV1B-TM)
MXV11-B User Guide (EK-MXV1B-UG)

MXV11-B2 ROM Set User Guide (EK-MXVB2-UG)

MXV11-B Multifunction Option Module User Guide (EK-MXV1B-UG)
MXV11-B Field Maintenance Print Set (MP-01469-00)

Program Options and Defaults
Address/Vector

One MXV11-B

Two MXV11-Bs

Channel 0

776500/300

Channel 1

777560/60

Channel 2
Channel 3

776510/310
776520/320

Diagnostic Programs

Test Functions

CVMX.BAO

Serial lines
ROM

Clock option

Page Control Register (PCR)
Diagnostic Display Register (DDM)
Random Access Memory (RAM)

885

MXV11-B/M7195
Default Jumpers

‘

)

5]
o

[

W10

The default jumpers are as shown below.

U T TS I P T SR B USSR

we —"

;
O
Jode

atslntelnin

]

SN s S e S
o [

3 —
(L]

MR-12852

Default Configuration of Push-On Connectors

886

MXV11-B/M7195
interface Connector Pins

Two 10-pin connectors, one for each serial line, are provided on the MXV11-B
module. The connector pins and signal functions are described below.

MXV11-B I/O Connector Pin Functions
Pin

Signal

BRCLK

Function

Baud rate clock. This output provides a clock signal at a frequency of 16 times the selected baud
rate.

This

MXV11-B

used

and does

output from

inputs.

Ground

XMIT+

Ground

Key, pin not provided

RCV—

Receiver input most negative

RCV+

Receiver input most positive

Ground

+12 'V

Transmitter output

Power for the DLV11-KA option

Jumpers are used to configure:

Console mode

Reboot

MXV11-B2 boot ROM set

Line time clock

System size

EVENT line

Boot and diagnostic ROMs Software programmed baud rates
Clock

Battery

Halt

User-supplied ROMs

887

the

not accept external clock

MXV11-B/M7195
Baud Rates

Each serial line can be software programmed or strapped to 300, 1200, 9600, or
38.400 baud and is compatible with EIA RS-423 or RS-232 signal levels.

When bit 06 is set, the BEVENT line clamp is removed and LTC is functional. The
LTC address is 777546.

CAUTION

There should be only one source drive on the BEVENT line in any
system. On most systems, the system power supply provides the
bevent signal. this source must be disabled if the mxvii-b is used to
drive the line clock.

This register is a write-only register, but generates a reply on DATIO and DATIO B
lines. The DDR resides in location 777524 on the 1/O page and is enabled when
the MXV11-B has its boot and console functions enabled.
Serial Line Unit Baud Rates
SLUO (See Note)

JOB to
GND

JOA to
GND

(J11 to J9)

Baud Rates

R
R
B

R
|
R

300"
1200
9600

(J10 to J9)

Ji1
J10
J9

JOB
JOB
GND

38.4K

SLU1 (See Note)

J1A to

GND

J9
J8
J7

GND
J1A
J1B

J1B to

GND

(J8 to J9)

J7 to J9)

Baud Rates

R
R
|

R
|
R

9600*
38.4K
300

1200

R = jumper removed

| = jumper inserted to ground
*Shipped configuration
NOTE

SOFT EN to GND jumper (J14 to J13) must be removed; otherwise
these jumpers have no effect. If the SOFT EN to GND jumper (J14 to
J13) is installed and PBRE bit 1 is set, baud rates are software
controlied.

888

MXV11-B/M7195
LED Diagnostic Display Register

The MXV11 has a diagnostic display register (DDR) which has four red LEDs to
show system diagnostics and one green LED to indicate power-on.

[
MXV118B
MODULE

LEDs
J1

S
v van iy N
GREEN LED

(POWER ON)

DIAGNGOSTIC DISPLAY REGISTER
MR-12855

MXV11-B Diagnostic Register (LEDs)

l UNUSED

WINDOW #1

L UNUSED

WINDOW #0

]

MR-12851

Page Control Register

ROM Window Addresses for 16-, 18-, and 22-bit Q-Bus

Window 1

Window 0

Start Addr

End Addr

Start Addr

End Addr

Q-Bus

(octal)

16-bit

165000

165777

173000

173377

18-bit

765000

765777

773000

773377

22-bit

17765000

17765777

17773000

17773377

889

MXV11-B/M7195
ROM Window Map
Normalized

Window 0 ROM
Address
Field

0
1
2
3
4
5
6

00000
01000
02000
03000
04000

10
11
12
13

10000
11000
12000
13000

14000

15
16

15000
16000

05000
06000

07000

17000

20
21
22

20000

23
24

23000

25000

26000

Maximum address for 4K by 8 PROM

21000
22000
24000

27000

30000

31000

32000

33000

34
35
36

34000
35000

Maximum address for 2K by 8 PROM

36000

37000

Maximum address for 8K by 8 PROM

890

MXV11-B/M7195

12
RCSR

UNUSED

RECEIVER

ACTIVE

DONE
INTERRUPT

ENABLE

RBUF

UNUSED

ERROR

DATA

FRAMING | RECEIVER
BREAK

ERROR

OVERRUN

UNUSED

ERROR

UNUSED

XCSR

TRANSMITTER|
READY

PROG.

RATE 2

RATE 0

PROG

BAUD

RATE
ENABLE

INTERRUPT

PROG.

ENABLE

BAUD

MAINTENANCE

BREAK

1
RATE

XBUF

DDR

WINDOW #0

UNUSED

DATA

WINDOW #1

UNUSED

PCR

LTC

UNUSED

LEDs (4)

UNUSED

ENABLE

CLOCK
MR-12854

MXV11-B Register Bit Formats

891

MXV11-B/M7195

Receiver Status Register Bit Assignments (RCSR)
Bit

Description

15-12

Unused

Receiver active
read only

A logic one indicates that the receiver is active.
Set at the center of the start bit of the input serial

data. Cleared at the expected center of the stop
bit at the end of the time prior to the leading
edge of RCV DONE. Also cleared by power up
sequence.

Unused

10-8
RD

A logic one indicates that the serial interface has
received a character. If enabled by bit 6, receiver
done requests an interrupt. Receiver done is
cleared by reading the receiver data register or
by power-up sequence.

Interrupt enable
read/write

5-0

A logic one enables receiver interrupts; a zero

disables interrupts. Cleared by initialization.
Unused

892

Receiver Data Buffer Bit Assignments (RBUF)

Bit

Description

A logic one indicates that bit 13 and/or bit 14 is a

Error

one. Cleared when the bit is read or cleared by

read only

power-up sequence.

A logic one indicates a word in the receiver buff-

Overrun error

er had not been read when another word was

read only

received and

placed in the receiver buffer.

Cleared when read or by power-up sequence.

A logic one indicates that a start bit was

Framing error

detected, but there was no corresponding stop

read only

bit. A framing error is generated when a break is
received. Cleared when read or by power-up
sequence.

Unused

This bit is set when serial-in (SI) signal goes

Receiver break
read only

from a mark to a space and stays in the space
condition for 11 bit times after serial reception
starts. This bit is cleared when the Sl signal
returns to the mark condition, or by power-up
sequence.

10-8

7-0

Unused

DATA
read only

These eight bits hold the most recent byte
received. When a new byte is transferred to the
data buffer, the RCV DONE in the RCSR is set.
Bit 0 is the LSB and bit 7 is the MSB. Cleared by
power-up sequence.

893

MXV11-B/M7195
Transmitter Status Register Bit Assignments (XCSR)
Bit

Description

15-8

Unused
TR

Transmitter read
read only

A logic one indicates the serial interface is ready
to accept a character into the transmitter data
register. If enabled by bit 6, transmitter ready
requests an interrupt. Transmitter ready is
cleared when data is written into the transmitter
data register. It is set by power-up sequence.

Interrupt enable
read/write

5-3

BR2-BRO*

Programmable baud
rate select
read/write

A logic one enables transmitter interrupts. A logic zero disables interrupts. Cleared by
initialization.

When PBR-bit 1 in XCSR is set, these baud bits
determine the baud rate (set by software if SOFT
jumper connected to GND). If SOFT jumper is
connected to OPEN, baud rate is obtained via
wire-wrap. Bits BR2-BRO are cleared by PBR
inhibit (SOFT EN) or by power-up sequence.

MAINT
Maintenance

read/write

This bit facilitates a maintenance self-test. When
the bit is set, the the transmitter serial output is
connected to the receiver serial input and the
external serial input is disconnected. This bit is
cleared by initialization.

* Read only as a zero when programmable baud rate inhibit (PBRI) is asserted
low. PBRI is asserted low by connecting the SOFT EN to OPEN jumpers (J14 to
J15). In this case, the baud rate is determined by the wire-wrap jumpers
(J7-J11). Otherwise, with SOFT EN to GND (J14-J13), the bit is read/write. This
bit is cleared by power-up sequence or PBRI (SOFT EN to OPEN jumper -

J14-J15).

894

MXV11-B/M7195
Transmitter Status Register Bit Assigments (XCSR) (Cont)

Bit

Description

PBR*

This bit selects between internal and external

Programmable baud

baud rate selection. When set (enable), the baud

rate enable

rate is determined by the PBR2-0 bits in this

Read/write when

software

determined by the J1, JO wire-wrap pins. This bit

programmable baud

is cleared by power-up sequence or SOFT to

rates enabled

OPEN jumper connected (programmable baud

(SOFT to GND

rate inhibit (J14 to J15).

jumper); else read

only as 0.

When this bit is set, it causes the serial output

Break

signal to go to a space condition. A space condi-

read/write

tion longer than a character time causes a framing error when it is received and is regarded as a

break. Cleared by bus initialization.

Read only as a zero when programmable baud rate inhibit (PBRI) is asserted
low. PBRI is asserted low by connecting the SOFT EN to OPEN jumpers (J14 to

J15). In this case, the baud rate is determined by the wire-wrap jumpers

(J7-J11). Otherwise, with SOFT EN to GND (J14-J13), the bit is read/write. This
bit is cleared by power-up sequence or PBRI (SOFT EN to OPEN jumper J14-J15).

895

MXV11-B/M7195
Transmitter Data Buffer Bit Assignments (XBUF)

Bit

Description

15-8

Unused

7-0

XMIT DATA
BUFFER
read/write

Transmitter data buffer — this byte register holds
a copy of the most recent byte written into it.
When a byte is written into this register, the

transmit ready (TR) bit in the XCSR register is
cleared. This byte is copied into the transmitter
serial output register whenever that register is
empty and the bit is clear. The TR bit is set when
a byte is copied from the transmitter data buffer
into the serial output register. Reading the contents of this register causes no other effect.
Cleared by power-up sequence.

896

MXV11-B/M7195

Definition of Cables

Cable

BC21B-05

Application

Length

EIA RS-232C modem cable to

1.5 m (5 ft)

interface with modems and
acoustic couplers (2 X 5 pin
AMP female to RS-232C male)

BC20N-05

EIA RS-232C null modem cable

1.5 m (5 ft)

to directly interface with a
local EIA RS-232C terminal

(2 X 5 pin AMP female to
RS-232C female)

BC20M-50

EIA RS-422 or RS-423 cable for

15 m (50 ft)

high-speed transmission
(19,200 baud) (2 X 5 pin AMP

female to 2 X 5 AMP female)

BCO05D-10

BC05D-25

BCO3M-25

Extension cable used in

3m (10 ft)

Extension cable used in

7.6 m (25 ft)

Null modem extension cable

7.6 m (25 ft)

conjunction with BC21B-05

used in conjunction with
BC21B-05

NOTE

Strapped logic levels are provided on data terminal ready (DTR) and
request to send (RTS) to all operation of modems with manual provisions (such as Bell 103A data set with 804B auxiliary set).

897

MXV11-B/M7195

LTC
FREQUENCY

SOFTWARE
CTRLLTC

—

322 423 124 425 426 J27 J28

PROM SIZE AND
TYPE DIR MODE
ENABLE/DISABLE
DIR MODE ADDR.

360

SLUO AND SLU1
BAUD RATES

59 |
RAM

J58 |

STARTING

j57 _|

ADDRESSES 55 |

55 !
54 -

HALT/REBOOT

J53

SOFTWARE
PROGRAMMABLE

PROM START ADDR <J52

BAUD RATES

148

MaSTER cLOCK {45
BOOT ROM
OR

(446

Jas

USER ROM \ J44

XE28

—

{—fl

LO BYTE

PROM

SOCKETS
XE19

)

HI BYTE

(I
)

CONSOLE Y63
mMmope

162

J61

s
e [ L ®

no oy

/
©
J43//1?§“
®
:
Jaz2

SLU VECTOR Ja1 -~~~
ADDRESSES J40 -1 -7

J398
J38

/LJ

]

J30 J31 J32 J33

J34 435 J36 437
DIR MODE BOOT

SLU STARTING

AND SMALL OR

ADDRESS

SLUA1

LG SYSTEM

*ENGINEERING TEST POINTS

MR-12853

MXV11-B Jumper Locations

898

MXV11-B/M7195
Jumper Connections for MXV11-B Summary
Jumper Name
J1

Connector for SLUO
Connector for SLU1

HALT

GND

RBOOT

OPEN

J1B

J1A

GND

Function

SLU connectors

Halt and reboot functions

POC (W3)

Serial line unit baud rates

J10

JOB

J11

JOA

J12

TP2

J13

GND

J14

SOFT EN

Software programmable

J15

OPEN

baud rates

J16

GND

For engineering use

J17

PG L/DIR H

Enables or disables direct

J18

OPEN

mode addressing

J19

AL12H

J20

NA12H

PROM size and type in

J21

+5V

direct mode addressing

J22

LTC COMM

J23

50 Hz

J24

60 Hz

J25

800 Hz

J26

OPEN

J27
J28

J29

Connection*

POC (W4)

POC (W5)

POC (W6)

Line time clock frequency

LTC EN IN

Software control of line

POC (W7)

LTC EN OUT

time clock

TP3

For engineering use

J30

SLUA3

J31

GND

Serial line unit starting

J32

SLUAZ2

address

J33

SLUA1

899

MXV11-B/M7195
Jumper Connections for MXV11-B Summary (Cont)

Jumper Name
DIR MODE BOOT

J34

J35

OPEN

J37

SM/LG

J38

JUT

J39

JU2

Ja1

JL1

J42

JL2

J43

JL3

GND

J36

GND

J40

BOOT L/PROM H

Ja4

J45

GND

J46

OPEN

Ja7

CLOCK IN

J49

PROM 1

CLOCK OUT

J48

PROM 2

J50

J51

GND

J52

BSK1

J53

BSK2

J54

AJ13

J55

AJ14

J56

AJ15

J57

GND

J58

AJ16

J59

AJ17

J60

AJ18

J61

OPEN

J62

GND

J63

CONSOLE

Function

ConnectionTM

Direct mode boot and

Serial line unit vector

Boot ROM or user ROM

POC (W9)

Master clock

POC (W10)

PROM size and PROM

small or large system

address

start address

RAM starting address

WWwW

Console mode

POC (W8)

*POC = Push-on connector
WW = Wire-wrap

NOTE
W1

and W2 are 0 ohm resistors associated with battery backup

option. Either one may be inserted but not both. The module is

shipped with W2 inserted.

900

MXV11-B/M7195
Miscellaneous Jumper Configurations

Connector

Connection

Description

J63
J62

GND to OPEN
(J62 to J61)

Enables console mode. SLU is
fixed at address 77560 and vector address at 60. Select SLU 0

J61

CONSOLE
GND

OPEN

address from Table B and vector
from Table C.

J63
J62
J61

J46

J45

Jd4

CONSOLE
GND

CONSOLE to GND
(J63 to J62)

OPEN

GND

BOOT L/PROM H

Disables console mode. For SLU
addresses, refer to Table B and
vectors from
Table C.

BOOT L/PROM H

to GND

Inserted when MXV11-B2 boot

ROM set is installed in sockets

XE19 and XE29. Enables the fol-

(J44 to J45)

lowing registers to be addressed

if the console GND to OPEN

jumper (J62 to J61) is installed:
Page control register

Line time clock control
Diagnostic display register.

J46
J45
J44

OPEN
GND
BOOT L/PROM H

J37

SM/LG SYS

J36

GND

J35

OPEN

GND to OPEN
(J45 to J46)

Inserted when ROMs are for user
code (not bootstrap code). See

Table A for addresses.

SM/LG SYS to

This

(J37 to J36)

bus backplane. Recognizes

GND

installed

when

the

MXV11-B is connected in a Q22

BDAL <21:00> L. This jumper

must

installed

RAM

addressed above 128K words.

J37
J36

J35

SM/LG SYS
GND
OPEN

GND to OPEN
(J36 to J35)

installed when the MXV11-B is
connected to a 16- or 18-bit QBUS. Recognizes BDAL <17:00>
L only.

J36
J35
J34

GND
OPEN
DIRECT MODE

DIR MODE BOOT
to OPEN
(J34 to J35)

BOOT

901

Module not wired for direct mode
boot.

MXV11-B/M7195
Miscellaneous Jumper Configurations (Cont)
Connector

J36
J35

J34

GND
OPEN

DIRECT MODE

Description

Connection

DIR MODE BOOT
to GND

(J34 to J36)

directly addressed.

BOOT

J18
J17

OPEN
PG L/DIR H

Ji16

GND

J18

J17

OPEN
PG L/DIRH

J16

GND

J48

CLOCK OUT

J47

CLOCK IN

PG L/DIR H to
GND

(J17 to J16)

Enables PROM sockets XE19

PG L/DIR H

and XE28 to be used for user
defined PROMs. In this case,
these sockets can only be
addressed in memory locations
below the 16K word boundary.

to OPEN
(J17 to J18)

CLOCK OUT to
K
CLOCIN
(J48 to J47)

HALT

HALT to GND

GND

(J3 to J4)

RBOOT

OPEN

HALT

HALT not con-

GND

nected to GND

RBOOT

OPEN

Factory test. Do not remove. This
is the master clock, and provides
on-board refresh and the charge
pump to generate —12 V.

Enables SLU 1 (console port) to
halt the processor upon receiving
a break character.

J3
J5

Enables ROM boot map option
and page mode on the MXV11-B.
Disables user PROM addresses
below 16K.

Module enabled for direct mode
boot. This jumper must be
installed when the user boot is

Disables CPU halt function.

RBOOT

Causes a system reboot when a
break condition is received from
SLU 1. Forces BDC OK-H low on

OPEN

the bus.

HALT

GND

RBOOT to GND

NOTE
H_ALT to GND (J3 to J4) and RBOOT to GND (J5 to J4) cannot be

simultaneously jumpered.

902

MXV11-B/M7195
Miscellaneous Jumper Configurations (Cont)

Connector

Connection

Description

Disables reboot function.

HALT

GND to OPEN

GND

(J4 to J3)

RBOOT

OPEN

J26

OPEN

J27
J28

LTC EN IN
LTC EN OUT

LTC EN IN to

LTC EN OUT
(J27 to J28)

Allows LTC to be software con-

trolled. Enables control of
BEVENT L on the bus via bit 06

of the LTC register. When bit 6 of
LTC register is 0, BEVENT L will
be asserted constantly low. This
inhibits LTC interrupts. To
address the LTC register
(777546), the MXV11-B must be
in boot mode (BOOT L/PROM H

to GND) (J44 to J45) and SLU1
must be the console port (CONSOLE to GRD removed).

J26
J27

OPEN
LTCENIN

LTC EN IN
to OPEN

Prevents bits 06 of the LTC register from controlling the BEVENT

J22
J23

LTC COMM
50 Hz

LTC COMM to
50 Hz

When installed, the BEVENT line
is driven from a 50 Hz crystal

J28

LTC EN OUT

L line.

(J27 to J26)

(J22 to J23)

derived clock. If the line time

clock jumper is installed, the
clamp has to be turned off by the

software for the clock to drive the
BEVENT line.

J24

60 Hz

LTC COMM to

When installed, the BEVENT line

(J22 to J24)

derived clock. If the line time
clock jumper is installed, the
clamp has to be turned off by the
software for the clock to drive the

60 Hz

is driven from a 60 Hz crystal

BEVENT line.

CAUTION

LTC EN IN to LTC EN OUT (J27 to J28) should not be connected if the

CPU has an LTC control register.

903

MXV11-B/M7195
Miscellaneous Jumper Configurations (Cont)

Connector

J25

800 Hz

Connection

Description

LTC COMM to

When installed, the BEVENT line

800 Hz
(J22 to J25)

is driven from an 800 Hz crystal
derived clock. If the line time

clock jumper is installed, the
clamp has to be turned off by the
software for the clock to drive the
BEVENT line.

J15
J14
J13

OPEN
SOFT EN
GND

SOFT EN to GND
to J13)
(J14

Enables software programmable
baud rates for both SLU1 and
SLUO via the CSR. The baud rate

jumpers in Table B have no effect
if the PBRE bit is set.

J15

OPEN

J13

GND

Ji4

SOFT EN

SOFT EN to OPEN Baud rates are selected from
Table B.

(J14 to J15)

(0 ohm resistor)
connected

Battery backup. +5 V is supplied

by user on backplane pin AV1.

DIGITAL does not supply battery

backup.

No battery backup.

(0 ohm resistor)
connected

J21
J20
J19

+5V
NA12H
BA12H

NA12H to +5 V
(Normalized
address 12)

Specifies 2K user UVROMs
(2716) instailed and direct mode
addressing

(J20 to J21) to
(Buffered Address

line 12)

J21
J20

+5V
NA12H

J19

BA12H

NA12H to BA12H
(J20 to J19)

Specifies 4K or 8K user-supplied
ROM in direct mode addressing.

NOTE

One of these jumpers (50, 60, or 800 Hz) should be installed: 1) If no
external BEVENT source is provided in the system, and 2) If the user
desires this source. Power supplies manufactured by DIGITAL normally supply BEVENT L to the backplane.
904

MXV11-B/M7195
NOTE

There are cases where none of these jumpers (+5 V, NA4H, and
AL12H) should be connected. In these cases, the push-on connector
must be completely removed or must be connected to one of the
outside pins to hold the connector. There is no open pin associated

with these jumpers. For example, if 2K non-UVY PROMs or the MXV11-

B2 ROM is to be installed, these jumpers are all disconnected.

Table A.

Jumpers for PROM Starting Address

BSK2 to

BSK1 to

User PROM

GND

Starting Address (octal)

(J53 to J51)

(J52 to J51)

(Note)

J51

GND

000000*

J52

BSK1

020000
040000

J63

BSK2

060000

R = jumper removed
| = jumper inserted to ground

Shipped configuration. Remove all jumpers from BSK1 (J52) and BSK2 (J53) if
not in user mode.

NOTE
These addresses are for user supplied ROMs only. Jumpers BOOT
L/PROM H to GND (J44 to J45) and PG L/DIR H to GND (J17 to J16)
must be removed.

905

MXV11-B/M7195
Table B.
SLUA3

J33
J32
J31
J30

SLUA1
SLUAZ
GND
SLUA3

Serial Line Unit Starting Address Jumpers
SLU1

SLUAZ

to GND
(J30to
J31)

toGND
(J32to
J31)

to GND
(J33to
J31)

Starting
Address
SLUO

SLU1
(See
Note)

R
R
R
R

R
R
I
|

R
|
R
|

776500"
776510
776520
776530

776510"
776520
776530
776540

I
|
|
fl

R
|
R
|

R
R
I
i

776540
776550
776560
776570

776550
776560
776570
776600

R = jumper removed

| = jumper inserted to ground

*Shipped configuration

NOTE

if the GND to OPEN jumper (J62 to J61) is installed (console enabled),
the SLU1 address is fixed at the standard console address of 777560
and this column does not apply.

906

MXV11-B/M7195
Table C.

Jumpers for SLU Vector Addresses

JU2

JU1

JL3

JL2

JL1

to GND

SLU1

(J39to

(J38io

(J43to

(J42to

(J41 to

(See

J40)

SLUO

Note)

310~
020

J43

JL3

300*

J42

JL2

010

J41

JL1

020

030

J40

GND

030

040

J39

JU2

040

050

J38

JU1

050

060
070

060

070

100

110

120

130

140

150

160

170

200

210

220

230

240

250

260

270
300

270

300

310

320

330

340
350

340

350

360

370

Undefined

= jumper inserted from specified pin to ground. Where multiple connections are
made, they are daisy-chained.

R = jumper removed

*Shipped configuration
NOTE

if the GND to OPEN jumper (J62 to J61) is installed (console enabled),
SLU1 vector address is fixed at 60 and this column does not apply.

907

MXV11-B/M7195
PROM Jumpers

NA12H to

to+5V

R
|

R
R

(J20 to J19)
J19
J20

J2t

BA12H
NA12H

45V

NA12H

BA12H

(J20 to J21)

Description

Page mode - Boot ROM

for 2K by 8 non-UV
PROMSs, 4K by 8 or 8K by
8 PROMs

Direct mode - for 2K by 8,
non-UV PROMs, 4k by 8,

or 8K by 8 PROMs”
Direct mode - for 2K by 8
UV PROMs

R = jumper removed
| = jumper inserted
*Shipped configuration

Jumpers to Configure PROM Size

J51
J50
J49

GND
PROM 2
PROM 1

PROM 2
to GND

PROM 1
to GND

(J50 to J51)

(J49 to J51)

PROM Size

R
R
|

R
i
R

No ROMs”TM
2K by 8
4K by 8

8K by 8t

R = jumper removed
| = jumper inserted

* Shipped configuration. Additional jumpers are required depending on user
mode/boot mode and direct addressing page addressing. Refer to the last three
tables in this section.

+ If the MXV11-B2 Boot Diagnostic ROM set is installed, install PROM 2 to PROM
1 to GND jumper (J50 to J49 to J51).

908

MXV11-B/M7195
RAM Starting Address Jumpers
AJ18

AJ17

AJ16

AJ15

AJ14

AJ13

RAM

to GND to GND to GND to GND to GND to GND Starting
(J60 to

(J59 to

(J58 to

(J56 to

(J55 to

(J54 to

Address

J57)

(Words)

J60

AJI8

J59

AJ17

J58

AJI16

J57

GND

12K

J56

AJ15

16K

J55

AJ14

20K

J54

AJ13

06
07
10

R
R
R

R
R
a

H
|
R

a
e
R

R
a
R

24K
28K
32K

36K

40K

13
14

R
R

a
1

R
B

a
R

s
R

44K
48K

15
16
17
20
21
22
23
24
25
26
27

R
R
R
R
R
R
R
R
R
R
R

R
R
R
|
!
|
e
|
a
s
u

s
n
u
R
R
R
R
R
R
R
R

a
e
n
R
R
R
R

R
s
a
R
R
|
u

a
R
s
R
a
R
n

52K
56K
60K
64K
68K+
72K+
76K+

n
|
s
a

R
R
a
a

R
a
R
a

80K+
84K+
88K+
92K+

30
31
32
33
34

R
R
R
R
R

a
I
a
a
i
s
s
|

:
s
a
u
|

R
R
R
R
e

35
36
37
40
41
42
43
44
45
46
47

R
R
R
|
1
|
|
|
|
|
|

R
R
R
R
R
R
R

a
s
|
R
R
R
R
R
R
R

909

i
s
|
R
R
R
R
a
a
a
|

R
R
u
u
R

R
a
l
R
R
u
a
R
R
a
|

R
I
R
a
R
a
R
|

R
a
R
u
R
e
R
|

96K+
100K+
104K+
108K+
112K+

116K+
120K+
124K+
128K+
132K+
136K+
140K+
144K+
148K+
152K+
156K+t

MXV11-B/M7195
RAM Starting Address Jumpers (Cont)
RAM

AJ18

AJ17

AJ16

Adi5

AJi14

AJ13

50
51
52
53
54
55

|
|
|
|
|
|

R
R
R
R
R
R

i
s
a
a
|
I

R
R
R
R
a
a

R
R
u
1
R
R

R
|
R
a
R
l

160Kt
164Kt
168K+
172Kt
176Kt
180K+t

64
65
66
67
70
71
72
73

|
|
|
|
|

s
s
a
a
u
n
fi
i

R
R
R
R
a
|
I
I

a
a
a
i
R
R
R
R

R
R
a
i
R
R
i
l

R
u
R
a
R
n

208Kt
212K+
216K+
220K+
224K+
228K+

to GND to GND to GND to GND to GND to GND Starting
(J60 to (J59 to (J58 to (J56 to (J55 to (J54 to Address
(Words)
J57)
J57)
J57)
J57)
J57)
J57)

56
57
60
61
62
63

74
75
76
77

|
|
|
|
|
|

R
R
a
i
s
l

i
s
|
n

|
s
R
R
R
R

n
n
u
|

a
u
R
R
R
R

a
s
i

l
a
R
R
a
a

R
R
a
a

R
e
R
i
R
a

R
i
R
l
R
|

184K+
188Kt
192K+
196K+
200Kt
204K+

232K+
236K+
240K+t
244K+
248K+t

252K+

jumper inserted from designated pin to GND. Where multiple connections are made, they are daisy-chained.

jumper removed.

* Shipped configuration

+ To use address above 64K words, SM/LG SYS TO GND jumper (J37 to J36)
must be installed

910

MXV11-B/M7195
NOTE
Be careful when configuring the MXV11-B RAM when ROM is used in

the USER ROM address space. USER ROM address space is defined
as bus addresses 0-16K, (00000-100000) on 4K boundaries. The RAM
start address must be higher than the last location of the ROM or dual

responses from both the RAM and ROM will occur. The chart below
shows several examples of right and wrong ways of assigning RAM
memory start addresses.

ROM

RAM

Size

Start

End

Comments

68K

Wrong, 4K overlap (4K—8K)

64K

Wrong, 8K overlap (4K—12K)

68K

Right, no overlap

12K

76K

Right, no overlapt

12K

76K

Right

1 Address space gap usually not recommended but up to user to decide

depending on application.

Jumper Connections for PROM Sizes in User Mode

Jumpers

No PROMs

2K by &

4K by 8

8K by 8

J17 to J18

J17to J18

J17 to J18

J19to J20

J20toJ21

J19toJ20

J19 to J20

J45to J46

J45 to J46

J49 to J51

J50 to J51

J49 to J50
to J51

J16

(GND)

J17

(PG L/DIR H)

J18

(OPEN)

J19

(BA12H)

J20

(NA12H)

J21

(+5V)

J44

(BOOT L/PROM H) J45 to J46

J45

(GND)

J46

(OPEN)

J49
J50

(PROM1)
(PROMZ2)

J51

(GND)

NOTE

Jumper connections are indicated. For example, in the 2K by 8 PROM,
J17 is connected to J18, J20 is connected to J21, J45 is connected to

J46, and J49 is connected to J51.

911

Jumper Connections for PROM Sizes in Boot Mode (Page Addressing)

Jumpers

No PROMs

2K by 8*

4K by 8

8K by 8

J16 (GND)

J17 to J18

J16t0 J17

J16to J17

J19 (BA12H)

J19 to J20

J44 t0 J45

J44 10 J45

J49 to J51

J50 to J51

J49 to J50
to J51

J17
J18

J20
J21

(PG L/DIR H)
(OPEN)

(NA12H)
(+5 V)

J44 (BOOT L/PROM H) J45 t0 J46
J45

(GND)

J46

(OPEN)

J49 (PROM1)
J50 (PROM2)
J51

(GND)

*2K by 8 UV PROM cannot be used in page mode.
NOTE

Jumper connections are indicated. For example, in the 8K by 8 PROM,
J16 is connected to J17, J19 is connected to J20, J44 is connected to
J45 and J49, J50 and J51 are connected.

912

MXV11-B/M7195
‘Jumper Connections for PROM Sizes in Boot Mode (Direct Addressing)
No PROMs

2K by
8

4K by 8

8K by
8

J17
to J18

J17 to J18

J19
to J20

J20 to J21

J19 to J20

J44

(BOOT L/PROM
H) J45 to J46

J44 to J45

J45

(GND)

J46

(OPEN)

J49 to J51

J50 to J51

Jumpers
J16

(GND)

J17

H)
(PG L/DIR

J18

(OPEN)

J19

(BA12H)

J20

(NA12H)

J21

(+5 V)

J49

(PROM1)

J50

(PROM2)

J51

(GND)

J34

(DIR

J35

(OPEN)

J36

(GND)

MODE BOOT)

J49 to J50
to J51

J34 to J36

NOTE

J34 to J36

Jumper connections are indicated. For example, in the 2K by 8 PROM,
J17 is connected to J18, J20 is connected to J21, J44 is connected to
J45, J49 is connected to J51, and J34 is connected to J36.

913

RKV11-D/M7269

RKV11-D BUS INTERFACE

FOR RKV11-D DISK DRIVE CONTROLLER
Bus Loads

Amps
+5

{.8max.

+12

1.93 1

Cables

(2) BCO5L + M993-YA

Standard Address

RKDS
RKER
RKCS
RKWC
RKBA
RKDA
RKDB

(Drive Status)
(Error)
(Control/Status)
(Word Count)
(Bus Address)
(Disk Address)
(Data Buffer)

177400
177402
177404
177406
177410
177412
177416

Vector
220

Diagnostic Programs

Refer to Appendix A.
NOTE

The logic test programs should be run first, then the dynamic

test, and finally the performance exerciser.
Related Documentation

RKV11-D Disk Drive Controller User’s Manual (EK-RKV11-OP-001)
RKV11-Disk Drive Controller Technical Manual (EK-RKV11-TM-001)
Field Maintenance Print Set (MP00223)

RKO05/RK05J/RKO5F Disk Drive Maintenance Manual (EK-RK5JF-MM-001)
RK05/RK05J Disk Drive Preventive Maintenance Manual
(EK-KK0O5J-PM- 001)

RKOS5F DEC Disk Drive Preventive Maintenance Procedure
(ED-RKO5F-PM- 001)

Microcomputer Interfaces Handbook (EB-20175-20)

914

RKV11-D/M7269

JUMPER SETTINGS

W17
— W1, W2, W3, W6, W7, W11,
INSTALLED
REMOVED — W4, W5, W8, W9, W10, W12, W13, W14, W15

W16

INTERRUPT
VECTOR

JUMPERS

0000

\OOOOO 00

8
P90 0401 ene
RESI0

BUS

~ |
ADDRESS

JUMPERS

NOTE:
NORMALLY INSTALLED
JUMPERS ARE SHOWN AS
SOLID LINES.

MR 6114

M7269 Jumpers

915

CONFIGURED

Wiz

wi3z

Wi4

FACTORY-

e + JOU

)

JUMPER ON

M7269 MODULE

ADDRESS (177400}

U—

RKV11-D/M7269

| = INSTALLED .
R = REMOVED

DEVICE ADDRESS
MR-0803

&“;::zggum

]

W10 W11 W15

W16

W17

I = INSTALLED

R = REMOVED

FACTORY-

CONFIGURED

————

ADDRESS (220}

VECTOR ADDRESS
MR-0804

Jumper settings on the three RKV11-D modules are identical to those in
the standard RK11-D configuration. A breakdown is given below for reference. There are no jumpers on M7268.

Module

Installed

Removed

M7254*
M7255* "
M7256

W1, W4, W6, W7
Wi, W2, W6
W2, W5, W7

W2, W3, W5
W3, W4, W5
W1, W3, W4, W6, W8

Interrupt priority jumper (BR4-7) in socket E8 is not required
since the RKV11-D was designed for single-line interrupt
scheme only.

288 MHz crystal used DEC PN 18-10694-3.

916

RKV11-D/M7269

M7254

917

RKV11-D/M7269

W 3
W2

WhH

&Bws

M7255

918

RKV11-D/M7269

M7256

919

RKV11-D/M7269

M7254

M7255
M7256

M7268

STATUS

conTROL

DISK
CONTROL

H780 POWER
SUPPLY

DATA

PATHS

BUS

ADAPTER
MR-0762

RKV11-D Module Utilization

Drive Status Register (RKDS)
Address = 177400
NOTE

This register is a read-only register, and contains the selected
drive status and current sector address.

DRIVE IDENT

DPL | AKO5 | DRU | SIN | SOK | DRY

R/W/S

RDY

WPS

{

24,01

SECTOR COUNTER

SC=

400
CP-3137

Bit Definitions
Bit

00-03

Function

Sector Counter (SC) - These four bits are the current sector ad-

dress of the selected drive. Sector address 00 is defined as the
sector following the sector that contains the index pulse.

Sector Counter Equals Sector Address (SC = SA) - Indicates

that the disk heads are positioned over the disk address currently held in the sector address register.

Write-Protect Status (WPS) - Sets when the selected disk is in
the write-protected mode.

Read/Write/Seek Ready (R/W/S RDY) - Indicates that the selected drive head mechanism is not in motion, and that the drive
is ready to accept a new function.

Drive Ready (DRY) - Indicates that the selected disk drive complies with the following conditions.

920

RKV11-D/M7269
Bit Definitions (Cont)
Function

NOO AN =

Bit

The drive is properly supplied with power.
The drive is loaded with a disk cartridge.

The disk drive door is closed.
The LOAD/RUN switch is set to RUN.
The disk is rotating at a proper speed.

The heads are properly loaded.

The disk is not in a DRU (bit 10 or RKDS) condition.

Sector Counter OK (SOK) - Indicates that the sector counter
operating on the selected drive is not in the process of changing, and is ready for examination. If this bit is not set, the sector

counter is not ready for examination, and a second attempt
should be made.
09

Seek Incomplete (SIN) - Indicates that due to some unusual
condition, to seek function cannot be completed. Can be accompanied by RKER 15 (drive error). Cleared by a drive reset
function.

Drive Unsafe (DRU) - Indicates that an unusual condition has
occurred in the disk drive, and it is unable to properly perform
any operations. Reset by setting the RUN/LOAD switch to
LOAD. If, when the switch is returned to RUN, the condition recurs, an inoperative drive can be assumed, and corrective maintenance procedures should begin. Can be accompanied by
RKER 15 (drive error).

RKO5 Disk on Line (RK0O5) - Always set, to identify the selected
disk drive as RKO5.

Drive Power Low (DPL) - Sets when an attempt is made to initiate a new function, or if a function is actively in process when

the control senses a loss of power to one of the disk drives. Can
be accompanied by RKER 15 (drive error). Reset by a BUS INIT
or a control reset function.
13-15

Identification of Drive (ID) - If an interrupt occurs as the result of
a hardware poll operation, these bits will contain the binary representation of the logical drive number that caused the interrupt.

921

RKV11-D/M7269
Error Register (RKER)
Address

177402

NOTE

This is a read-only register.
14

OVR | WLO | SKE

PGE | NXM | DLT

NXD

NXC | NXS

{

UNUSED
|

[]

CSE | WCE

|
cP-3138

Bit Definitions
Bit

Function

Write Check Error (WCE) - Indicates that an error was encoun-

tered during a write check function as a result of a faulty bit

comparison between disk data and memory data. Clears upon

the initiation of a new function. This is a soft error condition.
01

Checksum Error (CSE) - Sets while performing a read function
as a result of a faulty recalculation of the checksum. Cleared
upon the initiation of any new function. This is a soft error condition.

02-04

Unused.

The remaining bits of the RKER are all hard errors, and are cleared only by
a BUS INIT or a control reset function.

Bit Definitions

Bit

Function

Nonexistent Sector (NXS) - Indicates that an attempt was

Nonexistent Cylinder (NXC) - Indicates that an attempt was
made to initiate a transfer to a cylinder address greater than

made to a sector address greater than 13g.

312g.

07
08

Nonexistent Disk (NXD) - Indicates that an attempt was made

to initiate a function on a nonexistent drive.

Timing Error (TE) - Indicates that a loss of timing pulses for at
least 5 us has been detected.

922

RKV11-D/M7269
Bit Definitions (Cont)
Bit

Function

Data Late (DLT) - Sets during a write or write check function
when the multibuffer file is empty and the operation is not yet

complete. Sets during a read function when the multibuffer file is
filed and the operation is not yet complete.
10

Nonexistent Memory (NXM) - Sets if memory does not respond
with a RPLY within 20 us of the time when the RKV11-D becomes bus. master during a DMA sequence. Because of the
speed of the RKO5 disk drive, it is possible that NXM will be ac-

companied by RKER 09 (data late).
11

Programming Error (PGE) - Indicates that RKCS 10 (format)
was set while initiating a function other than read or write.
Seek Error (SKE) - Sets if the disk head mechanism is not properly positioned while executing a normal read, write, read
check, or write check function. The control checks 16 times before flagging this error. A simple jumper change will force the
control to check just once.

Write Lockout Violation (WLO) - Sets if an attempt is made to
write on a disk that is currently write protected.
14

Overrun (OVR) - Indicates that during a read, write, read check,
or write check function, operations on sector 13g, surface 1 of
cylinder address 312g were finished, and the RKWC has not yet
overflowed. This is essentially an attempt to overflow out of a
disk drive.

Drive Error (DRE) - Sets if a function is either initiated or in process, and

one of the drives in the system senses a loss of either ac or
dc power; or

the selected drive is not ready, or is in some error condition.

923

RKV11-D/M7269
Control Status Register (RKCS)
Address = 177404

ERR

scp

IBA FMT

SSE RDY

IDE

UNUSED

[4:]

[1)]

FUNCTION

)

cP.3139

UNUSED

00
GO

Bit Definitions

Bit

Function

Go - This bit can be loaded by the operator and causes the control to carry out the function contained in bits 01-03 of the

RKCS (functions). Remains set until the control actually begins
to respond to go, which may take from 1 us to 3.3 ms, depending on the current operation of the selected disk drive (to protect the format structure of the sector). Write only.

01-03

Function - The function register, or function bits, are loaded

with the binary representation of the function to be performed by
the control when a GO command is initiated. These bits are
loaded by the program and cleared by BUS INIT. Read/write.
The binary codings are as follows.
Bit3

Bit2

Bit1

Operation

Control Reset

0
0

O
1

1
O

Write
Read

1
1
1
1

0
0
1
1

0
1
)
1

Seek
Read Check
Drive Reset
Write Lock

04, 05

Write Check

Unused. The RK11-D uses these bits. Since the PDP-11/03 bus

structure has no provision for extended addressing, no connection is made to the bus from these bits on the RKV11-D.

They will respond as two unused read/write bits in the status
register; but, like the RK11-D they, will increment should the
RKBA overflow.
924

RKV11-D/M7269
Bit Definitions (Cont)
Function

Interrupt on Done Enable (IDE) - When set, causes the control

to issue a bus request and interrupt to vector address 220 if:
a.
b.

a function has completed activity
a hard error is encountered

a soft error is encountered and bit 08 of the RKCS (SSE) is
set

RKCS 07 (RDY) is set and go is not set.

Read/write.
07

Control Ready (RDY) - Indicates that the control is ready to
perform a function. Set by INIT, a hard error condition, or by the
termination of a function. Cleared by go being set. Read only.

Stop on Soft Error (SSE) - If a soft error is encountered when
this bit is set:

all control action will stop at the end of the current sector if

all control action will stop and a bus request will occur at
the end of the current sector if RKCS 06 (IDE) is set.

RKCS 06 (IDE) is reset, or

Read/write.
09
10

Unused.

Format (FMT) - FMT is under program control, and must be
used only in conjunction with normal read and write functions.
Used to format a new disk pack or to reformat any sector
erased due to control or drive failure. Alters the normal write operation, under which the header is rewritten each time the asso-

ciated sector is rewritten, in that the head position is not checked for proper positioning before the write. Alters the normal read
operation in that only one word, the header word, is transferred
to memory per sector. For example, a three-word read function
in format mode will transfer header words from three consecutive sectors to three consecutive memory locations for
software checking. Read/write.

Inhibit Incrementing the RKBA (IBA) - Inhibits the RKBA from incrementing during a normal transfer function. This allows data
transfers to occur to or from the same memory location throughout the entire transfer operation. Read/write.

Unused.

925

RKV11-D/M7269
Bit Definitions (Cont)

Function

Bit

Search Complete (SCP) - Indicates that the previous interrupt
was the result of some seek or drive reset function. Cleared at

the initiation of any new function. Read only.

Hard Error (HE) - Sets when any of RKER 05-15 are set. Stops
all control action, and processor reaction is dictated by RKCS

06 (IDE), until cleared, along with RKER 05-15, by INIT or a control reset function. Read only.

Error (ERR) - Sets when any bit of the RKER sets. Processor
reaction is dictated by RKCS 06 and RKCS 08 (IDE and SSE).

Cleared if all bits in the RKER are cleared. Read only.
Word Count Register (RKWC)
Address = 177406

Bit Definition

Function

Bit

WCO00-WC15 - The bits in this register contain the 2’s com-

00-15

plement of words to be affected or transferred by a given function. The register increments by 1 after each word transfer.
When the register overflows (all WC bits go to 0), the transfer is
complete and RKV11-D operation is terminated at the end of the
present disk sector. However, only the number of words speci-

fied in the RKWC are transferred. Read/write.

Current Bus Address Register (RKBA)
Address = 177410
I

{

BA15 =

I
BA0O
CP-3135

Bit Definition

Bit
00-15

| Function
BAOO-BA
15 - The bits in this register contain the bus address
to or from which data will be transferred. The register is incremented by two at the end of each transfer. Read/write.

926

RKV11-D/M7269
Disk Address Register (RKDA)
Address = 177412

1
|
DRIVE SELECT

CYLINDER ADDRESS

;054 4

1033023

SECTOR ADDRESS

SUR
3

0
CP-3136

NOTE

This register will not respond to commands while the controller
is busy. Therefore, RKDA bits are loaded from the bus data
lines only in the control ready (RDY - bit 07 of the RKCS) state,
and are cleared by BUS INIT and control reset. The RKDA is incremented automatically at the end of each disk sector.

Bit Definitions

Bit

Function

00-03

Sector Address (SA) - Binary representation of the disk sector
to be addressed for the next function. The largest valid address
(or number) for the sector address is 13g.

Surface (SUR) - When set, enables the lower disk head so that

operation is performed on the lower surface; when reset, enables the upper disk head.

05-12

Cylinder Address (CYL ADDR) - Binary representation of the
cylinder address currently being selected. The largest valid address or number for the cylinder address is 312 .

13-15

Drive Select (DR SEL) - Binary representation of the logical

drive number currently being selected.

927

RKV11-D/M7269
Data Buffer Register (RKDB)
Address = 177416

Bit Definition

Bit

Function

00-15

of this register work as a general data
DB00-DB15 - The bits

handler in that all information transferred between the control
and the disk drive must pass through this register. Loaded from
the bus only while the RKV11-D is bus master during a DMA sequence. Read only.

NOTE

Address 177414 is unused.

928

RKV11-D/M7269

TO M993-YA

TO M7269

(RKO5)

(LSI-11 BUS)

M7268

M983-YA

GROOVE
g SIDE DOWN

1
Top
L—J—I L__.}j
TOP |

L{ Ja I L—{ J3 |

M7268

M7269

~ |Top

[
42

BCOSL

GROOVE SIDE

5] I ]

BCOSL
ToP |

B
MR-0763

RKV11-D Cable Connection

929

RLV11/M8013,4

RLV11 CONTROLLER MODULES

Bus Loads

Amps

+5
6.5

+12
1.0

AC
3.2

DC
1

Transition Bracket Assembly
Terminator

Cables

BCO8R-XX
70-12122 (1 per drive)
70-12415-00
70-12293-00

Standard Addresses

CSR
BAR
DAR
MPR

174400
174402
174404
174406

Standard Vectors
160

Diagnostic Programs

Refer to Appendix A.

930

RLV11/M8013,4
1

N 7
12

[ 1 [ 1 l 1 l 1 l 1
ADDRESS SWITCH

SWITCH ON

SWITCH OFF

e Ye
09

~A
08

2 e

s
05

N
03

0 l 0

0 [ 0

1 l 0

0 ] 0 l 0

e
01

)
00

MR-2388

Address Selection

s
15

NOT USED
L

l 0 l 0

]

N
06

A
05

TM
Q03

A"—'—‘\
02

1 l 1 [ 1

] I 1]

VECTOR SWITCH

SWITCH POSITION

0 ] 0]
HARDWIRE

N =ON
F = OFF
MR-2289

Vector Selection

Related Documentation

RLV
11 Controller Technical Description Manual (EK-RLV11-TD)
RLV11 Field Maintenance Print Set (MP00635)
RLO1 Field Maintenance Print Set (MP00347)
RLO2 Field Maintenance Print Set (MP0O0553)
RLO1 Disk Drive IPB (EK-ORLO1-IP)

RLO2 Disk Drive IPB (EK-ORL02-1P)
RLO1/RLO2 User’s Guide (EK-RLO12-UG)

RLO1/RL0O2 Pocket Service Guide (EK-RL0O12-PG)
Microcomputer Interfaces Handbook (EB-20175-20)

NOTE

The M8013 must be installed above the M8014. The RLV11

controllers can only be used in a backplane built as an H9273
(slots A and B = LSI bus and slots C and D = interboard bus).
The BA11-N box currently is the only box that contains an
H9273 backplane.

931

RLV11/M8013,4

BCO6R CABLE

/—-—RED STRIPE
&

w2 ]

5
CABLE CONNECTOR

TO DRIVE

GND TP
O

VCO POT (5 K)

OVvCTP

o vcorTe

COMPONENT SIDE 1
RLV11 DRIVE BOARD MB8013

JUMPERS W2 & W4 IN PLACE FOR E PROM USE
JUMPERS W1 & W3 IN PLACE FOR MASKED ROM USE
W1

E49

ROM

EPROM

DV1

CY1

CA1

BY1

BA1

AY1

AAT

NOTE

JUMPERS ARE 0-OHM COMPOSITION RESISTORS.

RLV 11 Drive Module (M8013)

932

MR-2380

RLV11/M8013,4

COMPONENT SIDE 1

RLV11 BUS INTERFACE BOARD M8014
MSB

BUS ADDRESS SWITCH

LSB
MSB

VECTOR SWITCH
LS8

DY1

DAY

CY1

CA1

BY]1

BA1

AY1

AAT
MR-2391

RLV 11 Bus Interface Module (M8014)

CONTROL STATUE REGISTER (CSR)
DCRC

15%

OPI DS1[DSO}

774400 F;;R[ DE vann DIT
HNF

OPI

1 IE I

CRDY

l F2 l F1] FO 1 J

BA17

HCRC

]

DRDY
BA16

READ/WRITE

READ ONLY

READ

ONLY

MAR-2392

Control Status Register

933

RLV11/M8013,4
CSR Bit Definitions
Bit

Function

1-3

itiated and set when the seek operation is completed.
Function Code - These bits are set by software to indicate the

tes that the seDrive Ready (DRDY) - When set, this bit indica
seek operation
(no
nd
comma
a
e
receiv
to
ready
is
drive
lected
ion is inoperat
seek
a
when
d
cleare
is
in progress). The bit
command to be executed.

F2 F1 FO Command

Octal Code

MAINTENANCE MODE

WRITE CHECK

GETSTATUS

SEEK

READHEADER

WRITE DATA

READDATA

READ DATA WITHOUT

HEADER CHECK

Command execution starts when CRDY (bit 7) of the CSR is
cleared by software. In a sense, bit 7 can be considered a negative go bit.

Bus Address Extension Bits (BA15, BA17) - Two most significant bus address bits. Read and written as bits 4 and 5 of the
CSR, they function as address bits 16 and 17 of the BAR.

Interrupt Enable (IE) - When this bit is set by software, the controller is allowed to interrupt the processor at the assertion of
CRDY. This occurs at the normal or error termination of a command. Once an interrupt request is posted on the LSI bus, it is
not removed until serviced even if IE is cleared.

934

RLV11/M8013,4
CSR Bit Definitions (Cont)
Bit

Function

Controller Ready (CRDY) - When cleared by software, this bit

indicates that the command in bits 1-3 is to be executed. Software cannot set this bit because no registers are accessible

while CRDY is 0. When set, this bit indicates that the controller

is ready to accept another command.

8-9

Drive Select (DSO, DS1) - These bits determine which drive will
communicate with the controller via the drive bus.

Operation Incomplete (OPl) - When set, this bit indicates that
the current command was not completed within the OPI timer
period.

Data CRC (DCRC) or Header CRC (HCRC) or Write Check
(WCE) - If OPI (bit 10) is cleared and bit 11 is set, the CRC error

occurred on the data (DCRC). If OPI (bit 10) is set and bit 11 is
also set, the CRC error occurred on the header (HCRC).
if OPI (bit 10) is cleared and bit 11 is set and the function com-

mand was a write check, a write check error (WCE) has occurred.

NOTE

Cyclic redundancy checking is done only on the desired header. It is performed on the first and second header words, even
though the second header word is always 0.

Data Late (DLT) or Header Not Found (HNF Error) - When OPI
(bit 10) is cleared and bit 12 is set, it indicates that a data late
condition occurred on a read without header check operation.
One of two conditions exists:

Write Operation — The silo is empty, but the word count has not

reached zero. (Bus request was ignored for too long.)

Read Operation — The silo is full (word being read could not enter the silo and the bus request was ignored too long.)
When OPI (bit 10) is set and bit 12 is also set, it indicates that a
timeout occurred while the controller was searching
for the cor-

rect sector to read or write (no header; compare [NHF]).

935

RLV11/M8013,4
CSR Bit Definitions (Cont)
Bit

Function

Error Summary

Bit 12

RBit 11

OPI

WCE

O
1
1

1
0
0

1
0
1

HCRC
DLT
HNF

200 ms timeout

DCRC

Bit 10 Comments

Error

Function command is a write
check.

Nonexistent Memory (NXM) - When set, this bit indicates that

during a DMA data transfer, the memory location addressed did
not respond within 14 ms.

Drive Error (DE) - This bit is buffered from the drive error inter-

face line. When set, it indicates that the selected drive has
flagged an error, the source of which can be determined by executing a GET STATUS command.

To clear the drive error bit, execute a GET STATUS command
with bit 3 of the DAR.

Composite Error (ERR) - When set, this bit indicates that one or

more of the error bits (bits 10-14) is set. When an error occurs,
the current operation terminates and an interrupt routine is initiated if the interrupt enable bit (bit 6 of the CSR) is set.
BUS ADDRESS REGISTER (BAR)

774402 i

BA14

IBA9[BA8]BA7lBA6]BA5]BA4lBA3]BA2lBA1[ 0 }

BA11

BA13

BA15

]

]
\

BA10O

BA12

————

READ/WRITE

J
MR-2393

Bus Address Register
BAR Bit Definitions

The Bus Address Register (BAR) is a 16-bit word-addressable register with
an address of 774 402. Bits O through 15 can be read or written; bit O
should normally be written 0. Expansion bits 16 and 17 are programmable
via bits 4 and 5 of the CSR.

936

RLV11/M8013,4
The bus address register indicates the memory location involved in the

DMA data transfer during a read or write operation. The contents of the

BAR are automatically incremented by 2 as each word is transferred between system memory and controller in either direction. Clear the BAR by
executing a BUS INIT.

Disk Address Register (DAR)

The Disk Address Register (DAR) is a 16-bit read/write word-addressable
register with an address of 774 404. lts contents can have one of three

meanings, depending on the function being performed. Clear this register
by executing a BUS INIT.

DAR During a SEEK Command - To perform a seek function, it is necessary to provide address difference, head select, and head directional information to the selected drive.
DAR DURING SEEK COMMAND
15

774404 [DFB[DF7]DF6IDF5{DF4[DF3'DFZ[DH]DFOI 0 l 0 ]HS} 0] lDIR] 0

1 ]
MR-2394

DAR SEEK Command
Bit Definitions

Bits

Function

Marker (MRKR) - Must be a 1.

Must be a 0O, indicating to the drive that a SEEK command is
being requested and that the remaining bits in the register will
contain the seek specifications.

Direction (DIR) - This bit indicates the direction in which a seek
is to take place. When the bit is set, the heads move toward the

spindle (to a higher cylinder address). When the bit is cleared,
the heads move away from the spindle (to a lower cylinder address). The actual distance moved depends on the cylinder address difference (bits 7-14).
3

Must be a 0.

Head Select (HS) - Indicates which head (disk surface) is to be
selected. Set = lower; clear = upper.

5-6

Reserved.

7-14

Cylinder Address Difference (DF<8:0>) - Indicates the number

Must be a O.

of cylinders the heads are to move on a seek.

937

RLV11/M8013,4
DAR During READ or WRITE DATA Command - For a read, write, or write

1o
check operation, the DAR is loaded with the address of the first sector
the DAR

be transferred. Thereafter, as each adjoining sector is transferred,

is automatically incremented by 1. If the DAR increments to the nonexistent
sector address 50g, an OPI timeout will occur. The drive must then seek to
a new track if the transfer is to continue.

DAR DURING READING OR WRITING DATA COMMANDS
15 14 13 12 11 10 09 08 07 06 05 04 03

774404 lCABICA?]CAS‘CASICA4ICA3ICA2|CA1[CAO‘ HS ]SASISA4ISA3[SA2‘ SA1lSAfl
MR-2385

DAR READ/WRITE DATA Command
Bit Definitions

Bit

0-5

Function

Sector Address (SA<5:0>) - Address of one of the 40 sectors

on a track. (Octal range is O to 47.)

Head Select (HS) - Indicates which head (disk surface) is to be

7-14

Cylinder Address (CA<8:0>) - Address of one of the 256 cylin-

Must be a O.

selected. Set = lower; clear = upper.

ders. (Octal range is O to 377.)

DAR During a GET STATUS Command - After the GET STATUS command
is deposited in the CSR, it is the DAR’s responsibility to get the command
transferred to the drive. Therefore, the DAR must also be programmed
along with the CSR to do the GET STATUS command.

DAR DURING GET STATUS COMMAND
15

s[ T [ T

[ [

e s [oJe [o [o oo [ [
MR-2396

DAR GET STATUS Command

938

RLV11/M8013,4
For a GET STATUS command, the DAR register bits must be programmed
as follows.

DAR Register Bits for a GET STATUS Command
Bit

Function

Marker (MRKR) - Must be a 1.

Get Status (GS) - Must be a 1, indicating to the drive that its
status word is being requested. At the completion of the GET
STATUS command, the drive status word is read into the controller multipurpose (MP) register (output stage of FIFO). With
this bit set, bits 8-15 are ignored by the drive.

Must be a O.

Reset (RST) - When this bit is set, the drive clears its error register of soft errors before sending a status word to the controller.

4-7

Must be a 0.

8-15

Not used.

Multipurpose Register (MPR)
The MPR is two registers bearing the same base address. When writing
into that location, the word counter accepts the data. When reading from
that location, the FIFO output buffer provides the data.

MPR AFTER GET STATUS COMMAND

SKTO

MR-2397

MPR Status Word

MPR After 2a GET STATUS Command - When a GET STATUS command is
executed and a status word is returned to the controller, the contents of

the MPR (FIFO output stage) are defined as follows.

939

RLV11/M8013,4

Bits 0-2 - State<C:A) (ST<C:A>) - These bits define the state of the
drive.

Definition

Bits
C

O
O
0
0
1

0
1
1

O | Load Cartridge
SpinUp
1|
0 | Brush Cycle
Load Heads
1
O | Seek Track Counting

1
1

0 | Unload Heads
Spin Down
1

Seek LinearMode (Lock On)

Bit Definitions

Bit

Function

Brush Home (BH) - Asserted when the brushes are not over the
disk.

4
5

Heads Out (HO) - Asserted when the heads are over the disk.
Cover Open (CO) - Asserted when the cover is open or the dust

cover is not in place.

Head Select (HS) - Indicates the currently selected head.

Drive Type (DT) - Set = lower; clear = upper. Set = RLOZ;

clear = RLO1.

Drive Select Error (DSE) - Indicates that multiple drive selec-

tion was detected.

Volume Check (VC) - VC is set every time the drive goes into

load heads state. This asserts a drive error at the controller but
not on the front panel. VC is an indication that the program does
not really know which disk is present until it has read the serial
number and bad sector file. (The disk might have been changed

while the heads were unloaded.)

Write Gate Error (WGE) - Indicates that the drive sensed that

write gate was asserted when sector pulse was asserted, or
write gate was set with the drive not ready, or the drive was
write locked.

940

RLV11/M8013,4
Bit Definitions (Cont)

Bit

Function

Spin Error (SPE) - Indicates that the spindle did not reach
speed in the required time; or indicates over speeding.

Seek Time Out (SKTO) - Indicates that the heads did not come
on track in the required time during a SEEK command or loss of
“ready to read/write during lock on’’ mode.

Write Lock (WL) - Indicates write lock status of selected drive.
Set = write protected.

Head Current Error (HCE) - Indicates that write current was detected in the heads when write gate was not asserted.

Write Data Error (WDE) - Indicates that write gate was asserted
but no transitions were detected on the write data line.
MPR DURING READ- HEADER COMMAND
15

774406 WSRDIECWICA?lCAB,CASICA4|CA3‘CA2]CA1ICAOI HS ‘SA5|SA4ISA3ISAZISA1lSfi)J

Wowo[oJofofofofoofofofoofofofo]o]o]
3RD
WORD

CRC15

CRC13

CRC14

CRC11

CRC12

CRC5H

CRC7

CRC9

CRC10

CRC8

CRC6

CRC4

CRC3
CRC2

CRC1
CRCO
MR-2398

MPR Three Header Words

MPR After a Read Header Command - When a READ HEADER command
is executed, three words will be stored in the multipurpose register (FIFO

output buffer). The first header word will contain sector address (SA0:SAS5),

head select (HS - set = lower; clear = upper), and cylinder address information (CAOQ:CA8). The second word will contain all Os. The third word will

contain the header CRC information. All three words are readable by the
main program.

941

RLV11/M8013,4
MPR DURING READ/WRITE COMMANDS FOR WORD COUNT
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01

I
wWC12

e 2 e L

WwWC10

WC11

MR -2399

MPR Used As Word Counter
Bit Definitions

Bit

Function

0-12

Word Count (WC<12:0>) - 2’s complement of total number of

13-15

Must be a 1 for word count in correct range.

words to be transferred.

MPR During READ/WRITE DATA Commands — When transferring data via
DMA, the MPR functions as a word counter and is loaded by program with
the 2's complement of the number of words to be transferred. It is then incremented by 1 by the controller as each word is transferred. The reading
or writing operation generally is terminated when the word counter over-

flows. The word counter can keep track of from one data word to the full 40sector count of 5120 data words (decimal). The maximum number of words
that can be transferred in a single operation is limited by the number of sectors available to be written in the track.

NOTE

The RLO1/RLO2 disk drive will not do spiral read/writes. If
data is to be transferred past the end of the last sector of a
track, it is necessary to break up the operation into the following steps.

Program the data transfer to terminate at the end of the

Program a seek to the next track. This can be accomplished either by a head switch to the other surface but
the same cylinder, or a head switch to move to the next

last sector of the track.

cylinder.

Program the data transfer to continue at the start of the

first sector on the next track.

942

RLV12/M8061

RLV12 DISK CONTROLLER

Power Requirements
+5Vdc = 5% at 5.0 A
+12 Vdc = 5% at 0.1 A

Bus Loads
DC

2.7

Optional Drive Cables

Cable

Part No.

Length

BC20J-20

7012122-20

6 m (20 ft)

BC20J-40

7012122-40

BC20J-60

7012122-60

12 m (40 ft)
18 m (60 ft)
NOTE

Total length of cable(s) from controller to the last drive must
not exceed 30 m (100 ft).

FCC Cable Information

Order Number
RLV12-AP

Factory installed shielded cable and filter connector assembly,
plus RLV12 option.

RLV12

Disk Controller option only.

CK-RLV1A-KA

Cabinet Kit for BA23/Micro

CK-RLV1A-KB

Cabinet Kit for H3012/PDP-11/23S
Cabinet Kit for H349/PDP-11/23-PLUS

CK-RLV1A-KC

943

RLV12/M8061
Standard Addresses

Standard Address Assignments

Device
Address

Starting

address range

Starting
address

16-Bit
Addressing

18-Bit
Addressing

174400

774400

22-Bit
Addressing’

160000-177770 | 760000-777770 | 17760000~ 1 7777760
17774400

8 (5 are used;
3 are not)

Number of
registers

BAR (174402)
DAR (174404)
MPR (174406)

CSR (174400)

CSR (774400)
BAR (774402)
DAR (774404)
MPR (774406)

CSR (17774400)
BAR (17774402)
DAR (17774404)
MPR (17774406)
BAE (17774410)

Vector range

0-774

Standard

160

Registers

used

interrupt
Vector

vector

*Factory configuration (FCO M8061-002)
Diagnostic Programs

Refer to Appendix A.

Related Documentation

RL V12 Disk Controller User’s Guide (EK-RLV12-UG)
RLO1 Field Maintenance Print Set (MP0O0347)
RLO?2 Field Maintenance Print Set (MP00553)
RLO1 Disk Drive IPB (EK-ORLO1-IP)
RLO2 Disk Drive IPB (EK-ORLO2-IP)
RLO1/RLO2 User’s Guide (EK-RLO12-UG)
RLO1/RLO2 Pocket Service Guide (EK-RLO12-PG)

944

RLV12/M8061
CONFIGURATION
The user or installer can configure and install the RLV12 in a 16-, 18-, or
22-bit LSI-11 bus. The user can select the device address, interrupt vector,
and memory parity error abort feature.

Device Address Selection

Software control of the RLV 12 is by means of four or five device registers
— CSR, BAR, DAR, MPR, and BAE. Four registers are used for 16- or 18-bit
addressing; five registers are used for 22-bit addressing. The bus address
extension register (BAE) is added for upper address bit selection for 22-bit
addressing. The usual device starting address is as follows.

Device Starting Address

Addressing Mode

16-bit
18-bit
22-bit

Starting Address (Octal)

174400
774400
| 17774400

The first register, the CSR, is assigned the starting address, and the other
registers are incremented by 2.

The device starting address is selected by jumpers for bits 03 through 12. A
jumper from the selected bit to ground (M22) decodes a 1; no jumper decodes a 0; and a jumper to +5 V (M11) decodes an X (don’t care) condition. The following figure shows the RLV 12 device starting address format.
NOTE

For 22-bit addressing, bit A3 is not decoded in the starting address.

945

RLV12/M8061

6LG-VHWN

1D3INNOD "3INO TV¥2ID07 vV 300234 OL (ZZW NId) GNNOHD OL 1O3INNOD

p—

Ss3nNHA4IaAgdav

S30 03dv 1vOI1D07 ‘0d3Z

l
s
8
A
¢
e
d
a
i
u
l
Y
p
e
o
Q
4
y
g
rA 4£1M0N3V143HS
l

NOILVYHNDI4NOD

00vvLL
covviL
14812444
S0bvLL
OlbviL

4h)

450

1M£2N3v734S ONIS3HAv

946

4vda HdW vd

RLV12/M8061

ENABLE CRYSTAL
M29

:]4—M28
ENABLE

VCO CLK

M27 M26
MEMORY PARITY ERROR

eI yM23

M11-+5v |

\ TEST POINT
M30

M12- A3

M24
M25

M13 - A4
w3

| ABORT SELECTION

SEE NOTE

M14
- A5

DEVICE

ADDRESS

PINS

M15
- A6

M16 - A7

M10 M9

1 0" "0

M18-A9

M19-A10 | ¢

M20
- A11

M21-A12

| e

PASS CD PRIORITIES

M8
V6

M6
V4

M5
V3

M4
V2

VECTOBUSH

ofefsle
off
E23

(CDMG, CIAK)

ENABLE

22-BIT ADDRESSING
MPR-5748

NOTE:

THE MEMORY PARITY ERROR ABORT
FEATURE IS AVAILABLE FOR USE

WITH MEMORIES THAT HAVE PARITY
ERROR CHECKING.

THIS FEATURE DOES NOT HAVE TO
BE DISABLED FOR MEMORIES THAT

DO NOT HAVE PARITY ERROR

CHECKING. THE PINS ARE
CONNECTED AS FOLLOWS:

CONNECTION

FUNCTION

M23 - M24

NO PARITY

M24 - M25

PARITY ERROR ABORT

RLV 12 Module Layout

947

RLV12/M8061
interrupt Vector

The interrupt vector is preset
The interrupt vector has a range of 0 to 774.anothe
r vector by changing the
select
may
user
The
160.
at the factory to
tes a 1 for that bit; no
genera
M3
to
jumpers for bits V2-V8. A connection
priority level 4.
at
is
pt
interru
RLV12
The
0.
a
tes
genera
connection
20
0

21
0

FACTORY

}

)

09
o

08 07 08 05 04 03
Lvea | vz | ve | vs | va|vVv3

|v2]

(

CONFIGURATION
160

([

R—

INTERRUPT VECTOR PINS

CONNECT TO PIN M3 TO DECODE A LOGICAL ONE.
NO CONNECTION DECODES A LOGICAL ZERO.

MR-5750

RLV 12 Interrupt Vector Format

Bus Selection

When
The RLV 12 module can be used on 16-, 18-, or 22.-bit LSI-11 buses. M1
to
Jumper
bus.
22-bit
a
on
s
operate
module
the
sent from the factory,
M2 is installed, which enables bank select 7 (BBS7) to be determined by the
upper address bits (13-21). When the jumper is removed, the RLV12 has
an 18-bit mode bank select 7.

NOTE

The RLV12 may be used in a 16- or 18-bit system while configured to a 22-bit operation (factory-shipped configuration)
provided it is the only RLV12 in the system.

Memory Parity Error Abort Feature

When reading the system’s optional memory with parity error detection, a
parity error will set OPl and NXM of the CSR. This is a unique error condition that aborts the current command to the RLV12. This error abort feature
is possible only with memories that have parity data bits.

The RLV 12 is sent from the factory with the memory parity error abort feature enabled. To disable parity error abort, remove the jumper between pins

M24 and M25 and install a jumper between pins M23 and M24. This feature
does not have to be disabled for nonparity memories, as parity errors are
not generated. Parity error abort uses data bits 16 and 17.

948

RLV12/M8061
Jumpers That Remain Installed
The module has two jumpers, W1 and W2, that enable priority signals to
pass through the module. The module has these jumpers installed, and
they should be left in.

Jumper | Signal
W1

CIAKI to CIAKO

CDMGI to CDMGO

One jumper, W3, enables the word count register to automatically increment during a DMA operation. This jumper is used for factory testing
and should be left in.

Two jumpers on the module disable the crystal oscillator and the voltagecontrolled oscillator (VCQ) during factory testing. These jumpers should be
left in.

Oscillator

Jumper

M26-M27 | VCO
M28-M29 | Crystal

CONTROL STATUS REGISTER (CSR)

The control status register is a 16-bit, word-addressable register with a
standard address of 774400 for 18-bit addressing, and 17774400 for 22-bit
addressing. Bits 01 through 09 can be read or written; the other bits can
only be read. The bit functions are described in the following table.
When the LSI-11 bus is initialized with BINIT L, bits 01-06 and 08-13 are
cleared, and bit 07 (CRDY) is set. Bit 00 (DRDY) is set when the selected
drive is ready to accept a command; otherwise, this bit is cleared. Bit 14
(DE) is clear as long as there is no drive error. Otherwise, this bit is set and

stays set until the drive error is corrected; or if bit 03 (drive reset) is set in
the DAR and the controller is sent a get status command, the DE bit is
cleared.

Bit 15 (ERR) is set when there is a drive or controller error in bits 10-14.
L
STATUS REGISTER (CSR)
CONTRO

[ERR} DE l E3‘»E2 l E?l EO lDS1lDSOl

llE {

CRDY

l F2 I F1l FO l

DRDY

BA17
BA16

READ ONLY

READ/WRITE

;A\/—/
%%%8

MR-8679

Control Status Register (CSR)
949

RLV12/M8061
RLV12 Control Status Register Bit Assignments
Bit

Name

DRDY

Description

Drive ready - When set, this bit indicates that the
selected drive is ready to receive a command or
supply valid read data. The bit is cleared when a
seek or head select operation is started and set
when the seek operation is completed.

01-03

FO-F2

Function code - These bits are the function code set

by software to indicate the command to be executed.

=0
0O
O =
—_ O =

OO0 = =00

e
A

. w0000

Function
F2 F1 FO

Command
Maintenance mode
Write check
Get status
Seek
Read header
Write data
Read data
Read data without
header check

Octal
Code
O
1
2
3
4
5
6
7

Command execution starts when CRDY (bit 07) of
the CSR is cleared by software. The function code is
cleared by initializing the bus (BINIT L).

04, 05

BA16,

BA17

Extended address bits - These two bits are the upper-order bus address bits for 18-bit buses. These
bits are read and written as bits 04 and 05 of the
CSR. They function as address bits 16 and 17 of the
BAR. Writing bits 04 and 05 of the CSR also writes
bits 0 and 1 of the BAE.

Interrupt enable - When CRDY is asserted, bit 06 allows the controller to interrupt the processor. This
interrupt occurs at the termination of a command.
Once an interrupt request is placed on the LSI-11
bus, it is not removed until acknowledged by the LSI-

11 processor even if IE (bit 06) is cleared. This bit is

cleared by initializing the bus.

950

RLV12/M8061
RLV12 Control Status Register Bit Assignments (Cont)
Bit

Name

Description

CRDY

Controller ready - When cleared by software, this bit
indicates that the command in bits 01-03 is to be executed. This bit is set by the controller at the completion of a command, at the detection of an error, or

by initializing the bus. Software cannot set this bit
because registers are not accessible while CRDY
is O.

08, 09

DSO,

10-13

EO-ES

Drive select - These bits determine which drive will
communicate with the controller via the drive bus.
These bits are cleared by initializing the bus.

Controller status errors - These bits are the error
code set by the controller to indicate one of the following errors.

Error Code
E3 E2 E1 EO Error

0
O
O

0
0O
0

O
1
1

1
1

0O
0

0
O

O
O

1t
1

0
0

1
O
1
O
1
O
1

Operationincomplete (OPI)
DataCRC(DCRC)
Header CRC (HCRC)

Datalate(DLT)
Headernotfound (HNF)
Nonexistent memory (NXM)
Parity error abort (PARERR)

Octal
Code

1
2
3
4
5
10
11

Operation incomplete indicates that the current
command was not completed within the OPI timeout
period of 5560 ms.

A data CRC error indicates that while reading the

data field from the disk an error was found.

A header CRC error indicates that while reading
the header from the disk an error was found. The
CRC check is performed on the first and second
header words, although the second header word is
always O.

Data late indicates that the FIFO RAM was more
than half full and the controller was not able to read
the next sequential sector. This error may occur during a read without header check command.

951

RLV12/M8061
RLV12 Control Status Register Bit Assignments (Cont)

Bit

E Name

Description

Header not found indicates that an OPI timeout occurred while the controller was searching for the
correct sector to read or write. A header compare
did not occur.

A nonexistent memory error indicates that during a
DMA transfer the memory location addressed did not
respond with RPLY within 10 us.

A memory parity error abort indicates that a parity
error was detected while reading the system’s op-

tional memory that has parity error checking. If an
error was detected, the current command to the
RLV 12 is aborted.

Drive error - This bit is buffered from the drive error
interface line. When set, it indicates that the selected drive has flagged an error, the source of

which can be determined by executing a get status

command. DE will not set ERR (bit 15) or CRDY (bit

07) until the usual occurrence of CRDY.
15

ERR

Composite error - When set, this bit indicates that
one or more of the error bits (bits 10-14) are set.
When an error occurs, the current operation terminates and an interrupt routine is started if the interrupt enable bit (bit 06 of the CSR) is set.

All error bits are cleared by initializing the bus by
starting a new command, with the exception of DE
and ERR if they were caused by a drive error.

BUS ADDRESS REGISTER (BAR)

The bus address register is a 16-bit, word-addressable register with a
standard address of 774402 for 18-bit addressing, and 17774402 for 22-bit

addressing. Bits 00 through 15 can be read or written; bit 00 is usually written as 0. The bus address register indicates the memory location for the
DMA data transfer during a read or write operation. The register’s contents
are automatically incremented by 2 as each word is transferred between

the system memory and the controller.

952

RLV12/M8061
The bus address can be expanded for an 18-bit LSI-11 bus by using bits 04
and 05 (BA 16 and 17) of the CSR or by using bits 00 and 01 of the BAE

The bus address can be expanded for a 22-bit LSI-11 bus by using the BAE
register (BAE 16-21).

NOTE
When using 22-bit mode, writing CSR bits 04 and 05 modifies

BAE bits 00 and 01 and vice versa.
The BAR is cleared by initializing the bus (BINIT L).

BUS

ADDRESS REGISTER {BAR)

LT LT | [msfosa]swrlsnc]suclanafoncfoancfon]
o
BA15 l BA13
BA14

BA12

BAT1

BA10
>y

READ/WRITE

R 5752

Bus Address Register (BAR)

DISK ADDRESS REGISTER (DAR)
The disk address register is a 16-bit, read/write, word-addressable register
with a standard address of 774404 for 18-bit addressing, and 17774404 for
22-bit addressing. lts contents have one of three meanings, depending on
the command being performed.

Disk Address Commands

Command

DAR Function

Seek

Head selected, number of cylinders to move,
direction.

Read data or write data

Head selected, cylinder address, sector address.

Get status

Send

drive

status

registers.

The DAR is cleared by initializing the bus (BINIT L).

953

MPR;

reset

the

error

RLV12/M8061
DAR During a Seek Command

d
To perform a seek command, the program must provide the head selecte
The

(HS), direction to move (DIR), and the cylinder address difference (DF).

bits are as follows.

DAR DURING SEEK COMMAND

01 00
15 14 13 12 11 10 09 08 07 06 05 04 03 02

e oelrerrsproroel o Lo [T e o] o 1]
(RLO2 ONLY)
MR-5753

DAR During a Seek Command

DAR Seek Command Word Format
Name

Description

MRKR

Marker - Must be a 1.

None

Must be a 0, indicating to the drive that a seek com-

mand is being issued and that the other bits in the
register hold the seek specifications.

DIR

Direction - This bit indicates the direction in which

the seek is to take place. When the bit is set, the
heads move toward the spindle (to a higher cylinder
address). When the bit is cleared, the heads move

away from the spindle (to a lower cylinder address).

The actual distance moved depends on the cylinder
address difference (bits 07-15).

None

Must be a O.

Head select - Indicates which head (disk surface) is

05, 06

None

Reserved.

07-15

Cylinder address difference - Indicates the number

to be selected: 1 = lower, O = upper.

of cylinders the heads are to move on a seek.

954

RLV12/M8061
DAR During a Read, Write, or Write Check Command
For a read, write, or write check command, the DAR provides the head se-

lected (HS) and the address of the first sector to be transferred (SA). The
bits are described below. As each sector is transferred, the DAR sector ad-

dress increments by 1.

DAR DURING READ OR WRITE DATA COMMANDS

)
e o (D D e

eB
MR-5754

DAR During a Read, Write, or Write Check Command

DAR Read/Write Data Command Word Format
Bit

Name

Description

00-05

Sector address - Address of one of the 40 sectors
on a track. (Octal range is 0 to 47.)

07-15

Head select - Indicates which head (disk surface) is

to be selected: 1 = lower; O = upper.

Cylinder address - Address of one of the 256 cylinders for RLO1 or 512 cylinders for RL0O2. (Octal
range is 0 to 777.)

DAR During a Get Status Command

Both the CSR and the DAR must be programmed to perform a get status
command. Then a get status command is placed in the CSR. The DAR bits
are as follows.

DAR DURING GET STATUS COMMAND

LD DL [ Lo [e[o [ fee o]
MR-5755

DAR During a Get Status Command

955

RLV12/M8061
DAR Get Status Command Word Format

Bit

Name

Description

MRKR

Marker - Must be a 1.

Get status - Must be a 1, indicating to the drive to

send its status word. At the completion of the get
status command, the drive status word is read into
the controller multipurpose register (MPR). With this
bit set, bits 08-15 are ignored by the drive.

None

RST

Must be a 0.

Reset - When this bit is set, the disk drive clears its

error register of soft errors before sending a status
word to the controller.

04-07

None

Must be a O.

08-15

None

Not used.

MULTIPURPOSE REGISTER (MPR)

The multipurpose register is a 16-bit, read/write, word-addressable register. It is accessed using the standard address of 774406 for 18-bit address-

ing, and 17774406 for 22-bit addressing. Following a read header command or a get status command, reading the MPR obtains sector header or

drive status information.

Writing to the MPR is used to set the word count. The word count is cleared

by initializing the bus (BINIT L).

Writing the MPR to Set the Word Count

Before starting a DMA transfer, the MPR is loaded with the word count. The
program must load the MPR with the 2’s complement of the number of
words to be transferred. The bits are described below. As each word is
transferred, the MPR is automatically incremented by 1. The reading or
writing operation continues until a word count overflow occurs, indicating
that all words have been transferred.

The word count can range from 1 to 5120 data words. The maximum word
count is limited by the maximum number of sectors available (40) and the
maximum words per sector (128).
NOTE

Once written, the word count cannot be read back. Reading
the MPR does not change the word count.

956

RLV12/M8061
WRITING WORD COUNT INTO MPR

wC12

WC10

WC1T1

MR 57566

Writing the MPR to Set the Word Count

MPR Word Count Format

Bit

Name

Description

00-12

Word count - This is the 2’s complement of the total
number of words to be transferred.

13-15

None

Must be all ones for word count in correct range.

Reading the MPR After a Read Header Command
When a read header command is executed, three words can be sequentially read from the MPR, as the following figure shows. The first word includes the sector address, the head selected, and the cylinder address.
The second word is all zeros. CRC information is the header for the third
word.

READING MPR AFTER READ HEADER COMMAND

.10

0OV

&figRDIEABlCA7[CA5lCASICA4]CABICA2[CA1[CAO[P%SISASISA4ISABISA218A1[SAOJ

3RD
WORD

CRC15

CRC13

CRC14

CRC11

CRC12

CRC9

CRC10

CRC7

CRCS8

CRC5

CRCS6

CRC4

CRC3

CRC2

CRC1

CRCO
MR 5757

Reading the MPR After a Read Header Command
(Three Header Words)

957

RLV12/M8061
Reading the MPR After a Get Status Command

After a get status command is executed, a status word is stored in the

drive includes information on
MPR. The status word from the selected disk errors.
The bits are described
drive
any
and
drive
the
of
state
the functional
in the following table.

READING MPR AFTER GET STATUS COMMAND

IWDE(HCE[ WLI

]SPE]WGE] vC IDSE[ DT l HS ] CO l HO I BH lSTC'STBlSTfJ

SK]TO

STATE
MR-5758

Reading the MPR After a Get Status Command
MPR Status Word Format

Bit
00-02

Name

Description

STA,
STB,

STC

These bits (A, B, and C) define the state of the drive
as follows.

State of Drive

0
O
0
0
1

0
O
1
1
0

0
1
0
1
0

Load state
Spin up
Brush cycle
Load heads
Seek track counting

1
1

0
1

Unload heads
Spin down

Seek linear mode (lock on)

Brush home - Asserted when the brushes are not

Heads out - Asserted when the heads are over the

over the disk.

disk

Cover open - Asserted when the cover is open or

the dust cover is not in place.

Head select - Indicates the head selected: 1 =
lower, O = upper.

958

RLV12/M8061

MPR Status Word Format (Cont)
Bit

Name

Description
Drive type - Indicates the type of disk drive: 0 =

RLO1,
08

DSE

1 = RLO2.

Drive select error - Indicates multiple drive selection
is detected.

Volume check - VC is set every time the drive goes
into load heads state. This asserts a drive error at
the controller, but not on the front panel. VC is an indication that the program does not know which disk
is present until it has read the serial number and bad

sector file. (The disk might have been changed while
the heads were unloaded.)
10

WGE

Write gate error - Indicates that the write gate was
asserted when the drive was not ready, the sector
pulse was asserted, or the drive was write locked.

SPE

Spin error - Indicates that the spindle did not reach
full speed within a specific time, or that it is turning
too fast.

SKTO

Seek time out - Indicates that the heads did not
come onto track within a specific time during a seek
command.

Write lock - Indicates write lock status of selected
drive:

HCE

O = unlocked; 1 = protected.

Head current error - Indicates that write current was
detected in the heads when write gate was not as-

serted.

WDE

Write data error - Indicates write gate was asserted,
but no pulses were detected on the write data line.

959

RLV12/M8061

BUS ADDRESS EXTENSION REGISTER (BAE)
register used to
The bus address extension register is a 6-bit read/write
BAE has a standard

The
drive address bits 16-21 for a 22-bit LSI-11 bus.write
the BAE loads TS
address of 17774410 for 22-bit addressing. A s banktoselect
7 (BBS7 L) to
enable
BAE
the
g
Readin
0-5.
DAL 0-5 into BAE
M2 on the
and
M1
n
betwee
ted
the LSI-11 bus. (A jumper must be connec
are all
13-21
bits
s
addres
When
ing.)
address
22-bit
enable
controller to
ones, the RLV12 drives BBS7 L to direct data to the 1/0 page.

s lines 16 and 17) are
The two least significant bits of the BAE (bus addres
bits can be read or written
mirrored in bits 04 and 05 of the CSR. The same
as CSR bits 04 and 05 or BAE bits 00 and O1.
NOTE

Writing CSR bits 04 and 05 modifies BAE bits O and 1 and vice
versa.

The BAE register is cleared by initializing the bus (BINIT L).
BAE DURING 22-BIT ADDRESSING MODE

03 02

05 04

oo T T T L1 1]
Tolo
ColeTefooo
l

BA21

BA20

BA19

BA18

BA16

BA17
MR 5839

BAE Register Word Format

960

RQDX1/M8639

RQDX1 AND EXTENDER CONTROLLER MODULE
(RX50, RD51, RD52)

Bus Loads

Amps

+5V
6.4 A

+12 Vdc
7.3 mA

8 A (max.)

10 mA (max.)

AC
25

DC
1

Standard Addresses

Address Mode

Octal Address

16-bit
18-bit

772150

22-bit

17772150

172150

Vectors

Software selectable (normally set to 154)
Diagnostic Programs

ZRQA??
ZRQB??

BIN RDRX Performance Exerciser
BIN RDRX Formatter (RD51)

Related Documentation

RQDX1 Field Maintenance Print Set (MP01731-01)
UDAS50 Programmers Document Kit (QP-905-GZ)
RODX1 Controller Modules User’s Guide (EK-RQDX1-UG)

961

MNYE 1037138 £
ONISS3HAQY
MNVE 123738 £ HO4

0300230
1 ¥ 'l

L8CLLI-HN

LLLLLLLLL 00
RQDX1/M8639

14!

962

RQDX1/M8639
RQDX1 Standard Address Jumper Configuration
Jumper

State

ouT

A10

Ali

ouT

A12

Address selection (772150)

LOGICAL UNIT NUMBER SELECTION
The location of the RQDX1 controller module logical unit number jumpers is shown
below. These jumpers are set to the lowest logical unit number assigned to any
disk/diskette drive controlled by the module. The controller module automatically
sizes the logical unit configuration during initialization to determine how many (of

four possible units) are actually present. This automatic sizing eliminates the need
for the reconfiguration of jumpers when units (RD51 or RX50 drives) are added to
or removed from the controller module. The standard configuration for the logical

unit number jumpers (selecting logical unit number 0) is listed. To configure the

module for logical unit numbers beginning with other than unit number 0, use the
format shown below to determine the appropriate jumper configuration.
LOGICAL

UNITS
LUN
JUMPER SPECIFIED
7

32-35

28-31

24-27

20-23

16-19

12-15

811

4-7

ONLY ONE JUMPER IS
INSTALLED AT ANY
TIME

ALL JUMPERS REMOVED
SPECIFIES LOGICAL
UNITSO-3
MR-11286

RQDX1 Logical Unit Number Jumper Format
963

RQDX1/M8639
RQDX1 Standard Logical Unit Number Jumper Configuration
Jumper

State

LUN1

ouT

LUNZ2
LUNS
LUN4

ouT
ouT
ouT

LUNS

ouT
ouT

LUNG6
LUN7

l
number (0)*
ica
unit
Log

ouT
OouT

LUNS

This indicates that logical unit numbers 0-3 are assigned to this controller module.
The controller will automatically determine if less than four logical units are
present.

RQDX1-E Extender Module Jumper Configuration

The RQDX1-E extender module is a dual-height module that provides signal connectors and requires appropriate jumper configurations. The J2 connector
receives signals from the RQDX1 controller module. The other connectors (J1 and
J3) distribute these signals to the disk and diskette drives. Jumper functions for
the RQDX1-E extender module, as well as the jumpers installed in the factory

U -~

®
e

@
@

Ry —

OOGDJJL_

@ XU -

9%}

BRI
-

& & ¢ @

e eeeeoe6

@ @

’]

== e

[
Q= W~

e ¢e6 80 e %8

configuration, are listed.

{3 W3

— |

’]

|
MR-116577

RQDX1-E Extender Module Jumper Locations

964

RQDX1/M8639
RQDX1-E Extender Module Jumper Configuration
Factory

Jumpers
W1-W4

Functions

Configuration*

Must be installed

W1-W4

(Manufacturing use only)
JRD1-JRD3

Select the external drive to be

JD1 to JRD1

JD1-dD3

connected to the J3 connector

JD2 to JRD2

JRX1-JRX3

JD3 to JRD3

JB1-JB8

Determine which connector (J2 or J3)

JA2 to JC2

JA-JAS8

the RD read/write will connect to

JA2 to JC2

JC-JC8

JA3 to JB3
JA4 to JB4

JAS to JB5S

JAG to JB6

JAT7 to JC7
JAS8 to JC8

Factory configuration is set to connect an external RD51 disk drive to connector

J3. To configure the module for an external RX50 (connected to J3), jumpers
JD1 through JD3 are connected to JRX1 through JRX3 and jumpers JA1
through JA8 are connected to JB1 through JBS.
interrupt Vector

The interrupt vector has a range of 0 to 774 and is software selectable. A vector

selected by software must be greater than 0. The normal interrupt vector used by
the RQDX1 controller module is 154.
interrupt Request Level

The RQDX1 controller module interrupts at priority level 4 are determined by E3, a
DCO003 chip.

965

RQDX1/M8639
RQDX1 CONTROLLER MODULE INSTALLATION

slot of the
The RQDX1 module (M8639) is typically installed in the last occupied the
M8639
backplane. If empty slots are left between the other modules and
date
accommo
to
slots
empty
those
in
G7272)
no.
(part
cards
grant
install
module,
the interrupt and direct memory access structure of the backplane.

Before installing the module, make sure that the address and logical unit number

jumpers are properly configured.

the 50-conductor signal cable (part no. BC02D-1D) to the J1 connector on

Install
the M8639 module. This cable must be connected to a signal distribution panel
that will connect the appropriate signals to the RDJ1 andfor RX50 drives. An
example of the MICRO/PDP-11 signal distribution panel connecting the M8639
module to an RD51 disk drive and an RX50 diskette drive is on the next page. The

RD51 disk drive requires two signal cable connections. One is a 20-conductor
cable (part no. 17-00282-00), the other is a 34-conductor cable (part no. 17-0028600). The RX50 diskette drive requires a single 34-conductor signal cable (part no.
17-00285-02).

RQDX1-E EXTENDER MODULE OPTION

Typically, in the MICRO/PDP-11, the RQDX1 controller module is located in the
same mounting box as the disk and/or diskette drives that it controls. However, if
the system mounting box cannot hold all of these drives, the optional RQDX1-E
extender module may be used to connect the RQDX1 controller module signals to
any drive that is external from the system mounting box.
NOTE

Jumper selection (for configurations listed) is made by attaching twoposition jumper clips (part no. 12-18783-00).
RQDX1-E EXTENDER MODULE INSTALLATION

Installation of the RQDX1-E extender module option in the MICRO/PDP-11 system
(BA23 mounting box) is as follows. The M7512 dual-height module is installed in
the backplane slot directly below the M8639 (RQDX1) module, in connectors A and
B. A cable (part no. BC02D-0K) connects the RQDX1 controller module to the
RQDX1-E extender module through the J2 connector. Another cable (part no. 7018652-01), attached to the J3 connector, connects the RQDX1-E extender module
to a mounting plate (part no. 74-2866-01). This is mounted to the system’s patch
and filter panel assembly. The entire cable and mounting plate assembly may be
ordered as part number 70-20691-01. This external plate provides the signals to
be sent to the external drive. A third cable (part no. BC02D-1D - attached to the J1
connector on the RQDX1-E extender module) is connected to the signal distribution panel in the mounting box, providing signals to the disk or diskette drives that
are installed in the system mounting box.

Cable Signals
RQDX1 controller module signals on the J1 connector.

966

¥ d4v08

LXaoy1-dad/OdOIW|eubisuonquisigsuonosuo)
LNOYHA TINVd

RQDX1/M8639

S8ZL-HN

LGay

967

ONILNNOW
»31Vd

3-1XdJdoy
CLSLIN

£zva

NOILN8IY1SIa qNuvos

J-1XadyJ8puslix3SINPOSuOoiloBUOD

sNa-0

4 LNOY 1INV

G6ZLL-dW

RQDX1/M8639

968

RQDX1/M8639
J1 Connector Signals

J1 Pin

Signal Name

MFMWRTDT1 (H) (RD51 only signal)

MFMWRTDT1 (L) (RD51 only signal)

GROUND

HEAD SEL 2 (L) (RDXX only signal)*

GROUND

SEEKCPLT (L) (RD51 only signal)

RD1 RDY (H) (RD51 only signal)

WRT FAULT (L)

DRVBUSOE (L)

HEAD SEL 1 (L) (RD51 only signal)

RXOWPTLED (L) (RX50 only signal)

RDO RDY (H) (RD51 only signal)

RX1WPTLED (L) (RX50 only signal)

DRVSLOACK
(L) (RD51 only signal)

MFMRDDATO (H) (RD51 only signal)

MFMRDDATO (L) (RD51 only signal)

MFMWRTDTO (H) (RD51 only signal)

MFMWRTDTO
(L) (RD51 only signal)

MFMRDDAT1 (H) (RD51 only signal)

MFMRDDAT1 (L) (RD51 only signal)

GROUND

REDUCWRTI (L)

RDOWRTPRO (L) (RD51 only signal)

DRV SEL 4 (L)

GROUND

INDEX (L)

RD1WRTPRO (L) (RD51 only signal)

DRV SEL 1 (L)

DRV SEL 2 (L)

DRV SEL 3 (L)

RX2WPTLED (L) (RX50 only signal)

RXMOTORON (L) (RX50 only signal)

GROUND

DIRECTION (L)

GROUND

STEP (L)

GROUND

RXWRTDATA (L) (RX50 only signal)

GROUND

*Reserved for future use.

969

RQDX1/M8639
J1 Connector Signals (Cont)
J1 Pin

Signal Name

40
41
42

WRT GATE (L)
GROUND
TRACK 00 (L)

GROUND

47
48
49
50

GROUND

43
44

RX3WPTLED (L) (RX50 only signal)
DRVSL1ACK (L) (RD51 only signal)
READ DATA (L) (RX50 only signal)
HEAD SEL O (L)

GROUND
READY (L)

RD51 Disk Drive J1 Signal Connector Pin Assignments
GND Return
Pin

Signal
Pin

Signal
Name

Reserved

5
7
9
11

6
8
10
12

Write gate
Seek complete
Track O
Write fault

Head select 1

19
21
23

20
22
24

Index
Ready
Step

Direction in

13
15
17

25
27
29
31
33

Head select 2

Head select O
Reserved (to J2 pin 7)

14
16

Drive select 1
Drive select 2
Drive select 3
Drive select 4

26
28
30
32

970

RQDX1/M8639
RD51 Disk Drive J2 Signal Connector Pin Assignments

GND Return

Signal

Name

Drive selected

Reserved

Reserved (to J1 pin 16)

9, 10

Reserved

GND

+MFM write data

—MFM write data

GND

+MFM read data

—MFM read data

GND

RD51 Disk Drive J3 Power Connector Pin Assignments

GND Return

Signal

Name

+12 V
+5 V

971

RQDX1/M8639

RX50 Diskette Drive J1 Connector Pin Assignments
GND Return

Signal

Pir

Name

TK43L (controls write current level)

Drive select 3 L

9
11
13

10
12
14

17
19

18
20

22
24
26
28
30
32
34

21
23
25
27
29
31
33

Reserved
Index L

Drive select O L
Drive select 1 L
Drive select 2 L
Motor on L

Direction (head movement direction)
Step L (head movement distance)

Write data L
Write gate L
Track O L
Write protect L
Read data L
Reserved
Ready L

RX50 Diskette Drive J3 Power Connector Pin Assignments
GND Return
Pin

Signal
Pin

Signal
Name

2
3

1
4

+12 V
+5 V

972

RXV11/M7946

RXV11 FLOPPY DISK INTERFACE

Amps
+5
1.5 max.

Bus Loads
+12

1.74

Cables

BCO5L

Standard Addresses

First Device

Second Device

RXCS

177170

177150

RXDB

177172

Vector

264

177152
270

Diagnostic Programs

Refer to Appendix A.
NOTE

Run DZRXB before DZRXA.

Related Documentation

RXV11 User’s Manual (EK-RXV11-OP-001)
Field Maintenance Print Set (MP00024)
Microcomputer Interfaces Handbook (EB-20175-20)

973

RXV11/M7946

974

H3dWAPNON_:s#lJ;4AHOmL_O:sVQ3¢¥8_3:N>d9W1NIrNmOzNDO~wN—Wi;m‘_l::_;mfw_ifiow;df?l»m;.m_“;m_;Nv_fhHi_;wmffli4315193y1937135

$S340av

975

‘310N

OSitL
=Q8L0XLYLLVl=8DX%Y

~SS3uAgv
Ad0LloVvd

SPelW ITNC0OW

€180-4#H

4K #180-

SOXYH-=

530

3vQ0G1lAe3—0S1l19g'b6JLIWHN3:OTIN4TJ!ANOODW:@Ll1Y_ o_Y]]Y_]T@9i<2]_IAa(gI_SLT8I|_ILpT0)y<]_| H‘TiH“)]T=]_| I‘Ti {T1moXxm"]mo0
T=YT=sJaaddwwnnppppaajnoowisausl=1=100221106077@{T HOLOT3A$9J2T=O-150384AAYS8fJpYi T T T T

vaS$S34QavSle—Sli8

RXV11/M7946

juo2Q1:¥0X

saAlQ) ‘0 (1

s8AuQ) ‘0 (1

RXV11/M7946

976

RXV11/M7946
NOTES

When inserting the cable in the RXV11 interface module,
the red edge of the cable should be at the center of the
module (near the pin A end of J1).

BUS INIT ~ Install W18 to pass bus INIT to the RX0O1 as initialize.

]

ERROR

— TR|

NOT USED

DONE
INT

ENB

INIT

FUNCTION

UNIT

SEL

— GO|

000 FILL BUFFER
BUFFER

00t

EMPTY

010

WRITE

SECTOR

011

READ

SECTOR
USED

100

NOT

101

READ

110

WRITE
DATA

111

STATUS

DELETED
SECTOR

READ ERROR
REGISTER
CP-2248

Receiver Control/Status Register (RCSR)
Bit Definitions
Bit

Function

Go - Initiates a command to RX01. Write only.

1-3

Function Select - These bits code one of the eight possible

functions. Write only.

Unit Select - This bit selects one of the two possible disks for

execution of the desired function. Write only.

Done - This bit indicates the completion of a function. Done will

generate an interrupt when asserted if interrupt enable (RXCS

bit 8) is set. Read only.

Interrupt Enable - This bit is set by the program to enable an
interrupt when the RX01 has completed an operation (done).
The condition of this bit is normally determined at the time a
function is initiated. This bit is cleared by the LSI-11 bus initialize (BINIT L) signal, but it is not cleared by the RXV11 in-

itialize bit (RXCS bit 14). Read/write.

977

RXV11/M7946
Bit Definitions (Cont)
Bit

Function

Transfer Request - This bit signifies that the RXV11 needs data

8-13

Unused.

RXV11 Initialize - This bit is set by the program to initialize the
RXV 11 without initializing all of the devices on the LSI-11 bus.

or has data available. Read only.

Write only.

CAUTION

Loading the lower byte of the RXCS will also load the up-

per byte of the RXCS.
2.

Setting this bit (BIS instruction) will not clear the inter-

rupt enable bit (RXCS bit 06).

Upon setting this bit in the RXCS, the RXV11 will negate done
and move the head position mechanism of drive 1 (if two are
available) to track 0. Upon completion of a successful initialize,

the RX01 will zero the error and status register, set initialize
done, and set RXES bit 7 (DRV RDY) if unit O is ready. It will also
read sector 1 of track 1 and drive O.

Error - This bit is set by the RX01 to indicate that an error has
occurred during an attempt to execute a command. This read-

only bit is cleared by the initiation of a new command or by set-

ting the initialize bit. When an error is detected, the RXES is
automatically read into the RXDB.

The RXDB register serves as a general purpose data path between the
RX01 and the RXV 11 interface. It may represent one of five RX01 registers
according to the protocol of the command function in progress. The RX01
registers include RXDB, RXTA, RXSA, RXES, and RXER.

CAUTION

Violation of protocol in manipulation of this register may cause

permanent data loss. Refer to RXV 11 User’'s Manual.

978

RXV11/M7946
RXDB-RX Data Buffer — All information transferred to and from the floppy
media passes through this register and is addressable only under the protocol of the function in progress.
15

NOT

USED

[ TTTTTITTTITT
READ/WRITE

DATA
CP-2247

RXDB Format
RXTA-RX Track Address — This register is loaded to indicate on which of
the 114 tracks a given function is to operate. It can be addressed only un-

der the protocol of the function in progress. Bits 8 through 15 are unused
and are ignored by the control.
15

NOT USED

0-1144

CP 1810

RXTA Format

RXSA-RX Sector Address — This register is loaded to indicate on which of

the 32 sectors a given function is to operate. It can be addressed only under the protocol of the function in progress. Bits 8 through 15 are unused
and are ignored by the control.
i5

LD PP

Jefofe] P11
J

—

1-32,

NOT USED

CcP-15611

RXSA Format

RXES-RX Error and Status — This register contains the current error and

status conditions of the drive selected by bit 4 (unit select) of the RXCS.
This read-only register can be addressed only under the protocol of the
function in progress. The RXES is located in the RXDB upon completion of
a function.
15

07
DRV

RDY

NOT USED

PAR | CRC

NOT USED
MR-6313

RXES Format

979

RXV11/M7946
RXDB Bit Definitions
Bit

Function

check error was detected as
CRC Error - A cyclic redundancy
field of the diskette. The
data
a
from
information was received
ted.
RXES is moved to the RXDB, and error and done are asser
ted on command or on adParity Error - A parity error was detec
the RX01 from the LSI-11
to
d
ferre
trans
being
n
dress informatio
means that there is a
ation
bus interface. A parity error indic een the
RXO1 and the interbetw

problem in the interface cable
nt function is terface. Upon detection of a parity error, the curreand
the error and
RXDB,
the
to
d
move
is
RXES
minated: the
done are asserted.

RXES to indicate
Initialize Done - This bit is asserted in thecan
be caused by
which
,
routine
ize
initial
the
of
tion
comple
ammable or
progr
or
,
failure
power
m
RX01 power failure, syste
LSI-11 bus initialize.
Unused.

Deleted Data Detected - During data recovery, edtheas identia defication mark preceding the data field was decod
leted data mark.

ed
Drive Ready - This bit is asserted if the unit currentlye select
ed
exists, is properly supplied with power, has a diskett toinstall
speed.
up
e
diskett
a
has
and
closed,
correctly, has its door
NOTES

_ The drive ready bit is valid only when retrieved via a read
status function or at completion of initialize when it indicates status of drive O.

If the error bit was set in the RXCS but error bits are not set
in the RXES, then specific error conditions contained in the
RXER can be accessed from the RXDB via a read error register function.

RXER-RX Error — This register is located in the RX01 and contains specific

RX01 error information. This information is normally accessed when the
RXCS error bit 15 is set but RXES error bits 0 and 1 are not set. This is a

read-only register.

980

RXV11/M7946

NOT

USED
CP-2246

RXER Format

Octal Code | Error Code Meaning
0010

Drive O failed to see home on initialize.

0020

Drive 1 failed to see home on initialize.

0030

Found home when stepping out 10 tracks for INIT.

0040

Tried to access a track greater than 77.

0050

Home was found before desired track was reached.

0060

Self-diagnostic error.

0070

Desired sector could not be found after looking at 52 head-

ers (two revolutions).
0110

More than 40 microseconds and no SEP clock seen.

0120

A preamble could not be found.

0130

Preamble found but no I/O mark found within allowable time
span.

0140

CRC error on a header; no flag.

0150

The header track address of a good header does not com-

0160

Too many tries for an ID address mark.

pare with the desired track.

0170

Data mark not found in allotted time.

0200

CRC error on reading the sector from the disk. No code ap-

0210

Parity error on some word from interface.

pears in the ERREG.

981

RXV21/M8029

RXV21 FLOPPY DISK CONTROLLER

Bus Loads

Amps
+12

+5
1.8

AC
3.0

DC
1.0

Cables
BCO5L-15

Standard Addresses

RXCS
RXDB

First Controller

Second Controller

177170
177172

177200
177202

Standard Vectors
264

270

Diagnostic Programs

Refer to Appendix A.

Related Documentation

RXV21 Field Maintenance Print Set (MP00628)

RX02 Floppy Disk System User’s Guide (EK-RX02-UG)

RX01/RX02 Reference Card (EK-RX102-RC)

RX02 Technical Manual (EK-ORX02-TM)
Minicomputer Interfaces Handbook (EB-20175-20)
RX0?2 Field Maintenance Print Set (MP-00629-00)
CAUTION

PDP-11/23 systems require the M8029 to be at CS revision E1
or higher.

982

RXV21/M8029

BCO5L-15

CABLE CONNECTION

I“\W

O—0 A3
O—0
A12 O0—0 A4
O—0OV2 O—OA5
O
OV3 O—O0A6
OA7
O—0QV4 O

OA8
O—OV5 O
0OV6 O—OA9
O
V7 O—0 A10
O—0Q

0V8 O—0OAlI

]

{

MR-2373

M8029 Module Address and Vector Jumpers

983

RXV21/M8029
STANDARD ADDRESSES
!

177170

4
T

3
T

11
i

OTHER 177200

STANDARD VECTOR ADDRESS
14
15
264

]

13
|

5
1

{

OTHER 270

RX2BA

177172

STARTING MEMORY ADDRESS OF DATA

RXDB

177172

NQT USED

DATA BYTE

MR-5529

RXV21 Error Codes

Error Reg

Error Codes

1514131211109 8
DV

Track addr sel DV

SEL

DEN |HD | DEN
Dv1|LD|DVO

Target Sector

Target Track

Current Track DV1

Current Track DVO

Word Count Reg

Error Code

DEN

CMD

The following sequence is used to get definitive error information following
a bootstrap operation. (It is assumed that the bootstrap program has halted
and the CPU is in ODT.)

1. Examine R5 (RF will contain RXES after an error).
2.

Examine RXER by:

Loading the READ ERROR
(777 170/XXXXXX 17<CR>).

command

into

RX2CS

e Examining the four words of error information that will be transferred
into locations 2000, 2002, 2004, and 2006.

Reading and decoding this information using the format shown below. The error code can be used to help identify the failing FRU.

984

RXV21/M8029
15

RX
EXT
ool
abe
||

ERROR

HD
S
fee|te]

RX02

0OV

]| euncrion oo

INTR

ENB

U{]\HT
SEL

DONE
MR-2374

RX2CS Format RXV21
Bit Definitions

Bit

Function

Go - Initiates a command to RX02. Write only.

1-3

Function Select - These bits code one of the eight possible
functions described below. Write only.

Code

Function

000

Fill Buffer

001

Empty Buffer

010

Write Sector

011

Read Sector

100

Set Media Density

101

Read Status

110

Write Deleted Data Sector
Read Error Code

111

Unit Select - This bit selects one of the two possible disks for
execution of the desired function. This bit is readable only when
done is set, at which time it indicates the unit previously selected. Read/write.

Done - This bit indicates the completion of a function. Done will
generate an interrupt when asserted if interrupt enable (RX2CS
bit 8) is set. Read only.

Interrupt Enable - This bit is set by the program to enable an
interrupt when the RX02 has completed an operation (done).
The condition of this bit is normally determined at the time a
function is initiated. Read/write; cleared by initialize.

Transfer Request - This bit signifies that the RXV21 needs data

Density - This bit determines the density of the function to be
executed. This bit is readable only when done is set, at which
time it indicates the density of the function previously executed.

or has data available. Read only.

Read/write.

985

RXV21/M8029
Bit Definitions (Cont)

Function

Bit

for double-sided
Head Select - This bit selects one of two heads
At that time the side

operation, readable only when done is set.

that was previously selected is not valid.

Reserved for future use. Must be written as a O.

RX02 - This bit is set by the interface to inform the programmer

that this is an RX02 system. Read only.

12-13

Extended Address - These bits are used to declare an extend-

RXV21 Initialize - This bit is set by the program to initialize the

ed bus address. Write only.

RXV21 without initializing all devices on the UNIBUS. Write only.
CAUTION

Loading the lower byte of the RX2CS will also load the upper

byte of the RX2CS.

Upon setting this bit in the RX2CS, the RXV21 will negate done
and move the head position mechanism of both drives (if two
are available) to track 0. Upon completion of a successful initialize, the RX02 will zero the error and status register, and set
initialize done. It will also read sector 1 of track 1 on drive O into

the buffer.

Error - This bit is set by the RX02 to indicate that an error has

occurred during an attempt to execute a command. Read only;
cleared by the initiation of a new command or an initialize.
10

02 01

04 03

—

0-1144

NOT USED

MR-2375

RX2TA Format (RXV21)

RX2TA (RX Track Address) — This register is loaded to indicate on which
of the 1144 (0-76,) tracks a given function is to operate. It can be addressed only under the protocol of the function in progress. Bits 8-15 are
unused and are ignored by the control.

986

RXV21/M8029
15

Ll TP

“

—

NOT

Telelol TTTT]
)

USED

—

1-328
MR-2376

RX2SA Format (RXV21)
RX2SA (RX Sector Address) — This register is loaded to indicate on which
of the 32g (1-26,3) sectors a given function is to operate. It can be addressed only under the protocol of the function in progress.

MR-2377

RX2WC Format (RXV21)
RX2WC (RX Word Count Register) - For a double-density sector, the max-

imum word count is 128,5. For a single-density sector the maximum word
count is 64,4. If a word count is beyond the limit for the density indicated,

the control asserts word count overflow (bit 10 of RX2ES). This is a writeonly register. The actual word count, and not the 2’s complement of the

word count, is loaded into the register.

MR-2378

RX2BA and RX2DB Format (RXV21)

RX2BA (RX Bus Address Register) — This register specifies the bus address of data transferred during fill buffer, empty buffer, and read definitive
error operations. Incrementation takes place after a memory transaction
has occurred. The RX2BA, therefore, is loaded with the address of the first
data word to be transferred. This is a 16-bit, write-only register.

RX2DB (RX Data Buffer) — All information transferred to and from the floppy media passes through this register and is addressable only under the
protocol of the function in progress.

RX2DB (Data Buffer Register [177172]) — This register serves as a general purpose data path between the RX02 and the interface. It may represent

one of six RX02 registers according to the protocol of the function that is in
progress.

987

RXV21/M8029

process of executing a
This register is read/write if the RX02 is not in the affectin
g the RX02 subwithout
ated
manipul
be
may
it
is,
that
d:
comman
register will only
this
nd,
comma
a
ing
execut
y
system. If the RX02 is activel
can only be
data
valid
n,
additio
In
set.
is
(TR)
7
bit
RX2CS
if
data
accept
read when TR is set.

CAUTION

Violation of protocol in manipulation of the data buffer register
may cause permanent data loss.

DRV

DRV
UNIT

RDY

DEN

SEL

OVFL

L]RX

—
NXM
NOT USED

DEN
ERR

AC LO

CRC

iD
SIDE 1

RDY

SEL

MR-2379

RX2ES Format (RXV21)

RX2ES (RX Error and Status) — This register contains the current error and
status conditions of the drive selected by bit 4 (unit select) of the RX2CS.
This read-only register can be addressed only under the protocol of the
function in progress. The RX2ES is located in the RX2DB upon completion
of a function.

RXES bit assignments are as follows.
Bit Definitions

Bit

Function

CRC Error - A cyclic redundancy check error was detected as

information was retrieved from a data field of the diskette. The
data collected must be considered invalid. The RX2ES is moved
to the RX2DB, and error and done are asserted. It is suggested
that the data transfer be tried up to 10 times, as most errors are
recoverable (soft).

Side 1 Ready - This bit, when set, indicates that a double-sided

diskette is mounted in a double-sided drive and is ready to execute a function. This bit is valid only at the termination of an initialize sequence or a maintenance READ STATUS command.
988

RXV21/M8029
Bit Definitions (Cont)
Bit

Function

Initialize Done - This bit is asserted in the RX2ES to indicate
completion

of the

initialize

routine which

can be caused by

RX02 power failure, system power failure, or programmable or

bus initialize.

RX AC LO - This bit is set by the interface to indicate a power
failure in the RX02 subsystem.
Density Error - This bit indicates that the density of the function
in progress does not match the drive density. Upon detection of

this error the control terminates the operation and asserts error
and done.

Drive Density - This bit indicates the density of the diskefie’ in
the drive selected (indicated by bit 8). The density of the drive is
determined during read and write sector operations.
Deleted Data - This bit indicates that in the course of recovering data, the ‘“deleted data’’ address mark was detected at
the beginning of the data field. The DRV DEN bit indicates
whether the mark was a single- or double-density deleted data
address mark. The data following the mark will be collected and
transferred normally, as the deleted data mark has no further
significance other than to establish drive density. Any alteration
of files or actual deletion of data due to this mark must be accomplished by user software.

Drive Ready - This bit indicates that the selected drive is ready
if bit 7=1 and all conditions for disk operation are satisfied,

such as door closed, power OK, diskette up to speed, etc. The
RX02 may be presumed to be ready to perform any operation.
This bit is only valid when retrieved via a read status function or
initialize.

Unit Select - This bit indicates that drive O is selected if bit
8=0. This bit indicates the drive that is currently selected.
Head Select - This bit indicates which side of a double-sided
drive performed the last operation.
10

Word Count Overflow - This bit indicates that the word count is
beyond sector size. The fill or empty buffer operation is terminated and error and done are set.

Nonexistent Memory Error - This bit is set by the interface when
a DMA transfer is being performed and the memory address
specified in RX2BA is nonexistent.

989

RXV21/M8029
Function Codes

reFollowing the strict protocol of the individual function, data storage andand

covery on the RXV21 occur with careful manipulation of thebeRX2CS
permanent

RX2DB registers. The penalty for violation of protocol can

data loss.

A summary of the function codes is presented below.
000
001
010
011

Fill Buffer
Empty Buffer
Write Sector
Read Sector

101

Read Status

100

110
111

Set Media Density

Write Deleted Data Sector
Read Error Code

The following paragraphs describe in detail the programming protocol associated with each function encoded and written into RX2CS bits 1-3 if
done is set.

Fill Buffer (000) - This function is used to fill the RX02 data buffer with the
number of words of data specified by the RX2WC register. Fill buffer is a
complete function in itself: the function ends when RX2WC overflows, and if
necessary, the control has zero-filled the remainder of the buffer. The contents of the buffer may be written on the disk by means of a subsequent
WRITE SECTOR command or returned to the host processor by an EMPTY
BUFFER command. If the word count is too large, the function is terminated, error and done are asseried, and the word count overflow bit is set
in RX2ES.

To initiate this function the RX2CS is loaded with the function. Bit 4 of the
RX2CS (unit select) does not affect this function since no disk operation is
involved. Bit 8 (density) must be properly selected since this determines
the word count limit. When the command has been loaded, the done bit
(RX2CS bit 5) goes false. When the TR bit is asserted, the RX2WC may be
loaded into the data buffer register. When TR is again asserted, the RX2BA
may be loaded into the RX2DB. The data words are transferred directly from

memory and when RX2WC overflows and the control has zero-filled the remainder of the sector buffer, if necessary, done is asserted, ending the operation. If bit 8 RX2CS (interrupt enable) is set, an interrupt is initiated. Any
read of the RX2DB during the data transfer is ignored by the interface. After

done is true, the RX2ES is located in the RX2DB register.

Empty Buffer (001) - This function is used to empty the contents of the
internal buffer through the RXV21 for use by the host processor. This data
is in the buffer as the result of a previous FILL BUFFER or READ SECTOR
command.

990

RXV21/M8029
The programming protocol for this function is identical to that for the FILL
BUFFER command. The RX2CS is loaded with the command to initiate the

function. (This function will ignore bit 4 RX2CS, unit select.) RX2CS bit 8
(density) must be selected to allow the proper word count limit. When the

command has been loaded, the done bit (RX2CS bit 5) goes false. When
the TR bit is asserted, the RX2WC may be loaded into the RX2DB. When TR

is again asserted the RX2BA may be loaded into the RX2DB. The RXV21
assembles one word of data at a time and transfers it directly to memory.

Transfers occur until word count overflow, at which time the operation is
complete and done goes true. If bit

6 RX2CS (interrupt enable) is set, an

interrupt is initiated. After done is true, the RX2ES is located in the data
buffer register.

Write Sector (010) - This function is used to locate a desired sector on
the diskette and fill it with the contents of the internal buffer. The initiation

of the function clears RX2ES, TR, and done.
When TR is asserted, the program must load the desired sector address

into RX2DB, which will drop TR. When TR is again asserted, the program
must load the desired track address into the RX2DB, which will drop TR. TR
will remain unasserted while the RX02 attempts to locate the desired sector. The diskette density is determined at this time and is compared with

the function density. If the densities do not agree, the operation is terminated; bit 4 RX2ES is set, RX2ES is moved to the RX2DB, error (bit

RX2CS) is set, done is asserted, and an interrupt is initiated, if bit 6 RX2CS

(interrupt enable) is set.
If the densities agree but the RX02 is unable to locate the desired sector

within two diskette revolutions, the interface will abort the operation, move

the contents of RX2ES to the RX2DB, set error (bit 15 RX2CS), assert
done, and initiate an interrupt if bit 6 RX2CS (interrupt enable) is set.
If the desired sector has been reached and the densities agree, the RXV21
will write the 128,45 or 64,5 words stored in the internal buffer followed by a

CRC character which is automatically calculated by the RX02. The RXV21

ends the function by asserting done and, if bit 6 RX2CS (interrupt enable) is
set, initiating an interrupt.

CAUTION
The contents of the sector buffer are not valid data after a

power loss has been detected by the RX02. However, write
sector will be accepted as a valid instruction and the (random)

contents of the buffer will be written, followed by a valid CRC.
NOTE

The contents of the sector buffer are not destroyed during a
write sector operation.

991

RXV21/M8029

the desired sector and
Read Sector (011) - This function is used to locate
l buffer in the control.
interna
transfer the contents of the data field tove the
ms) the current status
(5
y
rapidl
retrie
to
used
be
also
This function may
RX2ES, TR, and
clears
on
functi
this
of
of the drive selected. The initiation
done.

load the desired sector address
When TR is asserted the program must
TR is again asserted, the proWhen
TR.
drop
into the RX2DB, which will
drop
gram must load the desired track address into the RX2DB, which will
TR.

attempts to locate the deTR and done will remain negated while the RX02
desired sector within two
the
sired sector. If the RX02 is unable to locate /RX21
1 will abort the operRXV21
the
,
reason
any
for
ions
diskette revolut
ts of the RX2ES
conten
the
move
,
ation, set done and error (bit 15 RX2CS)
to the RX2DB, and if bit 6 RX2CS (interrupt enable) is set, initiate an

inter-

rupt.

the data adIf the desired sector is successfully located, the control reads
If the diskette
dress mark and determines the density of the diskette. operati
on is ter(drive) density does not agree with the function density the
4 RX2ES is
minated and done and error (bit 15 RX2CS) are asserted. Bit
set (density error) and the RX2ES is moved to the RX2DB. If bit 6 RX2CS
(interrupt enable) is set, an interrupt is initiated.

s
If a legal data mark is successfully located, and the control and densitie
a
If
buffer.
internal
the
into
sector
the
from
data
read
will
control
the
agree,
RX2ES
6
bit
set
will
control
the
,
detected
deleted data address mark was
(DD). As data enters the internal buffer, a CRC is computed based on the
data field and the CRC bytes previously recorded. A nonzero residue indicates that a read error has occurred and the control sets bit 0 RX2ES
by
(CRC error) and bit 15 RX2CS (error). The RXV21 ends the operation bit
asserting done and moving the contents of the RX2ES into the RX2DB. If
6 RX2CS is set, an interrupt is initiated.

If the desired sector is successfully located, the densities agree and the
data is transferred with no CRC error; done will be set and if bit 6 RX2CS
(interrupt enable) is set, the RXV21 initiates an interrupt.

Set Media Density (100) - This function causes the entire diskette to be
reassigned to a new density. Bit 8 RX2CS (density) indicates the new density. The control reformats the diskette by writing new data address marks
(double or single density) and zeroing all of the data fields on the diskette.

992

RXV21/M8029
The function is initiated by loading the RX2CS with the command. Initiation
of the function clears RX2ES and done. When TR is set, an ASCH “I”’ (111)
must be loaded into the RX2DB to complete the protocol. This extra character is a safeguard against an error in loading the command. When the

control recognizes this character it begins executing the command.

The control starts at sector 1, track O and reads the header information,
then starts a write operation. If the header information is damaged, the control will abort the operation.

If the operation is successfully completed, done is set and if bit 6 RX2CS

(interrupt enable) is set, an interrupt is initiated.

CAUTION
This operation takes about 15 seconds and should not be in-

terrupted. If for any reason the operation is interrupted, an ille-

gal diskette will be generated which may have data marks of
both

densities.

This

diskette

should

completely

refor-

matted.

Maintenance Read Status (101) - This function is initiated by loading the

RX2CS with the command. Done is cleared. The drive ready bit (bit 7
RX2ES) is updated by counting index pulses in the control. The drive density is updated by loading the head of the selected drive and reading the
first data mark. The RX2ES is moved into the RX2DB. The RX2CS may be

sampled when done (bit 5 RX2CS) is again asserted and if bit RX2CS (interrupt enable) is set, an interrupt will occur. This operation requires approximately 250 ms to complete.

Write Sector with Deleted Data (110) - This operation is identical to func-

tion 010 (write sector) with the exception that a deleted data address mark
is written preceding the data rather than the standard data address mark.
The density bit associated with the function indicates whether a single- or
double-density deleted data address mark will be written.

Read Error Code (111) — The read error code function implies a read ex-

tended status. In addition to the specific error code, a dump of the control’s
internal scratch pad registers also occurs. This is the only way that the
word count register can be retrieved. This function is used to retrieve specific information as well as drive status information depending upon detection of the general error bit.

The transfer of the registers is a DMA transfer. The function is initiated by
loading the RX2CS with the command; then done goes false. When TR is
true, the RX2BA may be loaded into the RX2DB and TR goes false. The registers are assembled one word at a time and are then transferred directly to
memory.

993

RXV21/M8029
FOL|.OWING IS THE REGISTER PROTOCOL.

WORD COUNT REGISTER

WORD 2 |

CURRENT TRACK ADDR DRV 1

WORD 3 i

WORD 1 i

WORD 4 !

TARGET SECTOR
BAD TRACK

DEFINITIVE ERROR CODE

‘

CURRENT TRACK ADDR DRVO

TARGET TRACK

SOFT STATUS

MR-5527

Definitive Error Codes
10

Drive O failed to see home on initialize.

Drive 1 failed to see home on initialize.

Tried to access a track greater than 76.

Home was found before desired track was reached.

Desired sector could not be found after 52 tries.

110

More than 40 us and no SEP clock seen.

120

A preamble could not be found.

130

A preamble found but no ID mark found within allowable time.

150

The track address of a good header does not compare with desired track.

160

Too many tries for IDAM.

170

Data was not found in allotted time.

200

CRC on reading the sector from the disk.

220

Failed maintenance wraparound check.

230

Word count overflow.

994

RXV21/M8029
240

Density error.

250

Incorrect key word on SET DENSITY command.

Definitive error codes

Word 1<15:8>

Word count register

Word 2<7:0>

Current track address of drive O

Word 2<156:8>

Current track address of drive 1

Word 3<7:0>

Target track of current disk access

Word 3<15:8>

Target sector of current disk access

Word 4<7>

Unit select bit*

Word 4<5>

Head load bit*

Word 4<6><4>
Word 4<0>
Word 4<15:8>

Drive density bit of both drives”
Density of READ ERROR REGISTER command”*
Track address of selected drive**

RX02 Power Fail or Initialize

When the RX02 control senses a loss of power within the RX02, it will un-

load the head and abort all controller action. The RXAC L line is asserted to

indicate to the RXV21 that subsystem power has gone. The RXV21 asserts
done and error and sets the RXAC L bit in the RXZES.

When the RX02 senses the return of power, it will remove done and begin a

Move each drive head position mechanism to track O

sequence to:

Clear any active error bits

Read sector 1 of track 1, on drive O

Assert initialize done in the RXES.

Upon completion of the power-up sequence, done is again asserted. There
is no guarantee that information being written at the time of a power failure
will be retrievable; however, all other information on the diskette will remain
unaltered.

For DMA interfaces, the controller status soft register is sent to the
interface at the end of the command. The four status bits are included
in an 8-bit word. Unit select = bit 7; density of drive 1 = bit 6, head
load = bit 5; density of drive 0 = bit 4; density of READ ERROR REGISTER command = bit O.

The track address of the selected drive-error is only meaningful on a
code 150 error. The register contains the address of the cylinder that

the head reached on a seek error.

995

TSV05/M7196

TSV05 TAPE TRANSPORT AND BUS
INTERFACE/CONTROLLER

GENERAL

The TSVO05 tape transport subsystem provides magnetic tape storage capabilities
to computer systems using quad-sized LSI-11 bus backplanes. The subsystem
reads or writes up to 160,000 bytes per second in ANSI standard format. Data is
recorded by phase encoding 1600 bits per inch on nine-track tape. Reading and

writing are performed at either 25 or 100 inches per second.” The TSV05 subsystem is hardware compatible with 18- and 22-bit addressing versions of the LSI-11
bus quad backplane. It is software compatible with system and application programs written for the TS11 tape transport subsystem (as long as such programs

use the DIGITAL-supplied device handler). Tape formatting, error detection and

correction, and self-test diagnostics are included as integral components of the
TSV05 subsystem.

Voltage

+5 Vdc @ 6.5 A (max.)

Bus Loads
AC

3.0 (max.)

Standard Addresses

772520/772522

1st unit

772524772526

2nd unit

772530/772532
772534772536

4th unit

3rd unit

Vectors

224

1st unit

2nd unit

3rd unit

4th unit

100 IPS operating speed requires enabling special features and the appropriate software.

Rank of 37 in the floating vector area starting at 300.

996

TSV05/M7196
Diagnostic Programs

CVTSAA

Logic Test

CVTSBA

Advanced Logic Test

CVTSCA

Transport Test

CVTSDA

Advanced Transport Test

CVTSEA

Data Reliability Test

XTSAAQ

DEC-X11

Related Documentation

TSV05 Tape Transport Pocket Service Guide (EK-TSV05-PS)

Operation and Maintenance Instructions for Model F880 Tape
Transport (799816- 000*)
TSVO05 Tape Transport Subsystem Installation Manual (EK-TSV05-IN)

XXDP User Guide (AC-90931-MC)
TS05

Tape

Transport Operation and Acceptance Preventive Maintenance

Remove/Replace (EY-D3142-PS)

TSVO05 Field Print Set (MP-01157)
TSVO05 Subsystem Technical Manual (EK-TSV05-TM)
Microcomputers and Memories (EB-18451-20)

Microcomputer Interfaces Handbook (EB-17723-20)

TSV05 Hardware

TS05 tape transport
M7196 LSI-11 bus interface/controller module
H9642-series cabinet, including 874 power controller and remote power control

cable
Pair of 7016855 bus cables for connecting tape transport input and output to the
bus interface/controller module
The bus interface/controller module plugs into the LSI-11 bus. The two cables
connect the module with the tape transport.
Nominal, Vdc

Low Limit, Vdc

High Limit, Vdc

TSV05-BA

120

102

128

TSV05-BB

240

204

256

TSV05-BD

220

187

235

Electromagnetic Interference (EMI)

The TSV05 subsystem complies with FCC Part 15, Subpart J, Class A and is

designed to comply with VDE 0871 B requirements.

997

TSV05/M7196
NOTE

The TSVO05 subsystem has been designed and tested to meet DIGITAL

standards, including FCC requirements. The specifications in this
chapter are based on this testing. DIGITAL cannot guarantee the
TSV05 subsystem will meet these specifications if nontested equipment is installed into the TSV05 cabinet or the TSV05 cabinet is
installed in nontested configurations.

momtsos

()OO0
LOAD

UNLOAD ON LINE WRITE

ENTER

TEST

REWIND

- |
SGWER
MR-12856

Operator Front Panel

998

TSVO5/M7196
Controls and Indicators

Control/
Indicator

POWER

Type

Function

ON/OFF rocker switch
Switches line power ON and OFF.

and indicator

LOAD

Tactile switch and

REWIND

indicator

Blinks when the tape drive

executing

load

rewind

sequence.

Lit continuously when the beginning of tape (BOT) marker is

sensed.

Pressing the switch:

Initiates load sequence and
advances tape to load point.

Rewinds the tape to load
point.

UNLOAD

Tactile switch and
Pressing the switch causes the

indicator

tape to be unloaded regardless
of tape position.
Blinks when the tape drive is

executing an unload sequence.
Lit continuously when the tape

drive has completed its unload
sequence and the front access
door is unlocked. At this time,

the tape may be removed and
another tape inserted into the
drive.

Lit continuously after a successful power up, indicating a tape
may be loaded.

999

TSV05/M7196
Controls and Indicators (Cont)
Control/

Indicator

Type

Function

ON-LINE

Tactile switch and

1. Lit when drive is ready and on-

indicator

line.

Pressing the switch:

a. Takes the tape drive off-line
and extinguishes the
indicator.

Puts the tape drive on-line

and lights the indicators.

NOTE

Pressing the switch during a load sequence puts the tape drive on-line

when the BOT marker is sensed.

TEST

Operational only in the test mode.

Tactile switch

Selects alternative operational
mode for other switches.

WRITE

1. Lit when the write ring is

Indicator

installed and data may be writ-

ten on tape.

When indicator is off, write ring
is not installed and tape is file
protected.

ENTER

This control is used for manual

Tactile switch

loading and controlling the test
mode.

1000

TSV05/M7196

(

E122
THESE 14 ROMS ARE FACTORY

- INSTALLED AND SHOULD NOT
BE REMOVED.

w4
W5

VECTOR SWITCHPACK

ADDRESS

[‘Ti

SWITCHPACK

E109

MR-12857

VECTOR SWITCHPACK

| v7

| ve

| v6

| v3

| v2

ON
ve

| A12 | EB8

OFF

ADDRESS SWITCHPACK

| A8

| A7

| A5

| A4

| A3

] A0

A2 | ES7

OFF

V= VECTOR BIT
A = ADDRESS BIT

S1=BUFFERING
SO = EXTENDED FEATURES

JUMPERS

AS SHIPPED

BIRQ5

ouT

BIRQ6

ouT

w4
w5
w6

BIRQ7

ouT

BUS GRANT CONTINUITY
BUS GRANT CONTINUITY
SCLOCK ENABLE (USED DURING FACTORY REPAIR ONLY)

IN
IN
IN

MR-12948

M7196 Switch and Jumper ldentification

1001

TSV05/M7196

M7196 VECTOR AND ADDRESS SWITCHES

eleTe e elolo e ool To s Lol o Jresvia

‘ I ‘ ‘ l r r______; g’é

STANDARD VECTOR

OFF ON OTF OFIF 01‘\1 OFF ON OFF OFF

CONFIGURATION

(224)

SW|TCHI1lzlslalslel7lalgl1o

VECTOR

E58

STANDARD ADDRESS
CONFIGURATION

ADDRESS

(172520)

1213|456

I 9 [ 1OJ SWITCH

ES7

OFF

OFF OFF

(T T LT oL oL Lol oo [
15

S0 = EXTENDED FEATURES (MUST BE "ON"” FOR 22 BIT ADDRESSING)

S1 = BUFFERING ("ON" INCREASES THROUGHPUT BUT DATA WILL BE LOST IF POWER FAILS, NORMALLY
NOT USED)

MR-12858

M7196 Vector and Address Switches

1002

TSV05/M7196

TAPE TRANSPORT
UNIT SELECT

SWITCH

TERMINATOR*

TERMINATOR "

SOCKET

= ofI flufi‘nuflflmgu/5g :3=
S-00

poiogn 0By,

En
00

};

100 | o
300 (O

*NOTE: THE LAST (OR ONLY) TRANSPORT ON THE
BUS MUST HAVE THESE TWO DIP RESISTOR
PACKS INSTALLED. OTHER JUMPERS WITHIN
THE TRANSPORT ARE FACTORY-CONFIGURED

AND SHOULD NOT BE CHANGED. JUMPER
CONFIGURATION VARIES FROM BOARD TO
BOARD, DEPENDING ON THE EPROM TYPES IN
USE. HOWEVER, THIS DOES NOT AFFECT THE.
INTERCHANGEABILITY OF THE BOARD.

| o\ TMl FU UL

QW "o | L[]
MR-12859

TAPE TRANSPORT UNIT SELECT SWITCH

OFF

.
UNIT

220

33040

Utow

SEL

2
22

3300

usw
MR-129
o
45

Transport Switch and Terminator Identification

1003

TSV05/M7196

MODEL

RECEPTACLE

PLUG
SILVER

—# g8

TSVO5-BA | BRASS — &% ’G
NEMA #15-30P

DEC #12-11193

TSVO5-BB
p | BRASS 1

L5-30R

CIRCUIT RATING

120V

A
24

12-11194

V
220/240
220

ms_wen

NEMA #86-15P

DEC #90-08853

6-15R

12-11204
MR-12860

Power Line Connections

Power Cord Color Code

Pin connection

Color

Function

L5-30P

6-15P

Brown
Blue
Green/yellow

Hot
Neutral
Ground

Brass
Silver
Ground

Brass 1
Brass 2
Ground

1004

TSV05/M7196

S
M7196

INTERFACE/CONTROLLER
MODULE

N
TRANSPORT
BUS

NS
TS05

TAPE TRANSPORT

MR-12861

M7196 Interconnection

1005

TSV05/M7196
M7196 MODULE

1
L PIN

d
\_/)

L |

E 2
-

o~ LOW PROFILE

| —

CONNECTOR

RED STRIPE

MR-12862

Cabling the M7196 Module

TAPE TRANSPORT UNIT

| .

|I |

RED STRIPE

MR-12863

Cabling the Tape Transport

1006

VSV11/M7061,2,4

VSV11 RASTER GRAPHICS SYSTEM

GENERAL
The VSV11 raster graphics system is a basic Q-Bus system designed for color
graphics operation with LSI-11 hosts.

This

raster graphics module set is

installed

LSI-11

bus and a C-D

interconnect.
The first slot is reserved for either a CPU module or a connector which extends
the Q-Bus from another backplane. If slot 1 contains a CPU module, jumpers W1

and W3 must be removed in an H9273-A backplane used in a BA11-S mounting
box. Rows C and D carry the video bus signals of the VSV11 system. This is
modified for 22-bit bus addressing. (backplanes H9273 and H9276).
The basic module set includes:

N7061-YA SYNC generator module

M7062 image memory
M7064 display processor module

Power Requirements
1.

AC Power — The VSV11 system has one ac load, that being the M7064
(display process module), which is the only module in the VSV11 system that

communicates with the CPU.
2.

DC Power — To determine how many dc loads a VSV11 system has, count
the number of VSV11 modules (M7061, M7062, M7064) that reside on the LSI
bus. The total number is the number of dc loads. For example: a VSV11-AH
consists of:
1-M7061

2-M7062
1-M7064
4=dc loads

1007

VSV11/M7061,2,4
Module
M7061

M7062

M7064

5V @ 2.8A

12V @ 0.11 A

~5V* @ 0.006 A

+5V@1.7A
+12 V @ 0.45 A

+5V @ 6.0 A

Standard Device Address
767010
Vector

720 (octal)

Diagnostic Program

CVVSA?

Related Documentation

VSV11 Raster Graphics System User Guide (EK-VSVFQ-UG)

DW11 Installation Guide (EK-DW11A-INO)
VSV11 Field Maintenance Print Set (MP-01012)
VRVO02 Hitachi Monitor Maintenance Manual
VT101 Series Technical Manual (EK-VT101-TM)

*Supplied by M7061 module.

1008

VSV11/M7061,2,4
M7061-YA SYNC GENERATOR/CURSOR CONTROL BOARD
Jumpers and switches are configuration dependent and are located as shown.

R48

(=) )

—

M7061-YA

o Q
QO 9

Q QO
Q Q =&

Q ED

SET OPTIONS

[]

E21 SWITCH w1q

PACK

M7061-YA Switches and Jumpers

1009

MR-12872

VSV11/M7061,2,4

H9271-A

H9276
BACKPLANE

2
-

”L‘\.,\ LEFT OPEN FOR CPU OR M8401

?<Y —

=1 A I M7061-YA
1 \

M7062

) \ M7062

N AN\ M7062

| \ M7062

M7064

9
MR-12868

Module Placement Example, Four (Extended) Memory Systems

IN ONE MEMORY
SYSTEM,

OCCUPIES SLOT 3
ROWS C-F

!N TWO MEMORY

SYSTEMS,

OCCUPIES SLOT 4

LOCATING STRIPE

ROWS C-F

IN TWO MEMORY

SYSTEMS,

| OCCUPIES SLOT 3
| ROWS C-F

241 0CCUPIES SLOT 2
ROWS C-F
o

PROCESSOR

M7064

l/opPTiONAL

{ oND MEMORY | L

i M7062
-

OCCUPIES SLOT 1
ROWS C-F

15T MEMORY|
M7062

SYNC BOARD
M7061-YA

NOTE

IN SINGLE MEMORY

SYSTEM, THIS
CONNECTOR NOT
USED.
MR-12869

Intermodule Cabling Example, One or Two Memory Systems

1010

VSV11/M7061,2,4
M7061-YA Cable Connectors

The three cable connectors located on the M7061-YA module are:
J1 -

Accepts the drive board cable

J3 -

Accepts the driver board cable with the read stripe toward J4

J4 -

Accepts the beginning end of the daisy chain to memories and display
processor.

“THIS SIDE UP”

INTERCONNECT

CABLE

STRIPE

MOQUNTED IN

H349 BULKHEAD
FRAME

MR-12874

M7061-YA Interconnecting Cables

1011

VSV11/M7061,2,4
M7061-YA Switch Selections

Selection

Switch Setlings

60 Hz”
50 Hz

OFF
ON

Interlaced”
Noninterlaced
Special

OFF
ON
OFF

Normal Scan”
Special Scan

OFF
ON

Master”
Slave

ON
OFF

External Sync*t
internal Synct

ON
OFF

E21-2

E21-1

ON
OFF

E21-9

E21-3

ON
ON
OFF

E21-5

E21-4

ON
OFF

E21-6

E21-8

E21-7

OFF
ON

*These are factory settings.

tUse external sync when doing adjustments.

1012

E21-10

OFF
ON

VSV11/M7061,2,4
M7061-YA Jumper Selections

Selection

Jumper State
W19

Master*

Slave

ouT
W3

External Sync”

Internal Sync

ouT

Channel 0

OUT

OuUT

Channel 1

OUT

ouT

Channel 2

OUT

Channel 3

OUT

ouT

wi0

Wit

White Cursor*

Green and Blue Cursor

ouT

Green and Red Cursor

OuT

Green Cursor

ouT

ouUT

W16

W17

Small Cursor*

Large Cursor

ouT

OoUuT

W2o21

W22

16 Shades/Colors

8 Shades/Colors

OUT

ouT

“These are factory settings.

1013

VSV11/M7061,2,4

VSV11 Module M7061-YA - E21 Factory Switch Settings

Selection

E21 Switch No.

60 Hz~

OFF ON

50 Hz

OFF

laced

Special

OFF

Interlaced”
Noninter-

Customer

10 Selection

Norm Scan”
Special

Scan

OFF ON

OFF

Master”

Slave

OFF

External

Sync*

internal

Sync

*These are factory settings.

1014

ON OFF

OFF

OFF ON

VSV11/M7061,2,4
VSV11 Module M7061-YA Factory Set Jumper W - States
Jumper

Customer

Selecton

Master®

Slave

External

Sync*

Internal

Sync

Channel 0

Channel 1

Channel 2

Channel 3

White

Cursor*

Gr+B1
Cursor

GR+Rd

Cursor

Green

Cursor

Small
Cursor*

Large

Cursor
16 Colors”

8 Colors

*These are factory settings.

O = Out
I

=1In

1015

Selection

VSV11/M7061,2,4
M7062 MEMORY BOARD

ations. The numThe M7062 memory board is used in all VSV11 system configur
of memory
number
the
on
ing
ber of memory boards installed can vary dependor four memory modules can be
two,
One,
n.
uratio
config
ms
syste
the
modules in

present in a VSV11 system configuration. A three memory module system

does

not exist.

Switches and Jumpers
module, E59 and E49, which are
There are two switchpacks located on the M7062switch
es must be configured for
the data size and memory organization. These s configu
ration. Set the switch
system
a
in
t
presen
s
module
the number of memory

and jumpers as listed below.

NOTE

Cut pin 9 on resistor pack E77 on the first memory module only, in any
configuration including a one memory module configuration.

M7062

IMAGE CONTROL BUS

§4 TO BE CUT OFF

§ AT BODY \
P00
"

“fljnflm SWITCH PACK
10

ON1

—j OFF

Be775 | TERMINATOR flm
RESISTOR

SET NUMBER
OF MEMORIES

SET DATA SIZE
AND MEMORY

ORGANIZATION
(TABLE 2-3)

(TABLE 2-4)

WBW
w5

ON 1
OF

SWITCH PACK
E49

MR-12870

M7062 Memory Board

1016

VSV11/M7061,2,4
M7062 E49 and E59 Switch Settings* and
E76/77 Terminator Configuration
One Memory

Two Memories

Four Memories

Non-

interlaced

laced

Inter1st

2nd

Channel0 Channel
1
1st
2nd 3rd
4th

OFF

OUT

OuUT OFF

OFF

771

OuUT

OouUT OUT OUT

TRM

*Note that both switches are set identically.

tAlways remove and cut pin 9 and reinstall when IN.

1017

VSV11/M7061,2,4
M7062 Jumper Selections
Four Memories

W-

One Memory

Two Memories

Channel 0

Channel 1

ouT

1018

VSV11/M7061,2,4
M7064 DISPLAY PROCESSOR MODULE
The M7064 display processor module controls transactions between the control
logic and the LSI-11 bus logic. Switches on this module accommodate the host
system.

M7064

‘\
SET *
DEVICE

ADDRESS

SETS VECTOR

£43

BIT

109

3 45 6

SWITCH ot | bl

SLIDER

BIT

SWITCH
STATE

SLIDER
- ocKen

bl | 350

] ey

OFF OFF ON ON ON OFF ON OFF

E31

VECTOR | DEVICE ADDRESS

STATE OFF OFF OFF ON ON OFFON OFF | ppp.11

ROCKEH[

POP-11

179010

1110

9 10

STATE

ON OFF ON OFF OFF OFF OFF OFF OFF ON

SLIDER
et

ROCKER

SWITCH e

VAX

STATE
SLIDER

720

(OCTAL)

COCKER

gy I

(OCTAL)

767010

SWITCH

(OCTAL)

SWITCH L1 | Ny Wy (OCTAL)

]

[ =4

OFF ON ON ON OFF OFF OFF OFF OFF ON

SWITCH -

—
|

Tl T e

NOTE: TWO SWITCH TYPES MAY BE USED. BOTH HAVE THE SAME PART NUMBER.

MR-12871

Address and Vector Switch Settings for Module M7064

Install the sync generator module (M7061-YA) in slot 2 with either the CPU module
or an M9401 bus extender card occupying slot 1. Next, insert the M7062 memory
module(s) (up to 4). The last module to be inserted is the M7064 display processor
module, next to the last memory module.

1019

VSV11/M7061,2,4
VSV11 Module M7064 - Switch Settings

Vector

PDP-11

320

E43

VAX

E43

720

Setting
OFF

OFF

Selection

Pack

O~
O
WMo =

Factory

Octal

WK —

Switch

System

OFF

ON
ON

OFF

ON
OFF

OFF

E31

0O ~NOoO O
772010

PDP-11

&= WK

Device

OFF

OFF
ON

OFF

N
0
=t (O

OFF

1020

E31

OFF

ON
OFF
OFF

00~

OO O

767010

OFF

VAX

OFF

-t

Address

OFF

Customer

VSV11/M7061,2,4
Task Module 5 - Joystick

The joystick is used in this system to move and mark the cursor on the screen.
The equipment to be installed consists of the joystick itself, its cable, and an
extension cable as shown below.

JOYSTICK
EXTENSION CABLE
15M (50 FT)

CABLE 2.4M (8 FT)
JOYSTICK
ASSEMBLY

/ fl

/\/ERTICAL BALANCE ADJ
/

‘

/N
JOYSTICK

HORIZONTAL BALANCE ADJ

MR-12875

Joystick Components

1021

VSV11/M7061,2,4
CAUTION

Never connect the joystick to a system while power is on. To do this

can damage the M7061-YA Sync Gen/Cursor Ctrl module.

Shown below are the joystick and 4-conductor cable connections.
JOYSTICK

JOYSTICK

EXTENSION

/ CABLE

4-CONDUCTOR

MOUNTED IN

TMS

H349 BULKHEAD

FRAME

CABLE

Q’

VRVO2
MR-12876

Joystick Installation and 4-Conductor Cable Connection

1022

RC25

RC25 8-INCH DISK DRIVE SUBSYSTEM

GENERAL
The RC25 is a self-contained mass storage device that is used with a host to store

up to 52 million characters on two, hard, 8-inch disk platters.
One disk platter is fixed and the other is removable. Both platters are mounted on
the same spindle. The RC25 is available as a table top or rack mounted subsys-

tem. The two types of RC25 units are the master and the slave. The disks on the
master and slave units are interchangeable.
The master, containing the controller module, can drive two spindles (one master

and one slave), and must be the first drive in a subsystem.
Related Documentation

RC25 Disk Subsystem User Guide (EK-0RC25-UG)
RC25 Slave Disk Drive Customer Installation Guide (EK-RC25S-IN)
RC25 Disk Subsystem Installation Guide (EK-ORC25-IN)
RC25 Disk Subsystem Pocket Service Guide (EK-0RC25-PS)
llustrated Parts Breakdown (EK-ORC25-1P)

RC25 Field Maintenance Print Set (MP-01612-00)
MSCP Basic Disk Functions Manual (AA-L619A-TK)
Storage Systems UNIBUS Port Description (AA-L621A-TK)

1023

RC25

ADAPTER
MODULE

HOST COMPUTER

SYSTEM BUS

(UNIBUS, LSI-11)

DI
PP

| HOST COMPUTER SYSTEM__ __ _
!NTERFACE »

CABLE

RC25 DISK DRIVE
MR-12911

RC25 Disk Subsystem Components

1024

RC25

DIMENSIONS

CENTIMETERS

INCHES

A. HEIGHT

26.5

10.5

B. WIDTH

48.3

18.0

C. DEPTH

56.2

22.1
MR-12912

Space Planning for the Rack-Mount Unit

1025

RC25

”

MASTER RC25

DISK DRIVE

HOST

CONTAINS

SLAVE RC25
DISK DRIVE

DOES NOT

CONTAIN

CONTROLLER

’

PRI

SR,

INTERFACE

CABLE SET

MR-12913

RC25 Master and Slave Disk Drives

1026

RC25

EXHAUST
AIR QUT

COOLING
AIR IN

DIMENSIONS
A.

CENTIMETERS

INCHES

25.6

10.1

HEIGHT

B. WIDTH

25.4

10.0

C. DEPTH

52.1

20.5
MR-12914

Space Planning for the Tabletop Unit

1027

RC25

o(=)0
Jo ==
e
INTERFACE CONNECTORS

EXHAUST
AIR VENT

BACK VIEW

VOLTAGE
SELECTOR
SWITCH
CIRCUIT
BREAKER
MR-12915

Voltage Selector Switch and ON/OFF Circuit Breaker

1028

RC25
SPECIFICATIONS
The following list names the primary performance, power, environmental, and

physical characteristics of the RC25.

Size
Tabletop model

Height

25.6 cm (10-1/8 in)

Width (master or slave)

25.4 cm (10 in)

Depth

52.1 cm (20-1/2 in)

Rackmount model

Height

26.5 cm (10-1/2 in)

Width

48.3 cm (19 in) centers

Depth

56.2 cm (22-1/8 in)

Weight

Tabletop model

22.7 kg (50 Ib)

Rackmount model

Single disk

29.5 kg (65 Ib)

Dual disk

54.4 kg (120 Ib)

Environment
Temperature

Operating

10°-40°C (50°-104°F) ambient with a gradi-

ent of 10°C (18°F)/hr
Nonoperating

~40°-66°C (—40°-151° F) ambient with a

(storage/shipping)

gradient of 20°C (36°F)/hr

Relative humidity

10% - 90% with maximum wet bulb temperature of 28°C (82°F) and a minimum dew
point of 2°C (36°F) with no condensation

Operating

Nonoperating

5% - 95% with no condensation

(storage/shipping)
Altitude

Operating

Sea level to 2.4 km (8000 ft)

Maximum operating temperatures decrease

by a factor of 1.8°C/1000-(1°F/1000 ft) for
operation above sea level.
Nonoperating

(storage/shipping)

Up to 9.1 km (30,000 ft) above sea level
(actual or effective by means of cabin
pressurization)

1029

RC25
Shock

5 g peak at 7-13 ms duration in three axes

mutually perpendicular (maximum)

Heat Dissipation
Single disk drive
Dual disk drive

1091 Btu/h

Noise level (single disk)

53dBat1m

Electrical

Voltage/frequency

(single phase)

1828 Btu/h

90-128 Vac, 6.6 A, 47-63 Hz
180-256 Vac, 3.5 A, 47-63 Hz

Power (operating)
Single disk

320 W

Dual disk

536 W

Line cord length

1.83 m (6 ft)

(from enclosure)
Plug type

120 Vac

NEMA 5-15P

220-240 Vac

NEMA 6-15P

Data Capacity (Formatted)
Single disk drive

26.061824 Mb fixed disk

26.061824 Mb removable cartridge disk
52.123648 Mb total

(50,902 512-byte blocks/platter)
Dual disk drive

52.123648 Mb fixed disk

52.123648 Mb removable cartridge disks
104.247296 MbD total

(101,804 512-byte blocks/platter)
Media
Fixed

Removable

One 20 cm (7-7/8 in) double-sided nonremovable disk platter per drive

One 20 cm (7-7/8 in) double-sided disk platter in cartridge per drive

Seek Time
Average seek

35 ms maximum

One track seek

10 ms maximum

Maximum seek

55 ms maximum

1030

RC25
Latency

Speed

2850 r/min + 9 r/min

Average rotational latency

10.5 ms

Maximum rotational latency

21.0 ms

Average access

45.5 ms (overlapped seeks with double disk

drive configuration)
Data Rates
Average long transfer rate

0.57 Mb/sec typical

Spiral Read time
Per track

31 ms typical

Per disk

50 s typical

Per drive

1 min, 40 s typical

Start/Stop Time
60 sec maximum (includes purge and self-

Start time

test time)

30 sec maximum

Stop time

Safety precautions are listed with the following agencies.

Underwriter Laboratories

CSA

Canadian Standards Association

VDE

Verband Deutscher Electrotechniker (German Electrical Engineering Society)

IEC

International Electrotechnical Commission

1031

RC25
indicator States and Their Meaning
Write Protect

Eject Meaning

Run

Removable Fixed Fault

OFF

flash*

OFF

—

OFF

Slow

The drive is not running and the car-

tridge receiver door is unlocked.

The disk platters are spinning up or
down.

The drive is ready to accept

commands.

The removable disk cartridge is write

enabled.

The removable disk cartridge is in the
read-only state. Writing is prevented.

The fixed disk platter is write

enabled.

The fixed disk platter is in the read-

only state. Writing is prevented.

The drive has detected a failure.

Press FAULT briefly and refer to the
fault codes in Chapter 5 to determine
what went wrong.

slow

The drive is in maintenance mode

flash*

and is running a test.

*Slow flash is once per second.

1032

RC25

CONTROLLER
FAIL

INDICATOR
E

(MASTER DRIVE

ONLY)

dlilgliltlall
RECEIVER

Run

INDICATOR

Removable Fixed

1 11

Unit Select

POWER OK

_GREEN-—

[RC20
Write Protect

gf‘S[T(TRIDGE__ i

[

000/001

Fault

Eject

]

OPERATOR
PANEL
MR-12816

RC25 Front View Showing Operator Panel

Cartridge Loading

The RC25 is designed to make correct loading easy. To load the cartridge disk,
hold it label (writing) side up with the tapered end toward you. The opposite end

has a small trap door through which the read/write heads enter. This end enters
the cartridge receiver first.

if the cartridge receiver door is not open, press the EJECT button. The door opens

and swings down. Slide the cartridge straight in with a firm push until it locks into
place. Close the receiver door firmly by swinging it back up and latching it into
place.

Cartridge Unloading

Unloading the cartridge is as simple as loading. With the spindle stopped and the
receiver door unlocked (EJECT indicator on), press the EJECT button. The door

opens and the cartridge disk ejects. Once the door is open, grasp the cartridge
and pull it straight out of the receiver.
NOTE

Keep the cartridge receiver door closed when not in use to prevent

atmospheric contaminants from entering the disk enclosure.

1033

RC25

Inserting the Disk Cartridge

1034

RC25
Disk Operating Procedures
The procedures in this section are for starting and stopping the RC25.

Starting Procedure
Operator Action

Disk Drive Response

None.

Initial state of disk drive:
RUN button is released (out).

RUN indicator is off.

EJECT indicator is on.
Spindle is stoppled

Press EJECT.

Cartridge receiver door opens and disk cartridge partially ejects.

Reload cartridge or

replace with new cartridge.

None.

Close cartridge receiver

door.
Set WRITE PROTECT buttons.

None.
Corresponding WRITE PROTECT indicator
lights or goes off.

Press RUN in to lock it in.

Receiver door locks.

EJECT indicator goes off.
RUN indicator flashes slowly.

Disk platters spin up.
RUN indicator lights continuously.

Disk is ready for operation.

NOTE

A disk cartridge must be installed to spin up and operate the disk

drive. The fixed disk does not spin up and run without a removable

cartridge in place. The spin-up cycle takes approximately 1 minute. It
involves spinning the disk platters up to operating speed, cleaning the

internal air system, loading the read/write heads, and performing a
self-test.

1035

RC25
Stopping Procedure
Operator Action

Disk Drive Response

None.

Initial state of disk drive:
RUN button is pressed in.
Disk platters are spinning.
RUN indicator is on.

EJECT indicator is off.

Press RUN in to release it.

RUN indicator flashed slowly.
Disk platters slow down.

When disk platters stop spinning:
RUN indicator goes off.
EJECT indicator lights.
Receiver door unlocks.
Press EJECT.

Receiver door opens partially. Push down

door to eject cartridge fully.

Remove disk cartridge.
Close receiver door.

CAUTION

Do not try to open the receiver door until the EJECT indicator lights
and the EJECT button is pressed; you can damage the disk drive and
cartridge.

1036

RC25
Unit Select Number
The host computer system (or computer network) locates a peripheral device via a

unit select number. The RC25 can have any number pair from 0/1 to 252/253. It
has a pair of humbers because both disk platters have a unique number. The
removable disk platter always has an even number and the fixed disk platter

always has an odd number. The unit select number is chosen during installation,

but may be changed any time thereafter.

The unit select number is determined by a factory wired plug. This plug can be

removed and replaced to change the number. However, the RC25 cannot function
without a plug in place. The result is a fault indication. Two disk drives with the
same unit select number also cause a fault.

Change the unit select number plug by grasping the plug handle and pulling it
straight out of the operator panel. Install the new number plug by pushing it
straight into the empty, recessed socket. When installing the new plug, be sure to
hold it so the numbers are right side up. Do not try to force an upside down plug

into the socket. This mistake creates a false number and destroys the electronic
components inside the operator panel.

MR-12918

Changing the Unit Select Number Plug

1037

RC25
HOW TO MODIFY THE UNIT SELECT NUMBER PLUG

If you want to use a unit select number pair of 8/9 or higher for your RC25, you

must open and modify the unit select number plug. The procedure in this appendix
shows you how to make the modification.

1.
2.

Remove the plug on the operator panel by grasping the plug handle and

pulling it straight out.

The plug contains a small, eight-position DIP switch. Remove this switch from

the handle by spreading apart the two plastic retaining tabs and pulling
straight out.

When working with the switch, hold it so the number 1 position is on the left,
as shown below.

MR-12919

Unit Select Number Switch

Find the number pair you want and set the seven switches as indicated.
Three different types of switches are used in the RC25: one slide switch and
two types of rocket switches. It is important to identify which type of switch
your drive has before trying to change the number. To change the number
with a slide switch, push the switch tab to OFF or ON (up or down) as
indicated in the table. To change the number with a rocket switch, press in on
the corresponding side of the switch.

After setting the new number, press the DIP switch back into the plug handle

and insert the plug back into the operator panel.

1038

RC25
Unit Select Number Switch Settings

Unit
Number

DIP Switch Position Number
1

0/1

2(3

OFF

4/5

OFF

6/7

OFF

8/9

OFF

10/11

OFF

12/13

OFF

14/15

OFF

16/17

OFF

18/19

OFF

20/21

OFF

22/23

OFF

24/25

OFF

26/27

OFF

28/29

OFF

30/31

OFF

32/33

OFF

34/35

OFF

36/37

OFF

38/39

OFF

40/41

OFF

42/43

OFF

44/45

OFF

46/47

OFF

48/49

OFF

50/51

OFF

52/53

OFF

54/55

OFF

56/57

OFF

58/59

OFF

60/61

OFF

62/63

OFF

OFF
ON

64/65

OFF

66/67

OFF

68/69

OFF

1039

RC25

Unit Select Number Switch Settings (Cont)
DIP Switch Position Number

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

ON
ON
ON
ON

OFF
OFF
OFF
OFF

ON
ON
ON
ON

OFF
OFF
OFF
OFF

OFF

ON
ON
ON
ON
OFF

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF

90/91
92/93
94/95
96/97
98/99

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
OFF
OFF

OFF
OFF
OFF
ON
ON

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

100/101
102/103
104/105
106/107
108/109

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

110/111
112/113
114/115
116/117
118/119

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
ON
ON

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

120/121
122/123
124/125
126/127
128/129

ON
ON
ON
ON
OFF

OFF
OFF
OFF
OFF
ON

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

130/131
132/133
134/135

OFF
OFF
OFF

ON
ON
ON

ON
OFF
OFF

OFF
ON
OFF

Unit

Number

70/71
7273
7475
76/77
78/79

ON
ON
ON
ON
ON

80/81
82/83
84/85
86/87

88/89

136/137
138/139

OFF
OFF

OFF

ON
ON

1040

OFF
OFF

ON
ON

ON
OFF

RC25
Unit Select Number Switch Settings (Cont)

Unit

DIP Switch Position Number

Number

140/141

OFF

142/143

OFF

144/145

OFF

146/147

OFF

148/149

OFF

150/151
152/153
154/155
156/157
158/159

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

160/161
162/163
164/165
166/167

OFF
OFF
OFF

OFF
OFF
OFF
OFF

ON
ON
ON

OFF

ON
OFF

ON
OFF
ON
OFF

ON
ON

ON
ON
OFF
OFF

168/169

OFF
OFF

ON
ON
ON
ON

170/171
172/173
174/175
176/177
178/179

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
OFF
OFF

OFF
OFF
OFF
ON
ON

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

180/181
182/183
184/185
186/187
188/189

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

190/191
192/193
194/195
196/197

OFF
OFF
OFF
OFF

ON
OFF
OFF
OFF

OFF
ON
ON
ON

OFF
ON
ON
OFF

OFF
ON
OFF
ON

OFF

OFF
ON
ON
ON
ON

200/201
202/103
204/205
206/207
208/209

OFF
OFF
OFF
OFF

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
ON
ON
ON
OFF

OFF
OFF
OFF
OFF
ON

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

198/199

OFF

1041

OFF

RC25
Unit Select Number Switch Settings (Cont)
DIP Switch Position Number

Number

210/211
212/213
214/215
216/217
218/219

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
OFF
OFF

ON
OFF
OFF
ON
ON

OFF
ON
OFF
ON
OFF

220/221
222/223
224/225
226/227
228/229

OFF
OFF
OFF
OFF
OFF

ON
ON
OFF
OFF
OFF

OFF
OFF
ON
ON
ON

OFF
OFF
ON
ON
OFF

ON
OFF
ON
OFF
ON

230/231
232/233
234/235
236/237
238/239

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
ON

ON
OFF
OFF
OFF
OFF

OFF
ON
ON
OFF
OFF

OFF
ON
OFF
ON
OFF

240/241
242/243
244245
246/247
248/249

OFF
OFF
OFF
OFF
OFF

ON
ON
ON
ON
OFF

ON
ON
OFF
OFF
ON

ON
OFF
ON
OFF
ON

250/251
252/253
ILLEGAL

OFF
OFF
OFF

ON
OFF
OFF

OFF
ON
OFF

Unit

1042

RD51

RD51 11 Mb WINCHESTER DISK DRIVE SUBSYSTEM

GENERAL
The RDb51

fixed Winchester single element disk subsystem, found inside the

MICRO/PDP-11

and the MICRO VAX, can be attached to an existing 22-bit

MICRO, MICRO VAX, or a PDP-11/23 PLUS system.
The RD51 controller interface is used for both the RD51 and the RX50 disk and

diskette drives.
Related Documentation

MICRO/PDP-11 Technical Manual (EK-OLCP5-TM)

MICRO/PDP-11 Owner’s Manual (EK-OLCP5-OM)
MICRO/PDP-11 Unpacking and Installation (EK-OLCP5-IN)
RQDX1 Controller Module User Guide (EK-OLCP5-UG)

MICRO/PDP-11 System Option Manual (EK-OLCP5-0D)
H9302 Rack Mount Adapter Kit Instruction Manual (EK-LEPO3-IN)

RD51 Subsystem Component Specification
Unit Storage Capacity

11 megabytes (formatted data) 18 sectors
Power Supply Assembly
Inputs

Switchable line voltage

100-120 Vac (normal)
200-240 Vac (normal)

Line frequency

Line current

47-63 Hz either input range

120 Vac @ 2 A RMS (max)
240 Vac @ 1 A RMS (max)

Output

Power

65 watts (max)

DC Voltage

+12A Vdc +5% 1 A min. (4.5 A max.)
+12B Vdc +10% .12 A (max.)

+5 Vdc +5% @ .3 A min to 2 A (max.)

1043

RD51
Dimension

12 in long

g in wide

3 1/2 in high

14 |bs

Weight

switch ONJOFF (1 or 0) rocker switch — connects ac power to the subassemblie

Controls and Indicators

internal dc power supply.

Front Panel LEDs

Lit

Not lit

Top Green LED

RD51 ready

RD51 not ready

Middle Green LED

DC power present

DC power not present

Amber LED

RD51 write protect

RD51 not write protected
LED RD51 DRIVE
READY

LED + 5V

]

RDS!

pod

o Tal[tlal]

RD51 DRIVE

AC POWER
SWITCH

J‘l..f‘U‘L.HH"*L hfL.L"J"L.L_ L_____:J

LED SWITCH
WRITE-PROTECT

MR-13097

Front Panel, Switches and Indicators

1044

RD51
Rear Panel Connectors
J1 - DUO

J2 - DUA
J3 - DU2
Inside the BA23 system chassis (MICRO/PDP-11 and MICRO VAX 1) an RQDXi1
drive controller, RQDX1-E extender module and cables are used. (Cabinet kit CK-

RQDX1-KA)

PRIMARY VOLTAGE

SELECT SWITCH
120/240

CIRCUIT BREAKER
AC LINE

!
L
1

L
I

I
!

[

J
'IL

i
H

]
;J

{

J1|

O ewsnsssss°s) o

32|

o(wessssssas)o

33|

o\&wwasssessss)o

]

PRIMARY VOLTAGE
INPUT
MR-13099

Rear Panel Assembly

1045

RD51

VARIOUS CONFIGURATIONS FOR EXPANSION OF THE RD51
PATCH AND FILTER
PANEL ASSEMBLY
BACKPLANE

RQDX1

EXTERNAL CABLE

RD51

| I

CABINET KIT CABLE

(30" FOR H349 ENCLOSURE) ||
CK-RQDXI-KC

274 M

(9 FT)

MR-12184

Single Expansion Configuration

PATCH AND FILTER
PANEL ASSEMBLY
RX50

BACKPLANE

RD51

SUBSYSTEM

INTERCONNECT

CABLE BC17Y-1J

RQDX1
L

EXTERNAL CABLE

1|l
L
|

RD51

CABINET KIT CABLE

(30" FOR H349 ENCLOSURE}|__]

CK-RQDXI-KC

MR-12187

Double Expansion Configuration

1046

RD51

INBOARD

SIGNAL
DISTRIBUTION

BULKHEAD

BOARD

DRIVES

RQDX1

RX50
bt

INTERNAL

CK-RQDXI-KA
RD51

CABLE

BUS

CK-RQDXI-KA

EXTERNAL
|

CABLE

RD51

EXTENDER

1l |
4

HII

RQDXL;/’

|A4

MR.12188

Maximum Expansion Configuration

1047

RD51
J1, J2 and J3 Pin Numbers and Signal Names

ng.

Connectors J1, J2, and J3 have identical signal names and pin numberi

Pin No.

Signal Name

Pin No.

Signal Name

J1-01
J1-34
J1-18
J1-02
J1-35
J1-19
J1-03
J1-36
J1-20

MEMWRTDT1 (H)
MEMWRTDT1 (L)
GROUND
HEAD SET 2 (L)
GROUND
SEEKOPLT
RD1 RDY (H)
WPT FAULT (L)
GROUND

Ji-42
J1-26
J1-10
J1-43
J1-27
Ji-11
J1-44
J1-28
J1-12

INDEX (L)
RD1WRTPRAQ (L)
DRV SEL 1 (L)
DRV SEL 2 (L)
DRV SEL 3 (L)
RX2WPTLED (L)
RXMOTORON (L)
GROUND
DIRECTION (L)

J1-40
J1-24
J1-08
J1-41
J1-25
J1-09

MFMRDDAT1 (L)
GROUND
RFDUCWRTI (L)
RDOWRTPRO (L)
DRV SEL 4 (L)
GROUND

J1-32
J1-16
J1-49
J1-33
J1-17
J1-50

GROUND
READ DATA (L)
GROUND
HEAD SEL 0 (L)
GROUND
READY (L)

J1-04
J1-37
J1-21
J1-05
J1-38
J1-22
J1-06
J1-39
J1-23
J1-07

READ SEL 1 (L)
RXOWPTLED (L)
RDO RDY (H)
RX1WPTLED (L)
DRVSLOACK (L)
MEMRDDATO (H)
MFMRDDATO (L)
MFMWRTDTO (H)
MFMWRTDTO (L)
MFMRDDAT1 (H)

J1-45
J1-29
J1-13
J1-46
J1-30
J1-14
J1-47
J1-31
J1-15
J1-48

1048

GROUND
STEP (L)
GROUND
RXWRTDATA (L)
GROUND
WRT GATE (L)
GROUND
TRACK 00 (L)
RX3WPTLED (L)
DRVSL1ACK (L)

RD51
Power Supply Connectors
AC Power Input Connector

Pin No.

Signal

Ground

ac phase

ac neutral

DC Power Output Connector

Signal

+5V
+5V
+5V
Return

Return
Return
Return

12 VA

12 VB

12 VA
No pin

b
b
b

CONOOOUI
b WN =

Pin No.

No connection

1049

RD51
Logical Unit Number Selection

jumpers on the RQDX1 Controller
The logical unit number (LUN) selection is set by
assigned to any RD51 or RX50
LUN
lowest
the
to
set
are
module. These jumpers
module automaticaldrive subsystem that is controlled by the RQDX1. The RQDX1
of the system to deterly senses the logical unit configuration during initialization

mine how many of the four possible units are actually present.

at a time, and each
The LUN jumper format allows only one jumper to be installed
follows.
individual jumper specified a group of four logical units as
LUN Jumper

LUNs Specified

No jumper installed
1
2
3
4
5
6

0-3
4-7
8-1
12-15
16-19
20-23
24-27
28-31
32-35

7
8

Within the context of RQDX1 configurations as shown below, if number 4 jumper is
connected and using configuration number 2, then:
16 = unit 0
17 = unit 1

18 = unit 2
19 = unit 3

External subsystem

Logical numbers

for disk drives

Configuration

disk drives

One RD51, one RX50

Two RX50s

Two RD51s, one RX50

Two RD51s

Unit 0 = RD51

One RX50

Units 0, 1 = RX50

Unit 0 = RD51

Units 1, 2 = RX50

Units 0, 1 = RX50

Units 2, 3 = RX50

Unit 0 = RD51
Unit 1 = RD51
Units 2, 3 = RX50

Unit 1 = RD51

1050

RDS1
Expansion

MICRO/PDP-11 and MICRO VAX | systems contain inboard RD51-A and RX50-AA
drives and both systems are housed in BA23 enclosures. Each system also contains an RQDX1 controller. The controller has a capacity of four LUNs, three of
which are used internally. Thus, only one RD51 drive can be added externally to

the MICRO/PDP-11 and MICRO VAX I.
A BA23 enclosure (MICRO/PDP-11 and MICRO VAX 1) prior to any add-on RD51,
contains:

1 RQDX1 controller

1 CK-RQDX1-KA cabinet kit
1 RD51-A (drive only)
1 RX50-AA (drive only)

To accommodate an external add-on drive, an RQDX1-E bus extender and cable
must be added internally and connected to the patch and filter panel assembly.

A PDP-11/23 PLUS system, to accommodate external add-on drives, requires
internally an RQDX1 controller and a cabinet key cable CK-RQDX1-KC connected
to the H349 distribution panel.

REMOVABLE

INSERT

50-PIN CONNECTOR
EXPANSION SLOTS
MR-9529

BA23 Patch and Filter Panel Assembly

1051

RD51

DRV11

Dzvi1

(SYNC LINE INTERFACE)

LINEINTERFACE

{]

_________ 0

——————————————————

J13

—

——d

J10

J14

——

—————————

DZV11

—

DZV11

PARALLEL

DRV11-J

J12

CDl
—————DZV11

J15
———DZVI11

DLV11-J
MR-7378

PDP-11/23 PLUS/H349 Distribution Panel (Bulkhead)

1062

RD52

RD52 31 Mb WINCHESTER DISK DRIVE SUBSYSTEM

GENERAL

The RD52 fixed disk drive uses an RQDX1 controller and contains three nonremovable 5-1/4 inch disks as storage media. The three 5-1/4 inch disks can store
up to 31 megabytes of formatted data.

The interface between the disk drive and the host controller consists of four
connections:

11 - Control Signals
12 - Read/Write Signals
13 - DC power
14 - Frame ground

RD52 CONNECTOR LOCATIONS

J1 — CONTROL SIGNALS
J2 — READ/WRITE SIGNALS
J3 — DC POWER

J4 — FRAME GROUND

PIN
1
MR-12349

RD52 Connector Locations

1053

RD52
Power Requirement

+5 Vdc +5% @ 1.0 A

+12 Vdc +5% @ 2.5 A (4.5 A max.)

VOLTAG

MAX

Typ

MAX

TYP

ING

MAX

15AMP | 1AMP | 1.5AMP|

+12

45AMP | 3.8AMP|

TYP

MAX

STEADY | STEADY | RIPPLE

oTART | sTarT | SEEK- | SEEK

STATE | STATE | P-P

1AMP | 1.5AMP | TAMP | 50mV

3AMP | 25 AMP | 2AMP | 1.5 AMP | 50 mV

CURRENT REQUIRMENTS

6fi—

MAXIMUM

TYPICAL

4 4~
AMPS
3-—-—-—

2“_
0

—————————+———————+—
10

TIME (SEC)

+12V STARTING CURRENT
MR-12938

+12 V Starting Current

Related Documentation

RD52-D,R Disk Drive Subsystem Owners Manual (EK-LEP03-OM)
Physical Size

Height - 3.25 in
Width - 56.75 in

Depth - 8.0 in
Weight - 14 Ibs

1054

RD52
Connectors

J1 - 34 pin - control signal
J2 - 20 pin +12 Vdc data signals
J3 - 4 pin +5 Vdc dc power
J4 - single log - frame ground

TERMINATOR

+5V

RESISTOR PACK

RETURN

;;%RN

DRIVE SELECT
JUMPERS

4321R

srases
MR-12937

RD52 Power Connector (J3)

CAUTION

Damage will occur to the drive if the +5 V and +12 V connections are
reversed.

CAUTION:

DAMAGE WILL OCCUR TO THE DRIVE IF THE +5V AND +12V

CONNECTIONS ARE REVERSED.

+12V

+5V

+12V

RET

[

[
1

+5V

J3
—

NOTE:

THIS IS THE DRIVE END OF THE CONNECTOR

Selectable Address Internal

NOTE

This is the drive end of the connector.

1055

MR-12939

RD52
Environmental Limits

Operating temperature

Non operating temperature

Operating humidity
Non operating humidity
Maximum wet bulb
Thermal gradient
Operating altitude
Operating vibration
Non operating shock

10°to 50° C

—40° to 60° C

10% to 80%
5% to 95%

25° C (Non-condensing)
10°C per hour

0 to 10,000 feet

5 G at 10-500 Hz

30 Gs

Capacity Unformatted (+10 space cylinders)
Per drive

Per surface
Per track

33.07 MB
6.61 MB
10.416 KB

Capacity Formatted (+10 Spare Cylinders)
Per drive

Per surface
Per track

26.00 MB
5.20 MB
8.192 KB

Per sector

256 bytes

Sectors/Track

Transfer rate

5 Mbit/sec

Seek Time

Track to track

3.0 ms

Average

30.0 ms

Maximum

60.0 ms

Settling

3.0 ms

Average latency

8.33 ms

Start time

15 sec

Functional Summary
Rotation £1%
Recording max

Flux density
Track density

3600 rpm
8780 bpi

8780 fci
800 tpi

Data cylinders

645

Tracks

3175

R/W heads

Disks

Index

1056

RD52

le— 15 SEC MAX

—

DC ON

le— 11 SEC TYP —#
DISK UP

1 SEC

TO SPEED

AUTO RECAL

|le—Y"

-TRACK O
r—h

30 uSEC ,___1—“

-READY

—

-SEEK

COMPLETE

Afl

a— TYP 1 SEC

-TRACK O, -READY AND -SEEK COMPLETE WILL NOT BE PRESENT AT THE INTERFACE
UNLESS THE DRIVE IS SELECTED.

MR-12940

Power-Up Sequence

FLAT CABLE OR TWISTED PAIR
20 FEET MAXIMUM

DISK DRIVE

HOST SYSTEM

DRIVE SELECTED

D e

RESERVED

3
4 DN

SPARE

5
6

]

RESERVED (TO J1 PIN 16)
7

8 RN

SPARE

11 —
+MFM WRITE DATA

-MFM WRITE DATA

GND

J2/P2

12 —

—

16 —

+MFM READ DATA

-MFM READ DATA

GND

19 —

]

01
.

MR-12941

Data Signals

1057

RD52

FLAT RIBBON OR TWISTED PAIR MAX 20 FEET

DISK DRIVE

HOST SYSTEM
RESERVED

—

[E—

[rom—

usm—

—

-HEAD SELECT 22

_WRITE GATE

]

_SEEK COMPLETE

0
“TRACK

“WRITE FAULT

(TO J2 PIN 7)
RESERVED

"HEAD SELECT 2°

-INDEX

12
13 —
14
15

—

J1/P1

"READY

_STEP

_DRIVE SELECT 2

_DRIVE SELECT 3

"DRIVE SELECT 4

IN
_DIRECTION

_DRIVE SELECT 1

+5VDC

[] +5v RETURN

)

+12VDC

+12V RETURN

J3/P3

DC
GND

J4/P4

FRAME GND

FRAME GROUND

O TWISTED PAIR (20 GA OR LARGER)
MR-12942

Control Signals

1058

RD52

—

CONTROL

]

DATA

.___J

_—

—

/‘

DRIVE #1

|r—_ J2
l

J3
I

CONTROLLER

et
—

DRIVE #2

JL__ J2

DATA

L J3
Ja

>
]

-l

DRIVE #3

J‘"l J2

DATA

L J3
Ja

—

DATA

——{: J

1 J2

e
<
<

DRIVE #4

DC: VOLTAGES

———m——

FRAME GROUND

*THE LAST OR ONLY DRIVE IN THE CONTROL CABLE STRING MUST HAVE THE TERMINATOR

RESISTOR PACK INSTALLED. ALL OTHER DRIVES MUST HAVE THEIR TERMINATORS REMOVED.

MR-12943

Typical Connection, Four Drives

1059

RD52

A. RD52 SUBSYSTEM,

TOP MODEL
DESK

1. FRONT BEZEL
2. COVER

3. CHASSIS

4. REAR BEZEL

B. RD52 SUBSYSTEM,
RACK MOUNT MODULE

RD52 Desk-Top and Rack Mounting Housings

1060

RD52
LED RD52 DRIVE
READY

LED +5V

AC POWER

LED SWITCH

SW'TCH

WRITE-PROTECT

RD52 DRIVE

‘

[ig]i]tlal]

j” 3}

RD52

— 1V —

le
{

C—

LI
L

[

]

J)\=
|S

)

MR-13088

Front Panel, Switches and Indicators

PRIMARY VOLTAGE

SELECT SWITCH

120/240
AC LINE

CIRCUIT BREAKER

TM,

T
l]

]Il

fil1

I
[

i\
.|

L
p—

32|

[

]

;;

—lj

[

O\@)oooooooooooooooofy:/ O

—
oransssssss)o
)

O\%ooooooooaoooooooo‘W O

PRIMARY VOLTAGE
INPUT
MR-13099

Rear Panel

1061

RD52

1 UNPLUG CONNECTORS (2)

3. PUSH UNIT OUT

2. PRESS TAB DOWN

g‘

REMOVE DRIVE UNIT

Removal of Flexible Disk Drive Signal and Power Cable

1062

RD52
PATCH AND FILTER

1 RQDX1 CONTROLLER

PANEL ASSEMBLY
]

BACKPLANE

1 CK-RQDX1-KC CABINET KIT
1 RD52 SUBSYSTEM
OR

RX50 SUBSYSTEM

H9302 RACK MOUNT KIT

RQDX1

EXTERNAL CABLE

CABINET KIT CABLE

(30" FOR H349 ENCLOSURE)

CK-RQDX1-KC

“

RX50

0ol
-

FH"_“"_" %5?31——“"“"*fi

MR-12932

One Subsystem Add-On to a PDP-11/23 PLUS
PATCH AND FILTER
PANEL ASSEMBLY

RD52

]

x50

BACKPLANE

OR
RDS51

SUBSYSTEM
INTERCONNECT

CABLE BC17Y-1J

RQDX1
ERNAL C CABLE
EXTERNAL

[

RD52

i
T
KIT CABLE
CABINE

(30" FOR H349 ENCLOSURE)|___

CK-RQDXI-KC

574 M

‘

(8 FT)

MR-12931

Two Subsystem Add-Ons to H349 Distribution Panel

INBOARD

DRIVES

DIonAL
DISTRIBUTION

BULKHEAD

BOARD

{

RX50

RQDX1

INTERNAL

CK-RQDXI-KA

CABLE

\‘7

RQDXL;/"

RD51

BUS

EXTERNAL

CABLE

RD52

EXTENDER

LJ v/

IF
I

CK-RQDXI-KA

MR-12933

Maximum Expansion Configuration
1063

RKO05

RKO05 DISK DRIVE SUBSYSTEM

RKO5 Disk Drive

The RKO5-J disk drive uses a removable disk cartridge and the RKO5-F
uses a fixed, dual-density disk cartridge. Both drives are interfaced by the

RKV11-D option. The RKV11-D is set at address 177400 and vector 220.

Applicable diagnostic programs are found in Appendix A.
Related Documentation

RKV11-D Field Maintenance Print Set (MP-00223-00)
RKO5-J Field Maintenance Print Set (MP-ORK(05-0J)
RKO5-F Field Maintenance Print Set (MP-ORKO05-0F)

RKV11-D User’s Guide (EK-RKV11-OP)
Microcomputer Interfaces Handbook (EB-20175-20)
RKO5 Disk Drive User’s Guide (EK-ORK05-OP)
RK05,/05J/05F Maintenance Manual (EK-RK5JF-MM)
RKO5 Exercisor Maintenance Manual (EK-RKO5X-MM)

p——

!!
HH
MMMMMM

RKO5 Disk Drive

1064

RKO05
Controls and Indicators for the RK05, RK05-J, and RKO5-F

Controls and
Indicators

Description

RUN/LOAD

Placing this switch in the RUN position (provided

(Rocker Switch)

that all interlocks are safe):
a.

locks the drive front door

accelerates the disk to operating speed

loads the read/write heads

lights the RDY indicator.

Placing this switch in the LOAD position:
a.

unloads the read/write heads

stops the disk rotation

unlocks the drive front door when the disk has
stopped

lights the LOAD indicator.

CAUTION

Do not switch to the LOAD position during a write operation;
this results in erroneous data being recorded.
WT PROT

(Rocker Switch
Spring-Loaded Off)

Placing this momentary contact switch in the PROT
position lights the WT PROT indicator and prevents
a write operation; it also turns off the FAULT indicator, if that is lit.

Depressing this switch in the WT PROT position a
second time turns off the WT PROT indicator and allows a write operation.

PWR (Indicator)

Lights when operating power is present. Goes off
when operating power is removed.

RDY (Indicator)

Lights when:

the disk

rotating

at the correct operating

speed

the heads are loaded

no other conditions are present (all interlocks
safe) to prevent a seek, read, or write operation.

Goes off when the
LOAD.

1065

RUN/LOAD switch

is set to

RKO5

Controls and Indicators for the RK05, RK05-J, and RKO5-F (Cont)
Controls and
indicators

Description

ON CYL (Indicator)

Lights when:

the drive is in the ready condition

a seek or restore operation is not being performed

the read/write heads are positioned and settled.

Goes off during a seek or restore operation.
FAULT (Indicator)

Lights when:

erase or write current is present without a write
gate

the linear positioner transducer lamp is inoperative.

Goes off when the WT PROT switch is pressed, or
when the drive is recycled through a run/load sequence.

WT PROT (Indicator) Lights when:
a.

the WT PROT switch is pressed

the operating system sends a WRITE PROTECT
command.

Goes off when the WT PROT switch is pressed a
second time, or when the drive is recycled through a
run/load sequence.

LOAD (Indicator)

WT (Indicator)

RD (Indicator)

Lights when the read/write heads are fully retracted
and the spindle has stopped rotating.
Lights when a write operation occurs. Goes off when
the write operation terminates.

Lights when a read operation occurs. Goes off when
the read operation terminates.

1066

RKO5
Performance Specifications

Storage Medium
Type

Single-disk magnetic cartridge (RK05, RK0O5J - removable; RKO5F - nonremovable)

Disk Diameter

551 cm (14 inches)

Magnetic Heads

Number

Bit Transfer
Transfer Code

Double frequency, NRZ recording

Transfer Rate

1.44 m bit/s

Electrical Requirements
Voltage

115/230 Vac @ 50/60 Hz + .05 Hz

Power

250 VA

Starting Current

Power only: 1.8 A

Start spindle: 10 A (for 2 seconds)

Model Designation

RKO5-AA, RKOS5J-AA, RKOSF-AA, RKO5F-FA 95 - 130 Vac @ 60 = 0.5 Hz

RKO05-AB, RKO5J-AB, RKO5F-AB, RKO5F-FB 290 - 260 Vac @ 60 = 0.5 Hz
RKO05-BA, RKO5J-BA, RKOS5F-AC, RKO5F-FC 95 - 130 Vac @ 50 + 0.5 Hz
RK05-BB, RK0O5J-BB, RKO5F-AD, RKOSF-FD 190 - 260 Vac @ 50 = 0.5 Hz

Dimensions and Weight

Width:

48 cm (19 in)

Depth:

67 cm (26.5 in)
27 cm (10.5 in)

Height:
Weight:

50 kg (110 Ib)

1067

RK05
Unit Selection

unit designaAn RKO5 disk drive may be configured to respond to a desired
switch. The rotary

tion by selecting the appropriate setting on a rotary

cage. The circuit cards
switch is located on the second module in the card ed
ng the rear
are located behind the prefilter, and may be access byInremovi
, the
RKO05-J
the
unit.
drive
disk
the
of
side
cover panel on the bottom
rotary switch is on the M7700 module. In the RKO5-F it is on the M7680.
M7700 OR M7680

MR-0832

M7700 or M7680 Placement

Bootstrap Program for RKOS

If an RKO5 is used in a system that has no hardware bootstrap module, the
disk drive may be booted by entering the following program manually.
@R0/000000 ONOOOO<CR>*
@R1/000000 177404<CR>
@ 1000/000000 000005<LF>
001002,/000000 01006 1<LF>
001004,/000000 000006 <LF>
001006,000000 012761<LF>
001010,/000000 177400<LF>
001012,/000000 000002<LF>
001014,/000000 0127 11<LF>
001016,/000000 000005<LF>
001020,/000000 1057 11<LF>
001022,/000000 100376<LF>
001024,/000000 005007 <CR>
@1000G

*n = O for drive O: 2 for drive 1; and 4 for drive 2.
1068

RKO05

DISK DRIVE
UNIT NUMBER

SELECTOR SWITCH

LT
Controller Switches

1069

MR-0833

RLO1/RLO2

RLO1/RL02 5.2/10.4 Mb CARTRIDGE DISK DRIVE UNIT

RLO1/RLO2 Disk Drive

The RLO1 is a 5,000,000 byte disk drive that uses a modified, removable,
5440-style cartridge (RLO1K-DC). The RLO2 is a dual-density version of the

RLO1. The RLO2 uses an RLO2K-DC cartridge. Both the RLO1 and RLO2 use
the RLV11 interface module. Up to four drives of either type in any combination can be connected to an RLV11 interface. The RLV 11 is normally
configured for a bus address of 77440X octal with a vector address of 160

octal. For more in-depth information, refer to the RLV11 (M8013/8014)
section. Additional information can be found in the following manuals.

RLO1/RLO2 Disk Drive Technical Manual (EK-RLO12-TM)
11 Technical Description (EK-RLV11-TD)
RLV
RLO1/RL0O2 Pocket Service Guide (EK-RLO12-PG)
RLO1/RL0O2 Disk Subsystem User’'s Guide (EK-RLO12-UG)
RLO1 llustrated Parts Breakdown (EK-ORLO1-IP)
RLO2 lllustrated Parts Breakdown (EK-ORLO2-IP)
RLO1 Field Maintenance Print Set (MP-00527-00)
RLO2 Field Maintenance Print Set (MP-006398-00)
RLV11 Field Maintenance Print Set (MP-00635-00)
Microcomputer Interfaces Handbook (EB-20175-20)
Specifications RLO1/RL0O2
Medium

Type:

Single platter, top-loading cartridge (similar to IBM 5440).
Embedded servo information.

Capacity:

RLO1K-DC = 5.2 Mb
RLO2K-DC = 10.4 Mb

Cylinders:

RLO1 = 256
RLO2 = 512

Sectors:

Heads:

1070

RLO1/RLO2

SWITCH AND
INDICATOR

(B)

UNIT SELECT
PLUG/READY

LIGHT

(C)

FAULT WRITE
(D)
PROTECT AND

SWITCH INDICATOR

MR-5532

RLO1/RL0O2 Controls and Indicators

Data Transfer

MFM (Miller coding) recording; 244 ns cell time; 4.1

megabytes/s (4.9

us/word).

RLO1/RLO2 Bootstrap

Ensure that the heads are over cylinder O and head O is selected by releas-

ing the LOAD switch, waiting for the LOAD indicator to light, then depress-

ing the LOAD switch. After the drive is ready, initialize the controller with a
system initialize. Perform a bit status clear. Load the following program into
memory.

LOC

Contents

Comments

10000

012737

Load CSR

10002

000014

10004

174400

10006

000001

Wait

Start the program at 10000 and allow it to run for a few seconds, halt the
program and restart at 00000.

1071

RLO1/RL02

RLO1/RLO2 Controls and Indicators
Switches

Function

Power ON/OFF

In the OFF position, ac power is removed from the

rear of the drive)

In the ON position, ac power is supplied to the drive.

Circuit Breaker
(Located in the

(A) LOAD

drive.

‘This is a PUSH/PUSH alternating action switch.
When depressed, the RLO1/RL0O2 begins a ‘‘cycle
up’’ sequence, provided that:

the RLO1/RLO2K cartridge is installed
the cartridge cover is in place
the access door is closed

all ac and dc voltages are within spec
the R/W heads are retracted

the brushes are in the ‘““home’’ position.

When released, the RLO1/RL0O2 will begin a ““cycle
down’’ sequence.

(B) UNIT SELECT
PLUG

This is a cam-operated switch that is activated by inserting a numbered, cammed button. The switch
contacts are binary encoded so that the drive assumes the logical unit number that is printed on the
button.

(D) WRITE PROTECT

This is an alternating action PUSH/PUSH switch.

When depressed, the drive assumes a write protect

status (during a write operation). When released,

the drive is no longer write protected.

1072

RLO1/RL02
RLO1/RLO2 Controls and indicators (Cont)
Indicators

Function

(A) LOAD (Yellow)

Indicates that the drive is ready to have a cartridge

loaded (or unloaded). The LOAD indicator will light
when:

(B) READY (White)

the spindle is stopped

the R/W heads are “‘home”

the brushes are ‘“‘home.”

When lit, indicates a ‘‘drive ready’’ condition;

i.e.,

the heads are lcaded and detented.

Indicates when one of the following has occurred.
drive select error

seek timeout error (1.5 second)
write current in heads during ‘‘sector time”’
loss of system clock from RLV 11

write data error (no transitions)

spin error (over speed or 40 sec timeout)
write gate error (attempting to write when not
ready, when write protected,

or during

sector

time)
(D) WRITE PROTECT Indicates that drive is write protected. That is, write
(Yellow)

operations to the cartridge will be inhibited (and the
FAULT indicator will light).

1073

RX01

RX01 FLOPPY DISK DRIVE

RXO01 Floppy Disk Drive

The RX01 floppy disk drive is part of the RXV11 floppy disk system, and is

interfaced by the RXV 11 interface module (M7946). The disk system uses
address 177170 and vector 264 for the first option, and address 177174
and vector 270 for a second option.

]

MR 0834

RX01 Floppy Disk

Model Designations

RXV11-AA Single Drive System, 115 V/60 Hz
RXV11-AC Single Drive System, 115 V/50 Hz
RXV11-AD Single Drive System, 230 V/50 Hz
RXV11-BA Dual Drive System, 115 V/60 Hz
RXV11-BC Dual Drive System, 115 V/50 Hz

RXV11-BD Dual Drive System, 230 V/50 Hz

1074

RXO01
Related Documentation

RXV11 User's Manual (EK-RXV11-00)

RX01/RX8/RX11 Floppy Disk System Maintenance Manual (EK-RX01-MM)
RXV 11 Field Maintenance Print Set (MP-00024-00)
RX01 Field Maintenance Print Set (MP-00296-00)

RX01/RX02 Reference Card (EK-RX01-RC)

Microcomputer Interfaces Handbook (EB-20175-20)

NOTE
50 Hz versions are available in voltages of 105, 115, 220, and
240
Vac
by
field-pluggable
conversion.
Refer
to
the
RX01/RX8/RX11 Floppy Disk System Maintenance Manual for
complete input power modification details.

AC Power
The RXV 11 floppy disk system is available in the following three ac voltage/model configurations.

Models

Voltage/Frequency

RXV11-AA, -BA

100 Vac-132 Vac, 60 Hz

RXV11-AC, -BC

100 Vac-132 Vac, 50 Hz

RXV11-AD, -BD

180 Vac-264 Vac,

50 Hz,

one of two voltage

ranges. The actual voltage range is user-selected by
installing the appropriate power harness during sys-

tem installation, as follows.
Volitage

Power Harness

Range

180-240

70-10696-04

200-264

70-10696-03

Power Consumption

RXO1

3 A at 24 V (dual), 75 W;
5Aats5V, 25W

RXV11 interface (M7946)
Power input (ac)

Not more than 1.5 A at 5 Vdc
4 A at 115 Vac
2 A at 230 Vac

1075

RX01

Bootstraps for Manual Entry
Abbreviated Version
(Drive O Only)

Full Length Version

@ 1000/000000 5000<LF>
001002/000000 12701<LF>
001004,/000000 177170<LF>
001006,/000000 1057 11<LF>
001010/000000 1776<LF>
001012/000000 127 11<LF>
001014,/000000 3<LF>
001016,/000000 5711<LF>
001020,/000000 1776<LF>
001022,/000000 100405<LF>
001024,/000000 1057 11<LF>
001026,/000000 100004 <LF>
001030/000000 116120<LF>
001032/000000 2<LF>
001034/000000 770<LF>

@ 1000/000000 12702<LF>
001002/000000 1002n7 <LF>"*
001004,/000000 12701<LF>
001006,/000000 177170<LF>
001010/000000 130211<LF>
001012/000000 1776<LF>
001014/000000 112703<LF>
001016,/000000 7<LF>
001020,/000000 10100<LF>
001022/000000 10220<LF>
001024,/000000 402<LF>
001026,/000000 127 10<LF>
001030/000000 1<LF>
001032,/000000 6203<LF>
001034/000000 103402<LF>
001036,/000000 1127 11<LF>
001040,/000000 111023<LF>
001042/000000 32011<LF>
001044,/000000 1776<LF>
001046,/000000 100756 <LF>
001050,/000000 103766<LF>
001052/000000 1057 11<LF>
001054,/000000 10077 1<LF>
001056,/000000 5000<LF>
001060,/000000 227 10<LF>
001062/000000 240<LF>
001064,/000000 1347<LF
001066,/000000 122702<LF>
001070/000000 247<LF>
001072/000000 5500<LF>
001074,/000000 5007 <CR>

001036,/000000 O<LF>

001040/000000 5007 <CR>

4 for unit O
n
n = 6 for unit 1
<LF> = Line Feed

<CR> = Carriage Return
1000
Starting address

1076

RX02

RX02 FLOPPY DISK DRIVE

RX02 Floppy Disk Drive
The RX02 is part of the RXV11-XX floppy disk system. The RXV21-BX op-

tions use the RX02 in double-density mode with the RXV21 (M8029) interface module. The RXV21-DX options use the RX02 in single-density mode

with the

RXV 11 (M7946) interface module.

dilgiitlal| lRcEH

[

]

MR-5530

Front View of the Floppy Disk System
The density mode of the RX02 is selected by switches on the M7744 con-

troller module. This module is located in the RX02 floppy disk drive. The

following switch settings define the mode of the RX02.

Controller Configuration Switch Settings
(Located on M7744 Module)

Interface

Si-1

S1-2

RX211/RXV21

OFF
ON
OFF

ON
OFF
OFF

RX8E/RX11/RXV 11
RX28

NOTE

The subject of the RX02 as used in a PDP-8 system is beyond
the scope of this document.

Detailed configuration and diagnostic information is contained in this man-

ual. Refer to the section covering the applicable interface (M7946 or
M8029).

1077

RX02
Related Documentation

RX02 Floppy Disk System User’s Guide (EK-ORX02-UG)
RX01/RX02 Reference Card (EK-RX102-RC)

Microcomputer Interface Handbook (EK-20175-20)
RX0?2 Print Set (MP-00629-00)

Module Designations

RxXv21

115V, 60 Hz

-DC
-DD

M7946
M7946

M7946

RXO02-DA

RX02-DC
RX02-DD

115V, 50 Hz
230V, 50 Hz

-BA
-BC
-BD

M8029
M8024
M8027

RXO02-BA
RX02-BC
RX02-BD

115V, 60 Hz
115V, 60 Hz
230V, 50 Hz

-DA

Power Requirements

The RX02 is designed to use either a 60 Hz Vac or a 50 Hz power source.

The 60 Hz version will operate from 90 Vac-128 Vac, without modifications,
and will use less than 4 A operating. The 50 Hz version will operate within
four voltage ratings and will require field verification/modification to ensure
that the correct voltage option is selected. The voltage ranges of 90
Vac-120 Vac and 184 Vac-240 Vac will use less than 4 A operating. The
voltage ranges of 100 Vac-128 Vac and 200 Vac-256 Vac will use less
than 2 A. Both versions of the RX02 will be required to receive the input
power from an ac source (e.g., 861 power control) that is controlled by the
system’s power switch.

Input Power Modification Requirements

The 60 Hz version of the RX02 uses the H771-A power supply and will operate on 90 Vac-128 Vac, without modification. To convert to operate on a
50 Hz power source in the field, the H771-A supply must be replaced with
an H771-C or -D and the drive motor belt and drive motor pulley must be
replaced. The H771-C operates on a 90 Vac-120 Vac or 100 Vac-128 Vac
power source. The H771-D operates on a 184 Vac-240 Vac or 200
Vac-256 Vac power source. To convert the H771-C to the higher voltage

ranges or the H771-D to the lower voltage ranges, the power harness and

circuit breaker must be changed. The appropriate jumper and circuit breaker are shown in the following figure.

1078

RX02
JUMPER P1
/,

A~ (0re e

POWER PLUGS

SHIPPING

RESTRAINT (RED)

VOLTAGE (VAC)

JUMPER

90-120

70-10696-02

CIRCUIT BREAKER

3.5 A, 12-12301-01

100-128

70-10696-01

3.5 A, 12-12301-01

184-240

70-10696-04

1.75 A, 12-12301-00

200-256

70-10696-03

1.75 A, 12-12301-00
MR-5531

RX02 (Rear View)
Bootstrap for Manual Entry (ODT)
RX02/BRXV11 (M7946)
@1000/XXXXXX

5000<LF>

1002/ XXXXXX

12701<LF>

1004
/XX XXXX

177170<LF>

1006,/ XXX XXX

1057 11<LF>

1010/ XXXXXX

1776<LF>

1012/XXXXXX

12711<LF>

1014/XXXXXX

3<LF>

1016/ XXXXXX

5711<LF>

1020/ XXXXXX

1776<LF>

1022/ XXXXXX

100405<LF>

1024 /XXXXXX

1057 11<LF>

1026/ XXXXXX

1000004 <LF>

1030/ XXXXXX

116120<LF>

1032/ XXXXXX

2<LF>

1034/ XXXXXX

770<LF>

1036/ XXXXXX

O<LF>

1040/ XXXXXX

5000<LF>

1042/ XXXXXX

110<CR>

@1000G

<LF> = Line Feed.
<CR> = Carriage Return.

XXXXXX = Original contents of location opened

1079

RX02
RX02/RXV21 (M8029)
@2000/XXXXXX

2002/XXXXXX
2004 /XXXXXX
2006/ XXXXXX
2010/XXXXXX

12701 <LF>

177170<LF>

12700<LF>
100240<LF>

5002<LF>

2012/XXXXXX

12705<LF>

2014 /XXXXXX
2016/XXXXXX

200<LF>

2020/ XXXXXX

401<LF>

2022/XXXXXX

12703<LF>

2024 /XXXXXX
2026/ XXXXXX

30011<LF>

12704<LF>

177172<LF>

2030/XXXXXX

1776<LF>

2032/XXXXXX

100436<LF>

2034 /XXXXXX

12711<LF>

2036/XXXXXX

407 <LF>

2040/XXXXXX

30011<LF>

2042/XXXXXX

1776<LF>

2044 XXXXXX

100431<LF>

2046/XXXXXX

110413<LF>

2050/XXXXXX

304<lL.F>

2052/XXXXXX

30011 <LF>

2054 /XXXXXX

1776<LF>

2056/XXXXXX

110413<LF>

2060/XXXXXX

304<LF>

2062/XXXXXX

30011<LF>

2064 /XXXXXX

1776<LF>

2066/ XXXXXX

1100420<LF>

2070/XXXXXX

12711<LF>

2072/XXXXXX

403<LF>

2074/XXXXXX

30011<LF>

2076/XXXXXX

1776<LF>

2100/XXXXXX

100413<LF>

2102/XXXXXX

10513<LF>

2104/XXXXXX

30011<LF>

2106/XXXXXX

1776<LF>

2110/XXXXXX

100407 <LF>

2112/XXXXXX

10213<LF>

2114/ XXXXXX

6052<LF>

2116 /XXXXXX

60502<LF>

2120/XXXXXX

F>
122424<

2122/XXXXXX

120427 <LF>

2124 /XXXXXX

/<LF>

1080

RX02
RX02/RXV21 (M8029) (Cont)
2126 /XXXXXX

3737<LF>

2130/XXXXXX

5000<LF>

2132 /XXXXXX

5007 <LF>

2134 /XXXXXX

0<CR>

@2000G

1081

RX50

RX50 FLOPPY DISK DRIVE SUBSYSTEM

GENERAL

The RX50 R/D (rack or desk mount) uses an RQDX1 controller interface which
controls up to four logical units. The RX50 uses two logical units and the RD51
uses one logical unit. With a system using an RQDX1 controller, the maximum
configuration that can be used is two RX50 disk drive units or one RX50 and one

RD50 disk unit, expandable by one RD51 drive unit by using an RQDX1-E bus

extender option.

RX50 Flexible Disk Drives - 120 Vac or 240 Vac Voltage Selectable
Power Supply

+12 Av
.1 A
Minimum
Maximum 1.3 A

+5V
3 A
50A

+12 Battery voltage
0A
12 A

8 A
5 A
5 A

A2 A
A2 A
A2 A

RX50 Voltage

Maximum 3 A
Minimum 1.3 A
Standby 0.1 A
Capacity (diskette)
800K bytes

Related Documentation

MICRO/PDP-11 System, Technical Manual (EK-OLCP5-TM)
MICRO/PDP-11 System, Owner’s Manual (EK-OLCP5-OM)
MICRO/PDP-11 System, Unpacking and Installation Guide (EK-OLCP5-IN)
MICRO/PDP-11 System Option Manual (EK-OLCP5-OD-001)
RQDX1 Controller Module User’s Guide (EK-RQDX1-UG)

(includes RQDX1-E Bus Extender)

H9302 Rack Mounting Kit Installation Manual (EK-LEPQ3-IN)

Compatibility

RX50 R/D units are used as add-ons in the PDP-11/23 PLUS, MICRO/PDP-11,
MICRO VAX |, and other Q-BUS hosts.

1082

RX50
Front Panel Controls and Indicators
AC power ON/OFF switch - connects ac power to the internal power supply.

TOP THREE LEDs

LIT

1st (yellow) LED

When top drive is write protected

2nd (green) LED

+5 Vdc is being supplied to the drive

3rd (yellow) LED

When bottom drive is write protected
NOTE

Never open a disk drive door when either drive’s light is on (active
drive).

LED WRITE-PROTECT
DRIVE 2 (BOTTOM)

AC POWER

DRIVE 1 (TOP)

SWITCH

LIGHT 1

ACTIVE DRIVE

S
¥

[

LIGHT 2

DRIVE 2 DOOR

]

o —

\LHHHARHHAHHHHA R

ACTIVE DRIVE

RQ\

[ Gl

// h

\..

\ \

LED +5 V

LED WRITE-PROTECT

DRIVE 1 DOOR
MR12200

Front Panel, Switches and Indicators

1083

RX50
PRIMARY VOLTAGE

SELECT SWITCH
120/240

AC LINE

CIRCUIT BREAKER

jE—

—

PRIMARY VOLTAGE
INPUT
MR-13099

RX50 Rear View

RX50 Subsystem Dimensions and Weights
Dimensions

Approximately 12 inches long 9
inches wide, 5-1/2 inches high

Desk top configuration and
rack mount configuration

Weights

Approximately 14 pounds

Desk top configuration and
rack mount configuration

The hardware requirements for the BA23 enclosure are:
1

RQDX1 Controller

CK-RQDX1-KA cabinet kit

RX50-D subsystem
or

RX50-R subsystem

H9302 rack adapter Kkit.

1084

RX50
The hardware requirements for the H349 enclosure are:

RQDX1 controller

CK-RQDX1-KC cabinet kit

RX50-D subsystem
or

RX50-R subsystem

H9302 rack adapter Kkit.

The figure below illustrates how to add two subsystems, RD51 and RX50, to a
BA23 or an H349 enclosure.

PATCH AND FILTER

BACKPLANE

PANEL ASSEMBLY
]

1 RQDX1 CONTROLLER
1 CK-RQDX1-KC CABINET KIT
1 RD52 SUBSYSTEM

OR
1 RX50 SUBSYSTEM
1

H9302 RACK MOUNT KIT

RQDX1

r
]
L

EXTERNAL CABLE

h
d
|
L

CABINET KIT CABLE
(30" FOR H349 ENCLOSURE) J

RX50

CK-RQDX1-KC

MR-12932

Single Expansion Configuration

PATCH AND FILTER
PANEL ASSEMBLY
]

RX50

BACKPLANE

RD51

SUBSYSTEM
INTERCONNECT

CABLE BC17Y-1J

RQDX1

[

rFet

EXTERNAL CABLE

RDS51

CABINET KIT CABLE

(30" FOR H349 ENCLOSURE)|__|
CK-RQDXI-KC

274 M

(9 FT)

I
MR-12187

Double Expansion Configuration

1085

RX50
The hardware requirements for the BA23 enclosure are:
1

RQDX1 controller

CK-RQDX1-KA cabinet kit.

The two subsystems can be either:

RD51-D subsystems or 2 RD51-R with 1 H9302 adapter kit or

BC17Y-1 J subsystem interconnection cable.

1
1

RD51-D or -R with 1 H9302
RX50-D or -R with H9302

The hardware requirements for the H349 enclosure are:
1

RQDX1 controller

CK-RQDZ1-KC cabinet kit

and the two subsystems can be either:

RD51-D subsystems or 2 RD51-R with 1 H9302 rack adapter kit or:

RD51-D or 1 RD51-R with 1 H9302 rack adapter kit

RX50-D or RX50-R

BC17Y-1J subsystem interconnection cable.

The hardware requirements are:

RQDX1-E RQDX1 extender

CK-RQDXE-KA cabinet kit RD/RX controller EXT BA23
RD51-D
or

RD51-R with 1 H302 rack adapter Kkit.

1086

RX50
SYSTEM AND EXTERNAL SUBSYSTEM INTERCONNECT
System enclosures such as the BA23 and H349 have a patch and filter panel
assembly, attached to the rear of the unit. This panel has an unused area that can
be used for system expansion. The internal system cabling for the external subsystem is contained in the cabinet kits and will be connected to a proper connector
on the internal side of the patch panel. The subsystem user can simply connect to
the external connector of the port used.

J1, J2 and J3 Pin Numbers and Signal Names

Connectors J1, J2 and J3 have the same signal names and pin numbering.

Pin Numbers

Signal Names

Pin Numbers

Signal Names

J1-01

MEMWRTDT1 (H)

J1-25

DRV SEL 4 (L)

J1-34

MEMWRTDT1 (L)

J1-09

GROUND

J1-18

GROUND

J1-42

INDEX (L)

J1-02

HEAD SET 2 (L)

J1-26

RD1WRTPRO (L)

J1-35

GROUND

J1-10

DRV SEL 1 (L)

J1-19

SEEKOPLT

J1-43

DRV SEL 2 (L)

J1-03

RD1 RDY (H)

J1-27

DRV SEL 3 (L)

J1-36

WPT FAULT (L)

J1-11

RX2WPTLED (L)

J1-20

GROUND

J1-44

RXMOTORON (L)

J1-04

READ SEL 1 (L)

J1-28

GROUND

J1-37

RXOWPTLED (L)

J1-12

DIRECTION (L)

J1-21

RDO RDY (H)

J1-45

GROUND

J1-05

RX1WPTLED (L)

J1-29

STEP (L)

J1-38

DRVSLOACK (L)

J1-13

GROUND

J1-22

MEMRDDATO (H)

J1-46

RXWRTDATA (L)

J1-06

MFMRDDATO (L)

J1-30

GROUND

J1-39
J1-23

MFMWRTDTO (H)
MFMWRTDTO (L)

J1-14
J1-47

WRT GATE (L)
GROUND

J1-07
J1-40
J1-24

MFMRDDAT1 (H)
MFMRDDAT1 (L)
GROUND

J1-31
J1-15
J1-48

TRACK 00 (L)
RX3WPTLED (L)
DRVSL1ACK (L)

J1-08
J1-41

RFDUCWRTI (L)

J1-32

RDOWRTPRO (L)

J1-16

GROUND
READ DATA (L)

J1-49

GROUND

J1-33

HEAD SEL 0 (L)

J1-17

GROUND

J1-50

READY (L)

1087

RX50
Power Supply Connectors

AC Power Input Connector

Pin No.

Signal

1
2

Ground
AC phase

AC neutral

DC Power Output Connector

~NOoOO
e WM -

Signal
+5V

Pin No.

12 VA

12 VB

No pin

No connection

+5V
+5V
Return
Return
Return

Return

12 VA

Logical Unit Number Selection

The logical unit number (LUN) selection is set by jumpers on the RQDX1 controller
module. These jumpers are set to the lowest LUN logical unit number assigned to
any RD51 or RX50 drive subsystem that is controlled by the RQDX1. The RQDX1
module automatically senses the logical unit configuration during initialization of
the system to determine how many of the four possible units are actually present.

1088

RX50
The LUN jumper format allows only one jumper to be installed at a time, and each
individual jumper specifies a group of 4 logical units as follows.

No jumper installed

0-3

—

LUNs Specified

4-7

LUN Jumper

8-11
12-15

20-23

0O ~NOO

16-19

28-31

24-27
32-35

Within the context of RQDX1 configurations as shown below, if the number 4
jumper is connected and configuration number 2 is being used, then:
16 = unit 0
17 = unit 1

18 = unit 2
19 = unit 3

Configuration

External Subsystem

Logical Unit Numbers

Number

Disk Drives

for Disk Drive

One RD51, one RX50

Unit 0 = RD51
Units 1, 2 = RX50

Two RX50s

Units 0, 1 = RX50
Units 2, 3 = BRX50

Two RD51s, one RX50

Unit 0 = RD51
Unit 1 = RD51

Units 2, 3 = RX50

Unit 0 = RD51

Two RD51s

Unit 1 = RD51

One RX50

Units 0, 1 = RX50

One RD51

Unit 0 = RD51

1089

RX50

System Controller Options

Description

Model

RQDX1

RX50 and/or RD51 MSCP controller.

Controller/Interface,
MSCP Q-BUS

One controller handles up to four logical units. No more than two RX50s per
controller. One RX50L is equal to two
LUNSs.

RQDX1-E

Bus EXTENDER w/cable Enables external drive (RX50, RD51)

to connect to MICRO/PDP-11 internal
controller-to-drive bus. Allows either
one external RX50 or one external
RD51 to be connected to the
MICRO/PDP-11 controller depending
on the RQDX1 configuration

guidelines.

CK-RQDX1-KA Cabinet kit for installing the RQDX1 controller in a BA23 enclosure
(MICRO/PDP-11).

CK-RQDX1-KC Cabinet kit for installing the RQDX1 controller with the H349 1/O
panel (PDP-11/23 PLUS).

CK-RQDXE-KA Cabinet kit for installing the RQDX1-E extender in a BA23 enclosure (MICRO/PDP-11).

BQO1-C

Country kit, Doc, for RQDX1 Controller and Extender.

RQO1-D

Country kit, Doc, Labels, Diagnostic for RX50-R, -D.

BQO1-E

Country kit, Doc, Labels for RD51-R, -D.

1090

RX50

BASIC CHASSIS
FRONT VIEW

GROOVEFOR
____——>la
=
QUicK RELEASE TAB
CHANNEL GUIDE
A. SUBSYSTEM MOUNTING ARRANGEMENT,
UNDERSIDE
OF BASIC CHASSIS.

CATCH FOR

QUICK RELEASE

CHANNEL GUIDE

MATING

MOUNTING

ON FLOOR OF

SPRING

ARRANGEMENT,

EXTRUDED HOUSING.

RACK MOUNT HOUSING
FRONT VIEW

WALL OF EXTRUDED
COVER

(DESK TOP) FRONT
VIEW

MATING MOUNTING ARRANGEMENTS (2},
ON FLOOR OF RACK MOUNTING HOUSING.
MR-12181

Mounting Channel and Quick Release Latch

1091

RX50

A. RX50-R RACK MOUNTED MODEL

FRONT BEZEL

COVER

CHASSIS
REAR BEZEL

B. RX50-D DESK TOP MODEL
MR12212

RX50 Desk-Top and Rack Mounting Housing

1092

RX50

MR12208

Opening the Drive 1 Door

READ/WRITE ACCESS
SLOT FORWARD

WRITE-PROTECT
NOTCH TO LEFT

Inserting a Flexible Disk in Drive 1

1093

RX50

MR12209

WRITE-PROTECT

NOTCH TO RIGHT

ORANGE ARROW

\\\\\

[%;;\\\

READ/WRITE ACCESS
SLOT FORWARD

Inserting a Flexible Disk in Drive 2

1094

RX50

1. UNPLUG CONNECTORS (2)

3. PUSH UNIT OUT

2. PRESS DOWN TAB

4. REMOVE DRIVE UNIT

Removal of Flexible Disk Drive Signal and Power Cable

1095

RX50

DRV11-J
PARALLEL

DZv1i

(SYNC LINE INTERFACE)

DRV11-J

[

LINE INTERFACE

b Y

1J3

J5
__________________
s8

CONSOLE

J9
oo
|
7
JI0

b <—————D2ZV11
b

g1 [T T

J13

::i:&;: 4

/
DZV11

DZV11

\
DLV11d

Dzv11

MR-7378

H349 Distribution Cable

1096

RX50

REMOVABLE

INSERT

@N\°ce0c0c000000

0000000000000

oocooococo0C0

&
@

o)
0000000 D000C0

9
o

50-PIN

CONNECTOR

EXPANSION SLOTS
MR-12936

BA23 Patch and Filter Panel Assembly

PATCH AND FILTER
PANEL ASSEMBLY

T
BACKPLANE

1 RQDX1 CONTROLLER

CK-RQDX1-KC CABINET KIT

RX50 SUBSYSTEM

OR
RX50 SUBSYSTEM

1 H9302 RACK MOUNT KIT

RQDX1

EXTERNAL CABLE

|l
CABINET KIT CABLE

BO”FORFB49ENCLOSURE)~“J

RX50

CK-RQDX1-KC

MR12204

One Subsystem Add-On to a PDP-11/23 PLUS

1097

TU58

TU58 TAPE CASSETTE UNIT

GENERAL
tape
The TU58 DECtape Il is a random access, fixed length block, mass storage
ng
containi
s
package
eel
reel-to-r
atted
preform
's
DIGITAL
are
unit. Tape cartridges
consists
r
processo
TU58
The
42.7m (140 ft) long by 3.91mm (0.150 in) wide tape.
of an 8095 processor, supported by firmware in a 2Kb, read only memory (ROM).

Power Consumption

Board plus 1 and 2 drives
11 W typical, drive running

+5V + 5% @ 0.75 A (max.)
+12 V +10, -5% @ 1.2 A, peak
0.6 A average running
0.1 Aidle

Rackmount

90-128 Vac 180-256 Vac
47-63 Hz, 35 W (max.)

1098

TU58

Installing the Bezel

1099

TUS8
Related Documentation

TU58 DECtape Il User’s Guide (EK-0TU58-UG)

TU58 DECtape Il Pocket Service Guide (EK-0TU58-PS)
TU58 DECtape Il Technical Manual (EK-0TUS8-TM)
TU58 DECtape Il lllustrated Parts IPB (EK-0TUS8-IP)

Field Maintenance Print Set (MP00747-CA)
Field Maintenance Print Set (MP01014-EA)
Field Maintenance Print Set (MP01013-VA)

Field Maintenance Print Set (MP01063-DB)

Model Distinctions
CA Rackmount

Large chassis
Two drives

Serial interface controller board
Switch selectable 120/240 Vac
Detachable line cord

2 cartridges

Boot ROM for MR11

Two 1/O cables (BC17A/BC178-18)
Diagnostic kit (ZJ278-RG)

CABLE SHIELD
GROUND SCREW

o Io 110/220
V SWITCH
INTERFACE

<:>FUSEPOST

[:}CABLE

CONNECTOR

lm‘

LINE CORD RECEPTACLE

MR-12890

TU58-CA Rear Panel

1100

TUS8
DA Rackmount
Tabletop chassis

TUS8-CA features with additional accessory assembly hardware kit (7016753-00)

120/240V

FUSE POST

SWITCH

INTERFACE CABLE

To0

POWER

LINE CORD

RECEPTICAL

GROUND SCREW

SWITCH

CABLE SHIELD

CONNECTOR

MR-12891

TUS8-DA Rear Panel

EA Tabletop
Two drives

Serial interface controller board
EB Tabletop
Two drives

Serial interface controller board

Two 1/O cables (BC17A-18/ BC17B-18)
Boot ROM for MR11-EA

Accessory assembly hardware kit (70-16753-00)
Field Maintenance Print Set (MP01014)
VA Tabletop
Two drives

Serial interface controller

DC Power cable (70-17569-00)
I/O interface cable (70-17568-1F)
Two cartridges

MXV11-A2 boot ROM

Field Maintenance Print Set (MP01013)
Accessory assembly hardware kit (70-16753-01)

1101

TUS8
BA11-VA OR
SB11 BOX

TUBB-VA

DECTAPE Il

NG BRACKETS
"4ANDMOUNTI
10-32 X 1/2 INCH
TO BA11-VAOR TO

HANG MOUNT

METAL BRACKETS with |
[ Use
tos2xi2nchscrews |

L1
|

| :\"b HARDWARE KIT

tfi?fi?g%i T/EQElT[\JCH

DEC P/N 70-16753-01

SUPPLIED WITH BA11-VA

AND SB11 UNITS

SCREWS FOR TABLE

TOP MOUNTING

* 7O ATTACH BRACKETS TO BA11-VA OR SB11,
MOUNT BRACKETS TO BA11-VA (SB11) FIRST.
MR-4333

Mounting Choices for the TU58-VA

SB11 OR
BA11-VA

CPU SLOT
KD11-HA

MXV11-AC

+—OPTION
SLOT

SERIAL LINE

UNIT (SLU)
——
GROUND
SCREW

(OR EQUIVALENT)

¥ ~__OPTION
4
SLOT

RS-232-C OR RS423

1/0

INTERFACE
GROUND WIRE

CONNECTOR ONLY

S
TO DC SOURCE

ON BA11-VA,

FOR EIA USE (CONSOLE)

TU58-VA

OR SB11

MR-24334

Interfacing the TU58-VA

1102

TU58
Accessories

TUS8-DB
Rackmount kit for tabletop versions

TUS8-EC

Accessory kit with detachable line cord for hardware kit (70-16753-00)

User’'s guide
Field Maintenance Print Set (MP01014)
TUSS8-ED

Accessory kit with 120V/240V detachable line cord
Fuse for 230 Vac
Two cartridges

Two 1/O cables (70-BC17A-18/BC178-18)

Boot ROM for MR11-EA

Accessory assembly hardware kit (70-16753-00)
User guide
Field Maintenance Print Set (MP01014)
TU58-VB

Accessory kit with dc power cable (70-17569-1C)
I/O cable (70-177568-1F)
Two cartridges

MXV11-A2 boot ROM

User's Guide
Field Maintenance Print Set (MP01013)

Configuration Guide

1103

TUS8

Serial Interface Standards

are listed below.
To interface with the TU58, options with their appropriate cablessignal
standards,
nced)
(unbala
RS423
and
ed)
(balanc
RS422
In accordance with
C.
RS232with
ing
the TU58 is compatible with devices comply
NOTE

BC22D-10 replaces BC17A-18 and BC17B-18. The new cable has an
improved shield connection to comply with FCC regulations.
DL11 or

5.4 m (18 ft) 10 to 40 pin connector = BC17A-18

DLV11

DLV11-J
or

MXV11
EIA

5.4 m (18 ft) 10 to 10 pin connector = BC178-18
5.4 m (50 ft) 10 to 10 pin connector = BC20M-50
1.5 m (5 ft) 10 pin to DB25S female = BC20N-05

(null modem cable)

1.5 m (5 ft) 10 pin to DB25P male = BC21B-05
(Modem cable)

TU58/PDP-11 Toggle-in Boot
This boots drive 0 only.
1000/012701
1002/176500
1004/012701
1006/176504

1010/010100
1012/005212

1050/005003

1024/005012
1026/012700
1030/000004

1052/105711

1054/100376
1056/116123

1032/005761
1034/000002

1060/000002

1036/042700

1062/022703

1014/105712

1040/000020

1064/001000

1016/100376

1042/010062

1066/101371

1020/006300

1044/000002

1070/005007

1022/001005

1046/001362

1104

1105

laquinysweNo4SOWEeNS810N|LX/D3QASINPOWSO}l SNd 12sL¢
¥4

sLXXNin--p2oOVy09P2I|[uD/L(oH-LAEn-ALd1E/QMSA|H-TOM-)1ML|DpCoeE&LE¢rdluliITéLLOsHIeaF8XTDoYRgYEdVduLAéeMObINeAVAeAXVaXiMv0/LGrqIdAgDGAdA300LS9G8‘|l02L61|1o|SLou10XV---1n/-[I|13o|isLDSS7Ii8oT7T]3nX7suAL||dL1/boMggSMds11eeiIeydni1|A4ieqgo1]WGiIj8|u0]opo3eAiSsluunwsOo1So1eei3Nusl8A]noe0jbG]syoe®(MInds40l1oiuld1B9ggs|Su88s)1x1uoi138j0l+Io8Jgo1gS89ns|X]JSd@1N31i|]sPs8NeOu]PNlON (((((ABBBBBltuuuueunniunniiyissgsssii)iiiTTT)))))(Ld|ODDODODpOiNNNAINNWau-W-N-d-eDD--0reY0VOZ9Y9D5d2028V88v229BL68o01I921Z1d48283e8-8-38-]-D-0-M-)OOM00DO0U03VVVVYV||||¥¥¥¥OXI0X€€€€1LILILL08X888LFLL076666T1LLLL00000TCOcZZ2¢c2
AAAiltteeeuuuiiiggg))) LLL1ddd|( |( |( |( OOOMWNWV---OV0NIL/-16V821Z-88L)--ZVMM8V-V
|(AAtteeuuiigg)) LLdd|( |( |( OONWW--rYV981YG92¥519043--MMVV

XION3ddV V

JILSONDVYBIuCnsViIAG3NWALITIGVTIVAY444HH

T7¥XX

pue

ansoubeiq

1106

1107

3JIaNqPuOnWp|udownedNo p°juie4LsEaXw/e0n30dmm_zhmo_i:suousbeilxq\opmuea,mfioz JSeNdedade]O10¢0s0LOZ

Zr6.NW VV-ILAHIN| VN
8¥6.LWN LAHQ d-1 ¥N

AAitreeuulilgg)) LLdd|( |( |( OOWW--AT0GO8SL08Z2338I--MMYYV
AAtteeuulligg)) LLdd|( |( |( OOWW--34.8vL5E€0866--MMUVY
rA euig) Ld|( |( OW-H34.E€VY/E3B-MV

BAteuig) Ld|( OuW-n9sSi028-MV H44HH

oOLV9vNAv6)6..LA6WW4 LALHAQXSAYWLLLg-1 e&rrLE6nl6gdLisgoTOVEéo’VNDX¢uéMNHMEdbeDZAVevMIlg&d49q1AIag9GXx|BLaSvBL]LYvi||]AXLX-/X/H0/YS9QADOMDLT33W2L|Qa41lW21LLe4I1lA0LssIae1LAl]OgH-WdA0SI|MANlYJgj-18il8gs1es18l10sj8041a180y91X4x03831X893X(8M31SI9ION1NP)OPON (((BBBuuunniiisssiiyiT7))) pDDOODuWWIN-e--ar94Ar3620S9s05YEZ280E3386Bd---00OovVVv||XS¥G¥.2||lX€€V€11LI1X888LLL1666TLLL10T00¢2cZ2c
éPX1HgXé8LiYax0dz L] XEYX/1D|3@doeLlaLlOuX]YOJlajsioduibaexiyqBINPO (BuisiT) D|N-4369£€E263-O0V|9/L €918L16L02

ON-822.8-MV | (1d Areuig)

¢ I g T 1 SNd
4T 47T MH XH XH Bunpsuien

S3|}L SINPOW L X/DdQ |S®ION| souweN 8jid awepN | Jeqwnp
q
l
e
b
u
o
s
n
o

1108

1109

e|npoy|uondopueLX/D3dansoubeiqpue sededade]OO000O

BlaquinpysweN8jidSBWeNSOION||LX/DI(CSINPOWSOIL SNudnsi d1H2sH4L4¢
Aeuig) Ld|( ON-gi263-MV
AAAtltteeeuuuiiiggg))) 1L1Lddd|( |( |( |( OOONWW-W-4-Y¥V8OS6Yr5.06886Y8V---MMMVYY
l |{ VEYB

oZvGGS66..LLINN VLOA--GLLlEEVAA-M1SI||Lé&¢Lr¢nIeE1gasvGV9oIgoa°EIaéMull¢NeAbLIvVXeOgZgaMiNGlIqrDxA4Z0||ZL|B1Gea1‘|'4‘20y2vee2eg'8‘‘6L2e1e|EvXVA/--g-0A/SlLL0MOML|3MPWAAyZaGG-8IVlI|L-11tAo0(JI1iMoO8LonWs-eA1Ss0)M0Bo1IWoubaNlebyXMyi3Jel-sgiL8osqIu11b9N08es4PSl18O1q0%0N13I88(XXM3T91S)INPON(((AAA(BiBlttBBeueueuuuuiuinnynlisilssgggisi))i)viT))))(((1LL1ddd|||p|O-DDO|OLOWuNOD0WIWNWWO-OeN2---VWW-AV90YV-42SS0S6ZYQ812L220¥1G6-8806O1030634848-VYY3---M--DMOVM0VVVVYYV||X8¥G¥G22LLXS€S¥€¥L1IIILM8888LLLL16666+LLlL.T0000cc2cZZZ
LG. LAZQ &l19g¢é6ev9DzZAanAA|222°'9922||LLAAZZQQL|vvoyaaouulgitpuYYdedousuA|Aqsyye]XXNNIsWWej2L44O0¢¢ (BuinisiTT) DAN-VVIL8V.EP8BEYY-ODV|66SGGILI8L6L102c

1110

e|npon|uondQopueLIX/D30Qonsoubeiqpue Jededade]O0O0O

1111

I3aIqNupIonnWNuBoWnedNoQp8juiedLsEaXw/e2n30SOION|oIXn/sDoN3uQbPeLiIqOpueWS3|}L JSaNdedade]oL020s0LO¢
AAlteeuuilgg))(LLdd |( OONWW--0v¥98946-3MV-|MV
AAreeuuillgg)) 1LLdd|( |( |( OOWW--F8YO2¥L50Z1L393--MMVY
i 1 |( E£6 V

ééAdaxrdo Ad |L 3INPON AAtteeuuiigg)) LL1dd|( |( |( OOMNVWW--4V8vSY50S86L-EM-V

o¥

o9O0812I0N08L8WI1 E3EXA-Ad1N-LMALXT-AVQ1dY-A|ELMeLLrLnegIE8vVsNoGvA0YAo'TE°dNuM¢4AHAbUeAéVNZXVevNTGiLg1LIrqaHGgAxX0Y‘|L1PSqal9¥rty67|L||v8|2oLAXL[0d/YQA/elND1uM3L0LsTVdLo3|V-1EoLtLd1A-1uT1i€aYL1obI7/lAsSdTuNe82-)MLn041i9J(d8HVASq1sY/NOos1-LMg8noO]siJToe8xnHus3sib/doeIBJulaI8bqXNse3P1i0OgS4WeIxN3POW((A(BBtBuueuinnunlssiiligssvi)ynii)))(Ld|ODODOpB(NNIWNWWu--N-e-nIVV9A9VrsS4E0S2268i6Y9060£SE.16VL0BlHY9333SY----MO000OUVVVV|||98LS¥XH| L9¥X€4€vI1LII88X48LLL66641TLLL000TH22C
208N vEEHIN6ELVVDIHWNWDAAZ4LIF|9vV'aBbY|+1¥12S-OIe8-SW0Ts9M1W0YiA1HI-O-d0WWBOiNHW4JPaANxLXAHW3)(M(9v1a)-L1sel(Bbunsiy) ODN-4S0EYSS08I6E-0ODVY|8¥2|S€I8L6L02

1112

1113

aO19NW°a¢AN¢A19" LAWGL|TaHulLiyIOnyWund1dosnlosisuobuebiegqigq'O'"NON¢Z|

808 O-L AHWN |YN

AAttreeuullgg)) 11Ldd|( |( |( OOWW--Vd4Y¥88YS80963--MMVV
Ateuig) Ld|( |( OW-F4O8L7036-NMVYV
Adeuig) 1Ld|( |( OFLWM-IVY0N9LG.-4VMv

Bunsi HH 44H

aJ/G6€|aY07GPNqO80P0uO8Nn8Wn|uXarLVoA-wAS1-nNeWELLdGNEAoHXLA3ASI-W1N|/op¢eE4r&junEV1LgiVes9I04OIDoXNN¢HLuISiGeAbDMN8QvZAeXAwH1i/1LeA1qaD9pGn9Ix3Q||B6a8S86¥OyYY%||ION||/-oAEA9XX0HpHAS//WQAsXDOD2MIoL3pW3LLuZMdQr-Nb9X|Yl8-v4e11LT-A0i1LPHLlo0oIq1oLnuO-Wdssp@OO0SloouBWiIuueLMsNWbbpooJ2eeulJZ8Piib19sqqoesSIsl1o8oqM9u1[0sasSbJe}a1exd9L]0x3iJ1g3sl89ae"X(9O]3MdIN9N1¢|P|)O (((ABBblBueuuiunnnsssgtiii)TTv)))(Ld|LDODJpSINWWauNN-d-ed-VVer4VBYd60Sv9S90t5¥S.a80.Z9d348643e---]O0MO0DVVV|88S¥oX|21|LlSSOX¥¢G€IIl1LL80Ms88LLL606T6LLL1L000O¢TcZ2ZZ

1114

1115

OW-VEYYS-MY

AAteeuuliigg)) LL1dd|( |( |( |( OONWW--r8DD8EEGvV92/4I3--MMvYVV
4-HY OW-090Y

OONWW--V4I¥EGP8S--MMVY

AAlteeuuliigg)) 1LLdd|( |( |( OO44W--MWM-VV9-0O1vW02-409-6ME€V1

Bunsi HH 4 44H

°J988[oNN0nqN988upNon11wy|uSL14o4AWdn0SendXWNdQbV1d-1L JpsV&eEér.1djnuVl9Sa4léeiYse°gvX0dW8agIo¢0éd°dNAeué6LSaA4¢ObiaeaEZ6aréeXdrLv6XwiV4ngga/qLrred11g99rDa9GNOr30XQS0LSG®||ION||sS4LX14NS/n303/OD14MAsH4D3IWoO30||II1uWaA-yBNXNvbNLa0vddeLL1--iMX1|L11PIodq82llSd1oO2ioil01nlOpl3ssn80is1uLoos1S1Joeuuo888Wubbxu2s1eeb3tb180iieds0eqqoi1S1idll0q8Oq""eX1OOx8}3s"NN'3XlO8OTN]N¢F|8|ClS9NIPNOPWONW (((BBBuuunnnsssiiivvyy))) OODp|OLOJSODNuaWNWNWWW-WNde---Da--D004VIr9VHd2SY80SPvZ095ELzvrYav8LYe4vId4834SSIe-----0-]D0DoO0OOODVVvVVVV|SOX661I||0X2¥€€LIII0SM888LLL0766L6TL1L100O0T¢¢zc

0Z 61 8L ¥I S |DW-D2ZV.3-OV

pue

c L s 7 1 SNd
T 7T M X X

(Bunsi)

X/03d
L 1dd L1ex3
a|NpO J8sioi

ra0 ¢évddx

S|l SINPOW L X/D3Q |SOION| Sauwen 8jid sweN | Jaqunp

snsoubeiq

1116

1117

al|qnupionpwnuawoinepdNopajuiedLsawXie/nDN3QSION|aS/isDIo3uNbXeLiIPqpOueWSO}l iSsNdeyade]o8020g0LO¢
AA1ttdee/uuli2gg0))Q)LLdd|( |( OOaNyW---V8gZv28Le1.r6Lz318--MMVY
Ateuig) Ld|( OW-98Y06-MY

Bunsiy 44HHH
/At0euQlg)) Ld|( OW-ga¥y2-603s-eMrVzv

or909A20N900eY)98VY1 LLDAA-QXVL1YYLAVDVQ--Y11 éL6LrXnELEa¢sVEYvi0XYVoVOaéXVvuVYvYbAAAaeY0iag11rq99vLgx0€Ll2 LLXLXAAA//VQVX0DYYY33aaLD|L-LLsoo11dlnuisoLLesonAuAouslubVQoIbeYYuOelboqLLelqgJJai88d11qSss11aa10]0]ss44e8a8]]XXT3SBIINNPPOONW (((ABBBeuuunnniissgsi)iiy)))(1d||p||OOJ2uWWoe-NW0--99VO€./B¥219.166L18338---M00O0VYVV8X|I X¥S€¥IILLLM888LLL166671LLL000T¢¢Z2cc
Q£/€25H EANINL| DINADNZL¢1Gg|Bavy /-0SOMbNZ18L1A0IDdOuW-0BIMNg1lesg1i80iS1a0x138(XM391) (ABlueinlsgi)yv)(Ld||ODOW-N4-¥04S8P086M-0YV+2L€I18L6L102

- Notes

tor 70-

Wraparound test and auto-tests require Berg test connec
12894-00.

Requires an analog ground on any channel to be tested.
system. If run
May be run asynchronously if KWV 11 is present incted
from the
asynchronously, XKWE??.0BJ must be desele
DEC/X11 run.

4a.

ite.
Memory space under test should be contiguous and read/wr
For systems having noncontiguous memory, the memory boundm.

aries must be defined by the operator before running the progra
This diagnostic requires 8K of memory space to run in.
4b.

This test will run successfully only on an 11/23 processor with a
minimum of 16K of memory.

LTC must be disabled.

VKAA??.BI? and VKAD??.BI? should be run on the CPU prior to
running this test.

Scratch media must be mounted in drives to be tested before

starting the diagnostic.

ZRKJ??.BI?, ZRKK??.BI?, ZRKL??.BIl?, and ZRKI??.BI? (if needed)
should be run on subsystem before running this test.

7RKJ?7.BI? should be run on the sybsystem before running this
test.

7RKJ??.BlI? and ZRKK??.BI? should be run on the subsystem be-

fore running this test.
11a.

A wraparound test connector must be installed to run this test.
The connector is not available from stock. The F.E. must make
one up himself. The following instructions (excerpted from Tech
Tip PDP-11/03 TT-11) tell how this is done. The following items
are required:

1 Berg connector
4 Berg pins
#22 wire

(12-10918-15)
(12-10089-07)
(90-07350-00).

Crimp a short length of wire between two Berg pins. Make up two
sets of these. Install one set from pin F to pin J, and one set from
pin E to pin M of the Berg connector.
1118

11b.

To completely exercise the modem control portion of the DLV 11E, a special wraparound connector (H315) must be installed on

the modem end of the I/F cable. This test connector loops back
certain control lines as well as the data lines.
12.

The test has baud rate dependent configuration requirements.

Baud Rate

No. of Stop Bits

110

All others

No. of Bits

Requires BCO8R test cable for full test of module’s data lines.
14.

ZRXB??.BI? should be run on the subsystem before running this
test.

15.

a REV11

is in the system, DMA refresh must be disabled and

CPU refresh must be enabled.
16.

17.

H315A connector required for external loopback testing.
If customer hardware is connected to the
ject

signals

ST1,

ST2

slave

KWV 11 which could ininputs,

must

dis-

connected from the inputs.

All switches in switch pack 2 should be left off unless you are instructed otherwise.

1/O signal test no. 1 (ST1 in, ST2 out); install a jumper between

J1-SS (ST2 out) to J1-VV (ST1 in).

Switch Pack 2
Switch
~NO
O
WN -

19.

State
Off
On
Off

Off
On

On
Not used.

Use a program starting address of 210.

1119

20.

|/O signal test no. 2 (clock overflow tests); install a jumper

tween J1-RR (clock overflow) to J1-TT (ST2 in).

be-

Switch

State

~NOoO
Ok W
-

Switch Pack 2

Off
Off
Off
On
Off

Not used.

Use a program starting address of 214.
21.

/O signal test no. 3 (ST1 out, ST2 in); install a jumper betwe
J1-UU (ST1 out) to J1-TT (ST2 in).

Switch

State

~NOO
O s WN =

Switch Pack 2

Off

Off
Off

On
On

Not used.

Use a program starting address of 220.
22.

Test may be run with a ““‘known good module’ in the system for
comparison. The good module should be located second (electrically) on the bus, with a cable connecting it and the module under test.

“known good module’’ address - 760160
“known good module’’ vector - 660
23.

Starting restrictions:

If a free-running clock, such as 60 Hz from the power supply, is
attached to the BEVNT bus line on REV C/D/E systems, an interrupt to location 100 will occur when using the ODT “G” and “‘L”
commands. This will happen prior to the program executing the
first instruction. This program cannot disable the BEVNT bus line
by inhibiting interrupts.

1120

User systems requiring a free-running clock attached to the

BEVNT bus line can temporarily avoid this situation by setting the
PSW to 200, loading the PC with the starting address, and then
using the ‘P’ command, instead of using the starting address and
the “G”’ command.

Before using the “‘L”’ command, the PSW can be set to 200 to inhibit interrupts after loading the absolute loader.

24.

Possible program bombs:

The first two tests check to see if the IBV11-A responds to the address the program thinks it is at. If not, a bus error occurs.

Bus errors may alter the preset contents of location 4 before the
trap is executed. Program control may be transferred to an area of
the program which is not set up to handle the trap. Or, control may
be passed to some totally unknown and irrelevant piece of code

residing accidently in memory. If this occurs, the program will

most probably bomb, and it may also overwrite parts of itself. If this
occurs, the program must be reloaded before proceeding.

25.

If the IB-bus cable is not removed from the module under test, any

errors which are detected could be from some device out on the
IB-bus and not necessarily from the IBV11-A.

26.

27.

If run in staggered maintenance mode, an H329 staggered turn-

around connector is required.

If run in external maintenance mode, an H325 cable turn-around
connector is required on all lines which have been selected to be
tested.

28.

This test assumes that the module under test resides in the same
backplane where the line time clock is generated.

29.

Test 3 assumes that switch no. 5 of E21 is in the ON position.

30.

For the rocker switch test, the operator should specify the con-

31.

figuration for the module under test.

VRLA??.BI? should be run on the subsystem before running this
test.

32.

33.

VRLA??.BI? and ZRLG??.BI? should be run on the subsystem be-

fore running this test.

A KWV 11 programmable line clock is required to run test no. 7.
1121

34.

VRLA?2.BI?, ZRLG??.BI?, and ZRLH??.BI? should be run on the

subsystem before running this test.

35.

A KWV 11 programmable line clock is required for some tests.

36.

VRLA??.BI?, ZRLG??.BI?, ZRLH??.BI?, and ZRLI??.BI? should be

37.

VRLA??.BI?, ZRLG??.BI?, ZRLH??.BI?, ZRLI??.BI?, ZRLJ?7?.BI?,

run on the subsystem before running this test.

and ZRLN?7.BI? should be run on the subsystem before running

this test.
38.

VRLA??.BI?, ZRLG??.BI?, ZRLH??.BI?, ZRLI??.BI?, ZRLJ??.BI?,
ZRLK??.Bl, and ZRLN??.BI? should be run on the subsystem be-

fore running this test.
39.

VRLA??.BI?, ZRLG?7?.BI?, ZRLH??.BI?, ZRLI??.BI?, and ZRLJ?7?.BI?

40.

A KWV 11 programmable line clock is required for tests 1 and 4.

41.

should be run on the subsystem before running this test.

To check the power fail circuitry, nonvolatile memory must be in
the first 4K of memory.

42.

Power up option no. 1 should be selected on the CPU module for
power fail testing.

43.

The module should be in the standard factory configuration.
jumpers in:
jumpers out:

44.

45.

15
Wi1-W5, W7, W8, W11, W13-W
W6, W9, W10, W12

If the test is to be run in all address modes, then an extender card
and a special test cable (17-00124-01) are required.
The exerciser may be run with the module in address modes 1 or 3
only.

46.

This test may be run only if RAM is present on the board.

47.

All channels must be configured to the same bit-word length.

48.

A wraparound connector (H3270) is required for
wraparound tests for each of the lines to be tested.

49.

Requires a BCO5W-02 cable to be installed between the Berg connectors. The cable should have a half twist in it.

1122

the

data

50.

JKDB??.Bl? should be run on the first 16K of memory before running this test.

51.

JKDC?7.BI? should be run on the module before running this test.

1123

‘
u
o
l
j
e
l
u
a
w
‘
u
o
l
e
l
u
s
w
S9]0N
1124

APPENDIX B

FLOATING ADDRESSES / VECTORS
FLOATING ADDRESSES

The conventions for the assignment of floating addresses for modules on

the LSI-11 bus are the same as UNIBUS devices. UNIBUS devices are used
to explain the ranking sequence.

The floating-address convention used for communications and for other devices that interface with the PDP-11 series of products assigns addresses
sequentially starting at 760 010 (or 160 010) and proceeds upward to 763
776 (or 163 776). For the sake of compatibility with UNIBUS conventions,

addresses are expressed as consisting of 18 bits (7XX XXX) rather than 16
bits (1XX XXX).

Floating addresses are assigned in the following sequence.

OO O~NOOOPE
WN =

P—N

Rank

LSil-11
Device

UNIBUS
Device
DJ11

DH11

DQ11

DUV 11

DU11
DUP 11

LK11A

DMC 11

DZV 11

DZ11
KMC11

11 (extras)
RLV

RL11 (extras)

FLOATING VECTORS

The conventions for the assignments of floating vectors for modules on the
LSI-11 bus will adhere to those established for UNIBUS devices. UNIBUS
devices are used to explain the priority ranking for floating vectors and are
included in the subsequent table of trap and interrupt vectors as a guide for
the user.

The floating-vector convention used for communications and for devices

that interface with the PDP-11 series of products assigns vectors sequen-

tially starting at 300 and proceeding upward to 777. (Some LSI-11 bus
modules, such as the DLV11 and DRV 11, have an upper vector limit of
377.) The following table shows the sequence for assigning vectors to modules. It can be seen that the first vector address, 300, is assigned to the
first DLV11 in the system. If another DLV 11 is used, it would then be assigned to all the DLV 11s (up to a maximum of 32); addresses are then as-

signed consecutively to each unit of the next highest-ranked device

(DRV11 or DLV11-E, and so forth), then to the other devices according to

their rank.

1125

Ranking for Floating Vectors

(Start at 300 and proceed upward.)

Rank

UNIBUS

LSI-11 Bus

DC11

DLV, -F, -J

3
4
5

DP11
DM11-A
DN11

KL11, DL11-A, -B

DM11-BB

9
10

PA611 Reader
PA611 Punch

7
8

11
12

DT11
DX11

DJ11

15
16
17
18

DH11
GT40
LPS11
DQ11

19
20

DRV11-B
DRV 11

DR11-A
DR11-C

pDL11-C, -D, -E

DLV11-E

KWV 11
DUV 11

KW11-W
DU11

1126

APPENDIX C

LSI-11 BUS SPECIFICATION

GENERAL
NOTE

This is not the complete LSI-11 bus specification, but is included to
permit users to design and implement typical interfaces to the LSI-11
bus.

The processor, memory, and I/O devices communicate via 38 bidirectional signal
lines that constitute the LSI-11 bus. Addresses, data, and control information are
sent along these signal lines, some of which contain time-multiplexed information.
The lines are functionally divided as follows:

Data/address lines - BDAL<17:00>

Data transfer control lines - BBS7, BDIN, BDOUT, BRPLY, BSYNC,

BWTBT

3
6
5

Direct memory access control lines - BDMG, BDMR, BSACK
Interrupt control lines - BEVNT, BIAK, BIRQ4, BIRQ5, BIRQ6, BIRQ7
System control lines - BDCOK, BHALT, BINIT, BPOK, BREF

Most LSI-11 bus signals are bidirectional and use terminations for a negated (high)

signal level. Devices connect to these lines via high-impedance bus receivers and
open collector drivers. The asserted state is produced when a bus driver asserts
the line low. Although bidirectional lines are electrically bidirectional (any point
along the line can be driven or received), certain lines are functionally unidirectional. These lines communicate to or from a bus master (or signal source), but not
both. Interrupt acknowledge (BIACK) and direct memory access grant (BDMG)
signals are physically unidirectional in a daisy-chain fashion. These signals start at
the processor output signal pins. Each is received on device input pins (BIAKI or
BDMGI) and conditionally retransmitted via device output pins (BIAKI or BDMGI)
and conditionally retransmitted via device output pins (BIAKO or BDMGO). These
signals are received from higher priority devices and are retransmitted to lower
priority devices along the bus.

1127

Master/Slave Relationship

Communication between devices on the bus is asynchronous. A master/slave

relationship exists throughout each bus transaction. At any time, there is one

device that has control of the bus. This controlling device is called the “‘bus
master.”” The master device controls the bus when communicating with another
device on the bus, called the slave. The bus master (typically the processor or a

DMA device) initiates a bus transaction. The slave device responds by acknowledging the transaction in progress and by receiving data from, or transmitting data
to, the bus master. LSI-11 bus control signals transmitted or received by the bus
master or bus slave device must complete the sequence according to bus
protocol.

The processor controls bus arbitration (i.e., who becomes bus master at any given
time). A typical example of this relationship is the processor, as master, fetching
an instruction from memory (which is always a slave). Another example is a disk,
as master, transferring data to memory as slave. Theoretically, any device can be
master or slave, depending on the circumstances. Communication on the LSI-11
bus is interlocked so that for each control signal issued by the master device,
there must be a response from the slave in order to complete the transfer. It is this

master/slave signal protocol that makes the LSI-11 bus asynchronous. The asynchronous operation precludes the need for synchronizing with clock pulses.

Since bus cycle completion by the bus master requires response from the slave
device, each bus master must include a timeout error circuit that will abort the bus
cycle if the slave device does not respond to the bus transaction within 10
microseconds.

The actual time before a timeout error occurs must be longer than the reply time of
the slowest peripheral or memory device on the bus.

The signals and pin assignments are tabulated as shown below. The pin nomenclature is for reference and is only required when examining DIGITAL modules and
circuit schematics. A functional description of the LSI-11 bus pins and signals is
also found below.

1128

Categories of LSI-11 Bus Signal Lines
Number Functional

DIGITAL’s

(Name)

of Pins