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EK-KXJCA-IN-001

December 1986

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Document:	KXJ11-CA Single-Board Computer Installation Guide
Order Number:	EK-KXJCA-IN
Revision:	001
Pages:	52
Original Filename:

OCR Text

EK-KXJCA-IN-001

KXJ11-CA

Single-Board Computer
Installation Guide

EK-KXJCA-IN-004

KXJ11-CA
Single-Board Computer
Installation Guide

Prepared by Educational Services

of Digital Equipment Corporation

1st Edition, December 1986

Printed in U.S.A.

The reproduction of this material, in part or whole, is strictly prohibited. For
copy
information, contact the Educational Services Department,
Digital Equipment
Corporation, Marlboro, Massachusetts 01752.
The

information in this document is subject to change without notice. Digital
Equipment Corporation assumes no responsibility for any errors that may appear
in
this document.
The

following

are

trademarks

Digital

Equipment

Massachusetts 01754.

Corporation,

dlilolilt/al1 |

KA630

DEC

Q-Bus

MASSBUS

VAX

Rainbow

DECmate

VAXELN

MicroVAX

RSTS

DECUS

VMS

PDP

RSX

Work Processor

DECwriter

P/OS

DIBOL

Professional

UNIBUS

Maynard,

Contents

Chapter 1 — Introduction. . . . . ..........
... ... ... .......

1-1

Chapter 2 — Selecting Operating Features . . . .. . ............

2-1

2.1 Boot/Self-Test Switch. . . . . ... ... ... .

2-3

2.2Q-BusSize . . . . ...
e e
e

2-8

2.3 Q-Bus Base Address Selection . . . . ... ... ... ...

2-9

24DMARequests. . . . . . ...

. .

210 SLULBaud Rate.

. . . . . . .

... .. . .. .

2.8 Power-Up Option Selection . . . ... ... ...
i i

e e

...

i it

v
e

. 2-13

... 2-14

2. 11 SLUl Transmitter. . . . . . . . . oo v v i i i

e 2-11

.. .. ... 2-12

2.6 BREAK Enable Selection . . ... .... ... .. ...

29 PROM Addressing . . . . .. .. . .

2.5 Locked Instruction Enable. . . . ... ... ...
2.7HALT Option Selection . . . ... ... ...

.. 2-15

e 2-16

e e 2-17

i e .. 2-19

2.12SLUL Receiver.

. . . v v v v it et e e e

2.13 SLU2 Channel

AReceiver . . . . . .. . . . it 2-21

e 2-20

2.14 SLU2 Channel B Transmitter . . . . ... ... ... ... ... 2-22

2.15SLU2Channel

BReceiver . . . . .. .. ... ... . ...

2.16 Real-Time Clock Interrupt . . . . . .. ...

2-24

.. i 2-25

Chapter 3 — Power Supply Considerations . . .. ..............

3-1

.
. . . .. ...

4-1

4.1 Edge Connector Pin Assignments . . . . ............
... .......

4-3

Chapter 5 — Connectors and External Cabling . . . .. ..........

5.1 Parallel I/O Interface (J4) . . . . .. .. .. . . . e
5.2 Serial /O Lines (J1,J2,J3) . . . . . . . o e
5.3 Loopback Connectors. . . . . . ... .. . i i e

5-1

5-2

Chapter 6 — Diagnostics . . .. .............
... ... ... ...,
.. ...
6.1 Error Detection and Reporting withthe LEDs . . . . . ... ......
...
....
6.2 Diagnostic Testing with XXDP+. . . . . ... ............

6-1
6-1

Chapter 4 — Installing the KXJ11-CA in a Backplane.

5-8

6-3

Figures
2-1 KXJ11-CAJumper Layout. . . . . .. ... ... . ..

2-1

2-2 Memory Mapping — PROMinLowMemory.

. . . . ... ... .........

2-3

2-3 Memory Mapping — PROM in HighMemory

...................

2-4

2-4 Boot/Self-Test Switch.

. . . . . ... ... ... .

2-5

2-6 Q-Bus Size Selection . . . ... ... ... e

2-8

2-6 Q-Bus Base Address Selection
2-TDMA Requests.

. . ..

. . .. ... ... ... .. ... . . . . .. ..., 2-10

. . . . . . . o i i it ittt

e e

e 2-11

2-8 Locked Instruction Enable. . . . . ... .. ... ... ... ..., 2-12
229 BREAKEnable . . . ... ... .. . . ..
2-10 HALT Option Selection. . . . .. e
2-11 Power-Up Option Selection.

e e e e

e 2-13
e 2-14

. . . ... ... ... ... ... . .. ...

2-12PROM Addressing. . . . . . . . . ...

... 2-15

i e 2-16

2-13SLUl1Baud Rate.

. . . . ... ... ..

2-14 SLUL Transmitter.

. . . . . . .. .

e e 2-19

2-17

2-15 SLUL Receiver.

. . . . . . o

2-16 SLU2 Channel

AReceiver . . . . . .. ... ... . ... 2-21

e e s e

2-17 SLU2 Channel B Transmitter . . . ... ... ... ...

e 2-20

...

.. . ..... 2-23

2-19 Real-Time Clock Interrupt . . . . . . .. ... ... ... . . ..

... 2-25

2-18 SLU2 Channel

BReceiver . . . . . .. .. .. . .. . . ..

4-1 Backplane Installation . . . .. ... ... ... ... ...

2-24.
. . . ... . . . ...

4-1

4-2Using Grant Cards . . . . ...... . ... . . . . .. e

4-2

6-1 Parallel 1/O Interface Pin Assignments . . . . ... ... .............

5-1

5-2 J2 and J3 Pin Assignments (10-Pin) . . . . ... ... ... .. ... . ... ...

5-3

5-3 J1 Pin Assignments (40-Pin). . . .. .. ... ... ... ... ...,e

5-3

5-4 Loopback Connectors.

. . . ... ... ... .. . . .. ... ...

5-8

2-1 Factory Shipped Jumper Configuration . . . .. ... ...............

2-2

2-2 Boot/Self-Test Switch Functions . . . . ... ... .................

2-5

2-3 Q-Bus Base Address Selection

2-9

Tables

. . . ... ........
.. .. .. ... ..
..

2-4 SLU1 Baud Rate Jumpering. . . . ... ... .. ... ... .

4-1 KXJ11-CA Pin Identification . . . . ... ... ... ... ... ...

... 2-18
......

4-3

5-1 RS422/RS423 InterfacetoJ1 . . . . .. .. .. .. . . ... . . . .

5-4

5-2 RS232-C InterfacetoJ1 . . . . .........
... ... ... ... .
...

5-6

5-3 CCITT/V.35 InterfacetoJ1 . . . . ... ... ... ... .. . . .. ... .. ...

5-7

6-1 LED Display Definitions . . . . .. ... ... .. ... ... ... .. .. .....

6-2

Chapter 1
Introduction

This guide describes how to install the KXJ11-CA module.
NOTE

Before changing the factory shipped jumper configuration, make
sure the jumpers match the jumpers shown in Figure 2-1, and ver-

ify that the module is operating as described in Section 6.2.
Installation includes the following activities.
1.

Selecting

operating

characteristics

and

installing

appropriate

jumpers

(Chapter 2)
2.

Determining power supply requirements (Chapter 3)

Installing the board into a backplane (Chapter 4)

Selecting and connecting cables from serial and parallel I/O interfaces to
external devices (Chapter 5)

Verifying proper operation {Chapter 6)

Chapter 2
Selecting Operating Features

Several characteristics of the KXJ11-CA are defined by jumper settings. This section
describes the characteristics that are part of the factory-shipped configuration. It also
shows how to change these characteristics by changing the appropriate jumpers.
Figure 2-1 illustrates the factory-shipped jumper settings. Table 2-1 summarizes the

meaning of each jumper setting. The sections that follow describe the various jumper

setting alternatives available.

M47

M48

M34[0_o]Mm33
mM32[0
o |M31

MB0[0_ o]M59 © M54
M53

M1 rvnolms M7

M30{ o]m29
M44 o o M43 M28[o o|M27
M42 M41 M26[ 0o |m25
M40
M39 M24
M23

PIO

SLU2

SLu2

CHANNEL B

CHANNEL A

X der]
[Sojo

BOOT/SELFTEST
M12

M13

1D SWITCH
o o

[c
o]
(S
o]

&
el

EI o5

SWITCH

XIS

[o.of

[oo]

]

M17

]

MI16

M4 M6
M2

M15

HIGH BYTE

PROM

M8 o

LOW BYTE
!

Mig8o

PROM

M46 i

oo Dc‘/
Ealo

M85
}

M64 | M66|

[oxe)

1
Figure 2-1

KXJ11-CA Jumper Layout

2-1

]

M3¥

M38

§
¢

o—M35

M36

/ Mas M5 C\Mdg
M50

Table 2-1

Factory Shipped Jumper Configuration

Function

Setting

Jumpers Installed

Q-Bus Size

22 bits

M3 to M4

M5 to M6

Q-Bus Base Address
iD Switch Position

17760240

M1 to M2

DMA Requests

SLU2 Channel A Receiver

Enabled

M10 to M11

8036 Counter/Timer

Disabled

SLU2 Channel A Transmitter

Enabled

M7 to M8

Locked Instruction Enable

Disabled

Mé65 to M66

BREAK Enable

Enabled

M12 to M13

HALT Option Selection

MicroODT

M14 to M15

Power-Up Option Selection

Firmware

No jumper

PROM Addressing

15-bit

No jumper

SLU1 Baud Rate

9600

M56 to M55

M60 to M59
SLU1 Transmitter

RS423

M62 to M61

SLU1 Receiver

RS423

No jumper

SLU2 Channel A Receiver

RS422

M34 to M33
M32 to M31

M30 to M29

M28 to M27
M26 to M25
M24 to M23
SLU2 Channel B Transmitter

RS422

M38 to M36
M51 to M50

SLU2 Channel B Receiver

RS422

M42 to M41
M40 to M39

M20 to M21

Real-Time Clock Interrupt

60 Hz

Boot/Self-Test Switch Position

M52 to M53

NOTE

The SLU2 Channel A Transmitter is not configured with jumpers,
but is configured by selecting appropriate signals on connector J1.

2-2

2.1 Boot/Self-Test Switch
The boot/self-test switch is a 16-position switch that is used if the board is configured
to execute firmware (rather than MicroODT) upon power-up. It has three functions.
1.

It determines how the KXJ11-CA will act when a special interrupt condition

exists, including whether or not self-tests will run (see Section 3.5,
KXJ11-CA Single-Board Computer User’s Guide, EK-KDJCA-UG-001).
2.

The

It determines whether special interrupt handling is performed either by

user code or by firmware.
3.

It determines where in memory the on-board PROM is mapped. There are
two alternatives — low memory or high memory. The memory maps associ-

ated with low and high PROM mapping are shown in Figures 2-2 and 2-3,
respectively.

17777777

T‘

17774000

17773777

POWER UP

‘

17773000

1/0 PAGE

17772777

17770000
17767777

MONITOR AND
DIAGNOSTICS

17760000

17757777

Pand

NXM

Vand

’

2200000
2177777

2174000

2173777

2173000

POWER UP

2172777

NATIVE
FIRMWARE

2170000

2167777

MONITOR AND
DIAGNOSTICS

2160000
2157777
USER PROM

2000000
1777777
RAM
77777

0 §PRO[W/RAM SPACE w
* ADDRESSES 77777-0 MATCH ADDRESSES 2077777-2000000
MVIR-17263

Figure 2-2

Memory Mapping — PROM in Low Memory

17777777

17774000
17773777

POWER UP

17773000

1/0 PAGE

17772777

17770000

17767777

MONITOR AND
DIAGNOSTICS

17760000

17757777

NXM

2200000

2177777

2174000
2173777
2173000

POWER UP
NATIVE

2172777

FIRMWARE

2170000
2167777

MONITOR AND
DIAGNOSTICS

2160000

2157777

USER PROM
2000000

1777777

RAM

MR-17262

Figure 2-3

Memory Mapping —

PROM in High Memory

2-4

The location of the boot/self-test switch is shown in Figure 2-4. Table 2-2 summarizes

the functions associated with each switch position.

S
BOOT/SELFTEST SWITCH
\

—.

1
Figure 2-4

Table 2-2

]

MR-16215

Boot/Self-Test Switch

Boot/Self-Test Switch Functions

Special
Switch

KXJ11-CA

Interrupt

PROM

Position

Special Interrupt Response

Handling

Mapping

User PROM application code is

Firmware

Low

Firmware

Low

executed. No self-tests are
performed.
1

User PROM application code is

executed. Auto self-tests are
performed.

2-5

Table 2-2

Boot/Self-Test Switch Functions (Cont)
Special

Switch

KXJ11-CA

Interrupt

PROM

Position

Special Interrupt Response

Handling

Mapping

User PROM application code is
executed. Auto self-tests are
performed. The user (P)PROM
checksum test is also performed.

Firmware

Low

Application code is booted from
a TU58 via SLU1. Auto self-tests

Firmware

High

Firmware

High

Firmware

High

Firmware

High

None

High

User Code

Low

User Code

Low

User Code

Low

User Code

High

User Code

High

are performed, then the TU58
primary bootstrap is executed.

MicroODT is entered. No self-tests

are performed.

Auto self-tests are performed.
The KXJ11-CA awaits command from
the arbiter via TPRO.

No self-tests are performed.
The KXJ11-CA awaits a command
from the arbiter via TPRO.

Auto self-tests are performed
continuously. No application
code is booted or executed.
Loopback connectors (see

Section 5.3) are installed
for these tests.

User PROM application code is
executed. No self-tests are
performed.

User PROM application code is
executed. Auto self-tests are
performed.
10

User PROM application code is
executed. Auto self-tests are
performed. The user (P)ROM
checksum test is also performed.

Application code is booted from

a TU58 via SLUL. Auto self-tests
are performed, then the TU58

primary bootstrap is executed.
12

MicroODT is entered. No self-tests
are performed

2-6

Table 2-2

Boot/Self-Test Switch Functions (Cont)

Special
Switch

KXJ11-CA

Interrupt

PROM

Position

Special Interrupt Response

Handling

Mapping

Auto self-tests are performed.

User Code

High

User Code

High

None

High

The KXJ11-CA awaits a command
from the arbiter via TPRO.
14

No self-tests are performed.

The KXJ11-CA awaits a command

from the arbiter via TPRO.
15

Auto self-tests are performed

continuously. No application

code is booted or executed.

Loopback connectors (see

Section 5.3) are installed
for these tests.
NOTES

Switch position 5 is the factory-shipped configuration.

The encoded value of the boot/self-test switch position is available in the KXJCSRB register in bits
switch position

<7:4>. For example,

1 would be encoded as

0001

KXJCSRB

<T:4>.

The user (P)ROM checksum test looks for a checksum at the
highest word address of user (P)ROM. Similarly, the firmware
checksum test looks for a checksum at the highest word address of the firmware PROM. Either checksum is calculated
and checked according to the following DECPROM algorithm:
CHECKSUM = 0
FOR I = number of PROM addresses to be checksumed

DO CHECKSUM = CHECKSUM + contents of address
(high order carry from addition is discarded)

CHECKSUM

ROTATE_LEFT
ONE _BIT

(bit0 —>

bitl,

bitl —> bit2, .... ,bit15
— bit0) NEXT I
4.

Special interrupt handling can be performed by user code in

switch positions 8-15. This function is useful in applications
that need to continue running after the Q-Bus signal BHALT

or the Q-Bus signal BINIT has been asserted. For switch positions

through

special

interrupt

handling

done

firmware.

If the KXJ11-CA is in standalone mode, switch positions 5, 6,
13, and 14 should not be used. These positions cause the
KXJ11-CA to idle and wait for a command.

In standalone

mode, the KXJ11-CA will idle indefinitely, waiting for an arbiter command that will never come.

2-7

2.2 Q-Bus Size
The KXJ11-CA may be configured to handle 16-, 18-, or 22-bit Q-Bus addressing. This
is accomplished with the Q-Bus size jumpers (see Figure 2-5). 22-bit addressing is selected as part of the factory-shipped configuration.
Jumper Connection

Description

22-bit addressing selected*

M5
M6

18-bit addressing selected

16-bit addressing selected

.....

1
Figure 2-5

]

e o

Q-Bus Size Selection

* Factory-shipped configuration

2-8

[

MR-16216

2.3 Q-Bus Base Address Selection
In systems with multiple I/O processor boards, make sure each board has a unique

Q-Bus base address to distinguish the boards from one another. This is accomplished
on the KXJ11-CA by setting the ID switch and installing or removing a jumper which

connects M1 and M2.
Table 2-3 lists the base addresses that can be selected. Table 2-3 lists 22-bit addresses.
If the KXJ11-CA is configured for 16- or 18-bit addressing, use the lower 16 or 18 bits

of the addresses specified in Table 2-3.

Table 2-3

Q-Bus Base Address Selection

ID Switch Position

Base Address

(Jumper IN)

(Jumper OUT)

17760100

17762100

17760140

17762140

17760200

17762200

177602404

17762240

17760300

17762300

17760340

17762340

17775400

17777400

17775440

17777440

17775500

17777500

17775540

17777540

17775600

17777600

17775640

17777640

17775700

17777700

17775740

17777740

* These switch positions disable the Q-Bus interface. That is, the KXJ11-CA is running in standalone mode.

}

Factory-shipped configuration

2-9

Figure 2-6 shows the locations of jumper connections M1 and M2, and the ID switch.
The factory-shipped base address is 17760240.
Jumper Connection

Description

Factory-shipped configuration

Base address = 17760240

®/

S
1D SWITCH

o M1
o M2

]
]

1
Figure 2-6

]

Q-Bus Base Address Selection

2-10

MR-16217

2.4 DMA Requests
DMA requests to the on-board DMA transfer controller (DTC) may come from several

sources. The KXJ11-CA has a set of jumpers that enable or disable DMA requests
from: (1) the SLU2 channel A receiver, (2) the SLU2 channel A transmitter, or (3) the

on-board 8036 PIO counter/timer. The location of these jumpers is shown in Figure
2-7. Only two of the three sources may be specified (jumpered) at one time. The two
sources that are jumpered as part of the factory configuration are SLU2 channel A
receiver and SLUZ2 channel A transmitter.

Jumper Connection
M11

M10

Description

Allows DMA channel 0 requests from SLU2

0——0

channel A receiver*

M11

M10

Allows DMA channel 1 requests from PIO

0——0

counter/timer (pin C1 used as request line)

M1l

M10

Allows DMA channel 1 requests from SLU2

0——0

channel A transmitter*

NOTE
Do not connect a jumper between M10 and M9. This configuration

is not supported.

M11
o

M10 M9

[0}

—

1
Figure 2-7

* Factory-shipped configuration

[
DMA Requests

MR-16218

2.5 Locked Instruction Enable
The KXJ11-CA has a set of jumpers that enable or disable the locking characteristic of
the WRTLCK, TSTSET, and ASRB interlocked instructions. The location of the jumpers is shown in Figure 2-8. Locking is disabled as part of the factory-shipped configuration. For most applications, locking must be disabled. If locking is enabled, a Q-Bus
timeout may cause a trap to location 4 if the Q-Bus is heavily loaded, and one of these
instructions is executed.
Jumper Connection

Description

M64

The locking characteristic of the WRTLCK,
TSTSET, and ASRB instructions is enabled

M65

o——0

M66

The locking characteristic of the WRTLCK,
TSTSET, and ASRB instructions is

M66

M64

M65

o———0

disabled*

.....

]

—

M64
o]

M65
0

M66
O -

]

|
MR-1086-1235

Figure 2-8

Locked Instruction Enable

* Factory-shipped configuration

2-12

2.6 BREAK Enable Selection
There is a jumper on the board that enables or disables console BREAK requests from
SLU1 (the on-board DLART) to the J-11. The location of this jumper is shown in

Figure 2-9.

A BREAK is generated by SLU1 when a console terminal is attached to

the system and the BREAK key on the console keyboard is pressed. When BREAK is
received, the J-11 executes MicroODT. BREAK requests are enabled as part of the

factory-shipped configuration.
Jumper Connection

Description

M13

o—o0

M12

Console BREAK requests enabled*

M13

M12

Console BREAK requests disabled

.....
M12

]

M13

—

]
Figure 2-9

]

BREAK Enable

* Factory-shipped configuration

2-13

MR-16219

2.7 HALT Option Selection
A jumper on the KXJ11-CA determines what action will be taken if a HALT instruction is executed in kernel mode. The location of this jumper is shown in Figure 2-10.
The jumper affects the state of bit 3 of the Maintenance Register (see Section 3.2.10,
The KXJ11-CA Single-Board Computer User’s Guide, EK-KXJCA-UG-001). If the

jumper is installed (the factory-shipped configuration), a HALT instruction executed in
kernel mode causes the processor to enter MicroODT. If the jumper is not installed,
the KXJ11-CA traps to location 4 in kernel instruction space and sets bit 7 in the
CPU error register.

Description

Jumper Connection

M14

o—o0

M15

MicroODT is entered when a HALT instruction is
executed in kernel mode*

M14

M15

KXJ11-CA traps to location 4 in kernel instruction

space and sets bit 3 of the CPU error register if a
HALT instruction is executed in kernel mode

.....

]

— .

1
Figure 2-10

HALT Option Selection

* Factory-shipped configuration

2-14

MR-16220

2.8 Power-Up Option Selection
The power-up jumper (see Figure 2-11) determines what action the KXJ11-CA will take
when the board is powered up or reset. The jumper affects the state of bit 2 of the
Maintenance Register (see Section 3.2.10, The KXJI11-CA Single-Board Computer
User’s Guide, EK-KXJCA-UG-001). At power-up, if the jumper is installed, the processor enters MicroODT with the PS register cleared. This is also known as power-up
option 1. If the jumper is not installed, (the factory-shipped configuration), the KXJ11-

CA executes the firmware power-up code at location 173000 during power-up (PC =
173000, PS = 340). This is also known as power-up option 3. Only power-up options 1
onnn

and 3 are used for the KXJ11-CA.
Jumper Connection

Description

M17

o——o0

M1e6

MicroODT is entered during power-up

M17

M1l6

The

KXJ11-CA

Dbootstraps

through

location

173000 during power-up*

@’/,_.Nmo

oM16

]
[ ]

]
Figure 2-11

MR-16221

Power-Up Option Selection

2-15

2.9 PROM Addressing
The KXJ11-CA can be jumpered to accommodate various PROM types. The location of
the PROM addressing jumper is shown in Figure 2-12. If the jumper is not installed,
the on-board PROMs use 15-bit addresses. PROMs such as the Intel 2764 (8K x 8)
and 27128 (16K x 8) use 15-bit addresses. If the jumper is installed, the PROMs use
16-bit addresses. This accommodates PROMs such as the Intel 27256 (32K x 8) that
use 16-bit addresses. 15-bit PROM addressing is specified as part of the factoryshipped configuration.

Description

Jumper Connection

M19

M18

M19

15-bit addressing selected*
16-bit addressing selected

M18

1
Figure 2-12

PROM Addressing

* Factory-shipped configuration

2-16

MR-16222

2.10 SLU1 Baud Rate
The jumpers shown in Figure 2-13 select the default baud rate for the SLU1 transmitter and receiver. The default baud rate for SLU1 is set when the KXJ11-CA is po-

wered

reinitialized.

This

rate

can

changed

under

software

control,

KXJCSRJ
<3 > is set. Table 2-4 shows the various baud rates that can be selected. A

default baud rate of 9600 is specified as part of the factory-shipped configuration.
Jumper Connection

Description

M60

o—o0

M59

Factory shipped configuration

M58

M57

9600 baud

o—o0

M55

M60 o

o M59

M58 o

o M57

M58© o MoS \

1
Figure 2-13

N
SLU1 Baud Rate

]

MR-16223

Table 2-4

Baud Rate

SLU1 Baud Rate Jumpering

M56 to Mb5

M58 to MbH7

MG60 to M59

38400
19200

Out

9600*
4800

In
In

Out
Out

In
Out

2400

Out

1200

Out

600

Out

300

Out

* Factory-shipped configuration

2-18

2.11 SLU1 Transmitter
The SLU1 transmitter can be jumpered to send either single-ended (RS423) or differential (RS422) asynchronous serial data via connector J3. The location of the jumpers
is shown in Figure 2-14. RS423 transmission is selected as part of the factory-shipped

configuration.
Jumper Connection

Description

Mg2

RS423 transmission selected*

o0—o0

M63

M62

0——0

Mgl

M61

RS422 transmission selected

o
5

.....

(

—

1
Figure 2-14

]

SLU1 Transmitter

* Factory-shipped configuration

2-19

[

MR.16224

2.12 SLU1 Receiver
The SLU1 receiver can be jumpered to receive either single-ended (RS423) or differential (RS422) asynchronous serial data via connector J3. The location of the jumper is
shown in Figure 2-15. RS423 reception is selected as part of the factory-shipped
configuration.

Jumper Connection

Description

M48
M47
0———0

RS422 reception selected
:

M48

M47

RS423 reception selected*

M48

... —

M47

] J&[ —
—

1
Figure 2-15

]

SLU1 Receiver

* Factory-shipped configuration

2-20

MR-16225

2.13 SLU2 Channel A Receiver
The SLU2 channel A receiver can be jumpered to receive either single-ended (RS423)

or differential (RS422) serial data via connector J1. The location of the jumpers is
shown in Figure 2-16. RS422 reception is selected as part of the factory-shipped
configuration.

Jumper Connection

Description

M34

o—o0

M33

M32

o—o0

M31

M30

o—o

M29

M28

o—o0

M27

M26

o—o0

M25

M24

o—o0

M23

M34

M33

M32

M31

M30

M29

M28

M27

M26

M25

M24

M23

RS422 reception selected*

RS423 reception selected

M34 o 0 M33

M32 o o M31
M30 o o M29

M28 © o M27
M26 o o M25
M24 o

..... D B

o M23

Jl_J :Dl

—

1
Figure 2-16

[
SLU2 Channel A Receiver

* Factory-shipped configuration

2-21

]

[

MR-16226

2.14 SLU2 Channel B Transmitter
The SLU2 channel B transmitter can be jumpered to send single-ended (RS423), differential (RS422), or party line (CCITT R1360) serial data via connector J2. The location

of the jumpers is shown in Figure 2-17. RS422 transmission is selected as part of the
factory-shipped configuration.

Jumper Connection

Description
M38

M46

M45

RS422 transmission selected*

M37 I

M35

)

M36

0——o0

)

M51

M49

M50
M38

RS423 transmission selected

M46

M45

M37

M35

)

0——0

M36
0

)

M51

M50

M49

M38

Party line transmission selected

M46

M45

0——O0

M37
0

M35
o——0

M36
0

)

M51

M50

M49

* Factory-shipped configuration

2-22

M38
o

M46 M45 M37
]

|
Figure 2-17

]

SLU2 Channel B Transmitter

2-23

]

M36 M35

©o

M51

M50 M49

2.15 SLU2 Channel B Receiver
The SLU2 channel B receiver can be jumpered to receive single-ended (RS423), differential (RS422), or party line (CCITT R1360) serial data via connector J2. Two groups
of jumpers are involved and shown in Figure 2-18. RS422 reception is selected as part
of the factory-shipped configuration.

Jumper Connection

Description

M43

M20

o—o0

M4l

M2l

M40

o—o0

M39

M22

M44

M43

M20

M42

M41

M21

M40

M39

M22

M44

o—o0

M43

M20

M42

M4l

M44
M42

M21

M40

M39

M22

RS422 reception selected®

RS423 reception selected

Party line reception selected

M44
o0

o M43

- o M20

M420

o M41

oM21

M400

o M39

oM22

—.

1
Figure 2-18

]

SLU2 Channel B Receiver

* Factory-shipped configuration

2-24

]

[

MR-16228

2.16 Real-Time Clock Interrupt
SLU1 (the on-board DLART) can generate real-time clock interrupts at frequencies of
50 and 60 Hz. Jumpers M52, M53, and M54 select either the 50 Hz or the 60 Hz
real-time clock as input to the interrupt control logic. If interrupts are enabled, each
clock “tick” results in a maskable priority level 6 interrupt request to the on-board
J-11. The location of the real-time clock interrupt jumpers is shown in Figure 2-19. A
real-time clock rate of 60 Hz is specified as part of the factory-shipped configuration.
Description

o—©
Q

Jumper Connection

M54

60 Hz real-time clock selected*

M53

M52

M54

50 Hz real-time clock selected

M53
M52

1
Figure 2-19

]

[
Real-Time Clock Interrupt

* Factory-shipped configuration

2-25

MR-16229

Chapter 3

Power Supply Considerations

When installing the KXJ11-CA, make sure the power supply can handle the extra load
presented by the board. The KXJ11-CA draws a maximum of 6A at +5V. In addition,
the KXJ11-CA draws a maximum of 1.4A at +12V, for systems with the DLV11-KA
option, or .4A maximum at +12V, for systems without the DLV11-KA option. The
board adds 2.7 ac loads and 1.0 dc loads to the bus.

In standalone mode, at least four power fingers (backplane connections) and four
ground fingers for +5 Vdc must be connected to the power supply. In addition, at
least two power fingers and two ground fingers for +12 Vdc must be connected to the
power supply.

Chapter 4

Installing the KXJ11-CA in a Backplane

The KXJ11-CA plugs into any Digital standard quad-height Q-Bus backplane (see
Figure 4-1). No special backplane wiring or jumpering is required to accommodate the
KXJ11-CA. However, the grant structure must be preserved if there are blank slots
between the KXJ11-CA and the top of the backplane. This can be accomplished by
inserting grant cards where appropriate. (Figure 4-2 is an example of the use of grant
cards.) The dual-height grant card (M8659) preserves grant continuity for slots A and
B, and grant card G7272 preserves both the DMA and interrupt grant continuity for
slot C. The KXJ11-CA board must also be configured for the proper Q-Bus address
size.

MR-12021

Figure 4-1

Backplane Installation

4-1

Figure 4-2

Using Grant Cards

4-2

4.1 Edge Connector Pin Assignments
Table 4-1 summarizes the edge connector pin assignments for the KXJ11-CA. The
board is designed to mate with Digital standard quad height backplanes for Q-Bus

based systems.
Table 4-1

KXJ11-CA Pin Identification

Component Side

Solder Side

KXJ11-CA

Signal

AAl

AA2

+5V

AB1

AB2

AC1

BDALI16 L

AC2

GND

AD1

BDAL17 L

AD2

AE1l

AE2

BDOUT L

AF1

AF2

BRPLY L

AH1

AH2

BDIN L

AdJl

GND

AJ2

BSYNC L

AK1

AK2

BWTBT L

ALl

AL2

BIRQ4 L

AM1

GND

AM2

BIAKI L

AN1

BDMR L

AN2

BIAKO L

AP1

BHALT L

AP2

BBS7L

AR1

AR2

BDMGI L

AS1

AS2

BDMGO L

AT1

GND

AT2

BINIT L

AUl

AU2

BDALO L

AV1

+5VB

AV2

BDAL1 L

BAl

BDCOK H

BA2

+5V

BB1

BPOK H

BB2

BC1

BDALI18 L

BC2

GND

BD1

BDAL19 L

BD2

+12V

BE1

BDAL20 L

BE2

BDAL2 L

BF1

BDAL21 L

BF2

BDAL3 L

BH1

BH2

BDAL4 L

BJ1

GND

BJ2

BDALS5 L

BK1

BK2

BDALS L

BL1

BL2

BDAL7 L

BM1

GND

BM2

BDALS L

BN1

BSACK L

BN2

BDAL9 L

BP1

BP2

BDAL10 L

BR1

BR2

BDAL11 L

BS1

BS2

BDAL12 L

BT1

GND

BT2

BDAL13 L

BU1

BU2

BDAL14 L

BV1

+5V

BV2

BDAL15 L

4-3

Table 4-1

KXJ11-CA Pin Identification (Cont)

Component Side

Solder Side

KXJ11-CA

Signal

CAl

CA2

+5V

CB1

CB2

CC1

CC2

GND

CD1

CD2z

CEl

CE2

CF1

CF2

CH1

CH2

CJ1

CJ2

CK1

CK2

CL1

CL2

CM1

CM2

IAK L (Note 2)

CN1

CN2

IAK L (Note 2)

CP1

CP2

CR1

CR2

DMG L (Note 3)

CS1

CS2

DMG L (Note 3)

CT1

GND

CT2

Cu1

CuU2

Cvl

Cv2

DAl

DA2

+5V

DB1

DB2

DC1

DC2

GND

DD1

DD2

DE1

DE2

DF1

DF2

DH1

DH2

DJ1

DJ2

DK1

DK2

DL1

DL2

DM1

DM2

DN1

DN2

DP1

DP2

DR1

DR2

DS1

DS2

DT1

GND

DT2

DU1

DU2

DV1

DV2

NOTES
1.

NC = Not connected

Pin CM2 is jumpered to pin CN2 for the interrupt acknowledge daisy chain.

Pin CR2 is jumpered to pin CS2 for the DMA grant daisy

chain.

Chapter 5
Connectors and External Cabling

The KXJ11-CA communicates with external devices via a parallel I/O connector (J4)
and three serial I/O connectors (J1, J2, and J3). This section specifies the pin assignments of these connectors and lists the types of cables that can be used with each
connector.

5.1 Parallel 1/0 Interface (J4)
The parallel I/O (PIO) interface signals appear at connector J4. These signals are buffered. They can be driven over a 50-foot distance via a ribbon cable, or round cable
with a 40-pin AMP contact housing (AMP part number 746473-9) at each end. A PIO
cable is not provided with the KXJ11-CA. The following PIO cables are recommended
for use in the KXJ11 and are available from Digital Equipment Corporation.
.

Shielded ribbon cable BC06 R

“Mirror image” cable BC05 L

Figure 5-1 lists the pin assignments for J4, the parallel I/O connector.

BOARD

DD FF

RR TT

SG|sG|sG|sG|SG|SG{SG|SG|{sG{SG|C1|CO|BO|B1|B2|B3|B4|B5|86]|B7

A7laelAas] A4l A3 |AZ [ A1]AD|C3[C2]SG|SG|SG|[SG}SG|SG|SG|SG|SG| SG
A

AA CC EE HH

KK MM PP

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
NOTE: SG = SIGNAL GROUND

AO0- A7=PORT
A
BO-B7=PORTB
CO0-C3=PORTC
MR-12615

Figure 5-1

Parallel I/O Interface Pin Assignments

5.2 Serial 1/0 Lines (J1, J2, J3)
The KXJ11-CA has three serial /O lines.
o

SLU2 channel A (J1), a synchronous/asynchronous serial line with modem

control
.

SLU2 channel B (J2), a synchronous/asynchronous serial line without modem control

SLU1 (J3), the console asynchronous serial line (no modem control)

Each serial line is compatible with the EIA RS232-C and RS422/RS423 protocols. In

addition, SLU2 channel B (J2) is compatible with the CCITT R1360 party line protocol. To interface the KXJ11-CA with a 4-20 mA current loop device via the serial lines,

use the DLV11-KA option.
Users must supply their own serial line cables. The following cables are recommended
for use for the J2 and J3 serial I/O lines and are available from Digital Equipment
Corporation.
BC20N-05

A 5-foot EIA RS232-C null modem cable for a direct connection

between the KXJ11-CA and an EIA terminal. This cable has a 10pin (2

5) AMP female connector on one end and a

25-pin

RS232-C female connector on the other.
BC21B-05

A b5-foot EIA RS232-C modem cable for a connection between the
KXJ11-CA and a modem or acoustic coupler. This cable has a 10-

pin (2

5) AMP female connector on

one end and

25-pin

RS232-C male connector on the other.
BC20M-50

A 50-foot EIA RS422 or RS423 cable for a direct connection between the KXJ11-CA and a remote processor. Used in applications
requiring high data transmission speeds (up to 19.2 K baud), this

cable has a 10-pin (2 x 5) AMP female connector on each end.

The pin designations for J2 and J3 are shown in Figure 5-2.

All three serial lines are factory configured to handle differential inputs and outputs. If
you change the configuration of any of the serial lines to handle single-ended inputs or
outputs, make sure the return (-) signal(s) on the cable are tied to signal ground.

Because there is no standard cable available from Digital Equipment Corporation for
SLU2 channel A, you need to construct your own cable. A standard 40-pin AMP connector may be used (AMP part number 746473-9) for connection t¢ J1. Figure &-3
illustrates the pin assignments for SLU2 channel A (J1).

SLU

CONNECTOR

BAUD RATE CLOCK OUTPUT

(16 X BAUD)

TRANSMIT DATA+ —

INDEXING KEY —

RECEIVE DATA+ —

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
o

RECEIVE DATA—-

—

ololololo

+12VDC FUSED

—

)

oRNORN

REoNEe)

PC BOARD

INDEX (NO PIN)

GND
MR-O586-0691

J2 and J3 Pin Assignments (10-Pin)

Figure 5-2

BOARD

RRR

I=ka

RDR | DMR | TRR

\Y)

CcS

TTR
EE

RSR

STR

SDR

CSR | RTR

101

SS
37

\AY)

uUu

VIEW INTO THE CONNECTOR FROM THE MODULE EDGE
MR 12352

Figure 5-3

J1 Pin Assignments (40-Pin)

5-3

Tables 5-1 through 5-3 show the correspondence between the pins of the standard con-

nectors for the RS422/RS423, RS232, and CCITT protocols, and the pins of J1. These

tables make it easy to construct an appropriate cable. The KXJ11-CA register address
associated with each signal is specified in the last column of each table for ease of
programmer reference. For further details, see the register descriptions in Chapters 3
and 6 of The KXJ11-CA Single-Board Computer User’s Guide (EK-KXJCA-UG-001).

Table 5-1

RS422/RS423 Interface to J1

Circuit

Direction

Function

RS-232

SHIELD

—

Protective Ground

From Modem

SPARE

To Modem

From Modem Send Timing (+)

CCITT Pin

Location

—

112

17777522

—
Send Data (+)

103

23,AA

114

12N

17775706

6,F

17777520

From Modem Receive Data (+)

104

8,J

177756702

To Modem

Request to Send (+)

105

13,P

17775704

From Modem Receive Timing (+)

115

18,V
14
R

17775720

From Modem Clear to Send (+)

To Modem

From Modem Data Mode (+)

To Modem

106

16,T

17775700

141

25,CC

Dummy

107

227

17775710

108/2

33.M

17777520

Local Loop

Gen.
Terminal Ready (+)

26,DD
13

From Modem Receiver Ready (+)

RL.

To Modem

From Modem Incoming Call

SF/SR

To Modem

Remote Loop

Select Frequency

109

24,BB

17775700

140

9,K

Dummy

125

Gen.
20,X

17775710

17777520

126

3,C

Signal Rate Select

@ CH

111

3,C

Terminal Timing (+)

113

30,JJ

142

102

40,W

102b

2,B

To Modem

From Modem Test Mode

To Modem

From Modem Receive Common

17777530

10,L

Signal Ground

SPARE

SDR

To Modem

—_

STR

From Modem Send Timing (-)

RDR

From Modem Receive Data (-)

15,8

RSR

To Modem

32,LL

Send Data (-)

Request to Send (-)

5-4

31, KK
38, TT

17777522

RS422/RS423 Interface to J1 (Cont)

Table 5-1

Circuit

Direction

Function

RS-232

CCITT Pin

RTR

From Modem Receive Timing (-)

37,SS

CSR

From Modem Clear to Send (-)

35,PP

To Modem

3.C

DMR

From Modem Data Mode {-)

17,V

TRR

To Modem

19,
W

RRR

From Modem Receiver Ready (-)

To Modem

Terminal in Service
Terminal Ready (-)

Location

17777520

7,H

Select Standby

116

28,FF

Dummy

Gen.

From Modem Signal Quality

To Modem

TTR

To Modem

From Modem Standby Indication
To Modem
Send Common

110

= New Signal

—
—

Terminal Timing (-)

27,EE
117

102a

1,A

NOTES

Pins K 9, 25 CC, and 28 FF are driven by dummy generators

that disable RL (CCITT

140),

LL (CCITT

141),

and SS

(CCITT 1186) respectively.

The label NC indicates no connection.

The suffix R in a three-letter pin label (such as RDR) signifies
that the pin is associated with the return side of a differential
driver or receiver.

Circuit IS can be redefined to mean SF. Or IS can be redefined as SR. In the second case, TM is also redefined as SI.

5-5

Table 5-2
Pin

Circuit

RS232-C Interface to J1
Direction

Function

CCITT

Location

—

Protective Ground

101

39,UU

To Modem

Transmitted Data

103

6,F

From Modem

Received Data

104

8,J

17775702

To Modem

Request to Send

105

18,V

17775704

From Modem

Clear to Send

106

16,T

17775700

107

22,Z

17775710

From Modem

Data Set Ready

—

Signal Ground

102

40,W

From Modem

Receiver Ready

109

24,BB

—

(From Modem) (+ DC Test Voltage)

—

(To Modem)

—

(- DC Test Voltage)

—

Unassigned

SCF

From Modem

Secondary Carrier

SCB

17775706

17775700

—
122

—

121

—

118

—

Detector
From Modem

Secondary Clear to

Send
14

SBA

To Modem

Secondary Trans-

mitted Data
15

From Modem

Transmitter Clock

114

12,N

SBB

From Modem

Secondary Received

119

—

115

14
R

120

—

Data Terminal Ready

108/2

26,DD

Signal Quality

110

—

125

20,X

17775710

17777522

17777520

Data
17

From Modem

Receiver Clock

—

To Modem

Receiver Dibit Clock

SCA

To Modem

Secondary Request to

17777520

Send
20

To Modem

From Modem

17777520

Detector

From Modem

Ring Indicator

CH/CI

To Modem

Data Rate Selector

To Modem

256

To Modem

External Transmitter

111

112

3,C

17777520

113

10,L

17777530

Clock
Force Busy

5-6

—

Table 5-3

CCITT/V.35 Interface to J1

Circuit

Direction

Function

RS232 RS449 Pin

101

—

Protective Ground

102

—

Signal Ground

40,W

105

To Modem

Request to Send

18,V

17775704

106

From Modem Ready for Sending

16,T

17775700

107

From Modem Data Set Ready

22,Z

17775710

109

From Modem RCV Line Signal Det

24,BB

17775700

Location

39,UU

108/1

To Modem

Connect Data Set

108/2

To Modem

Data Terminal Ready

26,DD

17777520

125

From Modem Calling Indicator

20,X

17775710

104

From Modem Received Data A

8,J

17775702

104

From Modem Received Data B

—_—

115

From Modem Receive Timing A

14R

—

115

From Modem Receive Timing B

114

From Modem Transmit Timing A

114

From Modem Transmit Timing B

103

To Modem

Transmit Data A

103

To Modem

Transmit Data B

113

To Modem

Terminal Timing A

113

To Modem

Terminal Timing B

5-7

DD
DB

12,N

—_

6,F

—

10,L.

—

17777520
17777520

17775706

17777530

5.3 Loopback Connectors
Loopback connectors (not provided with the KXJ11-CA) are attached to the serial or

parallel communication ports to determine whether or not they are operating correctly

(see Figure 5-4). They are typically used in conjunction with the running of diagnostic
programs, and in some firmware self-tests (see Section 2.1). These connectors may be
ordered from Digital Equipment Corporation or may be built by the user.
There are three different types of loopback connectors available from Digital.

A 10-pin

loopback connector {Digital part number H3270j is plugged into either J2 to test SLU2
channel B, or into J3 to test SLU1. A 40-pin loopback connector (Digital part number
H3022) is plugged into J1 to test SLU2 channel A. This loopback connector can also

be configured to test RS422 or RS423 operation (see Figure 5-4). The third type of
loopback connector is also 40 pins (Digital part number H3021), and is plugged into J4
to test the parallel 1/O port.

BOOT/SELF-TEST
SWITCH

LOOPBACK
CONNECTORS

RS 422 TEST

$1-1
ON

Figure 5-4

8§12
ON

Si-3
ON

s14
OFF

515
ON

S$19
QFF

S110
ON

S1-6 $1-7 s1.8 819

S110

$16
OFF

S1-7
ON

S$1-8
OFF

RS423TEST

§1-1

OFF

812 813 514
OFF

OFF

Loopback Connectors

5-8

$1-5
CFF

OFF

Chapter 6
Diagnostics

6.1 Error Detection and Reporting with the LEDS
There are four LEDs on the edge of the KXJ11-CA board that the native firmware

uses to indicate the state of the board. These are especially useful for diagnostic purposes during power-up or reinitialization. These LEDs verify that the board is operating properly or, if there is a problem with the board, can help the user locate the
difficulty. Table 6-1 summarizes the conditions the LEDs can indicate.

Upon power-up or reinitialization, all four LEDs are illuminated for approximately 1/2
second, if they are working properly. When the KXJ11-CA is installed in a backplane
in a box, the LEDs are labeled L4 through L1 from left to right. If the KXJ11-CA
runs its self-tests (this is determined by the setting of the boot/self-test switch), L4 is
off and L3 - L1 should be on as the self-tests run. If one of the self-tests fails, L4 is
illuminated, and L3 - L1 indicate the test that failed. Self-tests are run in the order
listed in Table 6-1. Thus, if a test fails, the user can also determine which tests (if any)
passed.

If all the self-tests run without error, the KXJ11-CA performs a boot operation. The

boot/self-test switch setting determines which function is performed. L4 remains off
and L3 - L1 indicate the status of the executing code. Note that the boot/self-test
switch may be set so self-tests are not run. If self-tests have not been run, then L4 is
off, and L3 - L1 indicate the state of the board as it executes code.

Table 6-1

LED Display Definitions

LEDs

Meaning

All LEDs on for 1/2 second at the start of a power-up or
reinitialization operation

Can’t access Control/Status Registers in I/O page (fatal

error); or the power-up jumper (M16-M17) is installed,
which precludes self-tests.

)

DMA or RTC test failed

X -

RAM test failed

ROM checksum test failed

)

Serial line test of SLU1 failed

)

Serial line test of SLU2 channel A failed

Serial line test of SLU2 channel B failed

Parallel port test failed

Auto self-tests running. Auto self-tests do not require
loopback connectors.

Loopback tests and auto self-tests running

Q-Bus ODT mode

Unused

)

Waiting for command

Performing DTC load

TU58 primary bootstrap executing

Executing non-native code

Quick LED Reference
LEDs

o)
0

L2z

Meaning

Self-test error detected

Fatal self-test error detected

No self-test errors detected

)

Application running without error

Legend

= On

= Off
= Don’t care (either On or Off)

6.2 Diagnostic Testing with XXDP
+
The KXJ11-CA can be tested by running XXDP+, a diagnostic operating system that

is booted from the user’s system disk. This section explains how to run the XXDP+
diagnostics to test the KXJ11-CA. More information on XXDP+ is found in

The

XXDP+ System User’'s Manual (AC-F348F-MC).

When you have successfully booted XXDP+ from the system disk,

a message such as

the one shown below appears on the console terminal. The items that are blank (underscore) indicate values that are system-dependent.
BOOTING

XXDP-

XXDP-SM
BOOTED

MONITOR

VERSION

FROM

NON-UNIBUS

MEMORY
SYSTEM

RESTART

ADDR:

THIS

XXDP=

TYPE

"“H”

"H/L"

FOR

HELP

When the “period’ (.) prompt appears, the user types in
R

ZKXA??2<CR>

This initiates the running of the tests. The message
ZKA__.BIN

appears on the console, followed by several lines of system information (the underscore

indicates characters that are system dependent). Then the following message should
appear.

USE

<ESC>

KXJ

FUNCTIONAL

SWR

HALT
TEST

OCTAL

FUNCTION

100000

HALT

ERROR

040000

INHIBIT

ERROR

SUMMARY

020000

INHIBIT

ERROR

REPORTS

KNOWN

GOOD

010000

IOP

004000

TEST

002000

ENABLE

001000
000400

LOOP
LOOP

000200

INHIBIT

08
07
SWR

140000

NEW

IO#

STAND

ON
ON

6-3

ALONE

EXTENDED

ERROR
TEST IN

TEST

FOR

TESTING

IOP
MEMORY

TESTS

SWR<6:0>

NUMBER/TITLE

At this point, type <CR>, which runs the tests until an error is detected. As the tests
run,

their results

are displayed on the console.

If an error

detected,

self-

explanatory error message is displayed, and the tests halt if bit 15 in the SWR is set
to 1. The halt causes an entry into MicroODT. To continue after an error has caused a
halt, type

P<CR>

using the console keyboard.
If no errors are detected, testing can be terminated, if the BREAK enable jumper is

installed, by pressing the ESCAPE key (which halts the KXJ11-CA and causes microODT to be entered), or by pressing the BREAK key (which halts the arbiter).

6-4

EK-KXJCA-IN-004
KXJ11-CA Single-Board Computer Instaliation Guide

READER’S COMMENTS
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