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EK-KMV11-UG-001

1983

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Document:	KMV11 Programmable Communications Controller User Guide
Order Number:	EK-KMV11-UG
Revision:	001
Pages:	90
Original Filename:

OCR Text

EK-KMV11-UG-001

KMV11 Programmable

Communications
~Controller
‘User Guide

Course Prepared by Educational Services
of
Digital Equipment Corporation

First Edition, March, 1983

The information in this document is subject to change without
notice. Digital Equipment Corporation assumes no responsibility
for any errors herein.

Printed in U.S.A.

The following are trademarks of Digital Equipment Corporation.

dlilgliltlall

DEC
DECmate
DECsystem-10
DECSYSTEM-20

MASSBUS
PDP
P/OS
Professional

DIBOL

RSX

DECUS
DECwriter

Rainbow
RSTS

UNIBUS
VAX
VMS
VT
Work Processor

CONTENTS

Page
PREFACE

W DN e
B
ON U

el
o Ny -

CHAPTER 1

INTRODUCTION

SCOPE

1-1

KMV11 GENERAL DESCRIPTION ,,,,,,,,,,,,,,P

..........................................................
AN
SYSTEM OPERATION ...ttt

1-1

CSR LAY OUT .
ee
BSELL DEFINITIONS .. ... i ettt
KMVI1 - HOST INTERACTION ...ttt

CHAPTER 2

INSTALLATION

2.1
2.2
2.3

UNPACKING AND CHECKOUT ......ooooooeee,

INSTALLATION PHASES . ...t
et e,

2.4

PREINSTALLATION CONSIDERATIONS ........ccviiiiiiinn...

2.4.1
24.2
243
2.5

SCOPE

Mounting Space .....vvvviiiiiiii
ittt
i,

22
- 2-2
- 2-3
2-3

Power Requirement .............c.coiiiiiiiiiiiiniiiie
e
Modem Cable Assembly Requirements ..................c.ccuv.n...
M7500 INSTALLATION ...t
e
et
Voltage Check ............ e

SWILCh SettIngS . ..

v ittt

it i

s et e et e s e -

i e

2-3

Address Switches ............cciiiiiiiiiiii
i
i

2-3

................... e esasaenesess

2-9

DECX-11 System Exerciser .................R
S UA
Final Cable Connections ................ e eittireteieieeeee..
KMVI11 INSTALLATION CHECKOFF LIST ......................

2-10
2-10
2-10

CHAPTER 3

APPLICATION MODE

CSR DESCRIPTION ...
i
it et ettt canenns
BSELL DEFINITIONS ...
ettt

3-1
3-1

LOADING AND STARTING APPLICATION FIRMWARE ........

3-2

2.6
2.6.1
2.6.2
2.6.3
2.7
2.7.1
2.7.2
2.7.3
2.8

Vector Switches ..........iiiiiiiiiiiiiii
i,
2-4
Jumper Configurations ..............ciiiiiiiiiiiiinnrinnnnnnn.
2-5
Standard Switch Setting and Jumper Cenfiguratmn forKMV11-A .....
2-6
M7500 InSertion .. ........cuuiiiiniernnneernneennneennneennnns
2-7
MODEM CABLE ASSEMBLY IN STALLATION ...................
2-8
BC55H/BC55U/BCSSP Considerations .................ccovvnn.. 2-8
BC55H, BC55U, and BC55P Installation on the H349 Panel .......
2-9
BC55H, BC55U, and BCS55P Installation Without H349 Panel .....
29
KMVI11 SYSTEM TESTING ...ttt
iinenenns
2-9

W DD

2.5.5

1-4

2-1
2-1
2-2
- 2-2

2.5.2

2.5.3
2.5.4

1-2
1-3

2.35.1

2.5.2.1
2.5.2.2

1-2

Functional Diagnostic Testing

iii

CHAPTER 4

APPLICATION FIRMWARE DEVELOPMENT

4.1
4.1.1

KMV11 I/JO PROGRAMMING ...ttt
Front-End Processor Address Space ...........ccciiiiiiiinennnn

4-1
4-1

4.1.3

Front-End Processor Interrupt System ...........................

4-3

CSR and DMA Address Register Description . ....................
CSR and DMA Programming ...........c.coouiunineeeenennenenons
Programming Sequence for DMA OUT .....................
Programming Sequence
for DMAIN ........................
LINE CONTROLLER INTERFACE ........c.iiiiiiiiiiinnnnnnnns
Line Controller Register Description ...............cociviiian...
Channel
A Receive Buffer .....................civeveeee..
Channel
A Transmit Buffer .............
...
it
Channel B Receive Buffer ........................e
Channel B Transmit Buffer ............
..o iiiiiiinon..
Channel A Command Registers .............ccovviiiiinnn,
Control Register O ...t iiiiiiiiiinnnnn
Control Register 1 ...ttt iiiinnnnn
CcntrelReglsterZ(ChmeIA) vihes e bainseriraaennesnns
Control Register 3 ........cciiiiiiiiiiiiiiiiiinnnn
Control Register 4 .........ccoviiiiiiiieriinneennennnns
Control Register 5 .................... e
Control Register 6 ................... T S
Control Register 7 .......coviiiiiiiiiiniinnnennenn.
Channel B Command Register ......... U T A
Control Register 0 .........oiiiiiiiiiiinnrnnnennsnns
Control Register 1 ..........c.ciuiiiiiiiiiiieinnennenn.
Control Register 2 (Channel B) ...... e
Channel A Status Register ............ccoiiiiiininnnennn.

4-5
4-6
4-7
47
4-7
4-13
4-13
4-13
4-13
4-13
4-13
4-13
4-16
4-17
4-18
4-20
4-21
4-24
4-24
4-24
4-25
4-25
4-26
4-26

Status RegisterO ........ ...ttt
i,
~
Status Register 1 .........co it
Channel B Status Registers ............c.ciiiiiinnnnnnnnnn.
Status Register 0 KMV11-A .......
... .. ...
..
Status Register 0 KMV11-B (dual hne) .................
Status Register 1 .........
.0 iiiiiiiiiiiiinnnnnn.
Status Register 2 .........ciiiiiiiiiiiiiininnnnnnnnns
Line Controller Interrupt System and Mode Selection ..............
HDLC Operation Example ......... ..ot
LINE CLOCK
- REAL-TIME CLOCK INTERFACE ...............
Line Clock— Real Time Clock Regzster Descrxptmn ...............
Line Clock Programming ..............civuiiiinnennnnenennnnnn.
Real-Time Cleckngrammmg,...;..”““.‘..HH,.“.“” ,,,,,
Line Clock— Real-Time Clock Parameter Setting .................
PERIPHERAL
PORT INTERFACE ...........c.cciiiiiiiiiiann...
Peripheral Port Register Description ...............ccoiiii...
Modem Monitoring and Control .............
... ..ot
HOST INTERRUPT
AND Q-BUS CONTROL INTERFACE ........
Host Interrupt and Q-Bus Control Register Description ............
Host Interrupt and Q-Bus Control Programming ...................

4-26
4-28
4-29
4-30
4-30
4-30
4-30
4-31

I/O Register ASSIZNMENt . .....ovvnrterrineerrneeennnneeennnnns

4.2
4.2.1
4.2.2

’

B W
-

A
s

4. 4 1

4.4.2
4.4.3

4.4.4
4.5
4.5.1
4.5.2
4.6
4.6.1

4.6.2

L3
L]

00 1O\ L B WD

e S N N I I I S TR TS TR I G A N

]
»
*
.
®©
[
.
»
»
*
-

& el el el ol

bl i

R RERFARRE AR AR AR RE IR IR
.;:xwm'

ol ool ol el el el

RERR R R RN IR RE R R R
.
»
.
»
.
®
*
*

b ol ol ol ol ol ol o B

42.2.1
4.2.2.2

4-1

4-32
4-34
4-34
4-35
4-36
4-37
4-38
4-38
4-42
4-46
4-46
4-47

SERVICE

LUALNALU
LU LU LKL LLL
BB BB D WWWWWWWN
-

SCOPE ... .o
e i[
O S
MAINTENANCE PHILOSOPHY.. ..oveeiieeeee e,
MAINTENANCE TOOLS AND F EATURES,,,,,,,,,,,,,,,,,,,,,,
LED Indicators .............ccoiviiinivnnnnn. Ve
v e
N [ N

”

BN
e

W NI

W WWWN
-

CHAPTER 5

Line Clock and Loopback Connectors.......... eedenees R

LineClock .................. o e s s e s s e s e e ase e o s
enbonennan
Real-Time Clock ............. . e
Loopback Connectors/Tests ..................e
DIAGNOSTICS ... i, ittt
ee e,
VKMALogchlagnasuc R
N
T S
S
VKMB Line Controller Diagnostic ................covveuunnnnn..
VKMC Functional Diagnostic ............coovviiiimnenneunnnnn.
XKMD DECX-11 Exerciser Medule S
i e IO B
PREVENTIVE MAINTENANCE ................. TR APet
CORRECTIVE MAINTENANCE ............ TR
S0 J T P

5-1
5-1
5-1
5-2
5-3

5-5

5-5
5-6
5-6

5-9
5-10
5-10
5-11
5-12
5-12
5-12

Title

Page

CSR Definitions . ...ovvvittitn
e nnrneernernrrneennenneennennss
BSELI Definitions . ........ouuiiiniirintiiie
ittt
ianennnnn
HOST -KMVIl Interaction ...........ccoviiiiiiniinniinennnenna..

1-2
1-3
1-4

Address Switch Register Mapping ..........ccoviiiiiiiiiiiinnennnnns.

2-3
2-3

Address Switch Setting Example: 760020g ...................ooooilll.
VecterSwitchRegisterMa?pigg,m.“n,““.,.,,” ,,,,,, e e e nnaas

2-4

Vector Switch Setting Example: 320 ..........coiviiiiiiiiiinennnn..

2-4

RS-422 Versus RS-423 (RS-232) on Switch Pack E85 ... il

2-6
3-1

KMVII Memory Map

......ccoiiiiiiiiiiiiiiiiniiinenennn.e eeeeens

4-2

Control Register O, Bit Functions ..... s de
se -

553

Control Register 1, Bit Functions ...........coiiiiiiiiiiiiienenennnn.
Control Register 2 (Channel A), Bit Functions ........................
Control Register 2 (Channel B), Bit Functions ............. e
e eereeee
Control Register 3, Bit Functions .............oiiiiiiiiiirennnnennnns
Control Register 4, Bit Functions ............T
P N
Control Register
5, Bit Functions ...............ccciiiiiiinnnnneen..
Control Register 6, Bit Functions ............ R
Control Register
7, Bit Functions ...............cciiiiiiiiiiinenee...

4-9
4-9
4-10
4-10
4-10
4-11
4-11
4-11

\©

o ~J

P4£ PP L

N (&

O FOR NG

BSEL1 Bit Layoutin Application Mode ..............ccoviiveivennn...

6 IO

PR NG I

Figure No.
VRPN
WY

FIGURES

4-10
4-11

Status Register O, Bit Functions ............oviiimminnreennnnnn.. ...

4-12

Status Register 1, Bit Functions ................... R
Status Register 2, Bit Functions ...... A LA NEFIR Ceveeeeeae.
Control Register O Layout .............c.oiiiiiiiiiriiiiiiiinennn.
Control Register 1 Layout ...........ccuiiiiiiiierirnennreenennenens
Control Register 2(A) Layout ...........cciiiiiiiiiiiiiirirnnnenenns
Control Register 3 Layout .............cciiiiiiiiiiiiiiiiiiiinnnnnnn.
Control Register 4 Layout .............ciiiiiiiiiiiiiinnnennennnnn.

4-12
4-13
4-14
4-16
4-17
4-18
4-20

4-13
4-14
4-15

4-16

4-17
4-18

Control Register 5 Layout ..............ciiiiiiiiiiiiiniiinnennn, ..
Control Register 6 Layout ............ccoiiiiiiiiiiiiiiinieinnennnnns
Control Register 7 Layout ...............ccoiiiiiiiiiinn.. A
Control Registers in the KMV11-A and KMV11-B ....................
Control Register 2(B) Layout ..........ccoiiiiiiiiiiiiiiinnnneennnn.
Status Register O(A) Layout ............... P
Status Register 1 Layout ........ccoiiiiiiniiiiniiiiniiinnriineennnsStatus Register O(B) Layoutin KMV1 oAe
Status Register 2(B) Layout ..........coiiiiiiiiiiiiiii iy
iiiiiiia..
.........
Clock Control Register Bit Functions ..........
KMV11-A Port A Register Layout ............coiiiiiiiininnnnnnn.. .
KMV11-B Port A Register Layout ..........covivviniininiiiinennn.
Port CRegister Layout .........ccivuiiiiiiiiiiiiiiiiiiiniiennnnnn.
KMV11-A Port B Register Layeut ...................................
KMV11-B Port B Register Layout ...............cciiiiiiiiiiienn.n.
Q-Bus Control Register Layout ...........c.ooooiiiiiiiiinnn,
LED Indicator Location .......... AP
st ..........coititiiiierinrnrntnrnsnenennnns
Switch Locations
Self-Te
KMV11 Loopback Connector H3255 ........ ...,
KMV11 Loopback Connector H3251 ....... ... ... .o iiiiiiiiii.n,
KMV11 Turnaround Connector H325 ............ ..o,

421
4-24
4-24
4-25
4-26
4-26
4-28
4-30
4-30
4-37
4-38
4-39
4-39
4-40
4-41
4-46
5-2
5-4
5-7
5-8
5-9

TABLES
Table No.

2-2
2-3
s

4-1

4-2
4-3
4-4
4-5

4-6
4-7
4-8
4-9
4-10
4-11

4-12
4-13

4-14
4-15

5-1

5-3

Title

Page

KMV11 Packing Lists .......couiiniuniiniiiiiiinrneenrnenneannnnns
KMV11-A Switch Register and Jumper Settings .......................
KMV11-AA/AF Additional Switch and Jumper Settings ...............
KMV11-AE Additional Switch and Jumper Settings ...................
BC55H, BC55U, and BCS55P Jumper Settings . ...............covvunnt
Control Register 0 Description ........... R
AT
A
Control Register 1 Description ...........ccoiiiiiiiiiniiiininininn,
Control Register 2 Description ............ A
S S U
Control Register 3 Description ...........ccouiiiiiniinininennenenenns
Control Register
4 Description .............. B
Control Register 5 Description ..... il Fenaese e R
S
Status Register O Description .............. D
S
Status Register 1 Description .................. i
KMV11-A Port A Register Bit Description ...........................
KMV11-B Port A Register Bit Description .................ccviiine..
Port C Register Bit Description .........covvvivvieerreeeeeeanneeea..
KMYV11-A Port B Register Bit Descnptxon et iemes ettt atsesananns
KMV11-B Port B Register Bit Description ...................... ...
List of Supported Modem Signals ................
o iiitiiiiiiiiinn.n.
Q-Bus Register Function Description .................ccovvvnneeenn..
LED Meaning .......cuvuueuniuneuneeneeneenoronssnosassanennnennss
Self-Test
Switch Configuration ............cccevvivverenneneeseeennnes
Self-Test LSt .. .v ittt ittt it ittt is et et tneasa
s
vi

2-1
2-6
2-7
2-7
2-8
4-14
4-16
4-18
4-19
4-20
4-22
4-26
4-28
4-38
4-39
439
4-40
4-41
4-43
4-46
5-2
=3
5-4

PREFACE

This user’s guide describes how to use the KMV11 communications controller. It describes all the
functional elements of the KMV11 communications controller and the way user-developed firmware can
control those elements.

Other documents which support the KMV11 programmable communications controller are:
KMV11 Technical Manual (EK-KMV11-TM-001)

DCT11-AA Microprocessor User Guide (EK-DCT11-UG-001)
NEC

uPD7201 Multi-Protocol Serial Controller Technical Manual (NEC Electronics

(Europe) GmbH)

Microcomputer Processor Handbook (DIGITAL)
Microcomputer Interface Handbook (DIGITAL)

vii

CHAPTER 1

INTRODUCTION

1.1 SCOPE
This chapter contains a short 1ntroductxcm to the operatmn of the KMV11. The term KMV11, as used
throughout this manual, means the programmable communications controller.
In this manual the term firmwareis usedin relation to the KMV11, and means any set of instructions
whichis containedin the KMV11’s memory space, andis to be mterpreted and executed by the DCT11

microprocessor.

Root Firmware resides within the ROM space of the KMV11 andis a permanent component of the
KMVI11.

Appiication Firmware is to be loaded into the RAM space of the KMV11 at system startup time or after
power failure

1.2 KMVII GENERAL DESCRIPTION
’
The KMV11 is designed to be usedin a communication link by Q-bus-based systems. The KMV11 is
microprocessor based and able to perform functions for bit-oriented synchronous protocols (like HDLC),
byte-oriented synchronous protocols (like BSC), or asynchronous protocols. The application firmware
defines the computer instructions that are needed to execute the protocol-related activities.

Features of the KMV11 include:
1.

Direct Memory Access (DMA) across the Q~bus for medium-speed transmission and
reception

A DCTII microprocessor with the PDP—-I 1 base-level instructien set

A 7201 PUSART (Programmable
Transmitter) line controller chip

EPROM of 4K bytes, with root firmware and power-up self-test diagnostics

Customer-developed application firmware uses the PDP-11 instruction set

RAM space of 32K bytes, for implementéfion of data-lihk protocols.

Synchronous (bit-oriented or byte-oriented) as well as asynchronous capablhnes for the
application firmware
|

Extensive support of modem signals

On-board RS-422-A, RS-423-A (CCITT V.11, V.10) electrical interfaces

Universal

1-1

Synchronous

Asynchrencus

Receiver/

10.

RS-232-C (CCITT V.28) compatible

11.

An on-board null modem clock.

The KMV11, by using a microprocessor with a PDP-11 instruction set, makes the development of the
application firmware more easy.

1.3 SYSTEM OPERATION
Communication of control and status information between the host and the KMV11 uses 8 words (16
bytes) of control and status registers (CSRs). These have addresses from 76xx00 to 76xx17. These device
addresses are from here on referred to as ‘byte select 0 to 17° (BSELO to BSEL17) for indicating
individual bytes, and as “select0 to 16’ (SELO to SEL16) for indicating individual words.

BSELLI is defined by the KMV11’s root firmware routines for the following functions:
1.
2.
3.

Diagnostic firmware self-test execution
Application mode control
Special maintenance functions

In application mode, function bits are defined to load, unload, and run application firmware.
Before the KMV11 is able to execute the application firmware, thzs firmware must be loaded into the
RAM of the KMV11.

In order to recover the contents of the RAM, an unload function is provided by the root firmware.

To start the execution of the application firmware, the host can pass tothe KMV11 root firmware the start
address of the applicatien firmware.
14

CSR LAYOUT

Figure 1-1 shows the layout of the CSRsin the hest processor I/O page.

15{1a[13]12[11]10] 9|8 || 7|65 |4 [3]2]1]0
BSEL1

BSELO

SELO

BSEL3

BSEL2

| SEL2

BSEL5

BSEL4

SEL4

BSEL7

BSEL6

SEL6

BSEL11

BSEL10

' SEL10

BSEL13

BSEL12

SEL12

BSEL15

BSEL14

| sEL14

BSEL17

BSEL16

'SEL16
RD 959

Figure 1-1

CSR Definitions

1-2

1.5
BSELI1 DEFINITIONS
Figure 1-2 shows the BSELI1 layout.

RUN

MCLR

WRITE

READ

| ERROR

RD 973

Figure 1-2

Bit

BSELI1 Definitions

Name

Function

Error

This bit will be set when an illegal address is specified during
reading
or writing in the KMV11 RAM memory. It will also be
set when the address specified with the run command is illegal.

Read

This bit, when set, directs the root firmware to the memory read
routine. The contents of SEL4 will be used as the memory
address. The contents of the memory location will be returned
in SEL6.

Mode

These two bits define the KMV11 mode of operation.

0 - Application mode

Allows the root firmware to execute a read or a write

routine, depending on the content of bits 10, 13, and
15.
1

— Reserved

2 - Maintenance mode 1
Test routines in the root firmware are executed.

3 - Maintenance mode 2
The root firmware clears master clear (MCLR) and
puts itself in a continuous loop.

For normal operation, these bits will always be cleared on

power-up or master clear to enable the application mode.

Write

This bit is used in application mode. When set, it requests the
loading of the contents of SEL6 into the KMV11 at the address

specified in SEL4.

MCLR (Master
Clear)

When set, this bit requests power-up initialization to clear the
hardware and restart the root firmware in the mode defined by
the mode bits. The bit is cleared by the KMV 11 on completion
of initialization.

1-3

Run

When this bit is set after MCLR, in the application mode,

program control is transferred from root firmware to the
application firmware starting at the address contained in SEL4.
When set together with MCLR, the self-test is executed, before
starting operation.

NOTE

When a HALT instruction is executed, program control will
be transferred to the root firmware.

1.6

KMVI1 — HOST INTERACTION

To define the direction of data transfer between the host and the KMV11 the terms ‘IN’ and ‘OUT’ are

used throughout this manual:

‘IN’ applies to transfer from the host to the KMV11

‘OUT’ applies to transfer from the KMV11 to the host.

The terms ‘TRANSMIT’ and ‘RECEIVE’ (‘TX’ and ‘RX’) are used in conjunction with data transmitted
or to be transmitted on to the communications line or received from the communications line.

HOST

TX DATA

RX DATA

OuT

COMMANDS

<RESPONSE
STATUS

TX DATA

rRX & RX DATA

IN | KMV11

iOUT

LINE

X | MODEM CONTROL
a

MODEM
MONITORING

RD 958

Figure 1-3

HOST — KMV11 Interaction

1-4

CHAPTER 2
INSTALLATION

2.1

SCOPE

This chapter provides all the information necessary for installing and testing the KMV11. A checklist,

which can be used to verify the installation process, is also included.

2.2 UNPACKING AND CHECKOUT
|
|
The KMV11 is packed according to commercial packing practices. When unpacking, remove all packing
material and check the equipment against the shipping list (Table 2-1 contains a list of items shipped with
each configuration). Examine all parts and carefully check the M7500 module for obvious signs of
damage. Check the received components against the shipping list. Where necessary, report damages or
shortages to the shipper and inform the DIGITAL representative.

Table 2-1

KMVI11 Packing Lists

KMV11-A Suboption Packing List
Part Number

M7500
H3255

Description

Line unit module
Module test connector

EK-KMV11-TM-001
EK-KMV11-UG-001

KMVI11 Technical Manual
KMV11 User’s Guide

MPO1173

Customer print set

KMVi1-AA

Part

RS-232 Option Packing List

Number

KMVI11-A
BC55H

H325

KMVI11-AE

Description
|

Basic suboption
RS-232 cable assembly

Cable loopback connector RS-232

RS-422 Option Packing List

Part Number

Description

KMVI11-A
BC55U
H3251

Basic suboption
RS-422 cable assembly
Cable loopback connector RS-449

Table 2-1

KMVI11-AF

KMVI11 Packing Lists (Cont)

RS-423 Option Packing List

Part Number

KMV11-A

Description

Basic suboption

BCS55P

RS-423 cable assembly

H3251

Cable loopback connector RS-449

The diagnostics for the KMV11 are released through the Software Distribution Center (SDC). The
following options can be ordered separately by self-maintenance customers:
e
e
e

ZJ-360-RZ diagnostic documentation kit
ZJ-360-FR diagnostic fiche kit
ZJ-360-PY diagnostic RX01 kit

2.3 INSTALLATION PHASES
Installation of the KMV11 should be done in four phases:
1.

Phase I — Preinstallation

Verify KMV11 requirements with respect to power and location within the system.
2.

Phase II - M7500 installation

Configure the M7500 module for the customer application.
Install the M7500 module and verify its operation, using the appropriate diagnostics.
3.

Phase III - Modem cable assembly installation
Install the cable, lay the cable, and verify cable and module via the appropriate diagnostics.

Phase IV- KMVI11 system testing

Verify the complete KMV11 subsystem operation with the functional diagnostics and system
exercise programs.
2.4 PREINSTALLATION CONSIDERATIONS
The preinstallation phase checks that the host system is capable of receiving the KMV11 option.
2.4.1
Mounting Space
The KMV11 needs one quad slot with the Q-bus connected to slots A and B. The Q-bus signals may also
be connected to slots C and D but will not be used there. BDMG and BIAK lines are connected through on
the C and D module connector.

2.4.2

Power Requirement
+SV
+12V

@
@

26A
0.2
A

2-2

2.4.3 Modem Cable Assembly Requirements
The BCS5SH, BC55U, and BC55P modem cable assemblies are de51gned to be mounted on the H349
bulkhead connector panel. This bulkhead panelis normally provided with PDP-11/23+ or PDP-1 I./ 23B
systems.

In conditions where the H3 49 is not available, the BC55H, BC55U, and BC55P modem cable assemblies
may be screwed onto the vertical cabinet mounting rails, normally drilled at EIA spacings.

2.5

M7500 INSTALLATION

2.5.1
Voltage Check
Before installing the M7500 module:

Verify that the +5 V supply voltage at backplane pin AA2 is between +4.85 Vand +5.15V

Verify that the +12 V supply voltage at backplane pin AD?2 is between +11.64 V and +12.36V.

2.5.2 watch Settings
Check that the switch settings andjumper cenfigurations meet the system and customer requirements.

2.5.2.1

Address Switches:

SWITCH PACK E29

;
SWITCHES 1 TO 9

|15|14|13 12]11]10[9]8[7]6[5]4

3|2|1|o|

SWITCH PACK E29

SWITCH |88|s7|se|55|34|33|52]s1

Figure 2-1 Address Switch Register Mapping
A4

’

A2
TEST

g1 2
X

5 6 7

9 10

—
L

SWITCH PACK
A

Ix|

Ix]

Ix|

A T

Ix]

I'x|]

572

RD1011

Figure 2-2

Address Switch Setting Example: 7600204

2-3

An ‘on’ switch matches an asserted address bit.

The KMV11 addressis to be assigned within the floating address space atrank 31. It occupies exght CSR
addresses (for example, 7600204 to 760036;).
NOTE

The term ‘rank’ has no hardware significance. It
denotes the position of the address in a table used
by auto-configuration programs.
2.5.2.2

Vector Switches
SWITCH PACK E13

MSB

SWITCHES 1 TO
7

;

LSB

l15|14|13|12|11l10 9]8]7[6]5]4,3

2]1]0!

]o]ololo]olo

ololol

SWITCH PACK E13

SWITCH S7|SS|SS|S4[S3ISZIS1
fi

Figure 2-3

RD1014

Vector Switch Registe:r Mapping

V3—

—

oo
TEST

X
B

4 5

kB
B

w | x
¢

X
=2

-4

7 8

x|
2

*1 | switch Pack
E13

|x
—
RD1013

Figure 2-4 Vector Switch Setting Example: 320
An ‘on’ switch gives an asserted vector bit.
The KMV11

vector is to be assigned within the floating vector space at rank 54.

NOTE
The term ‘rank’ has no hardware significance. It
denotes the position of the address in a table used
by auto-configuration programs.

2-4

The other two switches on E13 and E29 affect self-test operation in the following way:

E13

E29

Self-test disabled

OFF

Self-test enabled (start via CSR command or at poWer up, for one pass)

OFF

=‘ Self-test manual start for continuous loop

OFF

‘ON

SW8

2.5.3

Self-Test Operation

SWI10

Extended self-test start for continuous loop

Jumper Configurations

1. | Extended address jumpers
Links W3, W4, and W7 to W10 are normally installed to allow extended addressing (BDAL

16 to 21). They should only be removed when the extended address lines (SPARE lines on
older LSI configurations) are in contention with other signals.
2.

BDMG and BIAK jumpers

Links W11 and W13 are normally installed to provide BDMG and BIAK continuity in the C
and D slots. They should only be removed when the correspondlng backplane pins are used for
other purposes.
3.

Factory test jumpers
Links W2 and W12 are only removed during factory module testing. They must be installed for
normal KMV11 operation.
|

The other switches andjumpers depend on the modem interface characteristics as shownin the following
notes andin Figure 2-5.

All other combinations of switches 1 to 8 are illegal.
E85 switch 9 OFF isolates pin 29 of the connector assemblies (CCITT 107). It should normally be ON,
and only OFF when a modem connects a different signal to this pin.

E85 switch 10 OFF isolates pin 2 of the connector assemblies (CCITT 112). It should normally be ON,
and only OFF when a modem connects a different signal to this pin.

Jumper W15 forces modem signal CCITT 109 (Camer Detect) permanently to the active (1) state. This
linkis normally not installed.
Jumper W14 installed connects modem signal Terminal In Service to connector assemblies pin 28. This
signal is not used by most modems, but is needed for loopback testing using the H3251 loopback
connector. It should therefore only be removed in situations where its presence causes a problem with the
modem.

| x|

OFF
OFF
OFF

OFF

OFF
ON
ON

| ]

SWITCH
oO~NOOOT
A~ WN =

o))

RS-423/RS-232

RS-423, RS-232-C

ON
ON

RD1015

Figure 2-5

RS-422 Versus RS-423 (RS-232) on Switch Pack E85

Standard Switch Setting and Jumper Configuration for KMV11-A

Switch

O OO ~JONW
B WD) e

Table 2-2
E29

(11

KMV11-AA/AF,

2.5.4

| x|~

ON
ON
ON
OFF
OFF
OFF
OFF

[~]-

OFF

ONOOTPRhWN
-

SWITCH

KMV11-AE, RS-422

E13

Switch

E29
E13

Switch 10
Switch 8

1
2
3
4
R
6
7

KMV11-A Switch Register and Jumper Settings
Address = 776020

OFF
OFF
OFF
OFF
OFF
OFF
OFF
Vector = 320

Self-test enabled
Runs for one pass at power-up
or via CSR command

2-6

Table 2-2
W3
W4

W7
W8

wWo

IN
IN

KMYVI11-A Switch Register and Jumper Settings (Cont)

Extended address bits 16 to 21
connected to Q-Bus
-

W10

ouT

Not used

Wil
W13
W2
W12

IN
IN
IN
IN

BDMG and BIAK continuity made
in slots C and D
DMA clock enabled
Microprocessor clock enabled

Table 2-3 KMV11-AA/AF Additienal Switch and;Juinper Settings
E85

Switch 1
2
3
4
h)
6

OFF

OFF
OFF

OFF

RS-423-A/RS-232-C selected

8
9
10

W15
W14

OouUT
IN

-’

ON
ON

CCITT 109 (Carrier Detect) follows input
Terminal In Service connected.
Table 2-4

E35

Switch

2.5.5

KMVI11-AE Additional Switch and Jumper Settings

1
2
3

ON
ON
ON

OFF

6
7
8

OFF
OFF
OFF

9
10

W15
wi4

CCITT 107, connected
CCITT 112, connected

OuUT
IN

ON
ON

RS-422-A selected

CCITT 107, connected
CCITT 112, connected

CCITT 109 (Carrier Detect) follows input
Terminal In Service connected.

MT7500 Insertion

When you have checked supply voltages and configured the M7500 module, you may insert the module in
the selected Q-bus slot. Make sure that system power is off while inserting the module.

After insertion of the module, power up and check that the supply voltages have stayed within acceptable
limits.

Perform the following quick test on the module:
1.
2.
3.
4.

Deposit O into the base address
Examine the base address; it should be 0
Deposit 440003 into the base address
Examine the base address; it should be 4000g.

If the above test does not give the expected result, the installation must not be continued, the M7500
module must be either replaced or repaired.

2.6 MODEM CABLE ASSEMBLY INSTALLATION
At this step the connector assemblies should be installed.

2.6.1 BCS55H/BC55U/BCS55P Considerations
In order to install modem cable assemblies correctly, the H349 bulkhead connector panel with free slots in
J12,J13, J14, or J15 should be available. Otherwise the cable assembly may be screwed directly to the

vertical cabinet mounting rails, selecting a proper location where the EIA spaced holes of the mounting
rail match the holes of the connector assembly.

Before installing the BC55H, BC55U, or BC55P, verify and configure the appmpriaté modem line

jumpers.

Refer to Table 2-5 for the configuration of the BC55H, BC55U, or BC55P.

Table 2-5

BCS55H, BC55U, and BC55P Jumper Settings
FUTURE D

‘ F/&/8L
%
i

W10

w11

w12

|S5Q

[110

SBB | SRD|

| 112

119

SBA|SSD|[118

SCF | SRR | 122

| 111

“1SF [126

| SR

RL-] 140

RS | 105
ST

{114

RT | 115

Wi3 | |

iN|

[1a1

SCA|SRS | 121

wia

;

W15

TM | 142

W16

[113

W17

[ 117

Wi8

(116

W19 | IN

W20

W2T

INTINT

INJINTINTINJINTIN|

)

[INJTINJIN]INJIN|IN|IN]IN

;

SCB|

SCS | 121

MAKE BUSY

101

BA | SD | 103

BB | RD | 104

CC | DM | 107

| CS

| 106

|SG
|10;
| RR | 109

| TR

|IC

|108

|125]

MK-2725

2-8

2.6.2 BC55H, BC55U, and BC55P Installation on the H349 Panel
When the connector panelis configured, it may be mounted onto the H349 bulkhead paeei into any
available slot from J13 to J15. Refer to Flgure 2-6 fer the correct paeel mounting.
;
Connect the BCO8-S flat cable between the cenneeter panel and the M7500 module, providing a pemt-—to—
point connection. To do this, one connector end should have the ribbed side up, the other end the smooth
side up. Complete the physical installation by neatly dressing and attaching the cable to the H349.
Refer to Paragraph 2.7 for the KMV11 checkout.
DRV11-J

DRV11-J
p

PARALLEL
UNE!@FACE

DZV1i1
(SYNC LINE INTERFACE)
s

—

J8
J6

CONSOLE

DLV11-J

(KMV11-A)

DZV11

(KMV11-A)

J5
,

J10
.-

J13

J11

J14

'\14

Dzvi1

J15

———— DzV11

(KMV11-A)

DZV11

Figure 2-6

(KMV11-A)

J12

Y
R

e
2

fantoie

Connector Panel Ins;:tallation‘

2.6.3 BC55H, BC55U, and BCSS5P Installation Without H349 Panel
When you have selected the appropriate mounting space and checked thejumper cenfiguratlen you may
mount the connector panel to the cabinet frame, tightening the SCrews hard to provide a good shield to
ground continuity.
Then connect the BC0O8-S flat cable between the connector panel and the M7500 module, providing a
point-to-point connection.
2.7

KMVI11 SYSTEM TESTING

When the physical installation of the KMV11 has been cempleted it should be tested by means of the

diagnostic programs.

2.7.1
Functional Diagnostic Testmg
The functional diagnostic VKMC exercises the KMVI lina standalene mode. Make sure, before starting
the diagnostic, that either the H3251 or H325 cable test connector is fitted to the cinch connector at the

cable assembly panel, or the H3255 module test connector is fitted on the M7500 module.

Allow the diagnostic to run for at least five error-free passes.
If errors occur, refer to Chapter 5 to perform corrective maintenance.

2.7.2 DEC-XI11 System Exerciser
The DEC-X11 system exerciser, CXKMD, will run the hest penpherals, and KMV11 ina worst~case
environment similar to a user’s operating system. Any error message calls for corrective maintenance to
be perfermed Refer to Chapter 5 for cerrectxve mamtenance

2.7. 3Fmal Cable Cennectmns
After the successful completion of diagnostic testmg, remove all test connectors and install the modem or
null modem cables as needed by the application.
Standard modem cables:

RS-232-C

BCO5D-25

- 7.5 m (25 ft)
Connects the modem to a 25-pin cinch connector on a BC5SSH cable
assembly

RS-423-A

BCS55D-33

10 m (33 ft)

Connects the modem to a 37 -pin cinch connector on a BCS5P cable
assembly

RS-422-A

2.8

BC55D-33

10 m (33 ft)
Connects the modem to a 37-pin cinch connector on a BC55U cable
assembly

KMVI11 INSTALLATION CHECKOFF LIST
Date Completed

PHASE

R
- TR

PHASE

Ny
N

PHASE 1

PREINSTALLATION
Mounting space (2.4.1)
|
Power requirements (2.4.2)
Modem cable requirements (2.4.3)
M7500 INSTALLATION
Unpack, check for full shlpmem (2.2)
Backplane voltages (2.5.1)
Switches configured (2.5.2)
(2.5.4)
Juznpers cenfigured (2.5.3)
(2.5.4)
M7500 installed (2.5.5)
Backplane voltages (2.5.1)

‘M7500 quick check (2.5.5)

MODEM CABLE ASSEMBLY INSTALLATION
H349 or meuntmg space on cabinet
frame availablefor BC55H/U/P (2.6.1)
BC55H/U/P configured (2.6.1)
BC55H/U/P installed (2.6.2)
(2.6.3)
BCO08-S installed and connected (2.6.2)
(2.6.3)

2-10

PHASE IV
.

KMVI11-A SYSTEM TESTING
Test connectors fitted (2.7.1)
Functional diagnostics (2.7.1)
DECX-11 exerciser (2.7.2)
Test connectors removed, modem cables
installed (2.7.3)

2-11

wly

CHAPTER 3
APPLICATION MODE

3.1
CSR DESCRIPTION
In application mode the KMV11 may use all the eight CSRs available, to provide communication
between the host and the KMV11’s application firmware. The CSRs have addresses from 76xx00 to
76xx16; they are also referred to as BSELO to BSEL17 for indicating individual bytes, and as SELO to

SEL16 for indicating individual words.

However, only the low-order bytes of the first two CSRs will generate an interrupt in the front-end

microprocessor when there are bit changes.

3.2 BSELI1 DEFINITIONS
The run bit, together with the master clear (MCLR) bit, determines whether the self-testis executed or not.
If the MCLR bitis set with the run bit clear, then the application firmwareis executed If the MCLR bitis
set together with the run bit, then the self-testis executed first.

‘The KMV11 will indicate thatit is ready to accept application commands by clearing the MCLR bit. If the
run bitis still set, it means that the self-test has failed.

The read, write, and run bits can then be used to load, unload, or start the application firmware. Theerror

bitis used by the root firmware to indicate errors in the read, write, or run command parameters.

15
RUN

| MCLR | WRITE

READ

| 9

s
ERROR

RD 972

Figure 3-1
Bit

Name

Error

BSEL1 Bit Layout in Application Mode |
Function

This bit will be set to 1 after a read, write, or run error (odd or
nonexistent address).

11‘
12

This bit must be O in application mode.

Read

This bit should be set if datais to be read from the front-end
RAM memory.

This bit must be O in application mode.
This bit must be O in application mode.

3-1

Bit

Name

Function

Write

This bit should be set if data is to be written to the front-end

MCLR (Master
Clear)

When set, this bit requests power-up initialization to clear the
hardware and restart the root firmware. The bit is cleared by the

RAM memory.

KMYV11 on completion of initialization.

Run

When this bit is set together with the MCLR bit, the self-test
will be executed. If an error occurs the run bit will stay set when
the MCLR drops. When it is set without the MCLR bit, transfer
to the application firmware transfer address will be performed.

load and start Lhe KMV11
RO
R3
RS

=
=
=

number
CSR of
RAM

of words
the KMV

LOAD

write

ADDRESS

START=
S.L0AD

RUN

= buffer

= BSEL1

=
[
WRITE=
ERKROR=

containing

the

instructions

firmware start address
= flad in STATUS to indicate

BSEL1
BSEL1
BSEL1
EBSEL1

load

(1)

or comrare

MASTER CLEAR

RUN
READ

WRITE
ERROR

MER MER

BB WER B

e R

MED

R ER

AWIe MER

BUFF

MER

BR YER g

3.3 LOADING AND STARTING APPLICATION FIRMWARE
Load and/or compare example:

EDR

guard

actual
asdainst

the

suystem

Self-test

wait

hang

loors
the

execution takes

should
event

about

made

hardware

seconds.

failure,

srodram

CLRE

1(R3)

y MAKE

SURE

MASTER

CLEAR

s CLEARED

MOVE
f

#¥MCLRs1(R3)

sMASTER

CLEAR

KMV11

FMCLR!RUN»1(R3)

¥MASTER

CLEAR

KMVI11

BITR
ENE

FMCLRs1(R3)
1%

sAND START
sKMV11 ACK
sWAIT

RITE
ENE

¥FRUN»1(R3)
25%

yFOR FOSSIEBLE SELF-TEST:
sRUN BIT CLEARED?
s ERANCH FOR FOSSIERLE ERROR

MOVE
143

3-2

SELF-TEST

(0)

10%:

16%3

17%¢

MOV

¥RUFF»R4

rGET

BIT

¥S.LOADYSTATUS

»IS

IT
IF

BUFFER

ADDRESS

LOAD?

BEQ

15%

yBR

MOV

RS»4(R3)

yLOAD

ADDRESS

MOV

(R4)y6(R3)

yLOAD

DATA

SELS

BISE

FWRITE»1(R3)

DATA

*WRITE»1(R3)

y LOAD
yACK?

THE

RITE

COMFARE

ENE

11%

BITE

¥ERROR
1 (R3)

yWAIT
y ERRORT

BNE

25¢%

MOV

BISH
RITE

R3+s4(R3)
#READ»
1 (R3)
¥READs1(R3)

s READ

ENE

16%

sWAIT

QUIT

rLOAD

ADDRESS IN
THE LDATA

SELA4

sACKT

EITE

¥ERROR1(R3)

y ERRORT

ENE

20%

QUIT

CMF

(R4)
s 6(R3)

s COMFARE

BNE

29%

y ERROR

ALDD
ADD

$¥2sR4
$¥29RO

sNEXT
y NEXT

DEC

fUPDATE

ENE

10%

MOV
MOVE

¥START»4(R3)
#FRUN»
1 (R3)

sSTART

BEITE

#FRUNs
1 (R3)

s ACK?

ENE
BITE

17%
$ERROR1(R3)

s ERRORT

ENE

20%

30%

BUFFER ADDRESS
ADDRESS

LOAD

COUNTER

START
IT

sWAIT
QUIT

s SUCCESS

SEC

DONE

y ERROR

RETURN

3-3

DATA

NEXT4+4s

fSET

CCC

SEL4

ADDRESS

FIRMWARE

Byt

CHAPTER 4
APPLICATION F IRMWARE DEVELOPMENT

4.1
KMVI1l1 I/O PROGRAMMING
~
|
Five functional elements make up the I/O section of the KMV11. These elements provide the
communications path between the host and the line(s).
~
The line end is made up of:

e
e
e

The PUSART (Programmable USART) integrated circuit
Modem control and monitor registers
The line clock generators used for null modem connections and maintenance purposes.

The host interface is made up of the CSR or SEL registers and DMA registers.

In addition miscellaneous logic is provided to generate Q-bus DC OK assertion, as well as a real-time
clock to implement communication protocol timer functions.

The information contained in the following sections should enable the application firmware programmer

to design efficient HDLC or SDLC front-end firmware.

The architecture of the KMV11 is primarily designed for dual-line operation. The basic version(KMV11-

A), however, provides line transmitters and receivers for one line only. This documentis valid for both

single- and dual-line configuratmns Differences between the two will be pointed out in the appropriate
section.

4.1.1 Front-End Processor Address Space
The DC1'11 microprocessor address space is divided into three sections: a read-write memory section of
16K words, a read-only memory section of 4K words, and an I/O address space of 12K words.
NOTE
Addresses are given in octal notation in this
chapter.

4.1.2

1/0 Register Assignment

Within the I/O register space, from 100 000g to 160 0003, are the locations of the device registers for the
five functional components. Each component has a subaddress space of 10 000g bytes.

The functional component subaddress spaces are:

CSR and DMA registers (100 000 to 107 777)
Line controller IC (integrated circuit) (110 000 to 117 777)
Clock IC (120 000 to 127 777)
Peripheral port IC (130 000 to 137 777)
Q-bus control (140 000 to 147 777).

177776

64K BYTES
ROOT FIRMWARE

ROM

DIAGNOSTIC ROUTINES
160000

56K BYTES

|70 REGISTERS

SPACE
100000

32K BYTES

APPLICATION FIRMWARE

SCRATCH PAD

200

)

RAM

SELF TEST RX TX BUFF
—
|
INTERNAL INTERRUPT

VECTORS

/
RD 963

;

Figure 4-1

KMVI11 Memory Map

Address Range

Destination

Address

Registers

100 000
107 777

CSR RAM

100 000
100 002
100 004
100 006
100 010
100 012
100 014
100 016

CSR O
CSR
2
CSR 4
CSR 6
CSR 10
CSR 12
CSR 14
CSR 16

110 000
117 777

7201 PUSART

(only loworder bytes
are used)

100 020
100 022
100 024
100 026
100 030
100 032
100 034
100 036

DMA DATA IN
DMA DATA OUT
DMA ADDRESS IN
DMA ADDRESS OUT
ROOT FW SCRATCH
ROOT FW SCRATCH
EXTENDED ADDR IN
EXTENDED ADDR OUT

110 000
110 002
110 004
110 006
110 010
110012
110 014
110 016

CHA RX BUF
CHA TX BUF
CHA STATUS
CHA COMMAND
CHB RX BUF
CHB TX BUF
CHB STATUS
CHB COMMAND

Address Range

Destination

Address

120 000
127 777

8254 Timer

120 000
120 002
120 004
120 006
120 010
120 012

(only low~order bytes
are used)

Registers

LINE CLOCK 1 RD
LINE CLOCK 1 WR
LINE CLOCK 2 RD
LINE CLOCK
2 WR
RT CLOCK RD
RT CLOCK WR

120 014
120 016

130 000
137 7717

8255 1/0

(only loworder bytes
are used)

140 000

Q-bus Control

130 000
130 002
130 004
130 006
130 010
130012
130 014
130 016
140 000

147 777

150 000
157 777

not used
|
CLOCK CONTROL WR

A PORT READ

not used
not used

C PORT WRITE
not used
-

B PORT WRITE

not used
8255 CONTROL WR
QIRQ, QDCOK

RESERVED

RO = Read-Only register
WO = Write-Only register

R/W= Read-Write register
"NOTE
Only MOV or MOVB instructions may be used to
operate on RO and WO registers. Instructions
which first read, then perform changes in internal
processor registers and write the results back like
INC, BICB, BISB, ADC, and so on, may only be
used with R/W registers.

4.1.3

Front-End Processor Interrupt System

The DCT11 microprocessor uses a 4-level interrupt system with eight hardwired vectors. For a detailed
explanation of the leveled and vectored interrupts of the DCT11 microprocessor please refer to the
DCT11 Microprocessor User’s Guide, Chapters 1 to 5.

Requesting Device
RX data channel A
RX data channel B
TX data channel A
TX data channel B
PUSART spemal cond.
Timer
CSR 0 transaction
CSR 2 transaction

Priority

Vector

Vector assignments and priorities are as follows:

140
150
100
110
120
130
60
70

NOTE

These interrupts are not self-clearmg A request
stays as long as the interrupting condition has not
been taken care of.

]

LINEY

To acknowledge the interrupts, the following actions have to be taken for each of the listed interrupt
conditions:

RX DATA channel A
vector 140

Read channel A receive buffer

RX DATA channel B

~ Read channel B receive buffer

vector 150

TX DATA channel A
vector 100

Load channel A transmit buffer

TX DATA channel B
vector 110

- Load channel B transmit buffer

PUSART special conditions
vector 120

Issue a Reset Extemal/ Status Interrupts (RE/SI)

command

Refer to Secticfi 4,35 Line Controller Interface
Timer
vector 130

Disable RTC, enéble RTC for next timer interrupt
(port C, bit D0)

CSR 0 transaction

Disable CSR 0 interrupt, enable CSR 0 interrupt for

CSR 2 transaction
vector 70

Disable CSR 2 interrupt, enable CSR 2 interrupt for

vector 60

next CSR O transaction (port C, bit D6)

next CSR 2 transaction (port C, bit D7).

4-4

4.2

CSR AND DMA INTERFACE

4.2.1
CSR and DMA Address Register Description
Addresses 100 000 to 100 016 are implemented within the ‘CSR RAM’. These eight words are referred to
as CSR or SEL registers, and can be accessed by the host to implement data ports for command and
response transactions. Except as stated belew bits may be assxgned according to the desired host to frontend interaction.
|

Excepticn
e

BSELI ( address 100 001)is used by the roct firmware and should not be reassxgned

The use of BSELO and/or BSEL2is reccmmended fer implementation of a handshake prc:tacel between
host andfront-end. Thisis because a write access from the host to either BSELO or BSEL2 may generate a
vectored interrupt in the front-end processor if this feature has been enabled. (See the description in

Appendix A of the KMV11 Technical Manual.)
Address 100020is the ‘DMA datain’ register. Data requested via DMA from the hest s memory may be
readin this register.
Address 100 022 is the ‘DMA data out’ register. Data to be transferred via DMA into the host memory
will be written into this register.

Address 100 024 is the ‘DMA address in’ register. The contents of this location specify the 16 low-order
bits of the host memory address used for a ‘DMA in’ transfer.

Address 100 026 is the ‘DMA address out’ register. The contents of this IOCation specify the 16 low-order

bits of the host memory address used for a ‘DMA out’ transfer.

Addresses 100 030 and 100 032 are reserved locations for use by the root firmware.

Address 100 034is the ‘extended addressin’ register. The contents of its low-order byte specify the six
high-order bits of the host memory address used for
action of writing to this location.

a‘DMAin’ transfer. The DMA itselfis initiated by the

Address 100 036is the ‘extended address out’ register. The contents ofits low-order byte specify the six
high-order bits of the host memory address used for a ‘DMA out’ transfer. The DMA itselfis initiated by
the action of writing to this location.
Register Bit
Low-Order Byte

XADDR Bit

2
3
4
5

18
19
20
21

4-5

4.2.2 CSR and DMA Programming
The interface to the Q-bus host is made up of two main functional elements:
1.
2.

CSR interface
DMA interface.

The CSR interface is made up of eight 16-bit registers, which can be accessed by the DCTI11
microprocessor, using the addresses from 100 000 to 100 016. This dual-port memory can be accessed by
the host at addresses from 76xx00 to 76xx16 (xx is defined by on-board DIP switch settings). Bit 14 of
SELO, when set by the host, generates an unmaskable HALT interrupt, which restarts the root firmware.
Except for the above-stated functions, all the other register bits may be defined to set up any desired host to
front-end interaction. Use of the low-order bytes of SELO and/or SEL2 is recommended for handshaking
protocol, as a write by the host to the low-order bytes of these registers will generate an interrupt in the
front-end processor at vector 60 and vector 70, in that order. To enable these interrupts, the priority of the
processor must be lower than level 4, and individual CSR interrupt enable bits must be set.
1.
2.

CSRO interrupt enable:
CSR2 interrupt enable:

port C
port C

bit D6 = 1
bit D7 = 1

Siiigy

HETE

To acknowledge these interrupts, the enable bits must be cleared, and may then again be set for a new
cycle.

All CSR registers are read and write accessible.

The DMA interface is divided into two unidirectional Channels:
1.
2.

The OUT DMA channel — front-end to host
The IN DMA channel — host to front-end.

The channels allow a 1-word transfer per transaction between the DMA registers and the host memory.
The sequences indicated below must be followed even when only 16-bit addressing is needed, as DMA
hardware is only triggered by the action of a write'into the extended address registers.
NOTE
Byte transfers in DMA mode are not available.

If the DMA cycle does not finish within the time defined by the Q-bus timing specifications, a timeout
occurs and bit D7 in port A of the peripheral IC is set.

In order to allow the KMV 11 to address other devicesin the I/O page, bit D3in port B can be set to allow
access to the I/O page.
In order to allow the DMA registers to be loaded without a DMA cycle taking place, bit DS in port B must
be clear. This bit should be set when DMA cycles have to take place.

4-6

@%130000

EMI

"TIMEQUT

DEC

"WORD

TSTH

ANTR
100026
XOHDRR%100036

LOAD
LOAD

ADDRESS
EXTENDED

MOV
MOVE

ENARLE

NATA

TRANSFER

I'MA

OUT

~
ADDRESS

AND

CHECK

SURTRACT
ONE FROM WORD COUNT

ERROR®

COUNT®

I'MA

Cdgs

$¥40sC%130012
NATAC#100022

MOV
MOV

Programming Sequence for DMA OUT - First transfer:

4.2.2.1

INITIATE

FOR

DIMA

TIMEOQUT

Subsequent transfers:
LOOF MOV

NATA@H100022

DAaTA

DIMA

OUT

REGI STER

¥2,0%#100026

UFI'ATE

AIC

@%100036

UFDATE EXTENDED ARDRESS
AND INITIATE DMA
CHECK FOR TIMEOUT

THTE

@%#130000

EMI

"TIMEOUT

NEC
ENE

"WORD
LAQOF

ADDRESS

ERROR®

COUNT®

SURTRACT ONE FROM WORD
LOOF UNTIL ALL WORDS

TRANSFERRED

owgs

ANNORESS

AND

INITIATE

CHECKR

XODRC#100034

*TIMEOUT

ERROR®

"WORD

MOV

1000205 DATA

¥2,024100024

@#100034

TS&TR

C¥130000

EM1

“WORD

BNE

LOOF

COUNT*®

READ

FOR

ADDRESS

IIMA

TIMEOUT

DATA

UFDIATE ADDRESS

UFDATE EXTENDED ADDRESS
AND INITIATE DMA

CHECK

FOR

TIMEOUT

REAID

DATA

LOOF

UNTIL

TRANSFERRET

4.3 LINE CONTROLLER INTERFACE
The line controller is a 7201 PUSART, or equivalent IC.
The following protocols may be implemented:

1.
2.
3.

EXTENDED

MOV

NEC

COUNT"

"TIMEQOUT ERROR®
C¥#100020IIATA

TRANSFER

DECKEMENT WORDN COUNT

NEC

@%$130000

EP wme

TSTE
BMI

DIIMA

LOOF
3

MOVE

ENARLE
LOAD
LOAD

100024

$40,%#130012
ANNIR

MoV

MOV

wgw

Programming Sequence for DMA IN - First transfer:

4.2.2.2

Asynchronous
Character synchronous (monosync, bisync)
Bit synchronous (SDLC, HDLC).

ALL

WORDS

COUNT

Error-checking features:
1.
2.
3.
4.
5.

Parity (odd, even)
CRC-16
CRC-CCITT
Break/abort detection
Framing error detection.

The line controller PUSART device cannot function until it is completely programmed to the required

configuration. This programming is done by writing appropriate bit patterns into the PUSART device’s
control registers. The PUSART contains eight such control registers for each of its two channels. Initial
access is to the first of these registers only: control register 0. Access to the other seven registers is through
this control register O, for each channel.
~
When the PUSART has been programmed, its function and operation can be checked and monitored by
the examination of its status registers for each of the two channels. Access to all three of these registers is
through the appropriate channel’s control register 0.
Figures 4-2 to 4-10 show the summarized functions of the eight control registers; and F igures4-11to4-13
show the summarized functions of the three status registers.

Lo Del Ds' D4| Dsl | 2!

o)
0
1

O
O

O
1

~0=-0—-0-0-

- —200==00

22220000

t
REGISTER
1

1
O

0
1

POINTER FOR

THE SELECTION OF
A READ/WRITE
REGISTER

NULL CODE
SEND ABORT (SDLC)

RESET EXT/STATUS INTERRUPTS

CHANNEL RESET
ENABLE INT ON NEXT Rx CHARACTER

RESET Tx INT/DMA PENDING

ERROR RESET

|
END OF INTERRUPT (EOI - CHAN. A ONLY)

NULL CODE
RESET Rx CRC CHECKER
RESET Tx CRC GENERATOR
RESET Tx UNDERRUN/EOM LATCH
RD 970

Figure 4-2

Control Register 0, Bit Functions

[07]06] 05| 0a[ 0] 02| 01 [ 0o)
_

O
O
1

O
1
0
1

Tx INT ENABLE

STATUS AFFECTS VECTOR (CH.B ONLY)

RxINT/DMA DISABLE
RxINTON FIRST CHARACTER
INTON ALL Rx CHARACTERS
~

l L EXT INTENABLE
|

(PARITY AFFECTS VECTOR)
INT ON ALL Rx CHARACTERS
(PARITY DOES NOT AFFECT
VECTOR)
|

OR ON
SPECIAL RECEIVE
| CONDITION
*
)

— \WAIT ON RECEIVER/TRANSMITTER

ALWAYS ZERO
WAIT ENABLE
RD 971

Figure 4-3 Control Register 1, Bit Functions

[o7]
2] o [ 0] 03] o2 o1 [ oo
0)

1
0O

ADMA, CH. BINT
CH.
BOTH CHANNELS DMA

UNDEFINED

0
1

BOTH CHANNELS INTERRUPT

SYSTEM
CONFIGURATION
:

- PRIORITY RXA>RxB>TxA>TxB

PRIORITY RxA>TxA>RxB>TxB

0
o)

O
1

8085 MODE 1
8085 MODE 2

8086 MODE

UNDEFINED

- INTERRUPT VECTORED/NON-VECTORED
e— ALWAYS ZERO

O
1

RTSBPIN 10
SYNCB PIN 10
RD 967

Figure 4-4

Control Register 2 (Channel A), Bit Functions

4-9

[27] 0|5 [ 04 | 0a] 02 |01 | oo)

[ v
V2

V3
V4

INTERRUPT
VECTOR

V5
V6

Figure 4-5

RD 968

Control Register 2 (Channel B), Bit Functions

lDlealD5lD4ngl02I01lDol

vkth i

l l— Rx ENABLE

)

- SYNC CHARACTER LOAD INHIBIT
ADDRESS SEARCH MODE (SDLC)

;
|

—

— — Rx CRC ENABLE

ENTER HUNT PHASE
- O-=0

AUTO ENABLES

Rx 5 BITS/CHARACTER
Rx 7 BITS/CHARACTER
Rx 6 BITS/CHARACTER

Rx 8 BITS/CHARACTER

RD 969

Figure 4-6 Control Register 3, Bit Functions

l L PARITY ENABLE

- =200

- =00

——

PARITY EVEN/ODD

SYNC MODES ENABLE

1
o)

1 STOP BIT/CHARACTER
1 1/2 STOP BITS/CHARACTER
2 STOP BITS/CHARACTER

O
1

8 BIT SYNC CHARACTER
16 BIT SYNC CHARACTER

SDLC MODE (01111110 FLAG)

EXTERNAL SYNC MODE

X1 CLOCK MODE

0O
1

X32 CLOCK MODE
X64 CLOCK MODE

X16 CLOCK MODE

Figure 4-7

RD 962

Control Register 4, Bit Functions

4-10

L Tx CRC ENABLE
RTS

CRC-16/CCITT
Tx ENABLE
» SEND BREAK

o)
0

O
1

Txb5 BITS (OR LESS)/CHARACTER
Tx 7 BITS/CHARACTER

O
1

Tx 6 BITS/CHARACTER
Tx 8 BITS/CHARACTER

- DCR

Figure 4-8

RD 961

ferihi

Control Register 5, Bit Functions

|D7|D6lD5|D4nglDz D1 Doi

! L SYNC BIT O
‘

~
—
—
-

SYNC BIT 1
SYNC BIT 2
SYNCBIT3

| ALSO SDLC

( ADDRESS FIELD
|

'SYNCBIT4
SYNCBIT5
SYNC BIT 6
SYNC BIT 7

RD 960

Figure 4-9

Control Register 6, Bit Functions

Dle1lD0l

|
SYNC BIT 8

—

SYNC BIT 9

SYNC BIT 10
SYNC BIT 11

mi2

SYNC BIT

SYNC BIl T

SYNC BIT 15

[

“

NOTE: (1) FOR SDLC IT MUST BE PROGRAMMED
TO ‘01111110 FOR FLAG RECOGNITION

Figure 4-10

Control Register 7, Bit Functions
4-11

D 964

lD‘;lel Dsl%l D3|Dzl Dy l Dol

L Rx CHARACTER AVAILABLE

INT PENDING (CHANNEL A ONLY)

Tx BUFFER EMPTY
‘

SYNC/HUNT

USED WITH

) EXTERNAL/STATUS

CTS
Tx UNDERRUN/ECM
BREAK/ABORT

INTERRUPT’ MODE

RD 965

Figure 4-11

Status Register 0, Bit Functions

[o7] 6] 05| 04 ] 0a 02 o1 0o]

L ALL SENT
| FIELD

| FIELD

BITSIN

SECOND

- PREVIOUS

OO0
-0 =0 =

BYTE

0
0
0

5
6
7|

RESIDUE DATA FOR
EIGHT Rx BITS/
CHARACTER

- PROGRAMMED

1.
;
\

- PARITY ERROR

Rx OVERRUN ERROR
CRC/FRAMING ERROR

END OF FRAME (SDLC)
RD 966

Figure 4-12

Status Register 1, Bit Functions

4-12

[o2]0s] 0] 0] 25] 22| °1[ 20

| =g

v2@

v3(® \ INTERRUPT

v4(2)

( VECTOR

NOTES: @ USED WITH SPECIAL RECEIVE CONDITION MODE.
~

VARIABLE IF 'STATUS AFFECTS VECTOR' IS
PROGRAMMED.
|
RD 974

Figure 4-13

Status Register 2, Bit Functions

4.3.1
Line Controller Register Description
Access to the PUSARTis provided by the followmg data or control bytes.
4.3.1.1
Channel A Receive Buffer (Address 110 000)
— This read-only register contains the character
received and assembled from the serial line, right justified, with the least significant received bit first. The
PUSART has an internal 4-byte F IF O (First In, Fzrst Out) buffer for data and corresponding status.

4.3.1.2 Channel A Transmit Buffer (Address 1 10 002)— The character to be transmittedis loaded
into this write-only register right justified with the least significant transmitted bit first.

4‘,3}1.3 Channel B Receive Buffer (Address 110 010) - This read-anly register is the same as the
channei A receive buffer, but is used only with KMV1 1~B.

4.2.1.4 Channel B Transmit Buffer (Address 110 012) — This write-only register is the same as the
channel A transmit buffer, but is used only with KMV11-B.

4.3.1.5 Channel A Command Registers (Address 110 006) — The seven write-only command
registers per channel are accessed through this address. It is also used to load the address pointer for the
two read-only status registers.

All control and status registers except Control Register 2 (CR2) are separately maintained for each
channel. CR2is linked with the overall operation of the PUSART and contains dlfferent meanings when
addressed through different channels.

When initializing the PUSART, CR2A (and CR2B if wanted) should be programmed first to set up the
PUSART processor/bus interface mode. Each channel to be used may then be programmed separately,
beginning with control register 4 to set the protocol mode for that channel. The rest of the registers may
then be programmed in any order.

4.3.1.5.1

Control Register 0 — The layout of this register is shown in Figure 4-14, and the register itself

is described in Table 4-1.

4-13

CRC CO}NTF\‘OL

C?MMAN?

RD 951 ’

Figure 4-14 Control Register 0 Layout
Table 4-1

Bit

D 20

Control Register 0 Description

Name

Description

The registe; pointer specifies which register number is accessed at

pointer

the next control register write or status register read. After a
hardware or software reset, the register pointer is cleared to O.
Therefore, the first control byte goes to control register 0. When the
register pointer is set to a value other than 0, the next control or status
(C/D=1) access is to the specified register, after which the pointer is
cleared to 0. Other commands may be combined in control register O
together with the setting of the register pointer.

D 5-3

Command

Commands normally used during the operation of the PUSART are

<000>

Null

<001>

Send abort

When operating in HDLC mode, this command causes the

<010>

Reset
external/
status

When the External/Status Change (E/SC) flag is set, the condition
bits D3 to D7 of status register 0 are latched to allow the detection of
short pulses that may occur. The Reset External/Status Interrupts

grouped in control register 0. They are:

This command has no effect and is used when it is only necessary to

set the register pointer or issue a CRC command.

interrupts
|

<011>

- Channel
Reset

<100>

Enable

PUSART to transmit the HDLC abort code, issuing from 8 to 13
consecutive 1s. Any data currently in the transmitter or the
transmitter buffer is destroyed. After sending the abort, the transmitter
returns to the idle phase (flags).

(RE/SI) command clears a pending interrupt and reenables the
latches so that ng:w;%interrupts may be sensed.

A Channel Reset (CR) command to channel A clears the internal
interrupt prioritization logic. This does not occur when a CR
command is issued to channel B. All control registers associated
with the channel to be cleared must be initialized again.

When operating the PUSART in Interrupt on First Character Only

interrupt
on next

(IFCO) mode, this command may be issued at any time (normally at
the end of a block or frame), to reenable the interrupt logic for the

character

next received character.

4-14

Table 4-1

Bit

Name

<101>

Reset
pending
transmitter
buffer
interrupt
or DMA
request

Control Register 0 Description (Cont)

Description
A pending Transmitter Buffer Becoming Empty (TBBE) interrupt or
DMA request may be cleared without sending another character, by
- issuing this command (normally at the end of a block or frame). A
new TBBE interrupt or DMA request is not made until either (1)
another character has been loaded and transferred to the transmitter
shift register, or (2) if operating in synchronous or HDLC mode, the
CRC character has been completely sent and the first sync or flag

character loaded into the transmitter shift register.
<110>

Error

This command clears a Special Receive Condition (SRC) interrupt.

reset

It also reenables the Parity Error (PE) and Overrun Error (OE)

latches that allow the testing for these errors at the end of a block or
frame.
<111>

End of

Once an interrupt request has been issued by the PUSART, all lower

interrupt

priority internal and external interrupts in the daisy chain are held
off. This permits the current interrupt to be serviced, while allowing
higher priority interrupts to occur. At some point in the interrupt
service routine (normally at the end), it will be necessary to issue the
End of Interrupt (EOT) command to channel A. This enables the
daisy chain, and allows any pending lower priority internal interrupt
requests to occur.

D 7-6

<00>

<01>

CRC control

These commands control the operation of the CRC generator/

Null

This command has no effect and is used when issuing other
commands or setting the register pointer.

Reset

This command clears the CRC checker to O when the channel is in

receiver

synchronous mode, and sets it to all 1s when in HDLC mode.

commands

checker logic.

CRC checker
<il>

Reset
transmitter
CRC checker

This command clears the CRC generator to O when the channel is in
synchronous mode, and sets it to all 1s when in HDLC mode.

<11>

Reset
IDLE/CRC
Latch

This command clears the IDLE/CRC latch so that when a transmitter
underrun condition occurs (that is, the transmitter has no more
characters to send), the transmitter enters the CRC phase of
operation and starts to send the 16-bit CRC character computed up
to that point. The latch is then set so that, if the underrun condition
continues, idle characters are sent following the CRC. After a
hardware or software reset, the latch is in the set state.

4-15

4.3.1.5.2

Control Register 1 - The layout of this register is shown in Figure 4-15, and the register itself

is described in Table 4-2.
D7

l 0

)

RECEIVER
INT,\JMODE
l SAV l TIE l E/SlEl
|

Figure 4-15

Table 4-2

RD 952

Control Register 1 Layout

Control Register 1 Description

Description

Bit

Name

External/
status

interrupt

enable

When this bit is set to 1, the PUSART issues an interrupt when any

of the following occur:

1. Transition of 109 input
2. Transition of 106 input

3.
4.

Transmitter

interrupt
enable

D 4-3

HDLC abort detection or termination, IDLE/CRC latch

becoming set (CRC being sent).

When this bitis set to 1, the PUSARTissues an interrupt when either
of the following occur:

The character currently in the transmitter buffer is transferred to
the shift register (transmitter buffer becoming empty)

Thetransmitter enters idle phase and starts transmitting sync or
flag characters

When this bit is cleared to 0, the fixed vector programmed into
CR2(B) during PUSART initializationis returnedin the interrupt

Status
affects
vector

Entering or leaving synchronous hunt phase (break detection or

termination in async mode)

acknowledge sequence. When this bit is set to 1, the vector is
modified to indicate the cenémen that caused the interrupt.

Receiver

This field controls how the interrupt or DMA loglc of the PUSART

interrupt

handles the character recelved condition..

mode

<00>

Disable character mode — The PUSART does not issue an interrupt
or a DMA request when a character has been received.

4-16

Table 4-2

Bit

Name

<01>

Control Register 1 Description (Cont)

Description
Interrupt on First Character Only (and issue a DMA request)
(IFCO) - In this mode, the PUSART issues an interrupt only for the
first character received after an Enable Interrupt on Next Character
(EINC) command (CRO) has been given. If the channel is in DMA
mode, a DMA request is issued for each character received,
including the first. This mode is normally used with the PUSART in
DMA or block transfer mode to tell the processor that the beginning
- of an incoming block or frame has been received. Note that there is

no actual DMA hardware in the KMV11, but the facility is used to
simplify the firmware and the operation.
<10>

Interrupt (and issue a DMA request) on every received character
(parity error is a special receive condition) — In this mode, an
interrupt (and DMA request, if DMA mode is selected) is issued
when there is a character present in the receiver buffer. A parity error
is considered a special receive condition. Note that there is no actual
DMA hardwarein the KMV1 1, but the facilityis used to simplify the
firmware and the operation.

<11>

Interrupt (and issue a DMA request) on every received character
(parity error is not a special receive condition) — This mode is the
same as above except that a parity error is not considered a special
receive condition. The following are considered special receive

conditions and, when SAYV is enabled, cause an interrupt vector
different from that caused by a Received Character Available
(RCA) condition:

Overrun error
Asynchronous framing error
Parity error (if specified)
HDLC end of message (final flag received).

4.3.1.5.3 Control Register2 (Channel A) The layout of this reglster is shownin Figure 4-16, and the
register itselfis describedin Table 3-3.

VECTOR MODE

INTERRUPT

IPR l DMA MODE
RD 953

Figure 4-16

Control Register 2 (A) Layout

4-17

Table 4-3
Bit

Name

Control Register 2 (A) Description

Description

DMA mode
select

RTINS

Setting this field controls whether channels A and B are used in
-~ DMA mode (that is, data transfers are performed by a DMA
controller) or in non-DMA mode where transfers are performed by

the processor in either polled, interrupt, or block transfer modes.
D 1-0
<00>

<01>
- <10>

<1 1>

D 5-3

Priority

Mode
-

Channel A non-DMA, channel B non-DMA

Chamnel A DMA, channel B non-DMA

(recommended for KMV11-A)

Channel A DMA, channel B DMA (recommended
for KMV11-B)
Illegal

This bit allows the selecnen of the relative priorities of the different
interrupt and DMA conditions according to the application.

Interrupt
vector

D2=0
~
|

priority 1 = channel A
RxA > TxA > RxB > TxB > external

D2=1
|

priority 1 = receive channel A or B
RxA > RxB > TxA > TxB > external

This field determines how the PUSART will respond to an interrupt
acknowledge sequence from the processor. As there is no provision

mode

for hardware vectoring, D5 should always be programmed to 0. See
also Figure 4-4. The value programmed into D4 will determine

which three bits will become affected when the interrupt vector is

read back: 0 to 2, or 2 to 4. Refer also to Section 4.3.1.8 and to

Figure 4-27. Itis recommended that D3 of this field should be always
~ programmed to 0. Thisbit provides a facility not Sfipportedin the
KMV11. Programming both D3 and D4 to 1 is illegal.

4.3.1.5.4 Control Register 3 --The layeat of this regxsteris shownin Figure 4-17, and the register itself
is describedin Table 4-4.

D3
. D2

DI
. DO

BITS/
CHAR&CTER
l AE| l EHP I RCE I ASM!| SCLI| l RE l
RD 954

Figure 4-17 | Control Register 3 Layout

4-18

- Table 4-4

Control Register 3 Description

Bit

Name

Description

Receiver
enable

After the channel has been completely initialized, setting this bit to 1
allows the receiver to start operation. This bit may be cleared at any
time to disable the receiver.

Sync
character
load
inhibit

In synchronous mode this bit inhibits the transfer of sync characters
to the receiver buffer, so performing a ‘sync stripping’ operation. The
load inhibit does not exclude sync characters embedded in the block
or frame from the CRC computation. Therefore this feature may
only be used to strip leading sync characters at the beginning of a
block or frame. Synchronous protocols using other types of block
checking, such as checksum or LRC, are allowed to strip embedded
sync characters with this bit.

Address
search
mode

In HDLC mode, setting this bit places the PUSART in address
search mode. Character assembly does not start until the 8-bit
character (secondary address field) following the starting flag of a
message matches either the address pregrammed into CR6 or the
global address 377.
;

Receiver
CRC
enable

This bit enables or disables (1 = enable) the CRC checker, in order
to control the exclusion of individual characters from the total CRC
computation. The PUSART features a 1-character delay between
the receiver shift register and the CRC checker. Enabling or

disabling takes effect with the last character transferred from the shift
register to the receiver buffer. Therefore, one full character-time is
available in which to read the character and determine whether it
should be included in the CRC computation.

D35

D 6-7

Enter hunt
phase

- Auto
enables

Number of
received
bits per
character

The PUSART receiver automatically enters sync hunt phase after a
reset. Sometimes it is
necessary to enter this phase again, for
example, when synchronization has been lost, or, in HDLC mode, to
ignore the current incoming frame. Writing a 1 into this bit at any
time after initialization causes the PUSART to enter sync hunt
phase again.

Setting this bit to 1 causes the CCITT 109* and CCITT 106* inputs
to perform as enable inputs to the receiver and transmitter, in that
order. This feature is not supported on the KMV11.

This field specifies the number of data bits assembled to make each

character. This value may be changed while a character is being
assembled, and, if the change is made before the new number of bits

has been reached, it affects that character. Otherwise the new
specifications take effect on the next character rcceived.

* Refer to Table 4-14 for equivalent EIA signals.

4-19

Table 4-4

Bit

Name

Control Register 3 Description (Cont)

Desériptiefi
D6 D7

Bits/Character

<00>

<01>
<10>

6
7
8

<1l1>

4.3.1.5.5 Control Register 4 — The layout of this register is shown in Figure 4-18, and the register itself
is described in Table 4-5.

CLOCK RATE
2

SYNC MODE

STOP BITS l PE/O l PE I

]

RD 975

Figure 4-18

Control Register 4 Layout

~ Table 4-5 Control Register 4 Deseriptian

Bit

~ Name

Parity
enable

Déscripti&n
~

|| |

Setting this bit to 1 adds an extra data bit containing parity
information to each transmitted character. Each received character
is expected to contain this extra bit and the receiver parity checker is
|

enabled.

D 4-2

Parity

Programming this bit to 0 when parity is enabled causes the

even/odd

- transmitted parity bit to take on the value needed for odd parity. The
received character is checked for odd parity. On the other hand, a 1 in
this bit indicates even parity generation and checking.

Number
of stop

This field specifies whether the channel is used in synchronous (or
HDLC) mode or in asynchronous mode. In asynchronous mode, this

bits/
sync mode

field also specifies the number of bit-times used as the stop bit length
by the transmitter. The receiver always checks for one stop bit.
D3 D2

Mode

<00>
<01>
<10>
<11>

Synchronous modes
Async 1 bit-time (1 stop bit)
Async 1.5 bit-times (1.5 stop bits)
Async 2 bit-times (2 stop bits)

4-20

Table 4-5

Bit

Name

D 54

Sync mode
|

Control Register 4 Description (Cont)

Description

When the NSB/SM field is programmed for synchronous modes
(D2 and D3 both clear), this field specifies the synchronous format
to be used. In asynchronous mode, this field is ignored. The
synchronous modes are:

DS D4
<00>

<01>
<10>
<l1>

D 7-6

Clock rate

Mede |
8-bit internal sync character (monosync)

16-bit internal sync character (bisync)
HDLC
Illegal

The field specifies the relationship between the transmitter and

receiver clock inputs (TxC, RxC) and the actual data rate at TxD
and RxD. When operating in a synchronous mode, a 1-times clock
rate must be specified. In asynchronous modes, any of the rates may
be specified; however, with a 1-times clock rate the receiver cannot
determine the center of the start bit. In this mode, external

synchronization of the samplmg (rising) edge of RxC with the datais

needed.

D7 D6 Clock Rate
<00>
<01>

<10> -

<11>

Clock rate = 1 X Data rate
Clock rate = 16 X Data rate

Clock rate = 32 X Data rate

Clock rate = 64 X Data rate

4.3.1.5.6 | Control Register 5 - The layout of thisregister
is shown in Figure 4-19, and it is described in
Table 4-6.

l 0

. D6 _ D5

. D2

BITS/
I CHARACTER
l SB I TE| l oepeCPS l COTT]
o5 | TCE l
|

RD 976

Figure 4-19

Control Register 5 Layout

4-21

‘Table 4-6 Control Register 5 Description

Bit

Name

DO
TAVE

Description

Transmitter
CRC
enable

The CRC computation is enabled when this bit is programmedtoal,
~and it is disabled when the bit is programmed to 0. The enable or
~ disable does not take effect until the next character is transferred
from the transmitter buffer to the shift register. This makes it possible
to include or exclude specific characters from the CRC computation.
By setting or clearing this bit immediately before loading the next
character, the next character and following characters are either
- included or excluded from the computation. If this bit is O when the
- transmitter becomes empty, the PUSART goes to the idle phase,

without regard to the state of the IDLE/CRC latch.

CCITT 105

In synchmnous and HDLC modes, setting this bit to 1 causes the
CCITT 105* signal to go to the active (marking) state, and clearingit
‘to O causes it to go inactive (spacing). In asynchronous mode,

- clearing this bit to 0 does not cause CCITT 105 to go inactive until
‘the transmitter is completely empty. This feature makes it easier to
~ program the PUSART for use with asynchronous modems.

CRC

“This bit selects the polynomial used by the transmitter and receiver

select

polynomial (x16 + x15 + x2 + 1). When clear, it selects the CRC
CCITT polynomial (x16 4+ x12 4+ x5 + 1). In HDLC mode, it is

polynomial

for CRC generation and checking. When set, it selects the CRC-16

necessary to select CRC CCITT. Either polynomial may be used in
c:s,ther ‘s"ynchreneus m&des.

Transmitter , After a reset, the transmitted data output (TxD) is held high

enable

(marking) and the transmitter is disabled until this bitis set.

In asynchronous mede TxD stays hzgh untfl data 1s laaded fer
transmission.

When the transmitter is disabled in asynchronous mode, any
character currently bemg sent is eampleted before TxD returns to the
marking state.
|

In synchreneus and HDLC m@des the PUSAR‘T autamatxcally
enters idle phase and sends the programmed sync or flag characters.

If the transmitter is disabled dfiriilg the data phase in synchronous

mode, the current character is sent, then TxD goes high (marking).

In HDLC mode, the current character is sent, but the marking line
following is zero-inserted. That is, the line goes to spacing for one bittime out of every five.
The transmitter should never be disabled during the HDLC data
phase unless areset is to follow immediately. Whether a reset follows
or not, any character in the buffer register is held.
* Refer to Table 4-14 for equivalent EIA signals.

4-22

~
Bit

Table 4-6

Name

Control Register 5 Description (Cont)

Description

Disabling the transmitter durinthe
g CRC phase causes the rest ofthe
-

CRC character to be bit-substituted with sync (or flag). The total

number of bits transmitted is correct and TxD goes marking
after
they are sent.

If the transmitter is disabled during the idle phase, the remaind
er of
the sync (flag) character is sent, then TxD goes marking.
D4

Send break

Setting this bit to 1 immediately forces the transmitter output (TxD)

to spacing. This function overrides the normal transmitter output

and

destroys any data being transmitted although the transmitter stays in

operation. Clearing this bit releases the transmitter output.

D 6-5

Number of
transmitted

bits per
character

This field controls the number of data bits transmitted in each
character. The number of bits per character may be changed by
writing this field immediately before loading the first character to
use
the new specification.
|

D6 D5

Bits per Character

<00>

5 or less (see below)

<01>
<10>
<I11>

7
6
8

Normally each character is sent to the PUSART right-justified and

the bits not used are ignored. However, when sending five bits or

less
the data should be formatted as shown below to inform the PUSAR
T
of the correct number of bits to be sent.
|
|

1
1
1
1
0O

1
1
1
0
0

1
1
0
0
O

1
0
0
0
D4

0
0
0
D3
D3

0 0
DO
0
DI DO
D2 DI DO
D2 DI DO
D2 DI DO

4-23

Number of bits

1
2
3
4
5

4.3.1.5.7 Control Register 6 — The layout of this register is shcwnin Figure 4-20, and the register itself
is described below.
1

]

SYNC BYTE 1
3

)

]

RD 977

Figure 4-20

Control Register 6 Layout

Sync byte 1 is usedin the fc)lk}wmg modes:
Monosync

The 8- blt sync character transmitted during the idle phase

Bisync e Least szgmficant (first) 8 bits of the 16-bit transmit and receive sync character
HDLC

—

Secondary address value matched to the seccndary address field of the HDLC
frame when the PUSARTis in address search mode.

4.3.1.5.8 Control Reg:ster 7 — The layout of this reg:ster is shownin Figure 4~21 and the register itself
is described below.
£

]

SYNC BYTE 2
Fl

[

]

RD 978

Figure 4-21

Control Register 7 Layout

Sync byte 2 is used in the following modes:
Monosync —

The 8-bit sync character received

Bisync

Most significant (second) 8 bits of the 16-bit transmit and receive sync characters

HDLC

4.3.1.6

—

Channel

Must be programmed with the flag character, 01111110,, in control register 7 for

flag matching by the PUSART receiver.

BCommand Register— This wnte¥only register has the address 110 016. The seven

control register bytes of channel B are accessed through this register. Itis also used for the address pointer
to status registers 0, 1, and 2.

In the KMV11-B dual-line option all the control registers of channel B have the same functions as those of
channel A, except for control register 2. Both channel A control register 2 and channel B control register 2,
contain information which affects both channels. Both must be programmed.
In the KMV11-A single channel option, both channel A control register 2 and channel B control register 2
have the same functions as in the KMV11-B. Again both must be programmed. One additional control
registeris provzlded Itis control reglster 1, which s accessible through channel B addressing. Therefore its
functionsin the KMV11-A andin the KMV 11-B are different. Access to these two channel B registers is
through channel B control register 0, which has only limited functionsin this option. Figure 4-22 shows the
layout of control registers for both options (KMV11-A and KMV11-B).

Control registers with functions unique to channel B are shown in Figure 4-22.

4-24

4.3.1.6.1
Control Register 0 — This register is similar to that of channel A, with the following
s
|
|
|
|
exceptions:

e
e

Bits D6 and D7 have no meaning
Only three commands are valid:

<000>

Null (for loading the register pointer)

<010>
<011>

Reset external/status interrupts
Channel reset.

4.3.1.6.2 Control Register 1 — Only bits DO and D2 are valid in this register. Their functions are the
same as defined in control register 1 for channel A (see Figure 4-15). In the KMV11-A, however, the
external/status signals affected by this register are only CCITT 125% and CCITT 107*. See also Section
4.3.1.8.1 for the associated status.
KMV11-A

CHANNELA

CHANNEL B

(ADDRESS 110 006)

(ADDRESS 110 016)

11711

oo T17]

| [

[

;

" CR1TFUNCT

|00

EXTRAFUNCT

| 001

CR2 FUNCT

010

VECTOR

| o010

CR3 FUNCT

011

CR4 FUNCT

|100

CR5 FUNCT

101

CR6 FUNCT

110

CR7 FUNCT

111

+ LIMITED FUNCTIONS
|

KMV11-B

CHANNEL A

CHANNEL B

(ADDRESS 110006)

cro

|1]]

(ADDRESS 110016)

CR1 FUNCT

cro

CR1 FUNCT

001

*CR2 FUNCT

010

* VECTOR

lo1o

001

CR3FUNCT

011

~ CR3FUNCT

| o011

CR4 FUNCT

100

CR4 FUNCT

100

CR5 FUNCT

101

CR5 FUNCT

101

CR6 FUNCT

110

CR6 FUNCT

110

CR7 FUNCT

111

CR7 FUNCT

111

;

[1]1]

« AFFECTS BOTH
CHANNELS

RD 941

Figure 4-22

Control Registers in the KMV11-A and KMV11-B

* Refer to Table 4-14 for equivalent EIA signals.

4-25

4.3.1.6.3 Control Register 2 (Channel B) — The contents of this register are modified if the Status
Affects Vector (SAV) mode is enabled. The value of CR2(B) may be read at any time. This feature is most
useful in determining the cause of an interrupt when the PUSART is used in non-vectored interrupt mode.
§

]

INTERRUPT VECTOR
i

]

RD 943

Figure 4-23

Control Register 2(B) Layout

NOTE
Modem lines controlled and monitored through
the PUSART integrated circuit are inverted.

4.3.1.7 Channel A Status Registers — These read-only registers start at address 110 004. They contain
transmitter, receiver, and modem status information.
In fact, two internal registers may be read through this address. The address of the register is selected with
the channel A command register.

4.3.1.7.1
Status Register 0 — The layout of this register is shown in Figure 4-24 and the register itself is
described in Table 4-7.

BRE

l CRC l ~CCITT
el SYNCl ~CCITT
- Cov ! T BE IIP

l RCA l
RD 944

Figure 4-24

Table 4-7

Bit

only)

Status Register O(A) Layout

Status Register 0 Description

Name

Description

Received

When this bit is ség it indicates that one or more characters are

character
available

available in the receiver buffer for the processor to read. Once all of
the available characters have been read, the PUSART clears this bit
until a new characteris received.

Interrupt

The Interrupt Pending (IP) bit is used wzth the interrupt vector

pending

determine the interrupt status of the PUSART. This is more
important in non-vectored interrupt mode, when the processor must
poll each device to find the mterruptmg source. In this mode, the IP
bitis set when a READ SR2(B)is executed, the PRI input goes
active (low), and the PUSARTis requesting interrupt service. There
is no need to analyze the status registers of both channels to
determine if an interrupt is pending. If SAV is enabled and IP is set,
the vector read from SR2(B) will contain valid condition information.

4-26

Table 4-7
Bit

Name

Transmitter
buffer

empty

Status Register 0 Description (Cont)
Description

This bitis set when the transmitter bufferis empty, except during the
transmission of CRC (the PUSART uses the buffer to make this
- function simpler). After a reset, the bufferis ccmmdered empty and
the bitis set.

The rest of the status bits indicate the state of the different conditions
that could cause an interrupt if enabled. The PUSART latches all
these bits after a change occurs, whether the interrupt is enabled or
not. This allows the detection of transient changes on the assocxated

External/status
flags:

lines with less timing restnctmns on the software.

When the PUSART is eperated in interrupt-driven mode for
external/status interrupts, and an interrupt occurs, status register O
should be read, and a Reset External/Status Interrupts (RE/SI)
‘commandsheuld be issued to reenable both the interrupt and the
latches. When the PUSART is operated in non-interrupt mode,
these bits may be polled by firstissuing a RE/SI commandin order to
update the status and cause it to mchcate current values.
CCITT 109*

(Carrier
Detect)

Sync

" This bit echoes the inverse state of the CCITT 109 input. When

CCITT 109is low, the CCITT 1009 status bitis high. Any transition

on this bit causes an external/status interrupt request.

The meaning of this bit depends on the eperatmg mode of the
PUSART.

Asynchronous mode: sync status echoes the inverse state of the
SYNC input. When SYNCis low, sync status is high. Any transition
on this bit causes an external/status interrupt request.

Monosync, Bisync, HDLC modes: In these modes, sync status

indicates whether the PUSART receiver is inthe sync hunt phase or

receive data phase of operation. This bit will become set as aresult of
setting the Enter Hunt Phase ( EHP) bitor as aresult of a reset. It will
be clear when the PUSARTis in the receive data phase of operation.
Asin other modes, a transition on this bit causes an external/status
interrupt request. Thxs may be cleared immediately by issuing a

RE/SI command.
D5

(Clear to
Send)

This bit echoes the inverse state of the CCITT 106 input. When
CCITT 106is low, the CCITT 106 status bitis high. Any transition
~on this bit causes an external/ status interrupt request.

IDLE/CRC

This bit indicates the state of the IDLE/CRC latch used in

CCITT 106*

synchronous and HDLC modes. After reset this bitis 1, indicating

“that when the transmitter is completely empty, ihe PUSART will
‘enter idle phase and automatically transmit sync or flag characters.
* Refer to Table 4-14 for equivalent EIA signals.

4-27

Table 4-7

Name

Status Register 0 Description (Cont)

Description

A zero indicates that the latch has been cleared by the Reset
IDLE/CRC Latch (RI/CL) command. When the transmitter is

completely empty, the PUSART will send the 16-bit CRC character
and will set the latch again. An external/status interrupt is issued
when the latch is set, indicating that CRC is being sent. No interrupt
is issued when the latch is cleared.

Break/abort

~
~

In asynchronous mode, this bit indicates the detection of a break

sequence (a null character plus framing error, that occurs when the

RxD input is held low (spacing) for more than one character-time).
The Break/Abort (B/A) bit is cleared when RxD returns to high
(marking).

In HDLC mode, the B/A bit indicates the detection of an abort
sequence when seven or more 1s are received in sequence. It is

cleared when a 0 is received.

Any transition of the B/A bit causes an external/status interrupt.
4.3.1.7.2 Status Register 1 - The layout of this register is}shcwn in Figure 4-25 and
thé register itself'is
described in Table 4-8.
,

I EOF l CFE l OE ! PE l
Figure 4-25

Table 4-8

RESERVED

l AS l

Status Register 1 Layout

Status Register 1 Description

Bit

Name

Description

All sent

- In asynchronous mode, this bit is set when the transmitter is empty,

and cleared when a character is present in the transmitter buffer
or
shift register. This feature simplifies the modem-control software
routines. In synchronous and HDLC modes this bit is always set to 1.

Special receive
condition flags:
|

The rest of the status bits described below — Parity Error (PE),
Overrun Error (OE), CRC/Framing Error (CFE), and End of
Frame (EOF) - all represent special receive conditions.
When any of these conditions occur and interrupts are enabled, the
PUSART issues an interrupt request. If the Status Affects Vector
(SAV) mode has been enabled, the vector generated (and the

contents of SR2(B) for non-vectored interrupts) will be different
from that of an RCA condition. Therefore
it is not necessary to
analyze SR1 with each character to determine that an error has

occurred.

4-28

Bit

Table 4-8

Name

Status Register 1 Description (Cent)

Description
As an additional facility, the PE and OE flags are latched; that is,

once one of these errors occurs, the flag stays set for all subsequent
characters until cleared by the ER command. With this facility, it is
only necessary to read SR1 at the end of a block or frame to
determine if either of these errors occurred anywhere in the block.
‘The other flags are not latched and follow each character as it occurs
“in the receiver buffer.

Parity
o

This
bit is set and latched when parity is enabled (that is, if parity is

error

Overrun
error

enabled as a special receive condition) and the received parity bit

does not match the sense (odd or even) computed from the data bits.

‘This error occurs and is latched when the receiver buffer already
contains three characters and a fourth character is completely
received, overwriting the last character in the buffer.

CRC/framing

error

In asynchronous mode, a framing error is flagged (but not latched)

when no stop bit is detected at the end of a character (that is, RxD is

low one bit-time after the center of the last data or parity bit). When

this condition occurs, the PUSART waits an additional half bit-time
before sampling again, so that the framing error is not interpreted as a

new start bit.

In synchronous and HDLC modes, this bit indicates the result of the

comparison between the computed CRC value and the new characters
being received. It is more usually set to 1 because a correct match is

seldom achieved until the complete block or frame has been received
and the actual CRC is in the buffer. Note that a CRC error does not

result in a special receive condition interrupt.

End of

frame

4.3.1.8

This bit is used only in HDLC mode to indicate that the End of

Frame (EOF) flag has been received and that the CRC error flag and
residue code is valid. This flag may be cleared at any time by issuing
an ER command. The PUSART also automatically clears this bit on
the first character of the next message frame.

Channel B Status Registers — These read-only registers start at address 110 104. They are

identical to the channel A status registers except for minor differences. As with control register 1, s atus
register 0 may have a dual function. In the KMV11-A single channel option, status register 0(B) adds
extra functions. Although these extra functions apply to the single channel (A) the register itself is
accessed via the channel B address.
P
TN
P
)

In the KMV11-B dual-line option, status register O(B) has the same layout and ftmctions as statu$ .:egister

O for channel A.

Status register 2 of channel B operates like control registejr 2(B). The contents éf status register 2( B) apply

to channel A in the KMV11-A single channel, or to both channels in the KMV11-B dual channel option.

4-29

4.3.1.8.1
Status Register 0 KMV11-A - For the KMV11-A (single channel), this register is used to
add extra functions. These functions monitor the CCITT 125 (Ring) line and the CCITT 107 (Data Set
Ready) line. Figure 4-26 shows the layout of this register.
»

D6 . D5

. D4 . D3

. D2 . DI _

FcorT | NOoT |-comr |

125* | USED | 107*

F 1

RD 946

Figure 4-26 Status Register 0 (B) Layout in KMV11-A

4.3.1.8.2 Status Register0 KMV11-B (dual line) - For the KMV11-B (dual line),
this register has the

same layout and functions as status register O for channel A, except for the IP bit (D1), which is only
available in channel A, but valid for both channels.

4.3.1.8.3

Status Register 1 - Status register 1 is only useful for KMV11-B. Its layeut is identical to the

status register 1 channel A.

4.3.1.8.4

Status Register 2 — Status register 2, available at this address, is shared by channel A and

channel B. Figure 4-27 shows the layout of this register; |

ok
e

)

INTERRUPT VECTOR

* BITS AFFECTED WHEN CR2(A) D4 PROGRAMMED TO O.
** BITS AFFECTED WHEN CR2(A)
D4 PROGRAMMED TO 1.
ik

Figure 4-27

Status Register 2(B)

Layout

Reading status register 2(B) returns the interrupt vector that was programmed into control register 2(B). If

SAV mode is enabled, the value of the vector is modified as follows:
D4 D3 D2
B
or
Condition

p2Dipo

<111>

<000>
<001>
- <010>
<011>
<100>
- <101>
<110>
<111>

No interrupt pending

Channel B transmitter buffer empty
Channel B external/status change
Channel B received character available
Channel B special receive condition

Channel A transmitter buffer empty
Channel
A external/status change
Channel A received character available
Channel A special receive condition

4-30

As can be seen, code 111 can mean either channel A special receive condition or no interrupt pending. It is

simple to separate the two by examining the IP bit (D1) of status register 0, channel A. Note that in nonvectored interrupt mode, in order for the interrupt pending to be valid, the vector register should be read
first.

4.3.2 Line Controller Interrupt System and Mode Selectien

The four DMA request lines (RXA DMA REQUEST, RXB DMA REQUEST, TXA DMA
REQUEST, and TXB DMA REQUEST) and the PUSART interrupt request line are used to generate
five different interrupt vectors according to the fellewmg
Condition

Vector

Priority Level

140
150
100
110
120

o
7
6
6
5

Receive A
Receive B
Transmit A
Transmit B
Special condition,
external/status

You are therefore recommended to initialize{ the PU SART with the following parameters:
Control register 1

2.
3.

External/status interrupt enable

Pt e

Transmitter interrupt (DMA) enable
Status affects vector enable (channel B CRI)

Receiver interrupt on first character and DMA on first and following characters

This initialization has to be done for both channels when using the KMV11-B.
For the KMV11-A the external/status mterrupt enable (chaxmei B) may be set if mi terrupts on
changes of state of CCITT 125* or CCITT 107* are wanted.

—

Recommended initialization parameters fer control register 1 (values in ectal):
KMV11-A (single line)

KMV11-B (dual line)

CHA control reg 1:17

CHA control reg 1: 17

CHB control reg 1:

CHB control reg 1: 17

Control register 2

This control register (channel A) defines the mode of operation of the PUSART for both
channels, therefore parameters are the same for the KMV1 I*A and the KMVII -B.

* Refer to Table 4-14 for EIA equivalent signals.

4-31

Recommended initialization parameters (in octal) for control

1. Both channels DMA
2.

Priority: RxA > RxB > TxA > TxB > special conditi

Vector bits 0, 1, and 2 are affected on special condition interru
pt or external/status
~interrupt.
|
|
*
NOTE

After power up, INIT, or channel reset, DMA
interrupt requests are waiting until this register
has been set up.
e

Control register 2 (channel B)

This should be loaded with 0, so that the variable vector
bits would provide an offset pointer to
the appropriate special condition interrupt routine or
external/status interrupt routine.

NOTE

As bits 0, 1, and 2 are affected, the vector would
have to be shifted one bit to the left, before being
used as a word address. e
A
The rest of the control registers would be programmed

parameters wanted for each channel.

with the protocol, receiver, and transmitter

The layaut;)f these reg’isters may be found in Section 4.3.1.
4.3.3
HDLC Operation Example
The values of bytes are given in octal notation in this

Mode cenfigura\\tifion;: -

sectien;

Issue a Channel Réset kCR)cem%mand [CRO(A): 30]

Set mode [CR2(A): 26]’

Load dummy vector [CR2(B): 0]

HDLC mode [CR4(A): 40]

5. Load HDLC flag [CR(A): 176]
6.

Load HDLC address [CR6(A): xxx|

Turn on the transmitter, receiver, and modem monito

Issue a Reset External/Status Interrupts (RE/SI) comma

Set interrupt/DMA enables [CR1(A): 17]

nd [CRO(A): 20]

4-32

(¥

Set CCITT 125*, CCITT 107%, interrupt enables [CR1(B): 5]
Enable transmitter [CRS(A) 151]

(the PUSART proceeds to transmit flags)

Enable receiver [CR3(A): 331] or enable receiver/address recognition [CR3(A): 335]

Issue a Reset External/Status Ifiterrfipté (RE/SI) command [CRO(A): 20]

Issue an Enable Ifitérrupt én Next Character (EINC) cemmd [CRG(A’V); 40] |
Expect interrupts on modem signal changes or start of frame reception.
Frame transmissions:

Issue a Reset Transmitter CRC Checker (RTCC) command [CRO(A): 200]

Load the first character into the transmitter buffer

Issue a Reset IDLE/CRC Latch (RI/CL) command [CRO(A) 300]

On interrupts to TX vector (100) load next cha:acters |
Repeat above until end of block or frame

Transmit loop:

Ignore interrupt to TX vector, when all transmitted

Wait for interrupt to PUSART vector (120), indicating that CRCis being transmztted

Wait for interrupt to TX vector, mdlcating CRCis transmitted

If next block or frame is ready to be transmitted, go to ‘Transmit loop’, else:
a.

Issue a Reset External/Status Interrupts (RE/SI) command [CRO(A): 20]

Issue a Reset Pending Transmitter Buffer Interrupt or DMA Request (RPTBIDR)
command [CRO(A): 50]

(The PUSART prcceeds to transmit flags.)

* Refer to Table 4-14 for EIA equivalent signals.

4-33

Underrun error:

This error will be detected, at the same time as the IDLE/CRC bit (bit D6)

CRC transmission is started due to an empty transmitter.

of status register 0, when

Issue a SendAbort (SA) command [CRO(A): 10]

Issue a Reset Extemal/ Status Interrupts (RE/SI) command [CRO(A)

|
: 20]

3. Issue a Reset Pending Transmitter Buffer Interrupt or DMA Request (RPTBIDR) command
(The PUSART proceeds to transmit flags.)
Frame reception:

1.
2.

Anexternal/status interrupt to PUSART vector (120) will occur, indicating that a flag has been

received

Issue a Reset External/Status Interrupts (RE/SI) command

The first character received will cause an interrupt to the RXA (140) and

vector (120)

to the PUSART

Read character; ignore PUSART receive interrupt.

Receive loop:

On interrupt to the RXA (140) vector

If status register 1 indicatesno EOF
~

Then read character and indicate end of interrupt
[CRO(A): 70]
Else
While status register 0 indicates data available
- Read character, release latch

- Endwhile

(Modem line changes and abort detection are indicated by external/status

4.4

interrupts.)

LINE CLOCK - REAL-TIME CLOCK INTERFACE

Two line clocks and one real-time clock are implemented within an

8254 timer/counter IC.

This IC provides three programmable down-counters.
4.4.1
Line Clock — Real-Time Clock Register Description
Address 120 000 is a 1-byte read-only register contained within the 8254 clock IC. This
register may be
used to read back the clock divider ratio for the channel A line clock generator.

Address 120 002 is a 1-byte write-only register contained within the 8254 clock IC. This registeris
usedto
load the clock divider ratio for the channel A line clock generator.

4-34

Addresses 120 004 and 120 006 are identicalin functional description to 120 000 and 120 002, except

that they apply to the channel B line clock generator.

NOTE
Channel B will not be unplemented in the
KMVI11-A.

Addresses 120010 and 120012 are 1dentica1 to 120 000 and 120 002, except that they apply to the realtime clock generator.

Address 120016

is a 1-byte write-only reglster within the 8254 clock IC andis used to define the mode ef

the clock counter IC.

4.4.2 Line Clock Programming
|
Two counters provide local transmit/receive clocks for null modem connections or test purposes. A and B
line clocks are identical, but the B line clockis only useful with the KMV 11-B.

In order togenerate a square wave thh an even mark space ratw, as needed by the transmxtter/receiver,

the initialization parameter for the two counters should be specified as mode 3 (square wave). The use of
even divider valuesis recsmmended

By using the follewing fermula, the synchronous bit rates may be computed.
Bit rate (kbits/s) = 6912/divider ratio
Standard bit rates:
Divider

Bit Rate

Actual Bit Rate

108
124
144
360

64
56
48
19.2

64
55.74%
48
19.2

1440
2880
5760

4.8
2.4
1.2

(decimal)

(kbits/s)

4.8
2.4
1.2

* Error = 0.5%

4-35

| B

1 to 32 76819in bmary mode or frem 1 to 100001@in BCD mode.

TRN

Both counters are fed with a 6912 kHz clock. The dxvzder ratio for both cgunters may be pregammed from

Far asynchronous bit rates, the PUSART IC needs at least a 16-times clock, and the appropriate formula

is:

Bit rate (kbits/s) = 432/divider ratio

Asynchronous

22
45
90

360
720
1440
*

Bit Rates
(kbits/s)

~ (16-Times Clock Mode)
(kbits/s)

19.2
9.6
4.8

19.63%
0.6%*
4.8

1.2
0.6
0.3

Error=225%

** Acceptable clock distortion of less than 1%
For maintenance or special applications the output of the A LINE CLOCK may be applied to the
TRANSMIT CLOCK A, RECEIVE CLOCK A; and the output of the B LINE CLOCK to the
appropriate channel B clock inputs of the PUSART IC. This is done by asserting the SCM bit (bit 5) in
Port
C of the 8255 IC (address 130 006).
N
'
The line clocks are always available on the CCITT 113 modem circuit, (channel A and channel

KMV11-B), regardless of the maintenance mode referred to above.

B for

NOTE

When PTT requirements specify that the CCITT
113 circuit is to be held
in a steady OFF state,
then no divider ratio should be programmed into
the clock IC for the relative counter(s).
4.4.3 Real-Time Clock Programming
The third counter within the 8254 IC is available as a real-time clock.

Its output will generate an interrupt to vector 130 on priority level 5.
Two modes of operation are available:
e
e

One-shot mode (mode 0)
Clock mode (mode 2)

In one-shot mode the counter will interrupt after the timeout and then stop. In clock mode the counter will
interrupt once for every time interval.
|

Time intervals for both modes may be computed according to the following formula:
Time = 18.5 microseconds X (N + 1)

where N is programmable from 1 to 32,768 10 in binary mode, and from 1 to 10,00010 in BCD mode.

4-36

In addition to processor priority level masking, RTC bit O of the 8255 Port C
(address 130 006)
disables/enables the real-time clock interrupt.
:
.
I
2
In addition, this bit must be cleared after an RTC interrupt has taken place, to acknewled
ge the interrupt. It
may then be set again to enable the next clock interrupt.

4.4.4 Line Clock — Real-Time Clock Parameter Setting
|
=
|
Before any of the three counters are to be used, the appropriate control byte has to be written into
the 8254
IC. The control byte write address is 120 016.
<
|
The byte layout is shown in Figure 4-28.

lD7 De |Ds o4lo3]ozlo,lnol
0

OO
= =00
o)
o)
1

O
1
O

BINARY (16 BITS)

BCD (4 DECADES)

MODE O (REAL TIME, ONE SHOT)
MODE 1 NOT SUPPORTED

MODE 2 (REAL TIME, CLOCK MODE)

'MODE 3 (LINE CLOCK, SQUARE WAVE)
MODE 4 NOT SUPPORTED
MODE
5 NOT SUPPORTED

COUNTER LATCH NOT SUPPORTED
LEAST SIGNIFICANT BYTE ONLY
MOST SIGNIFICANT BYTE ONLY
LEAST SIGNIFICANT BYTE FIRST,
~

THEN MOST SIGNIFICANT BYTE

SELECT COUNTERO

SELECT COUNTER 1

SELECT COUNTER 2

READBACK COMMAND NOT SUPPORTED

RD 942

Figure 4-28

Clock Control Register Bit Functions

Typical parameter load sequences:
1]

¥LSE,@¥$#120002

MOVE

#MSER@#120002

Control ward far A-line clock
Load LSE
Load MSE

for A-counter
forA-counter

#136,04120016

Control

#LSE,@2120006

Load

Control word for RTC

#LSE,@#120017
#MSEsC#120010

MOVE $#274,04120016
MOVE
MOVE

MOVE

#076,@%120016

MOVE

b RVTN

Load
lLoad

LSE

LSE
MSR

4-37

word
for

for
for

for

E-line

B-counter

RTC
RTC

clock

mmary

of 8254 addres
ses:

120 016 :
120 000 :
“120°002" :

IC mode line register, write only
Line clock A counter read *
Line clock A counter write =~

120 004
120 006
120 010
120 012

Line clock B counter read *
Line clock B counter write

:
:

RTC counter read *
RTC counter write

* Read operation is possible, but not supported.

4.5

PERIPHERAL PORT INTERFACE

4.5.1
Peripheral Port Reg:ster Description
|
Address 130 000, port A, is a 1-byte read—-only register contained within the 8255 peripheral IC. Reading
this register will provide different informationin the KMV11-A andin the KMV11-B. The layout of this
register in the KMV11-Ais shownin Figure 4-29 and thatin the KMV11-Bis shownin Figure 4-30.
Table 4-9 describes the bit functions for thls reglster in the KMV 11-A and Table 4-10 describes the bit
functionsin the KMV11-B:
|

. D6

. D5 .

! TTMO l S et l DIP2 l

D2. DI

l DIP1 I A/B I
|

Figure 4-29

l
RD 948

KMV 11-A Port A Register Layout

Table 4-9 KMV!I*A Pert ARegiSier Bit Description
Bit

Name

A/B

If set, the interface is a KMV11-A, if clear it is a KMV11-B.

DIP1

Status of DIP switch E13 SW 8 (on = 1).

DIP2

CCITT 112
B
o

- Description

Status of CCITT modem circuit 112 (Data ngnal Rate Selector

CCITT 142
TTMMO

|
|

Status of DIP switch E29 SW 10 (on = 1).
DCE), CCITT 112 on = 0.

Statusoef CCITTmadem circuit 142 (Test Indicator), CCITT 142
~

on=0.

Latched timeout. This bit will be set when a timeout has occurred

- during a DMA IN or DMA OUT transaction. Itis cleared by a
following DMA IN or DMA OUT.

4-38

l TTMO l

lmm}l DIP2 1107(8) l DIP1 l A/B l LB l
Figure 4-30

Table 4- IO

Bit

. D4

Name

KMV11-B Port A Regster Layout

KMVII B Port A Reglster Bit Descmptmn

Description

A/B

DIPL

Status of DIP switch E24 SW 8 (on= 1).

D 4

DIP2

Status ofDIP switch E36 SW 10 (on = 1).

CCITT 107B

Status of CCITT modem carcmt 107 (Data Set Ready) for channel
B, CCITT 107Bon
= 1.

;
;

CCITT 107A

Status of CCITT modem circuit 107 (Data Set Ready) for channel

*‘

o ,bapback, cennectervis in place if this bit is O.
If set, the mterfaceis a KMVI 1-A, if clear it is a KMV1 I*B

TMO

A, CCITT 107A on
= 1.

Latched timeout. This bit will be set when a timeout has occurred

- during a DMA IN or DMA OUT transaction. It is cleared by a
following DMA IN or DMA OUT.

Address 130 006, Port C, is a 1-byte wnte~e3nly register centazned within the 8255 peripheral IC. Flgure
4-31 shows the bit layout for this register and Table 4-11 describes the bit functions.

. D7

. D5

. D4

D3 . D2

. DO

!ECZIECO lSCMlSLMlREDlYEL IGRN'RTC,
RD 960

Figure 4-31

Bit

Name

Table 4-11

Port C Reg:ster Layeut

Port C Register Bit Description

Description

RTC

GRN

Green LED on if this bit is set.

YEL

Yellow LED on if this bit is set.

RED

Red LED on if this bit is set.

Enable the real-time clock if this bit is set.

4-39

Bit

Table 4-11

Name

Port C Reglster Bit Description (Cent)

Descnptmn

SLM

Select Loop Mode - 1 = mtemal loep made Serial transmit and
receive are leeped internally to the PCB. The CCITT 103 (Transmit

Data) leadis in the 1 (marking) state. For the KMV11-B, this mode
is selected far beth channels at the same time.
ps

SCM

Select Cleck Mede -1= mtemal cleck mode. In internal clock

mode, the DTE Transmit Signal Element Timing signals are
a f"‘previdecl by the channel A clock generator. This bit, together with bit
D4, is used for maintenance purposes. For the KMV11-B, this bit
selects eflly ehannel A

ECO

Enable CSR 0 interrupt. When this bitis set, any write access from

the host to BSELO (address 100 000) will generate an interrupt at

priority level 4, via vector 60. In order to acknowledge the interrupt,
- the ECO interrupt must be cleared and set again to reset the interrupt| sensmg legzc

EC2

Enable CSR 2 interrupt. This bitis identical to bit D6 except that it

applies to BSEL2 (address 100 002) and interrupt vector 70.

Address 130012, port ‘B is a 1-byte write-only reglster contained within the 8255 peripheral IC. Writing

into this regxsterwfllprogram different functionsin the KMV11-A and the KMV11-B. The bit layout for
this registerin the KMV11-Ais shownin Figure 4-32 and that for the KMV11-Bis shownin Figure 4-33.
Table 4-12 describes the bit fimctxens for tlns fegzster intheKMVl 1-A, and Table 4-13 describes the bit
functionsin theKMV11-B.

cciTT | cerT | cenT

108

141 | 140

111
- RD 955

Fxgure 4—32 KMVl l-A Pert B Register Layeut
Table 4~12

Bit

KMVI 1-A Pert B Regzster Bit Descrxptzen

Name

) Desenptlen

CCITT 111

,CCITT medem control lme lll (Data Sl@alRate SeleeterDTE),

CCITT140

CCITT modem control line 140 (Loopback and Maintenance Test),

CCITT 141

CCITT medern eentrel lme l4l (Local Leepbeck), 1=CCITT 141

1=CCITT
111 on.

1 = CCIT’I' 140 on.

4-40

Table 4-12

KMV11-A Port B Register Bit Description (Cont) |

Bit

Name

Description

IOP

When this bitis set, the DMA Iegm: will access the address indicated
in the DMA registers on the I/O page. This function will allow the

KMV11 to communicate with other devices on the Q-bus.

TIS

Terminal In Service
— This bitis used by the dlagnostlc firmware to
detect the presence of the loopback connector. Thisis called circuit
ISin EIA specification RS»422aA and RS-423-A (RS-449).

QDE

This bit must be set to enable the DMA register to start a DMA cycle
when the extended address bzts are wntten

CCITT 108

CCITT modem ccfntrcal line 108/2 (Data Termmal Ready),
1 = CCITT 108/2 on.
o

. D6

D4 . D3 . D2

[Tosi| Soais| ¢ [somim]| 107 l N
CCITT | cciTT

RD 950

Figure 4-33
Table 4-13

Bit

Name

I0P

KMV11-B Port B Register Layout

KMVI11-B Port B Reg:ster Bit Descnptmn

Descrlptlen

" When this bit is set the DMA legic will access the address indicated
in the DMA registers on the I/O page. This function will allow the
KMV11 to communicate with other devices on the Q-bus.

SCM-B

Select Clock Mode channel B. 1 = internal clock mode. In internal

clock mode, the DTE Transmit Signal Element Timing signals are
provided by the channel B clock generator. This bit, together with bit
D4 in port C is used for maintenance purposes.
D5

QDE
-

This bit must be set to enable the DMA register to start a DMA cycle
when the extended address bits are written.

CCITT 108B

CCITT modem control line 108/2 for lme B (Data Termmal
‘Ready), 1 = CCITT 108/2B on.

CCITT 108A

CCITT modem control line 108/2 for line A (Data Terminal
Ready), 1 = CCITT 108/2A on.

Address 130 016 is a 1-byte write-only register contained within the 8255 peripheral IC. Itis loaded by
the root firmware at start-up time with the correct mode for the 8255 IC (220g).

4-41

This control register may also be used to perform bit setting and clearing of the port C register. Loading
octal parameters will give the following results:
Parameter

Action

‘

RTC disable
RTC enable
Green LED off
Green LED on
Yellow LED off
Yellow LED on
Red LED off

ok s, ol e

ek, s

it ok

Red LED on
Internal loopback disable
Internal loopback enable
Clock source external
Clock source internal
CSR 0 interrupt disable
CSR 0 interrupt enable
‘CSR 2 interrupt disable
CSR 2 interrupt enable

4.5.2 Modem Monitoring and Control
Modem lines may be monitored or controlledin part threugh the PUSART line controller IC, andin part
through the 8255 penpheral IC.
Modem line assignments for the smgle—hne KMYV11-A are different to those of the dual-line KMV11-B.
KMV11-A:
|
’

‘The selection of balanced/unbalanced operation is done via DIP switches on the
modale Please refer te the technical manual for location and setting.

KMVI11-B:

The selection of balaficed/unbalanced operation is done via modem cable assembly.

Meéem Imes memtered through the PUSART IC

KMVI 1-A: CCITT 106 CCITT 109, CCI’IT 10‘7 CCITT 125
KMV11-B: CCITT 106A CCITT 109A CCITT 1065 CCITT 109B.
A change of state on these sxgnals may set up an mterrupt to PUSART vector 120 if the PUSART IC has

been correctly set up.

See Section 4.3.1 for PUSART prcgfamming of appropriate modem lines.

4-42

Table 4-14 List of SupportedMédem Signals
CCITT

RS449

RS232

DIN 66020

DEC STD 52

101

(none)

PRT GND

102

-~ SIG GND

103
104

SD
RD

BA
BB

‘DI
D2

"TxD
RxD

D
D

105

RTS

107

108/2

S1.2

DTR

109

111

DSRS

112

(none)

- SPDMI

113
114

TT
ST

DA
DB

Tl
T2

TxClock(DTE)
TxClock(DCE)

115

RxClock(DCE)

D
D
D

140

(none)

PS2.

Rem LPBK

141

(none)

PS3

Local LPREQ

142

(none)

PMI1

Test Indicator

125
(none)

IC
IS

CE
(none)

M3
(none)

DSR

IAD
D

RI
~ (none)

= Signal Ground

REMARK

'COMMENTS

A
.

= Send Data
= Receive Data
= Request to Send

T
T
|
&
A
= Available on KMV11-A only
—

= Clear to Send

= Data Mode
= Terminal Ready
= Receiver Ready
=

Signaling Rate selector

=
=
=
=

Signaling Indicator
Terminal Timing
Send Timing
Receive Timing

=
=
=
=

Remote Loopback
Local Loopback
Test Mode
Incoming Call
In Service (terminal)

IA.

4-43

Transmitted class 1 circuit

available as either RS-422
or RS-423 signal
AR
A
= Interrupts from both

KMYV11-B channels
R
= Causes interrupts (KMV11-A
only)
|
= There is no approved CCITT
~_equivalent circuit (it may
‘become CCITT 135)

KMV11-A:

PUSART status register 0, channel A

Bit 3 = inverse of CCITT 109
Bit5 = inverse of CCITT 106

PUSART status register 0, channel B
Bit 3 = inverse of CCITT 107
Bit 5 = inverse of CCITT 125
KMV11-B:

PUSART status register 0, channel A

Bit 3 = inverse of CCITT 109 channel A

Bit 5 = inverse of CCITT 106 channel A
PUSART status register 0, channel B

Bit 3 = inverse of CCITT 109 channel B

Bit 5 = inverse of CCITT 106 channel B

When the PUSART is pragrsnimed for external/

status interrupt,
any change in state will cause an
interrup
andt all the above bits will be latched.
They will be unlatched via the RE/SI command.

Modem lines controlled through the PUSART integrated circuit:

CCITT 105 and CCITT 105 channel B (KMV11-B),
The Request to Send lines are centrelled ihreugh PUSART control register, channel A, bit 1 and
PUSART control register, channel B, bit 1 for the two channels.

;

With the KMV11-B, before using this bit in channel B, control register 2, channel A must have been
|

correctly set np(bxt‘? = 0) ER T

Modem circuits monitored through the 8255 peripheral integrated circuit:
The Port A aédress 130 000 is used to monitor the following modem circuits in their true (non-

inverse) state:

" PortA
BIT 3

"BITS

BIT6

KMVII-A

KMV11-B

CCITT 112

CCITT 107A

CCITT 107B

CCITT 142

These signals will have to be scanned to detect a state change.

4-44

Modem circuits controlled through the 8255 peripheral IC:
The Port B address 130 013 is used to control the following modem circuits in their true (noninverse) state.

Port B

KMVII1-A

BITO

CCITT 111

BIT 1
BIT 2
BIT 6
BIT 7

KMV11-B
_

CCITT140
CCITT 141

CCITT 108/2

CCITT 108/2B
CCITT 108/2A

Maintenance loop back:
External loop:
When loopback connections are fitted
to the KMV 11 module or to the modem cables( s) for test
purposes, the following connections are made.

KMVand
11KMV11-B:
A
103

(TxD)

113

(ATxCLK)
to
and
to
(RTS)
to

105

108/2

and

(DTR)

KMV11-A only:

104
114
115
106

109

107

(RxD)
(TxCLK)
(RxCLK)
(CTS)

(CD)

(DSR)

111

(DSRS)

141

(LL)
(19)

~ to
to

(TxD)

“

112

142
125

(SPDMI)

(Test Indicator)
(R

KMV11-B only:

103
113

105

108/2

(ATxCLK)

and

(RTS)

and
(DTR)

4-45

104

114

106

to
to

109
107

115

(RxD)

(TxCLK)

(RxCLK)

(CTS)

(CD)
(DSR)

Internal loop:
-~

KMV11-A AND KMV11-B:
Address 130 006, bit 4

(SLM) when set, creates an internal loop.

Transmitter output ( TTL) connected to rec:eiver input.
The TxD output will be in the marking state. The RxD input is ignored. Modem lines are
not affected.
|
For the KMV11-B, SLM creates a loop for both channels at the same time.

4.6

HOST INTERRUPT AND Q-BUS CONTROL INTERFACE

4.6.1
Host Interrupt and Q-Bus Control Register Description
Address 140 000 contains the Q-bus control register. This write-only register is implemented to allow the
Q-bus control functions described in Table 4-15. The layout of this register is shown in Figure 4-34.
D7

l vVC4 [ VCO l

RESERVED
[

RD 957

Figure 4-34
Table 4-15
Bit

Name

D35

VCO
-

Q-Bus Control Register Layout

Q-Bus Register Function Description

Description

Q-IRQO — When this bit is set, an interrupt on the Q-bus to vector

xx0 will be generated. xx is defined by the vector DIP switch

configuration. As the interrupt hardware needs a leading edge, it is

necessary to clear this bit before setting it. Only one interrupt will be
generated per O to 1 transition.
|
-

VC4

Q-IRQ4 - This bit performs an identical function to bit D5, except
that the interrupt vector will be xx4 instead of xx0.

4-46

4.6.2 Host Interrupt and Q-bus Control Programming
Interruptsin the host Q-bus system may be set up for two different vectors. The vectors are xx0 and xx4,
where xx is defined by the setting of DIP switches. Refer to the technical manual for the correct setting.

An interrupt to vector xx0 is generated by asserting VCO, bit 5 of address 140 000.
As the interrupt logic needs a leading edge transition, the appropriate bit must be clear before setting it.

4-47

SERVICE

5.1
SCOPE
This chapter contains information for semcmg the KMVI11-A. It mcludes the maintenance phllcsephy,
maintenance functions, preventive maintenance, and corrective maintenance. The section on corrective
maintenance contains a short description of the diagnostics for the KMV11-A.
5.2 MAINTENANCE PHILOSOPHY
The field replaceable unit (FRU) for the KMV11 is either a defective module or cable. The training of
Field Service personnel concentrates on the use of diagnostics to isolate the FRU. Spare parts for module
repa1r are not availablein the field. Typical apphcatmns ofthe KMV11 do not permit long troubleshooting
sessions. Component troublesheoung and repaxr needs at least a 16-channel logic analyzer

CAUTION

When inserting or removing
the KMV11 module,
be sure not to move any components mounted on
sockets (for example, PROMs or the micropmcesser)

5.3 MAINTENANCE TOOLS AND FEATURES
The following features are provided with the KMV11 to help fault 1sc:latmn and status checking:
e
e
e

LED indicators
On-board diagnostics
Line clock and loepback connectors.

5.3.1
LED Indicators
Five small red LED indicators show the status of the following modem signals (at TTL level):

CCITT 103
CCITT 104
CCITT 107
CCITT 106
CCITT 109

| Transmxt Data
Receive Data
Data Set Ready
Clear to Send
Carrier Detect

(mveueiMAK LED OFF)
(true, MARK = LED ON)
(true, ON = LED ON)
(true, ON = LED ON)
(true, ON = LED ON)

Three large colored LEDs are operated by the microcode.
The physical location of the LEDs is shown in Figure 5-1.

5-1

CCITT 109 (CD)
CCITT 107 (DSR)

GREEN

CCITT 104 (R )
'RED ——

CCT‘T 105(S)

Y
RD1055.

Figfire 5-1 ‘:LED Indicator Location
Table 5-1 shows the meamng
of the mxcmcede-@perated LED dlsplay

This table is only true for the PROM-resident
firmware. Apphcatzcn firmwaze may drive the
LEDsin other ways..
Table 5-1

Red

OFF

LED Status
Yellow
Green

LED Meaning

OFF

KMV poweron

self-testdisabled

o seif-»tést staned

,‘

State

OFF

fSelf’test execution

- for1 pass

Comment
|

- Steady state if self-test
is disabled,

OFF

Self-test successful
completion

OFF

Self-test error

OFF

ON/
OFF

Normal self-test
running in
continuous loop

5-2

10 seconds, at self-test
o

10 secdnds duration

OFF

Steady state
S

o Steédy state on first error
10-second period between
green ON/OFTF states

LED Status

Red

LED Meaning (Cont)

Table 5-1

Yellow

Green

State

OFF

ON
'

ON/
OFF

Extended self-test
running in
continuous loop

ls-second period
|
between green ON/OFF states

OFF

ON/
OFF

Logic or line
controller diagnostic
running without errors

Random periods between
green ON/OFF states

OFF/
ON

ON/
OFF

Logic or line
controller diagnostic

Random periods between
green and red ON/OFF states

running with errors

Comment

depending on number of

errors and diagnostic

The self-test will run in one of the following modes. The modes are selected by on-board dip switches:
a.

Single pass on power-up or when requested by the host software’s setting the run and MCLR
bits together

Continuous k}cp on power-up

Continuous loop on power-up with extended diagnostic routines.

Refer to Table 5-2 for the switch configuration and Figure 5-2 for the self-test switch locations.
‘Tab

le
52

Self-

Test

Switc

h
Confi

gurat

ion

E13-8

State
E29-10

OFF

Action
oot

Self-test disabled
Self-test runs for one pass at power-up or when run bit ésSérted togethér

with MCLR bit

OFF

Self-test starts to run in endless loop a{%power-up: normal mode

OFF

Self-teSt starts to run in continuous leep at pewer-up: extendéd mode

Note that the loop time for normal mode is approximately 30 seconds, while for extended mode it can be as

long as 1 hour! Correct execution of the extended self-test needs either the module loopback connector
(H3255) or the RS-422/RS-423 modem cable assembly with loopback connector (H3251).

5-3

E |
i

The major part of the PROM-resident firmware is for on-board diagnostic facilities. Routines may be used
by the host-resident diagnostic or in a chained mode by the self-test.

5.3.2 Self-Test

E19-10
D:’.

1 E13-8
RD1056

Figure 5-2

Self-Test Switch Locations

On detection of any error condition, testing will be aborted and the red LED will be ON (green and yellow
OFF). In addition the low-order byte of CSRO wfll cc)ntam 1 XX or Zxx where xx is the test numberin error
according te the test number table ( Table 5 3)
Table 5-3
Test

Self-Test List

Description (Addresses and ?attemsin@et*al)‘“

1
2
3

Stack push-pull test (RAM locations 77774, 77776)
CSR and DMA registers word access test (pattern 52525)
CSR and DMA registers word access test (pattern 125252)
CSR and DMA reglsters byte access test (pattem 252)

4
5
6
7

CSR and DMA regxsters byte access test (pattern 125)
Dynamic RAM data test (pattern 52525)
Dynamic RAM data test (pattern 125252)
Dynamlc RAM address test (pattern
= address)

DynamicRAM address test (pattern
= address mverse)

11
12
13

Real-time clock test (8254 clock/counter chip)
Baud rate generator test, channel A (8254 clock/counter chip)
Baud rate generator test, channel B (8254 clock/counter chip)

5-4

Comment

Self-Test List (Cont)

Test

Description (Addresses and Patterns in Octal)

14
15
16
17

Dynamic RAM address interaction test (pattern 177777)
PROM checksum verification test
KMV11-B modem signal loopback test, channel A
KMV11-B modem signal loopback test, channel B

20
21
22
23

RX-TX, channel
A, internal loopback, interrupt disabled
RX-TX, channel B, internal loopback, interrupt disabled
~
RX-TX, channel A, internal loopback, low-speed,interrupts enabled
RX-TX, channel B, internal loopback, low-speed, interrupts enabled

24
25
26
27

RX-TX, channel A, internal loopback, high-speed,interrupts enabled
RX-TX, channel B, internal loopback, high-speed, interrupts enabled
RX-TX, channel A, external loopback, high-speed, interrupts enabled
RX-TX, channel B, external loopback, high-speed, interrupts enabled

KMV11-A medem signal loopback test

Comment |
-

E
|

~
|

B.E
B,E

B
@~

E
B.E

AE
e

SENRREEEE A

5.3.3

S: This test is always executed at power-up
A: Runs on the KMV11-A only
B: Runs on the KMV11-B only
E: Runs only in extended self-test mode

Line Clock and Laepback Connectors

A programmable line clock is available for transmission and reception without a modem or other
external
clock source.

5.3.3.1

Line Clock — Two counters provide local transmit/receive clocks for null nwdein connections

or test purposes. The A and B line clocks are identical, but the B line clock is only useful with the

KMV11-

Both counters are fed with a 6912 kHz clock. The divider ratio or both counters may be programme
d from
1 to 32768¢ in binary mode, or from 1 to 10000,y in BCD mode.
|

For maintenance or special applications the output of the A line clock may be applied tothe TRANSMIT

CLOCK A, RECEIVE CLOCK A, and the output of the B line clock to the respective channel
B clock
inputs of the MPSC chip.
~
|
|

The line clocks are always available on the CCITT 113 modem line. ( Channel A ané channel B for

KMV11-B).

NOTE

Table 5-3

When PTT requirements specify the CCITT 113
lines to be held in a steady OFF state, no divider
ratio should be programmed into the clock chip
for the counter(s) concerned.

5-5

5.3.3.2

Real-Time Clock - A third counter within the 8254 is available as a real-time clock.

Its output ‘inillgenérate an inién'upt to vector 130 on priority level 5 (on-board DCT11 system).

Two modes of operation are available :
e
e

One-shot mode (mode 0)
Clock mode (mode 2)

In one-shot mode the counter will interrupt after a preset time interval and stop. In clock mode the counter
will give a series of interrupts separated by the preset time interval.

Time intervals for both modes may ‘be computed %accordiag to the fcllewiag formula:
Time = 18.5 microseconds X (N + 1)

where N is programmable from 1 to 32768, in binary mode, and from 1 to 10000, in BCD mode.

In addition to processor priority level masking, RTC bit 0 of the 8255 port C (address 130 006y)

disables/enables the real-time clock interrupt.

This bit’muhs’t be reSet, after an RTC iaierrupt has occurred, to acknowledge the interrupt and may then be
set again to enable the next clock interrupt.

5.3.3.3

Loopback Connectors/Tests — Three types of loopback are available for use with the KMV11-A:

Module — provided by H3255 for use on the M7500 module connector J1.

Cable — provided by:
a.
b.

’

H3251 for 37-pin RS-449 cable connectors
H325 for 25-pin RS-232 cable connectors (see note)

NOTE

The RS232 loopback (H325) connector cannot
be used for modem signal loopback tests. It does
not provide turnaround for all modem signals
used by the KMV11.
g
SRR

Medem — some types of medem have intemal loapback facilities. Thls feature is used by the

functional diagnostic VKMC on the KMV11-A only. Both local and remote modems may
provide the loopback.
|
RN

SEND COMMON

REC COMMON

TERINSER
INCOMING CALL

—>—T—%
~

—=—1—s=

TER RDY + —»—i

DATA MODE + _%—
—=—
REC DATA +

—e—1—s-

SEND DATA - —s—t—s=——

REC DATA —

** NULL CLK SEND TIMING -

—e— %

_;-gr—--—-l
——1—erp—{

)

CTS +

——t—t ]

* NEW SIGNAL ~

—>— M:';
|
——f—e——

REC RDY + --4----55;-——1

* SIGNAL QUALITY
SEL SIGNAL RATE

SIGNAL RATE IND ~

* SEC SEND DATA
* SEC REC DATA

~—»—1—-

ML
"o

SIDE T

——f—e-

TH2

—e—t—at—

H3255

* SECRTS

—=——s—1—

*SECCTS

—e—1—s-

- LOCAL LOOP ———-L-E—---TEST MODE

* SEL STAND BY
*

STAND BY gf:_g R

CTS -

REC RDY -~

—>—J—&r——

—=

;

—<—1—

DATA MODE -

—s>—f—a-

TER RDY —

—<—t—e

‘
e

‘
:

H3255 MODULE TEST CONNECTOR

\—/
* NOT REQUIRED FOR KMV11
** RS-499 SIGNAL = TERMINAL TIMING
RD1057

Figure 5-3

KMVI1l1 Loopback Connector H3255

5-7

SHIELD GROUND

?
3

SIGNAL RATE INDICATION

+
SEND DATA

——tt—s

REQ DATA +

SEND TIMING +

——e—t—a

REQ TO SEND + —s—| 4
——t——f—
REQ TIMING +
_._%_...m
--.-a..+
CLEAR TO SEND
—

DATA MODE +

—e—}—o—

RECEIVER READY +

LOCAL LOOP

TERMINAL READY +

73-—]

—

'SIGNAL RATE SEL

TEST MODE

| 20

;'%m

—e

REMOTE LOOP

. INCOMING CALL

’
o

TERMINAL TIMING + ——}—
SIGNAL GROUND
RECEIVE COMMON

SEND DATA

’ 137

SEND TIMING
REQ DATA

s——

REQ TO SEND

REQ TIMING

CLEAR TO SEND
TERMINAL IN SERVICE

DATA MODE
TERMINAL READY

—

RECEIVER READY

~ ——=—

SELECT STANDBY
SIGNAL QUALITY

——

' FE

3’:4

—]

NEW SIGNAL

3:5 ‘

TERMINAL TIMING

3:6

STANDBY INDICATION

SEND COMMON

H3251 CABLE TEST CONNECTOR
RD1058

Figure 5-4

KMYV11 Loopback Connector H3251

H325

sce

—— 28

SCR

SEC XMIT

f
-—
'

|
SEC RCV

'
CUT TO TEST

12
,

SIDE 1

NEW { SYNC
St-

XMIT DATA —>———|

RCV DATA -

—»

[O&o:e:ticoarctt]o

5|
3

—=

NEW SYNC

000

DATA SET RDY

000
0

H325

CUT TO TEST

DTR

——

NEW SYNC

22 4»

H325 CABLE TEST CONNECTOR
RD1059

Figure 5-5

KMV11 Turnaround Connector

H325

5.4 DIAGNOSTICS
As well as the on-board self-test, four diagnostic programs are provided with the KMV11-A:
VKMA
VKMB
VKMC
XKMD

logic diagnostic
line controller diagnostic
functional diagnostic
DECX-11 exerciser module

The first three programs are run under the standalone dxagnosfic supervisor. ’I’hey must be overlaid with

the diagnostic supervisor, or be previously combined with it and loaded as a single file. In both methods,
the programs will not exceed 16K of memory with the exception of the VKMC functional diagnostic.

5.4.1 VKMA Logic Diagnostic
This diagnostic does not need any cable or loopback connector. The execution time for one error-free pass
is five minutes.
Test description:
Test 1:
Test 2:
Test 3:
Test 4:
Test 5:

checks accessibility of KMV CSR addresses
clears and checks KMV CSR registers
data integrity test (CSR 2 to 16)
data integrity test (CSR 0)
CSR byte access test

Test 6:
Test 7:
Test 8:
Test 9:
Test 10:

CSR 2 data transfer test
CSR 4 data transfer test
CSR 6 data transfer test
CSR 10 data transfer test
CSR 12 data transfer test

Test 11:
Test 12:
Test 13:
Test 14:
Test 15:

CSR 14 data transfer test
CSR 16 data transfer test
combined CSR data test
dynamic RAM pattern test
dynamic RAM address test

Test 16:
Test 17:
Test 18:
Test 19:
Test 20:

dynamic RAM inverted address test
PROM revision level check
PROM read checksum verify
DMA transfer, Q-Bus to KMV11
DMA transfer, KMV11 to Q-Bus

Test 21:
Test 22:
Test 23:

DMA transfers, both directions, and memory interaction test
KMV11 to Q-Bus interrupts
Q-Bus to KMV11 interrupts

5.4.2 VKMB Line Controller Diagnostic
This diagnostic may run in either internal or external loopback mode, depending on the operator’s answer
to the startup question on the presence of an external loopback connector.

Tests 7 and 8 will not be executed in internal mode.
Test description:

Test 1:

checks accessibility of KMV CSR addresses

Test 2:

PROM revision level check

Test3:

real-time clock intérrupt test

Test 4:

baud rate generator test

Test 5:

transmit-receive various length frames in internal loop mode —no interrupts — low-speed

Test 6:

transmit-receive various length frames in internal loop mode — interrupts enabled
— lowto high-speed

5-10

5.4.3

Test 7:

transmlt-recelve vanous length framesin external leep mode mterruptsé:abled -

Test 8: |

medem Ieads external lcopback test

VKMC Functional Diagnostic =

This diagnostic loads firmware into the KMV 11 and exercises
e
the KMV 1 1 asan HDLC communication

controller. It prcwdes X.25 Layer 1 (physical layer) protecol functions, and modem control. A detailed
discussion appears in the appendix.

The purpose of this dxagnestlcis to provide troubleshootingfacilities for both DIGITAL Field Service

engineers and users’ support staff, Itis fully supperted and wfll be updated as necessary by DIGITAL’s

software distribution organization.

When used on the KMV11-A this diagnostic program may be used with all types ef Icmpback thatis
mmlule cable, and lacaland remete modem (zf the m@dems have these facflmes)

”

NOTE

The host memory must be more than léK wards
for this diagnostic
|
|
|
|
o

Test description:

Test 1:

verifies KMV11 initialization

Test 2:

runs self-test

Test 3:

application firmware load, unload, and start

Test 4:

CSR handshaking without interrupts

- Test5:

CSR handshaking with interrupts

Test 6:

QIO processing in case of resource error

Test 7:

QIO processing for various command sequences

Test 8:

transmit/receive buffer processing at 2.4 kbytes/s with modem control

Test 9:

transmit/receive buffer processing at 2.4 kbytes/s with modem control

Test 10:

transmit/receive buffer processing at 64 kbytes/s with modem control

Test 11:

transmit/receive buffer processing at 64 kbytes/s without modem control

Test 12:

transmit/receive buffer processing at 48 kbytes/s with modem control and address
search enabled

5-11

5.4.4 XKMD DECX-11 Exerciser Module

This rzzedule is provided to allow the KMV11 to be mcludedin the hest systgm s DECX-11 system
exerciser. Error-free operation shows that the KMVI 1 does not react wzth other system bus acnvfl:y ina
worst-case environment.

;

The medde exercises the KMV11 using test routine number 14 (combined DMA datain and data out
test) ch 2C k.mg transmstted data agamst received dataand memtenng the KMV11 status.

N OTE
-

No datais transmitted or received via the serial
line. Only pathways and logic between the host
and KMV11 are exercised.

5.5 PREVENTIVE MAINTENANCE
|
Thereis no specxfic KMV11 PM schedule. A general eheck ef voltages and. connections sheuld be dane
when system PMis performed. After moving KMV11 modules or cables, a complete checkout of the
devices, by running all diagnostics, is needed.
‘
Special care must be exercised because some chips are installed in sockets and may be moved during
removal or replacement of the KMV11 or adjacent modules.
|

5.6 CORRECTIVE MAINTENANCE
The FRUis either the KMV11 module or a cable. All corrective diagnostics should be apphed to 1.salat1ng
the failing FRU. KMV 11 diagnostics are designed to helpin the isolation process and should be run in the
following sequence:

1.
2.
3.
4.

VKMA
VKMB
VKMC
XKMD

logic diagnostic
line controller diagnostic
functional diagnostic
DECX-11 module included within the appropriate DECX-11 system exerciser.

Before considering a KMV 11 module to be defective, check switch settings and the wire link configuration
by referring to Chapter 2.

5-12