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Document:	KE11-E and KE11-F Instruction Set Options User's Manual
Order Number:	EK-KE11E-OP
Revision:	001
Pages:	28
Original Filename:

OCR Text

KE11-E and KE11-F
instruction set
options
user’'s manual

dlilgliltiall

EK-KE11E-OP-001

KE11-E and KE11-F
iInstruction set

options
user’'s manual

digital equipment corporation - maynard, massachusetts

N’

/r‘

1st Edition, September 1976

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

This docfiment was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:

DEC

DECtape

DECCOMM

DECUS

RSTS

DIGITAL

TYPESET-8

DECsystem-10

DECSYSTEM-20

MASSBUS

PDP

TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1
1.1

GENERAL DESCRIPTION
KE11-E EXTENDED INSTRUCTIONSET

.. ... .........

1.1.1

Purpose

1.1.2

Configuration

. . . ... ... ... ... .. ... ......

Specifications

. . ... ... ... ... ... e

1.1.3
1.2

. . . . . . ..

KE11-F FLOATING INSTRUCTIONSET

ooooooooooo

1-1

e e e e e

... ... .........

1.2.1

Purpose

1.2.2

Configuration

. . ......... P
. . . . .. ... . ... . ... . .. ...,

1.2.3

Specifications

. . . . . ...

CHAPTER 2

INSTALLATION

2.1

KE11-E PROCEDURE

. ....... e, ..

2-1

2.2

KE11-F PROCEDURE

. ......... e,

2-1

CHAPTER 3

PROGRAMMING

3.1

KE11-E EXTENDED INSTRUCTIONSET

3.1.1

Operation

3.1.2

Formats

3.1.3

Instructions

3.2

. ... .. ........

3-1

. . . . . .. . .. . .. . ... ...

3-1

. ... .. ...... e

e e e e

3-1

. . . . . . . . ...

e e e e e e e e e

3-2

KE11-F FLOATING INSTRUCTIONSET

3.2.1

Operation

3.2.2

Formats

. ............ e

.. ......
.. .....

3-5

e e e e e e e e e e

3-5

. . . . . . . . . . .. ..

3.2.3

3-5

3-6

3.24
APPENDIX A

GLOSSARY OF TERMS

ILLUSTRATIONS

Figure No.

Title

3-1

EIS Number Formats

3-2

EIS Instruction Format

3-3

ASH Operation

ASHC Operation

3-5

FIS Number Format

. . ...
. .. e

Page

e e e e e e e e e e e e

3-2

. . . . . . . .. . .. ... ... ......

3-3

. . . ... ... .......... e
. . . . . . . ... ... .. .

e e e e e e

3-5

. . . . .. . .. . . . ... . ... ... ....

3-6

TABLES

Table No.

Title

1-1

KE11-E (EIS) Specifications

. . .. ... ... ... .........

1-2

KE11-F (FIS) Specifications

. . . . . .. ... ... .........

INTRODUCTION

This manual describes the KE11-E Extended Instruction Set (EIS) and KE11-F Floating Instruction Set (FIS)
Options to the KD11-A Programmed Data Processor for the PDP-11/40 System. These two options are described in
one manual because of their interdependency, in that KE11-F cannot be installed without the KE11-E being first
installed. The purpose of this manual is to:

Provide an overall understanding of the functions of these options in a PDP-11/40 System.

Explain how the KE11-E and KE11-F can be used
in software operating systems.

In this manual each chapter is split in two with the first half of the chapter presenting information concerning the
KE11-E Option and the second half being devoted to comparable information for the KE11-F Option. This

organization is intended to facilitate greater ease in use by those customers who utilize only the EIS hardware.

Chapter 1 provides an introduction to the options and lists brief specifications. Chapter 2 contains installation
information. Chapter 3 contains programming information, listing instructions and illustrating their formats.
Detailed descriptions of processor, console, Unibus, and memory logic that interface with these options are provided
in the following related documents:

PDP-11 /40 System Maintenance Manual

DEC-11-H40SA-A-D

KD11-A Central Processor Unit Maintenance Manual

EK-KD11A-MM-001

CHAPTER 1
GENERAL DESCRIPTION

This chapter contains a general description of both the KEI11-E and KE11-F Options. Mechanical descriptions are

given together with engineering specifications for each option. The chapter is divided in half with the EIS
information presented first, followed by comparable information for the FIS hardware.
1.1

KE11-E EXTENDED INSTRUCTION SET

The KE11-E Extended Instruction Set is a hardware option to the basic PDP-11/40 Computer System. It is supplied
as a pluggable option to the KD11-A Central Processor.
1.1.1

Purpose

The KE11-E Option expands the instruction set of the KD11-A Central Processor to provide extended manipulation
of fixed-point numbers. When installed, it adds the capability of Arithmetic Shift, Arithmetic Shift Combined,
N,

Multiply, and Divide. With these additional instructions, the system can multiply and divide signed 16-bit numbers,

and can shift signed 16-bit or 32-bit numbers. Condition codes are set in the processor on the result of each
instruction.

1.1.2

Configuration

The KE11-E Option consists of one module. The single-hex X 8-1/2 in. M7238 module plugs directly into slot 2
(A—F) of the processor system unit. This is a dedicated prewired slot such that no other modules need be moved to
accommodate its installation. When installed, the module functions as an extension of the basic KD11-A data paths,
N—

branch control, and control ROM. Basic timing of the processor is not degraded by use of this module, nor is the
NPR latency affected when its instructions are being executed. Interrupts are serviced at the end of each instruction
in the standard manner.

1.1.3 Specifications |
Specifications fer the KE11-E Option are given in Table 1-1.

Table 1-1

KE11-E (EIS) Specifications
Instructions

Arithmetic Shift (ASH)

Arithmetic Shift Combined (ASHC)

Multiply (MUL)
Divide (DIV)
Operations

Multiplication and division of signed 16-bit numbers
Arithmetic shifting of signed 16-bit or 32-bit numbers

1-1

Table 1-1 (Cont)
KE11-E (EIS) Specifications
Addressable Registers

None in option. Operands fetched from core or processor general registers.

Timing

Time = SRC Time + EF Time
SRC Mode

SRC Time

0.28 us

0.78 us

0.98 us

1.74 us

0.98 us

1.74 us

2.64 us

Instr

1.2

EF Time

MUL

8.88 us

DIV

11.30 us

Notes

ASH (right)

2.58 us

+0.30 us/shift

ASH (left)

2.78 us

+0.30 us/shift

ASHC (no shift)

2.78 us

ASHC (shift)

3.26 us

Size

Single Hex module (M7238)

Power Required

+5V, 2.3A

+0.30 us/shift

KEI11-F FLOATING INSTRUCTION SET

The KE11-F Floating Instruction Set is a hardware option to the basic PDP-11/40 Computer System. It is supplied
as a pluggable option to the KD11-A Central Processor and requires that the KE11-E described above be installed as
a prerequisite.

1.2.1

The

Purpose

KEI11-F

Floating Instruction

Set (FIS)

enables

direct

operations

single-precision

32-bit words in

floating-point arithmetic. Since the KE11-E is a prerequisite to the KE11-F, extended manipulation of fixed-point
numbers is available as well. The KE11-F Option further extends the PDP-11/40 instruction set to include Floating

Add, Floating Subtract, Floating Multiply, and Floating Divide. As with the KE11-E, condition codes in the
Processor Status Register are set on the result of each instruction. The prime advantage of this option is increased

speed without the necessity of writing complex floating-point software routines.
1.2.2

Configuration

The KE11-F Option consists of one single-quad X 8-1/2 in. M7239 module with the KE11-E Option described above

being a prerequisite. This FIS module plugs directly into slot 1 (A—D) also a dedicated prewired slot in the basic
KDI1-A. No degradation of processor timing or NPR latency is effected by the use of this option. Floating
instructions are aborted if a BR request is issued before the instruction is within approximately 8 us of completion,

at which time the Program Counter (PC) is adjusted to point to the aborted floating instruction so that the
instruction will be restarted upon return from the interrupt.

1-2

)

1.2.3

Specifications

Specifications for the KE11-F Option are given in Table 1-2.

Table 1-2

KE11-F (FIS) Specifications
Prerequisite

KE11-E Extended Instruction Set Option

Instructions

Floating-point Addition (FADD)
Floating-point Subtraction (FSUB)

Floating-point Multiply (FMUL)

Floating-point Divide (FDIV)
Operations

Single-precision floating-point addition, subtraction, multiplication,

and division of 24-bit numbers

Addressable Registers

None in option. Operands fetched from core.

Size

Single-quad module (M7239)

Power Required

+5V, 1.1A (typical)

Timing

Time = Basic Time + Binary Point Alignment Time + Normalization Time

Instr

Basic

Binary Point

Normalization Time

Time* us

Alignment Time

Per Shift us

FADD

18.78

0.30

0.34

FSUB

19.08

0.30

0.34

FMUL

29.00

——

0.34

FDIV

46.27

———

0.34

*Basic instruction times for FADD and FSUB assume exponents are equal or differ by one.

Per Shift us

1-3

CHAPTER 2
INSTALLATION

2.1

KEI11-E PROCEDURE

When the KE11-E is included as part of the initial PDP-11/40 System, the M7238 module is installed prior to
shipment. If it is being added to an existing system, proceed as follows:

Insert the M7238 module in 2(A—F).

Remove the jumper (W1) on processor module M7233 (IR DECODE) at location 5(A—F).

Install the three “over the back” cables from J1, J2, and J3 of the M7238 module to J 1,J2, and J3
respectively of the M7232 (U Word) module at location 3(A—D).

2.2

KE11-F PROCEDURE

When the KE11-F is to be added to a system, the KE11-E must also be added. Proceed as follows:
a.

Perform steps a. through c. above.

Insert the M7239 module in 1(A-D).

On the M7238 module, remove the following jumpers:
1.

W1 from CO2F2 to ground.

W2 from AO2B1 to ground.

W3 from DO2L1 to ground.
NOTE

If these jumpers are not removed, the KE11-E Option will still

execute EIS instructions but will not execute FIS instructions.

When the above steps are performed; the KE11-E and KE11-F Options are ready to be checked out using the

diagnostic programs supplied with the options.

2-1

CHAPTER 3
PROGRAMMING

This chapter is devoted to general programming information for the KE11-E and KE11-F Options. It provides
general descriptions of their operation, the formats and instructions for each. In addition, programming examples are
supplied for each option. This chapter is intended merely as an introduction to the programming of this hardware.
For more detailed information refer to the pertinent software documentation generated for these options. As with

Chapter 1, information has been separated for each option.

3.1

KEI11-E EXTENDED INSTRUCTION SET

There are no addressable registers in the KE11-E Option. EIS operands are fetched from either core memory or from
the general processor registers. The result of each operation is stored in the general registers.

p———

3.1.1

Operation

When the Arithmetic Shift (ASH) instruction is used, the contents of the selected register is shifted right or left the
number of places specified by a count. This shift count is a 6-bit, 2’s complement number which is the least
significant 6 bits of the source operand. If the count is positive, the number is shifted left; if it is negative, the
number is shifted right. This allows for shifts from 31 positions left to 32 positions right (+31 to -32) although a

shift of greater than 16 places loses all significance. A count of O causes no change in the number.
When the Arithmetic Shift Combined (ASHC) instruction is used, the contents of the register (R) and the register

ORed with 1 (RV1) are treated as a single 32-bit word. Register RV1 represents bits (15:00), register R represents

bits (31:16). This 32-bit word is shifted right or left the number of places specified by a count. This shift count is the
same as that described for the ASH instruction and permits shifts from +31 to -32. If the selected register (R) is an

odd number, then R and RVI1 are the same. In this case, the right shift becomes a rotate and the 16-bit word is
rotated right the number of bits specified by the count for up to 16 shifts.

When the MULtiply (MUL) instruction is used, the contents of the Destination Register and the source are
multiplied as 2’s complement integers. The result is stored in the Destination Register R and the register ORed with

1 (RV1). If the register is odd, only the low-order product is stored. This instruction multiplies full 16-bit numbers.
When the DIVide (DIV) instruction is used, a 32-bit dividend in R and RV1 is divided by a 16-bit divisor to provide
a 16-bit quotient and a 16-bit remainder. The sign of the remainder is always the same as the sign of the dividend

unless the remainder is 0. Overflow is indicated if more than 16 bits are required to express the quotient. In this
case, the instruction is aborted. If the content of the Source Register is 0, indicating divide by 0, an overflow is
indicated.
3.1.2

Formats

The number formats for the KE11-E Option are shown in Figure 3-1. A single word is 16-bits long and a double
word is 32-bits long. In the single word, bit 15 is the sign of the number; and in the double word, the sign bit is bit

15 of the high number part. The S bit is O for positive quantities and is 1 for negative quantities.

3-1

’/——SINGLE WORD SIGN

/—DOUBLE WORD SIGN BIT

[s l

HIGH OPERAND PART

15 14

]
0 15

BIT

LOW OPERAND PART
|

]
-

0
11-1602

'Figure 3-1 EIS Number Formats

3.1.3

Instructions

The EIS instruction format is shown in Figure 3-2. It is a double operand instruction in which bits (15:09) comprise
the Op code, bits (08:06) designate the Destination Register field (RRR), bits (05:03) indicate the Source Address
Mode (SSS), and bits (02:00) specify the Source Address Register (SSS). The octal coding is in the form 07XRSS.
There are four EIS instructions, as follows:

MUL

070RSS

Condition Codes:

setif product is <O0; cleared otherwise.

setif product is = 0; cleared otherwise.

R, RV1 < R X(SRC)

Operation:

MULtiply

cleared

set if the result is less than -2'5 or is greater than or equal to 2'°-1; cleared
otherwise.

Description:

The contents of the Destination Register R and source taken as 2’s complement integers
are multiplied and stored in the Destination Register R and the succeeding register RV1

(if R is even). If R is odd, only the low-order product is stored. Assembler syntax is:
MUL S, R. (Note that the actual destination is R, RV1 which reduces to just R when R is

odd.)

Example:

16-bit product (R is odd)
000241
012701, 400
070127, 10
1034xx

)

,
:
:
,

CLC
MOV #400, R1
MUL #10, R1
BCS ERROR

;Clear carry condition code

:Carry will be set if

;product is less than
~21% or greater than or
equal to 2! °
;no significance lost

Before

After

(R1)=000400

(R1)=004000

3-2

DIRR S x x|w 7 nls s s[5 s
]

JM__j,.—__J;fif____J

OP CODE

SOURCE
REGISTER FIELD

p %
SOURCE MODE FIELD
DESTINATION
REGISTER FIELD

J
11-1604

*Note that for the EIS instructions the Source Register is

considered the Destination since the answer is stored in that
register. The Destination Mode and Register Field are
considered to be the source. This is not consistent with other
PDP-11 family instruction formats but is used throughout the
discussions of the EIS instructions in this manual.
Figure 3-2

DIV

EIS Instruction Format

071RSS

DIVide

Operation:

R < R, RVI1 + (SRC) RV1 « Remainder

Condition Codes:

setif quotient <O; cleared otherwise.
setif quotient = 0; cleared otherwise.

set if source = 0 or if the absolute value of the register is larger than the absolute
value of the source. (In this case, the instruction is aborted because the quotient
would exceed 16 bits.)
setif divide by O attempted; cleared otherwise.

The 32-bit 2’s complement integer in R and RV1 is divided by the source operand (SSS).

Description:

The quotient is placed in R; the remainder is placed in RV1 with the same sign of the
dividend. R must be even.
Example:

ASH

005000

CLR RO

012701,20001

MOV #20001,R1

071027,2

DIV #2, RO

Before

After

(R0)=000000

(R0)=010000

Quotient

(R1)=020001

(R1)=000001

Remainder

072RSS

Arithmetic SHift

3-3

R « R shifted arithmetically NN places to right or left, where NN = low-order 6 bits of

Operation:

source.

Condition Codes:

Description:

set if result <0; cleared otherwise.

setif result =0; cleared otherwise.

setif sign of register changed during left shift; cleared otherwise.

loaded from last bit shifted out of register.

The contents of the register are shifted right or left the number of times specified by the
shift count. The shift count is taken as the low-order 6 bits of the source operand (SSS).
This number ranges from -32 to +31. Negative is a right shift and positive is a left shift
(Figure 3-3).
ASH RO, R3

Example:

Before

After

(R3)=000003

(R0)=001234

(R0)=012340

R[:ljl,lll,iuh.ll.l—'
RIGHT SHIFT

IF COUNT

NEGATIVE
0

3 Rt I R

LEFT SHIFT IF

v
COUNT

i
IS

POSITIVE
11-1605

Figure 3-3

ASHC

ASH Operation

073RSS

Arithmetic SHift Combined
Operation:

R, RV1 < R, RV1. The double word is shifted NN places to the right or left, where NN =
low-order six bits of source.
set if result <O0; cleared otherwise.

Condition Codes:

set if result = O; cleared otherwise.

set if sign bit changes during the left shift; cleared otherwise.
loaded with the last bit shifted out of the register.
Description:

The contents of the register and the register ORed with 1 are treated as one 32-bit word.
RV1 (bits 15:00) and R (bits 31:16) are shifted right or left the number of times
specified by the shift count. The shift count is taken as the low-order 6 bits of the source
operand. This number ranges from -32 to +31. Negative is a right shift and positive is a
left shift (Figure 3-4). When the register chosen is an odd number, the register and the
register ORed with 1 are the same. In this case, the right shift becomes a rotate. The
16-bit word is rotated right the number of bits specified by the shift count for up to 16
shifts.

]

I P

RIGHT SHIFT

e e

IF COUNT

NEGATIVE

P £

'
C | Gmocmm

16
|

]

|
fT

|
[

{

LEFT SHIFT IF

COUNT IS

POSITIVE
11-1606

Figure 34

3.2

ASHC Operation

KEI11-F FLOATING INSTRUCTION SET

There are no addressable registers in the KE11-F Option. FIS operands are fetched from core memory and the result
of each operation is stored in core memory. Operands are ordered on the stack in Polish Notation (Paragraph 4.2),
thereby reducing the number of operations necessary to achieve a result.
3.2.1

Operation

For Floating ADD, the A argument from the stack is added to the B argument from the stack with the result stored
in the A argument position on the stack.

For Floating SUBtract, the B argument from the stack is subtracted from the A argument on the stack with the
result stored in the A argument position on the stack.

The Floating MULtiply instruction multiplies the A argument on the stack by the B argument on the stack and
stores the result in the A argument position on the stack.

The Floating DIVide instruction divides the A argument on the stack by the B argument on the stack and stores the
result in the A argument position on the stack.

3.2.2

Formats

The number format for the KE11-F Option is shown in Figure 3-5. The KE11-F word is 32 bits long with bit 15 of
the high argument designating the sign of the fraction. Note that the 8-bit exponent separates the fraction from its
associated sign. In floating point, representation of binary numbers is in three parts: a sign bit, an exponent, and a
mantissa. The mantissa is a fraction expressed in sign and magnitude format with the binary point positioned to the

left of the most significant bit of the mantissa. The mantissa is assumed to be normalized. The MSB of the mantissa
is not stored in core because it is redundant. Leading Os are removed by shifting the mantissa left; however, each left
shift of the mantissa must be followed by a decrement of the exponent value to maintain the true value of the
number. The exponent value represents the power of 2 by which the mantissa is multiplied to obtain the value to be
used.

3-5

FRACTION

SIGN BIT \‘

HIGH ARGUMENT

LOW ARGUMENT

FRACTION

FRACTION (LOW PART)

(HIGH PART)

(EXCESS 2008)

EXPONENT

0
v

23-BIT FRACTION
°L__

BINARY POINT —/" I 23
H=1: Inserted by hardware before operating on
operands if exponent field # all zeros.

11-1607

Figure 3-5

FIS Number Format

The KE11-F Option stores the exponent in excess 2005 (128 o) notation. As a result, exponent values from -128 to

+127 are represented by the binary equivalent of O to 255 (octal .0—377). Mantissas are represented in sign
magnitude form.

The binary radix point is to the left. The results of the floating-point operations are always rounded away from O,
increasing the absolute value of the number.

If the exponent is equal to O, the number is assumed to be 0 regardless of the sign bit or fraction value. The
3.2.3

hardware generates a clean 0 (32-bit word of all Os) in this case.
Instructions

The FIS instruction format is shown in Figure 3-6. It is a double operand instruction in which the low three bits

(R,R,R) specify a register that is utilized as a stack pointer for the floating-point operands. The register may be any

one of the eight general registers, but some caution must be used if using the PC (R7). It is unlikely that the PC
would be desirable as a pointer.

[O{i

1]1011000|xxx[RRR]
L1

J;fi,_J

OP CODE

STACK
POINTER
11-1603

Figure 3-6

FIS Instruction Format

The operands are located on the stack as follows:

(R)

= High B Argument

(R)+2

HIGH FRACTION |
6

Low B Argument

(R)¥4 = High A Argument
(R)+6

EXP

= Low A Argument

LOW FRACTION

15
|

3-6

]

The floating-point answers are stored as follows:
(R)+4 = High Answer
(R)+6 = Low Answer

The floating-point stack pointer is repositioned to point to (R)+4 (High Answer).
The floating-point octal coding is in the form 0750XR. There are four FIS instructions, as follows:
FADD

07500R

Floating-ADD

Operation:

[(R) +4 O (R) +6] « [(R) +4 O (R) +6] + [(R) O (R) +2], if result =>2-12%;
else [(R) +4 O(R) +6] <0

Condition Codes:

set if result <O; cleared otherwise.

(See Note Below)

setif result = 0; cleared otherwise.

cleared

Description:

Adds the B argument to the A argument and stores the result in the A argument position
on the stack. A < A+B

FSUB

07501R

Floating-SUBtract

Operation:

[(R) +4 O (R) +6] < [(R) +4 O (R) +6] - [(R) O (R) +2], if result >2-"2%;

else [(R) +4 O (R) +6] <0

Condition Codes:

(See Note Below)

setif result = 0; cleared otherwise.

cleared

Description:

set if result < O0; cleared otherwise.

Subtracts the B argument from the A argument and stores the result in the A argument
position on the stack. A < A-B

FMUL

07502R

Floating-MULtiply

Operation:

[(R) +4 OO (R) +6] < [(R) +4 O (R) +6] * [(R) O (R) +2], if result >2-128;
else [(R) +4, (R) +6]

Condition Codes:

(See Note Below)

setif result <O; cleared otherwise.

setif result = 0; cleared otherwise.

cleared

3-7

Multiplies the B argument by the A argument and stores the result in the A argument

Description:

position on the stack. A < A*B. If the result is <2 '?® then underflow occurs and the
destination address will contain the A argument.

07503R

FDIV

Floating-DIVide

[(R) +4 O(R) +6] « [(R) +4 O (R) +6] / [(R) O (R) +2], if result >2-1*";

Operation:

set if result <O; cleared otherwise.

setif result = 0; cleared otherwise.

cleared

Divides the A argument by the B argument and stores the result in the A argument

Description:

position on the stack. If the B argument (divisor) is equal to O, the stack is left
untouched. A < A/B. If the result is < 2 '?2, then the destination address will contain
the A argument.

NOTE

of a floating instruction, the
If a trap occurs as a function.
‘condition codes are reinterpreted as follows:
N:

set if underflow, cleared if overflow.

cleared

set if underflow, overflow, divide by 0 (error
conditions).

setif divide by 0, otherwise cleared.

Traps occur through the vector 244. (R) is reset to point to
high B argument on the stack. The arguments are left
untouched.

3.2.4

Programming Example

CSECTY

gavdee’

FISEXM

1972

MAYNARD,

DIGITAL

EQU]IPMENTY

CORPORATIOQON,

MASSACHUSETTS,

EXAMPLE OF PDP=11/4@ FLQATING

INSTRUCTIQON SET USAGE

COMPUTE

LARGER

R0QT

0oF

QUADRATIC

SQRT(B#B

EQUATIONI

AeXwX

BaxXx

ALGORITHM

ISt

TITLE

ROOTL

(eB

e e i

ol ol
VM ONdOUNSDH WP
o IS
¢
Ul [AENETR
S

A sample floating-point program is given below.

3-8

4#AuC))/(204)

(F!S)

"\\

Condition Codes:

(See Note Below)

else [(R) +4 OO (R) +6]

RESULT

TERMINATION

30
31

32
34
35

3¥%9

200001
pearan2
Q02223
o00004
20005
ProRas
gapag?

R1
R2
RJ

2%1
=%2
a%3

z%4

- 8%5

=%7

;

eogog

NQRMAL

pogege

IMAG.,

}

MEMQRY

DISCRIMINANT

HALT

AZERQ

212786
303442

[

PROGRAM

STARTS

HALT

DANE,

LOCATION

#STACK,SP

JINITIALIZE
JB

B¢2,=(SP)

Rag1e

MQV

By=(SP)

pagL4

@16746

MQV

B*2,~(SP)

MQV

Bys(SP)

p75026

FMUL

CLR

» (SP)

212746

MOV

#2F4.0,-(SP)

MOV

A®2,=(SP)

216746
AA0142
gn1457

MQV

Ay*(SP)

BEQ

Pl6746
gegl4ds
peps2 216746
gagi4n
gogs6 g75026
gopend g75026
pageée2 Q75016
Rop64 100446

MOV

AZERD
Ce2,=(SP)

MOV

Ci=(SP)

FMUL
FMUL
FSUB

SP
SP

gapnil74
wRAR2e
vegz4
grpce
ep3n

eag34

216746

gaR4D

0op44

gesp4é6

p16746

pop6s

012667

gae72

on@13n
012667
g2p126

Qo102
Ap1n4
201a6

ga112

BMI

MQV

ge4567

200208206
70421
geR222
@10067
Ro@114
210167
gep112

gn1le

gRr122

p3126

g16746
geaa7r?2
P16746
P2RN264
062716

1202202

SP
IMAG

(SP)+,TEMP1

MQV

(SP)+,TEMP1+2

JSR

R5,)SQRT

, %4

MOV

TEMP1
R@, TEMP2

MOV

R1:TEMP2e¢2

WORD

STACK

FAGAIN

JFORM BeB
}J4,2 TO STACK

STACK

JHALY

IF A = @,
TO STACK

JFORM AsC
JFORM 4,eA@(
JFORM B#Bed wAsC (DISCRIMINANT)
JBRANCHW IF NEGATIVE
JSTORE DISCRIMINANY

JCALL

FORTRAN

ISTORE

RESULT

SQUARE

JCOMPUTE

STACK

740620

Qoo46

pog76

PROCESSQR

Pa@166

2apl52

LOCATION

éTART: MOV
MOV

THEN

€,

HERE

220204
#16746
paR176

HALT

ROOTY,

a%6

216746

AND

DECLARATIQNSI

poav4

NEGATIVE

26
27

NORMAL

B, AND C ARE
LOCATIONS A,
COMPUTED AND STORED
A,

VALUES

PLACED

WVWEe

INITIAL

19
20

ROOTY

MOV

B®2,«(SP)

MOV

By=(SP)

ADD

#iooeed,esp

)JB

STACK

INEGATE

STACK

ROOT

ROUTINE

PR136

69
70

gR142
gr144

gU150

2154

01680

Po174

78
79
8@

Po200
po2n2
pR2a4

MQV

TEMP2,=(SP)

FADD

MQV

CONST#2,«(SP)

MQV

= (SP)
CONST,

216746

MOV

A+2,=(SP)

MQV

Aye(SP)

FMUL
FRIv

MOV

(SP)+,R0O0T1

MOV

(SP)+,RO0T1+2

016746
pARB56

gagede
16746

p75@36
g12667

g20042

g12667

0202402
goapeoe
RooR0o
gnoeoe

DONE

IMAG?
AZEROQ:
}

83
84

}

TEMPYL
TEMP2;

paz232 0404080 CONST;
PB234 gogepa
89 PR236
RQOTL:
90
91
STACK}
92 po442
93
geg2@y’

TEMP2#2,=(SP)

16746
poQe64

81
82

pR206
peel2
85 gB216
86 pR222
87 pR226

MOV

ISOUARE ROOT YO STACK

}FORM eB+SQRT
12,8 Y0 STACK

STACK

IFORM

2 ,#@A

JSAVE

RESULT

JFORM

(=B#SQRT)/(2,84)

HALT

HALT
HALT

BLKHW
BLKW

BLKW

+BLKN
1 BLKW
FLT2
1 BLKW

' GLOBL
1 BLKW
' BLKH

SQRT

JEXTERNAL SUBROUTINE

}JSTART OF STACK 1S ToP OF AREA

JROOM

100

END

3-10

FQR STACK

\m/)

eape272
16746
PRQ064
2752086

gegaz2
2164 75026
Bn166
RA179

916746

NN NN

p2132

APPENDIX A

GLOSSARY OF TERMS

Table A-1 contains a collection of some of the terms used in this manual that may need defining. It does not include
all terms, only those that it is thought might be confusing. Listing is in alphabetical order.

Table A-1

Glossary of Terms

Term

Definition

ADD

Add (instruction)

ADR

Address

ALU

Arithmetic Logic Unit

ALUM

Arithmetic Logic Unit Mode

ARGA

Argument A (f/f)

ASH
ASHC

Arithmetic shift (instruction)
Arithmetic shift combined (instruction)

BBSY

Bus busy

BRQ

Bus request

BUS

Unibus

BUS U

Bus microprogram

BUSY

Busy

BUT

Branch microprogram test

CIN
CLK

Carry-in (ALU)
Clock

CLKB

Clock B Register

CLKBA

Clock BA Register

CLKD

Clock D Register

CLKOFF

Clock off

CLR

Clear C,V,N,Z (instruction)

CON

Constant

COUT MUX

Carry-out multiplexer (ALU)

C1 BUS

C1 of Unibus

DAD

Discrete alteration of data

DEST

Destination

DIV

Divide (instruction)

DMUX

Data multiplexer

EINSTR

Extended Instruction

EIS

Extended arithmetic instruction set

A-1

Table A-1 (Cont)
Glossary of Terms

Definition

Term
EPS
EUB

Extended Processor Status
Extended microprogram bus

EXP

Exponent

Extended microprogram pointer

EUPP

Function of

Floating add (instruction)

FADD

Floating C1 Bus

FC1BUS

FDIV
FETCH

Floating divide (instruction)
Fetch (Processor State)

Floating Instruction
Floating instruction set

FINSTR
FIS

Floating multiply (instruction)
Floating subtract (instruction)

FMUL
FSUB

Floating microprogram bus

FUB

Instruction register
Instruction set processor

IR
ISP

Jam microprogram pointer

Multiply (instruction)

Overtlow
Program Counter
Processor Status Register
Scratch Pad Register
Reserved instruction
Select arithmetic logic unit

Select arithmetic logic unit mode

SALUM
SBC
SERVICE
SET COND CODES
SF
SFV1

Select B constant
Service
Set condition codes
Source field
Source field ORed with 1

SRC

Source (processor major state)

STPM

Special Trap Pointer Marker

TRAP
U

Microprogram

User call

Microprogram branch field
Underflow

UBF
UNFL

Microprogram pointer

UPP

Microprogram word

U WORD

Vector

VECT

Exclusive OR (V)
“Z” bit previous state (flip-flop)

XOR
ZB

A-2

Multiplexer
No operation

MUX
NO-OP
OVFL
PC
PS
R(x)
RSVD INSTR
SALU

JAMUPP

MUL

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EK-KE11E-TM-002

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