Digital PDFs

EK-KDFEB-UG-001

2000

372 pages

Original

92MB

view download

OCR Version

31MB

view download

Document:	KDF11-BA CPU Module User's Guide
Order Number:	EK-KDFEB-UG
Revision:	001
Pages:	372
Original Filename:

OCR Text

EK-KDFEB-UG-001

KDF11-BA CPU Module

User’s Guide

SN
A S

et T

’ KDF11-BA CPU Module
User’s GGuide

Prepared by Educational Services
of
|
Digital Equipment Corporation

Ist Edition, January 1982

The material in this manual is for informational purposes and 1s subject to change without notice.

Digital Equipment Corporation assumes no responsi-

bility for any errors which may appear in this manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000 computerized

typesetting system.

The following are trademarks of Digital Equipment
Corporation.
DIGITAL

DECsystem-10

MASSBUS

DEC

DECSYSTEM-20

OMNIBUS

PDP

DIBOL

OS/8

DECUS

EduSystem

RSTS

UNIBUS

VAX

RSX

DECLAB

VMS

IAS

‘

MINC-11

11/82-14

CONTENTS
Page

PREFACE

—
—

DN bW N
N

)
pud
pd
ok
e
ot
ot
o
)
j—)
et

W —
L h LB

fnd
—
p—t
ol
ek

o L
© 00

ket

B B B B R B B B

—d

p—

CHAPTER 1

CHAPTER 2

SPECIFICATIONS

INTRODUCTION oo
e
FE AT UR E S oo
t
o
SPE CTIFICATIONS o
PROCESSOR HARDWARE ... e
General-Purpose REgIStETs ....cooueiiiiiiiiiiiiiiiiii
BUS CYCLES. .ttt
Addressing Memory and Peripherals...............ooo
Memory ManagemEnt .........coouiiiiiiiiiiiiiii e
Processor Status Word (PS) ...
Condition Codes (PS bits <<3:0>>) .o
Trace Bit (PS bit <C4=>) .ot
Priority Level (PS bits <C7:5>>) .o
Suspended Instruction (SI) (PS bit <<8>>) ..o
Previous Mode (PS bits <TI3:12>>) coiiiiiiiiiii
Current Mode (PS bits <<15:14>>) oo,
INSTRUCTION SET ..ottt
FLOATING-POINT OPTION ..o,
COMMERCIAL INSTRUCTION SET OPTION ..o
MEMORIES AND PERIPHERALS ... oo s
RELATED DOCUMETNS .. o

1-1
1-1
1-2
1-3
1-3
1-4
1-4
1-5
1-6
1-6
1-6
1-6
1-7
1-7
1-7
1-7
1-8
1-8
1-8
1-8

INSTALLATION

t 2-1
e e e e e ee
INTRODUCTION ett
. 2-1
..
TION
CONFIGURA
SWITCH
AND
JUMPER
- 2-1
tt
ot
..
JUIMIPEIS
TESt
Manufacturing Test JUMPETS .....ccoovriiiiiiiiii 2-3
e 2-3
UART TSt JUMPET...tiiiiiiieeeiiiiiiiiicee
iee s 2-3
e
Field Service Test JUMPET.......iiiiiiiiiiiiiiiiiiii
2-4
t
i
eiiiaiiieiiie
JUINPETS....cevuvi
OpPtion
CPU
Power-Up Mode SeleCtion .........coooiiiiiiiiiiiiiiie e 2-4
Halt /Trap OPtion .....ccooiiiiiiiiiiiis 2-5
On-Board Device Selection JUMPErs ... 2-5
Bootstrap/Diagnostic Switches and JUmMpPers ..., 2-7
Bootstrap/Diagnostic Configuration Switches...........ccoooiiin, 2-7
Bootstrap/Diagnostic ROM JUmMPETS ..o 2-8
Console SLU Switch and Jumper Configurations.............cooooiiiiiniinnnnie. 2-9
e 2-9
Console SLU Baud Rates . ...ccoooiiiiiiiiieiiiiie
iiiini 2-10
Console SLU Character FOrmats .........oooooeiiiiiiiiie
Break-on-Halt JUMPETS.......uveiiiiiiiiiiieiiiiiiiiiee e 2-11

CONTENTS (Cont)

2.2.6
2.2.6.1
2.2.6.2

2.2.7

2.2.8
2.3

Second SLU Switch and Jumper ConfigurationsS.......cccoovvveeoeeeoii

Second SLU Baud Rates.....oooovvvoi

Internal/External SLU Clock Jumpers.............oo.oooooiiioiioiioooe
Bus Grant Continuity JUMPEeTs ........ccccoiiiiiiiio
e

FACTORY SWITCH AND JUMPER CONFIGURATIONS ...

2.4

MODULE CONTACT FINGER IDENTIFICATION ..coooviiiiiiiiio
BACKPLANE PIN ASSIGNMENTS AND THEIR KDF11-BA

2.5

UTILIZATION oo
2.6

2.6.1

2.6.2
2.6.3

2.6.4
2.7

2.8

BacCKplanes ......coo.oooiiiiiiii

e
ENCIOSUTES ... e

MeEMOTY MOAUIES ...t
Peripheral OPtionS .....occuuviiiiiiiiiiio

e
SYSTEM DIFFERENCES ...

CHAPTER 3

W N

3.1

—

INTERFACE ...

B W
-

Lo Lo Lo Wo Lo Lo W

Lnmhnhnn
n b b

ODT OPERATION OF THE CONSOLE SERIAL-LINE
Console ODT Input SEqUENCE .........ooviiiiiiiieee e
Console ODT Output SEqUENCE .......oooviiiiiiei oo
CONSOLE ODT COMMAND SET ...t
J(ASCIT 057) — SIaSH oo,

<<CR> (ASCII 15) — Carriage RetUrn .......oooviveeeeeeeeeeeee e
<LF> (ASCIT 12) —Line Feed ...........cooommeeeeeeeeeeeee

$ (ASCII 044) or R (ASCII 122) -

.L)JL)J
= o

AN Lo
N =

O OO0 3 O\

Internal Register Designator ............ooooviiiiioie

e
S (ASCII 123) — Processor Status Word Designator ............ooovveivoiviii]
G (ASCIT 107) = GO e,

P (ASCII 120) — ProCeed ......c.ovviiiiieeeeeee e
Control-Shift-S (ASCII 23) — Binary DUump ........coooveooooeeeeeoeoee
Reserved Command............e
Processor I/O Addresses .......oo.oouviioieeioiiieeeeeeeeeeeeeeeeT
Stack Pointer Selection.............ooooiiiiiiii
e
Entering of Octal Digits .........oooiiiiiiiii
e
ODT TIMEOUL ..ot

CHAPTER 4

CONTENTS (Cont)

i
fo —

W
LW
L
W
W

kel
et
e

Page

4.
4.5

4.5.1

4.5.2
4.5.3

4.6
4.6.1
4.6.2

4.6.3

4.6.4

4.6.4.1
4.6.4.2
4.6.4.3

4.6.4.4
4.6.5
4.7

Bus Cycle ProtoCoL.......oiuiiiiiiiiiiiiiii 4-4
Device AdATESSING . ....ooiiieiiieee it 4-4
D A T oot 4-5
DATOB) .ot 4-8
DATIOB) ..o 4-10
DIRECT MEMORY ACCESS (DMA) ..ot 4-10
e e e 4-13
IN T E R RIU P TS .ottt
DIEVICE PrIOTIEY .vvveiieiiie ettt 4-16
INterruPt ProtOCO] .. .ot 4-16
4-Level Interrupt Configurations..........coovviiiiiiiiiiii 4-19
CONTROL FUN CTIONS e 4-20
Memory RefTesh .. ..o 4-20
IPPPPRPPIRS 4-20
TP RO PP
| O T TTUT TP U T U s T
e 4-20
e
LI ZAEIOMN et e e et e et e e e
IEIA
P OWET STATUS .ovneeeeeeeeeee e et e e et e e e e e e et e e e et e e e e e e e s e e e e e aar e e e e e e 4-21
et 4-21
BDCOK H oo
O K H oo 4-21
B
POWET-UD ..ottt 4-21
POWET-D OWI. oo 4-22
BE VN T Lottt 4-22

BUS ELECTRICAL CHARACTERISTICS ... e 4-22

4.8.3

Signal-Level Specification..........occooiiiiiiiiini 4-22
AC Bus Load Definition c......ooiiiiiiiiieeiee ettt 4-22
e 4-22
DC Bus Load Definition ........oeiiiiieiiiiiiiiiiiee
e e e e e e 4-23
120 © LSToTT BuUS . uuuueniee et ettt
eSUPUUURUTRT 4-23
e e ettt
BUS DITIVETS ..ot
BUS R CEIVETS. . eeeen ettt et ettt 4-24
e e e e 4-24
BUS TEITINATION vttt e et e et e e e e ettt eeee e
4-25
e
Bus Interconnection WITINg.....ooooueueemimmmimieiiiiiiiiiiiiiiieieeeee
Backplane WIrNE ......coovioiiiiiiiiiiiiiie i 4-25
Intrabackplane Bus WITing ..........ccoooiiiiiiiiiiii 4-25
Power and GIoUNd ........ooveiiiiiiiiee e 4-25
Maintenance and Spare PIns ... 4-26
SYSTEM CONFIGURATIONS ..o 4-26
Rules for Configuring Single-Backplane Systems ..o 4-26
Rules for Configuring Multiple-Backplane Systems ... 4-27
Power SUpply Loading.......cocoeoiiiiiiiiiii i 4-28

CHAPTER 5

FUNCTIONAL DESCRIPTION

4.7.1

4.7.2
4.7.3

4.7.4

- 4.7.5
4.7.6
4.7.7

4.7.8
4.7.8.1
4.7.8.2
4.7.8.3

4.7.8.4
4.8

4.8.1

4.8.2

5.1

5.2
5.3

5.4
5.5

5.6
5.6.1

5.6.2
5.6.3

e
ION Lot
INT R ODUCT
e
t
T A CHIP oo
DA
CONTROL CHIP ..o
IMIMU CHIIP oot
e
BASE TIMING LOGIC ..ot
.
MIB DECODE LOGIC ..
MIB Decode During Phase Time ...,
MIB Decode at the End of Phase Time .......ccoooviiiiii
MIB Decode at the End of Phase-Bar Time .......ccccoooeiiii

5-1
5-1
5-4
5-4
5-4
5-6
5-7
5-8
5-8

CONTENTS (Cont)
Page
5.7

5.7.1
5.7.1.1
5.7.1.2
5.7.2

5.7.3
5.7.4
5.7.5
5.7.6
5.7.7

5.8
5.9
5.9.1

5.9.2
5.9.3

5.10
5.11
5.12
5.13

5.13.1
5.13.2

5.14
5.14.1
5.14.2
5.14.3
5.14.4

5.14.5

BUS CONTROL LOGIC ...,

5-8

Bus Synchronizer Circuits......................... PR
RPRPPI

5-9

BRPLY, BSYNC, BSACK, BDMR Synchronization...........ccc.cc.......... 5-10

BDCOK and MCENB Synchronization ..........c.ooooeveeoeoioiieeeeeeee 5-10
Direct Memory Access (DMA) Control.........cccovveiiiieeeiiiieieiee
e 5-10
Address Microcycle Control..............ooooiiiiiiiiiiii
e 5-11
BSYNC Signal ..o 5-12
Noninterrupt Bus DIN CyCles. ... 5-12
Interrupt-Type Bus DIN Cycles .........ooooiiiiiii
e, 5-12
BUS DOUT CYCle..uiiiiiiiiiiiiiiee
e, 5-13

CDAL/BDAL INTERFACE ... 5-14
SERVICE, RESET, AND ODT LOGIC ... 5-14
Read Service Operation..............ooooiiiiiiiiiiiiii
e, 5-16
F11 Chip Reset Operation..........ooovviiiiiiiiiiiiii
e, 5-18

ODT Address LOZIC......coouviiieiie e 5-19
FIXED DATA DIN CYCLES ... ..., 5-20

CDAL/IDAL INTERFACE ... 5-20
IDAL ADDRESS DECODE ... 5-22
BOOTSTRAP/DIAGNOSTIC AND LINE CLOCK LOGIC ... 5-24
Boot and Di1agnostic LOZIC.........oooiiiiiiii

e 5-25
Line Clock RegISter....oouviiiiiiiii e 5-26

SERTAL-LINE UNITS ... e 5-26
Universal Asynchronous Receiver Transmitters .......ccocvvvevveeeeemeiveeiiii ... 5-26

The DCOO03 Interrupt Logic CirCUits......oooviiiiiiii oo, 5-29
Register Read Operations............ooooviiiiiiiii
e 5-29
Baud Rate Generator............ooouvviiiiiii
e 5-29
Charge Pump CirCuit......oooviiiice
e 5-30

CHAPTER 6

ADDRESSING MODES

6.1

INTRODUCGCTION ...t
INSTRUCTION FORMATS ...

6.2
6.3

6.3.1
6.3.2

6.3.3

6.3.4

W
Lo
WO
Lo

\O \O O

6.3.5

3.9.2

6.3.9.
6.3.9.4

6.3.10

6.3.11
6.3.12
6.3.13

ADDRESSING MODES... ...
Register Mode (Mode 0) ....oovvvviiiiiiiii

Register-Deferred Mode (Mode 1) ... e
Autoincrement Mode (Mode 2) ...
Autoincrement-Deferred Mode (Mode 3) ...oooovvimmmmeeee
Autodecrement Mode (IMode 4) .........ooooiiiiiiiiieeee

e
Autodecrement-Deferred Mode (Mode 5) ..o,
Index Mode (Mode 6)........oooiiiieee
e
Index-Deferred Mode (Mode 7) ..o
Use of the PC as a General Register .........cccccovveennnnn.. e,
PC Immediate Mode (Mode 2) ...

6-1

6-2
6-3
6-3
6-4
6-5
6-5

6-6
6-6
6-7
6-7
-8
6-8

PC Absolute Mode (Mode 3) ... 6-9
PC Relative Mode (Mode 6) .......oooooiiiiiiiieeeeeeeeeeeeeee e 6-10
PC Relative-Deferred Mode (Mode 7).....ccoovmoooe e 6-10
Direct Addressing Modes SUMmMATY............oooooiiiiiiiiiii
e 6-11
Indirect Addressing Modes SUummary ...............cooovoiie i 6-11

PC Register Addressing Modes SUMMATY .....ooouvviiieeimieieieee
e 6-12
Graphic Summary of Addressing Modes .............ccccoiiiiiiiiiiiieee 6-12

CONTENTS (Cont)
Page

LN
—

ok e
ke

et ok
b

T T R R T NS +—
NR

P B

CHAPTER 7

I NERE SIS b B B —
B W |\

00
0O 0O

B W N —

CHAPTER 8

8.3.4.1
8.3.4.2

8.3.4.3

8.3.4.4
8.3.4.5

8.3.4.6
8.3.5
8.3.6
8.3.7
8.4
8.4.1
8.4.2

INSTRUCTION SET

e
INTRODUGCTION oottt
s
Single-Operand INStrUCIONS .......ovoieiiiiiiii
Double-Operand INStrUCLIONS .....coviiiieiriiiiiii i
Double-Operand Instruction Format ...
e
Byte Instructions .........ccooooveniiiiiiiiinnn. e
iii
iiii
Program Control INStruCtioNS .......ooeii
e snnaiaees
eiii
eesasaa
e
e
eeeee
aaassssn
eeeee
eeeeetaanane
e
BrancCh TNSTIUCTIONS vveeneeeeeeeiee
iis
iiiii
.covi
Jump and Subroutine INStrUCtIONS .....
e
iiii
Condition Code INStruCIONS......ooiiiiiiiieiiiii
iiii
e
e vuur
Miscellaneous INSTIUCTIONS ......ov
Examples of Single-Operand, Double-Operand,

7-1
7-1
7-3
7-3
7-4
7-4
7-4
7-5
7-7
7-9

een 7-9
ne b ee
eteeee
iiii
e e e e e ees
eiee
e e et eeeeiae
ANd BranCh INSTIUCTIONS ... ceeeeeen
7-9
.
.
Single-Operand Instruction Example .
7-9
.
.
Double-Operand Instruction Example .
7-10
iiiii
oviii
.oooo
Branch Instruction EXample .....
INSTRUGCTION SET ..o 7-11
MEMORY MANAGEMENT

e e s e e e e e s s s s s st
INTRODUCTION .o
b
PrOZIAIITIITIE ...vvee vt eeen et
Basic AQATESSINE. .. .eeeuriiereeeeeiee e ettt
Active Page REGISTEIS ..ooiiiiiiiiiiiic it
Capabilities Provided by Memory Management ...,
MEMORY RELOCATION ..o
Program RelOCAtioN ........ccoiiiiiiiiiiiiiiii
MEIMOTY UTIES ....tenteniei ettt
MEMORY MANAGEMENT REGISTERS ...
Page Address Register (PAR) ..o
Page Descriptor Register (PDR) ..o
Access Control Field (ACEF) ...
Expansion Direction (ED) ...

8-1
8-1
8-2
8-2
8-3
8-3
8-3
8-5
8-5
8-5
8-5
8-6
8-6

Write AcCesS Bit (W) oo 8-7
Page Length Field (PLF). ..o 8-7
PAR/PDR Address ASSIZNMENTS .....covoioiiiiiissiiie 8-9
Status Register O (SRO) — Address: 177775728 ..cccooviiiiiiiiiis, 8-9
e e 8-10
e e e et
e e e e e et t
ADOTt INONTESIACTIE 1o
8-10
o
.
Abort Page Length .
8-10
i
iiiiiiiiii
AbOrt Read-Omnly ....oooviii
8-10
e
iiiiiiieieis
Mode Of OPETAtION .....eivviii
Page NUMDET.....ooiiiiii s 8-10
Enable Relocation and Protection ........ccooooeiiiiiiiiiinii 8-10
Status Register 1 (SR1) — Address: 177775748 oo, 8-10
Status Register 2 (SR2) — Address: 177775708 .....cccooimmiiiiinii, 8-10
Status Register 3 (SR3) — Address: 177725108 ..c.cccooimiiiiiniin, 8-11
VIRTUAL AND PHYSICAL ADDRESSES ... 8-11
Construction of a Physical Address .......c..cooviiiniii 8-11
Determining the Program Physical Address...........ooooiii 8-14
vil

CONTENTS (Cont)
Page
8.5
8.5.1
8.5.2
8.5.3

8.5.3.1

8.5.3.2
8.5.3.3

8.5.3.4
8.6

PROTECTION ..o e

8-14
e 8-15
Read-Only Memory .......cooioiiiiiioeeoe e 8-15
Multiple Address SPace...........ccoovviiioeiiioeeeee e 8-15
Mode Specification in the Processor Status Word .........ocoovovoivi 8-15
Inaccessible MemOTY ........oouoiiiiiiiiiio

Processor Status Word Protection..........ccoooveeeeooeeo 8-16
User Mode ReStrictions..............ocoooeoeeos oo 8-16
Interrupt and Trap Processing..........c.oocoooeoeomoeooee oo 8-16
MEMORY MANAGEMENT INSTRUCTIONS ..o
8-18

CHAPTER 9

FLOATING-POINT ARITHMETIC

9.1

INTRODUCTION ..ot
FLOATING-POINT DATA FORMATS ...oooooooeoeeeoeeoe

9.2
9.2.1

9.2.2
9.2.3

9.2.4
9.3

9.4
9.5
9.6

9.7

Nonvanishing Floating-Point Numbers ..........coccoooooioio
F1oating-Point Zero........c.cooiiiiiiiiieeeeeoeeeeeeeeeee e

The Undefined Variable ................ocoooooiio Floating-Point Data ................oc.ooiiiiii oo
FLOATING-POINT STATUS REGISTER (FPS)...cvooooeoo
FLOATING EXCEPTION CODE AND ADDRESS REGISTERS ...
FLOATING-POINT PROCESSOR INSTRUCTION ADDRESSING........
ACCURACQCY .o
FLOATING-POINT INSTRUCTIONS . ...c.oo oo

9-1

9-1
9-1

9-2
9-2

9-2
9-4

9-4
9-8
9-8
9-9

CHAPTER 10

PROGRAMMING TECHNIQUES

10.1

INTRODUCTION ..ot 10-1
POSITION-INDEPENDENT CODE.......c.ccooooioooooooeeeeoo 10-1
Use of Addressing Modes in the Construction of
Position-Independent Code..............oc.ooiooiimooeooee e 10-1
Comparison of Position-Dependent and

10.2

10.2.1
10.2.2

10.3

10.3.1

10.3.2
10.3.3

10.3.4
10.3.5
10.3.6

10.3.6.1
10.3.6.2

10.3.7
10.3.7.1
10.3.7.2

10.3.8
10.3.8.1

10.3.8.2

10.3.9
10.3.9.1

Position-Independent Code..............occoooemoioeoio e 10-3
STACKS ..o 10-4
Pushing onto @ Stack.............ocooiiiiioo e 10-5
Popping from a Stack ..........ccooooiiiiioioee
e 10-6
Deleting Items from a Stack.............c.ooooovioiooao oo 10-6

STACK USES ...t 10-7
Stack Use EXAMPIES ...c.oovvouiiiiiiieicoeoeee oo 10-8
Subroutine Linkage ..........occoooviivioiiieooeeoeee e 10-10
Return from a Subroutine ..o 10-10
Subroutine Advantages ..............c..oooooioiio e 10-10
INTETTUPTS ..o 10-10
Interrupt Service ROUtines ...............oooooviioeooeeo o 10-11
INESTINE ..o
e 10-11

REENtrancCy........cocoooiiiiiii e 10-11

Reentrant Code ..o 10-13
Writing Reentrant Code...............oooooiiiimio
e 10-13
COTOULINES ...ttt 10-14
Corouting CallS.......ccooiiiiiii
oo 10-14

CONTENTS (Cont)
Page

10.3.9.2

Coroutines Versus SUbroutines............cooeeiiiiiiiineiiiiiiiicie e 10-14

10.3.9.3

USING COTOULINES ...oovvviieeiiiiiiiiie
e e
ettt e e e e e e e e e e e e rvae e e e eeaaens 10-16

10.3.10

RECUTISION ...
e
e
e
e e 10-18

10.3.11

ProCeSSOr Tra
S . cciiiiiii e 10-19

10.3.11.1
10.3.11.2

10.3.12

Trap INStIUCHIONS c.ovueiiei e 10-20

Use of Macro Calls.......coooiiiiiiiiii

e, 10-21

Conversion ROULINES .........uoviiiiiiiiiiiiiii
e
e et 10-21

10.7

PROGRAMMING THE PROCESSOR STATUS WORD........ccooooeeiiiiiii, 10-25
PROGRAMMING PERIPHERALS. . ... 10-25
PDP-11 PROGRAMMING EXAMPLES ..., 10-26
LOOPING TECHNIQUES. ......oooeeee e, 10-31

CHAPTER 11

BOOTSTRAP AND DIAGNOSTIC LOGIC

10.4
10.5

10.6

11.1

INTRODUCGCTION. ...ttt
e
e,

11.2

11.4.2

BOOTSTRAP AND DIAGNOSTIC REGISTERS ... 11-1
Page Control Register (PCR) — Address: 17777520 ..., 11-2
Read/Write Maintenance Register (R/W) — Address: 17777522 ................. 11-2
Configuration and Display Register (CDR) — Address: 17777524 ................ 11-2
KDF11-BA ROM Memory
(ADDRESSES: 17773000—17T7T3777) ueeiieiieiiiiiiiiiieee e, 11-2
KDF11-BA BOOTSTRAP AND DIAGNOSTIC
FUNCTIONALITY o 11-3
KDFI11-BA LED Display ... 11-3
KDF11-BA Error Halts ... 11-5

CHAPTER 12

LINE FREQUENCY CLOCK

12.1

12.3

INTRODUCGCTION. ...
e e e e e e e aeaaaae, 12-1
LINE CLOCK STATUS REGISTER (LKS) (ADDRESS: 17777546) .............. 12-1
LINE CLOCK OPERATION ..o 12-1

CHAPTER 13

SERIAL-LINE UNITS

11.2.1
11.2.2
11.2.3
11.3

11.4

11.4.1

12.2

11-1

13.1

INTRODUCGCTION. ...t e,

13.2

SERIAL-LINE UNIT REGISTERS ..o 13-1

13.3

13.5

INTERRUPT VECTORS AND INTERRUPT PRIORITY ..o 13-4
CONSOLE SLU BREAK RESPONSE ..., 13-4
SERTAL-LINE I/O SIGNALS ... 13-4

CHAPTER 14

COMMERCIAL INSTRUCTION SET

13.4

13-1

14.1

INTRODUCTION ...
e et
aeenanees

14-1

14.2

UNPREDICTABLE CONDITIONS...o
CHARACTER DATA TYPES. ...,
AT ACEET et
CharacCter STIINE ..ovuiiiieiie e
e e e vaeaans
CRATACTET SEL. uni i i i i ie
ee
Character String InStruCtIONS ........coiiiiiiii
e
e

14-1
14-2
14-2
14-2
14-3
14-4

14.3
14.3.1

14.3.2
14.3.3

14.3.4

CONTENTS (Cont)
Page

14.7.20

DECIMAL STRING DATA TYPES ..., 14-6
e 14-7
Decimal String DeSCriPtors ....ooooiiiiiiiiiiii
PACKed SETINES .ooiveieeiiiie ettt 14-8
Z/0NEA SEIINES . ..eeeiuveieeettie ettt 14-10
Overpunched STHNES ....oooviiiiiiiiii 14-11
SEPATALE SEIIMES . v eeneeeitietieie et 14-13
LONE INEEZET 1.t 14-15
Decimal String INStruCtIONS. .....covviiieiiiiiiiiii e 14-15
CONAITION COAES...eeeneieeee e 14-16
Operand DElIVETY ......coiiiiiiiiii i 14-17
Data OVETIAD ..oiiiiie it 14-17
COMMERCIAL LOAD DESCRIPTOR INSTRUCTIONS .......ccccoooiin, 14-17
e 14-18
INSTRUCTION SUSPENSION . ...
o 14-20
......o
EXTENDED INSTRUCTION DEFINITIONS...
ADDN/ADDP/ADDNI/ADDPI ..., 14-20
ASHN/ASHP/ASHNI/ASHPI ... 14-21
CMPC/CMPCL...oiiiiii i 14-23
CMPN/CMPP/CMPNI/CMPPI ..o 14-25
CVTLN/CVTLP/CVTLNI/CVTLPI ..., PR 14-26
CVTNL/CVTPL/CVTNLI/CVTPLI ..o 14-28
CVTNP/CVTPN/CVTNPI/CVTPNI ... 14-29
DIVP /DIVPL .ot 14-30
LOCC/LOCCT ..t 14-32
e 14-33
R oo et
2D
e 14-34
e
R oo
3D
14-35
t
MATC /MATCT i
14-37
MOVC /MOVCI i
MOVRC/MOVRCT ... 14-39
MOVTC/MOVTC ..o 14-41
MULP/MULPLL..c.ooiiiiiiiii i 14-43
SCANC /SCANCT ..ot 14-44
SKPC /SKPCT ... 14-46
SPANC /SPANCT ... 14-48
SUBN/SUBP/SUBNI/SUBPI ..o, 14-50

APPENDIX A

GENERAL REFERENCE INFORMATION

14.4

14.4.1
14.4.2
14.4.3

14.4.4
14.4.5

14.4.6
14.4.7

14.4.8
14.4.9

14.4.10
14.5
14.6
14.7

14.7.1
14.7.2
14.7.3

14.7.4
14.7.5
14.7.6
14.77.7

14.77.8
14.7.9
14.7.10

14.7.11
14.7.12

14.7.13

14.7.14
14.7.15

14.7.16
14.7.17

14.7.18
14.7.19

SUMMARY OF KDF11 INSTRUCTIONS ... A-1
NUMERICAL OP CODE LIST ..o, A-8
PROCESSOR STATUS WORD (PS) 17777776t A-9
ABSOLUTE LOADER/BOOTSTRAP LOADER ... A-9
DEVICE REGISTER ADDRESSES AND VECTORS ... A-10
CONSOLE ODT COMMANDS ... A-12
T-BIT ASCIL CODE ... oo, A-13

APPENDIX B

INSTRUCTION TIMING

Al
A.2

A4
A.S

A.6

B.1

B.2
B.3

GENERAL INFORMATION ..o B-1
BASIC INSTRUCTION TIMING ..ottt B-2
DMA AND INTERRUPT LATENCIES ..., B-5

CONTENTS (Cont)
Page
APPENDIX C

LSI-11, KDF11/PDP-11 PROGRAMMING AND OPERATIONAL
DIFFERENCES

APPENDIX D

KDF11-BA BACKPLANE PIN ASSIGNMENT COMPARISON

APPENDIX E

MICRO-ODT DIFFERENCES

APPENDIX F

FUNCTIONAL DESCRIPTION OF BUS SIGNALS

FIGURES
Title

Figure No.

Page

General-Purpose REISTOTIS . ...uuuuiiiiiiiiiiiieee e

4-10

4-11
4-12
1
]
]
1

5-2

Base Timing Interface. ..o

5-5

MIB Decode LOZIC. ...

5-7

o
— O

]

KDFTT-BA PrOCESSOT....uiiiiiiiiiiie

]

ek
i

MMMMMMM%MMMMA&A
—_——— 0 W0 UL AL

AN
DN A

4-13

1-3
High and Low Bytes of a Processor Word ...,
1-5
Word and Byte Addresses for First 4K Words of Memory.......cccooooeieiiiiiiiiiinnn.., 1-5
Processor Status Word (PS) Format ...
1-6
KDF11-BA Jumper, Switch, and Diagnostic Display Locations.....................eeee., 2-2
Quad Module Contact Finger Identification...............cccoooiiiii
i, 2-17
H9276 Backplane Pin Identifications .............ccccviiviiiiiiiiiiiiiiiiiiie
e 2-18
Typical KDF11-BA S12K-Byte System........ooooiiiiiiiiiii
e 2-19
DATI BUS CYCLE .oueniee e
4-6
DATI Bus Cycle TIMING .....ooiiiiiiiiii e,
4-7
DATO or DATO(B) BUS CyCle .ovvniiiiii e
4-8
DATO or DATO(B) Bus Cycle Timing.........cooooiiiiiiiiiiii
e,
4-9
DATIO or DATIO(B) Bus CyCle ...oooviiiiiie
e 4-11
DATIO or DATIO(B) Bus Cycle TIMING......ccooeieiiiiiiiiiiiiieeee e 4-12
DMA Request/Grant SEQUENCE .......coovuiiiiiiiiiiieeiiiie
e, 4-14
DMA Request/Grant Bus Cycle Timing...........ccccceeeviiiiine e 4-15
Interrupt Request/Acknowledge Sequence...........ccoooiiiiiii, 4-17
Interrupt Protocol TimIng........ooviiiiii
e 4-18
Position-Independent Configuration ..............ooooiiiiiiiiiiiiiii
e, 4-19
Position-Dependent Configuration...............oeiiiiiiieiiiiiiiiiie e 4-20
Power-Up /Power-Down TIming........ccoocviiiiiiiiiiiii
e, 4-21
Bus Line Termination .......cccoooouiiiiiiii
e
e
e e 4-24
Single-Backplane Configuration ............ccccoiiiiiiiiiiiiii
e 4-27
Multiple-Backplane Configuration ..............cooiiiiiieiiiiiiiiiiieee
e 4-28

KDF11-BA Bus Control Interface ............oooooooiiii
e,
5-9
CDAL/BDAL Interface.........cccocceeeveiiiennn PO
PO SO OUPPRRPRTIOY 5-15
Service and Reset Logic Interface. ..., 5-16
KDF11-BA ODT Logic Interface..........coooiiiiii
e, 5-19
Fixed Data LOZIC ...oooviiiii e 5-21
CDAL/IDAL INterface.....ccoooviiiiiiiiiiiiiii
e 5-21
IDAL Address Decode LOZIC ..o 5-23

Bootstrap/Diagnostic and Line Clock LogIC .........ccccoiiiiiiii 5-25
e e 5-27

Ser1al-Line UnitS .. ..o

FIGURES (Cont)

Title

Baud Rate Generator and — 12 V Charge Pump......ccooooveiiiiii,

Single-Operand Instruction Format ..o
Double-Operand Instruction Format ...
Register Mode Increment Example ...
i,
Register Mode Add EXample........c.oooooiiiiiiiiiiiii
Register-Deferred Mode Example ...
Autoincrement Mode EXample ..o
Autoincrement-Deferred Mode Example ...,
i
Autodecrement Mode EXample ......ooooiiiiiiiiiiiiiii

Autodecrement-Deferred Mode Example ...,
Index Mode EXAmMPIE......ooiiiiiiiiiieeiiiiiceeei

e
Index-Deferred Mode EXample .....cooiiiiiiiiiiiiiiiiii
PC Immediate Mode EXample ......oooovviiiiii
iiiiii
e
PC Absolute Mode EXample.........ooooiiiiiiiiiiiii
PC Relative Mode EXampPle ......ooooiiiiiiiiiiiiiciiiii
PC Relative-Deferred Mode Example ...
General Register Addressing Modes ..o
Program Counter Addressing Modes...........ccooiiiiiiiii
Single-Operand Instruction Format ...
Double-Operand Instruction Format ...

e e
Branch InStruCtion FOTIMAt . oeoroee et
e e e ee e e e
e
TSR INStrUCION FOTIMAL oo oniiei ettt
et e e e e e e e e e e aeeeanees
RTS INSEIUCHION FOTITIAL ¢ oniiniin ettt
Condition Code Operators Format..........ccoooooiiiiiiiii
Active Page RegISters ....uuii i

Memory Relocation, Simplified Block Diagram ...

Relocation of a 32K-Word Program into 2 Megawords

Of PhySiCal MEMOTY ....veiiiiiiiiiiiiiic i
Page Address ReGISTEr ....ouiiuiiiiiiiiiiiii i
Page Descriptor REeZISTET .....eviiiiiiiiiiiii

Example of an Upward-Expandable Page ...
Example of a Downward-Expandable Page.............cccooi
e
Format of Status Register O (SRO) .....ooooviiiiiiii
Format of Status Register 2 (SR2) ...ouvviiiiii
Format of Status Register 3 (SR3) ..oeeiiiiiii
Interpretation of a Virtual Address...........cooooiiiii
Displacement Field of a Virtual Address............ocooooii
e
Formation of @ Physical Address ........cooooiiiiiiiiiiiii
i
Single-Precision FOrmat..........oooiiiiiiiiiii
Double-Precision FOTMIAL «......uuueiiiiiieieieee e
2’s Complement FOrmat.........cooooiiiiiiiiii
Floating-Point Status Register.........ccooiiiiiiiiii

Floating-Point Addressing Modes ...........cooiiiiiiiiiiiiiii

WO
DN »—

NP
OC?O

Pk
e
ok

0 9

===

]

0 90 0 90 g0 00 0

O 001N

<N ONn bW
— O

]

OOOOOO\]\]\]\]\]\IO\O\O\O\?\O\O\O\O\O\O\O\O\O\O\O\O\M
U,)[\)h—dO\Qj].hwl\)h—ih—diL‘t—‘h—ir—‘r—‘t—‘)—-fl\ow\]O\U] BSOS e

Figure No.

10-4
10-5
10-6

Word and Byte StacKs........oooiiiiiiiiiiiieiiiic i
Push and Pop OPerations ..........cooueieriiriiiiiiiiiiiiee it

Byte Stack Used as a Character Buffer............coooi
JSR Stack Condition EXample ........oooiiiiiiiiiii
Nested Interrupt Service Routines and Subroutines ..o,
R Nt aANt R OULIMIES - onononeeen e

e e

X11

e e e

e et

FIGURES (Cont)
Figure No.
10-7

10-8

10-9
10-10
10-11

10-12
11-1

11-2

11-3
13-1

14-1

14-2
14-3

14-4
14-5
14-6
14-7
14-8

14-9

14-10
14-11
14-12
14-13

14-14
14-15

14-16
14-17

14-18

14-19
14-20

14-21
14-22
14-23

14-24
14-25
14-26
14-27

14-28

14-29
14-30

14-31

14-32
14-33

14-34
14-35

14-36
14-37

14-38
14-39

Title

Page

Sharing Control of @ ROUtING ........ooiiiiiiiiiii 10-13
Coroutine EXampPIe .....uuuuviiiiiiiiiiiiie
e 10-15
Coroutines VErsus SUDTOULINES ......uiiiiiiiiiiiiiie
e
e 10-15
COorOULINE Path oo
e 10-16
Coroutine INtEraCtION . .....iivuui ittt 10-17
Recursive Routine FIOW ... 10-18

Page Control Register Format ..........cccccoiiiiiiii 11-2
ROM Address Format Using PCR LO Byte ... 11-3
ROM Address Format Using PCR HI Byte .......cooooiii 11-3
Serial-Line Register FOrmats...... ... 13-2
8-Bit Byte CRaracCter......cc.oviiiiiiiiiiiiiiie e 14-2
Character String Descriptor .........ST
PPPTPRN 14-2
Character String in MEIMOTY .. ... uuieiaeee e 14-3
Character Set FOIMat ....coooiiiiie et
e 14-4
Decimal String DeSCIIPLOT ....uuviveiiiiiiiiiiiiiiiiie e 14-7
Packed String — Odd Digits ......ooooiiiiiiiiiii 14-9
Packed String — Even Digits ........ooooiiiiiiiiiii 14-9
Packed String — Zero Length.........oooo
14-9
ZONEA STIIMES .ovvvveieeeeee et
e e e e e e e 14-10
Trailing Overpunched STIINE ........oeeeiiiiiiii 14-12
Leading Overpunched String.......cccooviiiiiiiiiiiieiiee
e 14-12
Trailing Separate StIINE ...oooveiiiieee e 14-13
Leading Separate STIINE ......vveiiiiiiiiiieiiiii
e 14-14
Zero-Length Trailing Separate STring .........uevieiiiiiiiiiiiiiiiiiiie e 14-14
Zero-Length Leading Separate SIriNg........ceviiviiioiiiiiiiiiiiiiicieiiriiee
e, 14-14
Decimal Convert (Register FOrm) ... 14-15
Decimal Convert (In-Line Form)...........ooo 14-15
Add Decimal FOMat ..ot 14-20
Add Decimal Format (Cleared)...........oooiimiiiiiiiiieee
e 14-21
Shift Descriptor FOrmat.......ooooiiiiiiiiiiii
e, 14-22
Arithmetic Shift Decimal Format ..o, 14-22
Arithmetic Shift Decimal Format (Cleared) ........coooovviiiiiiiiiii
e 14-23
Compare Character FOrmat.........ococciiiiiiiiii 14-24
Compare Character Termination Format...............ooooii 14-24
Compare Decimal FOrmat ... 14-26
Compare Decimal Format (Cleared) .......cccooiiiiiiiiii 14-26
Convert Long-to-Decimal Format...........ccooooiiii 14-27
Convert Long-to-Decimal Format (Cleared) ...........ocoooiiiiii, 14-27
Convert Decimal-to-Long Format..............oooiiiiii 14-28
Convert Decimal-to-Long Format (Cleared) .........ccoooiiiiimimiiiiiiiiiien, 14-28
Convert Decimal FOrmat ..o 14-30
Convert Decimal Format (Cleared) .......cooooiiiiiiiiiiiiiec
e, 14-30
Divide Decimal FOrmat .....cooooviiiiii e 14-31
Divide Decimal Format (Cleared) .........ccoooiiiiiiiiiii
e, 14-31
Locate Character Format (Register Form)..........cooooviiiini 14-32
Locate Character Termination Format..............cooiiiiiiiiiiii, 14-33
Locate Character Format (In-Line)........cccoooiiiiiiiiiiii
e, 14-33
Load Two Descriptors Format ..........cccooeeiiiiiiiiiiiii
e 14-34
Load Three Descriptors Format............cccoooiiiiiiiiiiiiii 14-35

X111

FIGURES (Cont)
Title

Figure No.

14-40
14-41

14-42

14-43
14-44
14-45

14-46
14-47
14-48
14-49

14-50
14-51

14-52
14-53

14-54
14-55
14-56
14-57
14-58

14-59
14-60
14-61

Page

Match Character Format (Register Form)....................o.ooST 14-36
Match Character Termination Format .................ooooiiiiiii
e 14-36
Match Character Format (In-Line) ... 14-37
Move Character FOrmat ... e, 14-38
Move Character Format (Cleared) ... 14-38
Move Reverse-Justified Character Format................ccciiiiiii
e 14-40
Move Reverse-Justified Character Format (Cleared) ..o, 14-40
Move Translated Character Format ................oooooiiiiiii
e, 14-42
Move Translated Character Format (Cleared)..........coooooiiiiiiii 14-42
Multiply Decimal Format ..., 14-43
Multiply Decimal Format (Cleared)..........oooooiiiiiii
s 14-44
Scan Character FOrmat.........ooooiii
e 14-45
Scan Character Termination Format..............ooooiiii
e, 14-45
Scan Character Format (In-Line) .........ooooiiiiiii
e, 14-46
Skip Character Format (Register FOrm) ........cocooooiiiiiiiiiiii 14-47
Skip Character Termination Format .............ccoooiiiiiiiiiii
e 14-47
Skip Character Format (In-Line)......c.coooooiiiiiiiiiii
e 14-48
Span Character Format (Register Form) ...........ccooiiiiie, 14-49
Span Character Termination Format...........c.coooiiiiiiiiiiie
e, 14-49
Span Character Format (In-Line)........ccooooeiiiii i, 14-49
Subtract Decimal FOrmat ..o 14-50
Subtract Decimal Format (Cleared)..........cooooiiiiiiii
e 14-51

TABLES
Title

Table No.

Page

1-1

Related DoCUmMENtation ......coooiiiiiiiiieee

1-8

2-1

Manufacturing Test

2-3

2-2

UART Test JUMPET c.ovniiii e

2-3
2-4
2-5

2-6
2-7

2-8
2-9
2-10
2-11

2-12
2-13

2-14
2-15

2-16
2-17

2-18

2-19

JUMPETS......ccooiiiiiiiiii

2-3
Field Service Test JUMPET ....ooovviiii e
2-4
Power-Up Mode Jumper Configurations ................ueeeeeiimmiiiiainaaaaaaaeaaaeaeeeeeeeeeeeeeeeen 2-4
Halt/Trap Jumper Configuration ..........ccocciiriiiiiiiiiiii
e, 2-5
On-Board Device Selection JUMPETS .......oooiviiiiiiiiiiiiiiiieie e
2-6
Diagnostic/Bootstrap Program Selection ...........ccccooviiiiiiiinniiiiniic, 2-7
Bootstrap Program SeleCtion .............uuiiiiiiiiiiiiiii
e
2-8
ROM (0r EPROM) JUMPETS ....coiiiiiiiiiiioe e
2-9
Console SLU Baud Rate Selection............ccvviiiieiiiiiiieee
e 2-9
Console SLU Character Format Jumpers.......ccoooeiiiiiiiiiiiii
e 2-10
Character Jumper Configurations ................uvviiiiiiiiiieiiii
e 2-10
Break-on-Halt Jumper Configurations.........ccoooeeiieieiiiiiiiiiiiii
e, 2-11
Second SLU Baud Rate SeleCtion..........cocooooiiiiiiiiiiiiii
e 2-11
Second SLU Character Format Jumpers .........coooooiiiiiiiie
e 2-12
Character Jumper Configurations ..........ccoooeiiiiiiiiiiiiie
e
e 2-12
Internal /External SLU Clock Jumper Configurations...........ccoccvevviiiiiiiicnnn. 2-13

Bus Grant Continuity JUMPETS .....uuiiiiiiiiiiiiiiiiie
e
e 2-13
Factory Jumper Configurations ............ooiiiiiiiiiieii
e, 2-14

X1V

TABLES (Cont)
Table No.
2-20
2-21

2-22
2-23

3-1

3-2

4-1

Ll»JLJJ N — — —
R
[\)b—tb-—iLL)[\)b——t

—_—

— — — — \D 00 00 00 G0 =1 NN\ L L L L B s
N O N
O S
S VCIN SR S
O

4-2

13-3

13-4
13-5

13-6
13-7

B-1
B-2
B-3
B-5

B-6

B-7
D-2
F-1

Title

Page

Bootstrap/Diagnostic Factory Switch Configurations..............ccccoooiii 2-16
SLU Baud Rate Factory Switch Configurations ............c.eovvoiiiiiiiriiiiiiii
e, 2-16
KDF11-BA Extended Address LInesS.........oooiiiiiiiiiiiiiiiie
e, 2-19
Console Power-Up Printout (or Display) ....ooooooiiiiiii 2-22
Console ODT CommandS ..........ouoiiiiiiiiiiiiie
e
e
e
3-3
Console ODT States and Valid Input Characters.........ccoooeiieiiiiiiiii 3-9
Summary of Signal Line FuncCtions .............ccooooiiiiiiiiiiiii e, 4-1
Data Transfer Bus CyCles ..o
4-3
Data Transfer Bus S1gnals ...
4-4
Position-Independent, Multilevel Device Requirements ...............cccooii
e, 4-19
Decoded General-Purpose OQUtPUL .......coooiiiiiiiiiiiiiiii
e 5-8
Service Logic Bits <<06,04:02,00>> .......oooiiiiiiiiiiii
e 5-17
Service Logic Bits <<T12:07,05,01 > ..o 5-17
F11 Chip Reset S1gnals.......coooiiiiiiiiiii
e, 5-18
Direct Addressing MoOdeS. ......ccoooiiiiiiiiiiii
e 6-11
Indirect Addressing MoOAES..........ooiiiiiiiiiii
e 6-12
PC Register Addressing MOAES ........oeeiieiieiiiiiieeieee e 6-12
INStruction SYMDOIS ....uuueiiiiii
7-11
Access Control Field Keys ...
e 8-6
PAR /PDR Address ASSIZNMENTS ........ccooiiiiiiiiiiiiiiiiiie i 8-9
Relating Virtual Address Ranges to PAR/PDR Sets.......cccccccciniiin 8-14
Processor Status Word ProteCtion ..o 8-17
FPS Re@iSter BItS. . o ovi i i i i i e
9-5
Register Address ASSIZNIMENTS......ccoeiieeiee ittt
ee e e
e e e 11-1
KDF11-BA LED DiSPlay....cooooiiiiii e 11-4
List of Error Halts. ..o
e 11-5
Line Clock Status Register Bit ASSIZNMENT .......oooiiiiiiiiiiiieiiiiiiiie e 12-1
Serial-Line Register AddreSSeS. ... iiiiiiiiiiiieiiiiiiie e 13-2
RCSRI1 and RCSR2 Bit ASSIZNMENTS ....uiiiiiiiiiiee e
e e 13-3
RBUF1 and RBUF2 Bit ASSIZNMENTS .....cooiiiiiiiiiiiiiiiiiiiiiie e 13-3
TCSR1 and TCSR2 Bit ASSIZNMENTS ......oovuiiiiiiiiiiiiiee
e
e e e 13-4
TBUF1 and TBUF2 Bit ASSIZNMENTS ....ccciiiiiiiiiiiiiiiiiieie
e ee e e
e e eee e 13-4
Console and Second SLU Interrupt VECIOrS......oooviiiiiiiieiiiiiiiiiiiiie
e 13-5
SLU Connector PIn FUNCLIONS .......uuuiiiiii
e, 13-5
KDF11-BA Common Microcode Cycle Times ..........ooevveeiiiiiiiiiiineeiiie e B-1
KDF11-BA Peripheral Microcode Cycle TImes ........ccoeeviiiiiiiiiiiiiiiiin B-2
MSVIT1-P Parity MEeIMOTY ...coovviiniiiiiiiie ettt
e B-2
SoUurce AdAress TIMMES ...ooooviiiiiiiei et B-2
Destination Address TIMES ........oooiiiiiiiiiiiiiiiie
e
e e e e e e e e e e eeeeeenenne, B-3
Basic (Fetch and Execute) Times ..o B-4
Jump INStruction TIMES .....oooviiiiiiiii
B-5
Backplane Pin Assignment Comparison (Rows A and B)........ccccvviviiiiiiiiiiiiinnne D-1
KDF11-BA Backplane Pin Assignment (Rows Cand D) ...............cci, D-2
Extended LSI-11 Bus Signal FUnCtions ... F-1

PREFACE

This guide is meant to familiarize you with the purpose and uses of the KDF11-BA Central Processor
Unit (CPU) module. Included are explanations of the features, options, capabilities, and technical characteristics of the module, as well as general reference data. Specifically, this guide presents:
e

Information needed to configure, install, and operate the CPU module in a computer system.

An explanation of the module’s configuration requirements and a definition of the factory
configuration.

The module’s hardware and software operating features.

A functional description of the module’s major logic elements (using block diagrams).

General reference information and the differences between the KDF11-BA CPU module and

previous LSI-11 CPU modules (Appendices A through F).

XVil

CHAPTER 1

SPECIFICATIONS

1.1

INTRODUCTION

The KDF11-BA is a quad-height PDP-11 CPU module (M8189). This module contains a central processor, memory management unit (MMU), a line frequency clock, a BDV11-compatible bootstrap and
diagnostic ROM, and two serial-line units. Three extra 40-pin sockets are provided for optional floatingpoint and commercial instruction sets. The central processor and memory management units are functionally compatible with the KDF11-AA CPU and MMU.

The KDF11-BA CPU supports up to 256K bytes of memory on a traditional LSI-11 bus backplane (18
address bits) or up to 4 megabytes of memory when the module is installed in an extended LSI-11 bus
backplane (H9276 or H9275). The extended LSI-11 bus backplane adds four address lines to the LSI11 bus to provide a 22-bit addressing capability when the KDF11-BA is used with the MSVI1I-P
(M8067) memory module. The extended LSI-11 bus will be referred to throughout this manual as the
LSI-11 bus except in those cases where a distinction must be made between it and the traditional LSI11 bus.

The central processor uses the LSI-11 bus or extended LSI-11 bus with 4-level interrupt bus protocol.
The KDF11-BA is compatible with existing LSI-11 processors and peripheral devices.

The LSI-11 bus is built based on LSI-technology requirements consistent with low-cost, high-performance and small-board-form factors. Low cost and high performance are realized, in part, through use of
multifunction lines such as the data/address lines (DALSs), which reduce the number of pins to the bus.
Other lines, such as the I/O page address decode line, eliminate hardware by removing the need for
identical page decoders on each interface module. A detailed description of the extended LSI-11 bus is
contained in Chapter 4.

The KDF11-BA is software-compatible with the PDP-11 family. A wide range of software is available,
including programming languages, diagnostic software, and operating systems. Note, however, that not
all PDP-11 family software uses the extended addressing capability (22 bits) of the KDF11-BA.
1.2

FEATURES

The KDF11-BA CPU module (M8189) has the following features.
KDF11-AA-Compatible CPU

Instruction set with over 400 instructions
4-level vectored interrupts

16-bit word or 8-bit byte addressable locations
Multiple general-purpose registers
Stack processing

Direct memory access (DMA)
Power-fail /autorestart hardware
18-bit ODT console emulator

1-1

KDF11-AA-Compatible Memory Management

18- or 22-bit address

Kernel and user modes only (no supervisor mode)

I-space only (no D-space)

Optional Floating-Point Instruction Set
Optional Commercial Instruction Set
On-Board Peripherals
Line frequency clock
BDV11-compatible boot and diagnostic
Console serial-line unit
Second serial-line unit

Extended LSI-11 Bus Interface (AB Rows)
1.3

SPECIFICATIONS

Identification

M8189

Size

Quad

Dimensions

26.6 cm X 22.8 cm (10.5in X 8.9 in)

Power Consumption

+5V = 5% at 6.4 A (maximum), 4.5 A (typical)

+12V = 5% at 0.7 A (maximum), 0.3 A (typical)
AC Bus Loads

2 unit loads

DC Bus Loads

1 unit load

Environmental
Storage

—40° C to 65° C (—40° F to 150° F) 10% to 90% relative humidity,
noncondensing

Operating

5° C to 60° C (41° F to 140° F) 10% to 90% relative humidity, noncondensing

Maximum outlet temperature rise of 5° C (9° F) above 60° C (140° F)

Derate maximum temperature by 1° C (1.8° F) for each 305 m (1000 ft)
above 2440 m (8000 ft).
Instruction Timing

Based on 75 ns intervals

(See Appendix B.)

1-2

5.7 us

Interrupt Latency

12.600 us, maximum (except EIS)
54.225 us, maximum (including EIS)

8.625 us (memory management off)

Interrupt Service

9.750 us (memory management on)

1.35 us, maximum

DMA Latency

NOTE

Interrupt and DMA latencies assume a KDF11-BA
with Memory Management Enabled and using
MSV11-P memory.

1.4

PROCESSOR HARDWARE

The KDF11-BA processor is implemented using three chips. Two MOS/LSI chips, data and control on
a single hybrid package, implement the basic processor. The memory management unit (MMU), the
,
third chip, provides a PDP-11/34 software-compatible memory management scheme.
The data chip (DC302) performs all arithmetic and logical functions, handles data and address transfers with the external world, and coordinates most interchip communication. The control chip (DC303)
does microprogram sequencing for PDP-11 instruction decoding and contains the control store ROM.
The data and control chips are contained in one 40-pin package. The MMU chip (DC304) contains the
registers for 18-bit or 22-bit memory addressing and also includes the FP11 floating-point registers and
accumulators. Optional floating-point requires the MMU chip. Data and control chips do not need the
MMU chip for 16-bit addressing.
1.4.1

General-Purpose Registers

The data chip contains nine 16-bit general-purpose registers that provide for a variety of functions.
Note, however, that only eight of these registers may be used at any given time. These registers can
serve as accumulators, index registers, autoincrement registers, autodecrement registers, or as stack
pointers for temporary storage of data. Arithmetic operations can be from one general register to another, from one memory location or device register to another, between memory locations, or between a
device register and a general register. Figure 1-1 identifies the general registers RO through R7.
GENERAL

REGISTERS

—
R1
R2

R3
R4

KERNEL

STACK POINTER

~ |isp)
R7

USER

STACK POINTER

| po)

PROGRAM COUNTER
MR-3635

Figure 1-1

General-Purpose Registers

1-3

Registers R6 and R7 are dedicated. The KDF11-BA contains two R6 registers which are selected by

the processor status word (PS) so that only one is accessible at any given time. R6 serves as the stack
pointer (SP) and contains the location (address) of the last entry in the stack. Register R7 serves as the
processor’s program counter (PC) and contains the address of the next instruction to be executed. Register R7 is normally used for addressing purposes only and not as an accumulator. Register operations
are internal to the processor and do not require bus cycles (except for instruction fetch); all memory
and peripheral device data transfers do require bus cycles, however, and longer execution time. Thus,
general registers used for processor operations result in faster execution times.
1.4.2

Bus Cycles

The bus cycles (with respect to the processor) are as follows.

DATI

Data word transfer input

DATO

Data word transfer output

Equivalent to read operation

Equivalent to write word
operation

DATOB

Data word transfer output

Equivalent to write byte
operation

DATIO

Data word transfer input

Equivalent to read /modify/

followed by word transfer

write word operation

output

DATIOB

Data word transfer input

Equivalent to read /modify/

followed by byte transfer

write byte operation

output

Every processor instruction requires one or more bus cycles. The first operation required is a DATI,

which fetches an instruction from the location addressed by the program counter (R7). If no more oper-

ands are referenced in memory or in an I /O device, no additional bus cycles are required for instruction
execution. If memory or a device is referenced, however, one or more additional bus cycles is required.
DMA operations may occur between individual bus cycles, since these operations do not change the
state of the processor.
Note the distinction between interrupts and DMA operations: interrupts, which may change the state of
the processor, can occur only between processor instructions, while a DMA operation can occur be-

tween bus cycles. For more details on bus operations refer to Chapter 4.

1.4.3

Addressing Memory and Peripherals

The KDF11-BA processor uses 16-bit data paths throughout. These data paths are also used to construct operand and instruction addresses. Octal notation is used to describe information on the data

paths.
A processor word is divided into a high byte and a low byte as shown in Figure 1-2. Word addresses are
always even-numbered. Byte addresses can be either even- or odd-numbered. Low bytes are stored at
even-numbered memory locations, high bytes at odd-numbered memory locations. Thus, it is convenient

to view the memory as shown in Figure 1-3.

1-4

LOW BYTE

HIGH BYTE
I

]

|
MR-3636

High and Low Bytes of a Processor Word

Figure 1-2

16-BIT WORD

8-BIT BYTE

BYTE

HIGH

LOW

000000

LOW

000000

HIGH

LOW

000002

HIGH

000001

HIGH

LOW

000004

LOW

000002

HIGH

000003

LOW

000004

MLM/ OR
MM

HIGH

LOW

017772

HIGH

017775

HIGH
HIGH

LOW
LOW

017774
017776

LOW
HIGH

017776
017777

BYTE ORGANIZATION

WORD ORGANIZATION

MR-3637

Figure 1-3

Word and Byte Addresses for First 4K Words of Memory

The full 16-bit data path allows a program to specify operand addresses (i.e., virtual addresses) anywhere within a 64K-byte range or 32K-word range. This virtual address range is fixed by the instruction
format and cannot be changed by the user.

For applications that require more than 32K words of physical addresses, such as multiprogramming
and/or timesharing applications, six additional addressing bits are available. These bits allow up to 2
megawords of memory to be physically addressed by the processor. This additional addressing capability is part of the standard memory management within the KDF11-BA architecture.
Memory Management

1.4.4

The memory management has the following three major features.

Two software modes that are useful for multiuser (timesharing) systems.

Extended memory addressing (greater than 32K words, up to 2 megawords) to allow more

than one program to reside in memory at the same time.

Memory protection for controlling user program access to system resources (e.g., memory,
1/0).

The first feature provides a kernel and user mode to allow efficient segmentation of memory for multiuser environments. Kernel mode is employed by the operating system to control system resources and
allows full privileges of the entire system. The user mode is employed for executing a user program and
restricts processor privileges. In user mode, the processor is inhibited from executing certain instructions (e.g., the HALT instruction cannot be executed).

1-5

The second feature provides a full 22-bit memory addressing capability. Mapping registers are used to

map (relocate) the 32K-word virtual address space anywhere in the 2 megaword physical address space.
The third feature allows restricted access to virtual memory pages (a page is defined as 4K words long).
This permits the operating system software rather than the user program to control system resources in
a multiprogramming environment. This feature ensures that no user operating in user mode can cause a

failure of the entire system. Chapter 8 contains a complete discussion of memory management.
1.4.5

Processor Status Word (PS)

The processor status word (PS) is in the data chip and contains information on the current status of the
processor. As shown in Figure 1-4, this includes: the condition codes describing the arithmetic or logical
results of the last instruction, a trace bit that forces a trap at the end of instruction execution (used
during program debug), the current processor priority, an indicator of the previous memory management mode, and an indicator of the current memory management mode. The processor status word is

located at physical address 17777776.

PRIORTY

“

]

RESERVED
Y

LEVEL
|

TRACE —j

[}

NEGATIVE

PREVIOUS MEMORY
MANAGEMENT MODE

ZERO

OVERFLOW

CURRENT MEMORY

CARRY

MANAGEMENT MODE
SUSPENDED
INSTRUCTION

MR-3638

Figure 1-4
1.4.5.1

Processor Status Word (PS) Format

Condition Codes (PS bits <<3:0>) — The condition codes contain information on the result of

the last CPU operation. The bits are set after execution of all arithmetic or logical single-operand or

double-operand instructions. The bits are set as follows.
N = 1

if the result was negative.

Z =1

if the result was O.

V =1

if the operation resulted in an arithmetic overflow.

C = 1

if the operation resulted in a carry from the MSB (most significant bit) or a 1 was shifted

from the MSB or LSB (least significant bit).
1.4.5.2

Trace Bit (PS bit <4>) — The trace bit is used in debugging programs since it allows instruc-

tions to be single-stepped.
1.4.5.3

Priority Level (PS bits <<7:5>) - These bits are used by the software to determine which

interrupts will be processed.

1-6

Octal Value of PS<<7:5>

Interrupt Level Acknowledged*

7
6
5
4
3
2
1
0

None
7,
7, 6,
7,6, 5,
7,6,5, 4
7,6,5,4
7,6,5, 4
7,6,5,4

*Higher levels acknowledged first.

1.4.5.4 Suspended Instruction (SI) (PS bit <<8>) — This bit is reserved for use by DIGITAL and is
intended for options such as the commercial instruction set (CIS). This bit is read/write and has no

protection mechanism. Refer to Paragraph 8.5.3.2 for more details.

1.4.5.5 Previous Mode (PS bits <13:12>) — These bits are used with memory management to indicate the last memory management mode. They are read /write bits and are present even without the

memory management option.

1.4.5.6 Current Mode (PS bits <15:14>) — These bits indicate the present memory management
mode. They are read/write and are present even without the memory management option.
1.5

INSTRUCTION SET

The KDF11-BA instruction set provides over 400 powerful instructions. As a comparison with other
instruction sets, consider that most other (for example, accumulator-oriented) 16-bit processors require
three separate instructions to execute a common double-operand instruction (e.g., ADD). The following
is the conventional approach to a simple operation.

LDA A

Load contents of memory location A into accumulator.

ADD B

Add contents of memory location B to accumulator.

STA B

Store result at location B.

By contrast, the KDF11-BA can fetch both operands, execute, and store the result in one instruction.
ADD A, B

Add contents of location A to location B; store result at location B.

This greater efficiency not only saves memory space and time, but also improves processor speed since
fewer instruction fetches are required.

Another major advantage of the KDF11-BA instruction set is the absence of special-purpose input/output instructions. Special I/O instructions are unnecessary since peripheral device registers are
accessed in the same way as main memory locations. This approach to handling I/O devices allows the
normal instruction set to be used to test and/or manipulate the various 1/O device register bits. For
example, a COMPARE instruction can test status bits directly in the I/O device register without bringing them into memory or disturbing any of the general registers; control bits can be set, cleared, or
shifted as is most convenient; and peripheral data can be arithmetically or logically altered when received at the device register and before being stored in memory. Refer to Chapter 7 for a complete

description of the instruction set and its utilization.

1-7

Addressing Modes — Much of the flexibility of the KDF11-BA is derived from its wide range of addressing capabilities. Addressing modes include sequential forward or backward addressing, address indexing, indirect addressing, absolute 16-bit word and 8-bit byte addressing, and stack addressing. Variable-length instruction formatting allows a minimum number of words to be used for each addressing
mode. The result is efficient use of program storage space. For more details on addressing modes refer
to Chapter 6.

1.6 FLOATING-POINT OPTION
Forty-six floating-point instructions are available as a microcode option (KEF11-AA) on the KDF11BA processor. These instructions supplement the integer arithmetic instructions (e.g., MUL, DIV, etc.)
in the basic instruction set. The floating-point option allows floating-point operations to be executed
faster than equivalent software routines and provides for both single-precision (32-bit) and double-precision (64-bit) operands. This option also conserves memory space, since floating-point routines are executed in microcode instead of software. This option implements the same floating-point instruction set
found on the PDP-11/34, PDP-11/60, and PDP-11/70. For a complete description refer to Chapter 9.

1.7 COMMERCIAL INSTRUCTION SET OPTION
The commercial instruction set (CIS) is a microcode option (KEF11-BB) that adds character string
instructions to the basic PDP-11 instruction set. The character string operations conveniently implement most of the common, as well as time consuming functions that are encountered in commercial
data and text processing applications. The microcode option is completely compatible with the standard
PDP-11 commercial instruction set. The CIS microcode resides in six MOS /LSI chips mounted on a
single double-width 40-pin carrier.

1.8 MEMORIES AND PERIPHERALS
Digital Equipment Corporation provides a wide range of memories and peripherals to allow maximum
flexibility in configuring systems. A detailed list and descriptions can be found in the Microcomputer
and Memories Handbook and the Microcomputer Interfaces Handbook.
1.9 RELATED DOCUMENTS
Table 1-1 lists documents containing additional information of possible interest to KDF11-BA processor
uscers.

Table 1-1

Related Documentation

Title

Document Number

Microcomputer Interfaces Handbook
Microcomputer and Memories Handbook
PDP-11 Processor Handbook
PDP-11 Software Handbook
PDP-11/23B Mounting Box Technical Manual
PDP-11/23B User’s Guide
KDF11-B Field Maintenance Print Set

EB-20175-20/80
EB-18451-20/80
EB-09402-20/81
EB-08687-20/80
EK-1123B-TM-001
EK-1123B-UG-001
MP-01236

These documents can be ordered from:
Digital Equipment Corporation
Printing and Circulation Services
444 Whitney Street
Northboro, MA 01532

Attention:

~ Communications Services (NR2/M15)
Customer Services Section

1-8

CHAPTER 2
INSTALLATION

INTRODUCTION

2.1

This chapter discusses the basic considerations and requirements for configuring and installing the
KDF11-BA processor in LSI-11 systems using an extended LSI-11 bus backplane as well as existing
LSI-11 systems using one of the LSI-11 bus backplanes. The items that must be considered fall into
four basic categories.

Configuration of jumpers and switches for operation of user-selectable features.

Selection of an LSI-11 bus-compatible backplane and mounting box.

Selection of LSI-11 bus-compatible options and accessories.

Knowledge of system differences if replacing an LSI-11, LSI-11/2 or LSI-11 /23 (KDF11-

AA) processor with an LSI-11/23B (KDF11-BA) processor.

See Paragraph 1.9 for information on ordering documents referred to in this chapter.
2.2

JUMPER AND SWITCH CONFIGURATION

The KDF11-BA contains two DIP (dual in-line package) switch units (E102 and E114) and a number
of jumpers that allow the user to select the module features desired. The location of the switch units
and jumpers is shown in Figure 2-1. The boot/diagnostic switch unit (E102) consists of eight switches
that let the user select boot and diagnostic programs. The second switch unit (E114) selects the baud
rate for the console SLU (serial-line unit) and the second SLU. The module contains both wirewrap
jumper stakes and soldered-in jumpers. The jumpers are divided into the following functional groups.
Test jumpers

U R W

CPU (central processor unit) option jumpers

2.2.1

Device selection jumpers

Boot and diagnostic ROM jumpers
SLU character format jumpers
Internal/external SLU clock jumpers
Bus grant continuity jumpers
_

Test Jumpers

The test jumpers described in the following paragraphs are used for tests performed by manufacturing
and field service.

2-1

lsgerozr]_ :—as?ws_w_m

_9gro _ver£E-ro

13X40S vL13 Zol3

oEr

anvg¢l

2-2

ZM LM

|oE!vla]

OYd3/IWOY
1IN3ID0S

G/3

9/3

IHZ)13(318A08:Gl
/T

(YVN-OLIL43dMO)

LEro

13S

ZEro

LL3

Liro

NTVOIOLHO_INYWLSONDI8(LN-O3LI4LS3dMO)

ger

8/3

O1LSONDVIQ

8rrS-"w

abST3HLDOLINMNSO1D—1OSL‘2g'vg'rZ'ASINvVer —
:S3LON

gr
vr

z|9Z130:£0S8pzZpNi8s&z|8rN—oSC1IL3]JvalvqoLz-r14-AyCEER‘EDroom0dwLnof]‘LYooCEuTIEmNTEg1p.ue'onsouger(qAerdsi(qs[uoned|oTLON‘03103INO

RERRSpr ¥r EYr ZbT Lol Al

§N3'M4LOI—HV¢SS".NONILOI.SO,d

AVdsIa

6 8r

6Lr

Lifo

vi3

(NdO)

o{—oJ

—

2[I-n3C1]

2.2.1.1 Manufacturing Test Jumpers — Three wirewrap jumpers are provided for manufacturing tests. |

The jumpers are removed while the tests are performed and must be installed for normal operation.
Table 2-1 lists the manufacturing test jumpers.
Table 2-1

Manufacturing Test Jumpers

Jumper

From

|To

Function

Connects the system oscillator to the CPU and LSI-11 bus timing circuits.

Connects the PHASE signal to the input of the F11 chip clock drivers.

J20

J21

Connects the baud rate crystal oscillator to the SLU baud rate generator and the —12
V charge pump circuit.

2.2.1.2 UART Test Jumper — For normal operation the bus initialize signal (BINIT) will clear the
UARTS on the console and second SLUs. If a character is in either of the UARTS’ buffers and a RESET instruction is executed before the character is read, the character is lost. The three jumper stakes
(J33-J35) allow the console UART to be configured so it will be cleared by power-up and system restart only. Currently this feature is not used by DIGITAL in manufacturing or field service testing.

Table 2-2 describes the jumper configuration for the UART test jumper.
CAUTION

Standard field service SLU diagnostics will FAIL if
the reset disabled configuration is selected. Normal
system and diagnostic operation requires that this
feature not be selected.

Table 2-2

Jumper
From

J35

J34

J33

J34

UART Test Jumper

Reset
Disabled

Normal
Operation

Connects LINITF(1) H to the

Connects DCOKC2B L to the console

Function

console SLU UART reset input.

SLU UART reset input.

R = removed; | = installed.

2.2.1.3 Field Service Test Jumper — This jumper allows field service personnel to check out the console
terminal and its cable independently of the processor. When the jumper is installed in the test configuration, the serial input from the console is looped through the console SLU connector (J1) back to
the console. Table 2-3 describes the jumper configuration for normal operation and field service testing.

2-3

Table 2-3

Jumper
From

Function

J27

J26

J25

J26

Field Service Test Jumper

Field
Service

Normal
Operation

Connects the output of the
console serial-line driver to
the console serial-output line.

Connects the serial-line input
from the console connector to
the console connector serial-line

output.
R = removed; I = installed.

2.2.2

CPU Option Jumpers
Four wirewrap stakes provide user-selectable features associated with the operation of the CPU. The
ground stake can be connected to any combination of the other three stakes to select the available features. Two power-up mode stakes select one of four power-up modes. The halt/trap stake selects the
halt/trap option.
2.2.2.1
Power-Up Mode Selection — The four power-up modes are selected by installing or removing
in various combinations the wirewrap jumpers between jumper stakes J17 and J19 and the ground stake
(J18). The jumper configurations for the modes are listed in Table 2-4.

Only the power-up mode is affected, not the power-down sequence. The following paragraphs describe
the sequence of events after executing common power-up for each of the four modes. The state of bus
signal BHALT L is significant in power-up mode operation.
Table 2-4

Power-Up Mode Jumper Configurations

Jumper

J18 to J19

J18 to J17

Mode

Name

PC@24, PS@26

Console ODT

Bootstrap

Extended microcode

R = removed; I = installed.

Power-Up Mode 0 — This mode causes the microcode to fetch the contents of memory locations 24g and
264 and loads their contents into the PC and PS, respectively. The microcode then examines BHALT L.
If BHALT L is asserted, the processor enters console ODT mode; if it is not, the processor begins program execution by fetching an instruction from the location pointed to by the PC. This mode is useful
when power-fail /auto-restart capability is desired, but is valid only when used with nonvolatile memory.
Power-Up Mode 1 - This mode causes the processor to enter console ODT (on-line debugging technique) mode immediately after power-up, regardless of the state of any service signals. This mode is
useful in a program development or hardware debugging environment — the user has immediate control
over the system after power-up.

2-4

Power-Up Mode 2 — This mode causes the processor to generate internally a 16-bit bootstrap start address of 1730003 (the conventional start address for DIGITAL systems). This address is loaded into the
PC. The processor sets the PS to 3403 (PS<<7:5> = 7) to inhibit interrupts before the processor 1s
ready for them. If BHALT L is asserted, the processor enters console ODT mode; if it is not, the processor begins execution by fetching an instruction from the location pointed to by the PC. This mode is
useful for turn-key applications where the system automatically begins operation without operator intervention.

Power-Up Mode 3 ~ This mode causes the microcode to jump to optional control chip number 37g,
location 76g, and begin microcode execution. This mode is reserved for future microcode expansion by
DIGITAL and is not recommended for customer usage. If it is erroneously selected, the processor will
treat it as a reserved instruction trap to location 10g.

2.2.2.2 Halt/Trap Option — If the processor is in kernel mode and decodes a HALT instruction,
BPOK H is tested. If BPOK H is negated, the processor will continue to test for BPOK H. The processor will perform a normal power-up sequence if BPOK H becomes asserted sometime later. If BPOK H
is asserted after the HALT instruction decode, the halt/trap jumper (J16) is tested. If the jumper 1s
removed, the processor enters console ODT mode. If the jumper is installed, a trap to location 10g will
OCCUTr.

NOTE

In user mode a HALT instruction execution will always result in a trap to location 10g.

This feature is intended for situations where recovery from erroneous HALT instructions is desirable,
such as unattended operation. Table 2-5 lists the halt/trap jumper functions for kernel and user processor modes.

Table 2-5
Jumper

Processor

Halt/Trap Jumper Configuration

J18 to J16

Mode

Function

Kernel

Processor enters console ODT microcode when it executes a HALT in-

Kernel

Processor traps to location 10g when it executes a HALT instruction.

User

HALT instruction decode results in a trap to location 10g regardless of

struction.

the status of the halt/trap jumper.

R = removed; I = installed; X = “Don’t care.”

2.2.3

On-Board Device Selection Jumpers

Six wirewrap stakes on the KDF11-BA module are used to select which on-board peripheral devices are
to be enabled or disabled. The ground stake can be connected to any combination of the other five
stakes to obtain the desired configuration. The jumper functions are described in Table 2-6.

2-5

Table 2-6

On-Board Device Selection Jumpers

Stake
Stake
Number | Name

Function

J10

Ground

This wirewrap stake provides a ground source for the other five wirewrap

J15

BDK DISJ L | When grounded, this signal disables the boot/diagnostic registers, the

J11

LTC ENBJ L | When grounded, this signal forces the line clock interrupt enable flip-flop to

stakes in this group.

boot/diagnostic ROMs, and the line clock register.

be set and allows the LSI-11 bus BEVNT signal to request program interrupts unconditionally.

J14

DL1 DISJ L | When grounded, this signal disables the console serial-line registers. When
ungrounded, the device and vector addresses for the console SLU are the
following.

Device Addresses

Interrupt Vectors

RCSR

17777560

Receiver

060

RBUF

17777562

Transmitter

064

XCSR
XBUF

17777564
17777566

NOTE

If DLL1 DISJ L is grounded, the break-on-halt feature must also be disabled
(Paragraph 2.2.5.3).

J13

DL2 DISJ L | When grounded, this signal disables the second serial-line registers. When
ungrounded, the device and vector addresses for the second SLU are determined by the status of the DL2 ADRJ L jumper.

J12

DL2 ADRJ L | When DL2 ADRJ L is ungrounded, the second SLU device and its vector
addresses are as follows.
Device Addresses

Interrupt Vectors

RCSR
RBUF
XCSR
XBUF

Receiver
Transmitter

17776500
17776502
17776504
17776506

300
304

When DL2 ADRIJ L is grounded, the device and vector addresses are as
follows.

Device Addresses

Interrupt Vectors

RCSR

17776540

Receiver

340

RBUF

17776542

Transmitter

344

XCSR

17776544
17776546

XBUF

2-6

Bootstrap/Diagnostic Switches and Jumpers

2.2.4

A 16-pin DIP switch pack (E102) and two jumpers on the KDF11-BA module provide switch-selectable
bootstrap and diagnostic programs for hard disks and diskettes or the customer’s own bootstrap program. The KDF11-BA will have BDV11 functionality only if the BDV11 2K X 8 diagnostic/bootstrap
ROMs or EPROMs containing DIGITAL programs are installed in sockets E126 and E127. The
switch and jumper functions are described in Paragraphs 2.2.4.1 and 2.2.4.2 and their locations are
shown in Figure 2-1.

2.2.4.1

Bootstrap/Diagnostic Configuration Switches — Boot and diagnostic configuration register bits

—<07:00> reflect the status of the eight switches of the S1 switch pack (E102). Switches S1-1 through
S1-4 are used to select a diagnostic and/or a bootstrap program. Switches S1-5 through S1-8 are used
in conjunction with switches S1-3 and S1-4 to select the specific bootstrap program desired. The switch
configurations when using the BDV11 2K X 8 diagnostic bootstrap ROMs (DIGITAL) are listed in

Tables 2-7 and 2-8.

Table 2-7
CDAL | Switch

Switch

Diagnostic/Bootstrap Program Selection
Function

Bit

Number

Position

S1-1

Execute CPU diagnostic upon power-up or restart.

S1-2

Execute memory diagnostic upon power-up or restart.

S1-3

DECnet boot (S1-4 through S1-7 are argumentsTM).

S1-4

Console test and dialogue (S1-3 Off).

S1-4

Off

;F)li}i{)n-key boot dispatched by S1-5 through S1-8 configuration (S1-3

* DECnet boot arguments are:
Switch Positions

S1-4

S1-5

S1-6

S1-7

DUVI11

DLVI1I1-E

Off

DLVI11-F

Off

Boot Devicet

+ DLV11-E CSR = 17775610
DLV11-FCSR = 17776500

DUVI11 CSR = 17760040 if there are no devices from 17760010 to 17760036

X = “Don’t care.”

2-7

Table 2-8

Bootstrap Program Selection

Device

Switches:

S1-5

S1-6

S1-7

S1-8

Program

Mnemonic*

CDAL Bit:

Selected

DKn;n < 8%

Off

RKO5 boot

DLn;n < 4

Off

RLO1 or RLO2 boot

DDn;n < 2

Off

TUS8 (SLU) at 776500
boot

DXn;n < 2

Ooff

DYn;n < 2

Off

RX01 boot

Off

RX02 boot

*n = unit number

All bootstrap programs other than the DECnet boots above are controlled by the bit patterns in switches S1-5 through S1-8. The bit patterns are described in Table 2-8. If the console test is selected (S1-4

On, S1-3 Off), the bootstrap program is controlled by a device mnemonic and unit number supplied by
the console operator. These device mnemonics are also described in Table 2-8.
The console test prompts the operator with
XXXX.KW

START?
where XXXX is the decimal multiple of 1024 words of RAM found in the system when sized from O up
in consecutive 1024-word increments. The first word of each 1024-word segment is read and written

back to itself.

The console operator responses are a 2-character device mnemonic with a 1-digit octal unit number or
one of two special single-character mnemonics. If no 1-digit unit number is specified, the unit 0 is se-

lected. The response must be followed by a <<CR> (carriage return). The special single-character
mnemonics are
Y

Use switch settings to determine boot device

HALT — enter ODT microcode

2.2.4.2

Bootstrap/Diagnostic ROM Jumpers — Two 24-pin sockets (E126 and E127) are provided for

the installation of 2K X 8 ROMs or EPROMs.-When EPROMs are inserted into the two ROM sockets, +5 V must be applied to pin 21 of each socket. For all other ROMs used in this option, ROM
address bit 13 (BTRA 13 H) must be applied to pin 21. This pin is a chip select input for 2K ROMs.
Table 2-9 describes the jumper configurations when using ROMs or EPROMs. Figure 2-1 shows the
location of jumper stakes J22, J23 and J24.

2-8

Table 2-9
Jumper

ROM (or EPROM) Jumpers

Memory Type

ROM

EPROM | Function

J23

Connects BTRA 13 H to pin 21 of the two ROM sockets.

J23

Connects +35 V to pin 21 of the two ROM sockets.

From

J24
J22

I = installed; R = removed.

2.2.5

Console SLU Switch and Jumper Configurations

Four switches of a 16-pin DIP switch pack (E114) and four jumpers provide user-selectable features
associated with the operation of the console serial-line unit. The switch and jumper functions are described in Paragraphs 2.2.5.1 through 2.2.5.3 and Paragraph 2.2.7.

2251 Console SLU Baud Rates — Switches 1—4 of the S2 switch pack (E114) select 1 of 16 possible
STL.U baud rates if the internal baud rate generator is used as the clock source. If the KDF11-BA is
configured to operate the SLU with an external clock, the positions of these switches are meaningless.
Paragraph 2.2.7 describes the jumper configuration for internal /external baud rate clock selection.
The SLU transmits and receives at the selected baud rate. Split baud operation 1s not provided. The
switch configuration for selecting any one of the available baud rates is described in Table 2-10.
Table 2-10
Switch Position

Console SLU Baud Rate Selection

S2-4

S2-3

S2-2

S2-1

Baud Rate

On
On
On
On
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off

On
On
On
On
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
Off

On
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
Off
Off

On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200

2-9

2.2.5.2

Console SLU Character Formats — Five wirewrap stakes are used to select options for estab-

lishing the console SLU character format. The ground stake can be connected to any combination of
the other four stakes to configure the character format for the following options.
One or two stop bits
Seven data bits plus parity

Eight data bits without parity
Odd or even parity
The jumper stake functions are described in Table 2-11 and the jumper configurations are described in

Table 2-12.

Table 2-11

Stake

Console SLLU Character Format Jumpers

Stake

Number | Name

Function

J38

This wirewrap stake provides a ground source for the other four wirewrap

Ground

stakes in this group.

J39

'DL1 CH7J L

|When grounded, this signal causes the UART to transmit and receive 7-bit
characters. Otherwise, the UART is formatted for 8-bit characters.

J37

DL1 ST1J L

|When grounded, this signal causes the UART to transmit and receive one

stop bit. Otherwise, it is formatted for two stop bits.

J36

DL1 PARJ L |When grounded, this signal enables UART parity generation and checking.

Otherwise, parity is disabled.

J40

DL1 ODDJ L|When DL1 PARJ L and DL1 ODDJ L are both grounded, odd parity is selected. If only DLL1 PARJ L is grounded, even parity is selected.

Table 2-12

Character Jumper Configurations

Jumper
From

J39

To J38

IN
OuT

J37

J36*

J40

Character Format Option

7-bit characters
|

OUT
IN

8-bit characters

Two stop bits
One stop bit

Parity check enabled

ouT

Parity check disabled

Odd parity if J36 is in.

ouT

Even parity if J36 is in.

NOTE: If 8-bit characters (J39 OUT) are selected, parity check
must be disabled (J36 OUT).

2-10

2.2.5.3 Break-on-Halt Jumpers — Two jumpers enable and disable the break-on-halt feature. If this
feature is enabled, the detection of a break condition by the console UART causes the processor to halt
and enter the on-line debugging technique (ODT) microcode. If this feature 1s disabled, there is no
response to the break condition. Table 2-13 lists the jumper configurations for selecting the break-onhalt feature.

Table 2-13

Break-on-Halt Jumper Configuration

Function

Break Feature
Disabled
Enabled

Connects ground to RQ HLT H.

Connects DLL1 FE H to RQ HLT H.

Jumper
From

R = removed; I = installed.
J3 = DLI FEH
J4 = RQ HLTH
J5 = Ground

2.2.6

Second SLU Switch and Jumper Configurations

The second SLU is configured in the same manner as the console SLU except that a different set of
switches and jumpers are used to select the available SLU features. The switch and jumper functions
for the second SLU are described in Paragraphs 2.2.6.1 and 2.2.6.2.

22.6.1 Second SLU Baud Rates — Switches 5 through 8 of the S2 switch pack (E114) select 1 of 16
baud rates for the second SLU, if the internal baud rate generator is used as the clock source. The
second SLU will transmit and receive at the same selected baud rate. The switch configurations for
selecting any of the available baud rates are listed in Table 2-14.
Table 2-14
Switch Position

Second SLU Baud Rate Selection

S2-8

S2-7

S2-6

S2-5

Baud Rate

On
On
On
On
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off

On
On
On
On
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
Off

On
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On

On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800

On
Off
Off

2-11

Off
On
Off

7200
9600
19200

2.2.6.2

Second SLU Character Formats — Five wirewrap stakes are used to select options for estab-

lishing the second SLU character format. The ground stake can be connected to any combination of the
other four stakes to configure the character format for the following options.
One or two stop bits

Seven data bits plus parity
Eight data bits without parity
Odd or even parity
The jumper stake functions are described in Table 2-15 and the jumper configurations are listed in
Table 2-16.
Table 2-15

Stake

Second SLU Character Format Jumpers

Stake

Number | Name

Function

J30

This wirewrap stake provides a ground source for the other four wirewrap

Ground

stakes in this group.
J31

DL2 CH7J L

|When grounded, this signal causes the UART to transmit and receive 7-bit

characters. Otherwise, the UART is formatted for 8-bit characters.

J29

DL2 ST1J L

|When grounded, this signal causes the UART to transmit and receive one
stop bit. Otherwise, it is formatted for two stop bits.

J28

DL2 PARJ L |When grounded, this signal enables UART parity generation and checking.

Otherwise, parity is disabled.
J32

DL2 ODDJ L|When DL2 PARJ L and DL2 ODDJ L are both grounded, odd parity is se-

lected. If only DL2 PARJ L is grounded, even parity is selected.

Table 2-16

Character Jumper Configurations

Jumper

From
J31

J29

J28

To J30
IN

7-bit characters

ouT

8-bit characters

OouT

Two stop bits

One stop bit

Parity check enabled
Parity check disabled

ouT
J32

Character Format Option

Odd parity if J28 is in.

OouT

Even parity if J28 is in.

‘

2.2.7

Internal/External SLU Clock Jumpers

Two sets of jumpers are provided to select an internal or external clock for the console SLU and the
second SLU. If the internal clock jumpers are installed, the SLU clocks are obtained from the internal
baud rate generator. When the external clock jumpers are installed, external clocks are routed to the
SLUs through pin 1 of the J1 and J2 SLU connectors. Table 2-17 lists the internal/external SLU clock

jumper configurations.

Table 2-17

Internal/External SLU Clock Jumper Configurations

Jumper
From

Function

Selected Clock
External
Internal

J43

J42

Connects internal baud rate

J41

J42

Connects external clOck to

J46

J45

Connects internal baud rate

J44

J45

Connects external clock to

generator to the console SLU
UART. (Normal configuration)

the console SLU UART.

generator to the second SLU
UART. (Normal configuration)

the second SLU UART.

R = removed; I = installed.

2.2.8

Bus Grant Continuity Jumpers

Two jumpers must be installed when the KDF11-BA is used in an LSI-11 /LSI-11 bus backplane. An
LSI-11/LSI-11 bus backplane (e.g., an H9275 or H9270) is one that carries the LSI-11 bus signals on
backplane rows C and D as well as rows A and B. The jumpers provide continuity for the interrupt
acknowledge (BIAK) and direct memory access grant (BDMG) LSI-11 bus signals. The jumpers are
described in Table 2-18.

Table 2-18

Bus Grant Continuity Jumpers

Jumper* | Function

Connects backplane pins CM2 and CN2, providing continuity for BIAK L.

Connects backplane pins CR2 and CS2, providing continuity for BDMG L.

*Must be installed when the KDF11-BA is used in an LSI-11/LSI-11 bus backplane; otherwise, the
jumper installation is optional.

NOTE

If the KDF11-BA is installed in an LSI-11/CD
backplane (H9273 or H9276) and the W1 and W2
jumpers are installed, pin CM1 is shorted to CNI1
and pin CR1 is shorted to CS1 on slot 2.

2-13

2.3

FACTORY SWITCH AND JUMPER CONFIGURATIONS

Users may reconfigure the module jumpers and switches to select the KDF11-BA options required for

the particular system application. All switches and all jumpers except those jumpers reserved for manu-

facturing and field service testing may be reconfigured. Therefore, the factory configuration as shipped
is described below to assist users in determining the jumper and switch changes that are required to
select the module options for their systems. Table 2-19 lists the factory jumper configurations. Tables 2-

20 and 2-21 list the bootstrap/diagnostic switch and SLU baud rate switch configurations, respectively.
Table 2-19

Jumper
From

Factory

Jumper Configurations

Jumper
To

State

Function

The manufacturing and field service test jumpers are described below

in Paragraph 2.2.1.

Master clock; enables internal oscillator.

[

Phase; connects signal to F11 chip clock drivers.

J20

J21

XTAL; connects baud rate oscillator.

J35

J34

LINITF (1) H; connects reset to console UART.

J33

J34

Installed reset disabled test feature (only after removing jumper

J35-J34).
J27

J26

J25

J26

| R

Connects console SLU serial output to connector J1.
Installed for field service wraparound testing (only after removing
jumper J27-J26).

The CPU option jumpers are described below in Paragraph 2.2.2.
J19

J18

J17

J18

Power-up mode 2 (jumper J19-J18

installed; jumper J17-J18 removed)
causes the processor to begin executing the bootstrap code at start

address 173000.
J16

J18

Processor enters console ODT microcode when it executes a kernal
mode HALT instruction.

The on-board device selection jumpers are described in Paragraph
2.2.3.

J11

JIO

| R

LTC ENJ L. BEVENT can request interrupts only if the processor
program has set bit 6 of the line clock register (17777546).
The second SLU is enabled with an RCSR address of 17776500

J12

JIO

| R

J13

JIO

J14

J10

and interrupt vector addresses of 300 and 304.

The console SLU ié enabled.

R = removed; I = installed.

2-14

Table 2-19
Jumper

Factory Jumper Configurations (Cont)

Jumper

From

State

Function

J15

J10

The BDV ROMs and registers, as well as the line clock register, are
enabled.

The boot and diagnostic ROM jumpers are described in Paragraph
2.2.4.2.

J22

J23

J24

J23

NOTE: When ROMs are used, jumper J22-J23 is installed and jumper
J24-J23 is removed.

NOTE: When EPROMs are used, jumper J22-J23 is removed and

jumper J24-J23 is installed.

The console

SLU character formats are described in Paragraph

2.2.5.2.

Console SLU parity check is disabled.

J36

J38 | R

J37

J38

Console SLU character contains one stop bit.

J39

J38

Console SLU character contains eight bits.

J40

J38 | R

No effect; console parity already disabled.
The break-on-halt jumpers are described in Paragraph 2.2.5.3.

J3
J5

J4
J4

R
I

Break-on-halt feature is disabled. The break key on the console SLU
does not halt the processor. This feature may be enabled by removing

jumper J5-J4 and then installing jumper J3-J4.

The second SLU character formats are described in Paragraph 2.2.6.2.

Second SLU parity check is disabled.

J28

J30

J29

J30 | I

J31

J30

Second SLU character contains eight bits.

J32

J30

No effect; second SLU parity already disabled.

Second SLU character contains one stop bit.

The internal/external SLU clock jumpers are described in Paragraph
2.2.7.

J41
J43

R
J42
J42 | 1

The on-board baud rate generator is connected to the console SLU.
The external clock input from connector J1 is disabled.

R = removed; I = installed.

2-15

Table 2-19

Factory Jumper Configurations (Cont)

Jumper
From

Jumper
State

Function

J44
J46

J45
J45

R
I

The on-board baud rate generator is connected to the second SLU.
The external clock input from connector J2 is disabled.
The bus grant continuity jumpers are described in Paragraph 2.2.8.

\VA!

Provides bus grant continuity for the BIAK signal.

Provides bus grant continuity for the BDMG signal.

R = removed; I = installed.

Table 2-20

Bootstrap/Diagnostic Factory Switch Configurations

Switch S1 (E102)

Number

Position

Function*

1
2
3
4

On
On
Off
On

Execute CPU diagnostic
Execute memory diagnostic
DECnet boot disabled
Console test and dialogue

5
6

Off
Off

=
—

RLO1/RLO2 bootstrap program

Off

—

*With the switch configurations shown, the KDF11-BA, upon power-up or

restart, will execute the CPU diagnostic, the memory diagnostic, and then
enter the console test. If the operator wishes to terminate the memory diagnostic and immediately enter the console test, control/C must be entered on
the console terminal.

Table 2-21
Switch S2 (E114)
Number | Position

2
3
4

Off
Off
Off

6
7
8

Off
Off
Off

SLU Baud Rate Factory Switch Configurations

Function

Console SLU set for 9600 baud per Table 2-10.

Second SLU set for 9600 baud per Table 2-14.

oo=8=STe=STo'So=>NOmioT=Tet=°OxF®,V©
- - - =D oo oz ) N\TR=2

82%—@eN,blRe-eAwy0l©flwS‘©mvu)/©wTuMR<OOyOA=WoiO-Q©=U,J,sfiQf.=o=OAooHr=OeVN\8T,I0Ne'MO”o/=!y\Q»=0ToSAVO/=fl0iwSTW<H3AON-SQ.WMfl%SltoBSo=yt8e,N.eLeDAN/MO/H)O>HluOiS.«.WMUoOOA.iWtVWyMNAWQH=PS"CMsW.VUe=)»o|/EO.TON8O—Q-TA°=YQOOW\_Uf©oaOANMMV0R}Q,Mio=CEO"

j\flMGoM.WwIOoe=,ST\eNiyoWm\R,Mmn/eu0wuMv/OENOOHMVHEAW,IOONVW7OOySh\.,OU&SdHOM.,-W\U/(TQMn/N/uwuBoON=NoPe\>T./,OMUMO/f\lOOW/VMO.g.OUo\A/IHW\Ola\I—-=OWoWnDA|m\R/O\o.=M.f"l03f/,CWnM.EWwHvOS=onuOfHl\—.mlfIHiUfoOl/h«O/N/.H:lt.OWA|US\//WuON.\}Wo)A.oA.‘#_PO.WMI‘O\n]
(pin) identification system. Figure 2-2 shows the contact finger identification for a typical quad-height
module. The LSI-11 bus signals are carried on rows A and B. Each row contains 36 lines (the component and solder sides of the circuit board having 18 lines each).
2.4 MODULE CONTACT FINGER IDENTIFICATION
Digital Equipment Corporation’s plug-in modules, including the KDF11-BA, all use the same contact

)UN

Figure 2-2
—

ROW A

ROW B

ROWC

/.‘

COMPONENT SIDE

SIDE
1

ROW D

DV1

DV2

Quad Module Contact Finger Identification

R=SNoTe

O\.\JO‘V oOO« M\Onfl,.O Ow.l flfV/OU AW“H\OQUOJ - WU\AWU= OA.VWOM I.:WJO O @U.\IWMV— Ofl OW\ \WO

R = S e g o w =B e % e, WY

2-17

.50J

MR-5456

Row A, shown in Figure 2-2, includes a numeric identifier for the side of the module. The component
side is designated side 1 and the solder side is designated side 2. Letters ranging from A through V
(excluding G, I, O, and Q) identify particular pins on a side of a slot. A typical pin is designated as
follows.

fi\EZd-w—-— Module Side Identifier “Side” (solder side)

Pin Identifier (Pin E)

Row Identifier (Row A)

The positioning notch between the two rows of pins mates with a protrusion on the connector block for
correct module positioning.

2.5 BACKPLANE PIN ASSIGNMENTS AND THEIR KDF11-BA UTILIZATION
When configuring a system with the KDF11-BA, the module may be inserted in one of several available
backplanes. (Refer to Paragraph 2.6.1 for information on the types of backplanes available.) As an example, Figure 2-3 shows the pin identifications of an H9276 backplane. Individual connector pins
shown are viewed from the module insertion side. Only pins for one slot location are shown in detail.
This pin pattern is repeated 36 times on the backplane, allowing the user to install several double-height
or quad-height modules.

EXTENDED LSI-11 BUS
e

(

A ROWS B

P”“A11
SLOT T
stoT2

CD BUS

PIN V1

C ROWS D

)

M= PIN V2
| Lpinaz

SLOT
3
SLOT
4

SLOT
5
SLOT
6

SLOT
7
SLOT
8
SLOT
9

(VIEW FROM MODULE INSERTION SIDE OF BACKPLANE)
MR 5449

Figure 2-3

H9276 Backplane Pin Identifications

The KDF11-BA backplane pin assignments for rows A and B (extended LSI-11 bus signals) add four

BDAL lines that extend the physical address space to four megabytes. The extended bus pin assignment additions are listed in Table 2-22. (Backplane pin assignment and signal pin functions for the
remaining pins on rows A and B are described in Appendix F.) A comparison of the KDF11-BA,
KDF11-AA, KD11-HA, and KD11-F processors’ backplane pin assignments appears in Appendix D.
2.6 HARDWARE OPTIONS
KDF11-BA systems can be configured with a variety of backplanes, power supplies, enclosures, memo-

ries, peripherals, etc. Figure 2-4 shows a typical configuration for a KDFI11-BA system with 512KB
bytes of memory capacity.

2-18

Table 2-22

KDF11-BA Extended Address Lines

Bus
Pin

Signal
Mnemonic

Signal Function

BCl1

BDAL 18 L

Data/address line 18

BDI1

BDAL 19 L

Data/address line 19

BE1

BDAL 20 L

Data/address line 20

BF1

BDAL 21 L

Data/address line 21

BACKPLANE

SLOTS

ROW A

ROW B

rowc

RowbD

KDF11-BA PROCESSOR MODULE

1
2

MSV11-PL 512 KB MEMORY MODULE

DZV11 FOUR ASYNCHRONOQOUS LINE MODULE

RLV12 DISK CONTRO‘L MODULE

FREE

VIEW FROM MODULE SIDE OF BACKPLANE
MR-5451

Figure 2-4

2.6.1

Typical KDFI1-BA 512K-Byte System

Backplaynes

The KDF11-BA is designed to run in any LSI-11 bus-compatible backplane that accepts quad-height
modules. The KDF11-BA provides 18-bit addressing in backplanes that feature the traditional LSI-11
bus, or 22-bit addressing in backplanes that feature the extended LSI-11 bus. The following LSI-11 bus
and extended LSI-11 bus backplanes are available.

H9276 — A 9-slot X 4-row backplane that supports 22-bit addressing for up to nine quad- or
dual-height modules. The AB slots are bused in accordance with the wiring scheme of the
extended LSI-11 bus; the CD slots are bused in accordance with the wiring scheme of the
CD bus.

H9273 — A 9-slot X 4-row backplane that supports 18-bit addressing for up to nine quad- or
dual-height modules. The AB slots are bused in accordance with the wiring scheme of the
LSI-11 bus; the CD slots are bused in accordance with the wiring scheme of the CD bus.

H9275 - A 9-slot X 4-row backplane that supports 22-bit addressing. Each slot may contain
one quad- or two dual-height modules. The AB and CD slots are bused in accordance with
the wiring scheme of the extended LSI-11 bus.

2-19

H9270 — A 4-slot X 4-row backplane that supports 18-bit addressing. Each slot may contain
one quad- or two dual-height modules. The AB and CD slots are bused in accordance with
the wiring scheme of the LSI-11 bus.

DDVII-B — A 9-slot X 4-row backplane that supports 18-bit addressing. The AB and CD
slots are bused in accordance with the wiring scheme of the LSI-11 bus. The EF slots are
available for user-defined interconnections.

Refer to the PDP-11/23B Mounting Box Technical Manual for a complete description of the H9276
backplane and the Microcomputer Interfaces Handbook for a complete description of the other backplanes listed.
Enclosures

2.6.2

The KDF11-BA may be installed in a variety of enclosures, including, but not limited to, the following.
e

BAI11-S Mounting Box — Contains the H9276 backplane and the H7861 power supply. It
supports 22-bit addressing for up to nine quad- or dual-height modules. The H7861 power

supply provides 36 A at +5 Vand 5 A at +12 V.

BA11-N Mounting Box — Contains the H9273 backplane and the H786 power supply. It supports 18-bit addressing for up to nine quad- or dual-height modules. The H786 power supply
provides 22 A at +5 V and 11 A at +12 V.

BA11-M Mounting Box — Contains the H9270 backplane and the H780 power supply. It supports 18-bit addressing for four slots, each of which may contain one quad- or two dual-height
modules. The H780 power supply provides 18 A at +5 V and 3.5 A at +12 V.

Refer to the PDP-11/23B Mounting Box Technical Manual for a complete description of the BAT1-S
mounting box and the Microcomputer Interfaces Handbook for a complete description of the BA11-N
-

and BA11-M.

Memory Modules

2.6.3

The KDF11-BA is compatible with a wide variety of memories, including, but not limited to, the ones
that follow.

MSVI11-P Quad-Height Memory Module — Provides up to 512K bytes of 22-bit addressable
memory.

MSVI11-L Dual-Height Memory Module — Provides up to 256K bytes of 22-bit addressable
memory.

MSVI11-D Dual-Height Memory Module — Provides up to 64K bytes of 18-bit addressable
memory.

The MSV11-B memory module, which does not have on-board refresh logic and only decodes 16-bit
addresses, is not recommended for use with the KDF11-BA.
2.6.4

Peripheral Options

The KDF11-BA is designed to be compatible with all peripheral options designed to the LSI-11 bus
specification. However, it is incompatible with two types of older options used in systems that support
22-bit addressing.

2-20

Direct Memory Access (DMA) devices that provide 18-bit DMA addresses, such as the
RLV11, RXV2l1, and DRV11-B, can only access up to 256K bytes of memory.

Peripheral devices that use pins BC1, BD1, BE1, and/or BF1 for test signals cannot be used
in extended LSI-11 bus backplanes that bus these pins for BDAL21-18 L.

The RLV12 disk controller is a single quad-height module that provides 22-bit addressing. It replaces
the RLVI11 as an interface to the RLO1 and RLO2 disk drives.
Non-DMA peripheral devices are generally not affected by 22-bit addressing because they monitor
BBS7 L instead of BDAL21-13 to decode 1/0O Page addresses. Refer to the PDP-11/23 Mounting Box
Manual for a listing of peripheral options compatible with the extended LSI-11 bus backplanes.
2.7

SYSTEM DIFFERENCES

A number of minor differences exist between the KDF11-AA or KDF11-BA processors and the LSI-11
(KD11-F) or LSI-11/2 (KD11-HA) processors. The following is a list of these differences.
1.

The KDF11-BA and KDF11-AA do not have a boot loader in console ODT microcode.

The KDF11-BA and KDF11-AA console ODT functions are a subset of the KDI11-F and
KD11-HA ODT functions.

KDF11-BA, KDF11-AA, and KD11-HA do not perform memory refresh.

The EVENT line is on level 6 for the KDF11-BA and KDF11-AA; KD11-F and KD11-HA
have the EVENT line on level 4.

The REV11-C refresh/boot module cannot be used to boot the KDF11-BA system.

Refer to Appendices C, D, and E for additional comparisons among these LSI-11 processors.
2.8

MODULE INSTALLATION PROCEDURE

Certain guidelines should be followed when installing or replacing a KDF11-BA module.
1.

Verify dc power before inserting the module in a backplane.

Ensure that no dc power is applied to the backplane when removing or inserting the module.

Verify the configuration of option jumpers and switches as specified under Paragraphs 2.2
and 2.3.

It is recommended that a single switch be used to apply +5 V and +12 V to the system.

The KDF11-BA module’s response to power-up depends on the power-up mode, as detailed in Table 223.

The following diagnostics are available for checking out the KDF11-BA module.
e

CJKDB CPU Diagnostic — Tests the basic instruction set, EIS, and processor traps.

CJKDA MMU Diagnostic — Checks out the memory management and extended addressing
functions.

2-21

CVMS8A BDV11 Diagnostic — Checks out KDFI11-BA BDV functionality.
CJDLA SLU Diagnostic — Checks out the KDF11-BA serial-line units.

CJKDC and CJKDD Floating-Point Diagnostics — Check out the floating-point option.
CJKDH CIS Diagnostic — Checks out the CIS option.

Table 2-23

Console Power-Up Printout (or Display)*

Power-up | BHALT L
Mode

State

Console Response

Unasserted | Processor will execute the program using the contents at location 24g as
the PC value.

Asserted

]

Unasserted

Asserted

| Terminal will print out a random 6-digit number, which is the contents of
the program counter.
Terminal will print out a random 6-digit number, which is the contents of
the program counter, and enter micro-ODT.

Unasserted | Processor will execute the program at location 773000.7
Asserted

Terminal will print and enter micro-ODT.

Unasserted

Asserted

Terminal will print out 173000 and enter micro-ODT.}
| Mode 3 causes microcode to jump to optional control chip 37g, location
768, and begin microcode execution. This mode is reserved for future use
by DIGITAL and is not recommended for customer use. If this mode is
erroneously selected, the processor will treat it as a reserved instruction
trap to location 10g.
A normal printout-terminal will print out the contents of memory location
10g and enter micro-ODT.

*The terminal printout consists of six octal digits as specified in the table, followed by a carriage return, line feed, and @
prompt in all cases.
TNormal mode for use with the BDV11 bootstrap/diagnostic ROM:s.

2-22

CHAPTER 3

CONSOLE ON-LINE DEBUGGING TECHNIQUE (ODT)

3.1

INTRODUCTION

a
A portion of the microcode in the KDFI1-BA processor emulates the capability normally found on
and
programmer’s console. Since the KDF11-BA does not have a programmer’s console (one with lights
- switches) or a console switch register at bus address 777570, the terminal at the standard bus address of
777560 is used to perform console functions. Communication between the processor and the user 1s via
a stream of ASCII characters interpreted by the processor as console commands. The console terminal
addresses 777560 through 777566 are generated in microcode and cannot be changed.
This feature is called the microcode on-line debugging technique, or micro-ODT. The KDF1 1-BA micro-ODT accepts 18-bit addresses, allowing it to access 248K bytes of memory, plus the 8K-byte I/O
page. A PDP-11 software version of ODT, macro-ODT, is necessary to access memory beyond these
limits. Macro-ODT provides a more sophisticated range of debugging techniques, including access of
memory locations by virtual address.

The differences in use of console ODT in the KDF11-BA as compared with that in the KD11-F (LSI-

- 11) and the KD11-HA (LSI-11/2) are listed in Appendix E.
3.2

TERMINAL INTERFACE

The hardware interface between a terminal (serial-line unit) and ODT is the on-board console serial-line
unit. The terminal is connected to the serial-line unit via connector J1 on the module. Refer to Paragraph 5.14 for a description of the console serial-line unit.

3.3 CONSOLE ODT ENTRY CONDITIONS
The ODT console mode can be entered by the following ways.

Execution of a HALT instruction in kernel mode, provided the HALT TRAP jumper (J16 to

J18) is not installed.

Assertion of the BHALT signal on the bus. Note that the signal must be asserted long enough
that it is seen at the end of a macroinstruction by the SERVICE state in the processor.
BHALT is level-triggered, not edge-triggered. Typically, BHALT remains asserted until the
processor enters ODT.

If power-up mode option 1 has been selected, ODT 1s entered upon processor power-up.

From the console serial-line unit if the halt-on-break feature is enabled. Refer to Paragraph
2.2.5.3.

3-1

NOTE
Unlike the KD11-F and KD11-HA, the KDF11-BA
does not enter console ODT upon occurrence of a
double bus error (for example, when R6 points to
nonexistent memory during a bus timeout trap). The

KDF11-BA creates a new stack at location 2 and
continues to trap to 4. If a bus timeout occurs while
getting an interrupt vector, the KDF11-BA ignores it
and continues execution of the program, whereas in

such case the KD11-F and KD11-HA enter console

ODT. Refer to Appendix E for a listing of the different ways certain processors interpret the same con-

sole ODT commands.

ODT causes the following processor initialization upon entry.
1.

Performs a DATI from RBUF (input data buffer at 777562g) and then ignores the character

present in the buffer. This operation prevents the ODT from interpreting erroneous characters or user program characters as a command.

Prints

Prints the contents of the PC (program counter R7) in six digits.

Prints a <CR> and <LF>.

Prints the prompt character @.

a <CR> and <LF> on the console terminal.

Enters a wait loop for the console terminal input. The DONE flag (bit 7) in the RCSR at

777560g 1s constantly being tested via a DATI by the processor for a 1. If bit 7 is a 0, the
processor keeps testing.

3.4

ODT OPERATION OF THE CONSOLE SERIAL-LINE INTERFACE

The processor’s microcode operates the serial-line interfacein half-duplex mode by using program I/0
techmques rather than interrupts. This means that when the ODT microcodeis busy printing characters using the output side of the interface, the microcodeis not monltorlng the input side forincoming

characters. Any characters coming in whlle the ODT microcodeis printing characters are lost. Overrun
errors detected by the universal asynchronous receiver/transmitter (UART) will be ignored because

the microcode does not check any error bits in the serial-line interface registers.
Therefore, the user should not “type ahead” to ODT because those characters will not be recognized.
More importantly, if another processor is at the end of the serial line, it must obey half-duplex oper-

ation. In other words, no input characters should be sent from the console terminal until the processor’s
ODT output has finished. This restriction does not pertain to echoed characters, however.

3.4.1

Console ODT Input Sequence

The input sequence for ODT follows. (Upon entry to ODT, the RBUF register at 777562 is read but the
character is ignored to prevent the character from being interpreted as a command by the console

ODT.)

3-2

Test RCSR bit 7 (DONE flag) of RCSR at 7775603 using a DATI bus cycle; it it 1s a 0,

If RCSR bit 7 is a 1, read the low byte of RBUF at 777562g using a DATI bus cycle.

continue testing.

Console ODT Output Sequence

3.4.2

The output sequence of ODT is as follows.

Test bit 7 (DONE flag) of the XCSR at 777564g using a DATI busy cycle; if it is a O, contin-

If XCSR bit 7 is a 1, write to the XBUF at 777566g using a DATO bus cycle. The desired
character is in the low byte. The data in the high byte is undefined and is ignored by the

ue testing.

serial-line interface.

If the interrupt enable (bit 6) in the XCSR is a 1, an interrupt will-be created to the software when the
proceed (P) console ODT command is used. If a go (G) command is used, all interrupt enables in peripherals are cleared and an interrupt will not occur.
3.5

CONSOLE ODT COMMAND SET

The ODT command set is listed in Table 3-1 and described in Paragraphs 3.5.1 through 3.5.9. The
commands are a subset of ODT-11 and use the same command characters. ODT has 10 internal states.
Each state recognizes certain characters as valid input and responds with a question mark (?) to all
others.

Table 3-1

Console ODT Commands

Command

Symbol

Function

Slash

Prints the contents of a specified location.

Carriage return

<CR>

Closes an open location.

Line feed

<LF>

Closes an open location and then opens the next con-

Internal register

tiguous location.

$ or R

Opens a specific processor register.

word designator

Opens the PS; must follow an § or R command.

Starts execution of a program.

Proceed

Resumes execution of a program.

Binary dump

Control-shift-S

Manufacturing use only.

(Reserved)

Reserved for DIGITAL use.

designator

Processor status

3-3

The parity bit (bit 7) on all input characters is ignored (i.e., not stripped) by console ODT and if the

input character is echoed, the state of the parity bit is copied to the output buffer (XBUF). Output
characters internally generated by ODT (e.g., <CR>) have the parity bit equal to 0. All commands

are echoed except for <LF>.
In order to describe the use of a command, other commands are mentioned before they have been defined. For the novice user, these paragraphs should be scanned first for familiarization and then reread

for detail. The word “location,” as used in the following paragraphs, refers to a bus address, processor
register, or processor status word (PS).

The descriptions of the ODT commands include examples of the printouts that the processor will output
to the console terminal in response to the commands entered by the user. In the examples given, the
processor output is underlined.
3.5.1

/ (ASCII 057) — Slash

This command 1s used to open a bus address, processor register, or processor status word and is normally preceded by other characters that specify a location. In response to /, ODT will print the contents of the location (six characters) and then a space (ASCII 40). After printing is complete, ODT will

wait for either new data for that location or a valid close command. The space character is issued so

that the location’s contents and possible new contents entered by the user are legible on the terminal.

Example:

where:

@00001000/ 012525 <SPACE>

@ =O0ODT prompt character.
00001000 = octal location in the QBus address space desired by the user (leading Os are
"not required).

=command to open and print contents of location.

012525 =contents of octal location 1000.

<SPACE> = space character generated by ODT.
The / command can be used without a location specifier to verify the data just entered into a previously
opened location. The / produces this result only if it is entered immediately after a prompt character. A
/ issued immediately after the processor enters ODT mode will cause ? <CR>, <LF>, to be printed
because a location has not yet been opened.
Example:

@1000/012525 <SPACE> 1234 <CR> <CR> <LF>

@/001234 <SPACE>

where:

first line =

new data of 1234 entered into location 1000 and location closed with
<CR>.

second line =

a / was entered without a location specifier and the previous location
was opened to reveal that the new contents was correctly entered into
memory.

3-4

(ASCII 15) — Carriage Return

3.5.2 <CR>
the user
This command is used to close an open location. If a location’s contents are to be changed,
location
the
close
will
<<CR>
desired,
is
change
no
If
should precede the <<CR>> with the new data.
without altering its contents.

Example:

@R1/004321 <SPACE> <CR> <CR> <ILF>
@

Processor register R1 was opened and no change was desired, so the user issued <CR>. In response to

the <CR>, ODT printed <CR>,<LF>, and @.

Example:

@R1/004321 <SPACE> 1234 <CR> <CR> <LF>
@

ODT
In this case, the user desired to change R1. The new data, 1234, was entered before the <CR>.
echoes
ODT
@.
and
<LF>,
<CR>,
printed
then
and
location
deposited the new data into the open
the <CR> entered by the user before it prints <CR>, <LF>, and @.
3.53

<LF> (ASCII 12) - Line Feed

Bus adThis command is used to close an open location and then open the next contiguous location.
when
open
is
PS
the
If
ely.
respectiv
dresses and processor registers will be incremented by two and one,
be
will
location
new
no
printed;
be
will
an < LF> is issued, it will be closed and <CR>, <LF>, @
If
<LF>.
the
precede
should
data
new
opened. If the open location’s contents are to be changed, the
no data is entered, the location is closed without being altered.
Example:

@R2/123456 <SPACE> <LF> <CR> <LF>
@R3/054321 <SPACE>

and then
In this case, the user entered <<LF> with no data preceding it. In response, ODT closed R2
to the
over”
“roll
will
ODT
<LLF>,
issues
and
opened R3. When a user has the last register, R7, open,
issues
and
segment
open
d
32K-wor
a
of
first register, RO. When the user has the last bus address

to cross the 32K-word
<LF>, ODT will open the first location of that segment. If the user wishes(i.e.,
ODT is modulo 32K
segment
d
32K-wor
boundary, he/she must reenter the address for the desired

words).

Example:

@R7/000000 <SPACE> <LF> <CR> <LF>
@R0/123456 <SPACE>
or

Example:

@577776/000001 <SPACE> <LF> <CR> <LF>
_@_477776/125252 <SPACE>

in
Unlike other commands, ODT will not echo the <LF>. Instead, it will print <CR>, then <LF>,
does
ODT
decode,
to
easier
this
make
to
order
In
order that teletype printers would operate properly.
@.
not echo ASCII 0, 2, or 10, but responds to these three characters with ? <CR>, <LF>,

3-5

3.5.4

$ (ASCII 044) or R (ASCII 122) — Internal Register Designator

Either character when followed by a register number (0 to 7) or PS designator (S), will open the proces-

sor register specified. The $§ character is recognized to be compatible with ODT-11, and the R charac-

ter was introduced for its being one key stroke representative of its function.
Examples:

@$0 /000123 <SPACE>

@R7/000123 <SPACE> <LF>
@R0/054321 <SPACE>
If more than one character (digit or S) follows the R or §, ODT will use the last character as the register designator. An exception: if the last three digits equal 077 or 477, ODT will open the PS rather than
R7.
3.5.5

S (ASCII 123) — Processor Status Word Designator

This designator is for opening the processor status word and must be used after the user has entered an
R or § register designator.
Example:

~ @RS/100377 <SPACE> 0 <CR> <CR> <LF>

@/000010 <SPACE>
Note that the trace bit (bit 4) of the processor status word cannot be modified by the user. This is so in
order that PDP-11 program debugging utilities (e.g., ODT-11), which use the T bit for single-stepping,

will not be accidentally harmed by the user. If the user issues an <<LF> while the processor status
word 1s open, the word is closed and ODT will print a <CR>, <LF>, @: no new location is opened in

this case.
3.5.6

G (ASCII 107) - Go

This command is used to start program execution at a location entered immediately before the G. This
function is equivalent to the LOAD ADDRESS and START switch sequence on other PDP-11 con-

soles.

Example:

@200 <NULL> <NULL>

The ODT sequence for a G, after echoing the command character, is as follows.
1.

Print two nulls (ASCII 0) so the bus initialize that follows will not flush the G character from
the double buffered UART chip in the serial-line interface.

Load R7 (PC) with the entered data. If no data is entered, 0 is used. (In the above example,
R7 will equal 200 and that is where program execution will begin.)

The PS, and FPS (floating-point status) register will be cleared to 0.

The LSI-11 bus is initialized by the processor asserting BINIT L for 12.6 us, negating BINIT L, and then waiting for 110 us.

The service state is entered by the processor. Anything to be serviced is processed. If the
BHALT L bus signal is asserted, the processor reenters the console ODT state. This feature
is used to initialize a system without starting a program (R7 is altered). If the user wants to
single-step a program, he/she issues a G and then successive P commands, all done with the
BHALT L bus signal asserted.

3-6

P (ASCII 120) - Proceed

3.5.7

This command is used to resume execution of a program and corresponds to the CONTINUE switch on
other PDP-11 consoles. No machine state visible to the programmer is altered using this command.
Example:

Program execution resumes at the place pointed to by R7. After the P is echoed, the ODT state 1s left
and the processor immediately enters the state to fetch the next instruction. If a HALT request is asserted, it is recognized at the end of the instruction (during the service state) and the processor will
enter the ODT state. Upon entry, the contents of the PC (R7) will be printed. In this fashion, a user can
single-step through a program and get a PC “trace” displayed on his/her terminal.
Control-Shift-S (ASCII 23) — Binary Dump

3.5.8

This command is used for manufacturing test purposes and is not a normal user command. It is intended to display a portion of memory more efficiently than the / and <LF> commands do. The protocol 1s as follows.

After a prompt character, ODT receives a control-shift-S command and echoes it.

The host system at the other end of the serial line must send two 8-bit bytes which ODT will
interpret as a starting address. These two bytes are not echoed. The first byte specifies starting address <<15:8> and the second byte specifies starting address <<7:0>. Bus address bits
<21:16> are always forced to 0; the DUMP command is restricted to the first 32K words of
address space.

After the second address byte has been received, ODT outputs 10g bytes to the serial line,
starting at the address previously specified. When the output is finished, ODT will print

<CR>, <LF>, @.

If a user accidentally enters this command, it is recommended that, in order to exit from the
command, two @ characters (ASCII 100) be entered as a starting address. After the binary

dump, the user will get the prompt character @.
Reserved Command

3.5.9

An ASCII H (110) is reserved for future use by DIGITAL. If it is accidentally typed, ODT will echo
the H and print a prompt character rather than a ?, which is the invalid character response. No other
operation is performed.

3.6

KDF11-BA ADDRESS SPECIFICATION

The KDF11-BA micro-ODT accepts 18-bit addresses, allowing it to access 248K bytes of memory, plus
the 8K-byte 1/0 page. All I/O page addresses must be entered by users with a full 18 bits specified.
For example, if a user wishes to open the RCSR of the SLU (serial-line unit), he/she must enter
777560, not 177560.

3.6.1

Processor I/0O Addresses

Certain processor and MMU registers have 1/O addresses assigned to them for programming purposes.

If referenced in ODT, the PS will respond to its bus address, 777776. Processor registers RO through
R7 will not respond (i.e., timeout will occur) to bus addresses 777700 through 777707 if referenced in

ODT.

The MMU contains status registers and PAR/PDR pairs. These registers can be accessed from ODT
by entering their bus address.

Example:

@777572/000001 <SPACE>
3-7

In this case, memory management status register O is opened to show the memory management enable
bit set.

The FP11 accumulators, which are also in the MMU chip, cannot be accessed from ODT. Only FPI11
instructions can access these registers.

3.6.2

Stack Pointer Selection

Accessing kernel and user stack pointer registers is accomplished in the following way. Whenever R6 is
referenced in ODT, it accesses the stack pointer specified by the PS current mode bits (PS<<15:14>).
This is done for convenience. If a program operating in kernel mode (PS<<15:14> = 00) is halted, and
R6 1s opened, the kernel stack pointer is accessed.
Similarly, if a program is operating in user mode (PS<<15:14> = 11), the R6 command accesses the

user stack pointer. If a different stack pointer is desired, PS<<15:14> must be set by the user to the
appropriate value, and then the R6 command can be used. If an operating program has been halted, the
original value of PS<C15:14> must be restored in order to continue execution.

Example:

PS = 140000
@R6/123456 <SPACE>

The user mode stack pointer has been opened.

@RS /140000 <SPACE> 0 <CR> <CR> <LF>
@R6/123456 <SPACE> <CR> <CR> <LF>

@RS/000000 <SPACE> 140000 <CR> <CR> <LF>
@P

In this case, the kernel mode stack pointer was desired. The PS was opened and PS<15:14> was set to

00 (kernel mode). Then R6 was examined and closed. The original value of PS<<15:14> was restored,
and then the program was continued using the P command.
If PS<<15:14> are set to 01, another unique register within the processor is accessed. This register is

reserved for future use by DIGITAL.
3.6.3

Entering of Octal Digits

In general, when the user 1s specifying an address or data, ODT will use the last six digits if more than

six have been entered. The user need not enter leading Os for either address or data; ODT forces Os as
the default. If an odd address is entered, the low-order bit is ignored, and a full 16-bit word is displayed.
3.6.4

ODT Timeout

If the user specifies a nonexistent address, ODT will respond to the bus timeout by printing ?, <CR>,

<LF>, @.
3.7

INVALID CHARACTERS

In general, any character that ODT does not recognize during a particular sequence is echoed (with the

exception of ASCII codes 0, 2, 10, and 12 as noted earlier) and ODT will print 7, <CR., <LF>, @.
ODT has 10 internal states, with each state having its own set of valid input characters. Some commands are allowed only when in certain states or sequences; thus an attempt has been made to lower the
probability of a user’s unconsciously destroying himself by pressing the wrong key. Table 3-2 defines

the ODT states and valid input characters.

3-8

Example of
Terminal Output

TQRE

State

Console ODT States and Valid Input Characters
Valid Input

0-7
AN

Table 3-2

Control-shift-S

@R or @$
S

@1000/123456
<CR>
<LF>

@R1/123456
<CR>
<LF>

0-7

@1000

@R1 or @RS
S

/
@1000/123456 1000

0-7

@R 1/123456 1000

0-7

@ Control-shift-S

2 binary bytes

*Indicates previous location was opened.

3-9

CHAPTER 4
EXTENDED LSI-11 BUS

4.1

INTRODUCTION

The processor, memory and I/O devices communicate via signal lines that constitute the extended LSI11 bus. The extended LSI-11 bus contains 4 additional address lines (BDAL<<21:18>) in addition to
the 38 lines of the original LSI-11 bus. The four additional address lines extend the 256K-byte physical
address space of the LSI-11 bus to 4 megabytes. Addresses, 8-bit bytes or 16-bit data words, bus synchronization, and control signals are sent along these 42 lines. Addresses may be either 16, 18, or 22
bits wide, depending on the addressing capability of the processor installed in the system. The 16-bit
data and the first 16 address bits are time-multiplexed over the same 16 data/address lines. Two additional address bits (<<17:16>) and the memory parity bits are also time-multiplexed over two-signal
lines. The signal lines are functionally divided as listed in Table 4-1. Refer to Appendix F for a detailed
list of the extended LSI-11 bus signal functions.

The LSI-11 bus lines may be considered transmission lines that are terminated in their characteristic
impedance (Zg) at both the near and far ends of the bus. The near end of the bus is defined as the first
bus interface slot in the backplane, the far end is the last bus interface slot.
Table 4-1

Summary of Signal Line Functions

Quantity

Function

Bus Signal Mnemonic

Data/address lines

BDAL<15:00>

Memory parity /address lines

BDAL<17;16>

Address lines

BDAL<21:18>

Address and data transfer

BSYNC, BDIN, BDOUT,

control lines

BWTBT, BBS7, BRPLY

Direct memory access (DMA)
control lines

BDMR, BDMG, BSACK

Interrupt control lines

BIRQ4, BIRQS5, BIRQ6,

System control lines

BPOK, BDCOK, BINIT,

BIRQ7, BIAK

BHALT, BREF, BEVNT

4-1

Most LSI-11 bus signals are bidirectional and use a terminating resistor network connected between
+5 V and ground to provide a negated (high) signal level. Devices may be connected to any point along
the bus to receive signals from the near or far end of the bus via high-impedance bus receivers, or to
transmit signals to the near or far end through gated open-collector bus drivers. A bus driver asserts a
signal by causing the line to go from a high level (approximately 3.4 V) to a low level (approximately
0.5 V). Although bidirectional lines are electrically bidirectional, certain lines carry signals that are
functionally unidirectional. The functionally unidirectional lines carry signals that are required to travel
in only one direction. For example, when a device asserts a bus request signal (BIRQ), the signal always
travels from the requesting device to the processor and never in the reverse direction.
The interrupt acknowledge (BIAK) and direct memory access grant (BDMG) signals are physically
unidirectional signals that are wired to each LSI-11 bus slot in a daisy-chain scheme. These signals are
generated by the processor in response to interrupt and direct memory access requests and are transmitted to the bus via output signal pins. Each of the output signals (BIAKO or BDMGO) is received on
a device input pin (BIAKI or BDMGI) and conditionally retransmitted via a device output pin
(BIAKO or BDMGO). These signals are received from higher-priority devices and retransmitted to
lower-priority devices on the bus. DMA and I/O interrupt priorities are discussed in Pargaraphs 4.4
and 4.5.1.

Bus Master/Slave Relationship

Communication between devices on the bus is asynchronous. A master/slave relationship exists
throughout each bus transaction. At any time, there is one device that has control of the bus. This controlling device is termed the “bus master.” The master device controls the bus when communicating
with another device on the bus, termed the “slave.” The bus master (typically the KDF11-BA processor
or a DMA device) initiates a bus transaction. The slave device responds by acknowledging the transaction in progress and by receiving data from, or transmitting data to, the bus master. The extended LSI11 bus control signals transmitted or received by the bus master or bus slave device must complete the
sequence according to the protocol established for transferring address and data information. The processor controls bus arbitration (i.e., “decides” which device is to be bus master at any given time).
A typical example of a master/slave relationship has the processor, as master, fetching an instruction
from memory which is always a slave). Another example is a disk drive, as master, transferring data to
memory, again, as the slave. Any device except the processor can be master or slave depending on the
circumstances. Communication on the extended LSI-11 bus is interlocked; therefore, for each control
signal issued by the master device, there must be a response from the slave in order to complete the
transfer. It is the master/slave signal protocol that makes the extended LSI-11 bus asynchronous. The
asynchronous operation allows both fast and slow devices to use the bus and eliminates the need for
synchronizing clock pulses between the bus master and slave device.

Since bus cycle completion by the bus master requires response from the slave device, each bus master
must include a timeout error circuit that will abort the bus cycle if the slave device does not respond to
the bus transaction within 10 us. The KDF11-BA has a bus timer that restarts the clock when no device
responds to BDIN L or BDOUT L within 10 us. An immediate trap to location 4g occurs. The slowest
peripheral or memory device must respond in less than 10 us to prevent a bus timeout error.

4.2

BUS SIGNAL NOMENCLATURE

Throughout the following protocol specifications, bus signals are referred to in several different ways.
1.

In general discussions where timing, polarity, and physical location are unimportant, the base

signal name without any prefixes or suffixes is used. For example:
SYNC, WTBT, BS7, DAL <21:00> or the DAL lines

Most signals on the backplane etch are asserted low and referred to with a prefix character
B, and a suffix (space) L. For example:
BSYNC L, BWTBT L, BBS7 L, BDAL<21:00> L

BPOK H and BDCOK H are asserted high.

Receivers and drivers are considered part of the bus. Signal inputs to drivers are referred to
with a prefix character T for transmit. For example:
TSYNC, TWTBT, TBS7, TDAL<21:00>

Signal outputs of receivers are referred to with a prefix character R for received. For
example:

RSYNC, RWTBT, RBS7, RDAL<21:00>

Whenever timing is important, the designations in items 3 and 4 above are used to reference timing to a
receiver output or driver input. For example, after receipt of the negation of RDIN, the slave negates
its TRPLY (0 ns minimum, 8000 ns maximum). It must maintain data valid on its TDAL lines until O
ns (minimum) after the negation of RDIN, and must negate its TDAL lines 100 ns (maximum) after
the negation of its TRPLY.

4.3

DATA TRANSFER BUS CYCLES

Data is transferred between a bus master and slave device to accomplish various functions. The data

transfer bus cycles and their functions are described in Table 4-2.

Table 4-2

Data Transfer Bus Cycles

Bus Cycle

Function (with respect

Mnemonic

Description

to the bus master)

DATI
DATO

Data word input
Data word output
Data byte output
Data word input/output
Data word input/byte output

Read
Write

DATOB
DATIO
DATIOB

Write byte

Read-modify-write
Read-modify-write byte

These bus cycles, executed by bus master devices, transfer 16-bit words or 8-bit bytes to or from slave
devices. The data to be written in the destination byte during byte output operations is valid on the

appropriate BDAL lines. For example, BDAL<15:08> contains the high byte, and BDAL<<07:00>
contains the low byte. Table 4-3 describes the bus signals used in a data transfer operation.
Data transfer bus cycles can be reduced to three basic types: DATI, DATO(B) and DATIO(B). These
transactions occur between the bus master and one slave device selected during the addressing portion

of the bus cycle.

4-3

Table 4-3

Mnemonic

Description

Data Transfer Bus Signals

Function

BDAL<<21:00>| 22 Data/address lines
L

BDAL<21:18> L are used for 22-bit extended addressing; BDAL<17:16> L are used for 18-bit extended ad-

BSYNC L

dressing, memory parity error, and memory parity error
enable functions; BDAL<15:00> L are used for 16-bit
addressing, word and byte transfers.

Synchronize

Data input strobe
Data output strobe
Reply

Strobe signals

BDIN L
BDOUT L
BRPLY L

BWTBT L

Write /byte control

Control signals

BBS7 L

Bank 7 select

4.3.1

Bus Cycle Protocol

Before initiating a bus cycle, the previous bus transaction must have been completed (BSYNC L negated) and the device must become bus master. The bus cycle is divided into two parts: an addressing
portion, and a data transfer portion. During the addressing portion, the bus master outputs the address
for the desired slave device (memory location or device register). The selected slave device responds by
latching the address bits and holding this condition for the duration of the bus cycle (until BSYNC L
becomes negated). During the data transfer portion of the bus cycle, the operations performed will vary
slightly, depending on the type of data transfer desired. Paragraphs 4.3.1.2 through 4.3.1.4 describe the
data transfer portion of the various bus cycles.

4.3.1.1 Device Addressing — The device addressing portion of a data transfer bus cycle comprises an
address setup/deskew time and an address hold/deskew time. During the address setup/deskew time
the bus master does the following.

Asserts TDAL<21:00> with the desired slave device address bits.

Asserts TBS7 if a device in the I /O page is being addressed.

Asserts TWTBT if the cycle is a DATO(B) bus cycle.

Asserts TSYNC 150 ns (minimum) after gating TDAL, TBS7, and TWTBT onto the bus.

During this time the address, RBS7, and RWTBT signals are asserted at the slave bus receiver for at
least 75 ns before RSYNC becomes active. Devices in the 1/O page ignore the 9 high-order address
bits RDAL<21:13> and instead decode RBS7 along with the 13 low-order address bits. An active
RWTBT signal indicates that a DATO(B) operation follows, while an inactive RWTBT indicates a
DATI or DATIO(B) operation.

4-4

The address hold/deskew time begins after RSYNC is asserted. The slave device uses the active
RSYNC to clock RDAL address bits, RBS7 and RWTBT, into its internal logic. RDAL<21:00>,
RBS7, and RWTBT will remain active for 25 ns (minimum) after the RSYNC becomes active.
RSYNC remains active for the duration of the bus cycle.
Memory and peripheral devices are addressed similarly, except for the way they respond to RBS7. Addressed peripheral devices must not decode address bits on RDAL<<17:13>. Addressed peripheral devices may respond to a bus cycle only when RBS7 is asserted during the addressing portion of the cycle.
When asserted, RBS7 indicates that the device address resides in the 1/O page (the upper 8K-byte
address space). Memory devices generally do not respond to addresses in the 1/O page; however, some
system applications may permit memory to reside in the I/O page for use as DMA buffers, read-only
memory bootstraps or diagnostics, etc.
|

4.3.1.2 DATI - The DATI bus cycle is a read operation that inputs data from the slave device to the
bus master. The operations performed by the bus master and slave device during a DATI are shown in
Figure 4-1. The DATI bus cycle timing is shown in Figure 4-2. Data consists of 16-bit word transfers
over the bus. During the data transfer portion of the DATI bus cycle, the bus master asserts TDIN 100
ns (minimum) after it asserts TSYNC. The slave device responds to RDIN active by asserting:

TRPLY after receiving RDIN and 125 ns (maximum) before TDAL bus driver data bits are
valid.

TDAL<17:00> L with the addressed data and error information.

When the bus master receives RRPLY, it does the following.
1.

Waits at least 200 ns deskew time and then accepts input data at RDAL<<15:00> bus receivers. RDAL<17:16> are monitored for a possible parity error indication.

Negates TDIN 150 ns (minimum) after RRPLY becomes active.

The slave device responds to RDIN negation by negating TRPLY and removing read data from TDAL

bus drivers. TRPLY must be negated 100 ns (maximum) prior to removal of read data. The bus master
responds to the negated RRPLY by negating TSYNC.

Conditions for the next TSYNC assertion are as follows.
1.

TSYNC must remain negated for 200 ns (minimum).

TSYNC must not become asserted within 300 ns of the previous RRPLY negation.

4-5

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
°* ASSERT BDAL <21:00> L WITH
ADDRESS AND

e ASSERT BBS7 IF THE ADDRESS
ISIN THE I/O PAGE
e ASSERT BSYNC L
\

DECODE ADDRESS

STORE"DEVICE SELECTED"
OPERATION

/ -

REQUEST DATA

REMOVE THE ADDRESS FROM

BDAL <21:00> L AND NEGATE BBS7
L

ASSERT BDIN L

—_—
\

INPUT DATA

e
/

PLACE DATA ON BDAL < 15:00> L
ASSERT BRPLY L

TERMINATE INPUT TRANSFER

e ACCEPT DATA AND RESPOND
BY NEGATING BDIN L

—_
\
,

\
—_

TT—a

TERMINATE BUS CYCLE
o NEGATE BSYNC L

OPERATION COMPLETED
e NEGATE BRPLY L
MR-6028

Figure 4-1

DATI Bus Cycle

T/RDAL

(4)

T ADDR

}(

150ns_.'

T SYNC

MIN

(4)

100ns |

MIN

200

R DATA

_.l

ns MAX

(4)

200ns MIN

—>

CLOCK DATA

8uS MAX r

—=

100ns MIN

T DIN

200ns MIN —

le——— 200ns MIN

'l:.

R RPLY

\/
150ns MIN

"‘

—

ja@—

300ns MIN

.4—100ns MIN

TBS7

(4)

TWTBT

(4)

(4)
TIMING AT MASTER DEVICE

R/T DAL

(4) ffl ADDR

(4)

25ns

—

X
—

T DATA

e— 125ns MAX

—

(4)
100ns MAX, Ons MIN

‘=

Ons MIN —|——#

RSYNC
>

75ns

o«

tg—————— 200ns MIN

MIN

R DIN

150ns MIN -&

\
r——- 300ns MIN

T RPLY

RBS7

—’l

<¢— 75ns MIN

(4) )(

X
-

RWTBT (4)

(4)
25ns MIN

(4)

TIMING AT SLAVE DEVICE

NOTES:

1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS.

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A “B” PREFIX.

2.SIGNAL NAME PREFIXES ARE DEFINED BELOW:

4. DON'T CARE CONDITION.

T=BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

MR-6037

Figure 4-2

DATI Bus Cycle Timing

4-7

4.3.1.3 DATO(B) - DATO(B) is a write operation. Data is transferred in 16-bit words (DATO) or 8bit bytes (DATOB) from the bus master to the slave device. The data transfer output can occur after
the addressing portion of a bus cycle when TWTBT has been asserted by the bus master, or immediately following an input transfer part of a DATIO(B) bus cycle. The operations performed by the bus
master and slave device during a DATO(B) bus cycle are shown in Figure 4-3. The DATO(B) bus cycle

timing is shown in Figure 4-4.

SLAVE

BUS MASTER

(MEMORY OR DEVICE)

(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY
e ASSERT BDAL <21:00> L WITH
ADDRESS AND

ASSERT BBS7 L IF ADDRESSIS
IN THE 1/0 PAGE

ASSERT BWTBT L (WRITE
CYCLE)

—_—

o ASSERT BSYNC L

\
—

DECODE ADDRESS

STORE “DEVICE SELECTED
OPERATION

__—
_—

-—

OUTPUT DATA

—

e REMOVE THE ADDRESS FROM
BDAL <21:00> L AND NEGATE BBS7 L
e NEGATE BWTBT L UNLESS DATOB

o PLACE DATA ON BDAL < 15:00> L
—
e ASSERT BDOUT L

——
\

—

T TAKE DATA

RECEIVE DATA FROM BDAL
LINES

— © ASSERT BRPLY L
/

-—

TERMINATE OUTPUT TRANSFER
e NEGATE BDOUT L (AND BWTBT L

IF A DATOB BUS CYCLE)
o REMOVE DATA FROM BDAL <15:00> L_____

—

\ \&
OPERATION COMPLETED

//
/

___°

NEGATEBRPLY L

TERMINATE BUS CYCLE
e

NEGATE BSYNC L

MR-6029

Figure 4-3

DATO or DATO(B) Bus Cycle

A.l

T ADDR

T DAL

MIN

TSYNC

l‘—

X
e

T DATA

100ns ' .

Ons MIN

g¢— 175ns MIN

T DOUT

L‘i 200ns MIN —

\?L— 300ns MIN ————

150ns MIN—"

R RPLY

'fl'mOnleN

T BS7
150ns MIN

TWTBT

L150nsMIN->

ASSERTION =BYTE

(4)

—-bl 100ns MIN L—

MIN

TIMING AT MASTER DEVICE

R DAL

(4)

X R ADDR

R DATA

<¢— 25ns MIN

—®

(4)

L—25ns MIN

R SYNC

/
.

R DOUT

MIN

2bns

—

[

le—— 100ns MIN

)

150ns MIN —>

\
/

——| 150ns MIN A

300ns MIN

T RPLY

75ns MIN

R BS7

RWTBT

25ns MIN

(4)

L
\/

—

ASSERTION =BYTE

L—‘ 25ns MIN

r— 25ns MIN
x

(4)

TIMING AT SLAVE DEVICE
NOTES:

1. TIMING SHOWN AT MASTER AND SLAVE DEVICE

BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T

3.BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A “B” PREFIX.
4. DON'T CARE CONDITION.

=BUS DRIVER INPUT

R =BUS RECEIVER OUTPUT
MR-1179

Figure 4-4

DATO or DATO(B) Bus Cycle Timing

4-9

The data transfer portion of a DATO(B) bus cycle comprises a data setup/deskew time and a data
hold/deskew time. During the data setup/deskew time, the bus master outputs the data on
TDAL<15:00> 100 ns (minimum) after TSYNC is asserted. If it is a word transfer, the bus master
negates TWTBT while gating data onto the bus. If the transfer is a byte transfer, the bus master asserts
TWTBT while gating data onto the bus. During a byte transfer, the condition of BDAL 00 L during the
address cycle selects the high or low byte. If asserted, the high byte (BDAL<<15:08> L) is selected;
otherwise, the low byte (BDAL<<07:00> L) is selected. An asserted BDAL 16 L at data transfer time
will force a parity error to be written into memory if the memory is a parity-type memory. BDAL 17 L
is not used for write operations. The bus master asserts TDOUT L 100 ns (minimum) after the TDAL
and TWTBT bus driver inputs are stable. The slave device responds to RDOUT by accepting the input
data and asserting TRPLY (8 wus maximum to avoid bus timeout). This completes the data setup/deskew time. During the data hold/deskew time the bus master negates TDOUT 150 ns (minimum) after the assertion of RRPLY. TDAL<21:00> bus drivers remain stable for at least 100 ns
after TDOUT negation. The bus master then negates TDAL inputs.
During this time, the slave device senses RDOUT negation and negates TRPLY. The bus master responds by negating TSYNC. However, the processor will not negate TSYNC for at least 175 ns after
negating TDOUT. This completes the DATO(B) bus cycle. Before the next cycle, TSYNC must remain unasserted for at least 200 ns. Also, TSYNC may not assert until 300 ns (minimum) after
RRPLY negates.
4.3.1.4 DATIO(B) - The protocol for a DATIO(B) bus cycle is identical to the addressing and data
transfer portions of the DATI and DATO(B) bus cycles. After addressing the device, a DATI cycle is
performed as explained in Paragraph 4.3.1.2; however, TSYNC is not negated. TSYNC remains active
for an output word or byte transfer [DATO(B)]. The bus master maintains at least 200 ns between
RRPLY negation during the DATI cycle and TDOUT assertion. The cycle is terminated when the bus
master negates TSYNC, which follows the same protocol as described for DATO(B). The operations
performed by the bus master and slave device during a DATIO or DATIO(B) bus cycle are shown in
Figure 4-5. The DATIO and DATIO(B) bus cycle timing is shown in Figure 4-6.

4.4

DIRECT MEMORY ACCESS (DMA)

The direct memory access (DMA) capability allows direct data transfers between I/0O devices and
memory. This is useful when using mass storage devices (e.g., disk drives) that move large blocks of
data to and from memory. A DMA device only needs to know the starting address in memory, the
starting address in mass storage, the length of the transfer, and whether the operation is read or write.
When this information is available, the DMA device can transfer data directly to or from memory.
Since most DMA devices must perform data transfers in rapid succession or lose data, DMA requests
are assigned the highest priority level.

DMA is accomplished after the processor (normally bus master) has passed bus mastership to the highest-priority DMA device that is requesting the bus. The processor arbitrates all requests and grants the
bus to the DMA device located electrically closest to the processor. A DMA device remains bus master
until it relinquishes its mastership. The following control signals are used during bus arbitration.
BDMGI L
BDMGO L
BDMR L
BSACK L

DMA Grant Input

DMA Grant Output
DMA Request Line
Bus Grant Acknowledge

4-10

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY

ASSERT BDAL <21:00> L WITH

®©

ASSERT BBS7 L IF THE

ADDRESS

ADDRESS IS IN THE I/O PAGE
®

ASSERT BSYNC L

B ECODE ADDRESS
e

STORE “DEVICE SELECTED"
OPERATION

REQUEST DATA
e

REMOVE THE ADDRESS FROM

ASSERT BDIN

BDAL <21:00> L
L

_—

— > |NPUT DATA

TERMINATE INPUT TRANSFER
e

PLACE DATA ON BDAL <15:00> L

ASSERT BRPLY L

ACCEPT DATA AND RESPOND BY
TERMINATING BDIN L
— — _— - -

COMPLETE INPUT TRANSFER

OUTPUT DATA
e

REMOVE DATA

NEGATE BRPLY L

PLACE OUTPUT DATA ON BDAL < 15:00
> L

(ASSERT BWTBT L IF AN OUTPUT
BYTE TRANSFER)

ASSERT BDOUT L
o

\\\~

TAKE DATA
e

RECEIVE DATA FROM BDAL LINES

ASSERT BRPLY L

TERMINATE OUTPUT TRANSFER
REMOVE DATA FROM BDAL LINES
e
e

NEGATE BDOUT L
\\

OPERATION COMPLETED

®
J—

TERMINATE BUS CYCLE
e

NEGATE BRPLY L

a—

a— - - -

NEGATEBSYNCL

(AND BWTBT L IFIN
A DATIOB BUS CYCLE)
MR-6030

Figure 4-5

DATIO or DATIO(B) Bus Cycle

r— 150ns MIN

R/TDAL

(4)

X T ADDR )

MIN

100ns

-.l

(4)

X R DATAX

(4)

T DATA

’

200ns

I“ Ons MIN

)(

(4)

— L—100ns MIN
!

TSYNC
lk@—

T DOUT

MIN

200ns MIN

175ns

— 150ns

100ns MIN
//

e 200ns MIN —e

\
e— 200ns IVHN—-I

T DIN

R RPLY

e—

150ns | o
MIN

T BS7

><
—

<€— 100ns MIN

TWTBT (4>\

100ns MIN

(4)

ASSERTION = BYTE

‘-—

(4)

<¢— 150ns MIN

TIMING AT MASTER DEVICE

RT/DAL D(R ADDR)(

—&

(4)

X T DATA

25ns MIN

R SYNC __//
—»{

(4)

)(

R DATA

—& L— 25ns MIN

— I<— 100ns MAX

ke— 75nsMIN

25ns MIN —# r-

—&

<t—

100ns MIN

150ns MIN |e-

TM ,1\,12:;'(5 <

R DOUT

(4)

200ns MIN —

R DIN

j“

[+— 150ns MIN —»> / le— 300ns
MIN —
T RPLY

R BS7

“L

¢— 75ns MIN

——!

F— 75r!s MIN

RWTBT (4%

(4)
—

25ns MIN

e— 25ns MIN

—

ASSERTION =BY TE

l-— 25ns MIN

(4)

TIMING AT SLAVE DEVICE
NOTES:
1. TIMING SHOWN AT REQUESTING DEVICE
BUS DRIVER INPUTS AND BUS RECEIVER OUTPUTS
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A “B"” PREFIX.
4. DON'T CARE CONDITION.

T =BUS DRIVER INPUT
R =BUS RECEIVER OUTPUT
MR 6036

Figure 4-6

DATIO or DATIO(B) Bus Cycle Timing

A DMA transaction is divided into three phases: the bus mastership acquisition phase, the data transfer
phase, and the bus mastership relinquish phase. The operations performed by the processor and bus
master during the DMA request/grant sequence are shown in Figure 4-7. The DMA request/grant bus
|

cycle timing is shown in Figure 4-8.

During the bus mastership acquisition phase, a DMA device requests the bus by asserting TDMR. The
processor arbitrates the request and initiates the transfer of bus mastership by asserting TDMGO. The
maximum time between BDMR L assertion by the DMA device and BDMGO L assertion by the processor is DMA latency. This time is processor-dependent. The KDF11-BA asserts TDMGO 1.4 us
(maximum) after the assertion of RDMR.

BDMGO L/BDMGI L is one of two signals that are daisy-chained through each module in the backplane. The signal is driven out of the processor on the BDMGO L pin, enters each module on the
BDMGTI L pin and exits on the BDMGO L pin. This signal passes through the modules in descending
order of priority until it is stopped by the requesting device. The requesting device blocks the output of
BDMGO L and asserts TSACK. If no device responds to the DMA grant, the processor will clear the
grant and rearbitrate the bus.

NOTE

The KDF11-BA uses a “NO-SACK” timer, which
clears BDMGO L if BSACK L is not received from
the DMA device within 10 us.

During the data transfer phase, the DMA device continues asserting BSACK L. If multiple-data transfers are performed during this phase, consideration must be given to the use of the bus for other system
functions, such as memory refresh (if required). The actual data transfer is performed in the same manner as the data transfer portion of DATI, DATO(B) and DATIO(B) bus cycles described in Paragraphs
4.3.1.2 through 4.3.1.4.

The DMA device can assert TSYNC L for a data transfer 0 ns (minimum) after it receives RDMGI L,
250 ns (minimum) after RSYNC is negated, and 300 ns (minimum) after RRPLY is negated.

During the bus mastership relinquish phase the DMA device relinquishes the bus by negating TSACK.
This occurs after the last data transfer cycle (RRPLY negated) is completed (or aborted). TSACK may
be negated up to 300 ns (maximum) before negating TSYNC.

4.5

INTERRUPTS

The interrupt capability of the LSI-11 bus allows any I/O device to suspend temporarily (interrupt)
current program execution and divert processor operation for service of the requesting device. The processor inputs a vector from the device to start the service routine (handler). As with a device register
address, the hardware fixes the device vector at locations within a designated range of addresses between 000 and 777g. The vector indicates the first of a pair of addresses. The content of the first address is read by the processor; it is the starting address of the interrupt handler. The content of the
second address is a new processor status word (PS). The PS bits <<07:05> can be programmed to a
priority level from O to 7g. Only interrupts on a level higher than the number in the priority level field
of the PS are serviced by the processor. If the interrupt priority level of the new PS is higher than that
of the original PS, the new PS raises the interrupt priority level and thus prevents lower-level interrupts
from breaking into the current interrupt service routine. Control is returned to the interrupted program
when the interrupt service routine is completed. The original (interrupted) program’s address (PC) and
its associated PS are stored on a “stack.” The original PC and PS are restored by a return from interrupt instruction (RTI or RTT) at the end of the service routine. The use of the stack and the LSI-11 bus
interrupt scheme can allow interrupts to occur within interrupts (nested interrupts) if the requesting
interrupt has a higher priority level than the interrupt currently being serviced.

4-13

KDF11-BA PROCESSOR

BUS MASTER

(MEMORY IS SLAVE)

(CONTROLLER)

REQUEST BUS

e ASSERT BDMR L

GRANT BUS CONTROL

e NEAR THE END OF THE
CURRENT BUS CYCLE

(BRPLY L IS NEGATED),
ASSERT BDMGO L AND

INHIBIT NEW PROCESSOR
GENERATED BYSNC L FOR
THE DURATION OF THE

ACKNOWLEDGE BUS
MASTERSHIP

o RECEIVE BDMG

DMA OPERATION.

WAIT FOR NEGATION OF
BSYNC L AND BRPLY L

ASSERT BSACK L
e NEGATE BDMR L

TERMINATE GRANT

SEQUENCE
e NEGATE BDMGO L AND

WAIT FOR DMA OPERATION
TO BE COMPLETED
EXECUTE A DMA DATA
TRANSFER
ADDRESS MEMORY AND
TRANSFER UP TO 4 WORDS

OF DATA AS DESCRIBED
FOR DATI, OR DATO BUS

CYCLES
RELEASE THE BUS BY
TERMINATING BSACK L

(NO SOONER THAN
NEGATION OF LAST BRPLY

RESUME PROCESSOR
a

OPERATION

L) AND BSYNC L.

ENABLE PROCESSORGENERATED BSYNC L

(PROCESSOR IS BUS

WAIT 4 us OR UNTIL

MASTER) OR ISSUE

ANOTHER FIFO TRANSFER

ANOTHER GRANT IF BDMR
L IS ASSERTED

IS PENDING BEFORE
REQUESTING BUS AGAIN.
MR-6031

Figure 4-7

DMA Request/Grant Sequence

SECOND
REQUEST

—.1

le— DMA LATENCY

—r 7

T T 7T T 7777

J—

Ons MIN

—

R DMG

T SACK

R/T SYNC

R/T RPLY

—

'4—

250ns MIN —»

T DAL

300ns MIN ——]

ADDR

Onsmm——l

250ns MIN —8

"— 300ns MAX

\
—b

DATA

(ALSO BS7,
WTBT,

7
77T

4 // // // // //

/S
/
\// A /S
A
A
S
A
S
A

T DMR

'4— 100ns MAX

REF)
NOTES:

1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER INPUTS
AND BUS RECEIVER OUTPUTS.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T=BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

3. BUS DRIVER QUTPUT AND BUS RECEIVER INPUT SIGNAL NAMES
INCLUDE A “B"" PREFIX.

MR-3690

Figure 4-8

DMA Request/Grant Bus Cycle Timing

Interrupts can be caused by LSI-11 bus options and can also originate in the processor. Interrupts originating in the processor are called “traps” and are caused by programming errors, hardware errors, special instructions, and maintenance features. The following are the LSI-11 bus signals used in interrupt
transactions.
BIRQ4 L
BIRQ5 L
BIRQ6 L
BIRQ7 L

Interrupt request priority level 4
Interrupt request priority level 5
Interrupt request priority level 6
Interrupt request priority level 7

BIAKI L
BIAKO L

Interrupt acknowledge input
Interrupt acknowledge output

BDAL<15:00> L

Data/address lines

BDIN L
BRPLY L

Data input strobe
Reply

4.5.1
Device Priority
The LSI-11 bus supports the following two methods of determining device priority.

Distributed arbitration — Priority levels are implemented on the hardware. When devices of
equal priority level request an interrupt, priority is given to the device electrically closest to
the processor.

Position-defined arbitration — Priority is determined solely by electrical position on the bus.
The device closest to the processor has the highest priority while the device at the far end of
the bus has the lowest priority.

The KDF11-BA uses both methods — distributed arbitration, with four levels of priority, and positiondefined arbitration within each level. Interrupts on these priority levels are enabled /disabled by bits in
the processor status word (PS<<07:05>). Single-level interrupt (position-defined) devices that interrupt
on BIRQ4 can also be used in KDF11-BA systems but must be placed in a bus slot following the last
bus slot in which a position-independent device is installed.
4.5.2

Interrupt Protocol
Interrupt protocol has three phases: the interrupt request phase, the interrupt acknowledge and priority
arbitration phase, and the interrupt vector transfer phase. The operations performed by the processor
and interrupting device are shown in Figure 4-9. Interrupt protocol timing is shown in Figure 4-10.

The interrupt request phase begins when a device meets its specific conditions for interrupt requests;
for example, when the device is “ready,” “done,” or when an error has occurred. The interrupt enable
bit in a device status register must be set. The device then initiates the interrupt by asserting the interrupt request line(s). BIRQ4 L is the lowest hardware priority level and is asserted for all interrupt
requests for compatibility with previous LSI-11 processors. The level at which a device is configured
must also be asserted. (A special case exists for level-7 devices that must also assert level 6.) The interrupt request line remains asserted until the request is acknowledged.

Interrupt Level

Lines Asserted by Device

BIRQ4 L

BIRQ4 L, BIRQS5 L

6
7

BIRQ4 L, BIRQ6 L
BIRQ4 L, BIRQ6 L, BIRQ7 L

During the interrupt acknowledge and priority arbitration phase, the KDF11-BA will acknowledge in-

terrupts under the following conditions.

The device interrupt priority is higher than the current priority level stored in PS<<07:05>.

The processor has completed instruction execution and no additional bus cycles are pending.

The processor acknowledges the interrupt request by asserting TDIN and, 225 ns (minimum) later,
asserting TIAKO. The device electrically closest to the processor receives the acknowledge on its
RIAKI bus receiver.

On the leading edge of RDIN, each bus option capable of requesting interrupts decides whether to
accept or to pass on the RIAKI signal. A device that does not support position-independent, multilevel
interrupts will accept RIAKI if it is requesting an interrupt when RDIN asserts. A device that does
support position-independent, multilevel interrupts accepts RIAKI if it is requesting an interrupt and if
there is no higher-priority request pending when RDIN asserts. This decision must be clocked into a
flip-flop, which settles within 150 ns of TDIN.

DEVICE

PROCESSOR

INITIATE REQUEST
/

—

——*°

ASSERT BIRQ L

STROBE INTERRUPTS

e ASSERT BDIN L

—_

‘

RECEIVE BDIN L

e STORE “INTERRUPT SENDING”

‘

IN DEVICE

GRANT REQUEST

——_

PAUSE AND ASSERT BIAKO L

\ \
\

RECEIVE BIAKI L

e RECEIVE BIAKI L AND INHIBIT
BIAKO L

e PLACE VECTORON BDAL <15:00> L
e ASSERT BRPLY L

__e NEGATEBIRQL
—

RECEIVE VECTOR & TERMINATE
REQUEST

o INPUT VECTOR ADDRESS
o« NEGATE BDIN L AND BIAKO L
\

COMPLETE VECTOR TRANSFER

e REMOVE VECTOR FROM BDAL BUS
NEGATEBRPLY L

PROCESS THE INTERRUPT
e SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK

e LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION
e EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE
MR-1182

Figure 4-9

Interrupt Request/Acknowledge Sequence

4-17

INTERRUPT LATENCY

MINUS SERVICE TIME

TIRQ

150ns MIN

—*I

j&—

R DIN

R 1AKI

T RPLY
—’l 125ns MAX
T DAL

()

R SYNC

(UNASSERTED)

R BS7

(UNASSERTED)

== 100ns MAX

|@—

VECTOR

(4)

NOTES:

1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER INPUTS
AND BUS RECEIVER OUTPUTS.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T=BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT SIGNAL NAMES
INCLUDE A “B" PREFIX.

4, DON'T CARE CONDITION.
MR-1183

Figure 4-10

Interrupt Protocol Timing

Devices that support position-independent, multilevel interrupts assert from one to three IRQ lines
when requesting an interrupt. Table 4-4 presents the IRQ lines a device at each level must assert in
order to request an interrupt, and the lines it must monitor to determine whether a higher-priority device is requesting an interrupt.
Table 4-4

Position-Independent, Multilevel Device Requirements

Interrupt Level

IRQ Lines Asserted

IRQ Lines Monitored

4
5
6
7

TIRQ4
TIRQ4, TIRQS5
TIRQ4, TIRQ6
TIRQ4, TIRQ6, TIRQ7

RIRQS5, RIRQ6
RIRQ6
RIRQ7

During the interrupt vector transfer phase, the responding interrupt device receives RIAKI and then
asserts TRPLY. The vector address must be stable at TDAL<08:02> 125 ns (maximum) after
TRPLY is asserted. The processor receives the assertion of RRPLY, and 200 ns (minimum) later it
inputs the vector address and negates both TDIN and TIAKI. The interrupting device negates TRPLY
after the negation of RIAKI and removes the vector address from TDAL <<08:02> 100 ns (maximum)
after TRPLY negates. Since vector addresses are constrained to be between 000 and 7743, none of the
remaining TDAL lines are used.
4.5.3

4-Level Interrupt Configurations

Users who have high-speed peripherals and desire better software performance can use the 4-level interrupt scheme. Both position-independent and position-dependent configurations can be used with the 4level interrupt scheme.

The position-independent configuration is shown in Figure 4-11. This configuration allows peripheral
devices that use the 4-level interrupt scheme to be placed in the backplane in any order. These devices
must send out interrupt requests and monitor higher-level request lines, as described in Paragraph
4.5.2. The level-4 request is always asserted by a requesting device, regardless of priority, to allow com-

patibility if an LSI-11 or LSI-11/2 processor is in the same system. If two or more devices of equally

high priority request an interrupt, the device physically closest to the processor will win arbitration.
Devices that use the single-level interrupt scheme must be modified or placed at the end of the bus for
|

LEVEL4 | BIAK

DEVICE

t BIRQ 4 (LEVEL 4 INTERRUPT REQUEST) l

LEVEL6

DEVICE

|BIAK

LEVELS | BIAK

DEVICE

7
LEVEL

BIAK (INTERRUPT ACKNOWLEDGE)

KDF11

arbitration to function properly.

DEVICE

BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)
BIRQ
6 (LEVEL 6 INTERRUPT REQUEST)

BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)
MR-2888

Figure 4-11

Position-Independent Configuration

4-19

The position-dependent configuration is shown in Figure 4-12. This configuration is simpler to implement, with the following constraint, however. Peripheral devices must be ordered so that the highestpriority device is located closest to the processor with the remaining devices placed in the backplane in
decreasing order of priority. With this configuration each device must only assert its own level and level
4 (for compatibility with an LSI-11 or LSI-11/2). Monitoring higher-level request lines is unnecessary.
Arbitration is achieved through the physical positioning of each device on the bus. Single-level interrupt devices on level 4 should be positioned last on the bus.

KDF11
Y

BIAK (INTERRUPT ACKNOWLEDGE)

LEVEL7

® DEVICE

|Blak | LEVEL®6
DEVICE

|BIak | LEVELS5
DEVICE

|BIAK | LEVEL4
® DEVICE

BIRQ 4 (LEVEL 4 INTERRUPT REQUEST)

BIRQ5 (LEVEL5 INTERRUPT REQUEST)

BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)

BIRQ7 (LEVEL7 INTERRUPT REQUEST)

v
MR-2889

Figure 4-12

4.6

Position-Dependent Configuration

CONTROL FUNCTIONS

The following LSI-11 bus signals provide system control functions.
BREF L
BHALT L
BINIT L
BPOK H
BDCOK H
BEVENT L
4.6.1

Memory refresh
Processor halt
Initialize
Power OK
DC power OK
External event interrupt request

Memory Refresh

If BREF is asserted during the address portion of a bus data transfer cycle, it causes all dynamic MOS
memories to be addressed simultaneously. The sequence of addresses required for refreshing the memories is determined by the specific requirements of each memory. The complete memory refresh cycle
consists of a series of refresh bus transactions. (A new address is used for each transaction.) The entire
cycle must be completed within 2 ms. Multiple-data transfers by DMA devices must be avoided since
they could delay memory refresh cycles. The KDF11-BA does not perform memory refresh.
4.6.2

Halt

Assertion of BHALT L stops program execution and forces the processor unconditionally into console
ODT mode. The processor does not assert the BHALT L bus line when it comes to a programmed
HALT.
4.6.3

Initialization

Devices along the bus are initialized when BINIT L is asserted. The processor asserts the BINIT L
signal under the following conditions.
1.

During a power-down sequence.

During a power-up sequence.

During the execution of a RESET instruction.

4-20

After detection of a G character in ODT mode (if the processor features an ODT mode and a
G command within it), and before execution of the code starting at the address that preceded
the G command.

4.6.4

Power Status

Power status protocol is controlled by two signals, BDCOK H and BPOK H. These signals are driven
by an external device (usually the power supply) and are defined as follows.
4.6.4.1 BDCOK H - The assertion of this line indicates that dc power has been stable for at least 3 ms.
Once asserted this line remains asserted until the power fails.

4.6.4.2 BPOK H - The assertion of this line indicates that there is at least an 8-ms reserve of dc power
and that BDCOK H has been asserted for at least 70 ms. Once BPOK H has been asserted, it must

remain asserted for at least 3 ms.

The negation of this line indicates that power is failing and that only 4 ms of dc power reserve remains.
The negation of this line during processor operation initiates a power-fail trap sequence.
4.6.4.3

Power-Up - The following events occur during a power-up sequence.

Logic associated with the power supply negates BDCOK H during power-up and asserts
BDCOK H 3 ms (minimum) after dc power is restored to voltages within specification.

The processor asserts BINIT L after receiving nominal power and negates BINIT L 0 ns
(minimum) after the assertion of BDCOK H.

Logic associated with the power supply negates BPOK H during power-up and asserts BPOK
H 70 ms (minimum) after the assertion of BDCOK H. If power does not remain stable for 70
ms, BDCOK H will be negated; therefore, devices should suspend critical actions until
BPOK H is asserted.

BPOK H must remain asserted for a minumum of 3 ms. BDCOK H must remairi asserted 4

ms (minimum) after the negation of BPOK H.

The timing diagram for the power-up/power-down sequence is shown in Figure 4-13.

]

)

Ons

—a

MIN

\
e—— 3ms MIN

B POK H

3ms

MAX

- 70msMIN fe

BDCOK H

lc— 8-20uS

MAX

4ms MIN —

4—1 70ms MIN L—

—-»‘ m e

— 5uS MIN

crom [
|

e —»] 185 L—

[‘—

s
POWER UP

SEQUENCE

NORMAL

‘_POWER TM

POWER DOWN

SEQUENCE

POWER UP

SEQUENCE

NORMAL

i‘“POWER >

NOTE:

ONCE A POWER DOWN SEQUENCE IS STARTED,
IT MUST BE COMPLETED BEFORE A POWER UP
SEQUENCE IS STARTED.
MR-6032

Figure 4-13

Power-Up/Power-Down Timing

4-21

4.6.4.4

Power-Down — The following events occur during a power-down sequence.

If the ac voltage to a power supply drops below 75% of the nominal voltage for one full line
cycle (15-24 ms), BPOK H is negated by the power supply. Once BPOK H is negated, the
entire power-down sequence must be completed.
A device that requested bus mastership before the power failure that has not become bus
master should maintain the request until BINIT L is asserted or the request i1s acknowledged
(in which case regular bus protocol is followed).

Processor software should execute a RESET instruction 3 ms (minimum) after the negation
of BPOK H. This asserts BINIT L for from 8 to 20 us. Processor software executes a HALT
instruction immediately following the RESET instruction.

BDCOK H must be negated a minimum of 4 ms after the negation of BPOK H. This 4 ms
allows mass storage and similar devices to protect themselves against erasures and erroneous
writes during a power failure.

4.6.5

The processor asserts BINIT L 1 us (minimum) after the negation of BDCOK H.

DC power must remain stable for a minimum of 5 us after the negation of BDCOK H.

BDCOK H must remain negated for a minimum of 3 ms.
BEVENT L

The BEVENT L signal is an external line clock interrupt request to the processor. When BEVENT L 1s
asserted, the processor internally assigns location 100g as the vector address for the BEVENT service
routine. Because the vector is internally assigned, the processor does not execute the protocol for reading-in the interrupt vector address as is the case for other external interrupt requests.
4.7 BUS ELECTRICAL CHARACTERISTICS
This paragraph contains information about the electrical characteristics of the LSI-11 bus.
4.7.1

Signal-Level Specification

Input Logic Levels

TTL logical low:
TTL logical high:

0.8 Vdc (maximum)
2.0 Vdc (minimum)

Output Logic Levels
TTL logical low:

0.4 Vdc (maximum)

TTL logical high:

2.4 Vdc (minimum)

4.7.2 AC Bus Load Definition
AC bus loading is the amount of capacitance a module presents to a bus signal line. This capacitance is
measured between each module signal line and ground. AC bus loading is expressed in ac unit loads
where each unit load is defined as 9.35 pF.
4.7.3

DC Bus Load Definition

DC bus loading is the amount of leakage current a module presents to a bus signal line. A dc unit load
is defined as 105 pA flowing into a module device when the signal line is in the unasserted (high) state.

4-22

4.7.4

120 Q LSI-11 Bus

The electrical conductors interconnecting the bus device slots are treated as transmission lines. A uniform transmission line, terminated in its characteristic impedance, will propagate an electrical signal
without reflections. Insofar as bus drivers, receivers, and wiring connected to the bus have finite resistance and nonzero reactance, the transmission line impedance becomes nonuniform, and thus introduces distortions into pulses propagated along it. Passive components of the LSI-11 bus (such as
wiring, cabling, and etched signal conductors) are designed to have a nominal characteristic impedance
of 120 Q.

The maximum length of the interconnecting cable in multiple-backplane systems (excluding wiring
within the backplane) is limited to 4.88 m (16 ft).

NOTE
The KDF11-BA processor (as well as all standard DIGITAL-supplied LSI-11 interfaces) connects to the bus via special drivers and receivers, described in Paragraphs 4.7.5 and
4.7.6.

4.7.5

The KDF11-BA processor provides resistive
(120 Q) pull-up (on all bused lines) to 3.4 Vdc
for this wired-OR interconnecting scheme.

Bus Drivers

Devices driving the 120 © LSI-11 bus must have open collector outputs and meet the specifications that
follow.

DC Specifications (These conditions must be met at worst-case supply voltage, temperature, and input
signal levels.)
Vcce can vary from 4.75 V to 5.25 V.

Output Jow voltage when sinking 70 mA of current: 0.7 V (maximum).
Output high leakage current when connected to 3.8 Vdc: 25 A (even if no power is applied
to them, except for BDCOK H and BPOK H).

AC Specifications

Bus driver output pin capacitance load: Not to exceed 10 pF.
Propagation delay: Not to exceed 35 ns.

Driver skew (difference in propagation time between slowest and fastest bus driver): Not to
exceed 25 ns.

Rise/fall times: Transition time from 10% to 90% for positive transition, and from 90% to
10% for negative transition, must be no faster then 5 ns.

4-23

4.7.6

Bus Receivers

Devices that receive signals from the 120 Q LSI-11 bus must meet the following requirements.
DC Specifications (These conditions must be met at worst-case supply voltage, temperature, and output
signal conditions.)
Vcc can vary from 4.75 V to 5.25 V.

Input low voltage: 1.3 V (maximum).

Input high voltage: 1.7 V (minimum).

Maximum input leakage current when connected to 3.8 Vdc: 80 uA with Ve between 0.0
and 5.25 V.
AC Specifications

Bus receiver input pin capacitance load: Not to exceed 10 pF.
Propagation delay: Not to exceed 35 ns.

Receiver skew (difference in propagation time between slowest and fastest receiver): Not to
exceed 25 ns.
4.7.7

Bus Termination

The 120 LSI-11 bus must be terminated at each end by an appropriate resistive termination. A pair of
resistors in series from -+ 5.0 V to ground is used to establish a voltage for each bidirectional line when
that line is not being driven (negated). The parallel impedance of this pair of resistors i1s 120 . The
terminating resistors are shown in Figure 4-14. The KDF11-BA contains terminating resistor networks
in 16-pin dual-in-line packages to provide the 120 Q terminations for the data/address, synchronization,
and control lines at the processor end of the bus.

Some system configurations do not require terminating resistors at the far end of the bus. If the system
configuration does require such termination, it is typically provided by a M9404-YA cable connector
module. Rules for configuring single- and multiple-backplane systems are described in Paragraphs 4.8.1
and 4.8.2.

+5V

18082
12082

BUS LINE
TERMINATION

39082

MR 6033

Figure 4-14

Bus Line Termination

4-24

4.7.8

Bus Interconnection Wiring

This paragraph contains the electrical characteristics of the bus interface. The bus interface for the
module connectors is provided by one, two or three backplanes, depending on the system configuration.
Since each backplane contains 9 slots, a system may have a maximum of 27 module interfaces to the
bus.

4.7.8.1

Backplane Wiring — The wiring that interconnects all device interface slots on the LSI-11 bus

must meet the following specifications.

The conductors must be arranged so that each line exhibits a characteristic impedance of 120
Q (measured with respect to the bus common return).

Crosstalk from a pulse-driven line to an undriven line to which a constant 5 V is applied must
be less than 5% of the 5 V. Note that worst-case crosstalk is manifested by simultaneously
driving all but one signal line and measuring the effect on the undriven line.

DC resistance of a bus segment signal path, as measured between the near-end terminator
and far-end terminator modules (including all intervening connectors, cables, backplane wiring, connector-module etch, etc.) must not exceed 2 ().

DC resistance of a bus segment common return path, as measured between the near-end terminator and far-end terminator modules (including all intervening connectors, cables, backplane wiring, connector-module etch, etc.) must not exceed an equivalent of 2 Q per signal
path. Thus, the composite signal return path dc resistance must not exceed 2 Q divided by 40
bus lines, or 50 mQ. Note that although this common return path is nominally at ground potential, the conductance must be part of the bus wiring; the specified low-impedance return
path must be provided by the bus wiring as distinguished from common system or power
ground path.

4.7.8.2 Intrabackplane Bus Wiring — The wiring that interconnects the bus connector slots within one
contiguous backplane is part of the overall bus transmission line. Due to implementation constraints,
the nominal characteristic impedance of 120 Q may not be achievable. Distributed wiring capacitance
in excess of the amount required to achieve the nominal 120 Q impedance may not exceed 60 pF per
signal line per backplane.

4.7.8.3

Power and Ground — Each bus interface slot has connector pins assigned for the following dc

voltages.

+5 Vdc

Three pins, 4.5 A (maximum) per bus device slot

+12 Vdc

Two pins, 3.0 A (maximum) per bus device slot)

Ground

Eight pins, shared by power return and signal return

The maximum allowable current per pin is 1.5 A. The +5 Vdc must be regulated to =5% and the
maximum ripple should not exceed 100 mV peak-to-peak. The 412 Vdc must be regulated to =3% and
the maximum ripple should not exceed 200 mV peak-to-peak.

NOTE
Power is not bused between backplanes on any interconnecting L.SI-11 bus cables.

4-25

4.7.8.4

Maintenance and Spare Pins

Maintenance Pins — There are four M SPARE pins per bus device slot assigned to maintenance (AKI,
AL1, BK1, BL1). The maintenance pins on the basic LSI-11 system are not bused from module to
module. Instead, at each bus device slot, the maintenance pins are shorted together as pairs. These pins
must be shorted together for some modules to operate. This allows a module to use these pins during
initial testing as two separate points. This feature is used by DIGITAL for manufacturing tests only.
Spare Pins — Spare pins are allocated on the backplane as follows.

S SPARES - These four pins, AE1, AHI1, BHI1, AF1 (with the exception of AF1 in slot 1),
are reserved for the particular use of a module or set of modules. They may be used as test
points or for intermodule connection. Appropriate wires must be added for intermodule communication since these pins are not connected in any way. The processor uses AF1 in slot 1
as an output pin for the SRUN signal. S SPARE lines cannot be used as bus connections.

P SPARES - These two pins, AUl and BUI are similar to the S SPARE pins except that
they are located in a manner that causes dc voltages to appear on them if a module is inserted
backwards. Use of these pins is not recommended.

4.8

SYSTEM CONFIGURATIONS

LSI-11 bus systems can be divided into two types. The first type comprises those systems that use only
one backplane, the second type comprising those systems that use multiple backplanes. Two sets of
rules must be followed when configuring a system to accommodate the different electrical characteristics of the two types of systems. These rules are listed in Paragraphs 4.8.1 and 4.8.2.
Three characteristics of each component in an LSI-11 bus system must be known before configuring
any system:

Power consumption — The total amount of current drawn from the +5 Vdc and +12 Vdc

power supplies by all modules in the system.

AC bus loading — The amount of capacitance a module presents to a bus signal line. AC
loading is expressed in ac unit loads, where one ac unit load equals 9.35 pF of capacitance.

DC bus loading — The amount of dc leakage current a module presents to a bus signal when
the line is high (undriven). DC loading is expressed in terms of dc unit loads, where one dc

unit load equals 105 uA (nominal).

Power consumption, ac loading, and dc loading specifications for each module are included in the Mi-

crocomputer Interfaces Handbook.

NOTE

The ac and dc loads and the power consumption of
the processor module, terminator module, and backplane must be included in determining the total bus
loading of a backplane.

4.8.1

Rules for Configuring Single-Backplane Systems

The following rules apply only to single-backplane systems. Any extension of the bus off the backplane
is considered a multiple-backplane system and must be configured accordingly. A single-backplane configuration diagram is shown in Figure 4-15.

4-26

The bus can accommodate modules that have up to 20 ac loads (total) before an additional
termination is required. The processor has on-board termination for one end of the bus. If
more than 20 ac loads are included, the other end of the bus must be terminated with 120 Q.

A terminated bus can accommodate modules comprising up to 35 ac loads (total).
The bus can accommodate modules up to 20 dc loads (total).
The bus signal lines on the backplane can be up to 35.6 cm (14 in) long.
BACKPLANE WIRE
35.6 CM (14 IN) MAX

L.
I

|
>

{{
)

12052 OR

22052

&
=

ONE

LOAD

UNIT

3.4V

35 AC LOADS

20 DC LOADS

OPTIONAL
1206

UNIT

+
1~

3.4V

TERM

PROCESSOR

MR 6034

Figure 4-15
4.8.2

Single-Backplane Configuration

Rules for Configuring Multiple-Backplane Systems

Multiple-backplane systems may contain a maximum of three backplanes. A configuration diagram for

a multiple-backplane system is shown in Figure 4-16.
1.

The signal lines on each backplane can be up to 25.4 cm (10 in) long.

Each backplane can accommodate modules that have up to 20 ac loads (total). Unused ac
loads from one backplane may not be added to another backplane if the second backplane
loading will exceed 20 ac loads. It is desirable to load backplanes equally, or with the highest
ac loads in the first and second backplanes.

DC loading of all modules in all backplanes cannot exceed 15 loads (total).
The first backplane must have an impedance of 120 Q (obtained via the processor module).
The second backplane is terminated by 120 Q resistor networks contained on the cable connector inserted in the third backplane.

The cables connecting the backplanes must observe the following rules.
a.

The cable(s) connecting the first two backplanes must be 61 cm (2 ft) or greater in
length.

The cable(s) connecting the second backplane to the third backplane must be 22 cm (4
ft) longer or shorter than the cable(s) connecting the first and second backplanes.

The combined length of both cables must not exceed 4.88 m (16 ft).

The cables used must have a characteristic impedance of 120 €.

4-27

BACKPLANE WIRE

35.6 CM

(14 IN)

MAX

CABLE

4§

1208

ONE

UNIT
LOAD

_3.4 V

—

~
20 AC LOADS
MAX

PROCESSOR
|

BACKPLANE WIRE

[

25.4 CM (10 IN) MAX

((
))

ONE

LOAD

UNIT

CABLE

UNIT
CABLE

“

MAX
20 AC LOADS

ADDITIONAL
CABLES AND

BACKPLANE WIRE

BACKPLANE

25.4 CM (10 IN) MAX

(

)}

ONE

CABLE/

ONE

UNIT
LOAD

12082
3.4V

TERM

20 AC LOADS
MAX
NOTES:

1. TWO CABLES (MAX) 4.88 M (16 FT) (MAX)
TOTAL LENGTH.

2.20 DC LOADS TOTAL (MAX).
MR-6035

Figure 4-16

4.8.3

Multiple-Backplane Configuration

Power Supply Loading

Total power requirements for each backplane can be determined by obtaining the total power requirements for each module in the backplane. Obtain separate totals for +5 V and +12 V power. Power
requirements for each module are specified in the Microcomputer Interfaces Handbook.

Do not attempt to distribute power via the LSI-11 bus cables in multiple-backplane systems. Provide
separate, appropriate power wiring from each power supply to each backplane. Each power supply
should be capable of asserting BPOK H and BDCOK H signals according to bus protocol; this is required if automatic power-fail /restart programs are implemented, or if specific peripherals require an
orderly power-down halt sequence. The proper use of the BPOK H and BDCOK H signals is strongly
recommended.

4-28

CHAPTER 5

FUNCTIONAL DESCRIPTION

5.1

INTRODUCTION

This chapter describes the control logic and data flow of the KDF11-BA. Figure 5-1 (Sheets 1 and 2) is
a functional block diagram that shows the major logical subunits of the KDF11-BA and their relation to
the LSI-11 bus and the three internal processor buses. The three internal buses are the chip/data address lines (CDALSs), the microinstruction bus (MIB), and the internal data/address lines (IDALs).
The functions of the logic subunits are described at the block diagram level. The block diagrams may
be used in conjunction with the KDF11-B Field Maintenance Print Set to locate the detailed circuit
logic for the logic subunits. Each block in a diagram contains the letter K followed by a number I
through 10. This alphanumeric designator refers to the specific drawing number of the KDF11-B Field
Maintenance Print Set that contains the detailed circuit logic for that block.

The KDF11-BA central processor unit is contained on two LSI chips (control and data) which reside on
a single 40-pin carrier. The optional memory management unit (MMU) is contained on one LSI chip,
which also resides on a 40-pin carrier. The KDF11-BA has sockets for these two carriers and three extra
sockets for the commercial instruction set (CIS) or floating-point (FP) options. The control and data
chips, the MMU chip, and the optional CIS and FPP (floating-point processor) chips are referred to in
this discussion as the F11 chip set. The F11 chips communicate among themselves and with external
KDF11-BA logic over the MIB <15:00> and CDAL <21:00> bus. KDF11-BA logic interfaces the
F11 chip set with the internal IDAL <<15:00> bus and the external LSI-11 bus. The KDFI11-BA bootstrap and diagnostic line clock and serial-line units reside on the IDAL bus. Memory and additional
peripherals interface with the LSI-11 bus. Bidirectional interfaces (CDAL/IDAL transceivers and
CDAL/BDAL transceivers) on the KDF11-BA module connect the CDAL <21:00> bus with the
IDAL < 15:00> bus and with the LSI-11 data/address lines BDAL <21:00>.

KDF11-BA logic supporting the F11 chip set includes the master clock control logic, MIB decode logic,
fixed data logic, service logic, reset logic and ODT logic. Logic pertaining to the LSI-11 bus includes
the bus control logic, bus synchronizer and the CDAL/BDAL transceivers. Logic pertaining to the
IDAL bus peripherals includes the bus control logic, CDAL/IDAL transceivers, the IDAL address
decode, bootstrap/diagnostic and line clock logic, the console and second SLU logic, the baud rate generator, and the —12 V charge pump logic.
5.2

DATA CHIP

"The data chip contains the PDP-11 general registers, the processor status word (PS), several working
registers, the arithmetic and logic unit (ALU), and conditional branching logic. The data chip does the
following.

Performs all arithmetic and logical functions.

Handles all data and address transfers with the LSI-11 bus (except relocation, which is han-

dled by the MMU; see Paragraph 5.4).

Generates most of the signals used for interchip communication and external system control.

5-1

LV,o_mAfi%ll1mnomals!a7zeSHISAmItFwO_SwNmVHLadvalN3Tvai1vad<0:1Z>H dIHD)10Vi8wH<0'sl>

A.Evom—wv«ewasSREE?<0:51>1va9dHTYNOILAO_{-_H<o0:51v>val()

2(vza0)8HA10A8H3IZINOHONAS| 901LDASO0N|d2311900A7D®T9O1HNL3NOdD0S2T3VdNDIS <9L:1Z>d1ivHaod5H10g 32a10~99037d_ < -

*(D(a(1Z19dNv98VS)))Y©&-o00RLT12E002LAMd0LEvv14I-hT1dLHEg8:7TNEsngE21R9I0£e7T1ER IU3noHaOwHiSLT-VTYNDRIS v1931£95037y dIHD|1Sd <<H .<@ > TvaD0:20-></0:80>H< B(dd1)0—109 1/1TVHdVHN:OILdO a. v

(e
2¥,0Rl A
>0

2Ind1][-S VE-T1IANJ0sa01d194S)TJO(T

Ivai/vao
SL8G-HW

P()a((D—A(zos=~MVP¢eCCL16EevN1IHNd_l5Nmv)A8VG@lN9iW))M)E(aW—Oeg3o2©©5¥L)0a5AIN511vLTA1vv3=DGTI0v/JaN0N<aa—av4aVgI3I7wvgJggodmE1Ov2asaDgav81N3e¢13LoT7L7sL1gp68u4g1Hl_9zst«H02emESLN)1ivasgS~/v¥ao41D3§YMdTav10a71yvHaaoln_Lv1d5"]1va87d—NdGi30C4NL4LSS1KVd<VNz0A1O84D08dgVI>Hi7D0dSi0no|v -<<SoRY <<00::G11ZL>>L1N1vddav.IIaadLHH0dIDMAHH3H1L1SSd40H(9L)HH¥T9HaM©[mdVLvST1SadOdHI1aHl0HI3vLo1aOA2NQx9IOi_vFD4O|SNV9_[>H1lNu1H3yt0YoSo3Il04Ia-S8MvXaOl1<d94v0<4d010:N~6:S<<_.03<5N'1ZO>LI>LHdHO<SAB
((tLdH8Y)oTNaAg |HTIDINIAT@0@0

1(A—(zZ11\3988E)0—oeo5!1v9v—:2a1aMgg7dBo0p791:z0 k TvayHZHlolsg Ol o N3Ival d)IHWD dvIwa<0\A n:.G1>H

(¢dv o 7Sgg ¢

A..|l._1If(l3d¢.mY_O3V.m9v.'Ho)

5-2

OJ_M_9190183B
Z1M40

[

naNsoD3s IS ef

/a1UMy<07 1088> SIHOLIMS

J1SONDVIC

NaO8SYWOH

5-3

NOILVHNOI4NOD

OG—A+pV—1Ada1SIdnSd

a1 UMY IH 431S193Y

1AV-1I0s 0 01d 19 4S) T JO(T

1
v
d
l
<
9
0
>
H
I
N
I
T
YD 1N3IAT

43151934 | HAVMS ay

H <00:G91>1vdal

J1LSONDVIA

<TH0v:aG1l>

2In31q [-G

9(8S-HW

wHV<107:£0>

8 L
a1 49d 431S193Y HOd <0 :50>'<80:E1>

300033

1val0:G1>SH< varay SHav V]H<10:£0>

aTvdl<0l1:VG0<>0'<:8£0:0€>LHl>H 3397Vv0dSNOD ©S|ieWOHY)

io.@<0:G1>H 1val<0d:y/0d>MHY-NO"ILNVIHoINOI4NOD_.-Io/oul.l_
al Havi

Tval

31dm/avay

2w>m@1P

A typical microinstruction cycle starts when the data chip receives a 16-bit microinstruction from the
control chip on the time-multiplexed, bidirectional MIB. During the first half of the cycle (phase time)
the register file is precharged, and the selected register(s) are read and sent part way through the ALU
chain (i.e., operands are latched into the propagate and generate latches). Also during the first half of
the cycle, control information is decoded from the microinstruction and output on the MIB for use by
other chips and external logic. During the second half of the cycle (phase-bar time) the ALU operation
is completed and the result is written into the appropriate register.

Output operations occur during the first half of the cycle when the contents of the selected source register are bused around the ALU logic directly to the output buffers. Input data is strobed into the data
chip during the first half of the cycle, although it is not written into the register file until the second
half.

5.3

CONTROL CHIP

The control chip contains the microprogram sequence logic and 552 words of microprogram storage in
programmable logic arrays (PLAs) and read-only memory (ROM) arrays.
During the course of a normal microinstruction cycle, the control chip accesses the appropriate microinstruction in the PLA or ROM, sends it along the MIB to the data and MMU chips for execution, and
then generates the address for the next microinstruction to be accessed. The next address is constructed
from either a next-address field associated with the current microinstruction or, if a microprogrammed
branch is to be executed, the target address contained within the microinstruction itself. The control
chip operation is pipelined for better performance so that the next microinstruction is being accessed
while the current one is being executed. This next address is then used in conjunction with various internal status and external service inputs to determine the microprogram sequence. The control chip accesses only its local storage. However, multiple chips (up to 32) can be cascaded with external buffering
to provide additional microprogram storage.

Chip Select (CSEL) — CSEL is an open collector line with a pull-up resistor. CSEL is routed to all F11
chips on the board except the MMU. The active control chip holds the line low. If a nonexistent control
chip is selected by the microcode, the line is pulled high. This causes a control chip error and a trap to
location 10g.

5.4

MMU CHIP

The MMU chip serves two purposes: it provides the memory management function and storage for the
FP11 floating-point accumulators and status registers. This chip provides dual mode (user and kernel)
address relocation of 22 bits. Sixteen-bit virtual addresses are received from the data chip via the
CDAL bus, relocated to the appropriate 18- or 22-bit physical address, and then sent on the CDAL bus
to replace the original virtual address for transmission to the external LSI-11 bus. The MMU chip contains the status register and active page registers (PAR/PDR register pairs), as well as access protection and error detection capability. The MMU chip also provides the 36 16-bit registers needed for
operand storage, scratchpad areas, and status information storage during floating-point operation.

The MMU chip is controlled by information received on the microinstruction bus (MIB) from the data
chip and control chip and by several discrete control inputs. Complete details of memory management
capabilities are described in Chapter 8.
5.5

BASE TIMING LOGIC

The base timing for the KDF11-BA is performed by the master clock control logic. Figure 5-2 shows
the major logic blocks of the master clock control, the outputs of the master clock control logic, and the
interface to the KDF11-BA logic.

IDAL

¢ IAD SEL
H

DECODE

ADR

]

MMU

CHIP
K4

FIXED

DATA

RESET

LOGIC

!'V”V'U RPLY H

75NS

375

I
osc

PBT NXT L

TIME

SHORT PT H

—>1c

DRIVER

PHASE (O) H

’

|
l
=

CONTRO

LOGIC

I
i

PBT5 (1) H

TIME
SHIFT

RRPLY2 H

PBT6 (N
H |
—————— .,'

CLK CLR

>
PBT3 (1) H |

PBT2 (1)H _ 4
*|

MCENB3 H ]

PHASE (1) L

—

26.666 MHZ

l_,

DOUT CYC H

0SC LOGIC

|
—~

RRPLY3 (0) H

CONTROL

p T4 (1) H =i

PT2 (1) H

PT3 (1) H

PT2 (1) H

— ngET

LOGIC

RD IDAL (O) H

RDCOK3 (0) H

PTS () H

PT3 (1) H

~ one

PAUSE

RRPLY3 (1) H .|

—

DIN CYC H
PHASE
MMU RPLY H | TIME
PT4 (1) H

OSC H

0SC H

LAD CYC (1) H

GT BDAL3 (0) H

[

l
PBT5 (1) H _ g

BAR

1
I

PTCLRL s
|

PBT2 (1) H

BUS

NIZER

PBT6 (0) H

SYNCHRO-

PBT CLR L

PT2 (1) H

PHASEA (1) L _ g

—0

— e

l—d

PT3 (1) H

CONTROL

LOGIC

PHASEA (1) H

| Loclc

| MED PT H

{ bouTcYCH

DECODE

CHIP CLK
B |
I

~]_PHASE (1) H
FF

PHASE

DRIVER

HASE

PHASE

g ENB RST H

CHIP CLK A _§

-FDIN ENB H

CHIP
CLK

. RELCYC (0) H

MIB

TTLPHASE L

CLK CLR

|
]

PHASE (0) H )

MASTER CLOCK CONTROL

]

MR-5877

Figure 5-2

Base Timing Interface

A 26.666 MHz crystal oscillator toggles a flip-flop whose buffered output (OSC H) drives the timing
logic for the F11 chip set, the control logic for the LSI-11 bus, and the IDAL bus. OSC H has a period
of 75 ns and a half period of 37.5 ns.
The chip clock driver uses the PHASE (1) H flip-flop output to produce the +12 V F11 chip set clock

signals (CHIP CLK A and CHIP CLK B). Each chip set clock cycle consists of a phase time [PHASE
(1) H set] and a phase-bar time [PHASE (1) H clear]. The F11 chip set is semistatic and loses information if it remains in phase-bar time (PBT) for longer than 500 ns. The F11 chip set can remain in phase
time (PT) indefinitely.

5-5

Two shift registers [PT2 (1) H through PT5 (1) H and PBT2 (1) H through PBT6 (1) H] operate as
state machines during phase time and phase-bar time, respectively. If PHASE (1) H 1s set, but PT2 (1)
H through PT5 (1) H are clear, the logic is in phase time one. If PHASE (1) H and PT2 (1) H are set,
but PT3 (1) H through PT5 (1) H are clear, the logic is in phase time two. Similarly, if PHASE (1) H is
clear and PBT2 (1) H through PBT5 (1) H are clear, the logic is in phase-bar time one. If PBT2 (1) H
through PBT4 (1) H are set, but PHASE (1) H and PBTS5 (1) H are clear, the logic is in phase-bar time
four.

The PHASE (1) H flip-flop and the two shift registers are clocked on the leading edge of OSC (1) H.
When PHASE (1) H is clear, the logic typically advances from one phase-bar time to the next. Usually,
it advances from phase-bar time two to phase time one. However, there are two exceptions.
1.

During address relocation cycles [REL CYC (0) H negated], the logic enters phase time one
after phase-bar time five.

During reset cycles (ENB RST L clear), the logic enters phase time one after phase-bar time
SIX.

When PHASE (1) H is set, the logic typically advances from one phase time to the next. However,
there are the following exceptions.

The logic pauses in phase time one if microcycle enable [MCENB3 (1) H] 1s clear.

The logic pauses in phase time one if the last phase time was an address cycle [LAD CYC(1)
H] and the address has not yet settled on the LSI-11 bus [GT BDAL 3 (0) H].

The logic enters phase-bar time one after phase time two during a chip set micro-NOP cycle

The logic enters phase-bar time one after phase time three if both MED PT H and —FDIN
ENB H are asserted. MED PT H is asserted during an F11 chip set address cycle or an F11
chip set data cycle that does not reference the LSI-11 bus, the IDAL bus, or an MMU regis-

(SHORT PT H).

ter. In these two cases, MED PT H is asserted. —FDIN ENB H is negated during a fixed
data cycle.

During an LSI-11 bus DOUT cycle, the logic pauses in phase time four until RRPLY3 (1) H
clears. This only affects LSI-11 bus DATIO timing.

During an LSI-11 bus, IDAL bus, or MMU DIN cycle, the logic pauses in phase time four
until it receives a reply signal. It then proceeds to phase time five.

During an LSI-11 bus, IDAL bus, or MMU DOUT cycle, the logic pauses in phase time five
until it receives a reply signal. It then proceeds to phase-bar time one.

The PBT CLR L signal clears flip-flops that gate data onto the CDAL lines during phase time. That
data must remain there for one-half an OSC period into phase-bar time. The PT CLR L signal clears
flip-flops that gate data onto the CDAL lines during phase-bar time. That data must remain there for
one-half an OSC period into phase time.
5.6

MIB DECODE LOGIC

The 16-bit microinstruction bus MIB <15:00> is common to all data and control chips. The MIB is
time-multiplexed and is used for different functions during the clock cycle. During the clock phase-bar
time, the MIB contains the current microinstruction provided by one of the F11 control chips. During
the clock phase time, the MIB lines contain control information provided by the F11 data chip. The
KDF11-BA logic monitors some MIB lines during phase time, some at the end of phase time, and some
at the end of phase-bar time. The MIB decode logic 1s shown in Figure 5-3.

5-6

PURPOSE

MIB <03:00> H

OUTPUT

DECODER

( DURING PHASE TIME

PHASE (1) L
ASTER
CLOCK

NTR
CONTROL
<

SRUN L

AF1)
——
(AH1,
————

GENERAL

PT3 (1N H

| [DGPOS L o (CLR EVENT)

DGPO6
L o (¢ R PWR LOW)

DGPO 7 L o (wR ODTA]

O H,

RELCYC (O) H

PHASEA (0) H RELOCATION ADDRESS [

LINITF (1) H

PHASEA (1) H_|CYCLE, ADDRESS

AND ODT
CYCLE

CYCLE DECODER

NHB<3544>LflNHB<D%OG>F{>>

END OF PHASE TIME

BINIT L

)

LAD CYC

( )‘>‘>CONTROL
(1)

TO BUS

BUSCYCH_

LOGIC

I—-'> K1

BUS CYC H

OF PHASE
END

BAR TIME

{

(1) H
L SYNCF

ODT CYC (1) H

IADRCYCH_‘\

1/0
ADDRESS

(1) H l cYCLE DECODERS
LSYNCF

PHASEA (1) H

(DURING PHASE TIME)
9

8 | MIB

0 | (AIO)

0 | UNUSED

MIB <12,09,08> H

| o

’;J

AWO

1 | ARW

ARO

o0 | pouTtB |

1 | pout

SHORTPTH_ | TOBUS

¢ CONTROL

MEDPTH

LOGIC

INCYCH

—>

|DOUTCYCH_
H
WTBT

—>

DIN

(1) H
HSYNCF

> |
MR-5878

Figure 5-3

5.6.1

MIB Decode Logic

MIB Decode During Phase Time

During phase time, MIB lines <12,09,08> contain the address/input/output signals AIO <<2:0>
while MIB lines <<03:00> contain the general-purpose outputs DGPO <3:0> L.

The AIO bits are decoded to determine whether the current cycle is an address cycle (ADR CYC H), a
bus-type data-in cycle (DIN CYC H), or a bus-type data-out cycle (DOUT CYC H). Bus-type DIN and
DOUT cycles are decoded only if BUS CYC H is asserted. The write/byte signal (WTBT H) is also
decoded, as are two signals that determine whether the logic enters phase-bar time either after phase
time two (SHORT PT H), phase time three (MED PT H), or phase time five (SHORT PT H and MED
PT H both clear). Table 5-1 describes the decoded general-purpose output signals derived from MIB
<02:00> when MIB 03 is negated.

The assertion of MIB 03 is used to set the read fixed data [RD FIXDT (1) L] flip-flop during phase
time three. When the RD FIXDT (1) L flip-flop is set, the jumper-selected power-up mode and
HALT/TRAP option information is gated onto the CDAL bus at the same time CDAL <<08> is negated to specify boot address 173000.

5-7

Table 5-1

Decoded General-Purpose Output

GPO2
(MIB02)

GPO1

GPOO

Output

(MIBO1)

(MIB00)

Name

Function

DGPO7 L

Loads the two highest order address bits into
a latch while in micro-ODT. These two bits
are necessary for 18-bit addressing because
the memory management unit is disabled
while in ODT.

DGPO6 L

Clears the power-fail flip-flop after the
power-fail sequence has been executed in
microcode.

DGPOS L

Clears the event flip-flop after the event
interrupt has been serviced in microcode.

SRUN L

Generates a low-going pulse that 1s routed
directly to edge fingers AF1, AH1. This
signal can be used to cause a steady RUN
indication while the processor is fetching
instructions, and a flashing indication when
typing characters in console ODT.

5.6.2

MIB Decode at the End of Phase Time

The following MIB lines are clocked into flip-flops by PHASEA (0) H at the end of phase time.
1.
2.

MIB 15 H is clocked into relocation cycle [REL CYC (0) H].

MIB 12 H is inverted to produce address cycle (ADR CYC H), which is clocked into latched

address cycle [LAD CYC (1) HJ.

MIB 07 H is inverted to produce SYNC H, which is clocked into LSYNCF (1) H. LSYNCF
(1) H is used by the bus control logic to generate BSYNC L.
MIB 14 H is clocked into LINITF (0) H, which is inverted to produce BINIT L.
5.6.3

MIB Decode at the End of Phase-Bar Time

PHASEA (1) H clocks the ODT CYC (1) H flip-flop at the end of phase-bar time. The ODT CYC (1)
H flip-flop sets if MIB 07 H is asserted and MIB 06 H is clear.

5.7

BUS CONTROL LOGIC

The logic described in this section controls the transfer of information between the F11 chip set and the
[.SI-11 bus, the transfer of information between the F11 chip set and the IDAL bus, and the transfer of
L.SI-11 bus ownership to DMA devices. Figure 5-4 shows the bus control logic interface to the LSI-11
bus and the internal KDF11-BA logic.

5-8

LSYNCF

(1) H

BUS CYC H

DOUT CYC H

DIN CYC H

MIB
DECODE

LAD CYC H

LOGIC

ADR CYC H

ODT
CYC (0) H

(AH2) < BDIN L
(AE2)
< BDOUT
L
(As2)

_MMU RPLY H

«-BOMGO
L

(AN2)
o BIAKO L

(BN1)

«BSACK
L

RSYNC2
H

(AJ2)

RRPLY2
H

@ BSYNC
L

MR2

(AF2) «2BEE Lol s

RDMAZ

(BA1) @BRCOK H ol SYNCHRO(AM2) < MCENB
H

NIZER

LSI-11 BUS

MCENB3
(1) H

DAL

IAD WR (1) L

ADDRESS

RD IDAL (1) H

DECODE

0SC H
—

LOGIC

oscH |
| TRANSCEIVERS
AL
OSCH
<:: CDAL <15:00~ H

BBS7 (1) H

LD BDAL (1)

PHASE
(1) H

RD BDAL (1) H

CLOCK
CONTROL

PT4 (1) H

ENDLIAK (1) H

PT4 (0) H

RD BDAL (1) H

PT5 (1) H

LPOK1 (1) H

PBT3 (1) H

CDAL/BDAL

TRANSCEIVERS

CDAL <21:00> H

RDCOK3
(1) H

PT3 (1) H

MASTER

—

GT BDAL (1) H

PHASEA
(0) L

-MMU RPLY H

IDAL <15:00> H

CDAL/

PHASEA
(1) L

MCENB3
(1) H

CDAL <21:00>H

CONTROL

YseLa
(1) HT
SELA (0) H

LOGIC

LD IADR (1) H

SELA

| miB 15 H (MME L)

DATA

IAD SEL H

BUS

0DT

FIXED

H
0SC

DMG (1) H

RDCOK3
(1) H

—

TSYNC
(1) H

TIMEOUT (1) H

FITCHIPS

LPOK2 (1) H

RSACK2
H

(ANT)<BRMR
L

MIB 13 H (IAK)

PBT4 (1) H

GT BDAL3 (1) H

DL IRQ L

_RRPLY3 (1) H

SERVICE

-DCcoOKC2B
L
-IRQ5 L
_IRQ 6 L
~ TIMEOUT (1) H

PBT CLR L

LOGIC

CDAL <12:00> H
BIRQ4L

(AL2)

BIRQ5L
~ BIRQ6L
BIRQ7L

(AAT1)
(AB1)
(BP1)

T
K9
CONSOLE
& 2ND SLU

RD IDAL (1) H

BDAL <21:00> BBS7 L

MR-5879

Figure 5-4

KDF11-BA Bus Control Interface

5.7.1

Bus Synchronizer Circuits
Because internal operation of the KDF11-BA is synchronous, asynchronous external signals must be
synchronized before they can be used by the KDF11-BA logic. The BRPLY L, BSYNC L, BSACK L,
and BDMR L signals received from the LSI-11 bus are time-critical and must be monitored as frequently as possible. At the same time, the registers that receive them must be allowed to settle for at
least 100 ns to ensure reliable bus operation. The bus synchronizer contains special circuits that clock
these four bus signals every OSC H period (75 ns), but allows them two OSC H periods (150 ns) to
settle. A fifth LSI-11 bus signal BDCOK H, and the microcycle enable signal MCENB H, are not as
time-critical; they are clocked every two OSC H periods.

5-9

5.7.1.1 BRPLY, BSYNC, BSACK, BDMR Synchronization — Each of the four bus signals (BRPLY L,
BSYNC L, BSACK L, and BDMR L) is applied in parallel to a pair of D type flip-flops. These flipflops are called the A and B synchronizer flip-flops. The outputs of the A and B flip-flops are connected
to the A and B inputs of a multiplexer. The select input of the multiplexer is obtained from the SELA
flip-flop, which is toggled by the leading edge of OSC H. The SELA (1) H output is used to clock the B
flip-flops and also for the select input of the multiplexer. The SELA (0) H output is used only to clock
the A flip-flops.

The BRPLY L signal is clocked into the B flip-flop by the SELA (1) H signal and into the A flip-flop
by the SELA (0) H signal. The SELA (1) H signal connected to the multiplexer selects either the A or
B flip-flop output to produce RRPLY2 H. When SELA (1) H is set, RRPLY?2 H equals the A flip-flop
output, which, by the next OSC H toggle, will have settled for two OSC H periods. This description
applies to the BSYNC L, BSACK L, and BDMR L signals, which are used to produce the RSYNC2
H, RSACK2 H, and RDMR2 H signals, respectively.
5.7.1.2 BDCOK and MCENB Synchronization - The BDCOK H signal is applied to two B synchronizer flip-flops, which are clocked by SEL (1) H. The output of the second B flip-flop [(RDCOK3 (1)
H)] is used to hold the KDF11-BA logic in the clear condition until RDCOK3 (1) H sets. This means
that the KDF11-BA logic will remain in the clear condition for two OSC H periods (150 ns) after
BDCOK H is asserted.

The MCENB H signal is applied to two A synchronizer flip-flops, which are clocked by SEL (0) H.
The output of the second A flip-flop MCENB3 (1) H is sent to the phase time pause control logic of the
master clock control. MCENB3 (1) H will clear two OSC H periods (150 ns) after MCENB H is negated. This signal is negated for manufacturing test purposes only.
5.7.2

Direct Memory Access (DMA) Control

DMA on the KDF11-BA module allows a peripheral to gain control of the LSI-11 bus from the processor and transfer data directly between that peripheral and memory. In this way, data transfers can occur at full memory speed rather than having the processor transfer data words one at a time between
the peripheral and memory. Paragraph 4.4 presents the LSI-11 bus specification for granting DMA
requests.

DMA Bus Grant Operation

A direct memory access (DMA) device requests control of the LSI-11 bus by asserting BDMR L. The
KDF11-BA grants control of the LSI-11 bus to a requesting device by asserting BDMGO L. The following events occur during a KDF11-BA bus grant sequence.

BDMR L is received, inverted to RDMR H, synchronized, and delayed by two OSC H periods to become RDMR?2 H.

After the KDF11-BA has released the LSI-11 bus [GTBDAL 1 (0) H and HLD BUS (0) H
both asserted], RDMR2 H asserts DMG ENB H.

OSC H clocks DMG ENG H into the DMG (1) H flip-flop, which asserts BDMGO L.

DMG (1) H also triggers the NO-SACK timeout circuit in the bus synchronizer. If BSACK
L is not asserted by the requesting DMA device within 10 us after the KDF11-BA 1ssues
BDMGO L, the NO-SACK timeout circuit will negate ENB DMR (1) L. The negation of
ENB DMR (1) L negates RDMR H, which leads to the negation of BDMGO L.

BSACK L is received, inverted to RSACK H, synchronized, and delayed by two OSC periods to become RSACK?2 H. RSACK2 H is clocked into the RSACK3 flip-flop (located in
the bus control logic) by OSC H to negate RSACK3 (0) H.

5-10

The negation of RSACK3 (0) H by OSC H causes the negation of BDMGO L to terminate
the bus grant sequence.

5.7.3

Address Microcycle Control

The KDF11-BA may perform either a normal-address microcycle or a relocated-address microcycle,
depending on whether the memory management unit is enabled or disabled. The memory management
unit is enabled or disabled under program control.

A normal-address microcycle is a 16-bit direct byte address that references the first 32K words (64K
bytes) of memory, and therefore, does not require the memory management function. A relocated-address microcycle is one that uses the MMU to convert a 16-bit program virtual address (VA) to an 18or 22-bit physical (PA) address. When the MMU is enabled, the normal 16-bit direct byte address is no
longer interpreted as a direct physical address but as a virtual address containing information to be
used in constructing a new 18- or 22-bit address that is capable of referencing addresses in a 4 megabyte memory.

Microinstruction bus bit (MIB 15) is the memory management enable (MME L) signal that indicates
to the processor logic whether a relocated-address microcycle should or should not be performed. The
memory management unit asserts MME L when a relocated-address microcycle should be performed.
MME is also asserted low by the KDF11-BA ODT logic during certain ODT address cycles.
The KDF11-BA logic stores the address provided by the F11 data chip during phase time if a normaladdress microcycle is to performed or if an ODT cycle has been decoded. During a relocation-address
microcycle (MMU asserts MME L), the address provided by the MMU is stored by the KDF11-BA
logic during phase-bar time. The following events take place during an address microcycle.
1.

The LD BDAL (1) H and LD BBS7 (1) H signals from the bus control logic clock the CDAL

The LD IADR (1) H signal from the bus control logic clocks the CDAL address into the
latched internal address registers of the IDAL decode logic at the end of phase time three.

If no DMA device is using the LSI-11 bus, the GT BDAL (1) L signal from the bus control
logic gates the address in the BDAL registers onto the BDAL lines at the end of phase time
three. Note that during address relocation cycles, the BDAL registers do not contain a valid

address into the BDAL registers at the end of phase time three.

address until the end of phase-bar time three.

If a DMA device is using the LSI-11 bus, the GT BDAL1 (1) H signal is inhibited until the
DMA device releases the bus by negating BSACK L. When the bus is released, OSC H sets
GT BDALI1 (1) H, which gates the address in the BDAL registers onto the BDAL lines.

LD BDAL (1) H and LD BBS7 (1) H clock the CDAL address into the BDAL registers at
the end of phase-bar time three when using the phase-bar time address (relocation address)
from the MMU.

LD IADR (1) H clocks the CDAL address into the latched internal address registers of the
IDAL decode logic at the end of phase-bar time four when using the phase-bar time address
from the MMU.

GT BDALI (1) H remains set until the recognition of a bus DIN cycle (MIB decode logic
asserts DIN CYC H), or the end of a bus DOUT cycle [DOUT 2 (1) H negates].

5-11

BSYNC Signal

5.7.4

The BSYNC L signal is asserted on the LSI-11 bus when the bus control logic asserts transmit synchronize [TSYNC (1) H]. All address cycles, except those that precede an interrupt-type DIN cycle, assert
TSYNC (1) H. According to LSI-11 bus specifications, TSYNC (1) H must be set 150 ns (minimum)
after the address is gated onto the BDAL lines. OSC L from the master clock control clocks TSYNC
(1) H set if both LSYNCF (1) H and GT BDAL3 (1) H are set. The MIB decode logic will assert
LSYNCF (1) H if MIB 07 H is negated at the end of phase time. The GT BDAL 3 (1) H signal in the
bus control logic is set 150 ns after the address is gated onto the BDAL lines. If GT BDAL3 (1) His
clear, the logic pauses in phase time until it sets, thus assuring two and one-half oscillator periods between the time the address is gated on the BDAL lines and the assertion of BSYNC L. If LSYNCEF (1)
H is clear, the logic continues but does not set TSYNC (1) H.

Once set, TSYNC (1) H remains set until the HLD BUS (1) H signal in the bus control logic clears and
the slave device negates BRPLY L. HLD BUS (1) H does not clear until GT BDAL2 (1) L and BUS
CYC H both clear.

Noninterrupt Bus DIN Cycles

5.7.5

A noninterrupt bus DIN cycle (DATI) is a read operation. During a DIN microcycle of a DATI bus
cycle, 16-bit data1s mput to the F11 chip set from the IDAL bus via the CDAL/IDAL transceivers or
from the LSI-11 bus via the CDAL/BDAL transceivers. The MIB 13 H (IAK H) signalis not asserted
during a noninterrupt bus DIN microcycle, and thus prevents the assertion of BIAKO L on the LSI-11
bus. The following events take place during a normal bus DIN cycle.
1.
2.

The TSYNC (1) H signal from the bus control logic is set one-half period before the end of
phase time one and is inverted to assert BSYNC L.

BDIN L is asserted by DIN CYC H from the MIB decode logic one-half period into phase
time three.

3.
4.
5.

5.7.6

GT BDAL (1) H is cleared at the end of phase time three because the MIB decode logic has

| asserted DIN CYC H.

If the IAD SEL H signal from the IDAL address decode logic is asserted, RD IDAL (1) H
gates the data on the IDAL lines onto the CDAL lines at the end of phase time four.
If the IAD SEL H signal is clear, RD BDAL (1) H gates the data on the BDAL lines onto

the CDAL lines at the end of phase time four.

The master clock control causes the logic to pause in phase time four until it receives an
indication that the data transfer is completed. The completion of the data transfer is indicated by the assertion of the BRPLY L signal, the RD IDAL (0) H signal from the bus
control logic, or the MMU RPLY H signal from the memory management unit.

The CDAL data is clocked into the F11 chip set at the end of phase time five.
Interrupt-Type Bus DIN Cycles

The KDF11-BA may accept interrupts from either the on-board SLUs or from external devices. If the
interrupt request is from an on-board device, the interrupt vector address is input to the F11 chip set via
the CDAL/IDAL transceivers. If the interrupt request is from an external device, the input vector
address is input to the F11 chip set from the LSI-11 bus via the CDAL/BDAL transceivers.

5-12

The F11 chip set asserts MIB 13 H (IAK H) during interrupt type bus DIN cycles. IAK H causes the
assertion of the BIAKO L bus signal to acknowledge the honoring of an external or internal interrupt
request. The following events take place during an interrupt-type DIN cycle.
1.

The KDF11-BA SLUs request an interrupt by asserting DL L. If one of the SLUs is requesting an interrupt, and if no higher interrupt request is pending (BIRQ 5 L and BIRQ 6 L
negated), the bus control logic asserts EN DLIAK (1) H at the beginning of phase time one.
Because LSYNCEF (1) H is clear, TSYNCF (1) H does not set.

The assertion of DIN CYC H from the MIB decode logic causes DIN (1) H to set one-half
period into phase time three. When DIN (1) H sets, it causes the assertion of BDIN L.

GT BDALI1 (1) H in the bus control logic is cleared at the end of phase time three by the
assertion of DIN ENB H.

If the EN DLIAK (1) H signal in the bus control logic is set, RD IDAL (1) H is set one
period into phase time four. When RD IDAL (1) H sets, one of the four KDF11-BA SLU
vector addresses placed on the IDAL lines is input to the F11 chip set via the CDAL/IDAL
transceivers.

If EN DLIAK (1) H is clear, RD BDAL (1) H is set one period into phase time four and
TIAK (1) H is clocked set one period after GT BDAL3 (1) H is clocked clear. When TIAK
(1) H sets, it causes the assertion of BIAKO L. The vector address input from the external
device is then read from the BDAL lines to the CDAL lines.
The master clock control causes the logic to pause in phase time four until it receives an
indication that the vector address transfer is completed. The completion of the vector transfer is indicated by the assertion of the BRPLY signal or by the negation of the RD IDAL (0)
H signal from the bus control logic.
8.

5.7.7

The CDAL data is clocked into the F11 chip set at the end of phase time five.
Bus DOUT Cycle

A bus DOUT cycle is a write operation. During a DOUT microcycle of a DATO(B) bus cycle, 16-bit
words (DATO) or 8-bit bytes (DATOB) are output by the F11 chip set to an IDAL register via the
CDAL/IDAL transceivers, or to an external device via the CDAL/BDAL transceivers. The following
events take place during a DOUT cycle.
1.

LD BDAL (1) H clocks the CDAL data into the BDAL registers at the end of phase time
three.

The CDAL data is also gated onto the IDAL lines.

The bus control logic clocks the internal address write [ITAD WR (1) L] signal on at the end
of phase time two and clocked off one period into phase time five. If the PLA in the IDAL
address decode logic has selected one of the writable registers, the IAD WR (1) L signal
gates the load signal (e.g., LD PCR LO L) to the selected IDAL bus register.
The master clock control causes the logic to pause in phase time four until the bus control
logic negates RRPLY3 (1) H. This occurs only during DATIO cycles.

5-13

The DOUT CYC H signal from the MIB decode logic is clocked into DOUT (1) H of the bus
control logic one period into phase time five. When DOUT (1) H sets, it causes the assertion
of BDOUT L.

5.8

The master clock control causes the logic to pause in phase time five until the MMU asserts
MMU RPLY H, an external device asserts BRPLY L or, if IAD SEL H is asserted, until the
bus control logic negates IAD WR (1) H.

The negation of GT BDAL (1) H is delayed by the setting and clearing of DOUT?2 (1) H.
DOUT?2 (1) H is set one period after DOUT (1) H sets (after BDOUT L is asserted).
DOUT?2 (1) H clears one period after DOUT1 (1) H clears.

CDAL/BDAL INTERFACE

The CDAL/BDAL transceivers transfer information between the LSI-11 bus and the F11 chip set in
response to load, gate, and read signals obtained from the bus control logic. The CDAL/BDAL bus
interface i1s shown in Figure 5-5.

The LD BDAL (1) H and LD BBS7 (1) H signals are used to load the information on the CDAL bus
into the transceiver registers during a data-out (write) bus cycle. The GT BDAL (1) L signal gates the
contents of the transceiver registers onto the LSI-11 bus. The RD BDAL (1) L signal enables the transceiver registers during a data-in (read) bus cycle to transfer the information on the BDAL <<18:00> L
lines to the CDAL bus.

The MIB decode logic decodes MIB <7:6> and sets or clears the ODT CYC flip-flop at the end of
phase-bar time to indicate whether the current cycle is a normal address cycle or an ODT address
cycle. The ODT CYC flip-flop is clear during a normal address cycle and set during an ODT cycle.
During normal address cycles, BBS7 L is asserted if BSIO H is asserted by the F11 data chip or the
MMU chip. During ODT address cycles, the ODT logic performs an ODT relocation cycle to clear
BBS7 L if either ODTA17 (1) H or ODTA16 (1) H is clear. The assertion of BBS7 L indicates that an
address references the 8K-byte I/O page.

The HWTBT (1) H signal is loaded into the CDAL/BDAL transceivers and gated onto the LSI-11 bus

during the address and data portions of the data-out bus cycle. The MIB decode logic decodes MIB

<9:8> to set or clear the HWTBT latch. The HWTBT (1) H signal is set during the address portion of
a data-out bus cycle. During the data portion of the data-out bus cycle, HWTBT (1) H is set to indicate
a write byte operation and clear to indicate a write word operation. The state of HWTBT is not gated
onto the LSI-11 bus during a data-in cycle.

The BDAL <17:16> L bits are used by the service logic for an address parity check. The bits are
transferred as RDAL <17:16> H to the service logic by RD BDAL (1) L during a data-in bus cycle.
If both RDAL bits are set, an address parity error [PAR ERR (1) H] is generated by the service logic
at the end of phase-bar time. PAR ERR (1) H is used by the reset logic to reset all of the FI1 chips
except the MMU chip. PAR ERR (1) H also causes the program to trap to location 114g.
5.9

SERVICE, RESET, AND ODT LOGIC

The service logic gates information onto the CDAL <12:07,05:00> lines in response to various external and internal KDF11-BA conditions. The service logic operation is described in Paragraph 5.9.1. The
reset logic monitors various error signal inputs and generates a reset signal for the bus control logic and
the F11 chip set if an error is detected. The reset logic operation is described in Paragraph 5.9.2. The
service and reset logic interface to the LSI-11 bus, CDAL bus, and other KDF11-BA logic is shown in
Figure 5-6.

14598

1791M8

SN8 LL-1ST

<79L:81>1vag

1
<
0
:
6
1
>
"
T
1
v
a
g
PN

<91:21>1vayKH1907 _ o
Ly

aIN /><9 [ 30 234

an oS

JOYINOD

9l<8:6> 30 23d
0885-HIN

ST<v91a:s8g1/>1v:ad oLoa>lLMH(1)H 0:LZ>18vlao<H< 86>|g~1|1Ad0L9IA0HN7DODAD(0)7 s1vHaLlv
1Gl vad<0:G1>H 1vad<0:51>H LSYIAoI5TOSNVYH

a0]/Raldv1Tdv/aS¥9dd3(HL()H1<){H9HlL)8L>1<eLiz1>1vad1[0J1—9B0m7Eo=_] £se8H—
SHYIAITFOSNYYL

<blile>

(71v1a9)g

5-15

Ival/van

:gL>vad

Tvasg/1va

AL2)

BIRQ
4L

AAT)

BIRQS
L

(AB1)

BIRQ
6L

BIRQ7
L

81)

BPOK
H

AP1)

BHALT
L

CDAL/BDAL

RDAL
16 H

INTERFACE

CDAL <12:00> H

LINE CLOCK
LOGIC

IRQ <4:7> H TO CDAL <11:8> H

]

::)

EVENT
FLG (1) H

SERVICE
LOGIC

SSSSOLE

RQ HLT H

IRQ5 L
_IRQ6
L

K9
DGPO 6 L (CLR PWR

MIB

DECODE
o

LPOK1 (1) H

A—

BUS

CONTROL
LOGIC

LINITF (1)
(1) L L(BINIT
(BIN
L)
REL CYC (0) H

RD SVC (1) L

PHASE (0} H
PT2 (1) L

DCOKC2
(0) H

PT4 (1) H

BUS ERR
(1) H

PBT4 (1) H

MASTER

—~

CLOCK

RESET
(1) H

NOCSEL
H

PARERR
(1) H

CONTROL
PT CLR

RESET

PBT3 (1) L

LOGIC

H
0SC

K1
MMU CHIP
F11 CHIP SET

ENB RST

ABORTL
CHIP RST H

K3
MR-5881

Figure 5-6

Service and Reset Logic Interface

The ODT logic gates the ODT address onto the CDAL <<21:16> lines during ODT address cycles.
The operation of the ODT logic is described in Paragraph 5.9.3 and the logic interface is shown in
Figure 5-7.

5.9.1
Read Service Operation
The CDAL <12:00> lines contain service information during phase-bar time if a relocated address is
not on the CDAL bus. The read service RD SVC (1) L signal from the reset logic gates the service
information onto the CDAL <<12:00> lines at the end of phase-bar time one, or when an MMU abort
occurs at the beginning of phase-bar time four. RD SVC (1) L is cleared by phase time clear PT CLR
L one-half period into phase time one.

5-16

Thirteen service information bits are placed on the CDAL <12:00> lines by tri-state drivers or tristate registers. Five of the CDAL lines <<06,04:02,00> are driven by tri-state drivers when RD SVC
(1) L is asserted. The signal names and functions for the CDAL lines are described in Table 5-2.
Table 5-2

Service Logic Bits <06,04:02,00>

CDAL

Signal

Line

Name

Function

CDAL 06 H

Ground

CDAL 06 H is always asserted.

CDAL 04 H

CTL ERR (1) L

The assertion of this bit indicates that none of the F11 control

CDAL O3 H

ABORT L

Negation of this bit indicates the occurrence of an MMU

CDAL 02 H

PAR ERR (1) L

Assertion of this bit indicates a parity error.

CDAL 00 H

DCOKC3 (1) L

Assertion of this bit indicates that the LSI-11 bus BDCOK H

chips asserted either CSELA L or CSELB L.

abort.

signal has been valid for at least three phase-to-phase-bar
transitions.

The remaining eight CDAL lines <12:07,05,01> are driven by a tri-state register. The signals described in Table 5-3 are clocked into the register by PHASE (0) H at the beginning of phase-bar time
and placed on the CDAL lines when RD SVC (1) L is asserted.
Table 5-3

Service Logic Bits <12:07,05,01>

CDAL

Signal

Line

Name

Function

CDAL 12 H

EVENT FLG (1) H

The assertion of this bit posts a line clock interrupt request.

CDAL 11 H

IRQ 4 H

The assertion of this bit posts a level-4 interrupt request.

CDAL 10 H

IRQS5SH

The assertion of this bit posts a level-5 interrupt request.

CDAL 09 H

IRQ 6 H

The assertion of this bit posts a level-6 interrupt request.

CDAL 08 H

IRQ7H

The assertion of this bit posts a level-7 interrupt request.

CDAL 07 H

PWR DWN (1) H

The assertion of this bit posts a power-down interrupt

CDAL 05 H

HALT H

This bit reflects the state of the LSI-11 bus BHALT L line.

CDAL O1 H

TIMEOUT (1) H

The assertion of this bit indicates that a bus timeout has

request.

occurred.

5-17

5.9.2 K11 Chip Reset Operation
The reset logic generates an F11 chip reset (CHIP RST H) signal for any one of five error conditions
that require immediate attention by the chip set. The CHIP RST H signal is routed to all the F11 chips
except the MMU chip. The CHIP RST H signal is asserted high for any one of the five following
|
conditions.

Control error — A nonexistent control chip is selected by the microcode.

Bus error — A nonexistent memory location is accessed.

Parity error — A parity error is detected on a current read from memory.

DC power-up — Upon power-up the processor forces the reset logic to assert CHIP RST H to
initialize all internal chip registers. The dc power-up line then clears and is not reactivated
while dc power is on.

MMU abort — The MMU has aborted a mapped memory reference. The MMU chip will
assert ABORT L for any of the following reasons.
e

The memory location referenced is not present in the current user’s protected address
space.

An attempt is made to modify a write-protected location.

The user is exceeding his allotted page boundary.

The reset logic input and output signals are shown in Figure 5-6. The CHIP RST H signal is obtained
from a RESET flip-flop that is clocked set at the beginning of phase-bar time four if any one of four

error signals from the service logic is asserted. The service logic error signals are applied to a NOR gate
to produce an enable reset (ENB RST L), which is applied to the D input of the RESET flip-flop and
the master clock control. The assertion of ENB RST L extends phase-bar time through phase-bar time
SIX.

The ABORT L signal generated by the MMU chip as a result of a memory error is applied to the set
input of the RESET flip-flop when phase-bar time three begins. The signal names and functions of the
error signals that cause assertion of CHIP RST H are described in Table 5-4. The RESET flip-flop is
cleared by PT CLR L from the master clock control one-half period after phase time one.

Table 5-4

F11 Chip Reset Signals

Signal

Name

Function

DCOKC3 (0) H

Assertion of this bit indicates that the LSI-11 bus BDCOK H signal has been

valid for less than three phase time-to-phase-bar transitions.

PAR ERR (1) H

Assertion of this bit indicates a parity error; a trap to location 114g occurs.

BUS ERR (1) H

Assertion of this bit indicates a bus timeout; a trap to location 4g occurs.

NO CSEL H

Assertion of this bit indicates that none of the F11 control chips asserted either
CSELA or CSELB; a trap to location 10g occurs.

ABORT L

Assertion of this bit indicates an MMU abort; a trap to location 250g occurs.

5-18

5.9.3

ODT Address Logic

During ODT addressing cycles the processor responds to commands and information entered via the
console terminal addresses 777560g through 777566g. The ODT logic interface to the CDAL bus and
other KDF11-BA logic is shown in Figure 5-7.

The ODT logic contains a flip-flop (PT2D) that is used to gate the CDAL <21:16> and MIB 15 H
drivers. PT2D is clocked set during every address cycle at the beginning of phase time two and cleared
one-half period into phase-bar time one by PBT CLR L. The ODT logic also contains an ODT ADR
flip-flop that gates the ODT address bits <<17:16> onto CDAL <17:16> H, controls ODT address
relocation by assertion or negation of MIB 15 H, and enables or disables the MMU by assertion or
negation of DMMUS L.

N\
CDAL <21:16> H

0SC H

PHASE (1) L

VASTER

PHASEA (1) L

CLOCK

PT2 (1) H

CONTROL

PBT (1) H

PTCLR L

PBT CLR L

ADR CYC H

REL CYC (1) H

MIB

DECODE

ODT CYC (1) H

LOGIC

DGPO 7 L (WR ODTA)
LINITF (1) L

A
(]

CDAL 00 H

F11 CHIP SET

oKS

cDAL <15:00> H

VMU CHIP

CDAL 01 H

OoDT

MIB15H ( (MME L)

LoGle

MMU RPLY L
DMMUS
L

BSIO H

ags7 L | COAL/BDAL
(AP2) @—=L =1 TRANSCEIVERS le—
K5

IDAL ADDRESS

DECODE

LD MMRO LO L

CDAL/IDAL

TRANSCEIVERS

IDALB 00 H

K3
MR-5882

Figure 5-7

KDF11-BA ODT Logic Interface

5-19

During ODT address cycles the ODT ADR flip-flop is clocked set by OSC H at the end of phase time
two and cleared one-half period into phase-bar time. If the ODT ADR flip-flop is set, the PD2D flipflop negates CDAL <21:18> H and gates ODT address bits <<17:16> onto CDAL <17:16> H.
During normal address cycles the ODT ADR flip-flop is clear and the PT2D flip-flop negates CDAL
<21:16> H. The remaining address bits (<<15:00>) are gated onto CDAL <15:00> H by the F11
data chip.

If the two ODT address bits, ODT17 (1) H and ODT16 (1) H, are both set, the phase time address and
BSIO H signal are correct and there is no need to prevent the DAT and MMU chips from responding
to their I/O page addresses. However, if either of the ODT address bits is clear, the ODT logic must
guarantee that the BBS7 L register bit is negated and that the DAT and MMU chips do not incorrectly
respond to an asserted BSIO H during phase time. Therefore, if either ODT17 (1) H or ODT16 (1) H is
clear, the ODT ADR flip-flop asserts DMMUS L to disable the MMU registers, and negates MIB 15
H to force an ODT address relocation cycle. The assertion of DMMUS L prevents the MMU from
decoding CDAL<12:00> for an MMU register address.
The ODT address relocation cycle negates BSIO H and CDAL <<21:19>, but presents meaningless
data on CDAL < 18:00>. This relocation cycle performs two functions. First, it prevents the DAT chip
from incorrectly responding to a phase time PS address of 177776 on CDAL <15:00>. The DAT chip
sees a relocated address with BSIO H negated. Second, it loads the negated BSIO H signal into the
BBS7 L register bit with the load signal LD BBS7 (1) H. Note that LD BDAL (1) H also updates the
BDAL <21:19> L register bits even though they were correctly negated during phase time.
5.10

FIXED DATA DIN CYCLES

The fixed data logic shown in Figure 5-8 gates the jumper-selected power-up mode and HALT/TRAP
options onto the CDAL bus during DIN cycles. If MIB 03 H is asserted during phase time, the RD
FIXDT flip-flop is set at the end of phase time two and cleared one-half period into phase-bar time one.
RD FIXDT L enables tri-state drivers that gate the following status bits onto the CDAL lines.

CDAL Line | Input Signal and Purpose

CDAL 08 H|

Ground. When power-up mode 2 is selected (CDAL bits 01-00 below), this bit specifies
boot address 773000.

CDAL 07 H|

LPOK2 (1) L. The assertion of this bit indicates that the LSI-11 bus BPOK H signal is
asserted.

CDAL 02 H|

CDAL 01 H|

TRAP OPJ L. Assertion of this signal indicates that the trap option jumper has been
installed.

PUP CD1J L. Assertion of this signal indicates that the power-up code bit 01 jumper
has been installed.

CDAL 00 H|

5.11

PUP CDO0J L. Assertion of this signal indicates that the power-up code bit 00 jumper
has been installed.

CDAL/IDAL INTERFACE

The CDAL/IDAL transceivers transfer address and data information to and from on-board peripheral
devices connected to the IDAL bus and other internal KDF11-BA logic and/or the LSI-11 bus via the
CDAL bus. The on-board peripheral devices are the console and second serial-line units, the bootstrap/diagnostic ROMs and the line clock. The CDAL/IDAL interface is shown in Figure 5-9.

5-20

VoVoYaYeVe

CDALO8H,

LPOK2 (1) L

J16
o

J18

_PUPCD1J L
J19

J17

(1) H
PT3
D

MIB
03 H

TRAP OPJ L

L
_PUPCDOJ

RD
FIXDT

OSC H

PBT CLR Lff

CDALO7
H

CDALOZ2H

CDALOTH
_

CDALOOH
_

RD FIXDT (1) L

__{::>x3FDHvENBL~
MR-5883

Figure 5-8

Fixed Data Logic

MASTER
cLOCK
CONTROL
K1

PHASE (1) L

CDAL <15:08>

v
do—| V

EN IDAL (1) .

0SC H

SERVICE DCOKC?2B

CDAL/IDAL

TRANSCEIVERS

IDAL <15:00> H

PBT3
(1) L

LOGIC

’

BUS

CONTROL

CDAL/IDAL

CDAL <07:00> ) TRANSCEIVERS

L——*fi

RD IDAL (1) H

%
MR-5884

Figure 5-9

CDAL/IDAL Interface

5-21

The CDAL/IDAL transceivers are enabled by the EN IDAL (1) L signal. The EN IDAL flip-flop is
clocked clear one-half period into phase-bar time one; this disables the CDAL/IDAL transceivers. The
CDAL/IDAL transceivers are enabled when the EN IDAL flip-flop is clocked set one-half period into
phase-bar three or one-half period into phase time one, whichever occurs first.
The direction of data transfer through the CDAL /IDAL transceivers is controlled by the RD IDAL (1)
H signal obtained from the bus control logic. The RD IDAL (1) H signal is normally low, causing the
transfer of data from the CDAL bus to the IDAL bus. When an IDAL bus register or vector address is
read, RD IDAL (1) H goes high at the end of phase time four and is cleared at the end of phase-bar
time one. RD IDAL (1) H causes the transfer of data from the IDAL bus to the CDAL bus.
5.12

IDAL ADDRESS DECODE

The IDAL address decode logic decodes the IDAL <12:00> H address bits and generates read and
load signals for the serial-line units, the bootstrap/diagnostic ROMs, the bootstrap/diagnostic registers,
and the line clock register. The IDAL address decode logic is shown in Figure 5-10.

The LD TADR signal from the bus control logic clocks BS7 H and IDAL <12:00> H into the latched
internal address register at the end of phase time three of a normal address cycle, or at the end of
phase-bar time four of a normal address relocation. Because BS7 H reflects BSIO H gated by the asser-

tion of ODT17 (1) H and ODT16 (1) H, ODT relocation cycles do not update the internal address
register. The outputs of the latched internal address register are sent to the programmable logic array
(PLA), ROM read decode logic, and the load and read decoders.

The PLA decodes address, control, and jumper signals to produce signals that control the loading and
reading of various IDAL bus registers. The PLA inputs may be subdivided as follows.
1.

Four wirewrap jumpers:

J15 BDK DISJ L, when asserted, disables the boot and diagnostic registers, the boot

J14 DLI1 DISJ L, when asserted, disables the console SLU registers.

J13 DL2 DISJ L, when asserted, disables the second SLU registers.

J12 DL2 ADRJ L, when asserted, changes the base address of the second SLU from

and diagnostic ROMs, and the line clock register.

17776500g to 17776540g.

2.
3.

HWTBT H - This signal is always clear during read data transfers, clear for write-word data
|
transfers, and set for write-byte data transfers.
HSYNCF H - This signal is clear when reading a vector address and set for a normal read or
write.

This signal is asserted (low) if LBS7 (1) H, LA12 (1) H, and LAI10 (1) H are all asserted.
This signal is asserted for all IDAL references. However, it is not decoded for vector address
references.

This signal is asserted (low) if LAO8 (1) H and LAO06 (1) H are both asserted while LAO7 (1)
H is negated. This signal is asserted for all IDAL register references. It is not decoded for
either boot and diagnostic ROM references or for vector address references.

LA <11,09,05:01> H — These seven address signals are individually decoded.

LA <00> H - If HWTBT H is asserted, this address bit determines whether the high byte
or low byte is referenced.

5-22

> L ATCHED

IDAL <12:00> H

INTNL

LD IADR

BSIO H

READ

LBS7 H

LO%C

AL ]
2
a

ADRS

REG

RD IDAL H T

> pEcope |RRROML
ROM

LA <12:09> H

LOAD

LDRWRLOL

LDDSPLY LOL _

READ

A <02.01> H

LD PCR LO L

AND

DECODERS [ LDKWLOL

LDPCRHIL

pra
ODT BS7 L

LD RWRHIL

|SELMMROL
(TO ODT LOGIC)

H
SEL BK HB

%I)DTL cyc

(

SEL BK LB L

FRoM mig

[—WTBTH

IAD WR L

Log?cDE

HSYNCF H

RD IDAL H

IDAL <15:00> H

LDRCSR2L

LDTCSR2L

LDTBUF2L

RD RWR L

RD KW L

RDSWADRL

LDRCSR1L

(FROM BUS

CONTROL LOGIC)

LDTCSR1L

LDTBUFTL

J10

1
—

\25

BDK DISJ L

J14

DL1DISJ L

J13

DL2DISI L

J12

DL2 ADRJ L

O-

SELDLLBL

RDTCSR L

RD RCSR L

RD RBUF L
— LA 09 H

SLU

|o seLecT
K7

IAD SEL H

RD IDAL L

RBUF

pSELDLIL
SEL DL2 L

RD VEC L

SELECT
S

RD RBUF1 L
RD RBUF2 L

g
&

SLU/CLK
VECTOR

RD KW L | ASSERTION

IDAL <07:00>
H

ZB 15—12 L

ZERO

ZB11-8 L

BIT

ZB 5—3A1 L

ASSERTION

IDAL <15:08>, <05:03>, <01>
K7

IDAL <15:00>
MR-5886

Figure 5-10

IDAL Address Decode Logic

5-23

The eight PLA outputs are sent to the load and read decoders, the SLU select logic, the SLU/CLK
vector assertion logic, and the zero bit assertion logic. The signal names and functions of the PLA outputs are as follows.
1.

SEL MMRO LB L - Asserted for low-byte references to memory management status register (SRO) at address 1777757
2.

SEL DL LB L — Asserted for low-byte references to device and vector addresses selected by
the following jumper configurations.
e

Device addresses 17777560g through 17777566g if DL1 DISJ L (J14) is ungrounded.

Device addresses 17776500g through 17776506¢ if DL2 DISJ L (J13) and DL2 ADRJ
L (J12) are both ungrounded.

Device addresses 17776540¢ through 17776546¢ if DL2 DISJ L (J13) is ungrounded
and DL2 ADRJ L (J12) 1s grounded.

SEL BK HB H - Asserted for high-byte references to addresses 17777521g through
17777525¢ and 17777547g if BDK DISJ L (J15) is ungrounded.
SEL BK LB L - Asserted for low-byte references to addresses
17777524g and 17777546¢ if BDK DISJ L (J15) is ungrounded.

17777520g

through

ZB-3A1 L — Asserted for all register references for which, when read, register bits
<05:03,01
> are always zero.
ZB11-08 L — Asserted for all register references for which, when read, register bits
<11:08> are always zero.
ZB15-12 L — Asserted for all register references for which, when read, register bits
<15:12> are always zero.
IAD SEL H — Asserted if SEL DL LB L, SEL BK HB H, or SEL BK LB L is asserted. Also
asserted for valid DL high-byte references and valid references to the boot and diagnostic
ROM addresses.
|

The various load and read control signals are produced by three 74L.S155 decoders and associated logic. The load signals are sent to the SLU registers, the page control register, the read /write maintenance
register, the boot/diagnostic display register, and the line clock logic when the IAD WR L signal from
the bus control logic is asserted.

The read signals are sent to the SLU registers, the boot configuration register, the SLU/CLK vector
assertion logic, and the read/write maintenance register when the RD IDAL H signal from the bus
control logic is asserted. The ROM read decode logic asserts RD ROM L when the RD IDAL H signal
is asserted. The RBUF select logic uses the RD RBUF L signal from the load and read decoders to read
the contents of either the SLU receiver buffer RD RBUF1 L or RD RBUF2 L.
5.13
BOOTSTRAP/DIAGNOSTIC AND LINE CLOCK LOGIC
Figure 5-11 shows the bootstrap/diagnostic and line clock logic.

5-24

BOOT/
DIAGNOSTIC
oM

H
IDAL <07:00>

INTNL
REG

RD ROM L

LA <07:00> H

ADRS

IDAL <12:00> H

BYTE

LATCHED

122

J24

123

E127
500/

LD IADR Hf

DIAGNOSTIC
ROM

> H
< 15:08
IDAL

PAGE

CONTROL

PCR <13:08> l
REGISTER

IDAL <13:08> H

ADDRESS

PCR <11:08> H

2Y
<
0

ROM

LD PCR LO H f

URATION '—"\"1 SWITCHES

IDAL <07:00> H

CONFIG-

BOOT/DIAGNOSTIC

RD SWADR

LD RWR HIH_|

HIBYTE

DISPLAY F—g—
REGISTER

IDAL <03:00> H

RD RWR H—:

D4 . M

| D4 g

| D5

LINE

LD KW LO H

CBE\/ENT L

(BR1)

EEG

G|EVENT FLGH

E'LNKE
i

CLK
STATUS
—

oLk
SLU/CLE

RD KW L_| AS SERTION

J10 J11
LTC ENJ L
e

IDAL <06> H

NVZ

W IE (1) H

MAINT.
ot

LDRWR LOH | LOBYTE

—e +5

LSO

LD DSPLY LOH |

RD/WR
.
H
IDAL <07:00>

MSD,,
P

RD/WR

<IDAL <15:08> H> “F?QC‘SNT-

BTRA <11:08> H

MUX

PCR <03:00> H

PCR <05:00>
K8

BTRA 13 H

ADDRESS

PGSt
REGISTER

IDAL <05:00> H

BTRA 12 H
N

LA 08 H—t

PAGE

MU X

PCR <05:00> H Jl>

LD PCR HI H f

BYTE

ROM

PCR <13:12> H

SERVICE

LOGIC
o

EVENT H
CLR EVENT
MR 5887

Figure 5-11

5.13.1

Bootstrap/Diagnostic and Line Clock Logic

Boot and Diagnostic Logic

The boot and diagnostic page control register consists of two bytes, PCR 13-08 (1) H and PCR 05-00
(1) H, each located in a hex register. These registers are loaded from the IDAL lines by —LD PCR LO
H and by —LD PCR LO H, respectively. A pair of quad multiplexers produce the six most significant
ROM address bits, BTRA 13-08 H. If LA 08 (1) H is set, BTRA 13-08 H equals PCR 13-08 (1) H. If
LA 08 (1) H is clear, BTRA 13-08 H equals PCR 05-00 (1) H.

5-25

The boot and diagnostic ROM sockets accept pin-compatible 2K, 4K, and 8K ROMs. These ROMs are
addressed by BTRA 13-08 and by latched internal address bits LA <<07:01>. A wirewrap jumper can
replace BTRA13 H with +5 V for 2K EPROMs. The ROM data is gated directly onto IDAL

<15:00> by RD ROM L. The KDF11-BA uses 2K ROMs that are compatible with the BDV11.
The boot and diagnostic read/write maintenance register consists of two bytes located in a pair of 8-bit
universal shift/storage registers. These registers are loaded from IDAL <15:00> by —LD RWR HI
H and —LD RWR LO H. RD RWR H gates their contents onto IDAL <<15:00>.
The boot and diagnostic write-only display register consists of four bits located in a quad register. —LD
DSPLY LO H loads this register with data from IDAL <<03:00>. Clearing one of the four display
register bits lights a corresponding LED mounted at the top of the KDF11-BA module.
The boot and diagnostic read-only switch register consists of eight switches that are gated onto IDAL

<07:00> by RD SWADR L. The remaining IDAL lines are negated by the zero bit logic driven by
the PLA outputs ZB 15-12 L and ZB 11-9 L. (See Figure 5-10.)
5.13.2

Line Clock Register

the line clock register contains a single read-write bit, KW IE (1) H. This bit is loaded from IDAL 06 H
by —LD KW LO H. KW IE (1) H is held set when the LTC ENJ L signal is.asserted by a wirewrap
jumper. The LSI-11 bus BEVENT L signal is received as EVENT H. If KW IE (1) H is set, the leading edge of EVENT H sets EVENT FLG (1) H.
The logic for reading the line clock register consists of a quad multiplexer that gates KW IE (1) H onto
IDAL 06 H and negates IDAL 07, 02, and 00 H. The remaining IDAL lines are negated by the zero bit
logic driven by the PLA outputs ZB 15-12 L, ZB 11-9 L, and ZB 5-3A1 L. (See Figure 5-10.)
5.14

SERIAL-LINE UNITS
Figure 5-12 (Sheets 1 and 2) shows the logic associated with the serial-line units.

5.14.1

Universal Asynchronous Receiver Transmitters
Each serial line unit is based on a universal asynchronous receiver transmitter circuit, contained in a
single 40-pin package (Digital Part No. 21-13937-01). Each UART contains a receiver section and a
transmitter section.

The receiver section contains receiver data buffer bits 07-00 and receiver status register bit 07. Serial
data (SERJAL IN1 H or SERIAL IN2 H) is clocked into a receiver shift register and then transferred
to the data buffer. Loading the data buffer sets the status bit (RX1 DONE H or RX2 DONE H). The
read control signal (RD RBUF1 L or RD RBUF2 L) gates the data buffer onto IDAL 07-00 H and
clears the status bit.
The transmitter section contains transmitter data buffer bits 07-00 and transmitter status register bit
07. The write control signal (LD TBUF1 L or LD TBUF2 L) loads IDAL 07-00 H into the data buffer
and clears the status bit (TBMT1 H or TBMT2 H). The contents of the data buffer is loaded into the
transmitter shift register (as soon as that register is empty) and then clocked out as serial data (SERIAL OUTI1 H or SERIAL OUT2 H). The status bit is set when the data buffer is empty and able to
receive another character.

For each UART the receiver and transmitter clock inputs are driven by the same clocking signal (RT
CLK1 H or RT CLK 2 H). The clock rate is 16 times the serial data rate.
Character formats are selected by wirewrap jumpers and may consist of seven or eight data bits, one or
two stop bits, parity or no parity, and odd or even parity.

5-26

—mowm_m_]aIyvVa1l1>(1)<07:50'60°LHaB1ERZzRusoVyTBV1<60>H53ysTH3lgRxXL
—HOLO3IA1aOMVIH IVIg L1HdZlHNYg0G1

(1) ym avl sneg [ Lnoasg

2IngigZ1-G oul-[esSsiun)19YS)1Jo(T

< 4LINDT (1)T

L aviYm(1) a12dSOL7 _

<o1val<0:£0>H 219037 D97NZAS1H—(GL)lH ¢1arS19a737oZ1-T6Glo= Tvdl<V190<>60H>H 1041NOD>-¢xH3lH-

A=e vRR£SE8R7(1e)H5137¥3sA|vZI|aAYzi1r24oLNr84 —”iL1ddNN4YYSOHIyILLNNI]eH3ZlxeyxX3llHo—J m)
HL NGL

HLIXNOYJ

H <00:SL> 1val

5-27

@ £000d

ciro » [ OL

oY3z

Y(|H¢—S—|O0X
e

888S-HWN

v+AMVvIal1mvHlaa_Zyl>gL0T<oN:0ZwG2z”0L:4>£n09>yHHezLO4dNnn;LasNyyGS—=—|o1O_33s|szr
1ll.AHuv valaT01:I£0n>aH< L V1LvVd1S 0S -03y 0.«5_
AHV 31L04SNNgOlD LINX .
L@ "EF1RdTHREO SN LX3 1DH3

5-28

HY0zZ1a 03y

a*3SzanaL
l

1dvn

—0 2
|

ayl4nay
1y>0 H T 1HVYN
XYHINOd
YILOVHVHD
O4 1YY
YILOVHVH)
O4 LYY
SYIJWNT

H<0:/

SHIJWNAT

V13

AHV >=1VZH¢X1aYdd0zH334i:I,aH0N>OdH< 1Svz4N14vLvnNVaaLLS 0S Vi3LX3_00TS*AeHo z1+

L NGL H T041LNOD

l—l

NanSz

5.14.2

The DCO003 Interrupt Logic Circuits

Each serial-line unit has an associated DCO003 interrupt logic circuit that consists of an 18-pin package.
Each DCO003 provides two interrupt channels for receiver and transmitter interrupts. The receiver channel has a higher priority than the transmitter channel.

The receiver channel contains a read /write interrupt enable bit [RX1 IE (1) H or RX2 IE (1) H] that s
accessed as bit 06 of the receiver status register. LD RCSR1 H or LD RCSR2 H loads IDALB 06 H
into this interrupt enable bit.
The transmitter channel contains a read/write interrupt enable bit [TX1 IE (1) H or TX2 IE (1) H]
that is accessed as bit 06 of the transmitter status register. LD TCSR1 H or LD TCSR2 H loads K6
IDALB 06 H into the interrupt enable bit.

If the receiver interrupt enable bit and the receiver done bit (RX1 DONE H and RX2 DONE H) are
both set, or if the transmitter interrupt enable bit and the transmitter ready bit (TBMT1 H and TBMT?2
H) are both set, the open collector interrupt request output is asserted. The interrupt request outputs of
the two DCO0O03 circuits are tied together as DL IRQ L.
The F11 chip set and KDF11-BA logic respond to an SLU interrupt request (DL IRQ L asserted) by
reading the vector address. PT2 (1) L drives the DC003 BDIN inputs and activates all channels requesting an interrupt at that time. RD VEC L not only gates the vector address onto IDAL 07-00 H,
but also asserts the console DC003’s BIAKI input. If neither of the interrupt channels in this DCO003
were activated by PT2 (1) L, the DCO003 asserts its BIAKO output, which drives the BIAKI input of
the other DCO003. The actual vector address gated onto IDAL 07-00 H depends upon DLL1 VECB H,
DL1 IAKO H, DL2 VECB H, and DL2 ADRJ L. The selected interrupt channel is cleared.
5.14.3 Register Read Operations
Control signal RD RBUF1 L or RD RBUF2 L gates one of the receiver data buffers onto IDAL 07-00
H. Simultaneously, the assertions of ZB 15-12 L and ZB 11-08 L cause the zero bit assertion logic to
negate IDAL 15-08 H.

Control signal RD RCSR L gates either RX1 DONE H and RX1 IE (1) H or RX2 DONE H and RX2
IE (1) H onto IDAL 07-06 H and negates IDAL 02 H and IDAL 00 H. If LA 09 (1) H is asserted, the
console receiver status register signals are selected. In either case, the assertion of ZB 15-12 L, ZB
11-08 L, and K7 ZB 5-3A1 L causes the zero bit assertion logic to negate the remaining IDAL lines.
Control signal RD TCSR L gates either TBMT1 H and TX1 IE (1) H or TBMT2 H and TX2 IE (1) H
onto IDAL 07-06 H and negates IDAL 02 H and IDAL 00 H. If LA 09 (1) H is asserted, the console
transmitter status register signals are selected. In either case, the assertion of ZB 15-12 L, ZB 11-08 L,
and K7 ZB 5-3A1 L causes the zero bit assertion logic to negate the remaining IDAL lines.
5.14.4
Baud Rate Generator
|
A dual baud rate generator circuit contained in an 18-pin IC produces the RT CLK1 H and RT CLK2
H clocking signals for the two serial-line units if the J42—J43 and J45-J46 jumpers are installed.

The baud rate generator and —12 V Charge Pump are shown in Figure 5-13. The baud rate generator is
driven by a signal provided by a 5.0688 MHz crystal oscillator. The baud rate generator divides the
basic crystal oscillator frequency into one of 16 possible SLU receiver-transmitter frequencies. Four
switches for each serial line select the desired RT clock frequency, which is 16 times the desired SLU
baud rate. The switch configurations for selecting the available baud rates are listed in Table 2-10.

5-29

E114

?/vféL%HGE

DUAL BAUD

RATE GENERATOR

————o"0—— RO
$2-2

—— o—— R1
__S.fi/o____ R2
S2-4

J43

GENERATOR
#1

J42

J418

RTCLKTH

EXTCLKI H

52-5

"‘—‘—"’826 — T0

=== o"o—1T1
S2-8

GENERATOR

J46 J45 RTCLK2H _

1448 ExTcLkoH

= FDOO XTALT
XTALO

5.0688 MHZ

CRYSTAL
ose.

K10

Figure 5-13
5.14.5

k1o

DIVIDE

|21o~
J20

BY
16

MFG TEST

COUNTER

JUMPER

+12V
12V

317 KHZ

CHARGE

L & » 12V

PUMP

CLOCK FREQ

BAUD

(KHZ)

RATE

0.8

1.2

1.76

110

2.1562

134.5

150

4.8

300

9.6

600

19.2

1200

28.8

1800

32.0

2000

38.4

2400

57.6

3600

76.8

4800

115.2

7200

153.6

9600

307.2

19200

Baud Rate Generator and —12 V Charge Pump

Charge Pump Circuit

The serial-line EIA transmitter-receiver drivers require +12 V and —12 V operating power. The
charge pump circuit supplies the —12 V, thereby eliminating the need for backplane power other than
the standard +5 V and +12 V.

The input to the charge pump circuit is a 317 KHz square wave signal obtained from a divide-by-16
counter driven by the 5.0688 MHz crystal oscillator. The 317 KHz signal drives a pair of MHO0026
+12 V MOS clock drivers that alternately charge a 0.47 uF capacitor to —12 V.

5-30

CHAPTER 6
ADDRESSING MODES

6.1

INTRODUCTION

In the KDF11-BA all memory reference addressing is accomplished using the eight general-purpose
registers. In specifying an address of the data (operand address), one of the eight registers and one of
several addressing modes are selected. Each memory reference instruction specifies the following.
1.

Function to be performed (operation code).

General-purpose register to be used when locating the source and/or destination operand.

Addressing mode, which specifies how the selected registers are to be used.

Many capabilities are provided by the combination of the addressing modes and the instruction set. The
KDF11-BA is designed to handle structured data efficiently and with flexibility. The general-purpose
registers implement these functions in the following ways.

Act as accumulators — they hold the data to be manipulated.

Act as pointers — the content of the register is the address of the operand rather than the

Act as index registers — the content of the register is added to the second word of the instruction to produce the address of the operand. This capability allows easy access to variable

operand itself, allowing automatic stepping through memory locations.

entries in a list.

Utilization of the registers for both data manipulation and address calculation results in a variablelength instruction format. If registers alone are used to specify the data source, only one memory word
is required to hold the instruction. In certain modes, two or three words may be utilized to hold the
basic instruction components. Special addressing mode combinations enable temporary data storage for
convenient dynamic handling of frequently accessed data. This is known as stack addressing. (Programming techniques utilizing the stack are discussed in Chapter 10.) Register 6 is always used as the
hardware stack pointer (SP). Register 7 is used by the processor as its program counter (PC). Thus, the
register arrangement to be considered in conjunction with instructions and with addressing modes 1s:
registers 0—5 are general-purpose registers, register 6 is the hardware stack pointer, and register 7 is the
program counter. The full KDF11-BA instruction set and instruction formats are explained in Chapter
7. To illustrate clearly the use of the various addressing modes, the following instructions and symbols
are used in this chapter.

6-1

Mnemonic

Description

Octal Code

CLR

Clear (Zero the specified destination.)

0050DD

Clear byte (Zero the byte in the specified

1050DD

CLRB

destination.)
INC

Increment (Add 1 to contents of destination.)

0052DD

INCB

Increment byte (Add 1 to the contents of the
destination byte.)

1052DD

Complement (Replace the contents of the

0051DD

COM

destination by their logical 1’s
complements; each O bit is set and each
1 bit is cleared.)
COMB

Complement byte (Replace the contents of the
destination bytes by their logical 1’s

1051DD

complements; each O bit is set and each 1

bit is cleared.)
ADD

Add (Add the source operand to the

06SSDD

destination operand and store the result
at the destination address.)

6.2

= destination field (6 bits)

= source field (6 bits)

()

= contents of

INSTRUCTION FORMATS

The instruction format for the first word of all single-operand instructions (such as clear, increment,

test) 18 shown in Figure 6-1. The instruction format for the first word of the double-operand instruction
is shown in Figure 6-2.

MODE
i

|
J

OP CODE

#* 3%

I
*

—.*

—

DESTINATION ADDRESS

1
#* % #

—

___.{

LEGEND

*SPECIFIES DIRECT OR INDIRECT ADDRESS
** SPECIFIES HOW REGISTER WILL BE USED

¥*%* SPECIFIES ONE OF 8 GENERAL PURPOSE REGISTERS
MR-3643

Figure 6-1

Single-Operand Instruction Format

OP CODE
]

MODE
1

|
N

#* 3

]

Rn
3 %#

MODE

]
J

SOURCE ADDRESS

DESTINATION ADDRESS

i
YT

Rn
* 3% H

1
_

LEGEND

* SPECIFIES DIRECT OR INDIRECT ADDRESS

** SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED

ES REGISTER
A GENERAL
**#* SPECIFI

MR-3644

Figure 6-2

Double-Operand Instruction Format

ADDRESSING MODES

6.3

Instruction bits <<5:3> specify the binary code of the addressing mode chosen. The four direct ad-

dressing modes are as follows.
1.
2.

3.
4.

Autodecrement
Index

When bit 3 of the instruction is set, indirect addressing is specified and the four basic modes become
deferred modes. In a register-deferred mode the content of the selected register is taken as the address
of the operand. In the other deferred modes the content of the register specifies the address of the
operand, rather than the operand itself. Prefacing the register operand(s) with an @ sign or placing the
register in parentheses indicates to the MACRO-11 assembler that deferred addressing mode is being
L=

used. The indirect addressing modes are as follows.
Register-deferred
Autoincrement-deferred
Autodecrement-deferred
Index-deferred

Program counter (PC or register 7) addressing modes are as follows.
1.
2.
3.
4.

Immediate
Absolute
Relative
Relative-deferred

The KDF11-BA addressing modes are explained and shown in examples in the following pages. They
are summarized in Paragraphs 6.3.10 through 6.3.13.
6.3.1

trieve an operand. Any of the general registers can be used as accumulators. The operand is contained
in the selected register. Assembler syntax requires that a general register be defined as follows.
= %0
RO
= %1
R1
= %2
R2

The % sign indicates register definition.

Instruction

Symbolic

Octal Code

Description

INC R3

005203

Add 1 to the contents of R3.

RO
15

“

]

OP CODE (INC(0052))

1
|

SELECT

R1
Ro

DESTINATION FIELD

Figure 6-3

= ————

R4
R5

R6(SP)

R7(PC)

Instruction

Symbolic

Octal Code

Description

ADD R2, R4

060204

Add the contents of R2 to the contents of R4, replacing the
original contents of R4 with the sum.

BEFORE

AFTER

R2|

ooooo2

R2]

oooo02

R4|

ooooo4

R4|

oooO06

MR-3675

Figure 6-4

6.3.2

(Rn)

In register-deferred mode, the address of the operand is stored in a general-purpose register. The ad-

dress contained in the general-purpose register directs the CPU to the operand. The operand is located
outside the CPU, either in memory or in an /O register. This mode is used for sequential lists, indirect
pointers in data structures, top-of-stack manipulations, and jump tables.
Register-Deferred Mode Example (Figure 6-5.)

Instruction

Symbolic

Octal Code

Description

CLR (R)Y)

005015

The contents of the location specified in R5 are cleared.

BEFORE
ADDRESS SPACE

1677

Rs|

1700(

001700

1677

000100

1700

Figure 6-5
6.3.3

AFTER
ADDRESS SPACE

Autoincrement Mode (Mode 2)

Rs[

001700

000000

In autoincrement mode the register contains the address of the operand; the address is automatically
incremented after the operand is retrieved. The address then references the next sequential operand.
This mode allows automatic stepping through a list or series of operands stored in consecutive locations.
When an instruction calls for mode 2, the address stored in the register is autoincremented each time
the instruction is executed. It is autoincremented by 1 if byte instructions are being used, and by 2 if
word instructions are being used.
Autoincrement Mode Example (Figure 6-6.)

Instruction

Symbolic

Octal Code

Description

CLR (R5)+

005025

Contents of R5 are used as the address of the operand. Clear
selected operand and then increment the contents of R5 by 2.

BEFORE

AFTER

ADDRESS SPACE

20000/

005025

30000

111116

R5|

030000

ADDRESS SPACE

| 20000]

30000{

o0s02s

000000

Rs|

030002

MR-3677

Figure 6-6

6.3.4

Autoincrement Mode Example

Autoincrement-Deferred Mode (Mode 3)

@(Rn)-+

In autoincrement-deferred mode the register contains a pointer to an address. The + indicates that the
pointer in R2 is incremented by 2 after the address is located. Mode 2, autoincrement, is used to access
operands that are stored in consecutive locations. Mode 3, autoincrement-deferred, is used to access
lists of operands stored anywhere in the system; that is, the operands do not have to reside in adjoining
locations. Mode 2 is used to step through a table of volumes; mode 3 is used to step through a table of
addresses.

Autoincrement-Deferred Example (Figure 6-7.)

Instruction

Symbolic

Octal Code

Description

INC @(R2)+

005232

Contents of R2 are used as the address of the address of the
operand. The operand is increased by 1, and contents of R2
are incremented by 2.

BEFORE

AFTER

r2|

r2{ 010300 |
1010 [

ADDRESS SPACE

1012

010302

000026

1010[

000025

1012

001010

10300

001010

010300

MR-3678

Figure 6-7

6.3.5

Autoincrement-Deferred Mode Example

Autodecrement Mode (Mode 4)

—(Rn)

In autodecrement mode the register contains an address that is automatically decremented; the decremented address is used to locate an operand. This mode is similar to autoincrement mode, but allows
stepping through a list of words or bytes in reverse order. The address is autodecremented by 1 for

bytes, by 2 for words.

Autodecrement Mode Example (Figure 6-8.)

Instruction

Symbolic

Octal Code

Description

INCB —(RO)

105240

The contents of RO are decremented by 1, then used as the
address of the operand. The operand byte is increased by 1.

BEFORE

1000 oos240 |

AFTER

mo[

017776

ADDRESS SPACE

REGISTERS

ADDRESS SPACE

] 1000[ oos240 |

mo|

17774

|
17774

ooooo0 |

000001

017774 |
7

|
MR-3679

Figure 6-8

6.3.6

Autodecrement Mode Example

Autodecrement-Deferred Mode (Mode 5)

@—(Rn)

In autodecrement-deferred mode the register contains a pointer. The pointer is first decremented by 2,
then the new pointer is used to retrieve an address stored outside the CPU. This mode is similar to
autoincrement-deferred, but allows stepping through a table of addresses in reverse order. Each address
then redirects the CPU to an operand. Note that the operands do not have to reside in consecutive
locations.

Autodecrement-Deferred Mode Example (Figure 6-9.)
Instruction

Symbolic

Octal Code

Description

COM @—(RO)

005150

The contents of RO are decremented by 2, then used as the
address of the address of the operand. The operand is 1’s com-

plemented.

BEFORE

AFTER

ADDRESS SPACE

10100 |

012345

Ro|

010776

ADDRESS SPACE

| 10100

10102

165432

rRo|

o10774

10102

10774

010100

10774

10776

010100

10776

Figure 6-9

Autodecrement-Deferred Mode Example

6.3.7 Index Mode (Mode 6) X(Rn)
In index mode a base address is added to an index word to produce the effective address of an operand;
the base address specifies the starting location of a table or list. The index word then represents the
address of an entry in the table or list relative to the starting (base) address. The base address may be
stored in a register. In this case, the index word follows the current instruction. The locations of the
base address and index word may be reversed (index word in the register, base address following the
current instruction).
Index Mode Example (Figure 6-10.)

Instruction

Symbolic

Octal Code

Description

'CLR 200(R4)

005064

The address of the operand is determined by adding 200 to

000200

the contents of R4. The location is then cleared.

BEFORE

AFTER

ADDRESS SPACE

1020 {

005064

1022

000200

rRa|

001000

ADDRESS SPACE

1024

1020

005064

1022

000200

Ra|

001000

1024
1000

'/’\ +200
1200

177777

1200

000000

1202

MR-3681

Figure 6-10

Index Mode Example

6.3.8 Index-Deferred Mode (Mode 7) @X(Rn)
In index-deferred mode a base address is added to an index word. The result is the address of a pointer
to the address of the source operand, rather than the address of the source operand. This mode is similar to mode 6, except that it produces a pointer to an address. The content of that address then redirects the CPU to the desired operand. Mode 7 provides for the random access of operands using a table
of operand addresses.

6-7

Index-Deferred Mode Example (Figure 6-11.)

Instruction

Description

Octal Code

Symbolic

1000 and the contents of R2 are summed to produce the ad-

Add @1000(R2), R1]067201

dress of the source operand, the contents of which are added

001000

to the contents of R1. The result is stored in R1.

BEFORE

AFTER

ADDRESS SPACE

1020

067201

R1 [fi

1022

1opa.

001000

1050

000002

1100

001050

ADDRESS SPACE

001234 44_]

1020

067201

R1 [47 001236 4__]

oooto0

1022

001000

rR2[ oooto0 |

1050

000002

1100

001050

1000
+100
1100

MR-3682

Figure 6-11
6.3.9

Index-Deferred Mode Example

Use of the PC as a General Register

Register 7 is both a general-purpose register and the program counter. When the CPU uses the PC to
access a word from memory, the PC is automatically incremented by 2 to contain the address of the
next word in the instruction being executed or the address of the next instruction to be executed. When
the program uses the PC to access byte data, the PC is still incremented by 2.
The PC can be used with all the addressing modes. There are four modes in which the PC can provide
advantages for handling position-independent code (see Chapter 10) and unstructured data. These
modes are termed immediate, absolute (or immediate-deferred), relative, and relative-deferred. The remaining modes operate normally when used with the PC. However, they have no practical use in normal programming.

6.3.9.1

PC Immediate Mode (Mode 2)

Immediate mode is equivalent to using the autoincrement mode with the PC. It provides time improvements for accessing constant operands by including the constant in the memory location immediately

following the instruction word.

6-8

PC Immediate Mode Example (Figure 6-12.)

Instruction

Symbolic

Octal Code

Description

ADD #10, RO

062700

The value 10 is located in the second word of the instruction
and is added to the contents of RO. Just before this instruction
is fetched and executed, the PC points to the first word of the
instruction. The processor fetches the first word and increments the PC by 2. The source operand mode is 27 (autoincrement the PC). Thus, the PC is used as a pointer to
fetch the operand (the second word of the instruction) before
being incremented by 2 to point to the next instruction.

000010

AFTER

BEFORE

ADDRESS SPACE

1020

1022

062700

000010

rRo[

oooo20

ADDRESS SPACE

1020

062700

ro |

1022

000010

1024

‘//

000030

MR-3683

Figure 6-12

6.3.9.2

PC Absolute Mode (Mode 3)

PC Immediate Mode Example

@#A

This mode is the equivalent of immediate-deferred or autoincrement-deferred mode using the PC. The
contents of the location following the instruction are taken as the address of the operand. Immediate
data is interpreted as an absolute address (i.e., an address that remains constant no matter where in
memory the assembled instruction is executed).
PC Absolute Mode Example (Figure 6-13.)

|
Symbolic

Instruction
Octal Code

Description

CLR @#1100

005037
001100

Clears the contents of location 1100.

BEFORE

AFTER

ADDRESS SPACE

005037

001100

1100

177777

’

\ PC

1100

005037

001100

/ PC

000000

1102

MR-3684

Figure 6-13

PC Absolute Mode Example

6-9

6.3.9.3 PC Relative Mode (Mode 6) A
This mode is index mode 6, using the PC. The operand’s address is calculated by adding the word that
follows the instruction (called an “offset”) to the updated contents of the PC. PC+2 directs the CPU
to the offset that follows the instruction. PC+4 is summed with this offset to produce the effective
address of the operand. PC+4 also represents the address of the next instruction in the program.

With the relative addressing mode, the address of the operand is always determined with respect to the
updated PC. Therefore, when the instruction is relocated, the operand remains the same relative distance away. The distance between the updated PC and the operand is called an offset. After a program
is assembled, this offset appears in the first word location that follows the instruction. This mode is
useful for writing position-independent code (see Chapter 10).
PC Relative Mode Example (Figure 6-14.)

Instruction

Symbolic

INC A

Octal Code

Description

005267
000054

To increment location A, the contents of the memory location
in the second word of the instruction are added to the PC to
produce address A. The contents of A are increased by 1.

BEFORE

AFTER

ADDRESS SPACE
1020

005267

1022

000054

ADDRESS SPACE
1020

1024

0005267

1022

000054

1024

1026

<— PC

1026

1100 [

000000

1024

+54

1100[

\_/ 1o

)

oooo01

MR-3685

Figure 6-14

6.3.9.4

PC Relative Mode Example

PC Relative-Deferred Mode (Mode 7)

This mode is index-deferred (mode 7), using the PC. A pointer to an operand’s address is calculated by
adding an offset (that follows the instruction) to the updated PC.

This mode is similar to the relative mode, except that it involves one additional level of addressing to
obtain the operand. The sum of the offset and updated PC (PC+4) serves as a pointer to an address.
When the address is retrieved, it can be used to locate the operand.

PC Relative-Deferred Mode Example (Figure 6-15.)

Instruction

Symbolic

CLR @A

Octal Code

Description

005077
000020

Adds the second word of the instruction to the PC to produce
the address of the address of the operand. Clears the operand.

1020

BEFORE

AFTER

ADDRESS SPACE

005077

1022

000020

1020

\ PC

005077

1022

1024

000020

/ PC

1024
I

1024

1044 ,L 010100

]

10100 lr 100001

1044 r 010100 j

10100 |

oooooo

|
MR-3686

Figure 6-15
6.3.10

PC Relative-Deferred Mode Example

Direct Addressing Modes Summary

Table 6-1 summarizes the four basic modes used with direct addressing.
Table 6-1

Direct Addressing Modes

Binary

Code

Mode

Name

000

010

Autoincrement

(Rn)+

100

Autodecrement

—(Rn)

110

Index

X(Rn)

6.3.11

Symbolic

Function

quential data, then is incremented.

as a pointer to sequential data.

Value X is added to (Rn) to produce

address of operand. Neither X nor
(Rn) 1s modified.

Indirect Addressing Modes Summary

Table 6-2 summarizes the same four basic modes used with indirect addressing.

6-11

Table 6-2

Indirect Addressing Modes

Binary

Code

Mode

Name

Symbolic

Function

001

@Rn or (Rn) | Register contains the address of the
operand.

011

Autoincrement-deferred | @(Rn)+

operand, then is incremented (always
by 2, even for byte instructions).

101

Autodecrement-deferred | @—(Rn)

the address of the operand.

111

Index-deferred

@X(Rn)

Value X (located in a word contained
in the instruction)

and

(Rn)

are

added and the sum 1is used as

pointer to a word containing the address of the operand. Neither X nor

(Rn) 1s modified.

6.3.12

PC Register Addressing Modes Summary

When used with the PC, these modes are termed immediate, absolute (or immediate-deferred), relative,
and relative-deferred. They are summarized in Table 6-3.

Table 6-3

PC Register Addressing Modes

Binary

Code

Mode

Name

Symbolic

010

Immediate

Function
Operand

1is

contained

the

instruction.

011

Absolute

@#A

Absolute address is contained in the
instruction.

110

Relative

Address of A, relative to the instruc-

111

Relative-deferred

Address of location containing ad-

tion, 1S contained in the instruction.

dress of A, relative to the instruction,
1s contained 1n the instruction.

6.3.13

Graphic Summary of Addressing Modes

Figures 6-16 and 6-17 provide a graphic summary of general register addressing modes and program
counter addressing modes.

Mode O

OPR P

R contains operand.

OPR (R)

R contains address.

INSTRUCTIONH OPERAND
Mode 1

INSTRUCTIOU——»{
Mode 2

ADDRESS J———-L

OPERAND ]

Autoincrement

OPR (R)+

R contains address,
then increment (R).

IINSTRUCTIQNH ADDRESS

I——’l

OPERAND J

.| +2 FOR WORD,
"1 +1 FORBYTE

Mode 3

Autoincrement

OPR @(R)+

R contains address of address,

deferred

then increment (R) by 2.

FNSTRUCT!ONH ADDRESS j———’lfi ADDRESS H OPERAND J
[

—|

Mode 4

Autodecrement

OPR -(R)

Decrement (R), then
R contains address.

INSTRUCTIOI\L}———’I ADDRESS

Mode 5

-2 FOR WORD,
J——»I 1
FOR BYIE

Autodecrement
deferred

INSTRUCTIONH ADDRESS

Mode 6

OPERAND J

OPR @- (R)

Index

—»I

Decrement (R) by 2, then R
contains address of address.

ADDRESS H OPERAND J

OPR X(R)

(R)+X is address, second

word of instruction.

'
R

PC [ INSTRUCTION }——[ ADDRESS

OPERAND
PC+2 [

Mode 7

]

1|
Index deferred

OPR @X(R)

(R)+X is address (second
word) of address.

PC FINSTRUCTION }-——{ ADDRESS
ADDRESS
PC+2 |

l-——a[ OPERAND J

R is a general register, 0 to 7.
(R) is the contents of that register.
MR-3687

Figure 6-16

General Register Addressing Modes

6-13

Mode 2

Immediate

OPR #n

Literal operand n is contained in the instruction.

PC [ lNSTRUCTION]
PC+2 I

Mode 3

Absolute

OPR @#A

Address A is contained in the instruction.

PC DNSTRUCTIOM

PC+2[

]-——0{

Mode 6

OPERAND

Relative

]
OPR A

PC+4+X is address.
PC+4 is updated PC.

INSTRUCTIONJ

PC+2 l

OPERAND

]

PC+4 [ NEXT INSTRJ

Mode 7

Relative deferred

OPR @A

PC+4+X is address of address PC+4 is updated PC.

PC [ INSTRUCTION ]
PC+2 I

ADDRESS

OPERAND]

Figure 6-17

Program Counter Addressing Modes

6-14

CHAPTER 7

INSTRUCTION SET

7.1

INTRODUCTION

The KDF11-BA instruction set and addressing modes produce over 400 unique instructions. The instruction set offers a wide choice of operations, and often a single instruction will accomplish a task that
would require several instructions in a traditional computer.
KDF11-BA instructions allow byte and word addressing in both single- and double-operand formats.
This saves memory space and simplifies the implementation of control and communications applications. The use of double-operand instructions makes it possible to perform several operations with a
single instruction. For example, ADD A,B adds the contents of location A to location B and stores the
result in location B. Traditional computers would implement these operations with three instructions:
LDA A
ADD B

STR B

The instruction set contains a full set of conditional branches, eliminating excessive use of jump instructions. All instructions fall into one of three categories.

Single-Operand — One part of the word, referred to as “op code,” specifies the operation; the
second part provides information for locating the operand.

Double-Operand — The first part of the word specifies the operation to be performed; the
remaining two parts provide information for locating two operands.

Program Control — The first part of the word specifies the operation to be performed; the
second part indicates where the action is to take place in the program.

7.1.1
Single-Operand Instructions
The following is a list of single-operand instructions.
General

Mnemonic

Instruction

CLR(B)
COM(B)
INC(B)
DEC(B)
NEG(B)
TST(B)

Clear destination
1’s complement destination
Increment destination
Decrement destination
2’s complement negate destination
Test destination

7-1

Shift and Rotate

Mnemonic

Instruction

ASR(B)
ASL(B)

Arithmetic shift right
Arithmetic shift left
Rotate right
Rotate left
Swap bytes

ROR(B)
ROL(B)
SWAB

Multiple-Precision
Mnemonic

Instruction

ADC(B)
SBC(B)
SXT

Add carry
Subtract carry
Sign extend

Processor Status
Mnemonic

Instruction

MFPS
MTPS

Move byte from processor status
Move byte to processor status

Instruction Format — The instruction format for single-operand instructions, as shown in Figure 7-1, is
described as follows.

Bits 15-6 indicate the operation code, which specifies the operation to be performed. (Bit 15
indicates word or byte operation.)

Bits 5-0 indicate the destination address, which gives information on locating the operand.

>
<

OP CODE

__...fi

MODE

DESTINATION ADDRESS
LEGEND

*SPECIFIES DIRECT OR INDIRECT ADDRESS

*# SPECIFIES HOW REGISTER WILL BE USED

*** SPECIFIES ONE OF 8 GENERAL PURPOSE REGISTERS
MR-3643

Figure 7-1

Single-Operand Instruction Format

7.1.2

Double-Operand Instructions

The following is a list of double-operand instructions.
General

Mnemonic

Instruction

MOV (B)
ADD
SUB
ASH
ASHC
MUL
DIV

Move source to destination
Add source to destination
Subtract source from destination
Shift arithmetically
Arithmetic shift combined
Integer multiply
Integer divide

Logical

Mnemonic

Instruction

BIT(B)
BIC(B)
BIS(B)

Bit test
Bit clear
Bit set

Exclusive OR

XOR

7.1.2.1 Double-Operand Instruction Format — The format of most double-operand instructions (see
Figure 7-2) is similar to that of single-operand instructions except that the former have two fields for
locating operands. One field is called the source field, the other is called the destination field. Each
field is further divided into addressing mode and selected register. Each field is also completely independent. The mode and register used by one field may be completely different from the mode and register used by another field.

OP CODE
|

MODE
1

MODE
]

SOURCE ADDRESS
DESTINATION ADDRESS
LEGEND

* SPECIFIES DIRECT OR INDIRECT ADDRESS
## SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED

### SPECIFIES A GENERAL REGISTER

MR-3644

Figure 7-2

Double-Operand Instruction Format

Bit 15 indicates word or byte operation except when used with op code 6. Then it indicates an ADD or
SUBtract instruction. Bits 14—12 indicate the op code, which specifies the operation to be done. Bits
]11-6 indicate the source address, which contains information for locating the source operand. Bits 5-0
indicate the destination address, which contains information for locating the source operand.

7.1.2.2

Byte Instructions — Byte instructions are specified by setting bit 15. Thus, in the case of the

MOV instruction, bit 15 is 0; when bit 15 is set, the mnemonic is MOVB. There are no byte operations

for ADD and SUB - that is, no ADDB or SUBB. In order to perform the equivalent of an ADDB or
SUBB, the MOVB instruction can be used along with an ADD or SUB. The MOVB instruction, when
the destination address mode is 0, sign-extends the byte operand through the high byte of the register.
This feature can be used by executing a MOVB to get the first byte operand and place it in one general
register, and another MOVB to get the second byte operand and place it in a second general register.
Then an ADD or SUB is performed on both general registers.
MOVB A,R0O
MOYVB B,R1
ADD RO,R1

The condition codes will be affected based upon the byte result.
7.1.3

Program Control Instructions

This paragraph discusses program control instructions.
7.1.3.1

Branch Instructions — What follows 1s a list of branch instructions and a discussion of the

branch instruction format.
Branch

Mnemonic

Instruction

Branch (unconditional)

BNE

Branch if not equal to 0

BEQ

Branch if equal to 0

BPL

Branch if plus

BMI

Branch if minus

BVC

Branch if overflow is clear

BVS

Branch if overflow is set

BCC

Branch if carry is clear

BCS

Branch if carry is set

Signed Conditional Branch

Mnemonic

Instruction

BGE

Branch if greater than or equal to 0

BLT

Branch if less than O

BGT

Branch if greater than O

BLE

Branch if less than or equal to 0

SOB

Subtract 1 and branch if not equal to 0

Unsigned Conditional Branch
Mnemonic

Instruction

BHI

Branch if higher

BLOS
BHIS

Branch if lower or same
Branch if higher or same

BLO

Branch if lower

Branch Instruction Format

The high byte (bits 8—15) of the instruction is an op code specifying the conditions for the branch to
take place. Refer to Figure 7-3.

OP CODE

BYTE OFFSET

MR-3645

Figure 7-3

Branch Instruction Format

The low byte (bits 0-7) of the instruction is the offset value in words that determines the new program
location if the branch is taken. The low byte is treated as an 8-bit signed integer, and since the CPU is
byte-organized, the integer must be converted from words to bytes. This is done during execution by
sign-extending the low byte and then shifting the 16-bit word left one position to create the offset in
bytes. Then the offset is added to the current value of the PC to form the new program location if the
branch is taken. Since the PC is always incremented by two bytes immediately after the instruction is
fetched, the current value of the PC, when the new program location is formed, points to the next location after the branch. Hence an unconditional branch to its own location is 000777g, rather than
00040g, which is a branch to the next location.

7.1.3.2 Jump and Subroutine Instructions — The following is a list of jump and subroutine instructions,
and a discussion of their formats. A list of related interrupt and trap instructions is also provided, along

with a list of ways to exit from a main program.
Jump and Subroutine

Mnemonic

Instruction

JMP
JSR

Jump
Jump to subroutine

Return from subroutine

RTS

JSR Instruction Format

Bits 9—15 are always octal 004 indicating the op code for

JSR. Refer to Figure 7-4.

MODE

LINKAGE REGISTER
DESTINATION ADDRESS
MR-3646

Figure 7-4

JSR Instruction Format

7-5

Bits 6—8 specify the link register. Any general-purpose register may be used in the link, except R6. Bits
0-5 designate the destination address that consists of addressing mode and general register fields. This
specifies the starting address of the subroutine.
Register R7 (program counter) is frequently used for both the link and the destination. For example,
JSR R7, SUBR, which is coded 004767, may be used. R7 is the only register that can be used for both
the link and destination, the other general-purpose registers (GPRs) cannot. Thus, if the link is R5, any
register except R5 can be used in the destination field.
RTS Instruction Format

The RTS (return from subroutine) instruction uses the link to return control to the main program once
the subroutine is finished. Refer to Figure 7-5.

0
1

0
|

0
i

0
]

0
|

0
]

0
|

1
1

0
|

0
1

0
]

Rn
i

LINKAGE REGISTER

0
|
.

Y-

OP CODE

T
MR-3647

Figure 7-5

RTS Instruction Format

Bits 3—15 always contain octal 00020, which is the op code for RTS. Bits 0-2 specify any one of the
general-purpose registers. The register specified by bits 0—2 must be the same register as the one used
in the JSR that called the subroutine.
Interrupts and Traps
Mnemonic

Instruction

EMT

Emulator trap

TRAP

Trap

BPT

Breakpoint trap

10T
RTI

Input/output trap
Return from interrupt

RTT

Return from trace trap

Exiting from a Main Program

There are three ways to leave a main program.
1.

Software Exit — The program specifies a jump to some subroutine.

Trap Exit — Internal processor hardware executes certain instructions (e.g., EMT) that cause
a jump to special software routines.

Interrupt Exit — External hardware forces a jump to an interrupt service routine.

In all of the above cases, there 1s a jump to another program. Once that program has been executed,

control is returned to the proper point in the main program.

7-6

7.1.3.3 Condition Code Instructions — The following is a list of instructions that affect the condition
codes in the PS, and their formats. How the condition codes are affected is also discussed.
Mnemonic

Instruction

CLC, CLV, CL2

Clear selected condition code

CLN, CCC

SEC, SEV, SEZ

Set selected condition code

SEN, SCC

Instruction Format

The format of the condition code operators, shown in Figure 7-6, is as follows.
1.

Bits 15-5 — The operation code.

Bit 4 — The “operator” that indicates set or clear with the values 1 and 0, respectively. If set,
any selected bit is set; if clear, any selected bit is cleared.

Bits 3—0 — The “select” field. Each of these bits corresponds to one of the four condition code
bits. When one of these bits is set, the corresponding condition code bit is set or cleared depending on the state of the “operator” (bit 4).

CONDITION CODE OPERATORS

]

OP CODE

0/1

|
J

OPERATOR

SELECT FIELD
MR-3648

Figure 7-6

Condition Code Operators Format

More than one condition code can be set by a particular instruction. For example, both a carry and an

overflow condition may exist after instruction execution.
Condition Codes

There are four condition code bits.
1.
2.
3.
4.

N indicates a negative condition when set to 1.
7 indicates a zero condition when set to 1.
V indicates an overflow condition when set to 1.
C indicates a carry condition when set to 1.

These four bits are part of the processor status word (PS). The result of any single-operand or doubleoperand instruction affects one or more of the four condition code bits. A new set of condition codes is
usually created after execution of each instruction. Some condition codes are not affected by the execution of certain instructions. Branch instructions may test the condition codes after execution of a singleor double-operand instruction. The condition codes are used by the various instructions to check software conditions.

7-17

N Bit

The CPU looks only at the sign bit of the result. If the sign bit is set, indicating a negative value, the
CPU sets the N bit. If the sign bit is clear, indicating a positive value, the CPU clears the N bit. When
an overflow occurs (V bit is set), the N bit does not indicate the true sign of the result since the N bit is
equal to bit 15 of the result.
Z. Bit

Whenever the CPU sees that the result of an instruction is 0, it sets the Z bit. If the result is not O, it
clears the Z bit. There are a number of ways of obtaining a O result.
1.
2.
3.

Adding two numbers equal in magnitude but different in sign.
Comparing two numbers of equal value.
Using the CLR instruction.

V Bit

The V bit is set to indicate that an overflow condition exists. An overflow means that the result of an
instruction is too large to be represented in 2’s complement format. There are two methods the hardware uses to check for an overflow condition.
One way 1s for the CPU to test for a change of sign.
1.

When using single-operand instructions, such as INC, DEC, or NEG, a change of sign indicates an overflow condition.

When using double-operand instructions, such as ADD, SUB, or CMP, in which both the
source and destination have like signs, a change of sign in the result indicates an overflow
condition.

Another method used by the CPU is to test the N bit and C bit when dealing with shift and rotate
instructions.

1.
2.
3.

If only the N bit is set, an overflow exists.
If only the C bit is set, an overflow exists.
If both the N and C bits are set, there is no overflow condition.

C Bit

The CPU sets the C bit automatically when the result of an instruction has caused a carry-out of the
most significant bit of the result. When the instruction results in a carry-out of the most significant bit
of the result, the carry itself is usually moved into the C bit. Otherwise, the C bit is cleared. During
rotate instructions (ROL and ROR), the C bit forms a buffer between the most significant bit and the
least significant bit of the word. A carry of 1 sets the C bit while a carry of O clears the C bit. However,
there are exceptions.

SUB and CMP set the C bit when there is no carry to indicate that a borrow occurred.

Logical operations (e.g., BIT) do not affect the C bit since they are not arithmetic in nature.

COM always sets the C bit, TST always clears the C bit.

7-8

7.1.3.4

Miscellaneous Instructions — Miscellaneous program control instructions are listed below.

Mnemonic

Instruction

HALT
WAIT
RESET
MTPD

Halt
Wait for interrupt
Reset 1/0
Move to previous data space

MTPI
MFPD
MFPI
MTPS
MFPS

Move to previous instruction space
Move from previous data space
Move from previous instruction space
Move byte to processor status word
Move byte from processor status word

7.1.4 Examples of Single-Operand, Double-Operand, and Branch Instructions
The following examples and explanations show the use of the various types of instructions in a program.

7.1.4.1
Single-Operand Instruction Example — This routine uses a tally to control a loop, which clears
out a specific block of memory. The routine has been set up to clear 30g byte locations beginning at
memory address 600.
(RO) = 600
(R1) = 30
LOOP:

CLRB(R0)+
DEC R1
BNE LOOP
HALT

Program Description
The CLRB (RO)+ 1nstruction clears the contents of the location specified by R0O. RO is the pointer.
Because the autoincrement addressing mode is used, the pointer automatically moves to the next memory location after execution of the CLRB instruction.

Register R1 indicates the number of locations to be cleared and is, therefore, a counter. Counting is
performed by the R1 instruction. Each time a location is cleared, it i1s counted by decrementing R1.
The branch if not zero (BNE) instruction checks for Done. If the counter is not 0, the program
branches back to start to clear another location. If the counter i1s 0, indicating Done, the program executes the next instruction, HALT.
7.1.4.2 Double-Operand Instruction Example — This routine prints out a portion of a payroll program
for review by the supervisor. It is known that 76 locations are to be printed and the locations start at

address 600.
INIT:

MOV #600,R0

MOV #76,R1
START:

TSTB I/0
BPL START

MOVB (RO)+,1/O
+2
DEC RI
BNE START
HALT

7-9

Program Description

MOV is the instruction normally used to set up the initial conditions. Here, the first MOV places the
starting address (600) into RO, which will be used as a pointer. The second MOV sets up RI as a
counter by loading the desired number of locations (76) to be printed.

The TSTB instruction tests the Done or Ready flag (bit 7) of the printer. The BPL instruction causes a
loop to start if the state of the Printer-ready flag is cleared.

The MOVB instruction moves a byte of data to the printer (I1/O) for printing. The data comes from the
location specified by RO. The pointer RO is incremented to point to the next sequential location, and the
counter (R1) is decremented to indicate one byte has been transferred.

The program then checks the loop for Done with the BNE instruction. If the counter has not reached 0,
more transfers must take place. The BNE causes a branch back to START and the program continues.
When the counter (R1) reaches 0, indicating all data has been transferred, the branch does not occur
and the program executes the next instruction, HALT.
7.1.4.3

Branch Instruction Example
NOTE

Branch instruction offsets are limited to be from
+177g to —200g words.

A payroll program has set up a series of words to identify each employee by his/her badge number. The
high byte of the word contains the employee’s badge number; the low byte contains an octal number
ranging from O to 13 that represents his/her salary. These numbers represent steps within three wage
classes to identify which employees are paid weekly, monthly, or quarterly. It is time to make out weekly paychecks. Unfortunately, employee information has been stored in a random order. The problem is
to extract the names of only those employees who receive a weekly paycheck. Employee payroll numbers are assigned as follows: 0 to 3 — wage class I (weekly); 4 to 7 — wage class II (monthly); 10 to 13 —

wage class III (quarterly).

The starting address of the memory block containing the employee payroll information is 600. The final
address of this data area is 1264. The following program searches through the data area and finds all
numbers representing wage class I. Each time one is found, the program stores the employee’s badge
number (just the high byte) on a “last-in/first-out” stack that begins at location 4000.
INIT:

START:

MOV #600, RO
MOV #400, R1

CMPB(RO)+,#3
BHI CONT

STACK:

MOVB (R0),—(R1)

CONT:

INC RO
CMP # 1264, RO
BHIS START
HALT

7-10

Program Description

RO becomes the address pointer, R1 the stack pointer. Compare the contents of the first low byte with
the number 3 and go to the first high byte. If the number is more than 3, branch to continue. If no
branch occurs, the number is 3 or less. Therefore, move the high byte containing the employee’s number onto the stack as indicated by stack pointer R1. RO is advanced to the next low byte. If the last
address (1264) has not been examined, this instruction produces a result equal to or greater than zero.
If the result is equal to or greater than zero, examine the next memory location.
7.2

INSTRUCTION SET

The KDF11-BA instruction set is described below. For ease of reference the instructions are presented
alphabetically. A number of special symbols are used to describe certain features of individual instructions. The commonly used symbols are explained in Table 7-1.

Table 7-1

Instruction Symbols

Symbol

Meaning

Single-operand instruction.

Double-operand instruction.

Program control instruction.

Miscellaneous instruction.

Condition code.

Indicates “the contents of”’; for example, (R5) means “the contents of R5.”

SIC

Source address.

dst

—

Destination address.

Becomes, or moves into; for example, (dst) «— (src) means that the source becomes the

destination or that the source moves into the destination location.

(SP) +

Popped or removed from the hardware stack.

— (SP)

Pushed or added to the hardware stack.

Logical AND.

Logical inclusive OR (either one or both).

Logical exclusive OR (either one, but not both).

Logical NOT.

Reg or

R |

Byte.

NOTE

Condition code bits are considered to be cleared unless they are specifically listed as set.

ADC/ADCB

Add carry

0055DD

1055DD

15
0/1

0
|

0
l

1
|

0
|

1
L

1
]

0
|

00
D
|

Type:

Operation:

(dst) — (dst) + C

Condition Codes:

N: set if result << O
Z: set if result = 0O
V: set if (dst) is 077777 and C = 1
C: set if (dst) 1s 177777 and C = 1

D
|

D
L

D
|

D
J

Adds the contents of the C bit to the destination. This permits the carry from the

Description:

addition of the low-order words/bytes to be carried into the high-order result,

such as in performing double-precision arithmetic.

ADD

06SSDD
15

1
|

S
1

S
|

S
]

S
|

D
|

D
1

D
]

Add

Type:

Operation:

(dst) «— (src) + (dst)

Condition Codes:

N: set if result << O
Z: set if result = O

V: set if there is arithmetic overflow as a result of the operation; that is, both
operands were of the same sign and the result is of the opposite sign

C: set if there is a carry from the most significant bit of the result
Description:

Adds the source operand to the destination operand and stores the result at the
destination address. The original contents of the destination are lost. The contents of the source are not affected. 2’s complement addition is performed.

7-12

ASH

072RSS

Arithmetic shift

S
J

]

S
|

]

1
|

MR-.2720

Type:

Operation:

R — R shifted arithmetically NN places to the right or left where NIN = (src)

Condition Codes:

N: set if result << O
Z: set if result = O

V: set if sign of register changed during shift
C: loaded from last bit shifted out of register

The contents of the register are shifted right or left the number of times speci-

Description:

fied by the source operand. The shift count is taken as the low-order six bits of
the source operand. This number ranges from —32 to +31. Negative is a right
shift and positive is a left shift.

ASHC

073RSS

Arithmetic shift combined
15

Type:

Operation:

Condition Codes:

R
|

00
|

S
|

)

R,LRV1I—R RVI

The double word is shifted NN places to the right or left, where NN = (src).
N: set if result < O
Z: set if result = 0

V: set if sign bit changes during the shift

C: loaded with high-order bit when left shift; loaded with low-order bit when
right shift (loaded with the last bit shifted out of the 32-bit operand)
Description:

The contents of the register and the register ORed with 1 are treated as one 32bit word. R \V 1 (bits 0-15) and R (bits 16-31) are shifted right or left the number of times specified by the shift count. The shift count is taken as the low-order

six bits of the source operand. This number ranges from —32 to 4+ 31. Negative
is a right shift and positive is a left shift.

When the register chosen is an odd number, the register and the register ORed
with 1 are the same. In this case, the right shift becomes a rotate. The 16-bit
word 1s rotated right the number of bits specified by the shift count.

ASL/ASLB
0063DD

Arithmetic shift left

1063DD

MR-2722

Type:

Operation:

(dst) — (dst) shifted one place to the left

Condition Codes:

N: set if high-order bit of the result < 0
Z.: set if the result = 0
V: loaded with the exclusive OR of the N bit and C bit (as set by the completion

of the shift operation)
C: loaded with the high-order bit of the destination
Shifts all bits of the destination left one place. The low-order bit is loaded with a

Description:

0. The C bit of the status word is loaded from the high-order bit of the destination. ASL performs a signed multiplication of the destination by 2 with overflow
indication.

ASR/ASRB

Arithmetic shift right

0062DD

1062DD

MR-2723

7-14

Type:

Operation:

(dst) «— (dst) shifted one place to the right

- Condition Codes:

N: set if the high-order bit of the result is set (result << 0)
Z: set if the result = O

V: loaded from the exclusive OR of the N bit and C bit (as set by the completion
of the shift operation)

C: loaded from low-order bit of the destination

Shifts all bits of the destination right one place. The high-order bit is replicated.

Description:

The C bit is loaded from the low-order bit of the destination. ASR performs signed division by 2.

BCC

Branch if carry clear

103000

OFFSET
L

1
1

Type:

Operation:

PC — PC + (2 X offset) if C = 0

Condition Codes:

N: unaffected

Description:

Tests the state of the C bit and causes a branch if C is clear.

Z: unaffected
V: unaffected
C: unaffected

BCS
103400

Branch if carry set

OFFSET

|
MR-2725

7-15

Type:

Operation:

Condition Codes:

N: unaffected

— PC + (2

X offset) if

Z: unaffected
V: unaffected

C: unaffected
Description:

Tests the state of the C bit and causes a branch if C is set. Used to test for a
carry in the result of a previous operation.

BEQ

Branch if equal

001400

OFFSET
1
MR-2726

Type:

Operation:

PC — PC + (2 X offset) if
Z = 1

Condition Codes:

N: unaffected
Z: unaffected

V: unaffected

C: unaffected
Description:

Tests the state of the Z bit and causes a branch if Z is set. As an example, it is
used to test equality following a CMP operation, to test that no bits set in the

destination were also set in the source following a BIT operation, and, generally,
to test that the result of the previous operation was O.

BGE

Branch if greater than or equal

002000

OFFSET
]

|
MR-2727

7-16

Type:

Operation:

PC — PC + (2 X offset) it N % V =0

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Causes a branch if N and V are either both clear or both set. BGE 1s the complementary operation to BLT. Thus, BGE always causes a branch when it follows an operation that caused addition of two positive numbers. BGE also causes
a branch on a 0 result.

BGT

Branch if greater than

003000

]

OFFSET

Type:

Operation:

PC — PC + (2 X offset) if Z V (N ¥ V) =0

Condition Codes:

N: unaffected

Z: unaffected
V: unaffected
C: unaffected

Description:

Causes a branch if the exclusive OR of the N and V bits is 1. Thus, BGT always
branches after an operation that added two negative numbers, even if overflow
occurred. In particular, BGT always causes a branch if it follows a CMP instruction operating on a negative source and a positive destination (even if overflow

occurred). Further, BGT never causes a branch when it follows a CMP instruc-

tion operating on a positive source and negative destination. BGT does not cause
a branch if the result of the previous operation was 0 (without overflow).

7-17

BHI

Branch if higher

101000
15

OFFSET

Operation:

PC — PC + (2 X offset) if
~
-

Type:

Condition Codes:

C =0and Z = 0

N: unaffected
7 unaffected
V: unaffected
C: unaffected

Description:

Causes a branch if the previous operation causes neither a carry nor a 0 result.
This will happen in comparison (CMP) operations as long as the source has a
higher unsigned value than the destination.

BHIS

Branch if higher than the same

103000

]

Operation:

PC — PC + (2 X offset) if

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

OFFSET

Type:

Description:

0
|

C = 0

Tests the state of the C bit and causes a branch if C is cleared.

BIC/BICB
Bit clear

04SSDD
14SSDD
15

0/1

1
]

0
]

S
1

S
L

S
1

S
i

D
1

D
L

D
1

D
1
MR-2731

Type:

Operation:

(dst) «— ~ (src) /A (dst)

Condition Codes:

N: set if high-order bit of result set

Description:

Clears each bit in the destination that corresponds to a set bit in the source. The
original contents of the destination are lost. The contents of the source remain

Z: set if result = O
V: cleared
C: not cleared

unaffected.

BIS/BISB

05SSDD

Bit set

15SSDD

0/1

]

s|{bpb

Type:

Operation:

(dst) « (src) VV (dst)

Condition Codes:

N: set if high order bit of result set

Description:

Performs an inclusive OR operation between the source and destination operands

Z: set if result = 0
V: cleared
C: not affected

and leaves the result at the destination address; i.e., corresponding bits set in the
source are set in the destination. The original contents of the destination are lost.

BIT/BITB

03SSDD

Bit test

13SSDD

0/1

Type:

Operation:

(dst) V (src)

00
|

]

Condition Codes:

N: set if high-order bit of result set
Z: set if result = 0
V: cleared

C: not affected

Description:

Performs a logical AND comparison of the source and destination operands and
modifies condition codes accordingly. Neither the source nor destination operands are affected. The BIT instruction may be used to test whether any of the
corresponding bits that are set in the destination are clear in the source.

BLE

Branch if less than or equal to

003400

OFFSET

Type:

Operation:

PC — PC + (2 X offset) if Z V (N ¥ V) = 1

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

]

Causes a branch if the exclusive OR of the N and V bits is 1. Thus, BLE always

branches after an operation that added two negative numbers, even if overflow
occurred. In particular, BLE always causes a branch if it follows a CMP instruc-

tion operating on a negative source and a positive destination (even if overflow
occurred). Further, BLE never causes a branch when it follows a CMP instruction operating on a positive source and negative destination. BLE does not cause
a branch if the result of the previous operation was O (without overflow).

BLO

Branch if lower

103400

0
|

1
]

1
1

OFFSET

|
MR-27356

Type:

Operation:

PC
— PC + (2 X offset) ifC = 1

7-20

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Tests the state of the C bit and causes a branch if C is set. Used to test for a
carry in the result of a previous operation.

BLOS

101400

Branch if lower or same
OFFSET

]

Type:

Operation:

PC —PC 4+ (2 X offset) if

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

]

CV Z =1

Causes a branch if the previous operation caused either a carry or a 0 result.
BLOS is the complementary operation to BHI. The branch occurs in comparison
operations as long as the source is equal to or has a lower unsigned value than the
destination.

BLT
002400

Branch if less than
08

]

0
|

OFFSET

]

|
MR-2737

Type:

Operation:

PC — PC + (2 X offset) if
- unaffected
- unaffected
- unaffected
. unaffected

O<NZ

Condition Codes:

NV V =1

7-21

Causes a branch if the exclusive OR of the N and V bits is 1. Thus, BLT always

Description:

branches after an operation that added two negative numbers, even if overflow
occurred. In particular, BLT always causes a branch if it follows a CMP instruction operating on a negative source and a positive destination (even if overflow
occurred). Further, BLT never causes a branch when it follows a CMP instruction operating on a positive source and negative destination. BLT does not cause
a branch if the result of the previous operation was 0 (without overflow).

BMI

Branch if minus

100400
08

]

OFFSET

]

|
MR-2738

Type:

Operation:

PC — PC + (2 X offset) ifN = 1

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected
Tests the state of the N bit and causes a branch if N is set. Used to test the sign

Description:

(most significant bit) of the result of the previous operation.

BNE
Branch if not equal

001000

0
!

0
L

0
]

0
|

1
1

OFFSET

|
MR-2739

Type:

Operation:

PC — PC + (2 X offset) ifZ = 0

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Tests the state of the Z bit and causes a branch if the Z bit is clear. BNE is the
complementary operation to BEQ. It is used to test inequality following a CMP,

to test that some bits set in the destination were also in the source, following a
bit, and, generally, to test that the result of the previous operation was not O.

7-22

BPL

Branch if plus

100000
08

0
|

0
!

0
|

0
]

OFFSET

|
MR-2740

Type:

Operation:

PC — PC + (2 X offset) ifN = 0

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Tests the state of the N bit and causes a branch if N is clear. BPL 1s the complementary operation of BMI.

BPT
000003

Breakpoint trap
00

Type:

Operation:

— (SP) < PS
— (SP) — PC
PC — (14)
PS «— (16)

Condition Codes:

N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

Description:

]

0
|

0
]

Performs a trap sequence with a trap vector address of 14. Used to call debug-

ging aids. The user is cautioned against employing code 000003 in programs run
under these debugging aids. No information is transmitted in the low byte.

Branch

000400
15

0
|

0
1

0
]

1
1

OFFSET
|

7
|

)

MR-2742

Type:

Operation:

PC — PC + (2 X offset)

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Provides a way of transferring program control within a range of — 128 to 4127
words with a 1-word instruction. An unconditional branch.

BVC

Branch if V bit clear

102000

]

OFFSET

]

}

Type:

Operation:

PC — PC + (2 X offset) if V = 0

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Tests the state of the V bit and causes a branch if the V bit is clear. BVC is the
complementary operation to BVS.
~

BVS

Branch if V bit set

0
|

0
)

0
|

1
] :

0
]

102400

OFFSET

Type:

Operation:

PC — PC + (2 X offset) if V = 1

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected

]

C: unaffected

Description:

Tests the state of the V bit (overflow) and causes a branch if the V bit is set.
BVS is used to detect arithmetic overflow in the previous operation.

7-24

CCC

Clear all condition code bits

000257

Type:

-l

]

Description:

Sets and clears condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition

code operator (bits 0-3) are modified according to the sense of bit 4, the
set/clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2,
or 3, if bit 4 is a 1. Clears corresponding bits if bit 4 = 0.

CLC

Clear C

000241
15

0
]

0
|

0
4

0
|

]

0
Il

1
]

0
1

0
|

0
1

1
]

Type:

Description:

Sets and clears condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the
set/clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2,
or 3, if bit 4 is a 1. Clears corresponding bits if bit 4 = 0.

CLN
Clear N

000250
15

0
|

Type:

Description:

0
]

0
|

0
]

O‘
|

1
|

0
|

1
1

0
|

1
1

0
|

0
1

0
|

set/clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2,
or 3, if bit 4 1s a 1. Clears corresponding bits if bit 4 = 0.

7-25

CLR/CLRB

0050DD

Clear

1050DD
15

0/1

]

Type:

Operation:

— O
(dst)

Condition Codes:

N: cleared

0
|

]

D
l‘

D
|

Z: set

V: cleared
C: cleared

Contents of specified destination are replaced with Os.

Description:

NOTE

As a performance optimization, the last bus cycle of
is a DATO (or DATOB).
a CLR (or CLRB)
Previous LSI-11 processors performed a DATIO
cycle for the last bus cycle as a “don’t care” for
hardware minimization.

CLV

000242

Clear V
00

1
1

]

1
|

]

0
1

]

Type:

Description:

Sets and clears condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition

code operator (bits 0-3) are modified according to the sense of bit 4, the
‘set/clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2,
or 3, if bit 4 is a 1. Clears corresponding bits if bit 4 = 0.
CLZ

000244

Clear Z
15

0
|

0
1

0
]

0
|

1
|

0
i

1
|

0
|

1
|

0
L

0
|
MR-2750

7-26

Type:

Description:

Sets and clears condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the
set /clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2,

or 3, if bit 4 is a 1. Clears corresponding bits if bit 4 = 0.

CMP/CMPB

Compare

02SSDD
12SSDD

0/1

1
|

S
1

D
1

Type:

Operation:

(src) — (dst) [in detail (src) + (dst) + 1]

Condition Codes:

N: set if result << O

Z: set if result = O

V: set if there is arithmetic overflow; i.e., if the operands were of opposite signs
and the sign of the destination is the same as the sign of the result
C: cleared if there is a carry from the most significant bit of the result

Compares the source and destination operands and sets the condition codes,

Description:

which may then be used for arithmetic and logical conditional branches. Both
operands are unaffected. The only action is to set the condition codes. The compare is customarily followed by a conditional branch instruction.

COM/COMB

Complement

0051DD
1051DD
15

0/1

0
I

0
|

1
|

0
|

Type:

Operation:

(dst) «— ~ (dst)

1
l

0
1

0
]

7-27

D
|

D
]

D
|

Condition Codes:

N: set if most significant bit of result = 0
Z: set if result = 0
V: cleared
C: set

Description:

Replaces the contents of the destination address by their logical complements
(each bit equal to O set and each bit equal to 1 cleared).

DEC/DECB

Decrement

0053DD
1053DD

0/1

0
]

0
|

1
|

0
1

1
1

Type:

Operation:

(dst) «— (dst) — 1

Condition Codes:

N: set 1f result < 0
Z: set if result = 0

0
|

| D

D
|

V: set if (dst) was 100000

C: not affected

Description:

Subtract 1 from the contents of the destination.

DIV

Divide

071RSS
15
0

1
|

1
L

0
1

0
l

Type:

Operation:

R, RV I — R, RV I/(src)

Condition Codes:

N: set if quotient << 0
Z: set if quotient = 0

7-28

00
S
|

S
|

S
]

S
|

S
1

V: set if source = 0 or if the absolute value of the register is larger than the

absolute value of the instruction in the source. (In this case the instruction is

aborted because the quotient would exceed 15 bits.)
C: set if divide by 0 attempted
Description:

The 32-bit 2’s complement integer in R and R V 11is divided by the source operand. The quotient is left in R; the remainder is of the same sign as the dividend.
R must be even.

EMT

Emulator trap

104000

MR-2755

Type:

Operation:

— (SP) — PS
— (SP) — PC
PC — (30)
PS — (32)

Condition Codes:

N: loaded from trap vector

Z.: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector
Description:

All operation codes from 104000 to 104377 are EMT instructions and may be

used to transmit information to the emulating routine (e.g., function to be performed). The trap vector for EMT is at address 30. The new PC is taken from
the word at address 30; the new processor status (PS) is taken from the word at
address 32.

CAUTION
EMT is used frequently by DIGITAL system software and is therefore not recommended for general
use.

HALT
000000
00

MR-2756

7-29

Type:

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Causes program execution to cease and enters console ODT. (If memory man-

agement is present, program execution ceases only if in kernel mode; a trap to

location 10 occurs if in user mode).

INC/INCB

0052DD

Increment

1052DD

Type:

Operation:

(dst) « (dst) + 1

Condition Codes:

N: set if result < 0

Description:

Adds 1 to the contents of the destination.

D
1

0
i

0
1

{

0/1

Z: set if result = 0O
V: set if dst was 077777
C: not affected

10T

000004

[/0 trap
00

15
]

]

Type:

Operation:

— (SP) — PS
— (SP) — PC

]

PC — (20)
PS — (22)

7-30

Condition Codes:

N: loaded from trap vector

Description:

Performs a trap sequence with a trap vector address of 20. Used to call the I/O

Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector

executive routine IOX in the paper tape software system and for error reporting
in the disk operating system. No information is transmitted in the low byte.

JMP

0001DD

Jump

15
|

]

Type:

Operation:

PC — (dst)

Condition Codes:

N: unaffected
Z:: unaffected
V: unaffected
C: unaffected

Description:

D
|

]

JMP provides more flexible program branching than provided with the branch
instruction. JMP is not limited to +177¢ and —200g words as are branch instructions. JMP does generate a second word, however, which makes it slower
than branch instructions. Control may be transferred to any location in memory
(no range limitation) and can be accomplished with the full flexibility of the addressing modes (with the exception of register mode 0). Execution of a jump
with mode 0 will cause an illegal instruction condition and a trap to location 4.
(Program control cannot be transferred to a register.) Register-deferred mode is
legal and will cause program control to be transferred to the address held in the
specified register.

NOTE

Instructions are word data and therefore must be
fetched from an even-numbered address.

7-31

JSR
004RDD

Jump to subroutine

D
MR-2760

Type:

Operation:

(tmp) « (dst) (tmp is an internal processor register) — (SP) «— reg
(push reg contents onto processor stack)

reg «— PC (PC holds location following JSR; this address now put in reg)
PC — (tmp) (PC now points to subroutine address)
Condition Codes:

N: unaffected
~ Z: unaffected
V: unaffected
C: unaffected

Description:

In execution of the JSR, the old contents of the specified register (the linkage
‘pointer) are automatically pushed onto the processor stack and new linkage information placed in the register. Thus, subroutines nested within subroutines to
any depth may all be called with the same linkage register. There is no need either to plan the maximum depth at which any particular subroutine will be
called or to include instructions in each routine to save and restore the linkage
pointer. Further, since all linkages are saved in a reentrant manner on the processor stack, execution of a subroutine may be interrupted, and the same subroutine
reentered and executed by an interrupt service routine. Execution of the initial
subroutine can then be resumed when other requests are satisfied. This process
(called nesting) can proceed to any level.

JSR PC, dst is a special case of the subroutine call suitable for subroutine calls
that transmit parameters. JSR PC saves the use of an extra register.
In both JSR and JMP the address is used to load the program counter, R7. Thus,
for example, a JSR is destination mode 1 for general register R1 (where (R1) =
100) will access a subroutine at location 100. This is effectively one level less of
deferral than operate instructions such as ADD.

A JSR with mode O will result in an illegal instruction and a trap through the
trap vector address 4.

7-32

MARK
0064NN
00

05
N

MR-2761

Type:

Operation:

SP — PC + 2 X NN
PC «— R5
R5 «— (SP) +

nn = number of parameters

N: unaffected

Condition Codes:

Z:: unaffected
V: unaffected
C: unaffected

Used as part of the standard subroutine return convention. MARK facilitates the

Description:

stack clean-up procedures involved in subroutine exit. Assembler format is:
MARK N

MFPD/MFPI

0065SS
1065SS

Move from previous data space
Move from previous instruction space
06

]

0/1

]

S
|

S
]

Type:

Operation:

(tmp) — (src)

Condition Codes:

N: set if the source << 0

Description:

Pushes a word onto the current stack from an address in the previous space. The

— (SP) — (temp)

Z: set if the source = 0
V: cleared
C: unaffected

source address is computed using the current registers and memory map. Since
data space does not exist in the KDF11, MFPD executes in the same way as an
MPFPI does.

7-33

MFEPS
1067DD

Type:

Operation:

(dst) — PS
dst lower & bits

Condition Codes:

N:set if PS bit 7 =

[U—y

MR-2763

Z:setif PS <0:7> =0

V: cleared
C: unaffected
Description:

The 8-bit contents of the PS are moved to the effective destination. If destination
mode is 0, PS bit 7 is sign-extended through the upper byte of the register. The
destination operand is treated as a byte address.
The KDF11-BA implements the PS address 17777776, which can be used as another method of accessing the PS. This method can be used on all PDP-11s except previous LSI-11 processors.

MFPT
Move from processor type

000007

MR-2884

Type:

Operation:

RO « 000003

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected

C: unaffected
Description:

A unique number assigned to each PDP-11 processor model is loaded into general register RO. The KDF11-BA processor number is 000003 and can be used to
indicate which processor a program is being executed on. LSI-11 and LSI-11/2
processors treat this op code as a reserved instruction trap.

7-34

MOV,/MOVB

01SSDD

Move

11SSDD
15

0/1

D
|

]

D
|

]

S
|

- Type:

Operation:

(dst) « (src)

Condition Codes:

N: set if (src) << 0
Z: set if (src) = 0O
V: cleared
C: not affected

Moves the source operand to the destination location. The previous contents of

Description:

the destination are lost. The source operand is not affected.

Byte: Same as MOV. The MOVB to a register (mode 0), which is unique among
byte instructions, extends the most significant bit of the low-order byte (sign extension) into the high byte of the selected register. Otherwise, MOVB operates
on bytes exactly as MOV operates on words.
NOTE

As a performance optimization, the last bus cycle of
a MOV (or MOVB) is a DATO (or DATOB).
Previous LSI-11 processors performed a DATIO
cycle for MOVB as a “don’t care” for hardware
minimization.

MTPD/MTPI

1066SS
0066SS

Move to previous data space
Move to previous instruction space
15
0/1

Type:

Operation:

Condition Codes:

(temp) — (SP) +
(dst) — (temp)

N: set if the source << 0
Z: set if the source = 0
V: cleared
C: unaffected

7-35

00
D

Description:

This instruction pops a word off the current stack determined by PS bits 15 and
14 and stores that word into an address in the previous space (PS bits 13 and 12).
The destination address is computed using the current registers and memory
map.

Since data space does not exist in the KDF11, MTPD executes in the same way
as MTPI does.

NOTE
As a performance optimization, the last bus cycle of
a MTPD and MTPI is a DATO. This instruction
was not implemented on previous LSI-11 processors.

MTPS
1064SS
15
1

0
l

0
L

1
1

0
L

1
|

0
|

]

00
S
|

S
|

Type:

Operation:

PS «— (SRC)

Condition Codes:

N: set according to effective src operand bits 03

S
1

S
|

Z: same
V: same

C: same
Description:

The eight bits of the effective operand replace the current low-byte contents of
the PS, if in kernel mode. Only PS bits 0 through 3 are affected if in user mode.
The source operand address is treated as a byte address. Note that PS bit 4 (T
bit) cannot be set with this instruction in either kernel or user mode. The src
operand remains unchanged.

The KDF11-BA implements the PS address 17777776, which can be used as another method of accessing the PS. This method can be used on all PDP-11s except previous LSI-11 processors.

MUL
Multiply

070RSS

00
S

MR-2767

7-36

Type:

Operation:

R, RV I~ R X (src)

Condition Codes:

N: set if product << O
Z: set if product = 0
V: cleared

C: set if the result is less than — 215 or greater than or equal to 21> — 1.
The contents of the destination register and source taken as 2’s complement integers are multiplied and stored in the destination register and the succeeding

Description:

register, if R is even. If R is odd, only the low-order product is stored. Assembler
syntax is: MUL S, R. (INote that the actual destination is R, R V 1, which reduces to just R when R is odd.)

NEG/NEGB

0054DD

Negate

1054DD
15

D
]

]

D
i

]

0
|

0/1

Type:

Operation:

(dst) — (dst)

Condition Codes:

N: set if result << 0
Z: set if result = 0
V: set if result = 100000
C: cleared if result = 0O

Description:

Replaces the contents of the destination address by its 2’s complement. Note
‘

that 100000 is replaced by itself.

RESET
000005
00

Type:

Operation:

PC(SP)

PS(SP)

7-37

0
|

)

]

Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

Causes bus signal BINIT L to be asserted for 10 us and then unasserted for 90
us. Used to initialize 1/O devices attached to the bus. In addition, memory management status registers SRO and SR3 are cleared.

ROL/ROLB
0061DD

Rotate left

1061DD

0/1

MR-2770

Type:

Operation:

(dst) «— (dst)
rotate left one place

Condition Codes:

N: set if the high-order bit of the result word is set (result > 0)
7 set if all bits of the result word = 0
V:loaded with the exclusive OR of the N bit and C bit (as set by the completion
of the rotate operation)
C: loaded with the high-crder bit of the destination

Description:

Rotates all bits of the destination left one place. The high-order bit is loaded into

the C bit of the status word and the previous contents of the C bit are loaded into
the low-order bit of the destination.

ROR/RORB
Rotate right

0060DD
1060DD

MR-2771

Type:

Operation:

SO
(dst) — (dst)
rotate right one place

7-38

Condition Codes:

N: set if high-order bit of the result is set
Z: set if all bits of result are O

V: loaded with the exclusive OR of the N bit and the C bit as set by ROR
C: loaded with the low-order bit of the destination

Description:

Rotates all bits of the destination right one place. The low-order bit is loaded into
the C bit and the previous contents of the C bit are loaded into the high-order bit
of the dcstination.

RTI
000002
15

Type:

0
|

]

PC — (SP) +

Operation:

PS «— (SP) +

Condition Codes:

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Used to exit from an interrupt or trap service routine. The PC and PS are restored (popped from the processor stack). If the RTI sets the T bit in the PS, a trace

trap will occur prior to executing the next instruction.

RTS

00020R

Return from subroutine
15

Type:

Operation:

PC — (reg)

Condition Code;%s:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

]

(reg) — SP +

7-39

]

R
|

Description:

Loads the contents of the register into the PC and pops the top element of the
processor stack into the specified register. Return from a nonreentrant subroutine is typically made through the same register that was used in its call.
Thus, a subroutine called with a JSR PC, dst exits with an RTS PC, and a subroutine called with a JSR RS, dst may pick up parameters with addressing
modes (R5)+, X(R5), or @X (RS5) and finally exit, with an RTS RS5.

RTT

000006

MR-2774

Type:

Operation:

PC — (SP)
+
+
PS — (SP)

Condition Codes:

N: loaded from processor stack
7 loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Description:

Used to exit from a trace trap (T bit) service routine and executes in the same
way as the RTT instruction does, with one exception. If the RTT sets the T bit in
the PS, the next instruction will be executed and then the trace trap will be processed. However, if an RTI sets the T bit in the PS, a trace trap will occur before
the next instruction is executed.

SBC/SBCB
0056DD

Subtract carry

1056DD

MR-2775

Type:

Operation:

(dst) < (dst) — C

7-40

Condition Codes:

N: set if result < 0
Z: set if result = O
V: set if (dst) = 100000 and C = 1
C: cleared if (dst) = 0 and C =

Description:

Subtract the contents of the C bit from the destination. This permits the carry
from the subtraction of the low-order words/bytes to be subtracted from the
high-order part of the result in order to perform double-precision subtraction.

SCC

Set all condition code bits

000277

0
]

0
1

0
)

0
]

0
|

1
|

0
|

1
|

1
1

1
|

Type:

Description:

Sets and clears condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the
set /clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2
or 3, 1f bit 4 1s a 1. Clears correspondmg bits if bit 4 = 0.

SEC

Set C

000261
15

0
l

]

0
1

0
|

0
]

0
|

0
1

1
I

0
|

1
|

0
|

0
L

0
l

1
]

Type:

CcC

Description:

Sets and clears condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the
set/clear bit of the operator; i.e., the program sets the bit specified by bit O, 1, 2,
or 3, if bit 4 is a 1. Clears corresponding bits if bit 4 = 0.

SEN

Set N

000270
00

MR-2778

7-41

Type:

Description:

Sets and clears condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the
set /clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2,
or 3, if bit 4 is a 1. Clears corresponding bits if bit 4 = 0.

SEV

Set V

000262

0
]

Type:

0
L

0
A

0
!

0
L

0
|

1
)

0
|

1
|

1
1

0
|

0
]

1
i

0
J

Description: |

Sets and clears condition code bits. Selectable combinations of these bits may be

cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the
set/clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2,
or 3, if bit 4 is a 1. Clears corresponding bits if bit 4 = 0.

SEZ

Set Z

000264

0
|

0
1

0
d

0
]

0
1

1
|

0
I

1
|

0
]

1
L

0
]

0
|

Type:

Description:

Sets and clears condition code bits. Selectable combinations of these bits may be
cleared or set together. Condition code bits corresponding to bits in the condition
code operator (bits 0-3) are modified according to the sense of bit 4, the
set/clear bit of the operator; i.e., the program sets the bit specified by bit 0, 1, 2,
or 3,if 4 is a 1. Clears corresponding bits if bit 4 = 0.

7-42

SOB

Subtract one and branch if not equal to O

077R00 + offset

OFFSET

Type:

Operation:

R «— R — 1: if this result does not = 0 then PC — PC — (2 X offset)

- Condition Codes:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Description:

The register is decremented. If it is not equal to O, twice the offset is subtracted
from the PC (now pointing to the following word). The offset is interpreted as a
6-bit positive number. This instruction provides a fast efficient method of loop
control. Assembler syntax is: SOB R, A where A is the address to which transfer
is to be made if the decremented R is not equal to 0. Note that the SOB instruction cannot be used to transfer control in the forward direction.

SUB

Subtract

16SSDD
15

1
1

S
1

S
L

Type:

Operation:

(dst) — (dst) — (sr¢)

Condition Codes:

N: set if result < 0

S
L

S
|

D
i

D
|

D
1

D
]

Z: set if result = 0

V: set if there is arithmetic overflow as a result of the operation, i.e., if the operands were of opposite signs and the sign of the source is the same as the sign
of the result

C: cleared if there is a carry from the most significant bit of the result

Description:

Subtracts the source operand from the destination operand and leaves the result
at the destination address. The original contents of the destination are lost. The
contents of the source are not affected. For double-precision arithmetic, the C
bit indicates a borrow when set.

7-43

SWAB
0003DD

Swap byte

0
1

0
|

0
1

0
)

Type:

Operation:

byte 1/byte O

0
L

D
1

D
]

D
|

D
]

byte 0/byte 1
Condition Codes:

N: set if high-order bit of low-order byte (bit 7) of result is set
Z: set if low-order byte of result = 0
V: cleared

C: cleared

Description:

Exchanges the high-order byte and low-order byte of the destination, which must
be a word address.

SXT
0067DD

Sign extend

0
|

1
MR-2784

Type:

Operation:

(dst) — O if N is clear
(dst) — — 1 if N bit 1s set

Condition Codes:

N: unaffected
Z: set if N bit clear
V: cleared
C: unaffected

Description:

If the condition code bit N is set, a — 1 is placed in the destination operand; if N
bit is clear, a 0 is placed in the destination operand. This instruction is particularly useful in multiple-precision arithmetic because it permits the sign to be extended through multiple words.

7-44

NOTE
As a performance optimization, the last bus cycle of
a SXT is a DATO. Previous LSI-11 processors performed a DATIO cycle for the last bus cycle as a
“don’t care” for hardware minimization.

TRAP
104400104777
15

0
|

0
L

1
A

0
1

Type:

Operation:

— (SP) — PS

0
|

1
]

]

— (SP) — PC
PC — (34)
PS — (36)

Condition Codes:

N: loaded from trap vector
7 loaded from trap vector
V:loaded from trap vector
C: loaded from trap vector

Description:

Operation codes from 104400 to 104777 are TRAP instructions. TRAPs and
EMTs are identical in operation, except that the trap vector for TRAP is at address 34.

NOTE
Since DIGITAL software makes frequent use of
EMT, the TRAP instruction is recommended for
general use.

TST/TSTB
Test

0057DD
1057DD
15

0/1

0
|

0
]

0
!

1
1

Type:

Operation:

(dst) — (dst)

0
1

1
L

1
|

1
4

7-45

D
1

D
L

D
l

D
|

N: set if result < 0
Z: set if result = 0
V: cleared
C: cleared

Condition Codes:

Sets the condition codes N and Z according to the contents of the destination

Description:

address.

WAIT
000001
15
0

00
0

0
J

Type:

0
|

0
]

0
|

]

0
J

0
|

1
|

Operation:

Condition Codes:

Description:

N: unaffected
Z: unaffected
V: unaffected
C: unaffected

Provides a way for the processor to relinquish use of the bus while it waits for an
external interrupt. Having been given a WAIT command, the processor will not
compete for the instructions or operands from memory. This permits higher
transfer rates between device and memory since no processor-induced latencies
will be encountered by bus requests from the device. In WAIT, as in all instructions, the PC points to the next instruction following the WAIT operation. Thus,
when an interrupt causes the PC and PS to be pushed onto the stack, the address
of the next instruction following the WAIT is saved. The exit from the interrupt
routine (i.e., execution of an RTT instruction) will cause resumption of the interrupted process at the instruction following the WAIT.

XOR
074RDD
09

MR-2788

Type:

Operation:

(dst) — R V (dst)

7-46

Condition Codes:

N: set if the result << O

Description:

The exclusive OR of the register and destination operand is stored in the destination address. The contents of the register are unaffected. Assembler format is:

Z: set if result = 0
V: cleared
C: unaffected

XOR R, D.

7-47

CHAPTER 8

MEMORY MANAGEMENT

8.1

INTRODUCTION

The KDF11-BA processor implements a 2 megaword physical address space. The mapping or translation of 16-bit virtual addresses to 18- or 22-bit physical addresses is implemented in one 40-pin
MOS/LSI integrated circuit. This chip is designated the memory management unit (MMU). The
memory management functionality is software-compatible with other PDP-11 processors (e.g., PDP11/34, PDP-11/60 and PDP-11/70). Eight programmable relocation registers are used to accomplish
the mapping function. These registers are added to the 16-bit virtual address to form a 18- or 22-bit
physical address. The actual physical address transformation occurs transparently to an executing program. The MMU chip also contains some of the floating-point registers in addition to the relocation
registers.

Programming

8.1.1

The memory management hardware has been designed for a multiuser operating system environment.
The processor can operate in two modes (kernel and user) to provide memory relocation and protection
in a multiuser environment. When in kernel mode, software has complete control and can execute all
instructions. Monitors and supervisory programs are executed in this mode.

In a multiuser environment several user programs reside in memory at any given time. The kernel soft-

ware normally does the following.

Controls execution of the various user programs.

Allocates memory and peripheral device resources.

Safeguards the integrity of the system as a whole by careful control of each user program.

When in user mode, software is executed in a restricted environment and is prevented from executing
certain instructions that could be destructive to the entire software system. This restricted environment
prevents the following.

1.
2.
3.

Modification of the kernel program.
Halting the computer.
Initializing the system.

Using memory space assigned to the kernel or to other users.

In a multiuser system the memory management unit assigns pages (relocatable memory segments) to a
user’s program and prevents the user from making any unauthorized access to pages outside his /her
assigned area. Thus, a user can effectively be prevented from accidental or willful destruction of any
other user’s program or of the system executive program.

Hardware-implemented features enable the operating system to dynamically allocate memory upon de-

mand while a program is being run.

8-1

8.1.2

Basic Addressing

The PDP-11 family word length is 16 bits; however, the extended LSI-11 bus and the KDF11-BA addressing logic are 22 bits wide. While a 16-bit word can generate up to 32K words (64K bytes) of virtual address references, the CPU and extended LSI-11 bus can reference up to 2 megawords (4 megabytes) of physical 22-bit addresses. The extra six bits of addressing logic provide the basic framework
for expanding memory references.

The uppermost 4K words of address space is reserved for I/O device registers. The 2 megawords of
physical address space that can be referenced with memory management consist of 2,093,056 words of user memory and 4,096 words of I/O device registers.
8.1.3

Active Page Registers

The memory management unit uses two sets of eight 32-bit active page registers (APRs) (see Figure 81). An APRis actually a pair of 16-bit registers: a page address register (PAR) and a page descriptor
register (PDR). These registers are always used as a pair and contain all the information needed to
—

describe and relocate the currently active memory pages.

One set of APRs is used in kernel mode, and the other in user mode. The set to be used is determined

by the current CPU mode (CM) contained in the processor status word, bits 15 and 14.

KERNEL (00)

PROCESSOR STATUS WORD
|

]

USER (11)

APR 0

APR 1

APR 2

APR 3

APR 4

APR 5

APR 6

APR 7

APR 7
~

1t _ 7

- -

REGISTERS

PAR

/
/

00 /

PDR

-~ g

PAR

CTIVE

AGE

= ~ ~

\
\

\ 16

~ g

PDR

PAGE DESCRIPTION REGISTER

PAGE ADDRESS REGISTER

MR-3649

Figure 8-1

Active Page Registers

8-2

8.1.4

Capabilities Provided by Memory Management

Memory Size (words)
Address Space

2 megawords (minus 4K words for I/O Page)
Virtual (16 bits)

Physical (18 or 22 bits)

Modes of Operation

Kernel and user

Stack Pointers

2 (one for each mode)

Memory Relocation

Number of Pages
Page Length
Memory Page Protection

8.2

16 (8 for each mode)
32 to 4,096 words
No access
Read-only
Read/write

MEMORY RELOCATION

When the memory management unit is operating, the normal 16-bit direct byte address is no longer
interpreted as a direct physical address (PA) but as a virtual address (VA) containing information to be
used in constructing a new 18- or 22-bit physical address. Information contained in the virtual address is
combined with relocation and description information contained in the active page register to yield an
18- or 22-bit physical address.

Because addresses are relocated automatically, the computer may be considered to be operating in virtual address space. This means that regardless of where a program is loaded into physical memory, it
will not have to be relinked; it always appears to be at the same virtual location in memory.
The virtual address space is divided into eight 4K-word pages. Each page is relocated separately. Thisis
a useful feature in multiprogrammed timesharing systems. It permits a new large program to be loaded
into discontinuous blocks of physical memory.

A basic function of the memory management unit is to perform memory relocation and provide extended memory addressing capability for systems with more than 32K words of physical memory. Two sets
of page address registers are used to relocate virtual addresses to physical addresses in memory. These
sets are used as hardware relocation registers that permit several users’ programs, each starting at virtual address 0, to reside simultaneously in physical memory.
8.2.1

Program Relocation

The page address registers are used to determine the starting physical address of each relocated program in physical memory. Figure 8-2 shows a simplified example of the relocation concept. Program A
starting address 0 is relocated by a constant to provide physical address 6400g.

If the next program virtual address is 2, the relocation constant will then cause physical address 6402g
(the second item of program A) to be accessed. When program B 1s running, the relocation constant is
changed to 100000g. Then, program B virtual addresses starting at 0 are relocated to access physical
addresses starting at 100000g. Using the active page address registers to provide relocation eliminates
the need to relink a program each time it is loaded into a different physical memory location. The program always appears to start at the same address.

RELOCATION

VIRTUAL

CONSTANT

ADDRESS

A = 6400

(VA) =0

B = 100000

PHYSICAL MEMORY

M
PROGRAM B

100000g

PHYSICAL ADDRESS

PROGRAM A
006400g

000000
MR-3650

Figure 8-2

Memory Relocation, Simplified Block Diagram

A program is relocated in pages consisting of from 1 to 128 blocks. Each block is 32 words in length.
Thus, the maximum length of a page 1s 4096 (128 X 32) words. Using all the eight available active
page registers in a set, a maximum program length of 32,768 words can be accommodated. Each of the

eight pages can be relocated anywhere in physical memory, as long as each relocated page begins on a
boundary that 1s a multiple of 32 words. However, for pages smaller than 4K words, only the memory
actually allocated to the page may be accessed. Refer to the relocation example shown in Figure 8-3.

VIRTUAL ADDRESS

PAGE|

RELOCATION

RANGES

CONSTANT

SPACE

160000—-177776

071500

13720000—-13737776

140000—-157776

000000

07150000-07167776

120000—-137776

001000

00400000—-00417776

100000—-117776

000200

00250000—-00267776

060000—-077776

000600

00100000-00117776

040000057776

002500

00060000—-00077776

PHYSICAL MEMORY

020000—-037776

137200

00020000-00037776

000000017776

004000

00000000-0001 7776‘
MR-5929

Figure 8-3

Relocation of a 32K-Word Program into 2 Megawords of Physical Memory

Figure 8-3 illustrates several points about memory relocation.
1.

Although the program appears to the processor to be in contiguous address space, the 32Kword physical address space is actually scattered through several separate areas of physical
memory. As long as the total available physical memory space is adequate, a program can be

loaded.

Pages may be relocated to physical addresses higher or lower in respect to their virtual address ranges. In this example, page 1 is relocated to a higher range of physical addresses,
|

page 4 is relocated to a lower range.

All the pages shown in the example start on 32-word boundaries.

Each page is relocated independently. There is no reason why two or more pages could not be
relocated to the same physical memory space. Using more than one page address register in
the set to access the same space would be one way of providing different memory access
rights to the same data, depending on which part of the program was referencing that data.
Memory Units

8.2.2

Block

32 words

Page

1 to 128 blocks (32 to 4,096 words)

Number of pages

8 per mode

Size of relocatable memory

32,768 words, maximum (8 X 4,096)

8.3

MEMORY MANAGEMENT REGISTERS

The memory management unit uses two sets of page address registers (PARs) and page descriptor registers (PDRs) referred to as PAR/PDR pairs. One set of PAR/PDR register pairs is used in kernel
mode and the other set of register pairs in user mode. The choice of which set is to be used is determined by the current processor mode contained in processor status word (PS) bits <<15:12>. The
MMU also contains four status registers (SRO through SR3) that implement various memory management functions. The memory management register functions are described in the following paragraphs.
8.3.1

Page Address Register (PAR)

The page address register contains the 16-bit page address field (PAF), which specifies the starting
address of the page as a block number in physical memory. The page address register is shown in Figure
8-4.

)

1
MR-5830

Figure 8-4

Page Address Register

The page address register may be thought of as a relocation constant, or as a base register containing a
base address. Either interpretation indicates the basic function of the page address register (PAR) in
the relocation scheme.

8.3.2

Page Descriptor Register (PDR)

The page descriptor register is a 16-bit register that contains information relative to page expansion,
page length, and access control. The page descriptor register bit assignments are shown in Figure 8-5.

8-5

7%
NOTE:

lF’LFJ

///AW %///%ED

A?F

ALL UNIMPLEMENTED BITS READ AS ZEROS.

Figure 8-5

Page Descriptor Register

8.3.2.1 Access Control Field (ACF) — This 2-bit field (bits 2 and 1) of the PDR describes the access
rights to a particular page. The access codes or keys specify the manner in which a page may be accessed, and whether or not a given access should result in an abort of the current operation. A memory
reference that causes an abort is not completed and is terminated immediately.

Aborts are caused by attempts to access nonresident pages, by page-length errors, or by access violations, such as attempts to write into a read-only page. Traps are used as an aid in gathering memory
management information.

In the context of access control, the term “write” is used to indicate the action of any instruction that
modifies the contents of any addressable word. A write is synonymous with what is usually called a
“store”” or “modify” in many computer systems. Table 8-1 lists the ACF keys and their functions. The
ACEF is written into the PDR under program control.
Table 8-1

Access Control Field Keys

AFC

Key

Description

Function

Nonresident

Abort any attempt to access this

Resident

Abort any attempt to write

(Unused)

Abort all accesses.

nonresident page.

read-only

into this page.

Resident

Read or write allowed;

read /write

No trap or abort occurs.

NOTE
A memory management abort causes the program to
trap to location 250g.

8.3.2.2 Expansion Direction (ED) — Bit 3 of the page description register (PDR) specifies in which
direction the page expands. If ED = 0, the page expands upward from block number O to include
blocks with higher addresses; if ED = 1, the page expands downward from block number 127 to include blocks with lower addresses. Upward expansion is usually used for program space while downward expansion is used for stack space. An example of page expansion upward is shown in Figure 8-6.
When the expansion direction is downward (ED = 1), the page length is increased by the addition of
blocks with lower relative addresses. Downward expansion is specified for stack pages so that more
stack space can be added. An example of page expansion downward is shown in Figure 8-7.

8-6

PDR

PAR

001

000
.

111

000

O 110
001
0000
0101

)

PLF = 51g = 4119= NUMBER OF BLOCKS
ED =0 = UPWARD EXPANSION
ACF = 6 = READ/WRITE

To specify a block length of 42 for an upNOTE:
ward expandable page, write highest authorized
block number directly into high byte of PDR. Bit
15 is not used because the highest allowable block
number is 177g.

‘

////////////// )
/ BLOCK 177g

ANY BLOCK NUMBER

L BLOCK 176
EXPANSION BY

‘

WILL CAUSE A PAGE

l =/
L
§BLOCK528/
)
BLOCK 51g

AUTHORI=ZE4219PAGEBLOCKS
' LENGTH
OROTHRU51g =

52g BLOCKS

0 24176

024100

_/_j
"’/-~fl/’~017276
2
BLOCK

017200
017176

1
BLOCK

0
BLOCK

017100
017176

017000

<—

S
OF PAGE
BASE ADDRES
MR-3655

Figure 8-6

Example of an Upward-Expandable Page

8.3.2.3 Write Access Bit (W) (Bit 6) — This bit indicates whether or not this page has been modified
(i.e., written into) since either the PAR or PDR was loaded. (W = 11s affirmative). The W bit is useful
in applications that involve disk swapping and memory overlays. It 1s used to determine which pages
have been modified (and hence must be saved in their new form) and which pages have not been modified and can simply be overlaid. Note that the W bit is “reset” to “0” whenever either PAR or PDR is
modified (written into).

8.3.2.4 Page Length Field (PLF) — The 7-bit PLF located in PDR<14:08> specifies the authorized
length of the page in 32-word blocks. The PLF holds block numbers from O to 177g, thus allowing any
page length from 1 to 128;¢ blocks. The PLF is written into the PDR under program control.

e—ACTIVE PAGE REGISTER CONTENTS—=
PDR

PAR

000 001 111 000 ] l01010110 0000 1110
——

——

PAF = 0170"———"J

ED= 1= DOWNWARD EXPANSION

TO SPECIFY PAGE LENGTH FOR

A DOWNWARD EXPANDABLE PAGE

WRITE COMPLEMENT OF BLOCKS REQUIRED INTO HIGH BYTE OF PDR.
IN THIS EXAMPLE, A 42-BLOCK PAGE IS REQUIRED
PLF IS DERIVED AS FOLLOWS;
4244 =52g: TWO'S COMPLEMENT = 126g

BLOCK 177g

036776

036700

BLOCK 176g

AUTHORIZED PAGE

LENGTH = 4219 BLOCKS

BLOCK 175g

036676

)

FIRST BLOCK OF
DOWNWARD
EXPANDABLE PAGE

036600
036576

036500

F,W_//—?fi—-’fl
BLOCK 126g

031676

031600

12
/BLOCK/
ADDRESS RANGE

OF POTENTIAL PAGE
EXPANSION BY

////////

A BLOCK NUMBER
REFERENCE LESS
THAN 126g

LESS THAN 126g)
(VA<12:06>

CHANGING THE PLF

U555

BLOC //////

/C47,owomx
¢,0077
/BL0014;¢
i //0,13999 /

WILL CAUSE A PAGE

LENGTH ABORT.

<—— BASE ADDRESS OF PAGE
MR-6173

Figure 8-7

Example of a Downward-Expandable Page

When the page expands upward, the PFL must be set to 1 less than the number of blocks authorized for
that page. For the example shown in Figure 8-6, since 52g (42;¢) blocks are authorized, the PLF is set
to 51g (411¢g). The hardware compares the virtual address block number (VA<12:06>) with the PLF
to determine if the virtual address is within the authorized page length.
When VA<<12:06> is less than or equal to the PLF, the virtual address is within the authorized page
length. If VA<<12:06> is greater than the PLF, a page-length fault (address too high) is detected by
the hardware and an MMU abort occurs.
When the page is to be downward-expandable, the PLF must be set to 200g (1281¢) minus the length of
the page (in blocks). For the example shown in Figure 8-7, since 52g (421¢) blocks are authorized, the
PLF is set to 1263 (861p).

8-8

When VA< 12:06> is greater than or equal to the PLF, the virtual address is within the authorized
- page length. If VA<<12:06> is less than the PLF, a page-length fault (address too low) is detected by
the hardware and an MMU abort occurs.

The downward-expandable example in Figure 8-7 uses the same PAF as the upward-expandable example in Figure 8-6. This is so to emphasize that the base address points to the lowest possible address
of the 128 block page, whether the page is upward- or downward-expandable. As shown in Figure 8-7,
the base address may not even be within the authorized page length of a downward-expandable page.
PAR/PDR Address Assignments

8.3.3

Addresses are assigned to the kernel and user active page registers as PAR/PDR register pairs. The

PAR/PDR register addresses are listed in Table 8-2.
Table 8-2

PAR/PDR Address Assignments

Kernel Active Page Registers

8.3.4

User Active Page Registers

No.

PAR

PDR

No.

PAR

PDR

0
1
2
3
4
5
6
7

17772340
17772342
17772344
17772346
17772350
17772352
17772354
17772356

17772300
17772302
17772304
17772306
17772310
17772312
17772314
17772316

0
1
2
3
4
5
6
7

17777640
17777642
17777644
17777646
17777650
17777652
17777654
17777656

17777600
17777602
17777604
17777606
17777610
17777612
17777614
17777616

Status Register 0 (SR0) — Address: 17777572g

SRO contains abort error flags, memory management enable, and other information essential for an
operating system to recover from an abort or to service a memory management trap. The format of SRO
is shown in Figure 8-8.

LENGTH ERROR
ABORT - READ ONLY
ACCESS VIOLATION
MODE

PAGE NUMBER
ENABLE MANAGEMENT
MR-3658

Figure 8-8

Format of Status Register 0 (SRO)

8-9

The enable management bit (SRO bit 0) is set and cleared under program control to enable and disable
memory management. The abort flag bits (SRO<<15:13>) can also be set and cleared under program
control, but they cause an MMU abort only when set automatically by an MMU abort condition. After
an MMU abort has occurred, the program must clear SRO<15:13> in order to resume monitoring
memory management status.

The abort flags are in priority order in that flags to the right are less significant and should be ignored
when a more significant flag is asserted. For example, a nonresident abort service routine would ignore
the page-length bit (14) and read-only access violation bit (13). A page-length abort service routine
would ignore the read-only access violation bit.

The mode bits (SR0O<06:05>) and the page number bits (SR0<<03:01>) are loaded automatically
when an MMU abort occurs. The status of these bits is frozen whenever one of the abort flags
(SRO<15:13>) is set. The SRO is cleared by the RESET instruction, power-up or restart.
8.3.4.1 Abort Nonresident — Bit <<15> is the abort nonresident bit. It is set by attempting to access a
page with an access control field (ACF) key equal to O or 4, or by enabling relocation with an illegal
mode in the PSW.

8.3.4.2 Abort Page Length — Bit <<14> is the abort page-length bit. It is set by attempting to access a
location in a page with a block number (virtual address bits <<12:06>) that is outside the area authorized by the page-length field (PLF) of the PDR for that page.

8.3.4.3 Abort Read-Only — Bit <<13> is the abort read-only bit. It is set by attempting to write-in a
read-only page. Read-only pages have an access control field (ACF) key of 2g.
NOTE

There are no restrictions against abort bits being set
simultaneously by the same access attempt.

8.3.4.4 Mode of Operation — Bits <<06:05> indicate the CPU mode (user or kernel) associated with
the page causing the abort. (Kernel = 00, user = 11.)
8.3.4.5 Page Number — Bits <03:01> refer to the virtual page number that caused a memory management fault. Pages, like blocks, are numbered from O upward. The page number bits are used by the
error recovery routine to identify the page being accessed if an abort occurs.
8.3.4.6 Enable Relocation and Protection — Bit <<0> is the enable bit. When it is set to 1, all addresses are relocated and protected by the memory management unit. When this bit is set to 0, the memory
management unit is disabled and addresses are neither relocated nor protected.
8.3.5 Status Register 1 (SR1) — Address: 17777574g
SR1 is a read-only register that always reads as zero.
8.3.6

Status Register 2 (SR2) — Address: 177775763

SR?2 is loaded with a 16-bit virtual address (VA) during each instruction fetch, but is not updated if the
instruction fetch fails. SR2 is read-only; a write attempt will not modify its contents. SR2 1s the virtual
address program counter. The content of SR2 is frozen whenever one of the abort flags
(SRO<15:13>) is set. The format of SR2 1s shown in Figure 8-9.

8-10

16-BIT VIRTUAL ADDRESS

I
MR-3660

Figure 8-9
8.3.7

Format of Status Register 2 (SR2)

Status Register 3 (SR3) — Address: 17772516g

SR3 bit <<4> enables or disables the memory management 22-bit mapping. If memory management is
not enabled (SRO bit O is clear), bit 4 is ignored and the 16-bit address is not mapped. If memory management is enabled (SRO bit 0 is set) and bit 4 is clear, the computer uses 18-bit mapping. If memory
management is enabled and bit 4 is set, the computer uses 22-bit mapping.
SR3 bit <5> is a read/write bit that has no effect on KDF11-BA operation. On systems that contain
an /0 map (e.g., the PDP-11/24), bit 5 is set to enable I/O map relocation and is cleared to disable
relocation. Status register 3 is cleared by the RESET instruction, power-up or restart. The format of
SR3 is shown in Figure 8-10.

MR-3661

Figure 8-10

8.4

Format of Status Register 3 (SR3)

VIRTUAL AND PHYSICAL ADDRESSES

The memory management unit is located between the central processor unit and the LSI-11 bus address
lines. When the memory management unit is operating, the normal 16-bit direct byte address is no longer interpreted as a direct physical address (PA) but as a virtual address (VA) containing information to
be used in constructing a new 18- or 22-bit physical address. The information contained in the virtual
address (VA) is combined with relocation information to yield an 18- or 22-bit physical address (PA).
Using the memory management unit, memory can be dynamically allocated in pages, each page composed of from 1 to 128 integral blocks of 32 words.

The starting physical address of each page is an integral multiple of 32 words, and each page has a
maximum size of 4096 words. Pages may be located anywhere within the physical address space. The
current mode of the processor (kernel or user) determines which set of 16 PAR/PDR registers is used
to construct the physical address.
8.4.1

Construction of a Physical Address

The basic information needed for the construction of a physical address (PA) comes from the virtual
address (VA), which is illustrated in Figure 8-11, and the appropriate APR set.

8-11

APF
i

DF
|

ACTIVE PAGE FIELD

DISPLACEMENT FIELD
MR-3656

Figure 8-11

Interpretation of a Virtual Address

The virtual address consists of the folloWing.
1.

The active page field (APF) — This 3-bit field determines which of eight active page registers
(APRO-APR7) will be used to form the physical address (PA).
The displacement field (DF) — This 13-bit field contains an address relative to the beginning

of a page. This permits page lengths of up to 4K words (213 = 8K bytes). The DF is divided
into two fields as shown in Figure 8-12.

BN
l

DiB
I

BLOCK NUMBER

DISPLACEMENT IN BLOCKS
MR-3657

Figure 8-12

Displacement Field of Virtual Address

The displacement field (DF) consists of the following.
.

The block number (BN) — This 7-bit field is interpreted as the block number within the current page.

The displacement in block (DIB) — This 6-bit field contains the displacement within the
block referred to by the block number.
The remainder of the information needed to construct the physical address comes from the 12- or 16-bit
page address field (PAF) (contained in the active page register), specifying the starting address of the
memory that APR describes. The PAF is actually a block number in the physical memory; for example,

PAF = 3 indicates a starting address of 96 (3 X 32 = 96) in physical memory. The formation of the
physical address is illustrated in Figure 8-13.
The logical sequence involved in forming a physical address is as follows.
1.

Select a set of active page registers. (Selection depends on the current mode specified by
PS<15:14>))

The active page field of the virtual address is used to select an active page register
(APRO-APRT7).
The page address field of the selected APR contains the starting address of the currently

active page as a block number in physical memory.

T2IngV1IqSA¢H[d-§9078uoONnewloJo®B[BJISAUJ=S—QIP-Y 81a ANIS
LN3IN3DV1dSIa)NI(SMO078

UW 826G

41z dv Y2018ON90 50 g14a 0VOLHIA

gGl T 1 €l ZL 0 90 S0 00

-@®

8-13

The block number from the virtual address is added to the block number from the page address field to yield the number of the block in physical memory that will contain the physical
address being constructed.
The displacement in blocks from the displacement field of the virtual address is joined to the
physical block number to yield a 22-bit physical address.
8.4.2

Determining the Program Physical Address

A 16-bit virtual address can specify up to 32K words, in the range of 000000 to 177776g (word boundaries are even numbers). The three most significant virtual address bits designate the PAR /PDR pair
to be referenced during page address relocation. Table 8-3 lists the virtual address ranges that specify
each of the PAR/PDR sets.

Relating Virtual Address Ranges to PAR/PDR Sets

Virtual Address Range

PAR/PDR Set

000000-17776

~NON DBk WwWiNo—
O

Table 8-3

020000-37776
040000-57776
06000077776

100000117776
120000137776
140000157776

160000177776

NOTE
Any use of page lengths of less than 4K words
causes unaddressable ‘“holes” in the virtual address
space.

8.5 PROTECTION
A timesharing system performs multiprogramming; that is, it allows several programs to reside in memory simultaneously, executing each sequentially. Access to these programs, and the memory space they
occupy, must be strictly defined and controlled. A timesharing system requires several types of memory
protection.
].

User programs must not be allowed to expand beyond their alldcated space unless authorized

to do so by the system.

Users must be prevented from modifying common subroutines and algorithms that are resident for all users.
3.

Users must be prevented from gaining control of or modifying the operating system software.

Users must be prevented from accessing or modifying memory occupied by other users.

Memory management provides the hardware facilities to implement all the types of memory protection
listed above.

8-14

8.5.1

Inaccessible Memory

Each page has a 2-bit access control key associated with it. The key is part of the page descriptor register (PDR). (The access control key functions are described in Table 8-1.) The key is assigned under
operating system control. When the key is set to 0, the page is defined as nonresident. Any attempt by a
user program to access a nonresident page is prevented from doing so by an immediate abort. Using this
feature to provide memory protection, only those pages associated with the current program are set to
legal access keys. The access control keys of all other program pages are set to 0, which prevents illegal
memory references.

8.5.2

Read-Only Memory

The access control key for a page can be set to 2, which allows read (fetch) memory references to the
page but immediately halts any attempt to write into that page. This read-only type of memory protection can be afforded to pages that contain common data, subroutines, or shared algorithms. It also
allows the access rights to a given memory area to be user-dependent. That is, the access right to a
memory area may be varied for different users by altering the access control key.
A page address register in each of the sets (in kernel and user modes) may be set up to reference the
same physical page in memory, and each may be keyed for different access rights. For example, the
user access control key might be 2 (read-only access for user programs), and the kernel access control
key might be 4 (allowing complete read/write access for the operating system).
8.5.3

Multiple Address Space

Two complete PAR/PDR sets are provided: one for kernel mode and one for user mode. This affords
the operating system software another type of memory protection. The mode of operation is specified
by the processor status word’s current mode field, or previous mode field, as determined by the current
instruction. Each mode has its own corresponding stack pointer (R6) for protection as well as software
considerations.

A user mode program is relocated by its own PAR/PDR set, as is a kernel program. This makes it
impossible for a program running in one mode to reference space allocated to another mode accidentally, when the active page registers are set correctly. For example, a user cannot transfer to kernel
space. The kernel mode address space may be reserved for resident system monitor functions, such as
the basic input/output control routines, memory management trap handlers, and timesharing scheduling modules. By dividing the types of timesharing system programs functionally between the kernel
and user modes, a minimum of space control housekeeping is required as the timeshared operating system sequences from one user program to the next. For example, only the user PAR /PDR set needs to
be updated as each new user program is serviced. (The PAR and PDR register formats are shown in
Figures 8-4 and 8-5.)

8.5.3.1 Mode Specification in the Processor Status Word — PS<(15:14> specify the current memory
management mode. These bits are used to select the corresponding PAR/PDR set to be used for the
currently executing program. PS<<13:12> specify the previous memory management mode. These bits
are used by the memory management instructions to communicate between kernel and user address
spaces. When an implicit mode change occurs, the previous mode bits (PS<<13:12>) are loaded by
hardware with the contents of the current mode bits (PS<<15:14>). This change can occur whenever
an interrupt or trap is processed. PS<<15:12> are cleared when power is applied. Clearing these bits
selects kernel mode. PS<<15:12> are encoded as shown below.

8-15

PS<15:14>
or

PS<<13:12>

PAR/PDR Set Enabled

Stack Pointer Selected

Kernel

Kernel (KSP)

Reserved for future DIGITAL

use; specifies supervisor
mode on some PDP-11s; does

Supervisor (SSP);

reserved for future
DIGITAL use.

not cause a halt.

Illegal; does not cause a

Reserved for future

User

USER (USP)

halt.

DIGITAL use.

Each mode selects its own corresponding stack pointer. Thus, all program references to register R6 use
a different register as specified by PS<<15:14>. Stack pointer selection occurs whether the MMU is
enabled or not (SRO bit 0 is a 1). The different stack pointers are initialized by loading the appropriate
mode value in PS<15:14>, and can be examined by console ODT.
8.5.3.2 Processor Status Word Protection — There are various software methods of affecting
PS<15:00>. Since kernel mode is defined to allow software access to all hardware features, free access to the PS is allowed. Since user mode is defined for operating user programs, and thus, protecting
the operating system software, certain PS bits such as the mode and priority level fields are protected.
Table 8-4 shows how all PS bits are affected.
8.5.3.3 User Mode Restrictions — User mode is intended for executing user programs. In user mode
the program is restricted from using those hardware features that could disrupt system integrity. The
following hardware features are protected in user mode.
1.

HALT instruction — Instead of entering console ODT, a HALT instruction causes a trap to
kernel location 10g. The intent is not to allow a user program to halt the operating system.

RESET instruction — Instead of causing a BUS initialize, a RESET instruction is executed
as an NOP instruction. The intent here is to prevent the user program from initializing /0
devices.

Access to PS<<03:00> only — All other PS bits are vital to system operations and cannot be
affected.

8.5.3.4 Interrupt and Trap Processing — All interrupt and trap vectors are forced by hardware to be
used always in kernel mode when the new PC and PS are fetched. The processor’s first step in processing the interrupt or trap is to fetch the new PS value from the interrupt or trap location plus 2. This
determines which mode (and consequently, which stack pointer) to use for pushing the old PC and PS.
The KDF11-BA copies the old PS into a temporary register and then loads the new PS value.
PS<15:14> are loaded from the memory location to select the new current mode. PS<<13:12> (previous mode) are loaded with the old value in PS<<15:14>, to keep a record of what the previous mode
was. This is the only place where the PS previous mode bits copy the current mode bits.

8-16

<IS$8>19:<Sd1>SdwJpoaeJlpj}eso]wJpOoaeplde}jsoT]w1p0oa3l.p1j0e9oA]w1p0oa1lp0je29o4A]p9w2ao1gJpndjNu0eoSy]oupnypw92aoI1glpNnuj0eoSy]oun)p3a[gqdIuSeyAoIuDBnU)ON]p3[aQgIuSeSy2o0u0nB)UONpales|)
uonedo|‘$Z710

Sua<<1A9IpodjNaPd0GonOlOD':uIoIs)apAnN€LNiiudy)>>goIuS]S)jdd‘y1wppLoaa3egdpgl}dYjuesueoeLy]yIooLuuYnn))[)w)pwwPoooaoUeedplIll}jdjessYo]]1w1wPwp0o03oaosl1osdddpt1}0e)j0jdejl99ot4A)]puesjdnirdj[1w1pwwuP00ofooU33a.diJ1I0p}j0dj9e9Y4oA])]13wp3dww22ooaon1SJdpdnNdjjje00xoSST]ySd$SN3[w9pwwYP22ooaoUIlldpINNj}jde00YoSS]]2S1wp903A[oaSIdgqdQp0.NdIj}eL0uIoSeN]yA2DdOuBnU)ON]9w[w9p32E2[ooa1LqIJlQpnRINjjNEeS00DoOSSY]I3IJO0BUON]dp1pdaan9nl9l-ie0e1su1d9|a|m[‘dy)od)emyu1g1pssayjtmoaoqmod
O'pa0draL1mnod "9p0o0IdIW

SUP-1Ld0NIS[}I3OAB8qV3AI01eSJ

1popndoepogeTos] )J01o3e10l90sA9A

8-17

20<A.Cvyl1I:2'E06Nt1I0>S8d

This process allows communication between mode address spaces using the memory management instructions. The remaining PS bits are loaded from the memory location. Thus, interrupt and trap service routines can be executed in either kernel or user mode, depending on the contents of the vector
plus 2 locations.

8.6 MEMORY MANAGEMENT INSTRUCTIONS
Memory management provides communications between two spaces, as determined by the current
memory management mode bits (PS<<15:14>) and previous memory management mode bits
(PS<13:12>) of the processor status word (PS). The following instructions are directly applicable to
memory management.

Mnemonic

Instruction

Op Code

MFPI
MTPI
MFPD
MTPD

Move from previous instruction space
Move to previous instruction space
Move from previous data space
Move to previous data space

0065SS
0066DD
1065SS
1066DD

Refer to Chapter 7 for a more detailed description. These instructions are directly compatible with
larger PDP-11 computers.

8-18

CHAPTER 9

FLOATING-POINT ARITHMETIC

9.1

INTRODUCTION

Forty-six floating-point instructions are available as a microcode option (KEF1 1-AA) for use with the
KDF11-BA processor. The KEF11-AA is completely software-compatible with the FP11-A used on the
PDP-11/34, the FP11-E used on the PDP-11/60, and the FP11-C used on the PDP-11/70. Both singleand double-precision floating-point capability are available with other features, including floating-tointeger and integer-to-floating conversion.

The KEF11-AA consists of two MOS/LSI chips contained in one 40-pin package. Operation of the
KEF11-AA requires the MMU chip, in addition to the base MOS/LSI chips, because all the floatingpoint accumulators and status registers reside in the MMU.
9.2

FLOATING-POINT DATA FORMATS

Mathematically, a floating-point number may be defined as having the form (2 ** K) * f, where K is an
integer and f is a fraction. For a nonvanishing number, K and f are uniquely determined by imposing
the condition 1/2 f << 1. The fractional part (f) of the number is then said to be normalized. For the
number 0, f must be assigned the value 0, and the value of K is indeterminate.
The floating-point data formats are derived from this mathematical representation for floating-point
numbers. Two types of floating-point data are provided. In single-precision, or floating mode, the data is
32 bits long. In double-precision, or double mode, the data is 64 bits long. Sign magnitude notation is
used.

9.2.1

Nonvanishing Floating-Point Numbers

The fractional part (f) is assumed normalized, so that its most significant bit must be 1. This 1 is the
“hidden” bit: it is not stored explicitly in the data word, but the microcode restores it before carrying
out arithmetic operations. The floating and double modes reserve 23 and 55 bits, respectively, for f.
These bits, with the hidden bit, imply effective word lengths of 24 bits and 56 bits.
Eight bits are reserved for storage of the exponent K in excess 128 (200g) notation (i.e., as K + 200g),
giving a biased exponent. Thus, exponents from —128 to +127 could be represented by 0 to 3773, or 0
to 25510. For reasons given below, a biased exponent of 0 (the true exponent of —200g), 1s reserved for
floating-point 0. Therefore, exponents are restricted to the range —127 to + 127 inclusive (—177g to
+177g) or, in excess 200g notation, 1 to 377g.

The remaining bit of the floating-point word is the sign bit. The number is negative if the sign bitisa 1.

9-1

9.2.2

Floating-Point Zero

Because of the hidden bit, the fractional part is not available to distinguish between 0 and nonvanishing
numbers whose fractional part is exactly 1/2. Therefore, the FPP (floating-point processor) reserves a
biased exponent of O for this purpose, and any floating-point number with a biased exponent of O either
traps or is treated as if it were an exact O in arithmetic operations. An exact or *“‘clean” 0 is represented
by a word whose bits are all 0s. A “dirty” 0 is a floating-point number with a biased exponent of 0 and a
nonzero fractional part. An arithmetic operation for which the resulting true exponent exceeds 2773 is
regarded as producing a floating overflow; if the true exponent is less than —177g, the operation is
regarded as producing a floating underflow. A biased exponent of 0 can thus arise from arithmetic
operations as a special case of overflow (true exponent = —200g). (Recall that only eight bits are reserved for the biased exponent.) The fractional part of results obtained from such overflow and underflow 1s correct.

9.2.3

The Undefined Variable

An undefined variable is any bit pattern with a sign bit of 1 and a biased exponent of 0. The term
“undefined variable” is used, for historical reasons, to indicate that these bit patterns are not assigned a
corresponding floating-point arithmetic value. Note that the undefined variable is frequently referred to
as —0 elsewhere in this chapter.
A design objective of the FPP was to assure that the undefined variable would not be stored as the
result of any floating-point operation in a program run with the overflow and underflow interrupts disabled. This is achieved by storing an exact 0 on overflow and underflow, if the corresponding interrupt

is disabled. This feature, together with an ability to detect reference to the undefined variable (imple-

mented by the FIOV bit discussed later), is intended to provide the user with a debugging aid: if —0
occurs becomes present, it did not result from a previous floating-point arithmetic instruction.
9.2.4

Floating-Point Data

Floating-point data is stored in words of memory as illustrated in Figures 9-1 and 9-2.
The FPP provides for conversion of floating-point to integer format and vice-versa. The processor recognizes single-precision integer (I) and double-precision integer long (L) numbers, which are stored in
standard 2’s complement form. (See Figure 9-3.)

F FORMAT, FLOATING POINT SINGLE PRECISION
15

FRACTION <15:0>
]

15
MEMORY +0

]

EXP
l

]

FRACT <22:16>
l

]

|
MR-3604

Figure 9-1

Single-Precision Format

9-2

D FORMAT, FLOATING POINT DOUBLE PRECISION

FRACTION <15:0>

]

FRACTION <31:16>
I

]

15
+2

FRACTION <47:32>

FRACT <54:48>

EXP

MEMORY +0

]

S=SIGN OF FRACTION

EXP = EXPONENT IN EXCESS 200 NOTATION, RESTRICTED TO 1 TO 377 OCTAL
FOR NON-VANISHING NUMBERS.

+ ONE HIDDEN
FRACTION = 23 BITS IN F FORMAT, 55 BITS IN D FORMAT

BIT (NORMALIZATION). THE BINARY RADIX POINT IS TO THE LEFT.
MR-3605

Figure 9-2

Double-Precision Format

| FORMAT, INTEGER SINGLE PRECISION

15
S

NUMBER <15:0>
1

)

L FORMAT, DOUBLE PRECISION INTEGER LONG

MEMORY +0

NUMBER <30:16>

S
1

]

15
+2

NUMBER <15:0>

]

{

]

WHERE S = SIGN OF NUMBER

NUMBER = 15 BITS IN | FORMAT, 31 BITS IN L FORMAT.
MR-3606

Figure 9-3

2’s Complement Format

9-3

9.3 FLOATING-POINT STATUS REGISTER (FPS)
This register provides mode and interrupt control for the floating-point unit and conditions resulting
from the execution of the previous instruction. (See Figure 9-4.) In this discussion a set bit = 1 and a

reset bit = 0. Three bits of the FPS register control the modes of operation.
1.

Single/Double — Floating-point numbers can be either single- or double-precision.

Long/Short — Integer numbers can be 16 bits or 32 bits.

Chop/Round — The result of a floating-point operation can be either “chopped” or “rounded.” The term “chop” is used instead of “truncate’ in order to avoid confusion with truncation of series used in approximations for function subroutines.

FER FID /// /// FIUV!] FIU FIv FIC
)

FT // FN
7

04
4

RESERVED

RESERVED
MR-3607

Figure 9-4

Floating-Point Status Register

The FPS register contains an error flag and four condition codes (5 bits): carry, overflow, zero, and

negative, which are analogous to the processor status condition codes.
The FPP recognizes six floating-point exceptions:
Detection of the presence of the undefined variable in memory
Floating overflow
Floating underflow
Failure of floating-to-integer conversion

Attempt to divide by 0
Illegal floating op code

For the first four of these exceptions, bits in the FPS register are available to individually enable and
disable interrupts. An interrupt on the occurrence of either of the last two exceptions can be disabled

only by setting a bit that disables interrupts on all six of the exceptions, as a group.

Of the 13 FPS bits, 5 are set by the FPP as part of the output of a floating-point instruction: the error
flag and condition codes. Any of the mode and interrupt control bits may be set by the user; the LDFPS
instruction is available for this purpose. These thirteen bits are stored in the FPS register as shown in

Figure 9-4. The FPS register bits are described in Table 9-1.
9.4

FLOATING EXCEPTION CODE AND ADDRESS REGISTERS

Floating divide by 0

—
[N

Floating-to-integer conversion error

Floating overflow
Floating underflow

00 O\

Floating op-code error

One interrupt vector 1s assigned to take care of all floating-point exceptions (location 244g). The six
possible errors are coded in the 4-bit floating exception code (FEC) register as follows.

Floating undefined variable

9-4

Table 9-1

FPS Register Bits

Bit

Name

Description

Floating Error (FER)

The FER bit is set by the FPP if:
1.

division by zero occurs,

an illegal op code occurs,

3. any one of the remaining floating-point exceptions occurs
and the corresponding interrupt is enabled.

Note that the above action is independent of whether the FID
bit is set or clear.

Note also that the FPP never resets the FER bit. Once the
FER bit is set by the FPP, it can be cleared only by an
LDFPS instruction (note the RESET instruction does not
clear the FER bit). This means that the FER bit is up-to-date
only if the most recent floating-point instruction produced a
floating-point exception.

Interrupt Disable (FID)

If the FID bit is set, all floating-point interrupts are disabled.
NOTE

1. The FID bit is primarily a maintenance feature. It should
normally be clear. In particular, it must be clear if one
wishes to assure that storage of -0 by the FPP is always
accompanied by an interrupt.

2. Throughout the rest of this chapter assume that the FID bit
is clear in all discussions involving overflow, underflow, occurrence of —0, and integer conversion errors.

Reserved for future DIGITAL use.

Interrupt on Undefined
Variable (FIUV)

An interrupt occurs if FIUV is set and a —0 is obtained from
memory as an operand of ADD, SUB, MUL, DIV, CMP,

MOD, NEG, ABS, TST, or any LOAD instruction. The interrupt occurs before execution on the KEFI1-A except on
NEG, ABS, and TST for which it occurs after execution.
When FIUV is reset, —0 can be loaded and used in any FPP
operation. Note that the interrupt is not activated by the presence of —0 in an AC operand of an arithmetic instruction; in
particular, trap on —0 never occurs in mode 0.
The KEF11-AA will not store a result of —0 without the simultaneous occurrence of an interrupt.

9-5

Table 9-1

FPS Register Bits (Cont)

Bit

Name

Description

Interrupt on Underflow (FIU)

When the FIU bit is set, floating underflow will cause an interrupt. The fractional part of the result of the operation causing the interrupt will be correct. The biased exponent will be
too large by 400g, except for the special case of 0, which is
correct. An exception is discussed later in the detailed description of the LDEXP instruction.
If the FIU bit is reset and if underflow occurs, no interrupt
occurs and the result is set to exact 0.

Interrupt on Overflow
(FIV)

When the FIV bit is set, floating overflow will cause an interrupt. The fractional part of the result of the operation causing
the overflow will be correct. The biased exponent will be too
small by 400g.

If the FIV is reset and overflow occurs, there is no interrupt.
The FPP returns exact 0.

Special cases of overflow are discussed in the detailed descriptions of the MOD and LDEXP 1nstruction.

Interrupt on Integer

Conversion Error (FIC)

When the FIC bit is set and a conversion to integer instruction fails, an interrupt will occur. If the interrupt occurs, the
destination is set to 0, and all other registers are left untouched.

If the FIC bit is reset, the result of the operation will be the
same as detailed above, but no interrupt will occur.
The conversion instruction fails if it generates an integer with
more bits than can fit in the short or long integer word specified by the FL bit.

Floating DoublePrecision Mode (FD)

The FD bit determines the precision that is used for floatingpoint calculations. When set, double-precision is assumed;
when reset, single-precision is used.

Floating Long-

The FL bit is active in conversion between integer and floating-point formats. When set, the integer format assumed is
double-precision, 2’s complement (i.e., 32 bits). When reset,
the integer format is assumed to be single-precision, 2’s complement (i.e., 16 bits).

Integer Mode (FL)

9-6

Table 9-1

FPS Register Bits (Cont)

Bit

Name

Description

Floating Chop Mode (FT)

When the FT bit is set, the result of any arithmetic operation
is chopped (truncated). When reset, the result is rounded.

Reserved for future DIGITAL use.

Floating Negative (FN)

Floating Zero (FZ)

Floating Overflow (FV)

Floating Carry (FC)

FN is set if the result of the last operation was negative; oth-

erwise it is reset.

FZ is set if the result of the last operation was 0; otherwise it
1s reset.

FV is set if the last operation resulted in an exponent over-

flow; otherwise it is reset.

FC is set if the last operation resulted in a carry of the most

significant bit. This can only occur in floating or double-tointeger conversions.

The address of the instruction producing the exception is stored in the floating exception address (FEA)
register. The FEC and FEA registers are updated only when one of the following occurs.
1.
2.

Division by O.
Illegal op code.

Any of the other four exceptions with the corresponding interrupt enabled.

This implies that only when the FER bit is set by the FPP are the FEC and FEA registers updated.
NOTE

If one of the last four exceptions occurs with the
corresponding interrupt disabled, the FEC and
FEA are not updated.

If an exception occurs, inhibition of interrupts
by the FID bit does not inhibit updating of the
FEC and FEA.

The FEC and FEA are not updated if no exception occurs. This means that the STST (store
status) instruction will return current information only if the most recent floating-point instruction produced an exception.
Unlike the FPS, no instructions are provided for
storage into the FEC and FEA registers.

9-17

9.5 FLOATING-POINT PROCESSOR INSTRUCTION ADDRESSING
Floating-point processor instructions use the same type of addressing as the central processor instructions. A source or destination operand is specified by designating one of eight addressing modes and one
of eight central processor general registers to be used in the specified mode. The modes of addressing

are the same as those of the central processor, except in mode 0. In mode O the operand is located in the
designated floating-point processor accumulator rather than in a central processor general register. The
modes of addressing are as follows.
0 = FPP accumulator
1 = Deferred
2 = Autoincrement

3 = Autoincrement-deferred

4 = Autodecrement

5 = Autodecrement-deferred

6 = Indexed
7 = Indexed-deferred

Autoincrement and autodecrement operate on increments and decrements of 4g for F format and 10g
for D format.

In mode O users can make use of all six FPP accumulators (AC0-ACS5) as their source or destination.
Specifying FPP accumulators AC6 or AC7 will result in an illegal op code trap. In all other modes,
which involve transfer of data to or from memory or the general registers, users are restricted to the
first four FPP accumulators (AC0O-AC3). When reading or writing a floating-point number from or to
memory, the low memory word contains the most significant word of the floating-point number, and the
high memory word the least significant word.

9.6

ACCURACY

General comments on the accuracy of the FPP are presented here. The descriptions of the individual
instructions include the accuracy at which they operate. An instruction or operation is regarded as
“exact” if the result is identical to an infinite precision calculation involving the same operands. The a
priori accuracy of the operands is thus ignored. All arithmetic instructions treat an operand whose
biased exponent is 0 as an exact O (unless FIUV is enabled and the operand is —0, in which case an

interrupt occurs). For all arithmetic operations, except DIV, a 0 operand implies that the instruction is

exact. The same statement holds for DIV if the 0 operand is the dividend. But if it is the divisor, division is undefined and an interrupt occurs.

For nonvanishing floating-point operands, the fractional part is binary normalized. It contains 24 bits or
56 bits for floating mode and double mode, respectively. For ADD, SUB, MUL, and DIV, two guard
bits are necessary and sufficient for the general case to guarantee return of a chopped or rounded result
identical to the corresponding infinite precision operation chopped or rounded to the specified word
length. Thus, with two guard bits, a chopped result has an error bound of one least significant bit
(LSB); a rounded result has an error bound of 1/2 LSB. These error bounds are realized by the KEF11AA of all instructions. Both the FP11-A and the FP11-E have an error bound greater than 1/2 LSB for
ADD and SUB.

In the rest of this chapter, an arithmetic result is called exact if no nonvanishing bits would be lost by
chopping. The first bit lost in chopping is referred to as the “rounding” bit. The value of a rounded
result is related to the chopped result as follows.

9-8

If the rounding bit is 1, the rounded result is the chopped result incremented by an LSB.

If the rounding bit is 0, the rounded and chopped results are identical.

It follows that:

If the result is exact: rounded value = chopped value = exact value.

If the result is not exact, its magnitude is:
a.
b.
c.

always decreased by chopping.
decreased by rounding if the rounding bit 1s O.

increased by rounding if the rounding bit 1s 1.

Occurrence of floating-point overflow and underflow is an error condition: the result of the calculation
cannot be correctly stored because the exponent is too large to fit into the eight bits reserved for it.
However, the internal hardware has produced the correct answer. For the case of underflow, replacement of the correct answer by 0 is a reasonable resolution of the problem for many applications. This is
done by the KEF11-A if the underflow interrupt is disabled. The error incurred by this action is an
absolute rather than a relative error; it is bounded (in absolute value) by 2 ** (—128). There 1s no such
- simple resolution for the case of overflow. The action taken, if the overflow interrupt is disabled, is
described under FIV (bit 9) in Table 9-1.

The FIV and FIU bits (of the floating-point status word) provide users with an opportunity to implement their own correction of an overflow or underflow condition. If such a condition occurs and the
corresponding interrupt is enabled, the microcode stores the fractional part and the low eight bits of the
biased exponent. The interrupt will take place and users can identify the cause by examination of the
FV (floating overflow) bit of the FEC (floating exception) register. You can readily verify that (for the
standard arithmetic operations ADD, SUB, MUL, and DIV) the biased exponent returned by the instruction bears the following relation to the correct exponent generated by the microcode.

On overflow, it is too small by 400sg.

On underflow, if the biased exponent is 0, it is correct. If the biased exponent is not 0, 1t 18 too
large by 400sg.

Thus, with the interrupt enable, enough information is available to determine the correct answer. Users
may, for example, rescale their variables (via STEXP and LDEXP) to continue a calculation. Note that
the accuracy of the fractional part is unaffected by the occurrence of underflow or overflow.

9.7

FLOATING-POINT INSTRUCTIONS

Each instruction that references a floating-point number can operate on either single- or double-precision numbers, depending on the state of the FD mode bit. Similarly, there is a mode bit FL that determines whether a 32-bit integer (FL = 1) or a 16-bit integer (FL = 0) is used in conversion between
integer and floating-point representations. FSRC and FDST operands use floating-point addressing
modes (see Figure 9-5); SRC and DST operands use CPU addressing modes.

9-9

DOUBLE‘OPERAND ADDRESSING

FSRC,FDST,SRC,DST

FOC

OoC
|

]

SINGLE-:OPERAND ADDRESSING

FSRC, FDST, SRC, DST

FOC

OoC
|

]

OC = OPCODE = 17
FOC = FLOATING OPCODE

AC = FLOATING POINT ACCUMULATOR (ACO-AC3)

FSRC AND FDST USE FPP ADDRESSING MODES
SPC AND DST USE CPU ADDRESSING MODES

MR-3608

Figure 9-5

Floating-Point Addressing Modes

Terms Used in Instruction Definitions

=largest fraction that can be represented:
1 — 2 *¥* (=24), FD = 0; single-precision
1 — 2 ** (=56), FD = 1; double-precision

XL1 =smallest number that is not identically zero =
2 *¥* (—128)—(2 ** (—127)) * 1/2

XUL =largest number that can be represented =
2 ¥ (127) * XL

=largest integer that can be represented:
2 ** (15) — 1; FL = 0; short integer
2 **(31) — I; FL = 1; long integer

ABS (address) = absolute value of (address)

EXP (address) = biased exponent of (address)
LT.

=*less than”

.LE.

=*less than or equal to”

.GT.

=“greater than”

.GE.

=*‘‘greater than or equal to”

LSB

=least significant bit

Boolean Symbols

= AND

= inclusive OR

= exclusive OR

= NOT

ABSF/ABSD

1706 FDST

Make absolute floating/double
15
1

00
FDST

FDST

Format:

ABSF

Operation:

If (FDST) < 0, (FDST) — —(FDST).
If EXP(FDST) = 0, (FDST) «— exact 0.

For all other cases, (FDST) — (FDST).
FC — 0

Condition Codes:

FV «— 0

FZ — 1 if (FDST) = 0, else FZ «— 0
FN «— 0

FDST to its absolute value.

Set the contents of

Description:

If FIUV is enabled, trap on —0 occurs after execution. Overflow and underflow

Interrupts: -

cannot occur.

These instructions are exact.

Accuracy:

If a —0 is present in memory and the FIUV bit is enabled, an exact 0 is stored in

Special Comment:

memory. The condition codes reflect an exact 0 (FZ « 1).

ADDF/ADDD

172(AC)FSRC

Add floating /double
15
1

1
|

08
0

1T
|

05
FSRC

AC
|

|
MR-3611

FSRC,AC

Format:

ADDF

Operation:

Let SUM = (AC) + (FSRC)

If underflow occurs and FIU is not enabled, AC — exact 0.
0.
If overflow occurs and FIV is not enabled, AC « exact
For all others cases, AC «— SUM.
Condition Codes:

Description:

FC «— 0

FV — 1 if overflow occurs, else FV «— 0
FZ — 1 if (AC) = 0, else FZ — 0
FN « 1 if (AC) < 0, else FN «— 0

Add the contents of FSRC to the contents of AC. The addition is carried out in
single- or double-precision and is rounded or chopped in accordance with the values of the FD and FT bits in the FPS register. The result is stored in AC except
for:

1.
2.

Overflow with interrupt disabled.
Underflow with interrupt disabled.

For these exceptional cases, an exact 0 is stored in AC.
Interrupts:

If FIUV is enabled, trap on —0 in FSRC occurs before execution. If overflow or
underflow occurs, and if the corresponding interrupt is enabled, the trap occurs
with the faulty result in AC. The fractional parts are correctly stored. The exponent part is too small by 400g for overflow. It is too large by 400g for underflow,
except for the special case of 0, which is correct.

Accuracy:

Errors due to overflow and underflow are described above. If neither occurs, then:
for oppositely signed operands with exponent difference of O or 1, the answer returned is exact if a loss of significance of one or more bits can occur. Note that
these are the only cases for which loss of significance of more than one bit can
occur. For all other cases the result is inexact with error bounds of:
1. LSB in chopping mode with either single- or double-precision.
2. 1/2 LSB in rounding mode with either single- or double-precision.

Special Comment:

The undefined variable —0 can occur only in conjunction with overflow or underflow. It will be stored in AC only if the corresponding interrupt is enabled.

CFCC

170000

Copy floating condition codes
12

0
MR-3634

Format:

CFCC

Operation:

C — FC
V —FV

/ — FZ
N — FN

Description:

Copy the FPP condition codes into the CPU’s condition codes.

CLRF/CLRD

Clear floating/double

1704 FDST

0
)

0
L

Format:

CLRF

Operation:

(FDST) « exact O

Condition Codes:

FC — 0

1
|

0
|

FDST

FV — 0

FZ — 1
FN — 0

Description:

Set FDST to 0. Set FZ condition code and clear other condition code bits.

Interrupts:

No interrupts will occur. Overflow and underflow cannot occur.

Accuracy:

These instructions are exact.

CMPF/CMPD

Compare floating/double

173(AC+4)FSRC

1
1

Format:

Operation:
Condition Codes:

1
|

CMPF

1
1

1
L

1
|

FSRC

FSRCAC

(FSRC) «— (AC)
FC — 0
FV — 0

FZ — 1 if (FSRC) = 0, else FZ — 0
FN — 1 if (FSRC) < 0, else FN «— 0

9-13

Compare the contents of FSRC with the accumulator. Set the appropriate floating-point condition codes. FSRC and the accumulator are left unchanged except

Description:

as noted below.

Interrupts:

If FIUV is enabled, trap on —0 occurs before execution.

Accuracy:

These instructions are exact.

Special Comment:

An operand that has a biased exponent of 0 is treated as if it were an exact 0. In
this case, where both operands are 0, the FPP will store an exact 0 in AC.

DIVF/DIVD

174(AC+4)FSRC

Divide floating /double
15
1

)

08
1

07
A,C

05
|

FSIRC

FSRCAC

Format:

DIVF

Operation:

If EXP(FSRC) = 0, (AC) «— (AC) and the instruction is aborted.
If EXP(AC) = 0, (AC) «— exact O.

For all other cases, let QUOT = (AC)/(FSRC).

If underflo{vw occurs and FIU is not enabled, AC — exact 0.

If overflow occurs and FIV is not enabled, AC — exact 0.
For all others cases, AC — QUOT.
Condition Codes:

Description:

FC — 0

FV — 1 if overflow occurs, else FV «— 0
FZ — 1if (AC) = 0, else FZ — 0
FN — 1 if (AC) < 0, else FN «— 0

If either operand has a biased exponent of 0, it is treated as an exact 0. For FSRC
this would imply division by 0; in this case the instruction is aborted, the FEC
register is set to 4, and an interrupt occurs. Otherwise, the quotient is developed to
single- or double-precision with two guard bits for correct rounding. The quotient
is rounded or chopped in accordance with the values of the FD and FT bits in the
FPS register. The result is stored in the AC except for:
1.
2.

Overflow with interrupt disabled.
Underflow with interrupt disabled.

For these exceptional cases, an exact 0 is stored in AC.

If FIUV is enabled, trap on —0 in FSRC occurs before execution. If (FSRC) =
0, interrupt traps on an attempt to divide by 0. If overflow or underflow occurs,
and if the corresponding interrupt is enabled, the trap occurs with the faulty result
in AC. The fractional parts are correctly stored. The exponent part is too small by
400g for overflow. It is too large by 400g for underflow, except for the special case

Interrupts:

of 0, which is correct.

Errors due to overflow and underflow are described above. If none of these occurs,

Accuracy:

the error in the quotient will be bounded by 1 LSB in chopping mode and by 1/2
LSB in rounding mode.

Special Comment:

The undefined variable —0 can occur only in conjunction with overflow or underif the corresponding interrupt is enabled.
flow. It will be stored in AC only

LDCDF/LDCFD

Load and convert from double-to-floating

177(AC+4)FSRC

and from floating-to-double
15
1

08 |
1

ESRC

MR-3618

FSRC,AC

Format:

LDCDF

Operation:

If EXP(FSRC) = 0, AC — exact 0.

If FD = 1, FT = 0, FIV = 0 and rounding causes overflow, AC «— exact 0.

In all other cases, AC — Cxy(FSRC), where Cxy specifies conversion from float-

ing mode x to floating mode y.
x

=D,y = F if FD = 0 (single) LDCDF

y="Fy = D if FD = 1 (double) LDCFD
Condition Codes:

FC —0

FV — 1 if conversion produces overflow, else FV «— 0
— 0
FZ — 1 if (AC) = 0, else FZ
FN «— 1 if (AC) < 0, else FN «— 0

Description:

If the current mode is floating mode (FD = 0), the source is assumed to be a
double-precision number and is converted to single-precision. If the floating chop
bit (FT) is set, the number is chopped; otherwise, the number is rounded.
If the current mode is double mode (FD = 1), the source is assumed to be a
single-precision number and is loaded left-justified in AC. The lower half of AC is
cleared.

Interrupts:

If FIUV is enabled, trap on —0 occurs before execution. However, the condition
codes will reflect a fetch of —O0 regardless of the FIUV bit. Overflow cannot occur for LDCEFD.

A trap occurs if FIV is enabled, and if rounding with LDCDF causes overflow.
AC — overflowed result. This result must be +0 or —0. Underflow cannot occur.

Accuracy:

LDCFD is an exact instruction. Except for overflow, described above, LDCDF
incurs an error bounded by 1 LSB in chopping mode and by 1/2 LSB in rounding
mode.

LDCIF/LDCID/LDCLF/LDCLD
Load and convert integer or long integer

to floating or double-precision
15
1

1
1

1
.

177(AC)SRC
08
1

1
|

0
|

AC
|

SRC
|

]

Format:

LDCIF

SRC,AC

Operation:

AC — Cjx(SRC), where Cjx specifies conversion from integer mode j to floating
mode y.

j=I1ifFL =0,j=Lif FL =1

x =Fif FD =0,x = Dif FD = 1

Condition Codes:

FC — 0
FZ — 1if (AC) = 0, else FZ — 0
FN — 1 1if (Ac) < 0, else FN «— 0

Description:

Conversion is performed on the contents of SRC from a 2’s complement integer

with precision j to a floating-point number of precision x. Note that j and x are
determined by the state of the mode bits FL and FD.
If a 32-bit integer is specified (L mode) and (SRC) has an addressing mode of O or
immediate addressing mode is specified, the 16 bits of the source register are leftjustified and the remaining 16 bits loaded with Os before conversion.
In the case of LDCLF, the fractional part of the floating-point representation 1s
chopped or rounded to 24 bits for FT = 1 or 0, respectively.

Interrupts:

None; SRC is not floating-point, so trap on —0 cannot occur.

Accuracy:

LDCIF, LDCID, and LDCLD are exact instructions. The error incurred by
LDCLF is bounded by 1 LSB in chopping mode and by 1/2 LSB in rounding
mode.

9-16

LDEXP

176(AC+4)SRC

Load exponent
15

1
|

1
1

0
|

1
|

AC
|

SRC
|

SRC,AR

‘Format:

LDEXP

Operation:

NOTE: 177 and 200, appearing below, are octal numbers.
If —200 << SRC < 200, EXP(AC) — SRC + 200 and the rest of AC is unchanged.

If (SRC) > 177 and FIV is enabled, EXP(AC) — [(SRC) + 200]<7:0>.
If (SRC) > 177 and FIV is disabled, AC «— exact 0.

If <SRC) < —177 and FIU is enabled, EXP(AC) — [(SRC) + 200]<7:0>.
If (SRC) < —177 and FIU is disabled, AC «— exact 0.
Condition Codes:

FC «— 0
FV «— 1 if (SRC) > 177, else FV «— 0
FZ — 1if (AC) = 0, else FZ — O
«— 0
FN « 1 1if (AC) << 0, else FN

Description:

Change AC so that its unbiased exponent = (SRC). That is, convert (SRC) from
2’s complement to excess 200 notation and insert it into the EXP field of AC. This

is a meaningful operation only if ABS(SRC) LE 177.

If SRC > 177, tue result is treated as overflow. If SRC < — 177, the result is
treated as underflow. Note that the KEF11-A does not treat these abnormal conditions the same as the FP11-C and FP11-B do, but it does treat them the same as
the FP11-A and FP11-E do.

Interrupts:

No trap on —0 in AC occurs, even if FIUV is enabled. If SRC > 177 and FIV is
enabled, trap on overflow will occur. If SRC << —177 and FIU is enabled, trap on
underflow will occur.

Accuracy:

Errors due to overflow and underflow are described above. If EXP(AC) = 0 and
(SRC) #= —200, AC changes from a floating-point number treated as O by all
floating arithmetic operations to a non-0 number. This happens because the insertion of the “hidden” bit in the microcode implementation of arithmetic instruc-

tions is triggered by a nonvanishing value of EXP.

For all other cases, LDEXP implements exactly the transformation of a floatingpoint number (2 ** K) * f into (2 ** (SRC)) * f where 1/2 .LE. ABS(f) .LT. 1.

9-17

LDF/LDD

Load floating/double

172(AC+4)FSRC

1
J

1
1

Format:

LDF

Operation:

AC — (FSRCQ)

Condition Codes:

FC «— 0

0
L

FSRC

FSRC,AC

FV — 0

FZ — 1if (AC) = 0, else FZ — 0
FN — 1 i1f (AC) < 0, else FN «— 0

Description:

Load single- or double-precision number into AC.

Interrupts:

If FIUYV is enabled, trap on —0 occurs before AC is loaded. However, the condition codes will reflect a fetch of —O0 regardless of the FIUV bit. Overflow and
underflow cannot occur.

Accuracy:

These instructions are exact.

Special Comment:

These instructions permit use of —0 in a subsequent floating-point instruction if
FIUYV is not enabled and (FSRC) = —O0.

LDFPS

Load FPP’s program status
15

1701 SRC
12

Format:

LDFPS

Operation:

FPS — (SRC)

Description:

Load FPP’s status register from SRC.

Special Comment:

SRC

Users are cautioned not to use bits 13, 12, and 4 for their own purposes, since
these bits are not recoverable by the STFPS instruction.

9-18

MODF/MODD

Multiply and separate integer

171(AC+4)FSRC

and fraction floating /double

MR-3617

Format:

Description
and Operation:

MODF

FSRC,AC

This instruction generates the product of its two floating-point operands, separates
the product into integer and fractional parts, and then stores one or both parts as
floating-point numbers.

Let PROD = (AC) * (FSRC) so that in

Floating-point: ABS(PROD) = (2 ** K) * f, where
1/2 LE.f .LT. 1, and
EXP(PROD) = (200 + K)g

Fixed-point binary: PROD = N + g, where

N = INT(PROD) = integer part of PROD, and
g = PROD — INT(PROD) = fractional part of

PROD with 0 .LE. F .LT. 1.

Both N and f have the same sign as PROD. They are returned as follows:

If AC is an even-numbered accumulator (0 or 2), N is stored in AC+1 (1 or
3), and f is stored in AC.

If AC is an odd-numbered accumulator, N is not stored and g is stored in AC.
The two statements above can be combined as follows:

"N is returned to AC V 1 and g is returned to AC.

Five special cases occur, as indicated in the following formal description with L =
24 for floating mode and L = 56 for double mode.

1. If PROD overflows and FIV is enabled, ACV 1« N, chopped to L bits, AC
|

— exact 0.

Note that EXP(N) is too small by 400g and that —O0 can be stored in AC V 1.
If FIV is not enabled, AC V 1 « exact 0, AC «— exact 0, and —0 will never

be stored.

9-19

If 2 ** L .LE. ABS(PROD) and no overflow, AC V

1 « N, chopped to L

bits, AC «— exact 0.
The sign and EXP of N are correct, but low-order bit information, such as
parity, 1s lost.
If 1 .LE. ABS(PROD) .LT. 2 ** L, ACV 1 — N, AC «— g.
The integer part N 1is exact. The fractional part g is normalized, and chopped

or rounded in accordance with FT. Rounding may cause a return of # unity
for the fractional part. For L = 24, the error in g is bounded by 1 LSB in
chopping mode and by 1/2 LSB in rounding mode. For L = 56, the errorin g
increases from the above limits as ABS(N) increases above 8 because only 64
bits of PROD are generated.
If2**p.LE. ABS(N) .LT. 2 ** (p + 1), with p > 7, the low order p — 7 bits

of g may be in error.
If ABS(PR)D) .LT. 1 and no underflow, AC V 1 — exact 0 and AC — g.
There is no error in the integer part. The error in the fractional part is bounded
by 1 LSB in chopping mode and 1/2 LSB in rounding mode. Rounding may
cause a return of + unity for the fractional part.

If PROD underflows and FIU is enabled, AC V 1 « exact 0 and AC — g.
Errors are as in case 4, except that EXP(AC) will be too large by 400g (if EXP
= 0, it 1s correct). Interrupt will occur and —O0 can be stored in AC.
If FIU 1s not enabled, AC V 1 — exact 0 and AC «— exact 0.
For this case the error in the fractional part is less than 2 ** (—128).

Condition Codes;

FC — 0
FV «— 1 if PROD overflows, else FV «— 0

FZ — 11if (AC) =0, ¢else FZ — 0

FN — 1i1f (AC) < 0, else FN — 0
Interrupts:

If FIUV is enabled, trap on —0 in FSRC occurs before execution. Overflow and

underflow are discussed above.
Accuracy:

Discussed above.

Applications:

Binary-to-decimal conversion of a proper fraction. The following algorithm,
using MOD, will generate decimal digits D(1), D(2) . . . from left to right.
Initialize:

[ — O
X «— number to be converted;

ABS(X) < 1;
While X # 0 do
Begin PROD — X * 10;
[ —14+ 1;

D(I) — INT(PROD);
X «— PROD - INT(PROD);

End;

9-20

This algorithm is exact. It is case 3 in the description because the number of
nonvanishing bits in the fractional part of PROD never exceeds L, and hence
neither chopping nor rounding can introduce error.
2.

To reduce the argument of a trigonometric function.

ARG * 2/PI = N + g. The low two bits of N identify the quadrant, and g is
the argument reduced to the first quadrant. The accuracy of N 4 g is limited
to L bits because of the factor 2/PI. The accuracy of the reduced argument
thus depends on the size of N.

To evaluate the exponential function e ** x, obtain x * (log e base 2) = N +
g, thene ** x = (2 ** N) * (e ** (g * In 2)).

The reduced argument is g * 1n2 << 1 and the factor 2 ** N is an exact power
of 2, which may be scaled in at the end via STEXP, ADD N to EXP and
LDEXP. The accuracy of N + g is limited to L bits because of the factor (log
e base 2). The accuracy of the reduced argument thus depends on the size of
N.

MULF/MULD

Multiply floating /double

171(AC)FSRC

15
1

08
0

Format:

MULF

Operation:

Let PROD = (AC) * (FSRC)

06
AC

00
FSRC

FSRC,AC

If underflow occurs and FIU is not enabled, AC — exact O.

If overflow occurs and FIV is not enabled, AC « exact 0.
For all others cases, AC — PROD.
Condition Codes:

FC — 0
FV «— 1 if overflow occurs, else FV «— 0O
FZ — 11if (AC) = 0, else FZ — 0
FN — 1 1if (AC) < 0, else FN «— 0

Description:

If the biased exponent of either operand is 0, (AC) — exact 0. For all other cases
PROD is generated to 32 bits for floating mode and 64 bits for double mode. The
product is rounded or chopped for FT = 0 or 1, respectively, and is stored in AC
except for:

1.
2.

Overflow with interrupt disabled.
Underflow with interrupt disabled.

9-21

For these exceptional cases, an exact O is stored in AC.
Interrupts:

Accuracy:

Errors due to overflow and underflow are described above. If neither occurs, the
error incurred is bounded by 1 LSB in chopping mode and 1/2 LSB in rounding
mode.

Special Comment:

The undefined variable —O0 can occur only in conjunction with overflow or underflow. It will be stored in AC only if the corresponding interrupt is enabled.

NEGF/NEGD

Negate floating/double

1707 FDST

15
1

1
|

06
0
]

0
]

1
1

1
]

1
|

FDST
1

Format:

NEGF

Operation:

(FDST) « (FDST) if (FDST) # 0, else (FDST) «— exact 0

Condition Codes:

FDST

FC — 0
FV «— 0

FZ — 1 if (FDST) = 0, else FZ — 0
FN «— 1 if (FDST) < 0, else FN — 0O
Description:

Negate the single- or double-precision number; store result in same location
(FDST).

Interrupts:

If FIUV is enabled, trap on —0 occurs after execution. Overflow and underflow
cannot occur.

Accuracy:

These instructions are exact.

Special Comment:

If a —O0 is present in memory and the FIUV bit is enabled, the KEF11-AA stores
an exact 0 in memory. The condition codes reflect an exact 0 (FZ «— 1).

SETD

Set floating double mode

170011

MR-3628

9-22

Format;:

SETD

Operation:

FD «— 1

Description:

Set the FPP in double-precision mode.

SETF

Set floating mode

170001

15
1

]

00
0
|

0
|

0
1

0
l

]

Format:

SETF

Operation:

FD «— 0

Description:

Set the FPP in single-precision mode.

SETI

Set integer mode

177002

]

0
b

0
|

0
]

0
|

0
]

Format:

SETI

Operation:

FL — 0O

Description:

Set the FPP for short-integer data.

0
|

SETL

Set long-interger mode

177012

15
1

1
|

00
0
|

0
|

0
]

0
|

Format:

SETL

Operation:

FL — 1

Description:

Set the FPP for long-integer data.

0
|

0
1

9-23

STCFD/STCDF

Store and convert from floating-to-double

and from double-to-floating
1

176(AC)FDST
08

FDST

MR-3619

Format:

STCFD

AC,FDST

Operation:

If (AC) = 0, (FDST) « exact 0.
IfFD = 1, FT = 0, FIV = 0 and rounding causes overflow, (FDST) — exact 0.
In all other cases, (FDST) «— Cxy(AC), where Cxy specifies conversion from
floating mode x to floating mode y.

Condition Codes:

=F,y

=D,y

D if FD = 0 (single) STCFD
Fif FD = 1 (double) STCDF

FC — 0

FV « 1 if conversion produces overflow, else FV «— 0
FZ — 1if (AC) = 0, else FZ — 0
FN — 1 if (AC) < 0, else FN «— 0
Description:

If the current mode is single-precision, the accumulator is stored left-justified in
FDST and the lower half is cleared.
If the current mode is double-precision, the contents of the accumulator are converted to single-precision, chopped or rounded depending on the state of FT, and
stored in FDST.

Interrupts:

Trap on —O0 will not occur even if FIUV is enabled because FSRC is an accumulator. Underflow cannot occur. Overflow cannot occur for STCFD.
A trap occurs if FIV is enabled, and if rounding with STCDF causes overflow.
(FDST) « overflowed result. This must be +0 or —O0.

Accuracy:

STCFD is an exact instruction. Except for overflow, described above, STCDF incurs an error bounded by 1 LSB in chopping mode and by 1/2 LSB in rounding
mode.

STCFI/STCFL/STCDI/STCDL

Store and convert from floating or double

to integer or long integer

175(AC+4)DST

1
|

0
]

1
|

AC
|

.
|

]

DST
|

I\
MR-3621

9-24

Format:

Operation:

AC,DST

STCFI

(DST) — Cxj(AC) if —JL — 1 < Cxj(AC) < JL + 1, else (DST) — 0, where
Cjx specifies conversion from floating mode x to integer mode j.
=1
i=TifFL=0,j=LifFL
x = Fif FD =0,x = Dif FD = 1
JL i1s the largest integer.
2% 15 — 1 for FL = 0
2 **% 32 — 1 for FL =1

Condition Codes:

C,FC — 0if —JL — 1 < Cxj(AC) < JL + 1, else C, FC « 1
V,FV «— 0

Z, FZ — 11f (DST) = 0, else Z, FZ — 0O
N, FN «— 1 if (DST) < 0, else N, FN — 0
Description:

Conversion is performed from a floating-point representation of the data in the

accumulator to an integer representation.

If the conversion is to a 32-bit word (L mode), and an addressing mode of O or
immediate addressing mode is specified, only the most significant 16 bits are
stored in the destination register.

If the operation is out of the integer range selected by FL, FC is set to 1 and the

contents of the DST are set to O.

Nuimbers to be converted are always chopped (rather than rounded) before they
are converted. This is true even when the chop mode bit FT is cleared in the FPS
register.
Interrupts:

Accuracy:

These instructions do not interrupt if FIUV is enabled, because the —O0, 1f present,
is in AC, not in memory. If FIC is enabled, trap on conversion failure will occur.

These instructions store the integer part of the floating-point operand, which may
not be the integer most closely approximating the operand. They are exact if the
integer part is within the range implied by FL.

STEXP

175(AC)DST

Store exponent
12

1
]

]

AC
|

DST
1

]

]
MR-3623

Format:

STEXP

AC,DST

Operation:

(DST) — EXP(AC) — 2003

9-25

Condition Codes:

C,FC — 0
V,FV «— 0

Z,FZ — 11f (DST) = 0,¢else Z, FZ — 0
N, FN — 1 if (DST) < 0, else N, FN «— 0

Description:

Convert AC’s exponent from excess 200 notation to 2’s complement and store the
result in DST.

Interrupts:

This instruction will not trap on —0. Overflow and underflow cannot occur.

Accuracy:

This instruction is exact.

STF/STD

Store floating/double

174(AC)FDST

]

0
|

Format:

STF

Operation:

(FDST) — AC

Condition Codes:

0
]

FDST

]

AC,FDST

FC — FC
FV — FV
FZ — FZ

FN — FN

Description:

Store single- or double-precision number from AC.

Interrupts:

These instructions do not interrupt if

FIUV is enabled, because the —0, if present,

is in AC, not in memory. Overflow and underflow cannot occur.

Accuracy:

These instructions are exact.

Special Comment:

These instructions permit storage of a —0 in memory from AC. There are two

conditions in which —O0 can be stored in AC of the KEF11-A. One occurs when
underflow or overflow is present and the corresponding interrupt is enabled. A
second occurs when an LDF, LDD, LDCDF, or LDCFD instruction is executed
and the FIUV bit is disabled.

STFPS

Store FPP’s program status

1702 DST

1
|

0
1

0
|

0
]

1
|

0
I

DST
J

]

|
MR-3632

9-26

DST

Format:

STFPS

Operation:

(DST) «— FPS

Description:

Store FPP’s status register in DST.

Special Comment:

Bits 13, 12, and 4 are loaded with 0. All other bits are the corresponding bits in
|
the FPS.

STST

1703 DST

Store FPP’s status
15
1

Format:

STST

Operation:

(DST) — FEC

06
0

DST

(DST + 2) — FEA

Description:

Store the FEC and FEA in DST and DST+
2. Note the following.
1.

If the destination mode specifies a general register or immediate addressing,

only the FEC is saved.

The information in these registers is current only if the most recently executed
floating-point instruction caused a floating-point exception.

SUBF/SUBD

173(AC)FSRC

Subtract floating/double
15

1
|

]

FSRC

1
]

]

FSRC,AC

Format:

SUBF

Operation:

Let DIFF = (AC) — (FSRC)
If underflow occurs and FIU is not enabled, AC «— exact O.

If overflow occurs and FIV is not enabled, AC — exact 0.
For all others cases, AC — DIFF.

9-27

]

Condition Codes:

FC — 0
FV «— 1 if overflow occurs, else FV «— 0
FZ — 11f (AC) = 0, else FZ — 0

FN — 1 if (AC) << 0, else FN «— 0
Subtract the contents of FSRC from the contents of AC. The subtraction is car-

Description:

ried out in single- or double-precision and is rounded or chopped in accordance
with the values of the FD and FT bits in the FPS register. The result is stored in
AC except for:
1.

Overflow with interrupt disabled.

Underflow with interrupt disabled.

For these exceptional cases, an exact 0 is stored in AC.
Interrupts:

If FIUV 1is enabled, trap on —0 in FSRC occurs before execution. If overflow or
underflow occurs, and if the corresponding interrupt is enabled, the trap occurs

with the faulty result in AC. The fractional parts are correctly stored. The exponent part 1s too small by 400g for overflow. It is too large by 400g for underflow,

except for the special case of 0, which is correct.
Accuracy:

Errors due to overflow and underflow are described above. If neither occurs: for
like-signed operands with exponent difference of O or 1, the answer returned is
exact if a loss of significance of one or more bits can occur. Note that these are

the only cases for which loss of significance of more than one bit can occur. For all
other cases the result is inexact with error bounds of:
1.
2.
Special Comment:

LSB in chopping mode with either single- or double-precision.

1/2 LSB in rounding mode with either single- or double-precision.

The undefined variable —0 can occur only
in conjunction with overflow or underflow. It will be stored in AC only if the corresponding interrupt is enabled.

TSTF/TSTD

Test floating/double

1705 FDST

1
1

1
|

Format:

TSTF

Operation:

(FDST)

Condition Codes:

0
1

0
]

1
|

0
]

1
|

FODST
1

FDST

FC «— 0
FV — 0

FZ — 1 if (FDST) = 0, else FZ — 0

FN — 1 if (FDST) < 0, else FN «— 0
Description:

Set the FPP condition codes according to the contents of FDST.

9-28

Interrupts:

If FIUV is set, trap on —0 occurs after execution. Overflow and underflow cannot
OCCur.

Accuracy:

These instructions are exact.

9-29

CHAPTER 10

PROGRAMMING TECHNIQUES

INTRODUCTION

10.1

The KDF11-BA offers a great deal of programming flexibility and power. Utilizing the combination of
the instruction set, the addressing modes, and the programming techniques makes it possible to develop
new software or to utilize old programs effectively. The programming techniques in this chapter show
the capabilities of the KDF11-BA. The techniques discussed involve position-independent coding
(PIC), stacks, subroutines, interrupts, reentrancy, coroutines, recursion, processor traps, programming
peripherals, and conversion.

10.2

POSITION-INDEPENDENT CODE

The output of a MACRO-11 assembly is a relocatable object module. The task builder or linker binds
one or more modules together to create an executable task image. Once built, a task can only be loaded
and executed at the virtual address specified at link time. This is so because the linker has had to modify some instructions to reflect the memory locations in which the program is to run. Such a body of
code is considered position-dependent (i.e., dependent on the virtual addresses to which it was bound).
The KDF11-BA processor offers addressing modes that make it possible to write instructions that do
not depend on the virtual addresses to which they are bound. This type of code is termed position-independent and can be loaded and executed at any virtual address. Position-independent code can improve
system efficiency, both in use of virtual address space and in conservation of physical memory.
In multiprogramming systems like RSX-11M, it is important that many tasks be able to share a single
physical copy of common code (a library routine, for example). To make the optimum use of a task’s
virtual address space, shared code should be position-independent. Code that is not position-independent can also be shared, but it must appear in the same virtual locations in every task using it. This
restricts the placement of such code by the task builder and can result in the loss of virtual addressing
space.

10.2.1

Use of Addressing Modes in the Construction of Position-Independent Code

The construction of position-independent code is closely linked to the proper use of addressing modes.
The remainder of this explanation assumes you are familiar with the addressing modes described in
Chapter 6.

The following addressing modes, which involve only register references, are position-independent.
R
(R)
(R)+
@*R)+
—(R)

@—(R)

Autodecrement-deferred mode

10-1

When employing these addressing modes, the user is guaranteed position independence, providing the
contents of the registers have been supplied independently of a particular virtual memory location.
Two relative addressing modes are position-independent when a relocatable address is referenced from
a relocatable instruction:
A
@A

Relative mode
Relative-deferred mode

Relative modes are not position-independent when an absolute address (that is, a nonrelocatable address) is referenced from a relocatable instruction. In such case, absolute addressing (i.e., @#A) may be
employed to make the reference position-independent.
Index modes can be either position-independent or position-dependent, according to their use in the
program:

X(R)
@X(R)

Index mode
Index-deferred mode

If the base, X, is an absolute value (e.g., a control block offset), the reference is position-independent.
The following is an example.
MOV

2(SP),R0

.POSITION-INDEPENDENT

N=4
MOV

N(SP),R0

.POSITION-INDEPENDENT

If, however, X is a relocatable address, the reference is position-dependent, as the following example
shows.

CLR

ADDR(R1)

;POSITION-DEPENDENT

Immediate mode can be either position-independent or not, according to its use. Immediate mode references are formatted as follows.

Immediate mode

When an absolute expression defines the value of N, the code is position-independent. When a relocatable expression defines N, the code is position-dependent. That is, immediate mode references are position-independent only when N is an absolute value.
Absolute mode addressing is position-independent only in those cases where an absolute virtual location
is being referenced. Absolute mode addressing references are formatted as follows.
@#A

Absolute mode

10-2

An example of a position-independent absolute reference is a reference to the processor status word
(PS) from a relocatable instruction, as in this example.

MOV
10.2.2

@#PSW,RO

‘RETRIEVE STATUS AND PLACE IN REGISTER

Comparison of Position-Dependent and Position-Independent Code

The RSX-11 library routine, PWRUP, is a FORTRAN-callable subroutine for establishing or removing
a user power failure asynchronous system trap (AST) entry point address. Imbedded within the routine
~is the actual AST entry point that saves all registers, effects a call to the user-specified entry point,
restores all registers on return, and executes an AST exit directive. The following examples are excerpts
from this routine. The first example has been modified to illustrate position-dependent references. The
second example is the position-independent version.

Position-Dependent Code
PWRUP::

CLR
CALL

—(SP)
X.PAA

:ASSUME SUCCESS
:PUSH (SAVE)

.WORD

1..$PSW

‘CLEAR PSW, AND

MOV

$OTSV,R4

-GET OTS IMPURE

MOV

(SP)+,R2

:GET AST ENTRY

BNE

109

-IF NONE SPECIFIED,

CLR

—(SP)

‘RECOVERY AST SERVICE

‘ARGUMENT ADDRESSES
:ONTO STACK

10$:

BA:

:SET R1=R2SP

:AREA POINTER

:POINT ADDRESS

:SPECIFY NO POWER

208

MOV
MOV

R2,F.PF(R4)
#BA,— (SP)

:SET AST ENTRY POINT
:PUSH AST SERVICE

CALL

X.EXT

-ISSUE DIRECTIVE, EXIT.

:ADDRESS

.BYTE

109.,2.

MOV
MOV
MOV

RO,—(SP)
R1,—(SP)
R2,—(SP)

:PUSH (SAVE) RO
:PUSH (SAVE) R1
:PUSH (SAVE) R2

10-3

Position-Independent Code
PWRUP::

CLR
CALL

—(SP)
X.PAA

-ASSUME SUCCESS
‘PUSH ARGUMENT
-ADDRESSES ONTO

.WORD
MOV

1. $PSW
|
@#$OTSV,R4

MOV

(SP)+,R2

BNE

10%

STACK
‘CLEAR PSW, AND
SET R1=R2—-SP.
‘GET OTS IMPURE
:AREA POINTER
:GET AST ENTRY
‘POINT ADDRESS
‘IF NONE SPECIFIED,
‘SPECIFY NO POWER
‘RECOVERY AST SERVICE

CLR

—(SP)

209

MOV
MOV
ADD

R2,F.PF(R4)
PC,—(SP)
#BA —.,(SP)

‘SET AST ENTRY POINT
:PUSH CURRENT LOCATION
‘COMPUTE ACTUAL LOCATION
‘OF AST

CALL
BYTE

X.EXT
109.,2.

ISSUE DIRECTIVE, EXIT.

10$:

208:

-ACTUAL AST SERVICE ROUTINE:

: 1) SAVE REGISTERS
. 2) EFFECT A CALL TO SPECIFIED
: SUBROUTINE
: 3) RESTORE REGISTERS
: 4) ISSUE AST EXIT DIRECTIVE

BA:

MOV
MOV
MOV

RO,—(SP)
R1,—(SP)
R2,—(SP)

:PUSH (SAVE) RO
:PUSH (SAVE) R1
:PUSH (SAVE) R2

The position-dependent version of the subroutine contains a relative reference to an absolute symbol
($OTSV) and a literal reference to a relocatable symbol (BA). Both references are bound by the task
builder to fixed memory locations. Therefore, the routine will not execute properly as part of a resident
library if its location in virtual memory is not the same as the location specified at link time.

In the position-independent version, the reference to $OTSV has been changed to an absolute reference. In addition, the necessary code has been added to compute the virtual location of BA based upon
the value of the program counter. In this case, the value is obtained by adding the value of the program
counter to the fixed displacement between the current location and the specified symbol. Thus, execution of the modified routine is not affected by its location in the image’s virtual address space.
10.3 STACKS
The stack is part of the basic design architecture of the KDF11-BA. It is an area of memory set aside
by the programmer or the operating system for temporary storage and linkage. It is handled on a LIFO
(last-in/first-out) basis, where items are retrieved in the reverse of the order in which they were stored.
A stack starts at the highest location reserved for it and expands linearly downward to lower addresses
as items are added.

10-4

It is not necessary to keep track of the actual locations into which data is being stacked. This 1s done
automatically through a stack pointer. To keep track of the last item added to the stack, a general
register is used to store the memory address of the last item in the stack. Any register except register 7
(the PC) may be used as a stack pointer under program control; however, instructions associated with
subroutine linkage and interrupt service automatically use register 6 as a hardware stack pointer. For
this reason, R6 is frequently referred to as the system SP. Stacks may be maintained in either full-word
or byte units. This is true for a stack pointed to by any register except Ro, which must be organized in
full-word units only. Byte stacks (see Figure 10-1) require instructions capable of operating on bytes
rather than full words.

WORD STACK

007100

ITEM # 1

007076

ITEM # 2

007074

ITEM# 3

ITEM # 4

007072

<P |

007072

]

<SP |

007075

]

007070

007066
007064

BYTE STACK

007100

ITEM # 1

007077

ITEM # 2

007076

ITEM # 3

007075

ITEM # 4

NOTE:

BYTES ARE

IN
ARRANGED

WORDS AS FOLLOWING:
BYTE3 | BYTE 2

BYTE1 | BYTEO
.

WORD
MR-3662

Figure 10-1

10.3.1

Word and Byte Stacks

Pushing onto a Stack

Items are added to a stack using the autodecrement addressing mode. Adding items to the stack is

called PUSHing, and is accomplished by the following instructions.

MOV

Source,— (SP)

‘MOYV contents of source word

Source, — (SP)

‘MOVB source byte onto

:onto the stack
or

MOVB

‘the stack

Data is thus PUSHed onto the stack.

10-5

10.3.2

Popping from a Stack

Removing data from the stack is called POPping. This operation is accomplished using the autoincrement mode.

MOV
|

(SP)+ ,Destination

:MOYV destination word
-off the stack

MOVB

(SP)+ ,Destination

:-MOVB destination byte

:off the stack

After an item has been popped, its stack location is considered free and available for other use. The
stack pointer points to the last-used location, implying that the next lower location is free. Thus, a stack
may represent a pool of sharable temporary storage locations. (See Figure 10-2.)
HIGH MEMORY
<— SP

stack¥

<—SP

LOW MEMORY

AN EMPTY STACK AREA

2 PUSHING A DATUM

3 PUSHING ANOTHER

ONTO THE STACK

DATUM ONTO THE
STACKS

A E2

<—SP

4 ANOTHER PUSH

5 POP

<—SP

6 PUSH

<@— SP

7 POP
MR-3663

Figure 10-2

Push and Pop Operations

10.3.3 Deleting Items from a Stack
The following techniques may be used to delete from a stack. To delete one item use:

INC SP or TSTB(SP)+ for a byte stack
To delete two items use:
ADD#2,SP or TST(SP)+ for word stack
To delete fifty items from a word stack use:

ADD#100.,SP

10-6

10.3.4 Stack Uses
A stack is used in the following ways.
1.

Often one of the general-purpose registers must be used in a subroutine or interrupt service
routine and then returned to its original value. The stack can be used to store the contents of
the registers involved.

The stack is used in storing linkage information between a subroutine and its calling program. The JSR instruction, used in calling a subroutine, requires the specification of a linkage register along with the entry address of the subroutine. The content of this linkage register is stored on the stack, so as not to be lost, and the return address is moved from the PC to
the linkage register. This provides a pointer back to the calling program so that successive
arguments may be transmitted easily to the subroutine.
If no arguments need be passed by stacking them after the JSR instruction, the PC may be
used as the linkage register. In this case, the result of the JSR is to move the return address
in the calling program from the PC onto the stack and replace it with the entry address of the
called subroutine.

In many cases, the operations performed by the subroutine can be applied directly to the data
located on or pointed to by a stack without the need to move the data into the subroutine
arca.

Example:

;CALLING PROGRAM

MOV SP,R1
JSR PC,SUBR

;R1 IS USED AS THE STACK
;POINTER HERE.

ADD (R1)+,(R1)

ADD ITEM #1 TO #2, PLACE

.SUBROUTINE

‘RESULT IN ITEM #2,
-R1 POINTS TO
ITEM #2 NOW

Because the hardware already uses general-purpose register R6 to point to a stack for saving
and restoring PC and processor status word (PS) information, it is convenient to use the same
stack to save and restore immediate results and to transmit arguments to and from subroutines. Using R6 in this manner permits extreme flexibility in nesting subroutines and interrupt service routines.

Since arguments may be obtained from the stack by using some form of register-indexed addressing, it is sometimes useful to save a temporary copy of R6 in some other register which
has been saved at the beginning of a subroutine. If R6 is saved in R5 at the beginning of the
subroutine, R5 may be used to index the arguments. During this time R6 is free to be incremented and decremented while being used as a stack pointer. If R6 had been used directly
as the base for indexing and not “copied,” it might be difficult to keep track of the position in
the argument list, since the base of the stack would change with every autoincrement/decrement that occurred.

However, if the contents of R6 (SP) are saved in RS before any arguments are pushed onto

the stack, the position relative to RS would remain constant.

10-7

Return from a subroutine also involves the stack, as the return instruction, RTS, must retrieve information stored there by the JSR.
|

When a subroutine returns, it is necessary to “clean up” the stack by eliminating or skipping
over the subroutine arguments. One way this can be done is by insisting that the subroutine
keep the number of arguments as its first stack item. Returns from subroutines then involve
calculating the amount by which to reset the stack pointer, resetting the stack pointer, then
storing the original contents of the register that were used as the copy of the stack pointer.

Stack storage is used in trap and interrupt linkage. The program counter and the processor
status word of the executing program are pushed on the stack.
When the system stack is being used, nesting of subroutines, interrupts, and traps to any level
can occur until the stack overflows its legal limits.
The stack method is also available for temporary storage of any kind of data. It may be used
as a LIFO list for storing inputs, intermediate results, etc.
10.3.5.

Stack Use Examples

As an example of stack use, consider this situation: a subroutine (SUBR) wants to use registers 1 and 2,
but these registers must be returned to the calling program with their contents unchanged. The subroutine could be written as follows.
Not using the stack:

Assembler

Address

Octal Code

Syntax

Comments

076322
076324
076326
076330

010167 SUBR:
000074
010267
000072

MOV R1,TEMPI1
*
MOV R2,TEMP?2
*

;save R1

076410
076412
076414
076416
076420
076422
076424

016701
000006
0167902
000004
000297
000000
000000

MOV TEMP1,R1
*
MOV TEMP2,R2
*
RTS PC
TEMP1:0
TEMP2:0

‘restore R1

*Index constants

10-8

:save R2

:;restore R2

Using the stack:

R3 has been previously set to point to the end of an unused block of memory.

Assembler

Address

010020
010022

Octal Code

Syntax

Comments

010143 SUBR:
010243

MOV R1,—(R3)
MOV R2,—(R3)

;push R1
;push R2

MOV (R3)+,R2

.pop R2

010130 | 012302

010132
010134

012301
000207

MOV (R3)+,R1
RTS PC

;pop R1

Note: In this case R3 was used as a stack pointer.

The second routine uses four fewer words of instruction code and two words of temporary “stack’ storage. Another routine could use the same stack space at some later point. Thus, the ability to share
temporary storage in the form of a stack is a way to save on memory use.
As another example of stack use, consider the task of managing an input buffe from a terminal. As
characters come in, the user may wish to delete characters from the line; this is accomplished very
easily by maintaining a byte stack containing the input characters. Whenever a backspace is received, a
character is “popped” off the stack and eliminated from consideration. In this example, “popping”
characters to be eliminated can be done by using either the MOVB (MOVE BYTE) or INC (INCREMENT) instructions.

001006

001005
001004
001003

001002
001001

INC

Z|O0|dlw»w|C|o

001007

001011
001010

Nlo|m|=z|ojd|w|c|o

Note that in this case the increment instruction (INC) is preferable to MOVB, since it accomplishes
the task of eliminating the unwanted character from the stack by readjusting the stack pointer without
the need for a destination location. Also, the stack pointer (SP) used in this example cannot be the
system stack pointer because R6 may point only to word (even) locations. (See Figure 10-3.)

<R3
|

001001

<R3 |

001002 |

|
MR-3664

Figure 10-3

Byte Stack Used as a Character Buffer

10-9

10.3.6 Subroutine Linkage
The contents of the linkage register are saved on the system stack when a JSR is executed. The effect is
the same as if a MOV reg, —(R6) had been performed. Following the JSR instruction, the same register
is loaded with the memory address (the contents of the current PC), and a jump is made to the entry
location specified.
|

Figure 10-4 shows the conditions before and after executing the subroutine instructions

BEFORE

AFTER

(RS) = 000132

(R5) = 001004

(R6) = 001776

(R6) = 001774

(PC) = (R7) = 001000

(PC) = (R7) = 001064

002000
001776

nnnnnn
mmmmmm

002000
001776

nnnnnn
mmmmmm

001774

000132

001772

<~ SP [

001776

]

<Sp|

001774

JSR RS5, 1064.

MR-3665

Figure 10-4

JSR Stack Condition Example

Because hardware already uses general-purpose register R6 to point to a stack for saving and restoring
PC and PS (processor status word) information, it is convenient to use that stack to save and restore
intermediate results and to transmit arguments to and from subroutines. Using R6 this way permits
nesting subroutines and interrupt service routines.
10.3.6.1 Return from a Subroutine — An RTS instruction provides for a return from the subroutine to
the calling program. The RTS instruction must specify the same register as the one the JSR instruction
used in the subroutine call. When the RTS is executed, the register specified is moved to the PC, and
the top of the stack is placed in the register specified. Thus, an RTS PC has the effect of returning to
the address specified on the top of the stack.

10.3.6.2 Subroutine Advantages — There are several advantages to the subroutine calling procedure

affected by the JSR instruction.

Arguments can be passed quickly between the calling program and the subroutine.

If there are no arguments, or the arguments are in a general register or on the stack, the JSR
PC,DST mode can be used so that none of the general-purpose registers are used for linkage.

Many JSRs can be executed without the need to provide any saving procedure for the linkage
information, since all linkage information is automatically pushed onto the stack in sequential order. Returns can be made by automatically popping this information from the stack in
the order opposite to the JSRs.

Such linkage address bookkeeping is called automatic “nesting” of subroutine calls. This feature enables construction of fast. efficient linkages in a simple, flexible manner. It also permits a routine to call
itself.
10.3.7

Interrupts

An interrupt is similar to a subroutine call, except that it is initiated by the hardware rather than by the
software. An interrupt can occur after the execution of an instruction.

10-10

Interrupt-driven techniques are used to reduce CPU waiting time. In direct program data transfer, the

CPU loops to check the state of the DONE/READY flag (bit 7) in the peripheral interface. Using
interrupts, the CPU can handle other functions until the peripheral initiates service by setting the
DONE bit in its control/status register. The CPU completes the instruction being executed and then
acknowledges the interrupt, and vectors to an interrupt service routine. The service routine will transfer
the data and may perform calculations with it. After the interrupt service routine has been completed,
the computer resumes the program that was interrupted by the peripheral’s high-priority request.
10.3.7.1

Interrupt Service Routines — With interrupt service routines, linkage information is passed so

that a return to the main program can be made. More information is necessary for an interrupt sequence than for a subroutine call because of the random nature of interrupts. The complete machine
state of the program immediately prior to the occurrence of the interrupt must be preserved in order to
return to the program without any noticeable effects. This information is stored in the processor status

word (PS). Upon interrupt, the contents of the program counter (PC) (address of next instruction) and
the PS are automatically pushed onto the R6 system stack. The effect is the same as if:
MOV PS,—(SP)

-Push PS

MOV PC,—(SP)

:Push PC

had been executed. The new contents of the PC and PS are loaded from two preassigned consecutive
memory locations which are called “vector addresses.”
The first word contains the interrupt service routine entry address (the address of the service routine
program sequence), and the second word contains the new PS that will determine the machine status,

including the operational mode and register set to be used by the interrupt service routine. The contents
of the vector address are set under program control.

After the interrupt service routine has been completed, an RTI (return from interrupt) is performed.
The top two words of the stack are automatically “popped” and placed in the PC and PS, respectively,

thus resuming the interrupted program. Interrupt service programming is intimately involved with the
concept of CPU and device priority levels.

10.3.7.2

Nesting — Interrupts can be nested in much the same manner that subroutines are nested. It is

possible to nest any arbitrary mixture of subroutines and interrupts without any confusion. When the
respective RTI and RTS instructions are used, the proper returns are automatic. (See Figure 10-5.)
10.3.8

Reentrancy

Other advantages of the KDF11-BA stack organization occur in programming systems that handle several tasks. Multitask program environments range from simple single-user applications that manage a
mixture of I/O interrupt service and background data processing (as in RT-11), to large, complex multiprogramming systems that manage an intricate mixture of executive and multiuser programming situ-

ations (as in RSX-11). In all these situations, using the stack as a programming technique provides
flexibility and time/memory economy by allowing many tasks to use a single copy of the same routine
with a simple straightforward way of keeping track of complex program linkages.

The ability to share a single copy of a program among users or among tasks is called reentrancy. Reentrant program routines differ from ordinary subroutines in that it is not necessary for reentrant routines
to finish processing a given task before they can be used by another task. Multiple tasks can exist at any
time in varying stages of completion in the same routine. Thus, the situation as shown in Figure 10-6
may OcCcur.

10-11

PROCESS 0 IS RUNNING; SP IS
POINTING TO LOCATION PO.

7.. SUBROUTINE A RELEASES THE
TEMPORARY STORAGE HOLDING

SP — PO

PSO

PCO

TA1 AND TA2.

TEO
TE1

INTERRUPT STOPS PROCESS O WITH
PC = PCO, AND STATUS = PSO; STARTS

PROCESS 1.

SP —>

PS1
PC1

PSO

PCO

SP —2

PROCESS 1 USES STACK FOR TEM-

PORARY STORAGE (TEO, TE1).

PSO

PCO
SP —p

PC2

SUBROUTINE A RETURNS CONTROL

TO PROCESS 2 WITH AN RTS R7; PC
IS RESET TO PC2.

550
BCO

TEO

TE1

TE1
PS1

PROCESS 1 INTERRUPTED WITH PC

SP—e

= PC1 AND STATUS = PS1;: PROCESS

PSO

2 1S STARTED.

PCO

TEO

PROCESS 2 COMPLETESWITH AN

RT1 INSTRUCTIONS (DISMISSES

PST

AND STATUS IS RESET TO PS1;

SP—>

PROCESS 1 RESUMES'

PC1

PROCESS 2 IS RUNNING AND DOES

PSO

PCO

INTERRUPT) PC IS RESET OT PC (1)

TET

Sp—>

PC1

TEO

TE1

10.

PROCESS 1 RELEASES THE TEMPO-

A JSR R7,A TO SUBROUTINE A WITH

PSO

RARY STORAGE HOLDING TEO AND

PC = PC2.

PCO

TE1.

550

SP —2

PCO

TEO

TE1
PS1

SP—>

PC1

PC2

11.

OPERATION WITH AN RT1,PC IS

SP— PO

RESET TO PCO, AND STATUS IS

0
SUBROUTINE A IS RUNNING AND

PROCESS 1 COMPLETES ITS

RESET TO PSO.

USES STACK FOR TEMPORARY

PSO

PCO

STORAGE.

TEO
TE1
PS1

PC1
PC2

TA1

SP =

TA2

4]
MR-3666

Figure 10-5

Nested Interrupt Service Routines and Subroutines

10-12

MEMORY

////////////////

PROGRAM1 77 SUBROUTINE A/

PROGRAM 1
PROGRAM 2

SUBROUTINE

IRIIAIIIIr AN,

PROGRAM 3

PROGRAM 2

////////////////

/SUBROUTINE A /

7L
L LT

PROGRAM 3

7SS

SUBROUTINE A

LT L L //

KDF11-BA APPROACH

CONVENTIONAL APPROACH

PROGRAMS 1, 2, AND 3 CAN SHARE

A SEPARATE COPY OF SUBROUTINE A

SUBROUTINE A.

MUST BE PROVIDED FOR EACH PROGRAM.
MR-3667

Figure 10-6

Reentrant Routines

10.3.8.1 Reentrant Code — Reentrant routines must be written in pure code (that is, any code that
consists exclusively of instructions and constants). The value of using pure code whenever possible is
that the resulting code has the following characteristics.
1.
2.

It is generally considered easier to debug.
It can be kept in read-only memory (is read-only protected).

hn b

—

Using reentrant code, control of a routine can be shared as follows. (See Figure 10-7.)
Task A requests processing
by reentrant routine Q.
Task A temporarily gives up control of reentrant routine Q before it completes processing.
Task B starts processing the same copy of reentrant routine Q.
Task B completes processing by reentrant routine Q.
Task A regains use of reentrant routine Q and resumes where it stopped.

REENTRANT

| TasK A |

ROUTINE Q

| Task B |
MR-3668

Figure 10-7

Sharing Control of a Routine

10.3.8.2 Writing Reentrant Code — In an operating system environment, when one task is executing
and is interrupted to allow another task to run, a context switch occurs in which the processor status
word and current contents of the general-purpose registers (GPRs) are saved and replaced by the appropriate values for the task being entered. Therefore, reentrant code should use the GPRs and the stack
for any counters, pointers, or data that must be modified or manipulated in the routine.

The context switch occurs whenever a new task is allowed to execute. It causes all of the GPRs, the PS,
and often other task-related information to be saved in an impure area. It then reloads these registers
and locations with the appropriate data for the task being entered. Notice that one consequence of this
is that a new stack pointer value is loaded into R6, thereby causing a new area to be used as the stack
when the second task is entered.

10-13

The following should be observed when writing reentrant code.

All data should be in or pointed to by one of the general-purpose registers.

A stack can be used for temporary storage of data or pointers to impure areas within the task

3.
4.

10.3.9

space. The pointer to such a stack would be stored in a GPR.

Parameter addresses should be used by indexing and indirect reference rather than by put-

ting them into instructions within the code.

When temporary storage is accessed within the program, it should be by indexed addresses,
which can be set by the calling task in order to handle any possible recursion.
Coroutines

In some programming situations it happens that several program segments or routines are highly interactive. Control is passed back and forth between the routines, each going through a period of suspension
before being resumed. Since the routines maintain a symmetric relationship with each other, they are
called coroutines.

Coroutines are two program sections, either subordinate to the call of the other. The nature of the call is
“I have processed all I can for now, so you can execute until you are ready to stop, then I will continue.” The coroutine call and return are identical, each being a jump to subroutine instruction with the
destination address being on top of the stack and the PC serving as the linkage register, as follows.
JSR PC,@(R6)+

10.3.9.1 Coroutine Calls — The coding of coroutine calls is made simple by the stack feature. Initially,
the entry address of the coroutine is placed on the stack, and from that point the
JSR PC,@*R6)+

instruction is used for both the call and the return statements. This JSR instruction results in an exchange of the contents of the PC and the top element of the stack; this permits the two routines to swap
control and resume operation where each was terminated by the previous swap. An example is shown in
Figure 10-8. Notice that the coroutine linkage cleans up the stack with each control transfer.

10.3.9.2

Coroutines Versus Subroutines — Coroutines can be compared to subroutines in the following

ways.

A subroutine can be considered to be subordinate to the main or calling routine, but a coroutine is considered to be on the same level, as each coroutine calls the other when it has com-

pleted current processing.

When called, a subroutine executes to the end of its code. When called again, the same code
will execute before returning. A coroutine executes from the point after the last call of the
other coroutine. Therefore, the same code will not be executed each time the coroutine is
called. An example is shown in Figure 10-9.

The call and return instructions for coroutines are the same:
JSR PC,@(SP)+

10-14

This one instruction also cleans up the stack with each call. The last coroutine call will leave
an address on the stack that must be popped if no further calls are to be made. Refer to
Paragraph 10.3.6.1 for information on the return from subroutine instruction.

Each coroutine call returns to the coroutine code at the point after the last exit with no need

for a specific entry point label, as would be required with subroutines.
ROUTINE A

STACK

ROUTINE B

COMMENTS
LOC IS PUSHED

ONTO THE STACK
TO PREPARE FOR

MOV #LOC,-(SP)
.

LOC

<SP

THE COROUTINE
CALL.
LOC:

<SP

PCO

JSR PC,@(SP)+

(PCO)

WHEN THE CAL'

IS EXECUTED,

THE PC FROM
ROUTINE A IS

PUSHED ON THE

STACK AND EXECUTION CONTINUES AT LOC.

JSR PC,@(SP)+

(PC1)

PC1

ROUTINE B CAN

RETURN CONTROL

TO ROUTINE A

BY ANOTHER
COROUTINE CALL.
PCO IS POPPED
FROM THE STACK

AND EXECUTION
RESUMES IN
ROUTINE A JUST
AFTER THE CALL
TO ROUTINE B,
I.E., AT PCO.
PC1 IS SAVED
ON THE STACK

FOR A LATER
RETURN TO
ROUTINE B.
MR-3669

Figure 10-8

COROUTINES

Coroutine Example

MAIN-PROGRAMS

SUBROUTINES

1ST LOC:

JSR PC,@ (SP)+

JSR Rn, LOC

‘

JSR PC,@ (SP)+

RTS
v

JSR PC,@ (SP)+

JSR Rn, LOC

Vv
JSR PC,@ (SP)+

v
MR-3670

Figure 10-9

Coroutines Versus Subroutines

10-15

10.3.9.3

Using Coroutines — Coroutines should be used in the following situations.

Whenever two tasks must be coordinated in their execution without obscuring the basic
structure of the program. For example, in decoding a line of assembly language code, the
results at any one position might indicate the next process to be entered. A detected label
must be processed. If no label is present, the operator must be located, etc.

To add clarity to the process being performed, to ease-in the debugging phase, etc.

An assembler must perform a lexicographic scan of each assembly language statement during pass 1 of

the assembly process. The various steps in such a scan should be separated from the main program flow

to add to the program’s clarity and to aid in debugging by isolating many details. Subroutines would not
be satisfactory here, as too much information would have to be passed to the subroutine each time it
was called. Such a subroutine would be too isolated. Coroutines could be effectively used here with one
routine being the assembly-pass-1 routine and the other extracting one item at a time from the current
input line. Figure 10-10 illustrates this example.

ROUTINE A

ROUTINE B

START AND SKIP

BLANKS
NONBLANK

READ NAME

PROCESS NAME

SKIP BLANKS

PROCESS MNEMONICS

READ MNEMONICS

READ ADDRESSES

LINE

SEMICOLON

TERMINATOR

SKIP COMMENT

END

MR-3671

Figure 10-10

Coroutine Path

10-16

Coroutines can be utilized in I/O processing. The example above shows coroutines used in double-buf-

fered 1/0 using IOX. The flow of events might be described as:
Write 01

concurrently,

Read I1
Process 12
then

Write 02

concurrently.

Read 12
Process 11

Figure 10-11 illustrates a coroutine swapping interaction.
ROUTINE #1 IS OPERATING, IT THEN
EXECUTES:

MOV #PC2,-(R6)
JSR PC,@(R6)+

WITH THE FOLLOWING RESULTS:
1.

PC2ISPOPPED FROM THE STACK

AND THE SP AUTOINCREMENTED.

SPIS AUTODECREMENTED AND

CONTROL IS TRANSFERRED TO THE

THE OLD PC (I.E., PC1) IS PUSHED.

LOCATION PC2 (I.E., ROUTINE #2).

SP—o

PC2

SP —

PC2

ROUTINE #2 IS OPERATING, IT THEN

EXECUTES:
|

JSR PC,@(R6)+

l
P —o

WITH THE RESULT THAT PC2 IS

PC2

EXCHANGED FOR PC1 ON THE
STACK AND CONTROL IS

TRANSFERRED BACK TO ROUTINE #1.
MR-3672

Figure 10-11

Coroutine Interaction

When routine #1 is operating; it executes:
MOV #PC2,— (R6)
JSR PC,@(R6)+

with the following results.

PC2 is popped from the stack and the SP autoincremented.

SP is autodecremented and the old PC (i.e., PC1) is pushed.

Control is tranferred to the location PC2 (i.e., routine 2).

When routine #2 is operating; it executes:
JSR PC,@(R6)+

with the result that PC2 is exchanged for PC1 on the stack and control is transferred back to routine 1.

10-17

10.3.10

Recursion

An interesting aspect of a stack facility, other than its providing for automatic handling of nested subroutines and interrupts, is that a program may call on itself as a subroutine just as it can call on any
other routine. Each new call causes the return linkage to be placed on the stack, which, as it 1s a lastin/first-out queue, sets up a natural unraveling to each routine just after the point of departure. Typical
flow for a recursive routine might resemble that shown in Figure 10-12.

MAIN PROGRAM

b
SUB 1

SUB 2

MR-3673

Figure 10-12

Recursive Routine Flow

The main program calls function 1, SUB 1, which calls function 2, SUB 2, which recurses once before
returning.

Example:

DNCEF:

BEQ 15

JSR R5,DNCF
1

.TO EXIT RECURSIVE LOOP
'RECURSE

RTS R5

.RETURN TO 18 FOR

'EACH CALL, THEN TO
'MAIN PROGRAM

The routine DNCEF calls itself until the variable tested becomes equal to 0, then it exits to 1§ where the
RTS instruction is executed, returning to the 1$ once for each recursive call and a final time to return
to the main program.

In general, recursion techniques will lead to slower programs than the corresponding interactive techniques, but recursion will produce shorter programs, and thus save memory space. Both the brevity and

clarity produced by recursion are important in assembly language programs.

Uses of Recursion — Recursion can be used in any routine in which the same process is required several
times. For example, a function to be integrated may contain another function to be integrated, as in
solving for XM, where

10-18

SM = 1 4+ F(X)
and

F(X) = G(X)

Another use for a recursive function could be in calculating a factorial function, because
FACT(N) = FACT(N — 1) * N

Recursion should terminate when N = 1.

The macroprocessor within MACRO-11, for example, is itself recursive since it can process nested
macrodefinitions and calls. For example, within a macrodefinition, other macros can be called. When a
macro call is encountered within definition, the processor must work recursively; that is, it must process
one macro before it is finished with another, then continue with the previous one. The stack is used for a
separate storage area for the variables associated with each call to the procedure.

As long as nested definitions of macros are available, it is possible for a macro to call itself. However,
unless conditionals are used to terminate this expansion, an infinite loop could be generated.
10.3.11

Processor Traps

Certain errors and programming conditions cause the KDF11-BA processor to enter the “service” state
and trap to a fixed location. A trap is an interrupt generated by software. Pending conditions are arbitrated according to a priority. The following list describes the priority from highest to lowest.
Condition

Description

Memory Management Violation* | A memory management violation causes an abort and traps to loca(MMUERR)

tion 250g.

Timeout Error* (BUSERR)

No response from a bus device during a bus transaction causes an

Parity Error* (PARERR)

A parity error signal received by the processor during a bus transac-

Trace (T) Bit*
Stack Overflow* (STKOVF)

abort and traps to location 4.

tion causes an abort and traps to location 114g.

If PS bit 4 is set at the end of instruction execution, the processor

traps to location 14g.

If the kernel stack pointer was pushed below 400g during an instruc-

tion execution, the processor traps to location 4g at the end of the
instruction.

Power Fail* (PFAIL)

If bus signal power OK (BPOKH) became negated during instruc-

tion execution, the processor traps to location 24g at the end of the
instruction.
(Continued)

*Nonmaskable software cannot inhibit the condition. CTLERR, MMUERR, BUSERR, PARERR are mutually exclusive
when the processor is executing a program.

10-19

Condition

Description

Interrupt Level 7(BIRQ7)
(Maskable by PS<<07:05>)
Interrupt Level 6 (BIRQO6)
(Maskable by PS<<07:05>)

[f device interrupt requests are asserted and PS<<07:05> are properly set, the processor at the end of the present instruction execution
will initiate an interrupt vector sequenced on the bus.

Interrupt Level 5 (BIRQ)Y)

PS<07:.05>

Levels Inhibited

(Maskable by PS<<07:05>)
Interrupt Level 4 (BIRQ4)
(Maskable by PS<<07:05>)

7
6

All
6,5, 4

Halt Line

5, 4

0-3

None

If the BHALT L bus signal is asserted during the service state, the

processor will enter ODT mode.

10.3.11.1

Trap Instructions — Trap instructions provide for calls to emulators, I/O monitors, debug-

ging packages, and user-defined interpreters. When a trap occurs, the contents of the current program

counter (PC) and program status word (PS) are pushed onto the processor stack and replaced by the
contents of a 2-word trap vector containing a new PC and new PS. The return sequence from a trap
involves executing an RTI or RTT instruction, which restores the old PC and old PS by popping them
from the stack. Trap vectors are located at permanently assigned fixed addresses.
The EMT (trap emulator) and TRAP instructions do not use the low-order byte of the word in their
machine language representation. This allows user information to be transferred in the low-order byte.
The new value of the PC loaded from the vector address of the TRAP or EMT instructions is typically
the starting address of a routine to access and interpret this information. Such a routine is called a trap
handler.

A trap handler must accomplish several tasks. It must save and restore all necessary GPRs, interpret
the low byte of the trap instruction and call the indicated routine, serve as an interface between the
calling program and this routine by handling any data that needs to be passed between them, and, finally, cause the return to the main routine.
A trap handler can be useful as a patching technique. Jumping out to a patch area is often difficult

because a 2-word jump must be performed. However, the 1-word TRAP instruction may be used to
dispatch to patch areas. A sufficient number of slots for patching should first be reserved in the dispatch table of the trap handler. The jump can then be accomplished by placing the address of the patch

area into the table and inserting the proper TRAP instruction where the patch is to be made.

10-20

10.3.11.2 Use of Macro Calls — The trap handler can be used in a program to dispatch execution to any
one of several routines. Macros may be defined to cause the proper expansion of a call to one of these
routines, as in the example below.

.MACRO SUB2 ARG
MOV ARG, RO
TRAP +1
.ENDM

When expanded, this macro sets up the one argument required by the routine in R0 and then causes the
trap instruction with the number 1 in the lower byte. The trap handler should be written so that it
recognizes a 1 as a call to SUB2. Notice that ARG here is being transmitted to SUB2 from the calling
program. It may be data required by the routine or it may be a pointer to a longer list of arguments.
In an operating system environment like RT-11, the EMT instruction is used to call system or monitor
routines from a user program. The monitor of an operating system necessarily contains coding for many
functions, such as I1/0, file manipulation, etc. This coding is made accessible to the program through a
series of macro calls that expand into EMT instructions with low bytes, indicating the desired routine or
group of routines to which the desired routine belongs. Often a GPR is designated to be used to pass an
identification code to further indicate to the trap handler which routine is desired. For example, the
macro expansion for a resume execution command in RT-11 is as follows.
MACRO .RSUM
CM3, 2.

.ENDM

CM3 is defined:
MACRO CM3 CHAN, CODE
MOV #CODE *400,R0
IIF NB
HAN,BISB CHAN,RO
EMT 374
.ENDM

Note that the EMT low byte is 374. This is interpreted by the EMT handler to indicate a group of
routines. Then the contents of RO (high byte) are tested by the handler to identify exactly which routine
within the group is being requested — in this case routine number 2. (The CM3 call of the .RSUM is set
‘

up to pass the identification code.)
10.3.12

Conversion Routines

Almost all assembly language programs require the translation of data or results from one form to another. Code that performs such a transformation is called a conversion routine in this guide. Several
commonly used conversion routines follow.

Almost all assembly language programs involve some type of conversion routine. Octal-to-ASCII, octalto-decimal, and decimal-to-ASCII are a few of the most widely used.

Arithmetic multiply and divide routines are fundamental to many conversion routines. Division is typically approched in one of two ways.

10-21

The division can be accomplished through a combination of rotates and subtractions.
Example:

Assume the following code and register data; to make the example easier, also assume a 3-bit
word.

DIV:
1$

MOV #3,—(SP)

;SET UP DIGIT COUNTER

CLR —(SP)
ASL (SP)
ASL R1

;CLEAR RESULT

ROL RO

CMP RO,R3
BLT 2§

SUB R3,R0
INC (SP)

;RO CONTAINS REMAINDER

DEC 2 (SP)
BNE §1

;DECREMENT COUNTER

; INCREMENT RESULT

Therefore, to divide 7 by 2:

remainder
7 (multiplicand)
2 (multiplier)

RO = 000
R1 =111
R3 =010

Chit =0
STACK
011

counter

000

quotient

Following through the coding, the quotient, remainder, and dividend all shift left, manipulating the most significant digit first, etc.
At the conclusion of the routine:
remainder

RO = 001
R1 = 000
R3 = 010

STACK
000

counter

011

quotient

‘

The second method of division works by repeated subtraction of the powers of the divisor,
keeping a count of the number of subtractions at each level.
Example:

To divide 22119 by 10, first try to subtract powers of 10 until a nonnegative value is obtained,
counting the number of subtractions of each power.
221

— 1000

10-22

Negative, so go to the next lower power, and count for 103 = 0.
221

— 100

121

count for 102 = 1

— 100
21

count = 2

— 100

Negative, so reduce power, and count for 102 = 2.
21

—10

count for 107 = 1.

—10

count = 2

—10

Negative, so count for 10! = 2.
No lower power, so remainder is 1.
Answer = 022, remainder 1.

Muluplication can be done with a combination of rotates and additions or with repetitive additions.
Example:

Assume the following code and a 3-bit word.
CLR RO
MOV #3,CNT

;HIGH HALF OF ANSWER

MOV R1,MULT;

;MULTIPLICAND

ROR R2
BCC NOW
ADD MULT,RO ;1F INDICATED,

NOW;

ROR RO

;SET UP COUNTER

ADD

;MULTIPLICAND
R04 R1

DEC CNT
BNE MORE
MULT:

CNT:

10-23

The following conditions exist for 6 times 3:
high-order half of result
multiplicand

= 000
RO
R1 =110
R3 = 011

multiplier

After the routine is executed:

high-order half of result
low-order half of result

RO = 010
R1 = 010
R2 = 100
CNT =0

MULT = 110
Example:

Multiplication of RO by 50g(101000).
MOV RO, —(SP)

MULS50:

ASL RO
ASL RO

ADD (SP)+,R0
ASL RO
ASL RO
ASL RO

RETURN

If RO contains 7:
RO =111

After execution:

RO = 100011000
(7 * 505 = 4303).

ASCII Conversions — The conversion of ASCII characters to the internal representation of a number, as
well as the conversion of an internal number to ASCII in 1/O operations, presents a challenge. The
following routine takes the 16-bit word in R1 and stores the corresponding six ASCII characters in the
buffer addressed by R2.
OUT:
LOOP:

MOV
MOV
BIC
ADD
MOYVB
ASR
ASR
ASR
DEC
BNE
BIC
ADD
MOYVB
RTS

#5 RO

‘LOOP COUNT

#0,@SP

:ONE OCTAL VALUE
:CONVERT TO ASCII
-:STORE IN BUFFER

SHIFT

‘RIGHT
‘THREE
‘TEST IF DONE

:COPY WORD INTO STACK

R1,—(SP)
4177770,@SP

(SP)+,—(R2)
R1
RO

‘NO, DO IT AGAIN
‘GET LAST BIT
:CONVERT TO ASCII
:STORE IN BUFFER
‘DONE,RETURN

LOOP
4177776,R1
40 R1
R5,—(R2)
PC

10-24

10.4

PROGRAMMING THE PROCESSOR STATUS WORD

The current processor status can be read and written using several programming techniques on the PS.

The PS has an I/O address of 17777776. The KDF11-BA and other PDP-11 processors implement this
address, whereas LSI-11 and LSI-11/2 processors do not. One technique is to use the

1/O address as a

source or destination address with any instruction.

CLR @#17777776
MOV @#17777776, RO
The first instruction clears the PS and the second instruction moves the contents of the PS to general
register RO.

The PS explicit address (17777776) can be accessed on a word or byte basis. The KDF11-BA will rec-

ognize the PS odd address (17777777) and the access result will be identical to an odd memory address

reference.
Another technique is to use the two dedicated PS instructions, MTPS and MFPS. These instructions
only reference the even byte. If memory management is enabled certain PS bits are protected. Refer to

Paragraph 8.5.3.2 for more details.
10.5

PROGRAMMING PERIPHERALS

Programming LSI-11 bus-compatible modules (devices) is simple. A special class of instructions that

deal with input/output operations is unnecessary. The bus structure permits a unified addressing structure in which control, status, and data registers for devices are directly addressed as memory locations.
Therefore, all operations on these registers, such as tranferring information into or out of them or ma-

nipulating data within them, are performed by normal memory reference instructions.
The use of all memory reference instructions on device registers greatly increases the flexibility of in-

put/output programming. For example, information in a device register can be compared directly with
a value and a branch made on the result.
CMP RBUF,

4101

BEQ SERVICE
In this case, the program looks for 101 in the DLVI1I receiver data buffer register (RBUF) and
branches if it finds it. There is no need to transfer the information into an intermediate register for
comparison.

When the character is of interest, a memory reference instruction can transfer the character into a user
buffer in memory or to another peripheral device. The instruction:

MOV DRINBUF LOC
transfers a character from the DRV11 data input buffer (DRINBUF) into a user-defined location.

All arithmetic operations can be performed on a peripheral device register. For example, the instruction

ADD #10, DROUT BUF will add 10 to the DRV11’s output buffer. All read/write device registers can
be treated as accumulators. There is no need to funnel all data transfers, arithmetic operations, and
comparisons through one or a small number of accumulator registers.

10-25

10.6

PDP-11 PROGRAMMING EXAMPLES

The programming examples on the following pages show how the instruction set, the addressing modes,
and the programming techniques can be used to solve some simple problems. The format used is either
PAL-11 or MACRO-11.

Program

Address

Contents

Label

Op Code Operand

Comments

EXAMPLE

; PROGRAMMING

: SUBTRACT CONTENTS OF LOCS 700-710
; FROM CONTENTS OF LOCS

R0=%0

000000
000001

R1-%1

000002
000003

R2=%2
R3=%3
R4=%4

000004

R5=%5
SP=%6

000005

000006
000007

PC=%7

.=500

000500

; INIT STACK POINTER

MOV

#.,SP

012701
000700

MOV

#700,R1

012702

MOV

#712,R2

000500

012706

000504
000510

000500

START:

000712
000514

012703
001000

MOV

#1000,R3

000520

012704

MOV

#1012 ,R4

000524

005000

CLR

000526
000430

005005
062105

CLR

RO
R5

000532
000534

020102

000536
000540
000542

062300

020304
001375

000544

160500

000546

000000

000700
000702

001012

SUM1:

ADD

CMP
BNE

001375
SUM2:

ADD

(R3)+,RO

s FINISHED ADDING?
; IF NOT BRANCH BACK

SUB

R5,R0

; SUBTRACT RESULTS
; THAT'S

HALT

=700

000001

WORD

1,2,3,4,5

000002

000003
000004

000710

000005
001000

=1000

001000

000004

WORD

001002

000005

001004

000006

001006

000007

001010

000010

000500

; START ADDING

BNE

000700

000704
000706

; START ADDING

s FINISHED ADDING?
; IF NOT BRANCH BACK

R3,R4
SUM2

CMP

DIFF:

(R1)+,R5

R1,R2
SUM1

4,5,6,7,8

END

10-26

ALL

FOLKS

1000-1010

Program

Address

Contents

Label

Code

Operand

Comments
; PROGRAM
;IN

;20.

COUNT

NEGATIVE

NUMBERS

TABLE

SIGNED

WORDS

;BEGINNING

; COUNT

MANY

HOW

LOC

VALUES

ARE

NEGATIVE

R0=%0
R1=%1

R2=%2

SP=%6
PC=%7
.=500
START:

MOV#.,SP

; SET

STACK

#VALUE,R1

; SET

POINTER

MOV #VALUES+40.,R2
CLR RO

; SET

COUNTER

MOV

TST

CHECK:
BPL

INC

(R1)+

; TEST

NUMBER

; POSITIVE?
;NO,

INCREMENT

; COUNTER

CMP

BNE

FINISHED?

;YES,

R1,R2

;NO,

CHECK

;YES,

HALT

BACK

STOP

VALUES:

; PROGRAM

COUNT

ABOVE

;LIST

16.

QUIZ

SCORES

LOC

SCORES

; BEGINNING

s KNOWN

AVERAGE

; COUNT

LOC

SCORES

AVERAGE

ABOVE

R0O=30

R1=%1
R2=%2
R3=%3

SP=%6
PC=%7
.=500
START:

CHECK:

NO:

MOV

#.,SP

; SET

STACK

MOV
MOV
MOV

#16.,R1
#SCORES,R2
#AVERAGE,R3

; SET

COUNTER

; SET

POINTER

CLR

CMP

(R2)+, (R3)

; COMPARE

BLE

; LESS

; TO

AVERAGE?

INC

; NO,

COUNT

DEC

; YES;

BNE

CHECK

; FINISHED?
;YES,

HALT
AVERAGE:

SCORES*

SCORE

THAN

NO,

STOP

25.,70.,100.,60.,80.,80.,40.

55.,75.,100.,65.,90.,70.,65.,70.

10-27

AVERAGE

EQUAL

DECREMENT

65.

- END

AND

COUNTER

CHECK

QUIZ

AVERAGE

SCORES

Program

Address

Contents

Label

Op Code Operand

Comments

EXAMPLE

; PROGRAMMING

; ACCEPT
; STORE

(IMMEDIATE ECHO)
CHARS

20.

AND

; FROM THE KEYBOARD, OUTPUT CR & LF
:ECHO ENTIRE STRING FROM STORAGE
R0O=%0
R1=%1

SP=%6
CR=15

LF=12

TKS=177560

TKB=TKS+2
TPS=TKB+2
TPB=TPS+2
.TITLE

ECHO

MOV

.=1000
#,,SP
MOV
#SAVE+2,R0

; SA

MOV

#20.,R1

; CHARACTER

IN:

TSTB

@#TKS

BPL

ECHO:

TSTB

@Q#TPS

BPL

ECHO

MOVB

@#TKB,@#TPB

START:

;sINITIALIZE

COUNT

WAIT

TELEPRINTER

;CHECK
; READY
; ECHO

STATUS

CHARACTER

; STORE CHARACTER AWAY

MOVB

@#TKB, (RO) +

DEC

BNE

s FINISHED

MOV

RO
#SAVE,

;:SA OF BUFFER

MOV

#22.,R1

: COUNTER OF BUFFER
; INCLUDING CR & LF

TSTB

@#TPS

; CHECK TELEPRINTER

BPL

OuT

MOVB
DEC

BNE

OuT

;:CR

.BYTE

; OUTPUT

(RO)+,@#TPB

CR,LF

- END

10-28

INCLUDING

STATUS

CHARACTER

; FINISHED

.=.+20,

INPUTTING?

; READY

HALT

SAVE :

POINTER

; CHAR IN BUFFER?
; IF NOT BRANCH BACK
; AND

OUT:

STACK

BUFFER
; BEYOND CR & LF
OF

OUTPUTTING?

Program

Address

Contents

Label

Code

Operand

Comments
; PROGRAMMING
; SUBROUTINE

INPUT:

MOV

#BUFFER,RO

; SET

MOV

#-10.,R1

; SET

@#TKS

; TEST

KYBD

; TEST

TTO

CHARACTER

; STORAGE
IN:

TSTB
BPL

OUT:

TSTB

Q@#TPS

MOVB

@#TKB,Q@#TPB

; ECHO

@#TKB, (RO)+

; STORE

INC

BNE

RTS

BUFFER

READY
READY

; INC

SORT:

MOV

#-10.,R4

MOV

COUNT,R3

#BUFFER+9.,R0

ADD

R3,R0

MOVB

(RO)+,R1

CMPB

(RO)+,R1

LT:

MOVB

- (RO) ,R2

MOVB

R1, (RO)+

CHARACTER

EXAMPLE

SORT

TEN

MOV

R2,R1

INC

BNE

LOOP

INSERT:

MOVB

R1,BUFFER+10.
(R4)
R4

INC

COUNT

BNE

MOV

#-9.,COUNT

; RESTORE

RTS

; EXIT

LOCATION

COUNT

.WORD -9.
.ASCII/INPUT ANY TEN SINGLE-DIGIT VALUES
.ASCII/SORT AND OUTPUT THEM IN/
.ASCII/SMALLEST TO LARGEST ORDER./
.=.+10.
.END

VALUES

GT:

LINE2:

STATUS

;s EXIT

MOV

LOOP:

BUFFER:

STATUS

COUNTER

; PROGRAMMING

LINE1l:

VALUES

COUNTER

s SUBROUTINE

INC

TEN

OUT

MOVB

BGE

INPUT

BPL

COUNT:

EXAMPLE
TO

INITSP

; FINISHED!
!!

10-29

(0-9);

I'LL/

Program

Address

Contents

Label

Op Code Operand

Comments
; PROGRAMMING EXAMPLE
; SUBROUTINE EXAMPLE
; INPUT TEN VALUES, SORT,

AND

;OUTPUT THEM IN SMALLEST TO LARGEST ORDER

RO=%0
R1=%1

R2=%2

R3=%3
R4=%4
R5=%5

SP=%6
PC=%7

TKS=177560

(address of terminal control status register)
TKB=TKS+2 - (terminal data buffer register)
TPS=TKB+2

(terminal

and

output control

TPB=TPS+2 -

status

registers)

(terminal output data buffer)

.=3000
INITSP:

MOV #.,SP
JSR PC,CRLF
JSR R5, OUTPUT
LINE1
69.

JSR PC,CRLF
JSR R5,0UTPUT
LINE2
26 .
JSR PC,CRLF
JSR PC,INPUT

;INITIALIZE STACK POINTER
:GO TO CRLF SUBROUTINE
:GOT TO OUTPUT SUBROUTINE
:SA OF LINE 1 BUFFER
;NUMBER OF OUTPUTS
;GO TO CRLF SUBROUTINE
:GO TO OUTPUT SUBROUTINE
:SA OF LINE 2 BUFFER
;NUMBER OF OUTPUTS

:GO
:GO
GO
:GO

JSR PC,SORT
JSR PC,CRLF

TO
TO
TO
TO

CRLF SUBROUTINE
INPUT SUBROUTINE
SORT SUBROUTINE
CRLF SUBROUTINE

JSR R5,0UTPUT

:GO TO OUTPUT SUBROUTINE

10.

;NUMBER OF OUTPUTS

: INPUT BUFFER AREA

BUFFER

JSR

PC,CRLF

s THE

HALT

END!!!

; PROGRAMMING

; SUBROUTINE
CRLF:

TSTB
BPL

LNFD:

@4#TPS

: TEST

OUTPUT

READY

STATUS

CRLF

MOVB - #15,@#TPB
TSTB @#TPS
BPL

TTO

EXAMPLE

:OUTPUT CARRIAGE RETURN
; TEST TTO READY STATUS

LNFD

MOVB #12,@#TPB
RTS PC

;OUTPUT

LINE

FEED

;EXIT

; SUBROUTINE

s VARIABLE

OUTPUT

LENGTH

MESSAGE

OUTPUT:

MOV (R5)+,RO
MOV (R5)+,R1
NEG R1

:PICK UP SA OF DATA BLOCK
:PICK UP NUMBER OF OUTPUTS
:NEGATE IT

AGAIN:

TSTB

:TEST

BPL

MOVB

@#TPS

TTO

READY

STATUS

AGAIN

(RO)+,@#TPB

INC

BNE

AGAIN

RTS

;OUTPUT
:BUMP

10-30

CHARACTER

COUNTER

LOOPING TECHNIQUES

10.7

Looping techniques are illustrated in the program segments below. The segments are used to clear a 50word table.
1.

Autoincrement (pointer address in GPR)
RO = %0
MOV #TBL,RO
CLR (RO)+
CMP RO,#TBL+100.
BNE LOOP

LOOP:

Autodecrement (pointer and limit values in GPR)
RO=%0
R1=%1
MOV #TBL,R0
MOV #TBL+ 100.,R1
CLR - (R1)
CMP R1,R0
BNE LOOP

LOOP:

Counter (decrementing a GPR containing count)
RO=%0
R1=%1
MOV #TBL,R0
MOV #50.,.R1
CLR (RO)+
DEC R1
BNE LOOP

LOOP:

Index Register Modification (indexed mode; modifying index value)
RO=%0
CLR RO
CLR TBL (RO)
ADD #2,R0
CMP RO,#100.
BNE LOOP

LOOP:

Faster Index Register Modification (storing values in GPR)
RO=%0
R1=%1
R2=%2
MOV #2,R1
MOV #100.,R2
CLR RO
CLR TBL (R0)
ADD R1,R0
CMP RO,R2
BNE LOOP

LOOP:

10-31

Address Modification (indexed mode; modifying base address)
RO=%0
MOV #TBL,RO

CLR 0(RO)

LOOP:

+2
ADD#2,LOOP
CMP LOOP+2,#100.
BNE LOOP

10-32

CHAPTER 11
BOOTSTRAP AND DIAGNOSTIC LOGIC

11.1
INTRODUCTION
The bootstrap and diagnostic logic features three hardware registers and two ROM sockets for 2K, 4K
or 8K of 16-bit read-only memory. This 16-bit read-only memory typically contains diagnostic programs
and a selection of bootstrap programs. These programs are user-selectable by setting eight switches on a

16-pin DIP switch pack (E102). Programming the bootstrap and diagnostic logic consists of setting the
switches for the programs desired and the supplying of inputs by the console operator. The bootstrap/diagnostic switch configurations and console operator responses are described in Chapter 2, Paragraph 2.2.4.1. The diagnostic programs test the processor, the memory and the user’s console.
The KDF11-BA includes two BDV11-compatible 2K X 8 ROMs that are installed in ROM sockets

E126 (low byte) and E127 (high byte). The BDV programs include both CPU and memory diagnostics
as well as bootstrap programs for loading memory from a variety of LSI-11-compatible peripherals.
Paragraphs 2.2.4.1 and 11.4 present specific information on the operation of the BDV ROM programs.
Alternatively, users may install ROMs or EPROMSs containing programs of their choice in the ROM

sockets. In such case the features of the BDV ROM programs would no longer be applicable unless
specifically included in the new ROMs.
11.2 BOOTSTRAP AND DIAGNOSTIC REGISTERS
The bootstrap and diagnostic logic contains three hardware regisiers that are software-addressable.
(One of the registers is a dual-purpose, functioning as the configuration register when read and the
display register when written.) These registers are assigned individual addresses that cannot be changed
or modified. The designations and addresses of these registers are listed in Table 11-1. The registers and
associated logic are described in the following paragraphs.

These three registers, along with the line clock register and the ROM addresses, can be disabled by
inserting a jumper from J10 to J15.
Table 11-1

Read/
Write

Bit
Size

Address

Page Control

17777520

Read/Write

R/W

17777522

Configuration®

17777524

Display*

17777524

Maintenance

*Dual-purpose register.

11.2.1

Page Control Register (PCR) — Address: 17777520

The page control register (PCR) is a write-only register that is both word- and byte-addressable. Only
bits <13:8> and <5:0> can be loaded. Whenever the KDF11-BA read-only memory is accessed, either the PCR high byte (bits <13:8>) or the PCR low byte (bits <<5:0>) is used for the six most
significant bits of the ROM address.

The read-only memory is accessed by bus addresses 17773000 through 17773777. The eight least significant bits (bits <<7:0>) of the bus address become the low-order bits of the ROM address. If bus address bit 8 is zero (17773000-17773377), PCR bits <5:0> become the six most significant bits of the
ROM address. If bus address bit 8 is one (17773400-17773777), PCR bits <<13:8> become the six
most significant bits of the ROM address. The format for the page control register is shown in Figure
11-1. This register is cleared by power-up and when the system is rebooted.
15

/////

PCR HB
Y

///%

]

PCR LB

SELECTS ROM ADDRESS
IN 17773000-17773377

SELECTS ROM ADDRESS
IN 17773400-17773777 RANGE

MR-7109

Figure 11-1

11.2.2

Page Control Register Format

Read/Write Maintenance Register (R/W) — Address: 17777522

The read /write maintenance register (R/W) is a 16-bit read/write register that is both word- and byteaddressable. It is used by the ROM diagnostics to test various read/write functions before accessing
main memory. This register is cleared by power-up and by system reset.
11.2.3

Configuration and Display Register (CDR) — Address: 17777524

The configuration and display register (CDR) is actually made up of two independent registers that
share the same address. The read-only configuration register is accessed when the CDR is read. The
write-only display register is loaded by a write transfer to the CDR.

Configuration register bits <<15:8> always read as zero; bits <<7:0> reflect the status of eight switches on the KDF11-BA module at location E102. The interpretation of these switches is determined by
the ROM boot and diagnostic programs. Diagnostic/bootstrap program selection for the KDF11-BA is
described in Tables 2-7 and 2-8.

Display register bits <3:0> allow for program control of a diagnostic LED display on the KDF11-BA

module. Writing a 0 into one of these bits lights its corresponding LED. Writing a 1 into one of these
bits turns its corresponding LED off. Display register bits <<15:4> are not used. The display register is
cleared (and the four LEDs are lit) by power-up or system restart.

11.3

KDF11-BA ROM MEMORY (ADDRESSES: 17773000-17773777)

The KDF11-BA boot and Diagnostic option has two ROM sockets for either 2K, 4K, or 8K of 16-bit
read-only memory.

Addressing ROM Memory

The KDF11-BA ROM memory responds to bus addresses 17773000-17773777. The eight least significant bits of the bus address (bits <<7:0>) become the low byte of the ROM address. If bus address bit
8 is zero (17773000-17773377), the PCR bits <5:0> become the six most significant bits of the 14-bit
ROM address. If bus address bit 8 is one (17773400-17773777), PCR bits <<13:8> become the six
most significant bits of the ROM address.

11-2

The KDF11-BA includes a pair of 2K X 8 ROMs that only require a 12-bit ROM address. The two
most significant ROM address bits (PCR bits <<13:12> or <<5:4>) must be zero. Figures 11-2 and 113 show the formation of the ROM address by the PCR LO byte and the PCR HI byte, respectively.
FIXED ADDRESS 17773
_A

—

VARIABLE 000-377
A

21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 0504 03 02 01 0O
T

PROGRAM

ADDRESS

VARIABLE <07:00>
\.

)

10
A

111

1
i

]

—

}

SELECTS PCR
LOW BYTE
WHEN 0"
0504
03 02 01 00
T

PCR LB <05:00>

PCR LO BYTE|

ROM ADDRESS
MR-7110

ROM Address Format Using PCR LO Byte

Figure 11-2

FIXED ADDRESS 17773

VARIABLE 400-777

(.
21 20 19 18 17 16 15 14 13 12 11
T

PROGRAM

ADDRESS

]

SELECTS PCR
HIGH BYTE
WHEN ‘1"
13 12

[

VARIABLE <07:00>

N
~
10 09 08 07 06 0504 03 02 01 0O

]

’

10 09 08
T

PCR HI BYTE | PCR HB <13:08>
A

—

13 12 11

L
J

10 09 08 07 06 0504 03 02 01

ROM ADDRESS

MR7111

Figure 11-3

ROM Address Format Using PCR HI Byte

11.4 KDF11-BA BOOTSTRAP AND DIAGNOSTIC ROM FUNCTIONALITY
The KDF11-BA ROM programs include both CPU and memory diagnostics as well as bootstrap programs for loading memory from a variety of LSI-11-compatible perpherals. Paragraph 2.2.4.1 describes
the use of the configuration register switches in selecting the diagnostic and bootstrap programs. The
LED displays and error halts used by the ROM programs are described below.
11.4.1

KDF11-BA LED Display

The KDF11-BA ROM programs use the four red LEDs to indicate which programs and program segments are running. If the program performs an error halt or if it hangs up waiting for data from a
peripheral device, these LEDs serve as an error indication.

11-3

The four red LEDs present an octal number from O (all LEDs off) to 17 (all LEDs on). The most
significant LED is separated from the other three LEDs by the green power-on LED. An octal code of
0 indicates that the diagnostics and bootstrap programs have been successfully executed. Codes 1 and 2
are lit during the CPU and memory tests, respectively. Codes 3 and 4 are lit when the ROM programs
are typing a message on the console device or waiting for a console input, respectively. Codes 5-12 are
lit during various phases of the bootstrap routines. (Code 12 indicates a ROM bootstrap error and
should never occur on the KDF11-BA which, unlike the BDV11, does not have sockets for additional
ROM boot code.) If the memory diagnostic is disabled, the ROM code still verifies the existence of
memory locations 0—6, indicating an error with LED code 13. Code 17 indicates that the ROM programs are unable to begin running, either because the halt switch is on, or because of a hardware failure. Table 11-2 lists the errors indicated by their corresponding LED display pattern.
Table 11-2

KDF11-BA LED Display

Display

MSD

(Octal)

Bit 3

Bit 2

LSD

Bit 1

Bit 0

Type of Error

Off

CPU test error.

Off

Memory test error.

Off

Waiting for console terminal transmitter

Off

Load device status error.

06
07

Off
Off

On
On

Off
On

Bootstrap code incorrect;
DECnet waiting for response from host.

Off

DECnet waiting for message completion.

Off

DECnet processing received message.

Off

ROM bootstrap error (not used on KDF11-BA).

Off

Special memory test failure on locations 0--6.

NOTE

READY flag.

Waiting for console terminal receiver DONE

flag.

(Can occur when memory test is disabled.)

System hung, halt switch on, or not power-up

mode 2.

The errors indicated above are valid only if the KDF11-BA BDV ROMs (part numbers 23-339E2-00 and 23-340E2-00) are
installed in ROM sockets E126 (low byte) and E127 (high byte).

11.4.2

KDF11-BA Error Halts

A failure in a diagnostic test or bootstrap program causes the error to be indicated by the display and
an error halt instruction is carried out by the processor. When entering the halt mode, the processor
outputs on the console terminal the PC address at the time of the error. The actual error address is one
word less than the terminal printout. In halt mode, the processor responds to the console ODT commands and allows the operator to troubleshoot the error. Table 11-3 lists the error halts that can result
when the KDF11-BA ROM diagnostics and boostrap programs detect an error condition.
Table 11-3
Address

Display

List of Error Halts

of Error*

(Octal)

Cause of Error

173036

CP1ERR, RO contains address of error.

173040

SLU switch selection incorrect; error in switches.

173046

SLU error; CSR address for selected device in error. Check CSR for selected

173200

ROM loader error; checksum on data block.

173232

Memory error 2; write address into itself.

device in floating CSR address area.

Test 0—30K words with MMU off if present.
R1 = Address in error and expected data
R5 = Failing data

173236

CP4ERR, RO points to cause of error.

173240

CP3ERR, RO contains address of error.

173262

Memory error 3; odd parity pattern (072527) using byte addressing. Failure

in this test usually will indicate problem in byte logic.
Test 0-30K words with MMU off if present.
R1 = Failing address
R4 = Expected data
RS5 = Failing data

173302

Memory error in prememory data test for locations 000-776.
R2 = Failing data
R3 = Expected data

R5 = Failing address (000-776)

173316

Memory error; bit 15 set in one of the parity CSRs (772100-772136). Failing

memory should have parity error light on.
R4 = Address of failing CSR

(Contents of failing CSR identifies which 1K-word bank of memory caused

error.)
*Contents of R7 after halt.

Table 11-3

List of Error Halts (Cont)

Address

Display

of Error*

(Octal)

Cause of Error

173364

ROM loader error; checksum on address block.

173376

ROM loader error; jump address is odd.

173526

RLO1/RLO2 device error.

173652

RKO05 device error.

173654

Switch mode halt; match was not made with switches.

173660

Memory error in 0000-2044K words of the 22-bit memory test. This is a com-

mon error halt for six different tests.

If R3 = 0, there is an error in test 1-5; R4 determines failing test.
R4 = Expected data
R5 = Failing data
Contents
of R4

Test
No.

Test Description

2000027776
177777
000000
072527
125125

1
2
3
4
5

Address test bits 11-0
Data test
Data test
Odd parity pattern test
Byte addressing test

| For tests 1-5 (R3 = 0), determine 22-bit failing address as follows:
R1 bits 11-00 = failing address bits 11-00
R2 bits 15-06 = failing address bits 21-12
Example:

R2 = 123400 R1 = 027776
R2 = 1234XX R1 = XX7776

Ignore the upper two octal digits of R1 and the lower two octal digits of R2.
Failing 22-bit address = 12347776
Errors in address uniqueness test.
Test checks address bits 21-06. Test 6.
If R3 is not equal to 0, an error is in this test.
R4 = Expected data
R5 = Failing data
R2 = 22-bit failing physical address bits 21-06.
Failing address bits 05-00 are always 0.
*Contents of R7 after halt.

11-6

Table 11-3

Address

of Error*

Display

(Octal)

List of Error Halts (Cont)

Cause of Error
Example:
R2 = 024566

Failing address = 02456600
173664

Memory error in prememory address test for locations 000—776.

R2 = Failing data
R5 = Failing address and expected data
173670

Error CPU Test 9; JSR R3 failed.

173700

Error CPU Test 9; JSR PC failed.

173704

RX01/RX02 device error.

173714

A NO typed in console terminal test.

173736

Memory error 1; data test failed.
Test 0-30K words with MMU off if present.

R1 = Failing address
R4 = Expected data (either O or 177777)

R5 = Failing data

173740

Error CPU Test 9; RTS return failed.

173742

03/04

Console terminal test; no DONE flag.

173760

TUS8 error halt.

*Contents of R7 after halt.

11-7

CHAPTER 12

LINE FREQUENCY CLOCK

12.1

INTRODUCTION

The line clock logic generates bus request level 6 interrupts to the processor at time intervals determined by the BEVENT L signal. The BEVENT L signal is obtained from the power supply via module
pin BRI at 16 2/3 ms or 20 ms intervals, depending on the line frequency source (60 Hz or 50 Hz,
respectively). The line clock logic is shown in Figure 5-11.

Recognition of the BEVENT L signal is typically enabled and disabled under program control using bit
6 of the line clock status register (LKS). When the line clock register is disabled, or if clock interrupts
are to be always enabled, recognition of BEVENT L is held enabled by inserting the jumper from J10
to J11.

LINE CLOCK STATUS REGISTER (LKS) (ADDRESS: 17777546)

12.2

The line clock status register (LKS) contains the read/write line clock interrupt enable bit (6), which
enables and disables recognition of the BEVENT L line. The remaining bits are not used and always
read as zero.

Program recognition of this register, along with the boot and diagnostic registers and ROM memory,
can be disabled by inserting a jumper from J10 to J15 on the KDF11-BA module. The line clock status

Bit

Mnemonic | Meaning and Operation

15:07

Unused.

LCIE

05:00
12.3

Line Clock Status Register Bit Assignment

Line Clock Interrupt Enable — When set, this read /write bit allows the LSI-11
BEVENT line to initiate program interrupt requests. When this bit is clear,
line clock interrupts are disabled. LCIE is cleared by power-up and BINIT.
LCIE is held set when the LTC ENJ L (J10 to J11) jumper is installed.
Unused.

LINE CLOCK OPERATION

When the line clock interrupt bit is set (either under program control or by a jumper from J10 to J11),
assertion of BEVENT L generates an interrupt request at level 6. If the current processor priority is 6
or 7, the processor ignores this request. If the priority is 5 or less, the processor traps to a service routine
via vector address 100. Memory location 100 must contain the starting address of the service routine;
location 102 contains the new processor status word.
Interrupt vector address:
Priority level:

100
6

12-1

CHAPTER 13

SERIAL-LINE UNITS

13.1

INTRODUCTION

The two full-duplex asynchronous serial-line units (console serial-line unit and the second serial-line
unit) provide the KDF11-BA with an EIA interface that is compatible with RS-232-C and RS-423. The
serial-line baud rates are determined by a clock signal from an internal baud rate generator or an external clock signal via connectors J1 and J2. Jumpers are provided to select either the internal clock or the
external clock. If the internal clock is jumper-selected, the serial-line baud rates are switch-selectable
from 50 to 19.2K baud. The console serial line and the second serial line may operate at different baud
rates, but each serial line will transmit and receive data at the same selected rate. The serial lines provide error indicator bits for overrun error, framing error, and parity error.

The console serial-line unit may be configured to respond to a break signal received from the console
terminal. Both serial lines interrupt the processor at bus interrupt priority request level 4 (BR4).
The character format for each of the serial-line units is selected by wirewrap jumpers. The format may
consist of seven or eight data bits, one or two stop bits, parity or no parity, and even or odd parity. The
wirewrap jumper configuration and baud rate switch configuration for the serial lines are described in
Chapter 2.

The console serial-line unit is connected to the console terminal via connector J1. The second serial-line
unit is connected to a line printer, the TU58 cassette tape, or an additional terminal via connector J2. A
block diagram of the serial-line units is shown in Figure 5-12.

13.2

SERIAL-LINE UNIT REGISTERS

The program communicates with and transfers data to and from the external peripheral devices via four
registers associated with each serial line. Two of the registers (RCSR and TCSR) contain control /status information for receiver and transmitter operation. The other two registers (RBUF and
TBUF) contain data received from and data to be transmitted to the peripheral device. The addresses
assigned to the console and second serial-line registers are listed in Table 13-1.
Register Bit Assignments

The console and second serial-line registers have the same bit assignments with the exception of bit O of
the TCSR. Bit 0 is used as a transmit break bit (TX BRK) in the second serial-line register (TCSR2)
and it is unused in the console serial-line register (TCSR1).

The bit formats for the registers are shown in Figure 13-1. The register bit assignments are described in
Tables 13-2 through 13-5.

13-1

Table 13-1

Serial-Line Register Addresses

Console Line
Register

Address*

Second Serial Line
Register

RCSRI1

17777560

RCSR2

17776500%**

17776540%**

RBUF1

17777562

RBUF2

17776502

17776542

TCSRI1

17777564

TCSR2

17776504

17776544

TBUF1

17777566

TBUF2

17776506

17776546

Address

*DL1 DISJ L (J14) must be ungrounded.
**DL2 DISJ L (J13) and DL2 ADRJ L (J12) must be ungrounded.
***DL2 DISJ L (J13) must be ungrounded and DL2 ADRJ L (J12) must be grounded.

]

11
¥

]

" —

RCSRLO

—

OlO

O
J

NOT USED

RECEIVER DONE (READ ONLY)
RECEIVER INTERRUPT ENABLE (READ/WRITE)

156

RBUF [

10
T

, 0

09
T

{

08
T

0 ]

NOT USED

RECEIVE DATA

£RROR

(7,8 BIT DATA IS RIGHT-JUSTIFIED)

(READ ONLY)

IF BIT O7 UNUSED =7 DATA BITS

OVERRUN ERROR

PARITY ERROR (READ ONLY)

(READ ONLY)

TCSR

FRAMING ERROR (READ ONLY)

14
¥

13
|§

12
¥

11
L}

10
L

09
1

08
¥

0 l

l 0
—

04
A

03
L

02
1

01
T

]

NOT USED

O l

NOT USED

TRANSMIT READY (READ ONLY)
TRANSMIT INTERRUPT ENABLE (READ/WRITE)
TRANSMIT BREAK (READ/WRITE)

TRANSMIT BREAK BIT OIS USED ONLY IN TCSR2. IT ISNOT USED IN TCSR1.

14
Y

TBUF

O
[l

13
!
A

12
U

O
A

11
T
Il

09
T

O
Il

08
1

0O
I

06
¥

O
|

]

—Y

NOT USED

TRANSMIT DATA

(7,8 BIT IS RIGHT-JUSTIFIED) ON

(WRITE ONLY). ON READ =0
MR-5892

Figure 13-1

Serial-Line Register Formats

13-2

Table 13-2

Bits

Mnemonic

15-08
07

RCSR1 and RCSR2 Bit Assignments

Description
Unused. Read as zeros.

RX DONE | Receiver Done. This read-only bit is set when an entire character has been

received and is ready to be read from the RBUF Register. This bit is automatically cleared when RBUF is read. It is also cleared by power-up and
BUS INIT.

RX IE

Receiver Interrupt Enable. This read /write bit is cleared by power-up and

BUS INIT. If both RCVR DONE and RCVR INT ENB are set, a program
interrupt is requested.
05-00

Unused. Read as zeros.

Table 13-3
Bits

Mnemonic

ERR

RBUF1 and RBUF2 Bit Assignments

Description
Error. This read-only bit is set if any RBUF bit (14—-12) is set. ERR is clear

if all RBUF bits (14-12) are clear. This bit cannot generate a program interrupt.

OVR ERR | Overrun Error. This read-only bit is set if a previously received character

was not read before being overwritten by the present character.
13

FRM ERR | Framing error. This read-only bit is set if the present character had no valid

stop bit. Also used to detect a break condition.
12

PAR ERR

Parity Error. This read-only bit is set if received parity does not agree with

expected parity. Always O if no parity is selected.

NOTE
Error conditions remain in effect until the next character is received, at
which point, the error bits are updated. The error bits are cleared by powerup and BUS INIT.
11-08

Unused. Read as zeros.

07-00

Received Data Bits. These read-only bits contained the last received charac-

ter. If less than eight bits are selected, the character will be right-justified
with the most significant bit(s) reading zero.

13-3

Table 13-4
Bits

Description

Mnemonic

Unused. Read as zeros.

15-08

TCSR1 and TCSR2 Bit Assignments

Transmitter Ready. This read-only bit is cleared when TBUF is loaded and

TX RDY

is set when TBUF can receive another character. XMT RDY is set by power-up and by BUS INIT.

Transmitter Interrupt Enable. This read/write bit is cleared by power-up

TX IE

and BUS INIT. If both XMT RDY and XMT INT ENB are set, a program

interrupt is requested.

Unused. Read as zeros.

0201

Break. When set, this read /write bit transmits a continuous space. This bit

TX BRK

is cleared by power-up and SYSTEM INIT. This bit is used only in TCSR2;
it is unused in TCSRI.

Table 13-5
Bits

Mnemonic

13.3

Description

Unused. Read as zeros.

15-08

07-00

TBUF1 and TBUF2 Bit Assignments

TBUF

TBUTF bits 07-00 are write-only bits used to load the transmitted character.
If less than eight bits are selected, the character must be right-justified.

INTERRUPT VECTORS AND INTERRUPT PRIORITY

Two interrupt vectors are provided for the console SLU: one for the SLU transmitter and the other for
the SLU receiver. Four interrupt vectors are provided for the second SLU, but only two may be used at
any given time. The two vectors that are used by the second SLU depend on the DL2 ADRIJ L (J12)
jumper configuration. Table 13-6 lists the vectors provided for the console and second serial-line units.

, The interrupt priority for both SLUs is BR4.
13.4

CONSOLE SLU BREAK RESPONSE

The KDF11-BA console serial-line unit may be configured either to perform a halt operation or to have
no response when a break condition is received. A halt operation will cause the processor to halt and
enter the on-line debugging technique (ODT) microcode.

If the console SLU is disabled (J14 connected to J10), the halt-on-break feature must also be disabled.
The halt-on-break feature is disabled by removing the jumper between J3 and J4 and connecting a

jumper between J4 and J5.

13.5

SERIAL-LINE I/0 SIGNALS

The two SLUS’ input/output signals interface to the console terminal and peripheral device via two
connectors (J1 and J2). The connector pin functions for both SLUs are identical and are described in
Table 13-7. The 10 pins on each connector (Digital part No. 12-13506-04) are arranged in two rows
with five pins in each row.

13-4

Table 13-6

Console and Second SLU Interrupt Vectors

Console SLU
Receiver

Transmitter

Second SLU*
Receiver

Transmitter

060

064

300%*

304

304 **

344

*DL2 DISJ L (J13) must be ungrounded to enable the Second SLU.
**DL2 ADRJ L (12) must be ungrounded.
***DL2 ADRJ L (J12) must be grounded to J10.

Table 13-7

SLU Connector Pin Functions

Pin | Signal

Function

EXT CLK

Input for optional external clock signal.*

Ground

XMIT+

Ground

Key; pin not provided.

RCV —

Receiver input (most negative).

RCV +

Receiver input (most positive).

Ground

+12V

Transmitter output.

Power for external options; fused at 1 A.

*Paragraph 2.2.7 describes the internal /external SLU clock jumpers.

13-5

CHAPTER 14
COMMERCIAL INSTRUCTION SET

14.1

INTRODUCTION

The commercial instruction set (CIS) provided by the KEF11-BB option is a series of instructions for
manipulating byte strings in order to improve COBOL performance, text editing, and word processing
capabilities. CIS includes instructions that operate on character strings and on decimal numbers. Each
generic type of instruction is provided in two forms. The essential difference between the two forms is
the manner in which operands are delivered to the instruction. The first form 1s the “register’” form,
where operands are implicitly obtained from the general registers. The second form 1s the “in-line”
form, where operands or word address pointers to operands follow the op-code word in the instruction
stream. The mnemonic for the in-line form is the mnemonic for the register form suffixed with the
letter ““I.”” The condition codes are set identically for both forms. The in-line forms minimize register
modifications.

The CIS also includes commercial load descriptor instructions used for instruction control. These instructions augment the character and form instructions by efficiently loading operands (string descriptors) into the general registers. Descriptors consist of the starting address of the string and the length of
the string. Two forms of instructions are provided. The first form of the instruction loads two string
descriptors into the general registers. The second form loads three string descriptors into the general
registers.

The instructions in the PDP-11 CIS consist of the following extended instruction groups.
07602X
07603X
07604X
07605X
07606X
07607X
07613X
07614X
07615X
07617X

14.2

Commercial Load 2 Descriptors
Character String Move
Character String Search
Numeric String
Commercial Load 3 Descriptors
Packed String
Character String Move (in-line)
Character String Search (in-line)
Numeric String (in-line)
Packed String (in-line)

UNPREDICTABLE CONDITIONS

A result of an instruction or the effect of an instruction can be “unpredictable.” Unpredictable describes an outcome that is indeterminate and nonrepeatable. When the results of an instruction are unpredictable, the condition codes and destination operands (but not their descriptors) will contain unpredictable values; destinations may not even contain valid results. When the effect of an instruction is
unpredictable, the entire user or process state, and not only the portion typically used by the instruction,
will be unpredictable. In a machine with multiple modes and address spaces, and unpredictable operation in a less privileged mode will not affect the state of a more privileged mode, nor will it result in
accesses to memory from user mode that are outside the mapped limits of the user’s program.

14-1

Note that architectural constraints exist on unpredictable effects. In particular, an unpredictable effect
that manifests itself as a trap must meet all the requirements for the particular trap.
14.3 CHARACTER DATA TYPES
There are three different character data types.

A “character,” a single byte with an abbreviated string of length 1.

A “character string,” a contiguous group of bytes in memory.

A “character set,” a subset of the 256 possible characters that can be encoded in a byte.

14.3.1
Character
A character is an 8-bit byte, as shown in Figure 14-1.

MR-6903

Figure 14-1

8-Bit Byte Character

A character is used as an operand by CIS instructions. When one appears in a general register, it is in
the low-order half; the high-order half of the register must be zero. When it appears in the instruction
stream, the character is in the low-order half of a word; the high-order half of the word must be zero. If
the high-order half of a word that contains a character is nonzero, the effect of the instruction that uses
it will be unpredictable.
14.3.2

Character String

A character string is a contiguous sequence of bytes in memory that begins and ends on a byte boundary. It is addressed by its most significant character (lowest address). The highest address is the least
significant character. A character string is specified by a 2-word descriptor with the attributes of length
and lowest address. The length is an unsigned binary integer that represents the number of characters
in the string and may range from 0 to 65,535. A character string with zero length is said to be vacant;
its address is ignored. A character string with nonzero length is'said to be occupied.

The character string descriptor is used as an operand by CIS instructions. The descriptor appears in two
consecutive general registers, or in two consecutive words in memory pointed to by a word in the in-

struction stream. Figure 14-2 shows the descriptor for a character string of length “n” starting at address “A” in memory.

RX+1

—

]

—

]

PTR

PTR+2
MR-6904

Figure 14-2

Character String Descriptor

14-2

Figure 14-3 shows the character string as it would be placed in memory.
07
!

]

MOST SIG CHAR

07
A+1

v
07
f

A+N-1

LEAST SIG CHAR
|

]

MR-69065

Figure 14-3

14.3.3

Character String in Memory

Character Set

A character set is a subset of the 256 possible characters that can be encoded in a byte. It is specified
by a descriptor that consists of the address of a 256-byte table and an 8-bit mask. The address is of byte
0 in the table. Each byte in the table specifies up to eight orthogonal character subsets of which the
corresponding character is a member. The mask selects which combinations of these orthogonal subsets
comprise the entire character set. In effect, each bit in the mask corresponds to one of eight orthogonal
subsets that may be encoded by the table. The mask specifies the union of the selected subsets into the
character set. Typical sets would be: uppercase, lowercase, nonzero digits, end-of-line, etc.
Operationally, a character (char) is considered to be in the character set if the evaluation of
(M[table.adr+char].mask) is not equal to zero. The character is not in the character set if the evaluation is zero. Each byte in the table indicates of which combination of up to eight orthogonal character

subsets (i.e., one for each of the eight bit vectors: 00000001(2), 00000010(2), 00000100(2),

00001000(2), 00010000(2), 00100000(2), 01000000(2) and 10000000(2)) the corresponding character
is a member. The mask specifies which union of the eight orthogonal character subsets comprises the
total character set. For example, if (a) the 8-bit vector 00000001(2) appearing in the table corresponds
to the character subset of all uppercase alphabetic characters, (b) 00000010(2) appearing in the table
corresponds to the character subset of all lowercase alphabetic characters, and (c) 00000100(2) appearing in the table corresponds to the decimal digits, then using the mask 00000011(2) with this table
specifies the character set of all alphabetic characters, and using the mask 0000011 1(2) specifies the
character set of all alphanumeric characters.

The character set descriptor is used as an operand by CIS instructions. It appears in two consecutive
general registers, or in two consecutive words of memory pointed to by a word in the instruction stream.
If the high-order half of the first descriptor word is nonnzero, the effect of an instruction that uses a
character set will be unpredictable. The character set format is shown in Figure 14-4.

14-3

—

]

<
>

00
T

——

]

PTR+2

—

4;—

—_

e S

——

RX+1

PTR

——

08
-~

TABLE ADDRESS
]

]

MR-6906

Figure 14-4

Character Set Format

14.3.4 Character String Instructions
Character string operations conveniently provide most of the common, as well as time-consuming, functions that are encountered in commercial data and text processing applications. Instructions are provided to move and to search character strings.

The character string move instructions use character string descriptors as operands. These descriptors
specify a source and a destination character string. The contents of the source are moved to the destination with alignment at either the most significant character, as in MOVC(I) and MOVTC(I), or the
least significant character, as in MOVRC(I). If the source is longer than the destination, characters are
truncated from the side opposite that of the alignment; if the destination is longer than the source, the
destination is completed with fill characters on the side opposite that of the alignment. The MOVTC(I)
instructions move a translated source string to a destination string. The character string move instructions are summarized below.
Character String Move Instructions

MOVC(I)
MOVRC(I)
MOVTC(I)

Move character

Move reverse-justified character
Move translated character

The character string search instructions use a character string descriptor as one operand. The other
operand is either a character, a character string descriptor, or a character set descriptor. These instructions are used to examine the source string to find the presence or absence of characters. The source
string is processed from most significant to least significant character. The character string search instructions are summarized below.
Character String Search Instructions

LOCC(D)
SKPC(I)
SCANC(I)
SPANC(I)
CMPC(I)
MATC(I)

Locate character

Skip character
Scan character
Span character
Compare character
Match character

Conceptually, the character string search instructions may be divided into three classes.

Character String Searches — CMPC(I) compares two character strings. The condition codes
are set according to the comparison of the corresponding most significant unequal characters.

MATC(I) finds an object string within a source string. This is the “in-string” function that
languages and text processing systems provide.

14-4

Character Searches — LOCC(I) finds the first occurrence of a given character in a string.
SKPC(I) skips to the first nonoccurrence of a given character in a string.

Character Set Searches — In these instructions, a string is examined until a member of a
character set is either found, as in SCANC(I), or found, as in SPANC(I). This aids the
search for one of several delimiters, such as the slash (/), comma (,), CR, LF, FF, etc., or the
passing of combinations of characters such as blanks, tabs, etc. LOCC(I) and SKPC(I) are
optimizations of SCANC(I) and SPANC(I), in which the set consists of a single character.

The setting of condition codes reflects the results of the character string operations. For character
string moves, the condition codes indicate whether the source and destination strings were of equal
length, the source was shorter than the destination so that fill characters were used, or the source was

longer than the destination so that characters were truncated. This is accomplished by setting the condition codes on the result of an arithmetic comparison of the initial source and destination lengths. For
CMPC(I) the condition codes are the result of arithmetically comparing the most significant corresponding pair of unequal characters. For the other search instructions they show whether or not the

operand strings were completely examined.

The condition codes for some character string search instructions may be interpreted according to the
notion of success or failure. Success is the accomplishment of the instruction’s task; failure is the inability to accomplish the task. Since the condition codes are set based on the results of the instruction,
there is an indirect correspondence between these settings and success or failure. This correspondence
is invariant within an instruction, but it is not the same for all search instructions. Therefore, different
branch instructions must be used to test the operation of each instruction. The branch instructions are
summarized below.

Instruction

Success

Failure

LOCC(I)
SCANC(I)
CMPC(I)
MATC(I)

BNE
BNE
BEQ
BNE

BEQ
BEQ
BNE
BEQ

The “register form” of character string instructions implicitly finds operands in the general registers.
These operands include character, character string descriptor, character set descriptor, and translation
table address. If an instruction does not use a register, its contents will be undisturbed. RO-R1 generally contain a source character string descriptor; R2-R3 generally contain a second source character
string descriptor, or the destination string descriptor. The low-order half of R4 is used as an explicit
character. R4-R35 are used to contain a character set descriptor. R5 contains the starting address of a
256-byte table, which is used for character translation.

When move instructions terminate, RO contains the number of unmoved source characters, and R1, R2,
and R3 are cleared. For search instructions, the registers are updated to represent descriptors for the
resulting strings.

The “in-line” form of character string instructions finds operands, or pointers to operands, in the instruction stream immediately following the op-code word. Operands that appear directly in the instruction stream include characters and translation table addresses. Descriptors are represented in the in-

14-5

struction stream by a single word whose contents are interpreted as a word address pointer to the 2word descriptor. These descriptors specify character strings and character sets. Some instructions return a character string descriptor in RO-R1.

In general, all character string instructions are unaffected by the overlapping of source or destination
strings. The result of the move instructions is equivalent to having read the entire source string before
storing characters in the destination. If the destination string of the MOVTC(I) instructions overlaps
the translation table, the characters stored in the destination string will be unpredictable.
14.4

DECIMAL STRING DATA TYPES

Two classes of decimal string data types — numeric strings and packed strings — are defined. Both have
similar arithmetic and operational properties; they differ primarily in their representation of signs and
the placement of their digits in memory.

- The numeric string data types are signed zoned, unsigned zoned, trailing overpunched, leading overpunched, trailing separate, and leading separate. The packed string data types are signed packed and

unsigned packed. Instructions that operate on numeric strings permit each numeric string operand to be
separately specified; similarly, packed string instructions permit each packed string operand to be separately specified. Thus, within each of the two classes of decimal strings, the operands of an instruction
may be of any data type within the appropriate class.

Decimal strings exist in memory as contiguous bytes that begin and end on a byte boundary. They represent numbers consisting of 0 to 31;¢ digits, in either sign-magnitude or absolute-value form. Signmagnitude strings (signed) may be positive or negative; absolute-value strings (unsigned) represent the
absolute value of the magnitude. Decimal numbers are whole integer values with an implied decimal
radix point immediately after the least significant digit; they may be extended conceptually with the
addition of Os before the most significant digit.
A 4-bit binary coded decimal representation is used for most digits in decimal strings. A 4-bit half byte
is called a “nibble” and may be used to contain a binary bit pattern that represents the value of a
decimal digit. The following shows the binary nibble contents associated with each decimal digit.

Digit

Nibble

0
1

0000
0001

0010
0011

3
4

0100
0101

5
6
7

0110
0111

1000

1001

Each decimal string data type may have several representations. These representations permit a certain
latitude when accepting source operands. Decimal string data types have a “preferred” representation,
which is a valid source representation used to construct the destination string. Also, “alternate” representations are provided for some decimal data types when accepting source operands.

14-6

Decimal strings used as source operands are not checked for validity. Instructions will produce unpredictable results if a decimal string used as a source operand contains invalid digit encoding, an invalid
sign designator, or, in the case of overpunched numbers, invalid sign/digit encoding. When used as a
course, decimal strings with zero magnitude are unique, regardless of sign. Thus, positive zero and
negative zero have identical interpretations.
Conceptually, decimal string instructions first determine the correct result, then store the decimal
string representation of the correct result in the destination string. A result of zero magnitude is considered to be positively signed. If the destination string can contain more digits than are significant in the
result, the excess most significant destination string digits have zero digits stored in them. If the destination string cannot contain all significant digits of the result, the excess most significant result digits
are not stored; the instruction will indicate decimal overflow. Note that negative zero is stored in the
destination string as a side effect of decimal overflow where the sign of the result is negative and the
destination is not large enough to contain any nonzero digits of the result.
If the destination string has zero length, no resulting digits will be stored. The sign of the result will be
stored in separate and packed strings, but not in zoned and overpunched strings. Decimal overflow will
indicate a nonzero result.
14.4.1
Decimal String Descriptors
Decimal strings are represented by a 2-word descriptor. The descriptor contains the length, data type,
and address of the string. It appears in two consecutive general registers (in the register form of instructions), or in two consecutive words in memory pointed to by a word in the instruction stream (in the inline form of instructions). The unused bits are reserved by the architecture and must be Os. The effect
of an instruction using a descriptor will be unpredictable if any nonzero reserved field in the descriptor
contains nonzero values or a reserved data type encoding is used. The design of the numeric and packed
string descriptors are identical:
First Word

(L) length <4:0>

Number of digits specified as an unsigned binary integer.

(T) data type <14:12>

Specifies which decimal data type representation is used.

Second Word

(A) address <15:0>

Specifies the address of the byte that contains the most significant digit
of the decimal string.

The descriptor format for a decimal string of data type T whose length is L. and whose most significant
digit is at address A is shown in Figure 14-5.

}

PTR+2

-—>—-L——

RX+1

PTR

MR-6907

Figure 14-5

Decimal String Descriptor

14-7

The encodings (in binary) for the “numeric” string data type field are
000
001
010
011
100
101
110
111

Signed zoned
Unsigned zoned
Trailing overpunched
Leading overpunched
Trailing separate
Leading separate
Reserved for use by DIGITAL
Reserved for use by DIGITAL

The encodings (in binary) for the packed string data type field are
000
001
010
011
100
101
110
111
14.4.2

Reserved for use by DIGITAL
Reserved for use by DIGITAL
Reserved for use by DIGITAL
Reserved for use by DIGITAL
Reserved for use by DIGITAL
Reserved for use by DIGITAL
Signed packed
Unsigned packed

Packed Strings

Packed strings can store two decimal digits in each byte. The least significant (highest addressed) byte
contains the sign of the number in bits <<3:0> and the least significant digit in bits <<7:4>.
Signed Packed Strings — The preferred positive sign designator is 1100; alternate positive sign designators are 10105, 11105 and 1111,. The preferred negative sign designator is 11015; the alternate negative
sign designator is 1011,. Source strings will properly accept both the preferred and alternate designators; destination strings will be stored with the preferred designator.
Unsigned Packed Strings — The unsigned signed designator 1s 11115.
Packed Sign Nibble
Sign
Nibble

Preferred
Designator

Alternate
Designator(s)

Positive
Negative
Unsigned

1100,
1101,
1111,

10105, 11105, 11115
1011,

For other than the least significant byte, bytes contain two consecutive digits — the one of lower significance in bits <<3:0> and the one of higher significance in bits <<7:4>. For numbers whose length 1is
odd, the most significant digit is in bits <<7:4> of the lowest addressed byte. Numbers with an even
length have their most signicant digit in bits <<3:0> of the lowest addressed byte; bits <<7:4> of this
byte must be zero for source strings, and are cleared to 0000 for destination strings. Numbers with a
length of one occupy a single byte and contain their digit in bits <<7:4>. The number of bytes that
represents a packed string is [length/2] + 1 (integer division where the fractional portion of the

quotient is discarded).

The format for a packed string with an odd number of digits is shown in Figure 14-6, and the format for
a packed string with an even number of digits is shown in Figure 14-7.

14-8

04
I

]

MSD
|

]

A+1

v
07

04
i

A+(LENGTH/2)

LSD
|

SIGN

|
MR-6908

Figure 14-6

Packed String — Odd Digits

04
I

MSD

]

A+1

v
07

04
1

A+(LENGTH/2)

00
T

LSD
|

SIGN
]

|
MR-6909

Figure 14-7

Packed String — Even Digits

A zero-length packed string occupies a single byte of storage; bits <<7:4> of this byte must be zero for
source strings, and are cleared to 0000 for destination strings. Bits <<3:0> must be a valid sign for
source strings, and are used to store the sign of the result for destination strings. When used as a source,
zero-length strings represent operands with zero magnitude. When used as a destination, they can only
reflect a result of zero magnitude without indicating overflow. The format for a packed string with a
zero length is shown in Figure 14-8.

MR-6910

Figure 14-8

Packed String — Zero Length

14-9

N
=

The following are the characteristics of a valid string.

14.4.3

A length of 0 to 31 digits.
Every digit nibble is in the range 0000 to 1001,.

For even-length sources, bits <<7:4> of the lowest addressed byte are 0000.
Signed packed strings — sign nibble is either 10105, 10115, 11002, 11015, 11105 or 11115.
Unsigned packed strings — sign nibble 1s 11115.
Zoned Strings

Zoned strings represent one decimal digit in each byte. Each byte is divided into two portions — the
high-order nibble (bits <7:4>) and the low-order nibble (bits <<3:0>). The low-order nibble contains
the value of the corresponding decimal digit. Zoned strings may be either signed or unsigned. The format for zoned strings is shown in Figure 14-9.

04
I

03
T

MSD

A
|

]

{

A+1

07
|

A+N-1

SIGN
|

LSD

“SIGN" IS PRESENT ONLY
|

SIGNED ZONED STRINGS
MR-6911

Figure 14-9

Zoned Strings

Signed Zoned Strings — When used as a source string, the high-order nibble of the least significant byte
contains the sign of the number; the high-order nibbles of all other bytes are ignored. Destination
strings are stored with the sign in the high-order nibble of the least significant byte, and 00115 in the
high-order nibble of all other bytes. In the high-order nibble 0011, corresponds to the ASCII encoding
for numeric digits. The positive sign designator is 0011,; the negative sign designator is 0111».
Unsigned Zoned Strings — When used as a source string, the high-order nibbles of all bytes are ignored.
Destination strings are stored with 0011, in the high-order nibble of all bytes. The number of bytes
needed to contain a zoned string is identical to the length of the decimal number.

A zero-length zoned string does not occupy memory; the address portion of its descriptor is ignored.
When used as a source, zero-length strings provide operands with zero magnitude; when used as a destination, they can only accurately reflect a result of zero magnitude (the sign of the operation is lost). An
attempt to store a nonzero result will be indicated by the setting of overflow. The following are the
characteristics of a valid zoned string.
1.

A length of 0 to 31;¢ digits.

14-10

The low-order nibbles of each byte are in the range 0000 to 1001,.

Signed zoned strings — The high-order nibble of the least significant byte is either 0011, or
0111,.

14.4.4

Overpunched Strings

Overpunched strings represent one decimal digit in each byte. Trailing overpunched strings combine

the encoding of the sign and the least significant digit; leading overpunched strings combine the encod-

ing of the sign and the most significant digit. Bytes other thar the byte in which the sign is encoded are
divided into two portions — the high-order nibble (bits <<7:4>) and the low-order nibble (bits <<3:0>).
The low-order nibble contains the value of the corresponding decimal digit. When used as a source
string, the high-order nibble of all bytes that do not contain the sign are ignored. Destination strings are
stored with 0011, in the high-order nibble of all bytes that do not contain the sign. In the high-order
nibble 0011, corresponds to the ASCII encoding for numeric digits.
The list below shows the sign of the decimal string and the value of the digit encoded in the sign byte.
Source strings will properly accept both the preferred and alternate designators; destination strings will
store the preferred designator. The preferred designators correspond to the ASCII graphics A to R, and
the open and close brace ({ and }). The alternate designators correspond to the ASCII graphics 0 to 9,
the open and close brackets ([ and ]), a question mark (?), exclamation point (!), and colon (:).
Overpunched Sign/Digit Byte
Overpunched

Preferred

Alternate

Sign/Digit

Designator

Designator(s)

+0
+1
+2
+3
+4
+5
+6
+7
+ 8
+9
—0

011110115
01000001,
01000010,
010000115
01000100,
01000101,
01000110,
01000111,
01001000,
01001001,
01111101,

001100005, 010110115, 00111111,
00110001,
00110010,
00110011,
00110100,
00110101,
00110110,
00110111,
00111000,
00111001,
010111015, 001000015, 00111010,

—1

01001010,

—2

01001011,

—3
—4

01001101,

—5

01001110,

—6

01001111,

—7
—8

01010000,
01010001,

—9

01010010,

01001100,

The number of bytes needed to contain an overpunched string is identical to the length of the decimal
number. The format for a trailing overpunched string is shown in Figure 14-10. The leading overpunched string is shown in Figure 14-11.

14-11

04
T

MSD
]

07/

A+1

07/

04
|

]

A+N-1

SIGN AND LSD
|

MR-6912

Figure 14-10

Trailing Overpunched String

04
1

03
T

00
!

]

)

SIGN AND MSD
|

]

A+1

v
07

]

A+N-1

LSD
1

|
MR-6913

Figure 14-11

Leading Overpunched String

A zero-length overpunched string does not occupy memory; the address portion of its descriptor is ig-

nored. When used as a source, zero-length strings provide operands with zero magnitude; when used as
a destination, they can only accurately reflect a result of zero magnitude (the sign of the operation is
lost). An attempt to store a nonzero result will be indicated by the setting of overflow. The following are
the characteristics of a valid overpunched string.
1.

A length of 0 to 31;¢ digits.

The low-order nibble of each digit byte is in the range 0000 to 10015,.

The encoded sign/digit byte contains values from the above list of preferred and alternate
overpunched sign/digit values.

14-12

14.4.5

Separate Strings

Separate strings represent one decimal digit in each byte. Trailing separate strings encode the sign in
the byte immediately after the least significant digit; leading separate strings encode the sign in the
byte immediately before the most significant digit. Bytes other than the byte in which the sign is encoded are divided into two portions — the high-order nibble (bits <<7:4>) and the low-order nibble (bits

<3:0>). The low-order nibble contains the value of the corresponding decimal digit.
When used as a source string, the high-order nibbles of all digit bytes are ignored. Destination strings
are stored with 0011, in the high-order nibble of all digit bytes. In the high-order nibble 0011, corresponds to the ASCII encoding for numeric digits. The preferred positive sign designator is 001010115,
and the alternate positive sign designator is 00100000,. The negative sign designator is 001011015.
These designators correspond to the ASCII encoding for the plus sign (4 ), a space, and minus sign

(—).
Separate Sign Byte

Sign

Preferred

Positive

00101011,

Negative

00101101,

Byte

| Alternate

Designator

00100000+

The number of bytes needed to contain a leading or trailing separate string is identical to the length +
1. The format for a trailing separate string is shown in Figure 14-12. The leading separate string is
shown in Figure 14-13.

04
|

MSD
|

]

A+1

v
07

]

A+N-1

LSD

A+N

SIGN
]

MR-6914

Figure 14-12

Trailing Separate String

14-13

04
]

]

SIGN

A-1

MSD

]

A+1

v
07

]

LSD

A+N-1

]

MR-6915

Figure 14-13

Leading Separate String

A zero-length separate string occupies a single byte of memory that contains the sign of the string.
When used as a source, zero-length strings provide operands with zero magnitude; when used as a destination, they can only reflect a result of zero magnitude without indicating overflow. The sign of the
result is stored.

The format for a zero-léhgth trailing separate string is shown in Figure 14-14. The zero-length leading
separate string is shown in Figure 14-15.

00
T

]

]
MR-6916

Figure 14-14

Zero-Length Trailing Separate String

00
T

A-1

]

SIGN
|

]

MR-6917

Figure 14-15

Zero-Length Leading Separate String

The following are the characteristics of a valid separate string.
1.

A length of 0 to 31;¢ digits.

The low-order nibble of each digit byte is in the range 0000 to 10015.

The sign byte is either 00100000,, 00101011, or 001011015.

14-14

14.4.6

Long Integer

Long integers are 32-bit binary 2’s complement numbers organized as two words in consecutive registers or in memory — no descriptor is used. One word contains the high-order 15 bits. The sign is in bit
< 15>; bit <<14> is the most significant. The other word contains the low-order 16 bits with bit <0>
the least significant. The range of numbers that can be represented is —2,147,483,648 to
+2,147,483,647.
The register form of decimal convert instructions uses a restricted form of long-integer format with the
number in the general register pair R2—R3. The format for the register form of decimal convert instructions i1s shown in Figure 14-16.

om—

HIGH
T

R2 | s

LOW

MR-6918

Figure 14-16

Decimal Convert (Register Form)

The in-line form of decimal convert instructions reference the long integer by a word address pointer,
which is part of the instruction stream. The format for the in-line form of decimal convert instructions
is shown in Figure 14-17.

PTR

PTR+2 |

LOW

HIGH
MR-6919

Figure 14-17

Decimal Convert (In-Line Form)

Note that these two representations of long integers differ. There is no single representation of long
integers among EAE, EIS, FPP and software. The “register” form was selected to be compatible with
EIS; the “in-line” form was selected to be compatible with current standard software usage.
14.4.7

Decimal String Instructions

Decimal string instructions aid in the manipulation of decimal data. Several numeric (byte) and packed
decimal data types are supported. Instructions are provided for basic arithmetic operations, as well as
for compare, shift, and convert functions.
Each arithmetic, shift and compare instruction operates on a single class of data type. Both numeric
and packed string instructions are provided for most operations. Convert instructions have a source operand of one data type and a destination operand of another data type. Decimal string instructions specify to which class each of their decimal string operands belong. The data type supplied as part of each
operand’s descriptor may be any valid data type of the class. This permits a general mixing of data
types within numeric and packed classes. The data types on which an instruction operates are designated by the last letter(s) of the op-code mnemonic. N denotes numeric strings, P denotes packed
strings, and L denotes long binary integers.

14-15

The arithmetic instructions are ADDN(I), ADDP(I), SUBN(I), SUBP(I), MULP(I) AND DIVP(I).
ASHN(I) and ASHP(I) shift a decimal string by a specified number of digit positions (in either direction) with optional rounding, and store the result in the destination string. Thus, they effectively multiply or divide by a power of 10. If the shift count is zero, these shift instructions can be used simply to
move decimal strings (destinations are stored with preferred representation). Move negated may be accomplished by using SUBN(I) or SUBP(I). Arithmetic comparison instructions, CMPN(I) and
CMPP(]), are provided to examine the relative difference between two decimal strings.

CVTNL(I) and CVTPL(I) convert a decimal string to a long (32-bit) 2’s complement integer.
CVTLN(I) and CVTLP(I) convert a long integer to a decimal string. CVTNP(I) and CVTPN(I) convert between numeric and packed decimal strings.
The following is a list of the decimal string instructions.
- Packed String Instructions

ADDP(I)
SUBP(I)
MULP(I)
DIVP(I)
ASHP(I)
CMPP(I)

Add packed
Subtract packed
Multiply packed
Divide packed
Arithmetic shift packed
Compare packed

Numeric String Instructions

ADDN(I)
SUBN(I)
ASHN(I)
CMPN(I)

Add numeric
Subtract numeric
Arithmetic shift numeric
Compare numeric

Convert Instructions

CVTNL
CVTLN
CVTPL
CVTLP
CVTNP
CVTPN
14.4.8

Convert numeric to long
Convert long to numeric
Convert packed to long
Convert long to packed
Convert numeric to packed
Convert packed to numeric
Condition Codes

For instructions that store a value in a destination string, the N and Z bits reflect the value stored. The
N bit indicates a negative destination; the Z bit indicates a destination having zero magnitude. A destination string with zero magnitude is considered to be positive (even if a negative zero was stored as a
consequence of decimal overflow). Thus, the setting of N and Z are mutually exclusive.
The V bit indicates whether the destination string accurately represents the result of the instruction. It
is also set if division by zero was attempted. If the V bit is set, the destination string will represent the
least significant portion of the result (truncated). If the V bit is cleared, the destination represents the
true result.

For DIVP(I), C indicates division by zero. Otherwise, C is always cleared. For comparisons using the
CMPN(I) and CMPP(I) instructions, the N and Z bits reflect the signed relationship between the
source strings. The signed branch instructions can test the result. V and C are cleared.

14-16

For instructions that return a long-integer value, N reflects the sign of the 2’s complement integer, and
7 indicates whether it was zero. V indicates whether the long integer could not contain all significant
digits and sign of the result. CVTNL(I) and CVTPL(I) also use C to represent a borrow from a more

significant portion of the long binary result. Otherwise, C is cleared.
Operand Delivery

14.4.9

The “register” form of decimal string instructions implicitly finds the operands in the general registers.
These operands include decimal string descriptors, long binary integers, and shift descriptor words. If
an instruction does not use a register, its contents will be undisturbed. RO-R1 generally contain the first
source descriptor, R2-R3 the second source descriptor, and R4-R5 the destination descriptor. ASHN
and ASHP use R4 to contain a shift descriptor word. CVTLN, CVTLP, CVTNL and CVTPL use
RO-R1 to contain a decimal string descriptor, and R2-R3 for the long integer. When an instruction is
completed, the source descriptor registers are cleared.

The “in-line” form of the decimal string instructions finds the operands, or pointers to descriptors, in
the instruction stream immediately following the op-code word. Operands that appear directly in the
instruction stream are shift descriptor words. Operands that are represented in the instruction stream
by a pointer containing the word address of the descriptor are decimal string descriptors and long binary integers. No in-line form of decimal string instructions modifies RO-R®6.
14.4.10

Data Overlap

The operation of decimal string instructions is unaffected by an overlap of the source operands, provided that each source operand is a valid representation of the specified data type. The overlap of the
destination string and any of the source strings will, in general, produce unpredictable results. However,
ADDN(I), ADDP(I), SUBN(I) and SUBP(I) will permit the destination string to overlap either or both
source strings only if all corresponding digits of the strings are in coincident bytes in memory. This
facilitates 2-address arithmetic.

14.5

COMMERCIAL LOAD DESCRIPTOR INSTRUCTIONS

The commercial load descriptor instructions augment the character and decimal string instructions by
efficiently loading the general registers with string descriptors. Two forms of instructions are provided.
The first form, the L2Dr instructions, load two string descriptors into the general registers. The first
descriptor is loaded into RO-R1 and the second descriptor is loaded into R2-R3. This instruction supports equal-length character string move, equal-length character string compare, character string
matching, and decimal string compare. The second form, the L3Dr instructions, take three descriptors.
1, the second into R2-R3, and the third into R4—RS5. The instruction supThe first is loaded into RO-R
ports 3-address arithmetic. The condition codes are not affected for either form of instruction.
Words containing the addresses of the descriptors (two for L2Dr and three for L3Dr) are in consecutive
locations in memory. The descriptor addresses are found by applying the addressing mode @(Rr)-+
once for each descriptor. The value of r is encoded as the low-order three bits of the instruction’s opcode. If 0 r 5, r can be thought of as the base address of a small table in memory, where each entry in
the table contains the address of a descriptor. If r = 6, the instructions effectively pop the addresses of
descriptors off the stack. If r = 7, the descriptor addresses are contiguous with the instruction’s opcode word.

The string descriptors are two words long. The address of the descriptor is that of the low-order word. It
is loaded into the corresponding even register. The high-order word of the descriptor is loaded into the
corresponding odd register. Note that although these instructions are described in terms of string descriptors, they are applicable for instances where two consecutive words in memory referenced by a
pointer are to be copied into even-odd general register pairs. The following is a list of the commercial
load descriptor instructions.

14-17

Command

Load 2 descriptors
using:

L2D0

@(RO)+

L2D1

@(R1)+

L2D2

@(R2)+

L2D3

@(R3)+

L2D4

@(R4)+

L2D5

@(R5)+

L2D6

@(R6)+

L2D7

@(R7)+

Load 3 descriptors
using:

L3DO0

@(RO)+

L3D1

@(R1)+

L3D2

@(R2)+

L3D3

@(R3)+

L3D4

@(R4)+

L3D5

@(R5)+

L3D6

@(R6)+

L3D7

@(R7)+

14.6 INSTRUCTION SUSPENSION

The intent in defining instruction suspendability is to establish a means for providing reasonable interrupt latency and does not presume to endow CIS instructions with an ability to recover from trap conditions from which sequences of basic instructions cannot recover.

Suspension events refer primarily to events that occur asynchronously with the instruction’s execution;
these are specifically the interrupts generated by 1/O peripheral devices, power-fail traps, and floatingpoint processor exceptions. Secondarily, suspension-events can refer also to those synchronous trap

events that occur only for information notification purposes and do not imply that the integrity of the
instruction’s execution is in jeopardy. Such suspension events include “yellow zone” traps.
Potentially suspendable instructions have a defined architectural mechanism (PS<8> as described be-

low) by which they can be suspended in midexecution to allow the processor to service suspension
events. The instructions are subsequently resumed from the point where they had been suspended.

The presence of suspension events may cause certain CIS instructions to be suspended on some processors. If the instruction is suspended, PS<<8> will be set, R7 will be backed up to address the op-code

word, and the suspension event will be serviced. When the instruction is resumed, PS<8> indicates
that execution of the instruction had been in progress.
In order to make these instructions suspendable on all processors, the instruction state is part of the user
state saved by interrupt handling routines. The instruction state includes the general registers, condition

codes, and memory. This state is processor-dependent when suspended. Software should not attempt to
interpret or modify this state; it must only be saved and restored.
Up to 6419 words of the internal instruction state may also have been pushed onto the stack. This state

must not be modified by software also. The instruction will remove this state from the stack when it is

resumed.
14-18

If PS<8> is set prior to the execution of a potentially suspendable instruction, the effect of the instruction is unpredictable. PS<<8> is cleared upon normal completion of a potentially suspendable instruction. PS<<8>> represents “instruction suspension” and has the corresponding mnemonic “IS.”

All suspendable instructions use PS<<8> to indicate instruction suspension. If, when a potentially suspendable instruction is executed, PS<<8> is clear, the instruction is being commenced; if the bit is set,
e

the instruction is being resumed. PS<<8> is cleared when:

A suspended instruction is successfully completed.
The processor powers up.

A new PS is fetched from a vector location with PS<<8> clear.
el S

RTI or RTT is executed with a new PS<<8> clear.
It is explicitly cleared by an instruction.
PS <8> is set when:

2SO
o —

A potentially suspendable instruction is interrupted and requests to be suspended.
A new PS is fetched from a vector location with PS<<8> set.
RTI or RTT is executed with PS<<8> set.
It is explicitly set by an instruction.

The setting of this bit has no effect on instructions that are not potentially suspendable; such instructions do implicitly modify this bit.

When an instruction is suspended, the state that follows may contain information vital to the resumption of the instruction. The information must be preserved and restored prior to restarting the suspended instruction. The nature of the information may vary from one execution of the instruction to
|

another; it may comprise any of the following.
1.

General registers RO-RS5.

Condition code bits (PS<<3:0>).

Up to 641¢ words on the stack of the context in which the suspended instruction had been
executing.

Any destinations used by the instruction.

Stack Utilization

CIS instructions may use the R6 stack for temporary ‘““scratch’ state storage. The maximum number of
additional words an extended instruction may claim on the R6 stack is 641g. The reason for imposing a
limit is to ensure that system software can adequately provide for worst-case stack allocation requirements. In addition to the above restriction, the normal PDP-11 stack-limit mechanism remains in effect
for extended instructions just as it does for any other instruction.

If insufficient stack space exists, the instruction will terminate by a memory management abort in such
a way that if additional stack space is allocated, the instruction will successfully restart.
Notation

dst
srcl

Destination string
Source string 1

STC2

Source string 2

dscr

Descriptor

14-19

14.7

EXTENDED INSTRUCTION DEFINITIONS

The commercial instruction set contains instructions to manipulate various data types and strings, in-

cluding character, numeric and decimal data. The operations performed include data type conversions,
string search operations, block moves, and arithmetic operations. The definitions of the 52 instructions
that compose the CIS are described in Paragraphs 14.7.1 through 14.7.20.
14.7.1

ADDN/ADDP/ADDNI/ADDPI

Purpose:

Add Decimal

Operation:

dst

Condition Codes:

N: set if dst << 0; cleared otherwise

src2 + srcl

Z: set if dst = 0; cleared otherwise
V: set if dst cannot contain all significant digits of the result; cleared otherwise

C: cleared

Op Codes:

ADDN

Description:

076050

ADDP

076070

ADDNI

076150

ADDPI

076170

Srcl is added to src2, and the result is stored in the destination string. The condition codes reflect the value stored in the destination string, and whether all significant digits were stored.

Register Form — ADDN and ADDP
When the instruction starts, the operands must have been placed in the general registers: the first
source descriptor must be in RO-R1, the second source descriptor in R2-R3, and the destination descriptor in R4-R5. The add decimal format is shown in Figure 14-18.

RO
—

SRCL.DSCR

—

————

——

]

R5
|

]

MR-6920

Figure 14-18

Add Decimal Format

14-20

When the instruction is completed, the source descriptor registers are cleared, as shown in Figure 14-

00
1]

]

1
|

1
I

|
{

|
|

|
LI

|
[

1
|

|
|

|
l

1
{

|
{

1
|

|
I

|
{

|
|

|
{

!
{

}
[

}
{

]
|

|
{

0
I

{

]

{

[

{

0
|
|

|
|

l
{

|
|

]
|

|
|

|
1

|
{

i
I

0
|
|

0
|
I

|
|

l
|

1
|

|
{

|
|

R4
—

DST.DSCR

]

R5
|

]

1
MR-6921

Figure 14-19

Add Decimal Format (Cleared)

In-Line Form — ADDNI and ADDPI
Each word address pointer that follows the op-code word in the instruction stream refers to a 2-word
decimal string descriptor. RO—R6 are unchanged when the instruction is completed.
|
Notes:

The operation of these instructions 1s unaffected by any overlap of the source strings, provided
that each source string is a valid representation of the specified data type.

Source strings may overlap the destination string only if all corresponding digits of the strings are
in coincident bytes in memory.

14.7.2

ASHN/ASHP/ASHNI/ASHPI

Purpose:

Arithmetic Shift Decimal

Operation:

dst

Condition Codes:

N: set 1f dst << O; cleared otherwise

src x 10** (shift count)

V: set if dst cannot contain all significant digits of the result; cleared otherwise
Z: set if dst = 0; cleared otherwise
C: cleared

Op Codes:

Description:

ASHN
ASHP
ASHNI
ASHPI

076056
076076
076156
076176

The decimal number specified by the source descriptor is arithmetically shifted
and stored in the area specified by the destination descriptor. The shifted result
is aligned with the least significant digit position in the destination string. The
shift count is a 2’s complement byte whose value ranges from —128;g to
+1271¢. If the shift count is positive, a shift in the direction of least to most

14-21

significant digits is performed. A negative shift count performs a shift from most

to least significant digit. Thus, the shift count is the power of 10 by which the
source 1s multiplied; negative powers of 10 effectively divide. Zero digits are supplied for vacated digit positions. A zero shift count will move the source to the
destination. The condition codes reflect the value stored in the destination string,
and whether all significant digits are stored.
A negative shift count invokes a rounding operation. The result is constructed by

shifting the source the specified number of digit positions. The rounding digit is
then added to the most significant digit that was shifted out. If this sum is less
than 101¢ the shifted result is stored in the destination string. If the sum is 10y
or greater the magnitude of the shifted result is increased by 1 and then stored in
the destination string. If no rounding is desired, the rounding digit should be
Zero.

The shift count and rounding digit are represented in a single word referred to as

the shift descriptor. Bits <<15:12> of this word must be zero. The shift descriptor format is shown in Figure 14-20.
15

08
[

0
|

00
T

RND.DGT

SHIFT.CNT
|

MR-6922

Figure 14-20

Shift Descriptor Format

Register Form — ASHN and ASHP
When the instruction starts, the operands must have been placed in the general registers: the source
descriptor must bein RO——RI the destination descriptorin R2—R3, and the shift descrlptorin R4. The
arithmetic shift decimal formatis shownin Figure 14-21.

,
|

{

]

00
I

RO
-

SRC.DSCR

—

RT
|
|

|
I

|
|

|
1

|
I

|
|

|
{

i
|

|
|

1
|

R2
—

DST.DSCR

—

R3
|
|

|
|

|
{

|
|

]

|
]

|
|

|
{

|
|

|
I

|
|

|
¥

SHIFT.DSCR
|

MR-6923

Figure 14-21

Arithmetic Shift Decimal Format

When the instruction is completed, the source descriptor registers and shift descriptor register are

cleared, as shown in Figure 14-22.

14-22

)

{

|
|

|
{

|
|

|
I

|
|

l
|

|
|

|
I

|
|

|
I

]
[

|
|

l
|

|
|

|
{

]
I

|
|

|
{

|
|

—

}

DST.DSCR

—
R3

L
|

]
I

|
|

]

|
{

|
|

1
{

|
|

]

MR-6924

Figure 14-22

Arithmetic Shift Decimal Format (Cleared)

In-Line Form — ASHNI and ASHPI

The words followong the op-code word in the instruction stream are a word address pointer to a 2-word
decimal string source descriptor, a word address pointer to a 2-word decimal string destination descriptor, and a shift descriptor word. RO—R6 are unchanged when the instruction is completed.
Notes:

If bits <15:12> of the shift descriptor word are not zero, the effect of the instruction is unpredictable.

If bits <<11:8> of the shift descriptor are not a valid decimal digit, the results of the instruction
are unpredictable.

Any overlap of the source and destination strings will produce unpredictable results.

14.7.3

CMPC/CMPCI

Purpose:

Compare Character

Operation:

Srcl is compared with src2 (srcl — src2).

Condition Codes:

The condition codes are based on the arithmetic comparison of the most significant pair of unequal srcl and src2 characters (srcl.byte — src2.byte)
N: set if dst << O; cleared otherwise
Z: set if dst = 0; cleared otherwise

V: set if there was arithmetic overflow, that 1is, srcl.byte<<7> and
src2.byte<<7> were different, and src2.byte<<7> was the same as bit <7>
of <<srcl.byte — src2.byte); cleared otherwise
|
C: cleared if there was a carry from the most significant bit of the result; set
otherwise

Op Codes:

CMPC
CMPCI

076044
076144

14-23

Description:

Each character of srcl is compared with the corresponding character of src2 by
examining the character strings from most significant to least significant characters. If the character strings are of unequal length, the shorter character string is
conceptually extended to the length of the longer character string with fill characters after its least significant character. The instruction terminates when the
first corresponding unequal characters are found or when both character strings
are exhausted. The condition codes reflect the last comparison, permitting the
unsigned branch instructions to test the result.

When the instruction starts, the operands must have been placed in the general reglsters the first
source character string descrlptor must bein RO—R1, the second source character string descriptor in
R2-R3, the fill character in R4<<7:0>, and R4<15:8> must be zero. The compare character format
is shown in Figure 14-23.

08
|

{

—

SRC1.DSCR

—
R1
]
|

|
I

|
|

|
I

|
{

|
1

|
|

]
{

|
{

|
|

1
{

|
{

|
l

|
I

—

SRC2.DSCR

—

R3
|
I

|
{

i
|

|
I

|
|

1
)

|
I

1
I

|
|

0
|

)
|

|
{

1
1

]

FILL

]

MR-6925

Figure 14-23

Compare Character Format

The instruction terminates with substring descriptors in RO—R1 and R2—R3 that represent the portion
of each source character string beginning with the most significant corresponding unequal characters.
RO-R1 contain a descriptor for the unequal portion of the original srcl string; R2—R3 contain a descriptor for the unequal portion of the original src2 string. A vacant character string descriptor indicates that the entire source character string was equal to the corresponding portion of the other
source character string, including extension by the fill character. The vacant character string descriptor’s address is one greater than that of the least significant character of the character string. The compare character format when the instruction terminates is shown in Figure 14-24.

]

SUB.SRC1.DSCR

—
R1
|
{

|
I

|
|

|
{

l
1

|
1

l
|

—

SUB.SRC2.DSCR

—

R3
|

{

0
|

{

FILL
|

]

MR-6926

Figure 14-24

Compare Character Termination Format

14-24

In-Line Form — CMPCI

The words following the op-code word in the instruction stream are a word address pointer to a 2-word
character string srcl descriptor, a word address pointer to a 2-word character string src2 descriptor,
and a word whose low-order half contains the fill character and whose high-order half must be zero.
RO-R6 are unchanged when the instruction is completed.
Notes:
1.
2.

The operation of this instruction is unaffected by any overlap of the source character strings.
If the srcl character string is vacant, the fill character will be compared with src2. If the src2
character string 1s vacant, the fill character will be compared with srcl. If both character strings

are vacant, the condition codes will indicate equality.
3.

CMPC - If an initial source character string descriptor is vacant, the resulting substring descriptor 1s the same as the original character string descriptor.

A test for success is BEQ); a test for failure is BNE.

When the instruction terminates, the condition codes will be set as if a CMPB instruction operated
on the most significant unequal characters. If both strings are initially vacant or are identical, the

condition codes will be set as if the last characters to be compared were identical. This results in
equality with N, V, and C cleared, and Z set.
6.

Both CMPC and CMPCI update the condition codes. CMPC returns substring descriptors.

14.7.4

CMPN/CMPP/CMPNI/CMPPI

Purpose:

Compare Decimal

Operation:

Srcl is compared with src2 (srcl — src2).

Condition Codes:

N: set 1f srcl << src2; cleared otherwise
Z: set if srcl = src2; cleared otherwise

V: cleared

C: cleared

Op Codes:

Description:

CMPN

076052

CMPP
CMPNI

076072
076152

CMPPI

076172

Srcl is arithmetically compared with src2, with the condition codes reflecting
the comparison. The signed branch instruction can be used to test the result.

When the instruction starts, the operands must have been placed in the general registers: the first
source descriptor must be in RO-R1, and the second source descriptor in R2-R3. The compare decimal
format is shown in Figure 14-25.

14-25

]

I
RO

—

SRC1.DSCR

—
R1

|
|

]
|

|
|

l
I

|
|

|
I

|
|

|
{

|
|

l
|

|
I
R2

‘

SRC2.DSCR

—
R3

]

MR-6927

Figure 14-25

Compare Decimal Format

When the instruction is completed, the source descriptor registers are cleared, as shown in Figure 14-

26.

—

——

+—

——p—

b—

—

+—

—-

MR-6928

Figure 14-26

Compare Decimal Format (Cleared)

In-Line Form — CMPNI and CMPPI

Each word address pointer following the op-code word in the instruction stream refers to a 2-word decimal string descriptor. RO-R6 are unchanged when the instruction is completed.
Note:

The operation of these instructions is unaffected by any overlap of the source strings, provided
that each source string is a valid representation of the specified data type.

14.7.5

CVTLN/CVTLP/CVTLNI/CVTLPI

Purpose:

Convert Long-to-Decimal

Operation:

decimal string

Condition Codes:

N: set if dst << O; cleared otherwise

long integer

Z: set if dst = O; cleared otherwise

V: set if dst cannot contain all significant digits of the result; cleared otherwise
C: cleared

Op Codes:

CVTLN

076057

CVTLP
CVTLNI

076077
076157
076177

CVTLPI

14-26

Description:

The source long integer is converted to a decimal string. The condition codes re-

flect the result stored in the destination decimal string, and whether all significant digits are stored.

Register Form — CVTLN and CVTLP
When the instruction starts, the operands must have been placed in the general registers: the destination descrlptor must bein RO——Rl and the source long integer in R2—R3. The convert long- to decimal
format1s shownin Figure 14-27.
15

00
|

{

[

RO
—

DST.DSCR

]

—

p—

—

——

—

—r—

R1
|
|

]
|

l
{

|
[

il
1

R2
—

SRC.LONG

]

R3
I

|
MR-6929

Figure 14-27

Convert Long-to-Decimal Format

When the instruction is completed, the source long-integer registers are cleared, as shownin Figure 1428.

—

DST.DSCR

—

p——

——

—

—p—

—

——

MR-6930

Figure 14-28

Convert Long-to-Decimal Format (Cleared)

In-Line Form — CVTLNI and CVTLPI
The words following the op-code word in the instruction stream are a word address pointer to a 2-word
decimal string descriptor, and a word address pointer to a 2-word long-integer source. RO—R6 are unchanged when the instruction is completed.
Notes:

In-line forms use a long integer oriented with the low-order portion in src.long, and the sign and
high-order portion in src.long + 2.

14-27

14.7.6

CVTNL/CVTPL/CVTNLI/CVTPLI

Purpose:

Convert Decimal-to-Long

Operation:

long integer

Condition Codes:

The condition codes are based on the long-integer destination and on the sign of

decimal string

the source decimal string.

N: set if long.integer << 0; cleared otherwise

Z: set if long.integer = 0; cleared otherwise

V: set if long.integer dst cannot correctly represent the 2’s complement form of
the result; cleared otherwise

# 0; cleared otherwise
C: set if src << 0 and long.integer
CVTNL
CVTPL
CVTNLI
CVTPLI

Op Codes:

076053
076073
076153
076173

The source decimal string is converted to a long integer. The condition codes reflect the result of the operation, and whether significant digits were not con-

Description:

verted.

CVTNL and CVTPL

When the instruction starts, the operand must have been placed in the general registers: the source
decimal string descriptor must be in the RO—R1. The convert decimal-to-long format is shown in Figure
14-29.

MR-6931

Figure 14-29

Convert Decimal-to-Long Format

When the instruction is completed, the source decimal string descriptors are cleared, and the destination long integer is returned in R2—R3, as shown in Figure 14-30.
00

—

f—

S—

—

———

—

_—

-t

(D)

—

DST.LONG
R3

]

|
MR-6932

Figure 14-30

Convert Decimal-to-Long Format (Cleared)

14-28

In-Line Form — CVITNLI and CVTPLI

The words following the op-code word in the instruction stream are a word address pointer to a 2-word

decimal string source descriptor, and a word address pointer to a 2-word long integer destination.
RO-R6 are unchanged when the instruction is completed.
Notes:
1.

order portion in R3.
2.

In-line forms use a long integer oriented with the low-order portion in dst.long, and the sign and

high-order portion in dst.long + 2.
3.

If the V bit is set, the contents of the long-integer destination are the least significant 32 bits of the
result.

A source whose value is +231 can be represented as a 32-bit binary integer. However, since the

destination is a 2’s complement long integer, the resulting condition codes will be: N set, Z

cleared, V set, and C cleared.

14.7.7

CVTNP/CVTPN/CVTNPI/CVTPNI

Purpose:
Operation:

Convert Decimal
CVTNP/CVTNPI
CVTPN/CVTPNI

Condition Codes:

packed string numeric string
numeric string packed string

N: set if dst << 0; cleared otherwise
Z: set if dst = O; cleared otherwise
V: set if dst cannot contain all significant digits of the result; cleared otherwise

C: cleared
Op Codes:

Description:

CVTNP

076055

CVTPN

076054

CVTNPI

076155

CVTPNI

076154

These instructions convert between numeric and packed decimal strings. The
source decimal string is converted and moved to the destination string. The con-

dition codes reflect the result of the operation, and whether all significant digits
were stored.
Register Form — CVTNP and CVTPN

When the instruction starts, the operands must have been placed in the general registers: the source

descriptor must be in RO-R1, and the destination descriptor in R2-R3. The convert decimal format is
shown in Figure 14-31.

14-29

[

]

—

SRC.DSCR

p—
R1

]

{

]

—

DST.DSCR

—
R3

]

!
MR-6933

Figure 14-31

Convert Decimal Format

When the instruction is completed, the source descriptor registers are cleared, as shown in Figure 1432.
15

|
|

]
|

|
|

0
|
I

|
|

]
|

|
|

]
|

]
I

|
|

]
I

]
|

R1
|
|

|
|

]
T

]
I

|
|

]
|

—

DST.DSCR

—
R3

]

Figure 14-32

]

Convert Decimal Format (Cleared)

In-Line Form — CVTNPI and CVTPNI

Each word address pointer following the op-code word in the instruction stream refers to a 2-word decimal string descriptor. RO—R6 are unchanged when the instruction is completed.
Notes:

1.
2.

The results of the instruction are unpredictable if the source and destination strings overlap.
These instructions use both a numeric and packed decimal string descriptor.

14.7.8

DIVP/DIVPI

Purpose:

Divide Decimal

Operation:

dst

Condition Codes:

N: set if dst << O; cleared otherwise

src2/srcl

Z: set if dst = O; cleared otherwise

V: set if dst cannot contain all si'nificant digits of the result or if srcl = O;
cleared otherwise

C: set if srcl = 0; cleared otherwise

Op Codes:

DIVP

076075

DIVPI

076175

14-30

Description:

Src2 is divided by srcl, and the quotient (fraction truncated) is stored in the destination string. The condition codes reflect the value stored in the destination
string, and whether all significant digits were stored.

When the instruction starts, the operands must have been placed in the general registers: the first
source descriptor must be in RO—R1, the second source descriptor in R2-R3, and the destination descriptor in R4-R5. The divide decimal format is shown in Figure 14-33.
15

[

—_

SRC1.DSCR

"""

R1
|
|

1
|

l
|

l
{

l
I

1
|

|
{

|
I

|
{

]
{

|
|

]
[

—

SRC2.DSCR

'——
R3

|
|

|
I

|
|

l
]

|
|

|
T

|
I

1
I

|
|

1
{

|
I

l
|

—

DST.DSCR

1
MR-6935

Figure 14-33

Divide Decimal Format

When the instruction is completed, the source descriptor registers are cleared, as shown in Figure 1434.

—

a—

—

——

—

—j—
—

—

—
—

—

s
——

—

.
—

——

R4
S

DST.DSCR

—

R5
]

]

]
MR-6936

Figure 14-34

Divide Decimal Format (Cleared)

In-Line Form -DIVPI

Each word address pointer following the op-code word in the instruction stream refers to a 2-word decimal string descriptor. RO—R6 are unchanged when the instruction is completed.

Notes:

The operation of these instructions is unaffected by any overlap of the source strings, provided
that each source string is a valid representation of the specified data type.

14-31

2.
3.

The results of the instruction are unpredictable if the source and destination strings overlap.
Duvision by zero will set the V and C bits. The destination string, and the N and Z condition code
bits will be unpredictable.

No numeric string divide instruction is provided.

14.7.9

LOCC/LOCCI

Purpose:

Locate Character

Operation:

Search source character string for a character.

Condition Codes:

The condition codes are based on the final contents of RO.
N: set if RO <<15> 1s set; cleared otherwise
Z: set if RO = 0; cleared otherwise
V: cleared

C: cleared
Op Codes:

LOCC
LOCCI

Description:

076040
076140

The source character string is searched from most significant to least significant
character until the first occurrence of the search character. A character string
descriptor is returned in RO—R1 that represents the portion of the source character string beginning with the located character. If the source character string
contains only characters not equal to the search character, the instructions return a vacant character string descriptor with an address one greater than that of
the least significant character of the source character string. The condition codes
reflect the result value in RO.

When the instruction starts, the operands must have been placed in the general registers: the source
character string descriptor must be in RO—R1, the search character in R4 <7:0>, and R4 <15:8>
must be zero. The register form of the locate character format is shown in Figure 14-35.

08
|

07
|

00
J

—

SRC.DSCR

—
R1
1

0
|

]

CHAR
|

]

MR-6937

Figure 14-35

Locate Character Format (Register Form)

14-32

When the instruction is completed, RO-R1 contain a character set descriptor that represents the substring of the source character string, beginning with the located character, as shown in Figure 14-36.
15

08
1

07
T

00
|

]

—

SUB.SRC.DSCR

——

0
|

]

CHAR
|

MR-6938

Figure 14-36

Locate Character Termination Format

In-Line Form — LOCCI

The words following the op-code word in the instruction stream are a word address pointer to a 2-word
character string source descriptor, and a word whose low-order half contains the search character and
whose high-order half must be zero. When the instruction is completed, RO-R1 contain a character
string descriptor that represents the substring of the source character string beginning with the located
character. R2-R6 are unchanged. The in-line form of the locate character format is shown in Figure
14-37.
15

{

00
|

—

SUB.SRC.DSCR

—
R1

]

1
MR-6939

Figure 14-37

Locate Character Format (In-Line)

Notes:

If the initial source character string descriptor is vacant, the instruction terminates with the condition codes indicating that no match was found. The original source character string descriptor is
returned in RO-R1.

A test for success is BNE; a test for failure is BEQ.

The condition codes will be set as if this instruction were followed by TST RO.

14.7.10

L2DR

Purpose:

Load Two Descriptors

Operation:

Load word pairs into RO—R1 and R2-R3.

Condition Codes:

: not affected
not affected
not affected
not affected

14-33

L2DR

Op Code:

07602r

This instruction augments the character and decimal string instructions by efficiently loading string descriptors into the general registers. A descriptor “alpha” is loaded into RO-R1; a second descriptor “beta” is loaded into R2-R3.
The address of the descriptors is determined by the addressing mode @ (Rr)+
where r is the low-order three bits of the op-code word. The address of the descriptor “alpha’ is derived by applying this addressing mode once; the address of
the descriptor “beta” is derived by applying this addressing mode a second time.
The addressing mode autoincrements the indicated register by two. The addressing mode computation is not affected by the descriptors loaded into the general
registers. The words containing the addresses of the descriptors are in consecutive words in memory; the descriptors themselves may be anywhere in memory. The condition codes are not affected.

Description:

When the instruction is completed, the “alpha’ descriptor is in RO—R1 and the
“beta” descriptor is in R2-R3. The load two descriptors format is shown in Figure 14-38.

BETA.DSCR

—

|
MR-6940

Figure 14-38
14.7.11

Load Two Descriptors Format

L3DR

Purpose:

LLoad Three Descriptors

Operation:

Load word pairs into RO—R1, R2-R3, and R4-R5.

Condition Codes:

Op Code:
Description:

- not affected
not affected
not affected
not affected
L3DR

07606t

This instruction augments the character and decimal string instructions by efficiently loading string descriptors into the general registers. A descriptor “alpha” is loaded into RO-R1; a second descriptor “beta” is loaded into R2-R3; a
third descriptor “gamma” is loaded into R4-R5. The address of the descriptors
is determined by the addressing mode @(Rr)+ where r is the low-order three
bits of the op-code word. The address of the descriptor “alpha” is derived by
applying this addressing mode once. The address of the descriptor “beta” 1s derived by applying this addressing mode a second time. The address of the de-

14-34

scriptor “gamma’’ is derived by applying this addressing mode a third time. The
addressing mode autoincrements the indicated register by two. The addressing
mode computation is not affected by the descriptors loaded into the general registers. The words containing the addresses of the descriptors are in consecutive
words in memory; the descriptors themselves may be anywhere in memory. The
condition codes are not affected.

When the instruction is completed, the “alpha” descriptor is in RO-R1, the
“beta” descriptor is in R2-R3, and the “gamma’ descriptor is in R4-R5. The
load three descriptors format is shown in Figure 14-39.
00

o—

——cy

a—

—

a—

—

a—

b—

—

p—

r—

—

—
p—

—

——

—
o

GAMMA.DSCR

]

|
MR-6941

Figure 14-39

14.7.12

Load Three Descriptors Format

MATC/MATCI

Purpose:

Match Character

Operation:

Search source character string for object character string.

Condition Codes:

The condition codes are based on the final contents of RO.

N: set if RO<<15> is set; cleared otherwise
Z: set if RO = 0; cleared otherwise
V: cleared
C: cleared
Op Codes:

Description:

MATC

076045

MATCI

076145

The source character string is searched from most significant to least significant
character for the first occurrence of the entire object character string. A character string descriptor is returned in RO-R1 that represents the portion of the original source character string, from the most significant character that completely
matches the object character string to the end of the source character string. If
the object character string does not completely match any portion of the source
character string, the character descriptor returned in RO-R1 is vacant, with an
address one greater than the least significant character in the source string. The

14-35

condition codes reflect the resulting value in RO. If the Z bit is cleared, the entire object character string was successfully matched with the source character
string; if the Z bit is set, the match failed.

When the instruction starts, the operands must have been placed in the general registers: the source
character string descriptor must be in RO—R1, and the object character string descriptor in R2-R3. The
register form of the match character format is shown in Figure 14-40.
15

{

,
—

SRC.DSCR

—

R1
1
|

1
|

|
I

1
|

|
|

|
i

|
|

1
|

]
|

|
{

|
|

R2
—

OBJ.DSCR

—

R3
1

{

]

{

|
MR-6942

Figure 14-40

Match Character Format (Register Form)

The instruction terminates with a character substring descriptor returned in RO-R1 that represents the
portion of the original source character string, beginning with the most significant character to com-

pletely match the object character string. The format of the match character after termination is shown
in Figure 14-41.

OBJ.DSCR

MR-6943

Figure 14-41

Match Character Termination Format

In-Line Form — MATCI

scriptor. The instruction terminates with a character substring descriptor returned in RO-R1 that represents the portion of the original source character string, beginning with the most significant character to

completely match the object character string. R2-R6 are unchanged when the instruction is completed.
The in-line form of the match character format is shown in Figure 14-42.

14-36

—

SUB.SRC.DSCR

—
R1

1
MR-6944

Figure 14-42

Match Character Format (In-Line)

Notes:

The operation of this instruction is unaffected by any overlap of the source and object character
strings.

A vacant object character string matches any nonvacant source character string. A vacant source
character string will not match any object character string. If the initial source character string
descriptor is vacant, the instruction terminates with the condition codes indicating that no match
was found. The original source character string descriptor is returned in RO-R1.

If the length of the object character string is greater than that of the source character string, no
match is found; RO-R1 and the condition codes will be updated.

A test for success is BNE; a test for failure is BEQ.

The condition codes will be set as if this instruction were followed by TST RO.

14.7.13

MOVC/MOVCI

Purpose:

Move Character

Operation:

dst

Condition Codes:

The condition codes are based on the arithmetic comparison of the initial character string lengths (result = src.len—dst.len).

src

N: set if result << 0; cleared otherwise
Z: set if result = 0; cleared otherwise

V: set if there was arithmetic overflow, that is, src.len<<15> and dst.len<<15>
were different, and dstlen<<15> was the same as bit <<15> of
(src.len—dst.len); cleared otherwise

C: cleared if there was a carry from the most significant bit of the result; set
otherwise

Op Codes:

MOVC
MOVCI

076030
076130

14-37

Description:

The character string specified by the source descriptor is moved into the area

specified by the destination descriptor. It is aligned by the most significant character. The condition codes reflect an arithmetic comparison of the original
source and destination lengths. If the source string is shorter than the destination
string, the fill character is used to complete the least significant part of the destination string. This is indicated by the C bit set. If the source string is longer than
the destination string, the least significant characters of the source string are not
moved. This is indicated by the Z and C bits’ being cleared. If the source and
destination strings are of equal length, all characters are moved with neither
truncation nor filling. This is indicated by the Z bit’s being set. The unsigned
branch instructions may test the result of the instruction.

When the instruction starts, the operands must have been placed in the general registers: the source
character string descriptor must be in RO—R
1, the destination character string descriptor in R2-R3, the
fill character in R4<7:0>, and R4<15:8> must be zero. The move character format is shown in
Figure 14-43.
15

—_—

SRC.DSCR

—
R1
|
|

|
|

]
|

|
{

|
|

|
I

|
|

|
I

i
|

|
|

|
{

|
|

l
|

—

DST.DSCR

—

R3
|
{

|
|

]

]
|

|
|

l
|

]
|

|
{

|
|

]

]
I

|
|

|
{

l
|

]

FILL

]

MR-69456

Figure 14-43

Move Character Format

When the instruction is completed, RO contains the number of unmoved source string characters, and
R1-R3 are cleared, as shown in Figure 14-44.
15

[

MAX(0,SRC.LEN-DST.LEN)
I

{

]

{

)

]

]
I

|
l

|
{

1
{

|
|

|
{

l
|

]

0
]
I

l
|

]
|

l
|

1
|

|
|

|
I

|
|

0
I

1
|

1
l

{

|
I

|
|

0
1

{

FILL
|

]

MR-6946

Figure 14-44

Move Character Format (Cleared)

In-Line Form — MOVCI

The words following the op-code word in the instruction stream are a word address pointer to a 2-word
character string source descriptor, a word address pointer to a 2-word character string destination descriptor, and a word whose low-order half contains the fill character and whose high-order half must be
zero. RO—R6 are unchanged when the instruction is completed.
14-38

Notes:

The operation of this instruction is unaffected by any overlap of the source and destination strings.
The result is equivalent to having read the entire source string before storing characters in the
destination.

If the source string is vacant, the fill character will be propagated through the destination string.
If the destination string is vacant, no characters will be moved. The condition codes will be up-

dated. MOVC will update the general registers.

MOVC — When the instruction terminates, RO is zero only if Z or C 1s set.

The condition codes will be set as if this instruction were preceded by CMP src.len, dst.len.

14.7.14

MOVRC/MOVRCI

Purpose:

Move Reverse-Justified Character

Operation:

dst

Condition Codes:

The condition codes are based on the arithmetic comparison of the initial charac-

reverse-justified src

ter strings (result = src.len—dst.len).

N: set if result << 0; cleared otherwise
Z: set if result = O; cleared otherwise

V: set if there was arithmetic overflow, that is, src.len<<15> and dst.len<<15>
were different, and dst.len<<15> was the same as bit <<15> of
(src.len—dst.len); cleared otherwise
C: cleared if there was a carry from the most significant bit of the result; set
otherwise

Op Codes:

Description:

MOVRC

076031

MOVRCI

076131

The character string specified by the source descriptor is moved into the area

specified by the destination descriptor. It is aligned by the least significant character. The condition codes reflect an arithmetic comparison of the original
source and destination lengths. If the source string is shorter than the destination
string, the fill character is used to complete the most significant part of the destination string. This is indicated by the C bit’s being set. If the source string is
longer than the destination string, the most significant characters of the source
string are not moved. This is indicated by the Z and C bits’ being cleared. If the
source and destination strings are of equal length, all characters are moved with
neither truncation nor filling. This is indicated by the Z bit’s being set. The unsigned branch instructions may test the result of the instruction.

When the instruction starts, the operands must have been placed in the general registers: the source
character string descriptor must be in RO-R
1, the destination character string descriptor in R2-R3, the
fill character in R4 <7:0>, and R4<15:8> must be zero. The move reverse-justified character format is shown in Figure 14-45.

14-39

08
|

]

SRC.DSCR

—
R1
]
|

1
i

|
|

1
|

]
1

|
1

1
|

|
1

|
|

i
|

|
|

l
|

—

DST.DSCR

—

R3
|

]

{

]

FILL

MR-6947

Figure 14-45

Move Reverse-Justified Character Format

When the instruction is completed, RO contains the number of unmoved source string characters, and
R1-R3 are cleared, as shown in Figure 14-46.
15

|
{

]
[

|
|

|
{

]
T

1
|

|
{

|
I

|
T

]
|

|
|

]
J

]
|

]
T

|
|

|
1

]
{

|
|

l
|

1
|

|
I

|
T

|
|

|
{

]
I

|
|

|
I

|
{

|
i

|
|

MAX(0,SRC.LEN-DST.LEN)
l
|

|
|
0

1
|

|
|

]
|

|
|

1
|

]
|

]
T
0

|
|

|
I

|
[

|
|

l
|

]
]

|
I

l
|
0

!
|

|
I

|
{

l
J

l
|

|
|

0
|

FILL
1

MR-6948

Figure 14-46

Move Reverse-Justified Character Format (Cleared)

In-Line Form — MOVRCI

The words following the op-code word in the instruction stream are a word address pointer to a 2-word
character string source descriptor, a word address pointer to a 2-word character string destination descriptor, and a word whose low-order half contains the fill character and whose high-order half must be
zero. RO-R6 are unchanged when the instruction is completed.
Notes:

If the source string is vacant, the fill character will be propagated through the destination string.
If the destination string is vacant, no characters will be moved. Condition codes will be updated.
MOVRC will update the general registers.

MOVRC - When the instruction terminates, RO is zero only if Z or C are set.

The condition codes will be set as if this instruction were preceded by CMP src.len, dst.len.

14-40

14.7.15

MOVTC/MOVTCI

Purpose:

Move Translated Character

Operation:

dst

Condition Codes:

The condition codes are based on the arithmetic comparison of the initial character string lengths (result = src.len—dst.len).

translated src

N: set if result << 0; cleared otherwise
Z: set if result = 0; cleared otherwise

Op Codes:

Description:

076032
076132

The character string specified by the source descriptor is translated and moved
into the area specified by the destination descriptor. It is aligned by the most
significant character. Translation is accomplished by using each source character as an 8-bit positive integer index into a 256-byte table, the address of which is
an operand of the instruction. The byte at the indexed location in the table is
stored in the destination string. The condition codes reflect an arithmetic comparison of the original source and destination lengths.
If the source string is shorter than the destination string, the untranslated fill
character is used to complete the least significant part of the destination string.
This is indicated by the C bit’s being set. If the source string is longer than the
destination string, the least significant characters of the source string are not
moved. This is indicated by the Z and C bits’ being cleared. If the source and
destination strings are of equal length, all characters are translated and moved
with neither truncation nor filling. This is indicated by the Z bit’s being set. The
unsigned branch instructions may test the result of the instruction.

When the instruction starts, the operands must have been placed in the general registers: the source
character string descriptor must be in RO-R1, the destination character string descriptor in R2-R3, the
fill character in R4<7:0>, R4<15:8> must be zero, and the translation table address in R5. The
move translated character format is shown in Figure 14-47.

14-41

SRC.DSCR

—
R1

|
|

|
I

l
1

|
|

|
{

|
|

|
I

|
|

i
|

|
i

|
|

|
|
R2

|
|

l
|

|
|

]
|

]
{
FILL
|
|

|
|

1
I

|
|

]

|
|

]
|

i
|

|
|

l
{

]
|

|
|
0
]
|

]
|

i
I

|
{

|
|

]

TABLE.ADR
|
|

}
{

]
I

|
|

]
|

|
|

]

R4
R5

DST.DSCR

—
R3

MR-6949

Move Translated Character Format

Figure 14-47

When the instruction is completed, RO contains the number of unmoved source string characters, and
R1-R3 are cleared, as shown in Figure 14-438.
15

|
i

|
|

1
|

|
I

i
|

|
1

|
|

|
{

1
|

|
|

|
I

|
|

]
|

|
I

i
{

|
i

|
1

1
|

|
|

|
1

1
|

i
|

|
|

|
{

|
|

1
|

|
|

1
1

|
|

]

TABLE.ADR
|
|

{

|
{

|
|

1
|

|
|

]
|

|
|

|
1

1
1

|
|

]
1

|
1

|
|

|
i

|
|

|
1

|
|

1
1

|
|

!
|

|
|

{

Figure 14-48

MAX(0,SRC.LEN-DST.LEN)

|
|

|
{
0
i
|

0
|
|
0

FILL

Move Translated Character Format (Cleared)

In-Line Form — MOVTCI

The words following the op-code word in the instruction stream are a word address pointer to a 2-word
character string source descriptor, a word address pointer to a 2-word character string destination descriptor, a word whose low-order half contains the fill character and whose high-order half must be
zero, and a word containing the address of the translation table. RO-R6 are unchanged when the instruction is completed.
Notes:

If the destination string overlaps the translation table in any way, the results of the instruction will
be unpredictable.

14-42

If the source string is vacant, the untranslated fill character will be propagated through the destination string. If the destination string is vacant, no characters will be moved. Condition codes will
be updated. MOVTC will update the general registers.

MOVTC — When the instruction terminates, RO is zero only if Z or C are set.

The condition codes will be set as if this instruction were preceded by CMP src.len, dst.len.

The effect of the instruction is unpredictable if the entire 256-byte translation table is not in readable memory.

14.7.16

MULP/MULPI

Purpose:

Multiply Decimal

Operation:

dst

Condition Codes:

N: set 1if dst << O; cleared otherwise

src2 * srcl

Z: set if dst = O; cleared otherwise
V: set if dst cannot contain all significant digits of the result; cleared otherwise

C: cleared
Op Codes:

MULP
MULPI

Description:

076074
076174

Srcl and src2 are multiplied, and the result is stored in the destination string.
The condition codes reflect the value stored in the destination string, and whether all significant digits were stored.

Form - MULP

When the instruction starts, the operands must have been placed in the general registers: the first
source descriptor must be in RO-R1, the second source descriptor in R2—R3, and the destination descriptor in R4-R5. The multiply decimal format is shown in Figure 14-49.

00
|

]

—

SRC1.DSCR

—

|
|

1
|

|
|

|
]

1
|

]
|

|
1

1
|

|
|

i
|

|
|

|
]

1
|

R2
|

SRC2.DSCR

—]

|
|

1
|

1
{

|
|

1
|

1
{

]
{

|
|

1
|

1
\

{
|

1
|

1
{

—

DST.DSCR

—

]

|
MR-6951

Figure 14-49

Multiply Decimal Format

14-43

When the instruction is complete, the source descriptor registers are cleared, as shown in Figure 14-50.
00

B
-

——

S—

wf—

R4
DST.DSCR

R5
|

|
MR-6952

Figure 14-50

Multiply Decimal Format (Cleared)

In-Line Form — MULPI

Each word address pointer following the op-code word in the instruction stream refers to a 2-word decimal string descriptor. RO—R6 are unchanged when the instruction is completed.
Notes:

The operation of these instructions is unaffected by any overlap of the source strings, provided
that each source string is a valid representation of the specified data type.

The results of the instruction are unpredictable if the source and destination strings overlap.

No numeric string multiply instruction is provided.

14.7.17

SCANC/SCANCI

Purpose:

Scan Character

Operation:

Search source character string for a member of the character set.

Condition Codes:

The condition codes are based on the final contents of RO.
N: set if RO<<15> 1s set; cleared otherwise
Z: set if RO = 0; cleared otherwise
V: cleared

C: cleared
Op Codes:

Description:

SCANC
SCANCI

076042
076142

The source character string is searched from most significant to least significant
character until the first occurrence of a character that is a member of the character set. A character string descriptor is returned in RO-R1 that represents the
portion of the source character string, beginning with the located member of the
character set. If the source character string contains only characters that are not

14-44

in the character set, the instructions return a vacant character string descriptor

with an address one greater than that of the least significant character of the
source character string. The condition codes reflect the resulting value in RO.

Register Form — SCANC
When the instruction starts, the operands must have been placed in the general registers: the source
character string descriptor must be in RO—R1, and the character set descriptor in R4-R5. The scan
character format is shown in Figure 14-51.
15

00
T

—

SRC.DSCR

—

R1
|

]

——

SET.DSCR

]

R5
l

]

Figure 14-51

]

Scan Character Format

When the instruction is completed, RO—R1 contain a character string descriptor that represents the
substring of the source character string, beginning with the most significant character that is a member
of the character set. The format of the scan character after termination is shown in Figure 14-52.
15

00
|

—

SUB.SRC.DSCR

—

R1
|

]

R4
—

SET.DSCR

]

R5
|

]

|
MR-6954

Figure 14-52

Scan Character Termination Format

In-Line Form —

SCANCI
The words following the op-code word in the instruction stream are a word address pointer to a 2-word

character string source descriptor, and a word address pointer to a 2-word character set descriptor.
When the instruction is completed, RO—R1 contain a character string descriptor that represents the
substring of the source character string, beginning with the most significant character that is a member

of the character set. R2—R6 are unchanged. The in-line format of the scan character is shown in Figure
14-53.

14-45

]

—

SUB.SRC.DSCR

—

]

1
MR-6955

Figure 14-53

Scan Character Format (In-Line)

Notes:

If the initial source character string descriptor is vacant, the instruction terminates with the condi-

tion codes indicating that no character in the set was found. The original source character string
descriptor is returned in RO—R1.

The source character string and character set table may overlap in any way.

A test for success is BNE; a test for failure i1s BEQ.

The condition codes will be set as if this instruction were followed by TST RO.

The effect of the instruction is unpredictable if the entire 256-byte character set table 1s not in
readable memory.

14.7.18

SKPC/SKPCI

Purpose:

Operation:

Skip Character

Search source character string until a character other than the search character
is found.

Condition Codes:

The condition codes are based on the final contents of RO.
N: set if RO<<15> is set; cleared otherwise
Z: set if RO = 0; cleared otherwise
V: cleared

C: cleared
Op Codes:

Description:

SKPC
SKPCI

076041
076141

The source character string is searched from most significant to least significant
character until the first occurrence of a character that is not the search character. A character string descriptor is returned in RO-R1 that represents the portion of the source character string, beginning with the most significant character
that was not equal to the search character. If the source character string contains
only characters equal to the search character, the instruction returns a vacant
character string descriptor with an address one greater than that of the least sig-

nificant character of the source character string. The condition codes reflect the
resulting value in RO.

14-46

Form — SKPC

When the instruction starts, the operands must have been placed in the general registers: the source
character string descriptor must be in RO-R1, the search character in R4<7:0>, and R4<15:8>

must be zero. The format of the register form of a skip character instruction is shown in Figure 14-54.
15

08
1

]

RO
—

SRC.DSCR

—

R1
i

]

0
]

]

Figure 14-54

]

CHAR
|

Skip Character Format (Register Form)

When the instruction is completed, RO—R1 contain a character string descriptor that represents the
substring of the source character string, beginning with the most significant character that was not
equal to the search character. The format of the skip character after termination is shown in Figure 14535.
15

08
]

07
T

00
T

RO
—

SUB.SRC.DSCR

—

R1
|

]

[

]

{

0
]

]

CHAR
|

]

MR-6957

Figure 14-55

Skip Character Termination Format

In-Line Form — SKPCI

whose high-order half must be zero. When the instruction is completed, RO—R1 contain a character
string descriptor that represents the substring of the source character string, beginning with the most
significant character that was not equal to the search character. R2-R6 are unchanged. The format of
the in-line form of the skip character is shown in Figure 14-56.

14-47

MR-6958

Figure 14-56

Skip Character Format (In-Line)

Notes:

If the initial source character string descriptor is vacant, the instruction terminates with the condition codes indicating the character string only contained search characters. The original source
character string descriptor is returned in RO-R1.

The condition codes will be set as if this instruction were followed by TST RO.

14.7.19

SPANC/SPANCI

Purpose:

Span Character

Operation:

Search source character string for a character that is not a member of the character set.

Condition Codes:

The condition codes are based on the final contents of RO.
N: set if RO<<15> is set; cleared otherwise
Z: set if RO = 0; cleared otherwise
V: cleared
C: cleared

SPANC

Op Codes:

Description:

SPANCI

076043
076143

The source character string is searched from most significant to least significant

character until the first occurrence of a character that is not a member of the
character set. A character string descriptor is returned in RO-R1 that represents
the portion of the source character string, beginning with the character that is
not a member of the character set. If the source character string contains only
characters that are in the character set, the instruction returns a vacant character string descriptor with an address one greater than that of the least significant
character of the source character string. The condition codes reflect the resulting
value of RO.

When the instruction starts, the operands must have been placed in the general registers: the source
character string descriptor must be in RO-R1, and the character set descriptor in R4-R5. The format
of the register form of the span character is shown in Figure 14-57.

14-48

—

SRC.DSCR

—

R1
|

]

{

R4
-

SET.DSCR

—

R5
|

1
MR-6959

Figure 14-57

Span Character Format (Register Form)

When the instruction is completed, RO—R1 contain a character string descriptor that represents the

substring of the source character string, beginning with the most significant character that is not a
member of the character set. The format of the span character after termination is shown in Figure 1458.
15

00
|

RO
—

SUB.SRC.DSCR

—

R1
|

]

R4
-

SET.DSCR

—

Re
1

]

l
MR-6960

Figure 14-58

Span Character Termination Format

In-Line Form — SPANCI

The words following the op-code word in the instruction stream are a word address pointer to a 2-word
character string source descriptor, and a word address pointer to a 2-word character set descriptor.
When the instruction is completed, RO—R1 contain a character string descriptor that represents the
substring of the source character string, beginning with the most significant character that is not a
member of the character set. R2-R6 are unchanged. The format of the in-line form of the span character is shown in Figure 14-59

MR-6961

Figure 14-59 Span Character Format (In-Line)
14-49

Notes:

If the initial source character string descriptor is vacant, the instruction terminates with the condition codes indicating that only characters in the set were found. The original source character
string descriptor is returned in RO-R1.

The source character string and character set table may overlap in any way.

The condition codes will be set as if this instruction were followed by TST RO.

The effect of the instruction is unpredictable if the entire 256-byte character set table is not in
readable memory.

14.7.20

SUBN/SUBP/SUBNI/SUBPI

Purpose:

Subtract Decimal

Operation:

dst

Condition Codes:

N: set if dst << O; cleared otherwise

src2 — srcl

Z: set if dst = 0O; cleared otherwise

V: set if dst cannot contain all significant digits of the result; cleared otherwise
C: cleared
Op Codes:

SUBN
SUBP
SUBNI
SUBPI

Description:

076051
076071
076151
076171

Srcl is subtracted from src2, and the result is stored in the destination string.
The condition codes reflect the value stored in the destination string, and whether all significant digits were stored.

Register Form — SUBN and SUBP
When the instruction starts, the operands must have been placed in the general registers: the first
source descriptor must be in RO-R1, the second source descriptor in R2—-R3, and the destination descriptor in R4-R5. The subtract decimal format is shown in Figure 14-60.
15

00
{

SRC1.DSCR

"—'
R1
|
{

|
|

1
|

Il
|

|
|

|
{

i
|

|
|

]
|

—

SRC2.DSCR

—

R3
|

I
R4

]

{

]

{

—

DST.DSCR

—

Rb5
|

]

1
MR-6962

Figure 14-60

Subtract Decimal Format

14-50

—

When the instruction is completed, the source descriptor registers are cleared, as shown in Figure 1461.

15
RO

R2
R3

]

|
{

|
|

|
1

]
|

|
|

|
0
|
|
0
|
|

|
|

]
|

|
|

|
1

|
|

|
]

|
|

{
|

|
|

|
)

1
|

|
|

|
i

|
)

|
|

|
1

|
||

|
1

|
|

|
1

|
|

1
|

|
1

1
|

|
|

i
]

|
|

]
i

1
|

|
|

|
1

|
|

1
|

0
0
|
I

—

DST.DSCR

—

{

]

|
MR-6963

Figure 14-61
In-Line Form —

Subtract Decimal Format (Cleared)

SUBNI and SUBPI

Each word address pointer that follows the op-code word in the instruction stream refers to a 2-word
decimal string descriptor. RO-R6 are unchanged when the instruction is completed.

Notes:

The operation of these instructions is unaffected by any overlap of the source strings, provided

Source strings may overlap the destination string only if all corresponding digits of the strings are

that each source string is a valid representation of the specified data type.
in coincident bytes in memory.

14-51

APPENDIX A

GENERAL REFERENCE INFORMATION

A.1

SUMMARY OF KDF11 INSTRUCTIONS

WORD FORMAT
00

BINARY-OCTAL
REPRESENTATION

Name

Mode

0
1

2
3
4
5
6
7

]

auto-increment
auto-incr deferred
auto-decrement
auto-decr deferred
index
index deferred

]

Symbolic

Description

(R) is operand [ex. R2 = 9%2]

MODE

ADDRESSING MODES

(R) is address

(R)

(R) is adrs; (R) +(1 or 2)
(R) is adrs of adrs; (R) 42
(R) —(1 or 2); is adrs
(R) —2; (R) is adrs of adrs

(R)+
@ (R)+
—(R)
@ —(R)

(R) 4+ X is adrs
(R) + X is adrs of adrs

X(R)
@ X(R)

PROGRAM COUNTER ADDRESSING

Reg =7/
7

MODE

]

]
MR 2887

2
3
6

immediate
absolute
relative

relative deferred

#n
@ #A
A

operand n follows instr
address A follows instr
instr adrs 4+ 4 4+ X is adrs

instr adrs + 4 4 X is adrs of adrs

LEGEND

Op Codes
B

— O for word/1 for byte

SS
DD
R

— source field (6 bits)
= destination field (6 bits)
— gen register (3 bits),

XXX

= offset (8 bits), +127

Oto7

to —128

Operations
()

— contents of

<«

— becomes

s
d
r

— contents of source
— contents of destination
— contents of register

Op Codes

Operations

— number (3 bits)

— relative address

= number (6 bits)

— register definition

Boolean

Condition Codes

— AND

— inclusive OR

—

— exclusive OR

— cleared

— NOT

— set

— conditionally set/cleared

SINGLE OPERAND:
15

— not affected

OPR dst
1

OP CODE

SSOR DD

Mnemonic

Op Code

Instruction

dst Result

General

CLR(B)

@ 050DD

clear

COM(B)

H 051DD

complement (1's)

INC(B)

H 052DD

increment

d+ 1
d—1

DEC(B)

® 053DD

decrement

NEG(B)

H 054DD

negate (2's compl)

—d

TST(B)

H® 057DD

test

o)
:
*
o)

Rotate & Shift

ROR(B)

H 060DD

ROL(B)

rotate right

® 061DD

rotate left

- C, d

C,d<

ASR(B)

® 062DD

arith shift right

ASL(B)

d/2

arith shift left

SWAB

0003DD

swap bytes

Multiple Precision
ADC(B)

B 055DD

add carry

SBC(B)

d+4+ C

H 056DD

subtract carry

d—C

sign extend

Oor—1

SXT

0067DD

—

Processor Status (PS) Operators
MFPS

1067DD

move byte from PS

MTPS

d < PS

1064SS

move byte to PS

PS «<s

DOUBLE OPERAND:
15

12
T

OPR src, dst

OPR src, R or OPR R, dst

06
!

[

OP CODE

A-2

Mnemonic

Op Code

Instruction

Operation

B 1SSDD
B 2SSDD
06SSDD
16SSDD

move
comapare
add
subtract

bit test (AND)
bit clear
bit set (OR)
exclusive (OR)

General

MOV(B)
CMP(B)
ADD
SUB

d<s
s —d
d<s+4d
d<d-—s

0]
woE
#%

Logical

BIT(B)
BIC(B)
BIS(B)
XOR

s
d
d<(—~s)
d
d<svd
d<rvd

0
o)
o)
0

r<rxs
r<r/s

EIS

MUL
DIV
ASH
ASHC

070RSS
071RSS
072RSS
073RSS

multiply
divide
shift arithmetically
arith shift combined

BRANCH:

B—Ilocation

*
x

If condition is satisfied
Branch to location,

New PC < Updated PC + (2 x offset)

adrs of brinstr 4+ 2
15

BASE CODE

XXX

Op Code = Base Code + XXX
Mne-

Base

monic

Code

Instruction

BR
BNE
BEQ
BPL
BMI
BVC

000400
001000
001400
100000
100400
102000

branch (unconditional)
br if not equal (to 0)
br if equal (to 0)
branch if plus
branch if minus
br if overflow is clear

BVS

102400

br if overflow is set

Branch Condition

Branches

A-3

(always)
= 0
=0
-+
—

Z/ =0
Z =1
N =0
N =1
V =0
V =1

Mne-

Base

monic

Code

BCC
BCS

103000
103400

Instruction

Branch Condition
C =0
C =1

br if carry is clear
br if carry is set

Signed Conditional Branches

BGE

002000

br if greater or

Nvv =0

BLT
BGT
BLE

002400
003000
003400

br if less than (0O)
br if greater than (0O)
br if less or equal (to0)

<0
> 0
<O

NvV=1
Zv(NvV)=0
Zv(NvV)=1

>
<
=
<

CvZ=0
CvZ=1
C =0
C =1

equal (to 0)

Unsigned Conditional Branches

BHI
BLOS
BHIS
BLO

101000
101400
103000
103400

branch if higher
branch if lower or same
branch if higher or same
branch if lower

JUMP & SUBROUTINE
Mne-

monic
JMP

JSR

RTS

Op Code
0001DD

O04RDD

O0020R

O064NN
O77RNN

PC <« dst

jump to subroutine 1

return from

subroutine

MARK
SOB

Notes

Instruction
jump

mark
subtract 1 & br
(if £ 0)

use same R
aid in subr return
(R) — 1, then if (R) £ O:
PC « Updated PC —
(2 x NN)

TRAP & INTERRUPT:
Mne-

monic

Op Code

EMT

104000
to 104377
104400

TRAP

Instruction

Notes

emulator trap
(not for general use)
trap

PC at 30, PS at 32
PC at 34, PS at 36

to 104777

BPT
IOT

000003
000004

breakpoint trap
input/output trap

PC at 14, PS at 16
PC at 20, PS at 22

RTI
RTT

000002
000006

return from interrupt
return from interrupt

inhibit T bit trap

MISCELLANEOUS:
Mnemonic

Op Code

Instruction

HALT

000000

halt

WAIT

000001

wait for interrupt

RESET

000005

reset external bus

NOP

000240

(no operation)

MFPI

0065SS

MTPI

0066DD

MFPD

1065SS

move from previous data space

MTPD

1066DD

move to previous data space

move from previous instr space
move to previous instr space

CONDITION CODE OPERATORS:
15
!

OP CODE BASE=000240

O = CLEAR SELECTED COND. CODE BITS
1 = SET SELECTED COND. CODE BITS

Mnemonic

Op Code

CLC

000241

clear C

CLV

000242

clear V

CLZ

000244

clear Z

CLN

000250

CCC

000257

SEC

000261

set C

SEV

000262

set V

SEZ

000264

set Z

-1

SEN

000270

set N

SCC

000277

set all cc bits

Instruction

clear N

—-—

clear all cc bits

-1

OPTIONAL FLOATING POINT:
Data Formats
F FORMAT, FLOATING POINT SINGLE PRECISION
15

FRACTION

150

MEMORY +0

EXP
i

FRACT
1

A-5

22 16
i

C
-

OPTIONAL FLOATING POINT:

Data Formats (Cont)
D FORMAT, FLOATING POINT DOUBLE PRECISION

FRACTION -.15:0

{

FRACTION -.31:16 |

FRACTION- 47:32

15
MEMORY +0

EXP
|

FRACT- 54 48 1

S = SIGN OF FRACTION

EXP = EXPONENT IN EXCESS 200 NOTATION, RESTRICTED TO 1 TO 377 OCTAL
FOR NON-VANISHING NUMBERS.

FRACTION = 23 BITS IN F FORMAT, 55 BITS IN D FORMAT + ONE HIDDEN

BIT (NORMALIZATION). THE BINARY RADIXPOINT ISTO THE LEFT.
M

| FORMAT, INTEGER SINGLE PRECISION

NUMBER+ 15:0":
1

]

)

L FORMAT,K DOUBLE PRECISION INTEGER LONG

MEMORY +0

NUMBER- 30:16

S
i

{

NUMBER- 15:0.-

+2
1

WHERE S

SIGN OF NUMBER

NUMBER

15BITSIN I FORMAT, 31 BITS IN L FORMAT.

1606

Addressing Formats

DOUBLE OPERAND ADDRESSING

]

FSRC,FDST,SRC,DST

FOC

OoC
)

]

SINGLE OPERAND ADDRESSING

00
FSRC, FDST, SRC, DST

0]0
)

OPCODE

FOC

FLOATING OPCODE

FLOATING POINT ACCUMULATOR (ACO AC3)

FSRC AND FDST USE FPP ADDRESSING MODES

SPC AND DST USE CPU ADDRESSING MODES
MR 3608

Mnemonic

Op Code

Instruction

Notes

CFCC

170000

copy fl cond codes

SETF

170001

set floating mode

SETI

170002

set integer mode

FL<0

SETD

170011

set fl dbl mode

« 1
FD

SETL

170012

set long integer mode

1
FL<

LDFPS

1701 src

load FPP prog status

STFPS

1702 dst

store FPP prog status

STST

1703 dst

store (exc codes & adrs)

FD <0

CLRF, CLRD

1704 fdst

clear floating/double

TSTF, TSTD

1705 fdst

test fl/dbl

ABSF, ABSD

1706 fdst

make absolute fl/dbl

fdst < fdst

NEGF, NEGD

1707 fdst

negate fl/dbl

fdst <« —fdst

MULF, MULD

171 (AC) fsrc

multiply fl/dbl

AC < AC x fsrc

MODF, MODD

171 (AC + 4) fsrc

multiply & integerize

ADDF,

fdst < O

AC < AC + fsrc

172 (AC) fsrc

add fl/dbl

LDF, LDD

172 (AC + 4) fsrc

load fl/dbl

AC « fsrc

SUBF, SUBD

173 (AC) fsrc

subtract fl/dbl

AC < AC - fsrc

ADDD

CMPF, CMPD

173 (AC + 4) fsrc

compare fl/dbl (to AC)

STF,STD

174 (AC) fdst

store fl/dbl

fdst < AC

DIVF, DIVD

174 (AC + 4) fsrc

divide fl/dbl

AC < AC/fsrc

STEXP

175 (AC) dst

STCFI,STCFL
STCDI, STCDL

175 (AC + 4) dst { dbl to int or long int

STCFD, STCDF

176 (AC) fdst

store & convert (dbl-fl)

176 (AC + 4) src

load exponent

LDEXP

LDCIF, LDCIF
LDCLF, LDCLD
LDCDF, LDCFD

store exponent

store & convert fl or

}

177 (AC) src

177 (AC + 4) fsrc

load & convert int or
long int to fl or dbl

load & convert (dbl-fl)

A-T7

A.2

NUMERICAL OP CODE LIST
Mne-

Op Code

monic

Mne-

Op Code

Mne-

monic

Op Code
00

00 00 00

HALT

04 XXX

00 00 01

WAIT

10 XXX

00 00 02

RTI

BNE

14 XXX

BEQ

monic

70 00
(unused)

00 00 03

BPT

XXX

00 00 04

10T

BGE

24 XXX

00 00 05

RESET

BLT

00 30 XXX

RTT

00 34 XXX
00 4R DD

JSR

CLR

JMP

COM

RTS

00 52

1R SS

DIV

NEG

ASH

ADC

07 2R SS
07 3R SS

ASHC

SBC

07 4R DD

XOR

00 57

TST

07 50 OR
1R

FADD
FSUB

07 50 2R
07 50 3R

FMUL
FDIV

00 06

00 00 07

00 00 77
01 DD
00 02 OR

00 02

10
(reserved)

00 02 27
00 02 40

MOV

BLE

CMP

BIT

BIC

BIS

06 SS

ADD

INC

07 OR SS

MUL

DEC

07 50
00

ROR

ROL

cond

00 62

ASR

codes

00 63

ASL

00 64

MARK

00 66 SS

MFPI

00 66 DD

MTPi

00 67 DD

SXT

00 02 77
DD

BGT

NOP

00 02 41

00 03

MFPT

00 00 10 } (unused)

SWAB

7R NN

SOB

XXX

BPL

10 04 XXX

BMI

10 44 00
TRAP

10 47 77

10 XXX

BHI

14 XXX

BLOS

XXX

BVC

24 XXX

BVS

XXX

BCC,

DECB

34 XXX

BHIS
BCS,
BLO

10 54

NEGB

10 40 00
EMT

10 43

CLRB

COMB

INCB

07 50 40

(reserved)
07 67 77

10 63 DD
10 64 SS

ASLB

10 65

MFPD

DD MTPD

MTPS

10 67

MFPS

MOVB

12 SS

CMPB

BITB

BICB

ADCB

14 SS

SBCB

BISB

10 57

TSTB

16 SS

SUB

RORB

17 00 00

ROLB

10 62

ASRB

A-8

floating
17

point

A.3 PROCESSOR STATUS WORD (PS) 17777776
14

}

PRIORTY

RESERVED
-

LEVEL
|

TRACE

NEGATIVE

PREVIOUS MEMORY

MANAGEMENT MODE

‘

ZERO

OVERFLOW

CURR ENT MEMORY

CARRY

MANAGEMENT MODE
SUSPENDED
INSTRUCTION

MR 3638

ABSOLUTE LOADER

BOOTSTRAP LOADER
Address

Contents | Address

Contents

Starting Address: — 500
Memory Size:
4K
017
8K
037
12K
057
16K
077

— 744
— 746
— 750
— 752
— 754
— 756

016 701
000 026
012702
000 352
000 211
105 711

000 002
— 400

20K

117

— 760

100 376

24K

137

— 762

116 162

28K

157

(or larger)

— 764
—766
— 770
— 772
— 774
— 776

005 267
177 756
000 765

177 560 (TTY)
or 177 550 (PC11)

—

773 000 Paper Tape Bootstrap
773 100 Disk/DECtape Bootstrap
773 200 Card Reader Bootstrap
773 300 Cassette Bootstrap

773 400 Floppy Disk Bootstrap

A-9

A5 DEVICE REGISTER ADDRESSES AND VECTORS

Device

Interrupt

Address

Vector

Console Terminal

Input Control/Status

RCSR

17777560

Input Buffer

RBUF

17777562

Output Control/Status

XCSR

17777564

Output Buffer

XBUF

17777566

2nd SLU Terminal

Input Control/Status

RCSR

17776500*

| 300

17776540** | 340
Input Buffer

RBUF

Output Control/Status

XCSR

17776502*
17776542%*

17776504*

| 304

17776544** | 344

Output Buffer

XBUF

17776506*
17776546**

KDF11-B Boot/Diagnostic
Page Control

PCR

Read Control

RWR

17777522

Lights Switches

CDR

17777524

17777520

Unused

17777526

Boot/Diagnostic ROM

17773000—
17774000

Line Frequency Clock

LKS

17777546

CSR

17774400

RLV12 Disk

160

Status
Bus Address

BAR

17774402

Disk Address

DAR

17774404

Multipurpose

MPR

17774406

Bus Address Extension

BAE

17777546

Printer Status

LPS

17777514

Printer Buffer

LPB

17777516

LPV11 High Speed Printer

200

*J13 and J12 must be ungrounded.
**J13 must be ungrounded and J12 must be grounded.
MMU Status Registers
MMU

100

Address

Status Register 0 | SRO

17777572

Status Register 1

| SR1

17777574

Status Register 2

| SR2

17777576

Status Register 3

| SR3

17772516

PAR/PDR Address Assignments

User Active Pagei Registers

Kernel Active Page Registers

No.

PAR

PDR

No.

PAR

PDR

0
1
2
3
4
5
6
7

772340
772342
772344
772346
772350
772352
772354
772356

772300
772302
772304
772306
772310
772312
772314
772316

0
1
2
3
4
5
6
7

777640
777642
777644
777646
777650
777652
777654
777656

777600
777602
777604
777606
777610
777612
777614
777616

RESERVED TRAP and INTERRUPT VECTORS
Vector

Description

000

(Reserved)

010
014

lllegal and Reserved Instruction
BPT Instruction and T Bit
|OT Instruction
Power Fail
EMT Instruction
TRAP Instruction
Console Input Device
Console Output Device

004

020

024
030
034

060

064

Bus Timeout and lIllegal Instructions (e.g., JMP RO)
(Odd Address Trap Not Implemented on LSI-11/23)

100

External Event Line Interrupt

114

Parity Error

160

RLV12

200

LPV 11

244

KEF11-A (Floating Point)

250

Memory Management Abort

264

RXV11, RXV21

300

Floating Vectors start here

A-11

A.6 CONSOLE ODT COMMANDS*

Command

Symbol

Description

Slash

Prints the contents of a specified
location.

Carriage Return

<CR>

Line Feed

<LF>

Closes an open location.
Closes an open location and then
opens the next contiguous
location.

Internal Register

$orR

Opens a specific processor register.

Opens the PS, must follow an ““$"”

Designator

Processor Status
Word Designator

or "R’ command.

Starts program execution.

Proceed

Resumes execution of a program.

Binary Dump

Control-Shift-S

Manufacturing use only.

Reserved for DIGITAL use.

* All addresses in ODT must be 18-bit addresses between O and 777776.

A.7

7-BIT ASCIl CODE

Octal
Code

Char

Octal
Code

Char

Octal
Code

Char

Octal
Code

Char

000

NUL

040

100

140

DC1
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM

061
062
063
064
065
066
067
070
071

1
2
3
4
5
6
7
8
9

121
122
123
124
125
126
127
130
131

Q
R
S
T
U
V
wW
X
Y

161
162
163
164
165
166
167
170
171

q
r
S
t
u
Vv
W
X
y

ESC

073

001
002
003
004
005
006
007
010
011
012
013
014
015
016
017
020

SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
S|
DLE

032

SUB

021
022
023
024
025
026
027
030
031

033

034

035

036
037

RS
UusS

041
042
043
044
054
046
047
050
051
052
053
054
055
056
057
060

072

074
075

076
077

|
“
H#
$
%
&
‘
(
)
d
+
’
:
/
0

<
—
>
?

101
102
103
104
105
106
107
110
111
112
113
114
115
116
117
120

132

A
B
C
D
E
F
G
H
I
J
K
L
M
N
@)
P

141
142
143
144
145
146
147
150
151
152
153
154
155
156
157
160

172

a
b
C
d
e
f
g
h
i
j
K
I
m
n
0
o)

AN
Jor ¢

173

{

134
135

[

136
137

A
— Or «

176
177

—~
DEL

133

174
175

|
}

APPENDIX B

INSTRUCTION TIMING

B.1

GENERAL INFORMATION

The KDF11-BA CPU executes PDP-11 instructions as a series of microcode cycles. A data fetch consists of an address cycle and a bus DIN cycle. A data write consists of an address cycle and a bus
DOUT cycle. An instruction fetch consists of an address cycle, a bus DIN cycle, and a non-1/0O cycle.
The execution of an instruction typically consists of one or more non-1/O cycles. Floating-point instructions also include interchip DIN and DOUT cycles that move data between the DATA and MMU
chips. The execution time for an instruction depends on the type of the instruction, the modes of addressing used, the type of memory referenced and whether the memory management unit is enabled or
disabled.

Each microcode cycle consists of an integral number of clock pulses, one occurring every 75 ns. The
number of clock pulses and the time required to complete the most common microcode cycles are listed
in Table B-1. The time required for bus DIN or DOUT microcode cycles accessing either the memory
management registers (MMU DIN or DOUT) or the KDF11-BA on-board peripherals (IDAL bus DIN
or DOUT) are listed in Table B-2. The KDF11-BA module’s peripherals include the bootstrap and diagnostic ROMs, the line clock logic, and the serial-line units.

The KDF11-BA detects RRPLY assertion within 112.5 ns of the time it asserts TDIN. (This
is typical for peripherals that assert TRPLY as soon as they receive RDIN asserted.)

The KDFll-BA detects RRPLY assertion within 337.5 ns of the time it asserts TSYNC.

The KDF11-BA detects RRPLY assertion within 150 ns of the time it asserts TDOUT. (This
is typical for peripherals and memories that assert TRPLY as soon as they receive RDOUT
asserted. This includes the MSV11-P parity memory.)

(This is typical for the MSV11-P parity memory.)

Table B-1

Type of Cycle

KDF11-BA Common Microcode Cycle Times

Address (no relocation)
Address (relocation)
LSI-11 bus DIN (1)
LSI-11 bus DIN (2)
LSI-11 bus DOUT (3)
Interchip DIN
Interchip DOUT
Non-I /O (micro-NOP)

B-1

Clock Pulses

Time (ns)

5
8
10
11
11
5
5
4

375
600
750
825
825
375
375
300

Table B-2

KDF11-BA Peripheral Microcode Cycle Times

Type of Cycle

Clock Pulses

Time (ns)

IDAL bus DIN

600

IDAL bus DOUT

600

MMU DIN

525

MMU DOUT

525

B.2

BASIC INSTRUCTION TIMING

The source, destination, and fetch/execute times for the KDF11-BA basic instruction set appear below.
KDF11-BA instruction times are calculated using the following equation:
Instruction Time = Basic Time + Source Time + Destination Time

(Basic Time = Fetch Time + Execute Time)
The basic, source, and destination times were calculated from the microcode cycle times listed in Table
B-1. LSI-11 bus DIN (2) and DOUT (3) times of 825 ns were used for the MSV11-P parity memory,
which has its specifications listed in Table B-3.

The instruction execution times for systems with memory management enabled or disabled are listed in
Tables B-4 through B-7.

Table B-3

Bus Cycle

MSV11-P Parity Memory

Access Time (ns)

Cycle Time (ns)

Typical

Maximum

Typical

Maximum

DATI

240

260

560

590

DATO(B)

120

610

640

DATIO(B)

660

690

1175

1210

Table B-4

Source Address Times
Time (us) with

Source

Memory

Memory Management

Instructions

Mode

Cycles

Enabled

Disabled

ADD, SUB

MOV (B), CMP(B)

1.425

1.200

BIS(B), BIC(B)

1.425

1.200
2.400

BIT(B)

2.850

1.725

1.500

3.150

2.700

3.150

2.700

4.575

3.900

Table B-4

Source Address Times (Cont)
Time (us) with

Source

Memory

Memory Management

Instructions

Mode

Cycles

Enabled

Disabled

MUL,DIV
ASH, ASHC
MFPI, MFPD
MTPS

0
1
2
3

0
1
1
2

1.275
1.725
1.725
2.850

1.275
1.450
1.450
2.400

4
5
6
7

Table B-5

1
2
2
3

1.725
3.150
3.150
4.575

1.500
2.700
2.700
3.900

Destination Address Times
Time (us) with

Source

Memory

Memory Management

Instructions

Mode

Cycles

Enabled

Disabled

MOYV(B), CLR(B)
SXT, MFPS
MTPI, MTPD

0
1
2
3

0
1
1
2

0
2.025
2.025
3.150

0
1.800
1.800
2.700

4
5
6
7

1
2
2
3

2.025 ,
3.450
3.450
4.875

1.950
3.000
3.000
4.500

0
1
2
3
4
5

0
1
1
2
1
2

0
1.725
1.725
2.850
1.725
3.150

0
1.500
1.500
2.400
1.500
2.700

4.575

3.900

0
1
2
3
4
5
6
7

0
1
|
2
1
2
2
3

0
2.850
2.850
4.275
2.850
4.575
4.575
6.000

0
2.625
2.625
3.825
2.625
4.125
4.125
5.325

CMP(B), BIT(B)
TST(B)

ADD, SUB
INC(B), DEC(B)
COM(B), NEG(B)
ROR(B), ROL(B)
ASR(B), ASL(B)
BIS(B), BIC(B)
ADC, SBC
XOR, SWAB

3.150

B-3

2.700

Table B-6

Basic (Fetch and Execute) Times
Time (us) with

Memory

Memory Management

Instructions

Cycles

Enabled

Disabled

MOU, CMP, BIT,
BIC, BIS, ADD,

2.025

1.800

SUB, SXT, CLR,
TST, COM, INC,
DEC, NEG, ADC,
SBC, ROR, ROL,

ASR, ASL,

SWAB, MFPS
MTPS

3.600

MFPI, MFPD

3.375

4.050

MTPI, MTPD

3.600

4.725

4.275

SOB (NO BRANCH)

SOB (BRANCH)

2.625

2.400

2.925

2.700

ALL BRANCH

2.025

1.800

CLN, CLE, CLYV,
CLC, SEN, SEZ,

2.925

2.700

SEV, SEC, CCC,

RTS

3.750

MARK

3.300

5.325

4.875

RTI

6.225

RTT

5.550

7.500

6.825

IOT, BPT

EMT, TRAP

10.500

9.375

9.525

WAIT

8.850

3.375

3.150

MUL

33.300

DIV

33.075

49.650

49.425

ASH

ASHC

24.825

24.600

46.050

45.825

NOTES
l.

The instruction times for MUL, DIV, ASH, and ASHC are operand-dependent and could be less than the values given

above.

The instruction times for the RESET and HALT instructions are mode /option-dependent.

B-4

Table B-7

Jump Instruction Times

Dest.
Mode

Memory
Cycles

Time (us) with

Instruction
JMP

JSR
|

B.3

Memory Management
Enabled
Disabled

2.325

2.100

2.625

2.400

3.450

3.000

2.625

2.400

3.750

3.300

3.750

3.300

5.175

4.500

1
2

2
2

4.350
4.650

3.900
4.200

5.475

4.800

4.650

4.200

5.100

5.775

5.100

7.200

6.300

DMA AND INTERRUPT LATENCIES

DMA latency 1s the time required for the first DMA device to obtain bus mastership after it asserts a
direct memory access request (BDMR L). The DMA latency is 1.35 us (maximum). The maximum

DMA latency was calculated for a relocated address cycle followed by a DOUT cycle. The processor
disables DMA grant (BDMGO L) from the end of the address cycle phase time for four 75 ns intervals
after the DOUT cycle phase time.
Interrupts (BR requests) are acknowledged by the processor at the end of the current instruction. Inter-

rupt latency is defined as the time required by the KDF11-BA to assert an interrupt acknowledge
(BIAKO L) after it receives an interrupt request. Interrupt service time is defined as the time required
by the processor to fetch the first service routine instruction after the assertion of BIAKO L. The interrupt latency time and the interrupt service time must be added to obtain the total time from the reception of the interrupt request to the fetch of the first service routine instruction. The specifications for
interrupt latency and interrupt service times are as follows.
Interrupt Latency

5.475 uws, typical [MOV X(R7),R0]
12.600 us, maximum (except EIS)

54.225 us, maximum (including EIS)

Interrupt Service

8.625 us (memory management Off)
9.750 us (memory management On)
NOTE
1.

Interrupt and DMA latencies assume a KDF11BA with memory management enabled and using

MSV11-P memory.
2.

The maximum interrupt latencies were calcu-

lated

for ADD

@X(R7),

@X(R7).
B-5

@Y(R7),

and

DIV

APPENDIX C

LSI-11, KDF11/PDP-11 PROGRAMMING AND

OPERATIONAL DIFFERENCES

The table on the following pages compares the programming and operational features of the KDF11BA, KDF11-AA, LSI-11, and PDP-11 processors.

ACTIVITY

ISI-11|

OPR%R, (R)+ or OPR%R,

KDF11PDP-11/
AAand BA | 04
|34 | 05/10 | 15/20 | 35/40 | 45

and —(R) using the same regis-

ter as both source and destination: contents of R are
incremented (or decremented)
by 2 before being used as the
source operand.
OPR%R, (R)+ or OPR%R,
and —(R) using the same register as both register and destination: initial contents of R are
used as the source operand.
2.

OPR%R, @(R)+ or OPR%R,
and @—(R) using the same

destination: contents of R are

incremented (or decremented)
by 2 before being used as the
source operand.
OPR%R, @(R)+ or OPR%R, | X

and @—(R) using the same
register as both source and

destination: initial contents

of R are used as the source
operand.

OPR PC, X(R); OPR PC,
@X(R); OPR PC, @A; OPR
PC, A: location A will contain
the PC of OPR + 4.

ACTIVITY

OPR PC, X(R); OPR PC,
@X(R), OPR PC, A; OPR PC,
@A location A will contain the
PC of OPR + 2.
JMP (R)+ or JSR reg, (R)+:
contents of R are incremented
by 2, then used as the new PC
address.
JMP (R)+ or JSR reg, (R) +:
initial contents of R are used

as the new PC.

JMP %R or JSR reg, %R traps
to 4 (illegal instruction).
JMP %R or JSR reg, %R traps
to 10 (illegal instruction).
SWAB does not change V.
SWAB clears V.
Register addresses
(177700-177717) are valid
program addresses when used

by CPU.

dress by the CPU. Can be addressed under console
operation. Note addresses can-

not be addressed under console
for LSI-11 or KDF11.
Basic instructions noted in
PDP-11 Processor Handbook.

SOB, MARK, RTT, SXT
instructions.

ASH, ASHC, DIV, MUL
XOR instruction.

LSI-11

KDF11-

PDP-11/

AA and BA

05/10

15/20

35/40

ACTIVITY

The external option KE11-A
provides MUL, DIV, and
SHIFT operation in the same
data format.
The KE11-E (expansion in-

struction set) provides the
instructions MUL, DIV, ASH,
and ASHC. These new instructions are PDP-11/45compatible.
The KE11-F adds unique

stack-ordered floating-point
instructions: FADD, FSUB,
FMUL, FDIV.

The KEV-11 adds EIS/FIS
instructions.
SPL instruction.

Power-fail during RESET instruction is not recognized until after the instruction is
finished (70 ms). RESET instruction consists of a 70 ms
pause with INIT occurring
during the first 20 ms.
Power-fail immediately ends
the RESET instruction and
traps if an INIT 1s in progress.
A minimum INIT of 1 us occurs if instruction aborted.
Power-fail acts the same as in
the PDP-11/45 (22 ms with
about 300 ns minimum).
Power-fail during RESET
fetch is fatal with no powerdown sequence.
RESET instruction consists of
10 us of INIT followed by a

90 us pause. Power-fail is not
recognized until the instruc-

tion is complete.

LSI-11

KDF11-

PDP-11/

AA and BA

|34

05/10

15/20

35/40

ACTIVITY

10.

LSI-11

KDF11-

PDP-11/

AA and BA

04 | 34

No RTT instruction.

If RTT sets the T bit, the T bit
trap occurs after the instruction following RTT.
11.

If RTI sets the T bit, T bit trap
is acknowledged after the instruction following RTT1.

If RTI sets the T bit, T bit trap
is acknowledged immediately
following RTI.
12.

If an interrupt occurs during
an instruction that has the T
bit set, the T bit trap 1s acknowledged before the
interrupt.

If an interrupt occurs during
an instruction and the T bit 1s
set, the interrupt is acknowledged before the T bit trap.
13.

T bit trap will sequence out of
WAIT instruction.
T bit trap will not sequence out
of WAIT instruction. Waits
until an interrupt.

14.

Explicit reference (direct access) to PS can load T bit. Console can also load T bit.

Only implicit references (RTI,
RTT, traps and interrupts) can
load T bit. Console cannot load
T bit.
15.

Odd address/nonexistent references using the SP cause a

HALT. This is a case of double
bus error with the second error
occurring in the trap servicing
the first error. Odd address
trap not in LSI-11 or F11.

C-4

05/10

15/20

35/40

ACTIVITY

Odd address/nonexistent refer-

LSI-11

KDF11-

PDP-11/

AA and BA

04 | 34

ences using the stack pointer

cause a fatal trap. On bus error
in trap service, new stack cre-

ated at 0/2.
16.

The first instruction in an in-

terrupt routine will not be executed if another interrupt
occurs at a higher priority level
than assumed by the first
interrupt.
The first instruction in an in-

terrupt service is guaranteed to
be executed.
17.

Eight general-purpose
registers.

Sixteen general-purpose
registers.
18.

PS address, 177776, not imple-

mented; must use new instruc-

tions, MTPS (move to PS) and
MFPS (move from PS).
PS address implemented,
MTPS and MFPS not
implemented.
PS address and MTPS and
MFPS implemented.
19.

Only one interrupt level (BR4)
exists.
Four interrupt levels exist.

20.

Stack overflow 1s not
implemented.
Stack overflow below 400 1s
implemented.
Red- and yellow-zone stack

overflow is implemented.

C-5

05/10

15/20

35/40

ACTIVITY

21.

Odd address trap is not

LSI-11

KDF11-

PDP-11/

AA and BA

04 | 34

implemented.
Odd address trap is
implemented.
22.

FMUL and FDIV instructions
implicitly use R6 (one push
and pop); hence R6 must be
set up correctly.
FMUL and FDIV instructions
do not implicitly use R6.

23.

Due to their execution time,

EIS instructions can abort be-

cause of a device interrupt.
EIS instructions do not abort
because of a device interrupt.
24.

Due to their execution time,

FIS instructions can abort be-

cause of a device interrupt.
25.

EIS instructions do a DATIP
and DATO bus sequence when

fetching a source operand.
EIS instructions do a DATI
bus sequence when fetching a
source operand.
26.

MOV instruction just does a
DATO bus sequence for the
last memory cycle.

MOV instruction does a
DATIP and DATO bus sequence for the last memory
cycle.
27.

If the PC contains a nonexistent memory address and a bus
error occurs, the PC will have
been incremented.

C-6

05/10

15/20

35/40

ACTIVITY

LSI-11

KDF11-

PDP-11/

AA and BA

If the PC contains nonexistent
memory address and a bus error occurs, the PC will be
unchanged.
28.

If a register contains nonexistent memory address in mode 2
and a bus error occurs, the register will be incremented.
Same as above but the register
i1s unchanged.

29.

If a register contains an odd
value in mode 2 and a bus error occurs, the register will be
incremented.

If a register contains an odd
value in mode 2 and a bus error
occurs, the register will be
unchanged.
30.

Condition codes restored to
original values after FIS interrupt abort (EIS does not abort
on the PDP-35/40).
Condition codes that are restored after EIS/FIS interrupt
abort are indeterminate.

31.

Op codes 075040-075377 unconditionally trap to 10 as reserved op codes.
If the KEV-11 option 1s present, op codes 075040-075377
perform a memory read using
the register specified by the
low-order three bits as a
pointer. If the register contents
are a nonexistent address, a
trap-to-4 occurs. If the register
contents are an existent address, a trap-to-10 occurs if
user microcode is not present.
If no KEV-11 option is present,
a trap-to-10 occurs.

C-7

05/10

15/20

35/40

ACTIVITY

32.

Op codes 210-217 trap to 10

LSI-11

KDF11-

PDP-11/

AA and BA

|34

as reserved op codes.
Op codes 210-217 are used as
maintenance instructions.
33.

Op codes 075040-075777 trap
to 10 as reserved op codes.
Only if KEV-11 option is present, op codes 075040-075377

can be used as escapes to user
microcode. Op codes
075400-075777 can also be
used.

Used as escapes to user microcode, and KEV-11 option

need not be present. If no user
microcode exists, a trap-to-10
occurs.

34.

Op codes 170000-177777 trap
to 10 as reserved instructions.
Op codes 170000-177777 are
implemented as floating-point
instructions.

Op codes 170000-177777 can

be used as escapes to user
microcode. If no user microcode exists, a trap-to-10
OCCurs.

C-8

05/10

15/20

35/40

APPENDIX D

KDF11-BA BACKPLANE PIN ASSIGNMENT COMPARISON

The KDF11-BA module (M8189) uses four bused spare lines that were reserved for future expansion to
implement 22-bit addressing. The KDF11-BA also uses two spare pins for the RUN light signal and one
spare pin for battery backup control of the power-up code 1 jumper signal (PUP CD1J L). The KDF11BA uses the AM2 pin in slot 1 for the input of a microcycle enable signal (MCENB H), which may be
externally negated to disable the master clock control for testing purposes. Pin AM2 in slots 2 through
9 is used by peripheral option modules as an input pin for the BIAKI signal. Two pairs of CD slot
signals can be connected together to provide continuity for the interrupt acknowledge (BIAK) and bus
grant (BDMG) signals when the KDF11-BA is used in an LSI-11/LSI-11 backplane.
Certain pins of the A and B backplane rows are used for different functions by the KDFI11-BA,
KDF11-AA, KD11-HA, and KD11-F processors. A comparison of the backplane pin assignment for the
processors is shown in Table D-1. The assignment of the remaining backplane pins of rows A and B are
identical for all four processors. The backplane pin assignment for rows C and D of the KDFI11-BA
module is listed in Table D-2.

Table D-1
Bus

Backplane

Backplane Pin Assignment Comparison (Rows A and B)
Backplane Pin Utilization

KDF11-AA

FD11-HA

KD11-F

Signal Name

KDF11-BA

AAl
ABI
BP1
ACl1
ADI1

BIRQS5 L
BIRQ6 L
BIRQ7 L BDALI16 L
BDAL17 L

BIRQS L
BIRQ6 L
BIRQ7 L
BDALI16 L
BDAL17 L

BIRQS5 L
BIRQ6 L
BIRQ7 L
BDALI16 L
BDAL17 L

Not used
Not used
Not used
Not used
Not used

AE]
AF1
AHI1
AK1
ALl

SSPAREI
SSPARE?2
SSPARE3
MSPAREA
MSPAREA

Not used
SRUN L
SRUN L
Not used
Not used

Single Step
SRUN L
SRUN L
Not used
Not used

STOP L
SRUN L
SRUN L
MTOE L
GND

Not used
SRUN L
Not used
Not used
Not used

AM?2
AR]1
AR2
BCl1
BD1

BIAKI L
BREF L
BDMGI L
SSPAREA4
SSPARES

MCENB H
BCTRL L
Not used
BDALI18 L
BDALI19 L

MMU STRH
Not used
Not used
BREF L
Not used*
Not used*
UBMAP L
Not used
Not used
MMU DALISH | SCLK3 H
Not used
MMU DALI9H | SWMIBI8H | Not used

*Not used on the KDF11-AA and KD11-HA but terminated in the inactive state to prevent problems with older memories.

Table D-1

Backplane Pin Assignment Comparison (Rows A and B) (Cont)

Bus

Backplane

Backplane Pin Utilization

Signal Name

KDF11-BA

KDF11-AA

BEI

SSPAREG6

BDAL20 L

BF1

SSPARE7

BDAL21 L

BH]1

SSPARES

PUP CD1JL|

BK1

MSPAREB

Not used

BL1

MSPAREB

Not used

Table D-2
Bus

Utilization | Pin

Bus

FD11-HA

KD11-F

KDF11-BA Backplane Pin Assignment (Rows C and D)
Pin

Bus

Utilization

DA2

CAl

CA2

CBl1
CCl1
CDl1

—
-

CB2
CC2
CD2

—
GND
—

DBI
DCl1
DD1

~
—
—

DB2
DC2
DD2

—
GND
-

CEl

—
—

CE2
CF2

DE]1
DF1

—
—

DE2
DF2

—

DA1

CF1
CH1

CH?2

DHI1

CJ1

—

DH?2

CJ2

—

DJ1

—

DJ2

DL1

—

DL2

DMI1

DM2

—

CKl1

—

CK2

—

CL1

CL2

CM1

CM?2

BIAKI L

CNI1
CP1
CR1
CS1
CTl1
CUl1
CVl1

—
-~
—
~
GND
—

CN?2
CP2
CR2
CS2
CT2
- CU2
CV2

BIAKO L
—
BDMGI L
BDMGO L
~
—

DK1

DNI1
DP1
DRI1
DS1
DT1
DUI1
DV1

D-2

—

—
—
GND
~
-

DK2

DN2
DP2
DR2
DS2
DT2
DU2
DV2

—

—
—
~
~
—
-

APPENDIX E

MICRO-ODT DIFFERENCES

A number of differences exist between the ways the LSI-11 (KD11-F), LSI-11/2 (KD11-HA), LSI11/23 (KDF11-A) and LSI-11/23B (KDF11-BA) CPUs interpret the same console ODT commands.
Notably, the LSI-11/23 and LSI-11/23B do not support the L command. The following list describes
these differences.

In most cases, if you are using ODT from a console terminal, your program will not be affected. However, the slight difference in response to some commands may impact users who have programmed a
host computer to emulate a console terminal to down-line load programs to the LSI-11.

LSI-11 and LSI-11/2
(KD11-F and KD11-HA)
1.

All characters that are input are echoed except when in the APT command mode,
where no characters are echoed. An echoed
line feed <LF> will be followed by a carriage return <CR> only (no second

L.SI-11/23 and LSI-11/23B
(KDF11-AA and KDF11-BA)
1.

All characters that are input in any command mode except the APT mode are echoed except the octal codes 0, 2, 10, 12, 200,
202, 210, and 212. This suppresses echoing
<LF>s, nulls (0), STXs (2), and BSx (10)

< LF> or padding nulls). This method cre-

because an automatic <CR> and <LF>

ates a potential timing problem with a TTY
ASR33, which types the next character before the printhead has completely returned.
2.

When an address location is open, another
location can be opened without explicitly
closing the first location. For example,
1000/123456 2000/054321

follow. In the APT command mode, no input characters are echoed.

An address location must be explicitly
closed by a <CR> or <LF> command
before another is opened or else an error (?)
will occur and any open location will automatically be closed without its contents being altered.

“7” will open the previous location.

“T”

illegal

and

micro-ODT

prints

“@” 1s illegal and
7<CR><LF>@.

micro-ODT

prints

“?”

micro-ODT

prints

7<CR><LF>@.

“@” will open a location using indirect addressing.

“«" will open a location using relative ad-

dressing.

illegal

and

T<CR><LF>a@.

LSI-11/23 and LSI-11/23B

LSI-11 and LSI-11/2

(KDF11-AA and KDF11-BA)

(KD11-F and KD11-HA)

“M” will print the contents of an internal

CPU register.

“M”

illegal

and

micro-ODT

prints

T<CR><LF>@.

Rubout (ASCII

177) will delete the last

Rubout

character typed in.

illegal

and micro-ODT prints

T<CR><LF>a@.

“L” 1s the boot loader command that will

“L”

load the absolute loader from the specified
device.

T<CR><LF>@.

illegal

and

micro-ODT

prints

Control-shift-S command mode (ASCII 23)

accepts 2 bytes forming a 16-bit address

accepts 2 bytes forming an 18-bit address

and dumps 10 bytes in binary format. The 2

with

input bytes are not echoed.

dumps 10 bytes in binary format. The 2 in-

bits

<<17:16>

always

zeros

and

put bytes are not echoed.
/

10.

11.

Up to a 16-bit address and 16-bit data may

Up to an 18-bit address and 18-bit data may

be entered. Leading zeros are assumed.

Incrementing <LF>, the address 177776

11.

results in the address 000000.

Incrementing

<<LF>,

the

addresses

177776, 377776, 577776 and 777776 result

in the addresses 000000, 200000, 400000,
and 600000, respectively. That is, the upper
2 bits of the 18-bit address are not affected;

they must be explicitly set.
12.

Incrementing a PDP-11 register from R7

12,

prints out “R8” and the contents of RO.

13.

The

I/O

page

the

address

group

13.

17XXXX.

14.

The micro-ODT mode can be entered from

Incrementing a PDP-11 register from R7

prints out “R0O” and the contents of RO.

The

[/O

T7XXXX,

page

where

14.

address
bits

group

<<17:12>

The micro-ODT mode can be entered from

the following sources.

A PDP-11 HALT instruction.

the

address
must be explicit ones.

A PDP-11 HALT instruction when in

kernel mode; the POKL line is low and
b.

A double bus error.

the HALT jumper option strap is present.

An asserted HALT line.

A power-up option.

LSI-11 and LSI-11/2
(KD11-F and KD11-HA)

L.SI-11/23 and LSI-11/23B
(KDF11-AA and KDF11-BA)
d.

A power-up option.

An asserted HALT line caused by a
DLVI11 framing error.

An asserted HALT line caused by a

A micro-ODT bus error.

DLV11 framing error.

A micro-ODT bus error.

(See NOTE*)

A memory refresh bus error.
An interrupt vector timeout.
L.

15.

A nonexistent micro PC address.

A carriage return <CR> 1is echoed and
followed by a line feed <LF> only.

15.

A carriage return <CR> is echoed and
followed by another <<CR> and a line feed
<LF>.

16.

“H” causes the LSI-11/23 to execute microcode routine that, in effect, does nothing.¥

16.

No “H” command.

*14.

The micro-ODT mode can be entered on the LSI-11/23B from the following sources.

t16.

A PDP-11 HALT instruction when in kernel mode, if the HALT TRAP jumper (J16 to J18) is not installed.

An asserted HALT line.

Power-up mode option 1 selected.

“H” causes the LSI-11/23B to echo the “H” and print a prompt character rather than a “?”, which is the invalid character response. No other operation is performed.

E-3

APPENDIX F

FUNCTIONAL DESCRIPTION OF BUS SIGNALS

The following Table F-1 offers a functional description of the extended LSI-11 bus signals.

Table F-1

Extended LSI-11 Bus Signal Functions

Bus | Signal
Pin

| Mnemonic

Signal Function

AAl | BIRQS5S L

Interrupt request priority level 5.

AB1 | BIRQ6 L

Interrupt request priority level 6.

AC1 | BDALI6 L

Address line 16 during addressing protocol; parity control line during data
transfer protocol.

ADI1 | BDALI7 L

Address line 17 during addressing protocol; parity control line during data

transfer protocol.

AE1 | SSPAREI
alternate
+ 5B

Special spare — Not assigned or bused in DIGITAL cable or backplane assemblies; available for user connection. This pin may be used optionally for +5 V
battery (+5B) backup power to keep critical circuits alive during power failures. A jumper is required on LSI-11 bus options to open (disconnect) the
+ 5B circuit in systems that use this line as SSPARE]L.

AF1

| SSPARE2

SRUN

Special spare — Not assigned or bused in DIGITAL cable or backplane assem-

blies; available for user interconnection. In the highest priority device slot, the
processor may use this pin for a signal to indicate its RUN state.

AH1 |SSPARE3

Special spare — Not assigned nor bused in DIGITAL cable or backplane as-

semblies; available for user interconnection.
AJl

|GND

Ground — System signal and dc return.

AK1 |MSPAREA

Maintenance spare — Normally connected together on the backplane at each

ALl

option location (not a slot-to-slot bused connection).

|MSPAREB

AMI1 | GND
ANI1 |BDMRL

Ground — System signal and dc return.
Direct memory access (DMA) request — Device asserts this signal to request

bus mastership.

F-1

Table F-1

Extended LSI-11 Bus Signal Functions (Cont)

Bus | Signal

Pin | Minemonic

APl | BHALT L
AR1 | BREF L

Signal Function

Processor halt — When BHALT L is asserted, the processor responds by going

into its halt state (generally console ODT mode.)

Memory refresh — Used during refresh protocol to override memory bank se-

lection decoding and to cause all banks to be selected.

Asserted or negated with BRPLY by block mode slave devices to indicate to
the bus master whether the slave can accept another block mode DIN or
DOUT transfer.

AS1 | +5Bor +12B|
battery

412 or +5 Vdc battery backup power to keep critical circuits alive during
power failures. This signal is not bused to BS1 in all DIGITAL backplanes. A
jumper is required on all LSI-11 bus options to open (disconnect) the backup
circuit from the bus in systems that use this line at the alternate voltage.

ATI1 | GND

Ground — Systems signal and dc return.

AUI1 | PSPAREI

Power spare 1 (not assigned a function; not recommended for use) — If a backplane is busing — 12 V (on pin BB2) and a module is accidentally inserted upside down in the backplane, —12 Vdc appears on pin AUI. If AUI 1s unused
on the module, no damage will occur.

AV1 | +5B

+5 V battery backup power — For keeping critical circuits alive during power
failures.

BA1 | BDCOK H

DC power OK (power supply) — Generated signal that is asserted when there
is sufficient dc voltage available to sustain reliable system operation.

BB1 | BPOK H

AC power OK — Asserted by the power supply when primary power is normal.
When negated during processor operation, a power-fail trap sequence 1s initiated.

BC1 | SSPARE 4
BD1 | SSPARE 5
BE1 | SSPARE 6
BF1 | SSPARE 7

Special spares <<7:4> in standard LSI-11 bus systems (16- and 18-address-bit
systems). Not assigned or bused in standard LSI-11 bus cable or backplane
assemblies. These pins are used to bus address lines <<21:18> in extended
L.SI-11 cable and backplane assemblies.
CAUTION
These pins may have been used as test points in some DIGITAL or customer
options. These options must be modified or designated incompatible with extended LSI-11 bus backplanes.

BHI1 | SSPARE 38

Special spare — Not assigned or bused in DIGITAL cable or backplane assemblies; available for user interconnection.

BJ1 | GND

Ground — System signal ground and dc return.

Table F-1

Extended LSI-11 Bus Signal Functions (Cont)

Bus | Signal

| Mnemonic

Signal Function

BK1 | MSPAREB
BL1 | MSPAREB

Maintenance spares — Normally connected together on the backplane at each
option location (not a bused connection).

BM1|

Ground — System signal ground and dc return.

GND

BN1 | BSACK L

This signal is asserted by a DMA device in response to the processor’s
BDMGO L signal, indicating that the DMA device is accepting bus mastership. Device remains bus master until it negates BSACK L.

BP1 | BIRQ 7 L

Interrupt request priority level 7.

BR1 | BEVNT L

External event interrupt request — The processor latches the leading edge and
arbitrates as an interrupt. A typical use of this signal is a line-time clock interrupt.

BS1 | +12B

+12 Vdc battery backup power (not bused to AS1 in all DIGITAL backplanes).

BT1 | GND

Ground — System signal ground and dc return.

BUI1 | PSPARE2

Power spare 2 (not assigned a function, not recommended for use) — If a backplane is busing —12 V (on pin AB2) and a module is accidentally inserted
upside down in the backplane, —12 Vdc appears on pin BUI. If BUI is
unused on the module, no damage will occur.

BVI1 | +5

+5 V power — Normal +5 Vdc system power.

AA2 | +5

+5 V power — Normal +5 Vdc system power.

AB2 | —12

—12 V Power — — 12 Vdc (optional) power for devices requiring this voltage.

AC2 | GND

Ground — System signal and dc return.

AD2 | +12

+12 V power — Normal +12 Vdc system power.

AE2 | BDOUT L

Data output — When asserted, BDOUT implies that valid data is available on
BDAL <15:0> L and that an output transfer, with respect to the bus master
device, is taking place. BDOUT L 1s deskewed with respect to data on the bus.

AF2 | BRPLY L

Reply — BRPLY L is asserted in response to BDIN L or BDOUT L and during IAK transaction. It is generated by a slave device to indicate that it will
place its data on the BDAL bus or that it will accept data from the bus, according to the appropriate protocol.

F-3

Table F-1

Extended LSI-11 Bus Signal Functions (Cont)

Bus

Signal

Mnemonic

Signal Function

AH?2

BDIN L

Data input — BDIN L is used for two types of bus operation:
1.

When asserted during BSYNC L time, BDIN L implies an input transfer
with respect to the current bus master and requires a response (BRPLY
L) from the addressed slave.

The interrupt fielding processor initiates interrupt service by asserting
TDIN L followed by TIACK L.

AJ2

BSYNC L

Synchronize — BSYNC L is asserted by the bus master device to indicate that
it has placed an address on the bus. The transfer is in process until BSYNC L
is negated. In block mode BSYNC L remains asserted until the last transfer
cycle is completed.

AK?2

BWTBT L

Write /byte — BWTBT L is used in two ways to control a bus cycle:

Itisasserted during the address portion of a cycle to indicate that an output cycle is to follow DATO or DATO(B) rather than an input cycle.

It 1s asserted during the data portion of a DATO(B) or DATIO(B) bus
cycle, to indicate a byte rather than a word transfer is to take place.

AL?2

BIRQ4 L

Interrupt request priority level 4.

AM?2

BIAKI L

AN?2

BIAKO L

Interrupt acknowledge — In accordance with interrupt protocol, the processor
asserts BIAKO L to acknowledge an interrupt. The bus transmits this to
BIAKI L of the next priority device (electrically closest to the processor). This
device accepts the interrupt acknowledge if:
1.

The device requested the bus by asserting an interrupt, BIRQX L.

The device had the highest priority interrupt request on the bus at the
time of the preceding BDIN L assertion.

If both these conditions are not met, the device asserts BIAKO L to the next
device on the bus. This process continues in a daisy-chain fashion until the device with the highest interrupt priority receives the interrupt acknowledge
(IAK) signal and proceeds with interrupt protocol.
AP2

BBS7 L

Bank 7 select — When the bus master asserts TADDR, 1t asserts BBS7 L to
reference the 1/O page (including that portion of the 1/O page reserved for
nonexistent memory). The address on BDAL <<12:0> L when BBS7 L is asserted is the address within the I1/O page.

F-4

Table F-1

Extended LSI-11 Bus Signal Functions (Cont)

Bus | Signal

| Mnemonic

AR2 | BDMGI L
AS2 | DBMGO L

Signal Function

Direct memory access grant — The bus arbitrator asserts this signal to grant
bus mastership to a requesting device, according to bus mastership protocol.

The signal is passed in a daisy-chain from the arbitrator (as BDMGO L)
through the bus to BDMGI L of the next priority device (electrically closest
device on the bus). This device accepts the grant only if it requested to be bus
master (by asserting BDMR L). If it did not, the device passes the grant (asserts BDMGO L) to the next device on the bus. This process continues until
the requesting device acknowledges the grant by asserting BSACK L after
BRPLY L and BSYNC L are both negated.
AT2 | BINIT L

AU2 | BDALO L

Initialize — This signal is used for system reset. All devices on the bus are to
return to a known, initial state; that is, registers are reset to zero, all bus drivers are disabled, and logic is reset to state 0, ready to be addressed for operations. Exceptions should be completely documented in programming and engineering specifications for the device.

Data/address line 00 — Specifies high or low byte during address for
DATO(B) and DATIO(B) cycles.

AV2 | BDAL1 L

Data/address line O1.

BA2 | +5

+5 Vdc power.

BB2 | —12

—12 Vdc power (optional, not required for DIGITAL LSI-11 or F11 hardware options).

BC2 | GND

Power supply return.

BD2 | +12

+12 Vdc power.

BE2 | BDAL2 L

Data/address line 02.

BF2 | BDAL3 L

Data/address line 03.

BH2 | BDAL4 L

Data/address line 04.

BJ2 | BDALS L

Data/address line 05.

BK2 | BDAL6 L

Data/address line 06.

BL2 | BDAL7 L

Data/address line 07.

BM2 | BDALS L

Data/address line 08.

F-5

Table F-1

Extended LSI-11 Bus Signal Functions (Cont)

Bus | Signal

Pin | Mnemonic

Signal Function

BN2 | BDALY9 L

Data/address line 09.

BP2 | BDALIO L

Data/address line 10.

BR2 | BDALII1 L

Data/address line 11.

BS2 | BDAL12 L

Data/address line 12.

BT2 | BDALI3 L

Data/address line 13.

BU2 | BDALI14 L

Data/address line 14.

BV2 | BDALI5S L

Data/address line 15.

F-6

KDF11-BA CPU Module User’s Guide

Reader’s Comments

EK-KDFEB-UG-001

Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our
publications.

What is your general reaction to this manual? In your judgment is it complete, accurate, well organized, well
written, etc.? Is it easy to use?

What features are most useful?

What faults or errors have you found in the manual?

Does this manual satisfy the need you think it was intended to satisfy?

Why?

Does it satisfy your needs?

Please send me the current copy of the Technical Documentation Catalog, which contains information on
the remainder of DIGITAL’s technical documentation.

Name

Street

Title

City

Company

State/Country

Department

Zip

Additional copies of this document are available from:
Digital Equipment Corporation
444 Whitney Street
Northboro, MA 01532

Attention:

Printing and Circulating Service (NR2/M15)
Customer Services Section

Order No. _ EK-KDFEB-UG

Do Not Tear — Fold Here and Staple

No Postage
Necessary
if Mailed in the

FIRST CLASS

PERMIT NO.33

MAYNARD, MA.

POSTAGE WILL BE PAID BY ADDRESSEE

Digital Equipment Corporation
Educational Services Development and Publishing

200 Forest Street (MR1-2/T17)
Marlboro, MA 01752

i
r

BUSINESS REPLY MAIL

United States

Digital Equipment Corporation - Bedford, MA 01730

—