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EK-KDF11-UG-PR2

January 1979

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Document:	KDF11-AA User's Guide
Order Number:	EK-KDF11-UG
Revision:	PR2
Pages:	365
Original Filename:

OCR Text

PRELIMINARY

KDF11-AA USER’S GUIDE

PRELIMINARY

EK-KDF11-UG-PR2

KDF11-AA
USER’'S GUIDE

digital equipment corporation ¢ marlboro, massachusetts

Preliminary Edition, January 1979

Revised Preliminary, March 1979

Copyright © 1979 by Digital Equipment Corporation
The material in this manual is for informational purposes and
is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for
any errors which may appear in this manual.

Printed in U.S
A,

The following are trademarks of Digital Equipment
Corporation,

Maynard. Massachusetts:

DIGITAL

DECsystem-10

MASSBUS

DEC

DECSYSTEM-20

OMNIBUS
0S/8

PDP

DIBOL

DECUS

EDUSYSTEM

RSTS

UNIBUS

VAX

RSX

VMS

IAS

6580 15

PREFACE

This

manual

versions

The

describes

the

KDF1ll

the

KDFll-AA

processor.

The

following

exist.

KDF11-AA

processor

with

2.
3.

KDF11-AB
KDF11-AC

processor
processor

with MMU and floating point
without MMU or floating point

LSI-11/23

processor

versions and can
in system boxes.

memory management

consists

ordered

one

conjunction

iii

of
with

unit

the

(MMU)

above

memory

KDF1ll

modules

CONTENTS

Page
PREFACE

General-Purpose Registers.....

CyCleS.iiciieiieacaacsnnnns

Addressing Memory and Peripherals.....

Management...ceceeceoscacceaccacns

(PS).cececececaacs

Condition Codes (PS bits <3:0>).....
Trace Bit (PS bit 4) .iiiciiiiacacecans

[]

[

CONTACT

FINGER

through WI15..

IDENTIFICATION..ccceceesas

BACKPLANE PIN ASSIGNMENTS AND THEIR KDF1ll-AA

UTILIZATION.
¢ ettt s aesccssssscssssssssaccasccas
HARDWARE OPTIONS . :ccccececccsccancancasns

BaCKpPlaneS.iieesseseeeaessasesacssccascancsas

*
»
[]
[]

nNdedwWwnH

=
W N

[
@
*
&

H9270 Backplan€...ceeececeacaacaanas
H9273-A BacKkplane..iecieeeeeteescsasacossenans
H9281 BacCKPlanE.:.cecaeeeeseasssssscscscasscs
......

DDV11-B

BacKkplane.:.ieceeseeeascecascacscacanas

[

—W8¢c.co..ooccc-oo¢-

Selectable Starting Address - W9

MODULE

& &RNN —

GTOU UL

NN DNNDNNDNODNDNDON
bl
|
I

173000

Starting Address

ABWWNNO

»
»

.
[)

[

Power-Up Mode Selection - W5 and Wé6....
POwer—Up MOde 0 e 6 6 6 06 6 6 6 6 6 a0 600080 0o s e
Power—Up MOde 1 4 6 6 4 6 6 068606068660 060aea00saascs
Power-Up Mode 2.......
Power—Up MOde 3.....‘l.l..ll..."‘l.“l.
Halt/Trap OptiOl’l - W7.-.cccoocc-occoooo-cc-occ

DN NN
N
I

[

[]

[

[}
[3

[
*
&

[

[)
[

[]
L]
[
[}
B w -

[

JUMPER CONFIGURATIONS.:cceaceacaacacas
Master Clock - Wl..c.eeese
Event Line _‘W4..l....C........l.“‘

[]
]
3
]
[]
]
[]
[J
[
[
ALk WWWWWN

»
L[]

SwWwhNoNDNDDNDDDNDNDND
NN

INSTALLATION
INTRODUCTION..ll.‘......‘...“.

oottt
otn

DOCUMENTS‘.....‘...‘.‘I‘

PERIPHERALS........

MEMORIES AND

SET. ® & &6 &6 & & ¢ & ¢ & & & & & & & & & & & o o

[]

INSTRUCTION

Previous Mode (PS bits <13:12>)......
Current Mode (PS bits <15:14>)....

[

Priority Level (PS bits <7:5>)..c...
(PS bit 8).
Suspended Instruction (SI)

[

Status Word

COoOOOWVWWYWWOWEWWO
NI ~JO0 W bW

e
e
T
o et sl o bt e b
I

»
[

[]
[

[]

[

&
]

e
[

D D

> i
00 ~J OV UT i

HARDWARE. ...«

Processor

[

b B DD WN -

gtk
wh -

e e

[]
[

e e

]
*

bt e bt b b

PROCESSOR

Memory

@
o
.
[
»
[]

[
]
[
]

SPECIFICATIONS
. ctceeaccassccascs

Bus

FEATURES i ittt e ccacsascssccssncansa

[
[

NDDODNDNDDNON

[

INTRODUCTION
. e ceeseccsscssccsaas

CHAPTER

SPECIFICATIONS

[]

CHAPTER 1

Device Priority Within Backplanes............2 -16

PoOwer

SUPPlieS.iciiceicacscaascscacnscascanaans c.co2—17

ENClOSUrEeS . cececeecsascessccssssasscsssacscsas ce...2-18

CONTENTS

(Cont)

Page

2.5.4

Memory

2.5.5

Peripheral

2.6
2.7
CHAPTER

3.1

MoOdUleS..iiiiititeeeceaaeaacacacanen -

SYSTEM

.2-18
OpPtioNS.iiieeeeeeeeeeeeoeeaeenannnes 2-18
DIFFERENCES
..ttt teeeeeeececeecssncacscesns ..2-18

MODULE

INSTALLATION

CONSOLE

PROC
. ¢t
EDUR
ettt eeescecocnn
E
es 2-19

ODT

INT RODUCTION. ¢ttt eeasenaeeaseeaseanccancsassaansesld-l
TERMINAL INTERFACE . .ttt teeseeteescscscscssssssaceas 3-1

3.2

3.2.1

Receiver

3.2.2
3.2.3

Receiver

3.2.4
3.3

Control and Status Register (RCSR).....3-1
Buffer Register
(RBUF) «ueiceeeeeeeeceeaeald=2

Transmitter

Control

Transmitter

Buffer

and Status Register (XCSR)..3-2
Register
(XBUF) ¢..ieeeeeeeaan 3-3

CONSOLE ODT OPERATION. .« tteeeeeecnceenascsccanaasseal—3
Console ODT Entry Conditions...... B

3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2

Console ODT INput SEQUENCE...ceiteeeccacacnseadsal—d
Console ODT Output Sequence...... I
|
CONSOLE ODT COMMAND SET .« cteteeacacacncacsenss «eee3-5
/(ASCITI 057) Slash.iiiiieieeeaaosccananeas ceeeeaa 3-7
<CR>
(ASCII 15) Carriage RetUIN...ciceececeancas 3-8

3.4.3
3.4.4

KLF> (ASCII 12) Line Feed...eeeeeeeecanacanns «es.3-8
$ (ASCII 044) or R (ASCII 122) Internal

3.4.5

3.4.6
3.4.7

G
P

(ASCII 107) GOeeveenoenaenossnoanncnnass ceeasesa3-10
(ASCII 120) ProcCeed. e .eceeeececcsesacsncaacaasasald=1l0
Control-Shift-S (ASCII 23) Binary DUMP.««......3-11

3.4.8
3.4.9

Reserved CoOmMmMaAnNdS .. eceeeeeeeaosessceaceanneanasald—1ll
SPECIFICATION.
.ttt teeccoasscocssaasnssccsas 3-11

3.5
3.5.1

ADDRESS

3.5.2
3.6

Stack

Processor

4.1
4.2

4.2.1

4.2.1.1
4.2.1.2
4.2.1.3
4.2.1.4
4.2.2
4.3
4.4
4.4.1
4.4.2

I/0
Pointer

AQAreSSeS.uiueeeeecenacaascaaneansald=1ll
SeleCtioN...ceicieeeeecaceasaceeaasald—l?

ENTERING

3.7
3.8
CHAPTER

DesSignator.cuiieeeeeseeeescccasasocsnsses 3-9
123) Processor Status Word..... cet e e 3-9

ODT

OF OCTAL DIGITS . et eeeeeeeaecsceacancaneaaedld—1l2
TIMEOUT . ittt eeeenetacastsosassssascsasssaaccacs 3-13

INVALID
¢4

LSI-11

CHARAC
. ittt
TERS
teeecanannes cs e st e

aan

«e.3-13

BUS

INTRODUCTION. ¢ttt s eeaoestoaacscescassossncanaasaaeeasd=l
TRANSFER BUS CYCLES....... c e s
eacas
s e N

DATA

Bus

Cycle ProtoCOl.iiieieeieeeeeeeaceacancncnasnes ..4-3
Device AdAresSSiNg...icieeeeeeececeeeaeaanannanna 4-3

32
DATO(B)
¢ e vt et eeneeaeanesesncsssacanasenes cees.d-5
DATIO(B) ettt teeeeaeeatsasssasoscascdascancseaasacd=9
Parity ProtoCOl.uieiieeeeeeaeeeeeaeceaaassannesedsd=9
DIRECT

MEMORY ACCESS . it tetteeeesescaasaacnes ceassd-=-12
INTERRUP TS . ¢ttt ittt eaeaeeaetsscancescnceancccncecas .4-14

DEeViCe

Priority.eeieieeseeeeeeeeaaensesaeaeanssad=15
Interrupt ProtoCOl..iiiieiieeesacacescnncscasaasd—1b

CONTENTS

[}

[J
W N

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[

AN A M RS S

I
[

[]

[

[3
]
[}
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»
OO
~IOYy NN
WN H

[

oA R AN a R AN

AC Load DefinitioON.ieeeeceesscccasccasacsasn
DC Load DefinitiONeececceeeaacsacconacnas
120 Ohm LSI-1] BUS:tteeetecccccscacscecses
Bus Drivers. [ ] [ ] [ ] L} L] . @ L ] - ® e & e o * & L] [ ]
Bus Receivers..Q...‘....‘.‘l..‘.Ol“l
BUS TerminNatioON.
e ceeeeeseescoes
Bus Interconnecting Wiring....soeeeceeeses
Backplane Wiring..e.cceeeesecasaccnsocsns
Intra-Backplane Bus Wiring......cceeee

= W+

o
e

[

XA R

@
o

Power

and

Ground........ cessasecsanace

Maintenance

and

Spare

PiNS...ceeecceees

CONFIGURATIONS
. . e e eteaaceccasscsssccscs

Rules for Configuring Single Backplane

—

e X X

Power StatlUS.cieesceaececcasoscaccssscscaans
BUS ELECTRICAL CHARACTERISTICS
. ccieeaacass
Signal Level Specification....ceeceeeces

SYSTEM
*

Configurations.........

Memory Refresh....... Ceecessssenn
Halt.l‘..“.‘.‘. ......
InitializatioN.eeeieceeeeoscasas ceeceaas « oo

[

*
L[]

»®

O
O
N
N
N
&

G
e

N
N
S

Interrupt

FUNCTIONS.“OQ“...O.“I

4-Level
CONTROL

(Cont)

SyStemS..ciieienseaanns

Rules for

Configuring Multiple Backplane

SYSteMS .t eiieeeeceanneacneannas

DESCRIPTION

ancnfiwm
b
I

BSYNCLLOGIC........Q....‘
DIRECT MEMORY ACCESS (DMA) ¢ttt ceceecassascns

»
[]

Occiieeennecaanns

[

]

[

L[]

[

L]
L]

[

00/GPO

01,

[

DMA

LOGiC.iceeeeeceaaaacesasosssascasancas

DMA

LatenCyieceecescesccccssoscscsscacaaacacs

L]
L]
(1IN
&)

SYNC/DMA ENA H.....cc..
.
MIB03/GPO 3.‘.'.‘.““...‘0.“‘..‘..‘I..

MIB02,

[

]

Huteooooaoaosaoassosssacssassssscassssascssas
[

CYC

BUS

]

MIBl4/Initialize (INIT F) i ceeeeacaaans
MIB13/Interrupt Acknowledge (IAK) «ccececaoasaans
MIB12, 9, 8/Address-Input-Output (AIO) Codes...

[

(MME)....

[

CHIP..cctteeeettasecctsacsssccasanss

MIB15/Memory Management Enable

]

o
o
3
[
]
[

B bW
N
AU

DATA-ADDRESS LINES (DAL) ccttetsecccennsanns
MICROINSTRUCTION BUS (MIB) ¢ ¢cccecececaancsscses

e
o
o
.
[}
[
]
@
o

LoVOwwoomoom~Toaoaooanoaoh oUW

MMU

S NGEGEGEGES RS RS NGNS N, NS RO RS RS S, RO RO RO R RN

ON
ssansscccsacs
DUCTI
..« cteeesssensasscc
INTRO
CHIP. ...t eeeteeaasessscnnnans
CONTROL CHIP... it eeeeeetsscctsssassaccssscns

DATA

NOWARCU
UTd &b
b DWW

PROCESSOR FUNCTIONAL

Loading..ccceeeeeccecaaocasnas

CHAPTER

Supply

oo
0ty L
o
I
|
I
o

Power

CLOCK GENERATOR CIRCUITRY..... ...................5-12
Initialization..i.icieiiieieeeenecscsacccacans ceeedb-12

Wake-Up CirCUit.................-.-............5"'13

vii

CONTENTS

(Cont)

[
*
[

[]

[
.
»

.5-14
.5-15

.5-16

[

[}

2
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»

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[d

[4
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-

Registe

L]
Ld

a General

Immediate MOAE€ .. vieeeceeecaeas
Absolute MoOde...veeeeeeaeasen
Relative MOde‘.‘...‘.‘...“l.‘.‘

PC Relative Deferred Mode€..........
Direct Addressing Modes Summary......
Indirect Addressing Modes Summary....
PC Register Addressing Modes Summary.

Graphic
7

Summary

INSTRUCTION

Addressing

Modes..

SET

INT RODUCTION . ¢ ¢ttt teeeeeensecasesececees

Format..

Control

InStructionS....ceee..
InstructionsS...e.eeeeeeeeee..

and

Subroutine

Condition

Code

Miscellaneous
0= 1) o

Instruction

= =

Instructions...

InstructionS........

InstructionS.........

Single

Operand

Double

Instruction

Operand

Example..

Instruction

Branch

Instruction

Example..

INSTRUCTION

Example.....oeeee..

SET.
vt
eeeenn S et e s ecc et escseacae

viii

DWW

Operand

Instructions...iiieieeeeeeeeees

Branch
Jump

InstructionS..........
InstructionS..........

Double
Byte
Program

w N+

]

[]

[

W WW W W NN N

[]
»
[
[
[]
»
»
[
[

MOA€ .. .ueeeeoeeeenn

W
-

the

Py S

Deferred

Use of
PC
PC
PC

Mode.......

MOAE . ittt ieeeeeeancanencnsens

Operand

[
»

[

»
)
»

[

HHEMHEFHFOWOWOOY

IndeX
Index

[

Mode€....eeeeeeae.
Deferred

[]

[

[)

»
.

[

Autodecrement

MOA€ ... eeeeeaos.
Deferred Mode..

[]

[

Autoincrement
Autoincrement

»
s

Mode....iveeewnenn.
Deferred Mode...

Operand

T e e el J o Sy Sy Sy G g

[}

MO
. ¢ et
DE
teeoeceens
S

Single

FORM
. vttt
ATS
eeeeea

ADDRESSING

UL
WD

INSTRUCTION

WNHH O

*
»

»
*
[
[
»
»
»

WWWwwWwwwiww
W+

[
[

[

[]

[

..5-14

MODES

Double

[

]

NN NN NN NN NSNS

ADDRESSING

«e.5-13

INT RODUC T ION . ¢ 4t et e ot eneececcesesennens

CHAPTER

Autodecrement

WWWLWwWWwWwwWww

AN
N
O

CHAPTER

[]

Stutter Cycle......
Clock Stop Cycle.iieenn..
Memory Management Cycle..
Reset Cycleiiiiieienannnn

Clock

CycCle..eeieieeieeennanns

]

Normal

[

Single-Step Circuit....eiieean.
CLOCK GENERATOR CYCLES......v...

[

Page

CONTENTS

(Cont)

Page

AND

PHYSICAL

WNNNDKHFH

I
|
[ o
I
|
o COoOVOmM~I~NOOOAAD

o
o

o
s

O
|
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000

*
3

@
*

]

»
*

[
L4

W N

2.2

Nonresident........
Page Length........

[
[]
N

=
O

o 0]

[

]

Status

(SR1) .iciieeecanns Cecesescseasad-19

Status

(SR2) iieceeeacanen cesecsacase8—-19

Status

(SR3) tceienesesencncans ceeess8-19

MEMORY

MANAGEMENT

INSTRUCTIONS.
.t ccceescccsaassss8—=20

PROGRAMMING EXAMPLES ..
9

Halt Read Only..ceeeeaas
Mode of Operation....ieceeeeens
Page NUmber....cceeceeeeceoacs
«
e
Enable Relocation and ProtectioN...cciceeeeeese8=19

e
e

Halt
Halt

2
2.1

[

ADDRESSES
.. it iieeeccccseceesad-14

Construction of a Physical AddresS....ccceee...8-15
Determining the Program Physical Address.......8-16
STATUS REGISTERS...... P
se X
Status Register 0 (SRO)...

L]
]

Expansion Direction (ED).cicacaana
.
Written INto (W) ciieeeieienosearseasocasosaaneasead=12
Page Length Field (PLF) citttieeeateccascnasssesad—13
PLF For an Upward-Expandable Page....eceeee..8-13
PLF For a Downward-Expandable Page...........8-14
VIRTUAL

(PAR)
¢t e ecaeeas

PAGE DESCRIPTOR REGISTER (PDR) ..... .
Access Control Field (ACF) ¢ee.eec.. .

ADDRESS

Status Word Protection....eeeeeces
ReStriCtioONS.iieeeeeesoseacassanasas
and Trap ProCcesSinNg...cccecececees

Processor
User Mode
Interrupt

&
e

> W+

Multiple AddressS SPACE:ccctctescasssscscsssssascs
Mode Specification in Processor Status Word.

PAGE

]
[
[3
L]
[
[
bW N

MEMOIY it cetiaeaoascnasscacasoacas

MemOI Y. ceeeeaeeaaesocasssocscsosscscacasas

Inaccessible
Read-0Only

0O Co 0O Co o CO 0o OO 0O O OO OO o Co o

[
»

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]

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[l
[

[]
]

[

[d
»

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UnitS.iiceeaoseascaaccascsanans ceeaan

MemMOry

PROTECTION . ¢t et teetteeostsacoscssecsssasasacsssesnaase

o
&
&
e

RELOCATION...«c«
.. C e eececs
st et cet
s
Program RelocCationN..iiiieeeeeaeseasosncacacas

MEMORY

4
[)
®
®
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MANAGEMENT

ProOgramming.ceeececeeesesessssescssscascacassaans
Basic AQdressing........ Cesteceseeesactaanana
Active Page Registers....... Cecsetseseaaeas
Capabilities Provided by Memory Management.

CHAPTER
\© OO\

MEMORY

INTRODUCTION.
¢« ettt s eacecosnastsssscscsstsssssccsans

WwwwwihhH-+

o
o

o
¢

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OCONNNNNNUNYNIN
OO
WwWWwWwwwwwwhNdNDHEHEEEE

©0 00 0O 00 0O 0O OO0 00 00 CO 0O OO CO 00 00 00 00 CO 0O OO OO 0O 00 0O 00 0O OO0 CO OO0 00 0O 0O OO0 CO CO Co GO O 0O GO

CHAPTER

FLOATING

it cteeeascasssssssseansesasesd—=20

POINT

INTRODUCTION. ¢t e et tseeecceasasasccsscassaccss
.9-1
FLOATING POINT DATA FORMATS
... ccceeececcccaacsscs ..9-1
Nonvanishing Floating Point Numbers.............9-1
Floating

Point

Z€r0...eeecicanaaas ceceacaeae ceeea9d-2

(Cont)

CHAPTER

|
HOWYWE
Wk N

[

]

.
L]

The Undefined Variable.....cieveeenn Ce
e e ca e 9Floating Point Data..ccceeeeeeannens ceesesscassal
FLOATING POINT STATUS REGISTER (FPS):ceeeeeeceseasad-

SN otk

WO WO

e
o))
Q
o

CONTENTS

FLOATING

EXCEPTION

CODE

AND

ADDRESS

REGISTERS.....9

FLOATING POINT PROCESSOR INSTRUCTION ADDRESSING...9
ACCURACY
..ttt eeetosscacsssssaccas c e e s s e s e e s s e s s s 9FLOATING
10

POINT

PROGRAMMING

INSTRUCTIONS.
..ttt eeeeertasascaccscas 9-1

TECHNIQUES

INTRODUCTION.
¢ ettt
eeeaecccccccseos C e et e e e st e s e 10-1

10.1
10.2

POSITION-INDEPENDENT

CODE..¢eetveeeses e
L R

Use of Addressing Modes in the Construction
of Position-Independent Code€.seevevereaneaeassall-1
Position-Dependent/Postion-Independent
Comparative Example...cieeeceerssaseascaosnseaessl0=3
STACKS .ttt sttt eesasssccassssssccssas cecescssessal0=5
Pushing Onto a Stack. i it eeeteteoescsanaacneseaasll=5

10.2.1
10.2.2
10.3

10.3.1

10.3.6.1

Popping From a Stack......c... ce et
«
oo
Deleting Items From a StacK.eieieeeeoeeceaasessl0=-6
Stack USeS.iiiieereseeccoccecacens oo e
.
Stack Use ExamplesS..ceieeeeseseasssascacscacocses 10-8
Subroutine Linkage....iveeeeettoceaasccsasecessal0-9
Return from a Subroutine.....¢ieceeeeeeeeses10-10

10.3.6.2
10.3.7

InterruptsS.. e e iieeeeesessssossstssossssnssassssslO-11

10.3.7.1
10.3.7.2

Nesting.....-.--........... ooooooo 00.1000000.10-12

10.3.8
10.3.8.1

REENEIANCY
¢ttt et enessosseossscsssacosssssscsas 10-12
Reentrant Code...o.......lltllv000000000‘000010-12

10.3.8.2
10.3.9

Writing Reentrant Code.....eeeee.e
COFOULINES
.ttt etetsessosastscssoscotsosssssosasase 10-15

10.3.2
10.3.3
10.3.4
10.3.5
10.3.6

Subroutine

AdvantagesS....ccesceeaascccasessasl0-10

Interrupt Service

Coroutine

10.3.9.1
10.3.9.2

Using

e 10-11

CallS.eeeeeeeeeeascsssosossossccaans 10-15

Coroutines Versus

10.3.9.3
10.3.10

RoutineS.......e... ce

SubroutineS....ceeeeeeeeas 10-17

COroUtineS...ceeeececestassssacacseessl0-17

RECUL SI1O0MNM e ¢t et oeecssosassssososscsasssasssascesas 10-19

ProCceSSOr

10.3.11
10.3.11.1

Trap

TraApPSeececsssccscsscsssscaassoscssassssssl0=21

INStruCtionNS.
i ceeeesesescscscscsnnessasl0=22

Use of Macro Calls..iceeeeeoeececeecans ceeees10-23

10.3.11.2
10.3.12

Conversion

ROULINES..cieetcoscsconcscacssscsosscs 10-24

10.4
10.5

PROGRAMMING THE PROCESSOR STATUS WORD:.:.::teeoea...10-28

10.6
10.7

PDP-11 PROGRAMMING EXAMPLES .. ¢ cctoeesseasessaseasal0-29
LOOPING TECHNIQUES . .t e eeeeesecossnssssnsassasssasl0=35

PROGRAMMING

APPENDIX

GENERAL

APPENDIX

INSTRUCTION

PERIPHERALS
. . ¢ ¢t tceesacosaossaesaeessl0—28

REFERENCE
TIMING

INFORMATION

CONTENTS

(Cont)

APPENDIX

KDF11/PDP-11

PROGRAM AND

APPENDIX

INTEGRATED

APPENDIX

BOOTSTRAP

APPENDIX

ODT

APPENDIX

KD11-F/KD11-HA/KDFl1l~-AA

APPENDIX

PARITY

OPERATION

DIFFERENCE

CIRCUITS

PROGRAMS

(CONSOLE

ENTRY)

DIFFERENCES

THE

LSI-11

DETAILED

COMPARISON

BUS

FIGURES

Figure
1-1
1-2

1—3
1-4

No.

Title
KDF11-AA

Processor

Module

Page
(M8186)

(Shown with Optional Floating Point)...eeececeaeaal=2
General RegiSter..icieeseeeecessoesssscscssoaacsaseassl=h
High and Low.... ......
@ & & & 5 & & & & ¢ & O & 5 & O 2 6 & & & S 0 0 o 1—6
Word and Byte Addresses for First 4K....eeieeeesesl=6

2-1

KDF11-AA Jumper

2-2

Double-Height Module Contact Finger
IdentificatiOn..o.................................2—6

2-3

H9270 Backplane Pin Identification
(Pin Side View Shown) @ 0 ¢ ¢ 0 2 0 ¢ 9 0 06 0 0 00 000000006000 00 02_7

2-4
2-5

H9270 Options POSitiONS..ceeietecesesscscscsoaesal2—13
H9273-A Option POSitiONS.cieeeeasecesecsosascsnssesl=l4

2-6

H9281 Option and Connector Locations (Module
SI1dE) tvvetrarrrsstnscssscassssseccassassssccnessasa=l5
DDV11-B Module Installation and Slot
ASSIgNMENtS
. e e eeesoesocncososs T
e V|

2-7

Status
Buffer

LOCAtiONS.:iccesscscsescscesoscssasel=3

3-1
3-2

Receiver
Receiver

3-3
3-4

Transmitter
Transmitter

4-1

DATI

BuS

CYCle.cieieeessssnososssssssssscscncsssedsd=5

4-2

DATI

Bus

CycCle

4-3
4-4

DATO
DATO

or
or

4-5
4-6

DATIO
DATIO

4-7
4-8

DMA
DMA

4-9
4-10

Interrupt

Request/Acknowledge

Interrupt

Protocol

4-11

Position-Independent

Control and Status Register....eeceee.3-2
Buffer Register....cceieeeestecacsoesald=3

DATOB
DATOB

or
or

TiMiNge.cieeeencsestscscccescsancecaseosd—6
BUS
Bus

DATIOB
DATIOB

CYCle.iieteseaeacassasasasscscaes .4-7
Cycle TiminNg...ceceeeoscscscasesd=8

Bus
Bus

CyCle.ceiieieneencsssecaseaseard=10
Cycle Timing....eeeeesseessead=11

Request/Grant

SEQUENCE .. «ctteetsesrsoasecassasad=13

Request/Grant

TiminNg....ceeeeeeeesccecaceeaasd=14

Sequence.......e...4-16

TiminNg...ieeeeeecoscensscceasecd=17
Configuration........eeec...4-20

X1i

FIGURES

Figure

(Cont)

Title

No.
Position-Dependent

Page

Configuration........... ceeescd-21

Power-Up/Power-Down Timing........ Ce e s e
Bus

Line

Single Backplane

T
T

Configuration.......... ceeeeesesd-29

Backplane

Processor
Bus

e 4-23

ConfigurationN.:...ceceeeeeaess.4=-30

Functional

Control

Block

Diagram....ceceeeeeeeeas 5-2

PROM....eeceaeonncos C e e e e et

e e et 5-5

GPO Decode LOgiCeveeacaaasca ceesesas e ea e ceesseasad—b

BUS

SYNC

LOGiCiteeseancanasan c et er s

et e 5-8

DMA LOgiC.i:eeresancas Cec e e C i etac e e e 5-11
Clock Generator.... ............. Ce e e e es e e e 5-13

Clock Generator Inltlallzatlon Circuitry.........5-14
Normal Clock Cycle.
C e e et et ec et s e e e
s «e.5-15
el B2
Clock Stutter Cycle... ..... o
Clock Stop CycCle.
. ieiiietieeeenosesnsonasonans ceeaead=16

Relocation Timing Circuit........ Ce e
Reset Circuit...ceeeaes c e et et ee e

Single Operand

Double Operand

e e e «.5=-17

e -

Instruction Format.......ccoceeeeees 6-2
Instruction Format....... c et e e e e 6-3

Mode Add Example.....ceeeeeeacanas ceeeaeab-5

Register Deferred Mode Example.....ceeciaececceans 6-5
Autoincrement Mode ExampPle...ccieeieeeeeecaccscancas 6-6
Autoincrement Deferred Mode Example......ceeeeenn 6-7
Autodecrement Mode Example......... c e e

e e

e .«6-7

Autodecrement Deferred Mode Example.....ccecesee..6-8
ExampPle.ciiieetaseccoccanoceces I

s
o0 WO

Mode

Index

N Y
PC Absolute Mode Example........... R

Program Counter Addressing MOdeS......eeeeesessesb6-17

[

0000 00N~

e X

AR AN A

TT T

N O

A R AR AR AR A R AN =22 N E WO I G, T SO i RO, IO RE O RO RN ) R )

& WNH
WO
WN - — b OO BWNHEFERERFROOIOUE

Multiple

TerminatioONnS.cecesceseesssssscaacsasenas 4-25

Index Deferred Mode Example....ceeeeeescoances «..6-10

Immediate Mode EXAmMpPle...icceesesescecanccscans 6-11

PC Relative Mode ExXampPle..icececeeesassasssseassasb=-1l3

PC Relative Deferred Mode Example........ et

e e 6-13

General Register Addressing ModeS.....cieeeeresas 6-16
Single Operand

Instruction Format.......cccecauees 7-2

Double Operand Instruction Format......ccceeeeecnen 7-3
Branch

Instruction Format...eeeeeieeeeeicecenanans 7-5

JSR Instruction Format.......... i eeteeseesssecassl—b
RTS

Instruction FOrmat..ceeeeecececescsnccsasonneeel=]

Condition Code Operators Format........... c et e 7-8

Active Page

RegiSterS..eieeecteesctoessasasssnossos 8-3

Simplified Memory Relocation..... ce
Relocation of a

32K-Word

Program

e 8-4
e et acaasens

into 124K—Word

@
o

oo 0

Example of a Downward-Expandable Page....ceceeeen 8-13

0 ~J O

Page Address RegiSter.i..iiieeeeessoaacsosnonnnoasassd=T

Page Descriptor RegisSter....cceeeitecssscoacccconns 8-8

O
|

Ul b

Physical MeMOIY..eeeseseresoaoesscansasssasasasssssB=D
Example of an Upward-Expandable Page...... et
Interpretation of

e e e 8-12

a Virtual Address....ceeeeeeens 8-15

Xxii

FIGURES

Figure No.

(Cont)

Title

Page

8-9

Displacement Field of Virtual AddresS.......s....8=15

8-11

Format of Status Register

8-10

8-12

8-13
W
O WO WO
[
i WN

-1

0-1

0-2

Construction

Format

Status

Single

Precision

Double Precision
2's

Complement

Physical

AddresSS..ccceecasecsecses.8-16

(SRO).:ieeeeeecaaasasa8-17

(SR2) cciceceescasaseasd-19

(SR3).iesteeacaccessa8-19

FOrmat.....eeeeeecaacoscaasccsssesd—2

Format....... S
R

FOrmMaAt...eeeeseeaseasossscascsacssecd—4

Floating

Point Status RegisSter...c.ieessascccccsssad=4

Floating

Point Addressing

Word and Byte
Illustration

ModeS....ccteeseeaaseasad-1l

StacKS....eeeestsscassassssssaceessl0—6

Push

and

Pop OperatiOnS.....c.e.. 10-7

10-3

Byte Stack Used as a Character

10-5

Nested

10-4

10-6

Buffer........ ...10-10

JSR EXxample..cceecesccacoaes ceccscscasssscscseasal0=-10

Interrupt Service

Routlnes and

SUDFOULEINES.t eeteesnesseeascacseassssoscsssaseaseall-13

Reentrant RoutineS........ cee

10-8

Coroutine Example...cceeeeeoses ceecsrnssenacessal0-16

10-10

Coroutine Path.....eeeeessesseessssasoccesaaassssl0-18

10-11

10-12

Coroutines vs.
Coroutine

N 0& A

Sharing

10-9

Control

e O

10-7

ROUtiINE€.::icetessosasoaseaasal0-14

Subroutines.....cceceeeseeeseesessl0-16

InteractionN.e..cecesscas B
L E R

Recursive ROUtINE FlOW....eoeessasoscaasosaaassesesl0-20
TABLES

Title

Page

2-1
2-2

Jumper ConfigurationsS....seceeecoceaca J A|
Backplane Pin Assignments/KDF11-AA Processor
UtilizatioN.ieeeeeeeoosaaeaananse C e et eacs et aaasan e

OWOOOJOAAAANUTWWN
|
HFWNHFWNHEFNDFW

Table No.

Console

Power-Up

Console

ODT

Printout

(or

Display).ceeeeees

COMMANAS e e s et aosoesscsoscsssacsssssssaose

Console ODT States and Valid Input Characters.....
General-Purpose Output SignalsS.:..eceeeeeacecess .o
Direct AAAressing MOAES .. ceseseeteascsscacsassscasesbd
Indirect Addressing MOdeS..ieieeeoscacacsesassssb—14
PC Register Addressing ModeS.....ceeeeeeeeeaecsasaab6-15
Instruction Symbols..... ceeeeseessseseane cesceseesl=13
Processor Status Word ProtectiOn.....eeceesecescesss8-9
PAR/PDR Address

Access
FPS

Control

ASSIigNMEeNtS..cceteesoeoscscccscas 8-10

Field

KeYS:ieeeteeeoeasesassnsesasesd—1ll

BitS..ieiieeieieeeseassscscscscssancassasd=h

x1ii

CHAPTER 1
SPECIFICATIONS
1.1

INTRODUCTION

The
KDF1ll-AA
is
a
16-bit,
high-performance
microprocessor
contained on one dual-height multilayer module
(M8186).
Figure
1-1
shows
the
module
with
1its
major
components
highlighted.
Utilizing the latest MOS/LSI technology, the KDF1l1l-AA brings the
full PDP-11/34 functionality to a microprocessor that communicates
along the LSI-11 bus.
The KDF1l1l-AA contains memory management as
a
standard
feature
and
offers
floating
point
as
an
option
(KEF11-A)
.
The

processor

uses

protocol
and
with existing

the

parity
LSI-11

LSI-11

bus

with

new

4-level

check
feature.
The KDFll-AA
processors and devices.

interrupt

1is

bus

compatible

The
LSI-11
bus
was
built
around
LSI
technology
requirements
consistent with low cost,
high performance
and
small
board
form

factors.
Low cost and high performance
using
multifunction
1lines
such
as
the

are realized, in part, by
data/address
1lines
(DAL)
that reduce the number of pins to the bus.
Other lines, such as
the I/0 page address decode line, eliminate hardware by removing
the need for identical page decoders on each interface module.
A
detailed description of the LSI-11 bus is contained in Chapter 4.
The
KDF11-AA
1is
software-compatible with
the
PDP-11
family.
A
wide
range
of
software
is
available,
including
programming
languages, diagnostic software, and operating systems.
1.2
The

FEATURES
KDF11-AA

contains

Four-level
response

the

following

vectored

without

management

program

space.

Memory

bus

parity

interrupts

device

Memory

features.

for

errors

provide

are

128K

fast

protected,

interrupt

recognized

during

multiuser

every

data-in

cycle.

Over
400
1instructions
programming.

for

16-bit

word

addressable

Eight

internal

accumulators

for

polling.

Stack

8-bit

and

processing

subroutines,

and

byte

powerful

general-purpose
for

for

operand

easy

interrupts.

and

convenient

locations.

registers

for

use

addressing.

handling

structured

data,

FLOATING

DATA/CONTROL UNIT

POINT

(BASIC PROCESSOR)

OPTION

MEMORY
= < z <Q L P w Z -

S z - 2 = =)

9562-2 BW-A0493

Figure

1-1

(Shown

KDF11-AA

with

Processor

Optional

Module

Floating

(M8186)

Point)

Asynchronous bus operation allows processor and system
their
at
run
to
(memory and peripherals)
components
speed.

highest possible

Direct memory access (DMA) allows peripherals to
memory without interrupting processor operation.

access

Modular

easily

component

configured

and

design

allows

systems

Power
fail
and
automatic
restart
hardware
protect against ac power fluctuations.

Compact,

upgraded.

double-height

module

size

detect

for

and

versatile

packaging.

ODT console emulator

1.3

ease of program debugging.

SPECIFICATIONS

Identification

M8186

Size

Double

Dimensions

13.34
(5.25

Power

ac
dc

2
1

Bus

for

Requirements

Loads

+12

cm X
in X
+

V +

21.59 cm
8.5 in)

5%,

unit
unit

2.0

0.2 A

loads
load

Environmental

Storage

40° ¢ to 65° C (104° F to 149° F)

Operating

5° ¢ to 60° c, (41° F to 140° F)

10%

relative humidity,

to 90%

noncondensing

Maximum 8utlet tSmperature rise of 5° ¢ (9° F)
C

above

(140"

Derate maximum temperature by 1° ¢
for

305

each

(1000

ft)

above

2440

(1.8° F)
m

(8000

ft).

10%

Timing

(Based on

(Refer
times.)

300

90%

relative

ns CPU microcycle

Appendix

for

humidity,

noncondensing

time)

detailed

1listing

instruction

Interrupt

worst

case

Worst

Case

Latency

with

(based

MSV11-D

without

parity,

add

500

parity)
55.7

microseconds

(for

infrequently

used

instructions)
10.8

microseconds

(for

frequently

(worst

case)

used

group)
Typical
Interrupt
Time
DMA

microseconds

8.2

microseconds

Service

Latency

1.4
The

6.0

3.49

PROCESSOR
KDF11-AA

microseconds

HARDWARE

1is
1implemented
using
three
chips.
Two
MOS/LSI
chips,
data and control,
implement the basic processor.
The
memory
management
unit
(MMU),
the
third
chip,
provides
a

PDP-11/34

processor

software-compatible

memory management

scheme.

The

data
chip
(DC302)
performs
all
arithmetic
and
1logical
functions,
handles
data
and
address transfers with the external
world, and coordinates most interchip communication.
The control
chip
(DC303)
does microprogram sequencing for PDP-11
instruction

decoding and contains the control store ROM.
The data and control
chips are both contained
in one 40-pin package
(refer to Figure
1-1).
The
MMU
chip
(DC304)
contains
the
registers
for
18-bit

memory
addressing
and
also
includes
the
FP1ll
floating
point
registers and accumulators.
Optional floating point requires the
MMU chip.
Data and control chips do not need the MMU chip for
16-bit addressing.

1.4.1
General-Purpose Registers
The data chip contains eight 16-bit

general-purpose registers that
provide for a variety of functions.
These registers can serve as
accumulators,
index
registers,
autoincrement
registers,
autodecrement
registers,
or
as
stack
pointers
for
temporary
storage

and

another,

data.

Arithmetic operations can be
from one general
another,
from one memory location or device register

between

general

memory

registers

locations,

Figure

identifies

through

1-2

between

device

the

eight

16-bit

R7.

Registers R6 and R7 are dedicated.
R6 serves as the stack pointer
(SP)
and contains the location (address) of the last entry in the

stack.
Register R7 serves as the processor's program counter (PC)
and contains the address of the next instruction to be executed.
It
is normally used for
addressing purposes only and
not
as
an
accumulator.
Register
operations are
internal
to the processor
and do not require bus cycles
(except for instruction fetch);
all
memory and peripheral device data transfers do require bus cycles
and

longer

execution

time.

Thus,

general

registers

used

for

processor operations result in faster execution
cycles required for memory and device references
Paragraph

times.
The bus
are described 1in

1.4.2.

GENERAL

REGISTERS

R2
R3
R4

| tsP)

STACK POINTER

] rc)

PROGRAM COUNTER
MR-3635

Figure

1.4.2

Bus

The

cycles

bus

1-2

General

Cycles
(with

respect

the

DATI

Data

word

transfer

input

DATO

Data

word

transfer

output

processor)

are

follows.

Equivalent

read

operation

Equivalent

word

write

Equivalent
operation

byte

write

Equivalent

word

read/

byte

read/

operation
DATOB

Data

word

DATIO

Data

word

followed

transfer

output

transfer

input

word

transfer

modify/write

output

DATIOB

Data

word

followed

transfer

byte

input

transfer

Equivalent

modify/write

output

Every

processor

instruction

first operation required is
from the location addressed

requires

one

bus

cycles.

The

a DATI, which fetches an instruction
by the program counter
(R7).
If
no

further operands are referenced in memory or in an I/0 device, no
additional bus cycles are required for instruction execution.
If
memory or a device is referenced, however, one or more additional
bus
cycles
1is
required.
DMA
operations
may
occur
between
individual bus cycles,
since these operations do not change the
state

the

processor.

Note

the distinction
between
interrupts
and
DMA
operations:
interrupts, which may change the state of the processor, can occur

only

between

operations

processor

refer

instructions.

Chapter

For

details

bus

1.4.3

Addressing Memory and Peripherals
processor
uses 16-bit data paths throughout.
These
same data paths are also used to construct operand and instruction
addresses.
Octal notation is used to describe information on the
data paths.

The

KDF11-AA

processor

shown

word

Figure

1is

divided

into

high

byte

low

byte

HIGH BYTE
1

and

1-3.

LOW BYTE
!

1
MR-3636

Figure

1-3

High

and

Low

Word

addresses
are
always
even—-numbered.
Byte
addresses
can
be
either
evenor
odd-numbered.
Low
bytes
are
stored
at
even-numbered
memory
locations
and
high
bytes
at
odd-numbered
memory locations.
Thus,
it 1is convenient to view the memory as

shown

Figqure

1-4.

16-BIT WORD
BYTE

BYTE

HIGH

LOW

000000

8-BITBYTE

LOW

000000

HIGH

LOW

000002

HIGH

000001

HIGH

LOW

000004

LOW

000002

HIGH

000003

LOW

000004

—T N

—
L~ R

(\fiM

HIGH

LOW

017772

HIGH

017775

HIGH

LOW

017774

LOW

017776

HIGH

LOowW

017776

HIGH

017777

WORD ORGANIZATION

BYTE ORGANIZATION
MR-3637

Figure

The

1-4

Word

and

full

16-bit

data

addresses

(i.e.,

virtual

addresses)

range.

This

range
the

32K

word

instruction

format

path

Byte Addresses

and

allows

First

program

anywhere

within

64K

range

fixed

virtual

cannot

for

address

changed

specify

the

user.

operand
byte

physical

words

32K

than

require

that

applications

For

address, such as multiprogramming and/or timesharing applications,
These bits allow up
two additional addressing bits are available.
to

128K memory words

This

additional

1.4.4

Memory

be physically addressed

part

capability

addressing

processor.

the

standard

the

memory management within the KDF11-AA architecture.
Management

Memory management has

Two

software

Extended

physical

words)

(timesharing)

128K

modes

three major

that

systems

are

addressing

for

memory

(greater

allowing

feature

has

employed

and

executing

two

operating

full

privileges,

program

and

(e.g., HALT instruction cannot
utilizes mapping
registers
to

for

than

multiuser

32K

one

words,

program

time

software modes,

the

allows

user

same

protection for controlling user
resources (e.g., memory, I/0)

1is

the

wuseful

Memory
system

first

features.

The

resources

following

reside

mode
for

the

program

kernel

system

while

user

restricts

and

access

user.

control

mode

processor

Kernel
system

employed

privileges

be executed).
The second
map
the
32K-word
virtual

space anywhere in the 128K-word physical address space.

feature
address

The third

feature allows restricted access go virtual memory pages (a page

is between 0
and
4K words 1long).
This permits the operating
system
software
rather
than
user
programs
to
control
system
resources.
Chapter 8 contains a complete discussion of memory

management.

1.4.5

The

Processor

processor

Status Word

status

(PS)

word

(PS)

end

the

data

chip

and

contains

information on the current processor status.
As shown in Figure
1-5, this includes: the condition codes describing the arithmetic
or
logical
results of
the
last
instruction,
a
trace
bit
that

forces

trap

the

current

memory management

instruction

program debug), the current processor
the
previous memory management mode,

execution

(used

during

priority,
an indicator of
and
an
indicator
of
the

mode.

1.4.5.1 Condition Codes
(PS
bits
<3:0>)
The
condition
codes
contain information on the result of the last CPU operation.
The
bits are set after
execution of all
arithmetic or
1logical
single-operand or double-operand instructions.
The bits are set
as

follows.

the

result

was

negative.

the

result

was

the

operation

if
the
operation
(most significant
LSB

arithmetic

overflow.

‘

PRIORTY

resulted
in
a
carry
from
the
MSB
bit) or a 1 was shifted from MSB or
significant bit).

(least

resulted

[
.

LEVEL

|
y

RESERVED
R
4

TRACE —

PREVIOUS MEMORY

NEGATIVE —

MANAGEMENT MODE

ZERO

OVERFLOW

CURRENT MEMORY

CARRY

MANAGEMENT MODE

MR-3638

Figure

1.4.5.2

Trace

programs

Bit

since

1-5

(PS
it

Processor

bit

allows

The

Status

trace

programs

bit

Priority

software

Level

determine

Octal

Value

(PS

bits

which

<7:5>)

interrupts

PS<7:5>

debugging

bits

are

used

processed.

Level

Acknowledged*

none

5
4

7,
7,

3
2

7,
7,

6,
6,

1
0

*Higher

1.4.5.4

used

single-instruction

These

will

Interrupt

(PS)

stepped.

1.4.5.3

Word

levels

Suspended

reserved

for

acknowledged

Instruction

DIGITAL

instruction

sets.

mechanism.

Refer

use

This
to

(SI)

and

bit

1is

Paragraph

first.

(PS

bit

intended

read/write

8.3.3.2

for

and
more

This

future

has

details.

bit

1is

optional

protection

1.4.5.5

Mode

memory management
was.

They

memory

management

are

1.4.5.6

Current

Mode

memory

are

present

even

bits

(PS

bits

the

and

These

last

are

<15:14>)

management

without

INSTRUCTION
KDF11l-AA

<13:12>)
what

bits

memory

present

used

with

management

are

mode

even

without

the

option.

present

1.5

bits

read/write

the

The

(PS

indicate

the

mode

memory

These

bits

indicate

what

They

are

read/write

and

is.

management

option.

SET

instruction

set
provides
over
400
powerful
As a comparison,
consider
that most other
(i.e.,
accumulator-oriented)
16-bit
processors
require
three
separate
instructions to execute a common double-operand instruction (e.g.,

instructions.

ADD) .

Conventional

Approach

LDA

Load

contents

ADD

Add

STA

Store

contents
result

memory

location

memory

location

A
B

into
to

accumulator.

By contrast,
the KDFll-AA can
fetch
store the result in one instruction.

both

operands,

execute,

and

KDF1l1-AA Approach
ADD

Add

contents

location

This greater efficiency
also improves processor
required.
Another

major

location

store

results

the

I/0
are

the
I/0

the

KDF1l1l-AA

instruction

set

but
are

absence of special-purpose input/output instructions.
Special
instructions are unnecessary since peripheral device registers
accessed 1in
to handling

advantage

not only saves memory space and time,
speed since fewer instruction fetches

same way as main memory locations.
This approach
devices allows
the normal
instruction
set
to be

used
to
test
and/or
bits.
For
example,

manipulate
the
various
I/0 device
register
a compare
instruction
can
test
status
bits

directly
in
the
I/0O
or
disturbing

device
any of

memory

into
bits

can
be
set,
cleared,
or
shifted
as
4s
most
convenient;
and
peripheral data can be arithmetically or
1logically altered when
received at the device register and before being stored in memory.
Refer to Chapter 7 for a complete description of the
instruction
set and its utilization.
:

Addressing

Modes

Much of the flexibility of the KDF1ll-AA is derived from its wide
range of addressing capabilities.
Addressing modes 1include
sequential forward or backward addressing, address 1indexing,
indirect
addressing,
absolute
16-bit
word
and
8-bit
byte
addressing,
and
stack
addressing.
Variable-length
instruction

formatting

allows

addressing

mode.

The

details

space.

For

1.6

FLOATING

Forty-six

option

(KEFll-A)
the

words

efficient

use

on addressing modes

used

for

program

refer

each

storage

to Chapter

OPTION

point

number

result

POINT

floating

supplement

minimum

the

integer

instructions

KDFll-AA

arithmetic

are

available

processor.

instructions

These

a microcode

instructions

(e.g.,

MUL,

DIV,

etc.)
in the basic instruction set.
The floating point option
allows
floating point operations to be executed 5 to 10
times
faster
than equivalent software routines and provides for
both
single

precision

(32-bit)

and

double

precision

(64-bit)

operands.

This option also conserves memory space,
since floating point
routines are executed
in microcode
1instead of
software.
This
option implements the same floating point instruction set found on
the

PpDP-11/34,

refer

1.7

-11/60,

Chapter

MEMORIES

AND

DIGITAL provides

and

-11/70.

For

complete

description

PERIPHERALS

a wide

range

of memories

and

peripherals

description can be found in the Memories
in the Microcomputer Handbook Series.

and

Peripherals

handbook

maximum flexibility when configuring systems.

1.8

allow

A detailed list and

DOCUMENTS

The following
is
a list of documents containing
additional
information of possible interest to KDF1l1l-AA microprocessor users.
Title

Document Number

Memories and Peripherals Handbook

PDP-11

Software

EB-09798-20

These

documents

Microcomputer Processors Handbook
PDP-11 Processor Handbook

Digital

444

Handbook
can

Equipment

Whitney

Northboro,

Attention:

ordered

from:

Corporation

Street
MA

01532

Communications

Customer

Services

15114

EB 15115 78
EB-09340-20

(NR2/M15)

Section

CHAPTER 2
INSTALLATION

2.1

INTRODUCTION

Items

that

include

must

the

considered

when

following.

Configuration

jumpers

features

installing

for

Selection
of
an
LSI-11
mounting, and installation

Selection

LSI-11

This

chapter

discusses

1.8

for

the

these
order

2.2
Several

procedures
number

chapter.

options

jumpers

Table

the

2-1

for

use

processor

lists

DIGITAL

Table
Jumper

Name

Master

the

module

jumper

provide

2-1

clock

Reserved

Event

and

should

Jumper

not

for

line

enable

option

Figure

used.

Out

Enable

internal

master

clock

Manufacturing

not

Disabled

Enabled

See

text

Trap

halt

108

not

remove

text

Enter

ODT

remove

only

Factory-installed

selector

Halt/trap

and

2.2.1 through
discussed
are

Configurations

use

Power-up

mode
W7

Refer

user-selectable

configurations

DIGITAL

W5,

referred

use

LSI-11

detail.

documents

shows the location of these jumpers.
Paragraphs
2.2.6 describe
the
jumper
functions.
Jumpers not

and

JUMPER CONFIGURATIONS

features.

reserved

backplane,

replacing

processor

user-selectable

bus-compatible

Knowledge of system differences
LSI-11/2 with a KDF11-AA

Paragraph

this

operation

KDF11-AA

bus-compatible

accessories

console

halt

Jumper Configurations

Table 2-1

(Cont)

Jumper

Name

Out

Conventional

Power—-up to

Power-up to

address, enable
if power-up mode

1730008

address selected
by jumpers

W9-W15

User-selectable
bootstrap

wWl7

wl8

2.2.1

Must be installed

Do not remove

Must be installed

Do not remove

Must be installed

Do not remove

use

Reserved for
DIGITAL

See text

power-

Reserved for
DIGITAL

See text

starting

for
2

Reserved for
DIGITAL

boootstrap

W9-W15

is selected

address
up mode

W16

bootstrap address

bootstrap start

use

Master Clock - Wl

The internal 13.8 MHz oscillator is disconnected from the clock
This jumper is used by DIGITAL
circuitry if W1l 1is removed.

manufacturing and is not to be removed by the user.

2.2.2

Event Line - W4

The bus signal BEVENT L causes the event line flip-flop to be set.

When the processor enters the service state the request will be
(BEVENT is a level 6
honored if the PS<07:05> is 5 or less.
clear the request
to
e
microcod
the
This causes
interrupt.)
If
100,) .
(location
vector
clock
line
the
to
flip-flop and trap
e
therefor
and
disabled
is
p
flip-flo
W4 is inserted, the request
which
BEVENT,
disable
would
Users
disabled.
is
the BEVENT signal
is normally used as a 60 Hz real-time clock, if they have a
programmable clock on the LSI-11 bus.

LSI-11

and

to Paragraph

2.6.

The

NOTE

LSI-11/2

processors

treat a BEVENT interrupt at a different
Refer
priority level than the KDF11-AA.

) R

wi1s
O—0

——

—

r—

W17

15|

[&g

92
.

aYe)
Q

Ico
§

o—o W15

W14 0——0

O——0 W13

W12 0—o0

OO0 W11

W10 0——0

O——0 W9

W8 0=——0
o—0 W7
W6 o———0

O——0 W5

W2
OO

wa
O

H
[

H
MR-2318

Figure

2-1

KDF11-AA

Jumper

Locations

2.2.3

Four

Power-Up Mode Selection - W5 and W6

power-up modes are

is made by removal or

the

following

listing.

Mode

available

selection.

user

for

Selection

insertion of jumpers W5 and W6 as shown in

Name

Wo*

W5*
R

PC@24,

PS@26

Console

ODT

2
3

Bootstrap
Extended microcode

R
I

I
I

Only the power-up mode is affected, not the power-down sequence.
The following paragraphs describe the sequence of events after

executing common power-up, when selecting each of the four modes.
The state of bus signal BHALT L is significant in power-up mode

operation.

2.2.3.1 Power-Up Mode 0 (PC@24, PS@26) - This mode causes the
and 26
microcode to fetch the contents of memory locations 24,

and loads their contents into the PC and PS, respectively.

microcode
processor

then

examines BHALT

enters console ODT mode.

If BHALT L

is asserted,

Thg

the

is not asserted,

the processor begins program execution by fetching an instruction
This mode is useful when
from the location pointed to by the PC.

power fail/auto restart capability is desired.

2.2.3.2 Power-Up Mode 1 (Console ODT) - This mode causes the
processor to enter console ODT mode immediately after power-up
This mode 1is
regardless of the state of any service signals.
environment,
debug
hardware
useful in a program development or
giving the user immediate control over the system after power-up.

2.2.3.3 Power-Up Mode 2

W8-W15)

(User Bootstrap Starting Address Shown by

- This mode causes the processor to internally generate a

bootstrap starting address by looking at Jjumpers W8 through W15
(see Paragraphs 2.2.5 and 2.2.6). This address is loaded into the
PC. The processor sets the PS to 3408 (PS<07:05> = 7,) to inhibit

?f BHALT L 1is
interrupts before the processor is ready for them.
If not, the
mode.

asserted,

processor

the processor enters console ODT

begins

execution

fetching

instruction

from

the

This mode is useful for turnkey
location pointed to by the PC.
ically begins operation
automat
system
the
applications where

without operator

intervention.

2.2.3.4 Power-Up Mode 3 (User Microcode - For Future Use) - This
mode causes the microcode to jump to optional control chip 378,
location

76,,

and

begin

microcode

execution.

This

mode

reserved fof future DIGITAL use and 1is not recommended for
customer usage. If it is erroneously selected, the processor will
treat it as a reserved instruction trap to location 108.
*R = jumper removed;

I = jumper

installed.

2.2.4
Halt/Trap Option - W7
If the processor is in kernel mode and decodes a HALT instruction,
BPOK
H
1is
tested.
If
BPOK
H
1is
negated,
the
processor
will
continue to test for BPOK H.
The processor will perform a normal
power—-up sequence 1if BPOK H becomes asserted sometime later.
If
BPOK
H
1is
asserted
after
the
HALT
instruction
decode,
the

halt/trap

jumper

(W7)

processor

enters

console

ODT

108

occur.

trap

location

1is

tested.

will

mode.

the

jumper

the

jumper

removed,

the

installed

NOTE

In
user
mode
a
HALT
instruction
execution will always result in a trap
to location 108.

This
feature
1is
operation,
where
desirable.
2.2.5

Starting

intended
recovery

Address

for
from

173000,

situations,
such
as
unattended
erroneous
HALT
instructions
1is

When power-up mode 2 is selecteg, the processor examines jumper W8
to

and
the

determine the starting address for program execution.
If W8
a compatible bootstrap module such as BDV-1l1l are installed in
system,
the
microcode
will
begin
execution
at
173000

(conventional

starting

removed,

trap

removed,
starting

the
processor
address.

address

for

(nonexistent

looks

DIGITAL
address)

Jjumpers

systems).
will

occur.

through

1is

1is
the

W15

for

2.2.6

Selectable Starting Address - W9 through W15
If the user wishes to start execution from an address other
1730005,
jumpers W9 through W15 can be used to
specify the

byte 5&5:09> of the starting address.
correspond

address

bits

<15:09>,

than
high

Jumpers W15 through W9

respectively.

Bits

<08:00>

the starting address are set to 0 by the processor.
Jumpers are
installed for logic 1, removed for logic 0.
The starting address

can
reside on
address space.

any

256-word

2.3

MODULE

CONTACT

DIGITAL
contact

plug-in
finger

FINGER

boundary

the

lower

32K

memory

IDENTIFICATION

modules,
including the KDF1l1l-AA, all use the same
(pin)
identification
system.
The
LSI-11
bus
is

based on the use of double-height modules that plug into a 2-slot
bus connector.
Each slot contains 36 lines (18 each on component
and solder sides of the circuit board).
Slots,

shown as row A and row B in Figure 2-2,
include a numeric
identifier
for
the
side
of
the module.
The component
side
1is
designated
side
1
and
the
solder
side
1is
designated
side
2.

Letters
ranging
from
A
through
V
identify a particular pin on a side
designated

follows.

(exclduding
of a slot.

G,
‘A

I,
O,
and
typical pin

Q)
is

i eiya

PIN AA1

PIN AA2

ROW A

PIN AV

PIN Av2

SIDE 1
COMPONENT

SIDE

)

PIN BA1

\ N

PIN BA2

ROw B

SOLDER SIDE

)

PIN BV

PIN Bv2

Figure

2-2

Double-Height

Module

Contact

BE2

Slot (Row) Identifier

l '

"Slot B"

Finger

Identification

Module Side Identifier
"Side 2"

(solder

side)

Identifer
"Pin E"

The positioning notch between the two rows of pins mates with a
protrusion on the connector block for correct module positioning.
2.4

When

BACKPLANE PIN ASSIGNMENTS AND THEIR KDF11-AA UTILIZATION

configuring

inserted

one

system

with

several

the

KDF1l1l-AA,

available

the

module

backplanes.

may

Refer

Paragraph 2.5 for information on the types available.
Using the
H9270 backplane as an example, Figure 2-3 shows the backplane pin
Individual connector pins shown are viewed from
identification.
the underside (wiring side).
Only pins for one bus location (two

slots)
times

are

shown

this

in detail.

backplane,

This

allowing

pin pattern
the

user

backplane pin assignments

and

repeated

install

eight

several

double-height modules.

Table

2-2

lists

the

use by the KDF11-AA processor module.

describes

their

H9270 POWER AND
SIGNAL CONNECTIONS

B3l

| o

r__Oo__

ROW IDENTIFIER

TYPICAL MODULE
LOCATION

MODULE SIDE IDENTIFIER
1 = COMPONENT SIDE
2 = SOLDER SIDE

(SLOTS A1-8B1)

D __1_________fgL_ .

WIRE-WRAP PINS
PASS THROUGH

H9270 PC BOARD

\¥?\

oo | o,

_____o _OOOOOOOOO

==
|
3

_____o _J_O_

| %

I
Lo
|
o

| o
LoS

o |<53on0zorocomonome | <ouomozerocsmosome | |

______

{NOOOOOOOOO

__+ _______ | ________

eI I

—\

/
MR-2320

Figure

2-3

H9270
(Pin

Table

2-2

Backplane
Side

View

Backplane

KDF11-AA

Processor

Identification

Shown)

Assignments/

Utilization

Bus

Mnemonic

Description

AAl

BIRQS5

Interrupt

Request

priority

level

AB1

BIRQ6

Interrupt

Request

priority

level

ACl
AD1

BDAL16
L
BDAL17 L

Extended address bits (also used for parity)

AE]1l

SSI

Single-step

AF1

SRUN

Run

light

signal

AH1

SRUN

Run

light

signal

AJl

GND

Ground

AK1

MSPAREA

ALl

MSPAREB

Maintenance
together
on

Spare
Normally
connected
the
backplane
at
each
option

location

(not

bused

Ground

System

AM1

GND

input

System

(Reserved

signal

for

ground

DIGITAL

and

use)

return.

connection).

signal

ground

and

return.

Table 2-2
KDF11-AA

Backplane Pin Assignments/
Processor Utilization (Cont)

Bus

Mnemonic

Description

AN1

BDMRL

Direct Memory Access (DMA) Request - A device
asserts this signal to request bus mastership.
The
processor
arbitrates
bus
mastership
between itself and all DMA devices on the bus.
If

the

processor

not

bus

master

(it

has

completed a bus ¢&ycle and BSYNC L is not being

asserted
by
the
processor),
1t
grants
bus
mastership
to
the
requesting
device
by
asserting
BDMGO
L.
The
device
responds
by
negating BDMR L and asserting BSACK L.
APl

BHALT

Processor
processor

Halt - When BHALT L is asserted,
responds by going into console

the
ODT

mode.
AR1

BREF

AS1

+12B

Memory Refresh - This signal
1is not
KDF11-AA; however, it is terminated.

used

+12

Battery

connection.
certain

Power

Battery

devices.

Not

System

signal

used

AT1

GND

Ground

AUl

PSPARE1

Spare
(Not
assigned.
recommended.)

AV1

+5B

Battery

connection.
certain

BA1l

BDCOK

voltage

asserted

available

used

can
on

usage

power

with

KDF1l1l-AA.

there

sustain

BPOK

Power

Asserted

primary power

normal.

processor
operation,
sequence 1is initiated.

BC1
BD1

MMU
MMU

DAL18
DAL19

BE1

MMU

DALZ20

BF1

MMU

DAL21

BH1

(Reserved

Clock

for

Disable

DIGITAL

system

the

power

supply

when

power

fail

trap

When negated during

use)

Reserved

signal

sufficient

reliable

operation.
This signal is also driven
"wake-up" circuit on the KDF1l1l-AA.

BB1

not

used

supply-generated

when

with

return.

and

Secondary

used

power

by KDF1l1l-AA.

power

Power

Customer

Not

+12

can

ground

Battery

devices.

Power

that

Power

Secondary

power

for

DIGITAL

use

Backplane Pin Assignments/

Table 2-2
KDF1l1-AA

Processor

Utilization

(Cont)

Bus
Pin

Mnemonic

Description

BJ1

GND

Ground

BK1
BL1

MSPAREB
MSPAREB

Maintenance
Spare
Normally
connected
together on the backplane at each option

System

location

BMll

GND

BN1

BSACK

(not

bused

ground

and

return.

connection).

Ground - System signal ground and dc return.
L

This

signal

response

1is

that

request

priority

Interrupt

BR1

BEVNT

External

Event

asserted,

the

6
a
4

the

DMA

processor

(Not

DMA

level

master.

Request

signal,

bus

arbitrates

assigned.

device

BDMGO

device

interrupt.
A typical use
line time clock interrupt.

Spare

processor's

indicating
BIRQ7

PSPARE

asserted

the

BP1

BS1

signal

this

Customer

When

level

signal

wuse

not

recommended.
BT1

GND

Ground

System

BU1l

PSPARE?2

Spare

(Not

signal

ground

assigned.

and

Customer

return.

wuse

not

recommended.)

BV1

Power

Normal

Vdc

system

power

AA2

Power

Normal

Vdc

system

power

AB2

-12

Vdc

-12

Power

=12

this

(optional)

devices

requiring

Modules

that

require

inverter

circuit

(on

required

voltage(s).

power

for

voltage.

NOTE

generates

power

the

options

not

required

including

AC2

GND

Ground

System

AD2

+12

+12 V Power

negative

with

the

KDF1l1l-AA

signal

ground

- +12 Vdc

voltages

each

contain

module)

which

Hence,

-12
DIGITAL-supplied

processor.

and

system power

return

Table

2-2

KDF11-AA
Bus

Backplane
Processor

Pin
-

Mnemonic

Description

AE?2

BDOUT

Data
that

and

Pin Assignments/

Utilization

(Cont)

Output - BDOUT,
when asserted,
implies
valid data is available on BDALKO0:15> L
that

output

transfer,
with respect
to
the bus master device, is taking place.
BDOUT
L is deskewed with respect,
to data on the bus.
The
slave
device
responding
to
the
BDOUT
L
signal
must
assert
BRPLY
I
to
complete
the

transfer.
AF2

BRPLY

1is

asserted

response

BDIN L or BDOUT L and during IAK transaction.
It is generated by a slave device to indicate
that it has placed its data on the BDAL bus or
that
AH2

BDIN

has

accepted

Data Input - BDIN
bus operation:

output

data

used

from

the

two

types

for

The

When asserted during BSYNC L time, BDIN L
implies an input transfer with respect to

the
current
bus
master,
and
response
(BRPLY L).
_ BDIN L

bus.

when

the

data

from

master

device

slave

requires
a
1is asserted

ready

device.

When

asserted
without
BSYNC
L,
indicates that an
interrupt operation
occurring.

master

BRPLY

device

must

deskew

input

data

1is

from

AJ2

BSYNC

Synchronize - BSYNC L is asserted by the bus
master device to indicate that it has placed
an address on
the bus.
The
transfer
1is
1in
process until BSYNC L is negated.

AK?2

BWTBT

Write/Byte - BWTBT L
control a bus cycle:
l.

asserted

during

used

the

two

ways

leading

edge

BSYNC
L
to
indicate
that
sequence
is
to
follow
(DATO
rather than an input sequence.

an
or

output
DATOB),

bus

cycle,

asserted

for

during

byte

BDOUT

addressing.

DATOB

Table

2-2
KDF11-AA

Backplane Pin Assignments/
Processor Utilization (Cont)

Bus

Mnemonic

Description

AL2

BIRQ4

Interrupt

request

AM2

MMU

(Reserved

for

AN2

BIAKO

STR

priority

DIGITAL

Interrupt

Acknowledge

generated

interrupt

request

asserts

the

BIAKO

L pin of the
to
Chapter

use)

Output

processor

(BIRQ

which

first
3

level

This

the

The

routed

signal

response

L).

device

for

the

bus.

©proper

processor

the

BIAKI

Refer

interrupt

protocol.

AP2

BBS7

gwfiv
AR2

AS2

BDMGO

MAP

Bank 7 Select - The
when an
I/O device
range)
1is placed on

bus master asserts BBS7 L
address
(upper
4K address

asserted

and

duration
cycle.

(Reserved

DMA

Grant

generated

BBS7

the

for

the

bus.

remains

addressing

DIGITAL

Output

BSYNC

active

then

for

the

bus

portion

1is

processor-

use)

This

the

daisy-chained

signal that grants bus
highest priority DMA device

mastership to the
along the bus.
The

processor generates BDMGO
L, which is routed to the BDMGI L pin of the
first device on the bus.
1If it is requesting
the bus,
it will inhibit passing BDMGO L.
1If
it is not requesting the bus, it will pass the

BDMGI
L
signal
to
the
device
wvia
its
BDMGO

next
(lower
priority)
L
pin.
The
device

asserting BDMR L is the device requesting the
bus, and it responds to the BDMGI L signal by
negating BDMR, asserting BSACK L, assuming bus
mastership,
and
executing
the
required
bus
cycle.

AT?2

BINIT

Initialize
-~
BINIT
1is
processor
to
initialize or

asserted
by
the
clear
all devices
connected
to
the
I/0O
bus.
The
signal
1is
generated in response to a power-up condition
(the
negated
condition
of
BDCOK
H),
or
by
executing a RESET instruction.

Table 2-2
Backplane Pin Assignments/
KDF11-AA Processor Utilization (Cont)
Bus

Mnemonic

Description

AU2
AV2

BDALO
BDAL1l

Data/Address Lines - These two lines are part
of
the
8-1line
data/address
bus
over
which
address and data information are communicated.
Address information is first placed on the bus

L
L

the
bus
master
device.
The
same
device
then
either
receives
1input
data
from,
or
outputs data to the addressed slave device or
memory over the same bus lines.
BA2

Power

Normal

Vdc¢

system

power

BB2

-12

-12 V Power
=12 Vdc
(optional)
power
for
devices requiring this voltage.
Not used by
KDF11-AA.

BC2

GND

Ground

BD2

+12

BE2

System

Power

BF 2

BDAL3

BDAL2

Data/Address

BH2

BDAL4
BDALS

L
L

described.

BJ 2

BK2

BDAL6

BL2
BM2

BDAL7
BDALS8

BN2
BP2
BR2

BDALY9 L
BDAL10 L
BDAL1ll L

BS2
BT 2
BU2
BV2

BDALl12
BDALl13
BDALl14
BDAL1S

2.5

power

systems

can

Backplanes

the

> WN
-

system power

Lines

These

8-1line

configured

enclosures,

2.5.1

the

+12 Vdc

data/address

return

lines

bus

are

part

previously

OPTIONS

Any
with

and

L
L
L
L

supplies,

ground

HARDWARE

KDF11-AA

the

signal

following

LSI-11

using

memories,

variety

peripherals,

bus-compatible

etc.

backplanes

backplanes,

can

KDF1l1l-AA.

H9270 - Accepts quad- or double-height modules
H9273-A - Accepts quad- or double-height modules
H9281 - Accepts double-height modules only
DDV11-B - Accepts quad- or double-height modules

used

Refer
to
the
description of

Memories

2.5.1.1

Backplane
The
H9270
consists
of
an
8-slot
a
card
guide assembly.
As
shown 1in Figure
2-4,
is designed
to
accept
up
to
eight
double-height

each

H9270

backplane
with
this backplane

and Peripherals
handbook
for
a
complete
backplane and installation information.

modules (including processor), four quad modules, or.a combination
of quad- and double-height modules.
When used for bus expansion
in multiple backplane systems, the H9270 provides
six option modules,
plus the
required
expansion
module(s) and/or terminator module.

space

for

cable

connector

VIEW FROM MODULE SIDE OF BACKPLANE

PROCESSOR

(HIGHEST PRIORITY LOCATION})

PROCESSOR OR OPfl_ON 1

OPTION 3

OPTION 2

OPTION 4

OPTION 5

OPTION 7

OPTION 6

(LOWEST PRIORITY LOCATION)

MR
- 1152

Figure

2.5.1.2 H9273-A
consists of a 9

2-4

H9270

Options

Positions

Backplane

- The H9273-A backplane logic assembly
4 backplane (nine rows of four slots each) and a
card
frame
assembly.
Power
and
signals
are
supplied
to
the
backplane through connectors J7 and J8.

The

H9273-A

backplane

is designed to accept both double-height and
with the exception of the MMV11-A core memory
module.
The backplane structure is unique in that it provides two
distinct buses: the LSI-11 bus signals (slots A and B)
and the CD
bus
(slots C and D).
The connectors that comprise this backplane

quad-height

are

modules

arranged

nine

rows.

Each

which

contains

pins,

Three

jumpers

(W1,

W2,

and

W3)

enables

the

line-time

clock

connector

either
are
when

side

shown

has

of
in

inserted

the

two

each

2-5.

Jumper

disables

Figure
and

slots,

slot.

removed.

NOTE

Only
one
BAll-N
system
may
have
enabled.

mounting
box
in
any
the
line-time
clock

when

CONNECTOR 1
Al

SLOT A

SLOT B

SLOT C

o
wi
TM
PROCESSOR

CONNECTOR 2
_A

SLOT D

o
wp
o o
wg
o

MODULE

OPTION 1

ROW 2

(HIGHEST PRIORITY)
OPTION 2

ROW
3

OPTION 3

ROW
4

OPTION 4

ROW 5

OPTION 5

ROW
6

OPTION 6

ROW 7

OPTION 7

ROW
8

OPTION 8

ROW
9

(LOWEST PRIORITY)
VIEW IS FROM MODULE SIDE OF BACKPLANE
MR.2880

Figure

2-5

H9273-A

Option

Positions

When inserted, jumpers W2 and W3 allow the LSI-11 quad-height CPU
to run in row 1.
Jumpers W2 and W3 are removed when the backplane
is

The

used

expansion

connectors

according

the LSI-11

backplane

designated

the

bus

LSI-11

signals

"Connector

bus

and

system.

Figure

specification.

Slots

are

termed

lower

row.

the

LSI-11

2-5
A

bus

are

and

wired

slots.

carry

The

connectors designated "Connector 2" are wired for +5 V and ground,
and have no connections to the LSI-11 bus; instead, C- and D-slot
pins on side 2 of ‘each row are connected to the C- and D-slot pins
on

side

1in

interconnection

2.5.1.3

H9281

designed

the

scheme see

Backplane

For

details

the

backplanes

are

the Memories and Peripherals handbook.

(Figure

double-height

2-6)

The

modules

H9281

only.

The

H9281

backplane
is available
in
six options as
listed below.
backplanes allow the user to configure compact LSI-11 bus
that most efficiently utilize available system space.

2-slot

These
systems

POWER CONNECTOR

BLOCK (J1)

a
z

Oooooo0oo0

[~
3

H9281-AA, -BA

(J2

SIGNAL

1 — PROCESSOR MODULE

SLOT BACKPLANE

2 < OPTION
1 (HIGHEST PRIORITY)

;

3 < OPTION 2

;

4 — OPTION 3 (LOWEST PRIORITY)

LROWNUMBER

B ——SLOT LETTER

OO0

OO0
S TR

1 ~PROCESSOR MODULE

2 < OPTION 1 (HIGHEST PRIORITY)

3 < OPTION 2

H9281-AB, -BB

4 — OPTION 3

5« OPTION 4

8-SLOT BACKPLANE

e
R

6 —OPTION 5

E—

7 <~ OPTION 6

8 <~ OPTION 7 (LOWEST PRIORITY)

120 OHM BUS TERMINATION RESISTORS

OO
OO0 O0O0OO0

1 <~ PROCESSOR MODULE

_4_ JW R SU N

2~ OPTION 1 (HIGHEST PRIORITY)

H9281-AC, -BC

OPTION 4

6 — OPTION 5

7 —OPTION 6

8 —< OPTION 7
9 —OPTION 8

e e e e

12-SLOT BACKPLANE

3 <~ OPTION 2
4~ OPTION 3

10— OPTION 9
11

OPTION 10

12 <~ OPTION 11 (LOWEST PRIORITY)

A
h
C1

120 OHM BUS TERMINATION RESISTORS
MR-0463

Figure

2-6

H9281

Option

and

Connector

Locations

(Module

Side)

Backplane
Option
Designation

Description

H9281-AA

4-module

backplane

H9281-AB

8-module

backplane

H9281-AC
H9281-BA

12-module backplane
4-module backplane and

H9281-BB
H9281-BC

8-module backplane and card cage assembly
12-module backplane and card cage assembly

Some

card

cage

assembly

NOTE
are
too

options

large
to
be
installed in an H9281 backplane.
Refer
to Memories and Peripherals handbook for
a complete list.

Bus Terminations
Backplane models H9281-AB,
-BB,
-AC,
and -BC
include 120 ohm bus
termination resistors at the electical end of the bus; therefore,
it is not necessary to install a separate 120 ohm bus terminator
module in these backplanes.
2.5.1.4 DDV11-B Backplane - The DDV11l-B is an optional LSI-11 bus
expansion
backplane
for
use
when
additional
1logic
space
1is
required.
The DDV11l-B is a 9 X 6, 54-slot backplane with a 9 X 4
slot section
(18 individual double-height or 9 gquad-height module
slots)
prebused specifically for LSI-11 bus
signal and power and
ground connections.
The remaining 9 X 2 slot section is provided
with +5 Vdc, GND, and -12 Vdc power connections only; this leaves

the
remaining pins
logic modules to be
modules

and

bus

free for use with any special double-height
used in conjunction with the LSI-11 family of
requirements.

Module Slot Assignments
Figure
2-7
shows
the
slot
1location assignments
Rows A, B, C, and D are dedicated to the LSI-11

of
the
DDV11l-B.
bus.
Any module

that conforms to the LIS-11 bus specifications may be used in this
portion of the DDV11-B.
The position numbers indicate the bus
grant

wiring

scheme

with

respect

the

processor

module.

The

bus

grant signals propagate through the slot locations in the position
order shown in Figure 2-7 until they reach the requesting device.
To provide bus grant signal continuity, any unused slots must be
jumpered
or
unused
locations
position-numbered locations.
Rows

ground

and

contain

connections

2.5.1.5 Device
backplanes are
for

from

DMA

and

the

occur

user-defined

only

the

slots

with

highest

power

and

provided.

Priority Within
Backplanes
All
LSI-11
bus
priority-structured.
Daisy-chained grant signals

interrupt

first

the

must

requests

(highest

propagate

priority

away

device)

from

the

processor

successively

lower

priority

devices.
Processor module locations and
priorities
are
shown
in
Figures
2-4,
2-5,
2-6,
further discussion, see Paragraph 2.5.5.

power

(1-+4]

PROCESSOR

2-4]

posmon3

3— 41

POSITION 4

a—4{

positon?

15— 11

device

(option)
2-7.
For

and

PROCESSOROROPTION 1 | | |

opmionposmionz

POSITION 8

f6-—

POSITION §

111

[

POSITION 6

[

POSITION 9

PoSITION 11

| | |

posiTioN10

7- 14

posiToNn12

|||

Pposimion1sa

|||

8-+

posimiont1s

posimonta

]

-1

posiToN1s

| [{

posmon1z

|||

TERMINAL

BLOCK

ROW —

[[

MODULE INSERTION SIDE

’

USER DEFINED SLOTS

MODULE (COMPONENTS MOUNTED ON OPPOSITE SIDE)

NI
PC BOARD

\%fiBHIMcW'IWT—T—W—mQ
n,

—n

WIRE WRAP PINS

TERMINAL STRIP

POWER SIGNAL PINS

MR
- 1156

Figure

2-7

DDV11-B

Module

Installation

and

Slot

Assignments

2.5.2

Power Supplies
H780
and
the
H786
configuring a KDF11-AA system.
in detail
in the Memories and

Both

not

the

available

separately,

only

power

supplies
can
be
used
when
The H780 power supply is described
Peripherals handbook.
The H786
is

part

the

BAll-N

enclosure.

2.5.3
Enclosures
The BAll-M mounting

box,

H780

the

H786

power

H9273

supply,

backplane

and

which

includes

BAll-N

mounting

power

supply,

with
the
KDFll-AA
processor.
handbook contains details on both

H9270
box,

can

backplane
which

used

The
Memories
boxes.

and

includes

system

Peripherals

2.5.4
Memory Modules
Several memory modules
are
available
for
use
with
the
KDF1l1l-AA
systems.
However, modules such as MSV11-C or MSV11-D that perform
memory refresh locally are required,
since the KDF1ll-AA does not

perform

memory

refresh

itself.

MSV11-C

provision is made for refresh with
REV11l;
however,
this will degrade
recommended.
The
further information

Memories
on LSI-11

2.5.5
Peripheral Options
All
LSI-11
bus-compatible

memories

will

work

1if

some other bus option such as
system performance and
1is not

and Peripherals handbook
bus-compatible memories.

peripheral

devices

may

contains

used

1in

KDF11-AA systems.
DMA peripherals should be installed with the
faster throughput devices physically closest to the processor and
slower
ones
farther
away.
The
user
must
ensure
that
faster
devices
have
adequate
access
to
the
bus;
otherwise,
data
drop
errors may occur.
Interrupt-driven peripherals can be installed
in

one

the

following

ways.

all

single-level
scheme,
they
must
be
interrupting devices physically closest

current

DIGITAL

can

advantage

level

peripherals

method.

take

Future

LSI-11

bus

peripheral

new

4-level

peripheral

the

devices,

peripherals

use

the

installed
with
faster
to
the processor.
All

devices

must

customer-designed

interrupt

scheme.

use

this

devices,

With

the

new scheme, peripherals that are designed to perform distributed
interrupt arbitration, and that are on different interrupt levels,
can be installed in any order.
Multiple peripherals on the same

request

and

that

not

perform

distributed

arbitration
must
be
installed
with
the
highest
priority,
or
faster,
devices
<closest
to
the
processor.
The
Memories and
Peripherals
handbook
contains more
information
on
available
devices and their
installation.
For further discussion of the
4-level interrupt system, see Paragraphs 4.4.2 and 4.4.3.
2.6
SYSTEM DIFFERENCES
A number of minor differences

and

the

LSI-11

(KD1ll-F)

KDF11-AA

Console ODT

KDF11-AA does

The

following is a list of
the KDF1l1l-AA's advanced
has

EVENT

KD11-HA

exist

boot

not

1line
it

KDF11l-AA

that

exist

loader

microcode.

system differences
design.

the

(KDll-HA)

functions

have

between

LSI-11/2

are different

perform memory

level

level
4.

processor

processor.

the

because

The
of

KDF1l1l-AA.

refresh.

KDF1l1l-AA;

KD1ll-F

and

The

following

paragraphs

contain

differences.
Also refer
comparison information.

systems

KD1l1l-F,

automatically

KDF11-AA

that

does

used

not

are down-line

the

enter

the

contain

Appendixes

the

details

and

additional

ODT

bootstrap
a

more
C,

command

for

"L"

could

loader.

Console

loader

command.

bootstrap

KDFll-AAs must

change

their

these

ODT

used

the

Users

who

host

software

to enter the 14 memory-word bootstrap loader via console ODT.
The
REV1l
refresh/boot
module
cannot
be
used
to
boot
a
KDFll-AA
system.
However, the refresh portion of the REV1l can be used to
perform refresh for older MSV11-B type memories.
This will cause
a degradation of system performance and
is not recommended.
If
this
method
of
refreshing
memories
is
employed,
the

bootstrap/diagnostic functionality of the REV11l must be disabled
by
removing/installing
the
appropriate
jumpers.
The
BDV11
bootstrap/diagnostic
module
may
be
employed
for
automatic
bootstrap
function.
The
automatically
sizes
memory.
varies will have
use console ODT.
For

improved

"L"
command
in
KDF11-AA
users

create

performance

the

program

KDF1ll-AA

was

self-size

refresh
(as was the KD1ll1-HA).
The newer
and MSV11-D perform refresh locally.
In

the

KDFll-AA,

all

multi-level

the
KD1ll-F
whose
memory

designed

memories

interrupt

the

system

without

such

also
size

PDP-11

memory

MSV11l-C

systems,

the event line is on 1level 6.
In the KD1ll-F it is on level
4.
Users whose own software locked out the event line by just setting
PS<07:05>
to
4
(priority
1level
4)
will
have
to
modify
their

software to
a
KDFll-AA

set PS<07:05> to 6
(priority level 6) when installing
into
their
present
system.
DIGITAL
software
1is

unaffected.
2.7

MODULE

Proceed

INSTALLATION

directed

Ensure

PROCEDURE

below.

that

there

power

applied

the

backplane.
2.

Remove

all

modules

from

the

recommended

that

and

+12

application of +5 V and
4.

Turn

power

backplane.

single

switch

used

the

backplane.

+12 V

recommended.

for

the

following

apply

Simultaneous

on.

the

respect

backplane,
to

GND

(pin

check
C2

any

Row

Slot

Row

Slot

Pin
Pin

A2:
D2:

+5 V
+12 V

Row

Slot

V1:

backplane

voltages

slot):

with

not

applied

power

off.

Turn

Ensure

that

described
Insert
Turn

the

system

into

system
as

with

power

backplane.

Paragraphs

module

responds

CAUTION
in
modules

plug

1is

2.2

properly

configured

2.6.

backplane.

power.

described

Observe
in

Table

that

the

console

device

2-3.

If
the
device,

BDV-1l1l
1is
used as a system bootstrap/diagnostic
the user must consider the following.

diagnostic portion
legal PDP-11 basic

The
most

the

BDV-1l1l will exercise
at least once.

instructions

The
diagnostics
were
originally
created
for
the
KD11-F.
1In the KDF1ll-AA the BDV-11] diagnostics will
not:

(1)

Perform
any
point-related

(2)

Exercise

memory
tests

any memory

management

present

above

32K

floating

words.

11.

Significant
differences
exist
between
console
ODT
responses generated by the KDll-F and the KDF1l1l-AA
(see
Appendix F).
Users familiar with the KD11-F (LSI-11) or
users
not
familiar
with
the
operation
of
console
ODT
should refer to Chapter 3.

12.

Use

console

qguick

check

proper

system

operation,

following short exerciser program can be used.
a continuous stream of ASCII characters on the
ODT

enter

the

following

program.

Location

Data

Macro

1000
1002

005000
12701
177564
105711
100376
110061

CLR RO
MOV #177564,

1004
1006

LOOP:

TSTB

Code

(R1)

1010
1012
1014
1016
1020

BPL LOOP
MOVB RO,

005200

INC

000137

JMP

@#1006

1022

001006

(R1)

the

It prints
terminal.

Enter
ASCII
13.

"1000 G" to console ODT and a continuous stream
characters should be printed on the terminal.

For
a
more
thorough
check
diagnostics are available to

of
do

the
KDFll-AA,
the following.

Exercise

the

basic

instruction

Exercise

the

traps

and

Exercise

the

addressing

functions

memory

interrupts
management

Exercise
the
floating point hardware
the floating point instruction set.

The

diagnostics

Basic
-

Instruction

MMU

Diagnostic

Floating

Point

Test

CJKDCA

Test

CJKDDA

and

extended

registers

and

Interrupts

Test

follows.

Set,

CJKDBA

processor

set

are

CJKDAA

Tests

EIS,

Traps

and

Table

Conditions
BHALT

(unas-

serted)

Mode

Processor

¢Z-¢

serted)

(as-

will

ecute

program

using

contents

Power-Up

exof
the

value.

Terminal will
print out contents
of memory location 024.

Printout

(or

Mode

location

BHALT

Console

2-3

Mode

Terminal will print
out a random 6digit number, which
is the contents of
the

program

Terminal
out

will

random

print
6-

digit number, which
is the contents of
the program counter.

If
mode
3
1is
selected,
and
user
microcode
is
not
implemented,
the
processor
will
trap
to
memory

location
010
and
start
program
execution
using
the
contents
of
location
10
as
the
PC
wvalue
and
location 12 as the PS value.
Normal mode for use with the BDV-11
option.
If
jumpers W15
through W9
are
used,
that
address
will
be
printed.

The terminal printout will consist of
6
octal digits
as
specified
in
the
table, followed
line
feed,
and
in all cases.

Mode

Processor
ecute

(Note

will

program

exat

location 173000.
(See Note 2.)

printout at
terminal.
(See
Note 1.)

counter.

NOTES

Display)

by a carriage return,
"@"
prompt character

Terminal will
print out
"173000."
(See Note 2.)

No printout at
terminal.
(See
Note

1.)

CHAPTER 3
CONSOLE

3.1

INTRODUCTION

Console

octal

ODT

debugging technique
(ODT)
exists as a portion of the
processor
microcode
that
allows
the
processor
to
respond
to
commands and
information entered
via
the
terminal.
The
terminal
addresses
are
777560
through
777566,.
They
are
generated
in

microcode and cannot be changed.
Console ODT is very useful as an
aid in running and debugging programs.
Communication between the
user and processor is via a stream of ASCII characters interpreted
by the processor as console commands.
These commands are a subset
of ODT-11.
The differences in use of console ODT in the KDF11-AA
as

compared

3.2

TERMINAL

The

minimum
permitting

contained
the

the

LSI-11

are

listed

Appendix

INTERFACE

hardware
a

minimum

requirements
for
a
serial
1line
interface
terminal
to
communicate
with
console
ODT
are
the following paragraphs.
The
intent is to describe

hardware
for
users who design their own serial
line
The necessary console ODT hardware is a subset of that
needed
to operate system software.
For
system software/hardware
requirements
refer
to
the
DLV11l
section
in
the
Memories and
Peripherals handbook of the Microcomputer Handbook Series.

interface.

3.2.1

Receiver

The

RCSR
input
to

3-1)

DATI

bus

and

must

console
ODT.
to this address;

cycles
to

Control

(Figure

cycles.

Status

exist

However,

NOT USED
i

software

such

DATO

Enable

cycles

(bit

6),

D
|

causes

Interrupt

use.

777560,

system

bits,

(RCSR)

address

for character
Console
ODT
does
not
exeécute
DATO
bus
therefore, the RCSR only needs to respond

in order to affect certain
which console ODT does not

NOT USED
1

7775608
|

1
MR-3639

Figure

Bit

Description

<7>

Done

flag.

After

the receiver
be
set
to a
(i.e. cleared
this

to
by

bit.

3-1

Receiver

Status

character

assembled

and

exists

buffer register
(RBUF),
the Done flag must
1.
When
a
DATI
is
performed
to
the
RBUF
pick up the character), the Done flag must be
hardware.
Also bus signal BINITL must clear

Bit

Description

<6:0>

Unused.
state

<15:8>

console

since

DIGITAL interfaces,

does

mode

ODT

1in

can

and

them.

use

not

these bits may be defined.

any
In

(RBUF)

Receiver Buffer Register

3.2.2

cares

don't

are

bits

These

for character
must exist at address 777562
This register only needs to respond to DATI

The RBUF (Figure 3-2)
input to console ODT.

bus cycles since console ODT does not execute DATO bus cycles to
System software interfaces similarly but DIGITAL
this address.
diagnostics may cause a DATO cycle and not operate properly.

NOT USED

3-2

Figure

DATA
l

Receiver Buffer

7775628

Bit

Description

<7:0>

These eight bits are read by the
ASCII character.
When
processor and interpreted as a console ODT command.
bit 7 of RCSR is a 1, the processor does a DATI to the
After the DATI, the hardware must clear bit 7 of
RBUF.
RCSR

since

state

interfaces,

console

ODT does

not

these bits may be defined.

any

In DIGITAL

them.

use

can

These bits are don't cares and

Unused.

<15:8>

Transmitter Control and Status Register (XCSR)
3.2.3
for character
The XCSR (Figure 3-3) must exist at address 777564

ODT does not execute DAT% bus cycles to

output from console ODT.
this address;

bus cycles.

certain bits

the XCSR only needs

therefore,

(e.g.,

to DATI

Interrupt Enable).

respond

However, system software causes DATO cycles to affect

NOT USED
|
|

]

NOT USED
|
|

]

7775648
MR-3641

Figure 3-3

Transmitter Control and Status Register

Bit

Description

<7>

Done flag.

In the idle state, this bit is a 1 indicating

that the hardware is ready to print a character.
to

DATO

buffer

transmitter

the

After a

processor

(i.e., a character loaded), this bit must be cleared to O
After the character is printed, the
by the hardware.

During power-up this bit is

hardware sets this bit to 1.

Bus signal BINIT L must set this bit to 1.

set to 1.

These

Unused.

<6:0>

cares

don't

are

bits

can

and

any

state since console ODT mode does not use them.
DIGITAL interfaces, these bits may be defined.

<15:8>

3.2.4
Transmitter Buffer Register (XBUF)
The XBUF (Figure 3-4) must exist at address 7775664,
output from console ODT.
This register only needs

for character
to respond to

DATO bus cycles since console ODT does not execute DATI bus cycles
to

this

address.

System

software

diagnostics may cause a DATI

Figure

but DIGITAL

7775668

DATA

NOT USED
1

interfaces similarly

cycle and not operate properly.

3-4

Transmitter

Buffer

]

Bit

Description

<7:0>

ASCII character.
These eight bits are written by the
processor with the ASCII character to be printed.
When
bit 7 of XCSR is a 1, the processor does a DATO to the

After

XBUF.
XCSR

<15:8>

Unused.

state

These

CONSOLE

hardware must

the

DATO,

bits

console

since

interfaces,

3.3

the

bit

clear

these

are

ODT

bits

don't

does

may

cares

not

use

and

can

them.

1in

any

DIGITAL

defined.

ODT OPERATION

The processor's microcode operates the serial line interface in
half-duplex mode.
Program I/0 techniques are used rather than
interrupts.

When

characters using
is

not

the

monitoring

the

console

ODT

transmit side of

the

receive

side

microcode

the

for

1is

interface,

incoming

busy

printing

the microcode

characters.

Any

The interface may
characters coming in at this time are lost.
post overrun errors,
but the microcode does not check for any
error bit in the interface.
Therefore users should not type ahead

ODT

because

those

characters

are

not

recognized.

addition,

if another processor is at the other end of the interface,
obey half-duplex operation.
No
1input characters should
until console ODT has finished outputting.
3.3.1

Console

ODT

may

ODT

entered

Execution

the
2.

HALT

Entry
as

1t
be

must
sent

Conditions

follows.

of a HALT instruction in kernel
TRAP jumper is not installed.

mode,

provided

Assertion

of the BHALT L signal on the LSI-11 bus.
BHALT
L
is
a
level,
not edge-triggered.
The
signal must be
asserted long enough so that it is seen at the end of a
macroinstruction by the service state in the processor.

option

has

been

selected,

ODT

1is

entered

upon

power-up.

NOTE

Unlike
the
KDll-F
and
KD1l1l-HA,
KDF11-AA does not enter console ODT

the
upon

occurrence of a double bus error
(i.e.,
R6 points to nonexistent memory during a
bus timeout trap).
The KDFl1l-AA creates
a new stack at location 2 and continues
to trap to 4.
Since the KDFll-AA does
not
perform
memory
refresh,
a
bus

timeout
during
refresh
cannot
take
place.
This differs
from
the KD1l1l-F,
which enters console ODT upon
such an

occurrence.
while getting

If
an

a
bus
timeout
occurs
interrupt vector,
the

KDF11-AA

ignores

execution

KD11-F

Refer

and

console

the

KDll-HA

Appendix

ODT

enter

the

character

that

erroneous

interpreted
is

halted.

The

input

present

and

the

characters

for

ignore

Read

Output

contents

the
ODT.

listing

buffer

user

command,

character

RBUF.

read

using

DATI

This

done

characters

are

not

especially when

ignored.

program

ODT

terminal.

console

console ODT

sequence

console

for

<continues

whereas

differences.

3.3.2
Console ODT Input Sequence
Upon entry to console ODT, the RBUF

and

program,

program

follows.

terminal.

(program counter

R7)

six digits

Output

Output

the

Enter a wait loop for terminal input.
The Done flag, bit
7 in RCSR, is tested using a DATI.
If it is 0, the test

prompt

terminal.

character,

terminal.

continues.

If
a

RCSR bit 7

then

low byte

RBUF

read

DATI

and

using

DATI.

3.3.3
Console ODT Output Sequence
The output sequence for ODT is as follows.

Test

XCSR

continue

3.4

The

bit

(Done

flag)

using

If XCSR bit 7 is a 1, write character
using a DATO (high byte is ignored by
CONSOLE

ODT

COMMAND

console ODT command

XBUF

to low byte
interface).

SET

set,

the following paragraphs.
use the
states.

testing.

listed

in Table

3-1,

described

The commands are a subset of ODT-11 and

same command character.
Console ODT has ten 1internal
For each state only specific characters are recognized as

valid inputs;
are described

other inputs
in Table 3-2.
Table

3-1

invoke

Console

"?"

response.

These

states

ODT Commands

Command

Symbol

Use

Slash

Prints

Carriage Return

<CR>

Closes an open location.

Line Feed

<LF>

Closes

open

location
the

opens

contiguous

processor

Internal Register|

$ or R

Opens

Processor Status

Opens

Starts program execution.

Proceed

Designator

Word Designator

an $

the
or

Resumes

must

R command.

execution

program.

Binary Dump

and

location.

specific

location.

then

contents

the

specified

Control-sSshift-S

Manufacturing

Reserved

for

use only.
DIGITAL

use.

Table

3-2

Console

Example

State

States

Terminal

ODT

and

Valid

Input

Characters

Valid

Output

Input

Comment

0-7
R,

G
P

Control-Shift-S

0-7
S

@1000/123456

0~-7
CR
LF

@R1/123456

0-7
CR
LF

@1000

0-7

@RI

@RS

0-7
S

/
7

@1000/123456

1000

0-7
CR
LF

@R1/123456

1000

0-7
CR
LF

Previous
was

Control-Shift-S

The

parity

not
the

stripped) by
state of the

Output
the

bit

(bit

bit

all

these

input

characters

(i.e.,

echoed,
(XBUF).

1internally

equal

to
describe
before
they

paragraphs

bytes
ignored

<LF>.
Where
applicable,
characters are recognized.
In
order
mentioned

binary

console ODT and if the input character is
parity bit is copied to the output buffer

characters

parity

generated
All

(e.g.,

commands

upper-

and

are

location

opened

<CR>)

1lowercase

the
use
of
a
command,
other
have
been defined.
For
the

should

scanned

first

for

echoed

ODT

have

except

for

command

commands
are
novice user,

familiarization

and

then

reread

paragraph,
processor

for

detail.

refers

status

word

The

word

bus

"location,"

address,

used

processor

1in

this
or

(PS).
NOTE

In the examples the response from
processor
1is
underlined,
while
user's

entry

the
the

not.

3.4.1
/(ASCII 057) Slash
This command
is used
to open

complete,

console

either

Example:

@001000/012525<SPACE>

LSI-11

bus

address,

processor

register,
or processor status word and is normally preceded by
other characters which specify a location.
In response to /,
console
ODT
prints
the
contents
of
the
1location
(i.e.,
six
characters)
and
then a space
(ASCII
40).
After
printing
1is

ODT waits

for

or a valid close command.
The space
the location's contents and possible
user are legible on the terminal.

new data

for

character is
new contents

that

location

issued so that
entered by the

where:

= console ODT prompt character.

001000

= octal location in the LSI-11 bus address

= command

open

and

012525.

octal

location

<SPACE>

= space

space desired by the
are not required).

location.

contents

character

user

(leading

contents

1000.

generated

console

ODT.

The

the

command

data

just

can

entered

used

without

into

location

previously

specifier

opened

location.

verify

The

is
recognized
only
if
it
entered
immediately
after
a
prompt
character.
A / issued immediately after the processor enters ODT
mode causes a ?<CR>XLF> to be printed because a location has not
been opened.

Example:

@1000/012525<SPACE>

1234

@/001234<SPACE>
where:

first

line

new

data

1000

and

location

1234

entered
closed

into

with

location

<CR>

second

line

/
was
specifier

entered
and the

without
previous

a
1location
location was

opened

reveal

were

3.4.2

This

<CR>

contents

the

(ASCII

command
new

are

15)

used

Carriage

changed,

the

@R1/004321<SPACE>

Processor

1issued<CR>.

the

new

into

memory.

location.

was

response

should

desired,

<CR>

open

user

If no change is
altering its contents.

Example:

that

entered

precede

<CR>

closes

this

case

the

user

entered

before

and

data

the

open

Console

ODT

echoes

additional

3.4.3
<LF>
This command

the

location
the

<CR>,

1234

desired

issuing

the

change

<CR>,

<CR>

when
a
printed;
no

contents

are

data

R1l,

was

printed

<LF>,

new

ODT

<KLF>

1is

data,

1is

entered,

changed,

the

and

1is

the

new

data

user

and

was

the

then

new

prints

then open the
and
processor
If the PS 1is

and

the

open

should

location

1234,

closed

opened.

the

<CR><LF>@.

open location and
LSI-11
bus
addresses
2 and 1 respectively.

issued,

1location

printed

deposited

(ASCII 12) Line Feed
is used to close an

new

location

desired

console

Console

entered

followed

with

change

then

next
contiguous
1location.
registers are incremented by
open

<CR>

<CR>.

and

<CR>

the

opened

a R1/004321<SPACE>
e

location's

the

<CR><LF>@.
Example:

contents

Return

data.

without

user

correctly

<CR><XLF>Q

precede

1is

closed

data

1is

1location's
the

<LF>.

without

being

altered.
Example:

@R2/123456<SPACE>

<LF>

@R3/054321<SPACE>
In

this

case,

response,

has

the

opens

the

user

entered

console

ODT

closed

1last

the

beginning

R7,

<LF>

and

open,

RO.

with
then

and

opened

1issues

When

the

preceding
R3.

<LF>,
user

When

it.
a

console
has

the

1In
user

ODT
last

LSI-11
bus address open of
a
32K word
segment
and
issues
<LF>,
console ODT opens the first location of that same segment.
If the
user wishes to cross the 32K word boundary,
he must reenter
the
address
for
the desired 32K word segment
(1.e.,
console ODT is
modulo 32K word).
This operation is the same as that found on all

other

PDP-11

consoles.

<LF>

@R7/000000<SPACE>
@R0/123456<SPACE>

Example:

@577776/000001<SPACE>
@477776/125252<SPACE>

<KLF>

Unlike other commands, console ODT does not echo the
<LF>.
Instead
it
prints
<CR>,
then
<LF>
so
that
terminal printers operate properly.
In order to make
this easier to decode, console ODT does not echo ASCII
0, 2 or 10, but responds to these three characters with
?2<CR><KLF>Q.

3.4.4

(ASCII

044)

Designator

Either

character when

designator,

(ASCII

followed

by a

122)

1Internal
number,

S, will open that specific processor

to 7,

The $ character is recognized to be compatible with ODT-11.
The R
character was introduced for the convenience of one key stroke and
because it is representative of what it does.
@$0/000123<SPACE>

Example:

@R7/000123<SPACE>

<LF>

@R0/054321<SPACE>

If more

than one character

ODT

console

the

uses

typed

There is an exception, however:
or 477, ODT opens the PS rather
3.4.5

(ASCII

This designator

must

123)

employed

Processor

the

if the last
than R7.

after

the PS

user

has

the R or

three digits equal

(processor

entered

§,

designator.

Status Word

for opening

after

(digit or

character

last

077

status word)

and

modified

the

are

not

designator.

Example:

@RS/100377<SPACE>
@/000010<SPACE>

Note

trace

user.

the

This

bit

(bit

is done

<CR>

the

ODT

case.

user

issues

prints

cannot

utilities

that PDP-11 program debug

ODT-11),
which
use
the
T
bit
accidentally harmed by the user.

and

<LF>

while

<CR><LF>@.

for

the

new

single-stepping,

open,

location

the

opened

(e.g.,

closed

this

3.4.6
G (ASCII 107) Go
This
command
is
used
to
start
program
execution
at
a
location
entered immediately before the G.
This function is equivalent to
the
LOAD
ADDRESS
and
START
switch
sequence
on
other
PDP-11
consoles.
Example:

The

200

console

character,
1.

ODT

sequence

two

that

for

after

echoing

the

command

follows.
nulls

follows

(ASCII

does

double-buffered

not

UART

the

LSI-11

flush

the

chip

bus

initialize

character

the

DLV1l

from

serial

the
line

interface.
2.

Load

(PC)

entered,
0
to 200 and
3.

The

PS,

The

(at

300

used.

bus

the

point

above

program

data

example,

execution

status

1is

equal

begins).

the

MMU

initialized by the processor asserting
microseconds
(at
300
ns
microcycle),

service

state

anything

(In

data.

and

then

waiting

for

110

microseconds

microcycle).

The

BHALT

entered

where

12.6

BINIT
ns

cleared

for

negating

the

floating

LSI-11

BINIT

1is

that

and

present,

with

bus

entered

serviced,

signal

the

asserted,

processor.

1is

processed.

the

processor

there

the

reenters

the
console
initialize
a

ODT
state.
This
feature
1is
wused
to
system without
starting
a
program
(R7
is
altered).
If the user wants to single-step his program
he issues a G and
then
successive P commands,
all done
with the BHALT L bus signal asserted.

This

(ASCII

command

corresponds

120)

the

programmer-visible
Example:
Program

the

resumes

the

immediately

enters

the

bus

the

instruction

enters

the

resume

execution

switch

state

other

altered

PDP-11

using

program
consoles.

this

and

command.

echoed,

BHALT

CONTINUE

machine

execution

Proceed

used

1is

printed.

step

through

the

signal

state
is

ODT

the

state.

this

program

the

address

ODT

state

fetch

asserted,

(during

console

(R7)

console

Upon

fashion,

and

get

terminal.

pointed

left

and

the

instruction.

service

3.4.7

recognized

state)

and

the

R7.

After

processor
the

end

I1f
of

processor

entry,

the

content

user

can

single-instruction

"trace"

displayed

the
on

PC
his

3.4.8
Control-Shift-S (ASCII 23) Binary Dump
This command is used for manufacturing test purposes

and is not a
normal
user
command.
It
1is
described
here
to
explain
the
machine's
response
if
accidentally
invoked.
It
is
intended
to
more efficiently display a portion of memory compared to using the
"/" and <LF> commands.
The protocol is as follows.
1.

After

prompt

character,

control-shift-S

command

and

The

other

host

system

the

console

echoes
end

ODT

receives

the

serial

line

send
two 8-bit bytes which console ODT
interprets
starting address.
These two bytes are not echoed.
The

first

byte

specifies

starting

second

byte

specifies

starting

address

bits

<17:16>

are

command

1is

restricted

the

address

byte

always

1it.

address

<15:08>

address

<07:00>.

forced

first

32K

words

must

and

the
Bus

the

dump

address

received,

console

space.

After

the

second

- ODT

outputs

the

address

finished,
If

console

user

3.4.9
An

Reserved

ASCII

reserved

typed,

rather

response.

3.5
18

bits

console
than

other

ADDRESS
I/0

line

When

starting

output

1is

the

<CR><LF>@.

enters

exit

100)

binary

this

from

the

command,

entered

dump,

for

future

ODT

will

"?"

which

operation

prompt

1is

that

two

starting

character

DIGITAL

echo

the

1is

use.

and

the

1invalid

1is

prompt

<character

performed.

SPECIFICATION

addresses

(124K

specified,

128K)

must

regardless

desires

not.

For

DLV1l,

he
must
enter
addresses must

18-bit

(ASCII
the

been
serial

specified.

prints

order

has
the

Commands

character

All

After

1is

accidentally

ODT

accidentally

characters

address.
printed.

bytes

previously

recommended,

octal

example,

user

777560,

not

used

entered

whether
to

the

users

MMU

open

the

with

present

RCSR

177560.
With
an MMU
access memory greater

all
or
the

present,
than 32K

words.

3.5.1
Processor I/0 Addresses
Certain processor and MMU registers have I/0 addresses assigned to
them for programming purposes.
If referenced in console ODT,
the
PS

responds

through
777700

through

its

not

bus

address,

respond

777707

(i.e.,

777776.

timeout

referenced

Processor

occurs)

console

ODT.

registers

bus

addresses

The MMU contains status registers and PAR/PDR pairs.
Any of these
registers can be accessed from console ODT by entering
1its bus
address.

Example:

@777572/000001<SPACE>

this

the

memory management

case,

Accessing

the

accesses

kernel

and

following
the

the

management
enable
user

kernel

status

pointer

specified

user

stack

registers

1is
by

opened

stack

pointer

pointer.

and

accomplished

referenced

the

current

1is
done
for
convenience.
If
mode
(PS<15:14>
=
00)
is
halted

ODT,
mode

it
bits

a
program
and
R6
1is

accessed.

3.5.2
Stack Pointer Selection
Similarly,
if a program is operating

the

set.

Whenever

pointer

This
kernel

stack

way.

stack

(PS<15:14>) .
operating
in

opened,

memory

user

specific

mode,

stack

"R6"

pointer

accesses

desired,

PS<15:14> must be set by the user to
the appropriate value and
then the "R6" command can be used.
If an operating program has
been halted, the original value of PS<15:14> must be restored in
order to continue execution.
Example:

140000

@R6/123456<SPACE>
The

user

mode

stack

pointer

was

this

been

opened.

@RS/140000<SPACE>
@R6/123456<SPACE>

0 <CR> <CR><LF>
<CR> <CR><LF>

@RS/000000<SPACE>

140000<CR>

was

has

case,

the

kernel

examined

and

closed.

opened

and

PS<15:14>

mode

stack

were

The

set

pointer

original

was

(kernel
value

restored and then the program was continued using

desired.

mode).

instructions

can

access

these

registers.

3.6

ENTERING OF OCTAL DIGITS

console

ODT

PS<15:14>

was

exists

the

the P command.

If PS<15:14> are set to 01, another unique register
processor, but is reserved for future DIGITAL use.

The floating point accumulators, which are
cannot be accessed from console ODT.

The

Then

also in the MMU chip,
Only floating point

When the user is specifying an address or data, console ODT will
use the last six octal digits if more than six have been entered.
The user need not enter leading 0s for either address or data;
entered,

the

displayed.

forces

0Os

low-order

bit

the
is

default.

ignored

and

full

odd

address

1is

16-bit

words

are

3.7

ODT

TIMEOUT

3.8

INVALID

Console

ODT

If the user specifies a nonexistent address or causes a parity
error, console ODT responds to the error by printing ?<CR><LF>d.

commands.

CHARACTERS

will

recognize

Any

character

unintentionally

destroying

upper-

that

and

console

lowercase

ODT

does

characters

not

recognize

during a particular
sequence
is
echoed
(with
the
exception of
ASCII 0, 2, 10, or 12 as noted earlier) and console ODT prints a
?<CR><KLF>@.
Console ODT has ten internal states, each of which
has its own set of valid input characters.
When in a particular
state, only commands specific to that state are valid
(see Table
3-2).
This
was
done
to
lower
the
probability
of
a
user
a

program

pressing

the

wrong

Kkey.

CHAPTER 4

LSI-11

BUS

4.1

INTRODUCTION
processor,
memory
and
bidirectional
signal
1lines
Addresses,
data,
and
control

The

I/0
devices
communicate
via
38
that
constitute
the
LSI-11
bus.
information
are
sent
along
these
some of which contain time-multiplexed information.
functionally divided as follows.

signal lines,
lines are

The

Data/address

Data

3
6

Most
a

transfer

BSYNC,

BWTBT

Direct

memory

Interrupt

BIRQ7

System

control

bus

signals

(high)

signal

high-impedance

bus

asserted

state

BDAL<17:00>

control

lines

access

control

BIRQ6,

LSI-11

negated

lines

are

BBS7,

BDCOK,

and

when

open

bus

BEVNT,

Devices

receivers

BDIN,

lines

BIAK,

and

BRPLY,

BDMR,

BSACK

BIRQ4,

BINIT,

use

connect

BIRQS5,

BPOK,

BREF

terminations

collector

driver

BDOUT,

BDMG,

BHALT,

bidirectional

level.

produced

these

for

lines

via

drivers.

asserts

the

The

line

low.

Although bidirectional
1lines are electrically bidirectional
(any
point along the line can be driven or received), certain
lines are
functionally unidirectional.
These lines communicate to or from a
bus
master
(or
signal
source),
but
not
both.
Interrupt
Acknowledge
(BIACK)
and Direct Memory Access Grant
(BDMG)
signals
are

physically

unidirectional

daisy-chain

fashion.

These

signals originate at the processor output signal pins.
Each 1is
received on device input pins
(BIAKI or BDMGI)
and conditionally
retransmitted

signals

via

are

device

received

retransmitted

(Priorities

discussed

are

output

from

1lower

pins

(BIAKO

any

time,

there

BDMGO) .

priority

devices

along

Paragraphs

4.3

and

Master/Slave Relationship
Communication
between
devices
on
the
bus
master/slave relationship exists throughout
At

higher

one

device

DMA

device)

that

These

and
the

are
bus.

4.4.1.)

is
asynchronous.
A
each bus transaction.

has

control

the

bus.

This controlling device
is termed
the
"bus master."
The master
device controls the bus when communicating with another
device on
the
bus,
termed
the
"slave."
The
"bus
master”
(typically
the

KDF11-AA

The

processor

"slave

progress

device"

and

responds

receiving

data

initiates

acknowledging

from,

bus

the

transaction.

transaction

transmitting

data

to,

in
the

bus master.
LSI-11 bus control signals transmitted or received by
the
bus
master
or
bus
slave
device
must
complete
the
sequence
according to bus protocol.

The processor controls bus arbitration (i.e., who becomes bus
master at any given time). A typical example of this relationship
is the processor, as master, fetching an instruction from memory
Another example is a disk, as master,
(which is always a slave).
Any device except the
as slave.
memory
to
transferring data
on the circumstances.
g
dependin
slave
or
processor can be master
d so that for each
interlocke
is
bus
LSI-11
the
Communication on
there must be a
device,
master
the
by
issued
control signal
It 1is
transfer.
the
complete
to
order
in
slave
the
from
response
the master/slave signal protocol that makes the LSI-11 bus
The asynchronous operation precludes the need for
asynchronous.
synchronizing with,

and waiting for,

clock pulses.

Since bus cycle completion by the bus master requires response
from the slave device, each bus master must include a timeout
error circuit that will abort the bus cycle if the slave device
does not respond to the bus transaction within 10 microseconds.
The KDF11-AA has a bus timer to restart the clock when no device
An
responds to BDIN L or BDOUT L within 10 microseconds.
immediate

trap to

location

occurs.

The actual time before a timeout error occurs must be longer than
the reply time of the slowest peripheral or memory device on the
bus.

4.2

DATA TRANSFER BUS CYCLES

Data transfer bus cycles are as follows.

Bus Cycle
Mnemonic

Description

DATI

Data word

DATIO
DATIOB

Data word input/output
Data word input/byte output

DATO
DATOB

input

Data word output
Data byte output

Function (with respect
to the bus master)
Read

Write
Write byte

Read-modify-write
Read-modify-write byte

These bus cycles, executed by bus master devices, transfer 16-bit
words or 8-bit bytes to or from slave devices.
signals are used in a data transfer operation.

The following bus

Mnemonic

Description

Function

BDAL<17:00> L

18 Data/address lines

BDAL<15:00> L are used for

transfers.
byte
and
word
BDAL<17:16> L are used for

addressing,
extended
and
memory parity error,
memory parity error
functions.

enable

Mnemonic
BSYNC
BDIN

Description

Synchronize

Data

input

output

BDOUT

Data

BRPLY

Write/byte

BWTBT

BBS7

Data

transfer

DATI,

DATO(B)

bus

Function

master

portion

bus

cycles

and

the

bus

4.2.1

Bus

Before

initiating

Cycle

Control

signals

select

can

DATIO(B).

one

signals

strobe

control

Bank

and

Strobe
strobe

slave

reduced

These

device

three

transactions

selected

basic

occur

during

the

cycle.

types;

between

the

addressing

Protocol

a bus cycle,
the previous bus
transaction must
have been completed
(BSYNC L negated)
and the device must become
bus
master.
The
bus
cycle
can
be
divided
into
two
parts,
an
addressing
portion,
and
a
data
transfer
portion.
During
the
addressing
portion,
the
bus
master
outputs
the
address
for
the
desired
slave device
(memory location or
device
register) .
The
selected
slave device
responds
by latching
the
address bits
and
holding
this condition
for
the duration of the bus cycle
(until

BSYNC

L becomes negated).
During
the data
transfer
portion,
the
actual data transfer occurs.
Paragraphs 4.2.1.2 through 4.2.1.4
describe the data transfer portion of the bus cycle.

4.2.1.1
Device Addressing
- The device addressing portion of a
data transfer bus cycle comprises an address setup and deskew time
and
an
address
hold/deskew
time.
During
the
address
setup and
deskew time the bus master does the following.

Asserts

BDALK17:00>

address

bits

Asserts

BBS7

with

Asserts

During

this

asserted

BWTBT

time
the

the

slave

desired

device

the

cycle

address,

BBS7

and

addressed
3.

the

bus

receiver

for

goes

the

I/O

DATO(B)

page

bus

BWTBT

least

slave

L
ns

device

being

cycle

signals
before

are

BSYNC

active.
Devices in the I/O page ignore the five high-order
address bits BDAL<17:13> and instead decode BBS7 L along
with the
thirteen
low-order
address
bits.
An
active
BWTBT
L
signal

indicates

BWTBT

The

that

indicates

address

DATO(B)

DATI

hold/deskew

operation

follows,

DATIO(B)

operation.

time

begins

after

BSYNC

while

inactive

asserted.

to
The slave device uses the active BSYNC L bus receiver output
al
intern
clock BDAL address bits, BBS7 L and BWTBT L, into itsactive for
logic. BDALK17:00> L, BBS7 L, and BWTBT L will remain
25 ns (minimum) after the BSYNC L bus receiver goes active. BSYNC
I remains active for the duration of the bus cycle.

for
Memory and peripheral devices are addressed similarly except
eral
periph
sed
the way the slave device responds to BBS7 L. Addres
Addressed
devices must not decode address bits on BDAL<K17:13> L. BBS7
L is
when
only
cycle
peripheral devices may respond to a bus

When
asserted (low) during the addressing portion of the cycle.
the
in
resides
address
device
asserted, BBS7 L indicates that the
y
generall
devices
Memory
space).
1/0 page (the upper 4K address

do not respond to addresses in the I/O page; however, some system
applications may permit memory to reside in the I/0 page for use

as DMA buffers, read-only-memory bootstraps or diagnostics, etc.
4.2.1.2 DATI (Figures 4-1 and 4-2) - The DATI bus cycle is a read
Data
During DATI data is input to the bus master.
operation.
During the data
consists of 16-bit word transfers over the bus.
transfer portion of the DATI bus cycle the bus master asserts BDIN
The slave device
L 100 ns minimum after BSYNC L 1is asserted.
responds to BDIN L active in the following ways.

Asserts BRPLY L after receiving BDIN L and 125
(maximum) before BDAL bus driver data bits are valid

Asserts BDAL<17:00> L with the addressed data and error
information

When the bus master receives BRPLY L, it does the following.

Waits at least 200 ns deskew time and then accepts input
data at BDAL<17:00> L bus receivers.

BDAL<K17:16> L are

used for transmitting parity errors to the master.
to Paragraph 4.2.2 for more details.

Negates BDIN
(maximum)

150

(minimum)

after BRPLY L goes active.

Refer

2 microseconds

ng BRPLY L
The slave device responds to BDIN L negation by negati
BRPLY L must be
and removing read data from BDAL bus drivers.
negated 100 ns (maximum) prior to removal of read data. L. The bus
master responds to the negated BRPLY L by negating BSYNC

Conditions for the next BSYNC L assertion are as follows.
BSYNC [ must remain negated for 200 ns (minimum).
1.

BSYNC

[

must

not

become

previous BRPLY L negation.

asserted

within

300

NOTE

Continuous assertion of BSYNC L retains
control of the bus by the bus master,
and
the
previously
addressed
slave
device remains selected.
This is done
for
DATIO(B)
bus cycles where DATO or
DATOB
follows
a
DATI
without
BSYNC
L
negation and a second device addressing

operation.

Also,

slow

slave

device

can hold off data transfers to itself by
keeping
BRPLY
L
asserted,
which
will
cause
the
master
to
keep
BSYNC
L
asserted.
BUS MASTER

SLAVE

{PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE MEMORY
* ASSERT BDAL <15:00>

LWITH

ADDRESS AND

e ASSERT BBS7 IF THE ADDRESS
ISIN THE 124 - 128K WORD RANGE

ASSERT BSYNC L

—_—
—_—

—

T
DECODE ADDRESS

STORE”DEVICE SELECTED"”
OPERATION

REQUEST DATA

*«

/ /

REMOVE THE ADDRESS FROM

BDAL < 15:00
> L AND NEGATE BBS7
L
+

ASSERT BDIN L

—_—
—

INPUT DATA

e
___-*

PLACE DATA ON BDAL <

15:00:-

ASSERTBRPLY L

—

TERMINATE INPUT TRANSFER

ACCEPT DATA AND RESPOND

BY NEGATING BDIN L

—_—
\

—_—

TERMINATE BUS CYCLE
s NEGATE BSYNC L

OPERATION COMPLETED
« NEGATE BRPLY L

MR.2321

4.2.1.3

DATO(B)

Figure

4-1

DATI

Bus

(Figures

4-3

and

4-4)

Cycle

DATO(B)

1is

operation.
Data is transferred
in 16-bit words
(DATO)
bytes
(DATOB)
from the bus master to the slave device.
transfer output can occur
after
the addressing portion
cycle
when
immediately
cycle.

BWTBT
L
had
following
an

been
input

asserted
transfer

by
the
part of

write

or
8-bit
The data
of a bus

bus
master,
or
a DATIO(B)
bus

T/R DAL

(4)X

T ADDR
15005 o4
MIN /

T SYNC

(4)

100ns
L——
MIN

200 ns MAX

R DATA

><7

(4)

CLOCK

— ! 100ns MIN

8us MAX

DIN

DATA

o2000nsMAX

200ns

MIN —»

V—300ns MIN —
R RPLY

BS7

T WTBT

R/T DAL

JL—/
"‘ 15 Ons MMIN | -—

l-—lOOns MIN

(4)

(4) X\

(4)

XR ADDR x
25ns

—1

R SYNC

MIN

TIMING AT

MASTER DEVICE

(4)

—»

ns MAX

—>

100 ns MAX, O ns MIN

T RPLY

/
150ns MIN

\
\

’4———300 ns MIN ————»

\)\
4-]

(4)

l—————-——150ns MIN
—

MIN

DIN

le—125

T DATA

Oons MIN
— |———»

75ns

fe— 75ns MIN

BS7

(4)

R WTBT

(4)

L 25ns MIN

(4)
TIMING AT SLAVE DEVICE

NOTES:
1

Timing shown ot Master and Slave Device
Bus Driver inputs and Bus Receiver Outputs.

. Signal name prefixes are defined below:
T
R

Bus Driver Input
Bus Receiver Qutput

Bus Driver Output and Bus Receiver Input

signal names include a "B'' prefix.

Don't care condition.
MR-2322

Figure

4- 2

DATI

Bus

Cycle

Timing

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
¢ ASSERT BDAL «<15:00>

L WITH

ADDRESS AND
*

ASSERT BBS7 L

IF ADDRESSIS

IN THE 124 - 128K WORD RANGE
»

ASSERT BWTBT L (WRITE

CYCLE)

ASSERT BSYNC L

\
—

—_—

_—
/

DECODE ADDRESS

STORE"”DEVICE SELECTED”

OPERATION

OUTPUT DATA
»

REMOVE THE ADDRESS FROM

BDAL < 15:00
> L AND NEGATE BBS7 L
AND BWTBT L

PLACE DATA ONBDAL < 15:00>

ASSERT BDOUT L
—_—

T~
TAKE DATA

RECEIVE DATA FROM BDAL
LINES

- -

TERMINATE OQUTPUT TRANSFER

NEGATE BDOUT L {AND BWTBT L

e«

REMOVE DATA FROM BDAL <15:00>

— * ASSERT BRPLY L

ADATOB BUS CYCLE)
L\ _
—_—

T OPERATION COMPLETED
__—*
——

TERMINATE BUS CYCLE
e

NEGATEBRPLY L

/ /

NEGATE BSYNC L
MR-2323

Figure

The

data

setup

During
data

the

transfer

and

the

time

data

setup

BDAL<16:00>

DATO

portion

deskew

transfer

4-3

and

and
at

word

of
a

DATOB

DATO(B)

data

deskew

least

hold

transfer.

bus
and

time,

100

Bus

Cycle

cycle

deskew

the

bus

master

after

BSYNC

comprises

data

time.

word

outputs

the

asserted

transfer,
the
bus
master
negates
BWTBT
L
at
least
100
ns
after
BSYNC
L
assertion.
BWTBT L
remains negated
for
the
1length
of
the
bus
cycle.
If
the
transfer
is
a
byte
transfer,
BWTBT
L
remains
asserted.
If
it
is
the
output
of
a
DATIOB,
BTWBT
L
becomes
asserted and lasts the duration of the bus cycle.
During a byte

4’1 Ons

DAL

(4)

l__

T ADDR
150ns
MIN

T DATA

100ns ’.

100ns
MIN

"I/M«N

DOUT

150ns MIN

BS7

]
T

WTBT

150 ns MIN

100ns

MIN

(4)

—’1/\|‘— \7[—-——— 300 ns MIN ~————
~

RPLY

ASS ERTION = BYTE

L150 ns MIN{ 100ns L—

——’l 100 ns MIN L—

MIN

TIMING AT

DAL

(4)

X R ADDR X

——
25ns MIN
/J

SYNC

R DATA

DOUT

BS7

(4)
25ns

WTBT

lfe—— 100 ns MIN —AfiL———ISOnsMIN—v
———| 150 ns MIN 4—\\

ML—

le———— 300ns MIN ———+
\\\

MIN

RPLY

L725nsM|N
\

MIN

‘bl 75 ns MIN
R

——

25ns

25ns .
T

MASTER DEVICE

MIN

75ns

/
175 ns MIN/Z—F— 200ns MIN ———

SYNC

" MAX }

(4)

8us

MIN l‘—

-—

MIN +

(4)

—>

ASSERTION = BYTE

r—ZS ns MIN

(4)

25ns MIN

75ns
MIN

TIMING AT SLAVE DEVICE

NOTES:

Timing shown at Master and Slave Device

Bus Driver Inputs and Bus Receiver Outputs.
Signal nam e prefixes are defined below:

Bus Driver Input

Bus Receiver Output

Bus Driver Qutput and Bus Receiver Input

signal names include a "B" prefix.

. Don't care condition.

Figure

4-4

DATO

DATOB

Bus

Cycle

Timing

transfer, BDAL 00 L selects the high or low byte.
while in the addressing portion of the cycle.
If
high byte
(BDAL<15:08> L)
1is selected;
otherwise,

This occurs
asserted,
the
the low byte

(BDALK07:00>
will force a

L)
1is selected.
An asserted BDAL 16 L at this time
parity error to be written into memory if the memory
is
a
parity-type
memory.
BDAL
17
L
is
not
used
for
write
operations.
The bus master asserts BDOUT L at least 100 ns after
BDAL
and
BWTBT
L
bus
drivers
are
stable.
The
slave
device
responds by asserting BRPLY L within 10 microseconds to avoid bus
timeout.

This

completes

the

data

setup

and

deskew

time.

During the data hold and deskew time the bus master receives
L and negates BDOUT L.
BDOUT L must remain asserted for at
150

from

master.

100

the

receipt

BDAL<17:00>

after

BDOUT

BRPLY

bus

before

drivers

negation.

being

remain

The

bus

negated

asserted

master

then

for

BRPLY
least

the

negates

bus

least

BDAL

inputs.

During this time, the slave device senses BDOUT L negation.
The
data 1s accepted and the slave device negates BRPLY L.
The bus
master responds by negating BSYNC L.
However, the processor will
not negate BSYNC L for
at least 175 ns after negating BDOUT L.
This completes the DATO(B) bus cycle.
Before the next cycle BSYNC
L

must

remain

unasserted

for

least

200

ns.

4.,2.1.4
DATIO(B)
(Figures
4-5
and
4-6)
The
protocol
for
a
DATIO(B)
bus
cycle
1is
identical
to
the
addressing
and
data
transfer
portions
of
the
DATI
and
DATO(B)
bus
cycles.
After
addressing the device, a DATI cycle is performed as explained in
Paragraph
4.2.1.2;
however,
BSYNC
L
is
not
negated.
BSYNC
L
remains active for an output word or byte transfer
[DATO(B)].
The
bus master
maintains
at
least
200
ns
between
BRPLY
L negation
during
the
DATI
cycle
and
BDOUT
L
assertion.
The
cycle
1is
terminated when the bus master negates BSYNC L, which is the same
as described for DATO(B).
4.2.2
The

Parity

KDF11-AA

114,

one

BDAL

Protocol

recognizes

occurs.

memory parity errors and traps to location
parity error detection occurs during every

after

DAT? or DATI portion of a DATIO(B) cycle.
to

and

BDAL

BDALK15:00>

detection
error and

BDAL

200

The processor samples

deskew

interpreted

time

similar

parity

hardware then asserts BDAL 17 L during the BDIN L
cycles to inform the processor or bus master that

1is

enabled.

asserted

system
parity

power—-up,
memory
error
signals may

known

data

1is

the

error
signal from memory and BDAL 17 L is interpreted as a parity error
enable signal from an external parity controller module.
BDAL 17
L is used by software to enable parity detection which is done by
addressing a parity
status
register
on
the
LSI-11
bus.
Parity

status register
portion of DATI

written

BDAL
the
may

be
into

selected

used
memory

to
indicate a parity
at REPLY time.
Upon

contain
random
data
and
erroneous
issued
(BDAL 16 L asserted).
Until

memory,

software

keeps

BDAL

negated,
to
avoid
false
traps.
After
known
data
and
correct
parity have been written into memory,
software can enable parity
detection in the parity status register.
If both BDAL 16 L and
BDAL

17
location

L
are
asserted
114,
will occur.

L will cause memory to
maintenance purposes.

time,
an
abort
and
trap
to
assertion of BDAL 16 L during BDOUT

The

write

wrong

parity

diagnostic

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE}

(MEMORY
OR DEVICE)

tool

ADDRESS DEVICE/MEMORY

ASSERT BDAL < 15:00> LWITH

ASSERT BBS7 L AND IF THE

ADDRESS

ADDRESS IS IN THE 124 - 128K WORD RANGE
®

ASSERT BSYNC L
—
——

—

——

B ECODE ACDRESS
e

STORE “DEVICE SELECTED"

OPERATION

REQUEST DATA
e

REMOVE THE ADDRESS FROM

ASSERT BDIN L

BDAL < 15:00 > L
——

— % uPUT DATA

TERMINATE INPUT TRANSFER
e

PLACE DATA ON BDAL < 15:00 > L

ASSERT BRPLY L

ACCEPT DATA AND RESPOND BY
TERMINATING BDIN L
—

—_

COMPLETE INPUT TRANSFER
e

REMOVE DATA

NEGATE BRPLY L

o —

OUTPUT DATA
e

PLACE OUTPUT DATA ON BDAL < 15:00
> L

(ASSERT BWTBT L IF AN OUTPUT

ASSERT BDOUT L

BYTE TRANSFER)
\\\;

TAKE DATA
e

RECEIVE DATA FROM BDAL LINES

ASSERT BRPLY L

TERMINATE OUTPUT TRANSFER
REMOVE DATA FROM BDAL LINES
e
e

NEGATE BDOUT L

OPERATION COMPI_ETED

®
.

TERMINATE BUS CYCLE
e

NEGATE BRPLY L

am—

a—

NEGATEBSYNC L

(AND BWTBT L IFIN
A DATIOB BUS CYCLE)
MR.-2324

Figure

4-5

DATIO

DATIOB

Bus

Cycle

for

,.,
R/T DAL

]-—150 ns MIN

(4)><TADDR ><
100ns
MIN_’ [—

4-‘

(4)

>(R DATA y
200ns
—fi MA X

(4)

T DATA

‘

r—Ons MIN

>(
(4)
L
!
—
100 ns MIN

100 ns MIN‘—l r— N RS

SYNC

l@— 200ns MIN

T DOUT

la— |50 ns MIN—-I
T

DIN

RPLY

150 ns

"] MIN [*
T

200 ns MIN —

/L/

MIN

300ns

BS7

—

—| 100 ns MIN ‘4—

l¢— {00 ns MIN

(4)

ASSERTION=BYTE

(4)

[¢— 150 ns MIN

TIMING

RADDRX

-T

l<—25ns MIN

X T DATA

MASTER DEVICE

(4)

‘

SYNC

R DATA

— LZSns MIN

‘4—100ns MAXJ

(4)

75nsMIN125

—

DOUT

25ns MIN

(4)

\
l‘—

—»{ 100
ns MIN

"s [*
MAX

150ns MIN e

| 5O ns MIN —
lfe—
‘\\.\

DIN

ld-—150ns MIN—> /4—3oonsM|N——>

RPLY

re— 75ns MIN
R

BS7

’)1( le— 25ns MIN

le— 75 ns MIN

R WTBT (4>\

ASSERTION = BYTE

(4}
25ns MIN
TIMING AT SLAVE DEVICE

NOTES:

Timing shown at Requesting Device

Signal name prefixes are defined below:

Bus Driver Inputs and Bus Receiver Outputs.

Bus Driver Input
Bus Receiver Qutput

Bus Driver Output and Bus Receiver Input

Don't care

signal names include a "B" prefix.
condition

DATIO or

DATIOB Bus Cycle

4-6

Figur e

—

|<725ns MIN

(4)

4.3
DIRECT MEMORY ACCESS
The
direct
memory
access
(DMA)
capability
allows
direct
data
transfers
between
I/0 devices
and memory.
This
1is
useful when
using mass storage devices (e.g., disks)
that move large blocks of
data
to
and
from memory.
A DMA device only needs
to
know the
starting address in memory, the starting address in mass storage,
the
length of
the transfer and whether
the operation is read or
write.
When
this
information
is
available
the
DMA
device
can
transfer
data
directly
to
(or
from)
memory.
Since
most
DMA
devices must perform data
transfers
in
rapid
succession or
lose
data, DMA devices are provided the highest priority.
DMA

1is

passed

accomplished

after

the

processor

the

highest

mastership

requesting

the

bus.

The

processor

grants

bus

DMA

device

processor.

the

bus
the

it relinquishes
used during bus

its mastership.
arbitration.

The

DMA

Grant

Input

DMA

Grant

Output

DMA

Request

Bus

Grant

L
L

Protocol

DMA

(Figures

transaction

4-7

can

relinquish

master)

device

all

requests

electrically

master

following

that

closest

indefinitely

control

has
is
and
to

until

signals

are

Line

Acknowledge

and
be

phase.

4-8)

divided

mastership acquisition phase,
mastership

bus

DMA

arbitrates

located

remains

BDMGO
BSACK

DMA

device

BDMGI

BDMR

the
DMA

(normally

priority

into

three

phases:

the data transfer phase,

and

the

bus

the bus

During

the bus mastership acquisition phase, a DMA device reguests
the bus by asserting BDMR L.
The processor arbitrates the request
and initiates the transfer of bus mastership by asserting BDMGO L.
The maximum time between BDMR L assertion and BDMGO L assertion is
DMA
latency.
This
time
1is
processor-dependent
and
1is
3.5
microseconds for the KDF11-AA.
BDMGO L/BDMGI L is one signal that

is daisy-chained through each module 1in the backplane.
It
1is
driven out of the processor on the BDMGO L pin, enters each module
on the BDMGI L pin and exits on the BDMGO L pin.
This signal
passes through the modules in descending order of priority until
it is stopped by the requesting device.
The requesting device
blocks the output of BMDGO L and asserts BSACK L.
If no device
responds to the DMA grant the processor will clear. the grant and

rearbitrate

will

the

hung

cleared

after

bus.

(the

If BDMR L

grant

signal

will

BSACK L occurs,

and

continuously
keep

passing

asserted,
down

be driven again

rearbitrated).
NOTE

The KDF1l1-AA
clears BDMGO
no

BSACK

uses a no-SACK timer which
L after 12 microseconds if

has

been

received.

the

after

the

bus,

bus
be

the bus

KDF11-AA PROCESSOR

BUS MASTER

(MEMORY IS SLAVE)

(CONTROLLER)

REQUEST BUS

GRANT BUS CONTROL

¢ NEAR THE END OF THE

= o

—

~—

——

—

_—

o ASSERT BDMR L

CURRENT BUS CYCLE

(BRPLY
L IS NEGATED),
ASSERT BDMGO L AND

—~

INHIBIT NEW PROCESSOR

GENERATED BYSNC L FOR
THE DURATION OF THE

—~

ACKNOWLEDGE BUS
> MASTERSHIP

DMA OPERATION,

_—

BSYNC
L AND BRPLY
L

TERMINATE GRANT

* RECEIVE BDMG

'« WAIT FOR NEGATION OF
»

ASSERT BSACK

* NEGATE BDMR L

SEQUENCE
o

NEGATE

BDMGO

L AND

WAIT FOR DMA OPERATION TM

—_

TO BE COMPLETED

o~
—

EXECUTE A DMA DATA
TRANSFER
« ADDRESS MEMORY AND

TRANSFER
UP TO 4 WORDS

OF DATA AS DESCRIBED
FOR DATI, OR DATO BUS

CYCLES

_—

« RELEASE THE BUS BY

TERMINATING BSACK L

FESUME

PROCESSOR

(NO SOONER THAN

—

OPERATION

NEGATION

LAST BRPLY

L) AND BSYNC L.

ENABLE PROCESSORGENERATED BSYNC L

(PROCESSOR IS BUS

WAIT 4 us OR UNTIL

MASTER) OR ISSUE

ANOTHER FIFO TRANSFER

ANOTHER GRANT |F BDMR

L IS ASSERTED.

REQUESTING BUS AGAIN

PENDING BEFORE

MR .3689

Figure

During
BSACK

the
L.

Paragraphs

data
The

4-7

transfer

phase,

Request/Grant

the

DMA

data

transfer

through

4.2.1.4.

actual

4.2.1.2

DMA

Sequence

device

continues

performed

NOTE

multiple-data

transfers are performed
phase, consideration must be

during this
given to
the use of the
system functions, such as
(if required).

bus for other
memory refresh

asserting

described

—-I
T

SECOND
REQUEST

le— DMA LATENCY
7"‘7_/_/'_7"7‘7"7"7 =7 =7

DMR

—>

L-Ons MIN.
L

R DMG

7‘7"7

AN
U

T SACK
<<<s\m\~.——\; \

R/T SYNC

I-—

——_J
O ns MIN-—DI

R/T RPLY

\\\ \\\

T DAL

fe—

ns MIN
0O ns
MIN

—»
(ALSO BS7,
WTBT, REF)

r\— 300 ns MAX

—

—»

ADDR

DATA

"_ 100 ns
ns MAX
\

NOTES 1.

Timing shown at requesting device bus driver inputs and bus receiver outputs.

Signal name prefixes are defined below:

T = Bus Driver Input
R = Bus Receiver Qutput

Figure

The DMA device
(minimum) after
becomes

4-8

DMA

Request/Grant

can assert BSYNC
it receives BDMGI

L for a data transfer
250 ns
L and its BSYNC L bus receiver

negated.

During the bus mastership relingquish
relinquishes
the bus by negating BSACK
completing
negated).
negating
4.4

Timing

(or aborting)
the last
BSACK L may be negated

BSYNC

phase
the DMA device
L.
This occurs after

data transfer
cycle
(BRPLY L
up to 300 ns (maximum) before

INTERRUPTS

The interrupt capability of the LSI-11 bus allows any 1/0 device
to temporarily suspend (interrupt) current program execution and
divert processor operation to service the requesting device.
The

processor

inputs

vector

from

the

device

start

the

service

routine
(handler).
Like the device register
address,
hardware
fixes the device vector at locations within a designated range

(below
of

location
addresses.

processor

The

and

content

(PS).

The

001000).
The vector indicates the
The content of
the
first address
1is

the

new

when

address

the

new

interrupt

processor

handler.

status

can

raise the interrupt priority level,
level
interrupts from breaking
into the

preventing lower
interrupt service
program

starting

second

first of a pair
is
read by the

routine.

the

Control

interrupt

returned

handler

1is

the

ended.

(interrupted)
program's
address
(PC)
and
its
stored on a
"stack."
The original
PC
and
PS

word

thereby
current

interrupted

The

original

associated
PS
are
are restored by a

return from interrupt
(RTI or RTT)
instruction at the end of
the
handler.
The use of the stack and the LSI-11 bus interrupt scheme
can
allow
interrupts
to
occur
within
interrupts
(nested

interrupts),

depending

Interrupts

can

operations

can

also

interrupts

are

called

errors,

hardware

the

caused

the

LSI-11

bus
following.

from

"traps."

errors,

signals

bus

within

Traps

special

that

BIRQ4 L

are

used

options.

the

are

These
programming

and

maintenance

caused

instructions

Interrupt

processor.

interrupt

transactions

Interrupt

request

BIRQ6

priority

level

Interrupt

request

BIRQ7

priority

level

Interrupt

request

priority

level

BIAKI

Interrupt

acknowledge

BIAKO

input

Interrupt

acknowledge

output

BDIN

4.4.1

Data/address

BRPLY

Data
L

strobe

Priority

bus

supports

priority.
1.

input

lines

Device

LSI-11

are

Interrupt request priority level 4

BIRQS5

BDAL<K15:00>

The

LSI-11

originate

features.

The

PS.

the

following

two

methods

device

Distributed

arbitration - Priority levels are implemented
the
hardware.
When devices of equal
priority level
request
an
interrupt,
priority
is
given
to
the
device
electrically closest to the processor.
on

Position-defined
by

electrical

device

The

KDF11l-AA

four

levels

each

arbitration

solely

1level.

uses

the

both

priority

processor,
the

and
Interrupts

position

Priority

the

distributed

the

higher

bus.

its

determined

The

closer

priority

is.

arbitration
method
with
position-defined
arbitration
within
on
these
priority
1levels
are

enabled/disabled by bits in the processor
Single-level interrupt (position-defined)
in

KDF11-AA

4.4.2

status word
devices can

(PS<07:05>).
also be used

systems.

Interrupt Protocol

(Figures

4-9

Interrupt protocol
has
interrupt acknowledge

three
phases:
and
priority

interrupt

phase.

vector

transfer

and

4-10)

interrupt request phase,
arbitration phase,
and

PROCESSOR

DEVICE
INITIATE REQUEST

.—* ASSERT BIRQ L
——

STROBE INTERRUPTS

—_

ASSERT BDIN L

——

e—

\ S—~

RECEIVE BDIN L
»

‘

STORE “INTERRUPT SENDING

IN DEVICE

GRANT REQUEST
¢

PAUSE AND ASSERT BIAKO L

—__
T

\ —RECEIVE BIAKI L
e

RECEIVE BIAKI L AND INHIBIT

PLACE VECTORON BDAL < 15:00
> L

BIAKO L

ASSERT BRPLY L

__*

NEGATE BIRC L

i
J—

RECEIVE VECTOR & TERMINATE
REQUEST

INPUT VECTOR ADDRESS

NEGATE BDIN L AND BIAKO L
\

\ —.
COMPLETE VECTOR TRANSFER
e«
_ e

REMOVE VECTOR FROM BDAL BUS
NEGATZBRPLY L

[

PROCESS THE INTERRUPT

SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK

LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION

EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE
MH

Figure

4-9

Interrupt Request/Acknowledge

1182

Sequence

INTERRUPT LATENCY
MINUS SERVICE TIME
T

IRQ

‘>1

R DIN

150
ns MIN.

j&—

R TAKI

////////,,,___

T RPLY

j\\i
——4 125 ns MAX. fe—

T DAL

R SYNC

(UNASSERTED)

BS7

><7

kAOOnsMAx
VECTOR

j}(

(4)

NOTES:
1.

Timing shown at Requesting Device Bus Driver Inputs and Bus Receiver Qutputs
.

Signal Name Prefixes are defined below:
T = Bus Driver Input

R = Bus Receiver Qutput

3. Bus Driver Output and Bus Receiver Input signal names include a "B" prefix.

4. Don't care condition
MR

Figure

The

interrupt

4-10

request

specific
conditions
device
1is
"ready,"

Interrupt

phase

Protocol

begins

when

1187

Timing

meets

its

for
interrupt
requests.
For
example,
"done,"
or
an
error
has
occurred.

device

the
The

interrupt enable bit in a device status register must be
device
then
initiates
the
interrupt
by
asserting
the

set.
The
interrupt

request
line(s).
BIRQ4
L
1is
the lowest hardware priority level
and is asserted for all interrupt requests for compatibility with
previous LSI-11 processors.
The level a device is configured at
must

also

which must
discussion

asserted.

also assert
involving

special

level
the

case

6.
See
4-level

explanation.

4-17

exists

for

level

devices

item 2 of the arbitration
scheme
(below)
for
an

The

Asserted
L

Lines
BIRQ4

Level

BIRQ4

BIRQ5

~I O

Interrupt

BIRQ4

BIRQ6

BIRQ4

BIRQ6

interrupt

request

line

remains

asserted

Device

BIRQ7

until

the

request

acknowledged.

During

the

interrupt

the
KDF11l-AA
conditions.

will

The

device

current

The

acknowledge

and

priority

interrupts

interrupt

arbitration

under

priority

phase

following

higher

than

the

PS<07:05>.

The processor has completed instruction
additional bus cycles are pending.

processor

the

acknowledges

the

interrupt

request

execution

and

asserting

BDIN

L,
and
150
ns
(minimum)
later
asserting BIAKO L.
The device
electrically closest to the processor receives the acknowledge on
its BIAKI

this

L bus

point

separately.
4-level

the

two

types

the device

interrupt

that

arbitration

receives

scheme,
it reacts

the

must

acknowledge

discussed

uses

follows.

the

If not requesting an interrupt, the device asserts BIAKO
L. and the acknowledge propagates to the next device on
bus.

the

receiver.

see

the device

that

requesting

level

higher

interrupt

it must check

currently

device

requesting

an interrupt.
This is done by monitoring higher level
The table below lists the lines that need
request lines.
to be monitored by devices at each priority level.

addition

to asserting

must

drive

this

protocol,

monitoring
level

and

level

and

since

devices

levels

This

arbitration by
level

level

and

devices

and
done

level

devices

assert

will

become

aware

very

seldom

are

since they monitor the 1level
has been optimized for levels
level

level

and

5 devices.

need

level

necessary.

the

1In

not

monitor

Level

level

6 request.
4, 5, and 6

7 devices

simplify

reguest

This protocol
devices, since

Device

Priority

Level

Line(s)

BIRQ5,

BIRQ®6

BIRQ7

higher

acknowledge

level
is

device

blocked

Monitored
BIRQ6

requesting

the

device.

interrupt,

(BIAKO

the
not

asserted).
Arbitration logic within the device uses the
leading edge of BDIN L to clock a flip-flop that blocks
BIAKO
L.
Arbitration
is
won
and
the
interrupt vector
transfer

phase

higher

begins.

level

request

1line

1is

active,

disqualifies itself and asserts BIAKO L
acknowledge to the next device along the

Signal
4-level

timing
must
interrupts.

be
<carefully
considered
Refer
to Figure 4-10 for

the

device

to propagate
bus.

the

when
implementing
interrupt protocol

timing.
If

single-level

reacts

interrupt

device

receives

the

follows.

not

requesting

and

the

bus.

the

interrupt,

acknowledge

device

the

propagates

was

acknowledge,

device

requesting

the

asserts

BIAKO

device

interrupt,

the

acknowledge
is blocked using the leading edge of BDIN L
and
arbitration
is won.
The
interrupt
vector
transfer

phase
The

interrupt

The

begins.
vector

device

transfer

responds

phase

asserting

bus driver
inputs
driver inputs must

with
the
be stable

vector
within

The

processor

then

and

BIAKO

The

asserted.

negates

BDIN

100

(maximum)

processor

then

later

enters

enabled

BRPLY

removes

inputs
the

device's

and

BBS7

and

BDIN
its

address
bits.
125 ns (maximum)

device

the

the
processor
arbitration and

address

and

BRPLY

and

address

bits.

routine.

asserted

during
the
interrupt
vector address transfer

assert

BRPLY L within 10
(maximum)
after
the

processor asserts BDIN L.
If the device
does not reply,
the KDF1ll-AA aborts the

interrupt

transaction

The
BDAL
bus
after BRPLY L

vector

operations.

The device must
microseconds

BDAL<K15:00>

negates

vector

not

BIAKI

the

service

are

and

then

NOTE
BSYNC

and

resumes

The

program
execution.
The
aborted
transaction
1is
transparent
to
the
program.
LSI-11 and LSI-11/2 processors
halt in this situation.

4.4.3
4-Level Interrupt Configurations
Users who have high-speed peripherals and desire better software
performance
can
use
the
4-level
1interrupt
scheme.
Both
position-independent and position-dependent configurations can be
used with the 4-level interrupt scheme.

LEVEL
B

DEVICE

|giak

LEVELS5 | BIAK

DEVICE

LEVEL
4 | BiaK

DEVICE

BIAK (INTERRUPT ACKNOWLEDGE)

KDF11

The position-independent configuration
is shown
1in Figqure
4-11.
This
allows
peripheral
devices
that
use
the
4-level
interrupt
scheme to be placed in the backplane in any order.
These devices
must send out interrupt requests and monitor higher level request
lines as described
in Paragraph 4.4.2.
The
level
4
request
1is
always asserted by a requesting device regardless of priority, to
allow compatibility if an LSI-11 or LSI-11/2 processor
1is 1in the
same system.
If
two or more devices of equally high priority
request
an
interrupt,
the
device
physically
closest
to
the
processor will win arbitration.
Devices that use the single-level
interrupt scheme must be modified or placed at the end of the bus
for arbitration to properly function.

LEVEL7

DEVICE

[

BIRQ 4 (LEVEL 4 INTERRUPT
REQUEST)

BIRQ S5 (LEVELS INTERRUPT REQUEST)

BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)

BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)
ME

Figure

4-11

Position-Independent

DHHH

Configuration

The
position-dependent configuration
is
shown
in Fiqure 4-12.
This configuration is simpler to implement.
A constraint is that

peripheral

devices

must

inserted

with

the

highest

priority

device located closest to the processor and the remaining devices
placed in the backplane in decreasing order of priority, with the
lowest priority devices farthest from the processor.
With this
configuration each device only has to assert its own level and
level
4
(for
compatibility
with
an
LSI-11
or
LSI-11/2).

Monitoring higher

level

request lines is unnecessary.

Arbitration

is achieved through the physical positioning of each device on the
bus.
Single-level
interrupt devices on level
4 should be
positioned

last

the

bus.

DEVICE

LEVEL 4

LEVELS | BIAK

DEVICE

LEVEL6 | BIAK

LEVEL7 | BIAK

DEVICE

BIAK (INTERRUPT ACKNOWLEDGE)

KDF11

}

BIRQ 4 (LEVEL 4 INTERRUPT REQUEST)

DEVICE

]

5 (LEVEL 5 INTERRUPT REQUEST)
BIRQ
BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)

BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)

MR 2889

Figure

4.5

The

CONTROL

following

4-12

Position-Dependent

FUNCTIONS

LSI-11

bus

signals provide

BREF L
BHALT L
BINIT L
BPOK

BDCOK

4.5.1

Memory

Refresh

If BREF
is asserted
transfer
cycle,
it

control

functions.

Memory refresh
Processor halt
Initialize
Power

Configuration

power

during
the
address portion of
a bus data
causes
all
dynamic
MOS memories
to
be

simultaneously addressed.
The sequence of addresses required for
refreshing the memories is determined by the specific requirements
for each memory.
The complete memory refresh cycle consists of a
series of refresh bus transactions.
A new address 1is used for
each
transaction.
A
complete
memory
refresh
cycle
must
be
completed within 1
or
2 ms.
Multiple data transfers by DMA
devices must be avoided since they could delay memory refresh
cycles.
The
KDF11l-AA does not perform memory refresh.
For
systems needing memory refresh, an REV11-A or -C may be used to
perform

this

function.

4.5.2

Halt

4.5.3

Initialization

Assertion
of
BHALT
L
stops
program
execution
processor unconditionally into console ODT mode.

and

forces

the

Devices along the bus are initialized when BINIT L is asserted.
The processor can assert BINIT L as a result of executing a RESET

instruction or as part of a power-up sequence.
asserted for approximately 10 microseconds when RESET
4.5.4

Power

status

BDCOK

BINIT L 1is
is executed.

Status

protocol

These

signals

(usually

the power

supply)

controlled

are

and

driven

are

two

defined

signals,

some

BPOK

external

follows.

and

device

BDCOK

The

assertion

for
the

at least 3 ms.
power fails.

this

The

negation

line

Once

this

indicates

asserted

line

that

this

the

line

first

power

has

remalins

event

been

stable

asserted

the

until

power-fail

sequence.
It
indicates
that
only
5
microseconds
of
dc
power
reserve remains.
Once BDCOK H is negated it must remain in this
state for at least 1 microsecond before being asserted again.

BPOK

The
ms

assertion
reserve

least

asserted

this

line

power

and

ms.
for

Once

BPOK

least

indicates
that

that

BDCOK

has

been

there

has

asserted,

Power-Up/Down

power

reserve

Protocol

assert

BINIT

When

other external

least

for

remain

must

the

device

4-13)

KDF1ll-AA
negated.

is failing and that

remains.

(Figure

Power-up protocol
for
the
applies power with BDCOK H
or

asserted

ms.

The negation of this line indicates that power
only

been

begins when
the
This forces the

voltages

asserts

are

BDCOK

stable,

The

the

power
supply
processor to
power

processor

supply

responds

by
clearing
the
PS,
floating
point
status
register
(FPS),
floating point exception register
(FEC).
BINIT L is asserted

and
for

12.6
microseconds
and
processor continues to

The
The

then
negated
test for BPOK

for
110
microseconds.
H until it is asserted.

power
supply
asserts
BPOK
H
70
ms
(minimum)
after
BDCOK
H
1is
asserted.
The
processor
then
performs
its
power-up
sequence.
Normal
power
must
be
maintained
at
1least
3.0
ms
before
a
power-down
sequence
can
begin.
The
KDF1l1l-AA
has
four
power-up
jumper options.
Refer to Paragraph 2.2 for details.

power-down

When

the

sequence

current

a
power-down
Location
24

routine.

f%e

voltages

decay.

instruction

When

the

BPOK

power-up

routine.
contains

end

avoid

processor

signal.

begins

when

instruction

sequence.

power

supply

the

The
KDF1ll-AA
traps
the
PC
that
points

the

any

routine

possible

executes

BPOK
It

the

completed,

the

clears

1is

HALT

internal

to
to

with

corruption

instruction,

the

BPOK

traps

1location
24,.
the
power-down

terminated

memory

negated,

negates

processor

HALT

the

tests

the

processor

enters

the

registers,

generates

BINIT

L and continues to check for the assertion of BPOK H.
If it is
asserted
and
dc
voltages
are
still
stable,
the
processor
will
perform the rest of the power-up sequence.

“*4-20#5

BINIT L

3ms

t——3 ms MIN

BPOK H

MAX

70msMIN fe

BDCOK H
_t;

DC POWER

3ms

MAX

4 ms MIN —»

—-I 70ms MIN L/

MIN

\
1us L7

8 ms MIN

5 us MIN

l4—

\_f
POWER UP

NORMAL

SEQUENCE

POWER DOWN

- POWER ~TM

POWER UP

SEQUENCE

NORMAL

" POWER

NOTE:

Once a power down sequence is started,
it must be completed before a power-up
sequence is started.

Figure

4.6

BUS

This

ELECTRICAL

paragraph

characteristics

4.6.1

4-13

CHARACTERISTICS

contains

the

Signal Level
Input
TTL

Power-Up/Power-Down Timing

High:

Output Logic Levels
TTL Logical Low:
TTL Logical High:

0.4
2.4

electrical

Vdc maximum
Vdc minimum

4.6.2

loads comprise the maximum capacitance
ground, as specified in Paragraph 4.7.

Load Definition

9.35

allowed per signal line
A unit load is defined

capacitance.

4.6.3
DC Load Definition
DC loads are defined as maximum

asserted or

Paragraph

the

0.8 Vdc maximum
2.0 Vdc minimum

AC
to

driver

about

bus.

Specification

Logic Levels
Logical Low:

TTL Logical

information

LSI-11

unasserted.

current

These

allowed

with

limitations

are

signal

line

specified

4.7.

4.6.4
120 Ohm LSI-11 Bus
The electrical conductors interconnecting the bus device slots are
treated
as
transmission
1lines.
A
uniform
transmission
1line,
terminated
in
its
characteristic
impedance,
will
propagate
an
electrical signal without reflections.
Insofar as bus drivers,

receivers and wiring connected to the bus have
nonzero
reactance,
the
transmission
1line

finite

and

resistance
becomes

impedance

nonuniform, and thus introduces distortions into pulses propagated
along it.
©Passive components of the LSI-11 bus
(such as wiring,
cabling
and
etched
signal
conductors)
are
designed
to
have
a
nominal characteristic impedance of 120 ohms.
The

maximum
1length
within the backplane

of
interconnecting
is limited to 4.88 m

cable

excluding
ft).

(16

wiring

NOTES

The
all

KDFll-AA processor
(as well
as
standard DIGITAL-supplied LSI-11

interfaces)
connects to the bus via
special
drivers
and
receivers,
described
in
Paragraphs
4.6.5
and
4.6.6.
2.

The

KDFll-AA
processor
provides
resistive
(220 ohm) pull-up (on all
bused
1lines)
to
3.4
Vdc
for
this
wired-OR interconnecting scheme.

4.6.5
Devices

Bus Drivers
driving the

120

outputs

and

following

meet

the

LSI-11

bus

must

have

open

collector

current:

specifications.

Specifications
Output
1low
maximum

voltage

when

Output

leakage

current

(even
BPOK

high
if

power

sinking

when

applied

connected

them,

except

3.8
for

0.7

Vdc:

BDCOK

and

These

conditions

temperature,

ohm

must

and

input

output

met

signal

worst-case

supply

voltage,

levels.

Specifications
Bus

driver

Propagation
Skew

delay:

(difference

fastest

gate):

Not

capacitive

exceed

load:

propagation

exceed

Not

exceed

ns
time

between

slowest

and

Rise/Fall Times: Transition time from 10% to 90% for positive
transition, and from 90% to 10% for negative transition, must
be no faster then 5 ns.

4.6.6
Bus Receivers
Devices that receive signals
the following requirements.
DC

from

the

120

LSI-11

bus

must

meet

Specifications
Input

low voltage

Input

high

(maximum):

voltage

1.3

(minimum):

1.7

Maximum input current when connected
no power is applied to them.
These

specifications

temperature,
AC

ohm

and

must

output

met

signal

3.8

Vdc:

worst-case

supply

even

voltage,

conditions.

Specifications
Bus

receiver

Propagation

input

capacitance

delay:

Not

Skew
(difference
in
fastest gate): Not to
4.6.7

Bus

Termination

its

propagation
25 ns

exceed

time

between

slowest

and

4-14)

must be
terminated
at each end
by an
This is to be done as a voltage divider

Thevenin equivalent

equal

This
type
of
termination
refresh/boot/terminator, or the

ohms

and

is
provided
BDV11-AA.

+5V

120

3.4
an

V nominal.
REV11-A

+5V

3300

1788
1%

25048

12080

BUS LINE
TERMINATION

3834
S

6800

Figure

Not

exceed

(Figure

The
120
ohm LSI-11
bus
appropriate terminator.

with

exceed

load:

4-14

Bus

Line

MR-2325

Terminations

Each of the several LSI-11 bus lines (all signals whose mnemonics
start with the letter B) must see an equivalent network with the
following
L/BIAKO L

characteristics
at each end
and BDMGI L/BDMGO L, which do

of the bus,
except BIAKI
not require termination.

Input
Open

impedance
circuit

Capacitance

(with

voltage:
Load:

Not

respect

ground):

3.4

Vdc

+5%

exceed

120

ohm

+5%,

-15%

NOTE

The
resistive
termination
provided
by
the
combination
modules
supplies

Dbe
two
processor
module
ground).
Both of

(i.e.,
the
220 ohms to

may
of

these two terminators must be physically
resident within the same backplane.
4.6.8
Bus Interconnecting Wiring
This paragraph contains the electrical
interface.
4.6.8.1 Backplane
device
interface
specifications.
1.

The

Wiring
slots
on

conductors

The
the

must

characteristics

Crosstalk
5%.

between

Note

that

any

the

bus

wiring
that
interconnects
all
LSI-11
must
meet
the
following

arranged

such

that

exhibits a characteristic impedance of 120
with respect to the bus common return).
2.

two

lines

worst-case

must

crosstalk

1is

each

ohms

1line

(measured

greater

than

manifested

by
and

simultaneously
driving
all
but
one
signal
measuring the effect on the undriven line.

1line

DC
resistance
of
signal
path,
as
measured
between
near-end
terminator
and
far-end
terminator
module
(including all
intervening connectors, cables, backplane
wiring,
connector-module etch,
etc.)
must not exceed
2
ohms.

resistance

near-end

common

terminator

return

and

path,

far-end

measured

(including all intervening connectors, cables,
wiring,
connector-module etch,
etc.)
must not
equivalent

ohms

per

composite
signal
return
exceed 2 ohms divided by

signal

between

terminator

path.

module
backplane
exceed an

Thus,

the

path
dc
resistance
must
not
40 bus lines,
or
50 milliohms.

Note that although this common return path is nominally
at ground potential, the conductance must be part of the
bus wiring;
the specified low impedance return path must
be

provided

common

system

the

power

bus

wiring

ground

distinguished

from

path.

4.6.8.2
Intra-Backplane
Bus
Wiring
The
wiring
that
interconnects
the
bus
connector
slots
within one contiguous
backplane is part of the overall bus transmission line.
Due to
implementation

constraints,

the

nominal

characteristic

impedance

120

ohms

may

in excess of
impedance may

not

the
not

achievable.

Distributed

amount required
exceed 60 pF per

4.6.8.3
Power and Ground - Each bus interface
pins assigned for the following dc voltages.*
+5

Vdc

+12

Vdc

Ground

Three

Two

pins

Eight

(4.5

(3.0

pins

maximum

(shared

wiring

capacitance

to achieve the nominal 120
signal line per backplane.

per

power

bus

slot

device

return

and

has

ohm

connector

slot)

signal

return).

NOTE

Power is not bused between backplanes
any interconnecting bus cables.

4.6.8.4

Maintenance

and

Spare

Pins

Maintenance Pins - There are four MSPARE pins per bus device slot
assigned
to maintenance
(AKl1l,
ALl,
BK1l,
BL1l).
The maintenance
pins
on
the
basic
LSI-11
system
are
not
bused
from
module
to
module.
Instead,
at each bus device slot,
the maintenance pins
are

shorted

together
these
used

pins
by

Spare

together

for

during

DIGITAL

Pins

any module

initial

for

Spare

pairs.

These

pins

operate.

This

allows

two

separate

testing

manufacturing

pins

are

tests

allocated

pins
be

are

used

PSPARE

shorted

points.

use

This

the

backplane

follows.

the particular use
test points or
as

communication.
For
intermodule
communication,
wires must be added to the backplane since these

not
as

module

only.

SSPARE - These eight pins are reserved for
of a module or
set of modules,
either
as

intermodule
appropriate

must

the

interconnected

bus

These

any

way.

SSPARE

lines

cannot

connections.
four

pins

are

similar

SSPARE,

except

that

they are located in a manner such that dc voltages will appear
on the pins if a module is inserted backwards.
Use of these
pins
4.7

not

SYSTEM

LSI-11

bus

recommended.
CONFIGURATIONS

systems

can

divided

into

Systems

containing

one

Systems

containing

multiple

two

types.

backplane

backplanes

*The

maximum allowable current per pin is 1.5 A.
+5 Vdc must
regulated
to +5%;
maximum
ripple:
100 mV pp.
+12 Vdc must

regulated

+3%;

maximum

ripple:

200

pp.

be
be

Before

module

configuring
in

the

any

system,

system

must

three

known.

characteristics
These

for

each

characteristics

include:

Power

consumption

Vdc

and

+12

Vdc

current

requirements.

bus

1loading

presents

in terms of act
capacitance.

the

bus

loads

where

bus

1loading

the

module

presents

(undriven).

where

load

one

amount

signal

line.
one

amount

bus

Power consumption, ac loading,
each module are included in the

capacitance

signal

equals

load

equals

when

expressed

module

expressed
pF

1leakage

current

the

1is

high

loads

line

terms

105 microamperes

9.35

(nominal).

and dc loading specifications for
Memories and Peripherals handbook.

NOTE

The
ac
and
consumption

dc
loads
and
the
power
of
the processor module,

terminator module, and backplane must be
included
in
determining
the
total

Ul
e
—

Rules

The

for

bus

loads

backplane.

Configuring

can

Single

accommodate

(total)

required.

end
the

The

before

processor

Backplane

modules

has

that

additional
on-board

Systems

have

(Figure

for

one

termination

1is

of the bus.
If more than 20 ac loads are included,
other end of the bus must be terminated with 120

ohms.

terminated

The

loads

bus

can

accommodate modules

comprising

loads

backplane

can

(total).

can

accommodate

modules

.
(total)

The
cm

bus
(14

signal

in)

lines

long.

the

35.6

BACKPLANE WIRE

35.6 cm

(14in) MAX

)

ONE
UNIT

2209

]

ONE
UNIT

LOAD

ONE
UNIT

LOAD

3.4V

—

20 AC LOADS

20DC

LOADS

PROCESSOR
MR-2326

Figure

Rules

4-15

for

The

Each

Configuring

Single

three

in)

backplane

loads

not

Multiple

backplanes

signal
(10

Backplane

lines

Backplane

may

each

can

compose

the

system.

backplane

can

25.4

to another
will exceed 20 ac loads.
backplanes equally, or with the
first and second backplanes.

modules that have up to 20
loads from one backplane may
backplane if the second backplane

added

loads

(Figure

accommodate
Unused

Systems

1long.

(total).

Configuration

all

modules

all

(total).

desirable

highest

load

loads

backplanes

cannot

exceed

the

Both

ends of the bus must be
terminated with
120
ohms.
This
means
that
the
first
backplane
must
have
an
impedance of 120 ohms (obtained via the processor 220 ohm
terminations and a separate 220 ohm terminator), and the
last backplane must have a termination of 120 ohms.

The cable(s)
61 cm (2 ft)

greater

the
in

first

two

backplanes

1is

length.

The

cable(s)
connecting
the second backplane to the
third
backplane
is
22
cm
(4
ft)
longer
or
shorter
than
the
cable(s)
connecting
the
first
and
second
backplanes.
The

connecting
or

The
of

combined

(16

cables
120

length

both

ft).

used

ohms.

must

have

cables

cannot

exceed

characteristic

4.88

impedance

25.4cm (10in) MAX

[

BACKPLANE WIRE

[

2208

[

]

ONE

UNIT

2208

LOAD

3.4V

20 AC LOADS MAX

PROCESSOR

CABLE/TERM
‘

BACKPLANE WIRE

]

25.4cm(10in) MAX

[

]

ONE

UNIT
LOAD

CABLE

UNIT
LOAD

—

ADDITIONAL

CABLE

20 AC LOADS MAX

CABLES

BACKPLANE WIRE

8 BACKPLANE

) MAX
25.4cm (10in
{{

L
ONE
UNIT
LOAD

ONE
UNIT
LOAD

1208
-+

3.4V

CABLE

20 AC LOADS MAX
NOTES :

1. TWO CABLES (MAX.) 4.88m {16 ft) (MAX )

TERM

TOTAL LENGTH.

2. 20 DC LOADS TOTAL (MAX)
MR-2328

Figure 4-16
4.7.3

Multiple Backplane Configuration

Power Supply Loading

Total power requirements for

obtaining

backplane.

the

total

Obtain

power

separate

each backplane can be determined by

requirements
totals

for

for
+5

each module

and

+12

the

power.

Power requirements for each module are specified in the Memories
and Peripherals handbook.

When

distributing

power

multiple

backplane

systems,

not

Provide
attempt to distribute power via the LSI-11 bus cables.
separate, appropriate power wiring from each power supply to each
Each power supply should be capable of asserting BPOK
backplane.
H and BDCOK H signals according to bus protocol; this is required
if automatic power fail/restart programs are implemented, or if
specific peripherals require an orderly power-down halt sequence.
recommended.

use

BPOK

and

proper

The

BDCOK

signals

1is

strongly

CHAPTER 5
PROCESSOR

5.1
A

FUNCTIONAL

DESCRIPTION

INTRODUCTION

function

block

diagram

of the KDF11-AA is shown in Figure 5-1.
processor
is contained on three MOS/LSI chips.
chip, the control chip and the memory management
unit
(MMU).
The data and control chips are combined in a single
40-pin package.
The MMU is packaged as one 40-pin chip.

The heart of
the
They are the data

The
MOS
chips
communicate
over
two
internal
buses:
the
microinstruction bus (MIB)
and the data address lines (DAL) .
The
MIB
1is
used
for
communication
and
control
among
the
three
MOS
chips and to control the logic circuitry on the processor board.
The
for

DAL

are used
transferring

for

transferring

data

and

the

functions

the

PDP-11

from

between

processor

the

bus.

This

chapter

processor

5.2

discusses

data

status

logic
does

logic

board.

DATA

The

word

the

MOS

chips,

and

the

and

LSI-11

contained

the

CHIP

chip

unit

the

contains
(PS),

several

(ALU),

and

general

working

conditional

registers,

branching

the

processor

arithmetic

logic.

The

data

following.

and

chip

Performs

Handles
all
data
and
address
transfers with the LSI-11
bus
(except relocation, which is handled by the MMU;
see
Paragraph 5.4)

Generates
most
of
the
signals
used
communication and external system control

all

arithmetic

and

logical

functions

for

interchip

typical
microinstruction
cycle
starts
when
the
data
chip
receives a 16-bit microinstruction from the control chip on the
time-multiplexed, bidirectional MIB.
During the first half of the
cycle
the
register
file
1is
precharged,
and
the
selected
register(s)
are
read
and
sent
part
way
through
the
ALU
chain
(i.e.,
operands
are
latched
into
the
propagate
and
generate

latches).

Also

information

decoded

MIB

for

use

other

half

the

cycle

into

the

written
Output

contents

ALU

logic

into

the

not

data

chip

into

half

the

cycle,

microinstruction

and

chips

and

external

During

ALU

occur

the

first

the

directly

written

the

from

operation

appropriate

operations

the

during

completed

the

source

first

the output buffers.
during the first half of

half

the

and

the

second

result

during

selected

logic.

control

output

file

until

the

are

bused

Input

data

cycle

around

when

the

cycle,

the
strobed
although it

the

second

half.

AF2

USEC SEL,

15.08

uODT

DATA

-15:00.-

BDAL4A L

BJ2

BDALS L

BK2

«'17-00tJ~>|>

BDALT L

BDAL3

BH?2

_ POK
L

HALT TRAP OPTION

BDALOL

BDAL2 L

BF2

LOGIC

DRIVERS

BE?

BSIO

BDALG
L

BL2

{7 BDAL7 L

DAL

RECI IVER/

BDALSB L

DRIVER

BDALY L

BDALTO L

o]
1923

BDALYY L

PAR
ERR

CHIP

BDAL12L
BDAL13 L

RESET

BDAL14A L

BV?2

;

LOGIC

BDAL1S L

ACH

BUS

BDALTZ L

AK?2

ERR

. d; d Y.

MMU

CHIP

L
BWTBT

BF1

BDAL CONTROL

X <15.00>

BDALIG L

AD1

DAL 21

BR1

DAL 20

BD1

DAL 19

BC1

DAL 18

AM2

MMU STR H

BSYNC L

AH2
MREPLY L

BDIN{

AE2

BUS

CONTRGOL

BDOUT L

_AF2

LOSIC

BRPLY L

AN2

BIAKO L

= SRUN L
AN1

BN1

COMTROL

AS2

SVC ‘

CONTROL

CHIP

- —

ey e

CHIP

BDMR L

BSACK L
BDMGO L

AL?2

‘”———A;TDD

ENA

ABORT L

DATA

CSEL L

DAL BUS <17:00~

MiB BUS- 15:00.~

AHY, AF1

RESET

wODT -

AV?2

FAST

BBS7 L

AU2Z

FDIN ENA

PWR UP OPTIONS

AB1

BIRQ4 L
BIRQS L
BIRQ6
L

AP2

SERVICE
<12:00.

L
BIRQ7
T
D
AP

LATCH

|
BHALT

BRI

BEVNT
|

BUS ERR

~.15:00>

EB1
MI314/INITF

PONER

UP DOWN

LCGIC

AT?2

CL+

CONTROL

-] BPOK H
BOCOK H

o] BINIT L

BHI

CLK HLD/RESTART

MOSCLK

BA1

INT CLK DISABL
MAN CLK INPUT
[EITERTSIN

Figure

5-1

Processor

Functional

Block Diagram

5.3
The

CONTROL CHIP
control chip contains

the

microprogram

sequence

words of microprogram storage
in programmable
and read-only memory (ROM) arrays.

logic

and

arrays

552

(PLA)

During the course of a normal microinstruction cycle, the control
chip accesses the appropriate microinstruction in the PLA or ROM,
sends
it along the MIB to the data and MMU chips for execution,
and then generates the address for the next microinstruction to be
accessed.
The
next
address
address field associated with

is
constructed
from
either
a
next
the current microinstruction or,
if

a microprogrammed
branch
is
to
be
executed,
contained within
the microinstruction
itself.

the
target
address
The
control
chip

operation
1is
pipelined
for
better
performance
so
that
the
next
microinstruction is being accessed while the current one is being
executed.
This
next
address
is
then
used
in
conjunction
with
various internal status and external
service inputs to determine
the
microprogram
sequence.
The
control
chip
accesses
only
its
local storage.
However, multiple chips (up to 32) can be cascaded

with

external

Chip
CSEL

Select (CSEL)
is an open collector

routed

control

buffering

all

chip

MOS

chips

holds

the

provide

additional

line

with

the

board

low.

line

pull-up
except

microstore.

resistor.

the

MMU.

nonexistent

5.4

MMU
MMU

chip

This

causes

CHIP

chip

serves

two

purposes:

provides

management function, and it provides storage for the
point accumulators and status registers.
This chip
mode

(user

virtual

and

kernel)

address

relocation

the

address,

and
for

contains

bits.

Sixteen-bit

the

then sent on the DAL to replace the original virtual
transmission to the external system bus.
The MMU chip
status

registers

and active page registers
(PAR/PDR
access protection and error detection

also
provides
the
thirty-six
registers needed for operand storage, scratchpad areas, and
information storage during floating point operations.

The

MMU

chip

1is

controlled

microinstruction
chip,
The

memory

FP1ll floating
provides dual

addresses are
received
from
the
data chip via
the data
lines
(DAL),
relocated to the appropriate 18-bit physical

address
address

active

control

selected by the microcode, the line is pulled high.
control chip error and a trap to location 108.

The

CSEL

The

and

KDF1l1l-AA

bus
several

can

would

limited

would

not

capabilities

information

(MIB) from both the data
discrete control inputs.

operate without the
to
32K
words
and

available.

refer

For

Chapter

complete

MMU
the

received

chip

and

the

16-bit
status

the

control

chip; however, the memory
floating
point
registers

details

memory

management

5.5

DATA-ADDRESS

The
DAL
bus
1is
processor board,

LINES

(DAL)

along
the
The 16-bit
DAL bus is time-multiplexed.
During clock-high time, the DAL bus
transfers
data
from
the
data
chip
to
the other
MOS
chips
or
between the processor board and the MOS chips.
During clock-low
time, the DAL bus transfers service data
(external and 1internal
interrupt
requests)
from
the
board
to
the
control
chip.
(The
control chip receives service information and determines whether
to

5.6
The

interrupt

routed
and to

fetch

between
all
the
MOS
chips,
the LSI-11 bus transceivers.

the

instruction.)

MICROINSTRUCTION BUS (MIB)
16-bit microinstruction bus is

common

all

data

and

control

chips.
A subset of the MIB is routed to the MMU because it does
not need access to all MIB control signals.
A different subset of
the
MIB
controls
the
processor
board
1logic.
These
control
functions are discussed in Paragraphs 5.6.1 - 5.6.6.

The MIB is time-multiplexed and is used for different functions
during clock high and low times.
During clock-high time, the MIB
transfers control
information from the data chip to all control
chips, the MMU and the board logic.
During clock-low time,
the
MIB transfers microinstructions from the active control chip to
other control chips and the data chip.
5.6.1

During

MIBl15/Memory Management

clock-high

is an active

MME

low signal.

indicates

relocated-address

asserted

access

time,

low

the

After

(MME)

MME

32K

from

being pulled

processor

than

Enable

carries

microcycle

the

greater

MIB15

should

words

board

MMU chip.

memory

MME

the MMU chip,

logic

performed.

during

the

low by

console

without

that

MME

1is

ODT

using

also

allow

the

MMU

chip.

5.6.2

MIBl4/Initialize

time,

(INIT

During

clock-high

MIBl14

contains

active

low

initialize

during
LSI-11

power-up so that BINIT L is constantly driven onto the
(Refer
bus until DCOK H from the power supply goes high.

At
signal (INIT F) used by the board logic to generate BINIT L.
the end of every clock-high time, the processor monitors INIT F.
If INIT F is asserted low, the processor generates BINIT L onto
the LSI-11 bus.
DINIT L holds the INIT F flip-flop in the 0 state

Paragraph

5.6.3

4.5.4

for

power

protocol.)

MIBl13/Interrupt Acknowledge

(IAK)

MIB13 contains IAK during clock-high time, and is used to generate
The highest priority device that is
BIAK L onto the LSI-11 bus.

requesting

interrupt

LSI-11

bus.

IAK

occurs

5.6.4
These

MIB12, 9, 8/Address-Input-Output (AIO) Codes
three control lines along with two other signals,

signal

its

ENA

the

BDIN

SYNC/DMA

and

assert

input vector

vector

BIAK

during

and

interrupt

uses

only

microcycle.

are

fed

into

the

bus

control

BUS CYC H

PROM

(Figure

5-2).
The PROM decodes them to determine the type of microcycle
currently
executing
within
the
MOS
chips.
The
PROM
outputs
control various signals and perform the following functions.
1.

CLK

HOLD

stops

the

clock

generator

for asynchronous data transfers.
free
up
the
bus
during
DMA
or

This
when

the

high

state

signal is used
bus
cycle
1is

to
in

progress.

BUS

ENA

data-out
3.

DIN

DOUT

CYC

WTBT

CYC

enables

bus
H

drives
H

drives

BDIN

the

drivers

bus

BDOUT

BWTBT

1is
byte

bus

during

data-out

and

bus

followed

data

driver.

bus

driver.

signal

transfer

whenever

data-out

microcycles

(refer

AI01

BUS CYC H

address

and

progress.
to

extend

nonbus

Paragraph

the

data-in

5.10.2.).

CLK HOLD H

A102

00|

microcycle

CLK
STUT
H,
for
clock
control,
is
used
clock-high time of address microcycles and
and

address

only.

the

drives

microcycle
whenever a

LSI-11

cycles

BUS ENA H
BYS

DIN CYC H

PROM

WIBT H

SYNC/DMA ENA H

CLK STUT H

MR-3693

5.6.4.1

BUS

from

the

data

chip

CYC

internal

allow
1In

transfers)
clock

5.6.4.2
yet

SYNC/DMA

MOS

set

function

data

chip

transfer,

chip

the

ENA

complete.

Its

use

sync

signal

transfer

set,

then

the

PROM

BUS

clock

to or
from the
BUS CYC H is low.

then

CYC
is

high.

lengthened

time

bus-type

data

transfers,

SYNC/DMA

complete

1In

one

its

the

clock

internal

the

bus drivers
receivers (DIN transfers)
are enabled, and the
halted
in
the
high
state,
waiting
for
BREPLY
L

still

transfers,

case

attempting

the

Control

bus.

peripheral

bus

data

the
the

Bus

(SYNCF).

external

tick

transfer.

the

signal

This

internal

from

chip

master

5-2.

data

case

(DOUT

Figure

H
bus

master

function

the

LSI-11

ENA

that

the

bus

when

indicates

prevent

the

last
the

bus

bus
MOS

that

another

cycle
chip

still

1is

set

being

not
from

used.

The

master clock is halted during LSI-11 bus data transfers while
transferring
data
to
the
peripheral
or
receiving
data
from
the
peripheral.
Once this is accomplished the master clock starts up

again

and

microinstructions

are

processor

1is

processor

cannot

terminate

deasserted

peripheral

terminating

the

again

executed.

previous
the

bus

cycle

(there

Concurrently,

Because
the
BREPLY
has
been

until

the

cycle.

time

1limit

this

action
taking
place
according
to
LSI-11
bus
protocol),
it
1is
possible for
the previous bus cycle to still be
active when
the
chip set is ready for the next bus cycle.
SYNC/DMA ENA H causes
the clock to stop in the address cycle in this case and halts the

chip

set

properly

the

address

completed

5.6.5

MIB03/GPO

Control

code

GPO

decode

ENA

GPO

logic

This

microcycle

(BSYNC

driven

(Figure

signal

1is

until

the

bus

cycle

negated).

the

data

5-3)

and

properly

used

jumpers
on
the
processor
information on jumpers.

gate

chip,

detected

timed

power-up

board.

Refer

MiB02/GPO?2

MIBO1/GPO1

5 GDGPOB L

MIBOO/GPOO

5 loDGPOS5 L

the

produce

FDIN

information

from

Chapter

for

DGPO7 L

E130 H
MCLK L

MIBO3/GPO3

110

SRUN L

E130 H

FDIN ENA
L

E33 H

MR-3694

5.6.6

MIB02,

GPO

and

perform

signals
output

and

are
is

5.7

01,

are

Figure

5-3

00/GPO

driven

control
decoded

shown

BSYNC

GPO

the

functions
the

Table

data

logic

Decode

chip

the

shown

Logic

during

processor
in

Figure

clock-high

board.

5-3.

time

These

The

decoded

5-1.

LOGIC

The

logic

shown

onto

the

LSI-11

bus.

Figure

The

5-4

controls

start

all

the

assertion

bus

cycles

<DATI,

SYNC

DATO(B),

DATIO(B)>

chip

1is signaled by SYNCF L going low on MIB07 of the data
during clock-high time.
SYNCF L is clocked into both the BUS

CYC

flip-flop

and

the

SYNCF

flip-flop

the

end

clock-high

time.
A set BUS CYC flip-flop indicates to the DMA
processor
is going
to use the bus,
and
therefore
cannot be granted.
Table

5-1

General-Purpose

Output

logic that the
a DMA
request

Signals

Output

GPO2

GPO1

GPOO

Name

DGP07

Function
L

Loads

the two highest order address
bits
into a latch while
in microODT.
This allows 18-bit addressing
to
be
accomplished
without
wusing
the memory management unit while in
ODT.

DGP06

Clears

after

been
1

DGPO5

the

executed

Clears

the

SRUN

flip-flop

sequence

has

microcode.

event

the
event
serviced in

power-fail

flip-flop

interrupt
microcode.

after

has

been

Generates a low-going pulse that is
routed
directly
to
edge
fingers
AFl,
AH1
whenever
an
instruction
fetch
occurs.
The
pulse
also
occurs

whenever

character

received from the serial line unit
while
in
micro-ODT.
This
signal
can be
used
to cause a steady RUN
indication
while
the
processor
is

The

SYNCF

flip-flop

executing
flashing

microinstructions

and

indication

typing

characters

when

console-ODT.

feeds

the BSYNC flip-flop.
This flip-flop is
33 ns after the start of clock-high time.
Thus,
the BSYNC flip-flop will be set 33 ns into clock-high time
of
the
microcycle
after
the
address
microcycle.
This
delay
is
strobed

every

necessary

Once

the

asserts

microcyle,

allow

BSYNC
BSYNC

Once

the

BSYNC

low

level

from

sufficient

flip-flip
L

onto

the

LSI-11

flip-flop

the

RESET

BSYNC

address

set,

set-up

drives

the

time

bus

are

both

REP

BRPLY

from

functions

the

set,

remains

logic

and

RESTART

END

BRPLY

BUS

from

being

CYC

cleared

LSI-11

BRPLY
to

and

after

its

set

until

reset

changed

line.

bus.

SYNC

The

BSYNC

RESET

pulse

generate

DOUT

the

bus.

and

bus.

signal
from
the
data
chip
clears
on
the
data-in
microcycle that completes the bus cycle.
The BSYNC
cleared

the

transceiver

BLOCK

DATI

REP

block

portion

L
the

the

The

or
data-out
flip-flop is

and

RESTART

logic

uses

rising

BSYNC

DATIO

SYNCF

END
SYNC

edge

flip-flop

cycle.

These

—
>
SYNCF
F/F

BSYNC L
-

—] CLK

| : RSYNC H
J

SYNC (1) H

BSYNC
SR

COMREP L I

fl
_—

]

E33 L

F/F

O CLK
K

ACCESS
F/F

PS ACCESS

LOGIC

BSYNC RESET
LOGIC

L —— AEEEE—— SEE—— oES—— —— J
MIBO7/SYNCF L

BUS

RESTART END

o CYCH

MIB12/A102

BUS CYC L

BUS

CYC F/F

CLK

L
SYNC REP L

DOUT L

65 CLK H

65 CLK L

SYNC RESET L

DOUT BLOCK L

CLK

l—

CLK

] CcLK

—— CLK

MR-3695

Figure

5-4

BUS

SYNC

Logic

signals also prevent the BSYNC flip-flop from being cleared for at
least 175 ns after BDOUT L is cleared (as per bus specifications).
SYNC
RESET
L clears
the
BSYNC
flip-flop
on
power-up
1if
a
bus

timeout

occurs,

and

prevents

from

setting

when

MMU

abort

occurs.

PS Access Logic
The PS
(processor

status word)
access logic feeds the K input of
the BSYNC flip-flop and is used only when the PS is accessed.
The
PS
1is contained in the data chip.
When 777776
(the address of

the PS in the data chip)

appears on the DAL guring an address

microcycle, the data chip decodes the address and access
is allowed.
The bus cycle is terminated by deasserting
line without allowing a DATI or DATO AIO code.
The
the

PS access flip-flop stores this condition until the start of
next clock-high time.
This signal
is fed to the K input of

the
BSYNC
flip-flop
microcycle.
5.8
DMA
the

to the PS
the SYNCF

DIRECT
on
the
LSI-11

and

resets

MEMORY ACCESS

KDF1ll1-AA board
bus
from
the

BSYNC

the

start

the

(DMA)

allows peripherals to gain control of
processor
and
transfer
data
directly

between a peripheral and memory.
In this way, data transfers can
occur
at the full memory speed
rather
than having
the processor
transfer
data
words
one
at
a
time
between
the
peripheral
and
memory.
A speed gain of about
12
to 1 over
regqular
programmed
transfers is gained by this technique.
The

signals

BDMR L

required

the

DMA logic

are

the

following.

This
is
the DMA request signal.
A peripheral
device asserts this line when it is ready to use
the bus for a DMA transfer.
This line 1is common
to

BDMGO

for

all

peripheral

This DMA grant
in response to

line,

devices.

signal is issued by the processor
a DMA request.
By asserting this

the

processor indicates that it will halt
as soon as
the current bus cycle
is
completed.
The processor will also disable all

processing

bus

control

lines

and

data-address

so
that
the
peripheral
device
control the bus.
The BDMR line
peripheral

devices.

signal.

Any

memory

does

want

not

signal

on.

The

use

first

BDMGO

the

bus

lines

(BDAL)

can use them to
is common to all

peripheral

daisy-chained

simply

(physically

device

passes

closest

that
the

the

processor) device on the bus desiring to use the
bus "takes the grant;"
i.e.,
blocks
the
signal

from

being
to

closest

passed on.
Therefore the peripheral
the processor
requesting
the
bus at

the
time
the
grant
is
issued
gets
to
use
the
bus.
1In order to prevent hogging of the bus by
peripheral
devices
nearest
the
processor,
DMA
transfer time must be as short as possible.
BSACK

This

DMA

acknowledge

signal

peripheral

device
taking
signal completes the

This

processor

SACK

Timeout

and

indicates

taken

bus.

the

LSI-11
bus
that
a
device

issued

the

control
of
the
bus.
handshake between the

peripheral

processor

that

device

and

device

has

systems
there
1is
a
possibility
can
request
use
of
the
bus
and

then

not take the DMA grant signal.
The no SACK
timeout feature clears the DMA grant signal and
returns

bus

mastership

the

processor

peripheral device has
issued BSACK L within 18
microseconds
after
the
processor
has
issued
a
grant.
This
prevents
a
potential
bus
lockup
problem in which the processor has given up the
bus

5.8.1
The
from

but

one

has

taken

the

grant.

DMA Logic
logic is shown in Figure 5-5.
BDMR L signals are received
the bus on edge pin AN 1 and synchronized with the processor

DMA

high-frequency

clock

through

high-speed

synchronizer.

signal
is called SYDMR for "synchronized DMR."
is gated with
the
signal
BUS
CYC
L
to
block
reaching
the DMA
gated
signal

ENA flip-flop when a bus cycle
is
is
called GADMR
for
"gated DMR."

flip-flop
clock-high

the
(about

The

samples

time

GADMR
every

latched
into
the
DMA
ENA
that
DMA
request
is

in progress.
The
DMA ENA

the

beginning
When
a
valid

every
GADMR
1is

flip-flop,
the
DMA
cycle
is
started.
taken
unless
the
processor
1is

Note

bus

line
at
290
ns).

This

The SYDMR signal
DMA
requests
from

always

currently

response

DMA

cycle.

This

ENA

1is

latched,

DMA

approximately

reguests.

(Refer

necessary
to

provide

fast

5.8.2,

DMA

LSI-11

bus

Paragraph

Latency.)
Once

DMA

grant

later

flip-flop.

grant

the

Granting

issued

DMA

ENA

being

the

DMA

request

the

clocked
also

into

the

starts

the

timer which is set for 18 microseconds.
At exactly the same time
DMA grant 1is enabled,
the DMA bus disable
flip-flop disables
the

BDAL bus drivers on the processor board.
The DMA ENA (1) L signal
also blocks
any
further
clock
restarts
from occurring
until
the
DMA cycle
that
1is just starting
is completed.
It does
this by
blocking

the

Once

grant

DMA

AND
is

inputs

issued,

the

clock

restart

the

processor

logic.

board

signal
indicating
that
a
peripheral
device
grant.
The BSACK L line is monitored by a bus
BSACK L resets the no SACK timeout timer which
DMA

restart

flip-flop.

The

DMA

restart

waits

for

BSACK

has
taken
the
DMA
receiver; an active
clocks a 1 into the

flip-flop

now

armed.

soon

the

flip-flop

will

logic

bus

allow

given

the

DMA

the

current

rearbitration

DMA

process

master,
to

this

restart.

This occurs when BSACK L and BSYNC L are deasserted as the bus
master gives up the bus.
These signals, along with the armed DMA
restart flip-flop, satisfy the logic which feeds the rearbitration
and

restart/rearbitration

takes

place.

REARB

BUS CYC L

GADMR | |
MCLK

BDMR

NIZING

1 \oaic
CLK

—1

SYDMR
REARB

DMA |ENA (1) H

DMA

O ENABLE
FF

DO_CL

DMA

CLK
GRANT
(DELAYED | g

]

>:BD'V'GOL

]

J‘q}
DMA ENA (1) L

{

TO CLOCK

STOP LOGIC
BUS DISABL (1) L

‘

BUS

DISABLE

TIMEOUT

LOGIC

]

BSACK L

TO BUS
LOGIC

CLK

L DMA

(DELAYED 65 NS)

DMA

RESTART
FF

BSYNC L [> ORSYNG »TOO
BSACK H O

INIT L

[

CLK | LOGIC |> C
REARB

REARB
MR-3696

Figure

5-5

DMA

Logic

According to system protocol the processor is the lowest priority
bus master.
'
When a bus master
gives up the bus,
the processor
should immediately check for another pending request.
If another
request is pending, another BDMGO is reissued and a new peripheral

takes control.
time the bus is
great

the

KDF1ll-AA,

given up.
If
it
1is
possible

rearbitration

takes

place

each

DMA requests are arriving at
too
to
have
the
processor
constantly

a
rate,
arbitrating among bus masters.
This effect can be illustrated by
holding the BDMR L 1line low which blocks any instruction fetches

the

The

processor.

rearbitration

1logic
synchronizes
the
input
signal
with
the
clock.
The
output
1is
inverted
to
become
REARB.

high-frequency
Low-going

REARB

(SYDMR) .

REARB

1is

gated

there

with

new

the

DMA

synchronized

request,

SYDMR

signal

clears the DMA enable flip-flop.
This
MCLK
to be
restarted
(if stopped)
on
the next
tick
frequency clock.
Since the DMA enable flip-flop is
next

clock

processor

pulse

does

bus

master

not

set

the

DMA

grant

DMA

request

low

and

the

event allows
of
the high-

cleared,

flip-flop

the

and

the

again.

a new DMA reguest is pending, the sequence is different.
REARB
is blocked from clearing the DMA enable flip-flop by a high SYDMR
signal.
Sixty-five ns later
the DMA grant flip-flop
is
set and
the

DMA

never

sequence

reset,

never

5.8.2
DMA

DMA

processor

DMA

again.

ENA

(1)

Since

the

signal

DMA

enable

constantly

flip-flop

low

and

MCLK

restarted.
Latency
is the time

latency

until

important

heads

starts

the

because

controller

BDMGO

disk

must

from

when

put

data

drive

become

loss

are

bus

the

DMA

request

bus.

The

problems.

over

master

the

For

proper

within

arrives

maximum

DMA

the

latency

example,

once

sector,

the

disk

time.

certain

period

the

If
it
does
not,
information
will
overflow
the
temporary
data
buffers
in
the disk drive
interface
and
cause data-late
errors.

Since
bus

the

arrives
In

KDF11-AA

cycles,

just

this

does

not

worst-case

DMA

before

the

grant

case

grant

bus

latency

start

will

mastership

occurs

the

when

longest

1issued

during

the

bus

after

ongoing

DMA

cycle
the

request

(DATIO).

<cycle

has

completed.

5.9
The

CLOCK
KDF1ll

GENERATOR

chip

set

indefinitely,
but
limited period of

CIRCUITRY

clock

can
be
suspended
in
the
high
state
can only
remain
in
the clock
low state for
a
time
to avoid
loss of
internal
chip data.
A

twisted
ring
oscillator,
shown
in
Figure
5-6,
1is
used
with
a
high-frequency crystal clock input to generate the required clock

signals that control
the
ring
oscillator

the MOS/LSI chips.
(MCLK
H)
1is
driven

clock

buffer/driver

drives

the

5.9.1
When

MOS

produce

the

The TTL
through

level output of
a
high-voltage

high-voltage

CHIP

CLK

that

ring

chips.

Initialization
the

processor

oscillator
asserted

receives

initialized
the

initialization

power

circuitry

and

held

supply

+5
(or

shown

Vdc

this

the

and

+12

Vdc,

the

state

until

BDCOK

wake-up

Figure

5-7.

circuit).

The

output

is
The

the second stage of the DCOK H synchronizer circuit holds START H
low.
The processor board initializes with MCLK H = 1 and all
three stages of the ring oscillator also equal 1
(E65H, E130H,
E195H).
When DCOK H goes high, it is first synchronized with the
high-frequency clock
(65CLK H)
and
then
releases
the
ring
oscillator
from
its
initialized
state.
The
synchronizer
1is
necessary because DCOK H is asynchronous to any circuitry on the

processor

board

and

feeding

DCOK

directly

into

the

ring

oscillator could lead to a truncated first cycle of the processor.
Once the oscillator 1is freed, it immediately causes MCLK H to go
low

and

enters

the

clock-low

state.

voe
MME HOLD
RESET H

CLKSTUTHI,

START H

MCLK H

CLK STOP

CHIP

CLK

E65 H

MCLK H

XTAL ADC

0sC

CLK

‘

E130 H

CLK

‘

65CLK H

E195 H

CLK

MR-3697

Figure

5.9.2

Clock

5-6

Generator

Wake-Up Circuit

The "wake-up" circuit on the KDF11-AA module consists of a diode,
a resistor, a capacitor, and a Schmidt trigger inverter, all shown

at
the
1left
in Figure
5-7.
This
circuit
provides
automatic
generation of BDCOK H 50 ms after the +5 V supply is turned on.
For the circuit to function, the +12 V must be applied before or
at

the

same

time

supply must

the

greater

5.9.3
Single-Step Circuit
The single-step circuit is

applied,

than

shown

and

the

rise

time

the +5

portion

Figure

ms.

the

lower

5-7.
This circuit
circuit to stop the

can be used in conjunction with an external
processor
(i.e., hold the clock indefinitely

time with a desired

stop address or

high)
in
the bus
selected address.
lines and compare

data-in or
data-out part of
the cycle
at a
The
external
circuit must monitor
the BDAL
the address issued by the processor at BSYNC L

addresses.

a valid compare

occurs,

low

the

level

processor
and

the

external

soon

will

data

transfers)

circuit

then

BDIN

stop

driven

from

received

can

single-step

line

should

bus

data-in

from

resume

STEP

the

data-out

the

case

address

logic

bus.

The

microcycle

(in

data-out

the

case of
BDAL lines and any other
procbed
manually.
The

the
be

this

(in

selected

observed on
system
can

will

SINGLE

appears

processor

the

released

and

pull

BDOUT

the

from

data-in transfers) can be
internal
points
of
the
processor

state

executing

releasing

the

instructions.

BDCOK H
BA1

—£:>OL—::::>0J
|WAKE{W(HRCUH'

| AE1

SINGLE STEP

65CLK H

5.10

CLOCK

four

variations

clock

Normal

Clock

state

cycle,

low.

Figure

Clock

Stutter

clock

and

for

the

same

the

bus.
MOS

Generator

Initialization

Circuitry

producing
a
normal
cycle
and
used for special functions.

START

and

5-8

of
two
cycles
of
the
high-frequency
two cycles in the low state.
For this

constantly

shows

this

high,

RESET

low,

and

CLK

cycle.

Cycle

cycle
is generated on
all
address microcycles
internal data
transfers among
the MOS chips.
It
1is

all

DAL

MR.2458

stutter
as

clock-high
clock

consists

high

type

5.10.2

)STARTH

is
capable
of
the normal cycle

STOP

The

Cycle

cycle

the

—

generator

normal

GENERATOR CYCLES

clock

5.10.1

65CLKl H G

5-7

The

SINGLE STEP CIRCUIT

Figure

D Q

the

time

three.
lines

The
chips.

cycle

normal

cycle

extended

This

stretched

settle

also

discussed

from

before

allows

two
or

the

extra

above

cycles

"stuttered"
address

time

for

except

the

.that
the
high-frequency

clock

driven

data

time
out

transfers

allows

onto

the

between

65CLKH||||||||||I

MCLKH_]__—_—L____[_—

MR-2459

Figure

The

c¢ycle

control

1is

PROM

generated
(see

5-8

Normal

the

Paragraph

CLK

5.6.4)

Clock

STUT

being

Cycle

signal

from

fed

through

the

bus

transparent

latch

that is enabled during phase time.
The output of the latch
inhibits the E130 H input to the feedback loop from causing MCLK H
to go low.
Instead, the ring oscillator output drops when E195 H
goes
high,
one
cycle
of
the
high-frequency
clock
later.
The
stutter cycle is shown in Figure 5-9.

65CLK H

MCLK H J

CLK STUT H

E65 H

E130 H

E195 H

[

L
MR-2460

Figure

5-9

Clock

5.10.3
Clock Stop Cycle
The
clock
stop
cycle
is

data-out

transfers

the

LSI-11

the

chip

clock
HOLD

bus

before

from

cycle

stop
H.

bus

set

cycle

The

when

CLK

generated

the

bus

STUT

two

cycles

flip-flop,

CLK

STOP,

until

CLK

STOP

the

wait

can

continue.

set

address

device

has

bus

stretches

high-frequency

flip-flop

1is

cleared.

bus

from

used

prevent

portion

STUT

For

clock-high

and

time

CLK
from

The CLK HOLD H signal
flip-flop)
every cycle

clock.

holds

and

"mastership."

the

and

microcycle

PROM generates CLK

clock cycles.
(the CLK STOP

low

data-in

for

also

the

signal

goes

past

control

two to three high-frequency
is clocked into a flip-flop

after

bus

must

chip

DMA

Cycle

during

the

continuing

when

Stutter

MCLK

The

output

the

case

high

this
state

bus

data-in or data-out cycle, the flip-flop is cleared 200 ns after
REPLY has been received from the addressed device, or, in the DMA

130

ns after

the processor.

the DMA device has given bus mastership back

This cycle

65CLK H

shown

MCLK H _l

Figure

E65 H

E195 H
CLK STUT H

_{C

E130 H

{(
)}

5-10.

case,

CLK STOP

]
MR-.:461

Figure

5.10.4

This

5-10

Memory Management

cycle

occurs

Clock

Stop

Cycle

during

address

microcycles

when

the

memory

management chip is present and is enabled to do address relocation
(enabling of the MMU is under software control).
The MMU chip
signals
to
relocation

the
processor
board
that
it
wants
to
do
by
asserting
the
MIB
1line
MME
L
at
the

clock-high time of an address microcycle.
shown

Figure

5-11,

detects

the

asserted

high

into

microcycle.

MME

total

five

high-frequency clock

produced

195

gate

causes

out

and

the

MMU

HOLD

into

chip

flip-flops.

clears

itself

during this time,
the BDAL lines.

MME

which

clock-low

time.

5.10.5

The

Reset

final

occurs.

onto

the

Since

and

time

periods

325

time

DAL

The relocation circuit,

signal

clock-low

latch

the

five

the

bus

BDAL

causes

clock

which

the

MME

the

low

state

ns.

HOLD

address
for

A pulse

1is

passes

through

the

relocated

address,

driven

bus

high-frequency

immediately

this

1is

time,

into

continuously

the

DAL

enabled

clock

allows

MCLK

basic

cycle

periods

and

high,

releases

ending

Cycle

variation

CHIP

CLK

the relocated address is immediately driven onto
The relocation timing circuitry automatically

after

HOLD

MCLK

clock-low

DALFF

driver

holds

MME

address
end
of

RESET

5-12 and occurs for
immediate attention

the

generated

any one
by the

the

1is

when

circuit

CHIP

RESET

shown

Figure

of five error conditions that warrant
chip set.
RESET H is enabled 65 ns

into
clock-low time
and
clock-low
time
from
two
three.
This
extended

initialize

the MOS/LSI

causes
the
ring
oscillator
to
stretch
periods of
the high-frequency clock
to
clock-low
time
allows
CHIP
RESET
to

chips.

MME HOLD

MiB15/

MMEL

MCLK L

65CLKH[7 7

‘7 Q

CLR

J— T

CLR

MR-2462

5-11

Relocation

Timing

Circuit

CTLERRH

PAR ERR H

BUSERRH

DCLOH

ABORT H

YYVYVYY

Figure

RESET H

E65 H

—="
g
MR-2463

Chip Reset/RESET
RESET is routed to

requiring
The

immediate

following

five

Control

Figure

5-12

Reset

all

chips

except

occurs,

interrupts

require

error

microcode.

MOS

attention

Circuit

the

MMU.

line

immediate

1If

interrupt

asserted

high.

attention.

- Nonexistent control chip selected by the
trap

location

104

occurs.

Bus

error

location

Parity

Nonexistent

error

from

memory.

MMU

abort

trap

memory

location

accessed.

trap

error

detected

current

read

occurs.

parity

trap

The

MMU

has

location

2508

location

1148

aborted

occurs

for

occurs.

mapped

reference.

any

the

following

reasons.

The

memory

current

location

user's

attempt

referenced

protected

address

made

modify

exceeding

his

allotted

location.

The

user

not

space.

present

write-protected

page

boundary.

Power-Up
Upon
power-up
the
processor
forces
sequential
RESETS
to
the
chip
set
to
initialize

internal

chip
registers.
is not activated

clears

and

(Refer

Paragraph

4.5.4

for

The
again

the

two

all

dc
power-up
1line
then
while dc power
is on.

power

protocol.)

CHAPTER 6
ADDRESSING MODES
INTRODUCTION

6.1

In the KDF1ll-AA all memory reference addressing is accomplished
In specifying an
registers.
the eight general-purpose
using
address of the data (operand address), one of the eight registers
and one of several addressing
reference instruction specifies
1.

Function

General-purpose
source

Many

modes are selected.
the following.

be performed

and/or

destination

are

memory

(operation code)

used

when

1locating

the

operand

Addressing
mode,
which
registers are to be used.
capabilities

Each

specifies

provided

the

how

the

combination

selected

the

addressing
modes
and
the
instruction
set.
The
KDF1ll-AA
1is
designed
to
handle
structured
data
efficiently
and
with
flexibility.
The general-purpose
registers
implement
these
functions

the

Act

Act
as
pointers:
the
content
of
the
register
1is
the
address of the operand rather
than the operand
1itself,
allowing automatic stepping through memory locations.

Act as index
added to the
the

Utilization

ways.

accumulators:

address

access

address

following

the

hold

registers:
the
second word of

the

variable

calculation

they

operand.

entries

registers

results

for

the

data

manipulated

content of the register 1is
the instruction to produce
This

capability

allows

easy

manipulation

and

list.

both

data

variable

1length

instruction

format.
If registers alone are used to specify the data source,
only one memory word
is
required
to hold the
instruction.
In
certain modes,
two or
three words may
be
utilized
to
hold
the
basic
instruction
components.
Special
addressing
mode
combinations
handling
of

enable temporary data storage for
frequently
accessed
data.
This

convenient dynamic
1is
known
as
stack

addressing.
Programming
techniques
utilizing
the
stack
discussed
1in
Chapter
10.
Register
6
1is
always
used
as
hardware
stack
pointer,
or
SP.
Register
7
1is
used
by

processor
arrangement

with

as
to

1its

program

considered

modes

registers

addressing

1is:

counter

(PC) .

conjunction

0-5

Thus,
with

are

the

are
the
the

instructions

and
general-purpose

registers, register 6 is the hardware stack pointer, and register
7
is the program counter.
The full KDF1ll-AA instruction set and
instruction formats are explained in Chapter 7.

For
the purpose of clearly
illustrating
the
use of the various
addressing modes, the following instructions and symbols are used
in this chapter.
Mnemonic

Description

CLR

Clear

CLRB

Clear

Byte (Zero
destination.)

the

INC

Increment

(Add

Increment

Byte

(Add

INCB

COM

Octal

(Zero

the

specified

destination

byte.)

Complement

(Replace

byte

destination.)

0050DD

1050DD

the

specified

contents

the

destination.)

contents

destination by their logical 1's
complements; each 0 bit is set and
1 bit is cleared.)

0052DD

the

1052DD

the

0051DD

each

COMB

Complement Byte (Replace the contents of the
destination bytes by their logical 1's
complements; each 0 bit is set and each 1
bit is cleared.)

1051DD

ADD

Add

06SSDD

(Add

operand

source

and

operand

store

the

Code

destination

result

at destination

first

word

address.)

()

6.2

The

destination
source

field
contents of

field
(6

INSTRUCTION

instruction

instructions

bits)

FORMATS

format

(such

bits)

for

the

clear,

increment,

all

test)

single

shown

MODE

* %

* % %

operand

Figure

6-1.

OP CODE

DESTINATION ADDRESS

LEGEND

*SPECIFIES DIRECT OR INDIRECT ADDRESS

** SPECIFIES HOW REGISTER WILL BE USED
*** SPECIFIES ONE OF 8 GENERAL PURPOSE REGISTERS
MR-3643

Figure

6-1

Single Operand

Instruction

Format

The

instruction

format

shown

for

OP CODE
1

the

Figure

MODE
1

first

* %

word

the

double

operand

6-2.

02
Rn
1

* %

DESTINATION ADDRESS

L
* % *

* %%

SOURCE ADDRESS

MODE
L

—

LEGEND

* SPECIFIES DIRECT OR INDIRECT ADDRESS
**SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED
*** SPECIFIES
A GENERAL REGISTER
MR-3644

Figure

6.3

6-2

ADDRESSING

Instruction
mode

bits

chosen.

specify

four

direct

The

Autodecrement
Index

bit
specified

Instruction

Format

MODES

When

Operand

<5:3>

Double

the

binary

addressing

of
the
instruction
is
and
the
four basic modes

code

modes

are

the
the

addressing
following.

set,
indirect
addressing
is
become deferred modes.
In a

register-deferred mode,
the content of
the
selected
register
is
as the address of the operand.
1In the other deferred modes,
the content of the register specifies the address of the operand,
rather than the operand itself.
Prefacing the register operand(s)
with an @ sign or placing the register in parentheses indicates to
taken

the

MACRO-11

assembler

that

indirect

addressing

modes

deferred

addressing

mode

being

used.
The

1.
2.

3.
4.
Program

follows.

deferred

deferred
Autodecrement deferred
Index deferred
counter

(PC

Immediate
[

Autoincrement

follows.
W
-

are

Absolute

Relative
Relative

deferred

addressing

modes

are

The

KDF11l-AA

the

6.3.13.

addressing

following

6.3.1

mode

need

reference

general

sign

Mode

summarized

faster

memory

and

shown

instruction
retrieve

defined

6.3.10

execution.

examples

Paragraphs

There

operand.

can be
used
as
accumulators.
selected
register.
Assembler

indicates

explained

are

MODE

provides

general
registers
contained
in
the
that

are

They

Mode

modes

pages.

Any

1is

no
the

The operand
1is
syntax
requires

follows.

definition.

Examples
Instruction

Symbolic

Octal Code

Description

INC

005203

Add

The

example

shown

in Figure

the

contents

R3.

6-3.

RO
15

-l

o0olo

}

R1
-

SELECT

R6(SP)

OP CODE (INC{0052))

R7(PC)

DESTINATION FIELD

MR 3674

Figure

Symbolic

ADD R2,

6-3

Mode

Instruction
Octal Code

Description

060204

Add

example

shown

Figure

6-4.

the

Example

contents

original

contents

the

The

Increment

sum.

R4,

the

replacing

the

with

AFTER

BEFORE

rR2[

oooooz2

R2[

ooooo2 |

R4 [

“ooooo4a

000006

MR-3675

Figure

6.3.2

6-4

Mode Add

Example

(Rn)

MODE 1

In register deferred mode, the address of the operand is stored in
a general-purpose
register.
The address contained
1in the

general-purpose

operand

directs

the

is located outside the CPU,

CPU

either

the

operand.

in memory,

in an I/O

This mode is used for sequential lists, indirect pointers
structures, top of stack manipulations, and jump tables.
Register

Deferred

Mode

The

data

Example

Instruction

Symbolic

Octal Code

Description

CLR

(R5)

005015

The

example

shown

Figure

BEFORE

ADDRESS SPACE

1677

001700

the

are

1location

cleared.

6-5.

AFTER

rRs|

1700

contents

specified

ADDRESS SPACE

1677
1700

000100

rRs| 001700

000000
MR-3676

Figure

6.3.3
In

6-5

Deferred

Mode

Autoincrement Mode

autoincrement

mode,

the

Example

MODE
register

contains

the

address

(Rn)
+
of

the

operand,
and the address is automatically incremented after the
operand
1is
retrieved.
The
address
then
references
the
next
sequential operand.
This mode allows automatic stepping through a
list or series of operands stored in consecutive locations.
When
an
instruction
calls
for
mode
2,
the
address
stored
1in
the

is autoincremented each time the instruction is executed.
It is autoincremented by 1 if byte instructions are being used, by
2 if word instructions are being used.

Autoincrement

Mode

Example

Symbolic

Instruction
Octal Code

Description

CLR

005025

Contents

(RS5)+

address

of R5
of the

selected

increment
2.
The

example

shown

Figure

are

as
the
Clear

operand
and
the contents of

then
R5 by

used
operand.

6-6.

BEFORE

AFTER

ADDRESS SPACE

20000

005025 |

30000

111116

ms|

030000

ADDRESS SPACE

| 20000]

005025

]

30000{

000000

ms|

osoo02

MR-3677

Figure

6.3.4

6-6

Autoincrement

autoincrement

address.

access

after

the

autoincrement

Deferred

deferred

The.
+

Autoincrement

mode,

indicates

address

operands

that

deferred,

stored

anywhere

the

reside

adjoining

table

volumes;

MODE

the

that

the

stored

Mode
in

used

locations.

Mode

used

pointer

lists

used

step

used
Mode

operands

not

step

through

incremented

locations.

operands

Q@ (Rn)
+

autoincrement,

access

the

consecutive

i.e.,

contains

pointer

system;

mode

Example

Mode

located.

are

Mode

have

through

table

addresses.

Autoincrement

Deferred

Example

Symbolic

Instruction
Octal Code

Description

INC

005232

Contents

@ (R2)+

address

operand.

increased
R2
The

example

shown

Figqure

6-7.

are

used

the

address
of
The
operand

the
is

the

and

incremented

contents
by

BEFORE

AFTER

ADDRESS SPACE

rR2|
1010

ADDRESS SPACE

010300 |

rR2|

000025

1010

1012

o10302

000026

1012

010300{

001010

10300

001010

MR-3678

Figure

6.3.5

6-7

Autoincrement

Deferred

Mode

Autodecrement Mode

MODE

In autodecrement mode, the
automatically
decremented;
locate

operand.

This

but allows stepping
order.
The address

Example

- (Rn)

mode

similar

through a list of words
is autodecremented by 1

autoincrement

is
to

mode,

or bytes in reverse
for bytes, by 2 for

words.

Autodecrement

Mode

Example

Symbolic

Instruction
Octal Code

INCB

105240

- (RO0O)

Description
The
contents
of
RO
are
decremented by 1, then used as
the
address
of
the
operand.
The
by

The

example

shown

Figure

operand

byte

1is

6-8.

BEFORE

AFTER

ADDRESS SPACE

1000|

005240

17774

oooo00

REGISTERS

ro|

017776

ADDRESS SPACE

1000]

oos240

17774

ooooo1

RO]

017774

MR-3679

Figure

6-8

Autodecrement

Mode

Example

increased

6.3.6

Autodecrement

Deferred

Mode

MODE

@- (Rn)

In autodecrement deferred mode,
the register contains a pointer.
The
pointer
1is
first decremented by 2,
then
the new pointer
is
used to retrieve an address stored outside the CPU.
This mode is
similar to autoincrement deferred, but allows stepping through a
table of addresses in reverse order.
Each address then redirects
the
CPU
to
an
operand.
Note
that
the operands do not have
to
reside in consecutive locations.

Autodecrement

Deferred

Mode

Example

Instruction

Symbolic

Octal

COM

005150

@-(RO)

Code

Description
The

contents

are

decremented by 2 and then used
as
the
address
of
the
address
of the operand.
The operand is
l's complemented.

The

example

shown

Figure

6-9.

BEFORE

AFTER

ADDRESS SPACE

10100

012345

RO[

010776

ADDRESS SPACE

j 10100

10102

165432

Rol

10102

10774

010774

]

‘/

010100

10774

10776

010100

10776
MR-3680

Figure

6.3.7
In

index

Index
mode,

6-9

Autodecrement

Deferred

Mode
a

base

Mode

Example

MODE
address

the

effective

address

the

starting

location

table

added

operand;
or

the

1list.

index

base
The

6
word

address
index

+X (Rn)
to

produce

specifies
word

then

represents the address of an entry in the table or list relative
to the starting (base) address.
The base address may be stored in

a
register.
In
this
case,
the
index word
follows
the
current
instruction.
The locations of the base address and index word may
be
reversed
(index word
in
the
register,
base address
following
the current instruction).

Index

Mode

Example

Symbolic
CLR

200 (R4)

Instruction
Octal Code

Description

005064
000200

The address of the operand is
determined by adding 200 to
the contents of R4.
The
location is then cleared.

The

example

shown

Figure

6-10.

BEFORE

AFTER

ADDRESS SPACE

1020

005064

1022 |

000200

rRa|

001000

ADDRESS SPACE

1024

1020

oos064

1022

000200

rRa|

ootoo0

1024
1000

1200

177777

1200

000000

1202

MR-3681

Figure

6.3.8
In

Index

index

Deferred

deferred

mode,

6-10

Index

Mode

Example

Mode
a

base

MODE
address

The
result
is
the
address
of
a
source
operand,
rather
than
the

pointer
address

added
to
of

the
the

@X (Rn)

index

word.

address
of
the
source
operand.

This mode is similar to mode 6, except that it produces a pointer
to an address.
The content of that address then redirects the CPU
to the desired operand.
Mode 7 provides for the random access of
operands using a table of operand addresses.

Index

Deferred

Mode

Instruction
Octal Code

Symbolic
Add

Example

@1000(R2),

Description

067201

1000

001000

summed

and
to

the

contents

produce

the

of the source operand, the
contents of which are added

the contents
is stored in
The

example

shown

Figure

6-11.

of Rl1.
R1l.

are

address

The

to
result

BEFORE

AFTER

ADDRESS SPACE

1020

067201

R1[

001234

]

1022

001000

2 |

]

1024

1020

067201

R1|

001236

1022

001000

a2 |

200700

]

1024

1050

000002

1100

001050

1000

1050

000002

1100

001050

+100

1100
MR-3682

Figure

6.3.9

Use

counter.

When

the
the
the
to

The

6-11

Index

Deferred

the

PC as a General Register
both
a
general-purpose
register

the

CPU

uses

the

access

byte

data,

can

which

used

the

with

all

the

can

still

incremented

addressing

provide

and

the

program

word

from

memory,

deferred),
operate

relative,

normally

practical
6.3.9.1

use
PC

and

when

normal

Immediate

relative

used

Symbolic
#10,

1including

Mode

for

PC.

The

are

four

handling

remaining

However,

they

MODE

operands

Immediate

There

10)
and unstructured data.
absolute
(or
immediate

Mode

mode is equivalent
It
provides
time
following

of
PC

modes.

deferred.
the

modes

have

programming.

Immediate
the
PC.

immediately

with

advantages

position-independent code
(see Chapter
These
modes
are
termed
immediate,

ADD

Example

PC is automatically incremented by 2 to contain the address
next word in the instruction being executed or the address
next instruction to be executed.
When the program uses the

modes

Mode

the

using

the

constant

instruction

autoincrement mode with
for
accessing
constant

improvements

the

memory

location

word.

Example
Instruction
Octal Code

Description

062700

The

000010

second
and is

RO.

wvalue

located

the

word of the instruction
added to the contents of

Just

before

this

instruction is fetched and
executed, the PC points to

the

first word

The processor

the

instruction.

fetches the first

word and increments the PC by
The source operand mode
2.
is 27 (autoincrement the PC).
Thus, the PC is used as a
pointer to fetch the operand
(the second word of the
instruction) before being
the

The example

062700

rRo[

000010

oooo20

\pc

ADDRESS SPACE

1024

instruction.

AFTER

BEFORE

1022

in Figure 6-12.

is shown

1020

to point

incremented by

1020

062700

1022

000010

1024

ro |

000030

MR-3683

Figure

6.3.9.2

6-12

Immediate

Mode

Example

This mode

is the equivalent of

mode

deferred

following

the

wusing

Q#A

MODE 3

PC Absolute Mode
the

instruction

PC.

are

immediate deferred or

The

taken

the

autoincrement

the

1location

the

operand.

the contents of

location

contents

address

Immediate data 1is interpreted as an absolute address (i.e., an
address
that
remains
constant
no
matter
where
in
memory
the
assembled

instruction

Absolute

Mode

executed).

Example
Instruction

Symbolic

Octal Code

Description

CLR @#1100

005037

Clears
1100.

001100

The example is shown in Figure 6-13.
6.3.9.3

This mode

PC Relative Mode

index mode

MODE

using

the

PC.

The operand's address

calculated by adding the word that follows the instruction
an "offset") to the updated contents of the PC.

1is

(called

BEFORE

AFTER

ADDRESS SPACE

ADDRESS 3PACE

005037

001100

1100

005037

”

001100

1100

000000

177777

1102

/ PC

1102
MR-3684

Figure

PC+2

directs

PC+4

the

always

the

CPU

with

operand.

instruction
With

the

summed

the

first

offset

also

Mode

that

Example

follows

produce

represents

1is

mode,

respect

the

instruction.

effective

address

address
the

relocated,

the

address

updated

PC.

operand

the

operand

Therefore,

remains

the

same

updated PC and the operand is called an
is assembled, this offset appears in the

word location that follows the
instruction.
This mode
for writing position-independent code (see Chapter 10).

Relative

Mode

when

away.

The distance between the
offset.
After a program
useful

Absolute

offset

addressing
with

instruction
distance

program.

relative

to
this

PC+4

the

determined

6-13

1is

Example
Instruction

Symbolic

Octal

INC

005267

000054

contents

Code

Description
increment

the

second

instruction
produce

A
The

example

6.3.9.4

This
an

mode

Relative

index

operand's

follows

This

the

mode

shown

Figure

Deferred

deferred

address

1is

instruction)

similar

one additional
of
the
offset
address.
When
the operand.

the

word

are

location

added

address

increased

1in

the

Contents

to
of

6-14.

Mode

(mode

MODE

7),

calculated
to

are

location

of memory

the

using
by

updated

relative

the

PC.

adding

pointer

offset

(that

PC.

mode,

except

that

involves

level of addressing to obtain the operand.
The sum
and
updated
PC
(PC+4)
serves
as
a pointer
to
an
the address is retrieved, it can be used to locate

BEFORE

AFTER

ADDRESS SPACE

1020

005267

1022

000054

1020

1024

0005267

1022

000054

1024

1026

<+— PC

1026

L
1100 [

000000

1024

+54

1oo[

ooooor

MR-3685

Relative

Figure

6-14

Deferred

Mode

Example

Relative

Mode

Example

Instruction

Symbolic

Octal

CLR

005077

Adds

000020

instruction

the

address

the

operand.

The

example

shown

Code

Description

Figure

the

second

AFTER

ADDRESS SPACE

005077

000020

the

produce

6-15.

ADDRESS SPACE

1022]

the address of
Clears operand.

'BEFORE

1020 [

word

1024

1020

005077

1022

000020

010100

1024

1044 [

010100

1024

+20

—

10100 |

100001

1044

—

10100 [

—

oooooo

MR-3686

Figure

6.3.10

Table

6-15

Relative

Deferred

Direct Addressing Modes Summary
summarizes
the
four
basic

6-1
addressing.

Mode

Example

modes

used

Addressing Modes Summary
summarizes the same four basic modes
addressing.

used

6.3.11

Table

with

direct

Indirect

6-2

with

indirect

Table

6-1

Direct Addressing

Modes

Binary

Code

Mode | Name

Symbolic | Function

000

010

Autoincrement | (Rn)+

contains

operand.

100

Autodecrement | - (Rn)

110

Index

Value X is added to (Rn) to
produce address of operand.
Neither X nor (Rn) 1is

X (Rn)

data,

decremented

then used as a pointer
sequential data.

and

modified.

Table
Binary

Code

6-2

Indirect Addressing Modes

Mode | Name

Symbolic | Function

001

@Rn or
(Rn)

011

Autoincrement | @(Rn)+
Deferred

Code

incremented (always
even for byte

instructions).

101

Autodecrement | @-(Rn)
Deferred

instructions)

even for byte
and

then

as a pointer to a word
containing the address
the

111

Index

Deferred

@X (Rn)

used

operand.

Value X

(located in a word

contained

instruction)

added

and

the

and

sum

(Rn)

1is

are

used

as a pointer to a word
containing the address of
Neither X
the operand.
nor (Rn) is modified.

6.3.12

When
(or
are

Register Addressing Modes Summary
with the PC, these modes are termed immediate,
absolute
immediate
deferred),
relative,
and
relative deferred.
They

used

summarized

Table

6-3.

Table

6-3

Addressing

Modes

Binary
Code

Mode | Name

Symbolic | Function

010

Immediate

Operand

contained

instruction.
011

Absolute

Q#A

Absolute

address

contained

the

1is

the

instruction.
110

Relative

Address

of A, relative
instruction, is
contained in the
instruction.

the

111

Relative
Deferred

Address

containing

location
address

relative to the
instruction, is

in
6.3.13

Graphic

Figures

6-16

the

Summary of Addressing Modes
and
6-17
provide
a
graphic
addressing modes and program counter

contained
instruction.

summary
of
general
addressing modes.

Mode 0

OPR R

R contains operand.

OPR (R)

R contains address.

FNSTRUCTIONHOPERAND
Register deferred

Mode 1

FNSTRUCTION j-————[ ADDRESS
Autoincrement

Mode 2

ADDRESSJ——

FNSTRUCTlON }-———I

R contains address,

OPR (R)+

then increment (R).

OPERAND

[

[
2 FORWORD,
* {1 FORBYTE

Autoincrement

Mode 3

deferred

R contains address of address,

OPR @(R)+

then increment (R) by 2.

|INSTRUCTIONH ADDRESLI—-—-»{ ADDRESSH OPERAND J

Autodecrement

Mode 4

Decrement (R), then

OPR -(R)

R contains address.

—-F OPERAND J

FOR WORD,
B
INSTRUCTIONH ADDRESSH_1"2 PR

Autodecrement

Mode 5

deferred

INSTRUCTIONH ADDRESH

Decrement (R) by 2, then R

OPR @- (R)

contains address of address.

ADDRESSH OPERAND J

-2

(R)+X is address, second

OPR X(R)

Index

Mode 6

-—]

-2

word of instruction.

PC IT\ASTRUCNONH
PC+2 [

ADDRESS

index deferred

Mode 7

OPERAND

OPR @X(R)

(R)+X is address (second
word) of address.

PC rINSTRUCTIONH ADDRESS
ADDRESS

PC+2 r

OPERAND

R is a general register, 0 to 7.
(R) is the contents of that register.
MR.-3687

Figure 6-16

General Register Addressing Modes

Mode 2

immediate

OPR #n

Literal operand n is contained in the instruction.

PC [INSTRUCTIOM
PC+2 I

Mode 3

|
Absolute

OPR @#A

Address A is contained in the instruction.

PC rINSTRUCTION I

PC+2r

Mode 6

l—.l

OPERAND

]

Relative

OPR A

PC+4+X is address.
PC+4 is updated PC.

PC [ INSTRUCTIONJ
PCH2 [

A
OPERAND

PC+4 UEXT INSTR ]

Mode 7

Relative deferred

OPR @A

PC+4+X is address of ad-

dress PC+4 is updated PC.

PC hNSTRUCTION]
PC+2 [

ADDRESS

l—.{

OPERAND

PC+4 [ NEXT INSTR ]

I
Register =7
MR-3688

Program

Counter

6-17

(o))

Figure

Addressing

Modes

CHAPTER 7
INSTRUCTION

7.1
The

SET

INTRODUCTION
KDF11l-AA

instruction set and addressing modes produce over 400
unique instructions.
The instruction set offers a wide choice of
operations,
so
that
a
single
instruction
will
frequently
accomplish
a
task
that would
require
several
instructions
in
a
traditional computer.
KDF11-AA instructions allow byte and word
addressing in both single and double operand formats.
This saves

memory

space
and
simplifies
the
communications
applications.
instructions makes it possible to

implementation

of
control
and
The
use
of
double
operand
perform several operations with

a single
location

instruction.
For example, ADD A,B adds the contents of
A
to
location
B
and
stores
the
result
in
location
B.
Traditional
computers
would
implement
this
instruction
in
the
following

way.

LDA

ADD

STR

The

instruction set contains a full set of conditional branches,
eliminating excessive use of jump instructions.
All instructions
fall into one of three categories.

Single

Operand

operation,
provides

One

information

Double Operand
operation
to
provide

referred

part

for

"op

the

code,"

locating

the

word

and

specifies

the

7.1.1

the

part

operand.

The

first part of the word specifies the
performed;
the
remaining
two
parts
information for locating two operands.
be

Program

Control
- The
first part of
the word
specifies
operation to be performed;
the second part indicates
where the action is to take place in the program.

the

The

second

Single

following

Operand
is

Instructions

list

single

operand

instructions.

General

Mnemonic

Instruction

CLR(B)

clear

COM (B)

1's

INC (B)

increment

destination

complement

DEC (B)

decrement

NEG (B)

2's

TST (B)

test

complement

destination

negate

destination

Shift

and

Multiple

Rotate

Mnemonic

Instruction

ASR (B)
ASL (B)

arithmetic
arithmetic

ROR (B)

rotate

right

ROL (B)

rotate

left

SWAB

swap

shift
shift

right
left

bytes

Precision
Mnemonic

Instruction

ADC (B)

add

SBC (B)

subtract

SXT

sign

Processor

carry
carry

extend

Status

Mnemonic

Instruction

MFPS
MTPS

move
move

byte
byte

from processor status
to processor status

Instruction Format - The instruction format for
instructions, as shown in Figure 7-1, is described

Bits

15-6

Bits

5-0

indicate

the operation to
byte operation.)

indicate

information

for

the

operation

performed.

code,

(Bit

single operand
as follows.

which

the destination address,

locating

~—

OP CODE

DESTINATION ADDRESS

" LEGEND

*SPECIFIES DIRECT OR INDIRECT ADDRESS

*#* SPECIFIES HOW REGISTER WILL BE USED
*** SPECIFIES ONE OF 8 GENERAL PURPOSE REGISTERS
MR-3643

Figure

7-1

Single Operand

Instruction

which provides

the operand.

MODE

specifies

indicates word

Format

Double Operand Instructions
7.1.2
The following is a list of double operand

instructions.

General

Mnemonic

Instruction

MOV (B)

move

SUB

subtract

source to destination

ADD

add

source

ASH

shift

destination

source

from destination

arithmetically

ASHC

arithmetic

MUL
DIV

integer
integer

shift combined

Mnemonic

Instruction

BIT (B)
BIC (B)
BIS (B)
XOR

bit test
bit clear
bit set
exclusive

multiply
divide

Logical

7.1.2.1

Double

another

field.

Operand

Instruction

Format

The

format

most

double operand instructions (see Figure 7-2) is similar to that of
single operand instructions except that they have two fields for
locating operands.
One field 1is called the source field,
the
other
is called the destination field.
Each field
1is further
divided into addressing mode and selected register.
Each field is
completely independent.
The mode and register used by one field
may be completely different than the mode and register used by

OP CODE
1

MODE
1

@
1

* *

MODE
1

* %%

SOURCE ADDRESS

1
—

—

1
* *

DESTINATION ADDRESS

i
*

i
* % *

LEGEND

* SPECIFIES DIRECT OR INDIRECT ADDRESS

** SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED
*** SPECIFIES
A GENERAL REGISTER
MR-3644

Figure

7-2

Double

Operand

Instruction

Format

Bit 15 indicates word or byte operation except when used with
code 6.
Then it indicates an ADD or SUBtract instruction.

Bits 14-12
be done.

Bits

11-6

indicate

for

locating

Bits

5-0

the

for

code,

source

indicate

information

which

specifies

address,

which

the

contains

operation

information

operand.

the

locating

destination
the

source

address,

which

contains

operand.

7.1.2.2
setting
is

Byte
Instructions
- Byte
instructions
are
specified
by
bit 15.
Thus, in the case of the MOV instruction, bit 15
when bit 15 is set, the mnemonic is MOVB.
There are no byte

operations for ADD and
perform the equivalent
can

SUB;

i.e.,
ADDB

no
or

ADDB or SUBB.
SUBB,
the MOVB

In order to
instruction

used along with an ADD or SUB.
The MOVB instruction, when
destination address mode
is 0,
sign-extends the byte operand
through the high byte of the register.
This feature can be used

the

executing

one

general

operand

SUB

and

get

the

and

another

place

MOVB

B,R1

ADD

RO,R1

condition

codes

Program

paragraph

first

second

both

general

will

byte
MOVB

general

operand
to

get

and
the

place

second

byte

Then

byte

result.

ADD

registers.

A,RO

MOVB

7.1.3

This

MOVB

performed

Example:

The

Control

discusses

affected

based

upon

the

Instructions

program

control

instructions.

7.1.3.1 Branch Instructions - The
following
is a
list of branch
instructions and a discussion of the branch instruction format.
Branch
Mnemonic

Instruction

BR
BNE

branch
branch

BEQ

branch

BPL

branch

plus

BMI

branch

minus

(unconditional)
not equal to
equal

BVC

branch

overflow

clear

BVS

branch

overflow

set

BCC

branch

carry

clear

BCS

branch

carry

set

Signed

Conditional

Unsigned

Branch

Mnemonic

Instruction

BGE
BLT
BGT
BLE
SOB

branch if greater than or equal to 0
branch if less than 0
branch if greater than 0
branch if less than or equal to 0
subtract one and branch if not equal

Conditional

Branch

Mnemonic

Instruction

BHI
BLOS
BHIS

branch
branch
branch

BLO

branch

if
if

lower

code

BYTE OFFSET

higher
lower or same
higher or same

Branch Instruction Format (Figure 7-3)
The
high
byte
(bits
8-15)
of
the
instruction
is
an
specifying the conditions for the branch to take place.

OP CODE

T
MR .3645

Figure

7-3

Branch

Instruction

Format

The low byte (bits 0-7) of the instruction is the offset value in
words that determines the new program location
if
the branch
is
taken.
The low byte
is
treated as an 8-bit signed
integer and
since
the CPU
is
byte-organized,
the
integer
must
be
converted
from
words
to
bytes.
This
1s
done
during
execution
by
signextending the low byte and then shifting the 16-bit word left one
position to create the offset in bytes.
Then the offset is added
to the current value of the PC to form the new program location if
the branch
is taken.
Since the PC
is always
incremented by two
bytes
immediately after
the
instruction
is
fetched,
the
current
value of the PC, when the new program location is formed, points
to
the next
1location
after
the
branch.
Hence
an
unconditional
branch to its own 1location is 0007778, rather than 000408, which
is a branch to the next location.

7.1.3.2
Jump
and
Subroutine
Instructions
The
following
is
a
list
of
jump
and
subroutine
instructions,
amd
a discussion
of
their formats.
A list of related interrupt and trap instructions
is also provided along with a list of ways to exit from a main
program.

Jump

JSR
Bits

and

Subroutine

Mnemonic

Instruction

JMP
JSR

jump
jump

RTS

return

Instruction
9-15

are

Format

always

(Figure

octal

subroutine
from

7-4)

004

subroutine

indicating

the

code

MODE

for

JSR.

OP CODE

LINKAGE REGISTER

DESTINATION ADDRESS
MR.3646

Figure

Bits
may

6-8
be

specify

used

the

7-4

link

link,

JSR

Instruction

except

Any

Format

general

Bits
0-5
designate
the
destination
address
addressing mode and general register fields.
starting address of the subrroutine.
Register

and

destination.

the

004767

both

may

the

(GPRs)
can be

(program
be

link

cannot.
used in

used.

counter)

For
R7

purpose

frequently

that
consists
This specifies

used

for

both

example,

JSR

R7,

SUBR,

which

the

that

can

and destination,

R6.

only

the

other

Thus,
if the link is
the destination field.

general-purpose

R5,

any

of
the

the

link

1is

coded

used

for

registers
except

RTS Instruction Format (Figure 7-5)
The
RTS
(return
from
subroutine)
instruction
uses
the
1link
return
control
to
the
main
program
once
the
subroutine

to
1is

finished.
Bits

3-15

always

contain

octal

00020,

which

the

RTS.

Bits

0-2

specify

any

one

the

general-purpose

registers.

code

for

OP CODE

LINKAGE REGISTER

T
MR-3647

Figure

7-5

RTS

Instruction

Format

The register specified by bits 0-2 must be the same
the one used in the JSR which called the subroutine.
Interrupts

and

Traps

Mnemonic

Instruction

EMT

emulator

TRAP

trap

BPT
I0T
RTI

breakpoint trap
input/output trap
return from interrupt

RTT

return

from

Exiting from a Main Program
There are three ways of leaving

Software

Exit

The

trace

a main

trap

program.

program

specifies

jump

some

subroutine.

Trap Exit - Internal processor hardware executes
instructions
(e.g., EMT)
which cause a jump to
software

all

Once

proper

routines.

Interrupt

Exit

External

interrupt

service

routine.

that

the

above

program

point

the

cases,

has

been

main

there

hardware

executed,

jump

control

forces

jump

another

How

the

Mnemonic

program.

returned

the

program.

7.1.3.3
Condition Code Instructions - The following is
instructions that affect the condition codes in the PS,
format.

certain
special

condition

codes

are

affected

also

a list of
and their

discussed.

Instruction

cLc,CcLv,CcLZ,CLN,CCC
SEC,SEV,SEZ,SEN,SCC

clear
set

selected
selected

condition code
condition code

Instruction Format
The format of the condition
is as follows.
1.

Bits

Bit
the

The

operators,

operation

shown

Figure

7-6,

code.

4 - The "operator" which indicates set or clear with
values 1 and 0
respectively.
If
set,
any selected
is set; if clear, any selected bit is cleared.

bit
3.

15-5

code

Bits

3-0

The

corresponds

one

bits

code
the

"select"

one

these

condition
state

bit

field.

the

four

set,

set

"operator"

these

bits

code

bits.

When

then
the
corresponding
cleared
depending
on
the

(bit

Each

condition

4).

CONDITION CODE OPERATORS
15

0/1

—

OP CODE

—

OPERATOR
SELECT FIELD
MR 3648

Figure

than

one

7-6

Condition

condition

Code

Operators

can

code

instruction.
For example, both a carry
may exist after instruction execution.
Condition
are

set

particular

overflow

condition

Codes

There

four

W N

and

Format

condition

code

bits.

indicates
indicates

a
a

negative condition when
zero condition when set

indicates
indicates

an overflow condition when
a carry condition when set

set to
to 1.

These four bits are part of the processor status word
(PS).
The
result of any single operand or double operand instruction affects
one
or
more
of
the
four
conditicn
code
bits.
A
new
set
of

condition

codes
1is
usually
created
after
execution
of
each
instruction.
Some
condition
codes
are
not
affected
by
the
execution of certain instructions.
Branch instructions may test
the condition codes after
execution of
single or double operand

instruction.
instructions

The
to

check

condition
software

codes

are

conditions.

used

the

various

N Bit

1If the sign bit
The CPU looks only at the sign bit of the result.
If
is set, indicating a negative value, the CPU sets the N bit.
the

then

a positive value,

indicating

is clear,

sign bit

CPU

the

When an overflow occurs (V bit is set), the N
clears the N bit.
bit does not indicate the true sign of the result since the N bit
is equal

to bit

the

15 of

result.

Bit

Whenever the CPU sees that the result of an instruction is 0, it
If the result is not 0, it clears the 2 bit.
sets the Z bit.
of ways of obtaining a 0

There are a number

Adding

Comparing

Using

in magnitude

equal

numbers

two

result.

different

but

1in

sign

two

numbers

equal

value

the CLR instruction.

V Bit

The V bit is set to indicate that an overflow condition exists.
An overflow means that the result of an instruction is too large
There are two methods
to be represented in 2's complement format.
condition.
overflow
an
the hardware used to check for
One way is

for

the CPU to test for

a change of

sign.

When using single operand instructions, such as INC, DEC,
or NEG, a change of sign indicates an overflow condition.

When using double operand instructions, such as ADD,
or CMP, in which both the source and destination

a change

signs,

overflow

sign

in the

result

SUB,
have

indicates an

condition.

Another method used by the CPU is to test the N bit and C bit when
dealing with shift and rotate instructions.

an overflow exits.

If only the N bit

If only the C bit is set, an overflow exists.

is set,

Bit

both

the N

and

bits

are

set,

there

overflow

condition.

when the result of an
most significant bit of
the
of
instruction has caused a carry-out

The

CPU

sets

the

bit

automatically

results in a carry-out of the
the carry itself is usually
result,
the
most significant bit of
Dur ing
C bit is cleared.
the
Othewise,
moved into the C bit.
the

result.

When

the

instruction

rotate

instructions

between
the
the

the

word.
C bit.
1.

most

(ROL

and

significant

ROR),

bit

and

the

bit

least

A carry of 1 sets the C bit while
However, there are exceptions.

SUB
and
indicate

CMP

set

that

the
C
bit
when
borrow occurred.

forms

carry

there

COM

sets

the

bit,

TST

always

Mnemonic

7.1.4

buffer

clears

bit

Logical operations
(e.g.,
BIT)
do not affect
since they are not arithmetic in nature.

7.1.3.4
Miscellaneous Instructions - The following
miscellaneous program control instructions.

The

always

significant

carry

the

of
clears

bit

bit.

list

Instruction

HALT

halt

WAIT

wait

RESET

reset

for

interrupt

I/0

MTPD

move

data

MTPI

move

MFPD

instruction

move

from

data

instruction

MFPI

move

from

MTPS

move

byte

MFPS

move

byte

from

space

processor

space

space
status

processor

space

word

status

word

Examples

following

various
7.1.4.1
tally

examples

types

Single

and explanations illustrate
instructions in a program.

Operand

control

memory.

The

beginning

routine

memory

(RO)

600

(R1)

LOOP:

Instruction

loop,
has

which
been

address

Example

clears

set

out

This
a

clear

the

use

routine

the

uses

specific

block

308

byte

locations

the

location

600.

CLRB (RO) +

DEC

BNE

LOOP

HALT
Description

(RO)+

instruction

specified

pointer.

the

Because

the
autoincrement
automatically moves to the

the

CLRB

clears

the

RO.

instruction.

addressing

memory

CLRB

Program

The

contents

mode

is
location

used,

after

the
pointer
execution of

decrementing
The

Branch

R1.

Not

Zero,

counter
another

1s
not
0,
location.

program

executes

7.1.4.2

Double

out

portion

known

start

number
of locations to be cleared and
Counting is performed by the DIGITAL Rl
location is cleared,
it
1is counted by

the

that

address

INIT:

START:

Operand

BNE,

instruction

checks

for

done.

the
program branches back
to
start
If the counter is 0,
indicating done,
instruction,

Instruction

payroll

locations

are

for

the

HALT.

Example

program

to clear
then the

This

review

printed

routine
the

and

prints

supervisor.

the

locations

600.

MOV

#600,RO

MOV

#76,R1

TSTB

1I/0

BPL

START

MOVB

(RO)+,I/0+2

DEC

BNE

START

HALT

Program
MOV
1is

Description
the
instruction

normally

used

set

the

initial

conditions.
Here, the first MOV places the starting address (600)
into RO, which will be used as a pointer.
The second MOV sets up
Rl as a counter by loading the desired number of locations (76) to
be printed.
The

TSTB

printer.
of

the

The

instruction

The

BPL

tests

printer-ready

MOVB

printing.

the

instruction
flag

instruction moves

Done

Ready

causes

loop

byte

data

comes

pointer RO
location.

then

incremented

The

(R1l)

then

(bit

start

the

state

cleared.

The

counter

flag

from

of data

the

location

point

decremented

the

printer

specified

the

indicate

one

(I/0)
RO.

for

The

sequential

byte

has

been

with

the

BNE

this

indicates

transferred.

The

program

instruction.

then
If

checks

the

that more transfers must
to START and the program
When

the

counter

transferred,

the

counter

not

take place.
continues.

(R1l)

reaches

branch

does

instruction,

1loop

has

HALT.

not

for

done

reached

The

BNE

indicating
occur

and

causes

all

data

the

branch

program

has

back

been

executes

7.1.4.3

Branch

Instruction

Example
NOTE

Branch
from

instruction

+1778

A payroll program has set up
employee by his badge number.
the

employee's

badge

offsets

—2008

number;

are

limited

words.

series of words to identify each
The high byte of the word contains

the

low byte

contains

octal

number

ranging from 0 to 13 which represents his salary.
These numbers
represent
steps
within
three
wage
classes
to
identify
which
employees get paid weekly, monthly, or quarterly.
It is time to
make out weekly paychecks.
Unfortunately,
employee
information
has been stored in
a random order.
The problem is to extract the
names
of
only
those
employees
who
receive
a
weekly
paycheck.
Employee payroll numbers are assigned as follows:
0 to 3 - wage
class I
(weekly),
4
to 7 - wage class II
(monthly),
10 to 13 wage class III (quarterly).
600

1is

employee
data

the

starting

payroll

area.

The

address

information.
following

memory

1264

program

the

searches

block

containing

final

address

through

the

this

data

area

and finds all numbers representing wage class I, and, each time an
appropriate number
is found,
stores the employee's badge number
(just the high byte) on a "last-in/first-out" stack which begins
at location 4000.
INIT:

START :

MOV

#600,

MOV

#400,

CMPB(RO) +,#3
BHI

CONT

STACK:

MOVB

CONT:

INC
CMP

(RO) ,-(R1)
RO

BHIS

1264,

START

HALT

Program Description
RO becomes the address

pointer,

the

stack

pointer.

Compare the contents of the first low byte with the number 3 and
go to the first high byte.
If the number is more than 3, branch
to continue.
If no branch occurs, it indicates that the number is
3
or
less.
Therefore,
move
the
high
byte
containing
the
employee's number onto the stack as indicated by stack pointer RIl.
RO

advanced

the

low

byte.

If the last address has not been examined (1264), this instruction
produces a result equal to or greater than zero.
If the result is
equal to or greater than zero, examine the next memory location.

7.2
The

INSTRUCTION
KDF11l-AA

ease

SET

instruction

reference,

the

set

described

instructions

number of special symbols are
of
individual
instructions.
explained in Table 7-1.

Table

7-1

are

Instruction

operand

instruction

Double

operand

instruction

Program

Miscellaneous

Condition

code

()

Indicates

the

Source

dst

Destination

the

contents

Symbols

of.

For

(R5)

means

(src)

address

that

source

moves

1into.

the

source

moves

into

removed

- (SP)

Pushed

added

the

from

For

becomes

the

example,

the

hardware

(dst)

destination

location.

stack

Logical

AND

Logical

inclusive

(either

one

Logical

exclusive

(either

one,

Logical

NOT

example,

R5."

are

instruction

Popped

features

symbols

instruction

(SP) +

Reg

used

address

Becomes,

means

certain

commonly

Single

src

describe

contents

paragraph.
For
alphabetically.

The

Meaning

"the

this

used

Symbol

control

presented

both)

but

not

NOTE

Condition

code

bits

cleared
unless
listed as set.

are

they

considered

are

specifically

both)

that

ADC/ADCB
Add

0055DD

Carry

1055DD

Type:

Operation:

(dst)

Condition

Codes:

Description:

N:
Z:
V:
C:

set
set
set
set

<--

if
1f
if
if

(dst)

result <
result =
(dst) 1is
(dst) is

O
0
077777
177777

and
and

C
C

Adds
the
contents
of
the
C
bit
1into
the
destination.
This permits the carry from the
addition
of
the
1low-order
words/bytes
to
be
carried into the high-order result, such as in
performing double precision arithmetic.

ADD

Add

06SSDD

1
1

S
]

Type:

Operation:

(dst)

Condition

Codes:

S
|

<--

(src)

D
|

D
.

D
i

D
1

(dst)

set

result

set

result

set

there

1is

arithmetic

overflow

result
of
the
operation;
that
1is,
both
operands
were
of
the
same
sign
and
the
result is of the opposite sign
C:

Description:

set
if
there
1is
significant bit of

a
<carry
from
the result

the

most

Adds
the
source
operand
to
the
destination
operand
and
stores
the
result
at
the
destination address.
The original contents of
the destination are lost.
The contents of the
source

addition

are

not

affected.

performed.

2's

complement

ASH

Arithmetic

Shift

072RSS

Operation:

R <-right

Condition

Codes:

Description:

N<TMNZ

Type:

The

set
set

R shifted arithmetically
or left where NN = (src)

i1f
if

set if
loaded

result
result

sign
from

contents
left
the

source

<
=

places

the

O
0

of register changed during shift
last bit shifted out of register

the
number

operand.

D700

The

times

shift

are

shifted right
specified by the

count

1is

taken

the
low-order
6
bits
of
the
source
operand.
This number ranges from -32 to +31.
Negative
is a right shift and positive is a left shift.

ASHC

Arithmetic

Shift

Type:

Combined

Operation:

Rvl

The

Codes:

<--

double

right
Condition

073RSS

Rvl

word

left,

is
where

shifted
NN
NN = (src).

places

the

set

result

Zz:

set

result

set

sign

loaded with high-order bit when left; loaded
with low-order bit when right shift
(loaded
with the last bit shifted out of the 32-bit

bit

changes

during

the

shift

operand)

Description:

The

contents of the register
and
the
register
OR-ed with
1
are
treated as one
32-bit word.
Rvl
(bits 0-15)
and R (bits 16-31)
are shifted
right or left the number of times specified by
the shift count.
The shift count is taken as

the

low-order
six bits of the source operand.
number
ranges from -32 to +31.
Negative
a right shift and positive is a left shift.

This

When

the

chosen

odd

number,

the

register and the register OR-ed with 1 are the
same.
In this case, the right shift becomes a
rotate.
The 16-bit word is rotated right the
number of bits specified by the shift count.

ASL/ASLB
Arithmetic

Shift

Left

0063DD
1063DD

Type:

Operation:

(dst)

Condition

Codes:

<--

(dst)

shifted

one

set

high-order

bit

set

the

loaded

result

with

the

place
the

left

exclusive

the

loaded

high-order

the

result

and C bit
(as set
shift operation)
with

the

completion

bit

the

1left

one

destination
Description:

Shifts

all

bits

the

destination

place.
The low-order
bit is loaded with a 0.
The C bit of the status word is loaded from the

high-order
bit
of
performs
a
signed
destination by 2 with

the
destination.
multiplication
of
overflow indication.

ASL
the

ASR/ASRB
Arithmetic

Shift

Right

0062DD
1062DD

MR.2723

Type:

Operation:

(dst)

Condition

Codes:

(dst)

shifted

one

the

high-order

place

right

the

result

(result

set

loaded
from the exclusive OR of
the N
and C bit
(as set by the completion of
shift operation)
loaded

Shifts

the

from

all

low-order

the

bit

the

ASR

destination

performs

signed

bit

the

destination

right

place.
The high-order bit is replicated.
C bit is loaded from the low-order bit of

destination.

1is

result

bits

the

set

bit

set

Description:

<--

division

one
The
the

BCC

Branch

carry

clear

103000

0
A

1
"

CFFSET

L
MR 2724

Condition

Codes:

Description:

<--

unaffected

Tests

the

branch

state

offset)

of
clear.

the

Operation:

bit

Type:

and

causes

BCS
Branch

carry

set

103400

08
0

0
|

1
1

OFFSET

i
MR.2725

Type:

Operation:

Condition

Codes:

Description:

<--

unaffected

Tests

the

branch

result

the

offset)

state

of
set.

the

Used

bit
and
causes
a
to test for a carry

operation.

BEQ

Branch

001400

equal

]

Type:

Operation:

PC <-- PC + (2 X offset)

Condition Codes:

N:
Z:

V:
C:

Description:

OFFSET
i

if Z =1

unaffected
unaffected

unaffected

Tests

the

state

the

bit

and

causes

As an example, it is used
branch if Z is set.
g a CMP operation, to
followin
equality
to test
the destination were
in
set
bits
no
that
test
a BIT
following
source
the
in
set
also
operation, and, generally, to test that the
result of the previous operation was 0.

BGE

Branch

greater

than

equal

002000

0]
1

OFFSET

L
MR.2727

Type:

Operation:

<--

unaffected

Condition

Codes:

Description:

unaffected

Causes

a
clear
or
operation

branch

offset)

NwV

and
V
are
either
both
BGE
1is
the complementary
to
Thus,
BGE
always
causes
a
branch when it follows an operation that caused
addition
of
two
positive
numbers.
BGE
also

causes

both

set.
BLT.

branch

result.

BGT

003000

Branch if greater than

]

OFFSET

0
L

U
O

MR.2728

Condition

Codes:

Description:

<=— PC

unaffected
unaffected
unaffected
unaffected

Z2v

(2 X offset)

d
@

Operation:

N< N2

Type:

(N ¥ V)

Causes a branch if the exclusive OR of the N
Thus, BGT always branches
and V bits is 1.
following an operation that added two negative
In
occurred.
overflow
1if
even
numbers,

particular, BGT always causes a branch if it
a
on
instruction operating
CMP
a
follows
negative source and a positive destination
(even

never

overflow

causes

instruction

negative

branch

was

occurred).

branch

operating

follows

BGT

does

not

destination.

the

(without

Further,

when

result of
overflow).

positive

source

BGT
CMP

and

cause

the previous operation

BHI

Branch

higher

101000

OFFSET
1

]

l
MR.-2729

Type:

Operation:

<-=-

unaffected

Condition

Codes:

Description:

offset)

Causes

and

a
branch
if
the
previous
operation
causes neither a carry nor a 0
result.
This
will happen in comparison
(CMP)
operations as
long as the source has a higher unsigned value
than

the

destination.

BHIS

Branch

higher

than

the

same

103000

0
[

0
1

Operation:

<--

unaffected
unaffected

Codes:

Description:

OFFSET
1

Type:

Condition

0
L

O<<NZ

offset)

unaffected
:

unaffected

Tests
the
state
of
the
branch if C 1is cleared.

bit

and

causes

BIC/BICB
Bit

Clear

04SSDD
14SSDD

1
1

0
1

Type:

Operation:

(dst)

Condition

Codes:

Description:

N:
Z:

<=-

S
1

(src)

high-order

result

cleared
not

D
.

D
L

D
|

D
1

(dst)

set

D
|

set

bit

result

set

cleared

Clears
each
bit
1in
the
destination
corresponds
to a
set bit
in
the
source.
original contents of the destination are
The

contents

the

source

are

unaffected.

that
The
1lost.

BIS/BISB

05SSDD

Bit Set

15SSDD

0/1

1
1

Type:

Operation:

(dst)

Condition

Codes:

Description:

S
b

<--

S
)i

(src)

set

if high order

set

cleared

not

D
i

D
L

D
b

v(dst)

D
I

result

bit of

result

set

affected

the
between
OR operation
1inclusive
Performs
source and destination operands and leaves the
1i.e.,
address;
destination
the
at
result
corresponding bits set in the source are set in

the destination.

destination

are

The

lost.

original

contents of

the

BIT/BITB
Bit

Test

03SSDD

13SSDD

Type:

Operation:

(dst)

Condition

Codes:

Description:

2733

(src)

set

high-order

set

result

cleared

not

bit

result

set

affected

Performs
1logical AND comparison of
the
source
and destination operands and modifies condition
codes
accordingly.
Neither
the
source
nor
destination operands and modifies condition

codes
accordingly.
destination
operands
instruction may be
the
corresponding
destination

are

Neither
the
source
are
affected.
The

used
bits

clear

nor
BIT

to test whether any of
that
are
set
1in
the
the

source.

BLE

Branch

if less than or

equal

003400

0
{

1
"

OFFSET

)

Operation:
Condition

Codes:

Description:

o)
@)

Type:

<--

<Nz

dJ
@)

MR.2734

unaffected
unaffected

offset)

1if

Zv(NwV)

unaffected

Causes a branch if the exclusive OR of the N
and V bits
1is 1.
Thus, BLE always branches
following an operation that added two negative
numbers,
even
1f
overflow
occurred.
In
particular, BLE always causes a branch 1f
it
follows
a
CMP
instruction
operating
on
a
negative source and a positive destination
(even
1if
overflow
occurred).
Further,
BLE
never
causes a branch when
1t
follows
a CMP
instruction operating on a positive source and
negative

branch

was

destination.

the

(without

result

overflow).

BLE

does

not

cause

the previous operation

BLO

Branch

103400

lower

0
|

1
1

OFFSET

L
MR.2735

Type:

Operation:

Condition

Codes:

Description:

<--

unaffected

offset)

Tests
the
state
of
the
C
bit
and
causes
a
branch 1f C is set.
Used to test for a carry
in the result of a previous operation.

BLOS

Branch

lower

same

101400

0]
1

0
L

OFFSET
1

g
@)

MR.2736

Type:

Codes:

Condition

d
@)

Operation:

Description:

{==

offset)

CvZ

unaffected
unaffected

Causes

caused

either

the

branch

the

carry

complementary

operation

result.

BHI.

The

BLOS

1is

branch

occurs in comparison operations as long as the
source
1is
equal
to
or
has
a
1lower
unsigned
value than the destination.

BLT

Branch

less

than

002400

08
0

OFFSET

1
MR.2737

Type:

Operation:

Condition

Codes:

Description:

<--

unaffected

offset)

N¥V

Causes

a
branch
if
the
exclusive OR of
the N
V
bits
is
1.
Thus,
BLT
always
branches
following an operation that added two negative

and

numbers,
even
particular,
BLT
follows
a
CMP

negative

overflow

occurred.
In
causes
a
branch
if
it
instruction
operating
on
a
source
and
a
positive
destination
overflow
occurred).
Further,
BLT

(even

never

causes

always

branch

when

follows

CMP

instruction operating on a positive source and
negative
destination.
BLT
does
not
cause
a
branch if the result of the previous operation

was

(without

overflow).

BMI

Branch

100400

if minus

OFFSET

MR-2738

Type:

Operation:
Condition

Codes:

Description:

(2 X offset)

<-- PC +

N:
Z:
V:
C:

unaffected
unaffected
unaffected
unaffected

Tests

the

state

the

if N =1

bit

Used to
branch if N 1is set.
(most significant bit) of the
previous operation.

and

causes

test the sign
result of the

BNE

Branch

not

equal

001000

0
I

0
i

OFFSET

]

1
MR.-2739

Type:

Operation:

Condition

Codes:

Description:

<--

unaffected

offset)

Tests

the
state
of
the
Z
bit
and
causes
a
branch
1f
the
Z
bit
is
clear.
BNE
1is
the
complementary operation to BEQ.
It is used to
test
inequality following a CMP,
to test that
some bits set in the destination were also
in
the

source,

test

that

was

not

following

the

result

bit,

the

and,

generally,

operation

BPL

Branch

100000

plus

CFFSET

2740

Type:

Operation:

Condition

Codes:

Description:

<--

unaffected

V:
C:

unaffected
unaffected

offset)

if N

a
causes
and
the N bit
of
state
the
Tests
BPL is the complementary
branch if N is clear.
operation

BMI.

BPT

Breakpoint

Trap

000003

0
|

0
1

Type:

Operation:

(SP)

<--

(SP)

<--

(14)

<--

(16)

Condition

Codes:

Description:

0
i

0
|

0
1

loaded

from

trap

loaded

from

trap

vector

loaded

from

trap

vector

loaded

from

trap

vector

0
1

1
1

1
L

vector

Performs
a
trap
sequence
with
a
trap vector
address of
14.
Used
to
call
debugging
aids.
The
user
is
cautioned
against
employing
code
000003
in
programs
run
under
these
debugging
No information is transmitted in the low
aids.
byte.

Branch

000400

OFFSET

MR.2742

Type:

Operation:

Condition

Codes:

Description:

<--

N:
Z:

unaffected

offset)

unaffected

Provides a way of transferring program control
within a
range of -128
to +127 words with a
l-word instruction.
An unconditonal branch.

BVC

Branch

if V

bit

clear

102000

0
Il

1
L

OFFSET

]

1
MR.2743

Operation:
Condition

Codes:

Description:

<--

N:
Z:

unaffected
unaffected

Type:

unaffected
:

offset)

if V

unaffected

Tests
the
state
of
the
V bit
branch
1if
the V bit
1is
clear.
complementary operation to BVS.

and
causes
a
BVC
1s
the

BVS

Branch

V bit

set

102400

0
1

1
A

OFFSET

)

l
MR

2744

Type:

Operation:

Condition

Codes:

Description:

<--

unaffected

V:
C:

unaffected
unaffected

Tests

offset)

the state of V bit
(overflow)
and causes
a branch if the V bit is set.
BVS 1s used to
detect
arithmetic
overflow
in
the
previous
operation.

CCC

Clear

all

condition code

bits

000257

MR.-2745

Type:

Description:

Sets
and
clears
condition
code
bits.
Selectable combinations of these bits may be
cleared or set together.
Condition code bits
corresponding
to
bits
in
the
condition code
operator

(bits

0-3)

sense

bit

specified

bit

the

operator;

i.e.,

are

the

4,
the

modified

according

set/clear

bit

program

sets

the

Clears corresponding bits if bit

b1t

= 0.

the
bit

CLC

Clear

000241

MR 2746

Type:

Description:

Sets
and
Selectable

clears
condition
code
bits.
combinations
of
these
bits
may
be
cleared or
set together.
Condition code bits
corresponding
to
bits
in
the
condition
code
operator
(bits
0-3)
are modified
according
to

sense

specified

corresponding

Clears

of bit 4,
the set/clear bit of
the
1i.e.,
the
program
sets
the
bit
by bit 0, 1,
2, 3,
if bit 4 is a 1.

the

operator;

bits

bit

CLN
Clear

000250

MR-2747

Type:

Description:

Sets

and

Selectable
cleared

clears
condition
code
bits.
combinations
of
these
bits
may
be
set together.
Condition code bits

corresponding
to
bits
in
the
condition
code
operator
(bits
0-3)
are
modified
according
to

the

sense

operator;

specified
1.

Clears

of bit
4,
the
set/clear
bit of
the
i.e.,
the
program
sets
the
bit
by bit 0,
1,
2, or 3,
if bit 4 is a
corresponding

bits

bit

CLR/CLRB

0050DD

Clear

1050DD

0/1

]

Type:

Operation:

(dst)

Condition Codes:

Description:

<--

cleared

set

V:
C:

cleared
cleared

Contents of specified destination
with

Os.
NOTE

last
DATO
Previous LSI-11 processors
(or DATOB).
performed a DATIO cycle for the last bus
for hardware
cycle as a "don't care"

As a performance optimization, the
bus cycle of a CLR (or CLRB) is a

minimization.

are

replaced

CLV
Clear

000242

MR-2749

Type:

Description:

Sets

and

clears

combinations
set

together.

condition

these

code

bits

bits.

may

Condition

Selectable

cleared
code

bits

corresponding
to
bits
in
the
condition
code
operator
(bits
0-3)
are modified according
to
the
sense of bit 4,
the set/clear
bit of the
operator;
1i.e.,
the
program
sets
the
bit
specified by bit 0, 1, 2, or 3,
if bit 4 is a
1.
Clears corresponding bit 4 = 0.

CLZ

Clear

000244

Type:

Description:

Sets
and
Selectable
cleared or

clears
condition
code
bits.
combinations of these bits may be
Condition code bits
set together.
corresponding to bits in the condition code
operator
(bits 0-3)
are modified according to
the sense of bit 4, the set/clear bit of the
bit
the
sets
the program
1i.e.,
operator;
specified by bit 0, 1, 2, or 3, if bit 4 is a
Clears corresponding bits if bit 4 = 0.
1.

CMP/CMPB
Compare

02SSDD

12SSDD

0/1

0
.

Type:

Operation:

(src)

Condition

Codes:

]

(dst)

[in

set

result

set

result

set

there

detail

(src)

D
i

arithmetic

(dst)

cleared

there

bit

Compares

the

source

and

the

condition

used

the
the

i.e.,

sign
sign

of
of

result

significant
Description:

overflow;

operands of opposite
signs and
the destination are the same as
the

D
1

sets
for

arithmetic

branches.

Both

only

action

carry

the

result

and

destination

codes,
and

operands
set

the

from

which may

1logical

are

the

most

operands

then

unaffected.

condition

conditional

The

codes.

compare
is
customarily
followed
conditional branch instruction.

The

COM/COMB

Complement

0051DD
1051DD

0/1

0
|

1
|

0
1

Type:

Operation:

(dst)

Condition Codes:

set

cleared

set

Description:

set

<--

D
I

D
L

D
i

D
1

D
)\

(dst)

if most
if

0
[

significant bit of

result

result = 0

Replaces
the
contents
of
the
destination
address by their logical complements (each bit
equal
to
0
set
and
each
bit
equal
to
1
cleared).

DEC/DECB
Decrement

0053DD

1053DD

0
i

0
|

1
|

Type:

Operation:

(dst)

Condition

Codes:

N:
Z:
V:
C:

Description:

1
i

0
1

1
1

D
"

<--

(dst)

-1

set
set

if
if

result
result

set
not

if (dst)
affected

Subtract
1
destination.

was

100000

from

the

D
|

D
1

D
i’

contents

D
L

the

DIV

071RSS

Divide

0
L

1
L

S
1

Type:

Operation:

Rvl

<-- R,

Condition Codes:

set

if quotient

set

set if source = 0 or if the absolute value
of the register is larger than the absolute
(In
source.
1is the
instruction
value of
this case the instruction is aborted because
the quotient would exceed 15 bits.)

set

Description:

The

Rvl/(src)

quotient

if divide by 0

32-bit

2's

attempted

complement

integer

and

Rvl

The quotient
is divided by the source operand.
same sign
the
of
is
remainder
the
R;
is left in

the dividend.

R must be

even.

EMT

Emulator

Trap

104000

0
L

Type:
Operation:

Condition

Codes:

- (SP)

<--

-(SP)

<--

(30)

<--

(32)

N:
Z:

loaded

from

trap

vector

loaded

from

loaded

from

trap
trap

vector
vector

loaded

from

trap

vector

codes

from

V:
C:
Description:

All

operation

EMT

instructions

information
function to
EMT

the

word

status

may

104000
be

at
1s

30.

The

address

30;

taken

from

new

is
new

word

32.

EMT

used

CAUTION
frequently by DIGITAL

software

and

recommended

for

general

therefore
use.

104377
to

are

transmit

routine
(e.g.,
trap vector for
PC

the
the

used

to
the
emulating
be performed).
The

address

(PS)

and

system
not

taken

from

processor
at

address

HALT

000000

Type:

Condition

Codes:

Description:

N:
Z:

unaffected
unaffected

unaffected

Causes program execution
to cease
and
enters
console ODT
(if memory management is present,
program
execution
ceases
only
1if
1in
kernel
mode; a trap to location 10 occurs 1if 1in user
mode).
Additionally if jumper W7 on the KDF1ll

module

1is

inserted,

unconditionally.

trap

will

occur

INC/INCB
Increment

0052DD

1052DD

0/1

0
1

Type:

Operation:

(dst)

Condition

Codes:

Description:

<-=-

(dst)

N:
Z:
V:

set
set
set

if
if
1f

not

affected

Adds

D
1

D
Il

D
i

D
1

result < O
result = 0
dst was 077777

the

contents

the

destination.

IOT

I/0

000004

Trap

MR 2758

Type:

Operation:

-(SP)

Condition

<-- PS
- (SP) <-- PC
PC <-- (20)

Codes:

Description:

(22)

<--

N:
Z:
V:
C:

loaded
loaded
loaded
loaded

Performs

address
routine

from
from
from
from

IOX

and

for

low

byte.

system.

trap
trap

trap

20.

error
No

trap vector
trap vector
vector
vector

sequence

Used

the

with

to call

paper

reporting

information

tape

trap

vector

software

system

the

I/0 executive

the disk

operating

transmitted

the

JMP

Jump

0001DD

0
d

Type:

Operation:

Condition

Codes:

7Z:

V:
C:

Description:

<--

(dst)

unaffected

unaffected
unaffected

JMP provides more
then provided with

flexible program branching
It
the branch instruction.

is not limited to +177,
instructions.
branch

and -200,
words as are
a
JMP does generate

second word, which makes it slower than branch
Control may be transferred to
instructions.
any location in memory
(no range limitation)
full
the
with
d
accomplishe
be
can
and
flexibility of the addressing modes with the

exception
jump

with

mode

Execution

mode

cause

will

1illegal

instruction condition and a trap to location 4.
(Program

will

control

cannot

transferred

is legal

and

transferred

cause program control

the address held

to be

in the specified

NOTE

Instructions are word data and therefore
must be
fetched
from an
even-numbered
address.

JSR

Jump

Subroutine

004RDD

Type:

Operation:

(tmp)
<-(dst)
register) -(SP)

(push

reg

contents

reg

<--

this

address

(tmp is
<-- reg

<--

onto

(PC

holds

now

put

(tmp)

(PC

internal

processor
1location

processor

stack)

following

JSR;

regq)

now

points

subroutine

address)

Condition

Codes:

Description:

unaffected

execution

the

JSR,

the

o0ld

contents

the
specified
register
(the
1linkage
pointer)
are
automatically
pushed
onto
the
processor
stack and new linkage information placed in the
register.

Thus,

subroutines

subroutines to any depth may
the
same linkage
register.

nested

all be
There

within

called
1is
no

with
need

either to plan the maximum depth at which
particular
subroutine
will
be
called
or
include
and

1instructions

restore

since

all

manner

the

linkages
the

each

1linkage

are

processor

routine

©pointer.

saved

stack,

any
to
save

Fur ther,

re-entrant

execution

subroutine
may
be
interrupted,
and
the
same
subroutine
re-entered
and
executed
by
an
interrupt
service
routine.
initial
subroutine
can
then
other
requests
are
(called nesting) can

Execution
of
the
be
resumed
when

satisfied.
proceed to

This
process
any level.

JSR PC, dst is a special case of the subroutine
call
suitable
for
subroutine
calls
that
transmit parameters.
JSR PC saves the use of

extra

In both JSR and JMP the address is used to load
the program counter, R7.
Thus, for example, a
JSR 1is destination mode 1 for general register
R1 (where (R1l) = 100) will access a subroutine
at location 100.
This is effectively one level

less of deferral

than operate

instructions

such

ADD.

JSR with
instruction
address 4.

mode

and

will
result
in
trap through the

an
1illegal
trap vector

MARK

0064NN

MR.2761

Type:

Condition

Codes:

Description:

<--

(spP)

<--

NnN<NaZ

Operation:

unaffected

number

parameters

unaffected
unaffected
unaffected

Used

as part of the standard subroutine return
convention.
MARK
facilitates
the
stack
clean-up
procedures
involved
in
subroutine

exit.

Assembler

format

is:

MARK

MFPD/MFPI
Move

from

Data

Move

from

Instruction

Space

0065SS
Space

1065SS

MR.2762

Type:

Operation:

Condition

Codes:

Description:

(tmp)

<--

(src)

-(SP)

<--

(temp)

N:
Z:
V:

set

the

source

if the
cleared

source

unaffected

onto

the

set

Pushes
address

word
in

current

space.

The

stack

from

source

address

is
computed
using
the
current
registers
and
memory map.
Since data space does not exist in
the KDF1l1l, MFPD executes the same as a MFPI.

MFPS

1067DD

MR 2763

Codes:

Description:

<N
Z

Condition

<--

lower
set
set

if
if

bits

PS
PS

bit 7
<0:7>

(dst)

dst

Operation:

Type:

cleared
unaffected

The 8-bit contents of the PS are moved to the
effective destination.
If destination mode 1is
0, PS bit 7 is sign-extended through upper byte

the

treated

The

KDF1ll

byte

The

destination

operand

1is

address.

implements

the

address,

777776,

which
can
be
used
as
another
method
of
This method can be used on
accessing the PS.
all PDP-11ls except previous LSI-11 processors.

MFPT

Move

From

Processor

Type

Type:

Operation:

Condition

Codes:

Description:

000007

<--

000003

unaffected

Z:
V:
C:

unaffected
unaffected
unaffected

unique

processor
RO.
The
and

can

program
LSI-11/2
reserved

number

assigned

each

PDP-11

model is loaded into general register
KDF1l1l-AA
processor
number
is
000003

used

indicate

1s
being
executed
processors
treat
instruction trap.

which

on.
this

processor

LSI-11
and
opcode
as
a

MOV /MOVB

Move

01SSDD
11SSDD

0
.

Operation:

(dst)

N:
Z:

Codes:

Type:

Condition

if
if

(src)
(src)

cleared

not

<
=

D
1

are

operand
to
the
destination
previous
contents
of
the

lost.

The

source

Byte:

Same

(mode

MOV.

(unique

extends

the

operates

most

bytes

exactly

NOTE

performance

bus

cycle

(or

DATOB)
.

performed

The
MOVB
to
a
register
among
byte
instructions)
significant
bit
of
the

into the high
Otherwise MOVB
MOV operates on

words.

operand

affected.

low-order byte (sign extension)
byte of the selected register.

D
.

source
The

destination
not

affected

Moves
the
location.

Description:

S
|

(src)

<--

set
set

"don't care"

optimization,

MOV

the

last

DATO

(or

MOVB)

1is

cycle

for

MOVB

Previous LSIi=11 processors

DATIO

for

hardware minimization.

MTPD/MTPI

Move
Move

to Previous Data Space
to Previous Instruction Space

1066SS
0066SS

0/1

0
1

]

1
L

1
|

D
1

D
i

D
1

D
|

Type:

Operation:

(temp)
(dst)

Condition

0
1

Codes:

N:
Z:
V:
C:

Description:

<-<--

(SP)
(temp)

set if the
set 1f the
cleared
unaffected

source
source

<
=

0
0

This
instruction pops a word off
the
current
stack determined by PS (bits 15, 14) and stores
that word into an address in previous space PS
(bits
13,
12).
The
destination
address
is
computed

using

the

current

registers

and

memory

exist

the

KDFll,

map.

Since
MTPD

data

space

executes

the

does

not

same

MTPI.

NOTE

As
bus

performance
cycle

optimization,

MTPD

and

MTPI

the

last

DATO.

This instruction was not implemented
previous LSI-11 processors.

MTPS

1064SS

2766

Type:

Operation:

Condition

Codes:

<--

(SRC)

set

according

same

effective

src

operand

0-3

same
same

The

eight

bits

the

effective

operand

replace

the current low byte contents of the PS, 1if 1in
kernel
mode.
Only
PS
bits
0
through
3
are
affected if in user mode.
The source operand
address
1s
treated
as
a
byte
address.
that PS bit 4
(T bit) cannot be set with
instruction in either kernel or user mode.
src

operand

remains

The

KDF1ll

implements

PDP-1ls

except

[

all

Note
this
The

unchanged.
the

address,

which
can
be
used
as
another
accessing the PS.
This method can

Description:

LSI-11

777776,

method
be used

of
on

processors.

MUL

Multiply

070RSS

1
I

1
1

0
1

R
1

Operation:

Rvl

<--

set

product

set

product

V:
C:

cleared
set
1if

Condition

Codes:

greater

Description:

S
i

Type:

R X

S
L

S
1

S
i

(src)

the
than

The

result
is
lfi%s
than
or equal to 2
-1.

contents
of
source
taken
as
multiplied
and

the

destination
2's
complement
stored
in
the

-2

which

Assembler
syntax
1is:
actual
destination

the

reduces

just

R when

MUL
S,
R.
R,
Rvl,

1is

odd.)

NEG/NEGB
Negate

0054DD
1054DD

MR.2768

Type:

Operation:

(dst)

Condition

Codes:

Description:

<--

(dst)

if
1f

result
result

N:
Z:

set
set

V:
C:

set if result = 100000
cleared if result = 0

Replaces
address

100000

the
by

1its

<
=

O
0

<contents
2's

replaced

the

complement.

itself.

destination
Note

that

RESET

000005

MR.2769

Type:

Operation:

PC (SP)

PS (SP)

Condition

Codes:

Description:

unaffected

Causes bus signal BINITL to be asserted for 10
microseconds
and
then
unasserted
for
90
microseconds.
Used to
initialize I/0 devices
attached
to
the
management
status
cleared.

bus.
In
registers

addition,
memory
SRO
and
SR3
are

ROL/ROLB
Rotate

0061DD

Left

1061DD

Type:

Operation:

(dst)
rotate

Condition

Codes:

<--

(dst)

left

one

place

set if
is set

the high-order
(result > 0)

set

all

loaded
and

rotate
C:

loaded

bits

with
bit

the

(as

the

bit

result

exclusive

set

the

result

word

the

completion

word

bit

the

operation)
with

the

high-order

bit

destination
Description:

Rotates all
bits of
the destination
1left
one
place.
The high-order bit is loaded into the C
bit
of
the
status
word
and
the
previous
contents
of
the
C
bit
are
1loaded
1into
the
low-order

bit

the

destination.

ROR/RORB
Rotate

0060DD
1060DD

Right

0/1

00
D

MR 2771

Type:

Operation:

Condition

(dst)

Codes:

Description:

<--

(dst)

rotate

right

set

high-order

set

all

loaded with the
and the C bit as

loaded
with
destination

Rotates
place.

one

place

bits

bit

result

the

result

are

exclusive OR
set by ROR

the

1low-order

set

the

bit

the

all bits of the destination right one
The low-order bit is loaded into the C
bit and the previous contents of the C bit are
loaded
into
the
high-order
bit
of
the
destination.

RTI

000002

MR 2772

Type:

Operation:

Condition

Codes:

Description:

<--

(SP)

<--

(SP)

N:
Z:

loaded
loaded

V:
C:

loaded
loaded

from
from
from
from

processor
processor

stack
stack
stack
stack

Used to exit from an interrupt or trap service
routine.
The PC and PS are restored
(popped)
from

T
to

processor

stack.

the

PS,

trace

executing

the

bit

the

trap will

instruction.

RTI

sets

occur

the

prior

RTS

Return

from Subroutine

00020R

0
.

0
i

0
1

Type:

Operation:

Codes:

Description:

0
i

<--

(reg)

Condition

0
|

1
i

0
Il

0
4

0
|

]

R
i

R
.

(regq)
<--

unaffected

Loads contents of register into PC and pops the
top
element
of
the
processor
stack
into
the
specified
register.
Return
from
a
non-reentrant
subroutine
is
typically made
through the same register that was used in 1its

call.
Thus, a subroutine called with a JSR PC,
dst
exits
with
an
RTS
PC,
and
a
subroutine
called

with

parameters

with

and

(R5)

JSR

R5,

addressing

finally

dst
modes

exit,

with

may

pick

(R5)+,

X (R5),

R5.

RTS

RTT

000006

Type:

Operation:

<--

(SP)

<--

(SP)

Codes:
O <N

Condition

Description:

loaded

from

processor

stack

loaded

from

processor

stack

loaded

from

processor

stack

loaded

from

processor

stack

Used to exit from a trace trap
(T
routine
and
executes
the
same
instruction
with
one
exception.

sets
will

bit)
service
as
the
RTT
If
the
RTT

the T bit in the PS, the next instruction
be executed and then the trace trap will
be processed.
However,
if an RTI
sets the T
bit in the PS,
a trace trap will occur before
the next instruction is executed.

SBC/SBCB
Subtract

0056DD

Carry

0/1

1056DD

0
|

0
1

Type:

Operation:

(dst)

Condition

Codes:

Description:

0
1

1
)|

result

if
if

result = 0
(dst) = 100000

cleared

D
1

(dst)

set
set
set

1
I

<--

Z:
V:

1
1

D
.

D
|

D
1

D
.

(dst)

and C =1
and C = 1

Subtract
the contents of
the C bit
from the
destination.
This permits the carry from the
subtraction of the low-order words/bytes to be
subtracted
from
the
high-order
part
of
the

result

order

subtraction.

perform

double

precision

SCC

Set

all

Condition

Code

Bits

000277

MR.2776

Type:

Description:

Sets

and clears condition code bits. Selectable
combinations
of
these
bits may be
cleared
or
set

together.

Condition

code

bits

corresponding
to
bits
in
the
condition
code
operator
(bits 0-3)
are modified according
to
the

sense

operator;

specified
1.

Clears

bit

1i.e.,

bit

the

set/clear

program

corresponding

bit

sets

the

bit

bits

bit

SEC

Set

000261

MR 2777

Type:

Description:

Sets

and

clears

condition

Selectable

combinations

cleared

set

corresponding
operator

together.

bits

Clears

0-3)

are

code

these

Condition

the

bits.

bits

may

code

bits

condition

code

to
the sense of bit 4,
the set/clear bit of the
operator;
1i.e.,
the
program
sets
the
bit
specified by bit 0, 1, 2, or 3,
if bit 4 is a

(bits

corresponding

modified

bits

according

bit

SEN

Set

000270

Type:

Description:

Sets
and
clears
condition
code
bits.
Selectable combinations of
these
bits may be
cleared or set together.
Condition code bits
corresponding
to
bits
in
the
condition
code
operator
(bits 0-3)
are modified according to
the sense of bit 4,
the set/clear bit of the
operator;
1i.e.,
the
program
sets
the
bit
specified by bit 0, 1, 2, or 3, if bit 4 is a
1.
Clears corresponding bits if bit 4 = 0.

SEV
Set

000262

0
MR.2779

Type:

Description:

Sets

and

clears

condition

Selectable

combinations

cleared

set

corresponding

together.

code

these

bits.

bits

Condition

may

code

bits

condition

code

bits

the

bit

bits

bit

operator
(bits
0-3)
are modified according
to
the
sense of bit
4,
the
set/clear
bit of
the
operator;
1i.e.,
the
program
sets
the
bit

specified
l.

Clears

bit

corresponding

SEZ
Set

000264

Type:

Description:

Sets
and
Selectable
cleared or

2780

clears
condition
code
bits.
combinations of these bits may be
set together.
Condition code bits
corresponding
to bits
in
the condition code
operator
(bits 0-3)
are mecdified according to
the sense of bit 4, the set/clear bit of the

operator;
1i.e.,
the
program
sets
the
bit
specified by bit 0,
1,
2,
3,
if 4
is a 1.
Clears corresponding bits if bit 4 = 0.

SOB
Subtract

one

and

branch

not

equal

077R00

plus

1
|

06
R
I\

offset

OFFSET

L
MR-2781

Type:

Operation:

Condition

Codes:

<--—

<--

unaffected

unaffected
unaffected
unaffected

V:
C:
Description:

this

result

does

not

then

X offset)

The
register
1is
decremented.
If
it
1is
not
equal to 0, twice the offset is subtracted from
the PC
(now pointing
to
the
following
word).

The

offset

interpreted

number.

This

efficient

method

syntax

1loop

6-bit

positive

provides

control.

fast

Assembler

is:
SOB

where

instruction

Note that the SOB instruction cannot be used
transfer control in the forward direction.

the

address

made

the

decremented

which
R

transfer
not

equal

SUB

Subtract

16SSDD

|
1

Operation:

(dst)

Codes:

Type:

Condition

S
1

<--

(dst)

D
.

D
1

D
I\

(src)

set

result

set

result

set
1if
there
1is
arithmetic
overflow
as
a
result
of
the
operation,
1i.e.,
1f
the
operands were of opposite signs and the sign
of the source is the same as the sign of the
result

cleared

significant
Description:

there

bit

carry

the

result

Subtracts
the
source
destination
operand
and
the destination address.

from

arithmetic,
borrow.

most

operand
from
the
leaves
the
result
at
The original contents

of the destination are 1lost.
The
the
source
are
not
affected.
precision
indicates

the

bit,

contents of
For
double
when

set,

SWAB

Swap

Byte

0003DD

MR.2783

Type:

Operation:

Condition

Codes:

Description:

Byte

1/Byte

Byte

0/Byte

set if high-order bit
7) of result is set

low-order

set

result

cleared

Exchanges

the

low-order

byte

high-order byte and
destination which must be

byte

(bit

low-order byte of
a word address.

SXT

0067DD

Extend

Sign

MR.2784

Type:

Operation:

Condition

Codes:

(dst)

<--

(dst)

<--

if N bit

N:
Z:

unaffected
set if N bit

V:
C:

cleared

1is

clear

set

clear

unaffected

If the condition code bit N is set, then a -1
is placed in the destination operand; if N bit
is clear, then a 0 is placed in the destination
This instruction 1is particularly
operand.
useful in multiple precision arithmetic because
to be extended through
sign
the
it permits

Description:

multiple

words.
NOTE

bus

performance

a SXT

is a DATO.

processors

performed

cycle

LSI-11

cycle for
care"

optimization,

for

the

last

DATIO

the last bus cycle as a "don't

hardware minimization.

TRAP

104400

104777

00
1

0
|

1
|

Type:

Operation:

(SP)

<--

(SP)

<--

(34)

<--

(36)

N:
Z:
V:
C:

loaded
loaded
loaded
loaded

Condition

Codes:

Description:

Operation

104400

from

trap

vector

from

trap

vector

from

trap

vector

from

trap

vector

codes

from

104777

are

TRAP

instructions.
TRAPs and EMTs are identical in
operation, except that the trap vecotr for TRAP

address

34.

NOTE

Since
DIGITAL
software
makes
frequent
use
of
EMT,
the
TRAP
instruction
1is
recommended for general use.

TST/TSTB
0057DD

Test

1057DD

MR 2786

Type:

Operation:

(dst)

Condition

Codes:

Description:

<--

(dst)

set

result

set

result

V:
C:

cleared
cleared

Sets the condition codes N and Z according
the contents of the destination address.

WAIT

000001

0
L

0
|

Type:

0
1

0
)

0
|

0
H

0
L

0
|

0
1

0
|

o]
Il

0
1

1
|

Operation:

Condition

Codes:

Description:

unaffected

Provides
use

way

for

the

bus

while

the

processor
it

waits

for

relinquish
an

external

interrupt.
Having been given a WAIT command,
the
processor
will
not
compete
for
the
instructions
or
operands
from
memory.
This
permits
higher
transfer
rates
between
device
and

memory,

since

processor-induced

latencies will be encountered by
from
the
device.
In
WAIT,
instructions,
the
PC
instruction
following

bus
as

requests
1in
all

points
to
the
next
the
WAIT
operation.

Thus, when an interrupt causes the PC and PS to
be pushed onto
the
stack,
the
address
of
the
next
instruction
following the WAIT
is saved.
The
exit
from
the
interrupt
routine
(i.e.,
execution
of
an
RTI
instruction)
will
cause
resumption
of
the
interupted
process
at
the
instruction

following

the

WAIT.

XOR

074RDD

MR 2788

Type:

Operation:

(dst)

Condition

Codes:

Rv(dst)

the

result

set

set if result
cleared

V:
C:
Description:

<--

unaffected

The
exclusive
OR
of
the
register
destination
operand
is
stored
in
destination address.
Contents of register
unaffected.
Assembler format is XOR R, D.

and
the
are

CHAPTER
MEMORY

8.1

MANAGEMENT

INTRODUCTION

The
KDF1ll-AA
processor
implements
a
128K
word
physical
address
space.
This improves the 32K word maximum physical address space
previously
available
in
LSI-11
processors.
The
mapping
or
translation
addresses is

of
16-bit
implemented

virtual
addresses
to
18-bit
physical
in one MOS/LSI integrated circuit.
This
chip is designated the memory management unit
(MMU).
The memory
management functionality is software-compatible with other PDP-11
processors

(e.g.

PDP-11/34,
-11/60
relocation
registers
are

programmable

mapping function.
address
to
form
transformation
8.1.1
The

-11/70).
Eight
to
accomplish
the

These registers are added to the
an
18-bit
physical
address.

occurs

transparently

executing

16-bit
The

virtual
actual

program.

Programming
memory

management

hardware

multiprogramming

environment.

modes,

user.

When

and
used

kernel

and

mode,

all instructions.
in this mode.

software

Monitors

a
multiprogramming
resident
in
memory
at
normally

does

the

any

execution

Allocates

memory

Safeguards

the

1in

user

designed

complete

control

supervisory

given

can

for

operate

1in

and

execute

programs

can
are

two

executed

several
user
programs
are
time.
The
Kkernel
software

following.

Controls

When

has

and

been

processor

environment

careful

has

The

and

the

various

peripheral

integrity

control
mode,

each

software

user

device

the

programs
resources

system

user

program

1is

executed

1in

whole

restricted

environment and
1is prevented from
that
could
be
destructive
to
the

executing certain instructions
entire
software
system.
Some

restricted

the

instructions

Modification

Halting

Using

the

could

cause

the

kernel

following.

program

computer

memory

space

assigned

the

kernel

other

users

multiprogramming system,
the memory management unit assigns
(relocatable
memory
segments)
to
a
user's
program
and
prevents
the
user
from making
any
unauthorized
access
to
those

pages

pages outside his assigned area.
Thus, a user can
prevented from accidental or willful destruction of
program

the

system

Hardware-implemented

dynamically

allocate

executive

features

memory

program.

enable

upon

effectively be
any other user

the

demand

operating

while

system

program

being

run.

8.1.2

Basic

The

PDP-11

bus

and

the

l6-bit

Addressing

family

word

KDF11-AA

word

can

length

addressing

generate

bits

logic

virtual

wide;

are

address

however,
bits

the

wide.

references

LSI-11

While

32K

words

(64K bytes),
the CPU and LSI-11 bus can reference physical
18-bit addresses up to 128K words
(256K bytes).
The
extra
two
bits of addressing logic provide the basic framework for expanding

memory

The

references.

uppermost

registers.
memory

words

address

space

1is

128K

physical

words

that

management

8.1.3
The

The

I/0O

device

Active

memory

consist

124K

Page

One

APRs

The

set

contained
8.1.4

currently
is
to

the

unit

uses

user

memory

sets

eight

32-bit

two

Size

Address

used

processor

memory

pages.

kernel

mode,

Space:

determined

status

Provided

(words):

128K

word,
Memory

(124K

Virtual

Stack

Pointers:

Memory

device

with

and

User

for

each

Pages:

for

4,096

Page

NoO

access

Protection:

Read-only

Read/write

each

pair
page

always used as a
to
describe
and

the

other

1in

user

current

CPU

mode

and

14.

Management
plus

bits)

and

Length:

active

is actually a
(PAR)
and
a

the

bits)

(18

Kernel
(one

bits

mode)

Relocation

Number

Page

Operation:

and
by

words

(16

Physical

Modes

An APR
register

These registers are
information
needed

active

used
be

Capabilities

Memory

I/0

referenced

Registers

descriptor
register
(PDR).
pair
and
contain
all
the

mode.

for

words

page registers
(APR)
(see Figure 8-1).
of
16-bit
registers:
a
page
address

the

can

registers.

management

relocate

reserved

mode)

words

for

I/0

Page)

00
PROCESSOR STATUS WORD

KERNEL (00)

APR
0O

APR 1

APR
1

APR 2

cTIvE

APR 3

»
APR 3

ACTI
PAGE

APR 4

REGISTERS

APR 5

APR
5

APR 6

APR
6

APR 7

PAR

PDR

~
~

00 /
PAR

15 _ 7

]

USER (11)

APR 0

]

\ 15

= 00

PDR

PAGE ADDRESS REGISTER

PAGE DESCRIPTION REGISTER
MR-3649

Figure

8.2

MEMORY

When

the

direct

Active

Page

Registers

RELOCATION

memory

byte

8-1

management

address

unit

longer

operating,

interpreted

the

normal

direct

16-bit

physical

address

(PA) but as a virtual address
(VA)
containing information
to be
used
in constructing a new 18-bit physical address.
The
information
contained
in
the
virtual
address
is
combined
with

relocation
and
description
information
contained
page register to yield an 18-bit physical address.

1in

the

active

Because addresses are relocated automatically, the computer may be
considered to be operating in virtual address space.
This means
that regardless of where a program is loaded into physical memory,
it will not have to be relinked;
it always appears to be at the
same

virtual

location

memory.

The

virtual

address

space

divided

into

eight

4K-word

pages.

Each page 1is relocated separately.
This is a useful feature 1in
multiprogrammed
timesharing
systems.
It
permits
a
new
1large
program to be loaded into discontinuous blocks of physical memory.
A

basic

extended

function

memory

addressing

perform

memory

capability

32K

words

physical

memory.

are

used

relocate

virtual

Two

relocation

for

systems

and

with

sets

page

address

addresses

physical

provide

than

registers

addresses

memory.

permit

These

sets

are

used

hardware

relocation

several users'
programs,
each starting at
reside simultaneously in physical memory.

registers

virtual

that

address

8.2.1
Program Relocation
page
address
registers
are
used
to
determine
the
starting
physical
address
of
each
relocated
program
in
physical
memory.
Figure 8-2 shows a simplified example of the relocation concept.

The

RELOCATION

VIRTUAL

CONSTANT

ADDRESS

A = 6400

(VA}) =0

B = 100000

PHYSICAL MEMORY
a/w

PROGRAM
B

100000g

|
——~——
PHYSICAL ADDRESS

PROGRAM A

006400g

\/\/w
000000

MR 3650

Figure

Program

physical

the

8-2

starting

address

Simplified

address

Memory

relocated

Relocation

program

virtual

address

the

will then cause physical address 6402,, which
of
program A,
to
be
accessed.
When
program
relocation
addresses

starting

constant
starting

relocation

time

program

is
at

100000,.

provide

relocation

constant

is the second item
B
1is
running,
the

changed to 100000,.
Then program B virtual
are relocated to access physical addresses
Using the active page address registers to
relink

program

each

into

different

physical

memory

location.

The

appears

start

the

address.

loaded

always

constant

64008.

eliminates

the
at

need

same

A
program
1is
blocks.
Each

relocated
block
1is

in
pages
consisting
32
words
in
length.

length of
available

a page
active

is 4096
(128 X
page registers

32,768

words

can

relocated

32) words.
in a set, a

accommodated.

anywhere

the

memory,

eight

relocated
page
begins
on
a
boundary
that
is
a
However,
for pages
that are
smaller
then

words.
the

memory

The

relocation

points

actually

about

allocated

example

memory

shown

the

to
128
maximum

Using all of the eight
maximum program length

Each

physical

of
from
1
Thus,
the

pages

can

each

long

multiple
of
32
4K words,
only

page

may

accessed.

Figure

8-3

illustrates

several

relocation.

VIRTUAL ADDRESS

PAGE|{

RANGES

RELOCATION

NO |

PHYSICAL MEMORY

CONSTANT

SPACE

160000177776

150000

340000357776

140000-157776

000000

330000347776

120000137776

100000

310000-327776

100000117776

020000

220000237776

060000077776

060000

020000037776

320000

040000~057776

000000017776

250000

»]

140000-157776

040000057776

400000

120000137776

MR-3651

Figure

8-3

Relocation

32K-Word

Physical

Although

the

program

contiguous address
space
1s
actually
areas of
physical
loaded.
2.

Pages

(even
3.

All

appears

space,
the
scattered

may

relocated

range
lower

though

124K-Word

the

processor

1in

physical address
several
separate

the total available
a
program
can
be

higher

1lower

physical

respect to their virtual address ranges.
in Figure
8-3,
page
1
is
relocated
to
a

physical

range,

its

the
pages
boundaries.

into

32K-word
through

physical memory.
As long as
memory
space
1is
adequate,

addresses with
In the example

higher

Program

Memory

and

addresses,

page

relocation
shown

1is

constant

the

page

not

example

relocated

all

non-0).
start

32-word

Each

page

relocated

independently.

There

reason

why two or more pages could not be relocated to the same
physical memory space.
Using more than one page address
register in the set to access the same space would be one
way of providing
different memory
access
rights
to
the
same
data,
referencing

8.2.2

Memory

depending
on
that data.

Page:

per

Size

pages:

8.3

blocks

(32

the

program

was

words
128

4,096

words)

mode

relocatable

memory:

part

Units

Block:

No.

which

32,768

words,

max.

4,096)

multiprogramming;

i.e.,

PROTECTION

timesharing

system

performs

several programs to reside in memory simultaneously and
sequentially.
Access to these programs, and the memory
occupy,

must

system

requires

User

strictly

several

programs

allocated
2.

Users
and

must

space

must

not

controlled.

allowed

expand

the

from

are

timesharing

protection.

authorized

prevented
that

and

memory
be

unless

algorithms

Users

defined

types

allows

to execute
space they

modifying

resident

for

beyond

their

system.

common

all

subroutines

users.

must
be
prevented
from
gaining
the operating system software.

control

modifying

Users
memory

must
be
occuplied

Memory

management

all

above

the

prevented
from
other users.

provides

types

accessing

modifying

facilities

implement

the

memory

hardware

protection.

8.3.1

Inaccessible Memory
has a 2-bit access control key associated with it.
The
key 1s part of the page descriptor
register
(PDR).
The key 1is
assigned under operating system control.
When the key is set to

Each

page

the

program

halt.

page
to

1is

defined

access

Using

this

nonresident.

nonresident

feature

provide

attempt

memory

read

Read-Only

access

are

set

user

immediate

only

legal
pages

those
access

are

set

Memory

control

(fetch)

protection,

The access control keys of all other program
which prevents illegal memory references.

8.3.2

program

keys.

The

current

Any

prevented

associated

the

pages

with

page

memory

key

for

page

references

can

the

set

page,

but

which

immediately

allows

halts

any

attempt

write

memory

protection

can

data,

subroutines,

into

that

afforded

shared

page.

rights
access

varied

altering

page

modes)

different

address

may

each

may

the

user

access

programs),

complete

8.3.3

set

and

users

keyed

Multiple

the

same

different

key

access

Address

might

for

system

access

type

sets

common

type

memory

control

rights.

key

operating

and

page

For
be

user

memory

example,

access

might

be
be

key.

(kernel

(read-only

contain

physical

access

the

for

user

(allowing

system).

Space

There are two complete PAR/PDR
for
kernel
mode
and
one
set
operating

the

kernel

read/write

This

each

for

read-only
that

to a given memory area to
right to a memory area may

reference

control
the

by
in

pages

algorithms.

protection allows the access
user-dependent.
That is, the
for

This

sets provided, one set
for
user
mode.
This

of registers
affords
the

software another type of memory protection.
The
1is
specified
by
the
processor
status
word
or previous mode field,
as determined by the

mode
of
operation
current mode field,

current
pointer
A

user

instruction.
Each
(R6)
for protection
mode

program

1is

mode has
its own corresponding
stack
as well as software considerations.

relocated

kernel programs.
in
one
mode
to

This makes
reference

accidentally

when

the

For

example,

mode

address

user

space

its

own

PAR/PDR

it impossible for
space
allocated

registers

are

cannot

transfer

space.

may

reserved

for

the

active
be

functions,

such

management

trap

handlers,

basic

page

set,

kernel

input/output

and

timesharing

a program running
to
another
mode

set

correctly.
The

kernel

resident

system

monitor

control

routines,

memory

scheduling

modules.

dividing
the
types
of
timesharing
system
programs
functionally
between
the
kernel
and
user
modes,
a
minimum
of
space
control
housekeeping
1is
required
as
the
timeshared
operating
system
sequences

from

the

user

serviced.

one

PAR/PDR

management

unit

user

set

The

two

are

shown

program

needs

PAR/PDR
in

the

next.

updated

sets

Figure

For

each

implemented

8-~4

and

example,

new

Figure

only

user

program

the

memory

in
8-5.

MR3652

Figure

8.3.3.1

Mode

specify

the

to
select
currently
memory

8-4

Specification

current

memory

Page

mode.

Processor

management

the
corresponding
executing
program.

management

Address

Status

Word

PS<15:14>

mode.

These

bits

are

PAR/PDR
set
PS<13:12>

to
be
specify

wused
the

for
the
previous

These

bits

are

used

the

used

memory

management

instructions

communicate

between

kernel

and

user

address spaces.
When an implicit mode change occurs, the previous
mode bits (PS<13:12>) are loaded by hardware with the contents of
the current mode bits (PS<15:14>).
This change can occur whenever
an
1lnterrupt or
trap
is processed.
PS<15:12>
are cleared when
power
1is
applied.
Clearing
these
bits
selects
kernel
mode.
PS<15:12>

are

encoded

shown

below.

7' /

PLF

NOTE:

7
)

ACF

ALLUNIMPLEMENTED BITS READ AS ZEROS.
MR-

Figure

8-5

Page

Descriptor

3653

PS<15:14>
or

PS<13:12>

PAR/PDR Set

Kernel

Reserved

use.

Each

for

mode

program

future

Specifies

mode

not

cause

some

Illegal.

Enabled

Does

for

DIGITAL

use.

for
use.

User

USER

own

are

initialized

and

can

8.3.3.2

Processor

software

methods

corresponding

specified by PS<15:14>.
the MMU is enabled or not

future

(USP)

stack

use

future

pointer.

different

Thus

all

Stack pointer selection occurs whether
(SRO bit 0 is a 1).
The different stack

examined

Status
of

Selected

(SSP)

Reserved

its

PS<15:14>,

Does

cause

(KSP)

DIGITAL

selects

not

Kernel

Supervisor

supervisor

PDP-lls.
halt.

Pointer

halt.

references

pointers

DIGITAL

Stack

Word

affecting

the

appropriate mode value

console

ODT.

Protection
PS<15:00>.

There

Since

are

kernel

various
mode

1is

defined to allow software access to all hardware features, free
access
to
the PS
1is allowed.
Since user mode
1is defined
for
operating user programs and thus protecting the operating system
software,

fields

are

affected.

certain

protected.

bits

such

Table

the

8-1

shows

mode

and

how

priority

all

level

bits

are

Table 8-1

RTI, RTI

Traps & Interrupts

Explicit PS Access

Kernel | User

User

PS Bits

Processor Status Word Protection

Loaded | Loaded | Loaded | Loaded
From
From
From
From

Condition | Loaded
From
Code
Stack
PS (3:0»

Stack

Vector | Source

Vector

Trap Bit

Loaded

Loaded | Loaded | Loaded

PS 4

From

Stack

Vector

Interrupt

Unchanged | From

PS(7:5)

Stack

Power

Kernel

User

Kernel

Loaded
From
Source

Loaded
From

Cleared

Source

Unchanged | Unchanged | Unchanged | Unchanged | Cleared

Loaded | Loaded | Loaded | Loaded

Priority

MTPS

Loaded

From

Vector

Vector | Source

Source

Loaded
Unchanged | From

Cleared

Source

Loaded

Loaded | Loaded | Loaded | Loaded

Loaded

MTPS

Non-

PS §

From

Non-

Accessible

Stack

Vector

Vector | Source

Source

Accessible

Mode

From

Loaded | Copied | Copied | Loaded

Unchanged | From
Stack

Cleared

Loaded

Non-

From

accessible

accessible | Cleared

Source

Loaded

Non-

From

accessible

accessible | Cleared

15:14) | (A5:14
Current

Loaded | Loaded | Loaded | Loaded

Mode

Unchanged | From
Stack

From

Vector

Vector | Source

Source

8.3.3.3
User
Mode
Restrictions
User
mode
1is
1intended
for
executing
user
programs.
While
1in
user
mode
the
program
1is
restricted

from

using

system integrity.
in user mode.

The

those

hardware features that
following hardware features

could

are

disrupt
protected

instruction
Instead
of
entering
console
ODT,
instruction causes
a
trap to kernel location 10
The
intent
is not
to allow a user
operating system.
HALT

HALT

RESET

program to halt tge

instruction

Instead

causing

instruction
is executed as
The
intent
is
to
prevent
the
initializing I/0O devices.
a

RESET

Access

system

BUS

NOP

user

initialize,

instruction.

program

to PS<03:00> only.
Al]l other PS bits
operations and cannot be affected.

are

from

vital

8.3.3.4
vectors

Interrupt and
are
forced by

All
interrupt
and
trap
be used
1in kernel mode
when the new PC and PS are fetched.
The processor's first step in
processing the interrupt or trap is to fetch the new PS value from
the
interrupt
or
trap
1location
plus
2.
This
determines
which
mode, and consequently which stack pointer, to use for pushing the
old PC and PS.
The KDF1ll-AA copies the o0ld PS into a temporary
register
and
then loads the new PS value.
PS<15:14> are loaded
from
the
memory
1location
to
select
the
new
current
mode.
PS<13:12>
(previous
mode)
are
1loaded
with
the
o0ld
wvalue
1in
PS<15:14>,

is the only
mode bits.

keep

place

This

process

using

the

memory

loaded

from

are

Trap Processing hardware to always

record

where

allows

the

what

the

communication

mode

between

management

instructions.

the

1location.

memory

bits

8.4

PAGE

ADDRESS

the

was.

the

mode

The

Thus,

service routines can be executed
in either
depending on the contents of the vector plus

The page address register
12-bit page address field

mode

copy

address

spaces

remaining
interrupt

This

current

bits

and

kernel or user
2 locations.

trap

mode,

(PAR)

(PAR), shown in Figure 8-4, contains the
(PAF) that specifies the base address of

page.

Bits

15-12

are

implemented

address

but

are

reserved

for

future

DIGITAL

use.

The

page

base

interpretation
register (PAR)
8.5

The

page

PAGE

may

thought

<containing

relocation

base

address.

indicates the basic function
in the relocation scheme.

DESCRIPTOR REGISTER

descriptor

(PDR)

(PDR),

shown

8-2

Either

the

page

address

in Figure

8-5,

contains

information relative to page expansion, page 1length,
Table 8-2 shows PAR/PDR address assignments.
control.

Table

constant,

and

access

PAR/PDR Address Assignments

Kernel Active Page Registers

User Active Page Registers

No.

PAR

PDR

No.

772340

772300

772344

772304

772342

772346

772302
772306

4
5

772350
772352

772310
772312

772356

772316

772354

777640

777600

777644

777604

777642

777646

6
7

PDR

4
5

772314

PAR

777602
777606

777€50
777652

777610
777612

777656

777616

777€54

777614

8.5.1
Access Control Field (ACF)
This 2-bit field, bits 2 and 1 of the PDR, describes the access
rights
to
this particular page.
The access bits specify the
manner in which a page may be accessed and whether or not a given
access should result in a halt of the current operation.
A memory
reference that causes a halt is not completed and 1is terminated
immediately.
Halts are caused by attempts to access nonresident
pages,
by page
length
errors,
or
by access violations
such as
attempting to write into a read-only page.

In the context of access control,
the term
action
of
any
instruction
that
modifies
addressable
word.
Table
8-3
1lists
the

"write"
indicates the
the
contents
of
any
ACF
keys
and
their

functions.

under

The

ACF

Table

written

8-3

into

Access

the

PDR

Control

Field

ACF

Key

Description

Function

Nonresident

Halt

any

access

program

control.

Keys

attempt

this

nonresident

page
01

Resident

Halt

read-only

write

any

Unused

Halt

all

Resident

Read

read/write

8.5.2
The ED

Expansion Direction (ED)
bit located in PDR bit position

this

page.

accesses.
write

halt

attempt

into

allowed.

occurs.

indicates

the

authorized

direction in which the page can expand.
A logic 0 in the bit (ED
= 0)
indicates the page can expand upward from relative zero.
A
logic
1
in
this
bit
(ED
=
1)
indicates
the
page
can
expand
downward toward relative zero.
The ED bit is written into the PDR
under
= 0),

program control.
the page
length

relative

addresses.

program

example

When
is

the

data

page

Downward

can

shown

8-7.

expansion

add

1is

shown

with
for

example

usually

program

downward

blocks

specified
An

upward

direction
adding

added.

Figure

expansion

space

Upward

pages

expansion

1increased

When the expansion direction is upward
(ED
increased by adding
blocks with
higher

1is

Figure

(ED

1),

space.

for
An

8-6.

the

page

relative

pages

page

specified

table

1lower

stack
of

that

expansion

length

addresses.
more

stack

downward

1is

PAR

000

001

—

PAF = 0170

PDR

111

00O

010100t
O0COO0C 0 110

\—_'W_J

L.Y_J

PLF =51g =4119= NUMBER OF BLOCKS

ED =0=UPWARD EXPANSION
ACF =6= READ/WRITE

NOTE:

To specify a block length of 42 for an up-

ward expandable page, write highest authorized

block number directly into high byte of PDR. Bit
15 is not used because the highest allowable block
number is 177g.

h
177g

BLOCK

%
AE%SESSRANGE

i;;//

”

TENTIAL PAGE

ANY BLOCK NUMBER

BLOCK 1768

' BLOCK 52g

BLOCK

241

51g

F AR

EXPANSION BY
CHANGING THE PLF

GREATER THAN 411q(51g)
> (VA<12:06> 518)
WILL CAUSE A PAGE
LENGTH ABORT.

024100

AUTHORIZE PAGE

OROTHRUb51g=

BLOCK
2

52g BLOCKS

017200
017176

BLOCK 1

BLOCK O

017100
017176

017000

<«+— BASE ADDRESS OF PAGE
MR-3655

8.5.3

Figure

8-6

Example

Written

Into

(W)

The W bit located in PDR bit
has been written into since

affirmative.
PDR of
that
control

The
page

logic.

Upward-Expandable

Page

position 6 indicates whether the
it was loaded into memory.
W =

W bit is automatically cleared when the
is written into.
It can be set only

page
1 1is

PAR or
by the

036776

BLOCK 177g

036700
036676

BLOCK 176g

036600
AUTHORIZED PAGE
LENGTH = 4219 BLOCKS

036576

BLOCK 175g

036500

BLOCK 126g
’

0311676
0311600

| BLOCK 125¢ /

/BLOCK 1248

ADDRESS RANGE

OF POTENTIAL PAGE
oF

CHA)IA\JNSIII\JON BH
GING
THE PLF

A
N MBER
REFERENCE
LESS

THAN

%
///

0131767

[ BLOCK 1

126g

(VA<12:06> LESS THAN 126g)
WILL CAUSE
A PAGE
LENGTH ABORT.

22277,

017100
Z

//017076/

BLOCK 0

000

/017000

<— BASE ADDRESS OF PAGE

Figure

disk

can

8-7

swapping
used

Example

and
to

Downward-Expandable

Page

memory overlay applications, the
determine
which
pages
in
memory

W bit
have

(bit
been

modified by a user.
Those
that have been written
into must be
saved
in
their
current
form.
Those
that
have
not
been written
into
(W
=
0)
need
not
be
saved
and
can
be
overlayed with
new
pages, if necessary.
8.5.4
Page Length Field (PLF)
The
7-bit
PLF
located
in
PDR<14:08>

length
from

blocks.
8.5.4.1
upward,

the

page

177,,

thus

32-word

blocks.

allowing

any

specifies

The
page

PLF

the

holds

length

authorized

block

from

numbers

128lO

The PEF is written into the PDR under program control.

PLF

blocks

For

PLF

must

Upward-Expandable Page - When the page expands
be set to one less than the intended number
authorized for
that page.
For example,
if
528
(42,
,)

the

blocks are authorized, the PLF is set to 51

(4110)

(Figure 8—%9.

The hardware compares the virtual address bfock number, VA<12:06>
with

the
PLF
to
determine
authorized page length.

the

virtual

address

within

the

When
PLF,

the
the

virtual
virtual

address
address

block number is less than or equal to
is within the authorized page length.

the
1If

the virtual address 1is greater than the PLF, a page length fault
(address too high)
is detected by the hardware and a halt occurs.
In this case,
the virtual address space legal to the program
is
noncontiguous
because
the
three
most
significant
bits
of
the
virtual address are used to select the PAR/PDR set.
8.5.4.2
PLF For
a Downward-Expandable Page - The capability of
providing downward expansion for a page is intended specifically
for those pages that are to be used as stacks.
A stack starts at
the highest location reserved for
it and expands downward toward
the lowest address as items are added to the stack.
When

the

page

downward

expandable,

the

authorize
a page
1length,
in
blocks,
that
address of the page.
That is always block
8-7,

which

shows

length

can be
8-6.

compared

example

blocks

with

the

PLF

starts
177,.

must

downward-expandable

arbitrarily

chosen

upward-expandable

set

at the highest
Refer to Figure
page.

that

example

the

shown

page

example

Figure

NOTE

The

same

PAF

in both examples.
to emphasize that the PAF,
address,
always determines

This is done
as
the
base

used

the lowest address of the page, whether
it is upward- or downward-expandable.
To

specify

complement
In

this

PLF

42lo

The

page
of

example,
derived
528;

2's

calculation

obtain

length

the

PLF

blocks
a

for

42-block

page

for

8
127lO
8.6

VIRTUAL AND

processor

byte

page,

write

the

required

PDR.

required.

1268
the

number

blocks

follows:

Minus

Length

Equals

PLF

52
8
4210

=
_
=

125

memory

high

Required

No.

177

The

into

complementing

Max imum
Block

downward-expandable

follows:

complement

1is

required

PHYSICAL

management

unit

and

the

8
85lO

ADDRESSES

unit
LSI-11

1is
bus

located
address

between
1lines.

the
When

central
memory

management
1is enabled,
the processor
ceases
to supply physical
address information to the bus.
Instead,
virtual addresses are
sent to the memory management unit where they are relocated by
various constants computed within the memory management unit.

8.6.1
The

Construction

basic

address

information
(PA)

illustrated

Physical

needed

comes

from

the

Figure

8-8,

and

Address

for

the

construction

wvirtual

the

address

appropriate

APF

physical

(VA),

APR

which

1is

set.

]

ACTIVE PAGE FIELD

DISPLACEMENT FIELD
MR-3656

Figure

The

virtual
1.

Interpretation

address

the

The active page field
which of eight active

(APF)
page

used
2.

8-8

The

consists

form

the

field

Virtual

Address

following.
- This 3-bit field determines
registers
(APRO-APR7)
will be
address
(PA).

physical

displacement

(DF)

This

13-bit

field

contains

an
address
relative
to
the
permits page
lengths
up
to

beginning
4K words

o§3a
page.
This
(2
=
8K
bytes)

The

into

fields

1is

Figure

further

subdivided

two

shown

8-9.

DiB

BLOCK NUMBER

DISPLACEMENT IN BLOCKS
MR-3657

Figure
The

8-9

displacement
1.

The
as

field

block
the

The

Displacement
(DF)

number

block

consists
(BN).

number

displacement

active

page

the

memory

which

that

address

the

Virtual

the

field

current

(DIB).

within

Address

following.

7-bit

the

block

the

interpreted

page.
This

block

6-bit

APR

physical

and

memory;

96)

specifies

describes.
in

e.g.,

the

starting

PAF

The
PAF

physical

physical
(part of

address

actually

indicates

memory.

field

referred

of the information needed to construct the
from
the
12-bit
page
address
field
(PAF)

the

number

This

within

contains the displacement
the block number.
The remainder
address
comes

Field

block

starting

The

formation

the

physical

address

1illustrated

Figure

8-10.

The
is

logical
as

sequence

involved

Select

current

mode

set

constructing

active

specified

The

displacement

the

wvirtual

physical

address

page

registers

depending

PS<15:14>.

active page field of the virtual
address
select an active page register
(APRO-APR7).

used

page address field of the selected APR contains
the
starting address of the currently active page as a block
number in physical memory.
block number from the virtual address is added to the
block
number
from
the page
address
field
to yield
the
number of the block in physical memory which will contain
the physical address being constructed.

number

8.6.2

follows.

in blocks from the displacement field of
address
1is
Jjoined
to
the
physical
block

yield

Determining

the

18-bit

Program

physical

address.

Physical

Address

16-bit

virtual address can specify up to 32K words,
in
the
range
from
000000,
to 177776
(word boundaries are even numbers).
The three
most significant Virtual address bits designate the PAR/PDR pair

referenced

virtual

during

address

Table

page

ranges

8-4

address

that

relocation.

Table

the

Relating Virtual Address

PAR/PDR Set

Range

PAR/PDR

PAR/PDR Set

000000-17776
020000-37776
040000-57776
060000-77776
100000-117776
120000-137776

140000-157775
160000-177776

NOTE

Any

use

words

page

causes

virtual

8-4

each

Virtual Address

specify

b WwWwNHO

the

SN O

lengths

unaddressable

address

space.

less

than

holes

the

lists
sets.

APF
]

LT-8

BLOCK NO
1

]

VIRTUAL

DIB

]

///////////
/

]

ADDRESS

]

PAGE ADDRESS FIELD
]
]
]
]

ACTIVE PAGE

]

PHYSICALBLOCKNO
]

]

b
o]
!

]

00
PHYSICAL

DIB
1

ADDRESS

{DISPLACEMENT iN BLOCKS)
MR-3658

Figure

8-10

Construction

Physical

Address

8.7
STATUS REGISTERS
Halts generated by protection
virtual address 250.
Status

hardware are vectored through kernel
registers are used to determine why

the halt occurred.
Note that a halt to a location which is itself
an
1invalid
address
will
cause
another
halt.
Thus
the
kernel
program must ensure that kernel virtual address
250
is mapped
into
a
wvalid
physical
address,
otherwise
an
1infinite
1loop
requiring operator intervention will occur.
8.7.1
Status Register 0 (SRO)
SRO contains halt error flags, memory management enable, and other
essential information required by an operating system to recover
from a halt or service a memory management trap.
The SR0O format

Its address is 777572,.
This register
of
power or a RESET instruction.

7708

ABORT-NON-__T

v—'

RESIDENT

is shown in Figure 8-11.
is cleared by application

— 4

ABORT
- PAGE

LENGTH ERROR
ABORT
- READ ONLY
ACCESS VIOLATION
MODE

PAGE NUMBER
ENABLE MANAGEMENT
MR 36549

Figure

8-11

Format of

Bits 15-13 are the halt flags.
priority order in that flags to

should

ignored.

For

Status

They may be
the right are

example,

(SRO)

considered to be in
less significant and

nonresident

halt

routine would ignore page length and access control flags.
length halt service routine would ignore an access control

service
A page
fault.

NOTE

Bit
15,
14,
or
13,
when
set
(halt
conditions)
cause
the
logic
to
freeze
the
contents
of
SRO
bits
1
to
6
and
status register SR2.
This 1is done to
facilitate recovery from the halt.

Note that only SRO bit 0 can be set under program control to
provide
memory
management
control
information.
Only
that
information which is automatically written into the remaining bits
as a result of hardware actions is useful as a monitor of the
status of the memory management unit.
Setting bits 15-13 under
program control will
not cause
traps
to
occur.
These
bits,
however, must be reset to 0 by software after a halt or trap has
occurred

order

resume monitoring

memory management.

8.7.1.1
It

Halt

set

field

Nonresident

(ACF)

attempting

key

equal

Bit

access

is
a

the

page

halt
with

nonresident
an

access

bit.

control

8.7.1.2
Halt Page Length - Bit 14 is the halt page-length bit.
It is set by attempting to access a location in a page with a
block number
(virtual address bits 12-6)
that is outside the area
authorized by the page length field
(PLF)
of the PDR for that
page.

8.7.1.3
set

Halt

Read

attempting

Only - Bit
to

write

the

halt

read-only

page,

bit.

access

key

NOTE

There are no restrictions against halt
bits
being
set
simultaneously
by
the
same

access

attempt.

8.7.1.4
Mode of Operation - Bits 5 and 6 indicate the CPU mode
(user or kernel) associated with the page causing the halt (kernel
= 00, user = 11).
8.7.1.5

Page

referenced.
page
number
identify the

Number

Bits

3-1

contain

Pages, like blocks,
field
1is
wused
by
page being accessed

the

virtual

page

number

are numbered from 0 upwards.
The
the
error
recovery
routine
to
if a halt occurs.

8.7.1.6
Enable Relocation and Protection - Bit 0
is the enable
bit.
When it is 1, all addresses are relocated and protected by
the memory management unit.
When bit 0 is set to 0,
the memory
management unit is disabled and addresses are neither relocated
nor

protected.

8.7.2

Status

(SR1)

SR1 is implemented on some PDP-11 computers to
capability.
The KDF11l-AA does not implement
does
This

provide additional
this register but

respond to its bus address, 777574,, and reads
information is provided here for clarity only.

8.7.3
SR2
1is

Status Register 2 (SR2)
1loaded
with
the
16-bit

beginning

each

set

freeze

instruction

wvirtual

fetch,

all

Os.

(VA)

the

updated

the

address

but

not

instruction fetch fails.
SR2 is read-only; a write attempt will
not modify
1its contents.
SR2
1is
the wvirtual
address program
counter.
Upon an halt, the result of SRO bits 15, 14, or 13 being

will

SR2

until

7775768.

the

SRO

address

8.7.4
SR3 is

Status Register 3 (SR3)
implemented on some PDP-11

capability.

The

reserved

future

and

SR3

7725168.

for

bit

Figure

KDF1l1-AA
DIGITAL

enables
8-13

(See

use.

the

flags

SR3

mapping.
format

are

cleared.

The

8-12.)

computers

implements

22-bit

shows

halt

Figure

bit

provide

portion
4

The

SR3.

enables

additional

SR3

address

I/0

which

mapping

SR3

ADDRESS
777576g

16-BIT VIRTUAL ADDRESS
-l

MR-3660

Figure

8-12

Format

Status

(SR2)

ENABLE /O MAPPING

ENABLE 22 BIT MAPPING
MR-3661

Figure

8-13

Format

8.8

MEMORY MANAGEMENT

Memory

management

determined
status

word

applicable

Status

INSTRUCTIONS

provides

the

current

(PS).

The

communication

between

and

modes

following

instructions

are

Instruction
move

from

MFPD

move

from

instruction space
previous data space

MTPD

move

Chapter

description.
PDP-11

8.9

directly

space

the

data

0065SS

0066DD
1065SS

space

instruction

instructions

are

Code

1066DD

set,

for

directly

MODE

enable

NOT

with

EXAMPLES

mode

are

unique

communications

and

from

1in

that

USER
STACK

-2

the

stack.
;MFPI,

detailed

compatible

computers.

MFPI,

instructions

instruction

These

PROGRAMMING
and

processor

move

spaces,

the

MFPI

MTPI

two

MTPI

other

(SR3)

to memory management.

Mnemonic

Refer

MOV

#KM+PUM,

MOV

#-1,-2(6)

CLR

INC

@#SRO

; ENABLE

MFPI

;— (KSP) €R0

PSW

s KERNEL MODE, PREV
-1 ON KERNEL

sMOVE

MEM

MGT
CONTENTS

these

user

The -1 in the
which is 0.

kernel

;MFPI,

The

MODE

stack

now

MOV

#UM+PUM,

CLR

;SET

MOV
MOV

#KM+PUM, PSW
#-1, -2
(6)

+ KERNEL

MODE,

INC

@#SRO

; ENABLE

MEM

MFPI

;— (KSP) €R16

obtain information
kernel mode, previous

contents

PSW

in the kernel stack is now
stack pointer which is 0.

the

-1

user

replaced

R16

USER

MGT
CONTENTS

replaced

the

from the user stack if the
user, two steps are needed.

MFPI

;GET

CONTENTS

MFPI

@(6)+

;GET

USER

contents

status

USER

POINTER

the

set

POINTER

FROM

KERNEL

; STACK

;USE

ADDRESS

; FROM

USER

OBTAINED

MODE

USING

now

GET

THE

DATA

; MODE

The
and

desired data from the user stack is
replaced the user stack address.

the

;MTPI,

MODE

,NOT

MOV

#KM+PUM,

MOV
INC

#TAGX,
@#SRO

MTPI

PSW

(6)

; KERNEL

MODE,

; PUT NEW
; ENABLE

USER

STACK

;1%7€(6)+
; ERROR

TAGX:CLR

@#SRO

;DISABLE

MEM

MGT

The

new PC is popped off the current stack, and since
and not register 6, the destination is register 7.

;MTPI,

The

MODE

#UM+PUM,

CLR

%36

MOV

#KM+PUM,

MOV

#-1,

INC

@#SRO

; ENABLE

MTPI

;%316

<(6)+

with

-1

PSW

;USER

; SET
PSW

MODE,

;MOVE

replaced

USER SP=0

; KERNEL

-(6)

now

mode

MODE,

-1

INTO
MEM

the

set

USER

(R16)
PREV USER
K STACK (R6)

MGT

from

the

contents

stack.

place

kernel

R16

this

MOV

kernel

stack

HLT

kernel

has

information

mode,

the

user

mode,

stack

three

the

separate

status

steps

are

needed.

MFPI

MOV

#DATA,

MTPI

@(6)+

-(6)

;GET

CONTENT

; PUT

DATA

CURRENT

STACK

:@(6)+ (FINAL

ADDRESS

RELOCATED) <€

R16=USER

POINTER

+
: (R6)

desired

obtained
1is

from

obtained

mode.

data

destination
address
relocated through the

o o)

The

the

kernel

from

the

stack,

kernel

then

the

stack

and

CHAPTER 9
POINT

FLOATING

9.1
INTRODUCTION
The floating point processor (FPP) is a microcode option (KEF1l1l-A)
for
use
with
the
KDF1l1l-AA.
The
KEF1ll-A
FPP
1is
completely
software-compatible
with
the
FPll-A
used
on
the
PDP-11/34,
the
FP11-E used on the PDP-11/60 and the FP11-C used on the PDP-11/70.
Both
single
and
double
precision
floating
point
capability
are
available
together
with
other
features
including
floating-to-integer and integer-to-floating conversion.

The FPP microcode resides in two MOS/LSI chips contained in one
40-pin package.
The FPP requires the MMU chip, in addition to the
base MOS/LSI
chips,
because
all
the floating point accumulators
and status registers reside in the MMU.

9.2

FLOATING

Mathematically,

the

form

For

POINT
a

DATA

FORMATS

floating

nonvanishing

point

where

number,

number

and

may be defined as having
integer and f is a fraction.
are

uniquely

determined

imposing the condition 1/2 < f < 1.
The fractional part (f)
of
the number
is then said
to be normalized.
For
the number
0,
£
must be assigned the value 0, and the value of K is indeterminate.
The

FPP

floating

mathematical
of
floating

floating
double

mode,

point

data

formats

are

representation for floating
point
data
are
provided.

the

data

bits

long.

derived

from

this

point numbers.
Two types
In
single
precision,
or

Sign

double

precision,

magnitude

notation

or
1is

used.

9.2.1
Nonvanishing Floating Point Numbers
The fractional part
(f)
is assumed normalized,
so that its most
significant bit must be 1.
This 1 is the "hidden" bit: it is not
stored explicitly in the data word, but the microcode restores it
before
carrying
out
arithmetic
operations.
The
floating
and
double

bits,

and

Eight

modes
reserve
with the hidden

23
and
55
bit, imply

bits,

respectively,
for £f.
These
effective word lengths of 24 bits

bits.
bits

are

reserved

for

storage

128 (200,) notation (i.e.,
Thus
exponents
from -128

as
to

3774,

reasons

255,.,.

For

the

exponent

excess

K + 2004), giving a biased exponent.
+127
could
be
represented
by
0
to

given

below,

biased

exponent

of % (true exponent of -2004), is reserved for floating point 0.

Thus exponents are restricted to the range -127 to +127
(—1778 to +1778) or, 1n excess 2008 notation, 1 to 3778.

inclusive

The remaining bit of the floating point word
number is
negative if the sign bit is a 1.

bit.

the

sign

The

9.2.2
Floating Point Zero
Because of the hidden bit, the fractional part is not available to
distinguish
between 0
and nonvanishing numbers whose
fractional
part is exactly 1/2.
Therefore the FPP reserves a biased exponent
of 0 for
exponent
in

this
0

purpose

either

and

any
or

traps

floating point number with a biased
treated as if it were an exact 0

arithmetic operations.
An exact or clean
whose bits are all Os.
A dirty 0 is a

word

represented by a
point number

floating

with a biased exponent of 0
and a nonzero fractional part.
An
arithmetic operation for which the resulting true exponent exceeds
2778
is
regarded
as producing
a
floating
overflow;
if
the
true
exponent
1is
less
than
-177,,
the
operation
is
regarded
as
producing a floating underflow.
A biased exponent of 0 can thus
arise
from
arithmetic
operations
as
a
special
case
of
overflow
(true

exponent

reserved

for

obtained

from

the

—2008).

biased

such

(Recall

exponent.)

overflow

and

that

The

underflow

9.2.3
The Undefined Variable
The undefined variable is defined

only

eight

fractional

any

are

results

correct.

bit

bit
of
1
and
a
biased
exponent
of
0.
variable" is used, for historical reasons,

bits

part

pattern

with

The
term
to indicate

sign

"undefined
that these

bit
patterns
are
not
assigned
a
corresponding
floating
point
arithmetic value.
Note that the undefined variable is frequently
referred to as -0 elsewhere in this specification.
A

design

objective

the

FPP

was

variable would not be stored as the
operation
1in
a
program
run
with

interrupts

disabled.
This
underflow,

overflow

and

disabled.
reference

This
the

1is

9.2.4

Floating
Figures

floating

feature,

together

with

undefined

variable

(implemented

point

Floating

point
9-1

Point
data is

and

that

achieved by storing
the
corresponding

discussed later), is intended
aid:
if
the
presence
of
-0
previous

assure

result of any
the
overflow

the

undefined

floating point
and
underflow

an exact 0
interrupt

ability
to
detect
by the FIOV bit

to provide the user with a debugging
occurs,
it
did
not
result
from
a

arithmetic

instruction.

Data

stored

words

memory

illustrated

9-2.

F FORMAT, FLOATING POINT SINGLE PRECISION
15

FRACTION <15:0>
1

15
MEMORY +0

EXP
i

FRACT <22:16>
i

]

.
MR.3604

Figure

on
is

9-1

Single

Precision

Format

D FORMAT, FLOATING POINT DOUBLE PRECISION
15

FRACTION <15:0>
4

FRACTION <31:16>
L

[

]

FRACTION <47:32>
1

15
MEMORY +0

]

EXP
1

FRACT <54:48>

S =SIGN OF FRACTION
EXP = EXPONENT IN EXCESS 200 NOTATION, RESTRICTED TO 1 TO 377 OCTAL
FOR NON-VANISHING NUMBERS.
FRACTION =

23 BITSIN F FORMAT, 55 BITS IN D FORMAT + ONE HIDDEN

BIT (NORMALIZATION).

THE BINARY RADIX POINT ISTO THE LEFT.
MR.-3605

Figure

The

FPP

provides

9-2

for

Double

Precision

conversion

Format

floating

point

integer

format and vice-versa.
integer
(I)
and double

The processor recognizes single precision
precision integer long
(L)
numbers, which

are

2's

stored

standard

complement

form.

(See

Figure

9-3.)

9.3
FLOATING POINT STATUS REGISTER (FPS)
This register provides mode and interrupt control for the floating
point
unit
and
conditions
resulting
from
the
execution
of
the
previous instruction.
(See Figure 9-4.)
For

the

Three

purposes

bits

the

Single/Double:
double

discussion

FPS

Floating

set

bit

control

point

the

numbers

and

reset

modes

can

either

bits

bit

single

operation.

precision.

Long/Short:

Integer

numbers

Chop/Round:
The result of
either chopped or rounded.
"truncate"
1in
series used in

can

bits.

a floating point operation can
The term "chop" is used instead

be
of

order
to
avoid
confusion
with
truncation
approximations for function subroutines.

| FORMAT, INTEGER SINGLE PRECISION

NUMBER <15:0>
A

]

L FORMAT, DOUBLE PRECISION INTEGER LONG
15

MEMORY +0

NUMBER <30:16>
1

NUMBER <15:0>
1

]

WHERE S = SIGN OF NUMBER

NUMBER = 15 BITS IN | FORMAT, 31 BITS IN L FORMAT.
MR-3606

Figure

9-3

2's

Complement

FER FID / 4 ;/ FIUV| FiU FIv

FIC

Format

RESERVED

FN | FZ

2
RESERVED

MR-3607

Figure

9-4

Floating

The

FPS

contains

bits):

carry,

overflow,

zero,

the

The

FPP

processor

status

recognizes

Detection
Floating

six

the

error

floating

presence

flag

and

condition

Status

and

negative,

four

condition

which

are

codes

analogous

codes.

point

the

exceptions:

undefined

variable

in memory

overflow

Floating underflow
Failure of floating
Attempt
Illegal

Point

integer

conversion

to divide by 0
floating opcode.

For the first four of these exceptions, bits in the FPS register
are available to individually enable and disable interrupts.
An
interrupt on the occurrence of either of the last two exceptions
can be disabled only by setting a bit which disables interrupts on
all

six

the

exceptions,

group.

the

thirteen

output

FPS

bits,

floating

five

point

are

set

the

instruction:

FPP

the

part

error

flag

the
and

condition codes.
Any of the mode and interrupt control
be set by the user;
the LDFPS instruction is available
purpose.
shown in
9-1.

These thirteen
Figure 9-4.
The

Table

Bit Name
15

Floating

bits may
for this
bits are stored in the FPS register as
FPS register bits are described in Table

9-1

FPS

Bits

Description
Error

The

FER

bit

set

Division

zero

Illegal

Any

the

FPP

(FER)

opcode

occurs

one of
the
remaining occurs
the
corresponding
interrupt
enabled.

Note

that
independent

set

Note

the

above
whether
the

action

FID

bit

clear.

also

FER

bit.

FPP,

that

the

FPP

never

resets

the

Once

the

FER

bit

set

the

can

cleared

only

instruction
(note the RESET
does not clear the FER bit).
that
the

and

the FER
most

instruction

bit is
recent

produced

LDFPS

instruction
This means

up to date
floating

only if
point

floating

set,

all

point

exception.
14

Interrupt
(FID)

Disable

the

point

bit

1is

interrupts

FID

are

floating

disabled.

NOTES

The

FID

bit

is
feature.

maintenance
normally

must
that

always
2.

clear.

be clear
storage

1In

if one
of
-0

accompanied

primarily
a
It
should
particular, it

wishes to assure
by
the
FPP
is
an

interrupt.

Throughout

the rest of this chapter,
it
is
assumed
that
the
FID
bit
is
clear
in
all
discussions
involving
overflow,
underflow,
occurrence of

-0,

and

integer

conversion

errors.

Table

9-1

FPS

Bits

(Cont)

Bit Name

Description

Reserved

for

future

DIGITAL

use.

Reserved

for

future

DIGITAL

use.

Interrupt
Undefined

Variable

-0
of

(FIUV)

interrupt occurs if FIUV is set and a
is obtained from memory as an operand
ADD,
SUB,
MUL,
DIV,
CMP,
MOD,
NEG,

ABS,

TST,

interrupt
KEF11-A

any

occurs

except

LOAD

instruction.

before

execution

NEG,

ABS,

and

The

the

TST

which
it occurs after execution.
FIUV is reset, -0 can be loaded and
in
any
FPP
operation.
Note
interrupt
is
not
activated

for

When
used

that

the

presence

of
-0
in
an AC operand of
an
arithmetic
instruction;
in
particular,
trap

The

Interrupt

Underflow

-0

never

KEFll-A

-0

without

occurs

will

the

not

mode

store

result

simultaneous

interrupt.

When

the

FIU

bit

1is

set,

floating

underflow will cause an interrupt.
fractional
part
of
the
result
of

(FIU)

operation

causing

correct.
too

the

interrupt

will

The

biased

exponent

will

400,,

except

for

large

special

case of 0, which is correct.
is
discussed
later
in

detailed
description
instruction.
the

FIU

occurs,
result

Interrupt
Overflow
(FIV)

When

bit

no
is

reset

set

the

FIV

exact

bit

operation

causing

correct.

The

small

the

FIV

there

exact

and

interrupt

overflow will
cause
fractional
part
of

too

be
An
the

LDEXP

underflow

occurs

and

the

set,

floating

an
interrupt.
the
result
of

The
the

the

overflow

will

biased

exponent

will

4008.

the

The
the

the

exception

occurrence

reset

and

interrupt.

overflow

The

FPP

occurs,

returns

Table

9-1

Bit Name

FPS

Bits

(Cont)

Description
Special

cases

overflow

are

in the detailed descriptions
and LDEXP instruction.

Interrupt on Integer
Conversion Error
(FIC)

discussed

the

MOD

When the FIC bit is set and a conversion
to
integer
instruction
fails,
an
interrupt will occur.
1If the interrupt
occurs, the destination is set to 0, and
all

other

the

registers

FIC

bit

left

reset,
will
be

operation

detailed

are

above,

but

untouched.

the result
the
same

interrupt

of
as

will

occur.

The

can

conversion
instruction
fails
if
it
an integer with more bits than
fit
in
the
short
or
1long
integer

word

specified

generates

Floating

Double

Precision

Mode

(FD)

Floating
Integer

Long
Mode

(FL)

the

when

reset,

The

single

bit

1is

Chop

Mode

precision

active

between

integer

format.

When

set,

assumed

double

(FT)

(bit

6).

FD bit determines the precision that
is used for floating point calculations.
When set,
double
precision
is
assumed;

and

32
format

used.

integer

format

precision

2's

bits).
When
is
assumed

reset,
to
be

complement

(i.e.,

bits).

When

any

2's

1in
conversion
floating
point

the

(i.e.,

the
integer
single
precision

Floating

bit

The

complement

the

bit

arithmetic

truncated).

is
set,
operation

When

the
result
of
is chopped
(or

reset,

the

result

rounded.
Reserved

Floating

Negative

(FN)

for

future

DIGITAL

use.

1is
set
1if
the
result
of
the
1last
operation was negative, otherwise it is
reset.

Floating

(FZ)

Zero

1is

set

operation

was

the

result

otherwise

the

last

reset.

Table

9-1

FPS

Bit Name

Overflow

(Cont)

if
an

the
last
exponent

FV
is
set
resulted
1in

Floating Carry
(FC)

otherwise

the

is set

carry

This

operation
overflow,

reset.

last operation

the

most

occur

can

only

integer

double

9.4
One

Bits

Description

Floating
(FV)

resulted

significant

floating

point
coded

the

4-bit

The

244,).

(location

floating

exception

conversions.

FLOATING EXCEPTION CODE AND ADDRESS REGISTERS
interrupt vector
is assigned to take care of all

exceptions

bit.

floating

six

possible

errors

are

code

(FEC)

follows:

2
4
6

Floating
Floating
Floating

opcode error
divide by O
to integer conversion

8
10
12

Floating
Floating
Floating

overflow
underflow
undefined variable.

error

The address of the instruction producing the exception
in the floating exception address (FEA) register.
The

FEC

FEA

registers

are

one

stored

updated

only

when

exceptions

with

the

corresponding

This implies that when and only when the FER bit
are the FEC and FEA registers updated.

set by the FPP

following

and

1is

the

occurs:

Divide

Illegal

opcode

Any

the

interrupt

other

four

enabled.

NOTES

If one
occurs

interrupt
are

not

last
the

of the
with

disabled,

four exceptions
corresponding

the

FEC

and

FEA

the

FID

updated.

Inhibition

interrupts

bit does not inhibit updating of the
FEC and FEA, if an exception occurs.

The

FEC

and

FEA do not get

updated

no exception occurs.
This means that
the STST
(store
status)
1instruction
will return current information only

if
the
most
recent
floating
point
instruction produced an exception.
4,

Unlike
the
FPS
register,
no
instructions are provided for storage
into the FEC and FEA registers.

9.5
FLOATING POINT PROCESSOR INSTRUCTION ADDRESSING
Floating
point
processor
instructions
use
the
same
type
addressing
as
the
central
processor
instructions.
A
source

of
oOr

destination
operand
1is
specified
by
designating
one
of
eight
addressing
modes
and
one
of
eight
central
processor
gdeneral
registers
to
be
used
in
the
specified
mode.
The
modes
of
addressing are the same as those of the central processor except
mode
0.
floating

In
mode
0
the
point
processor

processor
follows.

dgeneral

The

FPP

1l
2

=
=

Deferred
Autoincrement

3
4

=
=

Autoincrement
Autodecrement

deferred

Autodecrement

deferred

Indexed

decrements
mode

located
rather

modes

in
the
than
in

designated
a
central

addressing

are

accumulator

deferred

Autoincrement

operand
is
accumulator,

and

autodecrement

for

the

format

user

can

and

make

operate

108

for

use

all

1increments

and

format.
six

FPP

accumulators

(ACO-AC5)
as
his
source
or
destination.
Specifying
FPP
accumulators AC6 or AC7 will result in an illegal opcode trap.
1In
all other modes, which involve transfer of data to or from memory
or

the

general

registers,

the

user

restricted

the

first

four

FPP accumulators
(ACO0-AC3).
When reading or writing a floating
point number from or to memory, the low memory word contains the

most

significant

memory

word

9.6
General

The

the

ACCURACY
comments

descriptions

accuracy

word

least

which

the

floating

significant

the

they

accuracy

the

individual

operate.

point

number

and

the

high

word.

FPP

are

presented

instructions

instruction

here.

1include

operation

the
is

regarded as "exact"
if the result is
identical to an infinite
precision calculation involving the same operands.
The a priori
accuracy of the operands
is
thus
1ignored.
All arithmetic
instructions treat an operand whose biased exponent is 0 as an
exact 0 (unless FIUV is enabled and the operand is -0, in which

case

interrupt

occurs).

For

all

arithmetic

operations,

except

DIV, a 0 operand implies that the instruction is exact.
The same
statement holds for DIV if the 0 operand is the dividend.
But if
it is the divisor, division is undefined and an interrupt occurs.
For nonvanishing floating point operands, the fractional part is
binary normalized.
It contains 24 bits or 56 bits for floating

mode

and

double

mode,

respectively.

two guard bits are necessary and
to guarantee return of a chopped

the
to

corresponding

the

chopped
(LSB);

error
Both

1/2
In

result

the

LSB

has

rounded

bounds

the

infinite

specified

precision

1length.

error

result

are

FPll-A

word

the

SUB,

with

one

error

the

FPll-E

ADD,

operation

Thus,

bound

has

realized

and

For

MUL,

sufficient for the
or rounded result

ADD

and

SUB.

rest

this

specification,

least

bound

KEFll-A

have

for

chopped

two

error

DIV,

rounded

guard

bits,

significant

1/2

LSB.

all

bit

These

instructions.

bound

arithmetic

and

general case
identical to

greater

result

than

called

exact
if no nonvanishing bits would be 1lost by chopping.
The
first bit lost in chopping is referred to as the "rounding" bit.
The value of a rounded result is related to the chopped result as
follows.

the

rounding

chopped

result

If the rounding
are identical.

follows
1.

1is

bit

the

rounded

result

1is

the

chopped

results

LSB.

rounded

and

that:

bit

incremented

the

exact,

rounded value

chopped

the

a.
b.
c.

Occurrence

result

not

value

exact,

its

exact value
magnitude

1is always decreased by chopping
1is decreased by rounding if the
1is increased by rounding if the

floating

point

overflow

and

rounding
rounding

bit
bit

is
is

0
1.

underflow

error

condition:
the
result
of
the
calculation
cannot
be
correctly
stored because the exponent is too large to fit into the eight
bits reserved for it.
However, the internal hardware has produced
the

correct

many

answer.

answer

applications.

For

the

underflow,

replacement

reasonable

resolution

This

case

done

the

KEFll-A

the

problem

for

the

underflow

interrupt is disabled.
The error incurred by this action is an
absolute rather than a relative error; it is bounded (in absolute
value) by 2**(-128).
There is no such simple resolution for the
case of overflow.
The action taken, if the overflow interrupt is
disabled,

described

under

FIV

(bit

Paragraph

9.3.

The FIV and FIU bits
(of the floating point status word)
provide
the user with an opportunity to implement his own correction of an
overflow or underflow condition.
If such a condition occurs and

the corresponding interrupt is enabled, the microcode stores the
fractional part and
the
low eight bits of
the biased exponent.
The interrupt will take place and the user can identify the cause
by
examination
of
the
FV
(floating
overflow)
bit
of
the
FEC
(floating exception) register.
The reader can readily verify that
(for
the standard arithmetic operations ADD,
SUB,
MUL,
and DIV)
the
biased
exponent
returned
by
the
instruction
bears
the
following
relation
to
the
<correct
exponent
generated
by
the
microcode.
1.

overflow,

too

small

4008.

On
If

underflow, if the biased exponent is 0,
it is not 0, it is too large by 4008.

correct.

Thus, with the interrupt enable, enough information is available
to
determine
the
correct
answer.
The
user
may,
for
example,
rescale
his
variables
(via
STEXP
and
LDEXP)
to
continue
a
calculation.
Note that the accuracy of the fractional part is
unaffected by the occurrence of underflow or overflow.
9.7
FLOATING POINT INSTRUCTIONS
Each
instruction
that
references
a
floating
point
number
can
operate on either single or double precision numbers depending on

the
that

state

the

determines

integer

(FL

floating
floating

point
point

operands

use

mode

whether

bit.
a

1is

Similarly,

32-bit

used

1in

addressing

(FL

conversion

representations.
addressing
modes

CPU

there

integer

a mode

between

FSRC
and
(see
Figure

oC
!

1integer

and
use
DST

modes.

FOC
]

]

FSRC,FDST,SRC,DST

]

SINGLE OPERAND ADDRESSING
15

ocC
l

]

FOC
1

]

FSRC, FDST, SRC, DST
]

]

)

OC = OPCODE =17
FOC = FLOATING OPCODE

AC = FLOATING POINT ACCUMULATOR (ACO-AC3)

FSRC AND FDST USE FPP ADDRESSING MODES

SPC AND DST USE CPU ADDRESSING MODES
MR-3608

Figure

9-5

Floating

Point

1l6-bit

FDST
operands
9-5);
SRC
and

DOUBLE OPERAND ADDRESSING

bit

Addressing

Modes

Terms
XL

=
1

Used

largest
- 2 **

l1
XLL

XUL

Instruction

fraction that can be represented:
(-24), FD
0; single precision

(-56),

smallest

largest

**
**

number

(-128)

number

(127)

largest

2
2

integer

(15)
(31)

1;
1;

EXP

(address)

.LT.

"less

than"

.LE.

"less

than

.GT.

"greater

than"

.GE.

"greater

than

least

that

not

(=127))

precision
identically

represented

that

can

represented:

=
=

0;
1;

biased

significant

exponent

equal

short integer
long integer

value

equal

bit

to"

zero

1/2

can

absolute
=

double

that

FL
FL

(address)

ABS

LSB

Definitions

(address)
(address)

LDF/LDD

172 (AC+4) FSRC

Load Floating/Double

MR-3609

Format:

LDF

Operation:

<--

(FSRC)

<--

FV
FZ
FN

<-<-<--

0
1
1

Condition

Codes:

FSRC,AC

if
if

(AC)
(AC)

single or

else
else

FZ
FN

<-<--

Description:

Load

double precision number

into AC.

Interrupts:

If FIUV is enabled, trap on -0 occurs before AC
is loaded.
However, the condition codes will
reflect a fetch of -0
regardless of the FIUV
bit.
Overflow

Accuracy:

These

Special

These

Comment:

and

underflow

cannot

are

exact.

instructions

permit

occur.

use

-0

1in

subsequent floating point instruction if FIUV is

not

enabled

and

(FSRC)

-0.

STF/STD
Store

Floating/Double

174 (AC)FDST

MR-3610

Format:

STF

Operation:

(FDST)

Condition

Codes:

AC,FDST

<--

<{--

<--

Description:

Store

single

Interrupts:

These

instructions

enabled,

not

because
memory.

Overflow
Accuracy:

‘Special

Comment:

double

and

instructions

These

instructions

which

from

-0

occurs

and

the

second

are

permit

stored

when

occurs

underflow

instruction
disabled.

when

from AC.

present,

FIUV

AC,

-0

1in

occur.

exact.

There

corresponding

number

interrupt

cannot

AC.

can

One

not

-0,

underflow

These

memory

the

precision

storage

are

two

and

the

overflow

interrupt
LDF, LDD,

executed

conditions
1is

KEFll-A.
present

is
enabled.
A
LDCDF, or LDCFD

the

FIUV

bit

ADDF/ADDD
Add

Floating/Double

1
l

172 (AC) FSRC

[

08
1

Operation:

Let

SUM

underflow

Condition

Codes:

Description:

00
FSRC

(AC)

exact

For

all

(FSRC).

occurs

and

FIU

not

enabled,

FIV

1is

not

enabled,

overflow

<{--

occurs

and

others

cases,

<--

SUM.

<--

overflow

occurs,

else

<--

(AC)

else

<--

(AC)

else

<--

Add

the

The

addition

contents

and

accordance

with

the

FPS

Overflow with

Underflow

For

these

FIUV

before

with

values

The

interupt

contents

single

and

stored

bits

disabled
disabled.

<cases,

exact

enabled,

trap

-0

execution.
or

with
the
fractional
parts
part

too

underflow

interrupt

occurs

exponent

AC.

double
chopped
in

the

result

interrupt

exceptional

overflow

the

in
rounded

AC.

corresponding

out

<--

for:

stored

FSRC

carried

precision

FSRC,AC

except

Interrupts:

ADDF

Format:

<--

occurs

and

enabled,

faulty

are

FSRC

result
correctly

occurs

if
the

AC.
stored.

too

small

400,

large

400,

for

underflow,

for

the
trap
The

The

overflow.

except

for the special case of 8, which is correct.

Accuracy:

Special

Comment:

are
underflow
and
overflow
to
due
Errors
If neither occurs, then: for
described above.
exponent
with
operands
signed
oppositely
difference of 0 or 1, the answer returned 1is
exact if a loss of significance of one or more
Note that these are the only
bits can occur.
cases for which 1loss of significance of more
For all other cases the
than one bit can occur.
result is inexact with error bounds of:
mode

LSB in chopping
double precision

1/2 LSB in rounding
or double precision.

with

mode

either

with

single

either

single

in
only
can occur
The undefined variable -0
will
It
underflow.
conjunction with overflow or
the corresponding
in AC only if
be stored
interrupt

enabled.

SUBF/SUBD
Subtract

Floating/Double

1
|

173 (AC) FSRC

08
1

Operation:

Let

DIFF

underflow

Description:

00
FSRC

FSRC,AC
=

<{--

exact

(AC)

(FSRC).

occurs

and

FIU

not

enabled,

FIV

not

enabled,

<--

DIFF.

overflow

<--

exact

For

all

occurs

and

others

cases,

<--

overflow

occurs,

else

<--

(AC)

else

<--

(AC)

else

<--

Subtract the contents of FSRC from the contents
of AC.
The subtraction is carried out in single
or

double

precision

and is rounded or chopped in
the values of the FD and FT bits
register.
The result is stored in AC

accordance

the

except

with

FPS
for:

Overflow

Underflow

For

these

stored
Interrupts:

SUBF

Codes:

Format:

Condition

FIUV

before

with

interrupt

with

disabled

interrupt

exceptional

disabled.

cases,

exact

AC.

enabled,

trap

-0

FSRC

execution.

occurs

If
overflow
or
wunderflow
occurs
and
if
corresponding
interrupt
is
enabled,
the
occurs
with
the
faulty
result
in
AC.
fractional
parts
are
correctly
stored.
exponent

part

too

small

400,

large

400,

for

underflow,

for

the
trap
The

The

overflow.

except

for the special case of 6, which is correct.

9-17

1is

Accuracy:

to
Errors due
described above.

overflow and underflow
If neither occurs, then:

are
for

like signed operands with exponent difference of

0 or 1, the answer returned is exact if a loss
significance of one or more bits can occur.
Note that these are the only cases for which
loss of significance of more than one bit can
For all other cases the result |is
occur.
of

inexact with error bounds of:

1. LSB

chopping

double precision

2. 1/2 LSB

mode

in rounding mode

or double precision.

Special

Comment:

with

either

with

single

either

single

The undefined variable -0 can occur only 1in
It will
conjunction with overflow or underflow.
onding
corresp
the
if
only
AC
in
be stored
interrupt

is enabled.

NEGF/NEGD
Negate

Floating/Double

15
1

1
i

Format:

1707

06
0
i

Condition

Codes:

Description:

Interrupts:

1
L

1
i

FDST

]

FDST

(FDST)
<{--

0
L

NEGF

Operation:

FDST

<--

exact

(FDST)

else

<--

(FDST)

else

<--

(FDST)

else

<--

Negate

single

result

location

FIUV

(FDST)

same
is

double

precision

number,

store

occurs

after

(FDST).

enabled,

trap

underflow

cannot

-0

execution.
Overflow
Accuracy:

Special

Comment:

These
If

and

instructions
-0

present

are
in

exact.
memory

enabled,

then

the

memory.

The

condition

(FZ

<--1).

occur.

KEF1ll-A

and

the

stores

codes

FIUV

bit

exact

reflect

is
in

exact

MULF/MULD
Multiply

Floating/Double

171 (AC) FSRC

MR-3614

FSRC,AC

Format:

MULF

Operation:

Let

PROD

underflow

<--

exact

(AC)

Condition

Codes:

Description:

all

occurs

others

and

FIU

not

enabled,

and

FIV

1is

not

enabled,

cases,

<--

overflow

FZ
FN

<-<--

1
1

if
if

(AC)
(AC)

<--

PROD.

the

biased

(AC)

<--

=
<

occurs,

else

else
else

<-<--

0
0

0,
0,

exponent

exact

FZ
FN

For

<--

either

all

operand

other

cases

1is

PROD

is generated to 32 bits for floating mode and
bits for double mode.
The product is rounded

64
or

chopped

and

1is

stored

for
in

and

except

for:

Overflow with

Underflow with

For

these

stored
Interrupts:

(FSRC).

If overflow
<-- exact 0.
For

disabled

interrupt

exceptional

disabled.

cases,

exact

AC.

overflow

trap

parts

exponent part

underflow

corresponding
interrupt
occurs
with
the
faulty

fractional

respectively,

interrupt

If FIUV is enabled,
before execution.
If

are

too

-0

occurs

FSRC

occurs

and

is
enabled,
the
result
1in
AC.

correctly

small

400,

stored.
for

the

trap
The

The

overflow.

It is too large by 400, for uné%rflow, except
for the special case of 6, which is correct.

Accuracy:

Errors

due

overflow

and

described

underflow

are

above.
If neither
occurs,
the error
incurred
is bounded by
1 LSB
in chopping mode
and 1/2 LSB in rounding mode.

Special

Comment:

The
wundefined
variable
-0
conjunction with overflow or

be
stored
in
AC
only
interrupt is enabled.

can

occur

only

underflow.
It will
the
corresponding

DIVF/DIVD

Divide Floating/Double

174 (AC+4)FSRC

MR-3615

Format:

DIVF

Operation:

FSRC,AC

the

and

(AC)

<--

exact

For all other cases,

let QUOT =

(AC)/(FSRC).

If underflow
<-- exact 0.

occurs

and

FIU

not

enabled,

overflow

occurs

and

FIV

not

enabled,

<--

exact

For

all

<--

QUOT.

others

<--

FZ <-— 1 if
FN <-- 1 if

cases,

overflow

(AC)
(AC)

occurs,

else

<--

= 0, else FZ <-- 0
< 0, else FN <-- 0

If either operand has a biased exponent of 0,

For FSRC this would
is treated as an exact O.
the
<case
this
in
0;
by
division
imply
instruction is aborted, the FEC register 1is set

and

interrupt

the

Otherwise

occurs.

double
or
single
to
1is developed
guotient
correct
for
two guard bits
precision with
The quotient is rounded or chopped in
rounding.

accordance with the values of the FD and FT bits
The result is stored in
in the FPS register.
the AC

except

for:

interrupt disabled

Overflow with

Underflow with interrupt disabled.

For

these

stored

exceptional

in AC.

{

Description:

(AC)

{==-

aborted.

[Xe)

Condition Codes:

EXP(AC)

(AC)

EXP(FSRC)

instruction

cases,

exact

Interrupts:

If FIUV 1is enabled,
before execution.
If
(FSRC)
divide by

=
0.

trap

interrupt

-0

traps

FSRC

occurs

attempt

If
overflow
or
underflow
occurs
and
1if
the
corresponding
interrupt
1is
enabled,
the
trap
occurs
with
the
faulty
result
in
AC.
The
fractional
parts
are
<correctly
stored.
The
exponent part is too small by 400,
for overflow.

It is too large by 400, for uné%rflow, except
for the special case of 8, which is correct.

Accuracy:

Errors

due

overflow

and

underflow

are

described above.
If none of these occurs,
the
error
in the quotient will be bounded by 1 LSB
in
chopping
mode
and
by
1/2
LSB
in
rounding
mode.
Special

Comment:

The

undefined

variable

conjunction with

-0

overflow or

be
stored
in
AC
only
interrupt is enabled.

can

occur

underflow.
the

only

It will

corresponding

CMPF/CMPD
Compare

Floating/Double

173 (AC+4)FSRC

MR-3616

Format:

CMPF

Operation:

(FSRC)

Condition

Codes:

Description:

FSRC,AC

=--

(AC)

<--

(FSRC)

<--

(FSRC)

Compare

the

accumulator.

condition
left

If
FIUV
1is
execution.

Accuracy:

These

Special

Comment:

the

codes.

Interrupts:

enabled,

operand

trap

are
a

operands

AC.

with

the

floating

point

accumulator

are

below.

-0

occurs

before

exact.

has

both

0
0

FSRC

the

noted

were

exact

and

which

where

<-<--

FZ
FN

appropriate

FSRC

except

instructions

treated

else
else

contents
Set

unchanged

0,
0,

are

biased

exact

the

exponent

FPP

will

this

case

store

MODF /MODD
Multiply
and

and

Separate

Fraction

1
1

Integer

Floating/Double

171 (AC+4) FSRC

FSRC

Format:

MODF

Description

This
instruction generates
the product of
its
two
floating
point
operands,
separates
the
product
into
integer
and
fractional
parts
and
then stores one or both parts as floating point

and

Operation:

FSRC ,AC

numbers.

Let

PROD

Floating

(AC)

point:

(FSRC)

ABS (PROD)

that
(2

with

where

1/2

.LE.

EXP (PROD)
Fixed

point

.LT.

(200

binary:

INT (PROD)

and
K)

octal

PROD

the

integer

g = PROD - INT(PROD) = the
PROD with 0 .LE. F .LT. 1.
Both
are

and

returned

have

the

follows:
even-numbered

stored

AC.

not

stored

two

AC+l1]

statements

stored

above

part

PROD.

They

accumulator

and

accumulator,

1is

combined

returned

odd-numbered

and

PROD and

fractional

sign

2),

The

same

part of

3),

in AC.

can

follows:

AC,

Five

returned

where

v means

special

cases

ACvl

and

OR.

occur,

indicated

the

following
floating
1.

formal
mode

PROD

{--

that

-0

get

not
0,

FIV

bits,

small
ACvl.

-0

.LE.

ACvl

<--

chopped

ACvl

will

EXP

exact

<--

never

ABS(PROD)

for

enabled,

mode.

<--

too

and

exact

bit

with
double

stored

<--

The
sign
low-order

for

and
L

EXP(N)

can

FIV

overflows

chopped

Note

description

and

4008

exact

and

are

information,

such

and

stored.

bits,

ACvl

overflow,

<--

exact

correct,
but
parity,
is

lost.
If

<--

The

.LE.

ABS(PROD)

.LT.

ACvl

integer

part

exact.

The

return
L

LSB

of
=

+/-unity

24,

mode.

increases
increases

p>7,

the

For

from
above

.LE.

the

fractional

1is

and

56,

the
above
8
because

generated.

low

ABS(N)

order

rounded
cause a

mode

are

the

for

error

chopping

rounding

PROD

fractional

part g is normalized, and chopped or
in accordance with FT.
Rounding may
For

<--

1/2

the

by 1
LSB
1in

error

1limits
as
ABS(N)
only
64
bits
of

.LT.

p-7

part.

bounded

bits

(p+l),

may

with

error.

ABS(PR)D)

<--

exact

.LT.

and

error

There

error

the

LSB

and
g.

the

fractional

chopping

<--

mode

and

underflow,

integer

part

1/2

LSB

bounded

mode.
+/-unity

Rounding
may
cause
a
for the fractional part.

underflows

<{(--

PROD

exact

and

and
<--

FIU

part.
in

ACvl

The

rounding

return

enabled,

ACvl

Errors are as in case 4, except that EXP (AC)
will be too large by 400g (if EXP = 0, it is
correct).
Interrupt will occur and -0 can be
stored

AC.

If
AC

FIU is not enabled,
<-- exact 0.

For
this
case
the
part is less than 2
Condition

Codes:

Interrupts:

ACvl

<--

error
in
the
** (-128).

<-=-

<-—

PROD

overflows,

<=-

(AC)

else

<--

(AC)

else

<--

trap

-0

If FIUV
1is enabled,
before execution.

Overflow

and

Accuracy:

Discussed

Applications:

underflow

else

are

FSRC

discussed

and

fractional

<--

occurs

above.

Binary

fraction.
MOD, will

decimal

<conversion

The
following
generate decimal

I <-- 0;
X <-- number
ABS (X) < 1;
While X <> 0 do
Begin PROD <-- X * 10;
I <-—- 1 + 1;

proper

algorithm,
using
digits D(1), D(2)

right.

left

from

...

exact

Initialize:

D(I)

<=-

converted;

INT(PROD);

PROD

<--

INT (PROD) ;

End;

This

algorithm

description

nonvanishing
chopping

nor

reduce

exact.

the

because

bits

never

PROD

case

fractional

hence

exceeds

and

rounding

can

introduce

the

argument

the

part

number

neither

error.

trigonometric

function.

ARG * 2/PI = N + g.
The low two bits of N
identify the quadrant, and g is the argument
reduced to the first quadrant.
The accuracy

of N+g
factor

limited

2/PI.

argument

The

thus

bits

accuracy

depends on

the

because

reduced

size

the

of N.

To evaluate the exponential function e ** x,
obtain x * (log e base 2) = N + g,
then e ** x = (2 ** N) * (e ** (g * 1ln 2)).

The

reduced

argument

1n2

and

the

factor

exact

may

scaled

the

EXP

and

LDEXP.

limited
e
base

to L
2).

argument

thus

The

power

end

via

which

STEXP,

accuracy

ADD
N+g

N
is

bits because of the factor
(log
The
accuracy
of
the
reduced
depends

the

size

LDCDF/LDCFD

Load and Convert from Double to Floating
and from Floating to Double

177 (AC+4) FSRC

MR-3618

FSRC ,AC

Format:

LDCDF

Operation:

EXP(FSRC)

I1If

overflow,

<--

<—--

exact

Condition

Codes:

Description:

<--

FZ
FN

FV <-- 0
<-- 1 if
<-- 1 if

the

y=F
y =D

rounding

and

floating

=
=

(single)
(double)

if FD
if FD

=
<

current

0,
O,

0
1

else
else

mode

FZ
FN

<-<--

0),

single precision.

(FT)

is set,

and

chopped,

is converted

otherwise

the

number

Interrupts:

1is
and

lower

half

(FD

precision

the number

rounded.

If the current mode is double mode

source
number

else

double

the floating chop bit

number

LDCDF
LDCFD

mode

floating

Cxy

0
0

source

mode

overflow,

assumed

the

where

<-- Cxy(FSRC),
from

conversion produces
(AC)
(AC)

causes

cases,

specifies
conversion
floating mode vy.

x =D,
y =F,

exact

FIV

other

all

(FD = 1),

the

assumed
to
be
a
single
precision
The
is loaded left-justified in AC.

cleared.

trap on -0 occurs before
If FIUV is enabled,
execution.
However,
the condition codes will
reflect a fetch of -0 regardless of the FIUV
bit.

Overflow cannot

occur

for

LDCFD.

A trap occurs if FIV is enabled, and if rounding
with

LDCDF

result.

causes

This

overflow.

result must be +0

<--

-0.

overflowed

Underflow
Accuracy:

LDCFD

1is

overflow,

bounded

cannot
an

occur.

exact

described

by 1 LSB in
rounding mode.

instruction.

above,

LDCDF

chopping

mode

Except

incurs

and

for

error

1/2

LSB

STCFD/STCDF
Store and Convert from Floating
and from Double to Floating

Double
176 (AC) FDST

FDST

]
MR-3619

Format:

STCFD

AC,FDST

Operation:

(AC)

overflow,

(FDST)
FT

all

Cxy

specifies

other

Condition Codes:

Description:

=F,

<--

=
=

rounding

causes

<--

Cxy(AC),

where

from

0
1

conversion

<--

(AC)

<--

(AC)

the

=
<

current

the

floating

(single)
(double)

mode

STCFD

STCDF

state

-0

Overflow

cannot
cannot

and

not

FSRC

<-<--

0
0
precision,

double

1is

and

precision,

the

are

the

FDST

converted

rounded

stored

occur

even

else

depending

FDST.

1if

FIUV

1is

accumulator.

occur.
occur

trap occurs if FIV
with
STCDF
causes
overflowed

result.

STCFD

1is

overflow,

single

chopped

FT,

will

because

Underflow

FZ
FN

accumulator

1is

mode

the

precision,

enabled

else
else

mode

single
the

0,
O,

produces

stored left-justified
is cleared.

current

contents

Accuracy:

and

Trap

(FDST)

FD
FD

accumulator is
the lower half

Interrupts:

exact

vy.

FIV

<--

cases,

y=D
y=F

=D,

exact

conversion

floating mode
x
Xx

(FDST)

<--

exact

for

STCFD.

enabled,
overflow.

This

must

instruction.

and

if rounding
(FDST)
{—--

-0.

Except

for

overflow,
bounded

described

rounding

LSB

mode.

above,

STCDF

chopping

mode

incurs
and

error

1/2

LSB

LDCIF/LDCID/LDCLF/LDCLD
Load

and Convert Integer or Long
Floating or Double Precision

15
1

1
L

1
1

Integer

177 (AC) SRC

08
1

SRC

Format:

LDCIF

SRC,AC

Operation:

AC <-- Cjx(SRC), where Cjx specifies conversion
from integer mode j to floating mode vy.

I
F

Condition

Codes:

Description:

if
if

FC
FV

<-<--

0
0

FZ
FN

<-<--

1
1

FL
FD

if
if

0,
0,

(AC)
(Ac)

=
<

0,
0,

else
else

Conversion

1is

from

complement

floating

2's

performed
point

FZ
FN

the

integer

number

that
mode

j and x are determined
bits FL and FD.

32-bit

integer

has

addressing

(SRC)

addressing

mode

<-<--

1is

0
0

contents

with

precision

SRC

precision

the

state

Note

the

and

specified

mode)

mode

immediate

specified,

the

bits

the

source
register
are
left-justified
and
the
remaining
16
bits
loaded
with
O0s
before
conversion.

the

case

LDCLF,

floating

point

rounded

the

fractional

representation

bits

for

not

floating

1is

part

the

chopped

point,

trap

and

-0

respectively.
Interrupts:

Accuracy:

None;

SRC

cannot

occur.

LDCIF,

LDCID,

and

LDCLD

are

exact

The error incurred by LDCLF is
in
chopping
mode
and
by
1/2
mode.

instructions.

bounded
LSB
in

by 1 LSB
rounding

STCFI/STCFL/STCDI/STCDL
Store and Convert from Floating
to Integer or Long Integer

15
1

1
1

Format:

Operation:

(DST)

else

Description:

<--

Cxj(AC)

(DST)

<--

I
F

if
if

the

floating

AC,DST

2
2

STCFI

from

Condition Codes:

Double

175 (AC+4)DST

JL.

mode

FL
FD

-JL-1

0, [

integer.
FL
FL

<--

<--1

<--

for

-JL-1

(DST)

Cxj(AC)

mode

7j.

FL
FD

Cxj(AC)

JL+1,

else

(DST)

else

else N,

<--

Conversion is performed from a floating point
representation of the data in the accumulator to
an

integer

representation.

I1f the conversion is to a
and
an
addressing
mode

32-bit word (L mode)
of
0
or
1immediate

If the operation
1is out of
selected by FL, FC is set to

the

DST

Numbers

(rather

are

than

is
true
even
cleared in the
These

set

the
1integer
range
1 and the contents

converted

rounded)

are

because

the

not

-0,

always

mode

interrupt

chopped

This

conversion.

before

when
the
chop
FPS register.

instructions

enabled,

most
the

the
in

only
specified,
1is
mode
addressing
significant
16
bits
are
stored
destination register.

Interrupts:

JL+1,

specifies conversion

integer

largest

where Cjx

present,

bit

1if

FIUV

1is

AC,

not

FIC

will
Accuracy:

memory.

enabled,

trap

conversion

failure

occur.

These

instructions store the integer part of the
floating
point
operand,
which may
not
be
the
integer most closely approximating the operand.
They are exact if the integer part is within the
range

implied

FL.

LDEXP

Load

176 (AC+4)
SRC

Exponent

MR.3622

SRC,AR

Format:

LDEXP

Operation:

Note:
177
numbers.

and

200,

appearing

If -200 < SRC < 200, EXP(AC)
the rest of AC is unchanged.

If (SRC)
[ (SRC) +

> 177 and
200]1<7:0>.

(SRC)

177

FIV

and

FIV

is
»

below,

<--

are

SRC

enabled,

disabled,

octal

200

and

EXP(AC)

<--

exact

If <SRC)
[(SRC) +
If

< =177 and
200])<7:0>.

(SRC)
O.

=177

FIU

and

enabled,

FIU

EXP(AC)

disabled,

<--

exact

Condition

Codes:

FC
FV

FZ
FN
Description:

0
1
1
1

<--

<-<-<--

if
if
if

Change AC

(SRC) > 177, else
(AC) = 0, else FZ
(AC) < 0, else FN

so that

its unbiased exponent =
(SRC)

1is,

only

if ABS(SRC)

excess 200 notation
field of AC.
This

SRC

177,

Interrupts:

abnormal

FP11A

and

trap

the

Note

these

FPl11B

but

from

2's

(SRC).

complement

and insert it in the EXP
1s a meaningful operation

177.

result

the

=177,

underflow.

and

convert

That

FV <-<-- 0
<-- 0

that

the

conditions

it does

treated

1is

result

KEF1ll-A does

the

treat

same

them

the

overflow.

treated

not

the

same

treat

FPI11C
as

the

FIUV

trap

FPllE.

-0

occurs,

even

1if

enabled.
If

SRC

177

and

FIV

1is

enabled,

occur.

overflow will

If
SRC
<
=177
and
underflow will occur.
Accuracy:

Errors

due

FIU

overflow

described

above.

-200,

changes

from

treated

1is

and

EXP(AC)
a

all

enabled,

trap

underflow

floating

and

(SRC)

point

are

number

arithmetic

operations to a non-0 number.
This is because
the
insertion
of
the
"hidden"
bit
1in
the
microcode
implementation
of
arithmetic

instructions
value
For

all

other

cases,

the transformation
** Ky
* f into
(2
ABS (f)

triggered

nonvanishing

EXP.

.LT.

of
**

LDEXP

implements

exactly

a floating point number (2
(SRC))
* f where 1/2 .LE.

STEXP
Store

Exponent

175 (AC)DST

1
i

1
Il

Operation:

(DST)

<--

EXP (AC)

Description:

AC,DST

—2008

<--

(DST)

else

<--

(DST)

else

<--

Convert

2's

This

AC's

This

exponent

complement

instruction

Overflow
Accuracy:

to
Interrupts:

DST

STEXP

Codes:

Format:

Condition

and

and
will

underflow

instruction

from

store
not

excess

the

trap

cannot

always

200

result
on

-0.

occur.

exact.

notation

DST.

CLRF/CLRD
Clear

Floating/Double

1
l

1704

0
|

Format:

CLRF

FDST

Operation:

(FDST)

<-0

Condition

Codes:

Description:

Interrupts:

<--

exact

interrupts

These

and

Set FDST to 0.
other condition

Overflow
Accuracy:

1
1

FDST

Set

code

bits.

will

code

occur.

underflow

instructions

condition

are

cannot

exact.

occur.

and

clear

ABSF/ABSD
Make

Floa ting/Double

Absolute

15
1

1
i

1
J

Format:

ABSF

Operation:

Codes:

Description:
Interrupts:

FDST

If EXP(FDST)

For
Condition

1706

(FDST)

all

other

FC
FV

<--

(FDST)

<--

(FDST)

cases,

the

FIUV

1is

Overflow

and

<--

(FDST)

exact
<--

(FDST).

else

FzZ

<--

its

absolute value.

enabled,

trap

-0

underflow

cannot

are

exact.

(FDST)

contents of FDST

Set

- (FDST).

occurs

after

execution.

Accuracy:

Special

Comment:

These

instructions

occur.

If a -0 is present in memory and the FIUV bit is
enabled, then an exact 0 is stored 1in memory.

The
l)o

condition

codes

reflect

exact

(FZ

<--

TSTF/TSTD

1705 FDST

Test Floating/Double

FDST

0
|

]

L
MR-3626

Format:

TSTF

Operation:

(FDST)

Condition

Codes:

FDST

<--

0
0

FZ
FN

<-<--

1
1

if
if

Description:

Set the
contents

Interrupts:

If
FIUV
1is
execution.
Overflow

Accuracy:

These

(FDST)
(FDST)

=
<

0,
0,

FPP condition
of FDST.

and

set,

are

FZ
FN

codes

trap

underflow

instructions

else
else

cannot

exact.

<-<--

0
0.

according

-0

occurs

occur.

the

after

SETF

Set

Floating

Mode

1
1

170001

]

0
]

0
i

0
|

0
1

0
|

0
i

0
1

1
1
MR-3627

Format:

SETF

Operation:

Description:

Set

<-the

0
FPP

single

precision

mode.

SETD

170011

Set Floating Double Mode

1
L

Format:

SETD

Operation:

Description:

Set

<--

the

FPP

in double

0
1

precision mode.

SETI
Sett

Integer

Mode

177002

15
1

1
d

1
1

00
0

Format:

SETI

Operation:

Description:

Set

<-the

0
1

0
|

0
1

0
i

1
1

0
FPP

for

Short

Integer

Data.

0
L

SETL

177012

Set Long Interger Mode
15

1
1

Format:

SETL

Operation:

<--1

Description:

Set

the

FPP

for

long

9-45

integer

data.

0
1

LDFPS

Load

FPP's

Program

Status

1701

SRC

MR-3631

Format:

LDFPS

SRC

Operation:

FPS

(SRC)

Description:

Load

FPP's

Special

The

user

1is

and

his

not

recoverable

cautioned

own

for

status

\Ye)

Comment:

<--

from

not

purposes,
the

STFPS

SRC.

use

since

bits

13,

12,

these

bits

are

instruction.

STFPS

Store

FPP's

Program

Status

1702

0
|

1
1

0
I

DST

DST
1

L
MR-3632

Format:

STFPS

Operation:

(DST)

<--

Description:

Store

FPP's

Special

Bits
bits

Comment:

DST

13,
are

FPS

12,
the

status

DST.

and 4 are loaded with
corresponding bits in

0.
the

All other
FPS.

STST

Store

FPP'g

1703

0
.

0
L

0
)

1
J

DST

]

J
MR-3633

Format:

STST

Operation:

(DST)

<--

FEC

<--

FEA

Store

the

FEC

and

the

destination

(DST

Description:

DST

FEA

DST

and

DST+2.

NOTES

mode
specifies
immediate
addressing,

general
only
the

2. The information in these registers is current
only
1f
the
most
recently
executed
floating
point
instruction
caused
a
floating
point

exception.

CFCC

Copy Floating Condition Codes

170000

00
0

MR-3634

Format:

Operation:

Description:

CFCC

<--

<——-

F2Z

<--

Copy

the
condition

FPP
condition
codes.

into

the

CPU's

CHAPTER 10
PROGRAMMING TECHNIQUES

10.1

The

INTRODUCTION

KDF11-AA

offers

great

deal

programming

flexibility

and

Utilizing the combination of the instruction set, the
power .
addressing modes, and the programming techniques makes it possible
to develop new software or to utilize old programs effectively.

The programming techniques in this chapter show the capabilities
of
the
KDF11-AA.
The
techniques
discussed
are:
postition-independent
coding
(PIC),
stacks,
subroutines,
interrupts,
reentrancy,
coroutines,
recursion,
processor
traps,
programming

10.2

peripherals,

and

POSITION-INDEPENDENT

conversion.

CODE

The output of a MACRO-11 assembly is a relocatable object module.
The task builder or linker binds one or more modules together to

Once built, a task can only be
create an executable task image.
loaded and executed at the virtual address specified at link time.
This is because the linker has had to modify some instructions to
reflect the memory locations in which the program is to run.
Such
a

body

code

the virtual

considered

addresses

position-dependent

to which

it was

(i.e.,

bound).

dependent

The
KDF11-AA
processor
offers
addressing
modes
that
make
it
possible to write instructions that are not dependent on the
virtual addresses to which they are bound.
This type of code is
termed position-independent and can be loaded and executed at any
Position-independent code can improve system
virtual address.

efficiency,

conservation

both

virtual

use

physical

address

and

space

memory.

In multiprogramming systems like RSX-11M,
it is important that
many tasks be able to share a single physical copy of common code;
for

example,

task

using

library

routine.

make

the

optimum

use

task's virtual address space,
shared code should be positionindependent.
Code that 1is not position-independent can also be
shared, but it must appear in the same virtual locations in every
task

it.

builder

This

restricts

and

can

result

Addressing

the

placement

the

loss

the

such

the

Construction

virtual

code

addressing

space.

10.2.1

Use

Modes

Position-Independent Code

The construction of position-independent code is closely linked to
the
proper
use
of
addressing modes.
The
remainder
of
this
explanation assumes the reader is familiar with the addressing
modes

described

Chapter

10-1

All

addressing

modes

position-independent.

involving

only

These

are

modes

mode

(R)

deferred

(R)+

autoincrement

@*R) +
- (R)

autoincrement

deferred

autodecrement

mode

@- (R)

autodecrement

deferred mode

references

are

follows.

mode

When

employing
these
addressing
modes,
the
user
1is
guaranteed
position
independence,
providing
the
contents
of
the
registers
have
been
supplied
independent
of
a
particular
virtual
memory
location.

The
relative
addressing
modes
are
position-independent
when
a
relocatable address is referenced from a relocatable instruction.
These

modes

are

follows.

relative

mode

relative

deferred

Relative

modes

are

not

mode

position-independent

when

absolute

address
(that is a nonrelocatable address)
is referenced from a
relocatable instruction.
In this case, absolute addressing (i.e.,

@#A)

may be

Index

modes

dependent,
as

can

to make

according

either
to

their

the

reference

position

independent.

position-independent
use

the

program.

value

(e.g.,

These

positionmodes

are

follows.

X (R)

index

mode

@X (R)

index

deferred

the

base,

offset),
an

employed

the

mode

absolute

reference

position-independent.

control

The

block

following

reference

1is

example.

MOV

2(SpP),R0O

; POSITION-INDEPENDENT

MOV

N(SP) ,R0

; POSITION-INDEPENDENT

N=4

If,
however,
X
1is
a
relocatable
position-dependent, as the following
CLR

Immediate

according
follows.
#N

ADDR (R1)

mode

its

can

address,
the
example shows.

; POSITION-DEPENDENT

use.

immediate

either

Immediate

position-independent

mode

10-2

references

are

not,

formatted

When an absolute expression defines the value of N,
the code 1is
position-independent.
When a relocatable expression defines N,
the
code
1is
position-dependent.
That
1is,
immediate
mode
references are position-independent only when N
is an absolute
value.

Absolute

cases

mode

where

Absolute

mode

@#A

example

addressing

instruction,
MOV

the
as

absolute

position-independent

virtual

1location

references

only

being

1in

those

referenced.

are

formatted

position-independent

absolute

reference

absolute

reference

10.2.2

addressing

follows.

mode

processor
this

status

word

(PS)

from

relocatable

example.

@#PSW,RO

;sRETRIEVE

STATUS

AND

PLACE

Position-Dependent/Position-Independent

Comparative

Example

The
RSX-11
subroutine.

1library
routine,
to
establish
or

PWRUP,
remove

1is
a

asynchronous

system

entry

point

trap

(AST)

a
FORTRAN-callable
user
power
failure
address.

Imbedded

within the routine is the actual AST entry point which saves all
registers,
effects
a
call
to
the
user-specified
entry
point,
restores
all
registers
on
return,
and
executes
an
AST
exit
directive.
The following examples are excerpts from this routine.
The
first
example
has
been
modified
to
illustrate
position-dependent
references.
The
second
example
1is
the
position-independent version.
Position-Dependent

Code

PWRUP:
:

CLR
CALL

- (SP)

;sASSUME

.X.PAA

; PUSH

SUCCESS
(SAVE)

;sARGUMENT

.WORD
MOV

1l.,$PSW
SOTSV,R4

;sONTO

STACK

:SET

R1=R2SP

:GET

OTS

;sCLEAR PSW, AND
;AREA

MOV

(SP) +,R2

+:GET

CLR

108

IMPURE

POINTER

AST

; POINT

BNE

ADDRESSES

ENTRY

ADDRESS

+IF NONE

SPECIFIED,

;SPECIFY

POWER

- (SP)

s RECOVERY AST

208

;

MOV

R2,F.PF (R4)

;SET

MOV

#BA,- (SP)

: PUSH

10S:

SERVICE

;
AST

AST

: ADDRESS

10-3

ENTRY

POINT

SERVICE

20S$:

;
CALL
.BYTE

BA:

. X.EXT
109.,2.

MOV

; ISSUE
;

RO,-(SP)

; PUSH

R1,-(SP)

MOV
MOV

R2,-(SP)

DIRECTIVE,

(SAVE)

EXIT.

; PUSH

(SAVE)

; PUSH

(SAVE)

Position-Independent Code
PWRUP:
:

CLR

CALL

.X.PAA

(SP)

;ASSUME

; PUSH

SUCCESS

ARGUMENT

; ADDRESSES

ONTO

; STACK

.WORD

l.,SPSW

MOV

;CLEAR PSW,

@#50TSV,R4

R1=R2-SP.

;GET

OTS

;AREA

MOV

(SP)+,R2

;GET

108

IMPURE

POINTER

AST

; POINT

BNE

AND

;SET

ENTRY

ADDRESS

;IF NONE

SPECIFIED,

;SPECIFY

POWER

CLR
BR

-(5P)
208

; RECOVERY AST

MOV

R2,F.PF (R4)

;SET

MOV
ADD

PC,-(SP)
#BA-., (SP)

; PUSH CURRENT LOCATION
;COMPUTE ACTUAL LOCATION

10S$:

SERVICE

; OF

AST

ENTRY

POINT

AST

20S:
CALL

. X.EXT
109.,2.

.BYTE

SERVICE

;

SAVE

2)
3)

EFFECT A CALL TO SPECIFIED
RESTORE REGISTERS

ISSUE

EXIT.

ROUTINE:

~eo ~o

AST

DIRECTIVE,

L0 ~e ~eo

;ACTUAL

; ISSUE

REGISTERS

AST

EXIT

SUBROUTINE

DIRECTIVE

MOV

RO,-(SP)

; PUSH

(SAVE)

MOV

R1,-(SP)

; PUSH

(SAVE)

RI1

MOV

R2,-(SP)

; PUSH

(SAVE)

The position-dependent version of the subroutine contains a
relative
reference
to an absolute symbol
(SOTSV)
and
a
literal
reference to a relocatable symbol (BA).
Both references are bound
by the task builder
to fixed memory locations.
Therefore,
the
routine will not execute properly as part of a resident library if
its location in wirtual
specified at 1link time.

memory

10-4

not

the

same

the

1location

the

position-independent

version,

the

reference

S$OTSV

has

been changed to an absolute reference.
1In addition, the necessary
code has been added to compute the virtual location of BA based
upon the value of the program counter.
In this case, the value 1is
obtained by adding the value of the program counter to the fixed
displacement
between
the
current
location
and
the
specified
symbol.
Thus, execution of the modified routine is not affected
by its location in the image's virtual address space.

10.3
The

STACKS
stack
is

part

KDF11-AA.
It is
by the operating

the

an area of
system for

basic

design

architecture

the

memory set aside by the programmer
temporary storage and linkage.
It

or
is

handled
on
a
LIFO
(last-in/first-out)
basis,
where
items
are
retrieved in the reverse of the order in which they were stored.
A stack starts at the highest location reserved for it and expands
linearly downward to a lower address as
items
are added
to
the
stack.
It
is not necessary to keep track of
the actual
1locations
into
which data is being stacked.
This is done automatically through a
stack pointer.
To keep track of the last item added to the stack,
a general register is used to store the memory address of the last
item in the stack.
Any register except register 7 (the PC) may be
used
as
a
stack
pointer
under
program
control;
however,
instructions
associated
with
subroutine
1linkage
and
interrupt

service
For

automatically

this

reason,

Stacks may

use
1is

be maintained

frequently

hardware

referred

either

full

word

stack
the

byte

pointer.

system

units.

SP.

This

is true for a stack pointed to by any register except R6, which
must be organized 1in full word units only.
Byte stacks
(Figure
10-1)
require
instructions capable of operating on bytes
rather
than full words.

10.3.1
Pushing Onto a Stack
Items
are
added
to
a
stack
using
the
autodecrement
addressing
mode.
Adding
items
to
the
stack
1is
called
PUSHing,
and
1is
accomplished by the following instructions.
MOV

Source,-(SP)

+MOV

contents

;onto

the

source

word

stack

MOVB

Data

Source, - (SP)

thus

PUSHed

;MOVB

onto

source

;the

stack

the

stack.

10.3.2
Popping From a Stack
Removing data from the stack

stack) .

This

operation

byte

called

accomplished

mode.

10-5

onto

POP

using

(popping

the

from

the

autoincrement

MOV

(SP)+,Destination

:MOV

destination

;off

the

word

stack

MOVB

(SP)+,Destination

;MOVB
;off

destination
the

byte

stack

After
an
item has
free and available

been popped,
its stack location
for other use.
The stack pointer

last-used

implying
represent

Thus,

location,

stack

locations.

may

(See

Figure

that the next lower
a pool of sharable

is considered
points to the
location is free.
temporary storage

10-2.)

WORD STACK

007100

ITEM #1

007076

ITEM
# 2

007074

ITEM
# 3

007072

ITEM#4

<« spP

007072

<« sp

007075

007070

007066
007064

BYTE STACK

007100

ITEM#1

007077

ITEM
# 2

007076

ITEM#3

007075

ITEM#
4

NOTE:
BYTES ARE

ARRANGED
IN
WORDS
AS FOLLOWING:

BYTE
3

BYTE
2

1
BYTE

BYTE
O
J

WORD
N R-3662

Figure

10-1

Word

and

10.3.3
Deleting Items From a Stack
following techniques may be used

The
To

delete

one

INC

delete

two

ADD#2,SP

item

use

the

TSTB(SP)+

items
or

use

TST(SP)+

Byte

following.

for

the

following.

for

byte

word

stack

10-6

Stacks

delete

from

stack.

delete

fifty

items

from

word

stack

use

the

following.

ADD#100.,SP

HIGH MEMORY
«— SP

sTack ¥

«—5p
v

AREA
LOW MEMORY

1 AN EMPTY STACK AREA

2 PUSHING A DATUM

EO
E1

<SP

3 PUSHING ANOTHER

ONTO THE STACK

DATUM ONTO THE

STACKS

v
4

A E2

<SP

-—sp

ANOTHER PUSH

5 POP

<SP

6 PUSH

E3
EO
E1

<SP

POP
MR-3663

10.3.4
Stacks

Figure

10-2

Stack

Uses

are

used

the

following

Often

one

the

subroutine

returned
store

Illustration

The
a

the

stack

its

1is

and

purpose

interrupt

original

used

Push

Pop

Operations

ways.

general

contents

subroutine

value.

the

registers

service
The

registers

storing
1its

stack

can

used

and

then

used

involved.

linkage

«calling

must

routine

information

program.

between

The

JSR

instruction,
used
in calling a subroutine,
requires the
specification of a linkage register along with the entry
address

the

and

return

the

linkage
calling

subroutine.

stored

the

address

The

content

stack,
1is

moved

as
from

this

not

the

linkage

lost,

the

transmitted

easily

the

subroutine.

10-7

When

the

subroutine

stack

returns,

eliminating

Returns

from

necessary

skipping

over

the

"clean

up"

subroutine

arguments.
One way this can be done is by insisting that
the subroutine keep the number of arguments as its first
stack

item.

calculating

pointer,

original
copy

Stack

the

resetting

contents

the

stack

storage

program

,the

the

stack

then

reset

pointer,

then

The

word

the

nesting

the

are

pushed

storing

method

kind

and

interrupt

processor

stack

inputs,

data.

1is

wants

use

status

the

stack.

being

available

may

intermediate

10.3.5
Stack Use Examples
As an example of stack use,
(SUBR)

also

consider

registers

and

used,

for

used

results,

this

but

using

the

can

temporary

LIFO

occur

storage

list

these

subroutine

registers must be

contents

unchanged.

Stack:
Assembler

Address

Octal

076322
076324

010167
000074

076326

076330

Syntax

Comments

MOV
*

R1,TEMP1

;save

010267

MOV

R2,TEMP2

;save

000072

076410

016701

MOV TEMP1,R1

076412

000006

076414

0167902

MOV TEMP2,R2

076416

000004

076420
076422

000297
000000

RTS PC
TEMP1:0

076424

0000060

TEMP2:0

*Tndex

Code

SUBR:

constants

10-8

for

etc.

situation:

returned
to
the calling
program with
their
The subroutine could be written as follows.
Not

the

linkage.

and

stack

any

stack

storing

subroutines, interrupts, and traps to any level
until the stack overflows its legal limits.

The

1involve

the

trap

used

system

the

which

pointer.

program

subroutines

counter

executing

When

amount

;restore

;jrestore

Using

R3 has

Stack:

the

been

previously

set

Octal

Code

point

the

end

unused

block

memory.

Assembler

Address
010020

010143

MOV

R1l,-(R3)

;push R2

012302
012301

MOV
MOV

(R3)+,R2
(R3)+,R1

;pop R2
;pop R1

000207

RTS

010243

010130
010132
010134

SUBR:

Comments

MOV R2,-(R3)

010022

Note:

Syntax

this case R3 was used

;push

stack pointer.

The second routine uses four fewer words of instruction code
two words of temporary "stack" storage.
Another routine could

and
use

the same stack space at some later point.
Thus, the ability to
share temporary storage in the form of a stack is a way to save on

memory

use.

As another example of stack use, consider the task of managing an
As characters come in, the user may
input buffer from a terminal.
wish to delete characters from the line; this is accomplished very
easily by maintaing a byte stack containing the input characters.
Whenever a backspace is received, a character is "popped" off the

eliminated

stack

and

Note

that

the

unwanted

from

this

consideration.

"popping" characters to be eliminated can be done by
the MOVB (MOVE BYTE) or INC (INCREMENT) instructions.

preferable

this

1increment

either

instruction

(INC)

readjusting

the

1is

since

it accomplishes the task of eliminating

the

need

for

character

from

(SP)

without

pointer

(R6)

10.3.6

Subroutine

stack pointer
Figure

the

using

to MOVB,

pointer
(See

case

example,

used

the

stack

destination

location.

this example cannot be

because R6 may point only to word

the

stack

Also,

the

system stack

(even)

locations.

10-3.)

Linkage

The contents of the linkage register are saved on the system stack
when a JSR 1is executed.
The effect 1is the same as if a MOV
reg,-(R6) had been performed.
Following the JSR instruction, the

same register is loaded with the memory address (the contents of
the current PC),
and
a
jump
is made
to
the
entry
1location
specified.

Figure
the

10-4

gives

subroutine

the

before

and

after

instructions JSR R5,

10-9

conditions

1064.

when

executing

001011

001010

001007

001006

001005

001004

001003

001002

001001

INC

R
<R3 |

001001

<«R3[

001002

|
MR-3664

Figure

10-3

Byte

Stack

Used

Character

BEFORE

AFTER

(R5) = 000132

(R5) = 001004

(R6) = 001776

(R6) = 001774

(PC) = (R7) = 001000

{PC) = (R7) = 001064

002000

nnnnnn

001776

mmmmmm

002000

nnnnnn

001776

mmmmmm

001774

000132

001772

-SSP I

001776

<«sp|

Buffer

001774

MR -3665

Figure

10-4

JSR

Example

Because hardware already uses general-purpose register R6 to point
to
a
stack
for
saving
and
restoring
PC
and
PS
(processor
status

word)
and
from

and

information,

restore

subroutines.

interrupt

10.3.6.1

intermediate
Using

service

Return

convenient
results
R6

and

this

use

way

this

same

transmit

permits

stack

arguments

nesting

save

and

subroutines

routines.

from

Subroutine

for a return from the subroutine to
instruction
must
specify
the
same

RTS

instruction

the calling program.
register
as
the
one

provides
The
the

RTS
JSR

instruction
wused
1in
the
subroutine
call.
When
the
RTS
1is
the register
specified is moved to the PC,
and
the
top
of the stack to be placed in the register specified.
Thus, an RTS
executed,

has

the

stack.

10.3.6.2

the

effect

Subroutine

subroutine
1.

returning

Advantages

calling

Arguments
program

and

procedure

can
the

the

address

There

are

affected

passed

subroutine.

10-10

quickly

specified

the

top

several

advantages

the

instruction.

JSR

between

the

<calling

If
there
are
no
arguments,
or
the
arguments
are
in
a
general register or on the stack, the JSR PC,DST mode can

be used so that none
used for linkage.
3.

general-purpose

registers

are

JSRs can be executed without the need to provide any
saving procedure for
the linkage information,
since all
linkage
information
is
automatically
pushed
onto
the
stack
1in
sequential
order.
Returns
can
be
made
by
automatically popping this information from the stack in

order

linkage

opposite

address

subroutine
calls.
efficient linkages
a

the

Many

the

Such

routine

call

the

bookkeeping

JSRs.

called

automatic

"nesting"

This
feature
enables
construction
of
fast,
in a simple, flexible manner.
It also permits
itself.

10.3.7
Interrupts
An interrupt is similar to a subroutine call, except that
it
initiated
by
the
hardware
rather
than
by
the
software.
interrupt can occur after the execution of an instruction.

is
An

Interrupt-driven techniques are used to reduce CPU waiting time.
In direct program data transfer, the CPU loops to check the state
of the Done/Ready flag (bit 7)
in the peripheral interface.
Using
interrupts,
the
CPU
can
handle
other
functions
until
the
peripheral
initiates
service
by
setting
the
Done
bit
in
1its
control

status register.
The CPU completes the instruction being
executed and then acknowledges the
interrupt,
and vectors to an
interrupt service routine.
The service routine will transfer the

data

and

may

perform

service

routine

program

that

has

was

calculations
been

with

completed,

interrupted

the

it.
the

After
computer

peripheral's

the

interrupt

resumes

the

high-priority

request.

10.3.7.1

1Interrupt

routines,

linkage

Service
Routines
information is passed

With
interrupt
service
so that a return to the

main

program can be made.
More information is necessary for
an
interrupt
sequence
than
for
a
subroutine
call
because
of
the
random nature of interrupts.
The complete machine state of the
program immediately prior to the occurrence of the interrupt must
be
preserved
in
order
to
return
to
the
program
without
any
noticeable effects.
This information is stored in the processor
status

word

counter
(PC)
automatically
same as if:

had

been

(PS).

Upon

interrupt,

the

contents

(address
of
next
instruction)
pushed onto the R6 system stack.

MOV

PS,-(SP)

;Push

MOV

PC,-(SP)

; Push

executed.

10-11

the

program

and
the
PS
The effect is

are
the

The

new

contents

consecutive memory
The

first

address

the

word

(the

word

machine status,
be
used by the
vector

address

After

the

and

are

loaded

from

which

are

called

"vector

the

contains

including

interrupt

service

routine

the

new

service

interrupt)

routine

sequence),

and

determine

the

will

mode

has

performed.

preassigned

addresses."

program

which

operational

two

service

interrupt
service
routine.
are set under program control.

interrupt

from

contains

address

second

(return

the

locations

and

The

been

The

Interrupt

service

programming

CPU

device

10.3.7.2
manner

Nesting

that

arbitrary

mixture

When

the

proper

the

intimately

priority

Interrupts

subroutines

confusion.
used,

and

are

the

completed,

two

RTI

words

the

and

are
automatically
"popped"
and
placed
in
the
respectively, thus resuming the interrupted program.

concept

set

contents

top

stack

entry

involved

with

the

same

levels.

can

nested.

nested

much

possible

nest

any

subroutines
and
interrupts
without
respective
RTI
and
RTS
instructions,

any
are

returns

are

automatic.

(See

Figure

10-5.)

10.3.8
Reentrancy
Other
advantages
of
programming

the
KDF11l-AA
stack
organization
occur
in
that handle several tasks.
Multi-task program

systems

environments
range
from
simple
single-user
applications
which
a
mixture
of
I/0O
interrupt
service
and
background
data
processing,
as
in
RT-11],
to
large
complex
multi-programming

manage

systems

that

multi-user

manage

programming

situations,

using

intricate

the

flexibility

single

and time/memory economy
copy of
the
same routine

way

The

ability

keeping

among

tasks

differ

from

reentrant

can

varying

called

ordinary

routines

used

situation

track

shown

complex

program

linkages.

single

copy

subroutines

that

finish

processing

task.

Multiple

completion

Figure

may

10-6

program

Reentrant

the

the
1.
2.

The

resulting
It
It

value

using

code

has

the

generally

can

and

same

pure

kept

1in

code

following

considered

easier

read-only

protected).

- 10-12

among

users

program

not

oOr

routines

necessary

routine.

for
they
time

Thus

the

occur.

10.3.8.1
Reentrant Code - Reentrant routines
code,
(any code that consists exclusively
that

executive

a given
task
before
tasks can exist at any

pure

constants).

by allowing many tasks to use
with a simple straightforward

reentrancy.

another

stages

mixture

situations,
as
in
RSX-11.
In
all
these
stack
as a programming technique provides

must be written in
instructions and

whenever

possible

characteristics.
to

debug.

memory

(is

read-only

PROCESS 01S RUNNING: SP IS

e PO

POINTING TO LOCATION PO.

SUBROUTINE A RELEASES THE

TEMPORARY STORAGE HOLDING

PSO

TA1 AND TA2.

PCO

TEO
TE1

INTERRUPT STOPS PROCESS O WITH
PC = PCO, AND STATUS = PSO; STARTS

PROCESS 1,

SP —a

PS1
730

PCO

5P —e

PROCESS 1 USES STACK FOR TEM-

SUBROUTINE A RETURNS CONTROL

)

PSO

TO PROCESS 2WITH AN RTS R7; PC

PCO

IS RESET TO PC2.

PCO

TEO

SP ~—»

Pc2

PORARY STORAGE (TEOQ, TE1).

PC1

TEO

TE1

TE1
PS1

PROCESS1 INTERRUPTED WITH PC

SP—e

=PC1 AND STATUS = PS1; PROCESS

PSO

2 1S STARTED.

PCO

TEO

SP —

PROCESS 2 COMPLETES WITH AN

RT1 INSTRUCTIONS (DISMISSES

TE]

INTERRUPT) PC IS RESET OT PC (1)

PS1

AND STATUS IS RESET TO PS1;

PC1

PROCESS1 RESUMES'

PSO

- PCO
TEO

SP —a

PC1

PROCESS 2 1S RUNNING AND DOES

A JSR R7,A TO SUBROUTINE A WITH
PC = PC2.

TET

10.

PROCESS 1 RELEASES THE TEMPO-

PSQ

RARY STORAGE HOLDING TEO AND

PCO

TE1.

PSO
SP —

TEO
TE1

PCO

PS1

SP—s

PC1

11.

Pc2

SUBROUTINE A IS RUNNING AND

SP —

OPERATION WITH AN RT1,PC IS
RESET TO PCO, AND STATUS IS

0
6.

PROCESS 1 COMPLETES ITS

PO
0

RESET TO PSO.

USES STACK FOR TEMPORARY

PSO

STORAGE.

PCO
TEO
TE1

PS1
PC1

PC2
TA1

SP —»

TA2

0
MR-3666

Figure

10-5

Nested

Interrupt

Service

Routines

MEMORY

SUBROUTINE

Subroutines

MEMORY

PROGRAM 1
PROGRAM 2

and

PROGRAM 1 //S{JBROUTINE/A/

PROGRAM 3

PROGRAM 2

SUBROUTINE A

PROGRAM 3 V/S/UBROU/TINE A
KDF11-AA APPROACH

CONVENTIONAL APPROACH

PROGRAMS 1, 2, AND 3 CAN SHARE

A SEPARATE COPY OF SUBROUTINE A

SUBROUTINE A.

MUST BE PROVIDED FOR EACH PROGRAM.
MR-3667

Figure

10-6

Reentrant

10-13

Routines

Using

reentrant
code,
control
follows.
(See Figure 10-7.)

requests

routine

can

processing

reentrant

shared

Task

Task
A
routine

temporarily
relinquishes
control
Q before it completes processing.

reentrant

Task
B
routine

starts
Q.

reentrant

Task

where

processing

completes

regains

processing

use

the

same

routine

copy

reentrant

routine

and

resumes

operating

system

stopped.

TASK

REENTRANT

ROUTINE
Q

MR-3668

Figure

10.3.8.2

10-7

Writing

Sharing

Reentrant

Control

Code

Routine

environment,
when
one
task
is
executing
and
1is
interrupted
to
allow another task to run, a context switch occurs which causes
the
processor
status
word
and
current
contents
of
the
general-purpose registers
(GPRs)
to be saved and replaced by the
appropriate

reentrant
pointers,
routine.

The

context

execute.

values

for

the

task

being

code should use the GPRs and the
or
data
that must be modified

task-related

switch

causes

occurs

all

information

whenever

the

entered.

new

task

GPRs,

the

PS,

saved

Therefore,

stack for any counters,
or manipulated
1in the

1is

and

1impure

allowed

often

area,

other

then

reloads these registers and locations with the appropriate data
for the task being entered.
Notice that one consequence of this
is that a new stack pointer value is loaded into R6,
thereby
causing a new area to be used as the stack when the second task 1is
entered.

The

following

should

be observed when writing

All data should be
purpose

in or pointed

registers.

10-14

reentrant code.

to by one of

the general

stack

can

used

for

temporary

storage

pointers
to
impure
areas
within
the
task
pointer to such a stack would be stored in a

data

space.
GPR.

The

Parameter
addresses
should
be
indirect
reference
rather
than
instructions within the code.

When temporary storage is accessed within the program, it
should be by indexed addresses, which can be set by the
calling task in order to handle any possible recursion.

10.3.9

used
by
indexing
by
putting
them

and
1into

Coroutines

In
some
programming
situations
it
happens
that
several
program
segments or
routines are highly interactive.
Control
1is passed
back and forth between the routines, each going through a period

of suspension before being resumed.
Since the
symmetric
relationship
with
each
other,
coroutines.

routines maintain a
they
are
called

Coroutines

other,

are
two
program
sections,
either
subordinate
to
the
which can call each other.
The nature of the call is "I

have processed
ready to stop,

The

coroutine

all I can for now, so you
then I will continue.”

call

and

subroutine instruction
of
the
stack
and
the
follows.

return

are

can

execute

identical,

each

being

with the destination address
PC
serving
as
the
1linkage

JSR

until

you

are

jump

being on
register,

top
as

PC,@(R6)+

10.3.9.1
Coroutine Calls - The coding of coroutine calls is made
simple by the stack feature.
Initially,
the entry address of the
coroutine

placed

the

stack

JSR

and

from

that

point

the

PC,@*R6)+

instruction is used for both the call and the return
The result of this JSR instruction is to exchange the
the

and

routines
terminated
10-8.

Notice

that

transfer

the

top

swap

the

element

the

control

and

swap.

coroutine

stack,

resume

linkage

10-15

the

two

where

each

was

1is

shown

the

stack

with

operation
example

cleans

control.

and

statements.
contents of

permit

Figure

each

ROUTINE A

STACK

COMMENTS

ROUTINE B

LOC IS PUSHED
ONTO THE STACK

TO PREPARE FOR
MOV #LOC,-(SP}

LOC

THE COROUTINE

—SP

CALL.
LOC:

JSR PC,@{SP)+

PCO

WHEN THE CALL

<SP

IS EXECUTED,

(PCO)

THE PC FROM
ROUTINE A IS

PUSHED ON THE

STACK AND EXECUTION CONTINJSR PC,@(SP)+
PC1

(PCT)

UES AT LCC.
ROUTINE B8 CAN
RETURN CONTROL
TO ROUTINE A
BY ANOTHER
COROQUTINE CALL.

PCO IS POPPED
FROM THE STACK

AND EXECUTION
RESUMES IN

ROUTINE A JUST
AFTER THE CALL

TO ROUTINE B,

I.E., AT PCO.
PC1 1S SAVED

ON THE STACK
FOR A LATER
RETURN 70
ROUTINE B.
MR-3669

Figure

10-8

COROQUTINES

Coroutine

MAIN PROGRAMS

Example

SUBROUTINES
1ST LOC:

—>

JSR PC @ {SP)+

JSR Rn, LOC

JSR PC,@ (SP)+

JSR PC ,@ (SP)+

RTS

JSR Rn, LOC

\J
JSR PC,® (SP)+

MR-3670

Figure

10-9

Coroutines

10-16

vs.

Subroutines

10.3.9.2
compared
1.

Coroutines
Versus
Subroutines
Coroutines
to subroutines in the following ways.

A subroutine can be considered to be subordinate to the
main or calling routine, but a coroutine is considered to
be on the same level, as each coroutine calls the other
when

can

has

completed

subroutine

code.

When

current

executes,
called

when

again,

processing.

called,
the

same

the

code

end

will

1its

execute

before
returning.
A coroutine executes from the point
after the last call of the other coroutine.
Therefore,
the
same
code
will
not
be
executed
each
time
the
coroutine is called.
An example is shown in Figure 10-9.
The

call

same,

and

return

statements

for

coroutines

JSR

This one
call.

instruction

Each

coroutine

point

after

the

entry

point

label,

Coroutines

Using

the

with

each

PC,@(SP)+

also

cleans

stack

The
1last
coroutine
call
will
leave
an
stack that must be popped if no further
made.

10.3.9.3
following

are

follows.

call

returns

last

the

exit

with

would

Coroutines

address
on
the
calls are to be

coroutine

need

required

code

for

with

should

the

specific

subroutines.

used

1in

the

situations.

Coroutines

should

coordinated

basic

structure

used

whenever

their

execution

program.

the

two

tasks

without
For

must

obscuring

example,

the

decoding

a line of assembly language code, the results at any one
position might indicate the next process to be entered.

Where
label

a label is
is present,

Coroutines
process

detected,
it
the operator

should

being

must
must

employed

performed,

be processed.
If
be located, etc.

add

clarity

the

debugging

phase,

ease

the

etc.

assembler

must

perform

lexicographic

scan

each

assembly

language
statement during pass
1
of
the assembly process.
The
various steps
in such a scan should be
separated
from
the main
program flow to add to the program clarity and to aid in debugging
by isolating many details.
Subroutines would not be satisfactory

10-17

here,
as
too
much
information
would
have
to
be
passed
to
subroutine each time it was called.
This subroutine would be

the
too

isolated.
Coroutines
could
be
effectively
used
here
with
one
routine
being
the
assembly-pass-one
routine
and
the
other
extracting
10-10

one

item

illustrates

this

time

from

the

current

input

line.

Figure

example.

ROUTINE A

ROUTINE B

START AND SKIP
BLANKS

NONBLANK

READ NAME

»1

PROCESS NAME

)
SKIP BLANKS

PROCESS MNEMONICS

READ MNEMONICS

READ ADDRESSES

LINE

SEMI-COLON

TERMINATOR

SKIP COMMENT

END

MR-3671

Figure

Coroutines
shows

can

coroutines

events might

Write 01
Read I1
Process

utilized

used

10-10

Coroutine

I/O

processing.

double-buffered

described

Path

I/O

The

using

example
IOX.

as:

concurrently

then

Write 02
Read 12
Process Il
Figure

10-11

concurrently.

illustrates

coroutine

10-18

swapping

interaction.

The

above
flow

ROUTINE #1 IS OPERATING, IT THEN
EXECUTES:

MOV #PC2,-(R6)
JSR PC,@(R6)+
WITH THE FOLLOWING RESULTS:
1.

PC2I1SPOPPED FROM THE STACK

AND THE SP AUTOINCREMENTED.

SPIS AUTODECREMENTED
AND

TO THE
ROL
IS TRANSFERRED
CONT

THE OLD PC (I.E., PC1) IS PUSHED.

P —

)

5P —»

PC2

LOCATION PC2 (I.E.. ROUTINE #2).

ROUTINE #2 IS OPERATING, IT THEN

EXECUTES:

JSR PC.@(R6)+

WITH THE RESULT THAT PC2 IS

EXCHANGED FOR PC1 ON THE
STACK AND CONTROL IS

TRANSFERRED BACK TO ROUTINE #1.
MR-3672

Figure

Routine

with

operating,

MOV

#PC2,-(R6)

JSR

PC,Q@(R6)+

the

following

10-11

Coroutine

then

Interaction

executes:

results.

PC2

popped

from

the

stack

and

1is

autodecremented

and

the

o0ld

autoincremented.

(i.e.

PCl)

1is

pushed.

Control

1is

tranferred

the

location

PC2

(i.e.

routine

the

stack

and

other

than

1its

2) .

Routine
JSR

with

10.3.10

operating,

then

executes:

PC,Q@(R6)+

the

control

result
is

that

PC2

transferred

back

exchanged

for

PCl

routine

stack

facility,

Recursion

interesting

aspect

providing
for
interrupts,
is

automatic
handling
of
nested
subroutines
and
that a program may call on itself as a subroutine

just

call

can

any

other

routine.

10-19

Each

new

call

causes

the return linkage to be placed on the stack,
which,
as
last-in/first-out
queue,
sets
up
a
natural
unraveling
routine just after the point of departure.
Typical

shown

flow

for

Figure

recursive

routine

might

something

it
to

is a
each

that

10-12.

MAIN PROGRAM

SUB 1

SuB 2

SUB 2

MR-3673

Figure

The
SUB

10-12

Recursive

Routine

Flow

main program calls function 1, SUB 1, which
2, which recurses once before returning.

calls

function

Example:
DNCF:

’
r
r

BEQ

;TO

JSR

R5,DNCF

s RECURSE

EXIT

;RETURN

RECURSIVE

LOOP

'
[4
[4

RTS

;EACH

CALL,

sMAIN

PROGRAM

FOR

THEN

The
routine DNCF calls
itself
until
the
equal
to
0,
then
it
exits
to
1$
where
executed,
final
In

returning

time

general,

return

recursion

the

once

main

techniques

for

variable
the
RTS

each

tested

becomes
1is

instruction

recursive

call

and

one

program.
will

lead

slower

programs

than

the corresponding
interactive techniques,
but
the
recursion will
give shorter programs in memory space used.
Both the brevity and
clarity produced by recursion are important in assembly language
programs.

10-20

Uses of Recursion - Recursion can be used in any
the
same
process
1is
required
several
times.
function
to
be
integrated
may
contain
another

integrated,

i.e.,

solve

for

routine in which
For
example,
a
function
to
be

where:
SM

F(X)

and:
F(X)

Another
use
for
a
recursive
factorial function because

function

FACT (N)

Recursion
The

should

terminate

macroprocessor

recursive,
For

example,

When

must

work

macro

within

call

when

within

can

G (X)

could

nested

encountered
i.e.,

calculating

example,

1is

macrodefinitions

for

and

calls.

called.

other

within

macros

can

definition,

process

one

the

macro

itself

processor

before

finished
with
another,
then
to continue with
The stack is used for
a separate storage area
associated with each call to the procedure.

the
for

available,

1long

nested

possible for
are used to
generated.
10.3.11

Processor
errors
to

location.

definitions

macros

are

1is

Traps

and
enter

trap

conditions are
list describes

programming
the

conditions

"service"

interrupt

cause

state

and

generated

the

trap

Management

KDF1l1-AA
a

software.

arbitrated according to a priority.
the priority from highest to lowest.

Condition
Memory

previous one.
the variables

a macro to call itself.
However, unless conditionals
terminate
this
expansion,
an
infinite
loop could
be

Certain
processor

macrodefinition,

recursively;

FACT(N-1)
*N

MACRO-11,

process

The

fixed

Pending
following

Description
A

memory

(MMUERR)

Violation*

abort

Timeout Error¥*
(BUSERR)

No response from a bus device during
a
bus
transaction
causes
an
abort
and

Parity

Error*

(PARERR)

traps

parity

the

management

and

10-21

violation

location

error

processor

transaction
traps

traps

2508.

48.

signal

received

during

causes

location

causes

location

1148.

abort

by
bus

and

Trace

(T)

Bit*

If PSW bit 4
is set at the end
instruction execution, the processor
traps to location 148.

Stack

Overflow*
(STKOVF)

If
the
kernel
stack
pointer
was
pushed
below
400
dur ing
an
instruction execution, the processor
traps to location 48 at the end of
the instruction.

Power Fail*
(PFAIL)

If
bus
signal
became negated

Power
during

OK
(BPOKH)
instruction

execution,
the
processor
traps
to
location
248
at
the
end
of
the
instruction.
Interrupt
(Maskable
Interrupt
(Maskable
Interrupt
(Maskable

Level 7 (BIRQ7)
by PS<07:05>)
Level 6 (BIRQ6)
by PS<07:05>)
Level 5 (BIRQ5)
by PS<07:05>)

Interrupt

Level

(Maskable

by PS<07:05>)

Halt

device
1interrupt
requests
are
and PS<07:05> are properly
set,
the
processor
at
the
end
of
the present instruction execution
will
initiate
an
interrupt
vector
sequenced on the bus.
asserted

(BIRQ4)

PS<07:05>

line

All

5
4
0->3

5, 4
4
None

*Nonmaskable-software
is

BUSERR,

executing

10.3.11.1

Inhibited

If
BHALTL
bus
signal
during
the
service
processor

MMUERR,

Levels

Trap

emulators,

cannot

PARERR

are

will

enter

the

condition.

inhibit

mutally

1is
asserted
state,
the

exclusive

ODT

when

mode.

the

CTLERR,
processor

program.

Instructions

I/O0O

monitors,

Trap

instructions

debugging

provide

packages,

and

for

calls

user-defined

interpreters.
When a trap occurs,
the contents of the current
program counter
(PC) and program status word (PS) are pushed onto
the processor stack and replaced by the contents of a 2-word trap

vector containing a new PC and new PS.
The return sequence from a
trap involves executing an RTI or RTT instruction which restores
the o0ld
PC
and o0ld
PS by popping them from the stack.
Trap
vectors

are

located

permanently

assigned

fixed

addresses.

The
EMT
(trap emulator)
and
TRAP
instructions do not
use
the
low-order
byte
of
the
word
in
their
machine
language

representation.
the

low-order

This allows user

byte.

The

new

information

value

10-22

the

to be
PC

transferred

loaded

from

the

vector
address of
starting
address

the
TRAP or
EMT instructions
is typically the
of
a
routine
to
access
and
interpret
this
Such a routine is called a trap handler.

information.
The

trap

restore

handler
all

instruction
between the
that
needs
return

the

main

The

trap

handler

patch

accomplish
GPRs,

several

interpret

tasks.
the

low

must

byte

save

and

the

trap

and call the indicated routine, serve as an interface
calling program and this routine by handling any data
to
be
passed
between
them,
and,
finally,
cause
the

out

must

necessary

performed.

routine.

can

area

be
is

However,

useful
often

the

patching

difficult

l-word

TRAP

because

technique.
a

2-word

instruction

may

Jumping
jump

must

used

dispatch
to
patch
areas.
A
sufficient
number
of
slots
for
patching
should
first
be
reserved
in
the
dispatch
table
of
the
trap handler.
The jump can then be accomplished by placing the
address of the patch area into the table and inserting the proper
TRAP instruction where the patch is to be made.
10.3.11.2
Use of Macro Calls - The trap handler can be
program
to
dispatch
execution
to
any
one
of
several
Macros may be defined to cause the proper expansion of
one of these routines, as in this example.
.MACRO

SUB2

MOV

ARG,

TRAP

+1]

used in a
routines.
a

call

ARG

. ENDM

When expanded, this macro sets up the one argument required by the
routine in RO and then causes the trap instruction with the number
1 in the lower byte.
The trap handler should be written so that
it recognizes a
1
as a call
to SUB2.
Notice that ARG here
is
being transmitted to SUB2 from the calling program.
It may be
data required by the routine or
it may be a pointer to a longer
list of arguments.
In

operating

system

environment

is used to
The monitor

RT-11,

the

EMT

instruction

call system or monitor routines from a user program.
of an operating system necessarily contains coding for
many functions,
such as I/O, file manipulation, etc.
This coding
is made accessible to the program through a series of macro calls
which expand into EMT instructions with low bytes, indicating the
desired routine or group of routines to which the desired routine
belongs.
Often
a
GPR
1is
designated
to
be
used
to
pass
an
identification code to further indicate to the trap handler which
routine is desired.
For example, the macro expansion for a resume
execution command in RT-11 is as follows.
.MACRO

CM3,

.RSUM

. ENDM

10-23

CM3

defined

follows.

+MACRO CM3 CHAN, CODE
#CODE *400,RO0

MOV

.ITF

CHAN,BISB
EMT

CHAN,RO

374

. ENDM

Note

that the EMT low byte is 374.
This 1is interpreted by the EMT
handler to indicate a group of routines.
Then the contents of RO
(high byte)
are tested by the handler
to
identify exactly which
routine within the group is being requested, in this case routine
number
2.
(The
CM3
call
of
the
.RSUM
1is
set
up
to
pass
the

identification

10.3.12
Almost

code.)

Conversion
all

assembly

Routines
language

programs

require

the

translation

data or
results from one form to another.
Coding that performs
such a transformation will be called a conversion routine in this
manual.
Several commonly used conversion routines are included in
the

following

Almost

all

pages.

assembly

language

programs

1involve

some

conversion routines: octal to ASCII, octal to decimal,
to ASCII are a few of the most widely used.
Arithmetic
conversion
Division

multiply
routines.

and

typically

divide

approched

The division can be
rotates

and

routines

are

fundamental

two

ways.

one

accomplished

type

decimal

many

through a combination of

subtractions.

Examples:

Assume the following code and register data;
example easier, also assume a 3-bit word.

DIV:

MOV
CLR

ASL

(SP)

ASL

ROL

#3,-(SP)
- (SP)

CMP

RO,R3

BLT
SUB

2$
R3,R0

INC
DEC
BNE

(SP)
2 (SP)
S1

sSET UP DIGIT
; CLEAR RESULT

:R0

CONTAINS

: INCREMENT
; DECREMENT

10-24

COUNTER

REMAINDER

RESULT
COUNTER

make

the

Therefore,

to divide

remainder
7-multiplicand
2-multiplier

R0=000
R1=111
R3=010
C

bit=0

STACK
011

counter

quotient

000

Following through the coding,
the quotient,
remainder,
and dividend all shift left, manipulating the most
significant

the

digit

first,

conclusion of

etc.

the

routine:

R0=001

remainder

R1=000
R3=010
STACK
000

counter

011

quotient

second

the

method

division

occurs

subtraction of the powers of the divisor,
number

Example:

To divide

until

number

22110

subtractions

by 10,

nonnegative

first

value

subtractions

each

try to

1is

each

repeated

keeping a count

level.

subtract powers of

obtained,

counting

power.

221
-1000

negative so go to next lower power, count for lO3 = 0.
221
-100

121

count for 102 = 1.

count

-100

10-25

the

negative,
count for

sozreduce
10°
= 2

power.

for

10l

count

-10

-10
1

count

-10

negative, so count for 10l = 2.
No

lower

Answer

power,

022,

remainder

Multiplication can be done
through a combination
additions or through repetitive additions.

rotates

Example:
Assume

the

following

code

and

3-bit

word.

CLR
MOV

;HIGH

#3,CNT

;SET

MOV

R1,MULT;

s MULTIPLICAND

HALF
UP

ANSWER

COUNTER

ROR

BCC

NOW

ADD

MULT,RO

;IF

INDICATED,

ADD
;sMULTIPLICAND

NOW ;

The

ROR

R0O4

DEC

CNT

BNE

MULT:

CNT:

following

conditions

exist

000

110

high-order half
multiplicand

011

multiplier

10-26

for

result

times

and

After

the

RO
Rl

=
=

010
010

100

routine
-

executed:

high-order half of result
low-order half of result

CNT = 0
MULT = 110
Example:

Multiplication

MUL50:

508(101000).

MOV
ASL

RO,-(SP)
RO

ASL
ADD

RO
(SP)+,R0

ASL

RO
RO

ASL

RETURN

contains
RO

After

111

execution:
RO

100011000

(7*508

ASCII

Conversions

The

internal

representation

addressed

by R2.

4308).

conversion

number

ASCII

as well

characters

the

.to

conversion

the

an
internal
number
to
ASCII
in
I/0
operations
presents
a
challenge.
The following routine takes the 16-bit word in R1l and
stores
the
corresponding
six
ASCII
characters
1in
the
buffer

OUT:

MOV

#5,R0

; LOOP

LOOP:

MOV
BIC
ADD

R1,-(SP)
#177770,@SP
#'0,@SP

; COPY WORD INTO STACK
;ONE OCTAL VALUE
; CONVERT TO ASCII

COUNT

MOVB

(SP)+,-(R2)

;STORE

ASR
ASR

R1
R1

; SHIFT
; RIGHT

ASR
DEC

R1
RO

; THREE
;TEST IF

BNE

LOOP

;NO,

BIC
ADD
MOVB

#177776,R1
#'0,R1
R5,-(R2)

AGAIN
;GET LAST BIT
; CONVERT TO ASCII
;STORE IN BUFFER

RTS

; DONE
, RETURN

10-27

BUFFER

DONE

10.4

PROGRAMMING THE PROCESSOR STATUS WORD
current processor status can be read and written using several
prcgramming
techniques on
the PS.
The PS has an
I/0 address of
777776 .
The
KDF1ll
and
other
PDP-11
processors
implement
this
address, whereas LSI-11 and LSI-11/2 processors do not.

The

One

technique

address

The

with

any

CLR

Q@#177776

MOV

@#177776,

first

moves

the

use

the

I/0

address

source

destination

second

instruction

instruction.

instruction
contents

clears

the

the
to

and

general

the

RO.

The

PS explicit address (777776) can be accessed on a word or byte
basis.
The KDF1ll will recognize the PS odd address
(777777)
and
the
access
result
will
be
identical
to
an
odd
memory
address

reference.

Another

technique

MTPS

MFPS.

and

memory

Refer

10.5

These

management

Paragraph

the

two

enabled

8.3.3.2

PROGRAMMING

Programming
A
special

use

instructions

for

dedicated

only

certain

reference

instructions,

the

bits

even

are

byte.

protected.

details.

PERIPHERALS

of LSI-11
class
of

bus compatible
instructions

operations

modules
(devices)
is simple.
to
deal
with
input/output

is
unnecessary.
The bus
structure permits a
unified
addressing structure in which control, status, and data registers
for
devices
are
directly
addressed
as
memory
locations.

Therefore,

all

operations on these registers, such as tranferring
into or out of them or manipulating data within them,

information
are

performed

The

use

greatly
For

all

example,

this

need

normal

memory

increases

directly

buffer

with

case,

memory

reference

the

information

the

and

RBUF,

BEQ

SERVICE

the

looks

and

device

branch

CMP

program

(RBUF)

instructions.

instructions

flexibility

value

reference

made

registers

programming.

can

the

result.

DLV1l

compared

#101

for

101

the

branches

finds

information

device

input/output

into

comparison.

10-28

it.

intermediate

receiver
There

data
is

no
for

When

the

can

transfer

another

character

is of interest, a memory reference instruction
the
character
into
a
user
buffer
in memory or
to
peripheral device.
The instruction:
MOV

transfers

into

character

user-defined

from

DRINBUF

the

LOC

DRV11l

Data

Input

Buffer

(DRINBUF)

location.

All

arithmetic operations can be performed on a peripheral device
register.
For
example,
the
instruction ADD #10, DROUT BUF will
add 10 to the DRV11l's Output Buffer.

All

read/write

device

registers

can

There

is
no
need
to
funnel
all
operations,
and
comparisons
through
accumulator registers.

treated

accumulators.

data
transfers,
arithmetic
a
single or
small
number
of

10.6
PDP-11 PROGRAMMING EXAMPLES
The
programming
examples
the
on
following
pages
show
how
the
instruction
set,
the
addressing
modes,
and
the
programming
techniques can be used to solve some simple problems.
The format
used is either PAL-11 or MACRO-11.
Program

Program

Address

Contents

Label

Code

Operand

; PROGRAMMING

s SUBTRACT
s FROM

000000
000001

R0O=%0

000002
000003

R2=%2

000004
000005

R4=%4

000006
000007

SP=%6

012706
000500

000504

000510

700-710

1000-1010

.=500
START:

#.,SP

012701

MOV

000700
012702

#700,R1

MOV

#712,R2

MOV

#1000,R3

MOV

#1012,R4

012704

LOCS

PC=%7

MOV

012703

OF
LOCS

R5=%5

001000
000520

CONTENTS

R3=%3

000712
000514

EXAMPLE

CONTENTS

R1-%1

000500
000500

Comments

001012
000524

005000

CLR

000526

005005

CLR

10-29

s INIT

STACK

POINTER

SUM1l:

000542

062105
020102
001375
062300
020304
001375

000544

160500

DIFF:

000546

000000
000700

=700

000700
000702

000001

WORD

000704
000706
000710

000003
000004
000005

001000
001002
001004
001006

001000
000004
000005
000006
000007

001010

000010

000430
000532
000534
000536
000540

SUM2:

ADD
CMP
BNE
ADD
CMP
BNE

(R1)+,R5
R1,R2
SUM1
(R3)+,R0
R3,R4
SUM2

; START ADDING
; FINISHED ADDING?
; IF NOT BRANCH BACK
; START ADDING
; FINISHED ADDING?
; IF NOT BRANCH BACK

SUB

R5,R0

; SUBTRACT

HALT

; THAT'S ALL

1,2,3,4,5

000002

=1000
WORD 4,5,6,7,8

A-30

000500

END

; PROGRAM
; IN

COUNT

; COUNT

NEGATIVE

NUMBERS

TABLE

;20. SIGNED WORDS
; BEGINNING AT LOC

VALUES

HOW MANY ARE NEGATIVE

R0O=%0
R1l=%1
R2=%2
SP=%6
PC=%7
.=500
START:

MOV#.,SP
MOV #VALUE,R1
MOV #VALUES+40.,R2
CLR RO

RESULTS

;SET
;SET
;SET

10-30

UP
UP
UP

STACK
POINTER
COUNTER

FOLKS

CHECK:

TST

(R1l)+

; TEST

BPL

; POSITIVE?

INC

;NO,

CMP

R1,R2

; COUNTER
; YES, FINISHED?

BNE

CHECK

;NO,

INCREMENT

;YES,

HALT

VALUES:

NUMBER

BACK

STOP

0
.END

s PROGRAM

COUNT

ABOVE

AVERAGE

;LIST OF 16. QUIZ
;BEGINNING AT LOC

SCORES
SCORES

; KNOWN

AVERAGE

LOC

;COUNT

SCORES

QUIZ

SCQRES

AVERAGE

ABOVE

AVERAGE

R0=%0
R1=%1
R2=%2
R3=%3

SP=%6
PC=%7

.=500
START:

CHECK:

NO:

MOV
MOV

MOV

#.,SP
#16.,R1
#SCORES,R2

MOV
CLR

#AVERAGE,R3
RO

; SET

STACK

; SET

COUNTER

; SET

POINTER

CMP

(R2)+, (R3)

; COMPARE

BLE

; LESS THAN OR
;TO AVERAGE?

SCORE

INC

; NO,

DEC

;YES,

BNE

CHECK

;FINISHED?

HALT

;:YES,

AVERAGE:

65.

SCORES*

25.,70.,100.,60 .,80.,80.,40.

10-31

AVERAGE

COUNT
DECREMENT

STOP

55.,75.,100.,65 .,90.,70.,65.,70.
.END

AND

EQUAL

NO,

COUNTER

CHECK

; PROGRAMMING

;ACCEPT

;STORE

EXAMPLE

(IMMEDIATE

20.

ECHO)

AND

CHARS

;FROM

THE

; ECHO

ENTIRE

KEYBOARD,
STRING

OUTPUT
FROM

STORAGE

R0O=%0

R1=%1
SP=%6

CR=15
LF=12
TKS=177560

TKB=TKS+2
TPS=TKB+2
TPB=TPS+2
.TITLE

ECHO

.=1000
MOV
MOV

#.,SP
#SAVE+2,R0

;s INITIALIZE STACK
:SA OF BUFFER
;BEYOND CR & LF

MOV

#20.,R1

:CHARACTER COUNT

IN:

TSTB
BPL

@#TKS
IN

:CHAR IN BUFFER?
s IF NOT BRANCH BACK

ECHO:

TSTB

@#TPS

+CHECK

TELEPRINTER

s READY

STATUS

CHARACTER

START:

;AND

WAIT

BPL

ECHO

MOVB
MOVB

@#TKB,@#TPB

+:ECHO

@#TKB, (RO) +

+STORE

DEC

BNE

:FINISHED

MOV

#SAVE ,RO

:SA OF BUFFER INCLUDING

MOV

$#22.,R1

;CR

CHARACTER AWAY

TSTB

@#TPS

BPL

ouT

MOVB

(RO)+,Q@#TPB
R1

BNE

ouT

.BYTE

STATUS

;OUTPUT CHARACTER
+sFINISHED

HALT
:
SAVE

+:CHECK TELEPRINTER
: READY

DEC

INPUTTING?

; COUNTER OF BUFFER

; INCLUDING
OuT:

POINTER

CR,LF

.=.+20,
.END

10-32

OUTPUTTING?

; PROGRAMMING

; SUBROUTINE
INPUT:

MOV

EXAMPLE

INPUT

TEN

#BUFFER,
RO

VALUES

:SET

SA OF

: STORAGE

MOV
IN:

TSTB
BPL

OouT:

TSTB
BPL

;SET

@#TKS

;TEST

KYBD

: TEST

TTO

@#TPS

BNE

RTS

; SUBROUTINE

LOOP:

MOV

#-10.,R4

MOV

COUNT,R3

#BUFFER+9.,R0

MOVB

(RO)+,R1

CMPB

(RO)+,R1

; ECHO CHARACTER
; STORE CHARACTER
; INC COUNTER

TEN

VALUES

MOVB

- (R0O) ,R2

MOVB

R1, (RO)+
R2,R1

INC

BNE

LOOP

INSERT:

MOVB

LINE2:

SORT

R3,RO0

MOV

LINE]l:

R1,BUFFER+10.
(R4)

INC

COUNT

BNE

MOV

#-9.,COUNT

; RESTORE

RTS

; EXIT

LOCATION

.WORD -9.
.ASCII/INPUT

ANY TEN SINGLE-DIGIT VALUES
.ASCII/SORT AND OUTPUT THEM IN/
.ASCII/SMALLEST TO LARGEST ORDER./

BUFFER:
.END

STATUS

EXAMPLE

ADD

GT:

COUNT:

READY

;EXIT

MOV

BGE

LT:

STATUS

OUT

; PROGRAMMING

READY

MOVB @#TKB,@#TPB
MOVB @#TKB, (RO) +
INC R1

SORT:

BUFFER

UP COUNTER

#-10.,R1

INITSP

;FINISHED!!!

10-33

COUNT

(0-9);

I'LL/

; PROGRAMMING

; SUBROUTINE
; INPUT

;OUTPUT

TEN

EXAMPLE

EXAMPLE
VALUES,

THEM

SORT,

SMALLEST

AND

LARGEST

ORDER

R0O=%0
R1=%1

R2=%2
R3=%3

R4=%4
R5=%5

SP=%6
PC=%7
TKS=177560

(address of
TKB=TKS+2 -

terminal control status register)
(terminal data buffer register)

TPS=TKB+2

(terminal
TPB=TPS+2

output control and status registers)
- (terminal output data buffer)

.=3000
INITSP:

MOV

#.,SP

JSR PC,CRLF
JSR R5, OUTPUT
LINE1

69.
JSR PC,CRLF
JSR R5,0UTPUT
LINE?2
26.
JSR PC,CRLF
JSR PC, INPUT
JSR PC,SORT
JSR PC,CRLF
JSR R5,0UTPUT
BUFFER
10.
JSR

HALT

; INITIALIZE STACK POINTER
;GO TO CRLF SUBROUTINE
; GOT TO OUTPUT SUBROUTINE
;SA OF LINE 1 BUFFER
;NUMBER OF OUTPUTS
;GO TO CRLF SUBROUTINE
;GO TO OUTPUT SUBROUTINE
;SA OF LINE 2 BUFFER
;NUMBER OF OUTPUTS
;GO TO CRLF SUBROUTINE
;GO TO INPUT SUBROUTINE

;GO TO SORT SUBROUTINE

;GO TO CRLF SUBROUTINE
;GO TO OUTPUT SUBROUTINE
; INPUT BUFFER AREA
; NUMBER OF OUTPUTS

PC,CRLF

;THE

10-34

END!!!

; PROGRAMMING
; SUBROUTINE

CRLF:

TSTB
BPL

LNFD:

; TEST

TTO

MOVB

#15,@#TPB

;OUTPUT

TSTB

@#TPS

;TEST

;OUTPUT

RTS

; EXIT

OUTPUT

LENGTH

MOV

(R5)+,R0

MOV

(R5)+,R1

READY

LINE

RETURN
STATUS

FEED

MESSAGE

;PICK
; PICK

NEG R1
TSTB Q@#TPS
MOVB

STATUS

CARRIAGE

TTO

BPL LNFD
MOVB #12,Q@#TPB

BPL

READY

CRLF

; SUBROUTINE

AGAIN:

OUTPUT

@#TPS

s VARIABLE

OUTPUT:

EXAMPLE
TO

UP
UP

SA OF DATA BLOCK
NUMBER OF OUTPUTS

;NEGATE IT
; TEST TTO READY

STATUS

AGAIN

(RO)+,Q@#TPB

INC
BNE

R1
AGAIN

RTS

RS5

; OUTPUT

;BUMP

CHARACTER

COUNTER

10.7
LOOPING TECHNIQUES
Looping techniques are illustrated in the program
The segments are used to clear a 50-word table.
1.

AUTOINCREMENT

(POINTER ADDRESS
RO

MOV

LOOP:

AUTODECREMENT

GPR)

%0
#TBL,RO

CLR

(RO)+

CMP

RO, #TBL+100.

BNE

LOOP

(POINTER AND

LIMIT

VALUES

R0O=%0
R1=%1

MOV
LOOP:

#TBL,RO

MOV

#TBL+100.,R1

CLR

CMP

R1,RO

BNE

LOOP

10-35

segments

(R1)

GPR)

below.

COUNTER

(DECREMENTING

GPR

CONTAINING

COUNT)

R0O=%0
R1=%1

CLR

#TBL,
RO
#50.,R1
+
(RO)

DEC

BNE

LOOP

MOV

LOOP:

INDEX

MODIFICATION

(INDEXED

MODE;

MODIFYING

VALUE)

R0O=%0
LOOP:

FASTER

INDEX

CLR

CLR
ADD

TBL (RO)
#2,R0

CMP

RO, #100.

BNE

LOOP

MODIFICATION

(STORING

VALUES

1IN

GPR)
R0O=%0

R1=%1
R2=%2
MOV

MOV

LOOP:

CLR

CLR
CMP

TBL (RO)
R1,R0O
RO,R2

BNE

LOOP

ADD

ADDRESS

MODIFICATION

#2,R1
#100. ,R2

(INDEXED

MODE;

ADDRESS)
RO=%0
LOOP:

MOV

#TBL, RO

CLR

0 (RO)

ADD

#2,LO0OP+2

CMP

LOOP+2,#100.

BNE

LOOP

10-36

MODIFYING

BASE

APPENDIX

GENERAL

A.1

REFERENCE

SUMMARY OF KDF11 INSTRUCTIONS

WORD FORMAT
09

00
BINARY-OCTAL
REPRESENTATION

MODE
1

288!

R
{

1
MR 2886

NOO~rWN+HO

Mode

Name

Symbolic

Description

(R) is operand [ex. R2 = 9,2]

(R)

(R) is address

auto-increment

(R)+

auto-incr deferred

(R) is adrs; (R) +(1 or 2)

@ (R)+

auto-decrement

(R) is adrs of adrs; (R) 42

—(R)

auto-decr deferred

(R) —(1 or 2); is adrs

@ —(R)

index

(R) —2; (R) is adrs of adrs

X(R)

index deferred

(R) + X is adrs

@X(R)

PROGRAM COUNTER ADDRESSING

(R) + X is adrs of adrs

Reg =7
MODE
1

7
b

}

1
MR

2887

immediate

operand n follows instr

3
6

absolute

@ #A

address A follows instr

relative

relative deferred

instr adrs + 4 4+ X is adrs

instr adrs + 4 + X is adrs of adrs

LEGEND
Op Codes

Operations

[]

= O for word/1 for byte

()

— source field (6 bits)

= destination field (6 bits)
= gen register (3 bits),

— contents of destination

XXX

Oto7
= offset (8 bits), +127

— contents of register

<«

— becomes

to —128

INFORMATION

— contents of

— contents of source

Op Codes

Operations

N
NN

X
%

— number (3 bits)
= number (6 bits)

Boolean

Condition Codes

<
>

= AND
= inclusive OR

—_

— exclusive OR
= NOT

0
1

— relative address
— register definition

SINGLE OPERAND:
19

— conditionally set/cleared
— not affected
— cleared
— set

OPR dst
l

OP CODE

—

SSQOR DD

Mne-

monic

Op Code

Instruction

dst Result

CLR(B)
COM(B)
INC(B)

@ 050DD
W 051DD
W 052DD

clear
complement (1’s)
increment

0
~d
d+1

010
0
:

DEC(B)
NEG(B)
TST(B)

W 053DD
N 054DD
W 057DD

decrement
negate (2's compl)
test

d—1
—d
d

rotate right
rotate left
arith shift right
arith shift left

-C,d
C,d«
d/2
2d

add carry
subtract carry
sign extend

d+ C
d—-C
Oor—1

General

Rotate & Shift

ROR(B)
ROL(B)
ASR(B)
ASL(B)

SWAB

m
®
B
®

060DD
061DD
062DD
063DD

0003DD

swap bytes

Multiple Precision

ADC(B)
SBC(B)
SXT

W 055DD
MW 056DD
0067DD

*
*
-

g
0

Processor Status (PS) Operators

MFPS
MTPS

1067DD
1064SS

DOUBLE OPERAND:

move byte from PS
move byte to PS
OPR src, dst

d <PS
PS <s

OPR src, R or OPR R, dst
06

05
T

OpP CODE

0
*

Mnemonic

Op Code

Instruction

Operation

General
MOV(B)

CMP(B)

W 2SSDD

1SSDD

move

d<s

comapare

s —d

®ooR

ADD

06SSDD

add

des+d

SUB

16SSDD

subtract

de<d—s

Logical
BIT(B)
BIC(B)

W 3SSDD
W 4SSDD

BIS(B)

W 5SSDD

XOR

bit test (AND)
bit clear

074RDD

EIS

MUL
DIV
ASH
ASHC

O70RSS
071RSS
072RSS
073RSS

BRANCH:

B-—location

d<(~s)

bit set (OR)

de<svd

exclusive (OR)

d<rvd

multiply
divide
shift arithmetically
arith shift combined

re<rxs
r<r/s

0
0

wooE

If condition is satisfied
Branch to location,
New PC < Updated PC + (2 x offset)

adrs of brinstr 4+ 2
08
T

00
T

BASE CODE

XXX

Op Code = Base Code 4+ XXX
Mne-

Base

monic

Code

Instruction

Branch Condition

Branches
BR

000400

branch (unconditional)

(always)

BNE
BEQ
BPL
BMI

001000
001400
100000
100400

br if not equal (to 0)
br if equal (to 0)
branch if plus
branch if minus

0
=0
+
—

BVC
BVS

102000
102400

br if overflow is clear
br if overflow is set

V
V

=0
=1

Mnemonic

Base
Code

BCC
BCS

103000
103400

Instruction

Branch Condition

br if carry is clear

C
C

br if carry is set

=0
=1

Signed Conditional Branches
BGE

002000

br if greater or

Nvv=0

BLT

002400

equal (to 0)
br if less than (0)

NvVvV=1

BGT

003000

br if greater than (0)

Zv(NvV)=0

BLE

003400

br if less or equal (to0)

Zv(NvV)=1

Unsigned Conditional Branches
BHI
BLOS
BHIS
BLC

101000

branch if higher

CvZ=0

101400
103000
103400

branch if lower or same
branch if higher or same
branch if lower

<
>
<

CvZ=1
C =0
C

JUMP & SUBROUTINE
Mne-

monic

Op Code

JMP
JSR
RTS

0001DD
O004RDD
0O0020R

Instruction
jump
jump to subroutine l
return from
;
subroutine

MARK

SOB

O064NN
077RNN

Notes
PC <« dst

use same R

mark
subtract 1 & br
(if -« 0)

aid in subr return

(R) — 1, then if (R) =« O:
PC « Updated PC —
(2 x NN)

TRAP & INTERRUPT:
Mnemonic

EMT
TRAP

Op Code
104000
to 104377
104400

Instruction

Notes

emulator trap
(not for general use)
trap

PC at 30, PS at 32

breakpoint trap
input/output trap
return from interrupt
return from interrupt

PC at 14, PS at 16
PC at 20, PS at 22

PC at 34, PS at 36

to 104777

BPT
10T
RTI
RTT

000003
000004
000002
000006

inhibit T bit trap

MISCELLANEOUS:

Mnemonic

Op Code

Instruction.

HALT

000000

halt

WAIT

000001

wait for interrupt

RESET
NOP

000005
000240

reset external bus
(no operation)

MFPI
MTPI
MFPD

0065SS
0066DD
1065SS

move from previous instr space
move to previous instr space
move from previous data space

MTPD

1066DD

move to previous data space

CONDITION CODE OPERATORS:
15

OP CODE BASE=000240

O — CLEAR SELECTED COND. CODE BITS
1 — SET SELECTED COND. CODE BITS

Mnemonic

Op Code

CLC
CLV
CLZ
CLN

000241
000242
000244
000250

cCC

Instruction

clear C
clear V
clear Z
clear N

0
-

=
0
-

000257

clear all cc bits

SEC

000261

set C

SEV
SEZ

000262
000264

set V
setZ

-1
-1
-

SEN

000270

set N

SCC

000277

set all cc bits

OPTIONAL FLOATING POINT:
Data Formats
F FORMAT, FLOATING POINT SINGLE PRECISION
15

FRACTION-

15
MEMORY +0

1560

EXP
L

FRACT - 22:16
L

OPTIONAL FLOATING POINT:

Data Formats (Cont)
D FORMAT, FLOATING POINT DOUBLE PRECISION
15

FRACTION <15:0>

FRACTION <31:16>

00
FRACTION <47:32>

+2
1

15
MEMORY +0

EXP
i

FRACT -°94:48 L

S = SIGN OF FRACTION

EXP = EXPONENT IN EXCESS 200 NOTATION, RESTRICTED TO 1 TO 377 OCTAL
FOR NON-VANISHING NUMBERS

FRACTION = 23 BITSiIN F FORMAT, 55 BITS IN D FORMAT + ONE HIDDEN

BIT (NORMALIZATION). THE BINARY RADIX POINT [STO THE LEFT
M

3RO

| FORMAT, INTEGER SINGLE PRECISION

NUMBER <215:0>
1

L FORMAT, DOUBLE PRECISION INTEGER LONG

15
MEMORY +0

NUMBER <<30:16>

00
NUMBER <2165.0>
1

WHERE S = SIGN OF NUMBER

NUMBER = 15 BITS IN | FORMAT, 31 BITS IN L FORMAT
MR

3606

Addressing Formats

DOUBLE OPERAND ADDRESSING
07

FSRC,FDST,SRC,DST

AC
A

SINGLE OPERAND ADDRESSING
12

FSRC, FDST, SRC, DST
|

OC = OPCODE =17
FOC = FLOATING OPCODE

AC = FLOATING POINT ACCUMULATOR (ACO-AC3)
FSRC AND FDST USE FPP ADDRESSING MODES

SPC AND DST USE CPU ADDRESSING MODES
MR 3608

Op Code

Instruction

CFCC

170000

copy fl cond codes

SETF

170001

set floating mode

FD <0

SETI

170002

set integer mode

FL<0

SETD

170011

set fl dbl mode

« 1
FD

SETL

170012

set long integer mode

FL<
1

Mnemonic

LDFPS

1701 src

load FPP prog status

STFPS

1702 dst

store FPP prog status

STST

1703 dst

store (exc codes & adrs)

Notes

CLRF, CLRD

1704 fdst

clear floating/double

TSTF, TSTD

1705 fdst

test fl/dbl

ABSF, ABSD

1706 fdst

make absolute fl/dbl

fdst « fdst

NEGF, NEGD

1707 fdst

negate fl/dbl

fdst « —fdst

MULF, MULD

171 (AC) fsrc

multiply fl/dbl

AC < AC x fsrc

MODF, MODD

171 (AC + 4) fsrc

multiply & integerize

ADDF, ADDD

172 (AC) fsrc

add fl/dbl

AC < AC + fsrc

LDF, LDD

172 (AC + 4) fsrc

load fl/dbl

AC < fsrc

SUBF, SUBD

173 (AC) fsrc

subtract fi/dbl

AC < AC - fsrc

fdst < 0

CMPF, CMPD

173 (AC + 4) fsrc

compare fl/dbl (to AC)

STF,STD

174 (AC) fdst

store fl/dbl

fdst <« AC

DIVF, DIVD

174 (AC + 4) fsrc

divide fl/dbl

AC < AC/fsrc

STEXP

175 (AC) dst

store exponent

STCFI, STCFL
STCDI, STCDL

store & convert fl or
} 175 (AC
+ 4) dst { dbl
to int or long int

STCFD, STCDF

176 (AC) fdst

store & convert (dbl-fl)

LDEXP

176 (AC + 4) src

load exponent

LDCIF, LDCIF
LDCLF, LDCLD
LDCDF, LDCFD

177 (AC) src

177 (AC + 4) fsrc

load & convert int or
fong int to fl or dbl

load & convert (dbl-fi)

A.2

NUMERICAL OP CODE LIST
Mne-

Mne-

Op Code

monic

Mne-

Op Code

monic

Op Code
00 70 00

monic

00 00 00

HALT

00 04 XXX

00 00 01
00 00 02

WAIT
RTI

XXX

BNE
BEQ

00 00 03
00 00 04

BPT
10T

00 14 XXX
00 20 XXX
24 XXX

BLT

00 00 05

RESET

00 30

XXX

BGT

MOV

00 00 06
00 00 07

RTT

00 34 XXX

BLE

CMP

00 00 10

MFPT

00 4R DD

JSR

00 00 77

(unused)

00 01

00 02 OR

7R NN

MUL

DEC

DIv

NEG

ASH

ADC

ASHC

56 DD
00 57 DD

SBC

XOR

TST

OR
1R

NOP

SWAB

SOB

10 00 XXX

BPL

10 04

XXX

BMI

10
10

10 XXX
14 XXX

BHI

XXX

00 60

00 61
00 62

ROL

ASR

ROR

00 64

MARK

00 66 SS

MFPI

00 66 DD

MTPi

00 67

SXT

10 44 00

TRAP

CLRB

BVC

BVS

COMB
INCB
DECB

Jv (reserved)
07 67 77

DD
SS
10 65 SS
10 64

MFPS

MOVB

11
12

CMPB

DD
DD
DD
DD

BITB
BICB

BCC,

NEGB
ADCB

14 SS

BLO

10 56

SBCB

TSTB

16 SS

17 00 00

10 40

00
EMT

10 43

10 62

RORB

ROLB

ASRB

MFPD

10 67

BHIS
BCS,

ASLB
MTPS

DD MTPD

10 30 XXX
34 XXX

> (reserved)

10 63

10 47

BLOS

BIC

00 52
00 53
00 54
00 55

codes

BIT

COM
INC

00 51

00 02 77

BIS

RTS

cond

ADD

JMP

00 02 41

CLR

00 02 27

(unused)

DD
DD

(reserved)

00 03

BGE

00 02 40

BISB
SUB

floating
17

point

A.3 PROCESSOR STATUS WORD
15

PRIORTY

CTMm

]

LEVEL

1
J

TRACE——j

RESERVED
PREVI OUS

NEGATIVE

MEMORY

MANAGEMENT
MODE

CURR ENT

]

ZERO
OVERFLOW

MEMORY

CARRY

MANA GEMENT MODE

SUSPENDED
INSTRUCTION
MR 3638

ABSOLUTE LOADER

BOOTSTRAP LOADER
Address

Contents

Starting Address: — 500

— 744

016 701

— 764

000 002

Memory Size:

— 746

000 026

— 766

—

005 267

Address

Contents

400

017

— 750

012 702

— 770

037

— 752

000 352

— 772

177 756

12K

057

— 754

000 211

— 774

000 765

16K

077

— 756

105 711

— 776

177 560 (TTY)

20K

117

— 760

100 376

24K

137

— 762

116 162

28K

157

(or larger)

or 177 550 (PC11).

773 000 Paper Tape Bootstrap

773 100 Disk/DECtape Bootstrap
773 200 Card Reader Bootstrap

773 300 Cassette Bootstrap
773 400 Floppy Disk Bootstrap

A.5

DEVICE REGISTER ADDRESSES
Registers

Device

Line Time Clock

Device

Interrupt

Address

Vector

(external event)

100

interrupt

Console Terminal
Input Control/Status
input Buffer

177560

Output Control/Status

RCSR
RBUF
XCSR

Output Buffer

XBUF

177566

LAV11 High-Speed Printer
Printer Status
Printer Buffer

High-Speed Paper Tape
Reader/Punch
Reader Status
Reader Buffer
Punch Status
Punch Buffer

177562

177564

177514
177516

200

177550

177552
177554

177556

RXV11 Floppy Disk

System
Status
Buffer

RXCS

177170

RXDB

177172

REV11 ROM Programs

264

165000-165776,
173000-173776

A.6 CONSOLE ODT COMMANDS

Command

Symbol

Description

Slash

Prints the contents of a specified
location.

Carriage Return

<CR>

Line Feed

<LF>

Closes an open location.
Closes an open location and then
opens the next contiguous
location.

Internal Register

$orR

Opens a specifiec processor register.

Opens the PS, must follow an ““$"’

Designator

Processor Status
Word Designator

or R’ command.

Starts program execution.

Proceed

Resumes execution of a program.

Binary Dump

Control-Shift-S

Manufacturing use only.

Reserved for DIGITAL use.

A.7

7-BIT ASCIl CODE

Octal
Code

Char

Octal
Code

Char

Octal
Code

Char

000

NUL

040

100

056

+
!
)

DLE
DC1
DC2
DC3
DC4
NAK

060
061
062
063
064
065

0
1
2
3
4
5

ETB
CAN
EM

067
070
071

072
073
074
075

7
8
9

:
:
<
—

127
130
131

132
133
134
135

RS
us

076
077

>
?

136
137

001
002
003
004
005
006

007
010
011
012
013
014
015
016

017

020
021
022
023
024
025

SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
HT
LF
VT
FF
CR
SO

026

SYN

032
033
034
035

SUB
ESC
FS
GS

027
030
031

036
037

041
042
043
044
054
046
047
050
051
052
053
054
055

057

066

!
“
#
$
A
&
‘
(
)

Octal
Code

Char

140

A
B
C
D
E
F
G
H
|
J
K
L
M

141
142
143
144
145
146
147
150
151
152
153
154
155

117

157

124
125

T
U

101
102
103
104
105
106
107
110
111
112
113
114
115
116

120
121
122
123

126

P
Q
R
S

156

160
161
162
163
164
165

a
b
C
d
e
f
g
h
i
j
k
I
m
n

p
q
r
S
t
u

166

w
X
Y

V4
[
AN
Jor 1

167
170
171

172
173
174
175

w
X
y

A
— Oor «

176
177

—~
DEL

y4
{
|
}

APPENDIX

INSTRUCTION

B.1

BASIC

The
following
times.

Instruction

INSTRUCTION

TIMING

are

the

assumptions

times,

are

calculated

Instruction

Time

TIMING

Basic

Time

used

using

calculate

this

equation

Source

Time

instruction

Destination

Time

If memory management
is
enabled,
add
.16
microseconds
for
each
memory reference.
To arrive at incremental value to add to the
above

instruction

from memory

cycle

time,

use

the

following

equation

(select

Increment

.16

(Reads

Writes)

.32

(RMW)

All
timing
is based on the MSV11-D memory
(no parity)
following characteristics.
Typical times are shown for
microcycle +10%.

Bus

B.1l.1

Cycle

Access

Cycle

Time

(ns)

DATI

210

DATO (B)

100

545

DATIO (B)

630

1075

(ns)

500

Source Address Time

Instruction

Double

numbers

column).

Operand

Source

Memory

Time

Mode

Cycles

(Microseconds)

1.12

2.25

1.42

2.55

3.67

with the
a 300 ns

Destination

B.1.2

Time

Instruction

MOV,

MFPS,

CMP,

CLR,

MTPI

SXT,

(D)

BIT,

TST

MTPS,

DIV,

ASH,

ASHC

BIC,
SWAB,

BIS,
COM,

(D)

ADD,

SUB,

INC,

Memory
Cycles

Time
(Microseconds)

1
2

1
1

1.84
1.84

2.66

1.84

5
6

2
2

2.96
2.96

4.09

1
2

1
1

1.42
1.42

3
4

2
1

2.25
1.42
2.55

6
7

2
3

2.55
3.67

0
1
1

1
2

3
4
5

2
1
2

1.22
1.35

6
7

2
3

2.47

1
2

1
1

0.22
0.22
1.05

1.35

0
2.66
2.66

ADC,

3.49

ROR,

ROL,

2.66

ASR,

ASL,

XOR

5
6

2
2

3.79
3.79
4.91

and

Fetch

Execute

{]

NEG,

SBC,

DEC,

B.1.3

MFPI

MUL,

Destination
Mode

Memory

Time

Instruction

Cycles

(Mic roseconds)

1.72

MOV,

CMP,

BIT,

ADD,

SUB,

BIC,
CLR,

BIS,

SXT,

TST,

SWAB,

INC,

DEC,

COM,
NEG,

ADC,

SBC,

ROR,

ROL,

ASR,

ASL,

MFPS

Instruction

Memory
Cycles

Time
(Microseconds)

MTPS

4.72

MFPI

(D)

4.12

MTPI

(D)

2.85

MUL

24.52

DIV

50.62

ASH

30.8

ASHC

47.02

All

branch

1.72

SOB

(branch)

2.62

(no

2.32

RTS

3.15

MARK

4.65

RTI,

Set

JUMP

instructions

branch)

RTT

Clear

5.17

2.62
-

HALT

WAIT

2.92

RESET

EMT,

TRAP

7.98

IOT,

BPT

8.85

INSTRUCTIONS

Instruction

JMP

JSR

B.1l.4

Mode

Memory
Cycles

Time
(Microseconds)

2.02

2
3

1
2

2.32
2.85

2.32

3.15

4.27

3.86

4.16

4.69

4.16

5
6
7

3
3
4

4.99
4.99
6.11

acknowledged

Latency

Interrupts

(BR

requests)

are

the

end

the

current
when an

instruction.
Interrupt latency,
which
is
the
time
from
interrupt
is
requested
to when
it
is
granted,
is
10.79
microseconds
(max)
(non-EIS)
and
55.65 microseconds
(max)
(EIS)
for

the

KDF1ll-AA.

Interrupt

the

service

first

time,

subroutine

which

the

instruction,

time

from

8.18

acknowledgement

microseconds

max.

NPR

(DMA)

mastership

B.2

1latency,

for

FLOATING

The

execution

the

following:

the

which

first

POINT

time

INSTRUCTION

floating

Type

instruction

Type

addressing

Type

memory.

addition,
are

the

time

from

3.34

TIMING

point

mode

execution

dependent

the

NPR device,

ADDF,

1is

request

bus

microseconds max.

(OPTION)

instruction

dependent

specified

time

many

instructions,

such

data.

Table

B-1 provides the basic instruction times for addressing mode
0 with a microcycle time of 300 ns.
Tables B-2 through B-5 show
the additional time required, using the MSV11-D memory with parity

enabled,
for
instructions with other
than mode 0.
notes
for
the
execution
time
variations
for
the

Refer

instructions.

Table
Mode

B-1

Instruction

Times

Time

Micro- | (MicroInstruction | cycles | seconds)

Notes

Modes

LDF

9.15

1,2,19

Use

LDD

11.55

1,2,23

LDCFD

12.75

1,4

LDCDF

17.25

1,5

CMPF

20.25

14,15

CMPD

22.05

14,15

DIVF

301

91.05

1,29,41,43,44

DIVD

795

239.25

ADDF

121

37.05

1,16,17,18,20,25,27,28,41,43,44

ADDD

139

42.45

1,16,21,22,24,26,27,28,42,43,44

SUBF

124

37.95

1,16,17,18.20,25,27,28,41,43,44

SUBD

142

43.35

1,16,21,22,24,26,27,28,42,43,44

MULF
MULD
MODF

264
641
682

79.95
193.05
205.35

MODD

693

208.65

9.15

1,2,37

TSTD

10.35

1,2,37

TSTF

the

data-dependent

1-7

Table

8-2

1,30,42,43,44

1,29,31,41,43,44
1,30,32,42,43,44
1,26,30,32,33,34,35,41,43,44
1,26,30,32,33,34,36,42,43,44

Table

Instruction

B-1
Mode

Times

(Cont)

Time
Micro- | (MicroInstruction | cycles | seconds)
STF
STD
STCDF
STCFD

18
26
65
48

6.15
8.55
20.25
15.15

CLRF
CLRD

36
40

11.55
12.75

ABSF

13.65

Notes

Modes
Use

1-7

Table

8-3

Use

both

Tables

8-2

and

Use

Table

8-4

Use

Table

8-5

operands

1,38
1,4

ABSD

16.05

NEGF

13.35

1,37

NEGD

15.75

1,37

LDFPS

4.05

LDEXP
LDCIF

38
60

12.75
18.75

1,2,3,37
6,8
6,8

LDCID

17.25

LDCLF

18.75

6,7,8,9

LDCLD

17.25

6,7,8,9

STFPS

5.55

STST

5.85

STEXP

10.95

1,2

STCFI

18.15

11,12,39

STCDI

18.45

11,12,39

STCFL
STCDL

55
56

17.25
17.55

10,11,13,40
10,11,13,40

CFCC

4,35

SETF

4.95

SETD

4,95

SETI

4,95

SETL

4.95

8-3

Table

B-2

Instruction

Times

Read/Write
Memory Cycles

Microcycles*

Time
(Microseconds)

Addressing
Mode

6,8,11

8,10,13

2/0

4/0

4.81

6.92

7,9,11

2
3

Immediate|6,8,11
7,9,11

9,11,14
2,4,7

2/0
1/0

4/0
1/0

5.11
4.05

7.22
2.85

9,11,14

3/0

5/0

5.86

7.97

7,9,11

9,11,14

2/0

4/0

5.11

7.22

8,10,13

10,12,15

|3/0

5/0

6.16

8.27

6
7

8,10,13
10,12,15

10,12,15
[12,14,17

|3/0
(4/0

5/0
6/0

6.16
7.52

8.27
9.63

set

represent

*Note:

three

The

three

different

numbers

(of
conditions:

microcycles)

l.
2.

1If
If

the
the

floating
floating

point
point

number
number

is
is

the

floating

point

number

Table

B-3

positive
negative

each

and

negative

non-0

with

FIUV

flag

clear.

Instruction

Times

Time

Read/Write
Microcycles
Addressing
Mode
1
2

2
3
4
5

Immediate|

Memory Cycles

(Microseconds)

|Single
Double
Single
Double
Single
Double
Precision|{Precision|Precision|Precision|Precision|{Precision
3
6

5
8

0/2
0/2

0/4
0/4

2.56
3.46

4.82
5.72

-2
4
6
5

-6
6
8
7

0/1
1/2
0/2
1/2

0/1
1/4
0/4
1/4

0.23
3.61
3.46
3.91

-0.97
5.87
5.72
6.17

1/2

1/4

3.91

6.17

2/2

2/4

5.27

7.53

Table

B-4

Instruction

Times

Read/Write

Microcycles

Time

Memory Cycles

(Microseconds)

Addressing

[Single

Double

Mode

Single

Integer

Double

Integer

Single

Integer

Double

Integer

1
2
2

2
3

4
5

Immediate|l

1/0
1/0

2/0
2/0

1.35
1.65

2.71
3.01

3
4
5

3
3
4

5
5
6

1/0
2/0

1/0
3/0

1.05
2.41

1.05
3.76

1/0

2/0
3/0

1.65
2.71

3.01
4.06

2/0

3/0

2.71

4.06

3/0

4/0

4.06

5.42

2/0

Table

B-5

Instruction

Times

Read/Write
Memory Cycles

Microcycles

Time
(Microseconds)

Addressing
Mode

[Single
Integer

Double
Integer

Short

Long

0/1

0/2

1.43

2.86

0/1

0/2

Immediate|l

1.73

3.16

0/1

1.13

5
5

1.13

3
3

1/1
0/1

1/2
0/2

2.48
1.73

3.91
3.16

6
7

6
6

1/1
1/1

1/2
1/2

2.78
2.78

4.21
4.21

2/1

2/2

4,13

5.57

Single

Double

Integer

NOTES

Add

300

result

positive.

Add

300

result

non-0.

Add

900

SRC

Add

900

floating

Add

3.3

microseconds

Add

300

Add

1.5

65, 536.

177

point

integer

microseconds

SRC

number

overflow

-177.

rounding.

negative.

absolute

value

integer

Add 1.2 microseconds n times where n
absolute value of integer > = 65,536.
10.

Add

600

11.

Add

2.1

microseconds

the

two

absolute

L2.

Add

600

integer

negative.

L3.

Add

900

integer

negative.

14.

Add

1.2

microseconds

floating

15.

Add

2.1

microseconds

numbers

are

the

same.

16.

Add

600

17.

Add

2.4

microseconds

18.

Add 600
signs.

Add

2.4

microseconds

Add

900

exp

times

values:

adding

and

240

exp

and

1if

smaller

20.

FPACC

1.2

(310

where

exp)

point

are

the

(230

numbers

unequal

exp).

are

but

equal.

the

signs

subtracting

FPSRC.
if

FPSRC

opposite

FPACC.

signs

trapped

microseconds

undefined

times

variable.

where

exp

signs

difference.

Add

3.6

microseconds

1.2

microseconds

subtracting
Add

1.2

Add

900

and

FPACC.

adding

opposite

signs.

microseconds

FPSRC

1.8

trapped

microseconds

undefined

times

variable.

where

exp

difference.

Add
1.2
microseconds
normalize.

times

where

shifts

Add

times

where

shifts

1.8

microseconds

normalize.
Add

3.3

microseconds

Add

600

overflow.

Add

600

need

underflow.

normalize

after

multiply or

divide.

Add 1.2 microseconds if heed to normalize after multiply
or

divide.

31.

Add

600

32.

Add

1.2

for

every

"1"

microseconds

bit

for

multiplier

every

"1"

(FPSRC).

bit

multiplier

module

(calculate

(FPSRC)
.

33.

Add 900 ns
integer and

34.

Add 300, 600, or 900 ns
or 61-100 respectively.

35.

Add

1.8

microseconds

the

fractional

part

36.

Add

1.2

microseconds

the

fractional

part

37.

Add
4.5
microseconds
interrupts.

38.

Add

5.4

trapped

39.

Add

24.3

microseconds

trapped

conversion

error.

40.

Add

24.9

microseconds

trapped

conversion

error.

41.

Add

1.2

microseconds

rounding.

42,

Add

1.8

microseconds

rounding.

43.

Add

8.1

microseconds

trapped

overflow.

44.

Add

9.9

microseconds

trapped

underflow.

microseconds

B.2.1

Interrupt

For

floating

all

times n where
fraction).

exp

21-40,

trapped

41-60

any

100,

the

FPll

overflow.

Latency

point

instructions

except

ADD,

SUB,

MUL,

DIV,

and

MOD,
the interrupt latency is the length of the instruction.
The
longest execution times for each of the FPP instructions are shown
in

Table

B-6.

In the floating point arithmetic
instructions,
interrupts may be
serviced while in the midst of their execution.
Table B-7 shows
the longest times between checking for
interrupt requests during
the
floating
point
instructions.
If
an
interrupt
1is
to
be
serviced before execution is complete,
the instruction is aborted
and all the PDP-11 general registers and floating point registers
are

restored

serviced,
scratch.

the
This

their

original

floating
interrupt

values.

After

the

interrupt

1is

point
instruction
is
restarted
from
restore
routine
takes
6.9
microseconds

and the
time must be added to the interrupt
execution of an instruction is aborted.

latency

times

where

Table

Instruction

B-6

Longest Execution Times

Worst Case (Mode 7)
No. of Microcycles

Time
(Microseconds)

LDF
LDD
LDCFD

50
56
57

18.77
22.08
20.87

CMPF

29.57

LDCDF

33.48

CMPD

34.08

DIVF

350

108.77

259.98

DIVD

849

ADDF

310

96.77

ADDD
SUBF

596
313

184.08
97.67

SUBD

599

184.98

MULF

361

112.07

MULD

919

280.98

MODF

1166

353.57

MODD

1311

398.58

TSTF
TSTD

21.17

24.48

STF

11.42

STD
STCDF
STCFD

35
98
54

16.08
34.98
20.12

CLRF

16.82

CLRD

20.28

ABSF

28.54

ABSD

34.11

NEGF

28.54

NEGD

34.11

LDFPS

8.11

LDEXP
LDCIF
LDCID

64
127
122

22.21
41.11
39.61

LDCLF

134

43.97

LDCLD

129

42.47

STFPS
STST

9.68
11.42

STEXP

42
143

15.68

STCFI
STCDI

144

STCFL

145

46 .28
47.42

STCDL

146

47.72

45.98

Table

Longest

B-6

Worst Case (Mode 7)
No. of Microcycles

Instruction
CFCC
SEIF
SETD
SETI
SETL

Table B-7

Execution Times

(Cont)

Time
(Microseconds)

12
14
14
14
14

Longest

4.35
4.95
4.95
4.95
4.95

Interrupt Request Checking Times
Max.

Instruction

From

ADDF/SUBF
ADDF/SUBF
ADDF/SUBF
ADDF/SUBF
ADDF/SUBF

fetch
fetch
lst svcpt
fetch
lst svcpt

end
lst
2nd
3rd
3rd

ADDF/SUBF
ADDF/SUBF
ADDF/SUBF

2nd
3rd
3rd

3rd
4th
end

ADDD/SUBD
ADDD/SUBD
ADDD/SUBD

fetch
fetch
lst svcpt

ADDF/SUBF

4th

svcpt
svcpt
svcpt
svcpt

svcpt
svcpt

end

Max.

Latency

No. of
Microcycles

Time
(Microseconds)

Time
(Microseconds)
*

95
83
42
71
48

32.27
28.67
12.60
25.07
14.40

32.27
35.57
19.50
31.97
21.30

11
6
80

3.30
1.80
24.00

10.20
8.70
24.00

105
103
56

36.78
36.18
16.80

36.78
43.08
24.70

end
lst svcpt
2nd svcpt

23.70

ADDD/SUBD

fetch

3rd

svcpt

30.18

37.08

ADDD/SUBD
ADDD/SUBD
ADDD/SUBD
ADDD/SUBD
ADDD/SUBD

1st svcpt
2nd svcpt
3rd svcpt
3rd svcpt
4th svcpt

3rd
3rd
4th
end
end

svcpt
svcpt
svcpt

64
13
8
88
87

19.20
3.90
2.40
26.40
26.10

26.10
10.80
9.30
26.40
26.10

MULF

fetch

end

30.47

MULF

fetch

svcpt

28.37

35.27

MULF

svcpt

end

27.90

MULD

fetch

end

101

35.58

MULD
MULD

91
106

32.58
31.80

27.90

fetch
svcpt

svcpt
end

39.48
31.80

DIVF

fetch

end

30.47

DIVF
DIVF

fetch
svcpt

svcpt
end

73
96

25.67
28.80

32.57
28.80

Table

B-7

Longest

Interrupt

Request

Checking

Times

(Cont)
Max.

Max.

No.

Instruction

From

Microcycles

Max.

Latency

Time

(Micro(Microseconds) | seconds)
*

DIVD

fetch

DIVD

fetch

end
svcpt

101
85

35.58
30.78

35.58
37.68

DIVD

svcpt

end

112

33.60

MODF

fetch

end

MODF

fetch

lst

MODF

1st

svcpt

2nd

svcpt

MODF

2nd

svcpt

3rd

svcpt

MODF

2nd

svcpt

end

125

MODF

3rd

svcpt

end

MODD

svcpt

31.67

86
29

29.57
8.70

36.47
15.60

15.30

22.20

37.50

25.80

107

37.38

fetch

end

MODD

fetch

MODD

1st

lst
2nd

svcpt
svcpt

91
29

32.58
8.70

39.48
15.60

svcpt

MODD

2nd

svcpt

3rd

MODD

2nd

svcpt

end

49
135

14.70
40.50

21.60
40.50

MODD

3rd

svcpt

end

28.80

times

include

the

These

*Note:

restore

time.

APPENDIX

KDF11/PDP-11
The

following
operational

processors.

pages contain
features
of

PROGRAM AND OPERATION

DIFFERENCE

chart comparing the programming and
the
KDF1l1l-AA,
LSI-11
and
PDP-11

PDP-11/

ACTIVITY

LSI-11

OPR%R,
as

(R)+

both

incremented
the

sgource

SYwL

OPR%R,

as
of

OPR%R,

source

and

-(R)

using

destination:

(decremented)

the

same

contents

before

being

C s

(R)+

G c.

OPR%R,

and
the

(R)

using

the

same

destination: initial
source operand.

contents

OPR%R,

@(R)+ or OPR%R, @-(R) using the same
as both source and destination: contents of
incremented (decremented) by 2 before being
source

OPR%R,

operand.

@(R)+

OPR%R,

@-(R)

using

the

same

as both source and destination: initial
R are used as the source operand.

contents

OPR

PC,

X(R);

Location

OPR

PC,

JMP

(R)

OPR

A
+

PC,

A will

X(R);

Location

OPR

will
or

(R)+

Initial

JSR

PC,

reg,

the

X(R),

the

OPR

PC,

OPR

+4.
OPR

PC,

used

OPR

PC,

OPR

+2.

are

used

the

(illegal

reg,

traps

JMP %R or JSR
instruction).

reqg,

traps

SWAB

does

change

SWAB

clears

then

%R or JSR
instruction).

Program

(R)+:

JMP

not

OPR

new

PC.

(illegal

addresses
addresses

PC,

(R)+:

incremented

reg,

contents

X(R);

contain

Contents of R are
new PC address.
JMP

onerand

both register
R are used as

the

are

used

(177700
when

used

177717)
by

CPU.

are

valid

the

KDF1l1

05/10

15/20

35/40

ACTIVITY

PDP-11/
LSI-11

177717)

time-out when

the CPU.
Can be addressed under console operation.
Note addresses
cannot be addressed under Console for LSI-11 or
KDF1ll1.

Basic

instructions

noted

PDP-11

processor

hand-

book.
SOB,

MARK,

RTT,

SXT

ASH,

ASHC,

DIV,

MUL

XOR

instruction.

The

external

SHIFT

The

option

operation

KE1l1l-E

instructions.

KE1ll-A
the

(Expansion

provides

same

data

MUL,

Instruction

Set)

instructions MUL, DIV,
instructions are 11/45

ASH, and ASHC.
compatible.

The

stack

KEll-F

adds

instructions:

unique

FADD,

The

KEV-11

SPL

instruction

adds

FSUB,

EIS/FIS

ordered

FMUL,

DIV

and

format.

provides

These

new

floating

FDIV.

the

point

instructions.

Power fail during RESET instruction is not recognized until after the instruction is finished (70
milliseconds).
RESET instruction consists of 70
millisecond pause with INIT occurring during first
20 milliseconds,
Power

and

fail

traps

INIT of

immediately

INIT

microsecond

ends

the

REST

in progress.

occurs

instruction

A minimum

instruction

aborted.

Power fail acts the same as 11/45
(22 milliseconds
with about 300 nanoseconds minimum).
Power fail
during RESET fetch is fatal with no power down
sequence.

RESET

instruction

followed

not

recognized

consists of 10 microsecond of
microsecond pause.
Power fail

until

the

instruction

INIT
is

complete.

KDF1l1

05/10

15/20

35/40

PDP-11/

RTT

trap occurs

If TI
after

sets "T" bit, "T" bit trap
instruction following RTI.

interrupt occurs during

edged

before

interrupt

instruction

that

instruction

and

interrupt.

occurs during

the

interrupt is acknowledged

trap.

trap will

"T"

bit trap will not sequence out of WAIT
Waits

Explicit

"P"

bit.

until

sequence out of WAIT

instruction.

instruc-

interrupt.

(direct access) to PS can load
Console can also load "T" bit

reference

implicit references

(RTI,

"T"

bit.

0dd

address/nonexistent

RTT,

traps and

in-

Console cannot load

can load "T" bit.

terrupts)

references

using

the

references

using

the

stack

This is a case of double bus error
cause a HALT.
with the second error occurring in the trap serv0dd address trap not in
icing the first error.
LSI-11

0dd

F-11.

address/nonexistent

pointer cause a fatal
service,

16.

bit

Only

15.

bit

acknowle

"T"

tion.
14,

"T"

the

is set,

bit

"T"

before
13.

15/20

35/40

after

the "T" bit trap is acknowl-

has the "T" bit set,

the

05/10

acknowledged

trap

"T" bit, "T" bit
following RTI.

S ets

KRTI

immedi ately
12.

341

instruction

If RTT sets the T bit, the T bit
the instruction following RTT.

new stack

trap.

created

On bus error

in trap

0/2.

The first instruction in an interrupt routine will
not be executed if another interrupt occurs at a
higher

priority

level

than assumed

by the

first

interrupt.

The first instruction in an
guaranteed to be executed.

interrupt

service

1is

11.

KDF11

10.

LST-11

ACTIVITY

17.

General

18.

purpose

General

PDP-11/

registers

purpose

LSI-11|

KDF11 | 04 | 34 | 05/10 | 15/20 | 35/40 ] 45

registers

PSW address, 177776, not
instructions, MTPS (Move

implemented must use new
to PS) and MFPS (Move from

PS) .

19.

20.

21.

22.

23.

PSW address
mented.

implemented,

MTPS

and

PSW

and

MFPS

implemented.

level

(BR4)

address

Only

one

Four

interrupt

Stack
Stack

MTPS

interrupt

exist.

overflow

implemented.

overflow

below

400

zone

stack

yellow

0dd

address

trap

not

0dd

address

trap

implemented.

FMUL

and

FDIV

push

and

pop);

FMUL

and

FDIV

set

use R6 (one
correctly.

implicitly

Due to their execution time, EIS instructions
abort because of a device interrupt.

Due

EIS
when

EIS

their
because

execution
of

instructions
fetching

source

abort

time,

device

because

FIS

use
can

R6.

X
X

device

instructions

can

seguence

interrupt.

a DATIP

source

instructions

fetching

not

implemented.

implicitly

must

implemented.

instructions

overflow

instructions
hence

imple-

implemented.

and

abort

26.

Red

instructions
interrupt.

25.

not

exists.

levels

EIS

24,

MFPS

and

DATO

bus

operand.

DATI

bus

sequence

when

operand.

MOV

instruction

the

last memory cycle.

does

just

DATO

bus

sequence

for

PDP-11/

ACTIVITY

LSI-11

27.

MOV

instruction does

for

the

bus
If

contains
v

in mode
be

30.

PC will

sequence

memory

have

address

been

and

incremented.

nonexistent memory address
DM
i 11
4 B9 ¥4
b A2
w
be (SS9
unchanged

and

contains

2 and

DATIP and DATO bus

nonexistent

a bus error

memory

occurs,

address

will

incremented.

Same
29.

cycle.

nonexistent

occurs,

e rror

MUuO

memory

contains

error

hives

28.

last

above

but

unchanged.

If register contains an odd value in mode 2 and
bus error occurs, register will be incremented.

contains an odd value

bus

error

occurs,

will

in mode

and

unchanged.

Condition codes restored to original values after
FIS interrupt abort (EIS does not abort on 35/40).

Condition codes that are restored after EIS/FIS
interrupt
31.

abort

KEV-11

through

contents
10

occurs

If
10

codes

codes.

Op codes

the

low order

75040

using

are

user

no KEV-11l

existent

a nonIf the

address,

microcode

option

the

bits

1If the register contents are
address, a trap to 4 occurs.

present.
trap

is present,

specified

option

075377 perform a memory read

pointer.
existent

not

is present,

occurs.

210

through

217

trap

210

through

217

are

used

as maintenance

75777

trap

instruction.

33.

indeterminate.

Op codes 075040 through 075377 unconditionally
trap to 10 as reserved Op codes.

32,

are

Op codes 75040 through
reserved Op codes.

to 10

reserved

KDF1l1

05/10

15/20

35/40

ACTIVITY

PDP-11/

LSI-11

Only

KEV-11

option

through

75377 can be
microcode.
Op codes
also be used.

is present, Op codes 75040
used as escapes to user
75400 through 75777 can

Used as escapes to user microcode,
option need not be present.
If no
exists, a trap to 10 occurs.

34,

codes

170000

through

reserved

instructions.

codes

170000

floating

codes

170000

escapes

exists,

through

point

user

trap

177777

trap

KEV-11

177777

are

microcode

implemented

instructions.

through

177777

microcode.

and

user

occurs.

can

user

used

microcode

KDF11

05/10

15/20

35/40

APPENDIX

INTEGRATED

This

appendix

TTL-to-MOS

contains

driver

reference

(DIGITAL

part

bus
transceiver
(DIGITAL
part
integrated circuits are used on
D.1
The

the

and

number
19-15305-00).
the KDF11-AA processor

9643

the

2908

These
board.

two

9643
is a dual positive logic "AND" TTL-to-MOS driver.
This
has separate driver address inputs with common strobe and

accepts

standard

high-current

and
MOS
<circuits.
nomenclature.

The

for

19-16028-01)

9643

device

D.2

information

number

CIRCUITS

TTL

and

DTL

input

high-voltage

Figure

D-1

signals.

outputs

shows

Provision

made

for

levels

suitable for driving
chip
1layout
and
pin

the

2908
2908

1is
an
open-collector
bus
tranceiver
with
3-state
receivers and parity.
Figure D-2 shows
the terminal connection
diagram and defines the functional terms.
Figure D-3 is the logic
diagram and Figure D-4 is the associated truth table.
Table D-1
lists the parity output functions.

INAE

] vees

E[3:

—_;_] OuT A

INBE

D—— ] vee2

GNDE

—:] ouUT B

MR 2925

Diagram

Output

o »

& o

0odd
0dd

L
H

Output

—

Parity

3 2

O0dd

Functions

Parity

2908

Connection

D-1

9643

Table

D-1

|@)

Figure

(N~

)

(m [ Ree

vee [

(20

@ []ro

DRCP [

(19)

3 [] Ao

R3 :‘

(18)

(4[] 8uso

A3 _7_‘_]

(17)

(5) [ onos

BUsz [ ] (16)

GND2 [] (18)

@ [ A

BUS2 [ ] (14)

® [ R

A2 [] 03

(9 [ 8€

R2 ]

(10)
[] ooo

OE ]

NOTE:

(12)

Pin 1 is Marked for Orientation Purposes. Numbers in { ) Denote Terminal Numbers.

LEGEND:

Bus Enable. When the Bus Enable is LOW, the Four Drivers are in the

BE:

High Impedance State.

BUSq BUS, BUS, BUS3:
'
'
'
DRCP:

The Four Driver Outputs and Receiver Inputs (Data
is Inverted).

Driver Clock Pulse. Clock Pulse for the Driver Register.

Odd Parity Output. Generates Parity With the Driver Enabled, Checks

ODD:

Parity With the Driver in the High-Impedance State.

Output Enable. When the OE Input is HIGH, the Four Three-State Recciver

OE:

Outputs are in the High-impedance State.

Ro R4

"
RLE:

Ro R3 :

The Four Receiver Qutputs. Data From the Bus is Inverted

While Data From the A or B Inputs is Noninverted.

Receiver Latch Enable. When RLE is LOW, Data on the BUS Inputs is

Passed Through the Receiver Latches. When RLE is HIGH, the Receiver

Latches are Closed and Will Retain the Data Independent of all Other

Inputs.
M1:-2926

Figure

and

D-2

2908

Connection

Definition of

Functional

D-2

Diagram,

Terms

Aoo—D

[

D Q

BUSy

BUS;

{ f

D Q

— CP

A1 o—{> [

D of—
D

11 f

{>—- DQ

DQ 2
D

O OF conTROL
~——

OUTPUT

—{ ii

%—D Q

A3O———i >

<}3

Ccp

L cp

A2 O—-> I

w3
w

BUSg

—_)

PARITY

DRIVER

)

CLOCK

DRCP

BUS
ENABLE

BE O—

fiJ:{>—

%<}

O RLE

RECEIVER

LATCH

ENABLE
MR.2927

Figure

D-3

2908

Logic

Diagram

INPUTS
A

ITI\(I)TSS\'\/IQLE BUS | OUTPUT
:

|DRcP | BE|RLE | OE | D;

FUNCTION

DRIVER OUTPUT DISABLE

| x

RECEIVER OUTPUT DISABLE

HooL

DRIVER OUTPUT DISABLE AND

| H

[NC

| x

< |

| x

X |

NC|x

| x

X |

NC|[x

| X

RECEIVE DATA VIA BUS INPUT
LATCH RECEIVED DATA

LOAD DRIVER REGISTER

NO DRIVER CLOCK RESTRICTIONS

DRIVE BUS

H=HIGH

L= LOW

Z=HIGH IMPEDANCE

NC = NO CHANGE

X = DON'T CARE

i=0,1,2
3

= LOW-TO-HIGH TRANSITION
MR.2928

Figure

D-4

2908

D-4

Truth

Table

BOOTSTRAP PROGRAMS

E.1

RXV11 BOOTSTRAPS

APPENDIX

Axo)

Full Length Version

Abbreviated Version

(DRIVE 0 ONLY):

@1000/000000 12702 <LF>

@1000/000000 5000 <LF>

001002/000000 1002n7 <LF>*

001002/000000 12701 <LF>

001004/000000 12701 <LF>

001004/000000 177170 <LF>

001006/000000 177170 <LF>

001006/000000 105711 <LF>

001010/000000 130211 <LF>

001010/000000 1776 <LF>

001012/000000 1776 <LF>

001012/000000 12711 <LF>

001014/000000 112703 <LF>

001014/000000 3 <LF>

001016/000000 7 <LF>

001016/000000 5711 <LF>

001020/000000 10100 <LF>

001020/000000 1776 <LF>

001022/000000 10220 <LF>

001022/000000 100405 <LF>

001024/000000 402 <LF>

001024/000000 105711 <LF>

001026/000000 12710 <LF>

001026/000000 100004 <LF>

001030/000000 1 <LF>

001030/000000 116120 <LF>

001032/000000 6203 <LF>

001032/000000 2 <LF>

001034/000000 103402 <LF>

001034/000000 770 <LF>

001036/000000 112711 <LF>

001036/000000 0 <LF>

001040/000000 111023 (LF)

001040/000000 5007 <CR>

001042/000000 30211 <LF>
001044/000000 1776 <LF>
001046/000000 100756 <LF>
001050/000000 103766 <LF>
001052/000000 105711 <LF>

001054/000000 100771 <LF>
001056/000000 5000 <LF>
001060/000000 22710 <LF>

001062/000000 240 <LF>

*n =4 for Unit O

001064/000000 1347 <LF>

n =6 for Unit 1

001066/000000 122702 <LF>

<LF> = Line Feed

001070/000000 247 <LF>

< CF> = Carriage Return

001072/000000 5500 < LF>

Starting address — 1000

001074/000000 5007 <CR>

(CONSOLE ENTRY)

E.2

RKV11 BOOTSTRAP (Drive 0 only)

(terminal response underlined)
START

@001000/000000 6<LF>

001002/000000 10061 <LF>
001004/000000 6<LF>
001006/000000 12761 <LF>
001010/000000 177400<LF>

001012/000000 2<LF>
001014/000000 12711 <LF>

001016/000000 5<LF>
001020/000000 105711 <LF>

001022/000000 100376 <LF>
001024/000000 5007 <LF>

001026/000000 O<CR>
@RO/XXXXXX O<LF>
R1/XXXXXX 177404<CR>

APPENDIX

ODT

number

of differences

and
console
ODT
for
these differences.

exist

the

between

KDll-F.

console ODT

The

following

for

DIFFERENCES

the

1list

KDF1l1l-AA
describes

KD11-F

All

characters

when in
echoed.

the
An

that

are

KDF11-AA

input

APT command
echoed line

mode
feed

are

echoed

except

where no characters are
<LF> will be followed

by a carriage return <CR> only (no second <LF> or
padding nulls).
This method creates a potential

timing problem with a TTY ASR33
character before the print head

which types the
has completely

All

characters

the

APT

mode,

are

echoed

12,

200,

202,

210,

and

fand

nulls

<CR>

and

that

(0),

LF>

are

STXs

are

address

location

<LF>

212.
1In

except

(2),

follow.

characters

input

any

the

This

BSx
the

suppresses

(10)]
APT

command mode,
octal codes 0,

because

command

except
2, 10,

echoing

LFs

automatic

mode,

input

echoed.

returned.
When

address

location

open,

another

can be opened without explicitly closing
location, e.g., 1000/123456 2000/054321.

nrn

will

open

the

n@n

will

open

location

using

indirect

"€"

will

open

location

using

relative

"M"

will

Rubout

(ASCII

"L"

the

absolute

the
177)

boot

format.

delete

last

loader

command

which

command

mode

(ASCII

and

dumps

16-bit
The

address

input

10.

Up to a
Leading

11.

Incrementing (LF)
address 000000.

bytes

are

16-bit
0Os are

address and
assigned.

closed

opened

else

<CR>

error

automatically

"?",

<CR>,

<LF>,

"@"

addressing.

"@"

illegal

and

micro-ODT

prints

"?",

<CR>,

<LF>,

"@"

addressing.

"?"

illegal

and

micro-ODT

prints

"?",

<CR>,

<LF>,

"e"

"M"

illegal

and micro-ODT

prints

"?",

<CR>,

<LF>,

"@e"

CPU

character

will

23)

not

the

16-bit

address

load

typed

the

in.

Rubout

"L"

illegal

accepts

bytes

binary

illegal

and

micro-ODT

echoed.

Control-Shift-S command
bytes forming an 18-bit
always

data may

177776

results

entered.

the

input

prints

"?",

<CR>,

<LF>,

"@"

0Os

page

the

address

from

prints

out

"R8"

Incrementing
777776

17XXXX.

dumps

are

the

(LF)

result

not

bytes

the
in

binary

format.

The

echoed.
and

16-bit

addresses
the

data

177776,

addresses

may

entered.

377776,

000000,

577776

200000,

angd 600000 respectively, i.e., the upper 2
18-bit address are not affected; they must

bits
be

set.

Incrementing

and

group

and

bytes

mode (ASCII 23) accepts 2
address with bits <17:15>

Up to an 18-bit address
Leading 0s are assumed.

and

Incrementing a PDP-11 register
and the contents of RO.
10

and micro-ODT prints

explicitly

The

explicitly

illegal

400000
of the

13.

another

12.

must

before

"T"

internal

the

command

(?) will occur and any open location will
be closed without altering its contents.

location.

contents
will

first

loader.

Control-shift-S

forming

location
the

PDP-11

contents

from

prints

out

RO.

The 10 page is in the address groupt 77XXXX where
address bits <17:12> must be explicitly ls.

"RO"

"@"

KD11-F

14.

The micro-ODT mode

KDF11-AA

can be

entered

from

the

following

The micro-ODT mode

sources:

15.

A PDP-11

A double

A power

HALT

bus

asserted

instruction.

error.
HALT

line.

up option.

asserted

HALT

line

caused

bus

error.

A micro-ODT

A memory

h.
i.

An interrupt vector time-out.
A nonexistent micro-PC address.

carriage

can

entered

from

the

following

sources:

refresh

return

line feed <LF>.

bus

<CR>

a DLV1l

framing

error.|

A PDP-11
the POKL
strap is

HALT
line

instruction when in
is low and the HALT

kernel
jumper

mode,
option

DLV11l

framing

present.

asserted

A micro-ODT

power-up

asserted

HALT

line.

option.

HALT

line

bus

error.

caused

error.

echoed

and

followed

just

carriage

return

<CR>.

<CR> and line feed <LF>.

echoed

and

followed

another

APPENDIX

KD11-F/KD11-HA/KDF11-AA DETAILED COMPARISON
The

KDF1ll-A

for
and

future
expansion
to
implement 18-bit addressing
(two lines)
4-level interrupts (three lines).
1In addition, the processor

module

uses

five

bused

spare

lines

that

were

reserved

uses several of
the SSPARE lines for test points or
for control
functions
required
during
manufacturing
testing
of
the
boards.
These lines should not cause users any problems unless they have
inadvertently bused
user
signals
across
the
backplane
on
these
pins.
For a backplane pin assignment comparison, see Table G-1.
The

KDF11l-AA

uses

than either the
listed in Table

the LSI-11
bus closer
to
its
specified
limits
KD1l1l-F or KDll-HA.
These bus timing differences,

G-2, should have no effect on any user of LSI-11
peripherals or memories since a safety margin still exists between
actual times and bus limits.

Table

*Even

they

G-1

Backplane

Pin Assignment

Backplane
Line | Name

KDF11-AA

AAl

BSPARE1

BIRQSL

Reserved*

AB1

BSPARE?2

BIRQ6L

Reserved*

BP1

BSPARE®

BIRQ7L

Reserved*

ACl
AD1

BAD16
BAD17

BDALl6L
BDAL17L

Reserved*
Reserved*

AE1

SSPARE1

Single

AF1

SSPARE 2

SRUNL

KD11-F

Reserved*

Reserved*
Reserved*
STOP L
SRUNL

Not
Not

Used
Used

SRUNL
MTOEL

Not
Not

Used
Used

GND
Not

Used

BREFL
Not Used

Not
Not

Used+
Used

SCLK3H

AH1

SSPARE3

SRUNL

AK1
ALl

MSPAREA
MSPAREA

Not
Not

Used

AM2

BIAKIL

MMU

STRH

AR1

BREFL

AR2

BDMGIL

Not Used+
UBMAAPL

BC1

SSPARE4

MMU

DAL18H

Not

Used

BD1
BE1

SSPARES
SSPAREG6

MMU

DAL19H

Not

Used

SWMIB18H

MMU

DALZ20H

Used
Used

SWMIB19H
SWMIB20H

Used

SWMIB21H

Used

BF1

SSPARE7

MMU

DALZ21H

Not
Not

BH1

SSPARES

CLK

DISL

Not

BK1

MSPAREB

Not

Used

RAM

BIAS | Not

BL1

Used

MSPAREB

Not

Used

RAM

BIAS | Not

Used

though

are

used

inactive
All

KD11-HA

Step | Not Used
SRUNL

these

bused

lines

the

are

not

used

backplane

and

expansion.
+Not

Comparison

the

state

remaining

pins

the

KDF1l1-AA
and
KDl1l-HA
but
prevent problems with older
are

identical

among

KD1ll-F

terminated

all

and

for

terminated
memories.

three

KDl1l-HA,

future

processors.

bus

the

Table

G-2

Comparison

KDll-F,

KDll-HA,

and

KDF1l1l-AA

Bus

Timing

Bus

Interval

BSYNC

- BDIN

Specification
(ns)

KD11-F
(ns)

DK11-HA
(ns)

KDF11-AA
(ns)

100

200

188

144

BSYNC L

- BDOUT L

200

300

281

288

BSYNC

- BIAK L

325

600

562

435

setup

150

300

281

180

hold time

100

108

to DIN/DCUT

200

700+400/-0 | 675+375/-0 | 225+72/-0

Address
on

time

bus

Replay

inactive

time

APPENDIX

PARITY ON THE
H.1

INTRODUCTION
appendix describes

This

the

KDF11-AA

DMA

the

method

devices,

MSV11-DE
memory
boards.
suggested which implement

and

for

reporting

parity

Two
parity

control

LSI-11

parity

errors

information

different
control
error reporting.

BUS

the

circuits

are

The first design emulates the parity registers in a (PDP-11) MS-11
memory.
This relatively complicated circuit can be tested with a
standard
parity
diagnostic
which
also
completely
exercises
the
parity
memory.
This
design
also
allows
parity
memories
and
nonparity memories to be mixed in a system.
The

second

circuit

presents

simpler

parity

controller

design.

This circuit is sufficient if mixed memories are not present,
and
there
1is
no
need
to
run
a
standard
parity
controller/memory
diagnostic.
Both

options

provide

"write

wrong

parity"

diagnostic

feature.

H.2
PARITY CONTROL AND STATUS ON THE LSI-11 BUS
BDAL<17:16>,
which are
time-multiplexed
signals
(see Chapter
4),
report
parity
errors
to
both
the
KDFll-AA
processor
and
DMA
devices,
and
control
information
to
the
MSV11-DE.
During
the
address phase of all bus cycles
(150 ns before T SYNC until 100 ns
after T SYNC), BDALK17:16> represent the two highest address bits
of an address.
the data phase

BDAL<K17:16> only have parity significance during
of a reference
(read operations:
200
ns
after
R

REPLY until 25
DOUT until
100

ns
ns

during
error

the
to

asserts

data

the

control

BDAL

the

will

1is

only

enable

BDAL<17:16>

during

used

BRPLY

and

from

status

H.3

parity

by
the

both

1is
to

report

the
to

the

data

(write
the

operation

device,

portion

wrong

parity

the

The

the

processor
will
1location
114,.

KDFll-AA

Table

sent

CONTROL

exists

*Care must be
taken to make
manner that does not violate

trapping
during

the

parity
write

to
of

(see

Chapter

data

phase

ns
the

MSV11-DE*.
of

read

this

bit

operation

10).

When

KDF11l-AA

the
bus
cycle
actual
sampling

250-300

LSI-11

parity

operation

assertion
a

controller

the

phase

summarizes

test

abort
The

done

H-1

the

parity)

data

a
PDP-11
Unibus
MOS
emulate
this
memory

diagnostic

and

KDF11l-AA.

during

memory.

PARITY

read

DMA

asserted

information

MS-11

The
MS-11
desirable

processor

read
operation,
immediately
trap

BDAL<17:16>

of
the

controller

are

100 ns before T
asserts BDAL 16

information

parity

T DIN;
write operation:
T DOUT).
The MSV11-DE

portion

KDF11-AA

BDAL

send

after
after

after

and
of

receiving

parity

control

Bus.

EMULATION

memory
with
parity.
since
a
comprehensive

the

memory

sure
that
LSI-11 Bus

and

DAL
16
timing.

1is

parity

It
is
MS-11

control

asserted

logic.
The diagnostic
can
be
nonparity memory.
In this case,
in each nonparity memory bank.

Table H-1
on

run
the

in
a
system
that
parity subtests are

Parity Control

and Status

the

(Data

LSI-11

Bus

Write Operation

From

Function

MSV11-DE

Parity error
Parity
status for KDF1ll-AA | controller

BDAL

Information

Phase)

Read Operation

BDAL

contains
bypassed

From

Function
Write wrong
parity on

DMA devices.

Parity
Enable KDF11l-AA
controller | parity trap

MSV11-DE

No MSV11-DE
function

through location
114,
(if bus

masger).

Each MS-11 memory contains 8K words of memory and a parity control
register.
There
can
be
a maximum of
128K words of memory;
therefore, a system can have 16 parity control registers.
Each
register

has

the

format

shown

Figure

H-1.

15
1

]

WRITE WRONG PARITY ——J

|—- PARITY ERROR FLAG

ENABLE PARITY TRAPS
MR

Figure

These

number

registers
selects

H-1

respond

the

Parity

control

Control

addresses

2R72)

Format

The

772100-772136.

8K bank

The following functionality is designed into the LSI-11 Bus MS-11
parity circuit.
When a parity error is detected, the parity error
flag
is set in the control register that controls the bank of

memory

during

which

the

parity

error

occurred.

This

bit

can

only

cleared by writing a 0.
If the enable parity trap bit is set in
the selected control register when the error is detected, BDAL 17
is asserted by the circuit.
This causes the KDF1l1l-AA to trap.
If
bit 2
(write wrong parity)
1is enabled in the selected register
write

operation,

BDAL

will

asserted

the

LSI-11

Bus

and

wrong

parity

will

memory

address

that

caused

the

shown

set

the

parity

MSV11-DE.

error

indication

can

be obtained
by looking at the address pushed onto the stack during the trap.
The
address
on
the
stack will
point
to
the
instruction or data
reference that caused the error.

control

in Figure
registers.

the

RAM
the

H-2,

a 16 X 4 RAM is used to
major portion of the logic

power-up, and
LSI-11 bus.
Once

sequences

count,

writes

this

process,

each

4-bit

every

involved

any

every

memory

the

parity

control

accessed.

This

causes

Address

into

the

used

time

(Init

Control).

Following

a bus reset
(BINIT)
initialization is started,

the

counter

store

the

RAM

cycle.

selected

1is

through

switched

clear

issued

the

logic

pausing

cells

addressing

(772100

and,

RAM

explicitly

Explicit

registers

DAL<4:1>

Generation)

parity

the

(Init

implicitly

occurs

when

772136)

are

RAM

address

(Implicit/Explicit
RAM
Address
MUX)
and
DAL<1S5,
2,
0>
to
be
directed to the RAM input
(CSR 15 MUX).
The logic detects this
mode
(Explicit
Address
Detection)
by
examining
the
LSI-11
bus
address

memory

lines,

bank

selected

not

BBS7

memory

either

contains

and

switches

parity

parity,

which

nonparity

the

generated.

mark

each

memory.

explicit

word

the

addressing

mode

Implicit

cycles
(nonexplicit)
connect
address
bits<17:14>
(Implicit/Explicit RAM Address MUX)
to the RAM.
This selects the
parity control register which controls the addressed memory.
In
an implicit read cycle, bit 15 of the register is flagged with an
error
if
the
selected memory has
previously been marked
with
an
error,
or
if DAL 16
of the current cycle
signals a parity error
(CSR

MUX).

DAL<17:16>

are

the

previously

manner

asserted

when

appropriate

(DAL<17:16>

Drivers)

described.

H.4

SIMPLE PARITY CONTROLLER (Figure H-3)
This
circuit
is
a
simplified
version
of
the
circuit
shown
in
Figure H-2.
The 16 X 4 RAM is replaced by a simple latch.
This
eliminates all the RAM initialization circuitry (Init Control and

Init Address Generation).
The explicit addresses of the registers
do
not
have
to
be
decoded.
This
reduces
the
complexity
by
simplifying the decode logic and eliminating the Implicit/Explicit
RAM Address MUX.
The control logic is simplified as a result.

[—

——

DAL 16

—_—

| DIN

MuX

| |

CSR 15

DAL <02.00> > Dy 1674

DAL ADR <17:14>>\
MUX

! I
|

DAL ADR <04:01>

COUNTER

—I_

DAL ADR < 11:05>

MUX

> DECODE

INIT
conTROL

PARITY

NONPARITY

TS> DAL ~02:00> J>

CLR

CSR 15

DAL 15

[T TTM

mMTE
!

CONTROL

BUS

|
|

conTROL |
- T = =
:

Lo
8K BANK

— ——)

|Loy|

BS7

DAL <17:16> DRIVERS

* DATA PHAEE T_I
|

—1

PARITY

TRAPS

ADR

HD BDAL 17 531555&]

4-BiT

WRITE

4-BIT

L | |— d L
r—

CSR
>

MD Q

D gyt

l |GENERATION

|ADR MUX

CSH 00

PARITY

RAM

II-I-NIT ADDRESS

EXPLICIT RAM!

CSRO2

—
S

rIMPLICIT/

WRITE 1
> BPALTE \ronG|
|

DIN
| DpaTAPHASE

CSR 15 MUX-'
I

—
——

. - J

SELECT

| EXPLICIT ADDRESSING

DAL- 17.00

BDAL - 17:00

DECODING

BUS CONTROL

e —

—

— »

TS
MR

Figure

H-2

LSI-11

Bus MS-11

Emulation

DB 7§

—»D

DAL 15

___—’

MUX

CSR 1 15

DAL 15

S —

F__7§__j

|
|

DAL <02:00>
DAL 15

Lol D

CSR 15

CLR

WRONG

PARITY

|
|

TRAPS

PARITY

CSR 02
BDAL 17

ENABLE

CSR 00

—

LATCH

WRITE

DAL <17:16>

——

TS>

DRIVERS

—_——

DAL <02:00>

—

[}

D
|28BIT

BDAL
16

DATA PHASE

CLR

)

suscontror | CONTROL
waten
|I

on
T
DIN

CSR 15 MUX

DAL 16

I LAl
DIN

|e|

I BUS CONTROL

DAL ADR <11:05>

> DECODE

| EXPLICIT ADDRESSING
DECODING

|
|

BDAL <17:00>

DAL <17:00>

BUS CONTROL
e — - — — »

TS
MR 2879

Figure H-3

Simple Parity Cohtroller

KDF11-AA USER’S GUIDE

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