KDF11-AA User's Guide

This "KDF11-AA USER'S GUIDE" is a comprehensive technical manual describing the KDF11-AA processor, a 16-bit, high-performance microprocessor developed by Digital Equipment Corporation. It forms the core of the LSI-11/23 processor and is designed to be software-compatible with the PDP-11 family.

The document covers the following key areas:

1. Introduction and Specifications:

   • The KDF11-AA (M8186) utilizes MOS/LSI technology, offering full PDP-11/34 functionality.
   • It features a standard Memory Management Unit (MMU) for 128K words of protected, multiuser program space (extending beyond older LSI-11's 32K limit) and supports an optional Floating Point (KEF11-A) for accelerated floating-point operations.
   • Key features include a 4-level vectored interrupt system, parity checking on the LSI-11 bus, over 400 instructions, 16-bit word or 8-bit byte addressable locations, 8 internal general-purpose registers (R6 as Stack Pointer, R7 as Program Counter), stack processing, asynchronous bus operation, Direct Memory Access (DMA), and power fail/restart protection.

2. Installation:

   • Details jumper configurations for user-selectable features (e.g., master clock, power-up mode, halt/trap options).
   • Provides information on compatible LSI-11 bus backplanes (H9270, H9273-A, H9281, DDV11-B) and module contact identification.
   • Highlights minor system differences compared to older LSI-11 (KD11-F) and LSI-11/2 (KD11-HA) processors, such as the absence of a microcode boot loader, different Console ODT functions, and lack of on-board memory refresh by the KDF11-AA.

3. Console ODT (Octal Debugging Technique):

   • Explains the Console ODT, a microcode-based debugger accessed via a terminal, used for program debugging.
   • Describes the terminal interface registers (Receiver/Transmitter Control/Status Registers and Buffer Registers).
   • Outlines ODT operation, entry conditions (HALT instruction, BHALT L signal, power-up modes), input/output sequences, and available commands (e.g., Slash for displaying contents, Carriage Return/Line Feed for navigation, $ or R for registers, S for Processor Status Word, G for Go, P for Proceed).

4. LSI-11 Bus:

   • Describes the 38-line bidirectional bus, its asynchronous nature, and master/slave communication.
   • Details various data transfer bus cycles (DATI, DATO, DATOB, DATIO, DATIOB) and their protocols.
   • Explains Direct Memory Access (DMA) arbitration, grant signals (BDMGO L, BDMR L, BSACK L), and latency.
   • Covers the 4-level interrupt system, including device priority schemes (distributed and position-defined) and the interrupt protocol.
   • Provides bus electrical characteristics (signal levels, loading, termination) and control functions (Memory Refresh, Halt, Initialize, Power Status).

5. Processor Functional Description:

   • Explains the roles of the three main chips: Data Chip (DC302), Control Chip (DC303), and MMU Chip (DC304), and their internal communication via the Data-Address Lines (DAL) and Microinstruction Bus (MIB).
   • Details the clock generator circuitry, including normal, stutter, stop, memory management, and reset cycles.

6. Addressing Modes and Instruction Set:

   • Illustrates various addressing modes (Register, Autoincrement, Autodecrement, Index, and their deferred versions) for operands, along with specific uses of the Program Counter (PC) for position-independent code (Immediate, Absolute, Relative, Relative Deferred).
   • Outlines the KDF11-AA's extensive instruction set (over 400 instructions), categorized into single-operand, double-operand, and program control instructions, detailing their formats and how they affect condition codes.

7. Memory Management (Detailed):

   • Elaborates on how the MMU maps 16-bit virtual addresses to 18-bit physical addresses.
   • Covers kernel and user modes, memory protection features (inaccessible memory, read-only memory, multiple address spaces), and the Page Address Register (PAR) and Page Descriptor Register (PDR) for page relocation, expansion, and tracking.
   • Details how interrupts and traps are processed within the memory management context.

8. Floating Point (Optional, Detailed):

   • Describes single and double precision floating-point data formats, including concepts like biased exponents, hidden bits, floating-point zero, and undefined variables.
   • Details the Floating Point Status Register (FPS) for mode control, error flags, and interrupt handling for various floating-point exceptions (overflow, underflow, divide by zero, etc.).
   • Lists all specific floating-point instructions.

9. Programming Techniques:

   • Provides guidance on writing efficient software, including techniques for position-independent code (PIC).
   • Explains stack usage for temporary data storage, subroutine linkage, and interrupt handling, emphasizing nesting, reentrancy, coroutines, and recursion.
   • Discusses processor traps (Memory Management Violation, Timeout, Parity, Stack Overflow, Power Fail, Interrupt Levels) and their handling.
   • Covers programming peripherals by treating device registers as memory locations.
   • Includes examples of conversion routines and looping techniques.

The appendices offer summary information on KDF11 instructions, instruction timing data, detailed comparisons between KDF11-AA and other PDP-11 models, and information on integrated circuits.