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Document:	KDB50 Disk Controller User Guide
Order Number:	EK-KDB50-UG
Revision:	PRE
Pages:	88
Original Filename:

OCR Text

EK—-KDB50—-UG—-PRE

KDB5O

Disk Controller
User Guide

EK-KDB56-UG-PRE

PRELIMINARY

EDITION

KDB50

DISK

CONTROLLER

USER GUIDE

Digital

Equipment

Colorado

Springs,

Corporation
Colorado

Preliminary

by Digital

Edition,

July

1985

Equipment Corporation

Printed in U.S.A.
All Rights Reserved

The material in this manual is for informational purposes and
subject

change

without

notice.

assumes

DIGITAL

responsibility for any errors which may appear in this manual.

1is

make,
to
licenses
Digital Equipment Corporation does not grant
no
makes
and
manual,
this
in
described
as
sell equipment
or
use
manufacturers
other
of
those
with
claim that use of its products
will not infringe on existing or future patent rights.
This equipment generates,

uses,

and

may

emit

radio

frequency

has been tested and found to comply with the limits
It
energy.
15
Part
for a Class A computing device pursuant to Subpart J of
this
1If
environment.
commercial
of FCC rules for operation in a
equipment is operated in a residential area, the user, at his own
expense,

may be required to take corrective measures.

The following are trademarks of
Maynard,

Digital

Equipment

Massachusetts:

DEC
DECUS
HSC50

DECnet
DECsystem-10
DECSYSTEM-20

RQDX
RC25
VT

PDP
UNIBUS
VAX
RA81

RA8O
RSX
MASSBUS
RA60

RSTS
UDAS(
VMS
KDAS50-Q

dilg|i[t]a]l]

DECwriter

KDB50

Corporation,

CONTENTS

Control

KDB5@
-

¢«

Module

.«

¢«

Stream

1-18

1-19

MICROCODE

Stream

Control

SPECIFICATIONS
CUSTOMER

SERVICE

CONTRACT

OPTIONS

1-19

Hardware

Services

.«

Software

Services

&«

L ]

.«

FUNCTIONAL

Drive

(.
|
| “
NUNE I RPJAOAdWNDHH

Module

DIGITAL
N

MAOANIIT RC

VVINJI/V

PROTOCOL

Interface

Processor
BI

CONTROL

= —

SDI

e
i e

INTRODUCTION

Interface

Bus

DOCUMENTATION

o
o
o

oW N

=
*

N
N

STORAGE

Bus

KDB5@

1-20

1-21

LOGS

[]

System

Drive

Numbering

Clock
o«

VAXBI
BIIC

KDB50

.
.

¢«

INFORMATION

o
.

INFORMATION

o
«

o«

Registers

GLOSSARY

INDEX

1ii

| |IT>NN
i

.
.

Registers

Specific

.
.

Timer
o

Required
Control

CONSIDERATIONS

PROGRAMMING

REGISTERS

L]
.

PROGRAMMER

KDB5@-SPECIFIC
BIIC

Diagnostics

SOFTWARE

Error

Selftest

Subsystem

W N

Controller

b
=

KDB5@

SYSTEM AND

PROCEDURE

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= 00 00 =

Disk

KDB59

TEST

ACCEPTANCE

INSTALLATION

FIELD

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N

KDB5@

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SDI

CONTROLLER

SUBSYSTEM

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MASS

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APPENDIX

DISK

KDBS5#

KDB50

W wwww

CHAPTER

KDB5%

INFORMATION

INSTALLATION
WwwwihNhdNd
=

CHAPTER

.
L]
[
e
¢
o
o
¢
O
[}
o
[]
L}
AU BWWWNNN

GENERAL

CHAPTER

Configuration A
Configuration B

BI Module Physical Dimensions
SDI To DBUS <15:00> Datapath .
ECC Generation . « +
¢ + o o o
ECC Checking . . . . . . . .
BIIC And BCAI Configuration On

. .
. .
o o
e e
The

¢« ¢« «
. « «
o o o
o o o
KDB50

Processor

Scheme

¢
¢

o
¢

¢
¢

o
o

o
¢

o
o

o
o«

@
=

¢
«
o
o

«
«
o
o

&«
.
=
o

o«

. . . «
. . . .
Jumpers
. . .
. . .

.«
.
.

&
.
.

Bus

Format

Error Interrupt Control Register Format
.
Interrupt Destination Register Format
. .
BCI Control And Status Register Format . .
User Interface Interrupt Control Register
KDB5¢ IP Register Format . . . . . ¢« ¢« « «
KDB50 General SA Register Format . . . . .

.
.
.
¢«
.

.
.
.
.+
.

.
.
.
.
.

LED

TABLES

Error

And

Symptom Codes

¢«

Internal SDI Cable Installation
. .
External SDI Cable Installation
. .
KDB5@ Module LEDs And Revision Level
KDB5@ DTYPE Register Format
. . . .
KDB5@ BICSR Register Format
. . . .

o
.

WOJAUN
U
WWN
O

o
.

Error

KDB58 Modules
. . .
e e o s o
The KDB5@ Backplane I/O Assembly

Stream Functional D1v131on

VAXBI And SDI Control
Inserting
Attaching

¢«

Microprocessor

¢
o

¢
¢

¢
.

Module

.
.

Dual

.
.

KDB5@

Subsystem Configuration

WWWwWwWwWwwwww

|
WO-JAUNBWNRFU
L WNDEHFW

[

KDB5@

0 ~JA UV D

FIGURES

PREFACE

This

guide

KDB5#

disk

includes

This
-

detailed

gui de
these

Controller
Related

describes

how

controller.

does

equipment

¥ er

not

checkout,

intended

subjects

Manual.

for

specifications

malntenance

Service

Documentation

install,

provided
For

section

and

the

included

operate

the

first

ocLVLLLHg.

separately

further

and

equipment

1in

Chapter

and

chapter.

Information
-

the

information,

user

the

KDB5#

refer

Disk
the

CHAPTER
GENERAL

1.1

INFORMATION

KDB5¢ DISK CONTROLLER INTRODUCTION

The KDB5@# is part
of
the
Digital
Storage
family
of
1intelligent
disk
controllers.

Architecture
(DSA)
It
1interfaces
any

combination of up to four DSA disk drives to a host CPU operating
on
a
VAXBI bus.
Since the KDB5f is part of the DSA family, the
KDB58:

Handles
most
of
the
performed by the host.

Allows

the host

1I/0

view

management

the

contiguous string of error-free

disk

traditionally

suhsystem

sectors known as

one

logical

blocks.

Takes over
(cylinder,

the traditional host
track, and block).

concern of

Communicates with the host via the host
Storage Control Protocol (MSCP).

bus

disk

geometry

(VAXBI)

and

Mass

l.1.1

Communicates with
SDI

protocol.

KDB5@

SUBSYSTEM

the

disk

drives

via

the

SDI

bus

Figure 1-1 shows the basic KDB5#
subsystem
configuration.
KDB50 communicates with the disk drives using the SDI bus and
protocol.
It communicates with the host using the VAXBI bus
MSCP.

and

The
SDI
and

GENERAL

INFORMATION

CPU CABINET

< TEXr< >

HOST CPU

KDB50

PROCESSOR

MODULE

(T1002)

SDi
MODULE

(T1003)

EXTERNAL
SDI CABLES

4——————®

[

UP TO FOUR
SDI DISK

DRIVES

INTERNAL
SDI CABLES

CX-712A

Figure

1-1

1.1.2

MASS

STORAGE

MSCP
to

set

disk

driver

can

example,

disk

able

and

hosts

hides

error

replace

in a

PROTOCOL

that

communicate

are

MSCP
all

strategies,

invisible

different

supplying

with

intelligent

device-dependent

several

subsystem,

and

recovery

requirements

instead

drive

CONTROL
MSCP

geometry
these

Subsystem Configuration

rules

communicate.

Because

KDB5#

the

1-2

from

the

device

supplies

controllers

requirements,

the

host,

one

drivers.

host.

class

For

driver

for

disk

class

driver

disk

drives.

possible

SDI

each

use
such

type

that

INFORMATION

GENERAL

the

1illustrates

The following description further

function

MSCP:

the

request an I/0 operation,

constructs

host

The MSCP
message and sends it to the controller.
MSCP
be
message contains the drive address, the function to

the

performed,

amount of data

starting logical block number, and the

requested.

controller
the
When
performs
independently
movement,

as well

it
request,
the
receives
drive management and data
all
any

error

necessary

recovery.

subsystem gives status
the
completion,
command
Upon
response
MSCP
an
host
the
sending
by
information

message.

SDI Bus Interface

1.1.3

disk
the
and
KDB5¢
the
The SDI bus is the connection between
a radial bus, it supplies a separate internal SDI
As
drive(s).
to
cable to the CPU cabinet I/0 bulkhead for each disk drive (up
The KDB5@ is electrically attached to these cable(s) by a
four).
and
separate port and services each of these ports independently
short, all communication between the
In
priority.
equal
with
communication
SDI
the
follows
drive(s)
disk
the
and
KDB59
The SDI bus and protocol:

protocol.

Provide

real-time

controller

sector

from the drive.

and

index

pulses

the

[

‘g

rovide error detection when:
[4

formatting
than
(other
transfers
data
For
the correct
verifies
<controller
the
operations),
read/write head has reached the correct disk address
before attempting

the

transfer.

controller
the
disk,
the
to
writes
data
For
(ECC) and an
Code
Correction
Error
an
generates
these
appends
It then
Error Detection Code (EDC).

During data reads from the disk,
codes to the data.
for
ECC
and
EDC
the
checks
controller
the

consistency.

For

all

receiving

control

transmission

device
for

and

data

constantly

format errors.

transmissions,
monitors

the

the
SDI

GENERAL

1.1.4
The

VAXBI

the

KDB5#

VAXBI

Bus

bus

one

Interface
a

the host
synchronous

to
all

and

system

interlocked

(Processor,

because

must

addition,

complete

the

VAXBI

13.3

Bus

arbitration,

are

time

Mbytes/second

Bus

Distributed

Slot

Standardized

interface

One

address

Worst-case

Powerup

error

data

detection

the

bandwidth

over

High

I/0).
The
system
clocks

which
provide
synchronous
VAXBI is interlocked because

before

address,

degree

two

between

and

transaction

may

features:

bus

multiplexed

connection

memory,

its

all
VAXBI
nodes)
transactions.
The

transaction

start.

synchronous

and

(distributed
operation for

INFORMATION

and

maximum.

data

transmissions

that

lines.

integrity.
and

reporting

arbitration--no

for

central

all

VAXBI

arbitrator

nodes.

required.

interchangeability.

gigabyte
to

full

and

for

designs.

capability.

master-slave-interrupt

design

type

nodes.

analysis.

requested

self-test

1.1.4.1
VAXBI System Configurations
configured
in
many different ways,
Figures
1-2
and
1-3
show
the

configurations.

all

nodes.

The VAXBI
depending on
KDB5@
in

system

may

customer
two

needs.
possible

GENERAL

HOST

INFORMATION

BACKPLANE INTERCONNECT (VAXBI)

PROCESSOR

KDBS50

MEMORY

VAXBI

COMM

ADAPTER

(SDI)

DISK
DRIVE

DISK
DRIVE
1

DISK
DRIVE

TERMINALS

CX-714A

Figure

1-2

Configuration A

GENERAL

INFORMATION

MEMORY

MEMORY INTERCONNECT (M)

PROCESSOR

MI/BI
ADAPTER

(VAXBI)

VAXBI

COMM

UP TO FOUR

SDI DISK
DRIVES

<a—

ADAFTER

KDB5O

(SDI)

o TERMINALS
|

BI/NI

(

NI)
L
—» NETWORK

ADAPTER [ETWORK

INTERCONNECT

BI/CI

(

Cl)
L
= COMPUTERS

ADAPTER I -6ypUTER

INTERCONNECT
CX—715A

Figure

l.2
Two

1-3

KDB5@
BI

(SDI)

modules

Configuration B

MODULES

modules

make

module

(T1483)

are

modules

standards.

Figure

1-4

the

and

KDB5@:

the

Processor

that

are

shows

the

sized
BI

Standard

module

Disk

(T1@62).

according

module

physical

Interface

These

European

dimensions.

GENERAL

<
-

INFORMATION

8.0in
19.32¢cm

o
b

CORNER

B
T
C

£ AT

.10/ 1IN

22.8cm

COMPONENT

SIDE

Y
CX-713A

Figure

1-4

Module

Physical

Dimensions

NOTE

Figure

1-4,

diagnostic
the

LED

required

x
=
the
indicators

VAXBI

yellow

1location
of
the
red
and * = the location of
LED

indicators.

Using circuitry on these two modules, as well as
microprogrammed
control, the KDBS5# interfaces with the VAXBI bus and the SDI bus.
The following sections describe the hardware on both the SDI
and
Processor

1.2.1
The

modules.

SDI Module
Standard
Disk

Interface

communication
the

disk

interface
drives.
Some of

are

that

it:

Contains

Generates

(SDI)
module
(T1893)
is
the
between
the KDB58 Processor module and
the characteristics of the
SDI
module

lé6k-word
parity

for

high-speed
the

RAM

buffer

data

(RAM

buffer.

data

buffer).

GENERAL

INFORMATION

Detects RAM data

Converts data between the parallel format of
the
KDB5#
internal bus (DBUS <15:0@>) and the serial format of the
SDI

bus.

Generates
for

buffer parity errors.

disk

the Reed-Solomon Error
write

Checks

the

ECC

Provides

the

Detects

pulse

Correction

Code

(ECC)

data.

for

disk

electrical
errors

read

data.

interface
the

SDI

the

SDI

bus.

1.2.1.1
RAM
Data
Buffer - The
1l6k-word
high-speed
RAM
data
buffer
increases
system performance by supplying temporary data
storage during data transfers between the disk drive, the
KDB5#,
and
the
host.
Because this buffer can store up to 41 blocks of
data, the possibility of
a
buffer-full
condition
1is
reduced.
This,
in
turn, lessens the possibility that data will be missed
due to insufficient temporary storage.
(When data is missed, the

disk
must
make
another
full
revolution to retrieve it.
This
extra revolution decreases system performance.) By
reducing
the
possibility
of
missed
data due to a buffer-full condition, the
l6k-word

high-speed

buffer

increases

system

performance.

1.2.1.2
RAM Parity Generation And Parity
Error
Detection - The
SDI
module
contains
<circuitry that generates and checks parity
for the RAM data buffer.
This ensures that
the
parity
of
the
data
read
from
the
RAM
buffer
has
not changed since it was
written.
1In turn, this ensures that single bit and massive
data
errors are detected, thus providing data integrity.

l1.2.1.3
and the

Data Conversion - Data is converted
SDI bus in the following two stages:

Between
(NRZ)

parallel

format

and

serial

between DBUS

Non-Return-to-Zero

format.

Between

serial

NRZ

format

and

serial

<15:00>

SDI

format.

Both

the

volt

parallel

and

format

@.0

transfers

transfers
The

data

serial

pattern
pulses.

Because

pulses,

the

bit

format
be

detects

pulses

with

the

Figure

1-5

and

serial

the

bits

at
is

any

the

same

device

the

various

DBUS

<15:00>.

both

the

KDB5f

SDI

stages

module

simplicity,
Figure
1-5
However, there may be up

that

any

consist

one

observes

and

the

shows
to four

data
that

KDB50

alternating

KDB5@

on the
adjacent

two

conversion

DBUS

<15:880>

Processor

only
one
ports.

port

between
is

NRZ

PARALLEL
AND

TO SDI
AND

»~|

the

SDI

PARALLEL

SDI TO

TO SERIAL

NRZ

DISK

DRIVE

(ONLY ONE

PORT SHOWN)

h———

____.

1-5

1.2.1.4

SDI

Reed-Solomon

correction

codes

performing

certain

possible

altered.

(Altered
or

ten-bit

are

<15:00>

Datapath

Error

Correction

used

<correct

mathematical

correct

problems

DBUS

portions

data

circuit

occurs

problems

symbols

For
bus.

—

SDIBUS

Figure

common

module.

MODULE

SERIAL TO

16 BITS

D
B

data

negative

format

NRZ

and

end,

M
O

U
L

(+5.0

parallel

serial

positive

Notice

SDI

TTL

polarity.

and

must

when

shows

cC
E

SDI

errors

bus

drive

SDI

use

However,

while

alternating

(disk

the

time,

designed
as

transmission

format

data.

time.

also

data

NRZ

represent

represented

receiving

other)

INFORMATION

levels

data

one

SDI

can

format

volt)

GENERAL

Code

(ECC)

errors

calculations,
of

when
are

data

block

conditions

experienced.)

representing

1-9

the

CX—716A

512

Error

data.

they

make

have

been

that
such

The

data

ECC

media

consists

and

Error

GENERAL

Detection
contains.
The

ECC

Code

code

(EDC)

word

generated

INFORMATION

bytes

and

information

checked

the

custom

block

DIGITAL

component
known
as
the
R-S GEN.
This is done for each sector
(block) of data sent and
received
from
the
disk
drive.
For
example,
before
data
goes to the disk drive, it passes through
the R-S GEN which generates a unique ECC for that block
of
data
and
stores
this ECC data with the block of data.
When the data
is subsequently read from the disk, it again
passes
though
the
R-S

GEN.

However,

this

time,

the

R-S

GEN

recalculates

the

and compares it to the ECC read from the disk.
The R-S GEN
detects
an
error
1if the recalculated ECC does not compare
the actual ECC read from the disk.
(Figure 1-6
1illustrates
generation and Figure 1-7 illustrates ECC checking.)
If

the

R-S

Processor
Processor
it

not

sent

GEN

detects

ECC

error,

the
error.
Using
corrects the data,

module

the
to

host.
the

uncorrectable
ECC
algorithm is up to

DATA FROM THE KDB50

DBUS <15:00>

1If

host,

the
and

error
the

a
if

notifies

microcode
possible,

cannot

KDB5@

the

DATA FOLLOWED

GEN

BY ECC

SDI

BUS

the

data

host

DISK

DRIVE

THE R—S GEN GENERATES AN ECC

FOR THE DATA WHICH IS GOING
TO THE DISK DRIVE.
CX-717A

Figure

1-6

ECC

Generation

KDB50

algorithm,
the
sending

error.
The
correction
capability
one 18#-bit burst per block.

R-S

then
with
ECC

before

corrected,

notifies

ECC

this

GENERAL

INFORMATION
MODULE

L
___

DISK
DRIVE

SDI

)

BUS

SDI (T1003)

DATA FOLLOWED

DATA TO THE KDB50

BY ECC

DBUS <15:00>

—

[

|
I

THE R — S GEN CALCULATES
AN

ECC FROM THE DISK DRIVE.

ECC AND THEN COMPARES THIS
CALCULATED
VALUE WITH THE

CX-718A

Figure

1-7

1.2.2

Processor

The

ECC

Processor

Checking

Module

module

(T1002)

the

control

portion

the

KDB54.

It:

Performs
two

all

Interface
Adapter

Chip

sequencers

Contains
-

and

SRV A

the

VAXBI

Backplane

the

bus

via

Interconnect

VAXBI

Chip

consisting

1Interface

(BCAI).

shared

Control
VAR "2

AV iy

l16-bit

Store

two

12-bit

ALU.

Read

Only Memory

(CROM)

for

And

BCAI

between

the

Sy 1

checking

parity

from the VAXBI

BIIC

and

with
the

microprocessor
a

parity

Preserves

interface

(BIIC)

dual

the

chips:

microprocessor

Provides

1.2.2.1

interaction

DIGITAL

Interface

Contains

the

KDB50#

custom

bus

data

back

The

VAXBI

for

the

from

CROM.

RAM

the

VAXBI

bus

and

section
describes
<15:88>.
The acronyms

the
used

RAM.

following

and

DBUS

are:

BIIC

BCI

BCAI

---

Backplane
Backplane

Backplane

Interface.

Interconnect
Interconnect

Interconnect

Interface
Chip

Chip.

Interface.

Chip

Interface

Adapter

GENERAL

The BIIC
the
BCI
provides

INFORMATION

and the BCAI provide an interface between the VAXBI bhus,
bus,
and
the
KDB5¢ DBUS and control lines.
The BIIC
the interface between the VAXBI bus
and
the
BCI
bus,

while
the
BCAI
provides the
KDB5@ DBUS and control lines.
configuration

the

interface between the BCI bus, the
Figure 1-8 shows the BIIC and BCAI
Processor module.

KDB50

INTERFAGCE

CONTROL

LOGIC

CONTROL

LINES

5CI

BUS

KDB50
DBUS
<15:00>

‘
-

BIIC

VAXBI BUS

‘

BCAl

DATAPATH

LINES
CX—719A

Figure

1-8

BIIC And

BCAI

Configuration

The

KDB5#

Processor

Module

1.2.2.1.1
BIIC Features - The
BIIC features.
The BIIC:

following

list

describes

some

the

Handles

Implements

all

Provides

flexible

Provides

address

Provides the five required
VAXBI
registers,
two
BIIC
control registers, and three KDB5@-specific registers.

Provides all connections for the VAXBI bus
clock signals and three control signals).

(except

Provides

BCI

TTL

all

aspects of

all

VAXBI

the VAXBI

command

and

arbitration protocol.

types.

convenient

decoding

and

interrupt

system.

matching.

the necessary signals

for

the

bus

two

levels.

Allows the KDB5# to read or
write
BIIC
registers
via
loopback mode which does not use the VAXBI bus datapath.
Provides
parity,

extensive
data

error

compare,

checking

protocol).

(examples

are

data

GENERAL

Performs

Permits

node

Operates

Does

affect

not

self-test

retries
a

single
the

INFORMATION

powerup

most

and

request.

transient VAXBI

+5.8

volt

VAXBI

bus

errors.

source.
when

the

BIIC

1is

powered

down.

1.2.2.1.2
BCAI
Features - The
BCAI
1is
a
DIGITAL
custom
IC
containing
a
dual-ported
register
file which acts as a buffer
file between the BIIC and the
KDB5#'s
internal
data
bus.
In
addition,
the
BCAI contains a DMA Master Port through which the
KDB5f implements the BCAI.
The DMA Master Port consists
of
two

octal-word
DMA
data
buffers;
a
command/address register with
increment capability, and a next-page frame register.
(The
DMA
data buffers are protected via byte parity.)

1.2.2.2
Dual
Microprocessor - The
dual
16-bit
microprocessor
consists
of
several
bit-slice
components.
By
1itself,
each
bit-slice component has a limited function and a narrow data path
(4-bits).
However,
when connected in parallel, they create two
12-bit sequencers and a 16-bit ALU.
Each
sequencer
provides
a
program counter, stack, and stack pointer, while the ALU provides
the arithmetic and logic capabilities.

The

two

Drive

sequencers,

known as

Processor

{DPRGC) ,

individual
For

microprograms

example,

operation,
Similarly,

while

from

the

the DPROC is
while
the

the BI

Processor

operate
CROM

BPROC

(refer
1is

scheme.

wusing

fetching its next
DPROC
1is
wusing

operation, the BPROC is fetching its next
Figure
1-9
shows
a
simplified
block

microprocessor

(BPROC)

alternately
the

Section
ALU

and

and
to

the

execute
1.2.2.3).

perform

instruction from
CROM.
the
ALU
to perform an
instruction
diagram
of

from
this

CROM.
dual

GENERAL

INFORMATION

DRIVE
PROCESSOR
(DPROC)

12 BITS ADDRESSING

SECTIoNS

SECTIONS -—

OF THE
KDB50

CROM
8K X 48 BITS

ShaRep
16

DBUS<15:00>
:

A
e

)
12 BITS ADDRESSING

Bl
PROCESSOR
(BPROC)
CX—-720A

Figure

1-9

l1.2.2.3

Control

the

BPROC

the

BPROC,

KDB5@

48-bit

CROM

the

and

parity

Microprocessor

Store

Read

and

parity.

Dual

Read

Only Memory

(ROM)

DPROC.

One

half

other

half

the

Scheme

circuit

constantly

parity

1is

not

(CROM)

containing
of

the

The

CROM

microcode

CROM

1is

the

DPROC.

monitors

the

CROM

data

the

parity

for

an
both

dedicated

odd,

1is

circuit

for

odd

assumes

corrupted
microword
has
been
accessed
and
halts
all
KDB50
operation.
The
KDB50 then flags the host of an error and stays
in a
wait
state
until
re-initialized
by
the
host.
Before
initialization
can
complete,
the
KDB5#
examines
the
entire
contents

1.3

KDB5@

the

CROM

FUNCTIONAL

The

KDB5#

microcode

control

stream

and

the

for

drive

divided

which

drive
1interface.
division of the two

errors.

MICROCODE

control

parity

manages

stream

Figure
control

into

the

which

two

functional

controller

manages

the

streams:

host

controller

1-10 illustrates the
streams in a system.

basic

The

interface,

disk

functional

GENERAL

INFORMATION

HOST

COMM
AREA

KDB50

MSCP

PORT

CLASS
DRIVER

DRIVER

VAXBI BUS

KDB50
—

BI
CONTROL
STREAM

RAM
DATA
BUFFER

CONTROL
STREAM

DRIVE

MSCP

DATA

SDI

BUFFERS

TRANSFER

DATA

g%ggggg“ND

TRANSFER

SECTOR

TO/FROM

HOST

DRIVES

>DRIVE
0
» DRI

= DR!
>DRI

CX-721A

Figure

1-16

1.3.1

The

control

BI
o

VAXBI And SDI Control

Control

Stream Functional

Division

Stream

stream:

Handles

the

transfer

Exchanges

information

packets

Validates

each

from

Executes

MSCP

the

from

commands

responses

host.

packet

immediate

the

with

the

host.

commands.

host

memory.

INFORMATION

GENERAL

Generates the KDB5#
the

response packets for transmission to

host.

Analyzes the drive packets and

performs

the

following

functions:

Decodes the logical block number
group, track, and sector (block)

Optimizes

seek

(LBN) to
cylinder,
information.

from

selection

the

outstanding

for

each

commands.
-

Allocates

data

buffer

Computes

and

stores

packet

error

space.

parameters

block

transfer.

Performs

Performs memory mapping for mapped requests.

Transfers
data
between
internal RAM data buffer.

Performs

Polls

the

ECC

error

command

detection.

the

host

and

the

KDB5@

correction.

dqueue

the

completion

each

command.

Performs

initialization.

Initiates drive control
Monitors

host

Performs

attention and

stream packet executions.

activity.

log

message

transmission

the

VAXBI

bus

host.

Performs
errors.

the appropriate

error

handler

for

GENERAL

INFORMATION

1.3.2
Drive Control Stream
drive control stream:

The

Monitors

ATTENTION

attention
has
gets the drive
status,

and

Constructs

been
status,

takes
and

from

sends

Receives

and

validates

Monitors

the

drive

N
B E

Performs

the

result

status

between
stream.
following

the

flags

tasks

disk

from

status

the

control stream
the
previous

drives.

host

request

The

condition.

packets

drive

drive
with

drive

the

from

drives.

the

flags

control

are

used

stream

and

required

the

for
the

drive

flags:

1Initiates

the

the
it

When

action.

drive-attention

The

communication
drive control

status

packets

may
to a

drives.

detected,
compares

appropriate

packets
response

stream.

the

read,

write,

seek,

and

head

block

header.

select

packets

drive.

Reads

and

Performs

data

the

drive.

disk

verifies

Updates

drive

—

Performs

bad

the

transfers

status
block

and

between

the

buffer-use

revectoring.

internal

flags.

RAM

and

GENERAL

l.4

The

KDB5@

INFORMATION

SPECIFICATIONS

KDB5@ Disk Controller

Specifications

are described

1in

Table

1-1.

Table

1-1

KDB5@ Specifications
Specifications

Characteristics
—

Physical

components

———

—

——

—

——

—

——

—

— N

KDB5@

Processor

KDB5@

SDI

——— ——

—

module

——

—

—————

—

(T1002)

(T1003)

KDB58@
backplane
I/0
assembly
(78-22492-05 (8
ft.),
- 70-22492-06
(12 f£t.))
KDB5@ I/0 bulkhead

Power
Heat

consumption
dissipation

73.6 watts

(74-31369-01)

nominal

Approximately

voltage

1.4

volts,

and

current

milliamps
at
+12.0
wvolts,
milliamps at -2.0 volts,
3.1
at -5.2 volts

300
amps

Operating
temperature

range

10%
wet
C

altitude

range

(90

Sea

(36

degrees

F/hour)

or less to 95%, with a
bulb temperature of 32
degrees

point
Operating

+5.0

5 degrees C to
50
degrees
C
(41
degrees F to 122 degrees F), with a
temperature
gradient of 20 degrees
C/hour

Operating
relative
humidity range

BTU/hour

Electrical
requirements

amps

268.8

level

Reduce

and

degrees
to

the

maximum
degrees
minimum
dew

(36 degrees

2400 meters
maximum

(8000 ft).
allowable

operating
temperature
by
1.8
degrees
C/100@
meters
(1
degree
F/1008
feet)
for
operation above
sea

level

Mounting

Mounts

restrictions

cage

box

two

H9400-AA

module

slots

GENERAL

1.5
You

DIGITAL
can

CUSTOMER

upgrade

your

maintain

optimum

following

service

1.5.1

Hardware

Add-on

and

SERVICE
CPU

CONTRACT

system

performance

efficiently

taking

advantage

get

you

started.

Physical

Maintenance
installed

services

equipment

services

keep

DIGITAL

you

field

going.

DECservice

installation

Basic

Service

providing
calls,

services

less

Call

the

strongly

suitable
site
humidity.

and

verification

well

described

but

Service,

the

has

upgraded

following

service

engineering

complex

response
solved,

changes,

full-service

second

the

preventive

for

DECservice.

reliable

Service

DIGITAL

and

problems.

economical

equally

been
system

providing

maintenance, committed
until the
problem
1is

status

Carry-In

upgrade

entire

on-site

latest
for

priority

comprehensive

Per

escalation

your

the
of

comprehensive

program
of
preventive
times, continuous effort
automatic

and

Once

service,

be eligible for coverage by one
comprehensive service contracts:

and

functionality.

will

new
CPU upgrade be installed by qualified
technicians.
1Installation includes:

connection

system

of one

Services

upgrade

full

choose

and

Pre-installation evaluation to ensure
a
environment, including power, temperature

For

OPTIONS

smoothly

options.

recommend
that
vyour
DIGITAL field service
l.

INFORMATION

only

coverage

DECservice

maintenance

service,

DECmailer

on-site

you

can

Service.

GENERAL

INFORMATION

1.5.2
Software
If your need is

develop
or
your
needs.
interest

Services
to analyze or upgrade
your
current
system,
or
implement software, DIGITAL offers a service to meet

The

you

following

you plan

services

will

add-on

upgrade:

particular

Computer Performance Service - Helps you develop
growth
plans
by
identifying
add-on or upgrade options before
problems

begin.

System Start-up Service Packages Provides
training
for your staff, as well as one year
services.

Consulting Services - Provides software
programming
project
manager
expertise
on a resident, per-call,
fixed-price

basis.

Your

fixed-cost
of support

or
or

choice.

Any DIGITAL service option you select will provide you with
high
quality,
reliable
service
from
one
of
the
largest service
organizations in the industry.
For more information,
call
your
local DIGITAL field service office.

GENERAL

1.6

DIGITAL

INFORMATION

DOCUMENTATION

customers

may

order

the

following

KDB5@

DISK

CONTROLLER

USER

KDB5¢

DISK

CONTROLLER

SERVICE

External

DIGITAL

Customers:

KDB5#

GUIDE

(EK-KDB5@-SV)

User

Manual

Guide

may

from

and

Service

ordered

directly

Digital

Equipment

Corporation,

P.0.

Box

CS206d8,

Nashua,

Hampshire

@3061,

New

or
by
calling
800-258-1714.
Internal

DIGITAL

Customers:

The

User

Manual

Guide

from
Forbes

United

States,

consult

free:

and

Service
directly

Publication

and

Services,

Road,

Massachusetts

the

toll

ordered

may

Circulation

Outside

manuals:

(EK-KDB5#-UG)

MANUAL

The

NR12,

Mail

local

DIGITAL

01532

Code:

Northboro,

(RCS

Code:

NR@3/W3).

offices.

CHAPTER

INSTALLATION

2.1

KDB5#

INSTALLATION

certain

amount

installing

the

items

that

addition

should

the

voltages,

ensure

available

voltages.

logic

the

planning

KDB5#.

SDI

and

The

preparation

following

necessary

paragraphs

before

outline

some

considered.

required
that

BI-based

the

These

cage

voltages

system
also

are

+12.80

has

required

and

-2.0

+5.0

and

power

-5.2

the

ECL

the

module.
WARNING

Before

installing

system
power
electro-static
anti-static

install
l.
2.

the

Gain

KDB5#,

make

wriststrap

sure

Also,
wear

that

the

to
ensure
either
an

heelstrap.

KDRS4:
access

Insert
same

the

is
off.
protection,

the
BI

placed

of
the
assembly.

to
two

cage

cage.

KDB5#

modules

into

(Figure

2-1).

The

the

higher

numbered

adjacent
KDB50

(or

SDI

left)

slots
module

slot

should

because

configuration
of
the
KDB58
backplane
However, the location of the two modules

be
reversed
segment with
header

the

if
the

assembly

you interchange the section C
internal SDI cables in
the
(Figure

2-2).

1I/O
can

transition
transition

INSTALLATION

SDI(T1003)MODULE

Q [:fi J

ACTUATOR
HANDLE

REMOTE

PROCESSOR

MODULE

(T1002)

SLOT 6

BI CAGE

ZERO INSERTION
FORCE CONNECTORS

NOTE:

MODULE POSITIONS ARE FOR DEMONSTRATION PURPOSES ONLY.

CX-722A

Figure

2-1

Inserting

KDB5@#

Modules

INSTALLATION

Secure

the

actuator

Ensure

that

modules

handle

that

the

Insertion

the

KDB50

Attach

closes

Force)

connectors

between

KDB5@

Later

Gain

cage

are
the

all

KDB5f

closing

module

properly

backplane

cage

using

wversions

assembly

handle

KDB5#

slot

the

remote

(Figure

2-1).

way,

inserted.

signifying

The

provide

the

backplane

I/0

ZIF

(Zero

electrical
assembly

and

modules.

the

of
the
2=-2):

the

each

modules

connection

the

for

should

access

assembly

following

the

have

the

I/O

the

KDB58

molded

the

backplane

procedure

(Figure

backplane

I/0

cables.

backplane.
NOTE

Choose

unique

node

system

set

plugs.

plug

the

area

that

KDB5@

Processor

Remove

the

dust

covers

Attach

the

keyed

KDB58

backplane
module

sections

from
this

corresponds

module

plug

Insert

vyour

node

the

slot.

from

the

backplane

that

backplane.

I/0

assembly

«correspond

the

slots.
CAUTION

ensure

evenly,

that
only

(29-27381-003)

Tighten

each

all
use

screws
the

provided

are

torque

with

2-3

tightened
screwdriver

the

screw only half-way,

the

KDB58

system.

initially.

INSTALLATION

Bl CAGE

SECTIONS

)

SDI CABLES
INTERNAL

‘N
S

B CAGE

o 47

KDB50 BACKPLANE

1/0 ASSEMBLY

TRANSITION

///HEADER

ASSEMBLY

INTERNAL

SDICABLES\§

MODULE

TRANSITION TRANSITION SEGMENT

CONNECTORS

SEGMENTS

RETAINING CLIPS

(30-CONDUCTOR)
NOTE:

KDB5O I/0

BULKHEAD ASSEMBLY POSITION IS FOR

PURPOSES ONLY.

Figure

2-2

Attaching
Assembly

2-4

DEMONSTRATION

The

KDB5@

CX_723A
Backplane

I/0

INSTALLATION

Return the BI

cage to

its original

position.

Refer to your CPU user guide or installation
to determine the proper internal SDI routing.

manual

NOTE

Route

the

from

the

Attach

the

I/0

cabinet

using

power

the

SDI

cables

separately

cables.

bulkhead

following

procedure:

the

VAXBI-based

system

Bring the internal SDI cables through the opening of
one
of
the available option bulkhead panels of the
VAXBI-based

internal

system backframe.

Screw the internal SDI cables (J1 through
J4)
into
the
small
holes on either side of each port on the
I/0 bulkhead

(Figure

2-3).

You will

need

turn

two
of
the keyed internal SDI cables one-half of a
complete turn (180 degrees) to complete this task.
c.

Mount the

I/O bulkhead on

the option bulkhead panel.

Attach the keyed,
external
SDI
cables
cabinet I/0 bulkhead (Figure 2-4).

the

VAXBI

INSTALLATION

OPTIONAL
BULKHEAD

1/0 BULKHEAD

PANEL

CAPTIVE
SCREWS

MOUNTING

SCREWS

INTERNAL

SDI CABLES

INTERNAL SDI
MOUNTING

SCREWS

Figure

CX-724A

2-3

1Internal

SDI

Cable

Installation

INSTALLATION

I/0 BULKHEAD

I/0 BULKHEAD
PORT

N
EXTERNAL
SDI CABLES

CAPTIVE

SCREWS

OPTIONAL

\\\\\

BULKHEAD
PANEL

Figure

2-4

External

SDI

Cable

2-7

Installation

CX-735A

INSTALLATION

Power-up

the

system:

The

selftest

the

KDB5f

module

set
1is
activated
upon
power-up.
At
this time, two
single yellow LED indicators show the current
state
of
the
KDB54g.
Each
vyellow
LED has the same function to
enable
Figure
Check

that

after

about

2.2

The

viewing
from
different
1locations.
2-5 for the location of these LEDs.

FIELD

field

the

ten

yellow

ACCEPTANCE

acceptance

Subsystem

has

yellow

LEDs

seconds.

LEDs

not

turn

PROCEDURE

and

test

parts:

The

KDB5@

Disk

The

KDB5f

Subsystem

Controller

the

host.

turn

module

see

Section

for

the

2.2.1.

KDB5@

Disk

selftest

Diagnostics

2.2.1
KDB5@ Disk Controller Selftest
based diagnostics run upon powerup
by

on,

procedure

ROM

initialized

KDB5@

TEST

two

each

Refer

this

time,

anytime
two

the

sets

KDB5g

four

red

LED

indicators on each KDB5# module should display a cycling
pattern
in
the
LEDs.
Each
set
of
red LEDs has the same function to
enable viewing from different locations.
(Refer to
the
comment
following
Table
2-1
(*),
and
to
Figure
2-5 which shows the
location
cycling

of each
pattern

successful

set
in

KDB5f

not

display

the

LED code

selftest.

the
in

of four red
the
LEDs

cycling

Table

2-1

If,

LEDs on the KDBS5¢ modules.)
signifies
the
completion
however,

pattern
to

after

locate

the

KDB50

power

problem.

red

applied,

The
of a

LEDs

look

INSTALLATION

Table

2-1

LED

Error And

T1002

T1663

LEDs

Symptom

Error

Codes

Symptoms

Most
Likely

Failure

NOTE

LED

ON,

LED

OFF,

LED

Hex

undefined

81890

Hex

microcode

init
g

611

Hex

9100

Hex

timeout

stuck

OFF

T1002

software
T1002

software

microcode

step

Undefined

microcode

step

init

step

init

may

stuck

VAXBI

T10032

bus

host

error

inactive

B
L

101

operating

1120

11¢8

111

000

1001

19001

91606

10190

90149

9011

611

X X X X
11900

11009
X X X

test

complete

display

problem

for

KDB5@

Hex

undefined

Undefined

Hex

undefined

Undefined

wrap

Hex

4/5;

Normal

Hex

bit

set

T1002

Hex

board

one

error

T1002

Hex

board

two

error

T1063

Hex

undefined

Undefined

Hex C; Timeout error,
check error code in SA

Refer

Service

2-9

software

Manual

Many
causes

INSTALLATION

Table

2-1

(cont.)

T1002

T1003

LEDs
8 4 21

LEDs
8 421

1101

Error

Most

Likely
Failure

Hex

RAM

parity

error

T1003

Hex

ROM

parity

error

T10@2

sequencer

1101

11190

111090

111

1111

Hex

Cycling

None

pattern

Symptoms

error

T1002

problem

*
The

cycling

pattern

T1002

continues
beyond
the
start
of
the
initialization
process.
The
KDB5%
is
not

responding

the

host

CPU.

*
During a cycling pattern, LEDs begin flashing
on
the
T16062
module and then progress to the T1003 module.
The LEDs flash one
at a time, starting
at
the
LSB
(least
significant
bit)
and
progressing
through
the
MSB (most significant bit).
The flash
goes on and off for
approximately
a
quarter-second,
and
then
repeats
at
about
a seven-second rate.
However, the pattern is
executed so fast that it looks like all the LEDs are flashing
at
the same time.
The

LEDs

normally

start

the

responds to the
This
normally
software

When

two

codes

same

failure.

cycle

while

the

initialization

KDBS5f

process.

initialization and
occurs
1in
about

prepared

are

given

establish

for

the

waiting

this

for

the

host

time,

the

KDB5J

the
seven
a

<c¢ycling
pattern
stops.
seconds
1f
the system
connection with the KDB54.

same

error,

both

1indicate

the

INSTALLATION

2.2.2

KDB5#

Subsystem Diagnostics
CAUTION

The

diagnostic

printout

1identifies

the

KDB5#

software and hardware revision levels.
Determine
if the stated
revision
1levels
are
compatible.
The

1locations

jumpers

are

shown

the

hardware

Figure

2-5.

revision

level

INSTALLATION

4 RED LEDs

YELLOW LED

+ ~ 4 RED LEDs

PROCESSOR MODULE (T1002)

4321

REVISION
LEVEL

JUMPERS

(BCAI)
E9
E999

YELLOW LED

(BIIC)

4 RED LEDs

YELLOW LED

SD!I MODULE (T1003)

4 RED LEDs

4321

/DDB

g
=

YELLOW LED

REVISION

LEVEL
JUMPERS

Figure

2-5

KDB5f Module LEDs And

CX-725A

Revision

Level

Jumpers

INSTALLATION

NOTE

These

diagnostics

future

directions
Refer

that
the

descriptions

The

KDB5#

controller.

are

revisions.

are

and

the

diagnostics

diagnostic

the

KDB5f

are

paragraphs
o

vyour

program

terminal.

for

detailed

wused

describe

with

the

these

KDB59

diagnostics.

program

Disk

due

the

information.

change

documentation

other

following

displayed

software

subsystem

The

subject
Always

reports

Controller

errors,

Service

refer

Manual

(EK-KDB5g~-SV)
.

EVRLB

(KDB5@

Disk

Drive

Formatter

Utility--uses

code)

CAUTION

When

EVRLB

run,

erases

customer

data

the
disk.
EVRLB
should only be used after it
has been established that a hardware problem has
created
false
entries
in the RCT (Replacement
Control

EVRLB,

when

move

the

Table).

run,

the

FCT

will:

(factory

bad

block

control

table)

RCT

write

and

revector)

verify
as

each

necessary

sector

and

replace

(or

INSTALLATION

EVRLF

(UDAS50/KDB5@

Basic

Subsystem

Diagnostic--uses

code)

EVRLF

consists

Test

the

following

three

VAXBI

Bus

addressing

test

tests:

This test checks to make sure that
each
addressing
line
can
be
driven to both one and zero (that the
KDB50 addresses unique locations
as
each
1line
is
toggled).
The test then does large transfers to and
from memory with known patterns.
2.

Test

Disk-Resident

diagnostic

test

This

test issues a DIAGNOSE
command
to
each
disk
drive
selected
for
testing.
Each
drive
should
accept the DIAGNOSE command
and
respond.
Failure
status and all data from the disk drive will be sent
to the host for
error
reporting.
An
interactive
dialogue
allows
other
diagnostic

an operator to manually
options
available
1in

select any
the
disk

drive.

Test

Disk

function

test

This test checks out all disk functions
by the SDI.
The test will perform such
DRIVE

CLEAR,
RECALIBRATE.

READ,

All

as
defined
functions as

WRITE,
SEEK,
FORMAT,
writing and formatting will

and
only

be done on the
diagnostic
«c¢ylinders
of
the
disk
drives.
An
extensive
test
of
the
positioning
capability will be performed before
attempting
any
format
operation.
Positional verification will be
implemented before any formatting will be allowed.

EVRLG

(KDB5@

Disk

Exerciser

Test-—-uses

code)

This

exerciser will test the
disk
drives
selected
by
issuing
random
seeks
and
read/write
transfers.
Parameters can be specified to use
diagnostic
or
host

cylinders,
restrict
disk, control length

testing
of test,

to
specific areas of
and do error logging.

EVRLG will duplicate
mechanisms,
thereby
firmware.

all
the
firmware
error
thoroughly
checking out

the

recovery
the KDB5#

INSTALLATION
Before running the KDB5@ Subsystem
Diagnostics,
the
diagnostic
supervisor must be loaded and started.
If you need assistance in
this task, refer to the appropriate System Manual.
The following
Diagnostics:
DS>Load

DS>

procedure

describes

how to

load

the

KDB5#

Subsystem

EVRnn

Device
Device

type?
Link?

KDB5#
HUB

Device

Name?

DUA

(or

DUB)
NOTE

The
in

presence of B at the third character position
this
string
indicates
the
existence
of a

second

Node

The

controller.

response

that

UDAS5S#/KDAS5@3-~Q/KDB58

range

attached

15.

the BI

the VAXBI

This

value

cage backplane

for

the

node

ID plug

KDB5# Processor

module.
BR

Level

Type

in 5.

This

interrupt

1level

assigned

KDB54.
DS>

Device

type?

Device

1ink?

DUA

Device
DS>

Name?

DUAG

An RA60 must
DS>

RAnNnn

(or
(or

DUB)
DUBG®)

attached

by using

Device

type?

RAG60

Device
Device

1ink?
Name?

DJA@

DUA

(or DUB)
(or DJB@)

the

following

sequence:

the

INSTALLATION

NOTE

Notice

the

identifies
DS>Select
DS>Run

.Program:

2.3

Start)

EVRnn

the

removable.

This

how

VMS

EVRnn

VAX

nnnn

UDAS5A/KDB58

Basic

Subsystem

Diagnostic

0.0

SYSTEM AND
following

The

drive

DUA,DUAQ,DJAQ

(or

revision

instead

the

SOFTWARE
sections

CONSIDERATIONS
describe
common

system

and

software

concerns.

2.3.1
Some

System Clock Or Timer
of diagnostic and/or functional
wusage
of
a
upon
the ability of the host processor to time-out

aspects

depend

KDB5/
on

operation.

2.3.2
The

Error

KDB5#

system
include

has

Logs
the

ability

return

for
inclusion
into
specific information

attached

drives,

processor, memory,
problem sources.

other

information

an
error
log.
on the operation

parts

software)

which

the

may

system

the

These
the

operating

entries
KDB5#,

(examples

important

order

recovery
Operating
Replacement

support

the

features
System
and

error

fault

of
must

tolerant

and

the
KDB5@,
the
support
Bad

logging.

host

diagnosing

NOTE

are

may
its

error
host
Block

INSTALLATION

Some reports contained in the error log, however,
may
represent
changes in the configquration or operation of your system that are
only informational in nature and do not represent the
occurrence
of an actual error condition.
Examples of this may be:

Completion of
port

driver

further

documentation

unit

sequence

between

the

KDBS54.

to the availability
of
a
the
result
of changing a

number).

directions,

refer

the

appropriate

system

section.

2.3.3
Drive Numbering
DSA/SDI drives that can
given

initialization

the

Attention messages pertaining
disk
drive
(which
may
be
drive's

For

the

and

wunit

number

connected to the KDB5f can usually
be
ranging
from
@
to
254.
However, some

operating systems do
not
support
this
entire
range
of
unit
numbers and may only support the range @ to 7.
Consult operating
system documentation for accepted drive numbers.
Consult
drive
documentation for unit number programming instructions.
The

unit

numbers

assigned

drives

attached

KDB58

not

imply
any
priority
or
other special property:
all drives are
treated equally by the KDB5@#.
The only requirement is
to
avoid
duplicating drive unit numbers.
If these numbers are duplicated,
the KDB5f will not permit a drive to be accessed.
This situation
may be corrected by assigning unique drive numbers.
Unit numbers can usually be easily changed at the drive, although
this
is
recommended
only when the intended drive is offline to
the KDB50# (not mounted by the operating system).

CHAPTER

KDB50

3.1
All
bb

KDBS5@G-SPECIFIC PROGRAMMING
register addresses supplied
+

nn,

INFORMATION
in this chapter

20000000H

nn varies

(2800H

depending

(2000H

following

Node

the

For example, if the KDB5@ is node
Status (BICSR) register (bb + #4)

The

are

INFORMATION

the

form

where:

20000000H

PROGRAMMER

1ID)

then
the
at address:

information

necessary

Control

and

2000EQ@4H.

write

software

for

the

KDB50:

The
hh

KDB5#
+

initializing

and polling

address

|is

B2
o

be
®

The KDB5# allows
This
address

the host to
set
the
is
used
€for
both

(generated by the BIIC) and
user
(generated by the BPROC microcode

vector
address.
error
interrupts

interface
stream).

interrupts

NOTE

The vector address
configurations.

varies

with

different

system

The KDB5@d
has
a
command
1l1imit
wvalue
of
21.
This
includes 28 MSCP commands plus 1 immediate-only command.

The

KDB50

supports

only

512-byte

The

KDB5@

supports

MSCP

and

disk

UQSSP,

formats.

KDB5@

The

diagnostic

KDB50

The

are

PROGRAMMER

option

purge/poll

INFORMATION

capabilities

and

available

the

wrap.

KDB5@
supports
maintenance
to and from the KDBS5@ RAM.

read

and

maintenance

write
o

The

3.2

BIIC

The

KDB5#

supports

REGISTERS
uses 9 BIIC

last

registers

fail

log

which

packets.

are

divided

into

three

groups:
five
VAXBI-required
registers,
two
BIIC
control
registers, and
two
KDBS5#
specific
registers.
The
following
sections describe these registers as implemented on the KDB54.
NOTE

Refer

detailed

your

System

Reference

3.2.1
VAXBI Required Registers
VAXBI-required registers are the
that
any
node
needs to operate on
registers are:

The

DEVICE

CONTROL

BUS

ERROR

INTERRUPT

following

Manual

for

information.

ERROR

set

bus.

The

registers

required

(BICSR)

(BER)

CONTROL

DESTINATION

paragraphs

VAXBI

(DTYPE)

STATUS

INTERRUPT

minimum

the

describe

the

(EINTRCSR)

(INTRDES)

VAXBI-required

registers.

3.2.1.1
DTYPE - The DTYPE register (address bb + 00)
1identifies
the
type
of
node
and
1its
revision level.
The upper 16 bits
(31:16) provide
the
microcode
and
BI
module
revision
1level
information.
The
1lower 16 bits (15:00) provide the device-type
information.
Figure 3-1 shows the format of the DTYPE register.

KDB54

M CODE
REV

20 19

SDi
REV

PROGRAMMER

PROC
REV

INFORMATION

06o0o0600O0OO0OT1TOO0OODOT11T1T
KDB50 DEVICE TYPE

bb
+ 00

CX-726A

3-1

000

PFormat

0001

[&)]

[}

—
—

(=l

-—

L -

(&)

—

IR EV

DTYPE

BICSR - The VAXBI control and
status
register
(BICSR)
bb + 04) provide status and error indicators along with
ID.
Figure 3-2 shows the format of the BICSR register.

—

3.2.1.2
(address
the NODE

KDB5#

)]

Figure

Arg | D
NOPEl

bh+04

HES

SES
INIT

BROKE
STS
NRST
Uwp
HEIE
SEIE

Figure

CX-727A

3-2

KDB5@

BICSR Register

Format

3.2.1.3
BER - The bus error register (BER)
(address
bb
+
@8)
provides VAXBI transaction error status.
Unless otherwise noted,
all bits in the bus error register can be set
during
VAXBI
and
loopback
transactions.
Bits
<38:16>
are hard error bits, and
bits <2:0> are soft error bits.
Bit <3>, the User Parity
Enable
(UPEN)
bit,
1is
not
an error bit; it indicates the BIIC parity
mode.
(The BIIC contains all necessary
1logic
to
set
the
bus
error
register
bits.)
Figure
3-3
shows the format of the bus
error

KDB58

PROGRAMMER

INFORMATION

SOFT
.
HARD ERROR BITS (30:16)

—

.
|-BITS (2:0)8]

—

ERROR

>
—

e
|

ZEROS

‘T

)

NMR

bb
+ 08

—T
UPEN

MTCE

¢t

IPE

—~

CRD

MPE

NPE

CX-728A

Figure

3-3

Bus

Error

Format

3.2.1.4
EINTRCSR - The
error
interrupt
control
register
(EINTRCSR)
(address
bb
+
@C)
controls the operation of error
interrupts—--that is, error interrupts the BIIC generates when
it
detects
a
bus
error.
Figure
interrupt control register.

3-4

shows

the

format

the

error

KDB59

ZEROS

PROGRAMMER

16
LEVEL

INFORMATION

VECTOR

10
0|

bb+0OC

INTAB
INTC

‘

SENT
FORCE
CX-729A

Figure
Two

3-4

bits

HEIE

for

the host
finishes
error
the

Error
the
hard

sets
the

Interrupt

BICSR

errors,

and

HEIE
(SEIE
self-test.

interrupt

for

Control

enable

SEIE

for

BIIC-generated
soft

errors.

is
not
set)
Therefore, the

every

hard

error

Format

Jjust
KDB50

interrupts:

For

the

KDB54,

after
the
KDB59
BIIC generates an

detects

(HES

bit

set

1in

BICSR).

3.2.1.5

INTRDES

interrupts:
error (which
BPROC

- The

generates

interrupt

KDB5¢

can

generate

two

types

interrupts the BIIC generates when it detects a
sets a bit in the BER register), and interrupts
by

setting

destination

supplies
the
BI
Figure
3-5
shows

bit

node
the

the

UINTRCSR

(INTRDES)

address
format

(address

for
both
types of
of
the
interrupt

bus
the
The

10)

interrupts.
destination

After

the

KDB59

initializes
address

the

(NODE

completes

INTRDES

the

field

self-test,

the

host

the

host

node

ID).

ZEROS

INTERRUPT DESTINATION

bb+ 10
CX—730A

Figure

3-5

Interrupt Destination

3.2.2
BIIC Control Registers
two control registers give

The

control

using

over

BCI

INT

the

BIIC

<7:4>.

and

They

the

KDB50

ability

are:

Format

microcode

issue

additional

interrupts

without

KDB54

BCI

CONTROL

USER

PROGRAMMER

INTERFACE

INFORMATION

(BCICSR)

[KDB5@]

INTERRUPT

CONTROL

(UINTRCSR)

The

following

paragraphs

describe

the

BIIC

control

registers.

3.2.2.1
BCICSR - In general, the BCI control and status register
(BCICSR)
(bb + 28)
contains bits that enable or disable various
BIIC operations.
Figure 3-6 shows the format of the BCI
control

BURSTEN

[

(6]

ZEROS | bb+28

o
o

o=
o

—

N —

W =

ZEROS

IPINTR/STOP FORCE

g1 =—

o) —

status

and

——

MSEN

BDCSTEN

STOPEN
RESEN
IDENTEN
INVALEN
WINVALEN

UCSREN
BICSREN

INTREN
IPINTREN
PNXTEN

RTOEVEN
CX-731A

Figure

3-6

BCI

Control

And

Status Register

Format

3.2.2.2
UINTRCSR - The user interface interrupt control
(UINTRCSR)
(bb + 4f)
controls
and monitors interrupts
KDB50

generates.

generate
interface

The

KDB5#

sets

force

bit

interrupts.
Figure
3-7
shows
interrupt control register.

3-6

the

this

format

the

user

INTAB

INTC

SENT

and

PROGRAMMER

—

KDB58

FORCE

INFORMATION

VECTOR

0|0]

pb+40

EX VECTOR

Figure

3-7

3.2.3

KDB5#

I'ne

User

Interface

Specific

KDB50-specific

registers
KDB5@

that

specific
1.
2.

Interrupt

registers

INITIALIZING
AND

Control

Registers
registers

implement

STATUS

CX-732A

AND

are

the

three

BIIC

KDB58

1IP and

(IP)

general-purpose

registers.

The

are:
POLLING

(GPR#)

ADDRESS

(SA)

READ

(lower

word

AND ADDRESS

(SA)

WRITE

(upper

word

GPR1)

STATUS
GPR1)

The

following

3.2.3.1

command

queue

paragraphs

- The
by

the

host

and
for

the
KDBS5#
a command.

reads

mechanism
the format

informs

reading

the

and
of

host
IP

describe

the

KDB5@-specific

KDB5@

that

has

connection

specific bit definitions.
IP register.

KDB5#

NOTE

the

has

command

(address

exists, the KDB5# examines the
The IP register exists only as

the

Writing

effect.

registers.

between

the

F2).

When

the

host

host-command Jueue
a
communications

Figure

3-8

shows

KDB50
31

PROGRAMMER

INFORMATION

IP REGISTER

ZEROS

bb
+ FO

CX—733A

Figure

3-8

3.2.3.2

KDBS5@#

IP Register

Format

- The

When

and a host
perform the

the

host

reads

contains

data

and

initialization
2.

When

the

host

communicates
3.

When

the

For

the

KDB5#,

writes

reads

The

SAr

and

SAw.

one
is

SAr

host

read

only

Together,

1initialization,

information

relating

SAr

the

during

fatal

1initialization,

normal

the

KDB5@.

operation,

including

port

SAr

and

errors.

made

general

divided

(address

during

parameters

information,

32-bit

also

during

SAw

SAr

status

the

reside

process.

controller-detected

which

SAr

error

host-specific

host

contains

made

write only register (SAw).
following three functions:

into
F4)

two

16-bit

registers

purpose

BIIC

read

and

write

[viewed

from

the

(GPR1l).

sections:

host]

the

read portion of the SA register, while
SAw
(address
bb
+
F6)
[viewed
from
the host] is the write portion of the SA register.
Certain

on
the
register

bits

the

SAr

initialization
has the format

are

constant

step.
During
shown in Figure

and

normal
3-9.

not

operation,

depend

the

KDB58

16 15 14 13 12 11
SA WRITE

E|ls|s|s|s

Ri{4]|3

PROGRAMMER

|21

INFORMATION

0
INTERPRETATION

|PROC 8D

VARIES

]

—

SA READ REGISTER

Figure

3-9

bb
+ F4

KDBS5# General

SA Register

CX—734A

Format

—

The data portion of the SAr register
(bits
@-8)
is
qualified either by the ER bit (bit 15) or by
one of the step bits (bits 11-14).
The
content

the SAr

clear

and

is unspecified

step bit

not

3-9

set.

the ER bit

APPENDIX A
GLOSSARY
N

This

glossary

DSA

describe

ABORTED

defines

terms found in many publications
that
products.
It
also
contains
terms used to
devices that interface to the VAXBI bus.

describe

COMMAND

From

the

viewpoint

the
driver has issued
of an MSCP server,
a

class

driver,

an ABORT
command

any

command

command.

From

for

the

which

viewpoint

for
which
the
server
has
received
an
ABORT
command, located the specified command,
and taken explicit action to abort it.
An
aborted
command
will be either rejected or terminated.

data

cycle

VAXBI

during

which

the

code

acknowledge

the

cycle

will

not

slave
that

read-

asserts
no

error

write-type

the

ACK

has

been

from

the

transaction

confirmation
detected

and

(CNF)

that

STALLed.

ADAPTER

A device

that

different

bus

adapts
bus

adapters

format

information

format.

because

the

tape

Sometimes

they

adapt

disk

host

information

drive

bus

controllers
bus

(STI,

are

from

SDI)

format

referred
the

host

format.

GLOSSARY

ARBITRATION

A cycle
VAXBI

CYCLE

during which

nodes

arbitrate

become

"true"

true.

Or,

for

«control

the

bus.

ASSERT

cause

signal

(asserted).

ASSERTED

Synonymous with

the

true

state.

ASSERTION

The

transition

ATTENTION

signal

from

true.

CONDITION

A status change in the drive
controller interaction.

BAD

false

significant

enough

warrant

BLOCK

block

containing

defect

that:

Exceeds the correction capability of
correction scheme.

the

subsystem error

Exceeds a drive-specified error threshold.
Once a block
not
exceeds
this
threshold,
data
integrity
is
guaranteed.

Imposes

too great

strain on

system

performance.

this
case,
the subsystem still assures data integrity,
each
but the extensive error
correction
required
for
block
access
causes
too
great
a
strain
on
system
performance.

GLOSSARY

BAD

BLOCK

Read

replacement

revectoring

occurs
of

types

Write

block.

two

upon

each

revectoring

are:

Primary

operation

The

block

Non-Primary

revectoring

when

During
to

and

access

from
block

the

ascending

the

table

rate

measured

j3))

block.

The

complexity

the

first

non-primary

not

possible.

operation

address

caching

block

replaced,

uses

revectoring

block

bad
1is

track.

subsystem

revectoring,

bad

order

revectored

current

primary

replacement

bad

the

The

non-primary

implementation

replacement

operation

Once

and

REVECTORING

Transferring
a

(replacement

block

spare

block.

Substituting

O
Q
~

REPLACEMENT
b

BLOCK

)

BAD

revectors

supplied

the

(RCT).

BANDWIDTH

The

data

transfer

transferred
second).

per

All

unit

bandwidth

into

account
overhead.

time

figures

(for
quoted

command/address

information

example,

and

units

megabytes

per

this

manual

take

imbedded

ARB

cycle

BCAI

Backplane

Interconnect

chip

that

KDB5@8

DBUS

serves
and

Chip

control

Interface

interface

Adapter

between

Interface;

the

BCI

synchronous

and

the

1lines.

BCI

Backplane

Interconnect

interface

bus

the

BIIC

and

the

that
KDB58

Chip

provides
control

Interface;

for all communication between
lines and internal data bus.

GLOSSARY

BIIC

Backplane interconnect interface chip; a chip that serves as
a general purpose interface to the VAXBI bus.

BIIC

CSR SPACE

is
The first 256 bytes of the 8-Kbyte nodespace which
.
NODESPACE
also
See
.
registers
internal
BIIC
to
allocated

BIIC-GENERATED REQUEST

A transaction request generated by the BIIC rather
the user interface (KDB5# data and control lines).
can request only error

than by
The BIIC

interrupts.

BIIC-GENERATED TRANSACTION

no
with
A transaction performed solely by the BIIC
Only INTR and
from the master port interface.
assistance
IPINTR transactions can be independently generated by the
BIIC-generated
initiates
interface
user
The
BIIC.
the user
bit,
force
OP
IPINTR/ST
the
using
by
ons
transacti
one
asserting
by
or
bits,
force
interrupt
error
or
interface
ion
transact
erated
BIIC-gen
A
lines.
L
INT<7:4>
BCI
of the
can also result from a BIIC-generated request which results
from a bus error that sets a bit in the Bus Error Register.

BIT

A binary digit
The term bit stands for Binary Digit.
Sometimes, the
# or 1.
assumes one of two possible states:
terms false and true, or deasserted and asserted, or low and
However, care must be
high are substituted for @ and 1.
For
synonymous.
always
are
terms
these
assume
to
not
taken
e
therefor
and
low",
when
"true
be
may
signal
a
example,
low
the
be
would
level
logic
physical
the
however,
asserted;
logic level usually associated with #.

GLOSSARY

BLOCK

Block

synonymous

with

sector.

block

1is

the

smallest

data
unit addressable on a subunit.
It occupies a specific
physical position relative to the index, and it is available
for
of
1.

reading
blocks

or writing

Diagnhostic
for

once

per

disk

rotation.

Five

types

follow:

drive

Block

The

diagnostic

read/write

block

diagnostics.

area

This

1is

area

used
is

not
visible to the host operating system.
However,
it
is
visible
to
the controller.
Diagnostic block addresses
are 28-bits wide and are called Diagnostic Block Numbers
(DBNs)
.

External

The

Block

external

Contains

block

area

the

format

1is

not

control

visible

tables.

the

host

operating
system.
However,
it
1is
wvisible
to
the
controller.
External
block addresses are 28-bits wide
and are called External Block Numbers (XBNs).
3.

Logical Block -- Contains the
the
replacement
and caching
are visible to
addresses
are

Numbers

(LBNs).

Physical

Block

host applications area and
table.
All logical blocks

the host operating system.
28-bits wide and are called

—--

This

category contains

Logical
Logical

all

on a subunit.
DBNs, LBNs, RBNs, and XBNs
the physical block area.
Physical block
28-bits
wide
and
are
called
Physical

the

block
Block

blocks

are subsets of
addresses
are
Block Numbers

(PBNs)
.

BUS

Replacement

reserved

block

used

Numbers

Block

Replacement
are
called

(RBNs).

LATENCY

delay

ADAPTER

See

Replacement

transaction

BUS

a bad block on a subunit.
are
28-bits
wide
and

ACCESS

The

Block

replacement
for
block
addresses

ADAPTER

from
on

the
the

time

VAXBI

bus

node
until

desires
it

perform

becomes master.

GLOSSARY

BUSY

EXTENSION

CYCLE

bus

during

cycle

master
line to

which

VAXBI

or
the slave of a
delay the start of

node,

not

necessarily

transaction, asserts the
the next transaction.

the

BSY L

the

host

such

BYTE

A group

CLASS

eight

bits.

For

example,

10010141.

DRIVER

class

that

driver

communicates

pliece

with

software

class

residing

devices,

disk

class.
The communication occurs via a port driver and
MSCP
messages.
Hosts
generally
have
a
<class driver for each
class of device:
disks, tapes, and
the
controller
itself
(for
maintenance
commands).
For
example,
a
disk class

driver can communicate with a disk subsystem
that
has
any
combination
of
SDI
disks.
Contrast
this
with a device
driver that can communicate with only one type of disk.

CLOCKS

Any

one
not

signal that supplies timing or initiates
an
action
on
or more devices can bhe considered a clock.
A clock does
have to be continuous.

Pertaining

the

SDI

bus:

The

lines
1is
imbedded within the
any data pattern (ones, Zzeros,
clock at the receiving device.

COMMAND/ADDRESS

The

first

clock

signal

for

all

the

SDI

SDI data pattern.
Therefore,
or combination)
generates
a

CYCLE

cycle

VAXBI

transaction.

The

information

transmitted
1in
this
<cycle
1is
wused
to
determine
slave
selection.
In some cases the data on the BI D<31:8> L lines
is
not
an
actual address, but it serves the same purpose:
to select the desired slave node(s).
For example, during an
INTR command a destination mask is used.

A-6

GLOSSARY

COMMAND

AND

RESPONSE

For

UNIBUS,

host

OBUS,

memory

RING
and

BUFFER
some

that

VAXBI

the

bus

controllers:

controller

and

communication.
The ring buffer points to
host memory that contains command messages
response

COMMAND

All

messages

MSCP

commands

Immediate

Non-sequential

Sequential

Special

fall

The

controller.

into

one

the

following

four

commands

command

category has

certain

thus

constraints

1limiting

the

slave(s)

scope

when

they

controller

CONFIRMATION

response

sent

CONFIRMATION

third

cycle

TIMER

Mechanisms

AND

the

VAXBI

RESPONSE

the

bus

master

transaction.

CYCLE

confirm participation

COMMAND

in
and

commands

confirm participation

COMMAND

for

location
the host

commands

may
be
executed,
optimizations.

The

area

use

categories:

COMMAND

the

the
from