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Document:	KD11-E Central Processor Maintenance Manual
Order Number:	EK-KD11E-TM
Revision:	001
Pages:	134
Original Filename:

OCR Text

KD11-E central
processor

maintenance manual

dlilgliltiall

EK-KD11E-TM-001

KD11-E central
processor

maintenance manual

digital equipment corporation - maynard, massachusetts

1st Edition, December 1976

Copyright © 1976 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.
Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

PDP
RSTS

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

TYPESET-11
UNIBUS

CONTENTS
Page

CHAPTER 1

OVERALL DESCRIPTION

CHAPTER 2

INSTRUCTION SET

2.6

2-1
e e e e e e s e e e e
INTRODUCTION . . . . o
2-1
e
e
e
e
e
ADDRESSING MODES . . . .
PDP-11/34 INSTRUCTIONS . . . . . . . .o o 2-4
INSTRUCTION EXECUTION TIME . . . . . . . . .. . ... . 2-26
. . . . . . . . . . . ..o 2-26
Basic Instruction Set Timing
. . . . . .« . o . o - 2-30
Bus Latency Times
. . . . . . . . o oo oo 2-30
EXTENDED INSTRUCTION SET
e 2-31
. . . . . . . .. e
CES
INSTRUCTION SET DIFFEREN

CHAPTER 3

CPU OPERATING SPECIFICATIONS

CHAPTER 4

DETAILED HARDWARE DESCRIPTION

2.1
2.2
2.3

2.4

2.4.1
2.4.2
2.5

4.1
4.2

4.2.1
4.2.2

4.2.3

4.2.4
4.2.5

4.2.6
4.3

4.3.1
4.3.2

4.3.3

4.3.4
4.4

4.4.1
4.4.2

4.4.3
4.5

4.5.1
4.5.2

4.5.3

4.5.3.1
4.5.3.2
4.5.3.3

4.5.3.4
4.5.3.5
4.6

4.7

e e e e 4-1
e e e e e e
INTRODUCTION . . . .
e e e e e e 4-1
e
e
DATA PATH . . . . .
General Description . . . . . . . . . Lo 4-1
. oo 4-5
Arithmetic Logic Unit (ALU) . . . . . . . .. .
e 4-7
[
...
.
. . . . . . .
Scratchpad
e e e 4-11
e
BLeg . . . .
. . . . .. . .. S 4-20
ALU Multiplexer (AMUX)
Processor Status Word . . . . . . . . . .. .. e 4-20
e e 4-24
CONDITION CODES . . . . . .. . . . .. e
Instruction Categorizing ROM . . . . . . . . . . . . ... .. ... .. 4-24
Byte Multiplexer (BYTEMUX) . . . . . . . . .. .. ... ... .. 4-24
Cand VDecode ROM . . . . . . . .. ... ... e 4-25
. . . . . . . .. .. ... ... .. . 4-25
Condition Code Signal CCZH
. . . . . ... . .. . .. .. 4-25
UNIBUS ADDRESS AND DATA INTERFACE
Unibus Drivers and Receivers . . . . . . . . .« . ..o 4-25
Unibus Address Generating Circuitry . . . . . . . . . . . . . . . . .. 4-25
Internal Address Decoder . . . . . . . . . . . oo oo L. 4-29
INSTRUCTION DECODING . . . . . . . . oo 4-29
4-29
General DeSCHPHON .« .« o o v v v e e e
Instruction Register . . . . . . . . . . oo 4-30
Instruction Decoder . . . . . . . ..o 4-30
Instruction Decoder Circuitry
Double-Operand Instructions
Single-Operand Instructions .
Branch Instructions . . . . .
Operate Instructions . . . . .

.
.
.
.
.

. .
. .
. .
. .
.e

.
.
.
.

. . . . . . o 4-30
. . . . . . . . . . .. . .. 4-31
. . . . . . . . 4-33
.. oo .. 4-34
e e e 4-34

e e 4-35
AUXILIARY ALUCONTROL . . . . . oo oo
e e e e e 4-39
DATA TRANSFER CIRCUITRY . . . . . .« o o o

CONTENTS (Cont)

4.7.1

General Description

4.7.2

Control Circuitry

---------------------------

----------------------------

4.7.2.1

Processor Clock Inhibit

4.7.2.2

Unibus Synchronization

4.7.2.3

Bus Control

----------------------

. .

4.7.2.4

M&264 NO-SACK Timeout Module

4.7.2.5

MSYN/SSYN Time-Out Circuitry

4.7.2.6

Bus Errors

4.7.2.77

Parity Errors

4.7.2.8

End of Transfer Circuitry
Data-in-Pause Transfer

4.7.2.10

Odd Address Detection
PROCESSOR CLOCK

4.10

PRIORITY ARBITRATION

. . .

Bus Requests

4.11.1

General Description
Circuit Operation

4.12

MEMORY MANAGEMENT

4.12.1.2

Programming

----------------

. .

...

. .

...

...,

...

---------------------------

Capabilities Provided by Memory Management
.

4.12.2.1

Virtual Addressing

4.12.2.2

Program Relocation

4.12.2.3

Memory Units

..o

----------------------

----------

...

-------------------------

---------------------------

................................

Inaccessible Memory

-----------------------

4.12.3.2

Read-Only Memory

4.12.3.3

Multiple Address Space

Active Page Registers

------------------------

----------------------

--------------------------

4.12.4.1

Page Address Registers (PAR)

4.12.4.2

Page Descriptor Registers
Virtual and Physical Addresses

-------------------

.....................

4.12.5.1

Construction of a Physical Address

4.12.5.2

Determining the Program Physical Address
Status Registers

4.12.6.1

Status Register O (SRO)
Status Register 2 (SR2)
Mode Description

----------------

------------

-----------------------------

4.12.6.2
4.12.7

...

Active Page Registers

4.12.6

---------------------------

4.12.1.5

4.12.5

nnnnnnnnnnnnnnnnnnnnn

Basic Addressing

4.12.4

4.12.1.3

Protection

...

-----------------

4.12.1.4

4.12.3

.. ...

---------------------------------

Introduction

4.12.3.1

----------------------------

4.12.1.1

Relocation

...............................

4.11.2

4.12.2

------------------------------

Halt Grant Requests

General

-------------------------

Nonprocessor Requests (NPRs)

4.12.1

-----------------------

4.10.1

SERVICE TRAPS

----------------------

4.10.2

4.11

---------------------

POWER FAIL/AUTO RESTART

4.9

4.10.3

-----------------------------

4.7.2.9
4.8

----------------------------

----------------------

----------------------------

CONTENTS (Cont)
Page

4.12.8

4.13

Interrupt Conditions

CONTROLSTORE

.o 4-73

. . . . . . .. ... ... FR

4.13.1

General Description

4.13.2

Branching Within Microroutines

4.13.3

Control Store Fields

..o 4—24

. . . .

. .

. . . .

. .

CHAPTER 5

MICROCODE

5.1

MICROPROGRAM FLOWS

5.2

FLOW NOTATION GLOSSARY

4-74

. .

... ... 4-74

... 4-76

5-1

. .

5-1

ILLUSTRATIONS

Title

Figure No.

|
.

. .

...

... 2-25

...

2-30

4-2

KDI11-E Block Diagram

Simplified KD11-E Data Path

. .

Page

. . .

Extended Instruction Set Number Formats
.

PDP-11 Instruction Formats

—

Addressing Mode Instruction Formats

.s
.

. .

. . . . . . . . .. ...

.. ... .....

2-2

4-3

ALU Block Diagram

. . . . . . . . . . .o ..

Scratchpad Timing

. . . . . . . . . . . . . ... ...

Scratchpad Address Multiplexer (SPAM)

. ...

....

. . . . . . . . .. e

4-9

B Leg Block Diagram

. . . . . . . . . . . . ... ... ... e

BREG Block Diagram

. . . . . . . . . . ... Lo 4-12

BX REG Block Diagram

. . . . . . . . . . . . . ... ... T 4-14

BMUX Block Diagram

. . . . . . . . . . . .o 4-15

B Leg Shift Logic

4-11

. . . . . . . . . . .o 4-17

AMUX Block Diagram

. . . . . . . . . . . . ... .. ... e 4-21

Processor Status Word

. . . . . . . . ... .. e

Byte Multiplexer
Rotate Instructions

. . . . . . . . . .. S e

e e 4-23

e e, 4-24

. . . . . . . . . . . Lo 4-26

Cand
RDecode ROM . . . . . . . . . ... .. .... e e 4-27
Unibus Transceiver
. . . . . . . . . . .
e e e 4-27
Processor Clock Cycle Timing . . . . . . . . . . . . .. [ 4-28
Unibus Address Logic Block Diagram

. . . . . . . . . . .. L 4-28

Unibus Synchronizer
. . . . . . . . . .
o 4-39
NO-SACK Timeout Module
. . . . . . . . . . . .. . . .. ... 4-47

SSYN/MSYN Control
. .
Data Transfer Multiplexer
Error Logic
. . . . . . .
End-of-Transfer Logic . .
Odd Address Detection
.

. . . . . . . o 4-43
. . . . . . . . . . . . oo 4-44
4-46
. . . . . . . . . . . . . .. 4-47
. . . . . . . . ... e 4-48
BUS AC LO and BUS DC LO Timing Diagram
. . . . . . . . . . . . . ... 4-49
Processor Clock Circuit
. . . . . . . . . . . . . ... ... e 4-51

ILLUSTRATIONS (Cont)

4-28

Priority Arbitration Synchronizer

4-29

Priority Bus Control

. . . . . . . . . . . .. ...

. . . . . . . . . . .. .o

4-30

Active Page Registers

4-31

Simplified Memory Relocation Example

. .

. . . . .

4-32

Relocation of a 32K Word Program into 124K-Word Physical Memory

4-33

Page Address Register

. .

. ..o

. . . . . . . . .. ... ... ...

. .

..o

4-34

Page Descriptor Register

4-35

Example of an Upward-Expandable Page

. . . . . . . . . . ... ... ...

. . . . . . . . . .. .. .. ...

4-36

Example of a Downward-Expandable Page

4-37

Interpretation of a Virtual Address

. . . . . . .

. .

...

4-38

Displacement Field of Virtual Address

4-39

Construction of a Physical Address

4-40

Format of Status Register O (SRO)

. . . . . . . . . . ..

4-41

Format of Status Register

2(SR2)

. . . . . . . . . ..

4-42

Control Store Fields

. . . . . . . .

5-1

KD11-E Simplified Flow Diagram

. . .

. . . . . . . . . . .. ... ...

. . . . . . . . . . . . . oo

. ...

... ..

. ...

.. ... e

. . . . . . . . . . . ... ... ... ...

TABLES
Title

Table No.

2-1

Addressing Modes

2-2

Single Operand Instructions

2-3

Double Operand Instructions

. .

. . .

. .

2-4

Program Control Instructions

2-5

Miscellaneous Instructions

. .

. . .

.. Lo

. . . . . . .

. . .

2-6

Condition Code Operators

2-7

PDP-11/34 Instruction Set

2-8

Programming Differences

3-1

Standard and Modified Unibus Pin Assignments

. . . . .

. . .
.

.. oo
..o
..o

..o
o e

.«

o oo i

. . . .

. .. .o

. . . . . . . . . . . . . . ..

4-1

Function Units of the KDI11-E DataPath

4-2

ALU Functions and Control Signals

4-3

Scratchpad Enabling Configurations and Modes

4-4

SPAM Input Data Sources

. . . . . . . . . . . ... ...e
.

. . . . . .

. . .

4-5

SPM Register Utilization

B and BX Register Enabling Configurations and Modes

4-7

BMUX Enabling Configurations and Modes

4-8

Processor Status Word Register Bit Assignments

Auxiliary Control for Binary and Unary Instructions

. . .

. .

4-10

Priority Service Order

4-11

Vector Addresses

4-12

PAR/PDR Address Assignments

4-13

Access Control Field Keys

4-14

Relating Virtual Address to PAR/PDR Set

. .

. . ... ... ...

. . . . . . . . . . . . . ... ... ...

4-6

. .

. . . . . . . . . . . ..o

. .

. . . . . . . .

. . . . . . . . . . . ..
e e

..o Lo

. . . . .
. .

. . . . . . . . . . ..
. .

. . . . . . .. ...

. .

. . . . .

. .

. . .

. . . .
. ..

. ..

. .

e e

e e e e

. . . . . . . . . . . ..

. . . . .

. . .

. . . .

. .

.. ...,

. . . . . . . . . . .. ... ...

PREFACE

This manual describes the KD11-E Central Processing Unit (M7265 and M7266). The user must have
a general knowledge of digital circuitry and a basic understanding of PDP-11 computers to completeiy
understand the contents of this manual.

The following related documents may be valuable as references:
PDP-11 Peripherals Handbook
PDP-11/34 Processor Handbook
PDP-11/34 System User’s Guide (EK-11034-OP-001)
KD 11-E Print Set (MP00043)

CHAPTER 1

OVERALL DESCRIPTION

The KDI1I1-E 1s a 2-board central processing unit (CPU) that is combined with a memory system,

Unibus terminators, and optional peripherals in a DD11-P backpanel to build a basic PDP-11/34
computer. The unit connects directly to the Unibus as a subsystem, and is capable of controlling the
time allocation of the Unibus for peripherals, performing arithmetic and logic operations, and decoding instructions. It can perform data transfers directly between 1/0O devices and memory, do both
single- and double-operand addressing, handle both 16-bit word and 8-bit byte data, and address up to
128K of Unibus address space via a memory management system.
The KDI11-E is program-compatible with both the KD11-A (PDP-11/35 and PDP-11/40 computer

systems) and the LSI-11 (with the inclusion of the two special LSI-11 instructions). It contains the
KTI11-D Memory Management System (optional with the KD11-A, not offered with the LSI-11) and
executes the Extended Instruction Set (EIS) instructions, which were optional with the KD11-A and
standard with the LSI-11. The KD11-E does not execute the Floating Instruction Set (FIS).

1-1

CHAPTER 2
INSTRUCTION SET

2.1

INTRODUCTION

The KD11-E is defined by its instruction set. The sequences of processor operations are selected
according to the instruction decoding. The following describes the PDP-11 /34 instructions and
instruction set addressing modes along with instruction set differences from those of the KD11-A,
KD11-B, and KD11-D.

2.2

ADDRESSING MODES

Data stored in memory must be accessed and manipulated. Data handling is specified by a PDP-11 /34

instruction (MOV, ADD, etc.), which usually indicates:
L.

The function (operation code)

A general-purpose register to be used when locating the source operand and/or locating the

An addressing mode (to specify how the selected register(s) is to be used)

destination operand

Because a large portion of the data handled by a computer is usually structured (in character strings, in
arrays, in lists, etc.), the PDP-11/34 has been designed to handle structured data efficiently and flex-

ibly. The general registers may be used with an instruction in any of the following ways:
L.

As accumulators. The data to be manipulated resides within the register.

As pointers. The contents of the register are the address of the operand, rather than the
operand itself.

As pointers, which automatically step through core locations. Automatically stepping for-

ward through consecutive core locations is known as autoincrement addressing; automatically stepping backward is known as autodecrement addressing. These modes are

particularly useful for processing tabular data.

As index registers. In this instance the contents of the register and the word following the
instruction are summed to produce the address of the operand. This allows easy access to
variable entries in a list.

PDP-11/34s also have instruction addressing mode combinations that facilitate temporary data storage structures for convenient handling of data which must be frequently accessed. This is known as the
“stack.”

2-1

In the PDP-11/34, any register can be used as a ‘“‘stack pointer’’ under program control; however,
certain instructions associated with subroutine linkage and interrupt service automatically use Register
6 as a “hardware stack pointer.”” For this reason, R6 is frequently referred to as the “‘SP.”
R7 is used by the processor as its program counter (PC).
Two types of instructions utilize the addressing modes: single-operand and double-operand. Figure 2-1
shows the formats of these two types of instructions. The addressing modes are listed in Table 2-1.

HHK

T
|

]

MODE

;

Y
OP CODE

H
K

Y
DESTINATION ADDRESS FIELD

#* =SPECIFIES DIRECT OR INDIRECT ADDRESS

%% =SPECIFIES HOW REGISTER WILL BE USED
s%x = SPECIFIES ONE OF 8 GENERAL PURPOSE REGISTERS

(a)
*%

[

OP CODE
|

]

MODE

|
10

(@
9

Rn
v

MODE

SOURCE ADDRESS FIELD

it
v o

|
v

DESTINATION ADDRESS FIELD

+=DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS
%= SPECIFIES HOW SELECTED REGISTERS ARE TO BE USED
*#% = SPECIFIES A

GENERAL

(b)
11-1227

Figure 2-1

Addressing Mode Instruction Formats

2-2

Table 2-1

Binary

Mode

Code

Addressing Modes

Assembler

Name

Syntax*

Function

Direct Modes

000

010

Autoincrement

(Rn)+

100

Autodecrement

-(Rn)

110

Index

X(Rn)

Value X (stored in a word following

and. Register contents incremented
after reference.

before reference register contains
address of operand.

the instruction) is added to (Rn) to
produce address of operand. Neither X nor (Rn)
is modified.

Deferred Modes

001

@Rn or (Rn)

011

Autoincrement
Deferred

@(Rn)+

Deferred

the operand, then incremented
(always by two, even for byte
instructions).

101

Autodecrement
Deferred

@—(Rn)

Register is decremented (always by
two, even for byte instructions) and
then used as a pointer to a word
containing the address of the
operand.

111

Index Deferred

@X(Rn)

2-3

Value X (stored in the memory

word following the instruction) and
(Rn) are added and the sum is used
as a pointer to a word containing
the address of the operand. Neither
X nor (Rn) is modified.

Table 2-1

Mode

Binary
Code

Addressing Modes (cont)
Assembler
Syntax*

Name

Function

PC Addressing
2

010

Immediate

Operand follows instruction.

011

Absolute

@#A

Absolute

address

instruction.

110

‘Relative

follows

Address of A, relative to the
instruction, follows the instruction.

111

Relative Deferred | @A

Address

of location

containing

address of A, relative to the instruction, follows the instruction.
* Rn = Register
X, n, A = next program counter (PC) word (constant)

NELON
-

2.3 PDP-11/34 INSTRUCTIONS
The PDP-11/34 instructions can be divided into five groups:

Single-Operand Instructions (shifts, multiple precision instructions, rotations)
Double-Operand Instructions (arithmetic and logical instructions)
Program Control Instructions (branches, subroutines, traps)
Operate Group Instructions (processor control operations)
Condition Code Operators (processor status word bit instructions)

Tables 2-2 through 2-6 list each instruction, inCluding byte instructions for the respective instruction

groups. Figure 2-2 shows the six different instruction formats of the instruction set, and the individual

instructions in each format.

2-4

9[qeL-79[SuI§pueradQsuonjoniysu]
[S1D

[StD

D198

2-5

A1018I1eQN)G

dLSL 189

aI0Yd

ddLsol

adcLsoo

qao4ds
Z N > O
=

2-6

PIpeo]YI moY}Y3y 15pI0

}1qJOdY}UOIBUISOP

2-7

p1PaqpeJoO]YWY}OHIUM]OI9M}JO}B[U-IJQ1ASoIIpSPIT0I[}O1Xq2

STUOWUIA]dOPpo)uonjeradgUONIPUO)SIPO)uonduosa(g
JjoOayJjOu2oyr3je3uyrg}-sNappue1q-O

dqeL¢-T9pP[aupre§o|pYuIerma9dyQ}s1u9opn1p0o-nYi31sYuy(3u0)
p}JH3MQu4g-Oe3NJ 1jauoJn1o3iydsws (uonjerado

2-8

C RIqEL

|}[NSAIST)9SPIBI[O"(saIppe

OddTeVUmMOgUSI2U14A]gJOA3paos)o099u1144oggne9/s11r94d1g4Q/900[N19pUI3O180N-IJMPIO]U19O9p)1I40Sq-9Yp130Iq)Y1(£qJJoOSUOOT3IURBUYTIISXOHP1P9IpIO0M-YU3OITYIRu9U1oI4rIAdSQuOpPoU)seaI(SINy9UpIIO3-QMBO]PI91OAMQJOoY}
)paIBa[d

9qeL7-78A1w7:1Pp9A8uIBeJIIr[IdO9pQI0sOu-MoOn]o9n1AsQujJO(yuo)
*9SIMI]O0

- 2-9

AONW +{dAdS10(asp)—(015)i:NJr1as(0Is)>0palead:PIOMSIAOJY}32IN0Spuelado0]aY]UOIBUISAP'UOI1BO0[

OdadQrGNieAD0NdOTdwNUoO)UIUA] aJeAdONSsYapIAz1o!T)((u00si11]p5s))“u[-+roeT~n(1+aesppr)dq N7:7A3JJIMA1p31r9SIOSaU53T[IOl3aMNMJesIsnTIdIAa9}(I}pY0[YAJnu9IN)1UsSYO00oaa]*)ll9=°S=>TSpB)IatMP("is)OepO)Pa1upo[JaeIdO1ie:eWda(dYQ[d[IdooLIE|YpU3s[JA:BBOa9uO[yYLI1re1)4qi3BgId0sAaSW(P]wn[dYISoOdU[)tI[OWBDaSIUTeNUOYDiSjOII3dNo]pYISPuS)PBO3IMRSJ"2AUUPOSIIO[9DYTBNU1[JdISO9O"NIP}30SQUy]DaNP1JImAYySeUJ3QdEAOXLuUJIBeOYUuIIWGO[Y}o}qIBAnI])UNYdOUBujOWJUIYIooS)sIgOUBSaPT0WUsgq1UIPYpO1P€uUD}SsaeBI1pYD"srP0uoISna1Jeu998dIiPIe1poU0BOo5IlS]90DdqaI"1orS1JdYe"Sao]1pUOn"d[Ou,ubqPWTeoYraIY9Jfu]lIsjOndN,1Le)993dI1js9WeaSd}0O3UuIep0yTNouM}uOnwO9S0ert[SS1eT0N
dqel;.)¢j-aUp7oOruuloepsmeaajU1yjqld)o]n3oujaSgq3dee1ImpsuoJ9deOyr}aoaJ3dsuuwQIg-etSsss3upononxs(S1u2391j1p5l4)oq-aA‘[1(143I0qSBpPXu)d9i1sS0)eUA((uQ1osIrpN)su-saal"j(xe0ar1as9)dsoimuIoay‘ls(pQiogmAQWsajeradouo
:)PjAP1uaAIeII1deeBIddjI[IWdduoJ"I1I9jS3q1I93JMYyIo]}S)3Y1yS)s}BOoM“w3B{-n3s1aSl
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2-24

Table 2-6

Condition Code Operators

Mnemonic

Op Code

Instruction

CLC
CLV
CLZ
CLN
CCC
SEC
SEV
SEZ
SEN
SCC

000241
000242
000244
000250
000257
000261
000262
000264
000270
000277

Clear condition code C.
Clear condition code V.
Clear condition code Z.
Clear condition code N.
Clear all condition code bits.
Set condition code C.
Set condition code V.
Set condition code Z.
Set condition code N.
Set all condition code bits.

NOTE
Selectable combinations of condition code bits may
be cleared or set together. The status of bit 4 controls
the way in which bits 0, 1, 2, and 3 are to be modified. If bit 4 = 1, the specified bits are set; if bit 4 =
0, the specified bits are cleared.

1. Single Operand Group (CLR,CLRB,COM,COMB,INC,INCB, DEC,DECB,NEG,NEGB, ADC,ADCB,SBC,SBCB,TST,TSTB,ROR,RORB,ROL ,ROLB,ASR,ASRSB,
ASL,ASLB, JMP, SWAB)

OP Code
l

)

Dst
|

2.Double Operand Group(BIT,BIT8,BIC,BICB,BIS,BISB,ADD,SUB)

OP Code
|

|
12

Src
|

dst
|

]

3.Program Control Group

a.Branch(all branch instructions)

[

OP Code
|

offset

]

b.Jump To Subroutine {JSR)

]

reg

]

Src/dst
|

]

c.Subroutine Return (RTS)

]

reg

d.Traps (break point, IOT,EMT,TRAP)

[

OP CODE
1

4.0Operate Groupe (HALT,WAIT,RTI,RESET)

OP CODE
|

5,(}0ndition Code Operators
(all condition code instructions)

‘ o}

0]
|

o]
|

2
|

4
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|
11-1226

Figure 2-2

PDP-11 Instruction Formats

2-25

2.4

INSTRUCTION EXECUTION TIME

The execution time for an instruction depends on the instruction itself, the modes of addressing used,
and the type of memory being referenced. In the most general case, the instruction execution time is the
sum of a source address (SRC) time, a destination address (DST) time, and an execute, fetch (EF) time.
Instr Time = SRC Time + DST Time + EF Time

Some of the instructions require only some of these times, and are so noted in Paragraph 2.4.1. All
timing information is in microseconds, unless otherwise noted. Times are typical; processor timing can
vary £10%.

2.4.1

Basic Instruction Set Timing

Table 2-7 lists the PDP-11/34 instruction set, together with the timing characteristics and memory
cycles required. The timing requirements for determining instruction execution time are listed below.
Double-Operand (all instructions)

Instr Time = SRC Time + DST Time + EF Time
Single-Operand (all instructions)

Instr Time = DST Time + EF Time

Branch, Jump, Control, Trap, and Miscellaneous (all instructions)
Instr Time = EF Time
NOTES

The times specified apply to both word and byte
instructions, whether odd or even byte.

Timing is given without regard for NPR or BR
servicing.

If the memory management is enabled, instruction execution times increase by 0.12 us for
each memory cycle used.

All timing is based on memory with the following performance characteristics:
Access Time

Cycle Time

Memory

(us)

Core
(MM11-DP)

0.510

1.1

MOS
(MS11-JP)

0.635

0.920

2-26

Table 2-7

PDP-11/34 Instruction Set

SOURCE ADDRESS TIME

Instruction

Double Operand

Source

Memory

Core

MOS

Mode

Cycles

(MM11-DP)

(MS11-JP)

0.00

1.33

1.46

2.37

2.62

1.13

1.26

1.28

1.41

2.57

2.82

2.57

2.82

3.80

4.18

DESTINATION TIME

Destination

Memory

Mode

Cycles

Core

MOS

Modifying Single-Operand

0.00

and Modifying Double-

1.62

1.74

Operand (Except MOV,

1.77

1.89
3.15

Instruction

SWAB, ROR, ROL, ASR,

2.90

ASL)

1.77

1.89

3.00

3.25

MOV

MTPS

MFPS

3.10

3.35

4.29

4.66

0.00

0.93

0.93
2.29

2.17

1.13

2.22

2.34

2.37

2.49

3.50

3.75

0.00

0.95

1.13

1.26

2.26

2.51

1.13

1.26

2.26

2.51

2.44

2.69

3.57

4.20

0.00

0.64

1.95

2.08

0.82

1.95

2.08

2.13

2.26

3.26

3.51

2-217

Table 2-7

PDP-11/34 Instruction Set (Cont)
EXECUTE, FETCH TIME
Destination

Memory

Mode

Cycles

Core

MOS

2.03

2.16

1.83

1.96

1.83

1.96

1
1
2
2

2.03
2.18
2.99
1.99

2.16
2.31
3.12
2.12

MUL
DIV (overflow)

1
1

8.82%
2.78

2.91

12.48

12.61

ASH
ASHC

1
1

4.18%**
4.18%*

4.31%*
4.31%*

MFPI(D)

3.07

3.14

MTPI(D)

3.37

3.34

Instruction
Double Operand

ADD, SUB, CMP, BIT, BIC,
BIS, XOR

MOV
Single Operand

CLR, COM, INC, DEC, ADC,
SBC, TST

SWAB, NEG
ROR, ROL, ASR, ASL
MTPS
MEFPS
EIS Instructions (use with DST times)

8.95%*

Memory Management Instructions

SWAB, ROR, ROL, ASR,

0.00

ASL

1.42

1.54

1.57

1.69

2.70

2.95

1.62

1.74

2.80

3.05

2.90

3.15

4.09

4.46

Non-modifying

0.00

Single Operand and

1.13

1.26

Double Operand

1.28

1.41

2.42

2.67

1.33

1.46

2.52

2.77

2.62

2.87

3.80

4.18

2-28

Table 2-7 PDP-11/34 Instruction Set (Cont)
EXECUTE, FETCH TIME
Destination

Mode

Memory

Instruction

Cycles

Core

MOS

MFPI(D)
MTPI(D)

0
1

0.00
0.98

0.00
1.24

2
3
4
5
6
7

1
2
1
2
2
3

1.32
2.20
1.18
2.20
2.40
3.59

1.44
2.45
1.44
2.45
2.65
3.96

2.18

2.31

1
1
1

1.63
- 2.38
1.98

1.76
2.51
2.11

Branch Instructions

BR, BNE, BEQ, (Branch)
BPL, BMI, BVC, BVS, BCC,
BCS, BGE, BLT, BGT, BLE,
BHI, BLOS, BHIS, BLO

(No Branch)
SOB (Branch)
(No Branch)

Jump Instructions

JMP

JSR

1.83

1.96
2.31
3.37
2.16
3.32

2
3
4
5

1
2
1
2

2.18
3.12
2.03
- 3.07

3.07

3.32

4.25

4.78

1
2
3
4
5
6
7

RTS
MARK
RTI, RTT
Set or Clear C, V,N, Z
HALT
WAIT
RESET
I0T, EMT, TRAP, BPT
*Add 200 ns for each bit transition in serial data from LSB to MSB.
**Add 200 ns per shift.

2-29

3.32

3.44

2
3
2
3
3
4

3.47
4.40
3.32
4.40
4.60
5.69

3.59
4.65
3.44
4.65
4.85
6.06

2
2
3
1
1
1
1
5

3.32
4.27
4.60
2.03
1.68
1.68
100 ms
7.32

3.57
4.52
4.98
2.16
1.81
1.81
100 ms
7.7

2.4.2

Bus Latency Times

Interrupts (BR requests) are acknowledged at the end of the current instruction. For a typical instruction, with an instruction execution time of 4 us, the average time to request acknowledgement would
be 2 us.

Interrupt service time, which is the time from BR acknowledgement to the first subroutine instruction,
is 7.32 us max for core, and 7.7 us for MOS.

NPR (DMA) latency, which is the time from request to bus mastership for the first NPR device, is 2.5
us max.

2.5

EXTENDED INSTRUCTION SET

The Extended Instruction Set (EIS) provides the user with the capability of extended manipulation of
fixed-point numbers. Use of the EIS instructions does not degrade processor timing or affect NPR
latency. Interrupts are serviced at the end of an EIS instruction.
The EIS instructio ns are:
Mnemonic

Instruction

Op Code

MUL
DIV

Multiply
Divide
Shift arithmetically
Arithmetic shift combined

070RSS
071RSS
072RSS
073RSS

ASH
ASHC

The number formats are shown in Figure 2-3. Examples of the operation of each instruction are
presented in the paragraphs that follow.

16-B1T SINGLE WORD:

NUMBER

(‘

HIGH NUMBER PART

32-BIT DOUBLE WORD: <

]

LOW NUMBER PART
K

S is the sign bit.
S = 0 for positive quantities
S = 1 for negative quantities; number isin 2's
complement notation
11-4453

Figure 2-3

Extended Instruction Set Number Formats

2-30

Multiply Instruction - MUL 070RSS

Example: 16-bit product (R is odd)

000241

, CLC

1034xx

, BCS ERROR

012701,400
070127,10

:Clear carry condition code

, MOV #400,R1
, MUL #10, R1

:Carry will be set if

;product is less than

:=215 or greater than or ;equal to 2!°
'no significance lost

Before
(R1) = 000400

After
(R1) = 004000

Divide Imstruction — DIV 071RSS
Example:

005000
012701,20001
071027,2

, CLR RO
, MOV #20001,R1
, DIV #2,R0O

Before

After

(R0O) = 000000
(R1) = 020001

(R0O) = 010000 Quotient
(R1) = 000001 Remainder

Arithmetic Shift Instruction - ASH 072RSS
Example: ASH RO, R3

Before
(R3) = 000003
(RO) = 001234

After
(R3) = 000003
(R0O) = 012340

Arithmetic Shift Combined Instruction - ASHC 073RSS

Example: Similar to the example for the ASH instruction except that two registers are used.
2.6

INSTRUCTION SET DIFFERENCES

Table 2-8 lists the instruction set differences between the PDP-11/34 and other PDP-11 machines.

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CHAPTER 3

CPU OPERATING SPECIFICATIONS

Operating Temperature

5° to 50° C (41° to 122° F)

Relative Humidity

20 to 95% (without condensation)

Input Power

+5 Vdc +5% at 4.5 A (typical) per module (M 7265 and M7266)

Physical Size

Two hex modules (8-1/2 X 15 in.)

Interface Requirements

All I/0 signals are available on connectors A and B. These signals are pin-compatible with modified Unibus pinout as shown
in Table 3-1. The bus loading on each of these Unibus lines is
equivalent to one bus load.

Power and Ground Pinouts

+5 V: pins AA2, BA2, CA2, DA2, EA2, EA2

GND: pins AC2, ATI1, BC2, BT1, CC2, CT1, DC2, DT1, EC2,
ET1, FC2, FT1

Number of Integrated
Circuits

231 (M7265 = 120; M7266 = 111)

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3-2

CHAPTER 4

DETAILED HARDWARE DESCRIPTION

4.1

INTRODUCTION

The following paragraphs contain a detailed circuit description of the KD11-E Central Processing
Unit (CPU), which is used in the PDP-11/34 Computer. Segments of the CPU, shown in Figure 4-1,
are analyzed separately, using the block diagrams contained in this manual and the KD11-E circuit
schematics.

4.2

4.2.1

DATA PATH

General Description

The simplified KD11-E data path consists of six function units, as shown in Figure 4-2. Circuit schematics K1-1 through K1-4 (D-CS-M7265-0-1) each contain one 4-bit slice of the data path. Table 4-1
briefly describes the function of each of the six function units.

Data flow through the data path is controlled, directly or indirectly, by the Control Store circuitry on
the control module (M7266). Each Control Store ROM location (microinstruction) generates a unique
set of outputs capable of controlling the data path elements and determining the ALU function to be
performed. Sequences of these ROM microinstructions are combined into microroutines, which perform the various PDP-11 instruction operations.

4-1

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o
v
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a
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X
8

4-2

GL8¢E-1I
A

4\
ENABLE DATA

BUS DATA

SSMUX [15:00]

KT MODES

2
=

VBA

+
CC DATA

=
=

AUX

CONTROL

15:00

| SWAP

SWAP + SEX

PSW MUX

BMODE 1

BX MODE 1

MUX

BXREG
SEX

BX MODE 0——j

PSW

AMUX S1

BLEG
0

AMUX SO

BLEG 1

A MUX

ENAB
BMODE 0

v
LOAD PSW

BREG

sP |

- MODE

SCRATCH PAD

MEMOR Y

(TRI STATE)

SRO

PAR'S

SR2

PDR’S

VBA 15

_ VBA 14
VBA 13

BMUX

_.__

;"3‘2‘
)
l

KT
KT

KT MUX

CONSTANTS
(VECTORS)

(TRI STATE)

SsP

PAR + PDR

KT MUX

15:00

ENABLE

COMPARATOR

ALU CIN —

BUS CONTROL

ALU S3

ALU S2

ALU

ngu:éSZus

LOAD

Co,

(33 )

VBA

ACCESS CONTROL

ALU S1

MODES

‘

BUS DATA 15:00
ADDERS

PSW 15, 14,13, 12

LoGIC

PHYSICAL BUS
ADDRESS 17:00 (PBA)

KT ERROR
|

ERRORS

COND'TE'ON
cogl

USED IN INTERNAL

2
S

. ACF ACF 1

PROCESSOR

ALU MODE
BUS DATA

BITS ACFO,

ED
VBA
6.12

ALU SO

0,C C1

NON RESIDENT

LOAD BA

LOGIC

AD[LJRE'Sg
DECODE
oG

READ ONLY

PAGE LENGTH

6:17

CC DATA
ENABLE ADDRS

__]

LJLJ

VBA
0-5

RELOCATE

BUS ADDRS

DEFINITIONS: SRO — MEMORY MANAGEMENT CONTROL REGISTER 0"

T ERROR

SR2 — MEMORY MANAGEMENT CONTROL REGISTER "'2”

DISABLE MSYN

PAR — PAG ADDRESS REGISTER

THEN THAP

PDR — PAGE DESCRIPTION REGISTER

0 250

11-4454

Figure 4-2

Simplified KD11-E Data Path

4-3

Table 4-1

Function Units of the KD11-E Data Path

Unit

Function

Arithmetic Logic Unit (ALU)

The heart of the data path is the ALU, which is the logic element that manipulates the data. It is capable of performing 16
arithmetic or 16 logic (Boolean) operations on two 16-bit operands to produce a 16-bit result. The A input comes from either
the scratchpad memory or the memory management system; the
B input comes from the B leg. The ALU output is sent to the
AMUX,

ALU Multiplexer (AMUX)

The AMUX is a 4-to-1 multiplexer that controls the
introduction of new data and the circulation of available data
through the data path. Input to the AMUX is both external
(from the Unibus data lines) and internal (from the ALU, PSW,
or constants). The AMUX output is sent to the SSMUX.

Processor Status Word Register

The PSW register is a 12-bit register that contains information
on the current processor priority, condition codes (C, V, Z, and
N) which indicate the results of the last instruction, a *““trap” bit
(TBIT) which causes automatic traps after each fetch instruction used during program debugging, and both the current and
previous memory management modes (Kernel or User). PSW
input comes from the SSMUX or from condition code logic;

(PSW)

PSW output is sent to the AMUX.

Swap Sign Extend Multiplexer
(SSMUX)

This multiplexer controls the form in which data is output from,
or recirculated into, the data path. The SSMUX can pass the
data unchanged, swap the high and low bytes, sign-extend the
low byte into the entire word, or simultaneously swap high and
low bytes while sign-extending the high byte (which becomes the
new low byte) into the entire word. SSMUX input comes from
the AMUX. SSMUX output goes to either the rest of the computer system (via the Unibus), the other sections of the processor (the control section, via the Instruction register, and the
memory management system), or to other portions of the data
path (the PSW, the B leg, and the scratchpad memory).

B Leg

The B leg of the ALU consists of two 16-bit registers (B and BX)
and a 4-to-1 multiplexer (BMUX). Both registers can shift left
or right independently, or together they can perform full 32-bit
shifts. The BMUX selects one of the four functions (BREG,
BXREG, +1, +16) and connects to the B input of the ALU.
The B leg is used to store operands for the ALU, to implement
rotate and shift instructions, and to implement Extended
Instruction Set (EIS) instructions. B leg input comes from the
SSMUZX. B leg output goes to the B input of the ALU.

Table 4-1

Function Units of the KD11-E Data Path (Cont)

Unit

Function

Scratchpad Memory (SPM)

This random access memory can store sixteen 16-bit words in

eight processor-dedicated registers and eight general-purpose
(user available) registers. One of the general-purpose registers is
used as a stack pointer, another as the program counter. Input
to the scratchpad memory is from the SSMUX. Output, which
can be buffered and latched to enable reading from one address
and modifying another during the same cycle, goes to the A
input of the ALU and to the Virtual and Physical Bus Address

registers.

4.2.2

Arithmetic Logic Unit (ALU)

The ALU (Figure 4-3) is divided into four 4-bit slices (K1-1, K1-2, K1-3, and K1-4 each contain a
slice), with each slice consisting of one 4-bit ALU chip (74S181) and part of a Look-Ahead Carry
Generator chip (74S182).
ALU Inputs

The A input to each ALU chip comes from one of the scratchpad memory (SPM) registers or from the
KTMUX, as specified by the Control Store microinstruction being performed. (Refer to Paragraph
4.2.3 for details.) The B input comes from the B leg multiplexer (BMUX) logic, and can take the form
of the B register contents, the BX register contents, a constant 0, a constant 1, or a constant 16. (Refer
|

to Paragraph 4.2.4 for details.)

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ALU FKFunctions

The function performed by the ALU is controlled by the four Selection bits (S3, S2, S1, S0), the Mode
bit (M), and the Carry-In bit (CIN). Table 4-2 lists the ALU functions of the KD11-E and the corresponding bit patterns for the six control signals.

4.2.3

<
et

O et

OO bt et O

OO OO et

0
COO—RLR
OO OO OO~ OO0

=
ik pmma O OO
it

O OO
==
OO
O
O

)]

OO O
O

OO, —,L O, O—
O
OO

A®B

O O OO k==t O b=t

A plus A plus 1

A plus B plus 1
A plus A

A-B

A plus B

ALU Control Signals
CIN
S0
S1

——

b= e

A plus 1
A minus 1
A minus B

O b= b

ZERO

= Ot

ALU Function

ALU Functions and Control Signals

Table 4-2

Scratchpad

The scratchpad consists of a random access memory that can store sixteen 16-bit words, and can be
used for various functions. Scratchpad operation is divided into four 4-bit slices, with K1-1, K1-2, K13, and K1-4 (D-CS-M7265-0-1) each containing one slice. The scratchpad address multiplexer circuitry
is shown on K2-4.

Data Input

Data to be written into the scratchpad is channeled from the SSMUX and clocked into the scratchpad

registers.

Addressing the Scratchpad

The address of the scratchpad memory register to be accessed is generated by the scratchpad address
multiplexer (SPAM), located on the control module (K2-4). Depending on the state of the select lines
B
—

to the SPAM, the source of the address can be any of the following:
The Control Store ROM (ROMSPA03:ROMSPAOQ0).
Instruction Register Source Field (IR08:IR06)
Instruction Register Destination Field (IR02:IR00)
Bus Address (PBA03:00)

4-7

Reading from the Scratchpad

If the Control Store circuitry forces a low on the K1-10 ENAB GR L line at the beginning of a
machine cycle, the tristate outputs of the scratchpad will be enabled. Ninety or 120 nanoseconds after
the cycle begins (allows the scratchpad address to set up), K1-5 TAP 30 H goes low, allowing data
stored in the selected scratchpad register to be latched in the output buffer SP15:SP0O lines. This data
will continue to be read during the rest of the machine cycle. (See Figure 4-4.) Table 4-3 shows the
various scratchpad enabling configurations and the modes they select.

<
TAP 30 H |

MACHINE CYCLE
|

|E—

ENAB GR L |

[

SP WRITE L |

;

PROC CLK L |

;

l__[—

READ SOURCE

WRITE

SCRATCH PAD

DESIGNATION

INTO

SCRATCH PAD REGISTER

LATCH SCRATCH PAD

OUTPUT BUFFERS

TAP 30 H

e
7

meeoW

[

pROC CLK L

[

||
l&—— 180

—]

NOTE:
Source and Designation Register do not

have to be the same. Register selected

may be changed (See SPA Mux description
)
for second half of machine cycle.
11-3878

Figure 4-4

Table 4-3
OD

| WE | CLK | OS

Scratchpad Timing

Scratchpad Enabling Configurations and Modes

Mode

Outputs

OUTPUT STORE

Data from last addressed location

WRITE DATA

Data being written (if OD = L and OS = H)

READ DATA

Data stored in addressed location

OUTPUT STORE

High-impedance state

OUTPUT DISABLE |

High-impedance state

4-8

Latching of Outputs
When the OD (pin 12) and OS (pin 13) inputs are both low, the data being read from the scratchpad

that is addressed is latched into the buffers on the output of scratchpad memory (SP15-00). Once those
outputs are stabilized, they are not affected by any modifications to the scratchpad memory address
lines for the remainder of the cycle.
Clocking the Scratchpad
The REG CLK H clock signal clocks data from the SSMUX lines into the scratchpad register and
writes that data into scratchpad memory. TAP 30 H unasserted, placing a high at the OS input (pin 13)

of the scratchpad, is all that is required for a read operation. Both a read and a write can take place
during the same machine cycle. Figure 4-4 shows the scratchpad timing for one machine cycle.
Scratchpad Address Multiplexer (SPAM)
The SPAM (Figure 4-5) generates the four address signals that select the desired scratchpad register, or

word. The SPAM (shown in print K2-4 of D-CS-M7266-0-1) consists of two 745153 dual 4-line-to-1line data multiplexers, or a total of four 4-to-1 multiplexers, all with a common strobe input signal

(GND) and common address input signals (S1 and S0). Four data input sources are connected so that,
when the SPAM is addressed and strobed, it generates one 4-bit output, selected from one of the four

sources. Table 4-4 lists the sources of SPAM input data and the address input signal configurations
that select them.

PBA |

> D

IR-SRC |

> B

IR-DST |

> c 148153

CONTROL

STORE ROM

(K2-4)
SPAM

> spM

S(1:0)

K2-9 SPA DST

SEL (1:0)(1)H

[

745157

K2-9 SPA SRC

SEL (1:0) (1) H

(K2-4)

STB

i}
S8 |

NoOTE:
SPA =6, forced to 16 for
user mode ROM,IR-SRC,

IR-DST.

K1-5 TAP 30 H

Figure 4-5

11-3880

Scratchpad Address Multiplexer (SPAM)

Table 4-4

SPAM Input Data Sources

SPAM

Function

Source Operand

Source

Input

Source

Instruction Register Bits 08:06

K2-5

Instruction Register Bits 02:00

K2-5

ROM SPA Bits 03:00

K2-10

PBA Bits 03:00

K1-6

Destination Operand
Register Selection

General-Purpose Register
Selection from Console

Scratchpad Memory Organization

The scratchpad memory (SPM) is a 16-word-by-16-bit random access read /write memory composed
of four 16-word-by-4-bit bipolar (85568) memory units (K1-1 through K1-4). The 16-word-by-16-bit
organization of this memory provides 16 storage registers that are utilized as shown in Table 4-5.
Table 4-5

SPM Register Utilization

Number | Description

RO
R1

R2
R3 [ General-Purpose Registers
R4

R5 |
R6

(Processor Stack Pointer)

(Program Counter)

R10

Temporary Storage

R11

Unused

R12

Temporary Storage

R13

Temporary Storage

R14

Unused

R15

Temporary Storage

R16

Processor Stack Pointer
(Memory Management User Mode)

R17

Temporary Storage

4-10

Scratchpad Outputs

Data outputs from the scratchpad are fed to the ALU as t he A leg input and to the memory manage-

ment system.

42.4

B Leg

The B leg (Figure 4-6) of the ALU consists of three components: the B register, the BX register, and the
B leg multiplexer (BMUX). Each of these components is divided into four 4-bit slices, with circuit
schematic prints K1-1, K1-2, K1-3, and K1-4 each containing a slice. Data from the SSMUX can be
clocked into either register. Register contents can be shifted either individually as 16-bit words or
together as a double (32-bit) word.

B MODE

SP SR

s1(sp]|

L | L

|HOLD

/
s

REG.

_ | n [GHIFT
H

RIGHT
SHIFT

L leFT

H | H [LOAD

BITSOIS) (K1-1oK1-4)|
74194
CLK

PROC. CLK

FROM [L

MUX

+1 —3

SHIFT IN B

+16

—2

!(K1-1=K1-4)F :>XEC
MUX

B MODE 90

BIT®

BITsg)

@
BLEG

SP SR|

lLuliv]|

(K1-1+Ki-4)

I
SHIFT IN BX

BLEG 0@

s1|sp | F

REC

CLK

9T‘

B MODE @1

s1|s@g|

L | L

|HoLD

L|H | BX

HiL

|16

HIH

|+1

SHIFT

L | H |RIGHT
H|

H | H

Figure 4-6

SHIFT

L |LEFT
|LoAD

B Leg Block Diagram

11- 3881

B Register

The B register (B REG) is a general-purpose storage register (Figure 4-7) on the B leg of the ALU,
consisting of four 4-bit bidirectional universal shift registers (74194). The mode control lines of the
four 4-bit registers are connected in parallel, so that the signals K2-8 B MODE 00 L and K2-8 B
MODE 01 L select the function that will be performed by the B register when clocked by K1-5 PROC
CLK L. Table 4-6 shows the various functions and the shift configurations that select them.

K2-8

BMODE 00 L

K2-8 BMODE

{__~1

S@ SR

B REG

BITS 12-15

(K1-4)

74194

CLK

|BITS 12-15

BIT 12

SISO SR|

BITS 8-11

SHIFT
IN
SHIFT
IN 07 H —

B REG

74194

BITS 4-7

SO SR

BIT 7

B REG

> (K1-2) |BITS 4->
74194

CLK
L —

\ TO BMUX

{_} v

FROM SS MUXI

K1-5 PROC CLK

|giT
1

> (K1-3) [BITS 8-11)
CLK

K-10

)

BIT 4

|—
{________.,

S1 SO SR

BITS 0-3

B REG

> (k1-1)

74194

CLK

;

BIT 3
S1]S@ |[FUNCTION

[BITS 0-3)
.

L | L | HOLD
L | H|

SHIFT

HoLDp

SHIFT

H1L | CeEFT
H|H|

LOAD

K1-10 SHIFT IN B H
11-3882

Figure 4-7

BREG Block Diagram

4-12

Table 4-6
Mode

B and BX Register Enabling Configurations and Modes

Mode

Function (when PROC CLK L goes high)

Hold

Contents of register do not change.

Shift Right

Contents are shifted right one bit.

Shift Left

Contents are shifted left one bit.

Parallel Load

Data from SSMUX is loaded into B register
and appears at output.

The B register can be shifted as an 8-bit byte or a 16-bit word. The signal K1-10 SHIFT IN B determines what is shifted into the B register. When the contents of this register and the BX register are
combined into a 32-bit word, the B register contains the upper 16 bits.
BX Register

The BX register (BX REG) is a general-purpose storage register (Figure 4-8) on the B leg of the ALU,
consisting of four 4-bit bidirectional universal shift registers (74194), similar to the B register. The
mode control lines of the four 4-bit registers are connected in parallel, so that the signals K2-8 BX
MODE 00 L and K2-8 BX MODE 01 L select the function to be performed when the BX REG is
clocked by K1-5 PROC CLK L. The BX register can be shifted as a 16-bit word or, in conjunction with
the B register, as a 32-bit word. In the latter case, the BX register contains the lower 16 bits of the 32bit word, and the shift right (SR) input of the most significant register in the BX register is connected
to the zero bit of the B register. Table 4-6 shows the various functions and the shift configurations of
K2-8 BX MODE 00 L and K2-8 BX MODE 01 L that select them.

B Leg Multiplexer (BMUX)

The BMUX (Figure 4-9) consists of three 2-to-11 multiplexers and a 4-to-1 multiplexer, and is used to
select the proper input to be used as an operand on the B leg of the ALU. The BMUX can select the
contents of either the B REG or BX REG, or can act as a constant generator (constants 16, 1, or 0),
depending on the configuration of signals K2-8 BLEG 00 H and B LEG 01 H (Table 4-7) and the state
of K2-4 DISAB MSYN +1 L.

4-13

'K1-1

BREG 09 (1) H

——

BITS 12-15

50 SR

BX REG
74194

cLk

Ki-5 PROC CLK L —

BITS 8-11

81T

BX REG

74194

BIT 8
) TO BMUX

SO SR

BIT 7

REG

> (K1-2) [BITS 4->
74194

CLK

> (K1—-3) [BITS 8-1>

K2-8 BX MODE Of L ——}

—5 1
BITS 4-7

)

BIT 12

50 SR

CLK
K FROM SS MUX [

> (K1-4) [BITS12-15>

t_fi

BIT
4

{

—————————

K2-8 BX MODE 00 L —

BITS 0-3

SO SR

BIT 3

BX REG

> (K1-1) [BITS0-3)
74194

CLK

:
L

| S@ |[FUNCTION

H | RIGHT

L | L | HOLD

SHIFT

H1L | LEFT
H

| H | LOAD

K1-10 SHIFT IN BX H
11-3883

Figure 4-8

BX REG Block Diagram

4-14

(K1-4)

FROM BX REG[

BITS 12-15>8

‘

B MUX
FlBITS 12-15

12-15>A

BITS

74157

STB

(K1-3)

BITS 8-11

B
B MUX

F[BITS 8-11

K2-8

BLEG O0H

K2-8

BLEG O1H

BITS

8—1J1>A

STB

0
I

FROM B REG[

74157

(K1-2)

'\\

BITS 4-7 )B

BLEG BLEG
FUNCTION
00

B MUX

B-REG

BITS

4—7/ A

BIT 2
BIT 1

STB

/L
BIT 3 )

Ijir|xT

BIT 3 )

Irix|r

FIBITS 4-7

74157

ALU

BX-REG
16
1

K2-4 DISABLE
BIT @

MSYN
+ 1

K2-8 AUX

(1) H
CONTROL

BIT 2 |\_
BIT1

5 MUX

BITO |/

(K1-1)

F|BITS 0-3

BITS 0-3 B

74153

BITS 0-3

JA
S|
T

SO
I

11-3884

Figure 4-9

BMUX Block Diagram

4- 15

Table 4-7

B Leg

B Le:g

BMUX Enabling Configurations and Modes

Function

B REG

Description
Passes data from the B register to the BMUX out-

puts. This is the most common configuration.
L

BX REG

Passes data from the BX register to the BMUX

outputs. This
instructions.
H

+16

used

principally

for

EIS

Forces the constant +16 into the BMUX outputs

to preset a counter that is used for EIS instructions.
H

Forces the constant +1 into the BMUX outputs

during operations in which the contents of a register are being incremented or decremented by two.

—~

By asserting DISABLE MSYN +1 L, this configuration forces the constant 0 into the BMUX
outputs during operations in which the contents of
a register are being incremented or decremented by
one. (The signal K2-8 ALU CIN L to the ALU
from the control module provides the one.)

B Leg Shift Capabilities

Each of the four shift registers (74194) that make up each register (B REG and BX REG) has the
capability of being shifted left or right, as indicatedin Table 4-6 and Figure 4-10. The B register can be
shifted as an 8-bit byte or a 16-bit word; the BX register can be shifted as a 16-bit word or, in conjunction with the B register, as a 32-bit word.
Byte Shifts

If the mode control lines (K2-8 B MODE 00 L and K2-8 B MODE 01 L) specify a shift left, B REG
15:00 are shifted one position toward the most significant bit at the clock pulse K1-5 PROC CLK L
going high. The signal K1-10 SHIFT IN B H is shifted into bit 00 via the SL input. This signal is
generated by the SHIFT MUX (E117 on print K1-10) as a function of the select signals K2-8 SHIFT
MUX 01 L and K2-8 SHIFT MUX 00 L. The shift right input to B REG bits 07:04 comes from the
BYTE MUX (E106 on print K1-10). Assertion of K2-5 BYTE L (indicating a byte instruction) causes
bit 07 of the B REG to be loaded directly by K2-5 SERIAL SHIFT H; if K2-5 BYTE L is high,
however, B REG bit 07 is loaded from B REG 08. B REG bit 15 is loaded from K1-10 SHIFT IN BH
during a shift right (just as B REG bit 00 is loaded during a shift left), and can be loaded with itself,
K2-5 SERIAL SHIFT H, ground, or BX REG bit 15, depending on the SHIFT MUX. For a shift
right, BX REG bits 15:01 are shifted one position toward the least significant bit, and BX REG bit 15
is loaded with B REG bit 00. Thus, for all right shifts, the BX REG acts as the low-order 16 bits of a
32-bit word made up of B REG and BX REG. For a shift left, BX REG bits 15:00 are shifted one bit
position toward the most significant bit. BX REG bit 00 is loaded with the signal K1-10 SHIFT IN BX
H, which is generated by the SHIFT MUX. Depending on the configuration of the SHIFT MUX
control lines K2-8 SHIFT MUX 00 L and K2-8 SHIFT MUX 01 L, the BX REG may be loaded with
any of four possible inputs: K1-4 ALU COUT H, the output of the EIS overflow detection logic (E98
on print K1-10), ONE, and ZERO.

4-16

v | ]

—— ———

;
|

12-15

(K1-4)

K1-10 SHIFT INB H

+3D

ENAB CLR

I_' St SO

12-15

r__L———

K1-4 ALU CONT H
MUX ©1 L

K2-2 PROC.INITJLD‘ K2-8 SHIFT MUX pOL —

O_33R

| (K1-2) S*U_“

K2-8 ENABOVXL | | 5 o shIFT

K2-5 LOAD IR H

~ BRE_l

I
Fi

[ika-1) SL

OVERFLOW
LOGIC

|
I
I
iR
S
8-11 | 74194
I
|
| lxi-a) s

SHIFT

DETECTION

=
—

I (K1-4) SL)

|
|

r———‘———l

AD MUX
EIS

’ 38R |

I
L

___DQ(KHO)

(K1-10)

!
a-758

a o0

| k-2 s

K2-5 BYTE L

K2-5 SERIAL SHIFT H

|
|

sL| ]

BYTE MUX

|
8-11
|

(K1 -10)

STB

K1-10 SHIFT IN BX H

gJ I

| (K1-1) SL

———

s REG.__I
e

11 -3885

Figure 4-10

B Leg Shift Logic

4-17

Specific Shift and Rotate Operations
The shifting requirements for the ASL, ASR, ROL, ROR, ASH, and ASHC instructions are described
briefly below.
1.

Arithmetic Shift Left (ASL) - Shifts all bits of the destination left one place. The low-order
bit is loaded with a 0. The C-bit of the status word is loaded from the high-order bit of the
destination. ASL performs a signed multiplication of the destination by 2, with overflow
indication.
Arithmetic Shift Right (ASR) - Shifts all bits of the destination right one place. The highorder bit is duplicated. The C-bit is loaded from the low-order bit of the destination. ASR
performs signed division of the destination by two.
Rotate Left (ROL or ROLB, depending on whether a word or byte operation) — Rotates all
bits of the destination left one place. The high-order bit is loaded into the C-bit of the status
word, and the previous contents of the C-bit are loaded into the low-order bit of the
destination.

Rotate Right (ROR or RORB) - Rotates all bits of the destination right one place. The loworder bit is loaded into the C-bit, and the previous contents of the C-bit are loaded into the
high-order bit of the destination.

Arithmetic Shift (ASH) - Shifts the contents of the register right or left the number of times
specified by the source operand. The shift count is taken as the low-order six bits of the
source operand. This number ranges from -32 to +31. Negative is a right shift and positive
is a left shift.

Arithmetic Shift Combined (ASHC) - Treats the contents of the register and the register
ORed with one as one 32-bit word. Rv1 (bits 15:00) and R (bits 31:16) are shifted right or left
the number of times specified by the shift count. The shift count is taken as the low-order six
bits of the source operand. This number ranges from -32 to +31. Negative is a right shift
and positive is a left shift. (When the register chosen is an odd number, the register and the
register ORed with one are the same. In this case, the right shift becomes a rotate. The 16-bit
word is rotated right the number of bits specified by the shift count.)
NOTE
When R is an even-numbered register, Rvl will be
the next highest register. If R is an odd-numbered

4-18

BMUX Operation

Three 2-to-1 multiplexers (74157s) are used to switch B leg bits 15:04. Their select lines are tied in
parallel with each other and with the SO line of the 4-to-1 multiplexer (two 74153s) used to switch B leg
bits 03:00. The SO line is signal K2-8 B LEG 00 H. Signal K2-8 B LEG 01 H is connected to the enable
lines of the 2-to-1 multiplexers and to the S1 line of the 4-to-1 multiplexer. Table 4-7 describes the
enabling configurations and modes for these two select signals, which are logically determined as
follows:

Ifboth K2-8 BLEG 00 H and K2-8 B LEG 01 H are low, the 4-to-1 multiplexer (E8 and ES
on print K1-1) selects the A input and the 2-to-1 multiplexers (E28 on print K1-2, E18 on
K1-3, and E38 on K1-4) select the A inputs; the data from the B REG is switched to the
BMUX output.

If K2-8 B LEG 01 H is low and K2-8 B LEG 00 H is high, the 4-to-1 multiplexer selects
input B, the 2-to-1 multiplexers remain enabled, and the data from the BX REG is switched
to the BMUX output.

If K2-8 B LEG 01 H is high and K2-8 B LEG 00 H is low, the 2-to-1 multiplexers are not
enabled. The 4-to-1 multiplexer selects input C, where bit 0 is low and bits 03:01 are connected to K2-8 AUX CONTROL (1) L unasserted, generating a +16 constant to the B leg.

If both K2-8 B LEG 01 H and K2-8 B LEG 00 H are high, the 2-to-1 multiplexers are still
disabled and the 4-to-1 multiplexer selects input D, where bits 03:01 are grounded and bit 00
is connected to K2-4 DISABLE MSYN +1 L unasserted, generating a constant of +1 to the
B leg.

If,in 4 above, K2-4 DISABLE MSYN +1 L is asserted, a constant of Ois generated to the B
leg.

Constants +16, +1, and 0

The purpose of generating the constants +1 and 0 on the B leg input of the ALU is to aid the processor
to perform autoincrement and autodecrement operations. During either operation, if a word instruction is being performed, the specified register is incremented or decremented by two; if a byte instruction is being performed, the register is incremented or decremented only by one. The actual ALU
operation 1is:

RESULT = A LEG DATA + B LEG DATA + ALU CIN.

The ALU always uses the K2-8 ALU CIN L signal to increment or decrement the A leg input by one;
thus, the B leg input must provide the constant +1 or 0 to obtain the correct autoincrement or autodecrement result for both byte and word instructions. A B leg constant of +1 is generated by enabling
the least significant bit of the BMUX output (bit 00) and forcing all other bits (15:01) to 0. To generate
a constant 0, even bit 00 is cleared. The actual constant generated is defined by the state of the K2-4
DISABLE MSYN +1 L signal, which is determined by the Control Store.

4-19

4.2.5 ALU Mulitiplexer (AMUX)
The AMUX (Figure 4-11) consists of three 4-to-1 multiplexers (74S153s) and one 2-to-1 multiplexer
(745157), each one dedicated to a 4-bit slice of the AMUX. The 2-to-1 multiplexer (E14 on print K 1-3)
switches AMUX bits 11:08 according to the state of the STB and SO inputs. If the STB input is high,
the multiplexer is disabled, and the output is forced low. If the STB input is low, the multiplexer is
enabled, and the output depends on the state of the SO input and the appropriate data input. Thus, if
the SO input is low, the A data input will be gated through to the AM UX output; if the SO input is high,
the B data input will be gated through. Because the 4-to-1 multiplexer does not have an enable input,
the output always follows one of the inputs, corresponding to the binary value of select lines S1 and SO
(K1-10 AMUX S1 H and K1-10 AMUX SO H, respectively), as follows:
1.

Unibus Data Function - If both S1 and SO are low (binary 0), the 4-to-1 multiplexers select
input A and the 2-to-1 multiplexer selects input A. Thus, each 4-bit slice of the AMUX
switches Unibus data into the data path.

Constant’s Function - Certain operations require the introduction of specific numbers into
the data path. (For example, the data path must generate a vector of 24 for a power-fail trap,
or 114 for a parity trap.) Access to these and other numbers is facilitated by storing certain
constants in a read-only memory and presenting them to the constant’s input of the AMUX.
If S1 1s low and SO is high (binary 1), the 4-to-1 multiplexers select input B (the constant’s
input). Bits 11:08, which are controlled by the 2-to-1 multiplexer, are not used.

ALU Input - If S1 is high and SO is low (binary 2), the 4-to-1 multiplexers select ALU inputs

(input C) and the 2-to-1 multiplexeris enabled, also selecting ALU inputs, so that the ALU
lines are selected for all 16 bits.
4.

PSW Inputs - If both S1 and SO are high (binary 3), the 4-to-1 multiplexers select the PSW
input (input D). The 2-to-1 multiplexer is disabled, as bits 11:08 are not used.

4.2.6

Processor Status Word
The Processor Status Word (PSW) register contains information on the current and previous memory
management mode, the current processor priority, a processor trap for debugging, and the condition
code results of the previous operation. The PSW bit assignments and uses are shown in Table 4-8.

4-20

29242V,

psw |

(K1-4)

AMUX
(15:12)
F |[BITS12+15

GND

(K1-3)
ALU

AMUX

(11:08)

BITS 8+11

STB

Ov&@ WAVAVAY,

Ki-10 AMUX

S@ H

)

SO
K1-10 AMUX

(K1-2)
AMUX

UNCTION

s1 [sp| FONeT

AMUX

(07304)F BITS 4 =7

CONSTANTS

TO SS MUX

L | UNIBUS

L |H

[CONSTANT

ALU

PSW

(K1-1)

AMUX

(03:00)

UNIBUS
DATA

F|BITSO+3

11-3886

Figure 4-11

AMUX Block Diagram

4-21

Table 4-8

Processor Status Word Register Bit Assignments

PSW Bit

Name

Use

15:14

Memory Management
Current Mode

Contain the current memory management modes.

13:12

Memory Management
Previous Mode

Contain the previous memory management modes.

11:08

Unused

07:05

Priority

Set the processor priority.

Trace

When this bit is set, the processor traps to the trace

vector. Used for program debugging.
03

Set when the result of the last data manipulation is
negative,

Set when the result of the last data manipulation is
Zero.

Set when the result of the last data manipulation
produces an overflow.

Set when the result of the last data manipulation
produces a carry from the most significant bit.

The PSW (Figure 4-12) is a 12-bit register composed of three quad D-type flip-flops (74175s) and one

separate D-type latch. The first of these (E95 on print K1-1) stores the condition code bits (N, Z, V,
and C), and derives its input from the PSW MUX, a quad 2-line-to-1-line multiplexer (E96 on K1-1)
according to the state of the SO select line. When high, SO selects the B inputs (SSMUX bits 03:00);
when low, SO selects the A inputs, which come from the condition code logic (print K1-10). The
selected inputs are passed to the f-outputs of the multiplexer and into the PSW.
A second quad D-type flip-flop (E97 on K1-2) is used to store the three KD11-E processor priority
bits, which it obtains from SSMUX bits 07:05. A separate 74S74 (E107 on K 1-2) is needed to store the
Trace Trap flag (T-bit), which can be loaded from the K1-2 SSMUX 04 H line.
The third quad D-type flip-flop (E80 on K1-4) stores the bits containing the current and previous

status of the memory management mode. SSMUX bits 15 and 14 provide the input for PSW bits 15
and 14, which are then rerouted through a quad 2-line-to-1-line multiplexer (E90 on K 1-4) and multiplexed with SSMUX bits 13 and 12 according to the state of the SO select signal [K2-9 FORCE
KERNEL (1) H] to provide the input for PSW bits 13 and 12. Thus, PSW bits 15 and 14 reflect the
current status of the memory management mode, while PSW bits 13 and 12 indicate the previous
status.

All flip-flops in the PSW are clocked, directly or indirectly, by clocking signal K1-5 REG CLK L. All

of the enabling signals come from the Control Store.

4-22

(K1-4)

SS MUX (15:14) | |

BITS (15:14)

PSW (15:14) | [> B

K1-4)

PSW(15:12)

MEM.MGMNT. MODE

ABITS (13:12)
CLR

PSW MUX

SS MUX (15:12)

STB

FORCE KERNAL (1) H

[

CLK

LOAD H PSW

(K1-2)

ss MUX (07:05)

( REG.CLK)-

11>PSW(O7105)

PRIORITY

CLK

|CLR

[ (LOAD PSW LOW)+( LOAD PSW 12 =18 )]
SS MUX 94

(Ki-2)

“

PSW@4

(REG CLK)- ( LOAD PSW)

|T-BIT

CLK

CLR

SS MUX (03:00) [:>B (K1-1)

(K1:1)
PSW (03:00)

PSW MUX

CC LOGIC

STB

C,V,N,Z

CLR

CLK

(AUX CONTROL )-(LOAD PSW LOW)
PROC INIT L

(REG CLK)- [(LOAD PSW) +
(LOAD PSW LOW )+ ( LOAD CC)]
11-3887

Figure 4-12

Processor Status Word

4-23

T0
AMUX

4.3 CONDITION CODES
The logic necessary for determining the condition codes is shown on sheets K1-10 and K2-5, and can
be subdivided into three parts, each of which is discussed in some detail in this section. Constraints for
each condition code bit are shown in the instruction set specifications (Chapter 2).
4.3.1

Instruction Categorizing ROM
The Categorizing ROM (E67 on sheet K2-5) decodes the instructions in the IR and categorizes them
into eight groups, based on their effect on the carry and overflow condition codes. These groups are as

OO\
N B W
—

=)
=
=

follows:

Instructions

MOV, BIT, BIS, BIC, and non-PDP-11 instructions
INC, DEC
CLR, TST,SWAB
ADD, ADC
NEG, CMP, COM

SUB, SBC
Rotate instructions
Unused

Three of the four outputs of the Categorizing ROM are used to provide a binary representation of one

of the above instruction categories for the C and V Decode ROM (E105 on K 1-10). The fourth output
(K2-5 BYTE L) decodes the fact that the instruction in the IR is a byte instruction and is fed to the
select input of the BYTE MUX (E106 on K1-10).

4.3.2

Byte Multiplexer (BYTE MUX)
The BYTE MUX (E106 on K1-10) is a quad 2-line-to-1-line multiplexer (74S157) that determines the

N condition code bit and the K1-10 SHIFT IN 07 H signal for the B REG (Figure 4-13). A single select
input (K2-5 BYTE L) selects the A inputs when a byte operation is performed, and the B inputs when

the operation is not a byte.

(K1-10)

K1-3 BREG @8 (1)H —— B¢
K2-5 SERIAL SHIFT

f®

—— K1-10 SHIFT IN O7 H

H —{ A@

K1-4 ALU 15 H —— BT

K1-2 ALU @7 H —] A
K1-4 SP 15 (1)

K1-10CC N H

MU
X

H —— B2 (E106)

K1-2 SP@7 (1) H —— A2

K1-4 BLEG

BYTE
745157

h
f2

"“"

> 10 C + V DECODER

H ——{ B3

ROM

K1-2 BLEG @7H ——{
A3

£3

STB

K2-5 BYTE L
11-3888

Figure 4-13

Byte Multiplexer

4-24

Output signal K1-10 CC N H assumes the level of K1-4 ALU 15 H when the instruction being performed is a word operation, and the level of K1-2 ALU 07 H when the instruction is a byte operation.
Byte operations may be performed on either the high or low bytes of the input word, depending on

whether the processor microcode has already swapped bytes before the condition codes are detected.

For shift right operations, the K1-10 SHIFT IN 07 H output assumes the level of the K1-3 BREG 08
(1) H input when a word instruction is performed, and the level of the K2-5 SERIAL SHIFT H output
of the ROT/SHFT ROM (E61 on print K2-5) for a byte operation. The diagrams in Figure 4-14
indicate the operations performed by various instructions.
4.3.3

C and V Decode ROM

The C and V Decode ROM (E105 on K1-10) determines the values of the carry and overflow condition
code bits as a function of the instruction being performed (Figure 4-15). Inputs to this ROM come
from the ROT SHIFT ROM (E61 on K2-5), the PSW [K1-1 CBIT (1) H], the BYTE MUX, and the
Categorizing ROM (E67 on K2-5). Outputs K1-10 CC V H and K1-10 CC C H are fed via the PSW
MUX (E96 on K1-1) to the PSW register.
4.3.4

Condition Code Signal CC Z H

Each 4-bit slice of the data path contains an ALU output via a gate (type 8815) reflecting whether all
four of the bits in that slice are ZERO. If the instruction being performed is a byte operation, condition
code signal K1-10 CC Z H assumes the combined state of signals K1-1 0-3=0 H and K1-2 4-7=0 H;
for a word operation, K1-10 CC Z H assumes the combined state of those signals together with K1-3
8—11=0 H and K1-4 12-15=0 H. Thus, K1-10 CC Z H is asserted if bits 00 through 07 = O for a byte
operation and if bits 00 through 15 = 0 for a word operation. Assertion of K2-5 BYTE L selects byte
operation.

4.4
4.4.1

UNIBUS ADDRESS AND DATA INTERFACE
Unibus Drivers and Receivers

Standard bus transceiver circuits (type 8641) are used to interface the processor data path to the
Unibus address (BUS A00:A15) and data (BUS D00:D15) lines. These circuits are shown on prints
K1-1 through K1-4, and on K1-6. Figure 4-16 shows the logic diagram for an 8641.
4.4.2

Unibus Address Generation Circuitry

A unique feature of the KD11-E is that KT11-D equivalent memory management capability is built
into the 2-board processor. During Unibus transfers, virtual bus addresses are obtained from the
scratchpad memory (SPM) and the Physical Bus Address (PBA) register, if relocation is not enabled,
and latched in the Virtual Bus Address (VBA) register shown on print K1-6. Figure 4-17 shows the
actual VBA clock timing, while Figure 4-18 shows Unibus address logic in block diagram form.
If the memory management circuit is not enabled (K1-8 RELOCATE H is not asserted), the address
that was clocked into the Physical Bus Address register is used as address data for the 8641 transceivers
and driven onto the Unibus address lines.

When the memory management circuit is enabled (K1-8 RELOCATE H asserted), a selected relocation constant (detailed description in Paragraph 4.12) is added to the contents of the VBA before it 1s
latched into the BA and driven onto the Unibus.

4-25

oL
|

(6]

‘T
15

ROL

{ c F"‘“‘

ROLB

4Jo

WORD:

IIFI‘_—{15 I

BYTE

r
15[

ASR

00D

[

EVEN

TM Ll
C

ASRB

C
s

WORD

| T

| IIII

BYTE:

| ! |

CoL

ODD ADDRESS

}_’IHI ‘l ol
7

EVEN ADDRESS

L }"'IEI
Y

ASL
ASLB

WORD:

BN
15

BYTE:

kel

ODD ADDRESS

EVEN ADDRESS

11-3952

Figure 4-14

Rotate Instructions

4-26

+5V

K2-6 IR DECODE (1) L

K2-5 IR 15 (1) H —
K2-5 IR 14 (1)

(K2-5)

H —

K2-5 TR 12 (1) H

H —

K2-5 IR 09 (1)

H —

K2-5 IR 08 (1)

H ——

K2-5 CC CODE OO H

C+V
DECODE

— K1-10 CCV H

ROM

B
FROM
BYTE MUX

—K1-10 CCCH

K2-5 IR O7 (1) H —
K2-5 IR 06 (1) H —

(K1-10)

K2-5 CC CODE O1 H

CATEGORIZING
ROM

K2-5 IR 10 (1)

K2-5 BYTE L

K2-5 CC CODE O2 H

K2-5IR 13 (1) H

K2-5 BYTE H

K2-5 ROT CBIT (1) H—
E67

K1-1 CBIT (1) H—
E105
11-3889

C and R Decode ROM

UNIBUS

B
_J

LINES

VY]

Figure 4-15

11-3891

Figure 4-16

Unibus Transceiver

4-27

LOAD VBA

DELAY

LOAD VBA

LOAD BA

TAP 30 H
TAP 90 H
LOAD

TAP120 H

| f

PROC CLK L

——»L_F—Z%Ons

le—180ns—sfe-——240 ns———>|

SHORT CYCLE ————+———— LONG CYCLE —>
1-3900

Figure 4-17

Processor Clock Cycle Timing

BITS 11-0 t>>

FROM PAR | PAGE ADDRESS FIELD

(K1-6)
ADDER

—

BYTSl?~6t>>B (K1-8)

-8 ) e Ts12-6)
K1K1-6
FROM KT MUX

BITS5-0X

K1-5 LOAD VBA H ———l

L B”Lé——t\?’—EUNIBUS
TO

BITS 17-6
K1-8 RELOCATE H
K1-5

K2-2 PROC INIT L

f
FROM

DATA PATH

BYTSJ7—6i>> DRIVER

VBA
N

(K1-6)

LOAD BAR L

—

(K1-6)
-

BITS 5-0
BIT 15—\___4

BIT13—J—

DRIVER

BIT 17

BIT 16

K2-1 ENAB ADDRS L
11-3892

Figure 4-18

Unibus Address Logic Block Diagram

4-28

Internal Address Decoder

4.4.3

The receiver half of the bus transceivers continually monitors the Unibus address lines. If the processor
is running (HALT RQST L or BUS SACK L are not asserted), these transceivers allow the Internal
Address Decoder circuit (print K1-10) to detect transfers to or from the PSW and memory management registers. Note, however, that the CPU does not allow access to its general registers through their
Unibus addresses while it is running.

While the processor is halted (BUS SACK L is asserted), this decoder circuit enables data transfers
between CPU registers and Unibus peripheral devices. A list of these CPU registers and their Unibus
addresses is shown below; the registers are discussed in Paragraph 4.12.

4.5

PSW
RO
R1
R2
R3
R4
RS
R6

777776
777700
777701
777702
777703
777704
777705
777706

777707

R10
R11
R12
R13
R14
R15
R16
R17

777710
777711
777712
777713
777714
TT7715
777716
177717

INSTRUCTION DECODING
General Description

4.5.1

Two methods are used to control instruction decoding, one using microroutine selection and the other
using auxiliary ALU control. Dual control is required because of the large number of instructions that
require source/destination calculations. Auxiliary ALU control is evoked whenever the microcode
executes the action X = Y OP B as a result of a specific instruction.

There are two prerequisites to a thorough understanding of the instruction decoding procedure. One is
a knowledge of the microbranching process, and the other is a knowledge of the PDP-11 instruction
format.

The following facts pertain to the KD11-E/PDP-11 instruction set:

In general, the PDP-11 operation code is variable from 4 to 16 bits.

A number of instructions require two address calculations; an even larger number require
only one address calculation. There are also a number of instructions that require address
calculations, but do not operate on data.

All op codes that are not implemented in the KD 11-E processor must be trapped.

There are illegal combinations of instructions and address modes that must be trapped.

There exists a list of exceptions in the execution of instructions having to do with both the
treatment of data and the setting of condition codes in the processor status word.

4-29

4.5.2

Instruction Register
Each PDP-11 instruction obtained from memory is stored in the 16-bit instruction register (IR).

This
register consists of three 6-bit D-type 74174 registers (E55, E65, and E66 on K2-5) and one 74574 Dtype flip-flop (E33). The purpose of the IR is to store the instruction for the complete instruction
cycle
so that the IR Decode and Auxiliary ALU Control circuits can decode the correct control
signals
throughout the instruction cycle.
The IR latches data from the SSMUX 00-15 lines on K2-7 LOAD IR L and the leading edge

of K1-5

On the trailing edge of K2-9 BUT SERVICE (1) H, all the IR bits except K2-5 IR 15 (1) H are

cleared.

PROC CLK L.

[K2-5 IR15 (1) H is set by the same signal transition.] This means that the IR Decode circuit

conditional branch instruction in the IR after every service microstep. This action prevents

sor from decoding a HLT instruction after an Initialize condition.

will see a

the proces-

If a bus error (BE) occurs while the Control Store output signal Enable Double
Bus Error (K2-8
ENAB DBE L) is asserted, the whole IR is cleared (PDP-11 Halt), causing the processor
to halt
automatically. Bus errors occurring without the K2-8 ENAB DBE L signal have no effect
on the IR.
K2-8 ENAB DBE L is only asserted during certain microwords in the trap sequence to prevent
the
possibility of a second bus error occuring (Double Bus Error), which would cause the trap sequence
to
be re-entered before it is completed. For example, if R6 (Stack Pointer) were an odd address, the
first
bus reference using the stack in the trap routine would cause another trap (Odd Address), a sequence
that could tie up the CPU indefinitely if not for the Halt and Double Bus Error facilities. In short,
any
bus error during the four memory references of the trap sequence is fatal.
4.5.3

Instruction Decoder

4.5.3.1
Instruction Decoder Circuitry - The Instruction Decode (prints K2-5 and K2-6) and Control
Store (prints K2-7 through K2-10) circuitry could be thought of as an internal microproces
sor that
interprets PDP-11 instructions and translates them into a set of microinstructions, each consisting
of
40 control signals. These control signals then determine the operation of the data path and
Unibus
control circuitry.
A block diagram of this internal microprocessor is shown in Figure 4-1. Note that all outputs
of the
Control Store ROMs (K2-7 through K2-10) are latched in hex D-type registers (74174s).
Nine of these latched signals (K2-7 MPC 08 H through K2-7 MPC 00 H) are fed back
to the inputs of
the Control Store ROM as the next microinstruction address (and can then be called
the micro-PC).
The wired-OR capability of these lines allows the IR Decode circuitry to force
microbranching
addresses on certain enabling conditions. The actual microbranch address will depend
on the instruction being decoded, the instruction mode used (modes 0-7), and the operand required
(source or
destination).
The IR Decode circuitry is shown on prints K2-5 and K2-6. It consists of one 512 X 4 ROM, ten
256 X
4 ROMs, and two 32 X 8 ROMs, and 74HO1, 7402, 7400, and 7410 logic gates. The
following descriptions are based on instruction types. Complete block diagrams of the microcode flow are available
in
the KD11-E print set (drawing D-FD-KD11-E).

4-30

4.5.3.2 Double-Operand Instructions - Double-operand instructions require two address calculations,
one for the source and one for the destination operand. The microbranch to the sequence of microinstructions that determine the source operand is initiated by the Control Store output signal K2-6 IR
DECODE (1) H. When this signal is enabled, the IR Decode ROMs DOP Decode (E68 and E69 on
print K2-6) check the instruction in the IR (op code bits IR15-12). If the instruction is a doubleoperand type, the ROM outputs are asserted as follows:
|

Type
Instruction

ROM Outputs

K2-6
IR Code 0O

K2-7
MPCO7L

K2-7
MPCO06L.

SUB (SM0*DMO)

DOP (SM0*DMO)

Illegal Instructions

DOP NONMOD (SM0*DMO0)

MOV (SM0*DMO0)

K2-7
K2-7
MPCOSL MPC04L

K2-7
MPCO3L

DOP (MOV+SUB)

MOD (SM0*DMO0)
(ADD, BIC, BIS)

(CMP, BIT)

NOTE
Ground on the MPC lines represents a logic “1.”

Coupled with the microprocessor outputs of the DOP DEC ROM are the outputs of a set of type
74HO1 gates on K2-6. These gates, when enabled, place the contents of the source mode field (IR11:09)
of the PDP-11 instruction being decoded onto the MPC 00:02 lines. These gates are enabled by the K26 SRCH ROM output only when the instruction being decoded is of the double-operand type, the K26 IR DECODE (1) L signal is asserted, and the instruction is not reserved (K2-6 IR CODE 00 L
unasserted).

A summary of the various source microaddresses is shown below:

Instruction

DOP (SM0*DMO)

Source
Mode

Octal
Microbranch Address

0
]
2
3
4
5
6
7

110
111
112
113
114
115
116
117
00

Reserved DOP

NOTE
A ground on the MPC lines represents a logic 1.
4-31

The DOP DEC ROMs described above are also used to decode the microprocessor address for the
various Control Store destination operand routines. When the K2-7 BUT DEST L input is asserted by
the miscellaneous control field circuitry of the Control Store, the DOP DEC ROMs decode the
instructions, determine whether it is a modifying or nonmodifying instruction, and generate the following micro-PC addresses.
ROM Outputs

Type
Instruction

K2-7
MPCO7L.

K2-7
MPCO6L.

K2-7
MPCOSL.

K2-7
MPC0M4L

K2-7
MPCO3L

Move
(SM0O*DMO)

Modify
(ADD BIS BIC but
not MOV or SUB)

Nonmodify
(CMP BIT)

SUB

The circuitry used to decode the destination mode field of the instruction being decoded is similar to
that described above for microaddressing the source operand routine. A set of 74HO1 gates on K2-6 1s
used to place the contents of K2-5 IR 05 (1) H through K2-5 IR 03 (1) H on the lines when enabled.
For double-operand instructions, enabling occurs when the MPC miscellaneous control field asserts
K2-7 BUT DEST L.

ROM E73 on print K2-6 is also considered to be part of the DOP Decoder circuitry. This ROM
decodes all Extended Instruction Set (EIS) instructions, generating the following micro-PC addresses
when K2-6 IR DECODE (1) H is asserted:
ROM Outputs

Type
Instruction

K2-6
IR Code 00

K2-7
MPCO7L

K2-7
MPC06l.

K2-7
MPCOSL

K2-7
MPC04L

K2-7
MPCO3L

SOP

XOR

Reserved

Multiply or Divide
(MUL, DIV)

Arithmetic Shift or
Arithmetic Shift Combined
(ASH,ASHC)

4-32

The K2-6 DEST L output of the EIS Decoder ROM (E73) allows the 74HO01 (E64) on print K2-6 to
place the contents of the destination mode field of the instruction being decoded onto the micro-PC
(MPC00-MPCO02) lines. This microbranching technique is similar to that described above for microaddressing the source operand routine. Use of the EIS instructions does not degrade processor timing
or affect NPR latency.

4.5.3.3 Single-Operand Instructions - Unlike double-operand instructions, single-operand instructions only require one address calculation to obtain the necessary operand. Complete SOP instruction
decoding is done with the two 256- X 4-bit ROMs (ES9 and ES8).
The SOP Microbranch ROM (E59) monitors the necessary IR input lines and asserts the correct
micro-PC address on lines K2-7 MPCO03-L through K2-7 MPC 06 L when the K2-6 IR DECODE (1) L
signal is asserted and the SOP enable signal K2-5 IR 12-14=0 H is true. The K2-6 DEST L output is
also activated when an SOP instruction is decoded. This signal enables the destination mode monitoring circuitry described in the double-operand instruction decoding section. Microaddresses for
SOP instructions are shown below,
Base

Microbranch

Instruction

Address

SOP Modify
(CLR,COM,INC,DEC)

040

SOP Non-M odify
(TST)

160

NEG

150

Rotate and Shift
JSR
JMP

170
150
020

MARK
SWAB

030

MFPI (D)
MTPI (D)
MFPS
MTPS

100
250
130
120

The SOP Microbranch ROM (E59) is also used to decode JSR instructions. This decoding is performed in the same manner as that for SOP instructions. The K2-6 DMO H input to the ROM is used
to detect the illegal instruction JMP or JSR destination mode 0. When this occurs, no micro-PC
address is allowed on the ROM outputs.

4-33

The SOP Decode ROM (E58) monitors the same input signals as the SOP Microbranch ROM. Its
purpose, however, is to decode illegal, reserved, and trap instructions. The three output signals K2-6
IR CODE 00 L through K2-6 IR CODE 02 L are enabled as follows:
IR Code

Instructions

Reserved
[llegal

1
1

1
0

0
1

EMT
Trap

0
0

1
0

0
1

(JMP or JSR Mode 0)

The fourth output signal of the SOP Decdoe ROM enables the destination mode monitoring circuitry
described in the double-operand instruction decoding section.

4.5.3.4 Branch Instructions — Conditional branch instructions are completely decoded by the Branch
14 are all low and the K2-6
DEC ROM (E71 on print K2-6). This ROM is enabled when bits IR11:IR
code bits (N, Z, V,
condition
four
the
are
monitored
lines
IR DECODE (1) L signal is active. The input
MPC 07 L output
K2-7
the
decoded,
is
branch
a
When
8).
and C) and four IR bits (IR15, 10, 9, and
sign-extend the
will
Store
Control
the
in
routine
microcode
signal is enabled. The branch instruction
branch offset and shift it left one place.

4.5.3.5

Operate Instructions — There are three 256- X 4-bit ROMs in the instruction-decoding circui-

try for decoding PDP-11 operate instructions. These ROMs are the Reset/Trap Decode, Trap Decode,
and Op Branch ROMs (E62), all found on K2-6.

The Op Branch ROM (E62) monitors IR output lines IR00:IR07. It is enabled when IR0S and IR15
are low and K2-6 IR DECODE (1) L is active. The PDP-11 operate instructions are decoded into the
following micro-PC addresses on the ROM outputs K2-7 MPC 00 L through K2-7 MPC 03 L.
Microbranch

Instruction

Address

003
011
007
006
004
014

Reset
RTI/RTT
Set Condition Codes
Clear Condition Codes
RTS
Wait

The Reset/Trap Decode ROM (E53) decodes Reset, RTT, and RTI instructions and activates the
outputs K2-6 START RESET H and K2-6 ENAB TBIT H accordingly. This ROM also allows the

lower PSW bits (K2-6 DISABLE LOAD PSW H) to be loaded only from the stack when the processor
is operating in User mode (memory management restriction). It also treats a Reset instruction as a
NOP in User mode.

4-34

The TRAP DEC ROM (E52) has the same inputs as the Op Branch ROM. Its purpose is to decode
Halt, reserved, trap, and illegal instructions, and to enable the outputs accordingly. The K2-3 USER
MODE H input also allows this ROM to treat Halt instructions as reserved instructions when operating in the memory management User mode.

IR Code

4.6

Instruction

Reserved
Illegal
BPT
10T
HALT

1
1
0
1
0
1
1
0
0
0
1
1
Enable HLT RQSTL

AUXILIARY ALU CONTROL

The AUX Control circuitry on the KD11-E consists of three bipolar ROMs, shown on K2-5.
ROM

Name

32- X 8-bit
256- X 4-bit

DOP (E81)
SOP (E60)
ROT/SHIFT (E61)

256- X 4-bit

These ROMs determine the ALU operation to be performed whenever the microcode executes the
action X « Y OP B, where Y designates a scratchpad register and X designates either the B REG or a
scratchpad register.

The AUX DOP ROM (E81) decodes double-operand instructions, and is enabled by K2-8 AUX
SETUP H. The following table expresses the outputs of this ROM as a function of the instruction
being performed. (B represents the B register, A represents any scratchpad register, and F represents
the ALU output.)
ROM Outputs

Instruction
MOV (B)
COMP (B)
ADD
SUB
BIT (B)
BIC (B)
BIS (B)

XOR

ALU
Operation
F—A
F « A minus B
F « A plus B
F « A minus B
F—A.B
F—A.B
F—~A+B

F-cA® B

Func Code
03H

Func Code
02H

Func Code
01H

Func Code
00H

0
0
]
0
1
1
1

1
1
0
1
0
0
0

0
0
0
0
0
1
1

1
0
0
0
1
0
1

4-35

The AUX SOP ROM (E60) decodes single-operand instructions, and is enabled by K2-8 AUX SETUP
H. The following table expresses the ROM outputs as a function of the SOP instruction decoded.

ALU

Instruction

Function

ROM Outputs
Func Code
Func Code

Func Code

03H

02H

OIH

Func Code

O0H

SWAB

F—A

CLR (B)

F—~ZERO

COM (B)

F~A

INC (B)

F~Aplusl

DEC (B)

F « A minus |

]

NEG (B)

F « A minus
B

ADC (B)

F—A

]

0
0

0
|

|
0

|
|
0

plus CBIT (0)
F « A plus
CBIT (1)
SBC (B)

F<A

minus CBIT (0)
F «— A minus
TST (B)

CBIT (1)
F<A

ROR (B)

F<B

ROL (B)

F<B

ASR (B)

F~B

ASL (B)

F<B

MARK

N/A

MFPI

F—A

MTPI

Fe<A

SXT

F — NBIT (0)

F « NBIT (1)
Fe<A

0
0

|
|

MTPS

0
1

MFPD

F<A

MTPD

F—A

MFPS

Fe<A

Auxiliary

control

signals

are

also

necessary

for performing rotate

and

shift operations.

The

ROT/SHFT ROM (E61) on K2-5 decodes these instructions and outputs those control signals
required to shift the contents of the

B REG. Inputs K1-1 BREG 00 (1) H, K1-10 CC N H, and K1-1

CBIT (1) H also determine the K2-5 SERIAL SHIFT H and K2-5 ROT CBIT (1) H signals. The

SERIAL SHIFT H signal is sent to the BYTE MUX (E106 on K1-10), where it is used in determining
the K1-10 SHIFT IN 07 H signal used in the B REG shifting operation. K2-5 ROT CBIT (1) H is used

in the calculation of the new carry condition (C and V Bit ROM - E105 on K 1-10). Note that for all
rotate and shift operations, the AUX SETUP is performed on the B « B step before each X « Y OP B
step previously mentioned. This is done to allow the condition codes to be set up without slowing the
Processor.

Table 4-9 summarizes the auxiliary control instructions.

4-36

Table 4-9

Auxiliary Control for Binary and Unary Instructions
Condition Codes

ALU

Instruction

N and Z

Function

CIN

MOV(B)

Load

Cleared

Not affected

A Logical

CMP(B)

Load

Load like Subtract.

A minus B

BIT(B)

Load

Cleared

Not affected

A e B Logical

BIC(B)

Load

Cleared

Not affected

AeB Logical

BIS(B)

Load

Cleared

Not affected

A < B Logical

ADD

Load

Set if operands are same

Set if carry out.

A plus B

Set if carry.

A minus B

sign and result different.
SUB

Load

Set if there was arithmetic
overflow as a result of the

operation (i.e., if operands
were of opposite signs and
the sign of the source was
the same as the sign of the
result; cleared otherwise.

XOR

Load

Cleared

Not affected

A*B

CLR(B)

Load

Cleared (like Add)

Clear

COM(B)

Load

Cleared

Set

INC(B)

Load

Set if destination held

Not affected

A plus 1

100000 before operand.
DEC

Load

Set if result is 100000.

Not affected

A minus 1

NEG(B)

Load

Set if result is 100000.

Cleared if result is O;

A minus B

A plus CBIT

A minus CBIT

set otherwise.

ADC(B)

SBC(B)

Load

Set if destination was

077777 and C = 1.

177777 and C = 1.

Set if destination was

100000.

O and C = 1; cleared
otherwise.

TST(B)

ROR(B)

Load

Cleared

A Logical

Unaffected

(0)

B Logical

1f(15:01)*C=0
N<C

4-37

Table 4-9 Auxiliary Control for Binary and Unary Instructions (Cont)
Condition Codes

Instruction

ROL(B)

Nand Z

ALU

Function

B Logical

O <« (15)

B Logical

C < (15)

B Logical

(15)

Unaffected

CIN

If(14:00)*C=0

N<«(14)

ASR(B)

7<1

B (7)
Unaffected

If(15:01)=0
N<«N

ASL(B)

7<1
1f(14:01) =0
N<«(14)

SWAB
SXT

Load

Cleared

A Logical

/Z—Load

Cleared

N—Unaffected

MFEPI

Load

Cleared

Unaffected

A Logical

MTPI

Load

Cleared

Unaffected

A Logical

Z—Set

Cleared

Unaffected

A Logical

MTPS

If SRC(7)=0
N-—-Set

If SRC(7)=1

MFPD

Load

Cleared

Unaffected

A Logical

MTPD

Load

Cleared

Unaffected

A Logical

7—Set

Cleared

Unaffected

A Logical

MFEPS

If PS(7)=0
N—Set

If PS(7)=1

4-38

47
4.7.1

DATA TRANSFER CIRCUITRY
General Description

All Unibus data transfers are controlled by the DAT TRAN circuitry on K2-1. This logic monitors the
busy status of the Unibus, controls the processor bus control lines BBSY, MSYN, CI, and CO0, and
detects parity errors (PE), and bus errors (BE).
4.7.2

Control Circuitry

4.7.2.1
Processor Clock Inhibit — All processor data transfers on the Unibus are initiated by K2-8
BUF DAT TRAN (1) H. When K1-5 TAP 30 H goes high, the signal combines with the signal K2-1

EOT L (normally a logic 1 between transfers) to create K2-1 TRAN INH L, shutting off the processor
clock until the transfer is completed.
4.7.2.2 Unibus Synchronization - The synchronizer logic shown in Figure 4-19 (from K2-1) arbitrates
whether the processor or some other Unibus peripheral will control the Unibus. A logic 1 level (+3 V)

at the set input of the E31 flip-flop on K2-1 specifies that the bus is presently in use. Each of the inputs
that combine to create this level monitors a specific set of bus conditions.

K2-1 DATIP (1) L
K2-1 DATIP
(O) L
K2-1

BBSY H

7402

K2-2 NPR H

\10

K2-2 NPG (1) H
K2-2 NO

SACK L
ok

21y

S5
11,6

7474
E31

K2-8 BUF DAT TRAN (1) H—— 7400 \3

DE2

K1-5 TAP 30 H->-2] E49/

START

TRAN H

4Ons ItOOpf
ces

11-3893

Figure 4-19

Unibus Synchronizer

4-39

A Unibus peripheral has asserted a nonprocessor request
(NPR) and wishes to gain control of the bus immediately.

NPR

(K2-2 NPR H)

Another Unibus peripheral already has control of the bus, and
is asserting a bus busy (BBSY) signal.

BBSY

(K2-1 BBSY H)

An NPR device has requested control of the Unibus and the
KDI11-E processor has issued a nonprocessor request grant
(NPG). The condition may exist where the NPR device has
already recognized the NPG and has dropped its NPR signal,
while not yet having asserted a SACK or BBSY.

NPG

[K2-2 NPG (1) H]

A device has requested control of the Unibus. The KD1I1-E
processor has issued a grant, and the device has returned SACK
L, causing NO SACK L to go high. The condition may exist
where only SACK L remains on the Unibus for a period of time
before the peripheral asserts BBSY.

NO SACK L

(K2-2 NO SACK)

When this input is true, all of the above signals are overridden.
It indicates that the processor is performing a DATIP
(Read/Modify/Write) operation, and has control of the Unibus
(BBSY asserted). NPR devices may, however, be granted bus
control, but must wait until the processor releases BBSY before
asserting theirs. (DATIP operations dictate worst-case bus
latencies for NPR devices.)

DATIP (0) L

[K2-1 DATIP (0) 1]

A data transfer is still being completed; therefore, the processor
must wait before initiating another.

BUS SSYN L

If none of the above Bus-in-Use conditions exist, the K2-8 BUF DAT TRAN (1) H signal sets the E31
flip-flop on K2-1 when K1-5 TAP 30 H goes high, and activates K2-1 START TRAN H to start the
transfer. The RC circuit at the output of E36 eliminates any noise that may result from the synchronizer under worst-case conditions.

4.7.2.3 Bus Control - Once the K2-1 START TRAN H signal is activated, the DAT TRAN circuitry

begins a Unibus data transfer operation by asserting K2-1 ENAB ADDRS L, triggering the following
actions:

Enables the bus address drivers (BUS A15:A00 on K1-6).

Enables the BBSY driver (K2-1).

Enables the bus control signals BUS C0 and BUS C1, which determine the kind of transfer
being performed.

Cl1

Co0

]

Operation

DATOB

The actual condition of these control lines is determined by K2-8 BUF CO (1) H and K2-8
BUF C1 (1) H.

4-40

Enables the bus data drivers (BUS D00-BUS D15) if the operation being performed is a
DATO.

4.7.2.4 M8264 NO-SACK Timeout Module - The M8264 is a quad-height module containing circuitry that asserts BUS SACK L on the Unibus if a device requesting Unibus control does not assert
SACK within 10 us after a grant line has been enabled (Figure 4-20).

The grant signals (BUS NPG and BUS BG7 through BUS BG4) are ORed (E3) on the M8264. The
output of the OR gate enables a NAND gate (E6) and triggers a monostable multivibrator (ES). The
signals produced are ANDed (E1) to enable BUS SACK L. The monostable effectively delays (by 10
us) the assertion of BUS SACK L since it produces a 10 us pulse which prevents the AND gate from
being enabled. BUS SACK L, when asserted, will cause the processor to drop the grant line, which will
in turn cause the M8264 to drop BUS SACK L.

This module prevents the processor from being hung if a grant line is asserted and BUS SACK is not
returned by the device requesting bus control. If the requesting device returns BUS SACK, the M 3264
will not assert BUS SACK since the grant line will be dropped before the monostable times out.
As a maintenance aid, a counter is provided (E4) to drive a set of LEDs. The binary counter counts up
one each time BUS SACK is asserted by the M8264 and the number of occurrences is indicated by the
LEDs. The maximum number recorded is 15 before the counter is reset. The counter is cleared and the
monostable multivibrator is reset when BUS DC LO L becomes asserted (i.e., upon system power-up).

4.7.2.5 MSYN/SSYN Time-Out Circuitry - Unibus specifications require that the BUS MSYN L
control signal be enabled no sooner than 150 ns after the bus address, data, and control lines have been
asserted. To meet this requirement,
the circuitry in Figure 4-21 has been incorporated into the DAT
TRAN logic (K2-1).

The multiplexer (E10) shown in Figure 4-22 helps adapt the DAT TRAN circuitry to the type of bus
operation being performed (DATI or DATO). Specific functions performed are as follows:
.

Generates the correct Unibus control signals [K2-1 UBUS CO (1) H and K2-1 UBUS C1 (1)

Inhibits the detection of parity errors during DATO operations.

H].

Generates an End of Transfer (EOT L) signal as soon as BUS SSYN is returned by an
addressed peripheral.

Delays the assertion of BUS MSYN, using the clock signal K1-5 ALLOW MSYN H, which
does not become asserted until the Physical Bus Address register has been loaded.
NOTE

This applies only to DATI or DATIP. During
DATO or DATOB, the bus address is never loaded
in the same microcycle that does the DATO or
DATOB.

4-41

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BUS NPGH

BUSBG7H

BUSBG6
H
BUSBGS5H

)

H—

O®

BUS BG4

____,/

BUS SACK L

RESET

BUS DCLO
—C

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CUP
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AAA

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BUS SACK

ASSERTED HIGH

=
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10 us

ol
K

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)

BUS SACK L
UNASSERTED
11-4578

Figure 4-20

NO-SACK Timeout Module

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The RC circuit shown in Figure 4-21 prevents the MSYN flip-flop (E31) from being clocked until
approximately 150 ns after the bus address and control lines are placed on the bus. Once this latch is
set, BUS MSYN L is activated and the SSYN TIMEOUT one-shot E16 is triggered. When SSYN is
returned by the addressed peripheral, both the MSYN flip-flop (E31) and the SSYN TIMEOUT oneshot are cleared. The processor clock is then freed by the release of K2-1 TRAN INH L. If a DATI or
DATIP operation is being performed, that will be clocked into either the scratchpad, B REG, PSW, or
IR on the next low-to-high transition of K1-5 PROC CLK L.
If a DATO or DATOB operation is being performed, the data bus drivers are disabled after SSYN is
returned from the addressed peripheral but before the MSYN line is unasserted.
4.7.2.6 Bus Errors - Once the SSYN TIMEOUT one-shot is triggered, SSYN must be returned
within 22 us. If SSYN is not returned in this time, E16 times out, setting the TIMEOUT flip-flop
(E32). The output of this latch then generates the signal K2-1 ABORT RESTART L and pulse K2-1
ABORT H. K2-1 ABORT RESTART L reenables the PROC CLK and K2-1 ABORT H sets the Bus
Error flip-flop (E33). This same pulse that sets the Bus Error flip-flop also clears the micro-PC address
latches (MPCO00 through MPC008) on K2-7, forcing the processor to enter the service microroutine on
the next PROC CLK L low-to-high transition.
4.7.2.7

Parity Errors - If a data transfer is being performed with a parity memory (e.g., MS11-JP or

MMI11-DP), all parity errors detected by the memory will be reflected back to the KD11-E on the
Unibus lines BUS PA L and BUS PB L on K2-1 (Figure 4-23).

O
=
— O

— e

Control
PA
PB

Error
Description

No Parity Error
Parity Error on DATI
Reserved for future use
Reserved for future use

Errors detected while performing a DATIP or DATI [K2-8 BUF C1 (1) H unasserted] will result in the
Parity Error flip-flop (E34) being set when SSYN is returned to the processor. Processor operations
resulting from Parity Error will be discussed further in Paragraph 4.11, Service Traps.

4.7.2.8

End of Transfer Circuitry - To synchronize the DAT TRAN logic with the main KD11-E

processor clock, the End of Transfer (EOT) circuitry (Figure 4-24) has been incorporated into the CPU
(K2-1). During a DATI or DATIP, an EOT L signal is generated approximately 100 ns after SSYN is
returned to the processor. That EOT L removes the processor clock disabling signal (Paragraph
4.7.2.1), K2-1 TRAN INH L. During a DATO or DATOB, K2-1 TRAN INH L is unasserted immediately when SSYN is returned.
4.7.2.9

Data-in-Pause Transfer - Another circuit included in the DAT TRAN logic detects Data-in-

Pause

(DATIP)

transfers

and controls the bus

control signal

BBSY.

When

DATIP

(Read /M odify/Write) bus operation is initiated, the flip-flop (E32) is latched, forcing the processor to
hold BBSY L until the DATO portion of the routine has been completed. While BBSY is asserted, no

other Unibus peripheral can seize control of the bus. This feature often determines the maximum bus
latency for NPR devices (K2-1).

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Figure 4-24

11-3897

End-of-Transfer Logic

4.7.2.10 Odd Address Detection — The circuitry shown in Figure 4-25 is incorporated in the KD11-E
to detect odd address errors. ROM E78 (print K2-8) monitors the signals K2-8 BUF DAT TRAN (1)
H, K2-SBYTE H, and K1-6 VBAOO (1) H, and asserts K2-8 DISABLE MSYN L when an odd address
is detected. The multiplexer circuit (E38 on K2-4) forces the processor to always autoincrement or
autodecrement the PC (R7) or the SP (R6) scratchpad registers by two, regardless of the type of
instruction being performed. This is done by preventing the K2-4 DISABLE MSYN +1 L signal from
being asserted.
4.8

POWER FAIL/AUTO RESTART

The KD11-E power fail/auto restart circuitry (K2-3) serves the following purposes:

Initializes the microprogram, the Unibus control, and the Unibus to a known state immediately after power is applied to the computer.

Notifies the microprogram of an impending power failure.

Prevents the processor from responding to an impending power failure for 2 ms after initial
startup.

The actual power fail/auto restart sequences are microprogram routines. The operation of the power
fail/auto restart circuitry depends on the proper sequencing of two bus signals: AC LO and DC LO.
Because of the electrical properties of the Unibus drivers and receivers, the entire computer system
must be powered up for the machine to operate. Therefore, the processor is notified of a power fail in
peripherals, as well as in its own ac source.

4-47

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10

K2-3 R6+7 L —HH

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E38

E20

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K2—8

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K2-9 SS @1

K2-9 SS @@ H

K2-8 BUF DAT TRAN (1) H
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K2-8 AUX CONTROL (1) H

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256 x 4

E78

119 _\KZ-S BYTE H ——
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K2-6 MOVE L

‘4

11-3898

Figure 4-25

Odd Address Detection

The notification of power status of any PDP-11 system component is transmitted from each device by
the signals BUS ACLO L and BUS DC LO L (K2-3). The power-up sequence (Figure 4-26) shows that
BUS DC LO L is unasserted before BUS AC LO L is unasserted. When BUS DC LO L is not asserted,
it is assumed that the power in every component of the system is sufficient to operate. When BUS AC
LO L is not asserted, there is sufficient stored energy in the regulator capacitors of the power supply to
operate the computer for 5 ms, should power be shut down immediately.

As ac power is removed, BUS AC LO L is asserted first by the power supply warning the processor of
an impending power failure. When BUS DC LO L is asserted, it must be assumed that the computer
system can no longer operate predictably. Memories manufactured by DIGITAL use BUS DCLO L
as a switched signal, turning them off even if power is still available. Time at2 (Figure 4-26) is the time
delay between the assertion of BUS AC LO L and the assertion of BUS DC LO L; this time delay must
be greater than 5 ms. This allows for power to be rapidly cycled on and off. According to PDP-11
specifications, upon system startup a minimum of 2 ms run time is guaranteed before a power fail trap
occurs, even if the line power is removed simultaneously with the beginning of the power-up sequence.

After the power fail trap occurs, a minimum of 2 ms run time is guaranteed before the system shuts
down. Given the tolerances permitted in the timing circuitry used in most in most equipment, at2 must
be greater than 5 ms.

4-43

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INIT

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11-3950

Figure 4-26

BUS AC LO and BUS DC LO Timing Diagram

When a pending power fail is sensed, a program trap occurs, causing the present contents of PC (R7)
and the PSW to be pushed onto the memory stack, as determined by the contents of R6 (Stack Pointer
register). The PSW is then loaded with the contents of location 265 and R7 with the contents of 24s.
Processing is continued with the new R7 and PSW. The user’s program must prepare for the impending power failure by storing away volatile registers and reloading location 243 and 265 with a power-up
vector. This vector points to the beginning of a restart routine.

When power is restored, the processor loads the PC (R7) with the contents of location 245 and the
PSW with the contents of location 26s. After loading these registers, the user program presumably will
prepare locations 245 and 26; for another power failure. If the HLT RQST L input is asserted by an
external switch closure, the processor powers up through locations 245 and 26s, and halts.
Schematics for the power fail, auto restart, and bus reset logic are on K2-3. One-shot E14 generates a
150-ms processor INIT pulse as soon as BUS DC LO L is nonasserted after power is applied to the
processor. At the end of 150 ms, the PUP one-shot (E7) is fired if BUS DC LO L is not asserted and the
processor begins the PC and PSW load routine. The PUP one-shot generates a 2-ms pulse, during

which the assertion of BUS AC LO L is ignored.

The triggering of the 150-ms INIT one-shot also resets the POWER INIT flip-flop (E24). Setting this
flip-flop forces the Control Store to run the power-up routine beginning at micro-PC address 001. It is
this routine that reads locations 24 and 265 for the new PC and PSW.

After PUP has timed out, the assertion of BUS AC LO L would fire the one-shot PDWN (E7). Upon
entering the next service microcode state, K2-3 PFAIL H is latched into E19 (K2-2), causing a power
fail trap to be recognized by the microprogram on entering the next service state. Various traps are
arbitrated by the BUT service ROMs (E50 and E51 on K2-3).

If a momentary power failure occurs that causes the assertion of BUS AC LO L but does not cause the
assertion of BUS DC LO L, the processor will restart when the PDWN one-shot times out, retriggering the INIT one-shot.

4-49

When a Reset instruction is decoded by ROM ES53, the ROM output signal START RESET H is

clocked into the Start Reset flip-flop (E54 on K2-2). This flip-flop output triggers a 100-ms INIT, after
which the processor continues operation.

4.9

PROCESSOR CLOCK

The processor clock circuitry for the KD11-E is shown in Figure 4-27 and on print K1-5. A delay line
is used to generate a pulse train, to which the entire processor is synchronized. Because the KD11-E is
a fully clocked processor, events that result in the alteration of storage registers occur only on defined
edges of the processor clock.

If all clock disable inputs are unasserted, the clock will begin running as soon as +5 V is applied. The
length of an operating cycle can be either 180 ns or 240 ns, depending on the nature of the instruction
being performed. Most microinstructions employ the shorter cycle, with the longer one only necessary
when the machine is performing a DATO or DATOB, or in situations where the condition code must
be determined before an operation can be performed. Long cycles are also used in loading the Bus
Address register when memory management is turned on.

The clock is turned on and off by the gating of the feedback through the delay line. Taps of 120 ns, 90
ns, and 30 ns make it possible to vary the length of the cycle, according to a signal input [K2-8 LONG
CYCLE (1) L] from the Control Store, as the processor clock timing diagrams in Figure 4-17 show.
The indicated jumpers are inserted at W1 and W2 in the standard configuration; the overall cycle can
be slowed down slightly (approximately 30 ns) by inserting jumpers at the alternate locations (shown
on K1-5 by dotted lines) instead. It is also possible to disable the clock manually and use the manual
clock input; any TTL-compatible waveform may be employed. Multiplexer E94 issues the feedback
signal that, in effect, determines the length of the cycle.

The clock is turned off by the appropriate signal under the following conditions:
1.

During a BUS INIT that is not caused by a RESET

During the INIT portion of the power-up routine

During the INIT portion of the power-down routine

During a Reset

During the BUT Service arbitration delay

During a priority interrupt

While BUS SACK is asserted by an interrupting device (not for NPR transfers)

During bus data transfers

After a Halt instruction is executed

10.

When the manual clock is enabled

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11-3899

Figure 4-27

Processor Clock Circuit

4-51

4.10

PRIORITY ARBITRATION

4.10.1
Bus Requests
The KD11-E responds to bus requests (BRs) in a manner similar to that of the other PDP-11 proces-

sors. Peripherals may request the use of the Unibus in order to make data transfers or to interrupt the
current processor program by asserting a signal on one of the four BR lines, numbered BR4, BRS,
BR6, and BR7 in order of increasing priority. For example, if two devices, one at priority 5 and the
other at priority 7, assert BRs simultaneously, the device at priority 7 is serviced first. Furthermore, if
the processor priority, determined by PSW bits 07:05, is at level 4, only devices requesting BRs at levels
higher than 4, such as BR7, BR6, or BRS, are serviced. Table 4-10 contains the order of priority for all
BRs and other traps.
Table 4-10

Priority Service Order

Priority

Service Order

Highest

Halt Instructions
Odd Address
Memory Management

Lowest

Error
Time-Out
Parity Error
Trap Instruction
Trace Trap
Stack Overflow
Power Fail
Halt from Console
BR7
BR6
BRS5S
BR4
Next Instruction Fetch

Because a BR can cause a program interrupt, it may be serviced only after completion of the current
instruction in the IR. A device that requests a program interrupt must, at the appropriate time, place a
vector address on the Unibus data lines. The processor first stacks away the current contents of PSW
and R7; then a new PSW is loaded from the contents of the vector address plus two and a new PC is
loaded with the contents of the vector address. Further discussion of how the processor handles this
BR routine is contained in the section on Service (Paragraph 4.11).

4-52

Arbitration logic for BRs is contained on print K2-2 and in Figure 4-28. All BRs are received directly
from the Unibus (Unibus receivers E17), and latched into register E19 (quad D-type latch, 74S174)
when the microprogram enters the next service state [K2-9 BUT SERVICE (1) H is true]. The BR
Priority Arbitration ROM (E29) then determines whether the present processor priority [PSW (7:4)] is
higher than the highest BR received and, if not, which BR received has the highest priority. Arbitration
performed by E29 in the order of priority are shown below.
HLT RQST

PSW7

BR7

PSW6
BR6

PSWS5
BRS

PSW4
BR4

K2-2 RESET (1) H
K2-2 ALLOW

8 k2-2 BG INH

K2-2 SACK RET (1) H

K2-2 NO SACK H

13
10

K2-2 BUT SERVICE L |8

k-2 NPG (1) H

N i1

K2-2 CLK BG H

En/

9] E7Z

Zfi?;‘s

s
ES

/77

02—

O6~
O

C57

200ns
R18

K2-2 BG ENAB H

=<
/77

E2T>

K2-2 NPG ENABH

C56

BUS NPR L

AS?

K2-2

RCD

INIT H

So
)3
4q

K2-2 PROC INIT H

K2-2 NPR

12) ES

K2-2 RCDINIT L

11-3901

Figure 4-28

Priority Arbitration Synchronizer

4-53

If the highest BR received is of a higher priority level than the processor, the corresponding grant
enable ROM output is asserted low (Figure 4-29). With no HLT RQST or trap instruction pending,
the processor clock will be disabled by the K2-2 BG INH L signal. The actual bus grant is not transferred to the Unibus until the Enable BG flip-flop (E12) is set. Grants (both BG and NPG) are
controlled by the synchronizer logic shown in Figure 4-28 and on print K2-2.

This circuitry arbitrates whether a bus grant (BG) or a nonprocessor grant (NPG) will result, depending on which flip-flop input line (set or reset) was deactivated first. The set input K2-2 BUT SERVICE
L will cause the flip-flop to issue the BG ENAB H signal after a delay of 175 ns. Once the flip-flop is
set, the bus grant arbitrated by the BR Priority Arbitration ROM (E29) is channeled onto the Unibus
(bus driver E75). When the requesting peripheral receives BG, it returns BUS SACK L.
Upon receiving BUS SACK L, the processor clears its Enable BG flip-flop, removing the bus grant
from the Unibus, and sets the SACK RET flip-flop to keep the processor clock disabled. Removal of
bus grant causes the peripheral to drop its BUS SACK L (provided that BBSY is unasserted), assert
BUS INTR L and BBSYL, and enable a vector address onto the Unibus data lines. The processor then
deskews the removal of SACK, clears the SACK RET flip-flop (ES), and enables the processor clock
again. Once in operation, the processor clocks the peripheral vector address into the B REG, returns
BUS SSYN L, and begins running the microcode trap routine that branches the processor to the
interrupt handling program determined by the vector obtained.

4.10.2

Nonprocessor Requests (NPRs)

NPRs are a facility of the Unibus that permit devices on the Unibus to communicate with each other
with minimal participation of the processor. The function of the processor in servicing an NPR is to
yield control of the bus in a manner that does not disturb the execution of an instruction by the
processor. For example, the processor will not relinquish the bus following the DATI portion of a
DATIP transfer.

When the reset input of E5 (K2-2 NPR H) becomes unasserted before the set input, and BUS SACK L
is not true, the flip-flop issues K2-2 NPG ENAB H, enabling the BUS NPG H Unibus line and
granting the bus to the DMA device. The requesting device then returns BUS SACK L, clearing the
NPG, and waits until the bus is free (no BBSY).

4.10.3

Halt Grant Requests

The KDI11-E implements what is, in effect, another priority level by monitoring the
HALT /CONTINUE switch on the front panel. When a Halt is detected (HLT RQST L asserted), the
processor recognizes it as an interrupt request (refer to priority levels in Paragraph 4.10.1) upon entering the next service microstate. The processor then inhibits the processor clock and returns a recognition signal (K2-2 HLT GRANT H), causing the console to drop HLT RQST L and assert BUS SACK
L, gaining complete control of the Unibus and the KD11-E.

The user can maintain the processor in this inactive state (Halted) indefinitely. When the HALT switch
is released, the user’s console releases BUS SACK L, and the processor continues operation as if
nothing had happened.

4-54

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4-55

2-016tg

SERVICE TRAPS

4.11
4.11.1

General Description

All interrupts, error traps, and instruction traps are recognized and serviced by the KD11-E when the
processor enters what is called the service microinstruction state. The functions performed during this
state are most critical to the operation of the processor.

When the service state is entered, all bus interrupts, error traps, and instruction traps realized during
the performance of the last instruction are arbitrated by the service ROMs (E50 and E51 on print K23). Each trap condition is then serviced according to its priority, as listed in Table 4-10.

4.11.2

Circuit Operation

The service ROMs (E50 and E51 on print K2-3) service a specific trap by generating a vector address
unique to that trap condition (Table 4-11). Upon leaving the service state, the processor 1s forced to
push its present program counter (PC) and processor status word (PSW) onto its memory stack and
fetch a new PC from the location specified by the vector address. A new PSW is then obtained from the
next memory location after the vector. The end result of these operations is that the processor 1s now
performing a software subroutine written by the user that could correct or indicate the occurrence of a
specific error.

The various trap conditions that cause the processor to vector are as follows:

Bus Errors

A bus error indicates that the processor has attempted to access

nonexistent memory or odd address (non-byte), or a memory

location that did not return BUS SSYN within 22 us. The detection circuitry for bus errors is described in Paragraph 4.7.2.6 of

this manual.

Stack Overflow Error

Any attempt by the processor to decrement the contents of the

Parity Error

Parity error detection circuitry is described in Paragraph

Power Failure

Trace Trap

Reserved Instructions
Illegal Instructions
EMT Instructions

Stack Pointer register (R6) below the 400-location stack limit
(K1-10 8-15 = 0 H will result in the Stack Overflow flip-flop
(E24 on K 2-3) being set on the next transition of K1-5 PROC
CLK L. [Note that this does not apply to user stack (R16).]
4.7.2.7.

The power failure circuitry is described in Paragraph 4.8.

This trap is program-controlled by the user, allowing him to

insert a processor /user interactive subroutine into his main program. The circuitry is described in Paragraph 4.2.6.

Signals IR CODE 00 L-IR CODE 02 L are generated by the IR
Decode ROMs on K2-6 for these conditions. Their decoding 1s
discussed in Paragraph 4.5.3.

Trap Instructions

Upon entering the service microinstruction state, the service ROMs (E50 and E51 K2-3) monitor any
combination of the above trap conditions which, if true, cause the assertion of microprocessor address
line K2-7 MPC 00 L. While still in the service state, the ROM also generates a specific vector address
(Table 4-11), using outputs K2-3 C2 H, K2-3 C3 H, and K2-3 C4 H, and channels it onto the processor
AMUX lines to the SSMUX by activating K1-10 AMUX SO H.

4-56

Vector Addresses

Table 4-11
Octal Unibus

Trap Conditions

Vector Address

004

Time-Out, Odd Address, and Stack Overflow Errors

014
020
024
030
034
114
250

T-Bit Trap (BPT)
Input/Output Trap (I0T)
Power Fail
Emulator Trap (EMT)
Trap Instruction
Memory Parity Errors
Memory Management Errors

010

Illegal and Reserved Instructions

Before leaving the service state, the service ROMs also clear the condition that caused the original
trap. This is done either by asserting K2-3 STOV SERV H or K2-3 PFAIL SERYV H, or by performing
the steps in the trap service routine. For those traps specified by the IR Code lines, however, it is
necessary to remove the instruction in the IR. This is done through microcode output K2-9 BUT
SERVICE (1) H, which ORs with K2-2 PROC INIT H to generate K2-3 SERV IR H and, hence, K2-3
SERV IR (1) L, removing the trap instruction from the IR. This prevents the processor from looping
|

on the same trap condition.

For bus requests (BRs), the BUS INTR L control signal is allowed to force K2-7 MPC 00 L during
service, provided that there are no other traps of higher priority. By enabling this line, the processor
will branch to the trap routine. Higher priority BR interrupts are prevented from receiving BG by K29 BUT SERVICE (1) H.

MEMORY MANAGEMENT

4.12
4.12.1

4.12.1.1

General

Introduction — This section describes the memory management unit of the KD11-E Central

Processor. The KD11-E provides the hardware facilities necessary for complete memory management
and protection. It is designed to be a memory management facility for systems where the memory size
is greater than 28K words and for multiuser, multiprogramming systems where protection and reloca-

tion facilities are necessary.

4.12.1.2 Programming - The memory management hardware has been optimized toward a multiprogramming environment and the processor can operate in two modes, Kernel and User. When in
Kernel mode, the program has complete control and can execute all instructions. Monitors and supervisory programs would be executed in this mode.

B
=

When in User mode, the program is prevented from executing certain instructions that could:
Cause the modification of the Kernel program.
Halt the computer.

Use memory space assigned to the Kernel or other users.
Issue a Reset.

4-57

In a multiprogramming environment, several user programs could be resident in memory at any given
time. The task of the supervisory program would be to: control the execution of the various user
programs, manage the allocation of memory and peripheral device resources, and safeguard the integrity of the system as a whole by careful control of each user program.

In a multiprogramming system, the management unit provides the means for assigning pages (relocatable memory segments) to a user program and preventing that user from making any unauthorized
access to those pages outside his assigned area. Thus, a user can effectively be prevented from accidental or willful destruction of any other user program or the system executive program.
Hardware-implemented features enable the operating system to dynamically allocate memory upon
demand while a program is being run. These features are particularly useful when running higher level
language programs, where, for example, arrays are constructed at execution time. No fixed space is
reserved for them by the compiler. Lacking dynamic memory allocation capability, the program would
have to calculate and allow sufficient memory space to accommodate the worst case. Memory management eliminates this time-consuming and wasteful procedure.
4.12.1.3 Basic Addressing — The addresses generated by all PDP-11 family central processor units
(CPUs) are 18-bit addresses. Although the PDP-11 family word length is 16 bits, the Unibus and CPU
addressing logic actually is 18 bits. Thus, while the PDP-11 word can only contain address references
up to 32K words (64K bytes) the CPU and Unibus can reference addresses up to 128K words (256K
bytes). These extra two bits of addressing logic provide the basic framework for expanding memory
references.
In addition to the word length constraint on basic memory addressing space, the uppermost 4K words
of address space are always reserved for Unibus I/O device registers. In a basic PDP-11 memory
configuration (without management), all address references to the uppermost 4K words of 16-bit
address space (160000-177777) are converted to full 18-bit references with bits 17 and 16 always set to
1. Thus, a 16-bit reference to the I/O device register at address 173224 is automatically internally
converted to a full 18-bit reference to the register at address 773224. Accordingly, the basic PDP-11
configuration can directly address up to 28K words of true memory, and 4K words of Unibus I/O
device registers.
4.12.1.4 Active Page Registers - The memory management unit uses two sets of eight 32-bit Active
Page registers (shown on print K1-7). An APR is actually a pair of 16-bit registers: a Page Address
register (PAR) and a Page Descriptor register (PDR). These registers are always used as a pair and
contain all the information needed to describe and relocate the currently active memory pages (Figure
4-30).

One set of APRs is used in Kernel mode, and the other in User mode. The choice of which set to be
used is determined by the current CPU mode contained in the processor status word.

4-58

~No oabdhwd
=0

KERNEL ACTIVE PAGE REGISTER

PAR

PDR

~NoO oo bW
—- O

USER ACTIVE PAGE REGISTER

PAR

PDR
11-1396

Figure 4-30

4.12.1.5

Active Page Registers

Capabilities Provided by Memory Management

Memory Size (words)

124K, max (plus 4K for I/O and registers)

Address Space

Virtual (16 bits)
Physical (18 bits)

Modes of Operation

Kernel and User

Stack Pointers

2 (one for each mode)

Memory Relocation
Number of Pages
Page Length
Memory Protection
»

16 (8 for each mode)
32 to 4096 words
No access
Read-only

Read/write
4.12.2

Relocation

4.12.2.1

Virtual Addressing - When the memory management unit is operating, the normal 16-bit
direct address is no longer interpreted as a direct physical address (BA) but as a virtual address (VBA)
containing information to be used in constructing a new 18-bit physical address. The information
contained in the VBA is combined with relocation and description information contained in the Active
Page register (APR) to yield an 18-bit BA.

4-59

Because addresses are automatically relocated, the computer may be considered to be operating in
virtual address space. This means that no matter where a program is loaded into physical memory, it
will not have to be “relinked”; it always appears to be at the same virtual location in memory.
The virtual address space is divided into eight 4K-word pages. Each page is relocated separately. This
is a useful feature in multiprogrammed timesharing systems. It permits a new large program to be
loaded into discontinuous blocks of physical memory.

A page may be as small as 32 words, so that short procedures or data areas need occupy only as much
memory as required. This is a useful feature in real-time control systems that contain many separate
small tasks. It is also a useful feature for stack and buffer control.

A basic function is to perform memory relocation and provide extended memory addressing capability
for systems with more than 28K of physical memory. Two sets of Page Address registers are used to
relocate virtual addresses to physical addresses in memory. These sets are used as hardware relocation
registers that permit several users’ programs, each starting at virtual address 0, to reside simultaneously in physical memory.

4.12.2.2 Program Relocation - The Page Address registers are used to determine the starting address
of each relocated program memory. Figure 4-31 shows a simplified example of the relocation concept
as implemented by the circuitry on print K1-6.

CPU

MEM

MGMT

RELOCATION

CONSTANT

VRTUAL

A = 6400

(VBA)

B = 100000

PHYSICAL MEMORY

- —— |
PROGRAM

100000

PHYSICAL ADDRESS(BA)

PROGRAM A
006400

000000
1n-3906

Figure 4-31

Simplified Memory Relocation Example

4-60

Program A, starting address 0O, is relocated by a constant to provide physical address 6400s. If the next
processor virtual address is 2, the relocation constant will then cause physical address 6402g, which is
the second item of Program A, to be accessed. When Program B is running, the relocation constant is

changed to 100000s. Then, Program B virtual addresses, starting at 0, are relocated to access physical
addresses starting at 100000s. Using the Active Page Address registers to provide relocation eliminates
the need to “‘relink” a program each time it is loaded into a different physical memory location. The
program always appears to start at the same address.
A program is relocated in pages consisting of from 1 to 128 blocks. Each block is 32 words in length.
Thus, the maximum length of a page is 4096 (128 X 32) words. Using all of the eight available Active
Page registers in a set, a maximum program length of 32,768 words can be accommodated. Each of the
eight pages can be relocated anywhere in the physical memory, as long as each relocated page begins
on a boundary that is a multiple of 32 words. However, for pages that are smaller than 4K words, only
the memory actually allocated to the page may be accessed.
The relocation example shown in Figure 4-32 illustrates several points about memory relocation.

Although the program appears to be in contiguous address space to the processor, the 32Kword physical address space is actually scattered through several separate areas of physical
memory. As long as the total available physical memory space is adequate, a program can be
loaded. The physical memory space need not be contiguous.
Pages may be relocated to higher or lower physical addresses with respect to their virtual

address ranges. In the example shown in Figure 4-32, page 1 is relocated to a higher range of
physical addresses, page 4 is relocated to a lower range, and page 3 is not relocated (even
though its relocation constant is non-zero).
3.

All of the pages shown in the example start on 32-word boundaries.

Each page is relocated independently. There is no reason why two or more pages could not
be relocated to the same physical memory space. Using more than one Page Address register
in the set to access the same space would be one way of providing different memory access
rights to the same data, depending on which part of a program was referencing that data.

PROCESSOR

KT11-D

VIRTUAL ADDRESS
RANGES

PAGE| RELOCATION
NO. [ CONSTANT

PHYSICAL MEMORY
SPACE

160000-177776

1500XX

400000

417776

140000
- 157776

0200XX

320000

337776

120000- 137776

1000XX

250000

267776

100000 -117776

0200XX

150000

167776

060000 - 077776

0600XX

100000

117776

040000-057776

2500 XX

060000

O77776

020000-037776

3200 XX

020000

037776

000000-017776

4000 XX
11-1398

Figure 4-32

Relocation of a 32K Word Program into
124K -Word Physical Memory

4-61

4.12.2.3

Memory Units

Block

32 words

No. of Pages
Size of Relocatable Memory

8 per mode
27,768 words max (8 X 4096)

Page

4.12.3

1 to 128 blocks (32 to 4096 words)

Protection

A timesharing system performs multiprogramming; it allows several programs to reside in memory
simultaneousiy, and to operate sequentially. Access to these programs, and the memory space they
occupy, must be strictly defined and controlled. Several types of memory protection must be afforded
a timesharing system. For example:

User programs must not be allowed to expand beyond allocated space, unless authorized by
the system.

Users must be prevented from modifying common subroutines and algorithms that are resident for all users.

Users must be prevented from gaining control of or modifying the operating system
software.

The memory management option provides the hardware facilities to implement all of the above types
of memory protection.

4.12.3.1 Inaccessible Memory — Each page has a 2-bit access control key associated with it. The key 1s
assigned under program control. When the key is set to 0, the page is defined as non-resident. Any
attempt by a user program to access a non-resident page is prevented by an immediate abort. Using
this feature to provide memory protection, only those pages associated with the current program are
set to legal access keys. The access control keys of all other program pages are set to 0, which prevents
illegal memory references.

4.12.3.2 Read-Only Memory - The access control key for a page can be set to 2, which allows read
(fetch) memory references to the pages, but immediately aborts any attempt to write into that page.
This read-only type of memory protection can be afforded to pages that contain common data, subroutines, or shared algorithms. This type of memory protection allows the access rights to a given
information module to be user-independent. That is, the access right to a given information module
may be varied for different users by altering the access control key.

A Page Address register in each of the sets (Kernel and User modes) may be set up to reference the
same physical page in memory and each may be keyed for different access rights. For example, the
User access control key might be 2 (read-only access), and the Kernel access control key might be 6
(allowing complete read/write access).

4.12.3.3 Multiple Address Space - There are two complete, separate PAR /PDR sets provided: one set
for Kernel mode and one set for User mode. This affords the timesharing system with another type of
memory protection capability. The mode of operation is specified by the processor status word current
mode field, or previous mode field, as determined by the current instruction.

4-62

Assuming the current mode PSW bits are valid, the Active Page register sets are enabled as follows:
PSW (Bits 15,14)

PAR/PDR Set Enabled

Kernel mode

(l)(l)

Illegal (all references aborted on access)

User mode

Thus, a User mode program is relocated by its own PAR/PDR set, as are Kernel programs. This
makes it impossible for a program running in one mode to accidently reference space allocated to
another mode when the Active Page registers are set correctly. For example, a user cannot transfer to
Kernel space. The Kernel mode address space may be reserved for resident system monitor functions,

such as the basic input/output control routines, memory management trap handlers, and timesharing
scheduling modules. By dividing the types of timesharing system programs functionally between the
Kernel and User modes, a minimum amount of space control housekeeping is required as the timeshared operating system sequences from one user program to the next. For example, only the user
PAR/PDR sets needs to be updated as each new user program is serviced. The two PAR /PDR sets

implemented in the memory management unit are shown in Figure 4-30.
4.12.4

Active Page Registers
The memory management unit provides two sets of eight Active Page registers (APRs). Each APR

consists of a Page Address register (PAR) and a Page Descriptor register (PDR). These registers are

always used as a pair and contain all the information required to locate and describe the current active
pages for each mode of operation. One PAR /PDR set is used in Kernel mode and the other is used in

User mode. The current mode bits (or in some cases, the previous mode bits) of the processor status
word determine which set will be referenced for each memory access. A program operating in one

mode cannot use the PAR /PDR sets of the other mode to access memory. Thus, the two sets are a key
feature in providing a fully protected environment for a timesharing multiprogramming system.

A specific processor [/O address is assigned to each PAR and PDR of each set. Table 4-12 is a
complete list of address assignments.

NOTE
Unibus devices (except DMA and programmer’s
console) cannot access PARs or PDRs. The internal
address decode logic (print K1-10) allows only the
processor to access these registers.

Table 4-12

PAR/PDR Address Assignments

Kernel Active Page Registers

No.

User Active Page Registers

PAR

PDR

No.

PAR

PDR

772340

772342

772300
772302

0
1

777640
777642

777600
777602

772304
772306

2
3

777644
777646

777604
777606

772344

772346

772350

772310

777650

777610

772352

772312

777652

777612

772354

772314

777654

777614

772356

772316

777656

1777616

4-63

In a fully protected, multiprogramming environment, the implication is that only a program operating
in the Kernel mode would be allowed to write the PAR and PDR locations for the purpose of mapping
user’s programs. However, there are no restraints imposed by the logic that will prevent User mode
programs from writing into these registers. The option of implementing such a feature in the operating
system, and thus explicitly protecting these locations from user’s programs, is available to the system
software designer.

4.12.4.1 Page Address Registers (PAR) - The Page Address register (PAR), shown on print K1-7 and
1 in Figure 4-33 contains the 12-bit Page Address Field (PAF) that specifies the base address of the
page.

11-1036

Figure 4-33

Page Address Register

Bits 15-12 are unused and reserved for possible future use.

The Page Address register may be alternatively thought of as a relocation constant, or as a base
register containing a base address. Either interpretation indicates the basic function of the Page
Address register (PAR) in the relocation scheme.

The Page Address register (PAR) may be regarded as either a base register containing a base address or
a relocation constant. Bits are fed directly from the SSMUX to an address selected by the PAR/PDR
ADRS MUX (E89 on print K1-7) when enabled by K1-10 PAR & PDR LOW L. The three scratchpad
memories that comprise the PAR (E76, E77, and E78 on print K1-7) are clocked by K1-5 REG CLK
H. The two associated with PAR 03:00 and PAR 07:04 are enabled by K1-10 LOAD PAR LOW L,
while the other (PAR 11:08) is enabled by K1-10 LOAD PAR HIGH L. Outputs of the PARs are fed
directly to the KTMUX on print K1-9, and can be channeled onto the scratchpad output lines
(SP15:00) when K1-10 PAR & PDR L is asserted and K1-10 KTMUX SO L is unasserted. This allows
the contents of the registers to be accessed by a DATI or DATIP.

4.12.4.2 Page Descriptor Registers — The Page Descriptor register (PDR) comprises four scratchpad
memories (E79, E86, E87, and E88 on print K 1-7) and contains information regarding page expansion,
page length, and access control (Figure 4-34). Bits are fed directly from the SSMUX to an address
selected by the PAR/PDR ADRS MUX (E89 on print K1-7) and clocked by K1-5 REG CLK H.

PAGE LENGTH FIELD

EXPANSION

WRITTEN INTO
DIRECTION

ACCESS CONTROL

f//// .

FIELD

Figure 4-34

Page Descriptor Register

4-64

Access Control Field (ACF)

This 2-bit field (PDR 02:01) of the PDR describes the access rights to the specified page. The access
codes or “keys” [K1-7ACF 2 (1) H and K1-7 ACF 1 (1) H from E86] specify the manner in which a
page may be accessed and whether or not a given access should result in an abort of the current
operation. A memory reference that causes an abort is not completed and is terminated immediately.
Aborts are caused by attempts to access non-resident pages, page length errors, or access violations,
such as attempting to write into a read-only page. All memory management traps vector through
location 250 and can be used as an aid in gathering memory management information.
In the context of access control, the term ““write” is used to indicate the action of any instruction which
modifies the contents of any addressable word. A ““write” is synonymous with what is usually called a
“store” or “modify’’ in many computer systems. Table 4-13 lists the four ACF keys and their functions. The ACF is written into the PDR under program control.
Table 4-13

ACF

Key | Descriptiomn

Access Control Field Keys

Function

Non-resident

Abort any attempt to access this non-resident page.

Resident read-only

Abort any attempt to write into this page.

Unused

Abort all accesses.

Resident read /write

Read or write allowed. No trap or abort occurs.

Expansion Direction (ED)

The ED bit located in PDR bit 3 indicates the authorized direction in which the page can expand. A
logic 0 in this bit (ED = 0) indicates the page can expand upward from relative zero. A logic 1 in this
bit (ED = 1) indicates the page can expand downward toward relative zero. The ED bit 1s written into
the PDR under program control.
When the expansion direction is upward (ED = 0), the page length is
increased by adding blocks with higher relative addresses. Upward expansion is usually specified for
program or data pages to add more program or table space. An example of page expansion upward is
shown in Figure 4-35.

When the expansion direction is downward (ED = 1), the page length is increased by adding blocks
with lower relative addresses. Downward expansion is specified for stack pages so that more stack
space can be added. An example of page expansion downward is shown in Figure 4-36.
NOTE
To specify a block length of 42 for an upward-expandable page, write the highest authorized block number directly into the highest byte of PDR. Bit 15 is
not used because the highest allowable block number
is 177,.

4-65

PDR

PAR

000

001

111

000

0101001

OOO0O

PAF = 0170 J
= 514 = 41,,=BLOCK
PLF

O 110

NO.

ED=0=UPWARD EXPANSION
ACF=6=READ/WRITE
NOTE:
TO

SPECIFY A

PAGE,

WRITE

BLOCK

BYTE OF PDR. BIT 15 IS
NUMBER

VIRTUAL

LENGTH

HIGHEST

OF 42

AUTHORIZED

NOT USED

FOR AN UPWARD EXPANDABLE
BLOCK

INTO

HIGH

BECAUSE THE HIGHEST ALLOWABLE

NO.

DIRECTLY

BLOCK

17 7g

ADDRESS

BLOCK

NO
> PDR

BLOCK NO.-+PAGE

LENGTH

ERROR (PLE)

000

/////// //%
ADDRESS

RANGE

OF POTENTIAL PAGE
EXPANSION

CHANGING THE

70/

PLF

ANY

BLOCK

LGREATER

NUMBER

THAN 41, (51g)

(VA<12:06>) 51g)
wiLL CAUSE A PAGE

/////

LENGTH

ABORT.

BLOCK 52¢

//
L // 7
024176

BLOCK 514
024100

—

0170XX
51

START
BLOCKS

024 1XX

END

O17276
AUTHORIZED

PAGE

BLOCK 2

LENGTH =42,, BLOCKS

OR O

017200

THRU 51g=

52g BLOCKS

017176

BLOCK

1
017100
017076

BLOCK

017000

<+—BASE ADDRESS OF PAGE
11-1030

Figure 4-35

Example of an Upward-Expandable Page

4-66

«——ACTIVE PAGE REGISTER

CONTENTS —
PDR

PAR

000 001 111

01010110

000

-—

PAF = 0170

0000

{10

-—

PLF=126g
= 8640

ED=1=DOWNWARD EXPANSION

TO SPECIFY

PAGE

LENGTH

WRITE

COMPLEMENT

IN THIS

EXAMPLE, A

PLF

FOR A DOWNWARD

BLOCKS

42-BLOCK

REQUIRED
PAGE

EXPANDABLE

INTO

PAGE,

HIGH BYTE

OF PDR.

REQUIRED.

IS DERIVED
AS FOLLOWS
:

4240 =52g; TWO'S COMPLEMENT
= 1264
VIRTUAL

ADDRESS

BLOCK NO.<PDR

BLOCK NO.- PAGE

036776

LENGTH

ERROR (PLE)

FIRST BLOCK OF DOWNWARD

BLOCK 177g

EXPANDABLE PAGE

036700

036676
BLOCK 176g
036600

AUTHORIZED
PAGE
LENGTH=42
jo BLOCKS

036576

BLOCK

1758

0170XX
126

PAGE BASE
BLOCKS

0316XX
52

START
BLOCKS

0367XX

END

NUMBER

036500

031676

BLOCK

126g

031600

72777
N

BLOCK

1254¢

G 7
.
//////////%
BLOCK

ADDRESS

RANGE

OF POTENTIAL

PAGE

EXPANSION BY
CHANGING THE PLF

124g

j///// ///%

W
§??§/ i)

:2;;;5OCK537§2§:

Z///////QJE@QQX
BLOCK

Figure 4-36

BLOCK

REFERENCE

THAN

126 g

LESS

(VA <12:06>
LESS THAN {26g)
WILL CAUSE A

LENGTH

PAGE

ABORT.

<— BASE ADDRESS OF PAGE

Example of a Downward-Expandable Page

4-67

11-1031

Written Into (W)

The W bit located in PDR bit position 6 indicates whether the page has been written into since it was
loaded into memory. W = 1 is affirmative. The W bit is automatically cleared when the PAR or PDR
of that page is written into. It can only be set by the control logic (print K1-7). In disk-swapping and
memory overlay applications, the W bit can be used to determine which pages in memory have been
modified by a user. Those pages that have been written into must be saved in their current form; those
that have not been written into (W = 1) need not be saved, and can be overlaid with new pages, if
necessary.

Page Length Field

The 7-bit page length field (PLF) located in PDR bits 14:08 specifies the authorized length of the page
in 32-word blocks. The PLF holds block numbers from 0 to 1775, thus allowing any page length from 1
block to 128 blocks. The PLF is enabled by K1-10 LOAD PDR HIGH L, and written into the PDR
under program control.

PLF for an Upward-Expandable Page

When the page expands upward (ED = 0), the PLF must be set to one less than the intended number of
blocks authorized for that page. Thus, if the number of blocks authorized is 523 or 42,0, the PLF is set
to 513 or 41,0, with block O being the page boundary and the first block of the page. A comparator
network (E60 and E61 on print K1-8) compares the virtual address block number (VBA 12:06) with
the PLF to determine whether the VBA is within the authorized page length. If the VBA block number
is less than (A < B) or equal to (A = B) the PLF, the VBA is within the authorized page length. If the
VBA block number is greater than (A > B) the PLF, a page length fault is detected by the hardware
and K1-8 KT FAULT L is issued to the DAT TRAN circuitry on print K2-1, where it generates K2-1
ENAB ABORT H, causing a trap. When the expansion direction is upward, the page length is
increased by adding blocks with higher relative addresses. Upward expansion is usually specified for
program or data pages to add more program or table space (Figure 4-35).

PLF for a Downward-Expandable Page

The capability of providing downward expansion for a page is intended specifically for those pages
that are to be used as stacks. In the PDP-11/34, a stack starts at the highest location reserved for it,
and expands downward toward the lowest address as items are added to the stack. If the page is to be
downward-expandable, the PLF must be set to authorize a page length (in blocks) that starts at the
highest address of the page, which is always block 177;. The rationale for complementing the number
of blocks required to obtain the PLF is as follows:
Maximum Block No. Minus PLF

Required Length Equals
1773
12710

4210 = 8510

Figure 4-36 contains an example of a downward-expandable page. A page length of 42 blocks is
arbitrarily chosen to match the upward-expandable example shown in Figure 4-35.
NOTE
The same PAF is used in both examples. This is done
to emphasize that the PAF, as the base address,
always determines the lowest address of the page,
whether it is upward- or downward-expandable.

4-68

4.12.5

Virtual and Physical Addresses

The memory management Unibus addressing circuitry is shown on print K1-6. When memory management is enabled (K1-8 RELOCATE H asserted), the processor ceases to load Unibus addresses
directly from the scratchpad via the Bus Address register multiplexer latches (E43, E54, and E64).
Instead, addresses are relocated by various constants obtained from the memory management circuitry. (Selected PAR contents are added to the VBA using adders E44, E55, and E635.)

4.12.5.1 Construction of a Physical Address - The basic information needed for the construction of a
physical address (PA) comes from the virtual address (VBA), which is illustrated in Figure 4-37, and
the appropriate PAR set.

APF

ACTIVE PAGE FIELD

DISPLACEMENT

FIELD
11-3908

Interpretation of a Virtual Address

Figure 4-37

The virtual address (VBA) consists of:

The Active Page Field (APF). This 3-bit field determines which of eight Active Page registers
(APRO-APRY7) will be used to form the physical address (BA). The PAR/PDR ADRS
MUX (E89 on print K1-7) actually selects the specific PAR.

The Displacement Field (DF). This 13-bit field contains an address relative to the beginning
of a page. This permits page lengths up to 4K words (2!3 = 8K bytes). The DF is further
subdivided into two fields as shown in Figure 4-38.

BN
i

DIB
1

BLOCK NUMBER

DISPLACEMENT IN BLOCKS
11-3909

Figure 4-38

Displacement Field of Virtual Address

The displacement field (DF) consists of:

The Block Number (BN). This 7-bit field is interpreted as the block number within the
current page.

The Displacement in Block (DIB). This 6-bit field contains the displacement within the
block referred to by the block number.

4-69

The remainder of the information needed to construct the physical address comes from the 12-bit page
address field (PAF) (part of the Active Page register) and specifies the starting address of the memory
which that APR describes. The PAF is actually a block number in the physical memory, e.g., PAF = 3
indicates a starting address of 96 (3 X 32 = 96) words in physical memory.
The formation of the physical address is illustrated in Figure 4-39.

IAPF

BLoc»f

///%////é

’

NO.

VIRTUAL

DIB

ADDRESS

PAGE ADDFESS FIELD

’;@;4
6

PHYSICAL BLOCK
|

NO.

]"“

DIB
1

ADDRESS

PHYSICAL

(DISPLACEMENT IN BLOCKS)
11-3907

Figure 4-39

Construction of a Physical Address

The logical sequence involved in constructing a physical address is as follows:
1.

Select a set of Active Page registers depending on current mode.

The active page field of the virtual address is used to select an Active Page register (APROAPRY).

The page address field of the selected Active Page register contains the starting address of

the currently active page as a block number in physical memory.

The block number from the virtual address is added to the block number from the page
address field to yield the number of the block in physical memory which will contain the
physical address being constructed.

The displacement in block from the displacement field of the virtual address is joined to the
physical block number to yield a true 18-bit physical address.

4.12.5.2 Determining the Program Physical Address — A 16-bit virtual address can specify up to 32K
words, in the range from 0 to 177776 (work boundaries are even octal numbers). The three most
significant virtual address bits designate the PAR /PDR set to be referenced during page address relocation. Table 4-14 lists the virtual address ranges that specify each of the PAR/PDR sets.

4-70

Table 4-14

Relating Virtual Address to PAR/PDR Set

PAR/PDR Set
ONWDB W=
O

Virtual Address Range
000000-17776

020000-37776
040000-57776
060000-77776
100000-117776
120000-137776
140000-157776
160000-177776

NOTE
Any use of page lengths less than 4K words causes
holes to be left in the virtual address space.

4.12.6

Status Registers

Aborts generated by the protection hardware are vectored through Kernel virtual location 250. Status
registers SRO and SR2 are used to determine why the abort occurred. Note that an abort to a location
which is itself an invalid address will cause another abort. Thus the Kernel program must ensure that
Kernel virtual address 250 is mapped into a valid address; otherwise a loop will occur which will
require console intervention.

4.12.6.1 Status Register 0 (SR0) - SRO contains abort error flags, memory management enable, plus
other essential information required by an operating system to recover from an abort or service a
memory management trap. The SRO format is shown in Figure 4-40. Its address is 777572. Circuitry
used to implement the SRO register is shown on print K1-8.

ABORT-NON-RESIDENT —f

ABORT-PAGE LENGTH ERROR
ABORT-READ ONLY
ACCESS VIOLATION
MAINTENANCE MODE
MODE
PAGE NUMBER
ENABLE MANAGEMENT

[

—

-390

Figure 4-40

Format of Status Register 0 (SRO)

4-71

Bits 15-13 are the abort flags. They may be considered to be in a ““priority queue” in that flags to the
right are less significant and should be ignored. For example, a “‘non-resident” abort service routine

would ignore page length and access control flags. A “page length” abort service routine would ignore
an access control fault.

NOTE

Bit 15, 14, or 13, when set (abort conditions), causes
the logic (E121 generates K1-8 ERROR H) to freeze
the contents of SRO bits 1 to 6 and status register
SR2. This is done to facilitate recovery from the
abort.

Protection is enabled when an address is being relocated (K1-8 RELOCATE H is active). This implies
that either SRO, bit 0, is equal to 1 (memory management enabled) or that SRO, bit 8, is equal to 1 and
the memory reference is the final one of a destination calculation (maintenance/destination mode).
Note that SRO bits 0 and 8 can be set under program control to provide meaningful memory management control information. However, information written into all other bits is not meaningful. Only
that information which is automatically written into these remaining bits as a result of hardware
actions is useful as a monitor of the status of the memory management unit. Setting bits 15-13 under
program control will not cause traps to occur. These bits, however, must be reset to 0 after an abort or
trap has occurred in order to resume monitoring memory management.

Abort-Non-Resident

Bit 15 is the Abort-Non-Resident bit [K1-8 NR (1) H]. It is set by attempting to access a page with an
access control field (ACF) key equal to 0 or 4 or by enabling relocation with an illegal mode in the
PSW.

Abort-Page Length

Bit 14 is the Abort-Page Length bit [K1-8 PL (1) H]. It is set by attempting to access a location in a
page with a block number (virtual address bits 12-6) that is outside the area authorized by the page

length field (PFL) of the PDR for that page.
Abort-Read-Only

Bit 13 is the Abort-Read-Only bit [K1-8 RO (1) H]. It is set by attempting to write in a read-only page

having an access key of 2.

NOTE

There are no restrictions that any abort bits could
not be set simultaneously by the same access
attempt.

Maintenance/Destination Mode

Bit 8 specifies maintenance use of the memory management unit. It is used for diagnostic purposes.
For the instructions used in the initial diagnostic program, bit 8 is set so that only the final destination
reference is relocated. It is useful to prove the capability of relocating addresses, in destination mode
only.
Mode of Operation

Bits 5 and 6 indicate the CPU mode (User or Kernel) associated with the page causing the abort

(Kernel = 00, User = 11).

4-72

Page Number

Bits 3-1 contain the page number of reference. Pages, like blocks, are numbered from 0 upward. The
page number bit is used by the error recovery routine to identify the page being accessed if an abort
OcCcurs.

Enable Relocation and Protection

Bit 0 is the Enable bit. When it is set to 1, all addresses are relocated and protected by the memory
management unit. When bit 0 is set to 0, the memory management unit is disabled and addresses are

neither relocated nor protected.
4.12.6.2

Status Register 2 (SR2) - SR2 (shown on print K1-9) is loaded with the 16-bit virtual address

(VBA) at the beginning of each instruction fetch but is not updated if the instruction fetch fails. SR2 is

read-only; a write attempt will not modify its contents. SR2 is the virtual address program counter.

Upon an abort, the result of SRO bits 15, 14, or 13 being set will freeze SR2 until the SRO abort flags
are cleared. The address of SR2 is 777576 (Figure 4-41).

16-BIT VIRTUAL

ADDRESS

ADDRESS
777576
11-3910

Figure 4-41

4.12.7

Format of Status Regiser 2 (SR2)

Mode Description

In Kernel mode, the operating program has unrestricted use of the machine. The program can map
users’ programs anywhere in core and thus explicitly protect key areas (including the device registers

and the processor status word) from the user operating environment.
In User mode, a program is inhibited from executing a Halt instruction and the processor will trap
through location 10 if an attempt is made to execute this instruction. A Reset instruction results in
execution of a NOP (no-operation) instruction.

There are two stacks, called the Kernel stack and the User stack, used by the central processor when
operating in either the Kernel or User mode, respectively.
Stack limit violations are disabled in User mode. Stack protection is provided by memory protect
features.
4.12.8

Interrupt Conditions
The memory management unit relocates all addresses. Thus, when management is enabled, all trap,

abort, and interrupt vectors are considered to be in Kernel mode virtual address space. When a vectored transfer occurs, control is transferred according to a new program counter (PC) and processor
status word (PSW) contained in a 2-word vector relocated through the Kernel Active Page register set.

When a trap, abort, or interrupt occurs, the “push” of the old PC (old PSW) is to the User/Kernel R6
stack specified by CPU mode bits 15 (14) of the new PSW in the vector (00 = Kernel, 11 = User). The
CPU mode bits also determine the new APR set. In this manner it is possible for a Kernel mode
program to have complete control over service assignments for all interrupt conditions, since the
interrupt vector is located in Kernel space. The Kernel program may assign the service of some of these
conditions to a User mode program by simply setting the CPU mode bits of the new PSW in the vector
to return control to the appropriate mode.

4-73

User Processor Status (PS) operates as follows:
User Traps,

Explicit

PSW Bits

User RTI, RTT

Interrupts

PSW Access

Cond. Codes (3-0)

Loaded from stack

Loaded from vector

Trap (4)

Loaded from stack

Loaded from vector

Priority (7-5)

Cannot be changed

Loaded from vector

Previous (13-12)

Cannot be changed

Copied from PS (15, 14)

Current (15-14)

Cannot
be changed

Loaded from vector

Cannot be changed

*Explicit operations can be made if the processor status is mapped in user space.
4.13

CONTROL STORE

4.13.1

General Description

The Control Store circuit (prints K2-7 through K2-10) consists of twelve 512-word by 4-bit blpolar
ROMs, eight hex D-type flip-flops, and an assortment of multiplexers and gates. This logic operates in
a fashion similar to a microprocessor having 9 address lines and 48 data output lines with a fixed set of
ROM program routines.

Each Control Store ROM location can generate a specific set of outputs capable of configuring the
data path, determining the function performed by the arithmetic/logic unit (ALU), influencing the
DAT TRAN circuitry, or exercising general control over the total KD11-E operation. The contents of
each location are configured in such a way that sequences of locations can be combined into microroutines that perform the various PDP-11 instruction operations. Each ROM location is, therefore,
considered as a microinstruction or microstep.

4.13.2

Branching Within Microroutines

Each microinstruction in the Control Store specifies the location of the next microstep 1n a sequence.
After the execution of a microstep, the outputs of ROMs E107, E108, and E109 are latched into E89
and E91 (microprogram counter latch) to specify the location of the next microstep. Conditional
branching within a microroutine is accomplished by wire-ORing signals generated by external hardware onto the MPC lines when directed by some other Control Store output. Typical wire-ORed
signals include the following:

Instruction Decode

The microroutines contained in the Control Store are designed
to perform efficiently the operations specified by the various
PDP-11 instructions. Specific microroutines are implemented

for specific instructions. The main purpose of the IR Decode
circuitry is to translate the PDP-11 instruction in the IR to a set
of bits that can be wire-ORed onto the MPC lines upon request
(IR DECODE L), developing the next control word. A description of the specific addresses for each instruction is included in
Paragraph 4.5.3 of this manual.

4-74

A routine has also been included in the Micro Store to implement an error routine that pushes and pops the PC and PSW
onto or off the processor stack. Upon request of the Control
Store [K2-9 BUT SERVICE (1) H], the MPC 00 line can be
enabled by the Service ROM (ES50), causing a microbranch to

Trap Decode

this microroutine.

Upon performing a power restart, the MPC is cleared by an
Initialize signal (INIT). The power-up circuitry on print K2-3
then enables the MPC 00 line, forcing the Control Store to perform the power-up routine beginning at MPC address 001.

PWR Restart

In general, microsteps are not executed from numerically sequential locations in the Control Store;
therefore, care should be taken in following the flows described in Chapter 5 of this manual.

Figure 4-42 shows the format of all 512 words in the KD11-E Control Store. The fields, the possible
values they contain, and the significance of each value are described below.

O07

MPC

LOAD | LONG | AUX
BAR

|CYCLE|

CONT

—

BX | ovx | DBE

FORCE|

15
ENAB

BUS
CONTROL

MAINT

DATA
i

CONTROL

JAN

SSMUX
CONTROL

AMUX
CONTROL

PREV | BUT

RSVI | MODE | SERV

SEL | SEL

BUT

12
BUF

MISC
CONTROL

sPA | SRC

ALU

—/\

SPA DEST
SEL

FORCE

ROM

KERNEL

SPA

11-4252

Figure 4-42

Control Store Fields

4-75

4.13.3

Control Store Fields

Use the KD11-E flow diagrams as reference for actual control field bit patterns.
Field

Field Length

Description

MPC

Nine-bit micro-PC address, which specifies the ROM location of the next microstep to be performed.

Miscellaneous

Control

Three multiplexed control lines that generate the following
enable signals:

LOAD IR L - Allows loading of the Instruction register
(print K2-5).

LOAD PSW L - Allows the PSW register to be loaded upon
completion of this microstep (prints K1-1 through K1-4).

LOAD CC L - Allows the condition codes N, Z, V, and C to
be loaded upon completion of this microstep (print K1-1).
BUT DEST L - Enables microbranch to destination operand
microcode sequence (print K2-6).

ENAB STOV L - Enables the stack overflow detection circuit (print K2-3).

LOAD COUNT L - Allows the counter circuit (print K2-10)
to be loaded upon completion of this microstep.

CLK COUNT L - Enables the counter clock circuit (print
K2-10).
BUF DATTRAN

Enables the data transfer circuitry (print K2-1). Indicates that
the processor is performing a Unibus transfer during this
microstep.

Bus Control

Enables the Unibus control lines BUS CO L and BUS C1 L,
as follows:

ENAB MAINT

Ci(l)H

CO(1H)H

Transfer

0
0
1
1

0
1
0
1

DATI
DATIP
DATO
DATOB

Enables the memory management maintenance relocation
feature.

LOAD BAR

Allows the Physical Bus Address register (BA on print K1-6)
to be loaded during this microstep.

- 4-76

Field

Field Length

LONG CYCLE

Description

Forces the processor to perform a longer (240 ns) machine
cycle during this microstep. Typically this is done during bus
DATO:s.

AUX CONTROL

Enables the Auxiliary Control ROMs during operate instruction microsteps.

ALU S3-ALU SO

Determine the operation performed by the 16-bit ALU
according to Table 4-2. These lines are also wire-ORed,
allowing the Auxiliary Control circuitry to determine the
ALU operations according to Table 4-2.

ALU MODE,
ALU CIN
BLEG 01:00

Thesé multiplexed outputs control the operation of the B reg-

B, BX, OVX,

~ister and BX register during each microstep and detect over-

DBE, CONTROL

flow or double bus errors.

Controls the select lines of the SSMUX according to the

SSMUX
CONTROL

following:

Select
Straight
Sign Extend
Swap Bytes
External Data

SS 00 H

0
0
]
1

0
1
0
1

Controls the select lines of the AMUX according to the

AMUX

following:

CONTROL

Data

AMUX S1

AMUX S0

PSW
ALU
Vector
Unibus

0
0
|
1

0
1
0
1

Encoded control lines that select the specific microbranch
condition that can occur during this microstep.

BUT BITS

SPA SRCSEL

SS01 H

Controls the select lines of the scratchpad address multiplexer
during the first half of this microstep.
Field Select

ROM
RS
RD
RBA

4-77

SEL 1

SEL O

0
0
1
1

0
1
0
1

Field

Field Length

Description

SPA DST SEL

Controls the select lines of the scratchpad address multiplexer
during the second half of this microstep.

Field Select

ROM
RS
RD
RBA

SEL 1

SEL O

0
0
1
1

0
|
0
|

FORCE RSVI

Controls which source register will be selected by the scratchpad address multiplexer. If RS = is an even-numbered register, then RSV1 = Register 1. If, however, RS = an oddnumbered register, then RSV1 = the same register.

Allows the processor to perform this microstep using the previous memory management mode [PSW (13:12)].

MODE
BUT SERVICE

Force Kernel

Indicates that the processor has entered the Service microstep. Enables the Service ROM (ES0), causing the processor
to recognize any pending errors or interrupts.

Forces the processor to perform this microstep in the memory management Kernel mode.

ROM SPA

Allows the microinstructions from the Control Store to determine which scratchpad register will be addressed during the
next microstep, unless otherwise specified by the scratchpad
address multiplexer control lines previously mentioned.

4-78

CHAPTER §
MICROCODE

5.1

MICROPROGRAM FLOWS

A complete set of microinstruction flows is shown in block diagram form in the KD11-E print set.
Figure 5-1 is a simplified version that provides an overview and aids in using the detailed flows. No
attempt will be made in this manual to trace each path of this microcode, but the following examples
should provide an adequate background for the reader.
5.2

FLOW NOTATION GLOSSARY

The block flows should be self-explanatory. To aid in understanding them, the following glossary of
flow notation should be reviewed.
Designation

Definition

BA
;
DATI
+
PC
B
IR
BX

Unibus Bus Address lines
Minus the operator

Initiate DATI operation on Unibus
Plus the arithmetic operator
.
Program Counter = scratchpad register 7 (R7)

Scratchpad register specified by the source portion of the current instruction

Scratchpad register specified by the destination portion of the current

ENAB STOV
ENAB DBE
DATO
DATIP

Rn OP B
BUT

LOAD CC
UDATA
RSV1

Separator

B register
Instruction register
BX register
[IR (08:06)]

instuction [IR (02:00)]

Scratchpad register n specified by the Control Store ROM SPA lines

Enable the stack overflow detection logic
Enable the double bus error detection logic.
Initiate DATO operation on Unibus.
Initiate DATIP operation on Unibus.

ALU function determined by the auxiliary ALU control logic as a function
of the instruction currently in the Instruction register.
Branch on microtest.

Set condition codes (N, Z, V and C) according to the result of operation
being performed by the ALU.

Data being received from the Unibus data lines BUS D00 L through BUS
D15 L.

Source register specified by source portion of current instuction [IR (08:06)]
ORed with a logical 1. Example: If RS is even, RSV1 would be the next
highest register (RS = 4, RSV1 = 5); if, however, RS is odd, RSV1 would be
the same register (RS = 5, RSVI = 5).

—

MAINT

Assignment operator.

Indicates that the memory management Maintenance feature is enabled.

Indicates that this microstep is using the previous memory management
mode.
5-1

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KD11-E CENTRAL PROCESSOR
MAINTENANCE MANUAL

EK-KD11E-TM-001

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