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EK-KD11D-TM-PRE

May 1975

132 pages

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Document:	KD11-D Processor Manual (PDP-11/04)
Order Number:	EK-KD11D-TM
Revision:	PRE
Pages:	132
Original Filename:

OCR Text

EK-KD11D-TM=PKE

PRELIMINARY

KD1l-D Processor Manual (PDP-11/0L)

The information in this document is subject to

change without notice and should not be construed
as a commitment by Digltal Equipment Corporation.
Digital Equipment Corporation assumes no

responsibility for any errors that may appear in
this

manual.

Printed

in U_,S.A,

1975 by Digital Equipment Corporation

by PDP=11 Englineering

Page

DD
Q

Pregramming Differenceg Between PDPiils
Bug Latenecy Times

DETAILED HARDWARE DESCRIPTION

Ingroduction
Data Path Circuitry
General Desceription

) R

ALU
o
©

b
R =2

W
U

D) ==

D
D

rRegister

B LEG
AMyX

Circuitry

Multiplexer

Procegsor Status Word
Condition Coedes
General Deseription

O
®
®

Scratch Pad Address Mujitiplexer
Seratch Pad Register
Register

o)
R o=

O
®
o

Memory

Serateh Pad Cireuitry

(P8W)

Capry and Overflow Decode
Byte Multiplexing
UNTIBUS Address and

Data

Interfaces

UNIBUS Drivers and Receivers

> @) BRI &=

®@

Pad

Serateh

Bug

Address

Internal
Bus

Generation

Address

Data Line

Decoder

Interface

Ingtruetion Decodino

D
D9

d R

s RY ==

General

Deseription

Ingtruction Register
Ingtruetion Decoder
Double Operand Instructions
Singdle Operand Instruetions
Braneh Instruetions
Operate Instructions

General
Control

Centrol

t=m

®
®

ALU

Description
Cireultry

Double

Operand

Instruetions

Auxiliary

W WwWwWNONDDNNNOONOODNRIN
-

[

CPyU OPERATING SPECIFICATIONS

®»

)=
<A D

Ingtruction Descriptions
Differences Between KDiiD and KDIIB

OO UARARINUNRAGD D

SET

Adgressing Modes
Ingtruection Timing

©®
@
®
®

D
D
D
8
©
VD
O
@
O
O
©
©
VYV
O
©
@
Y
®
®
©
®
©
®
®
®
©®

ARAEARARARAAAARANTRNUARAARAORAARARBAAUVTIAA

®»

Ineroduction

) dad

©®

INGTRUCTION

OVERALL DESCRIPTION

ot bad bed bad (o

PREFACE

®»

CONTENTS

Sirgle

Operand

Instructioens

Data Transfer Control
Gemeéral Description

Contrel Cirecuitey
Proeessor Cloek Inhibit
UNTIBUS Synchronization
Bug Centrol
MSYN/SSYN Timeout
Errors

Address

Odd

End

Bus

Parpity

| .

]

w B

2 =B

2 =k A0 G0 0D A0 00 ~d <3 ~d ~d ~d ~d b~ ~3 ~f
= <J

Page

tad
B
=2

Powere=Up

Power=Fail
Process Clock
tad
R =2

b e

]

Fail/Auto Restart
General Description

L4 D

Detection

Power

ad
B &=

b b B
=t

® L]

Errors

Transfers
DATA=IN=PAUSE Transfers

Circuitry

Priority Arbitration
Bus Requests
Non

Hailt

Procegsor

Grant

Requests

Serviece
General

Deseription

Circulitry

Cipcuit

Operation

Control
General

Description

SsStore

Branching

Control

wWithin

Store

Fields

MICROCODE

Mieroprogram

Flew

Flows

Notation

Mieroporogram

Microroutines

Examples

Page

This manual
deseribes
the
KDii{D
Central
Proecessor
Unit
(M7263),
Complete
understanding
of its contents requires that the user have a
general knowledge of digital eireuitry and a
basie
understanding
of
PDpel{
computers,
The following related documents may be valuable as
references,

PDpil
PDpli

Peripherals Handbook
precessor Handbooeks

PDpl1/04

2,0

OVERALL

The

KD{1D

oneeboard

computer

subsystem

and

the

UNIBUS

and

instruction

between

for

I/0

addressing

The
the

handles

1s program

serial

options

will
now
PDP=11

the

3,6

INSTRUCTION

3,1

Introduection
is

perform

KDIiiB

both

werd

and

with

are

line,

be
provided
sense,

not

and

defined

3,2

Addressing Modes

1its

are

Data

stored

memory

handling
§s
specified
usually lndleates:

The

time

and

data

byte

the

UNIBUS

allocation

operations

transfers

8=bit

for

the

logie

single=and

directly

double=operand

data,

presently being used in
processing
capability

higher

speed,

provided
cloek

separate

{nstruction

selected

decoding,
The
following
describes
instruetion
set
addressing
modes
differen
fromces
those of the previous

1ine

desianed

Features

the

KD1{D

cireuitry,

UNIBUS

options
|

are

These

the

geguences

SET

operations

1in

the

the KD11B
all
the

significantly

which

(CPU)

directly

arithmetic

does

provides

communication

traditional

processor

ecan

16ebit

also

available

conscle,

KDi11D

beth

unit

conneets

controlling

memorys

compatible

opn

unit

performing

and

processor

The

capable

decoding,

available

The

devices

PDP=11/@5,

previously

central

¢geries,

peripherals,

and

KDi{1D

Manual

DESCRIPTION

PDP=11/04

Users

function

must

a&a

(operation

the

instruction

PpPDP=1{
instructions
along
with
instruction
KD11B’

and

instruetion

code),

The
to

the

accessed,

PDP=11

set,

according

manipulated,

(MOV,

ADD

ete,)

and

set

Data

which

Page

A general purpose reglster
te
be
used
vwhen
Jlocating
gource operand and/or locating the destination operand,

3.,

An addressing mode (to speeify how the
{s/are

selected

the

used),

Sinee a large portion of the data handled by
a
computer
1s
wusually
structured ({in character strings, Iin arrays, in lists etc,) the PDP=11
has been desjigned to handle structured data efficlently and
flexibly,
The
general
reglisters
may be used with an instruction in any of the
following

ways?g

As accumulators,

As pointers.,

the

3.,

The contents of

operand,

pointers

rather

autematically
addressing,

proeceéssing

than

the

operand

stepping
Known

stepping

Thege

tabular

resides

within

the address

1tself,

which automatically steps

Autematically
loecations
is

The data to be manipulated

reaister,

through

core

locations,

forward
through
consecutive
core
as
auteincrement
addressing

backwards

modes

data,

are

18 known as autodecrement

particularly

useful

for

As jndex registers,
In this instance
the contents
of
the
the word following the i{ngstructieon are summed
and
register,
easy
allowg
This
operand,
the
to produce the address of
access

variaeable

entries

in a

list,

PDP-11s also have
Iinstruction
addressing
mode
combinations
which
faci{litate
temporary
data storage structures for convenient handling
of

data whicp must

freguently

accessed,

Thig

Kknown

the

"gstack",

the PDP=11

proeqgram

subroutine

however,

used

certajn

"stack

{nstructions

pointer"

associated

under

with

linkage and interrupt service automatically use Reglster

"hardware

reterred

any reglister can be

control,

the

gstack

pointer",

For

this

reason R6

frequently

"SP",

is used by the processor as

its program counter

(PC),

Twe types
of¢
instructions
utilize
the
addressing
modes:
single
operand
and
double operand,
Figure | shows the formats of these two
tvpes of instructioms,
The addressing modes are listed in Table 1,

Page

Figqure

3,2,1

Instruction

{

Addresgsing

Mode

Instruetion

Formats

Timing

The PDPeii1 Is anm asynchronous
processor
{nmn
whieh,
{in
many
cases,
memery
and
procegssor
operations are overlapped,
The execution time
for an instryction is the sum of a basie instruction time and the time
to
determine and fetch the source and/or degtination oprerands,
Table
2 shows
the
addressing
times
required
for the
various
mode
of
addressing

source

and

destination

operands,

All

PDPeii1/¢4

times

stated are subject to +10% variation and are based on a
¢vyplical
core
memory
access time of 375 ns, a tvoical MOS memory access time of 5¢¢
nNg ahNd a proeceéssor clock cycle time of 260 ng,
PDP=11/05
times
are
based on a 319 ns processor clock cycle time and a MM{iL memory,

3,3
The

PDPe=11/094
PDP=11

Instructions

instructions

can

divided

i1,

Single=0Operand
Instructions
instructiens, rotates)

Douple-Operand

into

five

(shifts,

Instruetions

groupings?

multiple

(arithmetic

precision

and

loagical

ins¢gructions)

Program

Control

Operate

Group

Condition

Instruections

Instructions

(Codes

Operaters

(branches,

(processer

subroutimes,

Ccontrol

(processor

traps)

operations)

status

WOrd

bit

instructions)

Tables 3
for
¢the

threugh 7 1ist eaeh instruetion, ineluding
regbective
Iinstruction
groups,
Figure

different
individual

1ipstruetion
ipstructions

formats
in each

of
the
format,

byte
Iinstructions
2
shows
the six

instruction

set,

&nd

the

Page
S

MODE
1

[

]

, 5

{

OP CODE

DESTINATION ADDRESS FIELD

% =SPECIFIES DIRECT OR INDIRECT ADDRESS
x##=SPECIFIES HOW REGISTER WILL BE USE
waxn = SPECIFIES ONE OF 8 GENERAL PURPOSE REGISTERS

(a)
R

[

OP CODE
)

MODE

]

Ria-3 4

L1 2

}

MODE

{

SOURCE ADDRESS FIELD

2
v

DESTINATION ADDRESS FIELD

# = DIRECT/DEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS

#%= SPECIFIES HOW SELECTEQ REGISTERS ARE TO BE USED
#nw = SPECIFIES A GENERAL REGISTER

(b)
1n-1227

Figure

1 Addressing Mode Instruction Formats

Page

3,4

Instructlon Set

Differences

Table 8 lists the differences
ingstruction

séets,

between

the

PDP=11/05

and

PDP=11/04¢

Tahle

Binary
Code

Name

Registe r
Autelnerement

Auvtedeerement

e(Rn)

IndeX

LC(Rp)

Deferred

Auteinerement

ter
ster

deere
e¢ontentsg
centains ad

BRRA
e? (Rn)

@(Rn)+

Deferred

Auteodecrement

iens)
byte instruct
werd containing

IndeX Deferred

@X(RnN)

@10

Inmediate

Opera

Absolute

@&A

Abgojute

fia

Relative

Addressg
the

Deferred

instruetion,
¢0llows

imstruetion,

the

instruetion,

ing

containing

instruetion,

Page

instruetion,

" Rn = Register

Xen,A s next program counter

(PC) word

(constant)

Page

Table 2
Basiec Times

Deuble

Operand

Instruction
ADD,

SUB,

BIC,

BIS

Memory
Machine

11764

Option

CORE

CORE PARITY
MOS
MOS

CMP,

BIT

11704

PARITY

CORE
CORE PARITY
MOS
MOS

MOV

11/¢4

Single

PARITY

CORE

3,97
3,17

3,17
3,33

2,81
2,91

2+91
3,07

2.81

CORE PARITY
S
MO

2,91

MOS

3,7

PARITY

Memory

NEG,

(usec)

2,91

QOperand

Instruction

CLR,

Rasic
Time

COM,
ADC,

INC,

Machine

Option

Rasjic
Time (usec)

DEC,

SBr

11/04

CORE

PARITY

MOS
MOS

ROR,

ROL,

ASRy

ASL

11724

PARITY

CORE

PARITY

MOS§
MOS

11724

PARITY

CORE

CORE PARITY
&
MO
MOS

SWAB

11/04

PARITY

20335

CORE
CORE PARITY

MOS
MOS

PARITY

3.27

Page

Single

Operand

(cont?®d)

Memory

Maehine

Ingtruetion

All

Braneheg

(branch

true)

Option

14/04

CORE

CORE PARITY
MOS

All

Branches

(branch

false)

11/04

2,65
2,81

CORE

177

MOS

PARITY

1,87
1,87

2003

Instruetions

Memory

Instryction
JMP

Machine

Option

Basice
Time (usec)

11/04

CORE
CORE PARITY

Pef1

MOS

11/04

JSR

s
Mo
PARITY

CORE
CORE PARJITY
MOS8
MOS

Centrol,

Trap,

and

Miscellaneoug

PARITY

Machine

Option

11/04

RTS

CORE

PARITY

MO
S

MOS

RTT

@84
Pe91

?.88

3027
3,27
3627
3e27

Instruectionsg

Memory

Instruction

RTI,

2655
2,65

MOS
PARITY

CORE PARITY

Jump

Bagic
Time (usecg)

PARITY

CORE

11/04

CORE

PARITY

MOS
MOS
11/04

PARITY

CORE
CORE

PARITY

MOS

Rasic
Time (usec)
3,91
4,11
4,11

4043

501
5031
5,31
5¢79

20,29

2039
2539

Page {2

Clear

11/04

Ny,Z,V,C

MOS PARITY

2,55

CORE
CORE PARITY
MOS

2029
2,39

MOS

11/04

HALT

CORE
CORE PARITY
MOS8
MOS

11/24

WAILT

11/04

PARITY

CORE
CORE PARITY
MOS
MOS

RESET

PARITY

PARTTY

CORE
CORE PARITY
MOS

MOS

I0T,

EMT,

TRAP,

BPT

PARITY

CORE

11/04

2,39
2055
1,36

1,46
1,46
1,62

2,03
213
2013
2,29
120

100

190

9,79

Bo16

CORE PARITY
MOS

795

MOS

Re49

PARITY

Page

Table 2a&,
Addressing Times

ADDRESSING

Mode

FORMAT

TIME
Memory

Deseription

symbolic

Maehine

Option

CORE

11/04

CORE

DEFERRED

11/04

PARITY

CORE
CORE PARITY

MOS

(R)
MOS

AUTOINCREMENT

(R)+

11/704

PARITY

Q(R)+

PARITY

11/04
CORE
CORE PARITY
PRRITY

MQS

11/04

PARITY

CORE
CORE

+X(F)

11704

PARITY

M08
PARITY

CORE
CORE PAPITY
MO S
MOS

INDEXED

Re X(R)
Nk

11/04

2,66

2.98
110

MOS

INDEXED

2,46
2,66

1,20

Re (R)

1,20
{36

CORE

MOS
RUTODECREMENT

1.10

CORE PARITY

11/24

DEFERRED

Be94

1,10

MOS

«(R)

@86
@,94

1,20

MOS
AUTODECREMENT

CORE
MOS

AUTOINCREMENT
PEFERRED

0
*

CORE PARITY

MOS

PARITY

CORE
COFF PARITY
MO S

(R)

MOS

PARITY

Destinations##

PARITY

MOS

:
Source#

(us)

1629
136

246
2,66
2.66
2,98

272
2,92
2.92
3,24

4,78
4,38
4,38

4,86

1,95

Page

Memory

Machine

#For Source time, add
odd byte addressing
e4For

the

Destination time,

for

folowing

ii/04

modify as

Add for odd byte addressing with
modifying instruction MODES {=7

€,

for all none=modifying
Subtract
except

MODE @

11704

11/04
11/04

1,04

CORE
CORE PARITY
MOS

Add for MOVE instructions

MODES

Subtract for JUMP and JSR instructions

MODES

11/04

HAdd for all ROTATE even byte
|
imstructions

11/85
11h08%

Add for all ROTATE odd byte

i11/@5%
11AGAS

Add for all ROTATE odd byte

11705
11A0S

= Modes

1,2,4

instructions except Modes @,1,2,4

N/A

11/04

£,

instructions

(us)

0,52

N/A

MOS

Time

follows:

a,
Add for odd byte addressing with a
nonemodifying instruction

instructions

Option

N/A

PARITY

0,61
6,64

0,54
0,57

?,26

1D198

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Table 7
Condition Code Operaters

Mnemonic/

Instruetion

Time

CLC
CLZ

CLN

CLV

Set all CCs
Clear all CCs
Clear V and €
No obperation
No operation

op Code
dP0241
gR0242
gen244
2AR250
@RR277
@2028"

“

Deseription

Set and clear condition code bits,
Selectable combination of these bits
may be cleared or set together,
Condition code bits corresponding to
bits in the condition code obperator
(bit P=3) are modified according
to the sense of bit 4, the set/clear
bit of the operator;
1i{,e,, set
the bit spreecified by bit
¥,
1,
2,

bits

bit 4 as a

bit

4=¢0,

000240
PeR260

Figure 2

Clear corresponding

PDP=11 Instruction Formats

Pacjg 254
1. Single Operond Group (CLR ,CLRB,COM,COMB,INC,INCB, DEC,DECB,NEG,NEGB, ADC,ADCB, SBC,SBCB,TST,TSTB,ROR,RORB, ROL
,ROLB,ASR,ASRB,

ASL,ASLB, JMP, SWAB)

]

[

]

OP Code

]

|
6

Dst

)

(o]

2.Double Operand Group(BIT,BITB,BIC,BICB,BIS,BISB,ADD,SUB)

OP Code

]
12

. Sre

]

|
)

dst

3.Program Control Group

a.Branch (all branch instructions)

OP Code
|
:

offset
i

(¢}

b.Jump To Subroutine (JSR)

]

)

reg

Src/dst

¢.Subrontine Return (RTS)
0

]

reg

]

)

]

)

d.Traps (break point, IOT,EMT,TRAP)

OP CODE

4.0perate Groupe (HALT,WAIT,RTI,RESET)

OP CODE

]

1-1226

Figure

2 PDP-11 Instruction Formats

Page

TABLE R8
DIFFERENCES:

I1# a RUS ERROR occurs due to a transfer
to nonexi{stent memorv during an auteine
erement transfer (Mode 2), am instruction
feteh, or stack pop, the associated
regicster

PDP=11/04 (KD11iD)

(KDiiRB)

pDp=11/2%

{nerement transfer (Mode 2), &an instruce
t{en fetch, or stack pop, the assoclated
reqglister will not be incremented,

incremented,

will be

Examples:

Examples?

FETCH

FETCH ROUTINE

ROUTINE

" BA €=== PC, DATI
BsIR <=== UNIBUS DATA

BA ¢==«= PC, DATI
PC ¢=== PC PlusS 2

BRANCH

BA ¢=== R
B
R

BRANCH TO SERVICE

SERVICE

AUTOINCREMENT ROUTINE
[S]

===« R [S)
[8)] <e==s B

(SOURCE)

DATI,

Plus

ALBYT

RYTE BAR Plus

€oe

¢===
(===
[0)]

K
R

€==

([D]
([D)

DATIF,

Plus

ALBYT

Pilug

BYTE BAR

(RUs ERROR detected and recognized)

STACK

B
R

<e== UNIBUS DATA

[S)

DATI, ALBYT

AUTOINCREMENT ROUTINE (DESTINATION)
RA ¢=se= R

<¢eo=

[D]

DATIP,

ALBYT

DATA

UNIRUS

(BUS ERROR detected and recognized)

STACK POPS

POPS

RA ¢=e«

¢=e»

BRANCH TO SERVICE

BRANCH TO SERVICE
do

BRANCH TO SERVICE

SERVICE

AUTOINCREMENT ROUTINE (DESTINATION)
BA
B

AUTOINCREMENT ROUTINE (SOURCE)
(BUS ERROR detected and recognized)

(BUs ERROR detected and recognized)

RRANCH TO

(BUS ERROR detected and recognized)

(BlUsS ERROR detected and recognized)

If a BUS ERROR occurs due to a transfer
to nonexistent memory during an autos

(6]

«e== P (6]
[6] (=== B

RA <e=== R

DATI

Plus

[6]

g==e [UNTIBIIS

DATI

DATA

(R1J§ ERROR detected and recognized)

(BUg ERROR detected and recognized)

BRANCH TO SERVICE

BRANCH TO

SERVICE

Page

IT,

For

JUMP

autoincrement

yged
as the mpew
compatible with
IT1,

The

prOcesSor

using

Exampies:

CLR
MOV

Note?

PC address, This
the PDP=11/20,

can

registers

11,

ingtrucs

access

thelir

{its

feature

general

117,

UNIBUS addresses,

accegses

and

are

KDI1iB

time=put

provides

when

contentsg

‘PC.

fearure

Thig

are

used

compatible

the

with

The processor

cannot access its general
using their UNIBUS addresses,

nut operafte
supported,

IV,

recognizinag

ugec

BUS

SACK

interrupts,

The KDiiD CPU
elock, 8erial

does not contain a line
communicatiomn line, or

console circuitrv, These features will
be provided as UNIBUS optionsg in the
traditional PDP=11 sense, In systemsg that
do not contain these options, attempts to

address

them

memory

trap,

will

result

noneexistent

The KD1iD has mo provisions for SACK
timeeouyt on the basic CPU module, A SACK
return eircuit is provided on the M9302
Terminator module which must be used with
the KD11D at the end of the UNIBUS, This
device

autematically

peripheral

accepts

returns

GRANT

SACK

{if

1ssued

the

CPU,
Vi,

The

console

priority
the

ugser

thArough

The
apnd

HALT

level,
to
an

switech

This

has

feature

the

lowest

allows

single-instruction=step

The

console HALT switch has a higher
level than interrupts and

priority

therefore,

trabs

The
and

HALT

TRAp

TRAP

TRALP

RIJS

INSTRUCTION
ERRORS

TRACE

INSTRUCTIGNS
TRAPR

STACK

QVERFLOW

STACK

OQVERFLOW

POYWER

FATL

POQWER

FAIL

INTEFRUPTS

HALT

SWITCH

HALT

INTERRUPTS

CONSOLE

not

allow

the

user

fthrough

PDP=11/44 priority order for
interrupts is as follow#s:

RUS ERROPRS
HALT INSTRUCTION
IMNSTRUCTIOQONS

does

single=instruction=step
interrupt,

imterrunmt,

PnPe11/2% priority order for
{interruots 1s as follows:?

TRACE

new

the

not

for

autolncrement (Mode 2) {nstructjons,
or JSR rveg,
(R)+ the initial

In the 11/24, these accesses to the general
reglisters will return SSYN and not time out,
Reads will return zZere and writes will not
cause any change in the register contents,

The KpiiB CPU contains &8 line clock,
gserial eemmynicatien line, and

The

JUMP
(R)¢+

registers

programrmers console ¢circuitry, These
devices answer to the UNJBUS addresses
172540, 17756¢, and 177574 respectively,

For
JMP

PDP=11/40,

@# 177700
RY, @8 177700

These

correctly
v,

(Mode

tions, JMP (R)+ or JSR reg, (pl+, the
contents of R are incremented by 2, then

traps

Page

VIT,

The KpiiR

hags

capabjilities
gupport
VIII,

and

narity

PBRITY ERROR detection
theretore

does

VII,

not

is quaranse

VIIl,

executed,

RTT imstructions are not implemented,

The KD{iDP CPU contains

detection eireuitry,

parity memory

memory,

First instruction after RTI
teed

PARITY ERROR

&and will support

options,

AThe RTI sets the T bit, the T bit trap
acknowledged immediately after the RTI

instruetions,

IX,

First
to

instruection after

executed,

RTT {8 quaranteed

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Page

3,5

Bus

Latency

Timas

The tvopieal pUs latency timeg f£or bus requests (BR4 through
BR7)
Non=Processor requegts (NPR) are as followg,
Note that there are

gaps

these
of

eirevuitry,
BUS

REQUESTS

timing

the

sequences

UNIBUS

and

the

that are a
speed

» maximum

time

instruction

BG to SACK
to

BG OFF

OFF

toe

FIRST

the

userg

300

INTR

ROUTINE

NON=PROCESSOR

REQUESTS

NPR to

NPG =

NPR

BUS

340

FETCH

and

peripheral

lenath

and

6,36

MOS

’

6,43

MOS

Parity

6,81

nSs

CONTROL

Cores

MOS

CPU OPERATING

longest

KD11D,

6,63

3.52
Parity

3,66

MDS

3,56
Parity

3.75

SPECIFICATIONS

Temperatures

TBD

Relative Humiditv:

20% to 95%

Input

+S5VDC

Power:?

Interface

length

peripheral,

Parity

Core

Physical

eycle

Cores

Core

4,2

users

funétion of peripheral,

Memory

the

= function ef UNIBUS length and

BG OFF to SACK OFF
SACK

BR te BQC

SACK

rfunction of

realized

and
many

Sizes
Reguirementss

Single
All

+5%

Hex
1/0

connectors
compatible
Table 9,

(with condensation)
at

amperes,

module

signals

1/2
are

inches)

avallable

A and B,
These signals are
with UNIBUS pinout as shown

oin
1Iin

Power and
Pineutsgs

Number

Cireuitss

Greund

Pins

Integrated

AAZ,

BA2,

EA2,

FA2,

AB2,
AR1,
BB2,

"AS1y

AC2,

BT1,
DC2,

BC2,
BVZ,
DTi,

FC2,

FT1,

CA2,

DA2,

AN,

AP1,

ATL,
BD1,

AV2,

BEi,

€CC2;
EC2¢

CTi,
ET1,

Page

POWER

DO6
DOS

AH?Z
AJ1
AJ2

D10
DO9

AK1
AK2

AL1

D12
Di1
D14

AL2

D13

AM1

a ff «

DC4
DO3

DO8
DO7

BD2
BEZ2

BF1

BE1

BF2
BH1
BH2

BJ1
BJ2
BK1
BK2

BL1

AM2

D15

AN1

AN2
AP1

RP2
AR1

BBSY

AR2

SACK

AS1

BAT
NPR

AS?2

BC{
BC2
BD{

L
GROUND
D02

AF1
2
AF
AH1

BB2

DOO

il ol all o F 2l 2l o F ol o

AE?2

~ TEST POINT

DO{

~ BAf

BA2

AC1H
AC2
AD{
AD2
AE1

INTR

(+5V)

L(3)
L

BRAT

+185YV

BACKUP
L

=15V

AB2
ADS
A04
AGT

BN2

Ai@
Al3
A2
ALS
Ald

BR{
BR2

TEST POINT
BR 5[
GROUND
BAT=-BACKUP
BRe4l[,
INT, SSYN,
PAR: DET,
ACLO L
DCLO L
AGYL
pADO
AB3

APE
ARGY
AGSB

BP2

RACKUP

8PARE

BL2
BM{
BM2
BN{
BP1

SPARE
"POWER (+5V)

RS{

BS2

ol ap Y wn o Y wn i} cp il e

INIT L

AA2
AB1

SIGNAL

AA1Y

AB2

SIGNAL

el vl el el ol e i el

ASSIGNMENTS

A1l

il sl

9
TABLE

MODIFIED UNIBUS PIN

A17
Ai6

GROUND
ci L
SSYN L

AT{

GROUND

BT1

AT2
AU1

RR .7L

BT2
BU1

AUZ

BU2

AV1

+20V

MEYN

AV2

¢+20V

BV2

o8V

$20V

+5V

Page

5S¢0

DETAILED

5S¢l

Intreduetion

The

following

Processor
segments

allowing

Unit
of

the

DESCRIPTION

detalled

(CPU)
CPU,

the

Clarification.
the

HARDWARE

circuit

being

wused

shown

extensive

KD11D

deseription
in

Figure

use

circuit

the
4,

will

block

schematiecs

$.2.1

Data

PDP11/04

will

deseriptions,

5.2

the

KDIID

Central

computer,

Various

analized

dlagrams

for

referenced

separately

{improved

throughout

Path

General

Description

The sSimplified KD11D
gshowh {n Figuyre 3,

data

path

Figure

congists

PATH

DATA

five

functional

vunits

asg

fage 394

DATA

1afut

UNLBUS

—>=

FAD

{L‘

AL\ Fi—
—

N
X

WGl tfl‘

“

8\‘ =t

DATA

CONSTANTS

T
Powd

;

'\B

PATA

{ATH

AauRE

AMUX

OuTfuT

VL ANSTRUCTICN
Vo

ALU

The

heart

arithmetie

performing

(Boolean)
avallable
AMUYX

the

logle

data

Page

capable

path

unit

arithmetic or
16
logical
operations
on
the
two
{6«bjit input words,

four=to=one multiplexer which controls
the
1ntroduetion of
new
data and the
circulation of avajlable data around the
data

BeRegister

path,

This

(BREG)

16=bit

ghift

complementary

logle

the operands

operations,

ROTATE

well

and

generating
of

the

Eight

PSW

and
the

for

SHIFT

the

priority,

eondition

degcribing

the

ingtruetion,
to

the

one

most

ALU

needed

constant

eXxtended

1low

containing

current
eodes

the

its

store

econtentsg,

regults

and

{nstructions,

deteeting

8ign

bit

information

also

introducing

instruection

used

required

implement

byte

processor

(N,Z,V and
C)
of
the
last

indicator

exeecution

trapped

for

during

program

random

access

debugging,

Seratenh

Pad

Memory

(SPM)

This

memory

word
(RAM)

dedicated
purpogse
eight

ugsed

another

16ebit

containg

regligterg

elght

processor

and

ejight
aqeneral
registers,
Of
general purpose registers, one
as
a
stack
pointer (SP) and

(user

the

avajlaeble)

program

ecounter

(PC),

AR TeS ASOTIPm. NUI

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N.DN2dW n:w
EN

I40.S

FROM AUX

CONTROL

AUX,

> PAD

L
|
NTRO

SCRATCH

BUFFER

+1
r

AUXILIARY

DECODE

CONTROL

“

m 12:8

BA 3:0

I |

Efi 2:0

ROM SPA 3:0

T Ao e
T
ifigmcn
3:0 e
AT

g
gfi?,—g”

PSW
BALEY

“B'REG

_CONTROL
MICRO

BUT

BRANCH
CONTROL

DECODER

Al
L 4

U |

L ALU,CC, and

ENAB +1

LOAD CC’s

N, 15

Nl
ALUS 3:0 oo

ALy

AL@MODE%‘“‘"‘”I
ALUCIN

CONTROL

—

| ;

INTERNAL

W
CONTROL

STORE

d
:

e+ e v
PO ‘;:-.....__.,1 s

R6 STACK POINTER

R7 PROGRAM COUNTER

R10 SOURCE ADDRESS

CONTROL

R11 SOURCE OPERAND
R12 DESTINATION ADDRESS

STORE

LATCH

R13,14 TEMPORARY
R15,16 UNUSED

MPC 7:0

1:0

MUX
N

> 16

;

BUS

5. CONTROL.
DATA TRAM
C 1.0
|

—»J RESTART,
AND .

DATAPATHCONTROL
v

CLOCK

PROCCLK

—==

REGCLK

Ftfib\\x[f ///f

POWER FAIL/ 5

" ALLOW BYTE__s| PARITY

PSW 7:5

R17 SWAB

BUT 2:0

SPM REG ASSIGNMENT
R0O-R5 GENERAL PURPOSE

! -

}

CONTROL

)
j il

—
ie—

[T~ BUSACLO

e— BUSDCLO
+=— BS PAGPE

DATA 16:00

—
—]
——

Page

and Data Flow

ContrTol
Data

flow

indireetly

through

the

Data

elements

and

these
ROM
perform the

controliled

elther

directly

Rom location (microinstruction)
generates
a
capable
of
contrelling the above data path
the ALU
function
performed,
Sequences
of

determining

microinstructions
are
combined Into
various PDP11 instruction operations,

further

5.2,2

Path

by the CONTROL STORE ecireuitry (Figure 4} on prints K9 and

K18,
Eaeh CONTROL STORE
unigue
sget
©f
outputs

for

microroutines which
(See
section
5,11

detalls),

Arithmetic Legic Unit (Prints Ki,K2,K3,K4)

ORGANIZATION

The Arithmetic Logie Unit

(ALU)

is divided

into

(K1,K2,K3
apd
K&
each contain a sliee) eaeh
ALU chip (74181) and
part
of
a
Look
Ahead
(74182),
See
Appendix
for
specificationg
integrated

INPUTS

The

4ebit

slices,

4ebit
chip
74182

cireulits,

ALU

A<input

(SPM)

four

consisting of one
Carry
Generator
for the 74181 and

each

registers

ALU

¢hip

comes

specified

from

the

one

the

CONTROL

Scratch

STORE

Pad

Memory

microinstruction

being performed (see section 5,2,3 for detalls),
B=inputs to each ALl
are specified by the BeLeg Multiplexer logie and ecan take the forms of
either the fuyll 16 bit B Register contents,
the
lower
byte
of
the
BReRegister
eontents
sign
extended,
the
constant
one
(+1) or the

congtant

ALU

zere

(V)

(see

section

%5,2,4

for

further

description),

FUNCTIONS

The funetion performed by the
bits
(83,S2,51,89), the Mode
foliowing taple lists the ALU
corresponding
bit
patterns
funeti{ons

are

shown

in Table

ALU {s controlled by the four
selection
bit (M) eand the Carry Iim bit (CIN),
The
functiong used
Iin
the
KD1iD
and
the
for the six control signals,
Additional
12,

.oYi

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5way

moY A0o4 m..: |

~ ~

V6QTYNfifi= LAYsgyeviDgendgardionGSTyURIUMARm
==

O:d

:_um m

Page

ALY FUNCTION

ALU CONTROL
8
82
81

SIGNALS
89
CIN

)

A Plus

A
A

Plus
Plus

@
@

@
i

7
%)

@
@

@
i

@
{

B
A
A

Plus
Minug
¢ B

|
B
B

@
@
@

|
B
%)

7/
@
i

@
{
%
i

|
@
1

%
7]
@

@
|
@
i

|
@

i
i

i
)
|

@
{
i
@

Plus 1
Minus

A (=B)
A Minug B
A.B Mipus

1§

@
|
|

Table {0
ALU FUNCTIONS

52,3

Scrateh

5.2,3,1

pPad

Scrateh

Memory

Pad

Circultry

ORGANIZATION
The

Scrateh

(Figure 6)

Scratch
are

Pad

pad

functioen

comprised

The

Scratch

Pad

Iinmnto

£€our

4=-pit

gslices

K4,

Scratch

¢three

functional

units

Seratch Pad Address Multiplexer and

Memory,

divided

prints Ki, K2, K3, or
is shown on primt K8,

DATA

= Scratech Pad Register,

Pad

one

Addregs

and

8cratch

which

Pad

shown

Multiplexer

Memory

either
clircuitry

INPUT

Data to be wplitten into the Seratch Pad is channeled from
clocked
i{nteo
the
Serateh Pad Register Iin either normal
high
and
lo¥W
bytes
reversed
(for
implementation
of

instruetion),

ADDRESSING

THE

SCRATCH

PAD

the AMUX and
form-.or with
the
SWAB

Page

The

Scratch pad Memory

(SPM)

the

state

lines

the

Source

reglister

address

accessed

the

following

generated by the Secratch Pad Address Multiplexer (SPAM),
of the
of

select

the

8PAM,

any of

Source

Fileld

IR{1«IRAO

Depending on
can be

addresst

Bus

Instruction Register

Instruction Reglster Destination Fleld

the

CONTROL

THE

SCRATCH PAD

CLOCKING

Address

STORE

ROM

1IR@5=IRZ3

(ROMSPAD3I=ROMSPAMQ),

Cloeking data from the AMUX lines into the

Reglster and

writlng

that
data
i{nto the SPM, are both accomplished by the REG CLK H clock
signal,
Data is latched into the SP Reglister on the
rising
edge
of
REG
CLK
H
and
i{s
immediately written into the 8SPM until REG CLK H
returns low (leogie °92°),
LATCH DATA

(A SP REG.

REG CLKH

“—_fi\__,w,_~./

WRITE DATA
INTO

SCRATCH

PAD

CLOCK

The K9 SPW HIGH
CONTROL
STORE

S P,

ENABLES

H and K9 8SPW LOW H
determine
whether

during a particular REG CLK cycle,
byteg (either high or low or both)

enabling signals generated
by
the
a write operation will be performed

These
1lines
also
djictate
will be written inte the SPM,

which

fagel%é*
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ouTRIT

IMYERTTM

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ADRS (k)

5——*
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ADE.S, S

( \}*

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] -

(e2)

ADRS

1
-

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(k2 |

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i

(k)

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B

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APATLE

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sPA MUK

Page

'5,2,3,2

Scratch Pad Register

(SP REG)

Figure 7

OVERVIEW

SCRATCH

PAD

SCRATCH PAD REGISTER

The SP REG consists of four Multiplexer Latch (74298)

allow
high

data ¢trom the

and

LATCHING

low

bytes

HIGH

AMUX lines

reversed

AND

LOW

(AMUXP5=AMUX(O)

normal

to be

<circuits

which

latched with the

fashion,

BYTES

I1f K1 SWAR L {s unasserted (meanming that
PEGISTER
17
1is
not
©being
accessed Iin
the SPM), the 74298 B inputs are enabled and data stored
in the output of the AMUX,
1If, however, Ki SWAB L
is
asserted,
the

74298
and

A={nputs

low bvtes

{imgtruetion

are enabled and the data {8 stored with the AMUX high

swapped,

and

This

operating

feature

byte

used when

performing

SWAB

instructions,

determine
H
LOW
©SPW
The CONTROL STORE outputs K9 SPW HIGH H and K9
whether
the low, high or total AMUX lines will pe latched Into the SP
REG at the time K5 REG CLK H occurs, With K9 SPWw HIGH H enabled,
the

high byte of

the AMUX will

latched and correspondingly the

low byte

Fage 47H

(prts K k2,K3,k4)

SCRP\TC_H PAD ?E GISTER
A MNUIX

ovt PUT

R2
A2

‘>

SPM

AR
OvuTePuUT

BYTES

D
REVERSE
L
! SWABR

L
SPW Low

(k2 SPW N\GR L)

f?3b6Y€1u7

'fibviifCIl ffikl rfig956]QZV'

Page

will

entered

5,.2,3,2

SPAM
The

when

Scrateh

Pad

SPW

LOW

Rddress

true,

Multiplexer

(SPAM)

ORGANIZATION
SPAM

generates

SPM

word,

Data

Multiplexers,

The

the

SPAM

four

address

consists
The

SPARM

of
is

signals

two

Tvype

shown

4elineeto-i=line
multiplexers
(two
strobe input signal (GND) and common
2@

are

connected

and

denerates
Table
of

the

SPA

MuX

that

one
1ists

state

4=bit
the
the

H),

when

Four

the

sources

data

input

selected
the

select
Dual

K8,

the

desgsired

4=Lineeto=]1

Each

the

Line
¢four

per 745153 package) has a common
address input g8iagnals (K& SPA MUX

8SPAM

output,

that

745153

SPAM

sources

are

addressed

from

{nput

one

data

used

and

the

that

and

they

strobed,

four

are

sources,
function

processor,

Table

SPAM

Input

Fupnction

SPAM
Input

source Operand Register

Destinatien

Selection

seleetion
Puyrpose

SPAM

selection

Instruction RegQister |

"K11

Bits

06=78

Ingstruetion

Bits

0002

Bug

Address

Bits

0F<03

Reglister

Kii

Control

Store

ROM

Kid¢

Si1 (sigmal
Ki®
SPA
They are generated by

MUX
the

CONTROL

and

5S¢

STORE

Kio,

data

shown

Source
Print

1INPUTS

The SPAM address inputs are
(signal Ki@ sPA MUX 2@ H),

The

Mieroprogram

SELECT

Ssource

Consele

Operand

11
Data Sources

input

below,

gselected

funection

the

states

S1I

and

Page

Address

5.,2,3,3

Seratch Pad

SPM

ORGANIZATION

The

Seratch

read/write

3101A)
The

pad

l16eword

registers

Qutput

L
L

L
H

that

(8PM)

Figure

found

16=bit

are

Memory

Memorv (SPM)
composed

memory units

Inputs

memory

Seratch

is a
of

on KD11D

organization

utilized

pad

memory

16-word
by
16=werd

logic

Ki=K4,

four

shown

prints

this

below,

16<bit
random
access
4=bit bipolar (Type

memory

provides

storage

Page ¥9+#

Cersree Tap Memory

(;.(q SPw Hi6H H}

(prints K1,k2,k3,KA)

(SPV\! HIGH LB

(K9G 5PW Low )
7Yool

O‘

ks REG6CLK H

[
S P

Ko shaz

K & SPA g2 H

RENV @

1)
]

UERO C

{

F RaM

N, 7486

IO S

ez TOH

K2 SPA @I H
KS SPA

dd H

figaY@ B)

5(\"&11'("//1 Fad /7(«,1/‘70Yj

Urozos,
oG

Page

|
Regigter

FIGURE 9
Utilization

SPM

Description

RO
Ri
R2

Genera)l Purpose
Regjsters

R3
R4

RS
.uwan‘.uwvu-nwa-wm--u--'.-----n----a-bp.v-nn.--wn

Ré

Processgor

Program

R1Q
R

Source
L

X2 XN R

R11
R

-R-R-f

-3

R12

Pointery

CouUnter

Addregs

Storage

LY NXRYEESRENYEYYXE]LYRESR
XXX R

Source
LA

Stack

Data
NN B

8torage

Destination

Addregs

K-N-XJ

Storage

--OQQ-.-QG!D'Q..-Bfl'm..OQ.UQG.HQD.-U--.--.Q.-..’-

R13

Temporary Sterage

..UQ'..’..".-'.--O..’-Q.-flflfiflfi---‘.fl........-O..

Ri4
Ri15S

Unused

R16
2P

PRI

R17

SPM

DATA

EPREPITOESRPRP

PRl

Temporary

Sterage

f£or

SWAR

QUTPUTS

Data

inputs

REG,

The

exclusive

the

SPM

output

(74686)

are

obtained

frem

the

scratch

pads

(3121A)

the
gates

which

always

When

the

INVERT

4input,

(1)

ENAB

AUXILIARY

ALy

CONTROL

all

(¢)

the

ALEG

the

signal

REG

(1)

c¢ircuitry,

complement

ALU,

previously

recomplement

(Data read from the 3101A is
inte it) on read operations,

enable

the

used

L,
on
the

the

conjunction

exclusive
Kii

data

to
or

described

fed

into

memory

complement

print
SPM

are

force
(d)

output

what

was

set

data

written

with

the

SPM

gates

allow

the

(a)

true

all

SPM

i{°s

data

(b)
onto

Page

INVERT

(1)

ENAB

REG

(1)

ALU
All

ALEG DATA

1°s8

Complement

SPM

data

i
i

@
1

Flgure
12

Apother SPM genable imput,
STORE or INTERNAL ADDRESS
on

the

signal

SpM,

{is

write

enabled

WRITE
DECODE

into

and

the

ALU

ALEG

data

DATA

ENABLE,
allows
either the
CONTROL
cirecuitry te perform write operations

low

the

All Q°s
True SPM

byte

REGC

the

CLK

memory,

the

lowetoehigh

SPW

LOW

transition,

the bvte
{8 written,
Writing into the hich
byte
accomplished
{n a gimilar manner except that the

of
the
memory
18
K9 SPW HIGH H signal

ig enabled,
Full word
SPW HIGH H are enabled

5,2.4
The B
Beleg

operations oceur
simultaneously,

when

both

SPW

LOW

and

B Register
Register
of
thne

registers
required
register

(74194),

used

purpose gtorage
register
on
the
¢four
4ebit
bldirectional
shift

store

one of

the

two

operands

for
most
ALU
operations
and
as & shifteleft/shifteright
during rotate, shift and byte instructions,
Between the BREG

and

the

following

(B REG) is a general
ALU
econsisting
of

ALU

18 a

block

multieplexer

logle

(Figure

{1)

whieh

performsg

functions,

Permits
to be

the sign
extended

of the operand in the lower byte of the BREG
through the upper byte before {t enters the

ALU

Can

force

operations
or

the

constant

where

decremented

into

scratch

the

pad

ALU

Beleg

where

decremented
by

during

two,

Can force the constant 2 inte the
operations

inputs

being incremented

scratch

one,

by the K5 BREG CLK L signal,

(ALU

pad

CIN

ALU

Beleg

provides

inputs during

being

for

the

incremented
one)

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63 S
PBREGISTER
FGuRrE

Page

The type of eperation performed by
the
states of mode control inputs 1| and @2 as

BMode Control
29
@1

the

Operatien

BREG
{s
determined
shown below,

Parallel Load

Shift

Right

Shift

Left

Hold

(eleek

(towardg

(towards

LSB)

MSB)

1nnibited)

SOURCE OF BMODE CONTROL
The primary source for the BMODE contrel signals is the CONTROL
STORE
(print
K9),
A
wired=0OR connection allowsg these control signals to
alse be generated by the ROTATE and SHIFT ROM (EB87) in the AUX CONTROL
logic

Kii,

BREG SHIFT CAPABILITIES
A key to the

discussion

the

BREG

shifting

operations

the

of the BREG bit structure ag shown In Figure
representation
symbolie
Shift Registers which make up the BREG has
74194
FEaeh of the four
{3,
(SR) serial input
1input and a shi¢éteright
serial
(SL)
shifteleft
a
whieh are
shift

When

interconneected in such a way as

SL or

enabled,

the

other {mput

create

disabled,

full

16=blt

therefore,

being performed only one serial input
instruction
the
opn
depending
will acecept the Ki1 SERIAL SHIFT H signal generated
by
the
ROT/SHFT
specific SERIAL SHIFT signals are shown in Figure 12,
ROM (E87),

Instruction

Value of Kif
SERIAL

SHFT H

Remarks

@ to BREG bit @ via SL input

ASL

GND L

ASR

BREC 15 (1) H

ROL

COUT (1) H

ROR

COUT (1) H

Bit 15 of BREG output to bit 15 of

BREG

~
-~

via

input

C bit BREG bit @ via SL {input
C bit to BREG bit 15 via SR input

Figure 12 B REGISTER SHIFT SIGNAL INPUTS

Page

Figure

BIT

BYTE

SHIFTS

This

also

handles

byte

shifting

ASLB,

ASRB,

ROLB,

and

RORB,

Signal

Ki{

serial

right

ASRB
RORB

(SR)

input

instructicen
¢fopr

to
This

between
Iy @7 H

output

SPECIFIC

SHIFT

(K3

BREG

AND

ROTATE

The

shifting requirements
degcribed

briefly

Arithmetic Snhift Left
@,

loaded with

The

shifted

handle

ASR

and

ROR

bits 08 and 27 for a
i{s generated
by BYTE

are

BREG

SHIFT

replication

during

because

shift=right
MUX E66 and

word

instruetions
H

used

bit

for

the C=bit for
perform the word

there

direct

overation,
Signal
it represents BREG

instructiens

ASR and

ROR,

OPERATIONS

for

the ASL,

ASR,

below,

(ASL)

left

required

load the previous contents
signal is also required to

{instructions

connection
Kii
SHIFT
bit

bit

and

instruetion,

shifting

STRUCTURE

one

ROL,

and ROR

instructions

- Shifts all bits left one place,
place,

The

ROT/SHFT

ROM

(E87)

Bit

selects

—

S—

S
m———

pesm—

|
oTeTo]]

J el

[— & SERIAL SHFT H
{

Shifr

SHET M) &7 W

shift ond rotate word
instruction )

teft serial input

Shift right serial input

(From bit 08 oultput of
BREG vio BYTE MUX for

Figuve |3
B Register Bit Structure

Page

ASL

inmput

BREG

bit

Arithmetic
15

whieh is ground,

via

the

Shift

leoaded

Right

with

Kii1

input,

(ASR)

BREG

SERIAL SHFT H = @ and is

Shifts

output bit

all bits

right

one

loaded into
place,

Bit

158,

The BREG is shifted right one place,
The ROT/SHFT ROM
(EB7)
selects
ASR
{nput [K11 CCNH], whieh is output bit 15 of the BREG,
Kil SERIAL
SHFT H equals the bit 15 output of the BREG and {s loaded
into
BPFEG

bit 15 via the SR
7 H frem ROT MUX

leaded
from

bit

Rotate

into
@8

Left

{nput,
This
(E66) equals

BREG

bit

(ROL)

bit 15,
of the

K11 SHIFT
BREG
and

IN
1Is

@7 via the SR {nput to provide the connection

@7,

is replication of
the bit P8 output

Rotates

all

bits

left

one

place,

Rit

loaded

The BREG is shifted left one place,
The ROT/SHFT
ROM
(EB87)
selects
ROL
{mput
(K1
CBIT (1) H], whieh i3 the value of the Ce=bit prior to
execution of the instruction,
Kii SERIAL SHFT H equals thls value
of
the Cebit and is loaded inmto BREG bit 066 via the SL input,
|
Rotate
with

Right

(ROR)

Rotates

all

bits

right

one

place,

Bit

1loaded

Ce=bit,

The BREG 1s

shifted right

one place,

The ROT/SHFT ROM

(EB7)

selects

ROR
i{nput
[K1
eXeeUtion 0f the
the Cehit and is
H equals the bit
via the SR ipnPut

CBIT (1) H), which is the value of the Cebit prior
instruction,
Kil SERIJAL SHFT H equals this value
loaded into bit 15 via the SR input,
Ki1i SHIFT IN
28 output of the BREG and is loaded into BREG bit
to provide the connection from bit 28 to bit @7,

In each of

Instructions,

from

the

PSW

logle,

BMUX

The

these

BREG,

This

furnction

the Cebit is
is

discugsed

loaded with
in

the

gset

new

description

to
of
©7
@7

value

the

OPERATION

16<bit

(Type

output

74157),

the

BREG

and AND gates

fed

into

(Tvpe 749¥8)

showpn

2=te=]1

multiplexers

in Figure

11,

These

circuits allow the CONTROL STORE output signals K9 ENAB +1 L
and
Ki@
ENAR SEX L te control whether the BREG unmodified, BREG sign eXxtended,
constant 2, or econstant +1 will be passed on to the ALU Beword inputs,
The
followipa
¢truth table shows the various states of these control
signals,

ENAB

K1@ ENAB

SEX

ALU

BLEG

DATA

H
H

H
L

BREG
BREG

Constant
K8

contents
contents
H

+1
+1

unmodified
sign extended

er
@
L

depending

signal,

state

Page

SIGN

EXTENSION

When

the

extension

the

BLEGOO®

ENAB

BREG

DATA

and

data,

Ki®

the

ALUajong
with its
thru

BLEGIS

956

the

ENAB

highest

same

SEX

unmodified
as

bit

signals

low

byte

(BREGA7)

BLEGAT)

through

regquegt

the

BREG

extended
the

s8ign

passed

(makes

high

bvte,

the

BLEG

ALU

CONSTANTS +1 AND 0
The purpose

the
ALU. is
autodecrement

generating
the constants
to
aid
the
operations,

and

inputs

processor
in performing autoincrement and
DPuring
either
operation,
¢
a
word

imstruetion
1is being performed, the speciflied reagister is incremented
or decremented by two,
I£
however,
a
bvte
instruction
1is
beling
performed, the register is incremented (decremented) only by one,
The
actual

ALU

operation

RESULT
The

ALEG DATA

ALU always
uses

the

follows,

BLEG

Ki@

DATA

ALU

¢+

CIN

ALU

CIN

signal

{ncrement

decrement
the ALEG input by ones
which meang that the BLEG inbut must
provide the eonstant +1 or @ to obtain the
correct
autoincrement
or
altodeerement

result

for

both

byte

and

word

instructioens,

A BLEG eonstant +1 {s generated by enabling the least significant BLEG
bit (BLEG
¢9) and forcing all ether bits (RLEGA1=-BLEG1S) to ¢,
1If a
constant ? ig desired, even the least
significant
bit
(BLEGAY)
s
cleared, The actua)l constant geperated is defined by the state of the
K8 INH +1 L gignal
as shown inm Figure 11,
The state of
output
Ki®

Multiplexer

the K8
ALLOW

(SPAM)

alse

preventsg

5,2,5

AMUX

the

INH 41 L signal
RBYTE
H and the

shown

ALU

from

the

ever

The AMUX eirecultry on prints
Multiplexers
(Tvype
74153)

is determined by the CONTROL STORE
outputs of the Scratch Pad Address

elreuitry

incrementing

Ki thru
and two

the

K@,

This

by one,

1loegle

K4
eonsists
of
four
4
to
|
to | Multiplexers (Type 74157),
These eirecuits
can channel either the ALU output data,
data
received
from
the
UNIBUS, the BUT SERVICE constants (K8 C2 H, K8 C3 H, and K8
C4 H), or the contents of the PSW Register onto the
AMUX
0@
H
thru
AMUX 15
H 1lines
which
feed
the Scratch pPad Register, Instruction
2

STORE

The
specific
lines Ki? AMUX

L,
primary source of these econtrol
silagnals
(print Kip), A wire=OR connection capability

1s
also

data
to
S@ L and

be
Ki2

the
CONTROL
allows these

signals to be generated by the BUT SERVICE ROM (E71{ print K8), and the
INTERNAL,
ADDRESS
DECODER
ROM
(E48
print K8),
The following truth
table shows the relationship between ¢hanneled
data
and
the
select
lines,

Page

DATA

SELECTED

AMUX

UNIBUS DATA

ALU

DATA

PSW DATA

BUT SERVICE CONSTANTS

5,2,6

Procegsor Status Word

The processor status word register (PSW) contains information
current
priority
of
the
processor,
the
result
of
¢the

on
the
previous

operation, and {ndieates a processor
bit assignments and use are shown in

The
“

Processor

Bit

Name

07«05

priority

Trace

‘

When

8set,

when

the

set

whem

the

manipulation

set

when

Set

when

sianificant

trap,

as a
and

The

PSW

condition

8=bit

bits

debuqging,

result

of the

result

of
of

the

trace

| last

data

the

last

data

the

last

data

zereo,

the

result

produces
an

the

result

overflow,

preduces

the
carry

last
from

data

the

most

bit,

result of instruction execution, proaram trars,
returns
¢to
maine=line
code,
In the case
of a

interrupt,

code

traps

program

negative,

manipulatien

processor

for

Set

manipulation

word
of
the
vector
Otherwise, the PSW is
combinational
1logic
being exeeuted,

PsW
|

Asgignments

the

Used

manipulation

program

Use

vector,

The PSW is loaded
I1/0 interrupts,

debugging,

Set the processor priority.

Table 12
Status Word Bit

‘

trap during
Table 12,

return,

the

PSW

from
the
Unibus
data
loaded through a
network
that is controlled by the

flip=flop

(N,

and C)

are

loaded

with

the

second

1ines
via
the
AMUX,
of
multiplexers
and
particular instruction

(prints

stored

and

74175

flipeflop (print Ki),
The priority bits and Tebit
are
74175
quad D=type flip=flop called PSW 734 (Print K2),
the Tebit flip=flop 1s sent to another flip=flop (T DEL)

K2),

quad

The

Detype

stored
in
a
The output of
which is used

Page

the

The

trap

input

eondition

flag,

source

for

the

condition

code multiplexer

code

(CC MUX)?

bits

the

output

The CC MUX (print K1)

the

is a Type

74157 Quad 2-Line-toei-Line Multiplexer,
One of the two 4=bit
Iinputs
is selected by the state of the select (S) input, When S is high, the
Beinput is passed to the D=inputs of the condition code latches (NBIT,
ZBIT,
VBIT,
and CBIT),
The Be=input consists of AMUX outputs Ki{ AMUX
20

H-@3

consists

ROM

the

when

(print

signals

Ki1@),

condition

These

codes

deseribed

The

source for

input

outputs

the

74175,

the

source

detall

AMUX

low,

from

the

devices

Aeinput

BYTE

the

a functioen of

which

are

signal K2 AMUX @4 H is

the

sgelected,

Kig)

the

and

logle

The

the

used

Aeinput

and

BIT

setting

instruction execution and are

paragraphs,

priority bits
H

1is

(print

are part

subsequent

H=@7

MUX

(PSW

sent

@5=27)

consists

to D=inputs

D1,

sent to Deinput D@ of

D2,

of AMUX
and

the 74175

Tebit,

Each bit of the PSW Is ¢clocked by REG CLK H
when
the
CONTROL
STORE
(print
Ki19) output LOAD PSW L i{is enabled,
The condition code hits N,
Z, V) and C can be loaded separately by the same REG CILK
H
when
the
CONTROL STORE output LOAD CC L {s enabled,
The T=bit and PSwW<734> can
also be loaded separately by REG
CLK
H
when
¢the
INTERNAL
ADDRESS
DECODER ROM (E48 print K8) enables EXT LOAD pPSW I,

5.3

Conditien

The leoegie
print Ki1

Codes

neecessary for determining the condition codes
(s
and can be subdivided into three parts as follows,

shown

The condition codes are determined by the CC MUX (primt Ki) previously
discussed,
the
C and V BIT ROM (print Ki@), the RBRYTE MUX (print Ki2)

and the ROT/SHF ROM
code

bit

are

(print Ki2),

shown

in the

The constraints

instruction set

for

each

specifications

condition

section

3,0,

53,1

Instruction

Catagorizing

ROM

The CATEG ROM (F93) on print Ki{ decodes the instructions in
the
IR
reg{ster
and catagorizes them into eight groups based
on thelr effecs
on the carry and
overflow
condition
codes,
These groups
are
as
|
foliows?

Page

GROUP

INSTRUCTIONS

MOV,BIT,BIS,BIC,

INC, DEC
CLR,TST,SWAB
ADD, ADC
NEG,CMP,COM

2
3
4
S
6

8UB, SBC

ROTATES

UNUSED

Three of the four outputs
representation
of one of
V

BIT ROM (E99),
The
ingtruetion {n the IR

Figure

and

ndbn

of this ROM &are used
the above ingtruction

PDP11

to
provide
a
ecatagories for

fourth output (BYTEL) decodes
{8 a byte instruetion,

AND

CONDITION

INSTR,

CODE

the

ROMS

tact

binary
the C &

that

the

fl?’jg 39 /7

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K1

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H

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Cand V

CONDITION

FIGUR E

(oPE

ROMS'

Page

53,2

BIT

ROM

The C & V Bit ROM (E99) on print Ki{
determimes
carrey
and
overflow
condltion
code
bits
as
instruetion pbeing performed,
1Inputs te this ROM
ALEG

(K4

ALEG

and

ROT
CCN

CBIT (1) H), the
H) and the CATEG

fed

inte

5.,3,3

the

Byte

MUX

BLEG
(K1

ROM

(E93),

(E12)

signal

for

L)Y

wused

and

the

print
the N

the

when

Output

Kit CEN
H
instruction
being

AMUX

for

instructions

becaUse

high

when

the

and

BLEG

BIT

(1)

H),

Outputs

the

Kil1

ROT

SHFT

output

Ki,

the

and

of
of
the

ROM
the

Ki{

the
the
ALU

(Ef§7eKi1
ALU

(Ki1

are

BYTE

MULTIPLEXER

(print

the
not

K2),

Aeinputs
a

Quad
code

2 te
bits

single

1
1lime
and the

sgselect

whem
a byte

mnmultiplexer
Ki1 SHIFT IN

input

operation

(Ki{i

BYTE

performed

byte,

assumegs

the
level
of
K4
AMUX
15
H
when
the
performed
Iis a word operation and the level of K?

instruction

performing

operations

processor

1lew

Kil) 1s & 74157
and Z conditien

BREG

oppose

inputs

the
values
a
function
ecome
from

Multiplexer

The BYTE MUX (E66
whieh
determines
H

(K4

PSW

Figure

bvteg

microcode

the

byte,

(section

input

word

The

latter

onm

the

6,9)

hag

before

the

high

also

byte

already

posgsible

word

swapped

condition

the

codes

are

detected,

The
the

CC Z H output assumes the level of the K1} @«15
8 @ H
{input
instruction pbpeing cerformed is8 & word operation, and Kil Q7

when

the

instruction

are

connected to
H
{8
true
=185

For

shift

level
of
performed

determined

the
1f

true

right

the
{8 a

ALU
the

{if

byte operation,
by logiec on print

operations,

bit

the

result

Kii

SHIFT

when
@ H

PRath Kit @=15 = # H and K11
Kii and the Tvpe B8R15 gates

outputs on prints Ki, K2,
low byte of the processor
the

K3 and K4,
Kii 0=7
operatjion is zere,

= 0
Kii

zero,

K3 BREG @8 (1) H (print K3)
word operation and the level

output

{mput when
of the Kii1

assumes

the

the instruction
SERIAL SHIFT
H

/g)g,g cosT

BNTE

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Page

(erint

Ki1) output of the ROT/SHFT ROM (EB7)

for byte operations,

dlagrams
following
signals, the
<thesé
tor
understand the reasons
ird{cate the operations performed by the various ROTATE instructions,

Page

Word:.

J“’L:__,'“’

Byte:

Word:

LlJl.LtLlllkfil"o
0

Byte:

]

000 ADDRESS

llj}“’*“LTLx ( 1‘11 ]“‘°
EVEN ADDRESS

ds?
1]

Bytes:

Page

UNIBUS ADDRESS and DATA Interface

5,4

5,4,1

UNIBUs

Standard bug

Drivers

and

transeceiver

Recelvers

elircuits

Type

8641

gre

used

data path to the UNIBUS addrpess (BUS AGG=A15)
processor
Ki
These circuits are shown on prints
DP®=D15) 1ines,
logic

diagram

for

8641

Figure

5,4,2

UNIBUS

Address

Iinterface

the

and data (BUS
A
K4,
thru

shown below,

UNIBUS

Generation

TRANSCEIVER

Circuitry

A unique feature of
the
KDI{iD
1s
that
there
|
no
BUS
ADDRESS
REGISTER,
Durimng
UNIBUS
transfers,
bus
addresses
are
obtained
directly from the Seratch Pad Memory (SPM) previously discussed,
The
contents
of
the
selected
SPM
Jlocation
1s
complemented
by
tThe
Exelusive=Q0R gates at the outputs of the Secratch Pad and
driven
onto
the
UNIRBUS
by a set of Type 8641 Bus Transceivers (Prints Ki, K2, K3
and K4),
The driver outputs of these transcCelvers are enabled hy
the
signal K6 ASSERT ADDRESS [ whose source is the data transfer clrcultry
on

5.4,3

K6,

INTERNAL

ADDRESS

DFCODER

The receiver half of the above mentioned bus transeceivers
continually
monitors the 'NIBUs address linegs,
1If the processor is running, these
transceivers only allew the INTERNAI, ADDRESS
DECODER
cirecuit
(print
K&)
to
detect
transfers
te
or
from
the PSW regjster,
While the
procegsor 1s halted,
this
decoeder
c¢irciut
enables
data
transfers
between
CPU Registers and UNIBUS peripheral devices,
A 1ist of these
CpU reglsters and their UNIBUS addresses follows,
PSW

177776

R1p

777710

777700

R11

777711

7777081

R12

777712

777702

R13

777713

777703

R14

777714

64 e
fag

UNIBUS

TRANCEIVER

FIGVRE

Puge

777704

RS
R6

777705
777706
7777927

One

is
the

5,4,5

pnalted

UNIBUS

777717

UNIBUS

Cata

DATA

Path

all

CPU

circuitry

also

inputs

the

data

uponm

either

driver

5.5

sectlions

(print

Generagl

methods

control

require

these

Used

required

result

There

UNIRUS

the

Transceivers

AMUX

(Figure

transceivers

control

and

the

bpecause

are

the

(IR),

4)
B

two

Type

where

8G41

from the
circuits

may
or

be
PSw

the

general,

pits,
are

calculations
address

uses

Jarge

executes

from

the

AMUX

drivesg it onto the
by
the
DAT
TRAN

decoding,

auxiliary

number

One

uses

control,

Lual

{nstructions

that

ALU

Aux{liary

the

action

thorough

procedure,

ALU

X.RY

eontrol

One

understanding

(Section 5,11) and the
(Section 3,7),

knowledae

other

the

knowledge

format

concerning the

(instruction

<calculatiens,

prerequisiteg

microbranching process
the PDP=i11 instruction

There

data

instruction,

deecoding

facts

obtaing

K1 thru K4) and
s
generated

other

microcode

specifiec

instruetion

access¢d

Decoding

selecti{on

whenever

Description

evoked

Certain

(prinmts
DATA
L

source/destination
a8

can

K6),

are

microroutine

PSW

1Instruction

9,5,1

the

whieh send and receiver data
receiver
section
of
these

Instruction

1ines AMUXPP=-AMUX1S
when the signal ENAB

cireuitry

contains

K4)
The

D=inputs

the

redauest,

output
UNIBUS

and

Transgcelvers

K3 -and
D@@-D15,

chanbeled

Registers

addressing,

(Prints
K1,
K2,
UNIBRUS data 1ines

Two

R17

of clarification that should be noted, is that while the CPl
runnming,
only the PSW can be accegsed through its UNIBUS addresss
General Registers cannot be accessed {in this
manner,
Wwhile
the

througnh

The

7777158
777716

point

processor

The

R15
R16

the

PDP=11

PLPe-il

instruction

operation

ecode

numnber

instructions

and

Jlarger

calculation,

There

that

number
are

set

also

listed

varjable

require

¢that
a8

are

from

two

reguire

numher

helow,
4

address

only

one

instructions

that

vreguire

addresg

data,

caleulationg,

but

do not

Page

operate

3, All OP codes that are not implemented in the KDii=D processor
be trapped,

must

There are illegal combinations of

mode&

that

must

'There exists

{nstructions

trappeéed,

list

exceptions

iIin

the

and

execution

instruetlions having to do with both the treatment of
the setting of conditlen ecodeg in the program status

55,2

JInstruction

Each PDP=11

address

data and
word,

Reglister

instruction obtained from memory is

stored in

the

16=bit

INSTRUCTION
REGISTER (IR)
on
print Kii,
This register consists of
three 6-bit D=Type Registers (Type 74174)
and
one
D=Type
Flip=Flop
(Type
7474),
The
purpose of the IR {8 to store the instructien for
the complete instruction eycle
§o
the
IR DECODE
(primt
Ki2)
and
AUXILTARY
ALU
CONTROL
(print
KJiil)
<circuits
can decode the correct
control signals throughout the instruction cvecle,
<

The IR latches data from the AMUXQ@=AMUX1S (prints Ki thru

on
the

ejther
the
trallling edge of K&
trailing edge of K5 BREG CLK L,

When

PROC

clearedsy

INIT

K11

eeccurs,

all

{5(1)

the

set

SERV

bits

except

PROC

INIT

K12

Kd)

1L,OAD

Kii

This

1lines

15(1)

and

are

means

that

the IR DECODER
e¢ircuit
will
{nterpret
+his
new
IR
output
as
a
conditional
branch
while
K5
PROC
INIT
H
s true.
This prevents
processor from decoding a HLT instruction on any INITIALIZE condition,
If a trap Instruction
necessary to
clear

Joes

SERVICE

the next
routine

is
1loaded
{into
that instruction

SERVICE

loop

routine,

the

trap

the
frem

Failure

IR
the

and
decoded,
it
s
IR before the micro=pC

instruction,

this

The

will

BUT

cause

SERVICE

the

PROW

(E71 print Kg) asserts K8 INST TRAP SER L whieb in turn causes K5 SERV
IR
H,
On the trajiling edge of K5 SER IR H, Kii IR1% (1) H is set by
K8 INST TRAP SER L and all other bits of the
IR are loarded with
zeros

from

being

If a
DBE

the AMUX
loaded

lines,
into

BUS ERROR (BE) oecurs
L
1is
asserted,
the

causlng the

processor

without

ENAB

5,5,3

This

the

results

in a

conditional

branch

instruction

the IR,

DRE

1Instruction

to
L

while the
whole IR

automatically

signal

Deeoder

CONTROL STORE output signal
register 1s cleared (FPDP-11

have

halt,

effeet

Bugs
the

errors
IR,

ENAB
Halt)

occuring

Page

5:9,3.1

The

Ki@,

Instruetion

INSTRUCTION

DECODE

and

Cireulitry

CONTROL

STORE ROM cirecuitry

whieh interprets PDP=1l instructions
microinstructions
each
consisting
contreol

UNIBRUS
A

signals

control

block

in
K9

and

Eight

toe

4,2

Ki?)
of

the

then

are

these
and

determine

the

Note

latched

can

the

thus

will

Instruction

mode

all
in

and

translates them into a
38
control
signals,

operation

and

Hex
I’ Type

signals

(K9

the

called

the

INSTRUCTION

the

CONTROL

Registers

MpC

STORE

937

ROMS

L=K9

MpC

the

The

INSTRUCTION
S8Seven

the

(MODES

5¢95.,3.2

Double
the

the
is

DECODER

micro=PC,

the

@=7),

circuitry

256%X4

bpbit

ROMs

gates,

better

following

descriptions

Douple

operand

souree

this

(Print
If the

The

Operand

and

the

one

signal

reqguire

the

Other

being

place

with

set

the

K12
CODE @@

the

contents

‘It

consists

74vV2

and

the

operation

instruction

being

are

only

enabled

74HY!
the

decoded
when

this

Tvype

1loglc,

types,

calculatiens,

operand,

The

Rom

the TR
tvype,

MPC

K9
@8

the

outbuts

gates

the

source

mode

onr

MPC

the

one

for

micecroe=branch

souree
operand
IR DECODE (1) H,

DnP

DECODE

(EAR9)

(OP CODPE b{ts IR14=12),
the
ROM
ouytputs Aare

QUTPUTS

K12,

DOFCODER

microePC

Type

the

(source

Type

address

(EIS)

the

decoded,

ingstruction

two

ROM

Instruetions

Coupled

back

capabhility

required

Inst,

fed

74Hat,

follows:?

Operand

Reserved

are

Type

destination

enabled,

TYPE

Double

shown

(prints

Instructions

for

INSTRUCTION

i{s

ROMS

Wwire=OR

operand

shown

based

several

understand

are

instructions

and

&nd

force microbrancninag
actual
microbranch

{nstruction

and

Ki2)
checks the {nstruction in
{nstruction {s a double
operand

asserted

of
Trese

miereoeinstruction

sequence o0f mieroinstructions
which determine the
1Initiated
by
the CONTROL STORE output signal K9

When

set

74174),

loailc

Ka,

path

NECODFR

STORE

destination),

7424

data

(Type

the IR DECODER circultryv
to
enabling
conditions,
The

dependent
used

STORE

outputs

CONTROI,
be

of thegse 1ines allows
addresgsses on certain

address

the

CONTROL

that

latched

inputs

address

oporint

circuitry,

diagram

Figure

could be thought of ag an internal microprocessoar

K12

and

k11

Decoder

instruction

MPC "
3
L

DOP

LEC

K12,

fleld

V¢

MPC K9
P4

are

the

outputs

gates

»«hen

enabled

(IR11=«]IJR®9)

L=MPC

being

ROM

These

decoded

0of

lines,
1s

the

PDP1]

These

qgates

the

double

operand
type (K12 IR12=i{4m0
asserted and the instruction
ypasgserted),

true),
18
not

the K9 IR
reserved
,

DECODE
(K12

(1)
IR

Page

H signal
CODE
2@

is
L

A summary of the various source micro addresses is Shown below,
~

SOURCE

OCTAL

INSTRUCTION

MODE

MICRO BRANCH ADDRESS

DOP

2
3

62
63

RESERVED

67
aa

DOP

Note that a QroUnd on the MPC lines represents a logie

"g?

(negative

logie).,

address
for the various

The

DOP

DEC

above is8
CONTROL

When

input

the

ROM

cirecuitry,

deseribed

BUT

DEST

t¢the

DOP

modifying

address

205(8)

DEC

ROM

1is

decodes

nonemodify

946(8)

algso used to
decode
the
STORE destination operand
asserted

the

instruction
the

MPC

the

instruction,

and

@5+-K9

Control

Store

determines

asserts

MPC

mieroepPC
routines,

either

lines,

the
a

MOV

instruction i8
asserted,
the
25 linmes,

decoded and the Ki2 DM H (destination Mode @) input {s
miero address 0A1(8) is placed on the K9 MPC A3«K9 MPC
~
'
|

Similar

eircuitry

source

operand

also

used

the
to

described

routine,

decode

the

set

destination

above
Type

mode

¢for
74HO1

field

micro=addressing
gates

(K1{

onr

(1)

the

Ki2

are

K11

IR
@5
(1) H) of the instruction being decoded and place jts contents
on the K9 MPC 02 = K9 MPC 2 lines when enabled,
For
double
operand
instruetions,
enabling
occurs when the CONTROL STORE asserts Ki{2 RUT
DEST L,
symmary

the

various

destination

micro-addresses

DESTINATION
MODE

INSTRUCTION
MODIFY

follows,

OCTAL
MICRO=BRANCH
ADDRESS
40

MOV

Wiy —=

INSTRUCTIONS
(ADD,SUR,BIC,BIS, and
not DM@)

43
%4
45

MOV DESTINATION
INSTRUCTIONS

5,5,3.3

Unlike

8Single

MODE

~J Oh

INSTRUCTIONS

50
51
52
53

54
55
56
57

Operand Instructions

double orerand instructions,

single operand

require
one
address
calculation
taoa
obtain
Complete SOP instruction decoding is done with
SOP MICRO BRANCH (E81) and SOP DEC (E75), both

The

and

SNP MICRO

asserts

when the

signal

K12

activated

BRANCH

when

(EB81)

monitors

IR DECODE I,

12=-14=0

SOP

signal

instruction

true,
is

instructions

only

the necessary operand,
the two 256%4 Bit ROMs,
on print K12,

the necessary

the correct micro=pC address on lines

NON MODIFY
(CMP,BIT)

qam.bwmw‘s

Page

asserted

Input

lines

the

SOP

enable

K9 MPC @23

and

= K9 MPC

The Ki2 DEST L output is also

decoded,

This

Signal

enables

the

‘destination
mode monitoring cireultry deseribed
in the double operand
instruction decoding section. Microaddresses for SOp instructions are
shown below
|
|
|
|
'
The SOP MICRO BRANCH ROM {s also
used
to
decode
JSR
instructions,
This
decoding
1Is
performed
exactly
as described
above
for
SOP
instructions,
The Ki2 DM@ H {input to the ROM is used
to detect
the
fllegal
insgruction
JSR
destination
mode @,
When this occurs, no

miero=pc address

allowed
on the

INSTRUCTION

- S0P MODIFY INSTRUCTIONS
(CLR,COM, INC,DEC,NEG,ROTATE
AND SHIFT INST,)

ROM

outputs,

(TST)

DESTINATION

MICRO BRANCH

@
|
2

MODE

3
4
5
6
"

SOP NON MODIFY INSTRUCTIONS

")
1

ADDRESS

41
47?2

43
44
45
46
47

Page

JSR

THE

SOp

Its

DEC

ROM

purprose

enabled

monitors
however,

instruections,

N
G

37
Ao

~J OV A b W=
W

INSTRUCTIONS

55
56

the

sare

input

26
27

signals

decode

The three output

21
22
23
24
25

signals

the

J{llegal,

CODE

S0p

BRANCH

ROM,

and

¢trap

reserved

I = 92

are

follows,

CODE

INSTRUCTIONS
RESERVED

ILLEGAL

INSTRUCTIONS

INSTRUCTION

(JSR MODE®@)
EMT

INSTRUCTIONS

TRAP

5¢5,3,4

Branch

INSTRUCTIONS

Instructions

Conditional

DEC

branch instructions are completely decoded by
(Eg?)
on
print
K12,
This Roem
18
enabled

ROM

IR11{=TR14

are

active,

The

(N,Z,V

and

decoded,

all low
{mput

and

the

(IRi1l~14=¢ L) and the
IR
DECODE
1
signal
is
monitored are the four condition code bits

bits

(IR15,10,9,8),

output

signal

instruction microcode routine in the
the branch offeset and shift it left

5:65,3,5

Operadte

DEC,

The

(1)

and

BRANCH

(IRP8=1%20

1,)

Wwhen

branch

enabled,

CONTROL STORE
one place,

will

The

branch

sign

extend

Instructions

There are three 256x4
for
decoding
PDPil

TRAP

RRANCH
IR bits

11ines

four

MPC

the
when

Bit ROMs {in the instruection
operate instructions,
These

BRANCH

whiech

ROM

(EB82)

enabled

and

are

moeniters

when

DECODPE

found

the

IR?8

(1)

output

thru

active,

deecoding
ROMs are

circultry
T BIT DEC,

Ki2,

lines

IRQQ

(1)

IR15

(1)

H are

The

PpPDpii

IR@T

all

low

operate

instructions
are decoded inte the
ROM outputs MPC A0 L = MPC 92 L,

following

INSTRUCTION

microe-pc

BIT

DEc

SET CONDITION CODES

CLEAR

CONDITION CODES

(E76)

has

the

same

Its

purpose

decode

and

the

outputs

START

The TRAP DEC
ROMg ,
It

ROM (E7@8) aqain
purpose
s
to

instruetions

and

enable

the

RESET

inputs

RESET,
L

and

Auxiliargy

enables

RTT,

and

ENAB

TBIT

RT]
L

the

instruections

aceordinaly,

IR CODF

RESERVED

and

has the same {inputs as the
previous
two
decode
HALT, reserved, trap and illeqal
outputg aecordingly,

INSTRUCTION

5,6

the

&
7

BRANCH rOM,
activate

ROM

addresses

2
3

RTS
WAIT

MICRO BRANCH
ADDRESS

RESET
RTI

The

Page

INSTRUCTIONS

ap
?

ILLEGAL INSTRUCTIONS
BPT INSTRUCTIONS
IOT INSTRUCTIONS

|
|
0

?
|
D
1
{

HALT INSTRUCTIONS

Enable HLT RQET L

ALU Control

The AUX Control circuitry or the KDiiD consists of three pipolar
shown

on primt

Kii,

ROM

ROMS

NAME

32X8 Bit

AUX DOP

E94

236X8
256X4

AUX SOP
ROT/SHFT

ER9
EB7

Bit
Bit

These ROMs determine the ALU operation to be
performed
whenever
the
‘microecode
executes
the
action X.Y OP B where Y designates a scratch
pad register and X designates either
Register
B
or
a
scratch
pad
register,

The AUX DOP POM deecodes
the
the

CONTROL
STORE
outputs of this

double operand

imstructions

and is

enabled

siagnal AUX SETUP H,
The following table expresses
ROM
as
a
function
of
the Iinstruction
being

Page

represents the B Register and A represents any scratch

O
X

= e

el [

B.A+B

8-(01\).5

(B)

RIS

(B)

B.=A PLUS B PLUS
A,B

MODE

RIC

(B)

B.A PLUS B

SUB
BIT

ADD

) (=B

B_A MINUS B

(B)

BoA

CMP

'ROM OUTPUTS
§1 S¢ CIN

(B)

MOV

INVERT

OPERATION

DR
= e

INSTRUCTION

/- QD
R

pad

o fud

performed,

The AUX SOP ROM decodes single operand instructions and 1is enabled
the
the

CONTROL
STORE signal AUX SETUP H,
The following table eXpresses
ROM outputs as a function of the SOP instructions decoded,

INSTRUCTION

ENAB
REG

FUNCTION

INVERT

CLR (B)

DEC (B)Y
NEG (B)

B.(1.,B) MINUS 1
B2 MINUS B

@
%)

d
i

@
|

|
2]

COM
INC

TST

(B)

ADC

(B)

B.? PLUS B

SBC

(B)

Bo(1,B)

The INVERT
inputs
on

PLUS CIN

MINUS

{

PLUS

{
|

A
%)

B_=B
B.? PLUS B PLUS 1

(B)
(B)

%]
v

)S
0

i
7
@

%)
")
1

i
i

i
a

)
0

@
1
?
1

%)
A
)
|

i
@

@
i

@
|

{

|
82

@0
@

H and ENAB REG L outputs are used to create
the
the
ALEG
of
the
ALU as described previously

section,

ROM QUPUTS
Svd
CIN

@
in

‘

{

i
A

)
)

and
|
tne ALU

Auxiliary contrel signals are algso necessary for performing rotate and
shift

oeperations,

The

ROT/SHFT

ROM

Ki@

decodes

these

CC N H, and CBIT
(1)
H signals,

(1) H
The

instructions and outputs those control signals required te

contents
of
the
also determine the
SERIAL

used

SHIFT

conditien

operations

codes

signals

in determining

operatien.,

OP B

BREG,
SERIAL

ROT

CBIT

Vv BIT

the

AUX

the

Inputs BREG @0(1) Hy
SHIFT H and ROT CBRIT

sent

teo

the

uysed

SHFT

(1)

ROM),

SETUP

~Note

getup

without

s8lowing

BYTE

signal
the

that

performed

step previously mentjioned,
to

This

the

MyX

(print

used

ealculation

¢€or

the

all

B.B

step

where

the
is

B REG shifting

the

rotate

is done to allow

processor,

Kiv)

in the

shift

new

and

before

the

carry

shift

each

X.Y

condition

A summary of the AUXILIARY CONTROL is shown {n the Table enclosed,

©ODE

fi.

TABLE 12
Auxiliary Control for Binary and Unary Instructions
Condition Codes

lnst.

ALU

Nand Z

Function

Cleared

Not Effected

CMP (B) | Load

Load like SUBTRACT |

Load like SUBTRACT | A-BA¥

BIT (B)

| Load

Cleared

Not Effected

A tQB

BIC (B) | Load

Cleared

Not Effected

BIS(B) | Load

Cleared

Not Effected

8 RAB L0 | Loud

Set if OP’s same sign

Set if carry out

A plus B

Set if Carry

A plus B

+1 | Load

ADD

Load

- and result different.

SUB

Load

+-(-)=-

-(-)(H)=+

} A

Set

A Logical

MOV (B) | Load

‘,

CIN

Load

©® | Load

prml

0 | Load

@B Logupl 0 | Load
Load

CLR (B) | Load

Cleared (like ADD)

Clear

Load

COM (B) | Load

Cleared

Set

~B Logical

Load

Aove 8

+1 | Load

INC (B) | Load

Set if dst held 100000 | Not Effected

before OP

NEG (B) | Load

Set if result is 100000 | Cleared if resultis 0;

set otherwise

ADC (B) | Load

Set if dst was 077777

SBC (B) | Load

Set if dst was 177777

and C= 1.

and.‘C=l.

Sct if dst was 100000.

acaad if dfi wzfig
o

and C = |; g& other-

A-B 4

A: plus
&
*:

S | Load
|

]

+C | Load

f Logical

0 | Load

L ofi) MNuSH

wise.

TST(B) | Load

ROR(B) | Z«(C:01)

Cleared
| NoC

Cleared
(0)

Shift Right

(15)

Shift Left

C< (15

Shift Right

N«C

"ROL(B) | Z(14:C)

Neas

ASR(B)

{ Z+(15:01)]

ASL(B) | Z+(14:01)
N < (14)

| NeC
NeC

B())

C«(15)

| Shift Left

Page

5,7

Data

5.7.1

Trangfer

General

Circuitry

Deseription

All UNIBUS
print K6,

data transfers are controlled by the DAT TRAN eircuitrvy
on
This logic moniters the busy status of the UNIBUS, controls
the processor bus control lines BBSY, MSYN, €1
and
C@,
and detects
PARITY ERRORs (PE), BUS ERRORS (BE) and EOT ERRORS (ENT),

57,2

Contrel

5:7.2.,1

Circultry

Proeessor

Clock

Inhibit

All processor data transfers
CONTROL
STORE
output
Ki¢
combines with
transfers) to

5.7,2,2

The

UNIBUS

the

the
TRAN

the sigmal K6 EOT (2)
create K6 TRANS INy I,

UNIBUS
are
initiated
by
the
(1) H (primt Ki0),
This gignal
H (normally a
logic
"i"
bpetween
stopping the pbrocessor clock,

Synchronizatien

synchronjizer

whether

on
DAT

logie shown in Figure

processor

some

other

(from print

Ke&)

peripheral

will

UNIBUS

arbitrates
econtrol

the

UNIRUS,

FIGURE

logiec

"1"

specifies

combine
to
conditions,
NPR

1evel

that

(+3v)

the

create

bus

DATA

this

TRANSFER

the

set

pregently
level

SYNCHRONIZER

input

use,

monitors

Each

the

FEi121

the

speclfic

flip=flop

1lnputs

set

which

bUS

|
=

UNIBUS

Reguest

peripheral
(NPR)

and

has
wishes

aserted
to

gain

Non

Ccontrel

Processor
of

the

bus

Bus SSIN L —C{»
KL DATIP (@)¢

K
BRSY A
K1 NPR H
K1 NPG

K1 NO SAK TD L

KL SSYN H
|

‘

)! s
/

—&

—

Bus I USE

v?@___L

o :

| ‘

;

—
.x‘n""—‘:

L E'R”J

KA DAY tRaN ) H
Kb

EOT () H

’

——

F.'Gu}‘c /7
DATA

FRANSFER

SyscHRoNIZER

’

K STHORT

—

Kb TRAM INH &

TRAD H

Page

immediately,

BRSY

= Another UNIBUS peripherai already has control of the
bus

NPG

and

asserting

bus

busy

(BBsY)

signal,

An NPR device has requested control
of
the
UNIBUS
and
the
KDi1D processor has i{ssued
3 non=processor

request grant (NPG), The condition
may exist
where
the
NPR
device
has already recoqgnized the NPG and
hag dropped its NPR signal while rot having asserted
a SACK or BBSY vet,
NO

SACK

NPR

device

(@)

KD1i1D

When

this

has

requested

processor

input

is8

has

control

true,

issued

all

NPG

the

and

UNTIRBUS,

device
has returned SACK [ ecausing NO SACK TD L to go hiah,
The condition may exist where only SACK L remains on
the
UNIBUS
for
a
period
of
time
before
the
peripheral asserts BBSY,
DATIP

the

above

are overridden,
Generated on
that
the
processor
is

print K6, it
performing

(Reade=Modify=Write)

and

operation

has

signals

indicates
5
DATIP

control

the

UNIBUS (BBSY asserted),
NPR devices
may,
however,
be
qranted
bus
eontrol
but
must
wait unti{l the
processor releases to BBSY before asserting
thelirs,
- (DATIP
oprerations
dictate worst case bus latencies
for NPR devices),
BUS

SSYN

Another

data

transfer

therefore
initializing

none of

the above

signal

clears

the

transfer),

The

(start
any

nolse

that

BUS

may

still

being

the
processor.
another,

must

USE conditions

E121

flipe-flop

circuit

result

from

wait

the

Ki1¢¥ DAT

activates

the

output

the

synehronizer

TRAN

START

FE121
under

and

hefore
|

exist,

and

eompleted

(1)

TRAWN

{lliminates
worst

case

conditions,

5.7,2.3

Once

Bus

the

begins

shown

triggers

Control

START

UNIBUS

TRAN

the

thru

signal

logic

the following

Enables

data transfer

the

diagram

busg

activated,

operation

the

DAT

agserting

Figure

18,

TRAN
Ké

circuitry

ASSERT

ADDRESS

ASSERT

ADDRESS

A1S5)

drivers

(print

and

actiens,

BUS

ADDRESS

(BUS

APg=BUS

K4),

Enables

the

BUS

BBSY

Enables

the

bus

control

determine

the

type

driver

(print

signals

transfer

K6),

BRUS
being

performed,

BUS

which

Page

OPERATION

DATI

DATIP

DATIO

{

DATOR

‘The actual condition of these control lines is determined
the

CONTROL

4, Enaples the
operation

STORE

BUS

belng

5.7.,2,4

outputs

DATA

K10

(BUS

performed
{s a

Figqure
18

C¢

(i)

D@P<BUS
DATO,

and

K12

Di15)

(1)

drivers

1{f

the

DATA TRANSFER BUS CONTROL

MSYN/SSYN TIMEOUT Circuitry

UNIBUS specifications reguire
enabled
no sooner than 150 ns

that the BUS MsYM L
control
after the bus address, data,

lines

meet

have

been

Flgure
19 hasg

asserted,

been

incorporated

Fiagure

this

into

requirement,

the

MSYN/SSYN

DAT

TRAN

the

logic

sigmnal
be
and control

circuitrv
(print

Ke),

CONTROL

The £irst one-shot, E98, delavs the triggerind

the

SSYN

TIMEOUT

Fag€ 76

KS N T TT H— o

o eom

— K6

‘

K§ocdd H

—

fi o0

.
|

C/L

m;fi

kXt
:

—‘

kS PROC INMTL

“

‘

EOAG (AW —

X Q;
EANK

/
: Moy

(@)
L
:

KI SPéd L

¢1

()

_@‘fi [

gL/

ded!

@__J

Ko CoH

BYS BASY ¢

fir;{\/\

—

KL
.

BUS

c{>~— KG

BBSY K

msyA &

syl H

Attow BYTE H

DT TRANSFER

BuSs CoUTROL

G . D
oL

_ *5;/26

+5Sv

R24
56K

82 pf

|15

_5
+3ve

9602
~
AL DTRRT
TRAN¢3VCe
H‘fl) €98 L“"i

ol 9|

6_6____:

E9
22

1
5

1422
\4
-

LO £E68

K6 SSYN H

FlIGvRE

msyn,/sSYN conNTRoL

MO TRUABG (o) L

bl
Joead

—

Ko i

BUS

C{>

[

Duri

weSrCi

K9
¢t
K
‘*‘._‘)flH B-

Kb ENAB

2394
[kl AesERT Abbi?i\sfs

2402

KG STIRT TRAM H

e
|

Noz

TRAN

(L%

Page

one=-Shot

(E9B)
until
approximately 250 ns after the assertion of K6
START TRAN H_,
Once fired, the output af
the
SSYN
TIMEOUT
c¢ne=8hot
enables
the
BUS
MSYN
I, bus driver and waits for the bus peripheral
being sccessed
to return a BUS SSYN L,
When BUS SSYN L
{8
returned,
E98
s
cleared
75 ns
after the SSYN is received negating M8YN angd
cloeking data obtained from
memory
into
the
BREG
or
INSTRUCTION
REGISTER,

57,2,5

BUS

Ervors

Once the SSYN TIMEOUT one=shot is triggered,
SSYN
must be
Teturneg
within
22
microseconds,
If
SSYN {s not returned in this time, E98
times out setting the BUS ERROR (BE) flipe=flep
E115,
1lpon entering
the
next
SERVICE
microcode state, ¢the processor will moniter the

status

5,7.,2,6
Along
of

the

PARTTY

wieh

E98

flip=flop

trap

the

BPE

flip=flop

set,

Errors

clocking

also

and

data

clockg,

The

{nte

the

parity

BREG,
error

IR,

and

detection

latch,

logiec

the

shown

timeout
in

Figure

Figure
I1f

data

(MS{1l=FP,

the
PAL

transfer
MglieHP,

memory will
1L

and

BUS

PARITY ERROR CIRCUIT

belng performed
MMi1eCP

be reflected back to

with

or MMii=-Dp)

the

all

a&a

parity

KD11D or

the

L,
CONTROL

pPB

ERROR

DESCRIPTION

Parity

Regerved

for

future

use

Reserved

for

future

use

Parity

Error

memory

errors

DATI

option

detected

UNIBUS

lines

BUS

Page 774

+3V
DB

BUS PA

BUS PB L

‘E?@/

Chiie

%mL

TTSE,.?

\2__

[._,_‘:?q 5"9}

‘

TIMEoUT (@) H:

J)_'j? .
{5

1474
"

Eleai

,_F’

G o
o)

PAUTY
ENABLE

bs—

K9 DAT TRAY (1) H——

PARITY QRRoR CuRcbn
TM
RGURE. 20

' .\".a-@

()

Yage

Errers

found

while performing

a DATIP or

DATI

(K& €{

trues

#1111l

result {m the PARITY ERROR flip=flop (E121) being set when E98 tlmes
Processor operations resulting from PARITY ERROS wili ©be
out,

discussed

further

Note

the

that

in the BUT SERVICE section to

entire

follow,

PARITY ERROR circult can be

disabled by

Temoving

jumper
Wi
and
inserting
another
Jumper
in the Space provided for
jumper W2, .Note also, that the detection of a PARITY ERROR
forces
&
BUS ERROR conditen,
|
|
|

5,7,2,7

End

Transtfer

Cireuitry

Te svnehronlize the DAT TRAN logle with the main KD1iD processor elock,
the END OF TRANSFER (EQI) cireuitry has been incorporated into.the CPU

(print Ké6),
Approximately 109 ns
after the
SsYN
TIMEOUT
one=shot
(F98)
times
out,
the
EOT flip=flop (E115) is clocked removing the
L,
INB
previously discussed processor clock disabling signal K6 TRAN
I+
a BUS ERROR hag been detected, the delaved s8ignal that clocked the
EOT f1ipeflop generates a 17® ns pulse on the K6 FORCE
SERV
H
1line,

This

pulse elears the miero=pc address latches

K9 foreing
PROC
CLK

microepec and microroutine is available in the
whieh

£fo0llows

Anether

on print

CONTROL

STORE

section

later,

Figure

5.7.,2,8

(MPCO@=MPCWV7)

the processor to enter the SERVICE mieroroutine on the next
L
lowetoehigh
transitien,
An
exXplaination of the terms

Data=InePause

circuit

CIRCUITRY

Transfer

inecluded

transfers
(DATIP)
initiating a DATIP

ENDeQF=TRANSFER

the

DAT TRAN

logic

detect

DATA=IN=PAUSE

Upon
bus econtrol signal RRSY,
the
controls
and
¢flip=£flop
the
operation,
(READ=MODIFY=WRITE) bus

Page 75/

K6 PE (D H

2 ’{)'

Ko SSYN H

sl TimBoud (DjH
-

Ne—ry

K3 DAT TRAN () H

L
W H
B M
}-2——xe6 BRE

vl_\-.

7473

—

EUSE

hed

+ 3V

+5V

ENs

EOT*CO

CHD - oF - TRANGEER
e
Cieul

] B

7374

EQT

Q) H

QIR

{

7;223

_ W FORCE ST oy
_

Page

E97

1{s

DATO

portion

latehed

forcing

the

procegsor

routine

has

asserted,
ne
other
UNIBUS
This feature often determines

Figure

S5¢7.2,9

0d4d

Addregss

hold

been

BUS

B2sY

completed,

unti'

ihe

Whi{le

BBSY

is8

peripheral can seize control of
the maximum bug latency for NPR

DATA=INePAUSE

the n»us,
devices,

CIRCUITRY

Detection

To prevent odd addressing
errors,
two
NQOR
gateg
(E68)
have
ingerted
be¢tween
the
SSYN
TIMEOUT
one=8hot (E98) and the BUS
driver,
These gates prevent the assertion
of
MSYN
{f
an
odd
address

1{s

being

approval

the

ALLOW

BYTE

one=8hot

and

thus

would

5,8

The

would

Power

KD11D

SP?@

eondition

allowed

receiving

timeout

BUS

The

true)

exists,

without

SSYN,

(CONTROL
ever

end

without

the

output

K14

STORE
the

SSYN

asserting

result

oveen
MSYN
bus

TIMEOUT

BUS

this

MSYN

operation

ERROR,

Restart

fajil/auto

restart

eircuitry

(print

KS)

gerves

iLl.e

purposes?

InitlaliZes

the

Unipus

known

Preyents

falijure
actual

routinpes,
of

the

microprogram,
state

the

Unibus

immediately

the

microprogram of

the

for

power

The

after

controel,
power

and

the

applied

computer,

Notifles

Because

(Ki

this

depends

UNIRUS

true),

Faill/Aute

the

The

the

performed

detection

power

following

beinag

never

the

placed

mieroroutine
be

proecessor

fall/aute

operation
proper

<the

from

after

responding

i{nitial
restart

the

sequencing

electrical

an impending power

prorerites

impending

powery

startup,
seguences

power
two

failure,

are

fall/auto

bus
of

signals:
the

miecroprogranm

restart
AC

Unibus

circuitrv
and

LO,

drivers

and

(39¢ 79A

Kig Ct () H

PRoC \W\T L

DATA- 10 - PALLE

FIGURE

INIT

POWER UP
. _PDWN

(

|
I

_’lA'I’—

lAH)Oms

[

+3V

BUSDC LO L gy

+5V

BUS AC LO L gy

Qe TRY

—

— l“—AtZ’&ns
I

le——H60ms ——
|
]
|
P
| 1

o6 6ms—
1 -1187

~~Fizaiget9 BUS AC LO and BUS DC LO Timing Diagram

Page

recelvers, the entire computer system
machine
to
operate,
Therefore, the
fail in peripherals as well as in its

The notification of power status
transmitted
from each device by

unasserted
pefore BUS AC LO
asserted, it 18 assumed that

system

there

powe!
down

of any
PDP=i1
the signals ByS

sufficient

s&upply

L is
the

8hows

stored

energy

that

BUS

BUS DC LO
component

in the regulator

capacitors

1is
LO

{s
of

not
the

the

When BUs AC LO L 1s not asserted,

operate the computer for § ms,
|

immediatelvy,

system component
AC LO L and RBUs DC

unasserted,
When
power
In
every

to operate,

sufficient

must
be
powered
up
for
the
processor is notiflied of a power
own ac source,

The powereup sequence

L (Figure 23y,

should power be shut
.

?taure‘ZB‘ RUS AC LO and BUS DC LO Timing Diagrarm
As

AC power §{s removed, BUS AC LO L {s asserted
¢first
by
the
power
supply
warning the processor of an {mpending vower fallure,
When BUS
DE LO L i{is asserted, it must be assumed that the. computer
system
can
no
Jlonger
oberate predictably,
Memories manufactured by DEC use RUSR

PDC LO L as
available,

switen signal, turmning them off, even £ power
{5
still
Time A +2
(Figure
23)
{s
the
time delav between the

assertion of

greater

BUS AC

than

LO L and the

ms,

This

allows

assertion o¢

BUS DC LO L,

for

power

it must

rapidly evycled

and

off,
According to
PDPe=l11
specifications,
upon
S8System
sgtartun,
a
minfimum
of
2ems§
run
time
{g
qguaranteed
before a power fall trap
eecurs, even if the line power
{8
removed
simultaneously
with
the
beginning of the power-up sequence,
After the power fall trap oeg¢curs,

minimum

Given

the

eqgquipment,
A

2=m$

run

time

tolerances
+2

must

guaranteed before

permitted
greater

thap

the
5

timing

m§,

the

system

circuitry

shuts
used

down,
most

Page

When

pending

power

fail

sensed,

program

trap

ocecurs

causing

the

present contentg of R7 and the PSW to be pushed onto the memory stack,
85 determined by the contents o0f R6 (Stack pointer register),
R7
1s
then
loaded
with
the
contents of memory location 24(8), the PSW is
loaded with the contents of location 26(B),
Proeessing
{8
continued
with
the
new
R7
and
p8SW,
The user’s program must prepare for the
impending
bpower
fajilure
by
storing. away
volatile
registers
and
reloading
lecation
24(8)
and
26(8)
with
& power=up vector,
This
vector
When

pointg

power

the

beginnlng

restored,

the

o¢

regtart

processor

loadg

routine,
R7

with

the

contents

location 24(8) and the PSW with the eoentents of location 26(8),
After
locading these reglsgters, the
user
program
presuymably
will
prepare
locatioens
24(8) and 26(8) for another power failure,
If the HLT RQST
L input 1s agserted by
an
external
switeh
closure,
¢the
processor
powers up through leocationg 24(8) and 26(8) and halts,
Sehematics
found
on

pulgse

for the power fall, auto restart, and
print
K5,
One=shot Ei1@ generates a

soon

BUS

nonasserted

bus
15?2

atter

reset
1logic
ms processor

oower

are
INIT

applied

the procesSor.,
At the end of 15@ ms, the PUP one=ghot, E1¢Q3, is fired
it BUS AC LO L {5 not asserted and the orocegsor bedgins the R7 and PSW&
load
roeutine,
The PUP one=shot generateg a 2=ms pbulse, during which
the assertionm of RUS AC LO L 18 ignored,

The triggering of the 154 ms INIT one=ghot a4iso presets the POWER INIT
flipeflop
E{(99,
Setting
this lateh forees the CONTROL STORE to run
the power up routine beginning at mieroe=pe addregs @@i,
It
s
this

routine

that

reads

locationg

24(8)

and

26(8)

for

the

mew

and

psW,

After PUP has been reset, the asgertion of
BUS
AC
L[O
[
fires
the
one=shot,
PDWN, E103,
Fllo=flop E97 is set causing a power fall trap
te be recognized by the microprogram
on
entering
¢the
next
SERVICE
state,
Varjous traps are arbitrated by the BUT SERVICE ROM E71 (print
K8),

I1f
AC

a momentaryY power fallure oceurs whieh caduses the assertion of
BRUS
LLO L but does not cause the agsertion of BUS DC LO L, the processor
will restart when the PDWN (@) L one=shot times out, retriggering
the
INIT one=shot simultaneously with DC LLO H beeoming nonasserted,
When
K12

RESET instruetion
START
RESET
L
1s

(erint
the

5.9
The
KS .

K8),

This

processor

PROCESSOR

i{is

decoded by ROM E76, the ROM
<clocked
into the START RESET

flipeflop

continues

output

occur

onlyv

1@¢

signal
flipeflop E149

INIT,

afterwhilech

operation,

CLOCK

KD{iD procCessor clock eircuitry
A
single
delay line is ugsed

the entire
proecessor,

triggers

output

is
to

shown in
generate

Figure 24 and
a pulge train

orocessor {s synchronized,
Since It
{8
events
that result in the alteratiom of
on defined edoes of the procesgssor €lock,

on
to

print
which

a
£ully
clocked
storadge registers

Page

Figure

If all cioCK disable inputs

running

pulse output

soon

1Is

volts

fixed at

are
is

262 mng

PROCESSOR

CLOCK

unasserted,

applied,

as per

The

the

periocd

Filgure 25,

<clock
of

the

will

begin

oscillator

Ko TRAN CLK H

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Page

Figure

PROCESSOR

CLOCK

TIMING

DIAGRAMS

S,1#

5,1,1

O
©
©
®B

During

the

During

@& priority

Whilie

®»

During

®B

During a BUS INIT from another device,
The INIT portion of power up routine,
The INIT portion of power down routine,

After

VO DA
D W R

clock is turned on and off by means of gating the feedback through
delay
1ine,
It {e turned off under the following conditions by
appropriate signalsy
.
|

Yusd

The
its
the

Wwhen

PRIORITY

BUS

RESET,

BUS

BUT
SACK

bus

data

executing

the

manual

SERVICE
is

asserted,

transfers,

HALT

eloc¢k

ARBITRATION

Requests

arbitration

Interrupt,

instruetion,

enabled,

delay,

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Page

The KD{i=D responds to
of
the
other
PDPeli
the Unibus im order teo
proeesseor
program
by

bus requests (BRs) in a manner similar to
that
pProcessors,
Peripherals may request the us¢ of
make data transferg or to interrupt the curr«snt
assertina
a 8ignal
on one
of four BR 1ines,

numbered 4, Sy 6, and 7 in order of increasing priority, For exawmpie,
1§
two deviees, one at priority 5 and the other at prierity 7, assert
BRs simultaneously, the
deviee
at
prierity
7
{8
servieced
¢first,
Furthermore,
{f the processor priority, determined by bits (A7=05) of

the PSW,
than
4,
the

is at level 4, only devices that
such as BR 7, BR 6, or BR 5, are

order

priorities

for

all

BRs

Priority

and

other

Service

Hignhest

HALT

BUS

regquest BRs at levels higher
serviced,
Table 13 contains
traps.

Order

Instruction

ERRORS

INSTRUCTION

TRAPS
TRAPS
OVERFLOW
POWER FAIL
HALT SWITCH

TRACE
STACK

BR7

BR6

BRS
BR4

Lowest

i{instruction

PRIORITY

SERVICE

TABLE
S{inee
after

that

BR
the

¢an cause a
eompletion

requests

vector

away

the

eontentg

current

interrupt

the

Unibus

contents

the

ORDEFR

program inteprupt,
it
mgy
be
serviced
only
aof the current imstruetion in the IR,
A device

program

address

feteh

PSW

vector

must

data

the

lineg,

and

R73

address,

aporopriate

The

then

and

new

time

processor

new

pPSW

1ls

are

E32)

and

10gic

the

for

Teeejved
latehed

microprogram
true),

from

frcm

the

of
how
SERVICE

fellew,

Arbjtratien
BRs

stacks

loaded

contents of the veetor address plus two,
Further descriptions
the processor handles thig BR routine will be discussed im the

sectlion

place

first

The

present

recelved

Arbitration

into

enters,
RR

BRs

procegsor

HLT

PSwW7
BR7
PSW6

RQST

FEi{4

the

priority
by

whlch
E7

print
UNTRUS

(74174

SERVICE

ABRITRATION

not,

perftormed

shown
¢from

reqgister

the

PRIORITY

and

AdAilrectly

ROM

(PSW

Quad

(E7)

then

has
of

Figure

26,

receivers

D=Type

(K9

<734>)

order

and

state

received

the

(UNIBUS

BUT

lateh)

when

SERVICE

(1)

determines

higheyr

the

priority

thanm

highegt
are

All

E20,

and
the

whether

the

highest

priority,

shown

belows

Page 85
BR6

PS5

BR§

PSw4
BR4

the

highest

processor,

the

With

RQST

HLT

di{sabled

transferred

of
a

higher

corresponding

received

grant

enable

the

trap

the

UNIBUS

instruction
BG

INH

until

pending,

sigral,

the

priority
ROM

ENABLE

output

the

level
is

than

the

asserted

low,

processor

The

actual

flip=flop

BUS

clock

GRANT

ES5

will

set,

not

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Stop clock when Vo

BC INH L

ENAB BQ

(L_l)

A _ f\\

BUS GRANT H J'

{ \ |

BUs SAck Lo 7

\(’

\ —/ /

Sack TD

RET

(‘ I
\

No SaAcK To
L

Figure

BUS

REQUEST

G
—

SAack

TIMING

Grants both BG and NPG are controlled by the synchroniZer logic
below

and

K7,

Figure

GRANT SYNCHRONIZER

shown

fl;gé‘ ¥ 74

K9 BuT SERVICE() R

[Tlrwes— CLK B6 ENAR
____/

M% CLK NPG
-

IMITH _“CL_._/[ :

L K7 NPRH

NO SACK TD H

G RA/\/TA; SYNCHRoONIZER
FICORE

1.8

——F

88
Page
This cireuitpy arbitrates
Request

(set
(1)
lew,

Granted)

will

whether

result

or reget) was deactivated
H
s detected first, the
After a delay of 175 ms,

£lip=flop
ESS5
Once E55 is get

provided

the

UNIBUS

drivers

BG,

Upon

the

(pus

then

returns

receliving

BUS

flip=flop
removing
RETURN flipeglop to

Removal
assert

bus

depending

or
on

NPGC

which

(None=Precessor

£lip=flop

input

line

first,
If the set {nput K9 BUT SERVICE
Q@ output of E73 (pin 9) will transition
this signal
will
eleeck
the
ENAB
BRG

there {8 no BUS SACK L s{gnal on the UNIBUS,
grant arbitrated by ROM E7 is
ehanneled
onto

E26),

Once

the

requesting

peripheral

receives

BUS SACK L,
SACK L, the
the
BUS
Keep

of BUS GRANT
BUS
INTR
I

processor

then

clears

{ts

GRANT from the UNIBUS and
processor clock disabled,

the

sets

ENAR
BG
the SACK

causes the peripheral te drop
its
RUS
SACK
L,
and enable & vector address onto the UNIBUS data

lines,
The processor then deskews the removal
of
SACK
RET flipreflop (E73) and enables the processor

SACK,
clock

<clears
again,

the
Once

in operation, the processor clceks the peripheral veector address
into
the
BREG,
returns
BUS
S8SYN L and begins runninag the microcode trap
routine which branches the processor to the interrupt handling program
determined

5,13,2

NPRg

the

vector

Noneprocessor

are

facllity

communicate

Reguests

with

obtained,

the

each

(NPR)

Unibug
other

that
with

permit

devieces

minimal

the

participation

Unibus

the

processor,

The function of the
processer
in
servicina
an
NPR
s
simply to give up control of the bus in a manner that does not disturb
the execution of an instruction by the processor,
For
example,
the

processor
DATIP

wWi{ll

when

the

set

input,

E55

reset

enables

relinguish

the

bus

following

the

DATI

portion

set
the

clearing

the

inbut

the

NoneProcessor

not

transferl.

E73,

Q output

BUS
BUS

NPG

will

SACK

NPG

device,

and

The

will

NPR

becomegs

transition

not

low

true,

unasserted
causirg

The

output

befOre

the NPG
of this

Unibus
1line
granting
the
bhus
requesting device will them return

wait

until

the

bus

free

(no

the

flip=flop

flipeflop
to
BUS

BBSY),

the
SACK

Page

Figure
29

5.,17,3

Halt

Unlike all
could
be

imput

HALT

Grant

NPG

PRIORITY

ARBITRATION

Reguests

previous
PDP=11 processors the KDi1iD
considered
another
priority levels

used to

{is

monitor

detected

the

(K12

USER’S CONSOLE

HLT

RQEST

has
K12

implemented
HLT RQST L,

HALT/CQNTINUE

activated),

the

switch,

processor

what
This

I¢

will

recognize it as an interrupt request
(priority 1level
{s
shown
|{n
Figure
13) upon entering
the next SERVICE microstate,
The processor
will then innibit the
processor
cloeck
(Figure
26)
and
return
2
recognition
signal
(K7 HLT GRANT H),
Upon receiving K7 HLT GRANT H,
the console drops the K12 HLT RQST L and asserts
complete controel of both the UNIBUES and KDi11iD,

RUS

SACK

«gaining

The User can maintain the processor in this
inactive
(HALTED)
state
indefinitely,
= Upon
releasing
the
HALT
sgwiteh,
the Users Console
releases BUS SACK L
and
the
processor
continueg
operation
as
{f
nothing had nappened,

5,11

SERVICE

TRAPS

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Page

$.11,1

Rll

General

Description

Interrupts,

error

traps,

KD11D

by the

serviced

and

instructien

are

most

be completelvy

trapg

are

recognized

and

when the processor enters what is called the’

SERVICE micro-instruetion state,
state

critical
to

The functions performed during

the

understood,

operation

the

processor

and

this

should

Upon entering the SERVICE state, all bU§’ihterfugtsyerf§r traps,
iastruetion
instruetion

trap

traps

are

realized

during

arpbitrated
by the

condition is

S.11¢2

Cireuylt

Rom E71

services a

the

SERVICE

perfermance

ROM

E71

and

the last

Kg),

Each

then serviced aceording
te its prierity as shownm
in

Operation

speclific

trap by generating a vector

address

unigque

to
that
¢trap
econdition (Table 15), Upon leaving the SERVICE state,
the processor is forced to push its present program counter
(PC)
and
processor
status
word (PSW) onrto its memory stack and fetch a new PC
from the location specifled by the vector address,
A new FSW ls
then

obtalned

<£frem

software

S§Suproutine

result

the

these

memory

operations,
18 that

wrltten

location after
the

variousgs

trap

conditions

vector,

s now

The

performing

the

user

which

could

whieh

cause

the

brocessor

ERROR

indicates

indicate that a specific error occured,

The

the

processor

correct

vector

are

end

follows,

BUS

ERRORS

BUS

has

actempted

memorvy

return

memory

BUS

detectioan

the

sccess

lecation

SsYN

eirculery

previously

that

within
£or

deseribed

processor

none=existent

that

bus

did

not

usec,

The

errors

the

was

DAT

TRAN

gection,

Once detected, the bus error eonditien
of
flipeflop
EL15 (print K6) is clocked into
lateh
Ei1#1
(print
Ki9)
on
the
next
lowetoehiah
transition
of
PROC
CLK
L

creating
Double

the

error

buffering

is cleared at the
mieroeingtruction

detect
the

STACK

QVERFLoOW

ERROR

trap

AnYy

Double

attempt

location

end of
step

Bus

required

Error

the
and

FLAG

(1)

because

data
used

E115

transfer
again to

condition

during

routine,

decrementing
the
POINTER
FREGISTER
KN11D

sigral
1s

staeck

will

the

limit

result

precessor

contents
of
(R6)
bevond
in

(K1l

8=-1580

the

STACK

the
the

of
STACK
49@

the

OQOVERFLOW

(print K8)

flipeflep E{134

being set

Page

the

next high=towlow transitien of PROC CLK H,

Figure 3@
PARITY

ERROR

STACK OVERFLOW

the
that
indicates
ERROR
PARITY
8
to {nput data from a
attempted
processor
parity memory and that memory Indicated
a
parity

error,

was
ecireuitry
The PARTITY ERRQOR detection
TRAN
DAT
the
in
described
previously
error
the
detected
Once
section,
is clocked
FEi121
flip=flop
of
condition
next
the
on
into latewn E101 (print Ki#)

PROC CLK L low=toe=hiagn

Double
FEi121 is

step

allowing

error

conditioen,

end of

POWER

FAILURE

The

the data trangfer

eoutput

(print

asserts

TRACE

TRAP

trangition creatina

Ki@ pE FLAG (1) H,
becauge
necessary

K8)

Ei115

the
is

BUS AC

when

‘

This trap 1s

bprogranm

double

flipeflop
the

indicating

pQWQfa

1s
the

microinstruction

detect

PWR FAIL
set

buffering
cleared at

power

loss

céfitfolled

bus

E97

subply

the

a
insert
to
him
allowing
‘User
processor/user interactive subroutine into
The trap {s enapled by
main program,
nis

setting the Psw
TRIT
(K2
T8IT
(1)
L),
the next instruction
of
combletion
Upon
(K12 ENAB TBIT L), the J=K flipeflop
E134
is set
creating
the
KT
BIT FLAG (1) H
gignal,

fi)y o

KII

K§

8-15= g L

24¥HI02

- Kg 7oV (1)
H

R6L

K9 Enag sTov L

K& PREC CLKH

K5 PRoc /x
|1 |

K@ SToV Srrv L

)—

7474

+3VY
Kg

BvT

SeRvice

(1)
H —

— K® BuT seRVICE L

STACK

OVERFlLowW

FIGURE

KatairoL
Ki2 E¥AB T BIT.L

@
KE

74HIo 3

——

——TR
P

PRoz ¢iXH-L
o

K8 T 8IT seqv "1

Ks PRoc INMITL 'j
T BIT FLAG

FIGCGUVRE

TB.T

FLAG ()H

PIH

Page

Fiqura

IR CODE @@LIR CODE QzL

"TBIT

FLAG

< These three binary coded trap siqgnals
generated
~and E75 on

the IR DECODE
by
and
K12,
print

'f@llowifig trap ccmditions

ET?
the

e S = D)

Qhe

R e D

S
e
YR e

NS BBRSO

above)

TABLE

are

INSTRUCTION

(none

B |

HLT INSTRUCTION
TRAP INSTRUCTION
EMT INSTRUCTION
I0T INSTRUCTION
BPT INSTRUCTION
ILLEGAL INSTRUCTION
UNUSED

ROMS E69,
indicate

IR CODE LINES

TRAP CONDITION

RESERVED

Upon enterin@ the SERVICE micro={nstruction state, the'%EvaCE‘Rom E71

moniters
any combination of the above trap conditions, TIf any inputs
are enabled, the Rom forces the processor to branch to a speecial
TRAP
routine
on the next micro step by asserting the microe-pc address line
- MPC99
L, While still in the SERVICE state, the Rom also generates
a
speclifie
veetor address (Table 15) using outputs C2, C3 and C4 and
L
SA
~channels it onto the processor AMUX lines bv activatinq K9 AMUX
xwhare”it is then latched 1n the BREG,
Before leaving the SEPVICF state E71 also clears the conditi{on
which
caused
to origimal
trap,
This
is
done by asserting one of tne
fellowing oueputss
K8 TBIT SERV H, STOV SERV L, PFAI], SER L
or
INST
The first three of these outputs clear their respective
L,
SER
TRAP
CODF
IP
the
by
specified
traps
For those
trap signals directly,

lines,

hnowever,

it is necessarv to remove the Instruction in the IR,

This operatien i1s performed by the INST TRAP SER I, output whienh ORs
with the PROC CLK to generate K5 SERV IR L whien in turn removes the
the
This operation prevnnts
trap {nstruction from the IR,
e@nditicn,
trap
from laopihq on th@ same

processor
o

to force
:‘qu-BUS REQUst-(BRs). the BUS INTR control signal 1is allowed
‘MPC@? L ‘during SERVICE

provided there are no other traps of higner

Page

priority.,
By enabling this line the processor will branch to the TRAF
ROUTINE
and
veector
to
the
address specified by the BR device,
If
there {8 a trap of higher priority BR interrupts
are
prevented
from
receiving BG by the SERVICE TRAP L outpbut of E71,

OCTAL

UNIBUS

VECTOR

ADDRESS

TRAP CONDTITIONS

A04
a1e
P14
P20
@24

Time=out & other error
Illegal & regserved {mstructions
BPT, breakpoint trap
10T, input/outpuyut trap
Power Fail

EMT emulator

734
114

TRAP inmstruction
Memory Parity Error

Trap

VECTOR ADDRESSES
TABLE 15

5. .12

CONTROL

5,12.,1

The
by

0f
to

STORE

General

Description

CONTROL STORE circuit (orint K9 and K1¢) consists of five 256 word
8 bit blpolar Roms, seven Quad D=Type flip=flops and an assortment
gates and multiplexers,
This logic operates in a
similar
¢fashion
&
microprocessor
having
eight
address lines and 32 data outpuf

lires

with

fixed

gat

Fach

CONTROL

STORE

Rom

location

capable

configuring

Rom

the

program
can

data

routines,

generate

path,

performed by the arithmetic/logic unts

eirevitry
or
each location

speclfic

determining

(ALU),

set

the

outputs

function

influencing the DAT TRAN

{n general controlling the total KD11D,
The contants
is configured in
a
manner
that
allows
sequences

oOf
of

locations

to be combined into microroutines which perform the various

conslidered

pDPell

1instruction

5.12.2

Branehing

operations,

microinstruction

Fach

Rom

microstep,

location

{is

therefore
|

Within Microroutines

Each microingtruction in the CONTROL STORE specifies the
location
of
the next microstep in a sequence,
After the execution of a micCrostep,
the output of Rom E138 1s loaded into the MpC
(microproaram
counter)
lateh
to
specify
the
location
of the next microstep,
Conditioral

branching within a mieroroutine 18 accomplished by wire=0ORing
generated

external

hardware

onto

the

MPC

lines

when

signals

directed

some

other

CONTROL

STORE output,

Typical

wire=QRed

signals

Page

are

follows,

Instruction pecode

= As
previously
mentioned,
the
microroutines
the CONTROL STORE are designed to
in
contained

efficlently perform the operations specified
by
the
various
PDp=11
iInstructiens,
Specific
microroutines
are
Iimplemented
for
specific
instructions,
The
main
purpose
for
the
IR
DECODE

c¢ircuitry

tranglate

the

PDP1]

instruction
in the IR to a set of hits that
pe wire=ORred onte the MPC limes upon request
DECODE
L) developing the next contrel word,
adequate

for

description

Instruction

each

the

&pecific

ineluded

was

csarn
(IlF
An

addresses

1in

the

DECODE seection,

TRAP DECODE

« Routines have alsoe been included
STORE
toe

pap

the

stack,
SERVICE
by

the

{implement error

BYTE

PSW

onte

Iin

off

the

which
the

CONTROL

push

and

processor

Upon
regquest of the CONTROL STOKRE (BUT
(1) H), the MPC @@ line can
bhe
enabled
SERVICE ROM (E71) causing a microbranch

to one of
RRANCH ON

and

routines

these microroutines,

The various
whether
an

performed,

microsteps

PDP=11 instructions are dependent on
even or odd byte operation 1is beinag

Modificetieans

used

for svecific

made by
enabling
(BUT
based
on
even
or odd

the

Sequence

Iinstructions

can

be
BYTE
L)
microhranches
byte instructions in the

IR,

PWR RESTART

« Upon prerforming a

power

restart,

the

MPC

cleared by INIALIZE (INIT),
The pPwWrUP circuitry
(PwR
1line
@
on print K5 then enables the MPC
INIT
flipeflop
Ei1?29) forcina the CONTROL STORE
HPC
at
to perform the PWR UP routine beginmina
address

one

(@01),

In general, mlerosteps are not executed
from
numerically
seguential
locations
in
the CONTROL STORE and care should therefore be taken in

foliowing

the

flows

described

Figure 32 shows the format
STORE,
The
¢filelds,
the
signifiecance 0f each value

Chapter

of all
256
words
in
possikle
values
thev
are described below,

the
KDI11D
c¢contain,

CONTROL
and
the

» Wo2d dS14MD g2kAAFIS | R YP
N
N
@

Page

5,12,3

CONTROL STORE FIELDS

FIELD

DESCRIPTION

FIELD
LENGTH

MPC

Eight

the
be

perfermed,

scratch
pad
operations
the following format,

OPERATION

SP
CONTROL

Read

&
1

Write
Write

low byte
word and

Write

word,

BYTE

bit microe=pc address which specifies
ROM location 0of the next microstep to

Determines
according to

CONTROL

BUT

Allows

braneh

DECCDE

the

a bhyte,
Even

Odd

Actual

logic

Branches
Bvyte

will

ENAB

force

heing

MPC

performed

follows,

Byte

branch

instruction

enahle

logic

shewn

Ki2,

BUT SERVICE

Indicates that the processor
the
SERVICE
microestepr,
SERVICE ROM E71, causing the
recoagnize
any
pending
interrupts,

BMODE

Controls the operation 0f
the
BE=Register
during
each
microstep,
The
1latched
outputs of this fleld can be wire=0Red
by
other
CPI logi¢c,
Coding of these Signals

follows,
BMODE

BMODE

QPERATION

HOLD

SHIFT

RIGHT

SHIFT

LEFT

i
BUT

has
entered
Enables
the
brocessor
to
errors
or

DATA

PARALLEL

Multiplexed controel lines
which
the following enable signals,
BUT

DEST

Enables

LOAD
generate

microbranch

destination
operand
microcode
Cerresponding logic is on print

sequence,
K9,

Page

WQVefngw
SR

‘Stack
L -flEh&bl@fl
STOV
ENAB
detection circuit on orint K&,
ENAB

DBE

foreces

Enables

circuitry

processor to

bus
error
Corresponding

halt

during
logle on

which

on detecting

this
print

microstep,
Kii,

LOAD PSW L = Allows the PsSW register to be
loaded
See

upon

prints

LOAD
Z, V
this

primt

completion

TRAN

(1)

this

microstep,

K2,

CC L = Allows the condition codes
and C to be loaded upon completion
microstep,
Cirecuitry
1is&
shown

N,
of
on

Ki,
BUT

BUT

A
@
B

)
P
1

@
i

%
1|
1
1

i
@
)
i

i
%)
{
7

Enables

OPERATION

UNUISED
UNUSED

NEST
L

LOAD CC L
FNAR DRE L
LOAD PSW L
ENAB STOV [

UNUSED

{

1
"DAT

and

data transfer circultry

K6 ,
Indicates
that
the
performing a UNIRUS transfer

nprint

processor
1§
durina
this

microstep,

BUS

CONTROL

Enables

the

and BUS C1

ALLOW

AMUX

BYTE

UNIBUS

L. as

control

lines

BUS

C¢

follows.,

Ci1(1)H

CA(1)H

TRANSFEFR

@
@

@
|

DATI
DATIP

i
1

@
|

DATO
DATOR

Gates the UNIBUS contrel BUS MSYN
L
when
bvte
instruetions
are
being
performed
(print
K6),
Also
helps
generate
the
signal K& INH +1 L during bvte operations,

Controls the
according

AMUX

select

1lines

AMUX

DATA

the

follewing,

the AMUX

Page

ENAB SEX

(1)

Enableg

PSW

ALU

i
i

?
i

Service vector
UNTBUS DATA

the

Data Path

logie

whieh

low

the

through

the

extends

bvte

bits

(primts
the

sion

the

outputs

BREG

uoper

and

K2)

the

data

(bit

07)

bvte,

ALU
ALU
ALU

S3=ALU 8@,
MODE, and
CIN
|

Determine
the
operation performed by the
ié=bit
ALU
according te
Table 9,
These
linegs
are
algso
wire=0Red
allowing
the
AUXILTIARY
CONTROL
eircuitry to determine
the ALU operations according to Tanle 12,

SPA

MUX

Controls the select l1ines
Pad Address Multiplexer,

SPA

MUX

SPA

MUX

SPA

the

BUS

)

INSTRUCTION

|
1

)
{

INSTRUCTION REGISTER BITS 0p=92
CONTROL STORE ROM SPA 0@e=03

Sratch

OUTPUT

ROM SPA

ADDRESS

BITS

©¥A=03

BITS

@6=48

Allow microinstructions from
the
CONTROL
STORE
to
determine
which
Scratch
Pad
register will be addressed during the next
microstep

the

SPA

uUnless
otherwise
MUX
control
lines

expressed

oy
previously

mentioned,

AUX

SETUP

Enables
operate

LOAD

Allows
loading
Register,
(Print

6,4

MICROCODE

6,1

MICROPROGRAM

A complete Set
form
in
the

the AUXILIARY COMTROL
miereinstructions,

of
Kii)

the

Roms

during

Instruction

FLOWS

of microlnstruetion flows {8
8hown
{n
engineering
ecircuit sechematie paeckage,

simplified version that provides

an overview and

detaliled
flows,
No attempt will be made
path of this microcode, but the following
adeguate backqround for the reader,

aids

block
Figure

diagram
33 {s a

using

the

in this manuval to trace each
examples should
provide
an

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Page

6,2

10¢

FLOW NOTATION

6,2,1

Mierostep

Mnemonic

Names

All mierosteps have mnemonic names whiech signify the type
{nstructien
being
performed,
A micreroutine will often weave back and reuse part
of another
i{f
the
operations
are
identical,
To
understand
the
significance
of
the various mnemonic names the follewing definitions
apply,
All xs shown indicate the instruction mode and Y {ndicate
the
step

number,

MNEMONIC

DEFINITION

SMXeY
~
MDMXeY

Source
mode
instruetion,
Destination
single

microsteps

mode

operand

for

microsteps

any

£or

double

Modifving

Degstination mode mierosteps for
single operand instructions,

Mierosteps contained in FETCH microroutine,

SERV

SERVICE

TRAP=Y

Microsteps used upon recognition of an
instruetion (IOT, BPT, EMT or TRAP),

ROTX=Y

Microsteps

for

ROTATE

SWBXeY

Mierosteps

for

SWAB {nstructions

JMPXeY

Microsteps

for

JUMP

instructions

JSRX=Y

Mierosteps

for

JUMP

RTS=Y

Miecrosteps

for

Return

RTIeY

Microsteps

for

microcode

(RTI)

and

subroutine

from

double

and

WAIT

RESET

CCC =Y

CLEAR Condition Code microsteps

SCC=Y

Set

REST=Y

Microstep

interrupt,

Shift

instructions
RTI

and

Return

micresteps

Code microsteps

from

travo

instructions,

instructions

restarting

instructions,

Interrupt

RSET=Y

for

Modifving

gubroutine

Miecrosteps

{nstruetion

Non

Arithmetie

WeY

Condition

and

state

Return from
Imstruetions,

for

Aouble

inmstructions,

NDMYeY

TRAP

operand

power

failure,

from

Page

141

SBEe=Y

Source routine microsteps
mode 2) instructions,

for

even

byte
-

(except

source
|

SBO=Y

Source routine microsteps
mode 2) instrucetions.,

for

odd

byte

(except

source

SMBEe=Y

Source routine
instruetions,

for

source

microsteps

mode

SMBO=Y

Source routine microsteps for source

MDBeY

Modify byte
D,

MXOBeY

Modify

odd

byte

mode

Shown,

instruetions,

MXEB=Y

Medify

even bvyte

mode

destination

NoneModity

NDOBeY

destination

NMOB=Y

for

mede
2 odd
destination

byte

mode

destination

instruction mierosteps8

for

destination

odd

mode

odd
mode

byte
and

instruction

byte

instruction

microsteps

byte

Iinstruction

microsteps

even
mode

mierosteps

for
for
=

for

byte

{instruetion

microsteps

for

Microsteps for MOVE instruction destination mode
@,

MOVeY

ROTATE byte

ROTR=Y

instruction miecrosteps

for

destination

mode

odd

bvte

ROTATE

REBX=Y

mode
|

ROTATE

ROBXeY

instructien

microsteps

even

bvte

for

destination

for

destination

ingtruction

miecrosteps

Flow Notatien Glossary

The block flowg should be self-explanatory,

them:,

for

even

destination

62,4

bVte

mierosteps

modes

Non=Modify

NMEB=Y

instruetioen

even
-

8shown,

NomeModify

NDER=Y

instruction mierosteps

the

following

glosgsary

flow

notation

To aidv‘ifi
should be

understarnding

reviewed,

Page

102

FLOW NOTATION GLOSSARY

Definitien

Designation
BA

Unibus Bus
Assignment

}

Separator
)
Initiate DATI operatien on Unibus
Plus, the arithmetiec operator
Program Counter = fcrateh pad register
B Reglister
Instruction reglister
|
B Reg sign extended (bit 7 repeated in

DATI

Plus
PC

IR
B

SEX

Address lines
operater

15),

(R7),

bits

.
through

Seratch Pad Register specitied by the source portion of
the eurrent instruction [IR (836)]
destination
Seratch
Pad
Reagister
specified
by
the
portion of the current inmstruction IR (2:0)]
STORE
seratch Pad Register n specified by the
CONTROL
ROM SPA linesg,

RD
Rn

Allew byte Unlbus reference
Enable the stack overflow detectlon logle,
Enable the double bus error detection logic,
Initiate DATO opberation on Unibus
Initiate DATIP operation on Unibus
Lower byte of the Scratch pad Register specifled by the
destination portion of the current instruction,
Specifies m ag the mnemoniec 0f the next microsten,
ALY tunctioen determined by the
Auxiliary
ALU
control
logiec as & functien of the ingtruection currently in the

ALBYT

ENAB

OVER

ENAB

DBRE

DATO

DATIP

RDR

J/m
Rmn OP

Instruction
Branch

BUT

COND

DATA

B(SWAR)

Contents

MINUS

gswapped,
MINUS the

6,3

mierotest,

Set condition codes (N,Z,V and C) according
¢to
result
of operation being performed by the ALU,
Data being received from the UNIBUS data lineg BUS
D@@
LeBUS D1% L,

CODES

UNIBUS

arithmetiec

with

UuUpper

and

1lower

bytes

operator,

MICROPROGRAM EXAMPLES

6,3,1

PDPeili1

Instruction

Interpretation

To {lilustrate the interpretation of PDPe=i1
of

CMp

Ingtruction

in the RUN state (i,e,,
instruetion

(&8

located

traced

through

the

instructions,
mierocode,

the execution
The

machine

the machine is executing instructions) and the

Iin

memory

location

1094,

Page

Location Agsembler Symbolic
1000

CMP

#15,

1902
1004

CHAR

{03

Octal
222767
200015
Ban100

1166
This
7

CHARY

WORD 0

imstruetion compares the literal

sets

the

condition

Flgure

Figure

First
This
memery

CMP

code

accordingly,

to the contents

Source

mode

and destination
mode is relative
shows

the

simplified

#1%5,

CHAR

(©222767),

flow

for

Simpilified

the

CHAR

immediate

(mode 6,
CMP

Flow

example,

Diagranm

the ingtruction is fetched from memory (microsteps F1
and
is the same fetch microroutine used to get each instruction
and

update

the

PC,

and

(mode

F2),
from

(age 1024

BUT SERVICE -—-'{

F-l‘ FETCH

CONSOLE

(START OR CONTINUE)

(F-2 BUT IR DECODE
)
DOUBLE OPERAND INSTRUCTION
4

SM 2-1 SOURCE MODE 2] (ADDRESS MODE 2)
Imo-2 BUT

DESTINATION

NpM 6 -1 DESTINATION

MODE 6

(ADORESS MODE 6)

@ERV BUT SERV!CE)
FETCH

Figure 34

CMP #15, CHAR (022767), Simplificd Flow Diagrum

Page

LOCATION

MICROSTEP

NAME

ACTION

122

§123

BA_PC,DATI,
BoIR,LUNIBUS

J/F2

COMMENT

ADDRESS lines
the
DATI
a
data
the
Load
transfer,
into
memory
£rom
" received
B Register and the
the
" boeth
Jump
Reglister,
Ingtruction
Drive

DATA,

the

UNIBUS

with the contents of
PC (R7) and initiate

next
the
. te
(Loes
123),

123

PWIREORED F2

with efftset
of ingstruction
decoded

PCPC

PLUS 2,

BUT Ir DECODE,.
J/SERV

Add

twe

the

immediate

mode,

microstep

contents

Program Coeunter Bramch on

the

Micre tegt to the {instruction
the
by
determined
~ routine
instruction decode logic,

Sinee the Iinstruction 18 of the double operand group, the next step 1is
Source mode 2 is autoeincrement (Autolnerement
to get the spurce data,
{mplies one 1evel of deferred addressing), when used with R7 (PC), it

becomesg

{044

Page

LOCATION

MICROSTEP

LOCATION

NAME

114 WIREORED =

SM2e{

with

BYTE

status

ACTION

COMMENT

BA.RS,DATI,

Place

the

BUNIBUS DATA,

(@8128)

on the UNIBUS Address

ALBYTE,

BUT

gource

BYTE,J/5M202

lines,

contents

specifed

the

will

contain
the
location of the:
source data
(1002)
In
this
example,
Initiate
a UNIBUS
DATI
to
actually
get
the

data,
ALBYT
will
allow anodd UNIBUS transfer,
‘{f
the
IR
contains
a
byte
KA
the
and
instruction
contains
an
odd
address,
wWitheut

the

ALBYT,
&
UNIBUS
that
addresses
an

tranzfer

odd

results

bus

error,

Input the

into

data

the

micrebranch

locations
vhether

from

byte

SMBE=1
SMBQe1

114

124

104

@ WIREORD
with dest mode

SM2=2

RS..RS PLUS
J/8SM@e=2

SM@e2

RiiB,
BUT DEST,J/SERV

following

(odd

dependi{ng

mieroroutine

perform

Mode
the

starting

operation

NDM6ei

{ndicated

6, when uged with the PC,
word
cuyrrently
pointed

(address
data,

the

index word

plus

will
by

get

the

requires that the
index
to by the PC be added to
two)

get

the

peing

for
for

not byte
even hytes

for

odd

bytes,

Store
spurce
operand
Seratch Pad Register
{1
microbranceh
to

destination

CODE

even)

Add two to the contents of the
source register,
Mierobranch
te
the
next microstep SMR=2
|
(124),

destination

The

and

the

ingtruction
performed,
SM2=2

memory

data

routine,

and

instruction,

contained
1in
the updated PC
location of the source

{n
and
the

Page

LOCATION

233

MICROSTEP
NAME

COMMENT

ACTION

NDM6=1

Perform
@ UNIBUS DATI transfer

BALPC,DATI,
B.UNIBUS DATA,

_to obtain the index word and
|
the B
Register,
~place it in

. J/NDMe2

233

235

NDM6ée2

PCPC

PLUS

J/NDM6e=3

235

230

Add two to the eontents
proegram
counter
microbraneh to NDM6=3,

"B.B PLUS RD,
J/NDM3e3

NDM6 =3

231

164

NDM3e3

(230)

destination

J/NDM3=4

pad

BAsR12,DATI,

Place
(R12)

obtain

baUnibus

BUT

data,

BYTE,J/NDMO=2

will

allew

trangfer

destination

12,

I1¢£

the

odd
IR

instruction
following,

NDM@ =2

B.Ri1

COND

SERV

odd

even

bvyte

NDM@e2

not

byte,

source

(CMP)

condition

BUT SERVICE,J/F1

the

codes

useful

trace

this

according

each

lnstruction,

situations
to intervene

higher

seme

priority

exist,

mieroprogram
proceeds
next FETCH (F1),

This completes the example of the mieroprogarm inferpretation
may

and

that
before
- the
next instruction = 1is
fetehed,
Thelr
wvprioritires
are
arhitrated
as
shown
in
Table
13,
If
no conditions
the
the

I¢t

byte

“Mierobranch

end

various
attempt

with

$5,CHAR,

the

destination operands and set

CODES,

J/SERV

SERVICE,
162

one

NDERB=1

Operate

Input
an store
Register,

NDOBe=i

result,

UNIRUS

contains

byte
ingtruction,
destination
operand
it
in
the
B
Microbraneh iIf byte

164

address

destination address
om UNIBUS and perform
UNIRUS DATI operation,
ALBYT

“ALBYT,

the
8and

operand,

TRANSFER address of
oberand to scrateh

NDM3=4

Add index word to contents of
destination register specified
bY

230

step NDM6e=2,

“Microbranch

other

CMP

{nstruction

126

107

Page

through the detailed flovw diagrams avalilable in the KDI11D print set,

6,3,2

Intergupts

and

Traps

Interrupts and traps are also accomplished by the mieroprogram,

foliew

the

miecrocode

LOCATION

NEXT
LOCATION

102

necessary

for

these

MICROSTEP
NAME

SERYV

COMMENT

ACTION
BUNIBUS

DATA,

BUT SERVICE,
J/F1

pIF NOT SERVICE REQUEST

TRAP=11

R13.B,J/TRAP®2

1814

TRAP=21

R6R6 MINU8
ENABOVER,
J/TRAP=3

101

125

TRAP=3}

BAR6,DATO,
ENAB DBE,
UNIBUS DATA,PSW,
J/TRAP=4

TRAP=4}

R6R6 MINUS
ENABOVER,

§BRANCH ON SERVICE REQUEST

JLOAD VECTOR INTO BREG

) IF SERVICE REQUEST GO TO TRAP={

103

108

The

routines.,

yMOVE

CONTENTS

yTO SP REGISTER 13

TO F1

JSUBTRACT TWO FROM STACK

PERMIT OVERFLOW

jPOINTER,

JOUTPUT PROCESSOR STATUS TO
ENABLE DOUBLE

s STACK,
sBUS

ERROS

) SUBTRACT TWO FROM STACK POINTER

JALLOW OVERFLOW

J/TRAP=5

110

TRAP=51

111

TRAP=61

B_PC,J/TRAP=6

JMOVE

BAR6,DATO,

sOUTPUT PC

UNIBUS DATAWLB,

CONTENTS

TO STACK

J/TRAPe7

113

TRAP=7§

115

TRAP=83%

jMOCK

NOP,J/TRAP=@

INPUT

BA=R13,DATI,
BL.UNIBUS

MIRCO=STEP

DATA,

NEW

FROM

ADDRESS SPECIFIED

MEMORY

BY SP

J/TRAP=9

pADD

TWO

115

120

TRAP=9}

R13-R13 PLUS
J/TRAP=10

120

121

TRAP=10¢

PCoBsJ/TRAP=11

sLOAD

121

122

TRAP={111

BA-R13,DATI,
B UNIBUS DATA,

JINPUT NEW PROCESOR STATUS INTO REGISTER
g PROM LOCATION SPECIFIED BY

J/TRAP=12

NEW

35? REGISTER 139

Page

122

6,3,3

Restarts

TRAP=12¢

Frem

Power

Upon restarting the KD11D,

PSW.B,J/8ERV

) LOAD
JINTO

NEW PROCESSOR BTATUS
P8W REGISTER

Fatlure

the processor begins running the

microcode

routine
at
MPC
1location
one,
This routine alliowe the processor to
obtain its PC (program counter) and P8W (Processor 3tatus
Word)
f£from
memoery
and
then
begin
running the program specified, "This Restart
routine {8 as follows,

MICROSTEP

LOCATION

NAME

362

RESTe1}

B.PC,J/REST=?2

s PROGRAM COUNTER TO B REGISTER

362

363

RESTe2t1

R5.B,J/RE§Te3

JMOVE

163

364

RESTs31

R13.0,J/REST=4

JZERO 8P REGISTER

364

365

REST=41

P1{3_R{3 PLUS 2,

368

3166

REST«5:1

366

367

REST=61

367

370

REST=7¢

ACTION

COMMENT

J/RESTe8

R13.R13 PLUS R13J,

J/RE8T=6

R13_R13 PLUS
J/RE§T=7

R13.R13

JPERFORM NEXT 5 STEPS TO
JOPTAIN

A8 THE CONTENTS

JOF 8P REGISTER 13

PLUS R13,

J/RESTe8

370

113

RESTe81

113

R{3_R13

PLUS

R!3,

J/TRAP=8

118

TRAP=8t

BA.R13,DATI,
B.UNIBUS

DATA,

g INPUT NEW PC FROM MEMORY
) ADDRE8SS

SPECIFIED

BY SP

J/TRAP=9

115

129

TRAP=91

R{3_R13 PLUS
J/TRAP=10

120

121

TRAP=10%

PC.B,J/TRAP=11

TRAP»i11§

BAR13,DATI,

121

B_UNIBUS

1292

TRAP=123

DATA,

JADD TWO TO 8P REGISTER {3

JLOAD NEW PC
s INPUT NEW PROCESSOR S8TATU8
)FROM LOCATION SPECIFIED BY

J/TRAPe®{2

8P REGISTER 13,

PSWB,J/SERV

JLOAD NEW PROCESSOR S8TATUS
JINTO P8W REGISTER

INTO

108