This document is the preliminary manual for the KD11-D Processor (PDP-11/04), published by Digital Equipment Corporation in 1975.
The KD11-D is a single-board Central Processor Unit (CPU) designed for the PDP-11/04 computer series. It connects directly to the UNIBUS, managing its allocation for peripherals, performing arithmetic and logic operations, and decoding instructions. It supports direct data transfers between I/O devices and memory, handles both 16-bit word and 8-bit byte data, and utilizes single- and double-operand addressing.
While program compatible with the earlier KD11-B, the KD11-D offers significantly higher processing speed. Notable differences from the KD11-B are a key focus:
The manual outlines the KD11-D's instruction set, including addressing modes (such as accumulators, auto-increment/decrement pointers, and index registers), instruction timing, and detailed descriptions categorized by function (e.g., single/double operand, program control). It also delves into detailed hardware descriptions of the CPU's components like the Data Path, Arithmetic Logic Unit (ALU), Scratch Pad Memory, B Register, Processor Status Word (PSW), UNIBUS Address and Data Interfaces, Instruction Decoding, and control circuitry. Furthermore, it covers CPU operating specifications, bus latency times, power fail/auto restart procedures, and provides an overview of the processor's microcode flows and examples.
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