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Document:	KB11-C Processor Manual (PDP-11/70)
Order Number:	EK-KB11C-TM
Revision:	001
Pages:	376
Original Filename:

OCR Text

EK-KB11C-TM-001

KB11-C PROCESSOR
MANUAL (PDP-11/70)

digital equipment corporation - maynard. massachusetts

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon-

sibility for any errors which may appear in this
manual.

Printed in U.S.A.

This document was set on DIGITAL’s DECset-8000

computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

PDP

FLIP CHIP

FOCAL

DIGITAL

COMPUTER LAB

UNIBUS

MASSBUS

DECUS

9/85-15

TABLE OF CONTENTS

SECTION 1

BLOCK DIAGRAM AND CONCEPTS

SECTION I

PROCESSOR

INTRODUCTION

CHAPTER 1

INSTRUCTION DECODE AND MICROPROGRAM CONTROL

CHAPTER 2

DATA PATHS

CHAPTER 3

PROCESSOR CONTROL REGISTERS

CHAPTER 4

TIMING GENERATOR

CHAPTER 5

DATA TRANSFERS

CHAPTER 6

ABORTS, TRAPS AND INTERRUPTS

SECTION III

CONSOLE

INTRODUCTION

CHAPTER 1

SWITCHES, INDICATORS AND OPERATION

CHAPTER 2

LOGIC DESCRIPTION

SECTION IV

MEMORY MANAGEMENT

INTRODUCTION

PDP-11/70 ADDRESS SPACE

CHAPTER 1

GENERAL DESCRIPTION

CHAPTER 2

MEMORY MANAGEMENT MAPPING FUNCTION

CHAPTER 3

PAR AND PDR ADDRESSING DURING RELOCATION

CHAPTER 4

GENERATION OF THE PHYSICAL ADDRESS

CHAPTER 5

ADDRESS VALIDITY

CHAPTER 6

DESCRIPTION OF PDR

CHAPTER 7

READING AND WRITING OF PAR AND PDR REGISTERS

CHAPTER 8

MEMORY MANAGEMENT ERROR HANDLING

CHAPTER 9

MEMORY MANAGEMENT REGISTERS (MMRO, 1, 2 and 3)

SECTION V

UNIBUS MAP

INTRODUCTION

CHAPTER 1

GENERATION OF THE PHYSICAL ADDRESS

CHAPTER 2

UNIBUS/CACHE INTERFACE

CHAPTER 3

READING AND WRITING THE MAPPING REGISTERS

SECTION VI

CACHE

CHAPTER 1

CACHE CONCEPTS

CHAPTER 2

PDP-11/70 CACHE

CHAPTER 3

THEORY OF OPERATION

CHAPTER 4

DETAILED LOGIC

APPENDIX A

BLOCK DIAGRAMS

INTRODUCTION

This manual describes the KB11-C Central Processor Unit, which is the basic component of the
PDP-11/70 Programmed Data Processor System.
The purpose of this manual is to:

provide an overall understanding of how
the KB11-C functions in the PDP-11/70
System.

describe how the KB11-C logic works in
sufficient detail to enable maintenance
personnel to perform on-site troubleshooting and repair.

The format of this manual is functional, i.e., the intent is to explain the various processes that are exe-

cuted by the KB11-C, as opposed to a module by

Section

contains a description

of the

Cache.

Appendix A contains both a System Data
Paths and a System Address Paths block
diagram.

Due to the numerous references to specific logic
functions in the text, it is recommended that the
reader refer to the PDP-11/70 Engineering Print Set
while reading this manual.

Comments (both favorable and unfavorable), suggestions, and corrections are welcome. A Reader’s
Comment sheet is provided for this purpose at the
end of this manual.

module logic description. Since this might be a
problem for a technician who has a module to repair, an index of logic functions by module is

RELATED DOCUMENTS
This manual should be used in conjunction with the

provided.

following related publications:

PDP-11/70

This manual is divided into six sections:

Maintenance

and

Installation

Manual

Section I is an introduction to the PDP-11/70.
It describes a block diagram of the system
and introduces some system concepts.

MJ11 Memory System Maintenance Manual

Section Il describes the processor. Its six chapters explain processor control, data manipulation,

Control

Registers,

timing,

PDP-11/70 Processor Handbook

FP11-C Floating-Point Processor Manual

data
RWS04/RWS03 Fixed Head Disk Subsystem

transfers and error handling.

Maintenance Manual

Section 11l provides both an operating guide
to the Console and a detailed description of

RWP04

its logic.

Maintenance Manual

Scction

describes

Memory

Management

TWUI6

Moving

Head

Disk

Subsystem

Magnetic Tape Subsystem

and address space.

nance Manual

Section V describes the Unibus Map.

PDP-11 Peripherals Handbook

Mainte-

SECTION 1
BLOCK DIAGRAM AND CONCEPTS

Unless otherwise indicated, references within this section pertain to this section only.

SECTIONT

BLOCK DIAGRAM AND CONCEPTS

CONTENTS

CHAPTER 1

BLOCK DIAGRAM

1.1

BLOCK DIAGRAM

1.1.1

Processor

1.1.2

Memory Management

1.1.3

UnibusMap

1.14

Cache

. .. ... ... . .. e e

1.1.5

Unibus

. . . . . . o e
e
e

1.1.6

Optional Equipment

1.2

. . . . . .

e e

. . . . .. L
. . . . . . . .

e s

MEMORY SYSTEM

L e

. . . . . .o oo

. . . . . . . . . .. .

e e e

. . . . . . e
e

1.2.1

Representation and Storage

. . . . ... ... ...

12.2

Address Space

1.2.3

Mapping

1.2.4

Parity

CHAPTER 2

. . . . . L

. . . . . o o

e e e
e

e e

e e
e

e e

e
e

. . . . e

CONCEPTS

2.1

MICROPROGRAMMING

2.2

PARALLEL OPERATION (PIPELINING)

. .. .. ..

2.3

VIRTUALMACHINES

2.4

REENTRANT AND RECURSIVE PROGRAMMING

. .. ... .. .. ... .. ...

. . . . . . e
i e
. ... ... .. ... .......

ILLUSTRATIONS

Title

Figure No.
1-1

PDP-11/70 Block Diagram

1-2

PDP-11/70 System Simplified Block Diagram

1-3

Highand Low Byte

. . . . . . . . . .

1-4

Memory Addresses

. . . . . v v v it e e

1.5

Word and Byte Addresses

1-6

Main Memory Addresses

1.7

AddressPaths

1-8

Physical Address Space

1-9

16-Bit Mapping

. . . . . . . . . . . . ..
o

. . . . .. ... ... ... ... .....
o i

e e

e e e e

e e

. . . . . . ...
e
e
. . . . . . . .

e e

. . . . . . . . e
e
e
. . . . . . . . . . .

. . . . o . o v o i e

1-10

I8-BitMapping

. . . . . . . o o

1-11

22-BitMapping

. . . . . . .

1-12

Parity (P) in the PDP-11/70 System

e e e e e e e e e
e
e

e e

. . . . . .« o o v v vt i it

L-ii

e
e

e e e e e

e e

CHAPTER 1

BLOCK DIAGRAM

The PDP-11/70 is the most powerful computer in

Memory Management for relocation and pro-

the

tection in multi-user, multi-task environments.

PDP-11

large,

family.

It is designed

sophisticated,

high-performance

operate in
systems.

can by used as a powerful computational tool for

Ability

high-speed,

Main Memory.

real-time

applications

and

for

large

access

million

bytes of

multi-user, multi-task, time-shared applications requiring

large

amounts

of addressable

space. Although it is a

memory

Optional high-speed mass storage controllers

16-bit machine, it applies

as an integral part of the CPU. These con-

the power of a Cache memory and 32-bit memory

trollers provide dedicated paths to high per-

and

formance storage devices.

1/0O

structure

demanding,

multi-function

computing requirements.
Optional Floating Point Processor
The PDP-11/70 contains as an integral part of the
Central Processor Unit (CPU), the following hardware features and expansion capabilities:

1.1

BLOCK DIAGRAM

The PDP-11/70 is a medium scale, general-purpose

Cache memory organization to provide bipo-

computer.

lar memory speed at core memory prices.

shown in Figure 1-1.

block

diagram

of the

f’_——______—_—'——"__—“__—l
FLOATING
*

PROCESSOR

‘I

CONSOLE

CENTRAL

UNIBUS

PROCESSOR
MEMORY
MANAGEMENT

UNIBUS

HI-SPEED

CONTROL

[7]|

HI-SPEED | | HI-SPEED

HI-SPEED

CONTROL [ | CONTROL

CONTROL

UNIBUS

[]

PERIPHERAL

CACHE

-}
_eewocy
|\
MEéV\ORY

1/0

BUS

MAIN

MEMORY

= [NDICATES 32-8IT DATA BUS

1/0

BUS

]

170

BUS

MASS

STORAGE
PERIPHERAL

* = OPTIONAL

n-315

Figure 1-1

PDP-11/70 Block Diagram

I-1-1

computer

logical operations required in the system. Memory
Management is standard with the basic computer,

allowing expanded memory addressing, relocation,
and protection. Also standard is the Unibus Map,
which translates 18-bit Unibus addresses to 22-bit
physical memory addresses. The Cache contains
2048 bytes of bipolar memory that buffer the data
from Main (core) Memory. Main Memory is on its
own high data rate bus. The processor has a direct
connection to the Cache/Main Memory system for
high-speed access.

The PDP-11/70 Console allows direct control of
the computer system. It contains a power switch for

the CPU. This switch may also be used as the master switch for the system. The Console is used for
starting, stopping, resetting, and debugging. Lights
and switches provide the facilities for monitoring
operations, system control, and maintenance. Debugging and detailed tracing of operations can be

a Unibus Terminator and Bootstrap

The KB11-C Processor performs all arithmetic and

M odule.

Also standard are 128KB of parity core memory.

Memory, in the PDP-11/70, is not on the Unibus,
but on its own high-speed bus (refer to Paragraph
1.2).

1.1.1

Processor

The Processor is the instruction execution section
of the system. It implements the PDP-11/45 instruction set. It also acts as the arbitration unit for
Unibus control by regulating bus requests and transferring control of the bus to the requesting device
with the highest priority.

The Processor contains arithmetic and control logic
for a wide range of operations. These include highspeed, fixed-point arithmetic with hardware multiply and divide, extensive test and branch oper-

accomplished by having the computer execute

ations, and other control operations.

all locations can be examined, and data can be entered manually from the Console switches. Console

The Processor is described in Section Il of this

this manual.

1.1.2

single instructions or single bus cycles. Contents of
operation and logic are described in Section III of
Also within the CPU assembly are pre-wired areas
for an optional Floating Point Processor, and for
up to four optional high-speed I/O controllers
(RH70 Massbus Controllers). These controllers
have direct connections through the Cache to Main
Memory (using the Cache only for timing
purposes).

The Unibus remains the primary control path in
the 11/70 system. It is conceptually identical with

previous PDP-11 systems; the memory in the system still appears to be on the Unibus to all Unibus
devices. Control and status information to and
from the high speed 1/O controllers is transferred
over the Unibus. This expanded internal implementation of the PDP-11 architecture has no effect on
programming the PDP-11/70.

Three Unibus devices are standard on the PDP11/70:

a KWI1I-L Line Time Clock

a DLI1 Synchronous Serial Interface (an
LA36 DECwriter II is also standard in
the PDP-11/70)

manual.

Memory Management

Memory Management provides the hardware facilities necessary for address relocation and pro-

tection. It is designed to be a memory management

facility for accessing all of physical memory and for

multi-user, multi-programming systems where memory protection and relocation facilities are
necessary.

In order to most effectively utilize the power and ef-

ficiency of the PDP-11/70 in medium and large
scale systems, it is necessary to run several programs simultaneously. In such multi-programming
environments, several user programs could be resident in memory at any given time. The task of the
supervisory program would be to control the execution of the various user programs, to manage the allocation of memory and peripheral device
resources, and to safeguard the integrity of the system as a whole by control of each user program.

In a multi-programming system, Memory Management provides the means for assigning memory
pages to a user program and preventing that user

from making any unauthorized access to these
pages. Thus, a user can effectively be prevented
from accidental or willful destruction of any other
user program or of the system executive program.

The basic characteristics of Memory Management
are:

16 User mode memory pages

16 Supervisor mode memory pages
16 Kernel mode memory pages

Whenever a request is made from the Processor to

fetch data from memory, the Cache does an address compare to see if that data is already in the
Cache. If it is, it is fetched from there and no Main
Memory read is required. If the data is not already
in Cache memory, 4 bytes are fetched from Main
Memory and stored in the Cache, with the requested word or byte being passed directly to the
processor.

8 pages in each mode for instructions
When
8 pages in each mode for data

a request is made from the Processor to

write data into memory:

Page lengths from 32 to 4096 words

If it is stored in the Cache, it is written
both to the Cache and to Main Memory, thus assuring that Main Memory is

Each page provided with full protection and

always updated immediately.

relocation

Transparent operation

If it is not stored in the Cache, it is written only to Main Memory.

6 modes of memory access control
Memory access to 2 million words (4 million

Unibus Map references to memory are executed in
the same manner as processor references.

bytes)

Memory Management is described in Section IV of
this manual.

Because it stores 1024 words, and because programs tend to use localized sections of code and
data, the Cache already contains the next needed
word a very high percentage of the time, indepen-

1.1.3
Unibus Map
The Unibus Map is the interface to the Memory

dently of the program.

System

(Cache and Main Memory) from the
Unibus. It performs the address conversion that allows devices on the Unibus to communicate with
physical memory by means of Non-Processor
Requests (NPRs). Unibus addresses of 18 bits are
converted to 22-bit physical addresses using relocation hardware. This relocation is enabled (or dis-

The Cache is also the interface between the high-

abled) under program control.

Most of the computer system components and pe-

The top 4K word addresses of the 128K Unibus ad-

other on a bus known as the Unibus. Addresses,

dresses are reserved for CPU and I/0O device registers and is called the Peripherals Page. The lower
124K addresses are used by the Unibus Map to ref-

data, and control information are sent along the 56

speed /O controllers and Main Memory.

A detailed description of the Cache is contained in
Section VI of this manual.
1.1.5

Unibus

ripherals connect to and

communicate with each

lines of the bus. Refer to Figure 1-2.

erence physical memory.

The Unibus Map is described in Section V of this
manual.
1.1.4

Cache

‘Tt
CPU

1/0

170 l ‘ 1/0

The Cache is a high-speed memory that buffers

1/0

-3192

words between the processor and Main Memory.

The Cache is completely transparent to all programs; programs are treated as if there were one
continuous bank of memory.

Figure 1-2

PDP-11/70 System

Simplified Block Diagram

The form of communication is the same for every
device on the Unibus. Peripheral devices use the
same set of signals when communicating with the
processor, memory, or other peripheral devices.
Each device, including memory locations, processor
registers, and peripheral device registers, is assigned
an address. Peripheral device registers may be manipulated as flexibly as memory by the central processor. All instructions that can be applied to data
in core memory can be applied equally well to data
in peripheral device registers.
Processor Unibus operations are described in Section 1I, Chapters 5 and 6 of this manual. Cache
Unibus operations are transacted through the

Refer to the following manuals for detailed descriptions of these high-speed devices:
RWS04/RWS03 Fixed Head Disk Subsystem
Maintenance Manual

RWP04

Moving

Head

Disk

Subsystem

Maintenance Manual

TWU 16 Magnetic Tape Subsystem

Mainte-

nance Manual

MEMORY SYSTEM

1.2

Unibus Map (Section V).

1.2.1
Representation and Storage
The PDP-11/70 is a 16-bit machine. The data is

1.1.6

stored in Main Memory in blocks, each of which
consists of two 16-bit words. Thus, the PDP-11 instruction set and the addressing modes are identical
to other PDP-11s, but data storage is implemented
in a 32-bit configuration. This is transparent to the

Optional Equipment

Floating Point Processor

The

Floating

Point

slots in the Central

Processor

fits

into

Processor backplane.

prewired
It pro-

vides a supplemental instruction set for performing

single- and double-precision

program and to the processor logic.

floating point arith-

metic operations and floating-integer conversion in
with the CPU. The Floating Point Pro-

The PDP-11 data word consists of two 8-bit bytes,

cessor provides both speed and accuracy in arith-

parallel

as shown in Figure 1-3. The program addresses ei-

metic

ther a single byte, when it uses a byte instruction,

computations.

It provides

decimal

digit

accuracy in single word calculations and 17 decimal

or a 16-bit word, when it uses a word instruction.

digit accuracy in double calculations.

Floating point calculations take place in the FPP’s
six 64-bit accumulators. The 46 floating point instructions include hardware conversion from singleor double-precision floating point to single- or

double-precision

Floating

Point

integers.

Refer

the

00
LOW BYTE

HIGH BYTE

1
n-3193

FPII-C

Processor Manual for a detailed
Figure 1-3

description.

High and Low Byte

High-Speed Mass Storage

four

high-speed

1/O

controllers

can

plugged into the KB11-C backplane. A dedicated interface (wired on the backplane) connects these con-

From the point of view of the program, memory

trollers to the memory. A separate bus (Massbus)

can be viewed as a series of locations, with a num-

connects the controllers to high-speed devices. Pre-

ber (address) assigned to each location. Thus, a

sent DIGITAL devices that utilize this bus struc-

131,072-byte PDP-11 memory could be represented

ture are the RP04,

as in Figure 1-4.

RS04,

RS03, and TUI16. The

RPO4 is a moving head disk pack drive with capac-

ity for 88 million bytes and a transfer rate of 1.25

Because PDP-11 memories are designed to accom-

microseconds per byte. The RS04 is a fixed head

modate both 16-bit words and 8-bit bytes, the total

disk with a capacity of 1024K bytes and a transfer

number of addresses does not correspond to the

rate of 1 microsecond per byte (1.2 microseconds at

number of words.

50 Hz). The RSO3 is a fixed head disk, 512K bytes,

tain 128K bytes and consist of 777 7774 byte loca-

2 microseconds per byte. The TUI16 is an industry
standard 1600 bpi tape unit.

. tions.

Words

locations.

A 64K-word memory can con-

always

start

even-numbered

Main Memory stores data in blocks. A block con-

LOCATIONS

sists of two 16-bit words (plus 4 parity bits). Figure

00 000 000

1-6

00 000 001
00

shows

how

shown in

Figure

000 003

000 004

data

for

the

same

memory

1-5 is stored in Main Memory.

Block boundaries are located on program addresses

000 002

the

whose low-order octal digit is either O or 4.

Main Memory addresses are block addresses. The

processor and the Unibus use word addresses and

the

OCTAL

ADDRESSES<

Cache

translates

these

addresses to

block

addresses.

The Cache, which is the interface to Main Memory

00 777 774
00 777

for the processor, the Unibus and the high-speed
[/O controllers, reads and writes Main Memory as

775

00 777

776

_ 00 777

777

listed below for each of these units:

High-Speed 1/0 Controllers

N-3194

Figure 1-4

Memory Addresses

Read:

double word only

Write:

double

word,

single

word,

byte.

Low bytes are stored at even-numbered memory locations and high bytes at odd-numbered memory lo-

cations. Thus it is convenient, from the point of
view of the program, to represent the PDP-11 mem-

The controllers listed in Paragraph 1.1.6 do not im-

ory as shown in Figure 1-5.

plement byte writes.

16-BIT WORD

BYTE

08 07

8-BIT BYTE

BYTE

00 000 001

HIGH

LOW

00 000 000

00 000 003

HIGH

LOW

00 000 002

00 000 005

HIGH

LOW

00 000 004

\./M)

HIGH

LOW

00 777 774

00 777 777

HIGH

LOW

00 777 776

HIGH

LOW

00 000 000

HIGH

00 000 001

LOW

00 000 002

HIGH

00 000 003

{

LOW

00 000 004

{

HIGH

00 777 775

HIGH

00 777 777

WORD

00 777 772

{

LOW

BYTE

WORD ORGANIZATION

Figure 1-5

\_/J

00 777 773

00 777 775

WORD

Word and Byte Addresses

I-1-5

ORGANIZATION

00 777 776
N-3195

BLOCK

WOBP |

WOBB 0

BYTE 3

BYTE 2

BYTE

BYTE O

00 000 003

00 000002

00 000 001

00 000 000

00 000 007

00 000 006

00 000 005

00 000 004

00 000004
00 000 010

e
00 777 760

00777 767

00777

766

00 777 765

00777 764

00777 773

00777 772

00 777 771

00 777 770

00777 770

00777 777

00777 776

00 777 775

00777 774

00777 774
11-4000

Figure 1-6

Main Memory Addresses

Processor or Unibus

Read:

This address is an

double word, but only Word 0

or Word 1 are transmitted to processor
or Unibus
2.

Write:

18-bit address in the case of a

Unibus reference and a 22-bit address in the case of

a memory reference. The Unibus Map converts 18bit Unibus addresses to 22-bit Cache addresses.

single word (Word 0 or Word 1)

or single byte (one of bytes 0, 1, 2, or 3).
1.2.2

Address Space

The PDP-11/70 uses 22 bits for addressing physical

memory. This represents a total of 222 (over 4 million) byte locations.

UNIBUS

MEM. MGT. | 18 ADDRESS BITS
22

BITS
with

the

PDP-11/70. Main memory uses 22 bits, the Unibus

CACHE

ITS

UNIBUS

ADDRESS

Three separate address spaces are used

18 ADDRESS

MAP

Le22 ADDRESS BITS

uses an 18-bit address, and the computer program
uses a

16-bit virtual address. This information

summarized below:
16 bits

program virtual space

216 = 64K bytes

18 bits

Unibus space

218 = 256K bytes

22 bits

physical memory space

4 million bytes

22
ADDRESS
BITS

MAIN
MEMORY
11-4001

Refer to Figure

1-7.

Memory Management gener-

-ates the physical address output for the processor.

Figure 1-7

Address Paths

Processor Addresses
See Figure 1-8. Of the over 2 million 16-bit word locations

possible with

the

128K

top

rather than

are

the 22-bit physical address,

used

physical

reference the

memory.

Unibus

of each other. They are both part of the KB11-C
and are included in all PDP-11/70 systems.

Refer to Figures 1-9 through 1-11.

Maximum physical

memory is therefore 22 - 2! bytes, or a total of
1,966,080 words. The system size boundary is the

Mapping of processor addresses is per-

formed in one of three possible ways by

highest address available with the amount of mem-

Memory Management:

ory included in the system. If the CPU address is

between 00 000 000 and the system size boundary,

16-BIT MAPPING

an attempt is made to reference physical memory.

There is fixed mapping from virtual to

Memory addresses between the system size boundary

and

16 777

777 are

physical addresses. The lowest 28K vir-

known as Non-Existent

tual addresses are treated as correspond-

Memory (NEXM); any attempt to access these locations is aborted. If the address is in the top 128K,

ing to the same physical addresses. The
top 4K addresses cause Unibus cycles to

17 000 000 — 17 777 777, the lower 18 bits of the ad-

addresses 17 760 000 - 17 777 777. Refer

dress are placed on the Unibus.

to Figure 1-9. 16-bit mapping is enabled

after. Power Up, Console Start, or the
RESET instruction.

(\7) 777 777

PERIPHERAL
PAGE (4K)

| _ (17} 760 000

7) 757 777

18-BIT MAPPING

UNIBUS

32K

) REFERENCE
(128K)

are mapped

(17} 000 000

“\

for each

of the

into

128K

User)

of physical ad-

reference physical memory. The top 4K

NON -EXISTENT

addresses

MEMORY OR NXM

cause

Unibus

cycles

ad-

dresses 17 760 000 — 17 777 777. Refer to

Figure 1-10.

SYSTEM SIZE

BOUNDARY
MEMORY

22-BIT MAPPING

REFERENCE

00 000 000

This mode produces 22-bit addresses for

accessing
1-4002

all

of physical

memory.

The

top 128K addresses cause Unibus cycles

to addresses 17 000 000 - 17 777-777. Re-

Physical Address Space

fer to Figure 1-11.
2.

1.2.3

addresses

dress space. The lowest 124K addresses

6 777 777

Figure 1-8

virtual

three modes (Kernel, Supervisor,

Mapping

Unibus

addresses

per-

formed by the Unibus Map.

Mapping is the process of converting the virtual ad-

dress generated by the program to a physical mem-

UNIBUS MAP NOT ENABLED

ory address or to a Unibus address, or the process

When the Unibus Map is not enabled,

of converting a Unibus address to a physical mem-

Unibus addresses 000 000— 757 777 ac-

ory address.

cess memory locations 00 000 000
- 00

The virtual address is mapped by Memory Manage-

757 7717, i.e., they are not modified except for the insertion of leading zeroes.

ment: the Unibus address is mapped by the Unibus

Map.

Neither

these

increases

memory

access

time.

UNIBUS MAP ENABLED

When

the

Unibus

Map

enabled,

Unibus addresses 000 000 - 757 777 are
Memory Management and the Unibus Map are sep-

relocated and a Unibus device may ac-

arate units and one may be enabled independently

cess any location in physical memory.

FLOW

777777

T T T~~~

17777777
4K

17760000

17757777

UNIBUS

(18 BITS)

TT T T 17777777
PERIPHERAL PAGE
17600000

124K

000000

\
\

_ 117000000

UNIBUS
MAP

00757777

1920K

96K

VIRTUAL

00157777

28K

(16 BITS)
000000

177777

160000

6777777

00000000

INCOMING

| _

00000000

PHYSICAL

ADDRESS

ADDRESS SPACE

LOCATIONS

(22 BITS)

—————

=RELOCATION

— ————

=NO ADDRESS
RELOCATION

{MAX. AVAILABLE
MEMORY 1024K)

n-3196

Figure 1-9

16-Bit Mapping

FLOW

777777

T T T T

w7777

T T T T T T 7777777

PERIPHERAL PAGE

7760000
17757777

UNIBUS

(18 BITS)

000000

124K

T T

17600000

000000

UNIBUS

MAP\

177777

VIRTUAL

(16BITS)

00757777

124K

16777777

00757777

1920K

124K

— "MMEM .

000000
INCOMING
ADDRESS

Ll00000000
| A 00000000
PHYSICAL
ADDRESS
ADDRESS SPACE
LOCATIONS
(22 BITS)

(MAX. AVAILABLE
MEMORY 1024K)

———
= =RELOCATION

— ————& =NO ADDRESS
RELOCATION
1-3197

Figure 1-10

18-Bit Mapping

I-1-8

FLOW,

777777

7777777

17777777

PERIPHERAL PAGE

7760000

17757777

UNIBUS

(18 BITS)

17600000

124K

000000

A 17000000

\Y_

16777777

UNIBUS

16777777

MAP

\\,

1920K
ADDRESS
177777

MEM

/MGMT

\
00757777
124K

000000

Jlo0000000

INCOMING

| N 00000000

PHYSICAL

ADDRESS

ADDRESS SPACE

LOCATIONS

(22 BITS)

—————#

:RELOCATION

— ————

=NO ADDRESS
RELOCATION

(MAX. AVAILABLE
MEMORY 1024K)

n-3198

Figure 1-11

1.2.4

Parity

This

paragraph

parity

22-Bit Mapping

byte parity for data, and in addition it stores two
provides general

information

checking in the PDP-11/70 system.

parity bits for the address information (tag storage)

de-

associated with each two-word block of data.

tailed description of this subject is provided in Section VI of this manual (Cache) and in the Memory
Manual.

System Reliability

cPU

Parity is used extensively in the PDP-11/70 to en-

UNIBUS

sur¢ the integrity of the data and thus to enhance

the

reliability of the system.

All

memory (Cache

ADDRESS

and Main Memory) has byte parity. Parity is generated

and

checked

all

transfers between

Main

Memory and Cache, and between Cache and the

CPU.

is checked

between the high-speed mass

[ADDRESSIP) [CATAP)] | DATA (P)

storage devices and their controllers, and again between the controllers and core memory. A software

ADDRESS

routine can be used to log the occurrence of parity

CONTROL(P)

crrors, to handle recovery from errors, and to pro-

vide

information

system

reliability

and

performance.

HIGH
° SPEED | HiGH-seeeD
TRoL

CACHE

CONTROL

| 170 BUS

| pata & cONTROUP)

DATA(P)

DATA(P)
MAIN CONTROL
1-3199

Parity in the System
Main Memory stores one parity bit for each 8-bit
byte, (refer to Figure 1-12). The Cache also stores

Figure 1-12

Parity (P) in the

PDP-11/70 System

The bus between Main Memory and the Cache contains parity on the data lines and on the address
and control lines. The high-speed 1/O controllers
check and generate parity for data transfers to
Main Memory, and they have the capability of handling address errors that are flagged by the control
in the Cache memory. Refer to Section VI, Chapter
3 for a detailed description of the PDP-11/70 parity
system.

working, Memory Management can be used to map

around it. IT data found in the Cache does not have
correct parity, the memory system automatically
tries the copy in Main Memory, to allow program

execution to proceed. The correct data from Main
Memory automatically replaces the data in the
Cache which caused the parity error. Therefore,
if the error was caused by transitory conditions, it
will not occur again.

System Handling of Parity Errors

The design of the PDP-11/70 allows recovery from
parity crrors. It also allows operation in a degraded

mode if a section of the memory system is not operating properly. This type of operation is possible under program control by using the control registers.

I part or all of the Cache memory is malfunctioning, it is possible to bypass half or all of the Cache.
Misses can be forced within the Cache, such that
all read data is brought from Main Memory. Operation will be slower, but the system will yield correct results. If part of Main Memory is not

Aborts and Traps

One of two actions can take place after detection of
a parity error: (1) The cycle can be aborted. The
computer then transfers control through the vector
at location 114 to an error handling rou-

tine. (2) The instruction is completed, but then
the computer traps (also through location 114). In
the first case, it was not possible to complete the
cycle: in the second case it was, This second type of
parity error usually (but not always) causes the trap
before the next instruction is fetched.

I-1-10

CHAPTER 2
CONCEPTS

This chapter introduces several concepts that are
useful for the understanding of the KB11-C Processor and the PDP-11/70 system. The first two of
these concepts, Microprogramming (2.1) and Parallel Operation or Pipelining (2.2), should be well understood before reading any further. The other two
paragraphs, Virtual Machines (2.3) and Reentrant
and Recursive Programming (2.4), discuss system
concepts that may be easier to understand after a
working knowledge of the PDP-11/70 has been acquired. The block diagrams in Appendix A show
the interconnection between the several parts of the
PDP-11/70, including the RH70 controllers.
2.1

The KB11-C Processor uses a microprogram control section which reduces the amount of combinational logic in the processor. This paragraph
the concept

computer into various parts, and finally, describing
some

these

parts

differ

for

micro-

programmed processor.

Digital Computer Description
Although

The logical elements of a processor can only perform a small

number of operations at one time.

Therefore, to combine operations into an instruction, the instruction is divided into a series of operations

(or

performed

groups

operations

simultaneously).

The

that

can

processor

does

cach part of the series in order. One way to de-

scribe how the processor executes an instruction is

quence of machine states which the processor enters
in a specific order.

of microprogramming by

first describing a digital computer, then dividing the
how

plex operations.

to call each operation (or group of operations) a
machine state. An instruction then becomes a se-

MICROPROGRAMMING

introduces

be further combined into programs, which use the
combined instructions to construct even more com-

computer

can

effect

complicated

changes to the data it receives, it must do so by
combining a large number of simple changes in different ways. The part of the digital computer that

The processor can be completely described in terms
of machine states by listing all the machine states in
which the processor can perform (i.e., all the different operations or groups of operations that it can
perform) and all the sequences in which these machine states can occur. The sequence of machine
states is determined by the current state of the computer; this includes such information as the instruction being executed, the values of the data being operated on, and the results of previous instructions.

actually operates on the data is the processor. A

processor is made up of logical elements; some of
these clements can store data, others can do such

In terms of the machine state description, the pro-

simple operations as complementing a data oper-

cessor can be divided into two parts. The first part,

and,

called the data section, includes the logic elements
that perform the operations which make up a machine state. The second part, called the control sec-

combining two operands by addition or by

ANDing,

reading a

data operand

other

part

of the computer.

ations

can

such

a group

combined
is called an

from

some

These simple oper-

groups;

tion, includes all the logic that determines which

instruction, and it in-

operations are to be performed and what the next

into

functional

cludes operations that read data, operations that

machine state should be. The data section and con-

combine, change, or simply move the data, and op-

trol

crations that dispose of the data. Instructions can

paragraphs.

[-2-1

section

are

discussed

the

following

The data section in the KB11-C is usually referred
to as the Data Paths and is described in Section 11,
Chapter 2. The control section is described in Section II, Chapter 1, Instruction Decode and Micro-

The Control Section

The control section of a processor receives from the
data section, inputs which are used by the sensing
logic to help select the next machine state. The control

program Control.

section

also generates control

signals to

all

parts of the data section and communicates with
The Data Section

other parts of the computer system through control

During each machine state, the data section performs operations selected by signals from the control section. The data section provides inputs to the
control section which help to determine the next
machine state; the data section also exchanges data

signals. The following paragraphs describe the three
parts of the control section.
The Sequence Control Section

The primary control of the processor is the selec-

with other devices external to the processor.

tion of the sequence of machine states to be per-

The data section can be divided into three func-

section which selects the next machine state on the

tional sections; each section is discussed in one of

basis of:

formed.

This

done

the

sequence

control

the following paragraphs.
the current machine state
The Data Storage Section

For

the

processor

combine data

operands

inputs from the data section (such as the
instruction type or the data values)

must be able to store data internally, while simulta-

neously reading additional data. Often, a processor
3.

stores information about the instruction being exe-

information about external events.

cuted, about the program from which the instruction was taken, and about the location of the data

The sequence control section maintains information

being operated on, as well as a number of data op-

about the current machine state, and receives infor-

erands. When the processor must select some of the

mation from the data section and the external envi-

internally-stored data, or store new data, the con-

ronment through the sensing section.

trol section provides control signals which cause the
appropriate action within the data storage section.

The Function Generator

The Data Manipulation Section

erations selected by signals from the control section

This section includes the various logic elements that

of the processor. The function generator produces

In cach machine state, the data section performs op-

actually change data. Many of these elements are

these control signals on the basis of the current ma-

controlled

chine state and also on the basis of inputs from the

which

formed.
being

select

signals
the

from

particular

Data manipulation

transferred

between

the

control

operation

section,
be

sensing section, such as information on the instruc-

per-

tion type.

is performed on data
the

processor

and

the

The Sensing Logic

rest of the system, and on data that remains within

the processor. In some cases, the data that remains

In general, the sequence control section requires in

within

puts that select one of
a limited number of machine

the processor

used

to control the pro-

states to follow the current state.

cessor by providing inputs to the sensing section of

the processor control.

The Control Section in the KB11-C
The Data Routing Section

The

The interconnections between the logic elements in

program

the data storage section and the elements in the

buffer, and several logic elements that generate con-

function

generator

Read

Only

comprises

the

Memory (ROM),

micro-

its output

data manipulation section are not fixed; they are

trol

set up as required in each machine state. The con-

through the subsidiary ROMs). The sequence con-

signals

based

sensed

inputs

(notably

trol section generates signals that cause the logic ele-

trol

ments

ation logic. The sensing section includes the various

the

data

routing

section

form

the

comprises

the

microprogram

address

gener-

appropriate interconnections within the processor,

logical elements that receive inputs from the data

and between the data interface and the data storage

section, especially the condition-code generator, the

and manipulation sections.

subsidiary ROMs, and the branch logic.

I-2-2

Microprogramming

the

Control

Section

completely defined if its value is known for every

describes two methods of imple-

therefore be implemented as a storage device: the

menting the control section of a processor. The first

storage is divided into words, with each word con-

Implementation

machine state. The function generator section can

This paragraph

method, which is called the conventional method for

taining a bit for every control signal; there is one

the purposes of this discussion, uses combinational

word for each machine state. During each machine

networks, with many inputs combined in varying

state, the contents of the corresponding word in the

ways to produce each output. The second method,

storage

which is called microprogramming, replaces most of

lines.

the combinational

storage

networks with

an array struc-

ture. The array requires a small number (approx-

element

are

transmitted

the

control

For most control signals, the output of the
unit

the control

signal;

additional

logic is required.

imately 10) of inputs to select the output states for
a large number (approximately 100) of signals. Because the array is a regular structure, it is simpler

The two tasks of the sequence control section are

to construct and understand, and less expensive.

to select the next machine state, and to provide in-

formation about the current machine state to the
Conventional Implementation

function generator. The only information that the

In a conventional processor, each control signal is

function

the output of a combinational network that detects

cessor requires is which word to use as control sig-

all

generator

microprogrammed

pro-

the machine states (and other conditions) for
which the signal should be asserted. The machine

an address that selects the correct word. The se-

state is represented by the contents of a number of

quence control must also select the address of the

storage

next word to determine the machine state sequence.

clements

(such

flip-flops),

which

are

nals. Therefore, the seqence control simply provides

loaded from signals that are, in turn, the outputs of

Because

the

is determined

combinational

part by

the current machine state, information

networks. The inputs to these net-

machine state

works include:

stored in the microprogram that helps to select the

the current machine state

trol signal values and the address and sensing con-

senscd conditions within the Processor

address

next state; the microprogram word contains the con-

trol

information

required

generation

logic

the

microprogram

(i.e.,

the

sequence

control).
3.

sensed external conditions.

The number of logical elements in the processor is

In a microprogrammed control like the one described above, the two major portions of the con-

often reduced by sharing the outputs of networks
which generate intermediate signals needed in the
generation of several control signals, or even in the
generation

of control

signals and

trol section have been simplified to regular logical
structures. The function generator is entirely sepa-

machine states.

rate from the sequence control, so it is easy to isolate malfunctions to the microprogram storage or

Unfortunately, while this reduces the size of the processor, it increases the complexity and difficulty of
understanding the device because it is no longer ob-

to the address generator. In addition, the sensing
logic is simplified, because each sensed condition is

vious what conditions cause each signal.
ton,

In addithe distinction between the sequence control

reduced to a single signal and the sensing logic selects the appropriate signals for the current machine state, based on signals output from the

and the function generator is blurred, which makes
it more difficult to determine whether improper op-

microprogram

eration is caused by a bad machine state sequence
or, more simply, by the wrong control signals
within an otherwise correct machine state.

summarize

this

dis-

from stored information, and the selection of each
machine state, based on information stored in the

The microprogrammed implementation is based on

following observation.

structure, based on the generation of control signals

Microprogrammed Implementation
the

storage.

cussion, a microprogrammed processor has a simpler, more regular, more easily repaired control

current machine state, and on information from a

Each control signal is

simplified sensing section.

[-2-3

PARALLEL OPERATION (PIPELINING)

A second form of parallel operation occurs in the

In a digital computer system, the processor is usu-

KBI11-C to further improve the utilization of the

ally

processor.

2.2

the

fastest

part of the system.

order to

achieve the maximum speed of operation, all parts

Because the processor includes several

types of data storage and data manipulation ele-

of the processor should be used as much as pos-

ments, with different interconnections, several data

sible. To prevent the processor from wasting time

transfers can take place within the processor simul-

waiting for other parts of the system, the processor

taneously. As an example, during the same machine

must make use of the external data transfer inter-

state that completes an external data transfer, the

face as much as possible. Because any one oper-

processor can read a general register into a tempo-

ation that the processor performs uses only part of

rary storage register, and perform an addition that

the processor’s available resources, the two consid-

adds a constant to the program counter.

erations above require the processor to perform sev-

eral operations in parallel.

The use of parallel operations within an instruction

In general, the sequence of operations required for

fore the total time) required to execute each instruc-

each instruction uses various parts of the processor

tion:

of the processor,

number of machine states required to execute a pro-

such as the program counter, are used only during

gram by effectively eliminating the elapsed time be-

the early parts of the instruction; others, like the

tween many external data transfers.

reduces the number of machine states (and there-

different

times.

Some parts

the

use

pipelining

further

reduces

the

shift counter, are used only during later parts of the
instruction. The processor can be fully utilized only
il different parts of the processor can be used for

2.3

parts of different instructions during the same ma-

The processor executes instructions and operates on

chine state.

VIRTUAL MACHINES

data, both of which are stored in memory, and it responds to various asynchronous events.

When the processor works on the early part of an

instruction at the same time that it completes the

The response to an interrupt or trap is not entirely

previous instruction, this form of parallel operation

designed into the processor. Instead, the response is

is called pipelining. The processor attempts to make

controlled by a series of instructions (a program)

continuous
fetching

use of the external

each

word addressed

data

interface by

the

which

Program

is selected by a simpler hardware response

when the asynchronous event is detected. Often, a

Counter (PC) in succession (incrementing the PC

number of programs are required to respond to a

during each transfer), on the assumption that the

number of events, and the scheduling, coordination,

next word required will be the one following the

and

interaction

current instruction.

most

important (and difficult) parts of program-

In the pipelining analogy, the

processor attempts to fill a pipe, corresponding to

the different
sively

parts of the processor used

each

instruction,

with

of these programs is one of the

ming a computer system.

succes-

series

In many applications, the user programs that are

instructions.

written for the system are treated as though they

The current instruction often requires some other

simplify the scheduling, to allow each user program

words from the external storage. At times, the next

to operate with a terminal (some form of character

are interrupt response programs. This is done to

instruction does not follow the current instruction

1/O device), and to allow several user programs to

because the PC has been explicitly changed by the

operate at

current instruction. When either of these two condi-

once, the processor can be utilized more fully than

once.

running several programs at

tions occurs, the processor must stop the data trans-

is generally possible with only one user program,

fer begun after the instruction fetch and begin a

which would often be waiting while devices other

data transfer with a different address. In the pipe-

than

line analogy, this is a break in the smooth flow of

ations. With several programs to be run, the pro-

instructions through the pipe; some time is lost before the pipe drains (the current instruction is com-

cessor can be switched among the programs so that

pleted)

while others are waiting. The use of the processor

and

can

refilled

new

the processor completed data transfer oper-

those ready to run have the use of the processor

instruction

fetched and a transfer begun to read the word fol-

for

lowing that instruction).

multiprogramming.

[-2-4

several

programs

the

same

time is called

Running programs in a multiprogrammed system

Mapping

presents several difficulties. Each program can be

Each

run at arbitrary times, but all the programs must be

programming system is running several programs in

time

program

run

(or,

if the

multi-

capable of running together, without conflict. A fail-

a round-robin

ure in one program must not be allowed to affect

sumes operation), it has some of the system dar-

manner, each

time a program

re-

other programs. Each program must be able to use

dware allocated to it. This generally includes some

all features of the system in a simple, easily-learned

part of the memory to contain the instructions and

manner, preferably in such a way that the program

data required by the program, some of the pro-

does not need to be modified to run in a different

cessor’s registers, a hardware stack (which is ac-

hardware configuration.

tually an area in the memory and a pointer to that

area in

a processor register),

possibly some per-

These difficulties are overcome by providing each

ipheral devices, and perhaps a fixed amount of the

program with a virtual machine. The programmer

processor’s time. All of thse allocations must be

writes his program as though it is to run by itself;

made in such a way that the hardware machine can

the

then execute the user program with a minimum of

memory or peripheral devices), and the system pro-

extra operations; i.e., so that the execution of the

program

uses any system

resources (such

vides the services necessary to support the program

user program requires as few additional memory cy-

and coordinate it with other programs in operation.

cles,

The physical hardware in the system is combined

Therefore,

with a control, or executive program, to simulate a

hardware machine; registers in the hardware con-

this

tain all the allocation (mapping) information, and

more powerful, but abstract, machine that the pro-

all references to virtual addresses, virtual stack loca-

powerful

hardware

machine;

for

tions,

grams are written.

additional

machine

the allocation

virtual

cycles,

possible.

done entirely

or virtual

the

devices

converted by hardware to physical references.
Based

this discussion,

the

hardware machine

and the executive program must combine to fulfill

In a PDP-11/70 System, mapping is done by two

the following four major objectives of the virtual

devices. The mapping of virtual registers into pro-

machine:

cessor registers, of the virtual stack, and of the virtual

program

counter,

done

the

Mapping - The virtual machine of the

appropriate values into the processor registers; one

program currently in operation must be

of two sets of general registers can be selected for

assigned to some part of the hardware

the user,

machine.

pointer for user mode, while the program counter is

and the processor has a separate stack

changed by interrupt and trap operations and by
Resource management — The scheduling

the Return

of programs, and the allocation of parts

Trap (RTT) instructions.

from Interrupt (RTI) or Return from

of the hardware machine, must be performed by the executive program.

The remaining mapping functions distribute the virtual memory into the physical memory. In the phys-

Communication - The virtual

machine

ical memory, many specific addresses are reserved

must be able to request services from the

for special functions; the lowest addresses are used

executive program, and the executive pro-

for interrupt and trap vectors, while the highest ad-

gram must be able to transfer data back

dresses

and forth with the user programs.

functions

are

used

that

for

device registers.

require

reserved

Because all

addresses

the

physical memory are performed either by the physProtection - The system that supports

ical machine or by the control program, these ad-

the virtual machine, and all other virtual

dresses need not be reserved in the virtual machine.

machines, must be protected from fail-

Therefore, the programs written to be run in the vir-

ures in any one virtual machine.

tual

machine can

use any addresses;

specifically,

these programs can start at address 000000 and conEach of these subjects is discussed in one of the fol-

tinue through ascending addresses to the highest ad-

lowing paragraphs,

dress needed.

I-2-5

In discussions of the virtual memory and the phys-

Processor Management

ical memory, it is often necessary to describe the ad-

The processor can only execute one instruction at a

the

time. When several programs are sharing the use of

memory. The range of addresses that it is possible

the processor, the processor operates on each pro-

to use is called the address space. The maximum

gram in turn; either the processor is shared among

range of addresses that can be used in the virtual

the programs, by using periodic interrupts to allow

machine (which in the PDP-11/70 is the maximum

the executive program to transfer the processor to
another user program, or each user program runs

dresses

used

select

data

items

within

number that can be contained in a 16-bit word) is
called the virtual address space, while the maximum

to completion before the next user program begins.

range of physical addresses that can exist in the

To share the processor on a time basis, the execu-

hardware

tive program must perform the transfer from one

system

called

the

physical

address

space (in the PDP-11/70 this can be all the ad-

virtual machine to another. Each virtual machine is

dresses expressed by a 22-bit number).

given control of the physical machine by loading
the map of that virtual machine into the physical
machine. That is, the executive program changes vir-

If the user program is to use addresses in the vir-

tual address space that are reserved in the physical

tual machines by changing the contents of the pro-

address space, the virtual address space must be

cessor registers used by the virtual machine, and by

relocated to some other part of the physical address

changing the contents of the registers in Memory

space. In a multiprogramming system, several user

Management which map the virtual address space.

programs, each in its own virtual address space,
may be sharing the physical address space. There-

Memory Management

fore, the relocation of the virtual address space into

the physical.address space must be variable; each

The following discussion assumes that Memory
Management is enabled. Memory Management is

time a program is run, it may be allocated a differ-

much more complicated than Processor Manage-

ent

ment. If a program uses a large proportion of the
virtual address space, and only a small amount of
memory is physically available in the system, the
program may be too large to fit into the memory
all at once. Fortunately, in most programs only a
small part of the program (or possibly several small

part

of the physical

address space.

Memory

Management provides the capability of varying the
relocation for each user program by storing a map
of the memory allocation in a set of registers.

parts, one for the instruction stream and one or

Resource Management

In a multiprogramming system, each user program

more for blocks of data) is used at any one time.

operates in a virtual machine that can utilize any of

To take advantage of this fact, the virtual address

the possible devices or functions of the physical ma-

space is divided into pages so that each page can be

chine, as well as many functions performed by the

mapped separately. Only the pages that are in use

executive program. The resources that exist in the

in the current instruction are required to be in the

system must be allocated to each user program as

physical

required,

instruction,.

but

without

allowing

conflicts to

arise

where several

user programs require the same re-

sources.

The

physical

program

must

machine and

memory

during

the

execution

of that

A system which uses Memory Management to per-

the executive

resolve any protective conflicts by

mit cach virtual machine to have a larger address

scheduling the resources for use by different pro-

space than the available physical memory must also

grams

must schedule the

include a mass storage device to hold those parts of

user programs to operate when the resources are

different

times,

and

cach virtual memory that are not in the physical
memory.

available.

program

proceeds

through

se-

quence of instructions, it requires different pages of
The management of input/output or peripheral de-

the virtual memory. The memory map in the Mem-

vices is beyond the scope of this discussion, which

ory

is primarily concerned

the basic PDP-11/70

for cach page of the virtual address space, and also

System. Within the system, the two most important

includes information specifying which pages are cur-

with

Management

includes

relocation

information

resources which require the most care and effort to

rently in the physical memory. If the processor at-

control are the memory and the processor.

tempts to perform transfers with a virtual address

I-2-6

which is on a non-resident page, the instruction is

user programs with virtual machines of great power

aborted.

and flexibility, with a minimum burden on the user

part of the executive program which

transfers the required page into the physical mem-

program,

ory and changes the map in Memory Management
to reflect the newly available page is then executed.
Communication
Memory Use Statistics

A program running in a virtual machine must be

If it is necessary for the executive program to bring
a

page into the physical

physical

memory, but all of the

memory is already in

able to communicate with the executive program,
to request various services performed by the execu-

use, the executive

tive program, or to determine the status of the sys-

program must remove another page (from the same

tem. The same type of communication can be used

virtual machine or, in a multiprogramming system,

for communication

from some other virtual machine) from the physical

providing inter-machine communication as a service

between

virtual

machines,

memory. When a page is removed from the phys-

through the executive program. The same hardware

ical memory, a copy of that page must be stored in

functions that provide a means for the user pro-

the mass storage device; if a copy of the page is al-

gram to communicate to the executive program are

ready on the mass storage device, and none of the

also used

data (or instructions) stored on the page have been

the status of the user program when a trap or abort

changed, the writing of the page onto the mass stor-

condition occurs.

by the executive program to determine

age device can be bypassed. Each time a page must
be replaced, the executive program attempts to pre-

The

dict which page is least likely to be used in the fu-

trap instructions (such as EMT, TRAP, or 10T).
Abnormal conditions caused by a program failure,

ture,

so that 1t will

not soon

need to be moved

back into the physical memory.

user

program

requests services by executing

such as an odd address for a word data transfer, or
an attempt to execute a reserved instruction, cause

Mcmory Management includes hardware to permit

internal

choosing the page to be replaced and to determine

function performed by the processor serves to no-

whether that page must be written onto the mass

tify

storage

device.

Each

required.

formed

processor

the

external

data

requires

transfer

that

per-

processor

the executive

traps.

In either case,

program

that an

the trap

instruction

Memory

Management convert a virtual address into a phys-

ical address and keep track of which virtual pages
have been accessed and which virtual pages have
been written into. The executive program operates

Context Switching
The executive program must then begin executing
instructions to perform the requested service or to

on the assumption that pages which have been recently accessed will also be used soon. To find a

correct the failure condition, if possible. However,

page which can be replaced, the executive program

any program other than the user program, the map-

looks for a page which has not been used, prefera-

ping information must be changed to reflect the al-

bly from the address space of a user other than the

locations used by the new program.

in order for the hardware machine to operate on

current user. If there are no virtual pages currently

the

physical

memory

that

have

not

been

ac-

The trapping function performs the change of most

cessed, the executive program looks for a page that

of the mapping information. The contents of the

has not been written into, to avoid having to copy

Program

a page to the mass storage device. If all the virtual

(PS) registers are changed directly; the old contents

Counter

(PC)

and

the

Processor

Status

pages in the physical memory belong to the current

are stored on a stack in memory, pointed to by a

user, the executive program

stack

has

not

been

used

looks for a page that

pointer,

and

the new contents are supplied

recently, again preferably one

from locations called a trap vector. The address of

that has not been written into. By use of the hard-

the trap vector is provided by the processor and de-

ware Memory Management unit and of
a variety of

pends on the type of trap instruction or trap condi-

scheduling and allocation algorithms in the executive program, the system can provide a number of

tion, so that for each trap instruction or condition,

a different PC and PS can be supplied.

1-2-7

Inter-Program Data Transfers
When the new virtual machine begins executing a
service program for the programmed request (if a

Memory Management stores the maps for the executive program and one user program in separate
registers. The processor indicates which map should
be used to relocate virtual addresses. During the execution of instructions (as opposed to the interrupt
and trap service function), the address space map
to use is specified by bits 15 and 14 of the PS.
These bits also specify which Stack Pointer (SP) register in the processor to use (there is a separate SP
for each virtual machine). Because the trap and interrupt service function loads the PS register with a
new value, this function changes almost the entire

trap instruction was executed) or abnormal condition (if a trap condition occurred), the service program must get information from the previous
virtual machine. This information may define the
status of the previous virtual machine, after an abnormal condition occurred, so that the service program can correct the condition and restore the
correct status before returning control to the previous virtual machine. If the service program is performing a service, the information required from
the calling program may define the specific type of

virtual machine context directly.

The only remaining parts of the virtual machine

service to perform, or provide the addresses of data
buffers, or specify device and file names.

context that require changes are the general registers in the processor. These can be changed either
by saving the contents of the registers from the pre-

vious virtual machine on the hardware stack and
loading new contents, or by selecting the alternate
set of general registers (the processor has two sets
of general registers, 0 — 5). Register set selection is controlled by bit 11 of the PS register, so this
method can be used in conjunction with the trap

Most information required by the service program
is stored in the calling program’s address space. To
get this information, and to return information to
the calling program, the service program must be
able to operate in the present address space and
transfer data in the previous address space, at the
same time. The KB11-C Processor provides instruc-

service function.

tions to do this.

To summarize the change of virtual machines: the

The special instructions that transfer data between
virtual address space make use of the PS register to
specify which address space is being used by the current virtual machine, and which address space was
used by the previous machine (this is identified by
bits 13 and 12 of the PS). The data is transferred between the hardware stack of the current address
space and arbitrary addresses of the previous address space. The calculations of the virtual address

mapping in the hardware system includes the selection of a register set, a stack pointer, a program address (in the program counter), an address space,
and a processor status. The trap and interrupt service function, which is performed by the processor
as an automatic response to trap an instruction or
abnormal condition, can change all of these selections as follows:

in the previous address space; i.e., any index con-

The

Bits 15 and 14 of the new PS select the
new address space and stack pointer.

program counter and
status are changed directly.

stants or absolute addresses used to generate the virtual address, are taken from the current address

processor

space, just as the instructions are.
Each virtual address space is divided into an In-

struction (I) space and a Data (D) space. Each I or
D space has a full set of 2'¢ virtual addresses. There-

Bit I1 of the new PS selects the new reg-

fore, the communication instructions are available
in two versions; one to transfer with the previous |

ister set.

The mapping and selection information for the previous virtual machine is completely saved, either by

space,

and

one to transfer with

the previous

remaining in unselected portions of the processor
and the Memory Management unit, or by being
stored on the hardware stack. If the selected register set is shared with other virtual machines, the register contents must be changed by an instruction

transfer direction as well, so there are four commu-

space. A different instruction is needed for each
nication instructions: Move To Previous Instruction
(MTPI) space,

space,

Move

space,

and

space.

sequence.

I-2-8

Move To Previous Data (MTPD)

From

Move

From

Instruction

Data

(MFPI)
(MFPD)

Returning to the Previous Context

Because all the mapping and context information
for the previous virtual machine is saved when the
trap and interrupt service function sets up a new virtual machine, the hardware system can resume the
execution of any program at the same point that it
was interrupted. This is done with a Return from
Interrupt (RTI) or Return from Trap (RTT) instruction, which replaces the PC and PS values of the
current virtual machine with the stored values from
the previous virtual machine.

The PS selects most of the mapping information, as
described previously, so the return instructions completely restore the previous context.
Protection

The hardware system and the executive program
must be protected from failures in each virtual machine. In addition, most systems provide protection
so that no program operating in a virtual machine
can take control of the system or affect the operation of the system without authorization. A third
form of protection that is useful in a large and complex system is the protection of the executive program against itself. The executive program is
divided into a basic, carefully written Kernel, which
is allowed to perform any operation, and a broader
Supervisor, which cannot perform privileged operations, but which provides various services useful to
the executive program and to the user programs.

The forms of protection provided include the different address spaces for different types of programs,
a varicty of restricted access modes, and restricted
processor operations. The address space protection
can be used with any type of program, whether opcrating in User, Kernel, or Supervisor mode. The restricted processor operations are usable only in
Kernel mode: Supervisor mode has the same restrictions as User mode.

Separate Address Spaces

The most basic protection against modification of
the exccutive program by a User program (or of
the Kernel section by the Supervisor section) is the
separation of the address spaces. A program oper-

ating in User mode operates in the User address
space. It cannot access any physical addresses that

are not in that address space, regardless oftheir correspondence to addresses in any other virtual ad-

dress space. The executive (Kernel) program can
prevent a User program from accessing other virtual address spaces through the communication instructions (MTPI, MTPD, MFPI, MFPD) by
forcing bits 13 and 12 of the stored processor status
word to 1s (to reflect User mode) before executing
an RTI or RTT instruction to return control to the
user program. This forces the previous mode bits in
the PS register to take on User mode, just as the
current mode bits are set to User mode, and the
communication instructions operate only within the
User address space .
Access Modes

Within one address space, it is often useful to be
able to protect certain parts of a program from unintentional modification. This can be done by allowing the data in those addresses to be read, but
prohibiting transfers into the addresses. This is

known as read-only (or write-protected) access.
Arcas in a virtual address space that contain alterable data must permit read/write access, but areas
that contain unmodified instructions may be readonly.

Another useful form of access protection distinguishes between read accesses that fetch instructions (or address constants) and any accesses that
transfer data. If instructions can be accessed by the
processor only as instructions, they can be executed
but they cannot be read or transferred to any other
part of the address space. This prevents the user
from determining what the instructions are in order

to tamper with the instruction sequence or attempt
to modify the program in undesirable ways. This
type ol access restriction is called execute-only
ACCess.

Mecmory Management provides a read/write, readonly, and execute-only access modes system. The access mode is stored in the mapping registers along
with the relocation information; in fact, when a
page of the virtual address space is not in memory,
a special access code that identifies the page as
non-resident is used. The execute-only access mode
is not a scparate access mode, but is provided by
scparating the address space into two address

[-2-9

spaces that are used for the different kinds of trans-

fers. One address space is used for all transfers that
fetch

instructions and is called the Instruction (1)

space, while a second address space is used for all

the program

should be able to transfer the pro-

cessor o the instructions following the calling in-

struction.

routine

which

called

from

other

routines is said to be subordinate to those routines

data transfers and is called the Data (D) space. If

and

the two address spaces are mapped separately, at-

that transfer the processor to the beginning of a

tempts to use the same address for an instruction

and

for data may address different physical locations. If no addresses in the D space correspond to

is called a subroutine; the special instructions

subroutine and that return the processor to the call-

ing

routine

are

called

subroutine

linkage

instructions.

the physical addresses used in the I space, the instructions cannot be accessed as data and an execute-only access mode has been achieved. This
mode must be used with caution: tables that are ac-

cessed

indexed

address

modes

must

be in

space and MARK instructions, which are stored on

he hardware stack as data and then executed, and
require the stack to be in the same virtual addresses
in I and D space.

PDP-11

subroutine that either performs a part of the procedure and then calls itself to perform the rest of
the procedure, or completes a computation and returns a partial (and finally, a complete) result. This

is called recursive operation. The common example

of a recursive procedure is one that calculates the
factorial of a number (the factorial is the product
resulting from the multiplication ofa number, n, by
all smaller numbers). The recursive procedure to cal-

Privileged Instructions

Certain

Recursive Functions
Some procedures are most easily implemented as a

instructions that affect the oper-

culate a factorial of a positive integer is as follows:

ation of the hardware machine must be prohibited

in the virtual machine. These include the HALT instruction,

which

stops

the

physical

machine

and

thus prevents any virtual machine from operation,
the RESET instruction, which stops all in-

put/output devices, regardless of which virtual ma-

trol the entire hardware system; they are ineffective

in the Supervisor or User mode. The RESET and
Set Priority Level (SPL) instructions are allowed to
exccute

in these modes, but have no effect; the
HALT instruction activates a trap function so that

the executive program may stop all action for the
virtual machine that executed the HALT, but not
for other virtual machines.

2.4

REENTRANT

Il n is greater than I, compute the facto-

rial of n minus I, multiply that number
times n, and return that value.

chine they are allocated to, and various PS change

instructions. These instructions are allowed only in
Kernel mode so that the executive program can con-

Ifnis 1 or0, return 1 as the value of fac-

torial n.

For example, to compute the value of factorial 3,
the procedure is to compute the value of factorial 2
and multiply by 3. However, the value of factorial

2 1s the value of factorial

1 times 2. The value of
lactorial 1 is found by Step 1. to be I, so the final

result is 1

times 2, multiplied by 3, or 6. The same

recursion computes the factorial of any positive integer, in n recursions for a number n.

Use of a Stack in Recursive Routines
When a subroutine is called recursively, the linkage
AND

RECURSIVE

PROGRAMMING
A program can generally be divided into routines,

cach of which performs a function that is built up
from a sequence of instructions. Often, the function
performed by a routine is needed in several other
routines, so it is desirable to be able to call the routine from many other routines in the program; i.e.,

I-2-10

information for each call (the information required
to return to the calling program) must be saved during subsequent calls. Since a recursive subroutine
can be called again before it returns from the first
call, the linkage information should not be stored
in a fixed location; instead, it is stored in a stack,
cach linkage in a different location and a

with

pointer that identifies the specific location for each

linkage.

physical memory, and to map each virtual address

which then calls subroutine C. Subroutine C must

space into the same physical address space. How-

return control to subroutine B before subroutine B

cver, in a muliprogramming system, one virtual ma-

can return control to subroutine A. It can be seen

chine may begin execution of a program and then

Assume

that

subroutine

calls

subroutine

that in this case the last linkage which has not been

be interrupted: a second virtual machine may begin

used for a return must be the first one used; i.e.,

execution of the same virtual program and then run

the linkages must be used in a last-in, first-out se-

out of time: the original virtual machine may re-

quence. A storage area whose locations are used for

sume execution and complete the program; and the

last-in, first-out storage is called a stack; a pointer

second virtual machine may resume executions. The

used to point to the last entry placed on the

programmer cannot make any assumptions about

stack, and the subroutine linkage instructions that

where cach virtual machine may resume execution,

put information on the stack (a push operation), or

nor

remove information from the stack (a pop oper-

cach virtual machine stops, so the program must be

can

make

any

ation), change the contents of the pointer so that it

capable of being reentered at any time, regardless

always points to the correct word for the next link-

of what other virtual machines have done with the

age operation,

program,

store

all

about

their

data

where

One of the KB11-C processor’s general registers is

Programs

used

stack, so that each virtual machine that uses the

stack

pointer.

the subroutine linkage instructions as a

designed

assumptions

Stack

program simply uses a different stack, are called re-

Pointer (SP) and it must be initialized to point to

entrant programs. A different stack pointer is se-

This

the

Kernel

the first word in a stack area. This same stack is

lected

also used for storage of context or linkage informa-

selected. If the executive program changes the con-

tion

text of the user virtual machine, to run a different

which

the

trap

and

described

interrupt
Section

service

function,

each

time

different

virtual

machine

II, Chapter 6. The

user, it changes the address mapping of the stack

traps, interrupts, and subroutine calls are all han-

arca and the contents of the stack pointer, so that

dled in the same last-in, first-out manner.

cach activation of a program executes the program

A subroutine that can be called recursively should

other virtual machines.

complete

isolation

from

other

activations

not move data into fixed locations, because later exccutions of the same subroutine (before the current

exccution

Indexed Addressing of Parameters

finished) may also execute the same

When a program or routine calls a subroutine, the

data transfer instructions. The best way to keep the

calling

data storage for each execution of a subroutine sep-

The amount of the data to be “passed” to the sub-

routine

may send data to

the subroutine.

arate is to store the data on the stack in the same

routine may vary, as may the amount of data re-

manner as the linkage information.

turned by the subroutine. By placing all the data on

the stack, the amount of data becomes unimportant. The subroutine may read different data items

Reentrant Functions
Keeping the data

gram

storage separate from

is particularly

the pro-

on the stack by using the indexed addressing modes

important for programs and

with the stack pointer as the base register. Complex

subroutines that can be called from more than one

subroutines may require that the last word placed

virtual machine. If several virtual machines are exec-

on the stack (the word with the lowest virtual ad-

uting the same program, it can be called from more

dress, because the stack expands toward low ad-

than

dresses) contain the number of parameters passed

one

virtual

machine.

[If several

virtual

ma-

chines are executing the same program, it is desir-

so that the program does not use other data also

able to have only one copy of the program in the

on the stack but not intended as parameters.

[-2-11

Separate Stack and Index Pointers

index pointer while the stack is used for data stor-

Using the stack pointer as the base address for in-

age

dexed

addressing

presents

sub-

JSR instruction does not destroy the previous con-

routine

must,

turn,

another

tents of register 5 when it stores the return address

problems

pass

data

if the

during

the execution

of the subroutine.

The

subroutine. Each time the first subroutine calculates

in that register: the previous contents are pushed on

the stack, and are automatically restored by a Re-

parameter

for the second subroutine, it pushes

the parameter onto the stack. The address in the

turn from Subroutine (RTS) instruction.

stack pointer changes to reflect the new data on the
stack. As a result, all instructions in the first sub-

When

routine which contain index constants are invalid,

Counter (PC) value stored by the JSR instruction,

the

RTS

instruction

restores

the

Program

because the base value that the index constants are

the calling program must have some means of by-

supposed to modify has changed. It would be very

passing the stored data to get to the next instruc-

difficult,

tion.

if not impossible, to write a subroutine
that could use different index constants as the stack

The

word

immediately following the calling

instruction must contain the number of words occu-

pointer changes (because to remain reentrant, the

pied by the parameters. Both of these requirements

program cannot change any part of the instruction

can be fulfilled by placing a branch instruction in

code).

the return location; the branch instruction advances

A much simpler solution is to separate the
base register from the stack pointer by copying the

the PC so that the first word after the line parame-

stack pointer value into another general register before using the stack for any other data. This is still

of the branch instruction, contain the number of

reentrant

words used for the parameters (the offset is multi-

because

any

change

of virtual

machine

also changes the contents of (or the selection of) all

ters, and the offset in the eight least-significant bits

plied by 2, before use, to generate a byte address).

general registers.

The calling sequence and in-line parameter strucThe

used

as a separate index

ture used by non-reentrant routines permits the sub-

pointer is register 5. The standard method of call-

routine to return control to the calling routine with

ing subroutines in reentrant programs uses register

an RTS RS instruction. For compatibility, the reen-

stack

trant

subroutine

a word on the stack (at the address

RTS

the

index

pointer, and

contained

pointer,

the

call

must

also

permit

the

same

instruction to perform the return.

How-

in the index pointer) that indicates the

cver, when a subroutine has been called in a reen-

number of parameters on the stack. In addition to
providing a straightforward and completely reen-

hardware stuck, not to the calling program. In addi-

trant

tion, the space in the stack area used by the sub-

structure,

patible

with

this

method

similar

form

completely

com-

non-reentrant

subroutine call. The same subroutine can be called

both

reentrant programs and by simpler pro-

trant

manner,

routine

call

must

points

released

location

(the

stack

the

pointer

must be adjusted to point to the first location after

the parameter area) so that any additional informa-

grams that are non-reentrant.

tion on the stack (such as a return linkage to a rou-

Subroutine Call Compatibility

subroutine) is accessible. Thus, the word pointed to

tine that called the routine that called the current
In a non-reentrant program, the parameters passed

by RS should contain an instruction, whose least-

to a subroutine are placed in-line; i.e., they are in

significant

bits

the addresses immediately following the address of
the calling instruction. The subroutine call and re-

passed

the

stack pointer and also complete the subroutine re-

turn instructions use a register to store the program

turn sequence.

arc

the

subroutine,

number
which

of parameters
can

adjust

the

counter value for the calling program; the value in
the program counter at the time the subroutine call
(ump to subroutine or JSR) instruction is executed

The

is the address of the word following the JSR instruc-

the PDP-11/70. A detailed description of the use of

tion. The standard register specified in the JSR instructions is register 5; register 5 can be used as an

I-2-12

MARK

instruction performs this function in

this instruction is contained in the PDP-11/70 Pro-

cessor

Handbook.

SECTION II
PROCESSOR

Unless otherwise indicated, references within this section pertain to this section only.

SECTION II

PROCESSOR

CONTENTS
Page

INTRODUCTION
CHAPTER 1

INSTRUCTION DECODE AND MICROPROGRAM CONTROL

1.1

MICROPROGRAM ROM AND BUFFERREGISTER

1.2

FLOWDIAGRAMS

. .. ... .............

. . . .

1.2.1

ROMTiming

. . . . . . . . o

1.2.2

Glossary

123

Instruction Classes

. . . . .

e e

. . . . . . . . . . . . i

e e

e e e e
e

1I-1-7

II-1-10

124

Addressing Modes and Operand Fetch

. . . . . .. ... ... ..........

II-1-12

1.24.1

General Register Addressing

. . . ... ... ... .............

II-1-13

1.24.2

Program Counter Addressing

. . . . .. ... ... ... ..........

II-1-14

1.24.3

Aand CForks: OperandFetch

1.2.5

Flowchart Description

1.2.5.1

FLOWS 1

. .

. ... ... ... .............

. . . . .. .. ... ... .. ... ...

e e

...

e e e e

II-1-15

...

II-1-15

1.2.5.2

FLOWS 2

. e
e e e

II-1-18

12.5.3

FLOWS 3

. . ..
e e e e

II-1-19

1254

FLOWS 4

. . . e
e

II-1-20

1.2.5.5

FLOWS 5

. . .. e
e
e
e

I1-1-21

1256

FLOWS 6

. . . .

1I-1-21

1.2.5.7

FLOWS 7

. . e
e e e e e e e e e

11-1-22

1.2.5.8

FLOWS 8

. . . e
e
e

I1-1-23

1.2.59

FLOWS9and 10

12.5.10

FLOWS 11

1.2.5.11

FLOWS 12and 13

1.2.5.12

FLOWS 14

12.6

1.2.6.2

ROM ADDRESS

e e e e e e

e e

ittt e

II-1-30
II-1-31

. . . . ... ... ... .. ..

. . ... ... .. .. ... ... ... ...
. . . . .. ... ...

. . . . . .

e e

ROM Address Register (RAR)

14.2

ROM Address Selection

143

Branchesand Forks

144

Branch Logic

14.5

Instruction Registers

14.6

AForkLogic

e e e

II-1-31

L.,

II-1-35

. . . . . . ... ... . ...

. . . . . . . . ..

i it ittt e
e

14.6.1

Decode Logic

14.6.2

Address Bit Generation

1I-1-39

e e

I1-1-40

. . . . . . . . . i it i it
. . . . . ... ...

1.4.6.3

Instructions Other ThanBranch

1464

Branch Instructions

e e

e e e

CForkLogic

... ... ... ..

148

BForkLogic

. . .. . .. . . @

. . . . . .ot

I1-1-42
11-142

I1-1-40
I1-142

. . . . ... ... ... ... .......
i

II-1-39

Lo e

. . . . . .. ... ... ...

1.4.7

II-1-38

. . . . . . . . . . . . .. . . .. e

. . .. ... . ..

11-1-37
I1-1-37

. . . . . ... . ... . ... . ... .

. . . . . . . . . .

II-1-31

.....

. . .
e e
e e
e

CONDITION CODES

II-1-25

II-1-29

14.1

1.5

. . . . . . . .. . . .

An Instruction Example
ROMMAP

. . . . . . e

Figuresand Tables

1.3

e e e

. . . . . . . . . . . . e

. . .

Following an Instruction Through the Flowcharts

1.2.6.1

e e

.
e et
e e

11-142

I1-1-47
II-1-50

I1-1-51

e e e e e e e e e e it e e e

I1-1-53

. . . . . . . . . .. . . . it

II-1-53

1.5.1

Condition Code Storage

1.5.2

Condition Code Load Field

1.5.3

Instruction Dependent Control

. . . . . ... ... ... ... ...

...,

I1-1-54

154

SUBROM Address Generation

. . . . . . . . v v v v v v v v v e e e e e

e e

1I-1-54

. ... ... ... ... ... ... . ... .....

I1-ii

I1-1-54

SECTION II

PROCESSOR
CONTENTS (Cont)
Page

1.5.5

156
1.5.7

1.58

CHAPTER 2

CBitData
NBitData
ZBitData
VBitData

e e e e e e e e e e e e e e e e e e e e e e
e
. . . . ot o i
. . . . o o e e e e e e e e e e e e e e e e e e e e e e e e e e
e
e e
e e e e e e e e e e e e e e e e e
. . . .
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
o
.
.
.
.
.

II-1-55
II-1-55
I1-1-58
II-1-60

DATA PATHS

234

e e e e e e e e e e e e 11-2-3
. . . . . o
DATA MANIPULATION
Arithmetic and Logic Unit (ALU) . . .. . ... ... .. ... 11-2-3
.o e I1-2-3
Description of ALU . . . . . ...
e e e e 11-2-4
ALUCONIIOl . . o o o e e e e e e e e e e e e e e e
e e e 11-2-6
Shifter (SHFR) . . . . . . . o ot
Description of SHFR . . . . . . .. ... oo 11-2-6
Shifter Control . . . .« v v v v i e e e e e e e e e e e e e e e 11-2-7
. . .. ... .. ... oL 11-2-7
Program Counter (PCAandPCB)
General Registers . . . . . . . . . . o i i i it e 11-2-7
Source and Destination Multiplexers (SRMX and DRMX) . .. .. ... ... .. II-2-10
1I-2-11
Source Register (SR) . . . . . . . .. .
I1-2-11
o
0
.
.
.
.
.
.
.
.
Destination Register (DR) . .
I1-2-12
e
e
e
e
e
i
v
v
¢
.
Shift Counter (SC) . . . .
11-2-13
e
e
.
.
.
. . .
ALUInputs
11-2-13
e
..
.
.
.
.
.
(AMX)
Multiplexer
A
B Multiplexer (BMX) . . . .. . . o o 11-2-13
Constant Multiplexer 0(KOMX) . . . .. . .. ... ... ... ... 11-2-14
Constant Multiplexer 1 (KIMX) . . . ... ... ... ... ........ I1-2-14
INPUTS TO PROCESSOR DATAPATHS . . . . . .. . ... i I1-2-15
Bus Register Multiplexer (BRMX) . . . . ... ... ... ... ... I1-2-15
e e e I1-2-16
. i i i
. . . . . . . . .
Internal Data Bus (INTD)
. . . . . . . .. e 11-2-18
SSRJ Multiplexer
e e 11-2-18
SCCHBus Output . . . . . . .o oot
11-2-18
e
e
e
ittt
v
SCCM MultipleXxer . . . . . o o
I1-2-18
e
vttt
v
v
.
.
.
.
SCCN Multiplexer .
I1-2-18
oo
...
...
...
..
.
.
Bus Register (BRandBRA)
11-2-18
..
...
...
...
...
.
.
.
.
.
AFIR)
IRand
Registers
Instruction
PROCESSOR DATAPATHS OUTPUTS . . . . . . . . it i oo 11-2-19
Bus Address Multiplexer (BAMX) . . . . . ... . ... o 11-2-19
Unibus Data Multiplexer (DMX) . . . .. . .. .. oo oo 11-2-19
BusRegister A(BRA) . . . .. . . i 11-2-20
. . . . . . . . i e 11-2-20
Display Multiplexer

CHAPTER 3

PROCESSOR CONTROL REGISTERS

2.1
2.1.1

2.1.1.1

2.1.1.2
2.1.2
2.1.2.1

2.1.2.2
2.1.3

2.14

2.1.5
2.1.6
2.1.7

2.1.8
2.19

2.19.1

2.19.2

2.19.3
2.194
22

2.2.1
222
2221

2222

2223
2224

223
224
2.3

2.3.1

232
233

3.1

3.2
3.3

34
3.5
3.6
3.7

. . . ... ... ... ...
SWITCH REGISTER (SWR) AND LIGHT REGISTER(LR)
LOWERSIZE REGISTER . . . . . . o i i i e e e e e e e e e e e e e e e s
e e e s
UPPER SIZE REGISTER . . . . . . et e e e e e e e e e e e e e e
e e e
e
e
e
e
e
e
e
e
e e e
SYSTEMID REGISTER . . . . . . o o i o
e e e
e
e
e
e
e
e
e
e
e
e
e
e
e
CPUERROR REGISTER . . . . . .
..
.
..«
...
.
.
.
MICROPROGRAM BREAK REGISTER(PB)
PROGRAM INTERRUPT REQUEST REGISTER(PIRQ) . . . .. ... ... ... ...

II-iv

I1-3-1
I1-3-1
I1-3-1
II-3-1
I1-3-2
I1-3-2
I1-3-2

SECTION II

PROCESSOR

CONTENTS (Cont)
Page

3.8

STACK LIMIT REGISTER (SL)

PROCESSOR STATUS WORD (PS,PSW)

. . . . . . . .

e e

. . . . . . . . .

e e e e

I1-3-3

e e

I1-3-3

3.9.1

ReadingthePS

. . . . . . . . . .

39.2

Loadingthe PS

. . . . . . . . . . .

393

Processor Mode Bits [PS(15:12)]

394

Current Processor Mode [PS(15:14)]

. . . . . . . . . . . .

3.9.5

revious Processor Mode [PS(13:12)]

. . . . . . . . . .. e

3.9.6

PS(15:12) Implicit Write

General Register Set Bit (PS11)

39.8

Priority [PS(07:05)]

399

Trace Bit (T Bit,PS04)

3.9.10

ConditionCodes

114-2

MAINT STPR Switch

. . . .

SOURCE SYNCHRONIZER
RC Clock Selection

MAINT STPR Selection

4.24

Synchronization

4.3

PHASE SPLITTER/BUFFER
Level Converter
Phase Splitter

114-2

11-4-2

i i i

i
e

i i

e e

e e e e
e

114-2

e e e

11-4-2

e e e et et e

e e e e

e e e

e e e e

e
e

e e

114-3

e e e

11-4-3

114-3

e e e e e e

I14-2

e e e

e e

. . . . .

11-4-4

e e

e e e e e e e e e e e e e

[14-4

. . . . .

I14-5

e
e e e e
e
e e e

11-4-6

e e e e e e e e e

114-7

TIME STATES (TIGETS1 L-TS5L)

4.8

PAUSE CYCLES ANDCLOCKBR
SynchronousPauses

. . . . . . . .

11-4-9

. .. .. ... ... it

11-4-9

. . . . . . . . .. .

4.8.1.1

Internal Bus (INT D) Pause (T2)

4.8.1.2

CachePause (5)
AsynchronousPauses

UnibusPause (T2)

4.8.2.2

INTRPause (T2)
CLKBR,BRA

i it

114-9

11-4-9

. . . . o v i i i it

. . . . . .. . . .
. . . . . . @

. . ... .. .. ... ... .. ... ...

. . . . . . . .. . ...

4.8.2.1

4.8.3.2

. . . .. ... ... .. ..., e

4.7

4.9

. . . . . ..

. . . .

e e

. . . . . . . . i 0 i i

RING COUNTER

e e e e

. . . . . . . .

. . . . . . . . . .

e e e e

. . . . . . . . .

TIMING PULSES, T1—T5

4.8.3.1

e e

. . . . . . . . . . L

4.5

4.8.3

. . . . . . . . . o

4.6

4.8.2

. . . . . . . . . . . .

4.2.3

e e e e

e e e

. . . . . . . . . . .

Crystal Clock Selection

4.3.2

4.2.2

4.8.1

11-3-7

114-1

4.1.3

. . . . .t
e e s e e e e e e e e e e e e e e e

R/CClock

TS H

11-3-6

. . . . . . . o

. . . . . . . . .. .

I1-3-6

I1-3-8

4.1.2

4.6.2

I1-3-8

Crystal Clock

Buffers

I1-3-6

. . . . . . . . . . i i

CLOCK SOURCES

TIGCTPBANDTF

I1-3-5

e e e e

4.3.1

I1-3-5

e e

. . . . . . . . . .. . .

. . . . & . o

4.1.1

4.4

i i

11-3-7

4.1

4.3.3

TIMING GENERATOR

4.6.1

. . . . . . . . . .

CHAPTER 4

4.2

II-3-5
e

. . . . . . . . . . o

3.9.7

4.2.1

. .

11-4-9

114-9

et e

e e

e e e

e
e

. . . e
e
e

Non-Cache Cycles

. . . . . . . .

Cache Cycles

. . . . . . . o

MAINTENANCE STOPS

. . . . . . . .

49.1

Single CycleMode

4.9.2

ROM+UPB

4.9.3

TIGBCONTL

. . . . . . . . . .

. . . .

. . . . .

i i it ittt e

e e

e e e e e e e e
e e

e e

e
e

II-v

e e e e e e e

e e e e e

1149
114-11
114-11
I14-11
114-12
114-12

114-12

114-13

et e

114-13

SECTIONII

PROCESSOR

CONTENTS (Cont)
Page

CHAPTER 5

DATA TRANSFERS

5.1

PROCESSORDATATRANSFERS

5.1.1

Typesof Data Transfers
Types of BUST Cycles .
TypesofPause Cycles
.
BENDCycle
. . . . . .
UNIBUS INTERFACE . . . .
UNIBUS DATAINTERFACE

5.1.2
5.1.3
514

5.2

5.3

.
.
.
i
.
.

. . . . . . . . .

. . . ..
. . . . .
. . ...
i
. . .
. . . . .

5.3.1

Unibus Data Transfer Protocol

5.3.2

Unibus DataInterface

Unibus Device References

Unibus Timeout

5323

Control Register Reference

ABORTS, TRAPS AND INTERRUPTS

6.1

SERVICE FLOWS AND VECTORS

6.1.2

CPUError Register

6.1.3

Service Flows

I1-5-3
11-5-4
I1-5-4

II-5-5
I1-5-5
I1-5-5
I1-5-5

11-5-6

. . . . .. ... ... ... .. ... . ......

I1-5-6

i i i

. . . . . . . . . i it

CHAPTER 6

I1-5-1

... ...

. . . . . . . . . ..

5.3.2.2

/21
7

... ... .. . .
L.
0 i ittt
i e e
.. ..
. i,
e
e e e
e
e e e
e
e
e e i
e e
. . . . et
st

. .

. . . . .. . .. ... .. ... ..

5.3.2.1

6.1.1

i ittt

e e

I1-5-8

. . . . . . ... ... ... .. ... .. ...,

I1-59

. . . . . . . . . . .

e e e

e e e e

it it

e e

. . . . . . . . . 0

v it

. . . . . . . . o

et e

e e

I1-6-1
11-6-1
I1-6-2

e e

I1-6-2

. . . . . .. ... ... .. .. ... ... ...

I1-6-2

6.1.3.1

Entry into the Service Flows

6.1.3.2

BRK.90and ZAP.OO

. . . .. . . . .

11-6-2

6.1.3.3

BRK.O0Oand BRK.10

. . ... ... ... ... ...

11-6-2

6.1.34

Branch Enable 13

. . . . . . . . . . .. . . . e

I1-6-2

6.1.3.5

Red Stack Error (SER.00and SER.10)

6.1.3.6

BRK.80and BRK.20

6.1.3.7

BK.30

6.1.3.8
6.1.3.9

6.2
6.2.1

ABORTS

0 i i i

. . .. .. .. ... ... ......

. . . . . . . . . . . e

e e

I1-6-3

Entry intoSVC.00

. . . . .. . .. .. e

11-6-3

SVC.O0—SV.O0

. . . . e
e e e e
e e e

Address Errors

. . . . . . . . o

6.2.1.1

Odd AddressError

e e

. . . . .. . ...

e e

e e e

e e e e e e

e e

11-6-3

. . . . . . . . .. ... ..

Memory Management Aborts

. . . . .. ... ..

6.2.14

Timeout Error

. ..

...

11-6-5

. . . . . . . . . . e

I1-6-6

Timing of Address Error Aborts
Stack Errors

. . . . . . . o

. . . . . . . . e
e e e

11-6-7

Stack Limit Errors

6.2.2.3

Timing of Stack Error Aborts

. . . . . . . . . . .

e e e e e e

o e

. . . .. ... ... ... .. ... .. ...

. . . . . . ...

e e
e e

I1-6-10
11-6-10

Description

6.2.3.2

Timing of Parity Error Aborts
TRAPS AND INTERRUPTS

. . . . . .

6.3.1

Mlegal Halt

. . . . . . . . . .

6.3.2

Console Flag

. . . . . . . o .

6.3.3

Cache Parity Trap

I1-6-8
I1-6-10

. . . . . . . . .. e
e

6.2.3.1
6.3

e e e e e e e e

11-6-6
I1-6-7

Kemel R6

I1-6-5

6.2.2.2

Parity Errors

. . . . .. ... ... .. ... .......

6.2.2.1

6.2.3

I11-6-3
11-6-3

I1-6-3

Non-Existent Memory Error

6.2.1.2

6.2.2

e e e e e

o e

6.2.1.3

6.2.1.5

I1-6-3

. . . .

11-6-3

. . . . .. . ... ... ... ...
.

et
o

II-vi

11-6-11

e e e e e e e e e

I1-6-12

11-6-12

I1-6-12

i e

11-6-12

. . . . . . . . . .

...

SECTION II

PROCESSOR

CONTENTS (Cont)
Page

6.34

Memory Management Traps

. . . . . . . .. .. ... ... ...

6.3.5

Yellow Zone Trap (SLYEL)

. . . . . . . .. .

6.3.6

Power Down Trap (PDNF)

6.3.7

FP Exception Trap

6.3.8

Program Interrupt Request

6.3.9

External Interrupt (BUSBR)

6.3.10

TBitTrap

6.4

. . . . . . . . . . .

11-6-12
11-6-12

. . . . . .. . . ... ... ... ... . ... ...

11-6-14

e e

. . ... ... ... ...

11-6-14

NPR-NPG Sequence

BR-BG Interrupt Sequence and Passive Release

v v v v v i it

11-6-17

. . . .. ... ... .......

et e e et

11-6-18

. . . . . . ...

. . . . . . .. . ..

6.5.2

Power-Up

6.5.3

PDP-11/70 System Power Control

11-6-14
I11-6-14

I1-6-17

6.4.3

Power-Down

. ... ..........

6.4.2

6.5.1

. . ... ... ... ... ... .......

Unibus Arbitration Interface Logic
. . . . .

e i
e

. ... ... ...,

UNIBUS ARBITRATION AND INTERRUPT INTERFACE

6.5.3.1

I1-6-12

11-6-12

i i

. .

. . . . . .

UNIBUS POWERMONITOR

...

ie i
e

. . . . . . . . . 0 i i i i

6.4.1

6.5

i it

. . . . . o

et i

e e

11-6-19

e e

I11-6-20

e e

I1-6-21

e e e

e e

e e e e

e e

. . . ! ... ... ...............

ACLOConnections

. . . . . . v v v i v it it e e et e

6.5.3.2

DCLO Connections

. . . . . . v v v i vttt et e e e et

6.5.3.3

PowerDown

. . . .. . . . .

e e

11-6-21

[1-6-21

11-6-21

11-6-22

ILLUSTRATIONS

Figure No.

Title

1-1

Block Diagram

1-2

ROM Word: Clock, ICsand Registers

1-3

Flow Chart Symbols (P/OFlows2)

Page

. . . . . . . . . .

e e

. . . . . .. ... ... ... ...,

. . . . . . . 0

. . . . . . . .

i i

e e

II-1-5

11-1-8

ROMTiming

Source and Destination Mode Formats

1-6

Aand

1-7

Multiply Instruction

1-8

Divide Algorithm

1-9

Divide Instructions

1-10

Determination of an Instruction from the Binary Code

1-11

Instruction Execution Example

. . . ... ... .. ... ... . ...

1-12

ROM Address

e e

I1-1-38

1-13

Sources of C Bit Data, Simplified Diagram

. . . .. ... ... ... ... .......

II-1-56

1-14

Sources of N Bit Data, Simplified Diagram

. . . ...
.. .. e

II-1-56

1-15

Sources of Z Bit Data, Simplified Diagram

. . ... ... ... ... ... .......

I1-1-59

1-16

VENI1 Sources of V Data Bit, Simplified Diagram

. . . ... ... ... ........

I1-1-61

1-17

VEN2 Sources of V Data Bit, Simplified Diagram

. . . . ... ... ..........

11-1-62

2-1

Block Diagram DataPaths

2-2

Typical SHFRBit

. . . . ... ... ... .............

. . . . . . .

. . . . . . . . .

o i i i v i i e e

e e e

. . . . . . . . . .

. . . . . . . . .. .

i it

1-5

. . . . o

e e e

1-4

CForks,General Case

I1-1-2

e
e e

II-1-16

I1-1-23

e e e

I1-1-26

e e e

I1-1-27

. . . . . .. .. ... ... ..

e e e e e e e e e

.. ...,

e e e e e e e
e e e e

e e

. . . . . . .. ... ... . ... .. .. .. ..

. . . . .. . .

. e

2-3

General Register Storage in GS and GD Storage Elements

Processor StatusWord

2-5

SC Loaded With 00101

2-6

SCLoadedWith 175

2-7

BRMX Selection, Simplified Schematic

. . . .. ... ... ......

. . . . . . . . .. ...
. . . . . . . . . . . .
. . . . . . . . . . o

e e

i
i

. . .. ... ....... RS

H-vii

11-1-9
I1-1-12

I1-1-34
I1-1-35

I1-2-2
11-2-6

11-2-8
II-2-8

e e

11-2-12

1I-2-13

ITIRPP

I1-2-16

SECTION II

PROCESSOR

ILLUSTRATIONS (Cont)
Page

2-8
3.1

3.2
3.3

34
3.5

Internal Data Bus Block Diagram
. . ... ... .. .. ... ...
11-2-17
CPUError Register . . . . . . . . o o i i i i
i
e
e e e
e e
e
e 11-3-2
Program Interrupt Register . . . . . .. . .. .. ... ... ..
.
o
oo, I1-3-3
Stack Limit Register . . . . . . . . . o
i
e
e
e
e I1-3-3
Processor StatusWord
. . . . . . . . ... I1-3-3
PSW Clock and Direct Set Simplified Schematic . . . ... ... ... . ... ...... 11-3-7

4-1

Timing Generator Block Diagram

4.2

Timing Source Synchronization

4.3

Timing Pulse Generation . . . . . . . . . . . . .
i
e e
Simplified Schematics of TIGDTSH
.. ... ... ... . ... ...
... ...
Simplified Schematics of TIGDTSL
. . .. ... ... ..
..
Time States
. . . . . L L
e e e e e e e e e e e e e e
e
e
e e e
e

4.4

4.5
4-6

Timing Generatorand Pauses

. . . . . . ... ... ... ... ... ...
. . . .. ... ... ... ... ..

. . . . . . .. ... ... ... ..

4-8

Clock BR Circuit (Part of D-CS-M8139-0-1,Sheet3)

4-9

Clock BRTIiming . . . .
Processor Data Transfers
Unibus Data Transfers
.
Address Error Aborts
.

. . .« o i i it i i

. . . . . . . .. . .. ..

5-1
5-2

6-1

6-2

Examples of Stack Limit

6-3

Stack Error Aborts

Parity Abort

Program Interrupt Request Register

6-6

BR — Interrupt Sequence

. . . . . . . .

0oL

1149

I14-11

e e e

e e

11-6-9

e e

11-6-10

e e

I1-6-11

e e

. . . . . ... ... ... ... .. ... .....

I1-6-14

. . . . . . ...
e e
e e

11-6-16

. . . . . . . . .

I1-6-17

e e

11-6-18

I1-6-19

Power-Down . . . . . . L L
e
e e e e e
e e e e e e
e
Power-Up
. . . . i
e
e
e e e e e e e e e e e e e e e e
PDP-11/70 ACLO and DCLO Connections . . . . . . . . ¢ v v v v v v vt v v v v v

I1-6-21

6-8

NPR-NPG Sequence

6-9

INTR Sequence

6-10

6-12

I14-3
11-4-5
I14-6
14-7
1149

e i e e e e
e e e e
e e e e e
114-12
. . . . . . . . . . . . . i v i i i i it i
e I1-5-2
. . . . . . . . . .. . .
i
i
e I1-5-7
. . . . . . L.
e
e
e e e e e
e e e 11-6-6

6-5

6-11

114-1

. ... ... ...........

. . . . . . . . . L

UBCD Free Clock

...

e e s e

e i

. . . . . . o i v v it e e e e b e e e

e e

e e e e

. . . . . .« i i i i i i it e

e e et e e e et e

11-6-20
11-6-22

TABLES

Title

Table No.
1-1

Microprogram Bit Usage

1-2

Sign Correction for MUL Instruction

Page

. . . . . . . . . . . .

1-3A

Instruction Microprogram Properties

1-3B

AFork, BIN® SMO

1-3C

AFork, DAC

1-3D
1-3E

CFord, BIN
. . . . .
.
Branches (AllCycleson Flows 1)

1-4

Branch Signal Sources

1-5A

A Fork Address Generation

1-5B

AFork, BIN*-SMO

1-5C

AFork, DAC

1-6

Branch Instructions

e
e

e e

. . . . . . . . . .. .

I-viii

I1-1-32
I1-1-33

II-1-33

e e

i i it i it e

e
n s

I1-1-33
11-1-33

e
i

e e

000,
e

. . . . . . . .

II-1-6

11-1-24

e e e

. . . . . . . . . . . . i

.. ...,

...
e

. . . . . . . . . . . @

. . . . . . . .

. . . . .

. . . . . ... ... ... ... . .

. . . . . . . .

. . . . .

. . . .. ... . ... ...

e
e

I1-1-41

I1-1-44

e e e e

e
e

I1-1-45

I1-1-48

SECTION II

PROCESSOR

TABLES (Cont)
Page

1-7

1-8
1-9

1-10
1-11

1-12
1-13
1-14

1-15
2-1
2-2
2-3

2-5
2-6
2-7

2-8
29
3-1
4-1

6-1

6-2

6-3

6-4

. . . . . . . . . o v o v it i e
Branch Instruction ROM Address
e
e e e e
. . . . . . v o v v v v v it e
C Fork Address Generation
. . . . . . o v v v v it i e e e e e e e e e e e
B Fork Address Generation
e
e
e
i i
. . . . . . . . .«
Condition Code Load
. . . . . . . ... oo
Subsidiary ROM Address Sources
CBitData SOUICES . v v v v v v e e e e e e e e e e e e e e e e e e e e e

II-1-49
II-1-51
II-1-52
1I-1-54
II-1-55
11-1-57

. .. ... .. ... ... ..

I1-2-10

.« « « v v v v e e e e e e e e e e e e e e e e e e e e I1-1-58
e e e e e e II-1-59
. v v v v v o e e e e e e e e e e e e e e e e e
11-1-60
e e
e
VBitDataSources . . . . v v v v v i e e e e e e e e e e e e
I1-2-5
..
..
...
...
...
...
Non-Instruction-Dependent ALU Control Signals . . . . .
11-2-9
.........
...
...
...
.
.
.
.
GDAM
Multiplexer Input Selection GSAMand
11-2-9
o
oo
...
...
.
.
.
.
Multiplexer Input Values . . .

NBitData SOUICES
ZBit Data SOUICES

Multiplexer Input Selection GSREG and GDREGSET1

ALU Input Multiplexers . . . . . . . . . ... oo oo II-2-13
11-2-14
BMX Output Selection . . . . . . . . oo v vt
e e e e e e e e II-2-15
BMX Output FromKIMX . ... .. ............ e
Data Qutputto Unibus . . . . . . . . . 0o i 11-2-20
Display Register Selection . . . . .. .. ... ... ..o i I1-2-20
. . . . .. . ... oL oo I1-3-4
Processor Status Word Bit Assignments
. . ... ... ... ... ... .. ..., 11-4-10
Ring Counter Stop and Pause Conditions
e e 11-6-4
e
e e e e e e e e e e e
. . . o . 0 i
Service FIoWs
i i I1-6-13
. . . . . . . . .« . o o
Processor Service in Order of Priority
. . . . . . . ... oo e 11-6-14
Trap Vectors Enabled
. . . . . . . o o v v vt i i i i e e e e e e e I1-6-21
ACLO and DCLO Driver Qutputs

II-ix

INTRODUCTION

The KB11-C Processor System is capable of manip-

the latter case, internal conditions determine which

ulating, storing, and routing data. The processor is

branch the instruction will follow.

the system component that manipulates the data.
Although the processor is designed to effect com-

The

plicated changes to the data that it receives, it ac-

tional parts:.

tually

consists

of elements

making

only

processor

combining

number

these

divided

into

several

func-

exchanges

data

simple

changes. The complex data manipulation are acheived

can

simple

changes in a variety of ways.

The

Interface

with

devices

section
external

the

processor

(Chapters 5 and 6).
2.

The processor consists of logical elements, each ele-

The Data

Paths section

performs data

handling functions (Chapter 2).

‘ment designed to perform a specific function. For
example, some elements store data, some read data

from another part of the computer, and others per-

form

simple

plementing

modifying

functions

such

formed

the data or combining two operands,

cither

arithmetic

simple

basic

operations

logical

means.

are combined

into

Control section includes the logic that determines which operations are to be per-

com-

during

particular

state

and

These

what the next machine state should be

func-

(Chapter 1).

tional groups known as instructions. An instruction
4.

can include a number of operations so that data

The Timing section generates clock sig-

can be combined, changed, moved, or deleted. In-

nals which synchronize the various oper-

structions can be further combined into programs

ations of the KB11-C Processor System

which

(Chapter 4).

use

number of instructions to construct

cven more complex operations.

The Control Registers store the results of
processor operations. This data may be

The basic logical elements of the processor can per-

form only a small number of operations at one

used in determining future processor op-

time. Therefore, to combine a number of these oper-

erations (Chapter 3).

ations into an instruction, the instruction must beé

divided into a series of sequential steps. These steps

The Interface section consists basically of logic nec-

arc called machine states, or cycles, and may per-

essary for transferring data between the processor,

form cither a single operation or several operations

the

at the same time. An instruction thus becomes a se-

Data

quence of machine states. This sequence may be

form the three main processor functions of data

fixed or may provide alternate paths (branches); in

storage, modification, and routing.

II-1-1

Unibus,

the

memory,

and

the

Console.

The

Paths and Control sections interact to per-

The Data Paths section consists of storage registers,
shift registers, multiplexers, and an Arithmetic
Logic Unit (ALU). The multiplexers control the
data flow between registers. The ALU executes the
more complex data manipulations, while the shift
registers move the data bits stored in them, either

ROM
ADDRESS

LOGIC

to the left or to the right.

MEMORY

1—’ MANAGEMENT

ROM

Operation of the elements of the Data Paths section
is determined by the Control section. Refer to Figure I-1. This section consists of a Read Only Memory (ROM) and its associated logic. The ROM
contains 256, (400g) locations. Each location contains 680 bits. This 64-bit ROM output is divided
into 32 groups or fields, each of which controls a
discrete part of the KB11-C Processor. One of these
fields is called the Address Field (UADR or UAD).
The UAD field from the current machine state is
combined with selected data from other sections of
the KB11-C Processor in the ROM address logic,

UAD

DATA

INTERFACE

CONSOLE

TIMING

PATHS

11-3101

Figure I-1

whose output is the ROM address for the next ma-

chine state. In this manner, the required machine
states are generated in the proper sequence. The
UAD field may either be used as the next ROM address, or may be modified by the feedback from the
other sections of the processor to generate the next
ROM address. This allows for instruction branching that is dependent on other conditions, and also

Processor Control Section

for the use of machine states that are common to

several instructions. An auxiliary ROM in Memory

Management
cessor ROM.

II-1-2

uses the same address as the pro-

CHAPTER 1

INSTRUCTION DECODE AND
MICROPROGRAM CONTROL

The main function of the processor is to execute a

When an instruction is fetched (read from memory)

Program, or sequence of Instructions.

it is stored in two instruction registers (IR):IRCAIR(15:00)

Instructions

are

stored

memory.

Program

and

RACJ

AFIR

(15:00)

and

the

FPP’s FIRA if this option is installed. The contents

Counter stores the address of the next instruction.

of these registers are decoded, and these decoded

At the end of the execution of one instruction, the

outputs control the ROM address, along with in-

processor fetches (reads from memory) the instruc-

puts from other processor circuits.

tion that is to be processed next.

The decoded outputs of the IR are also used to de-

Instructions consist of a series of steps, called Machine States, or cycles, that are executed sequentially.

This

sequence of steps is

unique to each

instruction, although some steps, or series of steps,
may be common to several instructions.

termine how the results of the executed instruction
are interpreted in setting the Condition Codes. Refer
to Paragraph 1.5.
BLOCK DIAGRAM

Figure 1-1 is a block diagram of the KB11-C Read
Only Memory (ROM). The ROM contains 256, or

The sequence of operations within each instruction

400« processor control words. For each processor

in the KBI11-C is controlled by the microprogram

machine cycle, one of these stored words is output

Read Only Memory (ROM).

to the Data Paths section and to the other processor

circuits.

A ROM is a storage device whose contents are pre-

fields,

and each

The

ROM

word

divided

into

determined and cannot be changed. Each address

multiplexer or process of the processor. In Figure

field controls a specific register,

generates a unique output. The KB11-C ROM has

I-1,

an 8-bit address, which allows 256, different out-

name and by bits of the microprogram word occu-

puts, each consisting of 68 bits.

pied by the control field. The control selection that

This 68-bit output (ROM word) is divided into 32

value that can be stored in the field, is listed under

fields, each of which controls a different part of the

the field name. Where possible, the field name and

each

control

field

is listed

by a mnemonic

is made, or the action that takes place for each

Processor.

description are placed next to the logical element

controlled by that field.
The ROM word contains an address field, which in

The

most cases is the address of the next ROM word:

other parts of the processor must be stored in a buf-

microprogram

ROM

outputs

that

control

the ROM is self-sequencing. This address field can

fer register, so that the next microprogram word

be modified by conditions internal or external to

can

selected

while the current word is being

the

used. Therefore,

a ROM Buffer Register (RBR) is

processor,

such

the

instruction

operation

code, the addressing mode or other factors.

provided lor these outputs (Paragraph 1.1).

I1-1-1

FROM

CONDITION

CODE LOAD

[54-52]

ALUN-O

(T2)

NO CHANGE
INSTRUCTION DEPENDENT

CCL

VARIOUS

DATA PATHS
L

T0
CONDITION
CODES

CCLD6(N,C, & V UNAFFECTED; Z+— Z* SHFR=0)
CCLD7(Z,N,& V UNAFFECTED; C+—ALU CARRY)

CONDITION CODE
| GENERATOR

SET/CLR FROM BR (CCOP)
LOAD FROM FPP IF ENABLED
8 N ACC SHFR;C & V=—0)
CCLD4(Z

RAR

(GRAB, IRCE, F

V +—Void +(SHFRI5 ¥ AMX15))

CCLDS(Z &N ACC SHFR;
C <—AMX15;

FROM IR

SUBSIDIARY

FORK C

ROM CONTROL

)

(IRCH)

FROM AFIR

IR DECODE

AFIR DECODE

(IRCB, C,D)

(RACE, F,H)

ROM

RBR

< 67:64> ( (RACA )
ROM <

oK
TM

<63:
ROM M <63:60>
(RACA)

(RACA,

!
N

(IRCC)

[
»{ ROM <59:56>

FORK B

FORK A

{IRCB)

(RACE,F,H)

FEN C14-123

O1 NO
FORK
FORK A
FORK

{IRCH)

(GRAA)

ROM

FORK ENABLE

ALU
SUBSIDIARY
ROM

o0
RE

BRANCH ENABLE
8eF [11 -8}

4 FORK C

DESTINATION
MODE 3,5,7
CONDITION CODE Z

SR= 4
OND
-(PWRF+ INTR)

~DIV

CONDITION CODE N

UAD [07-00]

1
12
13

TO ADDRESS GATING

BUS DELAY

MSC (T1) [29-27]

BsD (T1) [40-39]

O
|

NO EFFECT
FPATIN

3 SET CONF IF KERNEL MODE

4 SPL (SET PRIORITY LEVEL)

CONDITIONAL

O
1L

BUS

BRQ

STROBE

8sc (T1) [26-24])
O

1
2
3
4
5

DATI

BSOP2

|RIP+ FP SYNC

SC= 0
|CONF
(CONSOLE FLAG)
PF{O)*(SF+TF

(Oyx(s

)

-FJ/CLASS

RACK RIP+FP SYNC L *

(o1

DRO (1)

~0/CLASS

(RACC)

[
—

Emsc
L
[—
= 8SC

L»| ROM <23:20> (RACC)

RARA | }+{ROM <19:16>

(RACC)

(RACC,

—

RACD) | eROM<15:12> (RACDIE=
.
-] ROM <11:08> (RACD) [=

— aLu

be{aLu

CTRL
1O AL
—*|(GRAA)

—

| ROM <07:04> (RACD) =

TMCB BRQ#
(T + CONF )L

BEF=14) =

ZAP

200

Le{ ROM <03:00> (RACD) =
—

CONDITIONAL FORK C

FP START

BCT (T1) [32-30]

FPS (T1) [67]

EFFECT

FPC (T1) [64-65]

MISCELLANEOUS
M TROL

TIMING

(UBC)

(TMC)

(T16)

CONTROL

NOP

3
4
5

LD FPA
READ DATA
READ FPS

tg "::?g

READ FOR

READ

Block Diagram

FPA

(PRIORITY ARBITRATOR)

NOP

1 FLOATING POINT START

1S HIGH ORDER

OF FPC

GENERATOR

" TO ALL MODULES

Y
TO/FROM
UNIBUS

TO/FROM
FPP, MEMORY MGMT.

SIGNALS

& UNIBUS

CONTROL
% BCT = 1

‘

UN1BUS
AND
CONSOLE

BEND (BUS END)

FLOATING POINT CONTROL

;
TRAPS AND

6 ACKNOWLEDGE

I1-1-2

et
L

( BEF =15)% FJ/CLASS
= CONDITIONAL FORK B)

BUS CONTROL

> ROM <31:28> (RACC)

SR15 (1)

TMCB BRQ* (T + CONF
)L

— 8CT

)

CONTRO
TM (GRAC) L " GENERAL
REGISTERS

— 8sD

sl ROM <35:32> (RACB)

FRMB FP CLASS L

DRO (1)
-BRQ
PF(O)%(SF+ —TF

GENERAL
REGISTER

> ROM <39:36> (RACB)

—»{ ROM <27:24>

RESTORE

(RACA)

|FEN

RACK FP REQH

E CCL}_

NO PAUSE
INTR PAUSE

SRC1 DATI
» 1 READ FPP DATA
KERNEL DATI
2 CONSOLE ACKNOWLEDGE
SRC2 DATI
3 CLEAR FLAGS
FC_(CONTROLLED BY FPP)
4 INIT IF KERNEL MODE
DATO
5 STACK REFERENCE
»

Figure 1-1

BR14
(0)
RACK BE 7S5H

FROM °°“5°LE:>

“?Acmi BEN

ADR

clk

Ti4 [EPWE
.
CLK =
Eoap
(RACB) —H _______|
—>| ROM <43:40>

-0BD (ODD BYTE DESTINATION)t| -DIV QUIT

3}BUS PAUSE

6 BSOP1

suB

- TM (RACA.I
|racc)| F»{rom <47:44> (RACB) '

— (RAC)
C

BRANCH

(RACA)

RARB | F»{ROM <51:48>

RACC))

((ssr=14;=gonso|_s BRAN(C):HES

BUST

CONDITION

C<0

T
INl |

5)* FORK B
OBD= CONDITIONAL
t (BEF=

7 BUST (BUS START)

SC C=0
=

M ISCELLANEOUS

UADR4 [+20]

GND

MICRO ADDRESS FIELD

r_’

UADRS [+40]

RAGH!

o ROM <55:52> (RACA)

L————-‘AD GA

CONDITION
CODE
SUBS IDIARY

—» TO MEMORY MGMT

FROM
MEMORY MGMT.
& UNIBUS

INTERNAL DATA BUS
.

CLEAR SYNC

CLS (T1) [66]

@ NOP
1

INITIALIZE

SYNCHRONIZER

‘

1-3447

from the primary IR and use the outputs of a sub-

Three output fields are used to select the next microprogram word (FEN, BEF, and UAD). They

sidiary ROM, which decodes some classes of in-

are not buffered because they are used immediately

structions. These forks are used after a destination

and the resulting address is buffered. Immediately

operand

‘after the beginning of a- machine cycle; when a-new

respectively.

fetch

and

source

operand

fetch,

microprogram word becomes available, the ROM
address generation circuits begin the calculation of

To summarize the operation of the microprogram

the next ROM address. This corresponds to select-

control logic: during each machine cycle, an ad-

ing the next machine state. The generated address is

dress is assembled from any enabled fork combined
with the address field of the microprogram word

assembled by the address gating logic and loaded
into the ROM Address Register (RAR). There are
three copies of the RAR to accommodate the output loading required for 16 ROM elements, and to
transmit the ROM

address to

Memory Manage-

ment. (Refer to Paragraph 1.4.1.)

and any enabled branches. This address is loaded
into the ROM address register to select a new microprogram word. At the beginning of the next machine cycle, the new microprogram word is loaded
into the ROM buffer register and the sequence is
continued.

The

address

gating

logic

assembles

the

address

from five sets of inputs. The basic input, which is al-

On power-up, the ROM is initialized and the pro-

ways present, is the Address (UAD) field of the cur-

gram is forced to a fixed address in memory which

rent microprogram word. The UAD is ORed with

contains the power-up subroutine. This subroutine
typically restores the program parameters that were

the outputs of the Branch logic, which is controlled

by the BEF field of the microprogram word. The
Branch Control logic selects a set of condition in-

stored during power-down. Refer to Chapter 6
(Traps, Aborts and Interrupts) for a description of

puts from signals received from the processor data

these features.

paths, the condition codes, and from the processor
interface modules. Depending on the state of the se-

DOCUMENTS

lected inputs, the Branch Control generates one or

The documents listed below contain the informa-

two signals that are used to modify the address

tion required to follow an instruction from fetch to

(Paragraph 1.4.4).

execution.
I.

The three other inputs to the address gating circuits

KBI11-C Flow Diagrams, drawing num-

ber D-FD-KBI11-C-1, sheets 1 — 15. This

are from the Fork logic. The three forks are similar

set contains a block diagram of the pro-

uses

cessor on sheet 1, and the sequence of

combinational logic to decode the instruction type

microprogram cycles in flowchart form,
on sheets 2 - 15. The flowchart sheets

implementation

and

purpose.

Each

fork

and a variety of processor conditions, and generates

one ofa number of addresses that is combined with
abled by one bit in the Fork-ENable (FEN) micro-

are labelled “FLOWS 1 through
“FLOWS 15, and are referred to in this
manner throughout this manual. (Refer

program field; normally all forks are disabled. No

to Paragraph 1.2.)

the UAD input by masking. Each fork can be en-

more than one fork is ever enabled at a time (Para2.

graphs 1.4.6 - 1.4.8).

ROM Map, sheets 12 - 15 of the RAC
module schematic,

drawing number D-

CS-M8123-0-1. These four sheets reproThe A Fork logic, used to select the machine state

duce the computer listing, in numerical

that follows an instruction fetch, requires a separate
instruction register (AFIR) because this fork must

word, the name of each state, and the

order,

of the

contents

of each

ROM

operate rapidly and therefore puts a heavy load on

page of the Flows on which this state is

the IR outputs. The B and C Forks decode inputs

shown. Refer to Paragraph 1.3.

I1-1-3

The ROM and its control logic is shown on draw-

The

ing

74S174

D-CS-M8123-0-1,

ROM

Control

buffer

D-type hex

implemented

flip-flop

primarily

registers.

(Some bits

(RAC module), and on drawing D-CS-M8132-0-1,

are implemented by individual flip-flops to provide

IR Decode & Cond. Codes (IRC module).

scparate

input

clocking

greater

output

load

capacity.)

The ROM, ROM Buffer Register (RBR)
and ROM Address Register (RAR) are

Various ROM bits are clocked into the output buf-

shown on sheets 2 — 5 of RAC (drawings

fer register at different times. Most bits are clocked

RACA-RACD).

by the T1 pulse, while others are clocked by the T2

Refer

Paragraphs

I.1 and 1.4.1.

pulse. Certain bits are clocked on the trailing edge

of the T1 pulse to allow slightly more time for the
The ROM Address bits (RADR), which

processor to complete operations started by the pre-

are the inputs to the RAR are shown on

vious machine cycle.

sheet 11

of RAC (drawing RACL). Re-

fer to Paragraph 1.4.2.

Figure 1-2 shows the ROM output bits, the type of
ROM IC that generates each bit (i.e., C71), which

The Branch Control logic is on sheet 10

groups of bits are stored in one 6-bit IC register,

(RACK) of RAC.

and

Refer to Paragraph

144,

the time at which they are clocked into the

RBR. Table

[-1 gives much of the same informa-

tion, plus the name given to each field.
4.

The A Fork logic is shown on sheets 6 -

8 of RAC (drawings RACE, RACF and

The

RACH). Refer to Paragraph 1.4.6.

RACA., is clocked by the T2 pulse; none of the con-

The B Fork logic is on sheet 3 of IRC

on this drawing can be assumed to have settled be-

(IRCB). Refer to Paragraph 1.4.7.

fore the T3 pulse.

output

buffer

shown

drawing

trol signals transmitted from the 18 bits of storage
5.

The C Fork logic is on sheet 4 of IRC

Five output signals are derived from the contents of

(IRCC). Refer to Paragraph 1.4.8.

the buffer

the falling

cdge of the T1 pulse, rather than the leading edge
7.

The Condition Code logic is on sheets 6

through 9 of IRC (IRCE - IRCJ). Refer
to Paragraph 1.5.

(drawing RACB). These signals (two pad write-enable and three pad address lines) gate the writing of

information

into

the

processor

general

registers.

The data is transferred into the registers by writing

1.1

MICROPROGRAM

ROM

AND

BUFFER

REGISTER
All control signals that are dependent only on the
machine state (i.e., that are not dependent on asynchronous signals or on data inputs) are derived
directly

from

the

outputs

the

microprogram

ROM. The ROM contains 256 68-bit words; during
cach processor cycle, one word is fetched from the
ROM and stored in a buffer register. The outputs
of the buffer register are transmitted to the other
modules of the processor to act as control signals

or to be used in combinational logic that generates
control signals for all processor operations.

them

with

the T1

pulse,

must

not

change

until

after

these enable signals
the

pulse

has

occurred.

One of the 6-bit output registers, shown on drawing
RACC, stores the output of bit 34 and of bits 32 -

28 of the ROM. Bit 33 is stored in a separate flip-

flop. This permits the buffer register to transmit
both polarities of USHCO00, with no additional sig-

nal

delays.

Bit

27 of the

ROM, which generates

UMSCO00, is also stored on a separate flip-flop to

generate both polarities.
The microprogram bits which are used to calculate
the new ROM address are used only on the RAC
module, so they are not brought to module pins.

However, several of the branch-enable signals are

The ROM is implemented by 16 256-word X 4-bit
read-only memories.

required either in both polarities or with greater fanout capacity: UBEFO03, UBEFO01, and UBEFOQ0 are

buffered by more than one gate.

I1-1-4

I
Ram
=TM

FEN
B

BEN

I U

UAD

WP U

14 | 13 | 12 |

c79
AMX

I
26

O
|

ceg

BSC

1o | oo | o8 | or | o6 | 05 | 0a | 03 | 02 | o1 | oo

c78

U I U

BMX

KMX

cet
ALU

N
23

19|

i
c75

c76

c77

SHC

BCT

34§

c78

MSC

32 | 31 | 30 | 29 | 28

]

c73

c74
BSO

c75

BAX

IBS

N
T9

450

| 39

PCA

PCB

c73

IRK

PWE

PAD

a5 | a4 | 43 | a2 | 4

50 | 49 | 48 | 47 | 46

c69

SRX

HEEE
63

| 62

c7or

DRX

NN
| 61

| 60

DRK

ccL

| s6

ce7

FPs | cLs

SSOETD

c71

SRK

cé6

c72

SHF

BRK | BRX

~Ti

| 54

ces

FPC

GTD_I 66 | 65 | 64
11-3448

c82
NOTE:
€82 = ROM IC type

Each 6-bit group: one 745174 register, except bits 66-64
which are clocked into a 745175 register.
Bits 27,33,67 are individual 74S74 flip-flops.

Figure 1-2

ROM Word: Clock, ICs and Registers

II-1-5

Table 1-1
Microprogram Bit Usage

Bit Positions

Contents

Clocked At

RACA

FP start (UFPS)

66
65-64
63
62

clear sync (UCLS)
Floating Point Control (UFPC)
bus register clock (UBRK)
bus register multiplexer (UBRX)

T1
T1
T2
T2

61-60
59-58

source register MUX (USRX)
destination register MUX (UDRX)

T2
T2

source register clock (USRK)

5655

destination register clock (UDRK)

54-52

condition-code load (UCCL)

51
50-49
4847

program counter A CLK (UPCA)
program counter B CLK (UPCB)
shifter control (USHF)

T2
T2
T2

instruction register CLK (UIRK)

RACB

45—-44
4341
40-39
38-37
36—35

pad write-enable (UPWE)
scratchpad address (UPAD)
bus delay (UBSD)
bus address multiplexer (UBAX)
internal bus (UIBS)

T1+15ns
T1+15ns
T1
T1
Tl

RACC

34-33

shift counter (USHC)

32-30

bus control (UBCT)

29-27

miscellaneous control (UMSC)

2624

bus conditions (UBSC)

23-22

A multiplexer (UAMX)

21-20
19-18

B multiplexer (UBMX)
constant multiplexers (UKMX)

T1
T1

17—-15

arithmetic logic unit cont (UALU)

RACD

14
13

fork C enable (UCFEN)
fork B enable (UBFEN)

not buffered
not buffered

fork A enable (UAFEN)

not buffered

11-08

branch-enable (UBEF)

not buffered

07-00

microprogram address (UADR)

not buffered

I1-1-6

1.2

FLOW DIAGRAMS

1.2.2

Glossary

The Flows are a description, in flowchart form, of

The symbols, abbreviations and terms listed below

the operation

occur on the Flow Diagrams and are also used in

of the KB11-C Processor.

Refer to

Figure 1-3. Each cycle, or machine state, is repre-

the text of this manual.

sented on the Flows by a rectangular box. The top

SYMBOLS

part of this box describes the operations executed
during the cycle. The bottom part lists the actual

operations that occur at each timing pulse.

(OP CODE).B - Refers to both the word and byte

The following information is supplied to aid in un-

e.g.: “NEG.B” means “NEG and NEGB.”

instructions,
derstanding and using the Flows:

when

describing

instruction

classes,

+ is used for a logical inclusive OR.

A note on timing (Paragraph 1.2.1).

* is used for a logical AND.

ANGLE BRACKETS

glossary of abbreviations and terms

(...)

Indicates operations

used on the Flows (Paragraph 1.2.2).

that are executed for diagnostic purposes only and

A definition of Instruction Classes (Para-

cycle.

are not necessary to the operation performed by the
3.

graph 1.2.3).

$ - Instruction dependent. See Chapter 2.
4.

description of Addressing

Modes as

they relate to operand fetch (Paragraph

ACKN - ACKNowledge:

1.2.4).

trap and abort flags when they have been serviced.

description

of the

Flow

Diagrams,

AFIR -

signal

that clear: certain

See IR

page by page, which explains in general
terms the use of the cycles on each page

ALU - Arithmetic Logic Unit. See Chapter 2.

(Paragraph 1.2.5).
BA 6.

Tables listing the cycles on each
used

each

instruction

Fork

Bus Address: Example: BA-PCB means that

the PCB is used as the address for a data transfer.

(Paragraph

1.2.6).

BC -

Bus Condition: defines the type of data trans-

fer that is to be executed; example: BC-DATI
1.2.1

ROM Timing

Refer

Figure

1-4.

The

ROM

address

RACL

BEND -

Bus

END:

aborts

data

transfer cycle

RADR(07:00) H is clocked into the ROM address

which cannot be completed because of an abort con-

dition (refer to Chapter 6) or one which was started

is clocked into the RBR at T1 - T2,

in the previous cycle and which is not required. See

Chapter 5.

NOTE
The KB11-C is controlled by the clock circuits de-

BR
-

scribed in Chapter 4, Timing Generator. For the pur-

data transfers: also used as temporary storage dur-

poses of this Chapter and of Chapters 2 and 3, it

ing instruction execution,

Bus

stores

data

received

during

must be known that there are two types of clock sig-

nals: the timing pulses, T1 - TS and the time states,

BRQ STROBE -

TS1 - TSS. The timing pulses are 15 ns wide and oc-

terrupts into the request register. See Chapter 6.

Signal which clocks traps and in-

cur at 30 ns intervals. The time states occur at the

same time as the timing pulse of the same number

BUS
-

Source of data

(TS1 occurs at the same time as T1) and are asserted

may

Unibus,

for 60 ns.

BR-BUS.

The timing pulse shown as ‘“T6” on the Flows occurs

BUS

at T1 ef the next cycle.

transfer. See Chapter 5.

II-1-7

PAUSE
-

during any

data transfer:

Internal

Bus or Cache; example:

Sccond

ROM

state of any

data

)

(F-ForK

Connector from

Condition for entry

BIN
¥

another page

67‘//2’-—‘__ into flows that follow

Sc7 2P
(@24)‘—2\
Name beffl/bfx WORD,; FIXUP SK.
Address of
ROM cycle
EDR TO POINT BE rond IMEX
Cycle
WORD IF SF7CR DF?

¢, BAePCE, BC—LATT

Ly SHFReACE 42
Cx BUS PAUSE

~SF7 SK&CGSLSFT
SF7:SR& SHFL

- OF7 - DRee—GOL DFT

next ROM

(D54)

]

Se7./p

cycle

00 IVDEXTNG ; FIX UP PC TO|.
ITNDEX WOX.

POINT BEYOND

t,(BAePCED>

Co SHFC.& SR+E8L
Ce

Se72%

)

cr74/)

(/47)

FETCH SBC; MO SL CHECK

Clock time

operations

S SHIAR
A
PCEE

}Description of Cycle operations
Operations executed during Cycle

tz KSHFR& FPCB>

are executed

JBUST: GRC DD

;:z 3o

[

?/:g

GET SecC

t, BR&SR ;8CeSEC) ORIT

Fork

Enable:

& PCA>
Ly (SHFR

Connector to

3 BRY 57'.6058[

-another page: may

L_V_J —

4 =C Fork

2 =B Fork

1= A Fork

be to Fork or Branch

2‘:’ eéués‘_fi;/(?fé o

/5_—-»(|rz~¢)8£m¢(3/7) -SM357

L o
é

S/3. 2@

32/

Page number (i.e., Flow 4)

[SRC ADORS 70 SE CINDIRECT))
¢, <BREPCE>
£y SHike BR

S/3 3

7743)

Condition for

2.5

Branch

fficgysez CRECAND 5 NO

SL e
BRSO BCESECE LRTL
1 CSHFR
- 2CE>
t,

U3 8UST;CRLYT

S/3.49

S5/3.4@

" BEN14: Branch
Enable #144
(317):

Base address

(/46

of next Cycle:

C/4¢)

final address

GET SRC QPERANO

¢, BRESL, BCESRCE DAL

depends on

conditions

ta CSHFREFCE>
23 BLQ STROBE

tx BUS PAUSE
te

BREZUS

FENE (377)

<5
Figure 1-3

11-3135

Flow Chart Symbols (P/O Flows 2)

I1-1- 8

~—FIRST ROM CYCLE

TH I

—

[ L

I
|

|
ADDRESS

e
—r

:4——-{ GENERATION

|
I

BITS
16:40

ROM

ACCESS

BITS
46:63

|
I
I

I
I

|
I

[ L
|
|

|
TIME P|

I
I

I
|

|
|

—/

T3H

SECOND ROM CYLE ———»

Té

T2H

»le

[
1

|
|

I
I

|
!

‘ ROM OUTPUT
e

RAR
CLOCKED

CLOCKED INTO
BUFFER (RBR)

RAR
CLOCKED

BITS 41:45
ROM OUTPUT
CLOCKED INTO

BUFFER (RBR)
11-3103

Figure 1-4

BUST -

ROM Timing

BU STart: first cycle of any data transfer.

DF
-

Sce Chapter 5.

BXX DISP -

Destination

Field:

bits 02:00 of instruction

word: this number is the address of a register.

The left shifted (multiplied by 2) and

DM -

sign extended value of the displacement field of a

word.

Destination Mode: bits 05:03 of instruction

branch instruction.
DR -

Destination Register: see Chapter 2.

CC - Condition Codes

EALU - Floating Point Processor (FPP) ALU.
CCLD - Condition Code Load
CHECK STACK LIMIT -

FC - FPP Cl1 line.

The contents of GD[6]

are checked to sce if there is a stack violation. See

Chapter 6.

FCC - FPP Condition Codes.
FDR - FPP Data Register.

FIRA - FPP Instruction Register.

CLEAR FLAGS -

Asserted when

UBCT =3: clears

the Address and Stack Error Flags. See Chapter 6.

FPA - FPP Address Register

CONF
-

FP ATTEN - Signals the FPP that data transfer is

CONsole

Flag:

causes

the processor

halt when set.

complete.

DATI -

cessor

Transfer of one word of data to the pro-

from

memory

from

Unibus

device.

SRCI. SRC2, KERNEL DATI. See Chapter 5.

DATO
-

Transfer of one word of data from the

processor to memory or to a Unibus device.

READ

DATA

Processor request for

FPP

data.
FPS - FPP Status Register.

FP START - Processor signal to FPP to initiate
operation,

I1-1-9

GD[X] - General Destination register. See Chapter
2. “X” designates the register number, e.g.. GD[4];
GD[DF] is the register designated by the Destination Field of the instruction word. The notation
“GD[X]” means that the register is read.

1.2.3

instruction will go next.

GR[X] - General Register: includes both GD and
GS when writing into these registers.

- General Source Register. See Chapter 2.
GS[X]
“X” designates the register number, e.g.. GS[4];
GS[SF] is the register designated by the Source
Field of the instruction word. The notation
“GS[X]” means that the register is read.
INIT - INITialization pulse (10 ms).

INTR PAUSE - INTerRupt PAUSE: the processor
stops and accepts an interrupt vector from the
Unibus. See Chapter 6.

IR,AFIR - Instruction Register which stores the instructon word.

Left Arrow («) - Signifies transfer of data to unit
on left from unit on right; example: BR~BUS, the
BR receives data from the BUS.

PC,PCA.PCB - Program Counter. See Chapter 2.
SC - Shift Counter. See Chapter 2.

SF - Source Field: bits 08:06 of Binary instruction
word; this number is the address of a register.
SHFR - SHiFteR. See Chapter 2.

SM - Source Mode: bits 11:09 of binary instruction
word.

SR - Source Register. See Chapter 2.

SRCCON - Value generated to modify the SR during auto increment or decrement addressing mode.

SV - Start Vector: address of a word that contains
the address that is entered on power-up. See Chapter 6.

SWAP(XX) - The SHFR moves the low byte into
the high byte position and the high byte into the
low byte position of the designated register.
TV - Trap Vector: address of a word that contains
the address of a subroutine that is entered after a
trap. See Chapter 6.

Instruction Classes

The instructions in the PDP-11 Instruction Set are
divided into classes by the decoding logic on RAC
and IRC. Some of these classes are used on the
Flows to determine the machine state to which an

During BSOP1 and BSOP2 data transfer cycles,
one of several types of bus cycles (DATI, DATIP,
DATO or DATOB) may be executed during a
given machine state. The type of bus cycle that is

executed during one of these machine states also depends on the instruction class. These instruction
classes are described as follows:

P/CLASS - Defines a group of instructions which
require a DATIP instead of a DATI cycle when obtaining the word which is to be operated on. This
allows for modification of the word without requiring memory to restore the word first during a
DATI and then again during a DATO. In addition,
it provides an interlock, i.e., the location cannot be
accessed by another device while it is being operated on. The following instructions are P/class:

00 03 DD
0050 DD
0051 DD
00 52 DD
00 53 DD
0054 DD
0055 DD
00 56 DD
00 60 DD
00 61 DD
0062 DD
00 63 DD
00 67 DD
04 SS DD
05SS DD
06 SSDD

SWAB
CLR
COM
INC
DEC
NEG
ADC
SBC
ROR
ROL
ASR
ASL
SXT
BIC
BIS
ADD

07 4R DD
1050 DD
1051 DD
10 52 DD
10 53 DD
1054 DD
1055 DD
10 56 DD
10 60 DD
10 61 DD
1062 DD
1063 DD
11SSDD
14 SS DD
15SS DD
16 SSDD

XOR
CLRB
COMB
INCB
DECB
NEGB
ADCB
SBCSB
RORB
ROLB
ASRB
ASLB
MOVB
BICB
BISB
SUB

I/CLASS - Defines a class of instructions which require a DATI during a BSOPI:

0057 DD
00 65 SS
02SSDD
03SS DD
07 OR SS

TS
MFPI
CMP
BIT
MUL

07 1R SS
10 57 DD
10 65 SS
12SS DD

DIV
TSTB
MFPD
CMPB

13SS DD

BITB

‘0O/CLASS - Defines a class of instructions which require a DATO during a BSP1: 01 SS DD MOV
and X0 66 DD MTP

I1-1-10

BIN(ayy) - All double-operand instructions; may require both source and destination calculations:

01 SSDD

02SSDD

03SS DD
04 SS DD
05SS DD
06 SSDD

MOV

11SSDD

BIT
BIC
BIS
ADD

13SS DD
14SS DD
15SS DD
16 SS DD

CMP

128SS DD

MOVB

CMPB
BITB
BICB
BISB
SUB

All
Calculation)
Address
DAC - (Destination
single-operand, register to destination or BIN*SMO
instructions:

always:

00 01 DD
00 03 DD
004R DD
00 50 DD
00 51 DD
00 52 DD
00 53 DD
00 54 D
00 55 DD
00 56 DD
00 57 DD
00 60 DD
00 61 DD
00 62 DD
00 63 DD
00 65 SS
00 67 DD
07 OR SS

JMP
SWAB
JSR
CLR
COM
INC
DEC
NEG
ADC
SBC
TST
RO
ROL
ASR
ASL
MFPI
SXT

07 1R S8S
07 2R SS
07 3R SS
07 4R DD
10 50 DD
10 51 DD
10 52 DD
10 53 DD
10 54 DD
10 55 DD
10 56 DD
10 57 DD
10 60 DD
10 61 DD
10 62 DD
10 63 DD
10 65 SS

DIV
ASH
ASHC
XOR
CLRB
COMB
INCB
DECB
NEGB
ADCB
SBCB
TSTB
RORB
ROLB
ASRB
ASLB
MFPD

MUL

E/CLASS - (Execute class) No address calculation
is required. These instructions use EXC.80 or
EXC.90 (Flows 3). In general, these are DAC*DMO
or BIN*SM0*DMO:

00 03 DD
0050 DD
0051 DD

SWAB
CLR
COM

06 SSDD
07 4R DD
10 50 DD

ADD
XOR
CLRB

00 52 DD
00 53 DD
00 54 DD
00 55 DD
00 56 DD
00 57 DD

INC
DEC
NEG
ADC
SBC
TST

10 51 DD
10 52 DD
10 53 DD
10 55 DD
10 56 DD
10 57 DD

COMB
INCB
DECB
ADCB
SBCB
TSTB

00 67 DD
01 SS DD
02SSDD
03 SS DD
04 SS DD

SXT
MOV
CMP
BIT
BIC

12SS DD
13 SS DD
14 SS DD
15SS DD
16 SSDD

CMPB
BITB
BICB
BISB
SUB

05 SS DD

BIS

00 60 DD
00 61 DD
00 62 DD
00 63 DD

ROR
ROL
ASR
ASL

10 60 DD
10 61 DD
10 62 DD
10 63 DD

RORB
ROLB
ASRB
ASLB

BSOPI1 - (BuS OPeration 1) When the ROM Bus

Condition (UBSC) equals 6 during a bus cycle
(data transfer), a DATO is executed for an O/class

instruction, a DATIP for a P/class or a DATI if
the instruction is neither O/class nor P/class. This
condition is shown on the Flows as BC—-BSOP1.

- (BuS OPeration 2) When UBSC=7 durBSOP2

ing a bus cycle, a DATOB is executed for a byte instruction and a DATO for a word instruction. This
condition is shown on the Flows as BCBSOP2.
J/CLASS - 00 01 DD JMP or 00 4R DD JSR -See
FJ/class.

if SMO:

01 SS DD
02SS DD
03 SS DD
04 SS DD
05 S DD
06 SS DD

F/CLASS - Floating Point Processor instructions

MOV
CMP
BIT
BIC
BIS
ADD

11SSDD
12SS DD
13SS DD
14 SS DD
15SS DD
16 SS DD

MOVB
CMPB
BITB
BICB
BISB
SUB

17 XX XX - See FJ/class.

FJ/CLASS - F/class or J/class, which require one
bus cycle less after the destination address calculation cycles than other DAC instructions (Flows 5
and 6).

I-1-11

1.2.4

NOTE

Addressing Modes and Operand Fetch

In the KB11-C, those FPP instructions whose bits
<11:06> = 0 are also classified as Mode 0 (CFCC,
SETF, SETI, SETD, SETL, op codes 170000170012). These are FPP Register operations. Refer

In general, the following steps are required for the
execution of an instruction:

Instruction Fetch: The instruction word
is read from memory. The PCB is used
as an address and a DATI is executed in
FET.10. The instruction word is stored
in the instruction registers (IR and

to Paragraph 1.2.5.2.

The mode determines how the contents of the register are to be used. Addressing is said to be:

AFIR).

DIRECT - when the contents of the register

Source Operand Fetch: This step is required only by BIN instructions whose
source mode is not 0 (-SMO0). This may
require up to three DATI bus cycles, depending on the addressing mode (refer

are the operand (mode 0);

DEFERRED - when the contents of the register are the address of the operand or the address of the address of the operand (modes 1

to Paragraphs 1.2.4.1 and 1.2.4.2).

- 5and 7);

Destination Operand Fetch: This step is

INDEXED - when the contents of the register are added to those of the word following
the instruction to obtain the address of the op-

required by all instructions that have a
destination operand when the destination mode is not 0 (-DMO0). Up to three

erand (mode 6).

bus cycles may be required, depending
on the addressing mode. Address word
fetches are DATIs; operand bus cycles
may be DATIs (I/class instructions),

Mode 7 is indexed and deferred. Modes 4 and 5
decrement the contents of the register by 2 before
address determination. Modes 2 and 3 increment
the contents of the register by 2 after the address

DATOs or DATOBs (O/class) or DA-

TIP/DATO(B)s (P/class).

determination.

Execution: After fetching the operand(s),
the operation specified by the op code is
performed. Execution may require several cycles or may be part of the destina-

Up to three bus cycles are required to obtain each
operand, one for each level of deferral, plus one for
indexing.

tion operand fetch.

NOTE

Programming documentation sometimes refers to the
contents of bits 05:00 of an instruction word as a
Source address. The KB11-C logic, however, treats
any operand field in bits 05:00 as a Destination address. For example, MFPI and MFPD are shown on
the PDP-11 Programming Card as 0065SS and
1065S, where “SS’’ indicates the source; these two instructions, however, are DAC and are executed as
such: the contents of the SS field (bits 05:00) are
used in the same manner as the bits 05:00 (=DD) in

PDP-11 instructions allow six bits for each operand
address. Three of these bits point to one of the general registers; the other three define one of eight addressing modes, 0 - 7, which are defined in
Paragraphs 1.2.4.1 and 1.2.4.2. The position of the
bits in the instruction word is shown in Figure 1-5.
Unary, or single-operand instructions require only

a destination (DST) address, located in bits 05:00.
Binary, or double-operand instructions require both
a source (SRC) and a destination address; the SRC
is located in bits 11:06 and the DST in bits 05:00.
BINARY OR DOUBLE

SOURCE

OPERAND INSTRUCTION (BIN)

an INC (0052DD) instruction.

REG

MODE

OP CODE

DESTINATION
I

UNARY OR SINGLE
OPERAND INSTRUCTION (DAC)
15

]

MODE

DESTINATION

[
OP

I
MODE

CODE

{

REG
1= 3104

Figure 1-5

Source and Destination Mode Formats

I-1-12

General Register Addressing — “R” is any

1.2.4.1

general register but register 7 (PC). The number of
bus cycles listed below for each mode is that required for operand fetch.

Mode

Name

Definition

AUTO-DECREMENT

The contents of Regis-

Symbolic: -(R)

ter R are decremented,
then used as the address

Mode

Name

Definition

Symbolic: %R

operand.

of the operand.
Example:

CLR -(3)=005043
One bus cycle is re-

Example:

quired.

CLR %3=005003

No bus cycle required.
1

DEFERRED

address of the operand.

AUTO-DECREMENT

The contents of register

DEFERRED

R are decremented by

Symbolic: @-(R)

a location which con-

Symbolic: (R)

tains the address of the

Example:

operand.

CLR (3)=005013

One bus cycle is

Example:
CLR @-(3)=005053

required.

2. The register then

contains the address of

AUTO-INCREMENT

Two bus cycles are re-

Symbolic: (R)+

address of the operand.

quired.

The register is incre6

mented after the

INDEX

The contents of register

Symbolic: X(R)

operand has been

R are added to the

word X to which the

fetched.

PC is pointing. This sum

is the address of the

Example:

operand.

CLR (3)+=005023

The word to which the

One bus cycle required.

PC is pointing is called

the INDEX word (engi-

AUTO-INCREMENT

DEFERRED

address of a location

Symbolic: @(R)+

which contains the ad-

(programming term).

dress of the operand.

This word may be the

neering term) or BASE

The contents of the

second or third word of

an instruction.

mented after its use.

Example:

CLR 100(3)=005063

Example:

000100

CLR @(3)+=005033
Two bus cycles are

Two bus cycles are re-

required.

quired.

II-1-13

Mode

Definition

Name

Definition

Mode

Name

INDEX DEFERRED

Same as Mode 6, except

Just before this instruction is fetched and executed, the

Symbolic: @X(R)

that the sum is the ad-

PC points to the first word of the instruction. The pro-

dress of a location

cessor fetches the first word and increments the PC by

which contains the ad-

two. The source operand mode is 27 (autoincrement the

dress of the operand.

PC). Thus, the PC is used as a pointer to fetch the
operand (the second word of the instruction) before

Example:

being incremented by two, to point to the next instruc-

CLR @100(3)=005073

tion.

000100

One bus cycle is required.
Three bus cycles are required.

ABSOLUTE
Symbolic: @#A

1.2.4.2

Program Counter Addressing - “R” is the

dress A of the operand,
instead of the operand

listed below for each mode is that required for oper-

itself,

and fetch.

Example:

CLR @#100 = 005037
000100

Modes 2, 3, 6 and 7 are also used with the PC as the
register. The machine sequence for obtaining the oper-

Two bus cycles are re-

and is the same in this case as that used when any

quired.

other register is used. Modes 0, 1, 4 and 5 are not illegal, but are of no practical use.

RELATIVE

Symbolic: A
Mode

Name

that the word that follows
the instruction is the ad-

PC (general register 7). The number of bus cycles

NOTE

Same as Mode 2, except

Relative mode is assembled
as index mode, using regis-

Definition

ter 7, the PC, as the index

IMMEDIATE

The PC, after the instruc-

address calculation, which

Symbolic: #n

tion fetch, contains the ad-

is stored in the second or

dress of the operand, which

third word of the instruc-

is the word contained in

tion, is not the address of

the memory location

the operand (as index

following that in which the

mode), but the number

instruction word is stored.

which, when added to the

The PC is incremented by

PC, becomes the address

of the operand. Thus, the
base is X-PC, which is
called an offset. The

Example:

operation is explained as

follows:

MOV #100,R0 ; MOVE 100(8) TO REGISTER 0
The operation of this mode is explained as follows:

Example:

The statement MOV #100,R0 assembles as two words.

If the statement MOV 100,R3 is assembled at absolute

These are:

location 20, the assembled code is:

012700

Location 20:

000100

Location 22:

4 (54 =100-24)

II-1-14

Mode

Name

Figure 1-6 shows the A and C Fork source and des-

Definition

tination calculation cycles. After the instruction has
obtained its operand(s) on these forks, it is exe-

The processor fetches the MOV instruction and adds two

cuted on the B Fork.

to the PC so that it points to location 22. The source
operand mode is 67; that is, indexed by the PC. To pick

1.2.5

up the base, the processor fetches the word pointed to

Flowchart Description

The KBI11-C Processor flowcharts (drawing D-FD-

by the PC and adds two to the PC. The PC now points

KB11-C-1) are divided into 14 drawings that illus-

to location 24. To calculate the address of the source

trate options of the flow. Where possible, a contin-

operand, the base is added to the designated register.

uous sequence of machine states is shown on a

That is, BASE+PC=54+24=100, the operand address.

single drawing. The succeeding paragraphs describe

Two bus cycles are re-

The description does not attempt to give detailed in-

the machine operations illustrated on each drawing.

quired.

formation about each machine state shown on the

RELATIVE

Same as Mode 6, except

DEFFERED

that the sum BASE+PC is

drawing; this information can be derived directly
from the flowcharts and the ROM map (Paragraph
1.3).

the address of a location

Symbolic: @A

which contains the address

Data Transfers

of the operand.

Data transfers require two machine states: a preliminary or BUST cycle, which sets up the conditions

Three bus cycles are re-

for the PAUSE cycle,

quired.

during which the data is

transferred. Data transfers are described in detail in
Chapter 3.

1.2.4.3 A and C Forks: Operand Fetch - After an
instruction has been fetched and decoded, the operand(s) are obtained from memory, if the addressing
mode is other than 0. The operation required by
the operation code is then executed.

1.2.5.1

Instruction Fetch

Flows 1 illustrates the instruction fetch sequence,
the address calculation sequence for five of the
source modes, a special sequence for the MTPI and
MTPD instructions, and the execution of the
branch type instructions.

The A FORK is used by all instructions:

Binary instructions that require source
mode calculation (-SMO0) calculate their
source address
operand.

Binary

Fetch States

The basic instruction fetch sequence requires two

and

fetch

the source

instructions

that

require

source address calculation (SMO0) and
single-operand instructions are DAC and
calculate

the

destination

address

and

machine states: FET.10 (fetch) and IRD.00 (IR decode). FET.10 completes a data transfer operation,
begun during the last cycle of the previous instruction, which moves the instruction word from an external storage location to the instruction register
(IR) and bus register (BR), and increments the pro-

Binary instructions with both SMO and
DMO, single-operand instructions with
DMO, and instructions that are not part

gram counter by 2. The instruction address is also
stored in the FPA (FPA<BA), if the FP11-C option
is present. If the data transfer is not overlapped
(i.e., if the transfer was not begun before the end of
the previous instruction), an additional state is required to begin the data transfer.

of any one of the classes listed on Flows
3 and 5 are executed.

The additional state, FET.00, also checks for as-

fetch the destination operand.

FLOWS 1

ynchronous operations (such as bus requests) that

The C Fork is used by F/class instructions or by
binary instructions with source mode other than 0
(-SMO) to calculate the destination address and to
fetch the destination operand after the source operand has been obtained on the A FORK.

must be performed before beginning a new instruction, and branches to BRK.90 (break) if necessary.
When the instruction fetch is overlapped, the ma-

chine state that begins the data transfer must also
perform the same check.

II-1-15

F/CLASS

DAC

BIN

sMg

-SMg

A FORK
F/CLASS

DAC % DM@

SM1

sM23

SM45

SM67

$13.00

$13,01

‘

$45.00

$67.00

{

(1)

DAC *-DM@

D12.00

A FORK
-E/CLASS

D12.01

DM3

030.00
(5)

(5)

(1)

FORK

DM45

(2)

DM&7

D45.00

D67.00

(6)

D45.01

D67.01

E/CLASS

(1,2,3)

A FORK

(DF7 + BRQ)

-(DF7 + BRQ)

EXC.90
(3)

EXC.80
(3)

DM@
% F/CLASS

(1)

A FORK

DM12

?wa

A FORK

FORK

DM@ x-F/CLASS

SR@(1)

-DMg@

SR@ (@)

SR@ (1)

SRE ()

DF7

-DF7

DF7

-DF7

DM12

DTB

DM145

DM67

FORS3

DO7.00

DO0O.80

DOT7.10

D00.90

DI2.90

D30.90

D45.90

D67.90

(4)

(5)

(6)

LEGEND:

SM: SOURCE MODE
DM:

DESTINATION

MODE

DF:

DESTINATION

FIELD

SR@(1): ODD BYTE ADDRESS

DM12

bM3

DM45

OM67

D12.80

D30.80

D45.80

D67.80

(5)

(6)

SR@ (@): EVEN BYTE ADDRESS

NOTE:

Numbers in parenthesis show page
of flows where cycle occurs.

Figure 1-6

(6)
11-3449

A and C Forks, General Case

II-1-16

Instruction Decoding

The NAND gate prevents the negation

IRD.00 begins a new data transfer that fetches the
word following the instruction word. This data

of BUST during IRD.00 when the cycle

that follows it is S67.00 (BIN*SM67,
Flows 2), if the destination mode of the
instruction is 1, 2, or 3. This cycle gets

transfer is used for address modes 6 or 7, and for
fetching the next instruction whenever the instruction being executed does not require other data

the index word for source mode 6 and 7
of a binary instruction. The PCB is used
here as the address and the bus cycle
started in IRD.00 is completed. The
NAND gate prevents BUST from being

transfers.

In some cases, the CONDITIONAL BUST is not issued, i.e., when a data cycle is required but the PC,
which is specified as the address in IRD.00, is not
the required address. In this case, for example
D30.00 (Flows 5), the DR is the address and a new
BUST is issued. CONDITIONAL BUST, which is
used only in IRD.00 (UMSC=5), and BUST are
controlled by RACH BUST H. Refer to drawing

RACH:

The four AND gates must be negated to assert
BUST.

inhibited if the destination mode of the
BIN instruction is 1, 2, or 3.
In

other

cases,

this

data

transfer

operation

aborted by a Bus End (BEND) operation in the machine state following IRD.00. During this machine
state, the processor also loads the source and destination registers (SR and DR) with the contents of
the general registers specified in the source and destination fields of the instruction; this operation is
also done in anticipation of the use of this data,

The top gate is negated when MCS=35

and in many cases the data loaded into the SR and
DR is ignored. However, when the data is needed,

or 7.

the anticipatory transfers allow the processor to op-

The three other gates are enabled when
MCS=5 (CONDITIONAL BUST in
IRD.00).

erate at maximum speed. The instruction word is
stored in the FIRA (FIRA«BR), if the FP11-C option is installed.

The second gate from the top is asserted,
and negates BUST during an IRD.00
that precedes S13.00 and S13.01

Source Modes 1 - 5

(BIN*SM123).

termined by decoding the instruction and certain

The A Fork logic is enabled during IRD.00 (FEN
1), so the machine state that follows IRD.00 is deother conditions. Six of the possible sequences that

The third gate from the top is asserted,
and negates BUST during IRD.00, if the
instruction is a Branch and if there is a
Brake Request (BRQ TRUE). FET.00,
which is a BUST cycle, follows IRD.00
in this case.

The last gate prevents BUST from being
asserted during an IRD.00, if this cycle
precedes the three cycles that calculate
destination modes 1, 2 and 3 on the A
Fork (D12.00, D12.01, DAC*DM12; and
D30.00, DAC*DM3; all on Flows 3J).
These cycles fetch the destination operand but use the DR as the address, instead of the PCB used by IRD.00.

follow IRD.00 are shown on Flows 1. These include the beginning of the data fetch sequence for
all binary instructions that have a source mode of 1
- 5. If the source mode is 1, 2 or 3, the external
data transfer is restarted with a new address and
the incrementation of the source register is started
for modes 2 or 3. If the source mode is 4 or 5, the
external data transfer can not be started until the
address has been decremented, so S45.00 performs
a BEND. After performing the data transfer to
fetch the word addressed by the source register, the
sequence conditionally enables the C Fork logic. If
the source mode is odd, another data transfer is required to fetch the data addressed by the word just
fetched; otherwise the fork determines the next
state.

I-1-17

transfer to the sequence required for the current instruction, unless an indirect-indexed address requires a third data transfer. In the latter case, the
sequence continues through three machine states
that are common to the sequences of all indirect
source modes 3, 5, and 7, and in part to the MTPI

Move to Previous Space Instructions

For an MTPI or MTPD (Move To Previous) in-

struction, MTP.00 and MTP.10 read an address

from the stack pointer and begin a data transfer operation to fetch a data word that will be transferred
to the destination address. The flow then transfers

or MTPD instruction.

to the last state of the source-data-fetch sequence,
because this state is alike for both the MTP sequence and the normal source data sequence.

Floating Point Instructions

When a floating-point instruction is recognized by
the A Fork logic, the sequence is transferred to
FOP.00 (floating-point operation). In this state, the
contents of the Destination Register are stored in
the BR; in the following state (FOP.10) the contents of the BR are stored in the FDR. Thus, at
this point in the instruction execution, the instruction word, its address, and the contents of the General Register specified by the instruction are all

Branch Instructions

For branch instructions, the A Fork logic determines whether the branch is successful, and if not,
whether a bus request has been sensed. If the
branch is successful, the PC must be changed before the next instruction is fetched; this is performed by the BXX.00 - BXX.05 (branch) machine
state which aborts the previous data transfer. This
state also strobes any new bus requests. The BRQ
STROBE must be performed in the state preceding
the state that starts the instruction fetch; this includes FET.10 (in case the A Fork logic returns

stored in the FPP.

The instruction flow then goes to the C Fork logic

control directly to FET.00), the next-to-last state of
instructions that overlap the instruction fetch, and
the last state of instructions that do not provide

to perform the address calculation:

overlap. The machine state following BXX.00 is

= 0. CFCC, SETF, SETI, SETD and
SETL), the next cycle is FOP.50 (Flows

FET.00.

If the branch is not successful and no bus requests

4);

are sensed, the instrucion fetch continues the data
transfer begun in IRD.00; if a bus request is sensed,

the sequence returns to FET.00, which in turn trans-

fers the sequence to BRK.00. Table 1-3E lists the
ROM words used by each branch instruction for

dress calculation cycles as the processor

RTI and RTT Instructions

The RTI and RTT instructions differ only in the
clocking of T bit traps after the data transfers, so
the sequence of machine states is identical. This sequence performs two data transfers to restore the

FLOWS 2

Indexed Source Modes and Operate Instructions
Flows 2 illustrates the sequence of machine states
for the data fetch for source modes 6 or 7, for the
transfer of floating-point instructions to the FPP,
and for the execution of five operate instructions.
Indexed Source Modes

For -DMO, the FPP uses the same adinstructions.

the four possible sequences.

1.2.52

For DMO (which also includes FPP op
codes 170000-170012, whose IR<11:06>

previous PC and PS words from the hardware
stack, and performs two increment operations on
the stack pointer. The sequence then continues with
an instruction fetch.

For BIN*SM67, the indexed source modes for
binary instructions, the transfer begun in IRD.0O is
completed and an increment from the source register is added to the data word; the resulting data
word is used for a second data transfer. When this
transfer is complete, a conditional fork is used to

RTS Instruction

The RTS sequence performs one register-to-register

transfer and one external data transfer to restore

the PC and the specified register, and updates the
Stack Pointer (SP) after the transfer. The sequence
then returns to the instruction fetch machine states.

II-1-18

SOB Instruction

Multiply and Divide with Destination Mode 0

The sequence of machine states for the SOB instruc-

For the multiply and divide instructions, a special

tion first generates a new PC value, based on the

sequence is used when the destination mode is 0. In

offset in the instruction, and then restores the old

either case, this sequence precedes the normal se-

PC value if the value in the specified register will be

quence for that instruction. MUL.80 (multiply) sets

0 after decrementing. This is done because the test

up the step counter and transfers to MUL.10, be-

on the value of the register requires one machine

cause MUL.OO is used to complete the data transfer

state in every case, which can be combined with the

begun

calculation of the new PC value, and because the

DVS.00 (divide start), the contents of the register

branch is successful most of the time; thus, the ex-

specified for the destination operand are transferred

tra machine state to perform the restoration of the

to the BR, which corresponds to the result of the

old PC value is executed less often than if an extra

data fetch sequence for other destination modes.

the destination data fetch sequence.

state were required when the branch is successful.

The SOB sequence initiates the fetch of the next in-

E/Class and Negate Instructions

struction during the last machine state, which also

For

performs the decrement on the specified register.

data, one machine state is required to perform the

the majority of instructions that operate on

data manipulation. If both the source (if any) and
destination modes are 0, the data is already in the

MARK Instruction

The machine state sequence for the MARK instruc-

SR and DR registers as a result of IRD.00. The

tion transfers the contents of general register 5 to

data manipulation (selected by the subsidiary ROM

the PC, transfers the top word on the hardware

for all except the NEG.B instruction) is performed,

stack to register 5, then begins fetching the next in-

the data is stored in the general register specified by

struction. The operation of the MARK instruction

the destination field, and the sequence returns to

assumes that the instruction has been fetched from

the instruction fetch. The NEG and NEG.B instruc-

the top of the hardware stack; for a discussion of

tions require two machine states because the com-

the purpose and effects of the MARK instruction,

plement

sec Chapter 4.

performed on the data during the same state; there-

and

increment

operations

cannot

fore the external data transfer operation started in
1.2.5.3

IRD.00 is aborted (a bus operation cannot be car-

FLOWS 3

ried across more than two machine states) and the
No Memory Reference Execution

sequence returns to FET.00. The other instructions

Flows 3 illustrates the machine state sequences for

complete the data operation and return to FET.10,

a variety of instructions that do not require mem-

unless a bus request has been sensed; because the

ory references other than the instruction fetch. A

transfer to the BRQ service sequence is performed

number of sequences are shown that transfer imme-

by FET.00, the bus operation must be aborted.

diately to machine states on other pages; they are
shown only to illustrate the routing from A Fork to

RESET Instruction

these states. These sequences include the breakpoint

Three

processor

trap (OP3), 10T trap, the EMT and TRAP traps,

HALT

and

and several groups of reserved op codes, including

shown

OP7,

transfers general register 0 to the DR so that the

OP22,

and

RSVD. The illegal instructions

JMP or JSR, with destination mode 0, also transfer
directly to a point in the trap sequence. The four in-

contents

structions ASH,

then

ASHC,

MFPI,

and

MFPD

are

this

control

WAIT,

are

drawing.

RO can

instructions,
executed
The

RESET,

sequences

RESET

instruction

be displayed

the

DATA

lights of the console during the reset operation, and
triggers

the

initialization

pulse.

The

in-

shown on other pages which do not show the A

itialization is inhibited if the processor is not oper-

Fork flow line; therefore, off-page connectors are
shown on this drawing for these instructions with
destination mode O (for other destination modes of

ating

these instructions, the sequence transfers to the destination address calculation sequences shown on

pulse (which lasts for 10 ms) is completed, and then

Flows 5 and 6).

sequence.

the

Kernel

instruction is, in effect,

mode;

this

case,

the

a NOP. The machine state

that triggers the pulse recycles to itself until

rcturns

I1-1-19

the

sequence

the

instruction

the

fetch

HALT Instruction

For all

The HALT instruction does not actually stop the

tions, these sequences correspond to, or join, the se-

processor; instead, control is transferred to the con-

quences

sole service sequence, which waits for manual inter-

destination modes are 0.

vention

determine

further

operations.

This

instructions except floating-point instrucused

when

both

the

source

and

the

performed by setting the console flag and then re-

Not Register 7

turning to the instruction fetch sequence where the

When the destination specification in an instruction

console flag generates a BRQ, which in turn trans-

refers to any general register other than register 7

fers to the break service sequence. The console flag

(the

is set only if the processor is in

Kernel mode; a

quences shown on this drawing are met, the instruc-

branch after HLT.10, (HALT) transfers control to

tion is executed by D00.90 (destination mode 0). If

the trap service sequence if the processor is not in

the source address is odd, a byte-swap operation

Kernel mode, i.e.,

a HALT instruction in Super or

User modes traps through location 4.

PC),

and

the

other

conditions

for

the

se-

must be performed on the contents of the BR before

the

operation.

instruction-dependent

data

manipulation

If the source mode is also 0, no byte

WAIT Instruction

swap 1s required, and the execution is performed by

The WAIT instruction is used to wait for an asynch-

the EXC.8 (execute) machine state.

ronous condition that either initiates the execution

of a service program or enters the console service se-

quence. The basic wait loop consists of two ma-

When the destination register is 7, the PC is modi-

chine states, so that the BRQ STROBE in one state

fied. Because the PC is stored as a separate register

is available for the branch in the other state. When

(not in the general register set), the execution is ac-

any BRQ is sensed, the sequence goes to the first of

complished by EXC.90, which requires the source

two states that test for console requests and then

data to be in the SR register.

for interrupts or traps (other than T bit traps) that

therefore required to transfer the source data from

supply vectors. If neither is found, the sequence re-

the BR to the SR. A byte swap can be combined

turns to the wait loop; otherwise, control is trans-

with this transfer, if necessary.

A machine state is

ferred to the appropriate sequence.

Floating-Point Instructions
Processor Status Change Instructions

FOP.50

Two types of instructions that transfer data from

DMO*F/CLASS

the instruction word to the PS word are the CCOP

Condition Code and accumulator to accumulator
operations, as well as FPP writes to the processor

instruction and the SPL instruction. The former af-

the

Fork

instructions,

cycle

which

used

all

include FPP

fects only the condition code bits [PS(03:00)] and
the latter affects only the priority bits [PS(07:05)].

general registers.

In the CCOP instruction, the external data transfer
begun by the IRD.00 state is aborted because the

This sequence reads the FPP Status Register into
the BR. If BRQ is true, a branch to FOP.60 is exe-

processor must maintain the data in the BR register

cuted. In this cycle, the address of the FPP instruc-

until the PS word is reloaded. In the SPL instruc-

tion is read into the BR; then, in FSV.90 (Flows
13), it is written back into PCA and PCB, and con-

tion, the first state does the actual transfer to the
priority. The second state also begins a new instruction fetch and control transfers to FET.10. SPL is a
no-op (no change to the PS) unless the processor is

in Kernel mode.

trol is transferred to the service routine (BRK.00,
Flows 12). The FPP instruction is aborted at this

time and its address is saved. This same instruction
will thus be fetched again and executed after the service routine.

1.2.5.4

FLOWS 4

Destination Mode 0 Sequence
IFlows 4 illustrates the five sequences used when the
destination mode is 0. These sequences are entered
through the C Fork microprogram address calculation; this fork is used to determine the next machine state after a source operand has been fetched.

FOP.30 repeats FOP.50 and waits for FP SYNC. If
BRQ is true, control is transferred to the service
routine as described above. If FP SYNC is re-

ceived, FOP.40 is executed.

FOP.30 cycles upon itself until either of these conditions is true.
FOP.45 instructs the FP11-C to execute the instruc-

tion (FP START).

I1-1-20

In the case of a CFCC, the FPP Condition Codes are written to the PSW from
the BR.

This is the only difference between D12.80 (destina-

If the instruction requires a write into a

JSR, and floating-point instructions, and instruc-

processor

REG

tions that transfer the source operand to the destina-

WR), the data is read into the BR in

tion unchanged (specifically, the MOV, MTPI, and

tion modes | or 2) and D12.90. After one of these
states or D12.00 has been completed, the processor
performs

General

(FP

three-way

branch,

separate JMP,

FOP.65 then transferred to GR[DF] dur-

MTPD instructions) from all others. For floating-

ing FET.08, as the next instruction fetch

point

is started.

aborted, and the sequence continues through the B

If the instruction does not require a
write into a processor general register,

tions, the sequence is directed to JMP.00; for JSR

the instruction is done and control is

(0 Class) instructions, the external transfer is forced

instructions,

the

external

data

transfer

Fork decision point to FOP.40. For JMP instruc-

transferred to FET.06.

instructions, to JSR.00. For the three direct-transfer

to be a DATO instead of a DATIP or a DATI,
and the transfer is completed before an instruction-

1.2.5.5

FLOWS S

dependent, condition-code load

operation

is per-

formed. The last machine state in the sequence for

Destination Modes 1 - 3

0 Class instructions also begins the instruction fetch

Flows 5 illustrates the machine state sequences used

for the

to fetch data specified by destination modes 1, 2, or

ronous conditions requiring service.

instruction

and

checks

for asynch-

3. These sequences are entered from one of the two
forks: some are entered from the A Fork decision

For all

point, for instructions which either do not require a

transfer is completed, and the B Fork logic is condi-

source operand or have a source mode of 0, while

tionally enabled in D12.10. If a byte swap is needed

others are entered from the C Fork decision point

because the destination address is to an odd byte,

after

the

source

operand

has

been

fetched

and

other instructions, the

DATI

DATIP

the extra machine state D12.30 is entered, and then

the B Fork decision point. Note that in all three of

placed in the SR.

the
Sequence Entry

sequences

shown

(in

DI12.60,

DI12.10,

and

D12.70) the destination register is incremented by a

All six sequences on this drawing start a data cycle

constant which can be either 0, 1, or 2, depending

(BUST).

on the address mode and whether a word or a byte

should

noted

that

the

CONDI-

TIONAL BUST in IRD.0O0 is not asserted when the

operand is being fetched.

two A Fork sequences on Flows 5 are entered; this

is because the PC is not the address required for

Destination Mode 3

the

The three sequences for destination mode 3 all en-

DM 123 data cycles on this drawing.

ter D30.10 (destination mode 3), which completes
The four sequences entered from the C Fork deci-

the data transfer, increments the destination register

sion point also start by transferring the contents of

by the necessary amount, and transfers to D10.20,

the BR to the SR, so that the source data is avail-

which begins the fetch of the operand addressed by

able in both registers; the opposite transfer is per-

the word just transferred. Because the first transfer

formed for the A Fork entry to move the source

during a destination mode 3 sequence can only be a

data to the BR for the DATO that follows the desti-

full word, the increment used in the register update

nation address calculation. If the destination is 3,

is always 2, not 1.

there is no point in loading the BR from the DR because the address fetched by the first external data

1.2.5.6

FLOWS 6

transfer is stored in the BR for use in the next data

{ransfer.

Destination Modes 4 — 7

Destination Modes 1 and 2

arc used to fetch the destination operand when the

Flows 6 illustrates six machine state sequences that
There are two entries from the C

Fork decision

destination address mode is 4, 5, 6, or 7. These six

point for address modes 1 or 2 because the source

sequences correspond to the six sequences for ad-

data may be an odd byte which must be swapped.

dress modes 1, 2, and 3.

I1-1-21

external data transfer, using the contents of the PC
as an address, and performs an increment operation
on the PC. The entry from the A Fork decision
point continues the transfer begun by the IRD.00
machine state, so this entry is to D67.00 (destination mode 6 or 7) that follows the first state for the
other entries. D67.10 adds the contents of the DR
to the data read into the BR, thus performing the
indexing operation, and then transfers to a machine
state in the flow sequence for destination modes 4
or 5. The transfer is to D10.30 (a state also used

Modes 4 and 5 require that the contents of the destination register be decremented before the value is
used in the external data transfer. They are treated
by one of three sequences. Modes 6 and 7 use general register 7 (the PC) first and then use the destination register. They are treated by one of three
sequences.

In either case, two of the three sequences are entered from the C Fork and one from the A Fork.
The two C Fork entries differentiate between
source operands that require byte swapping and
source operands that do not. There can be no re-

quirement for a byte swap on the A Fork entry, because the source operand would be address mode 0
and the high byte of a register cannot be specified.

for mode 4) if the mode is 6, or to DI10.10 (a state
also used for mode 5) if the mode is 7. The shared
sequences perform the remaining one or two data
transfers to fetch or store the actual data word.
Ending Sequence

C Fork Entries for Modes 4 and 5

When the last data transfer has been started, all six
scquences enter a combined conditional fork and
two-way branch that selects the next machine state.
For 0/class instructions (MOV, MTPI, and MTPD)
the last data transfer is a DATO operation, which

word operation. Byte operations in mode 5 use a

condition codes. The processor then returns to the

D45.80 (destination mode 4 or 5) and D45.90 differ
mainly in the microprogram addresses contained in
the microprogram word. Each state decrements the
DR by the value of the destination constant, which
is 1 for a byte operation in mode 4, and 2 for a
constant of 2 because the data fetched from the address taken from the DR is in turn used as an address and must be a full word. The state following
D45.80 or D45.90 begins the external data transfer,
which may be a DATI, DATIP, or a DATO, de-

pending on the specific instruction. D40.30 and
D50.30. which follow D4590, also perform the
byte-swap operation on the source operand. In each
of the two sequences, a different path is taken for
destination mode 4 where only one data transfer is
needed, than for destination mode 5 where a second transfer is needed. The second transfer is performed by a sequence that is common for address
modes 3, 5, and 7; this sequence transfers the first
word that is fetched from the BR to the DR and

then

uses the

as the address

for a second

transfer.

is completed by D10.40; this state also loads the

instruction fetch sequence. For all other instruc-

tions, the DATI or DATIP transfer is completed in
D10.60, leaving the destination data in the BR and
the source data in the SR, and the B Fork logic is
conditionally enabled. If a byte-swap operation is
required for the destination data, D12.30, which
performs this operation for all destination modes |
- 7. is entered. FJ/Class instructions go directly to
the B Fork.
1.2.5.7

FLOWS 7

ASH, ASHC, and Floating-Point Instructions
FFlows 7 illustrates the machine state sequences for

the Arithmetic Shift (ASH) and Arithmetic Shift
Combined (ASHC) instructions, and the first machine state of the floating-point instruction service
after the destination address calculation.

A Fork Entry for Modes 4 and 5

D45.00, which is entered from the A Fork Decision
point, is similar to D45.80 and D45.90, except that
a BEND is performed to abort the transfer begun
during the IRD.00 machine state. The sequences
that follow D45.00 are similar to the sequences that
follow D45.80 or D45.90, except that the source op-

erand, if any, is already in the SR.
Destination Modes 6 and 7 Entry
For address modes 6 and 7, the first machine state
entered from the C Fork decision point begins an

ASH Instruction

When the machine state sequence for the ASH instruction is entered from the B Fork decision point,
the destination data is in the BR register. The six
lcast-significant bits of the destination word are
used as a 2’s complement number which is the shift
count for the instruction. The DR is loaded from
the BR and this data is then loaded into the Shift
Counter (SC) from the DR in ASH.10. In an
ASH.20, the condition codes are loaded, based on
the value of the word in the source register, and the

I1-1-22

SC is tested for a 0 shift count. If the shift count is
0, the instruction is completed, and the processor returns to the instruction fetch sequence; otherwise,
one of two states is entered, depending on the sign
of the shift count. ASH.30 (Arithmetic Shift) and

ASH.40 perform the actual shift one bit at a time,
and increment or decrement, respectively, the shift
counter. These states also load the condition codes

with the results of each shift, so that after the last
shift the codes are correct, and test during each
cycle to determine whether any further cycles are re-

Floating-Point Instructions
When the B Fork logic decodes a floating-point instruction, FOP.40 (floating-point operation) is enThis state aborts the last external data

tered.

transfer

started

BRQ true: Control is transferred to
FSV.70 (Flows 13). In this cycle and the
two that follow it, the original DR and
PC are read back from the FP11-C and

the DR, PCA and PCB are restored to
the state in which they were prior to the

in ASH.30 or ASH.40 is performed with the SC=0,
and the final value in the SC is -0 (all 1s).

FPP instruction fetch. The service flows
(BRK.00 through SVC.90), and the inter-

ASHC Instruction

rupt subroutine are then executed; the

The ASHC instruction operates in a manner similar

FPP instruction is then fetched and exe-

to the ASH instruction. The difference is that two
words of data are shifted. ASC.00 and ASC.10 perform the same functions as ASH.00 and ASH.10,
in addition, load the DR (after the SC has

and

cuted again.
2,

been loaded from the previous value in the DR)
with the contents of a general register which is selected by ORing the destination register specifica-

OR produces the number of the next higher numbered register.
ASC .20 performs the first change of the SC, moves
the first data word to the BR, loads the condition
codes, and tests for a 0 SC, just as ASH.20 does.
However, if the SC is 0, the sequence continues

~(SYNC+BRQ):

The processor cycles
on FSV.60 (Flows 13) until it receives ei-

ther an FP SYNC or a BRQ. In this last
case it executes the sequence described in
(1) above. In the first case (FP SYNC) it

tion with 1. When the destination register specified
by the instruction is an even-numbered register, the

executes the sequence in (3) below.

SYNC+-BRQ: FSV.10 is entered. In
this state, a bus cycle is started, whose direction (DATI or DATO) is determined

by FC (BC<FC).

with ASC.80 (arithmetic shift combined), instead of
returning immediately to the instruction fetch sestate

required

se-

destination data, to the BR. A three-way branch is

formed in ASH.20; all tests are done on the value
before any changes are performed, so the last cycle

This

the destination-data-fetch

then entered:

- quired. Note that the first change to the SC is per-

quence.

quence, and sends the destination address, not the

four 16-bit words are transferred
by the FSV.10-FSV.70 loop.

test the second

data word, so that the Z condition code can be set
on the contents of both words. ASC.80 also starts

If the instruction is not a Floating
Pause Class (FPCLASS), up to

If the instruction is FPCLASS, this

the next instruction fetch, so the processor transfers

loop

to cither FET.10 or

FSV.30, FSV.40 and FSV.50 which

BRK .00 rather than FET.00.

cause
If the SC is not 0, ASC.20 is followed by ASC.30
or

ASC.40.

These states

perform

the

same oper-

ations as the corresponding states for the ASH in-

expanded

the

loop

include

execute

read/modify/write

operation.

FPCLASS

are ABSX

instructions

and NEGX.

struction, and also cause shifting of the DR (which

can be shifted internally, without passing the data
through the ALU or SHFR). The bit shifted into
the

is selected by processor hardware. When

the

does

reach

SC.60.

which

performs

the
the

machine state is

same

operationsas

ASC .80, but also stores the second word from the
DR into the appropriate general register.

I1-1-23

After the CPU completes this loop, it executes

FSV.20

where

can

copy

the

floating condition codes in the FP11-C,
if desired. From this state, the CPU sequences to FET.07 to start the next in-

struction fetch.

1.2.5.8

Note that correction of the product is required

FLOWS 8

when the DR (multiplicand) is negative.
Multiply Instruction

In Case 1, where both SR and DR are positive, the
product is correct and no correction is required.

The sequence of machine states shown on Flows 8
performs a multiplication operation on two words
of data, one from a general register and the other
in a word specified by the destination field and fetched into the BR. The results of the multiplication
are stored in two general registers: one is the register spccified in the instruction, and the other is a

In Case 2, 2*2 X DR must be subtracted, but since
the product is only 32 bits wide, this term is out of
range and no correction is required.

In Case 3, 2'¢ X SR has to be subtracted from the
product, as this term is within the 32-bit product

the number of the specified register (Figure 1-7). If

formed in the BR and DR.

the specified register has an odd number, only one

In Case 4, the first two terms are out of range, and
216 X SR must be added to the product. Since in
this case the SR is a 2's complement negative number, the addition is accomplished by subtracting it

SR (MULTIPLIER)

(SIGN OF SR
OR

SIGN OF BR) I

as in Case 3 (- - = +).

BR (PRODUCT)

The multiplication sequence begins with two ma-

HDR (MULTIPLICAND)

chine states that set up the four registers (BR, SR,
DR, and SC) used in the sequence, and performs

the first test and shift on the DR. Note that all
Figure 1-7

branches refer to the state of the DR and the SC at

Multiply Instruction

the beginning of the machine state preceding the
branch, not the values in the registers at the end of

The multiplier is in the SR, the multiplicand in the

that state. This is because the RAR is clocked at

DR. and the 32-bit product is formed in the BR

T3. The operand supplied by the destination-datafetch sequence is loaded into the DR, and the SC is

and DR by an add and shift algorithm.

loaded

The multiplier (SR) is used as a 32-bit, not a 16-bit,

with

the

octal

value

(decimal

15)

MUL.00 (multiply).

2's complement number. This is accomplished by ex-

tending its sign bit into the BR after every shift.
The multiplication thus has as its operands a 16-bit

In MUL.10, the BR is cleared; the other operand is
in the SR as the result of IRD.00. The SC is

multiplicand, the DR, and a 32-bit multiplier, the

decremented.

SR.

Fifteen multiplication cycles are then performed in
MUL.20 and MUL.30.

In 2’s complement notation, a negative 16-bit num-

ber (-A) is equivalent to (2'° -A), and a negative 32-

If the low order bit of the DR is

bit number (-B) to (2* -B). When a combination of

[DRO(1)], the SR is added to the BR

16- and 32-bit positive and negative numbers are

and both BR and DR are shifted right

multiplied, four conditions are possible, as shown

in Table 1-2.

product (MUL.20).

combined shift,

which forms the

Table 1-2

Sign Correction for MUL Instruction

Case

SR | DR | Representation of
SR
DR

=20 [ =20

|SR

3
4

20 | <0
<0 | <0

[SR
216-DR | 2!5SR-(SRXDR)
-(SRXDR) [ -2'¢SR
[232-SR | 2!6-DR | 2%8-232DR-2!SSR+(SRXDR) [ (SRXDR)
+216SR

<0 | >0

|2%2-SR | DR

(SRXDR)

Product
Correction
Should Be: | Required

Product Generated
(2" SR X DR)

232DR-(SRXDR)

I1-1-24

(SRXDR)

None

-(SRXDR) | None

If the low

order bit of the DR is 0

into two words; during division, the max-

[DRO(0)], the shift is performed, but no

imum result occurs when the largest pos-

add (MUL.30).

sible number is divided by a very small

number and the result does not fit into
At the end of these fifteen cycles, SC=0 and DRO

any reasonable number of words. There-

contains the sign bit of the multiplicand (DR).

fore, the division algorithm must recognize

If DRO(1), the multiplicand was negative
and correction is required. MUL.50 sub-

tracts the multiplier (SR) from the high

the

smaller

than

the

divisor;

the last reduction passed through O and

DRO(0).

correction

changed the sign of the remainder. This

required

condition

(MUL.40).

called

underflow

and

re-

quires that the results of the last reduc-

MUL.50 or MUL.40 store the more-significant half

of the result into the register specified by the source
field, and set the condition codes on the value of
this word.

tion be restored in some way.
The simplest division algorithm is to subtract the
divisor from the dividend until underflow occurs, re-

store the remainder, and keep a count of all but the

MUL.60 stores the less-significant half of the result
in the register, whose number is formed by ORing

the source field with 1; if an odd register is specified, this value replaces the more-significant half of
the result, which is lost. This is done because many
multiplications produce a result which can be contained in only one word, and this result is preserved

by this action. The condition codes are altered to
represent the value of the entire result; if all 32 bits

are 0, the Z bit is set, and if the result cannot be

contained in one word, the C bit is set. At the end

of this cycle, the sequence returns either to the instruction fetch sequence, or, if an asynchronous conneeding

service

was

sensed

the

BRQ

STROBE in machine state MUL.40 or MUL.50, to

the break service sequence.
1.2.5.9

when

usually this is done by recognizing when

product.

dition

condition

During the division process, it is necesmainder

same as subtracting 2!'¢ X SR from the

overflow

sary to recognize when the partial re-

order product (BR and DR). This is the

the

quotient is too large.

last subtraction for the quotient (this algorithm assumes all positive numbers). This procedure is very
tedious, particularly if an overflow condition exists,

so a shorter algorithm is used that is based on the
positional representation of numbers.
The result of the division is a quotient that can be
multiplied by the divisor to regenerate the dividend
(with a difference equal to the remainder). If, during the multiplication, each bit of the quotient can
generate a partial product that becomes part of the

total sum, then during the division, each bit of the
quotient can be generated individually while reducing

the

partial

remainder

appropriate

amount. To determine what the most-significant bit

of the quotient should be, the number that is subtracted from the dividend is equal to the divisor,
multiplied by the positional value of the most-sig-

FLOWS 9 and 10

nificant digit.

The Divide Instruction

Figure 1-8 illustrates the division algorithm. At the

Division is the process of counting the number of

beginning of the division, the dividend occupies all

times one number (the dividend) can be reduced by

of a word register. The divisor has been multiplied

another

The count of the

by 2 to the nth power, so that the number which is

number of reductions is called the quotient; the

first subtracted from the dividend is actually the

number (the

divisor).

part of the dividend that cannot be reduced by the

divisor times the positional value of the most-signif-

divisor is called the remainder.

icant bit. Before each step of the division, the divi-

complicated

than

Division is more

multiplication,

for

several

sor is divided by 2, so that the correct number for
generating the next bit of the quotient is formed;

reasons:

the division by 2 is done by shifting the 2-word divi1.

Division produces two results, not one.

sor 1 bit to the right. In order for the division algorithm

operate

with

negative

numbers,

the

During multiplication, the maximum re-

reduction that is performed at each step of the divi-

sult occurs when the maximum number

sion must be the correct operation to reduce the re-

mainder;
if the divisor and the partial remainder

multiplied

itself.

This

result fits

I1-1-25

)

owie

LOAD DD
LOAD HIGH HALF
OF DR AND CLEAR
LOW HALF

CLEAR Q
SHC «—N

YES

Lavena
>

| DD*——DD+DR4]

rgaDt——DD—DR J

DDZN=DR2N

DDon=DR2N

YES

Qe—Q¥%240

Qe—Q¥2+1

{(SHIFT

(SHIFT LEFT)

LEFT)

]

DR<«—DR/2

(SHIFT RIGHT)

-1
SHC «—SHC

DD2N=

S|V l

ORIGINAL

YES

SHC

OD«+—DD+DR

]
LEGEND:

DD=DIVIDEND

(REMAINDER iS DD <N-1:0>)

DR=DIVISOR
Q=QUOTIENT
SHC=SHIFT COUNTER

ODon=DRopN

YES

(

DonE

Qe—o+1

)
11-1070

Figure 1-8

Divide Algorithm

I1-1-26

(that is, the dividend) have the same sign, the divi-

sor is subtracted from the remainder, but if their
signs differ, the divisor is added to the remainder to

cycle of states that perform the actual division.
Flows 10 shows the quotient and remainder sign

reduce its magnitude.

corrections and the final overflow test.

The algorithm that is illustrated does not perform a

The division is performed by a non-restoring divide

restoration if an underflow condition occurs. In-

algorithm that is described above. The hardware im-

stead, while underflow exists, succeeding operations

plementation (Figure 1-9) uses the SR to hold the

are performed in the opposite manner to complete

divisor and begins with the dividend in the BR and

the restoration; while an underflow condition exists,

DR registers. The BR contains the more-significant

the bits of the quotient are set only when the under-

half of the dividend, while the less-significant half is

flow is corrected and are cleared if the operation

in the DR. Each cycle of the division shifts the divi-

does not complete the restoration. If the original

dend one bit to the left and shifts the next bit of

the

the quotient into the least-significant bit of the DR.

quotient should be negative, so bits of the quotient

When the division terminates, the quotient is in the

depend on the operation performed and its results,

DR and the remainder is in the BR.

divisor

and

dividend

are

of opposite

sign,

as follows:
1.

If the operation was a subtraction (the

SR (DIVISOR)

signs of the divisor and the partial remainder were the same), the quotient bit

is set if there was no underflow, and is
cleared if there was underflow.
2.

L BR (REMAINDER) HDR (QUOTIENT)

If the operation was an addition (the
signs of the divisor and the partial re-

NOTE:

mainder were different), the quotient bit

Dividend in BR and DR.
11-0844

is cleared if there was no underflow, and
is set if there was underflow.

Figure 1-9

Divide Instructions

The non-restoring division algorithm works because

an underflow at any step can be corrected to within
one multiple of the divisor by the succeeding steps.

The

This is true because a binary number that is repre-

with positive or negative operands; however, the

non-restoring

divide

algorithm

can

operate

sented by all 1s is changed to a number that is rep-

KB11-C always operates on a positive dividend to

resented

the

simplify the detection of underflow. (The divisor

number 1 is added to it. Therefore, the multiple of

may have either sign.) The first two machine states

the divisor that is subtracted from the partial re-

of the division sequence test for a 0 divisor or a

mainder at any step is only one more multiple of

negative dividend, and set up the SR and DR regis-

the divisor than can be expressed by all the less-significant bits of the quotient. The remaining single

ters. If a O divisor is sensed, the division is aborted
and the C, V, and Z condition codes are set to in-

multiple of the divisor can be restored by a single

dicate that an error has occurred.

followed

all 0s,

when

operation (which is always an addition, because un-

derflow exists and the divisor and partial remainder
have different signs) following the steps that gener-

If the dividend is negative, a sequence is entered to

ate the quotient bits; this step is also used to cor-

complement the dividend. Note that the branch on

rect the remainder.

the N condition code occurs after DIV.20, although

Initial Setup

the condition code is loaded in DIV.10 (divide), beDivide Instruction Sequence

cause the branch condition must be available at the

The divide (DIV) instruction is executed by the

beginning of the machine state in which the branch

longest

most complex sequence of machine

is used. Similarly, the branch on the Z condition

states used in the KB11-C Processor. This sequence

code after DIV.10 uses the condition code value set

is illustrated on two drawings. Flows 9 shows the

by DIV.00, not the new value set by DIV.10.

and

I1-1-27

Negative Dividend Processing

The sequence beginning with DVN.00 (divide negation) generates the 2’s complement of the 2-word
dividend as follows:

The 2’s complement of the less-significant word is formed by first clearing the
DR, then subtracting the SR, which contains the low order word, from the 0O in
the DR. The DR is cleared so that a subtract from 0, which requires only one machine state, can be used; normally a 2’s
complement is generated by forming the
1’s complement and then incrementing,
as shown for the remainder of correction
steps. The 2’s complement of the less-

portion of the sequence performs the first cycle of
the division and performs a test for overflow. This
test is based on the fact that if underflow does not
occur during the first cycle, the quotient is too
large to be expressed in 16 bits. If the instruction is
not aborted because of overflow, the processor enters the DIV.70 machine state to begin the main divide cycle.

Division Process

The test for underflow that determines whether
DIV.80 or DIV.90 is entered is based on the following considerations:
1.

If the divisor is negative, adding the divisor to the dividend should produce a re-

sult closer to 0 than the original
dividend. If the result is negative, under-

significant word is stored in the register
which originally held the less-significant

flow has occurred and a O is shifted into

word.

the DR.

DVN.20 generates a carry from the lesssignificant word to the more-significant
word. That is, if a carry-out of the mostsignificant bit of the ALU occurs during
the operations (which is repeated in

DVN.20), a 1 is shifted into the DR.

A 1 is subtracted from the DR. If a
carry occurred in Step 2, the DR contains 0 and the 2’s complement of the
more-significant word is formed; if no
carry occurred, the DR now contains a 1, which cancels the carry insert during
the subtraction in DVN.40, and the 1‘s
complement of the SR is formed. This is
the correct result if there is no carry.

After the 2’s complement of the dividend is formed,
DVN.50 begins the restoration of the divisor to the
SR and the dividend to the BR and DR. However,
if the dividend is still negative, which occurs if the
dividend was the maximum negative number (because the 2s complement notation can express one
more negative number than positive number, the
largest negative number complements to itself), the
division cannot be performed and the sequence is
aborted.

Overflow Test and First Cycle

After the setup is completed, the processor enters

DIV.30 with a positive dividend in the BR and DR,
17(8) in the SC, and the divisor in the SR. The next

If the divisor is negative and the dividend is also negative, an underflow condition already exists. The divisor is
subtracted from the dividend to return
the dividend to a positive number. If the
result is still negative, a 0 is shifted into
the DR; if the result is positive, the underflow has been corrected and a 1 is
shifted in.

For a positive divisor and dividend, a
subtraction is performed. If the result is
positive, a 1 is shifted into the DR, but
if the result is negative, underflow has occurred and a O is shifted in.

If the divisor is positive and the dividend
is negative, an addition is performed to

correct an existing underflow. If the result is positive, the underflow has been
corrected and a 1 is shifted into the DR,
otherwise a 0 is shifted in.
As a result of these considerations, the processor en-

ters DIV.80 if the divisor is positive and there is no
underflow (DRO is a 1), or if the divisor is negative
and there is underflow (DRO is a 0). DIV.80 performs a subtract operation and shifts the carry-out
of the ALU into the DR. (A carry-out of the mostsignificant bit of the ALU indicates that underflow
has occurred; if an uncorrected underflow existed,
the carry indicates that it has been corrected.)

I1-1-28

If the opposite conditions exist (SR is positive and

If the original signs of the dividend and divisor

DRO is 0, or SR is negative and SRO is 1), DIV.90

were different, the quotient should be negative. The

is entered and an addition is performed, followed

quotient is complemented by DVC.80 and DVC.90;

by a shift of the DR. Note that the cases for which

one special case in which the quotient is the most

a carry-out of the most-significant bit of the ALU

negative number is considered an error.

exist are equivalent to the cases described above for
which the least-significant bit of the DR is set.

1.2.5.10

Remainder Storage and Sign Check

Memory Reference Execution Sequences

FLOWS 11

After the divide cycle has been performed 15 times

Flows 11 illustrates eight sequences that execute the

(the first division cycle) and the first decrement of

data manipulation stages of a variety of instruc-

the SC is performed in DIV.30 - DIV.60, DVC.00

tions, when those instructions require external data

(divide correction) writes the remainder from the

transfers

BR into the appropriate general register, and trans-

These sequences are entered from the B Fork deci-

fers control to one of four machine states, depend-

sion point.

complete

the

instruction

execution.

ing on whether a remainder correction is required

and whether the quotient has the correct sign.

Standard Execution
The

majority

instructions

are

executed

Remainder Correction

EXC.00 (execute). When this state is entered, the

If, after the last division cycle, the least-significant

source operand, if any, is in the SR, and the desti-

bit of the quotient is a 0, an underflow condition

nation operand is in the DR. EXC.00 performs one

still exists. This condition can be corrected (unless

data manipulation operation and loads the condi-

an overflow condition also exists) by adding a posi-

tion codes; both the operation performed and the

tive divisor or subtracting a negative divisor to cor-

condition-code loading are controlled by subsidiary

rect the remainder. This is done by DVC.10 or

ROMs

DVC.20. If no remainder correction is needed, or

EXC.00 performs the byte-swap operation in the

following

the

SHFR automatically.

DVC.40

begins

remainder

correction,

complementing

the

DVC.30

remainder

(i.e.,

they

are

instruction-dependent).

case the remainder has the wrong sign. The current

For any instruction that is operating on an odd-

value of the remainder is not disturbed until a deter-

byte destinaton operand, EXC.00 also begins an ex-

mination is made of the appropriate sign.

ternal data transfer operation that is completed in
EXC.10; this operation transfers the result data to
the destination address, which is taken from the
DR.

Quotient Sign Change

If the N condition code is set, the original dividend

was negative. The complemented remainder, which

Negate Instructions

is negative because the corrected remainder is posi-

Several instructions, which are otherwise treated in

tive (if all underflow conditions are corrected), is

the same manner as those executed by EXC.00,

stored as the final value of the remainder. If both

must be executed separately. The negate and negate

the

byte

dividend

and

the

divisor

were positive,

the

quotient, which is also positive (the most-significant

(NEG.B)

instructions

require

two

machine

states for execution because the 2’s complement of

bit of the quotient must be positive or an immedi-

a number is formed by first generating the 1’s com-

ate overflow condition aborts the division), is written into the appropriate general register. Similarly,
if both dividend and divisor are negative, the

plement and then incrementing that value. After the

quotient should be positive and is written in its pre-

destination operand is an odd byte, and starts an ex-

sent form.

ternal data transfer that is completed in EXC.10.

negation

performed

and

the

condition

codes

loaded, the processor performs a byte swap if the

11-1-29

Shifter Instructions

contents of the specified register. JSR.10 transfers
the SR to the BR, which is the register that holds

Two instructions, which are executed by EXC.00

when they operate on an even byte [DRO0(0)], use
the SHFR to perform a right shift. These are the

data to be transmitted during external data transfers, and loads the DR with the contents of general

ASRB and ROR instructions. When these instructions operate on a destination operand taken from

the Stack

Pointer (SP).

JSR.20 decr-

ements the SP by 2 (to allocate a word at the top

an odd-byte location [DRO(1)], a second machine
state is required to perform the byte swap, which
also requires the SHFR. Therefore, SHR.00 (shift
right) performs the same actions as EXC.00, except

of the stack for the data to be stored); the new
value is stored in the SP and in the DR for use in
the external data transfer started in JSR.30. JSR.40
transfers the contents of the PCB to the specified
general register and loads the PCB from the PCA.

that no external data transfer is begun and no byte
swap is performed. These functions are performed
by SHR.10. No conflict occurs for the ASL and

The data transfer begun in JSR.30 is completed in
this state.

ROL instructions because left shifts are performed
by the ALU, not by the SHFR.

Move From Previous Space Instructions

The

MFPI or MFPD instruction transfers data
from the destination address to the hardware stack;

Test Instructions

The three instructions that set the condition codes
without modifying any stored data, TST, CMP,
and BIT, are executed by machine states that do

it acts like a ““push” instruction. If Memory Management is on, the address space from which the de-

not

space that the data is pushed into, but this does not

start

external

data

transfer

for

the

sination data is taken may differ from the address

data

operand.

affect

the

operations

within

the

processor.. The

MFP.00 state is entered with the data to be trans-

Jump Instruction

ferred in the BR; this state loads the condition
codes and loads the SR from the hardware stack
pointer. The MFP.80 machine state is entered if the

The jump (JMP) instruction performs only one operation; it sets a new value in the Program Counter
(PC). The value loaded into the PC is the destina-

destination mode is 0; this implies that the data is
in a general register. This data is loaded into the
DR while the bus operation started by the IRD.00

tion address, not the destination data word. The
last external data transfer to fetch the data word is
aborted, (BEND) the PC is loaded, and a transfer
to the instruction fetch sequence is performed by
the machine state JMP.00 (jump).

machine state is aborted. The MFP.90 machine
state transfers the DR to the BR and loads the SR

from the stack pointer. The sequence for destination mode O then joins the sequence for the other
address modes in MFP.10. This state decrements

Jump to Subroutine Instruction

The jump to subroutine (JSR) instruction performs

the

(which

two data transfers in addition to loading the PC.
The contents of a register specified by the instruc-

contains

SVC.90

(Flows

13)

tion are saved on the hardware stack, and the previous

value in the PC is saved in the specified
register. JSR.00 (jump to subroutine) the last exter-

the

complete

SP).

SVC.80

and

the

instruction

pushing the data onto the stack.
1.2.5.11
FLOWS 12 and 13 - Flows 12 and 13
show the abort, trap, interrupt and floating-point
service routines. The abort, trap and interrupt se-

nal data transfer, loads the destination address into
the PCA (but does not load the PCB from the
PCA, so that the PCB can be stored in the general

quences are described in Chapter 6. The FP11-C in-

7).

structions are described in Paragraph 1.2.5.7 (Flows

I1-1-30

1.2.5.12

FLOWS

14 - Flows

14 shows the se-

The horizontal line to the right of that

quences for manual Console operations. These oper-

number

ations are described in Part III of this manual

umn, for the next most-significant group

leads

another vertical col-

of bits in the binary code. Look down

(Console).

that

line

find

the

number

that

matches the value of the corresponding
1.2.6

Following

Instruction

Through

bit or bits in the instruction.

the

Flowcharts

To follow a particular instruction through the flow-

Repeat Step 2 for each portion of the

charts, it is necessary to know which machine state

binary code until the last number is fol-

sequences apply to that instruction in the particular

lowed by the symbolic name and struc-

state of the processor (specifically, which machine

ture

state will be entered from various fork decision

horizontal line. That instruction corre-

points).

sponds to the given binary code.
When

the

symbolic

instruction

code

for

instead

of a

instruction

that

instruction

The tables and diagrams in this paragraph are de-

known,

signed to help determine the exact sequence of ma-

Table

chine states for a particular instruction. Starting

quences used to execute that instruction. The table

the
1-3

reader

which

can

find

specifies

the machine state se-

with either the binary code, or the symbolic name

is in alphabetical order according to the mnemonic

of the instruction, the machine state entered from

codes used for the instructions, and lists both the in-

each decision point, and what branches are taken at

struction classes, if any, and the machine states en-

some of the primary branch points within the se-

tered from various decision points, when used. The

quences shown can be determined.

instruction classes are groupings of the instructions
according to properties of the execution sequences

(e.g.,
1.2.6.1

Figures and Tables - Figure 1-10 shows the

and

O/Class

instructions perform

DATI, DATIP, or DATO bus transfer as the last

correspondence between binary op codes and in-

transfer of the destination

struction mnemonics.

While the A Fork decision point is used by all in-

data fetch sequence).

structions (the A Fork decision point follows the in-

Starting with the most-significant bit of

struction

the instruction code, look down the cor-

instruction decoding system), not all instructions

responding

column

of Figure

fetch

sequence

and

is,

effect,

the

1-10 to

use the B Fork or C Fork decision points; those

find the number that matches the value

which do not are indicated by entry “N.U.” in the

of that bit in the instruction.

appropriate column.

il-1-31

Table 1-3A
Instruction Microprogram Properties

Instruction

ADC.B

ADD:

-SMO

ASH

-DMO

ASHC

-DMO

Class

B Fork

P, E, DAC

See Table 1-3B

EXC.00 (11)

N. U.

JMP

-DMO

P, E, BIN, DAC

See Table 1-3C

EXC.00 (11)

N.U.

JSR

-DMO

P, E, BIN

SMO

DMO

DAC

See Table 1-3C

P,E, DAC

See Table 1-3C

See Table 1.3C

EXC.00 (1)

P, E, DAC
P.E. DAC

See Table 1.3C
See Table 1-3C

P, E, DAC

DRO(0)
DRO (1)

EXC.00 (11)

See Table 1-3C

DAC

ASR

See Table 1-3B

DAC

ASL.B
ASRB

A Fork

ASH.10 (3)

N.U.
N.U.

MARK

ASC.00 (7)

N. U.

MFP

EXC.00 (11)

N.U.

MOV

EXC.00 (11)
SHR.00 (11)

N.U.
N.U.

ASC.00(7)

Branch Instructions: BCC (BHIS), BCS (BLO), BEQ, BGE, BGT, BHI, BHIS — See Table 1-3E
BICB -SMO
P, E, BIN
See Table 1-3B
EXC.00 (11)
SMO
P, E, BIN, DAC
See Table 1-3C
EXC.00(11)
BISB

-SMO
SMO
BIT.B -SMO

P,E, BIN
P, E, BIN, DAC
I,E, BIN

SMO

LE, BIN, DAC

See Table 1-3B
See Table 1-3C
See Table 1-3B

EXC.00 (11)
EXC.00(11)
TST.10 (11)

See Table 1-3C

See Table 1-3D

TST.10(11)

N.U.

See Table 1-3D
N.U.
See Table 1-3D
N.U.
See Table 1-3D
N.U.

Branch Instructions: BLE, BLO, BLOS, BLT, BMI, BNE, BPL — See Table 1-3E

BPT (OP3)

None

I TRP.00 (3)

Branch Instructions: BR, BVC, BVS — See Table 1-3E
CCOP
None
CCP.00 (3)
See Table 1-3C
P,E,DAC
CLR.B

[

Instruction

ASH.00 (7)
ASH.00 (7)

ASC.10 (3)

C Fork

DMO

-DMO

Class

A Fork

B Fork

1, FJ, DAC

See Table 1-3C

JMP.00 (11)

N.U.

J, FJ, DAC

See Table 1-3C

JSR.00(11)

N.U.

None

MRK.00 (2)

N.U.

RSD.00(3)

N.U.
N.U.

N.U.

N.U.
N.U.

DMO

I, DAC

MFP.80 (3)

See Table 1-3C

MFP.00 (1 l)

-SMO

O,E, BIN

See Table 1-3B

N. U.

N.U.

MOVB -SMO
SMO

P, BIN
P, BIN, DAC

See Tzble 1-3B
See Table 1-3C

EXC.00 (11)
EXC.00 (11)

See Table 1-3D
N.U.

MTP
MUL

0
I, DAC
I,DAC

MTP.00 (1)
See Table 1-3C
MUL.80 (3)

N.U.
MUL.00 (8)
MUL.00 (8)

See Table 1-3D
N.U.
N.U.

P, E, DAC

See Table 1-3C

EXC.00(11)

SMO

-DMO
DMO
NEG.B -DMO

RESET

DMO

ROL.B

I, DAC

RSD.00(3)

C Fork

0, E, BIN, DAC

P, DAC
P,DAC
None

See Table 1-3C

See Table 1-3C
NEG.70 (3)
RES.00 (3)

N.U.

N. U.

See Table 1-3D

NEG.00 (11)
N. U
N.U.

N.U.
N.U.
N.U.
N. U.

ROR

P, E, DAC

See Table 1-3C

EXC.00(11)

N. U.

EXC.00 (11)

N. U.

N.U.

RORB DRO (0)

P, E, DAC

See Table 1-3C

N.U.
N. U.
See Table 1-3D

None

RTLO1 (2)

N.U.

RTI
RTS
RTT

SBC.B

P, E, DAC

DRO (1)

P,E, DAC
None
None

See Table 1-3C
RTL.0O (2)
RTS.00(2)

SHR.00 (11)
N.U.
N.U.

N.U.
N.U.
N.U.

See Table 1-3C

EXC.00 (11)

N. U.

CMP.B -SMO

I, E, BIN

See Table 1-3B

N.U.
EXC.00 (11)
TST.10(11)

COM.B

P, E, DAC

See Table 1-3C

EXC.00(11)

N.U.

SOB

None

SOB.00 (2)

N. U.

N.U

DEC.B

P,E, DAC

See Table 1-3C

EXC.00 (11)

N.U.

SPL

None

SPL.00 (3)

N.U.

-DMO
DMO

I, DAC
I, DAC

See Table 1-3C
DVS.00 (3)

DIV.00 (9)
DIV.00 (9)

N.U.
N.U.

SUB

P, E, BIN
P, E, BIN, DAC

See Table 1-3B
See Tabie 1-3C

EXC.00 (11)
EXC.00 (11)

See Table 1-3D
N. U.

EMT
Floating Point:

None
F,FJ

RSD.00 (3)

N. U.

N.U.

E(S)g:gg ((g))

géeufable
1-3D
FOP.50 (4)

P, E, DAC
P,E, DAC

See Table 1-3C
See Table 1-3C

EXC.00 (11)
EXC.00 (11)

N.U.
N.U.

FOP.00 (2)

1;(.)&40
(7
FOP.40 (7)

SWAB
SXT

See Table 1-3C

EXC.00(11)

N. U.

N.U.

SMO

DIV

ifx?IFII{{EESS*]?II;IIF\FIIO
FP PRES*DMO

I, E, BIN, DAC

See Table 1-3C

HALT

None

HLT.00 (3)

10T

None

TRP.00 (3)

INC.B

[1-1-32

P,E,DAC

TST.10(11)

N.U.

N.U:

N. U.

TRAP
TST.B

WAIT
XOR

-SMO
SMO

None
IE,DAC
None

P,E, DAC

See Table 1-3C

RSD.00(3)

N.U.
TST.10(11)

See Table 1-3C

EXC.00(11)

WAT.00 (3)

N.U.
N. U.
N.U.

Table 1-3B

A Fork, BIN*-SM0

‘}’J ? %

Source Mode

Machine State

S$13.00(1)

2
3

A Fork, DAC Destination Mode

$13.01 (W—""

S13.01 (1)

4
5

$45.00 (1)

S67.00 (2)

Table 1-3C

//’

a?f“f{

py A b\)
N,

Machine State

(DF7 + BRQ):EXC.90 (3),

-(DF7 + BRQ):EXC.80 (3)

D12.00 (5)

- D30.00 (5)

D45.00 (6)

D45.01 (6)

D67.00 (6)

D67.01 (6)

Table 1-3D

Table 1-3E

C Fork, BIN

Branches

Destination Mode

SRO

Machine State

DF7:D07.10 (4), -DF7:D00.90 (4)

DF7:D07.00 (4), -DF7:D00.80 (4)

D12.80 (5)

D12.90 (5)

Instruction

Branch Successful
BRQ Present

Branch Not Successful

BRQ Not Present

BRQ Present

BRQ Not Present

BCC

BXX.03

BXX.00

FET.01

FET.11

BCS

BXX.04

BXX.01

FET.03

FET.13

BEQ

BXX.05

BXX.02

FET.03

BGE

BXX.03

BXX.00

FET.02

FET.13
FET.12

D12.80 (5)

BGT

BXX.03

D12.90 (5)

BXX.00

FET.02

FET.12

BHI

BXX.03

BXX.00

FET.01

FET.11

D30.80 (5)’/

BHIS

BXX.03

BXX.00

FET.01

FET.11

D30.90 (5)

BLO

BXX.04

BLOS

BXX.04

D45.80 (6)

D45.90 (6)

BLT

BXX.05

BXX.02

BMI

FET.03

BXX.04

FET.13

BXX.01

FET.03

FET.13

BNE

BXX.03

BXX.00

FET.02

FET.12

D45.80 (6)

BPL

BXX.03

D45.90 (6)

BXX.00

FET.01

BXX.05

BXX.02

BVC

BXX.03

BXX.00

FET.01

FET.11

D67.80 (6)

BVS

D67.90 (6)

BXX.04

BXX.01

FET.03

FET.13

D67.80 (6)

D67.90 (6)

(All Cycles on Flows 1)

BLE

BXX.05

BXX.02
BXX.01
BXX.01

FET.03

FET.13

FET.03
FET.03

FET.13
FET.13

FET.11

(always successful)

I1-1-33

IR
15

IR
14-12

IR
11-09

IR
08

l PC AND PS CHANGE (1 0OF 2)

+—

-l—_————

DOUBLE OPERAIGEI

OFFSET

BGE

OFFSET

IR
07-06

IR
05-03

)

01 HALT
WAIT

RESET l
65§ RTT
7 RESERVEDI

BNE OFFSET

BLT OFFSET

BIC

SRC,DST

F———

SXT

— 0

MUL

ASH

XOR

|7 bpIiv

REG. SRC

REG, SRC

RESERVED

]

| O

BPL

OFFSET

{———————
0

BHI

OFFSET

BMI

OFFSET

1 BLOS OFFSET

19 BV

ORESED

L BLa

OFFSET (BCS)

3——————] O BHIS OFFSET (BCC)

CMPB

SRC,DST,—— ——— — ———/TM-—-

BICB

SRC,DST

BISB

I
SRC,DST I

L_| &

sus

SRC,DSTJI

—_—

DST

———
e
— ——

SRC, DST

ASL
DST
MARK OFFSET

MOVB

SRC,0ST |

DST
DST

3 BITB

REG, SRC

["PCTAND PS CHANGE (2 OF 2)

DST

3
O

L_ 7 So8 Res oFFseT

(2 OF 2)

DST

ROR

3 ASHC REG, SRC

" T oousLE oPERAND!

SBC

RTS REG

1 3 SPL PRIORITY
I |' 2¢ }ccop MICROINSTRUCTION

ROL
ASR

2 RTI

2 RESERVED

1
2

Bg:rr

3 ISt DST

L_'_7_RESERVED

ggcc

’? r:gg gg

6
7

SWAB DST
DST
031 CLR
COM DST

| [ s abp sRc,psT |

JMP DST

—_— e — —

I 5 BIS SRC,DST II

O BGT OFFSET
3
|
(1 OF 2)
| MOV SRC . DST ||__ 4 JSR REG, DST |7 BUE OFFSET
—
e e e e e —
2 CMP SRC, DST

||— SINGLE OPERAND (1 OF 2)
I
0
| > BIT SRC,DST I I 5

IR
02-00

| ¥ TRAP CODE

SINGLE OPERAND (2 OF 2)

O CLRB DST

2 SBCB

;g%

DST
gg

ROLB

DST

3
O
!
2

2 ASRB DST

DST
ASLB
RESERVED
MFPD
SRC
MTPD
DST

3 RESERVED

FLOATING POINT

| [FLOATING POINT OPERATE

7 RESERVED

ggjr

OY Ao
NEGB DST
pat

%gccg

|
|

1 COMB DST
g

SINGLE OPERAND

I o

LDFPS

STST

1—} 0

2 STFPS

SRC

O CLR(F/D)

FDST l

i TST (F/D)

DST

FOST

l l

MOD(F/D)

AC, FSRC

3————————— 0

SUB(F/D)

AC, FSRC

4——————
0

ST(F/D)

O ADD(F/D) AC.FSRC
17 Lo(F/0) AC FSRG

1 CMP(F/D) AC, FSRC

I
|

§————————0 STEXP
1

6———-—10
1

DIV(F/D)

AC, FOST

AC, DST k= o

AC. FSRC

STC(F/ONI/L)

STC(F/DMD/F)
LDEXP

LDC(I/LXF/D)
LDC(F/DND/F)

AC,

DST

SETF

LDUB

|
|

S sta0
5

3
25

2 SETL
3a

2 SETI

4 MSN

[ FLOATING POINT AC AND OPERAND|| | 2 ABS(;/D) f:gsu
l
f———————0 MuL(F/D) Ac, FsRe |Lo 2 NEG (/D) FOST | ||,
l

0 CFCC

5 STAO
1

SETD

L__._...____..___
3

I
N

AC, FDST
AC. SRC

11-3450

Figure 1-10

Determination of an Instruction from the Binary Code

I1-1-34

Whenever possible, the entry for each active deci-

Its Source mode is 2 (SM2) and its source field (reg-

sion point specifies a machine state by its symbolic

ister) is 7 (SF7). After the Fetch cycles, the PC (reg-

name, with the number of the flowchart where that

ister 7) contains 1002. This value is the address of

state is illustrated in parentheses. If a particular ma-

the operand. A DATI is performed; it reads loca-

chine state depends on additional conditions, those

tion 1002 which contains 15, the source operand.

" conditions are shown preceding the corresponding
machine state and are separated from the state by a

The Destination mode is 6 (DM6) and the destina-

colon.

tion field is 7 (DF7). The PC contains 1006 after

To follow an instruction through the Flows with

is stored in the location whose address is the sum

Table 1-3, execute the following steps:

of the present PC (1006) plus the contents of the in-

the source operand fetch. The destination operand

dex word, whose address is 1004. The index word
1.

Find the instruction symbolic name in

equals 100, and the destination operand is at loca-

the INSTRUCTION column (Table

tion 1106. Two DATIs are required to obtain the

3A).

destination operand: the first reads the index word,

the second reads the operand.
2.

Go to the A Fork cycle shown under “A
Fork” and follow the Flows until a B or

Immediately before the processor begins the ma-

C Fork, if any, is found.

chine state sequence for this instruction, the Program Counter (PC) contains the value 1000(8), the

Go to the B or C Fork cycle shown in

processor status word contains the value 000340,

Table 1-3A. Repeat Steps 2 and 3 if the

there are no bus requests or other asynchronous

instruction uses both the B and C Forks.

conditions, and the processor is about to enter the

Determine the type of execute cycle from

operation is begun, using the contents of the PC as

the CLASS column of Table 1-3.

the address.

FET.0X machine state. In this state,

a DATI bus

A sample instruction is taken through the Flows, us-

FET.1X

ing this documentation, in Paragraph 1.2.6.2.

Assuming that no requests have been strobed into
the request register (refer to Chapter 6), the next

machine state entered is FET.1X. In this state, the
1.2.6.2

An Instruction Example — This paragraph

PC is updated (the new value is loaded into the

traces one instruction through a sequence of ma-

PCA and does not disturb the PCB, which is still

chine states to illustrate the process of finding each

being used for the address in the data transfer) and

machine state and using the flowchart and ROM

the word that is read is loaded into the IR and BR.

map information to understand the operations per-

Thz PCA now contains 1002, the IR and BR con-

formed by the processor. The example instruction

tain 022767, and the PCB still contains

and

nally, after the bus operation is completed, the PCB

the environment

which

executed

shown in Figure 1-11.

1000; fi-

is updated to 1002.

The instruction is a CMP, which subtracts the desti-

IRD.00

nation word from the source word and uses the re-

The third machine state entered is IRD.00. In this

sult to set the condition codes. These may then be

state, the A Fork logic is enabled. According to Fig-

used by arithmetic and logic conditional branches.

ure 1-10, the binary number in the IR represents a

BH1AE0

QZ¥e?

BGoE1s

gRolop

Figure 1-11

CHF

#13.

Instruction Execution Example

I1-1-35

CHAR

word, which when added to the destination mode
register (R7 or the PC), is the address of the desti-

CMP instruction; the entry for this instruction in
Table 1-3A refers to Table 1-3B, which indicates
that for a source mode of 2 (as specified by the

nation word.

third octal digit of the instruction), the next machine state is S13.01. Since both the source and destination fields are 7, the IRD.00 machine state also
loads the SR and DR with the updated PC value
(1002). Since CMP is a binary instruction and its

Following the D67.0 state, the processor enters the
D67.1 state, where the PCB is loaded from the
PCA and the contents of the BR is added to the
contents of the DR. The result (1106) is the index
word and is loaded into the DR. The branch condition in this machine state selects the D10.3 state to

source mode is 2, RACH BUST is not asserted in
IRD.00 (CONDITIONAL BUST, refer to Para-

follow the D67.1 state (-DM357).

graph 1.2.5.1).

In the D10.3 machine state, the processor begins a
fourth bus operation, using the contents of the DR
(1106) as the address. The type of bus operation
performed depends on the instruction class, according to Table 1-3A. A CMP instruction is an I/Class
instruction, so a DATI operation is begun. This machine state also loads the BR from the SR, so that

Source Operand

In S13.01 the DATI is started, using the contents of
the SR as the address. The contents of the SR
(1002) are incremented by 2, and this value is written back into the PCA and PCB, which now contain 1004.

both registers contain 15.

The fifth machine state entered for this instruction
is the S13.10 state. In this state, the DATI is completed, with the data that has been read-loaded into
the BR register. The new contents of the BR are 15
(the contents of the word following the instruction,
which is the source operand). The DR is loaded
with the updated contents of the register specified
by the destination field of the instruction (because
this is register 7, the DR is loaded from the PCB);

The next state entered depends on the instruction
class. A CMP instruction is not F, J, or O/Class,
so the D10.60 state is entered. This state completes
the fourth DATI operation, loading the contents of
the location addressed by the DR (location 1106)
into the BR. This word is the Destination Operand,
which equals 0.

the new contents of the DR is 1004.

Execute

Destination Operand

For a source mode of 2, the branch condition in
S13.10 enables the Fork C logic. The entry for the
CMP instruction in Table 1-3A refers to Table I3D, which indicates that, for a destination mode of
6 and the least significant bit of thg SR equal to 0
[SRO(0)=even address], the next machine state is
D67.80, which is shown on Flows 6. This machine
state transfers the contents of the BR (=source op-

erand) to the SR, and begins the third DATI bus
operation, using the contents of the PCB as the
address.

The next machine state is D67.00, which completes
the third DATI and increments the PCA by 2. Because the DR is intended to reflect the current contents of the specified register, the DR is updated to

reflect the new value in the PC, which is 1006. The
data read into the BR is 100. This is the index

The D10.60 machine state branch condition enables
the B Fork logic [DRO(0)]. The entry for a CMP instruction in Table 1-3A indicates that the next machine state is TST.10 (Flows 11).

The CMP instruction does not alter any data
words, so no further bus operations are required.
The TST.10 machine state performs instruction-dependent (3 on Flows) data operations and condition-code loading.

Flows 11 shows that the arithmetic operation is performed with the A operand = BR (destination

word) and B = SR (source word). The ALU Con-

trol ROM Map on drawing GRAK shows that for
CMP.B, the operation is A -~ B - 1, and that the
SHFR does not change the result (except in the
case of an odd byte operation, in which case the
bytes are swapped).

I1-1-36

In this example, the following operation is executed

These four drawings list all the ROM states in nu-

by the ALU:

merical

order.

The

following

information

provided:
A input:

0 000 000 000 000 000

B input:

-0 000 000 000 001 101

minus 1:

-0 000 000 000 000 001

1111111111110011

Result (to SHFR):

the

STATE

column,

the

name

which the state is called on the Flows.

1111111111110010
+ carry

In the FLOWS column, the sheet of the
Flow Diagrams on which the ROM state
is shown.

The condition codes are then set as shown by

the CC Control ROM Map on drawing IRCIJ:

In the ADR column, the ROM address
of the state.

N is set if “SHFR(15)0” (SHFR bit 15=0).

In the BRK - ALU columns, the value

Z is set if “A=B(15:00)" (four-input gate to

of each

IRCF Z DATAI L).

state.

Vissetif “A15*~BI5*-ALUI5+-A15*BIS*ALU

ROM

fields

for

each

In the FEN column, the fork that is enabled, if any.

15" (bottom two inputs to the lower IRCE
VDATA L 74S65:

of the

A=AMX, B=BMX).

In the BEN column, the branch that is
enabled, if any.

C is set if “ALU COUT 15" (DAPJ ALUCN
L).

7.
I.

In the UAD column, the base address

The N bit is cleared, since bit 15 of the

for the next ROM state, which may be

SHFR is 1.

modified if the FEN or BEN fields are
other than 0.

The Z bit is cleared, since the output of

the ALU is not 0.

1.4

ROM ADDRESS

The V bit is cleared, since A15 and B15
(AMX bit 15 and BMX bit 15) are the

Refer to Figure 1-12. The ROM Address Register
(RAR), which is clocked at T3, determines the out-

same.

put of the ROM for the next cycle and supplies the
address for the next cycle. It also supplies the ad-

The C bit is set, since there is a carry

dress for the Memory Management ROM (refer to

from ALU bit 15.

Section V).

NOTE

The input to the RAR [RACL RADR(07:00) H] is

The arithmetic and the N and

the address selection logic shown on RACL. The

condition code load oper-

ations

those

are

the

described

opposite

the

following are inputs to this logic:

First
1.

Edition of the PDP-11/70 Protion,

however,

performs

this is the

ROM

address for the next

cycle.

specified in the Handbook.
1.3

The UADR field of the ROM. In the absence of any of the modifying signals,

cessor Handbook. The instruc-

ROM MAP

Refer to drawing D-CS-M8123-0-1, ROM & ROM
CONTROL, sheets 12 - 15.

I1-1-37

The Branch inputs, which are controlled

by conditions occurring in the rest of the
processor logic.

TO MEMORY

MANAGEMENT ROM

PAR.1.4.4
EXTERNAL

PAR.1.4.1

RADR

RAR

PAR. 1.1

flzfigg“

CONDITIONS

RACK

PAR.1.4.5

PAR.1.4.6

AFIR

PAR.1.4.2

RACJ, H
)

I —

RACE, F,H

ROM

PAR.1.4.8

PAR.1.4.5

BELRA m—

IRCB

PAR.1.4.7

e
IRCA

S
IRCC

RACA

‘

RACL

RACC

RACD

RACA

RACB

RACC

RACD

1-31086

ROM Address

Figure 1-12

The Fork logic, which is controlled by
the instruction word there are three
Forks:

The A

Fork, used by all instructions, is the instruction decoder for
the KB11-C.

The C Fork, which is used only by
binary instruction that require address calculation (SM not 0)

1.4.1
ROM Address Register (RAR)
There are three identical copies of the RAR. Refer
to drawings RACA through RACD. In addition to
the two copies (RARB and RARA) used to provide
sufficient fanout for the 16 ROM ICs, a third copy
(RAR, shown on RACD) is used to transmit the
current microprogram word address to the Memory
Management ROM (refer to Section IV of this
manual).

Figure 1-12 lists both the paragraph and the logic
drawings containing information about the ROM

The RAR is normally loaded from inputs generated
by the microprogram address selection logic shown
on drawing RACL. Under some circumstances, the
RAR is forced to address 200 by clearing all but
the most-significant of the eight bits, and setting
that bit. To permit setting the most-significant bit,
it is implemented by a separate flip-flop. The remaining seven bits are implemented by 6-bit registers of the same type used for the ROM output

address generation.

buffer.

The B Fork, which is used for execute cycles by instructions that require either source or destination
address calculation, or both.

I1-1-38

RACA ZAP L is the signal used to force the processor into a known state to start the processing of
aborts and of the power-up sequence. The conditions that can generate this signal are:
1.

Power-up

sequence

start

From the above, it can be seen that:

A branch can assert an RADR bit for
which the UADR is not asserted;

sequence

Any Fork can negate an RADR bit for
which the UADR bit is asserted. For ex-

(ROM INIT)

Parity error abort, which is flagged
UBCB PE ABORT during the microprogram cycle which follows a pause

All other aborts (TMCC ABORT),
which are flagged during a pause cycle

ample, if UADROO is asserted (low) and
the A Fork (lower gate) is enabled,
RADROO is negated if none of the AQ,
Al, A2 RABOO signals are asserted
(low). The A Fork has an address of
377, or all eight UADR bits asserted;
any combination of these could be ne-

(RACB UBSDOI).

gated to generate any address between

PE ABORT and ABORT are gated with TIGD
TS2 L, which remains asserted longer than the
pulse TIGC T3 L that clocks the RAR, and ensures
that the ZAP signal overrides the normal address.

000 and 377.
Fork Inputs

The

Fork

input,

RACD

UAFEN

unconditional.

ROM INIT and ABORT are described in Chapter
6 of this manual.

1.4.2 ROM Address Selection
Refer to drawing RACL. RADR(07:00) are the inputs to the RAR. An address bit is asserted (high),
when all four of the negative-input-OR gates have
at least one low input.

On all RADR 74S64 gates, there are four input OR
gates. Three of these gates are used for the forks,
one gate each for the A, B and C Forks. The
fourth gate is the OR of the ROM UADR field bit
and of the Branch Enable Bit (BRCAB) for that bit
position. Since there is no branch enable for bit 3,
the gate for RADRO3 has only one input,

The C Fork input, RACD UCFEN L, is disabled
by BENI4 if the source mode is 3, 5 or 7. This
branch occurs during source mode operand fetch
when one more bus cycle is required to fetch the

source operand. Refer to Flows 1, S13.10 and
Flows 2, S67.30: if -SM 357, the next cycle starts the
DM operand fetch on the C Fork; if SM357, both
cycles fetch the operand in S13.20 - S13.40 and
then go to the C Fork.
The B Fork input, RACD UBFEN L, is disabled
by one of two conditions, both shown at the bottom of Flows 6:

BENIS. If the instruction is FJ/class, it
goes directly to the B Fork for execu-

UADRO3.

tion; if it is not FJ/class, it branches to

one of two cycles, depending on whether

When all three fork inputs are negated,
the OR gate inputs for the forks are low.
The inputs to the fourth gate then deter-

or not it is O/class, to complete its destination operand fetch.

mine the state of the address bit: if either or both UADR and BRCAB bits
are asserted (low), the RADR bit is as-

serted (high).

Only one of the three UFEN bits is ever
asserted at one time (in a microprogram
word). When one of these bits is asserted, its input to its RADR OR gates
is high, and this OR gate is asserted if
one or more of their fork logic input signals is asserted (low). In this case, the
RADR bit is asserted (high).

BENO5.

instruction that is neither

O/class nor FJ/class goes to the B Fork
if its destination address is not an odd
byte. If it is an odd byte [DRO(1) or
GRAB OBD] it first branches to D12.30
to swap bytes in the BR, and then goes
to the B Fork.

1.4.3

Branches and Forks

Normally, the address of the next microprogram
word is derived from the contents of the microaddress field (UADR) in bits 7 — 0 of the current

I1-1-39

microprogram word. Two Branch selectors allow 2-

follows, but is described in Section III (Console) of

way or 4-way branches on the conditions of various

this manual.

processor circuits and on the contents of various
data

registers.

For

most decision

points encoun-

tered during the flow of machine states, this branch
capability is sufficient.

RACK

BRCAB(05:04)

are the outputs of the

branch logic; each signal is ORed with the corresponding bit of the microprogram address from the

In certain situations, particularly after an instruc-

current

ROM word on one of the input gates to

RACL

RADR(05:04). When the 4-way branch is

tion or data has been fetched by a state sequence

used, bits 5 and 4 of the UAD address are both ne-

that is common to many instructions, it is necessary

gated (high), and the two branch signals select one

to select a next machine state that is unique to one

of four addresses. If only a 2-way branch is desired,

onc of the UAD address bits is asserted (low), and

small

much

class

of instructions.

wider branching capability.

This

requires a

In the KB11-C

Processor, this capability is provided by the Fork

the corresponding

branch bit is ignored,

because

the result of the OR is always asserted.

logic. Each of three forks generates one of a large
number of possible addresses, based on the decod-

Refer

ing of the instruction, the address modes, and vari-

BRCABO4 L are both generated by identical logic

ous

processor status indications.

RACK.

BRCABOS5

and

circuitry, which consists of two multiplexers and a
4-input AND-NOR gate. UBEF(03:00) controls the

microprogram, the address generated by the fork is

circuit.

into

a fork

drawing

enabled by the corresponding fork-enable bit of the
loaded

When

the ROM address register instead of

the contents of the microaddress field.

UBEFO03 selects the multiplexer: when this signal is
not asserted, the top multiplexer is enabled and the

1.4.4

Branch Logic

lower

The processor is controlled by words fetched from

one

disabled.

The

opposite

occurs

when

UBEFO03 is asserted.

a microprogram ROM; each word represents a machine state. The sequence of machine states is con-

UBEF(01:00) selects which input to each half of the

trolled

multiplexer

the sequence

of ROM words

fetched.

Normally, each ROM word contains the address of

selected.

Each

has

two

outputs.

the next word to be fetched. When it is necessary to
provide for alterations in the sequence of machine

UBEFO02 selects which of the two outputs of the

states, two bits of the address contained in the cur-

multiplexer

rent ROM word can be altered by inputs that sense

through the BRCAB gate.

selected

UBEF(01:00)

gated

processor conditions and data values. The altered
bits select different addresses, depending on their final

values, so that

up to four different addresses

When UBEF(03:00) = 00, the DI inputs to the top
multiplexers

are

selected.

Since

these

are

both

can be selected. This 4-way branch permits a wide

ground,

variety of machine state sequences to use the same

and the corresponding ROM address bits, RACL
RADR(05:04) follow the UADR(05:04) inputs, i.e.:

microprogram words.

BRCAB(05:04)

are

both

negated

(high),

the address is not modified.
The same is true for
The two bits that can be altered by branch condi-

UBEF = 14, which is the Console branch.

tions are bits 5 and 4 of the microprogram address.

Therefore, when a branch is used, the addresses se-

Table 1-4 shows the inputs for each branch.

lected for different conditions differ by 20, 40 or
60. There are 16 sets of branch conditions. One of

the 16 sets is selected by the four branch-enable bits

1.4.5

in the current microprogram word.

The instruction word is read from memory during

The Console branch (Flows 14) can modify bits 7,

at T1 of IRD.00; this is shown as T6 of FET.10 on

6 and 2:0; it is not included in the explanation that

the Flows.

[Instruction Registers

FET.10. It is clocked into the Instruction Registers

I1-1-40

Table 1-4
Branch Signal Sources

UBEF

RACK BRCAB 05 L

RACK BRCAB 04 L

Comments

Value
00

| GROUND

GROUND

|{IRCDDM357H

GRAE SREQONEL

|IRCFZ2(1)H

TMCB (PWRF + INTR) L

|GRAJSC=0L

GRAJ SCO5 L

|GRAJIDIVSUBL

IRCHN (1)H

GRABOBD (0)H

GRAJ DIV QUITL

No Branch

BRCABOS: Disable B Fork if OBD,
Flows 6

|DAPABRI14L

SSRA PS RESTORE (1) H

|RACKBE75H

RACK FP REQ H

|UBCCRIP+FPSYNCH

FRMB FP CLASS L

GRAJSC=0L

GRAD DROO H

|TMCACONF(1)H

TMCB BRQ TRUE L

TMCB PF(0) * (SF + TF) H

TMCB PF(0) * (SF + -TF) H

|GROUND

GROUND

DisabloC For 1tSM3s ’IZ?Flows 182

|IRCBFJCLASSL

IRCC 0 CLASS L

Disable B Fork if F/J Class, Flows 6

GRAD DROOH

GRAH SR15 .H

|RACKRIP+FPSYNCL

TMCB BRQ * (T+ CONF) L

*TMCB BRQ * (T+ CONF) L

I1-1-41

| Service Flows, Flows 12

There are two copies of the Instruction Register

the address from the microprogram in a bit-clear

(IR):

operation as shown on drawing RACL.

RACJ AFIR(15:00) (1) H, which is
used only by the A Fork logic for rea-

The signal names indicate the use of each logic circuit as follows:

sons of speed. For this same reason,

there is an extra copy of bits 9 and 10
[RACH AFIR(10A:09A) (1) H].
2.

IRCA IR(15:00) (1) H, which is used by

The fork signals that are connected to
the microaddress logic on drawing
RACL have names that include RAB
(for ROM Address Bit), followed by the

the B and C Forks, the Condition Code

number of the address bit to which the

logic and the rest of the KB11-C logic.

signal is connected.

UIRK bit of the microprogram field is asserted in

In some cases, a signal is connected to
more than one address bit because the

FET.10.

same conditions generate both bits.

Both copies of the IR are clocked at Tl when the

1.4.6

A Fork Logic

Many RAB signals are connected to the
same address bit. They are distinguished

1.4.6.1

by a letter that tells which fork generates

Decode Logic - Refer to drawing RACE.

The logic illustrated on this drawing is part of the

the bit, and where more than one signal

A Fork. This fork operates as the instruction deco-

can

der of the processor. Immediately after the instruc-

Thus, the signal

generated

for

the

tion has been loaded into the Instruction Register

one of several

signals

(IR) the A Fork begins to generate an address. Be-

Fork

generate

cause this address must be available within one ma-

address.

logic

same

fork.

RACE A0 RABOO is
used
bit

by the A
0

of the

chine cycle, the A Fork is designed to operate at
maximum speed. Therefore, the amount of decod-

Branch instructions are described separately in Para-

ing is minimized: classes of instructions are recog-

graph 1.4.6.4.

nized and the bits that differentiate members of the
class are used directly as low-order bits of the generated address. This technique can be understood by
examining the address utilization by the forks. As

Table 1-5 shows the RAB bits asserted by each in-

an example, consider the selection of addresses by

1.4.6.3

the A Fork for the group of instructions ranging
from HALT to RTT. The binary op codes for all

RACE A0 RAB (02:00)

these instructions are identical except for the three

RACE A0 RAB0OO L, RACE A0 RABOI

least-significant bits. When the A Fork decode logic

RACE A0 RABO2 L are used to generate micro-

struction on the A Fork.
Instructions Other Than Branch

L, and

recognizes that all but the three least-significant bits

program addresses 001 - 007. No other A Fork bits

are 0, bit 3 of the ROM address is set, and the

are enabled when these gates are enabled. The en-

three least-significant bits of the op code become

abling conditions for all three signals are identical,

the three least-significant bits of the address.

except that each signal corresponds to a different
bit of the Instruction Register. The IR bits passed

1.4.6.2

through the AND-NOR gates are the destination-

Address Bit Generation - The logic shown

on drawing RACE generates address bits for cer-

mode bits for instructions that require Destination

tain

then

Address Calculation (DAC), but no source address

ORed with other signals that generate the same bits

calculation. If the destination mode is 0, the destina-

for other classes of instructions to generate the A

tion data is in the Destination Register and no ad-

FFork address. The address is then combined with

dress calculation is required.

classes

of instructions.

These

bits

are

I1-1-42

This group of microprogram words is used for the
following groups of instructions:
1.

IF SMO:
01 SS DD

MOV

11SSDD

02 SS DD

CMP

12SS DD

All single-operand instructions (with op
codes of 005XDD, 105XDD, 006XDD

03 SS DD

BIT

13 SS DD

BITB

04 SS DD

BIC

14SS DD

BICB

and 106XDD); this includes the instruction group from CLR to ASL (in both
word and byte forms), the variable address-space moves, SXT, and XOR.
These instructions are recognized by
their op codes and generate the signal

05 SS DD

BIS

15SS DD

BISB

06 SS DD

ADD

16SS DD

SUB

RACE RCLASS H.

The

and

memory

RACE A0 RABO3

RACE A0 RABO3 L is generated for the following
groups of instructions:
1.

instruction

330 - 336. Refer to Paragraph 1.4.6.4.

tions is decoded, the signal RACE
(MUL:ASHC+MFP) H is generated.

Op codes 000000 - 000007; these instructions range from HALT to RTT and use

Any binary instruction with a source
mode of 0. Because the source data is already in the Source Register, it is not
necessary to do the source data fetch.
These instructions generate the signal
RACE BIN*SMO0 H.
instructions JMP,

JSR,

SWAB. These three instructions use the
same address calculation as the singleoperand instructions. The signal RACE
JMP + JSR + SWAB H is generated.

microprogram addresses 010 - 017 (017

is for op code 000007 and traps through
location 4).

The instructions in this group are:
00 00 00

HALT

00 00 04

10T

00 00 Ol

WAIT

00 00 05

RESET

00 00 02

RTI

00 00 06

RTT

00 00 03

BPT

00 00 07

E/class instructions, with the exception
of the binary instructions that have both
SMO0*DMO, if these instructions have a
DF7 or there is a BRQ to be serviced

The instructions that use AO RAB(02:00) are listed
below:
00 01 DD

JMP

07 OR SS

MUL

0003 DD

SWAB

07 IR SS

DIV

00 4R DD

JSR

07 2R SS

ASH

00 50 DD

CLR

07 3R SS

ASHC

00
51 DD

COM

074R DD

XOR

0052 DD

INC

1050 DD

CLRB

0053 DD

DEC

1051 DD

COMB

00 54 DD

NEG

1052 DD

INCB

instructions accompanied by a

Request (BRQ); these instructions

generate A Fork addresses ranging from

and ASHC. When one of these instruc-

three

Branch

Bus

group, which includes MUL, DIV, ASH,

The

MOVB
CMPB

(DF7+BRQ). These instructions all go
to address 030 because AFIR(05:03) are
all 0s, which causes RACE RAB(02:00)
to be negated. RACF A2 RABO3 asserts
bit 3 for BIN*SM0*DMO0*(DF7+BRQ).
The instructions in this group are:

00 55 DD

ADC

1053 DD

DECB

0003 DD

SWAB*DMO

00 6! DD

00 56 DD

SBC

1054 DD

NEGB

00 50 DD

00 57 DD

TST

1055DD

ADCB

0051 DD

00 60 DD

ROR

1056 DD

SBCB

0052 DD

0061 DD

ROL

1057 DD

TSTB

00 53 DD

0062 DD

ASR

1060 DD

RORB

00 55 DD

CLR
COM
INC
DEC
ADC

00 63 DD

ASL

1061 DD

ROLB

00 56 DD

ROL
ASR
ASL
SXT
XOR
CLRB
COMB

00 65 SS

MEPI

1062 DD

ASRB

00.37 DD.

SBC
IST

0062 DD
00 63 DD
0067 DD
074R DD
1050 DD
1051 DD
1052 DD

INCB

00 67 DD

SXT

1063 DD

ASLB

00 60 DD

ROR

10 53 DD

DECB

I11-1-43

Table 1-5A
A Fork Address Generation

Instruction

ADC.B

ADD:

-SMO

ASH
ASHC

Class

P,E, DAC

AO RAB

00 1 01 | 02

Al RAB

{02

A2 RAB

03|

Address

& Flows

JSR

-DMO

J, FJ, DAC

See Table 1-5C

DAC
DAC

See Table 1-5C

ASL.B

P,E, DAC

ASRB DRO(0) |

P,E,DAC

052 (3)

053 (3)

See Table 1-5C

MOV

-SMO

0, E, BIN

See Table 1-5B

See Table 1-5C

MOVB -SMO

P, BIN

See Table 1-5B

MTP

See Table 1-5B
See Table 1-5C
See Table 1-5B
See Table 1-5C

SMO

I, E, BIN, DAC

See Table 1-5C

MUL

-DMO
DMO
NEG.B -DMO
DMO

See Table 1-5B

Branch Instructions: BLE, BLO, BLOS, BLT, BMI, BNE, BPL — Sge Table 1-7

BPT (OP3)
None
Branch Instructions: BR, BVC, BVS — See Table 1-7

CcCcoP
CLR.B

None
P, E, DAC

I, DAC
I, DAC

See Table 1-5C

P,DAC

See Table 1-5C

ROL.B

P, E, DAC

See Table 1-5C

ROR

P,E, DAC

See Table 1-5C

RORB DRO(0) | P,E,DAC
DRO (1)
P,E,DAC

See Table 1-5C
See Table 1-5C

RESET

Ix|

| x|[x

013(3)

044 (3)

P,DAC
None

RTI
RTS

None
None

SBC.B

P,E, DAC

I,E, BIN

See Table 1-5C
See Table 1-SB

COM.B

P, E, DAC

See Table 1-5C

SOB

None

DEC.B

P, E, DAC

See Table 1-5C

SPL

None

I, DAC
I, DAC

See Table 1-5C

CMP.B -SMO

SMO

DIV

-DMO
DMO

I, E, BIN, DAC

EMT

None

Floating Point:
-FP PRESENT
FP PRES

F,FJ

HALT

None

INC.B

P,E, DAC

10T

None

11-1-44

RTT

See Table 1-5C

051 (3)

000 (3)
000(12)
101 (2)

See Table 1-5C

SUB

014 (3)

See Table 1-5C

|01

A1 RAB

]021]o04

A2 RAB

03 | 05

Address

& Flows

X | X

046 (3)

045 (1)

X
X

047 (2)

050 (3)
X

1000(3)

|X | X

301(3)
015(3)

X |X

012(2)

X [X | X

040(2)
016 (2)
057 (2)

043 (3)

P,E,BIN
See Table 1-5B
P,E,BIN,DAC | See Table 1-5C

See Table 1-5C

SXT
pRAP

P.E, DAC
None

See Table 1-5C

I,E, DAC

See Table 1-5C

TST.B

X [X

P, E, DAC

WAIT

|07

000 (3)

SWAB

XOR

None

-SMO
SMO

|05

X
See Table 1-5C

{03

None
I, DAC
I, DAC

P, E, BIN
P,E,BIN,DAC |
P, E,BIN
P, E, BIN, DAC

L, E, BIN

DMO
-DMO
DMO

-SMO
SMO
-SMO
SMO

-SMO

MARK

DMO

MFP

Branch Instructions: BCC (BHIS), BCS (BLO), BEQ, BGE, BGT, BHI, BHIS — See Table 1-7

BITB

AO RAB

00 ] 01 I 02

See Table 1-5C

-DMO
DMO

BISB

Class

See Table 1-5C

BICB

Instruction

J,FJ, DAC

DAC

|01

-DMO

DMO

JMP

See Table 1-5B

P,E,BIN,DAC |

|07

See Table 1-5B

P, E, BIN

SMO

{0305

one
P.E, DAC

000 (3)

X
See Table 1-5C

011 (3

)

Table 1-5B
A Fork, BIN*-SM0

AO RAB

Al RAB
07

00
| o1

0NbW
-

03 | 05

A2 RAB
0s

XX X 3 XX x|

Mode

Source

Address

03 | 05

& Flows

021 (1)

022(1)

022 (1)

024 (1)
024 (1)

026 (2)

Table 1-5C
A Fork, DAC

Destination Mode

A0 RAB

02 | 03

-(DF7+BRQ)

BIN*(DF7+BRQ)

00 | 03

Address

& Flows

030 (3)

001 (5)
>

002 (5)

003 (5)

KX
XK K

A2 RAB

030 (3)

102
] 04

020 (3)

0: -BIN*(DF7+BRQ)

Al RAB
05

004 (6)

005 (6)
006 (6)

007 (6)

I1-1-45

1055 DD
10 56 DD
1057 DD
10 60 DD

ADCB
SBCB
TSTB

1061 DD
1062 DD
1063 DD

X /Class - The X/Class instructions, MARK, MFP

ROLB
ASRB
ASLB

with a destination mode of 0, and MTP, generate

addresses of 074, 046, and 045, respectively. RAB02
is forced to a 1, and the two low-order bits are the
complements of the corresponding bits from the Instruction Register. Bit 5 of the address is set by

RORB

RACF A2 RABOS L.

RACE A0 RAB04

RACE A0 RABO4 L is generated for any branch instruction. This signal is an input to bits 4, 6 and 7
of the microprogram address; as a result, all branch
instructions generate A Fork addresses with these
three bits set (addresses between 320 and 336). Re-

U/Class - U/Class instructions include three
groups: the binary instructions; the SOB instruction: and the MUL, DIV, ASH, and ASHC instructions with a destination mode of 0.

fer to Paragraph 1.4.6.4.

The Binary instruction use four microprogram addresses, 021 for SM1, 022 for SM23, 024 for SM45,
and 026 for SM67. These bits are controlled by
AFIR(11:09); bit 0 (A1 RABO0O) can only be set by
SM1 [RACH BIN*(-SMOIl) L]. Bit 4 of these addresses is set by RACH Al RABO04 [(-BF1=T7)*(BF1=0)*(-SMO0) = op codes with bits 14:12 from | 6 and not source mode 0]. The instructions in this

RACE A0 RABOS

RACE A0 RABOS L is generated for MUL, DIV,
ASH, and ASHC instructions with a destination
mode of 0, and for SOB instructions. RACE BIN L
climinates the binary instructions from U/class.
This RAB signal is also connected to RABO3 to
generate addresses ranging from 050 to 057.

group are:

These instructions are listed below:
07 OR SS
07 IR SS

MUL

07 3R SS

ASHC

DIV

07 7R NN

SOB

07 2R SS

ASH

01 SS DD
02SS DD
03 SS DD
04 SS DD
05 SS DD
06 SS DD

RACH A0 RABO7 is asserted for a NEG or NEGB
instruction with DMO. Together with RACH A2
R ABOO, it generates address 301.

RACF Al RAB(02:00)

RACF Al RABOO L, RACF Al RABOI L, and
RACF Al RABO2 L generate the three least-significant bits of the ROM address for the classes of instructions described in the following paragraphs.

HALT Through Op Code 7 - These instructions
generate microprogram addresses ranging from 010
— 017: the 1 in bit 3 of the address is generated by
RACE A0 RABO3 L. The following instructions

HALT
WAIT

group include:

00 00 02

RTI

00 00 03

BPT

00 02 OR
RTS
00 02 10
Unused
’
through

00 02 27
00 00 04
00 00 05
00 00 06

MOVB
CMPB
BITB
BICB
BISB
SUB

RTS:CCOP - Op codes 0002XX (RST:CCOP) use
addresses 040 - 044. Bit 0 of the address is set
when IR(05:03) = 3 (SPL), bit 1 when IR(05:03) =
2 or 3 (OP22, Flows 3 and SPL), bit 2 when
IR(05:03) = 4 (CCOP). Bit 5 of the address is set
by RACF Al RABO5. The instructions in this

arc included in this group:

00 00 Ol

11 SS DD
12SS DD
13 SS DD
14 SS DD
15SS DD
16 SS DD

MUL, DIV, ASH and ASHC with DMO0 and SOB
use addresses 050 — 053 and 57. Bits 11:09 of the op
code generate bits 02:00 of the address; bits 3 and 5
of the address is asserted by RACE A0 RABOS.

RACH A0 RABO7

00-00 00

MOV
CMP
BIT
BIC
BIS
ADD

Unused

SPL
00 02 3N
NOP
00 02 40
CCOP
00 02 41
through

10T

RESET
RTT

00 02 77

I1-1-46

CCOP

RACH A1 RAB04

RACH A2 RABO00

RACH Al RABO04 L is asserted for the following
instructions:

RACH A2 RABOO generates bit 0 and 6 of the
ROM address. It is asserted in the following cases:

Binary instructions with:

Both source and destination modes
0 (addresses 20 and 30);

Any

7 in this case.

source

mode

except

(ad-

dresses 21, 22, 24, and 26);

when

either

For branch instructions when RACF
TRUE] is asserted. Refer to Paragraph
1.4.6.4.

The instructions in this group are the fol-

lowing,

For NEG.B instructions with DMO, address 301. RACH A0 RABO07 asserts bit

SMO*DMO

SM(1:7).

For floating point instructions, address
101.

RACH A2 RAB(02:01)

01SSDD

MOV

11SSDD

MOVB
CMPB

02SSDD

CMP

12SSDD

03SSDD

BIT

13SS DD

BITB

04 SSDD

BIC

14SSDD

BICB

05SS DD

BIS

158S DD

06 SS DD

BISB

ADD

16 SS DD

SUB

R/Class

instructions

with

These bits are used by the branch instructions. Refer to Paragraph 1.4.6.4.
RACF A2 RAB03

RACF A2 RABO3 asserts bit 3 of the address for
E/class binary instructions (= both source and des-

tination modes equal to 0; no address calculation),
either when the destination field is 7 or a BRQ is to

be serviced. RACE A0 RABO3 asserts bit 3 for the

destination

non-binary E/class instructions.

mode 0, except MFP and the NEG.B instructions (addresses 20 or 30);

The instructions in this group are the following,
when SM0*DMO and (DF7+BRQ):

The instructions in this group are the following, when DMO:

01 SS DD

MOV

11SS DD

MOVB

02SS DD

CMP

12SS DD

CMPB

03SS DD

BIT

XOR

13SS DD

BITB

04 SS DD

1050 DD

BIC

CLRB

14 SS DD

BICB

1051 DD

05SS DD

BIS

COMB

15SS DD

BISB

06 SSDD

ADD

16 SS DD

SUB

0050 DD

CLR

07 4R DD

00 51 DD

COM

00 52 DD

INC

00 53 DD

DEC

00 55 DD

1052 DD

INCB

ADC

1053 DD

00 56 DD

DECB

SBC

RACF A2 RABO5

1055 DD

00 57 DD

ADCB

TST

10 56 DD

00 60 DD

SBCB

ROR

1057 DD

00 61 DD

TSTB

ROL

1060 DD

RACF A2 RABO5 asserts bit 5 of the ROM address for MFP instructions with DMO, and for
MARK and MPT instructions.

00 62 DD

RORB

ASR

10 61 DD

00 63 DD

ROLB

ASL

1062 DD

00 67 DD

ASRB

SXT

1063 DD

ASLB

SWAB

instructions

with

1.4.6.4
Branch Instructions — Table 1-6 lists the
Branch Instructions, their op codes and the condi
tions on which they branch.

destination

mode of 0 (also addresses 20 or 30).
RACF A1 RABOS

RACF A1
cept

when

codes.

RABOS5 is asserted for RTS:CCOP exIR(05:03) = 1 which are unused op

With the exception of BR, which always branches,
the branch instructions are grouped in pairs, each
of which checks one condition (e.g.: BNE and BEQ
check the Z bit). Bit 08 of the op code determines
whether the instruction branches when the branch
condition is true (1 or asserted) or false (0 or negated).

For example:

BEQ branches if Z=1.

I1-1-47

BNE branches if Z=0 and

Branch A Fork Address

RACF TRUEI! and TRUE2 are asserted when the

branch condition is met. TRUE1 checks the result

Table 1-7 shows the generation of RACL

TRUE2 does the same for branches with a 0 in bit

Refer to Flows 1. Branch instructions (BXX) are

RADR(07:00) for branch instructions.

of branches that have a 1 in bit 15 of their op code;

15 of their op code. These two functions cannot

shown on three separate branches:

both be asserted at one time.

Table 1-6

Branch Instructions

Instruction

Branch

AFIR

RACF (See Note 1)

Condition

114

|13

|12 ] 11

[10]

09 | 08 | TRUE2 | TRUE1

Always

BNE
BEQ

Z
Z

0
0

0
1

X
X

0
0

BGE
BLT

NvV
NwV

0
0

1
1

0
0

0
1

X
X

0
0

BGT
BLE

Zv (NWV)
Zv (NWwV)

0
0

1
1

0
1

X
X

0
0

BPL
BMI

N
N

1
1

0
0

0
1

0
0

X
X

BHI
BLOS

CvZ
CvZ

1
1

0
0

1
1

0
1

0
0

X
X

BVC
BVS

\%
\Y%

1
1

0
0

1
1

0
0

X
X

BCC,BHIS | C
C
BCS,BLO

1
1

0
0

1
1

0
1

0
0

X
X

NOTE 1 — “X” in the RACF TRUE1 or TRUE2 columns means that the function is asserted if
the “Branch Condition” is asserted. For example, if the instruction is a BNE or a
BEQ, TRUE2 is asserted if the Z bit is set.

NOTE 2 — The op code (AFIR < 15:08) for each pair of Branch Instructions differs only inIfbitbit
08. If bit 08 is set, the instruction branches, if the Branch Condition is asserted.
08 is not set, the instruction branches if the condition is not asserted. For example:
BNE

Z=0
Z=1

BEQ

Z=0
Z=1

Branch
No Branch

No Branch
Branch

I1-1-48

BXX*BCOK (Branch OK
met).

this

case,

BXX.05

(all

identical)

= condition

BXX* - BCOK* - BRQ (condition not

BXX.00

met and no break request). Since BRQ is

cycles

are

executed.

not

true and

Since the branch is successful, the PC

branch,

plus the displacement is moved to PCA

FET.13.

and

PCB, a

the instruction

control

goes

does

not

FET.11

BRQ strobe is issued, the

IRD.00 is ended,

BXX* - BCOK* - BRQ (condition not

and the microprogram goes to FET.00.

met and break request asserted). Control

The instruction fetch sequence then fet-

remains

ches the instruction

BRQ must be serviced; the next states

bus cycle started

pointed to by the

with

are FET.0l

new PC.

the current PC,

but the

- FET.03, after which the

BRQ is serviced.

Table 1-7
Branch Instruction ROM Address

RACL RADR

Result

Next State

BCOK * -BRQ

FET.0X

BCOK * BRQ

FET.0X

-BCOK * -BRQ

FET.1X

-BCOK * BRQ

FET.0X

Input to RACL RADR (07:00):
RACH A2 RABOO = TRUE1 * BR INST
RACH A2 RABO1 = TRUE2 * BR INST
RACH A2 RABO2 = AFIRO08 * BR INST
RACE A0 RABO3 = BRQ TRUE * BR INST
0=-BRQ
1 =BRQ

RACE A0 RAB04 = BR INST

I1-1-49

specifications of the current instruction, and gener-

Refer to Table 1-7.

ates signals that control register selection and ad1.

RADRO04

dress calculation in the processor. The logic also

H are asserted (high) for all branch in-

generates addresses for the C Fork microprogram

structions by RACE A0 RABO4, which

address logic. The C Fork selects the address of the

RACL RADR(07:06)

H and

is a decode of all branch instruction op

next microprogram address when a destination oper-

codes.

and must be fetched.

RACL RADROS is negated (low) for all

Two 8251-1 BCD-to-Decimal Decoders are used to
recognize the source and destination modes, respec-

branch instructions.

tively, by decoding each 3-bit IR field. The source
3.

RACL RADRO3 is asserted (high) when

and destination modes determine the operations per-

BRQ is true during a branch instruction

formed in the fetching of operands; these signals

and negated when BRQ is not true. This

are used throughout the IRC module. Destination

bit is controlled by RACE A0 RABO3.

mode O is also used to separate the C Fork addresses

RACL RADRO?2 is asserted when bit 08

for

this

mode

and

all

other

destination

modes, by connecting IRCC DSTMO L to the C

of the op code is | (branch if condition

Fork input for bit 7 of the ROM address (as shown

true).

on drawing RACL) and connecting IRCC DSTMO0
H to the input for bit 6. In this manner, the C

RACL RADROI
A2

RABO!I

is asserted by RACH

when

RACF

TRUE2?

Fork

generates

program

asserted.

microprogram

addresses

ranging

from 202 - 211 for destination mode 0, and microaddresses

ranging

from

110

117

for

other destination modes.

RACL
A2

RADROO is asserted by RACH

RABOO

when

RACF

TRUEI

asserted.

The address generated by the C Fork logic depends
on:

It can be seen from Table 1-7 that a branch is suc-

For mode 0, whether or not the instruc-

cessful (BCOK) under the following conditions:

tion

F/class.

not

F/class,

whether the destination field is 7 or not,
[.

When the instruction requires a branch

and

quired (SRO = 1 or 0);

condition

false

not

(RAB02

TRUE!I

are asserted (RABOI

asserted

odd

byte swap is re-

0) and neither TRUE2 nor
= 0 and

For other modes, whether an odd byte

RABOO = 0).
N

whether an

swap is required.

When the instruction requires a branch

The C Fork multiplexer is 74S157 4-bit 2-Line-to-1-

on condition true or asserted (RAB02 =

l.inc

1) and either TRUE2 or TRUEI are as-

DSTMO L. Recognition of destination mode 0 gen-

serted (RABOI = | or RABOO = 1).

crates the four low-order bits of the microprogram

Multiplexer

that

controlled

IRCC

address for the C Fork. The two high-order bits are

branch

the

directly controlled by the destination mode and bits

above conditions are not met, i.e.. RABO2 asserted

4 and 5 are always 0. Bit 3 of the address is always

and

neither

not

successful

TRUEI

nor

(-BCOK)
TRUE2

when

asserted,

if the destination mode is not 0 (the input is a

RABO2 not asserted and either TRUE!I or TRUE2

ground which generates a low output, which asserts

asserted.

the

input

to the microprogram

address assembly

logic on drawing RACL). For destination mode 0,
bit 3 is controlled by the instruction class; the bit is
1.4.7

set for F/class instruc tions and clear for all others.

C Fork Logic

Refer to drawing IRCC. The logic shown on this

Table

drawing

outputs.

decodes

the

address

modes and

I1-1-50

1-8

summarizes

the

Fork

multiplexer

Table 1-8

C Fork Address Generation

Instructions

Flows
Adrs

DMO * -F/Class

ROM Cycle
Name

C Fork Multiplexer
Output: IRCC CO RAB

Input
Enabled

202

D07.00

203

D07.10

204

D00.80

205

D00.90

DMO * F/Class

211

FOP.50

DM12
* SRO (1)

110

D12.90

DM12 * SRO (0)

111

D12.80

DM3 * SRO (1)

112

D30.90

DM3 * SRO (0)

113

D30.80

DM45 * SRO (1)

114

D45.90

DM45 * SRO (0)

115

D45.80

DM67 * SRO (1)

116

D67.90

DM67 * SRO (0)

117

D67.80

* DF7 * SRO (1)

DMO * -F/Class

* DF7 * SRO (0)
DMO * -F/Class
* .DF7 * SRO (1)

DMO * -F/Class
* -DF7 * SRO (0)

1.4.8

B Fork Logic

instructions may require a byte swap during the exe-

Refer to drawing IRCB. The B Fork logic gener-

cution

ates microprogram addresses that are used to select

that permit a separate byte-swap operation for odd-

the next machine state after the destination operand

byte data.

cycle,

and

must

use other

machine

states

has been fetched. For each instruction that operates
on a destination operand, there is a unique micro-

The B Fork addresses are generated by a 745157 2-

program word that controls the execution of the op-

input,

cration for that instruction. The majority of these

gates. IRCB BO RAB0O4 L is connected to ROM ad-

instructions are included in the P/class group. The

dress bits 4 and 5, to generate ROM addresses rang-

P/class instructions are executed by a single micro-

ing from 60 - 67. IRCB BO RABO3 L is connected

4-bit

multiplexer,

and

two

additional

program word that is stored in ROM location 031,

to ROM address bits 3 and 4, to generate ROM ad-

with the exception of the NEG, ASRB, and RORB

dresses ranging from 31 — 36. The ROM addresses

instructions. The exceptions are made because these

used by the B Fork and the instructions executed
by cach address, are listed in Table 1-9.

II-1-51

Table 1-9
B Fork Address Generation

Instructions

P/Class * -[(ASRB

Flows

ROM Cycle

IRCB Multiplexer

Other

Adrs

Name

Inputs
Enabled

Outputs
Asserted

Signals
Asserted

031

EXC.00

B0 RABOO

BO RABO3

033

TST.10

B0 RABO1

B1 RABOO

+ RORB) * DRO (1) + NEGB]

TST.B + BIT.B + CMP.B

B0 RABO3

JSR

034

JSR.00

B0 RABO2

B0 RABO3

JMP

035

JMP.00

BO RABO2

B1 RABOO
B0 RABO3

F/Class

036

FOP.40

B0 RABO1
B0 RABO2

MUL

060

MUL.80

B0 RABO4

DIV

061

DIV.00

B0 RABOO
BO RABO4

ASH

062

ASH.00

B0 RABO!1
B0 RAB04

ASHC

063

ASC.00

B0 RABOO
B0 RABO1
B0 RABO4

[ASRB + RORB] * DRO (1)

064

SHR.00

B0 RABO2
BO RABO4

MFP

066

MFP.00

B0 RABO1
B0 RABO2

B0 RABO4

NEG

067

NEG.00

Multiplexer disabled,
output all 1s.

Note: All Signals on IRCB.

I1-1-52

B0 RABO3

When the multiplexer is disabled for a NEG instruc-

The four condition-code bits, N, Z, V, and C, are

tion, the outputs are all Is: this generates address

stored in the four least-significant bits of the Pro-

67. For all other addresses, the inputs are selected

cessor Status (PS) word. The remaining bits of the

by a signal that is generated for the MUL, DIV,

PS. and the PS loading and reading logic, are on

ASH,

the

ASHC,

ASRB,

RORB,

and

MFP instruc-

PDR

module

and

are

shown

drawing

tions. When this signal is asserted, the B inputs of

PDRD.

the

The condition codes are normally loaded to reflect

multiplexer are used;

RAB04 is forced to a

(Refer to Chapter

3, Control

Registers.)

logic I by a 0V input. Conversely, the A inputs are

the result of each instruction that operates on data.

used for F/class, J/class, K/class, and most P/class

When this is done (by clocking the data inputs to

instructions; RABO4 is forced to a 0 by a +3 V in-

each flip-flop), each bit takes on the value of the

put. The instructions that use the A inputs of the

corresponding signal from the condition code gener-

multiplexer also assert IRCB BO RABO3 L. IRCB

ation logic on drawings IRCE and IRCF. Two Z

BO RAB(02:00) L are generated by connecting the

bit flip-flops, provided to avoid the delay of a final

instruction group signals to the multiplexer inputs

stage OR gate before the clock time, are shown on

in the order required for each signal.

drawing IRCF.

1.5

Clocked Inputs - IRCH CCLK H clocks the condi-

CONDITION CODES

The four least-significant bits of the PS word con-

tion-code

tain the processor condition codes. These bits store

ROM cycle (T6 is the T1 of the following cycle) ex-

flip-flops

immediately

following

each

information about the value resulting from data ma-

cept when the clock is inhibited by a value of 2 in

condition

the Condition Code Load (CCL) bits in the micro-

codes are not altered to reflect the results of ad-

program. In many cases where the condition codes

dress calculations, but are changed only when an in-

are clocked, individual bits may remain unaffected

nipulation

during

instruction.

The

by loading the bit from itself, through the com-

struction explicitly operates on a unit of data.

binational logic that generates the condition codes.
The condition codes can also be set to any specific

value by transferring a word containing that value

BR Inputs — The condition code flip-flops can be

to the PS address. The value of the condition codes

loaded directly from the BR. This is done whenever

are altered by every interrupt or trap response func-

the bus address transmitted by the processor ad-

tion, and by every RTI or RTT instruction. In addi-

dresses the low byte of the Processor Status (PS)

tion,

word. UBCB CC DATA (1) H indicates this condi-

individual

condition-code

bits

may

manipulated directly, with the condition-code oper-

tion and is used to gate the BR bits into the direct-

ate instructions. These instructions provide a means

set and direct-clear inputs of the flip-flops. Com-

to set
with

any one, or more, of the condition codes
a

single

instruction

that

requires

only

one

plements are applied to set and clear inputs, so that

cach flip-flop is correctly set or reset.

memory reference; a similar set of instructions can
clear any one or more bits. The condition codes are

IR Inputs - A third method of modifying the condi-

used in conditional branch instructions, so the vari-

tion codes allows bits to be set or cleared directly

ous means of manipulating the condition codes are

from the CCOP instruction. The four least-signifi-

uscful because they permit setting up the PS word

cant bits of the IR are connected to either the set

to respond in a particular way to various branch

or clear inputs of the flip-flops, but not both. The

instructions.

selection of inputs is done by two enabling signals

1.5.1

The same polarity inputs from the IR are used for

that are generated from opposite polarities of IR04.

Condition Code Storage

Refer to drawing IRCH. The circuits shown on the

either setting or clearing; only bits which are Is in

top half of this drawing are used to store the pro-

the

cessor condition codes; the remainder of the draw-

affected.

shows

circuits

concerned

with

are

altered,

the

remaining

bits

are

not

the subsidiary

ROMs used in condition-code calculation, instruc-

When the condition codes are set or cleared from

tion

the IR, the normal clocking of the flip-flops is in-

decoding,

(ALU) control.

and

Arithmetic

and

Logic

Unit

hibited. When the condition codes are loaded from

I1-1-53

the BR, the loading signal is present beyond the
time when the data inputs are clocked, so the BR
inputs take precedence. Unless one of these two
conditions is true, the normal clocked input is used.

INSTR

DECODE

ROM,

both

SUBROM Address Generation

1.5.4

IRCH SUBROM(04:00) H is the address, for the
Condition Code Control and Instruction Decode
ROMs: it is also the address for the ALU Control
ROM (refer to Chapter 2). This address is generated from IRCA IR(15:06), by the two multiplexers

The Z bit is stored in two flip-flops shown on drawing IRCF. The flip-flop outputs are ORed to generate the value of the condition-code bit. If either
flip-flop contains a 1, the Z bit is considered to be
a 1. Both flip-flops are set or cleared together when
either the BR or IR bits are transferred to the con-

and the OR gate on drawing IRCH.

Each subsidiary ROM contains 32 8-bit words. The
32 addresses are organized as follows (addresses in

dition codes.

octal):

1.5.2 Condition Code Load Field
The Condition Code Load (CCL) field of the ROM
is decoded as shown on drawing IRCF to determine how the PSW condition-code bits are to be altered. The CCL field is summarized in Table 1-10.
1.5.3

the

and

ROM

shown on IRCH.

Instruction Dependent Control

When CCL = 1, the Condition Code loading is instruction dependent, i.e., controlled by the operation code field of the instruction; this control is

Addresses 0-7 are used for instructions
with op codes containing 06 in IR
(14:09). These include the rotates, shifts,
MARK, MFP, MTP, and SXT.

Addresses 10-17 are used for instructions with op codes containing 05 in IR
(14:09). These are the single-operand
instructions.

implemented by two subsidiary ROMs, CC CNTL

Table 1-10

Condition Code Load

RACA UCCL

Output Asserted IRCF:

Function

CC NON AFF L

CC INSDEP H

(IRCH SETCC H)*

Set or clear CC; dependent upon IR.

CCFP LOAD L

Load CCs from floating-point processor

CCLD4

No change

Instruction-dependent. Condition codes determined by
subsidiary CC CNTL ROM.

Z and N: ACC SHFR
Cand V:

CCLDS

Z and N: ACC SHFR
C:

AMXI5S

V: Vold + (AMX ¥ ALU)

CCLDé6

N, C, and V: not affected
Z:

CCLD7

7* SHFR =0

Z, N, and V: not affected
C:

carry

* Generated on drawing IRCH.,

I1-1-54

¢.

Addresses 20-27 are used for binary in-

1.5.5

structions [IR (14:12) contains any value

The C (Carry) bit of the PSW is set when a pro-

C Bit Data

from 1 to 6].

cessor operation causes a carry out of the most-significant bit. The logic that generates the C bit data

Addresses 30-37 are used for the register

is shown on drawing IRCF. Figure 1-13 is a sim-

destination instructions, which have a 7

plified

in IR(14:12). These include multiply and

CDATA L. Each AND gate input covers a group

divide, the long shifts, and XOR.

of instructions that could cause a carry. The nota-

diagram

of the

logic

that

asserts

IRCF

tion adjacent to each AND gate indicates the condi-

Instructions included in a. and b. above, have sub-

tions or instructions that enable the gate and the

rom addresses equal to IR(09:06) via the D inputs

resultant C bit source that asserts IRCF CDATA

to the multiplexers; SUBROMA4 is low.

SUB-

Table

1-12

ROMA4 is asserted, SUBROMAZ3 is driven by a

CNTL

ROM

For

the

destination

instructions,

lists

the

instruction-dependent

outputs that control

the C bit for

+3 V input to the multiplexer, and the remaining

cach group ofinstructions. IRCE WOB CARRY H

three address bits take on the value of IR (11:09)

and

through the C inputs of the multiplexer. For binary

74S153 multiplexer. These C bit inputs are deter-

instructions,

mined from AMX 00, AMX 07, or AMX 15,

the

B inputs of the multiplexer are

IRCE

LOB CARRY

are derived

from

used: SUBROMAA4 is asserted and SUBROMAZ3 is
1.5.6

clear. This data is summarized in Table I-11.

N Bit Data

The N (negative) bit of the PSW is set when a nega-

The SUB instruction is treated specially, to separate

tive

the ADD and SUB instructions when generating

The logic that generates the
N bit data is shown on

result is produced by a processor operation.

ROM uaddresses. Both SUB and ADD would nor-

drawing IRCF. Figure 1-14 is a simplified diagram

mally

of the logic that asserts IRCF NDATA L. Each

generate

ROM

address

(the

codes

differ only in bit 15). When the SUB instruction is

AND gate input decodes a particular group of in-

decoded, the four least-significant bits of the ROM

structions or processor operations for which a nega-

address are forced to Os to generate address 20. Ad-

tive result might be obtained.

dresses 27, 35, and 36 are not used. For the SWAB
instruction, which is not in any of the four groups

For most of the instructions, the CC CNTL ROM

that generatc ROM addresses, the contents of the

outputs IRCH

IR gencerate the same ROM address that is used for

arc asserted. These control outputs condition the

MODZN H and IRCH

ENZN H

the ASL instruction. The signal IRCH SWAB L is

NDATA logic to examine the SHFR output to de-

used

termine when the N bit should be set. For word or

distinguish between

the two instructions.

The UALU signals are used to recognize that the

odd-byte

ALU control is instruction-dependent, and that the

SHEFRAIS, and sets N accordingly. For byte oper-

outputs

ations, the input C logic tests SHFRAO7. These in-

the

ALU

control

ROM

drawing

operations,

the

input

logic

puts control the N bit for most operations.

GRAA are active.

Table 1-11
Subsidiary ROM Address Sources

Type of
Instruction

ROM Address

Multiplexer

Input
Selected

Subsidiary ROM Address Source

Select
S1

IR(14:09) = 05 or 06

IR09 | TRO8

|IRO7 | IRO6

IR11

|IR10 | IRO9

IR14

JIR13 | IRI12

Binary

Not used

I1-1-55

Not Used

tests

IRCF CCLD 7 L

IRCE WOB CARRY H

WORD OR ODD BYTE CARRY

IRCE LOB CARRY H

LOW BYTE CARRY:C+— AMXO7

Ce—CARRY

IRCH CMOD 1 H

{>o—<>—|-——/

CDATA L

ROM D10:Ce— ALUCN

IRCH CMODO H

\ IRCF CEN1 H=ENC#cCC INSDEPA

IRCH ENC H

CCLD 7+ROM 100:C-ALUCN
ASH: C—AMX00

GRAA AMX O%ASH L
DAPJ ALUCN L

IRCC CC INSDEPA H

IRCF

GRAD DROO H

IRCH CMODO H

ASHC:Ce~ DROO
+5V

MUL: Co=X

IRCF CEN2 H=ENC*CC INSDEPA* -CMOD1

IRCH CMOD1H

l |>° -

(1) H)« IRCF X L
(1)+ (DR15S*BR=-1 SAVE
-DR15%Z

ENC*C(I:RCE CCe—BR H=(PS LOAD+LOAD FCC)

LOAD PS+ LOAD FCC

DAPA BROO H

INSDEPA *MOD1

IRCF CC NON AFF L
IRCF CCLD6 L

CCLD6
+ CC NON AFF + ROM101:

NON - AFFECTED

IRCE PS LOAD L
IRCHC()H
IRCE LOAD FCC L

Figure 1-13

11-0793

Sources of C Bit Data, Simplified Diagram

IRCF CCLD4 L

IRCF CCLDS L

INPUT A
IRCH MODZN H

INCH SwAB L

{ WORD +08 SWAP)(C(%LD‘« +5+SWAB*MODZN®ENZN)

DAPJ SHFRA13 H

SHFRA 15=1:N
2

GRAA WORD+0OB SWAP H———iD*_____‘
13

DO—MODZN H
IRCF NEN1 H

INPUT B

CMP.B SHFR <0: N1
TRCF NDATA L

DAPJ SHFRAO7 H

INPUT C

SWAB +(WORD+0B) SWAP
MODZN H

SWAB+WORD+
0B SWAP
SHFRAOT=1: N

GRAA WORD+0OB SWAP L.

-IRCE PS LOAD H

IRCE LOAD FCC HE——— 2
IRCH N (1) H

IRCF CCLD 67 L

IRCF CC NONAFF L
IRCH ENZN H

IRCH CC
INSDEP H

DAPA BRO3 H
IRCF MUL+DIV NZV EN H

INPUT D
CCLDB7+MUL+DiV:
N NON AFFECTED

INPUT

D LOAD PS+ LOAD FCC

IRCE CC+-BRH

IRCH MODZN H

IRCF CHECKZ H

IRCF CCLD6 L

Figure 1-14

Sources of N Bit Data, Simplified Diagram

I1-1-56

1n-0794

Table 1-12

(_3 Bit Data Sources

CC Control ROM

CMODI1

CMODO

ENC

Source

ROR.B, ASR.B

C < AMX00 (VMODO=1)

ROL.B, ASL.B

C < AMX08 (WORD)

ASHC

C < DROO

COM.B, NEG.B,

C <«-ALUCN

MUL

C+«-X

CLR.B, ADC.B TST.B

C < ALUCN

C < AMXO00

non-affected

C+<1

C < AMXO08 (OB)

SBC.B SUB

CMP.B, ADD

ASH
MFP, MTP, SXT
INC.B, DEC.B

MOV.B, BIT.B, BIC.B
BIS.B, XOR

DIV

‘

C < 0if-DR15

C<«0

SWAB
Condition-Code Load Signals

IRCF CCLD4

C+0

IRCF CCLD5

C < AMXI15

IRCF CCLD6

non-affected

IRCF CCLD7

C < ALUCN

I1-1-57

The input B logic tests for CMP.B instructions. Under these conditions, if SHFRAI1S is 0, the N bit is

set, and if SHFRAIS is 1, the N bit is cleared. Input D covers all cases where the N bit is not af-

fected

by the current operation, and is therefore

reloaded with the previous content, IRCH N(1) H.
Input E allows IRCF NDATA L to be asserted by
BRO3 for load PS and load FCC functions. Table
I-13 summarizes the sources of N bit data.

1.5.7

Z Bit Data

The Z (Zero) bit of the PSW is set when the result
of a processor operation is 0. The Z bit data that
controls the condition code is generated by logic on

drawings IRCF and GRAB.

ZDATAI

Sources - The input gates that assert
IRCF ZDATATI L cover the special conditions that
control the Z bit, independent of the SHFR outputs being equal to 0. For example, during the DIV

instruction

execution, MODZN and ENZN are
both low and the Z bit is set. For the special case
of the CMP.B instruction, the logic tests for the

SHRF output = 1 condition to determine the Z bit.
The other input gates that assert IRCF ZDATAI L
test for load PS or load FCC operations and operations that have no effect on the Z bit. Under the

former conditions, the Z bit is loaded from BRO2

Figure 1-15 is a simplified diagram of the logic that
asserts IRCF ZDATAI

These outputs are clocked into the Z1 and Z2 flipflops, whose contents are ORed to provide the Z
bit of the PSW condition code.

L and GRAB ZDATA2 L.

and

under the

latter conditions, the Z bit is un-

changed [Z(1)H controls ZDATA1]. These special

conditions are summarized in Table 1-14.

Table 1-13
N Bit Data Sources
.

Instruction

CMP.B

CC Control ROM

IRCF NDATA L

Source

MODZN

ENZN

N« 1if-SHFRA15=1
N < 0if SHFRA15=1

DIV

non-affected

MUL

non-affected

all other instruction-

dependent codes

N « 1 if SHFRA15=1

(word or odd byte)

N < 1 if SHFRAQ7 =1

(byte)
SWAB

N < 1 if SHFRAO0S = 1
Condition-Code Load Signal

IRCF CCLD4

N «<if SHFR =0

IRCF CCLD5

N «<if SHFR =0

IRCF CCLD6

non-affected

IRCF CCLD7

non-affected

II-1-58

IRCH MODZN HAD&—T‘IRCF SET V H

DIV:Ze—1

IRCF MUL+DIV NZVEN H
IRCF

CCLD7

IRCF CC NONAFF

CCLDT: NON AFFECTED

IRCH PS LOAD LE]D_J

IRCE CCaBR HEE

H
IRCH Z (1)

IRCH LOAD FCC L

DAPA BRO2 H

IRCF NEN1 H=CC INSDEP&EN‘ZN
IRCF ZINV H=

DAPJ

o Po+ LOAD FCC

IRCF ZDATA1

CMP.B (SHFR=1) Z«—1

-~MODZN

A=B(15:8) +BYTE H
DAPF A=8(7:0) H

21 T

—Jdc

:D—IRCHZH)H

+5vV

DAPJ, H SHFR <15:08> H—

HEX

IRCE EN HIB H=BYINAxMODZNxNEN1 2

IRCE EN WORD H=(CCLD4+5)+
MODZN*NEN1)

INVERTERS 5y
%

DAPJ, F SHFR <07:00> H

HI BYTE:=0

'12
IRCH Z (1) H—

IRCF CHECKZ H 13

WORD=0

CCLD&+MUL: SHFR=0
Z<+—2 OLD

IRCH CC CLK H

Figure 1-15

—1RCH Z2 (1)L

GRAB ZDATAZ L |oy,

0_4|

(WDIN*-SWAB*

GRAA 0B SWAP H—

IRCF Z1 (1) L

Z Bit Data, Simplified Diagram
Sources of

Table 1-14

Z Bit Data Sources

Instruction

CC Control ROM
MODZN

ENZN

CMP.B
MUL
DIV

0
1
0

1
0
0

all other instruction-dependent codes

SWAB

Z Data Source

=1
Z< 1if SHFR
if SHFR =0
Z<2(HH
Z<1
Z < 1 if SHFR (07:00)=0
Z <« 1if SHFR=0

Condition-Code Load Signals

Z < 1if SHFR=0
Z< 1if SHFR=0
Z< Z(HH if SHFR =0
non-affected

IRCF CCLD4
IRCF CCLD5
IRCF CCLD6
IRCF CCLD7

I1-1-59

ZDATA2 Sources - The logic that generates
GRAB ZDATA2 L tests the SHFR output for 0.
The open-collector inverters function as 0 detectors

for SHRF(15:08) and SHFR(07:00). The enabling
inputs, IRCE EN HIB H, IRCE EN LOB H, and
IRCE EN WORD H are used to test each byte of

the SHFR separately, or together. The additional
GRAB ZDATA?2 gate tests the SHFR output word

for 0 under CCLD6 or

SHFR

MUL conditions.

arithmetic operations,

operations and other special cases determine IRCE
VDATA L. To simplify the description, arithmetic
operations and special cases are grouped as VENI

inputs. Word and byte operations are grouped as

If the

sources of both groups.

VENI

Figure 1-16 is a simplified diagram of the V bit
data sources that are grouped in the VENI cate-

V Bit Data

The V (overflow) bit of the PSW is set when a processor operation

of instructions:

and word or byte operations. The results of these

VEN2 inputs. Table 1-15 summarizes the V bit data

output is 0, the previous Z bit condition,
Z(1)H, controls the new Z bit.
1.5.8

drawing IRCE. The V bit is affected by two broad

categories

gory. A 748153

results in an arithmetic overflow.

Dual 4-Line-to-1-Line Multiplexer

is used to select the most-significant BMX bit for
the arithmetic operations that involve the B input.

The logic that generates the V bit data is shown on

Table 1-15
V Bit Data Sources

CC Control ROM

Instruction

IRCE VDATA L Source*

VMODI1 | VMODO | ENV

VENI
INC.B, ADC.B

V «<-A*ALUI5

DEC.B, SBC.B

V < A*-ALUI1S

NEG.B, ADD

V < A*B*~ALUI1S5 + -A*~B*ALUI5

SUB, CMP.B

V< A*-B*~ALU1I5 + -A*B*ALUI5

VEN2

MFP, MTP, SXT, CLR.B, COM.B,

V<0

DIV

V<l

ROL.B, ASL.B

V < SHFRAL1S5 ¥ AMX15

ROR.B, ASR.B

V < SHFRA15 ¥ AMXO00

TST.B, MOV.B, BIT.B, BIC.B,
BIS.B, MUL, ASH, ASHC, XOR

Condition-Code Load Signals
IRCF CCLD4

V<0

IRCF CCLD5

(VEN2)

V «Vold + (SHFRA15 ¥ AMX15)

IRCF CCLD6

(VEN1)

non-affected

IRCF CCLD7

(VEND)

non-affected

*A = DAPJ AMX SIGN H
B = DAPD BMX15 H (word) or DAPC BMX07 H (byte)

ALU15 = DAPJ ALU SIGN H

I1-1-60

IRCF CC INSDEP H

IRCH ENV H

IRCE VENI L

DAPC BMXO7 H

V—D!‘r

1 9

DAPJ AMX SIGN H

VMODO: A*EiA—L—U

VMODO: A xB»ALU

—@

10
4

IRCH

VMOD!

-5

DAPJ ALU SIGN H

rolZ

11,12

VMODO:
A B % ALY

A% B % ALU
L VMODO:

—#

13]

DAPD BMX15 H
St

RCD BYINA H
IRCD

IRCH VMODO H

)o—Emcs VDATA L
FROM

IRCE

CC+—BR

DAPA BRO1

IRCF MUL+DIV

VMOD1[BYTE

H|vMODO H|

|0 (WORD)

1
1 (BYTE)
1|1

)
1

—

IRCF SET

IRCH V (1) H

[-BMX15

IRCE

~BMX07| BMXO7
BMXO7 |—BMX07
0

FCC: Ve— BRO1

V H (= MODZN)

-BMX15 | BMX15
BMX15

NZVEN

LOAD PS+ LOAD
MOIV: Vo1

VEN2 LOGIC

FCC L

IRCE PS LOAD L
IRCF CC NONAFF L

LOAD

IRCF

CCLD5

NON AFFECTED

IRCF CCLD67 L
11- 0794

Figure 1-16

VENI1 Sources of V Data Bit, Simplified Diagram

These are NEG.B, ADD, SUB, and CMP.B, as in-

VEN2

dicated in Table 1-15. For these instruction-dependent codes, the CC CNTL ROM asserts IRCH
VMODI1 H, which gates the BMX outputs to the

data sources that are grouped in the VEN2 category. A 74S153 Dual 4-Line-to-1-Line Multiplexer

multiplexer inputs, and IRCE VENI L, which en-

selects the most-significant AMX bit for the word,

ables

odd-byte, or byte operations. The multiplexer truth

the

multiplexer.

IRCD

BYINA

selects

Figurc

1-17

is a simplified diagram of the V bit

BMXI15 or BMXO07 as the most-significant bit.
IRCH VMODO H selects the BMX bit or its complement at each output, as shown on the multi-

table 1s shown on

plexer truth table in Figure 1-16.

serts

Figure

1-17. The multiplexer is

only cenabled by CCLDS5, or those instruction-dependent codes for which the CC CNTL ROM asIRCH

VMODI

indicated in Table

and

IRCH

ENV

1-15, these instructions include

ROL.B, ASL.B, ROR.B, and ASR.B. For these in-

The notation on Figure 1-16 indicates the conditions and functions for which each AND gate input

structions, the notation on Figure 1-17 indicates the

asserts IRCE VDATA L.

conditions and functions for which each AND gate
input asserts IRCE VDATA L.

For INC.B, ADC.B, DEC.B, and SBC.B instruc-

For the majority of the instructions included in the

tion-dependent

codes,

VEN2 group of Table [-15, VMODI is low. As a

IRCH

H is low. As a result, the BMX

VMODI

CNTL

ROM

output

result,

the AMX

multiplexer is

not enabled

and

multiplexer outputs are always 0. For these instruc-

nonc of the AND gate inputs will be enabled be-

tions, B is eliminated from the source function, as

cause IRCE VEN L is not asserted. Therefore, pro-

listed in the source column of Table 1-15.

cessing these instructions clears the V bit.,

I1-1-61

IRCE VENZ
IRCH-SWAB
IRCH VMOD1
IRCF CC INS DEP
IRCH ENV

H
H
H
H

IRCE WOB CARRY H

[

IRCF
CCLD5 L

DAPJ SHFRA15 H

AMXO7x OB SWAP +
AMX15
% - 0B SWAP

hlu o

DAPB AMXO0O H

GRAA WORD +
OB SWAP H

IRCE

GRAA WORD +
OB SWAP L

DAPJ SHFRAOT H

FROM VEN1
LOGIC

'(WORD+OB SWAP)
(CCLDS5+VEN2)
* SHFRAOQ7

IRCF CCLD5 L

LOB CARRY = SHFRAO7

IRCH VMODO H

VMODO

» SHFRA{5

VDATA L

GRAA WORD +0B SWAP L ———I
WORD OR

(CCLDS +VEN2)

IRCE VEN2 L

00D BYTE

’(WORD+OB SWAP)

IRCF CCLDS L

DAPC AMXO?

’— wOB CARRY H» SHFRA1S

IRCE LOB CARRY H

IRCE

SWAP

xCCLD3

LOB CARRY

YES

IRCE

WOB CARRY
AMXO7 (ODD BYTE)
AMX15 (WORD)

YES

AMX00

NO
NO

NO
YES

AMXOT7
AMXO00

o)
o
t11-0792

Figure 1-17

VEN2 Sources of V Data Bit, Simplified Diagram

I1-1-62

CHAPTER 2
DATA PATHS

This chapter describes the Data Paths of the KB11-

The Source Register and Destination Register multi-

C Processor. The Data Paths consist of the logical

plexers (SRMX and DRMX, Paragraph 2.1.5) trans-

clements that execute the data manipulations re-

mit data from the GRs (including the PC or GR7)

quired by the Control section. The inputs to and

to the Source Register (SR) and to the Destination

the outputs from the Data Paths, as well as the

Data

Paths

themselves,

are

described

this

chapter.

The SR

and DR (Paragraphs 2.1.6 and 2.1.7), as

their name implies, are used for source and destina-

All the elements of the Data Paths logic are con-

tion address and operand storage.

trolled by the microprogram ROM; a separate field

this function, they are used as storage during cer-

In addition to

of the ROM output word controls each of these ele-

tain

ments. These fields, the values that they can as-

ASHC. The SR cannot change data, but the DR

sume, and the function executed by the logic unit,

can shift either right or left.

instructions,

such

MPY,

DIV, ASH and

are listed on the block diagram, Figure 2-1.
The Shift Counter (SC) is used only for instructions

The Arithmetic and Logic Unit (ALU), performs

that

most of the arithmetic and all of the logic (AND,

and ASHC. A value is loaded into the SC, which

OR. EXCLUSIVE-OR) functions required by the

counts to zero; at this time the instruction is com-

instruction set (Paragraph 2.1.1).

pleted. The DR is the input to the SC (Paragraph

require

multiple shifting:

MPY,

DIV,

ASH

2.1.8).

The ALU is the input to the Program Counter (PC)
and

the Shifter (SHFR). The

PC (Paragraph

The logic elements described above, plus the BR,

2.1.3) consists of two registers (PCA and PCB) and

and

is used both to keep track of the next program in-

KIMX) are the inputs to the ALU, via two multi-

the

Constant

Multiplexers

(KOMX

and

struction and as an auxiliary register during data

plexers (AMX and BMX). These two multiplexers

manipulation. The SHFR is the input to the Gen-

correspond to

cral

AMX. BMX, KOMX and KIMX are described in

Registers (GR) and to the Bus Register. The

SHER transfers data from the ALU or from the
PCB.

The

ALU

data

may

the A

and

B inputs of the ALU.

Paragraph 2.1.9.

be either unchanged,

shifted one bit to the right, or byte-swapped (Para-

The Bus Register Multiplexer (BRMX, Paragraph

graph 2.1.2).

2.2.1)

receives

data

from all

inputs to

the

Data

Paths and selects one for storage in the Bus Registers (BR and BRA, Paragraph 2.2.3) and, during an
The General Registers consist of two identical cop-

instruction fetch, into the Instruction Registers (IR

ies of 16 registers (00-17¢): one copy consists of the

and AFIR, Paragraph 2.2.4).

General Source (GS) registers, the other consists of
the General

Destination

(GD)

registers.

Both

The

inputs

the

BRMX

are

the

Cache,

the

these Copicey ewritten at “the shifie "fime and aré

SHE R, the Untbuk via the Bus Buffér Régister, and

identical (Paragraph 2.1.4).

the Internal Data Bus (INTD, Paragraph 2.2.2).

H-2-1

ALU

PCA(T2) [51]

(DAPF,H)

NO CLOCK

LOAD

pcB(T2)[50-49]
O NO CLOCK

PCB

(DAPF.H)

LOAD

SF7:LOAD

OF7:LOAD

A
L

SHF (T2) [48-47)

(ng,ffi 9

3 RIGHT SHIFT

Pcafl

O
1
2

SWAP BYTES
PCB
NO SHIFT

ALU(TY 17-15]

O NOT A
1B

2 A pLus B
ALU

0 KOMX
1 KIMX
2 SR
3

(DAPF,

BMX (T1) [21-20]

BMX
(DAPB,C.D)

M|
x|

M
|x

PANIVAN

APF,DAPH

]
|S

[

B8]
R|

PEPENDENT)

AMX (T1) [23-22)

AMX
(DAPB,C,D)

gOJLbJSSEAD

& INSTRUCTION
A MINUS B

FANVAN

(16 REGISTERS)
(GRAD.E.F.H)
£

0 DR
23 2%3

s||D

0 NO CLOCK

SRMX

[

LOAD

(GRAD F, H)

O SF

és

[43-41

)ec'%
SF

PWE (TH4) [45-44

]GS

SFvl

I (GRAD,E,FH)
DRMX

(GRAD,E FH)

O DON'T WRITE

DF
06

]

1 CONDITIONAL
23 NOT
WRITEUSED

DRX
(T2) [59-58]
0 SHER

23 DF7:SHFR.-DF7:GD
CLRDR

| |

]

SFvl

DRK (T2) [56 -551
0 NO CLOCK

1 SHIFT RIGHT |

(GRAJ)

SHIFT LEFT|
LOAD

BAX (TNC38-371

SHC (T1) [34-33)
? ESU%‘%””T

0 DR
21 gcas

2
3 LOAD
LOAD DR(50>
17

FP EALU (MAINT)

UNIBUS
ADDRESS

P
KOMX
(DAPD)

SHFR

(6RAD,E,FH)

3 NOT USED
SRK (T2) [57]

2 -SF7:65
2F7:sHFR,

PAD (T14)

(16 REGISTERs)| } SF DF
5 DF
(GRADEFH)
| 3¢ NOT
5 _ USED
5
67 06
LI

SRX
(T2) [61-60]
o SHER

sR]

> M

VIRTUAL

i | l ‘

(DAPB,
cD)

FROM FPP EALU
SHFR

INT DATABUS

(PDRA)
I ]

SHFR

(PDRJ)

1 BUS (DETERMINED
BY ADDRESS)

K1MX

NO CLOCK

1 LOAD

BRA

lDAPA)

(PDRB)

AFIR

(IRCA)

DATA TO/ FROM
UNIBUS( INCL.
CACHE 8 UNIBUS

(T3)

SHER

FROM Fg,fuusggé :>

IRK(T2)[46]

| O NOCLOCK

(RACJ) | 1 LOAD

MAP REGISTERS)

i T
Sk

> CE
A E

{}BR

(PDRF)

TRAP VECTOR

SOURCE

DEST. CONST.

CONST.

SOB & MARK OFFSET
BXX

OFFSET

1
2
3

READ SW
LOAD PS
READ PS

PIRQ

{}BR

{‘r
DATA
FROM FPP

DATA TO MEMORY
MGMT. REGISTER,

AND

Block Diagram

Data Paths

I1-2-2

FPP DATA

DATA T0O
CACHE
MEMORY

SL/PB

NO COMMAND

INTERNAL
DATA BUS

Figure 2-1

I
(PDRC) ] I
(PDRC)

IBS (T1) [36-35]
0

o
DATA FROM MEMORY MGMT,
SWITCH,CPU ERROR,AND

SYSTEM SIZE 8 ID REGISTERS.

xXZO

START VECTOR

!
(PDRB) l LDJ I (PDRD)

K1MX

] !BR

AV
V.

KOMX

{}BR

TO CONSOLE DATA LIGHTS

B8R

KMX (T1) [19-18]

CACHE
ADDRESS

BRK (T2) [63]

scQ)

DATA FROM
CACHE MEMORY

BRX (T2) [62]

BRMX

(DAPE)

WSSR,

(SAP,SSR

BUS BUFFER ¢

UNIBUS

MGMT

CACHE

SRCCON

DSTCON

ADDRESS

MEMORY

(PDRE)
11-2618

dress for transmission to Memory Man-

control on the basis of the microprogram word and
the current instruction. The manipulated operands
are selected by two multiplexers, one for each of
the ALU inputs. The operands can be the contents
of the SR, the DR, the BR, the PCB, or one of several numbers generated by the constant

agement from either the DR, the SR, or

multiplexers.

The outputs of the processor Data Paths select and

supply address, data and display information:
I.

The Bus Address Multiplexer (BAMX,
Paragraph 2.3.1) selects the virtual ad-

the PC.

The output of the ALU is gated either into PCA or
into the SHFR, from which it can then be routed

The (Unibus) Data Multiplexer (DMX,

Console and selects the source of the

to any of the General Registers, or to the SR, the
DR, or the BR (and the IR, although this path is
not used). All of these destinations for manipulated
data are internal to the processor; when data is
transferred out of the processor, it must go through
the BRA. When the ALU outputs are routed to the
PC, the signal paths do not pass through the
SHFR; this means that when shift or byte-swap operations are attempted with register 7 as the destination, the data that enters the PCA is unchanged.
FFor example, an ASR PC instruction does not shift
the PC but does set the condition code as would an

Console data display from the SHFR,

ASR.

Paragraph

2.3.2) selects the source of

data to the Unibus from the BR or from
the Control Registers (Chapter 3).

The BRA supplies data directly to the
Cache, the Memory Management registers, the Floating Point Processor and
the Control Registers (Paragraph 2.3.3).

The Display Multiplexer is controlled by
the Data Display selection switch on the

the FPP and CPU ROM Address Regis-

2.1.1.1 Description of ALU - Refer to drawings
DAPF and DAPH. The ALU does most of the

ters, the Light Register or the BR (Paragraph 2.3.4).

data manipulation in the processor. It operates on
2.1

two 16-bit words of data and a carry input to pro-

DATA MANIPULATION

duce one 16-bit word of data and a carry output.

Data manipulation is done mainly by the logic elements, shown in the top-half of the Data Paths

When the M input is high, the ALU operates in the

Block Diagram, Figure 2-1.

logical mode; when this signal is low, the ALU opcrates in arithmetic mode. The carry signals are not
active when the ALU is operating in the logical
mode. Drawing DAPF shows the low byte and
DAPH shows the high byte of the ALU.

The ALU is the most complex of these elements
and is the only one that can combine two operands.
It is the first one described. Its outputs are input to

the PC or to the SHFR, from where they may be
routed to the General Registers, to the SRs and
DRs and back to the ALU via the A and B
multiplexers.

2.1.1

Arithmetic and Logic Unit (ALU)
The primary data processing element in the KBI1-

C (the only element that can combine two operands
to form a result) is the Arithmetic and Logic Unit
(ALU). The ALU can perform a variety of arithmetic operations on two variables (such as addition
or subtraction) and can perform a variety of logical
operations on one or two variables, such as complementing or ANDing. The specific operation performed at any time is selected by the processor

The 16-bit ALU is implemented with four 74S181
4-bit Arithmetic Logic Units. Each 74S181 includes
look-ahead carry generation for the four bits. A second level of look-ahead carry generation Is provided by the 74182-1 Carry Generator. The carrypropagate (P) and carry-generate (G) outputs of
each 74S181 (except the most-significant four bits)
are connected to the corresponding inputs of the
74182-1, and the carry outputs of the 74182-1 are
connected to the appropriate carry inputs of the
ALUs. The least-significant bit carry input is controlled by GRAA ALUC H, based on the output
of the subsidiary instruction-dependent ALU control ROM.

I1-2-3

The ALU can perform any one of 16 logical functions (cach output bit is dependent only on the corresponding input bits) or any one of 16 arithmetic
functions (each output is dependent on the corresponding input bits and on a carry propagated
from less-significant bits). The selection of a particular function is controlled by five signals from the
GRA module which select the mode (arithmetic or
logical) and the function. The KB11-C uses only
ten of the possible 74S181 functions. These ten func-

DAPJ A = B(15:8) + BYTE H indicates
either that the high data byte is all Os or
that the processor is operating on byte
data. This signal is used in determining
whether all the active data is Os for the
Z condition code.

tions are listed at the bottom of drawing DAPF.

The low order byte of the ALU is controlled by the
SO - S3 inputs (DAPF LSO H - DAPF LS3 H) and
the M input (DAPF LM H). The high order byte is
similarly controlled by DAPH HSO H - DAPH
HS3 H and DAPH HM H. All of these signals are
derived from GRAA ALUSO L - GRAA ALUS3 L
and GRAA ALUM L.

In addition to the data and carry outputs, each
ALU c¢lement has a comparator output, which indicates (if the ALU is in subtract mode) that the
two inputs are cqual. These outputs, which are
open-collectors, are wire-ANDed for each data byte
to generate equality signals that are used in forming
the condition codes.

DAPJ ALUCN L is the carry output of

the active portion of the ALU; it takes
the carry output from the high byte for
word data or the carry output from the
low byte for byte data. This signal is
used to generate the Carry (C) condition
code.

2.1.1.2 ALU Control - During each machine cycle,
the ALU performs the function that is specified by
the ROM ALU control bits [RACC UALU(2:0)
H]. The signals that actually control the ALU (and
also the SHFR) operations are shown on schematic
GRAA.

If the UALU bits equal 0 - 6, the control signals are
independent of instructions being executed. If these
bits equal 7, the control signals depend on the
instruction code. In this last case (instruction dependent), the notation “$ALU” appears on the Flow
Diagrams.

The ALU control signals generated on the GRA

DAPEF A = B(7:0) H indicates that the inputs to
the low data byte are equal.

module are:

DAPF A = B(15:0) L indicates that the inputs to

the entire word are equal. DAPH BUS A = B(15:8)
H is the wired-AND of the A = B outputs for the
high-byte ALUs on drawing DAPH.

Four signals that are used in the generation of the
Condition Codes are derived from the ALU:

DAPJ AMX SIGN H is the sign of the
A input to the ALU. This signal corresponds to AMX15 if the processor is operating on word data, or to AMXO07 if
the processor is operating on byte data.

GRAA ALUS(3:0) L

(ALU SO - S3 control)

GRAA ALUM L

(ALU mode control)

GRAA ALUCH

(Carry in)

GRAA ALU INSDEP L controls the two 745158
multipiexers that select the source of these ALU
control signals. GRAA ALU INSDEP L is low
when the UALU bits equal 7 (A inputs), and high
when the UALU bits equal 0 - 6 (B inputs).

Non-Instruction Dependent Control
The ALU control field in the main microprogram

DAPJ ALU SIGN H is the sign of the
ALU output; it is taken from ALUIS
for word data or from ALUO7 for byte

ROM is a 3-bit field that controls the values of six
a one-to-one relationcontrol signals. There is not
the control signals,
and
bits
ROM
ship between the
and not all possible combinations of control signals
can be generated. Each control signal is the result

data.

of decoding the ROM bits.

I1-2-4

RACC UALUO and UALU?2 are inverted by the
multiplexer and generate GRAA ALUS3 and
ALUS2, respectively. If UALU = 1 or 6, the output of the 74564 at the lower-left of GRAA goes
high and GRAA ALUSI goes low; for other values
of UALU, ALUSI is high. If UALU = 3, the B0
input to the multiplexer is high and ALUSO is low.

GRAA ALUS2 and ALUS3, are forced high when
the SWAB instruction is being executed. The
SWAB instruction does not have a unique ROM

The M bit is asserted when UALU = 0 or I;
GRAA MODE H goes high and ALUM L goes
low. The carry bit is generated when UALU = 6
by GRAA CIN L, which goes low and causes

The ALUM (mode control) signal is taken directly
from the ROM, except when the SXT instruction is
executed with a negative operand [IRCH N(1) H is
high] or when both GRAA ROMM and ROMC

GRAA ALUC H to go high.

are high (GRAA CDEP L).

These control signals are all inverted on DAPF and
DAPH and input to the ALU. Table 2-1 shows the
operation performed by the ALU for each value of
the UALU field, and the state of the control signals

In the case of SXT and a positive operand [IRCH
N(1) H low], GRAA ROMM is high, ROMC is
low; this forces GRAA ALUM low, DAPF LM
and DAPH HM high, which puts the ALU in the
logic mode. DAPF LSO - LS3 (and DAPH HSO HS3) are respectively L, L, H, H and the ALU output is O (refer to the ALU table on DAPF). In the
case of a negative operand [IRCH N(1) H high},
GRAA ALUM is high, which puts the ALU in the
arithmetic mode. All other control signals being unchanged, the ALU output is a 2’s complement

at the 74S181.

Instruction-Dependent Control

When the ALU control signals are instruction-dependent, each of the six signals is controlled by a
separate output signal from the subsidiary ALU
control ROM, shown on drawing GRAA. The
ROM inputs [IRCH SUBROMA(4:0) H] are described in Chapter |, Paragraph 1.5.

When UALU = 7, the multiplexer SO inputs are
low and the A inputs are selected. Two of the ALU
select signals, GRAA ALUSO and ALUSI, take on
the value of the ROM outputs. The other two,

word, and uses the same word as the ASL instruc-

tion with some of the control signals modified in
this manner. Refer to the ALU Control ROM
Map, shown on drawing GRAK.

minus 1 (all 1s).

GRAA ROMM and ROMC are both high for the
ROL, ROLB, ADC, ADCB, SBC and SBCB instructions. In this case, GRAA CDEP L is low and
the ALU is put in the arithmetic mode instead of in
the logic mode.

Table 2-1

Non-Instruction-Dependent ALU Control Signals

UALU

Operation

Control Signals

DAPF or DAPH
LS3H { LS2H | LS1H | LSOH | LMH

Negation of
GRAA ALUCH

HS3H | HS2H | HS1H | HSOH | HMH

0
1
2

not A
B
A (plus carry)

not used

instruction-dependent

5
6

A plus B (plus carry)
A plus A (plus carry)
A-B

L
H
L

L
L
L

L
H
L

L
L
L

H
H
L

H
L

H
H

L
H

L
L

L
H

Instruction Dependent

I1-2-5

The ALU C (Carry-in) signal is modified for two

2.1.2.1

classes of instructions. The DIV and ASHC instruc-

four-input

Description of SHFR - The SHFR
multiplexer

provides

right-shifted

tion-dependent

ALU inputs. It accepts PCB as the fourth input.

one

that

shifts

the

two

byte-swapped

is a

unshifted,

tions operate on 2-word operands, and the instrucstate

and

that

outputs

from

the

words left. The carry-in must take on the state of

Left-shift operations are performed in the ALU by

the most-significant bit of the less-significant word.

using the A plus A mode. The sum of A added to

For the ADC on ROL instructions, a carry insert

A is equivalent to the product 2A, which in turn is

signal is generated if the C bit is set; for the SBC in-

equivalent to shifting A (as a binary number) one

struction,

bit to the left.

cleared.

the signal

This

is generated

data-dependent

if the C

carry

bit is

generation

controlled by the assertion of both

ROMM and
Bits (00:06) and (08:14) of the SHFR are similar,

ROMC.

and are shown on drawing DAPF and DAPH.
GRAA

SGNEX

MOVB

generated

when

MOYVB instruction is being executed. This instruction is used to extend the sign of the byte into the

high

byte

when

the

destination

General

operations are required in the SHFR for

the most-significant bit of each byte. The SHFR
logic for data bits 7 and 15 are shown separately on

drawing DAPJ.
WORD

OB SWAP

L and H

indicate

that the significant SHFR outputs include the high
byte, and the sign of the output is bit

15 (rather

than bit 7).
2.1.2

Special

BITS 00:06 AND 08:14

Refer to Figure 2-2, which shows a typical SHFR
bit 00:06 or 08:14.

Shifter (SHFR)

The output of the ALU

is input to the program

counter (PCA) and to the SHFR. The inputs to the

SHFR include, in addition to the ALU, the output

of PCB.

ALU(n+1)

ALUp

172
745153

The SHFR can perform right-shift or byte-swap opcrations on the data, or substitute the contents of

ALU(n+8)

an instruction is performed for an odd-byte destina-

operand,

the instruction

the data

manipulation

required by

ts completed in the ALU and the

SHFRS1 H-

NOTE:

n=00:06
08:14

SHFRSO H
1-3107

transfer of the result to the odd-byte data lines is
performed

SHFRn H

the PC for the ALU outputs. In many cases, where
tion

——

PCBn

the SHFR, all during one machine

Figure 2-2

cycle.

Typical SHFR Bit

In addition to its data manipulation (shifting and
byte swapping) activity, the SHFR is used as a rout-

ing clement. When General Register 7 (the PC) is

When a byte swap is required, the A inputs are se-

transferred to the SR or to the DR, PCB is routed

lected, and ALU(08:14) are switched to the outputs

through the SHFR, to the SRMX or DRMX, then

of SHFR(00:06), and ALU(00:06) to the outputs of

to the SR or DR,

SHER(08:14). Inputs B switch the PCB to the multiplexer outputs. Inputs C transfer ALU(00:06) and

The output of the SHFR goes to the General Regis-

(08:14) to SHFR(00:06) and (08:14) (no shift).

ters, GS and GD, to the SRMX and DRMX, to

right shift is executed by using input D, which trans-

the BRMX and to the display multiplexer - where

fers ALU (n+1) to SHFR n (for example, ALUOS

it provides the Data Paths display data.

to SHFRO04).

[1-2-6

BITS 07 and 15

Refer to drawing DAPJ. The most significant bit of
the shifter is SHFR 15. The shifter inputs are similar to the inputs for other shifter bits when the
byte-swap (A) or unshifted ALU inputs (C) are selected. However, the input used for the right-shift
mode is dependent on the instruction being
executed.

For some shift operations, such as ASR and
ASRB, the sign of the data word is replicated. This
is done by routing ALUI1S5 (the most-significant, or
sign, bit) to the right-shift inputs of both DAPJ

SHFR 15 and DAPH SHFR 14. For right rotate

(ROR and RORB) instructions and multiply instructions, this procedure is modified by forcing a
second level 2-input 74S157 multiplexer to select
GRAJ SHFR DATA H instead of DAPH PCB 15
H. The signal GRAJ SHFR DATA consists in this
case of the carry (C) bit and the P/class instruction

decode for the rotate instruction. For the multiply
instruction, the input is used to extend the sign of
the result during the calculation and to correct the
sign on the cycle, if necessary. In this last case, it is
high if the instruction is an I/class, and either the
SR is greater than 0 during an instruction-dependent cycle, or the contents of the SR are negative
(SR 15 1) during a non-instruction dependent cycle.
The shifter logic for data bit 7 must operate the
same as the normal bits for word data, and as the
most-significant bit for byte data. The right-shift input must be able to receive one of three values;
ALUO8 for word data; ALUO7 for byte shifts (if
not a rotate instruction); or the Carry (C) bit for an
RORB instruction. This is accomplished by multiplexing the C bit with the PCB input and forcing
the SHFR to accept input B for an RORB instruction; for any other byte shift, the SHFR is forced
to accept input C, the no shift input, so that
SHFR0O7 and SHFRO7 both receive ALUO7.
SHFRA15 and SHFR15 signals and SHFRAO7 and
SHFRO7 signals are logically identical and appear
only for additional loading capacity.

bytes, or during a SWAB instruction, only the high
byte is tested. A fourth input, enabled by IRCF
CHECKZ H, is used when the final result is two
words, to clear the 0 (Z) bit if the second word
does not contains all Os. If the second word is all
Os, the Z bit retains the previous value. Thus, only
if both words are all Os will the Z bit be set.
2.1.2.2 Shifter Control - The SHFR is controlled
by DAPF SHFRSO and SHFRSI1 H, which are inverted from GRAA SHFRSO and SHFRSI1 L.
These signals, in turn, are generated by the same
subrom that controls the ALU, and they are instruction-dependent when the ALU control signals are.
Refer to Paragraph 2.1.1.2.

GRAA SHFRSO and SHFRSI, when instructiondependent, take on the value of the subrom output,
except in the case of the ASRB, ROROB, NEG
and NEGB instructions if the destination mode is
not 0, and in the case of the SWARB instruction. In
both of these cases, DAPF SHFRS0O and SHFRSI
are forced low by GRAA SWAP L.

2.1.3 Program Counter (PCA and PCB)
The Program Counter (PC) provides the address of
the next instruction to be fetched. The PC is implemented as two 16-bit registers, PCA and PCB.

PCA accepts data only from the ALU; this data is
clocked in at T5 by DAPJ CLKPCA H when the
PCA ROM bit =1. The output of PCA goes only
to PCB, and is the only input to PCB.

PCA is clocked into PCB at Tl by DAPJ CLKPCB
H when the PCB ROM bits =1, 2 or 3: 1 is an unconditional load; 2 loads if the source field =7; 3

loads if the destination field =7, unless the instruc-

tion is I/class and the UPWEOO ROM bit is high.

(I/class instructions are those that cause a high output of the ITCH R (I CLASS) output of the instruction decode subrom. They are listed in the R
(1/CLASS) column of the table on IRCJ).
2.1.4

GRAB Z DATA2 L detects all Os at the SHFR output. Depending on the operation being performed,
cither the entire word of data or only one byte of
data may be significant. For word data, both
wired-AND circuits must detect all Os. For normal
byte operations, only the low byte (SHFRO7 SHFRO00) must be all 0s. During operations on odd

General Registers

In all instructions that transfer data, each address
reference specifies one of eight General Registers.
The specific register (of the 16 in the KB11-C. Processor) used for each reference depends both on the
value of the 3-bit register specification and on the
processor state, as represented by the contents of
the Processor Status (PS) word.

I1-2-7

Two of the eight General Registers that can be spec-

ified in the instruction code are also used by the

W13

CURRENT MODE *———

specification has a value of 7, it specifies the Pro-

SET (0,1}

ware

the

specification

Paragraph 2.1.3.

has the value 6,

case, depending on the processor mode: register 6 if
the processor is in Kernel mode, 16 if it is in Super
mode, or 17 if in User mode. If the register specification has the value 0 - 5, one of two registers is selected. depending on the register set selection

bit

(bit 11 in the PS word).

PRIORITY

|7lN\z|vlc]
11-3098

* MODE: 00 =KERNEL

01=SUPERVISOR

11=USER

it specifies the

is selected in this

|Norusso

GEMERAL REGISTER

Figure 2-4

hardware Stack Pointer (SP) register.

1n__10

PREVIOUS
QUS MODE*

One of three hardware registers, within the General

— ,—/%‘,——-/

KB11-C as special-purpose registers. If the register
gram Counter (PC). This always refers to the hard-

Processor Status Word

Each of the 16 General Registers is duplicated. The
duplication

allows

the

processor

access

than one register at a time. Each General Register,
with the exception of register 7, is implemented by

two

copies

the

two General

clements.

The General Source (GS) registers include 16 regis-

Figure 2-3 illustrates the General Register selection
in the KB11-C Processor. Figure 2-4 shows the format of the Processor Status word (PS).

ters allocated as shown in Figure 2-3. The General
Destination (GD) registers contain 16 registers used
in an identical manner. When data must be written

into a General Register, it is written into both cop
ies to ensure that all attempts to read the data will

read the same value. However, by specifying differ-

ent register addresses to the GS and GD storage ele-

ments,

possible

read

the contents

of a

different register from each. This feature is used pri-

marily in reading the contents of the two registers

specified by double-operand instructions.

GENERAL REGISTER

> SET O
3

PS<i1>:=0

Whenever the General Registers, as a group, serve

as a data source, the PC (register 7) can be selected
as
6

KERNEL

7
10

SP (R6)

}PS<15:‘|4> =00

This is accom-

to sclect the SHFR input, if register 7 is selected,

/////////4/

SEE

Registers.

and allowing the source or destination multiplexer

/A///////////A ?/

one of the General

plished by selecting the PCB input to the SHFR,

NOTE

and the GS or GD input if any other register is
selected.

Refer to schematics GRAD-GRAH. The General

Registers

GENERAL REGISTER
> SET |

PS<{1> =1

implemented

two

sets

four

ranged in sixteen 4-bit words. Each General Register

are

3101A 64-bit random-access memories that are ar1s

made

of one word

from

each

of four

memories, and the same word selection signals are

sent to all four memories for one copy of the regis-

SUPER SP (R6)

}PS<15:14>=01

ters. A different set of selection signals can be sent

USER SP (R6)

}PS<15:14>=11

but not when data is being written.

to the second copy of the registers while reading,

NOTE:

Data is written when the W input is low. The write

enable signals are GRAC GRWE LOB L for the
11-0963

Figure 2-3

low order byte, and GRAC GRWE HIB L for the
high-order byte.

General Register Storage in

The conditions for these signals

arc explained in a table on GRAC.

GS and GD Storage Elements

I1-2-8

Individual

registers are selected

for reading and

writing by GRAC GDA (0:2) H and by GRAC

The multiplexers are disabled when PAD =6; GSA
(0:2) and GDA (0:2) are low in this case.

GSA (0:2) H, all four of which go to the A0 - A2
inputs to the 3101As. The register sets are selected
by GRAC GDREG SETI1 H and GSREG SET! H,
,
:

Table 2-2

which go to the A3 inputs to the 3101As.

General Register Selection
Source

and

Destination

Address

Multiplexer

Multiplexer Input Selection

GSAM and GDAM

[GRAC GSA(0:2), GDA(0:2)] - The microprogram

PAD

GSAM

lects one of seven sets of sources; the value of 3 in

the PAD field is not used. Some of the sources are

selects the sources of the scratch pad addresses. The
microprogram includes a 3-bit PAD field that se-

0
1

constants, and are generated by +3 V and OV in-

GDAM

A
A

A
B

C
T

used

not use

ers are taken from the IR source and destination

?}S

1GD MX & b]13d

shows the multiplexer inputs used for each PAD

puts to the GDAM and GSAM multiplexers; oth-

value. Table 2-3 shows the values of these inputs.

D an

Y
4 I§

Table 2-3
Multiplexer Input Values

Input

Value
Bits 1 and 2

Source Field [IR(07:08)]

Bit 0

If IR06=1, high. If IR06=0, low, unless current mode is User
and the source field =6 or 7.
If PAD=4, same as above, but GRAC PLUS 1 is ORed with
IR06 to force an odd register address. Used only during MUL,
DIV and ASHC.

Destination Field [IR(01:02)]

IF IR00=1, high. If IR00=0, low if the console is not active; or
if the destination field is not =6; or if PS15=0 (Kernel or Super
current mode) and the instruction is other than MFP or MTP
with destination mode 0; or if PS13=0 (Kernel or Super previous
mode) and the instruction is MFP or MTP with destination

mode 0.

GSA(2:0) and GDA(2:0)=5

If PS15=0, GSA(2:0) and
GDA(2:0)=6 (Register 6, Kernel
or Super)
If PS15=1, GSA(2:0) and

GDA(2:0)=7 (Register 6, User)

I1-2-9

General

Selection

(GRAC GDREG

The C

SET 1 and GSREG SET 1) - The most-significant

input to

the Set

multiplexers is PSI11,

which defines the register set.

bit of the scratch pad address selects which General
Register set is used. This selection is, in general,

The

done by the multiplexer; in several cases, the pro-

which, when asserted (low), specifies User or Super

cessor forces the selection of General Register Set

modes.

input

these

multiplexers

PS14(1)L

I. Note that these multiplexers are always enabled.
The output of these multiplexers, when low, causes
Table 2-4 shows the multiplexer inputs selected for

the selection of General Register Set 1 through the

each PAD value.

GRAC GDREG

SETI

H and GSREG SET1

OR gates.

Table 2-4

The two other inputs to the OR gates cause the se-

Multiplexer Input Selection

lection of SET1:

GSREG and GDREG SET 1
GSREG SET 1

GDREG SET 1

OR gates to select the proper set.

not used

clocked into IRO03; it is then input to the

During a Console operation, bit 3 of the
address selects the

In the case of an MFP or MTP instruc-

|85

PAD

tion with destination mode 0 and destinafield

=6,

(conditional)

tion

and

PSI12=1

UPWEQO=1
(previous

User or Super modes), set 1 is also se-

lected.

MFP

instruction,

the

source is always specified in the field norGRAB SRC SET |

L and DST SET 1

mally designated as destination. The des-

L are, re-

tination is the current mode stack.

spectively, the A and B inputs to both source and

destination multiplexers.

2.1.5

Source and Destination Multiplexers (SRMX

Both gates are asserted (low) when the Console is

and DRMX)

not active, PS11 is asserted, and registers O - S are

The SRMX

specified by the source [IR(06:08)] or destination

Source and Destination Registers (SR and DR). Re-

[IR(00:02)] fields of the current instruction; regis-

fer to drawing GRAD.

and

DRMX

select the input to the

ters 0 — 5 are selected if not both IR08 and 07 (for

the source field) or IR02 and 01 (for the destination

The select inputs to these multiplexers are GRAC

field) are asserted.

SRMX SEL L and DRMX SEL L, which are controlled by the SRX and DRX ROM bits and by

Set

is also selected when the Console is not ac-

IRCB SRCF 7 L.

tive, PS14 is asserted (Super or User modes), and
register 6 is specified by the instruction source or

When the SRX and DRX bits =0, the SHFR is se-

destination

conjunction with the

lected as the input to the SR and DR. When SRX

forms address

16. If

and DRX =1, the General Source and Destination

PS15 is asserted, the A input to GRAC GDAO and

registers (GS and GD) are the SR and DR inputs.

fields. This, in

GRAC multiplexer outputs,

GSAO is forced high, thus generating address 17

If SRX

and

DRX

=2,

the inputs are either the

(GRAC PLUS 1). If the instruction is an MFP or

SHFR, if the Source or Destination fields =7, or

an MTP, and UPEWO00 =1 (conditional), and the

the GS and GD if this is not the case. SRX =3 is

destination field =6 or 7, and the mode is User or

not

Super, and the Console is not active, GRAB DST

TP(3:5), which is a flip-flop set by T3 and reset by

SETI L is also asserted.

TS.

11-2-10

used;

DRX

clears

the

GRAJ

2.1.6

2.1.7

Source Register (SR)

data-fetch operations.

All output from the GS registers must be transferred through the SR. When the PC is selected as
1 source register, the data from the PCB is routed
lhrough the SHFR and the SRMX to the SR.
From the SR, data can be routed anywhere in the
processor through the ALU inputs, or the contents

of the SR can be used as an address for external

data transfers through the BAMX. The SR is also
used as a temporary storage register during transfers of data within the processor; e.g., when the old
PC and PS are being stacked during an interrupt or
trap service sequence, the SR

Destination Register (DR)

In addition to performing two functions similar to
the major functions of the SR, the Destination Register (DR) also operates as a data manipulation element; specifically, the DR is used as a left or right
shift register during register and operand instructions such as ASH, ASHC, MUL, and DIV,

The Source Register (SR) performs two major functions. It is the output buffer for the General Registers when addressed as the SR in an instruction,
and it provides temporary storage during the source

holds the vector

address.

The SR is used as a data storage element for intermediate results during instruction execution. The
register and operand group instructions, such as
multiply, divide, and the arithmetic shifts, use the
SR to hold both operands and results.

All output from the GD registers (and from the
PC, when it is selected as a destination register)
must be through the DR. Data from the DR can
be routed anywhere in the processor through the
ALU, or used as an address in external data transfers through the BAMX. To transfer the contents
of either the SR or the DR to an external data storage location, the data must first be transferred from
the SR or DR through the ALU to the BR, and
then from the BR to the Cache, the Unibus, or the
Internal Data Bus.

The DR is used as a control register and to accumulate the less-significant part of the result during reg-

ister and operand instructions such as multiply,
divide, or the arithmetic shifts. The DR is also the
source for data to be loaded into the Shift Counter

(SC) register.

The outputs of the SRMX are connected directly to
the inputs of the SR and are clocked by T1 if enabled by the microprogram bit RACA USRK H.
The outputs of the SR are routed to the ALU input
multiplexers and to the bus address multiplexer. Bit
0 of the SR is also sent to the IRC module for use
in one of the microprogram address generation circuits, the C Fork, for odd-byte source branches.

Refer to GRAD through GRAH. The DR can be
loaded with a left shift of one bit, a right shift of
one bit, or no shift. The shift inputs are used when
the processor must operate on two words of data at
the same time (for example, during a multiply or divide instruction) and the operation includes shifting. The type of loading is determined by RACA
UDRK(00:01), as shown on GRAD. During a right

The output of the SR is checked for two conditions: SR € 0 and SR = +1, by GRAE SR LEQ
ZERO H and SR EQ ONE L. The two flip-flops
are clocked by the same signal that clocks the SR.

During a left shift, DAPJ LEFT DATA is loaded
into GRAD DRO00; DAPJ LEFT DATA is high
when both DAPJ COUTI5 H (the ALU carry out)
and the instruction is I/class. This input is used during the DIV instruction. When no shift is required,

They are both set if GS(01:15) = 0.

shift, DAPF ALUOO is loaded into GRAH DRI5.

DRMX(00:15) are loaded into DR(00:15).

The DR is cleared when the DRMX control bits

GRAE SR LEQ ZERO H is asserted if both flipflops are set and GRAD SR00 H is low (SR=0) or
if GRAH SR15 L is asserted (SR is negative).

GRAE SR EQ ONE L is asserted if both flip-flops
are set and GRAD SRO00 H is asserted (SR=+1).

UDRX(00:01)=3.

At T1, when UDRK(00:01)=3 (load DR),
DRMXO00 is clocked into the GRAB OBD (Odd-

Byte Destination) flip-flop. When set, this flip-flop
indicates that the destination field contains an odd

byte address.

I1-2-11

2.1.8

Shift Counter (SC)

The Shift Counter [GRAJ SC(00:05)] is used to
count the repetitive cycles of data manipulation in
the multiply (MUL), divide (DIV),. arithmetic shift
(ASH), and arithmetic shift combined (ASHC) instructions. The SC can be loaded either with the six
less-significant bits of the DR (for ASH or ASHC
instructions) or with a constant, 17(8), (for MUL
or DIV instructions). The SC is controlled by the
RACC USHC(00:01) ROM bits. The outputs of the
SC are used in the Branch Conditions logic on

SCP5

I—_——

scg3

sCg2

RACK.

The SC consists of two 74191 counters and associated logic. They are loaded with the value present
at the D inputs when the LOAD input is low. The
74191 counts on the positive transition of the clock
signal, if the ENABLE input is low. The counter
counts down if the DN input is high, and counts
up if DN is low. The MAX/MIN output goes high
when the outputs are all high (=1111), and the
count direction is up (DN=Ilow), or when the outputs are all low (=0000) and the count direction is

MIN/ MAX

l__]—L

R/CLK

U_LJ_

down (DN=high). The R/CLK (ripple clock) output goes low when MAX/MIN is high and CLK is
low. The R/CLK from the low order SC clocks the

SC=p L

COUNT DOWN

| CouNT

I
11-3108

high order SC. If RACC USHC(01:00)=0, the SC
is inoperative.

Figure 2-5

SC Loaded With 00101

If USHC=1, the ENB input is low and one clock
pulse is generated at GRAJ TP(3:5) H.

If USHC=2, the complement of DR(05:00) is
loaded with the sign extended to the two unused
high order bits of the SC.

If USHC=3, the eight bits of the counter are
loaded with Is. This is used to count to 16(10)
(=17%) during MUL and DIV. In this case, only the
four low order bits [SC(03:00)] are counted.

Refer to Figure 2-5. When 17; is loaded, SCOSL is
low, and the counter is made to count up, since
SCOSL is input to both DN inputs. At the first
clock pulse, SC(00:03) goes to all Os (1111+0001).
Neither MIN/MAX nor R/CLK are generated at
this time, and SC(04:05) stay high. Each clock pulse
increments the contents of SC(00:03) by 1. When
their value equals 1111, MIN/MAX goes high, and
since SC(04:05) are still high, GRAJ SC=0 L is asserted. This occurs on the sixteenth clock pulse.

Refer to Figure 2-6. When an ASH or ASHC specifies a right shift, bits (0:5) of the instruction word
contain a negative value. This causes a positive
value to be loaded into the SC (SC05=0), and the
counter will count down (GRAJ SC05 L = DN are
high). Assume that a 6-bit shift is desired: -6 in
2's complement, or 11010, is entered into bits (5:0)
of the instruction word and then loaded into the
DR. The I's complement of this value, or 00101, is
the number loaded into SC(05:00). Since the DN input is high, successive clock pulses cause the
counter to count down to 00000. At this time,
MIN/MAX goes high, but since SCO05 is low,
GRAJ SCO L is not asserted. At the next clock
pulse, the sixth, R/CLK is asserted. Since the
counter is still counting down, all five SC bits
change from 00000 to 11111. GRAJ SCO5 L and
the DN input both go low, which defines count up.
MIN/MAX stays high, SC04 and SCOS are high,
causing GRAJ SCO L to be asserted, thus ending
the count.

I1-2-12

2.1.9

ALU Inputs

The A multiplexer (AMX) is the “A” input to the

ALU. It can select one of four signals:

DR, SR,

PCB, or the Bus Register (BR).
The B multiplexer (BMX) is the “B” input to the
ALU. It can select the SR, the BR or one of two

constant multiplexers, KOMX or K1MX.

General

information

these inputs

is listed in

Table 2-5.

R/CLK

L
)

2.1.9.1

(DAPB AMX00 H - DAPD AMXI15 H) is con-

SCP5 H

A Multiplexer (AMX) - The A multiplexer

trolled by RACC UAMX(01:00) and selects one of

) =

four registers for input to the A operand of the

$CP4 H

ALU. The values of RACC and the registers se-

MIN/ MAX

)

lected are listed in the table on drawing DAPB.

2.1.9.2

B Multiplexer (BMX) - The B multiplexer

(DAPB BMX00 - DAPD BMX15 H) selects the B

1-3109
)

Figure 2-6

input to the ALU.

It is controlled by RACC

UBMX(01:00) H. Table 2-6 shows the outputs of

SC Loaded With 17,

the BMX for the several values of UBMX.

Table 2-5
ALU Input Multiplexers

Multiplexer

Output To

AMX

A input of ALU

BMX

KOMX

KIMX

B input of ALU

BMX

Input From

Type of Input

source register

variable operand

destination register

variable operand

bus register

variable operand

program counter

variable operand

source register

variable operand

bus register

variable operand

KOMX

constants

K1MX

constants and sign-extended operands

fixed constant

source constant

generated constant

destination constant

generated constant

trap vector

generated constant

start vector

fixed constant

BR (SOB & MARK)

shifted and sign-extended operand

BR (branch)

shifted and sign-extended operand

I1-2-13

When

Table 2-6

BMX

RACC UBMX(01:00) H

00
00

KOMXO00

01 | KIMXO01

conditions for these functions are shown on draw-

UKMX =2, a constant of 1 is generated if

IRCC SRCCON-1 H is asserted. A constant of 2 is
generated if IRCC SRCCON-1 H is asserted. The

BMX Output Selection

ing IRCC and are mutually exclusive. They normally indicate an auto-increment or auto-decrement

SROO | BROO

addressing mode for the source register.

When UKMX=3, constants of I, 2, 4, or 10 may

be generated by IRCD DSTCON-1 (or 2, 4, or 10)

H. Increments of4 or 10 are only used for FPI1 in-

structions. The conditions for these functions are

shown on drawing IRCD.

K1MX07

*08

KOEX

K1EX*UKMXO00

DAPD KOEX H is described in Paragraph 2.1.9.2,

*09

KOEX

KI1EX

B Multiplexer (Sign Extension).

*10

KOEX

K1EX

*11

KOEX

K1EX*UKMXO00

2.1.9.4

Constant

stant

Multiplexer

(KIMX) -

Con-

[DAPE KI1MX(07:01) H and

*12

KOEX

KI1EX

*13

KOEX

K1EX

K1EX H] generates vector addresses and program

*14

KOEX

K1EX

counter offsets. The KIMX is controlled by RACC

*15

KOEX

K1EX

UKMX(01:00) H.

SR15 | BR15

Table 2-7 shows the output of the BMX for the sev-

*Note: If GRAA SGNEX MOVB L is asserted, KOEX H

cral values of UKMX when the KIMX is selected

becomes the output of BMX(15:08) H.

(UBMX =1).

When

UKMX =0, DAPE SV(07:02) H are selected.

This is the start vector, which
is selected in ROM
Sign Extension - When RACC UALUQR2:0) H = 7

state 100 (PUP.00 on Flows 12) during the power

(ALU instruction dependent), and the instruction is

up sequence. The address may be selected either in

MOVB (IRCB MOVB H is high), GRAA SGNEX

the range of 000 000 to 000 174(8), or in that of

MOVB L is low. This forces the two signals that

173 200 to 173 374(8), depending on the jumper for

control BMX(15:08) high (DAPD BMXSI!1 HIB L

SVO7. This is due to the logic for DAPE BMXO08

and BMX SO HIB L), thus putting DAPD KOEX

and

H on the high order byte BMX output line. KOEX

extends the sign to all high order bits except bits 08

Il combined with the KIMX circuitry, which

takes on the value of BRO7 when the BR is selected

and 11.

(UBMX =3), or that of SRO7 when the SR is seThe trap vector (TV) is used to select a new PC

lected (UBMX =2).

and PS following a trap operation. The trap vectors
Multiplexer 0 (KOMX) - Con-

for a variety of internal conditions are defined by

stant Multiplexer 0 [DAPD KOMX(03:00)] supplies
values required for incrementation of ALU oper-

the logic in the lower-left corner of the drawing.

2.1.9.3

ands.

Constant

The

KOMX

controlled

RACC

UKMX(01:00) H.

The chart on DAPE defines the specific vector for

cach condition. If none of these conditions is prescnt, but the processor is doing a trap operation,
the trap vector is set to 4. This occurs for non-ex-

When

UKMX=0,

When

UKMX =1, a constant of 2 is generated, ex-

cept

the

case

a constant of
where

FRMJ

is generated.

ADDR

INC

istent

memory

references,

memory

parity

errors,

odd address errors, fatal stack violation errors, and
cxecuting the Halt instruction in User or Supervisor

(request by the FPII for an address increment) is

modes

not

EMT and TRAP instructions are one-half their as-

(Floating Point Condition) is asserted when the Bus

signed values. This is because they are executed by

asserted

and TMCE

is asserted.

operation.

The

KIMX

constants

for

Condition bits (BSC)=4, signifying that the pro-

the same machine states (Flows 12) that cause the

cessor

vector for reserved instructions to be left shifted (so

FPII.

is executing

memory

operation

for the

that vector 4 forms vector 10).
I1-2-14

Table 2-7
BMX Output From KIMX

Bit

BMX RACC

K1MXO01

RACC UKMX(01:00) H

UBMX=1

11
0

SV02

TVOl

BROO

1 02

} 01

04
05
06
07

04
05
06
K1MX07

04
05
06
SV07

09
10

K1EX
K1EX

SV07
SV07

0
0

BRO7
BRO7

11
12
13
14

K1EX*UKMX00
K1EX
K1EX
K1EX

0
SV07
SV07

0
0
0
0

BRO7
BRO7
BRO7
BRO7

K1EX

SV07

BRO7

K1EX*UKMX00

TVO04
TV05%07
TVO06
TV05*07

SV07

03
1 04
BROS

BRO6
BRO7

The third input to KIMX, BR(07:00)H, is used for
the offset in SUBTRACT | AND BRANCH

2.2

(SOB), and MARK instructions. This offset is always.in full words and is always a positive quantity

Bus Register Multiplexer (BRMX) from the Cache

that is subtracted from the PC in the ALU. Be-

ory

cause all PDP-11 Systems use byte addresses, the
offset, as it appears in the instruction, must be mul-

Point Processor and the Unibus. The Unibus input
is buffered by PDRJ D(15:00) H, the Bus Buffer

tiplied by 2 to generate the proper value to be sub-

tracted from the PC. This is done by shifting the 6bit offset 1 bit to the left. For example, BROO is the
input to the multiplexer for bit 01. The BR is used

The

BRMX

from

the

because it contains the same value as the Instruc-

from the SHFR to the ALU is through the BRMX

tion Register (IR) at the time of the PC modifica-

and the BR.

tion,

and

INPUTS TO PROCESSOR DATA PATHS

The Processor Data Paths receive data through the
Memory, the Console (Switch Register), the MemManagement registers,

the optional

Floating

also has an input for internal data

SHFR.

The

most generally

used

path

is directly-accessible to the data path
The BRMX is the input to the two Bus Registers

logic.

(BR and BRA) and to the two Instruction Registers

The fourth input to K1MX is used for the offset in
successful branch instructions. The branch offset

(IR and AFIR).

can be either positive or negative; the value taken

from the instruction is first multiplied by 2 (shifted

2.2.1

left) and then sign-extended, and the resulting 16-

All data input to the processor is routed through

Bus Register Multiplexer (BRMX)

.bit number is added to the PC. The branch offset

PDRA BRMX(15:00) H; in addition to the external

can have values from +127,, to =128, words; BR
(07:00) provide the offset and the left shift provides

data from the Unibus, the BRMX also accepts in-

word (rather than byte) addresses.

Internal Data Bus.

puts from the Cache Memory, the SHFR, and the

I1-2-15

The four inputs to the BRMX are:

PDRJ D(15:00) H (Bus Buffer Regis-

ter clocked each T3 from the Unibus
lines);

The Internal Data Bus is selected if TMCF SEL
INT L is low. One of three conditions may cause
this: an internal register is being addressed, or the
IBSO0 ROM bit is asserted (read Switch Register or
read PS), or the BCT(02:00) ROM bits = 1 (read
Floating Point data).

PDRA INT D(15:00) H (Internal Data

Bus)

DTML CDM(15:00) H (Cache Memory

data)

DAPF-DAPJ

SHFR(15:00)

(Shifter

The Unibus is selected when UBRX, TMCF SEL
MEM L, and TMCF SEL INT L are all high.
The BRMX is the input to both Bus Registers (BR
and BRA) and to both Instruction Registers (IR
and AFIR).

output).

Internal Data Bus (INTD)

2.2.2

Refer to Figure 2-7. These signals are selected by
PDRA BRMX S(1:0) H. The SHFR is selected
when RACA UBRX H is low, making S| and SO

The Internal Data Bus [PDRA INT D(15:00) H] is
a wired-OR bus that transmits the following data
to the BRMX:

both high.

The other three inputs can only be selected when
UBRX is high.

The Cache is selected when TMCF SEL MEM L is
low; the address is a Cache address, an interrupt
pause is not in progress, and the Internal Data Bus

Switch Register (from Console)

Memory Management Registers (MMR3
to MMRO and APR, which is a multiplexer that can select either a PAR or a
PDR)

is not selected.

System ID and System Size Registers

|S@ | BRMX OUT
| L | uniBus

|H|

INTD

|L |

CACHE

[ H

SHFR

PDRA
BRMX

SHFR

CACHE——C

TMCF SEL
INT L

SCCD INT REG (1) L

INT D—1B
UNIBUS —1A

BCT20@ HI

BCTOI L—]

BCcTO2 L—

TMCF FP

READ L

PDRA BRMX S@ H
RACA UBRX H

PDRA BRMX St H

SAPN NOT CACHE ADR H—<{>

TMCF SEL MEM L
BSDO@ H

L—TMCE INTR PAUSE L

BSD@I L

Figure 2-7

BRMX Selection, Simplified Schematic

I1-2-16

1-3110

Processor

Error

(TMCD

When IBS=1, 2 or 3, the Memory Management in-

TRAPS TO 4)

puts are also disabled.

IBS=1

selects the Switch

Processor Status Word (PS)

Floating Point Processor Data

When IBS=0 and BCT is not equal to 1, the Mem[FXPD

ory Management inputs are enabled. The selection

DOMX(15:00)].

of the register that is to be put on the INT D bus is
made by register address decoding in Memory Man-

Figure 2-8 is a block diagram of the Internal Data

agement.

Bus. The data put on the bus is a function of the

SCCM and SCCN) show the Memory Management

IBS (Internal Bus) and BCT (Bus Control) ROM

inputs to the Internal Bus. These inputs are:

Four schematic drawings (SSRJ, SCCH,

bits. Refer to schematic TMCF. TMCF GET OFF
H

is asserted when the IBS field equals

(Read

MMRO - MMR3

Switches), 2 (Load PS) or 3 (Read PS), or when the

and becomes SSRJ GET OFF L.

is inverted on SSRJ

System Size and ID registers

BCT field equals 1 (Read Floating Point Processor
Data). TMCF GET OFF H

TMCD traps to 4 error register

APR (PAR/PDR multiplexer)

Switch Register

When BCT=1, data from the FPI11 is enabled onto

One of these inputs is put on the Internal Bus if

the bus and all the Memory Management inputs

SSRJ GET OFF L is high, and if the operation is a

are disabled by TMCF GET OFF.

read (SSRJ CI B L not asserted).

MX j—l—v

SWITCH REG

SCCL MMR3—»f
|

1BS=1

READ SW
T

ADDRESS DECODE ——'7}
l_ —

_| SSRJ

SAPM APR —#

RACC IBS I

Il
s oot
<02:00>

I
|

|
l

183

reneno__|

. cm— —
L —-

—w}

L
—_

THAP

|
I

I
1

SCCM
=Ll SGC
SYS ID<00:07>

SYS SIZE LO

SIZE00HI
l SYS SIZESYS<O7-

ADDRESS}_+ SYS [D <15:08>

PS<15:00(1)>H

BUS INT D —I

I PDRD

l —[BS=3
IBS—.'——
DOMX

— — —
I

BUS INT D
03 L
<15:0

TRAPS TO 4

FXPD
0>
lt <15:0

Figure 2-8

ADDRESS DECODE _.I—}

SSRI MMR1

SSRC MMRG

=||

SSRH MMR2

|
I

PDRA

UNIBUS—

Shcne

{15:00> ''

{15:00>

11-34581

Internal Data Bus Block Diagram

I1-2-17

Address decode determines which one of the inputs

2.2.2.4

goes onto the bus.

of the System ID Register [SCCN SYS ID(15:08)
H] and the System Size Register are gated onto the
Internal Bus on SCCN by their respective address

SCCN Multiplexer - The high-order bytes

2.2.2.1 SSRJ Multiplexer - The inputs to the multiplexer on SSRJ are MMRO, MMRI, MMR2 and
the APR multiplexer (PAR or PDR). This multiplexer is enabled when SCCC INT REG B H is asserted and SCCC MMR3 is cleared in addition to

2.2.3

GET OFF and CI.

The Bus register consists of two slightly different

decode signals and by GET OFF and the negation
of ClI.

Bus Registers (BR and BRA)

registers, the BR and the BRA.

Input select signals are SCCC MMR REG (1) H
(MMRO, 1, 2), SSRH VA(02:01)
L (virtual address

The BRMX

bits 02:01) and SCCD APR REG L. VA(02:01) de-

This last register, however, also accepts the parity

is the input to both BR and BRA.

fine which MMR is being addressed.

bits from Cache Memory (DTML HI BYTE PAR

2.2.2.2 SCCH Bus Output - The Switch Register
[SCCJ SWR(15:00) H] is transmitted from the Console to Connector J2 on SCCJ. It is multiplexed

the BRA outputs as PDRB HI PAR H and LO

with MMR3 to make up the second Memory Man-

byte parity information to the Console indicators.

H and LO BYTE PAR H). These bits appear on
PAR H and are used only to generate PDRH IND
HI PAR H and IND LO PAR H, which transmit

agement input to the Internal Data Bus.

The BR outputs are designated DAPA BR(15:00)
Since MMR3 consists of only five bits (00, 01, 02,

H and DAPA BRI14 L. The high outputs are the in-

04 and 05), only these bits need be multiplexed.

puts

the

AMX,

the

BMX

and

the

KIMX.

DAPA BR14 L is an input to RACK BRCAB 05
The MMR3 input is selected when SCCC READ

MMR3 L is asserted.

The BRA outputs are called PDRB BR(15:00) A
The Switch Register is selected by SCCC SW REG

H. They are also inverted as PDRB BR(15:00) B L.

(0) H when the reference is an explicit one and by

They are the inputs to the Control Registers (LR,

TMCF READ SW L if the reference is implicit.

PS, PIRQ, SL, PB), the DMX, the Display Multi-

This last signal is asserted when the ROM IBS field

plexer, Cache Memory, Memory Management and

is equal to 1.

the FPP.

The BR and the BRA are clocked by TIGA CLK

2.2.2.3

SCCM

SCCM Mulitiplexer — The Multiplexer on

BR H and CLK BRA H, during the 15 ns of the

transmits

duration of TIGC TPB L, when RACA UBRK H

the

following

data

BUS

(load BR) is high and TIGA GATE BR (1) L is

INTD(07:00) L:

low. This last flip-flop is set at the rising edge of

TPB L when the output of the OR gate is high.

The System ID Register, bits (07:00),

The CPU Error Register (refer to Chapter 3), which consists of TMCD ILL
HALT H, ODD ADRS H, CACHE

2.2.4

Instruction Registers (IR and AFIR)

When

NXM

data storage location, the data word enters the pro-

This always occurs at T1 (refer to Chapter 4).

UBUS TIMEOUT

YEL

instruction is fetched from an external

TRAP H and SL RED ERR H, and

cessor

The two System Size Register low-order

(BRMX), and is loaded into the BR. To retain the
instruction word for decoding during the execution

through

the

Bus

Multiplexer

bytes.

of the instruction, while releasing the BR for other
data transfers that may be required during the exe-

L. Address decode signals select the output signal

cution of the instruction, the outputs of the BRMX
are simultaneously loaded into the instruction regis-

and, in conjunction with SCCC C1 B L and SSRJ

ter [IRCA IR(15:00)] and into the A Fork Instruc-

GET OFF L, enable the output drivers.

tion Register [RACJ AFIR(15:00)].

The Multiplexer is enabled by SCCD INTD REG

I1-2-18

The IR and AFIR are clocked only during data
transfers that fetch instructions. The BR is clocked

The

inputs

the

DMX

(data

outputs

the

Unibus) are:

during every external data transfer that brings data
into the processor. Both IR and AFIR are clocked
by TIGC T1 or TIB if RACA UIRK H is asserted

The Bus Register (BRA), which is used
as the data output of the processor to

(Load IR).

Unibus devices. BRA is always selected

during a processor DATO.

The IR is used for decoding circuits which operate

the subsidiary ROMs, the program ROM B and C

The

Forks, and a variety of instruction class selectors.

Control

Registers:

(Processor

Status word), SL (Stack Limit), PIR and

The instruction decoding logic is shown on the con-

PIA (Program

Interrupt),

Break).

explicitly

PB (Program

trol section block diagram, Chapter 1. The AFIR is
used only by the program ROM A Fork.

(by
Unibus address), these registers are read

2.3

a processor DATI.

The output of the Data Paths is routed through
one of four logic units:

addressed

by the program from the Unibus during

PROCESSOR DATA PATHS OUTPUTS

When

During any DATI other than those during which the processor reads the Con-

The Bus Address Multiplexer (BAMX)
selects the source of the Unibus address

The

data lines must not be asserted.

Display

Multiplexer

selects

trol Registers, the output of the DMX is
This is because the data is coming
from a Unibus device and the processor

the

source of the console data display
c.

The Data Multiplexer selects the source

The high order byte of the DMX corresponds to
BUS D(15:08) and is enabled by TMCD HI BYTE

of Unibus data
d.

The

the

low

order

byte corresponds

BUS

D(07:00) and is enabled by TMCD LO BYTE EN

Bus Register (BRA) supplies data
directly to the Cache Memory, the Mem-

sponding

ory

(low). In the case of the Control Registers (PS, SL,

Management registers and

the op-

tional Floating Point Processor.
2.3.1

Bus Address Multiplexer (BAMX)
The Bus Address Multiplexer (DAPB BAMX00 H

H. When these signals are not asserted, the correoutputs

DMX

are

not

asserted

PIR and PIA, PB), one or the other, or both, of
these signals are asserted when an internal address
is decoded (SCCE INTERNAL ADRS H) by Memory Management and a Unibus transaction has
been started (UBCA MSYN SET H). Both signals

to DAPD BAMXI15 H) accepts as inputs the DR,
PCB and SR registers, as well as an input, used for

are

maintenance purposes only, from the FPI1

TMCD CI B L).

Float-

of the

asserted

the

case

the

(DATO

ing Point Processor. Its output is the program virtual address, which is the input to Memory
Management, which in turn generates the physical

address for the Cache and the Unibus.

The

BAMX

output is selected by

H and SO H)

arc cnabled by UBCA MSYN SET H and the nega-

RACB

UBAX(01:00), as shown on the table on drawing
DAPB.

2.3.2

The sclect signals (TMCD DMX S1

tion of TMCD CI B L (=DATI). The combination
ol select signals for each register is determined by
register

address

decoding

drawing

SCCE.

none of the Control Registers are selected, both se-

lect signals are low and the BR is selected.

Unibus Data Multiplexer (DM X)

Refer to drawing PDRE. The Processor data output to the Unibus is BUS D(15:00) L, which consists of DEC 8881 bus drivers. The input to these

drivers

are the Data Multiplexer (DMX), and
UBCA CPBSY B H, which gates the DMX outputs

onto the Unibus. CPBSY generates BUS BBSY L
during a Unibus transaction (refer to Chapter 5).

During a DATO, both DMX SI

H and SO H are

low (C1 L is low) and the BR is selected.

Table 2-8 shows the selection of data outputs to the

Unibus.

I1-2-19

2.3.3

2.3.4

Bus Register A (BRA)

Display Multiplexer

The Display Multiplexer [PDRF DISP(15:00) H] seleets the input to the Console data display [KNLA

PDRA BR(15:00) A H transmits data to the Cache
Memory write multiplexer CDPE WRITE
MUX(15:00) H, to which the other input is Unibus
data from the Unibus map [MAPA DATA(15:00)

DISP(15:00) H].

The multiplexer select signals (PDRF DISPSI L
and SO L) are the inversion of PDRH DISP DATA
SELI H and SELO H, which in turn are the encoded outputs of the Console Data Display switch
(KNLD DISP DATA SELI H and SELO H).

H].

The BR is also the input to the Memory Manage-

ment registers, and the data input to the Floating
Point Processor.

Table 2-9 shows the register displayed for each
switch position.

Table 2-8

Data Output to Unibus

Unibus
Output

SCCE
INT

UBCE
MSYN

ADRSH | SETH

TMCD
LO

C1*

PDRE DMX
Byte
DMX | DMX | Input

BYTE | BYTE | S1IH | SOH
ENH | ENH

DATI

HI, LO

DATI

PIR

DATI

HI, LO

DATI

DATO

HI, LO

NONE

DATI

None | None

PIA

*NOTE: TMCD C1 B L low = DATO, high = DATL

Table 2-9

Display Register Selection

Switch Position

KNLD DISP

DATA SEL
OH

BUS REGISTER
DATA PATHS
DISPLAY REGISTER
uADRS FPP/
CPU

L
L
H
H

I1-2-20

L
H
L
H

BR(15:00)
SHFR(15:00)
LR(15:00)
FRMA/B CRAR(7:1)
RACD RAR(7:1)

CHAPTER 3
PROCESSOR CONTROL REGISTERS

The KB11-C Processor contains registers which con-

The

trol processor operations or provide information rel-

LR(15:00)] is write-only. They are both described in

ative to these operations. These registers, which are

Section III of this manual.

SWR

read-only

and

the

[PDRB

listed below, are described in this chapter (in order

of ascending addresses):
Address

3.2

LOWER SIZE REGISTER

This

read-only

bits

13:06 are all

SYS

SIZE(21:14),

1s] specifies the memory size of

17 777 570

Switch and Light Registers

17777 760

Lower Size Register

32 words in memory (the high order byte indicates

17 777 762

Upper Size Register

the

17777 764

System ID Register

minus 1). It i1s used by Memory Management to de-

termine the validity of an address. It is read on the

the system. It indicates the last addressable block of
number

of 8K

blocks

of available

memory

17777 766

CPU Error Register

17777 770

Microprogram Break Register

Internal

17 777 772

Program Interrrupt Request Register

(bit 0 is equivalent to bit 6 of the Physical Address). Refer to Section IV, Memory Management.

17777 774

Stack Limit Register

17777 776

Processor Status Word

Information

Memory

Management,

Unibus

Data Bus (INTD) at address 17 777 760

3.3

UPPER SIZE REGISTER

This

extension

of the system

size,

Map and Cache Registers are contained in Sections

which is reserved for future use. It is read-only and

IV through VI of this manual.

its contents are always read as zero. Its address is
17 777 762.

3.1

SWITCH

(SWR)

AND

LIGHT

It is read on the Internal

Data Bus

(INTD).

The Switch Register is the output of the Console
switches.

address

777

570

with

the

3.4

SYSTEM ID REGISTER

Light Register, whose input is the BR and whose

This

only

SCCM

output

the

Console

Display

indicators

read-only

SYS

ID(07:00)]

[SCCN

SYS

contains

ID(15:08),

information

through the Display Multiplexer when the Console

uniquely identifying each system. Its address is 17

Data display switch

777

is in the DISPLAY

REGIS-

TER position.

764.

(INTD).

I1-3-1

read

the

Internal

Data

Bus

The CPU Error Register (Figure 3-1) is a read-only
register, consisting of six bits which identify the
source of the abort or trap that used the vector at
location 4. These bits, which are set when the error

The CPU Error Register cannot be loaded by the
program. It is read via the Internal Data Bus
(INTD) at address 17 777 766. The individual bits
of this register remain set until they are cleared by
a DATO. The several bits of this register are de-

occurs, are:

scribed in Chapter 6.

3.5

CPU ERROR REGISTER

Illegal Halt

3.6

Function

Name

Bit

Set when trying to execute a

nance card, the processor can be halted during any

mode (TMCD ILL HALT).

Set when a program attempts

Error

to do a word reference to an
odd address (TMCD ODD
ADRS).

is being operated under the control of the mainte-

CPU is in User or Supervisor

Odd Address

BREAK

for use as a maintenance tool. When the processor

HALT instruction when the

MICROPROGRAM

(PB)
The Microprogram Break Register (PB) is intended

specific microprogram state by loading the address

of that state in the PB and setting the switches on

Non-existent

Set when the CPU attempts to

Memory

read a word from a location

the card to the proper positions. A sync point that
generates a pulse at T1 (when the microprogram address matches the contents of the PB) is provided
on TIGB. During normal operation of the processor, any value can be loaded into the PB without
affecting operation of the processor.

higher than indicated by the

System Size register. This

The PB is loaded directly from the BR whenever

does not include Unibus addresses (TMCD CACHE

the PB address is generated during an external data
transfer; refer to Chapter 5. The PB is an 8-bit regis-

NEXM).

ter that is loaded from the eight least-significant

Unibus

Set when there is no response

be transferred through the DMX to the BR by a

Timeout

on the Unibus within approxi-

Unibus data transfer operation. The PB is selected

mately 10 microseconds

by physical address 17 777 770.

bits of the BR. When the PB is read, the data must

(TMCD UBUS TIMEOUT).
3

The

[PDRC

PB(07:00)]

and its use are de-

scribed in detail in Chapter 4 of this manual.

Yellow Zone

Set when a yellow zone trap

Stack Limit

occurs (TMCD YEL TRAP).

Red Zone

Set when a red zone trap

Stack Limit

occurs (TMCD SL RED ERR).

3.7

PROGRAM INTERRUPT REQUEST REGIS-

TER (PIRQ)

The Programmed Interrupt Request register (PIRQ)

allows a program to schedule the execution of various subprograms according to a priority scheme,

WLEGAL HALT
ODD ADDRESS ERROR
NON-EXISTENT MEMORY {CACHE)
UNIBUS TIME-OUT

and at the same time, allowing various levels of
hardware interrupt priority to interact with the soft-

]

ware priority

levels. The register stores interrupt

requests set by transferring request data to the
PIRQ, and provides information about the requests

YELLOW ZONE STACK LimIT
RED ZONE STACK LIMIT
1-3100

through encoded data transferred from the PIRQ.
Figure 3-1

CPU Error Register

Refer to Figure 3-2.

I1-3-2

The SL is an 8-bit register that is loaded from the

eight most-significant bits of the BR whenever the

11-3097

Figure 3-2

SL is selected by the physical address generated in
an external data transfer. This requires address 17

Program Interrupt Register

777 775 during a byte transfer, or address 17 777

774 during a word transfer. The data is transferred
directly from the BR to the SL; refer to Chapter 5.
To read the contents of the SL, however, the SL

Data is transferred to the PIRQ through the BR
whenever the processor recognizes that the physical

must be selected by the DMX and the data trans-

address is the address assigned to the PIRQ (ad-

ferred from the Unibus to the BR. This requires a

17 777 772). The contents of the PIRQ are

Unibus data transfer operation. Although the SL

then input to the priority arbitration logic of the

and the PB registers share a common DMX input,

processor,

cach register uses a different byte, and only one set

dress

which

uses

the

information

from

the

PIRQ with information from the Unibus and the

is sclected at a time. Therefore, when

PS priority level to determine when requests should

transmitted on the eight most-significant data lines,

the SL is

be honored.

all Os are transmitted on the eight least-significant
data lines.

The data in the PIRQ can be transferred to other

The

devices or to other registers in the processor by ad-

check operations are described in detail in Chapter

[PDRC

SL(07:00)]

and

the

stack

limit

dressing the PIRQ during an external data transfer.

Because the only outputs from the PIRQ are to the
DMX

(Unibus

Data

Multiplexer),

all

transfers

which access the PIRQ are Unibus data transfers.

3.9

PROCESSOR STATUS WORD (PS, PSW)

The Processor Status Word [PDRD PS(15:00), Figure 3-4]

Refer to Chapter 5.

cessor

contains information

mode

(both

current

regarding the pro-

and

previous),

the

PIRQ

[PDRD

PIA(02:00)]

are

PIR(15:09)]

and

PIA

[PDRD

the Trace bit and the Condition Codes. Table 3-1

described

Chapter 6

of this

lists the fields of the PSW. The address of the PS is

17 777 776.

manual.

3.8

STACK LIMIT REGISTER (SL)

Because the number of locations occupied by a
stack is unpredictable, some form of protection

]

NOT USED

PRIORITY

1 T [Nl b3 [ v [ cj
1i-3098

CURRENT MODE *

PREVIOUS MODE *

GENERAL REGISTER

SET(0,1)

against the stack expanding into locations contain-

* MODE: 00 =KERNEL

01:SUPERVISOR

ing other information must be provided. If the pro-

11 =USER

cessor is operating in Kernel mode, the processor
provides for stack overflow detection through the

Figure 3-4

use of the Stack Limit register (SL). Refer to Fig-

Processor Status Word

ure 3-3.

Refer

drawing

PDRD.

The PS stores several

types of data that are dependent on the process
being performed. This data must be stored when-

v
11-3099

cver the processor changes processes; typically, this
occurs every time there is an interrupt or a trap. Be-

causc the contents of the PS control many parts of
the operation of the processor, modifications of the

Figure 3-3

Stack Limit Register

contents are carefully controlled.

1-3-3

Table 3-1

Processor Status Word Bit Assignments

Bit

Name

15—-14

Current Mode

Utilization
Specifies the current processor mode as follows:
1.

When PS(15:14) = 00, the processor is in Kernel mode; all operations are legal.

When PS(15:14) = 01, the processor is in Supervisor mode; HALT,
RESET, and SPL instructions are illegal; SUPER address space is
used if Memory Management is enabled.

PS(15:14) =10 is an illegal mode; if Memory Management is

enabled, a Memory Management abort occurs (refer to Section IV
of this manual).

When PS(15:14) = 11, the processor is in User mode; HALT,
RESET, and SPL instructions are illegal; USER address space is
used if Memory Management is enabled.

13—12

Previous Mode

Specifies the processor mode prior to the last trap, interrupt, or loading of the
PS.

Specifies which General Register set is used; if PS11 = O, register set O is
selected; if PS11 = 1, register set 1 is used.

10-08

Unused

07-05

Priority

Sets the processor priority; this priority determines which levels of programmed
and external device interrupt requests are honored.

Trace

When PS04 = 1, the processor traps to the trace trap vector address after each
instruction fetch; this facility is used for debugging programs.

Condition Codes:

This bit is set when the result of the last data manipulation is negative.

This bit is set when the result of the last data manipulation is O.

This bit is set when the result of the last data manipulation is incorrect because
of an arithmetic overflow.

This bit is set when a carry occurs during data manipulation.

I1-3-4

The four fields of information in the PS are:

Explicit reference — The PS word can be
read by the program with a reference to

Processor condition codes

Trace (T) bit

Processor priority

Processor mode control and register set
selection bits

address

PSW

gated

777

776.

this case,

the

onto

the

Unibus,

from

where it is read during a DATI by the
processor.

3.9.2

Loading the PS

All used PS bits, with the exception of bit 04, (the

T bit) can be written by the program when the PS
address (17 777 776) is used (SCCE PS ADRS H is

Some of the PS bits control the operation of the

asserted). In this case, the input is BR(15:00) and

processor, while others indicate the value of the re-

the clock is a function of MSYN and of UBCB HI
BYTE and LO BYTE. These signals are both as-

sult of the last data manipulation operation.

serted if the PS is referenced as a word.

In addition to accepting inputs from the BR, the
PS receives inputs from the condition-code generation logic.

In certain circumstances (the current

The

Control

shown

mode ficld replaces the previous mode field), some

Codes

IRCH

(bits

and

03:00)

are

are clocked

UBCB CC DATA.

bits of the PS also receive inputs from other bits of
2.

the PS. The outputs from the PS during data transfers can

The Priority bits (07:05) are clocked by

TMCE CLK LO PS.

be directed to the processor data paths

through the BR [by selecting the PS inputs to the
internal

bus

(IBS)

and

the

IBS

inputs

the

BRMX], or directed to the Unibus through the PS
inputs to the Data Multiplexer (DMX). The IBS

The Processor Mode bits and the Register Set bit (15:11) are clocked by TMCF
CLK HI PS.

path is used only for data transfers that implicitly
sclect the PS, such as the stacking operations dur-

The PS may also be loaded under microprogram

ing interrupt and trap service sequences. When the

control (implicit reference). Since the loading logic

PS is addressed explicitly, the data is transferred on

varies from bit to bit, it is explained with each bit

the Unibus, even if the transfer is to the processor

group.

data paths (through the BR).
3.9.3

Processor Mode Bits [PS(15:12)]

The current processor mode is stored in PS(15:14)

3.9.1

and the processor mode previous to the current one

Reading the PS

is stored in PS(13:12).

Implicit reference — The PS word can be
gated

the

Internal

Data

Bus

the

current

mode

other

than

Kernel,

the

PDRD READ PS H, which is generated
by a microprogram IBS field value of 3.

HALT, RESET and SPL instructions are illegal: A

This value is used in microstates
RSD.00, RSD.0I, RSD.02, BRK.20,
BRK.80, TRP.00, TRP.01, TRP.02, and

to 4: RESET or SPL in these modes are NOPs.

When Memory Management is enabled, the mode

HLT.00 to get the current PS into the

bits affect PAR/PDR selection, and thus the phys-

BR.

ical address generated from the virtual address. Re-

This

BR-PS.

shown

the

Flows

HALT in Supervisor or User modes causes a trap

fer to Section IV, Memory Management.

I1-3-5

3.9.4

Current Processor Mode [PS(15:14)]

into or out of any other address space. During trap

The

Current

determine

or interrupt service, these bits are set to reflect the

whether certain instructions are allowed or prohib-

value contained in the current mode bits prior to

ited. The processor mode can be set by moving a

the

data

DATI data transfer is used to fetch the new PS

through a trap or interrupt service function (which

value from the vector address; this causes bits 13

loads a new PS value from the trap or interrupt vec-

and 12 of the PS to be loaded from the old value of

tor), or through an RTI or RTT instruction (which

bits 15 and 14 instead of from BR(13:12).

word

Processor

the

Mode

at its

bits

Unibus address,

interrupt

or trap.

this

case,

KERNEL

restores an old PS from the hardware stack). In this
last case, PS(15:14) can only be changed to a higher

During the return from a trap or interrupt service

value

program (via an RTI or RTT instruction), the old

(i.e.,

these

bits

can

only

set

and

not

cleared). This allows a Kernel mode program to re-

PS value is restored from the stacked value. The

turn to Kernel, Supervisor, or User mode; a Super-

previous mode bits are protected in the same way

visor

as the current mode bits.

mode

program

return

Supervisor or

User mode; and a User mode program only to return to User mode. A User or Supervisor mode pro-

3.9.6

gram cannot use the RTI instruction to enter the

Refer to Figure 3-5. PS(15:12) can only be set, and

PS(15:12) Implicit Write

‘Kernel mode. When a new PS is loaded from the

not cleared, by their direct-set inputs; they can be

trap or interrupt vector, the old contents of PSIS5

both set and cleared when they are clocked. They

and PS14 are loaded into PS13 and PSI2.

are clocked only in three machine states (RTI.50,

When Memory Management is enabled, the current

exist.

SVC.30 and ZAP.30) when appropriate conditions
processor mode selects the mapping for the virtual
machine, except for trap and interrupt processing.

When IBS = 2 (LOAD PS) bits 15 - 12 are direct-

Supervisor and

set

User programs should not be al-

if the

BSC

bits do

not

require

KERNEL

lowed to change the contents of this field. If the cur-

DATI

rent

high. These bits cannot be cleared in this manner.

processor

registers in

mode

Memory

changed,

the

mapping

and

if the corresponding

DATA

input is

Management are selected by

the set for the new mode. The result of attempting

IBS = 2 clocks PS(15:12), thus allowing bits to be

to continue with the same PC value in the new vir-

cleared, when one of three conditions are present:

tual address space is unpredictable.
1.
The cntire PS word can

be protected from direct

PS14 = 0, or the mode is Kernel. This is
used during RTI and

transfers by being mapped only into Kernel address

RTT instructions

when IBS = 2 in RTI.50.

" space. Refer to Section 1V.
2.
PS bits PS15 and PSI14 control and indicate the cur-

TMCE

serted

KERNEL

DATI,

which

is as-

during the service flows (abort,

rent processor mode. The source of input data is al-

trap and interrupt service, see Chapter

ways BR15A and BRI4A, whether the PS is loaded

6). IBS = 2 is asserted during SVC.30,

by an RTT or RTI instruction, or if a new PS is

when the PS is loaded from the BR.

loaded from a trap or interrupt vector, or explicitly
referenced.

SSRA PS RESTORE is asserted when a

Memory Management abort occurs dur3.9.5

Previous Processor Mode [PS(13:12)]

ing

The previous processor mode is used primarily by

the

service

flows.

pens, the PC and

When

this

hap-

PS of the instruction

the MFP and MTP instructions to define which ad-

that caused the abort are restored before

dress

servicing

space

communicate

with.

During

User

the

Memory

Management

mode operation, these bits are set to reflect User

abort. In ZAP.30, IBS = 2 and the old

mode, so that the User program cannot move data

PS value is loaded back into the PS.

I1-3-6

RACB UIBS@1 H ———\_

—~

LOAD PS H

*¥DATA-REFER TO TEXT

DIAGRAM BELOW

)

‘

)

IMPLICIT
REFEREfiE

)

PDRD PS14 (@) L
TMCE KERNEL DATIL
D

I—-

SSRA PS RESTORE H

PDRD PS CLK H

!,/

. PpSi4 ONLY

I ‘

SCCE PS ADRS H————

UBCB MSYN SET H

PDRD

EXPLICIT/

REFERENCE

I——TMCF

CLK HIPS
L

T4H

TSH

I——I

UBCB HiI BYTE H

15:41>

T Tl

PDRB IBS@@ B L

*CLOCK-SEE TIMING

PDR D

DIRECT-SET PS14

CLOCK PSi14

DIRECT-SET PS15,13,12
CLOCK PS15,13,12
1-312

Figure 3-5

PSW Clock and Direct Set Simplified Schematic

Refer to drawing PDRD. Figure 3-5 shows the
DATA input to PS(15:12). This input is BR(15:12),
except in the case of KERNEL DATI. When KERNEL DATI is asserted, bits 15:14 are clocked from
BR(15:14) and bits 13:12 are clocked from
PS(15:14). The new processor mode is thus loaded
into PS(15:14) and the old processor mode into
PS(13:12).

can be external to the processor, in the case of
Unibus requests (BR), or internal, in the case of
Program Interrupt Requests (PIR). In general, the
purpose of requesting control of the system is to interrupt the current processor program and to run a
service routine or higher priority program before returning control to the interrupted program. Refer
to Chapter 6 for a description of the priority
scheme.

3.9.7

General Register Set Bit (PSI11)

The input to PS1t is BR11A. This bit is loaded in
the same manner as PS15 (Paragraph 3.9.6).

The processor priority level may be set by directly
transferring data to the PS, by popping a new PS
from the hardware stack, or by loading the PS
from an interrupt or trap vector. In addition, the
processor priority may be explicitly set by the set
priority level (SPL) instruction.

Priority [PS(07:05)]
The proeessor priority is stored in PS(07:05). The 3bit priority field is interpreted as one of eight priority levels. This level is compared with other
requests for control of the system. These requests

Refer to drawing PDRD. PS(07:05) are clocked in
a manner similar to the mode bits (Paragraph
3.9.6), but are not direct-set. The 74S157 multiplexer selects the input: in all cases, except during
an SPL instruction, the input is BR(07:05),while

PS11 indicates that General Register Set 0 is in use
(when cleared), or that General Register Set 1 is in
use (when set).

3.9.8

I1-3-7

during the SPL the input is BR(02:00) A, which cor-

3.9.10

responds to the position of the new priority bits in

The four least-significant bits of the PS word con-

the instruction word. TMCE SET PRIORITY

tain the processor condition codes. These bits store

Condition Codes

(MSC = 4) controls the multiplexer and gates the

information

clock.

data manipulation during an instruction. The condi-

about

the

value

resulting

from

any

In User or Supervisor modes, the processor priority

dress calculations, but are changed only when an

tion codes are not altered to reflect the results of adcan only be changed by a transfer to the explicit ad-

instruction explicitly operates on an explicit unit of

dress of the PS (17 777 776). This is possible only if

data.

Memory Management mapping allows it.

The condition codes can also be set to any specific
3.9.9

value by transferring a word containing that value

Trace Bit (T Bit, PS04)

The Trace (T) bit is provided as a software diagnos-

to the PS address. The value of the condition codes

tic aid. When this bit is set, a processor trap will be

arc altered by every interrupt or trap response func-

vectored through location

14. This trap occurs at

tion. and by every RTI and RTT instruction. In ad-

the end of the instruction that is being performed

dition,

when the T bit is being set, unless:

manipulated directly, with the condition-code oper-

individual

condition-code

bits

may

ate instructions. These instructions provide a means
I.

The instruction is a Return From Trap

to set

(RTT) instruction. In this case, the trap

with

any one, or more, of the condition codes

is delayed until the end of the following

memory reference; a similar set of instructions can

instruction.

clear any one or more bits. The condition codes are

single

instruction ‘that

requires

only

one

used in conditional branch instructions, so the vari[N

The instruction is a Set

Priority

ous means of manipulating the condition codes are

Level

(SPL) instruction. No BRQ STROBE is

uselul because they permit setting up the PS word

generated

to respond

during

the

execution

in a particular way to various branch

instructions.

SPL.
Some other trap or interrupt condition is
honored. In this case, the PS containing

The logic that senses data conditions and stores the

the T bit is pushed onto the stack and

selected indications is on the IRC module and is de-

all Trace operations are deferred

until

scribed in Chapter 1; the gates that control the read-

the PS word is popped off the stack at

ing of the condition codes onto the internal data

the end of the trap or interrupt service

bus arc shown on drawing PDRD. When the PS is

routine.

explicitly addressed at physical address 17 777 776,

the data transfer is on the Unibus; the internal bus
The T bit cannot be set by moving data to the PS;

is used only under direct microprogram control.

the only way the T bit can be set is by popping a
word off the hardware stack with bit 4 set. This can
be done with an RTI, an RTT, or any trap instruc-

The condition codes are loaded automatically with

tion (TRAP,

the results of most data manipulations. In addition,

10T,

BPT or EMT), even when the

processor is not in Kernel mode. The purpose of in-

the codes can be manipulated by a microcoded in-

hibiting other methods of loading the T bit is to

struction that can set or clear individual condition

protect the user from inadvertently setting the T bit

code

while changing the processor priority or condition

direetly to the processor status word inhibits the set-

codes.,

ting of the condition codes, because the data trans-

The

presence

of the

bit

precludes

the

use of

bits.

mitted

done

for

Any

loaded

operation

into

that

PS(03:00)

transmits

directly.

data

This

move instructions that address the

PS,

IEXC.80 by E/class*DMO instructions, since the T

RTI instructions that pop a value off the hardware

bit

stuck

trap

request.

EXC.90 is executed

in this

into

the

PS,

or interrupt service

that load the PS from the interrupt vector.

Ccise.

I1-3-8

sequences

CHAPTER 4

TIMING GENERATOR

(TPB) from that required by the other modules. A
TF failure does not stop the clock.

The Timing Generator supplies the clock signals

which control the various operations of the KB11-C

Processor System. The M8139 module contains all

The TPB pulses drive a five-stage ring counter, the
output of which generates gates to generators for
time pulses Tl - TS and for time states TS1 - TSS.

the components of the Timing Generator.

Refer to Figure 4-1. The synchronizer selects one of
three clock sources: A 33 MHz crystal clock, an
R/C maintenance clock (variable) or a pulse generated by a manual stepper switch. The selected clock
signal is routed through a phase splitter/buffer, the
output of which consists of two 180° out-of-phase

The ring counter is generally stopped during a
pulse cycle to allow the data transfer operation in
progress to accept the data. It is stopped in T2 for
Unibus, Internal Data Bus, interrupt and maintenance operations, and in T5 for Cache operations.
The ring counter is also stopped during maintenance operations such as single cycle.

ciock signals. These two signals are buffered again
and are called TIGC TPB H, TPB L, TF H and TF

L. TPB H and TF H are identical and are 180° out
of phase with TPB L and TF L, which are also

CLOCK SOURCES

4.1

identical.

The three sources of timing are the crystal clock,
the R/C clock, and the MAINT STPR switch SO
(on the maintenance card). These timing sources

Separate TPB and TF pulses are provided to sepa-

rate the timing source required by the TIG module

are shown on drawing TIGB.

STOP CLOCK

SOURCE
CLOCKS
XTAL CLOCK
33 MHz

PAR.4.2 & 4.3

\r\

RING COUNTER
>

(SELECTS ONE

OF THREE
SOURCE CI.OCKS)

TIGA

BUFFERED

TIMING

R/C CLOCK

TIGA

SYNCHRONIZER
AND PHASE
SPLITTER

PAR. 4.5

PAR. 4.4, | PAUSE CYCLES

PULSES

TPB H

PAR. 4.6

T=T5

TF L

_T|GC. TIGD

MAINTENANCE
STEPPER SW.

TIME STATES

TS1-TS5
TIGE

XMAA S4

TIGB

PAR.4.7

TIME PULSES

TPB L

TIGB

Figure 4-1

Tiee

Timing Generator Block Diagram

11-4-1

11-3116

4.1.1

Crystal Clock

EN flip-flops are not set, the XTAL SYNC flip-

The crystal clock provides a constant square wave

flop is set. With maintenance card switches S1 and

output of 33 MHz. The oscillator frequency is deter-

S2 equal to 0, MS EN will be cleared, as will RC

mined by the

SYNC and RC EN. Therefore, XTAL SYNC is set

stabilized

LC tuned-collector network and is

by the crystal connected between emit-

ters. The bias network in the base circuits ensures

and the source multiplexer output, TIGB SOURCE
CLOCK L, will follow the XTAL H input.

that the oscillator will start when +5 V is applied
to the module. The amplified output, TIGB XTAL

Note

maintenance

is a

+3.5

to 0

square wave with

period.
4.1.2

a 30-ns

R/C clock

the

XTAL

flip-flop

inhibits

the

module switch S3 inputs to the RC

EN flip-flop. Therefore, the XTAL SYNC flip-flop
must be cleared before a timing source change can
be accomplished. The RC EN and MS EN gating

R/C Clock

The

that

is provided for maintenance pur-

poses and can be enabled only when the mainte-

input

the XTAL SYNC

flip-flop ensures that

nance card is plugged into the CPU backplane. The

these sources have been disabled before XTAL EN
is allowed to gate the XTAL H pulse through the

frequency of the square wave output, TIGB RC H,

source multiplexer.

can be adjusted as high as 37 MHz by varying potentiometer

R104

the

feedback

network.

4.2.2

RC Clock Selection

Thus, the clock pulse period can be narrowed to ap-

The RC clock is selected as the timing source when

proximately 27 ns to test for race conditions in the

maintenance card CLK switch S3 is on RC, and S2

logic.

and S1 are both set to 0. When the XMAA S3 L in-

put is low, the RC SYNC flip-flop will be set. As a
4.1.3

MAINT STPR Switch

result,

The third source of timing is the manually-oper-

the

source

flip-flop

multiplexer

will

output,

be set

TIGB

and

the

SOURCE

ated, single-step MAINT STPR switch S4, located

CLOCK L, will then follow the TIGB RC H input.

on the maintenance card. This switch is only enabled when maintenance card switches S2 and S3

TIGB XTAL EN (0) H and TIGB MS EN (0) H
are fed back to inhibit TIGB RC SYNC D inputs

are both set to 1. Each operation of S4 creates one

to ensure that the enable flip-flops are cleared be-

transition of a given timing pulse. It therefore re-

fore the timing source can be changed.

quires

two actuations of S4 to complete a given

time pulse.

4.2.3

MAINT STPR Selection

The maintenance card S2 and St switches are both
4.2

SOURCE SYNCHRONIZER

set to

The timing source synchronizer is shown on draw-

to allow single timing pulses to be gener-

ated by MAINT STPR switch S4. The XMAA S|

ing TIGB. The purpose of the source synchronizer

L and XMAA S2 L inputs are both low. The result-

is to select only one timing source at any time and

ant input to the MS EN flip-flop D input causes

to inhibit the two remaining sources. The synchro-

the

nizer prevents cycles of improper length

XTAL H and TIGB RC H clock pulses, the XTAL

sures that TIGB
high

SOURCE CLOCK

and en-

L is in

the

(non-asserted) state when switching between

flip-flop

set.

the

following

TIGB

SYNC and RC SYNC flip-flops will be reset. Suc-

cceding clock pulses will then reset the XTAL EN

sources. Timing source selection is determined by

and

the setting of switches S1, S2, and S3 when the

with

STEP (1)

maintenance card is plugged in. If the maintenance

CLOCK

flip-flops.

MS EN (1) H is ANDed

assert

the TIGB SOURCE

L output of the source multiplexer. Each

card is not installed, the crystal clock is the only

time the MAINT STPR switch S4 is operated, the

source of timing. The following paragraphs describe

STEP flip-flop toggles. The MAINT STPR switch

timing source selection when the maintenance card

must be actuated twice to complete a single TIGB

1s plugged in.

SOURCE LOCK L output pulse. Removing the S2

or S|
4.2.1

Crystal Clock Selection

When

maintenance

card

switch

input conditions the MS EN flip-flop to be

cleared. MS EN (0) L direct-clears STEP to condi-

not

set,

tion

XMAA S3 L is high. When the RC EN and MS

it for the next time the ING TP function is

selected.

11-4-2

4.2.4

Synchronization

A feature of the source synchronizer is that the out-.
put level is maintained high (non-asserted) while
the timing source is being changed. The timing diagram in Figure 4-2 shows the TIGB SOURCE
CLOCK L output as the maintenance card CLK
switch is changed from XTAL to RC. With the
XMAA S3 L input low (RC clock selected), the
XTAL SYNC flip-flop is cleared on the next TIGB
XTAL L clock pulse going low.

is available for the enable flip-flop to change states
and gate the associated clock source through the
multiplexer.

4.3

PHASE SPLITTER/BUFFER

The Phase Splitter/Buffer, shown on drawing
TIGB, is driven by TIGB SOURCE CLOCK L
from the source synchronizer to produce timing
pulse outputs TIGB CLOCK L and TIGB CLOCK
H. The TIGB CLOCK L output pulses are in
phase with TIGB SOURCE CLOCK L.

One XTAL H clock pulse later, XTAL EN will be
cleared, enabling the D input to the RC SYNC
flip-flop. The next time TIGB RC H goes low, RC
SYNC will be set. The difference in XTAL H and
"'RC H pulse widths is exaggerated in Figure 4-2 to
indicate that the clock pulses are completely
independent.

Note that the SYNC and EN flip-flops are clocked
on the trailing edge of the source locks so that the
gating level to the source multiplexer is always removed as the clock input is non-asserted. This provides a clean leading edge for TIGB SOURCE
CLOCK L. Note also that only half a clock period

4.3.1

Level Converter

Transistors Q65 and Q66 convert the TIB
SOURCE CLOCK L output to the level required
at the phase splitter inputs. A low logic input at the
base of Q65 causes this transistor to conduct, thus
grounding the common emitter of Q65 and Q66.
The +V2 reference voltage applied at the base of
Q66 cuts this transistor off, causing no current to
flow through Q66 and R122. Thus, a low input pro-

vides a low output. When TIGB SOURCE
CLOCK L goes high, Q65 cuts off, and the +V2
reference at the base of Q66 allows current to flow
through Q66 and R 122 to provide a high output,

TIGB XTAL H

TIGE XMAA

TIGB

TIGB XTAL SYNC
XTAL EN

TIGB RC

TIGB RC SYNC

(

TIGB RC EN

TiIGB SOURCE

CLOCK L

~__ [

t1-0788

Figure 4-2

Timing Source Synchronization

[1-4-3

4.3.2

Phase Splitter

TPB

and TF

are driven

from CLOCK

The phase splitter consists of two emitter-coupled

TPB L and TF L are driven from CLOCK L. With

2N3009

TIGB

‘this exception, the circuits that generate these four

L is not asserted (high), Q61

pulses are identical: when TIGB CLOCK is high,

transistors,

SOURCE CLOCK

Q61

and

Q62.

When

turns on. A fixed bias at the Q62 base holds that

the NPN transistors conduct, the PNPs are cut off,

transistor

and the output is high.

cut

off.

Under

these

conditions,

the

TIGB CLOCK H output provided by buffer Q53
and Q54 is low because Q61 is conducting. Q54 is

When TIGB CLOCK is

low, the NPNs are cut off, the PNPs conduct, and

the output is low.

on.

When TIGB SOURCE CLOCK L

starts to go low,

4.5

RING COUNTER

as the result of a clock pulse, the base of Q61 goes

The Ring Counter is shown on drawing TIGA. It

negative with respect to the Q62 base. More current

consists of the two edge-triggered D flip-flops, TI

lows through Q62, causing a greater voltage drop

and TI1A, of the six J-K flip-flops T2 - T5, T2A

across the Q62 collector resistor, R109-R111. Less

and T5A,

voltage is developed across common emitter resist-

Figure 4-7 for the description that follows.

and their associated circuitry.

Refer to

ors R89-R96, increasing the forward bias on Q62.
As a result, when Q62 starts to conduct more current, Q01 starts to cut off. This circuit is a differen-

Start-Up and Normal Cycle

tial amplifier that responds to slight changes of the
input signal at high speed. When TIGB SOURCE

The ring counter is cleared by ROM INIT, which is

CLOCK L starts to go positive, Q61 turns on and

Console

Q062 cuts off in the same manner. The switching ac-

HALT/ENABLE switch is in the HALT position.

asserted on power-up, power-down, and when the

tion of Q61 and Q62 follows the TIGB SOURCE
CLOCK L signal with about a | ns difference be-

START

switch

depressed

while

the

T4 is not cleared by ROM INIT directly, but by a
flip-flop that is set by ROM INIT. When ROM

tween TIGB CLOCK H and TIGB CLOCK L.

INIT is negated, the trailing edge of the next TPB

L clears this flip-flop.
4.3.3

Buffers

Each

buffer

stage consists of a 2N3009 and a
2N4258 transistor. When Q61 turns off as a result

When the ring counter has been cleared, the J input
of T4 is high [T5 (0) H, T2 (0) H and T1A (0) H

of a low source synchronizer output, Q53 is turned
on and Q54 is cut off. Thus, the TIGB CLOCK H

are all high] and the next TPB sets T4.

output goes high, 180° out-of-phase with the TIGB

SOURCE CLOCK L input. At the same time, Q62

It should be noted that the D flip-flops (T1 and
TIA) are clocked by the trailing edge of TPB L,
while the J-Ks are clocked by the trailing edge of

turns on and the positive collector cuts off Q5 and

forward-biases Q56. Therefore, TIGB CLOCK
goes

low

phase

with

the

TIGB

SOURCE

TPB H.

Both of these trailing edges occur at the

CLOCK L input from the source synchronizer.

same time,

4.4

TIGC TPB AND TF

The

outputs

The next TPB after the one that sets T4, sets TS
and T4 complements (both J and K high) and is re-

of the

Phase

Splitter/Buffer,

TIGB

CLOCK H and CLOCK L, are buffered to generate the Time Pulses Buffered, TPB H and TPB L

set. If TIGA STOP T1 L is high, the next TPB complements TS (resets it) and sets T1. T5 (0) H is now

and the Free Clock pulses, TF H and TF L. TPB

high and asserts STOP T1 L. The TPB that follows

H and TF H are in phase with TIGB CLOCK H,

and are the complement of TPB L and TF L.

clears T1 and sets T2 but, since the common input
to T2-K and T3-J is low at this time [due to T2 (0)

The TF pulses are used throughout the KB11-C for

TPB toggles T2 (clears it) and sets T3. T5 (0) H, T2

synchronization. The TPB pulses are used only on
the M8139 module.

H] T3 is not set. T2 (0) H is now low, and the next
(0) H and TIA (0) H are all high, thus allowing T4

to be set as T3 toggles.

11-4-4

The ring counter flip-flops are used to gate the tim-

and at TS H by a 33 ohm resistor to ground. These

ing pulses T1 - T5. Note that there are two T2 and

lines are transmission lines, designed to guarantee

two T5 flip-flops. In both cases, the second flip-flop

the integrity of the CLOCK H and CLOCK L

(T2A and T5A) is used to generate its correspond-

signals from the phase splitter to the intended pulse

ing timing pulse. These flip-flops are used to pre-

generator.

vent the generation of more than one timing pulse
(T2 or T5) during Pause cycles: T2A and TS5A are

The +V and -V voltages shown on the schematics

reset

are taken from diode dividers shown on TIGB for

the TPB

following the one that sets

them, while T2 and T5 remain on for the duration

+VS5 to +VI1 and on TIGE for V3 to -VI.

of the Pause.
4.6

Since the circuits for T(1:5) H are identical, as are
those for T(1:5) L, only the T5 schematics are ex-

TIMING PULSES, T1-TS

The switching times of the flip-flops used in the

plained below.

ring counter are not very precise; therefore, the flip-

flop states are not used directly for processor timing. Instead, high-speed transistors are used to gen-

Figures 4-4 and 4-5 are simplified schematics of
TIGD T5 H and L, respectively. Q53 and Q54 on

erate the timing pulses. The timing pulse generator

the first figure and QS5 and Q56 on the second, are

schematics

are

shown

drawing

TIGC

the

and

output

the

Phase

Splitter/Buffer,

TIGB

TIGD.

CLOCK

H and L. The diode terminators are se-

lected

produce

Each of the timing pulse generators gates the Phase

imately 0 to +3.0 V for TS H and of approximately

pulse amplitude of approx-

Splitter/Buffer clock output, TIGB CLOCK H or

+3.0 to 0 V for TS L. Q32 and Q50 are not shown

L. with a ring counter output to generate the tim-

on Figures 4-4 and 4-5. These transistors are turned

ing

off when TIGA TS5A is asserted, thus allowing Q31

pulse

associated

with

that

state.

Figure 4-3

shows how T5A (1) H and T5A (1) L are gated

and Q49 to conduct. Q32 and Q50 conduct when

with CLOCK H and CLOCK L to provide the T5

TIGA T5A is negated and turn Q31 and Q49 off.

H and TS5 L timing pulses.
Note on drawing TIGC that the TIGB CLOCK H

NOTE

and L signals are carried by two separate lines to

The voltages shown on Figures 4-4 and 4-5 are ap-

the timing pulse drivers; these lines are terminated

proximate. They are based on a diode voltage drop of

at the TIGD TS5

0.7 V.

L circuits by diode terminators

I'_T'-YPICALLY

TIGB CLOCK

[ H

TIGA T5A (1)H

‘

als

L—m

TIGB CLOCK L

30ns

TIGA T5A (1)L

TIGD TS5

TIGD T5 H

L
11-0786

Figure 4-3

Timing Pulse Generation

11-4-5

46.1

TSH

+5V

Refer to TIGD and to Figure 4-4(a). The output
transistor pair, QI and Q2, is arranged to give a
push-pull type output. Diode D2 between the two
bases, along with the resistor network consisting of
R12 (15K to +15 V) and R10 (3K to =15 V), biases
the transistor pair QI and Q2 so that a small volt-

4¢
Q53 [

TIGB CLOCK H

100

)

age change at the base input turns one transistor on

Q21

and the other off. This arrangement has the effect

f
+5V

-V3A

of reducing the propagation time from the CLOCK

+V5

+V5H

+I15V

15K

H signal to the output time pulse TIGD T5 H.

Diode D1 clamps the bias at a level such that T5H

is at approximately 0 V when either CLOCK H is
low or the gate transistor Q31 is off. Diode D3 pre-

(Q32)

02 ¥

+0.7v.

——

o7V

ping the signal to +V5, or approximately 4 V.

-V38
=

-15V

TIGB CLOCK H

When TIGA TSA (1) H is low, Q32 conducts and
Q31 is cut off. When TSA (1) H goes high, Q32

‘

‘%33

TIGA T5 (1) H_J__L_

cuts off. Q31 cannot turn on at this time, since its
emitter is negative (CLOCK H at approximately 0

TIGB CLOCK H

~V3A

V. determined by the base voltage of Q54) with re-

TIGD TS H

spect to its base (=15 V - D36 to +V2 = approx-

11-3113

approximately -0.7 V and that at the base of Q2 is

Figure 4-4a

one¢ diode drop more positive, Q2 is off and QI conducts: TS5 H is low.

Figure 4-4(b) shows

Q31

vents the bias circuit from saturating Q2 by clam-

imately +0.7 V). The voltage at the base of QI

+5V

the circuit when

TIGB

CLOCK H goes high. Q54 is now off and Q53 is

Q53

on. The emitter of Q54 is now positive with respect

+V5

| (

(

to its base and it conducts. The voltage at the base

TIGB CLOCK
H

of Q1 and Q2 becomes more positive; Q1 conducts

and Q2 is turned off. TS H goes high.

+5V

+4.2v | (' 10

—_—

'I |

| |
| |

Q31

+3.0v

+3.9v

— -

-v3B

-15v

=
TIGB

—

Y02

+3.5V

Q54

—

(Q32)

__S(’

—

15K

+15V

+V5

CLOCK H

TIGA T5 (1) H

TIGB CLOCK H

iss

-V3A

TIGD T5 H

[

|
11-3114

Figure 4-4b

11-4-6

Figure 4-4(c) shows the end of the TS H pulse.
TIGB CLOCK H goes low: Q53 turns off and Q54

TIGB CLOCK H

turns on. TIGA TSA (1) H goes low and turns Q31
off. Q21 turns on and the voltage at the base of QI
and Q2 goes negative, turning Q2 off and QI on,

Q53 —Ts(,—

thus making TIGD TS5 H low. Q21 speeds this tran-

sition by providing a discharge path for the charge

left in the base bias circuit.

100

=
+5V

-V3A
+15V

+V§6
D3

15K

-0.3V
C

+4.7V

|
l

I‘L

—_———

D2y

Q32)

054@?

Q21

-0.7V

Tesc
-15V

TIGB

CLOCK

-V3B

TIGA TS5 (1) H l |

-V3A

TIGB CLOCK H

TIGD TS H

|—|
11~ 315

Figure 4-4c
462

TSL

Refer to TIGD and to Figure 4-5(a). The output

+5V

transistor pair, Q19 and Q20, is arranged to give a

+Vv4

push-pull type output. Diode D29 between the two

TIGB CLOCK L

bases, along with the resistor network consisting of
R6!

(IK

+15

and

RI10 (4.7K

to -15

Q55| —{¢

V),

biases the transistor pair Q19 and Q20 so that a
small voltage change at the base input turns one

—-V1A

transistor on and the other off. This arrangement

has

the effect

of reducing

the

propagation

+5V

time

+V4

030+

from the CLOCK L signal to the output time pulse
TIGD T5 L. Diode D30 clamps the bias at a level

such that TS5 L is at approximately +3 V when either CLOCK L is high or the gate transistor Q49 is

+|5vl

Q20

1K |

+ 3.5V

{Q50)

off. Diode D28 prevents the bias circuit from satu-

+2.8V

rating Q19 by clamping the signal to ground.

D29

-—

+2.8v

_—

Q49
D28

47K

When TIGA TS5 (1) L is high Q50 conducts and

Q19 ]

+vgq

-V3B

Q49 is cut off. When TS5 (1) L goes low QS50 cuts

.
)]

off. Q49 cannot turn on at this time, since its emit-

ter s positive (CLOCK L at approximately +3.5 V,

dcetermined by the base voltage of Q55) with respect

Q56

to its base (15 V - D49 to +V3 = approximately

TIGA TS ()L l
TIGB CLOCK L

+2.8 V). The voltage at the base of Q20 is approximately +3.5 V and that at the base of QI9 is one

-15V

TIGB CLOCK L

TIGD TS5 L

diode drop more negative. Q20 is conducting and

I
|

’r

~-VI1A

1n-3nzy

Q19 is off: TS L is high.
Figure 4-5a

11-4-7

+5v

Figure 4-5(b) shows the circuit when TIGB
CLOCK L goes low. Q55 is now off and Q56 is on.

the emitter of Q49 is now negative with respect to

its base and it conducts. The voltage at the base of

Q55

TIGB CLOCK L

Q20 and Q19 becomes more negative; QI9 con-

100

ducts and Q20 is turned off. TS L goes low.

—-ViA
+5V
+5V

Q30

+15V

+v4

D30

Q20

- 0.3V
i

210

(

-0.7V

(Q50)
gv

—

D29y r

-07v|

Q49

'
=
TIGB CLOCK L

n
|

~-V3A

+Va

347K qi9

]

D28

-Vv3B

-15vV

TIGA TS (1)L

TIGB CLOCK L

~V1A

TIGD TS5 L

|
11-3118

Figure 4-5b
+5v

Figure 4-5(¢) shows the end of the TS5 L pulse.

+V4

TIGB CLOCK L goes high; Q56 turns off and Q55
turns on. TIGA T5A 1 L goes high and turns Q49
off. Q30 turns on and the voltage at the base of
Q19 and Q20 goes positive, thus making TIGD T35
L high. Q30 speceds this transition by providing a
discharge path for the charge left in the base bias

Q55

circuit.

+3.5v

(Q50)
1.7V

Q49

428y

'
+2.8V
Yoo
W

D28

47K

Q19

TIGB CLOCK L

Q56

TIGA T5(1)L
TIGB CLOCK L

TIGD TS L

@: S 1&
-ViA

"-319

Figure 4-5¢

11-4-8

START-UP
Table

summary

of Stop

and

Pause

conditions.

TIGA T3 (1) H

[

TIGA T4 (1)H

| ! |

TIGA TSA (1) H 1

Emm

i
i

i
|

TIGE TS5L

|
‘

TPX H | ITll T2

E
i

T2]

|T3

11- 3120

Figure 4-6

Time States

PAUSE CYCLES AND CLOCK BR

The ring counter is stopped during Pause cycles, except in the case of a Cache read hit cycle. The stop
occurs during T5 for Cache Pause cycles and dur-

ing T2 for Unibus, Interrupt (INTR) or Internal
Data Bus (INT D) cycles. The INTR Pause cycle is
one

where

UBSD=1;

for

all

other

Pauses,

UBSD=2 or 3} [TIGA PAUSE H=ROM
40 asserted (UBSDOI=1)].

TIGA PSEUDO T3

—

TIGA T2 (1)
H

and SO (0) H are low, the output of the
74565 gates goes high, and on the net TPB pulse,
T2 (1) H is cleared, T3 (1) H is set, and the ring

FOR INTR
PAUSE

TIGA

ADRS

MEMSYNC

]

is asserted

not

asserted,

INTR PAUSE

Tiee:p Tx H

—
—
A
S
S
S

Itl

)

;

Cache. When this occurs, TIGA MEMSYNC (OH

TIGAT3 (1) H,|

TIGAT4 () H, 1i

Asynchronous Pauses

CACHE pAuss{

Synchronizing flip-flops are required during asynch-

TIGA T5 (1) th

[T
|
1

TIGA MEM SYNC (@) H'|

sible instability of flip-flops when clocked at the
same time that their data input is changing.

*FLIP-FLOP # 2° i

——
——
—
-

]

[

:
—

riec:0 Tx v,[Tl

|i
D

|
.
e

A
1

o
P
]

b
I

)

|
|

tha

TIGA CLK BR H,_L

Refer to figure 4-8

R_f_#
ol

ronous Pause cycles in order to minimize the pos-

*NOTE:

I
I

*FLIP-FLOP #1

Ifib

w1—I
1
—22

4.8.2.1

'
CACHE PAUSE CYCLE—l——I

TIGA Tt (1) HJ_—L

goes low. The next TPB sets T1, clears TS and res-

TIGAT2 (WK|

L,
'

/Mo
hal
|
|
!

]

I
]

]

! 7] [

[

)

TIGA PSEUDO T3

is asserted and prevents T1 from being
set until CCBC MEMSYNC H is asserted by the

stopped during T2, as for the INT D Pause.

TIGA

Unibus Pause (T2) - Refer to Figure 4-7.
During a Unibus Pause cycle, the-ring counter is

t——

;

)

TIGAT4 ()H_|

—

TIGA T3 (D H_!
o

;

TIGA 1ST SYNC F/F
TM T

)

TIGA 2ND SYNC F/F
T

during a

then

[

I!'

STOP T1 L

4.8.2

]

UNIBUS on{

}

UBCB TIG RESTART H_ |

pause for a Cache cycle and, in conjunction with
TIGA PAUSE; if there is no abort pending, and if
TIGA

]

S1()H_

}

i
33

NOT USED | TIGA S@ (1) H

Cache Pause (5) - Refer to Figure 4-7. The

CACHE

(0) H

—

TeATIMMH

UNIBUS OR INTR PAUSE cvcu-:l—-l

(UBSD=2 or 3, Bus Pause). S1 and SO are clocked
by TPB H and count up to 3. At this time, both S1

TMCF

—

— o

TIGC:D Tx H

—

TIGATS (1)H

tarts the ring counter.

4.8

TIGATS ()H_

TIGE Ts4|._|

ally not stopped; all other Cache cycles stop the
counter. CCBC MEMSYNC H is asserted by the
Cache when it has completed a memory cycle.

TIGA T4 (1)
H

ring counter stops in T5 during a Pause for a
Cache cycle. A read hit Cache Pause cycle is the
only Pause cycle in which the ring counter is gener-

]

TIGE TS3
L

set until this input becomes high. The low is caused
by the two gates that have SAPN NOT CACHE
ADRS H as inputs. Since the INT D registers have

4.8.1.2

TIGAT3 (VH

counter is restarted.

TIGBTPBHII'I'III'III'III

TIGE TSIL
TIGE TS2L

fli

TIGA SIMNK

]

| ,'

TIGA S@ (1)H ;777]

TIGA T2A (1)H

]

input of the T2 flip-flop. The flip-flop cannot be re-

Unibus addresses, this signal is high. S1 (0) H and
SO (0) H are also high, as well as TIGA PAUSE H

TIGAT2 (1)H

The ring counter is stopped by the low output of
the 74565 gates which cause a low input to the K

]

SO and S1 flip-flops.

[

Internal Bus (INT D) Pause (T2) - Refer to
Figure 4-7. During a Pause for an INT D read, a

is on from the leading edge of T! to the leading

TIGA nmul

}

—f

90-ns delay is inserted between T2 and T3 by the

the load requirement of the timing pulses.

T-T —J."'J.""'J

TIGATI(1) H

The time states are used throughout the KB11-C
and are on for two time pulse durations (e.g., TSI

areas where timing is not critical, in order to reduce

Synchronous Pauses

4.8.1.1

for use in

]

ing pulse of the same number (e.g., TS1 to TI)

These time state pulses are provided

[}

]

4.8.1

edge of these pulses corresponds to that of the tim-

edge of T3).

MLIMLMLUMULULN gugigEgigipigigigigigiy

TIGCTPBH||||||||||||||||||||'||||||||'||||||||||'||'||'

TS1 L through TSS L are generated from the ring
counter flip-flops and TIGB TPB H. The leading

mec
e L _[M

|~— NORMAL CYCLE —ufi—m D PAUSE CYCLE ——‘I

[

Refer to Figure 4-6. The Time State pulses, TIGE

4-1

TIME STATES (TIGE TS1 L-TS5 L)

3..___

4.7

]

)

LML

FLRLAFALFs
11-3121

Figure 4-7

Timing Generator and Pauses
(Figure repeated on next page)
11-4-9

START-UP

I‘—NORMAL CYCLE—C"-——INTDPAUSE CYCLE———"

TlccTPaH|r]r]|"||‘|['||']|‘||||||||||||||||||||||||||||
TIGA T1 (1) H

TIGA T2 () H

Teh s

TIGAT3 (0K

TIGA S@ (VH 22

[

] : LJ L

—

TIGA T4 (1) H

r—|‘\mM |! .

;

TIGA TS (1)H

I Il

TIGC:D Tx H

TIGA PSEUDO T3

, TM

~———

TIGAT2MH

I l LI

L.,

—e

| TIGA S1()H_|

;

TIGAT3 (0K, 1

TIGA TS (1) H_fi;

Ring Counter Stop and Pause Conditions

STOP
IN T2

Internal Bus Pa
nternal

Pause

Unibus Pause CPU Control
Registers
:

TIGA PSEUDO T3 |

TIGAT3 (1)H_|
il

: |

TIGATS () H:L

[

TIGA MEM SYNC (B) H |

*FLIP-FLOP # 2" i

—_

*FLIP-FLOP #1 :

TIGA CLK BR H, | _
|

:4
Ll

_A 4 9,

o
o

]

| ||

: ]':'
:

!_[

2 M

_fre

Tise:D TX W,y
AL
L R
AL

SO and S1 count to 3 (90 ns).

Stop::

Same as _IInternalal Bus
AND
] , Pause

Restart:

Same as Internal

Stop:

UBCD EXT BRQH

Stop:

Restart:

UBCB TIG RESTART H

(Passive Release or BUS INTR)

TIGB ROM+UPB (1) H

CONTINUE or MAINTENANCE

.
(XMAA S4) switches

STOPINTS

Cache Pause

Stop:

TMCF CACHE ADRS H
TIGA PAUSE H (UBSD =2 or 3)

No Aborts (not TMCC ABORT H)

Restart:
Single Bus Cycle

TIGA MEMSYNC (1) H

Stop:

TIGB SINGLE CY L

Restart:

CONTINUE or MAINTENANCE

Bus

UBCB TIG RESTART H

UBSD = 1 (INTR Pause)

P!
'
L1
|

Single ROM Cycle

)

;

Restart:

[ !__:__ll_':'*
-J

Interrupt Pause

TIGAT4 (1)H
|
o

—
-

—

.: 2

| '

le——— CACHE PAUSE CYCLE
|

TIGA PAUSE H (UBSD = 2 or 3)

(BUS SSYN)

SAPN NOT CACHE ADRS H

top:

: 2

TeATI 4 ]
TIGAT2 MH| [ 1

.
|
:

;

TIGA SO (0) H or TIGA S1 () H

{

Bus

;

TIGC:D Tx H ,..'r_JfiLfiil_'

—

TIGA T4 (1)H_|

*NOTE:

TIGA 2ND SYNC F/F’ :
N

CACHE PAUSE(

Table 4-1

TIGA 1ST SYNC F/F :

(

UBEB TIG RESTART Myi

'
|
le—————uniBus
OR INTR PAUSE CYCLE———]
|
co

PAUSE

INTR PAUSE

{1.

TIGA T1 (1) HPJ"_I

!
NOT USED {TIGA S@ (1
H+

UNIBUS OR

—R

l n

:4‘

n-3121

Refer to figure 4-8

Figure 4-7 Timing Generator
and Pauses
11-4-10

TIGA PAUSE H

(XMAA $4) switches

The Unibus Pause is started by the same two gates

asserted during an INTR Pause cycle (UBSD=1);

that start the INT D Pause, in addition to the gate

the output of the second rank synchronizing flip-

that has UBCA UNIBUS ADRS H as an input.

flop is high at this time. UBCD EXT BRQ H is as-

SCCD INTD REG (1) L is high, since the address

serted when any of TMCA HONOR BR(4:7) are as-

does not refer to an Internal Bus register.

serted. The T2 flip-flop remains set and the T3 flip-

There are two synchronizing flip-flops for this gate:

flip-flop is set. S1 and SO count up but have no ef-

flop cleared

until the second

rank

synchronizing

the first rank flip-flop is the one that has UBCB

fect, since they are ANDed with TIGA PAUSE H

TIG

RESTART L as its input; the second rank

(UBSD= 2 or 3), which is low. UBCB TIG RES-

flip-flop has the output of the first rank flip-flop as

TART H is asserted either by the receipt of INTR

its input. The output of the second rank synchro-

or by a passive release of the Unibus (UBCA PAS-

nizing flip-flop is high at this time. The output of

SIVE L). The first rank synchronizing flip-flop is

the 74565 gates is low, T2 (1) H is not cleared, and

sct by the next TPB L, and the second rank flip-

T3 (1) H is not set. The SO and St flip-flops count

flop by the TPB after that. This disables the EXT

to 3, at which time the NOT CACHE ADRS gates

BRQ gate, and the output of the 74S65 goes high,

are disabled. When BUS SSYN is received, UBCB

allowing the ring counter to restart.

TIG RESTART is asserted. The first rank 'synchronizing flip-flop is set by the next TPB L, and the

4.8.3

second rank flip-flop by the TPB after that. This

During any cycle during which UBRK (load BR) is

CLK BR, BRA

disables the UNIBUS ADRS gate, and the output

asserted, the BR is loaded at the proper time. Dur-

of the 74S65S goes high, allowing the ring counter

ing a Cache Pause cycle, the data is loaded into the
BR at MEMSYNC+30 ns. During any other type

to restart.

of cycle, the BR is loaded at T5+30 ns. These operWhen reading the Control Registers (PS, SL, PIR,

PIA

and

SSYN

see Chapter 2,

Paragraph

ations are independent of when T1 occurs.

2.3.2)
4.8.3.1

is generated by the processor; in this case

the 90 ns SO-S1 delay and the synchronizing flip-

Non-Cache Cycles - Refer to Figures 4-8

and 4-9. TMCF CACHE ADRS H is asserted dur-

flop delays may be concurrent.

ing all Cache cycles. RACB ROM 40 L is asserted
and TIGA PAUSE H is high during all Bus Pause

4.8.2.2

INTR Pause (T2) - Refer to Figure 4-7.

cycles

(UBSD=2

3).

When

either

CACHE

The interrupt (INTR) Pause cycle is similar to the

ADRS or PAUSE are low, gate 2 is high, TSA(I) is

Unibus Pause cycle.

gated through gate 3 and the OR gate and sets flipflop 1 one clock period later. The following TPB L,
which occurs at T1, asserts TIGA CLK BR (and
BRA) if RACA UBRK H is asserted.

The ring counter is sfopped in T2 by the UBCD
EXT BRQ H gate on the lower 74S65. This gate is

9 qrasei~E

Exi7%
<

CCBC MEM SIAEH

£ef

4(!)_«23 5

D24

TIEA T (1)
&

Zle

cus

TIGA MEM Svalc H

cdl!

RACA UBRK H

T/64 MEA SYAIC (1) #

75"3“

@ 32

TiGA ROM IMITA £ _,J

7/GA MEM SYAIC (B)
H

TIGC

7P8 ¢

7764 73() # |
T/GC

TPB W

‘% 00

7/6d

2
/50

Ctk B8R

TMEL CACLIE ADRS H

RACB

AOM 4O L
TIEA

Figure 4-8

PAUSE

11-3122

Clock BR Circuit (Part of D-CS-M8139-0-1, Sheet 3)

I1-4-11

CLK

T2
&

I
|

FLIP-FLOP #1

—

T’h

I
I

—

[
i

TIGA TS5 (1) H

——

TIGATI (NH

BR,CACHE PAUSE

e
—

e
L

TIGA MEMSYNC (W H

* NOTE:
TIGA

CCBC MEMSYNC H

Refer to figure 4-8

——

TIGA CLK BRH

STOP T1L

*CLIP-FLOP #2
11-31

n
ol

—

CLK BR, NOT CACHE PAUSE
T3

Clock BR Timing

Figure 4-9

4.8.3.2 Cache Cycles - Refer to Figures 4-8 and 49. MEMSYNC gates the data from the Cache into
the BR during a Cache DATI or DATIP. Flip-flop

ter each single bus cycle is completed (TIGA
PAUSE). When the CONT switch is pressed, TIGB
CONT is asserted and clocks the J-K flip-flop that
sets TIGA CONT (1) on the next TIGB TPB pulse

2 is set prior to the Pause cycle by T3.

Upon entering a Cache Pause cycle, gate 1 is enabled. When CCBC MEMSYNC H causes TIGA
MEMSYNC to set, the output of gate 1 goes low,
the output of the OR gate goes high, and flip-flop 1
is set at the same time as T1 (1) H (the ring counter
is restarted by TIGA MEMSYNC). Since RACA
UBRK is asserted, CLK BR is asserted 15 ns later
by TPB L, which occurs at the same time as T1.
Flip-flop 1 is on for only one clock period to ensure that only one BR clock pulse is generated.

going high. This enables the K input to the
SNGCY flip-flop so it will reset on the next TPB
pulse going high.

The processor enters T1 and proceeds through another bus cycle. As soon as T1 is entered, the flipflop controlled by the CONT switch is reset. The
CONT flip-flop resets on the next clock pulse and
the SNGCY flip-flop is again set on the trailing
edge of that clock pulse. As a result, STOP T1 is
again asserted to stop the processor after a single
bus cycle.

When the processor is halted and placed in the S
BUS CYCLE mode of operation from the console,

Since TIGA CLK BR is generated by either MEMSYNC or T5A (1), independently of T1, the data is
loaded into the BR 30 ns after TS. During Single
Cycle, the clock is stopped in TS, and the data
from the current cycle could not be displayed if the

TIGA STOP T1 and cause the processor to halt af-

restarted).

4.9
4.9.1

MAINTENANCE STOPS
Single Cycle Mode

the TIGA SNGCY flip-flop is direct-set to assert

BR were clocked by T1 (after the clock has been

11-4-12

49.2

Maintenance module switch inputs XMAA S| and

ROM+UPB

SINGLE ROM CYCLE operation (S1=0, S2=1)
stops the clock in TS of every ROM cycle.

S2 are decoded, ORed and input to the TIGB
ROM+UPB (1) H flip-flop, which is cleared by T5
(1) L and clocked by the following TPB L (at the

The UPB STOP (S1=1, S2=0) operation stops the

trailing edge of T1 (1) H). Since the CONT flipflop is cleared, the clock is stopped in T2.

clock in TS5 when PDRC PB COMP H is high. This
signal is asserted when the microprogram ROM address equals the contents of the Program Break Reg-

493

accessed at address 17 777 770.

cvele operation, either the Console CONT switch
or the maintenance stepper XMAA S4 can be used.
XMAA S4 must be used for single clock cycling.

ister [PDRC PB(07:00)]. This read/write register is

TIGB CONTL
It should be notea that, except for single clock

I1-4-13

CHAPTER 5
DATA TRANSFERS

This chapter examines the types of processor data

takes place.

transfers (Paragraph 5.1), discusses the Unibus inter-

the Pause cycle if the transaction is not to be com-

face,

general

terms

(Paragraph

5.2), -and

scribes processor data exchange with

A BEND (Bus END) cycle may replace

de-

pleted (either due to error or to the microprogram).

the Unibus

Stack and Address errors (aborts, refer to Chapter
6) are detected prior to the completion of a Bus

(Paragraph 5.3).

cycle and cause a BEND. Conditions in the microIn order to execute instructions, the processor ex-

program which can cause a BEND are those where

changes data with the Cache and with Unibus de-

Bus

vices;

which

forks or branches. If the fork or branch results in a

decides which device obtains the use of the Data

condition which does not require the Bus cycle to

contains

the

Unibus

arbitrator,

cycles

are

started

anticipation

of certain

Section of the Unibus. The Unibus arbitrator is a

be completed, it is stopped by a BEND. An ex-

part of the processor priority network, which is de-

ample of this is found on Flows 5: D12.00, D12.80

scribed in Chapter 6.

and D12.90 all do a BUST and branch to one of
three cycles; one of these, D12.70, does not require

In order to exchange data with either the Cache or
with

a Bus cycle and does a BEND.

a Unibus device, the processor must supply

the following information:

Refer to Figure 5-1. During the BUST cycle, the virtual address is generated from the BAMX; Memory

An Address, which defines the device or

Management in turn generates the physical address.

the location in memory with which the

RACH

data exchange is to take place; address

starts a CPU cycle if it is idle. During the BUST

generation is described in Section IV of

cycle, the type of transaction is determined by de-

this manual.

coding

BUST H is received by the Cache, which

the

BSC

ROM

field

(refer to

Paragraph

5.1.1).

Control information, which specifies the
direction of the data transfer; the C bits

Cache Address

determine the type of transfer and are de-

If the physical address is a Cache reference, SAPN

scribed in this chapter.

NOT CACHE ADRS is negated and TMCE CON-

TROL OK is sent to the Cache, which allows the

Data, in the case of a transfer from the

data cycle to start. The clock is stopped in TS5 and

processor to the Cache or to the Unibus;

is restarted upon receipt of the assertion of CCBC

data is supplied to the Cache by the BR

MEMSYNC H, by which the Cache indicates com-

and to the Unibus by the Data Multi-

pletion of its data cycle, i.e., data is ready on read,

plexer

or taken in on write (refer to Section VI, Cache).

(DMX),

both

of which

are de-

scribed in Chapter 2.

At TI1, the data from the Cache is strobed into the
BR (refer to Chapter 4). In the case of a read-hit

5.1

PROCESSOR DATA TRANSFERS

(i.c., the word is in the Cache and a Main Memory

The processor requires two ROM states to execute

cycle is not necessary) the clock generally does not

a data transfer; a BUST (BUs STart) cycle and a

stop, because the data is ready and MEMSYNC is

Bus Pause cycle, during which the transfer of data

asserted before T3.

I1-5-1

BUST
T1__...._...___——_————_—_._.
VIRTUAL ADDRESS

-SELECTED FROM
BAMX

—

CACHE CONTROL
BEGINS CP CYCLE
IF IDLE

T o

T2 e e e — —

BEND

PAUSE

— — — —

PHYSICAL ADDRESS

IS FORMED. ADDRESS
DECODE 1S COMPLETE.
TIMING GENERATOR
IS STOPPED FOR 90 ns

CACHE

LFDAA%Z-S?: f75

T+

—

—|— —

— —

MANAGEMENT

VIOLATION

NEXM

ADDRESS

MEMORY

ODD ADDRESS

SL ERROR

UNIBUS

CP BUSY ISSETIF

—(NPR + NPG + SACK
+ DSACK + ABORT).
ISSUE BEND TO

CACHE

INTD(1)

INTD(0)

CLEAR CP BUSY.
DISABLE SETTING
MSYN. COMPLETE
90 ns DELAY.

GENERATOR
STOPPED. DESKEW
ADDRESS AND
DATA 150 ns AND

KEEP TIMING

ASSERT MSYN

TIMEOUT

RESTART TIMING
GENERATOR.
DESKEW DATA
75 ns VIA

SYNCHRONIZER.

T3— — —

ISSUE CONTROL

—_— —_——

ISSUE BEND TO
CACHE CONTROL.

VECTOR THRU 250,
ISSUE BEND TO

ISSUE BEND TO

CACHE.

LOAD DATA TO

BUFFER. CLEAR

OK TO CACHE

B ———

ABORT CONDITION.
ZAP ROM TO 200.

ABORT CONDITION.
ZAP ROM TO 200.
VECTOR THRU 4.

MSYN. DESKEW
ADDRESS FROM

T3-T1.

WAIT FOR MEMSYNC|
IF MISS + WRITE +

PARITY ERROR

Tl — — — pr—————

LOAD DATA TO

BR IF READ
CYCLE

. — —

CLEAR.CP BUSY

CLEAR CP BUSY

IF —-DATIP, SHIFT
BUFFER TO BR

IF UNIBUS
TIMEOUT

—_—_—— -l
—_ -4

11-3134

Figure 5-1

Processor Data Transfers

I1-5-2

Unibus Address

If the physical address is a Unibus reference, SAPN
UNIBUS ADRS L and SAPN NOT CACHE
ADRS H are both asserted and the clock is
stopped for a minimum of 90 ns in T2. TMCE
CACHE BEND H is asserted and causes the Cache
to stop its CPU data cycle. Refer to Section VI.
Thirty ns after the assertion of T2, UBCA CPBSY
is set, if all NPRs have been serviced and if no

PAUSE. A Memory Management abort vectors
through address 250. A parity error abort vectors
through address 114. All other aborts vector
through address 4. (Refer to Chapter 6.)
5.1.1

Types of Data Transfers
Four types of data transfers are used by the KB11C. These types are defined by the condition of the
Control bits Cl and CO (TMCE Cl H and TMCE
COH):

abort is pending.

Cl1=0, CO=0 - Data-in or DATI. One word
of data is transferred to the processor from

SCCD INTD REG (1) L is asserted if the Unibus
address is a reference to one of the registers that
arc read on the Internal Data Bus (refer to Chapter
2, Paragraph 2.2.2). If this is the case, CPBSY is resct, MSYN is disabled, the 90 ns SO-S1 delay is
completed, the clock is restarted, and the contents
ol the register that is being referenced is clocked

memory or from the Unibus.
Cl1=0, CO=1 - Data-in, PAUSE or DATIP.
Same as DATI, but a data-out must be executed to the same address immediately following the DATIP. This type of data transfer
may

into the BR at the end of the PAUSE ROM state.

considered

the

first

part of a

read/modify/write operation.

If the Unibus reference is not to an INTD register,
a Unibus data cycle is executed. The TIG clock is
stopped and stays stopped past the 90 ns SO-S1 delay. Address, type oftransaction (C1, CO0) and, if required, data are put onto their respective Unibus
lines and deskewed. MSYN is asserted. The Unibus
device that is being addressed executes the transaction and responds by asserting SSYN. The clock is
restarted 75 ns after receipt of this signal.
At T3, MSYN is negated and the data is clocked
into the PDRJ buffer. At T1 of the next cycle, except in the case of a DATIP, the Unibus lines are
cleared by negating CPBSY. If the transaction was
a DATIP, CPBSY is not negated, the address lines
are not changed (except if the data-out is to be a
DATOB, in which case, A0O is changed from 0 to 1
for an odd byte address), the C lines are adjusted,

Cl=1, CO0=0 - Data-out or DATO. One
word of data is transferred from the processor
to memory or to the Unibus.

Cl=1, CO=1 - Data-out, byte or DATOB.
One byte of data is transferred from the processor to memory or to the Unibus. The high
order byte address is odd and its data is
stored in bits 15:08 of a word; the low order
byte address is even and its data is stored in
bits 07:00 of a word.

The CI

and CO signals are obtained by decoding

the BSC bits as shown on drawing TMCE.
1.

When

RACC

UBSCO02

negated

(low or BSC = 0 - 3) the 74S153 multi-

and the data is put on the D lines.

plexer is disabled, and both of its out-

In the case of a

CO H are low and call for a DATL

puts are low. Thus, TMCE Cl

DATI or DATIP, the data is

H and

clocked into the BR at TI.
2.

When

RACC

UBSC02

asserted

Aborts

(high or BSC = 4 - 7), the BUS COND

If an abort occurs, the microprogram forces the
ROM address to 200 (ZAP.00). This occurs at T2
of PAUSE for all aborts except parity aborts,
which ZAP at T2 of the cycle following the

multiplexer is enabled and its output is a

function

UBSCO00,

TMCE.

[1-5-3

RACC
defined

UBSCO!
by

the

table

and
on

BSC=111 - BSOP2 (BuS OPeration 2). Instruction-dependent bus transaction. If the instruction is a byte instruction, a DATOB
(data-out, byte) is executed; if it is not a byte
instruction, a DATO is executed.

The BUS CONDITION (BSC) bits of the microprogram ROM determine the type of data transfer
by its control of the C lines [TMCE CI1 (and CO)
H]. The significance of the BSC bits is defined
below:

BSC=000 - DATI (data-in), a transfer of one
word of data from a slave to the processor.
BSC=001 - SRC1 DATI (SouRCe | DATI),
a DATI used in odd address error detection
to distinguish the first bus operation of source
calculation. During a byte instruction, this
transaction cannot use an odd address if the
source mode is 3, 5 or 7. These are deferred
addressing modes and this transaction reads a
word containing the address of the operand;
this word cannot be odd.
BSC=010 - KERNEL DATI; a DATI is executed, and Memory Management selects the
KERNEL PAR/PDR set (refer to Section IV,
Memory Management) used in the Trap and
Interrupt Service routines to obtain vectored
PC and PS from Kernel PAR 0. KERNEL
DATI also affects the processor mode bits
[PS(15:12)] as explained in Chapter 3.
BSC=011 - SRC2 DATI (SouRCe 2 DATI),
a DATI used in odd error detection to distinguish the second bus operation of a source
calculation. During a byte instruction, this

5.1.2

Types of BUST Cycles

There are two types of BUST cycles: conditional
and unconditional, which are described in Chapter
1 (Paragraph 1.2.5.1).

A BUST cycle is one in which the MiSCellaneous
(MSC) bits of the microprogram ROM equal 5 or
7:

MSC=5 - CONDITIONAL BUST. This
value occurs only in IRD.00 (Flows 1), which
generates the A Fork. RACH BUST H is asserted during this cycle, except when the cycle
that follows is also a BUST cycle.

MSC=7 - 'BUST, unconditional.
5.1.3

Types of Pause Cycles

The BUS DELAY (BSD) bits of the microprogram
ROM determine the type of Pause cycle to be executed, if any. The significance of the BSD bits is defined below:
BSD=00 - No Pause.

transaction may use an odd address.

Conditions). Used during FPP Unibus transaction: TMCE CI H follows the FPP C1 line

BSD=01 - Interrupt Pause or INTR PAUSE.
The Timing Generator is stopped in T2. A
Bus Grant is issued. The Timing Generator is
restarted by INTR, NO SACK or Passive Re-

(FRMJ FP CI1 H) and CO is always negated,

lease of the Unibus.

BSC=100

(Floating

Point

Processor

since the FPP does only word operations.

BSC=101 - DATO (data-out), a transfer of

BSD=10, BSD=11 - Bus Pause. Used for Internal Data Bus (INTD), Unibus and Cache

one word of data from the processor to a

transactions:

slave.

INTD
BSC=110 - BSOP1

(BuS OPeration

The Timing

Generator

stopped in T2 for 90 ns.

1). In-

struction-dependent bus transaction, specified

operations. An O/class instruction calls for a

UNIBUS - The Timing Generator is
stopped in T2 and restarted after a minimum 90-ns delay by SSYN, Timeout or

DATO, a

TMCC ABORT.

in execute ROM cycles, common to several instructions that require different types of bus
P/class instruction for a DATIP,

and one that is neither O/ nor P/class for a
DATI.

P/class.

Instruction

instructions

are

classes

both
are

and

defined

CACHE - The Timing Generator is
stopped in TS and restarted by MEMSYNC or TMCC ABORT.

Chapter 1 and on Flows 3 and 5.

I1-5-4

5.1.4

BEND Cycle

Refer to drawing TMCE. When the ROM BCT
(Bus Control) field equals 7, TMCE ROM BEND
L is asserted. This condition is indicated by

To transmit or to receive data from
Unibus devices such as peripheral controller control registers.

“BEND" on the Flows.

To access memory via the Unibus Map
and then through the Cache; this path is
used mainly for diagnostic purposes.

TMCE CACHE BEND H causes the Cache to stop
a data cycle. It is asserted by a ROM BEND, when
the physical address does not indicate a memory reference (TMCF CACHE ADRS not asserted), by a
Memory Management abort (SSRC KT ABORT
FLG), by a fatal stack violation (TMCD SL RED)
or by an odd address error (TMCC ODD ADRS

To read (only) its control registers (PS,
SL, PIR, PIA and PB).

To receive a vector during an interrupt
transaction.

ERR).

The transactions listed in (1) and (2) above are identical, and (3) is very similar. These operations are
described in this paragraph. The interrupt transaction is explained as part of the Unibus arbitration
interface in Chapter 6, Paragraph 6.4.

TMCE KT BEND L, when asserted, prevents the
modification of the contents of some Memory Management registers and the setting of the KT
ABORT FLAG.

5.2

UNIBUS INTERFACE
The Unibus is the transmission medium that interconnects the various components of the PDP-11/70

5.3.1 Unibus Data Transfer Protocol
In order to execute a data transfer on the Unibus,
the processor must obey the Unibus protocol:

system, such as peripheral devices, the KB11-C Processor and the Cache Memory via the Unibus Map.
The principal connection between the processor and
the Cache, however, is direct and does not use the
Unibus. Main Memory can only be accessed

The processor obtains the use of the
Unibus from the Unibus priority arbitration logic (refer to Chapter 6).

The processor asserts BBSY, thus becom-

through the Cache.

The Data Section of the Unibus is used for data
transfers between a master device, which controls
the transaction, and a slave device, which responds
to the master. A master asserts BBSY (Bus Busy);
it determines the type of data transfer and is the
only device that may assert MSYN (Master SY Nc);
a slave executes the transaction requested by the
master and asserts SSYN (Slave SYNc). The pro-

ing bus master.

The processor defines the slave device
with which it wants to communicate. To
do this, the processor puts a Unibus address on the A lines [BUS A(17:00) L on

cessor is generally a master during Unibus transactions, but in the special case of interrupts, it acts as

SCCL]. Memory Management generates

a slave device.

manual).

this address (refer to Section IV of this

Only one data transfer may occur at a time on the
Unibus, and the priority arbitration logic decides
which device may use the data transfer lines on the
Unibus. (Refer to Chapter 6, Paragraph 6.3).

The processor defines the type of data
transfer to be execuuted, which is determined by the C lines (BUS CO L and
BUS ClI L on UBCC). Data transfers

5.3 WUNIBUS DATA INTERFACE
The KB11-C uses the Data Section of the Unibus

may be either from the processor to a
slave (data-out: DATO or DATOB) or
from a slave to the processor (data-in:

for the following types of data transfer:

DATI or DATIP).

I1-5-5

If the intended data transfer is a DATO
or

DATOB,

the

Il.

processor puts the

The slave typically negates SSYN upon

receipt of the negation of MSYN.

data word or byte on the Unibus D lines
[BUS D(15:00) L on PDRE]. Data selection

described

Chapter

12.

Para-

If the assertion of SSYN is not received
within a specified amount of time (Time-

graph 2.3.2.

out Delay), the instruction is aborted.

When these bits (Unibus A, C and D

5.3.2

lines) become valid, they are deskewed

The Unibus data interface is shown on drawings

Unibus Data Interface

for 150 ns to allow for decoding in the

UBCA, UBCB and

slave

and

ments the Unibus data transfer protocol.

and

receiver

for variations

bus driver

characteristics

UBCC. This interface imple-

(address

deskew).

The

description

that

follows

refers

processor

Unibus device references, which include the MemThe processor then asserts

MSY N:

ory via the Unibus Map. Processor Control Regis-

ter
a.

references

differ

some

details

from

these

Ifit is executing a DATI or a DA-

transactions. These differences are described at the

TIP, when the negation of SSYN

end of this paragraph.

from the previous Unibus transaction has been received,
b.

5.3.2.1

If it is executing a DATO or a DA-

Unibus Device References
During the BUST state, Memory Man-

TOB, 150 ns after receipt of the ne-

agement generates the Unibus address,

gation of SSYN from the previous

which

transaction.

PAUSE state.

becomes

valid

SAPN

TI1

the

UNIBUS ADRS

L., when asserted, informs the processor
The

slave

receives

the

assertion

that

MSYN and either accepts the data from

Unibus

transaction

the D lines (DATO or DATOB), or puts

asserted

the data requested by the processor on

thec PAUSE states.

the

lines

(DATI

DATIP).

required.

The Bus Condition (BSC) ROM bits are
during

the

BUST

and

during

The

slave then asserts SSYN.

During Tl

the

Unibus

and T2 of the PAUSE state,

Data

Multiplexer

(PDRE

DATI or DATIP - Upon receipt of the

DMX) selects the input to the Unibus

assertion of SSYN, the master deskews

data drivers [BUS D(15:00) L]. Refer to

the data received for a minimum of 75

Chapter 2, Paragraph 2.3.2).

ns. The master then strobes the data and

negates MSYN.,

Refer to drawing UBCA and to Figure
5-2.

9b.

SAPN

UNIBUS ADRS L enables

DATO or DATOB - The master may ne-

the gate that clocks the UBCA CPBSY

gate MSYN

flip-flop.

tion

upon

receipt of the asser-

of SSYN. The KB11-C, however,

waits 75 ns before negating MSYN.

The TIG clock is stopped in T2 of the
PAUSE state (refer to Chapter 4). TIGA

PSEUDO T3 H is asserted 30 ns after
The master waits a minimum of 75 ns after

negating

MSYN, then

T2.

removes the

address and control bits from the A and

When all NPRs have been serviced, and

C lines. The master then negates BBSY,
this signal must remain asserted during

if no abort is present, and when the previous master has negated BBSY, UBCE
CPBSY is clocked and the processor be-

the DATO or DATOB that follows the

comes master by asserting BUS BBSY

DATIP.

except in the case of a DATIP, where

I1-5-6

PHYSICAL ADDRESS

TS5

7///////

SAPN NOT CACHE ADRS H

[

SAPN UNIBUS ADRS H

p—

(' (

VIRTUAL ADDRESS

__.,._

DATI-DATIP—DATOL

—

BUST

TIGA PSEUDO T3 H

SEE
NOTE #2

SEE NOTE # | —
~

CP BUSY CLOCK H

UBCA CP BUSY H

SEE NOTE # 3

150NS

ADRS

TIGA

BR CLKH

T3 H

TIGC

SSYN

BUS

SEE NOTE #4

MSYN (1) H

UBCA

DESKEW

YBCA START BUS (1} H

|
SEE NOTE # 5—

NOTES:

Set CP BUSY if ~(NPR + NPG + SACK

CP BUSY is not cleared if DATIP cycle.

Used to start DATO address deskew on

DATIP/DATO operation.

+DSACK + ABORT + BBUSY).
4,

75 ns data deskew is obtained by 2 stage

It is cleared on DATO portion of DATIP/

synchronizer on TIGA.

DATO.

loaded into PDRH buffer register at T3.

Unibus data is

Address & control are deskewed from
T3 to T1. PDRH buffer register loaded

to BR at T1.
1-3124

Figure 5-2

Unibus Data Transfers

I1-5-7

UBCE CPBSY

[BUS

B H gates the address

At the same time (T1) CPBSY is direct-

A(17:00) on SCCL], the data

cleared and BUS BBSY L is negated, ex-

[BUS D(15:00) on PDRE] and the Con-

cept

trol

BBSY

bits

(BUS

ClI

and

BUS

UBCC), onto the Unibus.

the

case

must

of a

remain

DATIP,

asserted

when

until

the

end of the DATO or DATOB that follows the DATIP. This is controlled by

TIGA PSEUDO T3 also clocks and sets

the 74S74 flip-flop on UBCA whose D

UBCE START BUS. If the transaction

input

a DATO or a DATOB (UBCC CI B

MSYN- (1) H clocks this flip-flop, which

asserted) and SSYN is negated, the

UBCC

DATIP

UBCE

controls the direct-clear input to UBCE

150 ns address deskew is started. If the

CPBSY.

transaction is a DATI or a DATIP, the

deskew is started without regard to the

When

state of SSYN.

the address, data and control bits are re-

UBCA CPBSY

B H

is negated,

moved from the Unibus.

Upon completion of the delay, if SSYN
is negated,

BUS

MSYN

is asserted by

UBCA MSYN.
Upon receipt of the assertion of (UBCB)

BUS SSYN from the slave, and since
MSYN

being

asserted

the

Unibus Timeout - If SSYN is not received

in response to the assertion of MSYN by the pro-

cessor within 10 us a Unibus Timeout occurs.

pro-

cessor [UBCE MSYN (1) H], UBCB CP
SSYN

UBCA

START BUS and thus disables

asserted.

This

signal

clears

Refer

drawing

UBCA.

The

74193

binary counter is kept cleared by UBCA

the direct-set input to UBCA MSYN (1)

MSYN (0) H. When the MSYN flip-flop

is set, the counter is free to count up. It
is clocked by UBCD FREE CLK (0) H

UBCB CP SSYN

L also causes UBCB

(30 ns pulse every 90 ns) refer to Para-.

TIG RESTART to be asserted. This sig-

graph 6.4.1). On the 16th clock pulse, a

nal causes the clock to be restarted. T3

carry is generated which sets the UBCA

is asserted 75 ns (minimum) after TIG

START

RESTART is asserted (refer to Chapter

counter allows single clock cycle mainte-

TIMEOUT

latch.

This

4). T3 clocks the UBCA MSYN flip-flop

nance module operations when referen-

off and negates BUS MSYN.

cing Cache

registers (or the Cache via

the Unibus Map).

If the Timeout one-

If the transaction is a DATI or a DA-

shot was started immediately upon the

TIP, the data is clocked into the Bus Buf-

assertion

fer Register [PDRJ D(15:00) H] at T3.

uses the processor time pulses, could not

The 75-ns delay between the assertion of

complete

TIG RESTART and that of T3 is the re-

would always occur.

of MSYN,
the

the Cache,

transaction

and

which

Timeout

quired data deskew.

Refer

drawing

UBCB.

At Tl of the microprogram state that fol-

starts

the

timeout

74123

lows the

MS).

5.3.2.2

DATI

Pause cycle,

in the case of a

DATIP,

the

data

The

latch

one-shot

(10

from

PDRJ D(5:00) H is clocked into the BR.

If the assertion of BUS SSYN L is re-

This

ceived before the end of the 10 us, the

shown

“T6é

BR<BUS”

PAUSE on the Flows.

onc-shot is cleared.

II-5-8

If the assertion of BUS SSYN L is not

They are written directly from the BR,

received by the end of the 10 us the one-

whether they are referenced by Unibus

shot times out, UBCB TIMEOUT is set

address

and disables the direct-set gate to UBCA

Unibus cycle is performed as described

the

microprogram.

MSYN (1) H. TMCC BUS ERROR L

below when the reference is by Unibus

and TMCC ABORT H are asserted.

address.
2.

The PS can be read either via the Inter-

nal Bus (Chapter 2, Paragraph 2.2.2) or

Since the clock is stopped in T2 of the
Pause

cycle

serted),

(RACB

TMCC

UBSDOl

ABORT

via the Unibus. The SL, PIR, PIA and

as-

PB can only be read via the Unibus, and

asserts

not via the Internal Bus.

UBCB ABORT RESTART H. This signal

restarts

the

TIG

above.

The

ZAP.00,

thus ending

clock

microprogram
the data

(7)

When referenced by its Unibus address, the register

goes

to be read is selected by the DMX. Refer to Chap-

transfer

ter 2, Paragraph 2.3.2.

cycle.
The logic sequence is the same as that for Unibus
device references, with the exception that the proUBCB

TIMEOUT

sets

TMCD

cessor itself must generate SSYN.,

UBUS TIMEOUT H (bit 04 of the CPU
Error

when

TMCC

ABORT

Refer

CLK L is asserted at T3 of PAUSE. The

drawing

UBCC.

SCCE

INTERNAL

ADRS H is asserted when any one of the addresses

CPU Error Register may be read from

in the range of 17 777 770 - 17 777 776 is decoded

address 17 777 766.

Memory

Management.

These

addresses are

those of the Control Registers.

Fifty nanoseconds after UBCA MSYN (1) is as5.3.2.3

Control Register Reference - The processor

serted, BUS SSYN L (UBCC) is asserted. This sig-

Control Registers (PS, SL, PIR, PIA and PB) are

nal is received by the bus receiver on UBCB and

described in Chapter 3. They present a special case

asserts UBCB TIG

of data transfers:

the TIG clock.

I1-5-9

RESTART H, which restarts

CHAPTER 6
ABORTS, TRAPS AND INTERRUPTS

An Abort is the non-completion or interruption of
a data cycle due to error. This may be a non-recov-

6.1.1

Vectors

During all aborts, traps and interrupts a Vector is

erable error or, if Memory Management is enabled,

obtained. The vector is the address of the location

a prohibited transaction. Aborts are serviced imme-

where the PC for the required subroutine is stored.

diately, prior to the completion of the instruction

The vector+2
is the address of the location that

during which they occur.

contains the new PSW.

A Trap is an interruption of the normal program

flow by internal machine conditions. These conditions can be, but are not necessarily errors. A Trap

During an external interrupt, the vector is provided

is exccuted after the instruction during which it oc-

the device causing the interrupt, and is read
from the Unibus. Refer to Paragraph 6.4. During a

curs is completed.

power-up,

An Interrupt is similar to a Trap, but is caused by
conditions external to the machine. These condi-

logic.

it is read from the Start Vector (SV).
During all aborts, internal traps and processor PIR

interrupts,

is read

from

the Trap Vector (TV)

tions may be program action (PIR) or external device service requests (BR). Interrupts are controlled
by bits 7 - 5 of the Processor Status Word (PSW).
All

of the

Flows,

above

which

use

are

the

microprogram

described

Aborts are explained in

Refer to drawing DAPE. The SV (power-up) is generated by jumpers and is input to the ALU by the

Service

Paragraph

BMX. The jumpers may be cut to provide a SV be-

6.1.

tween 00 000 000 and 00 000 174 or between 17 173

Paragraph 6.2, traps and

200 and 17 173 374.

processor interrupts in Paragraph 6.3, and external

(Unibus) interrupts in Paragraph 6.4.

The TV
6.1

SERVICE FLOWS AND VECTORS

The microprogram Service Flows (Flows 12 and 13)
are used during all aborts, traps and interrupts.
During these cycles,

the

and

bits

[DAPE TV(01:04)

TV06 H

and

TVO05*07 H] are controlled by functions generated
on TMCB and

IRCD. The vectors generated for

‘cach function are listed on DAPE. If none of these

PS of the sub-

is asserted, the vector is 4 (TVO02).

routine that is required by the abort, trap, or interrupt are read from memory and the PC and PS of
the instruction that caused the entry into the Service Flows are pushed onto the new stack, as determined by the processor mode bits of the new PSW
[PS(15:14)].

IRCD decodes the operation code of the IOT, BPT
(OPCODE3), EMT and TRAP instructions, which
do nothing but generate an interrupt. They are
shown on Flows 3, on the A Fork.

I1-6-1

6.1.2

RSD.00 and RSD.10 generate a trap vector (TV) of

CPU Error Register

The CPU Error Register allows the program to determine which abort or trap to location 4 caused entry into the Service Flows. It contains the following

4 and

shift it left to obtain the correct vector,

which

10.

TRP.00

generates

the

correct TV.

These cycles all enter SVC.00 through TRP.10.

bits:

Bit
7

Name
lllegal Halt (trap)

Function
Set when trying to execute
a HALT instruction when
the CPU is in User or

Supervisor mode (not

In addition, ZAP.00 does a BRQ STROBE, which
allows setting the CONF after BRK.00 if the
HALT switch is down and the S BUS CYCLES

Kernel).

INST switch is in S INST.

Odd Address

Set when a program

Error (abort)

attempts to do a word

The BENO06 branch after ZAP.00 checks SSRA PS
RESTORE (1) H (Memory Management abort during SVC.70 or SVC.90). Refer to Paragraph 6.2.1.3.

reference to an odd ad-

dress.

6.1.3.2 BRK.90 and ZAP.00 - These two cycles do
a BEND, which ends any bus operation that may
have been started during the previous cycle.

Non-existent

Set when the CPU at-

Memory (abort)

tempts to read a word
from a memory location
higher than system size

6.1.3.3 BRK.00 and BRK.10 - The INTR PAUSE,
during which the vector is read from the Unibus
during an external interrupt, occurs during
BRK.00. INTR PAUSE is described in Paragraph
6.4. The PC of the instruction preceding the service
sequence is stored in the SR.

Unibus Timeout

Set when there is no

(abort)

response on the Unibus

During BRK.10, the INTR vector is moved into
the DR.

within approximately 10

6.1.3.4 Branch Enable 13 - The logic that controls
Branch Enable 13 (BENI13) is shown on TMCB.
All the errors and requests that might be honored
to cause an internal trap are ORed to provide an
output called TF (and its complement, -TF). The

microseconds.
3

Yellow Zone

Set when a yellow zone

Stack Limit (trap)

trap occurs.

Red Zone

Set when a red zone abort

Stack Limit (abort)

OCCUIS.

74H50 gates provide the following two outputs:
TMCB PF (0)*(SF+TF) H and TMCB PF (0)*(SF+TF) H. These outputs control which of four microbranch paths will be followed:

The CPU

Error Register is read on the internal
1.

data bus (INTD) at address 17 777 766.

PUPF (0) L - If the Power-up flag is set,
neither output will be asserted. Micro-

6.1.3

state PUP.00 (100) will be entered.

Service Flows

6.1.3.1
Entry into the Service Flows - Aborts and
Power-up enter the Service Flows through ZAP.00;

TF - When the Power-up and Stack Error flags are both cleared [PUPF (0) L

BRK.90. The

and -SERF (1) L] and a trap condition

EMT, TRAP and reserved operation codes (from

exists, only the TMCB PF (0)*(SF+TF)

traps and interrupts enter through

the A Fork, Flows 3) enter through RSD.00. The

H output will be asserted. This output

BPT (OP3) and IOT (also from the A Fork), and

causes

the illegal HALT, enter through TR.00.

entered.

I1-6-2

microstate

BRK.80 (140) to be

-TF - When the Power-up and Stack Error flags are both cleared and no internal

trap

conditions

are present

(-TF),

only the TMCB PF (0)*(SF+-TF) H output will be asserted. This causes micro-

SVC.60 - SVC.90 push the old PS and PC onto the
current mode stack as determined by the new PS. If
a Memory Management abort occurs during these
cycles, the PS RESTORE branch is taken after
ZAP.00. Refer to Paragraph 6.2.1.3.

state BRK.20 (120) to be entered.

SVC.90 does a BRQ STROBE. It is followed by
4,

SF - If the Stack Error flag is set and
the Power-up flag is not, SERF (1) L
will assert both outputs. This will cause
the

SER.00

microstate

(160)

FET.00.

Table 6-1 shows in detail the movement of data in
the processor registers during these cycles.

entered.

6.2
The Power-up sequence is described in Paragraph

6.5 and the INTR in Paragraph 6.4.
6.1.3.5

Red Stack Error (SER.00 and SER.10) -

ABORTS
Aborts are grouped under three headings in this

paragraph: Address, Stack and Parity. The several
errors, and their timing, are described under these
headings in this paragraph.

The PC and PS pushes in SVC.60 - SVC.80 must

be made to locations 0 and 2 of the stack. For this

6.2.1

reason, SER.00 and SER.10 set the stack pointer,

GR(6), to 4.

(TMCC AERF (1) H) to be set. An address error
may be one of the following:
B
—

After this cycle, the Red Stack Error flows rejoin
the flows for all other internal traps by entering
BRK.80.

6.1.3.6

BRK.80 and BRK.20 - During BRK.80 the

into the BR in both cycles.

The ACKN in BRK.20 clears the INTR flag.
BK.30 - This cycle is followed by SVC.00

- SVC.90, which are common to all aborts, traps

and interrupts. The ACKN in this cycle sets and
clears several functions related to the service flows.
6.1.3.8

Entry

into SVC.00 -

Odd Address error,
Non-Existent Memory error,
Memory Management abort,
(Unibus) Timeout error,

provided the bus cycle during which the error occurs is not a push to the Kernel stack.

trap vector is read into the DR. The PS is loaded

6.1.3.7

Address Errors

address error causes the Address Error flag

SVC.00 is entered

6.2.1.1 Odd Address Error - An odd address is permissible only during a byte instruction, and then
only when the transaction is a SRC1 DATI and the
source mode is not 3, 5 or 7, a SRC2 DATI, a
BSOP! or a BSOP2. TMCC ODD ADRS ERR L
is asserted when the address is odd (BAMX00=1)
and these conditions are not met. The bus cycle is
aborted and a trap to 4 is executed.

from either TRP.10 or from BRK.30. At this time,
the vector (address of the new PC, which is read
first) is in the DR, the old PC is in PCB and in the
SR, and the old PS is in the PSW and in the BR.
6.1.3.9

SVC.00 - SV.90 - During these cycles, the

reads the operand, whose address during a byte instruction may be odd.

PC and PS for the software service routine are read
from the Kernel stack

SRCI1 DATI is the first bus operation of source calculation: if the source mode is 3, 5 or 7 (all deferred modes), this transaction reads the address of
the operand, which cannot be odd. SRC2 DATI

during SVC.00 - SVC.20.

KERNEL DATI forces Kernel mode but does not
change the status bits in the PSW [PS(15:14)]. Refer to Chapter 3.

BSOP1 generates DATIP for a P/class instruction,
a DATI for an instruction that is neither P/class
nor O/class and a DATO for O/class instructions;
no byte instructions are O/class.

The new PS is loaded into the PSW during SVC.30.

a DATOB for byte instructions

SVC.40 loads the SP into the DR and SVC.50 decr-

BSOP2 generates

ements the SP.

and a DATO for all others.

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TMCD ODD ADRS ERR L is asserted under the

The SEG ABORTED flip-flop generates the Trap
vector for a Memory Management abort. This TV

following conditions:
I.

is 250 unless the bus cycle during which the error
occurs is a push to the Kernel stack; in this case,

The address is odd (BAMX00=1) and

the vector is 4 (Stack error, see Paragraph 6.2.2).

the instruction is not a byte instruction
H negated). The third

gate from the top is asserted in this case.

Refer to TMCB: TMCB SEGT L, when asserted,
generates vector 250 on DAPE. SEGT is asserted

If the address is odd and this gate is not

AERF are both asserted. AERF, however, cannot

asserted, the instruction is a byte instruction, and either the top or the bottom

be asserted when the error is a Stack error (i.e.,
when TMCC KERNEL R6 is asserted). In this last

gate can cause ODD ADRS ERR to be

case, the vector is 4 instead of 25.

(IRCD BY IN

for an abort when TMCC SEG ABORTED and
2.

asserted:

If the BSC field calls for a DATI,
a KERNEL DATI, a Floating
Point Bus Operation or a DATO

PS RESTORE
The Service Flows first fetch the new PC and PS
from the vector address; the Kernel stack is used

(BSC=0, 2, 4, or 5), the top gate is

for this operation (SVC.00 - SVC.50). The old PS
and PC are then pushed onto the new stack
(SVC.60 - SVC.90).

asserted;

If the BS field calls for a SRCI
DATI or a

DATI (BSC=0 or

Il the new stack is not the Kernel stack, and if
Memory Management is enabled and causes an
abort during the pushes in SVC.70 or SVC.90, this
abort may be a length error, which in this case is a
non-Kernel stack error. (A Red Stack error would
have occured if the Kernel stack was being used).

and a source mode of 3, 5 or 7, the

bottom gate is asserted. Note that
a DATI causes the top gate to be
asserted without regard to the
source mode.

6.2.1.2 Non-Existent Memory Error - TMCC
NEXM L is asserted when an address is neither a
Unibus nor a Cache address. This is determined by
ANDing SAPN NOT CACHE ADRS H and
SAPN UNIBUS ADRS L. Refer to Section IV of
this manual for a description of these functions.

The

ZAP.10 - ZAP.30 restore the PC and PS
of the instruction that caused entry into

The bus cycle is aborted when reference is made to
an address larger than that specified by the System
Size Register. The Trap vector is 4 for an NEXM
error.,

6.2.1.3 Memory Management Aborts - Memory
Management aborts are described in Section IV of

this manual. SSRC KT ABORT FLG L informs
the TMCC logic of such an abort condition. This
signal is inhibited when a Stack Limit Red, Odd
Address or Non-Existent Memory error is asserted
(TMCE KT BEND L). In other words, a Memory
Management abort is allowed if no Stack or Address abort is flagged.

microprogram goes to ZAP.00.
SSRA PS RESTORE (1) H has been asserted during the push cycle that causes
the abort and the microprogram
branches to ZAP.10. At this time, the
PC and PS of the instruction that caused
entry into the Service Flows are in the
SR and PCA. PCB and PSW contain the
values for the abort, trap or interrupt
that was being serviced.

the service routine. The Service Flows
are now reentered via BRK.00, BRK.10,
and BRK.80. This last cycle fetches the
trap vector, which is 250 (Memory
Management).

(1) H, except in the case of a Console operation

BRK.30 - SVC.30 get the Memory Management subroutine PC and PS. This subroutine is typically a Kernel subroutine,
and the pushes in SVC.70 and SVC.90
are then to the Kernel stack, and no er-

(UBCF CNSL ACT (0) H).

ror should occur.

KT ABORT asserts TMCC ABORT H and, at T3
of the Pause cycle, sets TMCC SEG ABORTED

I1-6-5

At the end of the Service Flows, control

within

is transferred to the Memory Manage-

aborted in this case. Refer to Chapter 5, Paragraph

ment

software

routine

subroutine.

typically

finds

the

approximately

10 us.

The

bus

cycle

This

sub-

5.3.2. The Trap vector is 4 for a Unibus Timeout

error

that

error.

caused the abort and corrects the error.

In this case, it may allocate more space

for the stack.

Unibus) cycle is flagged by CCBD CP TIMEOUT
L. This signal direct-sets PDRH CACHE PERF L,

When

software

returns

the Cache parity abort flag, and a Main Memory
timeout is processed as a fatal parity error. Refer to

tion that originally caused entry into the

Paragraph 6.2.3, Parity Errors. The Trap vector is

Service

[14 for a Main Memory timeout error.

Flows
a4

new

subroutine

Memory timeout on a processor (not a

control to the main program, the instruc-

causes

the

Main

executed

entry

into

again
the

and

Service

Flows. Since more stack space has been

6.2.1.5

allocated by the software subroutine, the

Figure 6-1. The timing diagram shows the approx-

pushes are not successfully executed.

imate time at which TMCC ABORT H is asserted
and

Timing of Address Error Aborts — Refer to

negated

the several

errors.

It should be

Refer to Section IV of this manual for a description

noted that NEXM is derived from the BAMX and

of Memory Management aborts.

is not gated: the times shown in this case indicate
the time during which NEXM is valid, i.e., during
a Pause cycle.

6.2.1.4

Timeout Error - UBCB TIMEOUT B L is

asserted when a processor Unibus cycle cannot be

TMCC ABORT asserts RACA ZAP L at TS2 of

completed

the Pause cycle (UBSDOI).

because no device responds to

BUST

MSYN

PAUSE
—
T5 T1

ZAP. 00
—————p

TS Tt

BRK. 3¢
+-—p

T5T1

SvC, 9¢g
*-—

TSTT

FET. 8¢

TS5 T

T6 T1

lIIIIIlIIIIIIIII A e
ODD ADRS

— QDD ADRS

NEXM

— NEXM

KT ABORT

TIME OUT
13

i
/>

~ TMCC AERF (1) H

SEG ABORTED (1) H

TMCC BLOCK

STROBE (1) H

77
/

[
\

TMCC

TMCC ABORT H

Wffimé‘g&”

uBCB ABORT ACKN L
3

TMCC PRIORITY CLR L

Tem

L &)

Inhibited by

BLOCK STROBE
TMCE BRQ STROBE H

RACA

ZAP L

A
Figure 6-1

1- 3126

Address Error Aborts

I11-6-6

hardware stack. These stacks are word-oriented and
the SPs can only be incremented or decremented by

TMCC AERF (1) H is set during TS2 of a Pause
cycle by any of the address error conditions, if the
reference is not to the Kernel stack (KERNEL R6
is negated) and if the bus cycle is not generated by
Console action (UBCF CNSL ACT (0) H).

The Kernel stack differs from the other two in that
it is hardware-protected.

TMCC ABORT direct-sets BLOCK STROBE and
asserts PRIORITY CLR during TS3 of the Pause
cycle. BLOCK STROBE, while asserted, inhibits
BRQ STROBE by asserting TMCC STROBE INH.

The Supervisor and. User stacks are not protected
by hardware, but may be checked by Memory Management and appropriate software. Refer to Paragraph 6.2.1.3 (PS Restore).

BLOCK STROBE and PRIORITY CLR prevent
any requests previously strobed in from generating
vectors during an INTR PAUSE. In this case, since
BLOCK STROBE is cleared by its ACKN clock input during BRK.30, the BRQ STROBE during
ZAP.00 is inhibited. TMCC PRIORITY CLR
clears the request register on TMCA. This allows
new requests to be clocked in SVC.90, and a new
brain

A stack error is one which occurs during a push to
the Kernel stack. When such a push occurs, TMCC
KERNEL R6 (1) H is asserted. If an error occurs
during this push, TMC SERF (1) H (the Stack Error flag) is set.

A stack error may be any of the address errors
listed in Paragraph 6.2.1 or a Stack Limit Red

1 to BRK.90 after FET.00.

AERF

and

BLOCK

STROBE are cleared

error.

ACKN in BRK.30.

6.2.2

The above errors all cause aborts. Stack Limit Yellow is a stack error, but traps instead of aborting.
Refer to Paragraph 6.2.2.2.

Stack Errors

A Stack is an area of memory set aside for temporary storage. Data is added to a stack (“‘pushed”
onto the stack) in sequential order and is retrieved
from the stack (“popped” from the stack) in reverse order. A stack starts at its highest address
and expands toward its lowest address as data is

Both SL YEL and SL RED vector to 4, with the exception of an SL RED that occurs during a power
fail. Refer to Paragraph 6.5.1.
6.2.2.1

Kernel R6 - TMCC KERNEL R6 (1) H is

a J-K flip-flop that is clocked at T4. It is set during

added to it.

a data-out (including DATIP) BUST cycle if the reference is to the Kernel stack. It is reset during the
Pause cycle that follows the BUST.

The address of the last valid item pushed onto the
stack is stored in a general register which is called
the Stack Pointer (SP). When an item is pushed
onto a stack, the SP is first decremented to the next
lower address, then the item is written using the SP
as the address. When an item is popped from a

The J input to the flip-flop is a 74S64 gate. All the
OR inputs to this gate must be asserted if the output of the gate is to be high (asserted).

stack. the item is read using the SP as the address,

then the SP is incremented to the next higher ad-

The second gate from the top is asserted
during a BUST cycle that calls for any
type of data transfer except a DATI.

The third gate is asserted when General
Destination Register Set 0 is addressed
(GRAC GRA3 L is asserted when GD

dress. Further details on stacks and their use are included in Chapter 9 of the PDP-11/70 Processor
Handbook.

There are three Hardware Stacks, one each for Kernel, Supervisor and User modes. The particular register (R6) for each mode is the SP for that mode’s

I1-6-7

Set 1 is addressed).

The top and bottom gates are asserted in

and can be addressed as a word at location 17 777
774, or as a byte at location 17 777 775. The regis-

two cases:

ter is accessible to the processor and Console, but

When

BAX

and

the

BAMX selects the contents of ei-

ther

the

(RACB

not

any

Unibus

device.

The

bits,

PDRC

SL(07:00), contain the stack limit information and
are compared with

BAMX(15:08). These bits are

UBAXO00 H is negated) and Gen-

cleared by System Reset, Console Start, or the RE-

eral

SET instruction. The lower 8 bits are not used. Bit

Destination Register 6

is se-

lected (GRAC GD6 L is asserted).

8 corresponds to a value of (400)s or (256).

In this case, GD register 6, Set 0,
is used as the address for a data-

Stack Limit Violations

out operation: this is a push onto

When instructions cause a stack address to exceed

the Kernel stack. During these cy-

(to go lower than) a limit set by the programmable

cles, the General Registers are ad-

Stack

dressed using the destination field

There is a Yellow Zone (grace area) of 16 words be-

Limit

Stack

Violation

occurs.

(GD[DF]}) on the Flows, and the

low the Stack Limit which provides a warning to

description

includes

the program so that corrective steps can be taken.

the sentence: “Check Stack Limit.”

Operations that cause a Yellow Zone Violation are
completed, then a bus error trap is executed. The er-

the

cycle

During a JSR, the contents of the

ror trap, which itself uses the stack, executes with-

source field register are pushed
onto the stack. This is done during

out causing an additional violation, unless the stack
has entered the Red Zone.

JSR.30 (Flows 11) where BCT = 5
(STACK

PS14

REFerence).

(0) H

asserted,

PDRD

the pro-

A Red Zone Violation is a Fatal Stack error. (Odd
stack

non-existent

stack

are

the

other

Fatal

cessor is in Kernel mode, and the

Stack errors). When detected, the operation causing

push

the crror is aborted, the SP is set to point to address 4, and a bus error occurs. The old PC and PS

is to the Kernel stack. The

74520 NAND gate is asserted, as
are the top and

bottom

gates of

are pushed into location 0 and 2, and the new PC

and PS are taken from locations 4 and 6.

the 74S64.
The K input to KERNEL R6 (1)

Stack Limit Addresses

H is TMCE PAUSES H, which is

The contents of the SL are compared to the stack

asserted

address during a push to determine if a violation

during

Bus

Pauses (BSD

has occurred.

= 2 or 3) to clear the flip-flop.

If the contents of the SL are zero:
6.2.2.2

Stack Limit Errors - The lower limit of the

Kernel stack is set by program control of the Stack

Yellow Zone = 340 - 376: execute, then trap;

Limit Register (SL). Any bus cycle that does a push
beyond

this

lower

limit

aborted

(Stack

Limit

Red Zone = 000 - 336: abort, then trap.

RED or SL RED). A warning zone of 16 words ex-

ists where any push causes a trap (Stack Limit YEL-

If the contents of the SL are greater than zero:

low or SL YEL).
Ycellow

The default boundary for stack

addresses is 400.

Zone

(SL)+(340 -

376):

execute,

then trap;

This 1s the case when the SL contains 0. The Stack
Limit Register allows this lower limit to be raised,

Red Zone =(SL)+(336): abort, then trap.

providing more address space for interrupt vectors
or other data that should not be destroyed by the

Stack Limit Yellow

program. This limit may be varied in increments of

Refer to Figure 6-2. PDRC STACK LIMIT H

4005 words,

up to a maximum virtual address of

serted when the high order eight bits of the virtual

177

modifying

400

the

content

of the

Stack

Limit Register (SL). This register contains eight bits

I1-6-8

is as-

address [BAMX(15:08)] equal the contents of the
Stack Limit Register [PDRC SL(07:00)].

When bits 7 - 5 of the virtual address are all ones,

TMCD SL RED is asserted. SL RED is a latch,

the value of bits 7 - 0 of the address is between 377

and is set by this gate at TS5 of the BUST cycle.

and 340. TMCD YEL ZONE H is asserted.
TS

is gated with KERNEL R6. This gate is dis-

Thus, when PDRC STACK LIMIT H and TMCD

abled if BLOCK STROBE and SERF are both as-

YEL ZONE are both asserted, a Yellow Zone stack

serted,

i.e.,

violation exists.

during

the

pushes

RED

cannot

and

asserted

SVC.60

again

and

SVC.80.

TMCD SL YEL (1) H is then set at T2 + 15 ns of
a Pause cycle (UBSDO1 H) that is pushing onto the

SCCE STACK OVERFLOW H is asserted if the

Kernel stack (KERNEL R6).

virtual address equals 177 776. This gate asserts SL

SL YEL is cleared by setting the SERF flip-flop

to protect the Processor Status word.

RED in the case that the SP is decremented from O

(ACKN

BRK.30);

SERF

inhibits

the

BRQ
PDRC RED ZONE H is asserted when the virtual

STROBE in SVC.90.

address is less than the SL.
Stack Limit Red

SL RED is cleared by ABORT ACKN in BRK.30.

Refer to Figure 6-2. If a Yellow Zone condition exists and the address is further decremented, TMCD

Figure 6-2

YEL

cause a Stack Limit error.

ZONE goes

low

and

the

bottom gate of

STACK LIMIT
REGISTER
=000(000)

is a

summary of the conditions that

STACK LIMIT
REGISTER
=001(000)
w

000400 |

LEGAL

grack

001376

000376
.

TMCD SL YEL (NH{

YELLOW

000340

zoNE

177776

001000
J

—

000000

SCCE STACK OVERFLOW H

PDRC STACK LIMIT H %

==~ (- TMCD YEL ZONE H

ZONE
|l¢——»

001336 ||

30—

—TMCD YEL ZONE H

2 ( TMED SLYEL () H

001340

000336
PDRC STACK LIMIT H{

| 001400

000776

M—-\

-~ )PDRC RED ZONE H
000000
|

177776

SCCE

STACK

OVERFLOW

/w‘\/

1-3125

Figure 6-2

Examples of Stack Limit

I1-6-9

6.2.2.3

Timing of Stack Error Aborts - Refer to

6.2.3

Parity Errors

Figure 6-3. The timing for stack errors is similar to

that

for

address

errors,

with

the

following

6.2.3.1

Description - A parity error may be de-

tected either by the Cache or by a Unibus device.

exceptions:

TMCC KERNEL R6 (1) H is asserted
at T4 +

Cache parity errors are either ““hard”, if bad parity

15 ns of BUST and cleared at

is detected in the word requested by the processor,

T4 + 15 ns of PAUSE.

or ‘“‘soft””, if the Cache can recover without processor intervention. Hard errors are signalled by the

KERNEL Ré6 causes TMCC SERF (1)

assertion of CCBJ PARITY ABORT H and cause

H to be set (instead of AERF).

the processor to abort; soft errors are signalled by
CCBJ PARITY TRAP H and cause a trap.

Since

SERF

STROBE

asserted,

therefore

BLOCK

PRIORITY

It should be noted that Main Memory Timeout is

CLR are asserted until TS3 of FET.00,

included in the Cache parity error logic: CCBD CP

when SERF and BLOCK STROBE are

TIMEOUT

cleared

CACHE

and

CLEAR

FLAGS

(BCT=3,

direct-sets

PERF)

that

the

stores

flip-flop

(PDRH

CCBJ

PARITY

ABORT.

TMCCQC).

BRQ STROBE is thus inhibited, not only during
ZAP.00, but also during SVC.90, thus guaranteeing

All

the execution of the first instruction of the error

abort; a device asserts BS PB L (UBCB) when it

subroutine before any other error can be processed.

senses a parity error (BUS PA is never asserted).

BUST

PAUSE

—————y

ZAP.gg

i
ADRS
SL

T5 T1

Unibus parity errors are hard and cause an

RED

NEXM

BRK. 3¢

TMCC SERF (1) H

TMCC BLOCK STROBE (1)H
UBCB ACKN B H

TS5 T4

IIIIII DL

ODD ADRS

NEXM

SL RED
KT ABORT
TIMEOUT

[y T

{TMCC) CLEAR FLAGS L

(UBCT=3 (@ T53)

3d %

(

TMCC PRIORITY CLR L

RACA ZAP L

inn

TMCC KERNEL R6 (1) H

B
o

KT ABORT
TIMEQUT

TMCC ABORT H

FET.gg

Z |
1-3127

Figure 6-3

Stack Error Aborts

11-6-10

The vector for both parity aborts and parity traps

UBCB UBUS PAR ERR H resets trap

is 114. UBCB PARITY ERR L enables the Trap

request flip-flop on CCBK (Refer to Sec-

Vector on DAPE.

tion VI, Chapter 4).

This Unibus parity error signal is ORed

6.2.3.2

with the Cache parity error signal and in-

Timing of Parity Error Aborts - Refer to

put

Figure 6-4.

UBCB

NAND gate

ABORT

is enabled

This

the 74S74

flip-flop, which is set during all cycles

Unibus Parity Error

that follow a Pause.

BUS PA L and BUS PB L are clocked
into the 74S175 flip-flop (UBCB) at T3

of a

ABORT

Unibus

Pause cycle

PAUSE, the 74S10 NAND gate is enabled by the negation of TMCE
PAUSES L. The output of the NAND
gate is asserted if PB is asserted and PA
negated (parity error), and if TMCE
PAUSEs is negated. PAUSES prevents
the assertion of the NAND gate and of
PE ABORT during the PAUSE state.

asserts

TMCC

STROBE (1)

BLOCK STROBE is cleared by UBCB
ACKN during BRK.30, which allows a
BRQ STROBE in FET.00.

SVC. 98

BRK. 30

TS5 T

TS T

T5 T1

BLOCK

cycle.

ZAP.QQ

TS T

then

H
and PRIORITY CLR L, as in other
aborts. RACA ZAP L is then asserted
by PE ABORT at TS2 of the microprogram state following the PAUSE

(MSYN ne-

gated). At T1 of the cycle following the

PAUSE

ABORT

|||III|l||IIlI|I

TS T

FET. 90
TS5 T

|I|I|l IIIIIl

PDRH CACHE PERF L

TMCC ABORT H

(UBCB) PA, PB FLIP-FLOP

UBCB PE ABORT L

TMCC BLOCK STROBE (1) H

TMCC PRIORITY CLR L

UBCB ABORT ACKN L

TMCE BRQ STROBE H

Inhibited by
BLOCK STROBE

9 A
&

RACA ZAP L

11-3128

Figure 6-4

Parity Abort

I1-6-11

Cache Parity Error

All

instructions

except SPL end

with

BENI2

branch to microaddress 240. If TMCB BRQ TRUE
1.

CCBJ

is clocked

L is asserted, BRK.90 is entered instead of a Fetch

into PDRH CACHE PERF L by TIGA

cycle, and the Service Flows are executed, followed

CLK BRA H, which occurs at T1 of the

by the subroutine determined by the new PC.

cycle

PARITY

ABORT

following

Pause.

(CCBJ

TIMEOUT direct-sets CACHE
thus

combining

the Cache

PERF,

Parity

and

Timeout errors).

6.3.1

end of a HALT instruction, if the processor is not

in
2.

lllegal Halt

A trap to 4 is executed, instead of a HALT at the

Kernel

mode,

as determined

This Cache parity error signal is ORed

mode

with the Unibus parity error signed and

branch to CON.00 is executed.

input

UBCB

NAND gate

ABORT

enabled

the

Kernel,

the Console

Flag

PSI14.

If the

is set and

This
74S74

Refer to drawing TMCE. During HLT.10 (Flows

flip-flop, which is set during all cycles

3), MSC=3, SET CONF if Kernel mode; TMCE

that follow a Pause.

SET HALT H is asserted. At TS3, if the processor
is in Kernel mode [PDRD PS14 (0) H], the Con-

ABORT

and

then

asserts

BLOCK

PRIORITY

CLR

TMCC

STROBE

(1)

sole

Flag

is set and

the processor halts. This is

shown on Flows 3 as CONF<«1 IF PS14(0).

other

aborts. RACA ZAP L is then asserted

If, on the other hand, PS14=1 (Supervisor or User

modes),

PE ABORT at TS2 of the micro-

program state following the Pause cycle.

BENO06, which examines

BR14, causes a

branch to TRPO0O. (The PS is stored in the BR during HLT.00.)

BLOCK STROBE is cleared by UBCB
ACKN during BRK.30, which allows a

6.3.2

BRQ STROBE in FET.00.

TMCA CONEF (1) H causes a processor HALT by

Console Flag

causing it to branch to CON.00 (Flows 14). Refer

6.3

TRAPS AND INTERRUPTS

to Section I (Console) of this manual.

Trap and interrupt requests are clocked into the
request storage (or Q") register on TMCA and

6.3.3

TMCB. TMCE BRQ CLK H clocks these requests

CCBJ PARITY TRAP H is asserted by the Cache

Cache Parity Trap

into the register at least once during the execution

if it detects a non-fatal parity error, i.e., one which

of each

does not affect the processor bus cycle in progress.

instruction (with the exception

BRQ CLK

of SPL).

may be inhibited by an abort which

may also clear the Q register in order to give high-

Refer to Section VI of this manual for a complete
description.

est priority to the abort (refer to Paragraph 6.2).
6.3.4

The

requests are examined

tration
only

network

the

(TMCA,

highest priority

by the priority arbi-

TMCB),

which

request to

be honored.

allows

Memory Management Traps

Refer to Section IV (Memory Management) of this
manual.

One of the signals in the Output column of Table

6.3.5

6-2 is then asserted.

Refer to Paragraph 6.2.2.

If the request is not an external interrupt (UBCD

6.3.6

EXT BRQ L) the ENB VEC flip-flop is set and en-

Refer to Paragraph 6.5,

Yellow Zone Trap (SL YEL)

Power Down Trap (PDNF)

ables the gates that generate the vector addresses
for the requests. Table 6-3 lists the requests, the

6.3.7

gates enabled and the vectors that are generated.

Refer to Floating Point Processor Manual.

I1-6-12

FP Exception Trap

Table 6-2
Processor Service in Order of Priority

Order
1

Condition
console flag

Input

Output*

UBCF STOP L

TMCA CONF (1) H

Result*
do console control
function

cache parity

CCBJ PARITY

TMCB PARTL

trap (114)

trap (250)

TRAP H

memory management

SSRD MEM MGMT

TMCB SEGT L

traps

TRAPL

TMCA HONOR SEGT H

warning stack

TMCD SL YEL

TMCA HONOR SLY H

trap (4)

UBCE PDNF (1) H

TMCA HONOR PWRF L

trap (24)

floating-point

FRHH

TMCA HONOR FPTRAP L | trap (224)

exception trap

FP EXC TRAPL

violation

5
6

power fail

CPLEV 7

priority interrupt

PDRD PIR15 (1) H

TMCA HONOR PIR7 L

trap (240)

BUSBR7 L

TMCA HONOR BR7 L

interrupt

PDRD PIR14 (1) H

TMCA HONOR PIR6 L

trap (240)

BUS BR6 L

TMCA HONOR BR6 L

interrupt

PDRD PIRI3 (1) H

TMCA HONOR PIRS L

trap (240)

BUS BRS L

TMCA HONOR BR5 L

interrupt

PDRD PIRI2 (1) H

TMCA HONOR PIR4 L

trap (240)

BUSBR4 L

TMCB HONOR BR4 L

interrupt

request PIRQ7

bus request, level 7
interrupt

CP LEV 6
9

priority interrupt
request PIRQ6

bus request, level 6
interrupt

CPLEV 5

priority interrupt
request PIRQS

bus request, level 5
interrupt

CP LEV 4
13

priority interrupt
request PIRQ4

bus request, level 4
interrupt

CPLEV 3

priority interrupt

PDRD PIRI1 (1) H | TMCB HONOR PIR3 L

trap (240)

PDRD PIR10 (1) H

TMCB HONOR PIR2 L

trap (240)

PDRD PIR09 (1) H

TMCB HONOR PIR1 L

trap (240)

TMCB HONOR T L

trap (14)

request PIRQ3

CP LEV 2

priority request
PIRQ2

CPLEV 1

priority request
PIRQI

T bit set and not RTT | PDRD PS04 (1) H
and -(IRCD RTT L)

* Only if no higher priority request has been received.

I1-6-13

Table 6-3
Trap Vectors Enabled

Trap Request Honored

Output

Trap VectorTM

TMCB PART L

UBCB PARITY ERR L

114

TMCA HONOR FPTRAP H

TMCB FPTRAP L

244

TMCA HONOR SEGT H

TMCB SEGT L

250

TMCA HONOR PWRF H

TMCB PWRF L

TMCB HONOR T H

TMCB TOK L

TMCB HONOR PIRQH
(OR of PIR (7: 1))

TMCB PIRQ L

240

* Trap vector generator is shown on drawing DAPE.

6.3.8

Program Interrupt Request

The Program Interrupt Request (PIRQ) Register allows a program to schedule the execution of various subprograms, according to a priority scheme,

at the same time allowing various levels of hardware interrupt priority to interact with the software

Refer to drawing PDRD. PIR(15:09) (1) H is
loaded from BR(15:09) when MSYN is set and if
the PIR address is decoded (SCCE PIR ADRS H).
The clock signal is TMCF CLK PIR H. The PIR
bits are encoded by the 9318, which generates
PDRD PIA(02:00).

priority levels. The register stores interrupt requests

sct by transferring request data to the PIRQ, and
provides information about the requests through en-

coded data transferred from the PIRQ.
A request is booked by setting one of the bits 15 9 (for PIR 7 - PIR 1) in the Program Interrupt Reg-

ister at location 17 777 772. The hardware sets bits
7-5 and 3-1

to the encoded value of the highest

PIR bit set. This Program Interrupt Active (PIA) is
used to set the Processor Level and also to index

Both PIR and PIA are read on the Internal Data
Bus (INTD). The PIR is read as bits 15:09, and the
PIA is repeated in bits 07:05 and 03:01. Bits 7 - 5 allow the program to move the PIA into the processor status register and thus set the processor
priority to the level of the request honored, if desired. This locks out all requests on the same level
or below. Bits 3 - 1 can be used as an index constant in dispatching to an interrupt service routine
for the appropriate priority level request.

through a table of interrupt service routines for the
scven software priority levels. Figure 6-5 shows the
layout of the PIR.

6.3.9 External Interrupt (BUS BR)
Refer to Paragraph 6.4.
6.3.10

there are no higher priorities, a trap to 14 occurs

through RSD.00.

11-3097

Figure 6-5

T Bit Trap

When the T bit is set (refer to Chapter 3), and if

Detailed information on the execution of the T bit
is contained in the PDP-11/70 Processor

Program Interrupt

trap

Request Register

Handhook.

6.4

UNIBUS

ARBITRATION

AND

INTER-

RUPT INTERFACE

When the PIR is granted, the processor traps to lo-

cation 240 and picks up the PC in 240 and the
PSW in 242. It is the interrupt service routine’s responsibility to queue requests within a priority level
and to clear the PIR bit before the interrupt is

Unibus device and memory; the processor is not involved in this transfer except to the extent that it

dismissed.

NPR

transfer

data

transfer between

cannot use the Unibus or memory during its execu-

tion. AN NPR transfer can be executed at any time
that the processor is not using the Unibus.

I1-6-14

Interrupt transactions require processor action, and can only be executed after the current instruction is completed.

A BR transfer is a data transfer during which a vector is transmitted to the processor by a Unibus device, which requires the execution of a service
routine by the processor. The vector is the address
of the PC that is to be used for this subroutine. A
BR can only be executed at the end of an

A BR may be asserted at any time that the device is ready to interrupt the processor, but

cannot be serviced until the processor is ready
to do so. BRs have lower priority than NPRs
and than a processor priority of the same

instruction.

The priority arbitration network (Paragraph 6.3) examines the requests received from the Unibus, compares their priorities against that of the processor,
and decides which device may become master when
the Unibus is released by the current master.

level (7 - 4).

Priorities permitting, the KB11-C responds to these
requests by asserting one of the following GRANT
signals:

The Unibus Request signals received by the KBI11-

NON-PROCESSOR GRANT, UBCD PROC
NPG H - unless INIT, RESET or ACLO are
asserted, or during a read/modify/write
(UBCC DATIP L), or if the Console
HALT/ENABLE switch is in HALT and the

C are listed below:
NON-PROCESSOR REQUEST, BUS NPR L

(UBCD). A signal from an asynchronous
running device requesting the use of the data
section of the bus, sent to arbitrator by a device that requires the use of the Unibus in or-

S INST/S BUS CYCLE switch is in S BUS
CYCLE. During a DATIP, no grants are issued in order to minimize NPR latency.

der to execute data transfers. These transfers
are made without active participation by the
processor. They do not affect processor operations, except to the extent that Unibus devices using the bus for a data transfer can

BUS GRANT, UBCD PROC BG7 - BG4 H if the priority arbitration network has asserted
the corresponding TMCA HONOR BR7 -

force the processor to wait in the PAUSE

BRS L.

state until all NPRs have been serviced.

Only one grant (NPG or BG) may be asserted at a

NPR transfers are executed between processor
Unibus cycles (i.e., when the processor is not

using the Unibus), and not necessarily after
completion of an instruction. NPRs may be asserted at any time that the device is ready to
start a data transfer. NPRs have a higher priority than processor data transfers or than
any of the BR lines.

BUS REQUEST, BUS BR7 L - BUS B4 L
(TMCA, TMCB); A signal from an asynchronous running device, requesting the use of
the data section of the bus. Typically, one of
these signals is sent to the arbitrator by a device that requires the use of the Unibus to
transmit an interrupt vector to the processor.

An interrupt is a transfer of control to a subprogram that handles device or task servicing.
An interrupt vector points to the address of
this subprogram; the vector is transmitted to
the processor during an interrupt (INTR)
transaction.

time.

The requesting device, upon receipt of a grant, as-

serts BUS SACK L, then negates its request. When
the assertion of SACK is sensed (UBCD), the grant
is negated. No grants may be asserted while SACK
is asserted. When the requesting device negates
SACK, a new grant may be issued.
If no device responds to a grant by asserting SACK
within 10 us, UBCD NO SACK (1) H is asserted,

forces SACK, thus allowing the assertion of a new
grant. A NO SACK timeout does not cause a trap
or abort. It should be noted that some Unibus ter-

minators (e.g., 9302), when used at the end of the
Unibus that is opposite to the processor, receive
NPR (if no device has accepted it), and assert
SACK. The Timeout delay is thus not used.
An NPG may only be used by a device for data
transfer. No interrupts are allowed on an NPG,
and the processor is not affected by an NPR
(ransaction.

I1-6-15

WAT. 20

)

BRK. 00

)

INTR PAUSE
RACBUBSD

<00:01> =1

-(BR4 + BR5 + BR6 + BR7)
BR4 + BRS + BR6 + BR7

SERVICE ALL

EXISTING NPR'S

NPR + SACK + NPG

—~{NPR + SACK + NPG)

GRANTBR <1
DISABLE NPG'S

ASSERT BUS
GRANT ON

APPROPRIATE
LEVEL

WAIT FOR BUS
SACK FROM
DEVICE

~SACK(t)

10 ps: NO SACK TIME OUT

.
1

SACKI(1)

USE NO SACK(1)
TO FORCE BUS
SACK

]

WAIT 90 ns AND

THEN CLEAR
GRANT

WAIT FOR BUS

INTR AND VECTOR

OR BUS BBSY TO
GO AWAY; SERVICE
NPR'S WHEN

—{SACK + GRANT
BR)
-BBSY

BUS INTR

RESTART TIMING
AND DESKEW

RESTART TIMING;
IF NO SACK TIME

VECTOR

OUT OR PASSIVE
RELEASE
T3

STROBE VECTOR
TO PDRH BUFFER
REG

——

CLOCK VECTOR

ENTER NEXT

ROM STATE

INTO BR
11-3136

Figure 6-6

BR -Interrupt Sequence

[1-6-16

A BG, on the other hand, is used for an interrupt.

30ns—>|

Refer to Figure 6-6. When an interrupt is sensed,
the microprogram branches to the BRK sequence
(Flows

12).

BRK.00 is the

INTR

l't—

je——90ns —+]

TIGC TF L
|

PAUSE cycle

FIRST FLIP-FLOP |

(BSD=1) in this sequence. A similar cycle,
WAT.20, is part of the WAIT instruction. The

UBCD FREE CLK (1)H

INTR PAUSE cycle is the only condition in which

LUBCD FLIP-FLOPS CLOCKED

the processor acts as a Unibus slave (i.e., asserts

1-3129

SSYN).

Figure 6-7

During the INTR PAUSE cycle, the clock is
stopped in T2 if an external interrupt is to be serviced (BR4+BR5+BR6+BR7). After all pending
NPRs have been serviced, the Bus Grant (BG) is asserted on the level corresponding to the level of the

UBCD Free Clock

negating its BR. The device that asserts SACK as-

The relationship between the FREE CLK and the
TIG timing pulses (T1-T5) and time states (TSITS5) is such that the leading or trailing edge of the
IFREE CLK and the first FREE CLK flip-flop outputs always coincide with the leading edge of T1-T5
and TSI-TS5. There is no other relationship to the

serts BBSY when the previous master negates it.

TIG clock.

request that is to be serviced.
When the requesting Unibus device receives the BG

it acknowledges this by asserting SACK and then

The processor negates the BG 90 ns after receiving

6.4.2 NPR-NPG Sequence
Refer to drawing UBCD and to Figure 6-8.

the asscrtion of SACK: typically, a device asserts
INTR and the vector just before it negates SACK.
Two parallel and generally unrelated sequences now

the Unibus. The clock is restarted at T3,

When BUS NPR L is asserted, and if
none of the disabling conditions are present, the D input to UBCD NPR (1) H
becomes high and this flip-flop is set by

the vector is strobed, and SSYN is as-

the

oceur:

The assertion of INTR is received from

first FREE CLK pulse to occur.
UBCD NPR (0) H disables the input to
UBCD GRANT BR (1) H: no BRs may
be granted while an NPR is present. The
next clock pulse, 90 ns later, sets UBCD
NPG (1) H, which asserts UBCD PROC
NPG H on the Unibus, starts the 10-us
NO SACK timeout one-shot and negates
UBCD ENAB BR H, which also dis-

serted. The Unibus device negates INTR
when it receives the assertion of SSYN.
The processor negates SSYN when it re-

ccives the negation of INTR.
The negation of SACK is received and,
after a minimum wait of 90 ns, allows
NPRs to be processed.

ables UBCD GRANT BR.

6.4.1

Unibus Arbitration Interface Logic

The Unibus arbitration interface logic is controlled
by UBCD FREE CLK which consists of the two
745112 J-K flip-flops clocked by TIGC TF L. The
FREE CLK generates a 30-ns wide pulse within a
period of 90 ns. The D flip-flops (74574S) on
UBCD usc the inverted output of this clock, while
the J-K flip-flops (74S112s) other than those that
make up the clock use the non-inverted output.
Thus. the two sets of flip-flops are clocked at the
same time. Figure 6-7 shows the output of the

When a device receives and accept this
NPG, it asserts BUS SACK L and negates BUS NPR L. The first clock pulse
to occur after receipt of these signals sets
the SACK and clears the NPR flip-flops.
The clock pulse after that sets UBCD
DSACK (1) H (delayed SACK, 90-ns deskew) and clears NPG. The only arbitration signal now asserted on the
Unibus is SACK.

FREL CLK.

I1-6-17

E
1

|
|

BUS NPR LTM

UBCD NPR (1) H

]

UBCD NPG (1}H

UBCD PROC NPG H

BUS SACK LTM

SACK F-F (1}
H

UBCD DSACK (1) H

*ASYNCHRONOUS SIGNALS FROM UNIBUS

Figure 6-8

The

device

asserts

BBSY

when

1-3130

NPR-NPG Sequence

the

Unibus is free (BBSY negated by previous master), executes its data trans-

fer(s) and negates SACK. The SACK
and DSACK flip-flops are cleared by the
first and second FREE CLK pulses after
receipt of the negation of SACK. If another NPR is pending, PROC NPG H
may be asserted 90 ns after DSACK is

serviced).

If the assertion of BUS SACK L is not

The BEN bits of the microprogram cycle, immediately preceding FET.10, always equal 12 and its
UADR field, 240. If TMCB BRQ TRUE L is not

received 10 us after UBCD NPG (1) H
is set, UBCD NO SACK (1) H is asserted. This signal forces a sequence similar to that described in (2) above. When
UBCD NPG (0) H goes high, UBCD
NO SACK (1) H is negated and the
SACK and DSACK flip-flops are

When the assertion of BUS SACK L is
received before the end of the 10 us time-

out, the 74S123 one shot is reset.

BR-BG

Release

traps (or interrupts) toward the end of every instruction. This is done by clocking all request lines into
the priority flip-flops on TMCA and TMCB
[TMCE BRQ STROBE H when RACC
UMSC(02:00)=6, at TS3]. If a Unibus request
(BUS BR7 L - BUS BR4 L) is asserted, and if its
priority is higher than that of any other request present, TMCA HONOR BRn L is asserted (n is the
same number as that of the request line being

cleared.

cleared as in (3) above.

6.4.3

—
_.___.__.'_'___.___ |-

]

Interrupt

Sequence

and

Passive

The processor checks for both internal and external

asserted (no interrupt request), the microprogram

branches to FET.10 (instruction fetch). If TMCB
BRQ TRUE L is asserted, the microprogram does
not branch, but goes to BRK.90 (Flows 12). This
cycle does a BEND to cancel the BUST in the previous cycle.

BRK .90 is now entered. If UBCD EXT BRQ H is
asserted (= any one of TMCA HONOR BR7 - R4
I. asserted) the clock stops in T2, since this is an
INTR PAUSE cycle (BSD=1) and UBCD EXT
BRQ H is asserted. Refer to drawing TMCA and
to Chapter 4, Timing Generator.

I1-6-18

Refer to UBCD and to Figure 6-9.

When all NPRs have been serviced and

when
1.

EXT BRQ

UBCD

BRQ

(1)

H to the input of

This

flip-flop

set

INTR PAUSE

Ts2

T
|
|
|
t

UBCD CLR BG (1) H

L
[

—

i
|
I

I
|

t
|

|
i

SACK F-F (1)H

UBCA PASSIVE
FLIP~-FLOP SET.

NPG MAY BE GRANTED

AT THIS TIME.

UBCB TIG RESTART H

TMCB

When the assertion of BUS SACK is received, the SACK flip-flop is set at the
first FREE CLK pulse. The next clock|

fore fetching the first instruction of the
subroutine pointed to by the vector.

PWRF+INTRF L is asserted
and BRK.20 branches to BRK.30 and
the Service Fiows (SVC.00 - SVC.90) be-

without doing an INTR. UBCA PASSIVE flags this condition: after a minimum delay of 90 ns, following the

receipi by the processor of the negation

The Unibus device now puts the vector
on the D lines, asserts INTR and ne-

input

gates SACK.

clocked by the trailing edge of UBCD

of SACK, the UBCA flip-flop, whose D

of the

negation

SACK

flip-flop;

of SACK
the

clears

second

DSACK.

BBSY,

the

and

clears,

of INTR

is clocked

CLOCK);

CLR

—

* NOT CLOCKED BY UBCD FREE CLK.
*%* ASYNCHRONOUS SIGNALS FROM UNIBUS.

=g
3

VECTOR CLOCKED INTO_T

PDRJ BUS BUFFER REG

(T3)

[

VECTOR CLOCKED
INTO

BR (T1)

11-3134

the

into

BG (1) H.

PDRJ

BRK.10 and

INTR Sequence

device

negates

PASSIVE L is asserted

clock

INTR

BRK.20

pulse clears

into

the

BR:

BUS SSYN L (UBCCO) is
also asserted by the processor at T3. The’

device

responds to the assertion of
SSYN by negating INTR. This, in turn,
causes SSYN-to be negated; thus ending”

the INTR Unibus transaction.

not

received.

TMCB

branches

RTI.60,

and

the

lowing that from which the INTR se-

The NO SACK logic is the same as that

for the NPR-NPG sequence. The nega-

followed.

clocked

was

quence (described above) was entered.

of DSACK clocks the PASSIVE
flip-flop and the sequence in (5) above is

INTRF

program resumes at the instruction fol-

serviced.

data

UBCC

PWRF + INTRF L is thus not asserted,

ENAB BR H is as-

At T1 of the next cycle (=T6 on Flows

BRK.20.

(1) H is not set in this case because BUS

D(15:00)

(BR-BUS).
Figure 6-9

(1)

BRK.00 is followed as in (4) above by

causes UBCB

tion

this

the

restarts the clock via UBCB TIG

serted, and the NPR input to NPG (n
H is enabled. An NPR can now be

12)

when

UBCA

CLR

from BUS D(15:00) L. At T4, the BRQ
flip-flop is cleared (-TS2 and FREE

2ND TIGA RESYNC F-F*

UBCD

RESTART H.

TART, T3 is asserted. At this time, the
vector

DSACK:

nal causes the main clock to be restarted
(refer to Chapter 4). A minimum of 75
ns after the assertion of TIG RES-

The above is the general case. Passive
Release is said to occur when a device

that becomes master, by asserting a BR
and obtaining a BG, releases the Unibus

TIG RESTART to be asserted. This sig-

1ST TIGA RESYNC F-FTM

TIGA T3 (1) HTM

issued [CLR BG (0) H], and DSAK (0)
H is high.
%

The assertion

(uBcC) BUS SSYN LTM
UBCC INTR B H**

The first FREE CLK pulse after receipti

UBCD DSACK (1)H

negated at this time, and the branch is
BRK.20(120). Since INTRF is set,

BG is done and no new grant has been

puts high).

H is high; this is the case when the last
NPG is done [NPG (0) H high], the last

plementing it (J-K flip-flop with both in-

}

BRK.10 is executed. TMCB PF(0)*(SF+-TF) H is asserted and TMCB PF(0)*(SF+TF) H is

H to be negated. The same clock pulse
also clears GRANT BR (1) H by com-

BUS INTR L also sets UBCC INTRF
(1) H. After BRK.00,

CLR BG (1) H, which causes ENAB BRT

}

! Y S—

is pending [NPR (0) H high]. All grant,
service has been completed if ENAB BR'

BR (1) H is high, the same pulse set

TS4

UBCD GRANT BR (1) H
UBCD PROC BGn H

T T

I
I
|

———

All NPRs have been serviced if no NPR

pulse sets DSACK (1) H. Since GRANT,]

> T3 T4TSTIT2 T3 T4 TS

UBCD ENAB BR H

H. This signal gates the

ofe- BRK. 19—

BRK: g or WAT. 2¢

——

UBCD BRQ (1) H

completed,

BGn H.

-] ———

INPUT TO UBCD BRQ (1)i \2 Y

serted onto the Unibus as UBCD PROC

BUS SACK L

BRQ (1)

UBCD FREE CLK H

service

TMCA HONOR BRn L signal that is as-

clocked by FREE CLOCK and its output goes high.

grant

GRANT BR (I) H is set by the first
FREE CLK pulse following the one that

TS2 and TMCE INTR PAUSE H gate

UBCD

all

6.5

UNIBUS POWER MONITOR
The processor monitors the condition of all power
supplies in the system.
1.

Two Unibus signals, BUS ACLO L and

BUS DCLO L, inform the processor of
the stite of thie Unibus power supplies:
The assertion of BUS ACLO L informs

11-6-19

a power supply, whose failure might
make the bus inoperable, has ceased to
be within specifications. The negation of
BUS ACLO L informs the processor
that all power supplies, whose failure
might make the bus inoperable, can
maintain dc power within specifications
long enough for a complete powerup/power-down sequence.

The assertion of BUS DCLO L informs
the procesor that dc power to any bus
drivers, receivers or terminators, whose
failure would make the system inoperable, is about to fail. The negation of
BUS DCLO L informs the processor

that dc power to all bus drivers, receivers and terminators, whose failure would
make the Unibus inoperable, is within

specifications.

Two signals from the Cache, ADML
MAIN ACLO L and MAIN DCLO L,

monitor the Main Memory power sup-

plies. These signals have the same significance and effect as the BUS ACLO and
DCLO signals, but are input only to the
processor power-up/power-fail circuits,
and not to BUS ACLO and BUS
DCLO.

These bus signals are input to the Cache,
which performs its power-up initialization sequence upon receipt of the
negation of both BUS ACLO and BUS
DCLO.

ACLO is always asserted before DCLO; DCLO is
always negated before ACLO. Whenever ACLO is
asserted, the power supplies must be capable of sup-

plying ¢nough dc power for 5 ms of system oper-

ation: this time allows for a 2-ms power-down

a power failure or power down. It can be retrieved

LIt L.

ACLO and DCLO control the power-up and

S$VC. 99

FET. g¢

5 T1 [_

S
————e
B

TIG CLOCK
STOPS

1 ittt

BUS ACLO L

power-down logic shown on drawing UBCE.

UBCE PDNF (1) H

Power-Down

Refer to UBCE and to the timing diagram shown
in Figure 6-10. When BUS ACLO L is asserted during normal operation, the Power-Down flag, UBCE
PDNF (1) H, is set, because UBCE BLOCK
DOWN (1) H has been reset at the end of the previous power-up sequence. PDNF is applied to the
priority arbitration logic on TMCE; the first BRQ
“strobe ‘generates' TMCE BRQ CLK H, which

TMCA HONOR PWRF L

UBCB ACKN B H

no higher priority flag is up (CCBJ PARITY
TRAP, Memory Management Trap or SL YEL),
TMCE HONOR PWRF L is asserted. At the end
of the current instruction, the ROM branches to
the Service Flows (BRK.90).

At microstate BRK.20, UBCB ACKN B H goes
high at TS3 and sets TMCC BLOCK STROBE (1)

TMCC BLOCK STROBE (1) H
TMCE CLK CONF H

clocks the interrupt flags into the priority logic. If

TMCC AC CLEAR L

UBCE PF CLR (1)H

UBCE BLOCK DOWN (1) H

(UBCE) 2ms ONE-SHOT

H. At microstate SVC.90, if no aborts are pending,
this signal and TMCE CLK CONF H (BRQ
STROBE at T3) generate TMCC AC CLEAR L,
which clocks the UBCE PF CLR (1) H flip-flop.
This Mip-flop is set at this time, since TMCA
HONOR PWRF L is asserted. The Q register is
cleared 1o ensure that the first instruction of the
power [ail routine is executed, in case a request of

(TMCC) CLR FLAGS L

8US DCLO L (UBCE)
UBCE PUPF (1) H

"(GENERATED BY PROCESSOR)
-2 %

2 A

—d )

3
—

K Oo—

Ry o—

K P

(UBCE) INIT L (all)

*NOTE: Power-Down subroutine exscuted during this time.

lower priority than power fail is present.

#1-3132

Figure 6-10

PF CLR does the following:

sets the TMCE priority flip-flops.

It starts the 2-ms timer which, at the end

of its delay, fires the l-us one-shot; the
pulse thus generated goes out on the

By this time, all the internal traps and service routines should have been executed; no further bus
transactions can occur, because DCLO asserts the
initializing signals:

Unibus as BUS DCLO L.

Power-Down

It asserts TMCA BRQ CLR L, which reIt resets UBCE PDNF.

sequence, plus a 2-ms power-up sequence.

During the power-down sequence, the program
stores the contents of volatile registers into core
memory: this information is thus preserved during

T5 T

tarted where it was interrupted.

6.5.1

BRK. 3¢

BRQ STROBE—;

by the power-up sequence, and the program res-

.t\)

the processor that the ac power input to

It sets UBCE BLOCK DOWN (1) H,
which disables the set input to PDNF.

UBCE INT BUS INIT L - clears internal registers PIR, SL, the priority arbitration flip-flops (TMC) and Memory
Management.

UBCE ROM INIT H - forces the ROM

to ZAP.00 (200), and stops and clears
the Timing Generator and the Cache
timing.

11-6-20

UBCE INIT - clears processor, Floating

BUS INIT L - initiaizes Unibus.

Point Processor, and Cache registers.

In addition, the DCLO generated by the processor
sets the UBCE PUPF (power-up) flip-flop, which
sets up the power-up sequence, should the DCLO
signal not be generated by the power supply, or
should ACLO be negated before DCLO is asserted
by the power supply.

SL RED During Power Fail
An SL RED abort can only occur during a push to

the Kernel stack. Two such pushes are executed during the power fail service routine, in SVC.70 and

SL RED sets SERF, which, together

As the ac power level rises, BUS DCLO L is ne-

Table 6-4

with

gated. When ac power reaches its specified level,

ACLO and DCLO Driver Outputs

HONOR

PWRF

PWREF, asserts TMCB

This signal generates the

If an SL RED error is flagged during one of these
pushes, the trap vector is 24 {(power fail) but the
pushes are made to locations 2 and O of the stack,
where no SL RED can occur (refer to Paragraph
6.2.2.4, Stack Limit Red). This allows the power

abort occurs.

TMCC PRIOCRITY CLR is not asserted
because both HONOR PWRF and SL
RED are asserted.

the assertion

The Service Flows can now be completed by doing the pushes to 2 and 0

TIG clock is started in T4 (refer to Chapter 4) and

without stack error.

are executed.

PUP. g¢g .

TS5 T1

the ROM cycles from ZAP.00 - BRK.10 to PUP.00

—

UBCE BLOCK DOWN (1) HZ

(RECEIVED FROM UNIBUS OR CACHE)

DCLO

prevents any

DC LO |

|Upper processor H7420 | P/J15-12

BUS ACLO L assertion from setting PDNF. This

DC LO 2

|Lower processor H7420 | P/J22-9

ensures that the processor will complete the power-

DC LO X

[|Lower processor H7420 | P/J22-12

in-

DC LOY

|Upper processor H7420 | P/J15-9

itiated. BLOCK DOWN is reset at the end of the

DC LOW

|Main Memory P/S

P/J6-1

2-ms delay.

DC LOW

|Main Memory P/S

P/J6-2

BLOCK

DOWN

sequence

remains set

before

another

and

power-down

specified by the start vector (SV). Refer to Para-

graph 6.1.

The processor power supply AC LO |, AC LO 2,

AC LO 3 and AC LO 4 signals are connected to
the Unibus AC LO line (BUS AC LO L) at the
backplane. This signal is the other input to the pro-

)
L,

PDP-11/70 System Power Control

Each Main Memory drawer power supply and both

cessor power-up/power-down circuits on
where it is ORed with ADML ACLO.

UBCE,

processor cabinet power supplies contain an 11086
Power Control Card. The ac power monitor circuits

(ACLO and DCLO) are on this card. ACLO and

The output of the OR, UBCE ACLO L, is also input to the Cache power-up circuits (ADMJ).

J‘-—?Oms

— bp—i }
R

)

2 -

Table 6-4 lists the processor cabinet and

)T‘Lfl_*

6.5.3.1 ACLO Connections - Refer to Figure 6-12.
The AC LOW signal from all Main Memory power
supplics are wire-ORed and transmitted to the
Cache (ADML) on the Main Memory Bus cable.
The signal is buffered, renamed (ADML ACLO H)
and is one of two inputs to the processor power-

UBCB ABORT ACKN L

{(UBCE) 2ms ONE-SHOT L

Main

Memory cabinet ACLO and DCLO signals.

*NOTE

2ms

up/power-down circuits on UBCE.

6.5.3.2 DCLO Connections - Refer to Figure 6-12.
There are two separate DCLO lines in the PDP11/70.
BUS DCLO (Unibus) and MAIN DCLO
(Main

Memory).

Two

signal

lines

required

The signal level on the Unibus O V -5
V) is different from that on the Main
Memory Bus (0 V - 3.5 V), and
The

impedance

of the

Unibus

(120

ohms) is diffecrent from that of the Main
Memory Bus (75 ohms).

®*NOTE: Power-up subroutine executed during this time.
.~ UBCE PDNF (1) H cannot be set
DC power coming up.
11- 3133

Figure 6-11

are

because:

ing Print Set for a schematic of this circuit.

output drivers on each 11086. Refer to the Engineer-

@———!

1
p

e
¥

(UBCE) INIT L (oll)z

TMCE BRQ STROBE H

UBCE PUPF (0) L initiates a 2-ms delay by trigger-

AC LO 2
AC LO 3
AC LO4
AC LOW
AC LOW

DCLO both have two independent open collector

UBCE PUPF (t) szz:

(UBCE) 70ms ONE-SHOT L

ACLOI IUpper processor H7420 | P/J15-8

ing the 74123 one-shot. For this period of time,

PUP.40) gets a new PC and PS from the location

T5 Tt

]

& Pin

serted; this clears PUPF. When PUPF is cleared,

6.5.3

Connector

The power-up microprogram sequence (PUP.00 -

RTL.6¢

BUS DCLO L (UBCE)

Unit

ACLO

%
_—

BUS ACLO L (UBCE)

Signal Nam

initializes its tag and data stores.

At T3 of PUP.00, UBCB ABORT ACKN L is as-

Power-Up

ZAP @g .

with

terval, all INIT signals are asserted and the Cache

Refer to UBCE and to Figure 6-11. When DC
power reaches a level at which the logic can operate, but before BUS DCLO L is negated, both
UBCE PUPF (1) H and UBCE BLOCK DOWN
(1) H are direct-set by DCLO. All INIT signals are
asserted by both DCLO and ACLQO. While INIT is
asserted, the ROM address is forced to 200
(ZAP.00) and the clock is cleared.

BLOCK STROBE, STROBE INH, and
HONOR PRF are asserted when the

T4 TS5

conjunction

INIT is negated at the end of the 70-ms delay, the

6.5.2

“

Since SERF is asserted, SER.00 is entered instead of BRK.80. SER.00 and
SER.10 set the Kernel SP to 4.

fail subroutine to proceed.

and,

PUPF (1) H, starts the 70-ms timer. During this in-

SVC.90.

BUS ACLO L is negated, UBCE ACLO L goes
high

power-fail vector (24).

Power-Up

I1-6-21

LSS

o iow

—CMOm SOt

fio:r?

I o o Low L | 2

:; A
P::;E:t:s:;g&' B2] = i MEM
|

T =
C

E'D

[

Frocesson

—

ACLO4

orocesson

onen soprer

]
|81

—40c Lo x

|cimcurrs | |

bcloy SHeusocloL

ACLO 2

:l BUS AGLO L

[ilwamoaor

FOIFT

aow e

b1252 i

2 |

porze

:lJ]eBC;l)srocessor power-up/power-down circuits on
:

H7420) and both DC LOW outputs from all Main

UBCE ACLOL

srzxz bovzLs

:D::D

MAIN DCLO is the wire-OR of DC LO 1 (upper

processor H7420), DC LO 2 (lower processor

berem

|aows wan UamgLE'

o M
T

Memory

TM1
TTMMC
|ue|35
'

}

_ '

1 | | - —1 |
!

[ T! | R -! l|

B44F1

devices on the Unibus. It is one of two inputs to

—_——t |

r——T—=—1T7T"
UBCE
|
MB136

BACKP|

FeIF2

[ eus ocro

BACKPLANE

wawocioL

——————
.

[s]—Jocioe

(34110086 IN 'l'o"
LOWER 7420)

}:—’{::‘s".::foi

(sanose N |9]

—P::T,E%flw

PROCESSOR

% soro

UPPER T420) 7;_\

processor H7420) and the DCLO signals from all

i “,f"fi:c"'(fi“i :
uP CIRCUIT |

| MOTH Meve _L. i

PROCESSOR
., HARRESS
To0s!

Maras

|M%h:'3

aacxeanel MeTh Moo

BUS DCLO L is the wire-OR of DC LO Y (upper

processor H7420 power supply), DC LO X (lower

P EAE Fe——————— T -I

'—“G

I |
I
L________________j |R

UNIBUS

BUS ACLO L

BUS DCLO L

drawers

(via

the

Main

Memory

named (ADML MAIN DCLO H), and is the sec.
ond input to the processor power-up/power-down
.

tercor;nec;tion;uar% suclcll tlfat a power failure So.m
any device nibus device, processor or Main
1.

Causes the processor to trap to location

24 and to perform the power-down subroutine, and

Causes
the Cache to prevent allR access to
R
Main Memory when DCLO is asserted

at the end of the 2-ms power-down sub-

BUS DCLO and MAIN DCLO are ORed (UBCE)

routine time allotment.

In addition, when the power failure is a processor

and input to both the Cache power-up and to the

. . MAIN
processor power-up/power-down circuits.

or a Main Memory failure, the Main Memory

DCLO, however,. is .the . only input to the
Main
.
.
.

Memory protection circuitry (MCTH). This circui-

LOW
is asserted by either. the processor or the
.
Main Memory power supplies.

raceves: Mansor Secnon - Craprer 6. T 0 en-e

2. Connector J4 connscis Main Memory Bus coble to J3 on
K8148 of naxt mamory frame.

1- 40800

Figure 6-12

6.5.3.3 Power Down - In the PDP-11/70, these in-

NOTES:

FI2€2

down 3 us after receipt of DCLO.

Bus

cable). MAIN DCLO is buffered in the Cache, recircuits.

try inhibits the memory write operations on power

PDP-11/70 ACLO and DCLO Connections

I1-6-22

pro-

. circuits
. . are activated
.
PDC
tection
when MAIN

SECTION 111

CONSOLE

Unless otherwise indicated, references within this section pertain to this section only.

CONSOLE

SECTION III

CONTENTS
Page

CHAPTER 1

SWITCHES, INDICATORS AND OPERATION

1.1

OPERATIONAL SWITCHES

. . . . . . . .

1.1.1

Power and Lamp Test Switches

1.1.2

LOADADRS Switch

1.1.3

EXAMSwitch

1.14

DEPSwitch

. . . . . . . o o i

. . . . . o

e e et e e e II1-1-1

. . . . ... ... ... ... ... .. ... ... I-1-1

e e e

e e I-1-1

e e

e I-1-1

. . . . . . . e
e
e e I11-1-1

1.1.5

Step Operations

1.1.6

CONT Switch

. . . . . . . . oL

1.1.7

ENABLE/HALT Switch

1.1.8

SINST/SBUSCYCLE Switch

1.1.9

START Switch

1.1.10

Switch Register

. . . . . o o

e e

. . . . . . . . .

. . . . . . .

. . . . . . . . .

ADDRESSING AND DATADISPLAY

12.1

ADDRESS SELECT Switch

1.2.2

ADDRESS Display Indicators
DATASELECT Switch

1.24

DATA Display Indicators

i i i ittt

. .

. . . . . . .

e e e III-1-3

e e I11-1-3
e e s e e e 1-1-3

e e
e

e I11-1-3
e 111-1-3

e 1-1-3

. . . . .. ... ... e I11-14

. . . . . . . . ..

. . . . . ... .. ...

. . . . . . . o v i v i

. . . . . . o o

. . . . . . . . . . 0

i i i i i it

. . . . . .. .. ..

e e

e e 111-14
e

e I11-1-4

e e e e e e

e e e

e e e I11-1-4

et et e

e I11-14

e 11I-1-4

133

RUN Indicator

. . . . . . . . . @

134

PAUSE Indicator

. . . . . . . .

o i i i

1.3.5

MASTER Indicator

1.3.6

KERNEL, SUPER, USER, Indicators

. . . ... ... ... ... ......... I11-1-4

1.3.7

ADDRESSING (Mapping) Indicators

. . . . . .. ... ... ... ... ..., II1-1-5

138
14

14.1

. . .

. . . . . . . . .

14.1.1

Unmapped Reference

14.1.2

Mapped Reference

14.2

e e

e II1-1-4

e e

. . . . . . . . . . .
e

Memory Reference

i
it i

General Register Reference

i i

e e

e e e

. i

e II1-1-5
e II-1-5

e e

. . . . ... ... .. ...

e e

e I-1-5

.. .

.. I11-1-5

. . . . . . . . . . . . e I1-1-5

. . . . . ... .. .. .. ... .. . .

CHAPTER 2

LOGIC DESCRIPTION

2.1

2.2

POWER CONNECTOR J4 (KNLA)
. . . . . . . .
POWER SWITCHS31 (KNLA)
. . . . . it i et

2.3

S1 —822: SWITCHREGISTER

S24 — S30 (“LOAD ADRS” — “STARTTM)

2.5

CONSOLEBRANCH

2.5.1

IdleState

. . . . ... ...

0oL, III-1-6

it i et i
e e e e e e e e e e

. . . . . .

. . . . . . .

e e 1-2-1

e e

us 11-2-1

i it 1-2-1

ittt i it I1-2-1

e e

e I11-2-2

. . . . . . . . . e
e
e I11-2-2

2.5.2

LOADADRS

2.5.3

RACK BRCAB(02:00)L

254

START and CONT

2.5.5

EXAM and DEP Switches

2.6

e e e I11-14

. . . . . . . . . o e 1I1-1-4

DATA (Space) Indicator
USAGE

i i

ittt

. e II-1-4

PARITY Indicators

ADRS ERR Indicator

e I1-1-1
e

i i ittt 1I-1-3

EXECUTION INDICATORS
PARERR Indicator

1.2.5

1.3.2

e e e

e e

1.3
1.3.1

i it i

. . . . . . .. . . .

1.2.3

e e e

. . . . . . . . . . .

1.2

... .. ......
.. ..... e

Single Instruction

2.6.2

Continue

2.6.3

Single BusCycle

. . . . . . . . . .. .

264

Console Reset

. . . . .. . o o

e e

e II1-2-2

e
i

. . . . . . . o i i i i i

e
e

e e e

e e e e

e
e

e e I11-2-2

e 11-2-2

. . ... ... ... . ...

. . . . . . . .. ...

. . . . . o o i i i i

e e

i ettt 11-2-2

. . . . . . . . .

ENABLE/HALT SWITCHIN HALTPOSITION

2.6.1

e e e e e

. . . . . . . .

..., 11-2-3
e I11-2-3

e 11-24

e I11-2-4

CONTENTS (Cont)
Page

2.7

ENABLE/HALT SWITCHIN ENABLEPOSITION

2.7.1

CONtNUE

2.7.2

Single BusCycle

2.7.3

. . . v

Comsole Start

vttt e e

. .. .. ............... I11-2-4

I11-2-4

. . . . . . . .. ..

LOAD ADDRESS

EXAM AND DEP OPERATIONS

2.10

ADDRESS DISPLAY

2.10.2

. . . . . ... . . . . ..

2.8

2.10.1

. . . . .

Memory Address

e I11-2-4

. . . . . . . . .

. . . .

General Register (GR) Address

e I111-2-4

e I11-2-5

e e e 1-2-5

e
e
e e e e
e I11-2-5
. . . . . . . . .. . .. i i i i ittt 111-2-5

. . . . . . . . ...
e
e I11-2-5

2.11

DATA DISPLAY

2.12

MISCELLANEOUS INDICATORLOGIC

. . . . .

e I11-2-6

. . ... ... .. . ittt I11-2-6

ILLUSTRATIONS

Figure No.

Title

1-1

PDP-11/70 Console

2-1

Step Branch Address Modification

. . . . . . . 0 i i i

Page
e e e

. ... ... ... ... ..... . ...

I11-1-2
. ..... I11-2-3

TABLES

Table No.

Title

I1-1

General Register Addresses

2-1

Address Display

Page

. . . . . . . . . . 0 i i it
e
e e
e I1I-1-6
. . . . . . . . .
e I1-2-5

Il-iv

INTRODUCTION

ccute

The PDP-11/70 Console, drawing D-CS-54-11294-

Memory cycles. The contents of any memory loca-

single

instructions

single

Unibus

0-1, allows direct control of the KB11-C computer

tion or of any register can be examined, and data

system. The Console is used for starting, stopping,

can be entered manually from the switches.

resetting and debugging. Its power switch may be
used as the master switch for a system. Indicator

Chapter | describes the various components of the

lights and the other switches provide facilities for

Console and their use; Chapter 2 describes the logic

monitoring, system control and maintenance oper-

that controls Console operations.

ations, during which the KB11-C can be made to ex-

II-1-1

CHAPTER 1

SWITCHES, INDICATORS AND OPERATION

The ADDRESS display shows either a virtual or a
physical address, as determined by the ADDRESS
SELECT switch. Refer to Paragraph 1.2.1.

Refer to Figure 1-1.

1.1

OPERATIONAL SWITCHES

1.1.4

1.1.1
Power and Lamp Test Switches
The POWER switch is a three-position, key-oper-

DEP Switch

The DEP(osit) switch is a momentary action
switch. When it is raised, the contents of bits 15 00 of the Switch Register are written into the location specified by the physical address generated by
the last LOAD ADRS operation. The data written
is shown by the DATA indicators if the DATA SELECT switch is in the DATA PATHS position.

ated switch.

OFF - Causes power to be removed from the
switched outlets of the Power Controller. Renders the system inoperative.
POWER - Power is applied to the system. All
switches are operational.

The ADDRESS display shows either a virtual or a
physical address, as determined by the ADDRESS
SELECT switch. Refer to Paragraph 1.2.1.

LOCK - Same as POWER, except that the
LOAD ADRS, EXAM, DEP, CONT, ENABLE/HALT, S INST/S BUS CYCLE and
START switches are disabled. All other

1.1.5

Step Operations

If several consecutive EXAM operations are performed, the address is incremented by 2 for each operation after the first one. Thus, it is possible to
examine a series of consecutive word addresses with-

switches are operational.

The LAMP TEST switch is the white switch between Switch Register 0 and LOAD ADRS. When
raised, it turns all the indicators on. It is used for

out doing a LOAD ADRS for each EXAM.

maintenance.

In the same manner, it is possible to execute a
series of DEP operations without doing a LOAD

1.1.2

ADRS for each one.

LOAD ADRS Switch

The LOAD ADRS switch is a momentary action
switch. When this switch is depressed, bits 21 - 16
of the Switch Register are loaded into SCCK
SWR(21:16) B (1) H, and bits 15 - 00 into the PCA
and the SR. The address displayed in the ADDRESS display indicators is a function of the ADDRESS SELECT switch (Paragraph 1.2.1 below).
1.1.3

EXAM Switch

The EXAM(ine) switch is a momentary action
switch. When it is depressed, the contents of the location specified by the ADDRESS display is shown
by the DATA indicators, if the DATA SELECT
switch is in the DATA PATHS position.

The following sequence illustrates these operations:
Operation

Location Shown in

(Activate Switch)

ADDRESS Display

LOAD ADRS

EXAM
DEP
EXAM
EXAM

X
X
X
X+2

DEP
EXAM

X 42
X+2

(Result is EXAM - STEP)

I1-1-1

[1-1-2

2In31q i-1 OL/1 -d d srosuo)

aL-cLeL

1.1.6
The

CONT Switch
CONT(inue)

switch

momentary

the

DATA

SELECT

switch

ting

BUS REG (Bus Register), the DA

action

rlay

switch whose action depends upon the position of

lights, on a read operation, will contain the

the HALT/ENABLE switch:

data that was read (this could be an instruction or data).

During a write operation, the

lights will contain the data just written (except

the point where it was stopped by the HALT

during a stack operation or Floating Point in-

switch or by a HALT instruction.

struction).

ENABLE -

Resumes

program

execution

LOAD ADRS,

are disabled in this mode.

HALT -

Used

conjunction

with

the

EXAM and DEP

If an

EXAM

DEP operation is desired, the S INST/S BUS

INST/S BUS CYCLE switch. See Paragraph

CYCLE switch should be changed to S INST

1.1.8.

and

the CONT switch

should

be depressed

once. (This will cause execution until the end

The

CONT

switch

has

the

same

effect

of the current

the

instruction).

The system

will

then be ready to perform an EXAM or DEP.

Maintenance Module Stepper Switch, XMAA $4,
when executing single ROM cycles or UPB stops,

but not when executing single clock cycles.

The

switch

has

effect

when

the

HALT/ENABLE switch is set to ENABLE.

1.1.7

ENABLE/HALT Switch

The

ENABLE/HALT

switch

1.1.9

two-position

START Switch

The START switch is a momentary action switch
whose

switch:

action

depends

upon

the

setting

the

HALT/ENABLE switch:
ENABLE

Used

conjunction

with

the

START or CONT switches, allows program

ENABLE - Starts program execution at the

execution.

address previously loaded by a LOAD ADRS,
after resetting the system (INIT).

HALT - Stops program execution,
HALT - Resets the system,

1.1.8

S INST/S BUS CYCLE Switch

The S(ingle)

switch

The START switch

INST(ruction)/S(ingle) BUS CYCLE

used

conjunction

with

the

has no effect when the pro-

cessor is in the RUN state.

CONT

switch when the HALT/ENABLE switch is in the

1.1.10

HALT position:

The Switch Register consists of the 22 switches la-

Switch Register

beled 0 through 21. These numbers correspond to

S INST - When CONT is depressed, a single

the bit positions of their respective switches. The

instruction is executed and the processor stops

Switch Register is used to manually enter both ad-

in CON.00. EXAM and DEP operations may

dresses and data into the KB11-C, and its bits, 15 -

then be executed. The contents of the DATA

00, may be rcad under program control; its address

Display indicators may only be determined by

is 17 777 570, which is the same as that of the Dis-

examination of the microprogram Flows for

play Register.

the instruction that has just been executed.
1.2

ADDRESSING AND DATA DISPLAY

S BUS CYCLE - When CONT is depressed,
execution

resumed

but

stops

TS5

1.2.1

ADDRESS SELECT Switch

PAUSE of the first Unibus or Memory cycle

The ADDRESS SELECT switch is an eight-posi-

to be executed.

tion rotary switch:

The ADDRESS display then contains the ad-

VIRTUAL

dress of the location at which the bus cycle

PER and USER [ space and KERNEL, SU-

Six

positions;

KERNEL,

SU-

was performed (virtual or physical, depending

PER

on the position of the ADDRESS SELECT

displayed is a 16-bit virtual address; bits 21 -

switch).

16 arc always off.

I1-1-3

and

USER

space.

The

address

During Console DEP or EXAM operations,

1.2.4

bits 15:00 of the Switch Register are consid-

The

ered to be a Virtual Address. If Memory Man-

Data Display Multiplexer. The output of the multi-

agement

plexer is selected by the DATA SELECT switch.

is enabled,

this Virtual

Address is

relocated. The set of PAR/PDRs indicated by

DATA Display Indicators
DATA

indicators display the output of the

Refer to Paragraph 1.2.3.

the switch position is used.
CONS PHY - (Console Physical). The 22-bit

1.2.5

address entered

The PARITY indicators display the parity bits asso-

LOAD

ADRS

is the

PARITY Indicators

physical address of the Console operation.

ciated with the HIGH and LOW bytes of the word

PROG PHY - (Program

during a write operation.

read from Cache Memory. These indicators are off
Physical).

Displays

the 22-bit physical address generated by Memory

Management for the current Unibus or

1.3

Memory cycle.
The

ADDRESS

SELECT

switch

indicator

EXECUTION INDICATORS

1.3.1

lights

PAR ERR Indicator

The PAR(ity) ERR(or) indicator is on when a Un-

are driven directly by the switch.

itbus or a memory parity error is flagged.

Refer to Paragraph

1.4 which explains the use of

the ADDRESS SELECT switch.

1.3.2
1.2.2

ADDRESS Display Indicators

ADRS ERR Indicator

The ADRS (Address) ERR (Error) indicator is on

The ADDRESS display indicators show the address

when

of the data deposited or being examined. The ad-

are: non-existent memory, access control violation,

dress is interpreted as a virtual or physical address

page length error, Stack Limit Red, odd address er-

addressing error occurs.

in accordance with the position of the ADDRESS

ror and

Unibus Timeout.

SELECT switch. (Paragraph 1.2.1 below).

dication

address

This

errors

Address errors

is a dynamic in-

that

occur

during

program cxecution. It is a static indication during

1.2.3
The

DATA SELECT Switch
DATA

SELECT

Console functions (i.e., EXAM or DEP).

switch

four-position

rotary switch:

1.3.3

RUN Indicator

The RUN indicator is on when the processor is exDATA

PATHS - Displays the output of the

Shifter. This position is the normal

display

mode, and is used to show the data examined

ecuting instructions, but is off during Pause cycles.
The

RUN

indicator

during

WAIT

instruction.

or deposited by Console operations.

1.3.4
BUS REG - Displays the output of the Bus
Register (BR).

PAUSE Indicator

The PAUSE indicator is on during all Bus Pause
and Interrupt Pause cycles, indicating that the processor 1s waiting for either Memory or a Unibus

uADRS FPP/CPU - Bits 15 - 08 display the
current

address

of the

Floating

Point

device.

Pro-

1.3.5

cessor microprogram ROM,

MASTER Indicator

The MASTER indicator is on either when the pro-

Bits 07 - 00 display the current address of the

cessor 1s Unibus master (UBCA CPBSY) or during

processor microprogram ROM.

Console operations [TMCA CONF (1) L asserted].

DISPLAY

Displays

the con-

1.3.6

KERNEL, SUPER, USER, Indicators

tents of the Light Register. The LR may be

The KERNEL, SUPER and USER indicators show

written

into

570,

the actual mode in which the processor is operating

which

Switch

during each cycle. Refer to Section IV of this man-

the

using

same

address
that

777

of the

ual (Memory Management).

I11-1-4

1.3.7 ADDRESSING (Mapping) Indicators
The 16-, 18-, and 22-bit indicators show the Memory Management mapping that is being used during

1.4.1.2

Mapped Reference

Set the ADDRESS SELECT switch to
one of the virtual positions (refer to Par-

each cycle.

agraph 1.2.1).

1.3.8 DATA (Space) Indicator
The DATA indicator shows whether I or D space
is used during each cycle. It is on when D space is

Enter the 16-bit virtual address into the
Switch Register.

used and off when I space is used.
Depress the LOAD ADRS switch. The
1.4

virtual

USAGE

address

shown

the

AD-

DRESS display. Bits 21 - 16 are off.

1.4.1
Memory Reference
Memory references from the Console may be either
mapped (i.e., using a virtual address) or unmapped
(using a physical address), when Memory Management is enabled. Mapped references are possible
only when Memory Management is enabled.

1.4.1.1
1.

Set

Unmapped Reference

SELECT

switch

address

loaded

the

LOAD

ADRS operation is relocated by Memory Management. Memory Management

Set the ADDRESS SELECT switch to

(if it is enabled) uses the mapping shown
by the ADDRESSING indicators (Para-

graph 1.3.8) and the PAR/PDR pair is

Enter the 22-bit physical address into the

selected

Switch Register.

DATA

If the EXAM switch is depressed, the vir-

tual

CONS PHYS.

the

DATA PATHS.

the

ADDRESS

SELECT

switch. The contents of this address are

read

Depress the LOAD ADRS switch. The
physical address in shown by the AD-

and

displayed

the

DATA

indicators.

DRESS display.
5b.

Set

the

DATA

SELECT

switch

DATA PATHS.

If the DEP switch is raised, the virtual

address is relocated as in the EXAM operation. The contents of the Switch Reg-

ister

5a.

If the EXAM switch is depressed, the
contents of the physical memory location entered by the LOAD ADRS operation is displayed by the DATA

are

written

into

the

physical

memory location pointed to by the physical address. The new contents of this location

are

displayed

the

DATA

indicators.

5b.

the

ADDRESS

SELECT

switch

If the DEP switch is raised, the contents
of bits 15 = 00 of the Switch Register are

now turned to PROG PHY, the physical

written into the physical memory loca-

address corresponding to the virtual ad-

tion entered by the LOAD ADRS oper-

dress used during the EXAM or DEP op-

ation.. This same data is displayed by
the DATA indicators.

eration

I11-1-5

is displayed by the ADDRESS

indicators.

1.4.2

General Register Reference

Table 1-1

EXAM and DEP references to the processor Gen-

General Register Addresses

eral Registers may be executed by entering the address

of the

(see Table

1-1)

into

the

SET
0

SWITCH REGISTER, depressing LOAD ADRS,

and then EXAM or DEP, as required. The AD-

17 777 700

DRESS SELECT switch setting is ignored; mapping to a General Register is not possible.

DEP-STEP operations can be

17 777 705
17 777 707

performed on the General Registers, in a manner

Program Counter

17 777 707

EXAM-STEP and

similar to that for memory locations, except that:

ADDRESS display is incremented by |
(instead of 2).

SET 1

17 777 710
.

The STEP after address 17 777 717 is 17

17 777 715

777

17 777 716

17 777 717

700,

such

that

the

addresses

are

looped.
3.

It is not possible to STEP up to the first
General Register (17 777 700) from 17
777 676.

IT1-1-6,

CHAPTER 2
LOGIC DESCRIPTION

The Console assembly consists of a printed circuit
board,

drawing

KNLD),

D-CS-5411294-0-1

indicator

panel,

(KNLA

drawing

D-IA-

switched outlets of the controller. When the pins
are connected,

power

is applied to

these outlets.

GND IN and GND OUT are not connected when

7413126-0-0, and a bezel, E-1A-7409306-0-0. This as-

the power switch is in the OFF position; they are

sembly is mounted on the front of the processor

connected when the switch is in the ON (terminals

mounting box. It is connected to the PDP-11/70 by

9 and

the power harness, whose Pl

and 12).

plug connects to the

10) or in the LOCK positions (terminals 11

Console J4 connector, and by three flat ribbon cables. One of these connects J1 on the Console to J1

S24 - S30 (KNLC) use the KNLA SWITCHED

on the M8134 module (PDRH). Another connects

GROUND

ground

the Console to JI

the

M8140 module

from

the

connection

power

the

switch;

LOCK

there

position,

no
and

(SCCJ). The third cable connects J3 on the Console

these

to J2 on the M8140.

KNLA PNL LOCK L is also generated in this posi-

This

chapter

describes

the Console

Power

that

the

Con-

switches

are

then

disabled.

addition,

tion, and forces the HALT/ENABLE switch output to the ENABLE logic value (low). Thus, when

Console

the power switch is in the LOCK position, the pro-

Switches (Paragraphs 2.2 through 2.9) and the Dis-

cessor is enabled, the HALT switch is inoperative,

plays (Paragraphs 2.10 through 2.12), in that order.

and the other switches are disabled, since they can-

2.1

SWITCHED GROUND is connected to GND B

nector

and

the

logic

controls

not be used when the KB11-C is running. KNLA

POWER CONNECTOR J4 (KNLA)

J4 connects to the Power Harness. It consists of the

when S31

is in the OFF position (terminals 2 and

following

the ON

lines:

VA,

which

powers

the

light

and

position

(terminals 4 and

5).

emitting diode (LED) indicators: GND A which is

KNLA PNL LOCK H is brought out to the KB11-

the

C backplane by the SCC module, but is not used
by any other part of the processor.

return

for the

ILAMP TEST

LAMP TEST switch

(KNLD

L); and with the Power Controller

GND IN and GND OUT (refer to Paragraph 2.2).
2.3

S1 - 822: SWITCH REGISTER

2.2

POWER SWITCH S31 (KNLA)

The Switch Register, S1 - S22 [KNLC SWR(21:00)

The

Power Switch

H].

controls

power to the system

transmitted

from

KNLC

to J2

of the

becomes

SCCJ

through the GND OUT/GND IN connections to

M8140

the Power Controller, and enables/disables switches

SWR(21:00) H. It is read by the processor on the

S24 - 830 (LOAD ADRS, EXAM, DEP, CONT,

Internal Bus from the multiplexer on SCCH.

ENABLE/HALT,

INST/S

BUS

CYCLE

module

(SCCJ),

where it

and

START).

2.4

S24 - S30 (“LOAD ADRS” - “START”)

S24 - S30 are input to latches (KNLC) for bounce
Power Controller = Pins 3 and 4 of J4, GND IN

suppression and transmitted from J3 of the Console

and GND OUT go to the Power Controller by way

to J2 of SCCJ (SCCJ CONT SW H - SCCJ HALT

of the power harness. When there is no connection

SW H). CONT, SINGLE CYCLE, LOAD ADRS,

between these two pins, power is removed from the

START and HALT are buffered on SCCJ.

I11-2-1

SCCJ

EXAM

SW H and DEP SW H are gated

2.5.3

RACK BRCAB(02:00) L

with SCCF GEN RG (1) H and (0) H to generate

These bits determine the branch required by the

SCCF REG EXAM H and REG DEP H when a

cight. remaining

General Register address has been decoded during

EXAM,

EXAM/DEP and REG EXAM/DEP STEP. The

LOAD

ADRS

operation.

When

any

address

other than a General Register address is detected,

DEP,

functions:

START,

CONT,

STEP EXAM, STEP DEP,

REG

bits are shown on UBCH.

SCCF GEN REG (0) H is high and SCCF EXAM
H or DEP H are generated.

2.5.4

The signals derived from S24 - S30, with the excep-

START and CONT

START and CONT are encoded on UBCH. Since

tion of ENABLE/HALT (S28), clock the flip-flop

BCE CNSLO7 (0) H is high (LOAD ADRS is not

shown on UBCF. When any of these switches is ac-

depressed),

tuated, and if the Console Flag is asserted, UBCF

START and 7 for CONT. Since the processor is in

CNSL ACT is set at TS3.

the idle state, RACK

UBCH

CNSL(02:00)

equals

for

BRCAB(02:00) L force the

next cycle microaddress respectively to 076 or 077.
These

flip-flops

(CNSL

are

ACKN),

reset

when

BCT=2

BSD=1

(ITR

PAUSE), or by INIT.

2.5.5

EXAM and DEP Switches

As described in Chapter 1, every successive depresWhen

the

processor

halted,

cycles

the

CON.00 microprogram state.

sion of the EXAM switch after the first one causes

the address to be incremented, thus making it possible to examine successive locations without reload-

When

any

of the LOAD ADRS,

EXAM,

DEP,

ing the address. This same procedure is followed

CONT or START switches are activated, a micro-

for DEP, or when operating on General Registers.

program branch from CON.00 occurs.

Operations following the first one are called STEP
operations. Refer to Flows 14,

2.5

CONSOLE BRANCH

The

Console

microprogram

flows

are

shown

Flows 14.

The

logic

shown

CNSL(02:00)

UBCH

stores

UBCH

H and UBCH MSB DATA L, in the

748175 register, the output of which is decoded by
2.5.1

Idle State

the 7442S. The functions generated by the outputs

CON.00 is the KB11-C idle state which is entered

of these decoders are gated with the outputs of the

upon a HALT. This cycle loops upon itself until

UBCH switch flip-flops and thus generate a modi-

one

of the Console

CNSL

fied UBCH CNSL(02:00) H value, which in turn

ACT (1) H. This function is low during the idle

causes a different branch address to be generated

state;

the

making

Branch

both

switches

sets

UBCF

Enable field of CON.00 is

RACK

BEF(3:2)3

and

14,

when

EXAM

DEP are depressed

more than

RACK

once. Note that when R3(1) of the 748175 is high,

BEF(1:0)0 H high. RACK BRCABO6 L is thus as-

the lower 7442 decoder is disabled (no outputs fO -

serted. Since the UADR field of CON.0O0 is 070, bit

f7 can be true), while the upper 7442 is enabled,

since R3(0) is low; if R3 is reset, the opposite is

forced

RADR(07:00)
CON.00,

which

the

ROM

becomes
thus

address

10,

the

succeeds

[RACL

address

itself.

true.

RACK

BRCABO6 L is not used by any other microstate.

ations.
2.5.2

LOAD ADRS

If the

LOAD

ADRS

The

branch

after

Memory oper-

CON.00

determines

whether the operation is or is not a STEP oper-

switch

now

depressed,

UBCF CNSLO7 (1) H and UBCF CNSL ACT (1)

ation. A second branch after this executes either an
EXAM or a DEP.

H are both asserted; this causes RACK BRCABO7

to be asserted, thus generating
270

(ADR.00).

[UBCF

a ROM address of

CNSLO07

(0)

Figure 2-1 shows a sequence of operations, shown

forces

above the waveshapes, the condition of the various

UBCH CNS(02:00) H low]. RACK BRCABO7 L is

modifying functions, and the inputs to the RACK

used only by LOAD ADDRESS.

logic.

I11-2-2

LOAD
EXAM
ADRS EXAM STEP

UBCF CONS@7 (1)H__|

6 0100
!

UBCH CONS@1 H

—{

]

i
10

UBCH CONS@@ H

I
!

UBCH REG EXAM+STEP L

!
|

A 0,

!
|
1

'
i

:
0

—
1

1
H

S—

0
1

—
1

i
{

/o0t 9040

I
o1

}

!
|

|
UBCH STEP DEP+DEP H 4:
UBCH STEP DEP+DEP L

;

|
|

{

|
!

REG
DEP
STEP

REG
DEP

!
I

:
ol

{

!
|

UBCH REG EXAM+STEP H

:
|

]

UBCH REG DEP+STEP L

REG
LOAD
REG
EXAM
ADRS EXAM STEP

DEP
STEP

(UBCH) R3 (1) H

UBCH REG DEP+STEP H

DEP

{

!
'
UBCH EXAM+STEP EXAM H |
L

:
:
l
1-3437

Figure 2-1

2.6

ENABLE/HALT

SWITCH

Step Branch Address Modification

HALT

POSITION
Paragraphs 2.6.1
of

the

UBCF STOP L is asserted. At the next BRQ strobe

(MSC=6), TCE CLK CONF H is asserted at T3
through 2.6.4 describe the effect

operational

switches

when

the

and sets the Console Flag [TMCA CONF (1) H].

EN-

TMCB BRQ TRUE is then asserted and the instruc-

ABLE/HALT switch is in HALT. When this is the

tion currently being executed branches (when com-

case, KNLC HALT SW H and SCF HALT H are

pleted)

high.

microprogram

BRK.90

(refer

cycle

where

Flows

12)

BEN=12

and

UAD=240. BRK.00 follows BRK.90, and its BEN

2.6.1

Single Instruction

bits=12, with UAD=130. Since the Console Flag is

If the S INST/S BUS CYCLE switch is in the S

set

INST position, KNLC SINGLE BUS CYCLE SW

CON.00 (Flows 14), in which the processor cycles

until Console action is initiated by the operator.

and

SCCF SINGLE CYCLE

H are low, and

I11-2-3

(CONF),

the

microprogram

state

2.6.2

not set at the end of the first instruction, and pro-

Continue

If the CONT switch is now depressed, CON.10 is
entered, followed by BRK.10 and BRK.20 (Flows
12). Since neither BUS INTR nor power-down

gram execution continues instead of stopping.

(TMCA HONOR PWRF L), nor an internal trap

The SINGLE BUS CYCLE switch is disabled when

2.7.2

Single Bus Cycle

has caused entry into the BRK sequence, UBCC

the

(PWRF+INTR) L is not asserted and a branch is

position.

HALT/ENABLE switch

is in the

ENABLE

made to RTIL.60 (Flows 2). During this cycle, the
Console Flag is cleared during TS3 by UBCH CLR

2.7.3

CONF L [BCT=2, or CONS.ACKN and UBCF
CONT (1) H]. The CONT switch flip-flop [UBCF
CONT (1) H] is cleared at T4 by UBCF ACKN T4

UBCF START (1) H can only be set if the Console
Flag has previously been set. START asserts UBCF

STATUS CLR L which sets the processor mode
bits

(BCT=2 and TS4).

Console Start

[PS(15:14)]

switch

signal,

UBCF

Kernel.

START

The

START

clocks

SCCF

The instruction following the one at which the pro-

HALT H into a flip-flop on UBCE; this flip-flop

cessor stopped is now fetched (FET.00) and exe-

sets if the HALT/ENABLE switch is in the EN-

cuted: since the ENABLE/HALT switch is still in

ABLE position.

the HALT position, the Console Flag is again set
by the BRQ strobe and the processor stops after exccuting one instruction.
'

The

2.6.3

In RES.10, BCT=4 (INIT if Kernel Mode). Since

Single Bus Cycle

KST.00

(Flows

14),

RES.00

and

RES.I10

(Flows 3) cycles are then executed.

If the S INST/S BUS CYCLE switch is in the S

PS(15:14) have been set to 00 by UBCF STATUS

BUS CYCLE position, the processor stops in T5 of
the current Unibus or Cache cycle. Refer to Section

CLR L, UBCC START INIT (1) H is set at T3.
This function:

1, Chapter 4 (Paragraph 4.9) of this manual. NPRs
are not allowed when the switch is in this position

direct-sets UBCC RIP+FPSYNC H and

starts the 100 us UBCC RESET WAIT

(UBCF DISABLE NPR L).
2.6.4

one-shot.

Console Reset

If the START switch is depressed when the EN-

position,

RES.20 is now executed, and the microprogram cy-

UBCF CNSL RESET L is asserted. This signal gen-

cles in this state until RIP+FPSYNC H is negated.

ABLE/HALT

switch

the

HALT

erates all three INIT signals and sets the Console
I.

Flag.

RESET WAIT is still on. When it goes
off, at the end of the 100 us, the RESET
ABORT (I us) and UBCC RESET (1) H

2.7

ENABLE/HALT

SWITCH

(10 ms) one-shots are started.

ENABLE

POSITION

Paragraphs 2.7.1

through 2.7.3 describe the effect

RESET

(1)

clears

UBCC

START

of the operational switches if the ENABLE/HALT

INIT (1) H and keeps RIP+FPSYNC H

switch is put into the ENABLE position. When this

asserted.

is the case, KNLC HALT SW H and SCCF HALT

H go low.

RESET (1) H is ANDed with the flipflop

2.7.1

Continue

UBCE

that

START

switch.

This

was

set

asserts

the

UBCE

When the processor is halted and the CONT switch

START INIT L, which in turn asserts

depressed, the sequence is similar to that described

all the INIT signals with the exception

in Paragraph 2.6.2. The Console Flag, however, is

of ROM INIT.

I11-2-4

Refer to Table 2-1. The address displayed depends
on whether or not it is a General Register (GR) ad-

At the end of 10 ms, RESET (1) H goes

low and INIT is negated. RESET (0) H
goes high and a T3 RIP+FPSYNC H is

dress (17 777 700 - 17 777 717).

also negated. This causes a branch to
FET.03 instead of to RES.20 at the end
of the cycle (BEN=10, UADR=334),
and the instruction whose address is displayed is fetched and executed.
5.

2.10.1

General Register (GR) Address

If the address is a GR address, bits 00:03 display

the register number (0 to 17), bits 4 and 5 are Os
(off), and bits 06:21 are 1s (on).

SCCF GEN REG ADRS is asserted (Switch Regis-

The BUST in FET.03 clears (at T3) the
flip-flop on UBCE that was set by the

ter bits 21 = 06 high, bits 05 and 04 low) and SCCF

START switch.

GEN

REG (1)

DRESS

2.8

is set when

depressed.

the LOAD AD-

forces SCCF
DISP ADRS(05:04) low and their corresponding indicators off, and also forces low both select inputs
to the SCCK DISP ADRS(21:16) H multiplexer,
thus selecting its A inputs (+3 V) and forcing the
corresponding indicators on. The SCCK DISP
ADRS(15:06) H multiplexer is disabled by SCCF
GEN REG (1) H and its outputs are high, thus
forcing their corresponding indicators on.

LOAD ADDRESS

During CON.00, bits 15 - 00 of the Switch Register
are loaded into the BR. During ADR.00 (LOAD
ADDRESS), the contents of the BR are loaded
into the SR and into the PCA. These bits are used
in any subsequent Console operation other than a
LOAD ADRS.

The actual physical address used during these operations is determined by Memory Management from
the position of the ADDRESS SELECT switch.

switch

This

VA(03:00) determine the state of address indicators
03-00.

2.10.2

Memory Address

If the address is not a GR address, the address dis-

2.9 EXAM AND DEP OPERATIONS
EXAM, DEP, REG EXAM/DEP and their respective STEP operations are described by Flows 14.

switch, described in Paragraph 1.12. The output of

2.10

signals, NLD DISP ADRS SEL(2:0) H are thus

play

function

of the

ADDRESS

SELECT

this switch is encoded on the Console board. Three
ADDRESS DISPLAY

The ADDRESS DISPLAY indicators are driven by
KNLB VA(03:00) and KNLB DISP ADRS(21:04)
H. These signals are received on J2 by the Console.
They originate on the M8140 module (SCCJ) connector J1. SCCA VA(03:00) H, SCCF DISP
ADRS(05:04) H and SCCK DISP ADRS(21:06) H

are the sources for the KNLB signals.

generated. They are decoded on SSRK and used in
the Memory Management logic. Two of these signals control the multiplexers on SCCK and determinc the source of the address display, as shown in
Table 2-1. VA(05:00) are used for all three map-

pings, since these bits never change (they are not
relocated). VA(15:06) is used for the VIRTUAL

Table 2-1
Address Display

Display
Indicators

Virtual
(6 positions)

00--03

VA(00:03)

04,05

Address Select Switch
CONS

General

PROG
PHY

VA(00:03)

VA04,05

OFF

06-15

VA(06:15)

1621

OFF

SWR(16:21)

PA(16:21)

PHY

IT1-2-5

and CONS PHYS positions (the Switch Register is

2.12

loaded into the SR after

The Console indicators not described in Paragraphs

from

the

BAMX).

a LOAD ADRS and read

VIRTUAL,

MISCELLANEOUS INDICATOR LOGIC

bits 21:16 are

2.10 and 2.1l are driven by the logic signals listed

forced off. In CONS PHY, SCCK SWR(21:16) H

below (in the same order as they appear in Chapter

are rcad. | PROG PHY, PA(21:06) are displayed.

ADDRESS SELECT SWITCH (1.2.1) - The
2.11
The

DATA DISPLAY
DATA

indicators are driven directly by the switch,

indicators [KNLA

DISP

D(15:00) H

and DISP PAR HI (and LO) H] receive their input
from

the

Data

Display multiplexer,

PDRF DISP

D(15:00) H, and from two flip-flops, PDRH IND
HI (or LO) PAR H.

(Refer to Paragraph 1.20.) The select inputs to this
multiplexer are encoded from the DATA SELECT
[KNLD

PARITY

(1.2.5) - PDRH

IND

PAR

and LO PAR H.

PDRFE DISP D(15:00) H selects one of four inputs.

switch

DATA SELECT SWITCH (1.2.3) - The in-

dicators are driven directly by the switch.

DISP DATA SELL (or SEL0O) H]

and mput to St and SO of the multiplexer (PDRF
DISPSI L and DISPSO L) after being inverted.

PAR

ERR (1.3.1) - UBCB IND PAR ERR

H
ADRS

ERR

(1.3.2)

SCCF

IND

ADRS

ERR H
RUN (1.3.3) - TMCF IND RUN H.

PAUSE (1.3.4) - TMC IND PAUSE H.
The

PARITY

indicators receive their input

the parity flip-flops on

from

PDRH. The Cache parity

MASTER (1.3.5) - UBCF IND MASTER H.

bits, DTML HI (or LO) BYTE PAR H are clocked

into the same flip-flop IC as PDRB BR(15:12)A H.

KERNEL,

The output of these flip-flops, PDRB HI (or LO)

by a decode (on the Console board) of SSRB

PAR H are clocked into PDRH DISP HI (or LO)

MMRO MODE 0

PAR

UBCA

IND CLK

H. This signal

SUPER,

USER

(1.3.6) -

Driven

H and MMR0O MODE 1 H.

is as-

serted at T4 during the ROM state following the

ADDRESSING

Pause cycle of all Cache DATI/P cycles. The in-

IND 16 (or 18 or 22) BIT MODE H.

(Mapping)

(1.3.7)

SCCF

dicators are cleared at T4 of PAUSE of all Unibus
cycles or Cache

DATO/B cycles by UBCB CLR

IND (0) H.

DATA (Space) (1.3.8) - SAPK IND DATA
H.

I11-2-6

SECTION 1V
MEMORY MANAGEMENT

Unless otherwise indicated, references within this section pertain to this section only.

SECTION IV

MEMORY MANAGEMENT

CONTENTS
Page

INTRODUCTION — PDP-11/70 ADDRESS SPACE
CHAPTER 1

GENERAL DESCRIPTION

CHAPTER 2

MEMORY MANAGEMENT MAPPING FUNCTION

2.1

CONSTRUCTION OF A PHYSICAL ADDRESS

MANAGEMENT REGSITERS

CHAPTER 3

PAR AND PDR ADDRESSING DURING RELOCATION

3.1

MEMORY MANAGEMENT ROM (SSRA)

3.2

ROM OUTPUTS, 04 — 16

.........................

.................................

3.3

K, S, OR U MODE SELECTION (SSRB)

1 OR D SPACE SELECTION [SAPK ADDR 3 (K, S OR U) L]

3.5

CHAPTER 4

GENERATION OF THE PHYSICAL ADDRESS

4.1

16-BIT MAPPING

4.2

VIRTUAL ADDRESS

4.3

18-BIT MAPPING

4.4

22-BIT MAPPING

...................................

.....................................

oooooooooooooooooooooooooooooooooo

ADDRESS VALIDITY

5.1

UNIBUS ADDRESS

5.2

NOT CACHE ADDRESS

5.2.1

18-Bit Mapping

522

22-Bit Mapping

5.2.3

Console Mapping

CHAPTER 6

..............

.....................................

4.5

CHAPTER 5

.........................

....................................

..................................

....................................

ooooooooooooooooooooooooooooooooooo

DESCRIPTION OF PDR

6.1

ACCESS CONTROL FIELD (ACF)

6.2

ACCESS INFORMATION BITS (A and W)

6.3

EXPANSION DIRECTION BIT (ED)

6.4

PAGE LENGTH FIELD (PLF)

----------------------------

oooooooooooooooooooooooo

---------------------------

64.1

Example of Upward Expansion

6.4.2

Example of Downward Expansion

--------------------------

CHAPTER 7

ADDRESS DECODERS AND READING/WRITING OF PAR/PDR REGISTERS

7.1

7.2

ADDRESSING OF PAR AND PDR REGISTERS FROM THE UNIBUS

7.2.1

PAR/PDR Addresses

7.2.2

Addressing

7.2.3

PAR/PDR Read

7.2.4

PAR Write

7.2.5

PDR Write

............................

.........

.................................

......................................

...................................

......................................

oooooooooooooooooooooooooooooooooooooo

IViii

SECTIONIV

MEMORY MANAGEMENT

CONTENTS (Cont)

CHAPTER 8

MEMORY MANAGEMENT ERROR HANDLING

8.1

PAGE LENGTH ABORTS

8.1.1

LengthFault

8.12

. . . . . . . . .

. .. ... ... .. ..

Illegal ProcessorMode

e
.

. . . . . . . . . . . .

8.2

ACCESS CONTROL FIELD ABORTSANDTRAPS

8.2.1

Non-Resident and Read-Only Protection

8.2.2

Access Faults (Aborts)

8.2.3

Abort Flag

. . . . . . . . o

. . . . . . . . . .

MEMORY MANAGEMENT REGISTERS (MMRO, 1, 2, and 3)

9.1

MMRO

e e

CHAPTER 9

. .

. . . ... ... ... ... .. ... ...

. . . . . . . . . i i i

MEMORY MANAGEMENT TRAPS

7. N5 T )

et e

. ... ... ... . ........

8.3

9.1.1

i it

e e e e e e e e e e

e e
e

e e

e e e e e e

e e e

e e

9.1.2

Trapsand TrapEnable

9.13

Maintenance/Destination Mode

. . .. .. .. ... .

9.14

Instruction Complete

9.1.5

ProcessorMode

9.1.6

Address Space and Page Number

9.1.7

Enable Relocation

... oo

. . . . . . . . . . .

. . . . . . . . .

e e e e e

. . . . . . . L L

e e e e e e e e e e e e

. . . . ... ... ... ...

0oL
e e e e IV9-3

. .. ... ... .... B e e e e e e e e e e e e e

9.1.8

Read/Write Under ProgramControl

9.19

Bits Controlled by Memory Management

. . . . . ... ... ... .. ... ...
. . . ... ... .............

9.2

MM R

e e e e

9.3

MM
R

CLEARING STATUS REGISTERS FOLLOWING TRAP/ABORT

9.5

MULTIPLE FAULTS

9.6

MM R

. . . . . i

. L

e e e e e e e e e e e e e e
e e e e e e e e e e e e

it i it

e e

e e e

e e e e e

e e
e

e .

e e

. ... ........

e e e et e e e et e e

e e e e e e e e e e e e e

e e

e e e

e e

ILLUSTRATIONS

Title

Figure No.
1-1

Example of Physical Memory Page

Construction of PA

. . . . ... .. ... ... ...

1-3

Relocation

BlockDiagram

Interpretationof VA

. . . . . . . ..o

2.2

Displacement Field

. . . . .. ... . ...

Construction of PA

2-4

MM Relocation Function

. . . . . . . . L

. . . . . . . o i i i

e e e e e

. . . . . . . . . i i

e e e e e

PAR/PDR Read/Write
Addressing of PAR/PDR

4-1

16-Bit Mapping

4-2

16-Bit Mapping: Generationof PA

4.3

18-Bit Mapping

4-4

18-Bit Mapping: Cache Address

. . . . . . . . . .

. . . . . . . o

0 i

e
e

e e

e
e

e e

i i

e e e

e e

. . . . . . . . . .

e e

. . . . . ... .. .. ..

2.5

e e e e e e e

. . . . . . . .

3-1

e e

e
e e e e e

. . . . .. ... ... ... .. o000,

. . . . . . . . .

e e e

. . . . . ... ... ... i

SECTIONIV MEMORY MANAGEMENT
ILLUSTRATIONS (Cont)

4-5

18-Bit Mapping: Unibus Address

4-6

22-BitMapping

. . . . . . o

4.7

22-BitMapping

. . . . . . .o

4-8
4-10

Physical Address Generation: Example 1
. . ... ... ... ..............
...
. . . ... ... ... ... ...
Physical Address Generation: Example2
Generation of Physical Address
. . . . . . . . .. ...
o
o e

5-1

Wraparound

18-and 22-BitOverflow

5-3

Console OVerflow

6-1

Page Descriptor Register (PDR)

6-2

AandWBIt Timing

e e

v i e

v v et e e e e e

. . . . . . . . .

6-4

Downward Expansion

Trapsand ADOItS

8-2

TrapTiming

9-1

MMRO

9-2

Clocking of MMRO

9-3

MMRO Write Timing

. . . . .. . . .. .

. . ot

e e

e e e

e e e e e

e e e

e e
e

e
e

e
e e

e e

i it ittt

. . . . . o o i i i it

. . . . . . . o v

e e

. . . . . . . . . . ..t ii

. . . . o o

8-1

e e e e

e e e e e

e e

. . . . . . . . o v i it

. . . . o

e e e

e e

. . . . . . . L

Upward Expansion

. .

. . . . ... ... ... oo

e
e

e e e e e e e

e e e

e e

. . . . . . . . o ot

. . . . . . .« ot v i i et
e
e e
e e e e e e e e e
.

e e
e e e

e
e e

e e e e e
e e e e e e

e
e e

e
e e
e e e

e
e e e
e e e e e e

9-5

Table No.
7-1

PAR/PDR Unibus Addresses

IV-v

INTRODUCTION
PDP-11/70 ADDRESS SPACE

Processor-generated addresses differ from those
that address memory; thus, the processor addresses

are termed Virtual Addresses (VA), and the mem-

\17) 777 777

PERIPHERAL

PAGE (4K)

| __{17) 760000

ory addresses are termed Physical Addresses (PA).

UNIBUS

(17) 757 777

REFERENCE
(128K)

The VA is that generated by the program. It consists of 16 bits. The PA is the result
of modifying

(17) 000 000

the VA in 18- or 22-bit mapping. It is the address

6 777 777

sent to the Cache (22 bits) or to the Unibus (18

)

> NON=-EXISTENT

bits). Three separate address spaces are used:
16 bits, program virtual space
18 bits, Unibus space

22 bits, physical space

SYSTEM SIZE

BOUNDARY
| MEMORY

REFERENCE

The KB11-C Processor System generates a 22-bit address,

which

allows

2048K words (22"

possible

l.
2.

MEMORY OR NXM

address

space

00000000

||
11-4002

2,097,152). Addresses 00 000

000 - 17 777 777 can be used; they are called Phys-

Figure I-1

ical Addresses.

Physical Address Space

Refer to Figure I-1, which shows the components

of the PA Space.
.

Unibus Reference includes 128K PAs, 17

000 000 - 17 777 777, which correspond
Unibus

reference in

turn

the

PAs from

system

size

Main Memory.

There may be no discontinuity in Main
Memory,

The Peripheral Page, which is re-

i.e.,,

available

memory

loca-

tions must be numbered sequentially -

served for Unibus device registers;

from 00 000 000 through the system size

it consists of 4K PAs, 17 760 000 -

boundary. The highest possible address

17 777 777 (Unibus addresses 760

is 16 777 777. Maximum possible mem-

000 - 777 777).

includes

through

available in the system

includes

the following:
a.

Reference
000

000

boundary, which is the highest address

to Unibus addresses 000 000 - 777 777.
The

Memory
00

ory

The remaining 124K addresses, 17

1920K

words

(22!

2!7

1,966,080, or 2048K - 128K = 1920K).

000 000 - 17 757 777 (Unibus ad-

dresses 000 000 - 757 777) may be

Non-Existent Memory or NXM includes

used by Unibus devices to access

the PAs from the system size boundary

memory.

plus | - 16 777 777.

IV.I-1

Relocation is controlled by the program, which can
enable or disable the Unibus Map and/or Memory
Management. The program also specifies the manner in which the addresses are modified when these

ADDRESS RELOCATION
The PDP-11/70, like all other PDP-11s, generates a

16-bit Virtual Address in the range of 000 000 177 777. In order to access the Unibus, which requires an 18-bit address, and Main Memory, which
uses a 22-bit address, the VA must be relocated. In
the same manner, Unibus devices generate an 18-bit
address, which must be expanded to 22-bits in or-

devices are enabled.

MEMORY MANAGEMENT MAPPING
Three methods of mapping are available to Memory Management:

der to access Main Memory.

Refer to Figure 1-2. The 16-bit VA is expanded to a
22-bit PA by Memory Management. If the four
high-order bits of this PA are all 1s (bits 21:18), the
Unibus is referenced. If these four bits are not all
Is (addresses 00 000 000 - 16 777 777), Main Memory is referenced.

18-bit mapping, when bit 4 of MMR3 is
cleared and bit 0 of MMRO is set. (Refer
to Figure 1-4.)

22-bit

mapping,

when

both

bit 4 of

MMR3 and bit 0 of MMRUO are set. (Refer to Figure I-5.)

The Unibus Map performs a function similar to
that of Memory Management: it expands Unibus
addresses from 18 to 22 bits. This function is also
called ““mapping.” The Map accepts Unibus addresses 000 000 — 757 777 and relocates them to the
PA space (00 000 000 - 16 777 777).

777 777-760 000= PERIPHERAL

16-bit mapping, when MMRAO is cleared.
(Refer to Figure 1-3.)

MMRO responds to Unibus address 17 777 572,
MMR3 to address 17 772 516.

PAGE

UNIBUS
777

757 777-000 000

777-000 000

184

18
UNIBUS

ADDRESS SPACE

VIRTUAL

ADDRESS

SPACE

16 777 777

(17) 777 777

UNIBUS MAP

[17] 000 000
16 777 777

00 000 000

00 000 000
22

17 777 777

MEM MGMT
00 000 000

177 777

PROCESSOR
000 000

MEMORY ADDRESS
l

SPACE

16777 777

00 000 000

CACHE MEMORY &
MAIN MEMORY
1-4019

Figure 1-2

11/70 Address Space

IV1-2

FLOW
777777

7777777

UNIBUS

PERIPHERAL PAGE

27760000

17757777

{18 BITS)

- 17600000

124K

000000

N
\

_ 17000000

UNIBUS
MAP

177777

16777777

00757777

1920K

96K

woo

VIRTUAL

00157777

(16 BITS)

28K

000000

————ei_ __looo00000

INCOMING
ADDRESS

_
00157777
28K

00000000

PHYSICAL
ADDRESS SPACE
{22 BITS)

ADDRESS
LOCATIONS
{MAX. AVAILABLE
MEMORY 1024K)

~——eeet= 2 RELOCATION

— ——-—

:=NO ADDRESS
RELOCATION

n-3196

In 16-bit mapping, only addresses in the ranges of 17 760 000 - 17 777 777 (Peripheral Page) and of 00 000 000 - 00 157 777 (Main Memory) may be generated.
In

16-bit mapping, the PDP-11/70 operates as the PDP-11/20, or as the PDP-

11/45 with Memory Management disabled.

Figure I-3

16-Bit Mapping

FLOW

777777

| T
T 4 Vzzzzr e

7777777

PERIPHERAL PAGE

70000
17757777

UNIBUS

{18 BITS)

000000

124K

/117000000

17600000

\\\

UNIBUS
MA?\

6777777

00757777

1920K

124K

177777

VIRTUAL
(168ITS)

000000
INCOMING
ADDRESS

MEM .
MGMT

00000000
PHYSICAL
ADDRESS SPACE

A 00000000

{22 BITS)

ADDRESS
LOCATIONS

(MAX. AVAILABLE
MEMORY 1024K)

————— :RELOCATION
-

- 2NO ADDRESS

RELOCATION

n-31e7

In 18-bit mapping, only addresses in the ranges of 17 760 000 - 17 777 777 (Peripheral Page) and of 00 000 000 - 00 757 777 (Main Memory) may be generated.
In

18-bit mapping, the PDP-11/70 operates as the PDP-11/45, with Memory

Management enabled.

Figure I-4

18-Bit Mapping

IV-1-3

FLOW

777777

7777777

K220

UNIBUS

{18 8ITS)

000000

PERIPHERAL PAGE

weeoooo

/737777

124K

—

L 17000000

17600000

_\_\U__ >

6777777

UNIBUS

6777777

MAP

\\.

1920K

ADDRESS
177777

MEM

MGMT

\
00757777
124K

000000
INCOMING
ADDRESS

Jlooooooo0 |
PHYSICAL
ADDRESS SPACE

g 00000000
ADDRESS
LOCATIONS

{22 BITS)

(MAX. AVAILABLE
MEMORY 1024K)

e 2 RELOCATION
—————

=NO ADDRESS

RELOCATION
n-3198

In 22-bit mapping, the VA may be relocated to any address in the PA space (00
000 000 - 17 777 777). This is the only mapping in which PAs 17 000 000 - 17
757 777 can be generated; they correspond to Unibus addresses 000 000 - 757

777, or the 124K Unibus locations which are not reserved for the Peripheral
Page. The addresses in this range can be usea by the program to access Main

Memory via the Unibus Map.

Figure I-5

22-Bit Mapping

FLOW

777777

STttt
T T
T 7777777

Tttt
T T 17777777

PERIPHERAL PAGE

17760000
17757777

UNIBUS
{18 BITS)

000000

e 17600000
N

\\
124K

17000000

UNIBUS
MAP

6777777

00757777

1920K

124K

00000000
INCOMING

PHYSICAL

ADDRESS

ADDRESS SPACE

{22 BITS)

J[_

ADDRESS

LOCATIONS

—————# + RELOCATION
—

——-—

:NO ADDRESS

11-40560

RELOCATION

Figure I-6

Unibus Map Address Space

V14

Software written for the PDP-11/20 or
11/45 runs without modification on the
PDP-11/70

because

the

Unibus

When the Map is disabled, Unibus addresses

Map

000

757

777

reference.

Main Memory addresses 00 000 000 - 00

should not be enabled by this software,

757 771, i.e., they are not modified.

and because Memory Management will
be enabled as required, i.e., the

18-bit

When the Map is enabled, a Unibus ad-

mode enabled or disabled, and the 22-bit

dress in the range of 000 000 - 757 777

mode disabled. This does not take into

is relocated by adding to it the contents

account the difference in speed between

ofa Mapping Register.

these processors.
UNIBUS MAP ADDRESSING MODES

It should be noted that the operations mentioned in

The Map is enabled when bit 5 of the Memory

2 and 3 above are subject to fixed upper and lower

Management Register #3 (MMR3) is set. MMR3 re-

address limits. These limits may be changed by add-

sponds to PA 17 772 516. Refer to Figure I1-6.

ing or removing jumpers in the Unibus Map.

The Unibus Map never responds to the
Peripheral Page addresses (17 760 000 -

The Unibus Map is described in Section V of this

17 777 777).

manual.

IVI-5

CHAPTER 1
GENERAL DESCRIPTION

Memory

Memory Management receives all Virtual Addresses generated by the program, relocates them if
necessary and then transmits the physical addresses
to the Cache or to the Unibus. Address modification is the main function of Memory Management.
This modification of addresses is called Relocation
because it consists of adding a fixed constant to
every virtual address (Refer to Chapters 2 through

Management

specifies

relocation

page basis, which allows a large program

to be

loaded into discontiguous pages in memory. This
ability eliminates the need to shuffle programs to accommodate a new one. It also minimizes unusable
memory fragments, allowing more users to be
loaded in a specific memory size.

4).

A program and its data may occupy as many as 16
Memory Management also allows the user to pro-

tect one section of memory from access by programs located in another section. It divides the
memory into sections - called pages (Chapter 8).
Each individual page has a protection or access key
associated with it that defines access to the page.
With the Memory Management unit, a page can be
keyed non-resident (memory neither readable nor
writable) or read-only (no write operations to mem-

ory). These two types of protection, in association
with other features, enable the user to develop a se-

cure computer operating system. With the non-resident key,

memory not specifically assigned to a

program can be made unavailable to it (Chapter 9).

pages in the memory. The size of each page may
vary and can be any multiple of 32 words, up to
4096 words in length. This feature allows small
areas in memory to be protected, i.e., stacks, buffers, etc., and also allows the last page of a program, exceeding 4K words, to be of adequate
length to protect and relocate the remainder of the
program (Chapter 8). As a result, the memory fragmentation problem inherent with fixed-length pages
is eliminated. The base address of each page can be
any multiple of 32 words in the Physical Address
space, thus ensuring compacted core. Finally, the
variable page size enables pages to be dynamically
changed at run time.

It is often desirable to load a program into one
area of physical memory and then execute it as if it
were located in another area of memory, e.g., when

The Memory Management unit provides two bits
of active page status information: an ‘“‘accessed” bit

several user programs are simultaneously stored in

cated in the set of addresses beginning at 0. This

and a ‘“written into” bit. These bits can be used by
the operating system program to determine whether
the page has been accessed and, if so, whether it
was written into. The accessed bit can be used by

process is called Relocation. When the processor ac-

operating

cesses virtual address 0, a base address is added to

page should be overlaid with the new program page:
in systems that swap programs back and forth from

memory.

When

any

one program

is running, it

must be accessed by the processor as if it were lo-

the address; thus, the relocated 0 location of the
program is accessed. Typically, this same base address is added to all references while the program is
running. A different base address is used for each
of the other programs in memory.

system

programs

determine

which

a disk. The written into bit can be used to determine whether the page to be overlaid must be

swapped back to the disk or whether it is identicalto a copy already there.

IvV-1-1

Memory Management provides three separate sets
of pages for use in the processor’s Kernel, Supervisor, and User modes. These sets of pages increase
system protection by physically isolating User programs from service Supervisor programs and the
Kernel program. The service programs (compilers,
editors, file system, assemblers, etc.) are also separated from the Kernel program (exception handling, 1/0, memory management, etc.). Separate
relocation register sets greatly reduce the time necessary to switch context between mapping. The three
sets also aid the user in designing an operating system that has clearly defined communications, is
modular, and is more easily debugged and maintained. During development cycles, these features result in time and cost savings; in the final system
design, they result in an efficient and reliable

but are not necessarily, errors. A trap is executed after the instruction during which it occurs is com-.
pleted. Both aborts and traps generated by Memory
Management transfer control to location 250. Three
status registers (Chapter 9) record all information

system.

statistics.

necessary to recover from a Memory Management
abort. This information includes the page number

that faulted, the type of violation that caused the
fault (exceeded length, read-only violation, etc.),
and all information needed to easily restart the
aborted instruction once the Virtual Address has
been corrected.

Three protection keys cause a trap, i.e., an automatic transfer of program control to location 250
at the end of the current instruction. The trap fea-

ture is useful for gathering “frequency of page use”

The Virtual Address space is further divided, within
each of the Kernel, Supervisor and User pages, into
Instruction Space and Data Space (I and D space).
I space contains code, i.e., any word that is part of
the program, such as instructions, index words and
immediate operands. D space contains information
that can be modified, such as data buffers.
By using this feature,

Memory Management can

relocate data and instruction references with separate base address values; thus, it is possible to have
a user program of 64K words consisting of 32K of
instructions and 32K of data. Moreover, a conven-

ient means of building reentrant shared programs is
provided (these programs keep a separate data area

for each user). The ability to relocate data with sep-

DEFINITION OF PAGE
A “Page” is a collection of contiguous addresses.

Memory Management divides the 32K Virtual Address space into eight 4K sections called Virtual
Pages. The lowest Virtual Address in each page is a
whole multiple of 4096. The three high order bits of

the VA [VA(15:13)] are the page number (0-7) and
select a PAR/PDR pair within the current mode
(Kernel, Super or User) and space (I or D).
This PAR/PDR pair in turn defines the Physical
Page. The PAR contains the base address of this
page, which may be on any whole multiple of 32
words. A block consists of 32 words, and a physical
memory page may consist of up to 128 blocks. The
Page Length Field (PLF) of the PDR (bits 14:08)

arate base address values enables shared compilers,
assemblers, editors, and supervisors to be

determines the allowable length of the page. A page
may expand upward (from lower to higher ad-

developed.

dresses) or downward. Expansion direction is deter-

PDP-11 stacks expand by pushing words into lower
addresses and thus growing downward; procedure
sections increase by growing into higher addresses.
All memory pages can be expanded downward or
upward by adding lower addresses (stack) or higher
address (procedure, data). As a result, it is easy to

mined by bit 3 of the PDR (ED).

expand both stack and program pages.

(bits 05:00) field of the VA specifies an address (00
- 77) within the block (refer to Chapter 4).

PHYSICAL MEMORY PAGE

Refer to Figure 1-1. A block consists of 64,0 = 100
bytes or 32;0 = 403 words. The 6-bit word number

An Abort is the non-completion or interruption of
a data cycle due to an error. Abcrts are serviced immediately, prior to the completion of the instruction during which they occur. A Trap is an

A page consists of a maximum of 200z blocks (000
177), or 20034 X 1005 bytes = 20,000 bytes or

10,000 words. Thus, a page starting at PA = 00 000

interruption of the normal program flow by inter-

000 has a maximum possible PA of 00 17 777. A

nal machine conditions. These conditions can be,

block starting at 00 000 000 ends at 00 000 077.

IV-1-2

A Physical Address is constructed as follows (refer
to Figure 1-2): the base address of the page is contained in the selected PAR. The block number field
of the VA (bits 12:06) is added to this base address
to give the base address of the block. The word
number field of the VA specifies the Displacement

PHYSICAL
MEMORY
00 017 777
BLOCK 177

00 017 700

00 017 677
BLOCK 176

In the Block (DIB).

00 017600
1 PAGE =

00 017 577

S g
e
S

» 20000 BYTES MAX.

00 000 200

210000 WORD MAX.

00 000 177

The relocation example shown in Figure 1-3 illustrates several points about memory relocation:

1 BLOCK

00 000 100

Although the PAs appear to the program to be in contiguous address space,
the 32K-word VA space is actually relocated to several separate areas of physical memory. As long as the total
available physical memory space is adequate, a program can be loaded. The
physical memory space need not be

=100 BYTES
=40 WORDS

BLOCK 1

00 000 O77
BLOCK O

00 000 000

ALL NUMBERS IN

BASE

“—ADDRESS

11-4017

OCTAL

contiguous.

Example of Physical

Figure 1-1

Memory Page

VIRTUAL ADDRESS=157 746|1

o[t

—~—

APF

PAR 6 =13 546 000

{

1]1
A

—~——

[

IN BLOCK

]

06/

DISPLACEMENT

BLOCK NUMBER

SELECTS PAF=

PAGE BASE ADDRESS

‘

ol 1

ACTIVE PAGE FIELD

06 05

1312

—

:
'

ADDER

ADDRESS =

13 565 746

00.

121

22-BIT RELOCATED

{

¢+

BASE ADDRESS OF BLOCK

DISPLACEMENT

IN BLOCK (DIB)
1-4082

Figure 1-2

Construction of PA

IV-1-3

MEMORY

PROGRAM

PHYSICAL
MEMORY

MANAGEMENT

VIRTUAL ADDRESS

PAGE|

RANGES

NO.

000000 - 017776

..cE

104 000XX

003200XX

012500%XX

060000 - 077776

000600XX

100000 - 117776

000200XX

120000 - 137776

071000XX

020000 — 037776
040000 — 057776

BASE

140000 - 157776

000200XX

160000 — 177776

001500XX

PHYSICAL

ADDRESSES

10400000}PAGE°

10417776

ooszoooo}PAGE1
00337776

01267776
01250000

}PAGE 2

00167776
00150000

}PAGE 7

oOTNNT7776
07100000

}PAGE 5

00077776
00060000

PAGE 3

00037776 | PAGES
00020000/4 86

I 00000000
1-4016

Figure 1-3

Pages

may

lower

PAs,

with

relocated

ranges.

In the example, Page |

respect

higher

their

Relocation

is relo-

BLOCK DIAGRAM

Refer to Figure 1-4. Memory Management receives

the VA

from the processor. It generates the PA,

cated to a higher range of PAs, Page 4 is

which is received by the Cache or by the Unibus.

relocated to a lower range, and Page 3 is

As a result of its management functions, Memory

not relocated at all, since the Page Base

Management

(=PAF) restores to the VA the three bits

aborts.

(15:13)

which

are

stripped

during

relocation.

Chapters 2 through 5 of this section describe the
generation

Each

informs the processor of traps and

page

relocated

independently.

Two or more pages can be relocated to

of the

Physical

Address.

Chapters

through 9 explain the address checking and error re-

porting functions of Memory Management.

the same physical memory space. Using
more than one page address register in

the set to access the same space is one

UNIBUS

way of providing different memory ac-

VIRTUAL

cess rights to the same data, depending

on which part of a program was referencing that data. In Figure 1-3, note that

the same relocation constant is assigned
to

Pages

within

same

and

both

PAs

address

ranges

memory,

result,

access

using

{AT

ADDRESS

KBI1-B

::::::>

PROCESSOR

MEMORY

:g;gggé

MANAGEMENT

VAs

the

different

CONTROL

CACHE
MEMORY

page address registers.

11-4015

Figure 1-4

IV-1-4

Block Diagram

CHAPTER 2
MEMORY MANAGEMENT MAPPING FUNCTION

When Memory Management is enabled, the normal

16-bit, direct-byte address is no longer interpreted
as a direct Physical Address (PA) but as a Virtual

the operating system may select to disable D space
and map all references (Instructions and Data)
through I space, or to use both I and D space.

Address (VA) containing information to be used in
constructing a new 22-bit PA. The information con-

The basic information needed for the construction

tained in the VA is combined with relocation information contained in the Page Address Register

of a PA comes from the VA, which is illustrated in
Figure 2-1, and the appropriate PAR set.

(PAR) to yield a 22-bit PA. Using the Memory
Management Unit, memory can be dynamically al-

The Virtual Address consists of:

located in pages each composed of from 1 to 128 in1.

tegral blocks of 32 words.

The Active Page Field (APF). This 3-bit
field determines which of eight Page Address

The starting PA for each page is an integer multiple
of 32 words, and each page has a maximum size of
4096 words. Pages may be located anywhere within

Registers

(PARO-PAR7)

will

used to form the PA.

the PA space. The determination of which set of 16
page registers is used to form a PA is made by the

The Displacement Field (DF). This 13-

bit field contains an address relative to

current mode of operation of the CPU, i.e., Kernel,

the beginning of a page. This permits

Supervisor or User mode.

page lengths up to 4K words (2" = 8K
bytes).

2.1

CONSTRUCTION

The

further

subdivided

into two fields as shown in Figure 2-2.

PHYSICAL

ADDRESS

All addresses with memory relocation enabled reference information in either Instruction (I) space or

Data (D) space. I space is used for all instruction

]

fetches, index words, absolute addresses and immediate operands. D space is used for all other refer-

BLOCK NUMBER

DISPLACEMENT IN BLOCK
11-4045

ences. | space and D space each have 8 PARs in
cach mode of CPU operation, Kernel, Supervisor,

and User. Using Memory Management Register #3,

FIELD

Displacement Field

APF

" ACTIVE PAGE

Figure 2-2

DISPLACEMENT FIELD

11-4044

Figure 2-1

Interpretation of VA

IV-2-1

The Displacement Field (DF) consists of:
1.

The PAF of the selected PAR contains

The Block Number (BN). This 7-bit field

the starting address of the currently active page as a block number in physical

memory.

interpreted

the

block

number

within the current page.

The Block Number (BN) from the VA is

added to the PAF to yield the number
of the physical block in memory which
will contain the PA being constructed.

The Displacement in Block (DIB). This
6-bit field contains the displacement
within the block referred to by the Block
Number (BN).

The Displacement in Block (DIB) from
the Displacement Field (DF) of the VA
is joined to the physical block number to

The remainder of the information needed to construct the PA comes from the 16-bit Page Address

yield a 22-bit PA.

Field (PAF), the Page Address Register (PAR) that
specifies the starting address of the memory page
which that PAR describes. The PAF is actually a

2.2

block number in the physical memory, e.g. PAF=3

Memory Management implements three sets of 32
16-bit registers. One set of registers is used in Kernel mode, another in Supervisor, and the other in

indicates a starting address of 96 (3 X 32) words in
physical memory.

User mode. The choice of which set is to be used is
determined by the current CPU mode contained in
the Processor Status word. Each set is subdivided
into two groups of 16 registers. One group is used
for references to Instruction (I) space, and one to

The formation of the PA is illustrated in Figure 23. The logical sequence involved in constructing a
PA is as follows:

MANAGEMENT REGISTERS

Select a set of PARs, depending on the

Data (D) space. The I space group is used for all in-

space being referenced.

struction fetches, index words, absolute addresses

The APF of the VA is used to select a

and immediate operands. The D space group is
used for all other references, providing it has not

PAR (PARO-PART).

been

VIRTUAL ADDRESS (VA)

disabled

APF

06 05
BN

00
DIB

PHYSICAL ADDRESS

OFFSET INTO PAGE (VA< 12:00))

Management

PAR

Memory

13 12

APF

SELECT PAR (VA {15:13))

PAF

11-4043

Figure 2-3

Construction of PA

IV-2-2

#3. Each group is further subdivided into two parts

Chapter 3 describes the selection of the PDR and

of eight registers. One part is the PAR, whose func-

PAR. The VA, the Processor Status Word (PSW or

tion

has

The

other

(PDR).

been

described

part

PARs

the

and

previous paragraphs.

Page

Descriptor

PDRs are always selected

pairs by the top three bits of the VA.

A PAR/PDR

PS),

the

processor

ROM

address,

and

Memory

Management Register #3 (MMR3) bits 2 - 0 (enable

data

space

for

User,

Supervisor,

Kernel

modes) make this selection.

pair contain all the information needed to describe

and locate a currently-active memory page.

Chapter 4 describes the generation of the PA. The

The various Memory Management Registers are lo-

mode), examined by the PA generation circuits, and

cated in the uppermost 4K of PDP-11

output to the Unibus or to Memory.

PAF

PA space

and

the

are summed (except in

16-bit

along with the Unibus I/O device registers.
This chapter and Chapters 3 through 6 describe the

Chapter 5

address

tions:

relocation

function

Memory

Manage-

describes the generation

SAPN

NOT

CACHE

of two func-

ADRS

and

SAPN

ment, and the reading and writing of relocation reg-

UNIBUS ADRS, which are used by other parts of

isters by the program.

the KB11-C for purposes of address checking for
non-existent

Refer to

Figure 2-4.

Relocation

is essentially the

memory

(NEXM) or control

of the

Timing Generator during bus cycles.

process of adding the contents (PAF) of a register

(PAR) to the program or VA. This sum is then
modified, depending on the mapping selected, and

The contents of the PARs and PDRs are controlled

becomes the PA.

by the program, which can load or read them.

CHAPTER

// \\

B8R

[

M.M.
ROM

MMR

ADDER

ADDRESS

PHYSICAL ADDRESS

GENERATION

TO
CACHE
8 UNIBUS

—>

PAR/PDR

ADDRESS

) PARSs

SELECT

SAPN NOT
CACHE

ADRS

SAPN

UNIBUS

ADDRESS

PROCESSOR
ROM

JAN

VA
PSW

CHAPTER

LIMIT
CHECK

SCCL

ENAB 22 BIT MODE

MMR

NJ]

SSRE
RELOC

ADRS

SCCN SYS

S1Z <21:14>

CHAPTER

#-400¢9

Figure 2-4

MM Relocation Function

IV-2-3

Refer to Figure 2-5. Chapter 7 describes these
read/write operations. The address decoders on the
SCC module, which are also explained in this chapter, decode the incoming PA and select the PAR or

ADDRESS

DECODERS
>

Bus.

scce

VA __

PDR indicated by this address. The outputs of
PARs and PDRs are driven onto the Internal Data

—

INT
REG

PARs

>
SAPM

PAR /PDR

APR

SELECTION

81T <15:00>

—

SSRJ
MUX,

> BUS INTD L

SAPK
APR
ADR

MUX.
PDORs

>
VAZ'S

READ
WRITE

)
:

PARs

PDRs

11-4010

Figure 2-5

PAR/PDR Read/Write

1V-2-4

CHAPTER 3
PAR AND PDR ADDRESSING
DURING RELOCATION

NOTE

program ROM, and thus reflects the current state

A working knowledge of the processor microprogram

of the processor.

ROM (Section II, Chapter 1) is required for the un-

derstanding of this chapter.

Drawing SSRL is a truth table of the output of the

Refer to

Figure 3-1. There are 48 PARs and 48
PDRs, which are arranged in PAR-PDR pairs. The

Octal

Location

cessor

ROM

outputs of all PARs are wired-ORed [SAPA+B+C
PAF(21:06)], as are those of the PDRs. Both the

Truth Value ROMOUT columns 1 - 16 show, for

PAR and the PDR, in a pair, are selected and read

serted by the Memory Management ROM. These

Memory

cach

at the same time,

Management ROM. The column headed
refers to

state

processor

listed

ROM

the address of the proin

the

second

column.

state, the bits that are as-

bits are called SSRA ROM OUT(16:01) H. Refer
to Section II, Chapter 1

of this manual for a de-

Each mode (Kernel, Supervisor and User) has 16
PAR/PDR pairs available, eight for I space and

tailed explanation of the processor ROM.

cight for D space.

The two 74S157 multiplexers on SSRA are used as

decoders

for

ROM

One of the Kernel, Supervisor or User PAR/PDR

clocked

into

the

scts

PULSE23 H, which is a buffered TIGE TS2 L.

selected

[PS(15:14)] in
bits

the

PSW

current

mode

bits

OUT(03:01).
74S174

Their output is

flip-flops

SSRK

conjunction with its previous mode

[PS(13:12)] and

the

U space logic on

The functions generated by Memory Management

drawing SSRB.

ROM outputs 1 - 3 are discussed as required where

they are used. ROM outputs 4 - 16 are used indiEither the I space set or the D space set for the cur-

vidually

rent mode is selected by Memory Management Reg-

paragraphs.

ister #3, bits 2 - 0 (Enable K, S or U D space) in
conjunction with the I space enable logic, which is

3.2

also shown on drawing SSRB.

SSRA ROM OUT(04:16) inform the Memory Man-

and

are

explained

the

following

ROM OUTPUTS, 04 - 16

agement logic of the occurrence of certain condi-

One of the cight PAR/PDR pairs in the selected set

tions

outputs is described below.

then

chosen

bits

of the

Virtual

the

processor.

The significance of these

Address.

ROM
3.1

MEMORY MANAGEMENT ROM (SSRA)

The Memory Management ROM shown on drawing SSRA controls many Memory Management
functions.

[RACD

This

ROM

RAR(07:00)

uses

the

same

OUTO04 (Destination Mode) is used during

maintenance mode only; this bit is asserted during
certain Destination Mode memory cycles. It is used
in conjunction with bit 08 of MMRO (Maintenance

address

the processor micro-

Mode)

enable

relocation

cycle of the instruction.

IV-3-1

during the execution

Selected by

SSRB KERNEL SPACE,
SSRB SUPER SPACE and
SSRB USER SPACE logic
Vi

SAPE

PAR

PDR

PAR

KERNEL CS L

SAPE

SUPER PARL

SAPE

SUPERCS L

SAPE

USER PAR L

SAPE

USER CSL

USER

SUPERVISOR

KERNEL

000

KERNEL PAR L

SAPE

PAR

PDR

001

010
I SPACE «——

011
100

101
110
11

PAR

PDR

PAR

PDR

SAPK ADDR 3K L

—(

PAR

SAPK ADDR 3S L
SAPK ADDR 3U L

PDR

| or D SPACE selected

by MMR3 (2:0) and
by SSRB | SPACE A
and SSRB | SPACE B.

D SPACE#—

When SAPK ADDR 3 K,
3 S and 3 U are high,
I space is selected;
when they are low, D

space is selected.

SAPK ADDRZ L
SAPK

ADDR1

SAPK ADDR2 L

One of eight registers

selected by VA (15:13),
11-4012

Figure 3-1

Addressing of PAR/PDR

[V-3-2

ROM OUTO5 [CLOCK PREV MODE (MT/FP)]

These cycles are executed in the space designated

is asserted during ROM cycles that assert BSOPI.
This is shown on the Flows as BC-BSOP1. BSOPI

by the Console ADDRESS SELECT switch.

is normally called for in an execute cycle that is
common to several instructions which have different bus operation requirements. Thus, BSOPI is a

ROM

OUTI3 (SRCM=1+243+4+5) is asserted

during

cycles

DATI for MFP instructions and a DATO for MTP

source register field is 7, this operand is the second

that

fetch

the

source

operand

for

binary instructions with source modes 1 - 5. If the

instructions. ROM OUTOS is used to clock the pre-

word of the instruction and as such is in I space.

vious mode [PS(13:12)] into the K, S, U flip-flops
during MFP and MTP instructions.

These cycles are S13.00, S13.01, S13.10 and S45.10

ROM

asserted

during

MTP and MFP and to other DAC or O/class in-

operand is in I space. ROM OUTOS is also asserted
when

ROM

OUTI14 is asserted (D12.00, DI12.01,

D12.10, D12.60, D12.80 and D12.90, Flows $5), so
that I

space is addressed when

ROM OUTI14 is

asserted

the

MTPI

instruction

either

MFPI

space is accessed, by defini-

tion), or

The Destination Mode of the instruction
(not MFPI or MTPI) is 7 (the word ac-

ROM OUTO07 (BUST) is asserted during all BUST
cycles. ANDed with TI, this bit is used as a clock
in several places in Memory Management.

OUTO09

SPACE

IND

WORD

FETCH) is asserted during all fetch cycles and during cycles that read index words. Since these are all
in I space, 1 space is unconditionally forced when
this bit is asserted. ROM OUTI10 is not used.
ROM OUTI0 is not used.

ROM OUTI5 (DSTM=3) is asserted during DestiMode

ROM OUTII (I IF INST START IN 1) is asserted

cutc the DATO/B portion of a DATIP/DATO
transaction and thus must be executed in the same
space as the previous DATIP data transfer cycle.
ROM OUTI12 (DEPOSIT+EXAMINE) is asserted
during Console EXAM or DEP cycles

only

EXM.10, EXM.20, Flows 14).

cycles

(D30.10,

D30.80

and

D30.90). If the destination register field is 7 during
these cycles, the addressing mode is Absolute and
the address word should come from | space.
ROM OUTI16 (FLOATING POINT INST) is asserted for FPP Immediate Mode bus operations
(FSV.00 and FSV.10, Flows 12). It is used to en-

sure

that

the

immediate operand

comes from

space if DM2 and DF7.

3.3

K,S,OR UMODE SELECTION (SSRB)

The chip select signals for PARs are SAPE KERNEL (or SUPER/USER) PAR L; for PDRs, these

signals are SAPE

during the EXC.00, EXC.10, NEG.20 and SHR.10
microprogram cycles (Flows 11). These cycles exe-

DEP.20,

cessed is in I space). See ROM OUTOS.

nation

ROM OUTO8 (I SPACE IF MT/FPI) is asserted
during destination cycles that are used by MFP and
MTP instructions, along with other instructions. I
space is forced when this bit is asserted if the instruction is an MFPI or an MTPI [(IR15=0)*(IRCC
MFP+MTP)]. See ROM OUT 4.

(DEP.10,

(DSTM=1+2)

structions. If the destination register field is 7, the

(IBS=2).

ROM

OUTI4

Destination Mode | or 2 cycles that are common to

ROM OUT 06 (KERN DATI) is asserted when the
BSC ROM bits=2 and forces Kernel mode during
the Service Flows (Section II, Chapter 6). During
these cycles, the new PC and PS are loaded from
Kernel space. This condition appears on the Flows
as BC-KERN DATI and occurs only in ROM cycles SVC.00 - SVC.30, BRK.30 and TRP.10. These
cycles all force Kernel mode but do not change
PS(15:14). BRK.30 and TRP.10 are followed by
SVC.00, 10, 20 and 30. In this last cycle, the current mode bits, PS(15:14) are stored in the previous
mode bits, PS(13:12), and the new current mode
bits are loaded into PS(15:14) from BR(15:14)

on Flows 1.

KERNEL (or SUPER/USER)

CS L. Because SCCC INT REG H is low during relocation and the B inputs to the multiplexers are selected, both the PAR and PDR chip select signals
have the same source:

SSRB

KERNEL (or SU-

PER /USER) SPACE (1) L. These signals are the
outputs

of three

flip-flops

SSRB

that

are

clocked on the trailing edge of T1 of all BUST cycles (SSRB CLK SPACE H). The input to these
flip-flops are the AND-OR-invert gates SSRB KS
(or SS/US) L.

IV-3-3

During a Console cycle (ROM OUTI2),
the Console ADDRESS SELECT switch
determines the mode [SSRK CNSL
KERNEL (or SUPER/USER) H].
A KERNEL DATI (ROM OUTO06) unconditionally forces Kernel Mode during
the Service Flows.

During the BSOPI (execute) cycle
(ROM OUTO05) of an MFP or MTP instruction, the mode is forced to the previous mode, as determined by PS(13:12).
Note that MFP instructions are
I/class* DAC*BSOPI, which causes their
destination cycle to be a DATI, and that
MTP instructions are O/class*BSOPI,
which causes their output cycle to be a

MMR3 is controlled by the program [BR(02:00)].
The output of the I space logic (SSRB I SPACEA

L and SSRB I SPACEB L) is clocked on the trailing edge

OUTO07

of Tl of BUST cycles (SSRA ROM
H) into the SAPK 1 SPACE flip-flops,

which in turn are gated with the MMR3 outputs to

generate the SAPK APR ADDR bits.

I space is forced whenever the output of either of
the SSRB I SPACE gates is asserted (=low).

SSRB I SPACEA L is asserted under the following
conditions:

DATO. IRCC MFP+MTP H is asserted
during the execution of all MFPI,
MFPD, MTPI and MTPD instructions.

3.4 1 OR D SPACE SELECTION [SAPK ADDR
SORU) L]
3(K,

SAPK APR ADDR3 K L, APR ADDR3 S L, and
APR ADDR3 U L determine whether the I space
or the D space PAR/PDR set is selected; when
they are high, I space is addressed, when they are
low, D space is addressed. The state of these bits is
determined by bits 0, I, 2 of MMR3 and by the 1
space logic on SSRB. During address relocation,
SCCC INT REG A L is high, and the B inputs to
the SAPK APR ADDR3 multiplexer are selected.
An input to this multiplexer is high (thus selecting
D space) if its corresponding MMR3 bit [SCCL
INBL D K (or S/U) (1) H] is high and if I space is

(Kernel,

Super

User)

During all instruction and index word
fetch cycles (ROM OUTO09).

During FPP Immediate Mode bus operations (ROM OUTI16 and IRCC
DSTM2 and SSRB DSTF7).

During Absolute Mode address word cycles (ROM OUTIS and SSRB DSTF7).

SSRB I SPACEB L is asserted under the following
conditions:

During cycles that fetch the source operand

for

binary

instructions

source

modes | - 5 (ROM OUTI13) when the
source field is 7 (IRCB SRCF7). This includes Immediate and Absolute Modes.
During

DATO or DATOB cycles that

complete

OUTI1I),

if the

DATIP

operation

(ROM

mode was

IV-3-4

(SSRB PREV=I). This ensures that the
DATIP-DATO/B

operation

per-

formed to the same memory location.

not required by the logic on SSRB.

indicated by SSRK CNSL I SPACE H.
3]

K, S, or D space is selected by the current mode PS bits [PS(15:14)], if the current cycle is not the BSOP1 cycle (ROM
OUTO05) of an MFP or MTP instruction
(SSRB MF/TP SPACE L), and if the
current cycle is not a Console cycle
(ROM OUTI2). An additional condition
that applies only to Super or User
modes is that the current cycle not be a
Kernel DATI (ROM OUTO06).

LECT switch is in any of the I space positions

During a Console DEP or EXAM
(ROM OUTI2) if the ADDRESS SE-

During

destination

OUTO08) when

cycles

(ROM

ensures that both current and previous

the instruction is either

mode bits are set to User. If this were

MFPI or MTPI [IRCC MFP+MTP and

not done, the User program could read

not IRCA IR15 (1) H], unless both cur-

the

rent and previous modes are User and

MFPI.

Kernel

proprietary

code

via

the

the instruction is an MFPI(IR07=0). In
other words,

the Destination Mode of
MFPI and MTPI is executed in I space,

During Destination Mode 1

or 2 cycles

except that the MFPI is executed in D
space if both previous and current

(ROM

modes

struction is not MFP or MTP.

are

OUTI14),

and

if the destination

ficld is 7 (Immediate Mode) and the in-

User. This prevents a pro-

gram from using MFPI to read from a
read-only page in his | space, thus preserving the integrity of proprietary pro-

3.5

grams (Execute-Only=1I space and read-

only).

The sclect bits for a PAR/PDR pair [SAPK APR
ADDR(2:0)

are

common

all

PARs

and

For example - assume that a User pro-

PDRs.

gram

PAR or a PDR is not directly referenced, and the

requests

service

from

the

Kernel

program by doing an EMT. After this in-

struction, the mode bits in the PSW are:
current [PS(15:14)] = Kernel

After

cxecuting

INT

REG

is high

because a

B inputs to the multiplexers on SAPK are selected.
SAPK

APR

arc

same as

the

which

previous [PS(13:12)] = User

SCCC

ADDR(2:0) and

APR ADDRA(2:0)

BAMX(15:13)

ADDRA(2:0),

are identical to ADDR(2:0), are used only

for the 3101As that contain

PAF(09:06), and are

not buffered (as are the ADDR bits). The address

the

User

program’s

request, the Kernel program returns con-

trol to the User program by an RTI. Before doing this, the Kernel program

IV-3-5

ts implemented in this manner to speed up the gencration of bits 09 - 06 of the PA. These bits, together with VA(05:00) are the index field of the
address input to the Cache.

CHAPTER 4

GENERATION OF THE PHYSICAL ADDRESS

In 16-bit mapping, the Virtual Address (VA) is not

is nrot, these bits are set to 0 to form the Physical

modified, and the relocated address is the same as

Address (PA).

the VA.

In 22-bit mapping, the PA is the same as the relocated address.

In 18- and 22-bit mapping, the VA is added to the

contents of the selected PAR. This sum is the relocated address. [The contents of the selected PAR

4.1

are

Refer to Figure 4-1.

space consists of 28K

memory locations (PA=00

also

referred

the

Page

Address

Field

(PAF)]. The logic that executes this operation is

16-BIT MAPPING

16-bit mapping, the PA

000 000 — 00 157 777) and the 4K Peripheral Page

shown on drawing SAPJ.

(PA=17 760 000 - 17 777 777).

In 16- and 18-bit mapping, the relocated address is

‘Physical Addresses 00 160 000 - 17 577 777 cannot

examined to determine whether it is a Unibus ad-

dress. If it is, the high order bits are set to lIs; if it

mapping.

FLOW

generated

the

processor

172277277

Tttt
T 7777777

PERIPHERAL PAGE

70000

17600000

6777777

1920K

177777

woooo

00157777

16 8ITS)

28K

o000

INCOMING

ADDRESS

opo00000

PHYSICAL

00157777

ADDRESS SPACE

{22 BITS)

————= =RELOCATION

— ==~
— :NO ADDRESS

28K

00000000
ADDRESS

LOCATIONS

11-4049

RELOCATION

Figure 4-1

16-Bit Mapping

IV-4- 1

when

using

this

VIRTUAL ADDRESS=157 745[ t ot ool ot 1t 01 1 1 0 0 1 ol
1

Nttt

21
16-8IT MAPPING

PHYSICAL ADOR.|

157 T46|

+00

16
|

ol1

13
[

o©

NOT UNIBUS ADDRESS

VIRTUAL ADDRESS=167 746l 1 1+ 1o « 1+
[

.—-—_J

“5
16-B81T MAPPING

PHYSICALADDR.l
€17

767

146

*
{

¢t

6
1

{

¢+

1]+

1+ 1+ 1+ 1 1 0 0o t 1 fl
|

[

13
|

00
o

{

UNIBUS ADDRESS

Figure 4-2

11-4020

16-Bit Mapping: Generation of PA

Refer to Figure 4-2. A 16-bit VA is a PA if bits
15:13 are not equal to 111. In this case, bits 21:16
of the PA are made Os, and bits 15:00 are the same

Bits 12:06, the Block Number (BN).
These bits are added to the PAF to form
bits 21 - 06 of the PA.

as in the VA, If bits 15:13 of the VA are equal to

111, a Unibus address is intended by the program,
bits 21:16 of the PA are made Is, and bits 15:00 are
unchanged from the VA,
4.2

Bits 05:00, the Displacement in Block
(DIB). These bits are not altered and become bits 05 - 00 of the PA.

VIRTUAL ADDRESS

The VA consists of three fields:

4.3 18-BIT MAPPING
Refer to Figure 4-3. In 18-bit mapping, the VA is

Bits 15:13, the Active Page Field (APF).
These bits select one of PARs 0 - 7

added to the selected PAF to generate the PA. This
address has a range of 128K, from address 00 000

within the mode and space selected.

000 - 17 777 777.

FLOW

2225k
% A

7777777

PERIPHERAL PAGE

wmoo00

{16BITS)

17600000

6777777

-5

00757777

1920k

124K

177777

VIRTUAL

MEM .
— T MGMT

000000
INCOMING

00000000
PHYSICAL

ADDRESS SPACE

ADDRESS

. 00000000
ADDRESS

(22 81T5)

- :RELOCATION

— — —— —

LOCATIONS

=NO ADDRESS

11-4048

RELOCATION

Figure 4-3

18-Bit Mapping

IV-4-2

If bits 17:00 of the PA are 000 000 - 757 777, it is a

Figure 4-4 shows the case of an 18-bit PA that is

Memory reference and PA(21:18) are forced to ze-

not a Unibus reference, i.e., bits 17:13 are not all

roes. If PA(17:00) are 760 000 - 777 777, it is a

Is. In this case, bits 21:16 of the PA are modified
to zeroes, which causes a memory reference.

Unibus reference and PA(21:18) are forced to ones.

be generated when using this mapping. Refer to Figures 4-4 and 4-5, which show examples of 18-bit

Figure 4-5 shows the case of an 18-bit relocated address that is a Unibus reference, i.e., bits 17:13 are
all Is. In this case, bits 21:16 of the PA are changed

PA generation.

to 1s, which causes a Unibus reference.

Physical Addresses 00 760 000 - 17 757 777 cannot

1312

VIRTUAL ADORESS
= 157 746[1

06 05

APF

BLOCK NUMBER

—-I f{

¢+

]

t+ 0%

]

i
]

I
1

1 0

I
|

06!

I
|

[

]

PAR 6 +13 546 000

IN BLOCK

SELECTS PAR 6

DISPLACEMENT

ACTIVE PAGE FIELD

o0 0o o

!
:

;

INPUT TO

MULTIPLEXERS = |

13 565 746

21
18-BIT MODE

200 565 746

[v]

PHYSICAL ADDR|]

[

)

[

{

o]}

NOT

UNIBUS ADDRESS
1-4032

Figure 4-4

18-Bit Mapping: Cache Address
i

1312

VIRTUAL ADDRESS =157 74sl vt

oot

APF

BLOCK NUMBER

PAR6 =13 746 000

|
|

)
[
I

I
|

06!
t

}

]

INPUT TO

MULTIPLEXERS=[t

13 765 746

PHYSICAL ADOR|

¢+

21
18-B1T MODE

=17 765 T46

IN BLOCK

12
1

]

DISPLACEMENT

2
t

[

SELECTS PAR 6

0 0

[

ACTIVE PAGE FIELD

1|1

06 05

UNIBUS

)

{

ADDRESS
1-403

Figure 4-5

18-Bit Mapping: Unibus Address

V-4-3

4.4

22-BIT MAPPING

Addresses 17 760 000 - 17 777 777 are Unibus /0O

Refer to Figures 4-6 and 4-7. In 22-bit mapping,

Page references. Addresses 00 000 000 - 16 777 777

the VA is relocated in the same manner as in 18-bit

are

mapping, but the relocated address becomes the PA

from 17 000 000 - 17 757 777 may be used to ac-

without modification. Thus, all PAs from 00 000

cess memory via the Unibus Map (dotted lines on

000 - 17 777 777 can be generated.

drawing).

FLOW

memory

references.

The

T 12777777

PERIPHERAL PAGE

wweo000

1700000

V737777

124K

17000000

6777777

_—

UNIBUS

16777777

MAP

19206

ADDRESS
177777

1920K

MEM

/.MGMT

000000

Jloooo0o00

INCOMING

)

00000000

PHYSICAL

ADDRESS

ADDRESS SPACE

LOCATIONS

(22 BITS)

= = RELOCATION

—————

:NO

ADDRESS

RELOCATION

11-4047

Figure 4-6

22-Bit Mapping

1312

06 05

VIRTUAL ADDRESS 157 746[ A

TR - T A T

(R TS TR SN SN N A T

]

APF

. S -S

]

}

BLOCK NUMBER

]

DISPLACEMENT

IN BLOCK

]

{

SELECTS PAR 6

[

PAR 6 =13 746 000

06!

ACTIVE PAGE FIELD

]

|
|

21
ADDRESS =
13 765 746

ADDER

17
|

;
{

13
1

22 BIT PHYSICAL

:
[|

X
¢}

00!
1

11- 4037

Figure 4-7

22-Bit Mapping

IV-4-4

124K

of addresses

1312

VIRTUAL AODRESS«157 746|1

o]+t

APF

06 05

BLOCK NUMBER

PAR 6 :13 546 000

|
[

i
|

o€’

]

1 00

]

1 0

]

0 0 O

:
1

]

22-81T MAPPING
PHYSICAL ADOR:|

13 568 746

PHYSICAL ADDR: | ©

18- BIT MAPPING

)

[+)

[}

[»)

[}

ADORESS

NOT UNIBUS

00 187 746

—-..[1

MAPPING

‘I

IN BLOCK

SELECTS PAR 6

PHYSICAL ADDR=|

ACTIVE PAGE FIELD

16-BIT

1 1

DISPLACEMENT

00 565 746

1|+ o o

11-4030

Figure 4-8

Physical Address Generation: Example 1

Refer to Figures 4-8 and 4-9. It should be noted
that if the mapping is changed, the PA may also be
changed. In Figure 4-8, three different PAs are generated from the same VA and PAF:
1.

In 22-bit mapping:

13 565 746

In 18-bit mapping:

00 565 746

In 16-bit mapping:

00 157 746

These PAs are all memory references.

IV-4-5

1312

VIRTUAL ADDRESS:
137 746t | 1

0ol

| W—

APF

BLOCK NUMBER

]

t
(

|
|

SELECTS PAR &

[

PARG <13 746 000

ACTIVE PAGE FIELD

IN BLOCK

{

DISPLACEMENT

112

22-BIT MAPPING
PHYSICAL

ADDR»

13 768 746

18-BIT MAPPING
PHYSICAL ADDR= |

]

ADORESS

00 157 746

16-BIT MAPPING
PHYSICAL ADDR:|

17 765 746

UNIBUS

¢+

1-4039

Figure 4-9

Physical Address Generation: Example 2

In Figure 4-9, also using the same VA, three different addresses are generated, two of which are mem-

ory references and one a Unibus reference:
I.

In 22-bit mapping:

13 765 746

In 18-bit mapping:

17 765 746

In 16-bit mapping:

00 157 746

1V-4-6

4.5

RELOCATION LOGIC

SELO

The relocation logic shown on schematic SAPJ is
controlled by three functions:
I

SSRA KY PH MEM AC (1) H, which
or

DEP cycles if the

ADDRESS SWITCH is in PROG PHY

or CONS PHY.
SCCL ENAB 22BIT MODE H, or bit
04

MMR3

(address

772

bits 00 and 08 of MMRO (address

777 572). These bits are also generated
by the program.

Bit 00 causes RELOC

when

SSRA

MEM AC (refer to |1 below) is cleared.

Bit 08 allows one additional condition to
assert

RELOC: SSRA

DST (1) H

set;

this flip-flop is set on the trailing edge of
T1 of bus cycles that write into a destination address. (See 5 below.)

it is the SO and S3 control input to the
ALU

ICs.

are combined

inputs

the

The

quired [VA(15:13)=111], and PA(21:16)

become all

Is; if VA(15:13) are not all

Is, EX MEM FLAG is low, PA(21:16)

become all 0s. In both cases, PA(15:00)
equal VA(15:00), since the B inputs to

the 74S157

are selected and the ALU

function is

A (RELOC not asserted).

If RELOC is now asserted and SCCL
ENAB 22BIT MAPPING H is not (18-

bit

mode),

A+B

and

the
all

ALU

mode

addresses

are

becomes
relocated.

SELI and SELO are both low, the B inputs to the 74S153s are selected, and the

ALU function is A+B. If PA(17:13) are
all

Is (Unibus address), PA(21:18) also

become all

1Is. If PA(17:13) are not all

Is, PA(21:18) become all Os (memory reference). In both cases, the remainder of
the PA equals the output of the ALU

RELOC controls the ALU function, as
74S181

18-BIT Mapping

SSRE RELOC L, which is controlled by

asserted

The

516),

which is controlled by the program.

low.

FLAG H is high, a Unibus address is re-

is a flip-flop that is set during all ROM
Console EXAM

74S153s are selected. If SAPH EX MEM

(bits

15:13

are

selected

through

the

745157 multiplexer).

three functions

to generate

SAPJ

SELO

22-BIT Mapping

and SEL1 H, which control the four PA

If ENAB 22BIT MAPPING is now as-

multiplexers.

serted, SELI

is low and SELO becomes

high, thus selecting the A inputs to the
Refer to Figure 4-10.

74S153s.

The

function

A+B.

The output of the ALU becomes the PA
Console Mapping

without modification.

If'SSRA KY PH MEM AC (1) H is set,

both SEL1 and SELO are high and Mem-

Destination or Maintenance Mapping

ory Management is in Console Mapping.

If MMRO bit 00 is cleared and bit 08 is

The D inputs to the 74S153 multiplexers

set,

and the B inputs to the 74S157 are se-

16-bit

lected.

SAPJ

PA(21:16)

equal

SCCK

Memory

Management

mapping,

except

operates

during

certain

destination mode ROM cycles, which it

SWR(21:16), PA(15:13) equal VA(15:13)

executes in either

[SWR(15:00) are stored in the SR during

ping (depending on the state of SCCL

18-bit or 22-bit map-

a LOAD ADRS and read back via the

ENAB

BAMX].

cycles during which this occurs are those

Since

RELOC

Console mapping,

negated

PA(12:00) also equal

VA(12:00).

for

22BIT

which

the

MAPPING).
Memory

The

ROM

Management

sub-ROM bit 04 is asserted.

16-BIT Mapping

If KY PH MEM AC is cleared and RE-

This mapping should only be used for di-

LOC is not asserted, SELI

agnostic purposes.

is high and

1V-4-7

YES

CONSOLE

PHYSICAL

RELOC

ASSERTED

SELOH =H

Yes

:Eto'l':-l-’:_

SEL1H=H

22 81T MODE TM\,
ENAB

SELOH =L

SEL1H=H

ASSERTED

SELOH=L
SELT1H=L

18.81T MODE

228I1T MODE

PA17:13

VA (15:13

=111 11

=111

YES

ADRS (21:00) —m——
g

Pal1r

111

pPA]JO0

11e——nu"
ADRS (12:000 —

111

000 «————eu
ADRS (17:00)

111

]

VA (16:00) ————a o\

]

*+—— VA(12:000 ——»f PA

1815

000

1312

1615

18 17

16 15

SWR (21:16

1312

18 17

111

CNSL PHYS.,

16-81T MODE

111

] PA
—
VA (15:00)
00 @————

P11

|
11 - 4011

Figure 4-10

Generation of Physical Address

fore the processor MSYN. The output

ROUTING OF PHYSICAL ADDRESS

of the drivers is BUS A(17:00) L.
1.

Unibus

Drivers

SAPJ

PA(17:12),

SCCA PA(11:06), and SCCA VA(05:00)
are

input

SCCL.

the

The gating

Unibus

function

Cache - SAPJ PA(21:06) are an input to

the Cache address multiplexer, ADME

UBCA

AMX(21:06). The Cache receives address

drivers

CPBSY B H, which is asserted 150 ns be-

1V-4-8

bits 05 - 00 directly from the BAMX.

CHAPTER 5§
ADDRESS VALIDITY

Memory Management examines an address for the

5.2

purpose of determining whether it is a Unibus ad-

SAPN NOT CACHE ADRS is used to notify the

NOT CACHE ADDRESS

dress, or a valid Cache address. The signals gener-

CP that the address generated by Memory Manage-

ated as a result of this examination are used by the

'ment does not exist in the Cache. This signal is the

TMC and
operations

result of a comparison between the PA and the Size

UBC

modules

during

data

transfer

5.1

UNIBUS ADDRESS

16-bit Mapping - All 16 bit mapping ref-

erences are legal memory references or

SAPN UNIBUS ADRS L is asserted whenever the
PA points to a Unibus reference.

Unibus

addresses;

therefore

com-

parisons are necessary.

The four AND inputs to SAPN UB ADRS L each

18-bit Mapping - If there is more than

decode the Unibus address for the four mapping

128K of memory on the system, then all

modes:

addresses that can be generated are valid
addresses. If, however, there is less than

In 18-bit mapping, when PA bits (17:13)

128K of memory, invalid addresses are

are all Is;

possible and must be tested for.

In 22-bit mapping, when

PA(21:18) are

all Is;
3.

16-bit

MEM

mapping,

FLAG

when

SAPH

high.

[i.e.,,

when

VA(15:13) are all asserted]
4.

22-bit

Mapping

- The PA

is checked

against the Size Register.
Two arithmetic signals are used to generate NOT
CACHE

ADRS:

OVERFLOW

and

WRAPAROUND.

In Console mapping, when switch regis-

WRAPAROUND

ter bits (21:18) are all 1s.

CACHE ADRS if there is a carry out of the MSB

asserted

and

disables

NOT

of the PA being generated.

The output of SAPN UB ADRS L is ORed with
SCCC INT REG

e.g., 18-bit mapping:

B L, which decodes PAR and

PDR addresses. These are Unibus addresses and as

If the PAR contains 007 777 and the VA is 000

such are decoded by SAPN UB ADRS L; SCCC

100, the address generated is 00 000 000 (a valid

INT REG B L, however, is stable until T1 of the

memory reference) and 18 BIT WRAPAROUND L

is true.

BUST

cycle,

and

keeps

SAPN

UNIBUS

ADRS L asserted if the reference was to a Memory
Management register.

e.g., 22-bit mapping:

IV-5-1

SAPJ 18-BIT WRAPAROUND L is the carry output of bit 17 of the adder; 22 BIT
WRAPAROUND is the carry output of bit 21. Refer to Figure S5-1. A carry can only be generated at
bit 21 when the PAF bits (21:13) are all Is and a
carry is generated by the sum of bits 12 of the PAF
and the VA. Figure 5-1 shows the generation of the
greatest PA possible with WRAPAROUND : 00
017 6(77). This is a Cache address. The 18-bit

If the PAR contains 177 777 and the VA is 000
100, the address generated is 00 000 000 (a valid
memory reference) and 22 BIT WRAPAROUND L
is true.

OVERFLOW H is asserted when the PA is greater
than the highest legal address in memory.

WRAPAROUND

The first time OVERFLOW H is asserted is when
the PA is greater than the value in the Size Register, i.e., the PAR is equal to the Size Register and a
VA of 000 100 is used. For instance, if the Size Register contains 5777, there is 96K of memory. If the
PAR contains 5777 and the VA equals 000 100, the
PA generated is 00 600 000, which is the first nonexistent memory address.

by the following examples:
Q<P

This is checked b)./ the WRAP'AROUND and
OVERFLOW functions, except in the case of

p
Q

SCCC INT REG H.

5
_3

WRAPAROUND is generated by the relocation

logic on SAPJ for 18-bit and for 22-bit mapping.

Q=P

101
+100
1

5
_s

]

5
-6

010

101
0

_*001

0 111

carry

0 110

no carry

(\
T

Q>P

101
+010

001

max-

OVERFLOW is generated on SAPN for 18- and
22-bit mapping and on SCCN for Console mode to
determine if the address is greater than the System
Size Boundary. In both cases, the adders are used
as comparators and only the carry output is used.
A I's complement subtraction is implemented in
both cases. A number Q is subtracted from another
number P by adding the 1's complement of Q to P.
A carry is generated only when Q<P, as illustrated

PA is above the size boundary.

T
]

generates the same

bit mapping.

SAPN NOT CACHE ADRS H is asserted when either SAPN UB ADRS L or the AND-OR-invert
gates are asserted. This last gate is asserted if the

PAF

also

imum address, which is also a Cache address in 18-

no carry

]

+
12

(C\

ADRS

1|0

(RN
|

(RN I
|

o
|

SAPJ

¢t

1t
|

t
)

]

22BIT WRAPAROUND L
11-4036

Figure 5-1

Wraparound

IV-5-2

The carry therefore flags a Q<P condition which in-

dicates a legal memory reference.

PAF13 is added to 0. The ALU function

is A plus B.

Overflow is generated for 18- and 22-bit mapping

SCCN

SYS

SIZ(21:14)

subtracted

on SAPN. There is an overflow if the PA is greater

from PAF(21:14). The ALU function for

than the system size: PA>SIZ. Refer to Figure 5-2.

these bits is

This is tested by the function

plished internally by adding A to the I’s

A minus B, which is accom-

complement of B.

PA-SIZ

For Console

But

mapping, overflow is generated

SCCN. SCCN CONS OVERFLOW H

is the in-

verted carry output of an 8-bit adder, the inputs to
PA = (PAF+VA)

which are the System Size Register and the nega-

tion of the Console switch address. Bits (15:14) of

therefore

the Switch Register are read from SCCA VA(15:14)
C L, while bits (21:16) are read directly from the

PA-SIZ=(PAF+VA)-SIZ or PA+(VA-SIZ)

switches; this is because bits (21:16) of the Switch
Register are loaded into the SR during

Since the subtraction is done by adding the com-

a LOAD

ADRS cycle, and read from the BAMX.

plement of the subtrahend to the minuend,

Refer to Figure 5-3. The arithmetic operation conPA-SIZ=PAF+[VA+(notSIZ)]

sists of summing the System Size Register with the

This is the function implemented by the adder on

tion of the final carry (=borrow) as the indication

SAPN:

of an OVERFLOW. This operation gives the same

negation of the switch address, and taking the nega-

result as would subtracting the System Size Register
I.

PAF(12:06) are added to VA(12:06). The

from the Switch

ALU function is A plus B.

verted carry as the indication of an OVERFLOW.

VA + (- S12)

-sl1z
I

+
+

21
PAF

PAF

21
PA-S1Z

—

SAPN

18 BIT OVERFLOW H

»SAPN

ADRS OVERFLOW H

1-4034

Figure 5-2

18- and 22-Bit Overflow

IV-5-3

[SYS SIZ(21:18) are all 0s]. If this is true, there is

less than

SIZ

invert gate is enabled, and an OVERFLOW with

no WRAPAROUND means that the address is too

128K of memory in the system. In this

case, the 18-bit input AND gate to the AND-OR-

high, and thus not a Cache address. The output of
the gate is low either when not in 18-bit mapping,

-SWR

or if the System Size is greater than 00 777 777.
Since this address is the greatest that can be generated

-VA

5.2.2

——

18-bit

mapping,

OVERFLOW

mean-

22-Bit Mapping

If there is a 22-bit OVERFLOW (SAPN

ADRS

OVERFLOW

asserted),

and

if there

WRAPAROUND (SAPJ 22-BIT WRAPAROUND

ingless and the 18-bit mapping gate is disabled.

L is high), then the address is not a Cache address

in 22-bit mode.

5.2.3

Console Mapping

The PA is not a Cache address if, during a Console

-C4

DEP or EXAM operation with the address switch

SCCN CNSL OVERFLOW H

in ecither of the PHYSICAL positions, the Switch
Register contains an address greater than the Sys-

11-4039%

tem

- Figure 5-3

Size

Boundary

(SCCN

H).

Console Overflow

CNSL OVERFLOW

SSRA KY PH MEM ACC is the output of a flipflop, clocked at every T1, whose input is the AND
of SSRA ROM OUT 12 and SSRK CNSL PHY

5.2.1

18-Bit Mapping

ADRS H. The first function is asserted only during

The logic for 18-bit mapping, SAPN NOT CACHE

EXM

ADRS, is the same as that for 22-bit mode with the

ADDRESS

exception of the added wired-OR gate; the output

PHY or CONS PHY positions. Note that PROG

or DEP ROM cycles; the second when the

SELECT

switch

either

PROG

of this gate is high only when in 18-bit mode (SAPJ

PHY is used only for readout and is meaningless

SELO and SEL1 H both low) and when the System

during a DEP (write) Console operation. Refer to

Size Boundary is less than or equal to 00 777 777

Section 111, Chapter 1.

IV-5-4

CHAPTER 6
DESCRIPTION OF PDR

In addition to its relocation function, Memory Management has supervisory or memory protection

The keys of access control are as follows:

functions.

000

non-resident

abort all accesses

001

read-only

abort on write attempt
memory management trap on

The Page Description Register (PDR) is read at the

same {ime as its corresponding PAR during relocation and contains all the information required for
the supervisory functions. Figure 6-1 shows the

read

010

read-only

011

unused

abort on write attempt

PDR bit pattern.
abort all accesses:
reserved for future use

6.1 ACCESS CONTROL FIELD (ACF)
This three-bit field, occupying bits 2-0 of the PDR
contains the access rights to a particular page. The
keys specify the manner in which a page may be ac~cessed and whether or not a given access should result in a trap or an abort of the current operation.
A memory reference which causes an abort is not
completed while a reference causing a trap is completed. In the context of access control, the term
“writeTM is used to indicate the action of any instruction which modifies the contents of any addressable

100

read/write

Memory Management trap

upon completion of
a read or write
101

read/write

Memory Management trap

upon completion of a write

110

read/write

no system trap/abort action

111

unused

abort all accesses;

reserved for future use

word.

.PLF ‘

PAGE LENGTH FIELD —T
A BIT (TRAP)

PAGE WRITTEN INTO (TRAP)

EXPANSION DIRECTION)
(0O=UP, 1= DOWN)

ACCESS CONTROL FIELD
11-4033

Figure 6-1

Page Descriptor Register (PDR)

IV-6-1

It should be noted that the use ofI Space in con-

OUTO07=BUST) the contents of the A and

junction with

(SAPD+E+F

read-only access, provides the user

with a further form of protection, Execute Only.

ATTN H

bits

and SAPD+E+F

RAM WRTN INTO H) are clocked into the SAPD
ATTN

6.2

RAM

ACCESS INFORMATION BITS (A and W)

and SAPD WRTN INTO flip-flops. This

saves the previous contents of these bits.

A bit (bit 7) — This bit is used by software to determine whether or not any accesses to this page met

the trap condition specified by the Access Control

PULSE BC9D H), if RELOC is asserted, and if the

Field (ACF). (A =

PDR is not being read or written (SCCC INT REG

1 is affirmative). The A bit is

the

pause

cycle

that

follows

(SAPC

used in the process of gathering Memory Manage-

B L is high or not asserted) and if Memory Man-

ment statistics.

agement is enabled (RELOC asserted), the write enable (W) input of the 3101A is enabled (SAPD WR

W Bit (bit 6) - This bit indicates whether or not

A+W L asserted), and SAPD ATTN DATA L and

this page has been modified (i.e., written into) since

SAPD WRTN DATA L are written, respectively,

either the PAR or PDR was loaded (W =
firmative).

The

bit

useful

1| is af-

into the A and W bits of the selected PDR. These

applications

two gates are enabled during relocation by SCCC

which involve disk swapping and memory overlays.

INT REG B L, which is high at this time.

It is used to determine which pages have been modi-

fied and hence must be saved in their new form,

If there is no abort condition (SSRC KT ABORT

and which pages have not been modified and can

FLG L

simply be overlaid.

(SAPL MEM MGMT H), or if the previous con-

high), and if there is a trap condition

tents of the A bit =

1, then SAPD ATT DATA L

The A and W bits are reset to 0 whenever either

is asserted, and a | is written into the A bit of the

the PAR or the PDR associated with it is modified

PDR (SAPD+E+F RAM ATTN H).

(written into) by the program, as described in Chapter 7 (Paragraph 7.2).

Similar logic is used for SAPD WRTN DATA L,
When the PDR (or its corresponding PAR) has just

which

loaded

into

the

bit:

if there

been loaded by the program, the A and W bits are

abort

condition,

and

the

cycle

0. Refer to Figure 6-2. When the PDR is next used

DATOB or DATIP (SAPL WRITE CYCLE H), or

during relocation, its output becomes available dur-

if the W bit was previously a

ing

INTO (1) L], then WRTN DATA is asserted.

the

BUST cycle. At T5 of this cycle (ROM

SAPD

BUST

TS5

—
T5|

BUST C (1) H

SAPE KERNEL (SUPER, USER) CS L

(CLOCK ATTN and WRTN INTO)

SAPL MEM

MGMT H

SAPD WR A+
W L
11-4023

Figure 6-2

A and W Bit Timing

IV-6-2

DATO,

[SAPD WRTN

PAUSE

T | h|

6.3

EXPANSION DIRECTION BIT (ED)

6.4.1

Bit 3 of the PDR specifies the direction in which

Example of Upward Expansion

A page starting at location 00 017 000 and contain-

the page is to expand. If ED = 0, the page expands

ing 52x blocks is to be defined. The page is to ex-

upward

pand upward.

from

block

number 0 to include blocks

with higher addresses. If ED = 1, the page expands

downward

from

block

number

177¢

Refer to Figure 6-3. When the page expands up-

include

blocks with lower addresses.

ward, ED = 0, and the PLF is set to the number of

blocks authorized for page, minus 1. As shown in
Upward expansion

is typically used

for program

the Figure:

space, and downward expansion for stack space.
PLF

S51g,

which

authorizes

524

blocks

(0-51) for the page.

6.4

PAGE LENGTH FIELD (PLF)

The seven-bit field occupying bits 14:08 of the PDR

PAF

specifies the block number (BN) which defines the

base address = 00 017 000.

1704, which establishes the physical

boundary of that page. The BN of the VA is compared against the PLF to detect length errors.

PLF + PAF =

170 + 51 = 241;, which is the

PA of the last block that may be used.
An error occurs when expanding upward if the BN

is greater than the PLF, and when expanding down-

Any

ward if the BN is less than the PLF.

will cause an abort.

A page length error causes an abort.

The last legal PA in this example is 00 024 176.

ACTIVE

block

PAGE REGISTER

number

greater

(APR)

PAR

PDR

000

[VA(12:06)]

0OO0COOCOOCTIYIT
T 1 %+ 00 O

08 07 06

03 02

1(O}O

oj1y

PAF

PLF

00
1t

ACF

PAF =000 1704

PLF=52,4-1251y=

LARGEST BLOCK

7.7, 00036776]

//BLOCK 1774
ADDRESS

RANGE

OF POTENTIAL PAGE
EXPANSION BY
CHANGING THE

NO.

UPWARD EXPANSION

)

7,
7’BLOCK 1764 oy

ANY BLOCK
GREATER

NUMBER

THAN 514

(VAC12:06> GREATER THAN 51g)

PLF

WILL CAUSE A PAGE
LENGTH ABORT

', BLOC

00024176

BLOCK

51g

00024100

e
K=

0170XX

START OF

+51

BLOCKS

024 1XX

LAST

PAGE

BLOCK

00017276
AUTHORIZED

LENGTH = 524

PAGE

BLOCKS

{0-51)

BLOCK 2

00017200
00017176

BLOCK 1
00017100

00017076
BL OCK O
00017000

f+—BASE ADDRESS OF PAGE
1-4026

Figure 6-3

Upward Expansion

IV-6-3

than

51y

367« - 52« (or + 1264) = 315, which defines the

6.4.2 Example of Downward Expansion
A page whose base address is 00 017 000 is to contain a 52x block stack (downward expansion).

first illegal address as 00 031 576.

Another method for calculating downward expan-

Refer to Figure 6-4. When the page expands down-

sion follows:

ward, ED = 1, and the PLF is set to the 2’s com-

PLF = 1264, which is the 2's complement of
52.«. the number of blocks authorized for the

plement of the number of blocks authorized for the

page. As shown in the Figure:

page.

PLF = 1264, which is the 2's complement of 52,

PAF = 1701, which establishes the physical

the number of bi cks authorized for the page.

base address of 00 017 000.

PAF = 170«, which establishes the physical base ad-

PLF+PAF = 1264170 = 3164, the last legal

dress of 00 017 000.

block address.

PAF + 177¢ (Maximum number of blocks per
page) = 367, thus making the starting word address 00 036 776, and the initial setting of the stack

3165+ 52« = 370, which is the highest legal ad-

dress +2, and gives the initial setting of the
stack pointers, or 00 037 000.

pointer 00 037 000.

ACTIVE PAGE REGISTER (APR)

BAR

POR

1t o1 01t t olo|o
|
|

000O0O0COO0OO0OT11T 1 1 1 00 O
|
|
|

A W

PLF

PAF

PAF=2's COMPLEMENT*

PAF : 0001704

OF 52g=1264 =

+ o
111
ED

Det=

* 2'S COMPLEMENT = 1'S COMPLEMENT + 1:
524+ 0101010

00036776

BLOCK 1778700

00036

00036676
BLOCK 176g

AUTHORIZED PAGE
LENGTH= 524 BLOCKS
(177g-1264)

00036600

00036576
BLOCK 175g
00036500

\’WV\M
SooeTe

170 PAGE BASE ADDRESS

/ PAGE
+177 MAX. BLOCKS

367 FIRST BLOCK ADDRESS
=52 BLOCKS

315 FIRST ILLEGAL ADDRESS
oR

_—
/ PAGE
+170 MAX. BLOCKS
316 LAST LEGAL BLOCK

+52 NO, OF BLOCKS

BLOCK 126g

]

FIRST BLOCK OF DOWNWARD

EXPANDABLE PAGE

370005 b4 STACK POINTER
00031600
—— >
1
9
/BLOCK 125

+1
—_1
1010110 =126

/BLOCK 124g

ADDRESS RANGE
QF POTENTIAL PAGE
EXPANSION BY
CHANGING THE PLF

A BLOCK NUMBER
REFERENCE LESS

YA THAN 126g
> LESS THAN 1263g)
" (VA <12:06
7 WILL CAUSE A PAGE
7, 00017176

7/, BLOCK | %

700017100

LENGTH ABORT.
{00 017 000 -00 031 576)

/00017176

BLOCK 07
Ja— BASE ADDRESS OF PAGE

11-4027

Figure 6-4

Downward Expansion

V-6-4

ACF

DOWNWARD EXPANSION

LOWEST 8LOCK NO.

= 1010101
1S COMP

03 02

08 07 06

CHAPTER 7
ADDRESS DECODERS AND READING/WRITING
OF PAR/PDR REGISTERS

SCCB SUPER PAR ADRS L

are used as addresses in the processor as well as in

17 772 240-17 772 276

Memory Management.

SCCB USER PDR ADRS L
This chapter contains a description of the Memory

17 777 600-17 777 636

Management register address decoders and of the

reading and writing of the

PAR /PDRs.

SCCB USER PAR ADRS L
17 777 640-17 777 676

PARs and PDRs are loaded (written into) only under program control (with the exception of the W

SCCB MMR3 ADRS L

and A bits in the PDRs). The program may also

17 772 516

read these registers. Both accesses are accomplished
by using appropriate Unibus addresses.

SCCB MMR ADRS L (MMRO,1,2)
17 777 572-17 777 576

7.1

SCCC,

dresses

are

SCCD,

buffered

SCCE,
for

and

various

SCCF.

Ad-

purposes

SCCB SW REG ADRS L
17777 570

SAPH.SSRH and SCCA.

SCCB SWR+MMR ADRS L
17 777 570-17 777 576

Most of the decode signals refer to the Memory
Management registers, but other signals decode the

All these address decode signals are clocked into

address of processor registers.

the

flip-flops on

which

occurs

SCCC

by TIGA

approximately

PSEUDO T3,
after

Table 7-1, at the end of this paragraph, lists the sig-

PAUSE; they are cleared by SCCD INT CLR (Tl

nals that refer to more than one register address.

of BUST). The Memory Management register ad-

dress flip-flops are ORed to generate SCCC INT
The logic on SCCB decodes all the Memory Man-

REG H.

agement register addresses plus the Switch Register
address:

The PAR and PDR flip-flop outputs are ORed on
SCCD:; SCCD APR REG H is asserted when any

SCCB KERNEL PDR ADRS L
17 772 300-17 772 336

PAR or PDR is addressed. The unlatched version

of these same signals, plus SCCB MMR3 ADRS L,
SCCB SWR+MMR ADRS L and SCCE SYS INT

SCCB KERNEL PAR ADRS L
17 772 340-17 772 376

REG

L are ORed to generate SCCD INT REG

ADRS H. This signal is stored in a flip-flop whose

output is SCCD INTD REG (1) L. It is asserted
SCCB SUPER PDR ADRS L
17 772 200-17 772 236

when any one of the registers that are read out on

the Internal Data Bus (INTD) is addressed.

IV-7-1

The logic on SCCE decodes the addresses of the sys-

SCCE PIR ADRS H

tem registers that are located on, or read from, the

17 777 772

SCC module (the two size registers, the ID and the
Trap to 4 Error register) and the addresses of the

SCCE SL ADRS H

processor Control registers (PB, PIR, SL, PS):

17 777 774

SCCE SYS INT REG L

SCCE PS ADRS H

17 777 760-17 777 766

17 777 776

SCCE SYS SIZL ADRS L
17 777 760

It should be noted that PSEUDO T3 is inhibited by
SSRC INH PSEUDO T3 L. This signal is asserted

SCCE SYS SIZH ADRS L

when Memory Management is enabled and a condi-

17 777 762

tion

exists

that

causes

Memory

Management

abort condition. INH PSEUDO T3 thus prevents
SCCE SYS ID ADRS L

changing the contents of the Memory Management

17 777 764

registers during an abort condition caused by a reference to a Memory Management register.

SCCE ERR REG ADRS L
17 777 766

SCCF GEN REG ADRS is asserted for Switch register addresses 17 777 700-17 777 717 (Console GR

SCCE INTERNAL ADRS L

addresses). This signal is clocked into the SCCF

17 777 770-17 777 776

GEN

REG (1) H flip-flop by the LOAD ADRS

switch. The flip-flop is cleared by
SCCE PB ADRS L

CONT switch or by

17 777 770

INIT, by the

a LOAD ADRS to an address

other than a GR address.

Table 7-1
Register Address Decode Signals

Module
SCCB

Signal

Addresses Decoded

MMR ADRS L

MMRO, MMR1, MMR2

SWR+MMR ADRS L

MMRO through 2, Switch Register

SCCC

INT REGH

MMRO through 3, PARs and PDRs

SCCD

APR REGH

PARs and PDRs

INT REG ADRS H

All registers read on Internal Data Bus: MMRO through

INTD REG (1) L

MMR3, PARs and PDRs, Switch Register, System Size L and
H Registers, System ID Register, Traps to 4 Error Register

SCCE

SYSINT REG L

System Size L and H, System ID, and Traps to 4 Error
Registers

INTERNAL ADDRS H

SCCF

PB, PIR, SL and PS Registers

GEN REG ADRS H

General Register addresses from Switch Register (22-bit

GEN REG (1) H

address).

IvV-7-2

7.2

ADDRESSING OF PAR AND PDR REGIS-

TERS FROM THE UNIBUS
7.2.1

selected whenever its own address, or that of the
corresponding PAR are decoded.

PAR/PDR Addresses

7.2.3

PAR/PDR Read

The Unibus addresses for the PARs and PDRs are

The

listed in Table 7-2. The address bit configuration se-

PAF(21:06) H] and/or PDR are input to the multi-

lects a

plexer on SAPM [SAPM APR BIT(15:00) H]. The

PAR /PDR

outputs

of the selected

PAR

[SAPA+B+C

PAR is selected if SAPH VAOS5 is high, and the

Bits (17-06) of a PAR/PDR address de-

PDR if VAOS is low.

termine the set desired:

SAPM APR BIT(15:00) H is in turn input to the In-

KERNEL:

17 772 3xx

SUPER:

17 772 2xx

USER:

17 777 6xx

ternal Bus data multiplexer on SSRJ.
7.2.4

Bit 05 of the address distinguishes be-

PAR Write

A PAR is written at T4 of DATO or DATOB
Pause cycle if TMCE KT BEND L is not asserted.

tween a PAR and a PDR:

There are WRITE LOBYTE and WRITE HIBYTE
PDR:

bit 05=0

write signals for each of the modes (Kernel, Super

PAR:

bit 05=1

and User). Each is gated by an address decode signal [SCCC KERNEL (or

Bit 04 defines I and D space:

H]. by SAPK

SUPER /USER) PAR (1)

WR OK (CI=DATO or DATOB

and not KT BEND), and timed by SAPC PULSE

4.
7.2.2

I SPACE:

bit 04=0

BC9B H (T4 of Pause cycle). Byte information is

D SPACE:

bit 04=1

supphed by SAPK LO and HI BYTE B H, which

are derived from the UBCB functions of the same
name, which decode VA(0O, DATO and DATOB.
The WRITE LOBYTE and WRITE HIBYTE sig-

Bits (03:01) select one of eight registers.
Addressing

nals are low when asserted and enable the W inputs

Address Bits 0-3 - Since SCCC INT REG A L is

to the 3101 As.

low, the A inputs to the multiplexers on SAPK are

selected. SAPK APR ADDR(3:0) and APR AD-

7.2.5

DRA(3:0) are the same as SAPH VA(04:01) B H.

All PDR bits, with the exception of the A and W

PAR

CHIP

manner as the PAR bits. The only difference is that

User

PAR

PDR Write

bits (bits 07 and 06), are loaded in almost the same
SELECT

- The

Kernel,

address decode signals

Super

[SCCC

and

KER-

the gating signals include a PDR instead of a PAR

NEL PAR (1) L, SUPER (1) L and USER (1) L]

address

are selected by the multiplexer and become the CS

KERNEL (or SUPER/USER) PDR (1) H.

decode

signal.

These

signals

are

SCCC

inputs to their respective PARs.
Refer to Chapter 6 for a description of the several
PDR CHIP SELECT - SCCC INT REG H is high

PDR

whenever a PAR or a PDR address is decoded, and

are loaded into the Page Length Field (PLF), BRO3

selects the A inputs to the SAPE KERNEL (or SU-

is loaded into the Expansion Direction Bit (ED),

PER/USER) CS L multiplexer. These three signals

and BR(02:00) are loaded into the Access Control

are the chip select signals for the PDRs.

Field (ACF).

A PDR is

IV-7-3

fields.

During a write operation, BR(15:08)

Table 7-2

PAR/PDR Unibus Addresses
Kernel
I Space

D Space

No.

PAR

PDR

No.

PAR

PDR

17 772 340

17772 300

17 772 360

17772 320

17 772 342

17 772 302

17 772 362

17 772 322

17772 344

17 772 304

17772 364

17 772 324

17 772 346

17 772 306

17 772 366

17 772 326

17 772 350

17772 310

17772 370

17772 330

17772 352

17772312

17 772 372

17 772 332

17 772 354

17772 314

17 772 374

17 772 334

17 772 356

17772 316

17772376

17 772 336

Supervisor
I Space

No.

PAR

1
2

3
4

5
6
7

D Space

PDR

No.

PAR

PDR

17 772 240

17 772 200

17 772 260

17 772 220

17 772 242
17 772 244

17 772 202
17 772 204

1
2

17.772 262
17 772 264

17 772 222
17 772 224

17 772 246
17 772 250
17 772 252
17 772 254
17 772 256

17 772 206
17772 210
17 772 212
17772214
17772 216

17 772 266
17772 270
17 772 272
17772 274
17772 276

17 772 226
17 772 230
17 772 232
17 772 234
17 772 236

5
6
7
User

I Space

D Space

No.

PAR

PDR

No.

PAR

PDR

17 777 640

17 777 600

17 777 660

17 777 620

17 777 642

17 777 602

17 777 662

17 777 622

2
3
4
5
6
7

17 777 644
17 777 646
17 777 650
17 777 652
17 777 654
17 777 656

17 777 604
17 777 606
17777 610
17 777 612
17777 614
17777 616

2
3
4
5
6
7

17 777 664
17 777 666
17777 670
17 777 672
17777 674
17 777 676

17 777 624
17 777 626
17 777 630
17 777 632
17 777 634
17 777 636

IvV-7-4

The A and W bits are written when SAPD WR

The

A+W L is asserted. The upper gate causes this sig-

SAPD WR A+W L is asserted. This sig-

and

bits

are

written

when

nal to be asserted when Memory Management is en-

nal is similar to the PAR and PDR write

abled (RELOC) and an address other than a PAR,

pulses, the difference being the omission

a PDR or MMRO - MMR3 is being referenced.

of byte information and of the address

The lower gate causes WR A+W to be asserted dur-

decode function. SCCD APR REG

ing a write to a PAR or to a PDR.

(=all PARs and PDRs) is the address de-

code signal in this case.
The A and W bits are set to O whenever a PDR or

Thus, the A and W bits of a PDR are

the PAR that corresponds to it is written into:

cleared whenever a
1.

SCCC INT REG B L is low during both

the

above

conditions.

This

SAPD

ATTN

DATA

causes

bit)

and

SAPD WRTN DATA L (W bit) to be
negated

when

the

PDR

the

corre-

sponding PAR is addressed.

IV-7-5

PDR or its corre-

sponding PAR are loaded.

CHAPTER 8
MEMORY MANAGEMENT ERROR HANDLING

A length fault is caused by a memory reference out-

Illegal memory references cause an immediate
abort, i.e., the memory reference is not completed
and an interrupt is sent to the processor. It should
be noted that the instruction containing the aborted
memory reference is not completed.

side the limits set by the Page Length Field and ED
bit of the PDR. It is explained in Paragraph 8.1.
A non-resident fault is caused by an attempted ac-

cess

a prohibited page.

read-only

fault is

Refer to Figure 8-1. Three kinds of faults cause an

caused by an attempted write to a page for which

abort:

only read accesses are allowed. The Access Control

page length violation, non-resident memory

Field (ACF) of the PDR determines the allowable

and read only violation.

BRC14:08>

ADDRESS (CHAPTER

L1
]
PLF

AcF

|pDR
PAR.

AR 83

KEY1 & READ

SAPL

7).

WRITE

KEYS5 8 WRITE

KEY 4

SAPL

[
—»]

BRZ9

SSRD

SOCE

SSRD

MEM MGMT

ENABLE

DET (1) H

MGMT (1) H

CYCLE H

KEY1 & WRITE

CHAPTER 6

TMTM Kkev 2 & WRITE

SAPL
o

READ

ONLY FAULT

>PAR.8.2
L

KEY

KEY 3

—»

KEY 7

SAPL

NON

RESIDENT

SSRD MEM | _ —mca

MGMT

FAULT H

CHAPTER

SAPL
LENGTH

VAC12:06) —————

SAPL
ABORT

FAULT L

PAR’ 8.1

TRAP

|—+|

COND H

SSRC KT
ABORT

|—+>TMCE

FLAG L

1—_

CHAPTER 9

MMRO | 15|14

|13

|12

/ 09
Z

NON RESIDENT —J
ABORT { PAGE LENGTH

ERROR

T———ENABLE TRAP
TRAP

READ ONLY
t1-4020

Figure 8-1

Traps and Aborts

IV-8-1

access modes of a given page. These two faults are

LENGTH FAULT is also ORed with the read-only

described in Paragraph 8.2.

and non-resident faults to generate SAPL ABORT
COND H. This function in turn generates SSRC

Paragraph 8.3 explains the Memory Management

KT ABORT FLAG L, which notifies the processor

traps. Certain access keys in the ACF cause a trap

abort logic of the abort condition. (Refer to Para-

instead of an abort. A trap is only executed at the

graph 8.2).

end of the instruction, and the memory reference
causing the trap is executed.

8.1.2
Finally, the A and W bits are set in the PDR to aid

statistics gathering

the executive program.

lllegal Processor Mode

A length fault occurs if the PSW contains an illegal
processor mode [PS(15:14) = 10].

The A bit is set every time that access to the se-

15:09 of MMRO. Additional information, to help

If this is the case, none of the mode flip-flops on
SSRB are selected, and no PAR/PDR set is selected, since the mode generates the Chip Select input to these registers (refer to Chapter 3). This
causes the output of the PAR to be all ones, SAPD
PGE EXPN DOWN H to be high, and LENGTH

the program determine the origins of aborts and

FAULT to be asserted.

lected page results in a trap condition; the W bit is
set if the page is written into (modified). This mechanism is explained in Chapter 6.
Information on aborts and traps is stored in bits

traps, is stored in the remaining bits of MMRO as
well as in MMRI, MMR2, and MMR3. Chapter 9

8.2

describes these registers.

TRAPS

All aborts and traps generated by Memory Management are vectored

through

Kernel

space address

ACCESS CONTROL FIELD ABORTS AND

8.2.1 Non-Resident and Read-Only Protection
A Page Descriptor Register (PDR) is selected in the
same manner as a Page Address Register (PAR).

250.

mine whether it falls within the selected page. If it

After the selection occurs, three bits from the PDR
are decoded as an access key. If the access rights
designated by the key are inconsistent with the current memory reference, the memory reference is not
completed and an abort to Kernel space 250

does not, the VA is illegal and the instruction is

occurs.

8.1

PAGE LENGTH ABORTS

When Memory Management is enabled, i.e., in 18-

or 22-bit mapping, the VA is examined to deter-

aborted. An illegal processor mode [PS(15:14)=10]

When the access key is set to 0, the page is defined

also causes a page length abort.

as non-resident, and an abort prevents any attempt
8.1.1

Length Fault

SAPL

LENGTH

FAULT

are

by a program to access a non-resident page. Using

FAULT L and MM
asserted

when

LENGTH

VA(12:06)

this

feature to provide memory protection, only

(block

those pages associated with the current program are

number) is greater than the PLF and the expansion

set to legal access keys. The access control keys of

is upward (SAPL PGE EXPN DOWN L is not as-

all other program pages are set to 0, which prevents

serted, or ED = 0), or when VA(12:00) (block num-

illegal memory references.

ber)

less

than

the

PLF

and

the expansion

downward (SAPD+E+F PGE EXPN DOWN H is

The access control key for a page can be set to 2, al-

asserted, or ED = 1).

lowing read memory references to the page, but
aborting any attempt to write into the page. This

SAPL LENGTH FAULT L is stored in bit 14 of

read-only type of memory protection can be given

MMRO (SSRC MMRO BIT 14). (Refer to Chapter

to pages that contain common data, subroutines, or

9).

shaded algorithms. This type of memory protection

IvV-8-2

makes certain that access rights to a given informa-

KT ABORT FLG is the input to the SSRC ABT

tion

access

FLG flip-flop, which is clocked by SSRK PULSE

right to a given information module may be varied

BC89 H (=TS3 of Pause cycle) and latches SSRC

module

are

user-dependent,

i.e.,

the

for different users by altering the access control

KT ABORT

key.

UBCB ABORT ACKN H.

A PAR in each of the sets (Kernel, User, and Su-

8.3

pervisor

modes)

FLG

L. The flip-flop is cleared by

MEMORY MANAGEMENT TRAPS

may

be set up to reference the

A timeshared system swaps programs, or parts of

same physical page in

memory and each may be

programs, in and out of memory using secondary

keyed for different access rights. For example, the

storage facilities such as disk systems. In a swap-

User access control key might be 2 (read-only ac-

ping environment, the operating system must provide

cess), the Supervisor access control key might be 0

the software routines that decide which programs

(non-resident), and the Kernel access control key

should be swapped and when and how these pro-

might be 6 (allowing completer read/write access).

grams can be swapped between memory and secondary storage.

8.2.2

Access Faults (Aborts)

The Access Fault (ACF) is decoded on SAPL to de-

The

tect abort and trap conditions.

complex

Non-resident (key = 0) and unused keys (3 or 7)

The

cause SAPL NON RES FAULT L to be asserted

which active page is least likely to be required in

operating

system

routines can

depending on

system

be simple or

requirements, e.g.,

the amount of overhead time that can be tolerated.
operating

system

may

also

have

decide

and stored in bit 15 of MMRO (SSRC MMRO BIT

the

15).

swapped out to make memory space available for a

immediate

future

and

may

therefore

new program.

If PS(15:14) contain 10 (illegal mode), none of the
mode

flip-flops

SSRB

are

selected,

and

PAR/PDR set is selected, since the mode generates

the Chip Select input to these

registers (refer to

To make such

Memory

Management decision,

the operating system requires statistics on the use

of active pages. Some indication of whether a pro-

Chapter 3). This causes the output of the PDR to

gram

be all 1s. The ACF is thus 7 and SAPL NON RES
FAULT L is asserted.

memory is also desirable. If it has been modified,

SAPL WRITE CYCLE H is asserted when the bus

has

been

modified

during

its

residence

the program must be swapped (rewritten) into secondary storage. If no modification has been made,
and the program can always be recalled from sec-

cycle is either a DATO, a DATOB, or a DATIP. It

ondary storage, the space it occupies in memory

can

used

detect

all

write or read/modify/write

overlayed,

thus eliminating

the swapping

(DATIP followed by DATO or DATOB) cycles.

delay.

WRITE

The logic provides the kind of information required

write

CYCLE

keys

ONLY

and

FAULT,

ANDed
2)

which

with

both

abort-on-

generate

SAPL

stored

READ

bit

MMRO (SSRC MMRO BIT 13).

The non-resident and read-only fault decoders are
ORed with SAPL LENGTH FAULT (refer to Para-

graph 8.1) to generate SAPL ABORT COND H.
8.2.3

Abort Flag

SAPL

ABORT

by an operating system to gather Memory Management statistics on the use of active pages. The availability of this information in the hardware reduces
the overhead time of any routine, simple or com-

plex, in the efficient management of memory.

The Page Descriptor Register associated with each
active page includes a W (written into) and an A
(attention) bit.

COND

asserts

SSRC

ABORT FLG L (which informs the abort logic on
TMCE that a Memory Management abort condi-

tion has been detected) if RELOC is asserted, and
if the cycle is not a BEND.

When

any active page is written

into, the W bit is set by the logic; therefore, by testing the W bit, the Memory Management software

routine can decide whether a page can be overlayed
or if it needs to be swapped out (e.g., copied onto a
disk).

1V-8-3

The A bit has several uses. To use this feature, the
system programmer may enable the Memory Management trap logic. He then sets the access control
keys of the active pages of interest for special trap
conditions. Access control keys are provided to
cause:

Memory Management trap on read (including instruction fetch)

2.
3.

Memory Management trap on write
Memory Management trap on read or
on write.

The A bit for the active page is then set when the
page is accessed and a Memory Management trap
condition occurs. The vector at trap location 250
Kernel address space causes the operating system
routine to service the Memory Management trap.

The routine can test the A bit to accumulate statistics on the use of that page. When a swapping decision is required of the operating system, these
statistics can be examined to determine the more active pages (which might therefore be retained in
memory).

Access Control Traps

Keys 1, 4, and 5 of the ACF are examined to determine whether a trap condition exists.. The following functions are generated:

These three functions are ORed to generate SAPL
MEM MGMT H which is stable by the end of TS

of a BUST cycle. If Memory Management is enabled (SSRE RELOC H) and if the address is not a
Memory Management register (SCCC INT REG
L), then SSRD CLK TRAP H is asserted.
Refer to Figure 8-2. If bit 9 of MMRO [SSRD ENABLE MGMT (1) H] is set, and if the abort flag is
not set, and if SSRD MGT TP DET DLY L is not
asserted (see below), SSRD MEM MGMT TRAP
L is asserted via its “‘pre-Mem Management Trap”
gate. This occurs during a Pause cycle, and if
TMCE BRQ CLK H is asserted (at TS3) during
this cycle, MEM MGMT TRAP is clocked into the
priority flip-flop on TMCA.

At SSRK PULSE BC89 H (which occurs at TS3 of
every Pause cycle), and if there are no abort conditions, SSRD MEM MGMT B L is asserted and
sets SSRD MEM MGMT DET (1) H, which is bit
12 of MMRO. At the same time, if MMRO bit 9 is
set, and if SSRD MGT TP DET DLY L is not asserted, SSRD MGMT HOLD L sets the latch flipflop. This flip-flop keeps SSRD MEM MGMT
TR AP L asserted; it is cleared when the trap is acknowledged by the processor trap logic or until a
Memory Management abort is detected.
This hold Nip-flop is necessary because, 50 ns after
SSRD MEM MGMT DET is set, SSRD MGT TP
DET DLY L is asserted and disables the “pre-Mem
Managment TrapTM input gate to SSRD MEM

MGMT TRAP L. This gate stays disabled until the

program clears the MEM

MGMT DET flip-flop

cycle (DATO, DATOB or DATIP).

(MMRO bit 12) by writing a 0 into it. The A and
W bits are clocked at T4 of Pause (PULSE BC9D).

SAPL KEY=4 L = key 4 on read or write.

The logic thus ensures that only one trap can be

SAPL KEY=5WR L = key 5 during a write

sensed per instruction, and that no subsequent trap
can be clocked by the TMCA logic until the program has reset bit 12 of MMRO.

SAPL KEY=1.WRI L= key | during a write

cycle.

1V-8-4

-—

PAUSE
T1+120n8

+150ns

SSRK PULSE BC89 H

SSRD MEM MGMT TRAP L

SSRD MEM

MGMT B L

SSRD MEM MGMT DET

MGT TP DET DLY L

NN\

(PRE-MEM MGMT TRAP)

NN
Y

SSRD

(1)L

SSRD MGMT HOLD (1) H

SAPD WR A+W L
11-4022

Figure 8-2

Trap Timing

IV-8-5

CHAPTER 9
MEMORY MANAGEMENT REGISTERS
(MMRO, 1, 2, AND 3)

Aborts and traps generated by the Memory Man-

This paragraph first defines the meaning ofthe vari-

agement hardware are vectored through Kernel vir-

ous

tual location 250. Memory Management Registers

these bits.

bits

MMRO,

then

the

logic that controls

0. 1, 2, 3 are used in order to distinguish an abort

from a trap, to determine why the abort or trap oc-

curred, and to allow for easy program restarting.

Setting bit 0 of this register enables address reloca-

Note that an abort or trap to a location which is it-

tion and error detection. This means that the bits in

self an invalid address will cause an-other abort or

MMRO become meaningful.

trap. Thus, the Kernel program must ensure that
Kernel VA 250 is mapped into a valid address, or a
loop

will

occur

which

will

require

console

Bits 15-12 are the error flags. They may be consid-

intervention.

cred to be in a “*priority queue” in that “flags to

the rightTM are less significant and should be ignored
9.1

MMRO

il more than one of them is set; i.e., a “non-resi-

contains

error

flags,

the

page

number

dentTM fault service routine would ignore length, ac-

whose reference caused the abort, and various other

cess control,

status flags. The register is organized as shown in

‘page lengthTM service routine would ignore access

Figure 9-1. Its address is 17 777 572.

control and Memory Management faults, etc.

SSRD

and

Memory

Management flags.

SSRC

SSRD
aSRC
1

ABORT-NON RESIDENTJ
J

LENGTH ERROR
ABORT— PAGE

)

ABORT-READ ONLY
ACCESS VIOLATION
TRAP-MEMORY MANAGEMENT

NOT USED
NOT USED

ENABLE MEMORY MANAGEMENT TRAP
MAINTENANCE MODE

INSTRUCTION COMPLETED
PAGE MODE

PAGE ADDRESS SPACE

1/D

PAGE NUMBER

ENABLE RELOCATION
11-4046

Figure 9-1

IV-9-1

MMRO

Bits 15-13 when set (error conditions) cause Memory Management to freeze the contents of bits 1-7
and of Registers 1 and 2. This is done to facilitate
€rror recovery.

These bits may also be written under program control. No abort will occur, but the contents of the
Memory Management registers will be locked up as
in an abort.

Bits 15-12 are enabled by SSRE RELOC. RELOC
is true when an address is being relocated by the
Memory Management unit. This implies that either
MMRO, bit 0 is equal to | (Relocation operating)
or that MMRO, bit 8 (Maintenance) is equal to |
and the memory reference is the final one of a destination calculation (Maintenance/Destination
mode).

Bits 11 and 10 are spares. They are always read as
0, and should never be written. They are unused
and reserved for possible future expansion.
Bit 9 is the “Enable Memory Management Traps”
bit. It is set or cleared by doing a direct-write into
MMRO. If bit 9 is 0, no Memory Management
traps will occur. The A and W bits will, however,
continue to log potential Memory Management
trap conditions. When bit 9 is set to 1, the next
Memory Management trap condition will cause a
trap. vectored through Kernel VA 250.

Note that if an instruction which sets bit 9 to O (disable Memory Management Trap) causes a Memory
Management trap condition in any of its memory
references, prior to and including the one actually
changing MMRO, then the trap will occur at the
end of the instruction.

9.1.1

Aborts

Bit 15 is the ““Abort-Non-Resident’ bit. It is set by
attempting to access a page with an Access Control
Field (ACF) key equal to 0, 3, or 7. It is also set by
attempting to use Memory Relocation with a pro-

The trap logic is described in Chapter 8.
9.1.3

Maintenance/Destination Mode

Bit 8 specifies that only Destination mode references will be relocated using Memory Management.

cessor mode of 2. [PS(15:14)=10].

This mode is only used for maintenance purposes.

Bit 14 is the ‘““‘Abort-Page-Length” bit. It is set by
attempting to access a location in a page with a
block number (VA bits, 12-6) that is outside the
area authorized by the Page Length Field (PLF) of
the Page Descriptor Register (PDR) for that page.

Bit 14 is also set by attempting to use Memory Relocation with a processor mode of 2.
Bit 13 is the “Abort-Read-OnlyTM bit. It is set by attempting to write in a “Read-Only” page. *“‘ReadOnlyTM pages have access keys of | or 2.
The logic that generates these aborts is explained in

Refer to Chapter 4.

9.1.4

Instruction Complete

Bit 7 indicates that the current instruction has been
completed. It will be set to | during T bit, Parity,
Odd Address, and Time Out traps and interrupts.
This provides error-handling routines with a way of
determining whether the last instruction will have
to be repeated in the course of an error recovery attempt (after an abort). Bit 7 is Read-Only (it cannot be written). Note that EMT, TRAP, BPT, and
IOT do not set bit 7.

Chapters 8 and 9.

Bit 7 [SSRE INSTR COMP (1) H] is set by SSRA
9.1.2 Traps and Trap Enable
Bit 12 is the “Trap-Memory Management” bit. It is

BRK .30 (1) H if there has been no previous Memory Management abort condition. [SSRC ND ER-

set whenever a Memory Management trap occurs;

ROR

that is, a read operation which references a page
with an Access Control Field (ACF) of 1 or 4, or
by a write operation to a page with an ACF key of

asserted at SSRK PULSE23 H (TS2) when the out-

equal

4 or 5.

(Flows 12).

(1)

none of bits

15:13],

BRK.30 is

put of the Memory Management ROM bits 03:00

IV-9-2

100:

this occurs during the

BRK.30 cycle

Bit 7 is cleared, if there is no abort, at TS3, when a

9.1.6

new instruction is fetched (SSRH LOAD IR H =

Bit 4 indicates the type of address space (I or D)

UIRK asserted).

the

Address Space and Page Number

unit

Space, |

was

when

abort occurred (0 =

= D Space). It is used in conjunction with

bits 3-1, Page Number.

The

following

conditions

may

occur

during

the

course of program execution:

Bits 3:1

contain

causing a

If the first abort is

a Memory Manage-

the page number of a

Memory

Management fault.

reference

Note that

pages, like blocks, are numbered from 0 upwards.

ment abort, NO ERROR clears at T4 of
PAUSE,

before entry

Flows.

Therefore,

into

the Service

SAPK IND DATA H is stored in bit 4 of MMRO.

INSTRUCTION

The SSRB space flip-flop that is asserted during a

COMPLETE is not set by BRK.30.

given

cycle

gates

the

Space information

from MMR3 [SAPK D S K (or S/U), H] to gener-

If the

first

(and

only)

abort

not

ate this signal. The SAPK D S signals are described

Memory Management abort, INSTRUC-

in Chapter 3.

TION COMPLETE is set by BRK.30,
but is cleared by FET.00 (217) at the be-

Bits 03:01

ginning of the instruction fetch sequence

which give the address of the selected

(after the pushes to the stack have been

set.

of MMRO are loaded with VA(15:13),
PAR/PDR

successfully executed).
9.1.7

Enable Relocation

If the first abort is not

a Memory Man-

Bit 0 1s the “Enable RelocationTM bit. When it is set

agement

INSTRUCTION

to 1. all addresses are.relocated by the unit. When

abort,

then

COMPLETE is set at BRK.30 (because

bit 0 is set to 0, the Memory Management Unit is

NO ERROR is set). If a Memory Man-

inoperative and addresses are not relocated or pro-

agement

abort

then

occurs

during

the

tected. Chapter 4 explains the logic associated with

Service Flows, NO ERROR is cleared at

this bit.

T4 of PAUSE. This prevents INSTRUC-

TION COMPLETE from being cleared

9.1.8

until the abort condition bits in MMRO

MMRO

are

Data Bus through the multiplexer on SSRJ. Refer

cleared.

this

case,

MMR2 con-

tains either a vector address or the stack

Read/Write Under Program Control
is

read

the processor on

the Internal

to Section I, Chapter 2.

pointer, and not a program address.

Bits 00, 08, 09, and 12:15 can be written into by the
program from the BR.
9.1.5

Processor Mode

Bits

mode

Refer to Figures 9-2 and 9-3. SCCB MMR ADRS

(User/Supervisor/Kernel) associated with the page

L decodes the addresses of MMRO - MMR2. At

causing the abort. (Kernel = 00, Supervisor = 01,

TIGA PSEUDO T3 H, it is clocked into the SCCC

User =

indicate

the

CPU

1) If an illegal mode (10) is specified, bits

15 and 14 will be set and an abort occurs.

SSR

REG flip-flop, whose output is ANDed with

TMCE CI

to generate SCCC WRITE MMRO

REG H [MMRO is the only writable register of the

threce (MMRO0-2)]. Since the address of MMRO Bits 05 and 06 of MMRO show the actual Processor

MMR?2 differ only by bits 02 and 01

mode [as decoded by SSRB MMRO MODEO (and

this

dicates a write to MMRO, and selects the A inputs

from

the mode flip-flops]. The actual

mode

signal,

when

NANDed

with

of the VA,

VA(02:01),

in-

may not be the same as that shown by PS(15:14).

[BR(15:13)] to the multiplexer input to the SSRC

Refer to Chapter 3.

MMRO BIT(15:13) flip-flop.

IvV-9-3

—15

T\, SSRH VAg2CL—
TTMCE CIH—___/

SCCB MMR ADRS L

|14

SAPL ABORT LOGIC

SCCC MMR REG (1) H

L SCCC WRITE MMR@ REG H

TIGA PSEUDO T3 H—

SSRB MMR@ MODE1 H

am":g“"‘f‘“

SSRH VA@2 C L —

SSRH VAg1 ¢ H—T|

SSRB MMR® MODE® H—

SSRC WRITE MMR@ HIBL
SSRC STROBE ENABLE H

‘

UBCB HI BYTE H —

>_L__

SAPK IND DATA H—l

04
|

—

SSRH VA15:13> H{—-—

SSRK PULSE

SSRC CLK MMR@ HIB H

02
—O1

BCB9 H

TMCE KT BEND L —

SSRE RELOC H—
SSRC NO ERROR (1) H—

SSRE

SCCC INT REG B L —

‘

STROBE OK L

I—ssm—: STROBE OK H

BR12—
c

BR@9

BR@S—

l—ssao

MMRZ HIB CLK L

UBCB HiI BYTE H—
SSRK TS3 H—
TMCE PAUSES B H-—

L 00

BROYE —|
[-ssm-: MMR@ LOB CLK L
L

UBCB LO BYTE H—

SSRK PULSE 23 H—

TMCE PAUSES B H—

11-4014

Figure 9-2

Clocking of MMRO

1V-9-4

TIGA PSEUDO

.
A

B )

PAUSE

TIGE

TS3
SSRK PULSE

SSRK

BC89 H

PULSE

23 H

SCCC WRITE MMRZ REG H}
SSRE WRITE MMR{Z H
SCCC INT

REG

CLOCK BITS 1,5:13-—T

CLOCK BIT 99
CLOCK BITS 08,09,12,06 : 01
f1-4021

Figure 9-3

MMRO Write Timing

SSRE WRITE MMRO H is the same as the multiplexer seleet: signal, but not inverted.

there has been no previous Memory Management
abort condition (SSRC NO ERROR), if no Memory

Gated
SSRK

with

UBCB

PULSE

BYTE

and

BC89

(TS3

Management register is being read or written

(SCCC INT REG B L not asserted), and if TMCE
KT BEND is not asserted.

PAUSE), it clocks the output of the mul-

tiplexer [SSRC PRE MMRO BIT(15:13)

SSRE STROBE OK is gated with SSRK

H] into MMRO bit 15:13 at T3.

BC&Y H (TS3).

NANDed

BYTE

and SSRK

TS3

the abort bits from SAPL are gated into

H, it clocks BR12, 09 and 08 into the

bits 15:13 of MMRO (since the register is

corresponding bits of MMRO at TS.

not

TMCE

with

PAUSES

UBCB

PULSE

On the leading edge of the pulse, at T3,

being

read

written,

the

multi-

plexer select signal is high, and the B in3.

NANDed
TMCE

with

UBCB

PAUSES

LO
H

BYTE

and

puts are selected).

SSRK

PULSE 23 H (TS2), it clocks BROO into

On the trailing edge of the pulse, at TS5,

bit 00 of MMRO at T4.

bits 06 - 01 are clocked into MMRO.
9.2

9.1.9

Bits

Bits Controlled by Memory Management

MMRI

MMRI1

15:13 are also clocked automatically on abort

records

any

autoincrement/decrement

the general-purpose registers. MMRI is cleared at

conditions. Bits 06:01 are clocked on every memory

the beginning of each instruction fetch if no abort

reference. but cannot be changed once an abort bit

condition

is present.

(15:13) 18 set.

cither

Whenever a general-purpose

autoincremented

autodecre-

mented, the register number and the amount (in 2’s
SSR1- STROBE OK is asserted when Memory Man-

complement

agement is enabled (SSRE RELOC is asserted), if

modificd, is written into MMRI.

IV-9-5

notation)

which

the register was

The information contained in MMRI is necessary

Bits 03:00 of the Memory Management

to accomplish an effective recovery from an error

ROM

resulting in an abort. The low order byte is written

autoincrement

informs the MMRI logic of the

first and it is not possible for a PDP-11 instruction

ement causes

decrement.

decr-

a ROM output of 011, an

two gen-

increment an output of 010. SSRA ONE

cral-purpose registers per instruction (refer to Sec-

CHANGED (1) H is asserted when the

autoincrement/decrement

more than

tion 1. Chapter I). Only three bits are available to

ROM output is either 010 or 011. SSRA

record the register number; thus, it is up to the soft-

AUTO DEC is asserted when the output

ware

registers

is 011. This signal supplies the sign bit

0/General

to the increment/decrement value.

determine

which

set

(User/Supervisor/Kernel-General
Set

Set

1) was modified, by determining the CPU and

Memory

Management abort

[SSRC

displacement on R6 (SP) that can be caused by the

NO ERROR (1) H not asserted], latches

MARK

the contents of MMRI.

instruction cannot occur if the instruction

is aborted.

MMRI1 and ONE AUTOED are both cleared, if no
MMRI

is read on the Internal Data Bus through

the multiplexer on SSRJ. Its address is 17 777 574,

Memory

Management

aborts

have

oc-

curred (NO ERROR),

Refer to Section I, Chapter 2.

FFigure 9-4 shows the format of MMRI. Its logic is

during an

instruction

LOAD

IR), or

during

the

fetch (SSRH

on drawing SSRF.

2.
.

The register number is taken
General

address

from the

bits,

Service

Flows

(SSRA

BRK.30), or

GRAC

GRA(3:0) L and are encoded to fall in

if INIT is asserted.

the range of 0 - 7. Refer to Section II,
Chapter 2 of this manual (Data Paths).

For the first increment or decrement, SSRF ONE
AUTOED (0) H is high (the flip-flop is cleared). At

The amount of the increment or decr-

TSB.

ement is that shown by the KOMX multi-

SSRA

if there is a change to the register, and if

plexer input to the ALU. This logic is

change to the register and the register number are

described in the same chapter as the Gen-

written

cral

07:00).

address

bits.

The

multi-

ONE
into

CHANGED
the

low

(1)

order

asserted,

byte of MMRI

the
(bits

plexer to which they are input selects the

complement of the KOMX

if the cycle

The ONE AUTOED flip-flop is then clocked by

calls for a decrement.

AMOUNT CHANGED

(2's COMPLEMENT)

the trailing edge of TS and its (1) output goes high.

1110

NUMBER

AMOUNT CHANGED

(2'S COMPLEMENT)

NUMBER

11-4042

Figure 9-4

MMRI1

IV-9-6

Thus, if there is a change to another register during

9.5

the same instruction, it will be stored into the high
order byte (bits 15:08) of MMRI1.

Once an abort has occured, any subsequent errors

MULTIPLE FAULTS

that occur will not affect the state of the machine.
The information saved in MMRO - MMR2 will al-

9.3

ways refer to the first abort that it detected. How-

MMR2

MMR2 is the VA Program Counter. (Refer to Figure 9-5.) It is loaded with the 16-bit VA at the beof each instruction fetch, or with the

ever, when multiple traps occur, the information
saved will refer to the most recent trap that

ginning

occurred.

address Trap Vector at the beginning of an interrupt, “T” Bit trap, Parity, Odd Address, and Timeout traps. Note that MMR2 does not get the Trap

the same instruction, only one stack operation will

Vector on EMT, TRAP, BPT and IOT instructions.

occur: and the PC and PS at the time of the abort

MMR2 is Read-Only; it cannot be written.

will be saved.

In the case that an abort occurs after a trap, but in

MMR?2 is loaded at TS4, if there has been no previous Memory Management abort, when the IR is

9.6

loaded

Refer to Figure 9-6. MMR3 enables or disables:

during

BRK.30 cycle.

instruction

fetch,

during

the

MMR3

Note that the EMT, TRAP, BPT

and 10T instructions do not use the BRK.30 cycle.

The

use

of the

space

PARs

and

PDRs,

MMR?2 is shown on drawing SSRH. Its address is
17 777 576. It is read on the Internal Data Bus

22-bit mapping,

Unibus Map mapping.

through the multiplexer on SSRJ. Refer to Section
1. Chapter 2.

9.4

CLEARING

STATUS

REGISTERS

FOL-

LOWING TRAP/ABORT

At the end of a fault, service routine bits 15-12 of
MMRO must be cleared (set to 0) to resume error

checking. On the next memory reference following
the clearing of these bits, the various registers will
resume monitoring the status of the addressing oper-

ations, MMR2 will be loaded with the next instruction

address.

MMRI1

will

store

change

information and MMRO will log Memory Manage-

ment status information.

When D space is disabled, all references use the |
space registers: when D space is enabled, both the |
space and D space registers are used. Bit 0 refers to
the User's Registers, bit 1 to the Supervisor’s and
bit 2 to the Kernel's. When the appropriate bits are
sct, [ space is enabled: when cleared, it is disabled.
Bit 03 is rcad as zero and never written; it is re-

served for future use. Bit 04 enables 22-bit mapping. Il Memory Management is not enabled, bit
04 is ignored and 16-bit mapping is used.

.
1

11-4041

Figure 9-5

MMR2

ENABLE UNIBUS MAP

0
MMR3

ENABLE 22-BIT MAPPING
KERNEL

SUPERVISOR
USER
{1-4040

Figure 9-6

MMR3

IV-9-7

If bit 4 is clear and Memory Management is enabled (bit 0 of MMRO is set), the computer uses
I8-bit mapping. If bit 4 is set and Memory Management is enabled, the computer uses 22-bit mapping.
Bit 5 is set to enable relocation in the Unibus Map:
the bit is cleared to disable relocation. Bits 6-15 are

unused. On initialization this register is set to 0 and
only I space is in use.

MMR3 is loaded from BR(05:00) by SCCL MMR3
CLK L [=T4+15 ns of PAUSE during a write
cycle and the address decode, SCCC MMR3 (1)
H].

MMR3 is shown on drawing SCCL. Its address is
17 772 516. It is read on the Internal Data Bus
through the multiplexer on SCCH. Refer to Section
1. Chapter 2.

The

following

table

summary

of these

conditions:

Bit

State

Unibus Map relocation disabled

Unibus Map relocation enabled

Operation

Enable 18-bit mapping if bit 0 of
MMRO is set

Enable 22-bit mapping if bit 0 of
MMRO is set

Enable Kernel D Space

Enable Supervisor D Space

Enable User D Space

IV-9-8

SECTION V
UNIBUS MAP

Unless otherwise indicated, references within this section pertain to this section only.

SECTION V

UNIBUS MAP

CONTENTS

Page
CHAPTER 1

GENERATION OF THE PHYSICAL ADDRESS

1.1

CONSTRUCTION OF

1.2

1.3
14

ADDER
. . .
ADDRESSING LIMITS
. . . . .

CHAPTER 2

UNIBUS/CACHE INTERFACE

2.1

2.6

UNIBUS DATACYCLE
DATOORDATOB
. .
DATIORDATIP
. . .
ENDOFDATA CYCLE
PARITY ERROR
. . .
CACHE TIMEOUT . . .

CHAPTER 3

READING AND WRITING THE MAPPING REGISTERS

3.1

READING AND WRITING MAPPING REGISTERS

2.2
2.3
2.4

2.5

3.2
3.3
34

3.5

APHYSICALADDRESS
. . . . . . .

.
.
.
.
.
.

. ... ... ... ... ........

e e
e

. . . . i it it i
e
. .
e e
.
e e et
. . . . . i
i
e
.
i
. .
it it e

et e e et e e et i e e

e e
e

V-1-2
V-1-2
V-1-2

e e e
e e
s
e e e e
e
e e
it e e
e
e e
e e
et e
e e

V-2-1
V-2-5
V-2-5
V-2-6
V-2-6
V-2-6

.. ... .........
e e e e e et e e e e
e e e e e
e e

V-3-1
V-3-2
V-3-2
V-3-3
V-3-3

e e
e e e e
e
e
e e e e e e e e e e e

e
et
e e
e e
e
e e

e e e et e e e
e e
e e e et
e e e e e et e e
e e e e e e e
e e
e e
e
e e e e e e e e e

. .. ..
REGISTER SELECTION
. . . . . . .
e et e
DATO
. . . .
e e e
e e e e e
e e e
e
7.
N
REGISTER ACCESS . . . . . . i i i
e e e e e e e

V-1-1

e
e

e e e e e e

e as

ILLUSTRATIONS

Title

Figure No.
11

Construction of the PA

2-1

Unibus Map Flowchart . . . .
Unibus Map Block Diagram
.
Unibus Map Interface
. . . .
Cache/Unibus TransactionsS
.
Addressingof UBMap Register
UB Map Register Read/Write .

22
2-3
2-4
3-1

3-2

Page

. . . . . . . . . . .

.
.
.
.

. .
. .
. .
. v
. .
. ..

V-1-1

. .. .
o
i
i e
... ... ... . i
. .
o i i
e
e
v v v v v v v e e e e e e e e e e e e e e e e
e
. . . . . .. ... . i
... .....e
e e e e e e e e e e e e e e e e e

V-2-2
V-2-3
V-24
V-2-5
V-3-1
V-3-2

TABLES

Title

Table No.
3-1

. . . . . . . . . . . . . 0
Access to Unibus Map Registers
. . . . . . . .. .

Page

Unibus Data Selection

Viiii

e
e
vttt i i

V-3-3
V-3-4

INTRODUCTION

The

Unibus

The Unibus Map is the interface to memory from

Map

the

interface

between

the

Unibus and Cache. It responds as a slave device to
Unibus

signals

and

converts

18-bit

Unibus

the Unibus. The operation is transparent to the
user, 1f it is disabled.

ad-

dresses to 22-bit Cache addresses.
The reader of this section should be familiar with
the concepts related to PDP-11/70 Address Space.
The

Introduction

(Memory

Section

of this

manual

Management) describes PDP-11/70 Ad-

dress Space in detail.

Relocation Disabled

If the Unibus Map relocation is not enabled, an incoming

18-bit Unibus address has 4 leading zeros

added

for

referencing

22-bit

Physical

Address

(PA). The lower 18 bits are the same. No relocation
is performed.

The top 4K word addresses of the 128K Unibus addresses are reserved for CPU and I/O registers and
are called the Peripherals Page (see Figure I-1). The
lower 124K addresses are used by the Unibus Map

to reference physical memory.

Relocation Enabled
There are a total of 31 mapping registers for address relocation. Each register is composed of a
double 16-bit PDP-11 word (in consecutive locations) that holds the 22-bit base address. These reg-

17 777

isters have Unibus addresses in the range

777

PERIPHERAL
PAGE

(4K WORDS)

17 760 000
17 757

17 770

200-17 770 372.

If Unibus Map relocation is enabled, the 5 high or-

777

der bits of the Unibus address are used to select

124K

one of 31 mapping registers. The low order 13 bits
of the incoming address are used as an offset from

(TO UNIBUS MAP)

the base address contained in the 22-bit mapping
register. To form the PA, the 13 low order bits of
the Unibus address are added to 22 bits of the se17 000

lected mapping register to produce the 22-bit PA.

000

The lowest order bit of all mapping registers is always

11-4051

zero,

boundaries.

Figure I-1

Unibus Address Space

V-I-1

since

relocation

is always on

word

The Unibus Map is disabled upon the occurrence
of any of the following:
I.

Power-up

Depressing the START switch on the
Console, and

The execution of a RESET instruction.

These all cause the assertion of INIT, which clears
MMR3. It should be noted that after a power-up
the contents of the mapping registers are not
defined.

There are 32 mapping registers which may be written and read. These registers are 21 bits wide, and
require two Unibus transactions for each read or
write; 64 addresses on the I Page (17 770 200 - 17
770 376) are thus allotted to them. The contents of
the mapping registers are added to the Unibus address during the relocation process. It should be
noted that the last mapping register (addresses 17
770 374 and 17 770 376) can be read and written,
but cannot be used to map Unibus addresses because it would be used by addresses in the range of
17 760 000 - 17 777 777, the upper limit jumpers
cannot recognize these as valid Cache Unibus addresses. Refer to Chapter 4.

V12

CHAPTER 1

GENERATION OF THE PHYSICAL ADDRESS

Relocation expands the

18-bit Unibus address to

that the mapping box does not know if a byte oper-

the 22-bit Main Memory address. This allows the

ation

Unibus to access any location in Main Memory.

required.

is being executed, and if so, what byte is

-This relocation, or mapping of addresses, is done

by adding the contents of one of the mapping regis-

Refer

ters to bits (12:01) of the incoming Unibus address.

Unibus address select which register a device is us-

Figure

1-1.

Bits

(17:13)

of the

18-bit

ing. The remaining bits (12:00) of the Unibus ad1.1

CONSTRUCTION

PHYSICAL

ADDRESS

dress act as an offset into the page to which the
mapping register is pointing.

All mapping registers in the Unibus Map are 21
bits wide. A “22nd” bit, which is not writable and

When an address is taken off the Unibus, the map-

is always read as a zero, acts as the lowest order bit

ping register is automatically selected and the con-

for cach register. Each register specifies the 21-bit

tents read out.- That 21-bit address is added to the

Physical Address (PA) of a 4K page residing on

13-bit offset in the Unibus address to form the PA.

any word boundary in memory. The reason for us-

This mapping function is very similar to that per-

ing

formed by Memory Management.

boundaries

the

mapping

registers is

BUS A (17:00) l

BUS
A (17:13) select

one of 32 Mapping

Registers, 00—37,

ooL
b

MAPH

b |

—11
b

MAPL

ADDER

MAPE

word

CACHE ADDRESS Ll

\V4

01 00

MAPE CA (21:01) H, MAPA CAOO H
11-4029

Figure 1-1

Construction of the PA

V-1-1

The program controls this process both by selecting

the contents of the mapping registers and by its abil-

ity to enable and disable the Unibus Map relocation function.

The Unibus address lines, BUS A(17:00) L are received by the Map. The output of their bus receiv-

ers is labeled MAPA ADRS(17:01) H and MAPA
CAO00 H. Address bit 0 is always transmitted, unmodified, to the Cache, since the Map ignores byte

One of 16 registers is selected by MAPA
ADRS(16:13) H via the multiplexer on MAPC.
MAPC INDA(4:1) H address the mapping register
that is being selected.
1.3

ADDER

The Adder consists of the five 745181 ALU ICs,
and the full adder circuit for bit 21 shown on
MAPE.

instructions.

When MAPD ENAB MAP H is negated, the incoming Unibus address is transmitted, unmodified,

The address used by the Cache during a data transaction consists of MAPA CAO00 H, the output of
the Map receiver for BUS A00 L, and of MAPE
CA(21:01) H. These bits are the output of a 21-bit

through the Adder.

gated. The state of this signal reflects that of SCCL

When MAPD ENAB MAP H is asserted, the Adder is enabled. In this case, bits 01 - 12 of the address are added to bits 01 - 21 of the selected
mapping register (adder function A plus B). The
output of the Adder then goes to the Cache as the

ENAB

PA.

adder which is enabled when MAPD ENAB MAP
is asserted, and disabled when ENAB MAP is ne-

MAP

H (bit 5 of Memory Management

’

When the adder is disabled, its output is the same
as the incoming Unibus address, with bits 18 - 21
equal to 0.
Refer to

Figure

1-1. When the adder is enabled,

bits 17 - 13 of the Unibus address-select one of the
mapping registers [MAPC+D

RA(21:01) H]. The

contents of this register are summed with bits 12 to
I of the Unibus address [MAPA ADRS(12:01) H]
to generate the Cache address [MAPE CA(12:01)
H].

1.4 ADDRESSING LIMITS
Refer to schematic MAPF. There are 31 mapping
registers which can be accessed by the Unibus for
relocation. The actual number is determined by two
sets of five jumpers which set the upper and lower
address limits to which the Unibus Map will respond. The jumpers for the lower limit can be cut
so that the Map will start to respond at Unibus ad-

dress OK, 4K, up to 124K on 4K boundaries. Similarly, the jumpers for the upper limit can be set so
that the Map will stop responding at Unibus address 124K, 120K, and down to OK on 4K boundaries. The Map will not respond to the uppermost

The mapping registers consist of the 12 3101A 16-

4K of Unibus address space. The maximum range

word

of Unibus addresses that the Map can accept is 000

by 4-bit

scratch

pad

memories,

shown

000 - 757 777.

drawings MAPC and MAPD.

or those on MAPD (addresses 17 770 300 - 17 770

Bits(17:13) of an incoming Unibus address are
checked against the jumpers to ensure that the address lies inside these limits. If the address is
greater than or equal to the upper limit, or less
than the lower limit, it is assumed that some other
device is being addressed and no request is made to
the Cache. The Unibus Map can be bypassed altogether by cutting both sets of jumpers to all zeroes.
This would mean that Main Memory cannot be ac-

376) through their CS inputs.

cessed from the Unibus.

1.2 REGISTER SELECTION
During a Cache Unibus cycle, MAPB REG OP L
is high (i.e., the address does not point to a map
register).

MAPA

ADRSI7

then

causes either

MAPC EN LO REG L or EN HI REG L to be asserted. These signals enable, respectively, the registers on MAPC (addresses 17 770 200 - 17 770 276)

CHAPTER 2
UNIBUS/CACHE INTERFACE

This chapter describes the Unibus/Cache interface,

which

excluding address relocation, which is explained in

(or DATOB), which requires a write into memory.

Chapter 1.

The

requires a read from memory, and

Map

does

not

distinguish

DATO

between

DATI

(data-in) and DATIP (data-in, pause), nor between
Figure

2-1

outlines this interface function of the

DATO (data-out) and DATOB (data-out, byte): it

Map, and Figure 2-2 is a functional block diagram.

transmits

Unibus

DATA

tinguishes

DATI

exchanged

between

the

Unibus

[BUS

D(15:00)} and the Cache is buffered by the Unibus
Map

and

transmitted,

without

modification,

control

from

bit

CO0,

which

DATIP and

DATO

disfrom

DATOB, to the Cache.

both directions. The Unibus Control bits (BUS CO

and C1) are received by the Unibus Map and transmitted directly to the Cache. BUS MSYN is sent to

the Cache as MAPF UB REQUEST (1) L if the

Unibus address [BUS A(17:01) L] is recognized as

2.1

UNIBUS DATA CYCLE

The Unibus address lines, BUS A(17:00) L are received by the Map. The output of their bus receivers is labeled MAPA ADRS(17:01) H and MAPA

a valid Cache data or register address. A parity er-

CAO00 H. Address bit 0 is always transmitted, un-

ror in the Cache causes BUS PB L to be asserted
by the Unibus Map. BUS SSYN L is asserted by
the Unibus Map when it is informed by the Cache

instructions.

modified, to the Cache, since the Map ignores byte

that the data cycle is finished (CCBC UB DONE

MAPA

ADRS(17:02)

H).

CACHE

REG

are

decoded

and

MAPB

is asserted if a Cache register ad-

dress is sensed [(17) 777 740 - (17) 777 752]. This
The

Unibus

address

decoded

the

Unibus

Map. I it is a Cache register address (17 777 740 -

signal

and

MAPA

ADRS(03:01)

constitute

Cuche register address.

17 777 752), MAPB CACHE REG L is sent to the

Cache:r this signal, in addition to Unibus address
bits MAPA ADRS(03:01) H allows the Cache to select

the

required

for

the

current

data

transaction,

If' the address is a valid Cache address (as determincd by the limit jumpers), it is either sent to the

MAPA ADRS(17:13) H are compared with the upper and lower limit jumpers shown on schematic

MAPF. If the address falls within the limits set by
the jumpers, or if a Cache register address has been

decoded

(MAPB

CACHE

REG

L),

MAPF

CACHE BUS ADRS L is asserted.

Cache unmodified (if the Map is not enabled), or
relocated (if the Map is enabled). The Map is en-

abled if bit-5 of Memory Management Register 3 is

REQUEST (1) L is set; its output starts a Cache

sct (Unibus address 17 772 516). Figure 2-3 shows
Map. and the Cuche.

read or write sequence. The UB REQUEST flipflop is reset by CCBC UB ACKN L, which is asscrted by the Cache when the Unibus memory cycle

The

is initiated. MAPJ ENBUS H is asserted at the
same time as UB REQUEST H. It gates SSYN and

the

signals

Map

exchanged

between

the

Unibus,

the

responds as a slave to the two major

types of Unibus transactions:

DATI (or DATIP)

V-2-1

Refer to Figure 2-4. Upon receipt of the assertion
BUS

MSYN

the

flip-flop

the data onto the Unibus lines.

MAPF

co, c1

A (17:00

MSYN

NO ACTION

SSYN

DECODE

ADDRESS

REG. ADDR.
?

MAPB

CACHE REG. L
& MAPA

MAP

ADRS (03:01

ENABLED

MSYN

YES

UNIBUS
ADDRESS
UNMODIFIED

UNIBUS
ADDRESS

RELOCATED

MAPF UB
r——-

REQUEST

Jd
CACHE

SSYN

11 -4013

Figure 2-1

Unibus Map Flowchart

V-2-2

MSYN

MAPF

UPPER 8 LOWER
LIMIT JUMPERS

MAFPB

| |
<17:13>

MAPF

NOT PERIPHERAL

LIMIT

»|

UB REQUEST (1) L

PAGE

COMPARATOR
MAPF

CCBC UB ACKN L

SCCL. ENAB MAP H

MAPD ENAB MAP

|%
R
UB

MAPA

"| baTa

D<05:00>»

AIT:13)

MAP REGS. | Raq21:01>

|[MXDIMAPH[

MAPL

MAPC, MAPD
R

D<15:01>

MAPA

A<06:02>

DATAC15:00>

*1ADDER

MAPE CA{21:01> H

.
RACITION
|\ ape

"l aDDRs
MAPA

MAPA
|

MAPA

CAQ@ H

ADRS <03:01>H

ADDRS
R

DECODE

CACHE REG

MAPB CACHE REG L

ct,CO

MAPS

MAP REG

MAPB

oLY
MAPB CiH, C@ H

CCBD UB TIMEOUT L j[>c

BUS SSYN
—

CCBC UB DONE H
MAPB

DTML CDMX D<15:00 H
"l

CCBF REG D(15:00> H

<15:01>

<05:00>

eS| BUFFER

REG

| 8YS?
MAPY

MAPH
MAPB PB

DTML BAD PARITY

DATA H

BUS

MAPH

MAPB

NOTE:

D= UNIBUS DRIVER,

1H-4018

R=UNIBUS RECEIVER

Figure 2-2

Unibus Map Block Diagram

V-2-3

UNIBUS MAP

UNIBUS

MS YN

CACHE

MAPF UB REQUEST (1) L

{

cCBB

PRE

UBUS

F/F

cCBC

ACKN

MAPB

ADMJ

MAPB

ADMJ

READ

MAPA

CAQ@P@ H

ADME

AMX <21:00>

MAPE

CA<21:1> H

A<17:00>

}

MAPA ADRS <@3:21> H
MAPB

CACHE REG L

MAPJ

DATA

<15.:00>

CCBH, CCBY (REG. LOGIC)

CDPE

WRITE MUX <15:00> H

D<15:00>

(MAPJ) BUS D<15:00> L

SSYN

(MAPB)
MAPB

BUS PB

DATA

L
H

(MAPB) BUS SSYN L

MAPD

ENAB

MAP

{

———

DTML COMX

D<Ii5:00> H

CCBF

REG

D<15:00>

DTML

BAD PARITY

CCBJ

(REG.LOGIC)

CCBC

uUB

DONE

CCBD

TIMEOUT

SCCL

ENAB

MAP

H
L

11-4052

Figure 2-3

Unibus Map Interface

V-2-4

MAPA ADRS(17:00>
H 7/

#%MAPA

DATA<15:00> H

MAPB MSYN H

MAPB CACHE REG H /2222
7,

MAPJ

MAPF CACHE BUS ADRS L zz-é;/
ENBUS H

MAPF UB REQUEST

(1)L

CCBC UB ACKN L

CCBC UB DONE H

BUS

SSYN

*MAPH CA DATAC15:01>

#BUS D{15:00>L,

PB L
*#*NOTE: DATI or DATIP only.
®#%# NOTE : DATO or DATOB only,
11-4025

Figure 2-4

Cache/Unibus Transactions

Along with the Control bits Cl and CO, the Cache
receives

the

address

MAPE

CA(21:01)

and

casc of a memory reference; if the operation refers
to

Cache

the

data

transmitted

MAPA CAO00 H for memory references, or MAPA

CCBF REG D(15:00) H. One of these two sets of

ADRS(03:01)

data is selected by MAPB CACHE REG L via the

H and MAPB CACHE REG L

Cache register reference. When

for a

UB REQUEST is

multiplexer shown on drawing MAPH.

received, it executes the write (DATO/B) or read
(DATI/P) operation required of it.

The output of this multiplexer is clocked

into the

MAPH CA DATA(15:00) (1) H flip-flops by the ris2.2
In

DATO OR DATOB

g edge of CCBC UB DONE H. (UB DONE is as-

the case of a data-out, the Cache accepts the

data,

MAPA

DATA(15:07)

then

asserts

CCBC UB DONE H.

serted

the

Cache

when

its

data

operation

completed.) MAPH CA DATA is then multiplexed
with

the map

MAPB

REG OP H is low (not a map register operation),

2.3

DATI OR DATIP

the Cache data is the input to the Unibus data driv-

I the transaction is a data-in, the Cache puts the re-

ers [BUS D(15:00) L], which are enabled by MAPJ

quested data on DTML CDMX D(15:00) H, in the

ENBUS H.

V-2-5

2.4

PAR ERR (1) H: it is gated with Cl and MAPF

END OF DATA CYCLE

The falling edge of CCBC UB DONE H, which oc-

PAR ADRS OK H to generate MAPB PB DATA

curs 60 ns after its rising edge, sets a flip-flop on

MAPB which in turn causes BUS SSYN L to be as-

MAPB PB DATA H is also ANDed with ENBUS

which

input

the

Cache error

registers.

serted. When the negation of MSYN s received at

to generate BUS PB L. MAPF PAR ADRS OK H,

the Map, MAPJ ENBUS H is negated. This causes

when asserted, signifies that the address of the cur-

SSYN and. in the case of a DATI or DATIP, the

rent transaction lies within the limits of the upper

data and PB, to be removed from the Unibus.

and lower limit jumpers.
2.6

CACHE TIMEOUT

2.5

PARITY ERROR

CCBD UB TIMEOUT L is asserted by the Cache

BUS

PB L is asserted when a parity error is de-

when a timeout has occurred on the Main Memory

tected by the Cache. DTML BAD PARITY H is

Bus during a Unibus transaction. When asserted, it

clocked into a latch on MAPH at the same time as

sets a flip-flop on MAPB which prevents the asser-

the Cache data. The output of this latch is MAPH

tion of BUS SSYN L.

V-2-6

CHAPTER 3
READING AND WRITING

THE MAPPING REGISTERS

The mapping registers are loaded and read by the

3.1

program via the Unibus. These registers are 21 bits

REGISTERS

READING

AND

WRITING

MAPPING

wide: two Unibus cycles are required to read them

Refer to Figure 3-1. The Unibus Map responds to

or to write into them. There are 32 mapping regis-

64 Unibus Addresses [(17) 770 200 - (17) 770 376].

ters which require the 64 1/0 Page addresses in the

This allows reading and writing of the mapping reg-

range of 770200 - 770376. Each of the registers con-

isters. Once the Map has recognized one of these

sists of two parts (for the purposes of reading and

addresses, it uses bits (06:02) to select the correct

writing): a high word, MAPH (bits 21 - 16) and a

low word, MAPL (bits 15 - 01). Bit 0 does not ex-

operation]. Sixty-four addresses are needed due to

ist, since the Map ignores byte operations.

the 22-bit register width.

BUS
A (17:00

]

Bit A01 = 0 enables

data transfer between

BUS D (15:01) and
h 4

bits (15:01> of a
register.

Bit AO1 = 1 enables
transfer between

BUS D (15:01)

y
BUS A (06:02) select

one of 32 Mapping

BUS D (05:00 and
blt§ (21:16) of a

16 15

00
4
A

BUS D (05:00)

Registers, 00—37,

MAPH

1 1

I |

MAPL
|

01
|

11-4030

Figure 3-1

Addressing of UB Map Register

V-3-1

MAPB REG OP L gated with MSYN causes
MAPJ ENBUS H to be asserted. ENBUS gates
SSYN and, during a DATI, the register data onto

Also as a result of this, two Unibus cycles are required to complete a read or write operation to a
mapping register. The bit assignment in the registers is divided so that Unibus address (17) 770
XXX will access bits (15:01) of the register and address (17) 770 XXX +2 will access bits (21:16).

the Unibus.
3.3

DATO

with MAPA ADRSO06 H to select either registers 00

A DATO is a write to a register. MAPB CI1 H is asserted and, when MSYN is received, either MAPB
WRITE HI WORD L or WRITE LO WORD L is
asserted, depending upon the state of MAPA
ADRSOI. WRITE HI WORD gates bits 05 - 00 of
Unibus data into bits 21 - 16 of the selected register; WRITE LO WORD gates bits 15 - 01 into bits

- 17« on MAPC (MAPC EN LO REG L), or regis-

15 - 01 of the register.

3.2 REGISTER SELECTION
MAPB REG OP is asserted when an Unibus address in the range of 770 200 - 770 376 is decoded.
Refer to Figure 3-2. MAPB REG OP H is gated

ters 205 - 37« on MAPD (MAPC EN HI REG L)
by enabling the 3101s via the enable (CS) input.

The receipt of MSYN also starts a 70-ns delay,
which allows for the write propagation time of the

16 registers (either one of 00-17, or 20-37;, depend-

3101As. At the end of the delay, MAPB REG
SSYN L turns off the write pulse and causes BUS
SSYN L to be asserted. When BUS MSYN is ne-

ing on which set of CS inputs is low).

gated, SSYN is negated.

MAPB REG OP L gates MAPA ADRS(05:02) H
to MAPC INDA(4:1), which in turn select one of

MAPA ADRS <17:00
**MAPA DATA (15:00

MAPB MSYN H

MAPB REG OP H

)

MAPJ ENBUS H

|#100 ns»

(

yd
\

MAPB REG SSYN L

**MAPB WRITE LO WORD

BUS SSYN L

*BUS DCI5:00>L

% %*MAPB WRITE HI WORD L}

\‘

* NOTE: DATI only

#%#NOTE: DATO only
11-4024

Figure 3-2

UB Map Register Read/Write

V-3-2

3.4

DATI

H. thus putting the contents of the selected register

When a register has been selected, the output of the

on the Unibus D lines.

selected register [MAPC+D RA(21:01) H] is read

and input to the data multiplexer shown on draw-

When

ing

itiated to allow for the access propagation times of

MAPJ.

Since

MAPB

REG

high,

MSYN

received,

the 70-ns

delay

is in-

MAPA ADRSOI selects (via the multiplexer) either

the

the low word (MAPL) or the high word (MAPH)

serted after the delay, BUS SSYN L is asserted on

of the register that is being addressed, as shown in
Table 3-1. When the MAPH part of a register is se-

the Unibus. SSYN is negated upon receipt of the

3101As.

When

MAPB

REG

SSYN

L is as-

negation of MSYN.,

lected [RA(21:16)] the A inputs to the 74S157 multiplexers are selected. This is the Cache data input

3.5

[MAPH CA DATA(15:06) H], but it is 0, since the

Table 3-2

flip-flops on drawing MAPH were cleared by the

Unibus addresses that select each mapping register

negation

and the two addresses used for reading or writing

MSYN

the

reference.

Thus, bits 15 - 06 of BUS D are all 0, and BUS

the

the same register.

D(05:00) contain the high order bits (21:16) of the
selected register.

Note

that

selected

Unibus

ad-

dresses (17) 760 000 - (17) 777 777. Since these addresses are higher than the maximum allowed by

The multiplexer is enabled if the operation is a
DATI (MAPB C1

H is low). The 8881 bus drivers

[BUS D(15:00) L] are enabled by MAPJ ENBUS

the upper limit jumpers, register 37 cannot be used
as a mapping register. It can, however be read and
written

into

using addresses (17) 770 374 and

(17) 770 376.

Table 3-1

Unibus Data Selection

MAPB

MAPA

REGOPH

ADRSO1

Bus D(15:06)

Bus D(05:01)

Bus D00

MAPC+D

RA(21:17)

RA16

MAPC+D

RA(15:06)

RA(15:01)

V-3-3

Table 3-2

Access to Unibus Map Registers

Unibus Address for
Memory Reference

Unibus Address
Read or Write
MAPH
MAPL

0
|
2
3

17 770 200,
17 770 204,
17 770 210,
17 770 214,

02
06
12
16

17 000 000 — 17 017 777
17 020 000 — 17 037 777
17 040 000 — 17 057 777
17 060 000— 17 077 777

4
5
6
7

17 770 220,
17 770 224,
17 770 230,
17 770 234,

22
26
32
36

— 17 117 777
17 100000
17 120000— 17 137 777
17 140 000 — 17 157 777
17 160 000 — 17 177 777

10
11
12
13

17 770 240,
17 770 244,
17 770 250,
17 770 254,

42
46
52
56

17 200000 — 17 217 777
17 220000 — 17 237 777
17 240 000 — 17 257 777
17 260 000 — 17 277 777

14
15
16
17

17 770 260,
17 770 264,
17 770 270,
17 770 274,

62
66
72
76

17 300 000— 17 317 777
17 320000 — 17 337 777
17 340 000 — 17 357 777
17 360 000 — 17 377 777

20
21
22
23

17 770 300,
17 770 304,
17 770 310,
17 770 314,

02
06
12
16

17 400 000 — 17 417 777
17 420 000 — 17 437 777
17 440 000 — 17 457 777
— 17 477 777
17 460 000

24
25
26
27

17 770 320,
17 770 324,
17 770 330,
17 770 334,

22
26
32
36

17 500 000 — 17 517 777
17 520000 — 17 537 777
17 540 000 — 17 557 777
17 560 000 — 17 577 777

30
31
32
33

17 770 340,
17 770 344,
17 770 350,
17 770 354,

42
46
52
56

17 600 000 — 17 617 777
17 620 000 — 17 637 777
17 640 000 — 17 657 777
17 660 000 — 17 677 777

34
35
36
*37

17 770 360,
17 770 364,
17 770 370,
17 770 374,

62
66
72
76

17 700 000— 17 717 777
17 720000 — 17 737 777
17 740 000 — 17 757 777
17 760 000 — 17 777 777

*Note: Can be read or written into, but not used for mapping.

V-3-4

SECTION VI

CACHE

Unless otherwise indicated, references within this section pertain to this section only.

SECTION VI

CACHE

CONTENTS
Page

CHAPTER 1

CACHE CONCEPTS

1.1

SCOPE

1.2

OVERALL ORGANIZATION OF A CACHE MEMORY SYSTEM

. . . . .

e e e e

1.3

PROGRAM LOCALITY

1.4

BLOCK FETCH

1.5

FULLY ASSOCIATIVECACHE

1.6

DIRECTMAPPINGCACHE

1.7

SET ASSOCIATIVECACHE

1.8

WRITE-THROUGH AND WRITE-BACK

CHAPTER 2

PDP-11/70 CACHE

2.1

SCOPE

2.2

PDP-11/70 CACHE

. . . . . o

e e

e e et e e et e e e et e i

e e e e e et e e e e e e e e

. . . . . . . . .

. . . . . . . .

. . . . . .

2.2.3.2

Read Miss

2.2.3.5

Power-Up Initialization

. . . . . .

i i i i i

. . o o o o

e e e

THEORY OF OPERATION

DataParity

3.2.2

Address Parity

e e e

e e

e VI-24

e e

e Vi-24

e e e e

. . . . . .

e e e e VI-24

e e

e e e VI-2-6

e e e e e e

e e

e VI-3-1

. . . . .

3.3.1

AddressPaths

. . . . . . . .

3.3.2

Read DataPath

. . . . . . . . . . .

Write DataPaths

. . . . . .. .. ... .

e VI-2-6

e e

e e e

. . . . . . . . . .

CACHE DATAPATHS

e e

. . .. ... .. ... ... ... ... VI-2-6

e e

. . . . . . . .

e e

e e e e e e e e e e e e e e

CHAPTER 3

3.2.1

e i

EXAMPLE OF PDP-11/70 CACHE OPERATION

. . .

... .. VI-2-2

. . ... ... ... .. .. ... ... .. ..... VI-2-6

2.3

SCOPE

e e VI-2-1

. e
e e e VI-2-4

. . . . . . 0 o 0

OVerview

e VI-1-3

VI-2-1

. . . . . . . o o o i

Write Miss

et e

it i, PP VI-1-5

. . . . .. ... ... ... ... VI-2-2

. . . . . . . .

Write Hit

PDP-11/70 SYSTEM

e et e e e

e e e e e e e e e e e e

. . . . . . . . o i

2233

3.2

it e

e VI-1-2

e ettt e e VI-1-2

. . . ... ... ... .. .. ...

2234

3.1

e e VI-1-1
e

Cache Operation
Read Hit

e VI-1-1

. ... .. ... ... ... ... .. ..... VI-1-6

. ................ST

2231

. . ... .. .. .

2.2.3

e
.

e e e e e e

e e e VI-3-3

e e e e

e VI-3-3

e e

e VI1-3-3

e e VI-3-3

e V1-3-4

. e VI-3-4

PROCESSOR-CACHE INTERFACE

. ... .. ... ... . .. .. . .. ... VI-3-4
. . . . .. . .. . . . it VI-3-9

3.5

UNIBUS MAP-CACHE INTERFACE

3.6

RH70-CACHE INTERFACE

3.7

MAINMEMORY BUS

3.8

OPERATIONAL FLOWS

. . . . . . . . .

e e

e e e e

e e

. . . . . . .
. . . .

3.8.1

ProcessorRead Hit

3.8.2

Processor Read Miss

3.8.3

ProcessorWrite

3.84

Processor BUST-BEND Cycle

3.8.5

UnibusMap Read Hit

. . ............ e

Unibus MapRead Miss

. . . . . . . . . . .

e e

Data Memory Organization

3.8.6

e e e e

. .. ......
... VI-1-1

Address Memory Organization

333

22.1

3.3

. . . . .t

2.2.2

2.2.3.6

e e e e

e e

e e e VI-3-9
VI-3-15

e e e e e e e e e

. . . .. .. .. .. .. .. .. . . ... . . 0.

VI-3-19

...,

VI1-3-20

. . . . . . . . . . . . . .. i

VI-3-20

. . . . . . . . . o i

e e e

e e

. . . . . .. ... .. . . ...,
e e e

v i i it

3.8.7

Unibus Map Write

3.8.8

Cache Register Read/Write

. . . . . . . . . . . .

3.8.9

MBC Read From Memory

. . . . . . . . .

3.8.10

MBC Write to Memory

. . . . . . . . . . . . . o

VI-3-27

s it et e

VI-3-29

v i it i it e i

i i i it i

e e

VI-3-24

. . . . . . . . o it e

Vliii

e e e e e e

VI1-3-23

e e e

e e e e e e

e e

VI-3-30

VI1-3-32

VI-3-32

VI-3-37

CONTENTS

(Cont)
Page

CHAPTER 4

DETAILED LOGIC

4.1

SCOPE

4.2

BLOCK DIAGRAM DESCRIPTION

. . . .

. . . . . . .

4.2.1

MBC Address Latch

. . . . . . . . v

. . . . . .. ... ..

422

Address Multiplexer

423

Main Memory Bus Control Generator

424

Main Memory Bus Address Drivers

4.2.5

Address Field Inverter

4.2.6

Index Field Inverter-Drivers

4.2.7

Address Memory

4.2.8

Valid Bit Generator

4.2.9

Address Memory Parity Generator

e e e e e e

e e

e e e Vi4-1

i it ittt ettt e et i
i

e Vi4-1

. . . . ... ... ... ...

..., Vi4-2

. . . . . .. ... ... ... ... .. .. ... VI4-3

. . . . . . . . . . . ... e Vi4.-3
. . . . ... . .. ... ... ..., Vi4-3

. . . . . . L

. . . . . . . . .

e e

e e e e e e e e VI4-3

e e e e e e e e

e Vi4-4

. . . . . . ... ... ... ..

4.2.10

Tag O and Tag 1 Parity, Address, and Validity Checker

4.2.11

Write Data Multiplexer

. . . . . . .. ... .. ... . ..

4.2.12

Data Parity Generator

. . . . . . . . . .

e Vi4-4

. ... ... ... ... .. Vi4-4
e

e
e e

Main Memory Bus Data Drivers

. . . . . . . . v v v i

4.2.14

Main Memory MBCDataDrivers

. . . . . . ... ... ... ... ...

4.2.15

Main Memory Bus Data Receivers

4.2.16

BusData Register

VI4-5

..., Vi4-5

. . . . .. ... ... ... ... .. .. ..., Vi4-5

. . . ... ... ... . . ... . Vi4-6

4.2.17

Even Multiplexer and Odd Multiplexer

42.18

Main Memory Data Parity Check

4.2.19

FDMIndex Field Drivers

. . . . . . . .. . .. . .

4.2.20

Fast DataMemory (FDM)

. . . . . . . . . i i i i i

4.2.21

FDM Data Parity Check

. . . . . . . . . .

4.2.22

Even and Odd Multiplex Inverters

Cache Data Multiplexer

4.2.24

. . . . .

Cache Timing Sequence

4.3.2

Read Hit Timing

433

434

. o

i it i

e e

e, Vi4-6

e e e e e

it et

e Vi4.7

e e Vi4-8

. . . . . . ... ... ... ... ... ..... Vi4-8

. . . . . . . . . . . i i i

. . . . . . . .

4.3.1

. . ... ... ... ... ........ “. . VI4-6

. . . .. ... ... ... ... ... . ...... Vi4-6

4.2.23

CACHETIMING

. VI4-5

e e VI4-5

4.2.13

e e Vi4-1
e Vi4-1

i i

0 o

e e

e VI4-8

e e e

e et e e

e e e e

. . . . . . . . ¢ o v i v it it e

. . . . . ... .. ...

e VI4-9

e e e

e Vi4-9

ittt i i,

VI4-10

Main Memory Bus (Slow Cycle) Timing

. ... ... ...............

VI4-10

Timing Restart After Main Memory Cycle

. . ... ... ... ..........

VI4-11

4.4

POWER-UPLOGIC

. . . . . . .

4.5

REQUEST ARBITRATORLOGIC

4.6

MBC ARBITRATIONLOGIC

e e

e VIi4-9

e e

et i

e e e e e et e i

Vi4-11

.. ... .. ... ... it

Vi4-12

. .. .. . ..

4.6.1

Request Block Logic (DrawingCDPH)

4.6.2

Addressand Data Select Logic

i i

et i

e et e e

VIi4-13

. . .. ... ... ... ..........

VI-4-13

. . . ... ... ... .. ... ...

. .....

Vi4-13

4.6.2.1

Single Request Operation

. . . . . . .. ... ...

4.6.2.2

Multiple Request Operation

. . . . . . . ... . .. v

4.6.3

Data Ready Logic

. . . . . .. . . . .

VI4-15

i e

Vi4-16

VI4-17

4.7

GROUP SELECTION AND VALIDBITLOGIC

. ... ... ..............

4.8

CACHE REGISTERS AND REGISTERLOGIC

. ................. v v .

VI4-17

Low Error Address Register (17 777740)

. . . . . . ..

.. ...

VI4-18

4.8.2

High Frror Address Register (17777742)

. . . . . . . v v i i i v i i i v

Vi4-18

4.8.3

Memory System Error Register (17777744)

4.8.1

4.8.4

Control Register (17777746)

4.8.5

Maintenance Register (17 777750)

4.8.6

Hit/Miss Register (17 777 752)

4.8.7

Useof Cache Registers

4.8.8

. ... ... ... .. .... ... VI419

. . . . .. ...

. . . ... . . .

. . ¢ v v v i i

. . . . . . . . . . .. . .

. . . . . . . o 0 i i i

... PR

Vi4-19

...

Vi4-21

e e e e e et e e e

VI4-21

VI4-22

e e

VI-4-24

i i i it
e

e e

ILLUSTRATIONS
Figure No.
1-1
1-2
1-3

14
1-5
2-1

22
23
2-4

3.1
3.2

3.3
34
3.5

3.6
3.7

3.8
39
3.10
3.11

3.12
3.13

3.14

3.15

3.16
3.17
4-1
4.2
4.3
44

4.5

4-6
4.7
4-8

4.9
4-10
4-11
4-12

4-13
4-14

Title

Page

Relationship of Cache to Processor and Main Memory . . . . ... ... ... ... ... VI-1-1
. . . . ... ... . ... VI-1-3
Fully Associative Cache Memory System

Direct Mapping Cache Memory System . . .. ... ... .. ........ e VI-1-4
. . ... ... ... .. VI-14
18-Bit Byte Address Breakdown (4 Words per Block, 64 Blocks)

. ... ... ............. VI-1-5
Set Associative Cache Memory System (Two-Way)
Sets of Blocks) . ... ... .. VI-2-1
256
Block,
per
Words
(2
Breakdown
Address
22-Bit Byte
o VI-2-2
o v
v v v
...
...
.
.
.
.
.
Organization
Memory
Data
Fast
e e VI-2-3
Address Memory Organization . . . . . . . . o 0 v vt i e e
PDP-11/70 Cache Simplified Data Path Diagram . ... .................. VI-2-5
e e VI1-3-2
e e
PDP-11/70SYStem . . v v v v v v o v v et et e e ettt
v oo o oo VI-3-5
v v v v it i
Cache Data Paths Block Diagram . . . . . . . . ..

e e e e e e VI-3-8
Processor — Cache Protocol . . . . . . v 0 v i i i
Unibus Map — Cache Protocol . . . . . .. ... ... ... . v VI-3-9
RH70 — Cache Protocol . . . . . v v v i i it e e e e e e e e e e oo e VI-3-12
Cache — Main Memory Protocol . . . . . .. . .. o oo VI-3-16

i i VI-3-19
v v ot
Flowchart Symbol Definitions . . . . . . .. . ..
e e e e e VI-3-21
e
e
e
e
e
e
e
e
e
i
i
i
i
o
.
Processor Read Hit . . . . . . . . .
e e e e e VI-3-22
e
e
e
e
e
e
e
e
e
i
i
v
i
i
v
.
.
.
.
.
.
.
Processor Read Miss .
e e e e VI-3-25
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
i
v
v
v
v
v
.
.
.
Processor WHtE
Processor Bust-BendCycle . .. ... .............. e e e e e e VI-3-26
. . . . . .. . .. 0o it it VI1-3-27
Unibus MapRead Hit
UnibusMap Read Miss . . . . . . v o v v v i it e VI1-3-28
VI-3-31
e
e
. . . . . . . . o o i
Unibus MapWrite
i i VI-3-33
vt
Register Readand Write . . . . . . . ... ...
e VI-3-35
MBC Read FromMemory . . . .« v v v v i i e i et e e e e e e e e e e
MBC Write to MEIMOTY . « « v v v v v et v v et e et it e et e et e e e e e s VI-3-36
Cache Clock Waveforms . . . . . . v v v i v i e e e e e e e e e e e et e e e e e e Vi4-9
e e VIi4-10
Cache Timing SEQUENCE . . . . v v v v v v v et v v e e e e e e
Power-Up Sequence Timing Diagram . . . . .. ... .. ... ............. Vi4-12
Relationship of the MBC Arbitrator tothe Cache . . . ... .. ... ... ... ... VI4-13
. . . . . . . ... . o o Vi4-14
MBC Arbitrator Block Diagram
. . . . ... ... ... Vi4-14
MBC Request Timing (MBC A Requesting)
MBC Address and Data Select Timing (Multiple Requests — Straight Priority) . . . . .. Vi4-15
Low Error Address Register . . . . . . . . . o v i v i ittt Vi4-18
v i v i Vi4-18
High Error Address Register . . . . . .. . ... .
o oo Vi4-19
...
...
.
.
.
.
.
.
.
Register
Memory System Error
Vi4-21
e
e
e
e
it
v
v
v
v
.
.
.
.
.
Register
Control

. . . . . . . o o oo Vi4-22
Maintenance Register
VI4-25
e e
Hit/Miss RegiSter . . . . v v v o v v v e e i e e et e e e e
Register Logic Block Diagram . . . . . . .. ... ... . o oo VI4-25
TABLES

Table No.
2-1
2-2

3-1

3-2
3-3

Title

Page

V1-2-9
e
e
e e
e
. . . . . . . . .
Example Program
Summary of Cache Operations Example . . .. ... ...... ... .......... V129
. . . .. ... ... ... ... .. ... VI-3-6
Master Timing and Initialization Control Lines
. . . . . . . ¢« v o v v v v v i v v v i o VI-3-6
Processor-Cache Data Transfer Control
Unibus Map-Cache Interface Signals . . . . . ... .. ... VI-3-10

TABLES (Cont)

Title

Table No.
34

RH70-Cache Interface Signals

3-5

Main Memory Bus Signals

3-6

Memory Bus Signal Pin Connections

4-1

MBC Selection Priorities

4.2

Cache Registers

4.3

High Error Address Register

Memory System Error Register

4.5

Control Register

4-6

Control Register Bits 5:2

4.7

Maintenance Register

Page

. . . . . .. ... . .. . i

. . . . . . .. ...

Lo e

. . . . .. .. ... ... .. ..

VI-3-17

VI-3-18

0., e e

VIi4-13

e e

Vi4-17

. . . . . .. ... .. .. ...,

VIi4-18

. . . . ... ... ... ... ...

. . . . .« v v o v i i

. . . . .. . ... ... ...

. . . . . . . . . 0 o 0

. . . . . . . . . . . .
. . . . . . . . . . .. L

Vi-vi

VI-3-13

o
e

e e

V14-20

e e

Vi4-21

Vi4-22

VI4-23

CHAPTER 1
CACHE CONCEPTS

1.1 SCOPE

Figure 1-1 illustrates the relationship of a cache to

This chapter explains the purpose of cache memory

the processor and Main Memory.

systems and describes various methods used to implement such systems. Parameters and strategies involved

cache

memory

design

are

introduced,

described, and analyzed in order to facilitate the

PROCESSOR

reader’s understanding of the specific Cache implemented in the PDP-11/70 system.

1.2 OVERALL ORGANIZATION OF A CACHE

CACHE

MEMORY SYSTEM

GMAIN MEMORY BUS

The cache memory system is intended to simulate a
system having a large amount of fast memory. To
do this, the cache system relies on a small amount

MAIN

MEMORY

of very fast memory (the cache), a large amount of

11-2833

slower memory (the Main Memory), and the statis-

tics of program behavior.

Figure 1-1

The basic idea is to store some data in the fast
memory and some in the slow memory. If it can
somehow be arranged that data is in the fast mem-

ory when the processor needs it, the program will
execute quickly, slowing down only occasionally for
Miain

Memory

operations.

Conventional

mixed

MOS-Core systems attempt to achieve this goal by
having the programmer guess beforehand which sections of his program should go in each memory.
This is often awkward, and usually only moderately
successful.

The

cache

achieve the same goal

memory

system

tries

by automatically, dynam-

Relationship of Cache

to Processor and Main Memory

1.3 PROGRAM LOCALITY
A cache memory works because it can usually predict successfully which words a program will require soon. If programs used words completely at
random from all of memory, it would be impossible
to

predict

needed

which

next.

words

would

most

Under these circumstances,

likely

a cache

memory system could perform no better than a conventional

mixed

memory

system

with

small

amount of bipolar memory.

ically shuffling data between the two memory types
in a way which gives a high probability that useful

data will be in the fast memory. All of the following discussions of cache organizations and strategies are intended to show implementable methods

of shuffling data so that the data most likely to be
needed next will be in the fast memory instead of
the slower Main Memory.

Fortunately, programs do not generate random addresses. Instead, programs have a tendency to make
most accesses in the neighborhood of locations ac-

cessed in the recent past. This is the basis of the
principle of program locality. The fact that programs display this type of behavior makes cache
memory systems possible.

VI-1-1

An understanding of why the principle of program

The block size is one of the most important parame-

locality is true can be obtained by examining the

ters in the design of a cache memory system. If the

small scale behavior of typical program data struc-

block

tures. Code execution itself generally proceeds in

sufficient

straight lines or small loops; the next few accesses

slightly, particularly for programs which do not con-

size is too small, the system will have inlook-ahead and performance will suffer

are most likely to be within a few words ahead or

tain many loops. Also, as will be discussed later,

behind. Stacks grow and shrink from one end, with

small block sizes require the system to store more

the next few accesses near the current top. Charac-

addresses than large blocks, for the same total mem-

ter strings and vectors are often scanned through

ory size.

sequentially.

If the block is too large, there may not be room for
enough blocks in the cache to provide for adequate

The principle of program locality is a statement of
how

most

programs

tend

behave,

not a

look-behind. Large blocks also tend to mean more

law

memories operating in parallel within the slow memory, and therefore wider buses between slow and

which all programs always obey. Jumps in code sequences, seemingly random access of symbol tables

fast

by assemblers, and context switching between programs

are

examples

of behavior which

can

ad-

reference

can

never

increased cost.

As the

originally

requested word and less likely to be
needed soon by the program. It has been found em-

a processor. The process of guessing which words a
will

resulting

is less likely to be useful, since it is further from the

versely affect the locality of addresses generated by
program

memory,

block gets larger, each additional word in the block

com-

pirically that while a block size of two words in-

pletely successful. The percentage of correct guesses

creases memory system

is a statistical measure affected by the size and or-

ganization of the cache, the algorithms it uses, and

the behavior of the program driving it.

further

increases

smaller

improvements

performance dramatically,

block
which

size

produce

much

are

seldom

worth

implementing.

1.5 FULLY ASSOCIATIVE CACHE

1.4 BLOCK FETCH

If a cache memory system was designed so that the

The principle of program locality states that for the

fast memory

cache to have the best chance of having the word

words,

make

reference

the

program

needs

next,

the

cache should

have

held

would

one contiguous block
fail

miserably.

code

Most

segments,

of 1000
programs

subroutines,

words near those recently used. The basic method

stacks, lists, and buffers located in scattered parts

of accomplishing this is the block fetch. When the
cache controller finds it necessary to move a word
of data from slow memory to fast memory because

cache would hold the 1000 words the controller esti-

the data was not in the fast memory when needed,
the controller will move not just the word required,

of the whole address space. Ideally, a

1000-word

mated as most likely to be needed, no matter how
scattered these words were throughout the address
space of Main Memory.

but a block of several adjacent words at once. Typi-

cally, the block will contain one (degenerate case),

Since

two, four, or eight words starting on an even block
boundary.

dresses of these thousand words to each other or to

The

carry its address with it, Then, when the processor

there

would

no relation

of all

the ad-

any single register or mapping function, each of the
1000 data words in the fast memory would have to

block

fetch

can

provide either look-behind,

look-ahead, or both, depending on the position of
originally requested word within the block.

requested a word from memory, the cache would

the

simply

Since many important generated address sequences
(e.g., most code) tend to move in increasing order,

processor with each of the thousand addresses of

compare

(associate)

the address from

the

words in the fast memory. If a match were found,

the originally requested word is usually the first in

the data for that address would be sent to the proc-

the block,

essor. This is the principle of an associative mem-

look-ahead.

the block

fetch generally provides

ory (Figure 1-2).

VI-1-2

MAIN
MEMORY

ADDRESS

BLOCK

-—=

CACHE

623124

4’//
>~

==
-

44322

\X4
\\

NN
N
\:\

2214

1736

11-2834

Figure 1-2

Fully Associative Cache Memory System

This system, called fully associative because the in-

Memory only one possible location in fast memory

coming address must be compared (associated) with

(Figure

all the stored addresses, gives the cache controller

being made up of three parts. The first part starts

maximum

flexibility in deciding which words it
fast memory, i.e., any words at all until
memory is full. Unfortunately, 1000 address

Consider

each

incoming

address

byte out of a block

is being requested. The next
fiecld, called the index field, starts where the first
ficld leaves off and contains enough bits to specify

comparisons would be unacceptably slow and/or expensive. One of the basic issues of cache organiza-

any

tion

the address field, contains the rest of the bits.

how to provide

minimum

restrictions on

what groups of words may be present in fast memory, while

limiting

the

number

of address

com-

parisons required.

at bit 0 and contains enough bits to specify which

wants in
the

1-3).

block

fast memory. The third field, called

As an example, consider an 18-bit PDP-11 byte ad-

dress as input to a 256-word, 4 word per block direct

mapping cache. (This cache would thus be 4

words

1.6 DIRECT MAPPING CACHE
At the opposite extreme from the fully associative
cache 1s the direct mapping cache. Instead of one

address comparison on every block, the direct mapping cache requires only one address comparison.

wide

and

blocks deep.

Assuming

four

words per block allows us to break down the ad-

dress conveniently, using octal notation.) As illustrated

Figure

1-4,

the word

field

this case

comprises bits 2, 1, and 0, where bit 0 indicates the

byte, and bits 2 and | indicate the word. The index

The many address comparisons of the fully associ-

ative cache are necessary because any block from

field comprises bits 8 through 3, and indicates the
block. The address field comprises bits 17 through
9.

Main Memory can be placed in any block of fast
memory. Thus, every block of fast memory must be
checked to see if it has each requested address. The

controller looks at the address which goes with the

direct mapping cache allows each block from Main

information currently

If the processor requests word

VI-1-3

274356, the cache

block number 35 in

fast

MAIN

MEMORY

ADDRESS

287460

BLOCK

CACHE

257450

bHh

201620

6412

4570

3334

11-283%

Figure 1-3

Direct Mapping Cache Memory System

WORD

INDEX FIELD

ADDRESS FIELD

—_J

BYTE
)

INDICATE WORDS
AND BYTES
WITHIN A BLOCK
11-2836

Figure 1-4

18-Bit Byte Address Breakdown (4 Words per Block, 64 Blocks)

memory. If this address field is 274, the controller
sends the third word in that block to the processor.
If the stored address field is not 274, the controller
must fetch block 27435 from Main Memory, transmit the third word in the block to the processor,
load the block into block 35 of fast memory, replacing whatever was there previously, and change the
address field stored with block 35 to 274.

Any address whose index field is 35 will be loaded
into block 35 of fast memory, and therefore this is
the only place the cache controller has to look if
the processor requests the data from an address
whose index field is 35.

Notice also that only the address field of the address need be stored with each block, because only
the address field of the address is required for comparison. The index field need not be compared because anything stored in fast memory block 35 has

an index field of 35. The word field need not be
compared because if the block is there, every word
in the block is there.

This is how the direct mapping cache uses inexpensive direct addressing of fast memory to eliminate almost all comparison operations.

Of course there are disadvantages to this simple
scheme. If the processor in the example above
makes frequent references to both location 274356
and location 6352, there will be frequent references
to slow memory, because only one of these locations can be in the cache at one time. Fortunately,
this sort of program behavior is infrequent, so that
the direct mapping cache, although offering significantly poorer performance than fully associative, is
adequate for some applications. Usually the system
of choice is a compromise between a direct mapping cache and fully associative cache, called the set

VI-1-4

associative cache.

1.7 SET ASSOCIATIVE CACHE

which place (if any) the requested data is located.

The set associative organization is a compromise be-

The number of times it must compare (associate) is

tween the extremes of fully associative and direct

of course equal to the number of groups, usually

This type of cache has several directly

two, three, or four. A set associative cache can be

mapped groups (Figure 1-5). For each index posi-

classified as an n-way set associative cache, where n

tion in fast memory there is not one block, but a

is the number of compares performed (i.e., the num-

set of several, one in each group. (The set of blocks

ber of groups).

mapping.

corresponding

index

position

called

“set.””) A block of data arriving from Main Memory

can

into

any

group

its

proper

index

Another

aspect

of the

increased

complexity

be-

comes apparent when a block of fast memory must

position.

be overwritten. There are now several locations in
Since

there are several

places

for data with

the

fast memory where the new data from Main Mem-

same index field in their addresses to be stored, the

ory may be written (one in each group), so the con-

type of excessive Main Memory traffic possible in a

troller must have some means of deciding which

direct mapping organization is less likely to occur.

block will be overwritten. The decision could be

This gives a set associative cache higher perform-

made- using any of the following considerations:

ance. In fact, a four-way set associative cache (four
groups) will normally perform very nearly as well

Least Recently Used (LRU) - The block least re-

as a fully associative cache.

cently used is replaced.

The price that is paid

for higher performance is

some

increase

places

memory where any given

fast

complexity.

There

are

several

First In-First Out (FIFO) - The block which has

been stored the longest time is replaced.

piece of

data can be stored, so the controller must do sev-

Random -

eral compares (i.e., must associate) to determine in

manner.

Blocks

are

replaced

MAIN
MEMORY
ADDRESS

BLOCK GROUPO GROUPt /
CACHE

2
1
o

‘\

A:*<?

FIELD

INDEX

425332
425320

]
"’74’,——

27622

27612

1410

1406

11-2837

Figure 1-5

Set Associative Cache Memory System (Two-Way)

VI-1-5

random

A replacement strategy based on LRU or FIFO information requires the storage of LRU or FIFO
bits, along with the address fields in the address
memory, and the logic necessary to generate and decode these bits. The random strategy is far easier
and cheaper to implement, yet provides performance only slightly lower than that obtainable by the
other strategies.

The extra performance of a set associative cache
usually justifies the slightly extra complexity of at
least two-way associativity in all but low performance applications.

1.8 WRITE-THROUGH AND WRITE-BACK
Assume that the following sequence of events occur. First, the processor does a read of location
200, resulting in the block containing this address
being copied into fast memory. Then the processor
writes new data into location 200, updating this location in fast memory. Next the processor does a
reference which causes the cache controller to overwrite the block in fast memory containing location
200. If the processor reads location 200 again, the
obsolete data in Main Memory will be loaded into
fast memory. This is unacceptable, and two methods have been devised to deal with the problem.
The methods are called write-through and writeback.

With write-through, whenever a write reference occurs, the data is not only stored in fast memory,
but is also immediately copied into Main Memory.
This means that the Main Memory always contains
a valid copy of all data. If the controller wants to
overwrite a block in fast memory, this can be done
immediately, without losing any data.,
The advantages of write-through are its relative sim-

plicity and the fact that the Main Memory always
has correct data. The primary disadvantage is some
reduction of speed due to the need to access the

slow memory on every write reference. This is offset somewhat by the fact that write references are a
small fraction of all references to memory. In addition the cache does not have to wait for the Main
Memory to finish before starting the next cycle.

VI-1-6

Since a reasonable design would only cycle the
memory being written into and not all the parallel
memories in Main Memory, the system should not
even be held up by multiple sequential writes. However, some fraction of the time, the system will
have a read miss following a write, or two writes to
the same memory stack within Main Memory, and
then the system must wait. This causes the system
to run slightly slower than first-order estimates
would indicate.

The other method of handling the stale data problem in a cache system is called write-back. Under
this method, data written by the processor is only
stored in the fast memory, leaving the Main Memory unaltered and obsolete. A bit in the address
field of the block in fast memory, called the altered
bit, is set to indicate that this block contains new information. When the controller wants to overwrite
a block of fast memory, the altered bit is inspected
first. If this bit is set, the controller must write the
block into Main Memory before overwriting it.
The primary advantage of write-back is higher per-

formance. For almost any program, the number of
times an altered block must be copied into Main
Memory is less than the number of write references,
so write-back is noticeably faster than writethrough. One disadvantage of write-back is increased complexity. A write-back system must have
the ability to regenerate addresses from tags and
the extra sequencing logic to do double cycles.
Another disadvantage of write-back is the power

fail problem. When power fails, fast memory will
be holding the only valid copies of some arbitrary
set of locations. If these are not copied into Main
Memory, they will be lost. Since there is no way of
knowing which locations were lost, the entire memory must be considered volatile. If Main Memory is
volatile anyway, there is no problem; otherwise,
steps must be taken. One possibility is to require

the power fail program to do a sequence of reads
calculated to ensure that every block in the cache
has been overwritten. A more reliable, but more expensive system would automatically ensure that all
altered blocks are copied into Main Memory, after
the program halts, but before power disappears.

CHAPTER 2
PDP-11/70 CACHE

2.1

SCOPE

Bits 9-2 comprise the index field used to

This chapter describes the specific Cache which has
been implemented in the PDP-11/70 system. The

designate a set. A set consists of two

reader should be familiar with the cache concepts,

index position designated by the index

classifications, and definitions described in the pre-

field.

blocks, one in each group, located at the

vious chapter.

2.2

PDP-11/70 CACHE

Bit | designates the word (one of two in
the block).

The Cache used in the PDP-11/70 is two-way set associative. It consists of two groups of 256 blocks
each. Each block consists of two words; therefore,
the total data storage capacity of the fast memory

Bit 0 indicates the byte, as in all PDP-11
addresses.

is 1K words. The 11/70 Cache is implemented using

random

replacement

strategy

and

write-

NOTE

through.

This manual uses the term ‘‘address

Since the PDP-11/70 system uses a 22-bit address

field” to designate that part of an

space,

address

address which is stored in the Ad-

field, index field, and word field as illustrated in

dress Memory. The term ‘‘address

Figure 2-1 and outlined below.

tag” designates the tag used to iden-

the

address

is broken

down

into

tify data stored in the Cache. The

Bits

field

address tag thus consists of an ad-

used to identify a block of data in fast

dress field, a Valid bit, and two par-

memory.

ity bits.

21-10 comprise the

address

ADDRESS FIELD

——"

INDEX FIELD

WORD BYTE

BLOCKS

"WORD" FIELD

INDICATES

SET OF

;—W'—J

INDICATES WORD
AND/OR

BYTE WITHIN
A

BLOCK

11-2838

Figure

22-Bit Byte Address Breakdown
Words per Block, 256 Sets of Blocks)
2-1

VI-2-1

72BI1TS

e
36 BITS
ADDRESS BIT

ole

36BITS

I— 18 BITS —sle—18 8ITS —

)

(WORD FIELD)

BLOCK/SET
s

EVEN

GROUP ©

Iooo

000

EACH 18 BIT WORD
CONSISTS OF

GROUP 1

IEVEN

00D

16 DATA BITS PLUS
2 PARITY BITS

SET

BLOCK

jle—— WORD —»jt—— WORD ——»

i
{

ADDRESS BITS (9:2) _|

(INDEX FIELD)

256

NDEX

|
!
(

POSITIONS

|
|
|

|
1
|

]

{

]

3 77 8
DATA OUT

DATA OUT

(FOR REFERENCE)
MUX

HIT ON GROUP O
HIT ON GROUP 1
11-2839

Figure 2-2

2.2.1

Fast Data Memory Organization

Data Memory Organization

2.2.2

Address Memory Organization

Figure 2-2 illustrates the organization of the PDP-

The organization

11/70 Cache Fast Data Memory (FDM). Note that

trated in Figure 2-3, is determined by the Fast Data

the FDM consists of 256 sets = 512 blocks = 1024
words,

and

subdivided

into

two

equal

groups

(Group 0 and Group 1). Bits (9:2) of the incoming

address index into the FDM and select one of the
256 sets. (A set consists of two blocks, one in each
group.) Bit 1 of the incoming address enables either

the low (even) word or the high (odd) word within
the blocks that comprise the selected set to be gated

out of the FDM to a Cache Data Multiplexer. One
of these words will be selected if a hit is detected
upon address field comparison. The word selected
will be from the group upon which the hit occurs.

VI-2-2

of the Address

Memory,

illus-

Memory organization. The Address Memory is divided into two equal parts: the Tag 0 Address Memory and Tag | Address Memory, corresponding to

Group 0 and Group | of the Fast Data Memory.
Since an address tag field must be stored to identify
cach block in the FDM, 512 locations are required

for address tag fields; 256 of these locations are in
Tag 0 Address Memory, while the remaining 256 locations are in Tag

Address Memory.

Each ad-

dress tag consists of 15 bits. Therefore, the total
width of Address Memory is 15 X 2 = 30 bits.

30 BITS

e 15 BITS
1BIT

—»|

15 BITS —————

|le———128ITS

e—
2 BITS
PARITY

VALID BIT

o000

l_l ADDRESS FIELD

ADDRESS TAG FIELD

[}

ADDRESS BITS (9:2) _|

(INDEX FIELD)

| |

VALID BIT

ADDRESS FIELD

[

PARITY

256
INDEX

POSITIONS

377

ADDRESS BITS

(21:10)

(ADDRESS FIELD)

—% PARITY

> PARITY

CHECK

COMPARATOR

A=B

CHECK

COMPARATOR

A=B

MATCH O

MATCH 1

HIT O

HIT
1
11-2840

Figure 2-3

Address Memory Organization

VI-2-3

Ten bits are required to select one of the 1024

The address tag is organized as follows:

One bit is used to store a Valid bit; this

The remaining two bits are used to store
the address tag parity bits which verify
that the address tag has been properly

dress field comparators, which determine which of
the two groups (or equivalently, which of the two
blocks within the set) has the desired data. After
this last signal arrives, the data is available from
the data memory and will be sent to the processor

dress field.

words in Fast Data Memory. Eight of these bits are

the same index bits used to index into the Address
Memory. These bits select a set of two blocks, one
block in each group. Also required is bit 1 of the incoming address, which selects either the high or low

Twelve bits are required to store the ad-

bit indicates whether the address tag
(and therefore the FDM data corresponding to the tag) is valid.

loaded into the Address Memory.

When a memory cycle is performed, bits (9:2) of an
incoming address index into the Address Memory
and select an address tag in Tag 0 Address Memory
and Tag | Address Memory. The two address fields
are read from the Address Memory and compared
with the address field (bits 21:10) of the incoming

address. If either comparison results in a match, if
the corresponding Valid bit is set, and if no address
tag parity error is detected, HIT 0 or HIT | is asserted. These signals perform the final selection of
the words output from the FDM, as illustrated in

word of the blocks within the set. The last selection
is provided by the comparison signal from the ad-

or Unibus as required.

- If neither address field from
2.2.3.2 Read Miss
the Address Memory matches the address field of
the incoming address, then the requested data is
not in fast memory. This is called a miss condition.
When the Cache controller determines that there is
no match, it must start a Main Memory cycle to
fetch the required block. The block address will be
the 20 high order bits of the incoming address.

Figure 2-4.

During the Main Memory access time, the Cache
controller can decide where to put the incoming
data when it arrives. The index field determines
which block within a group is replaced. The con-

2.2.3 Cache Operation
When a 22-bit address arrives from the processor

or Unibus, bits (9:2) (the index field) are immediately used as an index into the 256 by 30 bit Address Memory, which contains the high order bits
(address field) of the addresses presently stored in
the Cache and their Valid bits. At the end of the
Address Memory access time, two tags are available for use. Each tag consists of a 12-bit address
field, a Valid bit, and two parity bits. The two address fields go directly to two comparators, where

they are compared with the 12 high order bits of

the incoming address. (The stored address tags are
checked for correct parity while the address fields

are compared. The following discussion assumes
that no address tag parity errors are detected.)

troller determines in which group the new block
will be placed by examining an internally generated
Random bit. When the data block arrives from
Main Memory, it is written into the selected block
of fast memory, while the requested word is passed
along to the processor or Unibus. At the same
time, the address field of the block is loaded into
the corresponding location in Address Memory
along with a set Valid bit. (A set Valid bit is loaded
into Address Memory whenever the Fast Data
Memory is loaded as a result of a read miss.)

2.2.3.3 Write Hit- During a write cycle initiated
from the processor or Unibus, the initial sequence
of events in the Cache is the same as during a read
cycle: the address comes in, the Address Memory is
accessed, and the address fields are compared. If
the address fields match and the corresponding
Valid bit is set, a hit is indicated and the new data

2.2.3.1 Read Hit - Assume that one of the address
comparisons results in a match and that the corresponding Valid bit is set. This condition is called a
“hit” and means that the word requested is in the
Fast Data Memory. The appropriate select signal is
therefore sent to the Fast Data Memory.

VI-2-4

is written into the appropriate word or byte of fast
memory, as selected by the index, word, and byte
fields of the address and the comparator outputs.
Since the PDP-11/70 Cache is implemented using
write-through, the data is also written into Main

Memory. This ensures that the data in the Main
Memory and in the Cache are never different.

TAG O
MEMORY

TAG 1

ADDRESS

VALID BIT —
¥

ADDRESS BITS (9:2)
(INDEX

FIELD)

o000
4

ADDRESS

PARITY

ADDRESS FIELD
ADDRESS TAG FIELD

VALID

ADDRESS FIELD

POSITIONS

|
|

|
|
|

ADDRESS BITS (21:10)
(ADDRESS

I—PARITY

256

MEMORY

BIT

377

—

FIELD)

S
—*" PARITY

PARITY
CHECK

CHECK

gfi“

COMPARATOR

At B

MATCH 1|

ADDRESS BITS 1,0
(WORD/BYTE SELECT)

) HITO
|/

o000
4

GROUP

lEVEN

oDD

BLOCK

256
POSITIONS

SET

|
|
|

I
|
|
|

|
|
|

Looo

BLOCK

——

|
|
|

INDEX

GROUP
1

lEVEN

le——WORD ——>f¢———WORD

(INDEX FIELD)

PAR
oK

AsB

MATCH O

ADDRESS BITS (9:2)

COMPARATOR

;

|
|

|
I

|
|
|
|

|
|

377

DATA

ouT

DATA OUT

1-2953

Figure

2-4

PDP-11/70

Cache

Path Diagram

VI-2-5

Simplified

Data
‘

2.2.3.4 Write Miss
- If, during a write operation
from the processor or Unibus, a miss is indicated

and that no verification (read operation) was per-

by the address comparison in the Cache, a write

Address Memory of the Cache are asserted. Ad-

cycle is performed to the specified address in Main
Memory. The contents of the Address Memory and
the Fast Data Memory are left unaltered.

dress 1000 is now loaded into the processor PC, the

formed. At this point, none of the Valid bits in the

ENABLE/HALT switch is set to

ENABLE, and

the START switch is depressed. Program execution,
summarized in Table 2-2, begins as follows:

2.2.3.5 Power-Up Initialization - On power-up, the
Cache performs a power-up sequence during which
all of the Valid bits in the Address Memory are
cleared. This is done because anything stored in the
Cache immediately after a power-up must not be
construed as valid data. As program execution begins, the density of read misses is high (because of all
the negated Valid bits), and data must be fetched
from Main Memory. As a result, the FDM gets filled

NOTE

The program used in this example is designed to illustrate Cache operations, not a typical use.

The processor initiates a fetch of the contents of address 1000.
a.

corresponding

and Valid bits get asserted. This in turn results in
fewer misses, i.e., a higher hit rate and greater speed
b.

FDM, as determined by the Random bit.

terns having correct parity. This is to ensure that

the bit patterns resident in the Address Memory

sponding

errors when program execution begins.
apparent

along

1000 are sent to the processor.

The processor initiates a fetch of the contents of address 1002.

The recently used data tends to be in
fast memory.

The Main Memory always has a correct

The address field (0000) is compared with the contents of the Ad-

copy of all data.

dress

The same Main Memory location never

0 of the FDM. (The match occurs
with the tag field loaded at step

index

position

Ic.)

ory locations at the same time.*

EXAMPLE

Memory

200. This results in a hit on Group

ends up in two different Fast Data Mem-

2.3

Memory

same time, the contents of address

the

ing paragraphs ensure that:

Address

with an asserted Valid bit. At the

reader that the mechanisms described in the preced-

The address field (0000) is loaded
at index position 200 of the corre-

and FDM upon power-up will not generate parity

The contents of addresses 1000 and

position) 200 of Group 0 of the

dress Memory and FDM are loaded with bit pat-

are

1002 are fetched from Main Mem-

bits are negated, all the remaining bits in the Ad-

should

bits

ory and loaded into block (index

At the same time that the Address Memory Valid

Overview - It

Valid

unasserted.

as program execution continues. The time interval
required for the memory system to achieve nominal
speed is only on the order of 1 ms.

2.2.3.6

This results in a miss, because the

PDP-11/70

CACHE

The requested word is sent to the
processor.

OPERATION

The following is an example illustrating Cache oper-

ations. Assume that the following sequence of
events has occurred. The system was powered up,
and the machine code listed in Table 2-1 was man-

ually loaded into core memory at the locations specified. Assume that the code was properly loaded
*This condition can occur, however, if the Control Register Force
Replacement bits are manipulated.

VI-2-6

The processor initiates a fetch of the contents of address location 5000.

The address

field (0002)

is com-

pared with the contents of Address

Memory

index

position

This results in a miss.

200.

The contents of addresses 5000 and
5002 are fetched from Main Memory and loaded into block (index

The

Cache

therefore

writes

the

data from the processor into the
specified

location

(3000) in

Main

position) 200 of Group 0 of the

Memory.

(This

illustrates

write-

FDM as determined by the Ran-

through.)

The

contents

of the

dom bit. The previous contents of
block 200 of Group 0, loaded at

FDM

Address

and

Memory

are

left unaltered.

step lc, are overwritten. This is because of the random nature of
group selection; the Random bit,

The processor initiates a fetch of the contents of location 1006.

as assumed in Table 2-2, happens
to be in the same state as it was
when

the

FDM

was

previously

field (0000)

is com-

dress

Memory

index

position

201.
b.

This results in a hit on Group 0 of

tents of location 5000 are sent to

the FDM. (The match occurs with

the processor.

the address field loaded at step 4c.)

The processor initiates a fetch of the con-

tents of location 1004.
a.

address

pared with the contents of the Ad-

loaded. The corresponding position
in Address Memory is also overwritten with the new address field
(0002). At the same time, the con-

The

address

processor.

field (0000)

is com-

pared with the contents of the Ad‘dress

Memory

The requested word is sent to the

index

The processor initiates a fetch of the con-

tents of location 1010.

position

201. Since the Valid bits at this in-

The

address

field (0000)

is com-

dex position are unasserted, this re-

pared with the contents of the Ad-

sults in a miss:

dress

Memory

index

position

202. This results in a miss.

= The contents of address 1004 and
1006 are fetched from Main Mem-

The contents of addresses 1010 and

ory and loaded into block (index

1012 are fetched from Main Mem-

position) 201

ory and loaded into block (index

of Group 0 of the

FDM, as determined by the Ran-

position)

dom bit.

FDM, as determined by the Ran-

202

of Group

0 of the

dom bit,

The address field (0000) is loaded
at index position 201 of the correAddress Memory along

The address field (0000) is loaded

sponding

at index position 202 of the corre-

with an asserted Valid bit. At the

sponding

same time, the contents of address

with an asserted Valid bit. At the

1004 are sent to the processor.

same time, the contents of address

Address

Memory

along

1010 are sent to the processor.

The processor now initiates a write to location 3000. (The data being written was

The processor now initiates a fetch of

previously fetched from location 5000.)

the contents of address location 3000.

The address

field (0001) is compared with the contents of Address
Memory at index position 200.

This results in a miss.

The

address

field

(0001)

Memory

index

position

This results in a miss.

VI-2-7

com-

pared with the contents of Address
200.

The contents of addresses 3000 and
3002 are fetched from Main Memory and loaded into block (index
position) 200 of Group 1 of the
FDM, as determined by the Random bit.

This results in a hit on Group O of
the FDM. (The match occurs with
the tag field loaded at step 7c.)

The requested word is sent to the

The address field (0001) is loaded
at index position 200 of the corresponding Address Memory, along

The processor increments the received
word and then initiates a DATO to
write it back into address location 1012,

processor.

with an asserted Valid bit. At the

same time, the contents of address
3000 are sent to the processor.

The address field (0000) is compared with the contents of Address
Memory at index position 202.

The processor now initiates a fetch of
the contents of address location 3002.
a.

The address field (0001) is compared with the contents of the Address

Memory

index

This

results in a write hit on
Group 0 of the FDM. (The match
occurs with the tag field loaded at
step 7¢.)

position
c.

200.

The Cache performs a write cycle
to Main Memory. (This is an illus-

This results in a hit on Group | of
the FDM. (The match occurs with
the tag field loaded at step 8c.)
The requested word is sent to the
processor.

of write-through.)

also

updates the high word at index position (block) 202 of Group 0 of
the FDM.

If the write operation

had been a DATOB, only the specified byte in the FDM (and Main
Memory) would be altered.

The processor now initiates a DATIP
type fetch of the contents of address location 1012,

tration

The address field (0000) is compared with the contents of Address
Memory at index position 202.

VI-2-8

The processor would now fetch the
HALT instruction at address 3004 (read
miss), execute it, and halt. It should be
clear that if the Random bit is asserted,
the contents of locations 3004 and 3006
will be loaded into block 201 of Group 1
of the FDM.

Table 2-1
Example Program

(all numbers in octal notation)
Address

Machine

Loaded

Index

Code

001000
001002

013737
005000

001004

Address

Field

[

Field

]

200

001006

003000

000137

[

201

]

001010

003000

202

001012

17777

Mpaemonics

Remarks

MOV @#5000@#3000
5000

0000

This program
moves the INC

3000

instruction at

JMP @#3000

address 5000

3000

to address 3000,

then jumps to

address

3000,

performs the
INC instruction,

003000

DONT CARE

003002
003004

001012
000000

[ 200

]

[

]

201

and HALTS

[

HALT

.
0001

005000

005237

[ 200 ]

INC @ #

0002

Table 2-2
Summary of Cache Operations Example
Processor
REF|

Random |

Bit

Operation

Fast Data Memo

GROUP 0

Hit /

KAssumed)|Miss | Block { Low Word High Word

[1000 | Fetch (1000) = 013737

11002 | Fetch (1002) = 005000

|1004 | Fetch (5000) = 005237

11004 | Fetch (1004) = 003000

Read

{1006 | Write 005237 into 3000

Write

[1006 | Fetch (1006) = 000137

Read|{

200

| (1000)=

(1002) =

013737

005000

Miss
Hit

| 200

Address Memory

GROUP |

Contents

TAG 0

Contents

|Block | Low Word

TAG |

ddress Memory

Address Memory

High Word | A ddress Field Loaded | Address Field Loaded

Remarks

0000

Fetch MOV instruction

Hit

Fetch source address

0002

Fetch contents at source address

0000

Fetch destination address

Read|

200 | (5000)=

Miss

(5002) =

005237

XXXXXX

Miss

!
201 | (1004)=

(1006) =

003000

000137

MOV contents of source to

Miss
Hit

| 201

destination address

Hit

Fetch JMP instruction

11010 | Fetch (1010) = 003000

{3000 | Fetch (3000) = 005237

Read

13002 | Fetch (3002)= 001012

Hit

13004 | Fetch (001012)=177776

Hit

11 {3004 | Write 177777 into 001012

Hit | 202

Read|

202

| (1010)=

(1012) =

003000

177776

Miss

0000

Miss

Fetch destination address

.
200}

(3000) =

(3002) =

005237

0001

001012

200

1 Hit

‘

’

13004 | Fetch (3004) = 000000

| 202

1(1010)=
|

Read

Miss

unaltered

JUMP: Fetch INC instruction

’

Fetch destination address

Hit

Fetch contents of destination

address (DATIP)

A Hit
|

(1012)=

[

177777

)

2011

(3004)=

000000

(3006)=

xxxxxx

INC and rastore (DATO)

! Fetch and execute HALT

)

J instruction

VI-2-9

CHAPTER 3
THEORY OF OPERATION

3.1

SCOPE

The address inputs to the Cache are 22 bits wide.

This chapter provides a detailed explanation of
Cache operation within the PDP-11/70 system.
Areas covered include PDP-11/70 data paths,
Cache data paths, Cache interfaces, and operational
flows for the various operations that the Cache can
perform. The latter is the key to a full understanding of the PDP-11/70 Cache.

The 22-bit address from the processor is derived by

mapping the processor’s 16-bit virtual address. The
22-bit address from the Unibus Map is derived by
mapping the 18-bit Unibus address. The 22-bit address from an MBC is the contents of a Memory
Address

(MAR).

(The

MAR

is an

ex-

tended register, and requires two Unibus DATO operations by the processor to specify a complete 22bit address.)

Data can be read from the Cache Fast Data Mem3.2

PDP-11/70 SYSTEM

Figure 3-1

ory (FDM) only during processor and Unibus Map

is a block diagram of the PDP-11/70

terconnect the functional components of the sys-

memory accgsses. During MBC memory accesses,
the Cache merely performs the required data transfers from the Main Memory Bus to the MBCs and

tem. The data lines connecting the Cache to the

vice versa. It can therefore be said that MBC cycles

Main Memory and to the Massbus Controllers are

are not ‘‘cached.” The reason for this is expained in

System showing the address and data lines which in-

36 bits wide, and comprise 32 bits of data plus 4

Paragraph 3.6. Note that because the data lines be-

parity bits. The remaining data lines are

tween the MBCs and the Cache are 36 bits wide,

16 bits

wide.

two 16-bit words (plus their associated byte parity

bits) can be transferred simultaneously.
The Cache, because of its function and position relative to the other functional components of the sys-

A 22-bit address input to the Cache is converted

tem, acts as a clearing house for all accesses to

into a Main Memory Bus address by stripping off

Main Memory. Requests for Main Memory access

the two least significant bits of the address. This is

come from three sources: processor, Unibus Map,

done because Main Memory is organized into two

and Massbus Controllers. When more than one of

word (i.e., double word) blocks. Each double word

the above require memory access concurrently, pri-

consists of two 16-bit data words plus their associ-

ority is given according to the following structure:

ated

parity

bits.

When

data is

read

from

Main

Memory, a 36-bit double word is transferred via
Ist Priority: Unibus Map

the Main Memory Bus. However, when data is writ-

2nd Priority: Massbus Controllers

ten into Main Memory, it is written on a byte-by-

3rd Priority: Processor

byte basis. There are lines on the Main Memory
Bus which determine which bytes will be operated

In addition, concurrent requests for memory access

on.

by Massbus Controllers are arbitrated in the Cache.

ignored.

VI-3-1

During

read

operation,

these

lines

are

_H0S3204d)|alabvay_.fir
o]

| _

)

0w12La/-I1ns3€-A1dS4d

V¥Q31iS5v1d93aY4

VI-3-2

3.2.1

3.3

Data Parity

During

processor

and

Unibus

Map

write

oper-

CACHE DATA PATHS

Figure 3-2 is a detailed block diagram of the data

ations, data parity bits are generated in the Cache.

paths in the Cache. Each block in the diagram refer-

The

ences

parity

bits

are

written

into

Main

Memory

along with the data. During a write hit, the data

the

location

the

engineering

drawings

where the logic schematics can be found. A detailed

and parity bits are also written into the Fast Data

description of the block diagram is given in Para-

Memory. Parity bits stored in memory (FDM or

graph 4.2.

Main Memory) are treated as data within the memory system.

The Cache checks for correct parity

when the data is read from memory by the pro-

cessor or Unibus Map. If a parity error is detected
by the Cache, a corresponding bit in the Memory
System Error Register is set. If, during a processor
read,

parity error is detected on the word re-

quested by the processor, an abort results. However,

parity

error

the

non-requested

word

3.3.1

Address Paths

Based

arbitration

among

its

three

ports,

the

Cache gates in address and control bits from the selected source. This function is performed by the Address

Multiplexer.

The

incoming

address

processed as described below.

results in a trap (unless traps are disabled). Parity
errors during Unibus Map read operations result in

a trap. If the parity error is on the requested word,

the Unibus parity error line (PB) is asserted.

Address bits (9:2) index into the Address Memory
to select two address tags (one from Tag 0 Address
Memory and one from Tag

Address Memory).

The two tags are checked for correct parity and, at

NOTE

the same time, compared against bits (21:10) of the

An abort occurs if the processor cannot be supplied

incoming

with valid data. If a requested word stored in the

parison

FDM is found to have bad parity, the Cache fetches
the backup copy of the word from Main Memory. If

address.

results

referenced

stored in the FDM.

ror handling is thus performed by the MBC’s service routine.

address

field

com-

if the corresponding

Valid bit is set, and if correct parity is determined,

incorrect parity, an abort results.
During an MBC cycle, data parity generation and

either
match,

a hit has been detected. This means that the data

the requested word fetched from Main Memory has

checking is performed in the MBC. MBC parity er-

If
a

the

incoming

address

currently

The address and operation control bits selected by

the Address Multiplexer are also used to generate
address and control

for the

Main

Memory

Bus.

Bits (21:02) of the incoming address are driven onto
the Main Memory Bus directly. Incoming address

3.2.2

Address Parity

The

Cache generates

parity

bits

for

the address

fields which are stored in the Address Memory as a

result of a read miss. When the Address Memory is
accessed to determine whether a memory cycle is a
hit or a miss, the contents of the Address Memory

are checked. Detection of a parity error in the Address Memory results in a trap.

bits A0l

and AO00 are used along with operation

control bits CI and CO to generate Main Memory
Bus

control

lines

MAIN

BYTE

MASK

3:0

and

MAIN C1:0. (Note that the MAIN C1:0 lines are

coded differently from the Unibus C1:CO lines.) In
addition, a parity bit is generated for the address

and control lines of the Main Memory Bus.

The Cache also generates a parity bit for the ad-

Bits (21:10) of the incoming address are applied to

dress and control lines of the Main Memory Bus.

a parity generator along with the internally gener-

The

ated Valid bit. The parity bits generated are applied

these lines; if incorrect parity is detected, a parity er-

Main

Memory

checks

for correct parity

to the inputs of the Address Memory along with

ror line on the Main Memory Bus is asserted. Fur-

bits

thermore, the addressed memory controller will not

loading. The Address Memory will be written if ei-

respond, and a time-out will occur.

ther a read miss or a write hit occurs.

VI-3-3

(21:10) of the incoming address for possible

receivers and loaded into the Bus Data Register.

bits are then driven onto the Main Memory Bus
data lines. The data is driven on both the low word
(MAIN DATA BYTE 1:0) and high word (MAIN
DATA BYTE 3:2) lines of the Main Memory Bus.
The data can thus be written into either the low

The even addressed word within the 36-bit double

word or high word locations in Main Memory.

3.3.2

Read Data Path

Data is read from Main Memory as 36-bit double
words when

a read

miss is detected. The 36-bit

double word is received by Main Memory Bus data

word is gated by the Even Multiplexer to the Cache

Data Multiplexer and to the FDM. The Odd Multi-

The output of the write multiplexer and the gener-

plexer performs the same function for the odd ad-

ated data parity bits are also applied to both the

dressed word within the 36-bit double word. The

Odd and Even Multiplexers. During a write oper-

data fetched from Main Memory is checked for cor-

ation, the Odd and Even Multiplexers select write

rect parity at the outputs of the Odd and Even Mul-

data as input to the FDM. When a write hit is detected, the write data is therefore available to update the FDM group on which the hit occurred.
The FDM is written on a byte-by-byte basis; only
the byte(s) referenced by the write operation are

tiplexers. The Cache Data Multiplexer gates out the

word requested to the device that initiated the read.
At the same time, the double word is written into
FDM

Group

selected

by the

Cache control logic. The index position which is
written

determined

During an MBC write to memory the Cache drives

field) of the incoming address.

During a read hit, data is read directly from the
FDM. Bits A09:02 of the incoming address index
into the FDM. Bit AOI of the incoming address enables either the odd or even word at the indexed location to be output from Group 0 and

of the

FDM. (Note that the odd and even word outputs
of each FDM group are common collectored.) The

two

words

(both

odd

altered.

bits A09:02 (the index

even

addressed)

are

checked for correct parity and applied to the Cache
Data Multiplexer. The Cache Data Multiplexer se-

the data

from

the Massbus Controller onto the

Main Memory Bus data lines. The MBCs can trans-

fer single bytes, single words, or double words. If
the Cache detects a hit during an MBC write operation, the FDM data on which the hit occurred is
invalidated. This is accomplished by negating the

Address Memory Valid bit which corresponds to
the FDM block on which the hit occurred. The en-

tire

FDM

block

(i.e.,

four

bytes)

thereby

invalidated.

lects the word from the group on which the hit occurred and routes it to the device which initiated
the read operation.

During an

MBC read operation, a 36-bit double

word

is received in the Cache by Main

Memory

Bus

data

Massbus

receivers

and

routed

the

3.4 PROCESSOR-CACHE INTERFACE
The signal lines routed between the processor and
the Cache may be categorized into two types:

Controllers.

3.3.3

Write Data Paths

The data to be written into memory is selected by

Master

Timing

and

Initialization

Control

Data Transfer Control

sequence, the write multiplexer outputs are forced to

The master timing and initialization control lines,
originating in the processor, are required by the
Cache for its overall operation. These lines route
system failure signals, initialization signals, and processor clock signals to which Cache operation is
synchronized. For reference, the signals which
make up the master timing and initialization control lines are listed in Table 3-1, along with the

all high. This keeps the data lines stable while data

functions they perform.

the write multiplexer, based on whether a processor

or Unibus Map cycle is being performed.
NOTE

Processor data

is selected by default if a Unibus

Map cycle, MBC cycle, or power-up sequence is not
being executed. During an MBC cycle or power-up

parity is generated.

The data transfer control lines are active in the
the data parity generator, which generates byte par-

transfer of data between the processor and Cache
memory. For reference, the signals are listed in

ity bits for the 16 bits of data. The data and parity

Table 3-2, along with their functions.

The outputs of the write multiplexer are applied (o

VI-3-4

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VI-3-5

Cache Data Paths Block Diagram

Table 3-1

Master Timing and Initialization Control Lines

Function

Signal

UBCE ACLOH

This signal is transmitted from the processor to the Cache to notify it

that ac input power to one of the power supplies in the system is
failing.

This signal is transmitted to the Cache to notify it that ac input power

UBCEDCLOH

to one of the power supplies in the system is below the point that

guarantees dc outputs to be in regulation.

Upon the negation of both of the above signals, the Cache performs its
power-up initialization sequence, clearing all the Valid bits in its Address
-

Memory.

This signal is asserted by the processor when it receives DC LO, AC L0,
or when a console reset (START switch depressed while in HALT) is

UBCE ROM INIT H

performed; it causes the initialization of all the timing state flip-flops
in the Cache.

Asserted by the processor upon receipt of AC LO or DC LO or when
the console START switch is depressed while the ENABLE/HALT

UBCE INIT H

switch is in the ENABLE position. This signal clears the Cache registers.

This is the processor free running clock to which Cache operations are

TIGC TF H

synchronized.

These are the processor T2 and T3 ROM time states (buffered) used
in the Cache to synchronize several particularly critical (timewise)

TIGC T2BH
TIGC T3BH

operations. [Examples are generation of CCBC MEM SYNC H and
generation of CCBC T2 DLY (1) H.]

Table 3-2

Processor-Cache Data Transfer Control

Function

Signal

DAPB BAMX 05-00 H

‘

These are the six low order bits of the physical address, gated directly
from the Bus Address Multiplexer (BAMX) in the processor. (The six

low order bits of the processor-generated virtual address are unaltered
in generating the 22-bit physical address.) Bit 00 is used to address the
FDM during DATOB operations. Bit 01 addresses the FDM to select
the desired word within a two-word block.

Bits 05 through 02 are part of the index field, and are used to index
into the FDM and Address Memory.

SAPJ PA 21-06 H

These are the 16 high order bits of the physical address, generated from

the virtual address by the Memory Management. Bits PA09-PAOQG are
part of the index field, and are used to index into the FDM and Address
Memory.

VI-3-6

Table 3-2 (Cont)
Processor-Cache Data Transfer Control
Signal

Function

SAPJ PA 21-06 H (cont)

Bits PA21-PA10 comprise the address field, and are compared with the
address fields stored at a selected Address Memory index position. They
will be loaded into the Address Memory should a read miss occur.

PDRB BR 15-00

These are the outputs of the processor Bus Register (BR), and comprise
a 16-bit data word to be stored in memory.

UBCCC1 BH

UBCCCOBH

RACH BUST H

These are the operation control lines, and indicate the type of operation

to be performed, as follows:

Cl1

Operation

DATI

DATIP

DATO

DATOB

Asserted by the processor during the “BUST” ROM state to initiate the
operation indicated by the C1, CO bits.

TMCE CACHE BEND H

Asserted by the processor to abort a memory operation initiated by

BUST H.
TMCE CONTROL OK H

Asserted by the processor during the “PAUSE’’ ROM state if it desires
to continue with the memory access operation initiated by BUST H.

CCBC MEM SYNC H

Asserted by the Cache and transmitted to the processor at the conclusion

of a memory access operation. This signal allows the processor to proceed past TS of the PAUSE ROM state. During a DATI/DATIP, it also
causes the read data to be loaded into the processor’s BR register.

DTMM CDMX
D15-D00 H

DTMM HI BYTE PAR H
DTMM LO BYTE PAR H

These 16 lines comprise the data word requested by the processor (or
Unibus Map) during a DATI/DATIP operation.

These signals are the parity bits for the low and high bytes of a requested
data word. They are loaded into the processor along with the data word,
and are used for console display purposes only.

DTMM BAD PARITY H

Transmitted by the Cache to the processor when a parity error has been
detected on a requested data word which has been fetched from Main
Memory.

CCBD CP TIMEOUT L

Transmitted by the Cache to the processor when a Main Memory Bus
time-out occurs during a CP cycle.

CCBJ PARITY ABORTH

Aborts the processor cycle when good data cannot be given to the
processor.

VI-3-7

Table 3-2 (Cont)

. Processor-Cache Data Transfer Control

Signal

CCBJ PARITY TRAPH
PDRH CACHE PERF L

Function

Transmitted to the processor by the Cache to indicate a soft* parity

error during a CP cycle or Unibus Map memory (i.e., nonregister) cycle.

Parity Error flag; this signal is transmitted by the processor to the
Cache upon receipt of CCBJ PARITY ABORT H or CCBD CP
TIMEOUT, and sets bit 15 (CPU ABORT) or bit 14 (CPU ABORT
AFTER LOCK) of the Cache Error Register.

TMCA PERF ACKN L

Transmitted by the processor to the Cache in response to CCBJ
PARITY TRAP H; causes its negation.

UBCB UBUS PAR ERR H

Negates CCBJ PARITY TRAP H when processor performs Unibus
parity error trap. Sets Error Register bit 09.

*A soft parity error is one which the Cache can recover from without processor intervention and still provide correct data, e.g.,
parity error in the nonrequested word; parity error in the Address Memory or FDM (if the copy of the requested word in Main Mem-

ory is fetched without error).

Processor Cache Protocol

The processor must receive MEM SYNC in order

To initiate a data transfer, the processor asserts

to proceed past TS of the “PAUSE” ROM state.

ADDRESS, CONTROL

AND DATA

CONTROL OK

MEM SYNC

r |
a.WRITE

BUST

detects a hit, the read data is accessed from the
FDM. The data is routed to the processor and the

)

If the processor is performing a read and the Cache

Cache asserts MEM SYNC, which causes the data

BUST

s o8

Figure 3-3 illustrates the processor-Cache protocol.

—

BUST, and generates an address, operation control
bits C1:0, and (if a write is being performed) data.
BUST initiates Cache timing. If the processor is performing a BUST-BEND sequence, or if the address
generated by the processor is a Unibus address,
CACHE BEND is transmitted to the Cache, and
brings it to its quiescent state. If the processor is
performing a memory access, the Cache receives
CONTROL OK from the processor. CONTROL
OK indicates that the processor-generated address,
control, and data bits are stable and valid, and is
treated as a “‘go ahead’ signal by the Cache.

ADDRESS AND CONTROL

to be loaded into the processor’s BR register.

( I

CONTROL OK

If a read miss is detected, the Cache fetches the
data from Main Memory. The Cache routes the requested word to the processor and then asserts
MEM SYNC. (Main Memory Bus protocol is de-

DATA

)

MEM SYNC

scribed in Paragraph 3.7)

READ

During a write operation, the Cache writes the data

11-4003

into Main Memory and then notifies the processor
Figure 3-3

by asserting MEM SYNC.

VI-3-8

Processor -~ Cache Protocol

3.5

UNIBUS MAP-CACHE INTERFACE

Memory

references by

Cache Register Accesses

Unibus devices are inter-

Unibus

Map-Cache

protocol

during

ac-

faced by the Unibus Map to the Cache. The pro-

cesses is similar to normal protocol except for the

cessor can also access memory via the Unibus and

following points:

Unibus Map; this is normally done only for maintenance and diagnostic purposes. However, in order

When the Unibus Map detects that the

to read or write any of the device registers located

Unibus address references a Cache de-

vice register, it asserts CACHE REG.

the Cache, the processor must do so via the

Unibus Map.

2.
For

reference,

the

signals

which

make

When

CACHE

REG

asserted,

the

Cache uses bits (03:01) of the Unibus ad-

Unibus Map-Cache interface are listed in Table 3-3

dress (gated by the Unibus Map) to ac-

along with their functions.

cess the desired register.
3.

to the Unibus Map, where it is latched

Unibus Map-Cache Protocol

by UB

The Unibus Map interfaces the Unibus data transa

data

transfer

from

memory,

the

device asserts

an 18-bit address, operation control

bits,

performing

and

Unibus.

(if

After a

write)

data

DONE if a register read oper-

ation is being performed.

fer lines to the Cache. When a Unibus device per-

forms

The data in the accessed register is gated

If a register write operation is being performed, the Unibus data (gated by the

the

Unibus Map) is written

deskew delay, the device asserts

into the speci-

fied register, and then the Cache asserts

MSYN.

UB DONE.

The Unibus Map generates a 22-bit

address from

the 18-bit Unibus address and gates the operation

control bits and (if performing a write) data to the
Cache. When the Unibus Map

receives MSYN on

the

REQUEST.

Unibus,

asserts

3.6

RH70-CACHE INTERFACE

The

Cache

Massbus

handles

memory

accesses

REQUEST in the Unibus Map. As Cache timing
progresses,

the address

from the Unibus

Map is

used to access into the FDM and Address Memory.

RH70

processor or Unibus Map memory accesses. MBC

REQUEST initiates Cache timing. The Cache responds by asserting UB ACKN; this negates UB

Controllers (MBCs) very differently than

{ {
1

ADDRESS ,CONTROL

AND DATA ___r

UB REQUEST

)

UB ACKN

—

UB DONE

If the operation is a read and a hit is detected, the
requested

word

routed

from the FDM

to the

Unibus Map, and the Cache asserts UB DONE.

This latches the data in the Unibus Map. If a read
miss

detected,

from

Main

the Cache must fetch

Memory.

The

Cache

routes

ADDRESS AND CONTROL

UB REQUEST

S______

the data
the

re-

UB ACKN

l (
!

quested word to the Unibus Map and then asserts
UB DONE.

writes the data into

tifies

the

DATA

During a write operation, the Cache

Unibus

Main

Map

f I

Memory and then no-

by asserting

DONE.

UB DONE

When the Unibus Map receives UB DONE, it ter-

minates its transaction on the Unibus by issuing
SSYN.

Figure

3-4

illustrates

Unibus

11-4004

Map-Cache

Figure 3-4

protocol during read and write operations.

VI-3-9

Unibus Map - Cache Protocol

Table 3-3

Unibus Map-Cache Interface Signals
Function

Signal
MAPA CA21-00H

These 22 lines are the physical address generated by the Unibus Map
from the 18-bit Unibus address.
Bit 00 is used to address the FDM during DATOB operations.

Bit 01 addresses the FDM to select the desired word within a two-word
block.

Bits 09 through 02 comprise the index field used to index into the FDM
and Address Memory.

Bits 21 through 10 comprise the address field, and are compared with
the address field stored at a selected Address Memory index position.
They will be loaded into the Address Memory should a read miss occur.
Bits 21 through 02 are also gated onto the Main Memory Bus in case a
cycle to Main Memory should be required.
MAPA DATA 15-00H

These are the Unibus data lines gated by the Unibus Map, and comprise
a 16-bit data word to be stored in memory (or written into a Cache device register).

MAPA ADRS 03-01 H

These three address bits are gated from the Unibus by the Unibus Map
to access a Cache register.

MAPB C1 H

MAPB COH

These are the operation control lines gated from the Unibus by the
Unibus Map. They indicate the type of operation to be performed, as
follows:

Operation

0
0
1
1

0
1
0
1

DATI
DATIP
DATO
DATOB

MAPF UB REQUEST (1) L

Asserted by the Unibus Map to initiate the operation indicated by the
C1, CO bits. This occurs after receipt of an address within the Unibus
Map response range, and MSYN, on the Unibus.

MAPB CACHE REG H

Asserted by the Unibus Map to indicate that a Cache device register,

rather than memory, is being accessed. When a Cache device register

is accessed, the Cache utilizes only bits 03 to 01 of the nonrelocated
Unibus address gated by the Unibus Map (MAPA ADRS 03-01 H).
CCBCUB ACKN L

Asserted by the Cache when the Unibus cycle has been initiated, to
negate UB REQUEST (1) L.

VI-3-10

Table 3-3 (Cont)
Unibus Map-Cache Interface Signals
Signal

Function

CCBC UB DONE

Asserted by the Cache to indicate that the Unibus Map memory

cycle (or Cache device register access) has been performed. This
causes the Unibus Map to accept read data from the Cache and to

complete the transaction on the Unibus.

CCBF REG D 15-00

These lines transmit read data from the Cache device registers to the
Unibus Map.

DTMM CDMX D15-D00 H

These 16 lines comprise the data word requested from memory by the
Unibus Map during a DATI/DATIP operation.

DTMM BAD PARITY H

Asserted by the Cache when a parity error has been detected on a re-

quested data word which has been fetched from Main Memory.
CCBD UB TIMEOUT L

Asserted by the Cache when a time-out has occurred on the Main Mem-

ory Bus during a Unibus Map memory access cycle.

MAPB PB DATAH

Transmitt~d by the Unibus Map to the Cache in response to DTMM
BAD PAKITY H if the parity error occurred on a valid access, i.e., on

an address within the Unibus Map’s response range. MAPB PB DATA H
inhibits clocking of the Cache Error Address register and sets various
bits in the Cache Error Register.

memory accesses always require cycles on the Main
Memory

Bus, whether or not the operation per-

formed is a read or a write, a hit or a miss. The
MBCs never read from or write into the FDM.
They only require the Cache to perform the Main
Memory Bus protocol needed to access Main Memory. Because the MBCs never read or write into the
FDM,

can

said

that

the

MBCs

are

not

cached.” The MBCs are handled this way for the
following reasons:

MBC data transfers differ in their statistical behavior from processor data transfers for which the Cache was designed.
If the MBCs ““cached,” data and codes
required

the

processor

would

swept out of the Cache.

Only single words can be output from
the

FDM, whereas the MBCs are ca-

pable of transferring double words.

For reference, Table 3-4 lists all the signals which
comprise the RH70-Cache interface, along with
their functions.

MBC-Cache Protocol

To initiate a data transfer to or from Main Memory an MBC asserts its request signal (Figure 3-5)
CTRLA (or B, or C, or D) REQ.
The

Cache arbitrates the simultaneous requests
from possibly four MBCs. The protocol proceeds
as follows if the request from MBC A is recognized

The Cache transmits SELADRS A to the selected
MBC, which responds by gating out address and
control lines to the Cache. When the Cache begins
executing the MBC cycle, the address and control
lines are latched in the Cache. As Cache timing proceeds, the Cache transmits SEL DATA CTRL A to
the selected MBC. If the MBC is performing a
write operation, this enables it to gate out write

VI-3-11

data. The Cache then asserts MBC REQ ACKN,
which negates the selected MBC’s request signal
and allows the MBC to alter the address and control bits transmitted to the Cache. The Cache now
performs a cycle on the Main Memory Bus. When
Main Memory responds with MAIN ACK, the
Cache transmits ADRS ACK to the MBC.

If a read operation is being performed, the Cache
routes the double word received from Main Memory to the MBC. When Main Memory asserts
MAIN DATA READY, the Cache transmits
DATA RDY CNTL “X” to the appropriate MBC.
(Although the Cache may be executing some other
cycle, it keeps track of which MBC is performing
the read operation.)

If a write to memory is being performed, this terminates the MBC-Cache transaction.

CTRL REQ

SEL ADRS

ADDRESS AND CONTROL

SELDATA

DATA

MBC REQ ACKN

ADRS

ACKN

CTRL

ADDRESS

REQ

SEL ADRS

AND CONTROL

—

SELDATA

MBC

REQ ACKN

ADRS ACKN

DATA

RDY

{1- 4005

Figure 3-5

RH70 - Cache Protocol

VI-3-12

Table 34

RH70-Cache Interface Signals

Signal

Function

CSTC CTRLA REQL
CSTC CTRLB REQ L

These are the memory access request signals generated by MBC A, B, C,
or D, respectively, and transmitted to the Cache Massbus Arbitrator.

CSTC CTRLCREQL

CSTC CTRLD REQL

CDPJ SELADRS CTRLA H
CDPJ SELADRS CTRLB H
CDPJ SELADRS CTRLC H
CDPJ SELADRS CTRLD H

One of these signals is asserted by the Cache Massbus Arbitrator to
select an MBC requesting memory access. The MBC which receives an
asserted SELADRS CTRL X signal is enabled to gate out a memory
address and control signals.

MBCBUS A21-A00 L

These lines transmit a memory address from a selected MBC to the
Cache. The address is latched in the Cache MBC Address Register prior
to the start of the MBC Main Memory cycle.

Bits 09 through 02 of the address index into the Cache Address Memory
(and FDM). Bits 21 through 10 are compared with the address field
stored in the Address Memory to determine whether a hit or miss condition exists. (On a write hit, the corresponding data stored in the FDM
must be invalidated.)

Bits 21—02 of the address are also gated onto the address lines of the
Main Memory Bus in order to perform the required Main Memory Bus
operation.

MBC BUS C1,C0,CX L

These are the operation control lines transmitted from the selected MBC

to the Cache. They are latched in the Cache along with the MBC

address. C1, CO, and CX determine the type of operation to be performed, as follows:

CDPJ SELDATACTRL AH
CDPJ SEL DATACTRL BH
CDPJ SEL DATACTRLCH
CDPJ SEL DATACTRLDH

Cl1

Operation

0
0

0
1

0
0

Read double word
Read double word

Write byte

Write single word

Write double word

One of these signals is transmitted by the Cache to the corresponding
selected MBC. The selected MBC is thereby enabled to gate out data
and parity bits to the Cache, if it is performing a write to memory. If
it is performing a read, it ignores the SEL DATA signal.

VI-3-13

Table 3-4 (Cont)
RH70-Cache Interface Signals

Signal

Function

MBCBUS D31-D24 L

These are the byte data lines and their corresponding parity bits. An

MBCBUS B3 PAL

MBC performing a write operation gates out data and parity bits onto

MBCBUS D23-Dl16 L

these lines when it receives a SEL DATA signal.

MBCBUSB2PAL
MBCBUS D15-D08 L
MBCBUSB1 PAL
MBCBUS D07-D00 L
MBCBUSBOPA L

CCBE MBC REQ ACKN L

Asserted by the Cache as it begins servicing an MBC request. This signal
is transmitted to all MBCs, and notifies the selected MBC to remove its

request and enables it to alter the current memory address.
ADML ADRS ACKN L

This signal (received by the Cache from Main Memory as MAIN ACK L)

is transmitted to all MBCs. The MBC which last received a SEL DATA
signal from the Cache is thereby notified that:
I.

Main Memory is responding.

If a write to memory is being performed, the current MBCCache write data transaction is now terminated.

CDPD MEM D31-D24 H

These are the data lines and their corresponding parity bits received

CDPD MEM BYTE 3 PAR H

from the Main Memory Bus in the Cache, and then transmitted to the

CDPD MEM D23-Di6 H

MBCs.

CDPD MEM BYTE 2 PAR H

CDPC MEM D15-D08 H
CDPC MEM BYTE 1 PAR H

CDPC MEM D07-D00 H
CDPC MEM BYTE 0 PAR H
CDPK DATA RDY CNTL AH

When the Cache receives DATA READY from Main Memory during an

CDPK DATA RDY CNTLBH

MBC memory (read) access operation, it transmits DATA RDY CNTL

CDPK DATA RDY CNTLCH

“X” H to the MBC which initiated the read. DATA RDY CNTL X

CDPK DATA RDY CNTL DH

loads the Main Memory data into MBC X and terminates the MBC

Cache transaction.

CCBD MBC TIMEOUT L

Asserted by the Cache when an MBC cycle results in a time-out on the
Main Memory Bus.

VI-3-14

3.7

MAIN MEMORY BUS

The

The Main Memory Bus interfaces the Cache with

Cache

places

six

control

bits

(MAIN C1:0 and BYTE MASK 3:0) de-

the Main Memory. The Main Memory Bus is a de-

fining the operation to be performed on

fined bus with bidirectional data lines. The address

the Main Memory Bus.

and control lines of the bus are unidirectional and
can only be asserted by the Cache. The Cache is

The Cache places a parity bit correspond-

thus the sole master of the Main Memory Bus; only

ing

the Cache can initiate data transfers on the Main

lines on the Main Memory Bus.

Memory Bus.
The Cache can perform two types of memory operations: a read and a write. When a read operation
is performed, the Main Memory transmits a 36-bit
double word to the Cache. A write operation, how-

ever, can be performed on specified bytes or words
within an addressed double word.

Address

the

above

address

‘

NOTE

lines

MAIN

and

A24:22

control

and

MAIN C0 are always maintained in
the negated state in the PDP-11/70.
The Cache selects a read operation
by negating MAIN C1 and selects a

write operation by asserting MAIN
Cl.

During a

four

Byte

write operation, the

Mask

bits

determine

Memory Bus is made up of four type

which of the four bytes within the ad-

BCO6R cables. Two cables carry the Main Memory

dressed double word will be operated

Bus data lines, while the other two carry the Main

on.

Memory Bus address and control lines. Each cable

serted, byte “X* of the double word

contains 40 conductors. Alternating conductors and

will be written. The Byte Mask bits

the cable shield are grounded to reduce crosstalk;

are negated by the Cache during a

The

Main

If BYTE

MASK

“X”

is as-

this leaves 20 conductors in each cable to carry the

read operation; this is done only to

Main

ensure that the lines remain stable

Memory Bus signals are asserted low (~0.4 V), and

while Main Memory checks for cor-

Memory

Bus

interface

signals.

The

rect parity for the address and con-

are high (~3.2 V) when negated.

trol lines. The Byte Mask bits are

For reference, Table 3-5 lists all the Main Memory
Bus signals and their corresponding cable conductor number and connector pin number, while
Table 3-6 describes the functions of these signals.

otherwise ignored by the Main Memory during a read operation.
If a write operation is to be performed,

the Cache gates out data onto the Main
Memory Bus data lines (MAIN DATA
BYTE 3-8:0-0). The Cache must wait until the bus data lines become unoccupied

Main Memory Bus Protocol

initiate a memory operation, the Cache per-

(MAIN

BOCC

negated)

before it can

gate out the data.

forms the following steps (refer to Figure 3-6):

After an access and deskew delay for the

The Cache places the address of the desired double word on the Main Memory

address, control, parity, and data lines,

Bus address lines (MAIN A24:02)

the Cache issues MAIN START.

VI-3-15

~p—~

ADDRESS
AND CONTROL

PARITY

%/////

ADDRESS 77

CACHE TO fi

MAIN MEMORY

/%————

S H

i
N

SIGNALS FROM

sYTE Mask /]

(ACKNOWLEDGE

SIGNALS

BUS OCCUPIED

CACHE FROM
{
MAIN MEMORY

—

DATA

DATA READY
a.WRITE

{
)

ADDRESS

AND CONTROL

BYTE MASK W//////////////////////////// |GNORED DURING READ OPERATION ////////////////////////////////%
MAIN MEMORY

I
N\

SIGNALS FROM
CACHE TO‘

ADDRESS %
PARITY

DATA 7//////////////////// i
START

|~—1 MINIMUM ACCESS TIME —sl

(ACKNOWLEDGE

SIGNALS TO

MAIN MEMORY

BUS OCCUPIED

¢
CACHE_FROM
DATA

3570 ————f

DATA READY

—»

|+ 50ns

b. READ
11- 4006

Figure 3-6

Cache - Main Memory Protocol

VI-3-16

Table 3-5
Main Memory Bus Signals
Function

Signal

MAIN A (21:02) L

This is the 20-bit address of a 2-word block located in Main Memory.

Function

Signal
MAIN BOCC L

During a read operation, this signal is asserted coincidentally with MAIN

They are the high order bits of a 22-bit physical address gated onto the

ACK by the active memory controller within Main Memory, and is kept

Main Memory Bus by the Cache. (Main Memory Bus address lines

asserted until the data is removed from the Main Memory Bus data lines

MAIN A24:22 are not used by the Cache, and are always maintained

[MAIN DATA BYTE (0-0:0-8; 1-0:1-8; 2-0:2-8; 3-0:3-8)] . The Cache

in the negated state.)

may gate data onto the Main Memory Bus data lines only when MAIN
BOCC is not asserted.

MAIN BYTE MASK 3 L

These bits define which of the 4 bytes within the block addressed by

MAIN BYTEMASK 2 L

MAIN A (21:02) will be operated on. There is a one-to-one correspond-

MAIN BYTEMASK 1 L

ence between bytes 3 to 0 and byte mask 3 to 0. If MAIN BYTE

MAIN DATA BYTE (0-0:0-8) L

MAIN BYTE MASK O L

MASK “X” is asserted, byte ““X” will be operated on. The byte mask

MAIN DATA BYTE (1-0:1-9) L

parity is utilized. MAIN DATA BYTE 1-9 and 3-9 L are not used in the

signals are derived by the Cache from the two low order bits of an in-

MAIN DATA BYTE (2-0:2-8) L

PDP-11/70 implementation. The MAIN DATA BYTE lines are organ-

coming address, operation control bits C1 and CO, and the CX bit if an

MAIN DATA BYTE (3-0:3-9) L

ized as follows:

MAIN
C (1:0) L

These are the data and data parity lines of the Main Memory Bus. Odd

MBC operation is being performed. The Main Memory ignores the mask

MAIN DATA BYTE (0-0:0-7)

— Byte 0 data

bits on all DATI/DATIP operations.

MAIN DATA BYTE 0-8

— Byte O parity

-MAIN DATA BYTE (1-0:1-7)

— Byte 1 data
-~

These bits, gated from the Cache, determine which operation is to be

MAIN DATA BYTE 1-8

— Byte 1 parity

performed by Main Memory. They are decoded as follows:

MAIN DATA BYTE (2-0:2-7)

— Byte 2 data

Operation

MAIN DATA BYTE 2-8

— Byte 2 parity

MAIN DATA BYTE (3-0:3-7)

— Byte 3 data

Read

Not used

Write

During a write operation, the Cache gates out data and data parity bits

Exchange (not used by PDP-11/70 Cache)

onto these lines while MAIN BOCC is negated, and then asserts MAIN

MAIN DATA BYTE 3-8

Byte 3 parity

START. Bytes are written into memory along with their parity bits.
MAIN

APARL

Which bytes are written is determined by the MAIN BYTE MASK bits.

This is an odd parity bit generated by the Cache (on drawing ADMJ)

The parity bits are generated in the Cache if a processor or Unibus Map

for the 26-bit control word consisting of MAIN A (21:02), MAIN C(1:0)

write cycle is performed. The parity bits are received from an MBC if

and MAIN BYTE MASK (3:0). This bit is received and checked by the

an MBC write to memory operation is being performed. During a read

Main Memory.

operation, Main Memory brings up all four bytes and their correspondMAIN START L

Asserted by the Cache to initiate the Main Memory cycle designated by

ing parity bits and places the information on the MAIN DATA BYTE

the MAIN C (1:0) bits on the Main Memory address locations designated

lines.

by the address and Byte Mask bits.
MAIN DATA READY L
MAIN PAR ERR L

MAIN ACK L

This signal is asserted by Main Memory during a read operation, after it

Asserted by the Main Memory if it detects a parity error in the 26-bit

has placed data on the MAIN DATA BYTE lines, to indicate to the

address and control word described above when START is asserted.

Cache that the requested data is available.

This signal is asserted by the addressed memory controller within

MAIN ACLOW L

Asserted by Main Memory to inform the processor that the ac power
input to a Main Memory power supply is failing.

Main Memory when it has actually started execution of the commanded
memory cycle. Receipt of MAIN ACK in the Cache allows it to alter

MAIN A (21:02), MAIN C (1:0), MAIN BYTE MASK (3:0), and

MAIN DC LOW L

Asserted by the Cache or Main Memory to inform the rest of the system

MAIN ADDR PAR lines on the Main Memory Bus, and to negate MAIN

that input power to a power supply somewhere in the system is below

START. If a write operation was just initiated, MAIN ACK indicates

the point that guarantees dc outputs to be in regulation.

that the Main Memory Bus transacticn is now terminated.

VI-3-17

VI-3-18

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Response of Main Memory

termed “‘stacking MBC reads.” When MBC reads

Each memory controller in Main Memory checks

are stacked, the Cache routes the DATA READY

for correct parity in the address and control lines.

signals

If a parity error is detected when MAIN START is

MBC.

from

Main

Memory

the

appropriate

received, MAIN PAR ERR is asserted on the bus.

If the addressed memory controller detects a parity

If the next cycle is a write operation, the Cache

error, execution of the memory cycle is inhibited

must also wait for MAIN BOCC to become unas-

and a time-out results.

serted, indicating that Main Memory is no longer

driving

the

bidirectional

data

lines of the

Main

Write Operation - When Main Memory begins exe-

Memory

cuting the requested memory cycle, it latches Main

data on the bus, wait the required data deskew de-

Memory Bus address, control, and data lines, and

lay, and issue MAIN START.

Bus.

The

Cache

may

then

assert

write

asserts MAIN ACK on the bus. With the required

information latched in Main Memory, active participation by the Cache is no longer necessary. When
the Cache receives MAIN ACK, it is notified that
the

Main

Memory

transaction

terminated.

MAIN ACK negates MAIN START in the Cache.
When

MAIN

ACK

becomes

negated,

the Cache

can again assert MAIN START if address, control,
and

data

(if

applicable)

have

been

sufficiently

deskewed.
Read Operation - When Main

Memory begins exe-

ACK

and

MAIN

BOCC. After the Main

Mcmory access delay, read data is placed on the
bus. After a data deskew delay, the Main Memory
asserts

MAIN

DATA

50 ns. The Main

data

OPERATIONAL FLOWS

This paragraph provides a dynamic description of

Cache operations. Flowcharts and flowchart descriptions are provided for each type of operation that
the PDP-11/70 Cache can perform. The flowcharts
illustrate the relationships and interdependence of
the various Cache functions. Specific references to

the Cache schematic diagrams are made for each

cuting therequested memory cycle, it latches Main
Mcemory Bus address and control lines, and asserts
MAIN

3.8

from

the

discrete function, allowing direct use of the flowcharts,

along

with

the

schematics,

trouble-

shooting the Cache hardware.

Only

five different symbols are used in the flow-

charts; these are defined in Figure 3-7.

READY for approximately

Memory then removes the read

bus,

and

simultaneously

negates

MAIN BOCC.
If the Cache is performing a processor or Unibus

OPERATION

PROCESS

Map cycle, the DATA READY signal latches the
Main Mcemory Bus data in the Bus Data Register

of the Cache. If the Cache is performing an MBC
OPERATION OR PROCESS REQUIRING TWO
OR MORE CONDITIONS TO BE MET

cycle, the Main Memory Bus data and a data ready
signal are routed by the Cache to the MBC performing the read from memory.

Initiation of Overlapped Cycles
When

performing

MBC

FIXED

read

operation,

the

DELAY

_l._

Cache does not need to wait for the assertion of
DATA

READY

before

can

initiate

the

NO CONDITIONAL

Main Memory cycle.

BRANCH

(ALSO USED TO IMPLEMENT
UNFIXED DELAYS)
YES

Il the next cycle is a read operation, the Cache can
assert MAIN START as soon as MAIN ACK is ne-

gated,

providing that the Main

dress

and

control

lines

have

Memory

been

PARALLEL

(FOLLOW

Bus ad-

stable for the

FLOW

BOTH

PATHS)
1-2857

required time period. Thus, two MBC read oper-

ations

may

performed

back

back:

this

VI-3-19

Figure 3-7

Flowchart Symbol Definitions

3.8.1

Processor Read Hit

Figure 3-8 is a flowchart illustrating Cache operation during a processor read hit. The processor
may initiate a data transfer only when it is in a
“BUST" ROM state. When the processor performs
a read operation, it generates a 16-bit virtual address and control bits C1 and C0. Memory Management converts the virtual address to a 22-bit
physical address which is routed to the Cache. During the BUST ROM

state, the processor asserts

BUST: this causes “BUST” HOLD to be asserted
in the Cache. A CP cycle will be initiated by the
Cuache if:

causes the Cache Data Multiplexer to gate out only
the odd addressed word from Group 0 of the
FDM: this word is routed to the processor.

When LOCK is asserted, a timing sequence is in-

itiated in the Cache. If the processor does not wish
to abort the read operation, it asserts CONTROL
OK. which, when received by the Cache, allows the
genceration of MEM
BUST

SYNC and the negation of

HOLD at TI180 of the Cache timing se-

quence. BUST HOLD negated prevents the Cache
from responding twice to the same processor BUST

cycle.

MEM

SYNC

routed

the processor;

The Cache is not presently servicing the
request of some other device.

!\)

receipt of MEM SYNC allows the processor to con-

The Cache is not presently waiting to ex-

tinue past time state TS of the “PAUSE” ROM
state. MEM SYNC also causes the data from the

Cache to be loaded into the processor’s BR.

ecute the write portion of a DATIP initiated by some other device.

At T180 of the Cache timing sequence, DONE is as-

scrted

thereby

There

are

other

requests

pending

(i.c., PRE UBUS or PRE MBC is not

the

brings

Cache.
the

This

Cache

negates
to

its

LOCK

and

quiescent

state.

With LOCK negated, the Cache can begin servicing

other requests for memory access.

asserted).

If the above conditions are satisfied when (or while)
BUST is asserted, or even if the above conditions

are satisfied when only BUST HOLD is asserted,
the Cache asserts CP CYCLE and LOCK. LOCK
indicates that the Cache is presently “locked’ into
an operating cycle (CP CYCLE in this case) and
that no other requests will be serviced until the
present cycle is completed. CP CYCLE causes the
address generated by the Memory Management to
be gated into the Cache by the Address Multiplexer. This address is processed in the Cache and,
at the same time, gated to the Main Memory Bus
(along with control bits), in case a slow cycle to

3.8.2 Processor Read Miss
Figure 3-9 is a flowchart illustrating Cache operation during a processor read miss cycle. The processor may initiate a data transfer only when it is in
a “BUST" ROM state. When the processor performs a read operation, it generates a 16-bit virtual
address and control bits Cl and C0. Memory Management converts the virtual address to a 22-bit
physical address which is routed to the Cache. During the “BUST"” ROM state, the processor asserts
BUST: this causes BUST HOLD to be asserted in
the Cache. A CP cycle will be initiated by the
Cache if:

Muain Memory will be required. Incoming address

The Cache is not presently servicing the

bits (9:2) address the FDM to select data to be

request

rcad. Incoming address bits (9:2) also address the

LOCK is not asserted).

of some

other

device

(i.e,,

Address Memory. Incoming address bits (21:10) are

checked against the contents of the Address Memory to determine whether the contents of the ad-

The Cache is not presently waiting to ex-

ecute the write portion of a DATIP in-

dress referenced are currently stored in the Cache.

itiated by some other device.

HIT 0 or HIT 1 will be asserted if the data being re3.

quested is in the FDM. Since this paragraph dis-

There

are

other

requests

pending

cusses processor read hits, assume HIT 0 is asserted

(i.e., PRE UBUS or PRE MBC is not

and

asserted).

that

odd

word

address

(XXXXXX2

XXXXXX0) is being read. Address bit 1 = 1 (odd
word address) causes the odd areas of the FDM to

If the above conditions are satisfied when (or while)

be enabled: therefore, an odd addressed word is out-

BUST is asserted, or even if the above conditions

put from each group of the FDM. HIT O asserted

are satisfied when only BUST HOLD is asserted,

VI1-3-20

CPU
TIME

PROCESSOR

CACHE

STATE*

CPU ENTERS
BUST ROM

STATE

|
ADDRESS &

OPERATION

CONTROL BITS
GENERATED

ASSERT BUST

[RACH)

ASSERT

BUST HOLD

{ccac)

CPU ENTERS
PAUSE ROM

INITIATE CACHE
TIMING SEQUENCE

STATE

ASSERT LOCK
:
{ccaB)

ASSERT CP
CYCLE

(cces)

(CCBE)

T30

OPERATION
ADDRESS &

CONTROL BITS
GATED INTO
CACHE

{ADME.F.J)

160

|
ADDRESS
PROCESSED

ADDRESS &
OPERATION

CONTROL BITS
GATED ONTO

MAIN MEMORY

T90

BUS

{ADML)

ASSERT

CONTROL OK

(TMCE)

ASSERT
HIT

I
T4

{ADMK)

T120

FDM DATA

SELECTED

(DTMC-M)

DATA GATED

NEGATE

OUT OF CACHE

BUST HOLD

{DTMM)

(cCBC)

T150
ASSEAT MEM
SYNC

(ccBC)

[
T8

T180

CPU RECEIVES

ASSERT DONE

(CCBC)

MEM SYNC

{TIGC)

)

LOADED

NEGATE LOCK

(cecBR)1]

CACHE

QUIESCENT

*The processor time states are intended

as a frame of reference only for events

11.2830

which occur in the processor.

Figure 3-8

Processor Read Hit
VI-3-21

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Processor Read Miss

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the Cache asserts CP CYCLE and LOCK. LOCK
indicates that the Cache is presently “locked” into

Memory Bus and, after a data deskew delay, the assertion of DATA READY. DATA READY, when
received in the Cache, loads the data on the Main

an operating cycle (CP CYCLE in this case) and
no other requests will be serviced until the

that

present cycle is completed. CP CYCLE causes the
address generated by the Memory Management to

be gated

into

the Cache by

the Address

Multi-

plexer. This address is processed in the Cache and,
at the same time, gated to the Main Memory Bus
(along with the control bits), in case a slow cycle to

Main Memory will be required. Incoming address
bits (9:2) address the FDM to select data to be read

if a hit occurs. Bits (9:2) of the incoming address
also address the Address Memory. Bits (21:10) of
the incoming address are checked against the contents of the Address Memory to determine whether
the contents of the address referenced are currently

stored in the Cache. HIT 0 or HIT 1 will be asserted if the data being requested is in the FDM.
Since this paragraph discusses processor read
misses, assume that neither HIT 0 nor HIT 1 is asserted.

Assume also that an odd address
(XXXXXX2 or XXXXXX6) is being read. Address

bit I = 1 (odd word address) causes the odd areas
of the FDM to be enabled and therefore an odd ad-

dressed

word

is output

from

each group of the
FDM. However, because SLOW CYCLE is asserted during this cycle (see below), the Cache Data
Multiplexer ignores the outputs from the FDM.
When LOCK is asserted, a timing sequence is initiated in the Cache. While this sequence is occur-

ring, the processor may abort the read operation by
issuing

a BEND during T2 of the ROM state fol-

lowing the “BUST”

ROM state.

However, if the’

Memory Bus into the Bus Data Registers. The outputs of the

Bus

Data

FDM

also

and

Registers are gated to the

the

Cache Data Multiplexer.
Since we have assumed that the processor is request-

ing

causes

odd

word,

the Cache

ADRS
Data

bit

The

receipt

both

MAIN

ACK

time-out by negating CCBE ALLOW TIMEOUT
.. When the time-out is inhibited, write pulses are

generated.

The write pulses load the two words
(block) brought from Main Memory into the FDM
and their address tag into the Address Memory.

Whether Group 0 or Group | of the FDM (and
corresponding Tag O Address Memory or Tag 1 Address Memory) is loaded is determined as described

Paragraph

4.7.

When

time-out

BUST

HOLD

negated

prevents

the

BUST

cycle.

START

SLOW

generates

SLOW

CYCLE and, after a 100 ns deskew delay, START
is asserted on the Main Memory Bus. START
causes the address and control bits presently on the

Main’ Memory Bus to be loaded into Main Mem-

ory.

The

memory

cycle

results

two

inhibited,

the processor. Receipt of MEM SYNC allows the
processor to proceed past TS of the PAUSE ROM

state, and also causes the data from the Cache to
be loaded into the processor’'s BR. When time-out
is inhibited, RESTART is also asserted in the
Cache. This asserts DONE, which negates LOCK
and

brings the Cache to

LLOCK

necgated,

the

its quiescent state. With

Cache

can

begin

servicing

Processor Write

Figure 3-10 is a flowchart illustrating Cache operation during a processor write cycle. The processor
may

initiate a data

transfer only when

it is in a

“BUST” ROM state. When performing a write to
memory, the processor/Memory Management trans-

mits data gated from the BR, a 22-bit physical address,

and

Cache.

During the “BUSTTM ROM state, the pro-

operation

control

bits Cl,

CO to

the

cessor asserts BUST: this causes BUST HOLD to

be asserted

in the Cache. A CP cycle will be in-

itiated by the Cache if:

A memory cycle is then started, and MAIN
ACK is transmitted from the Main Memory to the

Cache.

MEM SYNC SLOW is asserted and causes the assertion of MEM SYNC. MEM SYNC is routed to

3.8.3

sequence.

DATA

ory has responded properly. Therefore, these signals inhibit the generation of a Main Memory Bus

ROM state.

Cache from responding twice to the same processor

and

READY in the Cache indicates that the Main Mem-

other requests for memory access.

tion of BUST HOLD at T180 of the Cache timing

and

select

the
data stored in the Bus Data (High Word) Register
and gate it to the processor.

processor does not wish to abort the read operation, it asserts CONTROL OK at T3 of the
“PAUSETM ROM state following the “BUST”

CONTROL OK, when received by the Cache, allows the generation of START SLOW and the nega-

is asserted,

Multiplexer to

[8-bit

words being placed on the data lines of the Main

VI-3-23

The Cache is not presently servicing the
request

some

other

LOCK is not asserted).

device

(i.e.,

The Cache is not presently waiting to execute the write portion of a DATIP initiated by some other device.

There are no other requests pending
(i.e., PRE UBUS or PRE MBC is not
asserted).

If the above conditions are satisfied when (or while)
BUST is asserted, or even if the above conditions are
satisfied when only BUST HOLD is asserted, the
Cache asserts CP CYCLE and LOCK. LOCK indicates that the Cache is presently ‘“‘locked’ into an
operating cycle (CP CYCLE in this case) and that no

other requests will be serviced until the present cycle

“PAUSE"” ROM state following the *“BUST”
ROM state. CONTROL OK, when received by the
Cache, allows the generation of START SLOW
and the negation of BUST HOLD at T180 of the
Cache timing sequence. BUST HOLD negated prevents the Cache from responding twice to the same
processor BUST cycle. START SLOW generates
SLOW CYCLE and enables the assertion of
START on the Main Memory Bus 100 ns after the
bus becomes unoccupied (START WRITE asserted). START causes the address, data, and control bits presently on the Main Memory Bus to be
loaded into Main Memory. A memory cycle is then
started, and MAIN ACK is transmitted back to the
Cache.

is completed.

CP CYCLE causes the Cache Write Multiplexer to
select the processor data, thereby routing it to the
FDM and the high and low word Main Memory
Bus Data Drivers. When the Main Memory Bus
data lines become free (MAIN BOCC L negated),
the Cache enables the data word onto the Main
Memory Bus.

CP CYCLE also causes the address generated by
the processor and Memory Management to be
gated into the Cache by the Address Multiplexer.
This address is processed in the Cache and, at the
same time, gated to the Main Memory Bus (along
with the control bits). Incoming address bits (9:2)

address the FDM to select a block in Group 0 and
Group 1 which will be updated in case a hit occurs.
Bits 0 and | of the incoming address select the
word or byte in the selected blocks which will be

updated in case a hit occurs. Bits (9:2) of the incoming address also address the Address Memory.
Bits (21:10) of the incoming address are checked
against the contents of the Address Memory to determine whether the contents of the address referenced are currently stored in the Cache. HIT 0 or
HIT | will be asserted if the data being referenced
is in the FDM.

The receipt of MAIN ACK in the Cache indicates
that Main Memory has responded properly, and
therefore inhibits generation of a Main Memory
Bus time-out by negating CCBE ALLOW TIMEOUT L. When the time-out is disabled, write pulses
are generated if a hit has been detected. The write

pulses (DTMA LO BYTE WP 0*1 L, HI BYTE WP
0¥t L, LOBYTE WP 2*3 L, and/or HI BYTE WP
2*3 ) load the word or byte being written into the

on which the hit occurred at its proper
FDM group

position within the currently indexed block.
When time-out is inhibited, MEM SYNC SLOW is

asserted and causes the assertion of MEM SYNC,
which is routed to the processor. Receipt of MEM
SYNC allows the processor to proceed past TS of
th¢ PAUSE ROM state.

When time-out is inhibited, RESTART is also as-

serted in the Cache. This asserts DONE, which negates LOCK and brings the Cache to its quiescent
state. With LOCK negated, the Cache can begin
servicing other requests for memory access.

3.8.4

Processor BUST-BEND Cycle

Figure 3-11 is a flowchart illustrating Cache oper-

When LOCK is asserted, a timing sequence is initiated in the Cache. While this sequence is occurring. the processor may abort the read operation by
issuing a BEND during T2 of the ROM state following the “BUST” ROM state. However, if the
processor does not wish to abort the read operation, it asserts CONTROL OK at T3 of the

ation during a processor BUST-BEND cycle. The
processor often initiates a data transfer (by asserting BUST) that is immediately aborted in the next

ROM state (by asserting BEND). This allows the
processor to operate more quickly; data transfers
can be initiated earlier than otherwise possible and,
if they are not required, they are then aborted.

VI-3-24

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Processor Write

VI-3-25

CPU
TIME

PROCESSOR

CACHE

STATE*

l
CPU ENTERS

BUST ROM

STATE

(RACH}

ASSERT BUST

l
T4

ASSERT
BUST

{ceac)

HOLD

Locx
ASSERTED
on

YES

NON-CPU
DATIP

CPU ENTERS

BEND ROM STATE

INITIATE
CACHE
TIMING SEQUENCE

ASSERT

ASSERT CP

{cceat ook

CYCLE
{ccea)

ICCBE)

T30

OPERATION

ADDRESS, DATA &

CONTROL LINES
GATED INTO CACHE
& PROCESSED IN

I
T2

ASSERT
CACHE

BEND (TMCE)

CONTINUE

OPERATION

NORMAL MANNER

T60

T90

l
|

T120

NEGATE

BUST HOLD

tccech

7150

T180

ASSERT DONE
(ccee)

NEGATE LOCK

(cces)

CACHE

QUIESCENT
11-2831

*The processor time states are intended
as a frame of reference only for events

which occur in the processor.

Figure 3-11

Processor Bust-Bend Cycle

VI-3-26

Cache timing during a BUST-BEND cycle is sim-

ilar to that
of a processor read hit, as illustrated in
Figure 3-8,

During the “BUST”

ROM

state, the

processor asserts BUST: this causes BUST HOLD

3.8.5

Unibus Map Read Hit

Figure 3-12 is a flowchart illustrating Cache oper-

UNIBUS MAP

performing

read

operation

via

the Cache,

the

to be asserted in the Cache. A CP cycle will be in-

Unibus Map transmits a 22-bit address (generated

itiated by the Cache if:

from the

18-bit Unibus address) and Control bits

UNIBUS MAP
GENERATES
ADDRESS &

OPERATION
CONTROL BITS

Cl1. CO to the Cache, and asserts UB REQUEST.
1.

The Cache is not presently servicing the

request of some other device.

Cache internal clock (SYNC CLK), generates PRE

The Cache is not presently waiting to ex-

Cache operation to service the Unibus request if:

REQUEST,

UBUS
2.

CACHE

ation during a Unibus Map read hit cycle. When

(Pre

delayed

Unibus

and

Cycle),

synchronized
which

will

—

ASSERT
UB REQUEST

initiate

]
ASSERT
PRE-UB

ecute the write portion of a DATIP in-

{cces)

itiated by some other device.

The Cache is not presently servicing the
request of some other device.

There

are

other

requests

pending

(i.e.. PRE UBUS or PRE MBC are not

| 4

The Cache is not waiting to execute the

asserted).

write portion of a DATIP initiated by

some other device.

If the above conditions are satisfied when (or while)

—

BUST 1is asserted, or even if the above conditions

If the above conditions are satisfied, the Cache as-

are satisfied when only BUST HOLD is asserted,

serts UB CYCLE and LOCK. LOCK indicates that

the Cache asserts CP CYCLE and LOCK. (The pro-

the Cache is presently “locked” into an operating

cessor could assert BEND prior to the assertion of

cvele (UB CYCLE in this case) and that no other

LOCK. in which case BUST HOLD is immediately

requests will be serviced until the present cycle is

negated and the cycle is aborted before the Cache

completed.

actually

in-

ated by the Unibus Map to be gated into the Cache

dicates that the Cache is presently “locked” into an

by the Address Multiplexer. This address is pro-

begins

executing

the

cycle.)

LOCK

cessed in the Cache and, at the same time, gated to

no other requests will be serviced until the

the Main Memory Bus (along with control bits), in
case a slow cycle to Main Memory will be required.

cycle 1s completed. CP CYCLE causes the address,
control, and data bits currently being output from
the

processor/Memory

Management

be gated

and processed in the Cache, in the same manner
they

normally

would

for

read

write

operation.,
When

LOCK

is asserted, a timing sequence is in-

iiated in the Cache. While this sequence is occurthe processor may abort the operation by

ring.

issuing a BEND during T2 of the ROM state following

the

BUST

ROM

state.

When

it does so,

BUST HOLD is negated in the Cache and BEND
HOL.D is asserted.

BEND HOLD asserted causes

the assertion of DONE at T180 of the Cache timing scquence. This negates LOCK and thereby
brings the Cache to its quiescent state. With LOCK
negated. the Cache can begin servicing other
requests for memory access.

T30

ASSERT LOCK

gyssci? v

lccesl

(ccsa)

ASSERT UB

ADDRESS &

ACKN

OPERATION

{CCBC)

CONTROL BITS
GATED INTO

CACHE

{ADME F )

l
I

ADDRESS &

OPERATION

CONTROL BITS

T90

GATED ONTO

ADDRESS
PROCESSED

I
}

T150

T180

cusses Unibus Map read hits, assume that HIT 0 is
asserted and that an odd address (XXXXXX2 or

1 (odd

address) causes the odd areas of the FDM to be enabled and therefore an odd addressed word is output from cach group of the FDM. HIT 0 asserted

I
I

BUS
{ADML)

SSEE“T us
ON
{CCBC)

ASSERT

FDM DATA

HIT{0OR 1)

SELECTED

(ADMK}

{DTMC-M)

ASSERT DONE

{ccae)

NEGATE LOCK

(cces)

NEGATE
usCvcLE

DATA LOADED

MAIN MEMORY

T120
:

is in the FDM. Since this paragraph dis-

causes the Cache Data Multiplexer to gate out only

(CCBE)

REQUEST

ory to determine whether the contents of the address referenced are currently stored in the Cache.
HIT 0 or HIT 1 will be asserted if the data being re-

INITIATE CACHE

TIMING SEQUENCE

T60

Memory. Bits (21:10) of the incoming address are
checked against the contents of the Address Mem-

XXXXXX6) is being read. Address bit 1

NEGATE U8

Incoming address bits (9:2) address the FDM to select data to be read in case a hit occurs. Bits (9:2)
of the incoming address also address the Address

quested

UB CYCLE causes the address gener-

operating cycle (CP CYCLE in this case) and that
present

I |
i

icCcBB)

CACHE

QUIESCENT

the

odd addressed word from Group 0 of the
FDM: this word is routed to the Unibus Map.
UNIBUS
TRANSACTION

Note that during a BUST-BEND cycle, the pro-

When

cessor does not issue CONTROL OK. This pre-

itiated in the Cyche.

vents

the

Cache

from

asserting MEM SYNC.

starting

slow

cycle

LOCK

s asserted, a timing sequence is in-

COMPLETED

11.2829

At T30, UB ACKN is asserted

and transmitted to the Unibus Map. This signal negates the Unibus Map request, thereby preventing

Figure 3-12

Unibus Map Read Hit

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Unibus Map Read Miss

VI-3-28

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the same request from being serviced twice. At
T180, DONE is asserted in the Cache. This signal

dressed

word

FDM.

However,

generates UB DONE, which loads the FDM data

serted during this cycle (see below), the Cache Data

gated out of the Cache into the Unibus Map, and
causes the Unibus Map to terminate its transaction

Cache

into

its

quiescent

state

When

negating

LOCK, which in turn negates UB CYCLE. With
negated, the Cache can begin servicing

3.8.6

because

each group

SLOW

CYCLE

of the
is

as-

LOCK

is asserted, a timing sequence is in-

ittated in the Cache. At T30, UB ACKN is asserted
and transmitted to the Unibus Map. This signal ne-

LOCK

other requests for memory access.

output from

Multiplexer ignores the outputs from the FDM.

on the Unibus by issuing SSYN. DONE also brings

the

gates the Unibus Map request, thereby preventing

-the

same

request

from

being

serviced

twice.

T180. START SLOW s asserted in the Cache. This

Unibus Map Read Miss

asserts SLOW CYCLE and, after a 100 ns skew de-

Figure 3-13 is a flowchart illustrating Cache operation during a Unibus Map read miss cycle. When

START causes the address and control bits pres-

performing

a read operation via the Cache, the
Unibus Map transmits a 22-bit address (generated

ently on the Main Memory Bus to be loaded into

from

and MAIN ACK is transmitted back to the Cache.

lay, START is asserted on the Main Memory Bus.

Main

the

18-bit Unibus address) and control bits
Cl, CO to the Cache, and asserts UB REQUEST.
UB

REQUEST,

delayed

and

synchronized

Memory.

memory

cycle

is then started,

The memory cycle results in two 18-bit words being

placed on the data lines of the Main Memory Bus

Cache internal clock (SYNC CLK), generates PRE
UBUS (Pre Unibus Cycle), which will initiate

and,

Cache operation to service the Unibus request if’

in the Cache, loads the data on the Main Memory

after a

DATA

data

READY.

deskew delay, the assertion of
DATA

Bus into the Bus Data
I.

Registers. The outputs of

The Cache is not presently servicing the
request of some other device (i.e.,

also to the Cache Data Multiplexer. Since we have

LOCK not asserted).

assumed that the Unibus Map is requesting an odd

The Cache is not waiting to execute the
write portion of a DATIP initiated by

Cache Data Multiplexer to select the data stored in

some other device.

the Unibus Map.

the Bus Data Registers are gated to the FDM and

word,

READY, when received

ADRS

bit

asserted,

and

causes

the

the Bus Data (High Word) Register and gate it to

If the above conditions are satisfied, the Cache as-

The

serts UB CYCLE and LOCK. LOCK indicates that

READY in the Cache indicates that the Main Mem-

receipt

both

MAIN

ACK

and

DATA

the Cache is presently “‘lockedTM into an operating

ory

cycle (UB CYCLE in this case) and that no other
requests will be serviced until the present cycle is

nals inhibit the generation of a Main Memory Bus

time-out

completed.

L. When the time-out is inhibited, write pulses are

has

responded

properly. Therefore, these sig-

negating CCBE ALLOW TIMEOUT

UB CYCLE causes the address generated by the Unibus Map to be gated into the Cache

generated.

thc Address

Multiplexer. This address is processed in the Cache and, at the same time, gated to

words (i.c., the block) brought from Main Memory

the¢

Main

Address Memory. Whether Group 0 or Group | of

Memory

Bus

(along

with

the

control

bits). in case a slow cycle to Main Memory will be
required.

Incoming

address

bits (9:2)

address

the

The

write

pulses

load

the

two

18-bit

into the FDM and their identification bits into the

the FDM (and corresponding Tag 0 Address Memory or Tag

Address Memory) is loaded is deter-

FDM to sclect data to be read in case a hit occurs.
Bits (9:2) of the incoming address also address the

mined as described in Paragraph 4.7.

Address Memory. Bits (21:10) of the incoming address are checked against the contents of the Address Memory to determine whether the contents of

When time-out is inhibited, RESTART is asserted,
which in turn asserts DONE. DONE generates UB
DONE. which loads the data word gated out of the

the address referenced are currently stored in the
Cache. Since this paragraph discusses Unibus Map
read misses, assume that neither HIT 0 nor HIT |
is

asserted.

Assume

also

that

odd

address

(XXXXXX2 or XXXXXX6) is being read. Address
bit I = | (odd address) causes the odd areas of the
FDM

enabled

and

therefore

odd

ad-

Cache into the Unibus Map. The Unibus Map will
place the data word on the Unibus and then com-

plete its Unibus transaction. DONE also brings the
Cache into its quiescent state by negating LOCK,
which in turn negates UB CYCLE. With LOCK ne-

gated, the Cache can begin servicing other requests

for memory access.

VI-3-29

3.8.7

Unibus Map Write

Figure 3-14 is a flowchart illustrating Cache operation during a Unibus Map write cycle. When performing a write to memory, the Unibus Map
transmits data gated from the Unibus, a 22-bit physical address (generated from the 18-bit Unibus Address), and operation control bits Cl and CO to the
Cache, and then asserts UB REQUEST. UB
REQUEST., delayed and synchronized by a Cache
internal clock (SYNC CLK), generates PRE UBUS
(Pre Unibus Cycle), which will initiate Cache operation to service the Unibus request if:

The Cache is not presently servicing the
request of some other device (i.e.,

[

LOCK not asserted).

The Cache is not waiting to execute the
write portion of a DATIP initiated by
some other device.

If the above conditions are satisfied, the Cache asserts UB CYCLE and LOCK. LOCK indicates that
the Cache is presently “‘locked” into an operating
cycle (UB CYCLE in this case) and that no other
requests will be serviced until the present cycle is
completed.

UB CYCLE causes the Cache Write Multiplexer to
select the Unibus data, thereby routing it to the
FDM and the (high and low word) Main Memory
Bus Data Drivers. When the Main Memory Bus
data lines become free (MAIN BOCC L negated),
the Cache enables the data word onto the Main
Memory Bus.

UB CYCLE also causes the address generated by
the Unibus Map to be gated into the Cache by the
Address Multiplexer. This address is processed in
the Cache and, at the same time, gated to the Main
Memory Bus (along with control bits). Incoming address bits (9:2) address the FDM to select a block
in Group 0 and Group | which will be updated in
case a hit occurs. Bits | and 0 of the incoming address select a word or byte in the selected blocks

which will be updated in case a hit occurs. Bits
(9:2) of the incoming address also address the Address Memory. Bits (21:10) of the incoming address
are checked against the contents of the Address
Memory to determine whether the contents of the
address referenced are currently stored in the
Cache. HIT 0 or HIT 1 will be asserted if the data
being referenced is in the FDM.

When LOCK is asserted, a timing sequence is initiated in the Cache. At T30, UB ACKN is asserted
and transmitted to the Unibus Map. This signal negates the Unibus Map request, thereby preventing
the same request from being serviced twice. At
T180. START SLOW is asserted in the Cache. This
asserts SLOW CYCLE and enables the assertion of
START on the Main Memory Bus 100 ns after the
bus becomes unoccupied (START WRITE asserted). START causes the address, data, and control bits presently on the Main Memory Bus to be
loaded into Main Memory. A memory cycle is then
started, and MAIN ACK is transmitted back to the
Cache.

The receipt of MAIN ACK in the Cache indicates
that Main Memory has responded properly, and
therefore inhibits generatioh of a Main Memory
Bus time-out. When the time-out is inhibited, write
pulses are generated if a hit has been detected. The
write pulses (DTMB

BYTE WP 0*1

L, HI

BYTE WP 0*1 L, LO BYTE WP 2*3 L, and/or HI
BYTE WP 2*3 L) load the word or byte being written into the FDM group on which the hit occurred
al its proper position within the currently indexed
block. When time-out is inhibited, RESTART is asserted. which in turn causes the assertion of
DONE: DONE generates UB DONE, which is
transmitted to the Unibus Map and informs it that
the write operation has been executed; this allows
the Unibus Map to terminate its transaction on the
Unibus by issuing SSYN. DONE also brings the
Cache into its quiescent state by negating LOCK,
which in turn negates UB CYCLE. With LOCK negated, the Cache can begin servicing other requests
for memory access.

VI-3-30

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Unibus Map Write

VI1-3-31

3.8.8

Cache Register Read/Write

If a register write operation is being performed, a

Figure 3-15 is a flowchart illustrating Cache operation during a Cache register read or write. A
Cache register read or write operation is quite similar to a Unibus Map read hit. When the Unibus
Map decodes a Cache register address on the

CCBH CLK CONTROL REG L) at T60 of the
Cache timing sequence.

Unibus, it gates bits (03:01) (MAPA ADRS 03:01)
of the Unibus address and transmits MAPB
CACHE REG L to the Cache. When the Unibus
Map. receives MSYN on the Unibus, it asserts UB

At T180, DONE is asserted in the Cache. This sig-

REQUEST. UB REQUEST, delayed and synchro-

Unibus. DONE also brings the Cache into its quies-

nized by a Cache internal clock (SYNC CLK) generates PRE UBUS (Pre Unibus Cycle), which will
initiate Cache operation to service the Unibus

gates UB CYCLE. With LOCK negated, the Cache

request if:

access.

nal generates UB DONE, which enables the Unibus
Map to accept register data (if it is performing a

read)

and

terminate

its

transaction

the

cent state by negating LOCK, which in turn necan

begin

servicing

other

requests

for

memory

The Cache is not presently servicing the

3.8.9

request of some other device.

The flowchart in Figure 3-16 shows a single MBC

MBC Read From Memory

(MBC

requesting

memory

access.

If two

The Cache is not waiting to execute the

more MBCs request memory access concurrently,

write portion of a DATIP initiated by

Cache operation is similar. Multiple MBC requests

some other device.

are discussed in Paragraph 4.6, which describes the
Massbus arbitrator.

If the above conditions are satisfied, the Cache as-

MBCs requesting memory access assert their respec-

serts UB CYCLE and LOCK. LOCK indicates that

tive request signals [CSTC CTRLA (B, C, or D)

the Cache is presently ““locked” into an operating

REQ L]. The Cache MBC arbitrator receives these

cycle (UB CYCLE in this case) and that no other

requests

requests will be serviced until the present cycle is

MBCs.

and

The

arbitrates

among

MBC arbitration

the

requesting

logic asserts MBC

completed. UB CYCLE causes the 22 physical ad-

REQ and transmits SEL ADRS CTRL “X” H to

dress bits and the operation control bits (C1 and

the selected MBC (MBC A in this case). Receipt of

C0) to be gated into the Cache by the Address Mul-

the SEL ADRS signal enables MBC A to gate out

tiplexer. The 22-bit physical address gated out of

an address and operation control lines Cl1, C0, and

the Unibus during a Cache register operation is not

CX to the Cache. MBC REQ, delayed and synchro-

a valid address. It is gated into the Cache, indexes

nized by a Cache internal clock (SYNC CLK), gen-

into

may

erates PRE MBC (Pre MBC Cycle), which causes

cause HIT 0 or HIT | to be asserted; however, be-

the address and control bits gated out by the se-

cause MAPB CACHE REG L is asserted, assertion

lected

of CCBD START SLOW (1) H is inhibited; there-

Latch. PRE MBC will initiate Cache operation to

fore.

service the MBC request if:

the

FDM

and

Address

Memory,

and

reading or writing into the FDM

Memory

also

inhibited.

Address

or Main

bits

MBC to be loaded into the MBC Address

MAPA

ADRS (03:01) select the desired Cache register. The

The Cache is not presently servicing the

selected register data is gated out of the Cache to

request

the Unibus Map on the CCB REG D 15:00 lines

LOCK not asserted).

(whether

not

read

write

of some

other

device

(i.e.,

being
W]

performed).

The Cache is not waiting to execute the
write portion of a DATIP initiated by
some other device.

When LOCK is asserted, a timing sequence is in-

itiated in the Cache. At T30, UB ACKN is asserted
and transmitted to the Unibus Map. This signal ne-

There are no Unibus Map requests cur-

gates the Unibus Map request, thereby preventing

rently pending (i.e., PRE UBUS is not

the same request from being serviced twice.

asserted).

VI-3-32

CACHE

UNIBUS MAP

UNIBUS MAP
GATES ADDRESS,

& OPERATION
CONTROL BITS &

{IF WRITE) DATA
FROM UNIBUS

ADDRESS

ASSERT

BITS SELECT

CACHE REG

(MAPB)

READ DATA

{CCBF)

L
ASSERT
UB REQUEST

(MAPF}

7
ASSERT

PRE-UB

{cces)

'
I

INITIATE CACHE

TIMING SEQUENCE

éfi':i':’ vs

ASSERT LOCK

{cces)

(ccea)

{CCBE]

T30

ASSERT UB

ADDRESS & DATA

OPERATIONfi

INTO CACHE &

GATED INTO

PROCESSED IN

CACHE (ADMJ)

ACKN

LINES GATED

NORMAL MANNER

NEGATE UB

CONTROL BITS

REQUEST

ves

OPERATION
?
——

WRITE

Te0

T90

T120

T180

[
DATA LOADED

l
l

(CCBH J,K}

T150

SELECTED

ASSERT UB
DONE
(ccae)

ASSERT DONE
[{: 1]

NEGATE LOCK
(cces}

NEGATE

UBCYCLE
icces)

CACHE

QUIESCENT

(IF READ)

[

UNIBUS

TRANSACTION

11-2832

COMPLETED

Figure 3-15

VI-3-33

If the above conditions are satisfied, the Cache as-

At TI50 of the Cache timing sequence, DISABLE

serts MBC CYCLE and LOCK. LOCK indicates

REQ is negated. DISABLE REQ negated enables

that the Cache is presently “locked” into an operating cycle (MBC CYCLE in this case) and that no
other requests will be serviced until the present
cycle is completed. MBC CYCLE causes the address generated by the selected MBC to be gated
into the Cache by the Address Multiplexer. This address is processed in the Cache and, at the same
time, gated to the Main Memory Bus along with
control bits C1 and CO0. Incoming address bits (9:2)

clocking the MBC priority arbitration logic, caus-

presently on the Main

Memory Bus to be loaded

address the FDM and the Address Memory. Bits

into

(21:10) of the incoming address are checked against

started, and MAIN ACK is transmitted back to the

the contents of the Address Memory to determine

Cache.

ing selection of the next MBC if an MBC request is
pending.

At T180, START SLOW is asserted in the Cache.
This asserts SLOW CYCLE and, after a
skew

delay,

START

asserted

the

100 ns
Memory

Bus. START causes the address and control bits
Main

Memory.

memory

cycle

then

whether the contents of the address referenced are

currently stored in the Cache. HIT 0 or HIT 1 will

The receipt of MAIN ACK in the Cache indicates

be asserted

that

if the data being requested is in the

FDM:

however, since data is not read from the

FDM

during

MBC cycles,

these signals are not

the

Main

Memory

therefore, this signal

responding

properly;

Main Memory Bus time-out by negating CCBE ALLOW TIMEOUT

used.

inhibits the generation of a

ACK.

L. Also in response to

MAIN

the Cache transmits ADRS ACKN to the

When LLOCK is asserted, a timing sequence is in-

MBCs. Time-out inhibited causes the assertion of

itiated in the Cache. At T30 of the timing sequence,

RESTART, and this in turn causes the assertion of

DISABLE REQ is asserted. DISABLE REQ clocks

DONE. DONE brings the Cache into its quiescent

the MBC uarbitration logic and causes SEL DATA

state by negating LOCK. With LOCK negated, the

CTRL A to be transmitted to the selected MBC;

Cuache can begin servicing other requests for mem-

the MBC ignores this signal during a read from

Ory 1¢eess.

memory.

While

DISABLE

REQ

is asserted,

the

MBC arbitrator is prevented from arbitrating new

The memory cycle just initiated results in two 18-

incoming requests.

bit

words

being

placed

the data

lines of the

Main Mcmory Bus and, after a data deskew delay,

AL T60, MBC REQ ACKN is asserted. MBC REQ

the assertion of DATA READY. The Main Mem-

ACKN is transmitted to all the MBCs and notifies

ory Bus data is received in the Cache and routed to

the sclected MBC that it can negate its request and

the

alter the address and operation control bits.

Cache

MBCs.

The

routes

MBC

DATA

Arbitration

READY

Logic
the

the

MBC per-

forming the read operation (MBC A in this case)

At T120 of the Cache timing sequence, CLK PRI

by asserting CDPK DATA RDY CNTL A H. This

causes MBC A to accept the read data. Note that

(Clock

MBC

Priority)

priority

generated,

arbitration

logic;

and
this

clocks

the

records that

while

the

Cache

routing

the

MBC

data

and

MBC “*ATM is currently selected and will influence fu-

DATA RDY signals, it may already be in the midst

ture selections.

of servicing some other request for memory access.

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3.8.10

MBC Write to Memory

be asserted

if the data

being requested is in the

The flowchart in Figure 3-17 shows a single MBC

FDM. If HIT O or HIT

(MBC

sponding

requesting

memory

access.

If two

data

the

FDM

is asserted, the correwill have to be in-

more MBCs request memory access concurrently,

validated by loading a negated Valid bit into the

Cache operation is similar. Multiple MBC requests

Tag 0 Address Memory or Tag | Address Memory,

are discussed in Paragraph 4.6, where Massbus arbi-

respectively.

tration is described.
When LOCK

is asserted, a timing sequence is in-

MBCs requesting memory access assert their respec-

itiated in the Cache. At T30 of the timing sequence,

tive request signals [CSTC CTRL A (B, C, or D)
REQ L]. The Cache MBC arbitrator receives these

DISABLE REQ is asserted. DISABLE REQ clocks
the MBC arbitration logic and causes SEL DATA

requests

CTRL A

MBCs.

and

The

arbitrates

MBC

among

arbitration

the

requesting

logic asserts

MBC

REQ and transmits SEL ADRS CTRL “X” H to
the selected MBC (MBC A in this case). Receipt of

to be transmitted to the selected

MBC;

this enables the selected MBC to gate write data to
the Cache. The write data is gated onto the Main
Memory Bus by the Cache when MAIN BOCC be-

the SEL ADRS signal enables MBC A to gate out

comes

unasserted.

While

an address and operation control lines Cl, CO, and

serted,

the

arbitrator

CX to the Cache. MBC REQ, delayed and synchro-

arbitrating new incoming requests.

MBC

DISABLE
is

REQ

prevented

as-

from

nized by a Cache internal clock (SYNC CLK), gencrates PRE MBC (Pre MBC Cycle), which causes

the address and control bits gated out by the selected

MBC to be loaded into the MBC Address

Latch. PRE MBC will initiate Cache operation to
service the MBC request if
I.

ACKN is transmitted to all the MBCs and notifies

the selected MBC that it can negate its request and

alter the address and operation control bits.

The Cache is not presently servicing the

AL T120 of the Cache timing sequence, CLK PRI
H is generated and clocks the MBC priority arbi-

request

tration logic: this records that MBC A is currently

of some

other

device

(i.e.,

LOCK not asserted).
2

AL T60, MBC REQ ACKN is asserted. MBC REQ

selected and will influence future selections.

The Cache is not waiting to execute the
write portion

of a

DATIP initiated by

some other device.

AU TI50 of the Cache timing sequence, DISABLE
REQ 15 negated.

DISABLE REQ negated enables

clocking the MBC priority arbitration logic, causing sclection of the next MBC if an MBC request is

There are no Unibus Map requests currently pending (i.e.,

pending.

PRE UBUS is not

asserted).

AU TIR), START SLOW is asserted in the Cache.
This asserts SLOW CYCLE and enables the assertion of START on the Main Memory Bus 100 ns af-

Il the above conditions are satisfied, the Cache as-

ter the bus becomes unoccupied (START WRITE

serts

asserted). START causes the data, address, and con-

MBC CYCLE and

LOCK.

LOCK

indicates

that the Cache is presently ““locked” into an oper-

trol bits presently on the Main Memory Bus to be

ating cycle (MBC CYCLE in this case) and that no

loaded into Main Memory. A memory cycle is then

other

requests

cycle

is completed.

dress gencerated

will

present

started, and MAIN ACK is transmitted back to the

MBC CYCLE causes the ad-

Cache. The memory cycle results in the data being

serviced

by the selected

until

the

MBC to be gated

written into Main Memory. In response to MAIN

into the Cache by the Address Multiplexer. This ad-

ACK.

dress is processed in the Cache, and, at the same

MBCs: the MBC which initiated the write to mem-

time, gated to the Main

Memory Bus along with

control bits C1 and CO. Incoming address bits (9:2)

the

Cache

transmits

ADRS

ACK

the

ory is thereby notified that the Main Memory oper-

ation has been executed.

address the FDM and the Address Memory. Bits

(21:10) of the incoming address are checked against

The receipt of MAIN ACK in the Cache indicates

the contents of the Address Memory to determine

that

whether the contents of the address referenced are

Therefore,

currently stored in the Cache. HIT 0 or HIT | will

Main Memory Bus time-out.

VI-3-37

th¢

Main

Memory

this signal

has

responded

properly.

inhibits the generation of a

When time-out is inhibited, a write pulse is gener-

ated il a hit has occurred during the cycle. The
write pulse loads a negated Valid bit into the Address Memory (Tag 0 or Tag 1), thereby invalidating the FDM data words on which the hit
oceurred.

When time-out is inhibited, RESTART is asserted,
which in turn causes the assertion of DONE.
DONE brings the Cache into its quiescent state by
negating LOCK, which in turn negates MBC

CYCLE. With LOCK negated, the Cache can begin
servicing other requests for memory access.

VI-3-38

CHAPTER 4
DETAILED LOGIC

4.1

SCOPE

This

chapter

4.2.2

Address Multiplexer

Cache logic functions. Paragraph 4.2 provides a de-

The Address Multiplexer (Drawings ADME, F, J)
multiplexes address and operation control bits from

tailed description of the Cache data paths. Paragraphs 4.3 through 4.7 describe Cache timing and

The four sources are:

provides

detailed

descriptions

one of four sources to various logic in the Cache.

control logic. Paragraph 4.8 provides Cache register
definitions and describes the register logic.

Unibus Map - A 22-bit physical address

and Cl, CO operation control lines are
selected

4.2 BLOCK DIAGRAM DESCRIPTION
Figure 3-2 is a block diagram of the Cache, showing the major functional areas of the data paths.
Each block on the diagram references the location
of the represented logic in the schematics of the en-

Cache

implemented

four

hex-height

M8144 DTM (Data Memory)
M8145 CDP (Cache Data Paths)

The ADM, DTM, and CDP modules contain almost all of the data path logic illustrated in the

4.2.1

MBC Address Latch

The MBC Address Latch (Drawing ADMH) is
clocked by CCBB CLK MBC ADRS L and loaded
with an address (MBCBUS A21-A00 L) and oper-

ation control bits (MBCBUS Cl1, C0, CX L) gener-

cycle is

Processor/Memory Management - A 22-

MBC Address Latch
- A 22-bit address
and Cl, C0O, CX operation control lines,
generated by a selected MBC and presently stored in the MBC Address Latch,
are selected when an MBC cycle is being
executed by the Cache.

block diagram. The CCB module contains the regis-

ter data paths and almost all the timing and control

Map

Cache.

logic in the Cache.

Unibus

ation control lines are selected when a
processor cycle is being executed by the

modules;

M8142 CCB (Cache Control Board)
M8143 ADM (Address Memory)

bit physical address and Cl, CO oper-

gineering print set.

The

when

being executed by the Cache.

Power-Up Address Logic - An 8-bit address generated by a counter within the
Cache (Drawing ADM)) is selected during the Cache power-up initialization sequence. During the power-up sequence,

this address is incremented from 0 to
255 while, at the same time, it is used to
index into the Address Memory. At each
address, both Tag 0 Address Memory
and Tag 1 Address Memory are loaded

ated by a selected MBC. CCBB CLK MBC ADRS
is asserted just prior to the execution of an MBC
cycle by the Cache. With the address and operation
control bits latched in the Cache, the MBC may
unassert or alter these lines upon receipt of CCBE
MBC REQ ACKN L from the Cache. The outputs
of the MBC Address Latch are routed to the Ad-

ity. The negated Valid bits indicate that
the address tag fields (and therefore the
corresponding data in the FDM) are invalid. This is equivalent to the FDM

dress Multiplexer.

being empty.

VI-4-1

with negated Valid bits and correct par-

Selection

is based on the state of signals CCBB

Used to generate Main

AMS SO H and CCBB AMX S1 H, which are as-

Memory Bus Byte Mask

serted as follows:

bits (during MBC cycles
only).

Operation

CP Cycle

operation

Power-Up

and Byte Mask bits are

MBC Cycle

gated

UB Cycle

Memory Bus along with

Address Bits (21:02)

The Main Memory Bus
control

onto

the

bits
Main

a parity bit correspondThe outputs of the Address Multiplexer are used as

ing to these lines.

follows.

Address Bits (21:10)

Used

for

with

the

comparison
address

fields

4.2.3

Main Memory Bus Control Generator

This circuitry (Drawing ADMJ) generates the Main

at the selected Address

Memory Bus Byte Mask bits (BYTE MASK 3:0),

Memory index position.

operation control bit MAIN CO0, and the address
and control parity bit (ADMJ ADRS PARITY H).

Used to index into the

Address Bits (09:02)

FDM

and

Address

Main Memory Bus operation control bit MAIN ClI

Memory.

is always maintained in the negated state, as illus-

Used to select a desired

therefore solely determines whether the Main Mem-

word in the FDM dur-

ory operation will be a read or a write. MAIN C0

trated on Drawing ADML. The state of MAIN CO

Address Bit 01

ing read or write oper-

is derived from the Cl operation control bit that is

ations.

selected as input to the Cache by the Address Multi-

select the desired word

plexer. If the selected C1 input is negated, ADMJ

in Main Memory during

READ L is asserted, and in turn negates MAIN C0

Also

used

write operations.

L on the Main Memory Bus. The MAIN CI1:0 signals are thereby encoded for a read operation.

Used to select a desired

Address Bit 00

byte

Main

the

FDM

Memory

and

during

DATOB operations.

The Byte Mask bits are generated by decoding operation control bits C1:0 (and CX during MBC cycles) and address bits A01:00, which are selected by

the
Cl, CO

Address

Multiplexer.

The

decoding

per-

Determine the operation

formed by a pair of type 74S153 dual 4 to 1 multi-

be performed.

Used

plexers. If a read operation is to be performed on

generate

Main

the

Main

Memory

Bus,

ADMJ

READ

L is as-

Memory

Bus operation

serted. This negates the multiplexer strobe inputs

control

bits

and

C0:Cl1

MAIN

L. Also used to

forces

all

BYTE MASK

the

multiplexer

3:0 H) low.

outputs

(ADMJ

During a write oper-

generate the Main Mem-

ation (ADMJ READ L negated), the multiplexers

ory Bus Byte Mask bits

are strobed and cause Byte Mask bits to be gener-

and

ated as listed in the table on drawing ADMJ.

address

bits

AOI

and A00.
An address and control parity bit (ADMJ ADRS
NOTE

PARITY H) is generated for the address and con-

Operation control bits C1, C0 are multiplexed by an

trol lines of the Main Memory Bus. The parity bit

extension

is generated in a slightly unconventional manner, in

of the

Drawing ADMJ.

Address

Multiplexer, located on

order to minimize the required logic.

VI-4-2

The following signals are input to the final parity

4.2.6

Index Field Inverter-Drivers

generator chip:

The

Index

Field

Inverter-Drivers

(Drawings

ADMA, C) are used to invert bits (9:2) (index field)
1.

ADMIJ PARA GEN H - This signal is a
parity bit for address lines 21:15.

of the incoming address, and simultaneously to provide sufficient drive to allow these signals to address

ADMJ PARB GENO H - This is a Tag
0 Address

all

the

chips

that

comprise

the

Address

Memory. The Index Field Inverter-Drivers consist

Memory parity bit for bits

of two sets, as illustrated in the block diagram. One

14:10 of the address and the Tag 0 Valid

set supplies drive for the Tag 0 Address Memory

bit (CCBM VALID 0 INPUT L).

address inputs (Drawings ADMA, B). The other set
performs the same function for the Tag 1 Address

CCBM VALID 0 INPUT L - This sig-

Memory (Drawings ADMC, D).

nal counteracts for CCBM VALID 0 INPUT L used in generating ADMJ PARB

4.2.7

GENO H.

The Address Memory (Drawings ADMA, B, C, D)

Address Memory

is comprised of the Tag 0 Address Memory and
4.

ADMJ

DATOB

H - This signal repre-

Tag | Address Memory, each containing 256 15-bit

sents parity for the Byte Mask bits. An

address tags. The tags consist of a 12-bit address

odd number (actually one) of Byte Mask

field, a Valid bit, and two parity bits. The Tag 0

bits will be asserted only if this signal is

Address Memory (Drawings ADMA, B) contains

asserted.

the address tags for data stored in Group O of the

ADMJ READ H - This signal, used to

ADMC, D) contains address tags for data stored in

generate MAIN CO, represents parity for

Group 1.

FDM, while the Tag | Address Memory (Drawings
5.

MAIN C1:0, since MAIN CI is always
negated.

The

The Tag 0 Address Memory consists of 15 type 19-

12069

remaining

input

represents

parity

for bits (09:02) of the Main Memory Bus
address.

random

access

memory

chips.

Each

chip

stores | bit position of the 15-bit address tag. Eight
address inputs provide 256 address locations. Data
being accessed is available at the Y (pin 6) output.

Data to be stored is applied to the DI input (pin

Main Memory address bits (24:22) are always maintained in the negated state, and therefore are not

13), and is written by a low pulse at pin 12.

used in generating the parity bit.

The Tag

4.2.4

The index field of an incoming address (bits 09:02)

Main Memory Bus Address Drivers

These drivers (Drawing ADML) drive bits (21:2) of

the

address

selected

Address Memory is structured in an

identical manner.

the Address

Multiplexer

(along with operation control lines MAIN C1:0)
onto the Main Memory Bus. The Cache thus anticipates a cycle to Main Memory whenever the Ad-

dress Multiplexer makes an address selection. Note

that signal MAIN C1 is always maintained in the
negated state.

is used to index into the Tag 0 and Tag 1 Address
Memory. The address tags thus accessed are then
checked against the address field of the incoming

address (bits 21:10) by the Tag O and Tag 1 Address,

Parity,

and

Validity

Checkers

(Drawing

ADMK) to determine whether the contents of the
incoming address are presently stored in the Cache.

The address memory is written with a new address
tag whenever new data is loaded into the FDM as

4.2.5

a result of a read miss. Also, whenever an MBC

Address Field Inverter

The Address Field Inverters (Drawings ADME, F)

write hit occurs, the Valid bit of the address tag on

perform a simple inversion of bits 21 through 10 to

which the hit occurred is negated; this invalidates

allow for comparison in the parity, address, and

the

validity check circuitry. The inverters compensate

non-MBC write hit occurs, the Address Memory is

for

written, but its contents do not change; the address

the

inversion

performed

the

Address

corresponding

block

the

FDM.

(When

tag written is the same as the old address tag.)

Memory.

VI-4-3

Note that the Tag 0 Address Memory is written
whenever data in Group 0 of the FDM is modified
or invalidated (ADMJ WP H and CCBM WRITE
SEL 0 H is asserted), while the Tag 1| Address
Memory is loaded whenever data in Group 1 of the
FDM is modified or invalidated (ADMJ WP H
and CCBM WRITE SEL 0 H asserted).

Checker performs a parallel check to determine

4.2.8

Valid Bit Generator
The Valid Bit Generator (Drawing CCBM) gener-

ates the Valid bits to be stored in the Address Memory. If data is loaded into the Fast Data Memory
as a result of a read miss, the Valid bit associated
with the corresponding location in Address Memory is asserted. Two Valid bits are generated by this
circuitry: CCBM VALID 0 INPUT L and CCBM
VALID 1 INPUT L. They are generated as inputs
for the Tag 0 Address Memory and Tag | Address
Memory, respectively. The circuit used to generate
these signals is discussed in detail in Paragraph 4.7.
4.2.9

whether valid data corresponding to the same address is stored in Group 1.

The Tag O check is performed by comparing address bits (21:10) coming from the Address Multiplexer with address bits (21:10) stored in the Tag O
Address Memory location selected by incoming address bits (9:2). If bits (21:10) of the incoming and
stored addresses match and the Valid bit in the addressed location of the Tag 0 Address Memory is
asserted, the Tag O Parity, Address, and Validity
Checker asserts ADMK GROUP 0 AMATCH H.
If no parity errors were detected on the address tag
ADMK GROUP 0 PARA OK H and ADMK
GROUP 0 PARB OK H are asserted), ADMK
GROUP 0 HIT L is asserted. This indicates that
the content of the memory address being accessed
is presently in Group 0 of the FDM. A hit on
Group 0 results in the following:

Address Memory Parity Generator

The Address Memory Parity Generator logic generates the following odd parity bits (Drawings
ADMEF, J) for loading into the Address Memory:
1.

One parity bit (ADMF PARA GEN L)
is generated for bits (21:15) of the in-

During a non-MBC read, data will be
fetched from the FDM at high speed
without requiring a slow cycle to Main
Memory (unless an FDM parity error is
detected on the requested word).
During a non-MBC write, the data word

coming address, and can be loaded into

in Group 0 of the FDM on which the

either the Tag 0 Address Memory or

hit was made will be updated.

Tag | Address Memory.

3.
2.

One parity bit (ADMJ PARB GEN 0
H) is generated for bits (14:10) of the incoming address plus the VALID 0 INPUT

bit,

for

into

the Tag 0

During an MBC write, the data word in
Group 0 of the FDM on which the hit
was made will be invalidated by negating

the Valid bit stored in the Tag 0 Address
Memory location selected by bits (9:2) of

Address Memory.

the incoming address. Negating this
Valid bit invalidates both the odd and

One parity bit (ADMF PARB GEN 1
H) is generated for bits (14:10) of the in-

even words in Group 0 addressed by bits
(9:2) of the incoming address.

coming address plus the VALID 1
PUT

bit,

for loading

into

IN-

the Tag

This logic, represented by two blocks on the block

Detection of a hit on Group 0 and/or Group 1 can
be inhibited by setting bits 4 and/or 5 of the Control Register (17 777 746). This asserts CCBH
FORCE MISS GP0 and/or CCBH FORCE MISS
GPI, thereby preventing detection of address equal-

diagram, is located on Drawing ADMK. The Tag 0

ity by the comparators.

Address Memory.

4.2.10

Tag 0 and Tag 1 Parity, Address, and Valid-

ity Checker

Parity, Address, and Validity Checker determines
whether valid data, corresponding to the incoming

address

selected by the Address Multiplexer, is
Group 0 of the Fast Data Memory
(FDM). The Tag ! Parity, Address, and Validity
stored

VI-4-4

Setting bits (11:08) of the Maintenance Register (address 17 777 750) forces detection of parity errors
by the parity checkers.

4.2.11 Write Data Multiplexer
The Write Data Multiplexer (Drawing CDPE) selects write data from either the BR of the processor
or from the Unibus Map, depending on whether a
memory access is being performed from the processor or the Unibus Map.

The two parity bits are also routed, along with the

data from the Write Multiplexer, to the Even Multiplexer and Odd Multiplexer to allow updating of
the Fast Data Memory if a write hit occurs.
4.2.13

Main Memory Bus Data Drivers

These drivers (Drawings CDPC, D) drive the data

The output of the Write Data Multiplexer is fed to
the Main Memory Drivers to be driven across the
Main Memory Bus to Main Memory. The data is
placed on the Main Memory Bus as soon as the
bus becomes vacant (BOCC not asserted and MBC
read cycle not being performed).

selected by the Write Data Multiplexer (i.e., pro-

cessor or Unibus Map data) and the corresponding
byte parity bits (generated by the Data Parity Generator from the selected data) onto the data lines of
the Main

Memory Bus. The

18 bits of data and

data parity are driven concurrently on the MAIN
DATA BYTE (0-0:0-8) (1-0:1-8) and MAIN DATA

The write data output of the Write Multiplexer is
also applied to the A inputs of the Even Multiplexer and the Odd Multiplexer. During a write operation, the A input is selected by the Even
Multiplexer and the Odd Multiplexer, and switched
to the Fast Data Memory. The write data thus becomes available to update the data memory if a hit
occurs. The output of the Write Data Multiplexer
is also applied to the Data Parity Generator, which
generates data parity for the word being written,
for use on the Main Memory Bus and possible stor-

BYTE (2-0:2-8)

(3-0:3-8) data

lines of the

Main

Memory Bus. Since the processor and Unibus Map

are capable of only single word or byte transfers,
this

arrangement

allows

writing

into

either

word/byte within a Main Memory block.

Data is gated onto the Main Memory Bus when

CDPC CACHE DATA EN H is asserted. This occurs when the Main Memory Bus data lines become unoccupied (CDPD OCC L negated), while a
non-MBC write to memory operation is being exe-

age in the Fast Data Memory.

cuted by the Cache.

During an MBC cycle (CCBB MBC CYCLE L as-

4.2.14

Main Memory MBC Data Drivers

serted) and during the power-up sequence (CDPJ
INIT A L asserted), the select inputs to the Write

These

drivers

(Drawings

CDPC,

drive

data

(MBCBUS D31-D00 L) and associated byte parity

Data Multiplexer are both high. This forces all 1s

bits (MBCBUS B3PA-BOPA L) from the Massbus

to be output from the multiplexer and ensures that

Controllers onto the data lines of the Main Mem-

the data lines are stable while data parity bits are

ory

generated. The all Is pattern thus generated is writ-

MAIN

ten into the FDM during the power-up sequence,

Main Memory Bus data lines become unoccupied).

and also when an FDM location is invalidated as a
result of an MBC write hit.

Note that the 36 MBCBUS data and data parity

Bus during a write Cache MBC cycle, when
BOCC becomes unasserted (i.e., when the

lines allow the MBCs to perform double word trans4.2.12

fers to and from Main Memory.

Data Parity Generator

The Data Parity Generator (lower left of Drawing
CDPF) generates odd parity bits (CDPF WRITE

MUX LO GEN H and CDPF WRITE MUX HI
GEN H) for the two 8-bit bytes gated by the Write
Multiplexer. WRITE MUX LO GEN H corresponds to the high byte (WRITE MUX 15:08 H).

4.2.15

Main Memory Bus Data Receivers

The Main Memory Bus Data Receivers (Drawings

CDPC, D) are represented by two blocks in the
block diagram. One group of receivers receives the
low (even addressed) word (i.e., bytes 0 and 1) and
the associated byte parity bits that are asserted on

The two parity bits are routed to the Main Mem-

the Main Memory Bus. The other group of receiv-

ory Bus Data Drivers and will be gated onto the
Main Memory Bus along with the data from the
Write Multiplexer when the write-through oper-

ers

ation is performed.

outputs of the receivers, only used when data is

receives the high (odd

addressed) word

(i.e.,

bytes 2 and 3) and the associated byte parity bits
that are asserted on the Main Memory Bus. The

VI-4-5

being read directly from Main Memory, are routed
directly to the MBCs (for MBC reads) and to the
Bus Data (Low Word and High Word) Registers
(for non-MBC reads).
4.2.16

Bus Data Register

The Bus Data Register (Drawing CDPA) is active
during a non-MBC read miss cycle. The Bus Data
Register is loaded with the 36-bit double word
being read from the Main Memory when the Cache
receives DATA READY asserted on the Main
Memory Bus. The Bus Data Register is clocked by
CDPA BD CLK H. This signal is asserted in response to DATA READY (CDPC DATA RDY H
asserted) provided that an MBC read is not in progress (CDPK RIP L negated).

even word sections of the Fast Data Memory for
possible use in updating the Fast Data Memory. If
the write operation is to an address presently stored
in the Cache (write hit), the data in the corresponding Fast Data Memory location must be updated if
it is to remain valid. If the write operation is to an
address not stored in the Cache (write miss), the
Fast Data Memory is not updated, and the output
of the Even Multiplexer is not used.

The Odd Multiplexer operates in a manner similar
to the Even Multiplexer, switching data from the
Bus Data (High Word) Register to the Fast Data
Memory and Cache Data Multiplexer during a read
operation, and switching write data to the odd
word sections of the Fast Data Memory during a
write .operation.

Data read from Main Memory is always read in
two-word pairs by the Cache. Each double word
consists of an even word (ADRS BIT 1 = 0) and

An extension of the Even and Odd Multiplexers, located at the lower right of Drawing CDPF,

the next

switches the byte parity bits.

higher odd word (ADRS BIT

These

words

are

stored

Word)

the

in
Bus

the

Bus

Data

1).

(Low

Data (High Word)

The output of the Bus Data (Low Word) Register
is applied to the B inputs of the Even Multiplexer.

The output of the Bus Data (High Word) Register
is applied to the B inputs of the Odd Multiplexer.
4.2.17

Even Multiplexer and Odd Multiplexer

This logic, located on Drawings CDPB, F, is repre-

sented by two blocks on the block diagram. The
Even Multiplexer switches data to the even word
Fast Data Memory and to the Cache Data
Multiplexer.

During a read operation in which a cycle to Main

Memory occurred, the Even Multiplexer selects the
even word which was brought from Main Memory
and is presently stored in the Bus Data (Low
Word) Register. This data word is applied to the inputs of the even word Fast Data Memory and will

be stored in one of the memory locations. The data

During the power-up sequence, CDPJ INIT A L is
asserted, and causes the Even and Odd Multiplexers to select the all Is pattern generated by the
Write Data Multiplexer.

4.2.18

Main Memory Data Parity Check
This circuitry (Drawing CDPF), represented by two
blocks in the block diagram, checks for correct parity on data words brought from Main Memory.
The checks are made at the outputs of the Even

Multiplexer and Odd Multiplexer, i.e., on the low
word and the high word brought from Main Mem-

ory. If a parity error is detected, CDPF MAIN LO
PAR OK L or CDPF MAIN HI PAR OK L are
negated, and the corresponding bits in the Memory
System Error Register are caused to set.
Setting bits (15:12) of the Maintenance Register (address 17 777 750), causes byte parity bits to be
checked as Is. This will cause parity errors to be detected on bytes having negated parity bits.

word is also applied to the Cache Data Multiplexer

(DTMM), and will be transmitted to the device initiating the read operation if the even word was the
one requested by the device.
During a write operation, the Even

4.2.19

FDM Index Field Drivers

The FDM Index Field Drivers (Drawing DTMA)
provide the drive necessary to allow bits (9:2) (in-

Multiplexer

switches the 16 bits of write data from the Write
Data Multiplexer, plus two data parity bits, to the

VI-4-6

dex field) of the incoming address to address all the
chips that comprise the FDM. The drivers have
four sets of outputs (DTMA WRD 0 A09-02 H,
DTMA WRD 1 A09-02 H, DTMA WRD 2

A09-02 H, and DTMA WRD 3 A09-02 H). Each

During a write cycle (DTMB WRITE H asserted),

set of outputs addresses the chips in the FDM that

either DTMB CSO L and DTMB CS2 L or DTMB

store a particular word, as listed below.

CSI

L and DTMB CS3 L are asserted, depending

on whether the address being referenced is odd or
WRD
0 A09-02 address

The

even

addressed

words in Group 0.

even (as determined by signal ADME AMX 01 H).
Thus, the even word in each FDM group or the

odd word in each FDM group will be enabled. If a
WRD | A09-02 address

The

odd

addressed

words in Group 0.
WRD
2 A09-02 address

The

even

hit is detected, write pulses will be generated only
for the byte/word in the group on which the hit

occurred.

addressed

words in Group 1.

During a read hit cycle (CCBD SLOW CYCLE L

negated), chip selection is performed in the same
manner as during a write cycle.

WRD 3 A09-02 address

The

odd

addressed

words in Group 1.

During a read miss cycle, (ADMJ READ L and

CCBD SLOW CYCLE H asserted), either DTMB
4.2.20

Fast Data Memory (FDM)

CSO L and DTMB CSI

The 1024 data words that the Cache is capable of

L or DTMB CS2 L and

DTMB CS3 L are asserted, as determined by sig-

storing are stored in the FDM (Figure 2-2). The

nals CCBM WRITE SEL 0 H and CCBM WRITE

FDM

SEL I

divided

into

(Group 0 and Group

two

sections

groups

1), each capable of storing

512 18-bit words. The words comprise an eight-bit

H. The CCBM WRITE SEL 1:0 signals are

generated by the Group Selection circuitry (Paragraph 4.7).

low byte, a low byte parity bit, an eight-bit high
byte, and a high byte parity bit.

DTMB LO BYTE WP 0*1 L, DTMB HI BYTE WP

0*1 L, DTMB LO BYTE WP 2*3 L, and DTMB HI
Each group is divided into two equal areas (256

BYTE WP 2*3 L are the FDM write pulses. The

words each). In one of the areas, the contents of

first pair of signals writes the low and high bytes

even addresses (address bit 1

within

= 0) are stored; the

contents of odd addresses (address bit 1

1) are

stored in the other.

Group

of the

FDM.

The

second

writes the low and high bytes in Group

chips enabled

pair

1. FDM

by a chip select signal are written

when the write pulse is low.

The FDM is implemented using type 19-12069 256
X

bit random access memory chips. Nine chips

(as. shown on Drawing DTMC) can therefore store

NOTE
The chip select signals and the write pulses operate

256 nine-bit bytes (eight data bits plus one parity

together to write the desired byte, word, or double

bit). The organization on Drawing DTMC is dupli-

word into the FDM. the chip select signal must be as-

cated on Drawings DTMD through DTML. Draw-

serted

ings

generated.

DTMC-F

illustrate Group 0

of the

FDM;

and

the corresponding write pulse

must be

Drawing DTMH-L illustrate Group 1.

During

the

power-up

sequence,

CCBM

WRITE

FDM chip select signals DTMB CS3:0L (Drawing

SEL 1:0 H are asserted; this enables all four write

DTMB) enable the FDM chips to be written and to

pulses to be generated.

output data. The FDM is enabled on a word-byword basis. DTMB CSO and CSI enable the even

During a read miss, only one of the WRITE SEL

and

signals is asserted; therefore, only the pulses which

odd words (respectively)

Group 0 of the

FDM. Similarly, CS2 and CS3 enable the even and

write into the selected group will be generated.

odd words (respectively) of Group 1.
During a write hit, write pulses are generated for

During

the power-up sequence

[ADMJ

chip

(1)

asserted.

asserted],

all

four

POWER

selects

are

the word/byte in the group on which the hit occurred, as determined by the WRITE SEL signals,
ADME AMXO00 H and ADMJ DATOB H.

V1-4-7

During a write miss, the WRITE SEL signals are
negated, and no write pulses are generated.

or Group |, DTMN DATA PARO OK L or
DTMN DATA PARI OK L are negated, respectively, and the corresponding bits in the Error Reg-

The contents of a Main Memory location (i.e., a
two-word block) is loaded into the FDM whenever
a non-MBC read miss occurs. The block is loaded
into either Group 0 or Group | (depending on the
state of an internally generated Random bit; refer

ister are set.

to Paragraph 4.7) at an index position determined
by the index field (bits 09:02) of the incoming address. The words within the block become available
for future reference by either the processor or
Unibus Map. When one of these words is read in
the near future (assuming that they are not over-

If, during a read hit operation, the requested word
stored in the FDM is found to have bad parity, the
Cache initiates a cycle to Main Memory to fetch
the (hopefully error-free) backup copy of the word.
The newly fetched word will be loaded into the
FDM, replacing the word on which the error
occurred.

high speed because a Main Memory Bus cycle will

Setting bits (7:4) of the Maintenance Register (address 17 777 750) causes the FDM data byte parity
bits to be checked as 0s. Thus, an FDM data parity
error will be detected on bytes having asserted par-

not be required.

ity bits.

During a non-MBC write hit, the data word (or
byte) written into Main Memory is also written
into the FDM. If the word to be written into the
FDM has an even address, it is applied via the
Even Multiplexer to the even word storage areas of
both Group 0 and Group 1 of the FDM. It thus becomes available to replace the obsolete even address word in the group on which the hit occurs.

4.2.22 Even and Odd Multiplex Inverters
These inverters (Drawing DTMP) invert the data
and data parity bits being read from Main Memory

written by another pair of words having an address

with an identical index field), it will be fetched at

during a non-MBC read miss cycle. The inversion
is performed so that all inputs to the Cache Data
Multiplexer are at a true high when asserted. The
inversion is required to compensate for the extra inversion performed on data being read directly from
the Fast Data Memory.

MBC read hit, read miss, and write miss operations
do not affect the FDM. However, when an MBC
write hit occurs, the FDM location on which the
hit occurred is loaded with all Is (i.e., correct data
parity). At the same time, the corresponding Address Memory location is loaded with a negated
Valid bit, invalidating the block.

Within each group of the FDM, the odd word and

4.2.23 Cache Data Multiplexer
The Cache Data Multiplexer (Drawing

DTMM)

switches data being read out of the Cache to the
BR of the processor and to the Unibus Map. The
data switched may be from one of four sources, depending on the memory address requested (odd or
even address), and whether a hit occurred on FDM
Group 0, Group 1, or neither group.

even word outputs are common collectored. When

data is read from the FDM, only the even or odd

word in each group is read out. The two words

(both odd or both even) are checked for correct parity, and also applied to the Cache Data Multiplexer. During a non-MBC read hit, the Cache
Data Multiplexer selects the word from the FDM
group (Group 0 or Group 1) on which the hit

Input A to the Cache Data Multiplexer
is the output of Group | of the FDM.
An odd or even word is gated out of
Group 1 of the FDM, depending on
whether the address input to the Cache

is odd or even. If a hit on Group | occurs, this input is selected by the Cache
Data Multiplexer.

occurred.

4.2.21

FDM Data Parity Check
This logic (Drawing DTMN), represented by two

Input B to the Cache Data Multiplexer
is the output of Group 0 of the FDM.
An odd or even word is gated out of

blocks in the block diagram, checks for correct parity on the data output from Group 0 and Group |
of the FDM. One parity check is performed on

Group 0 of the FDM, depending on
whether the address input to the Cache

data output from Group O; the other check is performed on the data output from Group 1. If a par-

is odd or even. If a hit on Group 0 occurs, this input is selected by the Cache

ity error is detected on data output from Group O

Data Multiplexer.

VI-4-8

Input Cis the even word received by the

T = 30ns

Cache from Main Memory. If the ad-

cceaars ck n [

dress input to the Cache is an even address (ADRS BIT

0) and a read

miss occurs, this input is selected by the

CCBA SYNC CLK H |

L
11-2843

Input D is the odd word received by the

Cache from

-»lle-6-10ns

Cache Data Multiplexer.
4,

Figure 4-1

Main Memory. If the ad-

Cache Clock Waveforms

dress input to the Cache is an odd ad
dress (ADRS

BIT

1) and a read

miss occurs, this input is selected by the
Cache Data Multiplexer.

The output of the Cache Data Multiplexer becomes
available to both the processor and the Unibus
Map. If the processor initiated the read operation,
the Cache will respond with MEM SYNC to the
processor when the data is ready; this will cause the
transfer of the data.to the BR of the processor.
If the Unibus Map initiated the read operation, the

Cache will respond with CCBC UB DONE
(Unibus Done) when the data is ready. This will
cause the transfer of the data to the data latch in
the Unibus Map.
4.2.24

The operating speed of the PDP-11/70 Cache is
achieved by using fast logic and running the Cache
synchronously with the processor. The short time
between clock pulses makes Cache timing very critical. To speed up signal processing, a parallel implementation is generally used in place of a serial
implementation. For this reason, type 74564 2-2-3-4
AND-OR-INVERT gates are often used in the design wherever signal delays must be minimized.
4.3.1

The

Cache Timing Sequence
cache timing sequence

generated

using

CCBA ARB CLK H. (Refer to Drawing CCBE.)
The Cache timing sequence is a series of time states
generated whenever the Cache begins executing a

The register logic shown on the Cache data paths
block diagram is described in Paragraph 4.8

4.3 CACHE TIMING
The PDP-11/70 Cache operates synchronously with

the processor. This synchronous operation aids in
achieving overall high operating speeds.

memory access cycle. These time states are used to
synchronize various Cache functions as indicated in
Paragraphs 3.8.1 through 3.8.10.
The timing sequence is initiated (Figure 4-2) as a result of the assertion of LOCK. Generation of more
than one timing sequence during any Cache cycle is
inhibited

gating

LOCK

with

signals

CCBD

START SLOW (0) H, CCBE T60 (0) H, CCBE
T120 (0) H, and CCBE T150 HOLD (0) H.

The Cache is synchronized to clock signals gener-

ated on the TIG module (M8139). The processor
free clock, TIGC TF H, is buffered to generate
CCBA ARB CLK H. The buffering circuitry, comprising discrete components (located on Drawing
CCBA) is designed for minimal propagation delays
and rise and fall times. This is achieved by operating the transistors at or near their active region.
CCBA ARB CLK H is inverted by a 74S140 gate
to generate CCBA SYNC CLK H. Figure 4-1 illustrates these two waveforms, and emphasizes the
6-10 ns delay introduced by the inversion. Only the
negative-going edge of CCBA ARB CLK H is used
for clocking purposes. Likewise, only the positivegoing e¢dge of CCBA SYNC CLK H is used. Thus
the active edges of these two clocks are separated

When

by the 6-10 ns inversion delay.

cides

LOCK

asserted,

the T30

flip-flop

clocked set by the falling edge of ARB CLK. The

T60 flip-flop is then clocked set on the next falling
edge of ARB CLK. With T60 (1) H asserted, the
T30 flip-flop is cleared on the next negative-going
ARB CLK pulse. This in turn causes CCBE T90 H
to be asserted.

On the next negative-going ARB

CLK pulse, the T120 flip-flop is set. At the same
time, the T60 flip-flop is cleared and CCBE T60 (1)
H and CBE T90 H are negated. The T150 HOLD
flip-flop is clocked set at the next ARB CLK pulse,
while at the same time the T120 flip-flop is cleared.

The T150 HOLD flip-flop remains set until either
CCBD START SLOW (1) L or CCBC DONE (1)

VI-4-9

L is asserted. During T150 HOLD, the Cache dewhether or not to assert CCBD START

T 120

T 150 HOLD

——

I
I

T 90

—~—

T 60

[
17

————— =

sTARTSLOW

DONE
Dashed
write

- ——_L

{4 —

———="

lines indicate timing during

and read miss cycles.
11-2844

Figure 4-2

Cache Timing Sequence

SLOW (1) H and thereby initiate
-a cycle to Main

4.3.3

Main Memory Bus (Slow Cycle) Timing

Memory. Thus if a processor cycle is being per-

When

the

formed, the Cache must receive CONTROL OK

Unibus Map, or MBC cycle, bits (21:02) of the in-

from the processor during or prior to the assertion

coming address are placed on the Main

of TI50 HOLD.

bus, along with Main Memory control bits (MAIN

Cache

begins

executing

processor,

Memory

BYTE MASK 3:0 and MAIN C1:0) and an address
parity bit. While the Cache timing sequence is pro4.3.2

gressing, these signals are deskewed on the Main

Read Hit Timing

If a read hit i1s detected during the Cache timing sequence, the Done flip-flop is clocked set (by the
first: CCBA ARB CLK H pulse during TI150
HOLD) and asserts CCBC

DONE (1) H. CCBC

DONE (1) H resets much of the Cache logic, including the Lock flip-flop. With CCBB LOCK (1) H negated, the Cache is in its quiescent state and may
begin executing the next cycle.

Memory Bus. During T150 HOLD of the timing sequence, the Cache decides whether or not to perform a Main Memory Bus cycle. If a cycle to Main
Memory

required,

the

Cache

asserts

CCBD

START SLOW. If a write operation is being performed, CDPC START WRITE is asserted when

the Main
(MAIN

Memory data lines become unoccupied

BOCC negated). At the same time, write

data 1s gated onto the Main Memory Bus by the
Cache. START WRITE asserted enables START

If a processor cycle is being executed, CCBC MEM

SLOW to generate CCBD START H after a 100 ns

SYNC H is asserted synchronously with processor

data

deskew
the

delay.

is driven

and initiates the Main Memory cycle. In response

ceived TMCE CONTROL OK H, or during TI50
HOLD when the Cache receives TMCE CON-

ADRS ACKN H is asserted in the Cache and ne-

TROL OK H.

gates CCBD START H.

ACK

from

Bus as

timing. CCBC MEM SYNC H is asserted at the

VI-4-10

Memory

START

start of T150 HOLD if the Cache has already re-

to MAIN

Main

CCBD

onto

Main

MAIN START,

Memory, ADML

During a read operation, CDPC START WRITE is
asserted throughout the Cache cycle. This allows
CCBD START H to be asserted 100 ns after the as-

The power-up control logic is located on Drawing
ADMIJ. The circuitry consists of a pulse generator,

a counter, and the PUP (Power-Up) flip-flop.

sertion of START SLOW.

The following discussion describes operation of the
power-up circuitry upon initial power turn on. It

NOTE

During Main Memory read cycles, the 100 ns delay

should, however, be kept in mind that the same se-

is still necessary in order to ensure sufficient deskew

quence of events occurs when power returns after a

for the address and control lines of the Main Mem-

momentary failure.

ory Bus. This is required because the high order bits
of the 22-bit physical address generated by Memory
Management may not be valid until the Cache is in
the midst of its operation cycle.

4.3.4

timing

diagram

illustrating

the

puts, AC LO L is asserted and clears the eight-bit

Cache timing is restarted when proper Main Mem-

ory response causes the negation of CCBE ALLOW TIMEOUT L. CCBE ALLOW TIMEOUT L
is negated when the Cache receives MAIN ACK
from Main Memory after initiating a write operation or an MBC read operation. If a non-MBC
read operation is being performed, the Cache must

DATA

4-3

As ac power is appearing at the power supply in-

Timing Restart After Main Memory Cycle

also receive MAIN

Figure

power-up circuitry operation.

READY. The Cache

Power-Up Address Counter. When DC LO L is asserted, the Power-Up flip-flop is direct set; this enables the Power-Up Pulse generating oscillator to
begin operation when power has reached normal
levels (i.e., when AC LO L is negated).
When POWER UP (1) H is asserted, the following
events occur:

dress are generated upon negation of CCBE AL-

CCBB AMX SO H is asserted, causing
the Address Multiplexer to select the

LOW TIMEOUT L.

power-up

address

generated

Power-Up

Address

Counter.

(During

The negation of CCBE ALLOW TIMEOUT L is

power-up,

CCBB

synchronized

serted due to INIT.)

write pulses (CCBE WP L), which write the Ad-

CCBA

SYNC

CLK

CCBA

AMX

SIH

the

unas-

ARB CLK H, and TIGC TF H to generate CCBE
MEM SYNC SLOW (1) H and CCBE RESTART

(1) H. CCBE MEM SYNC SLOW (1) H causes the

CCBM VALID 0 INPUT L and CCBM
VALID 1 INPUT L are negated, and

cessor cycles which result in Main Memory oper-

CCBM WR OK H, CCBM WRITE
SEL 0 H, and CCBM WRITE SEL | H

ations.

are asserted.

assertion

of CCBC
CCBE

MEM

SYNC H during pro-

RESTART

(1)

enables

the

assertion of CCBC DONE (1) H. CCBC DONE (1)

resets much of the Cache logic, including the

Lock flip-flop. With CCBB LOCK (1) H negated,
the Cache is in its quiescent state, and may begin
executing the next cycle.

4.4

POWER-UP LOGIC

DTMB GROUP 0 H and DTMB
GROUP | H are asserted and, in turn,
enable assertion of DTMB LO BYTE
WPO*! L, DTMB HI BYTE WPO*I L,
DTMB LOBYTE WP2*3 L, and DTMB
HI BYTE WP2*3 L when write pulses are
generated.

On power-up, the Cache performs a power-up sequence during which all of the Valid bits in the Adanything stored in the Cache immediately after a

The FDM chip selects (DTMA CS O L,
DTMA CS I L, DTMA CS 2 L, and

power-up must not be construed as valid data. At

DTMA CS 3 L) are asserted.

dress

Memory are cleared. This is done because

the same time that the Address Memory Valid bits

The output of the Write Multiplexer
(CDPE) is forced to all ones.

upon power-up will not generate parity errors when

The Even Multiplexer and Odd Multiplexer (CDPB,F) select the outputs of

program execution begins.

the Write Multiplexer.

are negated, all the remaining bits in the Address
Memory

and

FDM

are loaded with bit patterns

having correct parity. This is to ensure that the bit
patterns resident in the Address Memory and FDM

VI-4-11

. N

AC LO
L

DC LO L

(

{
LR

(¢

POWER UP (1) H /M
COUNT CLK L

POWER UP ADDRESS

ALLOW WP H

L‘

o3l)

377|s

“'L

BRA

PUP

-4

WP L

171

|
N

1-2845

Figure 4-3

When

generating

Power-Up Sequence Timing Diagram

LO L is negated, the oscillator begins

the UBUS flip-flop to be set when

pulses. The pulses produced clock

gated, provided that no non-Unibus DATIPs are in

the

LOCK is ne-

FDM and Address Memory (causing the locations

progress.

indexed by the Power-Up Address Counter to be

be set when LOCK is negated, provided that no

loaded)

non-MBC DATIPs are in progress.

and

increment

the

Power-Up

Address

PRE

MBC causes the MBC flip-flop to

Counter. Each FDM word position indexed by the
Power-Up Address Counter is loaded with all ones.

If the UBUS flip-flop is set, CCBB UB CYCLE H

The

loaded

is asserted: the Cache will perform a Unibus Map

with negated Valid bits and correct address parity.

memory access cycle. If the MBC flip-flop and the

Address

Memory

word

locations

are

As the Power-Up Address Counter is clocked from

UBUS flip-flop are set, CCBB UB CYCLE H is as-

000 to 3774, all the locations in the FDM and Ad-

serted, and the Cache will perform a Unibus Map

dress Memory are loaded, and the contents of the

memory

Cache arc thereby invalidated.

Map requests priority over MBC requests. CCBB

When the Power-Up Address Counter is clocked to

overflow, the Power-Up flip-flop is clocked clear:;
this inhibits further PUP WP L pulses and terminates the power-up sequence.

4.5

REQUEST ARBITRATOR LOGIC

Unibus Map, or MBC memory access.
signals

are

input

this

what

gives

Unibus

MBC CYCLE is asserted when the MBC flip-flop

is set and

the

UBUS

flip-flop is not;

the Cache

would then perform an MBC memory access cycle.

Processor memory access cycles are performed only

Request Arbitrator (Drawing CCCBB) determines whether the Cache will perform a processor,

request

cycle;

when neither the Unibus Map nor the MBCs are re-

The

Two

access

questing memory access. When neither the UBUS

flip-flop nor the MBC flip-flop is set, CCBB CP
CYCLE H is asserted. This is a default condition,
and therefore gives the processor the lowest priority

the

Request

status. The priority structure is thus:

Arbitrator:
I.

MAPF

Ist priority: Unibus Map

REQUEST (1) L from the

“2nd priority: MBCs

Unibus Map.
2.

-3rd priority: Processor

CDPJ MBC REQ L from the MBC Arbitration Logic.

Whenever a memory access cycle is performed, the

CCBB AMX SI, SO H signals are generated to en-

The request signals are synchronized and delayed

able the Address Multiplexer (ADMH) to select ad-

(90

dress and operation control bits from the correct

and

180

ns,

respectively)

and

then

assert

PRE UBUS and/or PRE MBC. PRE UBUS causes

source.

Vi-4-12

4.6

MBC ARBITRATION LOGIC

Table 4-1

The MBC Arbitration Logic, located on the CDP

MBC Selection Priorities

module (Drawings CDPH through CDPK), selects

Jumper Configuration

one of four possible Massbus Controllers and performs with it the protocol required to transfer data
on the RH70-Cache Interface.
As illustrated in

Figure 4-4, the MBC Arbitrator

can be considered a discrete device which just hap-

pens to be located on the Cache modules.

Cacve — — "~
|

]
N

CACHE DATA

ADDRESS & DATA LINES

|l MBC
A

I| :

ARBIT- | V|

MBC
B

£\

MBC

RATOR

MBC
c

MBC
D

[)

Priority Structure *

OouT

OuT

OuUT

(A< B)e (CeD)

OuT

OouT

(A->B)e (Ce D)

OouUT

OuT

(A< B)«(C~>D)

OuT

(A->B)«(C—>D)

OouT

OuT

(A< B)—>(C<D)

OuT

(A->B)—»>(CeD)

OuT

(A<B)—~>(C—>D)

(A—>B)—»(C—>D)

| !

*SYMBOLS <, = are defined in the text.

\MBC REQUEST &
SELECTION

LINES
1-2846

Figure 4-5 is a block diagram showing the three maFigure 4-4

Relationship of the MBC Arbitrator
to the Cache

jor sections of the MBC Arbitration Logic: Request
Block Logic, Address and Data Select Logic, and
Data Ready Logic.

The selection of an MBC is based on a number of

4.6.1

criteria:

Requests from the RH70s are input to the Request

Request Block Logic (Drawing CDPH)

Block Logic. If one of the MBCs is currently perI.

memory

forming a DATIP, this circuitry inhibits requests of

cycle is not in proggress and no MBC

other MBCs from being processed by the Cache. Al-

requests are pending or being executed,

though none of the Massbus devices presently man-

thhe first request received will be granted.

ufactured

MBC

DATIP/DATO

Request

MBC

TIP/DATO

performing

memory

cycle,

DA-

the

DATO

portion

DEC

utilize

DATIP

cycles,

the

cover their utilization in the future.

requests

from other MBCs are not recognized un-

til

Block circuitry has been implemented to

of the

DA-

4.6.2

Address and Data Select Logic

Refer to Drawing CDPJ and Figure 4-6.

TIP/DATO cyycle has been initiated.
4.6.2.1
3.

Jumpers

(WI,

W2,

W3)

the

CDP

Single

Request

Operation - The

Address

and Data Select Logic input latch (consisting of the

module allow MBC selection to be based

four D-type flip-flops at the left-hand side of Draw-

on the history of the most recent selec-

ing CDPJ) is clocked when MBC REQ L is as-

tions. Table 4-1

lists the selection pat-

serted. This causes SEL ADRS CTRL X H (where

terns obtainable for the different jumper

X is A, B, C, or D) to be transmitted to the request-

configurations.

If two

MBCs

ing MBC. At T30 of the Cache MBC cycle, the Ad-

request memory access concurrently, se-

dress and Data Select output latch (a type 74S175

lection will be based on the pattern of

data

previous selections,

clocked by DISABLE REQ H asserted, and SEL

in a manner deter-

mined by the jumper configuration.

latch

DATA X

VI-4-13

the

center

of Drawing CDPJ)

H is transmitted to the selected MBC.

+ | SELECT

DATA LINES
» [ (ONE TO EACH MBC)

——
—

—— | SELECT

— [ (ONE

ADDRESS

LINES

TO EACH MBC)

—

REQ A
REQUEST [ —5"|

LINES | ——=»

(oNE From] —Cof

EACH MBC) | —D4

REQUEST

BLORE
(CDPH)

ADDRESS
é\xr%

paTa

| | DATA READY

SELECT
(COPJ)

R
(CDPK)

| [(ONE TO EACH

»|

DISABLE
REQ

MBC

= | LINES

. | MBC)

READ IN

REQ

PROGRESS

TO AND FROM CACHE CONTROL

(€CB)
11-2847

Figure 4-5

CSTC CTRA REQ.L
COPJ MBC REQ L

(

MBC Arbitrater Block Diagram

ekL

{f-

COPJ SELADRS CTRLA H %
180ns
-

ccBB

PRE MBC

CCBB CLK MBC

ADRS

77,

CCBB LOCK (1) - H JPREVIOUS 93CLEJ
CCBB MBC CYCLE H

|
T30

CCBE

COPJ

SEL

T150

[T60

DISABLE REQ

DATA CTRLA

H 22777022

ACKN

CCBE MBC REQ

=
Y

% CDPJ SELADRS CTRL"X"sent to
next MBC if request is pending.

14-2848

Figure 4-6

MBC Request Timing (MBC A Requesting)

VI-4-14

When CCBE CLK PRI H is asserted at T120, the
Priority Generator (upper-right of Drawing CDPJ)
is clocked and records the current MBC selection.
Future selections aré based on the output of the Pri-

ture (A over B ovver C over D) has been selected via

the priority jumpers, and that the MBC requests arrive in the following sequence: B, C, A. The MBC
B request, first to arrive, asserts MBC REQ, which

ority Generator.

in turn asserts SEL ADRS CNTR B. Therefore, the

4.6.2.2 Multiple
Request
Operation - Multiple
MBC requests are handled in a manner similar to a
single request. In fact, the first of the multiple
requests to arrive is always serviced first, and is handled in the same way as a single request. The re-

request is serviced next because of the straight prior-

MBC

maining requests are handled slightly differently
because CDPJ MBC REQ L remains asserted; this
enables the Address and Data Select Logic input
latch to be clocked by the trailing edge of DISABLE REQ H at T150 of the MBC cycle. The input latch is thus loaded with any MBC requests

request

serviced

firstt

The

MBC

ity struucture, and finally the MBC C request is
serviced.

The

Priority Generator determines which request

will be granted when more than one MBC request

is pending. Jumpers W1, W2, and W3 allow control

of the priority structure. When all jumpers are out,
a pseudo round-robin priority structure results as

follows:

still pending.

(AoB) & (CoD)

Figure 4-7 is a timing diagram of the Address and
Logic during multiple request oper-

MBC A REQUEST

MBC B REQUEST
MBC

The symbol - indicates that selection alternates between the expressions on either side of the symbol.

REQUEST

POSSIBLE UB CYCLES
L]

wec cvee

SEL ADR B _ |

SEL ADR A

SEL DATA

SEL ADR

SEL DATA

MBC CYCLE

L%ZJ

MBC CYCLE

(

ODISABLE REQ
SEL DATA B

1‘22’]

_‘/\\_
-

LOCK

‘l

Select

Data

ation. It is assumed that a straight priority struc-

11-2849

Figure 4-7 MBC Address and Data Select Timing (Multiple Requests — Straight Priority)

VI-4-15

With all three jumpers out, the signals output by

Refer to

the Priority Generator indicate the true history of
past MBC selections, as follows:

cycle is performed by the Cache, one of the flip-

Drawing CDPK. When

MBC read

flops at the left-hand side of the drawing is direct
set at T300 of the Cache timing sequence.

CDPJ B LAST (1) H

If no

MBC
A has not been se-

other

lected since MBC B was

memory (i.e., waiting for data ready), CDPK RIP

last selected.

MBC is currently performing a read from

H (Read In Progress) is in the negated state. This
allows one of the flip-flops in the center of the

CDPJ D LAST (1) H

MBC C has not been se-

drawing to be direct set, causing the assertion of

lected since MBC D was

CDPK RIP H.

last selected.
As a specific example, assumme that MBC A per-

CDPJ C OR D LAST
(O H

MBC A or B have not

forms a read from memory. When the Cache as-

been

serts CCBE MBC REQ ACKN

selected

since

L at T30 of the

MBC C or D was last

Cache timing sequence, the flip-flop at the top left

selected.

of CDPK is direct set. If no other MBC read is in
progress (RIP negated), the top center D-type flip-

Each of the above signals can be forced to assertion
by installing jumpers W1, W2, or W3, respectively.
When jumpers are installed, MBC selection is based
on a distorted view of past history, and therefore,
some MBCs ccan be given priority over others. For
example, if all the jumpers are installed, a straight
priority structure results:

DATA RDY originating in Main Memory control

MBC A. Assume, however, that before Main

Memory responds with DATA RDY, the Cache begins

executing

MBC

read

When

from

memory

initiated

thhe Cache asserts CCBE MBC

REQ ACKN at T30 of the current Cache timing sequence,

the

D-type flip-flop at

the lower left of

CDPK is direct set. The flip-flop at the lower cen-

(A-B) - (C-D)

where the symbol —»

flop is also set. This enables the top 74S11 to gate

ter is not direct set at this time because CDPPK RIP

indicates that the expression on

the left is given priority over the expression on the
right.

H is asserted; the Cache is waiting for Main Mem-

ory to

respond with

DATA

RDY to a read in-

itiated by MBC A. When DATA RDY is received
in the Cache, CDPK DATA RDY CNTL A is as-

serted and routed to MBC A. At the trailing edge
Table 4-1

lists the MBC selection priorities result-

ing from the eight jumper configurations.

of DATA

RDY, the RIPP A flip-flop is clocked

clear. This negates RIP H momentarily, and allows
the

RIP

flip-flop

be direct set.

RIP

thereby reasserted, and the transmission of CDPK
DATA RDY CNTL D is enabled.

4.6.3

Data Ready Logic

The Data Ready Logic (located on Drawing
CDPK) keeps trackk of which MBCs are currently

The

performing read operations and routes the DATA

DATA

RDY signal originating in Main Memory to the cor-

intended.

rect MBC. A read operation can be initiated on the
Main Memory Bus before a previous read operation has been completed. This is termed ‘‘stack-

A third MBC read cycle is inhibited by the asser-

ing” operations on the Main

Memory

Data

track

Ready

Logic can

keep

Bus. The

of two con-

Cache

MBC

thus

reads,

keeps

and

RDY

track

remembers

response

from

of two concurrent
for

which

Main

MBC

Memory

tion of CCBD READ IN PROG (1) H. This signal
is asserted during the second of two stacked MBC

reads

and

inhibbits

current reads, thereby allowing two MBC read oper-

TIMEOUT

atiions to be stacked on the Main Memory Bus.

terminated.

VI-4-16

negation

until

the

of CCBE

ffirst

MBC

ALLOW
read

4.7

GROUP

SELECTION

AND

VALID

BIT

parity error has been detected in either Group 1 of

LOGIC

the FDM or Tag

The Group Selection and VValid Bit Logic is located

output will be high if a parity error has been de-

Address Memory. The R2(1)

on Drawing CCBM. The group selection circuitry

tected in either Group 0 of the FDM or Tag 0 Ad-

produces outputs CCBM

WRITE SEL 0 H and

dress Memory. The RI(]) output will be low if a

CCBM

These signals enable

write hit on Group 0 has been detected. The RO(1)

Group 0 and Group | of the FDM and correspond-

WRITE SEL

outpput will be low if a write hit on Group 1 has

ing Tag O or Tag | Address Memory to be written.

been detected. If any of the above conditions is detected, the Random bit is overridden. If a parity er-

The Valid Bit Logic asserts CCBBM VALID 0 IN-

ror

PUT L and CCBM VALID | INPUT L, the Valid

occurred is selected for replacement. On a write hit,

bit

Memoryy.

the group on which the hit occurs is selected for
replacement.

The heart of the circuitry is the D-type flip-flop at

The

the lower left of Drawing CCBM. This is the Ran-

power-up sequence and during MBC cycles. During

inputs

the

Tag

and

Tag

Address

detected,

Random

the

bit

group

also

overridden

dom bit generator. At T60 of every Cache timing se-

quence, the Random flip-flop is clocked and causes

causes the assertion of CCBM

power-up,

ADMJ

which

POWER

UP (1)

the

error

during
L

the

asserted

WRITE SEL 0 H

the Random bit to change state. During normal er-

and CCBM WRITE SEL 1 H, and the negation of

ror-free operation, the state of the Random bit de-

CCCBM VALID O INPUT L and CCBM VALID |

termines which group of the FDM is loaded when

INPUT L. During an MBC cycle, the Valid bits are

also negated, while the assertion of CCBM WRITE

non-MBC

read

miss

occurs.

If CCBM

RAN-

DOM (1) H is asserted during a non-MBCC read

SEL 0 H and WRITE SEL |

miss cycle, CCBM WRITE SEL

cycle is a read from memory.

VALID

INPUT

are

H and CCBM

asserted.

Likewise,

H is inhibited if the

CCBBM RANDOM (1) H is negated during a non-

MBC read

miss cycle, CCBM

WRITE SEL 0 H

and CCBM VALID 0 INPUT L are asserted.

4.8

CACHE

REGISTERS

AND

LOGIC

A four-bit latch (type 74175) is clocked by CCBD

This section defines the Cache registers and the bits
they contain; a description of the actual implemen-

START SLOW (1) H just prior to the initiation of

tation is also provided.

a slow cycle on the Main Memory Bus. The outputs of this latch represent conditions detected in

Table 4-2 lists the six registers located in the Cache,

the FDM and Address Memory during the Cache

along

timing sequence. The R3(1) output will be high if a

graphs describe each register.

with

their

addresses.

Table 4-2
Cache Registers

Address

Low Error Address

17 777 740

Read only

High Error Address

17777 742

Read only

Memory System Error

17777 744

Read/selective clear

Control

17 777 746

Read/write

+Maintenance

17777 750

Read/write

Hit/Miss

17 777 752

Read only

VI-4-17

Access

The

following

para-

/é

4.8.1 Low Error Address Register (17 777 740)
This register, illustrated in Figure 4-8, contains the
_J66 low order bits of the 22-bit physical address

4.8.2 High Error Address Register (17 777 742)
This register, illustrated in Figure 4-9, ccontains the
six high order bits of the 22-bit physical address
being accessed when an error occurred. The type of

significant bit is bit 0. The high order bits of the addresses are contained in the High Error Address

memory cycle being performed when the error occurred is indicated by register bits 15 and 14, which
store the operation control bits (C1 and CO) of the
memory cycle. Table 4-3 lists the register bits.

being accessed when an error occurred. The least
Register.

All bits are read only. The bits are undetermined after a power-up. They are not affected by a Console
Start or RESET instruction.

All the bits are read only. The bits are undetermined after a power-up. They are unaffected by a
Console Start or RESET instruction.

LOW ADDRESS (16 BITS)
11 2891

Figure 4-8

Low Error Address Register

11.20852

- Figure 49 High Error Address Register

Table 4-3
High Error Address Register

Bit

Name

1514

Cycle Type

5-0

Address

Function

These bits are used to encode the type of memory cycle which
was being requested when the parity error occurred.
Bit 15

Bit 14

Cycle Type

Data In (read)

Data In Pause

Data Out

Data Out Byte

These bits contain the highest 6 bits of the 22-bit address of

the first error. The most significant bit is bit 5.

VI-4-18

4.8.3
Memory System Error Register (17 777 744)
The Memory System Error Register, illustrated in
Figure 4-10, keeps track of hard and soft errors

half the Cache will be operating. Bus system
throughput will not decrease by 50 percent, since
the statistics of read hit probability will still provide

within the memory system.

reasonably fast operation. If Group 1 is malfunctioning, bits 4 and 3 should be set and bits 5 and 2

A soft error is an error which does not result in the
processor

receiving

erroneous

data;

soft

cleared so that only Group 0 is operating. If all of
the Cache is malfunctioning, bits 3 and 2 should be

error

causes a trap.. An error which causes the processor

set. The Cache will be bypassed, and all references

to receive erroneous data is a hard error; this type

will be to Main Memory.

Table 4-4 defines the bits in the Memory System Er-

Control Register bits 5 and 4 can also be used to
keep a desired routine in the Fast Data Memory.

of error causes an abort.

ror Register. All the bits are read/write. The bits
are cleared on power-up or by Console Start: They

For example, if bit 5 is cleared and bit 4 is set prior
to execution of a desired routine, the routine will
be loaded into Group 0. If bit 5 is cleared and bit 4

are unaffected by a RESET instruction.

is set when the desired routine is not being executed, the routine will remain protected in Group 0

When writing to the Memory System Error Register, a bit is unchanged if a 0 is written to it, and it

for future reference. The routine can be protected

is cleared if a | is written to it. Thus, the register is

in Group 0 while it is being executed if bit 5 is set
and bit 4 is cleared.

were set between the read and the write, they will

not be inadvertently cleared.

Table 4-6 summarizes the uses of Control Register
bits (5:2).

4.8.4

Bits 1 and 0 can be set to disable trapping. With
these bits set, the processor will not spend time per-

cleared by writing the same data back to the register. This guarantees that if additional error bits

Control Register (17 777 746)

This six-bit register, illustrated in Figure 4-11, controls several important internal functions; these are

forming trap service routines each time a non-fatal
error occurs. Overall system operation will produce

outlined in Table 4-5. The Control Register allows
running thhe PDP-11/70 in a degraded mode; this

correct results; however, more Main Memory Bus

cycles may be performed.

may be desirable if parts of the Cache are malfunctioning. If Group 0 of the Cache is malfunctioning,

The Control Register can also be used in troubleshooting. For example, by setting register bits 3

it is possible to force all operations through Group
I. Setting bit 4 or bit 5 allows the internally generated Random bit to be overridden and causes data,

and 2, the Cache is effectively disabled. If the system operates with these bits set and does not oper-

fetched from Main Memory as a result of a read
miss, to be replaced in the specified group. If bits 5
and 2 of the Control Register are set and bits 4 and

is indicated.

3 are cleared, the CPU will not be able to read data
from Group 0, and all Main Memory data replacements will occur within Group 1. In this manner,

power-up or by Console Start. They are unaffected

ate if they are cleared, a malfunction in the Cache

Bits (5:0) are read/write. The bits are cleared on
by a RESET instruction.

1514131211109876543210

cru ABORT—-J

CPU ABORT AFTER enaon

DATA ERRORS

I
4

I
[

UNIBUS PARITY ERROR

UNIBUS MULTIPLE PARITY mon
CPU ERROR
UNIBUS ERROR
CPU UNIBUS ABORTY
ERROR IN MAINTENANCE
DATA MEMORY GROUP 1
DATA MEMORY GROUP 0
ADDRESS MEMORY GROUP |
ADDRESS MEMORY GROUP
0
MAIN MEMORY ODD WORD
MAIN MEMORY EVEN WORD
MAIN MEMORY ADDRESS PARITY ERROR
MAIN MEMORY TIMEOUT
112864

Figure 4-10

Memory System Error Register

VI-4-19

Table 4-4

Memory System Error Register

Function

Bit

Name

CPU Abort

CPU Abort After
Error

locked by a previous error.

Unibus Parity
Error

Set if an error occurs which results in the Unibus Map
asserting the parity error signal on the Unibus.

Unibus Multiple

Parity Error

CPU Error

Unibus Error

CPU Unibus Abort

Set if an error occurs which causes the Cache to abort a
processor cycle.

Set if an abort occurs with the Error Address Register

Set if an error occurs which causes the parity error signal

to be asserted on the Unibus with the Error Address
Register locked by a previous error.

Set if any memory error occurs during a Cache cycle
from the processor.

Set if any memory error occurs during a Cache cycle
from the Unibus.

Set if the processor traps to vector 114 because of a

Unibus parity error on a DATI or DATIP cycle by the
processor on the Unibus.

Error in Maintenance

Set if an error occurs when any bit in the Maintenance
Register is set. The Maintenance Register will then be

cleared.

7-6

Data Memory

These bits are set if a parity error is detected in the Fast
Data Memory in the Cache. Bit 7 is set if there is an

error in Group 1, bit 6 for Group 0.

5-4

Address Memory

These bits are set if a parity error is detected in the Address

Memory in the Cache. Bit 5 is set if there is an error in
Group 1, bit 4 for Group O.

3-2

Main Memory

These bits are set if a parity error is detected on data from

Main Memory. Bit 3 is set if there is an error in either byte
of the odd word, bit 2 for the even word. An abort occurs
if the error is in the word needed by a CPU reference. A
trap occurs if the error is in the other word, orif itisa
Unibus reference.

1
0

Main Address

Parity Error

Main Memory
Time-out

Set if there is a parity error detected on the address and

control lines on the Main Memory Bus.

Set if there is no response from Main Memory. For CPU

cycles, this error causes an abort. When a Unibus device requests a non-existent location, this bit will not set.

V1-4-20

7 T T 11 1]
6

FORCE REPLACEMENT GROUP 1
FORCE REPLACEMENT GROUP O
FORCE MISS GROUP 1

FORCE MISS GROUP 0
DISABLE UNIBUS TRAP
DISABLE TRAPS

11.288%

Figure 4-11

Control Register

Table 4-5
Control Register

Bit

Name

Force Replacement

Function
Setting these bits forces data replacement within a group
in the Cache by Main Memory data on a read miss. Bit 5
selects Group 1 for replacement; bit 4 selects Group 0.

3-2

Force Miss

Setting these bits forces misses on reads to the Cache. Bit 3
forces misses on Group 1; bit 2 forces misses on Group 0.
Setting both bits forces all cycles to Main Memory.

Disable Unibus Trap

Set to disable traps to vector 114 when the parity error

signal is placed on the Unibus.
0

Disable Traps

Set to disable traps from soft errors.

4.8.5
Maintenance Register (17 777 750)
This register, illustrated in Figure 4-12, is used for

4.8.6

memory

dicates whether the six most recent references by
the CPU were hits or misses. A one indicates a

system

maintenance.

Table

4-7

lists

the

functions of the register bits.

The

Maintenance Register is read/write. It is
cleared on power-up or by Console Start. It is also
cleared whenever any memory system error is
detected.

Hit/Miss Register (17 777 752)
The Hit/Miss Register, illustrated in Figure 4-13, in-

read hit; a zero indicates a read miss or a write.
The lower numbered bits are for the more recent
cycles.

All the bits are read only. The bits are undetermined after a power-up. They are not affected by a

RESET instruction.
This register is for maintenance use only.

This register is for maintenance use only.

VI-4-21

Table 4-6
Control Register Bits 5:2

Control Register Bits

Bit Patterns

Force Replacement to Group 1

Force Replacement to Group 0

Force Miss on Group 1

Force Miss on Group 0

Disables Group 0

Disables Group 1

Disables Cache (Group 0 and 1)

Protects and maintains code in Group 0 while it is executed

)
N

Protects and maintains code in Group 1 while it is executed

—

MAIN MEMORYPARITY
PARITY—J

FAST ADDRESS
FAST DATA PARITY
MEMORY MARGINS

—~——

;,_l___J\

Maintenance Register

Use of Cache Registers

When a memory system error is detected, the processor traps to location 114, If location 114 is used
as a trap catcher, the operator can examine the
Memory System Error Register to determine the

type of error which has occurred. The Low Error
Address and High Error Address Registers can
then be examined to determine where in the program, and during what type of cycle, the error occurred. If statistics on the hit ratio are desired, the
Hit/Miss Register can be read. The Control Register can be read to determine what the control conditions were at the time the error occurred.

If location 114 is not used as a trap catcher, the
above tasks must be performed by the trap service
routine.

1 %

11.2858

Figure 4-12

4.8.7

If bit 14 (CPU Abort After Error) or bit 12
(Unibus Multiple Parity Error) of the Memory System Error Register is set, the address stored in the
Low Error Address and High Error Address Registers is the address of the first error and not the ad-

dress at which the most recent error occurred. The
address at which the most recent error occurred
must be reconstructed from the contents of the SP
(which points to the virtual address incremented by

2) and the appropriate Memory Management PAR.

The contents of the Memory System Error Register
and the High and Low Error Address Registers indicate the failing section of the memory system.

For example, if type MJI1 16K core memory is
used in the system, and a Main Memory parity error bit is set in the Error Register, all the information required to determine the failing 16K section

VI-4-22

Table 4-7
Maintenance Register

Bit

Name

15-12

Main Memory Parity

Function
Setting these bits causes the four Main Memory parity bits
to be checked as 1s.
There is one bit per byte; there are four bytes in the data
block.
Bit Set

11-8

Fast Address Parity

Byte

Odd word, high byte

0Odd word, low byte

Even word, high byte

Even word, low byte

Setting these bits causes the four parity bits for fast address

memory to be wrong.

Bits 11 and 10 affect Group 1; bits 9 and 8 affect Group 0.
7-4

Fast Data Parity

Setting these bits causes the four parity bits to be checked
as 0s.

3—-1

Memory Margins

Bit Set

Byte

Group 1, high byte

Group 1, low byte

Group 0, high byte

Group 0, low byte

These bits are encoded to do maintenance checks on Main
Memory.
Bit 3

Bit 2

Bit 1

Normal operation
Check wrong address
parity

Early strobe margin

Late strobe margin

Low current margin

High current margin

Reserved

All of Main Memory is margined simultaneously.

VI-4-23

-of memory is present. The Low and High Error Address Registers indicate the 32K section of memory
in which the error occurred. The Error Register indicates whether the error occurred on the odd or
even addressed word. If, for instance, the error occurred in the odd addressed word, the 16K section
containing odd addressed words should be

lect Logic consists of a BCD to one of ten decoder
(type 7442) and some gating. The A, B, and C inputs of the decoder are bits (03:01) of the Unibus
address. When input D of the decoder goes low,
one of the three writable Cache registers may be

replaced.

ing

written. Input D goes low at T60 of the Cache tim-

sequence

when

the

Cache

performing

Unibus Map write operation during which MAPB

If an FDM parity error bit is set in the Error Register, the bad chip is on the M8144 (DTM) module.
Knowing which group failed and the state of address bit A0l (from the Low Error Address Register), it can be determined which of the four word
sections of the FDM (Group 0 even and odd,
Group 1 even and odd) has failed.

CACHE REG H is asserted. If the A, B, and C in-

puts indicate a binary 2, 3, or 4, the “2,” *3,” or
“4TM output of the decoder goes low when input D
goes low: this causes the assertion of CCBH CLK
CONTROL

REG

CCBH

CLK

MAINT

REGL,or CCBH WRITE ERR REG L.

CCBH CLK CONTROL REG L clocks the ConIf an Address Memory parity bit is set in the Error

trol Register and loads it with the data gated from

the Unibus. CCBH CLK MAINT REG L clocks

ule. The Error Register indicates whether the error

the

occurred in the Tag O or Tag | Address Memory.

loads it with the data gated from the Unibus.

Mauaintenance

CCBL) and

If the Main Memory Address Parity bit is set, there

CCBH WRITE ERR REG L is input to a set of

may be a problem in the parity generator (Drawing
ADMJ) or in a memory controller parity checker.

CCBK), selecting the data gated from the Unibus.

- A failure in the Main Memory Bus address and con-

This data is invertéd and applied to the clear inputs

four type 8266 multiplexers (Drawings CCBJ and

of the Error Register flip-flops. Thus a 1 bit is in-

trol lines is the most likely cause for this error.

verted to a low level which clears the corresponding

If the Main Memory time-out bit is set, the most

Error Register bit.

probable cause is a memory controller failure. An-

other possible cause is a misconfiguration of the

Trap and Abort

Logic
- The Cache asserts CCBJ

System Size Register in the processor.

PARITY

TRAP

when

one

of the

two

trap

request flip-flops is set. One of the flip-flops is set
4.8.8

when the Unibus Map asserts PB on the Unibus

The

Cache

device

registers

and

their

associated

(MAPB PB DATA H asserted). The other flip-flop

logic are located on Drawings CCBF, H, J, K, and

is st when CCBK ANY ERR (1) H is asserted dur-

ing a valid processor cycle (CCBJ VALID CP CYC

Figure 4-14

is a

block

diagram

showing the

Cache device registers and associated logic. Each

H asserted) or a Unibus Map memory (i.e., non-

block in the figure references the page of the engi-

neering schematics on which the logic is located.
CCBK ANY ERR (1) H is asserted as a result of:
Read Multiplexer- The Read Multiplexer gates the

contents of one of the Cache registers onto the
DI5-00

05:00

are

lines.

multiplexed

15,

I-line

8-line

decode

of Unibus

time-out on the

Main

Memory

Bus

during a non-MBC cycle.

multi-

plexers on Drawing CCBF. These multiplexers are

controlled

14, and

address

[\S]

REG

parity error on

data read

from

the

FDM.

bits

MAPA ADRS 03:01 H (gated by the Unibus Map).
3.

The remaining register bits are multiplexed by dual
4:1

line

multiplexers

shown

Drawing

A parity error on address tags read from

the Address Memory.

CCBF.

These multiplexers are controlled by an independ-

A parity error on data read from Main

Memory during a non-MBC cycle.

ent decode of the Unibus address bits.

VI-4-24

Umiiiiiiiiim
Figure 4-13

]

-+—— FLOW
1

11.2883

Hit/Miss Register

HIT/ MISS
REGISTER

(CCBL)

UNIBUS MAP DATA
"]

MAINT ENANCE
REGISTER

ggvgg%

ELECT

(ccBL)

ERROR

(CCBJ
K)

(CCBH)

READ

MULTI PLEXER

»[
|

conTROL
REGISTER

(CCBH)

[

LOW ERROR
RE SS
ADD
REGISTER

(CCBH)

UNIBUS
MAP

HIGH ERROR
MUX

FROM

m\"fus

CACHE

(CCBH)

(CCBF)

REG

REe eER

ADDRESS BITS 3.0

CONTROL
H)
(CCBF
1-2850

Figure 4-14

VI-4-25

If traps are disabled (CCBH DIS TRAPS L and
CCBH DIS UNI TRAPS L asserted), assertion of
CCBH PARITY TRAP H is inhibited.
The trap

request

flip-flops are cleared

upon in-

itialization (CCBA INIT D L asserted) or when the
processor acknowledges receipt of a trap request
(TMCA

PERF ACKN

knowledge

(PDRH

L asserted) or abort ac-

CACHE

PERF

asserted).

The trap request flip-flops are also cleared when
the processor traps due to a Unibus parity error
(UBCB UBUS PAR ERR H asserted); this is done

because the Unibus parity error trap routine will

Error Address Register Logic
- The Error Address
Register (Drawing CCBH) is in an undetermined
state at power-up, and is loaded with a 22-bit physical address and operation control bits at T60 of
each Cache cycle. If any error is detected, further
clocking of this register is inhibited by the negation
of CCBJ CLK ADRS H. Thus, the address at
which the error occurred is maintained in the Error
Address Register.

CCBJ CLK ADRS H is negated when one of the
trap request flip-flops is set.

also handle other concurrent trap conditions.

The Cache asserts CCBJ PARITY ABORT H to

abort the processor. This occurs if the Cache can-

not supply good data (DTMM BAD PARITY H
asserted) to the processor, or when a Main Memory Bus timeout occurs during a processor cycle
(CCBD CP TIMEOUT L asserted).
The processor acknowledges receipt of CCBJ PARITY ABORT H by asserting PDRH CACHE
PERF L. In an abort due to a timeout, the processor asserts PDRH CACHE PERF L in response
to CCBD CP TIMEOUT L; PDRH CACHE
PERF L then asserts CCBJ PARITY ABORT H.

Clocking of the Error Address Register may again
be enabled by servicing the error condition that
caused CCBJ CLK ADRS H to be negated. Note
that CCBJ CLK ADRS H can be immediately asserted by simultaneously clearing Error Register
bits 15 and 13.

Negation of CCBJ CLK ADRS H causes the assertion of CCBJ AOK (0) H. Therefore, if another error occurs after the error that caused the Error
Address Register to lock, bit 14 or 12 of the Error
Register is set.

VI-4-26

APPENDIX A

BLOCK DIAGRAMS

MEMORY MANAGEMENT

[
i8/22 BIT 16 BIT

.
BITS <21:16>

SAPJ

A
S

{

A
8
&

A SAPJ g

S
>

<«

ABORT

FAGE LENGTH ABOR

ACF ABORTS

SCCK

SWITCH REG <21:16>

ACCESS CONTROL
LOGIC

PDR

KERNEL

ct——

PROCESSOR DATA PATHS

—

Sa P

SAPL
A

—

)
fi

Vv
!

BIT

t
PDR<14:08 >

A
8

::/

VAL12:06>

———

—

SAPD

av—

PDR

SUPER

USER

SAPE

SAPF

PAF <21:06>

| D

I I D

I l D

KERNEL

SUPER

USER

PAR

SAPA

SAPB

PAR

SAPC

e—

———

[

[—é%—l

{

SYS

SIZE

REG <21:14>
VA<12:06>

SCCN

{ 9

{

[_ésL|

e—

| S

PDR<02:00>

C—

<15:13>

[ ]

ALU BITS <21:06
>

SAPH

COMPARATOR

c—

PAGE LENGTH

SAPL

c—

g
EX MEM
FLAG

]

0
o

sapL

8 TRAPS

FIELD

VALID ADDRESS CHECK

(T UBCA) UNIBUS ADRS |

_(TO

i
—

TMCC)

NOT

CACHE

ADRS

BAMX <15:00>

UNIBUS

ADDRESS DRIVERS
I

SAPN

— 4
UNIBUS

11-4096

Figure A-1

PDP-11/70 Address Paths

Block Diagram (Sheet 1 of 2)

A-1

I UNIBUS MAP

' CACHE

MBC BUS PA <21:00>
BITS<09:02 >
POWER UP LOGIC

UB REQUEST

PA<21:00>

ADMJ

T
UB MAP PA<21:00>

————MBC BUS COL

rMBC BUS C1L

BITS <21:00>

MBC

ADDRESS

COMPARE
MAPF

\/I
5

LIMIT

ALU

ADRS BITS <21:01>
FUNCTION: A+B

SWITCHES

A'B

3Y3T5>MASK

BYTE MASK LOGIC

BITS <21:00>

<01:00>

spme,F

ADMJ C@ H

ADMJ

<01:00>

21:00

SYS ADRS

CCBH

BITS

<21:16> | <15:01>

MAPD

MAPC

VALID
BIT GROUP

14:10

21:15

ERROR REG

17:00

BITS

|MBC

—————CCBD READ L

UNIBUS MAP REGS

37:20

cg.c1

21:01

BITS

ct
¢g,

CACHE ADDRESS MUX
warE

Z\
I
UNIBUS MAP REGS

|MBC

UNIBUS

CPU

ADMH

|ci

MAPB

uBcC

MBC ADDRS REG

}FROM RH70

MBC BUS CX L

VALID

PARITY
GENERATOR "A"

PARITY
GENERATOR"B"

<21:15>

<14:10>

BIT GROUP

,J
ADMF

ADMF
A

PARITY

GENERATOR

LO REGISTERS

WRITE ENABLE

ADMJ

WRITE ENABLE

<21:02>

MUX

HI REGISTERS

MAPC
A

09:02

4 N A

MAIN MEMORY BUS ADRS
LINE DRIVERS

UB MAP

ADML

REG OP

UNIBUS MAP REGISTER
DECODE
MAPB,C

21:10

BIT

N g 7

CCBM_l

VALID

TAG

GROUP @

09:02

STORE TM 59:02
| TAG
| PARITY
PARITY
<21:10>
wn
"o
ADMA,B

VALID

BIT

TAG

GROUP 1

STORE
| PARITY | TAG
PARITY
<21.00>
wan
ey 0
'ADMC,D

UNIBUS

MAPA

21:10

CCBM

)

BUFFERS

BITS<I7:13>

~
o
2

i /-

RECEIVERS
ADDRESS

MAPA

ADDRESS

e — —

—

COMPARATORS

—

ADMK

TAG @ PARITY ERR

HIT

TAG 1 PARITY ERR

11-4097

Figure A-1

PDP-11/70 Address Paths
Block Diagram (Sheet 2 of 2)

A-2

PROCESSOR DATA PATHS

[

iy “[ | WIA’IJI

CACHE

INE

oy
R

———

>
V]

DATA

e [=F

DATA

MEMORY

FROM FPP

MGMT
BR

(o]

A\
4

[o]

PARS

PDRs

t|ofr]o]t]o
K

v
[,

tfof1]o|1]o0

UNIBUS MAP

APF

\/.

BIT MUX

UB MAP REGS

SCCH

37:00

PDR

PAR

MUX

g
SAPM

x
<

UNIBUS

DATA

RECEIVERS

REG MUX & DRIVERS

DRIVERS

SSRJ

:;:J

2
2

[72]

[&)

UNIBUS

DRIVERS
DATA

sc CH

PDRE

UNIBUS

| RECEIVERS

DATA

LATCH
MAPH

DATA

MAPA

MAP

REG

MUX
MAPJ

72}

MUX 8 DRIVERS

UB DATA
DRIVERS

MAPJ

SCCM,N

JhiBuS

INTERNAL

CACHE

o
|

MAPH

MAPC,D

PDRJ

Q
=

DATA

REG DATA

CACHE

CONTROL

CACHE

DATA

BUS

>
11-3444

Figure A-2 PDP-11/70 Data Paths
Block Diagram (Sheet 1 of 2)

CACHE

MAIN MEMORY DATA BUS <35:00>

‘

MAIN MEMORY DRIVERS

MEMORY RECEIVERS USED

32 BITS (CDPC,D)
F
BYTE PARITY Y (CDPF}

AS MBC DRIVERS
32 BITS + 4 BYTE PARITY
orc.o

ld
0

)
.

15:00
+ 2P

PARITY

GENERATE

Y—-—-—

(CDPF)

(

MAIN MEMORY

32 BITS + BYTE PARITY
BD REGISTER

/\_,

CDPA

RB/RA ENB

J\ /L

HIGH WORD

MUX DEPOSIT

CCBH

GENE MDPEC

MBC BUS
DRIVERS

32 BIT MUX

<3116
>
MDPH

PARITY
le— — — — — %':‘ECKED

le— — —

| |

GROUP

GROUP O

LO WORD | HI WORD | LO WORD

INVERT

MDPD

qL
B

DTMB

MBC BUS

MDPB

<15:00>
MDPH

DRIVERS

{}

A__

MBC BUS

LV4

WRITE

CHECK
COMPARE

HI WORD

15:00 + 2P |15:00+ 2P 15:%%+2P 15:00 + 2P

DTMP

MDPB

DTMH DTMJ |DTMK DTML|DTMC DTMD|DTME DTMF
cSoL

RC REG

MIXER

]

\ V4

HopC

GENERATE

RD/RC ENB

{}

CDPF

CHECK &

RAT

LOW WORD

MDPB

PARITY

CHECK &

RD REG

CACHE REG

RA REG

MDPD

PARITY

MDPB

MDPC

DRWECT)SPC b

CSiL

DTMB

]

A MUX

RB REG

DATA AND

PARITY BUS

15:00

MDPC

0DD WORD ‘ EVEN WORD

@ |>

n
-

TNORY DATABUFTER

15:00

35:00

CDPE

B MUX

15:00
+ 2P

r—

WRITE MUX

MBC BUS

A
RE REG

MDPE

MDPF

MASSBUS
RECEIVERS
MBSA., B.C

INVERT
DTMP

BARITY

DTMC.D.E.F

G%'LEECRA%
K

[___I

MDPE

;

RF REG

MDPF

MASSBUS

FDM

parity

V| _________

CHECK

(DTMN)

OUT BUF

MDPF

RF REG
MDPF

MASSBUS
DRIVERS

MBSA,B,C

CACHE DATA MUX

DTMM

UB DATA
DRIVERS
BCTC,D

UNIBUS

UB DATA
RECEIVERS

I MUX
I

MDPH

BCTD

11-3445

Figure A-2

PDP-11/70 Data Paths

Block Diagram (Sheet 2 of 2)

INDEX

This Index lists the principal references to the CPU
modules (slots 6 through 22 of the processor back
plane). Each module schematic sheet is listed sepa-

rately. Roman numerals indicate the Section of this
manual which contains the reference; arabic numer-

als indicate the Chapter and the Paragraph within
the Section.

ADM (M8$143)

CCBA

V142,487

VI 3.8.5, 3.8.6, 3.8.7, 3.8.8, 3.8.9, 3.8.10, 4.3,
43.1,4.3.2,43.4

ADMA
V14.2.6,4.2.7

CCBB
VI 3.8.1, 3.8.2, 3.8.3, 3.8.4, 3.8.5, 3.8.6, 3.8.7,
3.8.8, 3.8.9, 3.8.10, 4.2.1, 4.2.2, 4.2.11, 4.3.2,

ADMB
V1 4.2.6,4.2.7

4.3.4,44, 4.5

ADMC

CCBC

V14.2.6,4.2.7

I1 48.1.2, 4.83.2, 5.1, V 2.0-2.4, VI 34, 3.5,
3.8.2, 3.8.3, 3.84, 3.8.5 3.8.6, 3.8.7,

3.8.1,

ADMD

3.8.8,4.2.23, 4.3.2, 4.3.4, Table 3-2, Table 3-3

V1427

CCBD

ADME

I 6.2.1.4, 6.2.3.1, V 2.6 VI 3.8.2, 3.8.3, 3.8.6,
3.8.7, 3.8.8, 3.8.9, 3.8.10, 4.2.20, 4.3.1, 4.3.3,
4.6.3, 4.7, 4.8.8, Table 3-2, Table 3-3, Table 3-

IV 4.5, V14.2.2,4.2.5,4.2.20
ADMF

V14.2.2,4.25,429

CCBE

ADMH

VI 3.6, 3.8.2, 3.8.3, 3.8.6, 3.8.7, 3.8.9, 3.8.10,
4.2.1,4.3.1,4.3.4,4.6.2.1, 4.6.3 Table 3-4

V1 4.2.1,4.5

ADMIJ
IT

6.5.3.1,

CCBF
VI

3.7,

422,

42.3.

4.2.7 4.2.9,

V 2.3, VI 4.8.8, Table 3-3

4.2.20, 4.4, 4.7, 4.8.7

CCBH

ADMK

VI 3.8.8, 4.2.10, 4.8.8

VI 3.8.5, 3.8.6, 3.8.7, 3.8.8, 4.2.7, 4.2.10

CCBJ

ADML
IT

6.5,

6.53.1,

4.3.3, Table 3-4

6.53.2,

I1 6.2.3.1-6.2.3.2, 6.3.3, VI 4.8.8, Table 3-2

3.6, 4.2.3, 4.2.4,

CCBK
I16.2.3.2, VI 4.8.8

CCB (M8142)

CCBL

VI 3.8.8, 4.2

V1 4.8.8

INDEX-1

CCBM

DAPF

CDP (M8145)

DAPH

I 2.1.1.1-2.1.2.2, 2.1.7, 2.2.1

V14.2.3,4.2.7,4.2.8,4.2.20, 4.4, 4.7

I12.1.1.1-2.1.1.2, 2.1.2.1

VI 4.2

CDPA
VI 4.2.16

DAPJ

CDPB
V1 4.2.17, 4.4

DTM (M8144)
V1 4.2, 48.7

CDPC

DTMA
VI 3.8.3,4.2.19, 44

1 1.2.6.2,2.1.1.1, 2.1.2.1, 2.1.3, 2.1.7, 2.2.1

38.2, 3.8.3, 3.8.6, 3.8.7, 389, 4.2.14,

4.2.15, 4.2.16, 4.3.3, 4.3.13 Table 3-4
CDPD

DTMB
VI 3.8.7, 4.2.20, 4.4

CDPE

DTMC
V1 4.2.20

VI 4.2.13, 4.2.14, 4.2.15, TABLE 3-4

11 2.3.3,VI4.2.11,4.2.12, 4.4

DTMD

V1 4.2.20

CDPF

V14.2.12,4.2.17,4.2.18, 4.4

DTME
V14.2.20

CDPH
VI 4.6

DTMF
VI 4.2.20

CDPJ

VI 3.6, 3.8.9, 3.8.10, 4.2.11, 4.2.17, 4.5, 4.6,
46.2,4.62.1,4.6.2.2, Table 3-4

DTMH
V1 4.2.20

CDPK
VI 3.6, 3.8.9, 4.2.16, 4.6, 4.6.3, Table 3-4

DTMJ

DAP (M8130)

DTMK

DAPA

DTML

V1 4.2.20

VI 4.2.20

11 2.2.1,2.2.3, 111 2.11, V 2.3, 2.5, VI 4.2.20

11223

DAPB

DTMM

DAPC

DTMN
VI 4.2.21

VI 4.2.17, 4.2.23, 4.8.8, Table 3-2, Table 3-3

T 2.1.9.1-2.1.9.2, 2.3.1, VI Table 3-2

I12.1.9.1-2.1.9.2
DAPD

DTMP

V1 4.2.22

I12.1.9.1-2.1.9.3, 2.3.1
DAPE

I12.1.94, 6.1.1, 6.2.1.3

GRA (M8131)
I12.1.1.2

INDEX-2

GRAA

IRCJ

IT 1.54,2.1.1.1-2.1.1.2, 2.1.2.2, 2.1.9.2

I11.2.6.2,2.1.3

GRAB

MAP (M8141)

I1 1.4.2, 1.5.7, 2.1.2.1, 2.1.4, 2.1.7

GRAC

MAPA

IT 2.1.4, 6.2.2.1 IV 9.2

11 2.3.3, V 1112, 2.0-2.2, 3.2-3.4, VI 3.8.6,

3.8.8, 4.8.8, Table 3-3

GRAD
IT 2.1.4-2.1.7

MAPB
V

GRAE

1.2, 2.0-2.1, 2.3-2.6, 3.2-3.4, VI 3.5, 3.8.8,

4.8.8, Table 3-3

IT 2.1.6

MAPC
GRAH

V1.1-1.2,32, 34

I12.1.4, 2.1.6-2.1.7

MAPD

GRAJ

V1.1-13, 32,34

IT 2.1.2.1, 2.1.5, 2.1.8

MAPE

GRAK
T 1.2.6.2

V1.1, 1.3 21

MAPF
INIT

V 1.4, 2.0-2.1, 2.5 VI 3.5, 3.8.5, 3.8.6, 3.8.7,

1.2.2,

264,

1.4.1, 4.5, 6.5.1-6.5.2, 11T 1.1.9, 2.4,

273,

7.1,

9.2,

1.0,

3.8.8, 4.5, Table 3-3

VI 4.2.11,

4.2.17

MAPH
V23,25, 3.0, 34-35

IRC (M8132)

MAPJ

111.2.3, 1.4.7, 2.1.6, 3.9.10
IRCA

V21,23-24,32, 34
MAPL

I11.45,154,224,1V 3.4

vV 3.0, 34, 3.5

PDR (M8134)

IRCB

11148, 2.1.5,2.1.9.2, VI 3.4
PDRA

IRCC

I 2.2.1-22.2,233

11 1.4.7,2.1.9.3, VI 3.2-3.4
PDRB
IT 2.2.3, 3.1, IIT 2.11, VI Table 3-2

IRCD

IT1.5.8,2.1.93,6.1.1, 6.2.1.1
PDRC
IRCE

I1 3.6, 3.8,4.9.2, 6.2.2.2

T 1.2.6.2, 1.5.1, 1.5.5, 1.5.7-1.5.8
PDRD
IRCF

I11.2.6.2, 1.5.1-1.5.2, 1.5.5-1.5.7, 2.1.2.1
IRCH

151,

3.7,

39-39.1,

6.2.2.1, 6.3.1, 6.3.8
PDRE
I1 2.3.2, 5.3.1, 5.3.2.1

I11.5.1, 1.5.3-1.5.4, 1.5.6, 1.5.8, 2.1.1.2, 3.9.2

INDEX-3

3.9.6,

3.9.8,

3.9.10,

SAPC

PDRF

IV 6.2,7.2.4

IT 2.3.4, IIT 2.11

SAPD

PDRH

I1 2.2.3, 2.3.4, 6.2.14, 6.2.3.1-6.2.3.2, 1II 2.0,
2.11-2.12, VI 4.8.8, Table 3-2

1V 6.2, 7.2.5, 8.1.2
SAPD.E.F
IV 6.2, 8.1.1

PDRJ

I1 2.2-2.2.1, 5.1, 5.3.2.1, 6.4.3
SAPE

IV 3.3,7.2.2

RAC (M8133)
IT11.2.3

SAPH

IvVva45,5.1,7.1, 722723

RACA

I 1.1, 1.4.1, 2.1.6-2.1.7, 2.2.1,
4.8.3.1-4.8.3.2, 6.2.1.5, 6.2.3.2

2.2.3-2.24,
SAPJ

IV 4.0, 4.5, 5.2-5.2.2, VI Table 3-2

RACB

I1 1.1, 1.4.1, 2.3.1, 4.8.3.1, 5.3.2.2, 6.2.2.1

SAPK

I 2.1.2,1V 3.4, 3.5,72.2,7.24,9.1.6

RACC

1.1,

2.1.1.2,

2.1.8,

2.1.9.1-2.1.94,

5.1.1,

SAPL

IV 6.2, 8.1.1, 8.2.2-8.3, 9.1.9

6.4.3

SAPM

RACD

I1 1.4.1-14.2,2.3.4, 1V 3.1

IV 7.23
SAPN

RACE

I1 4.8.1.1, 4.8.3.2, 5.1, 5.3.2.1, 6.2.1.2, IV 2.2,

I11.4.6.1-1.4.64

5.1-5.2.2

RACF
SCC (M8140)

I11.4.6.3-1.4.64

I 2.2, 1V 2.2, 7.1
RACH

11 1.25.1, 1.2.6.2, 145, 1.4.6.3-1.4.64, 5.1,
5.1.2 VI 3.4, 3.8.1, 3.8.2, 3.8.3, 3.8.4, Table 3-

SCCA
I 2,10, 1V 4.5, 5.2, 7.1

SCCB
IV 7.1,9.1.8

RAC]

I11.4.5,224
SCCC

I1 2.2.2.1-2.2.2.3, 1V 3.3-3.5, 5.1-5.2, 6.2, 7.1,
7.2.2,7.2.4-7.2.5, 8.3, 9.1.8-9.1.9, 9.6

RACK

I11.4.4,2.1.8,2.2.3,III 2.5.1-2.5.5
RACL

SCCD

I1 1.2.1, 1.4-14.2, 144, 1.46.2, 1.4.64, 1.4.7

I12.22.1,22.23,48.2.1,51,1V 7.1, 7.25

I 2.5.1
SCCE

IT123.2,39.2,53.2.3,6.2.2.2,638, IV 7.1
SAP (M8137)

SCCF

11 2.4, 2.6-2.6.1, 2.7, 2.7.3, 2.10-2.10.1, 2.12,

SAPA.B.C

7.1

1V 3.0, 7.2.3

INDEX-4

SCCH
11222, 11 23,1V 9.6

SSRL

SCClJ

TIG (M8139)
VI 4.3

IV 3.1

1 2.2.2.2, 111 2.0, 2.3-2.4, 2.10

TIGA

SCCK

11 2.2.3, 4.5-4.6.2, 4.8, 4.8.1.1, 4.8.1.2, 4.8.2.2,
4.8.3.1-48.3.2, 49.1, 53.2.1, 6.2.3.2, IV 7.1,

I 1.1.2, 2.10-2.10.2, 4.5

9.1.8

SCCL

IT 5.3.1, 5.3.2.1, 34, 4.5,9.6, V 1.1

TIGB

I1 3.6, 4.1-4.1.2, 4.2-4.4, 4.6-4.7, 4.8.3.2, 4.9.1-

SCCM
112.22,2223,34

4.9.3
TIGC

SCCN

11 1.4.1, 2.2.3-2.24,4.0, 4.4, 4.6, 6.4.1, VI 4.3,

112.22,22.24,32,34,1V52, 523

Table 3-1

SSR (M8138)

TIGD

IV 9.1.8

I11.4.1,2.2,4.6-4.6.2

SSRA

IT 3.9.6, 6.1.3.2, 6.2.1.3, 1V 3.1-3.2, 34, 4.5,

TIGE

I14.7,1V 3.1

523,9.14,9.2
SSRB

11 2.12, 1v 3.0, 3.3-3.4, 8.1.2, 8.2.2, 9.1.59.1.6

TMC (M8135)
IV 5.0
TMCA

SSRC

I1 4.8.2.2, 6.2.1.5, 6.3, 6.3.2, 6.4, 6.4.3, 6.5.1,
I11 1.3.5, 2.6.1-2.6.2, 1V 8.3, VI 4.8.8, Table 3-

I 5.1.4, 6.2.1.3, IV 6.2, 7.1, 8.1.1, 8.2.2-8.2.3,
9.1.4,9.1.8-9.2

2
SSRD

TMCB

IV 83

IT 6.1.1, 6.1.34, 6.2.1.3, 6.3, 6.4, 6.4.3, 6.5.1,
IIT 2.6.1

SSRE

IV 45,8.3,9.1,9.1.4,9.1.8-9.1.9
TMCC

I1 14.1, 4832, 51.3-5.14, 53.2.2, 6.2.16.2.1.3, 6.2.1.5-6.2.2.1, 6.2.2.3, 6.2.3.2, 6.5.1

SSRF

1V 9.2

TMCD

SSRH

I1222.1,1V7.1,9.14,9.2-9.3

222,

2223,

23.2,

3.5

5.14,

5322,

6.2.1.1, 6.2.2.2
SSRJ

I1222-222.1,2223,1V 7.2.3,9.1.8, 9.2-9.3

TMCE

SSRK

2.10.2,

3.1,

3.3-34, 5.2.3, 8.2.3-8.3,

9.1.4,9.1.89.1.9

INDEX-5

IT 2.1.9.3, 3.9.2, 3.9.6, 39.8, 5.1-5.1.1, 5.1.4,
6.2.1.3, 6.2.2.1, 6.2.3.2-6.3.1, 6.4.3, 6.5.1, III
2.6.1, 2.12, IV 7.2.4, 8.2.3-8.3, 9.1.8-9.1.9, VI
3.4, 3.8.2, 3.8.3, 3.8.4, 4.3.1, 4.3.2, Table 3-2

TMCF
IT

UBCC
2.2.1-2.2.2,

22.2.2,

39.2, 48.1.2, 4.8.3.1-

4.8.3.2,5.1.4, 6.3.8, I1I 2.12

5.3.1-5.3.2.1, 5.3.2.3, 6.4, 6.4.3, III 2.6.2,

2.7.3 IV Table 3-2
UBCD

UBC (M8136)

114.8.2.2,483.2,53.2.2,6.3, 6.4-6.4.3

UBCE

UBCA
I

I 2.3.2, 5.3.2.1, 6.5-6.5.2, 6.5.3.1, 111 2.7.3, VI

232,

48.2.1-48.2.2,

5.1,

5.3.2-5.3.2.3,

Table 3-1

6.4.3, 111 1.3.5, 2.11, IV 4.5

UBCF
UBCB
IT

IT
1.4.1,

1.5.1,

5.3.2-5.3.2.3,

3.9.2, 48.2.1-48.2.2, 48.3.2,

6.2.14,

6.23.1-6.2.3.2,

6.2.1.3, 6.2.1.5,

6.4.3,

6.5.1-6.5.2, 111 2.11-2.12, IV 7.2.4, 8.2.3, 9.1.8,

1II

2.6.1-2.64, 2.7.3, 2.12

UBCH

VI 4.8.8, Table 3-2

11T 2.5.2-2.5.5, 2.6.2

INDEX-6

2.4, 2.5.1-2.5.2, 2.5.4,

’
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