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Document:	VAX 8800 System Technical Description Volume 3
Order Number:	EK-KA883-TD
Revision:	PRE
Pages:	513
Original Filename:

OCR Text

EK-KA883-TD-PRE

VAX 8800 System
Technical Description
Volume 3

FOR INTERNAL USE ONLY

dlilglilt}a)I

EK-KA883-TD-PRE

VAX 8800 System
Technical Description
Volume 3

FOR INTERNAL USE ONLY

Prepared by Educational Services

of
Digital Equipment Corporation

Preliminary

Digital Equipment Corporation
All Rights Reserved

The information in this document is
without
notice
and
should
not

commitment by Digital
Equipment
Corporation
errors that may appear

A Computing

July

1986

subiject
to
be
construed

Equipment
Corporation.
assumes no responsibility
in this document.

Printed

Class

Edition,

change
as
a
Digital
for any

U.S.A.

Devices

Notice:

This equipment generates, uses,
and
may
emit
radio
frequency
energy.
The
eguipment has been type
tested and found to comply with the limits for a Class A
computing device pursuant to Subpart J of Part 15 of FCC
rules,
which
are
designed
to
provide
reasonable
protection
against
such
radio
frequency interference
when operated in a commercial environment.
Operation of
this
equipment
in
a
residential
area
may
cause
interference in which case the user at his
own
expense
may
be
required
to
take
measures
to
correct
the
interference.

The

following

are

trademarks

Digital

Equipment

Corporation:
logo

DECwriter

RSX

logo

DIBOL

Scholar

DEC

MASSBUS

ULTRIX

DECmate

PDP

UNIBUS

DECset

P/0OS

VAX

DECsystem-10
DECSYSTEM~20

Professional
Rainbow

VMS
VT

DECUS

RSTS

Work

Processor

1986

CONTENTS

SECTION

MEMORY

SYSTEM

(MBOX)

MBOX

FUNCTIONS

MBOX

OVERVIEW.

Signals

Used

MBox

D DD W N

Y
Y
SO

s
o

T UT U U

L
.
L]

S
[]

YOO OYUN

[

Bus

Cycles

Octaword

Bus

Cycles
Cycles

(Table

1-7)

Read

Octaword

Bus

Cycles

(Table

1-8)

Hexword

Bus

Controller

Cycles

(Table

(MCL).

Sequence

Normal

Write

o«

Read

1-20

1-22

Read

Write

MEMORY

Memory

Select

and

Operation

CONTROLLER

OVERVIEW

1-32

1-33

2-1).

(MCL)

Cycle.

First

Read

Data

¢«

o«

~N O

Cycles.

NMI

Memory

BUSY.

Single-Bit

Error

Correction

eo]

Data

CSR

(DAD)

MCAS.

DAD

POrtsS.

Writes

NMI

Reads

from

Writes

¢«

Memory.

.«

Requiring

Correction

Decode

Addressing.

Reading
CSR

Reads

FUNCTION

CSR1
to

the

(FUNK)

Function

Field

Slngle Bit

Writes

Masked

Initially

Memory

Error-Free

RAM

During

NMI

Masked

the

Decode

RAM

NMI

MCA.

Parity.

iii

1-30

Cycle(s).

Write

1-25
1-29

Data

Reads.

.
(MAR4).

Write

Masked

Board

(Figure

Read

Array

Command/Address.

Operation.

Command/Address

1-9).

Interrupt.

1-6)
.

Bus

NMI

~N o ooy

(Table

1-3).

1-5).

Longword

"Next"

(Table

Read

MAR4

=W
N

*
.
o
¢
LJ
.

Quadword

DATA/ADDRESS

Cycles

Write

W N

Bus

Masked

e
o
.

Four-Megabyte

[

*®
@
¢

el
e

NN
NN N
NDNND

@
¢

N NN

NN
*

.
®

W N NN

.
.
.
«
«
«
.
Cycles (Table

Error

Command/Address

DFA

Bus

Read

NN
NN

Sort-of-Write

Longword

Memory

the

Write
Write

CHAPTER

Operations.

Command

T
*
.

T e

il e e

R
[

MBox

Octaword

R o

~NY SN SO N

Gy A S G

NMI

I
el ol
e e
e T
e Sy
- |
|
|
WHEHEFOWOOOO
BN

el
N

Y SO N N

PHILOSOPHY

SCOPE

WRITING

e
e
e

MANUAL

INTRODUCTION

Lock-Timeout Counter
Block Command. . « «

.
«

.
=

W N

Longword
Longword
Quadword
Octaword

<«

NMI

Confirmation

NMI

2-4).

DEAD

(Figure

2-24
2-26
2-26
2=27
2-28
2-30

2-31
2-32

MCL Immediately Gets the NMI
MCL Waits for the NMI,

Force

One

[]

DNDN

In.

Parity

Out

L
.

*
.

Parity
Parity

Fault Detect

NMI
.

(NI

ID/Mask

ID/Mask
ID

Out

(Figure

*
.

*®
.

In.
Out

2-33
2-34

2—-35

2-35

2-6)

(Figure

Cycle

2-32

2-6).

(Figure

MRM Hold Command

(F'

Read/Return and Read/Contlnue

NMI Function/ID Parity

B D
e
.

2—-24

to CSR.
. . .« .
. . . .
«

2-23

Memory

Faults

CSRs
N

N WwwihHH
O

Fault

Seguence

Write
Write
Write
Write
NMI

[}

[]
[]

Write

UT U

e
.

NEW CMD EARLY/NEW CMD LATE
Read Lock Function . . .
Write Unlock Function. .

ARBITRATION/ID (ARID) MCA,
NMI Data Parity {(Figure

[

[)

[]

i et e e el b= b= WO 00 00 00 00 0 N OGN U1 s W N

W wwwwwww

s BRBE_AEAEEPR,WWWWWWWWWW W W

NN NNNDNDNNNNDNDNODNRRNDNDNNNNDNDDDDD NDNNNNDNDDNDNDNDNDNDND

Decoder

Function

2—-35

2-7)

2-35

o
o

2-37

2-34

(Figure

2-38

L]
.

2-38

2—-38

2-8)

2—-38
2-40

2-40

2-9)

2—-42

2—-43

Arbltratlon/Hold Loglc .
Memory Gets the Bus Right Away
Longword

Read.

QOctaword

Read

2.4.5.2

Memory Gets the Bus Right Away

2.4.5.3

Memory Gets

2.4.5.4

Another Read Function.
Memory Gets the Bus Right Away -

2.4.5.5

Memory Does Not Get the Bus Right Away -

2.4.5.6

Memory Does not Get the Bus Right Away Two Longword Reads Back-to-Back

CSRs

N+

Longword

.«

Read.

or an Octaword Read.
Interrupts (Figure 2-12)

~1~J

s
b

s b

L
.

U O

Read

(Figure

\.«SRO

CSR3

Memory Busy
Clocks

and

MDP OVERVIEW
-

DNDNDMNDN

2-11).

......

Longword Read Back-to-Back with

Hexword

(Figure

the Bus Right Away

MDB

Address

2-46
2-47

2-13)

2-49

(Flgure

Clcck

Cont rol

(Figure
In

2 14)

.«

2-16)
«

2-49
[

ure
(F i
o

2-49

2=-50
2-54
2=-54

OO0~
U
WN
W N+
b

Address

Out.

2-54

Data

IN.

MDB

2=54

Data

Out

¢«

&«

o«

2-56

Bits

2-56

Write-Enable

and

Bad-Data

Data

Parity.

Data

Read

Masked

ReadS.

MEMORY

DATA

Data

¢«

2=57

¢«

&«

o«

2-57

Operation

2-58

o«

2=-59

Read

Write

POrt

Write

POt

CSR

LOGICe

MEMORY

DATA

(MDB)

(Figure

2-59

o«

2=-61

2-62

o«

2-62

o«

2-63

4«

o«

2-64

CONTROL

into

the

Octaword

2.7.1.3

Masked

Write

With

2.7.1.4

Masked

Write

With

Masked

Write

With

Unloading

Data

From

the

(MDBC)

MDB.

Normal

2.7.2

2.7.1.2

2.7.1.5

Empty.
X

Octaword Write

the

2-17)

Buffers
in

BUFFER

Data

Normal

Port.

POrt

BUFFER

Read

Operation.

Write

CSR

Address

L]
*
e
*
L]
L J

NDDODDDDNDNDND NN

o
e

@
o
e
o
o

SIS o oottt
g ot v n

NNV

MDB
MDB

2-66

2-67

and

2-74

With
«

.«

With

Buffer

Write

MCA.

Data

Already

¢«

Errors.

o«

2-76

Error.

2-78

Error

2-79

2-80

Correctable

Uncorrectable

MDB.

2.7.2.1

General.

¢«

2.7.2.2

Detailed

2-80

&«

2-82

2.7.3

Out

2.7.3.1
2.7.3.2

2.7.4

Logic

+«

¢«

2-83

¢«

Detailed

2-83

2-84

Internal

and

W N
OY Ul W

o
e

10U
> W N

o«

2=-89

¢«

o«

2-89

CSR2.

2=92

295

2- 28)

2-95

2-28)

2-98

2-33)

2-99

¢«

o«

2-104

Parity

2-105

¢«

o«

2=105

(Figure

Field

MDB

Address

Selection.

Select

Error

CSR

MSC

¢«
«

¢«

&«

o«

2=-106

&«

o«

2-106

¢«

o«

2-106

¢«

o«

2-106

¢«

2=107

e«

2-108

MCA)

2-108

2-35)

2-109

SEQUENCE

Buffer

CMD

and

Cycle(s)

Writes.

Buffer

Load.

Writes.

READS.

AMRM

(Flgure

(Figure

Write-Data

2-87
2-87

Board

Masked

O O
L ]

o
o

Clocks

Read-Data

e
e

Command

Octaword

c
MCA

NAB

Internal

RAM,

Mode

and

Decode

NAB

MEMORY

pood

o
e
®

[]
.

OCDODO-.

and

OVERVIEW

MDB

Generate.

Diagnostic
Reset
MRM

o
o

0
0 G0

0000

Status

Serializer

Error

o
e

O WO WO

o
o
*®
o

Write

(DCHK)

Check.

= WO W0 WO WO WO WO

Clocks
CHECK

Syndrome

DATA

Error,

Error

NNV NNDNNNDNNNRONDNDNNNDNNDNNNDNNNDNDNDNDND

Select

General.

.«

CONTROL

Control

BUSY
PROC

(MSC)

(Figure

Operation

2-109

¢«

o«

2-112

START

2-113

REQ.

BNUM

2.10.2

Probe

N
[N

and
o

¢«

Command

Channel.

Logic

Error
o

¢«

o«

2-38)

+«

2- 40)

Logic

Address

Logic

Machine
21
@

Write

Command

BitS

¢«

Logic

(Figure

2-44)

Command

Done

BMSC

PRE

CMD

DONE.

¢«

BMSC

PRE

MASK

DONE

&«

o«

MCA

2-46).

Parity

SEQUENCE

Store
Out

Read

Buffer

MDB

Address

CONTROL

(MSC1l)

(Figure

2-45)

Buffer

Control

Control
I/0

ARRAY

SEQUENCE

.«

Bits.

.«

(MASC)

.
.
.
L]

AN
W N

MCA

o«

Parity

¢«

Board

Number

(BMAS

BNUM<2: 0>).

SEL<2 0>).

Send

MASC

Empty

Command.
.

Select

CONTROL

(BMAS

SEQUENCER

Control

BMRM

o«

(Figure

BMRM

SERIAL
CSR

ARCS

FORCE

AMRM

MPR

BMRM

FAKE

Read

and
o
¢

Board
«
o
«

¢«

RDK2:0>.,
CMD

DATA

&
e

¢«

ACPT.

4«

¢«

SEL.

CMD ACPT

¢«

2-52).

2- 52).

Bits

(Figure

AMRM

READ

CMD<KO>

BRCS

READ

CMD<1>

Select/Enable

Board

Select

Board

MCA

2-50).

2-51).

RD.

WRITE

Command

(RCS)

(Figure

SERIAL

AMRM

2-48)

Error

CSR

Parity

Power

N =

Force

Board

(Figure

Command Accept (BMAS CMD ACPT)
Valid (BMAS BD VALID).
.
&4
&
«

2-47).

CONTROL

(Figure

Bits

Select

ADDR4.

Logic

Select

INVERT

2-49).

(Figure

Select

Command/Address

Command

NOY
U s W

*
L]

o
¢
[]

W NN
WW

READ

MEMORY

W ds b

WWWWWWWwwWwwWwwwwwww

(Figure

2-42).
e

Pointer.

Address

2-41)

(Figure

2-43)

Error

(Figure

BMRM

Logic

2.11.6

o«

Masked-Write

2.11.5

o«

Out

[

Address

NDNDDND

Address

(Figure

MDB

MDD

Buffer

MDB

(Figure

Address

2.11.4.2

2.,11.4.1

Write
e
S
s

Select

¢«

Address/Size

Mask

Incrementation

2,12

(Figure

Command

Starting

Write

Logic
o

Channel

Initial

Mask

o o o o o o o o o o
«
.
e e e s e e
Buffer (Flgure 2-37).

Address

MEMORY

NN NONNNDDNDNDNDNDNN

&«

Address/Size
Starting

Buffer

2-36).

Probe LOgiC. « o 4
Error LogicC. « + «
Command/Address/Size

Size

O
e

OO OOOOOOO0O0COCOO0O
[]
e
&
@
O

L]
.

HOWWOWOJIIAAWUMUTUdWwwwNN

o OO0

o
e
e
e
®
bt
e
e
[]
e
e
e
b
b
e

=
.

=
[

NN DNDNONDNDNDDNDNDNODNDNDDNDNDND

(Figure

Board

Select

o«

(Flgure
.

Enable.

2,13.5

Read

Data

2.13.5.1

AMRM

DRIVE

2.13.5.2

BMRM

2.13.6

RCS

NAB

Signals

NEW

GATE.

Full/Empty

(Figure

DATA,
.

Status

2-52)

2-153

(Figure

2-5 2).

2-153
2-154

2.13.6.1

ARCS

2.13.6.2

FULL.

o«

BRCS

EMPTY

2~-154

(BBU).

2-154

2.14

BATTERY

BACKUP

2,14.1

Loss

2.14.2

Return

CHAPTER

FOUR
VAX

2-154

Power.,

2-156

MEGABYTE
8800

UNIT

Power.

MEMORY

ARRAY

Signal

BUS

Clocks.

Longword

Write

Longword

Read

Octaword

Read

MAR4

Read
MAR4

.
.

(Figures
(Figures

Banks

Data

Flow.

.
.

Sequencing

Refresh

start
Bank

Sequencing

Mode

Cold

Array

Command

Differences

Parser

Command/Address

.«

Parity

Inhibit.,

Check

Data

Ready

Done.,

Board

Selection

Array

Not

Array

Busy

Battery Mode .
ECC/DPARITY.
.
«
ECC Check Bits

«v
,

Write

Inhibit.

Write

Data

INT
Data

BAD

Check.
.

.
.

Transfer

Data

Select.

Refresh.,

Bank

Battery

MAR4

SNC

Control.

Read

DRDY

Signals

Enable

MAR4

Control

Bank
.

Parity

DATA

Output

Read

Enable.

Data

Transfer.

CLK

Mode

Normal

Mode.

Battery

Mode

vii

MAR4

Generation

3-5)

3-6)

and

Components.

Array

Battery

3-4
3-4

Bank

Write

Array

Input

DESCRIPTIONS

Logic.

AMBARRAY

Operation

DETAILED

Timing

Operation

Clock

(NAB)

Timing.

BOARD

Timing

OVERVIEW.

Write

ARRAY

FIGURES

UT R

el
=
N

0~
O

NN NNNDODNOMNDNNDODDNDND
|
[
[
— O 0 ~J O U
= W+
N~ O

2-13
2-14
2-15
2-16

2-17
2-18
2-19

2~20
2-21

2-22

2-23
2-24
2—-25

2~26

2-27

Diagram

Block

O ~J O

MBox

i
e

. . « .
Diagram
=

Z
O

MBox Simplified Block Diagram. .
MBox Read/Write Simplified Block

el el

Page

Title

Command/Address Flow Diagram . . « «
Write Data Cycly Flow Diagram. . . .«
Read Data Cycle Flow Diagram . . + «
Masked Write Data Cycle Flow Diagram
MAR4 Read/Write Flow Diagram . . . .

«
«
«
.
.

.
.
.
.
.

1-23

MAR4

1-21
1-27
1-31

1-32

DFA Block Diagram. « « o« o o o o
DAD Block Diagram. . . .« .
c o
FUNK Function and Control Loglc.

o
e
o«

o
o
o

=
o
o

2-18

FUNK

Command

Fields.

¢«

2-11

2-25

Read/Return and Read/Continue Logic.
Clock and Command Control LogiC. . «
Parity Generation and Checking . . .
Fault Detect LOQiC .+« o ¢« o o o o o o

.
«
.
o

.
.
.
&

2-29

ID/Mask LOQIC. v & « & o o o
Arbitration/Hold Logic « « ¢«
NMI Arbitration/Hold Timing.

o
o
«

=
&
o

2-41

CSRS:

o
«
.

o
o
.

o
o«
«

o
o
+«

Interrupt LOGiC.e « ¢ « ¢ « o o o o o o o
CSR LOJiCue o 4 o o o o o o o o o o o o
Memory Busy LOQIiC. o ¢ o« o o o o o o o o
Clock, Reset, and Unjam Logic. . .
. o
Memory Data Path (MDP) Block Dlagram o o
Memory Data Buffer (MDB) Block Diagram .
CSR LOgiC.e o + o o« &
e e« o o s e o o »
MDBC -- MDB Data-1In Selectlon. c o s o e
Input Load Command Detect Logic. . . . .
Full LOgiC o
¢
o ¢
¢ o o
o
o
o
o o o o o
X and Y Bit Storage. . . .« ¢« ¢« ¢ ¢« o o .
MDBC -- MDB Feedback Selection . . . . .
Double-Bit Error Logic . . .
s o s e e
MDBC -- MDB Data-Out belectlon .« o e e
Y Out Select Flow Diagram.
. . .
. MDBC -- Internal Error, Write Decode RAM
and

CloCcks

2-28

DCHK

Block

2-29

¢«

2-44
2-45
2-48

2-51
2-52

2-53
2-55

2-60
2-65
2-69
2-70

2-71
2-72
2=-717

2-80
2-81
2-85

2—-88

o«

.
.
.«

«
.
«

«
«
«

o«
«
«

«
«
«

«
«
o+

2-31

Error Check Block Diagram.
Error Status Block Diagram
Serializer Block Diagram .

2-96

2-32

CSR2

Bit

2-97
2-100

Map

2—-40

Diagram

2-30

2-36

2-39

2-33

MRM

Block

Diagram.

+«

MSC

Block

Diagram.

2-35

Buffer

¢«

2-36

BNUM Probe Buffer and Error Logic.
Command/Address/Size Buffer. . . .
Size Logic .

.
.

2~-37
2-38
9]

State
Qb

Mac 0ain

viii

TM EE

wiagram

2-110

2-111

2-114

2—-117

2-119

Hex

2-91
2-93

2—-34

Control

2-90

2-121

2-40

Starting

2-41

Mask

2-42

Write

2-43

Mask

Address

Command
Write

2-44

Command

Mask

2~-46

Select-Out

2-47

Read

Buffer

2-48

MDB

Address

2-49

MASC

Block

Done

Store

2-50

Power

2-51

CSR

2-52

Array

2-53

MCL

Down

¢«

o«

LogiC

Diagram

Control

Control
I/0

BlOLk

Block

Select

Diagram

Dlagram.

Diagram.

.
.

Block

Diagram

o«

¢«

o«

Control

o«

Diagram.

o«

Diagram.

Block

Buffer

Read

Power

Control.

Power

Block

Control.

BBU

Buffer

LOogiC.

LOogiC

2-45

Flow

Diagram.

Write

Longword

Read

Timing

Diagram

.«

Octaword

Read

Timing

Diagram

OO0

i
dO0

WWwWwwwwwwwwwww

Logic

Address/Size

Timing

MAR4

Block

Diagram

Write

Flow

Diagram

o«

Diagram.

o«

Read

Flow

Clock

Logic

Clock

Timing

4MBARRAY

Block

Diagram.
.
«
«
o
o«
o
o+
o
Diagram .«
o«
«
o
o
o
o
o
o
o
&
Bank Block Diagram (Bank 0 Shown)

Array

Command

Flow

Diagram

o«

Array

Refresh

Flow

Diagram

.«

Input

Parser

Block

Diagram

o«

Diagram.

o«

Diagram.

ECC/DPARITY

Block

Data

Control

Output

Block

Refresh

Time

Refresh

Block

Refresh

Flow

Diagram

Refresh

Flow

Diagram

Periods

Diagram.

Normal

Mode.

Battery

Mode

Initiation of Battery Mode Refreshes .
Termination of Battery Mode Refreshes.,

NMI

WN
0 ~JO UL b

[

Title

MBox

e R S Ry Sy

TABLES

Signals

Write
NMI

Used

Command

Longword

Bus

Confirmation

Write
Write

the

MBox

o«

Cycles.

&«

Functions

Quadword*
Octaword

Codes

Cycles

CycleS.

Bus
Bus

&«

Read

Longword

Bus

Cycles

Read

Octaword

Bus

Cycles

Read

Hexword

Cycles.

¢«

o«

Bus

+«

.«

OPERATION.

=W
N

2-46

@«

.«

¢«

.«

I
L]

[}

[

IPINTR Source Register (IPINTRSRC)
Starting and Ending Address Registers
(SADR and EADR). « « « « +
BCI Control and Status Register (BCICSR)
Write Status Register (WSTAT).
Force IPINTR/STOP Command Register
L]

Interrupt

Noarnoaral
LAV I S B

Control
L]

Purnoc o
L
p Ay

oy 1aete
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RN
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LN
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User

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O

AND CIRCUIT TECHNOLOGY.

Registers

.
o
o
e

NDNDNDNDNDND
NN

N
NN

.
.

ADAPTER)

DIAGRAM.

3-2
3-26

el
|

BLOCK

BASIC

(UINTRCSR)
[\

+«

INTR Destination Reglster (INTRDES)
IPINTR Mask Register (IPINTRMSK)
IPINTR/STOP Destination Register

u1b1m
o N
—

L ]

BASIC

REGISTERS.

Code

o
Control/Status Registers (CSRO and CSR1)
Vector Registers (BR4VR through BR7VR)
NBIB (BIIC) Registers. . . . .
Device Register (DTYPE). . .
VAXBI Control/Status Register (BLICSR)
Bus Error Register (BER) . .
Error Interrupt Control Register

—

2-128

DESCRIPTION

(FIPSCMD).

(T.)I\J

b
.

b
0O

®
.

Utun U1 U

e
o

U
VTN

e
L]

INFORMATION.

NBIA

Ut on

2-123

PHYSICAL

NBI

1.5.2.13
n

o
I
e
B
o B

el e
N
.

el el

Tl =
o
*

—

CPU Read/Write Data Transfers.
DMA Read/Write Data Transfers.
Interrupt Operation. . . . . .

GENERAL

(FIPSDES)

o«

TO VAXBI

(EINTRCSR)

2-99

INTRODUCTION

<3:0>),
\.».1.-)/

2-82

CHAPTER

¢«

(NMI

2-59

NBI

2-34

Truth Table.

Clock Distribution . . . . « .
Read Bank Shift Register Modes

SECTION

[

o
&
o
o

Signals.

2-118

Code

Command

o
o
o«
+
o«
o
o«
.

State

o
.«
«
o
o
.

o
o
o
«
¢
¢
o
«

|
O
el il e

NAB

o
o

Write

v«

Address

o
o
o
.
«
¢
o
.

Write

[

W
w

Code€.

Initial

Size

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|
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WN -

Command Code . « « o o«
Size CoOd€.
o« o
¢ o
o o
Function Codes . ¢« ¢« «
NMI Confirmation Codes
Read Function CodeS. «
Read Command Code.
« «
Write Commands . «
o o
ENABLE ECC Truth Table

DESCRIPTIONS

NMI

Address

NMI

Read/Write

NMI

Arbitration/Memory

~] O

Timing

NMI

Interrupts

Errors

NMI

BUS

VAXBI L]

Space.

(BETWEEN

VAXBI

Signals.

W N

Basic

Timing

VAXBI

Address

VAXBI

Read/Write

Interrupt

w:.uw
ERTRE
W

(INTR,

(INTR)

Transactions.

Identify

(IDENT)

Transactions.

STOP

2.3.7

Invalidate

2.3.8

Bus

Interrupt

(INVAL)

Arbitration.

Modes.

Arbitration

Control.

Extending

Transaction.

2.3.8.3
2.3.8.4

Requests

Special
VAXBI

Mode

Errors

o«

Checking.

Parity

2.3.9.2

Transmit

Check

2.3.9.3

Protocol

Checking.

3.1.1

Error
.

¢«

Buffer.

Data

3.1.1.2

NPAR

MCA

3.1.1.3

NBIM

MCA

3.1.1.4

NBFD MCA

¢«

.«

3.1.1.5

NBAP

MCA

3.1.1.6

o«

NBCT

MCA

.«

&«

3.1.1.7

DSEQ

MCA

3.1.1.8

DC022

3.1.1.9

Data

3.1.1.10

Data

3.1.2.2

BCI

«
+
.«
.
Transaction Buffer

(Bus) Buffers . .
Bus (and Transaction

Block

3.1.2.1
3.1.2.3

Diagram

NMI

NBIB

.
Detection

Block

3.1.1.1

3.1.2

DESCRIPTION

INTRODUCTION

NBIA

Functions

2.3.9.1

FUNCTIONAL

(IPINTR)

Arbitration

3.1

2.3.8.2

IPINTR

Transactions.

Bus

and

Transactions.

2.3.8.1

IDENT,

Interrupt

2.3.6

CHAPTER

NBIB)

Transactions.

Operation

Transactions

2.,3.8.5

AND

Space.

Interprocessor

2.3.9

Busy.

Transactions).

NBIA

Transactions.

Bus

Diagram

Data

.
.
Buffer

Data Buffer.
.
.
.
Parity and Translation

Buffer)

Logic

Controls

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[
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NMI.
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L]
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NMI Signals.

*
L]

DATA

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DN
W N

Slave

+«

POWEYUD.

o«

INIT/UNJAM

READ/WRITE OPERATIONS.

Command/Address Cycle.
. .
Write Data Cycle .
Return Data Cycle. . .

[]
L]

o«

.
.
«

.
.
.«

.
&
.

Device).

=W
o -

Parity Generation and Checking
VAXBI Read/Write (and IDENT) Operations.
Command/Address Transfer .
Write Data Transfer. . . .
Return Read Data Transfer.,

=W
N -

..—l

—

(By Connected VAXBI

NMI Address Decoding and Translation
PR,
T~ =~ A
Vel 2~ o
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a g
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Parity Generation and Checking

Write Seqguence
NMI BUS ACCESS

TIMEOUTS.

.
.

VAXBI

Errors

Faults.
.«

.
.

READ/WRITE OPERATIONS.

Command/Address Transfer
Command/Address to BCI
and Data Bus Buffer. .

DMA

VAXBI Clock Drlver/Recelver.
.
INITIALIZATION/SELFTEST., . .
Basic NBI Initialization . . .
BIIC Initialization/Selftest .

RESET

WwWwwwwivNd

[]
o
e«
L]
o

and

BIIC

CPU

Sequencers

Port

Master

NBI

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Data Buffer Read/Write Control
Length and Interrupt Control Logic

Data

Buffer

Command/Address to NBIA's Transaction
o

Data Transfer.

Buffer.

Cycle)

Write

Buffer

Command/Address to NMI
¢

¢«

Data to BCI

Write

Bus

(NMI Command/Address

Data Buffer

and

Data

Cycles)

o«

DMA

ErroOrS

o«

Return

Read

Data Transfer.

¢ o o o
to NBIB

o
.

End of VAXBI Transaction (and Retrles) .
Write Data to NBIA's Transaction Buffer,
Write Data to NMI (NMI Write Data Cycle
.«

+«

o
.

o«

o
.

NMI Write Transaction Retries (NO
ACCESS/MEMORY BUSY/NOACK). + « « «

Return Read Data to Transaction Buffer
NMI Read Transaction Retries
(MEMORY BUSY):e ¢«
Return Read Data

Data to BCI

Return

Read

(VAXBI
End of

READ DATA CYCLE).,
VAXBI Transaction

Data BdffeL
.
.

«
.

=+
«

«
«

and

=
=«

=
=

DMA Errors (VAXBI Transaction Retries)
Parity Generation and Checking . . « . .+
xii

'__J

Return

Read

TIMEOULS.

s
|—

Oy
U >

Read

BIIC

w N

INVAL

N =

DIAGNOSTIC

~N 9O

Faults

AND

IPINTR)
.

Nodes)

Transactions.

BROADCAST

3-90

OPERATIONS

3-91

3-90

3-92

3-96

.«
«
«
o
«
«
Transactions

«
.,

o
.

3-96

¢«

3-97

3-98

to Memory
¢

3-97

(Flip

Address

o«

«
o
o«
o
o
o
Organization

o
.

bt
—

NBI

Configuration.

NBI

Basic

Transaction

Buffer

Read/Write

Data

Transfer

o«

DMA

Read/Write

Data

Transfers.

¢«

o«

SCB

Operation

Vector

Format

o«

(CbRO)

(CSR1l)

Format

(Example)

Control/Status

BR7VR)

o«

Device Register (DTYPE). . v v ¢ o o o
VAXBI Control/Status Register (BICSR).
Bus Error Register (BER)
.
«
.
&
¢«
«
o

o
.
o«

o
.
«

o
.
o

Vector

Registers

1-15

Error

Interrupt

1-16

INTR

Destination

1-17

IPINTR

Mask

1-18

IPINTR/STOP

1-19

IPINTR

(BR4VR

Starting
Ending

Address

1-22

VAXBI

Control/Status

1-23

Write

Status

1-24

Force

IPINTR/STOP

Address

User

General-Purpose

NBIA

Interrupt

N
W

NMI

NBIB

Address

(GPR

SPace

Xiii

.
.
.

(BICSR).

.
.

Input/Output

Timing

(FIPthS)

Registers

(WSTAT).

Control

.
.

(SADR)

Command

.
.

(SADR)

1-26

NMI

(IPINTRSRC)

1-25

(EINTRCSR).

(INTRDES).
(IPINTRMSK)
.
.

Destination

Source

and

1-20

BaSiC

through

Control

1-21

}

Diagram

CPU

Interrupt

W
N o O

Ry W
gy
Sy S
vy Seb
e I
e
T

|
|
WO 00O
U
W+

P
O

Title

INTR/IPINTR

3-96

FIGURES

DC022

3-88

Requests

<22>).

Block

3-86

TRANSFERS.

Wraparound.

and

Operations

DATA

Parity

Read/Write

and

Data/Mask

Requests.

OPERATIONS

Loopback

<29>

Write

Read/Write

Bits

VAXBI

o
«
.

o
o

NBIA

Interrupt

VAXBI

CPU

and

Data/Status

(INTR

Other

BIIC

Sequence

Decoding

(by
wwwwww

MISCELLANEOUS
[

OY OV Ul Ul W

PArity

INTERRUPT

—

[]

wwwwwww

Command/Address

(FIPSCMD)

(UINTRCSR)

<3:0>).

Signals

W N [ (B

NNMNMNDNODNNNDNDNDNNDNDDND
|
|
{
N
e
=
O 00~ Oy U W

NMI Write Transaction
. . ¢« ¢ ¢« o o o
NMI Read Transaction . « « ¢ « o« o o+ o
Basic NMI Arbitration Line Timing
. .
NMI Arbitration Line Timing (Typical)
MEMORY BUSY Timing «
« o« o
o
o
o o o o
Fault Signal Timing
. « « « + & o o o
Basic VAXBI Timing .+ « « o
o
o o o s o

&
=
.
.

2-13

2-22

2-14

2-16
2-18

2-19
2-34

2-37

VAXBI Node Register Space. « .
VAXBI-Required Registers . « ¢«
BIIC-Specific Device Registers

«
¢«
.

«
«
.

&
o«
.

&
o

2-38

VAXBI

Address

SpacC€.

2—-38
2-39

2-15

VAXBI

Write

VAXBI

Read

Length
Length)

2-42

2-16
2-17

VAXBTI Interrupt (INTR) Transaction . . .
VAXBI Identify (IDENT) Transaction . . .
VAXBI Interprocessor Interrupt (IPINTR)
TransactionN. «
o o o
o o
o
o
o
o
o o
o o
VAXBI STOP Transaction . ¢« ¢«
« o« o« « o
VAXBI Invalidate (INVAL) Transaction . .
Bus Arbitration Request Lines. . . . . .
Arbitration State Diagram. .« « «+ o « «
VAXBI Arbitration (Example). « « « « « =

2-46

2-18
2-19
2-20
2-21
B

I
(N

|
00~
O
w N fend o
b~

Detailed

Block

Diagram.

Detailed

Block

Diagram

NBI

POWELXUP

3-14

¢«

VAXBI

&«

Node

UNJAM/Programmed

NMI

NBIA

NBIB
Reset

WWWWWWwwWwwwwwww

NN
= W

2-22

Transaction (Octaword
Transaction (Octaword

Address

NBI
Decoding

2-43
2—49
2-51

2-53
2-55

2-56
2-58

2-60

=
o

3-15

INIT
.
.
.
. .
and Translation

3-19

3~-23

3-17

Local

Read/Write

Command/Address

Cycle

3-27

Local

Write

Cycle

3-29

Data

o«

Local Read Data Cycle
.+
¢«
¢
¢
o
«
o o
=
Basic Information Flow Between NMI and VAXBI
NMI to VAXBI Command/Address Transfer. .
NMI to VAXBI Write Data Transfer . . . .
VAXBI to NMI Return Read Data Transfer .
Aligned and Unaligned Quadword Read Data
Ordering «
«
v « « o o o
o
o
o o
o o o

3-16

Basic Information Flow Between VAXBI and
During DMA Read/Write Operations . . .
VAXBI to NMI Command/Address Transfer.

3-17

VAXBI

3-31
3-34
3-37

3-44

3-50

3-64

3-67

3-74

.
o

3-80

3-19

to NMI Write Data Transfer .
. .
NMI to VAXBI Return Read Data Transfer
INTR/IPINTR Operations . « «
« « o« o« «

3-20

FLIP

3-101

3-18

29/22

Diagnostic

Xiv

Data

Transfers

3-93

TABLES

Title
NBIA

Page

Registers

Control/Status
Descriptions

Bus

.
.

.
«

¢«

o
.

Status
Descriptions

¢«
v

¢«

o«

(FIPSDES)

Interrupt

NMI

Signals

Connecting

(SADR)

[

(BCICSR)

Bit

(FIPSCMD)

(UINTRCSR)

[]

NBIA

[

BCI

Signals.

NBI

Initialization

¢«

o«

.«

Signals

Signals.

Bit

Command

Control

Bit

(IPINTRSRC)

.
.
.
.
«
«
.
.
.
©
Register (WSTAT) Bit

Bit

(EINTRCSR)

(INTRDES)

(IPINTRMSK)

Bit

.
¢

(BICSR)

Descriptions

User

e
e
Bit

Bit

VAXBI

Bit

v
¢
v
v«
¢
v
4
v
Register (EADR)

IPINTR/STOP

BUS

Control/Status

Descriptions

Descriptions.

Reglster

Address

Write

Control

Address

Descriptions

Data

Destination

Source

Descriptions

Bit

Descriptions

Ending

Descriptions

Starting

Destination

IPINTR

Descriptions

DesCcriptions

v
.

INTR

IPINTR/STOP

Bit

(CSR1l)

Bit

Mask

(DTYPE)

Interrupt

IPINTR

Error

Force

(CSR0O)

Bit

BCI

RegisSterS.

Control/Status

Error

¢«
.

(BIIC)

Descriptions

VAXBI

I
=W N

Device

w wWw

Control/Status
NBIB

CPU

Read/Write

SUMMArY

DMA

Read/Write

SUMMAYY

©«

3-9
.

3-13

3-21
o

3-61

CHAPTER

INTRODUCTION

DOCUMENTATION.
DESCRIPTION . .

o«

.«

DESCRIPTION .
FUNCTIONAL DESCRIPTION
Console SubsSysStemM. o«

¢«

.
o

«
o«

o
o

o
«
o

.
o

o
o

Unit.

«
o

¢
¢

o«
<«

¢
s

o
o

«
o

o
s

¢
o

o
o

¢
o

o
o

¢
o

o
o

Logic

.
¢

1]
o

[
o

.
e

3
o

=
N

o~
Ial ol
MchJL
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System

Buses

flflQ"I

L]
N~

SOTTLWAre

v«

Hardware

COMPONENTS.

SOFTWARE

Program.

.«

Special Control Program Features
Multiple Command Streams . . . .
File Transfer Program. . « o« o s o«
Logical Block Server Program . . .

.
.

.
.
o
.
.

Real-Time Interface Driver . . . .
CONSOLE SUPPORT MICROCODE (CSM). . . .
Console Support Microcode Structure.,
CSM Data Transfers/Protocol. o« o e e

Xv1i

.«

~JA

o«

|
U

¢«

CONTROL

RN NN BN N

(NMI)

RO B

o
e

Interconnect

SYSTEM

Control

W N

L]
*
]

L[]

U W

CONSOLE

3
¢

VAX Bus Interconnect (VAXBI) . . .
Visibility Bus (VBus). . . . .« =
VAX Bus Interconnect and I/0O Adapters.
Power System Complex . . . « « + «
876 Power Controller . . . . « .+ .
NBox Port Conditioner. . « « .+ « =
Module Power Supplies. . . « « . .
Environmental Monitoring Module.
Battery Backup Unit. . . . . « . .

SYSTEM

i ol o
A.L
i a_‘x7 .

VAX 8800 Memory

GENERAL.,

¢
o«

—

W N

s
.

e
*

Memory Control

U
[
o

e
e

NN NN

Instruction BOX.
Execution BOX. «
+«
¢«
.
Cache BOX.
Clock Module .
Memory (MBOX).

[

AW wWwwwwwbdhNN
-

Processing

¢«

Central

WD NN

s et e sl el el e el el el
L) L] . LJ ° ® L] . L]
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L] ® *
L[]
[

S S
° [ ] L] e

ORGANIZATION.

PHYSICAL

R
> Ld [ ]
AN
e

[

[]

NNDNDNONDNDDRN

VNN
NN
DN

SCOPE

MANUAL

SYSTEM

CHAPTER

MANUAL

e e el e
|
AN W OW~JWLWN

INTRODUCTION AND SYSTEM OVERVIEW

e
|
el
e o

NN ANNAAONAATTAAAASO
U
W

SECTION

Mode

INTERACTION

Bits

¢«

State

Console

Logfile

Operation.

Display

Prompts

the

Logflle

SEQUENCING

Power

Fail

Powerdown.

Restart

OPERATION

INTRODUCTION

MICROCODE.

Characteristics.

.«

.
.

Operation.

¢«

o«

SEFUCLUTYE.

o«

Control.

Ul
W N

Interrupt

and

Condition

Code

Gateway

Processor

and

Control

Microtrap

Branch

(GWYC)

(UTRP)

.
Slices

&«

(CCBR)

(INPR).

v
v

o
v

o
e

«
v

o
W

.
W

MIiCrOLraps

v &«
(UBRS).
v
v
v
v

Micromatch

¢«

e«

Microbranch
Pipelining .
.

Stop

Match,

Trap

Match.

MEMORY

ADDRESSING

Virtual

AND

Addresses.

Layout

OPERATIONS.

¢t

e
e

Physical

Format

READ/WRITE

AdAresses

DWW

N =

Address

Translation.

+«

Cache

Table

Entry

Operation.

Translation
.

Page

Cache.
NMI

Buffer

Interface.

Xvii

N
e e

SYSTEM

.
.

Power

.
.

.
o

Remote

Language

.
o

Functionality.

Microcode

e
e
e
o
o
e
e
Logical Terminals/Logfile Integrity.
Saving the Logfile .
.
.
.
.
.
.
.
.

Microcode

During

Command

Displaying

Commands

Display

w N =

Display

Ll WWWWWWWwwwwwwwwww W wwww

Local

1!
R
I
T
Y
OCOWAOONAUTUTD WWWWWNN

N
—

Commands

Console
System

UE WNDNDDNDDNDNN
A

Validity

Executing

Warm

Console/Operator

S E DB WWWN
N

Saving
Console

State

— |

—
N

Program

Command

W0
N =

.
.

L]
[]

o
o

o
¢

NNNNdOOOONOOOO
AN
U Ul Ul

NN NDNDNDNDNDNDND NN

*
o

[]
®
»

POWER-UP/DOWN

[]

Mode

Console

[]

WWWWWWWWWWWNNNNNONNNMONNNMOMNMNNDNONDNDNDND
-

WWHWWWWWWLWWWWWWWWWWWWWwWwwWwwwwwwww

MODES.

Console

OPERATOR/CONSOLE

CHAPTER

OPERATIONAL

Read/Write Operations. .
Device Address Selection
Transaction Significant
Servicing.
Types

Interrupts.

SCB Pagination . .
Of fsetable Devices

3.4.3.3

VAXBI

3.4.3.4

SCB

Node

Format

Machine
Types

DIAGNOSTIC

4,2

4.3

DIAGNOSTICS.

Selftest

Console
Microdiagnostics
Commands

CSM

4.3.2.2

Status

Micromonitor

Error

Messages.

Diagnostics.

4.4.1.1

Module

Key

Test.

4.4.1.2

Module

Placement

4.4.2.1
4.4.2.2

4,4.3

4.5
4.5.1

Power Monitoring/Error Reporting
Default Mode Error Reporting
Operational Error Reporting.
Voltage Margining. . .
.
MAINTENANCE

Machine

AIDS

Check

St
1

4,4.2

Remote Diagnostics . . .
POWER/ENVIRONMENTAL SYSTEM
Module Placement Verification

Mode.

Information

4.4
4,4.1

and. Error

Macrodiagnostics
Customer Runnable
Auto-Test Mode
Menu

3-25

4.3.4.2
4.3.5

3-23

3~-24

4.3.2.1

4.3.4.1

AND MAINTENANCE

INTRODUCTION

4.3.4

Devices

Check Exception.
Exceptions. .

GENERAL.,

4,3.3

Connected

4,1

4,3.2.3

3-23

3-21

.
.

3.4.4.1

3-20
Format

3.4.4

Direct

3-20

3.4.3.2

.
.

3-20

3.4.3.1

3-20

3.4.3

4.3.2

3.4.2

4.3.1

Enable

Servicing the Interrupt.
Priority Levels.
System Control Block (SCB)

3.4.1.3

3-20

Interrupt

3-19

3-20

lvb»?hh:—b»&nh.h»b»brb

3.4.1.2

Bits

Logout

xviii

Stack

—
b
— =
(T
el
b WW
kOY o W W NN OO0 O OWHOANA

NMI

Address

EXCEPTIONS.

3.4.1
3.4.1.1

CHAPTER

AND

INTERRUPTS

3.3.6.1
3.4

3-17

3-19

3.3.5

3.3.6

4-16

FIGURES

Title
VAX

Page

8800

(Rear

System

View).

Cardcage

Module

Diagram of
¢

Simplified

Block

Diagram

Simplified

Block

Diagram of

Simplified

Block

Diagram

BOX:e

¢«

(Front

View).

¢«

1-6

System.

1-8

the
e

VAX

the
¢

Locations

&«

the

CPU

1-12

IBox

1-13
1-17

CPU

the
e

CPU
o

Execution
s

1-21

Module

1-22

1-24

1-26

Diagram

the

CBox

Simplified

Block

Diagram

the

Clock

Simplified

Block

Diagram

the

MBox

Simplified

Block

Diagram

the

VAX

8800

VAX

and

Adapter

Block

CompleX

System

Console

Local/Remote

~N oUW

&«

Wwwwwww

CoOmMPONENES

1-28

1-31

1-32

o«

1-34

T
T

Translation.

Software
s

Modes.

¢«

Character
«

Control

¢«

o«

Flow.

o«

3=7

¢«

o«

3-8

Layout.

o«

Configuration.

3-10

o«

3-12

o«

3-13

¢«

Configuration

Address

¢«

(PO

Space

Address

Translation.

Process

Space

Address

Translation.

(Pl

&«

Region)
.

o«

3-9

o«

&«

o«

Virtual-to-Physical
.

&«

o«

3-14

.
«

.
&

.
«

.
&

«
o

¢«
o

&«
«

«
o«

«
»

3-15
3-18

Significance

3-19

Format

324

3-11
3-12

NMI

Address

3-13

NBI

I/0

Bit

3-4

Virtual-to-Physical

CBox Functional Components
NMI Address Selection.
.
«
Adapter

2-8

2-14

Virtual-to-Physical

Process

2=2

Layout

Bit

Power

Space

Entry

Space

the

FOrmat

Table

and

Address

Page

Pipelining.

Address

Virtual

Enable

e«

Display

¢«

Space

Physical

Address

MAP

Interconnect
.

¢«

.«

Memory

Diagram

Operational

Simplified

Hardware
o

Bus

Adapters.

Virtual

System

VAX

Configuration).

Interconnect

8800

1-10

Block

Diagram

1-4

Console
4

Single

8800

Simplified

System

3-10

Block

Simplified

Layout

Simplified

NMI-to-VAXBI

SubsysStem.

(Maximum

Component

Diagram of

I/0

[

Block

Interconnect

Simplified

Major

SCB

Vector

Xix

Offset

N O
=

—

= so

Bottom=Up

TeSting.

o«

4-2

Module Keying Test Simplified Block Diagram.
Module Key Test Connections. . . .« « .+ .
Margin Enable and Margin Hi Lo Registers

4-11

Machine Check Logout Stack . .
CBox Error Reglster. . « +« o «
IBox Error Register. . . ¢« ¢« «
EBox Error Register. . . « « o
NMI Interrupt Control Register

.
o
o
o

4-17

NMI

Fault

NMI

Silo

Summary.

.
o
&
&

4-12

4-15

.
o
o
o

.
o«
o
o

.
o
o
o
.

4-19

o«

4-20

4-18
4-18

4-19

4-21

NMI Error Address Register
Cache ON Register. . « « «

.
«

.
o

.
&

4-21

Machine

Check

Status

4-22

Revision

1/2

RegiSterS

Data.

4-272
4-22

TABLES

Technical
Related

Description Manual

Documentation.

Organization
¢

o«

Power Supply Identification. . . . . . .
VAX 8800 Processor Functional Units/Data
o

o«

Clocks.

¢«

MCL Command OperationS . « « « « o « o
NMI Function Descriptions. . « « « « =«
VAXBI Function Descriptions. . .« « « «
Optional VAX Bus Interconnect Adapters
NBIA Registers . o ¢ ¢
o
o
o o o o o o
NBIB RegistersS . «
o+
o
o o o o
o o o o

o
&
=
.
o
&

NBOX

o«

Software

Sections

Console

Support

CSM

Component
Code

Microcode

Bit

Descripti
.

Entry

Points

Examples .
.
«
+
¢
o
Console Command Overview

+«

o«

Console

Prompts

Sequence

«
.

.
.

Module

Command

Power

Language

Supply

Turn-On

VAX 8800 System Microtraps .
. .
Page Table Entry Bit Description

Translation Buffer
Hardware Interrupt

«
.

.
.

Field Description . .
Priority Level Assignments.

System Control Block Page 0 (000--1FF)
Machine Check Exception Examples . . .

and

Hardware
Major

MOAUIES

System

W
|
NN

SO
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N
B
Ul W
Y

O Q0 =

=
el el
g

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VAX 8800 System Physical Characteristics
Cabinet Module Identification. . . . . .

Descriptions

M)
W L) W

e
el

Title

Microcode

Error

for
¢

Use
«

with

o
Addresses

&
.

EXAMPLES

No.

Title

4-1

Sample

Microdiagnostic

Display

4-2

Sample

Microdiagnostic

Error

Display

4-3

EMM Warning

MesSsSage.

SYSTEM

BUS

CHAPTER

MEMORY

INTERCONNECT

N
W

=
0
e

e
=
b
=

@
o
o

o
o
o
¢

o
o
o

NDDNDDNDDNMDNDNDDNDNDDNDDNDND

.3
4

(NMI)
o

o«

TIMING

¢«

READ/WRITE

TRANSACTIONS.

¢«

INTERLOCKED

OPERATIONS

NMI

SIGNALS

AND

NMI

ADDRESS

SPACE.

ARBITRATION.
.+

&+«

&«

o«

Levels.
« «
&« «

.
o«

.
o

NMI

Faults

ERKUKS

VAX BUS

NMI Interrupt Priority
Device InterruptS.
« +«
o«

[]

[

INTERCONNECT
.

(VAXBI)

FUNCTIONS.

VAXBI

SIGNALS

AND TIMING

VAXBI

ADDRESS

SPACE.

Memory

Address

.«

¢«

Space

.«

«
«

o«
o«

«
o«

«
o

o«
o

&
&

FORMAT

I/0 Address Space.
Address Selection.
VAXBI

«
.

TRANSACTION

Command/Address Cycle. « .
Embedded Arbitration Cycle

«
.

Data Cycles.
Bus Parity .

+
¢

o
¢

o«
o«

o
o

o«
o

o
o

TRANSACTIONS.

Write Data Cycles. . .
Read Data Cycles . . «
Nonexistent Addresses.

¢«
¢«
.

¢«
¢«
«

«
«
«

.
&
o

READ/WRITE

1
e 2
3

BASIC

1
2

INTRODUCTION

BASIC

.2
3

NMI

o
e

FUNCTIONS

INTERRUPTS

o«

BUS

CHAPTER

SUMMARY

INTRODUCTION
BASIC

000

~JONUTE
WN -

SECTION

Output

.
.«

.
.

¢«
¢

Xx1i

¢
¢«

Addresses

CSM

4-2

Diagnostic

TEMP

4-1

Stalls

o«

TRANSACTIONS

INVALIDATE

TRANSACTIONS.

INTERRUPT

OPERATION

BROADCAST

TRANSACTIONS

IDENT,
o

AND
2-28

2-34

.«

¢«

o«

CONTROL.

.
o

ARBITRATION
.

¢«

[]

Control.

2-39

Extending a Transaction.
Special Mode Functions .

.
.

«
.«

.
.

2-41

2-42

LaANSNA

Arbitration

¢«

Checking.

Check Error
Checking.
.

¢«

2-42

Detection
.
« «
«
¢«

.
«

.
.«

2—-43

o«

SIGNALS

¢«

VBUS

REGISTERS

.«

¢«

o«

CIRCUITRY.

Configuration.

Expanded

Configuration

VBUS

ADDRESS/DATA SUMMARY.

VBUS

CONSOLE

(NMI).,

COMMANDS.

CHANNEL

Minimum

e
0
s W
U

NMI

0 ~JO0

[

NMI

Address

[

NMI

Write

NMI

Read

NMI

Write

ol
el el
i

Memory

Basic

Interconnect

NMI

Timing
v

NMI

SignalS.

NMI

AddresSs

SpacCe€.

Address

BitS

o«

Selection.

Transaction.

¢«

Types.

Transaction

XXii

+«

o«

~~1 b

FUNCTIONS.

VvBUS

2-44

(VBUS)

VBUS

MODULE

2-41

WWwwwww

BUS

VISIBILITY

2-39

ERRORS

2-38

¢«

Mndeg
T e

Avhitrationn
A/ A e
(A
d N2

Title

2-36
2-38

FIGURES

[

2-31

—

Requests

AND

£ A4

INTRODUCTION

o«

BASIC

W wwowwwWw

Parity

TRANSACTIONS.

Transmit
Protocol

(INTR,

Transaction.

VAXBI

SO
OO
W N

2-29

Bus

2-24
2-26

.
.

BUS

2-24

Interrupt (INTR) Transactions. . .
Identify (IDENT) Transactions. . .
Interprocessor Interrupt (IPINTR)
STOP

CHAPTER

2-23

RetrieS.

Dl
W N
O

e
pd

[

el e

NMI

W IN

Transaction

NMI

Arbitrator

Detailed

NMI

BUSY

Fault

Signal

Bus

Types

Arbitration

Line

Operation

Arbitration
Timing

Timing.
.

Line

.
Timing

Timing.

Interconnect

(VAXBI)

¢«

Timing

.«

o«

Space.

Signals.

Basic

VAXBI

Address

Node

Required

U
O

O 00~

BIIC-Specific
VAXBI

Read/Write

Basic

VAXBI

Transaction

Format

VAXBI

Write

Transaction

(Octaword

O
=

Read

Device

VAXBI

Broadcast

VAXBI

—

N
N

Registers

VAXBI

(Octaword

VAXBI

Space.

VAXBI

Registers

Address

Transaction

Length).

(Octaword

(BDCST)

Invalidate

Bits.

Length)
Length)

Transaction

(INVAL)

Transaction

VAXBI

Interrupt

(INTR)

Transaction

VAXBI

Identify

(IDENT)

Transaction

VAXBI

Interprocessor

Interrupt

(IPINTR)

o«

Transaction

Lines.,

Transaction.
VAXBI

Bus

STOP

+«

CLK

Bus

VBus

Access

VBus

Channel

(Example).

Diagram.

(VBus)

Module).

Control

Request

State

VBus

Control

Reglster.

Reglster

Channel

and

Conflguratlon)
VBus

Arbitration

Visibility

(on

Arbitration

Arbitration
VAXBI

(Typical)

¢«

VAXBI

Read

MEMORY

VAX

NN
DD

NMI

Basic

CPU

Module

CPU

Module

.
W

(Minimum

(Expanded

TABLES

Title
Glossary

NMI

Signal

NMI Terms.
.
Descrlptlons

I/0

Registers

NMI

Interrupt

Priority

NMI

Errors

NBI
L]

and
.

Levels

Xx1i1i

e
e
e
Memory Controller
L]

*®

(IPLs)

=
N

VBus

RELATED DOCUMENTATION AND REFERFNCES

GENERAL.,

iae B el
i
«

R
e
.

(S
L
L[ ]

INTRODUCTION

L1
NN
N
=

Nd~Jooooouuiutunon
it
Ut
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CHAPTER

CONSOLE

SUBSYSTEM

—

(Excerpt)

{

Terms.

VBUS Signal Descriptions . . . . . . .
VBus Control Register Bit Descriptions

Signal

SECTION

Descriptions.

VAXBI

Glossary

VAXBI

~——

2-17

Console

Mode

2-20

Mux.

.«

2-20

Registers.

2-21

Control .
.
.
Interrupt Generation

.
.

2-22
2-23

Output

OO0 ~J

YU bW

O
—

2-16
2-17

Bus

Status

8800

Turn

EMM.

and
.

Console
Load

INTERACTION

2-24

.
«
.
System

2-24

Monitor
¢

Poweron.

.«

Run

Test

and

Load

RAMs

Console

Power

Initialize

2-23

and

2-19

¢«

Sequenced

.
.

Initialization

~J OO

MCA)

Console

*®

2-16
2-16

Mode

Control

2-24

2=-27

Power-Up

Software

Application.

Hardware.

Checkout.
and

Power/Reset

2-28
2-32

2-36

2-44

DRAMs.,

2-46

Control

2-63

Sequencer.

2-64

Control

Registers.

Transfers
ClocK.

Interval

Clock

¢«

AND

¢«

TIMING
«

¢«

o«

2-75

¢«

o
&

o
o

@
&

2-78

Bus

o
¢«

2-79

DESCRIPTION
.

CONSOLE

SEQUENCER
Strobe

¢«

INTERVAL

MCA

Console

Write

Sequencer.

Control

Store

Load

Sequencer
.

CLOCK

(CSEQ)

W N~

Acknowledge

¢«

.«

Sequencer

¢«

CONSOLE/VAX 8800 REGISTER SUMMARY.
Console Registers (Refer to Figure
CONSOLE

2-73
2~73

8800

GENERAL.,

VAX

¢«

Console

o«

TERMINAL

Read

2-68
2-70

WO OO0

DETAILED

CLOCKS

TimeoutsS

Visibility

CPU

Registers

CABLING.

XXV

(Refer
o«

o«

to
o

3 7)

Figure

3- 8)

CPU

I WWWwwwww
|
!
I
T
=

o
o
e
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8800

One-MHz

Data

|
NN

CPU

CONSOLE/VAX

8800

Console

wwww

o
o

WNNN

.
L]

.
.

VAX

=W N

L
L]

.
L]

(CSEQ

Program

Decode

Sequencer

*
[)

o
o

Address

S
.

NN DNDONNNDNDNDNDDDDDDNDND

=R WWwWwWwwwwwwwwww
Y=
S YS

Console

CONSOLE/VAX

.
.
.
.
.
Synchronize

Console

Power

and

Visibility

g
o

b wwwwwidoH+-

Translate

Data

CHAPTER
WWwwwwwwwwww

INTERFACE.

Buffer

Terminal

O R

s
e
o
e

(2RO 201 RO

CONSOLE

—

Diagram of

Modes

Operation

.«

¢«

o«

1-5

Power—-Up

SeqUEeNCe.

1-11

Initialize

the

Console
1-3

1-13

Restart/Boot/Halt. .
Power—-rall Sequence.

¢
.

v
«

o
«

¢«
o

¢
¢

o
o

«
o

o
o

o
s

o
o

1-18

Powerdown

1-22

EMM/Console

[

Format.

.«

¢«

Format.

Register Format. . .
Register . . o
o
o
o
Register . .
v
o
o
o
ECPI Command Register. .
.
.
+ «
Serial Line Port Data and Status

o « « o« o
o o o
o o
o o o o
o
o « o« s o
Registers

o
o
o

o
o
o
o
.

RXDB,

o«

Control RegisSterS. . o v o« o« o
o o
VBus Control and Access Registers.

o
.

2-22

System

o«

PPI

Port

PPI Control
ECPI Mode 1
ECPI Mode 2

TXDB,

and

DBCS

Power-0n

Environmental
v

Sequence

Monitoring
4

Module
o

Ports

Interconnect

Through

Ports B and
Interface Data Path

Unbuffered

Data

C.
.
. .«
Loopback
.

¢«

o«

«
« «
Test

o«

Buffered
« « « .« .
. . . . .
. . . . .

Hardware

Initialization

Test

Checkout

Events

2-28

2-30
2-32

Testing

Interface Data Path Loopback Test of
Data Through RXDB and TXDB . . . . «
Console Sequencer Enable Logic . . .
Control Register Initialization. . .
and

2-26

2=27

Console

Through

.
.
.

Loopback

.
.
.

o«

and

2—-25

Reset
o

Serial Line Port Data Transfer Registers .
Load/Run Console Power-Up Software Events.
Sequenced Power Application Events . . . .
Console Interconnect Loopback Testing
A,

Events.,

Console

roto

Power-0On

bty

tuts

SEQUENCE

Port

S g e

WNOWO

PPI

AN NP S

RFAarmat

[

WWN

£x

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Diagram

[

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Block

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]

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Console

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L

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S
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prnt

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to
to

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bty
teto

Page

Subsystem.

paet

gt pt pd

P—

FIGURES

Title

2-39

2-40
2—-41

2-42

+«

2-44

2-49

VBUs

Parity

Blts

¢«

DRAM

AdAressS

2-51
2-53

MNI

Control

Store

RAM

Simplified

RAM/DRAM

Address.
Events.

Console/Interface
Write

SEeQUENCE

Diagram

2-56
2-57

Signals

.«

2-64

o«

2-65

o«

Out)

Timing
v

Block

Read

Sequence

(SetuD).

Read

Sequence

(Data

XXvi1

2-66
2-67

Simplified

Diagram

Control

Simplified

Diagram of
Diagram of

Control

Interface-to-VAX

Simplified
Data

Transfer

Control

Transfer

VAX

O
Data

Interface.
1

MHz

Clock

[

X0 ~JO
O

Generation

2=72

¢«

2-74

Clock

Registers

Clock

Simplified

CPU

Status

Timeout

and

VBus

Control/Data

VBus

Logic

TRIC

MCA

BlocKk

TRIC

MCA

Bit

2-75

2-77

2-78

(CST).

2-78

Diagram.

Block

Diagram

Layout.

Configuration

+«

Signals.

Simplified

Block

Timeout

¢«

o«

2=-79

Diagram.

2-80

3=2

o«

3-3

TRIC

MCA

Body

Drawing.:

o«

CSEQ

MCA

Block

Diagram

o«

CSEQ

o«

MCA

CSEQ

MCA

Body

U W

wwwwwwwww

CPU-to-Console

Interval

Simplified

e|
8800

Interval

Clock

Console
VAX

Layout.

&«

o«

3-11

Drawing.

o«

3-12

Registers.

8800

Console

CPU

3-4
3-10

¢«

3=17

Registers

¢«

&«

3=-24

Diagram.

3-29

Subsystem

Cabling

TABLES

Title

Page

PPI

Port

Bit

Description

¢«

o«

PPI

Port

bit

Description

¢«

&«

PPI

Control

Bit

Description

ECPI

Mode

Bit

Description

ECPI

2-1

Mode

Bit

Description

ECPI

2-1

Command

Bit

Description.

2-1

and

Status

2=15

Serial

Bit

Line

Port

Description.

Data

Serial

Data

Bit

Line Port
Description.

Key

Initialization

ICCS

Bit

¢«

MCA

CSEQ

MCA

2-29

2-62

2-76

¢«

o«

Descriptions

v«

¢«

Assignments

Signal

CSEQ

AssignmentsS

Signal

MCA

Registers
v

MCA

Signal/Functions.

TRIC

Cable

Transfer

Configuration

TRIC

Console

Registers

Descriptions

List

XXvii

¢«

3-5
3-6

3-13

3-14

¢«

&«

o«

3-28

SECTION

POWER SYSTEM

CHAPTER

GENERAL

COMPLEX

¢«

o«

876A

Power

Controller.

1.2.2

NBox

Power

Converter

1.2.3

Modular Power System (MPS) . . .
Environmental Monitoring Module.
Cooling System . « « & o o o o o
Battery Backup Unit H7231-M. . .

1.2.4
1.2.5
l1.2.6

CONFIGURATION

MECHANTCAT,

876A Power Controller. .
NBox Port Conditioner. .
MPS Modules (Regulators)

. .
. .
and

. .
.
Cage.

1.3.4

Battery

1.3.5

Air

1.3.1

1.3.2

1.3.3

System.

POWER

Unit.
.

DISTRIBUTION

1.4.1

POWEE

1.4.2

POWEYr

¢«

1.4.3

Controls

Breakers.

and

1.4.3.1

Controls

1.4.3.2

Circuit

Breakers

.«

SPECIFICATIONS.

.«

Requirements.

SOUrCeS

INDICATORS.

Electrical
AC

FAULT

Power

AND

STATUS

l1.6.1

876A

Power

Controller.

1.6.2

NBOX

1.6.2.2
1.6.3
1.6.4

1.6.5

CHAPTER

H7170

Built-In Test Equipment.
ILM Built-In Test Equipment. .
Modular Power Supply Regulators,
Environmental Monitoring Module,
System Console Device. . . . . .

FUNCTIONAL

DESCRIPTION

2.1

INTRODUCTION

2.2

POWER

BLOCK

2.3

SIMPLIFIED

SYSTEM

DIAGRAM

OPERATION

¢«

o«

2.3.1

876A

Power

Controller.

2.3.2

NBOX

Converter.

2.3.2.1
2.3.2.2

2.3.2.3
2.3.2.4
2.3.3
2.3.4

2.3.4.1
2.3.5

H7170

Power

Control Start-up Power Module (CSP)
Interface Logic Module (ILM) .
New Box Translator Module (NBT).
Modular Power System (MPS)
., .
Battery Backup Unit (BBU Model H723l
-M).
e

BBU

Control.

Environmental

¢«

Monitoring
XXviii

.«

Module

&
(E'Viu; .

WWwWHE

1.6.2.1

o«

1.6

UTUTUE

1.5.1.1

POWER

1.5.1

NN DN
[

1.5

1.4

Backup

Flow

oo N
—

1.3

1.2.1

e
|

=
!

COMPONENTS.

SYSTEM

INTRODUCTION

1.2

|
=

1.1

=00~y

DESCRIPTION

System

Monitoring.

.«

¢«

Control.

¢«

.
.

Monitoring

Regulator
BBU

Control.

Air

Flow

AC/DC

v«

.«

&«

Signals

¢«

.
.

Regulator

Overtemp.
«

Circuit

Breakers

summary

Power-Up

POWER-UP

POWER-DOWN

(FIGURE

2-7)

POWERUP

FROM

BBU

«v

Sequence

2- 5)

¢«

(FIGURE

WITH

BBU

2-6).

FLOWCHART

(FIGURE

2- 8)

Modules

Module

THE

VAX

SYSTEM

8800

POWER

ASSEMBLY.

¢«

=
N

)
NBT

o
o

L
N

H7186
H7186

Main

L J

|—
-

W N

o«

Requlator.

¢«

Board

o«

.
.

-2.0-Volt

Regulator.

.«

-5.2-Volt

.«

Reqgulator.

¢«

H7180

Side

Panel

H7180

Main

BIP

Board.

Functional

and

Regulator.

Regulator

Buses

H7180

BITE

o«

&«

o«

Description

Indicators.

o«

Backplanes

¢«

o«

300-VAcC BUSES.
&
&
4
v
¢
o«
o
o
Environmental Monitoring Module.
8085A Microprocessor SysStem.
.

MPS

-—-

H7187

H7189

MPS.,

System

+5.0-Volt

Panel

MPS

P OCOOOOO-

Power

Side

H7189

Backplane.

Electric

Key

Monitor

Circuits

Regulator

Control

Regulator

On/Off

Control

Circuits.,

Regulator

Margin

Control

Circuits.

4«

Status

AC/DC
(NS

PR
OO
IO
U
WWwWWWNNDN

DIAGRAM

Modular

o
&
o

SR S T -

i
@
e

[]

SN ST SN S

SN N

[]

TS S

CONVERTER

CONTROLLER.

Registers

Total-Off

CirCUitS.

Control

and

XX1X

Indicator

Circuits

POWER

St = St Y

876A

FLOWCHART

NBOX

*®

DESCRIPTION

INTRODUCTION

el R

FLOWCHART

BLOCK

NBox

INTERRUPT

WWWWWWwWWwWWwwwwWwwwwwwWwWwiwwwwwwwwwwwwwww

Cabinet

FLOWCHART

POWER-DOWN/POWER

DETAILED

CPU

Volts)

WWwWwWwWwwwwww

CONSOLE

and

(Thermistor

SEQUENCES.

SYSTEM

Status.

Temperature
POWER

Key

o=
OO 00O

Power

Temperature

3-53

3-55

Voltage TestS. « o « o
Unit (BBU) Control.
Backup Unit (H7231-M).
.
«
«

«
.

+
.

3-58

&
.
.

Voltage

Sensing

Measuring

Circuits

Circuit.

EMM/Console
Battery
Battery

Air

Flow

Backup

Sensing

Circuit

¢«

3-58

3-59
3-63
3-65

FIGURES

VAX

8800

System

VAX

8800

Power

System

Block

Diagram

(60

Hz).

VAX

8800

Power

System

Block

Diagram

(50

Hz).

VAX

8800

CPU

Cabinet

Front

8800

CPU

Cabinet

Rear

Power

VAX

8800

Section

System

EMM

Front-Panel

VAX

8800

MPS

Backplane

o«

NBox

Battery

876A

Power

Front-Panel

WO N

for

Power

Receptacles

Diagram

Modular

Indicators

Panel.

o
.

Regulators.
.+«

Block

Diagram.

View).

(Rear

¢«

Flowchart.

Block

System

Power-Down

Dlagram

Flowchart.

Powerdown/Power

Interrupt

BBU

from

Functional

Power-Up

Block

with

Operation

BBU

Flowchart

Flowchart.

Diagram

¢«

Panels

o«

Diagram.

876A

Front

and

876A

Power

Controller

Rear

Block
.

¢«

o«

Board

Interconnect

Signals

NBT

Board

Signals

¢«

Regulator

Configuration.

.«

MPS

H7186

Block

Diagram.

H7180

Block

Diagram.

«.

o«

Block

Diagram.

o«

Indicators.
of

Backplane.

MPS

Backplane

¢«

EMM

Block

Diagram.

o«

Circuit.

o«

Voltage

Margining

XXX

MPS

Organlzation

.
.
the

H7189
BITE

et b b et el b
2
YU
LN
O

ILM

O 00

System

Subsystem

System

NBox

Location

Power

Configuration

Diagram.

System

Front

System

Backup

Powerup

Indicators.

the

Functional

Power

OY U

View)

l
|
oy
Ul

View.
View

Circuit

Controller

Indicators

EMM

Block

Power

= O
= O

Showing

—
N

T
T

[

NN DN

View

(Front

876A

Block

Layout

VAX

Diagram.

WWWWWWwwwwwwwwwww

Physical

ol
L W O
~J N O O

T
el el

U
W N

Title

3-17

AC/DC

Timing

3-18

AC/DC

Circuit

Diagram.
.

o«

3-19

Temperature

3-20

Voltage

Measuring

Circuit.

Measuring

Technique.

Voltage
BBU

Block

Circuit.,

Diagram.

3-57

3-62

3-23

Air

Flow

Sensing

3-24

Circuit

Air

Flow

Path.,

3-64

3-66

2
o

3-21
3-22

Sensing

Title

R
gy S
=

Page

Power

System

NBox

Modules

876A
VAX

Power
8800

H7170

|
= w o+

Tl el o

|
NOoOY
D W N

TABLES

Components.,

Distribution.,

Breakers.

Circuit

Status

Indicators.

MPS

Regulator

Indicators

EMM

Magnetic

876A

Power

Modules

Status

Indicator

Distribution.

Using

CSP

Codes

Voltage

System

Circuit

Breakers.

876A AC

Power

Distribution

B WK
O

Voltages.

WWwWwwwwbwwwwwwww
1
|
I
l
bt b b b
= S 00 ~] OY U
W N

Bias

.
.

Voltages

.«

¢«

o«

8800

Regulators.

NBox

Modules

CSP

VAX

MPS

H7186

Side-Panel

Components

H7186

Main

Board

Circuits

H7180

Side

Panel

Components

H7180

Main

PCB

Circuits

H7189

Module

H7189

OUtputS.

H7189

Module

H7189

Module

MPS

Functions

Regulator

300-V

3-15

Regulators

Buses,

Battery

SECTION

CLOCK

CHAPTER

INTRODUCTION

and

Interconnects.

and

Interconnects.

L] [ ] L ] L] [ ]
L] L] L
® L]
Circuits and Interconnects.
Circuits

Connectors

Power

Backup

and

and
.

Sources,

Interface

Interconnects
.

and

Loads.

Signals

MODULE

BASIC

OPERATION.,

BASIC

COMPONENTS

AND

¢«

TIMING

CLOCK

CONTROL

CLOCK

STALLS

CLOCK

STATUS

(BY

CONSOLE)

CHAPTER

>
L]

4.
Oy Ul b

2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.2
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2.4.3

FUNCTIONAL

DESCRIPTION

DETAILED BLOCK DIAGRAM . . &« v « o« o o o s o o
0sCillator v o v v v ¢ o o o o s 4 0 e e e e
Phase GeneratOr. .« « o o « & « s o o « s o s
Clock Control LOGiC.e o« v o o o o o o o o o o
Clock Distribution CircuitS. « « o o« ¢ o o o
CLOCK GENERATOR INITIALIZATION . v v o « o o o
SYSTEM CLOCK PERIOD CONTROL. . ¢« ¢ « ¢ ¢ o o o
Phase-Locked Loop Operation. . . . « + + =
Changing Clock Period. . . « « ¢« « ¢« o o o« «
SYSTEM CLOCK START/STOP/BURST CONTROL. . . . .
Starting the ClocksS. « + « v ¢ « &« o o & o &«
Stopping the Clocks Unconditionally. . . . .
Stopping the Clocks on Micromatch/Scope Sync
Generation « o o o ¢ 4 4 s s e e s e e e e .

o
e
o
o
o«
o
«

Single-Stepping the Clocks . . .
Single-Stepping the B CLK. . .
SLOW CLOCK GENERATION AND CONTROL
CLOCK CONSOLE COMMANDS . & ¢ o« o o

Bursting the Clocks.

.
.
o
.

o
s
o
o
«
o
o
.

2-1
2-1
2=2
2=2
22
2=7
2-8
2-8
2-11
2—-12
2-13
2-13
2—-16

o«

2-17

. .
e+
o o
o o

.
+
o
o

.
o
e
o

.
+
o
o

.
&
e
o

.
o
.
=

2-17
2-18
2-19
2-20

FIGURES

Page

No.

Title

1-1

1-2

Clock Generator (and Console
On Clock ModU]—e * L4 L] » L] L *
System Clock Timing Diagram.

1-4
1-5
1-6

Burst Count Register . . . « ¢
Clock Period RegiSter. « « « «
Clock/Timeout Status Register.

Interface)
L ] L J Ll L4 LJ *
. . « « « o«

L]
o«

L]
«

L
o

LJ
o

®
o

]-—2
1-4

o
o
o«

«
o
«

o
o
«

o«
o«
o

o«
«

1-9
1-9
1-10

2-1
2-2
2-3

e«
Clock Generator (Detailed Block Diagram)
Simplified Clock Frequency Control Clrcultry e
Simplified Clock Start/Stop/Burst Control

e
o«

e
o

2-3
2-9

2—4
2-5
2—-6
2-7

Start/Stop/Burst Control Timing Diagram. .
Micromatch and Scope Sync Timing Diagram .
Single-Stepping B CLK Timing Diagram . . .
Slow Clock Timing Diagram. . . « « o« « o« o«

.
.
.
o«

.
.
.
«

LOGIC.

o«

XXX11i

¢
«
«

¢
o
«

«
o
«

o
s
«

o
o
¢«

.
.
.
«

2-14

2-15
2-16
2-18
2-19

TABLES

Title
System

Clock

Clocks.

Control

Clock/Timeout
Descriptions

¢«

Status
.

Bit

¢«
¢
¢
¢
¢
o
.
Descriptions.

¢«

Bit

Clock

Generator

Inputs

Clock

Generator

Outputs.

.«

Clock

Console

Commands

Xxxxiii

¢«

the

Control.

LOgiC.

¢«

Special Address Encoder.
Microsequencer Logic . . .

.
.+

.
.

Control

Decoder

RAMS

Store.

¢«

CPU

¢«

e B e

.
.
&

Logic

Flags.

—

[

Generator

i
i

Logic

[

N
N~
w

L]
o

State

Control Logic.
Functions. . .

.
.

.
«

.
.«

.
.

1-11

1-12

Cons Bidi Data BusS .
IBOX RESIDENT INTERNAL

« « « « o o
PRIVILEGED REGISTERS

1-12

(IPRS)

1-13

IPRS.

.«

Address

Gateway
Primary
BUSES

Data

VAX

BiftSe

Interrupt and Processor Register
Interrupt LogiC. +« « + « + o
Processor Register Logic . . .

PSL CC

Data Consumed

Computing Amount of

Read/Write

el el el

.«

N -

Manager

File

WD
-

the

Reading

o
1

Writing

o B e

.
.

.
L]
.

Condition Code and Macrobranch

®
L]
.

L]
L]
.

o
o

HEEYOXXXINI~NOU
bR
WWwWwNNDdDND -

.
.

w N

ELEMENTS

Decoder

ST
L

Physical Implementation.
Instruction Buffer (IB).

(G2 RNO2NN0 s B0 RO 2NN ) BRO 2 QY -~

—t

Cache

gt =

IBOX

e b
e

L]
.

@
s
e
&
&
&
¢

ot ot et et e

e
s

R
Tl
el o N i el

Dual-Processor Configuration
LOGIC

e e b

e b

e ped bt bl e

[]

OVERVIEW

[
|
el el e

INTRODUCTION

CHAPTER

(IBOX)

U NN - O OO COVWYWYWwWXOXIOOIJOONONUTU

INSTRUCTION BOX

B W WWWNNNMNODNNMNNNNNNNDDNNDNNODNNDNDNODNDNDNDND
N -

SECTION

¢«

Bus

Bus.

[]

o«

Architecture

1-12

VAX 8800-Specific IPRs . . . . .
TR L.
NMI Interrupt Control Register (N
Interrupt Other Processor Register (I NOP)
IBOX MICROCODE VISIBLE ONLY REGISTERS.
Clear Interrupt Other Processor (CIOP)
IBox Error Register (IBER) . . .
IBER

Usage

IBER

Bits

IBER Bits
Clear Error

1-11

1-13

1-14
i-14
1-15

1-16
1-16
1-16

1-16

=«

<7:0>.

¢«

1-17

<11:08>,
Register

XXXiv

.
.
(CER)

1-17

1-19

CHAPTER

MICROCODE

2.1

CHAPTER

2.2

VAX

2.2.1

OVERVIEW AND

SCOPE.

8800

MAIN

Microcode

StrucCture

Microcode

File

Assembly

Other

Loadable

2.2.5.2

MICROCODE

Pipelined

2.3.2.1

VAX

8800

o«

2-1

.«

2-1

o«

2-1

2=2

Files.

o«

2-3

o«

2=3

Convention.

&«

2-3

¢«

o«

2-3

2=11

DEFIN. MIC

211

2-15

2=20
2-20

Versus

o
«

¢«

Files

File
File

MACRO.MIC

Documentation.
CONCEPTS.

¢«

Nonpipelined

Machines

o«

2=22

CHARACTERISTICS.
Cycle.
.
.
¢
v
¢
v
¢
¢

¢«
o

¢
o

o
o

o
o«

o
o

o«
o

2-23
223

o«

2-23

Clock

Hardware

DeSigN.

2.4.3

Relationship

Between

Microcycles

Functions.

IBOX

and

CPU

¢«

+«

o«

2=25

.«

2=25

StateS.

Time

Overlapping

2.4.5.2

CHAPTER

Definition

Time

Cycle.

2.4.5.1

2.4.6

2-20

CPU

Canonical

2-13

CPU

2.4.5

FaAactorsS.

2.4.2

Decode

2.4.1

@«

PIPELINE

2.4.4

2=1

&«

Rationale

Performance

2.4

PIPELINING

2.3.2

Pipelining

Definition

2.3.1

Macrodefinition

2.3

Definition

Microcode

o
+

Functionality.

2.2.6

Naming

Field

o«

Field

o«

Field

Microcode

OVERVIEW
.

Binary

FOrmat

2.2.4.2

2.2.5

CONCEPTS

Allocation.

2.2.4.1

2.2.5.1

and

Microcode

Microword

STORE

Size

2.2.3

2.2.4

CONTROL

2.2.2

2.2.3.1

PIPELINE

State

3.1

CHAPTER

SCOPE.

3.2

CONTROL

STORE

o«

2=27

2=-27

¢«

2=-27

2-29

Canonical

Time

States.

.«

¢«

Events.

FUNCTIONAL

State

¢«

Time

DESCRIPTION

o«

LOGIC.

o«

3-1
3=2

RAM

Segments

¢«

o«

3-2

3.2.1

Control

Store

3.2.2

Control

Store

RAM

Addressing

3-5

3.2.3

Control

Store

RAM

Data

3-5

3.2.4

3-6

Microaddress.

&«

3-6

3.2.4.1
3.2.4.2
3.3
3.3.1

the

Control

Load

Control

Write

Data

Microbranch

3.3.1.2

Microtrap

3.3.1.3

MICrostack

Normal

3.3.3

3.3.4

Microbranching

3.3.4.2
3.3.5

Address

3-7

o«

3-9

Hardware.

o«

379

MCAS.

3-9

(UBRS)

¢«

3-9

¢«

&«

3-9

Flow.

o«

3-11

Microaddress

3-11

Supplied
.

+¢

MCA

Microcode

Decoder

(UTRP)
o

RAMs

Slice

3.3.2

3.3.4.1

Selected
4

Microsequencer

3.3.1.1

Store

MICROSEQUENCING.

Latches

¢«

3-11

Microbranch

Conditions

¢«

3-13

Microbranch

Latency

¢«

o«

3-19

Returns,

3-21

Microsubroutine

Calls

3.3.5.1

Normal

3.3.5.2

Microsubroutine

Microstack

.
and

Operation.

Calls.

XXXV

3-21

o«

3=21

[

w
N

N+~

w
N

N
W

Full

L]
*

Ul
WD

.
.

JdAHNU
O
W N
(@)

Oy
0

3-23

3-25

Flush.

IB Flush Logic . . «
Partial IB Flush . .
I-Stream Prefetching .
General Description.
Refilling Cache. . .

«
.
.

3-30
3-30
3-32
3-32

3-32

3-38

3-34

.
.
.
.
.

Control

Cache Monitor Logic.
IB Full Logic. . . «

.
.«

.
.

3-43

the

Write

Load Example.
The IB . .

.
.

3-39

3-39
3-39
3-40
3-40

3-4

3-43
3-45

3-45

Read

Ports.

IB
IB

Data
Data

Aligner. . . . .
Formatter and Da

3-51

Example.

Pipeline

Timing.
.

3-46
3-60

3-66

IB Manager Operations. .
IB Read Address Logic.
Opcode Watcher Logic .
Specifier Size Logic

.
.
.

3-73

Read

3-73
3-76
3-78

Checking TEMPINC

<2:0> Validity.

Decoder

Stall.

Modifying

the

P01nter

nnnnflo

Pnfry

Point

Microaddresses.

Spe01al Microaddresses .
IBST MCA Signals Related
«
« o o
o
RAM (DRAM)

o
.

Condition Code and Macro Branch

XXXVi

3-93

3-96
3-104

3-121

3-128
3-128

3-129
3-129

3-129

Instruction Basics.
L

3-91
3-93

3-118

Branch Instruction Classes
Unconditional Branches
3
1
4+
Ql
Branch
Conditional
Short
Long Conditional Branches.

3-85

Instruction

o
.

3-82

3-111

Decoder
Optimized Instructions . .
Simple Move Instructions
Simple Branch Instructions
INSTRUCTIONS

3-81
3-82

IB Read Address Logic Control Slgnals
Computing Number of IB Longwords Consumed.
Instruction Decoder Operation.
Pipeline Timing Considerations
Operand Specifier Entry Point Addresses.

~l ~d

e
L]

N
W

o«

Branch

3-23

Returns.
«

MACROBRANCH

Reading

.
.
.
o
e
L

L]
L]

SSoMNoNo oUW
WWWwWwNNNN -

o«

S
St S
Y

[]

S
N

o
e

S
Y
Y
S
N
S
S
s
o
Y
e
¢
*

o
e

GANG) B U 2 B0 BNV 2 Y

W wwwwwwwwww

Microtrap Servicing. .
Disabling Microtraps .
Console Supplied Microaddresses.
MACROINSTRUCTION DECODING. .
Initializing the IB (IB Flush)

Decoding

(G2 RGN

3-130

n
-

o
e
L]

VR B

WWWwWWWwwWwWwwWwwWwwWwwWwwwwUWwwwWwwWwwWwWwwWwwwwwwwwwwwwwwww

Microsubroutine
Microtraps

3-135
i

3-141

Logic.

3-147

w N

and

N =

.
o

3-150

¢«

o«

3-150

3-152

¢«

3-153

Interrupt

Requests

¢«

3-153

Interrupt

Servicing.

¢«

o«

3-153

CONTROL.

¢«

&«

o«

3-158

RAMs

3-158

3-160

GATEWAY

Loading
Data

Control
the

Breakpoint
Console

Store

and

Decoder

Micromachine.

Transfer

Registers.

RLOG

Starting

ADDRESSING.

RNUM2

MDNUM

CONSOLE

oo ol o oo e U BEN BEN Bfe ) e A Ne ) W0

RNUM1

INTERRUPTS

o oo

WWwwwwwwwwwwww

SPECIAL

with

Console

Parity

Resident

IPRs

3-160

¢«

3-160

Check.

3-161

Microtrap

Data

FIGURES

Title
IBox

Page
Block

Interrupt

Bit

MAPe

Interrupt

Bit

Map.

Other

Error

¢«

(NICTRL)

Processor

(INOP)

o«

1-14

Format

APORT

Field.

4«

1-15

Bit

Map

1-18

State

Basic

CPU

TiMING

Microcycles/CPU

Decode

8800

Control

o«

2=-11

CPU

2-21

4«

Diagram

Pipelined

2=24

Functions.

¢«

o«

2-26

INEXT

2-21

o«

2-28

¢«

o«

2-28

Diagram

2-30

Diagram

3-3

3=7

Time

State

Simplified

RAM

e«

o«

Addre551ng

3-12

Selection.

3-14

¢«
¢«

¢«
¢

o«
v

o
«

«
o«

«
«

o«
o

3-20
3=-22

Latency.
Operation

.
.

«
.

Microtrap

Servicing.

Microtrap

Latency

=W
N pod

Condition

Console

Supplied

¢
«

¢
+«

Logic

3-8

3-10

¢«
v

¢«
&

o«

3-26

327

Microaddress.

Buffer

Logic

Block

Micromatch

Path.

Load

Field

for

Microstack

Instruction

¢«

2-4

Logic

Store

States.

Microbranch

Normal

Slices

Microbranch

Bit

Microsequencer

¢«

Microaddress
Control

Pipeline
Store

Cycle.

Time

=000
IO Uk W

N
T
[

VAX

Canonical

Definiton

Time

1=3

Field

Microword

Bit

N -

(IBER)

Basic Time State Diagram - Nonpipelined CPU.

Sample

Basic

Microword
I

NDNDNDN

Control

W oo -JOoy Ul > W

IBox

WwWwwwwwwwwwww

Diagram

NMI

¢«

3-31

¢«

o«

3-33

Flush

LogicC

&«

¢«

o«

3-35

Load

LOGIC.

¢«

o«

3-41

XXXVii

I-Stream

Data

Entering

Memory

Unit

Read

Port

Example

Read

Port

Example

the

3-44

MOVL

Example

3-47

Part

3-48

Part

3-49

Contents

IB.

for

Data

Aligner

MUXE€S.

Data

Aligner

Output

Example

Part

Data

Aligner

Output

Example

Part

MUuX

SOUYXCES

Data

Formatter

Read

Example.

PCNC

MCA

Block

Simplified

Instruction

Operand
Opcode

.«

and
.

Data
.«

Diagram

Read

Decode

Specifier
Entry

Opcode

o«

3-51

3-54

3-55

3-57

Scrambler

Logi

3-61

3-69

o«

3-74

Address

Logic

3-83

Logic

¢«

3-96

Entry

Address

Format

3-94

Address

Format.

.«

3-104

Special

Microaddress

Format.

3-111

Special

Address

LOgiC.

Decoder

RAM

Read

Format.

3-121

Decoder

RAM

Output

3-123

Instruction

3-131

Encoder
Address

Signals

Pipeline

State

for

BRB

Pipeline

State

for

Successful

Instruction.

Pipeline

Instruction.

Condition
File

Interrupt

for

Successful

Code

Address

Gateway

State

¢«

o«

and

Macro

Branch

Slice

MCAS.

Logic

Control

3-112

BEQL
o«

3-140

AOBLEQ
«

Logic.
o«

3-145

3-148

3-151

Simplified

Block

Diagram

3-155

LogiC.

¢«

o«

3-159

o«

TABLES

Title

TRA v
A

RIS N

Features

Dno%rqnn‘t
AN

NICTRL

IDbRsg

INOP

IBER

Bit
8800

¢«

o«

[

Descriptions

Bit

Description.

Files

U WM+

¢«

Sample

Cache

VAX

Sample

CREG/IREG

Sample

Microbranch

Sample

Miscellaneous

Pipelined/Nonpipelined

¢«

o«

Definitions.

Macroexpression

ClassSeS.

.
o

Transfer

Macros.

Microword

Pipeline

Microcode

W -]

Descriptions.

[

—

Microcode

Field

Time

Command

Macros.

MacroS.

o
&

Macros.

o«

Macros.

CPU

States/CPU

XXXviii

.
o

Comparisons

Events.

W W wwwwwww
|
O 03U
& W+

Control
Next

Store

RAM

Segment

Microaddress

IBRTYPE/IBRMASK

Functionality.

Sources.

Microword

Field

Microtrap
Machine
IB
IB

Read

MCA

State

Data

Format

Data

Format

Execute

Code

IMISC

Field

Hardware
Interrupt

Selection.

Data

Scrambler

Type.

i
a

Correlation.

Bit

v
Blt

Address

o«
+
Decode

Signal
BRB

Conditions.
e

Symbolic

Descriptions.

.
During

Serviced
i

Type

Address

Entry

IB
e

Descriptions

Recipes

Instruction

Event

Timing

Settings

for

Macrobranch

Settings

for

PSL

Condition

Code

Instructlon.

Control.

.
.

for

AOBLEQ

Settings

Interrupt
ID

CTL.BRB.MEM

for

Field

Code

IMISC

Source.

Execute

Recipes

PCNC

Output

Field

and

Entry

RAM

IMISC

Decoder

Microword

Address

Conditions
v

Microaddress
&

Specifier

Flush.

Signals

Operand

Special

Control

Cycles

ValuesS.

Size/Access

Special

<2:0>

Data

Logic

Descriptions

Operand

Source.

Signals/Functions
Data

Specifier

Entry

IBST

Size

Labels

Size

Opcode

.
.

Output.

Specifier
Pointer

.
IB

.
.«

Formats

Slow

Port

Literal

Short

Operand

Signals/Data

and

Point

Spec

Signals/Specifier

Formatter

Floating

Changes

Read

Control

After

Control

Conditions

Address/IB

Aligner

Vectors

Outputs

Relative

and

Microtrap

PCNC

Flush

Data

Conditions

Check

and

Conditions .
.
.
.
.
.
.
.
.
Microbranch Condition Bit Usage.

Special

MCAs

Relatlonshlp

Microbranch

IBST

o«

for

State

Priority

CodesS/IPLS.

Flag

Levels
©v

I APORT

¢«

Assignments

EXAMPLE

No.

Title
Sample

Field

Value

XXX1X

SECTION

EXECUTION

CHAPTER

INTRODUCTION

1.1

GENERAL.

BOX

o«

1=-1

EBoXx

Organization.

1=2

1.1.2

EBOX

Operators

Main

1.1.2.2

ALU

Cache

(EBOX)

i.1.1
1.1.2.1

LOGIC

Data

o«

1-4

o«

1-4

FUNCTIONS

&«

1=-5

¢«

o«

1-5

Path

Watcher/Decoder

1.2

SLICE

1.2.1

MODULE

Parity

1.2.2

(SLC1/SLCO)

File

(PAR)

o«

&«

1-6

(SDF)

o«

1-6

Counter

(PC)

Subsystem

¢«

1=7

(Main ALU).

1-8

+«

1-8

FUNCTIONS

&+«

¢«

@«

o«

1-9

¢«

o«

1=-9

Program
Cache

1.2.96

Main Arithmetic

1.2.7

Bus

Data

Path

(CDP).

Logic

Unit

Watcher/Decoder
MODULE

Shifter

(RGF).

1.2.5

SHIFTER

Bus

¢«

File

Data

1.2.4

1.3.1

and

Generator/Checker

1.2.3

1.3

(CDP)

(BWD).

(SHR)

(SHF).

1-7

Integer

o«

1.3.1.2

Floating=Point

Data.

¢«

Decimal

Data.

¢«

o«

1-10

Support.

1-10

1.3.2

String

Floating-Point

1.3.2.1

Priority

1.3.2.2

Shift

1.3.2.3

(FP)

Encoder

ALU

Exponent

1.3.3

ALU

EBOX

REGISTERS

1.4.1

POLR,

1.4.2

VAX

1.4.2.1

Pl1LR,

¢«

1-10

o«

1-11

(XALU).

Check

1.4,2.2

System

1.4.2.3

Revision

1.4.2.4

EBox

1-11

(MULT).

¢«

1-11

1-12

Formats

1-13

SLR

8800-Specific

Machine

Registers

Parity

Error

GENERAL.

SLICE

2.2.1.2

Parity

Checker

2.2.1.3

EBox

Parity

Carry

Save

Logic

File

2.2.2.3

Traps
Slow

Data

1-13

1-14

1-15

1-17

REVR2)

(EBER).

o«

2-1

¢«

o«

2-8

¢«

(EBER).,

2-11

2-8

2-12

2-14

(FPS)

¢«

2-14
2-16

RegiSterS

o«

¢«

o«

2-16

(SDF)

¢«

o«

2-18

o«

2-19

Stalis

File

Shuffle

(MD)

¢«

and

¢«

Memory

¢«

(PAR)

2.2.2.2
2.2.3

&«

(MCSTS).

Floating-Point

¢«

(RGF).

2.2.2.1

and

Error

DESCRIPTION

Generator/Checker
Generator

2.2.2

(SLC1/SLCO)

Parity

2.2.1.4

Bit

(SID)

(REVR1l
Register

2.2

MODULE

Identification

2.1

Parity

Registers.

Status

DESCRIPTION

2.2.1.1

Internal

FUNCTIONAL

2.2.1

and

(PEN)

1-9

(SALU)

Multiplier/Divider

1.4

CHAPTER

(BWD).

1.3.1.1

i.3.1.3

Data

2.2.3.1

WEItesS

2.2.3.2

ReadS.

o«

2.2.3.3

Stalls

and

TrapsS

¢«

o«

2—-19
=

2-19

W
N

N+~
N+

Address

D>
W N~

Path

2-22

o«

2-22

File.

2-22

2-23

¢«

2-24

2-31

2-33

(CDBF)
(CDS)

Logic

Half

(SHR)

Unit

(Main

ALU).

2~-41

o«

2-41

2—-44

DESCRIPTION

2-51

(ALF)

Functions

(SHF).

Count

Bus.

2-51

2-55

General

Function

Logical

Selection

Shift

Rotate.,

2-55

2-58

Conversion.,

2-58

Arithmetic
Decimal

Priority
Shift

Shift

String

Floating-Point
=

Store

Shift

Buffer

ALU

Data

MODULE

(PC)

Data

First

(CDP).

Cache

Arithmetic

(VA)

Cache

Main

Subsystem

Logic.

Counter

Data

ALU

w N

(PC)

Multiplexer

Shadow

Program

(FP)

ALU

W N

Carry

and

2-60

2-62

2-70

(MULT).

2-78

o«

2-86

.
.
.
Functions

2-86

Signals

Signals.

Arithmetic

Multiplier

Divider

Control

and

MCA

Interface

Logical

(XALU).

Multiplier/Divider
Data

(PEN)

(SALU)
ALU

Support.

Encoder

Exponent

e
L

¢«

OYOY U UTUT W

Trap

Shifter

Counter

Virtual

Main

Cache

[]

[)

[]

........00...'

SHIFTER
WWwWwWWwWiNDN
NI

wwwwwwwwwwwwwwwwwNMNNNNNMNNN

NNV NRNNONNONNNNONMNOMNNNNONNMNONMNNNONNODENDNNDNDN
DN D

Program

Operation
Operation.
.

2-95

2-96

i
W N

Title
VAX

Page

8800

CPU

Execution
Machine
System

Kernel

Unit

Check

Block

(EBox)
Status

Diagram.

Block

Diagram.

(MCSTS).

Identification

(SID)

Revision

(REVR1).

(REVR2).

.«

Slice

Block

Diagram

(PAR)

Block

— \O

Revision

NN
DNDDNDNDN
|
!
i
O JO U
WM

O
Y U1 >

P
o

FIGURES

Module

(SLC1/SLCO)
Generator/Checker

Parity
EBox

Parity

Data

Program

Cache

Error

File

(RGF)

Block

File

(SDF)

Counter

(PC)

Main

Data Path
Arithmetic

Block

Diagram.

Diagram

Block

(CDP)

Block

Logic

Unit

Shift

Module (SHR) Block
MCA (SHFT) Logic and

Block

Diagram.

(EBER).

Diagram.

Subsystem

Shifter

x1i

Diagram

Block

Diagram

Diagram.
(Main ALU)
4

Diagram
Gating

Shift

Control

Shift

Count

MCA

Block

Diagrame

Bus

(SHC)

Signal
o

Block

Diagram.

and

Gating

o«

2-55

«
.
.

.«
.
.

.
.
.

2-61

Shift ALU (SALU) Block Diagram . «
Exponent ALU (XALU) Block Diagram.

o«
«

o
«

+
.«

o
.

2-73

Diagram.

2—-88

.
.

Block

(MULT)

VAX-11] Floating-Point Formats. . . « .+
Priority Encoder (PEN) Block Diagram .
INMUX Mapping of the BPORT Input Data.

Multiplier/Divider

«
.

&+
.

TABLES

Title
Privileged IPRs
POLR, Pl1LR, and
Machine
Bit

Check

Maintained by the EBox
SLR Internal Formats .

Status

DescCriptionsS

.«

Revision Register 1 (REVR1)
Descriptions .
.
. .
.

B1t

Revision

Bit

Descriptions
Parity

.«

Generator/Checker

DesSCriplionsS

o«

Signal
o

¢«

.«

o«

(EBER).

EALUCIK1:0>

Control

SOUrCEe

CD PAR<3 1>
EBox Parity

the

o«

File

(RGF)

Signal

Descriptions.

Descriptions

Signal

Subsystem
¢
¢
«
«
o

APORT<7:6>

Input

Multiplexer

and

o«

Carry-In

Allocation

VAWRT

Address

(SDF)

ALU

(RGF)

File

Data

Selection

Signal
&
.

Control

Selection.

Input

Select Signals . .+ ¢«
¢ v
Cache Data Buffer (CDBF)

.
FA

.
Multlplexer

¢«
¢ o
o«
o o
o o
o o
Signal Description.

o
.

Cache Data Store (CDS) Signal Description. . .
CDS Output Multiplexer Control for Each Slice.
ALU First Half (ALF) Signal Descriptions .
.
.
.

Select

(ASEL)

Input

Control

Signals

B-Side

Select

(BSEL)

Input

Control

Signals

—f\

Conditions
1

Signal

}_l

Keepgoifig/Stall

(ALS)

-r-

Half

Second

Descriptions.

(T
o

A-Side

9]
0]

ALU

Control.

Multiplexer

Port

Program Counter (PC)
Descriptions .
.«
«
o«

O S S
C WO
U
W

B-Side

Slow

O
—

o«

Field

Keepgoing Conditions for A
E SHFT<4:0> Control of the

NN DNDNDDNDNNDNDND

Field

(PAR)

Control.

Port

o«

A-Side

Error Register

.
.

Bit
e
e

(REVRZ)

(MCSTS)
o

System Identification (SID) Register
Field Descriptions . . . .
.
e
e o

.
.

o
Main

ALU,.

2-64
2-65

2-79

shift

Count

ESHFT<4:0>

(SHF)

MCA

ESHFTSEL

the

Bus

Logic

Bus,

Data

EPEFUNC
the

Increment
to

the

Field

(PE)

Count

Logic

Data

Selection.

Functions

Signals

Control

Condition

Microbranch

Functions
&

.
¢

with

Condition

e
.

and

General

e
e

Equal

XALU

Not

Equal

2-81

(XALUCC)

TestS

o«

2-82

2-83

B-side

2-84

the

Adder

Outputs

the

XREG

Data

Bus

the

Multiplier/Divider

(MULT)

from

Control

LOGIC

Branch

Passed

MULT Logic Signal

.
.

Passed

Field

Inputs

Microcode

Inputs

the

Inputs

SXALUFN<5 3>
e

Description

M1l

Passed

ESXALUFN<5:3>

Code

BPORT

the

SALU

Inputs

o«

w1th

the

Code

Control

Functions

Code

Condition

ESXALUFN<5:3)

BOX

Multiplexer.

CACHE

¢«

Fraction

MULDIV

Selection

APORT

the

&
.

the

&
.

o
.

Control

o«

000

o«

Sign

Selection

XALU

Selection

Resulting

Field

Input

Microcode

000

Input

the

Bit

from

XALU

Functions

Test

ESXALUFN

Functions.,

R<1:0>
XALU

XALU

and

A-Latched

Passed
«

o
e

(INCD)

(INCR).

Dec1mal

PEN

Results

Bus

Output

Input

Guard

Bit

Control

Shifter

Result

Selection

SALU

Multiplexer

Bit

G<1:0>

CHAPTER

Incrementer

Sticky
Round

FunctionS.

Encoder

Shift

Source
of

ConversionS.

Field

Priority
to

and

Selection

EFPFORMAT<1:0>

String

Signals

Field

2-85

e
.

2-91

2-93

Control
.

.
the

Signals
e

MULT

Functions

Port Function Description.

2-90

(CBOX)

INTRODUCTION

CACHE
CBOX

BOX

SYSTEM

OPERATION

CBOX

CYCleS.:

Quiescent
Read

The

State.

¢«

o«

Cycles

¢«

Cycle

Write

DESCRIPTION

PIBA

x1iii

<o
U

[]
®
*

[]

=
N

W N~

U W~

et
et

1-9

1-10

Cycle

¢«

1-10

o«

1-11

DESCRIPTION.,

W N~

Buffer

BYyPasSS.

DESCRIPTION.

RAM

LatCh

SUBSYSTEMS

¢«

MCA

RAM

Match

¢«

Cache

Data

Cache

Tag

Cache

Match

Cache

Control

NMI

DESCRIPTION

Latch

Path
MCA,

Number

o
¢«

MCA.

Interface.

LogicC.
.+

MCA:

¢«

o«

¢«

MCA.

¢«

NMI

Address/Data

Sllces.

NMI

Out

¢«

NMI

¢«

=«

NMI

Arbitration/Acknowledgment

CBox

Control.
Control

NMI

¢«

«
o

o+
o

o
o

Translation Buffer -- Block Diagram. . .
Virtual Address Fields . + « ¢« ¢« o o o o
TB -- Write Sequence Diagram .
. .
TB Match MCA -- Simplified Block Dlagram
PABH MCA -- Simplified Block Diagram . .

.
o
o
.
.

PABL MCA -- Simplified Block Diagram
PA Latch =-- Logic Diagram. .
«
+ « o
PA Latch Bit Routing —-- Refill Cycle
PA Latch Bit Routing -—- VA Reference
Cache -- Block Diagram .
«
«
o
«
o
o

.
o
.
.
o

.
&

bt b
P

R
N

SUBSYSTEMS

L J

e
el
i

[ J

[]

Translation

Cache.

L[]

Stalls.

FUNCTIONAL

CBOX

¢«

Invalidate

CBOX

WWWWWWWNNNNNNN

L]
o
.«

Operation

CYCleS.

Refill
CBox

CHAPTER
MOVNNNNNRONNMOMOMNONNDNONNNNODNODNONNDNDN

Registers

k= =
N = O

MMM

O 00

NDNDDNNDDNDDN
i
30 U
Wi+

Z
o

CBox
CBeox

FIGURES

Title

~-— Block Diagram.
Cycle Timing., v o

NMI

Interface

NMI

Address/Data

Block
-14
2-15

NMI

Diagram.

Out

Control
NMI

Store

Diagram

Slices

Control
Control

Block

+«
o

o«

-o

Simplified

Microword
--

MCA

Block
x1iv

Format

.
o«
.
.
o

.
o
.
.
o

.
.
.

.
.
o

Slmpllfled
o

Block

Diagram

Diagram.

Diagram.
.

NMI

Arbitration/Acknowledgment

Control

Simplified

Block

Diagram

2-17

Timeout

Flow

Diagram.

.«

2-18

CBox

o«

2-19

Cache

2-20

Cache

Error

Byte

Bit

Format.

2-21

Cache

Error

2-55

Byte

Bit

Format.

2-22

Cache

2-56

Error

Byte

Bit

Format.

2—-23

NMI

2-57

=--

NMI

Registers

Fault/Status

Bit

Location

Diagram

2-52

2-53

Format

NMI

Fault/Status

Reglster

Bit

Format

NMI

Error

NMI

Silo

NMI

Silo

NMI

Silo

Cache

Bit

¢«

Address

Byte

.
¢«

Byte

c
v

Byte

Bit

—--

Bit

Format.

Byte

Bit

Format.

Byte

Bit

Format.

TAG

Initialization

Diagnostic

Control

Format

2-61

2-63

2-65

2-66

2-67

Format

2-68

Bit

Format.

2-69

TABLES

Title
CBOX

CYCleSo

PROTection

Field

<03:00>

Coding

Allowed.

MCA

Match

Descriptions.,
- Byte 2 Bit

¢«

Byte

DesSCriptions

¢«

Byte

Fault/Status

Descriptions

Reglster
.

Address

Descriptions

Reglster

Fault/Status
Error

Descriptions

NMI

Access

Error

NMI

and

Coding.

Operation

DeSCriptions

NMI

Cache

Error

- Bit
Register

Error

Cache

Reglster

¢«

o«

Bit

o
Bit

Byte

Bit

o
¢
Byte

s
o
Bit

e«

e
--

Blt

NMI

Silo

Byte

Bit

Descriptions,

NMI

Silo

Byte

Bit

Descriptions.

NMI

Silo

Byte

Bit

Descriptions.

Cache

TAG

Initialization

Descriptions

.«

Diagnostic

Control

Descriptions

¢«

-4

Bit
4

Bit Descriptions
Register -- Bit
¢

Xx1lv

¢«

o«

2-60

Bit

Format

2-49

2-51

Format

Bit

EK-KA88M-TD-PRE

SECTION
MEMORY

SYSTEM

(MBOX)

CHAPTER

INTRODUCTION

1.1

MANUAL

This

SCOPE

document

memory

provides

system

(MBox)

architecture

software

explaining

does

not

the

memory

provides

the

Chapter

Included

its

interface
comprise

Chapter

with
the

the
MCL,

areas.

The

the

engineering

are

correlated

MCL's

and

bus

MAR4

array

detailed

(NAB)

within

the

memory

MCL,

overview

and

description

detailed
areas

description

all

the

Thus,

the

prints,

8800

system

microcode

this

and

manual

treatment

the

MBox.

how

the

describes

system.

controller

the

NMI

with

(MCL).

signals

functional

description

the

that

areas

that
functional

the

organization

detailed

descriptions

specifications,

etc.

the four-megabyte memory array
3 is a description of the MAR4
the

includes

the

coincide

engineering

how

and

also

features

system

VAX

memory

thorough

8800

system

the

however,

VAX

description

and

cover

the

documentation.

board.

major

memory

Chapter 3 provides a description of
board
(MAR4).
1Included in Chapter
array

made

functions;:

the

not

complete

functional

with

description
does

system.

the

function

provides
in

purpose

overview

performs

Chapter

Use

hardware

aspects

MBox

technical

software.

purport

software

provides

hardware.

NAB

MAR4's

signals

overview

functional

function

the

areas.

the

MAR4

and

The

MAR4's

functional areas coincide with the organization of the
engineering
documentation
in
the
same
manner
as
the Chapter 2 functional
areas.

used

appendix

the

1.2
It

provided

explained

detailed

reader

has

explains

the

flow-diagram

symbology

description.

PHILOSOPHY

helpful

followed

that

technical

WRITING
will

were

The

MBox

1in

the

to
the

the

following

descriptions
read

and

reader

writing

this

aware

some

document.

These

points
points

that
are

paragraphs.

Chapters

understands

1-1

the

and

overall

assume

that

the

descriptions.

The

detailed descriptions are confined to the area being described. It
is important that the reader has read and understands the overview
in
order
to
understand how the detailed functions relate to the
overall

operation.

The
functional
block diagrams use logical AND and OR symbols. It
does
not
necessarily
follow that a corresponding gate exists on
the
engineering
circuit
prints. The assertion of inputs A and B
causing
the
assertion
of output C may be represented on a block
diagram by a single AND gate, yet the engineering drawing may show
that several circuit stages are involved in the ANDing operation.

The
signal
mnemonics
used in the illustrations are identical to
the
signal
mnemonics used in the engineering logic prints except
for
"fan-out"
1line
designations
which
have a number or letter
designation
(<X>)
that
specifies
a
fan-out of a given signal.
Fan-out
lines
are functionally identical, hence the fan-out line
designations
have
been
omitted
to prevent confusion with other
signal

designations.

The
signal mnemonics do not contain the H or L designations found
on
the
engineering
drawings.
Signals
are referred to as being
asserted
or
negated
without
regard to high or low states. This
point must be kept in mind when using timing waveform diagrams. As
the
signals
have
no
H
ovr L designation, they are always shown
above
the
reference
1line
for
an asserted condition and on the
reference

line

for

negated

condition.

Flow diagrams are used extensively throughout
to
Apendix
A
(Flow
Diagram
Symbols)
for
meaning

any

the

flow

diagram

this document. Refer
any question on the

symbols.

It
1is to be noted that the flow diagrams are NOT timing diagtams;
in
some cases the assertion or negation of a signal may not occur
exactly
when
shown
1in a flow diagram. A given signal may assert
before
it
serves
1its
purpose
in the flow of events. In such a
case,
the
signal
would appear in the diagram at the point it is
used
rather
than at the point it was asserted. The flow diagrams
are
meant
to
1illustrate
the
purpose
and
functioning
of the
hardware;
to
do
this, the signals must be discussed at the time
they
are
performing
their
function.
Where signal timing has a
functional
significance,
separate timing diagrams are used. With
this
restriction
noted,
the
flow
diagrams
provide
a
useful
representation
of
what
is
happening
by serving as a pictorial
supplement to the written descriptions.

1.3

Figure

MBOX FUNCTIONS
1-1
is
a
simplified

block diagram of the MBox. The
interfaces
with
the
NMI
where
it
always functions as a sl
nexus.
The
MBox
consists of a memory controller (MCL) and up to
eight
identical
four-megabyte
array
boards
(MAR4s). The MAR4s
interface
with
the MCL via an array bus (NAB). The NAR has eight

board-select
—-=

which

lines

enable

shown

Z/\r

ADDRESS
DATA<31:0>

Figure

(AMCL

MAR4

1-1

are

BRD

SEL<7:0>)

execute

common

all

MASK<3:0>

each

The

array

other

board

NAB

lines

MAR4s.,

>{%§;§;§;; r’

AMCL
CMD<3:0>

MCL

MARa

anl

<25.

one

’——D

SEL<7:0>

NMI

the

AMCL BRD*

NMI

—--

function.

;

(

BOARD 0

)

____.»

AMCL

DATA<31:0>

BMAR
DATA<31:0>

0Oococoo0

MAR4
(BOARD 7)
*

ONE LINE

PER ARRAY BOARD.

SCLD-337

Figure

NMI

transaction

the

NMI

the

NMI.

In
by

longword(s)

the

commander

the

MBox

the

data

the

commander

1ID,

Simplified

initiated

places
more

data

write

ready

to
in

Block

cycles

NMI

send

the
in

address,

which

NMI.
the

1-3

the

read

cycle(s),

the

wherein

its

cycle

commander

places

In a read transaction,
command/address cycle.

requested
data

cycle

and

command/address

the

transaction

after

the

read

Diagram

command/address

function,

data
the

NMI

initiates

transaction,

vteleases

When

that

MBox

write

one

the

Nexus

commander*

followed

1-1

NMI.

data,
along

places

with

the

1is a simplified flow diagram which illustrates the
Figure 1-2
sequencing of read/write transactions. When a commander issues a
command to memory, it places its ID code (NMI ID MASK<3:0>), the
and the address (NMI
(NMI FUNCTION<4:0>),
commanded function
on the NMI during the command/address bus
ADDRESS DATA<31:0>)
cycle.

The MCL then:

Stores

°®

the

commander

be used if this is a read

operation.

Determines which MAR4 board is being selected from the
and asserts the select line (AMCL BRD SEL)
NMI address,

for the selected array board.

Transfers the NMI address to the MAR4 as AMCL ADDR<25:4>
become part of the 4-bit command
<3:2>
bits
[address

[

(AMCL. CMD<3:0>) and are used to select the array bank on
bits <1:0> are not used as all array
address
the MAR4;
addresses are longword alignedl.

Transfers

°®

the commanded function to the selected MAR4 by

asserting AMCL CMD<3:0> on the NAB.

If a write operation is executing, the commander places the write
data on the NMI address/data lines in the next (data) bus cycle.
The MCL takes the write data from the NMI and transfers it to the
The selected MAR4 then writes the data
NAB as AMCL DATA<31:0>.
into

its

memory

arrays.

If a vread operation is executing, the selected MAR4 supplies the
addressed read data to the MCL as BMAR DATA<31:0>. The MCL places
the read data on the NMI address/data lines along with an NMI
function code specifying the data as good read data. The MCL also
1ID code on the NMI ID mask<3:0> lines to
places the commander's
identify to whom the read data belongs.

If a masked write operation is commanded, the commander places the
masked write data on the NMI address/data lines, and the mask
during the data cycle. The masked
lines,
field on the 1ID/mask
1is transferred to the MCL where it is held while the
write data
The BMAR
read.
1is
selected MAR4
the
1location on
addressed
DATA<31:0> read data is transferred to the MCL where it overwrites
the stored write data according to the mask field. The new write
data is then written into the MAR4 as AMCL DATA<31:0>.
MBOX OVERVIEW

1.4

used in the MBox are prefixed with the phase of the clock
Signals
to which they are referenced (A or B) and with the signal source.
"AMCL" prefix indicates the signal is referenced to the
an
Thus,
phase A clock and its source is the MCL. A "BMAR" prefix indicates
1is vreferenced to the phase B clock and its source is
the signal
the

MARA4.

1-4

Commander initiates
NM! MBOX transaction.

NMI 1D MASK<3:0>
Store

commander

I1D.

NMI FUNCTION<4:0>
Command to

AMCL CMD<3:0>
Command to

G-1

Write

selected

MAR4,

Command

NMI

]

ADDRESS

Address

DATA<31:0>
MCL.

MCL.

AMCL BRD SEL

AMCL ADDRESS<25:4>

MAR4 board

Array

Masked write

function

selected.

address

selected

MAR4.

NMI

ADDHRESS DATA<31:0>

Write

data

MCL.

BMAR DATA<31:0>
Read

data

from

NMI

MAR4,

ADDRESS

DATA<31:0>

NM!

Maskod
writel data
_MCL

AMCL DATA<31:0>

NMI

Write

Read

data

MAR4.

ADDRESS DATA<31:0>
data

NMI.

NMI

Read

FUNCTION<4:0>

data

function.

NMI

MASK<3:0>

Commander

[D.

MASK<3.0>

Mask tield 1o MCL.

BMAR DATA<31:0>
Read

verwrite
read data

AMCL

data

from

masked write
according to

MARS4,

data
mask

with
field.

DATA<31:0>

New write

data

MAR4.

SCLD 338

Figure

1-2

MBox

Read/Write

Simplified

Block

Diagram

1.4.1

NMI

Signals Used

the MBox

Signals on the NMI that interface with
1-1.
Most
of
these signals are used
described in Section 1.4.5.

1.4.2

The

MBox Operations

operations

supported by the MBox,

function

codes,

are

listed

Table

1.4.3

Octaword Sort-of-Write

the MBox are shown in Table
in NMI/MBox transactions as

and

their corresponding NMI

1-2.

A
non-masked
octaword
write
transaction
is
a "sort-of-write"
operation
in
that the mask field associated with the longword is
used
to
specify
if
the
1longword
1is
to
be
written.
The
sort-of-write feature allows a nexus with longwords of data within
an octaword address to use the octaword write function even though
all
the
longwords
are not to be written. This allows data to be
transferred
on
the
NMI
1in
one
1large transfer, rather than in
several

slower

transfers.

Non-masked
longword
writes
are
also
sort-of-writes.
The
sort-of-write
rationale
does
not
apply
to
longword
writes,
however,
due to logic standardization, the sort-of-write function
is implemented for all non-masked write transactions.

1.4.4

Command Bus

Possible

sizes of NMI
Longword

Cycles

transfers

for read/write operations

are:

writes

Quadword writes

(masked writes

only)

Octaword
Longword

writes
reads
Octaword reads
Hexword reads

Sections
1.4.4.1 through 1.4.4.6 describe the NMI bus cycles that
occur
for
the six transfers listed above. An NMI bus cycle is 50
ns.

1-6

Table

NMI

1-1

Signals

Used

the

MBox

No.

Signal
NMI

ADDRESS

NMI

DATA

DATA<31:0>

PARITY

Direction

of
Lines

Function

Address

and

data

Parity

bit

address/data
NMI

FUNCTION<K4:0>

Command

NMI

Commander

MASK<3:0>

lines.
for

lines.

function

(Table

and

mask

code.
NMI

FUNCT

PARITY

Parity

bit

for

function/ID/mask
NMI

CONFIRMATIONK1:0>

MBox

confirmation

(Table
NMI

MEMORY

ARB

MCL

BUS

code

1-4).

MBox

arbitration

request
NMI

lines.

NMI

line.

bus

grant

MBox

from CPU,

NMI

MEMORY

HOLD

Holds

NMI

for

MBox

after

receiving

bus

grant.

NMI

MEMORY

NMI

MEM

BUSY

ARB

MBox

busy

arbitrator
NMI

LCPU

MEM

INTR

MBox

NMI

RCPU

FAULT

MEM

INTR

DETECT<K3:0>

FAULT

MBox

interrupt

right

CPU.

Fault

bidirectional;

unidirectional

1-7

1lines

NMI

nexus.

NMI

CPU.
line

line

CPU.

fault

line

interrupt

left
NMI

line.

MBox

1lines

nexus.

from

other

fault

and

from other

Table

1-1

NMI Signals Used by the MBox (Cont)
No.

Lines

Function

Signal

Direction

NMI SLOW COUNT ENABLE

NMI DC LO

Warning

NMI BAT DC LO

Backup

Increments MBox timeout

counter.

power

battery

power

loss.

low

power

will be a "cold start.”

NMI SLOW MODE

Warning that clocks avre

NMI HARBINGER

Inhibits MBox clocks.

NMI UNJAM

Initializes MBoX.

NMI F A CLK IN

§]

Free

NMI F B CLK IN

Free

B = bidirectional; U

unidirectional.

Table 1-2
Function

about

stop.

running,

phasc A

trunning,

phase B

clock.

MBox Command Functions

321 0>

Command

1 0
1 2
1 3

1
1
1

¢ 0 0C ¢
0010
0011

Recad longword
Read octaword
Read hexword

1 4
1 6
1 7

1
1
1

0100
0110
0111

Read longword interlocked
Read octaword interlocked
Read hexword interlocked

1 B
1 F

011
1 111

Write longword
Write octaword

1 8
19
1 A

1
1
1

1000
i 001
1 010

Write masked longword
Write masked quadword
Write masked octaword

1 C
1D
1 E

1
1
1

1100
1 101
1110

Write masked longword unlock
Write masked quadword unlock
Write masked octaword unlock

(Hex)

1-38

Table

1-2

MBox

Command

Functions

(Cont)

Function

(Hex)

3210>

Command

1010

Read/return

1110

good

Read/return

bad

data

1000

Read/continue

1100

good

Read/continue

bad

Write

1.4.4.1

Write

Longword

Table

Bus

1-3

data

Cycles

Write

DATA<31:00>

FUNCTION<4:0>

MASK<K3:0>

CONFIRMATIONK1:0>

the

command/address

the

NMI.

write

five-bit
The

and

bus

function

code

further

code

defines
identifies the

data

cycle,

the

Wwrite-data

write-data

the

cycle

and

specifies

The

byte
or

the

third

the

NMI

codes
and

Table

occur

bus

the
Four

—-———-

Addr

Data

—-———-

Write

=——--

data

CMDR

Byte

mask

————

the

write

flag

Section

third

places

four-bit

the

places

identifies
on

operation

the

32-bit

mask

the

data

cycle

address/data

mask

for

non-masked

MBox

places

bus

cycle

confirmation

the

for

all

responses

1-4.

1-9

2-bit

data

NMI

write

transaction

confirmation

code

Confirmation

transactions
possible

The

NMI. The
write-data

masked

write

longword

longword,

lines

commander.

are

32-bit

code

function.

byte

the

response

byte
for

the

ID/mask

1.4.3).

the

its

commander

and

data

cycle,

the

————

it as a masked or unlock
transaction commander.

specifying

writes).

Data

specifies

the

mask

Sort-of-Write,

Addr

code,

code

data.

(see

Cycles

commander

function

transaction,

—--

Bus

cycle

function

ID/mask

1-3)

Cmd/

ADDRESS

address,

(Table

Longword

Cycle

data
data

(reads

shown

1-4

Table

NMI Confirmation Codes

Confirmation

NMI Confirmation

1.4.4.2

State

0
0
1
1

0
1
0
1

No acknowledgement
Command accepted
Interlock busy
Memory busy

Write Quadword Bus Cycles

Write Quadword* Bus Cycles

Table 1-5

Cycle
ADDRESS

(Table 1-5)

DATA<K31:00>

FUNCTION<K4:0>

Cmd/
Addr

Data

Addr

Data

Masked

Write

write

data

ID MASK<3:0>

CONFIRMATIONK1:0>
*

Masked writes

CMDR
ID

Byte

mask

—_——

————

only.

In the command/address bus cycle the commander places the address,
code, and the ID code on the NMI. The function code
function
the
specifies the transaction as a masked quadword write (a non-masked
quadword write is not a valid NMI function) and if the transaction
is a write unlock function. The ID code identifies the transaction
commander.

data

two write-data cycles that follow,

the

longword,
The

NMI.

write-data
as

The

write

a write-data cycle code,

write-data

cycle

code

the commander places a

and the byte mask on the

1identifies

the

<cycle

cycle and specifies the data on the address/data lines

data.

third

bus cycle

is the data cycle for the second longword of

write data. The confirmation code is placed on the NMI during this
cycle.

1-10

1.4.4.3

Write

Octaword

Table

Bus

1-6

Cycle

Cycles

Write

Cmd/

(Table

Octaword

1-6)

Bus

Cycles

Data

Addr

Data

Write

data

Addr
ADDRESS

DATA<K31:00>

FUNCTION<K4:0>

MASK<K3:0>

CONFIRMATIONK1:0>

the

command/address

function

specifies

code,

the

transaction

the

four
The

Byte

mask

————

—_————

bus

and

masked

cycle

the
or

the

code

unlock

write-data
a

cycles
<cycle

<code

write

data.

for

write

The
of

The

the

write

The

address,

function
and

code

the

identifies

transaction,

code,

the

commander

and

specifies

The

the

byte

write

byte

the

mask
flag

places

mask

data

the

for

the

byte

mask

non-masked,

transaction.

confirmation
the

follow,

cycle

lines

masked

places

NMI.

octaword

that

write-data

the

function.

address/data
sort-of-write

commander
on

commander.

longword,

NMI.

Byte

transaction

the

data

CMDR

code

placed

NMI

the

third

bus

cycle

transaction.

1.4.4.4

Read

Longword

Bus

Cycles

(Table

1-7)

1In

the

command/address
function
code,
specifies
the

bus
cycle
the commander places the address, the
and
the
1ID
code
on the NMI. The function code
transaction
as
a
longword
vread,
and
if
the

transaction

transaction
The

MBox

cycle

places
the

After

the

board,

the

1is

interlock

function.

The

code

identifies

the

commander.
the

confirmation

code

the

NMI

the

third

bus

transaction.
MBox

has

arbitrates

arbitration

extracted

for

logic

it
asserts
NMI
MCL
grant is issued in the

the
in

BUS
same

NMI

the

CPU

requested

asserting
grants

EN as a bus
arbitration

won.

1-11

the

grant
cycle

data

NMI

from

MEMORY

the

array

ARB.

When

arbitration

to the MBox.
in which the

request,

The
bus

bus
was

Table

1-7

Cycle

Read

Longword

Bus

Cycles

Cmd/

Arb

Data

Addr
ADDRESS

DATAK31:00>

FUNCTION<4:0>

Addr

Data

Read

-—

Read

MASK<K3:0>

Rtn

CMDR

CONFIRMATIONK1:0>

—-—

NMI

MEMORY

ARB

Arb

NMI

MCL

BUS

NOTE

Table

1-7

right

away.

illustrates

The

Dbus-grant

the

MCL

lines,

cycle

places

commander

read
ID

functions

the

case

followed

longword

return function
the ID/mask
in

Table

the

read

MBox winning

first

data

data
the

the

cycle

NMI

bus

which

address/data

code on the function lines, and the
lines. There are four possible read

seen

1-2.

These

are:

data

placed

the

first

any)

have

Read/return good data
Read/return bad data
Read/continue good data
Read/continue bad data
The

first

return”
data.

The

function
The

Jlongword

function

MCL

following

performs

1longwords

(if

(double-bit)

error
with

NMI

carries

ECC

(single-bit)

data

read

specifying

the

NMI

has

longword
a

"read

"rcad

read

continue"

code.

correctable
the

code

1is
a

check

errors

detected,

"bad-data"

"good-data"

read

found.

the

code.

1-12

data

erroneous

function

all

code.

and

corrects

any

non-correctable

longword
Otherwise,

placed

the

read

1.4.4.5

Read

Octaword

Table
Cycle

Bus

1-8

Cycles

Read

{Table

Octaword

Cmd/

1-8)

Bus

Cycles

Arb

Data

Addr
ADDRESS

DATA<31:00>

FUNCTIONK4:0>

Addr

—

-—

Data

Read

rtn

cont

CMDR

-—

MASK<3:0>

CMDR

-—

CONFIRMATIONK1:0>

NMI

MEMORY

ARB

Arb

NMI

MCL

-—

NMI

MEMORY

HOLD

Hold

BUS

-—

NOTE

Table

1-8

right

away.

the

1illustrates

command/address

function

specifies

the

transaction

MBox

cycle

the
it

the
as
one

CPU
a

places

board,

cycle

the

interlock

the

MBox winning

commander

ID code

octaword

the

function.

The

places

NMI.
ID

The

the

NMI

bus

address,

function

read,
code

the

and

code

the

identifies

the

commander.

the

After

bus

and

case

transaction

1is

transaction
The

code,

the

confirmation

code

the

NMI

the

third

bus

transaction.

MBox

has

extracted

arbitrates

grants

the

bus-grant

cycle.

asserts

NMI

MEMORY

HOLD

for

the

arbitration
the

the

MBox.

MCL

the

HOLD.

arbitration

The

the
it

bus-grant

the

MEMORY

When

request,

The

needs

requested

NMI.

NMI

CPU

for

data

asserts

the

NMI

array

logic

MCL

BUS

in
EN

holds the NMI for only
the next bus cycle,
it

arbitration

request

from

arbitration

and

logic

keeps

NMI

treats

MCL

NMI

BUS

asserted.

The

first

data

cycles.

NMI

along

bus-grant

The
with

MCL

«cycle
1is followed by the first
places the first longword of read

the

read

commander

ID.

The

MCL

bus

and

keeps

cycle

also

function
asserts

asserted

for

1-13

of the four
data on the

code
NMI

the

(read/return) and the
MEMORY HOLD on the first

two

bus

cycles.

This

NMI

the

gives

transfer

the

MCL

for

the

four bus cycles needed to

the data octaword.

the read
of
any
in
detected
1is
error
non-correctable
a
If
function code is placed on the NMI with
"bad-data"
a
longwords,
the

longword containing the non-correctable error.

the
1In
-1-9)
(Table
Cycles
Bus
Hexword
Read
l1.4.4.6
the commander places the address, the
<cycle
bus
command/address
on the NMI. The function code
<code
1ID
the
and
code,
function
the
if
and
vread,
hexword
a
as
transaction
the
specifies
an interlock function. The ID code identifies the
1is
transaction
transaction commander,

The

MBox places the confirmation code on the NMI

cycle of

the

in the third bus

transaction.

extracted the requested data from the array
has
MBox
the
After
arbitrates for the NMI. When the MBox receives the NMI
it
board,
it places the first longword of read data on the NMI
grant,
bus
along with the read- data function code, the commander ID, and the
NMI

MEMORY HOLD signal.

the read
of
any
in
detected
1is
error
non-correctable
a
If
function code is placed on the NMI with
"bad-data"
a
longwords,

the longword containing the non-correctable error.

of read data is transferred to the NMI in two octaword
A hexword
MBox requires that there be at least one bus cycle
The
transfers.
octaword transfers; hence, it must re-arbitrate
two
the
between
for the NMI

1.4.5

The

MCL

Memory Controller

interfaces

performing

for the second octaword

the

following

(MCL)

memory

transfer.

array

with

boards

the NMI by

functions.

on the array
commands
NMI
the
of
execution
Controls
interlocked
and
masked
implementing
as
such
boards,
functions.

octaword
and
gquadword
Converts
writes for the array boards.*

Converts

writes

into

longword

hexword reads into octaword reads for the array

boards.*

Performs ECC checking of read data, correcting single-bit

errors

and

flagging double-bit errors.

* The array boards perform only longword write,
octaword

read

operations.

1-14

longword read,

and

Table

Cycle

Cma/

1-9

XI
S1-1T

MASK<3:0>

Data

Arb

Data

Read

rtn

cont

CMDR

Data

Read

rtn

cont

CMDR

- -

1D
CONFIRMATION

MEMORY

NMI

MCL

NMI

MEMORY

BUS

-—

—-

ARB

-—-

Art

-—-

Arb

~-—

-—

- -

—--

Hold

<1:0>»
NMI

Cycles

Data

Bus

Addr

DATA<31:0>
FUNCTION<4:0>

Hexword

Arbb

Addr
ADDRESS

Read

HOLD
NOTE

Table

1-9

illustrates

the

case

the

MBox

winning

the

NMI

bus

right

away.

Figure 1-3 1is a block diagram of the MBox (MCL, NAB, and MAR4).
The MCL is divided into three sections; the DFA, the MDP, and the

MRM, whose functions are listed below:

The DFA interfaces the memory system to the NMI.

The

MDP

The

MRM interfaces the MCL commands to the array boards,

Signal

1lines

®
®
e
®

AMCL
AMCL
BMAR
BMAR

(memory

data

path) routes the read/write data

between the DFA and the array boards.
and monitors array board status.

th e

NAB

are common to all of the array boards

except the following four signa

BRD SEL<7:0>
READ BD SELK7:0>
DATA RDY DONE<K7:0>
SEND NO CMDK7:0>

output

signals

These

the

MRM

eight

connected to each arrvay board slot.

1lines

with

one 1line

1.4.5.1 Command/Address Sequence —- Figure 1-4 is a flow diagram
of the command/address sequence (receiving an NMI command and
accessing the array boards). Refer to it and to Figure 1-3 during
the following discussion.

When

sends a command to memory, it places the following

nexus

signals on the NMI in the command/address cycle:
®

NMI FUNCTION<4:0> -— the command function

NMI ID MASK<3:0> -- the commander ID

NMI

NMI ADDRESS DATA<31:00> -- the memory address

)

NMI DATA PARITY —-- parity bit for the address/data field

FUNCT

ID/mask

1ID

fields

PARITY

parity

over the function and

The memory system may not be able to accept a command at this time
due to its being busy processing other commands, or due to being
If this 1is the case, the DFA asserts a "busy" or
write-locked.
nwrite-locked" confirmation code (NMI CONFIRMATION<1:0>) on the

(Table 1-4). The commander will then try again at a later
NMI
If the DFA determines the command to be invalid, it asserts
time.

a "no acknowledgement" confirmation code. If the command 1is
accepted by the MCL, a "command accepted"” confirmation code is
asserted.

1-16

NM|

ADDRESS

ADFA

DATA<31.0>

PARITY

Mcrionca:0n

ARTA apDRcas0

NMI 1D

ERABOA1

BMAR DATA<38°22»

<31.0>

MASK<3.0>

DATA PARITY

ADFA BAD DATA

PR
DATA<31:0> |

NM|

moe

NMI_FUNCT
NMi_FUNCY

AMOP

AMt Mol

OFA

<«

M0P DBE

]

Eal'm HOLD

¢ CONFIAMATION<1:0> |

3
Z Le NMI_FAULT

ANCL ADDR<25:4>

‘0>

A’E&Mfi.‘.&;fi INT DATA<310»

AMCL. BAD DATA.

INPUT

BDFA SIZE<1:0a

VEM INTA

DA MASK 0

»

AMCL CMD

ADQH PAR_ERA

ADDH_FAR

a0 SAR emn

AMCL CM0<.0>

BMAR DATA

‘_flm——NMl-

NO CMD<?
Ox

aMAR

CHEC

KER

o i <

BanK o

LOAD

ROY DONE<7:.0>*
SEND

LOAD

—>acon
»|

la—>]

M8, mu{

war

BANK 2

—
]

LOAD

> whr

BANK 2

QE'G'[()

EN<Q>

>
"

[

INTR

ATAc38 32>

gffifi

ANK

Shele

FF
4

READ

BQ’:K

AD,

il AODR |,ARRAY
1MB DATA{H
%
P

» DATA

SLOW MOOE

NM|_HARBINGER

DATA<1>

DATA<2» |

NMI UNJAM

ARRAY

LOAD

AMCL BRD SEL<7.0a°
SELS7:0> o

¢-2MEM (NT ERR. |

AooR

—~pf DDA IMB OATA{

BMAR CMD

*J‘MW—NW
| CQUNT ENARLE

I’S%'R 0

L _READ 8D

NMI ACPU

MM INTA

]

CMD_ADDR PAR

BOFA CMD<2.0»

NMI LCPU

AMPRM
AMCL

BNUM<2:0>

FAULT DETECT<3:0»

AMCL ADDRA<254

EN<3:0> | EN<3:0>

ADFA PAM

NMI

AMCI DATAc31
0y

| AMCL WAITE ENABLE

aus

LT-T

BMAR DATA<31°0

<Jd1.0>

AMCL DATA PARITY v

BIT

NMI

BMAR DATA<38-32>

BMAR DATA<31:0

P
READ

EN
R ‘*—fl

DATA<3:0>

NMLDC
10
NML BAT_DC LO

88U

MCL_COLD STABT

AMCL
CMD<3:0>

—»

CONTROL

LOGIC

|-BEAD BANK EN<3-0a

|DB_WAT DATA DIS

wc_pATTERY EnaR 5] | BRGse

AMCL_REA

DATA
OUT CLK
READ SELECT

SEL

|
DRIVE
BMCL
NEW DATA
o-BMAR_DATA RDY DONE

¢-EMAR SEND MO CMD

ONE LINE PER ARRAY BOARD.

W
e

MCL

MAR4

=||

SCI0. )8

Figure

1-3

MBox

Block

Diagram

NMI FUNCTION<4:0>
NMI iD MASK<3:0>

NMI FUNCT 1D
PARITY
NMI

DATA«<31:0>
DATA PARITY

M\m

Commar
by
accepted/

MCL

NM|

AMRM INPUT WRT
ENc3:0>
Address stored
in MDB.

CONFIRMATION

<1:0>

NMI CONFIRMATION

<1:0>

Pann\m
0(/

81-1

YES

BMAR
SEND NO CMD

L
|

NO
NM{

NMI FAULT

CONF:AMATION

<1:0>

No acknowledgemaent,

AMCL
AMCL
AMCL
AMCL

BRD SEL
CMD<«3:0>
ADOR<25:4>

CMD ADODR PAR
y

Abort

operarion.

Parity
oK

]

Command accepted.

‘_—.—.—

Memory is busy or
write-ltocked, or
function is
invalid.

Y
BMAR CMD ADDR
PAR ERR

YES

AMAM INT ERR
Abort

Road

NMI
NMI

YES

ADFA PRM BNUM
<3:0>
BDFA CMD«<2:0>
BDFA SIZE<1:0>
ADFA DATA ADDR
<31:0>

operation.

LCPU MEM INTR
RCPU MEM INTR

)

SCLD-340

Figure

1-4

Command/Address

Flow

Diagram

Using

the

data

the

NMI,

the

function/ID

NMI

FAULT

and

the

parity
DFA

and

field.
"no

operation

parity

bit

performs

the

1If

acknowledgement"

error

the

NMI

extracts

size
of
function
®

°®

The

for

the

board

DATA

AMRM

INPUT

MRM

checks
board

command

this

°®

type

them

sends
is

the

DFA

code

the

NMI

EN<K3:0>

due

BMAR

Enables

the

AMCL

SEL

The

from

CMD
if

target
select

the

line

the

NMI,

from

the
the

and

the

NMI

commander
NMI,

DFA to

stored

the MDP

the

MDP

MRM.

line
it

from

the

not

able

false,

array

BNUM<2:0>)

CMD<2:0>)

the

data

MRM.

stores

executing

CMD

PRM

and

asserts

MRM.

placed

through

the

SEND

the

SEND
to

(BDFA

address

from

the

SIZE<1:0>)
to

data

(ADFA

executing,

read

address

BMAR

operation

and

asserts

Provides

bit

address

the

processes

number

sends

(BDFA

the

WRT

BRD

and

ADDR<31:0>.

time

refresh.

parity

memory

detected,

DFA

transfer

when

the

The

doing

the

transfers

board.

array

address

operation

ADFA

the

confirmation

the

code,

use

detected,

the

read

aborted.

extracts

from

checks

error

follows:
)

function/ID/mask

parity

the

target
to

read

array

command

a
or

MRM:

board

asserting

the

command

the

board

board's

line.

four-bit

arrav

(AMCL

CMD<3:0>).
The command contains a read/write bit, a size
bit,
and two starting address bits. The starting address
bits
select
the
bank
on the array board (array boards
have

Provides

The

MRM

abort

asserts

If
to

NMI

the
the

the

address

Provides

CMD ADDR

(AMCL
board

and

The

banks).

MRM
array

fields

and

four

responds
the

BMAR
to

two

CPU

MEM

INTR).

checks

OK,

parity

check

parity

error

AMRM

the
in

AMCL

parity

ERR

interrupt

operation

bit

ADDR<25:4>.

generated

the

PAR).

PAR

operation.

the

parity

MDP

CMD ADDR

the

RCPU

type

the

command/address

performs

asserts

from

INT

ERROR

lines

command

progress.

1-19

the

command/address

error is
asserting AMRM

detected.

sent

DFA which

the

NMI

operation

(NMI

the
LCPU

proceeds

INT
MEM

ERROR
INTR

according

1.4.5.2
Normal
Write =-- Figure 1-5 is a flow diagram of a write
operation
data
cycle
and
1is used in conjunction with the block
diagram (Figure 1-3).
In
a
write
operation
following signals on the

NMI

data
NMI:

FUNCTION<4:0>

<cycle,

the

commander

command

places

function

the

(write data

cycle)

NMI

ID MASK<3:0>

FUNCT

-- write

flag

PARITY -- parity over the

function and ID/mask

fields

NMI ADDRESS

NMI

DATA<31:00>

-- the write data

DATA PARITY -- parity bit

longword

for the write data

NMI
FUNCTION<4:0> specifies a write—-data function to the MCL. NMI
ID MASK<3:0> is checked for the write flag that specifies that the
write
data is to be written into the memory arrays (sort-of-write
operation,
Section
1.4.3).
An
asserted
flag causes AMCL WRITE
ENABLE

asserted

the

array

board.

Using the data parity bit and the function/ID/mask parity bit from
the
NMI, the DFA performs parity checks on the write data and the
function/ID/mask
fields. If an error is detected, the DFA asserts
NMI
FAULT
on
the
NMI
and
ADFA PARITY ERROR1 to the MDP. ADFA
PARITY
ERROR1
causes
the
MDP to set the bad-data bit (AMCL BAD
DATA)
on
the
NAB,
however
the
write
operation is allowed to
execute.
When
the
write
data
1is
written into the arrays, the
asserted
bad-data
bit marks the data as bad. The data is written
so that it can be analyzed later by maintenance diagnostics.
The

write data

the

MDP

(NMI ADDRESS

DATA<K31:0>)

as ADFA DATA ADDR<31:0>.

by AMRM

INPUT WRT

EN<K3:0>

from

passes

through

The write data
the

the

stored

DFA to

the

MRM.

The
only
write
operation
performed
by
the
array boards is a
longword
write; hence, the MCL must convert quadword and octaword
writes

For
not

into a

series

longword writes

for

the

array

board.

a
normal
(non-masked) write operation, the array board does
assert
1its
BMAR
SEND
NO
CMD
1line due to an operation in

progress,
because
only
one
array
bank
1is being written (only
longword writes are executed by the array boards). The other three
banks

are

free

The
write
DATA<31:0>.

data
The

accept write

commands.

stored
MDP

in
the MDP is placed on the NAB as AMCL
also
supplies
a
data
parity
bit,
a
write—-enable
bit,
and a bad-data bit. The data parity bit allows
the
array
board to make a parity check on the write data. If the
array
board detects a data parity error, the data is written into

1-20

NM! FUNCTION<4:0>
NMI ID MASK<3:0>
NMI FUNCT ID PARITY
NMi ADDRESS DATA
I

<31:0>

DATA PARITY

Parity

Oi///’///'
YES

ADFA

PARITY

AMCL BAD

R
ERROR1

NMI

FAULT

DATA

Y
AMBM INPUT
EN<3:0>

WRT

Write data
in MDB.

stored

AMCL DATA<31:0>
AMCL DATA PARITY
AMCL WRITE ENABLE
AMCL BAD DATA

v
Write longword
into seiected
array

bank.

All
longwords
written

4
AMCL CMD<3:0>
AMCL ADDR<25:4>

BMAR DATA

RDY DONE

For

longword

each

written.

SCLD-350

Figure

1-5

Write

Data

Cycle

1-21

Flow

Diagram

the
arrays
but
1is
marked
as
bad
data.
The write-enable bit
specifies whether the associated longword is to be written or not.
Occasions
when a longword is not to be written is for an unwanted
longword during a sort-of-write operation (Section 1.4.3); or when
a double- bit error is encountered during a masked write operation
(Section
1.4.5.4). The bad-data bit (or a write-data parity error
in
the
array
board)
specifies the associated longword as being
bad.
The
bad-data
bit is set in any data cycle in which the MCL
detects
a
data
parity
error or a function/ID/MASK parity error
(Section
1.4.5.2), or when the DFA detects missing write data and
asserts ADFA BAD DATA

the

MDP.

If
the
function
being
executed
1is a longword write, the board
asserts
BMAR
DATA RDY DONE to inform the MRM that the array bank
just
written is ready to accept another command. The operation is
now finished.
If
the
function being executed is a multiword write, the MRM reasserts
the longword write command and address for the next array
bank.
The
next
1longword of write data from the NMI is processed
and
supplied
to
the
array
board
along
with the data-parity,
write-enable, and bad-data bits. The process repeats until all the
longwords are written.

BMAR
DATA
RDY
DONE
asserts
for
each longword of data that is
written. The MRM does not have to received BMAR DATA RDY DONE from
the
first
1longword
write
command
before
it
1issues
a second
longword
write
command because the second longword will be going
to
the
next
array bank. In an NMI octaword write operation, the
MRM
will
have
initiated
four
longword write operations to the
array
board
before it receives the first BMAR DATA RDY DONE. The
MRM
knows the first BMAR DATA RDY DONE signal asserted is for the
first longword write operation.

1.4.5.3
Read
and is used in

Longword
by
the
into two

-- Figure 1-6 is
conjunction with

a flow diagram of
the block diagram

a read operation
(Figure 1-3).

and octaword reads are the only read operations performed
array
boards. Hence, the MCL must convert a hexword read
octaword reads for the array board.

For
a read operation, the array board asserts it BMAR SEND NO CMD
line to lock-up the board until the read operation is completed. A
read
of
the
array
board
executes in two segments: reading the
arrays
and
taking
the data. The two segments do not necessarily
follow
each
other
immediately,
so
when
the
first segment is
initiated
(reading the arrays) all new commands to the board must
segment

[ ]

second

the

until

poert

out

locked

executed.

G
EMAR SEND NO CMD

Arréy board is

locked

up.
|

v
Read

array

board.

v
BMAR DATA RDY DONE

Data

array

available

board.

AMCL READ BD SEL

Select board to
take read data.

Array board negates
H;s send-no-command
ine.

SCLD-341A

Figure

1-6

Read

The

array

DATA

RDY

the

data

the

data,

asserts

the

board

send

AMCL

then

READ
The

DATA<31:0>)

MDP

found,
FB

1is

and

data

ARB.

then

the

taken.

board's

When

negates
NEW

ECC

ECC
DFA

check

arbitration

the

READ

array

BMAR
a

read

the

for

logic

1-23

data.

the

read

NMI

asserts

BMAR

been

read

and

ready

take

line

prepare

read-selected

CMD

the

line.

read

data

The

MRM

the

(BMAR

DATA<38:32>).

DFA

"good

the

SEL

1longword

(BMAR

the

board

SEND

then
have

MRM

transfer

bits

generates

arbitrate

When

the
to

and

arrays

sent

data

(Sheet

the

AMCL

its

DATA

Diagram

the

that

consists

longword
The

Flow

read

MRM

data.

DRIVE

seven

proceeds

When

data

performs

the

DATA<31:0>).

and

SEL,

the

BMCL

read

Cycle

proceeds
inform

available

asserts

MDP.

The

board

DONE

Data

CPU

ECC

feedback
data"

the

(BMDP

function

asserting
grants

error

data

code

NMI

MEMORY

NMI

the

f—

BMCL DRIVE NEW DATA
Take

from

read

array

data

board.

BMAR DATA<31:0>
BMAR DATA<38:32>
T

Ir Pertorm ECC check. 1

4
NMi LCPU MBM INTR
NMi RCPU MBEM INTR

Single

BMDP FB DATA<31:0> B

bit

error

A4
# YES

Set
for

NMI function
good read

data.

BMDP FB DATA<31:0>
AMDP DBE

BMDP FB DATA<31:0>
AMDP BIT CORRECT<2:0>

Correct

Double

bit

error.

read data.

Set NMI tunction
bad read data.

for

|
First
longword
read

NMI MEMOHRY ARB

v
NM|
NMI
NMiI
NM!
NMI

ADDRESS DATA<31:0>
DATA PARITY
FUNCTION<4:0>
ID/MASK<3:0>
FUNCT 1D PARITY

All
longwords
read

NMI MBVORY HOLD

|
SCLD-341

[

[\]

Flow Diagram

|-.-J

Read Data Cycle

1-6

Figure

(Sheet

2 of

memory,

asserts

output

lines

onto

the

The

read

data

The
function
code
"read-return" data.

The
ID
of the
MASK<3:0>).
command/address

function/ID parity

PARITY).

data

NMI

parity

MCL

NMI.

BUS
The

EN.

NMI

MCL

DFA outputs

(NMI

ADDRESS

bit

generated

BUS

enables

the

DFA

are:

DATA<31:0>).
in

the

specifying

DFA

(NMI

the

DATA
data

commander that requested the
(The
1D
was
stored
sequence, Section 1.4.5.1.)

bit generated

the

PARITY).
as

good

data (NMI ID
during
the

DFA

(NMI

FUNCT

If
the
function
taken
off
the
NMI
was
a longword read, the
operation
is
finished.
If
the function taken off the NMI is an
octaword
read,
the
DFA asserts NMI MEMORY HOLD to hold the NMI.
This
eliminates
the
need
of re-arbitrating for the NMI for the
second, third, and fourth longwords of read data.

The MRM holds the array board read-enabled by keeping AMCL READ BD
SEL
asserted, and then re—-asserts BMCL DRIVE NEW DATA to take the
next
longword
of
vread
data
along with its ECC check bits. The
process repeats until all the longwords are read. The NMI function
code
generated for the second, third, and fourth longwords is for
good "read/continue" data.

If a single-bit ECC error is detected during an ECC check, the MDP
generates
correction
bits (AMDP BIT CORRECT<K2:0>) which are sent
to the DFA along with the feedback read data (BMDP FB DATAC31:0>).
The
data is corrected in the DFA and then outputs onto the NMI as
good

read

data.

If a double-bit
the
DFA
along

ECC error is detected, the MDP outputs AMDP DBE to
with
the feedback read data. The DFA generates a

"bad
read
data"
function
code which is placed on the NMI along
with
the
erroneous
read
data
and
the
other NMI signals. The
bad-data
function
code
may
be a read/return or a read/continue
function

code,

the

case may

be.

The
DFA,
sensing the MDP correction bits or the double-bit error
signal
from the MDP, asserts a CPU interrupt on the NMI (NMI LCPU
MEM
INTR and NMI RCPU MEM INTR) to indicate that an ECC error has
been

detected.

1.4.5.4 Masked
Write -- In a masked write opeation, write data is
placed into the MDP during the write-data cycle(s) as described in
Section
1.4.5.2. Data is then read from the addressed location on
the
selected array board and used to overwrite the data stored in
the MDP. The new data is then written back into the array board.

1-25

Figure

1-7

used

conjunction

in
a

masked

following

NMI

1is

flow

write

signals

FUNCTION<K4:0>

NMI

ID MASK<3:0>

NMI

ADDRESS

NMI

DATA

FUNCT
1ID
ID/mask fields

the

data

NMI,

the

NMI

FAULT

PARITY

DATA)

the

when

the

bad-data

write
MDP

can

data
as

AMRM

this

The

MRM

which
when

then

all

marks

for

the

set

the

data.

MRM

specific

ECC

line

check

1is

later

MRM.

masked

stored

write

are
in

command

and

bits

the
to

ADFA

BAD

found,

the

MDP

uses

read

data

into

the

stored

write

into

the

The

data

arrays,

the

written

diagnostics.
through
is

the

stored

data

DFA

the

operation,
in

the

where
MDB.,

the
the

MDB

process

and

their

array

board

DATA RDY
asserts

DONE
the

selected

then
MRM
an

AMRM

LZAL214ANL

MDB,

data.

BMAR
then

line

ECC

check

transfer
is

the

made

WRT EN<3:0> fr
thereby overwriting

AMRM

FB WRT

EN<3:0>

derived
from the mask field(s) stored in the MRM. Hence,
data overwrites write data according to the mask field.

execute,

ADFA MASK<3:0>

data

MDP where

the

allowed

data

the

DFA asserts

MRM,

drive-new

the

from

and

{(AMCL

stored

the

bit

data

MDP.

passes

the

parity

the

by maintenance

from

MCL.

bit

bad.

write

the

The

and

bad-data

written

data

DATA<31:0>)

read

data)

function

write

ERROR1

the

input
of

the

data

detected,

error

bytes

the

operation

longwords

1issues

and

longword

write

function

PARITY

ADDR<31:0>.

are

select

places

(write

the

data

the

asserts
its
BMAR SEND NO CMD, and
the
arrays
have
been
read.
The
data

over

function/ID/mask

the

EN<K3:0>

function

write

checks

ADFA

MDP

ADDRESS

bit

error

and

fields

read

and

1-3).

commander

is transferred to the MRM as
use in overwriting the write

read-board

the

a multi-longword

mask

the

write—-data

data

WRT

until

associated

write

INPUT

parity

analyzed

(NMI

the

parity

the

bit

operation

(Figure

field

write

DATA

1is

repeats

mask

The

ADFA

ID MASK<3:0>
is stored for

command

and

NMI

asserted

the

bit

causes

however,

The

fields.

NAB.,

specifies

the

that

the

DFA performs

ERROR1

cycle,

PARITY

function/ID/mask

data

DATA<31:00>

parity

masked-write

diagram

NMI:

NMI

the

NMI

the

block

operation

FUNCTION<4:0>

MDP

the

Using

diagram of

with

the

1is

read

y
NMI

FUNCTION<4:0>

NMi iD MASK<3:0>
NMI FUNCT ID PARITY
NM! ADDRESS DATA
<31:0>

NM!

DATA

PARITY

Parity

OK
y

YES

ADFA PARITY ERRORt

NMI FAULT

A
AMCL BAD DATA

AMRM INPUT

rite data
MDB.

WRT

ADFA MASK<3:0>

stored

EN<3:0>

Mask field
in

MARM.

All
longwords
stored in
MDB

‘ YES
BMAR SEND NO CMD
Array board
locked up.

v
Read

array

board.

v
BMAR DATA RDY DONE
Data
array

avaifable
board.

AMCL READ BD SEL
Select board to
take read data.

Array

its

board

negates

send-no-command

line.

SCLD-343A

Figure

1-7

Masked

Write

Data

Cycle

Flow

1-27

Diagram

(Sheet

\/
BMCL DRIVE NEW DATA
Take read

from array

data

board.

¥
BMAR DATA<31:0>
BMAR DATA<38:32>

Perform ECC check.J

ECC

YES

error

4///////,

[T NMI LCPU MEM INTR |

| NMI RCPU MEM INTR|

Single

bit error

.
Y

{ Double bit error.J
:

h 4

AMDP DBE

| YES

BMDP FB DATA<31:0>

AMDP BIT CORRECT<2:0>

gfig;&g :h‘AtCL V\',TRI':TSE

Correct read data.

longword will not
be

;

written.

]

ADFA DATA ADDR<31:0>

V‘

Corrected read data.

AMRM FB WRT EN<3:0>

Overwrile dala

AMRM INPUT WHRT EN<3.0>

stored

_Overw’;ite

MDP.

‘&

!‘

data

stored

All

longwords
read

AMCL BRD SEL
AMCL CMD<3:0>

AMCL ADDR<25:4>
AMCL CMD ADDR PAR

Parity

~
|

Write

YES

masked

data

into memory arrays.
(Figure 1-5)

[

BMAR CMD ADDR
PAR ERR

AMRM INT ERR

Abort operation.

Y
NMI
NMI

LCPU MBM INTR
RCPU MEM INTR

o
SCLD-343

Figure 1-7

Masked Write Data Cycle Flow Diagram (Sheet 2 of 2)

1-28

this

the

a multiword

read

data

operation,

taken

from

the

process

array

repeats

until

board

and

entered

from

the

MDP

MDP.

The

MRM

poard
and

then

with
if

transfers

write

false,

the

MRM

write-longword

command,

MDP

address

outputs

made.

arrays

the

parity

described

single-bit

array

board,

the

DFA,

along

The

data

longword

the

MDP,

via

bytes

EN<3:0>.

The

MRM

the

DFA

and

path

from

code

AMRM

When

the

negated

corrected

stored
into

the

MDP

Consequently,

write

data

error

EN<3:0>

will

ECC

error

DBE

double-bit

the

NMI

1.4.6
The

following

There

with
The
data

that

Four-Megabyte
MAR4s

four

NAB

the
to

then

the

CORRECT<2:0>).

wrapped

overwrites

bits

AMRM

INPUT WRT

associated

mask

signals,

thus

field.

data

write-enable

read

bit

from

(AMCL

the

WRITE

MRM

then

proceeds

bad

read

data,

just

will

have
in

Array

there

its
the

the

sensing

error

signal

module,

into

data

DFA,

array

has

Board
1lines

were

the

error.

longword(s)

bank(s).

for

CPU

bits
This

analysis

correction

the

been

using

write-enabled
array

array

asserts

DATA ADDR<31:0>

the

mask

corrected

the

enabling

the

back

where

ADFA

applies

read

bits

interrupt

detected.

(MAR4)
on

the

NAB

except

for

the

signals:
BRD

READ

SEL

BMAR

SEND

CMD

BMAR

DATA

RDY

eight

SEL

DONE

1lines

connected

carries

between

from

DATA<31:0>)

BIT

had

longword

signal,

ECC

Memory

AMCL

line

the

common

the

data

written

AMCL

are

one

code,

error

into

The

error

occurs,

check

MDP with

erroneous

AMDP

the

The

1longword.

into

array

checked

parity

data

and

via

the

mask

written
not

indicate

the

written

enabling

according

with

line

(BMDP

path,

EN<3:0>

negates

stored

WRT

found

MDP

(AMDP

DFA

inputing

the

ADDR<31:0>

via

preserves the original
maintenance routines.
When

bits

read

INPUT

where

longword

the

DFA.,

CMD

data

longword

correction

double-bit

and

data

containing

board

masked

that

data

WRT

in
the

DATA

1.4.5.2.

found

routes

ADFA

the

error

associated

overwrite
the

the

board,

ENABLE)

the

AMRM

double-bit

array

senses

the
the

overwriting

the

Section

SEND

of
the

the
board's
select line,
command/address parity bit.

the

OK,

MDP

the

specific

asserts

and

data

BMAR

with

new

The

checks

error
the

the

command.

all

into

board
the

MCL

the

each

NAB

for

each

MAR4

slot

the

select signals,
and the MAR4s.

1-29

the

above

signals

backplane.

command/address signals, and
Separate data lines exist on

the

NAB

for

read

data

and

for

write

data.

Thirty-two

write

data

lines carry write data from the MCL to the MAR4. Thirty-nine*
data lines carry read data from the MAR4 to the MCL.
The

MAR4

board

has

megabyte
to

the

The

and

MCL

total

memory

memory.

MAR4's

longword

has

four

The

internal

seven

ECC

performs

storage

array

capacity of
banks with each

array

banks

data

bus.

check

bits.

three

have

bits

The

command

four
bank

39-bit

opertions

megabytes.
containing

wide

consists

read

MAR4

The
one

common
of

I/O

32-bit

board.

These

are:

Longword

check
®

wrlte

into

one

bits

read

bits

Octaword

The

read

all

check

the

addition,

which

1is

basis.

refreshes

during

Figure

1-8

1is

operations.

the

1.4,6,1
and

the

The

MCL

BRD

SEL

AMCL

are

Figure

performed.

32-bit

AMCL

1longwords

that

provides

refresh

backup

periods

simplified
it along

The

seven

ECC

and

data

from

MCL

each

can

their

read

bank),.

from

any

from

the

order.

the

For

first

transferred

example,

longword
are

from

order.

refresh

clock

the

MAR4

boards

logic to refresh the arrays on a
1is
provided
to maintain array

power

interruptions..

flow
with

ECC

transferred

wrap-around

bank

and

longwords

the
are

seven

banks,

board.

from
in

longword

Battery

diagram of MAR4 write and
the block diagram (Figure

read
1-3)

discussion.

C/A parity

function

and

Selec

CMD<3:0>

logic.

MAR4

(one

transferred

the

assertlng

selects

and

banks.

array
data

selects

from
banks

MAR4

four

banks

MAR4

operation

bits

longword

array

data

three

MCL

Refer

following

MAR4's

the

longwords

periodic

Reads

three

the

wused

data

array

longword

MAR4's

other

transferred,

banks

the

Reads

longword

The

following

four

first

bank.

from one

associated
from

Writes

and

bit

the

a
on

the

MAR4

the

MAR4

1is

Command/Address

board-select

by
by

four-bit

specifying
1is

command/a ddress,

ECC

the

AMCL

MAR4

applied

command

BRD

1-30

bits,

initi ates

SEL

control
to

line.

AMCL

logic.

the

fields.

the
operation
write bit which

check

its

the

command

bits

and

MCL

the

asserting
enabling

illustrates

longword

The

NAB.,

1-9

CMD<3>

—-

signal,

check

j9)

MAR

AMCL

control

CMD<3:2>

that
1is
to
be
is negated for a

(

STAiRT j

AMCL BRD SEL --- Selacts MARA.
AMCL CMD<3:0> --- Specifies operation
and selects
AMCL ADDR«<25:4> --- Address in array
bank
AMCL CMD ADDR PAR --- C/A parity bit.

Perform
addren

YES

4
[_* aMcL DATA<a1:05

bank.

command/
parity

Write

[Femwo o]

4 INT DATA<31:0»
Write data on
internal bus

DR WHT DATA DIS ---

Disable data.in

path

4 READ SELECT ---

4 READ BANK EN<X»

from

NAB

internal

bus.

Enable data-out

path

bus

from

internal

NAB.

Enablo
?elected

GM&%%FC

rntern.al

4 BMCL DRIVE
NEW DATA

[ 4nTR DATA<38:32;I

[€-T

bus.

Octaword
read

$ DATA OUT CLK

$ LOAD DATA<X>
Load

write

data

L bank.

lbmok selected

Read selected

L
BMAR

YES

’

data

Increment READ
BANK EN<X>.

Octaword .
read

4 BMAR DATA RDY

Write data into
selected array.

read
NAB.

BMAR DATA<31:0>
BMAR DATA<38:32>

Data from selected
bank on intarnal
bus.

negated

$INT DATA<31:0
INTR
DATA<38 32>

CMD ADDR PAR
ERR or write-enable

bit

]

Transfer

Fourth
longword

DONE

transferred to
NAB

[ 4 BMAR DATA RDY

DONE

% AMGL READ BD SEL

SCLD-344

Figure

1-8

MAR4

Read/Write

Flow

Diagram

AMCL CMD

<03

00>

Write ——J
Octaword

Read

Starting Address{
SCLD-351

Figure

1-9

MAR4 Command Fields

write and asserted for a read*. AMCL CMD<2> is the octaword read
is asserted for an octaword read and negated for a
bit which
longword read. AMCL CMD<1:0> 1is the starting address which
specifies the bank to be accessed for a longword read or write.
For an octaword read, it specifies the first bank to transfer its
data

the

MCL.

AMCL ADDR<25:4> is the array address tc be accessed.

AMCL CMD ADDR PAR is a parity bit on the command/address.

The command/address and the command/address parity bit are applied
If a parity error is
to a command/address parity checker.
detected, BMAR CMD ADDR PAR ERR is asserted back to the MCL which
aborts the operation and asserts the memory-interrupt lines on the
NMI.

1.4.6.2 Write Operation -- If a write operation is executing, the
MCL places the write data (AMCL DATA<31:0>) on the NAB. The write
INT
internal data bus as
is coupled onto the MAR4's
data
DATA<31:0>.

The

data is applied to all of the array banks and to

an ECC generator. The ECC generator generates 7 ECC check bits on
the data and applies them to the banks as INTR DATA<K38:32>.
AMCL ADDR<25:4>

is applied to all four banks.

The MAR4 control 1logic responds to the input write command by
asserting LOAD DATA<X> where X is the number of the bank selected
by the command starting address. LOAD DATA<X> loads the write data
into the selected bank but does not
(longword and check bits)
write

The

the

state

data

into the

array.

write bit is inverted on the MAR4 board where its asserted
specifies a write command.

1-32

After
the
write data is loaded into the bank, it is written into
the array providing that there was no command/address parity error
and
the
1longword's write—-enable bit is set. If a command/address
parity
error
(negated), no
A

did

write-data

prevent

occur,
or
written.

data

parity

the

write-enable

bit

1is

not

set

data

error

from

detected

being

written

the

but

array

board

will

mark

will

not

bad

data.

The
control
1logic
then asserts BMAR DATA RDY DONE on the NAB
inform
the MCL that the write operation has been completed and
can
1issue
a new command to the array bank. BMAR DATA RDY DONE
asserted

whether

not

the

write

data was

to
it
is

written.

1.4.6.3
control

Read
Operation
=-- If a read operation is executing, the
logic asserts the MAR4's BMAR SEND NO CMD line on the NAB
to inhibit the MCL from issuing any new commands to the MAR4 until
the
read
operation is complete. A read operation executes in two
segments;

read

the

array(s)

and

transfer

the

read

data

to the MCL. The two segments do not necessarily follow one another
immediately.
After
the array(s) have been read the MCL will take
the read data when it is ready. BMAR SEND NO CMD serves as a "read
lock" signal between the two segments. It asserts during the "read
array"
segment and inhibits the MCL from issuing any new commands
to the MAR4* until the "data transfer" segment is started.
The
MAR4
control
1logic
responds
to
the input read command by
asserting
READ
BANK
EN<KX>
where
X
1is
the number of the bank
selected
by the command starting address. READ BANK EN<KX> enables
the output of the selected bank onto the MAR4 internal bus.
The
array
progress.

banks(s) are then read according to the type of
If
a
longword read is executing, the selected

read
bank

in
is

read
and
the data longword and
to
the
1internal
bus
as
INT
respectively.
If
an octaword
are
read
and
the
data from
internal
bus.
The
data read
held within the banks.
The

control

inform

and

the

can

1logic
MCL

start

then

that

the

"data

associated check bits are coupled
DATA<K31:0>
and
INTR DATA<K38:32>
read is executing, all of the banks
the selected bank is coupled to the
from the other three array banks is

asserts

BMAR

DATA RDY

DONE

"read

array"

segment

has

been

transfer"

segment

Note
that
a command/address
operation within the MAR4.

parity error

to other

The

MCL may

issue

commands

1-33

MAR4

when

has

the

ready.

no effect

boards

NAB

completed

the

NAB.

read

"data transfer" segment by asserting the
the
initiates
MCL
The
MAR4's read board-select line (AMCL READ BD SEL). The MAR4 control
AMCL READ BD SEL by asserting DR WRT DATA DIS
to
responds
logic
DR WRT DATA DIS disables the data-in path from
SELECT,
READ
and
READ SELECT enables the
bus.
internal
MAR4's
the
to
NAB
the
internal bus to the NAB.

data-out path from the

DRIVE NEW DATA to the control logic
BMCL
asserts
then
MCL
The
CLK. DATA OUT CLK transfers the
OUT
DATA
asserts
turn
in
which
to the NAB via flip-flops. The
bus
internal
the
from
data
read
appear on the NAB as BMAR
bits
longword and associated check
data
DATA<31:0> and BMAR DATA<38:32> respectively.

OUT CLK increments READ BANK EN<KX> within the
DATA
addition,
In
1logic to enable the read data (if any) from the next bank
control
out onto the internal bus. This function is used for octaword read
operations.

longword read operation is being executed,

the operation is

complete.

read
octaword
an
If
DRIVE
BMCL
re-asserts

MCL
the
executed,
Dbeing
1is
operation
DATA to transfer the second longword
NEW

(and its check bits) out to the NAB. DATA OUT CLK again increments
READ BANK EN<X> to couple the third longword (not necessarily from
the

third bank)

to the

internal bus.

BMCI DRIVE NEW DATA continues to assert causing READ BANK EN<KX> to

step

through

all four array banks taking a data longword and its

associated check

bits

from each bank.

When all four banks have been read,

the octaword read operation is

}

-4

complete.

CHAPTER
MEMORY

The

MCL

(memory

discussed

controller)
is
divided
Chapter 1. The three areas are:

The

DFA

(DAD,

The

MDP

(memory

°®

The

MRM

(MSC,

Overviews

the

DFA,

and

respectively.

2.9

description
description

2.1
The

of
of

the
the

FUNK,

and

data

MSCl,
MDP,

MCAs

RSC,

and

MRM

°®

DAD

the

NMI.

FUNK

NMI,

decodes

function:

confirmation
°

ARID

parity,

the

NMI,

and

Command/Address

Cycle

command/address

cycle,

the

NMI

the

NMI

ID MASK<3:0> —-- commander's

FUNCTION<4:0>

FUNCT

1ID

commander

PARITY

NMI

2-1

2.5,

general

detailed

and

address

field

the

NMI

faults.
data

and

commander

following

NMI

function

1ID

fields,

interrupts

placed

and

the

NMI

field

and

function

parity

generates

command

below.

function

and

2.1,

commander.

the

Processes

mask

read

the data

field,

the

2.1.1

Sections

defined

generates

arbitration/ID:

processes

for
requests.

are

Interfaces

and

can

is followed
respective area.

function

code,

areas

MCAs)

given

areas

1Interfaces

the

arbitrates
busy

are

the

DFA OVERVIEW (Figure 2-1)
MCAs that make up the DFA

data/address:

MASC

overview

three

MCAs)

and

three

Each

used

into

(MCL)

path)

These

MCL.

ARID

CONTROLLER

bit

for

function

ADDRESS DATA<31:0> -- memory address

NMI DATA PARITY -- address parity bit

The five-bit function field (NMI FUNCTION<4:0>) is applied to a
parity generator in the FUNK where parity is generated for the
function field. The generated parity bit (CTRL GEN PARITY) 1is
applied to a parity checker in the ARID.

The function field specifies the commanded function as shown in
Table 1-2. The function field is decoded in the FUNK function
logic, which outputs a three-bit command code (BDFA CMD<2:0) and a
two-bit size field (BDFA SIZE<1: 0>). The three-bit command code
spe01f1es a read or write operation, a memory or CSR access, and a
as shown in Table 2- 1.

r masked operation,

Command Code

Table 2-1
BDFA CMD

Command

<21 0>
- O HOMQOMF
O

Read memory
No

Read
No

CSR

Write memory

Write memory masked
Write
No

CSR

-—-———--- Non-masked/masked
T Yy
—————— Memory/CSR
yf
—————————— Read/write

The

function

logic uses address bit 29

(NMI ADDRESS DATA<Z29>) to
—

— o

e—

determine if the command function is to memory or to a CSR.

The two-bit size code specifies the size of the operation as shown
in Table

2-2.

Table 2-2
BDFA SIZE

Size Code

Size

0O
0
1
1

O
1
O
1

Longword
Octaword
Quadword
Hexword

2-2

S
L1

N
N MGL

ADEA

QUTRUT

)

————W

8 vewe

}m- 1)

ADORESE

DATA<1:0>

—

{

lJ
°

ADEA DATA

ADDR<)1.0»

i aconars

’

ADFA

NWM_DEAD

e v

o mas

822

oo
DATA<29>

flFflh‘a:u»

PAR

—®(Fla

pilitic]

)

(f18

;)

ADEA

outPuT

}(FIG. 21

NP DOE

A READ CMO<1:05

—G"— FEAD
FUNCTION

BN NEW LW

CTAL OUT PARITY.

FUNCTION<4 Qs
PAR

CTR. GEN PARITY

(F18. 2-33)

INBUT DATA

BOFA CMD<2:8>

DBATA CYGLE

FUNCTION
Loaic

DATAgS:

BOFA SIZE<1:

START T NEW CMD

(F1a.

2.18)

> ) (Fia. 2-33)

| FumcTion 1NvaLlD

cuo.zo
>.

INTERLOCK BUBY]

UNLOCK | INTERLOCK

NME

SLOW

COUNT EN

NMi

ADEA

TIMECUT

TIMEOUT

LoGic

¢ SONFIRMATION
10>

ADFA

[ conrimmaTIioN

PARITY ERROR?

] LOGIC
NAK_MEMCRY BUSY

—

@ FAULT

FALLT

LOGKS

PR 305
DETECT

[

— >—>

NW_DEAD

ADEA_BAD DATA

-y

o
Loac

svs

FAULT

»(Fia. 2-33)

;
‘

FUNK

> (FIG.

2.18)

ADFA

PARITY ERACRP

ADFA

PARITY ERRCR1

P(FIG. 2-186)

ADEA_CEN
PARITY<3:0>

ADEs

OUTPUT ENAILE

TM
CHECK

ARIO
Al

CTP, PASITY EPR

S uask e
<

1D PAR

g Dbttt |

A
T

CTAL
QUT_PARITY.

PAR
it

cTAL

GEN_PARITY

Loaic

1D_PARITY.

PARITY

A DATA

PARITY
DATA PARITY EPR

NMI_FUNCT

—

BOFA OUT

Laa¢

‘

AOEA

fi
i

e
|

BTORE

;

MEMCRYY HOLD,

ILU‘

%vma

2.°8)

(F1G. 2.33)

N
<

{F1G.

LBEAD CMD<3-0a

MEM INTRPT

< Ao INTHeT
N

MEADMEOUT

Looie | [¢—4ME DX

(Sic

—iasiws

Figure

command
the

code

command

(—-——

BusY

ARID

\/l

The

and

size

2-1

DFA

Block

field

are

2-3

function.

sent

»—

(Fig. 2-33)
(Fig.

2-18)

8CLD-488

Diagram

the

MRM

for

execution

the function logic detects an invalid function code, it aborts
operation
and
asserts
FUNCTION INVALID to the confirmation
logic
which
will assert a "no acknowledgement" confirmation code
(Table
1-4)
on
the
NMI
during
the
confirmation
cycle
(the
confirmation
c¢ycle
is the second cycle after the command/address
cycle;
see
Table
1-3
and
Tables
1-5 through 1-9). If a valid
function is decoded and no parity errors are detected (ADFA PARITY
ERRORZ2 false), START NEW CMD is asserted to the confirmation logic
causing
it
to
place a "command accepted" code on the NMI during
the confirmation cycle.
the

If
a
read interlock command is decoded, INTERLOCK is asserted to
the
timeout
logic
which
then starts counting NMI SLOW COUNT EN
ciocks
from the NMI. When a write uniock command is received, the
function logic asserts UNLOCK which resets the timeout logic. If a
write unlock command is not received within approximately thirteen
microseconds
from
a
read
interlock
command, the timeout logic
asserts
to

ADFA TIMEQOUT

assert

interrupt

the
on

If
a
read
interlock
interloc
command
15
received
the

but

function

asserts

INTERLOCK

logic

places

during

the

Another
which

command

unlock

aborts

BUSY

the

ARID

causing

command

has

new

not

read

confirmation
busy"

been

received

interlock

logic.

The

confirmation

yet),

command

and

confirmation

code

the

NMI

cycle.

output

the

wused

inform

1is received while a previous read
({previous
read interlock comman

the

"interlock

confirmation

logic

NMI.

pending

write

logic

interrupt

the

FUNK

function
the

logic

MRM

that

is
a

BDFA

new

NEW CMD

command

EARLY

has

been

received.
The

commander

it
1is
stored
executed,
the
and
The

placed

commander

parity

1is

(NMI

in
the
commander
the

NMT

along
also

generated

MASK<3:0>)

1ID
store
ID will be

with

the

applied

the

applied

read

1ID

logic.
popped

the

and

the

ARID where

When a read command is
from the ID store logic
data.

ARID

parity

checker

combined with

the

where

function

parity

bit
from the FUNK (CTRL GEN PARITY). The composite parity
bit
1is
compared
to the function-ID parity bit from the NMI (NMI
FUNCT
ID
PARITY) and if an error is detected, CTRL PARITY ERR is
asserted to the ARID fault logic and to an OR function outside the
ARID.
The ARID fault logic asserts ARID FAULT DETECT which causes
SYS
FAULT
DETECT
to
assert to the fault logic in the FUNK. The
FUNK

fault

When

the

asserts

FUNK

abort

logic

then

function

ADFA

the

PARITY

code

the

ERROR2

logic
on

NMI

outside

operation.

confirmation

confirmation
(O B DR X

asserts

the

ADFA

ARID

the

will

during
A s L. L

2-4

the

NMI.

receives

CTRL

FUNK

PARITY

which
NMI
18 B A 3

FAULT

function

ERROR2

place

the

also

"nc

PARITY

logic

ERR,

causing

applied

the

acknowledgement"

confirmation
R
N
L L
S U
S L

cycle.

The

memory

address

where

1t
passes
ADDR<31:0>.
ADFA
stored
are

the

sent

(NMI

ADDRESS

through
DATA
MDB

the

DATA<31:0>)

a mux

and

ADDR<31:0>

(memory
MRM

data

where

outputs

sent

buffer).

they

DATA

selects

operation.
used

ADDR<K31:0>

1is

primary

and

the

select

ADFA

PRM

select

the

BNUM<2:0>
array

longword

and

octaword

transfer

alternate

numbers

the

array

DEC

RAM

PARITY)

MRM

parity

check.

the

Parity

1is
GEN

the

memory

(NMI

latched
DATA

data

NMI

operation

Write

Data

cycle(s)

operations.

For

cycle

For

the

case

ERR

and

ADFA GEN
The
to

the

ARID
in

parity

parity
an

the

function/ID

address

detects

results

for

PARITY<3:0>

against

NMI.

sent

parity

bit

checker

address

fault

logic

assertion

parity

which
of

NMI

error.

asserts

and

the

case

"no
of

acknowledgement"
a

function/ID

confirmation

parity

error.

Cycle(s)

the

command/address

operations,

only

cycle,

the

)

NMI

FUNCTION<4:0>

NMI

MASK<K3:0>

FUNCT

(ADFA

use

write-data

mask

select

DAD

1-5,

NMI

for

bit

confirmation

longword

byte

RAM

alternate

the

1-3,

and

used

the

storage

Tables

commander.

are

octaword

outputs

(see

second

MDP

operations,

occurs

octaword

and

ERR
of

first

is
for

the

checker
This

and

address

output

PARITY

command

number

primary

decode

where

the

BNUM<2:0>

the

they

sent

checked

then

PARITY

for

operations,

the

ALT

DAD
DATA

it is
<3:2>

bank

decode-RAM parity
the

the

ADFA

RAM

for

board

for

The

multi-longword

NMI

DETECT.

aborted
as

Write-data
occurs.

parity

1logic

NMI,

from

the

from

decode

write

ADFA

where

addition,

and

MRM

accessed.

and

operation.

memory

all

only

array

board

primary

for

used

the

DATA

being
the

where

the

operation.

output

where

function

2.1.2

FAULT

addition,

for

also

asserts

the

code

ARID

FAULT

PARITY)

the

ARID

checker

asserts

FUNK

buffer.

DATA
1in

read

generated

PARITY.

error,

hexword

PARITY<3:0>

parity

bit

and

sent

array

operations,

number

board(s)

ADFA

read

are

applied

board

hexword

board

transfer

board

also

alternate

DAD

to the MDP where
Data-address bits

accessed.
ADFA

applied

the

PARITY

and

for

all

write

write-data

cycle

than

one

write-data

the

NMI

1-6).

following

command

cycle
one

placed

the

field

and

function

byte

mask

parity

2-5

bit

for

function

NMI ADDRESS DATA<31:0> -- write data

NMI DATA PARITY -- write data parity bit

A function parity bit (CTRL GEN PARITY) is generated for the
function field as was done during the command/address cycle.
For each write-data cycle, the FUNK function logic outputs BDFA LD
INPUT DATA to the MDP to load the associated write data into the
memory data Dbuffer, and to the MRM to load the mask field into

mask store logic. It also outputs WRITE DATA CYCLE to the NMI dead
logic for wuse in single-bit error correction during masked write
operations

(see Section 2.1.7).

The byte mask (NMI ID MASK<3:0>) is applied to the ARID and then
output to the MRM as ADFA MASK<3:0> where it is used for byte

h
4+

selection in masked write operations.

Parity 1is checked on the byte mask and function field just as in
the command/address cycle. The function parity bit (CTRL GEN

1is sent from the FUNK to the parity checker in the ARID
PARITY)
where it 1is combined with the parity bit generated from the byte

mask. The composite parity bit is compared to the function and
byte mask parity bit and if a parity error is detected, CTRL
PARITY ERROR asserts to the fault logic in the ARID and to the OR
function outside the ARID. The fault logic causes an interrupt on
the NMI. The OR function asserts ADFA PARITY ERRORI1 to the MDP
where it causes the bad-data bit to assert. Note that the write
operation is allowed to continue as opposed to the command/address
cycle where a function/commander 1ID parity error aborted the
operation.

write data (NMI ADDRESS DATA<31:0>) is routed through the DAD

The

(via a mux) and sent to the MDP as ADFA DATA ADDR<31:0>. Parity is
generated on the write data and sent to the MDP as ADFA GEN
PARITY<3:0>.
in

the

The write data and parity bits are stored in the MDB

MDP.

As in the case of the command/address cycle, parity bits ADFA GEN
PARITY<3:0> are generated on the write data and sent to the parity
checker where it is checked against the write-data parity bit NMI
DATA PARITY. If the parity checker detects a data parity error, it
asserts DATA PARITY ERR which causes a fault on the NMI via the
ARID

and

FUNK

fault logic. In addition, DATA PARITY ERR asserts

ADFA PARITY ERROR1 to the MDP where it causes the bad-data bit to
assert as in the case of a function/mask parity error. Note that
the write operation 1is allowed to continue as opposed to the
command/address cycle where a memory address parity error aborted
the

operation.

function 1logic
If th
an octaword
1is,
(that

1in the FUNK, detects missing write data
write operation is executing but the NMI

2-6

commander
SEQ

FAULT

sends

only

DETECT.

SEQ

Asserts

ADFA

had-data

bit

2.1.3
When

First
a

from

read

FAULT

Read

asserting

NMI

arbitration
CMD<1:0>

MEMORY

from

data

specifies

has

that

the

masked

write

the

first

longword

Due

same

time),

next
at

pipelining

BMRM

longword

the

ARID

CMD<O0>

this

won.

The

store

fields.

logic

The

FUNK

for

the

data.
the

ARID,

during

the

also

the

MRM

1logic
and

logic.
causes

the

data

been obtained
of the NMI hy

-—-

the

ARID

and

AMRM

READ

longword

that

arrays.

logic

AMRM

not

READ

data

read

specifies

part

the

data

the

first

not

the

combined

with

the

composite

parity

bit

parity

bit

generator

for

the

read-return

the
and

from

(POP

READ

logic
cycle

and

AMRM

ID<3:0>)

cycle.

parity

NEW
ID

AMRM

first
AMRM

the

read

data.

function

longword

READ

read

which

where

and

code

read

CMD<1:0>

from

data

contains

determines:

NMI.
longword

data

the

applied

bit

output

2-7

operation.

bit

for

CTRL OUT

parity

PAR.

read

double-bit

parity

ARID

generated
as

the

contains

generates

parity

arbitration
the next bus

longword

1logic

the
for

NEW

MDP,

the

outputs

to
NMI

BMRM

bus.

the
the

appear

the

commander

with

will

won

generates

That

PARITY

operation)

CMD<K1>

yet

receives
the

(asserted

for

OUT

the

also

BMRM

the

function

hold

associated

DRE

from

not

output

Whether

CTRL

generated

NEW

command/address

receives

has

applied

field

there

where

signifies

longword

data

which

fault

data has
control

multi-longword

The

read

MDP

for

ARB

the

read

MCL

generation

AMDP

error)

That

field

function

double-bit

The

causing

read-function

The

is
the

ARID

NMI

contributes

asserts

sequential longwords of data at
AMRM READ CMD<1:0> associated with

the

1is

FUNK

AMRM READ CMD<K0>
read operation.

the

once

ID<3:0>

true

HOLD

assert

POP

the

BMRM
LW

from

"next"

stored

NEW

was

MEMORY

BMRM

and

though

specifies

that

read

(processing

(if

CMD<K1:0>

and

NMI

causing

READ

the

data),

folliowing:

operation.

NEW

even

arbitrates

read

data

DATA

via

receives

MRM.

NMI

executing

ARB.

been

the

MCL

which

the

write

the

Cycle

the

logic

does

assert.

Data

arrays,

longwords

DETECT

BAD

operation

the

read

NMI

three
FAULT

for

the

function

PARITY.

generator

the

error.

where

commander

ID.

the
is

The

first

MDP,

longword
BMDP

read

data

DATA<31:0>.

received

The

data

the

DAD

routed

from

the

through

ECC

correction logic where it undergoes single-bit error correction if
necessary.
If
a
single-bit
error
had
been detected, AMDP BIT
CORRECTK2:0>
from
the
MDP will effect the correction in the ECC
correction
logic. From the correction logic, the read data passes
through a mux to become B WRAP DATA<K31:0>.
Read

in
and

data

BMDP

DATA<K31:0>

the
DAD
where
sent
to
the

consolidated

During
NMI),
The

the
NMI

1into

1-8,

cycle

and

parity

generator

BDFA OUT PARITY<3:0> are
the
ARID,
the
parity

also

generated
bits
are

parity

applied

bit

data

parity

generator.

c¢ycle
(when the MCL is granted use of the
is asserted and becomes ADFA OUTPUT ENABLE.

1-9).

bits
1In

single

bus-grant
MCL BUS EN

bus-grant

1-7,

parity
ARID.

also

The

the

first

assertion

read

data

ADFA

OUTPUT

cycle

(see

ENABLE

Tables

does

the

following:
®

Enables

the

gating

first

WRAP

longword

DATA<31:0>

read

out

data

the

onto

DAD

the

NMI

ADDRESS

DATA<K31:0>.

°®

Enables
NMI

the
NMI

Enables

the

NMI

Enables

2.1.4

the

NMI

FUNCT

PARITY.

this

HOLD.

"Next"

Read

ARID

field

Data

subsequent

read

The

read
first

longwords
read data

pass

Parity

)

1is
in

The

read

bit

<0>

output

monitors

AMD

function

code.

first

function

out

the

FUNK

onto

the

NMI

gating

POP

MASK<3:0>.

and

commander

PAR

out

operation,
HOLD

DBE

data

out

the

holds
of

the

parity

bit

ARID

NMI

the

NMI

for

ARID

NMI

cycles:

through
cycle.

generated
the

the ARID onto

Cycles

and

NMI

gating

second

onto

gating

the

out

field

NMI

multi-longword

<cycle

MEMORY

function

the

data

commander
of

bit

FUNCTION<K4:0>.

onto

the

out

data parity
PARITY.

read

NMI

the

ID<K3:0>
®

read
DATA

the

read

data

logic

the

read

the

specify

(RS
R

2-8

data

and

the

NMI

placed

the

cycle.
FUNK

read-continue
to

DAD

senses

function
good

read

code.,

data

command

also

bad

data

The

read

store

data

commander
cycle.

new

senses

cycles

onto

does

not

"first"

Parity

1is

field

and

read

command

"next"

the
pop

generated

placed

new

outputs

the

same

the

first

read

data

until

read

the

commander

<0>
and

NMI

longword

bit

cycles

determine

the

senses

data.

NMI

commander

first

the

and

function

read

data

cycle,

The

arbitration

long

HOLD

the

1is

read

for

the

NMI

Interrupt

logic
ADFA

NMI

DBE

2.1.6

has

AMRM

INT

NMI

ARID

the

fourth

NMI

the

bus
of

cycle.

NMI

cycle.

re-arbitrate

read

interrupt
FUNK

asserted

bus

MCL must

octaword

from

data

the

send

HOLD

data.

when:

timeout

logic

2.1.1.
the

MDP

asserts

error

indicating

uncorrectable

from

power

the

MRM

indicating

failure.

Busy

ARID

generates

NMI

asserts

from

the

any

BUSY

REQ

full

and

cannot

AMDP

(see

Section

AMRM

BUSY

array

the

from

ERROR

AMDP

asserts

MEMORY

for

detected.

parity

Memory

the

NMI

progress,

asserts

been

NMI

generates

Section

asserts

error

logic

1in

output

TIMEOUT

internal

Busy

keeps

the

during
1is

the

discussed
AMDP

logic
needs

false

hexword

2,1.5

MCL

BUSY

REQ

when

MEMORY

BUSY

MDP

when:

indicating

write

data.

single-bit

the

The

error

MDB

MDP

also

detected

2.1.7).
REQ

boards

asserts

are

from

the

and

busy

MRM

indicating

that

commands

the

can

done

accepted.
AMRM

INT

prevent

an
NMI

MEMORY

FUNK

which

during

the

MEMORY

BUSY

ERROR

other

internal
BUSY
will

error

also

place

from

the

sending

MRM.

commands

This

memory

when

exists.
applied

"memory

confirmation
is

asserts

nexus

cycle

confirmation

command

true.

the

busy"

2-9

any

logic

code

received

the

NMI

while

NMI

single-Bit Error Correction During a Masked Write
2.1.7
If the MDP detects a single-hit error in data read from the arrays
the data is sent to the DAD,
operation,
write
masked
a
during
AMDP BIT CORRECT<2:0> correction bits, for errnr
the
with
along
correction and

then returned

to the MDP.

Upon detecting the single-bit error, the MDP asserts AMDP BUSY REO
busy logic which places NMI MEMORY BUSY on the NMI.
ARID
the
to
1is done to halt commands to memory so that the DAD data path
This

corrected

the

for

used

can

the

corrected read data

read

data. NMI MEMORY BUSY is

applied to NMI dead logic in the FUNK, which then asserts ADFA NMI
DEAD to the DAD. ADFA NMI DEAD switches the DAD data mux to select

(B WRAP DATA<31:0>) for the return to the

MDP.

A copy of ADFA NMI DEAD (ADFA NMI DEAD1)

logic

DAD and

is sent to the mask-store

in the MRM to signify that the read data is coming from the
from

not

the

NAB.

logic does not assert ADFA NMI DEAD (nor ADFA NMI
dead
NMI
The
a write operation is in progress as indicated by the
if
DEAD1)

of WRITE DATA CYCLE from the function logic. The write
is allowed to finish before the DAD data mux breaks the

assertion
operation
NMI

through

data path

2.1.8

CSR

the

DAD.

Reads

1in the DAD collects CSR serial and-parallel data from
logic
CSR
FUNK, and ARID; converts it to parallel data; and
MDP,
DAD,
the
during a CSR read operation, The MRM
the NMI
to
it
supplies

detects the operaton as a CSR read and asserts BMRM EN SERIAL READ
SERIAL READ switches a mux to select CSR
EN
BMRM
DAD.
the
to

DATA<31:0>

from

the

CSR logic for the read data path out to the

NMI.

2.2

There

DATA /ADDRESS

are

four

(DAD)

MCAS

identical DAD MCAs that consist of muxes,

ports,

and drivers which pass data to and from the NMI. Each DAD carries
32-bit data/address. A two—-bit mode
the
an eight-bit slice of
is applied to each DAD to specify its byte position within
field
longword. This allows the MCAs to be physically identical but
the
logically. Areas where the DADs are logically
slightly different
different are noted in the block diagram description.

1is a block diagram of the DAD MCAs with all four DADs
2-2
Figure
The four data slices have been
represented on the diagram.
total bit representation of the signals (for
combined giving
the NMI ADDRESS DATA bits are the <31:0> longword rather
example,
than the <7:0> byte processed by a single DAD MCA).

eight
are
There
DAD
the
through
names

used

1in

forming the various data paths
1in
used
muxes
MCAs. The block diagram keys the muxes to their
the

text.

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Figure

2-2

DAD

M
M
TA

WOR

SERALPARAUEL

Block

[2V-B 1)

Diagram

(Sheet

(—*P(FlGS.2-6,2-15)
A

NMD

| UNJAM

(F1G.2-50)
)L

LATCH

BDFA
HARBI

NGER

—o—>{ LD
NO NEXT CLOCK<3>

NM! HARBINGER

¢1-¢

RESET

[L » (FIG.2-6)

NMI_UNJA

— LATCH]
B

AVAM

]
A CLEAR STATE
B
JCLEAR B o
|

|
(FIG§2-6, |
|
)l

NO_NEXT

(FIG.2-15)

CLK

NO NEXT

CLOCK<3:0>

LATCH

2-45)

CLK

|
|

LATCeH

(7)

|
|

(g)

|_FACIK

CLK IN

(5)

|_FBCIK

F B GLK IN

e,
LATCH

BLOCK A »

CLOCK — p(FIGS.2-27,
>

— 5'3352'34' |
NG NEXT

(8)

|
:

DAq__J
.

NOTE:

NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC
SCLD-40

Figure

2-2

Dad Block

Diagram

(Sheet

The

major

describe

DAD ports

2.2.1
The

how

DAD

major
e

the

are

defined

DAD

functions

and

then

for

the

block

various

diagram

MCL

used

operations.

Ports

DAD
NMI

ports

are:

ADDRESS

DATA<31:0>

data

and

address

data-address

I/0

the

NMI

port

the

(bi-directional).
®

ADFA

DATA

ADDR<K31:0>

output

MDB.

°®

BMDP

MAR4

during

decode

2.2.2
to

SER

from

CSR0O,

NMI

Writes

the

false,

and

parity

input

selects

Parity

1is

MCA0

1is

address
outputs

2,2.3
Data

sent

NMI

port

BMDP

from

NMI.
FB

the

NMI

latched

CORRECT<2:0>

are

<3:0>

the

RECV

DATA

ADDR<31:0>

mux.

When

ADFA

NMI

DEAD

ADFA

DATA

1is

output

the

from

data-address

When

ADFA NMI

are

NMI

data.

the

mux

where

sent

(ADFA

are

the

mux

ADFA

GEN

is false,
MDB

the

as
ARID

nibble
in

The

not

applied

NIBBLE

used

arrays*.

the

four-bit

bit

MCAs

and

DEAD

them

also

parity

memory

the

MDB.

coupled

data

from

input

occurs

data-address

BMDP

bits

from

DATA<31:0>.

correction

Address

NMI.

then

RECV

the

ADFA

where

RECV

DATA

PARITY)

from

generation

NIBBLE

PARITY

used.

Memory

The

error
BIT

DATA<31:0>

and

read back

bits

three

memory

which

for serial

CSR3

outputs

MDB

the

other

the

from the

writes,

and

the

for

Reads

parity

from

data

masked

ADDR<K31:0>.

the

generated

the

transfer

DATA<31:0>

generated

parity

read

a
to

bits

made

The

from

generated

also

ADDR<7:4>,

DATA

data-address

The

input port

DATA<31:0>

input

parity

PARITY<3:0>.

check

CSR2,

GEN-parity mux.

the

parity

CSR1l,

transferred

feedback

from memory,

to Memory

RECV

receives

RB<3:0>

ADDRESS

the

ADDR<31:0>

Byte

NMI

reads

addressing.

CSR<3:0>

Dbecomes

applied

RAM

NMI

data

Data-address
DAD

DATA<K31:0>

latched

applied

(if

are

not

ECC

from

used.

2-13

DAD

to
at

the
the

DATA<31:0>

RECV

XOR

AMDP

arrays

the

become

needed).

received

the
to

gate

CORRECT

the

DCHK

DAD

for

feedback

becomes

DATA<31:0>.
where

single-bit

EN<3:0>
and

and

applied

AMDP
to

ed by the
correction decoder. If a single-bit error was detect
byte in the
DCHK, AMDP CORRECT EN<3:0> enables the appropriate
bit within
decoder. AMDP BIT CORRECT<2:0> specifies the erroneous
with the
the byte. The decoder output (BIT CORR EN<31:0>) isallXORed
32 bits from
memory read data. If no error exists in the data,
If a single-bit error exists, the
the decoder are negated.
corresponding bit from the decoder 1is asserted causing the
erroneous data bit to be flipped (corrected).

input of a
The output from the ECC XOR gate is applied to the asDO MUX
CORRECT
correct-data mux which outputs the memory read data
into a B latch to
DATA<31:0>. MUX CORRECT DATA<31:0> 1is loaded latch
ed by HOLD FB
is
31:0>
DATA<
WRAP
B
.
become B WRAP DATA<31:0>
DATA from the ARID arbitration logic, until the ARID has won the
NMI

bus.

transferred to
B WRAP DATA<31:0> is gated by EN DATA OUT and then 31:0>
port. EN
DATA<
SS
ADDRE
NMI
onal
recti
the NMI via the bi-di
within the MCL
DATA OUT 1is true when there is no internal error
ted. ADFA
(AMRM INT ERROR negated), and ADFA OUTPUT ENABLE is asser
is the NMI bus
OUTPUT ENABLE 1is asserted by NMI MCL BUS EN which the
MCL has won
grant received from the CPU arbitration logic when
Fho

Ltne

DSuUusS.

applying the
parity 1is generated on the memory read data byator
before it
data (FB DATA<31:0>) to an out-parity gener
arity generator
passes through the ECC correction logic. The out-p
which in turn
mux
arity
out-p
an
of
input
outputs into the DO
The parity bits
outputs the parity bits as BDFA OUT PARITY<3:0>.
is made on
check
y
parit
a
where
MCA
are transferred to the ARID
on the
red
occur
ction
corre
e-bit
singl
If
the memory read data.

Byte
read

read data, the ARID compensates for the corrected bit.

Masked Writes Requiring Single-Bit Error Correction
2.2.4
detected a
In a masked write operation in which the is DCHK
the DAD
into
fed
data
the
data,
single-bit error 1in the read
ned
retur
and
d
aroun
ed
wrapp
then
feedback port, ECC corrected, and
on
ated
gener
is
y
Parit
port.
ss
to the MDB via the ADFA data-addre
that
Note
data.
the
with
MDB
the
the wrapped data and returned to
the data/address
the wrapped data uses the same output port as the
NMI while the
from
input
no
be
from the NMI. Hence, there must
the ARID
this,
plish
accom
To
DAD.
the
wrap-data is passing through
wrap
DAD
the
ver
whene
NMI
the
on
ic
asserts NMI BUSY to halt traff
NMI
no
is
there
that
s
sense
FUNK
the
path is to be wused. When

the wrap-data path.
traffic, it asserts ADFA NMI DEAD to enabledescr
ibed below.
is
DAD
the
gh
The path of the wrap data throu
el where it
BMDP FB DATA<31:0> is passed through the feedbackThechann
cted data
corre
gate.
XOR
ECC
the
undergoes error correction in
31:0>,
DATA<K
WRAP
B
s
become
it
where
is then input into the B latch
MDBC
the
from
DATA
WRAP
HOLD
BMDP
by
ed
B WRAP DATA<31:0> is latch
true)
DEAD
NMI
(ADFA
quiet
is
NMI
the
until the MDBC senses that
and negates BMDP HOLD WRAP DATA.

2-14

The

corrected

applied
the

true

which

wrap

data

input

the

state

causes

DATA<31:0>

the

held

WOR

ADFA

WOR

output.

NMI

mux

WOR

ADDR<31:0>

output

port

The

corrected

wrapped

data

wrap-parity

generated.
output

generator

CSR

from

DEAD,

DAD

latch

OR)

the

data-address

WRAP

DATA<31:0>)

becomes
ADFA

OUTPUT

input

DATA

WRAP

for
to

also

CSR

DATA

the
the

WOR
ADFA

applied

PARITY<3:0>

sensing

mux.

bits

WRAP

GEN

MDBC,

transferred

via

parity

DATA<31:0>)

The

BMDP

the

then

WRAP

mux.

asserts

select

where

PARITY<3:0>

the

(wired

DATA<31:0>

DATA

the

via

the

to
are

which

GEN-parity

mux.

2.2.5

Error-Free

The

MAR4

error

the

NMI

read

OUT

applied

correction

required.

data.

from

PARITY

DAD

never

wrap

back

2.2.6
A

read

the

ARID

the

MDB

DECRAM-ADDR

mux

outputs

mux.

the

WOR

state

BMDP

OUTPUT

when

the

also

RAM

1Initially
for

(BMDP

DATA<31:0>).

turn

DATA<31:0>
READ

the

feedback
done

the

for

same

DEAD

parity

checked.

OUTPUT

port

The

ENABLE

even

parity

path

generating

when

checking

during
bits

read

false),

BDFA

data

nor

does

decode

RAM.

false).

is
SEL

for

addressing

store-decode

DATA

input

from

RAM

the

addresses

selected

MDBC

(no

into

the

DECRAM-ADDR mux inputs are
initially loaded and when reading

the
RAM

BMDP

latched
to

the

false,

Decode
are

RAM

input

The

the

become
input

the

mux

RECV
of

the

selects

error

CSR1.

feedback

port

FB DATA<31:0>

DATA<31:0>.

RECV

DECRAM~ADDR mux.

the

negated

generated

initial

DAD

FB DATA<31:0> becomes
DO

the

single-bit

The

decode

applied

CSR1

NMI

used

addresses

which

follows
parity

The

WRAP

occurring).

decode

2.2.6.1

RAM Addressing
path

correction

DAD

(ADFA

data

input

NMI

the
This

2.2.3),

where

the

data

(Section

reaches

Decode
wrap

The

memory

for

the

The

Writes

read

Masked

data

input

for

With

the

WOR

mux.

2.2.6.2

Reading

CSRl

addressed

DATA<31:0>

becomes

latch.

obtained
from

The

CSR

which

CSR

ADDR<4>

ANDing

decoder

CSR

selected

CSR

that

DAD

The

decoder

and

CSR1

the

When

CSR

the

DAD.

STRD

accessed.

AMRM

<receives

port

DATA<31:0>

latch

BMDP

DECODE

reading

feedback

3-bit

accessed,

The
is

stored
from

3-bit

outputs

applied

MRM

and

address

the

address
B

store-decode

DATA<31:0>).

the

asserted.

2-15

for

from

ADDR<3:2>)

output

the

(BMDP

which

enabled

WRITE

CSR1,

When

CSR1

MDB

is
the

the

input

CSR

WRITE

CSR1

(BMDP

which

DECODE

SPECIAL

specifies

decoded
decoder

DECODE.

RAM

BMDP

and

the

senses

CSR

WRITE

which
ST

1loads

appears

the

DECRAM ADDRK31:0>

mux

where

READ

CSR1

The

latch

output
is

applied

selected

for

the

store-decode

latch
the

the

input

output

RAM

address

DECRAM ADDR<K31:0>.
of

the

true

DECRAM-ADDR
state

SEL.

READ

CSR1

SEL

DECODE
with SEL CSR
EN SERIAL RD (always

select

CSR Reads

signal

obtained

ANDing

CSR1

DATA. SEL CSR DATA is asserted by ANDing BMRM
asserted when CSRO, CSR1l, CSR2, or CSR3 is to

be read) and the false state
CSR0O, CSR1, CSR2, or CSR3 is

2.2.7

with
the

the

of
to

stored address
be accessed).

bit

<4>

(false

when

NMI

Four MCL CSRs (CSRO, CSR1l, CSR2, CSR3) are read out to the NMI via
the
DAD
serial
read-back
port.
The port receives CSR data, in
serial
format,
from
the FUNK, the ARID, and the MDP. The
is accumulated and assembled inside the DAD and ocutput
NMI in parallel format.
data

The

serial

where
one

two
of

the

selected
from

the
negated

state

the

enabled

The

counter

enabling
data

mux

CSR

applied

CSR~-select
data

from

the

mux.

The

path

the

outputs

mux

select

the

serial-parallel

mux

enabled

the

ADDRK4>,

selects

the

input

SEL.

32-bit

output

BIT

CSR

from

ENK31:0>

one

loaded

from
latch which is

CLK

sequence,

time.
in

presently

output

counter.

due

The

incremented

locations
latch

DATA

and

CSR

the

serial-parallel

EN<K31:0>

bit

(STRD ADDR<K3:2>)

mux

BIT

latch

applied
MDB

input

applied

SERIAL

is
the

CSR-select

asserts

the

CSRs
from

PARALLEL

mux

STRD

serial-parallel

four
bits

The

CSR-select

state

enabled

the

serial-parallel

false

from

address

CSRs.

CSR

the

The

data

stored

serial
to the

bit

The

and

counter

CLK.

thereby

load

the
at

the
load

serial

CSR

time.

The
serial
1loading
process
1into
the CSR latch is accomplished
simultaneously
by
the
four
DADs;
therefore,
each DAD counter
outputs
eight
CSR
BIT
EN counts in sequence to serially load a
byte
1into
each DAD latch. After eight cycles of the counter, the
32-bit
An

CSR

latch

exception

occurs

(bits

the

fully
the

case

loaded

serial

CSR1l.

with

the

data

format

The

least

CSR
of

data.
the

received

significant

CSR

byte

data

received

<7:0>)
1is in serial format while the other three bytes are
1in parallel format. Consequently, when it is sensed that

received

CSR1

(PARALLEL

the

input

significant
PARALLEL

CSR

PSRV

read,
is

from

the

SEL

MCAO

the

SEL)

bytes

DATA

mux.
EALN

DATA

into
in

will

select

asserted

input
in

feedback

the

MCAO

pass

port.

feedback
is

false

the

CSR1l

MCAl,

CSR1

port
to

select

least

the

2-16

and

routes
FB

MCA3

its

three

mux

select

most

DATA<K31:8>.

the

input

significant
A B d N

serial-parallel

MCA2,

byte

from

the

through

PARALLEL

from

DATA

(MODE<1:0>)
to

its

the

MCA

SEL

slice

which
be

PARALLEL

MCAO

selects

The

CSR

latch

applied
the

mux

DATA.

CSR

the

CSR
of

for

CSR

data

DATA<31:0>
HOLD

1is

DATA

until

its

bus

grant

CSR

data

The

1latched

CSR

data.

data

the

from

to
The

the

32-bit

correct-data
B

latch

mux
and

asserts

WRAP

where

described

NMI

are

CSR ADDR
are

for

the
of

to
The

FUNK

I/O

When

out

is
the

the

CSRs

slice

decoder

space

CSR

inputs

specify

each

which

MCA will

(FUNK)

MCA

CSR
of

CORRECT

DATA

latched

MCL

receives

transfers

the

port.

applied

generated

the

BDFA

ouT

ARID

discusion,
the

NMI.

from

the

serves
Address

the

RECV

addresses

detected.

3E000000

MCAO,

the

SEL

MUX

the

monitor

then

decoder

CSR7.

decoder

the

and

monitors

address

ranging

assertion

and

gate

mux

mux.

preceeding
the

senses

input

then

also

out-parity

vread

bus.

the

input

internal

NMI.

PARITY<3:0>

applied

the

DATA<31:0>)
CSR

input

during

the

FUNCTION
FUNK

the

won

address.

2.3
The

the

DATA<31:0>

MODE<1:0>

that

ADDR<4>

DATA OUT

ADDR<31:0>

3E00001C

STRD

state

ADDRESS

decoder

addresses

read

true

function

asserts

CSR

the

NMI

The

and

for

into

SLICE

AND

which

The

the

CSR

mux.

CPU,

data

the

DATA<31:0>

correct-data

the

CSR

from

CSR

decoder

output

has

serial-parallel

via

inputs

the

NMI

PARITY<3:0>

DATA

slice

from

generator

state

inhibits

MCL

PARITY<3:0>

slice

the

which

negation

1loaded

CSR

another

Hence,

the

true

the

wrap-parity

When

SLICE

asserted
and

output

which

the

receives a two-bit code
position of the MCA according

byte

the

OUT.

The

input.

input

DATA

MCAQ

decoder

module.

SEL.

selected

SERIAL

the

asserts

its

slice

MCL

DATA

outputs
the

SEL

BMRM

the

MCA0,

producing

never

false

The

specifies

location
to

held

decoder.

MCAl,

correct

for

The
CSRO

etc.,

byte

the

MCA

MCA:
Decodes

the

NMI

Generates

read

Generates

the

Asserts

the

Provides

Figure
2-3
1is
throughout this

function
function

confirmation

NMI

status

block

fault

bit

codes

used
for

the

codes

for

and

CSRI1.

the

MCL.

NMI.
the

NMI.

FUNK

MCA.

line.

CSRO

diagram

section.

2-17

the

Refer

(FlG.z-z)%

_GCSR ADDR

. BOFA CMD<2»,<0>

— (FIG.2-5)

<4 0>

(1)

YNMI

BECOOER.

FUNCTION

XNMI FUNCTION <2:05)

FUNCTION «<3:1>

READ

(1121418)

VD
Rew

FUNCTION <1:0>)

PNCTION <43,

:|
4,
<<4>
FUNCTION

NMI

FUNCTION
INVALID

PAR

CTRL GEN PARITY

(FIG.2-7)

INTERLOCK

GEN

{1}

_UNLOCK
ADFA DATA

ADDRESS<20>

()

(FIG.2-2)—)
i

ADDRESS 29

81-C

_WRITE DATA CYCLE l
(FIG 2--67)
(7)f

(F1G.2-14)—F
(FIG 2.7)

NMI MEMORY

mTE;uoc

BUSY

—

ADFA

PARITY ERROR2

CONFIRMATION<1> _ ({7 1.

MEMC

BUS
NMI

CONFIAMATION<0>

NMI— - -

ADFA

(2~2,s2-7
FIG
1
2-23.2-34)

(FIG.2-45)

NMI_DEAD

BDFA

NMmi oEADY|

~{(8)

WRITE

@
oJ—

o)
6

QUAD

G"" B

()

——®

[‘DO-—(G) -

WRITE

LONG

(7)

FUNK

. NUMBER DESIGNATIONS IN PARENTHESEY REFER TO ENGINEERING DRAWINGS CONTAINING CORRESPONDING LOJGIC
NOTE-

Y
EYSRTRET

Figure

2-3

FUNK Function and Control Logic

(Sheet 1 of 2)

Mfi»_'(fla 2-9)
e ——/.__DDFA SIZE<}.02

BDFA CMD<2
02

»r—

BOFA CMD<0»

}(FIG 2-34)

X¥—(FIG 2-19)

—BOFA CMD<2>

4 __(FiG.2.9)

BDFA_NEW

D-CMOEARLY
w

—- (F1G.2-46)

[

BOFA

NEW

rr—.[(—f:l—om-—)‘-—-mes 2-9,2.34)

LOCK
TIMEOUT
COUNTER

F-— NMI

)

rd(ma.z»iz)

(3)

(FIG.2-4)

e
P
a—

AP CSH WHRITE

(FIG.2-51)

_BMOP FB D.AIAsZfiL___‘,,,A. BMOP STRD

-E£SRO_DECQDE

e1-¢

(FIG.2-4)

ADDR<42>

«—CSA3 DECODE

ADP BUSY REQ

}(FIG 217)
(F1G.2-19)

MM BUSY BREQ

MMM INT ERROR

(F1G.2-34)

(FIG 2.4)

WRITE

B TRANS T
DUR_FAUL

TRANS

FAULT

SEQ
FAWT

A»M—-g‘%

FAULT

DETECT

SYS
FAULT
INPUT

DATA

ADFA

T
F

ACLK

DECODE

DETECT

EAULT. .

BMM EN
EAIAL

p—— NMI

5
.--F.B CLK
NOTE

NUMBER DESIGNATIONS IN PARENTHESES REFER
TO ENGINEERING DRAWINGS CONTAINING CORREGPUNDING LOGIC

Figure

2-3

(Fl ()52

FUNK

(FIG.2- 19)

Function

and

(FIG.2-51)

Control

SCLD41A

Logic

(Sheet

Function Field Parity

2.3.1

The
five-bit
function
field from the NMI (NMI FUNCTION<4:0>) is
to the FUNK MCA. NMI FUNCTION<K3:1> is
applied
then
and
renamed
renamed
XNMI
FUNCTION<K2:0>,
and
NMI FUNCTION<K4>,<0> is renamed
YNMI

FUNCTIONK1:0>.

The
function
bits
are latched to become FUNCTION<4:0> which are
then
applied
to
a
parity generator. Parity is generated on the
function field and output as CTRL GEN PARITY to the ARID MCA where
the

function

field parity

checked.

Function Decoder

2.3.2

FUNCTION<4:0> is applied to a function decoder where the commanded
Another input to the function decoder is
decoded.
1is
operation
which is received from the DAD MCA as
29)
(ADDRESS
29
bit
address
bit 29 specifies the commanded
Address
ADDRESS<29>,.
DATA
ADFA
to I/O space (to a CSR).
or
memory
to
access
operation as an
Table

2-3

they

specify.

lists the function bit codes and the command operations

Table

2-3

Function Codes

FUNCTION

(Hex)

321

1 0
1 2
1 3

1
1
1

606060
0010
0011

Read longword
Read octaword
Read hexword

1 4
1 6
1 7

1
1
1

¢6102¢0
0110
0111

Read longword interlocked
Read octaword interlocked
Read hexword interlocked

i B
1

i
1

10611
1111

Write longword
Write octaword

18
1 9
1A

1
1
1

1000
1001
1010

Write masked longword
Write masked quadwoxrd
Write masked octaword

1 C
1D
E

1
1
1

1100
1101
111

Write masked longword unlock
Write masked quadword unlock
Write masked octaword unlock

0 A
0 E
0 8
0 C

0
0
0
0O

1010
1110
1000
1100

Read/return good data
Read/return bad data
Read/continue good data
Read/continue bad data

1001

Write data

Command Operation

2-20

The

decoder

outputs

2-bit

size

code

(BDFA

SIZE<1:0>)

that

specifies the size of the data transfer. The size code is shown in
Table
2-2.
BDFA
SIZE<K1>
goes
to the ARID to specify a hexword
operation to the ID/mask logic. BDFA SIZE<K1:0> goes to the MRM.
The
decoder
outputs
specifies
the
type
Table

a
of

3-bit
command code (BDFA CMD<2:0>) that
operation.
The command code is shown in

2-1.

Note
1in
Table 2-1 that bit BDFA CMDK2> specifies a read or write
operation,
bit
BDFA CMDK1> specifies a memory or CSR access, and
bit
BDFA
CMD<K0> specifies a non-masked or masked operation. Bits
BDFA
CMD<2>
and
BDFA
CMD<KO0O>
are
obtained
directly
from the
function
decoder.
Bit BDFA CMDK1> is derived from CSR VALID. CSR
VALID
is
true
1if
CSR
ADDR
from
the DAD is asserted (the NMI

address
is
to
one
of
the
CSRs)
and the function decoder has
decoded
a
WRITE CSR function or a READ LONGWORD function (access
to CSRs must be a longword function).
BDFA
CMDKO>
goes to the MDBC to specify
CMD<2> goes to the ARID to specify a read
goes

the

a masked operation. BDFA
operation. BDFA CMD<K2:0>

MRM.

The
command
code
(BDFA CMD<2:0>) and size code (BDFA SIZE<1:0>)
specify all the functions listed in Table 2-3 except:
°

A write

These

lock

three

respectively

function

unlock

function

data

cycle

functions

are

specified

when

the

function decoder

asserts:

INTERLOCK

UNLOCK

WRITE

DATA CYCLE
NOTE

The
function
decoder
does
not decode
read/return
or
read/continue functions
as
these are not commands received from
the NMI. They are commands issued by the
MCL (from the MRM).

The
function decoder
mnemonics,
that
are
following sections.

2.3.3

asserts other outputs, with
wused
within
the
FUNK as

self-explanatory
discussed in the

NEW CMD EARLY/NEW CMD LATE

Early
and late new-command
a
valid,
error-free,
new
signals
are
sent
to
the

signals are generated by the FUNK when
command
is detected. The new-command
MRM
as
the load signals for the new

command.

2-21

A new-command mux selects CSR VALID from the function decoder
(true if a valid CSR access is commanded) or ADFA MEM ADDR from

the

RAM

decode

the

(true

DFA

if a valid memory access 1is

The output from the new-command mux is START NEW CMD.
commanded).
Mux selection is made by memory/CSR address bit ADDRESS 29.

START NEW CMD is applied to two AND gates to generate BDFA NEW CMD
EARLY and BDFA NEW CMD LATE. BDFA NEW CMD EARLY and BDFA NEW CMD
identical

functionally

are

LATE

(BDFA

NEW

occurs

EARLY

CMD

slightly before BDFA NEW CMD LATE) and are applied to different
areas within the MRM. There are three conditions that will inhibit
the assertion of BDFA NEW CMD EARLY and BDFA NEW CMD LATE. These
are:

when
by
asserted
FUNCTION INVALID
P the function decoder
c
function
valid
a
g
specifyin
not
code
a
the decoder senses
mT

TAIUZAT

in Table

listed

de VAL E s

e 4

PR W A

2-3.

BLOCK COMMAND -- asserted by the block-command logic when
the new command is to be blocked for reasons discussed in
Section

2.3.7.

LLLLLL PARITY ERROR2 -- asserted by the ARID module when a
parity error is detected 1in the ID/mask field, the
B

function field, or the data/address field (Figure 2-7).
ADFA PARITY ERROR2 inhibits only BDFA NEW CMD LATE in the
FUNK, however BDFA NEW CMD EARLY is inhibited by a parity
error 1in the MRM, thus the BDFA NEW CMD EARLY and BDFA
NEW CMD LATE remain functionally identical.

2.3.4

Read Lock Function

When the function decoder senses a read-lock function, it asserts
INTERLOCK is ANDed with B NEW CMD (an asserted B NEW
INTERLOCK.
CMD means a valid, error-free, new command) to set a lock-1logic
circuit. When set, the 1lock 1logic asserts LOCK which remains
asserted until the lock logic is cleared by a write-unlock command
or a write

The

to CSRO.

assertion of LOCK enables a lock-timeout counter which starts

to time the interlock

2.3.5

interval.

Write Unlock Function

Wwhen the function decoder senses a write-unlock function, it
asserts UNLOCK. UNLOCK 1is ANDed with B NEW CMD to assert CLEAR
LOCK (B TIMEOUT false). CLEAR LOCK clears the lock logic (thereby
negating LOCK)

and resets the lock-timeout counter.

Had a lock-timeout occurred, B TIMEOUT would have been true and
inhibited the <clearing of the 1lock 1logic by the write-unlock
function. In this case the lock logic is cleared by writing bit 26
into CSRO. Writing bit 26 into CSR0O asserts CLEAR LOCK via an AND
gate which is enabled by the following three inputs:
IX

2-22

AMRM

CSR

WRITE

asserted

from

the

MRM

whenever

written.
®

BMDP

DATA<K26>

—--

asserted

from

the

MDP

when

CSR

bit

true.

CSRO

DECODE

three-bit
from

2.3.6

the

MDB

from

the

1logic

the

counter

received

from

the

clock

The

command

lock

logic

and

negation

unlock

COUNT

sets

outputs

and

BLOCK

lock

the

NMI

COMMAND,

logic.

ADFA

the

timeout

2.3.7

Block

BLOCK

COMMAND

for

ms.

reset
and

LOCK),

the

does

occur

not

ten

when

the

received

SLOW COUNT

bit

NMI

Once

COUNT

where

(bit

Thus,
(to

when

clear

counter

the
used

lock-timeout
in

command

the

FUNK
B

an
the

reset.

SLOW
LOCK

counter

the

generation

from

clearing

the

CSRs

where

TIMEOUT

sets

output

causes

interrupt

CSR3)

set.

counter.

2-4).
it

EN)

SLOW COUNT

LOCK

lock-timeout

unlock

Figure

TIMEOUT

counter.

SLOW

LOCK.

CLEAR

cycle),

applied
25;

The

CLEAR

timeout

TIMEOUT

inhibit

(bit

(NMI

after three cycles of NMI
thirteen ms depending on where

asserts

the

enable

the

CPU

Command
1is

aborting

inhibiting

the

LATE

MRM.

The

conditions

the

1is

disables

also

MCA

3.3

ARID

clock

approximately

bit

decoder

ADDR<K4:2>)

lock-timeout

NMI.

and

timeout

by
the

TIMEOUT.

CSRO

module

negate

command

ADDR

STRD

via

(approximately

asserts

enables

received

LOCK

CSR

CSRO.

increment

counter
1is

The

lock-timeout

UNLOCK

clock

period

(BMDP

Counter

1lock

enabled,
has

from

code

specifies

Lock-Timeout

LOCK

asserted

address

asserted

new

when

command.

assertion

that

condition

The

BDFA

assert

sensed

new

command

NEW CMD

EARLY

BLOCK

COMMAND

and

atre

that

calls

aborted

BDFA

NEW CMD

described

the

following:
®

INTERLOCK

command

INVALID

1is

(INTERLOCK

from

UNLOCK

INVALID

command

1is

asserts

while

TIMEOUT

cannot

while

read-lock

true).

LOCK

1indicates

unlocked

received

true).

while

that

memory

false),

timed
Once

memory

The

interlock

already
is

locked

memory
still

will

locked

command.

because

LOCK
has

that

the

command

read-lock

invalid

command

indicates

because

asserts

not

lock

invalid

out

locked
the

asserts

command

write-unlock

2-23

received

not

because

(UNLOCK

read-lock

has

unlock

(UNLOCK
existing
while

timed-out,

command.

WRITE

write

BUSY

=-function

time.

Similar

sooner

and

during

the

asserts

command
MEMORY

BUSY

Serves

WRITE

BUSY

(WRITE

indicates
and cannot

does

2.3.8

1is
AMRM

BUSY

NMI

MEMORY

BUSY

SEQ

FAULT

was

detected

Write

The

enough

write

command

when

from
or

function

AMDP

BUSY

that

command

indicates

that
transfer.

prior

FUNK

MCA

sections

longword

input

occurs

insufficent

and

three

when

number

ADFA

MEM

write

time.

write

data

and

AMRM

true.

is busy and
Serves as a

sequence

command

cycles

for

section

input

and

the

circuit,

octaword).
write

fault

received

complete

the

octaword

divided

into

must

gate

first

checks

from

the

for

enabled

from

valid

memory

decode

RAM

(true

(false

for

access,

INVALID,

NMI

MEMORY

BUSY,

and

WRITE

BUSY

1is

enabled

and

turn

enables

write-sequencer

via

Longword

Write
a

write

enables

the

long

section

longword

assert

DLY

outputs

memory

and

quadword

asserted

for

memory

AND

gate.

looking

access).

the

long

memory

command

AND

command.
sserts

all

gate,

these

The

access)

two

valid

false),

and

signals

(FUNCTION
the

memory

path

for

the

quad

AND

gate,

(via

sequencer.

Upon

sensing

write

the

free-running

followed

INPUT

the

DATA

DLY

write

dat

function

input

the

during

the

WRITE

wuses

asserts

output

-it

and

BDFA

write

Memory
command,

gate

occur

longword
7

longword

section

or
O

DLY

latched

write

the

command;

three

and

gate.

2.3.8.1

inputs

detects
longword

command

for

wmemory

AND

for

section

octa

input

command.

ADDR

gate

longword

asserted

memory

indicate

REQ

this

ADDRESS

the

NMI

this.

received

decoder)

the

sequencer

quadword,

asserted

quadword

inputs

AND

1is

octaword

memory

contains
(longword,

the

command;

Fault

fault

section

write

AND

command.

soon

write

transfer.

three

The

Sequence

sequence

followed

write

DETECT

cycle

ndi
indicates

)

the

new

BUSY

block

data

REQ,

another

however WRITE

can

assert

asserted

ERROR,

BUSY,

flag.

asserted

INT

write

first
not

"read-busy" flag.

MEMORY

therefore

"write-busy"

COMMAND

cannot

NMI

that the memory is busy with a
accept another command at this

2-24

the

gate)

and

output.

data

cycle

MDBC

and

decoder

LONG
the

The

which
to

the

input,

clocks

and

following

the

DLY

MRM

load

AMEM

(FIG.2-17) \\!

DATA<25>

A COLD

POMER_UP

_CSR WRITE|

|
|

BMOP
FB

|I (F1G.2-3) -CSR3_DECODE

G¢—-C

(9)

DATA<26>

(FIG.2-51)-—§f

5SER RB<3> >lL

EN
(

START

—_

L(()ga)nc

r>(F|G.2 - 2)

'
:

Lg) —|CLR

——

COLD

o ———

’7

CLR

CSR
3

(9)

STARTI

(FIG.2-53)

INTERNAL

BMDP FB

P4l

(FIG.2-3)

BMRM

B_TIMEQUT

M csr o
-

WRITE SEQ FAULT

*1 B TRANS DUR FAULT

SERIAL_RD<2:0>

SER

, | BD=2:0>

|
FUNK CSRO

> EN
Y

SERRB<3>

I
FUNK

NOTE:
THE LOGIC IN THIS FIGURE |S CONTAINED ON
SHEET 9 OF THE ENGINEERING DRAWINGS.
*

Figure

2-4

FUNK

CSRs

8CLD 42

it 1is
DLY 8 asserts WRT CMD DLY to a sequence etrror AND gate where
on
functi
the
from
CYCLE
DATA
ANDed with the negated state of WRITE
data
write
the
that
tes
indica
decoder. A negated WRITE DATA CYCLE
cycle that should have followed the write longword command did not
occur. If this is the case, SEQ FAULT DETECT asserts.

The assertion of SEQ FAULT DETECT causes the following to occur:
Asserts BLOCK COMMAND to inhibit new transactions.
®
®

Asserts ADFA BAD DATA to the MDBC.

Asserts SEO FAULT DETECT to the confirmation logic where
a memory-busy code is generated to stop memory commands
from NMI

nexus.

Asserts NMI FAULT from the fault logic.

Sets the write-sequence-fault error bit in CSRO.

Note

that the occurrence of a write sequence error does not cause

ons to
the current write sequence to be aborted. The MCL functir,
the
Howeve
there.
were
it
write the missing data just as though
the
g
markin
memory
into
n
bad-data bit 1is set and gets writte
addressed location as bad data.

s is to a
2.3.8.2 Write Longword to CSR -—-- If the write addres
disables
This
true.
is
29
CSR, ADFA MEM ADDR is false and ADDRESS
gate.
AND
CSR
a
s
enable
the 1long, gquad, and octa AND gates, but
the
from
ADDR
CSR
that
es
The enabling of the CSR AND gate requir
CSR
WRITE
that
and
CSRs)
DAD be true (the address is one of the
D,
from the function decoder be true. In addition, FUNCTION asINVALI
the
1in
just
false
be
NMI MEMORY BUSY, and WRITE BUSY must all
case of a longword write to memory.

CSR AND gate enabled, the longword section of the write
ds to
sequencer receives an input (via the OR gate) and procee
the
follow
should
that
data cycle
write
the
for
check
a
g,
missin
is
cycle
data
command/address cycle. If the write
rd
longwo
a
of
case
the
in
as
write-sequence error is asserted just

With

the

write

to memory.

to
2.3.8.3 Write Ouadword -- Returning to the case of anrd access
d,
comman
quadwo
write
a
s
detect
r
memory, 1f the function decode
s an
it asserts WRITE QUAD which enables the quad gate and assert
g
sensin
Upon
cer.
sequen
write
the
input to the quadword section of
B
and
A
unning
free-r
the
uses
n
the input, the gquadword sectio
The
.
output
6
DLY
a
by
ed
follow
clocks to assert a DLY 5 output
write
DLY 6 output 1is fed back into the longword section of theoutput
s
DLY
the
All
.
output
8
sequencer causing a DLY 7 and a DLY
the
during
occur
s
output
6
DLY
and
occur in sequence. The DLY 5
fFirst write data cycle following the guadword command. The DLY 7
IX

2-26

and

DLY

following

outputs

the

DLY

the

1latched

write

CMD

DLY

the

asserts

the

first

data

the

<cycle.

the

write

write
of

signals

will

2.3.8.4

DLY

for

cycles

data

cycle

MRM

for

BDFA

the

write
WRT

load

asserts

WRT

presence

INPUT

DATA

data

the

CMD

DLY

the

second

FAULT

DETECT

presence

cycles

have

hold

SEQ

This

the

occurred

have

transfer,

will

cycles.

will

SEQ

missing

write

(all
be

the
WRT

sequence

FAULT

data

error

DETECT

implemented

sequence-error

occurred),

gate

operation.

write-data
data

missing,

AND gate.

cycles

CMD

DLY

will

disabled,

and

the

for

feeding

When

the

not
SEQ

asserted
all

current

assert,
FAULT

the

DETECT

clear.

Octaword

the

function

asserts

1input

the

sequencer.

Upon

sensing

free-running

and

fed

the

DLY

check

the

case

WRITE

and

latched

are

the

asserts

the

and

sequence.

section

write

cycle.

re—-asserts

command,

gate

MDBC

re-asserts

check

data

DETECT

AND

Write

octaword

load

write

data
the

should

sequence~error

error

DLY

the

data
gate

just

longword

FAULT

transfer

gate

functions

rest

SEQ
DLY

second

cycle.

multi-longword

tor

AND

write

during

back

errcr

MRM

AND

first

cycle.

and

DATA

the

either

sequence

error

the

data

asserts

any

INPUT

and

data

cycle

data

write

sequence

write

BDFA

during

command.,

MDBC

the

second

occur

guadword

into

the

back

the

clocks

The

causing

the

assert
output

and

longword

DLY

which

octaword

input,

DLY

decoder

OCTA

section

octaword

DLY

fed

DLY

into

The

causing

DLY

during

the

octa
write

uses

the

and

DLY

3,
6

write

the

DLY

a
the

section
2,

back

output.

section

detects
enables

quadword

output

and

DLY

output.

The

and

DLY

cycle

following

the

cycle

has

odd

DLY

numbered

the

MRM

The

odd

DLY

load

even

Due

output

the
AND

command.

FAULT

DETECT

ADFA

BAD

though

the

outputs
an

even

asserts

latched
DLY

occur

command.
numbered
BDFA

write

output

gate

check

any

the

SEQ

data

write

data

each

write

data

asserted.

The

DLY

output

INPUT

DATA

asserts
for

first

Likewise,

the

current

WRT

CMD

the

presence

write

data

cycles

are

FAULT

DETECT,

MDRBRC

data
DLY

and

cycle.
to

the

write

data

missing,

SEQ

asserts.

the

early

and

numbered

sequence-error
cycle

octaword

feedback

the

DATA to
later

octaword

stay

data

transfer

will

asserted for

cycles

are

missing

SEQ

rest

the

present.

2-27

cause

FAULT

the

data

cycle

DETECT

transfer

and

even

NMI

2.3.9

Faults

The
FUNK receives fault-detect signals from all the NMI nexus and
from
the
ARID, and ORs them with the FUNK write-sequence errors.
The
FUNK
then
outputs
one fault line on the NMI for the entire
system. The assertion of any of the fault-detect lines will assert
NMI

FAULT

the NMI.

FAULT DETECT<3:0> is received from the other system nexus and
NMI
ORed
with
ARID
FAULT
DETECT
from the ARID MCA*., The result is
input to the FUNK as SYS FAULT DETECT. SYS FAULT DETECT is applied

(via
an
OR
gate) to an NMI fault lock-up circuit. The NMI fault
lock—-up circuit asserts BDFA NMI FAULT to the ARID to latch up any
fault
that
may
have
been
detected
by the ARID. The NMI fault
circuit also asserts NMI FAULT on the NMI. A third output
lock-up
signal
(A FAULT) is asserted and fed back to the input OR gate to
lock-up
the
NMI
fault
logic
and hold the three output signals
asserted.

A
FAULT
1is
also
applied
to
the
lock inputs of a trans-fault
lock-up
circuit
and
a
write-seq-fault
lock-up
<circuit.
The
TRANS-fault
lock-up circuit receives EN FUNC OUT which is derived

from ADFA
OUTPUT
ENABLE
(received from the CPU as a bus grant)
ERROR is false (Figure 2-5). The true state of EN
INT
AMRM
when
FUNC
OUT
signifies
that the MCL has the NMI and is transmitting
data.
Whenever
EN
FUNC
OUT
asserts,
the
output
from
the
trans-fault lock-up logic (B TRANS DUR FAULT) is asserted. B TRANS
DUR
FAULT
1is
applied
to
the FUNK CSR logic (Figure 2-4) as an
bit in CSR0O. However, the assertion of EN FUNC OUT does not
error
an error unless A LOCK asserts at the same time. If EN
constitute
OUT is true when A LOCK asserts, then a fault occurred while
FUNC
transmitting. In this case, B TRANS DUR FAULT is
was
memory
the
locked-up
by
A FAULT, thereby holding B TRANS DUR FAULT asserted
to
CSRO.
When
CSRO
1is read, the B TRANS DUR FAULT error bit is
read

being

set.

The write-seg-fault lock-up circuit receives SEQ FAULT DETECT from
the
write
sequence fault logic if a write-sequence error oOcCcCurs.
The write-seg-fault lock-up circuit outputs WRITE SEQ FAULT to the
CSR

SEQ

logic

which

FAULT

an error bit

DETECT

1is

in turn asserts

in CSRO.

also appled to the NMI fault lock-up logic

its

three error outputs

(BDFA NMI

FAULT,

NMI

read,

the

FAULT, and A FAULT). A FAULT locks-up the NMI fault logic (holding
NMI
FAULT
asserted
on
the
NMI)
and the write-seg-fault logic
(holding WRITE SEQ FAULT asserted

to CSRO).

WRITE SEQ FAULT error bit

read

being

When CSRO

set.

The NMI FAULT line on the NMI, and the WRITE SEQ FAULT and B TRANS
DUR FAULT error bits in CSR0O, are cleared by reading CSR5. The CSR

2-28

FUNK
DBE

FIFO

(1X1)

DBE QUL

LAT

(12)

D1
DOUBLE

r—{>o- ~{LD

(12) | _BIT ERR

GEN

~P] PAR

CTRL
OlT PARITY

(2.7)
b —(FIG.

(13)

.
8)
DBE
-2
— ) AMOP
(FIG.2

——><:EEEAYUQ)}

BLOCK

A—}]

Y 1]

_FUNCTION<3>

- (FIG.2-3)

P](13)

DLY

SRS

READ CMD F1FO
(1X2)

i13)

LAT}—t-

—

READ

XI
6C-C

AMRM

(FIG.2-45)

AMM

DECODE
READ CMD.

READ CMD<0>

FUNCTION<2>

- pf LAT

(12) LM QUT
(F1G.2-52) __’

NMI

LAT

(12)

fij -

E:)

FUNCTION<1>J

DECODE

READ CMD<1>

BHAM

___f10)
-3 MWW
(F16.2.52)

_DFA VALID_ |

LATT

DFA VALID1

~—>e-—{LD

BLOCK 1

NT ERAOR

50
(Fig.2.3) - NSO Do
|

(FIG.2-2)—3

[ IEN FuNc our

)L-(Flc;.z-sz)

z I| AREA TASK_ CMPT
l (15

ENA
FA_OUTPUT ENABLE
ARFA
NOTE:

NUMBER DESIGNATIONS IN PARENTHESES REFER TO
ENGINEERING DRAWINGS CONTAINING CORRESPONDING LOGIC.

Figure

2-5

Read/Return

SCL0 48

and

Read/Continue

Logic

ADDR decoder decodes

address

input BMDP

STRD ADDR<4:2>

and outputs

CSR5 DECODE when the CSR5 address is decoded. CSR5 DECODE is ANDed
with
BMRM
EN
SERIAL RD (true for a CSR read function) to assert
CLEAR
FAULT. CLEAR FAULT clears the NMI-fault lock-up logic which
negates
the
FAULT line on the NMI and A FAULT from the NMI-fault
lock-up
logic.
The
negation
of
A
FAULT
releases
the
write-seg-fault
lock-up
logic and the trans-fault lock-up logic,
thereby clearing the two fault error bits in CSRO.

2.3.10

NMI

Confirmation

The
MCL
places
two confirmation bits (NMI CONFIRMATION<C1:0>) on
the
NMI
during
the
second
bus cycle after the command/address
cycle. The confirmation bits notifies the commander that:
The MCL does
The
The
The

The

MCL
MCL
MCL

confirmation

Table

2-4

NMI

not

acknowledge

bit

code

shown

Confirmation

State

0
1
1

1
0
1

in Table

command,

2-4.

acknowledgement
Command accepted
Interlock busy
Memory busy

four confirmation states are described
®

the

Confirmation Codes

NMI CONFIRMATION

The

receipt of

accepts the command,
is interlocked, or
is busy.

in the following.

Memory
busy -- The assertion of MEMORY BUSY asserts both
NMI
confirmation
bits.
The
assertion
of
MEMORY BUSY
requires
the
reception
of a new command (START NEW CMD
true) and that the new command be valid (FUNCTION INVALID
false).
In
addition,
one
of
the
following
three
true:

conditions must

NMI

BUSY

SEQ
FAULT
DETECT
from
the
write-sequence
fault
logic.
When
a
write
sequence
error
oOCCurs,
a
memory-busy
confirmation
code is placed on the NMI

MEMORY

to stop

new

from

commands

the

ARID.

from other

NMI

nexus.

WRITE
BUSY
from
the
block-command logic. Used to
indicate
that
the
memory
became
busy during the
first
write-data
«cycle
of
a
write transfer (NMI
MEMORY BUSY not asserted yet; see Section 2.3.7).

2-30

busy

Interiock
NMI

requires

that

true).
be

The

the

-—

the

unlock

The

during

new

command

there

The

signifies

"no

for

(FUNCTION

cause

data

processing.
that

NMI

from

The

CMD

INVALID
the

the

two

assert

(see

CYCLE

true)

and

false),

new

asserts

CYCLE

that

the

and

that

command

BUSY

(BLOCK

makes

negated

any

detected

NMI

because

the

will

CONFIRMATION<1:0>

NMI
BLOCK

COMMAND

COMMAND CYCLE

error

signals

generate

both

false).

the

ARID will

doing

internal

response.

DEAD
and

isolation

the

DEAD

exists,

this

the

time
data

performs
then

MCL

the

this

sent

ADFA

NMI

DEAD]l

NMI

isolation.

asserted

the

operation

not

DATA

CYCLE

talse)

write

NMI

2-31

used

DAD

is
to

progress

operation

isolated
for

ADFA

where

DEAD
sent

assertion

write

function.

NMI

BDFA

busy

must

may

the

task.

and

MCL

paths

the

COMMAND

1lack

(NMI

internal

FUNK

NMI

long

state

NMI

MDBC,

ADFA

COMMAND

condition.

parity

no-ack

the

its

areas

out

makes

BLOCK

INTERLOCK

assertion

ADFA

the

WRITE

its

perform

these

NEW

INTERLOCK

non-valid

During

ARID

and

block

false.

response

memory-busy

(UNLOCK

DEAD

generated

state

the

ack"

When

processing.

MCL
timed

negated

BUSY

assertion

valid

reason

addition,

asertion

The

(START

acknowledgement

also

asserts)

true).

the

either

INTERLOCK

The

state.
by

command

negated

must

false).

required

NMI

asserted

cause

CONFIRMATION<1>

conditions

CYCLE

accepted

COMMAND

ADDR

already

COMMAND

CONFIRMATION<KO>.

new

BUSY

MEM

(LOCK

unlock

has

interlock-busy

that

Command

requires

tries
memory

asserts

(ADFA

(INTERLOCK

locked-up

the

2. 3.7).

NMI

the

following

BUSY

INTERLOCK

memory

received

false.

Dbecause

conditions

the

state

Section

NMI

true).

negated

true

2.3.11

INTERLOCK

the

already

command

CONFIRMATION<KO>

COMMAND

when

TIMEOUT

command

MCL

asserts)

one

assertion

access

addition,

interlock

when

The

true:

-—

assertion

CONFIRMATIONK1>.

NMI

DEAD

used

sent

the

MRM

MEMORY

(COMMAND

would

data

NMI

also
the

from

the

inform

BUSY

CYCLE

require

and

input

2.3.12
Three
three

CSRs (Figure
bits
of
CSR0O
CSR0O

bits

2-4)
and two bits

of CSR3

reside

the

FUNK.

The

are:

B TIMEOUT --

WRITE

SEQ

from the
FAULT

lock

timeout counter

from

the

write-seg-fault

lock-up

logic

°®
The

B TRANS DUR FAULT -- from the

two

CSR3

bits

INTERNAL
the

SER

lock-up

logic

are:

ERR =--

derived

from AMRM

INT ERROR received

from

MRM

COLD
START -- derived from A COLD POWER UP received from
the
MCL
battery
backup
unit
(BBU).
A
COLD POWER UP
asserts
when power is applied after a power outage which
was
too
(battery
minutes).

CSRO
being
from

trans-fault

long
power

for
battery
maintain
s

power to
memory

sustain memory data
data
for
only ten

and CSR3 are read out serially with the serial bit selection
made
by
BMRM SERIAL RD<2:0> from the MRM. The serial bits
the two CSRs are output as FUNK CSR3 SER RB<3> and FUNK CSRO

RB<3>.

The
two CSR3 bits are cleared by commanding a CSR write (AMRM CSR
WRITE
asserted),
selecting
CSR3
(CSR3 DECODE from the CSR ADDR
decoder),
and asserting the appropriate feedback bit from the MDB
(BMDP
FB
DATA<K25>
to clear INTERNAL ERR and BMDP FB DATA<K26> to
clear

COLD

START).

The three CSRO bits
already described.

are

cleared

their

respective

logic

areas

2.3.13
The
MCL

Read/Return and Read/Continue (Figure 2-5)
becomes
a transmitter when it is sending read data to a
commander
that
initiated
a read transaction. When the MCL is to
transmit
tread data, the FUNK receives a two-bit read command code

from
the
MRM
specifying
the
data
transfer
as
a read/return
function
ot
a
read/continue
function.
It
also
receives
a
double-bit
error
signal
from
the
DCHK
which
specifies
the
read/return
or
read/continue
data
as
being good or bad. These
signals
are
used
to
generate a three-bit code for the NMI that
identifies the read data transfer (see Table 2-5).

When

the

MCL arbitrates

for

function, the NMI bus may be
processing
of the read data

the
processing
commands
from

1is
the

the

NMI

busy.
until

bus

In this
the bus

execute

read/return

case, the MCL stops the
is won. However, before

stopped, the FUNK would have received
MRM
and one double-bit error signal

2-32

two read
from the

DCHK.
FIFOs
are
used
double-bit error signal

The

case

the

MCL

the

MCL

wait

having

store

until

the

immediately
for

sections.

MCL

Immediately

CMD<1:0>

operation

are

(first

Also

received

from

new

ANDed
any

DECODE

DFA
CMD

READ

CMD

read-cmd

the

1is

DBE

they
The

a
a

BMRM

VALID.
or

for

is also clocked
to

the

ENABLE
ENABLE

the

input

CMD

CMPT

and

the

three-bit

informs

can

send

bits

the

MRM

read

FUNCTION<3:1>

data

codes

FUNCTION<K1>

being

DOUBLE

applied

the

error

the

when

mux

NMI

lists

the

bus

grant

TASK

CMPT

logic

(AMRM

access

functions

and
of

transmitted.
ERR

bits

then

through

could

DOURLE

bad

data.

codes

the

are

function
included

shown.

2-33

two

error

occur

the

AMDP

DBE

RIT

ERR.

a
is

latch output

from

MRM

ERROR

NMI

and

been

FUNC

onto

function

OUT

the
is

OUT
CMD

bit

OUT

codes.

Table

2-3

CPU.
FUNC

ADFA

obtained

enables

NMI.

NMI

associated

becomes

FUNCTION<2>

READ

the

False).

has

function

The

the

FUNC

NMI

input

double-bit

received

the

FEN

error mux.

data.

becomes

the

latches

longword.

INT

read

through

two

FUNCTION<3:1>

type

read-command

function

for

DECODE

and

become

MCL

true,

are

asserts

DECODE

the

double-bit

function.
2-5

ADFA

(NMI

function

which

presence

CMD<K1>

produce

This

read/continue

commands

BIT

AMRM

operation

the

READ

into

data.

what

bits

operations.

into a DBE FIFO latch.

code

read/return

VALID

clocked

whenever

that

specifies

FUNCTION<K3>.

read

are

clocked

read

lock-up

the

DFA

latches

DCHK

the

AMRM

ANDed

the

asserts

trans-fault

TASK

three

are

signifying

read/return

signal

also

command

specify

and

case

following

OUT.

output

from

the

read/continue

LW
LW

the

read/continue).

CMD<0>

two

Read

DECODE

READ

CMD

NEW
NEW

only

double-bit

OUTPUT

Table

and
in

2-6.)

BMRM

READ

FIFO

longword

OUTPUT

true,

are

longword

ADFA

with

DFA)

READ

DECODE

ADFA

Table

through

asserted

through

applied

OUT

AMRM

become

two

read/return

-and

mux.

DBE

AMDP

NMI

DFA

asserts

FIFO.

detected
passed

NMI,

and

bus.

discussed

MRM

data.

DECODE

pased

MRM

and

latches,

read-cmd

AMDP

VALID

mux

read-cmd

the

are

the

(read/return

which

first

signal

getting

the

(See

the

produce
longword

READ

DFA).

longword

data

commands

the

from

longword

read

won

NMI,

Gets

received

(next

two

has

2.3.13.1
READ

the

MCL

NMT

which

when

becomes

NMI

read-return

Note

that

the

for

the

four

Table
NMI

FUNCTION

1
1
1
1

Read Function Codes

2-5

Command

Read/return good data
Read/return bad data
Read/continue good data
Read/continue bad data

1
1
O
O

0
1
0
1

DOUBLE BIT ERR and READ CMD OUT are also applied to a parity
generator where they generate CTRL OUT PARITY. CTRL OUT PARITY is
it is used to generate the function/ID
sent to the ARID where
bit (NMI FUNCT T ID PARITY) which is placed on the NMI along
parity
the

with

read data.

2.3.13.2 MCL

Waits

for the NMI -- If the MCL has to wait for the

ENABLE and EN FUNC OUT are false and ADFA TASK
ADFA OUTPUT
NMI,
CMPT is not asserted to the MRM. The false state of ADFA TASK CMPT
stops the command processing in the MRM but not before it has sent
FUNK (and the DCHK has sent one AMDP
the
to
commands
read
two
The two read commands assert DECODE DFA VALID twice. DECODE
DBE).
FIFO-control latch asserting DFA VALID1l. DFA
a
1loads
DFA VALID
a second FIFO-control latch asserting DFA
to
applied
1is
VALID1l
still false at the time DFA VALID2
is
FUNC OUT
EN
If
VALID2.
asserts, BLOCK 2 asserts and does the following:

Asserts SEL FIFO to the read-cmd mux which selects the Dl

Latches the second stage of the read-cmd FIFO to hold the
bit (read/return) at the D1l input of
read-command
first

input

the

°®

from the

FIFO.

read-cmd mux,

Latches
VALID2

°®

read-CMD

the second stage of the FIFO control to hold DFA
asserted.

the
Enables
the
latches
read-command

block-1 AND gate asserting BLOCK 1. BLOCK 1
stage of the FIFC to hold the second
first
(read/continue) and the first stage of
bit

the FIFO control to hold DFA VALID1

Asserts

BLOCK

DLY

asserted,

to the double-bit error mux which

the D1 input from the DBE FIFO. BLOCK 2 DLY also
selects
DBE FIFO latch to hold the double-bit error
the
latches
bit associated with the first data longword.

When the MCL has acquired the NMI bus, ADFA OUTPUT ENABLE and then
FUNC OUT asserts. The assertion of EN FUNC OUT negates BLOCK 2
EN
1 to release the latch stages in the read-cmd FIFO and
BLOCK
and
two read-command bits in the
The
logic.
FIFO control
the
in
the double-bit-error bit in the DBE FIFO, are
and
FIFO
read-cmd
IX

2-34

clocked
out
double-bit-err

signals
have
to

(SEL

2.3.14

MRM

SLOW

the

system

normal
EN

Hold

MODE

executing
BDFA

are

for

If
case

causes

the
the

BDFA

HARBINGER

1is

and

normal

MODE

When

single-step

thereby

HARBINGER

1is

SLOW

the

MODE

MRM

and

2.3.15
NO

into
NO

keeping

mode

then

normal

One

single-step
NEXT

addition,
®

ended

negates,

which

(Figure

2-6)

received

from

asserts

BDFA

NEW

FORCE

ONE

EARLY

Locks-up

2.4

current

ARBITRATION/ID

2.4,1

NMI

DATA

data

parity

data

being

2.4.1.1
address
the

the

data

Data

bits

(and

Parity
parity

In
bit
bit

BLOCK

CYCLE
and

for

the

MRM,.

the

last

single-step

are

resumed,

unlatched.
BDFA

SLOW

the

HOLD

BDFA
ADFA

CMD

system

goes

have

stopped.

lock-up

latches

which:
NEW

CMD

LATE

bits

the

NMT.

the

2-7)
signal

When

line

an
input,
NMI
command/address cycle

ADFA

MRM.

that

carries

the

with

the

address parity bits) associated
between the NMI and memotry.

MCA

(Figure

clocks
B

BDFA

the

for

CMD

when

confirmation

bi-directional

transferred

parity

(ARID)

Parity

PARITY

NMI

MODE

execute

the

negates

the

SLOW

function

into

that

and

command

latches

clocks

system

and

MRM.
®

the

normal

BLOCK

CMD

goes

ADFA

resumed.

asserts

FIFOs
inputs

warning

write

HOLD

not

MODE

turn

write

assetrted

normal

Cycle

and

HARBINGER

SLOW

FUNK.

Dlocks

system

and

operation

BLOCK

the

CMD

HOLD

BDFA

but

BDFA

ADFA

CLOCK<2>

the

when

hold

BDFA

two

their

operation

occurs,

present,

stopped.

and

CLOCK<2>

throughout
In

are

negated

Force

asserted

clocks

this

asserts

command.

the

select

resumed.

module

presence

FUNK

and

mux

the

switch

single-step

When

the

MRM

until

then

clock

into

either

mux

the

2-6)

the

delayed

muxes

operation

stopped.

checks

which
CMD

are

The

(Figure

DLY)

normal

asserted

cycle.

HOLD

and

about

and

data

bits.

Command
1is

1is

asserts

BLOCK

stored

channels

clocks

write

NMI
through
the
read-cmd
respectively.
The negation of

and

their

signal

NMI

the

mux

FIFO

output

the

write

data

2-35

cycle.

DATA
(read

PARITY
or

write),

the
or

——

(FI1G.2-52)

—————————

ADFA SLOW MODE EN

NMI),.N.M_[_SLQW._NQDE__'. LAT
-4 LD

34— (Fia.2-34)

__BDFA HOLD CMD

="\
(5)

WRITE COMMAND

(F‘G'2‘3){ WRITE DATA CYGLE

BDFA
HARBINGER

>
>

__;

NO NEXT

LAT

BLOCK B

ONE CYCLE

(4)

(15)

RESET B

LAT
(15)

»|

Lar |—BESEL A,
(15)

AMRM RESET
CLEAR

LAT

(15

ADFA UNJAM

(15)

F_A_GLK_IN

LAT

A
[—CLEAR

(15)

|—FACK

F B CLK IN

FBCLK

LAT

FORCE

Me N

(FIG.2-2)<

BLOCK A

CLAT
(15)

—_N
Mg

9¢-¢

NOTE:
NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
SCLD-46

Figure

2-6

Clock

and

Command

Control

Logic

NMI

DATA

output

PARITY

from

the

parity

ADFA

GEN

the

error

DATA

error

PARITY

latched
into

and

PARITY

ERROR2

the

write-data

parity

ERR

asserts

1is

1In

and

during

command/address

ADFA

fault-detect

the

When

CSR

ADFA

fault.

data

OUT

and

(NMI

DATA

NMI
and

for

parity

Out

each

the

PARITY<3:0>
the

MDBC,

ADFA

PARITY

the

The

DATA
ERR.

and

ADFA

PARITY

ERRORI1

longword

during

ERROR2

confirmation

PARITY

MDBC,

DAD.

NMI.

with

DATA

then

the

generated

associated

ADFA

DATA

(via

DATA
NMI

PARITY

the

code

check

When

inputs

PARITY)

longword

are

aborts

the

NMI

the

applied

does

not

the

CSRO

cause

ARID

not
when

blocked.

logic)

the

Thus,

wrap-data

the

parity

to wrapped

invalid.

output,
of

ERR

asserted

would

ERR

fault-detect

PARITY

DEAD

NMI

the

PARITY<3:0>

the

gate

DAD.

which

applied

Parity

read

NMI

DATA

data

outputs

byte

OUT

PARITY

transmitted

parity

composite

the

data

from memory

correct

the

parity

whenever

1is

required

because

single-bit

error

corrected

AMDP

error

data.

DATA

SBE
a

AMDP

the
DATA

applied
bit

occurs.

parity
SBE

the

error

generated

corrects

which

the

occurs.

generated
Hence,

read

parity

applied

single-bit

(PAR30)

also

parity

correction

corrected,

generated

parity

XOR

gate.

bits

PARITY<3:0>

before

the

are

BDFA

correction

single-bit
for

true,

wused

generator

DAD

the

from

asserts
to

and

applied

NMI.

BDFA

XOR

being

Parity

data
then

DEAD

Also

cycle.
false,

ADFA

bit

the

FUNK,

and

DAD,

the

2.4.1.2

1logic

GEN

DAD

ERROR1

no-response

the

parity

parity
to

NMI

from

DEAD

PARITY

PARITY,

bits

the

detected,

logic.

1In

path

bit

NMI

parity

ADFA

DATA

PARITY<3:0>

1into

MRM.

detector.

GEN

byte

for

the

forces

When

bit

and

ARID

the

ADFA

operation

the

ADFA

compares

FUNK

cycles.

error

bad-data

Dbecome
error

received

asserts
the

parity

are

detector

PARITY<3:0>

address/data

parity

1is

ARID

the

whenever

not

this

latch.

right

flipping

PAR30.

The

output

HOLD

DATA

PARITY

1is

then

gated

onto

the

from

the

XOR

gate

(OUTPAR)

false,

OUTPAR

NMI

DATA

is
is

PARITY

applied
loaded

line

When

into

the

true

state

memory

has

use

latch

and

OUTPUT.

OUTPUT

1is

the

NMI,

OUTPUT

DATA

PARITY

bus

true

NMI.

If
is
1is

and

HOLD

memory

DATA

PARITY

false

when

false

arbitrating for but has not yet won the
isolate the memory from the NMI, and HOLD

true

latch

the

OUTPAR

won.

2-37

parity .bit

until

the

NMI

2.4.2
NMI Function/ID Parity (Figure 2-7)
NMI
FUNCT
1ID PARITY is a bi-directional signal

line

that

carries

the

(or

write

mask).

parity

bit

for

the

function

2.4.2.1
function

Parity
In
-When
and
1ID
parity bit

write),

and

the

function

and

commander

an input, NMI FUNCT ID PARITY is the
for a command/address cycle (read or
and

mask

parity

bit

for

parity

error

write

data

cycle.

NMI

FUNCT

1ID

PARITY

applied

detector

where

the
function
parity and the ID (or mask) parity are checked. The
ID
(or
mask)
1is input from the NMI as NMI ID MASK<3:0> and then
latched
to
become
1ID<3:0>.
1ID<3:0>
1is
applied
to
a
parity
generator
which
generates
the
parity
bit,
ID
XOR. ID XOR is
applied
to
the
parity error detector along with function parity
bit
CTRL GEN PARITY generated in the FUNK. CTRL GEN PARITY and ID
XOR are compared with NMI FUNCT ID PARITY and if a parity error is
detected, the parity error detector outputs CTRL PAR ERR.
CTRL

PAR

ARID.

ERR

becomes

Outside

ERR,

hence,

the
it

CTRL

PARITY

ARID,

too

CTRL

ERR which

1is

PARITY

ERR

ADFA

PARITY

asserts

then

output

from

the

ORed

with

DATA

PARITY

ERROR1

and

ADFA

PARITY

ERRORZ.

CTRL
PAR
ERR
1is also
the fault-detect logic)

2.4.2.2

Parity

parity

bit

Out

for

the

read/continue

applied
to CSRO

to
in

-- When

function

and

the
the

output,

fault-detect
logic.

logic

and

(via

CSR

NMI

commander

FUNCT

PARITY

ID during

the

read/return

operation.

CTRL
OUT
PARITY
1is the read command parity bit generated in the
FUNK.
CTRL OUT PARITY is applied to a parity generator along with
the
commander ID (POP IDK3:0>) from the ID/mask logic. The parity
generator
output
(ID
PAR)
1is
a
composite
parity bit for the
Uit

iivg

PAR

gated

error

true

FUNCT

Fault Detect (Figure 2-8)
FAULT
DETECT
1is asserted to
parity

NMI

2.4.3
ARID

OUTPUT

the

detects

OUTPUT.

onto

state

when

PARITY

memory

has

line

use

the FUNK MCA whenever
incoming data.

the

true

NMI.

the ARID

A
data parity error signal is received
and
checking logic when a parity error

from the parity generation
is detected on the address

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Or

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w1tk
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received
parity

being
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the
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e
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parity
detected

from
the

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the
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NMI.
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the

and

function

Either

parity

NMT
NI
o

CTRI,
CLiRL

checking
and

error

PAR
AR

logic

ERR
ORR

1 a
1S

when

(or

write

mask)

will

assert

ARID

OUTPAR
¢ —
2

—G

__pARs0 [] PAR | PAHITY<5.00

(1)

AMDP

GEN

NMI

DATA SBE

__v* PARITY.

HOLD DATA PARITY-

- (F1G.2-2)
(FI1G.2-28)

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(F1G.2-10)

OUTPUT

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<3:9>
(FIG.2-2))— BRI
EAR ¢ S
DET

6t-¢

(FIG.2-3)—p—DMLDEAD

IR,

BARITY

ERR

(FIG.2-19) 4~
(FIGS.2-3,

2-46)

<«

(FI1G.2-8)

CIRL PARITY ERR

NMI_FUNCT
NMI*‘%
ID

e
ERR

PARITY

(1)|

EQE

1D PAR| PAR
1)

CTRL

_GEN

CTRL

QUT_PARITY

u__mfl‘lDS_QL_QL(F|GA2_9)

PARITY

(F1G.2-5)
(FIG.2-3)

DET

(1)
(FIG.2-9) ——————

1D XOR

ARID
NOTE:
NUMBER DESIGNATIONS

PARENTHESES

REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

Figure

2-7

Parity

Generation

SCLD.52

and

Checking

_z:>_’ LAT MW
(FIG.2-7)

CTRL _PAR ERR
TR ] B,CTRL

FAULT|

LAT

]

—»{LD

>>(F!G.2—3)

&(Fle.

B DATA

»{DATA | PARITY FAULT

f‘“’j 2-13)

FAULT
LAT

—PILD

%BDFA NMI FAULT

ARID

]

NOTE:

THE LOGIC IN THIS FIGURE IS CONTAINED ON
SHEET 4 OF THE ENGINEERING DRAWINGS.

Figure

2-8

Fault

SCLD 51

Detect

Logic

CTRL PAR ERR is applied to a CTRL-fault latch which outputs B CTRL
PARITY FAULT. Likewise, a data parity error asserts the input to a
data-fault

latch which

outputs

DATA PARITY

from
the
FUNK, latches the two fault
error they may contain until the fault
The

latched

FAULT)

are

fault-errors

applied to CSRO

NMI

2.4.4.1

1ID/Mask

BDFA NMI

FAULT

PARITY

FAULT and

DATA PARITY

in the ARID CSR logic.

(Figure

ID/Mask

2.4.4

(B CTRL

FAULT.

latches thereby holding any
is cleared.

2-9)

-- When an input,

NMI

ID MASK<3:0>

is the

of
the
commander
nexus
for
a
command/address
cycle (read or
write), or the write mask for a write data cycle. NMI ID MASK<3:0>
is
latched
to
become
1ID<3:0>
which
is
applied to the parity
generation and checking logic for a parity check.
A.

Commander

In
a
command/address cycle, ID<3:0> (commander ID) is applied to
the
input
of
a six-deep ID/hex FIFO. The commander ID is loaded
into the FIFO by READ CMD which asserts for every new, error-free,
:
P
T
DNEPA
COMDCZ 92N
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read command received by the memory (BDFA CMDK2> is false for read
see

Also

entered

from

the

Table

2-1).

1into the

FUNK.

BDFA
TM

F
2

FO is a hex flag (BDFA SIZE<K1>) recei v e
[
—~
T
<1> is asserted for hex reads i Se e 1L4a o}
P

2-2).

2-40

commands;

———»(FIG.2-7)

Lar

NMI

NMI ID

MASK<3:0>

(f)

IQAEEX

(F1G.2-10)
POP

XI
1P-2

¢J

< -

STORE

(10)

LD [
(9/10)
(‘fl UNLD
y

BDFA

READ

LMD (1)

Cfl

“J

NEW

FIFO

igggx

RETURN)

DECODE FIRST
LW|
|

)

(DREEADECONTII‘I‘I_\LAJIE)

ARID

(FIG.2-3)

<MD LATE

(F1G.2-12)

(E)UTPUT

(F1G.2-10)

(9)

(READ

(FIG.2-10)

SIZE<1>

(FIG.2-19)

(F1G.2-45)

’(\,\J}A?MERROR

STORE HEX

BDFA CMD<2>

S0FA

E”fgp

_MASK<0>

[ADFA MASK<3:0>

(5X6)

1D<3:0> [ AT kgD <3:05

(FIG.2-7) 4—

ADFA

ID<3:0>

AMRM READ|

READ

¢@@fllmhe—(mez4m
AMRM READ

Défi%fl‘
(7)

<ABMRM

(FIG.2-52)

;

NOTE:

NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS CONTAINING

|
CORRESPONDING LOGIC.
SCLD-50

Figure

2-9

1ID/Mask

Logic

The commander ID and its associated hex flag is stored in the FIFO
the memory transmits the requested read data. At this time,
until
the

FIFQO

is unloaded to supply the

ID to go with the

The FIFO can store up to six read commands,
enters
B.

the

"busy"

state

and asserts

read data.

after which the memory

BUSY on the NMI.

Write Mask

write data cycle, ID<3:0> (write mask) is output to the MRM
a
In
as
ADFA
MASK<3:0>
where
it
functions
as
the
write mask. In
addition,
ADFA
MASK<0>
1is
sent
to
the MDBC to specify a mask
operation.

2.4.4.2

the

Out

commander that

-- When an output, NMI ID MASK<3:0> is the ID of
regquested

the

read data.

The
1ID/hex
FIFO
1s
unloaded
for the read/return commands of a
longword
read,
an octaword read, and the first half of a hexword
read. At these times, the FIFO is unloaded to supply the commander
that goes with the read data. The hex flag associated with the
ID
unloaded along with the ID. The FIFO is
1is
function
read/return
not
unloaded
for
read/continue
commands because the same ID 1is
used.

A special case occurs during the second octaword read of a hexword
read
when a read/return command will occur but the FIFO is not to

be
unloaded
(same
ID
for both octawords). The hex flag signals
FIFO. The
the
of
wunloading
the
1inhibits
and
condition
this
FIFO is controlled by the FIFO control
1ID/hex
the
of
unloading
logic

described

in the

following.

BMRM
NEW
LW
is
asserted from the MRM for every new longword of
read
data.
BMRM
NEW
LW
enables
a
read-command decoder which
READ<1:0>) generated by
(AMRM
commands
read
two-bit
the
decodes
a
for
LW
FIRST
DECODE
asserts
decoder
read
The
MRM.
the
read/return

operation

and

DECODE

NEW

for

a read/continue

operation.

FIRST

DECODE
logic

read

where

they

DECODE

and

NEW LW are sent to the arbitration

are used to acquire

(and hold)

the

NMI

for the

data.

addition,

causing

unloads

the

DECODE FIRST LW is applied to the FIFO control logic

assert

stored

POP

FIFO

(via an OR gate).

1ID (STORE ID<3:0>)

and loads

B POP FIFO

into a latch

where
1t
becomes
POP
1ID<3:0>.
If
the
memory has won the bus
(OUTPUT
true),
the
commander
ID
1s gated to the NMI as NMI ID
MASK<3:0>.

When
for

B POP FIFO negates,
any

read/continue

POP ID<3:0>

operations

that

is
may

latched to provide
follow.

the

POP

ID<3:0>

logic
As

for

the

(STORE

1If

(STORE

HEX

was

going

the

may

reads,

monitors

read

signal
OUTPUT

senses

holds

the

When

not

to
EN

the
to

OUTPUT

hence

FIFO

these

FIRST

OUTPUT

asserts,

the

new

two

the

POP

checking

read

the

longwords

will

used.

win

the

NMI

bus,

before

commands
have

are

issued

The

memory

has

signal

until

read
halts

longword

second

DECODE

control

logic

won

not

two
it

both

FIFO

has

flag

control

operation

same

MRM

hex

FIFO

four

(memory

control

associated

logic.

the

false

DECODE

and

associated

hexword

the

will

control

second

unload

the

decoder

determine

the

immediately

data.

assert

1issued

command

its

applied

senses

LW because

been

generation

FIFO,

and

not

commander

does

the

logic

will

parity

function/ID parity.

from

FIRST

have

the

unloaded

same

the

to
the

control

DECODE

memory

processing
FIRST

FIFO

the

also

true),
of

commands

applied

unloaded

was

the

assertion
be

also

generation

HEX)

logic.

the

won

NMI

the

OUTPUT

bus.

NMI)

asserts.

logic

asserts

the

second

longword-read

with

POP

FIFO

operation,
Note

that

FIFO

load

and

unloading

flush

2.4.5

memory

command

the
all

FIFO
the

arbitration/hold

NMI

bus

memory

when

the

won

read

data

1is

read

hexword

after

the

memory

Several

2-10.

the

bus,

the

are

cases

places
read

the

read

logic

results

new

IDs

from being

loaded,

arbitration
to

rest

the

which

into

request
a

read

use

hold

the

block

general

gets

the

bus

right

but

does

not

get

the

operation.

DECODE

gate

FIRST

and

causing
ADFA OUTPUT
EN
(providing there
ENABLE

read

necessary

also

data
to

hold

Bus

the

logic

LW asserts

enabled

AND

NMI

gate.

the

NMI

DAD where

during

NMI.

2-43

the

bus

NMI

while

Figure

away

bus

right

Longword

Read

signifying

MEMORY ARB
Memory

ENABLE to assert which in
is no internal error) and

applied

Right Away

ID/mask

the

octaword

diagram of

and

the

and

categories:

arbitrates

from

the

data.

arbitrates

Gets

signal

Memory

asserts

hold

Memory

When

removed

transmission

removed,

two

request

transmitted.

)

the

This

2.4.5.1

inhibits

FIFO.

places

request

divided

data

arbitration

considered

are

ERROR)

POP

IDs.

the

any

INT
B

Logic

transmitted.

transmits

(AMRM

asserts

stopping

has

read,

error
and

1logic

arbitration

cases

The

FIRST

the

stored

memory

has

CMD)

Arbitration/Hold

The

the

internal

(READ

1is

turn

away

DECODE

read/return

the

NMI

via

granted

the

bus

asserts OUTPUT
ADFA OUTPUT

OUTPUT.

functions

bus

cycle.

transfer

not

HOLD

(F1G.2.7) €22TA

XI
vv—-¢

DECODE_NEW UNj}

DECODE: FIRST LW (FIG.2-9)

2
ARB |_ARB_DLY

(It
U——

LOCK

MSRL'_‘DG:W

rB_f

amg

NMI
NMt

L.
l(-‘g

HOLD FB DATA

(FIG.2-2)

PARITY |

Lplen

CLR

SECOND LW|

HOLD

1(7)

SECOND

W [

LOGICH-

(7)

»CcLR

LAT

- (7)
<¢—oI

(F1G.2-9)

BLOCK ARBHOLD

ARID

QUTPUT P (FIGS.2-7, 2-9)
7

ADFA OUTPUT ENABLE

¢ | TERROR
G
ADFA_UNJAM }(F'G-2'15)

(FIG.2-2)

((F1G.2-12)

NOTE:
NUMBER DESIGNATIONS
REFER TO

ENGINEERING

CONTAINING

PARENTHESES

DRAWINGS

CORRESPONDING LOGIC.

SCLD 39

Figure

2-10

Arbitration/Hcld

Logic

Note

that

asserted

With

AMRM

placed

INT
the

ERROR

NMI.

Memory

NMI.

Memory
and

cycle),

OUTPUT

NMI,
AND

1is

from

the

to
the

DECODE

The

gate

the

read
is

detected,

NEW

true

NMI

memory

the

and

AMRM

not

RESET

cycle)

during

which

CPU

state

hold
of

OUTPUT

MEMORY

complete.

1in

during

the

first

MEMORY

HOLD

1is

2.4.5.3

asserts

the

data

Gets

NMI

bus

for

HOLD

the

second

longword

NMI

MEMORY

HOLD

the

enable

MEMORY

NMI

bus

grant

causes

the

keep

NMI

cycles

can

asserted.)

Timing

NEW
1last

two

data

that

NMI

MEMORY

HOLD

cycles
only

the

won.

read

occurs

HOLD

With

MEMORY

1is

longword

DECODE

HOLD.

NMI

the

2-11

asserted

Memory

second

data

but

when

continue

not

during

the

NMI

the

to
is

asserted

fourth,

needed

for

NMI
the

cycle.

function

the

read/continue

DECODE

that

Figure

three

first

OUTPUT

the

Arbitration/Hold

Back-to-Back

first

NMI

assertions
asserted

Note

following

2-11

DATA

two

HOLD

—

MEMORY HOLD

NMI

Figure

and

OUTPUT

OUTPUT EN

NM!I

(Figure

transferring

asserts

to maintain
and

(the

first

the

NMI

NEW

false)

OUTPUT

MEMORY ARB

the

1is

keeping

for

cycle

data

HOLD

true

Read

NMI

next
read

DECODE

(The

Octaword

NMI.

MEMORY ARB
ADFA OUTPUT ENABLE,

the

NMI.

arbitrator

thereby

HOLD.

data

Away

asserts

second

ARBHOLD

for

unreliable

asserted

asserts

causing
On

states

which

cycle

transferred

bus

longword

ARBHOLD

The

BLOCK

arbitrating

data
also

Right

FIRST

assert.
first

BLOCK

(the

Bus

the

(providing

the

error

memory

ARBHOLD

DECODE

granted

while

cperation.
an

true,

BLOCK

Gets

2-11)

the

UNJAM.

2.4.5.2

EN,

internal

prevents

SN E——

ADFA

which

and

FIRST

inhibits

assertion

ARB

Bus

Right

Another

Read

the

being

asserts

the

NMI.

OUTPUT

Longword
--

and

QUTPUT

the

read

data

transferred

the

NMI,

DECODE

FIRST

again.

enable

AND

the

re-assertion

FIRST

LW)

2-45

NMI
and

The

gate

Read

DECODE

OUTPUT

DECODE

cycle,

and
of

Away

Function

FIRST
assert

from

second
true

which

the

read

states
asserts

MEMORY

ARB

(due

asserts

NMI

MEMORY

the
HOLD

to hold the NMI for the next cycle during which the read data from
the

second read function

transferred to the NMI.

Hexword Read -- A
Away
Right
Bus
the
Memory Gets
2.4.5.4
1in Section
described
as
reads
octaword
two
1is
read
hexword
bus cycle
one
least
at
that
dictate
s
requirement
MCL
2.4.5.2.
Hence,
read.
hexword
a
of
octawords
two
the
between
elapse
octaword
second
the
for
occur
must
NMI
the
for
re—-arbitration
read.

Memory Does Not Get the Bus Right Away - Longword Read -2.4.5.5
NMI MEMORY ARB on the NMI. An ARB lock
LW asserts
FIRST
DECODE
.
.
*—]fl
'.l.
~
request and asserts ARB DLY. The
arbitration
the
senses
circuit
reset by OUTPUT, however, as the
held
usually
is
1lock circuit
ARB

does not have the bus, OUTPUT is false. On the next cycle,
FIRST LW negates but ARB DLY keeps NMI MEMORY ARB asserted

memory
DECODE
on

the

NMI

long

necessary.

means of an enabled AND gate, ARB DLY asserts HOLD FB DATA and
By
HOLD DATA PARITY. HOLD FB DATA ia sent to the DAD where it latches
up the read data until the bus is won. HOLD DATA PARITY is sent to

the

does

parity

the same

generation
thing

and checking section of the ARID where it

for the data parity.

wins the NMI bus, OUTPUT is asserted and clears
memory
the
When
thereby removing the arbitration request
«circuit,
lock
ARB
the
from the NMI.

DATA

In addition,

the assertion of OUTPUT negates HOLD FB

and HOLD DATA PARITY, thereby allowing the read data and its

associated parity to transfer out to the NMI on the next cycle.

2.4.5.6

Memory
Reads

Does

not

Back-to-Back

Get

the Bus Right Away - Two Longword

or an Octaword Read -- If the memory

arbitrates for, but does not get the bus right away, the MRM could
read commands before it halts its processing of
two
issued
have
read operation. This could be two back-to-back longword reads
the
a read/return and the first read/continue of an octaword read.
or
The

following discusses these two situations.

asserts NMI MEMORY ARB on the NMI but no memory
LW
FIRST
DECODE
received from the NMI arbitrator (in the CPU) so OUTPUT
is
grant
are false. NMI MEMORY ARB is locked up by ARB DLY
OUTPUT
and
EN
which is also asserting HOLD FB DATA and HOLD DATA PARITY to latch
the read data and the read data parity in the DAD.

The

assertion

ARB

DLY enables a second-longword logic block

the DECODE FIRST LW and DECODE NEW LW signals. If
monitors
which
the operation that initiated the arbitration was an octaword read,
the
second-longword
logic will sense the assertion of DECODE NEW
first read/continue of the octaword read. The
the
by
caused
LW
LW by asserting
NEW
DECODE
to
responds
logic
second-longword
and OUTPUT EN
won
is
bus
the
When
gate.
AND
an
to
LW
SECOND

2-46

asserts,
HOLD

the

and

AND

NMI

read/continue

OUTPUT
SECOND

LW.

read

Had

data

which

fourth

this

gate

MEMORY

the

clears
The

the

two

read

would

have

and

enabled

the

would

have

sensed

output

SECOND

2.4.6

the

interrupt

to
An
A

the

bus

DECODE

(Figure

for

FIRST

memory

The

single-bit

error
error

two

CSR3,

BDFA

CSR3

that

CSR3

1is

inputs

latches.
INTERNAL

ERR

into

load

The

errors

WRITE

MDP.

BMDP

TIMEOUT

which
The

winning

signal

that

were

interrupt

Interrupt

enable

allows

AMRM

INT

turn

ERR

INTERRUPT

CPU,

and

cause

asserts
then

RCPU

INT

FUNK

MEM

bus

ARID

have

been

would

then

already

issue

interrupt, they must
appropriate bits,

signals

ERR

the

write

and

four

SBE

EN,

After

are

ERR

lock

and

bits

DBE

latches

negated

INT

INTRPT

four

assert

when

these

(BMDP

are

written,

lock-up

AND gate

the

AND

the

gate

CSR

that

input

INTERRUPT

which

ARID

output.,

MEMORY

interrupt

right

the

which

the

left

CPU.

allowing

CPUs.

ERR

from

INTERRUPT

2-47

CSR3

assert

the

INTERRUPT

right

enables

MRM

outputs

MEMORY

left

the

MEM

TIMEOUT

With

respectively

applied

interrupt

enables

DAD

WRITE

load-enables

and

the

CSR

from

LCPU

from

feedback

DATA<31:28>

INTERRUPT

asserts

CSR

asserts

INTERNAL

NMI

assert

INTERRUPT

asserted

command.

signals

INTRPT

1is

CSR WRITE)

input

MEMORY

TIMEOUT

interrupt

ERROR

aserts

from

TIMEOUT

would

latch.

enable

The

Likewise,
the

the

asserted.

signal

INT

lock.

NMI

DLY,

read

AMRM

logic.

the

longword

logic

the

and

ARB

addressed.

one

EN,

respective

enable

four

indicating

receives

the

EN,

the

signals

first

second

may

DECODE

being

CSR

latch

from

written
the

MRM

true,

DATA<31:28>)

enable

the

Each

third

asserted,

asserted

logic.

any
of
these errors can cause an
interrupt-enabled by writing CSR3 with the

from

the

asserts

negating

error

double-bit

asserted

the

HOLD

of
the

timeout

write

2-12)

four

indicating

also

thereby

MEMORY

reads,

assertion

transfer

bus

(due

arbitration,

Before

the

logic

NMI

logic.

the

CPU.

internal
lock

NEW

longword

the

await

following

in
the

keep

second-longword

Interrupts
of

second-longword

enabled

results
bus

Winning

DECODE

back-to-back
initiated

discussed.

Any

the

cycle.

functions

re-asserted
the

This

hold

second-longword

assertion

longwords)

been

enabled.

HOLD

ADFA TIMEOUT
timeout
turn

lock.

asserts

(Fle.z-aa)—al

AVRM INT_ERROR

(F1G.2-3)

» (FIGS.2-9, 2-10, 2-14)

ADFA TIMEQUT

—

BMDP FB DATA<31>

INT

INTERNAL

a7 | _ERR EN

(6)

(5)
EN

BMDP FB DATA<30> | §I TAT

TIMEOUT
LEN

XI
8¥—-¢

BMDP_FB_DATA<29>

—)“

SBE
LAT | EN

L EN

BMDP FB DATA<28
s>

(FIG.2-28)<

AMDP LD PAGE ADDR

AMDP_DBE

INTERS RUPT
—fi—fl!—l

Tock

e
—

(6 )-INTERRUPT

NMI LCPU
MEM _INTRPT

NMI RCPU
MEM INTRPT

SBE

HNIEBRUPT

NMI

—p1 CLR (6)
6

DBE

LAT |E

(5)

INT_ERR

(6)

SBE

(6)}——»|

ERR

(6)

TIMEOUT
LocK

w4 CLRA

——pf EN

—! CLR

(6)——»

(5)

(F1G.<
2-17)

LOCK

o)1

——1(6) )~

wlen

Dee

LOCK

DBE

INTERRUPT

p|cir (6)

CSR3

(FIG.2-2) —
{(F1G.2-51)

—H

(FIG.2-2)

BDFA CSR4 DECODE

‘

(F1G.2-13)

ARID
NOTE:

NUMBER DESIGNATIONS IN

PARENTHESES REFER TO

ENGINEERING DRAWINGS CONTAINING CORRESPONDING LOGIC.
SCLD-49

Figure

2-12

Interrupt

Logic

SBE

and

assertions
INTERRUPT

SBE

enable

Note

that

order

for

the

interrupt.
1is

PAGE
in

DBE

error

interrupt
while

into

interrupt
CSR4

the

ARID.

BDFA

CSR4
the

the

DECODE

interrupt

error.

DBE

the

BDAF

assert

interrupt
false)

reading

ADDR

assertion

will

channel,

will

interrupt

asserts

applied

PAGE

determine

The

DBE

error

DCHK whenever

true)

error

(AMDP

cleared

read,

single-bit

being

cause

assert

channel.

CSR4.

When

the

CSR4

DECODE

the

four

lock

bits

CSR3.

circuits

signal.

2-13)
bits of

CSR0O

and

four

FAULT)

CTRL
when

received

PARITY
the

ARID

and

three-bit

enables

RB<3>.

FAULT

from

the

CSRO

fault-detect

DATA

read

fault

SER

the

PARITY

code

logic.

FAULT

from

the

are
MRM

read
(BMRM

bits

out

the

ARID

sent

the

CSR

logic

RB<K3>

ARID
in

DAD.

2,4,7.2
received
MRM

PARITY

RD<K2:0>)
SER

the

DCHK

checked

(AMDP

error

the

-- The two CSRO bits are the function/ID/mask parity
CTRL PARITY FAULT) and the data/address parity fault

serially

SERTIAL

double-bit

signal

2.4.7
CSRs (Figure
The ARID contains two

bits

DBE

from

AMDP

double-bit

DATA

memory

error

When

the

senses

CSRO

DCHK

double-bit

locked-up

Fault

asserted

1into

DAD

out

asserted

data.

the

1is

read

lack

signal

bit

ADDR
the

signal

2.4.7.1
CSRO
fault
bit (B

respective

INTERRUPT
generates

double-bit

DCHK

clears

allow

SBE

which

the

interrupt

from

where

ADDR must

from

single-bit

double-bit

that

which

INTERRUPT.

INTERRUPT

error

the

PAGE

bit

AMDP

single-bit

asserted,

channels

DBE

MEMORY

AMDP
a

CPUs.

AMDP
a

similar

INTERRUPT

asserts

interrupts

there

DBE

CSR3
-- The CSR3 bits are the four interrupt-enable bits
from
the
interrupt logic. BMRM SERIAL RD<2:0> from the

enables

RB<3>.

ARID

2.4.8

the

four

bits

CSR3

SER

RBK3>

Memory

The

ARID

and

cannot

condition

Busy

asserts

any

(Figure

the

new

out

serially

the

CSR

logic

ARID
in

the

CSR3

SER

DAD.

2-14)

memory-busy
a

read

sent

the

command.

following

three

2-49

NMI

The

when

ARID

the

senses

inputs:

memory
a

busy

memory-busy

AMRM

BUSY REQ from the MRM
AMRM INT ERROR from the MRM
AMDP BUSY REQ from the MDBC

®
®
Any
and

these

NMI

MEMORY

three inputs
BUSY on the

*
*

will assert NMI MEM BUSY ARB
NMI and to the FUNK MCA.

the

NMI

NMI
MEMORY
BUSY
notifies
all
NMI
nexus
not
to send any new
commands
to
the
memory.
NMI
MEM
BUSY ARB is an identical but
separate
NMI
line that connects only to the arbitration logic in
the
CPU.
NMI
MEM BUSY ARB disables the arbitration logic in the
CPU
so
that
no
nexus can arbitrate for the memory. A dedicated
line is used for NMI MEM BUSY ARB to reduce signal loading so that
the
CPU
arbitration
1logic
will
be notified of the memory-busy
condition as quickly as possible.
An NMI requirement is that the memory asserts busy on the NMI, for
a minimum of 2 bus cycles+. Delay logic is used in the memory-busy
logic
to
meet this requirement. If the MRM or the MDBC asserts a
busy
request,
it
asserts the output of an OR gate which in turn
asserts
NMI
MEMORY
BUSY and NMI MEM BUSY ARB. On the next cycle
(50
ns
later)
an AND gate receives a delayed output from the OR
gate.
If
the memory busy request is asserted for only one cycle,
the AND gate is enabled and holds busy asserted on the NMI for one
more

cycle.

When
the
busy
request
1s
asserted for more than two cycles, a
second
50
ns
delay disables the AND gate thereby making the NMI
busy signal a direct function of the busy request.

2.4.9
Clocks and Clock Control
NO
NEXT
CLOCK<3>
1is
asserted

(Figure 2-15)
from
the DAD during

operation,
1It,
1in
turn,
asserts
various clocks throughout the ARID.
AMRM

RESET

gate)

CLEAR

ADFA

UNJAM

The

and

throughout

from
B

from

MRM

asserts

CLEAR A

the

NMI

clocks

the

ARID.

are

RESET

the

asserts

ARID
only

received

and

single-step

BLOCK

RESET A and

(via

stop

an OR

MCA.
CLEAR

from

the

and

NMI

CLEAR A.

and

are

distributed

AMRM
INT ERROR and AMDP BUSY REQ assert memory-busy as a means
of
stopping
other
nexus from sending commands or data to the
memory.
AMRM
INT
ERR
asserts
when
the MRM has detected an
internal
error. AMDP BUSY REQ asserts when the MDB is full and
cannot

single-bit
+

the

and

BLOCK

allow

any

new

data,

when

the

MDBC

has

detected

error.

time

for

other

nexus

re—arbitrate

2-50

for

the

NMI

bus.,.

INTERNAL
ERR EN

:
l

}

Flee.12)

|
—»

| 47 |

B TIMEOUT

SBE_EN

|_B SBE EN

eeDBEEN
[ "7

B DBE EN

|
I

(5)

ARID GCSR3 |

——~:j%§;\SER RB<3> o

f—

5
i

|
|

'
I

l__l

CSRO

B CTRL

PARITY

FAULT

(FIG-2-12)4:

ey | |
|

B DATA
PARITY
FAULT

BVEM SERIAL RD<2:0>

Ly 48Pae
_SER

RB<3>_

(Fl1G.2-51) _):__,.__._, o

—

'
|

|
|

-1 »EN

ol _ar

» EN

(5)

)

TiMeourt

—

16-¢

CSR3

ERR EN

(5)

]

B_INTERNAL
:

LaT

ARID|

NCTE:
NUMBER DESIGNATIONS

IN PARENTHESES
REFER TO ENGINEERING DRA
CCNTAINING CORRESPONDING LOGIC
SCLD-43

Figure

2-13

CSR

Logic

(F1G.2-2)

(F1G.2-19)—-

(FIG.2-12)

AMPRM
INT ERROR
AMDP_BUSY REQ

(FIG.2-34)—3

AVRM BUSY REQ[—2—"

he?

l~—>-—‘—
NS 5

50 NS

BUSY_ARB
S
MEMORY 3 NMI
,A_,._.’| z i BUSY

D AR e NMI

)—[>o—

M—(FIG.2-3)

N
ARID

NOTE:
THE

LOGIC

SHEET 8

THIS

OF THE

FIGURE

ENGINEERING

CONTAINED

DRAWINGS.

SCLD-44

Figure

2-14

Memory

Busy

Logic

NO NEXT

LAT
(11)

CLOCK<3>

BLOCK A

—

AMRM RESET

ufle.2403{j

LAT

+———

F A

CLK

RESET B| |

LaTFEESELA

(11)

F A CLK

clEaR A

|
I

F A CLK1
FACK

(12)

F B

Car|cLEAR8| |

BLOCK

)

4_“

!
(11)
)

(HG.ZWS)J

’

TM12

CLK

B CLKf

CLK

ARID
NOTE:
NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
SCLD-47

Figure

2-15

Clock,

Reset,

2-53

and

Unjam

Logic

MDP OVERVIEW (Figure 2-16)
2.5
The MDP is comprised of the following:
memory data buffer: a multi-port RAM (four ports)
=
MDB
with
sixteen,
36-bit
1locations.
Eight
1locations
are
reserved
for
memory
addresses
and eight locations are

reserved

for

write

data.

MDBC
=
memory
data buffer control: an MCA that selects
the
1location
in the MDB where the write data is placed,
and selects the write data that is output from the MDB.

)

DCHK
read

data check: an MCA that performs an ECC check of
=
generates correction bits for single-bit
and
data

errors.

2.5.1

the

MDB Address

cycle,

command/address

the

memory

address

(ADFA DATA

ADDR<31:0>) and the address parity bits (ADFA GEN PARITY<3:0>) are
from the DFA and applied to the W write port of the MDB.
received
IN SEL<2:0> from the MRM is mux selected as the address
ADDR
BMRM
places the memory address into the
it
MDB where
the
to
input
INPUT WRT EN<3:0> from the MRM
AMRM
MDB.
the
of
section
address
loads the memory address into the selected location.
MDB Address Out

2.5.2

The memory address and the associated parity bits are available at
address read port. The address (BMDP STRD ADDR<25:4>) is
MDB
the
NAB as AMCL
the
onto
placed
and
TTL
to
ECL
from
converted
are sent
APARK3:0>)
STRD
(BMDP
bits
parity
address
The
ADDR<25:4>.
command/address
a
generate
to
used
are
they
where
MRM
the
to
parity

bit

for

the

arrays.

address selection is made by selection bits AMRM ADDR

The

memory

QUT

SEL<2:0>

from

the

MDB

Data

2.5.3

the

write

PARITY<3:0>

parity

data

from

the

MRM.

«cycle(s),

DFA

bits respectively.

ADFA DATA ADDR<31:0> and ADFA GEN

are the write data and the write data

The load command remains AMRM INPUT WRT

LD INPUT DATA asserts from the DFA
BDFA
MRM.
the
from
EN<3:0>
the MDB address mux to select B
causing
cycles,
write-data
during
MDB location select signal.
the
as
MDBC
the
DATA IN SEL<2:0> from
B DATA IN SEL<2:0> is generated by the data-in select logic in the
is divided into two sections (an X
section
data
MDB
The
MDBC.
four locations. The data-in
having
each
buffer)
Y
a
and
buffer
in the X buffer. For
1location
first
the
selects
logic
select
increments through
logic
select
data-in
the
writes,
lti-longword
1
~ ther X-buffer
| o=
locations. BDFA LD INPUT DATA asserts from the
cr o

X E N

o At

2-54

[‘

READ
PORT

ADDR<25:4>

ADDRESS)

BMDP STRD

BMOP_STAD APAR<3.02 9|

ADDR)q— -.AMRM ADOR OUT SELs2:02. ¢ ,__}‘F'G-z‘“)

DATA

READ

———

PORT

ATA<31.0

(FIG@.2-1)¢

—

<31:0>

*
N BLDATA IN

SEL<2:0>

ADOR

ECL | DATA

SEL<3:0x>_. € ——

NAB

TTL

[

BMEM, ADOR IN SELc2:0>

I—

A DATA

/ADDH o

BYTE

PARITY<3.0> '

our

3 R'S%E_&ds.b’ms

DATA<31:05]

B F

ATA

NAB

ECL

SEL<2:0>

AWM
FB

(F1G.2-33)¢

—1 .

AMRM INPUT WAT EN<3:0>

BMOP FB

(FIG.2-1)4¢

HF1G.2:33)

o1 f————

DATA<31:0>

Do
AMARM MPR

G6-7

DATA SEL

BMDP
<

E‘E\I:z':‘

_MOB

A IN

DATA

fi_iflsLyEl—g-EkfiLy(ma.z-aa)

(FI1G.2-33)

BMDP

B FB

CMDg1>

Ly
B

FEED BACK { B FB

SELECT

DATA

SEL<2:0>

LOGIC

SEL<2.0>
A SELECT

DATA IN

Y. OUT

DATA

SELECT
LOGIC

—

SELEC?UT

A LOAD X

LOGIC

SEL«<3:0>

BMAM WRIT
M
WRITE

ALOAD Y

DOUT<1:0>

}(FuaAz-as)

BRI

1TY<3:0>

GEN
ATA
LOGIC

(Fla.2-1)

DATA

%‘ACPT

GQooD
ATA

ey | AMCL

BMDP

BAD DATA
BMOP

BIT
STORAGE

SAA‘%

&iz EARITY,_,_______’F—"_EABHL’
LAY

WRITE ENABLE

NAB
HATE

—

WRITE

ENABLE
LOGIC

MDBC

(

F1a.2.1

AMDP DBE

.2-1)

< ——

AMOP BIT

EC
e

AMDP. DATA SBE

LOGIC

—jg
- SORRECT<20>| copprenon

DECODE
LOGIC

le¢——SYNOROME<6:0> |

DATA<31.0>

ARCY CHECK

BMAR

BITS<6.0>

DATA<38:32>

2922
¢ NAB

DCHK

SCiD-an

Figure

2- 16

Memory

Data

Path

(MDP)

Block

DFA

each

for

write-data

causing

cycle

DATA IN SEL<L2:0> to

increment.

When the write data in the X buffer has been transferred to the
the MRM asserts BMRM CLEAR BUF USE informing the
memory arrays,
1logic that the X buffer can be used for the next
data-in select
the next write command occurs before the data in
If
write command.
transferred to the arrays, the data-in select
1is
the X buffer
logic places the new write data into the Y buffer. With the X and
the data-in select logic outputs A BUFFER FULL
full,
Yy buffers
This places
AMDP BUSY REQ to assert to the DFA.
causing
memory-busy on the NMI to halt any more commands to memory.

airF £ A
S aY=X af
the next
Hence,
on a FIFO basis.
operates
The data buffer
been
has
data
X
the
that
indicates
USE
BUF
CLEAR
assertion of BMRM
A
asserts
then
logic
select
data-in
The
arrays.
transferred to the

SELECT

buffer

OUT

to the data-out select logic specifying that the Y

to be unloaded next.

MDB Data Out

2.5.4

The write data and the associated parity bits are available at the

MDB

data-read

converted

DATA<31:0>.
sent to a

port.

The

write

data (BMDP WRITE DATA<31:0>) is

placed onto the NAB as AMCL
bits (B BYTE PARITY<3:0>) are
parity
The write-data
MDBC where they are used to
the
in
parity generator

from

ECL

TTL

and

generate a data parity bit for the arrays.

The

data selected for output is determined by A DATA OUT SEL<3:0>

from the data-out selct logic in the MDBC. BMRM CMD ACPT from the
MRM informs the data-out select logic that the write command has
been accepted by the arrays. The data-out select logic selects the
location 1in the X buffer. For multi-longword writes, BMRM
first
WRITE CMD<1> from the MRM specifies the following longwords as
"next," causing the data-out select logic to increment
being
through the other X locations.

The data-out select logic always selects the MDB X buffer unless A

SELECT

OUT

1is

asserted by the data-in select logic, in which

case the Y buffer is selected.

Write-Enable and Bad-Data Bits
2.5.5
Write—enable and bad-data bits are generated in the MDBC and
supplied to the arrays with each write-data longword. The bits are

generated in good-data logic and write-enable logic, and stored in
an eight 1location bit-storage area. The storage area is divided
into a four-location X section and a four-location Y section
similar

the

MDB.

good-data logic receives ADFA PARITY ERRORIL and ADFA BAD DATA
The
from the DFA. ADFA PARITY ERROR1l indicates an NMI parity error was

detected
sequence

in the DFA. ADFA BAD DATA indicates a write command
detected in the DFA. Both ADFA PARITY ERRORI
error was
TMA

2-56

and

ADFA

GOOD

BAD

DATA

DATA must

The

write-enable

the

DFA,

and

write-enable
®

be false for
bit-storage area.

the

logic

AMDP

1logic

this

from

the

longword

the

GOOD

DATA

data-in

1is

For

three

the

data-in

the

MDB,

the

GOOD

asserted

The

two

and

for

asserted.

Data

parity

the

2.5.7
Read

parity

data

converted

associated
operation;

bits

written

are

asserts

write

are

LOAD

data.

the

LOAD

into

the

bit-storage

the

A
X

LOAD X

section

Y to the
WE
bits

the

buffer

places

held

into

bits

bit-storage

area

the

bit-storage

asserted

other

and

three

BAD

become

from

the

the
select

MDB.

except

the

held

into

the

area.

then

section

buffer

placed

BMDP
on

LOAD

are

data-out

increments

the

area which loads
Y section of the

which

respectively

the

into

operations,

ENABLE

data

bit-storage
into
the

pairs

storage

the

Read

read
from

BYTE

DATA

BAD

DATA
are
the

bit-storage

will

The

when

(inverse

AMCL

NAB. The bits
logic selects

bit-storage

PARITY<3:0>)

the

composite

applied

bit

sent

longword

Data
data

(BDFA

the

longwords

bits

PARITY)
on

will

operation

generator

bits.

which

contained

longword

SELECT
output

OUT

locations

Parity

parity

data

masked

of
the

operations.-

write-enable
the

placed

DOUTK1:0>

data

not

that

sort-of-write

three

ENABLE

for multi-longword

2.5.6

DBE

(see

bits

WRITE

from

The

operation,

associated

operations,

1IN

the

BMDP

data

output

AMDP

portion

indicates

the

output

corresponding
always

1),

the

2-1).

must

into

LOAD

and

output

WRITE

selected

Table

MASK<KO0>

logic

locations

and

from

informs

read

and

multi-longword

the

bits

DATA)

AMCL

select

DATA

DBE

assert

MASK<0>

(see

the

written

with

bits

ADFA
CMD<0>

CMD<0>

during
AMDP

logic

bit-storage.

For

and

three

GOOD

asserts

bit-storage.

loaded

(BDFA

masked-write

this

logic

pairs

the

IN WE

select
1IN

When

and

being
and

multi-longword

locations

the

and

BDFA

operation

false

error

ADFA

1.4.3).

other

0),

Section

DATA

area.

asserted

for

MDB

written.,

DCHK.

operation

should

longword

The

GOOD

masked

read

Dbe

CMD<0>

a masked

uncorrectable

not

The

good-data

CMD<0>

the

this

DCHK

BDFA

from

operation.,

area.

receives

DBE

the

and

the

over
on

Operation
the

from
TTL

ECL

bit

NAB

AMCL

the

array
to

and

boards
become

2-57

the

with

arrays

bad-data

from

along

parity

the

MDBC

MDB
the

are

generated

DATA

Note

that

data

write-enable

(BMAR
ARCV

and

(BMDP

PARITY.

represents

applied

bad-data

parity

bits.

DATA<31:0>)

DATA<31:0>

and

is
then

applied
to a mux in the MDB. The mux outputs the read data to the
DFA
as
BMDP FB DATA<K31:0>. BMDP FB DATA<31:0> is also applied to
ECC check logic in the DCHK.

Seven

ECC

array

board

<check

bits

along

(BMAR

with

each

DATA<K38:32>)
data

longword,

are

received from the

converted

from TTL to

ECL,
and
then
applied to the DCHK ECC check logic as ARCV CHECK
BITS<6:0>.
The
ECC
check
1logic re-generates the ECC check bits
from
the
data longword and compares the re-generated bits to the
received check bits to determine if there is a bit-error.
If
a
single-bit
error is detected, the check-logic asserts AMDP
DATA
SBE and a syndrome code (SYNDROME<K6:0>) to correction decode
logic.
AMDP
DATA
SBE
enables the correction decode logic which
decodes
the
syndrome
code
to generate correction bits AMDP BIT
CORRECT<2:0>.
The
correction bits are sent to the DAD in the DFA

where

they correct

the

bit-error

the

data

longword.

If
a
double-bit
error is detected, the check-logic asserts AMDP
DBE
to the DFA where it generates a "read bad data" function code
and

NMI

2.5.8
In

interrupt.

Masked Write Operation

a masked write

operation:

Write

data

Read data

The
the

loaded

is used

modified
arrays in

into the MDB

to overwrite

the normal manner.

the write-data.

write
data is transferred
the normal manner.

from the MDB to

The
read
data
overwrites the MDB data via the C write port. The
read
data
(ARCV DATA<K31:0>) is applied to the C write port along
with parity bits AMDP GEN PARITY<3:0> generated from the read data
longword.
The read data is byte-enabled to overwrite the MDB data
by AMRM

The

FB WRT

read data

EN<3:0>

from the MRM.

ECC checked as

in the case of a normal

read.

single-bit
error
is
detected
AMDP
DATA
SBE and SYNDROME<K6:0>
function to provide correction bits (AMDP BIT CORRECT<2:0>) to the
DAD in the DFA where the read data is corrected.

AMDP DATA SBE is applied to mask-correction logic in the MDBC. The
mask-correction
logic
1is
enabled
by BMRM NEW LW (a longword of
read
data
has been received) and a negated AMRM READ CMD<K1> (the
read data is part of a masked write; see Table 2-6).

2-58

Table
AMRM

SBE

Read

CMD

Command

Code

longword

MDP

{(masked

write)

First

longword

MDP

(masked

write)

1longword

DFA

First

longword

DFA

The

READ

2-6

vValid when

used with

mask-correction

logic

BMRM NEW

responds

LW.

the

assertion

by:

)

Asserting

MASK

BUSY

REQ

the

ARID

place

and

the

read

data

where

the

memory-busy

FUNK

switches

ERROR which
DFA.

path

the

NMI

the

ADFA

the

wrapped

overwrites

the

AMDP

generate

data

causes
DFA,

around

assertion

BUSY

REQ

halt

NMI

DEAD.

ADFA

allow

the

returned

the

MDP

via

AMDP
the

traffic,

to
and

DATA

causes

NMI

DAD

data

AMDP

NMI

DEAD

corrected
to

the

MDP

the

W write

switches

port.

Asserting

the

load

The

the

data-in

address

write-enable
The

the

bit

longword

logic

was

when

The

the

informed

and

read

data

byte-enable

SEL<2:0>

proper

retained

corrected

the

into

where

DATA

masked

the

data

MDB

was

AMRM

write
select

returned

overwrites

signal

location.

the

MDB

INPUT WRT

MRM,

was

detected

write-enable

logic

the

DCHK,

AMDP

the

MDBC

which

negates

DBE

is
the

associated

1is

sent

with the modified write-data longword.
the array module but is not written into

array.

2.5.9

CSR

Reads

CSR

read

When

DATA

SEL

data

from

operation

the

The

MDB

combined

with

other

2.6

MEMORY
MDB

ports.

1is
The

a
read

MDB

arrays.

The

MDB

CMD<0>

error

the

use

BDFA

according

double-bit

select
use

from

mux

data

MDB.

EN<C3:0>

CORRECT

input

read

for

the

data

ADDR

corrected

operation

asserted

MASK

port

data-read

write

executing,

cause

port

data

CSR data

the
1is

and

rather
fed

are

placed

designated

MRM

onto

2-59

asserts

mux

than

back

DATA BUFFER (MDB)
(Figure
multi-port RAM having two
ports

the

data-path

read
the

the

data

DFA

from

where

MPR

write
it

the
is

NMI.

2-17)
read ports
the

AMRM

select

address

and
read

two

write

port

and

B
(FIG.
e

[is

DATA 3 > o
ADEA <25:24
_ ADDR<25:245r7)]

3} EARITY<

ADFA GEN PARITY<0> ot

I» apa oaTa

09-¢

DFA_GEN ;

(FIG.

2-2)

l Z
(FIG.

2-18)

r‘& DATA INPUT EN ” |

]

B DATA IN SEL<2:0>

(FIG. 2-48) B
(FIG.

2-23)

(FIG.

2-3)

(FIG.

2-45)

—j

INPUT

_DATA

2-2)

(FiG. 2-3)
" SIB0 ADDR<4:22p

STRO
BaDP STRO | BMDP
ADDR«28:2>
ADDR«28:4

02 . (FIG. 2-19)
RIIY<31

(F1G.2-49)
g
BMDP WRITE DATA<232.<20:19>

DATA

HEAD

ADDR

BMDP

WRITE DATA<3L:0»

plTor

BU TEST
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TTL
EN

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4 POl
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APAR<INOz.

3 uas
DATA<31:0x
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GENEPATE

DATA 4= &

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(F1a.

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DATA<31:0>

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2-48)

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ECL

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BUAR

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DATA<31.9> ¢Nap

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(FIG.

ACIKIN

2-2,
2-27)
2-4)

2-61)

mn‘.r_ifiuz;fl){( £1G. 2-23)

» - ADDR

|
I

EN_MASK CORRECT
_BDFA

B STAD

B_INPUT

ADDR IN SEL<2:02.. ]

W WRITE

BMD° STRD ADOR<3:2y,
B8 STRD

PORT

ADDR<3) 0x

BMDP GFECIAL ADDR<4> o,

‘ 8 STAD ADDRs31:282.<1:92. .9 po

19 ADDR

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A SEL

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R

B.UF)';E!}g

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DATA

BUFFER

ADFA_GEN

L oo

COND_OCTA

—

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ADDFESS
BUFFEA

I A..,..E&H!T.Xsk-fi

A DATA OUT SEL<3:0>

o4—Plok—I3

—

B 8%.0.

FIG. 2-48)
2_25)) >—3%
K

INPUT wAaT

J EN<ao»

AP
FB

VAT EN:3:0> (1@,

2-45)

[ R

2-34)

BMOP FB DATA<31:28>
BMDP FB DATA<31:0>

BMDP FB DATA<20>
BMDP FB DATA«<25»
BMDP FB DATA<28>

£CLY a8

Figure

2~ 17

Memory

Data

Buffer

(MDB)

Block

Diagram

the

data

port

and

read

The

buffer

the

half
MAR4

storage

area

36-bit

the

storage

where

the

arrays.

(read

and

page

1is

write

)

the

address

for

MDB

made

data

Figure

2.6.1

and

2-17

address

the

address

STRD

The

command

bits

address

sent

the

FUNK

sent

ADDRK25:4>

ADDR<25:4>,
address

AMCL

for

the

ECL

NAB

backplane.

testing.

Note

that

address

from

the

wused

the

from

second

SECOND
next

OCTA

which

octaword

addition,

applied

The

RAM

area

B
the

write

data

bits.

The

lower

through

the

transmission
area

the

data

the

(locations

command

used

view

RAMs
RAMs

addresses

store

each
have

MDB

the

MAR4

error

processing
been

combined

operation.

the

MRM

the

port

the

parity)

from

port

BMDP

composite

STRD ADDR<31:0>.

ADDR<K25:2>,.,

parity

BMDP

selection

from

1is

output

not
a

CSR.

specifies

TTL

Address

used.

STRD

STRD ADDR<4:2>

also
ECL

are

and

the

BMDP

STRD

CSR.

BMDP

becomes

AMCL

NAB

bus

the

arrays.

enabled
NAB

TEST

NAB

ENABLE

used

for

maintenance

during

normal

STRD ADDR<4>

address
flips

STRD

asserted

where

STRD ADDR<K1:0>

DAD where

This

(and

output

TEST

bit

addresses

specify

location

contiguous

36-bit

board.

outputting

being

executed,

(the

XORED with

for

port

being

bit

read

addressed,

two

the

SECOND

hex

same

read

address

octawords.
MRM

This

reads

BMRM

wrapped

both

address.

octaword

from

operation.

used

hexword-read

the

bits

the

and

octaword

are

bits

transmission

four

command

sent

memory

MRM.

parity

translated

always

The

overall

translator

OCTA

addresses.,

bit.

ADDR<K25:4>

the

addressable

logging.

MAR4

BMDP

The

W write

parity

where

prior

the

storage

locations

four

outputs

MAR4

TTL

buffer

outputs
are

1is

the

identical

The

the

becomes

ADDR<3:2>
STRD

error

STRD ADDR<31:26>

ADDR<K25:2>

prior

Port

port

for

half

stored

four

and

generated

stored

parity

buffer.

APAR<K3:0>

bit

of
one

(locations
is

address

with

associated

four

address

Read

read

consists

to present

Address

The

designated

location

are

use

are

and
data

the

ports

upper

One

byte

write

area

write

The

15)

arrays.

port.

address)

through

The

write

32-bit
of

buffer

The

iocations*,
(or

port.

asserts

When
BMRM

addresses

the

hexword

read

locations).

STRD ADDR<4>
DAD

storage

becomes

third

area

actually

used.

2-61

BMDP

SPECIAL ADDR<4>

stored

address

but

only

bit

half

and

for

CSR

the

the DAD before being XORED with BMRM
to
sent
1is
It
selection.
SECOND OCTA because CSR selection requires the address as stored
in

the

MDB.

addresses

The

be outputted through the address

read port are

a four-bit select signal at the port ADDR input. The
by
selected
most significant select bit is a 1 (+V) so only the address buffer
locations are selected. The other three select bits (AMRM ADDR OUT
buffer location. The three select
address
the
select
SEL<2:0>)
hence the MRM controls which
MRM,
from the
received
are
bits
addresses output

through

the

address

read port.

reading CSR1), the output of the data
(not
operation
wormal
read
port
1is
write data (and parity bits) from the data buffer.
The four parity bits output the port as B BYTE PARITY<3:0> and are
sent to the MDBC where a composite parity bit is generated for the
MAR4
.

The

data
to

write

data

outputs the port as BMDP WRITE DATA<31:0>. Write

bits BMDP WRITE DATA<23> and BMDP WRITE DATA<20:19> are sent

the

MRM,

WRITE

BMDP

applied

DATA<31:0>

to the NAB bus

1is

translated

from

ECL to TTL and then

as AMCL DATA<31:0>.

The data to be outputted through the data read port is selected by
select signal at the port ADDR input. The four select
four-bit
a
(A DATA OUT SEL<3:0>) can address all sixteen locations of
bits
operation, the most significant
normal
For
buffer.
memory
the
the port outputs write data from the data
and
0
is
bit
select
buffer.

significant select bit is switched to a 1 when the CSRI1
most
The
1is to be read. The CSR1 address
buffer
address
the
1in
address
the address buffer through the data read port and is then
outputs
fed

back

to the

DAD,

via a mux,

BMDP FB

DATA<K31:0>.

four select bits for the data read port are received from the
The
the data buffer.
from
outputs
data
what
controls
which
MDBC
the CSR1 address is to be selected from the address
when
However
puffer,

2.6.3

the MRM provides the select bits
W Write Port

the
to
input
The
from
data/address

(via the MDBC).

memory buffer through the W write port is the
its
and
DATA ADDR<K31:0>)
(ADFA
DAD
the

associated parity bits

(A SEL PARITY<3:0>).

GEN
from ADFA
derived
are
PARITY<2:1>
SEL
A
bits
Parity
PARITY<2:1>. ADFA GEN PARITY<2:1> is generated in the DAD on bytes
two and three of the data/address. Parity bits A SEL PARITY<3> and

2-62

SEL

PARITY<0>

whether

the

port

false

and

PARITY<0>
DAD

ADFA

they

address

the

port

(ADFA

GEN

write

PARITY<3>)

and

GEN

PARITY<0>).

This

32-bit

data

longword.

location
four-bit

input.
the

The

the

most

or
port

select

input

which

the

select

The

port

address,

the

The

select

two

BDFA

write-data
EN

data

MASK

The

the

MRM.

the

writing

the

when
DAD

INPUT
in

alters

the

is
SEL

the

parity

bit

the

bits

parity

(<25:4>)

all

bits

written

are

asserted

DAD

generated

parity

the

data

sixteen

data

for

and
byte

byte

the

full

selected

the

obtained

input

mux

input

data,

The

are

selects

bits

the

W port

ADDR

locations

through

mux

W port

the

mux

(BMRM

ADDR

three

obtained

from

The

the

SEL<2:0>)

buffer

switched

D1
(B

the

input.

selects
is

MRM.

the

bits

which

the

locations

its

(+V)

address

from

bit

other

the

read-data

correction

Write

input

the

read

portion

the

read

data
1its

data
by

the

being

byte

enable

process

Data

write

and

operations,

and

1is

address

SEL<3:0>)

obtained

asserted

unmasked

bus,

bits

locations

eight

bits

port

With

generated

DATA

data

the

select

input

the

which

SEL<2:0>)

buffer

MDBC.

signals can switch the mux to select its D1 input.
INPUT
DATA
obtained
from
the FUNK, during a

the

write

2.6.4

This

MDBC

cycle,
by

parity

address

significant

buffer.

CORRECT

corrected

bit

three

are

write

most

the

1is

bits

The

other

eight

select

which

Either

case,

four

whether

select

One

can

selects

written.

the

this

DATA

INPUT

select

from

the

parity

bit
The

input

1input.

data

bits

generated

provides

The

INPUT

PARITY<3>

data.

Dbuffer.

written.,

data,
bit

input

according

write

boards,

the

input

according

write

significant

address

the

buffer.

selects

address
If

four

memory

which

where
select

select

inputs.

<25:24>.

parity

DATA
DO

SEL

bits

which

address

which

array

(ADFA

The

PARITY

address

the

their

<7:4>.

MAR4

muxes

address,

reflect

input

via

port

select

bits

select

NIBBLE

(XORed)

muxes

input

the

muxes

that

the
3

input

address

used
If

the

generated

bits

are

input

cycle

into

the

The

other

read

data

was

MDB.

AMRM

INPUT

WRT

EN<3:0>

four

bits,

the

MRM

all

selected

masked

being

allowing

and

processed.

when

written

enabled
input

being
MDBC

masked

the

bytes

write

to
be

from

controls

written

for

for
the

operation.

Port
the
of

memory
a

longword

buffer

masked

(ARCV

associated

write

through

DATA<31:0>)

parity

the

operation.

bits

2-63

from

(AMDP

write

The

data

the

memory

GEN

port

during

consists

array

NAB

PARITY<3:0>).

The

read

data

ECL

enabled
The

from

the

become
by

BMRM

<four

NAB

parity

parity-generate

The

location

The

select

buffer.

masked

write

data.

write
With

writing

CSR

logic

the

cycles,

The

CSR1

from

the

DAD,

bits
the

the

only
are

read

the

AMRM

four

overwriting

the

from

TTL

translator

data

specific

the

FB WRT

bits,

ADDR

the

which

overwrite

MRM

bytes

MDBC

EN<3:0>

the

MDP

input.

locations

from

the

selected

port

eight

buffer

being

written
at

obtained

data

enabled

input

CSR data

DAD.

BMRM

inputs

the

inputs

data

(BMDP

mux,

and

multi-bit

BNUM<2:0>),

SEL<2:0>)

address

byte

incremented

all

ECL

the

from

the

controls

the

according

the

Logic

convert

MRM.

generated

1in

illustrates

1is

translated

TTL

field.

select

RD<2:0>

enable

mask

2-18

can

data

process

2.6.5

Figure

The

the

data

select

port

the

associated

are

read

bits

read

the

The

the

The

DATA<31:0>)

from

input

places

MRM.

GATE
bits

where

select

three

(BMAR

DATA<31:0>,

logic.

three-bit
data

NAB

ARCV

and

the

mux

have

CSR1

alternate

been

SER
the

one-bit

RB<0>)

bit

(ADFA

bit

<4>

the

MRM

BMRM

SERIAL

logic
eight

serial

outputs.

output
number

(ADFA

from

outputs.

board

ADDR)

the

area
from

serial-read

one-bit

number

MEM

from

MDB

logic.

the

serial

array

board

and

the

supplied

and

converted

memory-address

write-data

mux

primary

array

serial-read

the

into

from

RD<2:0>

and

cause

inputs

carries

supplied

SERIAL

ALT

the

obtained
(ADFA

PRM

BNUM<2:0>),

decode-RAM

MDB.

The

CSR3 data (BMDP CSR3 SER RD<2:0>) are three bits obtained from
serial-read logic, that indicate the array-board size. A three-bit

code

from

bits

from all

three,

The

each

array

the

eight-bit

CSR0O

data

The

board

boards

serial

(BMDP

CSRO

eight-bit

specifies

(ARRAY

the

array

SIZE<23:0>)

board

are

size.

output

The

CSR3

segments.

SER

RD<2:0>)

revision

code

most-significant

bit

consist

of:

volts

(BMRM

SERIAL

RDK2>)

2~-64

the

serial-read

select

bits

ADFA ALT
BNUM<2:0>

[ -

BMDP CSR1

SER RB<0>

BMDP CSR3

SER RB<2:0>

ADFA_MEM ADDR

BMDP_CSR3

SER RB<2>

SER

READ

ADFA PRM_BNUM<2:0>

MEM

— SIZE

BMDP CSR3
\___SER RB<1>

2-2)

‘
SER

FEAD

(FIG.

(

Fla.

MM
)
SIZE 5<2:0>»

)

(

<0>
MEM

2-17)

6<2:0>

2.
<2:1>

SIZE

G9-¢

SEL be—

(FIG.

¥ 00,

s4>

4<2:0>

MEM SIZE

3<2:0>

MEM
,

<2>

SEL j4—
BMDP CSR3

\___SER RB<0> | SER

READ

1:0

|€&1=1°Z

SIZE 2<2:0>

MEM SIZE

1<2:0>

€|

-MEM SIZE 0<2:0>

SEL |4

BMDP CSRoO
[

BMDP CSRO

)

READ

BMDP CSRO
SER RB<1>

<7:0>

REV

CODE

BMDP CSRO
SER RB<«0>

SEL|€4—

BMRM SERIAL

RD<2:0>

BMRM SERIAL 1
RD<2>

—{(FIG.

2-51)

§CLD-470

Figure

2-18

CSR

Logic

2.2

)

RCV_ARRAY

SIZE<23:0>

ARRAY

, SIZE<23:0>

<{ NAB

MEMORY DATA BUFFER CONTROL (MDBC)

2.7

MCA

main function of the MDBC is to control operation of the MDB.

The

MDB operations controlled by the MDBC are:

1location in the data buffer for the write

Selecting

the

SEL<2:0>.

Enabling

the W write port. The select
via
loaded
1is
that
data
B DATA IN
1is
data
write
the
to
points
that
signal
by

the

of the MDB to write the data is done

MRM.

for the
data buffer
the
in
location
the
Selecting
data that is read from the MAR4 and loaded into
feedback
buffer via the C write port. The select signal
data
the

)

B FB SELL2:0>.
is
data
feedback
the
to
points
that
Enabling of the MDB to write the feedback data is done by
the

MRM.

the write data in the data buffer and the CSRI1
Selecting
data in the address buffer that is to be unloaded via the
data read port. The select signal that selects the write

CSR1 data is A DATA OUT SEL<K3:0>. The MDBC
the
or
data
complete control of the unloading process as the MDB
has
does not require an enabling signal to unload data.

Other

functions

to:

the MDBC are

Store up to eight pairs of bad-data and write-enable bits
the data stored in the data buffer, and

associated with
them as
unload
unloaded

their

from the

associated

data

longwords

are

MDB.

data

parity bit for the write data unloaded

Generate

Generate a busy request for the FUNK when the data buffer

from

the

full.

Notify

MDB.

the

MRM

masked

when

write

operation

completed.

Generate a delayed internal-error signal for the MRM.

Generate a write strobe for the decode ram.

data buffer portion of the MDB is divided into halves; an X
The
buffer consisting of four longwords (locations 0 through 3) and a

four-longword Y buffer (locations 4 through 7). Each buffer holds
the write data associated with a write command. The MDBC always
tries to place the write data into the X buffer. The only time the

MDBC

will

already

has

place

data

into

the

buffer is when the X buffer

data.

The data from only one write command is placed into a buffer. If a
1is in the X buffer and another longword
data
longword of write
IX

2-66|

write
even

command
though

In the
writes

the

are

new

three

1is

DATA or

the

AMRM

WRITE

CMD

first

cycle

Hence,

longword

READ

<1:0>).

description

The
block
illustrations

the

and

the

input

the

output

1longword

first

quadword

Normal

function.

the

buffer

buffer.

cycles

writes

are

command

unload

transfer

octaword

implicitly

(BDFA

command

(BMRM

only

the

transfer.

included

the

MDBC
2-23,

contained
2-27).

and

MDBC according to function.
the illustrations.

four

The

four

All

the

and

for

considered

Octaword

1is

The

MCA
1is
2-25,

done

for

normal

writes

During a masked write, feedback data from the NAB
into the MDB to overwrite the data already there.

are

2-19

octaword writes.

masked
writes.
is
also
1loaded

2.7.1.1

into

the

load

quadword

two

Loading Data into the MDB
write data into the MDB is

Figure

of normal and masked writes, octaword
only way the MDBC knows the size of a

diagram
of
the
(Figures
2-19,

writes

placed

CMDK1>)

illustrations
divide
the
I/0 signals are shown

Normal

locations

duration

MDBC

2.7.1
Loading

longword

empty

following discussions
are
described.
The

transfer
INPUT

occurs,

there

major

block
areas

first.

Write

With

diagram
shown

and

the

Figure

Y Buffers

Empty --

data-in

selection

MDBC
2-19

are

defined

below.

Full Logic -- indicates that data is stored in the X or Y
buffer by asserting B X VALID or B Y VALID respectively.

Input
status

Load
CMD
Detect
-- senses load commands and the
of
B
X VALID. Indicates whether the new data is
the
X
or
Y buffer by asserting B NEW X or B NEW Y

for

respectively.

[

Input

IN
the

Load Counter -- provides a two-bit select output (B
COUNT<K1:0>) used as the two least significant bits of
B

DATA

SEL<K2:0>

as
a
select
1input
enabled, the counter

Also

used

for
the
X
&
Y bit-storage.
is incremented each bus cycle,

input

selection

signal.

When

X
&
Y bit-Storage -- an eight-deep storage buffer which
stores
the
good
data
and write-enable bits associated
with

When

write

BDFA

the

data

data
1is
INPUT
DATA

longword(s)

stored

be loaded into
into the MDBC and

entire
transfer
(one
<cycle
for
an
octaword
transfer).
does the following:

the MDB,
holds it

for a longword
The assertion

2-67

the

&
the

buffers,

FUNK
asserted

asserts

for

the

transfer; four cycles
of BDFA LD INPUT DATA

[

Asserts
parity
the

A
DATA
(rather

W write

INPUT
EN to the
than
the address

Latches
B
LOAD
Y
1IN which is
output mux. B LOAD Y IN is 0 due
(the X buffer is empty).

Enables
output

the
(B

Switches

applied to the selection
to B X VALID being false

input-load counter. Once enabled, the counter
IN COUNT<1:0>) is incremented from a count of

CLK

the

outputting

and

CLK.

selection output mux
B

LOAD

significant

bit

its

(presently
DATA

Enables
el
2 o~ la

the

input
-load- CMD

WIil1icCil

asSsercs

into

the

empty.

AT TITAT

INIL VY

buffer.

NEW

.Lllu_l.k,al_.l.ug

VALID

asserts

input
as

loglc
amArr

l_ua\_

new

LOAD X via

(Flgure

2- 20)

Aok

gu;ug

uat.a

the

and

most

1IN
bits. This starts
000 which is then
counter to select

false

thereby

the

SEL<K2:0>,

detect

D1
0)

COUNT<1:0> as the two least significant
the
B
DATA
1IN
SEL<2:0>
output
at
incremented
to
011
by the input load
the four locations of the X buffer.

)

the data
input to

port.

MDB to select
parity) as an

J.D

v
o

buffer

latch.

BDFA

INPUT
DATA is delayed one cycle and then negates B NEW X
but latches A LOAD X for the duration of the transfer.

NEW

CLR X

1is

applied

asserts
B
X
VALID latches

the

VALID

MDB.

the

full logic (Figure 2-21) where it

VALID
1indicating that
itself until cleared by
is

After

asserted

after

the

has

data

the

been

data is in the
B CLR X VALID.

data

has

unloaded,

been

the

MRM

X buffer.

unloaded

from

asserts

BMRM

CLR BUF USE while BMRM CMD ACPT is true. A SELECT Y OUT asserts 1if
the
Y
buffer
is selected for an unload (see Section 2.7.3).
As
the
X buffer was selected for the unload; A SELECT Y OUT is false
and

FLUSH

CLR X VALID asserts. B
DATA as part of a reset

CLR X VALID

also

asserted

AMRM

function.

In addition, B NEW X checks for a masked operation by loading BDFA
CMD<0>
into a latch. If this were a masked operation, BDFA CMD<O0>
would
be
true
and B X IS MASK would be asserted and latched for
the
duration
of
the
transfer.
B
X
IS
MASK
1s
sent to the
Y-out-select
1logic
to
indicate
that
the data going into the X
buffer is masked data.

A
LOAD
X is applied to
where
it
enables the B
within

the

the X & Y bit-storage block (Figure 2-22)
IN COUNT<K1:0> bits to select the location

bit-storage

block

where

the

good-data

and

the

write—-enable
bits are to be stored. B IN COUNTK1:0> is applied to
a
decoder having four outputs. As B IN COUNTK1:0> 1is incremented,
the four decoder outputs are asserted in sequence. This causes the
four
LOAD
X<3:0>
select
signals
to be asserted in sequence to

within

locations

IND

storage

[m))

four

the

|><

select

the

X bit-storage

block.

(FIGS. 2-23, 2-25)

(F16. 2-34){
(FIG.

AVEM_FLUSH DATA

2-49)

__BVBM CLEAR BUF USE
BMAM CMD ACPT

(FIG 2-21

A SELECT Y OUT,

® 8 on Y vaup’] FULL

>(F1Q.2-25) 4B CLR X VALID |

».

By
[——

BNWY

VAL

»(FIGS.

@%J

LD .

2-21):

—p (FIG.2-25)

Rew[INPUT
v[IET 1o

l(2)l B LOAD Y IN

P COUNTER

TeALOAD v | (FIQ.

2-20IE)N

B IN
1
COUNT<1:0>
}l B DATA

_J (FIG.2-25) fi E Elgifi ffi 1 | N_SEL<2:0>

Q'K‘EE' NPT

Bew »|DETECT

¢
( FIG.2-23)¢ )(L‘A
LOAD

(3
(3)

(F1G.2-23)

=\ B#

(F18.

)6 )A DATA INPUT EN

(Fia. 2.3)—y-80F

.23y

%SEEE
(FIG.

2-9)—Y

2-14)

*-,}
> TAT

2-3,

B X YALID

(Fla

B NeW X |

(L;‘)T“‘

IS_MASK

15 MASK Iv«

XI
69-C

<«

G. FB;LST%IB‘

2-45)

SEL<2:9> .1

L P (FIG.2-17)

L
g)

B8DFA
INPUT LDATA
(FiG.2-3)

fAHEECL_Oy

7o [ A5
paTa ————» 0 NA B
,“EI

[ &oto*5ARA

(£

B DATA

——— WAITE ENARIE >

Bhor|P

GORMECT

BMDP DATA
IN"SEC<2> ),

g‘eg
R?fiémry P EMB&LEEL&LE_
ARITY<3:0-lp
O
e e Fonce (€ (FIG.2-17)
BAD DPAR

(F1G.2-49)

A SELECT

(FIG.

2-7)-)

(FIG.

2-3)

R DQ!!I;]'Q;_

RELO& Y«g:

(FIG.2-23){
e e

e e

RELOAD X<3.

(FIG.2-25)

. <

— ———— —

_— ——_ — o

e oo

NOTE:
NUMBER DESIGNATIONS I{N PARENTHESES
REFI:R TO ENGINEERING DRAWINGS
CONTAINING CORRESFONDING LOGIC.
SCLD-473

Figure

2-19

MDBC

MDB

Data-In

Selection

BDFA

INPUT

DATA

LOAD X

NEW X

0L-C

e
>0—
on
Co)—{

i___{——"
B

\
_—J

VALID

NEW Y

LAT

LOAD Y

N
=

NOTE:

THE LOGIC IN THIS FIGURE IS CONTAINED ON
SHEET 2 OF THE ENGINEERING DRAWINGS.
MKV86-1289

Figure

2-20

Input Load Command Detect Logic

X
B NEW

(7)

BMRM

CLR

BUF

USE

BMRM

CMD

ACPT

(8)

1L-C

(8)

A SELECT
Y OUT

(8)

VAUD

CLR
VALID

AMRM

FLUSH DATA

]

VALD

B NEWY

(7)

NOTE:

NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
MKV86-1290

Figure

2-21

Full

Logic

GOOD
A

GOOD

(@)

STRD

GOOD

DATA

B X

DATA

DATA
X

BIT

STORAGE

(4 X 2)

RELOAD X<3:0>
.
AL OAD

“

LOAD

{(4)

——1 SEL

¢L-C¢

COUNT <1:0>

DECODER

(4/5)

0
GOOD

GOOD

(5)

DATA

W WE

LOAD

RELOAD

GOOD

DATA

BIT

STORAGE

(4x2)
(5)

B Y STRD

DATA
Y

Y_IN

X <3:C>

(4)

STRD

(5)

STRD

—»1SEL

Y<3:0>

DOUT <1:0>
NOTE:

NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS

CONTAINING CORRESPONDING LOGIC.
MKV86-1296

Figure

2-22

and

Bit

Storage

The

good-data

bit

from

the

were

data

PARITY

ERROR1

detected
are

indicating
buffer

that

write-enable
the

write

parity

1If

ADFA

GOOD

errors

there

BAD

DATA

is derived from the parity
data bit from the FUNK. If

bad

DATA

associated

bit

inputs
error

bit

operation,

from

was

data

WE)

derived

detected

from
the

generated
bit

DBE

<0>

error

there

ARID,

sequence

error

stored

inputs

OR gate

the

write

normal

ADFA

error

bit-storage

being

bit

the

both

logic.

the

longword

write

false.

asserted

data.

The

double-bit

DATA)

the

false.

the

GOOD

and

FUNK,

good

control

1is

the

false,

ARID

block

the

with

one

and

the

mask

(non-masked)

<0> of the write mask (ADFA MASK<K0>) is a 1
longword
is
to
be
written
(sort-of-write
operation).
With ADFA MASK<0> true, MASK IN<O> is also true.
In a
masked
write
operation,
BDFA CMD<0> is a 1 (see Table 2-1) also
causing
MASK
IN<O>
to be true. The double-bit error function is
disabled
during normal writes (Section 2.7.1), hence A
X MASK DBE
will
be
false, With A X MASK DBE false and MASK IN<O>
true, X IN
WE
1s
asserted
to
the
X bit-storage block indicating that the
associated
data
longword stored in the X buffer is to be written
intp the memory arrays.
if

the

The

associated

other

PARITY

input

ERROR1.

The

asserts

not

detected

parity

for

the

wuse

because
As

the

locate
X

ADFA

PARITY

second,

The

existence

bit

when

double-bit

ERROR1

data

bits

negated,

hence

normally

bit

set
The

will

also

the

negate

fourth
B

longword

DATA

into

loads

operation

when

and

the

ADFA

PARITY

good-data
is

locations
four

bit-storage

given

ARID

ERRORI1

written

bad

data,

bit.

loaded

SEL<2:0>)

the

will

written

ADFA

ERROR]

false)

longword

the

PARITY

longword*.

longword

bit

ADFA

(ADFA MASK<O0>
the

longwords

into

write-enable

which

sort-of-write

then

the

wunder

into

the

MDB,

incremented

through

associated

the

good-data

block.

of a parity error does not force the write-enable
double-bit error is detected because by the time the
error
has
been
detected,
ADFA PARITY ERROR1 has

bit

and

COUNT<K1:0>

write-enable

analysis.

(and

write

assert

written

error

third,

COUNT<1:0>

write-enable
error

buffer.

and

during

the

will

condition

longword

forces

that

the

double-bit

error

would.

2-73

negates

the

write-enable

After
the
last data longword has been entered into the X buffer,
the Funk negates BDFA LD INPUT DATA. The negation of BDFA LD INPUT
DATA
prepares the MDBC for the next write (which will be into the
Y buffer if the X data has not been unloaded) by:
®

Loading B X VALID into a latch thereby asserting B LOAD Y
IN.
With
B LOAD Y IN asserted, the most significant bit
of B DATA IN SEL<2:0> becomes a 1 thereby selecting the Y
buffer

for

next write

operation.

Disabling the input load counter, thereby resetting it to
zero
to
address
the
first
1location
in
the Y buffer
(location

4).

Disabling
the
input-ioad-CMD
detect
1logic,
thereby
negating A LOAD X which disables the X bit-storage block.

Negating
A DATA INPUT EN so that the MDB will select the
address parity as an input to the W write port.

2.7.1.2

Normal

s £ £y am

uffer
still
in

data
the

the

FUNK and

Octaword

do the

Assert
parity

With

Data Already in the X or Y

following:

to the MDB to select the data
EN
INPUT
than
the address parity) as an input to

DATA
A
(rather

the W write

Write

TE
RISA
i
b
3
3
d
executed with
is
operation
write
another
If
-the X buffer, BDFA LD INPUT DATA will assert from

port.

Latch
B
LOAD
Y
IN. B LOAD Y IN is now true due to B X
VALID
being
true (the X buffer contains data). B LOAD Y
IN is applied to the selection output mux .

input

the

Enable

counter

load

increment

COUNT<1:0>.

selection output mux to its D1

the

Switch

outputting
significant

input thereby

LOAD
Y
1IN
(presently
true)
bit
of
B
DATA
1IN
SEIL<2:0>,

as the most
and
B
IN

COUNT<1:0> as the two least significant bits, This starts
the
B
DATA
1IN
SEL<2:0>
output
at
100 which is then
incremented
to
111
by the input load counter to select
the

four

locations

the

Y buffer.

which asserts B NEW Y
1logic
input-load-CMD
the
Enable
indicating
that new data is going into the Y buffer (B X
B NEW Y asserts A LOAD Y via a latch. BDFA
true).
VALID
LD

INPUT DATA is

Y but

delayed one cycle

and

then negates B NEW

latches A LOAD Y for the duraticon of the transfer.

B
NEW
Y
1is applied to the full logic where it asserts B Y VALI
indicating
that data is in the Y buffer. B Y VALID latches itsel
until
cleared
by B CLR Y VALID. B CLR Y VALID is asserted by the

2-74

assertion
CLR

BUF

1is

CLR

unloaded.

part

BMRM

USE

CLR

BUF USE while BMRM CMD ACPT is true.
after the data in the Y buffer has

Y
VALID
function.

reset

BMRM
been

asserted

also

asserted

AMRM

FLUSH

DATA

With
both B X VALID and B Y VALID asserted, A BUFFER FULL asserts
in turn asserting AMDP BUSY REQ to the FUNK. The busy request sent
to
the FUNK will cause memory-busy on the NMI indicating that the
data
A

buffer

LOAD

enables

1is

the

full

storage

locations

The

good-data

from
the X

The

write-enable

the

COUNTK1:0>

are

asserted

the

the
B

the
FUNK

The

write

data

DBE

logic,

other

for

data

data
°

the

longwords
also

into

loads

the

longword

has

DATA

INPUT

output

was

1in

command

was

the
B

(read

the

data

write)

buffer

received,

buffer,

LOAD

the

but

with

false

buffer

selected

NEW

is
X

and

LOAD

bit-storage

block.

After

1is

anymore

the

for
X

buffer

commands

the

VALID

the

for

the

which

block.

into

the

MDB,

incremented

through

into

the

good-data

LOAD

buffer

the

buffer,
Y

first)

the

before

memory.

buffer)

when

the

executed

load

differences:
false

SEIL<2>

(no

data

and

the

enables

the

data.

asserted.

loaded

one

and

ERROR1

associated

sequence

new

that

PARITY

processed

DATA

with

mask

described

error

described

block.

following

are

buffer
can

the

OR gate

negates

parity

write

loaded

four

loaded

four

(instead

Consequently,

buffer

similar

buffer).

ADFA

which

can

locations

been

the

bit-storage

BDFA

LOAD

select

FUNK

SEL<2:0>)

the

four

from

bit-storage

into

data

Dbe

bits

the

longword

DATA

last

commands

into

input

fourth

then

from

generated

negates

must

from

the

Data

write

it
the

block.

derived

bit

where

within

the write-enable

sequence

from

logic.

and

block

location

incremented,

<0>

COUNT<1:0>
bits

the

bit

and

(and

data.

bit-storage

from

described

third,

select

data

IN WE)

bit

bit-storage

DATA)

input-load-CMD detect

any

GOOD

any

good-data

derived

block.

write-enable

After

bit

error

second,

buffer.

and

COUNT<1:0>

locate

within

bit

functions
the

where

1inputs

bit-storage

X
to

the ARID and the bad
bit-storage block.

double-bit

the
bits

signals

bit
for

block

select

COUNT<K1:0>

stored.

Y<3:0>

also

cannot

applied
IN

bit-storage

are

and

must

processed.

2-75

LOAD

AMDP

BUSY

unloaded

REQ

asserts,

first

before

2.7.1.3
A.

Masked Write

With

Errors

operation,

write

General

Y)
in

buffer
via the B
Sections
2.7.1.1

masked

arrays

1is

write

checked

detected,

the

overwrites

DATA
and
for

errors

applied

data

specific

The

receive

the

feedback

2-23

1is

Figure

MDBC

bytes

MRM.

function.
)

selects

The

Feedback
FB

the

DBE

Logic

the

DCHK

MASK

DBE

and
®

(or

into

the

(or

If
Y)

errors

buffer

are

where

the

byte

mask

within

the

data

buffer

it
the

that

the

MDBC

feedback

Figure

2-23

are

provides
the

feedback

two-bit select output
significant bits

input

selection

each

double-bit

error

write

DBE)

below.
(B
of

least

incremented

masked
MASK

two

selection

defined

bus

(or

and

When

cycle.

(AMDP

operation,
the

signal.

DBE)

from

asserts

A X

reload

decoder

block.

reloads

negated

write-enable

bit

into

the

for

the

bit-storage
was detected

for any longword in which a double-bit error
during the feedback-read portion of a masked

write

the

Reload

buffer.

write—-enable
B.

senses
a

bit-storage

Reload

counter
~--

placed

DCHK.

the

diagram of

wused

during

the

determined

shown

SEL<K2:0>

the

1in

location(s)

Counter
FB

data.

areas

SEL<K1:0>)

enabled,
®

the

block

major

data

IN SEL<2:0> select signals as described
2.7.1.2.
Feedback
data read from the

same

bit

the

during

reload

masked

write

block

but

the

buffer.

Detailed

The

signal

SEL<2:0>.

that

selects

The

the

location(s)

MASK

from

the

Y-select

logic.

MASK

when

the

feedback

data

the

most-significant

description

bit (B
Y-select

The

for

the

Y-select

the

feedback

data

FB SEL<2>)
is
logic asserts

buffer.

logic

This

B
B

contained

Y
Y

FIRST
FIRST

discussed

Section

2.7.3.

The

two

1least

the

feedback

counter.

CTR

from

MRM

the

significant

counter

and

the

inverse

new

longword

(negated)

being

supplied

Table

2-6.)

CLK

MDP
READ

the

MDB

is
the

counter

SEL

cleared

which

derived

BMRM

supplied

counter

CLK.

2-76

NEW

obtained

BMRM

from

RESET

MASK

initiated.

from

BMRM

asserts

The

NEW

for

each

AMRM READ CMD<1>
to the MDB.
(Read

is 0
data

masked
is

are
by

operation

transferred.

part

SEL<1:0>)

write

CMD<1>.

being
read data

enabled,

masked

data

to
F

AMRM

the

When

and

when

The

when

enabled

bits

write

incremented

operation;
from

see
11

{FIG. 2-52)

BVIRM RESET MASK CTR

(FIG. 2-51)

BVIRM FAKE CMD ACPT

217

BIADP STRB FB DATA

(FIG.

2-17)

FIG. 2.45)

/¢

F A CLK
i

AMRM READ CMD <0>

A MDP SEL

'\ AMDP PBE

(FIG. 2-19)
.

LL-T

—=

A DLY
LAT | mpp SEL
2

—DATA

A LOAD

{FIG. 2-45)

}(HG. 217
-

DBE LOGIC

12)

RELOAD

1 RELOAD
X

A 'Y, MASK DRE
LD

A LOAD X

BMDP FB

DATA SEL <2>

COUNT <1:0>

FLUSH

—

B SAVE

LAT

cLa

B FB SEL<2>

ony

ANMRM

(FIG. 2-19)

COUNTER
T

B FB SEL <1:0>

FEEDBACK

F A CLK

BVIRM NEW LW

B Y FIRST MASK

{11}

(( AMRM READ CMD

(FIG. 2-52).{

(FIG. 2-25)

(FIG. 2.25)

DECODER

{13)

A X MASK DBE

.
)
(FIG. 2-19)

Y <3:0>

—

____atospx

B Y FIRST MASK

FIG. 2-24 2-24)
(FIG.

TM|

ReLoAD

RELOAD

X <a:<3:0>

]

DECODER
2

(FIG. 2-28){

—
e

)

[}

Lon]

DMDP HOLD WRAP DATA

AMDPIDATA SBE

n2)

SET

MASK

\_MASK ERROR

“:l__/

ERROR

(11/12) CLR f——
Lock-up

B MASK ERROR

161}

(FIG

__FZ)\

112)

e
e
e

EN MASK CORRECT

(FIG. 2-10

n2)

‘OQ

F165. 2.2, 2.45)

{FIG. 2-25)
ADFA NMI DEAD

)

(F1G. 2-19)

}(FIG. 2.19)

(13)

]

(FIG.

2.3

(FIG. 2-17)

BMDP OUTPUT WRAP DATA

{FIG.

C TAS

AMDBC TASK CMPT

BMDP

2-2)

e Lar PASKEMPT k16, 252
.

l
MK

Figure

2-23

MDBC

MDB

Feedback

Selection

In addition, BMRM NEW LW asserts BMDP STRB FB DATA to the feedback
feedback data to the DAD (Figure 2-17). BMRM FAKE
strobe
to
mux

1is

ACPT

CMD

BMDP STRB FB DATA for maintenance

assert

used

testing.

2.7.1.4
A.

Masked Write With a Correctable Error --

General

Feedback data from the NAB is checked for errors in the DCHK. If a
single-bit
error is detected, the location select signal 1is saved
while the data is routed through the DAD for error correction. The
to the data buffer through the W
input
then
1is
data
corrected
where its location in the buffer is determined by the
port
write
location select

signal

Refer to Figure

2-23 for the following discussion.

that was

saved.

Detailed

A MDP SEL is held asserted while the feedback data from the NAB is
SEL asserts A DLY MDP SEL one cycle later (after
back. A MDP
read
DCHK has checked the feedback data). A DLY MDP SEL checks for
the
a single-bit error (AMDP DATA SBE). If there is
of
presence
the
1is asserted (via an OR gate) to indicate
CMPT
TASK
AMDBC
none,

write of the longword has been completed. AMDBC

masked

the

that

TASK CMPT becomes

BMDP TASK CMPT for the

is detected, AMDP DATA SBE asserts which

error

single-bit

MRM.

the assertion of AMDBC TASK CMPT. In addition, AMDP DATA
inhibits
asserts SET MASK ERROR which in turn asserts AMDP BUSY REQ to
SBE
Figure 2-19). AMDP BUSY REQ causes memory-busy to
(see
FUNK
the
the NMI to stop traffic to the MCL so that the DAD can
on
assert
return

the

corrected data

the MDB.

O 1

SET MASK ERROR is also applied to a mask-error lock-up block which
utputs B MASK ERROR.

)

Holds

AMDBC

B MASK ERROR performs the following:

TASK

CMPT

negated until the mask write is

completed.

)

Holds

AMDP BUSY REQ asserted until the corrected data is

returned

from

DAD.

the location select signal from the feedback
up
Latches
SAVE COUNT<1:0>. B SAVE COUNT<1:0> is the
B
as
counter
location
in
the
MDB
where the corrected data is to be
written when

the

returned

from the

DAD.

Asserts BMDP HOLD WRAP DATA to the DAD where it holds the
corrected
indicated

has stopped as
traffic
NMI
the
until
data
ADFA NMI DEAD from the
of
assertion
the
by

FUNK.

2-78

When

ADFA

masked

NMI

write

DEAD

Switches

the

select

Asserts

mask
®

AMDBC

Clears

HOLD

wrap

around

latched

two

least

(see

parity
WRAP

data

TASK

The

WRAP

the

Figure

BMDP
allows

DAD

signal

bits

and

the

data

DATA

DAD

the

With

negated

MDB

input.

enable

indicating

logic

thereby

HOLD WRAP

DATA.

the

corrected
to

the

that

the

DATA

the
the

negating

negates

The

data

the

selected

select

most-significant

Uncorrectable

NMI

negation

feedback

SEL<2:0>

proper

the

MDB.

COUNT<1:0>)

block

error.

write-enable

the

The

double-bit

negated

bit

output

and

longword

the

Refer

the

Figure

for

error
a

the

will

2-23

occurs

location

Error

signal

bit.

This

the

data

1is

containing

already

detected,

been

write-enable

the

into

following

the
the

associated

written

the

masked

bit

memory

the

erroneous

the

write

into

uncorrectable

stored

hence

When

reloaded

operation.

not

for

has

been

during

bit

longword

bit

has

reload

NAB,

error

write-enable

bit-storage

time

the

longword

will

false

arrays.

discussion.

Detailed

When

the

DCHK

asserts

enables
error.

the

MASK

DBE

DBE)

LOAD

DBE

logic

loaded.

which

block.
Y)

logic

DBE

being

bit-storage
A

detects

AMDP

The

buffer

(or

the

MRM

ERROR

SAVE

1into

uncorrectable

operation,

DATA

General

When

the

MDB.

MASK

return

the

selected

corrected

DATA

location

Masked Write

the

buffer.

2.7.1.5

resume

2-19)

for

lock-up

negation

and

the

FIRST MASK

select

bits

DATA

MDBC.

flow

CMPT

mask-error

significant

the

asserts

completed.

request

BMDP

The

writes

the
ERROR.

busy

while

1is

ADDR mux

data

OUTPUT

CORRECT

from

INPUT

the

feedback

write

MASK

W port

signal

DATA

BMDP

corrected
®

MDB

select

Asserts

EN MASK
follows:

SELL2:0>

port
®

asserts,

seguence

uncorrectable

the
which

Note

logic

senses

looks

that

normal

the

2-79

the

MASK

asserts
Y

feedback

2-24).,

presence

FIRST

(or

DBE

writes

error

(Figure

the

Accordingly,

negates

during

DBE

WE)

of
to

A
to

DLY

the

MASK
the

logic

disabled

the

data

buffer.

SEL

double-bit

determine

data,

MDP

DBE

which

(or

appropriate

LOAD X

A DLY MDP SEL

AMDP_DBE

MASK DBE

]

A Y

B Y

FIRST MASK|

L) _Mmask pee

A LOAD Y

»>

{>O_l_

NOTE:

THE LOGIC

SHEET 13

IN THIS FIGURE IS CONTAINED ON
OF THE ENGINEERING DRAWINGS.
SCLD-477

Figure

The
location
of
COUNT<1:0>
code
counter.

decoders.
double-bit
input
and

SAVE

2-24

Double-Bit

data

2.7.2

COUNT<1:0>

1is

applied

both

and

reload

the
the

negated write-enable signal
location of the bad data in

buffer.

Unloading

defined

The
appropriate
decoder
1is
enabled
by
the
mask
error signal. The decoder decodes the B SAVE COUNT<1:0>
asserts a reload signal to the appropriate bit-storage

Data From the MDB

2.7.2.1
General
-Figure
data
out selection function.

2-25
1is a block diagram of the
The major areas shown in Figure

MDBC
2-25

below.

Data-Out
Counter
-- provides a two-bit select output (A
DOUT<1:0>)
wused as the two least significant bits of the
A DATA OUT SEL<K3:0> output selection signal. Also used to
select
the
output
signals from the X and Y bit-storage
areas.
When enabled, the counter is incremented each bus
cycle.

Y
Out Select Logic -- selects the Y buffer for an unload
of
write
data
from
the data buffer by determining the
second
most-significant bit of A DATA OUT SEL<K3:0>. Also
selects the Y buffer for a load of feedback data into the
data
buffer by determining the most-significant bit of B
FB

SEL<2:0>.

Write

Command

Logic

~--

Initiate
Initiate

an
an

unload
unload

continue

an unload

decodes
of
of

normal

that

2-8

input

masked

are

Logic

the
erroneous
longword
exists
in the B SAVE
obtained
one
<cycle
earlier
from the feedback

block.
The
reload
signal
loads
into the location corresponding to
the

Error

has

write

commands

to:

data
data

already

been

initiated

—-———————
-

(FIG. 2-34){

(FIG. 2-19)

AMRM FLUSH DATA

~(x
(;)

FACLK

F B CLK

| BMRM WRITE
>/
\

R
LOGIC

CMD <1:0>

COMMAND
19)

CLEAR

|
|

SELECT

A SELECT Y OUT

19}

A DOUT <1:0>

OUT SEL <3:0>

—>>—(FIG. 2.17)

BMRM EN

(FIG. 2-27)

BMRM FAKE

ADFA NMI DE AD

CMD ACPT
BMRM

——————q

(FIG. 2-23)

CMD ACPT

AMRM CSR

)
>

PROBE VALIDH

18-¢

A SELECT Y OUT
(FIG. 2-18)

(

B NEW Y

B8 Y VALID

B X VALID

(FIG. 2-19)4

Y
NORMAL/

B Y IS MASK

SELECT

B X IS MASK

B CLR Y VALID

8 Y FIRST MASK

Y FIRST

(9)

NORMAL

MASK

(8/9)

LAT

{9)

FIRST MASK

9
CLR

—_—
BCLR Y

L vaup.

AMRM

(FI1G. 2-23)

CLR

]

FLUSH DATA

]

E——(FIG. 2-51)

BOFA CSR1 DECODE

VALIDATE

{FIG. 2-19) —

SERIAL RD

CLR

MASK

€ (FIG. 2-48)

A DATA
9

((;())UNTER

COUNT

]

ADDR PTR <2:0>

DAT.
EN - our

z(E)LRE’a';L

(FIG. 2-23)r

AMRM ERR

INCREMENT COUNT
©

Y OUT SELECT LOGIC

A A3

B S|
MDBC

NOTE:

NUMBER DESIGNATIONS {N PARENTHESES

REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

Figure

MKVEHE- 1 200

2-25

MDBC

MDB

Data-Out

Selection

€—RIG. 2:2)

;—_————— — SRS D SIS G em—— > —

]

2.7.2.2

selects

Detailed -- A DATA OUT SEL<3:0> is the select signal that

MDB output that passes through the data-read port. A

the

DATA OUT SEL<3:0> is obtained from a mux which can choose a select
signal from the MRM (AMRM ERR ADDR PTR<2:0>) via its DIl input, or
the MDBC select signal via its DO input.

The AMRM ERR ADDR PTR<2:0> input is selected when a read of CSRI
(BMRM EN SERIAL RD and BDFA CSR1 DECODE both true)
is executing
is quiet (ADFA NMI DEAD true). The most-significant
and the NMI
bit of A DATA OUT SEL<3:0> is a 1, hence the MDB address buffer is
accessed. The three least-significant bits select the location of
the CSR1 bits

in the address buffer.

For normal operation, the mux chooses the MDBC select bits. The
most-significant bit of A DATA OUT SEL<3:0> is a 0, hence the MDB
SELECT Y OUT 1is the next
A
accessed.
is
buffer
data
whether the X or Y buffer is
s
determine
and
bit
nificant
most-sig
OUT SEL<3:0> are A DOUT<K1:0>
DATA
A
of
bits
two
last
The
selected.
The counter receives a CLEAR
counter.
out
data
the
from
obtained
the write-command logic.
from
signal
COUNT
INCREMENT
an
COUNT and
INCREMENT COUNT enables
and
zero
to
counter
the
CLEAR COUNT resets
counter

the

be incremented each bus cycle by F A CLK and F B

CLK.
-

The write-command logic receives a two-bit write command (BMRM
WRITE CMD<1:0>) from the MRM which specifies the function being
executed as shown

in Table

2-7.

Table

2-7

Write Commands

Output*

Function

=——-

No Op

1
1

¢
1

SELECT MASK
SELECT NORMAL

Select first masked longword
Select first normal longword

BMRM WRITE CMD
0>

Next longword

INCREMENT COUNT

VALIDATE

true.

The write command is decoded by the write-command logic and
asserts an output according to Table 2-7, if VALIDATE is true.
VALIDATE is true when the MRM asserts BMRM CMD ACPT while AMRM CSR
PROBE VALID 1is false, or when the MRM asserts BMRM FAKE CMD ACPT
for maintenance testing.

The

write

command

received

for

a normal (non-masked) octaword

is SELECT NORMAL followed by three INCREMENT COUNTs. SELECT

NORMAL initiates an unload of normal data from the data buffer,
SELECT NORMAL is applied to the Y-out-select logic where it checks
the state of Y FIRST NORMAL to determine if the Y buffer should be
Y FIRST NORMAL 1is true, A SELECT Y OUT asserts,
TIf
accessed.,
OUT SEL<2> a 1 to select the Y buffer for the
DATA
making A
IX

2-82

unload.

FIRST

the
wunload.
The
in Section 2.7.3.
SELECT

NORMAL

counter

enable

the

DOUT<1:0>

The

the

MASK
is

data

from

buffer

SELECT

OUT

buffer

selected

asserts

The

data-out
and

locations

the

DOUTK1:0>

the

from

Figure

bits

the
of

BMDP

BAD

DATA

become

NAB.
bits

WRITE

A SELECT Y
selected.

The
data
combined
generator

with

PARITY).

BMDP

AMCL

2.7.3.1
or

DATA

PARITY

generate

2.7.3

Out

DATA

the

making
If

are

SELECT
Y

used

OUT

DATA are
and

FIRST

the

false,

bit

the

select

the

DATA

OUT

TIf

PARITY

the

SELECT
an

applied

FIRST

FIRST MASK

SEL<K2>
MASK

data-out

that

false,

counter

follow,

This
step

enable

increments

through

the

four

AMCL

unload

within
OUT

the

used

true,

and

translated

the

DATA

BMRM

error

storage

ECL

and
to

respectively,

the

and

BMDP

TTL

for

the

good-data

PARITY<3:0>) are
in a parity
bit
(BMDP DATA

bits

ECL

BAD

DPAR

for maintenance

the

and

BMDP WRITE

ENABLE

from

FORCE

choose

STRD WE

X write-enable

translated

NAB.

good-data

X and

become

BMDP WRITE

BAD

the

Y bit-storage block (see
select the good-data and

selected

are

OUT

parity

DATA OUT

resets

respectively.

MBDC

the

commands

locations

and

for

MASK

initiates

state

accessed.,

the
X and
1is
wused to

ENABLE

Select

General
that

selected.

MASK

parity
bits
from
the
MDB
(B
BYTE
the
write-enable
and
bad-data
which
generates
a
composite
parity

DATA

used

checks

COUNT

SELECT

STRD GOOD
the

four

unload.

OUT

their

2-22).

BAD

output

AMCL

If
are

the

buffer.

bits

and

SEL<K1:0>

(see

inverse

increments

through

SELECT

OUT

blocks

ENABLE

SELECT

DATA

This

step

incremented.

SELECT

follow,

write-enable

bits.

data-out

that

buffer.

COUNT which

bits
from
DOUT<K1:0>

the

octaword write

unload.

the

and
write-enable
Figure
2-19).
A

resets
commands

selected

and

discussed

COUNT

COUNTs.

data

INCREMENT

then

for

which

incremented.

should

for

counter

selected

a masked

asserts,

for

CLEAR

three

logic

where

the

MASK

for

the

logic

buffer

SEL<K1:0>

INCREMENT

see

OUT

received

three

COUNT
to

buffer,

Y-out-select

DOUT<1:0>

DATA

selected

masked

zero.

the

Y-out-select

INCREMENT

counter

then

the

CLEAR
three

the

SELECT
to

The

command

true,

select

the

asserts

followed

unload

false,

the

data-out

write

MASK

zero.
and

locations

NORMAL

operation

TTL

from

to
the

become
MRM

1is

buffer

testing.

Logic
The

Y-out-select

unloaded

signal.
SEL<K2>

logic

When
bit

does

not

logic

selects

controlling

the

logic

the

asserts

SEL<K2>

Y OUT,

becomes

and

assert

its

SELECT

2-83

the

DATA OUT

SELECT

the
Y

buffer

OUT

output,

the

DATA

OUT

SEL<2>

bit

becomes

and the X buffer is

selected.

previously

The Y buffer

mentioned,

is used only

the X buffer is used whenever possible.

the X buffer already has data.

If
the
X
and
Y
buffers
contain
the
same
type of data, the
Y-out-select
logic
acts
as
a FIFO and the data loaded in first
will
be unloaded first. If the buffers have a mix of data (normal
data

1in

one

buffer

and

masked data

in the other),

the MRM can

unload
either buffer by commanding a mask write or a normal write
to the Y-out-select logic via the write-command logic.

Figure
2-26 is a flow diagram of the Y-out-select logic. The flow
starts
with
the condition that there is data in the X buffer and
new
data
arrives
to
be
placed
into
the
Y
buffer,
It then
determineds
what
type of data is in each buffer. After that, the
four possible

conditions

Normal
Normal
Masked
Masked

e
®
®
o

data
data
data
data

in
in
in
in

both buffers
masked data
X, normal data
both buffers)
X,

are
flowed
to empty both buffers. In the following discussion of
the
flow
diagram,
note
that all of the signals required by the
flow are input to the Y-out-select logic in Figure 2-25.

-- With data already in the X buffer (B X VALID
Detailed
2.7.3.2
into the Y buffer (B NEW Y asserts). The
placed
is
data
new
true),
logic
then
<checks
B
Y IS MASK and B X IS MASK to determine the
type

data

each

buffer,

If
the
new
Y data is masked but the X data is not, the Y buffer
select
block
asserts B Y FIRST MASK indicating that the Y buffer
will
be
selected
by
a
masked write command. If a masked write
occurs (SELECT MASK asserts), A SELECT Y OUT is asserted to select
the Y buffer and the Y bit-storage block output. When the Y buffer
is emptied, B CLR Y VALID is asserted by the full logic and resets
the
Y-out-select logic (negating B Y FIRST MASK). The X buffer is

then
unloaded
by
a
SELECT
NORMAL
command.
If a normal write
occured (instead of a masked write), SELECT NORMAL asserts and the
X buffer is unloaded. When SELECT MASK does assert, A SELECT Y OUT
asserts
and
selects
the
Y buffer for the unload.
then resets the Y-out-select logic.

B CLR Y VALID

For
the
case
where
there is masked data in both buffers, the Y
buffer
select block does not assert either of its outputs thereby
selecting
the
X
buffer for the next unload. SELECT MASK unloads
the
X
buffer
after
which B CLR X VALID is asserted by the full
logic.
The
Y buffer select block senses the assertion of B CLR X
VALID
as
an
indication
that the X buffer has been unloaded. It

also

senses

the

true

state

of B Y VALID as an indication that

(

Start

Y New
Y

Newy data into Y
bulfer. Data
airgady in Xbuffer

YES

New

Y data

~
X

data is

masked

YES

masked

data is

_YES_

masked

B Y FIRST MASK

Y buffer

selected

$8-C

write

will

Masked data in

both

by a mask

buffers.

buffer

Normal data

both

selectaed

command.

for

unload.

Masked
write
command

Unload
from X

SELECT MASK

for

SELECT NORMAL

sELECT

Unload normal data
from

+ Y FIRST NORMAL

Y buffer

selected

will

?lglr%wcatleevn o2

unload.

command.

4 SELECT NORMAL

masked data
buffer.

Unload normal data
from X buffer.

v
4

buffers.

buffer

~ Normai
wrlte‘ command

B CLR X VALID

4 B CLR X VALID

seLect

4 SELECT MASK

Unload masked data

X buffer.

4 B Y FIRST MASK

4 Y FIRST NORMAL

y
4 SELECT MASK

+ A SELECT Y OUT
Unioad masked data

Y bulter witl be
write command.

Yohudlay with be
pormal wrile

4 A SELECT Y OUT
Unioad normai data

4+ SELECT NORMAL

} B CLR Y vVALID

4 A SELECT Y OUT

Unload masked data

from Y buffer.

4 B CLR Y VALID
Y

Reset Y out select

from Y buffer.

logic-

4 B CLR Y VALID

X bulter selecled

;

'Res.el Y-out-selecl
ogic.

4 SELECT MASK
4 A SELECT Y OUT

$ SELECT NORMAL

Unload normal data

from

X buffer.

4 A SELECT Y our

'L:glr:‘)as tr)nua?:(:? data

for next unload.
Y

Unload normal data

from Y buffer.

Reset Y-out-select

logic.

from Y buffer.

4 B CLR Y VALID

Reset Y-out-seiect

v
4 SELECT NORMAL

¥ A SELECT Y OUT

Y
Unload normal data

from ¥ buftfer.

4B CLR Y VALID

Reset Y-out-select

logic.

SELECT MASK

Unload

masked

from

buffer.

‘

X buffer.

]

Res‘al Y-out-select

logic.

?(D?unffee;; 3fi{3§‘£"

+ B CLR Y VALID

logic.

from

data

Both X and Y
buffers are empty.

(

Done

)
8CLD-472

Figure

2-26

Out

Select

Flow

Diagram

there

1is

data

asserts

select

the

asserts

FIRST

the
MASK

Y
so

buffer.

select

wunloaded,

the

CLR

buffer.
that

When

The

the

SELECT

buffer

VALID

for

buffer
masked

MASK

the

asserts,

unload.

asserts

select
write

then
will

SELECT

After

reset

block

command

the

OUT

buffer

Y-out-select

logic.
For

the

case

normal
output.

buffer

will
occurs

full

NORMAL).

The

After

resets

the

For

the

case

the

buffer

and

resets

the

buffer

The

VALID

also

asserts

select

the

asserts

OUT

asserts

write

the

CLR

buffer

and

not

normal

assert

for

the

which

CLR X

buffer

select

true

data

FIRST

NORMAL

buffer.

select

the

CLR

block

that
state

the

Y
so

MASK

a
is

block

asserted

(negating

is,
that

OUT

bit-storage

the

CLR

FIRST

command.

SELECT MASK
NORMAL does

buffer

Y VALID

for

the

asserted

the

SELECT
for

the

buffer

both

its. outputs

VALID

the

VALID

unload.

buffer.

buffer

data

either

senses

that

When
Y

data

command.

SELECT

selects

unloaded,

SELECT

VALID

logic

the

indicating

logic.

there

does

indication

and

unloaded

after

the

unloaded,

normal

asserts),

Y-out-select

then

buffer

where

senses

there

block

buffer

logic.

1is

but

NORMAL

occured (instead of a normal write),
X
buffer
1is unloaded. When SELECT

Y-out-select

the

emptied,

masked

FIRST

NORMAL

the

select

selected

(SELECT

not
Y

SELECT

and

the

assert,

selecting

data

asserts

buffer

If a masked write
asserts
and
the
unload.

the

logic

new
block

select

When

buffer

the

select

write

asserted

the

where

buffer

SELECT

asserted

the

assertion
has

VALID

The

buffer
normal

NORMAL
the

asserted

been
an

and

asserts,

full

CLR X

unloaded.

block

then
will

the

that

command

SELECT

After

resets

unloads

select

the

indication

write

unload.

the

thereby

NORMAL

buffer
Y

buffers,

OUT

buffer

Y-out-select

logic.
B

FIRST

(Figure
select
feedback

asserts
®

MASK

from

2-23)
signal.

which
B FB

data.

Note

only

When

just

two
the

When

both

flow

buffer

has

data.

the

buffer

has

just

buffers,
reads

before

data

the

masked

into

there

buffer

1in

select

block

becomes

SEL<2>

diagram

that

FIRST

MASK

buffer

cases:

received

should

is the most-significant bit of the feedback
SEL<K2> selects which buffer will receive the

normal

data

this

masked

data

been

emptied.

and

case

overwrite
in

both

When

the

data

masked

data.

the

buffers

there

has

feedback

and

masked

the

data

the MRM will always unlcad the X buffer
feedback
data to overwrite the masked

buffer,

2-86

2.7.4
Internal Error,
Miscellaneous
functions
Figure
The

AMRM
cycles,

INT

ERR

feedback

CSR
WRITE

cycle

the

counter
back

long

CLK

and

the

AMRM

INT

ERROR

bit

<20>

strobe

shown

signal

for

the

Generates

Reports

and
of

means

Detects
of

means

following

correction

Detects

CLK.

After

COUNT

DLY

ERR

write

when

the

DECODE,

DLY
up

decode

for

the

MRM

asserts

then

BMDP

DECRAM

(Figure

2-2).

RAM

throughout

the

AMRM

MDBC.

functions:

from

the

for

MAR4

for

single-bit

bad-data

bit

DATA

from

MAR4,

INT

an
BAD

double-bit

reports
a data
BAD DATA bit

INT

formats

Provides

for

reading

)

Provides

for

diagnostic

cycles

CSR2

bit

errors.

the

parity error in
from the MAR4.

the

MDBC

MAR4

CSR2.

testing.

minimum.

The

be
longer
depending
on
the assertion
with respect to F A CLK and F B CLK.

time

data.

and writing

errors.

asserted

one-half

BMDP
locked

strobe

reports

and

1/2*

asserted.

the

clocks

causing

INT

and

Assembles

and

the

signals

FPFifteen

counter

single-bit

the

and
the

MCA

Checks
the data returned
double-bit errors.

for

both

remains

BDFA CSR1

MCA performs

the

BMDP

distribute

(DCHK)

and

generates

asserts

error

enables

TERMINAL

MRM.

write

CLK

DATA CHECK

outputs

logic

delayed

F A CLK

the

DAD

the

a
MRM

DCHK

the

feedback

and

asserts

2.8
The

bus

assert
so

RAM.

WRITE

generates

from

write-decode-RAM

decode

logic

ERROR

each

bus

error

1INT

incremented

The

are

2-27.

internal

MRM.

Write Decode RAM, and Clocks
executed
on
the
MDBC MCA

2-87

time
of

period

AMRM

INT

could
ERROR

F A CLK

.
(FIG. 2-34)

DELAY

N\
>

TERMINAL

COUNT

COUNTER
3
dey P

F B CLK

I
'
|

r-_-——--—-—--—-

—

(3)

AMRM INT ERROR

BMDP DLY INT ERR

(FIG. 2-25)

N\
fi/fi

(FIG. 2-17)

>\fi

(FIG. 2-2)

AN
7/

g8-C

(FIGS. 2-34, 2-50)
-

Iy =

]

BDFA CSR1 DECODE
]

AMRM CSR WRITE

G 2-2)
(FIG. 0.

N\
/{,

BMDP DECRAM WRITE

_(&

BMDPFBDATA<20>|

e2-51)
(FIG.

—

(3)

NO NEXT CLOCK
ADFA
X

STOP A

LAT
(1)

STOP B

LAT

FACLK IN

Q\,

(1)

1 (14)

F A CLK

(]

F A CLK1

F B CLK

F B CLK1

(14)

F B CLKIN

(14)

I
L

L _J

|
)

S CHEESNEEEED TN GENDENEEES GN) TEEEENEERS A O

MDBC

- '—‘

NOTE:

NUMBER DESIGNATIONS IN PARENTHESES

REFER TO ENGINEERING DRAWINGS

CONTAINING CORRESPONDING LOGIC.

Figure 2-27

MDBC -- Internal Error, Write Decode RAM, and Clocks

MKVE6. 1293

Figure

2-28

1is

illustrates

distinct

logic

prints,

etc.).

partioning.
®

four

block
diagram of the
functional
areas
that

The

check

them

check

Error

the

Check

BAD
the

MDBC,

Error

Status

PAGE

interrupt

via

the

ARID.

for

Syndrome
<check

the

DCHK

latched

ARCV

mux

the

comparing

MAR4,

asserted

was

detected

any

bits.

signal

BAD

set

the

CSR2

which

DATA

the

MARA4.

detected

Generates
a

signal

INT

was
in

errors

error

ADDR

bit

parallel-to-serial

read

and

error

asserts

conversion

the

locks
bit.
an

NMI

CSR2

operation.

Generate
bits

associated
CHECK

and

heck

does

CSR2

syndromes

data

bad-data

CSR2

ECC

through

1locks

high-error-rate

Serializer

2.8.1

from

MAR4.
the

error

The

the

that

parity

error

read

generated syndrome bits, detects
double-bit error, or an asserted

from

logic

the

returned

Generates

data

dgenerates

from

the

means

data

error-check
up

bit

MAR4
a

bits

error,

DATA

from

—-—

bits

using

single-bit

INT

Generate

generating

The block diagram
been
defined as

areas
by
the
engineering
documentation (logic
This
description
follows
the
same
functional
four functional areas are defined below,

Syndrome

DCHK.
have

then

bits

are

with

the

BITS<6:0>.

loaded

into

applied

the

read

The

the

data

check

latch

syndrome

are

applied

bits

BMRM

are

NEW

e
v
generate

passed

LW.
as

The

CHECK
el
R nlalvd

BITS<6:0>.

also

serializer
mode;

see

Data

read

where
Section
(fed

DATA<31:0>.

DATA<31:0>
In

the
L9

data

which

outputs

logic.

CB<6:0>.

MEM

becomes

part

CSR2

the

MAR4

DATA<K31:0>

applied

generate
A
T

regenerate

are

seven

from

sundrome

bits

copy

MEM

check

bits

into

another

CB<6:0>

(except

sent

latch

the

diagnostic

2.8.5).

back)

BMDP

~
J
filA
L (i

bits

check

loads

output

compared
syndrome

data

input

becomes

the

TAarsl
~

syndrome

“

oTM

seven

ECC

CHECK

BITS<6:0>

longword

check

“

AJ 4

error-free,

DCHK

IN<31:0>

BMDP

and

then

logic.
or

The

regenerated

bits.

(SYNDROME<6:0>)

the

generate

~ha~b_h

the

bits

DATA

)

they

s
e

NEW

e
o

BMRM

where

uses
uses

comparator

the

error

SYNDROME<6:0>

the
+h
A

which
check

are

all

Os.

2.8.2

The
logic

Error

syndrome
(Figure

detector.

The

Check

bits

(SYNDROME<6:0>)

2-29)
detector

where
looks

they

are

applied

the

are

input

for

the

2-89

syndrome

code

error

check

INT-bad-data

that

specifies

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FORCED DBE

:DF\HABAD <
DETECTOR

GATED

¢_FORCED gl
|

,—O<l’ ERROR

SNGL

2O S

SINGLE|

SBE

DETECTOR [®]

ERROR @

ENABLE
4—PSUEDO ECL

Figure

that

the

senses

DBE

INT

the

BAD

DBE

under

diagnostic

SYNDROME<6:0>

1looks

error

has

MCL

the

MAR4.

ECC

code,

output

FORCED

ENABLE

was
the

DBE

ECC

control

(Section

2.8.5).

applied

those

When

error

all

syndrome
the

1is

for

SBE

indicated

hence

double-bit

assert

true.

2-91

logic

error)

indicate

senses

another

During

normal

which

detector

single-bit

asserted bad-data

data

single-bit

parity

by an odd number of
code
0000111.
This

error

FORCED

data bits and check bits
condition. The SBE detector

detector

logic.

the

error

the

asserts

error-check

that

detection

syndrome

(single-bit

codes

set

When

enable-ECC

detector

the

set.

1is

the

HIGH

Diagram

(0010011),

except

when

MAR4

code

asserted

are

double-bit

the

Block

for

single-bit

this

when

(MDBC)

syndromes

obtained

INT BAD DATA bit

the

occurred+.

The MAR4

Check

syndrome

GATED

output

which

error)

ENABLE

Error

bit*

causes

error-check

operation,

DATA

INT-bad-data

(double-bit

FORCED

2-29

ECC

error

bit

error

asserted
code is

are 1s, which is
does not respond

indicated.

ERROR IS SINGLE which in turn asserts SNGL BIT

asserts

code,

ERR if ENABLE ECC is true. If the INT BAD DATA bit is set, FORCED
SNGL BIT ERR. Hence, the
inhibit the assertion of
DBE will
SNGL BIT ERR indicates a single-bit error with the
assertion of
INT BAD DATA bit

reset.

SNGL BIT ERR outputs the DCHK as AMDP DATA SBE (Figure 2-28). AMDP

sent

SBE

DATA

the

ARID

where

wused for parity

correction.

A double-bit error is detected in the error-check logic by first
ORing the seven syndrome bits. The OR gate asserts ERROR if any
error

condtion

ENABLE

ECC

condition).

The

exists

true

1is

(syndrome

assertion

bits are all 0s for a no-error

ERROR

will

assert

DBL

BIT

ERR

and:

The INT BAD DATA bit is set (FORCED DBE true), or
single-bit error (ERROR IS SINGLE
a
not
is
error
The

®
)

false).

Hence,

the

assertion

of DBL BIT ERR means a double-bit error in

the current longword or, the INT BAD DATA bit is set.

DBL BIT ERR outputs the DCHK as AMDP DBE which is sent to the ARID

and

FUNK MCAs.

interrupt

In the ARID, AMDP DBE is used to generate a memory

on the NMI. In the FUNK, it is used to signify bad data

in the read/return or read/continue function codes.

When a single-bit error exists, SYNDROME<6:4> points to the byte
containing the error. SYNDROME<6:4> outputs the error--check logic
as SYN32, SYN16, and SYN8 respectively. They are applied to a byte
which,

decoder

when

enabled, decodes the bits to assert BYTE<X>

the byte with the erroneous bit. BYTE<KX> outputs the
where X 1is
as AMDP CORRECT EN<KX> which enables the
(via a mux)
DCHK
the appropriate DAD MCA. The byte decoder
within
correction logic
ERR when a single-bit error has been
BIT
is enabled by SNGL
detected.

For the single-bit error case, SYNDROME<3:1> indicates, in binary
which data bit within the erroneous byte is incorrect.
format,
as BITK2:0>
logic
error-check
the
outputs
SYNDROME<3:1>
>
CORRECTK2:0
BIT
AMDP
as
DCHK
the
outputs
BIT<2:0>
respectively.
logic.
correction
error
DAD
the
and are applied to
2.8.3

Error

coupled

Error

Status

from

the

signals GATED FORCED DBE, SNGL BIT ERR, and DBL BIT ERR are

error-check

1logic

the error-status logic

(Figure 2-30) where they are locked up as status bits for CSR2,.

The three error signals are enabled into the error-status logic by
NEW LW

(derived from BMRM NEW LW).

2-92

I
|

]
[

| LD PAGE

———

|
|

—_—

I
|
|

CSR2 FDBE

Li
<

CSR2 SBE

AI
AN

CSR2 DBE

.
I

CSR2 HERR

NEW LW

)

[

LCK |

FDBE

LOCK-UP

£€6-¢

N
:

SBE

LOCK-UP

{

]

CLR

DBE

—

LOCK-UP

CLR {&

]

HERR

LeK

—

LOCK-UP

BDATA <292

—

LOK e

B DATA <30>

—

]

SNGL BIT ERR

DBL BIT ERR

\\___

[
\

‘

< i FORCED DBE

—

)
‘\

{
i

)

g
'

)

.
B DATA <31>

!
:

GATED FORCED DBE

B DATA <28>

—

LCK f—

]

I
l

)

CSR2 WRT

CLEAR B

B DATA <31:28>

3\
/J

L D GEG TEae IR LN AR G R G G T I GED AN GIED GER AP ED MED GER GIND AP GMP GE) TGED RE GlEP GIENS GIES GRED GNP GEED GIID D GEED AP G G GEED GMER GNP GWED GaEED AEE I S -J
MKV86-1291

Figure

2-30

Error

Status

Block

Diagram

GATED

FORCED

outputs

CSR2

SNGL.

BIT

CSR2

SBE.

DBE

1is

applied

the

FDBE lock-up block which

FDBE.

ERR

1is

applied to the SBE lock-up block which outputs

DBL.
BIT ERR is applied to the DBE lock-up
false),
which
outputs
CSR2
DBE.
CSR2
FORCED
DBE
1is false, hence the assertion
true double-bit error, not an asserted INT

block (if FORCED DBE is
DBE is asserted only if
of CSR2 DBE indicates a
BAD DATA bit.

CSR2
DBE
1is
applied
to
an
AND
gate
which looks for another
double-bit
error
input
£from
the
error-check logic. If another
double-bit
error
occurs
while
CSR2
DBE is still locked up, an
input
1is
asserted
to
the
HERR (high error rate) lock-up block
which

outputs

CSR2

HERR.

The
four
1lock-up
blocks are cleared by a write to CSR2 with the
appropriate
data
bit
(B
DATA<31:28>)
asserted.
CSR2
WRT
is
asserted
by
the
assertion
of AMRM CSR WRITE from the MRM while
ADFA CSR2

DECODE

The

CSR2

error

four

asserted
s

[=)]

the

are

ho T ol on. 3

DAD,
:

DTy
]
applied
1

the
i

serializer

CSER2
L

bits.

A LD PAGE
a singleone
bus
(CSR2 SBE

error signal is generated by the error-status logic when
or double-bit error occurs. LD PAGE 1s asserted for only
cycle. When the single- or double-bit error is locked up
or CSR2 DBE asserts), LD PAGE is negated.

LD PAGE is sent to the MRM as AMDP LD PAGE ADDR where it holds the
error
page address pointer. This reserves the location in the MDB
that
contains
the
address at which the single-bit or double-bit
error

occurred.

AMDP
LD
PAGE ADDR is also sent to the ARID where it generates an
interrupt
on
the NMI. Single-bit errors are corrected on the fly
and do not halt the current operation. They do generate interrupts
and are logged by the software so that if a location gets too many
single-bit
errors, the software can remove the page from its list
of available pages.

Double-bit errors are hard errors that halt the current operation.
Hence,
as
seen
1in
Figure
2-30,
LD
PAGE is not asserted by a
single-bit error if a double-bit error has already been detected.
In
addition, LD PAGE saves the syndrome bits from the error-check
logic
by
1loading them into a latch. The latched syndrome bits (B
STRD SYNDROME<6:0>) are applied to the serializer as CSR2 bits,

2-94

2.8.4
The

Serializer and CSR2
serializer

data.

CSR2

logic

functions

occurs.

(Figure
as

Figure

2-31)

assembles

parallel-to-serial

2-32

bit map

Four
parallel-to-serial
converters
data.
The converters are enabled by
itself
enabled
by
EN SERIAL READ.
the

assertion

DECODE
When

from the

enabled,

(BMRM

SERIAL

BMRM

DAD

true.

the

SERIAL

incrementer

RD<2:0>)

formats

the

when

CSR2

read

CSR2.

each
supply
a byte of CSR2
a binary incrementer which is
EN SERIAL READ is asserted by

READ

from

responds

received

code
1s
1incremented
1in
incrementer
(B
CNT<2:0>)

and

converter

from

the

MRM.

MRM when ADFA CSR2

three-bit

The

input

three-bit

code

input

binary format causing the output of the
to
also increment in binary format. B

CNT<2:0>
enables the parallel inputs to the converters to pass to
the
output
1in
serial
format. Eight cycles are required to step
through
The

the

CNT<2:0>

first

bits

converter

and

read

outputs

out

BYTE

byte

from each

SERIAL<K3>.

This

converter.
converter

receives
the
four
error
signals
1locked up by the error-status
logic.
Note the change in signal names going from the error-check
logic
to
the
error-status logic. As byte three of CSR2 contains
only four information bits, only two counter bits (B CNT<1:0>) are
supplied by the incrementer.

which

The

second
converter
receives
six
are output as BYTE SERIAL<K2>.

diagnostic

The
and
bits

third
converter
receives seven check bits (CSR2 RD CB<6:0>)
B
READ
CB SEL which are output as BYTE SERIAL<K1>. The check
are
obtained
from
a mux which selects a copy of the check

bits received
bits
(B
SUB
check bits is

from the MAR4 (MEN CB<6:0>), or the
CB<6:0>) used for diagnostics. The
latched by the assertion of BMRM EN

CSR2

read.

being

Mux selection is made by B
mode
(Section
2.8.5).
B
bits

(DIAGK5:0>)

substitute check
copy of the MAR4
SERIAL READ when

READ CB SEL which asserts in diagnostic
READ CB SEL is also one of the byte <K1>

CSR2.

The

fourth

STRD

SYNDROME<K6:0>)

The
AMDP

CSR2
serial
data (BYTE
CORRECT
EN<K3:0> output

SERIAL

bits

READ

converter

receives

which

are

the

output

seven
as

stored

BYTE

syndrome

bits

SERIALKO>.

SERIAL<K3:0>) is mux
when a read of CSR2

selected for
is occurring

the
(EN

true).

2.8.5
Diagnostic Mode (Figure 2-28)
Most
of
the
MCL
diagnostic bits reside in the DCHK. To run the
diagnostics,
a
write
of
CSR2
1is done wherein control bits and
substitute check bits are loaded into three DCHK latches. The data

2-95

G NS CAND GEED GEED

GEND

GED

GED GEED

CGISE

GEES

QRN CEND

GINP

GNP

MNP

GEND

GRER

GNP

THED

GES

BYTE

SERIAL

SER EN |

BYTE

SERIAL <2>

i
XI
96-¢

PARALLEL

SERIAL

SER EN

BYTE

SERIAL <1>

I
l

PARALLEL

SERIAL

CSR2 RD

CB <6:0>

DIAG BITS <5:0>

SER EN

B SUB CB «<6:0>

'
MEM CB <6:0>

B READ CB SEL

)

CONVERTER

FDBE

CONVERTER

CRD

CONVERTER

RDS

BYTE

SERIAL <0>

S ARALLEL

SERIAL

B CNT <1:0>

SER EN |

B SERIAL RD <2:0>

<
)

EN SERIAL READ
-

B STRD SYNDROME <6:0>

CONVERTER

CNT <2:0>

BINARY

INCREMENTER

.
'

»{ EN

— —— —— —— — —— —— — ——— —— — — —— — o — — — — —

MKV86-1297

Figure

2-31

Serializer Block

Diagram

30 29 28

27 26

2524 2322 21201918

L11 LI

17161514

PP TP

131211109

TP T T

[}

FDBE

DIAGNOSTIC

CHECK

BITS

SYNDROME

BITS

CRD

TTIX

CHECK
BIT

SELECT

RDS

BIT

RDS HIGH
ERR RATE

X = DON'T CARE
MKv86-1298

Figure

lines
CSR2

are
WRT

]..

used

carry

2-32

the

CSR2

diagnostic

Bit

Map

bits

into

the

latches.

are

loaded

When

asserts:

Diagnostic
latch

applied

mux
part

applied

the

Select

bit

outputs

READ

SUB

part

Diagnostic
latch

applied

the

BITS<5>

DIAG

MCL

another

mux

where

(test)

SUB

into

CB<6:0>

where

are

they

are

SUB

CB<6:0>

are

they

are

selected

for

the

CSR2.

check

bits

logic.

for

1is

SEL.

1loaded
B

byte

<1>

DIAG

latch

SEL

sent

diagnostic

CSR2.

The

DATA<23:18>

are

BITS<5:0>.

DIAG

serializer

the

into
CB

which
to

check

the

bits

select

bit

loaded

into

<1>.

bits

the

READ

selects

BITS<5:0>

into

serializer

<1>

outputs

DIAG

the

CB<6:0>.

byte

control

which

addition,

where

CBK6:0>)

DATA<1l4:8>
SUB

DATA<15>

serializer mux

included

B
B

substitute

syndrome—~generate

bits

outputs

selected
also

check

which

byte

performs

diagnostic

the
mode

mode.

BITS<5:0>

<2>

CSR2.

are

following:
enable
~

ealm
s
A

hit,

Places

Within

i1s applied to the enable-ECC logic
which looks at diagnostic bit <3>.

the

and

AND gate

DIAG

BITS<4>

mode

true)

with

disables
ECC.

the
of

diagnostic

disabled

error-check

Disabling

correction

loopback

the

read

(DIAG

1logic

error-check

data.

2-97

DCHK,

(DIAG

BITS<5>

BITS<0>

false),

negating

ENABLE

1logic

inhibits

the

DIAG
BITS<3>
in
diagnostic
mode,
selects
the
for
CB<K6:0>)
SUB
(B
bits
check
substitute
syndrome
generate
logic, instead of check bits from
the

MAR4.

DIAG BITS<2:1> -- forces the MRM to generate a parity

error

the NAB via

diagnostic

mi. _

lIie

bits

the MDBC.

The MRM

receives

the

via CSR2.

DIAG
BITS<0>
-in
diagnostic
mode,
enables
a
loopback
of data from the MDB into the MCL read-data
path
for
testing.
In
the
DCHK,
it
enables
the
error-check logic by asserting ENABLE ECC.

| nVa Vo NN

enable-ECC

TATATT
ENABLE

el e T

1logic

asserts

SERIAL

READ

m
ECC

v
~hanl
error-check

T AT~
logic

normal mode except when CSR2 is being read. When CSR2 is being
EN

read,

BMRM

cycles

required to serially

asserts

and negates the ENABLE ECC

This is done so the outputs of the error-check logic will
output,
change the CSR2 bits) during the eight
thereby
(and
change
not
In

diagnostic

dlagpostlh

the

hite

table

mode,
as

are

read CSR2.

the

shown

described

enable-ECC

1logic is controlled by the

Truth

2-8_.

—

Table

-l
s

The

four

states

shown

below.

Normal mode -- ENABLE ECC is a function of BMRM EN SERIAL
READ.

Diagnostic mode with loopback enabled -- ECC is enabled.

Diagnostic
negated

mode

with

loopback disabled -- DIAG BITS<4>

mode

with

loopback disabled -- DIAG BITS<4>

ENABLE

ECC

1is a function of BMRM EN SERIAL

READ.

Diagnostic

asserted -- disables

ECC.

2.8.6
Reset and Clocks (Figure 2-28)
CLEAR
A
and
CLEAR B are asserted in the DCHK by AMRM RESET from
the
ontaining
latches
three
the
<clears
CLEAR A
MRM.
the
diagnostic
control
bits, the diagnostic check bits, and the CSR2
check-bit

select

signal.

CLEAR B clears the four CSR2 error bits in the error-status logic.
It also negates PSUEDO ECL HIGH in the error-check logic.
F A CLK IN and F B CLK IN supply A and B clocks to the DCHK logic.

2-98

Table

2-8

ENABLE

ECC

Truth

Table

State

DIAG

Number

DIAG

BITS<5>

DIAG

BITS<0>

BMRM

BITS<4>

SERIAL

(Normal

ENABLE

READ

ECC

Mode)

1
(Diagnostic

(Enable

Mode)

Loopback)

(Diagnostic

(Disable

Mode)

Loopback)

(Diagnostic

(Disable

Mode)
X

don't

2.9
The

care

MRM

Loopback)

OVERVIEW

comprised

MSC

memory

buffers

for

(Figure

the

sequence

command

1internal

memory

2-33)

following:
control

information

errors,

—arrays,

and

generates
generates

MDP.

MSCl

memory

extension

associated

the

load

MDB.

with

MSC

two

enabling

command

sequence
the

masked

commands

generates

address

into

MDB.

MASC

memory

array

status

the

receive

the

current

read

control

RCS

transfer

arrays

have

specify

the

read
Dbeen

type

select

control

—-

and

command.
sequencer
data
read.

read

data

from

2-99

the
the

this
the

the

MCA

that

array

generates

being

that

selects

the

place

the

out

that
the

checks

after

commands

transferred.

the

board

controls

boards

read

fields

generates

ports

address

MCA

mask

and

write
bits

the

boards

for
for

select

and

checks

field

commands,

the

also

commands

stores

two

receives

command

the

and

that

DFA.

write

for

status

array

the
the

write

MCA

the

control
MCA.

also

from

the
the
that

TS GEEEN SR H
r cMED CINED GEENS SHEES CEND T CGEERS NS SRS SR OIS TR

(¢

( —_— N

—AMRM INT ERR

\LDFA

PRMIBNUM

(I!DFA CMD <2:0>

(f/\DFA DATA ADDR <3:2>

QBDFA SIZE <1:0>

E:QAMRMIBUSY REQ
BMAS CMD ACPT

)'f

]

001-¢

b, AMSC PROBEIBNUM <2:0>

__(¢-AMSC CSR PROBE VALID

J, 8MRM CLEAR BUF USE
<

]

WRITE
DONE
LOGIC

ECL

AMRMISTADDR <1:0>

A\f

BMAR CMD

ADDR PAR ERR

f————

NAB

AMSC MASK

suFFer; | AWRITE

DECODER | A OCTA

L
10

AMSC READ

<2:0> l

3 ADFA ALT{BNUM <2:0>

~
ADDR PAR ERR__
AMR CMD

LOGIC

;l DFA

F1G. 2.1)

INTERNAL
ERAOR

ADEA DEC RAM PARITY

TTL

—-‘

AMCL

CMD <3:0>

NAB

PARITY

GEN

WRITE

COMMAND
LOGIC

B WRITE ST <1:0>

J/ BMRM WRITEICMD <1:0>

(FIG. 2-16))

A AN

, BMSC:CMD PAR

MSC

L)
Figure

2-33

MRM Block

Diagram (Sheet

1 of

MKVB6-1799

)¢

—

Fe 1

\l BMDP FB DATA SEL <2>

VL4

AMRM INPUT

U BMRM NEW LW

l
|

WRT EN <3:0>

(

AMRM FB

STORE

BDFA NMI DEAD
{{
2,

10T-C

(FIG. 2-1)

BMDP DATA (N SEL <2>

z\/ ADFA MASK <3:0>
7.
\/BDFA LD INPUT DATA

MASK

WRT EN <3:0>

{{ BRCS READ CMD <1>

AMRM

[_____l
I z |

BDFA

READ CMD <1>

NEW CMD

T
'

>L
(

EARLY

L
—>

IN SEL <2:0>

;

LOGIC

ADDRESS
ouT

BUFFER —*1 crlecT

CMD ACPT

AMRM ADDR

OUT SEL <2:0>

LOGIC

{FIG. 2-1)

BMRM ADDR

ADDRESS
SELECT

BMASS

{FIG. 2-16)

(

(FIG. 2-16)

MSC1

UG
Figure

2-33

MRM

Block

Diagram

(Sheet

MKV86. t 3

v
F_—l__—____—_—-——_'

L BMSC CMD PAR
I

[ BMRM

CMD

ACPT

PARITY

GEN

BMDP STRD APAR <3:0>

J
’,

AMRM STADDR <1:0>

igg"E'\:?ND

AMAR SEND NO CMD <7:0>

{"‘J
>

PROBE 3NUM <2:0>

BMAS BNUM <2:0>

I
|

BMAS BD VALID

ARCS

BD SEL <2:0>

BMAS BO SEL <2:0>

Cmare (S Gm———

= v G

Gamn

G Sma—— S— — cwe)

NO.CMD <7:0>

TTL

NAB

ECL

L
1

]

NAB

AMCL BRD
SEL <7:0>

emm— ensmm o

NAB

READY DONE <7:03>

1 ECL.TO TTL
DECODER

NAB

BMAR SEND

ECL

MASC

PAR

LAT

CMD AVVR

BMAR DATA

)
AMSC

ECL
TTL
TO

AMAR DATA READY DONE <7:0>

LOGIC

AMCL

\'\
(

BMAS
CMD ACPT

¢c01-¢

(FIG. 2-16)

5y,

BMRM CMD ADDR PARITY

tagt

ECL TO TTL

BRCS BD | DECODER

AMCL READ

SEL EN

BD SEL <7:0>

NAB

a
MKVEG-

Figure

2-33

MRM

Block

Diagram

(Sheet

30T

jad

r———_.

- i

ARCS BD SEL <2:0>

€0T-¢C

DRIVE

A MAR

NEW

DONE

DATA
LOGIC

l
I
/7 BMRMINEW Lw

NN
.,

AMARM

READ CMD <0>

READ
o

QUEUE

BNUM <2:0>

AMSC MASK

—&

BMSC LEN

MAR

AMRM DRIVE

BNUM <2:0>

/.&

NEW DATA

AMAR DATA

‘__J

BRCS BD SEL EN

lgmct pRive NEW DATA

—NAB

—27

AMRM M MPR MPR DATA DAT

BMRM EN SERIAL RD

csh
LoGic

ENABLE
P

AMSC READ

READ

ECL
10

ADY DONE <7:0> \\
BOARD

B NEW LW CNT <2:0>

AMRM CSR PROBE VALID

B8MAS

m==-

A MAR OCTA

{FIG.2-16)

———_—1

BUFFER

BRCS READ CMD <1>

(FIG. 2-1){

i& |

_————-

SEL

—K
N

(RIG.
FG. 2-1)
218)

RCS

MKVBG-

Figure

2-33

MRM

Block

Diagram

(Sheet

140

2.9.1

NAB Board Select

In the NAB command/address cycle, the MRM places onto the NAB the:
board

select

1line

the selected (X) array

Asserted

°®

Command field

°®

Command/address parity bit (AMCL CMD ADDR PAR).

(AMCL BRD SEL<KX>).

(AMCL CMD<3:0>).

Commands and board-select numbers are received from the DFA and
Commands and
applied to a buffer/decoder in the MSC.
are
held in the
be
can
commands
three
to
up
for
board-select numbers
commands.
the
accept
to
ready
are
boards
buffer until the array
it
command
first
the
from
data
command
The buffer/decoder outputs
command
next
the
from
data
command
output
not
receives but will
until it receives BMAS CMD ACPT from the MASC. The assertion of
indicates that the command data £from the
ACPT
CMD
BMAS
buffer/decoder has been accepted by the array board and the
buffer/decoder can output the data from the next command. When the
buffer/decoder has command data for two commands, it asserts AMRM

BUSY

REQ

the

DFA to place memory-busy on the NMI. The third

location in the buffer/decoder is filled only when a read command
is received in the next bus cycle after the assertion of AMRM BUSY

REQ.

passes
(ADFA PRM BNUM<2:0>)
The primary board-select number
PROBE
AMSC
as
MSC
the
outputs
and
buffer/decoder
the
through
read
octaword
second
the
senses
coder
BNUM<2:0>. When the buffer/de
ect
board-sel
alternate
the
uses
it
,
of a hexword read operation
output.
BNUM<2:0>
PROBE
AMSC
the
number (ADFA ALT BNUM<2:0>) for

AMSC PROBE BNUM<2:0> is applied to the MASC where it is latched to
become BMAS BNUM<2:0>. AMSC PROBE BNUM<2:0> is also applied to
checks the send-no-command and
which
logic
command-accept
data-ready-done status of the selected board. If the selected
board can accept the command, the command-accept logic asserts
BMAS CMD ACPT to inform the MCL of this fact. BMAS CMD ACPT
becomes BMAS BD VALID which outputs the MASC and enables an
decoder decodes the board select number
Th
ECL-to-TTL decoder.
from the MASC (BMAS BNUM<2:0>) to assert one of eight AMCL BRD SEL
lines.

The

asserted AMCL BRD SEL line enables the selected array

board to perform the commanded operation.

BMAS BNUM<2:0> is also applied to the RCS where the board number
is stored in a buffer queue during read operations.

2-104

2.9.2

NAB

The

Command

Field

NAB

command

four-bit

specifies

and

Parity

field

(AMCL

CMD<3:0>;

Figure

1-9)

the:

Command

)

Transfer

function

(longword

{(read

Starting

address

write)

read/write

(which

the

octaword

four

read)

array

banks

accessed).

The

MRM

writes,

functions

recognized

From

1input

the

outputs

array

BMSC
DATA

parity

MASC

generator
field

the

bits

command

from

the

The

NAB

MSC

write

AMSC

the

READ

BUF

buffer

that

2.9.3

MDB

Address-in
the

select

types

the

(masked

command

types

the

buffer

specifies

decoder

the

command

of the transfer.
specify starting

Address
address

write

and

the

address

parity

generate

PARITY).
TTL

and

MDB

CLEAR

that

the

MSCl

and

senses

false),
When

BMAS

BMRM

The

placed

the

BUF

can

USE

place

monitors

array

CMD ACPT

OCTA

the

board

asserts

the

new

data

longword
has

causing

MDP.

BMRM

into

the

Selection
in

the

port

DFA

FUNK

asserts

1logic

generates

address

area

are

sent

the

MDB.

When

BDFA

increment

NEW

the

select
of

the

bits
MDB.

MDP where

new

CMD

select

the

bits

they

command

EARLY

to
The

the

buffer

MDB.

select

address

logic

are

port

bits.
MASC

WRITE

MASC.

command,

assert

W write

select

the

NAB

logic

A OCTA

the

address-in

the

true

SEL<2:0>)

read

the

unloaded.

(BMRM

SEL<2:0>)

outputs

ADDR

address-out

for
PAR.

ADDR
ECL

write-done

within

the

bit
CMD

the

from

the

address

with

CMD

also

the

BMSC

APARK3:0>)

converted

from

just

select

When

parity
as

PAR,

command

the

select

ADDR

(A WRITE

location

buffer

combined

bit

CMD

signal

address-in

address

logic

MASC

(BMRM

Address

bits

output

bit

select

applied

received,

the

STRD

informs

was

generates
to

bit

logic

USE

MSC

sent

(BMDP

longword

write-done

locate

the
1is

parity

ACPT

CLEAR

from

information,

LEN.

MDP

logic.

CMD

accepted

size

parity

AMCL

operation,

BMAS

OUT

and

buffer/decoder

write-done

The

command

into

BMSC

parity

the

which

command/address

are

and

LEN
specifies
the size
ADDR<3:2>
from the DFA

command/address

the

other

reads)

boards.

command

READ

the

hexword

STADDRK1:0>.

command

convert

writes,

the

AMSC

function.
bits
ADFA
AMRM

octaword

The

bits

are

where

dJgenerated.

sent

the

MDB.

first

(indicating

the

output

where

buffer

the

The

select

hold

bits
has

locate
bits

are

assertion

array

2-105

that

they

can

select

through

bits

The

logic.

that

applied

select

MDP

The

set

address-out

also

the

(AMRM

applied

three

output
of

BMAS

accepted

the

from

to
MDB

ADDR

the
sets

the

CMD ACPT

current

command

select

address)

2.9.4

Internal

the

field

selected

received

MDP,

atter

asserts

the
ADDR

applied

PAR

generates

which
output

logic

board

from

the

detects

MRM

BMAR CMD ADDR

enters

output

MSC

the

compared

the

1If

AMAR

asserts

CMD

AMRM

ADDR

INT

memory-interrupt

ERR

the

3-1

CMD

1is
is

the

set

PAR

the

cycle

3-3).

BMAR

ERR

where

board

select

RAM

in
the

resulting
the

the

bus

decode

asserted,

onto

command

from

internal-error

detected

DFA

placed

NAB

through

ADDR

The

from

received

second

alternate

bit

error

PAR

being

AMAR

and

parity

(Figures

error

address

1logic.

primary

parity

the

ERR

cycle

the

PAR

internal-error

parity

1is

buffer

Error

array

ERR

PARITY).

and

the

command/address

CMD

RAM

causes

bits,

logic

numbers

(ADFA

DEC

decode

RAM

internal-error

memory-busy

NMI.

2.9.5

MDB Write-Data Load
write-data cycles, the MSCl generates the load-enable
signals
that
byte-load the write data from the NMI (via the DAD)
into
the
MDB.
The
4-bit
1load-enable
signal
(AMRM
INPUT WRT
EN<3:0>)
1s
sent
to
the MDB where it is applied to the W write
During

the

port.

The

which

asserts

1load-enable

all

cases

except

during

read

data

required

2.9.6

Octaword

For

bit

signal,

the

WRITE

NAB
and

write-done
operation
has

been

unload

effect
OCTA

write

WRITE

incremented

BUF

USE

four

the

Section

from mask-store

entire

when

longword)

error

logic

all

correction

2.9.8).

the

and

longword
the

the

data

are

When

write

field,

from

bits

arrays.

the

from

ST<1:0>)
by

when

the

this

occurs,

MDP

allow

The

WRITE

the

write-done

CMD ACPT.
longword

the

also

has

the

been
logic
MDB

supplies

logic.

Thus,

write-done

re-use

memory

array.

inform

write-command

CMD<1:0>)

MDB.

fourth

the

board

parity
the

logic of an octaword write
them of each longword that

the

BMAS

buffer/decoder

board.

(BMRM

the

command/address

writes

MSC

array

bits

MRM maintains

the

and the write-command
BMAS CMD ACPT informs

accepted

determine

obtained

load

operation,

command

bits
can

(see

write-command

the

(to

masked

write

the

logic
while

generates

bits

Writes

octaword

select
A

the

signal

four

The

the

logic
MDP

write-state

write-done

transferred
asserts

buffer

write-state

logic
to

BMRM

that

was

the

CLEAR
just

unloaded.

2.9.7
In

Read-Data
read

Cycle(s)

operations
atior

writes),
the
board
along with AMSC MASK
three-stage

buffer

(including

reads
associated
with
masked
select number {(BMAS BNUM<2:0>) from the MASC
and BMSC LEN from the MSC, are entered into a
la]
1

queue.

2-106

AMSC

MASK

(BRCS

READ

normal.

BRCS

the

The

outputs

CMD<1>)

DFA

Dboard

SEL<2:0>

for

PROBE

any

ECL-to-TTL
of

SEL

RCS.

buffer

the

directed
ARCS

BMAS

When

AMCL

read

which

logic

READ

data

commanded
DATA

RDY

BRCS

the

array

READ

The

read-board

DONE
to

board

SEL

lines

read

the

NEW

logic

DATA

the

DRIVE

longword

the
If

also

then

MAR

OCTA

retrieve

The

three

SEL

Masked
as

the

read

basically

The

INPUT

data

the

1in

from

senses

the
MDB

the

more
of

NEW

counter

the

entire

the

NAB

which

from

the

array

which

bit

the

<0>

the

outputs
MCIL

that

specifies

operation.

octaword

transfer

pulses

read

the

data

from

this

pulses

and

via

logic

longword
causing

array

octaword

specifies

read-command

outputs

read-board-enable

for

the

drive-new-data

sensing

longwords

read

AMRM

informs

command

DONE

AMCL

DATA.

counter

transferred

this

BMRM

"next"

the

Read

three

also

read

enables

NEW

longword

NEW

then

MAR

DATA

When

asserts

asserting

DRIVE

the

array

logic

which

AMRM

the

BNUM<2:0>.,

enable

data

NEW

longwords

MRM

concerned,

array

field

and

MDP.
the

bit

the

<0>.

count
to

hold

transfer.

masked

can
Y

operation

The

mask

the

SEL<2>

being

(via

the

operation

write

stored

to
MSC1l

associated

MDB).

The

mask

the

same

BDFA

with

the

data

field

the

BMDP DATA IN SEL<2>
specifies in which section

stored).)
BRCS

2-107

write

(corresponding

according

masked

fields

stored

buffers

DATA

data

followed

MASK<3:0>)

MDP.,

section

(BMDP

write

board

(ADFA

the

commands

the

from

two

stored

bit

three

mask

stored

MAR

from

BRCS

Writes

DATA

for

asserts

asserted

2.9.8

asserts

longword
senses

three

transfer,

Insofar

board.

line

decoder

asserts

coming.

logic

CNT<2:0>)

read-counter,
asserts

the

"first"

other

longwords

During
BRCS

the

true)

the

transfer,

NEW

drive-new-data

board.

enable 'logic

DONE

asserts

read

BMRM

also

board

into

inputs
CMD<0>.

1is

applied

decoder

CMD

(AMSC

array

data

also

BMAS

read

SELK2:0>

then

number

enabled

DRIVE

READ

longword
the

ARCS

read

DATA

board

the

first

AMRM

data

sent

enable

BMCL

NEW

read

<1>

decoder

RDY

the

RCS

being

read-board

and

then

inhibits

read-board

ECL-to-TTL

board.

NEW

and

the

ECL-to-TTL

specified

logic

becomes

<clock

bit

masked

ARCS

DATA

the

transfer

which

board

which

The

the

MASC

where

array

the

MCL.

AMAR

select

data

functions

BMRM

logic
the

the

SEL<2:0>).

the

enable

for

command

MSC1l

outputs

SEL<2:0>

asserts,

the

SEL<X>.

drive-new

AMAR

queue

MASC.

the

generated

monitors

board

read

operation

through

enabled

read

CMD<1>.

command-accept

decoder.

SEL

READ

AMAR

DRIVE

the

passed

become

its

The

from

command

eight

transfer

AMRM

the

buffer-queue

applied

BNUM<2:0>

latched
one

RCS

specifies

CMD<1>

MDB

number
and

applied

ACPT

READ

and

the

which

READ

When
CMD<1>

the

mask-store

bit)

and

that

read data has been obtained from the array board
longword of
a
(BMRM NEW LW asserts), it outputs the mask field as AMRM FB WRT
EN<3:0> to byte load the read data into the MDB. The mask field is
output from the X or Y section of mask store according to the BMDP
FB DATA SEL<2> bit from the MDP. BMDP FB DATA SEL<K2> specifies
which section of the MDB (X buffer or Y buffer) is being unloaded.
If a single-bit error is detected in the read data, the mask-store
is informed of this by the assertion of BDFA NMI DEADl from the
The mask store then outputs the mask field as AMRM INPUT WRT
DFA.

EN<3:0> to byte-load the corrected read data into the MDB via the
W write port. The corrected read data is loaded through the W
write port because after being corrected 1in the DAD, it was
wrapped

and returned to the MDB via the normal write data

around

path.

2.9.9

CSR READS

When the read command is for a CSR read, the MSC buffer/decoder
this and outputs AMSC CSR PROBE VALID. AMSC CSR PROBE
decodes
VALID is applied to read-CSR logic in the in the RCS to specify
the read operation as a CSR read. The read-CSR logic responds by
outputing

BMRM

SERIAL

READ

and

AMRM MPR DATA SEL. BMEM EN

SERIAL READ is sent to the DAD in the DFA where it switches the
CSR data onto the data output path to the NMI. AMRM MPR DATA SEL
is sent to the MDB where it switches a mux which wraps the write
from the MDB back into the DFA as CSR feedback data.
data output
The wrapped write data is applied to the CSR logic in the DAD.
MEMORY SEQUENCE CONTROL (MSC) MCA
2.10
MCA) recives and processes
the MSCl1l
(along with
MSC MCA
The

commands
the MSC

for the array modules. Figure 2-34 is a block diagram of
The block diagram divides the MSC into nine areas
MCA.

°®

Buffer Control -- if a target array board is busy, the
buffer control will queue up to three commands in the
the BNUM probe buffer.
command/address/size buffer and
The buffer control asserts a busy request on the NMI when
are queued. When the array board is free,
two commands
allows the commands to pass through
the buffer control

that perform the following functions.

the

buffers.

BNUM

Probe

board

probe

Buffer and Error Logic -- stores up to three

numbers. Checks for errors and asserts AMRM

INT ERR to the MCL if an error is detected.

Command/Address/Size
command/address/size

data

Buffer
associated

with

stores
up to three

commands.

Size

size

Logic

the

=--

g ene rates

n
commanded

size signals according to the
er

Starti‘.l

AA.d‘JLeSS

boards.

Mask

Address/Size

associated

write
®

array

with

i\,‘

—-—

generates
=

Buffer

the

read

stores

portions

Command

unloading

Logic

MDB.

generates

Indicates

Mask

Write

generates

)

Command

Logic

Done

involvement
Figure

2-34

functional

diagram

that

may

Figure

2.10.1

2-34

MSC

2.10.1.1

LATE

the

from

Buffer

(BMSC

PRE

third

write-command

masked

write

BNUM

latches
the

DONE

CMD

buffer

)

from

The

the

probe

become

BNUM

probe

the

VALID

buffer

not

read),

VALID

Negate

able

command

latch
A

the

(as

Latches

VALID

case

the

remove

the

VALID

Assert

HOLD

CS2

Refer

CMD<1>.

VALID
CMD

the
the

an
In

bypass

DONE
the

supplying
buffer

and

around

the

buffers.

the

MSC

this

write

case

the

asserts.

The

path

the

and

BNUM

buffers.

command/address/size

the

command

the

CMD<K2>

maintain

HOLD

2-109

CMD

octaword

CMD<2>

probe

true

command

reaching

false

command

the

BNUM

ACPT

the

probe

false.

the

commands

NEW CMD

BDFA NEW

from

latch

nine
block

buffer.

logic),

BNUM

will

and

the

and

FIRST

buffers

and

the

DONE

command/address/size

BDFA

command/address/size

set

will:

the

entered

remains

CMD

CMD<2>

(BMAS

CMD<1>

FIRST bypasses

command/address/size

the

MSC's

area(s).

processing

command-done
B

the

detailed

has

BNUM

completed

prevents

assertion

command

latches

has

and

2-35)

signal

board

probe
®

true

buffer.

hexword

and

MSC

connecting

has

functional

FIRST

assertion

other

A VALID CMD<2>

processing

signals

hence,

still

third

buffer

accepted

operation

completion

area

valid

the

for

write

operations.

latch,

the

array

Operation

DONE

probe

has

bits

octaword

not shown on the overall block
their
source
or
destination

(Figure

two

data

masked

2.10.

new
through

and

CMD
B

asserted

the

board

MASC)

asserts.

clocked

Section

Control

array

number,

throughout

Control

the

major

have

Buffer

the

functional

three

for

signals.,

signifies

signals

figure

and masked

signals

signifies
LATE

=--

show other

command/address/size
CMD

senses
control

normal

Each

These

referenced,

Logic

illustrates
areas.

diagram.

appropriate

state

transfers.

audress

address/size

operations,

Write

SLart_i 1

buffers.
CS2

asserted.

BMIM WROF

MASK

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BUFFER

(FiG.2-

A oM

A PH

TADDA

ADDRESS/SEE [X o prw aamc

BEC

CONTROL
(F1Q.

(F1a.2-52)

MMo1
CLEAR
e

SIADDA

A MASK

CMD«2:0»

(F1G.2-49)

(FI1G.2-48)

STARTING

:le«‘ 8>
ry

CMD DONE

msc PR
MASK DONE

F 244
(FI1G.2-44)

A_PFE

|—AlaDDAdo

—_—

1} 4= 1 L

(F1G.2-3) R TSR

Loak

(F1a.2-28)

BSC PRE

(F10.2-2)

g&um

r—-————-————.

A
MATK
A WRITE.

o P31 70

—P

B WAITE ST<1:02y,

LA B

L&m_.@ PUFTER
35,

CMDg1-02

‘l

53‘2‘ 20

(Fia.2-3)

}(_

»>

(F1Q5.2-17, 2-48)

e
NOTES:

A FIRST

8 HolD €352

AHaD et

NUMBER DESIGNATIONS IN PARENTHESES

REFER TO ENGINEERING DRAWINGS

CONTAINING CORRESPORDING 1OGIC,
SCLD-298

Figure

Block

Diagram

BMAS

oMD AcPT

CMD DCNE

BMSC

FRE

CMD DONE

hg)}~~~'~~~-

A VALID

glaEALRJPéV ol LAT

CMD<0>

LAT

(13)

Fl:

D&,A.fiELBiL.__)

VALID
MD<2>

VALID

CMD<1>

—1

>o[79)\ B HOLD_ CS2
‘_1_3}

(13)

-p{

HOLD

cS1

ITIT1-C

- [1[13\\ B _HOLD €S0

8 HOLD €S0

AR A

VALID

CMD<2>

CMD<0> E‘J
A VALID

VALID

CMD<1>

13)

)

_CSR1

OPER

)

]

K(FIG.2-37)

)
[
——DAMEM_&&Y__BEL '

<2>

(1)

(F'G-Z‘“){
(FIG.2-42)

BDFA

HOLD

A_DO

MASK

CMD

A_MASK FEND
A

WRITE

(9)

MACHINE

N(FIGS.2-42,

2-44)

IDLE

NOTE:
NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

SCLD-164

Figure

2-35

Buffer

Control

HOLD

€S2

is applied to an A-HOLD-CS1 AND gate which looks for

another command as indicated by the assertion of B VALID CMD<K1>.

BDFA NEW CMD LATE asserts,
another command 1is received,
1f
CMD<0> and B VALID CMD<1>. B
VALID
A
of
n
assertio
followed by the
gate asserting A HOLD CSl
AND
1
A-HOLD-CS
the
VALID CMD<1> enables
to the two buffers.

e
®

A HOLD CSl:

LLatches the second command in the two buffers.
Latches B VALID CMD<1> to maintain A HOLD CS1 asserted.

ANDed with either B VALID CMD<1> or A VALID
BUSY REQ. AMRM BUSY REQ causes memory-busy
AMRM
CMD<0> to assert
stop new commands to memory. Only a read
to
NMI
the
to assert on
bus cycle after the assertion of AMRM
next
the
in
command received
A

VALID

1is

CMD<2>

BUSY REQ will be accepted by the MCL.

VALID CMD<2> and B VALID CMD<1> are applied to a B-HOLD-CSO AND

gate which looks for another command as indicated by the assertion
of A VALID CMD<O>. If a read command occurs in the next bus cycle

and the array board is still not free, BDFA NEW CMD LATE and A
The assertion of A VALID CMD<0> causes B
VALID CMD<0> asserts.
HOLD CS0O to assert which:

the read command as the third command in the two

Latches
buffers.

L.atches A VALID CMD<0> to maintain B HOLD CSO asserted.

When the array board is free (BMAS CMD ACPT true) and the MSC has
(BMSC PRE CMD DONE
finished processing the current command*
negates the three
DONE
CMD
B
B CMD DONE asserts.
asserted),
the
output
commands
the
and
signals
latch
HOLD-CS
command/address/size and BNUM probe buffers in order.

2.10.1.2 AMRM BUSY REQ -- When the buffer control has latched two
it asserts AMRM BUSY REQ to the ARID
in the buffers,
commands
the NMI. As seen in Figure 2-35, the
on
sy
memory-bu
asserts
which
along with the the assertion of
CMD<2>
VALID
A
of
true state
CMD<1>, will assert the busy
VALID
B
or
CMD<0>
VALID
A
either
request,

A CSR1 operation always requires that busy be asserted (see
Section 2.2.6). The assertion of A CSR1 OPER from the command
logic will assert the busy request when the CSR command is valid
(A VALID CMD<2> if signals are queued; A VALID CMD<O> if no
signals

This

are

queued).

would

four

longword

writes

for

an octaword write

2.10.1.3 A

CMD PROC START ~-- A CMD PROC START

is generated

in the

buffer
control
and
sent
to
the
BNUM
probe
buffer
where it
initiates
the processing of a command by enabling the BNUM probe.
A
CMD
PROC START is also sent to the write-command logic and the
command-done logic to initiate command processing in those areas.
The
write
portion
of
a
masked
write
has priority over other
commands.
A CMD PROC START is inhibited when the write portion of
a
masked
write
1is pending (A MASK PEND true from the write-mask
logic)
and
a
multi-longword
write
operation is not already in
progress (A WRITE MACHINE IDLE true from the write-command logic).
When
the
write portion of the masked write is started, A DO MASK
asserts
(and A MASK PEND negates) from the write-mask logic. This
results
in
the
assertion of A CMD PROC START to start the write
portion
of the masked write. If the masked write is a quadword or
octaword write, A CMD PROC START remains asserted for the duration
of

the

transfer.

For a non-masked operation
operation),

°®

A CMD PROC

read portion of

asserts

a masked-write

when:

There
1is
a valid command in the first or third location
of
the
buffers
(A VALID CMD<K0> or A VALID CMD<K2> true)
while
BDFA
HOLD
CMD is false. (The only time BDFA HOLD
CMD
1is
true is in single-step mode when a write command
is

being

execute.d)

Or,

There
is
a
valid
command
1in
the
second
and
third
locations
of
the
command/address/size
and
BNUM probe
buffers (B VALID CMD<1> and A VALID CMDK2> true).*

2.10.2

BNUM Probe Buffer and Error Logic

2.10.2.1 Probe

probe number
PROBE VALID)
to
receive
the

(and the

START

probe

Logic

The

probe

(Figure

2-36)

logic supplies the three-bit

(AMSC PROBE BNUM<2:0>) and a probe-valid signal (AMSC
to the MASC. The probe number selects the array board
the current command. The probe-valid signal validates

number

for

the

MASC.

Three-bit
probe numbers ADFA PRM BNUM<2:0> and ADFA ALT BNUM<K2:0>
are
recieved
from
the
decode
RAM and specify a primary and an
alternate
board
number.
The
primary
board
number is used for
longword,
guadword, and octaword operations (only one array board
is
accessed).
The
alternate board number is used for the second
octaword
read
of
a
hexword
read
operation.
For
interleaved
oeration,
the
primary and alternate board numbers are different.
For

non-interleaved

In
is

operation,

they

are

the

same.

this case, BDFA HOLD CMD is not a factor as A CMD PROC START
for
the A VALID CMD<2> command whose data has already been

loaded

into

the

MDB.

2-113

iS;JAMi?) )

a)
(4)

o} BNUM<2:0> |
ADFA

>|_._~MBL,ACLDB._..\
5|

I ADFA DEC

"o
(4)
—Do—>

Do—»lLo

(4)

—01N

Do)

> (4)

_PRE

APROBE<5:3>
_PRE

ausc

’

LAT |« B0 Sevszion

—|>o——> LD

A_SECONDARY

A FIRST

HOLD CS2

LD jug—NEW_MASK

(4)] -PROBE BNUM<2.0> ~~)|
(6)

RAM PARITY

HOLD CS1

DO MASK

(FIG.2-43)
v

HOLD €S0

BOEA

CMD LA#E
BDFA DOV’

8
‘

PARITY

CHECKER

(14)

@—» EN

AMAR CMD ADDR PAR ERR

3yDLY INT_ERR

{>O

B _ECL RC POWER OK

|- AMSCI DLY7 BD VALID
I

A CSR_CMD
A _CMD

B DECR

|.PAR_ERR

PROC START

m —

)

l
sT ADEA_UNJAM

—\ PROBE VALID
(9

T
) PRRRE VAL
(9))

L AMSC

—{)C

CMD<1>

Sop—o
o

ADFA NM!| DEAD

. |
|

AMRM

INT_ERR

:
A BLOCK PROBE
KAR
(

\J___AMRM RESET

,,
LAT | B RESET

(1)

o PATA
M F) [FHUSH

N
| LAT | B INIT

(1)

[T
p| LAT

LA INIT

(1)

NOTE:
NUMBER_DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

Figure

SCLD-362

pIl-C¢

LAT

LAT |

| aoen, e

-1D1

> PROBE<2:0> | |pq
D1

BNUM Probe

Buffer and

Error

Logic

ADFA

PRM

BNUM<2:0>

three-stage

and

buffer.,

ADFA

numbers

associated

with

three

CS1,

from

the

and

probe

HOLD

numbers

from

the

probe

number

The

the

second

buffer.

the

buffer

probe

PRE

PROBE<5:3>)

from

the

size

logic.

from

the

read

select

the

primary

board

number.

alternate

The

probe

number

output

where

the

selected

read

portion
a

probe

wused

was

1logic
number

the

loaded

logic

provided

the

probe

wvalid

indicating

that

The

buffer

command

for

(AMSC

PROBE

signal

internal

indicated

the

current
A

signal,
VALID).

and
In

NMI

DEAD

CMD

CSR

this

RAM

PROBE

the

MDBC,

that

the

DAD

data

required

for

VALID

AMSC

applied

thereby

CSR

the

CSR

CMD

(not

now

MASC

valid

from

memory

the

MDBC

where

unjam

the

BLOCK

memory

CSR

PROBE

required

assert.,

for

the

probe-valid

(AMSC

clear

the

state

write

2-115

the

number

reset,

VALID

MDB

probe

start

the

from

START,

read

disabling

board

MASK

signal

PROBE

the

masked-write,

access

access,

path

from

BMAS

the

false

inhibit

CSR1

before

logic

CSR
to

the

NEW

error,

the

probe-valid
is

true

2.3.11).

write-command

assert

DEAD

CSR

will

addition,

indicates

decode

operation

CSR

write

PROC

There

arrays),

AMSC

CMD

)

during

the

asserted

supplied

This
must
be
a
memory
access
(A
command/address/size buffer false).

must

another

and

portion.

For

still

executing.

VALID)

must

selects

was

detects

SECONDARY

When

board

mux

SEL<2:0>

valid.

asserting

select

portion

PROBE,

ADFA

logic

MASK

write

FIRST

primary

controlled

oprations

conditions

the

operation.

portion

logic

applied

buffer

the

number

control

process

Otherwise,

BMAS

read

number

probe

size

MASC.

PROBE<2:0>),

asserts

HOLD
three

alternate

mux

read

PRE

the

non-masked

probe

the

When

the

probe

mux.

read,

mux

CS2,

queued,

mux

the

BNUM

the

valid:
°

the

are

into

the

latch

This

executing,

for

the

signal

the

buffer.

masked-write

from

when

board

the

HOLD

bypasses

the mux
receives

number.

causing

MASC

1into

mask-write

from

during

and

via

also

hexword

from

masked-write

mask-write

number

probe

mux

SEL<2:0>

latches

output

input

hold

logic,

commands

true

which

the

can

commands.

number
another mux

octaword

1logic

are

buffer

control

SECONDARY

portion

BNUM<2:0>

the

queued

buffer

control

around

applied

number

buffer

primary

CSO

ALT

necessary,

that

ADFA

NMI

accessing

the

CSR]

data-out

(see

Section

disables

function

the

2.10.2.2 Error
applied

are

ADFA
outputs;
and ADFA DEC

Logic

The primary and alternate board numbers

a parity checker along with two other decode RAM

MEM ADDR (true when the memory is being addressed)
a parity error is detected, the
If
RAM PARITY.

checker

asserts B DECR PAR ERR which in turn asserts AMRM INT ERR

shown

Figure

an OR gate. AMRM INT ERR is distributed throughout the MRM as

via

2-34,

Other OR gate inputs that will cause an internal error are:
®

The negation of B ECL RC POWER OK from the BBU.

)

from the memory array
error
parity
A command/address
(AMAR CMD ADDR PAR ERR) if the array module is validated
by AMSC1

DLY7 BD VALID from the MSCl.

AMRM INT ERR is locked-up and remains asserted for a minimum of 15
1/2 bus cycles after which BMDP DLY INT ERR is received from the
MDBC to <clear AMRM INT ERR. Fifteen and one-half bus cycles is
sufficient

time

for

the

system

to flush queues and prepare to

The flush of read commands gqueued in the RCS is
start over.
AMRM INT ERR will not clear
checked by monitoring BRCS EMPTY.
until the RCS buffer is empty (BRCS EMPTY asserted).

AMRM INT ERR also asserts A BLOCK PROBE which prevents any command
from executing by inhibiting any memory or CSR probe-valid
signals. In addition, it asserts AMRM FLUSH DATA to the MDBC where
it clears all the MDB input commands and resets the MDB input
logic.

A system unjam or reset signal also asserts A BLOCK PROBE.

Command /Address/Size Buffer (Figure 2-37)
2.10.3
A three-bit command (BDFA CMD<2:0>) and a two-bit size code (BDFA
(ADFA DATA
address
two-bit
a
and
FUNK,
from the
STZE<1:0>)

from the DAD, are input into a three-stage buffer. If
the buffer can hold the command, address, and size
associated with three queued commands. B HOLD CS2, A HOLD CS1l, and
latch the
logic,
controcl
buffer
the
from
Cs0
HOLD
B

ADDR<3:2>)
necessary,

command/address/size data in the buffer.

If no commands are queued, A FIRST from the buffer control logic
command/address/size data around the
the
and bypasses
true
is
latches via a mux (except during the write portion of a
buffer

masked-write).

2.10.3.1 Command Channel -- The three command bits are:
0 = read;

1 = write

)

BDFA CMD<K2> = write bit;

BDFA CMD<O0> = mask bit; 0 = non-masked;

BDFA CMD<K1> = CSR bit;

0 = memory;

2-116

1 = CSR

1 = masked

—

BDFA

CMD<2> [ TAT]—[>o—

()|

(2)

—p{ LD

BDFA

___CMD<0:

XI
LTT-C

(2)

LD
[

I TAT

(2)

ADFA_ DATA
ADDR<3:?>

|
|
|
|

%
|

B_HOLD

€S0

B_HOLD C52

(3)
LD

(3)

(2)

A MASK

(3)l/

(3)

A_PRE
STADDR<1>

A DO MASK

| A PRE STADDR<0s:

A PRE STADDR<1:0>

(3)

l
—(5))SSRLOPER

g5 2.35,

5| 2-36)

'
|
|
|

S|
|
|

I|
|

_A_MASK CMD<2:1>

A_MASK CMD<0> \

”

A FIRST

BYPRSS

|
|

—

NOTE:
NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
SCLD-3556

Figure

2-37

)

o1
A

FIG.2-41

o[ AT

i
=

Do-

>:! A_MASK CMD<2:0> f

LAT

(3)

[

hY|

(2)

(3)
a0

(2)

—»|LD

L_DX3A WRITE

QVing

—

I>o

» LD

(2)
LD

A HOLDOLD CS1CS

A PRE_READ

'|SkFic.2-a1)

(

OVlipe

).i

)

(2)

—» LD
y

(2)

(2) b—-—|o

~— LD

BDFA

(2)

Command/Address/Size

Buffer

The
a

output
read

this.

Note

asserted),

masked

When

is
to

the

after

1in

masked

PRE

READ

forced

command
to

the
the

the

CSR

PRE

the

READ)

first

write
true

and

the

asserted

latch

operation

for

and

CMD

and

the

forces

CSR

will
the

the

During

negates

code

control

mux.

asserts

This

access,

bit

<channel

output

MASK
L

address
buffer

read/write

feeds
A

channel

inversion

that
A

CSRl,

assert

muxes

read/write
An

(BDFA

read

CMD<0>

portion

PRE

asserts.

0:1

BNUM

causing

probe

channel

contain

portion

into

the

and

two

CSR

the

access

CSR1

OPER

mux

that

logic.

CSR

the

write

READ

for

accomplishes

write,.

The

the

operation.

masked

channels

CMD

for

write,
via

the

write

oneration
~r

2.10.3.2

Address/Size

address

channel

size

channel

During

the

CMD<0>

for

MASK
the

address

Dbits

size

the

masked

and

the

masked

write

and

the

length

bit

addition,

address

command

2.10.4

Size
logic

size

state

the

Logic

The

MASK

address
The

are

the

bits

size

bits

output

the

output

the

will
will

with

the

the
read

the

starting

the

read

portion

masked

address

bits

write.

selected
mask

from
the

are

false

the
the

during

starting

BYPASS

output
output

obtained

CMD<2:0>

portion

forces

channels

are

stored

associated
used

write

MASK

were

A MASK

bit
now

channels

CMD<2:0>

they

write.

and

(Figure

receives

0s,

address

that
and

the
the

and

size

from

the

that

2-38)

two-bit

buffer,

commanded

machine

operation.

The

CMD<2:0>).

command/address/size

size

where

length

for

CSR

MASK

The

size

and

-~-

STADDR<1:0>.

bits.

buffer

read/write

PRE

portion of a masked write, A DO MASK asserts and
CMD<2:1> for the address bits, and 0 and A MASK

address/size

portion

A SIZE<1:0>.

write

substitutes
mask

Channel

and

size

transfer.

generates

SIZE<1:0>

code

Table
A

SIZE

2-9

code

generates

The

signals

logic

Code

Size

Longword

Octaword

Quadword

Hexword

2-118

SIZE<1:0>)

also

relating

shown

Size

signals

Table

specifying

the

contains

hex

2-9.

hexword

read

FNSU
) _A HEX
1(3))

\
BMRM

HEX- | SECOND ocTA
MACHINE & hEx sT<1:0j

>l BMAS,

(11)

HEX

(3))-A_SECONDARY

\!SIZE<«1:0

| 1 A SIZE<0>

7z LA ocTA

(3)

NOTE:
NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS

CONTAINING

CORRESPONDING LOGIC.
SCLD-356

Figure

discussing

°®

the

size

2-38

logic,

Size

three

Logic

points

must

quadword
transfer
1is treated
no
data
transferred
for

The

locations.

hexword

transfer

array

boards

longword

LEN

1is

array

for

operation,
bits

longword

OCTA

sent
A

LEN

PRE

n
READ

1
is

For

examined

two

octaword
size

write)

transfers.

transfers:

and

array

board

transfer

obtained

from

octaword

making

operation

assert

LEN

READ

LEN

the

asserted

gate

buffer.

~s
false

PRE

part
and

AND

command/address/size

will

that
For

A
SNA~
to
specify

true),

except

the

when

0:0).

the
and

the

longword

read

current

identical

transfer

two

false

and

(size

that

for

the

indicates

octaword

bit

from

specified

only

(read

READ

only)

transfer.

A OCTA

treated

recognize

negated

transfer.

are

operation.
an

1length

PRE

longword

size

(read

octaword

receives

write

the

command.

transfer

noted:

as an octaword transfer
the
third
and
fourth

with

octaword

hexword

transfers).

2-119

command

SIZE<0>

which

transfer

1is

octaword

asserted

(two

for

octaword

A HEX indicates that the current command is a hexword operation.,
HEX asserts when a size code of 1:1 is detected.

A
hex state machine receives A HEX and BMAS CMD ACPT which places
the
machine
into
various
hex
states during the execution of a
hexword
read operation. The machine generates a two-bit hex state
code
(B
HEX
S8T<1:0>)
that
indicates
the current state of the
machine.

Figure

2-39

1is

a flow diagram of

the operation of

the hex state

machine
during
the
execution
of a hexword command. The machine
idles
in
state
0
while
waiting
for a hex command. When a hex
command
is received, A HEX asserts causing the machine to advance
to state 2 (1:0) while the MCL attempts to send the first octaword
read
command.
When the array board accepts the octaword command,
BMAS

CMD

ACPT

signifies

that

asserts
the

first

which

turn asserts A HEX ST.

octaword has

been

A HEX ST

sent.

A
HEX will still be asserted to send the second octaword command,
unless the write portion of a masked write is ready to execute. If
this
1is
the
<case,
A HEX will be false placing the machine into
state
3
(1:1)
until
the masked write completes., While A HEX is
-

false,

will

PRl

the state machine does not respond to BMAS CMD ACPT

assert due

(which

to the masked write).

The
true
state
of
A
HEX places the machine into state 1 (0:1)
signifying
that the MCL is attempting to send the second octaword
command.
When
in
state
1, the machine outputs BMRM SECOMD OCTA
signifying
that
the
current command is the second octaword of a
hexword

has

been

returns

transfer.

BMAS CMD ACPT asserts when the

accepted

to state

to await

BMRM SECOND OCTA is used
the

the

second octaword

array

board.

another

hexword

increment

second octaword

The state machine
read

then

command.

the address from the MDB for

location.

A
HEX ST is applied to an AND gate that checks for a size code of
1:1.
When a 1:1 size code is detected (hex transfer), A SECONDARY
is asserted to the BNUM probe buffer to select the alternate board
number

for

the

second

octaword

transfer.

Starting Address Logic (Figure 2-40)
2.10.5
The
starting
address
1logic
<converts
the
pre-starting address
received
from the command/address/size buffer (A PRE STADDR<1:0>)
into
an
1initial
starting
address
(A
INIT
STADDRK1:0>)
that
specifies
which
bank on the array board is to be accessed first.
In
addition,
the logic increments the starting address during an
octaword
write
operation
to
access the four banks on the array
board.

2.10.5.1 Initial

passed

through

Starting

the

Address -- The pre-starting address

1initial

address

2-120

logic to become

the

1is

initial

Start

v
B

HEX ST<1:0>

0:0

1:0

v
+ A HEX

HEX ST<1:0>

Send first
command.

octaword

1¢1-¢

BMAS
CMD ACPT

HEX

First

octaword

command

B HEX ST<1:0>
Write

1:1

portion
of

masked-write is

executing.

sent.

YES

B HEX ST<1:0>
Send

= 0:1

* BMRM SECOND OCTA

v A HEX

¢ A HEX ST

Second octaword
command sent.

second

octaword command.

B
BMAS
CMD ACPT

NO
—

HEX ST<1:0>

v
Done

0 0

)
SCLD-354

Figure

2-39

Hex

State

Machine

Flow

Diagram

—

A_PRE
INITIAL
:
HMINITIALL
STADDR<1:0>

A INIT
.
STADDR<1:0>

LOGIC

)

AMARM

STADDR<1:0>

(5)

XI
¢¢1-¢

A_PRE READ _pf

JA S1ZE<1:0>

»|ADDRESS
fCONTROL

)

A_MASE

A_DO MASK

(5)

—

E A GLK

—INCREMENTER

()|~_

F B CLK

(5)

(F1G.2-42)

MaCRINE 1oLE

A WRIT

BMAS

CMD ACPT

(9)

B START
—|_G WRITE MACHINE
o) (

1 B WRITE

> (FIG.2-42)

NOTE:

NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
SCLD-361

Figure

2-40

Starting Address Logic

address.

bits

initial

zero

choice

2-10

the

address

initial

2-10

Command

All

For

OW Writes

First

Bits

For

masked

or
a

normal

forced
masked

The

1initial

octaword

1initial

the

write

negated

writes,

A normal

initial

MASK

the

establish

initial

or masked

address

size

write,

code

the

address

longword write

control

(0:0)

bank.
a

write

The
and

octaword

must

checks

for

establish

the

address

both

control

size

<0>

either

code

pre-address

address

with

the

checks

(0:1)

bit

with

the

checks

(1:0)

bits

are

normal

write,

writes,

start

starting

start

quadword

starting

control

«code

must

initial
a

quadword

initial

size

pre-address

quadword

address

address
wuse

has

the

starting

that

control

portion

initial

the

0:0.

first

for

array

bank

negated

establish

the

(bank

PRE

command

READ
as

write.

The

write

0).

control

The

READ

masked

and

write.

PRE

giving

identical

any bank and an octaword
address control checks for

initial

longword

array

command

octaword

masked
A

zero

bank.
and

third

the

access

longword

quadword

negated

establish
For

any

address

bit,

read.

longword

the

and

pre-address.

READ

zero.

first

The

READ

masked

command

for

initial

bank.

third

STADDR<1:0>

can

any

forced.

PRE

the

PRE

are
A

read

PRE

reads,

normal

1longword

at
A

shown

Corresponding

made

0O>*

OW Writes

negated

torced

First

Any

normal

Accessed

Any

Table

STADDR

start

identical
can

pre-address

Bank

asserted

command

INIT

normal

can

specific

Truth

pre-address.

read

Address

Reads

1Initial

LW Writes

all

forces

logic,

thereby restricting the
banks that can be selected as the starting bank. Table
truth table of the initial address.

Table

For

control

address

been

receives

masked

pre-starting

a masked-write,

address
stored

used
in

asserted

the

mask

2-123

operation,

address

the

for

the

write

unchanged.

pre-starting

read

portion

address/size

MASK

which

the

During

the

address

during

tells

the

buffer.

the

masked

2.10.5.2 Address

Incrementation

The initial address from the

initial address logic (A INIT STADDR<1:0>) is passed through a mux

and output from the MSC as AMRM STADDR<1:0> for transmission to
the array board. The true state of A WRITE MACHINE IDLE from the
write-command logic causes the mux to select the initial starting
address as the AMRM STADDR<1:0> output.

For

longword

read

write,

the

specifies the only bank to be accessed.

initial

starting address

For an octaword read, the array board needs only the starting
address. The length command bit specifies an octaword transfer to
the array boards which reads the four array banks starting with
the bank selected by the initial starting address.

For an octaword (and quadword) write, the initial starting address
must be incremented because four longword writes are to be

The

executed.
loaded

WRITE

1initial

starting

address

(AMRM

STADDR<1:0>) 1is

into an incrementer. The incrementer is enabled by B START

MACHINE from the write-command logic when an octaword write

command 1is received. B START WRITE MACHINE is validated by BMAS
CMD ACPT when the array board has accepted the BNUM probe. When

the incrementer 1is enabled, the 1initial starting address is
removed, and F A CLK and F B CLK function to increment the initial
address to select subsequent banks in the array board. Once the

write machine starts, the write-command logic negates A WRITE
MACHINE IDLE causing the mux to select the incremented address for

the
the

AMRM STADDR<1:0> output. The incrementer is held enabled for
octaword command by the binary state code (B WRITE ST<1:0>)

from the write machine.

Mask Address/Size Buffer (Figure 2-41)
2.10.6
The mask address/size buffer receives the starting address (AMRM

STADDR<1:0>) and the length bit (A LEN) associated with every
command sent to the array boards. The starting address and length
bit pass through three buffer stages and are loaded into an output

latch by A NEW MASK from the mask-write logic. A NEW MASK asserts
only when the mask-write logic senses the read portion of a masked

write operation. Hence, only the starting address and iength bit
associated with a masked write are loaded into the output latch
and made available to the command/address/size buffer.

The starting address and length bit associated with three read
operations (including masked-write reads) can be stored in the
buf fer. When a read command is received (A PRE READ true), and the
array board has accepted the command (BMAS CMD ACPT true), and the
read access is to memory (A CSR CMD false), a latch is set
asserting A VALID RD<0O>. A VALID RD<0> becomes B VALID RD<1> which
A VALID RD<2>. A POP 1is received from the
becomes
then
masked-write logic and is asserted every time a new read command
If A POP is false when A VALID RD<2> asserts, the read
executes.
command

latch

didn't

the

execute (array board busy) and B HOLD2 asserts to

starting

address

and

length bit associated with the

AVRM

STADDR<1:0>
A LEN

TaT

(6)

—>0—»|LD

CAT

LAT

(6)

LAT

(6)

I-[)o—» LD

A_MASK

—

r’ LD
A

NEW MASK

POP

Y (FIG.2-43)

GZ1-¢

A
Csm
|

HOLD2

77,

Rosrs

VALID

[ LAT <« BD<1>
(7)

A_HOLD1

B_HOLDO

le-o<]

VALID
A

LAT| . RD<0>

LAT

(7)

avp

PRE_READ

(7)] BMAS cMD AcPT D

(F1G.2-37)

"
e—o—

{

)

G-

]

NOTE:
NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
SCLD-360

Figure

2-41

Mask Address/Size Buffer

pending

read

HOLD2

command.

latch

B HOLD2

latches A VALID RD<2>

to maintain

the

signal.

another read command is received while A POP is still false, A

VALID RD<K0O> asserts causing B VALID RD<K1> to assert. B VALID RD<1>
causes A HOLD1l to assert and latch the starting address and length
bit
associated with the second read command. A HOLD1 latches up B
VALID RD<1> to maintain the A HOLDl1 latch signal.
Likewise,
1if
VALID
RD<0>
length

a
third read command is accepted, it will assert A
and B HOLDO to latch up the third set of address and

bits,

When
A POP does assert, B HOLD2 negates, in turn negating A HOLDI
~ A
»
OAT
N
11
y 3
+h
AA
]
:
and
B
HOLDO,
allowing
the
address
and
length bits
to procceed
through
the
buffer.
Address
and length bits that are part of a
masked
write
will get loaded into the output latch by A MASK and
be applied to the command/address/size buffer as A MASK CMD<2:0>.

2.10.7
Write Command Logic (Figure
The
write
command
logic generates

2-42)
a two-bit write

command

(BMRM

WRITE CMD<K1:0>) for the MDBC that specifies a write command as the
first
longword of a transfer or a "next" longword, and identifies
the
first longword as masked or normal. The logic also contains a
write-state
machine that generates a two-bit, write-state code (B
WRITE ST<1:0>) related to an octaword write operation.

2.10.7.1 Write

assertion
is

received.

Machine

The

Once

The

write

machine

START WRITE MACHINE asserts

write

MACHINE

is started by the

of B START WRITE MACHINE when an octaword write

machine

IDLE

1is

has

allowed a

(A CMD PROC

START

The

command

a write

The

command

an octaword

the

write
by

neutral

state

(A WRITE

command process

to start

true).

The buffer control

incremented

its

command

when:

machine

true),

1is

(A WRITE

true).

transfer

started,

BMAS CMD ACPT each time

the

(A OCTA true).

write-state

code is

the array board accepts

longword
write command. The write-state code indicates the status
of
the
octaword
transfer
by indicating which longword is being
transferred.
The
write-state
code
does not increment in binary
format,

can

seen

Table

2-11.

|
[

B_WRITE

S$T<1>

ST<0»>

_WRITE

DO _MASK

XBFWZZIDEQ&QW&g__J
*

BMAM
(9)

ST

B_WRITE

B WRITE!

LCT-C

—

B_WRITE

[ >0

WRITE
‘:.(9) AMACHINE
IDLE

ST<1>

- B_WRITE ST<0> M

(FIG.2-35))

OCTA

wmfi?
CMD

TART

START

BMAM
WRITE

CMD EN

B LW WRITE CMD

BMAS CMD ACPT

(FIGS.2-35,

2-44)

%(FIG.2-44)

WRITE

MACHINE

FACLK
I

(10)

(FIG.2-40)

)l' PP

INC

—A(FI1G.2-40)

NOTE:
NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
SCLD-358

Figure

2-42

Write

Command

Logic

B WRITE ST
0>

O O

longword
longword
longword
longword

Binary
State
N WO

Longword Being

Transferred
1st
2nd
3rd
4th

Write State Code

2-11

O =
O

Table

Once the write state code advances from its neutral (0:0) state, A
IDLE negates which in turn negates B START WRITE
WRITE MACHINE
MACHINE.

2.10.7.2 Write Command Bits -- Write command bits BMRM WRITE
CMD<1:0> identify every write command as the first or following
longword 1in a write transfer, and the first longword as masked or
The bits are generated by two AND gates enabled by BMRM
normal.
WRITE CMD EN whenever a write command is issued by the MRM. BMRM
is asserted Dy:

WRITE CMD EN

WRITE

from the command-done logic whenever a

CMD

START WRITE MACHINE for the first longword transferred

The

longword write command is received, or by
in an octaword write command,

WRITE

ST<1:0>

or by

code during the 2nd, 3rd, and 4th

longword transferred during an octaword write command.

Table 2-12 defines the write command bit code that is generated.
Table
BMRM WRITE CMD

2-12

Write Command Code

Function

No Op

O
1

First masked longword
First normal longword

1
1

longword (normal or masked)

As seen in Table 2-12, an asserted BMRM WRITE CMD<1> indicates the
longword 1in a transfer. BMRM WRITE CMD<1> is asserted by A
first
WRITE MACHINE IDLE which is true except when the write machine is
or fourth longword of an
third,
stepping through the second,

N
0

Jomaert

transfer.

octaword

asserted

BMRM

WRITE

CMD<KO>

indicates

performs

AV4

the

first

two

functions:

longword

transfer

being

normal.

During

indicates

the

first

state-code
MASK.

1is
DO

CMD<0>

WRITE

CMD<O0>

During

the

transter,

making

1is

true

negate.

For

normal

being
a

for

"next"

write

transfer,

WRITE

CMD<0>

masked

write

writes,

longword.

the

function

causing

MASK

write
of

BMRM

false

WRITE

and

BMRM

asserted.

second,

BMRM

MASK

third,

and

write-state

keeping

longwords

longword

0:0

the

thereby

BMRM

"next"

code

WRITE

fourth

longword

has

least

CMD<K0>

asserted

one

bit

octaword
asserted,

indicate

the

three

longwords.

2.10.8
Masked-Write Logic (Figure 2-43)
masked-write
1logic senses when the write portion of a masked
write
1s
commanded
and
generates
A
NEW MASK and A DO MASK to
The

inform

The

the

MRM.

masked-write

CMD<1:0>

from

normal

longword

and

transfer

READ

CMD<O0>

NEW

LW,

POP

asserts.

the

1is

true

FIRST

this

any

butffer

longword

and

true

the

mask

NEW MASK

loads

the

MASK

buffer

until

checks

operation
MASK

while

the

also

mask

do-mask

address/size
to

first

2-6).

read

SERIAL

command

the

transfer
by

buffer

pass

BMRM

false),

through

first

longword

masked

write

operation

where

all

the
read

and

asserts

masked

NEW MASK

buffer

array

board
MASK

number
loads

making

(AMRM
to

specifying

transfer.

NEW

from

the

MASK

the

write

the

first
probe

MASC.

address/size

available

mask-pending
A

completed.

1IDLE

not

true)
B

asserts

2-129

and

ALLOW

lock-up

PEND

command

block.

block

MASK

new

machine

MACHINE

lock-up

PEND.

write

lock-up

BNUM

the

READ

the

applied

masked

WRITE

do-mask

READ

command

validated

the

gqueue

1inhibit

the

for

Table

are

AMRM

read

buffer.

that

(A
a

buffer,

buffer

holds

control

initiated
PEND

and

the

bits

(BMRM

address/size

part

from

read

(see

longword

read

normal).

being

command/address/size
NEW

part

address/size

asserts

sent

CSR

MDP

the
data

first

the

bits

longword

asserts

buffer,
mask

command

determine

current

address/length

POP

and

the

"next"

for the
a

read
to

queued

command

false),

1if
a

LW.
not

at
MSCl

(masked

read

POP

Hence,

CMD<1>
probe

and

transfers

the

masked,

asserts

allows

1looks

and

the

and

RCS

AMRM

buffer.

logic

the

block

applied

process

In
then

holds

from
an

the

being

A MASK

octaword

asserts

clears

which
to

addition,

executing

MASK

and

MASK

MASK.

ALLOW
PEND

(FIG.2-42)

A WRITE
MACHINE

IDLE

(FI1G.2-35)

0el-¢

(F1G.2-36)

(FIG.2-41)

BMRM NEW LW

BMAM EN

SERIAL_AD[>o

READ

CMD<0>

;

AERY cMD<1

MASK T

PENDING

A FIRST

LOCK-UP

| RO LW

MASK b

X (F1G.2-35)

fLLOW

A DO MASK

)MAsK—pfoo

—

LOCK-UP

CLR

HOLD

BVRM

UEUSE K(FI1G.2-44)

—oH(_
] bwas owp acer | K

[o-A-HoP
A

NOTE:

THE LOGIC
SHEET

THIS

OF THE

FIGURE

CONTAINED

ENGINEERING

DRAWINGS.

SCLD-1357

Figure

2-43

Mask

Write

Logic

MASK

stays

the

ACPT)

from

2.10.9
The

true

the

Command

processing
or

the

BMRM

Done

the

NAB.
PRE

control

MASK

the

(including

MSC

the

read

normal

write

for

masked-write

all

2.10.9.1
A.

BMSC

Non-Hex

Read

completion

true

HEX

CMD.

The

MSC
be

DONE.

Hex

The

Read

state

Normal

The

hex
in

command

assertion

requires

that

and

the

BMSC

of
PRE

indicated

BMAS

CMD

MSCl

MSC

BMSC

asserted

for

all

masked-write

MASK

DONE

non-hex

has

completed

command

data

onto

CMD

DONE

PRE
to

the

read

commands

command)

asserted

buffer

and

all

the

RCS

PRE

READ

-Done

processing
is

READ

indicated

CMD

requires

the

that

read

command

assertion

the

command

data

CMD PROC START true) and that the
state (A WRITE MACHINE IDLE true).

READ

CMD

results

the

asserticon

write

BMSC

PRE

Done

MSC

processing

size

0:1

logic.

command

HEX
A

hex

results

Commands

the

hexword

read

ST<1:0>

0:1)

state

Q:1

hexword

assertion

read

has

BMSC

command

from

the

hex

indicates

the

been

PRE

sent

CMD

DONE.

Done

of
MSC processing of a normal or masked longwo
rd
(A WRITE true and A OCTA false) is indica
ted by the
B
LW
WRITE
CMD.
The assertion of B LW WRITE CMD
the
command
data be in the MSC (A CMD PROC START

that

the

true).

MSC

has

board.

the

IDLE

The

DONE

read

MACHINE

array

CMD

state

0:1

Write

completion

true)

PRE

board*,.

state

write

the

driving

BMSC

false)

idle

octaword

array

hex

MSC

Commands

machine

second

its

completion

indicated

that

commands.

buffers

assertion

CMD

the

assertion

the

machine

and

assertion

DONE

2-44)
MRM

the

Commands

READ

(validated

portion

CMD

The

completed

USE

the

command

commands.

PRE

BUF

(Figure

informs

indicated

DONE.

write

CLEAR
logic.

Logic

logic

current

This

BMSC

masked

command-done

the

until

assertion

only
The

write

array

machine

transmit
board

then

2-131

its

octaword
reads

the

idle

state

read

command

four

longwords.

WRITE

the

A_HEX

-v

N
llJ

-—17;;\ B READ CMD
_k-/

{ A PRE READ
1 A wRITE
(F|G.2_42):_MAQHJNEJDLE___
A CMD
PROC START

(FIG.2-35)

)

A _OCTA

$ A WRITE
-42)

(FIG.2

D”

(8)

]

B HEX ST<0>

(9)PRE

BMSC

CMD DONE Yy

A DO MASK

<=y AVENR BUF USE
(8))WRITE CMD 9P
L B
B LW

‘

(

BMSC
o))—PhE MASK DONE

|}(FIG.2-43)
—

B WRITE_ST<1>

—-~— B_WRITE ST<0>
—

—_
NOTE:

NUMBER DESIGNATIONS IN PARENTHESES

REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

SCLD-353

Figure 2-44

Command Done Logic

The
completion
of
(normal
or
masked)

MSC
processing
is indicated by

of an octaword write command
a write state of 1:0 (B WRITE
ST<1:0>
= 1:0) from the write machine in the write-command logic.
A
write
state
of
1:0
indicates
the last longword write of an
octaword write has started (see Table 2-11).

An asserted B LW WRITE CMD or a 1:0 write state asserts BMRM CLEAR
BUF
USE
signifying the completion of MSC processing of any write
command.
BMRM CLR BUF USE is sent to the MDBC where it clears the
MDB write control logic.
BMRM
CLEAR
BUF
USE
1is
ANDed
with a negated A DO MASK (normal
write)
causing
BMSC
PRE
CMD
DONE
to
assert
signifying
the
completion of MSC processing of any normal write command.

2.10.9.2
asserted

BMSC
PRE
MASK DONE -- BMRM CLR BUF USE is ANDed with an
A
DO
MASK (masked write) causing BMSC PRE MASK DONE to
The
assertion
of
BMSC
PRE
MASK
DONE
signifies
the

assert.
completion

2.10.10
Figure
command

command
bit

for

Parity
command

°®
)

MSC

processing

Command Parity
2-~34
depicts a
parity

bit

parity
the

array

any masked

command parity

(BMSC

bit

CMD PAR)

generate

for

the

write

command.

generator

which

the

The

MASC.

final

generates

MASC

uses

command/address

the

parity

board.

bit
BMSC
signals:

CMD

PAR

generated on

the

following

five

MSC

A WRITE from the command/address/size buffer.
AMRM STADDR<1:0> from the starting address logic.
A LEN from the size logic.
A HEX from the size logic.
A HEX ST from the size logic.

°
®

)

2.11
MEMORY SEQUENCE CONTROL 1 (MSC1l) MCA
The
MSC1
MCA
(along
with
the
MSC
MCA) recives and processes
commands
for
the
array
modules.
The MSCl is divided into four
functional
areas
and
a block diagram is provided for each area.
The
four
diagrams
1illustrate
the
entire
MCA.
All
the
MCA
input/output
signals
are
shown on the diagrams with each signal
having
a
source
or destination referenced, by figure number, to
other
The

functional

area(s).

four

functional

areas

are

defined

Mask
Store
-- stores four-bit masks associated with the
data
longwords
in
the X and Y portions of the MDB data
buffer.
Generates the write-enable signals for the MDB W
and C write ports.

2-133

below.

Select-Out

Buffer

Control --

a target array board

busy,
the
select-out
buffer
control
will queue up to
three
select-out
signals
in a select-out buffer in the
MDB
address
I/0O
select
1logic. When the array board is
free,
the
control
allows
the
select
signals to pass
through

the

buffer.

Read
Buffer
Control -- if a target array board is busy,
the read buffer control will queue up to three select-out
signals
associated
with read commands, in a read buffer
in
the
MDB address I/0 select logic. In addition, up to
three
second-octa
flags
can
be
queued
1in a hex read
buffer.
When the array board is free, the control allows
the select bits and the second-octa flags to pass through
the

buifers.

MDB
Address I/0 Select Logic -- generates the address-in
select
bits
that
1locate
the
command
address
1in the
address
buffer
portion
of
the MDB. Also generates the
address-out
select
bits
that select the address in the
address

buffer

that

output

from the MDB to the

array

board.

2.11.1
Mask Store (Figure 2-45)
The
mask
fields
associated
with
each
data
1longword
(ADFA
MASK<3:0>)
are
received
from
the
ARID
and
applied to four Y
latches

and

four X

latches.

BMDP DATA IN SEL<2> from the MDBC specifies which portion (X or Y)
of
the
MDB data buffer is being loaded with the write data. With
BMDP
DATA
1IN
SEL<2>
asserted (Y buffer being loaded), A LOAD Y
asserts to allow the four Y latches to be loaded. When A LOAD Y is
false,

the

four X latches

are

allowed

load.

BDFA
LD
INPUT
DATA
from
the FUNK is asserted while the MDB is
being
loaded.
BDFA
LD
INPUT
DATA allows all the latches to be
loaded,
and
also starts an input-load counter. Once started, the
counter
sequence

latches.

operation

1s
incremented
each bus cycle by
through four outputs which enable

When
1is

sequence,

the

1latches

load

the

being executed,

F A CLK and F B CLK to
the load inputs to the

are enabled and an octaword-write

LOAD Y<0>

through

latches.

For

LOAD ¥<3>

assert,

longword-write

operation,
BDFA
LD _.INPUT
DATA
1is asserted for only one cycle,
hence only LOAD Y<0> asserts to load the first Y latch.

A similar action occurs when the X latches are enabled.

ADFA
the

NEXT CLOCK asserts only for single-step operation,

input-load counter

hence

normally enabled.

The
four-bit
masks
are
unloaded
through
a
network
of muxes
controlled
by
a
two-bit, binary, mask-out code (MASK OUT<1:0>).
When
the
code
1is
0:0,
the masks in latch 0 (both X and Y) are

2-134

(FIG.2-9) _)l

ADFA MASK<3:0>

(FI1G.2-19)
)’I
'

NEel) (8)
o

A_LOAD. ¥

-~ v
(D) gmmn

LAT

LOAD

RBUT BaTA
(FiG.2-3) —}I——-

(FI1G.2-2) fl)mw
.

LoD

INPUT

[

(8)

)
Lo
(9)

*—:1;} Y<2»

A OUT

u‘%gr,

(9)

LOAD

:‘ED_[QL— 0
LOAD

]
i

>(F1a.2-17)

AWM INPUT

J(_nsxsgn._
AVRM_INPUT

(9)

.:T(—,,D_Y_db_

LOAD

(9)

LOAD

(9)

—

aour
OUT

(F1G.2-3)

AMRM_INPUT

—MAsela—

‘

HMI DEADY

GE1-C

LAT
-

(U)o

S—

N—

BMDP

DATA SEL<2>

—_—

4
LAT]7

:'ED_Xsb___

LOAD

(9)

LAT

"—:]’(T‘D_m;

e
.

LOAD

:1 a1)X

(FIG.2-51)

orgsoawx

(F13S.2-5,
AMAM
2-9, 2-23,¢—BEAD CMD<1> 4
2.34)

(F1G.2-52) -

MASK

MASK OQOUT<0>

COUNT<1.0>I 57

(10)

(10)
o

F A

CLK

(FIG.2-23)

QUT<1>

(10)

(F1G3.2-52) N

(9)

'(—!

(F1G.2-52) *

(10)

Do,

I
BMDP
WRAP HOLD
DATA

F B CLK

BMRM_RESET MASK CTA

NOTE:
NUMBER DESIGNATIONS IN PARENTHESES
AEFER TO ENGINEERING DRAWINGS

CONTAINING

CORRESPONDING

LOGIC.

8CLD 358

Figure

2-45

Mask

Store

Block

Diagram

unloaded
octaword

to become Y STRD MASK<0O> and X STRD MASK<0>. If an
write is executing, the code is incremented in binary

format to unload the other latches in sequence.

The MASK OUT code is obtained from a feedback counter started by A

MDP SEL<0> when read data associated with a masked write operation
is obtained. BRCS READ CMD<1>» 1is false when read data is
associated with a masked write operation (Table 2-6). Once
started, the counter output 1is incremented each bus cycle, in
binary format, by F A CLK and F B CLK.

BMDP FB DATA SEL<2> from the MDBC asserts when the Y buffer in the
MDB is selected for a data unload. Accordingly, Y STRD MASK<3:0>
is selected as A OUT MASK<3:0>. When the X buffer is selected for
a data unload, X STRD MASK<3:0> is selected as A OUT MASK<3:0>.

A OUT MASK<3:0> drives the write enable signals for both the W and
C write ports of the MDB. AMRM FB WRT EN<3:0> enables bytes of
read data from the array board to overwrite longword bytes of
masked-write data in the MDB via the C write port (Figure 2-17).
An AMRM FB WRT EN<3:0> output requires that the read data be
associated with a masked write operation (A MDP SELLU> truej. AN
asserted A OUT MASK bit negates the corresponding AMRM FB WRT EN
bit. Hence, the associated byte of read data is not written into
the MDB and the masked-write byte remains intact. A negated A OUT
MASK bit asserts the corresponding AMRM FB WRT EN bit, causing the
associated byte of read data to be written into the MDB and
thereby returned to the arrays.

AMRM INPUT WRT EN<3:0> enables bytes of data to be written into
the MDB via the W write port. For write operations (both normal

and masked), BMDP HOLD WRAP DATA is false and all four AMRM INPUT
WRT EN bits are asserted to write the entire longword from the NMI
(via the

DAD)

into the MDB.

when the read
routed through

data associated with a masked-write coperation is
the DAD for single-bit error correction, it 1is

returned to the MDB and is also loaded in via the W write port.
The corrected read data is byte-loaded into the MDB according to
the mask

bits.

BMDP HOLD WRAP DATA is asserted by the MDBC to hold the corrected
read data in the DAD until NMI traffic has stopped. BDFA NMI DEAD1
is asserted by the FUNK when NMI traffic has stopped. The true
state of these two signals make the AMRM INPUT WRT EN bits a
function of the A OUT MASK bits. An asserted A OUT MASK bit
negates the corresponding AMRM INPUT WRT EN bit. Hence, the
associated byte of read data is not written intc the MDBR and the
masked-write byte remains intact. A negated A OUT MASK bit asserts
the corresponding AMRM INPUT WRT EN Dbit, causing the associated
byte of read data to be written into the MDB and thus returned to

arrays.

the

For
normal
writes
and
masked
writss
with no single-blt =2rror
correction required, BMDP HOLD WRAP DATA is false and the mask-out
code
(MASK
OUT<1:0>)
1is
obtained
directly
from
the feedback
counter.
If
single-bit
error correction was required, BMDP HOLD
WRAP DATA 1is asserted and a delayed mask-out code 1s obtained from
three delay latches. The code 1s delayed and latched to select the
proper
mask for the corrected read data after it is returned from
the

DAD.

2.11.2
Select Out Buffer Control (Figure 2-46)
The
assertion of BDFA NEW CMD EARLY signifies a new valid address
is
ready
to be written into the MDB. If there is no parity error
associated

with

CMD asserts.
output

the

new

command

B NEW CMD informs

MDB

select

signal

(ADFA

PARITY

ERROR2

the MDB address

for

the

new

false),

I/0 select

B NEW

logic

address.

In
addition, B NEW CMD is clocked through two latches to become B
VALID CMDK1>. If the array board has accepted the BNUM probe (BMAS
CMD
ACPT true from the MASC) and the MSC has completed processing
the
command
(BMSC
PRE
CMD
DONE true from the MSC), B CMD DONE
asserts.,
B
CMD
DONE
prevents
B VALID CMD<K1> from reaching the
third
buffer
latch,
hence, A VALID CMD<K2> remains false thereby
supplying an asserted A FIRST signal to the MDB address I/O select
logic.
A
FIRST
bypasses the select signal around the select-out
butfer latches in the logic.

It
the
array
board is not yet able to accept the command or the
MSC is still processing the command (as in the case of an octaword
write
or
a hexword read), B CMD DONE will be false. In this case
the
third
buffer
1latch
is
set and A VALID CMD<2> asserts. The
assertion of A VALID CMD<2> will:

Negate
A
FIRST
select-out buffer

Assert

Latch A VALID CMD<2>

B
HOLD
another

latch

to
remove
the
bypass
path
1in
the
in the MDB address I/0 select logic.

B HOLD CS2 to the MDB address

the

select

signal

the

I/0 select

select-out

buffer.

logic to

to maintain B HOLD CS2 asserted.

CS$2
1is applied to an A-HOLD-CS1 AND gate which looks for
command
address as indicated by the assertion of B VALID

CMD<1>.

If
another
command
address
is
received,
BDFA
NEW
CMD EARLY
asserts,
followed
by the assertion of A VALID CMD<0> and B VALID

CMD<1>.

HOLD CS1

B VALID CMD<1>» enables
to

the

Latches

MDB

address

the

I/0

second

the A-HOLD-CS1 AND gate asscrting A
select

select

logic.

signal

HOLD CSl:

1in

the

select-out

bufter,

)

Latches

B VALID CMD<1>

to maintain

2-137

A HOLD CS1

asserted.

——> (F1G.2-48)

BMSC PRE

(FIG.2-34)

_>J

(FIG.2-49) -

CMD DONE
BMAS

—MD

BDFA NEW

ADFA
PARITY

NEW

CMD

> —

VALID
AT L|_CMD<0»
b

LD"'

VALID
LAT | CMD<1>

»|

-—|>o—> LD

LAT

VALID
CMD<2>

[

}D_CS2y,

Do LD

? (F1G.2-48)

A
HCLD CS1

———

BeT-¢

(F,G.z_s)._)_m,_QAD_E_l\_BLL

i
(FIG.2-7)-9!

’__DD_A_EURS_T______,

B_CMD [DIONE

A
HOLD CS1

p—

BHIDCSO
-

———

1]
NOTE:
THE LOGIC
SHEET 3

THIS

OF THE

FIGURE

ENGINEERING

CONTAINED

DRAWINGS.
SCLD-371

Figure

2-46

Select-Out

Buffer

Control

Block

Diagram

VALID

which

CMD<2>

looks

VALID

2.10.1.1)

before
to

Latches

DONE

This

the

MDB

2,11.3
When

pointer

latch

VALID

RDK1>

trom

the
read

bits

A VALID

causes

with

When
and

read

POP

does

HOLDO,

buffer,

MDB Address
MDB

locations

suceeding
from

the

always

error

(BMRM

MDB

page

right

EARLY

and

causes

HOLD2
MDB

MSC

has

true),

signals

select-buffer

RD<2>.
false

when

(array

HOLD2

while
RD<K1>
the

HOLD]l

POP

asserted

read

RD<0>

pending

the

and

select

becomes

received

every

time

VALID

RD<2>

board

busy)

and

latch

the

command.

still
B

HOLD2

false,

VALID

signal

MDB

signal.

assert.

latches

BNUM

true),

latch
POP

the

BD VALID

RD<1>

associated

B VALID RD<1>

A VALID

RD<0>

and

negates,
select

bits

turn
to

negating

Bits

SEL<2:0>)

The

the

pass

3-bit

increments

MDB

placing

the

buffer.

Command

addresses

the

for
logic

hence,

one

2-139

command

the

that

are

unloaded
locations

reserved
the

eight

address

succeeding

location

detects

address-in

through

buffer

loaded,

HOLD1

the

2-48)

Logic

through

(Figure

being

are

through

Select

except

HOLDO

proceed

Select

signal.

flag(s)

the

DONE

latch

second-octa

after

asserted.

and

true),

logic

select

the

address

buffer.

CMD

the

select

latch

PRE

A VALID
is

execute

accepted,

1In

available
address.

and

POP

VALID

CSO

true)

(BMAS

RD<K0>.

received
B

HOLD

READ

valid

the

third

ADDR

locations

are

CMD

CMD<0>

Section

signal.

I/O

Address

the

2,11.4

signal

(see

2-47)

I/O

with

assert,

and

output

(BMRM

logic

maintain

the

allowing

buffer.

2,11.4.]1

gate

order.

A VALID

didn't

latch

hex-read

select

AND

assertion

select-out

HOLD-CS

are

the

(BMSC

three

VALID

command.

command

latch

NAB

becomes

assert

HOLD1

NEW

VALID

CMD ACPT

the

address

command

logic

causing

read

the

accepted

maintain

signals

select

command

HOLD1

read

RD<2>

asserts

(Figure

the

MDB

second

third

associated

the

B-HOLD-CSO

BDFA

signal

received

command

asserted

1is

I/0

the

maintain

select

executes.

the

read

RD<K0>

free,

(BMAS

select

Control

address

latches

another

free

then

command

read

current

asserting

select

I1/0

which

the

command

select

causing

the

command

asserts

VALID

command

MDB

indicated

assertion

CMD<0>

the

Buffer

set

asserts,
HOLD2

board

address

and

new

third

asserts

read

board

The

VALID

allows

Read
a

applied

another

array

processing

CMD

are

which:

the

negate.

the

assert

array

CS1

command

asserts.

Latches

the
finished

HOLD
still

When
B

TIf

CMD<O0>

CS0

another

CMD<0>.

VALID

HOLD

and

for

the

location

i—
l

(FIG.2-48)

—AFQP

B
VALID

A
VALID

READ
\! BVRM
(5)

—Do—i LD

LAT

(8)

(5)

—-Do_> LD

HOLD1

0¥ 1-¢

(5)

i BMAS
—3-—BD VALID
(F1G.2-49)

3 1/2 CYCLE
LATCH
DELAY

{7)

NOTE:

NUMBER DESIGNATIONS IN PARENTHESES
REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.
SCLD-373

Figure

2-47

Read Buffer Control Block Diagram

(F1G.2 . 34)—1.

BMFM

SECOND OCTA,]

HEX

READ

BUFFER

—— W

(4)

AVEM

READ CMD<0>

(F1G.2-52)

(FIG.
2-45;

i T\ N

FlG.z-ze)—fl
XI

~"AMDP LD

(F1G.2-17)

—
)EE

]
(F1G6.2-2)

PAGE ADDR

> (FIG.2-47)

(FIG.2-47) { NOTE 3 )
.

IP1-C

pCT .
AT 8.LERR_A<2:0>

()

(8)
LD

)

AMAM ERR

Nryey

PLUS

.
ADDR PTR<2:0>

W—(F16.2-25)

A
DIFF

(6)

bt SEaa:0
L<2:0>]

(FIG.2-17)
|

(F1G.2-24)-Y

AMSC

)
(8)

S%ETCT

BUFFER

DO_MASK

DLY ADDR

SEL<2:0>

(‘)

ADOR IN

2:0>
9 (F1G.2-17)
(6) | BSELs

PLUS 2

‘

LAT |¢

LD}«

HEW _CMD

(8)

NOTES:

(FIG.2-46))———:|

(F|G.2.46))_LNQIE_ZJ_.

REFER TO ENGINEERING DRAWINGS
CONTAINING CORRESPONDING LOGIC.

(FIG.2-50)

FACK

1. NUMBER DESIGNATIONS IN PARENTHESES

(FIG.2-34)

A FIRST

B HOLD CS82

A HOLD CSt
B HOLD CSo

B HOLD2
A HOLD1
8 HOLDO
SCLD-367

Figure

2-48

MDB

Address

I/0

Select

Block

Diagram

contains
two

the error page address,

thereby

NEW

skipping over

CMD

assertion of

asserts

°®

when

increments the select bits by

location of

valid

the

error page

new command

address.

received.

The

B NEW CMD will:

Cause
D1

the

the BMRM ADDR IN SEL<2:0> output mux to select the

input

for

the

BMRM ADDR

Loads BMRM ADDR IN SEL<2:0>
A DLY ADDR

SEL<2:0>

output.

into a latch where

SEL<K2:0>.

it becomes

A DLY ADDR IN SEL<2:0> is incremented by 1 in plus-1 logic, and by
2
in
plus-2
logic.
The plus-1 incremented select bits are made
available
at the D1 input of a DIFF mux. They are also applied to
a
comparator where they are compared to the error address pointer
that specifies the buffer location of the address containing a bit
error.
If
the
two
sets
of
select
bits
are
not
equal, the
comparator
asserts
A
DIFF
which selects the plus-1 incremented
select bits as the BMRM ADDR IN SEL<2:0> output for the next B NEW
CMD. If they are equal, A DIFF is false and the plus-2 incremented
select
bits
are selected as the BMRM ADDR IN SEL<2:0> output for
the

new

command,

When
B NEW CMD negates, the BMRM ADDR IN SELK2:0> select bits are
maintained
by
feedback
of A DLY ADDR IN SEL<K2:0> through the DO
input

the

output

mux.

Address Out Select Bits -- A DLY ADDR IN SEL<2:0> is

2.11.4.2 MDB

applied
to a three-stage, select-out buffer which can queue up to
three
sets
of
select
bits if the array boards are not ready to
accept
commands
from the MCL. B HOLD CS2, A HOLD CSl, and B HOLD

CS0

are received from the select-out buffer control which asserts

them,
in
order,
1if
the
array
board(s)
are
busy.
The three
hold-signals latch the select signals associated with the commands
that
are
gqueued. If no signals are qgueued, the select-out buffer
control
asserts
A
FIRST which bypasses the select signal around
the
buffer
and applies it directly to the AMRM ADDR OUT SEL<2:0>
output
mux
where
it
is
selected as the AMRM ADDR OUT SEL<K2:0>
output.

AMRM
ADDR
OUT
SEL<2:0>
1is applied to a three-stage read buffer
where
up
to
three select signals associated with read commands,
signals (B HOLD2, A HOLDl, and B
latching
The
latched.
be
can
are asserted by the read-buffer control when read commands
HOLDQ)
are sensed but the target array board(s) are busy. The output from
the read buffer is loaded into a latch by A POP when a longword of
read

data

1is

received

from the arrays

(BMRM NEW LW true

and BMRM

EN
SERIAL RD false) and the longword is the first longword of the
transfer
(AMRM
READ
CMD<0>
true).
The latch output (B POT ERR
A<2:0>)
1is a stored set of select bits that represent a potential
error

address

(if

a bit

error

is detected

2-142

in the

read data),

and,

this

for

the

If
the

this
1is
MSC when

latched

POT
the
for

masked write

write

portion

operation,
the

masked

serves

2.11.5

POT

ERR A<K2:0>

AMDP
DLY

Error Address
the

LD
LD

MDB

a masked write operation, AMSC DO MASK is
the write portion initiates. AMSC DO MASK
for

the

AMRM ADDR OUT

ERR
A<2:0>
were the select-out bits for
masked
write. Now they are being used as
the write portion.

When

the

DCHK

select

bits

write.

asserted by
selects the

SEL<K2:0>

the
the

output.

read portion of
select-out bits

Pointer

detects

bit

error

the

read

data,

asserts

PAGE ADDR. AMDP LD PAGE ADDR ANDs with A POP to assert A
ERROR
PAGE ADDR when the read data is found to contain a

bit
error.
B
DLY
LD
ERROR
associated
with
the
error (B
outputs
the
error select bits

PAGE
ADDR
1loads
the select bits
POT ERR A<2:0>) into a latch which
as an error pointer (AMRM ERR ADDR

PTR<2:0>).

AMRM

ERR ADDR

PTR<2:0>

MDB

containing

the

PTR<2:0>

1is

location

11.6

also
the

BMRM
NAND

the

to a

discussed

MDBC

erroneous

the

location

data.

AMRM

comparator

2.11.4.1.

Section

reserve

the

ERR ADDR

the

pointer

INVERT ADDR4

Uoe

sent

applied

MDB

NCTA

UINL

address

iLib

varaiwuoad

FrAam

o L

reelved

hexword

read

+ha

MCO
Y

whan

LINJI N

executing.

Wil e 1k

BMRM

+hao

acar~r~nnA

SECOND OCTA

At atanrA

applied

to
a
three-stage,
hex-read
buffer identical to the three-stage
read
buffer.
Up to three BMRM SECOND OCTA flags can be queued in
the
buffer by the same three latch signals (B HOLD2, A HOLD1l, and
B
HOLDO)
that queued up to three sets of select bits in the read
buffer.
A
POP loads the the output of the hex-read buffer into a
latch
when the first longword of the second octaword is received.
The
latch
output
(B
SECOND HEX IN PROG) is loaded into another
latch
1if a bit error is detected during the second octaword read.
This causes B PRE ADDR<K3> to assert for the erroneous longword.
When

CSR1

true)

the
of

MDP
the

1is
a

read

result

where

MDB.

This

(BDFA CSR1
of

the

bit

flips

the

changes

the

octaword

where

the

bit

2.12

MEMORY ARRAY

error

4th

address

applied

composite

parity

bit

SERIAL

the

error

address

the

location

address
of

RD both

asserts
read

the

to
out

second

occurred.

from

generator

BMRM

INVERT ADDR4

SEQUENCE

parity

and

BMRM

bit

CONTROL

(MASC)

1in

MSC

2.12.1
Command/Address Parity
The
command
parity
generated
stored

DECODE

error,

the
in

(BMRM

the
MDB

the

(Figure

2-49)

CMD PAR)

and

the

STRD APARK3:0>)

are

(BMSC

(BMDP

MASC.

MCA

The

generator

CMD ADDR PARITY)

2-143

developes

over the

entire

___,____mm_mu_.[a_uul_____,
Y

oD PAR

(F1G.2-34)

- -—fl'—m*
BMDP STAD APAR<3:0
3

(FIG.2-17

ae waite

ATEp|y ERAGR
(FIG.2-51) ——JpCSBW.
N

%cficfi"m

(F16.2-2)

>4
[\o]
ot

(FIG.2-34)
telo 2.52)

RN“MP;‘K‘))E

ARCS_BD
_SELEN
Al

(F16.2-52)

F%erz0

LAT

A LD

» DLYZ

BNUM2<2:0y

DONE<2>

LAT

A LD

TAT

LD
EC <0»

(FIG.2-51)

—

(F:G»z-ma—““-‘cfl{ z

DAYR

RE
DONE

S
‘T

LOAD

BUAS

SECTION

(FIGS.2-34, qummme—]
2-46, 2-52)

f—

OURE [TTB NEXT

0 ACPT
——

(FIG.2-34)
)

DECOOER

BN AEAD

1o
ECL

(ri16.2-52)

BOFFER | BIARDRI22
MSC

PRORE VALID

2
:

>(F|e.z-u)

A EMPTY SEG<2:0»

MASC

S5C1L0 3%

Figure

2-49

MASC

Block

NAD

Me
or

&‘an@&$°>
enje
En ja-SELE N——{(F1G.2-52)

B neany
[Tri Ly OONE<7:0>

AVAR DATA
READY DONE<Z:0>

EGL
To

SnhiE

ARCS FORCE

M) ACFT

C*]

(FIG.2-47)

ECL

ApLyz
<2 0
NUM

pRELsl—p10

»(FIG.2-50
> 2-80)

SELez 0n

H‘

] en

= NAB

BRD
AMCL
|_SEL«<7:0>
ECL |7
BMM _BRD o) OO
stlazoe

BMAR SEND

o »r ]
U

~H(FI6.252)
p——

] %L | S CMineT0x

L——_————

PROBE_ENU
€D SEL
M =]
[

AMAR

kfi

JENABLE

£nylq B0_TEST WA EMABLE

v cusnE:?o,

H’E

—BWF\
____—Macs
Fulll

(F1G.2-34) ~

BMAS
BNUM<20>

TEST NAB

ECL JARRB
BAR . .y N Nag
[

¢ 0o

(FIG.2-19)

AMCL OMD

rayined PARITY
ADDR

PARITY
=

.ma_gAH..EmJ

;
FRTEy

Py 22520182

Diagram

NAB

command

address

and

placed

then

field.

BMRM

the

NAB

CMD ADDR
AMCL

2.12.2
Force Parity Error
Write data bits BMDP WRITE DATA<K23>
write

only

bits

testing.

AMRM

CSR2

enabling

write

data

while

bit

forced

1is

parity

the

2.12.3
The

Board

BNUM

MASC

BRD

SEL<X>.

<19>

where

FORCE

2.12.4

array

The

send-no-command

when

number

selects

the

command.

the

(via

gate)

being

sent

forced
or

for

write

assertion

error

function

command/address

FORCE

BAD

error.

is
bit

the

MASC

error

the

asserted

parity

DPAR
When

boards.

PROBE

BMAS

by
to

the

BD VALID,

array

ECL

the

BNUM<2:0>)

BNUM<2:0>

BMAS

from

1lines

TTL

outputs
also
The

one

asserted

become

array

the

applied

asserts

boards.

selected

1line

the

AMCL

BRD

for

the

board

CMD

RCS

buffers

selecting

array

also

AMSC

PROBE

SEL

board

the

masked

1inhibit

array

EN
BNUM

1is

applied

the

read

mux
The

MASC

SEND

are

received

are

asserted

from

the

refresh.

controlled
probe

associated

asserted,

the

inhibit

MCL,

the

board

number

the

probe

with
NO

CMD

command

during

(ARCS

FULL

true).

SEND

full

assertes
N wT

CANRNT
AT N
e

board

true

that

already
and

with

being

write.

BNUM<2:0>).
1line

command

doing

are

has

<2:0>

number

and

asserted

that
T dldtA

board

CMD<7:0>)

board),

asserted

data

from

(AMSC

READ

board.

condition
g
R
et

each

board

are

within

array

the

ARCS

cannot

PROBE
1is

SEND

from

send-no-command

third
Ak e de A

(AMAR

line

array

(AMSC

SEND

the

RCS.

enables

board

the

The

parity

array

(AMSC

lines

true)

the

(one

respective

occur

board

probe

MSC

converted

boards

the

are

errors

specify

BMRM

data

ERR

DATA<20:19>

Command

will

- -

the
error

forces

TTL

operation.
et
e A A2
3

This
probe

parity

logic.

asserted,

enabled

SEL<KX>

when

converted

BNUM<2:0>)

the

send-no-command
the

SELK7:0>

BRD

Send

Eight

(BMAS

from

line

force

DECODE

assert

forces

Number

SEL

forced

CMD ADDR PAR

sent

BRD

<20>
data

where

field

AMCL

commanded
S NP
|

from

bit

MDBC

used

force-parity-error

When

which,

BMRM

ADFA CSR2

BNUM<2:0>

decoder

seven

and

probe
BMAS

WRITE

and

negated,

command/address

are

<23>

PAR.

BMDP WRITE

and

specifies

generator

and

CSR2

the

bits
<19>

error.

asserted

<19>

CSR

PARITY

CMD ADDR

the

two

transfer

the

are

board.

read

2-145

CMD
Ls

RCS
new

for

for
A

command
N \W/LLLLLLCA
LL

masked

write.

masked

write,

which

compares

SEL<K2:0>

1is

write

portion

SEND

command

the
W lls~

ARCS

the

is
4 wJ

the

comparator

SEL<2:0>.

equal,

the

command

involved

been

enables

ARCS

saved

read

data

CMD
to

asserts

the

array

MASC

2.12.5

Empty

the array boards are free, as indicated by all eight AMAR
all
If
SEND NO CMD<7:0> lines being false, and the MASC queue is empty (A
all true), AMAS MASC EMPTY is asserted to the RCS
SEC<2:0>
EMPTY
to

inform

the

empty

status.

Board Select (BMAS BD SEL<2:0>)

2.12.6

ARCS BD SEL<2:0> from the RCS, specifies an array board containing
read data that 1is 1is available to the MCL. ARCS BD SEL<2:0> is
also used to specify the array board for the write portion of a
masked write operation.

During a read operation, the board select code outputs the MASC as

RMAS

BD SEL<2:0> where it is applied to a decoder. The decoder 1is

enabled by BRCS BD SEL EN from the RCS, and functions to assert
one of eight read-board-select lines (AMCL READ BD SELK7:0>) to
the array boards. The asserted AMCL READ BD SEL<K7:0> line enables
to send its read data to the MCL.
the selected array board
During a masked write operation, the decoder is not enabled. In
this case, BMAS BD SEL<2:0> is used by the MSC as the board number
for the write portion of the masked write.

2.12.7

Command

(BMAS CMD ACPT) and Board valid (BMAS BD

VALID)

BMAS CMD ACPT signifies to the MCL that the probe command was
accepted by the array board and processing of the command can
BMAS BD VALID signifies that the BNUM probe and command
proceed.
data on the NAB are valid.

For CSR operations, the RCS asserts ARCS FORCE CMD ACPT which
asserts BMAS CMD ACPT but negates BMAS BD VALID. The assertion of
BMAS CMD ACPT initiates the CSR command processing in the MCL. The
false state of BMAS BD VALID signifies the NAB data as invalid as
the command access is not to the array boards.

For non-CSR operations, the assertion of BMAS CMD ACPT causes BMAS

BD VALID

assert.

BMAS CMD ACPT is asserted from the load-section queue by any of
(A LD SEC<2:0>), provided A IN SEND NO
the load-section signals
CMD is false. A 1IN SEND NO CMD inhibits the processing of a
command due to the reasons discussed in Section 2.12.4.

AMSC PROBE VALID 1is received from the MSC when a new command 1is
received for the array boards. With no commands in the queue (A LD
SEC<2:0> all negated), AMSC PROBE VALID causes the load-section

queue to assert A LD SECK2>. A LD SECL2> loads the AMSC PROBE
BNUM<2:0> command probe into a latch. The latch output (A DLY2
causes a mux to monitor the data-ready-done line from
BNUM2<2:0>)
the array board selected by the BNUM probe. When AMAR DATA RDY

2-146

DONE<X>

asserts,

causing

The

SEC<2>

load-section

waiting

for

command

command,

address
NEXT

The

BNUM

mux

monitor

selected

the

still

another

1is

asserted,

the

third

DONE<2:0>

array

the
code

from

selected

from

second

the

first

starting

asserts

SEC<K1>

output

while

the

STADDR<1:0>)

latch

line

commands

boards.

addition,

bank

asserts
The

three
asserts

(AMRM

array

data-ready-done

similar

into

monitor

accepted
sequence

third

the

from

the

before
asserts

latch.

The

data-ready-done

EMPTY

SEC<2:0>

queue.

2.13
Three

All

the

These

1inputs

memory

system

2.13.1

RCS

the

load

causes

first
the

another

the

new

array

board

the

data-ready-done

SEC<K0>

latch

output

contols

line

from

the

load

third

1in

and

the

outputs

outputs
are

sequence

when

their

asserted.
full/empty

and

appear

referenced

on
to

status

2-52)
the

cover

three

other

the

RCS

diagrams.

figures

the

description.

Power Control
system

battery
DCLO
in

are

SEQUENCER (RCS) MCA
(Figures 2-50, 2-51,

inputs

and

assert

lines

indicates

READ CONTROL
block diagrams

MCA.

muxes,

data-ready-done

load-section

When

queue

board.

respective
A

the

latch.

command

load-section

probe.

BNUM probe
mux

from

command

next-bank

the

queue

re-asserts.

the

another

BNUM

line

array

with

into

data-ready-done

VALID

according

asserted

probe

<can

before

PROBE

associated

new

asserted

indication

received

AMSC

negate.

queue

"done"

BANK1<3:0>

bank.

DONE<K2>
to

power

(Figure

1is

2-50)

interrupted,

B
ECL RC POWER OK from the
backup
wunit
(BBU) is negated causing the assertion of A
the RCS. A DCLO is applied to an AND gate where it checks

that:

All

1in-process

EMPTY

All

reads

indicated
®

DLY

It
then
asserts
place
the
array
then

asserts

DOWN

asserts

AMRM

throughout

the

have

been

aborted

have
by

internal

(BMDP

writes

been

completed

(AMAS

MASC

true).

error

INT

ERR

all

signal

(RCS

via

reset

empty

has

been

asserted

the

MCL

true).

POWER

RESET

buffer

false).

AMRM FORCE BATTERY to the
boards
into battery mode

DELAYED

MCL

VALID<2:0>

DOWN

back

reset mux.

logic

and

2-147

BBU which proceeds to
of operation. The BBU

the

RCS.

AMRM

RESET

clear

queues.

DELAYED

POWER

distributed

(FIG.2-52)

AMAS MASC EMPTY

(FIG.2-49)

BMDP

DLY INT

(FIG.2-27)—3
B _ECL
RC POWER OK S,

AMRM

L__ED_EQBQE_EAHERY__)__(HG,Z-M)

I-—PFIG.2-5 2)

F
v

ERR

A DCIO

AMBRM RESET

(FI1G.2-53)<

B DELAYED POWER DOWN

B COLD
POWER UP

J—(FIGS.2-2,
|

2-34,

2-28,

2-48)

AMRM

CLEAR BATTERY

LAT

»—(FIG.2-53)

(¢0]

SCLD-352

Figure

2-50

Power

Control

When

power

array

data

outage,
the

returns,
was

1if

array

power

up).

CLEAR

BBU

the

cold
power

AMRM

RESET.

power

is
via

2.13.2
A

CSR

The

BBU

The
CSR

machine

state
PROBE

the

POWER

true),

CLEAR

becomes

AMRM

POWER

RESET

COLD

POWER

DOWN.

when

power

returns,

cold

prepares

the

BATTERY

also

function
negated

asserted.

(Figure

When

asserts,

the

negating

FALSE),

DELAYED

during

AMRM

POWER

causing

AMRM

code

CSR

DOWN

RESET

2-51)

CSR

idles

that

signals
in

idle

SERIAL

from

various

read

state

CSR

enabled

the

machine

determine

state

two-bit

generated

state

the

The

internal

COLD

where

POWER

DELAYED

CSR

RESET

and

AMRM

ECL

long
is

battery mode

state

BMRM

BBU

too

the

power

state

was

the

this

POWER

full/empty

output

outage

The

AMRM

indicates
during

from

the

holding

2.13.2.1

BBU

power

ECL

asserts,

Factors

power

executing

keeps

generates

machine
VALID

the

mux.

CSR Control

states.

reset

controls

that

thereby

negated

the

completed,

from

the

operation.

mux

has

OK.

from

battery

asserted

normal

function

state

which

1is

(powering-up

reset

1immediately

negate

lost
power

power

cold

the

cold

POWER

duration

BATTERY

the

ECL

COLD

was

return

switches

RESET

the

data

AMRM

maintained

state

the

MCL

BMRM

counters

the

buffer

MCL

locations

ST<1:0>

RCS

ST<1:0>)

RCS.
=

0:0).

When

move

into

machine

are:

(BRCS

other

EMPTY).

IDLE).

SERIAL

throughout

output

the

enables

the

MCL.

CSR data

CSR

bits

starts

serial

format.
BMRM

true)

when

SERIAL

2.13.2.2
the

the

BMRM

MCL

CSR

SERTAI,

RD<K2:0>

enabled

When
CLK.

enabled,
The

1is

AMRM

write

MCL

command

1is

CSR

write

during
is

read

state

BMRM

SERIAL

read

out

from

(while

output

<cleared

command
or

RD<2:0>

ARCS

read

FORCE

READ

specifies

CSR

read.

counter

SERIAL

incremented

(AMSC

during

serial

BMRM

CMD

BMRM

which

asserted).
CLK

ACPT

and
from

the

logic.

WRITE

CSR

(AMSC

obtained

force-command-accept

2.13.2.3

are

counter

the

machine

RD<2:0>

bits

state
the

asserted

state

SERIAL

what

CSR

data.

READ

AMRM

CSR

false).

WRITE

asserted

2-149

asserted

CSR

state

inform

during

AMSC READ

BMRM EN,

\ SERIAL _RD

p—

L_“/*

A CSR ST<1>
I,(HG.

222-

2-52)

FIGS.2-4,
2-13, 2-18,

BMRM

SERIAL BD<2:0>

(FIG.
2-34)

E A CLK |

061-¢

E B CLK

»1CEUNTER
CLR
A

AMRM CSR
PROBE_VALID ,,

CSR

STATE

BRCS

A _CSR
ST<1:0>

__EMPTY» MACHINE]

(FKlZfiZ%: B

MCL

A CSR

ST«<1:0>

___.CD&@M”E
AMRM

“C§:>MHXMUASB_

ANRM

DRIVE NEW DATA

2-28

P o (FIG.2-49)

ARCS FORCE
CMD AC

L»!

(FIG.Q-SZ){

FORCE
CMD
ACPT
LOGIC

FAKE

CMD
ACPT

BVRM

FAKE CMD_ACPT

B(FIG.2-17)

M—(F1G.2-23)

»| LOGIC

B VALID<2:0> [So

S5CLD-349

Figure

2-51

CSR Control

2.13.2.4
to
the
CMD

ARCS
MASC

ACPT.

FORCE
during

For

CSR

CMD ACPT -- A
CSR operations
reads,

ARCS

RCS FORCE CMD ACPT is asserted
to force the assertion of BMAS

FORCE

CMD

ACPT

asserts

every

read
bits.,
For
CSR
writes,
ARCS
FORCE CMD ACT asserts
fourth
c¢ycle (third count of BMRM SERIAL RD<2:0>) and then
the

eight

on the
resets

counter,

2.13.2.5 AMRM
MPR
all CSR operations

DATA
SEL -- AMRM MPR DATA SEL
(CSR states 1, 2, and 3). It is

where

MDB

routes

the

data

the

is asserted
sent to the

for
MDB

DFA.

2.13.2.6 BMRM
FAKE
CMD ACPT -- BMRM FAKE CMD ACPT is sent to the
MDBC
where
it asserts the MDB strobe to enable the CSR data from
the
MDB to the DFA, It is asserted in CSR state 1 when the MCL is
idle

array

boards

data

MCL

queued

2.13.3

IDLE

true),

(AMRM

the

and

DRIVE
RCS

read

NEW

queue

Read Command Bits

data

DATA

not

false),

buffer

(Figure

being

and

taken

from the

command

there

VALID<2:0>

all

false).

2-52)

2.13.3.1 AMRM READ CMD<K0> -- AMRM READ CMD<(0> specifies a longword
of read data as being the first longword of a command, or a "next"
longword. The cases of CSR reads and normal reads are considered.
®

For

CSR

states

read,
3

AMRM

READ

(A CSR ST<K1>

CMD<K0>

when

the

true)

asserted
CSR

longword

CSR
is

read.

For

normal

decoder

1is

read,

the

examined.

The

output

decoder

count

the

and asserts its output {(causing AMRM
assert) for longword 0. The decoder output
longwords

2.13.3.2 BRCS READ CMD<1>

and

longword

decodes

the

count

longword

READ CMD<O0>

negated

to
for

-- BRCS

READ CMD<1>

specifies

longword

of
read
data
as
being
for
the
MDP
(masked)
or for the DFA
(normal).
BRCS
READ CMDK1> is the AMSC MASK signal from the MSC,
that
has
been
routed
through the three-stage, queue-buffer and
then
inverted.
Consequently, read bit <1> is asserted for normal
reads
(AMSC
MASK
false) and negated for masked reads (AMSC MASK
true).

2.13.4

Board

Select/Enable

(Figure

2-52)

2.13.4.1 Board
Select
-ARCS
BD SEL<K2:0> is the command probe
number received from the MASC as BMAS BNUM<2:0> and routed through
the
queue
buffer. It is returned to the MASC as the board select
number.

2-151

(FIG.
2-49)

{ BMAS

* BNUM<2:0>

10<2:0>

MAR OCTA

——

|
XI

(F1G.2-6)
}

[Do———»{

DRIVE

ADFA UNJAM

DATA

¢S1-¢

|
|
I
I
|
|
X
—-\‘______,, — Al

(FIG.
2-34)

‘D

>
»

EMPTY

’# (FIG.2-34)

BMAS €MD ACPT

& (FIG.2-49)

\ BRCS

"'jlbme.'z-sn

NEW DATA

}(FIG.2-51)

—

B
MCL

LONGWORD | B NEW
PIPE

B TASK

ADFA TASK CMPT

BOFA HARBINGER

BMRM

? count
DECODER

DPJ—

A CSR

(Fi@.2-51)—>1<1>
.

P
ERABLE

BMSC PRE MASK DONE
=

(&)

DALA<1.0>

»|

2.23,

2-28,

2-34, 2-45)

NAB GATE

$—(FIGS.2-17,2-28)

2-5. 2-9.
READ CMD<0> ¢ frigs 2-34,2-48)
| 2-23,
BRCS

z |[EDSELENY

ARCS BD SEL EN

AMAR DATA RDY DONE<7:0>

MAR BNUM<2:0>

z [MASK CTR
(FIGS.2-23, 2-45)
ol
EMRM NEW LW X—(FIGS.2-5,
2-9,

FULL

CMPT

BMCL DRIVE

|
BvAM RESET - |

COUNTER | LW CNT<2:0>DD_E£> IDLE
A

BMDP TASK CMPT

(FIG.2-23)

(FiG.2-2)

2-50)

2-51)

AMRM_DRIVE

[

}—'(FIG.Z--ts)

E{Z}fifiiML____%?flHGQJM

(FIGS.2-50,

ADFA SLOW
MODE_EN

| (Fla

(FIG.2-49)

DOEBQi_EEA_Q____CMQslz__i

_’,_AM_MA%_’ QUEUE
BUFFER

2-34)

(FIG.2-5)

ARCS
BD SEL<230>

(FIG. { ;' BMSC LEN

(FIG.2-2)

*®

MAR BNUM<2:0>

(FIG.2-49)

scLp-32485
Figure

2-52

Array

Read

Control

—»

p. nAB

2.13.4.2

Board

board-select
for

the

which

board.

ARCS

the

number

compared

with

the

new

array

Enable

signals

where

MASC
a

Select

enable

the

probe

Board enable

logic generates

validate

board-select

signal

SEL

board

number

the

enables

being

read

the

board

comparator
(ARCS

accessed

two
the

SEL<2:0>)

for

command.

BRCS

SEL

enables

three-bit
board
board-select line
Three

signal

determine
®

areas

the
The

2.13.5

longword

count

DATA

RDY

array

board

has

BMSC

PRE

Read

the

current

the
MASC
into
an
selected array board.

yet

the
to

enabled

DONE<K7:0>

These

longword

counter

from

from
the

the

for

the

(Figure

see

board.

see

the

operation.

MSC

Signals

logic

are:

array

NAB

current

the

from

board-enable

should
be held enabled
write operation.

Data

DONE

the

converts

enabled.

come

completed

MASK

which

board

from

are

AMAR

decoder

monitored

hold

longwords

board
masked

code
from
enable the

are

period

select
used to

see

write

the

array

portion

2-52)

2.13.5.1 AMRM DRIVE NEW DATA -- AMRM DRIVE NEW DATA is asserted
the array board instructing it to place a longword of read data

to
on

the

NAB.

taken,

the

determine

LW CNT<2:0>),
these
FULL

and

a multiword

outputs

number

the

requested

from

BMRM

read

the

AMRM

octaword

transfer

more
MCL

longwords

informing

When

the

1longword

turn

asserts

clears

the

2.13.5.2
NAB
to
read

BMRM

feedback

BMRM
pass

portion

yet

counter
RESET

the

a masked

come

read

data

MCL

counter

LW CNT<2:0>)
AMRM

decremented,

that

1is

set

DRIVE

1longword

When

from the
(A

PIPE

new

enabled

for
NEW

the
DATA

read data
the

longword

counter

read

(B NEW LW CNT<2:0>) provides an
read transfer by specifying the

reaches
CTR

NAB GATE -- BMRM
to the DFA for a
of

come.

MASK

counter

longword

NEW

time

board.

(B NEW

(A MAR OCTA).

new

transferred.

each

array

data

count

DATA.

read

longword

NEW

data
1is
coming. The output count
indication
of
the
state
of the
number

read

can

DRIVE

has

the

count

counter

NEW

array board

monitors

executing,

three-bit

the

that

longwords

decrements
asserts

this

asserts

the

logic

indicate

board,

false),

When

and

sugnals

array

drive-new-data

write.

the

MSCl

MCL

IDLE

MSCl.

mask-store

NAB GATE enables
normal read, and
BMRM

2-153

NAB

asserts

BMRM

GATE

RESET

which

MASK

CTR

logic.

read data from the
to the MDB for the
asserted

there

Full/Empty

the

EMPTY

BRCS

memory

assertion
——————

®
®

system

BRCS

EMPTY

The

RCS

buffer

read

sl nYalkeal

boards
®

longwords

2.14

Power

EMPTY

NEW

UNIT

the

refresh
67

clock.

sensing
battery

The

are

three

clock

refresh
clock

loss

notifies
battery

array

data

supplied

Battery
minutes.

from

during

outage

the

power

that

The

from

the

array

obtained

from

the

have

been

accepted

false).

functions:

the

array

boards

for

refreshes.

oscillator

power,

block

allow

that

14.9

both

The

BBU

generates

the

microseconds.

places

the

memory

svstem

mode.

a power up,

state.

false).

requested

yet

period

During

all

battery-mode

power

2-53

MSC

true).

CMD ACPT

and

KHz

the

(BBU)

performs

refreshes

the

assert.

false).

commands

unit

refresh

Upon
into

data

(BMAS

internal-error

being

DATA

IDLE

read

asserted

is
three

currently

new

asserted
an

(B VALID<K2:0>

empty

DRIVE

contains

from

signal

boards

Supplies

FULL

that:

BACKUP

ARCS

requires

are

backup

and

send-no-command

return

There

(power

Figure

BRCS

read

normal

full

MCL

BATTERY

battery

true

all

buffer

becards

array

data queued in the RCS
VALID<2:0> latch bits. If

array

the

The

data

(AMRM

CMPT

the
MASC

2-52)

TASK

more).

Command

buffer

causes

(Figure

for

too

power
long

will

maintain

array

the
from

MCL
the

array

system whether

(battery

outage),
and

diagram of
BBU

the memory
mode

data

power

it
is

the

maintained
cold

start

lost¥*),

BBU.
system

data

BBU

V module.

2.13.6.2

ready

T
D

asserted,

where

MCL

N
ms

are

counter,

and

Status

FULL
=-looking at

MASC

longword

(]
8V

2.13.6.1 ARCS
monitored
by

the

processed

|._.l

RCS

data

-1-

2.13.6

1left

read

count

(preceding

A DELAYED
BDELAYED
[ ¢—POWER_DOWN| | o1 | ¢ POWER DOWN &«

BBU

T e
TO
ECL

(FIG.
2.50) <

_ _AMBM FORCE BATTERY

SET

DELAY
FF

B ECL RC

A ECL RC

FD“—*

CLR

TTL

FOWER OK 1 |a7 |@-POWER
OK e | 1o

SG1-¢

]

BATTERY

ECL

(FIG.2-34)

NMID>—

NML .DC LO )#

, [

B COLD

A COLD

TTL

(FIG.2-50) 4___P_OW.._EB_U_P_ LAT

MCL REF 2|2
%Dls

'OWER UP fi_._ T0 nil
ECL

(F1G.2-4)
<

NM>-NML BAT

MCL

SET

COL

flSTART

COLD
FF
CLR

(FIG.2-50)

CLEAR"BATTERY
:
+5V _BBU

|
)‘

REFRESH

086
_-%BE_E.QSQ_,, A
(67 KHZ)

SCLD-374

Figure

2-53

MCL

BBU

Block

Diagram

Power

Loss of

2.14.1

Figure 2-54 is a flow diagram of the BBU power-down seguence. When
system power is interrupted, NMI DC LO is asserted to the BBU. The
assertion of NMI DC LO does the following:

Asserts MCL DIS REF to the refresh logic in the array
boards where it disables normal refresh operations.

Removes the clear input from the BBU delay flip-flop.

Negates B ECL RC POWER OK to the MSC and the RCS.

the

Wwhen

senses

MSC

the

negation

ECL

RC POWER OK, i

initiates the power-down seguence by asserting AMRM FLUSH DAT
INT

AMRM

ERR.

When the RCS senses the negation of B ECL RC POWER OK, it checks
that all in-process writes are completed, all reads have been
aborted, and that all the array boards are not busy. It then
asserts AMRM FORCE BATTERY to the BBU which sets the delay
flip-flop. Setting the delay flip-flop asserts:
®

B DELAYED POWER DOWN back to the RCS.

MCL

BATTERY

ENABLE

the

refresh logic in the array

boards where it initiates battery-mode refreshes.

Battery-mode refreshes
power stays up. This is
power returns while the
from battery mode will

continue so long as the +5 V BBU battery
guaranteed to be at least ten minutes, If

BBU +5 V is still operational, a power up
occur. If the BBU +5 V is not operational

when power returns, a "cold start" power up will execute,
.1 4

Return of

Power

e 2-55 1is a flow diagram of the BBU power-up sequence. The
return of system power is indicated by the negation of NMI DC LO.
The power-up sequence varies according to whether the power up is
ig

A A

from battery mode or

is a cold start.

the power up is from battery mode, the BBU +5 V from the power
If
system was operational during the power loss and the memory system
is operating in battery mode. Here, the negation of NMI DC LO:
®

Negates B DELAYED POWER DOWN to the RCS.

Negates

MCL

BATTERY ENABLE to take the array boards out

Negates

MCL

DIS

Asserts

battery mode.

normal

REF

the

array boards may eXxecute

refreshes.

ECL

RC POWER OK to the RCS and MSC informing

them that system power is operational.
IX

2-156

4 NMI DC LO

\ 4

MCL DIS REF

vB ECL RC POWER OK

Removes clear from

Disables normal
refreshes in array
boards.

Indicates to RCS
and MSC that Blower
SC
is failing-

delay flip-flop.

asserts FLUSH DATA
and INT ERR to
start power-down
sequence.

In-process
writes

reads

are

completed,

aborted,

arrays

are

and

not

4 AMRM FORCE BATTERY
Sets

A MCL BATTERY
ENABLE

Places

array

delay

flip-flop.

B DELAYED POWER
DOWN

boards

into battery mode.

A&
+5V BBU
operational

YES

Memory
to

arrays

retain

refreshed

data.

When power returns,
memory will powerup
Array

data

from

lost.

battery

mode.

When power returns,
memory will execute

cold

start.

SCLD-375

Figure

2-54

Power

Down

Flow

Diagram

If
the
power
up
is
a
cold start, the BBU +5 V from the power
system
was
not
operational during the entire power loss and the
array data is lost. After the BBU +5 V becomes operational, NMI DC
LO
negates
which
will
assert
B
ECL
RC POWER OK and negate B
DELAYED
POWER
DOWN
just as in the case of power up from battery

2-157

Power

YES

Memory system is
in battery mode.

4 NMI DC LO

becomes

operational.

8G1-¢

B _DELAYED POWER

MCL DIS REF

+5V BBU

DOWNRCS.
¥ To

'flkogéhé\grr‘noaloccur
in array boards.
efr

MCL BATTERY

* ENABLE

nakesfarray boards

cr’n%tdeo battery

B8 ECL
FC‘JCK
4 POWER

To RCS and MSC.

1 NMI BAT DC LO
|

¢ NMI

v B DELAYED POWER
To

4 B COLD POWER
P

DC LO

(nform RCS of
cold-start
pperation.

t B ECL RC
POWER OK
To RCS and MSC.

f MCL BATTERY
ENABLE
input
parser and data
output control
in array boards.

4 MCL COLD START
Iinhibits

currents
memory

array

Initializes

arrays.

4 AMRM CLEAR BATTERY]
Power-up
completed.
}

RCS.

‘ 8 COLD POWER UP

¥ MCL COLD START

MCL‘power
operational.

gl errers

MCL BATTERY

ENABLE

Normal

operation.
SCLD-369

Figure

2-55

Power

Flow

Diagram

mode.

cold

start.
°

addition,
The

Assert

tlow

NMI

assertion
MCL

blocking

NMI

for

the

START

MCL

BATTERY

parser

and

When

system

BATTERY

and

MCL

power
the

BATTERY

BBU

COLD

the

POWER

boards

data

the

ENABLE

completed,

negates

resume

COLD

normal

2-159

inhibit

the

initialize

control

RCS

status,

which

already

enhances

data-output

the

lost

and
power-up

system.

ENABLE

the

this

will:

array

flow

input

cold-start

the

signifying

current
rest

Assert

Array

boards.
®

asserts

BAT

currents.

array

sequence
®

COLD

array

BAT

the

RCS

POWER

logic

the

informing

asserts

AMRM

UP,

operation.

MCL

COLD

the

array

the

CLEAR
START,

CHAPTER
FOUR MEGABYTE

3.1

VAX

There

are

between

the

number

MCL

MAR4

8800

lines

Signal

and
as

180

are

with

listed

degrees

out

receives

from

the

from which

the

MCL

One

exception

the

(the

read

and

3.1.2
Figure

listed

Table

see

and
B

read

are

one

first

the
bus

bus

select

signals
and

the

3-1.

The

and

(MCL

its

MAR4

ECL

are

signals

are

prefixed

DRIVE

NEW

DATA

MCL.

will

appear

CLK

clocks.

referenced

NAB

and

the

internal

with

signal
NAB

the

which

referenced

the

from

sooner

3.1.3).

NAB

edge

diagrams
signals

the

which

shown

phase

show

both

the

diagrams

phase

clock

longword

write

designation.

NAB
cycle

cycle
1line

BMCL

timing

The

rising

prefix

clock

data

Section

3-3

clock

all

the

clocks.
the

their

the

letter

the

that

phase

derives
from

MAR4

for

and

signals

the

3-2,

command/address

carry

NAB

the

asserted

select

Longword Write Timing
3-1
1illustrates
NAB

board

are

that
The

with

from

All

the

this

operation.

the

phase

bus

first.

data

referenced

according

prefixed

cycle;

3-1,

are

bus

each

free-running,

referenced

«clock

Figures
are

and

are

transfers

phase

MCL

signals

clock

NAB

boards.

phase.

MAR4

(MAR4)

on
the
NAB
bus are referenced to two clocks
A and phase B.
The clocks have a period of 45

IN)
the

the

MAR4

The

Consequently

BOARD

Clocks

data
phase

designated

the

associated

ARRAY

(NAB)

lines

and

signals

3.1.1

BUS

signal

MCL

Signals
and

ARRAY

166

MEMORY

signal

signals
(45

timing

used

for

the

command/address

write

operation

are

ns).

(command/address
for

for

the

desired

command/address
signals

are

3-1

cycle),

MAR4.

the
also

parity

referenced

MCL

bit.
to

asserts

the

The
A

the

board

clock.

Signal
MCL

ECL

CLK

Table

3-1

Bits

Direction

Function

MCL

Supplies

NAB

Signals

MAR4

for
AMCL

BRD

SEL<7:0>

MCL

MAR4

Selects
a

CMDK3:0>

AMCL

CMD<3>

MCL

MAR4

for

operation

Command

write
CMD<2>

clock

write).

write

Negates

AMCL

board

command

(read
AMCL

phase

MAR4.

bit.

specify

operation.

Command

octaword

Asserts

bit,.

specify

octaword

an
read

operation.
AMCL

CMDK1:0>

Command

starting

address.,

Specifies

MAR4

bank

for

For

read,

ADDRK25:4>

MCL

MAR4

read

bank
to

the

Specifies

the

return

MCL.

location

accessed

octaword

specifies

first

AMCL

the

accessed

longword

write.

data

within

the

array(s).
AMCL

CMD

ADDR

PAR

MCL

MAR4

Command/address

parity

bit.
AMCL

DATAK31:0>

MCL

MARA4

Write

AMCL

BAD

MCL

MAR4

Asserted

DATA

when

write

data

Asserted

when

write

data

written.

is
AMCL

AMCL

WRITE

DATA

ENABLE

PAR

MCL

MAR4

MAR¢4

data.

bad.

Parity

bit

MCL

ECL

One

per

MAR4

CLK

and

MCL

ECL

board.

3-2

the

and

for

data

and

write

bits.

for

data

CLK

write

the

bad

enable

Table

Signal
AMCL

3-1

Bits

READ

SELL7:0>

NAB

Signals

Direction

(Cont)
Function

MCL

MARA4

Selects
MAR4

and

transfer

the
BMCL

DRIVE

NEW

DATA

MCL

MAR4

REF

0OSC

MCL

MAR4

ENABLE

MCL

MAR4

data

Initiates

transfer
from

data

the

Refresh
MAR4

BATTERY

read

the

read

of
MAR4

MCL.

clock.

refresh

MCL

for

MCL.

bank
MCL

prepares

board

Initiates

cycles

the

boards.

Places

MAR4

into

battery

mode.
MCL

DIS

REF

MCL

MAR4

Inhibits

initiation

refresh

cycles

battery
MCL

COLD

START

MCL

MAR4

Disables
dur 1ng

BMAR

PAR

CMD

mode.

array

system

currents

power-up,

ADDR

ERR

MAR4

MCL

Command/address

parity

error.

MAR4

MCL

Signifies

that

commanded

operation

been

completed.

write,
selected
been

written,

read,

array

(have)

data

For

indicates

selected
has

For

indicates
array bank

been

the
has
a

the
has
a
the

bank(s)
read

available

and

the

MAR4,
+

One

MCL
all

per

MAR4

boa rd.

REF OSC H to four MAR4s
MAR4s

will

not

and MCL REF 0OSC

refreshing

3-3

L to other

simultaneously.

four so

Table
Signal
BMAR

3-1

NAB

Signals

Bits

Direction

MAR4

(Cont)
Function

SEND

CMD<7:0>

MCL

Inhibits

commands

from

MCL.

BMAR

DATA<K31:0>

MAR4

MCL

Read

data

(longword).

BMAR

DATA<K38:32>

MAR4

MCL

Read

data

(check

MAR4

MCL

Indicates

MAR

MEM

SIZE<23:00>

array

board

MAR MEM

One

Three

the

per

MAR4

per

second

longword,

the
on

the

bad

write

detects

will

bank.

parity

not

Consecutive

data-parity
the

megabytes

MCL

the

bit

places

bit,

and

the

data

the

data

from

referenced

the

from

indicating
but

command/address,

157.5

one-half

seen

the

writes

bit

with

are
the

ignals
cannot

Dbe

ns
MCL

parity

the

time

has

was

clock.

the

MAR4

completed

A
error

time

the

detected,
AnrAar~r+rn~nA

data-ready-done

Figure

same

the

3-1,

array

bit

will

the

issued

the

bank

minimum

negation

another

495

time

(11

command
period

bus

the

between

cycles).

banks of a MAR4 board can be made
MCL asserts four sets of board
signals in four succeeding bus
followed by its data cycle in which the
The
bit

bit,

asserted.
in

the

assert

four

other.
parity

signals

after
can

the

write-enable

Four

signal

one

sequence

following
to

any

one

command,

first

error

bit

from

NAB

enable

bit

and

the

with each bus cycle
data,
the
bad-data

command

error

one-half
bit,

one
right
after
the
select/command/address/

the

write

command/address

write

and

commands

cycles

asserted.

Sixty-seven

write

the

error

parity

eighty-two

write

parity

data-ready-done

data-ready-done
same

the

MAR4

follows:

Size

cycle),

the

bit,

command/address

operation,

still

data

(data

hundred

asserts

NAB,

command/address

Three

cycle

The

the

bus

the

MAR4

asserts

memory

board.

bit

board.

array

parity

size

bits).

sequences
displaced

sequence.
bank

bit,

will

until

one

However,
495

and

the

assert

bus

cycle

second

after

the

Phase

B Clock

Phase

A Clock

AMCL BRD SEL

AMCL CMD<3:0>

AMCL ADDR<25:4>

AR}

AMCL CMD ADDR PAR

|
]
|
1
]

AMCL DATA<31:0>

)

1
1
I

]
I

i
)
]

AMCL WRITE ENABLE

4
|
1

|
|

AMCL DATA PAR

BMAR DATA RDY DONE

|
|

4——157.5 NS-

‘

|
)

i
|

382.5 NS

BMAR CMD
ADDR PAR ERR

|
|
|

}

t
I

}

———

G-¢

AMCL BAD DATA

495

NS (Il

BUS CYCLES)

—»

SCLD-388

Figure

3-1

Longword

Write

Timing

Diagram

— 45 NS

E(Hglpigipipipinink
RN
1L jpEpNpEpE

Phase B Clock

{
1

...................... . . . . . . . . . . . . . | Y Y

A 4

SN RNIRERIN

[Ve] TM~

3I-X6

o w

P4 w

(42 TM

0 3

[42]

]
[+

(28] > o)

- 98] 43]

Minimum

Figure

3-2

SCLD-386

Longword

Read Timing

Diagram

w|_vvlLoyl..._F—_
2Boo T&§° go-©& z b“o >52 5e& &S M2m9 <R-LLL<<23 LI8o 22

Wv&m33@m§T£Ww|22mHcm“9 &Q2) y8&)1&£O&m2)
<

Figure
3-3
*

630 NS (14

Octaword
Read
Timing

T —IIIII

A ...

Z 2]

T r—

]e b ee

————

A Clock

Phase

B Clock

oOx| ol

> wuNloK iTZM~

~Nz "= 0 ZN]ol -.|..|..|..|..|..|..|..|..|..|..|..|.
A[ B - -

ui n,fi 1"1 1TT N.....

3-7 IX
Phase

BMAR DATA<38:32>

BUS CYCLES)*

675 NS*

Minimum
SCLD-387

Diagram

Longword Read Timing
3-2
1illustrates
NAB

3.1.3
Figure

signal

timing

for a

longword read

operation.

first

the

bus cycle

(command/address cycle),

the MCL asserts

1line for the desired MAR4. It also asserts the
select
board
the
bit. The board
parity
command/address
the
and
command/address
select and command/address signals are referenced to the A clock.
parity error in the command/address, it
a
detects
MAR4
the
If
asserts the command/address parity error bit 157.5 ns from time 0.
The command/address parity error bit is referenced to the B clock.
Two

SEND

hundred two and one-half ns from time

CMD.

to the MAR4 until

commands

read

§ the MAR4 asserts BMAR

BMAR SEND NO CMD prevents the MCL from issuing any
it has taken the read data.

BMAR SEND

CMD remains asserted until the MCL initiates a transfer of the
data.

Three
hundred
thirty-seven
and one-half ns from time 0 the MAR4
completed
has
it
indicating
bit
data-ready-done
the
asserts
The
and the read data is available.
Dban
selected
the
reading
detection
of
a
command/address
parity error has no effect on a
read
operation
in
the
MAR4. The operation executes in a normal
manner,

Sixty-seven
and one-half ns after the MCL senses the assertion of
the
data-ready-done
bit,
it
can
assert the MAR4's read-boardselect bit (AMCL READ BD SEL). The 67.5 ns is a minimum.
The MCL
can wait

longer

AMCIL.,
READ
BD
the
MCL.
The
receiving

AMCL

is busy with another array board.

SEL prepares the MAR4 to transfer the read data to
MAR4
negates
BMAR
SEND
NO
CMD
112.5 ns after
READ BD

SEL.

Twenty-two and one-half ns after the assertion of AMCL READ BD SEL
0), the MCL asserts BMCL DRIVE NEW DATA to
time
from
ns
(427.5
take
the
read
data from the MAR4.
The read data appears on the
NAB

One

one

bus

hundred

cycle

later.

twelve

and one-half

after

the

read data appears

the
NAB,
the
MCL
can
issue another command to the MAR4.
Five
hundred eighty-five ns (13 bus cycles) is the minimum time between
read
operations.
Unlike a write operation, consecutive longword
reads
cannot occur to the four banks. Once a command is issued to
read
a
MAR4 bank, the bank must be read and the data transferred
to the MCL before another command can be given to the MAR4.
Octaword Read Timing
3-3
illustrates
NAB
N

signal

timing for an cctawcrd

read

The

functioning

parity

bit,

error

and

the

identical
last
In

still
As

under

Section

soon

The

MCL

AMCL

the

630

SEL

can

READ

MAR4.

(14

NAB

This

case

line

negated

may

let

the

bus

1is

shown

DATA.

the

one

this

read

data

NAB.

Note
after

that
an

octaword

than

after

which
the
MAR4.

the

MAR4's

from

the

negates

the

the
a

During

MCL

(All

octaword

read

but

the

read.)

read-board-select

last

while

can

1issue

factor

1is

can

3-3.

can

occur

the

bank

the

read

the

data

and

between

read

the

NAB.)

assertions

The

MCL

BMCL

existing

re-asserts

issue
the

new

AMCL
of

BMAR

CMD and

respond

longword

read

required

3-9

read

for

the

BMAR

sooner
banks)
one

negation
to

know

read,

the
MCL

the

longword

read,

SEND

CMD by

the

MCL

detect

the

SEL

place

only

lines

octaword

READ

command.

negation

looks

read-board-select

command.

time

read-board-select
the

presently

(585

MCL

factor

time

the
on

pulse.

new command relatively
(630 ns to read four

overhead

extra

bus

appearing

drive-new-data

DATA

The

relative

another

reads

consecutive

banks

the

data

NEW

the

negation

operation

another

SEND

issue

octaword

operation

read

the

that

gating
of

can

four

each

data

DRIVE

issue

for

the

(Note

read

operation,

immediately

negation

MCL

between

DATA

from

following

BMCL

send-no-command

the

time

NEW

data

read

negates,

DRIVE

longword
a

SEL

minimum

case,

new

gating

applies

data

cycle

until

the

octaword

read.

holds

final

remain

read

cycles

will

when

data-ready-done

MCL

read

NAB

bank).

command/address

the

cycles)?*,

the

3.1.3

Figure

while
than

BMCL

the

NEW

for

the

for
a longword

actually

The

bus

assert

resulting

the

DRIVE

the

bit

bit,

bus.

seen

cycles

READ

the

command

read,

until

cycle,

send-no-command

functioning

octaword
AMCL

command/address

the

their

asserted

NAB.

the

read-board-select

paragraph

line

bit,

accounts

operation.

for

the

3.2

MAR4

OVERVIEW

Figure

3-4

figure

includes

function

functional

1s
the

areas

Clock
by

MAR4

board.

listed

The

logic

MAR4

board.

illustrates
the

MAR4

The

their

into

six

all

the

clocks

requires

-The
4MBARRAY
banks consist of four
with each bank providing one megabyte of
array bank contains thirty-nine 256K x 1

resulting in 256K 39-bit locations. A 39-bit
made up of a 32-bit data longword and seven
bits.

The

one

megabyte

provide

the

array

megabytes.

with

the

and

divides

supplies

four

the

256K

board
The

data

longword
L~

data

with

array

and

storage

total

banks

check

The

storage

use

bits

four

bank

banks

capacity

common

I/O

passing

path

through

Input

-The
1input
parser processes the input
and controls many of the board functions.

also

and

informs

performs

the

parity

MCL of

any

the

A
R

latches

parser

within

storage.

bi-directional

command/address

figure

equates

check

The

signals

board.

storage.

reC

diagram of

NAB

below:

clock

array

DRAM
chips
location
1is

the

A4MBARRAY
banks
identical* banks
data

block

—--

the

overall

all

banks.,.

check

parity

the

command/address

error.

ECC/DPARITY
-The
ECC/DPARITY logic generates partial
bits
on
the input write data. It also performs a
parity
check
on the input data and two data information
bits (bad data bit and write enable bit). It generates an
check

INT
bits

BAD DATA bit that is incorporated
outside the ECC/DPARITY logic.

into

the

ECC

Data-output
control
-- The data-output control
the read data flow out of the array board.

Refresh

arrays

the

The

refresh
when

logic performs

they

are

not

busy

controls

periodic
doing

check

refresh

read

The

six

functional

the
major
engineering

areas

are

shown

the

block

signals
that
connect
one
area
logic prints are grouped into the

write.

diagram

alcong

to
same

another.
The
six functional

with

areas.

Routing of two MAR4 signals (CLR REF REQ and MCL COLD START) is
not
identical
1in
all
four
banks.
This minor difference is
described in Section 3.3.2.7. For functional purposes the banks
can be considered identical.

3-10

LETHE

. _AMCL WAITE ENA

]

—

—1

AMCL DATA«<It
<1105

DATA
oA

INT OATACIO»

REAL
e
[

AV ADOR 254>

‘FIG.

anelARRAY RANKS

ADOH

_CLK SEleOs |

{‘
FtG

MR MM BIZEars

WAL MM ENES1.0r

WL ECLEBGXIN
)

“oox

cao suAr

11-¢€

..MO_DI8 REE
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e,

DONE <0

cueen

BANK

<«

BEL

MAR OMD ADDA FAR ERA

OQUTPUL

CONCROL)

INH l

)

CLK winT

o SR DATA FDY DONE
>

CLY: 3%

Cex
TARDR< 9y

|G~Lr HAD

OATA

» [ IREFRIBN)

/1Ll

S 7

[

ADDIT &S
"‘fl"‘V

[

l -

ALl

———

HEFREEH

CLM

<3 0»|8F1«3 0>

Conmmmny

: ¥l m[AN 3

Loao

E{D

K UM INH
Ci

ufl:;‘f}{l tct
.

. S—_—

LATCH

-G, D AR PAR .-EE" O ADOR PAIITY

AMCL BRD

<::> LATCH )

ADDR

3 A¥CL CMDS T

PCAB.0»

(INPUT
PARSER
AND DATA

h[fl

AljHLY

. B) 3

> ML M2

£CC/DPARITY

PAALTY

NDATA

A (MD<h

)

r—

—

84D

lmu

» KMBAHIWY BANKE)

]

‘DO

> Hoaate
= e
RB
=

e I

AESET
it
DIDY

AND REFREBHY

- AP ONC D‘M T‘ -

—

o (ARRAY BANK

- >

1w,

17)

V[mo:»

Pt I

b—t{m

—

ECt

]
—_————d
»-MoL

<+ »

1 g

]

»-——[—

x
StLa1

—_

—_——_—

r—

LATCH

2-8)

0ATA OUT
oar
I

S WRITE N

INPUT

12)

INT_CMD

ADDA_PAR tAR

ATA
PARSER (51G.3

BMG. DRIVE MW DAIA

)

AMCL ALAD B0 SEL

BMAR SEND
A
OV

5CLD 338

Figure

3-4

MAR4

Block

Diagram

Figures 3-5 and 3-6 are flow diagrams illustrating the three
command operations that can be executed by a MAR4 (longword write,
longword read, octaword read). Refer to the block diagram (Figure
3-4) and the flow diagrams (Figures 3-5 and 3-6) during the
following discussion.

Write Operation (Figures 3-4 and 3-5)

3.2.1

There are eight BMAR SEND NO CMD signal lines on the NAB with one
line connected to each array board. An array board will assert its
SEND NO
BMAR
command/address

CMD 1line
from the

when
MCL.

it
An

1is not able to accept a
array board cannot accept a

command/address when it 1is doing a read operation or a refresh.
When doing a write operation, BMAR SEND NO CMD is not asserted
because only the bank being written 1is busy. Another write could
be initiated to one of the other three banks.

Before sending a command/address to a MAR4, the MCL checks the
MAR4's BMAR SEND NO CMD line. If BMAR SEND NO CMD is false, the
MCL selects the MAR4 by asserting AMCL BRD SEL on the MAR4's board
line.

select

There are eight AMCL BRD SEL lines on the NAB with one line
connected to each array board. The MCL selects a board by
asserting AMCL BRD SEL on the select line connected to that board.

AMCL BRD SEL 1is clocked into a flip-flop to become INT BRD SEL.
INT BRD SEL is applied to the input parser where it enables a
bank-select decoder to process the input command.

The MCL also asserts a 4-bit command (AMCL CMD<3:0>), an address
(AMCL ADDR<25:4>), and a command/address parity bit (AMCL CMD ADDR
PAR) on the NAB. The command/address and its associated parity bit
are clocked into flip-flops to become CLK WRITE, CLK OCTA, CLK
STADDR<1:0>, CLK ADDR<K25:4>, and CLK CMD ADDR PAR., The CLK WRITE
and CLK OCTA bits of the input command specify the type of

operation to be performed (write, read, octaword read). The
command write bit (AMCL CMD<3>) is negated for a write operation.
Signal inversion results in CLK WRITE being asserted. The CLK
STADDR<1:0> bits (starting address) are a two-bit code specifying
the bank array to be accessed for the write. These signals are
applied to a parity checker in the input parser.

If the parity checker detects a command/address parity error, it
asserts INT CMD ADDR PAR ERR causing CLK CMD INH to assert to all
the array banks. CLK CMD INH inhibits the CAS (column address
strobe)

will

sequence

all

four banks. With no CAS sequence, data

not be written into an array. All other actions of the write

operation sequence will occur normally.

In addition to inhibiting the CAS sequence, a command/address
parity error will assert BMAR CMD ADDR PAR ERR back to the MCL
indicating that a command/address parity error has occurred. The
MCI. will abort the operation and assert a memory interrupt on the
NMI.

3-12

Starting
address
CLK STADDR<1:.0>
applied to Bank
Select Decoder in
Input Parser.
YES

4 CLK SEL<X>
Start RAS and CAS
sequence in
selected bank.

AMCL BRD SEL
This MAR4 is
selected.

INT

4 CLK WRITE
Place selected
bank into

write

BRD SEL

Enable Input Parser
to process input
command.

4 AMCL. CMD ADDR PAR

4INT DATA<31.0>

Command/address
received from MCL.

Negated state of DR
WRT DATA DIS gates
write data to array
banks, and to
parity checker and

Command/address
becomes:

CLK
CLK
CLK
CLK
CLK

ECC generator in
in ECC/DPARITY
logic.

WRITE
OCTA
STADDR«<1:0>
ADDR<«25:4>
CMD ADDR PAR

The following
data
information
bits
applied to MAR4:
- AMCL WRITE ENABLE
- AMCL BAD DATA
- AMCL DATA PARITY

Data information
bits inverted to
become:
-CLK WRITE INHIBIT
-CLK GOCD DATA
-CLK

DATA PARITY

Input Parser checks
command/address
arity.

CLK
WRITE INHIBIT

—

4 BMAR_CMD ADDR
PAR ERR

MCL notified of

command/address

parity error.

4 CLK CMD INH
inhibit CAE

written

PAR ERR

CMD ADDR

v
4 INT

4 WRITE INHIBIT

YES

army

»d

Command/address

4 AMCI. ADDR<25:4>

¢1-¢€

4 AMCL DATA<31:0>

4 AMCL. CMD<3:0>

mode.

se&uence.
No data
ivgll | abe written

SCLD-389

Figure

3-5

Write

Flow

Diagram

(Sheet

CAS

sequence

.Y.Es

inhibited
CLK

oo¥

GOCD DATA

* BAD DATA

YES

4 PCB<8:0>

partial

P1-¢

check bits on
INT DATA<31:0>.

Parity check on
INT DATA<31:0>

and on CLK WRITE
INHIBIT and CLK
GQOOD DATA bits.

DATA\

PARITY EIW

YES

Lon%worg and

bank
s ected
address
ADDR«<25:4>.

|PP

t INT BAD DATA

ECC generator

generates

(Ili

[ t DRDY DONE<X> I

I 4 RESET F109<X> I

[ + BWR DATA RDY

4 ARRAY NOT BUSY
Time

YES
for a
retry

[ % INT BAD DATA

* REF REQ

I
.

4 REFRESH

Perform a rsfrash .

{NT BAD DATA
bit incorporated
into ECC check
bits.

on all bank

* BMAR SEND NO
COMMAND

[ % CLR REF REQ |

A4
4 INTR DATA<38:32>

Final check bits
coupled to array

banks.

4 LOAD DATA<X>

Longword INT DATA
<31:0> and check
bits INTR DATA
<38:32> loaded
into selected bank

+Ras{o

]

v
¢ BMAR SEND NO
COMMAND

=)
SCLD-390

Figure

3-5

Write

Flow Diagram

(Sheet

2 of

Starting address
CLK STADDR<1:0>

4 AMCL BRD SEL
i

applied

-ggiséc'f@?‘ 'S
H

Select

Bank

Decoder

lput Parser.

4 INT BRD SEL
Enable Input Parser
and Data Output
Control to process
input command.

4 AMCL CMD<3:0>

AMCL ADDR<25:4>

$ CLK SEL<X>

AMCL CMD ADDR PAR

Start RAS and
sequence (n

Command/address
received from MCL.

Array

¢1-t

Command/address
becom

CLK STADDR<1:0>

CLK ADDR<25:4>

CLK €MD ADDR PAR

Start RAS and CAS
sequence in all

read

banks.

Arrays

I%g[axtstor:gnm
bi-directional

banks.
Data stored
in bi-directional

latch.

latches.

RESET F109<X>

o
mand/address "
parmy.

read

all

DRDY DONE<X>

pRDY DONE<3:0>

¥ DONE
BMAR DATA FDY

3 DONE
BMAR DATA FDY

avhilBe PR Bicy.

Read
S

?(#
b

R(la-'ad

? MCL.

Command/address
Parity erro

&
4 RESET F109<3:05

datablnk

4 BMAR
BMAR_CMD
ADDR
M

A ARRAY

NOT

BUSY

MCL notified of
command/address
parity error.

[

4 CLK SEL<3:0>
CAS

selected bank.
+

_YES

YES
e

A refresh of all
four banks will
occur it
it
is

time

for

refresh.

SCLD-346

Figure

3-6

Read

Flow

Diagram

(Sheet

4 BMCL DRIVE NEW
DATA

Y
%

DATA OUT CLK

DATA«<31:0> and
check blts INTR
clocked
DATA325

slate.

Y
$ GOT READ

Flip- Hops and
taced on NAB as
MAFL DATA<31:0>
ATA<38:325]
and
respeciively.

{

Load Read Bank
Shift Re |ster
starling

addr SS

C K

STADDR<1:0>.

4 READ BANK EN<X>
A}

L)
e

ched

dala in

Latched data in
next bank output
trom bank as INT
DATA<31:0> and
INTR<38:32>.

Isolate internal
bus from Write
Dala Flip-tlops

YES

DLY READ IN
PROGRESS

]

Y
4 READ BANK EN<X>

into

t DATA OUT CLK

with

Increment Read
Bank Shift
Register.

Data Ion%word INT

Fourth

longwcrd

CLK WRITE
in negated

clocked

out to
NAB

BMAR SEND

YES

NO COMMAND
v

fitrs

¥ AMCL READ BD

SEL

v
.

Refresh

progress

Complete refresh.

4 READ SELECT
Enable output of

CLR REF REQ

]

[ v

REF REQ

FlipRead Data
flops 1o NAB.

vBMAR SEND NO
COMMAND

v BMAR SEND NO

]

)

SCLD-347

Figure

3-6

Read

Flow

Diagram

(Sheet

Note

that

the

selection,

command/address

All

array

boards

command/addresses

placed

array

number

ERR

slot

1line

(slot

the

command/address
NAB

NAB.
of

command/address.

on
0)

the

check

NAB make

the

Hence,

parity

regardless

parity
on

NAB.

independent
a

However,

connected

the

board

checking

array

for

which

array

follows

from

all

the

only

BMAR

check

1is

that

board
of

the

all

first

CMD ADDR

slot

selected

slot

must

four

array

that

PAR

does

command/addresses

board
this

parity

the

for

the

always

used.

Address

CLK

address

specifies

ADDR<K25:4>

the

applied

1location

1in

the

banks.
1is

The

accessed®*,
Starting
decoder

address
the

CLK

strobing

Command

input

STADDRK1:0>
parser.

sequence

bit

CLK

the

write

mode.

the

selected

bank

will

WRITE

not

applied

its

decoder

asserts

the
CLK

bank-select
SEL<KX>

execute,

true

CLK WRITE
has

The

1is

where
X is the number of the selected bank. CLK SELKX> initiates the RAS
and
CAS strobing sequence in the bank. The strobing sequence will
access
the bank array at the address specified by CLK ADDR<K25:4>,.
As
noted earlier, if a command/address parity error occurred, the

CAS

1in

and

places

applied

strobing

the
all

sequence

selected
four

bank

into

but

only

banks

enabled.

The
MCL
places
the write data (AMCL DATA<31:0>), a write enable
signal (AMCL WRITE ENABLE), a bad data signal (AMCL BAD DATA), and
a data parity bit (AMCL DATA PARITY) on the NAB.
The
write
outputs
of
by

the

data
the

negated

DATA<31:0>.
latches

data

the

1in

parity

AMCL.

WRITE

AMCL

four

banks,

ENABLE

array

write
some

the

true

and

1.4.3).

When

write

data

inverted

false

(write

data

ECC

become

generator

INT

data
and

to be written

write
four

CLK WRITE

not

because

the

INHIBIT.

are

write

written),

into

there

operation

longwords

masked with

become
is

data

than

they

bi-directional

necessary

octaword

less

where

The
bus

logic.

the write
signal

longwords

DIS

applied

ECC/DPARITY

enable

unwanted

ENABLE

DATA

all

the

WRITE

DR WRT

1is

(Section

written,
signal.

DATA<31:0>

when

written

state

INT

checker

MAR4.

times

bits are clocked into write-data flip-flops.
flip-flops are enabled onto the MAR4 internal

not

be
enable

AMCL

CLK WRITE

INHIBIT
will
be
true.
CLK
WRITE
INHIBIT
1is
applied
to the
ECC/DPARITY logic where it asserts WRITE INHIBIT. WRITE INHIBIT is
applied

the

input

parser

The

4MBARRAY banks

the

address

(CLK

where

do not use the

ADDR<25:22>).

asserts

CMD

INH.

four most significant

(See

3-17

CLK

Section

3.3.2.3.)

CLK

CMD

bits of

INH

1is

applied

sequence

from

being

AMCL

BAD

DATA

oOr

can

analyzed

AMCL

BAD

DATA

1is

CLK

GOOD

state

later

DATA

DATA
CLK

1is

GOOD

that

external

DATA

the

checker

1input

error

asserts

The

INT

(outside

the

incorporated

final

Section

from

The

bank

CAS
data

The

<check

bits

processing

check

bits

LOAD

DATA<KX>

exist

the

(DLY

enable

3.3.2.2

under

BAD

false.
negated
asserts

ECC

generator

parity

where
check

the

being

BAD

INT

data

checked

data

bits.

which

ECC

BAD

input

the

turn

generator

INT

the

generated.

(INTR

one

DATA).

are

ECC

bits

for

bad

asserts

applied

and

inverted

applied

the

(PCB<6:0>)

(DATA

DATA

The

logic

bit

DATA<38:32>).
data

from

the

inputs,

BAD

DATA

which

bit

the

(see

the

bad

are

with

and

input

sequence

they

applied

enables

data
the

sense,

final.

the

selected

that
All

is,

seven

state.

longword

DATAKX>)

the

<check

true),

along

decoder

the

a preliminary
before

LOAD

4MBARRAY

pass

are

banks

bank-select

"partial”

only

array

strobing

ERROR

DATA<38:32>)

bank

done

PARITY

both,

four

CAS

partial

the

AMCL

The

data

ERROR

error

the

and

DATA

PARITY

asserted

state

selected

are

BAD

write

and

(INTR

RAS

logic.

PARITY

DATA

true),

bits

enables

signal
to

parity

asserted

parity
that

of the check bits may show the data as
being true) but it will not catagorize

DATA

1latches

The

Section

(BAD

array+.

decoder

the

Here

unique

BAD

DATA.

DATA

logic.

bits

are

INT

reflect

check

latch

delayed

the

DATA will

assert,

enable

applied

bits

With

being
MCL

DATA<KX>
data

are

AMCL

DATA<31:0>)
check

An analysis
BAD DATA as

final

the

write

logic.

already

final

bits

the

not

1logic)

bi-directional
write data.
LOAD

the

written

GOOD

portion

PARITY

generate

2.8.2).
(INT

error

write

ECC/DPARITY

bad

the

inhibits

detected

GOOD

DATA

(if

check

bit

bits.
CLK

the

(INT

derived.

data

parity

has

ECC/DPARITY

DATA

<check

being

the

enable

bits

generated

are

applied

CLK

DATA

ECC/DPARITY

partial*

<check

they

the

data

seven

partial

The

the

BAD

data

become

1is

and

causes

detected,

BAD

write

where

preventing

diagnostics.

applied

PARITY.

data

maintenance

bad),

write

DATA

bad

the

PARITY

and

CLK

parity

where

MCL when
The

data

DATA

which

become

banks

thereby

the

data.

1inverted

DATA

data

(write

BAD

bad

array

write

INT

AMCL

the

asserted

missing

true

all

selected

written.

error
be

the

bits

Banks).

3-18

pass

issued
to

pass

by
to

the

the
the

array.

bank-select
array

(see

bank

will

(due

inhibit
data

not

input

into

array,

parser.

CAS

into

selected

the

data

the

written

the

into

the

command/address

signal),

After

write
a

writes

DRDY

DONE<X>

asserts

the

NAB.

There

one

line

connected

commanded
RESET

with
NOT

for

ARRAY

all

this

NOT

refresh

F109

1is

from

the

asserts

REF

NAB

REFRESH

the

refresh

cycle

1is

logic

the

cycle

then

banks

the

BMAR

another

3.2.2
In

SEND

command

Read

many

NO
to

Operation

respects,

operation.

Before
MAR4's

false,

the

MCL

MAR4's

board

applied

the

input

enables

the

logic

MCL

command/address
ADDR

PAR.

These

input

parser.

asserted

error

command/address

OCTA,

normal

has
read

the

BMAR

are

hence

BMAR

REFRESH

REQ

only

one

the

out

operation.

write

the

MCL
is

AMCL

BRD

SEL

the

INT

BRD

SEL

and

where

becomes
command.

NAB.

the

The

address,

WRITE

CLK

parity

detected,

indicating

that

notifying

occurred,

1is

(false

ADDR<25:4>,

control

and

command/address

CLK

3-19

MAR4,

asserting

" operation where the array CAS sequence

CMD

SEL

This

send

input

has

SEND

After

error

bank

refresh

allowed

data-output

error

the

COMMAND.

BMAR

applied

MCL

the

become

the

SEND

When

that

for

3-6)
starts

command,

are

ARRAY
true,)

time

REF

SEND

ANDed

indicate

banks.

CLR

MCL

assert

banks.

completion

line.

STADDR<1:0>,

occurred.

parity

array

the

parity
to

and

BRD

the

bit

CLK

REQ

CMD

and

signals

back

AMCL

operation

asserts

array

asserts

the

3-4

4-bit

bit

command/address
is

parity
do

the

deems

turn

four
1

MAR4

process

parity

CLK

the

parser

parity

all

arrays

logic

command/address

SEND

line.

asserts

operation),

selects

select

command/address

ERR

BMAR

bits

assertion

where

other

operation

sending

the

negated,

read

the

the
RDY DONE
lines on the

board.

(Figures

checks

The

MAR4

and

check

write

banks

simultaneously

1logic

COMMAND

the

The

logic

which

REF

cycle.

With

DONE

the

true
write

DATA

RDY

refresh

bank

refresh

BMAR

parser

the

all

negates

refresh

F109<X>

board.

three

refresh

REQ

finished,

which

array

notify

and

RESET

that

input

from

MCL

other

signals

DATA

INH

asserted

inhibited

bits

MAR4's

array

the

cycle,

and

CMD

completed.

the

applied

BMAR
the

free.

the

need

applied

RESET

been

data

the

each

are

COMMAND

refresh

eight
to

DONE<X>

banks

initiates
refresh

has

signals

BUSY

are

indicates

MAR4

1is

F109
(The

the

All

DONE

F109<X>

RESET
BUSY.

RDY

CLK

sequence

the

DRDY

with

array.

asserts

line

DATA

error

NAB
BMAR

array.

strobing

the

bank

the

parity

the

for

and

the

and the
a

read

CLK

CMD

the

checker

BMAR
a

CMD ADDR PAR
command/address

the

MCL

that

MAR4

continues

contrast

inhibited.

write

As
discussed
under
Section
3.2.1 (Write Operation), only array
slot
number
1
1is connected to the BMAR CMD ADDR PAR ERR line on
the NAB. Hence, the array board in slot 1 does the command/address
parity
check
for
all command/addresses on the NAB regardless of
which
array board is selected for the command/address. It follows
from this that slot 1 must always be used.
Address
address

CLK
ADDRK25:4>
specifies
the

1is
applied to the four array banks. The
1location
in
the
array
that
1is
to be

accessed*,

Starting
address
CLK
STADDRK1:0> and octa-read bit CLK OCTA are
applied
to
the
bank-select
decoder in the input parser. If CLK
OCTA is false (longword read), the bank-select decoder outputs CLK
SEL<KX>
where
X
1is
the
number of the selected bank. CLK SELX>
initiates
the RAS and CAS strobing sequence in the selected bank.
With
CLK
WRITE
false, the selected bank is placed into the read
mode.
The
strobing
sequence
functions to read the array at the
address
specified
by
CLK
ADDR<K25:4>
and place the data into a
bi-directional latch in the bank. The array bank then asserts DRDY
DONE<X> and RESET F109<X> indicating that the array has been read.

DRDY
DONE<X>
1s applied to the input parser where it asserts the
MAR4's
BMAR
DATA RDY DONE line on the NAB. The assertion of BMAR
DATA RDY DONE informs the MCL that the array has been read and the
read

data

1is

available.

RESET
F109<X>
1is
applied
to
the input parser where it asserts
ARRAY
NOT
BUSY to the refresh logic. ARRAY NOT BUSY indicates to
the
refresh
logic
that the arrays are free and a refresh can be
executed

one

1is

needed.

If
CLK
outputs

OCTA
1is
true
(octaword
read), the bank-select decoder
CLK
SEL<3:0>
to
all
four
array
banks.
CLK SEL<3:0>
initiates
the
RAS
and CAS strobing sequence in all of the array
banks.
With
CLK WRITE false, the four banks are read at the CLK
ADDR<25:4>
address
and
the
data
placed
into
the
banks!

bi-directional
directional
DONE signals

DRDY

latches.

After placing the read data into the bi-

1latches,
each
bank
asserts
indicating that its array has

DONE signal

from any bank

asserts

its RESET F109
been read.
the MAR's

and

DRDY

BMAR DATA RDY

DONE
1line on the NAB. The assertion of BMAR DATA RDY DONE informs
the
MCL
that the array banks have been read and the read data is

available.

The
RESET F109 signals are applied to the input parser where they
are ANDed tc assert ARRAY NOT BUSY to the refresh logic. ARRAY NOT
USY indicates to the
refresh logic that the arrays are free and a
refresh

can be

executed

one

needed.

The
4MBARRAY banks do not use the four most significant bits of
the address (CLK ADDR<25:22>). (See Section 3.3.2.3.)

3-20

The

data-output

normally

and

MAR4

the

which

control
the

board

turn

CLK

clocks

the

CLK

STADDRK1:0>.

Bank

the

read

selected

from

the

WRT

DATA

read

MCL,
READ

read

data.

and

true),

DR WRT

GOT

DATA
in

where

longword

READ

DIS.

and

the

DIS

also

MCL
the

selected

read

the

applied

couples

the

data

longword

1latch

the

internal

There

After

are

eight

bus

from

AMCL

asserting

AMCL

READ

SEL

MAR4

for

Placing
mode

Taking

DATA

path

bus

the

driven

The

MCL

from

the

MCL

the
CLK

DIS

BMAR

the

bits

INT

write-data

only

BMAR
in

the

refresh

SEND

COMMAND

the

SEL

lines

RDY
it

which

assertion

The

DATA

prepare

MAR4

the

BMAR

the

until

DATA

RDY

DONE,

ready.
one

MAR4

board

where

the

data-output

shift

the

take

with

data

MCL must

the

connected

read

asserts

transfer

NAB,

selects

line

DONE,

SEL whenever

MCL

the

SELECT

(via

read

asserts

clocks
from

line

it.

control

by:

out

enable

the

into

the

"shift"

READ

the

output

the

NAB.

SELECT)

making

the

READ

COMMAND

(via

new

command

the

assertion

internal

AMCL

SEND

issue

board

thereby

BMAR

data-output

DATA<38:32>

flip-flops

the

then

MAR4

PROGRESS

commands

READ

read-bank

function

Negating

takes

the

transfer

control

WRT

the

and

applied
the

READ

read-data

check

operation.

Asserting

board.

SEL

the

new

MAR4

AMCL

READ

array

the

any

assert.

requirement

sensing

assert

each

READ

state

the

time

prepares

DLY

COMMAND

true

select

bank

respectively,

sending

free

first

and

internal

the

bank.

data.

SEL

data.

from
read

address

causes

EN<X>

asserts

SEND

DATA OUT

BANK

that

false

asserts

starting

decoded

which

WRITE

READ

1isolates

connected

SEL

read.

DIS

sensing
BD

read

MCL

There

OUT

CLK

EN<X>

DATA<38:32>

ensure

the

The

AMCL

BANK

octaword

BMAR

takes

AMCL

the

BRD

thereby

INTR

causing

MCL

the

shift
With

outputs,

inhibits
the

READ

bi-directional

DATA

WRT

logic

OUT

read-bank
operation.

STADDR<K1:0>

where

and

flip-flops
array

DATA

(INT

CLK

bank

DATA<31:0>
DR

asserts
shift

bank

mode

selected

output
in

contains

"load"

bus-to-NAB

data

SEL.
READ

the

SELECT)

MAR4

board

allow

after

data.

BMCL

DRIVE

the

control

NAB.
where

NEW

DATA

BMCL
it

to
DRIVE

asserts

data

longword

INT

DATA<31:0>

the

internal

bus

into

3-21

the

clock

NEW

the read data
DATA is applied

DATA

OUT

and

check

read-data

CLK.
bits

DATA
INTR

flip-flops.

The

flip-flops

output

BMAR

DATA<K38:32>

respectively.

DATA

OUT

shift

read

CLK

mode)

also

the

bank

1is

SEL

progress,

the

any

new

refresh

completed,

logic

which

array

The
new

command

octaread

NEW

DRIVE

NEW

off

the

internal

longword

DATA

READ
bank

and

check

DATA<38:32>

(READ

will

is
to

being

negates

the

read

CMD

CLR

from

board

REQ

and

MCL.

receive

the

refresh

the

refresh

BMAR
CaLasN

SEND NO

then

AMCL
is

the

cannot

When

COMMAND allows

the

MCL will

second

longword

DATA

OUT

which

the
bus;

that

clocked

are

the

CLK

read-data

internal

cycle

REF

REQ

the

READ

negate

MCL

coupled

NAB

the

BMAR

the

clocks

read

into

re-assert
MAR4,

the

data

flip-flops.

the

hence,

from

data

the

The

from

second

the
data

flip-flops.

DATA<K31:0>

The

and

BMAR

that

true).
the read-bank shift register
the
next
array bank.
The
array banks have been read.

SEL

de-select

the

process
The

MCL

and

end

BMAR

SEND

the

MAR4.

MAR4

board

before

operation.

refresh
negated

3.3
Detailed

AMCL

(used

refresh

command

executed,

has

still

and

(now

increment

MCL will

MAR4

REF

EN<KX>

SELECT

the

completed.

BANK

the

into

appear

DATA<31:0>

board.

take

DATA OUT CLK again increments
READ
BANK
EN<KX>
points
to
repeats itself until all four
then

the

SEND

re-asserts
bus

shift

new

assert

MAR4

BMAR

output

negate
BMAR

operation).

refresh

the

bits

outputs

read

progress,

DATA

EN<KX>

operation,

NAB

operation.

turn
LTI N Y 2 S

operation

BMCL

flip-flop

bank

DRIVE

array

the

BMCL

negation

incremented

ready

until

will

issue
an

cycle

read
its

the

read-bank

BANK

octaword

longword
is

the

READ

complete

commands

COMMAND.

MAR4

data

clocks

causing

this

READ

the

and

progress,
the

MAR4

DETAILED
descriptions

MCL

can

must

issue

complete
a

new

command

DESCRIPTIONS

are

given

the

six

functional

areas

defined
1in Section 3.2. The descriptions are confined to the area
being
described.
Therefore,
it is important that the reader has
read
and
wunderstands
the
MAR4 overview given 1in Section 3.2 in
order

the

understand

overall

how

operation

the

signals

the

functional

areas

relate

MAR4.

A block diagram is provided for each functional area showing input
and
output
signals.
These
signals are tied to the other block
diagrams by reference figure numbers.
An exception to this 1is the
Clock
Logic
Block Diagram where the clock destinations are given
but
not
figure
numbers.
This 1s because timing clocks are not
included in the detailed description block diagrams.

3-22

3.3.1

Clock

Refer

(Clock

Timing

The
B

clock
clock

other

receives

(MCL

ECL

The

listed

MCL

of
MCL

CLK

LATCH

ECL

SEL

LATCH

DRDY

SNC

CLK*

TTL

CLK

BM,

CLK

can

TTL

sets

CLK

clocks
in

BUS

ECL

CLK

later

the

and
are

this

clock
B

CLK

with
IN

Six

distributed

the

data-output

section

CLK

1IN

delayed

asserting

ECL

SEL

LATCH.

MCL

the

MCL.

The

ECL

CLK

and

results
and

positive

sent

then

asserts

the

delay

reset

DRDY

with

its

clock

and

with

DRDY

SNC

CLK

the

that

its

All

six

clocks

input

clock

1is

the

voltage

the

wused

SNC

CLK

edge

and

Eighteen

ECL

SEL

CLK

used

edge

This

then

sets

later

TTL

CLK

results

essentially

asymmetrical

the

waveshape

SEL

Latch

flip-flop

LATCH

clock delayed 24 ns
and with an asymmetrical

supply

data-output
set

DRDY

clock

which

This

delayed

phase

being

for

clock

phases).

edge

SNC

data-output

control.

3-23

back

DRDY

respect

3.1.1

DRDY

where

fed

with

waveshape

MAR4

flip-flop.

results

the

control
SNC

closer

leading

the

asserting

reset.

leading

with

ns.

asymmetrical

Section
of

an
F

flip-flop.

leading
an

ECL

flip-flop

the

but

ns.

Generated

phase

bus.

generated

identical

flip-flop

(see

NAB

are

described.

are

latch

the

and

HIGH

developed

discussed

and

LATCH

MCL

ECL

delay

via

IN.

code

the

1is

TTL

This
respect
to

clock

ECL

3-8

CLK

reset.

clocks

ECL

waveshape

MCL

clock

BUS

flip-flop

with

from

other

CLK

TTL
ns

MCL

the

below.

with

non-single-stepped,

from

Five

Twenty-three

phase

running,

sixth

CLK

ECL

LATCH.

Figure

IN)

the

TTL

and

discussion.

free

board.

the

Diagram)

following

MAR4
sixth

Block

the

CLK

while

TTL

CLK,

ECL

derived

ECL

Logic

are

the

logic

relationship

MCL

({(Clock

throughout

logic

throughout
control.

3-7

Diagram)

clocks

clock

are

Logic

Figure

and

clock

This

CLK

with

memory

The

delayed

flip-flop

through

SNC

CLK

the

size

clock

phase

ns.

than

phase

due

the

respect

DATA OUTPUT CONTROL

—+Y pf5

DRDY SNC CLK

.
)P,

L—(
MCL ECL

AND REFRESH)

—»>(__20 NS

9 NS

» (DATA OUTPUT CONTROL)

ECL CLK

(NAB)y—E B CLK IN I

(INPUT PARSER

—» (INPUT PARSER, REFRESH,

> TTL CLK EM

AND 4MBARRAY BANKS)

TTL GLK BUS |

L—» (MAR4 LOGIC,

DATA OUTPUT CONTROL,
INPUT PARSER, AND
ECC/DPARITY)

|-[TL CLK LATCH

—2V p 5o
LATCH
FF

pic

—+V

> (INPUT PARSER)

CLR

SEL
LATgH

ECL SEL LATCH
—

—»(

)—[—mm

24 NS

|—>( 18 NS
*Y__ECL HIGH
*

3 (MAR4 LOGIC
*)

MAR4 logic refers to miscellaneous logic not
(See Figure 3-4.)
part of a functional area.
SCLD-385

Figure

Clock

3-7

Logic Block

Diagram

Hence DRDY SNC CLK is used to clock all data going
phase B clock.
The
clock).
phase A
the
on
MCL operates
(the
MCL
the
to
MAR4-to-MCL signals clocked by DRDY SNC CLK are:

°®

data-output control -- DATA OUT CLK is generated
the
In
by the DRDY SNC CLK circuit and is in phase with DRDY SNC

DATA OUT CLK clocks the read-data flip-flops which
CLK.
the data longword (BMAR DATA<31:0>) and check bits
place
(BMAR DATA<K38:32:)

input

the

RDY

DONE

the

refresh

the

NAB.

parser -- BMAR CMD ADDR PAR ERR BMAR DATA

logic

-- BMAR SEND NO CMD

3-24

]

§g—— 45 N5 ———Pp}
\

MCL ECL

F B CLK IN _J

]

G¢-t

(&1 sNSPY

TTL CLK BUS_!-L

—

1
l

[

TTL CLK LATCH__!"‘ 23 NS—|

ECL SEL LATCH E"“z“ Ns—m 27 NS —pf

r—L

|
DROY SNC CLk M 20 ns P ons f— 36 ns —pf
*

Generated

Data

OQOutput

the

Control

Figure

3-8

Clock

Timing

Diagram

—
—

Figure
Table

3-7
3-2

identifies

lists

Table
Functional

the

3-2

the

destinations

Clock

all

the

clock

signals.

area.

Distribution

Area

Clock(s)

Received

MAR4 légic *

TTL CLK BUS
ECL

HIGH

4MBARRAY

TTL

CLK

Input

functional

banks

parser

TTL

CLK

TTI,

CLLK

RUS

ECL

SEL

LATCH

TTL CLk LATCH
DRDY

Data-output

control

SNC

CLK

ECL

CLK

TTL

CLK

BUS

ECC/DPARITY

TTL

CLK

BUS

Refresh

TTL

CLK

DRDY

MAR4

1logic

not

part

Figure

refers

differences

the

banks

START

and

COLD

described

Section

Only
one
bank
equally
to
the

between

MCL

3.3.2.1

(See

voltage.

signals:

bank

logic

area.

3-4.)

positive

array

CLK

to miscellaneous

functional

3.3.2
4MBARRAY Banks
The
4MBARRAY
Banks
consist

SNC

bank

four

almost

identical

are

minor

and

CLR

REF

(bank
other

Bank

array
8409

Two

two

differences

are

0)
1is
described. The description
three banks.
Figure 3-9 is a block

applies
diagram

Array

The

only

3.3.2.7.

Components

-- The major

are:
The

REQ.

banks.

involve

DRAMs

DRAM

controller

bi-directional

bank

shift

I/0

latches

manager

3-26

components

array

cHK BIT

LATCH

ouT)

e ""—'GTOQJAM&

p————
L BCAD ENAMLE ¢
_w

DATA

{Fle.

-14)

DATA<3Y
0>

LATCH
{ouT)

LoH
INT

S—

DATA<31:0>

DATA

\‘

INTR
DATA<38:32>

" J_L’:) i
OAD DATASE:
a J:“)\‘L-—fi DA WAT DATA DIS
.
>T oLv 1ofD baTame

).IQ_EM_EJABJ_D_L&L.
cux aDDR<z 100

,_{DDMde

LCH

DATA<38132>

m'ogt'vm.mn

LAT

RAM

fre A
.
(1n

(To array banks
1.2, and 3)

(F19:3°4)Q,

<31:10>

(IN}

—P L
(FIG.3-4)

DATA

(ROW)

i AT

TN g

@_l

I ADDRO<12:4> | (coL)

(F16.3-16))—REERESH

b0 p—

OAAM

oM | —

256K

<b:0>

286K |—— | 286K

ACOR

MM ADDRO

l
REFRESH
COUNTER

[

CLK_WRITE

{FIG.3-%)

LATCH

(*F1a@.3-12))

)

{me

WT«,

LATCH

Aed>

LCH

AAS<0>

CAS<0>
BIT

BESEY PAL<Qx
CLR

SHIFT

REG.

WAT CONE o>

J—

BIT

j¢—

ARRAY

BANK NO.

CHECK CMD INH

SET CASINCR>

TIL

e
SET AC<0>

CHECK_CMD INH<1>

R
———H
REF FEO
FiG.3-16)

CLR

HOLD

DONE <0>

DROY

<>
(FIG.3-12)

RESEYT

Figure

Array

There

chip

thirty-nine

are

has

One

BCLD-342

Bank

Block

Diagram

512

chips

512

matrix

bank

one-bit

locations*,

The

megabyte

data

oOne

32-bit

the

data

row

the

provides

DRAM

effective

the

within
makes

4MBARRAY

(Bank

Shown)

DRAMs

(262,144)
locations
contains a

3-9

F109<0>

DRAM

actual

256K

bits

longword

address
to

provide

matrix

and

the

array

check

bits

muxed

ten

bits

256

rows

storage).

3-27

256K

39-bit

DRAM
256K

39-bit

location

bits).

the

column

1024

Each

providing

provides

storage

ECC

bank.

array

column

address

addressing.

columns

(which

This

still

Each

bank

data

and

has

check

The

of
a

DRAMs has
32-bit

seven-bit

input

32-bit
port

input port

supply

the

to receive
read

the write

data.

port and a seven-bit output port

also

for the

bits.

DRAMs

receive:

A
nine-bit
address (RAM ADDR0<8:0>)
muxed for row and column addressing.

°®

write

read

enable signal

or write

row

address

output

(WE<K0>)

internally

to place the DRAMs

into a

mode.

address

strobe

(RAS<K0>)

from the

address

lines.

A
column address strobe
address from the address

8409

which

(CAS<K0>)
lines.

strobe

to strobe

1in the row

in the

column

DRAM Controller

The
8409
DRAM
controller
supplies
the
row and column address
to
kAl
address
ninao—_hit
and the
cai~anal
anasahlhlasa mads
writa
h
tlle
W.L.LL.C CIIQL}.LC
.I.ll\JUD O.Lyllbl..l-’
CALLINA
il 15
4 L1G ok
LI i Rl
sScrooes,
the
DRAMs.
The
controller
functions to mux the row and column
addresses
onto
the
DRAM
address
lines.
During a refresh, it
supplies the refresh address to the DRAMs.
C.

Bi-Directional

I/0 Latches

Two bi-directional I/O latches control the data flow from the bank
I/0
ports
to
the
DRAMs.
One latch transfers the data longword
(INT
DATA<31:0>)
while
the other transfers the associated check
bits
D.

(INTR

Bank

DATA<38:32>).

Manager

The
bank
manager
sequencing
of
the
listed

1is
a
PAI,
state
array operations.

below.

PRE

RC<K0>

~--

controller

machine used to control the
It generates five signals as

from

PRE

CASIN<KO>

BANK

DRDY

muxes

the

row

address

the

column

DRAM address
to

column

address

lines

the

8409

address.

strobe.

DONE<O> -- the data-ready-done signal

for the

MCL.

RESET
that

F109<0>
bank

RESET<0>

—--

-not

resets

vresets the

input parser and

indicates

busy.

the

bank

3-28

for another operation.

Shift

The
for

shift
each

manager

has

six

output

states

that

operation.

The

six

output

states

are

for

functions

control

are

3.3.2.2
Data
Flow
data
1longword

check

bi-directional
DRAMs.

The

separately

while

the

port.
parser
LOAD

the

"in"

section

data-output

read

When

the

is
on

into

INT

are

the

shown

the

two

DATA<31:0>

I/0
port

into

the

"in"

section

the

check

bits

the

DR WRT

DATA

coupling

the

latches

into

the

DRAMs

from

the

DRAMs

DIS

into

from

the

longword

and

respectively.

data

coupled

latch

RAM

DATA<31:0>

"out"

section

ENABLE

from

the

strobing

latches

for

the

the
read

which

latches

out

functioning.

applied

the

EN<O0>

and

their

data

the

is for the
connects to a

latches

longword

BANK

for

other

port

The

read),

latches

latch.

One

on the INTR DATA<38:32>
write operation, the input
followed by DLY LOAD DATA<KO>.

thereby

read

ports.

the

bank
array

the

longword

bit

negates

data

through
the

placed

DATA<O>

sections

READ

data

Each
of

Specific

the

latches.

sections

data

placed

false

selected

asserts

"out"

check

bit

the

been

write

LOAD

the

stepped

states.

I/O

illustrate

DATA<38:32>

CASIN<KO>

have

bank

control

the

DLY

check

applied

bits are
selected
for
LOAD
DATA<O0>

"in"

data
while

sections

check

RAM

DATA<K38:32>.

arrays

the

longword

operation,

section

With
the

the

and

transfers

diagram

and

two

DATA<38:32>).

block

while

from

the

DATA<31:0>)

(INTR

1is

true.

has

the

RAM

bank

DATA<31:0>

are

The

control

RAM

"out"

1latches

latch

bits

which

bank
0
assert

DATA<0>

data

each

output

data

the

and

associated

With
will

bits

sequencing.

operation,
The

the

check

bits

latch
the

write
ports.

array

(INT

1input
in

data

the

performed

the

associated

are

supplied

the

applied

while

check

the

bit

data-output

sequence

the

check

latch

control

(after

the

read data in both latches.
operation, the data-output

transfers

the

I/0

the

read

data

from

ports.

NOTE

read

octaword

read,

simultaneously

check
bits
are
respective
latches.
not

harmed

after
MCL

the
can

latches

3.3.2.3
of
Use

the

Array
array

the

while

Command
diagram

following

the

The

are

the

banks

are

data

and

into

latched
that

read,

read

refresh

Sequencing

four

the

loaded

refresh

arrays
take

sequencing

flow

all

and

may

fact,
from

occur

data

the

the
executing.

Figure

3-10

for

command

operations

along

with

the

block

3-29

discussion.

their
data

flow

diagram

and

reads).

(writes

diagram

Figure

3-9

Y
t LATCH ADDR<G>

——

DRAM

4 RAM ADDRO<8:0>
LAT ADDRO<21:13>
selocted by DRAM
controller as row

LAT WRT<0

address.

LAT WRT<0> falise )

I CAS strobe

is written.

inhibited.

WE<0> false. Read

t WE<0>

4 CLK SEL<0>

WRITE

YES

latched

WRT<0>

CLK

address

$ LAT ADDRO<21:14>

LAT

)

function enabled

Write function

in DRAMSs.

enabled in DRAMSs.

No data

4 PRE CASIN<O>

e —

RASIN<O>

XI
0e-¢

Assert input to
shift register.

‘

4 CASIN<O>

% DRDY DONE<O> I

4 CAS<0>

BANK DRDY DONE<O

RAS<0

Lgtgh _RA(M ADDlflo

<:>|nocou_mn

latchte in
address
DRAMs.dE)(ecu
command tn arrays.

INH<0>
4 CHECK
regigter
Shift CMD
state no. J.

L’atch "RAM
row
into ADDRO
<805

address latch in

# SET RC<0>
Shift regi?tar
state

no.

3
v

—

t PRe RC<0>

;r‘_—

4 RC<0>

|
i

.YES

NO
S

LAT
WRT<0>

+ BANK DRDY DONE<0>|

4 BANK DRDY DONE<O>

controller”as
cplumn address

4 SET CASIN<O>
Shift register
state no. 2.
SCLD-376

|\A

Figure

3-10

Array Command Flow Diagram

(Sheet

1 of

4 SET WRT DONE«0>
Shift

state

LAT
WRT<0>

YES
l

¥ BANK DRDY DONE<0>

Y
¥ DRDY DONE<0>

1€-¢

‘,v, e

4 CLR WHAT DONE<0>
Shift
state

RESET<0>

4 RESET PAL<O>
Shift

state

RESET F109<0>

v PRE CASIN<O>

¥ PRE RC<0>

4 HOLD RESET<0>

v CASIN<0>

y
Reset

Bank

¥
Manager)

Done

Reset shift
register.

RESET<0>

¥ RESET F109<0>

v RC<0>

* CAS<0O>

¥ HOLD RESET<0>

Figure

3-10

Array

Command

Frq. 3—/0 (2 ot 2>
Flow

Diagram

(Sheet

SCLD-377

1is received from the input parser to
ADDRKO>
LATCH
asserted
An
address (CLK ADDR<21:4>*) and the commanded
array
the
up
latch
function

(CLK WRITE).

CLK WRITE is true (write operation), LAT WRT<0> is output from
If
the DRAM controller which in turn asserts WE<KO> to
to
1latch
the
of
write mode
the
into
DRAMs
the
places
WE<0>
DRAMs.
the
also
are
WE<O>
CLK WRITE is false, LAT WRT<0> and
If
operation.
false and the DRAMS are placed into the read mode of operation.

address latch (LAT ADDRO<21:4>)

the

from

is divided

The

output

LAT
row

the array row address and is applied to the
1is
ADDRO<21:13>
DRAM controller. LAT ADDRO<K12:4> is the array
the
of
input

into

two nine bit sections;

column

and

address

LAT ADDRO0<21:13> and LAT ADDRO<K12:4>.

applied

to the column input of the DRAM

1Initially, the controller selects the row address for
controller.
transfer to the DRAMS as the RAM ADDR0<8:0> address input.

received from the input parser to start the array
1is
SEL<K0>
CLK
DRAM
the
to
RASINKO>
asserts
SELKO>
CLK
sequence.
strobing
to the DRAMs. RASK0>
RAS<0>
asserts
turn
in
which
controller
address now on the DRAM address lines, into the
row
the
latches
row address

latch

in the

DRAMs.

the shift
to start
needed
input
the
also provides
RASIN<KO>
the next TTL CLK BM clock, RASINKO> is clocked into
On
register.
the

shift

which attains state number 1 and asserts SET

The bank manager asserts PRE RC<0>
bank manager.
the
to
RC<0>
causing RC<0> to assert to the DRAM controller. RC<0> switches the
that the column address LAT
so
controller
the
in
mux
address
RAM
as
lines
address
DRAM
the
onto
muxed
is
ADDRO<K12:4>
ADDRO<K8:0>.

On the next TTL CLK BM clock,
SET
asserts
and
2
number

receiving
N\
WRTLG>.

T.ITYNTY 2

SET

T £
If

the shift register advances to state
the bank manager. Upon
to
CASIN<KO>

CASINKO>, the bank manager checks the state of LAT

LAT

T am

WRTKO>

TITYM 7 Y\

:
is

true

.
3
3
operation),
{(write

the manager

CLK CMD INH input from the input parser to see if the
the
checks
CMD INH is false, the
CLK
If
execute.
should
operation
write
PRE CASIN<O> which becomes CASIN<O>. CASINKO> 1is
asserts
manager
to the DRAM controller which asserts CAS<0> to the DRAMS.

applied

the column address now on the DRAM address lines,
latches
CAS<0>
into the column address latch in the DRAMs. The data at the DRAM's
into the arrays. If CLK CMD INH is
then written
1is
port
input
column address strobe is not generated and no data is
the
true,
written

into

* Address

the

bits

arrays.

CLK

ADDRK25:22>

are

pbanks,

3-32

not used by tne MAR4 array

LAT WRTK0>

1is

false

(read

operation),

the

bank

manager

asserts

PRE CASINKO> which generates CAS<K0> to latch up the column address
in
the
arrays.
The
arrays
are
then read and the read data is
available
at
the
data
ports
as
INT
DATA<K31:0>
and
INTR
DATA<38:32>.,
1In
addition,
the
bank
manager
asserts BANK DRDY
DONE<KO>
DRDY

which

DONE<KO>

however,
back

operation.
to

turn

asserts

asserted

1is

for

asserted

This

select

DONE<K0O>

both

earlier

because

the

DRDY

MAR4

read

1in

the

and

the

input

parser.

write

operation,

sequence

read

operation,

for

read

and

take

the

read

MCL must

for

come

read

data.

BMAR

SEND NO CMD inhibits the MCL from issuing any commands to the MAR4
until
this
occurs.
1In a write operation BMAR SEND NO CMD is not
asserted
and
the
write
operation
must
be completed when DRDY

DONE<O>
1is
asserted
operation to the

as
the MCL may
same bank.

write
The

state

clock

number

bank

manager.

CMD

INHKO>

asserted

this

the

shift

causes

assertion

moves
the

BANK

1input

CHECK

CMD

asserts

«c¢lock
SET

operation,
were
If

this

1is

state

WRT

moves

number

DONE<0O>

action
The

occurs

number
manager.,

)

1is

clock

6,
In

the

Negates

and

CMD

the
a

assertion

In
the

CHECK

read

operation,

the

DONE<O>

DONE<KQO>

and

preceeding

state

manager.

3.
to

DONE<KO>

DRDY

state

number
INH<KO0>

DRDY

BANK

another

number

which
write

negated

(they

shift

action

occurs

asserts

CLR WRT

DRDY

state

this

are

the

and

the

shift

refresh

operation

(Section

DONE<O>,

CLR

3.3.2.4).

commands.

the

shift

state

during

DRDY

preceeding

shift

the

its

bank

the

number

normal

response

shift
to

command

CHECK
and

this

causes

operation,

moves

where

asserted

DONE<O>

state

used

for

INH<K0>

the

read
to

DONE<K0O>

the

DRDY

during

operation,

DRDY

were

DONE<O>

BANK

asserted

moves

WRT

write
parser.

DONE<KO>
to negate (they
of the shift register).
The

shift

immediately

RESET

asserts

PALKO>,

PRE

RC<0>

output

its

PRE

CASIN/KO>

CASIN<KO>

and

CAS<K0>).

the

its

final

state,

RESET

PALKO>

bank

manager:

(followed

the

state

the

bank

negation

RCKO0>).

Negates
of

Asserts
parser

Asserts
another

RESET
logic

ocutput

F109<0>

and

indicate

RESET<0>

reset

operation.

the

that

3-33

{followed

input
bank

the

bank

parser
is

the

negation

reset

longer

the

busy.

in preparation

for

RESET<0>

and

HOLD

asserts

fed

back

RESET<0>,

The

negation

The

array

HOLD

RESET<0>

into

the

manager

RESET<0>

bank

initiate

another

3.3.2.4

Array

now

bank

Refresh

its

clears

negates

RESET

causes

command

which

manager
HOLD

Sequencing

shift

it.

F109<0>

RESET<0>

initialized

operation

the

reset
to

state

response

and

RESET<O0>.

negate.

and

prepared

refresh.

NOTE

Refresh

sequencing

logic

(Section

refresh

logic

sequence

that

sequence

Figure

3-11

refresh

3-9

1is

flow

during

the

precedes

command

functions

When

logic

sequence

are

refresh

followed

applied

all

not

il oL

banks

which

applied

column

address

inputs

counter.

The

counter

incremented

CLK
of

that

REFRESH
the

listed
®

five

diagram

during
of

Figure

many

and

bank

the

A
manager

T 3 g 1n
mucrh

command

signals

8409

asserted

refreshed

DRAM

REFRESH

addresses

also

refresh

REFRESH

where

substitutes

output

the

CLK

are

simultaneously.

controller

and

from

and

enables

disables

address

from

the

row

the

counter

the
to

the

manager

bank

manager

functions.

The

where

functions

inhibits

four

inhibited

are

below.
PRE

RC<K0>

PRE

address

CASIN<KO>

BANK

RESET

refreshes

are

done

row

time.

needed.

=~-

due

the

above,

column

address

needed.

DRDY

informs
e

sequencing

block

RASIN<O>.

applied

strobe
®

the

refreshed.

bank

column
o

array

REFRESH

are

1is

array

REFRESH

and

refresh

n
1 =
-~
register

REFRESH.

the
a

array

the

that

REFRESH

row

signal

the

and

+
ft

except

occur,

CLK

four

the

used.

[o]

the

refresh

Hence

discussion.

and

the

here.

diagram of

Refer

following

describes

described

operation.

begins

3.3.6.1).

the

DONE<O>

the

MCL when

the

refresh

F109<0>

not

need

has

completed

the

reset,

the

input

and

the

refresh,

3-34

state

BMAR

SEND

CMD

completed.

parser
refresh

was

not

logic

used
knows

does

when

4+ REFRESH
In

DRAM controller:

.disable normal row
and column addressing,

- couple refresh
output to
address lines,
- enable refresh

counter

counter.

4 SET WRT DONE<0>

t cLK REFRESH

Shift

stale

4 CLR WHT DONE<0>
Shift
stale

‘Inhibit

PRE RC<0>

‘Inhibit

PRE CASIN<O>

-inhibit BANK DRDY
DONE<0>

-Inhibit

RESET F109<0>

GE-¢

4 RESET<0>

t RAsIN<O>
T

v
Assert input to
shift register.

Shift register
passes through
1

and

Increment

Latch RAM ADDRO
<8:0> into row
address latch in
DBAMs

counter.

4 CHECK CMD INH<0>

Array

Manager.

Reset

shift

No. 1

Bank

¥ RESET<0>

4 CHECK CMD INH<1>
Shift
state

no.

Bank

states

state

reiresh

Reset

Shift

4 HOLD RESET<0>

4 RAS<0>

¥ HOLD RESET<0>
4 CLR REF REQ
Reset

Relfresh

logic.

§CLD-383

Figure

3-11

Array

Refresh

Flow

Diagram

CLK REFRESH also asserts RASIN<KO> which in turn:

the refresh counter to the address of the row

Increments

that

to be

refreshed.

Asserts RAS<(0> to the DRAMs to latch the row address from
the row address latch in the
1into
counter
refresh
the

DRAMs.

Provides

the

input

shift

for

state

seguencing.

The

shift

1is clocked from state number 1 through state

number 4 as the arrays are being refreshed.

the shift register enters state number 5, it asserts CLR WRT
When
the bank manager to reset the array bank. In response
to
DONE<O>
the manager asserts RESET<0> causing HOLD
DONE<0O>,
to CLR WRT

RESET<0>

to assert and clear the shift register. HOLD RESET<KO0> is

fed back into the bank manager causing it to negate RESET<K0>
also
now
is
bank
array
The
HOLD RESET<0>.
negates
then
which
refresh.
another
or
initialized for a command operation

When

CHECK

the shift
CMD

1in

bank 1 reaches state number 3, the

INH<1> output from the register changes to CLR REF REQ

CLR REF REQ clears the
logic.
refresh
the
to
applied
is
and
for another refresh
logic
refresh request and prepares the refresh
cycle.

3.3.2.5

Battery Mode

-NOTE

mode events in the refresh logic
Battery
precede those in the array banks. Section
describes battery mode operation
3.3.6.2
£
of

th
the

refresh

logic.

an
1is
there
entered when
automatically
is
mode
Battery
is
object
the
mode,
battery
in
While
interruption in system power.
resumed.
1s
power
until
arrays
the
1n
data
the
save
to
command
-allowed
are
cycles
refresh
only
Consequently,
drain
power
reduce
To
inhibited.
operations (writes and reads) are
battery
and
suspended
are
on the battery, normal refresh sequences
Battery mode refreshes use only the
refreshes are executed.
mode
barest minimum of logic thereby making lower power demands on the
battery.

arrays for
the
in
data
the
retain
cannot
operation
Battery
only ten
for
retained
is
data
long-term power outages. The array

minutes.

After this the data

is no longer reliable.

battery mode is enabled, th e a rray banks receive the refresh
When
oscillator clock (REF 0SC) from the MCL, and five signals from the

3-36

refresh

logic.

The

signals

received

below.
°

REF

OSC

14.9
°

from

MCL

battery

initiates

microseconds.

REFRESH

during
mux

from

normal
the

column

8409

address

the

output

also

refresh

DRAM

from

the

enables

controller
the

refresh
the

logic

operation.
DRAM

REFRESH

It
to

RESET

functions

HOLD

INH

NORM

the

REF

DIS

REF

RESET

RASINKO>

address

assert

DRAM's

RAS

row

250

for
the

the

When
and

refresh

refresh
of

the

1logic

RASIN<O>

and

lines.

PWR

inhibits
is

turn

all

asserted

holds

the

INH NORM REF

logic

used

during

operations.

refresh

the

RESET

RESET<0>

which

row

enables

incremented

logic

RASINKO>

1logic

BATTERY

that

1is

from

each

has

disabled

set

starts

DRAMs

logic

the

enables

used

where

for

REF

RAS

negates

power.

manager

and

the

counter

supply

refresh

enabled

the

refreshed.
it

DIS

bank

increments

conserve

refresh

clocking

1logic

RASINKO>

row

refresh

strobes

the

REF

OSC

BATTERY

and

causes

refresh

shift

cycles.

also

counter

causes

row

address

holds

the

RASIN<O>

is
the

RAS<0>

the

to
the

lines.
takes

about

7,300

(see

REF

RAS

edge

REF

DIS
is

150

ns.

0SC.

than

the

duration

1in

the

OSC

3-19).

asserted

current

REF

Figure

and

Thus

enough

negates

RASIN<QO>

time

for

RASIN<O>

arrays

shorten

thereby

the

power

operation

returns,
is

the

battery

resumed.

3-37

the

RASINKO>
array

mode

signals

250

for
row

significantly

reducing

logic

duration

asserts

power,

system
normal

OSC

Reducing

battery

assert

refresh

RASIN<KO>

leading

which

refreshed.

the

RASINKO>,

after

REF

the

refresh

enabled

PWR

assert.

address

from

after

the

REFRESH

address,

applied

and

the
and

R
S

RASINCO>

After

RESET<0>.

portion

logic

manager where

except

normal

BATTERY

the

refresh

bank

address

reset.

the
and

from

RESET<0>

command

the

causing

disables

manager

shift

°®

PWR

applied

the

lines

every

functions

inhibit

onto

counter

described

cycle

causes

RASINKO>,
°

are

refresh

address

counter

refresh

mode

the

are

only
to

reduces

drain

removed

3.3.2.6
banks

Cold

from

sSstart

the

interruption

MCL

when

(greater

MCL

COLD

START

system

power

than

asserted

applied

ten minutes).

The

after

the

array

long

power

purpose

MCL

COLD

START is to inhibit the arrays from operating until the system has
powered
wup and initialized. The current drawn by the arrays would
have a detrimental effect on the system power-up process.
MCL

COLD

PWR

UP.

sent

COLD
which

Iin

START

COLD
the

PWR

1is

PWR

DRAM

condition,
refresh).,
refresh

functions
removes

for

the

must
where

Array

Bank

four

array

banks

the

MCL

COILD
(4

COLD

START

bank

applied

CHECK

1in

other

holds

and

the

DRAM

CMD

MCL

START

three

becomes

from

CLR

the

Generates the write
is to be aborted.

Generates

commanded

operation

"data

that

also

two

tri-state

applied

(not

the

minor

These

areas

where

involve

only

PWR

bank

the

shift

REQ

array

UP.

COLD

and

bank

PWR

1is

the

DRAM

ready
has

done"

MAR4

3-38

the

are

exactly

(and

refresh

identical.

command/address

when

signal

for

write

the

data

operation

MCL when

the

completed.

board

MCL.

bank

the

signal

been

applied

functions:

inhibit

and

banks

following

the

its

operation

same.

COLD

a
parity
check
from the MCL.

outputs

attain

are

the

applied

REF

four

the

also

banks.

mode
1is

COLD

and

banks.

output

Establishes

controller

negated.

There

controller

renamed

Performs

where

three

becomes

1is

respects,

DRAM

TNH<1>
A LNLA
N A/

N\rd X

INH<K1>

received

COLD

START

other

the

command

exactly

CHECK
N ld LN LN

COLD

bank

other

REFRESH

not

3.3.3
Input Parser
The input parser performs

the

MCL

are

from

the

Differences

MCL

the

CMD

only
bank
logic.
all

controllers

START
WAk LAMAN L

controller

be
it

3.3.2.7

array

DRAM
R

array

to tri-state the DRAM controller
the signal inputs to the DRAMs.

Consequently,

logic

applied

controllers

the

The

effectively

order

MCL

applied

has

been

selected

the

The

Decodes

the

enabling

signals

Generates

"array

logic

the

array

functions

3.3.3.1

when
are

input

CLK

OCTA,

ADDR<25:4>)

parity

detects

error

parity

PAR

ERR

BMAR

CMD

ADDR

and

INT

PAR

command/address

used

3.3.3.2
to

the

Write

assert

the

returned

error

3-12

and

The

and

for

four-bit
the

array

checker

ADDR

the

(CLK
(CLK

the

MCL

flag

INT

where

PAR
it

ERR

the

part

the

received
was

detected

asserts

DATA

INHIBIT

from

inhibit

bit

PAR

CLK

CMD

INH

the

array

the

write
ERR

asserting

CLK

could

conditions

the

data

turn

Ready

array

asserts

BMAR

MCL

indicate
write

the

bank

that

The

can

send

write

was

Done

from

DATA

RDY

DONE.

the

command

bit

1is

check.

done

ECC/DPARITY

inhibit
parity

bit

error

the

logic

prevents

WRITE

because

the

error*,

thus

written.

Under

write

these

precaution.

generate

BMAR

DATA

BRD
RDY

operation

gate

BMAR

parity

will be
executed,

logic,

and

data-ready-done

commanded

written.
another

The

parser

This

the

ORed

the

ECC/DPARITY

input

meant

are

1inhibit

the

INH.

banks
that

was

CMD

written

operation,

that

the

causing

data

Data

data
to

the

INHIBIT

write

data

derived
from
the
write
write data from the MCL. If a

3.3.3.3

WRITE

1is

uncertain

from

that

causes

disables

the

asserted

fact

ERR

CMD

INHIBIT

CMD

PAR

CLK

also

BMAR

ADDR

the

checker

CMD

being

INH

with

the

1If a write operation is being executed,
into
the
arrays. If a read operation is
operation will execute normally.

WRITE

below.

command

asserts

written

logic.

refresh

address

along

PARITY).

occurred.

CMD ADDR

function.

the

ERR.

has

banks

generates

described

function.

INT

array

signal

busy.

parity

PAR

and

not

CMD

MCL

command/address,

inhibit"

Inhibit

busy"

are

Check

(CLK

the

bank(s).

Figure

ADDR

parity

"write

bit

CMD

ERR

not

STADDR<1:0>)

applied

command/address

from

array

banks

Parity

CLK

are

ADDR

the

illustrated

Command/Address

WRITE,

command

for

will

DATA

RDY

(read

included

3-39

signals

DRDY
DONE

DONE
is

received
which

sent

has

been

executed.

receive

DRDY

DONE<X>

DONE
ey

and

indicates

write)

write

the

from

the

same

in
the

MCL

bank.

data parity

DRDY.

(Fig.

3.9)) DONE<Q0>

_DRDY_DONE<3>

BMAR DATA

BE_BY DON

DRDY DONE<2> L

-FOY DONE__p. (F(g. 3-4)

Dnoz_ggy_rs_gl@ T

DRDY

—

BMAR CMD ADDR_PAR ERR

ADDA_PARITY
5. CLK_CMD

(3-49)

WAITE
>—GLK
> CLK OCTA

yCLKSTADDR<! 05

o
N»

SNC CLK.

(Fig. 3-7)
e

EN rev
ADDRc3>

CIA

CAECKER

EN NEW
. DO_QDfl';Z>

INH ]
ALERR3=~y CLK_OMD

WRITE _INHIBIT AD
(Fig. 3-13)¢ 2,

‘

ADDR<O>

XI
0¥-¢

CLK_OCTA

I D SEL<3:0>
p

SE <dn

CODER ||-] |- {TM) SEL<ze
(8)—CLk_STADDR<1:0 )| PECOPER
B

"D.,S,EJ:JZ, L 2

t
——=D

RESET

CLK_SEL<3>

RESET

l eyfi
lL] ctk sEL<t>
RESET

(.._E_l_Q9~<_l.>’ K

=ZSET F109<3:02
(Fig. 3-9)»
a-4y) JATTERY ENABLE

plk

LATCH

ADDR<2>

‘

fl—

LATCH

ADDR< 1>

OAD

J-F"F'TDATA<O /)

CLK SEL<0> _/

DELAYS

LOAD 2]
o[I 7r] DATA1

LOAD
DLY
DATA<30-.

> P(Fig.
.

"1 3.9)

DLY LOAD

(150 NS)

LOAD
_DATA<224

4 |
= | |owserees

r,.E.LQS(Z?.K

RESET

LOAD
)]
Fr] DATA<d24

LATCH

&k‘;

’ F109

Figure

LOAD

— > ADDR<3>

TT‘

(Frg.

DATA<3:0»

CLK

‘ .

.
SEL<3:0>

L ——
INT_BRD_SE
e dEmmm——y
(Fig., 3-4)p

RAAY._|

EN NEW [“
53

INT _CMD

>(Fig.: 3-9)

DATA<3>

—»

LOAD
"/
DATA<2>
| DLY

LOAD
DATA<T>
| DLY
DLY LOAD _/

_DATA<O>

LATCH

. D ADDR<O>

_s:.tfl_

LATCH

| ADDR<3:0> _

—

]
SCLD 80

3-12

Input

Parser

Block

Diagram

For

longword

DONE<X>

from

operation,
at

the

both

read

the

same
has

that

OR gate

time

<cases

array(s)

operation,

bank

will

because

BMAR

(have)

read.

receive

four

gate

will

For

receive

DRDY

octaword

read

data-ready-done

signals

the

four banks are read simultaneously,
RDY DONE indicates to the MCL that the

DATA

been

the

was

read

and

the

read

data

available

SEL

asserted

taken.

3.3.3.4
MCL

MAR4

when

operation.

derived

Board

the

INT

all

Selection

MAR4

board

BRD

SEL

the

array

has

INT

BRD

been

enables

five

enabling

selected

AND

for

functions

signals

the

commanded

from which

developed

the

are

input

parser.

3.3.3.5

Generation

command

bits

parser

for

used

(CLK

bank

1in

Array

OCTA

and

selection

the

checking.

input
CLK WRITE 1is

establishes

either

the

Bank

CLK
and

Signals

STADDR<1:0>)
control.

parser
only
sent directly

write

read

The

Three

are

used

fourth

of
in

bit

the
the

(CLK

four
input

WRITE)

for command/address parity
to the array banks where it

mode

operation

(see

Figure

3-4).
When

bits

CLK

longword

functions.
bank

SEL<KX>
CAS

cycle

sequence.

LATCH

later

LOAD

DATA<KX>

asserts

write

data

data
of

the

that

independent

for

Dbank

LATCH

ADDR<KX>

write

operations.

LOAD

the

where
a

J-K

associated

the

check

perform

DATA<X>

bits

their

and

135

check

operation
DLY

bank

"in"
ECC

address

four

AND

the

flip-flop

CLK
and

X where

bit,

array

bank

the

section

later

DLY

LOAD

check

bits

into

the

bit
to

developed

the

command

selected

the

Approximately
the

signals

whether

and

into

bi-directional

SEL<X>

write

load

time

the

1longword

latch.

SEL<X>
and then LATCH ADDR<X>.
bank X where it initiates the RAS
WRITE

Note

latch.

The

generated

135

the

input

parser

are

read

write.

CLK

functions

LOAD

for

DATA<X>

both

are

read

and

used

only

bank

after

the

F109<X>

resets

the

operation.

F109<X>

1is

received

operation

flip-flop

sets

applied

Logic.

SEL<KX>

ECC/DPARITY

which

address.

one

SEL<X>

CLK

allows

When

CLK

array

asserts

ADDR<KX>

delay

J-K

starting

enable

and

section

ADDR<X>,

function

executed,

address

"in"

RESET

AND

asserts

commanded

being

array

the

decoded

asserts

bi-directional

for

read

are

the

DATA<KX>

the

applied

strobing

load

enabled

turn

latches
One

The

selected

which

write

STADDRK1:0>

LOAD

has

resulting
DATA<KX>,

octaword

turn

and

read

asserts

from

been

selected

RESET

1in

the

negation

DLY

LOAD

DATA<KX>.

being

executed,

1is

all

the

executed.

four

the

3-41

CLK

SEL<3:0>

CLK

SEL<X>,

OCTA

inputs

LATCH

asserted

the

J-K

flip-flops. This sets all four flip-flops causing CLK SEL<3:0> and
to all the array banks. CLK SEL<K3:0>
assert
to
ADDR<K3:0>
LATCH
the RAS and CAS strobing sequence in the banks while LATCH
starts

array address and CLK WRITE function.
the
up
latches
ADDR<3:0>
the arrays have been read, RESET F109<3:0> is received from
After
the four J-K flip-flops and negate the bank
reset
to
banks
the
signals

developed by the

3.3.3.6

input parser,.

Array Not Busy -- An AND function senses the state of the

J-K flip-flops and asserts ARRAY NOT BUSY when they are all reset.

If
be

command is executing, at least one of the flip-flops will
any
set causing ARRAY NOT BUSY to be false. ARRAY NOT BUSY is sent
the

refresh

logic to indicate that the arrays are free and a

refresh operation may

3.3.3.7

Battery

oOcCcur.

Mode

battery

1In

mode,

BATTERY

ENABLE is

MCL to hold the J-K flip-flops in the reset
from the
received
when power returns and the system comes out of
Therefore,
state.
battery mode, the flip-flops will be in their initialized (reset)
any of the flip-flops were to power-up to the set state,
state. If
Cardad
S
o

3.3.4

The

write

The

ECC/DPARITY

1logic

performs the following functions during a

operation:

Generates partial check bits on the write data longword.

Provides WRT INHIBIT to the input parser to abort a write
operation.

Performs a parity check on the write data.

Generates an INT BAD DATA bit for the final ECC logic.

functions are illustrated in Figure 3-13 and described in the

following

sections.

ECC Check Bits -- The data longword (INT DATA<K31:0>) is
3.3.4.1
received from the write-data flip-flops (Figure 3-4) and applied
The generator develops seven ECC partial
ECC generator.
to an
The check bits are output
check bits unique to the data longword.
as PCB<6:0> to final ECC logic on the MAR4 board.

3.3.4.2

Write Inhibit -- CLK WRT INHIBIT is received from the MCL

longword

WRT INHIBIT. CLK2 WRT INHIBIT is output as WRT
CLK2
becomes
and
INHIBIT tc the input parser. WRT INHIBIT is asserted when the data
not

to be written

into the array.

3-42

(Fig. 3-4)<

CLK2 GOOD DATA

(NHTBIT

CLK
DATA PARITY
|

CLK2_DATA
PARITY
‘

WRT INHIBIT |

[>o-BAD DATA

PARITY

Ev-¢

CLK

GOOD DATA o1

pp | WBLINHIBIT

DATA

DATA<31:0>

INT

| _PARITY ERROR

CHECKER

INT

__}}(Fig. 3-12)

ECC
GEN

DATA
PAR_ERR

PCB<6:0>

’ 4 -'49)

Fig.

>ECC TEST[S,
SCLD-382

Figure

3-13

ECC/DPARITY

Block

Diagram

(INT
3.3.4.3 Write Data Parity Check =-- The data longword
is applied to a parity checker along with CLK2 WRT
DATA<31:0>)
CLK2 GOOD DATA, and CLK2 DATA PARITY. CLK2 GOOD DATA and
INHIBIT,
CLK2 DATA PARITY are respectively derived from CLK GOOD DATA and
CLK DATA PARITY received from the MCL (Figure 3-4). CLK2 DATA
PARITY

GOOD

DATA

detected,

parity bit for the data longword and for the CLK2

the

1is

WRT

CLK2

and

INHIBIT

bits.

parity error is

DATA PARITY ERROR is asserted which in turn asserts INT

BAD DATA to the final ECC logic on the MARA4.

detection of a data parity error also asserts DATA PAR ERR toO

The

it disables the write inhibit function.
input parser where
the
the write inhibit bit is included in the
because
done
is
This
causing the parity error.
the bit
and could be
parity check
is uncertain whether the data is meant to be written,
it
Because

write operation is allowed to execute even though WRT INHIBIT

the
is

true.

INT BAD DATA -- If the write data longword contains bad
3.3.4.4
data, CLK2 GOOD DATA will be false causing BAD DATA to assert. The
BAD DATA will assert INT BAD DATA (if not already
of
state
true
asserted by a data parity error) to the final ECC logic on the
MAR4. Here the INT BAD DATA bit is combined with the partial check
to

bits

the

produce

check

final

bits

(INTR DATA<38:32>). An

the final ECC bits will show if the INT BAD DATA bit
analysis of
is true, but it will not show if it was asserted by a parity error
or by an asserted bad-data bit.

Data Output Control
3.3.5
The data-output control functions to:

The

for a read.

°®

Enable the MAR4

Select the bank for the read data transfer to the MCL.

Enable the MAR4 board for the data transfer.

Control

Generate the DRDY SNC CLK clock.

the

transfer of

read data.

functions are illustrated in Figure 3-14 and described in the

following sections,

3.3.5.1

applied

MAR4
to

Read

Enable

-- Board select signal INT BRD SEL is

the data-output control and asserts BRD SEL. The read

signal (negated CLK WRITE) is applied to the data-output
function
asserts READ. READ and BRD SEL are ANDed and applied
and
control
to an OR function which asserts READ ENABLE and DR WRT DATA DIS.

3-44

SR
CLK

)

(Fig. 8-4))—STARDR<1:0=pdrr
e

EAD

fiE;A-.';> (Fig.

READ

> B

]

3-9)

EN<3:0>

REG
BRAR, BANK

cle

>
N

—DATA OUT CLK

[rr

BMCL DRIVE NEW DATA

CLK

..,_WBLE#DO_,

(Fig.

——
Fp

pe-

[»]

CODER

BATTERY

——

BD SEL

fe |l

ENABLE

FF | DATA

__GflBEAD_J

OUT

CLK

P (Fig. 3-4)

—_—

|HIEAD

¢v-¢

BRD SEL

(£V) ECL HIGH __[.

| e

IL.‘_F 83D
N

"'”“‘"I| S—

[

READ SELECT

'
1

BRD SEL

e e

INT

READ ENABLE

D
DR WHT DATA DIS I

;}(FIG.Z ) 9)
- s

HASESS o

READ_SELECT

(Fig.

3-16)

DLY READ SELECT

————(Fig.

3-4)

SCLD-370

Figure

3-14

Data

Output

Control

Block

Diagram

READ
ENABLE
1is
applied to the four array banks where it enables
the
"out" sections of the bi-directional latches., DR WRT DATA DIS
is
applied to the array banks where it disables the "in" sections
of the bi-directional latches.

DR WRT DATA DIS is also applied to the write-data flip-flops where
it
disables
the data-in path from the NAB to the MAR4's internal
data

bus.

The

OR function further prepares

READ IN PROGRESS which
IN
PROGRESS
1is
sent
SEND NO

CMD

the

the MAR4 for a

read by asserting

then asserts DLY READ IN PROGRESS. DLY READ
to the refresh logic where it asserts BMAR

MCL.

READ IN PROGRESS is fed back to the OR function through a latch to
hold
READ
ENABLE,
DR
WRT
DATA
DIS,
and DLY READ IN PROGRESS
asserted.
This
holds
the
MAR4
board in the read enabled state
until the MCL takes the read data.

3.3.5.2

Bank

Select -- The asserted BRD SEL and READ signals are

applied
to
a
decoder
causes the assertion of

causing
it
to output GOT READ. GOT READ
DATA OUT CLK which is applied to the clock
input
of
a
read-bank
shift
register.
The
shift
register is
presently
in
the
"load"
mode; hence, DATA OUT CLK functions to
load
the
shift register with the bank starting address. The bank
starting
address
is
obtained
from a decoder which uses the CLK
STADDR<1:0>
starting
address to assert one of four inputs to the
shift

The
mode
CNTRL<1:0>.

PROGRESS

mode

of
the
shift
register
RD
BANK
CNTRIK1:0>
1is

and

control

AMCL

signals

Table

3-3

READ BD SEL.

are

shown

Read Bank

1is
controlled
derived
from

The shift register modes and the

in Table

3-3.

Shift Register Modes

DLY READ
IN PROGRESS

AMCL READ
BD SEL

RD BANK
CNTRLK1>

RD BANK
CNTRL<KO>

Mode

0
0
1

0
1
0

1
1
0

Load
Load
No op

1l
2

asserted

negated

by
RD
BANK
DLY
READ IN

Sshift right

state
state

When DATA OUT CLK clocks the register, DLY READ IN PROGRESS 1is not
yet asserted. Therefore RD BANK CNTRL<1:0> is 1:1 and the register
is

the

load

mode.

3-46

The

shift

where

«couples

outputs
the

bi-directional

latches

When

DLY

and

the

3.3.5.3
take

READ

MAR4

the

bank(s),

the

data

read

AMCL

Data

READ

the

SELECT

Another

1is

become

also

BMAR

READ

1is

READ

the

BD
then

preparing

SELECT

1is

—occur

CMD

may

assert

due

PROGRESS

negates

(see

3.3.5.4

Control

bus

NEW

Clocks

The

the

DATA

the
the

thus

addition,

(now

bank.

the

next
the

the

bank

1is

OUT

CLK

DRIVE

This

done

the

was

delayed

DATA

DIS,

SELECT

the

"race"

the

NEW

the

SEND

asserts

DATA

OUT

read,

"out"

the

MAR4's

from

CLK

the

which

flip-flops.

the

NAB

shift

EN<X>

BMCL

internal

transferred

read-bank

that

READ

MAR4

where

DLY

the

signal

3-47

MCL

1IN

their

BMAR

read-data

BANK

octaword

bank

The

asserts
the

logic

form

READ

condition

before

from

enabled

from

DATA

data

READ

DLY

continue

wherein

negating

into

and

refresh

operation

DATA

and

latch.

transfer.

flip-flops

applying

the

WRT

the

outputs

SELECT which

data

bus

gate
gate

increments

Transfer

transferred

1latches
BMCL

the

causes

SELECT

NEW

the

the read

advancing

command

into

releasing

already

0:0

control

the

prevents

Data

are

becomes

where

all

3-16).

DRIVE

data

take

that

read

READ

internal

mode)

bi-directional
await

BMCL

read

DATA

"shift"

the

transfer

the

for

sent

Read

the

READ

This

Figure

outputs

the

MCL.
In

shift

Logic

SEL.

MAR4

also

end

NAB.,

data

flip-flop

SELECT;

ENABLE,

SEND NO CMD.

READ

asserted

may

DRIVE

DLY

the

CNTRL<1:0>

refresh

READ

functions

BMAR

SELECT

and

held

READ

the

gate

are

inhibits

AMCL

READ

BANK

CMD.

function

bus.

bank

READ SELECT to the read-data
flip-flop outputs onto the NAB

the

released

selected

sections

data

read-bank

PROGRESS

DLY

the

asserts

applied

SELECT.

SEL

SEND

function

SELECT

the

enables

control

1latch

READ

function

data-output

The

READ

"out"

Enable
-- When the MCL is ready to
bi-directional latches in the
array
BD SEL to prepare the MAR4 board
for

the

places

the

state.

operation.

3-4).

negation

READ

from

AMCL

SEL

In addition, AMCL
tlip-flops
where

(Figure

no-op

transfer.

mode

asserts,

EN<KX>

from

internal

Transfer

data

BANK

data

the

PROGRESS

asserts

READ

"shift"

attains

read

READ

read

READ

the

output

read

data

sections

the

internal

bus

the

MCL.

the

all the read data has been transferred to the MCL, AMCL READ
Wwhen
BD SEL is negated to complete the read data transfer.

3.3.5.5 DRDY SNC CLK -- The DRDY SNC CLK clock is generated from
a delayed ECL clock. The delayed ECL CLK sets a flip-flop which is
cleared by feedback to produce the DRDY SNC CLK waveform shown in
Note from the block diagram of Figure 3-14 that when
3-8.
Figure
CLK

OUT

DATA

waveshape

asserted,

1is

SNC

DRDY

it is in phase with and has the same

CLK.

CLK is applied to the input parser where it clocks BMAR
SNC
DRDY
CMD ADDR PAR ERR and BMAR DATA RDY DONE. It is also applied to the
refresh logic where

it clocks BMAR SEND NO CMD.

The DRDY SNC CLK clock is discussed further in Section 3.3.1 under
Clock

Logic.

3.3.5.6 Battery Mode -- When the system goes into battery mode,
applied to the data-output control where it
1is
ENABLE
BATTERY
the OR function. This prevents false "read
to
inputs
disables
enable" signals from being asserted when power returns. During the
remains true until all the data-output
ENABLE
BATTERY
power-up,
control logic has been initialized.
Refresh

3.3.6

NOTE

The
the

refresh logic initiates and controls
in the 4MBARRAY
operations
refresh

banks.

The

refresh events occurring in

of the
result
a
are
banks
array
the
section;
this
in
described
actions
the refresh description given
therefore,
4MBARRAY banks
the
on
section
the
in
(Section 3.3.2) complements the sequences
described here.

array

The

refreshing
All
data.
The
time.

matrices

the MAR4 boards are volatile and require

every 4 milliseconds to retain their stored
least
at
banks on a MAR4 are refreshed at the same
array
four
arrays are refreshed a row at a time with the same row

in each bank being refreshed simultaneously.

array bank has 256 rows*; therefore 256 refresh cycles must be
An
by a refresh
initiated
are
Refreshes
ms.
4
executed within

array matrices
* The
pattern
rectangular
A

are arranged in a
They
square.
not
are
256 rows by 1024 columns. (See Section
of

3-48

oscillator
time

signal

period

REF

OSC

time

cycles

period.

thus

the

occur

mode

refresh

1is

are

each

0SC)

refresh

cycles)

than

256

well

two

modes

operation:

REF

OSC

cycle

initiates

waits

the

arrays

are

free

SEND

any

(ARRAY

NOT

After

and

new

stated

Table

3-1,

REF

OSC

receive

REF

OSC

This

four

executing
Even

refreshes

the

refresh

four

Battery

than

until

power
only

logic
the

3.3.6.1

wused

during

limit.

and

battery.

inhibit

new

In
The

commands

finish.
refresh

BMAR

SEND

When
cycle

CMD

while

the

MCL.

four

out

MAR4s

the

power

instead

phase

has

the

time

that

time

request.

given

refresh

executed,

used

268

required;

evens

at
a

edge
and

REF

wait

drain

all
0SC

for

may

eight.
not

current

MAR4

short

periods

retain

and

board.

the

mode,

all

the

power
data

mode

interruption
in

commands

Battery

stored

the

are

utilizes

4MBARRAY

banks

arrays

inhibited
separate

to minimize

battery.

-Figure
3-16 is a block
3-17 is a flow diagram of a

figures

REF

(MCL

then

flip-flop

executed.

logic

Mode
Figure
these

battery

are

the

assert

REQ

MAR4

banks

minutes)

REF

four

refresh

drain

leading

input

Any

has

normal

true),

issued

MAR4s

receiving

resumes.

Refer

REQUEST

SET

1is

Normal
logic.

refresh

The

the

ten

the

power

cycle.

refreshes

within

cycles

has

finish will refresh later than one that was free when
OSC. The only refreshes that are simultaneous are

mode

(less

cycle

can

occur
4

OSC

allowing

REF.

refreshes

and

MAR4s

simultaneously.

operation to
it
received
the

commands

REF

3-15)

operation

BUSY

negated

the

CMD

current

four

refresh

within

executes.

other

the

BMAR

for

MCL.

refresh

refreshed

asserts

and

the

Figure

268

MCL,

the

from

(see

request

from

obtained

microseconds

(hence

This

arrays

Refreshes
normal

(REF
14.9

0SC

DIS

REF

thereby

during

clocks

REF

REQ.

the

following

discussion.

flip-flop

causing

REFRESH

REQUEST

asserts

negated).

SET

causing

REF

REQ

REFRESH

diagram of the
normal refresh

REFRESH

fed

REQUEST

back

and

SET

clear

REF

REQ

the

negate.

The

REF

until
enable
Y

Vet R

REQ

the
the

e el

reguest

flip-flop

refresh

cycle

The

input.

has

—

REF

been

SET

REF

REQ

and

SET

SEND

CMD

inhibits

any

new

REF

REQ

asserts;

that

needed

new

made

J-K

true
— —

and

REQ

and

T
T

will

are

hold

from

BMAR

hence,

and
of

CLR
REF

execute

applied
BMAR

from

therefore,

commands

state

then

commands

type;

executes

will

REF

REQ

soon

gate

SEND

CMD.

MCL.

SET

REF

used

assert

the

MCL

are

CMD asserted

negates.

3-49

refresh

arrays

which

BMAR

REQ

inhibited

the

asserted

received

indicates

the

SEND NO

stay

SEND

asserts

BMAR

SEND

sooner.

after

SET

are

asserts
NO

CMD

before
NO

CMD

REF

REQ

REF

REQ

—p

4—14.9
US

|||||||'|||||//||||||||||||||||'|
e

REF OSC

MS=4,000

i
i
|

l
>

268 cycles

!
!

SCLD-381

Figure

REF

delayed

then

REQ

ANDed

with

true

when

delay

CMD

after
REF

the

REF

that

ARRAY

has

asserts

REF

applied
mode.

Approximately

strcobing

required
delay
mode

REF

the
REQ

which

time

the

1is

Don
Nis

noAN
RV,

REF

REQ

the

arrays

for

the

strobing

refresh
to

the

operation

logic.

ANDed

with

A NTTY
nmulng

1is

DAY
PEND

REF

ATHD
CLR

asserted

negation
CMD

row

REF

REQ

ikl
witn

DHRL
REPF

every

The
the
SEND

power-up

start

mode

backup
a

which

backup

power

cold

the

1is

start,
requires

Section

PEND

~AA
LCLiu..LLCU

time

commands

During

not

100

The

refresh

asserts

CLR

REQ

REF

and

negate

geladuse

oTD
LN

completes

any

true state of REF selects
refresh operation.

SET

(Battery

the

flip-flop

4
1is

new

data.

bank

the

into

strobe

establish

reset

battery

The

negated*)

CLK

time.)

asserts

send

refers

gate.

MODE,

array

for

command

initiates

CAS

145

banks

REF

(The

REQ

negates

START

SET

The

started.

REQ

long

REFRESH

MCL

minutes.)
cold

the

too

places

REF

COLD

and

BUSY

BMAR SEND

new

and

MCL

to
a

START

allowing

was

via

REF

bank

COLD

CLK

REQ,;

NOT

refresh.

respond

MODE

completed,

DN
REQ

REF

(MCL

banks

operation (write, read, or refresh).
only the CLR REF REQ associated with
The

CLR

DRI
REF

banks.

refresh

has

refresh

ARRAY

assertion
banks.

array

sequence

DLY

REF.

negated

REF

banks

4MBARRAY

the

REFRESH

the

become

execute

time

then

4MBARRAY

can

not

4MBARRAY

after

the

sequence

allows

and

Periods

assert

had

will

asserts

the

ns
to

because

before

When

100

asserts

MODE,

MODE

and

Time

MCL has
BUSY

REF

refresh

RAS

the
NOT

145

BUSY

free

SET

which

REFRESH

are

asserted.

the

NOT

been

assertion

Refresh

approximately
ARRAY

arrays

insures
and

3-15

CMD

and

then

BMAR

the

MAR4

board.

after

power

outage

to maintain

maintains

array

the

4MBARRAY

that

REFRESH

the

data

banks
be

SEND

that
array

for

ten

into

negated

(see

3.3.2.6).

3-50

3-4)>-

BATTERY

ENABLE

INH_REAL CMD

TTL CLK BM<1J

BAT

-BEE OC

REON
SE
PWR UP
T
_

‘

(Fig.

:D___r,‘:,

(Fig.

»c

D
250

1 |

en saTiERyY

3-9)

RIS

REF

RAS

3-14)

_READ SELECT

SET SEND
b)

16-¢

(Fig.

BMAR SEND

INH

CMD

_REAL CMD

REF_REQ

(Fig.

3-4)

)

¥ ORAY
(100

NS)

CLK REFRESH

‘

(o -9y

SCLD-378

Figure

3-16

Refresh

Block

Diagram

v
% SET REF MODE

REF OSC

100

4 CLK REFRESH

# REFRESH REQUEST

Initiate RAS
sequence
strobing
in 4MBARRAY Banks.

4 SET REF REQ

v
¥ REFRESH REQUEST

¢G-t

v
v SET REF REQ

Banks into
refresh mode.

Refresh completed.

4 BMAR SEND NO CMD

4 PEND CLR REF REQ

160

Piace 4MBARRAY

4 CLR REF REQ

% SET SEND NO CMD

Hold BMAR SEND
NO CMC asserted.

4 REFRESH

Refresh one row
in all four
array banks.

v
4 REF REQ

4 REF MODE

¥ REF REQ

4 DLY REF REQ

ARRAY\ NO

NOT BUSY ::>>—-———

SET REF MODE

¥ CLK REFRESH

¥ REF MODE

¥ SET SEND NO CMD

v
¥ BMAR SEND NO CMD

4 REF

v REFRESH
Return 4MBARRAY
Banks to normal
mode.

Fl‘?.
Figure

2-/7
3-17

)
SCLD-379

Refresh Flow Diagram -- Normal Mode

In
addition,
the
negated
REF REQ bypasses the 145 ns delay and
directly
causes
the
negation
of
SET
REF
MODE, REF MODE, and
REFRESH.
This
promptly
takes
the
4MBARRAY
banks
out of the
refresh mode and returns them to normal operation.

3.3.6.2
Battery
Mode
-- When power is temporarily interrupted,
the memory system automatically goes into battery mode. In battery
mode, the arrays are continuously refreshed in order to retain the
stored
data
until power is restored. Only refresh operations are
allowed
in
battery mode. Read and write operations are suspended
until

normal

power

resumed.

Battery
mode refreshes do not use all of the refresh logic in the
4MBARRAY
banks. In battery mode, only the barest minimum of logic
is
wused
and in its most efficient manner so as to draw the least
amount

Battery
minutes.

power

from

the

battery.

mode refreshes will execute reliably for a maximum of ten
After
that,
the data stored in the arrays 1is no longer

reliable.

The
block
diagram
in
battery
mode.
Figqure

Figure
3-18 is

3-16 illustrates the logic used in
a flow diagram of the battery mode

sequence.,

Upon

sensing
®

)

Sends

impending
no

new

Inhibits
the

loss

commands

new

power,

to the

refresh

the

MCL:

MAR4.

cycles

asserting MCL

DIS

REF

MARA4,

Allows
sufficient
time
operation to complete,.

Places

the

MAR4

(up

675 ns)

for

any

current

into battery mode by asserting BATTERY

ENABLE,

BATTERY

ENABLE

battery

refreshes

asserts
as

INH REAL CMD which prepares

the MAR4

for

follows:

°®

Asserts
RESET ON PWR UP and INH NORM REF to the 4MBARRAY
banks via a J-K flip-flop*.
RESET ON PWR UP disables the
normal
refresh
sequencing
in the arrays,
INH NORM REF
disables the normal RAS refresh logic.

The
time

J-K flip-flop is set by system clock TTL CLK BM<1>. At the
battery mode is entered, power is still available to power

the

clock

1logic and place the MAR4

battery mode,

system

clocks

are

not

3-53

into battery mode.

used

Once

)

Asserts

REF

MODE,

wvia

REFRESH

places

the

arrays

Asserts

SET

SEND

CMD.,

battery

mode

normal

Holds
any

until

the

REF

normal

refreshes
Enables

cycle

CMD

assure

when

flip-flop

the

MCL.,

1logic

1in

and

then

asserted

transistion

That

reset

thereby

ensure

operation.

battery mode

REFRESH.

BMAR

during

back

new

is,

terminated.

also

normal

then
mode,

gate,

stays

returns.

This

orderly

flip-flop

BAT

oscillator

CMD

REQ

until
a

power

and

refresh

via

mode

J-K

gate,

the

battery

back

from

into

SEND

refreshes.

transition

operation

commands
®

BMAR

is
to

That

orderly

is,

new

REF

0SC

terminated.
be

set

Battery

power

the

keeping

MCL

inhibiting
an

the

supplies

the

REF

refresh

0SC

signal

enabled.

Figure

3-19

battery

rising

edge

OSC

SYN.

RAS

1is

assert.

that

BATTERY

4MBARRAY

Due

and

REF

OSC

RAS

logic

REF

row

250

the

inverter,

flip-flop
REF

keeping

flip-flop

become

the

RAS

refreshed.

4MBARRAY

enables
As

seen

battery

RAS

logic

This

action

which

DIS

REF

BATTERY

DIS

REF

RAS

used

the

250

logic

REF

OSC

cycle,

timing

after
in

the

time

for

after

250

ample

RAS

the

resuits

the

along

battery

reduces

seen

trailing
enabled
From
as

the

When

Figure

edge
until

the

second

BATTERY
system

ENABLE

battery

second

REF

cycle

on,

the

returned

1logic

logic

normal

has

starts

the

cycle

0OSC

the

MAR4

assert

battery

after

initiates

MCL

negates

normal

operation,

BATTERY

the

0OSC

REF

returns,

normal

doesn't

hence

INH

until

RAS
REAL

refresh

after

logic
CMD

the

not

asserts.

cycles

long

asserted.

return

BATTERY

O0OSC,

power

after

refresh

REF

remains

executed

battery

3-19,

the

current drain in the arrays and conserves pattery power.
As

STAGEl

banks

the

strobing.

250

the

RAS,

edge

OSC

the

REF

causing

REF

Disabling

until

initiation

BATTERY.

the

1it.

strobing.

only

BATTERY

RAS

DIS

trailing

asserts

the

asserts,

asserting

flip-flop

disables

for

disabled

CMD

applied

disables
the

enabled
Dbe

are

RAS

and

MCL.

initiate

initiated
to

RAS

the

REAL

BAT

clocks

REF

DIS

the

delayed

DIS

being

clocks

involved

INH

from
to

timing

After

and

the

banks

has

OSC

DIS

OSC

diagram,

and

0OSC

while

array

REF

clocks

REF

logic

REF

the

refreshes.,

inverted

OSC

with

1illustrates

mode

one

ENABLE

completed

its

first

1its

and

1logic.

last

refresh.

3-54

DIS

battery

negates

refresh

MCL

REF

operation.

This

refresh

and

refresh

before

from

cycle

control

ensures

before

BATTERY

going

that

the

is
is

the

normal

N
it
sh

normal
requests.
e

y
An
operation is
in progress

YES

4 BATTERY ENABLE

Y
* INH REAL CwD

Hold REF REQ
flip-flop reset
whye

mode.

battery

REF MODE

+ RESET ON PWR UP
Disable normal

refreash

4 SET SEND NO CMD

seguencing

in 4MBARRAY

Banks.

4 REFRESH

Place 4MBARRAY

Banks into g

4 INH

refresh mode.

NORM REF

¢ B

SEND NO CMD

Disable normal RAS

refresh logic in
4MBARRAY Banks.

4 STAGE1 OSC SYN

v
250

% DIS REF RAS

SCLD-365

Figure

3-18

Refresh

Flow

Diagram

3-55

Battery

Mode

(Sheet

EN BATTERY

Enable battery
RAS
logic in 4MBARRAY
Banks.

REF OSC

\4
250

DIS

Disable

REF

Refresh one
in all four
fou
array

RAS

row

banks.

RAS logic.

BATTERY
ENABLE

YES

REF OSC

v
+ STAGE1 OSC SYN

250

Refresh one row
in all four
array banks.

DIS REF RAS

Disable

RAS logic.

+ EN BATTERY
Disabie battery
RAS logic in
AMBARRAY Banks.

v INH REAL CMD

REQ flip-flop.
Release

REF

—--

Diagram

Flow

Refres h

Enable noarmal RAS
refresh logic in
4MBARRAY Banks.

+ REFRESH
Return 4MBARRAY
Banks to normal
mode.

=
3-18

¥ INH NORM REF

¥ REF MODE

D
NO CMD
¥ SET SEN

¥ BMAR SEND NO CMD

Figure

YRESET ON PWR UP
Enable normal
refresh seguencing
in 4MBARRA
Banks

Battery

SCLD-366

Mode

{Sheet

INH

REAL CMD

STAGE1

OSC SYN

DIS REF RAS

—p fi

EN BATTERY

enabled.

NOTE:

250

segments

not

250 NS H

““"

Battery RAS

logic

scale.
SCLD-363

Figure

3-20

battery

STAGE1l

trailing
The

(negating
RAS

SYN

edge

arrays.

the

board

°®

DIS

also

Negating

the

sequencing

the

arrays.

BATTERY

negation

REQ

NORM

being

the

termination
ENABLE

initiates

the

state

false

negated

disables

The

battery

INH

operation

by:

CMD

flip-flop

REF

4MBARRAY
ON

the

Negating

REF

takes

4MBARRAY

the

while

the

BATTERY

last

the

RAS

REAL

CMD

whi

the

MCL to enable

new

allowing

respond

requests.

RESET
in

SYN)
in

Refreshes

MARA4,.

REF

INH

Negating

involved

disables

SEND

the

Mode

RAS.

the

refresh

1in

normal

BMAR

Negating

logic

Releasing
normal

OSC

BATTERY

causes

back

commands

REF

Battery

negation

sequence

results

timing

The

STAGE1l

strobing

OSC

the

refreshes.

negation

MAR4

1Initiation

illustrates

mode

flip-flop
battery

3-19

PWR

array

MODE

enable

the

normal

RAS

refresh

normal

refresh

banks.
UP

enable

the

banks.

which
banks

out

3-57

in
of

turn

negates

REFRESH

the

refresh

mode.

which

———14.9 US —P

— 7,300

REF OSC _j

NS 4—

|
|

STAGE1

OSC SYN

|
|
|
t

|
|

DIS

REF

RAS

ir
|
|
|
|

!:\7'

84—t

BATTERY ENABLE

EN BATTERY

Battery RAS
logic enabled

|
|
|
|

—::{_}l—wzso NS

NOTE: 250 ns segments not to

scale.
SCLD-372

Figure

3-20

Termination

Battery

Mode

Refreshes

APPENDIX A
FLOW-DIAGRAM

X=Description of an event or action (Lower Case).

TPWRFL

The signal PWRFL is asserted (Upper Case).

L PWRFL

The signal PWRFL is negated.

Flow delayed.until CLK. asserts.

CONDITION
or SIGNAL

If condition or signal is true flow
follows yes branch, otherwise flow

follows no branch.

On-page connector.

Off-page connector.

Beginning or ending point of a flow diagram.
MKV85-0511

Figure

A-1

Flow-Diagram

A-1

Symbols

SYMBOLS

EK-KAB88N~-TD-PRE

NBI

SECTION
(NMI

VAXBI

ADAPTER)

CHAPTER

INTRODUCTION

1.1

GENERAL

The

INFORMATION

NMI-to-VAXBI

VAXBI-based

the

(NBI)

1I/0

system.

interconnect

adapter

device

That
(the

interfaces

controllers

1is,

NMI)

Reads/writes
of

NMI

the

device

read/write

VAXBI

the

Allows

NBI

Reads

interrupt

read

transactions

read

NBI

read

the

response

bhe

which
be

expansion
(and

thus

consists

(not

module

the

NMI

four

CPU,

does

means

registers

read/write

means

registers

NMI

the

NBI,

devices.

(The

response

vector

Allows

INTR

data

and

system's

and

NBIA

cabinet.

Each

The

between

the
the

module

(connecting

VAXBI
CPU,

backplanes)

the

that

CPU

and

X 1-1

DMA

backplane

plugs

VAXBI).

1into
A

between

the

NBIA

called

directly

the

backplanes.

and

cabinet

data

1into

and
bus.

the

VAXBI

controllers
CPU

VAXBI

lines

modules
CPU

the

1is

plug

quadword,

NBIB

into

device

may

4+~

Lub}L.

longword.

module

“

interrupt

one

two

NBIB

memory.

response

inter iy

longword,

plugs

connection

cables

t¢

NMI

+he

transactions.)

are

device

NMI).

devices

IPINTR

transfers

NBIA

contains

VAXBI

the

transactions,

transactions

appropriate

interfaced

side)

the

ribbon

the

to/from

The

slot

also

read/write

the

NMI

VAXBI

to/from

the

read/write

transfers)

VAXBI

read/write

Allows

VAXBI

1-1.
it

backplane

consists

(connecting

backplane

transactions.)

transferred

Figure

backplane,

NBIB

and

data
of

the

VAXRI

CPU,

transactions

transfers

adapters

data

(DMA
means

asserts

NBI

CPU

slot

the

IDENT

NBI

blocks.

VAXBI

from

initiates

(The

single

vectors

memory

VAXBI

octaword

shown

vector

Interrupts

can

the

CPU.

in
Device

DMA

NBI

Allows

installed

the

directed

VAXBI

devices,

make

(The

are

transactions.)

Reads/writes
VAXBI

data

interrupt

initiates

NMI

vectors

the

initiates

response

memory

buses.

access

transactions.)
2.

and
that

CPU/memory

VAXBI

registers
(The

CPU

two

transactions,

devices.

transactions

the

adapters

connects

with

following:
l.

and

each
It

back

to two NBIs

can be

(11-slot)

in some

installed

(21-slot)

dual-CPU

having

backplanes.

These are systems

systems.

Systems having a single-CPU

backplane can accommodate only one NBI,

cPU

CPU
0

1
(OPTIONAL)

MEMORY

]

CPU

BACKPLANE

NBIA

NBI

DATA BUS 0

—

_DATABUS 1

(OPTIONAL)

VAXBI 0

e
ADAPT/ |°°°°|

CONT

110

ADAPT/

CONT

Figure

1-1

NBI

AN AL}
E| {GPTIONAL]

110

CONT

170 DEVICE(S)

/0 DEVICE(S)

1/0 DEVICE(S)

ADAPT/ |

|oceo|

VAXBI 1

170
ADAPT/

VAXBI

> > BACKPLANE

1/O DEVICE(S)

VAXBH

BACKPLANE <

\4
1

NBIB

Configuratlon

1.2

PHYSICAL

The

NBIA

that

plugs
2

TTL®

circuit

MCAs.

The

are

RAMs

NBIB

are

F544

VAXBI,

1.3

the

NBIA's

module
1into

two

1l0-layer,

BLOCK

diagram
data

bus

VAXBI
the

used.

NBIB

chip,

called

the

NBI

ECL

interface

ports,

and

interface

the

shown

(to

ECL/TTL

basically

the

To
the

along

chip,
the

buffer).

that
The

components

interface

with

"VAXBI

and

chips

module

Bus

are

latch

backplane.

principal

called

10KH

PALs

RAM

eurocard

in
and

the

Interconnect

VAXBI

1located

clock

corner".

DIAGRAM

consists

This

DC022

FLPAs.)

receiver

module

that

TTL

and

circuit

are

several

VAXBI

the

ECL

transceiver

transaction

300-pin,

(Again,

PALs,

clock

buffer

TTL.

both

components

and

the

associated

interfaces),

transaction

interface

the

(BIIC)

area

(in
port.

uses

Also,

TTL

Chip

buses,

path

integrated

mainly

ECL
F544

module

backplanes,

module

are

slot

are

NBIA

data

extended-hex

dual-CPU

purposes.

and

latches,

and

The

data

ECL

ZMOS

consists
two

principal

control

transceiver

BASIC

block

NBIA

the

chip

reserved

1in

both

480-pin,

the

custom

Interface

driver

for

components

TECHNOLOGY

components

used

have

The

TTL

are

plugs

module

slot

interface

(T1020)

always

9-layer,

components.

that

used

CIRCUIT

backplanes.

principal

that

AND

either

single-CPU

circuits

These

module

1into

slot

FPLAs

DESCRIPTION

(F1011)

has

Figure

allow

the

ECL

interface

VAXBI.

BIIC.

X 1-3

The

1-2,

NMI,

Basically,

TTL

communication

translation
both

TTL

logic

and
to

its

major

TTL

between

and

the

ports.

single

data

component

the

interface

these

DC022

NBIB

bus

port,

the

VAXBI

NBIB
#0

NB(A

ADR/DATA

NMI

—

_ DATA/CTL_PAR

-1 X

ECL 4—{—-5 TTL

DCo22
TRANSACTI
BUFFER ON

UNC )

pco22
CTL
(ECL)

Ml
e o1lL.l cTL

<« PDIPME

—

DATA > <JATA
18us ;~:> e
BUF <POEME
PD/PME
-

aUs o

pcozz | t--T‘ g GTL

(TTL) t—— —1

INIT

AC/DC LO
A/B_CLKS

DATA
BUF

(L)

CLK

(FZCLM—J

LD(TTL)

L CTL

CTL ...
¢«INTA

cTL

8c!

SEQ

—b

BliC

AC/DC 1O

ADR/DATA

<PO

M — T-

g><

4—————CTL———»—-—-»>

CLK

" RESET ‘

o PO/PME

BUS 1

tS R

SYNC
INIT eT

NBIB

]

1a P}

PAR/ J
—pl xLATE

Bl
BUF
o DATA

CcTL

T
CTL

DATA
BUS
BUF

e
a0 bl| ~— e || TRE
BIIC -~|
e | o ——y
DATA
|REGISTERS_
pp—
[
A ——
ot
grrry ~® SLAVE
M‘ INTR
PORT

e1L
INTR_

Bus

—(TTL

ECL)
(ECL)

eTL

cTL

g© ME

-»

SYNG:
XLATE

'T]

o3
%

cTL

INTR

8CLD 421

Figure

1-2

NBI Basic Block Diagram

The

NBIA's
1.

data

NMI

path

data

consists

buffer

transmitted

and

contains

NBIA's

DC022

the

bus

data

for

five

DMA

and

VAXBI1l

the

command/address

data

transferred

(The

transaction
buffers

contains

four

longwords

devices.

VAXBIO

buffering

the

command/address
data

the

buffer

and

data

X 1-5

DMA

locations

longword

either

VAXBIO

are

(one

not
per

by
to

hold

read/write

VAXBI
or

device
VAXRI1l.)

used.
data

latches

transmitted

group

connected

the

the
read/write

second

VAXBI
two

and
buffer

transfers

accesses

transceiver

bus.

for

first

single

locations

Another

CPU

may

Each

the

buffer

sets

Also

16-location
for
the

NMI

four

and

device

the

second.)

when

between
five

provide
the

1-3) -- A
buffering

first

(VAXBIO

address/data

The

transfers

devices.

NBI;

passed

for

transactions.

registers.

provides

data

and

VAXBI1

NMI

(Figure

that

locations

buffering

during

control/status

interfaces.

command/address

following:

Provides

buffer

RAM

command/address
data

the

received

transaction

dual-port

and

bus

for

port)

buffering

received

The NBIR's data path consists of the following:
Data bus buffer -- Similar to the data buffers in the NBIA
contains eight sets of transceiver latches for
but

and

buffering the command/address
received on the data bus.

data

transmitted

and

latches for
BCI data buffer -- Contains two sets of
buffering the command/address and data transferred to/from
(The interface to the BIIC is called the BCI.)
the BIIC.
buffer is located between the data bus buffer
data
BCI
The
and

the

BIIC.

BIIC -- Contains

command/address

separate

the

and

1internal

data

butfers

for

transmitted on the VAXRTI,

Also, it contains VAXBI and BCI control/status registers,
(and showing the
plus other registers for controlling
the BIIC.
by
d
performe
ns
operatio
VAXBI
status of) the
TRANSACTION BUFFER
VAXRBIo

DMA C/A

VAXBI0O

DMA DATAQ

VAXBIO

DMA DATA1

VAXBI0O

DMA DATA2

VAXBIO

DMA DATA3

VAXBI1

DMA C/A

VAXBI1

DMA DATAQ

VAXBI1

DMA DATATt

VAXBI1

DMA DATA2

VAXBI1

DMA DATA3

888885
CPU C/A

CPU DATA
SCLD-410

Figure 1-3

DC022 Transaction Buffer Organization

1-6

1.4

BASIC

The

basic

OPERATION

operations

performed

transfers,

DMA

1.4.1

Read/Write

Data

previously,

one

CPU

stated

allow

is,

the

NBIB.

any

CPU

NMI

received

read/write

the

NBIA)
to

The

address

vector

from

1-4

shows

Figure
NBI

during

transaction
When

NBIA's

the

(both

only

when

VAXBI

complete

command/address
the

sent

VAXBI

to
by

transmitted
the

device

vector

the

NBIB

vector

the

VAXBI
to

the

data

buffer

and

When

control/status

only

transfer

contains

the

data

transaction

VAXBI

and

access

the

NMI

1If

the

reading
perform

a
a

vector

IDENT

command

logic)

the

"in

the

NBIA
vector
VAXBI

collect

the

data

the
be

bus,

VAXBI

only

where

the

(by

NMI

the

within

registers.

X 1-7

the

then

a
interrupt
into

the

buffer,

but
data

transmitted

a
is

transaction).

When

data

1in

the

from

read

transferred

transaction

the

transaction

operation.

read

data

both

command/address

read

NBI,

transaction

transaction).

device)

the

NMI

into

read,

write

the

read

NBIA

the

1in

read

1loaded

end

loaded

the

then

from
and

command/address,
the

loaded

and

1is

write

VAXBI

transaction).

read

read,

1is

write

VAXBI

the

command/address

transaction

operation

are

the

written,

NMI

write

the

transaction)

VAXBI

data

vector

<can

(and
by

and data
through
the
Basic
NMI
and
VAXBI

written,

the

(during

loaded

NBIA

CPU

registers

previously,
device.

control

over

the

transaction

include

read

(during

the

transmitted

initiated
read/write

command/address
operations.

write

BIIC

functions of the NBI
is
to
in the VAXBI devices.
That

stated

the

(during

transmitted

The

also

responds

BIIC

buffer.

Also

and

basic

VAXBI

buffer.

CPU

data

indicated.

the

interrupts.

(during

generated

buffer,

CPU

buffer.

CPU

consisting

transmitted

and

VAXBI

also

transaction

command/address
level

flow

transfers,

transactions.
However,
NBIA can cause the NBIB to

This,

transaction

can

read/write

timing

VAXBI

CPU

the

read/write

VAXBI,

interrupting

CPU

transmitted

the

VAXBI

transaction.

CPU

transaction

connected

are

registers

causes

device

NBI

the

accessed

IDENT

trom

registers

BIIC.

the

Transfers

The

NBIB's own
resulting

the

data

read/write

written,

buffer,

which

the
also

VAXBI
WRITE TRANSACTION

NMI
WRITE TRANSACTION

C/A

WRITE

C/A

——»| CYCLE

CYCLE | DATA

CYCLE

NMI

VAXBI

C/A

NMI

TRANSACTION

VAXB| ADR/ BUFFER

INTR LVL

>
o
| q
<:]§
CSR| ADR
(SELv CSR)

BUS X

DATA

BUFFER

0>
<2S

[cPucra]

CTL

BC|

DATA
BUS

BUFFER

B
<| ¥

NMI

R/W
CMD

NBIB

COMMAND/ADDRESS TRANSFER

NBIA

BUFFER

C/A

\ CYCLE’

{\ADR

READ

”"’w &YeLe | womer [VEOR
CYCLE

0 |

NMI DATA

CYCLE

READ/IDENT TRANSACTION

READ TRANSACTION

‘ CYCLE‘

WRITE

20ece | DATA

[::’
<:j

DATA

1>
-

ADR/

BIIC

BUFFE

INTR LVL
R/W/
IDENT
MD

D L] xiatef

<:|

511G REG

rjl_/r

INTR_LVL]
ADR/

READ/
WRITE

<K N

READ)

LMD

AND

ECTOR

—

]

R/W/

IDENT

SCLD-412

Figure

1-4

CPU

Read/Write

Data Transfer

(Sheet

WRITE

DATA TRANSFER

NBIA

/\rDATA BUPreh

|_DATA

vaxpl

TRANSACTION

DATA

| <]

——

CSR! DATA

BUFFER

NBIB

BUS X

BUFFER
DATA

w5
Bl

BCI

BUFFER

BUS

=
-

DATA

BUFFER

CTL

P XLATE

=T X

NMI DATA
——bUrFER

TRANSACTION
VAXBI
DATA/
BUEFER

)
M—
]
VECTOR

CSR! DATA

{

RETURN

ER§AX
BUFFER

READ

‘4

DATA/VECTOR

|
/}

BIIC

TRANSFER

;

DATA
BUS
BUFFER

%ET'A
BUFFER

N
<

CTL

DATA

2K
<§‘

DATAL

BlIIC

<STATUS

BLIC

XLATE

STATUS

]

ECTOR)

CTOR

DATA/
(

READ

PYECIOR_N

AND

_|>

NEIB

x Kb
§

[}

WRITE

NBIA

—
MASK

MASK

DATA

[}

NMI

/\ DATA/ !
VECTOR

L1
<

BIIC

DATA

>
A

[=—=w—m==q/
| STATUS.

RTN

DATA
SCLD-413

Figure

1-4

CPU

Read/Write

Data

Transfer

(Sheet

1.4.2

DMA Read/Write Data Transfers

A VAXBI device can directly access the system's main memory
a VAXBI
1is,
That
through the NBI.
(connected to the NMI)
to a
directed
and
read/write transaction initiated by the device
NMI
required
the
memory address causes the NBI to initiate
a
within
fall
must
(The memory address
read/write transaction.
the
in
registers
address
range specified by starting and ending
BIIC.) The NMI transaction is the same length (longword, quadword,

or octaword) as the VAXBI transaction with one exception. There is
so a VAXBI read quadword
no NMI read quadword transaction,
transaction causes the NBI to do an NMI read octaword transaction.
The addressed quadword in the octaword of data read from memory

then returned to the device.

Figure 1-5 shows the flow of command/address and data through the
Durlng the VAXBI
operations.
read/write
DMA
during
NBI
transaction, the command/address received by the BIIC is loaded 1in
the NBIB's data bus buffer and then transferred to the NBIA's data
buffer over the data bus. Also, if the transaction is a write, the
(up to four longwords) is loaded in the NBIB's data
write data
After 1its
buf fer and transferred to the NBIA's data buffer.
(and write data) 1s
the command/address
transfer +to the NBIA,
written in the transaction buffer and the NMI read or write
transaction

initiated.

If the NMI transaction is a write, the command/address and write
data are read from the transaction buffer and transmitted on the

If the NMI
NMI to end the memory write data transfer in the NBI.
transaction is a read, and after the command/address is transmitted
(up to four
on the NMI, the memory returns the memory read data
to the NBIA where it is written into the transaction
longwords)
1is read from the transaction buffer,
Then the data
buffer.
transferred to the NBIB over the data bus, and transmitted on the
VAXBI by the BIIC to end the memory read data transfer in the NRI.

NMi

WRITE TRANSACTION

VAXB!

WRITE TRANSACTION

OR 4

[4— DATA' CYCLES —]
C/A

WRITE

CYCLE | DATA
CYCLE

OR 4

|ooo. | WRITE
CYCLE|

[4— DATA'CYCLES

WRITE

|[o» oo |DATA | € ——CYCLE

GYCLE

NMI_READ TRANSACTION

|oooo | paliE
CYCLE

VAXB| READ TRANSACTION

4
1 OR
DATA CYCLES

&Re | Data
R

B&TA

20l

&YoLe I

‘,__,7

—_

‘ «4— DATA
1.2, CYCLES
OR 4
©

READ

DATA

CYCLE

NBIA

TI-T X

TRANSACTION

ADR

NMi

BUS X

BUFFER
DATA

PN
K
N

[DMA C/A]

_——

| READ
1

DATA

I CYCLE

COMMAND/ADDRESS TRANSFER

BUReRRT
BUFFER
e
> ] Ky
Kq
|ATA

[92]

NMI
cTL

NBIB

DATA

BCI

BURFER
>
-

BUFFER
>
-

BUS

‘

>
g

BIIC

DATA

VAN
ADR

dal

R/W

CMD

Q
_

— XLATE |

R/W
CMD

SCLD-414

Figure

1-5

DMA

Read/Write

Data

Transfers

(Sheet

NBIA

TRANSACTION

BUFFER

NMI_DATA
72N DATA __ BUFFER

WRITE_DATA_TRANSFER

BUS X

DATA
BUFFER

KB b K=. ’C*@*D
— Il ova Do

BURren

-9
<¢ - —
.

DMA D2
DNA D3

E:j

BC| _

DATA

NBIB

L1
|

BIIC

DATA
BUFFER

)

DATA

MASK

D - !
17 i

o
>
N5

i
<t@ L FUNC

NMI
cTL

VAN

L8(1ST_LW)
L10(2ND LW)
L12(3RD LW)
LE(4TH LW)

MASK

|
|

RETURN

READ

DATA TRANSFER

NBIA

’

DATA

TRANSACTION

| NMI DATA

BUFFER

> Ty A

DMA D1DO
Q q ‘ —p| DVA

DVA D2

NBIB

BLS X

BUFFER

L’S‘F
<]

<®

NMI
CTL
STATUS

BitC

-4:>>

STATUS

pi
z

» FUNC|

L5(1ST LW)
L7(2ND LW)
L9(3RD LW)
LIT(4TH LW)

Figure 1-5

DATA

—

BF>
g <:]

»@}
<

]

BUFFER

DATA

BUFFER

DMA Read/Write Data Transfers

SCLD-415

(Sheet 2 of

1l.4.3
The

Interrupt

NBI

fields

request

may

Operation

CPU
be

interrupt
due

requests

VAXBI

INTR

the

VAXBI

devices.

transaction

device

The

conventional

interrupt
request)
or
a
VAXBI
IPINTR
transaction
(an
interprocessor
interrupt
request).
n
interprocessor interrupt
request differs from a conventional 1nterrupt request in that it is

originated
an

by one processor and directed to another.
For example,
processor on the VAXBI can direct an IPINTR
transaction
to

I/0

the

NBI

and

thus

interrupt

the CPU.
Another difference is that no
by means
of
a
VAXBI
IDENT
transaction
following
the
interrupt.
That
1is, vector (and interrupt level)
information is stored in
the
interrupted
processor.
Basic
NBI
operation
in response to an INTR or IPINTR transaction is shown in
Figure 1-6.

interrupt

vector

When

NBIB

the

interrupt
the

data

(its

logic
bus

read

BIIC)

connecting

request

signal

1is

specify

wup

four

different
lowest.)

interrupt

the

transaction)

level,

other

and
INTR

When

the

bus,

NBIA

(and

(local)
When
a

and
to

BIIC.

Also,

asserted

also

CPU

asserts

NMI

that

can

requests

ready

indicate

generated

corresponding

the

VAXBIs)

are

from

service
in

NMI

interrupt

the

NBIA.

priority

transaction

the

CPU.

(When

its

own

IDENT

and

internal

NBI

interrupt

the

NBIB's

IDENT

taking

the

NBIA.

All

system's

SCBB

contains

the

There

three

are

generate

dispatch
basic

and

BIIC

vector

place

types

read

for

in
the

vectors,

1-13

NBI

by
the

the

These

CPU

IDENT

returned

responds

the

CPU.)

are
(The

returned

added
SCB

service
in

reads

already

VAXBI

vector

SCB.

NBIBs

Interrupt

BR4

shown

two

vector

interrupt

two

interrupting,

the

interrupt

vector

level,

device

line
higher

request,

device,

(BR)

is returned

and

address

data

request

itself.

VAXBI

interrupt,

vectors

address

NBIB

(local)

with

CPU

NBIA

There

interrupt

the

NBIA.

the

any

the

The

level.

BR4

level

the

interrupt
by

BR4

the

executed

a
like

request

priority.

either

INTR

one

asserting

the

(an

at
bus

than

interrupt

connected

each

read

1is

data

encoded

request

already

the

locally,

are

address

NMI
not

when

the

(if

request

interrupt

transaction,

request
on

interrupt

priority

described,

the

IPINTR

interrupt

signal

asserts

signals

one

INTR transaction can
(BR<7:4>),
each
at
a
highest priority, BR4 the

This

request

CPU)

lines

vector

the

VAXBI

asserted

then

the

interrupt

the

signal

thus

requests

own

transaction,

single

conventional

resolves

request.

requests

NBIB's

asserts

has

INTR

request

Normally,

requests

(BR7

VAXBI

interrupt

NBIA.
but

receives

forces

detects

asserted)

NMI

level.

the

first

priority

the

transaction.

(connected
other

interrupt

NBIB

logic

one

asserted,

priority
When

receives

asserts

Figure

the

location
routine.)
1-7.

NBIA

TRANSACTION

—
BIIC

NN/

BUFFER

Y29

NMI
CTL

INTR
LVL/

MASK

tgflfifiz

IPINTR
CAUSES
Biic .

FUNC

INTR

INTR
LVL=BR4
NebistAbad AN
VL )

el oSN

INTR
LVL

<« BRX

|
INTR_

/NININ

NMI

T-T X

BUFFER

8X?Ax

INTRJEHQELA
SCLD-4186

Figure

1-6

INTR/IPINTR Operation

NBI

VECTOR

(LOCAL

INTERRUPT)

BR4

00000

LEVEL

L 1000(NBI0)

1100(NBI1)

100(BR4)
VAXB!

DEVICE

VECTOR

(OFFSET)

BRX

VAXB!

NON-ZERO
Non
ze

DEVICE

VECTOR

VECTOR (NO

OFFSET)

00000

BR LEVEL

YAXBI

VECTOR OFFSET

CSRO

A4
14

BRX

10]

NBI VOR

09 | 08

PRVEL

HA N

0(VAXBI0)
1(VAXBI1)
SCLD-411

Figure

1-7

Interrupt

X 1-15

Vector

Format

(local)

The first type of vector is the NBI

interrupt

vector.

depending on which NBIA is
(hex)
130
120 or
a value of
has
can be
two NBIs
previously,
stated
(As
vector.
asserting the
page 0
SCB
an
is
value
vector
NBI
The
systems.)
some
in
installed
and
architectural
for
reserved
is
0
page
This is because
address.
NMI device

(nexus)

vectors.

(The NBIA is an NMI device.)

«consist

The other two types of vectors read by the CPU both
vector

device

and a higher order

(nonzero)

vector offset.

In one

In
case, the offset (bits <13:9>) is supplied by the VAXBI device.
<13:9>
bits
(when
NBIA
the
by
supplied
1is
offset
the
other,
the
from the device equal zero).

The NBIA supplies the offset for most

the DWUBA (VAXBI to
as
such
adapters
However,
devices.
VAXBI
an
sent with
vectors
The
offset.
UNTBUS adapter) supply their own
bus
other
the
on
interrupting
are from the devices
offset
adapter
in the case of the DWUBA).

(the UNIBUS,

Offset values are previously

loaded

and

device

NBIA

vector

(The NBIA's vector offset register is
offset registers by the CPU.
an
supplying
that devices
so
chosen
are
values
in CSRO.) Offset
with
starting
device,
per
SCB
the
in
page
are allocated one
of fset
Then,

page 1.

following these pages and

starting

with

the

even page (this may leave an unused page), an SCB page 1is allocated
offset.
an
supplying
not
VAXBI
for the devices (nodes) on each
the
like
adapter
an
because
devices,
the
all
1is
this
Actually,
interrupt
also
can
CPU)
the
to
DWUBA (which passes UNIBUS vectors
a VAXBI node (BIIC detected errors, etc.) and send an internal
as
vector

the

CPU.

Figure
in
An example of SCB page allocation for a system is shown
the
of
one
and
3)
and
2
(pages
two VAXBIs
has
system
The
1-8.
VAXBI

nodes

is a DWUBA

(page

1l).

SCB PAGE

ARCHITECTURAL AND NMI NEXUS VECTORS

OFFSET (UNIBUS) DEVICE VECTORS FOR DWBUA

VAXBI0O NODE VECTORS

VAXBI1 NODE VECTORS

3
SCLD-417

Figure

1-8

SCB Format

(Example)

1.5

NBI

REGISTERS

Six

registers

the

BIIC)

also

contains
to

NBIA

and

four

operations.)
used

the

control
In

and

show

thirteen

the

status

general-purpose

the

indicate

registers
of

NBI

the

NBIB

(in

(The

BIIC

1in

NBI

registers

descriptions

bit

Cleared

goes

when

from

DCLOL

Loaded

DCLOS

Set

when

DCLO

asserted

read/write

DCLO

asserted

goes

from

DMW

BIIC

INITC

Cleared

Read-Only.

R/W

Read/Write.

R/W1C

Read/Write

clear.

STOPC

Cleared

VAXBI

STOP

STOPS

Set

1.5.1

when

VAXBI

Cleared

UNJAMC

The

diagnostic

NBIA

status

reserved

UNJAM

(NBIB

are

other

when

registers).

deasserted

state.

writeable.

ADAPTER

STOP

codes

and

registers)

state

asserted

used

focllow,

INIT

(in

CSR1l)

set.

command.

console

command.

Registers

registers

1-1.
The
read/write

mode

(NBIA

deasserted

not

that

information.
DCLOC

operations.

the

NBIA

registers
(longword)

and

not

(NMI

nexus

are
accessed
transactions.

currently

registers)

Two

are

the

CPU
register

listed

Table

means of
addresses

NMI

are

used.

Table

1-1

NBIA

Registers
NMI

Address

(Hex)

Read/Write

Control/Status

(CSRO)

2X08

0000

Control/Status

R/W

(CSR1)

2X08

0004

R/W
-

Reserved

(RSVDO)

2X08

0008

Reserved

(RSVD1)

2X08

000C

(BR4VR)

2X08

0010

BR4

Vector

BR5

Vector

(BR5VR)

2X08

0014

BR6

Vector

(BR6VR)

2X08

0018

BR7

Vector

(BR7VR)

2X08

001cC

Note:

(NBIA

X 1-17

1.5.1.1 Control/Status Registers (CSRO and CSR1) -- The NBIA has
two control/status registers. Bit format is shown in Figures 1-9
Register bits are defined in Tables 1-2 and 1-3.
and 1-10.

CONTROL/STATUS REGISTER ¢ (CSRO0)

0|0

2X08 0000

09 08 07

1514
18 1716 19
31302928 2726 252423222120

0001 0000

010

]

NB!

L- ADAPTER CODE
VECTOR QFFSET

—— NB! DATA PARITY ERROR
-——— B!IC LOOPBACK

FORCE NBIA PARITY ERROR

FORCE DMA BUSY
FLIP

NBI

2g/22

INTERRUPT ENABLE

TIMEOUT <0>

TIMEOUT <1>

TIMEOUT

<2>

TRANSMITTER DURING FAULT
WRITE SEQUENCE FAULT
READ SEQUENCE FAULT

CONTROL PARITY FAULT
DATA PARITY FAULT
SCLD-423

0 ¢]

[

Control/Status Register 0

Figure 1-9

(CSRO)

Table

1-2

Control/Status

Bit(s)

Name

<31>

DATA

PARITY

FAULT

(DPF)

(CSR0O)

Bit

Descriptions

Description
Indicates
NMI

bad

ADDRESS

parity

DATA

detected

lines

(RO,

for

DCLOC,

INITC)
.
<30>

CONTROL

FAULT

PARITY

(CPF)

Indicates
NMI

DCLOC,
<29>

READ

FAULT

DATA

SEQUENCE

(RDSF)

<27>

WRITE

DATA

FAULT

(WDSF)

TRANSMITTER

FAULT

SEQUENCE

DURING

DCLOC,

Indicates
NMI

(TDF)

NBIA

unexpected

(RO,
<28>

parity
and

detected

MASK

for

lines

(RO,

INITC).

Indicates
or

bad

FUNCTION

write

received
NMI

read

data

INITC).
NBIA

data

received
(RO,

Indicates

NBIA was

NMI

was

fault

incomplete

return

incomplete

DCLOC,

INITC).

transmitter

detected

(RO,

when

DCLOC,

INITC).
<26:24>

TIMEOUT

INTERRUPT

Indicate

timeout

Cause

NBIA.

interrupt

INITC).

condition

NBIA

request

Writing

(R/W1C,

any

detected

generate

bit

CPU

DCLOC,

clears

all

three.
TOI

<2:0>

Read

Data

Timeout

000

None

001

Reserved

010

Reserved

Read

100

Response

101

Bus

Access

Timeout

Data

110

Interlock

111

Busy

Command/address
start

NMI

acknowledged

Response

Interrupt)

011

(No

but

was

NBIA

continued

Timeout
Timeout

Busy

Timeout

transmitted

read

data

Timeout

by NBIA

transaction
no

return

was

read

received.

receive

acknowledgment for the command/
address transmitted during retries
of

NMI

response
retry.

X 1-19

write

was

transaction.

received

during

last

Table

1-2

Control/Status
Bit

Bit(s)

Name
Bus

Descriptions

(CSRO)

the

NMI

the

bus.

receive

(Cont)

Description
Access

Timeout

NBIA

requested

granted
Interlocked

NBIA

Busy

Timeout

use

continued

acknowledgment

address
of

for

the

transmitted

NMI

but

INTERLOCKED

response

retry.

normally

because

response

does

during

retries

was

received

(Cannot

not

command/-

transaction.

last

was

occur

INTERLOCKED

not

normally

receive

cause

retry.)

Busy

Timeout

NBIA

continued

acknowledgment
address
of

for

the

transmitted

NMI

response

write
was

command/-

during

retries

transaction.

received

during

BUSY

last

retry.

NOTE

Timeouts

occur

after

(approximately

<21>

[

two

system

normal

slow

clock

periods

system

clock

rate).

RESERVED

Not

NBI

Enables

INTERRUPT

ENABLE
<20>

(NIE)

RESERVED
T

T TM

FLiY

oWV A

49/22

<23:22>

{FLIP)

used

Not

(RO,

used

Diagnostic

a
a

<22>

memory

(FDB)

(DMA)

bits

<29>

causing

VAXBI

address

read/write

(R/W,

control

DCLOC,

error
BIIC

UNJAMC)
.

bit.

operation

normally.

timeout
NBIB's

controil

address

NBIA

address

read/write

ending

UNJAMC).

Diagnostic

DMA

interrupt

INITC,

transfer

NMI

the

CPU

ZERO).

read/write

generate

INITC,

BUSY

make

DCLOC,

data

Switches

CPU

DMA

(R/W,

and

FORCE

NBIA

ZEROS).

requests

bit.

<18>

(RO,

(R/W,

Causes
be

Prevents

from
stall

detected

DCLOC,

INITC,

Table

Control/Status

1-2

Bit

Bit(s)
<17>

Descriptions

Name
FORCE

NBIA

ERROR

(FAPE)

PARITY

Diagnostic
the

NBIA

and

BIIC

LOOPBACK

(BILP)

line

parity

data

DATA

ERROR

PARITY

(NDPE)

control

read/write
by

loopback

DCLOC,

its

and

NMI

DCLOC,

NBIB's

BIIC

(R/W,

detected

information

NBIA

interrupt

Causes

UNJAMC).

NBIA

for

bit.

transactions

the

internal

Causes

data

the

(R/W,

requests

INITC,

Indicates
parity

buses

Causes

bad

UNJAMC).

generated

bit.

transmit

Diagnostic
VAX

NBIA

control

both

INITC,

<15>

(CSRO)

Description

control

<16>

(Cont)

bad

data

read

from

transaction
to

generate

request

buffer.
CPU

(R/W1C,

DCLOC,

INITC).
<14:9>

NBI

VECTOR

(NBIVO)

OFFSET

<14:9>

Offset

value for VAXBI device
interrupt vectors not already

offset.
DCLOC,

<8>

RESERVED

<7:0>

ADAPTER

(NAC)

Not
CODE

<7:0>

X 1-21

Bit

<9>

must

INITC).

used

(RO,

ZERO).

(R/W,

CONTROL/STATUS REGISTER 1 (CSR1)

12 1110 09 08 07 06 05 04 03 02 01 00

16 15

0000 ---- 0000

2X08 0004

NBIA MODULE REVISION—
FRC NBIB PARITY ERROR—

NBIA WRAPAROUND——
VAXBI1 POWER UpP—————
VAXBI0 POWER UP—

NBIA FUNCTION PARITY ERROR
NBIB VAXBI1 PARITY ERROR
NBIB VAXBI1 PARITY ERROR—
NBiB VAXBI0 PARITY ERROR—
VAXBi1

PRESENT

VAXBI0O PRESENT
ADAPTER INIT
SCLD-424

Figure 1-10

Table 1-3

Control/Status Register 0

(CSR1)

Control/Status Register 1 (CSR1) Bit Descriptions

Bit(s)

Name

Description

<31:16>

RESERVED

Not used (RO, ZEROS).

<15:12>

NBIA MODULE REVISION

NBIA module (hardware) revision

RESERVED

Not used (RO, ZERO).

<11>

<10>

FORCE NBIB PARITY

ERROR (FBPE)

level

(RO).

Diagnostic control bit. Forces

each NBIB to generate and detect
bad parity

its

internal data

path (R/W, DCLOC, INITC, UNJAMC) .

<9>

NBRIA WRAPAROUND
(NAWR)

Diagnostic control bit. Causes

CPU read command/address to be
locoped back through the NBIA
data bus buffers and returned

CPU as read data
INITC,

<8>

RESERVED

UNJAMC).

* Not used (RO,
X 1-22

(R/W,

ZERO).

DCLOC,

Table

1-3

Control/Status

Bit

Bit(s)

Name

<7>

BI1

Descriptions

POWER

(BI1PU)

Indicates

POWER

(BIOPU)

FUNCTION

ERROR

(NFPE)

PARITY

and

VAXBI

NBIB

initialization.

generate

CPU

DCLOC,

have
1

after

Causes

interrupt

NBIA

request

INITC).

Indicates DC LO and AC LO have
been deasserted on VAXBI 0 after
NBIB initialization. Causes NBIA
generate

(R/W1C,
NBIA

deasserted

<5>

been

(R/W1C,
BIO

(CSR1)

Description

<6>

(Cont)

CPU

DCLOC,

interrupt

request

INITC).

Indicates

NBIA detected bad
parity for information
from its internal trans-

control

read

action buffer. Causes NBIA to
generate CPU interrupt request

(R/W1C,

<4>

NBIB

BI1

ERROR

PARITY

(BOPE)

DCLOC,

Indicates

NBRIB

parity

its

Causes

NBIA

interrupt

INITC).
1

detected

bad

internal

data
to generate CPU

request

(R/W1C,

path.

DCLOC,

INITC).
<3>

NBIB

BIO

ERROR

PARITY

(B1PE)

Indicates
parity in
Causes

BI1

PRESENT

(BI1lP)

Indicates

the NBIA
VAXBI is
<1>

BIO

PRESENT

(BIOP)

Indicates
the

NBIA

VAXBI
0>

ADAPTER

INIT

(ADIN)

its

NBIA

interrupt
INITC).
<2>

NBIB

and
not

X 1-23

bad

data

generate

(R/W1C,

path.

CPU

DCLOC,

connected

BI DC LO on the
asserted (RO, DCLOS).

NBIB

is
DC

connected

and

not

asserted

NBIA,

VAXRBRI

self-clearing

INITC,

detected

request

Initializes
connected

internal

UNJAMC).

(RO,

NBIB(s),

devices.

(WO,

the

DCLOS).

and

This

DCLOC,

bit

1.5.1.2

four

Vector Registers

vector registers:

(BR4VR

through

BR7VR)

The

BR4VR, BR5VR, BR6VR, and BR7VR.

NBIA

has

(Refer to

Figure

1-11.) When the NBIA is making a CPU
interrupt
request
at
some request level (BR4, BR5, BR6, or BR7), the CPU microcode reads
the interrupt vector by reading the corresponding vector
register.
Vector
format,
which differs depending upon the type of interrupt
request, is discussed in Section 1.4.3.
The

vector registers are read-only registers.
Zeros
are
returned
(to
the
CPU)
1if
an error is detected by the NBIB when reading a
VAXBI vector.
(The NBIB's BIIC posts an interrupt request to
flag
the error.) Also, zeros are returned if the interrupt request is no
longer pending.

BR4 VECTOR REGISTER

(BR4VR)

2X08

15 14

0010

0000

BRS VECTOR REGISTER

----

0000

BR4

VECTOR

(BRSVR)

15 14

2X08 0014

0000 ----

0000

BR5 VECTOR

BR6 VECTOR REGISTER (BR6VR)
31

2X08 0018

0000

BR7 VECTOR REGISTER

----

0000

BR6 VECTOR

(BR7VR)

2X08 001C

0000 ----

0000

BR7 VECTOR
SCLD-425

Figure

1-11

Vector

Registers

(BR4VR

through

BR7VR)

1.5.2
The

NBIB

(BIIC)

NBIB's

BIIC

implemented
or

may

not

the

NBIA

CPU

is,

the

NMI

its

nodes,

registers,
of

the

NMI

1-4.

the

BIIC

can

also

node)

normally

associated

node.

NBIB's

BIIC

access

accessed

means

done,

because

1-4

NBIB

(BIIC)

Bus

(DTYPE)
(BICSR)

(BER)

Interrupt

Control

Destination

{(IPINTRMSK)

IPINTR/STOP

Destination

Source

Starting

Ending
BCI

(FIPSDES)

(IPINTRSRC)

Address

(SADR)

(EADR)

Control/Status

Write

Status

Force

IPINTR/STOP

User

(EINTRCSR)

(INTRDES)

Mask

IPINTR

that

may

all

the

NBIR

uses

are

accessed

VAXBI

(BCICSR)

(WSTAT)

Interrupt

Command

Control

(FIPSCMD)

(UINTRCSR)

transactions.

the

device

processor

Registers

Read/Write

R/W

(GPRO)

General-Purpose

(GPR1)

General-Purpose

Not

used

(GPR2)

Not

R/W

used

General-Purpose

(GPR3)

R/W

Not

used

R/W

(bb)

for

Base

address

Not

NMI

used

address:

2000

0000

(hex)

2000

(hex)

2200

node

0000

(NBIA

(hex)

2000

NBIB

(hex)

2400

node

0000

1iD

(hex)

(NBLA

2000

NBRIB

(hex)

2600

node

0000

(NBIA

(hex)

2000

NBIB

(hex)

node

(NBIA

NBIB

node

Base

address

2000

NBIB's

read/write

NOTE:

The

VAXBI

General-Purpose

(bb)

0000

for

(hex)

VAXBI

2000

address:

(hex)

X 1-25

by
That

read/write

registers.

(Hex)

Error

IPINTR

registers

Address

Control/Status

Error

the

are

connected

NBIB

own

VAXBI

the

transactions.

cause

its

located

that

registers

transactions
that

are

registers

(The

(longword)

VAXBI.

Table

VAXBI

All

required

BIIC—-specific

read/write

read/write
by

VAXBI
not

VAXBI

Table

VAXBI

implemented

means

registers

This
on

all

either

registers.)

the

transactions

listed

are

(another

are

and

BIIC-specific

BIIC

Registers

registers

node

1.5.2.1
1-12)
the

Device

contains
VAXBI

node.

jumper-selectable
At the same time,

loaded.

loads

that

value

can

written

This

necessary

selftest

occurs

loaded

the

Table

1-5.

code

the

The

and

NBIB,

Then,

during

identifies

system

the

powerup)

BIIC

with

will

by
1s

(Figure

identify

revision

<code

This

selftest

not

pass

1its

value

selftest

definitions

software

all

are

1ls

still

given

1615

bb + 0

1is

hardware at powerup.
(a default value) is

NBIB.

default

bit

code

initialization,
an

BIIC

the

type

module

loaded
of all

node

software when

because

the

device

the

and automatically
a device type code

automatically
a

(DTYPE)

revision

DEVICE REVISION

DEVICE TYPE
MLO-034-85

Figure

Table

1-5

Bit(s)

Name

<31:16>

DEVICE

1-12

Device

REVISION

Indicates

Bit

TYPE

Descriptions

loaded

device
then

DMW,

type

code,

code

VAXBI

device.

loaded

DCLOL).
VAXBI

powerup
equal

loaded by
initialization

X 1-26

level

revision

(R/W,

Indicates

are

revision

module's

powerup
DEVICE

(DTYPE)

Description

NBIB

<15:0>

NBIB,

0106

software

(R/W,

node.

All

The

(hex),

1's

NBIB
is

during system
DMW, DCLOL).

1.5.2.2

VAXBI

Controcl/Status

control/status
described

Table

{BICSR)
Figure

-- Th

1-13.

VAXBI
Bits

are

1-6.

24 23

161514131211109

bb + 4

VAXBI INTERFACE REVISION |
CE
TYPE
VAXBIINTERFA
HARD ERROR SUMMARY

SOFT ERROR SUMMARY
INITIAL!ZE
BROKE

SELF-TEST STATUS

NODE RESET

UNLOCK WRITE PENDING
HARD ERROR INTR ENABLE

SOFT ERROR INTR ENABLE
ARBITRATION CONTROL
NODE ID
MLO-035-85

Figure

1-13

VAXBI

Control/Status Register

X 1-27

(BICSR)

Table

1-6

VAXBI

Control/Status Register
Bit

(BICSR)

Descriptions

Bit(s)

Name

Description

<31:24>

VAXBI INTERFACE
REVISION (IREV)

Indicate the revision level of
primary interface to the VAXBI
BIIC)

<23:16>

<15>

Indicate the primary interface
Equal to 01 (hex) for the BIIC

HARD ERROR
SUMMARY (HES)

Indicates that one or more of the hard
error bits in the bus error register 1is

SOFT ERROR
SUMMARY (SES)

INITIALIZE

(INIT)

BROKE

(RO).

Implementation dependent.
NBIB

12>

type.
(RO).

Indicates that one or more of the soft
error bits in the bus error register is
set

<13>

(RO).

VAXBI INTERFACE
TYPE (ITYPE)

set

<14>

the
(the

(R/W1C,

Indicates

DCLOS,

node

has

Not used

1in

STOPS).

not yet

passed

its

selftest. Only the BIIC performs a
selftest in the NBIB (R/W1C, DCLOS).

<11>

SELF-TEST
(STS)

STATUS

Indicates the BIIC
test (R/W, DCLOS).

has

passed

its

self-

Table

1-6

VAXBI

Bit
Bit(s)

Name

<10>

NODE

Control/Status

Descriptions

RESET

(NRST)

Clears

SELFTEST

BIIC's
which

<8>

RESERVED
UNLOCK

PENDING

WRITE

(UWP)

BIIC

BCI

ERROR

ENABLE

C<6>

SOFT

INTR

(HEIE)

ERROR

ENABLE

INTR

(SEIE)

Not

used

(RO,

Indicates

the

completed

(IRCI)

node

(the

NBIB)

write

but

node

(the NBIB)

error

interrupt

STOPC).

Enables

the

node

generate

error

SUMMARY

Determine

(the

node's

(R/W,
<5:4>

NBIB)

<14>)

HARD

set

(R/W,

(NBIB's)

Arbitration
e

————

———

when

SOFT

set

(R/W,

Dual
Fixed

high

Fixed

low

Arbitration
arbitration

inhibited

from

corresponding
arbitration
bus

Indicate

——

—

——

round-robin

priority
priority

disabled

disabled,

asserting
its

cycles.

node

1is

line

node

during

Thus,

can

never

master.

node's

powerup

inserted

arbitration

Mode

————

X 1-29

interrupt

become

to
when

DCLOC).

—

DCLOC).

<15>)

(bit

STOPC).

mode

When

not

(UWMCI)

(bit

has

interlocked

transaction

DCLOC,

This

ZERO).

lock

SUMMARY

asserted,

DCLOC).

the

CONTROL

1ID

NBIB.

Enables

ARBITRATION

NODE

generate

ARB

<3:0>

logic

(W0,

and

causes

output

successful

ERROR

<11>)

Also

(R/W1C,

DCLOC,

(ARB)

(bit

transaction

ERROR

<5:4>

self-clearing

subsequent

HARD

STATUS

selftest.

initializes

bit

read

<T7>

(BICSR)

(Cont)

Description

initiates

<9>

and

ID.

NBIB's

determined

backplane

(RO,

ID
by

loaded
ID

DMW,

plug

DCLOL).

1.5.2.3
Bus Error Register
1-14)
indicates any hard or
VAXBI
<2:0>

transactions.
are

the

soft

(BER)

—--

The

soft

errors

Bits

<30:16>

are

error

bits.

bus

error register (Figure
by the BIIC during

detected

the

(Hard

hard

errors

error
abort

bits,

bits

transaction,

soft errors do not.) The register also contains a bit that
1is
not
an
error
indicator.
This is bit <3>, which indicates the BIIC's
parity

mode.

Table

Bit(s)

1-7

bits

Bus

are

Error

defined

Bit

Name

Description

<31>

RESERVED

Not

<30>

NO ACK

received

COMMAND

STOP,

RECEIVED

CHECK

TRANSMIT

ERROR

(MTCE)})

bus

master

ACK

the

node

ERROR

PARITY

(MPE)

INTERLOCK

SEQUENCE

ERROR

(ISE)

when

the

node

Indicates

node

UWMCI

corresponding

previously

(or

when

error

vector)

on
ACK

NBIB)

successfully

transaction
transaction

(R/W1C,

has

1-30

{(R/W1C,

no
been

DCLOC).

a parity error during a cycle when
was responsible for transmitting

parity

(the

when

DURIONG

correct

bus

the

DCLOC).

Indicates

FAULT

node

attempting
DCLOC).

TRANSMITTER

(TDF)

the

DCLOC).

NBIB),

parity

(the

IRCI

was

(R/W1C,

(the

read

completed

(R/W1C,

node

Indicates

(R/W1C,

data

(the NBIB) detected
CNF <2:0> was

signal

during

the

when

the

detected

samples
lines

the

from

transmitted

the

assert

cycle

transmit)

Indicates the node
NO ARB, BUSY,

issued
<25>

BIIC

that

data

differed

and

source

compares

VAXBI

26>

only

master,

transmitted

(The

NBIB)

command

NBIB)
I,

the

deasserted

MASTER

data

(the

received.

the

(the

response

IPINTR

intended

<27>

that

and

CONTROL TRANSMIT
ERROR (CTE)

ZERO).

data

28>

Descriptions

DCLOC).

Indicates

VAXBI

1-7.

the
a

INTR,

(R/W1C,

MASTER

(RO,

Indicates

MULTIRESPONDER

(NMR)
<29>

used

Table

NBIB)

DCLOC).

detected
it

Bus

Error

Bit(s)
24>

Bit

IDENT

VECTOR

Indicates

ERROR

(IVE)

receive
VAXBI

COMMAND

ERROR

PARITY

(CPE)

parity

PARITY

Indicates

ERROR

(SPE)

bus

READ

DATA

SUBSTITUTE

the

TIMEOUT

(RTO)

STALL

TIMEOUT

(STO)

<18>

BUS

TIMEOUT

(BTO)

NONEXISTENT

ADDRESS

(NEX)

STALL

BDCST

node

(the

the

(or

received
or

error

node

responses

same

transaction

the

data

the

lines

<1:0>

cycle

Indicates

the

not

start

4096

code

during

cycle

the

(R/W1C,

DCLOC).

when

consecutive
slave

for

the

DCLOC).

slave

code

128

and

NBIB),

(R/W1C,

for

when

DATA

4096

from

STALL

(R/WI1C,

NBIB),

(the

BIIC's

asserted

port

the

RCI

consecutive

DCLOC).

node

(the

pending

bus

cycles

NBIB)

could

transaction

elapsed

DCLOC).

Indicates

the

master,

command

node

(the

detected

read/write-type

check

data

READ

detected

received

RETRY

Indicates

data

was

the

master,

RESERVED

vector)

Indicates

bus

ACK

when

error

DCLOC).

master,

(R/W1C,
<17>

parity

ACK

before

detected

NBIB),

during

cycles

the

command/address

(the

write

bus

<19>

node

parity

DCLOC).

NBIB)

read

RETRY

(the

during

detected

SUBSTITUTE

<20>

(R/W1C,

cycle

bus

not

transmitted

during

Indicates
(RDS)

did

DCLOC).

the

slave,

NBIB)

IDENT

node

(R/W1C,

(R/W1C,
<21>

error

SLAVE

(the

response

vector

Indicates
a

node
ACK

during

cycle
22>

(Cont)

Description

interrupt

<23>

Descriptions

parity

error

was

NBIB),
NO

ACK

when
response

transaction
master

detected

and

transmit

(R/W1C,

DCLOC)
.
<16>

ILLEGAL

CONFIRMATION

(ICE)

Indicates
ERROR

bus

master

the

node

illegal

(R/W1C,

DCLOC).

X 1-31

(the

slave,

RESERVED

NBIB),

when

received an
confirmation

code

Table

1-7

Bit(s)

Name

<15:4>

RESERVED

<3>

Bus Error Register Bit Descriptions

(Cont)

Description
Not used

USER PARITY
(UPEN)

ENABLE

(RO,

ZERGS).

Indicates the user interface to the
BIIC (the NBIB logic), not the BIIC,
is to generate VAXBI parity (RO,
DCLOL)
.

ID PARITY
(IPE)

ERROR

Indicates the node (the NBIB) detected
a parity error on the VAXBI I lines
during an embedded arbitration cycle
(R/W1C,

DCLOC).

<1>

CORRECTED READ
DATA (CRD)

Indicates the node (the NBIB), when bus
master, received a CORRECTED READ DATA
status code during a data cycle and no
parity error was detected (R/W1C, DCLOC).

<0>

NULL BUS PARITY
ERROR (NPE)

Indicates odd parity was detected on
the VAXRI during the second cycle of a
two—-cycle sequence during which VAXBI
NO ARB and VAXBI BSY were not asserted.
(R/W1C,

DCLOC)

3130292827262524232221201918171615
bb
+ 8

43210

NO ACK TO MULTI-RESPONDER COMMAND RECEIVED

MASTER TRANSMIT CHECK ERROR

CONTROILL TRANSMIT ERROR

MASTER PARITY ERROR
INTERLCCK SEQUENCE ERROR
TRANSMITTER DURING FAULT
IDENT VECTOR ERROR

COMMAND PARITY ERROR
SLAVE PARITY ERROR

ee-T X

READ DATA SUBSTITUTE
RETRY TIMEOUT
STALL TIMEOUT
BUS TIMEOQUT

NONEXISTENT ADDRESS
ILLEGAL CONFIRMATION ERROR

USER PARITY ENABLE
ID PARITY ERROR

CORRECTED READ DATA
NULL BUS PARITY ERROR
HARD ERROR BITS

SOFT ERROR BITS

<30:16>

<2:0>
MLO-036-86-R

Figure

1-14

Bus

Error

(BER)

1.5.2.4

Error

interrupt

Interrupt

control

Control

controls

the

(EINTRCSR)

—--

The

operation

interrupts

initiated by a BIIC-detected bus error
or
when
forced by setting bit <20>.
Register bit format
1-15.
Bit definitions are given 1in Table 1-8.

25242322212019

bb+C

0's

an
interrupt
1is
is shown in Figure

16161413

210

ABORT

NTR COMPLETE
INTR SENT
INTR FORCE

LEVEL <7:4>
VECTOR
MLO-037-85

Figure

1-15

Error

Interrupt

Control

error

(EINTRCSR)

Table

1-8

Error

Interrupt

Bit

Control

Bit(s)

Name

Description

<31:25>

RESERVED

Not

<24>

INTR

ABORT

(INTRAR)

used

INTR

COMPLETE

(INTRC)

(RO,

Indicates
the

control

aborted
<23>

INTR

SENT

command

this

the

vector

has

been

under

was

aborted.

Not

used

INTR

control

Cleared

request

(RO,
an

control

sent.

for

error

successfully
command

this

when

error

deasserted

DCLOC).

Indicates
the

the

under

was

DCLOC).

interrupt
sent

sent

Indicates

(R/W1C,

<21>

INTR

(R/W1C,

interrupt

RESERVED

(EINTRCSR)

ZEROS).

transmitted

22>

Descriptions

ZERO).
INTR

Cleared

request

command

this
when

under

deasserted

has

been

interrupt

(R/W1C,

DCLOC,

STOPC)
.
<20>

INTR

FORCE

Forces

(R/W,
<19:16>

LEVEL

<7:4>

The

error

DCLOC,

interrupt

commands

this

respond

this

<15:14>

RESERVED

Not

used

<13:2>

VECTOR

The

vector

<1:0>

RESERVED

under

(RO,

(R/W,

DCLOC).

used

X 1-35

(RO,

INTR

control

the

(the

IDENT

command

NBIB)

will

node

(the

DCLOC).

ZEROS).

sent

error

request

for

the

Also,
node

(R/W,

during

Not

level(s)

sent

level(s)

interrupt

STOPC).

this

interrupt

ZEROS).

sequences

NBIB)

1.5.2.5

1INTR

Destination

destination

addressed

INTR

(Figure
command.

1-16)

(INTRDES)

controls

bits

1-9,

which
are

The

nodes

defined

Table

16 15

bbt10

INTR

are

0's

INTR DESTINATION
MLO-038-85

Figure

Table

1-9

1-16

INTR

Destination

Bit(s)

Name

Description

<31:16>

RESERVED

Not

<15:0>

INTR

DESTINATION

(INTRDES)

used

(INTRDES)

Bit

(RO,

ZEROS).

Destination

bits

Transmitted

during
the

the

INTR

set,

node.

node

(R/W,

15;

for

the

INTR

VAXBI

command.

lines

command/address

cycle

bit,

when

transaction.

selects

For

Descriptions

the

corresponding

example,

bit

DCLOC).

<0>

Each

bit

<15>

selects

VAXRI

selects

node

1.5.2.6

IPINTR

Mask

(Figure

1-17)

controls

this

node

defined

(the

NBIB)

Table

with

(IPINTRMSK)
which

IPINTR

nodes

The

are

command.

IPINTR
to

select

bits

are

1-10.

1615

IPINTR MASK

bb+14

mask

permitted

0’s

MLO-039-85

Figure

Table

1-10

1-17

IPINTR

Bit(s)

Name

<31:16>

IPINTR

TIPINTR

Mask

(IPINTRMSK)

Bit

Descriptions

Description
MASK

Destination
commands.

the

node

IPINTR

<15:0>

(IPINTRMSK)

RESERVED

mask

Each

hits

bit,

(the NBIB)

commands

from

IPINTR
set,

allows

respond

the

correspond-

ing

VAXBI

minus

16.

For

example,

bit

<31>

the

mask

bit

for

node

15;

bit

16>

the

mask

bit

for

node

(R/W,

Not

used

X 1-37

node

for

when

(RO,

DCLOC).
ZEROS).

(FIPSDES) —-- The
Register
Destination
IPINTR/STOP
1.5.2.7
IPNTR/STOP destination register (Figure 1-18) controls which nodes
Register bits are
are to be addressed by IPINTR and STOP commands.

defined

in Table

1-11.

1615

bb+18

FORCE-BIT IPINTR/STOP DESTINATION

0's

MLO-040-85

Figure 1-18

IPINTR/STOP Destination Register (FIPSDES)

Table 1-11

IPINTR/STOP Destination Register (FIPSDES)
Bit

Descriptions

Bit(s)

Name

Description

<31:16>

RESERVED

Not used

<15:0>

IPINTR/STOP

DESTINATION

ZEROS).

(RO,

Destination bits for IPINTR and STOP

commands. Transmitted on the VAXRBI D
lines during the command/address cycle
of the IPINTR and STOP transactions.
Fach bit,

when

set,

responding VAXBI
<15>
node

selects
0 (R/wW,

X 1-38

selects

node.

node 15;
DCLOC).

the

cor-

For example,

bit

<0>

bit

selects

1.5.2.8

IPINTR Source Register

(IPINTRSRC)

-- The

source

IPINTR

Bit
register 1indicates the node that has sent an IPINTR command.
1in
described
are
bits
Register
format is shown in Figure 1-19.
1-12.

Table

1615

0's

IPINTR SOURCE

bbt1C

MLO-041-85

Figure 1-19

Table 1-12

IPINTR Source Register (IPINTRSRC)

IPINTR Source Register (IPINTRSRC) Bit Descriptions

Bit(s)

Name

Description

<31:15>

IPINTR SOURCE

Source bits for IPINTR commands
TM

J3LHAY

received by this node

bit,

when set,

(the NBIB).

indicates

Each

the

corresponding node minus 16 sent the
command. For example, bit <31>

indicates node 15 sent the IPINTR;

bit

<15> indicates node U sent the IPINTR.
In order for a bit to be set, the
appropriate bit in the IPINTR mask
register must

<15:0>

RESERVED

Not used

1-39

(RO,

set.

ZEROS).

and
(SADR
Registers
Address
Ending
and
Starting
1.5.2.9
the
defines
1-20)
(Figure
register
address
starting
EADR) -- The
by
recognized
be
to
is
that
addresses
of
first location in a block
commands.
read/write
VAXBI
to
responding
the BIIC's slave port when
The ending address register (Figure 1-21) defines the last location
The block of addresses may be in memory or I/O space,
one).
(plus
but the I/0 space cannot include node space or multicast space.
the NBIB, a block of memory addresses is specified that defines

storage block in NMI memory used for DMA data transfers by the

devices

connected

the

1In
the

I1/0

VAXBI.

Register bits are described in Tables 1-13 and 1-14.
The value
1in
the
starting
and
ending
address
fields
specifies
only
the
The low-order eighteen bits are
high-order twelve bits of address.
Tor example, if the
zeros by the BIIC logic.
all
be
to
assumed
ending
the
starting address register contains 1C440000 (hex), and
address
register
contains
1D680000
(hex), the BIIC's slave port
will

respond

to addresses

1C440000

1D67FFFF.

1817

313029

bb+20 0 0

through

0’s

STARTING ADDRESS

MLO-042-85

Figure

Table

1-13

1-20

Starting Address

Starting Address Register

(SADR)

Bit Descriptions

Bit(s)

Name

Description

<31:30>

RESERVED

Not used

(RC,

ZERQCS).

<29:18>

STARTING ADDRESS

Specifies

the

twelve

<17:0>

RESERVED

Not used

(RO,

ZEROS).

high-order

address bits of an address (the
low-order address bits are
assumed to be zeros), that is, the
lowest address to be recognized by
BIIC's slave port (R/W, DCLOC).

X 1-49

1817

313029

bb+24 0

ENDING ADDRESS
MLO-043-85

Figure

Table

1-14

1-21

Ending Address Register

(EADR)

(SADR)

Bit Descriptions

Bit(s)

Name

Description

<31:30>

RESERVED

Not used.

<29:18>

STARTING ADDRESS

Specifies the twelve high-order

RESERVED

ZEROS)

address bits of an address (the
low—-order address bits are
assumed to be zeros), that is,
one greater than the highest
address to be recognized by the

BIIC's

<17:0>

(RO,

slave port

Not used

X 1-41

(RO,

(R/W,

ZEROS).

DCLOC).

1.5.2.10
BCI
Control
and
Status
Register
(BCICSR)
control/status
register
is
shown
in
Figure
1-22,
described

Table

The
Bits

BCI

are

1-15.

1817161514131211109 8 7 6 5 4 3 2

BURST ENABLE

iPINTR/STOP FORCE
MULTICAST SPACE ENABLE
BDCST ENABLE

STOP ENABLE
RESERVED ENABLE

IDENT ENABLE

INVAL ENABLE

WRITE INVALIDATE ENABLE

USER INTERFACE CSR SPACE ENABLE
BIIC CSR SPACE ENABLE
INTR ENABLE

IPINTR ENABLE
PIPELINE NXT ENABLE

RTO EV ENABLE
MLO-044-85

Figure

Table

1-15

1-22

BCI

VAXBI

Control/Status

Bit(s)

Name

Description

<31:18>

RESERVED

Not

<17>

BURST

ENABLE

(BURSTEN)

used

(BCICSR)

(RO,

Causes

BIIC

VAXBI

NO ARB

successful
(the NBIB)

X 1-42

(BICSR)

Bit

Descriptions

ZEROS).

continuously

following

assert

arbitration by
(R/W, DCLOC).

this

node

Table

1-15

RCI

Con trol/Status

Bit(s)
<16>

Descriptions

IPINTR/STOP

FORCE

Causes

BIIC

command.

MULTICAST

SPACE

(MSEN)

Enables

BDCST

ENABLE

(BDCSTEN)

Enables

ing

(R/W,
<13>

STOP

ENABLE

(STOPEN)

RESERVED

ENABLE

(RESEN)

IDENT

ENABLE

(RESEN)

the

read/write

assert

SC<2:0>

BDCST
(the

assert

BCI

SC<2:0>

this

the

Enables

assert

BCI

SC<2:0>
of

to
is

SEL

Enables

the

directed

and

follow-

NBIB)

and

follow-

RESERVED

assert

SC<K2:0>
of

SEL

code

this

node

BCI

(the

SEL

code

IDENT

and

followcommand

this node (the NBIB).
cleared, BIIC still
in

and

(R/W,
BIIC

transaction

even

SC<2:0>

not

assert

BCI

SC<2:0>

this

DCLOC).

are

DCLOC).

receipt

BCI

receipt

appropriate

X 1-43

SEL

command

BCI

BIIC

the

(R/W,

command
NBIB)

code

STOP

(the

receipt

appropriate

ing

node

BIIC

asserted
ENABLE

and

follow-

DCLOC).

though

(INVALEN)

SEL

code

participates

INVAL

BCI

node

receipt

directed
When bit

<10>

and

follow-

multicast

this

appropriate

ing

SEL

code

command directed to
NBIB)
(R/W, DCLOC).
<11>

BCI

BIIC

Enables

ing

FIPSCMDS

DCLOC).

directed

<12>

appropriate

(R/W,

assert

SC<2:0>

receipt

Enables

ing

BIIC

the

DCLOC).

appropriate
directed

bus

STOP

transmitted

BCI

directed

(R/W,

for

DCLOC).

receipt

command

space

command

(R/W,
BIIC

the

IPINTR

contents

appropriate

ing

arbhitrate

(The
on

ENABLE

transmit

depends

<14>

(BCICSR)

(Cont)

Description

Name

and

<15>

Bit

node

BCI

SEL

code

INVAL

and

follow-

command

(the NBIB)

Table

Bit(s)
<9>

BCI Control/Status Register
Bit Descriptions (Cont)

1-15

Description

Name

INVALIDATE

WRITE

ENABLE

(WINVALEN)

Enables BIIC to assert BCI SEL and
appropriate BCI SC<2:0> code following the receipt of a write command
whose address falls outside the
range specified by the starting and
ending address registers and it 1is
a memory

<8>

USER

CSR

INTERFACE

ENABLE

SPACE

(UCSREN)

<7>

BIIC

CSR

ENABLE

SPACE

(UCSREN)

INTR

ENABLE

(INTREN)

<5>

IPINTR

ENABLE

(IPINTREN)

<4>

PIPELINE

ENABLE

<3>

RTO

NXT

(PNXTEN)

ENABRLE

(RTOEVN)

RESERVED

(R/W,

DCLOC).

Enables BIIC to assert BCI SEL and
appropriate BCI SC<2:0> code following the receipt of a read/write
directed at the BIIC's CSR
command
space. When bit is cleared, BIIC
still participates in transaction
SC<2:0> are not
even though SEL and
asserted (R/W, DCLOC).
T

Enables BIIC to assert BCI SEL and
appropriate BCI SC<2:0> code following the receipt of an INTR command
directed to this node (the NBIB)
(R/W, DCLOC).
Enables BIIC to assert BCI SEL and
appropriate BCI SC<K2:0> code following the receipt of an IPINTR command
from a node included in the IPINTR
mask register (R/W, DCLOC).
the

Causes

BIIC

assert

BCI

NXT

for an extra cycle during write and
BDCST transactions. Facilitates the
use of FIFO pointers for some nodes
(not the NBIB) (R/W, DCLOC).
Enables

the

BIIC

assert

RETRY

TIMEOUT code on the RCI EV<4:0>
lines after a retry timeout
(R/W,

<2:0>

address

Enables BIIC to assert BCI SEL and
appropriate BCI SC<K2:0> code f[ollowing the receipt of a read/write
command directed at user interface
CSR space (R/W, DCLOC).

<6>

(BCICSR)

Not

1-44

DCLQC).

used

(RC,

ZERCS).

1.5.2.11

ragister

Write

Status

(Figure

1-23

general-purpose

registers

only

parity

good

general-purpose

and
have

1is

registers

(WSTAT)

Table
been

written.

received
are

not

with

used

The

1-16)

write

status

the

write

the

status

indicates

NRIB

bit

which
is

set

data.

(The

node.)

3130292827

bb+2C

0’s

GENERAL PURPOSE REGISTER 0
GENERAL PURPOSE REGISTER 1
GENERAL PURPOSE REGISTER 2

GENERAL PURPOSE REGISTER 3
MLO-045-85

Figure

Table

Bit(s)
<31>

1-16

1-23

Write

Status

Name
GENERAL

GENERAL

PURPOSE

(GPR2)
<29>

GENERAL

PURPOSE

(GPR3)
<28>

<27:0>

GENERAL

(WSTAT)

Bit

Descriptions

Description

(GPR3)
<30>

PURPOSE

General-purpose

written

DCLOC)

(R/W1C,

General-purpose

written

DCLOC)

(R/W1C,

General-purpose

written

DCLOC)

(R/W1C,

General-purpose

(GPRO)

written

DCLOC)

RESERVED

Not

X 1-45

used

(R/W1C,
(RO,

ZERO)

Force IPINTR/STOP Command Register (FIPSCMD) -- The force
1.5.2.12
command register (Figure 1-24 and Table 1-17) contains
IPINTR/STOP

the code for the command initiated by the BIIC when the IPINTR/STOP
IPINTR/STOP

command

1615

121110

0’s

O’s

bb + 30

COMMAND

1-17

[
@)
D

]

N
=

[)

"~
D

’—l -

MASTER ID ENABLE

Table

Force

MLO-046-85

TPINTR/STOP Command

IPINTR/STOP Command Register
Bit

Bit(s)

(FIPSCMD)

Descriptions

Name

Description

<31:16>

RESERVED

Not used

<15:12>

COMMAND

(CMD)

(RO,

ZEROS).

IPINTR OR STOP command
VAXBI

transaction

BIIC when
bit

(R/W,

<11>

MASTER ID ENABLE

Causes

(MIDEN)

VAXBI

the

set

code

initiated

IPINTR/STOP
the

IPINTR

the
be
D

node's

(the

transmitted
lines

command

Not used

X 1-46

FORCE

DCLOS).

during

field.

RESERVED

for
by

BCICSR

NBIB's)

the

action initiated by the
IPINTR/STOP FORCE bit (in
BCICSR). Must be set when

<10:0>

Only
force

(BCICSR).
the
1in

FORCE bit is set in the BCI control/status register
1loaded
be
should
code
an IPINTR or STOP command

(RO,

ZEROS).

the

trans-

the
an
command

1.5.2.13
interrupt

VUser

Interrupt

control

initiated

format

shown

the

user
in

Control

controls

interface

(the

UINTRCSR}

the

NBIB

operation

1logic).

Figure

1-25.

Bit

definitions

28 27

24 23

2019

16151413

bb+40

—-of

The

user

interrupts

are

given

bit
Table

210

INTR ABORT <7:4>
INTR COMPLETE <7:4>

INTR SENT <7:4>
INTR FORCE <7:4>

EXTERNAL VECTOR
VECTOR
_
MLO-047-85

Figure

1-25

User

Interrupt

X 1-47

Control

(UINTRCSR)

Table

User Interrupt Control

1-18

Bit
Bit(s)

Name

<31:28>

INTR

(UINTRCSR)

Description
ABORT

<7:4>

(INTRAR)

<27 :24>

Descriptions

COMPLETE

<7:4>

(INTRC)

Indicate an INTR command sent under
the control of this register was
aborted. The bit(s) set indicate the
INTR level(s) BR<7:4> (R/W1C, DCLOC).

Indicate the vector for an interrupt
has been successfully transmitted or if
an INTR command sent under the control
of

this

was

aborted.

The

bit(s) set indicate the TNTR level(s)
BR<7:4>. A bit is cleared if the corresponding error interrupt request 1is
deasserted (R/W1C, DCLOC).
<23:20>

INTR

SENT

(SENT)

<7:4>

Indicate an INTR command sent under
the control of this register has been
sent. The bit(s) set indicate the INTR
level(s) BR<7:4>. A bit is cleared
by an IDENT servicing the corresponding

interrupt
INTR

FORCE

(FORCE)

EXTERNAL

(EX

<1:0>

level(s)
VECTOR

VECTOR)

interrupt request.
the

BR<7:4>

interrupt

(R/W,

DCLOC,

STOPC).

The

bit(s)

request

STOPC).

Causes BIIC to send vector supplied by
user interface on BCI D lines during
user

interface

(R/W,

DCLOC).

VECTOR

The vector sent by this node (the NBIR)
during user interface interrupt
sequences unless the EX VECTOR control
bit

Not

used

(RO,

sequences

Not

RESERVED

used

intervrupt

RESERVED

<13:2>

determines

set

ZEROS).

set.

9:0]

<14>

Forces

i,, -d

<15>

<7:4>

<19:16>

DCLOC,

(R/W1C,

level

(RO,

ZEROS).

1.5.2.14

General

general-purpose

Purpose

registers

However,

the

registers

the

initialized

NBIB

may

Registers

(Figure
be

(R/W,

(GPR

1-26)

accessed

and

<K3:0>)

are

not

they

used
are

The

BIIC's

the

NBIB.

cleared

when

DCLOC).

bb+F0

GENERAL PURPOSE REGISTER O

bb+F4

GENERAL PURPOSE REGISTER 1

bb+F8

GENERAL PURPOSE REGISTER 2

bb+FC

GENERAL PURPOSE REGISTER 3
MLO-048-85

Figure

1-26

General-Purpose

X 1-49

Registers

(GPR

<3:0>)

CHAPTER
INTERFACE

2.1

NMI

The

NMI

lines
are

signal

the

data

Backplane

The

NMI

that
such

lines

connecting
bus

the

the
Bus

the

NRIR,

signal

assignments

main

the

NBIA(s).
Summary

are

1lines

are

system

interconnects

System

connecting

NBIA,

and

the

VAXBI

signal

Figure

2-1.

Also

shown

the

NBIA

and

NBIB.

connecting

interconnect.
memory,

detailed
2

indicated.

CPU(s),

(Section

the

shown

DESCRIPTIONS

follows.

X 2-1

It
and

description
this

is
any
of

manual).

synchronous

I/0

adapter

the

NMI

basic

bus

modules
given

description

DATA PATH _SIGNALS
ADDRESS

DATA<O>

ADDRESS DATA<1>
ADDRESS DATA<2>
ADDRESS DATA<3 >
ADDRESS DATA<4>

___ADDRESS DATA<5>
ADDRESS DATA<6>
ADDRESS DATA<7>
ADDRESS DATA<8>

DATA<9>
_ADDRESS
Al
ADDRESS_DATA<10>

ADDRESS DATA<11>

ADDRESS DATA<12 >
ADDRESS DATA<13»>
ADDRESS DATA<«t4 >
ADDRESS DATA<15>

-¢ X

ADDRESS DATA<16 >

ADDRESS_DATA<17>
ADDRESS DATA<18>
ADDRESS DATA<19>

ADDRESS DATA<20>
ADDRESS DATA<21>

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NMI

BUS

<A01 >

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(SLOT

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NOTE:

—

DATA BUS CABLES PLUG INTO BACKPLANES.

SCLD-418

Figure

2-1

NBIA

and

NBIB

Input/Output

Signals

(Sheet

BUS

CONFIBRMATION<1>_H

CONFIRMATION<O>
MEMORY BUSY

O _ARB H
10

BUS

HOLD

NBIA

<«C10> ¢
P

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(SLOT

12)

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REVN LINTR165

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BACKPLANES.

SCLD-419

Figure

2-1

NBIA

and

NBIB

Input/Output

Signals

(Sheet

2.1.1

NMI

Signals

NMI signal lines connecting to an NBIA are defined 1in Table 2-1.
All the signals are ECL except for ACLO and DCLO, which are
FET-driven and received.
2.1.2 Basic Timing

Generally, NMI signals are asserted and deasserted at the beginning
of a bus cycle, which is phase B of the system clock. Also, bus
signals are received and latched using phase A of the system clock.
Refer

to Figure

2-2.

NMI BUS CYCLE

B CLK H

TRANSMIT PERIOD
i¢

A CLK H

DATA VALID

/_——\
|

RECEIVE PERIOD

DATA
LATCHED

Figure 2-2

Basic NMI Timing

X 2-4

Table

2-1

NMI

Signal(s)

Number

ADDRESS

DATA

<31:00>

Signals

Connecting

Multiplexed
Transfer

address/data

30-bit

address

command/address

cycles.

data

<4:0>

NBIA

Description

longword

FUNCTION

read/write

lines.
during

Transfer
during

data

cycles.

Specify

command

address

during

cycles

data

during
and

command/-

data

type

cycles.

FUNCTION

<4:0>

(Hex)

Command/Data

Read

Longword

Read

Octaword

Read

Hexword

Type

Read

Longword

(Interlocked)

Read

Octaword

(Interlocked)

Read

Hexword

Write

Longword

Write

Octaword

(Interlocked)

Write

Longword

Masked

Write

Quadword

Masked

Write

Octaword

Masked

Write

Longword

Unlock

Write

Quadword

Unlock

Masked

Write

Octaword

Unlock

Masked

Memory

Return

Read

Data

(Good

Return

Read

Data

(Bad

Pause

(Not

Used)

Read

Continue

(Good

Read

Continue

(Bad

Write

X 2-5

Masked

Data

Data)
Data)

Data)

Table 2-1

NMI Signals Connecting to NBIA (Cont)

Signal(s)

Number

Description

ID MASK<3:0> H

Specify ID of commander during
command/address cycles and
read data cycles. No ID is

for

the memory nexus

the commander
action.

during

bus

return
required
is never
trans-

Nexus

0100

CPU

(Primary CPU)

CPU

(Attached CPU)

0101

0110

0111

1000

1001

1010

1011

NBIA O

(VAXBIO)

NBIA 0

(VAXRI1)

(VAXBIO)

NBIA 1

(VAXBI1)

NBIA

1100
1101

1110
1111

Dual-CPU

backplanes

only

Also, during NMI write data cycles
of masked write transactions, specify

the bytes

in the longword

of write data
MASK

that

are

(four bytes)

to be written.

BIT

3210

X X X1
X X 1X
X 1 X X
1 X X X

DATA PARITY H

Write byte
Write byte
Write byte
Write byte

0
1
2
3

Transfers even parity bit for the
32 ADDRESS DATA lines during NMI
command/address and data cycles.

Table

Signal(s)
FUNCTION
PARITY

2-1

NMI

Signals

Connecting

Number

Description

Transfers

lines

CONFIRMATION

<1:0>

even

FUNCTION

and

(Cont)

NMI

and

bit

for

MASK

the

command/address

cycles.

Specify
to

NBIA

parity

lines

during

data

response

function

sent

(by
by

responder)
commander.

CONFIRMATION

<1:0>

Response

No response (NOACK)
Command/address

acknowledged

MEMORY

BUSY

Interlocked

Busy

Asserted

memory

command/data
current

action
when

transmitter

and
of

memory

ARB

memory

Asserted

BUS

HOLD

LINTR

abort

for

Causes

trans-

the

bus

first

during

data

cycle

write.

NBIA

Asserted

bus

arbitrator

NBIA

the

bus.

Asserted

NBIA when

another

(more

request

use

bus.

use

after
DEVN

its

full.

command/address

read,

when

the
IO

during

command/address
of

are

rearbitrate

asserted

cycle

nexus

buffers

(ACK)

getting

Asserted

CPU

left

(the

than

use

NBIA
CPU

one)

to
in

the

grant

requires
bus

cycle

bus.

interrupt

the

dual-processor

systems).
DEVN

RINTR

Asserted

right
DEVN

LINTR

LVL<1:0>

Asserted

interrupt

(the

NBIA

interrupt

dual-processor
NBIA

request

left CPU

systemnms).

X 2-7

CPU in

specify

level

the

systems.
the

the

in dual-processor

CPU

Table 2-1

NMI Signals Connecting to NBIA (Cont)

Signal(s)

Number

Description

DEVN RINTR
LVL<1:0> H

Asserted by NBIA to specify the
interrupt request level to the

right CPU in dual-processor systems.
DEV (L/R)INTR LVL
<1:0>

Interrupt
Request Level
BR4
BR5
BR6
BR7

00
01
i0
11

FAULT DETECT H

Asserted by NBIA when it has detected

Signal is ORed with FAULT
a fault.
DETECT lines from other nexus 1in

memory

FAULT H

nexus.

Asserted by fault handling logic in

memory nexus to signal a FAULT DETECT
line has been asserted.

UNJAM H

Initializes all nexus without clearing

status indicators.

Also,

causes

NBIB(s) connected to NBIA to generate
an ACLO/DCLO sequence on the VAXBI.
Asserted by clock module in response
to a console command.

RESET H

Asserted by NBIA if VAXBI RESET 1s

asserted by a VAXBI device connected
to the NBIB.

Causes console to stop

the CPU(s) and then bootstrap the
system (a cold start). The bootstrap
does not occur until RESET is negated.

SLOW CLOCK
ENABLE H

SLOW MODE H

Asserted by clock module and used
to increment timeout counters in all
nexus.

Early-warning signal asserted by clock

module to indicate that the normal
system clocks (A CLK and B CLK) are
Asserted a
about to start or stop.
minimum of 4 microseconds before
HARBINGER.

X 2-8

Table

2-1

Signal(s)
HARBINGER

NMI Signals Connecting to NBIA
Number

Description

Asserted
B

PHASE

(Cont)

clock module

clock

when

during

normal

last

system

clocks are stopped. Used as clock
blocking signal by nexus using freerunning clocks(F A CLK and F B CLK)
to simulate stopped-clock behavior.
Not
AC

used

NBIA.

FET-driven and
warning signal

received
asserted

power-loss
by system

power supply when ac power
specified limits.
DC

FET-driven
warning

and

signal

SELECTK1>

asserted

LEVEL

OUT

system

1is

below

Backplane—-generated (hard-wired)
signal that determines I/O address
space for NBIA. A logical one is
generated by backplane wiring that
connects 10 SEL input to the NBIA's
ONE LEVEL output. (No connection
is equivalent to a logical zero.)
IO

ONE

below

received power-loss

power supply when dc power
specified limits.
I0

NMI

SELECT

<1>

NBIA

0
1

Logic level output
asserted

I0 SEL

X 2-9

by NBIA.

Base

Address
2000
2400

(Hex)

0000
0000

(logical one)
Used

to generate

input signal on the backplane.

Table

Signal(s)

CLK

2-1

NMI

Signals

Number

H/L

Connecting

CLK

H/L

Phase

CLK

H/L

CLK

MODULE

KEY

H/L

normal

system

bus

defined

cycle

CLK

the

and

Phase
~T A~

Phase

of
AN A~ 4+

leading

the

edge

free-running
UO T

ey
U_Y

Module

keying

NMI

period
one

system

NMDTA

INIDL{M
e

free-running

Not

clock.

module.

next.

R~ aYa

clock.

module.

clock

CILUCN

(Cont)

system

clock

between

normal
by

Generated

NBIA

Description

Generated

used

system

NBIA.

loop.

connection

within NBIA module. This line is
grounded 1if the wrong module type
is

plugged

into

the

NBIA

slot.

2.1.3
NMI

NMI

Address

address

ADDRESS/DATA

Figure

2-3,

memory.

space,

each

one

system

1in

the

backplane

NMI

the

write

been

transaction

transaction)
more

ends

the

bus,

the

than

(the

be granted
commander.,

the

transfers

(each

for

one

nexus

bus

For

read

the

two

NBIAs

can

NBIAL.

data

during

addressed

order

hexword
one

transfers

transactions

originated

NBIA

addressed.

and
in

physical
the

Mbytes

I/0

for

installed

block
NBIA

can

then

is
in

transfer.
(the

bus

octaword)

made.

transactions

supported

NBIA
by

the

VAXBI
the

NMI,

responds
CPU

X 2-11

when

to
a

and

has
the

one

cycles.

This

other

hand,

been

must

read

is shown in
(longword/octaword)

originating

information

commander)

granted

2.1.5.)

Once

nexus

are

transfer

Section

two

transactions

the

memory)

return
the
transactions,

read

although

the

consecutive

the

read/write

single

read
transaction,
on
the
transfer.
First, after it has
transmits the
command/address.

originates

Also,

NMI

shown

Within

NMI

NBIA.)

(The

discussed

NBIA

transactions,

64-Mbyte

request

command/address

transferring

data

first

single

(longword/quadword/octaword)

CSR,

(32

commander

write

the

space.

NBIA

The

DMA

allocated

each

first

2-5.,
during

address

the

CPU,

must

the

write

commander

responder

Timing

consists

transaction.

wore

arbitration

bus,

multiplexed

second

NBIA,

NMI,

transmits

longwords

requires
the

the

When

purposes.)

Transactions

(Bus

granted

the

NBIAl.)

(an

the

bus.

1I/0

allocated

the

space

backplane),

addressing

address
is

and

nexus

the

for

system.

Read/Write

information
use

NBIAO

(Only

used

half

(dual-CPU

single-CPU

NMI

block

2.1.4

Gbyte.

other

allocated

Before

are

half

64-Mbyte

VAXBI)

lines

The

Space

space

granted

Then,

the

request

and

data

return

the

read

datsa

Figures

2-4

transactions

and
and

access

memory

device.

(Read

hexword

are

not

originated

read/write

VAXBI device

(longword)
register,

0000 0000

NBI ADAPTER ADDRESS ALLOCATION
(32 MB FOR EACH VAXBI)

PHYSICAL
MEMORY

(512 MB)

NBI

2000

1FFF FFFF

2000 0000

23FF FFFF

2400 0000

2800 0000

27FF FFFF

*NBIAO

0
EES
?EAPI,
M
4

NBIA1

ADAPTER 1

(64 MB)

RESERVED

—
l

0000

|21FF FFFF|

2400 0000

—(

(352 MB)

77 77

(32

MB)

2200 0000 | vAXBI 1

23FF FFFF
S

0
VAXBI

(32 MB)

NBI 1
VAXBI 0

oseF Frep| (32 M9
2600 0000}

VAXBI 1

(32 MB)

27FF FFFF

3DFF FFFF
3E00 0000 | MEMORY

CONTROLLER

arFr FrFF [(32 MB)

*RESERVED ADDRESS SPACE IN SYSTEMS THAT CAN
HAVE ONLY ONR NBIA INSTALLED (SYSTEMS
HAVING SINGLE-CPU BACKPLANES). IN THESE
SYSTEMS, THE SINGLE NBIA IS NBIAT.

SCLD-128

Figure 2-3

NMI Address Space

WRITE OCTAWORD

WRITE QUADWORD

VAN

J/
WRITE

NMI

LONGWORD

VAN

CYCLE

C/A

30-BIT
ADDRESS

DATA <31:00>

ADDR

DATA

<29:00>f

DATA

WRITE | WRITE
DATA

DATA

| WRITE

DATA

LEGEND

WRITE
DATA

G -

COMMANDER

R = RESPONDER

AN =

C/A

ALL

NEXUS
COMMAND/

ADDRESS

SOURCE

c
WRITE

FUNCTION<4:0>

CMD

CMDR'S |

MASK<3:0>

PARITY

FUNCTION

PARITY
CHK

BYTE

wrRite

DATA

EVEN
AN

write

EVEN |

EVEN

warre

BYTE

MASK |
C

BYTE

MASK
c

—

MASK FIELD

EVEN | EVEN | IGNORED
BY
EVEN

EVEN

RERPORORR

OK
R

SOURCE

T
c

WRITE

CYCLE

WRITE.

CONFIRMATION<1:0>

HOLD H

—

EVEN | EVEN

DATA | DATA

BYTE

MASK

—

EVEN

DATA

MASK |

SOURCE

| WRITE

SOURCE

CONFIRMATION OCCURS THIS CYCLE
FOR ALL

N .

COMMANDS.

c
~

e
—

LONGWORD

WRITE

WRITE QUADWORD

L WRITE OCTAWORD
SCLD-131

Figure

2-4

NMI

Write

X 2-13

Transaction

C = COMMANDER

R = RESPONDER

READ HEXWORD (SEE NOTE 2)
A

AN = ALL NEXUS

BEAD OCTAWORD

C/A = %OYhéhfé\ND/ADDRESS

VAN

READ
LONGWORD

NMI
CYCLE

C/A

o
DATA DATA

~__

DATA DATA

DATA

DATA DATA DATA

BIT

ADDRESS

ADDR

DATA
<31:00>

SOURCE

FUNCTION

ID MASK

CMDR

SOURCE
GEN
DATA PAR/

c
Cc
EVEN

<4:0>

SOURCE

<3:0>

F ID PAR

CHK

CONFIRMATION

<1:0>

HOLD H
NOTE 2:

_| R

TcmoR | omoR |oMoR [cMpr|

. 1

RTN | READ | READ | READ

DATA | CONT | CONT | CONT
|

OMDR | CMDR | CMDR | CMDR
1D

R
R
R
_ | R
R
R
R
R
2
EVEN | EVEN | EVEN |EVEN

R
R
R
R
_
R
R
R
TR | EVEN
| EVEN |EVEN
EVEN

EVEN | EVEN | EVEN |EVEN

EVEN

SOURCE

NOTE 1:

READ

| AN
AN | AN | AN
|

EVEN | EVEN | EVEN | EVEN

AN | AN | AN

—d

Jfi‘

Jf_/i
7

—\___’,;_/

NMI AVAILABLE FOR OTHER TRANSACTIONS.

BESPONDER (MEMORY) RELEASES NMI AFTER TRANSFER OF FIRST OCTAWORD

IN THE READ HEXWORD TRANSACTION SHOW. RESPONDER (MEMORY) MAY
ALSO HOLD BUS AND TRANSFER ALL THE DATA (EIGHT SUCCESSIVE -DATA
CYCLES) IF SECOND OCTAWORD 1S READY FOR TRANSMISSION.

Figure 2-5

NMI Read Transaction

X 2-14

SCLD-132

During the command/address cycle of a
transaction,
the
commander
transmits
the
address
on
the ADDRESS DATA lines, the read/write
function (read longword, write
octaword,
etc.)
on
the
FUNCTION
lines,
and
the
commander's
ID
on
the
ID
MASK lines.
If the
responder
accepts
the
command/address,
it
asserts
an
ACK
(acknowledge)
response on the CONFIRMATION lines.
A BUSY response
is asserted if a responder (the memory, for example) is
not
ready
to
accept
the
command/address at this time.
The memory can also
assert an INTERLOCKED response.
The memory is hardware interlocked
by
a read interlocked transaction.
Although it executes the first
interlocked transaction normally, any read interlocked transactions
that
follow
are not accepted until the interlock has been removed
by a write unlock transaction.
During the
write
data
<cycle(s)
immediately
following
a
write
transaction's
command/address
cycle,
the commander transmits the
write data on the ADDRESS DATA lines, a code identifying
the
data
(as
write
data)
on the FUNCTION lines, and a byte mask on the ID
MASK lines if the transaction is a masked
write.
The
byte
mask
indicates
which
bytes
1in
the
1longword
of write data are to be
written.

During read data cycles, the responder transmits the read
data
on
the ADDRESS DATA lines, a code identifying the data as read data on
the FUNCTION lines, and the (saved) commander's ID on the
1ID
MASK
lines.
The
FUNCTION
1line code indicates if the read data is the
first longword in the transfer and if the
data
1is
good
or
bad.
That is, a RETURN READ DATA (GOOD or BAD) code is returned with the
first longword.
A READ CONTINUE (GOOD or
BAD)
code
1is
returned
with

all

other

longwords.

Two separate even parity bits
are
transmitted
by
the
commander
during
command/address and write data cycles, and by the responder
during read data cycles.
One parity bit, which
1is
generated
for
the
information
on
the ADDRESS DATA lines, is transmitted on the

DATA PARITY line.
The other parity bit, which is generated for the
information
on
the
FUNCTION and ID MASK lines, is transmitted on
the FUNCTION ID PARITY line.
The two parity bits
are
checked
by
all
nexus.
If
bad
(odd)
parity is detected, it causes the NMI
FAULT

line

discussed

to
in

asserted.

Section

Parity

2.1.7.

X 2-15

and

other

NMI

errors

are

2.1.5
The

NMI

bus

Arbitration/Memory

arbitrator

for

the

Busy

NMI

the

CPU

(the

1left

CPU

dual-processor
systems).
Each
NMI
nexus
has a bus arbitration
(ARB) line, a BUS EN line,
and
a
HOLD
1line
connecting
to
the
arbitrator.
Basic arbitration line timing is shown in Figure 2-6.

NEXUS

CYCLE

C/A

ARB X

///f

BUS EN X

C/A

DATA

N\,

___,/’//i:____///

ARB Y

///

BUS EN Y

HOLD Y

SCLD-135

Figure

2-6

Basic

NMI

Arbitration

Line

Timing

request use of the bus, each nexus must assert its
ARB
request
line.
The
request
1line
1s
asserted
at the beginning of a bus
cycle.
More than one nexus may request the bus at a time
and
the
bus
arbitrator
resolves
request
priority and asserts the BUS EN
line
for
the
winning
nexus.
The
BUS
EN
1line
is
asserted
immediately
if
the bus is not currently in use.
If the bus is in
use, the BUS EN line is not asserted until the bus is
free.
This
ensures

necessary

BUS

the

dead
due

signal,
bus

cycle

between

electrical

negates

transfers

constraints.

its

ARB

cycle.

X 2-16

request

on
When a
line

B v
T
[5-Sups

the

nexus
at

the

NMI,

which is
receives its

beginning
;;;;;;;

]

nexus

wins

transfer,

line

asserted

transfer.
the

disables
to

The

memory

The

CPUs

the

bus

last,
an

NBIAs

(or

NBIA

(or

Typical
In

has

the

bus

1last,

two

CPUs)

requests

and

BUSY

the

3
read/write

transmitting

retrying

the

another

(lower

available
only

the

indicates
the
after

the

unless

can

will

some

the

data

not

the

bus.
share

and

NBIA

NBIA won
a

CPU

the
use

shown

are

the

rather

bus
than

when

two

bus
and
an
the bus last.

Figure

2-7.

memory
nexus
MEMORY BUSY

may
ARB

the

bus

arbitrator),

buffers

are

full,

until

«can

and

indicated

Figure

thus

empty

cycle

2-8),

the

memory.
status

preventing

further

not

Mk
o &
'nat

have

the

bus

for

-~
s o
nexus

the
and

BUSY
then

before

memory

BUSY

memory

retry

should

(MEMORY

line

A
tne

aborting

nexus

the

time.

:
1is,

to wait

before

indicates

early-warning
|
ous.

gets

become

asserted

cases.)

the

memory

(write

data
by

command/address

write

accepted

without

1 2 v~
lines.

cycle

command

BUS

and

the

accepted
an

allows

after

retried

MTANT
CONFIRMATION

first

1line

priority

bus

=
the

This

cycle

the

Furthermore,

temporarily

asserted

data

otherwise

CONFIRMATION

be
as

request

command

transactions),

not

acts

1lines

cycle

HOLD

causes

command/address

does

first

the

(refer

possible

transaction

respeonse

will

bus

command/address.

shortest

BUSY

wins.

the

CONFIRMATION

bus cycles

the

using

during

the

CPU or NBIA bus requests.
still be granted.
The memory

can

priority)

the

two

MEMORY

during

BUSY

transaction.

CPU

than

system

command/address

the

command/data

transaction

function

the

When

requesting

Conversely,

cycle

granting

its

transactions

response

both

connecting

from

asserted

MEMORY
its

itself

nexus

command/address

sense,

lowest

from

when

respond
is

when

CPU

HOLD

last

also

for

The

asserted.

the

cycle

bus.

asserted

have

CPU rather

timing

memory

other

the

priority

bus.

BUSY

read/write

addition

for

the

remain

bus

the highest priority, the
This signal, by means of

MEMORY

the

buffers

line

bus

the

system are requesting
is the one that did not

arbitrator

MEMORY

preventing

the

wins,

copy

this

wins

line

that

the

CPU)

MEMORY

and

NBIA

BUSY.

highest
basis.

bus,

having

memory

bus

alternating

the

system

the

arbitration.

MEMORY

asserts

beginning

the

first

bus

holding

had

addition

Bus

the

one

keep

further

assert

than
to

the

arbitration

prevents

beginning

more
line

arbitrator,

the

then

NBIA

HOLD

bus

NBIAs

requires
its

the

nexus

requesting

the

negated

nexus

and

assert

1In

any
the

bus

transfer.

line

the
must

will
the

lines.

X 2-17

the

having

memory.
wait

DAMAT
MEMORY

nriQw

quadword

cycle

transaction,

DUOD I

accepted

response

and

also

Again,

for

the

I m
is

merm
e
asserted

write

the

returned

BUSY

octaword

memory
on

the

NEXUS

INBIAO

CYCLE

C/A

RIGHT CPU ARB H
ARB H

1/0

ARB H

READ
DATA

WRT

DATA

READ
DATA

READ | R EAD
DATA
DATA

C/A

LEFT CPU ARB H

C/A

NBIA1

MEMORY ARB H

170

MEMORY

LEFT CPU

LEFT CPU HOLD H

MEMORY HOLD H

MCL BUS EN H

LEFT CPU BUS EN H

RIGHT CPU BUS EN H

1/0

BUS EN H

I/0

BUS

EN H

N\
SCLD-137

Figure

2-7

NMI

Arbitration

Line

Timing

MEMORY BUSY ASSERTED

COMMAND/ADDRESS CYCLE

ABORTS MEMORY READ/WRITE

NEXUS

TRANSACTION

C/A

(MEM

MEMORY BUSY H

R/W)

ARB
X H

BUS EN X H

(RETRY)

(ABORT)

A‘A

MINIMUN I ASSERTION TIME

TWO BUS CYCLES

—

—~

—

?<.'

CONFIRMATION<1:0>

CYCLE

BUSY

NOTE:

RESPONSE

MEMORY BUSY ASSERTED IN FIRST DATA CYCLE OF MEMORY WRITE.
ALSO ABORTS TRANSACTION AND CAUSES RETRY.

SCLD-138

Figure

2-8

MEMORY

X 2-19

BUSY

Timing

2.1.6 NMI

Interrupts

systems.
NMI interrupt lines connect to both CPUs in dual-processor
upts.
interr
NMI
accept
to
d
enable
is
However, only the primary CPU
enable

A CPU is enabled by setting bit <00> in its

interrupt

NMI

There are two types of CPU interrupt requests generated on the NMI.
1.

Conventional interrupt requests by an 1/0 device (memory OY
an NBIA) when it has errors or other conditions to report
to the CPU. There are four interrupt request levels, BR7
through BR4, where BR7 has the highest priority and BR4 the
lowest.

A special CPU interrupt request caused by the assertion of
the NMI FAULT line. FAULT not only interrupts the primary
CPU, it freezes an NMI transaction silo in the CBox that
holds the state of selected bus signals for the faulting
and preceding bus cycles. All NMI nexus, including the
CPU(s),

can

are detected.

assert FAULT when certain types of bus errors

The interrupt priority

level

(IPL)

assigned

request asserted on the NMI is listed below.

Request (Device)

IPL

NMI Fault

BR7 (NBIAO)
BR7 (NBIAl)

17
17

BR6 (NBIAO)
BR6 (NBIA1l)

16
16

BR5 (NBIAO)
BR5 (NBIAl)
BR5 (Memory)

15
i5
15

RR4 (NBIAO)
BR4 (NBIAl)

14
14

X 2-28

each

1interrupt

An NBIA makes conventional device interrupt requests
by
asserting
an
1interrupt request signal and two other signals that specify the
interrupt request level, BR7 through BR4.
(The memory just asserts
a
request line; its request is always serviced by the CPU at a BR5S
level.)
The
interrupt
request
by
an
NBIA
can
be
generated
internally (an NBI interrupt) or it can be a request generated by a
VAXBI device.
For internal interrupts,
the
interrupt
1level
(as
specified
by
the
two
NMI
interrupt level signals) is BR4.
For
VAXBI device interrupts, the level (also asserted on
the
NMI)
is
the same as the VAXBI interrupt level.
That is, the VAXBI also has
four

interrupt

levels,

BR7

through BR4.

There are two copies of the interrupt request signal asserted by an
NBIA (and memory).
The NBIA signals are called DEVN LINTR and DEVN
RINTR.
Also, there are two copies
of
the
NBIA
interrupt
level
signals,
DEVN
LINTR LVL <1:0> and DEVN RINTR LVL <1:0>.
One copy
connects to the left CPU
1in
dual-processor
systems
and
to
the
The other copy
in single-processor (bounded) systems.
CPU
single
connects to the right CPU in dual-processor systems.

and
request,
When ready to service the highest priority interrupt
if the request is by an NBIA, the CPU microcode (by means of an NMI
read transaction) reads one of the NBIA's
four
vector
registers.
a vector register for each of the four interrupt request
1is
There
levels,

and

interrupt

generated

its value

vector

is used by the CPU microcode to

address

the

interrupts by each NBIA are

SCB.

generate

The vectors for locally

in page 0

the

SCB.

1is interrupting as an NMI nexus like memory,
NBIA
an
case,
this
devices
for VAXBI
Vectors
O,
1in page
also
is
whose vector
Refer
the NBIAs are allocated starting with page 1.
to
connected
to Section

1.4.3.

X 2-21

When

CPU

negates

FAULT

DETECT

line

logically
NMI

FAULT

memory

the

primary

(the

interrupt

discussed

detects

DETECT

for

the

vector
silo.

NMI

CPU

memory

line
in

Also,

fault

status

sequence.

Section

NBIA,

and

all

causing

the

just

then

Figure

page

fault,
to

nexus

fault,

FAULT

NMI

(Refer

and

beginning
a

1line.

each

detects

CPU,

the

nexus

in
at

transaction

latches
the

ORed
line

nexus

request
NMI

NBIA

asserts

generates
of

the

bus

CPU

and

bits

can

be
an

line.)

DETECTensH
DETECT<
n>H

FAULT H

freezes

the

NBIA),

examined
NMI

during

FAULT

READING CSR5

CONTROLLER

MEMORY

SCLD-138

Figure

2-9

Fault

Signal

Timing

the

2.1.7.

the

interrupt

CLEARED BY
FAIRT
FALLT

are

single

(When

the

SCB),

<causing

assert
FAULT

(including

and
is

signals

the

nexus

Conditions

There

cycle.

all

they

asserts

2-9.)

are

2.1.7

NMI

Errors

There

are

two

conventional
Faults
single

are

NMI

(when

FAULT

the

NMI

recent

the
are

bus

sequence

error

when

Also,

read

sequence

the
READ

DATA

data)

during

NMI

errors

causing

the

NBIA

(and

interrupt
interrupt
Timeout

are

continues

response,

but

received

the

to
if

transaction

CPU

the

bus

not

When

when

and

Also,

not

return

or
a

any

unlocked

X 2-23

read

and

first

longword

nexus

made

detecting

cannot

BUSY

error

the

NMI

CPU,

the

gain
a

data.

detected

retrying

unlock

is
was

using

data.

code

there

enough

sequence

CONTINUE

read

interlocked
write

errors.

the

acknowledged

timeout

receive

detected

while

class
useful

transfer.

(by

request

the

but

sequence

cycle,

the

NBIA when

transaction

does

interrupt

response,

responder.

read

memory

but

read

the

CPU

assert

return

READ

(flagging

interrupt

wins

receive
the

responder
the

not

enough

when

cycle

errors.

nexus

write

does

receive

during

data

cause

the

this

Similarly,

caused

conventional

occur
(if

from

NBIA

the

occurs

not

When
a
timeout
internally generated.

errors

NMI,

lines

timeout

memory),

read

transaction.
is

(For

causing

responder

causing

nexus)
interrupts

transactions

Errors

1lines.

the

CPU

those

any

silo.

NMI

and

all

errors

does

code

and

This

when

error

FUNCTION

RETURN

error)

the

commander

read

the

complete

error.)

parity

error

data

received

transaction

write

detected
asserted.

history

cause

faults

request.

that

write

errors:

line

determining
A

NMI

FAULT

freezes

errors,

interrupt

errors

NMI

also

types
CPU

access to
transaction)

INTERLQOCKED
is

the

A
read

set

the

responder

timeout

error

interlocked

transaction.

NMI

error checking

is summarized below.

Interrupt/

Fault

NMI Error

Error

Nexus

Checking

CPU

1/0

Memory

No Return Read Data (Timeout)
No Access To Bus (Timeout)
No Access, Busy (Timeout)
No Access, Interlocked (Timeout)
No Access, No Response (Timeout)
Interlock, No Unlock (Timeout)

I
I
I
I
I
I

YES
YES
YES
YES
YES
NO

NO
NO
NO
NO
NO
YES

Bus Parity Error
Write Sequence Error
Read Sequence Error

F
F
F

YES
NO
YES

YES
YES
YES

YES
YES
NO

2.2 DATA BUS

The data bus

(BETWEEN NBIA AND NBIB)

interconnects the NBIA and an NBIB.

The NBIA has

two

data bus ports (0 and 1) each connecting to one of the two NBIBs (0
of
consists
data bus
Physically,
and 1) that can be connected.
four

bus

cables

signal

that plug

levels

are

into the

the NBIA an

TTL.

to
Similar
2-2.
Data bus signal descriptions are given in Table
However,
lines.
address/data
32 multiplexed
are
there
NMI,
the
unlike the NMI, there are also multiplexed mask and function lines.
enables and read enables that allow
1latch
include
lines
Control
transferred
be
command/address information and read/write data to
of the
control
under
from the data bus buffers in the NBIB
and
to
signal
(and
start
Also included are handshaking signals that
NBIA.
and
NBIA
the
the end of) the CPU and DMA read/write operations that
connected

NBIBs

perform.

X 2-24

Table

Signal(s)
D

<31:0>

2-2

Data

Bus

Signals

Description
L

Multiplexed

address/data

Information

Trans-

Operation

Transferred

mitted

CPU
CPU

Write
Read

VAXBI

address/

write

data

NBIA

VAXBI

address/

NBIA

read

DMA Write
Read

read

<4:0>

Multiplexed

NBIB

address/

NBIB
NBIB

data

Memory

address/

NBIB

data

mask(and

NBIA

data

Memory

write
DMA

lines.

NBIA

status)/function

lines.

Operation
CPU
CPU

Write
Read

Information
Transferred

NMI

write

Transmitted

function/

NBIA

NMT

NBTA

read

funct

Os
DMA

Write

DMA

Read

NBIA

write mask

NBIB

NMI

write

write
NMI

mask

read

function/

data

NBIB

function/

NBIB

status

NBIA

NOTE

Function transmitted by NBIA
during CPU read is a modified
IDENT

Transfers

D
PMF

command

reading

equal

(hex)

interrupt

vector.

even

parity

bit

for

the

even

parity

bit

for

the

lines.

Transfers
MEF

linec

R
S
i
Y

X 2-25

Table 2-2

Data Bus Signals

(Cont)

Signal(s)

Number

Description

L. <n> LTCH EN
(n =5,7,9,11)

Asserted by NBIA to latch command/address information and read/write

L <n> RD EN
(n = 6,8,10,12)

INTR REQ <3:0>

data

into

NBIB.

Asserted by NBIA to read command/address information and read/write
data

from

NBIB,

Asserted by NBIB to indicate VAXBI
interrupt request(s)

INTR

VAXBI

REQ

=«

REQUEST

LEVEL

<3:0>

@)
Y,
c

received.

Asserted by NBIA during CPU read/write
to initiate VAXBI read/write (or IDENT)
transaction

NBIB.

CPU REQ PENDING

Asserted by NBIA before CPU REQ.

NXT OR CPU
DONE L

Asserted by NBIB during CPU read/write
to indicate successful completion of

CPU ERROR L

Prevents NBIB from responding to a
VAXBI read/write transaction (a DMA
request) until VAXBI transaction
initiated by CPU REQ is attempted.

VAXBI

transaction.

Asserted by NBIB during CPU read/write
to indicate VAXBI transaction did not

complete

BUF SEL L

successfully.

Asserted by NBIB during DMA read/write
to request that NBIA take command/address (and write data) and initiate

NMI

read/write

X 2-26

transaction.

Table

Signal(s)
REQ

DONE

2-2

Data

Bus

Signals

Number

Description

Asserted

NBIA

(Cont)

during

indicate
(and

it has taken
write data) from

NBIA

then

action.)
read

Asserted
indicate

address,

action,
of
DMA

ERROR

and

read

NBIA
has

data

NBIA

indicate

the

NMI

complete

one

tected

parity

trans-

longword
NBIB.

DMA

Read

NBIB

indicate

error

for

FRC

NBIB

DMA

BSY

NBIA

assert

Asserted

stall

BIIC

regenerates

transmits

Asserted
NBIB

FRC

(The

did

de-

information

(command/address or data) to be
the BIIC for transmission on
it

transaction

loaded

when

DMA

command/-

read

the

during

trans-

during

successfully.

Asserted

VAXBI.

(The

write

taken

NMI

read

write

NBIB.

NMI

transferred

Asserted

the

initiated

return

not
NBIB

initiates

DMA

command/address

CSR
PE.

error

parity

information.)

NBIB

NBIA

timeout

the

CSR

bit).

Forces

bit).

Forces

during

DMA

read/write.
BIIC

LPBCK

Asserted
a

BIIC

NBIA

loopback

read/write.

X 2-27

CSR

request

bit)

during

force
a

CPU

Table 2-2

Data Bus Signals

(Cont)

Signal(s)

Number

Description

BI RESET L

Asserted by NBIB when it receives

RESET from a connected VAXBI device.

Causes NBIA to assert NMI

ADAPT INIT H

RESET.

Asserted by NBIA to initialize NBIB
and connected VAXBI devices.

(NBIB

generates ACLO/DCLO sequence on VAXBI.)

[

(ol

Asserted by UNJAM console command oOr
programmed NBI INIT (a CSR bit).

Armemoaimdand
1
3
NBRIR has
Oy NBIB +to indicate
ASserced
an
generated
or
up
just powered

ACLO/DCLO sequence

in response

ADAPT INIT or RESET by a VAXBI device.
(Sets CSR bit in NBIA.)

BUF NMI ACLO H

Asserted by NBIA when NMI ACLO is
asserted.

BUF NMI DCLO H

the

VAXRT.

Asserted by NBIA when NMI DCLO is
asserted.
DCLO on

NBIB PRESENT H

Causes NBIB to assert ACLO

Causes NBIB to assert BI

the

VAXBI.

Asserted by NBIB (when BI DCLO on
the VAXBI is not asserted) to
indicate it is inserted in the

backplane.

X 2-28

(Sets CSR bit in NBIA.)

2.3

VAXBI

The

VAXBI

connected

the

system's

depending

I/0

upon

bus.

the

system

four

VAXBIs

configuration.

can

connects

to an NBIB, two NBIBs can be connected to an NBIA,
NBIAs can be connected to the NMI in some systems.)

two

Each

VAXBI

interconnect
for

each

NBIA)

bit

wide

synchronous

VAXBI

interfaces

VAXBI

interfaces

system

the

that are connected to the
arbitration) is performed

ZMOS
As

integrated

for

the

NMI,

other

the

nodes

NBIB,
to

all

data

transferred

parity
The

a VAXBI

nodes

the

over

the

can
node

with
and

the

memory

(including
node's BIIC,

bus

that

CPU(s)

protocol

and

processor

(together

system's

Most VAXBI
automatically by

used

with

which

the

NMI.

circuit
is

bus

(nodes).

(Each VAXBI

bus

the

interface.

VAXBI

means

read/write transactions.
However, there are additional transaction
types (to generate interrupt requests and read
interrupt
vectors,
for
node

example).
requesting

node

with

the

during
the

current

Also,
of

use

highest

bus

arbitration when
included as part
A

detailed

System Bus

there is distributed bus arbitration.
bus samples all bus
requests,
and

the

cycle

priority

then

(when

the

bus

(when

the

bus

transaction

Summary.

basic

2.3.1

VAXBI

signals

except

for

the

VAXBI

control

inactive),
is

the bus is busy, an embedded
of every bus transaction.

description

VAXBI

assumes

given

busy).

the

Each
the
bus

following

allow

bus

arbitration

cycle

the

levels

are

TTL

Chapter

description

follows.

Table

All

Signals

are
the

defined
FET

driven

clocks.

X 2-29

2-3.
LO

and

signal
LO

signals

and

the

ECL

Table

Signal(s)
D<31:00>

2-3

VAXBI

Number

Description

Multiplexed

address/data

and

transfer

address

cycles

and/or

30-bit
of

transactions.

destination

command/address
write,
cycles.

nodes

during

Information

data

during

and

decoded

lines.
and

data

cycles.

embedded

invalidate

level

during

transactions.)
during

data

IDs

arbitrating

cycles.

Specify

cycles,

length

command/-

interrupt

information

arbitration

cycles,

vector

mask

Specify

command/address
data

write,

specify

Specify
during

cycles of other
read, or vector

VAXBI

byte

mask

status

Also

command

during

write

during

specify

arbitration

read

the

and

master's

cycles.

I<3:0>

(Hex)

Command

(See

Reserved

Read

(READ)
Interlocked

note)

Read

with

Cache

Intent

(IRCI)

with

Write

Read

Write

Unlock

Cache

Intent

(WRITE)
with Cache
Write

(RCI)

Intent

Masked

with

(WCI)
Cache

Intent

(WMCI)

Write

> 0w

(UWMCI)
Masked

Interrupt (INTR)
Identify (IDENT)

with

Cache

Reserved

o oo
o

data

lines.

address

read,

(Also

Transfer

I<3:0>

Signals

Stop

(STOP)

Invalidate
Broadcast

(INVAL)
(BDCST)

Interprocessor

X 2-39

Interrupt

(IPINTR)

Table

Signal(s)

Number

VAXBI

2-3

Signals

(Cont)

Description
I<3:0>

Byte

Mask

XXX1

Write

Byte

XX1X

Write

Byte

X1XX

Write

Byte

1XXX

Write

Byte

NOTE

Broadcast
I<3:0>

transaction

Data

not

currently

Status

0X00

Reserved

0X01

Read

0X10
0X11

Corrected
Read Data

0X00

Reserved

Data

Read

1X10

Corrected

read

1X11

Read

Substitute,

the

line.

lines

Data,

Read Data
Substitute

1X01

Parity

used.

Data

Don't

Transfers

during

Cache

Data,

odd

embedded

Don't

Cache

Don't

parity

cache

bit

for

arbitration

cycles

and for the D and I lines during
command/address cycles, decoded ID (IDENT)
cycles,

/write

and during
(or vector)

X 2-31

data

cycles

data

when readbeing transmitted.

Table

Signal(s)

Number

CNF<2:0> L

2-3

(Cont)

VAXBI Signals

Description

Confirmation lines. Specify command/data

response by slave(s) during the data cycles
Also specify data response
of a transaction.
by node receiving data during the two bus
cycles following the data cycles of a
transaction.
CNF

ARB

<2:0>

Response

000

001
010

Illegal

011

Acknowledgment

No Ackn
Illegal

100

Illegal

101

STALL

110

RETRY

111

Illegal

Asserted

arbitrating

(ACK)

nodes,

master,

pending master, or slave to inhibit
arbitration by nodes during the next bus
cycle. The pending master is the node
winning the bus after an embedded
arbitration

BSY L

NnNNN

Asserted by master or slave to indicate

a transaction is in progress. Can also be
asserted by any node to extend the current
transaction, or (when asserted together
with NO ARB), delay the start of the next
transaction in order to perform special mode
operations

RESET L

BAD L

cycle.

such

loopback

request.

Asserted by NBIB when it generates a VAXBI
ACLO/DCLO sequence during NBIB initialization.
Asserted by connected VAXBI device tc bootstrap
the system.
(Causes NBIA to assert NMI RESET.)

Indicates one or more nodes detected a selftest

or other error.

Not asserted or monitored by

NBIB.

STF L

Fnables fast selftest mode
asserted

or monitored

X 2-32

in all nodes.

by NBIB.

Not

Table

Signal(s)
TIME

H/L

Number
2

2-3

VAXBI

MHz

with

H/L

differentially

PHASE

NBIB.

H/L

differentially

MHz

generated

with

H/L

TIME

cycle

Indicates

limits.

NBIB.

power

Asserted

all

for

(ECL)

clock

conjunction

reference

for

nodes.

below

NBIB

clock

nodes.

driven

Used

(ECL)

conjunction

reference

all

to provide

timing

provide

cycle

timing

driven

Used

VAXBI

(Cont)

Description

generated

PHASE

Signals

specified

(when

NMI ACLO
asserted) and by VAXBI expander cabinet
during powerup. Also asserted when NBIB is

initialized by NBIA. (NBIB generates
ACLO/DCLO sequence to simulate power-up/power-fail

Indicates

condition.)

power

below

specified

limits.
Asserted by NBIB (when NMI DCLO
is asserted) and by VAXBI expander cabinet
during powerup. Also asserted when NBIB is

initialized by NBIA.
(NBIB generates
ACLO/DCLO sequence to simulate power-up/power-fail

condition.)

X 2-33

2.3.2

Basic Timing

Signals
The clocks and basic bus timing are shown in Figure 2-10.
and synchronous control lines are asserted and
data path
the
on
are
signals
The
cycle.
bus
a
of
deasserted at the beginning
(The data path
the end of the cycle.
near
latched
and
received
control
synchronous
the
signal lines are the D, I, and PO lines;
are the CNF, NO ARB, and BSY lines.) The other control lines
lines
deasserted
and
asserted
are
(AC LO, DC LO, RESET, STF, and BAD)
asynchronously with respect

to the bus

cycle.

4——50 NS—P

TIME H _____//’————\\____//r——_q\\_____//’_—__\\\____///_-—_\\\____J//--“\\_____//F-_—\\g____
PHASE H

<
X

100 NS

=¥<

100 NS—P‘

TRANSMIT PERIOD
|

RECEIVE

PERIOD

DATA
LATCHED
SCLD-142

Figure

2-10

Basic VAXBI

Timing

2.3.3

VAXBI

address

half

Refer

Memory

Address

physical

Figure

space

VAXBI

Space

space,

1I/0

for

VAXBI

processor
to

that

writes

address,
the

when

NMI,

the

not

allocated

I/0

the

address

addresses,

the

(up

I1/0

space

must

Dbe

address

the

NMI

2000

0000

the

accessed
are

system

memory)

that

other

Gbyte

half

the

for

actually

with

address

from

(except

causes

for

where

I/O

NMI

that

NMI

memory
NMI

space.

address,

when

the

only

NBIA

the

The

and

21FF

FFFF

VAXBIs

during

the

cleared

NMI
NMI
the

reserved.)

NBIA

VAXBI

transmitted

(Hex),

Mbytes.

The
the

(The

range
same

(Hex)

rest

VAXBI

I/0O

for

each

system.

This means that when VAXBI
transaction, address
bits
<26:25>
to

VAXBI

NBIA

address

before

the

translation.

address

NBIB.

I/O Addresses

allocated

memory.

one

space.

address

transaction

NBIB

VAXBI

space
to

four)

cleared

the

NBIB,

space

bits

space,

and

modified.

The

1I/0

node's

transferred

space

transaction

responded

address

2-11.

read/write

reads

NMI

memory

VAXBI

I/0

(Hex)

[Bits

Cleared

The

sent

Addresses

<26:25>
NBIA]

2000

0000

21FF

FFFF

VAXBIO

(NBIB

2000

0000

2200

0000

21FF

23FF

FFFF

VAXBI1

(NBIB

2000

0000

21FF

2400

FFFF

0000

25FF

FFFF

VAXBIO

(NBIB

2000

0000

2600

21FF

0000

FFFF

27FF

FFFF

VAXBI1

(NBIB

2000

0000

21FF

FFFF

X 2-35

FFFF

The

Mbytes

space

for

adapter
space

I/O

each

window

space.

contains
private

space

the

VAXBI.

For

CSRs

and

nodes
is,
other

bus

(UNIBUS

allocated

The

2-11,

The

space

first

NMI

1is

bus
are

more
nexus

wused

and
for

consists

private

Figure

2-11.)

than

for

one

are

node

not

registers

have

its

address

can
the

mapping

the

block

and

Multicast
respond.
from

NBIA

private

addresses

example).

accessed

node

devices
to

node

that

converted

addresses,

each

which

registers)

another

addresses

VAXBI
space,

registers

the

offset

Window

each

again

for

contains

vector

VAXBI

(Refer

example,

interfacing
the

for

multicast

addresses

Node

addresses.

space

node,

(the
space

adapter

VAXBI.

That

specific

the

window

space

shown

Figure

node.

for

each

group

node

(8K

bytes)

registers,

iS
cal led

T
1A
the VAXBI
reguired
registers, is implemented by every node on
a
VAXBI.
The
second
group is the BIIC-specific registers.
A register in this group may

may

not

used

depending

TYyLioULT

upon

the

Loy

node

design.

All

the

VAXBI-required
and BIIC-specific
are contained in the node's BIIC.

registers (Figures 2-13 and 2-14)
(BIIC register bit
formats
and

descriptions

1.)

are

given

Chapter

X 2-36

ADDRESS(HEX)

0000

MEMORY

SPACE
(512

MB)

0000

2000

1FFF

2000

3FFF

2000

4000

2000

5FFF

2000

6000

2000

7FFF

2000

8000

NODE 0 REG SPACE
(8KB)

NODE 1

FFFF

NODE 2

2200

0000

NODE 3

RESERVED FOR
MULTIPLE VAXBI
SYSTEMS
(480

2000

BFFF

REG SPACE

(8KB)

NODE 4 REG SPACE
(8KB)
NODE 5 REG SPACE
(8KB)
oo

1/0 SPACE
(32 MB)

A000

REG SPACE
(8KB)

2000 0000
21FF FFFF

2000

REG SPACE

(8KB)

2000 9FFF

\FFF

SPACE

MB)

VAXBI

2000

1/0

0000

2001

E000

2001

FFFF

(8KB)

2002

0000

MULTICAST SPACE
RESERVED
(128KB)

2003

FFFF

2004

0000

203F

FFFF

2040

0000

NODE 15

REG SPACE

NODE PRIVATE SPACE
(3.75 MB)

ADAPTER

FFFF

207C

0000

3FFF

FEFF

207F

FFFF

2080

0000

21FF

FFFF

)

2043

WINDOW

SPACE #0
(256KB)

ADAPTER WINDOW
SPACE #15
(256KB)
RESERVED
(24 MB)

SCLD-426

Figure

2-11

VAXBI

X 2-37

Address

Space

ADDRESS (HEX)

[SEE

NOTE]

bb + 00

]
VAXBlI

REQUIRED

REGISTERS

BIIC CSR SPACE
(256 BYTES)

BIIC

REGISTERS

NOTE:

SPECIFIC

REMAINDER OF 8 KB NODE
REGISTER SPACE RESERVED
FOR USER CSR REGISTERS
(NOT IMPLEMENTED IN BIIC)

BASE ADDRESS =

2000

0000

(HEX)

+ 2000

(HEX)

NODE ID

SCLD-144

Figure

2-12

VAXBI

Node

Space

ADDRESS (HEX)

[SEE

NOTE]
31

+ 00

DEVICE

04 | VAXBI

bb + 08

NOTE:

10 |

CONTROL/STATUS

BUS ERROR REGISTER
ERROR INTERRUPT CONTROL
REGISTER

INTR

DESTINATION

BASE ADDRESS = 2000

0000

(HEX)

+ 2000

(HEX)

X NODE ID

SCLD-145

Figure

2-13

VAXBI-Required

X 2-38

Registers

ADDRESS (HEX)

[SEE

NOTE]

IPINTR/STOP

IPINTR

STARTING

IPINTR

MASK REGISTER

DESTINATION

SOURCE REGISTER

ADDRESS REGISTER

bb + 24

ENDING ADDRESS REGISTER

bb + 28

BCI CONTROL REGISTER

bb + 2C

WRITE STATUS REGISTER

bb + 30

FORCE IPINTR/STOP COMMAND REGISTER

UNUSED

bb + 38

UNUSED

bb + 3C

UNUSED

bb + 40

USER INTERRUPT CONTROL REGISTER

+ 44

—
bb

UNUSED

bb + FO

GENERAL-PURPOSE REGISTER 0

GENERAL-PURPOSE

bb + F8

GENERAL-PURPOSE REGISTER 2

GENERAL-PURPOSE

NOTE:

BASE ADDRESS =

2000

0000

(HEX)

2000

(HEX)

NODE ID
SCLD-146

Figure

2-14

BIIC-Specific

X 2-39

Device

Registers

2.3.4 VAXBI Read/Write Transactions

and octaword
The VAXBI supports read/write longword, duadword,
transactions
read/write
The NBIB responds to VAXBI
transactions.
falls
address
the
addressing memory (DMA data transfers) provided
address
ending
and
starting
within a range specified by the
Also, the NBIB originates read/write
registers in the BIIC.
(longword) transactions when a VAXBI device register is addressed
by a CPU read/write.

Read/write transaction timing is shown in Figures 2-15 and 2-16.
LLike all VAXBI transactions, the first cycle is a command/address

1least one
cycle followed by an embedded arbitration cycle and at
read/write transactions, there are one, two, Or
For
cycle.
data

four data cycles depending upon the transaction length (longword,
cctaword
read/write
for
Timing
octawordj .
or
quadword,
transactions

(four data cycles)

is shown.

During the command/address cycle, the bus master {the node winning
bus and originating the transaction) transmits a 2-bit
the
transaction length code and the 30-bit memory or 1/0 address on the
It also transmits a read/write command on the I lines.
D 1lines.
allows
The command, in addition to specifying a normal read/write,
writes).
ck
reads/unlo
ed
(interlock
interlocked memory operations

However,
Read/write commands can also specify that data be cached.
intent.
cache
having
not
as
commands
the NBIB interprets all
on a
supported
not
are
s)
processor
I/O
Cached operations (by any

VAXBI

in this

(NMI-based)

system.

(discussed in Section
Following the embedded arbitration cycle
write transaction, the
a
of
and during each data cycle
2.3.8),
and the write mask
lines
D
master transmits the write data on the
(if

any)

data

cycle.

the

1lines.

Also,

if it is ready and detects no

errors, the addressed node (the slave) takes the write data and
transmits an acknowledgment (an ACK code) back to the master on the
An ACK response 1s also
CNF lines during each data cycle.
generated by the slave during the two bus cycles following the last

After

the

embedded

transaction,
detected

selected

errors)

the

also

transmits

code

arbitration

the

1lines

transmits

together
a

read

indicates

1if

the

uncorrectable

(READ

DATA

code

the

causes

caching
not

subsequent

NMI-based

ACK

when

the

response

master)

for

two

during

read
ACK

status
data

(if

data

1is

data

cycle

ready

back

response

code

SUBSTITUTE

each
it

the

lines.

wvalid,

wvalid

code).

CNF

but

READ

read

has

master

lines.

and

The

status

corrected,

DATA

SUBSTITUTE

master

and

indicates

the

with

data

and

slave

read
is

to set an error flag.) Also, to limit the
invalidation of data in
some
systems
(but
system
1like
this
one),
the
status code

data

not

the

transmitted

cycles

after

the

last

cached.

CNF

data

lines

the

write,

(this

time

the

cycle.

If there is a NO ACK response (no
responding
slaves)
during
the
first
cycle
of a read or write transaction,
it probably indicates
the master transmitted a nonexistent memory
or
I/0
address.
In
this case, the master sets an error flag and ends the transaction.
If

the

read

CNF

selected

data

lines.

master

until

response.

any

the

state)

consecutive

STALL

sets

error

transmit
read

until

ready

the

assert

cycles

for

the

longword

the

data

stalled

the

data

during
a

and

data

STALL

code

the

write

the

selected
not

slave
only

not

transaction.

following

stall

transferred)

slave

sets

causes
error

ready

stall.

slave

may
data

cause

also

ACK

undefined

(may

ACK

response

are

generate

128

ACK

transaction

write

transaction,

response,

(if

data

cause

in
no

the

first

data

has

response

retried

4096

flag.

X 2-41

and

send

master

RETRY

has

read/write

retry

cycle

transmitting

accept
may

data

generates

transaction.

may

the

transaction,

are

and

return

lines

slave
a

generates

write

same

transaction,

responses

write

can

takes

the

slave.

flag,

cycle,

data

slave
a

transmitted

not

data

stall

For

any

During

continues

lines

slave

during

the

ends

read

data

retry

data

cycle

previously
CNF

times,

lines.

the

it
the

the

or
been
If

master

VAXBI

CYCLE

C/A

DATA

LENGTH
<31:30>

LEGEND
M = MASTER
S = SLAVE
AN = ALL NODES

PDEC,D

AAN

QRBING

C/A = COMMAND/

<31:16>

IA =

30-BIT

ADDRESS CYCLE

IMBEDDED ARB
CYCLE

WRITE | WRITE | WRITE | WRITE

ADDR

<29:00>

ALL

LOwW

PRIOR

D<31:00>

DATA

DEC'D
ID
HIGH
PRIOR

¢v—¢ X

<15:00>

SOURCE

1<3:0>

WRITE

CMD

SOURCE

AAN
| MASTER

GEN

ACK

M.S

M,S

AN ASTERISK (*)

INDICATES

ACK

SLAVE MAY STALL

FOR ONE OR MORE BUSY CYCLES
A DOUBLE ASTERISK
TRANSACTION (GIVE

. S

M,AAN

|q¢——0—

M,S

UNDEFINED
.

F NTT MASKED WRITE

M,S

NO ARB L

BYTE

MASK

M,S

BYTE

MASK

BSY L

SOURCE

CNF<2:0>

NOTES:

BYTE

MASK | MASK

CHK

BYTE |

MASK FIELD
|

BEFORE TAKING

(“*) INDICATES SLAVE
RETRY RESPONSE).

(GIVE

STALL RESPONSE)

DATA (ACK

RESPONSE).

MAY REQUEST RETRY OF
SCLD-185

Figure

2-15

VAXBI

Write

Transaction

(Octaword

Length)

VAXBI

CYCLE

C/A

DATA

LENGTH
<31:30>

LEGEND

M =
S =

MASTER
SLAVE

2§N=
,

DEC'D

LOW

NODE

ARB’ING

C/A = COMMAND/

P?IQRG

<31:16>
30-BIT

D<31:00>

fikh-NODES
=

A =
READ | READ

ADDR

DATA | DATA

<29:00>

READ

| DATA

ADDRESS CYCLE

IMBEDDED ARB
CYCLE

DEC'D
ID
HIGH
PRIOR

<15:00>

1<3:0>

AAN

READ

MASTER

STAT

ACK
S

ACK
.S

M,S

M.S

CMD

S
READ

CNF<2:0>

BSY L

NO ARB

/——\M,AAN

NOTES:

S
READ

READ

ACK
S

/o
/

AN ASTERISK (*) INDICATES SLAVE MAY STALL (GIVE STALL RESPONSE)
FOR ONE OR MORE BUSY CYCLES BEFORE TAKING DATA (ACK RESPONSE).
A DOUBLE ASTERISK (**)
TRANSACTION (GIVE

INDICATES SLAVE MAY REQUEST RETRY OF

RETRY RESPONSE).
SCLD-186

Figure

2-16

VAXBI

Read

Transaction

X 2-43

(Octaword

Length)

2.3.5 Interrupt Operation (INTR, IDENT, and IPINTR Transactions)
The interrupt (INTR) and identify (IDENT) transactions are used
to
signal
and
service
conventional
device
type
interrupts on the
VAXBI.
A node can send an interrupt request to one or
more
nodes
using
the
INTR
transaction.
(As
for
the
NMI, there are four
request priority
levels:
BR4,
5,
6,
and
7.)
Then,
when
an
interrupt
fielding node is ready to service the interrupt requests
at a specific request level, it uses an IDENT transaction
to
read
an
interrupt vector from the interrupting node.
Because more than

one

node may be

read

from the

interrupting at

highest

that request

priority device

level,

based on

the

the
node

vector

Iis

ID.

The VAXBI also allows
one
processor
node
to
1interrupt
another
processor
node.
This
1is done using the interprocessor interrupt
(IPINTR) transaction.
Transaction format is similar
to
the
INTR
transaction.
However,
there
1is no need for a node responding to
the interrupt request to follow with an IDENT transaction.
This is
because the interrupt fielding node stores the vector (and alsc the
request level) information for this type of interrupt.
The interrupt fielding nodes on a VAXBI in this system are the NBIB
and
any
I/0
processors that are installed.
The NBIB fields INTR
transactions by passing the interrupt requests on to
the
NMI
and
the CPU.
It then issues an IDENT transaction to collect the vector
information when the CPU reads a vector
register
address
1in
the
NBIA.
(There are four NBIA vector registers, one for each request
level.) The interrupt requests generated on the VAXBI are
normally
from I/0 devices but they may also be from an I/O processor node.

The NBIB
<can
also
field
IPINTR
transactions
allowing
an
1I/0
processor
to
interrupt
the CPU using an interprocessor interrupt
request.
(An
I/O
processor
can
also
interrupt
another
1/0
processor
using an IPINTR.) Not only can the NBIB field an IPINTR,
it can generate one.
It can also generate
an
INTR
allowing
the
primary
CPU
to
interrupt
an
I/0O
processor with either type of
interrupt

request.

X 2-44

2.3.5.1

Interrupt

transaction
cycle,

the

(INTR)

shown

master

destination

(the

mask

corresponds

one

the

Figure

During
node)

lines.

the

master

select

one

example,

the

master

may

The

master

the
is

that

also

bit

for

data

each

adapter

node,

level

than

one

request

I/0

device

attached

same

time

and

different

level

with

D<19:16>

Request

1XXX

BR7

X1XX

BR6

XX1X

BR5

XXX1

BR4

the

embedded

service

the

This

slave(s).
sets

data

bit

VAXBI

the

slaves

field

both

the

INTR

the

NBIB

16-bit

the

mask

allowing

interrupt.

and

four

1I/0

interrupt

request level
command/address

the

shown

below.

make

This
an

allows

interrupt

cycle.
a

There

master

request

(an
more

single

INTR transaction.
(More
than
adapter can be interrupting at the
assigned request levels.)

the

Level
Priority)

Priority)

«cycle

following

«cycles,

request

any

slave

the

ACK

command

between
responds

flag.

X 2-45

command/address

selected

asserts

essentially a

transferred

error

the

transmits

during

(Lowest

interrupt

Dbeing

for

command/address

Each

nodes

signal

(Highest

arbitration

lines.
data

single

example)

one

During

possible

the

lines

for

the

interrupting.

transmits

high-order
a

Format

low-order

For

processor

2-17.

interrupting

the

Transactions

the
(a

slave

that

response

confirmation
master

ACK

and

the

CNF

cycle with
the

response),

and

intends

selected
the

master

VAXBI

CYCLE

C/A

LEGEND
M =

FESV'D
,

FIELD | DEC'D

<31:20> | ID

LOW

PRIOR

<31:16>

AAN =

ALL ARB'ING

C/A

COMMAND/

LEVEL

D<31:00>

<79:106>

MASTER

S(S) = SLAVE OR SLAVES
AN = ALL NODES

NODES

ADDRESS CYCLE .

IMBEDDED ARB
CYCLE

RESV'D
FIELD

INTR

DEST
MASK
<15:00>|

SOURCE
1<3:0>

INTR

SOURCE

GEN

CHK

CMD
M

DEC'D

ID
HIGH
PRIOR

<15:00>

AAN
MASTER | RESV'D

iD
M

CNF<2:0>

FIELD

RESV'D

FIELD

ACK

S(S)

SOURCE

VAXBI BSY L

VAXBI NO ARB L

SNl

M AAN

/
S
SCLD-18¢

Figure

2-17

VAXBI

Interrupt

X 2-46

(INTR)

Transaction

2.3.5.2 Identify (IDENT) Transactions -- As stated
previously,
interrupt
fielding
node responding to an INTR transaction does
IDENT transaction to read an interrupt
vector.
IDENT
format
shown

Figure

an
an
1is

2-18.

During
the
command/address
cycle
and
similar
to
the
INTR
transaction,
the
master
transmits the interrupt level on four of
the
high-order
D
1lines.
However,
this
1is
the
only
select
information
transmitted
and
only one of the four lines should be
asserted.
The line asserted specifies the single interrupt request
level

serviced.

Request Level

D<19:16>
1000

BR7

0100

BR6

0010

BR5

0001

BR4

(Highest Priority)

(Lowest

Priority)

During the cycle following the command/address cycle
and
embedded
arbitration
cycle,
the
master transmits its decoded ID on the 16
high-order D lines.
Only the D line corresponding to the
master's
node
ID
(plus
16)
will
be
asserted.
The transmission of the
masters ID
1s
necessary
because
there
can
be
more
than
one
interrupt
fielding
node
on
the bus, and nodes with an interrupt
pending at the specified request level may not want service by
the
node

doing

the

IDENT.

During the next bus cycle of the IDENT, the nodes wanting interrupt
service
by
the
master
must
arbitrate
for
the
bus
as
when
arbitrating to become bus master (Section 2.3.8).
(Decoded IDs are
transmitted
only on the high-order data lines, however.) The nodes
must arbitrate because only one can be serviced by the IDENT.
That
is,
only
one
node
can
become the slave and return an interrupt
make
Nodes not winning the arbitration must
vector to the master.
are
they
wunless
transaction)
(INTR
request
interrupt
another
serviced by

another

IDENT before

a request

X 2-47

can made.

After

winning

response

during

the

slave

the

bus,

the

slave

the

CNF

lines

and

may

cycles

node

would

bus

cycle.

transmit

until

the

this

I/0

set

error

flag

the

slave,

the

lines

for

the

correctly.
error

flag

node

device.)

serviced

next
an

just

for

reason,

node

the

during

may

bus

the

following

have

been

serviced.

abort

ACK

not

and

error

the

slave.

IDENT

and

interrupt

node,

and

the

request

not

The

embedded
for

during

has

response

the

bus

(not

This

bus

cycle

the

and

happen

than

already

been

serviced

one

the

CNF

executed

then

the

have
could

For

this

INTR

IDENT.

IDENT

made

node

the

request

slave

may

vector

causes

the

one

adapter
from an

have

IDENT.

the

after)

can

was

transaction.

master,

because

condition
before

ACK
lines

the

response

and

for

(An
read

cause

Once

necessarily

INTR

transaction,

transaction

service

transaction

request

ACK

arbitration

pending

will

the

lines

transmit.
to be first

ACK

issued

arbitrate

read

CNF

interrupt

initiate

condition.

may
was

the

IDENT

cycles

asserts

vector

transaction.

occurring

result

stall

cycles

become

INTR

had

detected,

arbitration
the

response

bus

the

vector

transmits

request.
bus

the

ready)
the

cannot

transaction

before

arbitrate

interrupt

occurred

win

two

similar

ready

128

end

master

error
set

the

and

response

Again,

transmits

Also,

STALL

vector

attached
sent

(if

may

win

would

then

had

already

transaction

IDENT

the

interrupt

fielding

node.

another

DMID

C/A

CYCLE

VAXBI

INTR

ARB

DATA

LEGEND
M =
S =

AN = ALL NODES

RESV'D
FIELD

<31:20> | ID
DEC'D

DEC'D

LOW

AAN = ALL ARB'ING

NODES

|DECD

|ID

APS = ALL
POTENTIAL
SLAVES

o's

MASTER |ARB'ING

PRIOR
|ID
. |SLAVES
<31:16> [<31:16>|<31:16>

IDENT
LEVEL

C/A = COMMAND/
ADDRESS CYCLE

IMBEDDED ARB
CYCLE

<19:16>

D<31:00>

DEC'D

RESV'D | RESV'D

RESV'D | HIGH
FIELD

| PRIOR

|FIELD

APS

<15:00> | <15:00> | <15:00>| <15:00>

SOURCE

AAN

M
IDENT

1<3:0>

| MASTER | RESV'D|

CMD
SOURCE

GEN

MASTER
SLAVE

CHK

VECTOR

|<08:02>|

|<13:02>|

(VAXB! NODE)

(OFFSETABLE DEVICE)

0'S

RESV'D | VECTOR

FIELD | FIELD. | STATUS

Ays

RESV'D

hsd

IF ACK RESPONSE

IN VECTOR DATA
CYCLE

FIELD

CNF<2:0>

ACK/

ACK

NO ACK

SOURCE

M.S

M.S/

M,S

M.,S

BSY L

/———\M,AAN
NO ARB L

NOTE: A NO ACK BY SLAVE IS A VALID RESPONSE INDICATING A TRANSIENT
INTERRUPT OR THE INTERRUPT HAS BEEN SERVICED BY ANOTHER NODE.
s

Esae=

BUS CYCLES BEFORE RETURNING VECTOR (ACK RESPONSE).
SCLD-190

Figure

2-18

VAXBI

Identify

X 2-49

(IDENT)

Transaction

2.3.5.3
for

Interprocessor

the

IPINTR

Interrupt (IPINTR)
Transactions
-Format
(Figure
2-19) differs from the INTR

transaction

only

master

the

command/address

1in

transmitted

interrupt
level.

for

the

arbitration
data

the

node
the

lines

cycle

the

transferred

respond

with

the

1lines.

third

cycle

slave

may

not

requests

from

the

single
data
essentially a

between
an

A
no

(the slave)
holds
master's
decoded

interrupt

INTR,

information

cycle.
lines, but

high-order

because

interprocessor

must

the

fielding

necessary

selection

low-order

Instead,

high-order

the

ACK

and
the

master.

X 2-58

This

the
1ID is
of

cycle
command

master
during

transmitted

1is

1is
is

because

the

IDENT.
enabled

current

This
to

master.

following
the
embedded
confirmation cycle.
(No

slave.)
cycle

the

interrupt
request
transmitted on the

an
be

by
mask
1level

destination
interrupt

least

one

error

flag

slave
is

set

VAXBI CYCLE

C/A

LEGEND
MASTER | DEC'D
DEC'D
ID
ID
LOW

M =

<31:16> | PRIOR
<31:16>

IP
INTR

ALL ARB’ING

COMMAND/
ADDRESS CYCLE

IMBEDDED ARB
CYCLE

NODES

DEC'D

DEST
MASK

AAN =

C/A =

RESV'D
FIELD

D<31:00>

MASTER

S(S) = SLAVE OR SLAVES
AN = ALL NODES

<15:00>

HIGH

PRIOR

<15:00>

SCURCE
1<3:0>

SOURCE
s}

AAN

IPINTR | MASTER | RESV'D

GEN

CHK

CMD

CNF<2:0>

S(S)

M
BSY L

VAXBI

NO ARB L

RESV'D

FIELD
ACK

SOURCE

VAXBIl

FIELD

SCLD-191

Figure

2-19

VAXBI

Interprocessor

X 2-51

Interrupt

(IPINTR)

Transaction

2.3.6

STOP Transactions

for
(the NBIB,
The STOP transaction is used by processor nodes
cannot
they
where
state
a
into
nodes
other
the
force
to
example)
issue any more VAXBI transactions while retaining as much error and
other status information as possible. However, nodes must still be
able to respond to VAXBI transactions so that the retained status
A node can be
information can be examined by another node.
operation.
selftest
a
forcing
by
operation
returned to normal
STOP transaction format (Figure 2-20) is similar to INTR and IPINTR
format except that the master transmits only a
transaction
the
during
lines
D
the
on mask on
destinati
transaction
at
and
addressed
be
may
slave
one
than
More
cycle.
command/address

least one must generate an ACK response on the CNF lines or the
Like the INTR and IPINTR transactions,
master sets an error flag.
the single data cycle following the
in
the response is generated
(No data is actually transferred over
cycle.
n
embedded arbitratio
the D lines

in this cycle.)

X 2-52

VAXBI

CYCLE

C/A

LEGEND
,

RESV'D | DEC'D

FIELD

M =

MASTER

S(S) = SLAVE OR SLAVES

| ID

<31:00> | LOW

PRIOR

AAN

<31:16>

C/A =

D<31:00>

RESV'D
FIELD

.
INTR
DEST

MASK

ALL NODES
ALL

ARB’ING

COMMAND/

ADDRESS CYCLE

IMBEDDED ARB
CYCLE

DEC'D
ID

HIGH

<15:00> | PRIOR
<15.00>

SOURCE

1<3:0>

STOP

SOURCE

GEN

CHK

AAN
| MASTER | RESV'D

FIELD

| RESVD

| FIELD

CNF<2:0>

ACK

SOURCE

S(S)

VAXBI BSY L

VAXBI NO ARB L

/1_/

/
M.AAN

SCLD-192

Figure

2-20

VAXBI

X 2-53

STOP

NODES

Transaction

2.3.7

The

Invalidate

(INVAL) Transactions
transaction (Figure 2-21)

invalidate

signal

other

valid.

The

invalid
slave

nodes
bus

block

may

data

respond

with

The

parity
no

not
by

invalidate

(NMI-based)
turned
and

single

response

off

memory
thus

master
of

transaction's

and

that

data

the

address

and

that
data

command/address

cycle.

ACK

response

CNF

cycle.

(No

checked

error

node,

Any

not

local
VAXBI

used

on
is

X 2-54

VAXBI

must

because

on)

the
one

the

transferred

there

master.

connected

passed

could

than

during

the

have

longer

length

cycle.)

node

lines

this
set

not

actually

nodes
are

turned

during

NMI

data.

the

data

This

the

(if

flag

processor

previously.

the

processor

the

any

stated

cached

generated

transactions

allows

have

transaction

caches

may

transmits

data

system.
as

they

their

addresses
to

the

contain

this

caches
of

VAXBI,
invalid

VAXBI

CYCLE

C/A

LENGTH

<31:30>

LEGEND
M =
,

IDDECD

<29:00>

D<31:00>

‘

ALL

C/A

PRIOR

| <31:16>

ADDR

= SLAVE OR SLAVES

AAN =

30-BIT

MASTER

S(S)

RESV'D

=
=

FIELD

NODES

QLL ARB’ING

CgslidsAND/

ADDRESS CYCLE

IMBEDDED ARB

CYCLE

DEC'D
ID
HIGH
PRIOR

<15:00>

SOURCE
1<3:0>

M
INVAL

SOURCE
Po

CMD
M

ot V1

AAN
| MASTER | RESV'D

ID
M

(€1 =d)

CHK

SOURCE

VAXBI BSY L
VAXBI

NO ARB L

FIELD

sy s

HEOSV D

FIELD

S(S)

SCLD-188

Figure

2-21

VAXBI

Invalidate

X 2-55

(INVAL)

Transaction

ration

2.3.8 Bus Arbit
the bus is
A node may request the bus during any bus cycle when the
embedded
during
bus
It may also request the
inactive.
Dbusy.
1is
bus
the
arbitration cycle of any VAXBI transaction when
the
has
it
if
and,
ts
Each requesting node monitors all reques
either
master
bus
as
highest priority, assumes control of the bus
ss) or at
in the next cycle (when there is no transaction in progre
during
bus
the
the end of the current transaction. If a node wins

embedded arbitration cycle, it is called the pending bus master

until it assumes control of the bus.

asserting
2.3.8.1 Bus Requests -- A node requests use of the bus by
2-22,
Figure
in
shown
a D line that corresponds to its node ID. As
of
one
or
lines
the line asserted may be cne of the 16 high-order
ty
priori
high
are
The low-order lines
the 16 low-order lines.
Within
are low priority requests.
lines
rder
high-o
The
ts.
reques
the
with
node
the
ecach group of high or low priority requests, has the highes
t
lowest ID (lowest numbered D line asserted) always has a higher
t
reques
priority. Of course, any high priority
priority than any low priority request.

VAXBI

LINES

NODE

16 15

31
DATA

‘

LOW PRIORITY REQUEST LINESI
1

.......

]

REQUEST LINES
HIGH PRIORITY.......
l I
l

0 15

LOWER <

PRIORITY

) HiGHER

NOTE: NODE ASSERTS EITHER A HiGH OR LOW REQUEST LiNE TC ARBITRATE FOR VAXBIL
SCLD-183

Figure 2-22

Bus Arbitration Request Lines

X 2-56

2.3.8.2

Arbitration

priority
mode.

There

are

Fixed

high

Fixed

low

only

the

than

does.

All

nodes

the

some

1in
its

access

high

(higher

its

low

bus

mode

ensures

priority

may

applications,
request

further

low

priority

Control

bus

mode.

request

priority)

priority

master,

line.

which

arbitration

asserted

current

various

times

during

1length,
is

mode

cycle

the

The

any
a

nodes
and

ARB

requesting
pending

the

is,

except

will

requesting

for

to
bus.

nodes

requests

the

shown,

bus

always

the

other

priority

will

any

arbitration

BSY.

the

bus.

masters

depending

responses

asserted

bus

That

low

and

the

programmed

programming

2-23.

arbitration

transaction

and

always

access

can

when
by

(only

Figure

signals,

1line

equal

rapid

mode.

enhanced

asserted

the

requires

priority

two

ARB

the

robin

1its

high

robin

priority

lower

node

controlled

its

arbitration

asserts

illustrated

that

round

type,

has

high

embedded

high

Arbitration

round

dual

its

the

node

ARB

asserts

during

real-time

operate in fixed
be asserted).

operate

time,

lines

dual

fixed

assert

2.3.8.3

ID
I

node

master

other

nodes.

special

Also,

VAXBI

the

transaction.

all

operate

bus

any

the

average,

for

asserts
on

priority

programmed

the

bus

node
depends

modes.

requesting

the
line

robin

store

asserted

Whether

priority

normally

mode,

low

three

round

are

Modes
its

Dual

this

the

Nodes

1line

and

upon

generated.
during

the
The

the

slave

also
at

transaction
net

result

following

bus

transaction

cycles.
1.

Null

<cycles

(no

bus

arbitration

progress)

Command/address

The

last

pending

data
bus

cycles

cycle

transactions

master

X 2-57

unless

there

1is

REQ

_»|

IDLE

'NO ARB

i NO ARB * REQ
WIN *

BSY

CYCLE

¢ LOSE

ARB

PENDING

MASTER

WIN » BSY

lBSY

|«

MASTER

BSY

SCLD-1954

Figure

2-23

Arbitration State

Diagram

BSY is asserted only by the
current
master
and
slave
during
a
transaction.
The master asserts BSY during the command/address and
embedded

arbitration

cycles.

Both

the

master

and

slave

can

assert

BSY
during
data cycles as for the NO ACK signal.
BSY can also be
asserted to extend a transaction and, together with NO ARB,
during
special
mode
functions
as
well
(Section
2.3.8.5).
BSY is not
asserted during the following bus cycles.
A

Null

Arbitration

s
a

cycles

(when

there

1is

transaction

progress)

The

last

cycle

transactions

special mode

functions

When

ARB

the

1is

asserted,

not

cycle.

When

nodes

may

arbitrate

for

1is

not

asserted,

BSY

the

node

bus
may

during
begin

transaction in the next cycle.
For example, a node winning
a
bus
arbitration
when
BSY
=
0
becomes
bus
master
and
begins the
transaction in the next
cycle.
(Refer
again
to
Figure
2-22.)
a node wins the bus during the embedded arbitration
Similarly,
1if
=
cycle when BSY = 1, it must wait as pending bus master until BSY
can begin its transaction in the next cycle.
0
before
it
Timing
for NO ARB and BSY during typical bus operations is shown in Figure
2=-24.

2.3.8.4

Extending

extend

The

additional

transaction
transaction

2.3.8.5
A

bus

Special
by

the

Mode

node

called

busy

BSY
enter

and

asserts

(The

and

paths

the

bus

to
length.

activity

transaction.

discussed

start

STOP

the

Both

BSY

bus

some

and

special

may

transaction,

ARB

mode

may

functions.

may

the

assertion

not

BSY

transaction until the special mode
signal is asserted to identify

ARB

operation

function.)
For
example,
a
node
cannot respond to bus transactions

prevent

special

loopback
1is
complete.
reading or writing one of
data

nodes

stop

another

previously

other

loopback
BSY

the

node

STOP mode.

extending
the

cycles,

delay

between
of

BIIC

stall

properly

Functions

completed.

may be asserted by a
cycles beyond its normal

start

operation

BSY

execution

when

doing
1t

during

1is

assert
it can

transaction

function

one

is ready to respond
node responding to

may
until

progress.
delays

Transaction

cycles,

until the node
For example, a

asserted

transaction

mode
ARB

any

transaction

A
loopback operation is
its own
BIIC
registers

only.

X 2-59

until

the

when the node is
wusing
internal

TRANSACTION

NULL | ARB | C/A | iA

CYCLt

MASTER

TRANSACTION 2

|DATA|

ARB | C/A | iIA

PENDING
MASTER
ARB’ING
NODE(S)

BSY L

NO
ARB L

J‘TRANSACTION 3

|DATA|DATA|

Me—

C/A | IA

|DATA|C/A

B.C

N\
N

N\
AN

SCLD-185

Figure

2.3.9

VAXBI

Required

the
l.
2.

2-24

VAXBI

Arbitration

(Example)

Errors

error detection

by VAXBI

nodes

following:
Parity Checking
Transmit Check Error
Protocol Checking

Detection

X 2-60

(done

the

BIIC)

consists

2.3.9.1

Parity

Except

for

nodes

embedded

generated)
embedded

Checking

for

the

The

VAXBI

and

cycles,

only

checking

has

cycles,

information

arbitration

generating

arbitration

single

the

on the D
and
I-line parity

parity

during

parity

VAXBI

1
(w

lines.
genera

below.

Cycle

bit

cycles

Parity

Generating

Checking
Node(s)

Node

Command/Address

Master

All

Embedded

Master

All

Decoded

Write
Read

Arbitration
ID

(IDENT)

Data
(Vector)

Data

Null
NOTE:

All

nodes

null

When

bus

error

detects

during

participate

transmit

the

made

during
when

the

The

the

are

error,

BIIC)

(see

lines

Slave(s)

note)

are

asserted

FrvrAr

master

the

master

only

node

lines.

When

the

compare,

the

master

when

ARB,

and

does

the

generates

transaction

node
an

also

master

not

sgets

“All

(=3

The

F£1

Ve
L_Lbly

same

node).

and

decoded

X 2-61

(if

type

state
Mt

enabled).
aborted.

wuo

the

A am e~

trans

asserting

(if
not

transmi
flag

ILC

infor

request

The

error

other

asserted

request

progress,

ir
not

information

the
o

the
does

sets

should

L\ P

when
lines

transmitting

slave

detect

1interrupt

1is

interrupt

aborted.

detect
transacti

the

data,

not

transaction

and

(by

error

that
IDENT

and

generates

{ A
LA

does

and

pari

write

the

bad

cycle.

I ,

received

command/address,
the

flag

1nterrup

type

One

errors.

raYalk
=
et L
R

error

~l
apnnuw¢cuyc
K

nodes

cycle

arbitration

detecting

nct

interrupting
ID

sets

generates

Nodes

IDENT

Check

and

enabled.

decoded

the

Again,;

parity

information

cycles

error

that

Also,

check

with

All

the

transmitted

received

N/A

cycles

Transmit

T~
8
S
@

Master

hal® S

command/address.

Slave

(in

interrupts

command/address

error

Potential

Slave

cycle.

node

error

check

Master
Master

BS
VAX

regi
Howeve

VAXRBI
2.3.9.3 Protocol Checking -- The following errors 1in
by a
detected
is
transaction execution are checked. When an error
s
generate
and
node, it sets an error flag in its bus error register
an interrupt request (if enabled).

NO ACK to Multi-Responder
received

Command

Received

ACK response for an INVAL,

STOP,

master

INTR, or

IPINTR command.

1Interlock Sequence Error - A node successfully completed
transaction that was not preceded by a
unlock write

corresponding read interlocked transaction.

1IDENT Vector Error - An ACK response was not received by
master indicating the vector was not correctly
the
received by

the

slave.

Read Data Substitute Error - A read data substitute (or
reserved) status code was received with read (or vector)
data and no parity error was detected.

Retry Timeout - The master received 4096 consecutive RETRY
responses from the slave for the same transaction.

Stall Timeout - The slave
(causes
responses
STALL

transmitted 128 consecutive
to abort the
slave
the

transaction).

pending

Bus Timeout - A node was unable to

Nonexistent Address - A master received no response

Xe)

start

Illegal Confirmation Error - A master OY slave detected

transaction after 4096 consecutive bus cycles.

bus

to a
error
read/write type command, and it detected no parity
command/address
the
for
error
check
or transmit
transaction).
the
abort
to
master
the
(causes
on
informati
reserved or illegal response code.

X 2-62

CHAPTER
FUNCTIONAL

3.1

INTRODUCTION

This

chapter

describes

path
and
control
description of how

input/output

the

signal

level)

Circuit operation within
etc.) is not discussed.

3.1.1
The

NBIA Block

NBIA

major

1logic.
It
the
major

each

logic
then
1logic

elements

gives
a
elements

detailed functional
interact
(at
the

perform

logic

the

element

the

DESCRIPTION

NBI's

data

basic

NBI

operations.

(within

the

MCA,

BIIC,

major

logic

Diagram

(Figure

3-1)

consists

the

following

elements:
e

NMI

data

buffer

NPAR

MCA

NBIM

MCA

NBFD

MCA

NBAP

MCA

NBCT

MCA

DSEQ

MCA

Translation

Data

(bus)

Data

bus

buffer

buffers

(and

transaction

X 3-1

buffer)

control

sequencers

3.1.1.1

MCAs,

NMI

Data

Buffer

The

NMI

<K3:0>,

Each

MCA

data

between the NMI
data buffer

and the EBus.
(The ERus
to the DC022 transaction

The

data

buffer

contains

and

data

received

for

holding

NMI

to the
latch,
which

loaded
~¥+

ALIT LIl

two

the

32-bit

NMI,

and

information while

the

four

data

path

connecting

the

bus

the

buffer.)

latches

consists

slice

for

32-bit

holding

EBus

the

transmit

transmitted

(on

address

the

EBus)

transaction buffer.
The first latch, called the NMI receive
is latched by the trailing edge of A CLK.
The second latch,
holds
the
address/data
piped
forward
from the first, is

latched
is

that

from

buffer

8-bit

the
from

trailing
the

vYoAay1orbEnNnv

.I.k/H.LOb\./.L

edge

second

A1l

latch
~1 A

D.Lllg&b

CLK.

the

1fi+-nh

til

The

EBus

trailing
A+ 1

AR VA

iy §

9D
~ L

transmit
edge

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transferring
address/data in the opposite direction,
from the EBus
to the NMI.
An EBus receive register holds the
address/data
read
from
the
transaction buffer, and the latch holds the address/data
while it is transmitted on the NMI.
The EBus receive
register
1is
clocked
by
A
CLK
(the leading edge).
The latch, called the NMI
transmit

latch,

latched

the

trailing

edge

CLK.

The

NMI data buffer also contains the NBIA's CSRs, logic to
decode
the
NMI
address,
and
parity
generators
for
the
address/data
received and transmitted on the NMI.
Associated with the CSRs
are
interrupt
request levels asserted when a timeout error or a parity

error
NBI

(internal

powered

up.

the

NBIA

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Figure

3-1

NBIA

Detailed

Block

Diagram

3.1.1.2 NPAR MCA -- The NPAR MCA contains the logic for generating
the data and control parity bits for information transmitted on the
NMI, and for information into the NBIA's own transaction buffer.
The 1logic also checks data and control line parity for the
information received on the NMI, and for information read from the
transaction buffer. Data parity is generated and checked using the
Control
outputs of the parity generators in the NMI data buffer.
parity
of
parity 1is generated and checked using the outputs
generators

in the NBIM and NBFD MCAs.

In addition to the parity logic, the NPAR MCA contains
counters and related (confirmation check) control logic.

timeout
It also

contains CPU read/write request logic.

NBIM MCA -- The NBIM MCA is the NBIA's interface to the
3.1.1.3
NMI ID/MASK lines. It also connects to the transaction buffer and
The
to the NBFD MCA (the interface to the NMI FUNCTION lines).
function

main

of the NBIM MCA is to act as a multiplexer, to pass

either a write mask or a read/write command to/from the transaction
In addition to
buffer, depending upon the operation in progress.
multiplexing logic, the NBIM MCA contains parity generators for the
ID/mask information received and transmitted on the NMI, and parity
generators for the mask or read/write command passed to/from the
transaction buffer (over the EBus). The NBIM MCA also contains
logic to decode and save the ID on the NMI, and to decode the
read/write command passed from the transaction buffer (to the NBFD
MCA) .

3.1.1.4
latches

NBFD MCA -- The NBFD
for interfacing to

MCA
the

contains the
NMI FUNCTION

transmit/receive
(The NMI
1lines.

information is gated to/from multiplexing logic in the NBIM MCA as
described in Section 3.1.1.3.) However, its main component is the

receive sequencer. The sequencer's outputs are the principal NMI
interface control signals when information (command/address or
data) is being received from the NMI. The NBFD MCA also contains a
parity generator for the read/write command (or status) received on
the

NMI.

3.1.1.5 NBAP MCA -— The NBAP MCA contains the NMI arbitration line
It also contains the transmit sequencer. The outputs from
logic.
this sequencer are the principal NMI interface control signals when
information (command/address and data) is being transmitted on the
NMI.

3.1.1.6
NBCT
confirmation

MCA

The

NBCT

MCA

1line

logic,

the

error

CSRO),

DMA

response

end

and
a

DMA

contains

logic.

read/write

the

timeout
The

operation

NMI

response
by

3.1.1.7

DSEQ

access

4-bit

DCO022

discrete

the

1if

the

NMI

interface

DC022

DMA

NBIA's

ECL

and

TTL

the

bits

are

command

bits

data

for

Basic

3.1.1.9

Data

for

(Bus)

buffers

and

40-bit

bits

(As

4-bit

ten

Data
of

the

buffer
for

control

four

buffers

generate

DCO022

ECL

for

(L2

(External

initiation

the
data

for

transfers

the

response

RAM

chips

40-bit
connected

Each

bus

chips

bus

TTL

(discrete)

the

are

L4)

for

bus

the

sequencer
control

state

are

PALs)

Other

bus

transaction

buffer

enables.

X 3-5

two

NBIB,

from

available

The

main

port,

asserts

some

NBIB.)

FPLA
to

generate

outputs

logic

the
bus
and

internally

gated

that

data

Each

used

also

control

74F544

associated

mainly

(two

buffers,

bus

outputs,

logic

port.

the

also

received

data

shown

provide

the

not

8-bit

associated

consisting

present

the
are

data

Controls

per
for

control

two

transmitted

only

enables

bits

ten

information

one

ports

Buffer)

controls,

the

connected

buffer,

buffer

NBIA's

information

(latch)

control

read/write

(12

data, 5 bits for
information,
and

RAM

consists

wused

ports
by

(One

both

Transaction

sequencer's

the

parity.

and

NBIA.

control

the

status

for

DMA
(and

data

location

used.)

write

each

address

port,

L3)

(and

the

buffer

for

that

port).

stores

16-location
DC022

The

data

and

FEach

transaction

additional

Bus

PALS.

address

The

mask/read

transaction

are

the

read

enables

and

the

-—-

bus

chips.

buffering

3.1.1.10

bus

its

sequencer
the

(or

requests.

timing

Buffers

(L1

for

function
assert

the
DMA

generated.

The

controls

Buffer

control

data

latch

40-bit
two

and

each

transceiver

NBIB.

signals
DONE

sequencer

(via

read/write

and

reserved

write

read/write

Appendix

one

DMA

read/write

interfaces.

32
read/write

used.)

are

and

loaded

The RAM chips have
independent
ECL
and
TTL
simultaneous
asynchronous
read/write
operations

used),

the

control

controls

monitors

consists

buffer

enable.)

then

parallel.

allowing

enable

and

Transaction

buffer

contains

write

also

CPU

MCA

transaction

read

necessary)

interface.

and

NBIB(s),

NMI

3.1.1.8

DSEQ

DCO022

generates

the

transaction

The

the

address

from

retry,

1logic

requests

the

MCA

(outputs

logic

asserting

ERROR) .

controls

interrupt

encoder

DC022

the

cause

generate

3.1.2
The

NBIB

Block

Diagram

(Figure

3-2)

consists

the

following

major

logic

elements:
e

Data

bus

BCI

data

Parity

Data

Length

and

interrupt

Master

and

slave

BIIC

VAXBI

buffer

read/write

clock

Data
to

10)

Bus

buffers
four

74¥544
40-bit

the

are

used..

Data

used.)

One

Buffer

Again,

The

these
chips
information.

buffer

the

(L3/L5)

other

(L4/L6)

each

buffer,

one

VAXBI

address

L6)

1is

for

information

3.1.2.3

the
and

generator

and

command/status
VAXBI

group

data

only

data

bus

circuits

generate

well

translate

NMI

are

format,

four
by

the

74F373

bits

1latch

provide two 40-bit
each
buffer
are
transmitted
received

(L3

L4)

Another

from
is

the
the

for

group

command/status/mask

Logic

information

available

uses

to
1in

gives

received
for

are

the

(L5

line)

bit.

When

information

buffer

codes

the

buffer

latches

parity

PAL

L2)

information

buffer
there

This

information

VAXBI

data

and

transferred.

Translation
the

chips.

L1,

for

bus
that

information

L8,

BCI

1is

bits

single

and

between

information,
from

the

Parity

transferred

four

for

data

except

are configured
(Only 37 bits

BIIC.

bits

(L6,

NBIA

latch

L1)

and BCI data buffer, parity
(and
check)
parity
for
the

command/status

codes.

The

translated

from

NMI

format,

depending

upon

the

flow

and

NBIB.

NBIB's

the

BIIC,

and

]

BCI

Ten
of
for BIIC

L9,

buffers

3.1.2.2

The

transceiver

transmitted

chips.
buffers

buffer

L7,

buffering

logic

sequencers

and

port

Buffer

bus

(L5,

control

driver/receiver

Data

data

logic

control

NBIB,

buffer

translation

3.1.2.1
(instead

buffer

and

similar
40-bit

data

the

VAXBI
of

information.

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oy

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Figure

3-2

NBIB

Detailed

Block

Diagram

3.1.2.4

Data

read/write

(latch)
buffer

Buffer

enables,
and

3.1.2.5

the

and

VAXBI

lines
PAL.

(and

address

DMA

The

request

1is

length

bit)
An

logic

asserted

levels

transaction.

decoder

output

when

clears

the

also

1is
stores

the

The

the

transaction

(stored)

length

the

BIIC

set

latches

transaction

length

lines

beginning

then

the

signals

stores

lines

the

has

interrupt

the

3.1.2.6

Master

Each

1in

and

the

Slave
NBIB

Port
are

Sequencers
the

master

request

during

The

INTR

port

and

principal

slave

of
the

asserting

received,

—--

code

been

and

interrupt

during
lines,

certain

when

transaction.

elements

control

logic

IPINTR

state

PALs.

state

data

the

associated

The

data

stores

three

=--

counter

the

data

buffer
read and write
between the data bus

store

the

interrupt
on

The

received

length

asserted

Logic

logic

consists

appropriate

consists

Control

Each

internal

the

transferred

control

BCI.

complete.

(BR)

information

the

transfer.

transfer

Interrupt

when

control

buffer.

interrupt

Control

asserting

data

and

the

transmitted

causes

BCI

Length

logic

Read/Write

control,

IDENT

control

sequencers.

consists

of
an
FPLA
and
two
PALs.
The
first
sequencer
to the BIIC's master port and controls operation during
read/write
operations.
That
1is,
it
initiates
the
VAXBI

interfaces

read/write
through
slave

the

port
also

responds

the

state

second

fielding

read/write

then

(like

the

transfer

DMA

interrupt

INTR/IPINTR

master

through

and

the

sequencer
during

and

BIIC

the

port

NBIB

then

connects

(by

means

the

read/write

BIIC's

operations

requests.

That

transactions

is,

received

sequencer)

controls

means

its

information

the

present

outputs.

BIIC
as

and

user

the

case.)

Its

consists

The

interface

consists

control/status
defined

to,

133-pin

control

the

“MOS

and
the

and

logic

parity,

master

signals

logic

NBIB

equivalent

VAXBI

Table

general-purpose

address/data,

functionally

response

BIIC

standard,

control

transactions

3-1.

integrated

interface

node

corresponding

port

the
the

NBIB,

the

BCI.

(I)

that

the

VAXBI

this

The

1lines

VAXBI

(and

lines.

RBCI
that
It

miscellaneous)

1initiation
BIIC.

circuit

between

(the

called

information

slave

3.1.2.7

are

and

controls

operation

information

serves

also

the

VAXBI

The

controls

during
to

transactions

outputs)

NBIB.

and

BIIC,

transfer

IDENT

state

and

present

its

CPU

BCI

of,

and

signals

the
are

3.1.2.8
clock

VAXBI

for

the

Clock
VAXBI

VAXBI clock driver chip
receiver
contained
1in

receiver
designed

Driver/Receiver —- The

NBIB

result,

connected

BCI

Line(s)

D<31:00>

I<3:0>

BCI

RQO<K1:0>

Number

3-1

BCI

Bidirectional
all

tri-state

address

Bidirectional
to

transfer

and

write

and

mask.

(Refer

Request
perform

driver

used

transfers.

lines
read

used
status,

Table

2-3.)

used to generate
BCI D and I 1lines.

lines that cause the
a VAXBI transaction,
or

BIIC to
a loopback
diagnostic mode.

enter

Request

VAXBI

Request

Transaction

~Loopback

abort

line

the

Request

Diagnostic

Master
to

lines

command,

Bidirectional line
odd parity for the

Mode

that

current

causes

master

the

BIIC

port

transaction.

BCI

RAK

Request acknowledge line asserted by
the BIIC to indicate it has initiated
a transaction requested by the master
port.

BCI

NXT

line

asserted

the

BIIC

request that the next data word be
asserted on the BCI (for writes),
and that the current data asserted

on
BCI

MDE

the

contains

The

data

tri-state

the

<1:0>

Description

BCI

MAB

generates

Signals

transaction,

BCI

are custom bipolar integrated
circuits.
to drive sixteen clock receivers.

for

BCI

in addition to
the
standard
VAXBI
clock
all
nodes.
Both the clock driver and the

Table

Signal

to.

the

Master

the

BCI
data

BIIC

address

to
be

X 3-9

valid

enable

request
asserted

(for
line

asserted

that
on

reads).

the

command/BCI.

Table

Signal
BCI

Line(s)

RS<K1:0>

Number
2

3-1

BCI

Response lines that specify the
confirmation code to be asserted by
the BIIC (on the VAXBI CNF lines)
in

response
on

CNF

VAXBI

Resulting
CNF

ACK

STALL

STALL,

ACK

RETRY

RETRY,

ACK

the

latch
BIIC

data
to

Select
VAXBI

SC<2:0>

enable

when

code

BCI

INT<7:4>

Buffered
f

and

asserted

that

line

VAXBI

asserted

read

data

has

selected

used

Interrupt
the

ACK

the

BCI.

been

the

BIIC

order

the
to

information.

BIIC

give
(These

NBIB.)

synchronized

version

synchronized

version

request
to

asserted

SEL

selection

not

and

progress.

that

lines

Buffered
AC

line

asserted

asserts

BI
-

L B¢

the

detailed

BCI

ACK

transaction.

lines

enable

indicate

request

line

Select

ACK

indicate

BCI

Code

Slave

not

ACK,

asserted
SEL

BIIC

Response

BIIC

BCI

transaction.)

ACK

Command

lines

and

always

Code

command/cycle
SDE

code

BCI

command/address
(NO ACK

involved

<1:0>

cycles.

asserted

BCI

CLE

(Cont)

Description

data

BCI

Signals

lines

generate

that

VAXBI

cause
INTR

transaction.
BCI

<4:0>

Event code lines used
significant events in
the

VAXBI.

X 3-10

to indicate
the BIIC or

Table

3-1

BCI

Signals

(Cont)

Signal
Line(s)

Number

Description
BCI

EV<4:0>

Mnemonic

Description

00000

00001

MCP

Master

00010

AKRSD

ACK

received

00011

BTO

Bus

timeout

EVENT

--—

Port

transaction
for

slave

complete
read

data

00100

STP

Selftest

00101

RCR

RETRY

00110

IRW

Internal

00111

ARCR

Advanced

RETRY

01000

NICI

NOACK

illegal

01001

CNF

received

NICIPS

(INTR)

NOACK

illegal

CNF

received

(Force

01010

AKRE

ACK

01011

IAL

IDENT

passed

CNF

received

(as

master)

written

CNF

received

IPINTR/STOP)
received
ARB

for

error

vector

lost

01100

EVS4

External

vector

selected

01101

EVS5

External

vector

selected

01110
01111

EVS6
EVS7

(RBR5)

External
External

vector
vector

selected
selected

(BR6)
(BR7)

10000

STO

Stall

10001

BPS

Bad

timeout

parity

detected

received

(BR4)

(as

slave)

10010

ICRSD

Illegal

10011

BBE

Bus

busy

10100

AKRNE4

ACK

received

for

nonerror

10101

vector

(BR4)

AKRNES

ACK

received

for

nonerror

vector

(BR5)

CNF

received

for

slave

data

error

10110

AKRNE®6

ACK

received

for

nonerror

10111

vector

AKRNE7

(BR6)

ACK

received

for

nonerror

vector

(BR7)

11000

RDSR

Read

data

status

11001

ICRMC

Illegal

11010

NCRMC

11011

BPR

Bad

ACK

CNF

received

CNF

received

parity

received

11100

ICRMD

Illegal

11101

RTO

Retry

11110

BPM

Bad

11111

MTCE

Master

X 3-11

substitute

reserved

received

CNF

for

received

command

(data

cycle)

timeout

parity

received

transmit

(as

check

master)

error

3.2

INITIALIZATION/SELFTEST

3.2.1
Basic NBI Initialization
The NBIA and the NRIBs connected to it are initialized
at
powerup
a programmed NBI INIT (when the ADAPTER INIT control bit is set
by

in the NBIA),

and by an UNJAM console command.

command

UNJAM

The

does
everything
a powerup or programmed NBI INIT does except that
it does not clear the state indicators in the NBIA's control/status
registers.

Control

bits

are

cleared.

One is when a control bit

Two operations initialize just the NBIB.
(NODE

RESET)

1in

the BIIC's VAXBI

control/status

is set.

connected
a
from
received
1is
Another is when a BI RESET signal
VAXBI
device
(a
VAXBI
to CI adapter, for exampie).
Although BI
RESET does
not
directly
initialize
the
NBIA,
it
does
do
it
That
the NBIA to assert RESET on the NMI.
causing
by
indirectly
is, the NMI RESET signal initiates a system bootstrap
sequence
Dby
during the sequence, initializes the NBIA and
which,
console
the
reinitializes

the NBIB,

by means of

a programmed NBI

INIT.

NBIB
set,
1is
bit
control
RESET
NODE
BIIC's
the
Except when
the assertion of DCLO on the VAXBI.
by
<caused
1is
initialization
signal;
DCLO
received
a
(Setting the BIIC control bit simulates
actually asserted on the VAXBI.) Furthermore, the BI
not
is
DCLO
DCLO signal, and also BI ACLO, are asserted by the NBIB itself.
During powerup,

assert

ACLO

is NMI ACLO and DCLO

and DCLO.

(Circuitry

that

<cause

the

programmed

©NBIB

in an expander cabinet also

asserts BI ACLO and DCLO during powerup.)

NBI

INIT,

or BI RESET cause the NBIB to generate a simulated
command,
UNJAM
failed
rup sequence (just as if power had
power-fail/powe
ACLO/DCLO
ACLO
asserts
normally
NBIB
the
Because
restored).
been
then
and
NBIB
an
initialized,
is
it
when
VAXBI
the
on
DCLO
and
initialization
also
initializes
all the connected VAXBI devices.
After initialization is complete (both BI AC LO and DCLO have
been
deserted),
the
NRIR sets a POWRRUP status bit in the NBIA causing
it

to generate

interrupt

request

X 3-12

the

CPU.

NBI

initialization

summarized

Table

3-2

NBI

Table

3-2.

Initialization

Initializing
Signal
NBI

INIT

(NBIA

CSR)

NBIA

NBIB

INIT

ACLO/BI

sequence

NODE
NMI

RESET
UNJAM

(BIIC

CSR)

N/A

INIT

(not

status
BI

RESET

DCLO

(INIT)

bits)

N/A

ACLO/BI

sequence

ACLO/BI

sequence
NMI

ACLO

N/A

ACLO

NMI

DCLO

INIT

DCLO

X 3-13

DCLO

(INIT)

DCLO

(INIT)
(INIT)

3.2.2

BIIC

Initialization/Selftest

During NBIB initialization, BI DCLO causes the NBIB's
the

BIIC

following:

Load the node

Load

the

ID in

NBIB

its VAXBI control/status register.

module

its

1level

revision

device

Set the USER PARITY ENABLE bit

its bus error register.

1f
selftest.
Then, when BI DCLO is deserted, the BIIC performs a
the SELFTEST STATUS bit in the
successfully,
completes
test
the
the
on
LEDs
two
the
and
VAXBI control/status register is set,

module

(visible from the front of the cabinet)

are

lit.

USER
the
and
1level,
revision
For the BIIC to load the node ID,
PARITY ENABLE bit, the NBIB logic must drive nine of the BIIC's BCI
1ID,
The node
interface lines during the time BI DCLO is asserted.

by the ID plug inserted in the backplane, is
determined
is
which
1is
which
level,
revision
The
1lines.
I
four
asserted on the
Jjumpers (etch) on the module, is asserted on four of
by
specified
the
bit,
To set the USER PARITY ENABLE
the data lines (<19:16>).
This bit disables VAXBI
NBIB logic deasserts the parity (P0) line.
information
transmitting
parity generation by the BIIC when it is
by the
supplied
is
that
VAXBI
the
on
data)
or
s
(command/addres
the
to
supplied
1is
NBIB)
the
in
The parity bit (computed
NBIA.
information to be transmitted.

BIIC with the

light

the LEDs after successful completion of

the BIIC selftest,

sets a flip-flop (BCI STPASS)
sequencer
port
master
NBIB's
the
on
code
whenever the the BIIC asserts an STPASS (selftest passed)
causes
low,
asserted
The flip-flop output,
<code lines.
event
its
+5 V to be applied across the two LEDs (and a
resistor)
connected
in
series.
Both
LEDs
are
1lit
because
there
1is
no selftest
implemented for the NBIB logic.
(In some VAXBI nodes, one
LED
is
the
BIIC
selftest
indicator, and the other is the user interface
selftest

3.2.3

indicator.)

Powerup

The power-up

sequence

shown

Figure

3-3.

system

power

comes
on,
NMI ACLO and DCLO (generated in the CPU cabhinet's power
supply) are both initially asserted.
The two signals, received
by
FETs
1in the NBIA, are asserted on the data bus to each NBIB.
Each
NBIB then uses the signals to drive FETs connected to the
BI
ACLO
and DCLO lines.
Thus, BI ACLO and DCLO are asserted as long as NMI
ACLO and DCLO are asserted.
They can be
asserted
1longer
1if
the
NBIB is in an expander cabinet, which also asserts ACLO and DCLO on
the

VAXRBIT.

X 3-14

DATA BUS

INIT

ECL LOGIC

INIT TTL LOGIC

NBIB
INIT

VAXLI R Up
L

DCLO

——
7

BCI ACLO
¢ g/ |

BCI DCLO
€
|

—_———

BUF l\%MI ACLO >

o __p

DCLO

i
|

—-——— b

NMI/Bl DCLO L

|
—
Bl

NOTE) /}

BIIC SELF-TEST

NMI/BlI ACLO L
Bl RESET L

(SEE

BUF NMI

————>

LOGIC

ID/REV—pBIIC

ACLO
%

——
PWR UP L

ACLO
DCLO

ACLO

VAXBI

NBIA

DCLO

RESET
——

NOTE: ACLO/DCLO ALSO

ASSERTED BY VAXBI
EXPANDER CABINET

(1F ANY).

SCLD-3

Figure

3-3

NBI

X 3-15

Powerup

The

ACLO signal causes no
initialization
in
the
NBIA
or
NBIB.
However,
NMI
DCLO
1initializes
both the ECL and TTL logic in the
NBIA by asserting NBI INIT (ECL) and NBIA INIT
(TTL).
Similarly,
BI
DC LO is received by the BIIC and initializes the NBIB logic by
asserting NBIB INIT.
The received DCLO signal also causes register
bits in the BIIC to be initialized (Section 3.2.2).

The BIIC receives BI ACLO in addition to BI DCLO, and both
signals
(asserted
by
the BIIC as BCI ACLO and DCLO) connect to the NBIB's
reset/power-up sequencer.
(The signals are first
synchronized
to
the
sequencer's clock.) During powerup, the assertion of both ACLO
and DCLO cause the sequencer to also assert
RESET
on
the
VAXBI.
The
BI RESET signal is asserted while DCLO is asserted and for 100
microseconds after it is deserted.
This initiates a
"cold
start"
initialization
sequence
in the VAXRI devices.
RI RESET causes no
action in the NBIB during powerup, but the deassertion of DCLO
(as
always)
causes
the
NBIB's
BIIC
to
perform a selftest (Section
3.2.2).

When BI ACLO is deserted ending
the
powerup
sequence,
the
NBIB
asserts
BI
PWR UP on the data bus to the NBIA.
The corresponding
PWR UP status bit is then set in the NBIA's control/status register
(in
CSR1)
<causing
a CPU interrupt request.
There are two PWR UP
status bits, one for each VAXBI (each NBIB).

3.2.4
NBI INIT/UNJAM
A programmed NBI INIT causes the NBIA to be initialized
NMI
DCLO
had been asserted.
Setting the ADAPTOR INIT

just as
control

1if
bit

in the NBIA's control/status register (in CSR1l)
asserts
both
NBI
INIT
and
NBIA
INIT which initializes both the ECL and TTL logic.
An NMI UNJAM signal also asserts NBIA INIT to
initialize
the
TTL
logic.
However, NBI UNJAM (not NBI INIT) is asserted, and not all
the ECL logic is initialized.
The logic left in its current
state
are
the
status
1indicators in the NBIA's control/status registers
(CSRO and CSR1).
Both a programmed NBI INIT and UNJAM operation assert ADAPT INIT on
the
data
bus
to
each
NBIB.
Refer to Figure 3-4.
This signal
causes the reset/power-up sequencer in each
NBIB
to
generate
an
ACLO/DCLO power-fail/power-up (system reset) sequence on the VAXRI.
First, BI RESET is asserted.
Also, BI ACLO and then
BI
DCLO
are

asserted
simulating a power-fail condition.
This is followed by a
simulated power-up sequence with the sequencer first deasserting BI
DCLO,
then
BI
RESET,
and
finally BI ACLO.
As occurs during an
actual power-up sequence (Section
3.2.3),
the
simulated
powerup
initializes
the
NBIB and all the connected VAXBI devices.
During
the NBIB initialization, the BIIC registers are initialized
and
a
BIIC
selftest
1s
initiated (Section 3.2.2).
Also, at the end of
the power—-up seguence, the PWR UP status bit is
set
in
the
NBIA
causing a CPU interrupt reguest.

DATA BUS

NBIA

NBIB

é @

INIT LOGIC

VAXBI_PWR UP

RESET

ID/REV
— BIIC

BIIC SELFTEST

———
BCI DoLoe—_
~

<:> ‘/\}

ACLO | =
P90 1<

<RESET

VAXBil

RESET

ACLO

DCLO

RESET

ADAPT INIT H

VAXBI RESET L

VAXBI ACLO L |

VAXBI DCLO L

Bl PAMR UP L

SCLD-18A

Figure

3-4

Reset

X 3-17

VAXBI

Node

3.2.5
A

RESET

remote

via

(By

Connected

processor

1its

VAXBI

may

(to

VAXBI

bootstrap

Device)
the

NI)

system

adapter

asserting

node.

When

RESET

received by the NBIB, its reset/power-up sequencer asserts a
reset
signal
on the data bus to the NBIA.
(Refer to Figure 3-5.) In the
NBIA, the signal asserts NMI RESET causing the console to stop
the
CPU(s)

and

initiated
After

bootstrap

until

asserting

reset/power-up
sequence

programmed

3.2.4), r
the

NMI

the

VAXBI.

INIT

initializes

and

the

begins.

reset

sequencer

NBI

bootstrap

the

RESET

system.

signal

generates
This

The

system

bootstrap

not

deserted.
to

sequence,

UNJAM

NBIB

and

which

console

the

NBIA,

ACLO/DCLO
is

also

command

connected

the

NBIB's

power-fail/power-up
generated

(refer

VAXBI

devices

Section

before

DATA BUS
NBIA

ANJAM

UNJAM ECL LOGIC

NMI

PROG INIT
INIT ECL LOGIC

INIT TTL LOGIC

BIIC SELF.TEST

|
|

BCI ACLO® g/

ADAPT! INIT
|

BCI DoLO<€—

o
N

ACLO

DOLO
g
<

(:)

ACLO
DCLO

RESET _

Bl RESET L

Bl ACLO L

/’}

—

|
|

ADAPT INIT H

]
l

INIT LOGIC

ID/—»
REV
BIIC

I____ | CSR1
| INIT €8T

Bl PWR UP

INIT TTL LOGIC

UNJAM

NBIB

DCLO L

SCLD-18

Figure

3-5

UNJAM/Programmed

X 3-19

NBI

INIT

3.3

CPU READ/WRITE OPERATIONS

The CPU

access

can

following

the

read/write transactions to the NBIA.

data

registers

NMI

means

The transactions are longword

transfers.

Read and write the NBIA's control/status
or

registers

(CSRO

1).

Read and write registers in the VAXBI devices connected to
NBIB must initiate a VAXBI
the
this,
do
To
NBIB.
an

read/write
read/write transaction in response to the NMI
of the
any
The registers accessed may be in
transaction.
registers
16 nodes connected to a VAXBI, and includes the
in

the

NBIB's

own

BIIC.

interrupt
four
from the NBIA's
Read interrupt vectors
To read VAXBI
BR7VR).
through
(BR4VR
registers
vector
IDENT
VAXBI
a
initiate
NBIB must
device vectors, the
read transaction.
the NMI
to
1in response
transaction
no
Reading the NBI interrupt vector (from BR4VR) requires
VAXBI

transaction.

shown,
As
CPU read/write operations are summarized in Table 3-3.
masked
unlock
write
write masked and
NMI
to
responds
NBIA
the
It
transactions.
write
transactions in addition to standard NMI
as
transactions as well
interlocked
read
to NMI
responds
also
is
register
When a VAXBI
transactions.
read
standard NMI
addressed, the NBIB generates the equivalent transaction (standard,

is
When an NBIA register
masked, interlocked, etc.) on the VAXBI.
not support internal masked or
does
(which
NBIA
the
addressed,
interlocked operations)

standard

reads

executes

or writes.

X 3-20

all

NMI

transaction

types

Table

3-3

CPU

Read/Write

Interrupt
NMI

Pending

Transaction

(Note

NBI

Address

WL/WLM/WLUM

(BR4)

Summary

Progress

Resulting

VAXBI

R/W

Loc

BRx

DMA Wrt

Vec

NBI

Response

ACK,

Write

CSRx

Yes

WL/WLM/WLUM

RSVDx

ACK,

No write

WL/WLM/WLUM

BRxVR

ACK,

No write

WL/WLM/WLUM

VAXBI

ACK,

Write

Yes

RL/RLI

CSRx

Yes

RSVDx

Yes

BR4VR

Yes

BR4VR

BRxXVR

Yes

BRxVR

Yes

BRxVR

Yes

VAXBI

Yes

Transaction

See

(Note

Note

CSRx

BSY

regq.

WR/WMCI /UWMCI

BSY

ACK,

Rtrn

CSR data

BSY

ACK,

Rtrn

zeros

BSY

ACK,

Rtrn

NBI

vect

BSY

ACK,

Rtrn BI

ACK,

Rtrn

vect

IDENT

Transaction
NMI

zeros

BSY

ACK,

Rtrn

data

RD/IRCI

BSY

WLM

Read

Unlock

Masked

Longword

Read

Longword

Zeros

returned

BIIC

return

deserted

Masked

Longword

NBI's
The

Longword

Write

Causes

Resulting

Longword

Write

WLUM

RLI

Write

types.

Transaction

NMI

interrupts
of

zero

VAXBI

passive

error

CPU

Write

vector

device

release

(or

(NAP)

detected

error

indicates
error

CPU

Transaction

(Length

Write

UWMCI

IRCI

flag

VAXBI

WMCT=

RD
Interlocked

Masked

Unlock

Cache

Write

Intent

Make

Cache

Intent

Read
=

Interlocked

reading

Read

VAXBI

Cache

Intent

data/vector.

condition.

interrupt

detected

interrupt

2,3

BSY

NOTES
:

request
reading

handler.

X 3-21

has
VAXBI

been
vector).

3.3.1
NMI Address Decoding and Translation
NMI address decoding by an NBIA during CPU read/write operations 1is
shown
in
Figure
3-6.
Also
shown is the translation of the NMI
address to
a
VAXBI
address
when
a
VAXBI
device
register
1is
accessed.

An NBIA
<29:27>

is selected
are
equal

level.
This signal, hardwired
as either NBIAO or NBIAl.

I/0

SEL

the

NBIA

The

remaining

specifies
determine

by a
CPU
read/write
when
to 100, and address bit <26>

address

the
the

bits

are

decoded

VAXBI
and
thus
the
register
selected.

the

NMI
address
bits
matches the NBIA's
backplane,
defines

follows.

AAn~~ARAAAd

a2
VVAVYVRT
adAvnoocna
decoded as
VAXBI vramic+nr
register addressces
and passed to
except for one block of addresses within the node
VAXBIO,
This
address
block,
most
of
which

contains

the

(unused)

registers,

registers

NMI

are

nexus

the

registers

the

NBIA.

interrupt

vector

two control/status

and

the

four

Bit

<25>

NBIB selected.
Bits <24:00>
All
register
addresses
are

registers,

the selected NBIB
private space for
1is not allocated,

The

the

NMI

nexus

two reserved

registers.

When an NMI address is passed to an NBIB and its associated
VAXBI,
the
bits
selecting the NBIA and NBIB (bits <26:25>) are forced to
zeros.
(VAXBI register addresses must fall within the 32 Mb of I/0
space
allocated
to each VAXBI.) No other bits are modified.
This
includes bits <31:30>, which are not used for
addressing
purposes
on
the
NMI.
However, these bits are used on the VAXBI to specify
the transaction length, and the CPU asserts
a
value
of
01
(the
length
code
for
a longword transfer on the VAXBI) during the NMI
command/address cycle.

SEL

NBIA-I

3130

NMI | o]

292827

2625

1/0]0

X| 0

\—Y_/

SEL

VAXBI

—

N— —

NOT USED FOR

ADDRESSING.

0 0000 1000---0000

0OXX = CSRO

0000 01XX = CSR1

CPU ASSERTS

<31:30>=01

000¢ 10XX = RSVDO

SO THAT BITS
MAY BE USED
TO SPECIFY

0000 11XX = RSVD1
0001 00XX = BR4VR
0001 01XX = BR3VR | NI NEXUS

A LONGWORD

0001

LENGTH CODE

0001

ON THE VAXBI

10XX = BR2VR | REGISTER SPACE.

11XX = BRiVR

0 0000 1000----0010 00XX | UNUSED
0

2c¥25
X|

0000

1001----1111

292827

2625

NOT PASSED

TO VAXBI.

VAXBI
| ADDRESS

v©

—

11XX

THESE ADDRESSES

ADDRESS
SPACE

FORCEDlTO ZEROS
3130

VAXBIO

x | ADDRESS

[

VAXB!|

1!0

0|0

t LENGTH=LW
Figure

SCLD-427

3-6

NMI

Address

Decoding

and

Translation

3.3.2

Local Read/Write Operations

The following

read/write

local

are

all

is,

That

NMI

nexus

The

reading

The

reading of

The reading of an interrupt vector register
(BRxVR)
when
there
1is
no
corresponding interrupt request (BRx).
The
This condition occurs when
NBIA returns zeros to the CPU.
a VAXBI or NBI interrupt request is deserted before it can
a
causes
=zeros
of
return
The
be serviced by the CPU.
handler.
interrupt
CPU's
the
by
{(NAP)
release
passive

4.,

(reserved)
wunused
The reading or writing of the two
(ACKs)
acknowledges
NBIA
The
(RSVDx).
nexus registers

to/from the VAXBI

NMI

registers

operations.

address

in the NBIA and no transfer of data

required.

and

writing

the NBI

the

CSRs.

interrupt

transaction but writes

vector

(from BR4VR).

zeros

returns

no data and

NMI
the
as

be no
will
there
that
so
done
1is
This
data.
read
or
read
are
registers
nexus
NMI
the
when
discontinuities

block.

A condition exists when a

1local

written

For

the
addressing
transactions
data
nc
though
acknowledged even

similar

read-only
is written.

read/write

acknowledged by the NBIA, at least temporarily.
This occurs when
returned to the CPU instead.
been

write

reason,

the

are

BRxVRs

CPU

1is

not

A busy response is
has
read
1local
a

issued previously and the NBIA has not yet been able to return

it
before
NMI
(The NBIA must request and win the
the read data.
write
local
a
prevents
The busy response
data.)
read
return
can

prevents
also
It
read.
from modifying a register that is being
The busy
NBIA.
the
by
supported
stacked local reads, which are not
the
to
directed
writes
local
for
generated
not
1is
response

read-only

because

vector

no data

registers

is written by

A description of NBIA

the

these

operation

reserved registers.

X 3-24

transactions.

during

follows.

This

1local

reads

and

writes

3.3.2.1

Command/Address Cycle -- During NMI command/address cycles
(Figure
3-7),
the
CPU
asserts
the
register address on the NMI
ADDRESS/DATA lines, its ID
on
the
NMI
1ID/MASK
lines,
and
the
read/write
command
on
the
NMI FUNC lines.
The CPU also asserts
even
In

parity

the

NBIA,

buffer

(the

advance

conditions

the

NMI's

address

MCAs)

state

and

are

The

NBIA
NMI

from

device

interrupt
(both

read

started

BUSY

No NMI

start

ACK

the

1if

the

has

the

CPU

the

NMI

the

second

bus

cycle

CNF

and

the

NBI

I/0

set

read

SEL).

when

BRxXVR

(BRx

1nterrupt

exception

the

when

VAXBI

NBI

interrupt
this

and

the

FUNC

read-only

the

local

lines

not

already

NBFD's

vector

written).

NBI

read

BUSY

or
=

the NPAR MCA.

receive

ACK

1is

progress.

sequencer

response

lines.

The

ACK

following

the

command/address

X 3-25

request

case,

vector.

being

corresponding

prlorlty

detected

causing

MCA

following

not

received

(unless

data

NBFD

vector
An

NMI

the

command.

read/write,

the

both

higher

error was

MCA

but

pending).

NBCT

<26>

device

requests).

command

local

bit

addressed,

there

return

not

parity

local
to

sequencer

read/write

VAXBI

request

longword

reserved

device

BR4

read/write

indicates

SEND

lines.

decoded

(address

and

request

read/write

VAXBI

pending

CSR

parity

receive

local

read

The

BR4VR

the

addressed

1nterrupt

.5.

start

control

partially

causing

nexus

request

and

true.

addressed

data

response

asserts

returned

asserted

cycle.

during

For

local

before

read,

returning

Sets

Asserts

the

receive

its

CSR BUSY

NBIM

MCA

idle

sequencer

also

does

the

following

state.

indicate

NBI

write

store

local

function
the

read

(SAVE

CPU's

ID)

progress.

that

received

causes

the

CNF

NMI

lines.
3.

Asserts

data)

NBAP's

transmit
to

vYoad

A~Awvr~1laAa

local

Aabka

uwdeda

write,

1local

the

read

command/address

1is

the

SEND ACK.

respeonse

{(instead

receive

sequencer

the

BSY

other

CPU,

the

read

local

AT et

arm

start

progress

and

NBFD's

asserted

the

response)

to
on

the
take

the

data

cycle

the

CPU.

The

the

write

idle

the

for

return
to

two

asserts

when

the

busy

(BSY)

SEND

transmit
CNF

after

lines

waits

NMI

state

place.

CNF

MCA

DeJdeleJdoe

sequencer

NBCT

zero
causes

command
read

BUSY

NBIA must

receive

causes

ACK

(CSR

the

NBAP

OTUCULLUIL

cycle.

the
(or

the

data

CAa~d
1 ~»m

111

data

The

simply

operations

cycle.

CPU.

sequencer

This
the

the

latched

command/address

1in

the

ULODLCUODODOTU

returns

NBIA

response

command/address

received,

instead

T
e

command,
local

sequencer

receive

the

response

BUSY.

return

vyvovavw

following

what

returned

necessary

cycle

sequence

1indicates

LTdu

For

transmit

that

the

data

MCA,

the

BUSY

BSY

lines.

The

asserting

SEND

ACK

cycles

response,

after

the

o8]

ONOOHAWOND—=O)>

VAN

ND<3:0>
ADDRESS/DATA
ADDRESS

WRITE

XMIT

FUNCTION

WRT CPU

DWN—-0O

NOP
WHT CSRO
WRT CSRt
SAVE ID
WRT CPU C/A
WRT DMA DATA
WRT CPU IDENT

SEQ CMD

NOP

RD CSRoO
RD CSR1

RTN ZEROS
RD NBI

VECT

DATA

CPU CMD PEND

>“’ ROV
NMI

LTCH

DATA PAR FLT/CNTRL
170

SEL —p»

RCV BYTE

NMI| FAULT

NMI NEXUS
REGISTERS

PAR

— ——3 NBI

PAR FLT

INTR

REQS (TO

NBFD)

ADDR DECODE
v

DATA

PARITY

NPAR

_
»”

s
<

FUNCTION

ID_PARTIY

ID/MASK=CMDR'S

NBIM

RCV_ID/MASK PAR

SAVE |

L
1ID0"| l&—waT Func=s

NMI
SR
ERROR

NBFD
4

FUNC= AW LW

RCV_FUNC PAR

——SI28) plipcsr Busy

[

PAR

ERROR

(IF

XMIT

READ)

SEND ACK
|
———
9 WRT FUNC-3

SEQ|CMD=1/2/3/6

(IF READ)

(IF

READ)

NBAP

NBCT

.‘._______

INTR

(TO
CNF=ACK

(ASSERTED

LVL

NBFD)

SECOND CYCLE AFTER

C/A

€ — -

INTR

¢ REQS

CYCLE)

SCLD-1

Figure

3-7

Local

Read/Write

X 3-27

Command/Address

Cycle

3.3.2.2

3-8),

the

Write

Data

CPU

asserts

Cycle

the

mask data (if any) on
function
on
the NMI
on the NMI's data and
In

the

NBIA,

operations.
the NMI data
(which is in
1.

any

During

write

data

NMI

write

the

NMI

the NMI
ID/MASK
1lines,
FUNC lines.
The CPU also
control parity lines.
mask

data

1is

1ignored

data

cycle

and
a
asserts

during

local

(nonzero)

NBI

write

function

and

idle
state.
The
NBI write function causes
buffer to strobe the write data from the NMI
lines
into one of the CSRs.
These registers

nexus

registers

Just go to the idle
This
occurs
when
has

been

addressed

ADDRESS/DATA

that

can

write

the

the NMI data
ADDRESS/DATA
are the only

written.

state (NBI write function
equals
0).
NMI nexus register other than a CSR

an
and

data

strobed

1its

1idle

from

the

NMI

ends

the

lines.

The return of the receive sequencer
local write operation in the NBIA,
-

lines,

write
data
even parity

However,
the received write data function identifies
as write data causing the NBFD MCA's receive sequencer
a wait state) to do either of the following:

Generate

NMI

(Figure

ADDRESS/DATA

X 3-28

state

— NO WRITE

DATA TRANSFER

NB!I

WRITE

NOP

WRT CSRO
WRT CSRt
SAVE ID
WRT CPU C/A
WRT DMA DATA

I1F BRXVR/RSVDX
ADDRESSED

2
3

ND<3:0>

ADDR/DATA

WRITE DATA>—> RCV
NMI

LTCH

WRT CPU

IDENT

WRT CPU

DATA

CPU CMD PEND

F
T
T
<QAIA_P_AF_’L__LI./_CN__BL
_P_AB_EL_1I

RCV BYTE PAR
NMI

FAULT

CS RX

4— WRT FUNC=0/1/2
NPAR

DATA PARITY

PARITY

NBIM

ID/MASK=MASK

RCV_ID/MASK PAR

<___

FUNCTION

NMI

ERROR

NBFD

FUNC-WRT DATA _,,

> WRT FUNC=0/1/2

(STOP) )

RCV_FUNC PAR

NMI
PAR
ERROR

NBCT
NBAP

N/
\4

SCLD-14

Figure

3-8

Local

Write

X 3-29

Data

Cycle

FUNCTION

3.3.2.3 Return Data Cycle -- To return local read data (Figure
and after latching the transmit sequence command asserted by
3-9),
the NBFD MCA during the command/address cycle, the transmit
sequencer in the NBAP MCA does the following:

Asserts I/0 ARB on the NMI to request use of the bus.

Asserts an NBI read function equal to the latched transmit
The NBI read function value determines
sequence command.
what NMI nexus register data (or if

=zero

returned to the CPU by the NMI data buffer.

data)

will

a RTN
that
This signal specifies
Asserts RTRN RD DATA.
MCA.
NBFD
the
by
CPU
the
DATA function will be returned to

Nothing else occurs until the bus is granted to the NBIA by the NMI
arbitration logic in the CPU. When the bus is granted (which may
be immediately or after a number of bus cycles), I/0 BUS EN from
The
the bus arbitration 1logic asserts NMI ENABLE in the NBIA.
following

then takes place.

zero
(or
The NMI data buffer transmits the register data
selected by the read function on the NMI
that was
data)
ADDRESS/DATA

The NBIM MCA transmits the CPU's ID

the

NMI

ID/MASK

The ID was saved during the command/address cycle.
lines.
which
the NBAP MCA,
It is selected for transmission by
asserts a PAR MUX SEL code that is equal to 0 (its default

value)

lines.

during the local read cycle.

The NBFD MCA transmits a RTN DATA function on the NMI FUNC
lines.

Following transmission of the read data and ID on the NMI, the NBIA
relinguishes the bus (never asserts I/0O HOLD) ending the NBIA local
read

operation.

X 3-30

N\
ADDRESS/DATA

< CSRX/VECTOR/0s

READ FUNCTION
NOP
RD CSRO
RD CSR1
RTN ZEROS
RD DC VECT

RD DC DATA
RD NBI VECT

PAR
w0

DA WN—=O

NBI

MUX SEL

LOCAL RD
Bl READ

XMIT
XMIT

C/A
DATA

NMI

¢— XMIT
LTCH

XMIT
Os

BYTE

PAR

4—RD FUNC=1/2/3/6
NMI

CSRX/BR4VR

ENABLE

NPAR

DATA PARITY
FUNCTION

PARTIY

NMI

PAR MUX SEL=0

ID/MASK=CMDR'S ID

XMIT

ID/MASK

PAR

SAVE | [€¢—PAR MUX SEL=0

NMI_ENABLE
NBCT

NBFD

FUNC =

RTN

DATA
NMI

ENABLE

RIRN

DATA | _nBAP
—» PAR MUX SEL=0

L/ AR

{0 BUS EN

—»RD FUNC=1/2/3/6

NM! ENABLE

N
CLK

Figure

SCLD-21%

3-9

Local

X 3-31

Read

Data

Cycle

3.3.2.4
Parity Generation and
Checking -- Parity
generation
and
checking
during command/address and write data cycles is the same.
The NMI data buffer generates an even parity bit for
each
of
the
four bytes of address/write data received from the NMI.
Similarly,

the NBIM MCA generates an even parity bit for the received
information,
received NMI

ID/MASK

and the NBFD MCA generates an even parity bit for
function.
The NPAR MCA then does the following:

the

Completes the computation of data
4-byte
parity bits, and compares
parity bit (DATA PARITY) received

Completes the computation of
control
1line
parity
using
both
the
ID/MASK
and function parity bits, and compares
the result with the control line parity bit
(F
PARITY)

received

from

the

line
parity
wusing
the
the result with the data
from the NMI.

NMI.

If bad (odd) NMI data or control parity is detected, the
NPAR
MCA
asserts
DATA
PAR
FLT or CNTRL PAR FLT, which causes the NMI data

buffer (the ND3 MCA) to set the corresponding parity error flag
1in
CSRO.
This,
1in
turn, asserts the NBI's FAULT DETECT line on the
NMI, which causes an interrupt request to be generated in the
CPU.
(Because all NMI nexus check NMI parity during every bus cycle, all
could be asserting their NMI FAULT DETECT line.) The NPAR MCA
also
asserts
NMI
PAR
ERROR
for
either
type
of error.
This signal
connects to the NBFD MCA, stopping the
receive
sequencer.
As
a
result,
a parity error prevents the NBIA from acknowledging an NMI
transaction with a
bad
command/address.
Also,
1if
the
command
address
1is
good
but
write
data
1is
bad,
the
transaction
1is
acknowledged but bad data is not written into a register.

During return read data cycles, the
NPAR
MCA
must
generate
and
transmit (not receive and check) the NMI data and control line even
parity bits.
The NMI data buffer again generates
and
sends
even
byte
parity
bits to the NPAR MCA, but the parity bits are for the
NMI data it is transmitting and not receiving.
Also, the NBIM
MCA
generates
and
sends
a parity bit to the NPAR MCA, but the parity
bit is now for the ID it is transmitting on the NMI.
The NBFD
MCA
does
not
generate
a
parity
bit
during
the return data cycle,
however.
This is because it always transmits a RTN
DATA
function
on
the
NMI FUNC lines, which means the NPAR MCA only needs the ID
parity bit to generate NMI control parity.

For diagnostic purposes, a control bit (FORCE NBIA PE) in CSRO
can
be
set
that
causes the NPAR MCA to generate bad (odd) parity for
both

the

NMI

data

and

control

lines

data.

X 3-32

when

the

NBIA

returns

read

3.3.3
VAXBI Read/Write (and IDENT) Operations
A CPU read/write to a VAXBI device register requires first that the
NMI
command/address be transferred from the NBIA to the associated
NBIB so that a VAXBI read/write transaction can be started.
For
a
CPU
write, this is followed by a transfer of the NMI write data to
the NBIB where 1s transmitted on the VAXBI (during the VAXBI
write
transaction).
For
a
CPU
read,
the VAXBI data read by the NBIBR
(during

where

the

Another

CPU

reading

reading
generate

VAXBI

read

returned
read

then

from

the

operation

VAXBI

does

the

device.

operation, the NBIB
returned to the CPU

transfer
shown

the

CPU

over

requiring

device's

passed

the
a

interrupt

back

VAXBI

IDENT

Following

VAXBI

transaction

and

passes the vector
over the NMI.

back

and

3-10.

X 3-33

data

the

transaction

vector.

this,

command/address

Figure

NBIA

NMI.

The

the NBIA's vector
register
(BRxVR)
causes
and
transfer
an IDENT command/address to

NBIB

The

transaction)

the
the

the

between

1is

NBIA
NBIB.

the

NMI

and

to
The

vector

VAXBI

NBIA where

the

transaction

<collect

similar
to

NMI

read

1is

VAXBI

C/A

ID/MASK

NMI

CYCLE

FUNC

CMDR'S 1D

(CPU

READ/WRITE

ADDRESS)

ADDRESS/DATA

3130 29

R/W FUNC

TO VAXBI

DAT

CTL

EVN

PAR

ADDRESS

<29:27>=100; <26:25> FORCED TO ZEROS

ID_ SAVED

PAR BIT INVERTED ————

(1F RD FUNC)

IF FORCING <26:25>

TO ZEROS

04
DATA BUS

R/W FUNC

PARITY.

3130 29
D|

CHANGES

PME

ADDRESS

PD|

EWVN

VAXBI

PMF|

TRANSLATED

pe-¢ X

PAR

R/W CMD

31 30

EVN

PMF

—1

ADDRESS

Po|

obD

LENGTH=LW

C/A_CYCLE

ID/MASK
NMI

CMDR'S

FUNC

(CPU

READ TO

ADDRESS/DATA

3130 29

R/W FUNC

BRXVR ADDRESS)

DAT

CTL

EVN

PAR

ADDRESS

PAR

SAVED

04
DATA BUS

IDENT

00
FUNC

31
D|

00———
00| BRX | 00 -——
00

20 10Y1615

PD | EVN

y
PMF|

TRANSLATED
03
VAXBI

PMF
00

IDENT

CMD

EVN

31
D

20 19
—— 00|

y 16 15

BRX

| 00—
00

Po|

ODD

SCLD-428

Figure

3-10

Basic

Information
(Sheet

Flow
of

Between

NMI

and

VAXBI

WRITE DATA CYCLE (CPU

ID/IMASK

NM!

FUNC

MASK

VAXBI

¢y

ID/MASK

NMI

WRITE DATA

CMDR'S ID

31
READ DATA/VECTOR

_____

ZEROS

SAVED 1D

WF]

PMF

oDD

EVN

DAT

CTL

PAR

EWN

EVN

CTL

PAR

—

ERROR

DATA BUS

CPU ERROR

EVN

RETURN ~———

01010

CINE

RTN RD DATA

EVN

READ TO VAXBI/BRXVR ADDRESS)

ADDRESS/DATA

PAR

FUNC

MASK

CcTL

WRITE DATA

RETURN READ DATA/VECTOR CYCLE (CPU

PAR

EVN

WHT DATA

DAT

WRITE DATA

ADDRESS)

ADDRESS/DATA

WRT DATA

DATA BUS

WRITE TO VAXBI

00000

READ DATA/VECTOR

1L zeros

;

EVN

PMF

EVN

:
PD

PMF

ERROR

VAXBI

! [

STATUS

READ/VECTOR

oDD

READ DATA/VECTOR
SCLD-464

Figure

3-10

During

Basic
CPU

Information

Read/Write

Flow

Between

Operations

X 3-35

(Sheet

NMI
2

and
of

VAXBI

3.3.3.1
address

consists

command/Command/Address Transfer -- The transfer of
information from the NMI to the VAXBI (Figure 3-11)
of

four basic operations.

The NBIA loads the NMI command/address (or the generated
IDENT command/address) into its DC022 transaction buffer.

The NBIA reads the command/address from 1its transaction
buffer and loads it into the NBIB's data bus buffer (over
the

interconnecting data bus).

The NBIB requests a VAXBI transaction by its BIIC, and it
reads the command/address from its data bus buffer into
its

BCI

data buffer.

The NBIB's BIIC reads the command/address from the BCI
arbitrates for the VAXBI, and starts the
data buffer,
transaction transmitting the command/address on the VAXBI.
Command /Address to Transaction Buffer

NBIA operation during the NMI command/address cycle is as follows:
1.

Similar to a local read/write, the receive sequencer 1in
the NBFD MCA advances state asserting SEND ACK and
beginning the operation, provided the NMI address 1is
selecting the NBIA, the NMI function 1is a read/write
longword command, and there is no data or control 1line
However, unlike the local read/write, CPU
parity error.
BUF BUSY and EBUS BUSY must both be deserted.

not,

busy response is returned to the CPU (SEND BUSY asserted).

IDENT
read/write or
indicates a VAXBI
CPU RUF BSY
s
indicate
BUSY
EBUS
.
operation is already 1in progress
to
about
1is
and
NMI
that the NBIA has requested the
transfer a DMA command/address (and write data if a DMA
EBUS BUSY also indicates that the NBIA
write) to memory.
has requested the NMI and is about to return read data to
a VAXBI
(CSR BUSY is not checked, which means
the CPU.
read is
local
a
while
read/write or IDENT may be started
in

progress.)

The NBFD MCA also gates the received NMI function to the
NBIM MCA over the five NEBUS lines (it always does this)
and asserts one of two NBI write functions, WRT CPU C/A
(for VAXBI reads and writes)

X 3-36

or WRT CPU IDENT.

O
NMI
A

C/A

CYCLE

(LOAD

C/A

TRANSACTION BUFFER)

ECL4— |~

ND<3:0>

ADDRESS/DATA

ADDRESS

LICH

LTCH

XMIT

170 SEL———»f

[ —

NBIB

EBUS

ADDRESS

NBIA 4—|— NBIB

T8US

DC022 TRANSACTION BUFFER

>—>

DATA _PAR FLT/CNTAL PAR FLT

[---» NBI INTR REQS
(TO NBFD)
e
WRT FUNGe4/6

|
I
{

CPU

CIA [ ADDRESS I MFI PDTPME]

EUNC |D PARITY

ADDRESS

£D

_ PMF

PME
MF (STATUS)

LE-€ X

KoCMDR'S 1D

ID/MASKe

LSAVE

£BUS Bsy
FUMC-R/W

(8TOP) |

RCV_ID/MASK PAR

IDENT

1— CPU BUF

BsY

FUNC

EBUS

[
i

NOTE: ADDRESS-BRX BIT

IF IDENT.

NM| PAR

ERROA

WRT ADA=14

SEND ACK

MF_RD FUNC

ECL—1—> TTL

NBAP

Bi0

CPU

REQ

CPU REQ

PAR

ERROR

NBCT

INTR

LVL

(TO NBFD)

<4———

- NBI

CPU_REQ PENDING

INTR REQS

l¢--VAXBLINTR
REQS|

CNF=ACK ASSERTED SECOND CYCLE AFTER C/A_CYGLE)

1-8YNC

;

REQ PENDING

]

| P——BI_INTR_REQS
NBI

o] NoP

DATA BUF

CTL

SYNC/XLATE

‘f

|
l

WRT FUNC=4/6

o Wil FuNoare

L7 LTICH EN

RCV_FUNC PAR

SEQ

(1—»(32\:‘0;}0

DCo22
CTL

NBFD

I
:

BUS o

{TTL)

NMI

L3/ RD

CcTL

RD|ADR=14

CPU BSY INEBUS FUNC
]

L3|LTCH

DSEQ

[4——— WHT FUNC=4/8

REG

|
—

WA FUNCai5 ——b

}

FUNC PAR

NBIM

; J

DATA PAR

US XMIT PAR FUNC

DATA BUS BUFFER

l NPAR

DATA PARITY

paTAlBUS

BUS 0 DATA BUFFER

READ DATA

RCV BYTE PAR

VoNMIFAULT

LOAD C/A

TTL

WRITE

FUNCTION

1|
WRT CSRO
2 | WRT CSR1
3|
SAVE ID

4 | WRT CPU C/A

5 | WRT DMA DATA
6 | WRT CPU IDENT
7 | WAT CPU DATA
9|
CPU CMD PEND

SCLD-20

Figure

3-11

NMI

VAXBI

Command/Address

Transfer

(Sheet

DATA BUS

NBIA 4——|—P NBIB
‘*

LOAD C/A IN 8CI DATA BUFFER (REQ VAXBI)

DATA BUS BUFFER

‘

PuE_,

PARITY

LFUNC)

GEN/CHK

— I—»

XLATED PO

M- MPS=1

NBIB PE
(TO NBIA

‘1o

|
‘

BCI DATA BUFFER

ADDRESS

R ——

[

CSR)

MPS -~ &«

v,
(

l=R/W/DENT

;

)

PORT

=
%

MDE

6
'y

MASTER

" hak_
y

SLV_BUSY|
1

[P E—

SLAVE

'
NOTE)
:
R ——— e

SeQ

INTR

LOGIC

SYNC

PORT

IF_IDENT)
;
|

MASTER PORT

SEQ STATES

23 || CHK
EV RD
AD CYCLE

2 | WRT DATA
T

e e e VAXBI
e INTR_REQS
e eeee

SYNC CPU_REQ

SYNC REQ PENDING

o | IDLE

[IDLE

6 | WRT STALL
5 | xF

7 | WRT CMPLT
8 | RETRY

9 | WRT BI
A | CPU DONE

B | WRT CYCLE

s | RD wWAIT

D | CHK EV WRT

E | START WR

B8 _| RD ROY

F | RESTART WR

NOTE =

SLV

BUSY DELAYS VAXBI

IF DMA TRANSFER IN

REQ

PROGRESS {SPS=2/3/6/6/7/9)

Figure

3-11

NMI

to VAXBI

Command/Address

Transfer

| WRT C/A

3 | WAT WA

RESTART RD
87 || WAIT
o

‘

SLAVE_PORT

5 | START RD

SEQ STATES

f-— MPSai

4“‘1*——— T e T T

(SEE | SPS=4%—

CLE

(0 ~»BRX

L13/L15 WAT EN

BSY

DATA BUF

ADDRESS

LNGTH
CNTR

L7 {RD EN

T cggDnE‘ADD/———i»IDENT

(IE CMD=RO/IDENT)

BCI

MPS = 14—

—

‘

ADDRESS

— L {CMD)

115

—» CPU READ

' TOF

[::I

BIIC TAKES C/A (VAXB! C/A CYCLE)

(Sheet

oL 15

2 of

The

NBI

write

function

NMI

the

causes
to

data

the

zeros

one

bit

does

ND3)

(ND

NMI
be

buffer.

This

the

buffer

received

transaction

ND2).

then

following:

MCAs),

WRT

CPU

bit

either

WRT

(with

transmitted

depending

address

C/A

the

EBus

function

transaction

<19>,

function

<26:25>

IDENT

the

CPU
bits

<18>,

forced
to

the

causes

just

buffer

<K17>,

on the vector register (BRxVR) addre
ssed.
transmitted
on
the
VAXBI
as
part
of the
command/address, this bit specifies
the
BR
level
serviced.

later

the

NBIM

received
on

the

CPU

EBus

IDENT

(hex)

MCA,

NMI

FUNC

9.)

the

DSEQ

and

MCA,

written
the

the

MCA,

NPAR

(there

selected)

(either

into

CPU

1is

associated

The

the

REQ

IDENT

write

that

NBIB.

X 3-39

CPU
it

the

equal

WRT

the

CPU

BUF

NBIM

MCAs

location

read

and

reguest

that

bus

command/address

may

Also,

This

VAXBIs

data

the

equal

and

buffer

asserted.

are

sets

command/address.

each

being

causes

code

function
from

appropriate

that
and

command

transaction

for

When

IDENT

transmitted

buffer.

function

<K16>

low-order
bits
function lines during

VAXBI

signal

the

four

read/write

one

buffer

NBI

transaction

information

CPU

signals

transaction
the

the

function

NBFD)

causes

(The

either

causes
for

line

cycle.

C/A

from

the

however,

reserved

CPU

(gated

transmitted.
transmitted
on the

later

WRT

lines

function,

command/address

BSY

function

(by

can

controller

the

transferred

Command/Address

to NBIB

The CPU REQ signal, asserted as CPU REQ PEND after ECL to TTL
translation and synchronization to the TTL clock, causes the data
to the NBIB.
bus control to transfer the CPU command/address

However,

the transfer will be delayed if the control is busy doing

a DMA transfer.
the

If (or when) the bus control is not busy,

does

following:

Reads the command/address from the transaction buffer and
_ (by asserting a latch enable signal) latches it into the
(L1).

data bus buffer's first set of data latches

After loading L1, immediately asserts Ll's read (transmit)
on the data bus, the latch enable for L7 in
enable and,

then
is
The command/address
the NBIB's data bus buffer.
L7),
(into
NBIB
transferred over the data bus to the
independent of

any NBIB control.

Asserts CPU REQ on the data bus to signal
the

CPU

command/address

has

the

been loaded.

NBIB

that

Also sets an

1is a
internal control bit (CPU RD PEND) if the command
(When a CPU read is pending and before the
read function.
return read data is loaded in the NBIB, the bus control is
These can occur 1if the
DMA transfers.
to handle
free
1in the NBIB by the
initiated
VAXBI read transaction
command/address has to be retried.)

In addition to activating the NBIA's data bus control as Just
the CPU REQ PEND signal is asserted on the data bus to
described,
NBIB's slave port seguencer from starting a DMA
the
prevent
the CPU
the end of
until
interrupts)
fielding
(or
transfer
read/write operation

(in the NBIB).

Command/Address
CPU

REQ

request

from

delayed

(The
a

SLV

DMA

the
a

NBIA
VAXBI

the

BUSY

BCI

NBIB
1is

present

VAXBI

make

the

state

BCI

lines.

assert
write

buffer

When

the

BCI

data

the

IDENT

L5.

outputs

the

BIIC.

port

sequencer,

now

1in

The
the

and

begins

first

bus

both

RAK

(unmodified)
it

VAXBI

request

may
will

the
for

respond

node.

pending

the

BCI

data

transaction
MDE

the

VAXBI

cycle,

the

BCI

1is

data

bus

buffer)

the

BCI

the

data

bus

VAXBI's
of

data

buffer

and

with

read/write

level

bit.)

However,

modified

NMI

logic

before

code

the

Cycle)
connect

requested
BCI

address

directly

the

master

the

command/address

data

and

command (I)
arbitrates
for
read/write (or IDENT) transaction.
command/address
cycle,
the
BIIC

command/address,

and

BSY

the

progress)

from

data

the

buffer

the

data

BCI

function

buffer

into

the

causing

read

one

could

Command/Address

asserts

Furthermore,

and

the

data

directly

the

VAXBI

IDENT

which

through

latches

that

the

port

sequencer

code

code.

transaction
onto

the

when

slave

transaction.

1loaded
is

transmitted

the

VAXBI

translate

VAXBI

(in

and

between
is

buffer,

(VAXBI

BIIC

determines

causes

command/address

code,

for

1).

port

asserting

then

BUSY

the

master

sequencer
will

(SLV

counter,

the

upcoming

gated

request

monitoring

state

address

the

command/address

case

and

then

indicating

address

port

The

operation

state)

passed

bus

BIIC

VAXBI,

(The

BIIC

After
and

the

master

BIIC.

length

enable

the

command

address

data

code,

VAXBI

DMA

request,

VAXBI)

NBIB's

the

enable

for

length

This

The

asserts

read

the

Command/Address

the

(latch)

transfers

longword

the

REQUEST
REQUEST

required.

appropriate

During

the

buffer,

function

lines.

the
by

progress

command/address

command

stored

located

preparation

translation

with

doing

The

the

This

busy

transaction

control

buffer.

causes

transaction

(Request

state.)

(to

and

also

first

sequencer's

advances

Buffer

logic,

operation

Data

the

and

NBIB

BCI

respond

X 3-41

own

BIIC

IDENT.)

signals

data

buffer

the

directly

(Note:

VAXBI

registers,

which

cycle

NBIB

(both

transmits

lines.

BIIC's

command/address
the

VAXBI

and

may

1like
have

any
an

other

interrupt

During

any VAXBI

BCI.

this

command/address

case,

when

the

cycle,

the

BIIC

command/address

asserts

cycle

CLE

the

transmitted

by the BIIC and the result of a CPU read/write operation
(CPU
REQ
PEND
=
1),
the
CLE
signal
<causes
the slave port sequencer to
advance to the MASTER PENDING state.
The sequencer then causes the
BIIC
to
send RETRY responses to any DMA request (VAXBI read/write
transaction) by a
in the NBIB.

VAXBI

device

until

the

CPU

initiated

read/write

operation

CLE

ends

the VAXBI

transaction

just

IDENT,

causes
the
interrupt
request
being
serviced
(latched
interrupt logic) to be cleared.
The interrupt logic always
and
decodes
the
VAXBI
command
on
the BCI I lines, and
checks the
identify

state of BCI
data
1lines
interrupt
reguests
(by

transactions)
has initiated
line

used

<19:16>.
incoming

It
does
this
to
INTR
and
IPINTR

from the VAXBI devices.
In this case, when the
the transaction and it is an IDENT, the asserted
to

clear

the

appropriate

level.

also

in
the
latches
it also

NBIB
data

3.3.3.2

Write

Data

command/address,
VAXBI

(Figure
1.

The

Transfer

the

3-12)

consists

NBIA

loads

transaction
2.

The

NBIA

and

reads

loads

The

NBIB

loads
4.

The

into

NBIB's

buffer

end

the

NBIB

VAXBI

node.

buffered

Write

Data

the

BIIC

The

loading
like

the

The

and

The

NBI

The

NBI

NMI,

Finally,

and

retry

the

DC022

transaction

buffer

bus

its

buffer

data

from

the

VAXBI

not

ends

the

(over

the

bus

buffer

and

the

BCI

data

(VAXBI

write

requests

command/address
have

CPU

requested

simply

write

operation

the

addressed

another

and

VAXBI

write

data

are

buffer

very

reloaded.

Buffer
data

the

transaction

function

(this
time,
a
write
data
NBFD's receive sequencer causing

the

assert

function
NMI

data

(instead

NBI

(this
buffer

write

function.

time,
WRT
to transmit

CPU
the

DATA)
then
received NMI

command/address)

also

causes
the
NBIM
write mask (not the

the

buffer.

function
function)

and

again

function

mask

the

read

IDENT,

and

the

its

data

NMI

data

its

data

from

write

received

write

into

NMI

buffer.

the

NBI
case,

data

the

The

NMI

write

from

NBIB's

data

NBIB

write

transmit

data

the

command/address.

sequencer

transaction

data

transaction

BIIC.

the

data

write

from

progress).

advances

write

NMI

write

BCI

the

received

the

operations.

bus).

unless

NMI

causes

basic

data

write

the

function)

four

the

reads

to Transaction

much

NBIA)

data

transmits

Then,

transaction

transfer

write

the

BIIC

VAXBI

(and

the

into

its

and

transaction

The

the

reads

buffer.

interconnecting
3.

transfer

into

location

the

transaction

writing

causes

the

DSEQ

transaction
is

the

data.

X 3-43

one

MCA
to
received

buffer.

command/address,
the
MCA to load the write

buffer

reserved

location.
for

both

1In
CPU

this
write

NMI WRITE DATA CYCLE (LOAD WRITE DATA IN TRANSACTICN BUFFER)

ADDR/DATA

[ WRITE DATA _ i

<3:0

m—
[c303
|LTCH

LTcH

EBUS

ACV/XMIT BYTE PAR

(o8

z—

‘

FUNC PAR

EBUS XMIT PAR MASK

whT Func-7—»{ O > SEY BUF
f

ACY_IDIMASK PAR

iDMASK=MASK

FUNC (MASK)

FUNC (MASK),,

)

DATA
|FUNC=WRT

(..
(STLL.
NMI PAR

BRR

D
Ls

-»>

I:‘

L fren u|ro

CLA BUF|BUSY

DSEQ

- g‘_-r’f 0

WHAT AbRet5 FD|ADR=15
P—

[4—- WRT FUNC.7?

cTL

LS: LTCH EN

(TTL)

NBFD

OATA PAR

PARITY

WRITE DATA

[:I

Y.l wRiTE DATA| MF| PD

N
NBIA4——b NBIB
DATA| BUS
DATA BUS BUFFER
-

ATA

DATA PARITY
FUNC ID

—

BUS 0 DATA BUFFER

WRITEE DATA

PAR FLT
¢ PATA_PAR FLT/CNTRL

L[]
e

NI/
DC022 TRANSACTION BUFFER

WRITE_DATA

e ¥ xmi

LOAD WHlTE/\DATA IN NBIB

O\ 7

Ecu—}—» TTL

ACV_FUNC PAR

NBAP

NBI_WRITE FUNCTION

NBCT

DATA BUF

'
SYNC/XLATE

LVAXBIO CPU DONE

cTL

)

0 | NOP
1

ECL4—(-—» TTL

WAT FUNCa7 —#

—® WRT FUNC=7

CPU DONE 0

| WRT CSRO

2 | WRT CS!
3 | SAVE ID
4 | WRT CPU C/A

SYNC

5 | WRT

6 | WRT CPU IDENT
7 | WAT CPU DATA

9 | CPU CMD PEND

SYNC NXT & DONE 0
NXT &

CPU DONE 0

< SET

CPU

DONE
SCLD-9

Figure

3-12

NMI

VAXBI

Write

Data

Transfer

(Sheet

1 of

DATA BLS
LOAD WRITE

NBIA «—r—» NBIB

P
¥

BCI

DATA BUFFER

BIIC

TAKES WRITE

DATA (Bl

WRITE DATA CYCLE)

DO0E0000

F**

WRITE DATA

BCI

—

PD
PARITY

PME

GEN/CHK

(MASK)

XLATED PO

H— MPS=9
-

NBIB PE
(TO NBIA CSR)

DATA BUFFER

DHDF

DATA BUS BUFFER

L13

WRITE

I=MASK
<

(MASK)

MPS=9,8,0,A
—

MASTER
pPORT

¢—CNF=ACK

SEQ

RAK
[¢

—NXT
«

EV=MCP

NoaRs

_BSY
LNGTH
CNTR

TOF

PASSTHRU

L13/L15

|—

WRT EN

INTR

LOGIC

CTL

SLAVE
PORT
SEQ

MASTER

PORT

SLAVE_PORT

SEQ STATES

H4-—— MPS=9,B
[¢]

F TO I

DATA BUF

MDE

SPS=4

DAT

DATA

! {MASK)

XLATED |

—

PaN

BCI

Sv-¢ X

I
|
|
|
|
|
|
l
|
l
|
|
|
|
|
l
|
|
|

DATA IN

2 | CHK EV RD

3 | AD CYCLE
RD

PENDING

2w
s g%

65 | STARTERR

[

7 | RESTART RD

SYNC

3 Wasic

REQ PENDING

88 || RE'War
RD
ROY

A | CPU
B | WRT CYCLE
D | CHK EV WRT
E | START wR
F
RSwar

0—¥SYNC

WA'T

?ALL

7 | WCueLT

SET CPU DONE

SCLD-11

Figure

3-12

NMI

VAXBI

Write

Data

Transfer

(Sheet

Write

data

There
the

one

NBIB

NBIB
major

and

Although

the

and

asserting

Dby

data

still

transfers

then

quickly

the

transfer

transfer
is

control

(by

the

between

transfer

bus

was

initiated

difference

the

NBIB's

write

the

latch

and

the

NBIA's

bus

data

bus

buffer,

does

CPU

request
REQ

the

signal.

(The

PENDING.)

bus

enable)

buffer
not

NBIB.
buffer

read

and

initiate

command/address

Instead,

control

data

the

transaction

enables

response

data

initiated

automatically

transfer

command/address

reading

appropriate

information
the

the

immediately

transfer
following

the transfer of the command/address.
(Both the command/address
write data/mask are in the transaction buffer by the time
CPU
PENDING is asserted.)

and
REQ

Another

difference

the

NBIB's

data

buffer,

(L9).

(The

not
L7

bus

wait

before

can

data

a
to

when

the

write

1is

loaded

command/address

have

doing

that

DMA
the

for

the

transfer

transfer.)
NBIB

ends

was

the

write

CPU

the

NBIA's

CPU

when

the

CPU

write

end

the

BCI

Data

NBIB.

(The

both

BSY

data

write

set

the

NBIA

Thus,

1in

latches

does

command/address

(The

NBIB

might

command/address
transfer
must

transfer

VAXBI

1loaded

the

data
signal

another

L7.)

data.

write

BUF

transfer

Transferring

the

However,
DONE)

loaded

NBIB

data

still

busy

and

write

the

NBIA.

cleared

completed

transaction

from

1is

(by

the

discussed

presently.)

Write

Data

When

the

and

begins

the

MDE

the

BIIC

reads

the

buffered

command/address

(which

port

MDE

the

VAXBI

signal

master

Buffer

gated

signal

1is

sequencer

state

(WRITE

now

NBIB's

data

the

data

buffer

make

the

necessary

overwriting

transfer,
read

command/address.
logic

because

transmission

the

sequencer

the

and

Also,
the

the

write

VAXBI

command/address.

BIIC)

then

buffer

advance
to

data

the

enables

asserts

mask

the

(in

PASSTHRU

does

NMI

not

(or

data

the

need

buffer

described,

BIIC)

after

causes

delay.

sequencer.)
write

data

transferred

buffer

(latch)

the

causes

(L9)

BCI

previously

state

command/address

NBIB's

write

advance
to

the

command/address

wused

bus

from

cycle

and

control
when

and

mask

the

asserts

modified

BCI

L5.)
the

transferring

signal
to

(A
This

the

translated

IDENT)

the

I
for

function

Write

Data

When

the

BCI

data

BIIC

the

(VAXBI

ready

buffer,

advances
MDE

the

port

node

VAXBI

during

ACK

the

not

the

CNF

the

own

the

data

write

data

VAXBI

When

the

was

asserted

causes

the

CHECK

port

sequencer

the

beginning

port

EVENT

ends,

the

master

BIIC

master

the

WRITE

transaction

advances

state

deasserts

the

The
the

CPU

the

NBIA,

and

CPU

DONE

causes

data

the

write

CPU

DONE

ECL

clock)

This

after
the

and

(after
then

clears

synchronization

bus

control

mask
TTL

causes

CPU

CLR

BUF

BSY

operation

and

allowing

the

CPU

(or

read)

write

the

ECL

(that

NBIB)

in
NBIA

VAXBI

BUSY

to
to

the
to

and

NPAR

the
node

may

STALL

the

completed

response

the

(RAK
This

code

asserted

advances

1indicates
(MCP

code),

the

DONE

CPU

TTL

CPU

asserted

MCA

to
the

clock,

command/address

the

CNF

BCI.

DONE

SET
plus

signal.

synchronization

acknowledge

node

the

cycle).

also

SET

takes

addressed

node

code

finally

NBIA's

assert
be

address.

X 3-47

code

the

addressed

event

the

sent

translation

BUF

asserting

NBIA.

that

successfully

DONE)

the

bus

sequencer
event

the

when

two

RAK

the

during

command/address

check

transaction

BIIC
of

cycle.

end

this

return

RETRY

the

mask

1indicates

when

Retries)

completed

(to

the
a

data

this

and

the

responding

before

(and

lines.

state.

may

ended

asserts

sequencer

BCI

cycles

also

and

Transaction

transaction

the

Write

(The

that

lines

the

signal

did

acknowledged

addressed.)

data,

bus

write

case,

CNF

data

until

NXT

state),

single

and

cycle.

lines.

End

write

normal

data

been

transaction
write

the

state

now

The

CYCLE

BIIC

the

VAXBI

acknowledges

WRITE

successfully.

has

the

mask

BCI.

the

CYCLE

write

one

and

response

for

successfully.
cannot

taken

BIIC

ready
lines

data

WRITE

completed

following

NBIB's

the

and

the

the
in

data
on

has

returning

(to

mask

transaction.

has

cycles

and

latches

them

transaction

MDE

then

remains

addressed

write

and

BIIC

transmitting
write

the

NXT

Cycle)

The

VAXBI

take

Data

sequencer

write

command/address.
sequencer

asserts

master

gates

Write

the

DSEQ

MCA.

ending

the

CPU

write

and

execute

the

When a VAXBI transaction ends and the
a retry

indicates

event

response was received,

code

(an

RTR

code)

the master port sequencer

The
BIIC.
the
immediately requests another VAXBI transaction by
be
to
have
not
does
information
data/mask
write
and
command/address
WRITE
1its
to
returns
then
The sequencer
reloaded in the BIIC.
1is retried on the VAXBI (BIIC
transaction
the
when
state
CYCLE
As before, the sequencer remains in this state
asserts RAK again).
until
the
transaction
ends.
Also, as before, the sequencer then
checks the event code and requests
another VAXBI
transaction
if
there

1is

retry

response.

This process

quencer's

WRITE

repeated

for all

retry

the
takes
When the addressed node finally
responses that follow.
write data and acknowledges the transaction completed successfully,
SET CPU DONE is asserted to end the CPU write operation.
M hh
s WaY
11

PENDING
its IDLE

to
be
state.

[

CYCILFE
S NP 1 | |

atate

[

causesg
LR O B

SYNC

REO
s

cleared, which returns the slave port sequencer to
DMA
to
The slave port sequencer can then respond

requests with DMA transfers occurring during the time a VAXBI write
transaction is being retried and before
the
CPU
write
operation

.
0

>‘A

(O]

ends.

3.3.3.3
data

Return

(Figure

transaction
return

but

read

transaction
Like

the

return

Data

can

data

the

The

end

may

start.)

The

return

write

data

four

basic

the

opposite

direction

The

NBIB

loads

the

VAXBI

return

BCI

data

buffer.

The

NBIB

buffer
3.

4.,

its

transfers

into

its

The

NBIA

loads

data

bus

buffer

The

NBIA

the

transaction

and

then

the

data
the

read

data

(or

read
IDENT)

VAXBI
the

for

read

transfer
an

IDENT

its

the

transmits

data

(received

from

the

BCI

Data/Vector

Following

the

BIIC),

state.
CLE,

This

latch

data

held

transaction

reads

into

its

data

the

NMI
the

return

data
NMI

the

NBIB's

buffer.
read

buffer

when

data

(ND

from

MCAs),

wins

the

from

When

BIIC

the

node

cycle),

(also

and
A

loaded

VAXBI

be
node

STALL

data
be

(in

the

return

delayed
not

together

and

RAK

control

data

buffer's

enable

asserted

though

return

the

return
VAXBI

asserted

the

READ

assert

internal

continuously

read

data

has

data

before

NXT

BCI

buffer

data

the

cycle,

from
cycle

BCI

and

asserted.

VAXBI's

(in

the
(or

MY
and

long

yet

been

responding
IDENT

then

vector

asserts

NXT

bus

cycles.

return

the

read

ACK

CNF

lines.

response.

stalled.)

X 3-49

The

lines,

status
also

the

received

L6).

the

data
data

CYCLE

(The
NBIB's own BIIC may be the responding
that the return read data is
loaded
in
the
L4)

with

the

read
read

one

ready

response

buffer

BCI

even

asserted

read

for

data
the

(MDE

advances

latch

the

BCI).
is such

data,

NBIB's

transmits

buffer

read

cycle

sequencer

VAXBI.

receives

the

port

asserts

and

during

Timing

data

return

the

first

node.)
BCI

the

The
1,

Buffer

command/address

turn,

enable.
CLE

Data

master

causes

received

VAXBI

BCI

VAXBI

the

which,

its

data

bus.

Read

of
data

NMI).

read

own

NMI,

the

transfer
However,

buffer.

return

buffer

the

operations.

(VAXBI

return

bus

into

requests

return

read

before

transfers,

into

VAXBI

retried

passed

BIIC)

transfer
the

vector.

and

consists

command/address.

IDENT,

interrupt

command/address
read

not

data

Transfer

occurs

1initiated

transaction,
of

Read
3-13)

VAXBI

write

That

is,

data

when

data

right

away,

Then,

when

ready,

(An

IDENT

vector

cycle,

an
it
it

can

addressed
can

send

sends

cycle

the

cannot

DATA

BUS

NBIA 4—|— NBIB

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Figure

3-1 3

VAXBI

Return

Read

Data

Transfer

(Sheet

TRANSACTION

BUFFER

AEAD
NBIA_DATA/FUNC

XMIT

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Figure

3-13

VAXBI

NMI

Return

Read

Data

Transfer

(Sheet

Read Data/Vector to Data Bus Buffer

the NXT signal
loaded,
Immediately after the BCI data buffer is
the data buffer control to assert I TO F RD EN and a latch
causes
buffer
bus
enable, transferring the return read data to the data
when
NBIA
the
The data status code, which is not used by
L2).
(toc
code
the
That is,
it takes the data from L2, is not transferred.
in
loaded
Zeros are
is not passed through the NBIB's I to F logic.
L2,

instead.

End of VAXBI Transaction

(and Retries)

from
data
The BIIC acknowledges that it has taken the return read
for
lines
node by generating an ACK response on the CNF
the VAXBI

the next two bus cycles.

The BIIC also deasserts RAK (on the

BCI)

This causes the master
of the transaction.
end
the
indicate
to
If
port sequencer to check the event code asserted by the BIIC.
the event code is an MCP code, indicating the transaction completed
successfully and good data was

asserts

CPU

received,

the master port

sequencer

DONE to the NBIA ending the CPU read operation in the

NBIB.

can be
transaction,
A VAXBI read transaction, like a VAXBI write
be retried.) That is, a
transaction cannot
IDENT
(An
retried.
ends
RETRY response on the VAXBI's CNF lines by the addressed node
master
the
and
deserted
is
RAK
when
Then,
transaction.
the current
the
(an RCR code),
code
port sequencer checks the BIIC event
sequencer requests another VAXBI transaction and eventually returns

1
(RAK =
to the READ CYCLE state when the transaction is retried
additional
any
for
process
this
repeats
sequencer
The
again).
read
good
returns
finally
When the VAXBI node
retry responses.
as
asserted
is
DONE
CPU
and
NBIB
the
in
loaded
1is
it
data,

previously described.

REQ
SYNC
causes
state
CYCLE
READ
sequencer's
The master port
advance
to
sequencer
port
slave
the
allowing
cleared,
be
to
PENDING
to
respond
then
The slave port sequencer can
to the IDLE state.
read
VAXBI
a
when
occurring
transfers
DMA
with
requests
DMA
transaction is being retried and before the CPU read operation ends
in

the

NBIB.

Read

Data/Vector

When

the

asserts

NBIB

loads

SET

CPU

command/address
generating

the

may

also

which

the

to NBIA's

case,

NBIA's

causes

case,

the

(from

L2)

Also,

the

return

DONE,

the

NBIB)

necessary
in

the

TTL

set)

the

Transaction

idle

SET

clock,

the

read

NBIA's

Buffer

data
data

normally

read

and

its

bus

latch

enables

assert

CPU

write

transaction

take

the

already
the

data.

transferring

DMA

DONE

signal

(after

synchronized

and

with

internal

and

latch

enables

SET

the

state

and

sent

(after

CPU

synchronized

buffer

state

being

control
to

CPU

DONE

data

DONE.

The

buffer

location

1in

signal

the

return

read

CPU

PEND
either

data
buffer
buffer (to L4).

data

the

transaction

data

for

RD
1In

in
to

NBIB's

causes

NBIA's

reserved

bit

data),

generated.

data is transferred from the
across
the data bus to the NBIA's

bus

(which

wait

return

control

data

control

1is

data

bus

buffer

and

1in

the

and

write

written

both

CPU

read

data.

Read

Data/Vector

The

CPU

DONE

RDY

and

transaction
(and

write

The

BUFFER

CPU

NBAP

cycle

and

prevent

DMA

cleared

before

may

begin

local

This

the

ECL
the

the

being

input

the

EBUS

(in

and
CPU

read

DMA

assert

data

from

(in

the

written

transmit
for

BUSY

into

sequencer

return

signal

NBFD MCA)

the

(cleared
are

not

Causes

the

1is

from

BSY

the

operation.)

does

the

same

The

bus

wused

starting

thing,

receive

but

the
been
it

sequencer

however.

the

DC022

NMI

read

(I/O

ARB

function

1is

(READ

asserted
CPU

read

the

MCAs).

the

data

NMI
The

NBIB)

(from

data
MF

bits

are

the

buffer's

transaction

EBus

DATA).

associated

also

loaded

BUF

BSY

cleared

X 3-53

the

buffer)

receive
with

the

NPAR

MCA.

latches

the

NBIM

used.

CPU

data

following:

return

BUF

requests

asserts

loaded

the

sequencer

does

(CPU

end

the

command/address

from memory.

NMI

the

translation
MCA

being

returned

request
The

DSEQ

return

delayed

sequencer

NMI.

also

Causes

read

read/write,

transmit

bus),

function
1.

causes

operation)

state.

receive

the

will

write

signal

advance

transmitted

and

data

causing

TTL

clock,

This
DMA

Cycle)

CPU read/write that requires a VAXBI transaction until
the operation, that is, when the return read data has

end

When

BUSY,

Data

after
ECL

read

RDY

MCA

the

another
of

the

EBUS

data

the

buffer.

memory,

(NMI

signal,

synchronization
BUFFER

to NMI

MCA

data

but

The

transmit

READ

DCO02Z

DATA

(BI

READ),

and

select

the

granted

sequencer
or

then

READ

RTRN

information
the

The

NBIA

NMI

from

NMI

data

its

the

data

line

<9>

for

1),

read
PAR

read

local

the

depending

read,

NMI.

these

1is

offset

transmits
it

(now

NMI

and

<13:9>

vector

whether

bus

data

the

vector,

also

signals

the

read

(bits

equal

occurs:

latches)

(either

code

When

return

device

(13:10>.

SEL

following

the

data

VAXBI

function

MUX

transmit

transmits

lines

the

transmits

return

buffer

NMI

nonoffsetable

NBI

returned

ENABLE

buffer

1into

lines.

CSRO)

VECTOR),

DATA.

(NMI

data

clocked

asserts

DC022

0),

the

wvalue

data

NBIAQ

(in

1
or

NBIAl.

The

NBIM

MCA

transmits

command/address
3.

The

NBFD

MCA

cycle

transmits

the

NMI

RTN

DATA

lines.
This

ends

the

CPU

read

the

operation.

saved

ID/MASK

during

the

lines.

function

the

NMI

FUNC

3.3.3.4

Parity

Generation

Command/Address
During

the

line

parity

that

require

generated

described

3.3.2.4).

The

error

detected

1is

NMI

Checking

Data/Mask

command/address

transactions

bits)

and Write

and

write

VAXBI

and

for

checked

transaction

(against

not

and,

Both

bit

(PMF)

NBIB

over

data

parity

are
the

data/mask.
NPAR

thus,

VAXBI

bit

(PD)

loaded

data

These

and

bus

along

bits

(both

write

control

with

received

data

parity

(Section

cycle.

parity

Also,

has

NMI

control

bad

(mask/function)

the

buffer

and

bits)

are

never

parity

passed

command/address

parity

the

parity,

That is, a CPU REQ is
never takes place.

transaction

even

of
and

operations

acknowledged

transaction

the

data

the

command/address

command/address has good parity but the
no
data
1s
written
1in
a register.
generated

cycles
NMI

read/write

the

data

transaction,

1local

during

Parity

generated

the

write

the

MCA.

generate

(address

command/address
1.

Gates

buffer

(These

the

NMI
bits

data

bits

are

not

affected

bits

are

PMF

parity
1in

FUNC

and

loaded

are

cleared

1in

the
are

not

the

same

before

function

way

ID/MASK
1in

the

both

value,
in

parity)

during

following:
to
the
both the

NMI

data

buffer

buffer,

are

1.)

data

transaction
same value.

before

parity

the

two

the

NMI

parity

the

transaction

data

bit

buffer.

not

an IDENT, gates the NMI
FUNC
the NBIM MCA to the transaction

NMI

control

because

lines.)

function

the

transaction

computed

received

any

(function

transaction

loaded

computed

(The

PMF

MCA does

parity
bit
and <25> are

<26>

both

the

buffer.

the

and

NPAR

data

loaded

bit

used

the

data

they

inverted
2.

parity)

transfer,

For

buffer),

parity

computed

IDENT
the

bit
for

cannot
both

function

NPAR

MCA

bit.

simply

and

PMF

(mask

does

the

following:

does

makes

the

be
NMI

(11001
not

use

PMF

during

1.
To

generate

write

data
1.

(write

transfer,

Gates

data

the
the

parity)

NPAR
NMI

MCA

data

parity

bit

parity)

the

transaction

buffer,
2.

PMF
NBIM

Gates
MCA

control
for

both

the
to

the

parity
the

NMI
bit

NMI

ID/MASK

parity

transaction

cannot

FUNC

and

X 3-55

bit

buffer.

used

because

ID/MASK

lines.)

computed
(Again,

the

NMI

computed

Data and control line parity are not checked in the NBIB until
the
command/address
or
write
data/mask are transferred from the data
bus buffer to the BCI data buffer.
1If a parity error is
detected,
(NBIB
signal
error
an
asserts
er
parity generator/check
NBIB's
the
PE).
A
parity
error
does
not
prevent
the
operation
from
(The VAXBI transaction is executed.) However, NBIB PE
continuing.
interrupt
NBI
an
sets an error bit in the NRIA (in CSR0O) causing
may be forced during diagnostic operations by
error
An
request.
setting

a control

bit

(FORCE NBIB PE)

in CSRI.

Dbit
parity
single
a
The parity generator/checker also generates
This bit, the
command/address and write data/mask.
the
for
(PQ)
(along
and
VAXBI odd parity bit, is loaded in the BCI data buffer
BIIC
the
to
passed
is
data/mask)
write
or
command/address
the
with
(The
transaction.
VAXBI
the
during
VAXBI
the
on
and transmitted
for
bit
parity
VAXBI
the
generate
to
enabled
not
1is
BIIC
NBIB's
information supplied by the NBIA.)

the
from
PO for write data/mask information is generated directly
PMF
the
However,
PMF).
and
(PD
NBIA
the
by
sent
bits
parity
two
1is
This
bit cannot be used to generate PO for a command/address.
VAXBI
a
to
translated
is
NBIA
the
by
sent
function
the NMI
because
logic
I
to
F
As a result, the
command as explained previously.
function.
NMI
the
translates
it
when
bit
parity
the
regenerates
The parity generator/checker then uses this regenerated value (PI),
together with PD, to generate parity for the command/address.

command/address
If the BIIC transmits bad parity during the VAXBI
VAXBI) set an
the
to
connected
it (and BIICs in other nodes
cycle,
Dby means
request
interrupt
internal bus error bit and generate an
during
parity
bad
If the BIIC transmits
transaction.
INTR
an
of
data)
the
taking
node
the
the write data cycle, it (and the BIIC in
(The
request.
an internal error bit and generate an interrupt
set
NBIB's BIIC could also be taking the data.)

RETURN

READ

DATA

PARITY

is
data
the
Return read data parity is checked by the BIIC when
the
until
again
It is not checked
VAXBI.
the
from
taken
first
NBIA,
the
return read data is read from the transaction buffer in
and
bit
error
an error, it sets an internal
detects
BIIC
the
If
generates

interrupt

request.

X 3-56

To generate both data and control parity
(PD
and
PMF)
bits
transmission
to
the
NBIA (the single PO parity bit received
the VAXBI and asserted by the BIIC is not used), the NBIB does

for
from
the

following:

PD -

The

the

VAXBI

parity

generator/checker

data when

the

data bus buffer.
The
buffer
(along
with

data

computes

even parity

transferred

the

for

NBIB's

parity bit is gated to the data
the
PMF
bit)
by the NBIB's I

bus
to F

logic.

PMF - When the I to F logic gates the PD bit to
the
data
bus
buffer,
it
gates
a
PMF (even parity) bit equal to
zero.
This is because no VAXBI control information
(read
status)
1s
1loaded
1in
the
data
bus buffer.
Zeros are
loaded and taken by the NBIA along with
the
return
read
data as explained previously.

The NBIB generates bad (odd) parity for both the data
and
control
information
(zeros)
taken by the NBIA if the FORCE NBIB PE bit in
CSR1 is set.
In the NBIA, when the
buffer, the following

return read
occurs:

data

read

from the

transaction

The NMI data buffer generates parity for
each
data
byte
(the data is now in the buffer's EBus receive latches) and
the NBIM generates an even
parity
bit
for
the
control
information (zeros in this case).

The NPAR MCA then completes the data parity
checks
the result with the data parity bit
the transaction buffer.
Also, it compares

generation and
(PD) read from
the
generated

control
parity bit with the control parity bit (PMF) read
from the transaction buffer.
If
an
error
1is
detected,
NBIA
DATA
PAR
ERR
or
NBIA
FUNC
PAR
ERR
sets
the
corresponding parity
error
bit
in
ND1
(CSRO)
or
NDO
(CSR1), causing an NBI interrupt request to be asserted.
The NPAR MCA also generates the NMI data and
control
1line
parity
transmitted
during the NMI return data cycle.
It uses PD from the
transaction buffer to generate
the
data
1line
parity.
However,
similar
to
a
1local read, it uses the parity bit generated by the
NBIM MCA
control

(which
line

transmits

the

saved

parity.

X 3-57

the

NMI)

(dgenerate

3.3.4

Write

Sequence

Faults

A
write
sequence
fault
can
be
detected
during
a
CPU
write
operation.
If an NMI write data cycle does not immediately follow
the NMI
(which

command/address cycle,
1is
waiting
for
the

the
NBFD
MCA's
receive
sequencer
write
data) asserts WRT SEQ FLT and
advances to the idle state.
This signal causes
the
corresponding
error
bit
to be set in CSRO.
The error bit, in turn, asserts the
NBI's FAULT DETECT line on the NMI, which causes
a
CPU
interrupt
request
to
be
generated.
The
write
sequence
fault
ends the
operation with no data being written in an NBIA register (during
a
local
write) or the transaction buffer (for a VAXBI write).
Also,
for a VAXBI write, timing is such that WRT
SEQ
FLT
prevents
the
NPAR
MCA
from
asserting
a CPU request signal and, thus, a VAXBI
transaction is not initiated.

3.3.5
NMI Bus Access Timeouts
When the NBAP MCA requests the NMI in order to
return
read
data,
and
the
bus
is
not
granted after two system slow clock periods

(approximately six milliseconds at the normal system
clock
rate),
the MCA's bus access timeout counter asserts an error signal.
This
signal (BUS ACCESS TMOUT) connects to the timeout
encoder
in
the
NBCT
MCA.
The encoder then asserts the appropriate timeout error
code, which is loaded in CSRO causing an NBI interrupt
request
to
be

asserted.

3.3.6

VAXBI

Errors

Once the NBIB has initiated a VAXBI transaction on the
VAXBI
(RAK
asserted
by
the
BIIC),
any
BIIC
event
code other than an MCP
(transaction completed successfully) or a RCR (retry)
code
causes
the
master
port sequencer to assert SET CPU ERROR.
(SET CPU DONE
is not asserted.) Some of the events that can cause the
CPU
error
condition

are

follows:

Read data substitute (RDS) error - Addressed
bad (uncorrectable) read data/vector.

Bad

parity

bad

parity.

(BPR)

Returned

Retry
timeout
(RTO)
Addressed
consecutive retry responses.

data/vector

had

node

returned

4096

NOTE

the

BIIC.

an
0 ¢]

detected

returned

read

Refer to the event code descriptions
3-1
to see all the error conditions

(%)

received

node

in Table
that can

Also,

the

master

transaction

port

has

sequencer

been

deserted),

and

code.)

The

bus

timeout

the

VAXBI

after

4096

bus

all

cases,

when

the

BIIC's

asserted,

the

failure

and

SET

ERROR

CPU

bus

ends

Causes

the

write,

CPU
the

leaving

the

For

CPU

transmit

(CPU

DONE

normal

CPU

read

transmit

NMI

ENABLE

when
BI

ends

CPU

the

state

ends

DONE

clear

CPU

BUF

the
BSY

acknowledge

the

ZEROS.

(in

and

the

MCA

last

request

the

bus

request

during

transmit

sequencer

ZERO)

causing

then

the

asserts

the

normal

case.

Except

for

NMI

data

«cycle

normal

the

function

read/write

not

ERROR

the

NBIB.

shortly

transaction

NMI

after

The

the

ID/MASK

(data

with

the

terminated

NBIA

and

return
one

corresponding

buffer.

buffer

transaction

Actually,

the

NBIA's

the

data

a
an

granted

transmitted

operation

the

connected

case,

described.

transmitted

DATA

detected

CPU

from

NMI.

asserts

NMI

from

this

CPU

causes

MCA

read

1In

clear

cause

case,

NBAP

data

special

the

liines.

MCA)

the

(RTRN

that

asserted.

NBIB

the

RDY

bus

CPU

is,

signal

the

be
the

NPAR

execute

DSEQ

This

That

once

not

operation

asserted.

NMI

condition

access

assert

idle

the

RTN

get

follows:

NBIA

returns

then

RTRN

The

FUNC

previously

CPU

BUF

(saved)

command/address

operation

causes

controller

cannot

0).

BIIC

request.

ERROR

and

sequencer

the

addressed

identify

CPU

lines

PRESENT

ERROR

address.

commander's

error

CPU

VAXBI

function

zeros,

event

SET

ERROR

free

zeros

BTO

bit

read.)

still

error

also

assert

sets

NBI

buffer

one

and

asserts

read.

MCA

read,

BSY

BIIC

VAXRBI

causes

when

(The

a
(RAK

code

control

CPU

NBIA

read/write

the

DSEQ

CPU

BUF

CPU

normally

causes

CPU

bus

For

initiated

internal

event

control

ERROR

yet

cycles.

read/write

CPU

not

the

CPU

data

SET

when

interrupt

operation
a

The

occurs

but

occurs.

condition

sets

generates

ERROR.

timeout

BIIC

asserts

requested

NMI

occurs

bus

input

data

bus

reading

the

operation

then

3.4

DMA READ/WRITE OPERATIONS

through
A VAXBI device can access the system's memory (on the NMI)
by
specified
is
addresses
memory
accessible
of
the NBI. The range
and
starting
the
in
control)
program
the values loaded (under

All memory
located in the NBIB's BIIC.
registers
address
ending
addresses, by definition, have address bit <29> equal to 0.

When a VAXBI read/write transaction makes a memory reference within
the specified range of addresses, the NBIB responds by first taking
write
(and the write data for a VAXBI
the command/address

The NBIA
the VAXBI transaction.
stalls
then
It
transaction).
from
data)
write
(and
ress
command/add
the
taking
responds by first
After
.
transaction
read/write
NMI
an
initiating
the NBIB, and then

the NBIA takes all the write data, the NBIB ends the VAXBI write
This is before the data has been written into memory
transaction.
(a disconnected write). A VAXBI read transaction continues to bDe
stalled.

If an NMI write transaction is initiated by the NBIA, it transmits
immediately after sending the
memory
to
data
write
the

command/address.

This ends the NMI write transaction and completes

a DMA write operation.

the
initiated by the NBIA,
read transaction 1is
If an NMI
NBIA.
the
to
data
read
the
transaction ends when the memory returns
it on the
which transmits
The data is then passed to the NBIB,
completes
This
.
transaction
ending the (stalled) VAXBI read
VAXBI
a DMA read operation.

As shown, a
DMA read/write operations are summarized in Table 3-4.
or
quadword,
(which may specify a longword,
transaction
VAXBI
length
same
the
of
n
octaword transfer), initiates an NMI transactio
The exception is for a VAXBI read gquadword
with one exception.
Because there is no NMI read quadword transaction, an
transaction.
The NBIB then
read octaword transaction is initiated instead.
NMI

returns only the addressed quadword to end the VAXBI transaction.
in Figure 3-14, the addressed quadword will be the first
As shown
is
the address
two longwords in the octaword read from memory if
wrapped
(a
However, if the quadword address is unaligned
aligned.
longwords
quadword read), the quadword will be the first and last
read

from memory.

X 3-60

Table

VAXBI
Transaction
(Note 1)
WR/WCI

DMA Read/Write Summary

Data
Length

NBI

L
[0]%)

STALL --> [ACK,ACK,ACK]/RETRY
ACK,STALL --> [ACK,ACK,ACK]/RETRY

OwW

UWMCI

3-4

Response

ACK,ACK,ACK,STALL -->

STALL -->

[ACK,ACK,ACK]/RETRY

Resulting NMI
Transaction
(Note 2)

See
Note

WL
WOM

3
3,4

WLUM

ow
ow

ACK,STALL --> [ACK,ACK,ACK]/RETRY
ACK,ACK,ACK,STALL --> [ACK,ACK,ACK]/RETRY

WQUM
WOUM

3
3

WMCI

L
oW
OwW

STALL --> [ACK,ACK,ACK]/RETRY
ACK,STALL --> [ACK,ACK,ACK]/RETRY
ACK,ACK,ACK,STALL --> [ACK,ACK,ACK]/RETRY

WLM
WOM
WOM

3
3
3

RD/RCI

L
QoW
QW
OwW

STALL
STALL
STALL
STALL

RL
RO
RO
RO

6
5,6
5,6
6

RLI

IRCI

OW
QW
OwW

(A)
(UA)

--> ACK/RETRY
--> [ACK,ACK]/RETRY
--> [ACK,STALL,STALL,ACK]/RETRY
--> [ACK,ACK,ACK,ACK]/RETRY

STALL --> ACK/RETRY

(A)
(UA)

STALL -->
STALL -->
STALL -->

[ACK,ACK]/RETRY
[ACK,STALL,STALL,ACK]/RETRY
[ACK,ACK,ACK,ACK]/RETRY

ROI
ROI
ROI

5,6
5,6
6

NOTES:

VAXBI

Transaction

types:

WR = Write

WCI = Write (Cache Intent)
UWMCI = Unlock Write Mask (Cache Intent)
WMCI
NMI

= Write Mask
Transaction

(Cache

RD =

Read

RCI = Read (Cache Intent)
IRCI = Interlock Read (Cache

Intent)

Types:

WL/WO = Write (Longword/Octaword)
WLM/WQOM/WOM = Write (Longword/Quadword/Octaword) Masked
WLUM/WQUM/WOUM = Write (Longword/Quadword/Octaword)} Unlock Masked
RL/RO = Read (Longword/Octaword)
RLI/ROI = Read (Longword/Octaword)

Interlocked

NBIB stalls VAXBI write transaction until NBIA takes command/address and write data. NBIA
retries NMI write transaction if no response from memory, or if MEMORY BUSY asserted during
command/address or
Write mask

set

first data
all

ones

cycle.

by NBIB

hardware.

VAXBI read quadword transaction causes octaword to be read from NMI memory.
{(No NMI
quadword read transaction implemented.)
The quadword read may be aligned (A) or
unaligned

(UA).

NBIB stalls VAXBI read transaction until NBIA returns read data from memory. NBIB also

stalls transaction between data cycles of an unaligned QW read due to the reordering of
NBIA retries NMI read transaction if MEMORY BUSY asserted during command/address
data.
cycle. NBIB requests retry of VAXBI read transaction if bus access timeout or retry
timeout

NBIA.

X 3-61

X---X0000

LW 1

0100

LW 2

1000

Lw 3

1100

ALIGNED
ALIGNED

QUADWORD

OCTAWORD
IN

NMI

MEMORY

MEMORY ADDRESS
FROM VAXBI
ALIGNED

QUADWORD

READ

DC022
ALIGNED QN READ
MEM ADR = 0000

(

) »

UNALIGNED

QW READ

(MEM ADR =

0100)

ADR<2>

ALIGNED
(MEM

DATA

ORDER _TO VAXBI

W 0

Do ———P

W 0

D1t —TM

LW 3

D0——p

LW 2

LW 0

W 3

tw 0

W 2

DO—p»

tw 2

LW 3

DI———>»

W 3

LW O

LW A

Do——

LW o

W 2

Lw 2

QW READ

ADR =

ADR

BUF

UNALIGNED
(MEM

XACTN

1000)

QN READ

ADR<2>

1100)
=

SCLD-465
-

Figure

3-14

Aligned

and

Unaligned

X 3-62

Quadword

Read

Data

Ordering

Referring

again

transactions

Table

with

3-4,

cache

you

can

intent

are

see

that

treated

VAXBI

read/write

ordinary

reads and
system does not
support
cached
VAXBI
operations.)
Also,
a
write
mask,
interlock
read, or unlock write mask VAXBI
transaction
1initiates
a
corresponding
NMI
transaction
(write

writes.

(The

masked,

read

ordinary

quadword

write

are

masked

NBIB

1interlocked,

writes.)

forces

VAXBI)

write

all

The

transfer

and

NMI

NMI.

(All

result,

the

mask

ones

before

during

the
DMA

unlock

WR/WCI

the

write

(VAXBI

bits

NMI

for

are

command/address
read/write

write

these

(received

they

passed
and

However,

causes

quadword

VAXBI

with

operations

X 3-63

masked).

transaction)

the

transactions

transactions,
write

the

data

shown

masked

data

the

from

the

NBIA.
between
in

the

Figure

VAXBI
3-15.

C/A CYCLE (DMA

VAXBI

READ/WRITE TO NMI

R'W CMD

MEMORY ADDRESS)

LNG

ADDRESS

TRANSLATED

31 30 29

LNG

ADDRESS

RW PUNC

DATA BUS

pD—]

PMF

l
PD

EVN

PMF

PMF PARITY BIT
INVERTED IF NBI
ID

NBI 1D

03
NMI

‘

EVN

HAS ODD NUMBER

OF BITS.

CMDR'S D

R'W FUNC

ID/MASK

FUNC

31 30 29

ADDRESS

EVN

ADDR ESS/D.ATA

DAT
PAR

CTL
PAR

LNG

NOT
USED

WRITE DATA CYCLE (DMA WRITE TO NMI

VAXBI

{

MASK

MBMORY ADDRESS)

WRITE DATA

MASK BITS FORCED TO 1

IF VAXBlI WR/WCI XACTN.

04
MF

DATA BUS

abD

PMF

EVN

MASK

WRITE DATA

]

v
PMF

EVN

1001

NMI

MASK

WRT DATA

WRITE DATA

EVN

ID/MASK

FUNC

ADDRESS/DATA

DAT
PAR

CTL
AR
SCLD-466

Figure 3-15

Basic Information Flow Between VAXBI and NMI During

DMA Read/Write Operations

X 3-64

(Sheet 1 of 2)

RETURN

READ DATA CYCLE (DMA

VAXBI

STATUS

READ TO NMI

MEMORY ADDRESS)

READ DATA

TRANSLATED
04

DATA BUS

STATUS

READ DATA

03
NMI

1’

PWF

EVN

PMF

EVN

(READ DAT, ) STATUS)
NBI 1D

|
o

obD
A

PMF ——

CMDR'S (D

RRD/RD CONT

READ DATA

ID/MASK

FUNC

ADDRESS/DATA

EVN

DAT

CTL

PAR

PAR
SCLD-467

Figure

3-15

Basic

Information

DMA Read/Write

Flow

Between

Operations

X 3-65

(Sheet

VAXBI

and

NMI

During

3.4.1

The

Command/Address

transfer of

(Figure

3-16)

Transfer

the command/address

consists

three

from

basic

the

VAXBI

the

NMI

operations.

The NBIB transfers the VAXBI command/address
received
by
its
BIIC
into
its
BCI data buffer and then immediately
into

its

data

bus

buffer.

The NBIA transfers the command/address held in the
data bus buffer into its own transaction buffer.

The NBIA requests the NMI, reads the command/address
its
transaction buffer into its NMI data buffer, and
transmits the command/address on the NMI when it wins
bus.
During a DMA write operation, the requesting
NMI and the reading of the command/address into the

transaction
buffer
does
transferred all the write
Section 3.4.2.)

not
data

occur
until
from the NBIB.

NBIB's

from
then

the

of the
NBIA's

the NBIA has
(Refer
to

3.4.1.1
Command/Address
to
BCI
Data
Buffer
and
Data
Bus
Buffer -- When
the
BIIC detects a VAXBI command/address cycle, it
asserts CLE and transmits the command/address on the BCI.
The
CLE
signal

does

the

following:

Causes the VAXBI command/address transmitted by
the
BIIC
to be loaded in the BCI data buffer.
The VAXBI address on
the BCI data lines is loaded in one set of
latches
(L4).
The
VAXBI command on the BCI I lines is loaded in another

(L6).
2.

In addition, latches the VAXBI
set
of latches located in the
outputs, (BUF 1I<3:0>), connect
the I to F logic.

Also stores the state of
line <2> in latches (BUF
length counter 1logic.

command on the I lines in a
interrupt logic.
The latch
to
decoding
circuitry
1in

BCI data lines <31:30>
and
data
D <31:30> and <2>) located in the

N
o)

CLE also advances the slave port sequencer to the WRITE
C/A
state
unless
the
NBIB
1is about to do a VAXBI read/write transaction as
the result of a CPU read/write request.
1In this
case,
the
slave
port sequencer will be locked in (or advance to) the MASTER PENDING
state.
The sequencer is locked in the MASTER PENDING state by
CPU
REQ PENDING as discussed in Section 3.3.3.1.

LOAD COMMANDVADDRESS

DATA BJS

DATA BUS BUFFER

NBIA<~—I—D NBIB
DATA BUS BUFFER

D I

BCI

DATA BUFFER

BCi

ADDRESS

GEN/CHK

[:I

Po
1

(FUNC)

L9-€ X

31:30>

< <2>

(

(NOT USED)4——
f
U

L16

(Bi

CMD

Po
:

[=R/W

——1=BW__|

CLE

FTO |
E

|
TM
CMD/MASK

TOF

MASTER
SEQ

LnaTH

CNTR

CNF=ACK/ST

CMD

ALL

¢—BUF D<31:30>

551,99

¢—

semv

L6|LTCH EN
DATA BUF
cTL

ADDRESS

PARITY

BUF | (BI cMD) | \nR
|_TO F

'>}

—

;]

ADDRESS

[

RS=ACK/STALL
]

LoGiC

_RD EN

CLE

SLAVE

PORT

SEQ STATES

l——SPSa1

)
DMA READ (IF

RD CMD)

]

[T pala

g | IR By

SYNC

SELNOT INYTR

TAL

CMPL

AIT

e ,J

SCLD-s

Figure

3-16

VAXBI

NMI

Command/Address

Transfer

(Sheet

ND<3:0>

<
k4~

ADDRESS

TM~ :%

_NBIA_DATA/FUNG PAR_ERR

{

89-¢ x

|D/MASK-ID

110 SEL

}

NBIM __EBUS ACV PAR FUNC

0 -»CRU BUS
BSY

|
'.

Kiir Lo

LTCH

NMI_ENABLE

%\‘E0?4!:

DMA C/A XMTD

NBAP

¢ DMAREQ
|- PAR MUX SEL=3

| DC FUNC-1.2

> J_} T

WRITE DATA
NOTE: FIRST LONGNORD OFTRANSAGCTION
BUFFER
CAN BE READ FROM

BEFORE NMI 1S WON (NMI ENABLE-1
AND T?ENCOMMI MANDVADDRESS TFANSMITTED

ON T H

C/A TYPE —M

‘

|
|

NOP

LTCH

]‘

SYNC SEL

DATA BUF

i|
I

| - _SEL NOT_INTR
I

RO DMA C/A

2 | RD DMA DATA
3 | RD CPU DATA

DMA REQ NOT ASSERTED UNTIL ALL
WRITE DATA LOADED IN TRANSACTION

BUFFER |F OMA WRITE OPERATION.

Figure 3-16

ME(FUNG)
fi

DMA’ REQ 0

RO
T"LOCAL

DC022 READ FUNC
0

|
SYNC/XLATE

PAR MUX SEL

|
C7A
XMIT
351 || XMIT
DATA

OC DATA
VECT
65 | RDRD NBI
4

»-

o | NoP
3

[¢--~C/A TYPE

NMI ENABLE

NBI READ FUNCTION

B &R
)| g{T)N
D(?.;EeggT

|—# RD FUNC-5

Lé RD EN !

ECL4—|—® TTL

T
BIO OMA REQ

NBCT

DCO22 g

cTL
(TTL)

EBUS BUSY
DC FUNCa1—]

*—

WR| ADR-00

DMA REQ

[

DSEQ

NMI ENABLE |

ADDH|ESS

DATA BUS BUFFER

]

L2|RD

4~ DC FUNC-1

11O _ARB
1/0 BUS EN

DATA| BUS

FD ADR=00

- C/A TYPE
}—

I::l

ME (FUNG)

FUNG

|4—-PAR MUX SELe3

EBS e LTCH|

NBIA €—|—# NBIE

[:I

|
< FUNC - AW

o« PMF

NPAR

FUNC_PAR

DC FUNC-1

< DATA PAR
PAR MUX SEL=3

Y [ ADDRESS I MFI PDIPMd

DC FUNC-1

NMI_ENABLE

I l

‘_L ) " ADDRESS

FUNC 1D _PARITY

T pus | 2SO DATA BUFFER

XMIT BYTE PAR

DATA PARITY

110 SEL:

10N BUFFE R
TRANSACTION
:
LOAD COMMANDADDRESS/1{

DC022 TRANSACTION BUFFER

£8US

——

ECL

CYCLE
NMI COMMANDYADDRESS
oo

VAXBI to NMI Command/Address Transfer (Sheet 2 of 2)

SCLD 19

When

the

sequencer

control

asserts

command/address
bus

buffer

logic and
command.

(in

(if
The

provided

address

the

BIIC's

case,

the

BIIC

read/write

then

advances
WAIT

DMA

READ

and

the

SEL

Asserts

2.,

Transmits
BIIC.

SEL

NOT

1is

data

was
slave

will

port

transaction
In
CPU

one

other

the

after

to
on

signal

buffer

moving

the

data

DMA

during

the

transmitted
data

STALL

code

all

others

until

the

STALL

code

and

the

VAXBI

NBIA.

1lines

BIIC

the

transmitted

depends
the

the
the

return

transmitted

transaction.

circuitry

cycle

(and

NBIA

WAIT
output

latched

read,

the

by
the

following:

READ

the

CLE.

the

just

request)

first

this

NMI
NBIA

1is,

decoder

from

the

specified

asserts

does

code

either

then

code

the

That

range

whether

decoding

STALL

write,

BIIC,

read

upon

length

the
the
one

can

move

CPU

REQ

DMA
1is

sending
a

DMA

the

CPU

has,

read/write

the

RETRY

code

device

WRITE

C/A
is

can

requests)

read/write.

X 3-69

code

the

(if

That

state

CNF

the
the

and

the

when

the

has

the

locking

lines)

when

retry

retried.

SEL

retry

retries
is,

request

accepted

from

the

received

being

when

cleared

read/write

itself,

state

requests
on

cleared.

PENDING

process

retry

RETRY

VAXBI

PENDING

or
the

PENDING

sequencer

(asserts

the

request.

MASTER

port

requests

REQ

the

transaction

initiated

make

slave

CPU

sequencer

device-(by

the

returned

wuntil

words,

the

Retry

successfully

(This

memory.

cycle

sequencer

the

read/write

needing

BIIC).

read/write

completed

read/write

the

continue

slave

data

1into

registers.

depends

sequencer

NMI

within

sequencer

lines

cycle.

transaction)
DMA

buffer

state

first

port

asserted
DMA

data

the

enable

1is
also
transmitted
during
the
length is a quadword or octaword, an
code is transmitted.
(The data length, BUF
D<31:30>,
previously latched in the data length counter logic.)

ACK

state,
latch

port

returned

longword,

the

C/A
a

address

INTERRUPT

ACK

1length

first

lines

BCI

falling

determines

CNF

the

VAXBI).

the

that

The

VAXBI

data

the

not.

logic

transaction.

and

immediately

The

This

during

WRITE

directed

slave

<3:0>).

the

ending

STATE.

asserted

the

BUF

to
RD

address

asserts

WRITE

loaded

memory

starting

L6).
The VAXBI command is passed through the I
a read/write) is translated to
the
appropriate
command/address is then ready to be taken by the

SEL

command,

just

located

advances
I

VAXBI
either

request.

NBIB

when

This

prevents

out

another

3.4,.1.2
SEL

Command/Address

NOT

the

NBIA

INTERRUPT

NBIA's

TTL

asserts

to NBIA's Transaction

signal

clock),

the

received

the

necessary

from

associated
read

and

data

latch

Buffer

NBIB

-- When

(and

bus

controller

enables

the

synchronized

the

transfer

the

command/address from the NBIB's data bus buffer (from
L6)
to
the
NBIA's
data buffer (to L2).
Then, if internal control bit DMA BUF
BSY is not set, it writes the command/address into the
transaction
buffer.
There are two transaction buffer locations reserved for a
DMA read/write command/address, one for each VAXBI (NBIB).
After

the

data

bus

and

also

read.

until
A LS N he ok

the
e £
SN

command/address
control
asserts
the

DMA

REQO

operation

write

(either

data

DMA REQ n signal
read/write
memory.

written

1)
0

DMA

taken
Ty N2

the

transaction

buffer,

the

sets

its

DMA

control

bit

write,

from
\F2LL

the

de A

the

BIn

BUF

BSY

operation

DMA

REQ

NRIR,
%L A

DMA

not

asserted

{(Refeor
S

Section
LA

L QI S N S

3.4.2.)
The

the

data

bus

used to initiate
the
The
now set DMA BUF BSY

control

from writing

transaction

buffer,

and

responds

the

transaction

NMI

another

asserting

3.4.1.3

Command/Address

initiate

the

NMI

translated from TTL to ECL and
then
causes
the
DSEQ MCA to

read

the

DMA

command/address

asserted,

from

transfer
the

I/0 ARB),

(NMI

local

from

DMA

the

prevents

CPU

PAR MUX

function

the

read/write

sequencer

assert

read

BUSY

any

first.

Command/Address

the

may
the

REQ

SEL

code

(READ

DMA

C/A).

read

from

the

memory

That

Cycle)

signal

transaction

1is,

first

clock.
BUSY, and

buffer.

It
to

This

engaged in an NMI transfer
the other NBIB) or
a
CPU

receive

sequencer

transaction

started),

NBAP

MCA

and

DMA

request

the

(TRANSMIT C/A),
The

read

the

NBFD

VAXBI

requiring

and

function

REQ

causes

NMI

(assert

assert
then

causes

following:

The

address

the

NMI

The

translated

from

the

data

the

buffer's
VAXBI

transaction

EBus
(to

receive
NMI)

buffer

[

the

{(a

transmit

DC022

EBUS

beginning

the

until

synchronized to the ECL
assert DMA REQ and EBUS

MCA

request,

write transaction, or until
previous read transaction.

will
be
delayed if the NBIA is already
due to another DMA request (initiated by
read/write operation.
Once

DMA

initiated

transaction,

transaction
to
control bit prevents

command/address

another

until memory acknowledges a previous
returns the read data requested by a

NMI

buffer

loaded

1in

latches.

read/write
latched

function
the

NBIM

read

MCA.

The

DSEQ

MCA

then

transaction
another

DC022

function
The

reads

the

first

and

the

transmit

buffer,
read

(READ

function

DC022

following

then occurs
transaction
buffer

the

(READ

DATA)

and

while
1is

DMA

data

DMA

DATA)

PAR MUX

the

code

that

into

the

NBIM

the

asserts
NBI

read

(TRANSMIT

C/A).

was

NMI

again

plus

SEL

address

clocked

location

sequencer

just

data

read

from

buffer’s

NMI
latches (from its
EBus
receive
1latches),
and
the
NMI
read/write
function that was just read from the transaction buffer

transmit
is

gated

and

the

latched
1.

The

PAR

the

data

MUX

SEL

NBFD

MCA.

the

transaction
now

holds

first

buffer

both

latches)

code

the

well

from

DMA

data

into

the

DMA

address

the

MCA

location
NMI

DMA

data

The

mask

the

This

write,

NMI

function,

in)

the

NBFD MCA.

occurs
its

the

only

DMA

read,

location

the

(of

now

data

real
wins

gated

latched

the

read

the

Then,

(and

first

the

For

and

buffer.

BUS

address

DMA

possibly

transaction

operation.
I/0

transaction

request.

transaction

overall

1latched

For

buffer

Nothing

now

asserts

NMI

following:

The

NMI

data

the

NMI

ADDRESS/DATA

The

NBFD

buffer

MCA

transmits

the

NMI

the

FUNC

(VAXBI)

making

derived

from

the

BI1

DSEQ

MCA

when

There

also

DMA

the

read/write

holding

the

request.

PROGRESS,
a

PROGRESS

X 3-71

ID
on
the
NMI
from the hard-wired

NBIA)

MCA

DMA

function

commander's

generated

NPAR

receives

DMA

lines.

NBIM MCA transmits
the
ID/MASK
lines.
The
1ID is
I/0 SEL signal
(identifies
signal

the

lines.

The

XACTION

holding

the

receive

same

write

NMI.

transmit

EBus

latches

been

the

buffer

location

the

from

The

NMI

its

ENBUS)

the

1location

contents

the

read

from

data

has

data
DMA

course)

write

NBIA

the

holding
3.

causing

which

DMA

has

ENABLE

loaded

both

the

and

DMA

first

reads

until

the

longword
it

for

function

occurs

any)

MCA.

the

reading

buffer

(if

NBIM

loaded

its

(in

latches).
2.

the

buffer.

(in

data

(over

DMA

that

and

This
which

last
is

request

signal

DSEQ

BIl

the

NBIB

identifies

for

signal

asserted
from

VAXBIO.

is
the

VAXBIL.

The transmit sequencer in the NBAP MCA asserts I/O HOLD on
the operation is a DMA write, and it asserts
if
NMI
the
together
signal,
The NPAR MCA uses this last
C/A XMITD.
the DMA IN PROGRESS signal asserted by the DSEQ MCA,
with
signal
DUE
CONF
(Again, there is a
to assert CONF DUE.
for each VAXBI.) Its main function is
response logic in the NBAP MCA.
This

confirmation

the

command/address

sent

just

memory

transmitted

to condition the DMA
1logic
responds
to

after it receives the

the NBIA.

After the DMA REQ signal is asserted by the DSEQ MCA and before the
NMI is won, it is possible for the DMA request to be aborted by the
the
(The reading of the command/address and/or
receive sequencer.
buffer
transaction
the
from
location
data
DMA
first
the
of
contents

a
from
data
read
return
1if
occurs
may also be aborted.) This
To
memory.
the
by
NBIA
the
to
sent
being
is
request
DMA
previous
an ABORT
asserts
sequencer
receive
the
abort the DMA request,
The DSEQ
sequencer.
transmit
the
in
ARB
that deasserts I/0
signal

(assert DMA REQ again)
MCA will then reinitiate the DMA request
in the transaction
loaded
been
has
data
DMA return read
the
when
in
described
1is
data
read
return
the
The loading of
buffer.
Section

3.4.2

3.4.3.

Write

Data Transfer

write
of
transfer
the
Like the transfer of the command/address,
three
of
consists
NMI
the
to
data (and mask, if any) from the VAXBI
for
However,
3-17.)
Figure
to
(Refer
basic "~ operations.
(for
times
two
repeated
transfers, each operation is
multilongword
quadword writes) or four times (for octaword writes).
1.

BIIC
its
by
received
The NBIB transfers the write data
buffer and then immediately into its
data
BCI
its
into
data

bus

buffer.

The NBIA reads the write data from its transaction
buffer
into its NMI data buffer and then transmits it on the NMI.

~J
)

The NBIA transfers the write data held in the NBIB's
bus buffer into its own transaction buffer.

data

3.4.2.1
Write Data to BCI Data Buffer and Data Bus Buffer —-- After
the
command/address of a VAXBI write transaction has been received
by the BIIC and moved to L6 in the
NBIB's
data
bus
buffer,
the
slave
port
sequencer moves from the WRITE WAIT state to the WRITE
DATA state.
In then remains in
this
state
for
as
1long
as
1is
necessary
to
move
each
longword
of write data (and write mask)
received by the BIIC to the data bus buffer.
The

sequencer's WRITE

DATA

data
(and
its
mask
assert MY CLE, I TO F

state

bits)
RD EN,

by
and

transfers

each

longword

causing the data buffer
a data bus buffer latch

write

control
enable.

The MY CLE signal first allows the received data
and
mask
to
be
clocked
into
the
BCI data buffer (L4 and L6).
The I to F signal
and the latch enable then cause the data
and
mask
to
be
1loaded
almost
immediately into the data bus buffer.
During the transfer,
the mask bits are passed through I to F logic unmodified
with
one
exception.
Because there is no unmasked NMI quadword transaction,
the I to F logic sets the mask bits to
all
ones
when
the
VAXBI
quadword
transaction
is
an
ordinary
write
(WR
or
WCI).
The
transaction type is known because the VAXBI command
and
the
data
length
were
stored (in the BUF I and BUF D<31:30> latches) during
the command/address transfer.
The

latches

that

are

longword

data

loaded

(the

loaded

being

only

latch

the

data

moved.

The

loaded

bus

buffer

first

during

depend

longword

which

and mask

longword

are

transfer).

If
there
1is
a
second longword (a quadword transfer), it
mask are loaded in L1l.
Similarly, if there is a third
and
(an octaword transfer), they are loaded in L2 and L6.

and its
£fourth

The last longword and mask can be loaded in L6
(which
also
holds
the
command/address) because the command/address has been taken by
the NBIA by this time.
This is true
even
during
backed
wup
DMA
write operations when the NBIA is not taking the write data shortly
after it is loaded in the NBIB latches.
That is, even
though
the
first
operation
has not completed (data not written into memory),

the NBIA still takes
when
it
is
first
operation

ends

before

the command/address
1loaded
in
L6.
It
taking

the

data

X 3-73

for

for the
second
then waits until
the

second.

operation
the first

LOAD N
DATA

LONGWORDS OF WRITE

DATA

DATA BUS

BUFFER

(N=1/2/4)

BUS

NBIA 4~—|~» NBIB

WRITE

EME

(NOT

PARITY

)

BCI DATA BUFFER
DATA

[ |_l4(MASK)

USeD) 4Pt

I——_—'

WRITE DATA

L16
MASTER
MasT

SEQ

LNGTH

]

CNTR

4 cMomAsK

slv Busy &
CNT = DON

CNF=ACK/STALL

I TO F |g{MASK)
<

SPS=2

BUF D<31:30>

2IPZE]

C) L1z

WRITE DATA

1=MASK

FTOI

L10

BlIC

(MASK)

LENGTH CNT

LW
2

‘<

PO
<

/—

BCI

VAXBI

DATA BUS BUFFER

Je—

sPs-2,6,7.54—]

BUF D<31:30>,<2>

gave
PORT

SEQ

FS=ACK/STALL

DATA BUF

cTL

BUF

LTOFPRDEN
MY CLE

¢——— LENGTH

.,
oNT

(81

GMD)
INTR
LOGIC

LENGTH CNT
SLAVE

l4—— 5Ps-2

DMA DONE

SYNC

PORT

SEQ STATES

DEeENONAEWDN-O

L8/L10/L12/L6|LTCH

DMA DONE

IDLE
WHT CG/A
WHT DATA
MSTR
XCTN

WAIT

PEND
CMPLT

SCLD 10

Figure

3-17

VAXBI

NMI

Write

Data

Transfer

(Sheet

©,

N NMI WRITE

©,

LOAD N LONGWCRDS OF \A?F;‘ITE‘I /g:}I)A IN TRANSLATION BUFFER

DATA CYCLES

(N ~1/214)

ECL 4—|—P TTL

ND<3:0>

ADDRESS/DATA

WRITE DATA

DCO22 TRANSACTION BUFFER

WRITE DATA
EBUS

l¢—NBIA DATA/FUNG PAR ERR

K WRITE OATA

PME

l¢— RD FUNC.5

NMI_ENAEL

|
|

DATA PARITY

BUS 0 DATA BUFFER

¢—XMIT_BYTE PAR

l¢—0C FUNC-2

DMA

DATAX

NPAR

I WRITE DATA l| MF| | PD |[ PM Fi

PAR MUX SEL=5

ME (MASK

NMI

PMF

{i [:‘ I|

FUNC (MASK)

v2lRD

RD ADR=01/02/43/04

ADR=01/02/03/04

L p

L2|LTCH

EN|

DATA BUS BUFFER

le——F0 .. .__J_ ]

—

IO/NASK = MASK

paTAlBUS

K ::::W.EE&TL__

FUNC PAR

RD FUNG-=5

EBUS AGV PAR FUNG

NBIA <—|—> NBIB

DATA PAR

Do FUNG-2

NBIM

FUNG ID PARITY

SL-€ X

78US

|
|

BUS 0

peng

0P DMAO BUF BSY

L8/L10/L12/1.6 RD EN

4— PAR MUX SEL=%

l¢— DC FUNC-2

». NMI ENABLE

019022

cTL
(TTL)

NBFD

FUNC-WRT_DATA

NMi ENABLE

DC FUNC=2——

ECL<—-:~—-> TTL
SYNC/XLATE

NEAP

1/D_HOLD

NBCT

DC FUNG-2

RD FUNC-S

BIC VA

)

DONE

INITIATES NMI G/A CYCLE.
REFER TO FIGURE

C/A TRANSFER.

NBI READ FUNCTION

NMI ENABLE

GNF-ACK

DC022 READ FUNG

4 | RD DG VECT

cix

E‘EI?NciE!?!OS

DC DATA

6 | RD NBiI VECT

_REQ DONE

SHOWING

NoP

RD DMA C/A

2 | RD DMA

DATA

3 | RD cPU DATA

DMA DONE]

SYNC

DMA DONE ©

0
1 | Ao csRo

BUF

|
DMA_FEQ 0

-—% PAR MUX SEL=5

1/0 BUS EN

DATA
CTL

W%TE
DATA

PAR_MUX SEL

0 | LOCAL RD
1

| BI

READ

3 | xMmca
SCLD-12

VAXBI

NMI

Write

Data Transfer

(Sheet

2 of

last
3.4.2.2 End of VAXBI Transaction (and Retries) -- When the
output
counter
longword of write data has been transferred, length
(The transaction length count was loaded
CNT = DONE is asserted.

the

1length counter logic during the command/address transfer.)

The slave port sequencer then advances to the WRITE STALL state
a STALL code on the RS
(asserts
transaction
stalling the VAXBI

lines to the
The
data.
NBIB) which,
slave port

BIIC) until the NBIA indicates it has taken the write
NBIA does this by asserting REQ DONE (DMA DONE in the
after synchronization to the NBIB clock, causes the
sequencer to advance to the WRITE COMPLETE state, then

IDLE state.
to the TRANSACTION COMPLETE state, and finally to the
on the RS
asserted
is
code
ACK
an
states,
two
first
the
During
CNF
VAXBI
the
(on
e
acknowledg
to
it
causing
BIIC
the
to
lines
port
slave
The
ly.
successful
completed
n
transactio
the
that
lines)

sequencer is then free
transaction

from the VAXBI.

another

DMA

write

(or

read)

As can be seen, the VAXBI write transaction is normally ended when
(The data has not yet been
the NBIA has taken the write data.
control bit called FORCE
c
diagnosti
a
However,
written in memory.)
that holds the NBIB's
CSRO)
(in
NBIA
the
in
set
DMA BUSY can be
forces the BIIC
and
state
STALL
WRITE
the
in
slave port sequencer
e stall
consecutiv
128
(after
timeout
stall
a
generate
to
node
the
NOACKs
BIIC
the
occurs,
responses). When the timeout
it
and
n),
transactio
VAXBI
the
originating the transaction (ending
asserts an STO event code that causes the slave port sequencer
go the IDLE state ending the DMA write operation in the NBIB.

3.4.2.3 Write Data to NBIA's Transaction Buffer -- After an NBIA's
data bus control has written the command/address for a DMA write
it transfers all
operation into the NBIA's transaction buffer,
in the transaction
it
writes
also
and
write data from the NBIB
L4 in the NBIA's
or
L2
either
(to
d
buffer. The data is transferre
one longword
buffer
n
transactio
the
into
and written
data buffer)

its own length counter,
has
taken during the
function
read/write
conditioned by the NMI
the transfer.) The
of
end
the
indicate
to
command/address transfer,
initiates an
which
signal,
REQ
DMA
a
asserts
then
control
data bus
3.4.1.
Section
in
y
previousl
discussed
as
cycle
ddress
NMI command/a
VAXBI
the
ends
that
signal
DONE
REQ
the
asserts
also
control
The

at a time.

(The data bus

transaction

the

control

NBIB.

X 3-76

3.4.2.4

Write

Data

NMI

Cycles)

-- After

the

DSEQ

MCA

(NMI
reads

Write

Data
Cycle
command/address from

the

transaction

or
the

buffer, it also reads the first longword of write
data
from
the
transaction
buffer
as
described previously in Section
3.4.1.
Then, when the
NBIA
wins
the
NMI,
the
command/address
followed
by
the
first
Jlongword of write data (and its mask) are
transmitted on the NMI while the DSEQ MCA reads the next
DMA
data
location

the

transaction

single

NMI

command/address
by

cycle), and
an ACK code on

asserting

cycle.
If

the

NMI

transaction

1is

sequencer

the

NBAP

MCA

DMA

DATA)

and

NBI

read

did

for

the

first

the

write

data

ENABLE

still

NMI

the

DMA

second
data

write

transaction,

the

transactions,

sequencer

during

last

write

data

When

the

(The

DMA

and

bit

operation.
to

data

write
in

write

longword write
following

write,

DC022
DC022

data.

the

function

DATA),

just

before,

longword)

loaded

the

NBIM

loaded

and

mask

data
the

HOLD

are

cycle)

also

while

transaction

For
to

ends.

command/address

cycle)

the

NMI
NMI

transmitted

DSEQ

This

two more

MCA

write

During

(asserted

causes

With

the

NMI

generate

line

(READ
as

this

MCA.

buffer.

transmit

read

repeats

I/O

(READ

transaction

acknowledges

cycle),

the

signal

asserted
request.)
This

synchronization

control

the

data

signals.

the

ends

the

deserted

octaword
NMI

any

reads

write
the

NMI

transmit
during

the

cycle.

memory

original

second

operation

write

asserts

transaction.

before

ends

cycle

multilongword

function

location

cycles

write

again

mask

NMI

quadword

data

first

the
its

asserted,

the

NMI

and

This

data

the
the memory acknowledges the transaction
the NMI CNF lines during the
next
bus

longword

(now

buffer,

buffer.
write

the

With
another

the

TTL

associated

DMA
DMA

BUF

BSY

request

NMI

NBCT

write

MCA

transaction

asserts

depends
on
signal, after
clock,

then

the
ECL

clears

data

bus control
cleared, the data
from

X 3-77

the

one

NBIB.

(after

two

DMA

the

DONE

NBIB
making
the
to TTL translation
the

DMA

BUF

BSY

ending the DMA write
bus control is
free

3.4.2.5

NMI

Write

Transaction

Retries

(NO

ACCESS/MEMORY

BUSY/NOACK) -- If the NBIA won the NMI and has started an NMI write
transaction, and MEMORY BUSY is asserted by
memory
(on
the
NMI)
during
the
command/address
cycle
or first write data cycle, the
transaction is retried.
The retry is done by the
NBAP's
transmit
sequencer,

which

checks

the MEMORY BUSY signal

after

it generates

the read functions and other signals that control the
transmission
of the command/address and first longword of write data on the NMI.
If MEMORY BUSY is asserted, the sequencer stops the transmitting of
write data (if there is more to transmit), allows the I/O HOLD line
to be deserted (I/O BUS EN is then deserted by the
bus
arbitrator
in the CPU), and then it requests the bus again and reinitiates the
transaction just as when it first received the DMA REQ signal
from
the
DSEQ
MCA.
The transaction then completes as it does normally
unless

ancther

retry

reguired.

An NMI write transaction will also be retried if the transaction 1is
not acknowledged by memory (usually because of a nonexistent memory
address).
In this case, the command/address and all write data are
transmitted
on
the NMI as is done normally.
However, when an ACK
response is not received by the NBIA, the NBCT
MCA
asserts
RETRY
(BIO
or
BIl)
DMA REQ which causes the DESQO MCA to assert DMA REQ
again.
The
transmit
sequencer
then
reinitiates
the
NMI
transaction.

3.4.2.6
DMA Errors -- A DMA write operation will be terminated
if
the NBIA cannot win the NMI (after a timeout), or if it is retrying
the NMI transaction and the retry counter
times
out.
When
this
occurs, DMA ERROR (there is a signal for each VAXBI) is asserted by
the NBCT MCA.
This signal, like DMA DONE, then clears DMA BUF
BSY
in
the associated data bus control ending the DMA write operation.
DMA ERROR

asserted

A bus

access

A retry

the

timeout

following:

(Section

3.4.5)

X 3-78

3.4.3
The

Return

transfer

VAXBI

Read
of

Data

return

shown

command/address

{and

The

NBIA

loads

the

into

its

DC022

transaction

The

NBIA

reads

the

and

read

interconnecting

The

NBIB

reads

into

the

BIIC

similar

repeated

for

repeated

transfers

but

the

its
and

the

four

read

buffer
on

third

However,

when

repeated

four

the

VAXBI

and

second

the

twice

3.4.3.1

Return
the

acknowledges

the

data

device
are

When

the

NBIA

the

NBCT

bus

cycle

When

the

RETURN

The

DATA

READ

indicate
by

the

four

case,

read

data

read

operation

ACK

(octaword
times
aligned.

step

has

data

cycles

but

code

winning

When

the

ACK

code

the

NBIA

transmission

sending
longword

the

NMI

ID/MASK
on

the

all

X 3-79

during

data

code

for

first
NMT

memory

not

from

the

bus)

transmits

requesting

data

transfers

only

latched

during

the

1in

second

command/address.

and

read

identify

sent

good

the

data,
of

CONTINUE

sent

code

memory
it

generates

occurs

first

the

read

from memory,

read

these

always

the

been

also

data/status

between

and

is
each

four

third

read

bus

VAXBI

transaction,

valid

(Two

hexword,

the

READ

data

NBIA).

acknowlegdment

commander's

the
memory).

(over

transfers,

transactions.)

starts

the

stalled

asserting

consecutive

receives

code

NMI

the

transfer

the

NMI

taken

quadword

Buffer

NMI

(after

CONTINUE

for

and

transmits

DATA

to Transaction

data

The

the

quickly

each

are

the

read

memory

its

octaword

transmits

when

following

VAXBI

unaligned,

only

Then,

MCA.

lines,

when

octaword

basic

buffer

repeated

must

Data

transaction

bus

transfers

transaction

from

steps

address

longword

the

(The

this

required

RETURN

Read

three

quadword

two

twice

BIIC

the

opposite

cycles).

requests

(in

cycle,

VAXBI

read

the

interlocked.)
it

the

command/address

1lines.

array,

but

(the

VAXBI

repeated

from

where

For

VAXBI
first

quadword

times

receives
CNF

only

the

its

data

transfers,

transfers.

For

NMI),

from

NBIB's

data/status

data

data/mask

times.

the

bus).

transmitted

write

NMI

transfer

received

data/status

data

BCI

multilongword

the
the

buffer.

cycle).
Also,

from

data/status

read

1loads

the

buffer

status)

3-18.

data/mask
information
in
VAXBI to the NMI), it consists

the

buffer

data

Figure

write

direction
(from
operations.
1.

Transfer
read

first

bad

NMI

lines,

the

others

each
the

and
FUNC

longword

(if

any).

(cannot

read

data

ADDRESS/DATA

either
lines.

a
The

data.

Both

codes

corrected

N NMI READ DATA CYCLES (LOAD N LONGWORDS OF READ DATA IN TRANSACTION BUFFER)

LOAD N LONGWORDS OF READ DATA IN NBIB
(N=1/4)

]

PMF

DATAX I

M— WR FUNC«5
NPAR

DATA PARITY
FUNC 1D

DATA PAR

PARITY

DATA

MF (STATUS)

|
I
I
I
I
|
|
I
I
|
I

| __FUNC PAR
»

EBUS XMIT PAR FUNG

FUNC (STATUS) »

NBIM

NMIL

ACV ID/IMASK

PAR

WR ADR=-01/02/03/04

FUNC (STATUS)

ID/MASK=D

|LTCH

0
BUS

RD| ADR=01/02/03/04

CTL

DSEQ
MY 100

pco22
CTL

LE/L7/LO/LTY

0—P DMAO BUF

(TTL)

asy

NBFD

ACV _FUNC PAR

FUNC=RTN DATA/CONT
-

ON BUS
RAD

—% WAT FUNC-5

BOEL BIO OR
———

WR FUNC=5——

ECL & I—P TTL
|

8YNC/XLATE

REQ DONE

NBI WRITE FUNCTION
L-XNTYL
CY Ly

8-t X

WA FUNC-5 ——»

PME

NOP
WHT CSRO

WHT CSR1
SAVE 1D
WAT CPU C/A
WHT DMA DATA
WRT CPU IDENT
WHT CPU DATA
CPU CMD PEND

B10 DMA DONE

]

RCY_BYTE PAR

READ DATA

)

DATA PAR FLT/CNTRL PAR FLT

TBUS

READ DATA

LTCH

READ DATA

OEIDE
I E]

LTCH

EBUS

ROV f-—W

LTCH

I
|
|
I
I
I

-~ O

XMIT

DATA BUS BUFFER
-

AEAD DATA

DATA I aus

BUS 0 DATA BUFFE ]

ADDRESS/DATA

DC022 TRANSACTION BUFFER

NBIA (—l—b NBIB

NL<3:4>

ECL4—
P TTL

e Rt

(N=1/4)

DATA

BUF

CTL

I[DMA DONE
|
I
!

DiMA DONE

|
|

CNF-ACK

8CLD-T

Figure

3-18

NMI

VAXBI

Return Read Data Transfer

(Sheet

LOAD N LONGWCRDS OF R%QD D;}T/'A;/IaN) BIIC

VAXBI

READ DATA CYCLES)

DATA BJS

T
D8

@[]
[]
@[]
[]
@[]
L]

READ DATA
7

BCl

DATA BUFFER

8CI

L13

READ DATA

BlIC

READ DATA

PD
e

PARITY

GEN/CHK

XLATED

| (STATUS

L1s

NBIA CSR)

F 1o

MASTER
PORT
SEQ

XLATED |
(STATUS)

LNGTH

CNTR
|

]

BB PE

(TO

I_(STATUS)

siveusy

ONT = DONE

SDE
CNF=STALL/ACK

TOF

SPS=9,B

[]

SPS=9,B 44—
BUF D<31:30>,<2>

SLAVE
PORT
SEQ

RS=ACK/STALL
T
e

—

’

LS/L74L9/111

RD EN

L13/L15_

INTR
LOGIC

WHRT EN

SLAVE POR
SEQ STATES

DATA BUF
CTL

TOONDPREWDO=O

8-¢ x

DATA BUS BUFFER

VAXBI

NB|A<—|—> NBIB

[¢—— SPS=9,B

DMA DONE

SYNC DMA DONE

SYNC

IDLE
WRT C/A
WRT DATA

WRT WAIT
MSTR PEND
XCTN CMPLT

WHT STALL

WRT CMPLT

RETRY

RD WAIT
RD RDY

SCLD-s

Figure

3-18

NMI

VAXBI

Return

Read

Data

Transfer

(Sheet

When

the

made

the

signal
an

for

RDEL

will

DMA

TYPE

the

ccde

RDEO

VAXBI

data

VAXBIO

from

both

for

either,

With

both

the

signal

previously
The

write
1.

signal

function
the

the

data
data

NBIM

This

ends

its

status)

the

operations

command/address

read

data

RDEO

ed on
transfer
t'l..

write

and

the

function

ABORT.

operation

(The

described

(over

transmit

transaction

the

received

(RETURN

lines

buffer.

DATA

gated

this

from

case)

the

NBFD

the

NEBUS)

and

transmitted

MCA

then

write

the

read

data

and

status)

into

the

causes

the

function

(the

data

with

BI1l)

DATA

(BI0O

buffer.

signal,
NBCT

for

buffer.

read

assert
the

NMI

MCA

DSEQ

causes

the

FUNC

BUS

turn,

BUS

C/A

RDEL

signals

asserting

buffer
to

code

transaction

MCA

recei

DMA write

the

DSEQ

RRD

function

the

RDEL

e
s oee

the

requested

internal

and

from
is

following:

read

MCA

Causes

asserts
pending

NMI

the

state

asserted

3.4.1.)

does

transaction

RRD

Section

received

The

also

the

are

read

the

function

signal

there

send

octaword)

there

DMA

data,

derived

can

Firmad
3

starts

that

read

corresponding

advancing

received

DATA

signal

that

getting

VAXBI

This
it

the
(there

expecting

(Again,

two

is,

MNMAMA

RETURN

aborts

Causes

and

DTTIDAN

sequencer

DATA).

longword
2.

and

have

before

71
with

Causes

can

longword

reason

VAXBI1

data

The

MCA.

and

receive

DMA

NBIM

That

lines,
(WRITE

NBCT

transfer,

NBIA

expected,

the

specifies

asserts

the

time.

and

ABORT

the

VAXBI.)

the

also

MCA

same

asserted,

read

each

that

return

Also,

(read

for

which

NBIM

command/address

progress

the

ID,

the

asserted

transmitted

signal

each

NBIA's

each VAXBI).

already

during

the

request,

together
a

(BIO

MCA

assert

single

longword

signal,
RCVD

BI1)

signal.
DMA

This,

DONE.

return read data (and
data is locaded in the
first of the four transaction buffer
locations
reserved
for
DMA
data (for that VAXBI).
If an octaword is returned from memory, the
receive sequencer continues to generate the
same
write
function,

causing

the

transaction

remaining

transaction buffer as each
code
1in
the
transaction
CONTINUE code.)

three

buffer.

longwords

The

1loaded

the

is received on
the
NMI.
(The
status
buffer with these longwords is the READ

3.4.3.2
NMI

NMI

write

MEMORY

Read

Transaction

transaction,

BUSY

the

asserted

Retries

NBIA

during

(MEMORY

retries

the

BUSY)

NMI

-- As

read

command/address

for

transaction
cycle.

this,
the
transmit
sequencer simply requests the NMI again.
The
command/address has already been read from the transaction buffer.

3.4.3.3

Return

Read

Data

asserted

NBCT

MCA

when

NMI,

and

gated

the

translated
to

the

control,

which

control

bit

four

longwords

the

NBIB

TTL,

set,

then

clears

DMA

return

read

data

the

CPU

into

Also,

counter

the

command/address

the

when

transfer)

BSY
data

data

bus

transferring

one

longword

transfer,

this

For

octaword

transfer,

the

NBIB,

the

other

three

longwords

loaded

NBIB.

3.4.3.4
DATA

did

the

Return

CYCLE)

during

currently

asserting

the

status)

DMA

Data

REQ

VAXBI

read

the

control

first

NBIB's

data

The

bus

cycle)
the

by asserting

only

VAXBI

data

cycle

transaction

sequencer
transfer

L7,

L9,

stays

an ACK code on
for

the

rest

and

L1)

read

VAXBI

the

READY

read

BIIC

X 3-83

and

the

has

been

data

(and

DONE.

the

SDE

signal

the

BIIC

lines.

the

The

VAXBI

longword
for

VAXBI.

enable

levels

(and

its

BCI

data

its

causes

VAXBI

read

three
the

the

data

This

the

transaction.

the

1lines.

transaction,
state

BIIC

latched and
sequencer
causes
(a

the RIIC's RS

the

causes

This

then

where

sequencer,

data

L5)

the

and

READ

DONE

with

state.
read

when

(VAXBI
DMA

NBIA.

buffer

port

assert

its

For

the

ends

BIIC
SYNC

return

the

data

REQ

slave

data/status

and

NBIB,
during

operation

(from

octaword

READ

read

the

buffer

BIIC's

transmitted

the

transaction

longword

the

bus

(loaded

READY

from

into

asserts

READ

CPU

1longword

transaction

The

data

read

Buffer

DONE

time,

operaticn

read

one

code)

NBIB's

asserts

the

operation.

buffer

read

the

from

all

bus
BSY

(this

data

The
BUF

for

read

first

return

from

BCI

advances

L3/LS).

NBIB,

when

DMA

the

bus.

control

on the VAXBI's data and
data/status
to be transmitted

the

(in

Data

the

status

the

clock,

1).
DMA

transfers

buffer

signal,
from

TTL

its

control

bus

read

the

then

move

from

are

write

data

ends

the

stalling

SDE,

buffer
(to
data/status
transmitted

DMA

NBIB's

necessary

Read

data

transfer,

passed

DMA write

determines

status)

and

with

transferred.

After

(0
its

quickly

data

the

with

status)

NBIA's

control

BUF

received

bus

(each

NBIA's

1is

state

data/mask

its

DONE

data

synchronized

wait

write

(and

before

buffer.

DMA

read

interconnecting

data

buffer

The

data

read

latches)

been

over

transaction

ECL

return

corresponding

has

command/address
return

from

NBIB

slave

port

bus

cycles

data

bus

buffer

buffer
bus
data
For VAXBI read quadword transactions, the NBIB's
from
read
is
octaword
(an
data
read
of
octaword
an
contains
also

memory as previously discussed),

but only two VAXBI data cycles are

For an aligned quadword read,

generated.

the slave port sequencer

stays in the READ READY state long enough to transfer the first two
longwords of read data in the data bus buffer (in L5 and L7) to the
This is done in two consecutive VAXBI data cycles.
BIIC and VAXBI.
quadword read, the first and fourth longword of
unaligned
an
For
on
bus buffer (in L5 and L1) are transmitted
data
the
in
data
read
(Refer again to Figure 3-14.,) To do this, and similar
VAXBI.
the
to an octaword transfer, the slave port sequencer stays in the READ

long enough to transfer all four longwords to the BCI
state
READY
to
1lines
it asserts a STALL code on the RS
However,
data buffer.
two
only
result,
a
As
longwords.
third
and
second
the
the BIIC for

VAXBI data cycles are generated with
between

the

first

and

two

stall

cycles

occurring

second.

During the internal transfer of return read data (from the data bus
status code for the
the NMI
data buffer),
to the BCI
buffer
VAXBI status
corresponding
a
to
translated
is
longword of read data
NMI RETURN
an
either
is,
That
logic.
I
to
F
NBIB's
the
by
code
causes
good
is
data
the
indicates
that
code
DATA or READ CONTINUE
the
on
transmitted
be
to
code
Cache)
Don't
(Read Data
an RDDC
data
the
indicates
code
CONTINUE
READ
or
DATA
RETURN
the
If
VAXBI.
(Read Data Substitute Don't Cache) code is
an RDSDC
bad,
is
transmitted.

of
End of VAXBI Transaction —-- During the last data cycle
3.4.3.5
data
the
octaword),
or
quadword,
(longword,
transaction
the VAXBI
transfer
command/address
the
during
length counter logic loaded
to the
returns
then
sequencer
port
slave
The
CNT=DONE.
asserts
IDLE state ending the DMA read operation in the NBIB.

After the node originating the VAXBI read transaction takes all the
data from the NBIB, it asserts an ACK code on the VAXBI's CNF lines
error
for two bus cycles unless it detects a transaction execution
not
is
code
ACK
this
If
error).
parity
VAXBI
a
example,
(for
and
bit
error
internal
an
sets
it
received by the NBIB's BIIC,
returned
data
read
the
When
request.
VAXBI interrupt
a
generates
to the node originating the VAXBI read transaction is bad (an RDSDC
the VAXBI's I lines), the
on
NBIB
the
by
transmitted
1is
code
originating node sets
interrupt

internal

error

bit

and

generates

request.

the
As for a VAXBI write transaction during a DMA write operation,
VAXBI
a
prevents
CSR0O)
(in
BUSY
DMA
FORCE
bit
control
diagnostic
read transaction from ending normally by forcing a stall timeout by
Again, when the timeout occurs, the BIIC NOACKs the node
the BIIC.
and
originating the transaction (which ends the VAXBI transaction)
asserts

the

STO event code that causes the slave port sequencer to

IDLE

state.

3.4.3.6
DMA
Errors
(VAXBI
Transaction
Retries) -- A
DMA
read
operation
is
terminated,
and
then
caused to be retried, if the
command/address cannot be immediately sent
to
memory,
or
1if
an
error
1is
detected
when return read data is received from memory.
DMA ERROR, asserted by the NBCT MCA in the NBIA (there is a
signal
for
eac
VAXBI),
first
<clears DMA BUF BSY in the associated bus
control.
(DMA DONE normally does this.) Then, DMA ERROR causes the
slave
port sequencer in the associated NBIB to assert a RETRY code
on the RS lines to the BIIC and go to the IDLE state.
DMA ERROR is
asserted by the following:
1.

bus

access

timeout

retry

response

interlocked

NMI

read

NMI

data parity

timeout

(Section

3.4.5)

from memory

response

sequence

from memory

fault

X 3-85

(Section

3.4.6)

3.4.4)

3.4.4

Parity

Generation

and

Checking

3.4.4.1
Command/Address and Write Data/Mask
Parity -- Parity
for
DMA
command/address
and
write
data/mask
information
(like CPU
return read data/mask information) is checked when the
information
is
received
by
the
information is loaded
checked
and
read from the
If

the

it
(All

~amraarmA

BIIC

could

faAdAAvaAaces
QUUL

error

parity

bit

interrupt

~rr~1 Am

TOO

BIIC, regenerated by the NBIB when the
NBIB's
data
bus
buffer,
and
then

again by the NBIA when
buffer and transmitted

detects

internal

nodes

CUIILIIAIIU/

the

regenerated
transaction

NBIB's

sets

NBIB's
in the

CYLLITOe

command/address

and

AT e~

1Oy

DMA

error

and

for

the

generates
they

all

ATRDTD
! o

LIIT

INNDJLD

read/write

[CW g

UUUCTO

operation

request.

parity

AAans

Dl1L\O

command/address,

interrupt

check

DTTN

the information
on the NMI.

during
~A

l1ivu

LCDPUHU

not

[
)

started

in
the
NBI.,
If the BIIC detects a parity error when taking write
data/mask information, it also sets an error bit and
generates
an
interrupt
request.
(Only the nodes taking and transmitting write
data check its parity.)
Write
data/mask
information
having
bad
parity

1is

accepted

The

NBIB

for

transmission

regenerates

The

parity
data

with

both

data

and

control

the

are

mask
even

the
the

data

the

data

bits

bit

bit)

VAXBI

address
is

all

the

gated

the

command

are

and

bits

(PD

PF)

the

function

data

the

(the

and,

NBIB's

write

through

buffer

bus

mask

one

buffer

along

with

the

write
bus

buffer

logic.

VAXBI

for

even

associated

logic

and

command

VAXBI

are set to ones), the I to F logic
bit (PMF) for the information and

bus

and

computes

parity

data

memory.

longwords
the

NBIB's

and

gated

bus

NMI

NBIA

parity

and

transferred

PMF

the

dgenerator/checker

memory

parity

follows:

parity

the

write

they

When

the

NBIA

The

translated

the

passed

the

with

loaded

and

NBIB's

when

(along
PMF

BIIC

for

buffer.

the

data

command,

computes
it

gates

parity

bit

(PD).
make

control

during

diagnostic

NBIA.

the

both

bit

and

CSR1l

operations

PMF

odd

(in

the

test

will

Q
o))

NBIB

The

parity

NBIA)

the

bits
set.

parity

the

This

bit

checking

FORCE
is

set

circuits

the

NBIA,

information

when

the

read

command/address

from

the

and

transaction

write

buffer,

data/mask

the

following

occurs:

The NMI
address

parity
2.

The

data buffer generates
parity
for
each
byte
of
or write data, and the NBIM MCA generates an even

bit

NPAR

buffer,

checks
the

for

the

byte

parity

bits

generates

even

parity

for

result
by

NPAR

MCA

uses

data

1line

generate

also

from

the

parity,

control

computation

ID/MASK

lines)

code

bits.
(for
to
an

inverted

odd

(from a

number

VAXBI1

error

NMI

bit

parity.

(for

the

and
on

can
the

the

bits.

FUNC

and

During

write

mask

used

NMI

FUNC

is,

device).

X 3-87

the

and

from

parity

ERR

data

bit

parity

bit

error
sets

CSR1)

control
and

write

bit

from

data

is
the

causing

line

parity

data

cycles.

generate

the

NBIM

cycles,

lines

because

has

cycles,

the

NMI

the

NMI

ID/MASK

NMI

write

number

parity

bit

lines)

has

FUNC

command/address

NBIM

the

even

NBIM

the

MCA

the

transmitted

directly

transmitted

That

CSRO

NMI
bytes

read

the

PAR

(directly)

(PD)

control

(in

parity

transmitted

bit

the

four

asserted.

data

command/address

function

from
all

buffer.,

command/address

uses

mask.

compares

the

NBIA

the

during
if

buffer

valid

read/write

ERR

transaction

transmitted

However,
the

the

DMA

with

and

line

parity
data

the

Also,

request

generates

parity

transaction

PAR

parity

data

MCA

the

DATA

interrupt

during

the

buffer.
NBIM

from

NBIA

corresponding

transmitted

with

the

read

detected,

The

write

using

transaction

NBI

then

generated

function

MCA,

the

(PMF)

NMI

lines

has

from

NBIB

3.4.4.2

read

Return Read Data/Status Parity -- Parity

data/status

(like

information

CPU

for

DMA

return

command/address and CPU

write/mask information) is checked by the NBIA when the information
is taken from the NMI, regenerated by the NBIA when the information
and
checked
then
and
buffer,
transaction
the
1in
written
is
transferred
is
information
the
in the NBIB when
again
regenerated
from the data bus buffer to the BIIC for transmission on the VAXBI.

During NMI

return data cycles,

the NMI

data buffer computes

an even

parity bit for each of the four bytes of return read data received.
the
Similarly, the NBIM and NBFD MCAs compute even parity bits for
the
completes
then
The NPAR MCA
ID and read data status.
received

data and control line parity computation comparing the results with

1If there
and control parity bits received from the NMI.
data
the
PAR
CNTRL
is a parity error, the NPAR MCA asserts DATA PAR FLT or

This,
the corresponding error bit to be set in CSRO.
causing
FLT
the
in turn, causes the NBI's FAULT DETECT line to be asserted on
all
(Because
NMI, which generates an interrupt request in the CPU.
could be
all
cycle,
NMI nexus check NMI parity during every bus

FAULT DETECT lines.) The detection of an NMI
NMI
their
asserting
and
parity error does not stop the NBIA from writing the read data
into the transaction buffer.

status

However,

DATA PAR FLT asserts

a
(BIO or BI1l) DMA ERROR, which causes the associated NBIB to send
VAXBI read
the
originating
node
VAXBI
the
to
response
RETRY
by
transaction (Refer to Section 3.4.3.) DMA ERROR is not asserted
information (and not just the
1line
control
If
FLT.
PAR
CNTRL
be
will
fault
sequence
read
control line parity bit) is bad, a

(If just the control parity bit is
and assert DMA ERROR.
detected
the
taken by
and
NBIB
bad, the read data is transferred to the

VAXBI

node

is done

normally.)

The NPAR MCA also generates both the data and control (even) parity
and PMF, that are loaded in the transaction buffer along
PD
bits,
To generate PD (read
with (in this case) the read data and status.
data parity) and PMF (read status parity), it does the following:
1.
2.

received

PD - Gates

the

transaction

buffer.

NMI

data

parity

bit

the

PMF - Gates the parity bit computed by the NBIM MCA to the
This is not the parity bit for the ID
transaction buffer.
for
It is the parity bit computed
received from the NMI.
status code when the code is passed through the
read
the
NBIM MCA (from the NBFD MCA) to the transaction buffer.

Data

and

return

control
read

buffer

NBIB's

the

control
The

bit

parity

passed

read

(PD)

(in

bit

(PMF)

status
When
for

NBIB

causing

error

PE)

(The

VAXBI.)

The

the

and

BIIC,

the

NBIB
from

the
by

from
the

data

bit

NMI

and

errors.

and

when

the

data

NBIA,
the

the

BIIC

is
in
on

generated

from

and

generates

loaded

NBIB's
NBIA

read

NBI

transmitted

read
NBIB

the
bus

data/status
is
PE sets an error

interrupt
asserted

parity
I

cannot

status

the

are

bit

the

single

not

enabled

the
the

used

(from

transmitted

error

1If

setting

the
is

node

BCI

data
along

(PI)

data

for
The

because
the

detected,

interrupt

X 3-89

taking

request.

VAXBI

the

logic.

code

BIIC

generates

request.

CSR1.

also

bit

signal

NBIB's

and

status.

BIIC

parity

error

transferred

the

NBIA)

the

the
each

buffer,

read
I
to

VAXBI,
an

the

bit

status
parity

F
a

both

data/status
sets

odd

with

parity

the

generate

control

code.

read

NBIB's

the

(PO).

computed

translates

CSR0)

generator/checker

sent

that

<checked
are

the
operation.
(The
BIIC and VAXBI.) However,

force

(FORCE

data

the

can

bit

parity

stop

NBIA

Diagnostics

are

status

data buffer.
If a parity error is detected,
the
generator/checker asserts NBIB PE.
Again, a parity

does not
transferred
to

parity

and

BCI

parity

error

bit

line

data

logic
VAXBI

the

check

internal

3.4.5

Timeouts

There are two timeout counters in the NBIA.

the

One,

bus

access

in the NBAP MCA, asserts BUS ACCESS TMOUT if the
timeout counter
(after requesting the NMI) does not win the bus
sequencer
transmit
This is approximately six
slow clock periods.
system
two
after
The other counter is
rate.
clock
system
normal
the
at
s
millisecond
asserts (BIO or BIl)
It
MCA.
NPAR
the
in
counter
timeout
retry
the
retried by the
be
to
continues
transaction
NMI
the
if
TIMEOUT
slow clock
system
two
of
period
a
(again)
for
sequencer
transmit
started
is
counter
The
milliseconds.
six
y
approximatel
or
periods
the
transmits
and
bus
the
wins
first
sequencer
transmit
the
when
then
can
timeout
A
1).
=
XMTD
C/A
(DMA
memory
to
ess
command/addr
occur because MEMORY BUSY continues to be asserted, or because the
memory continues to return no response Or an interlocked response.

After a bus access or retry timeout occurs,

NBCT

the

MCA

asserts

appropriate error code in its timeout
the
1loads
DMA ERROR and
last
the code is generated from the
timeouts,
For retry
encoder.
or
interlocked,
response,
(no
memory
from
received
type of response
and
CSRO,
1in
1loaded
is
asserted
code
timeout
The
memory busy).
causes an NBI

interrupt request to be generated.

Read Sequence Faults

3.4.6

The receive sequencer in the NBFD MCA asserts
asserts DMA ERROR)

if the following occurs:

SEQ

FLT

(which

not
1is
it
NBIA when
the
to
Return read data is sent
RETURN
a
with
sent
is
data
read
1is,
That
it.
expecting
the
1identifies
(which
1lines
FUNC
DATA code on the NMI
RDEL
corresponding
no
but
transfer),
a
in
longword
first
signal
or RDEO (Read Data Expected, Longword or Octaword)
the
by
asserted
is
signal
RDEO
or
RDEL
An
asserted.
is
read
DMA
normal
every
of
beginning
the
at
NBCT MCA
transmitted to
1is
command/address
the
after
operation
memory
.

it
after
memory
by
Not enough return read data is sent
read
(incomplete
NBIA
the
to
longword
first
the
sends
on
received
That is, a READ CONTINUE code is not
data).
data
read
more
when
cycle
bus
a
during
lines
FUNC
NMI
the
all
identifies
code
CONTINUE
READ
(The
is expected.
first.)
the
following
data
read
of
longwords

X 3-99

3.5
INTERRUPT (INTR AND IPINTR) OPERATIONS
The NBIB is the device interrupt fielding node
VAXBI.
In
this
capacity,
1t
responds

on
to

1its

associated
1INTR

all

VAXBI

transactions directed to it by causing
the
NBIA
to
generate
an
interrupt request on the NMI.
The CPU then responds to the request
by reading an interrupt vector from the
interrupting
VAXBI
node.
(The

NBIB

NBIA

vector

The

NBIB

generates

also

VAXBI

responds

IPINTR
transactions)
Furthermore, it
can
request.

control
Device

The

bit

the

requests

interprocessor

the

CPU

reads

interrupt

requests

(VAXBI

directed

generated when

the

CPU

sets

the

NBIB

can

generated

1is
how
the NBIB's BIIC normally flags any
is also the means by which the
NBIB
fields

interrupt.

NBIB,

request
by
its
interrupt.

when

from
I/0O
processor
nodes
on
the
VAXBI.
generate
a
VAXBI
interprocessor
interrupt

BIIC,.
This
detects.
It

interprocessor

decoded

transaction

IPINTR transaction is
the BIIC's BCI control

interrupt

its
own
errors it
an

IDENT

address.)

the

BIIC,

NBIB

When
forces

which

the
a

then

TIPINTR

standard

serviced

transaction
device

the

1is

interrupt

CPU

any

other
The

fielding

interrupt

requests

consists

two

basic

operations.
1.

Decoding

the

Generating

VAXBI
the

transaction)

INTR

NMI

the

interrupt

VAXBI

transaction).
Refer

Figure

IPINTR

3-19.

X 3-91

transaction.
request

interrupt

(for

request

(for

INTR

IPINTR

3.5.1

Decoding

Interrupt

Requests

When

the BIIC detects a command/address on the
VAXBI,
it
asserts
CLE
and
transmits the command/address on the BCI I lines and data
lines.
The CLE signal then causes the command/address to be loaded
in
the
BCI
data buffer, and it also causes the VAXBI command (on
the I lines) and the states of data lines <19:16> to be latched
1in
the

NBIB's

cycles

because

commands.
to

make

INTR

interrupt

the

VAXBI.

they

1logic.

The

specify

than

interrupt

one

This

states

the

data

requests

occurs

the

interrupt

line

can

for

four

request

all

data

one

are

1level(s)

asserted,

than

command/address

lines

latched
for

allowing

level

with

transaction.
Interrupt

D<15:16>
1XXX

Request

X1XX

BR7
BR6

XX1X

BR5

XXX1

BR4

X 3-92

Level

Priority
Highest

Lowest

INTR
node

single

BC| DATA BUFFER

LVL/MASK

—

I L6

GEN/CHK

[ rp

[¢———

(NOT USED)«4—

i PR

BIIG

INTR

L (INTR/IPINTR)

LVL/MASK

4 =INTR/IPINTR |

L16

FTO I

LVL/MASK

L14

PARITY

BCl

INTR

(2
v

[—

l:]

DATA BUS: BUFFER

<——F0

CLE

—
D

]

MASTER
PORT

LNGTH

SEQ

CNTR

t6—t X

]

I TOF |g CMD/MASK

_CNF=ACK
SR

SPS-1/4/8 "_‘

SLAVE
PORT

SEQ

SEE_NOTE

CLE

SEL

RS=ACK

L6|LTCH EN

1Pt

LOGIC
DATA BUF

|_TO F

NTR

(

INT

<4>)

BR<4

CLE

SEL

RD EN

SLAVE_PORT

“

(SEE_NOTE)[4— SPS-1

————— e e e

e e o
NBIA

e e

s e

. e e

NBCT
DEVINTR

]

e e

SYNC/XLATE
BIO

INTR LVL <X»

DATA

BUS

INTR/IPINTR TRANSACTIONS

¢ BITINTR LVL <X>

¢ .| |

3 | WAT _WAIT
PE|

4
5

GMPLT

|WHL'STALL

8 E/I:BFRY
9 | RD WAIT

92 || WRT
oEcia
DATA
6

BRX_INTR

DEV INTR
INTR LVL
LVL <1:0>
<1:0
DEV

SEQ_STATES

NOTE: TRANSFER
OF COMMAND/ADDRESS TO DATA
BUS BUFFER NOT SIGNIFICANT FOR

BRX INTR

===

]

{
i

OTHER

NBIB

B | RD RDY

}
!

ool

SCLD-5

Figure

3-19

INTR/IPINTR Operations

The slave port sequencer can be in one of three states

(WRITE

C/A,

MASTER
PENDING,
or
RETRY)
when
CLE
1is
asserted and the VAXBI
command/address is loaded in the
BCI
data
buffer
and
interrupt
logic.
If
in
(or
if
advanced to) the WRITE C/A state when CLE
occurs, the command/address is also loaded from the BCI data buffer

to
the data bus buffer.
This is because the sequencer can begin a
DMA read/write in this state, and the command/address (for a
VAXBI
read/write transaction) must be loaded in the data bus buffer where
it can be taken
by
the
NBIA.
However,
this
transfer
has
no
significance
when
the
command/address
1is
for an INTR or IPINTR
transaction.

When the command/address for a VAXBI transaction is directed to the
NBIB,
the
BIIC
asserts SEL after it asserts CLE.
For example, a
VAXRT

road/wri+n

transaction

causes

SEL

acsgerted

when

the

address
(a
memory
address)
1is within the range specified by the
BIIC's starting and
ending
address
registers.
For
VAXBI
INTR
transactions,
SEL
is
asserted
when
the
appropriate
interrupt
destination mask bit in the command/address is equal to
one.
For
IPINTR transactions, the appropriate destination mask bit must also
be
equal
to
one
with
the
additional
requirement
that
the
corresponding
bit
in the BIIC's IPINTR mask register must be set.
The BIIC may be prevented from asserting SEL
for
either
type
of
interrupt
request
if
normally
set enable bits in the BIIC's BCI
are

cleared.

following occurs when SEL

asserted

for an

INTR transaction.

The NBIB's interrupt
logic
uses
the
interrupt
request
level(s)
asserted
on
data lines <19:16>, and latched by
CLE, to
assert
interrupt
request(s)
to
the
NBIA.
A
request
remains
asserted
wuntil
cleared
by
the
IDENT
transaction that reads the corresponding vector.
Latched
D<19:16>

Interrupt
Request(s) to NBIA

1XXX
X1XX
XX1X

BR7
BR6
BR5

INTR
INTR
INTR

XXX1

BR4

INTR

O
e

The

control

The

slave

port

lines

VAXBI's

the

In the NBIA,
synchronized
TTL

sequencer

the

ECL

BIIC.
CNF

another

When

lines

level.

Then,

higher

NBCT

the

MCA

INTR

asserts

DEV

1level,

encoded

DEV

LVL

Also,

then

for

asserts

for

INTR

ACK

NMI

the
a

its

BCI

transaction,

ACK

INTR

transaction

transaction
NBIA.
an

INT<4>
the

(In

interrupt

input

(to

case,

request

the

code

transaction.
first
from a

ENABLE

1is

not

the

other

bit

asserted.

NBIB

interrupt

also

binary

The

the

request,

the

asserts

number,

transaction,

(IPINTR)

connecting

(BCI INT
the BIIC

transaction,
code

code

BIIC

causes
this

the ACK

INTERRUPT

bus.

the

SEL

the

VAXBI

asserted,

itself).

the

NBIB

BR4
on

INTR

the

to
is

and

for

just

assert

the

NBIB's

one

the

ending

VAXBI

and

interrupt
The

port

The

BIIC

the

IPINTR

the

IPINTR

initiates
the

request

NBIA

the

input
a BR4

slave

inputs.

described,

asserted).

X 3-95

following

the

NMI.

causes

BIIC's

arbitrates

the
to

<7:4>).
The
to interrupt at

the

transaction.

With

VAXBI

2-bit

IPINTR

signal

assert

transmits

code

transmits

lines.

asserted

four interrupt request inputs
asserted
(BCI
INT
<4>)
reqguests
level.

from

BIIC's

sequencer

NBI

request

make

request

1is

ACK

request from the NBIB
is
clock and then translated

can

1logic

the

priority

request

configuration.

SEL

ending

NBI

interrupt

then

the interrupt request from the NBIB causes
assert an interrupt request on the NMI
if

priority

INTR

BIIC

an interrupt
to
the TTL

is set in CSRO,
the NBCT MCA to
higher

asserts

The

then

INTR

the

asserts

3.6

MISCELLANEOUS

The

registers

nodes.
Also,
in addition to
already

OPERATIONS

the

NBIB's BIIC can be
accessed
by
NBIB's BIIC can generate VAXBI STOP
read/write, IDENT,
and
interrupt

the
the

other

VAXBI
transactions
transactions

discussed.

3.6.1
BIIC Register Read/Write Operations (by Other VAXBI Nodes)
registers in the NBIB's BIIC are normally read and
written
by

The
the

CPU.

other

The

node

accessed

registers

VAXBI.

one

are

the

VAXBI

example.) During one of these
and
during
a CPU read/write
o
matter,

the

A
responds

BIIC

independent

That

response

is,

the

any

the
BIIC.
For
control register
during

BIIC

addressed

However,

devices

+ 1

(an

BIIC

NBIB's

read/write

transactions

a VAXBI,

been

initiate

control

bit

another

control

detected,

a VAXBI

bit

in
the

same

bit

one

must

When

loaded
VAXBI

forced

VAXBI

NBIB

does

Although

the
is

1in

However,

INVAL
not

node,

for

+ 3
transaction

port

and

NBIB's

and,

thus,

the

The

SEL

line

the

BIIC's

BCI

slave

not

initiate

cleared

selected
can

this

cleared.

error

associated
by

setting

Because

IPINTR

the

transaction,

BIIC's

IPINTR/STOP

be
loaded
destination

this

stopped.

STOP

cannot

respond

does

the

BIIC's BCI
sequencer)

after

transaction,

issue

VAXBI

any

read

VAXBI

transactions

be examined.
A node can
a selftest operation.

returned

BROADCAST Transactions

BIIC

control

sequencer.

automatic

normally

BIIC
It

BCI

nodes

which

respond

the

SEL

processor

usually

command code must
BIIC's IPINTR/STOP

that error status bits may
normal operation by forcing

3.6.3
An

BIIC

state

used

first

specify

node's
a

transactions.

so
to

any

also

slave

the

transaction.

BIIC's

command register.
The STOP
register
as
well, and the
must

STOP

the

can

read/write

causing

control

registers

A L
. 4.
read/write

VAXBI

the

condition
a

I/0

IZAVDT

the

3.6.2
VAXBI Stop Transactions
The CPU can stop all activity on

NBIB

the

registers

this
reason,
the
control bit in the
enabling the assertion of SEL (to
the

has

BIIC

(local) VAXBI read/write
operations,
operation to a BIIC register for that

control

the

to VAXBI
may

port

INVAL

sequencer

asserted

and

selected,

because

are

X 3-96

BROADCAST
the

BIIC

ignores

the

enabling

normally

transactions.

does

not

control

cleared.

assert

transaction.

bits

3.7

DIAGNOSTIC

There

are

DATA TRANSFERS

three

types

BIIC

NBIA wraparound

CPU

3.7.1

BIIC

loopback

diagnostic

data

transfers.

requests

read/write

Loopback

NBI

to memory

(FLIP

29/22)

Requests

CPU read/write operations can be executed that do not
require
the
use of the VAXBI data lines.
When the BIIC LOOPBACK control bit is
set in the NBIA (in CSR0O), and a CPU read/write
to
VAXBI
address
space
1is initiated, the master port sequencer in the NBIB does not
make

normal

loopback
BIIC

VAXBI

request

operation
1.

The

transaction

during

BIIC

loopback

ignores

all

the

own

nodal

BIIC's

Also,

the

VAXBI

can

the

BIIC.

makes

does

BIIC

internal

data

follows:

bits

<12:00>

NBIA.

Thus,

only

address

the

VAXBI

address

registers

space

(its

within

internal

addressed.
not

read/write
of

loopback

BIIC

transfer

diagnostic

request

but

from

BIIC

transferred

registers)
2.

request

instead.

arbitrate

transaction

for

the

read/write

bus

does

data

generate

normally.

made

The

wvia

path.

requests

are

operations.

wused

They

also

1isolate

have

the

function

VAXBI

during

normal

operation.
At

powerup,

the

node

control/status
register
which depends upon which
cannot

determined

operation.

(The

normally.)

Consequently,

read

the

CPU

loaded

automatically

the

as described in Section 3.2.
ID plug
is
inserted
in
the

needs

the

CPU

the

node

the

CPU makes

1ID.

X 3-97

means

access
a

BIIC

BIIC's

normal

BIIC

loopback

BCI

This value,
backplane,
CPU

read

3.7.2

NBIA Wraparound
If a CPU read operation to a VAXBI address is executed with control
bit
NBIA
WRAPAROUND
set
(in
CSR1l), the read command/address is
passed through the NBIA and transmitted on one of data bus ports as
is
done
normally.
However,
the
command/address
(now
in
the
cerresponding NBIA data bus buffer) is passed back through the NBIA
and
the
address
returned to the CPU as read data.
This allows a
large portion of the NBIA's data path and control
«c¢ircuits
to
be
checked without the need for an NBIB.

The normal transfer of the read command/address through the NBIA is
as described in Section 3.3.3.1, and as shown in Figure 3-11 (Sheet
l1).
The command/address is taken from the NMI and written into the
transaction
buffer.
It
1is then read from the transaction buffer
and joaded into a set of latches (Li) in a data
bus
buffer.
The
same
thing
occurs
1in
wraparound
mode.
The only difference in
overall operation is that after the command/address
is
1loaded
1in
the
data
bus buffer, a CPU REQ signal is not asserted on the data
bus port (in case an NBIB is connected).
To begin the loopback of the command/address through the NBIA,
the
data bus control immediately asserts the latch and read enables for
another set of latches in the data bus buffer (L4).
These are
the
latches
normally
1loaded
with return read data from the NBIB.
In
this case, however, the latches are loaded with the command/address
because it is still being transmitted on the data bus port from the
other set of latches (L1) in the buffer.
Once the
command/address
has
been
turned
around in the data bus buffer, it is passed back
through the NBIA just like return read data.
That is, it is
first
written
1into
the
transaction
buffer.
Then, it is read from the
transaction buffer and (in this case) the address is transmitted on
the
NMI
data lines after the NBIA requests and wins the bus.
The
transfer of return read data is described in
Section
3.3.3.3
and
shown in Figure 3-13 (Sheet 2).

X 3-98

3.7.3
CPU Read/Write to Memory (Flip Address Bits
Normally, a CPU read/write (longword) operation to

<29> and
a VAXBI

<22>)
address

can

only access a register in a VAXBI node.
The register address,
a VAXBI I/O address, has address bit <29> equal to
one.
However,
if a CPU read/write is initiated with control bit FLIP 29/22 set in
the NBIA (in CSRO), the NBIA changes address bit <29> from a one to
a
zero
after the command/address is taken from the NMI.
(Another

address

bit,

parity.)
0).

bit

This

Thus,

when

transaction
BIIC

will

does

<22>,
makes
the

also

changed

value

I/O

address

memory

NBIB's

BIIC

transmitting

respond
a

is
the

(to

memory

the

its

generates

converted

own VAXBI

reference

to maintain
address

the

VAXBI

address

transaction)

VAXBI

device.

1In

VAXBI,

other

CPU read/write operation causes a
DMA
read/write
transfers read/write data to/from memory instead of

<29>

read/write

the

correct

(bit

the

normally
words,

the

operation
that
to/from a VAXBI

node.

The

flipping

allows

read/write
device.
being
and

just

data

control

through

the

are

before
rest

changed

they
the

shown

operation

and

NBI

are

address

without

CPU

the

majority

can

checked

value
in

need

read/write

the

loaded

bits

command/address

in
the

the

of
in

<29>
and

for

and

the
one

and

longword

VAXBI

1I/0

DMA

NBI's

read/write
data

operation.

NBIA's

NMI

transaction

<22>

data

buffer

path

The

two

buffer

along

with

command/address.

and

data

Figure
a

with

circuitry

bits

value)

loop

concurrently,

Command/address
is

the

Furthermore,

executed

address
the

(changing

diagnostics

CPU

flow during

3-20.

write

Flow

operation.

X 3-99

the

diagnostic

1is

shown

for

data
both

transfer
a

CPU

read

For

CPU

write

data

operation,

from

the

NMI

the
and

NBIA

takes

passes

the

command/address

the

NBIB

causing

and
VAXBI

write transaction to be initiated as in
normal
operation.
Then,
with address bit <29> = 0, the VAXBI transaction causes a DMA write
operation to be initiated in the NBIB while the CPU write operation
is
still
executing.
That
1is,
when
the
NBIB
transmits
the
command/address and write data on the
VAXBI,
it
also
takes
the
command/address and write data from the VAXBI and passes it back to
the NBIA.
The NBIA then generates an NMI
write
transaction,
and
the
command/address
and
write
data are transferred to memory to
complete the operation.
For

CPU

takes
Ml
L11CT

read

the

AIDTD
IND LD

operation,

and

command/address

+hAam
L1iiT11

amabdadbacs
LliliviauTo

a
a

similar

from

YTAVDT
VAND L

the

NMI

and

CPU

S aamime
o ~de 2 o~
LLdiloaoeu 1LuUll

write,

passes

{ =1 3 ~
VLIILD

a4
L 1LIIC

the

NBIA

the

NBIB.

ITAVDT
VAAND
L

read
transaction).
Also,
with
address
bit <29> = 0, the VAXBRI
transaction
causes
a
DMA
operation
(this
time,
a
DMA
read
operation)
to
be
initiated
in
the
NBIB.
That
1is,
the
command/address transmitted on the VAXBI is looped back to the NBIA
and

NMI

transaction

initiated.

When

the

passed

the

NBIB

read

(this
data

and

time,

1is

read

returned

transmitted

operation.
Then, with the CPU read still
the
read
data
£from the VAXBI and
loops
data is then transmitted on the
NMI
to
operation.

transaction)

from
the

memory,

VAXBI

1is
1is

normal

executing, the NBIB takes
it back to the NBIA.
The
the
CPU
completing
the

The reason a CPU read/write to a memory address can be
implemented
in
the
NBI
is
Dbecause
the
NBIB's master port sequencer (which
initiates VAXBI transactions) and its slave port
sequencer
(which
responds

independent

operation
initiated
one

time.

The

retry

MASTER

each

try

CYCLE

slave

transactions)
operate
almost
other.
However,
an
exception

completely

normal

is
that
when
the
VAXBI
by the master port sequencer,

read/write
transaction
1is
it always has to be retried

occurs

sequencer

PENDING

first
the

VAXBI

state

the

WRITE
port

acknowledge

because

slave
a

CPU

transaction,

the

CYCLE

state

sequencer

the

the
by

port

read/write.

master

clears

the

transaction

when

SYNC
IDLE

port

REQ

placed

and
a

the

during

sequencer's

PENDING,

state
tried

However,

which
allows

second

time.

the

READ

returns
it

(This

is the normal
mechanism
that
allows
the
NBIB
to
perform
DMA
read/write
operations
during
the
time a CPU read/write is being
retried.) The transaction
can
now
be
acknowledged
because
the
command/address
(and the longword of write data if a CPU write) is
buffered in the BIIC during the first try.
That is, the NBIB
data
path
is
now free to transfer the command/address and data for the
upcoming

DMA

transfer.

CPU WRITE TO MEMORY

Z/\X

DMA C/A & DATA

CPU

VAXBI

NBIA

NBIB

NMI

MEM

Y
CPU C/A

& DATA

CPU_READ TO MEMORY

NMI

MEM

DMA DATA

NBIA

DMA C/A

NBIB

SCLD-2

Figure

3-20

FLIP

29/22

Diagnostic

X 3-191

Data

Transfers

Digital Equipment Corporation.Bedford,

MA 01730