VAX 8800 System Technical Description Volume 3

This document, Volume 3 of the VAX 8800 System Technical Description, provides a detailed technical overview of specific hardware components within the VAX 8800 system. It focuses on two primary areas: the Memory System (MBOX) and the NBI (NMI to VAXBI Adapter).

The document is structured into two main sections:

1. Memory System (MBOX): This section details the hardware of the VAX 8800's memory, comprising the Memory Controller (MCL) and Four-Megabyte Memory Array Boards (MAR4s). It covers:

   • MBOX Operations: Including various NMI signals used, different command bus cycles (longword, quadword, octaword, hexword for reads and writes), and the "sort-of-write" feature.
   • Memory Controller (MCL) Functional Areas: Detailed descriptions of the Data/Address (DAD) MCAs, Function (FUNK) MCA, Memory Data Buffer (MDB), Data Check (DCHK) MCA, Memory Request Manager (MRM), Memory Array Sequence Control (MASC), Read Control Sequencer (RCS), and the BNUM Probe Buffer and Error Logic. These sections elaborate on command/address sequencing, data transfer cycles, error correction (ECC), handling of NMI interrupts and busy states, and CSR (Control/Status Register) operations.
   • Four-Megabyte Memory Array Boards (MAR4s): Describes their internal architecture, including the VAX 8800 Array Bus (NAB), clocking mechanisms, 4MBARRAY banks, input parsing, ECC/DPARITY logic, data output control, and refresh operations (normal and battery mode).
   • Battery Backup Unit (BBU): Covers its role in power loss and recovery scenarios.

2. NBI (NMI to VAXBI Adapter): This section describes the NBI, which serves as the interface between the VAX 8800's main CPU/memory bus (NMI) and its VAXBI I/O buses. Key aspects covered include:

   • General Information and Physical Description: Overview of the NBI's two main modules (NBIA and NBIB) and their role in connecting CPU/memory to VAXBI devices.
   • NBI Registers: Details various registers within the NBIA and NBIB (BIIC) that control and monitor NBI operations, including control/status, vector, interrupt, and address registers.
   • Interface Descriptions: Explains the NMI and VAXBI signal lines, their basic timing, address spaces, and transaction types (read/write, interrupt, stop, invalidate, broadcast).
   • Functional Description: Provides block diagrams and explanations for the NBIA's internal MCAs (NPAR, NBIM, NBFD, NBAP, NBCT, DSEQ), transaction buffers, and data buffers. It also details NBIB components, initialization, self-test procedures, and power-up sequences.
   • CPU Read/Write Operations: Describes address decoding and translation, local read/write operations, and the command/address and write data transfer processes between NMI and VAXBI.
   • DMA Read/Write Operations: Explains the flow of DMA data transfers, including command/address and write data transfer, return read data transfer, and error handling.
   • Interrupt Operations: Covers INTR, IDENT, and IPINTR transactions and their decoding and generation.
   • Diagnostic Data Transfers: Discusses specific diagnostic features like BIIC loopback requests and NBIA wraparound.

In essence, Volume 3 provides an in-depth technical understanding of the VAX 8800's memory subsystem and its critical interface to the I/O bus, detailing their architecture, functionality, and error handling mechanisms.