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Document:	VAX 8800 System Technical Description Volume 2
Order Number:	EK-KA882-TD
Revision:	PRE
Pages:	456
Original Filename:

OCR Text

EK-KA882-TD-PRE

VAX 8800 System
Technical Description
Volume 2

FOR INTERNAL USE ONLY

EK-KA882-TD-PRE

VAX 8800 System

Technical Description
Volume 2

FOR INTERNAL USE ONLY

Prepared by Educational Services

of
Digital Equipment Corporation

Preliminary

Digital
All

Equipment

Rights

Edition,

Corporation

1986

Reserved

The information in this document is
without
notice
and
should
not

subject
to
be
construed

commitment by Digital
Equipment
Corporation,
Equipment
Corporation assumes no responsibility

errors

that may

appear

Notice:

change
as
a
Digital
for any

this document.

Printed

Class A Computing

July

U.S.A.

Devices

This equipment generates,

uses,

and

may

emit

radio
frequency
energy.
The
equipment has been type
tested and found to comply with the limits for a Class A
computing device pursuant to Subpart J of Part 15 ot FCC
rules,
which
are
designed
to
provide
reasonable
frequency interference
vradio
such
against
protection

when operated

in a commercial environment.

this
equipment
in
a
interference in which case

may

required

Operation of

residential
area
may
cause
expense
own
the user at his

take

measures

correct

the

interference,

The

following

are

trademarks

Digital

Equipment

Corporation:

logo
logo

DECwriter
DIBOL

DEC
DECmate

MASSBUS
PDP

DECsystem—-10
DECSYSTEM-20
DECUS

Professional
Rainbow
RSTS

DECset

P/0OS

RSX
Scholar
ULTRIX
UNIBUS

VAX

VMS
VT
Work

Processor

1986

CONTENTS

Logic.

b=
—

RAMs

Address

Store.

Code

CPU

State

[]

Address

Bus.

Data

[)

Logic.

Bus

RESIDENT

[

INTERNAL

[

=
N

8800-Specific

VAX

Interrupt

Clear
=

IBER

Usage

Bits

IBER
Clear

PRIVILEGED
[

IPRs

REGISTERS

ONLY

Other
.

Processor

VISIBLE

IBER

Control

Interrupt
Error

IBox

Logic

I PRS [ )

Other

MICROCODE

Architecture

Interrupt

Bus

VAX

NMI

Logic

Generator

Functions.

IBOX

Macrobranch

Processor

Primary

Bidi

[]

Control

Data

Gateway

Regist er

Cons

Processor

Consumed

Flags.

and

Data

Logic.

Cache

Interrupt

BUSES

.«

Data

and

Bits.

Encoder.

Log 1C

IBOX

Control
N =

[]

W00

Control

Amount

Read/Write

PSL

Microseguencer

File

R e

Computing

Interrupt

T e vy S RS = b
I
R
R
R
R
R
R
R |
COWOUWLCOINODAOANUT
ULV N N
’..._l

the

(IB).

L 4

ot
.

wwWwbhN DN e

Reading

Manager

Condition

the

o
o
e«

Writing

Special

NN
N

.
[]

Buffer

IBOX

[)

Con figuration

Implement ation.

Decoder

WD
-

Instruction

[]

e B T

ELEMENTS

Decoder

el e
e

e e
R
e
e
e

Ll e
e
e
.

VUTUTO
U Utul e b

SR
*

i
S
o
R

Physical

LOGIC

(IPRS)

Dual-Processor

Nd~JOWU b

U
TP
S
U
S
.

S
S

OVERVIEW

I e e

INTRODUCTION

Processor
.

Bits

<11:08 >.

[]

Error

Regist er

(CER)

(NICTRL)

<7:0>.

iii

REGISTERS.

(IBER)

(INOP)
.

(CIOP)

(IBOX)

—

CHAPTER

BOX

—

INSTRUCTION

B WWWWNONDNINNNNNNDNODMOMNNMODMNNDONNDNDNDNDNNNDN

SECTION

.
.

.
e

Flles.

.
«

.
.«

.
.

MICROCODE PIPELINING CONCEPTS.
Pipelining Rationale . . . .

.
.«

.
.

.«

VAX 8800 PIPELINE CHARACTFRISTICS

Microcode Definition Files . . .
Field Definition File - DEFIN.MIC,
Macrodefinition File - MACRO.MIC
Microcode Related Documentation.

Format

Field Naming Convention.
Field Functionality. . .

L]
.

Pipelined Versus Nonpipelined Machines

Factors.

¢«

Desighn.

Funct iOnSQ [ ] . L ] L ] L L
IB Decode Cycle. + ¢« ¢«
Canonical Time States.

L]
¢

LJ
«

L
«

L]
o«

[]
&

.«

States.

+«

o
o

Segments

o
.

Performance

Clock

Cycle.

o
.«

o
.

Latency

Microsubroutine Calls and Returns.
Normal Microstack Operation. . .
Microsubroutine

Calls.

B
N

b~
—

s
.

¢
.

Microbranch

o
+
«
Flow.

S
[]

Decoder Supplied Microaddress
.«

Microbranch Conditions

MCAs.
.

=0 WVWOWOWO-JOAONUTUN
N -

«
Microstack .«
Normal Microcode

(UBRS)

MCA

(UTRP)

—

Microtrap

o
&

wWw
N =

Microbranch Slice

¢ « « o o
Hardware.

.
. .
Loading the Control Store RAMs .
Load Control Store Microaddress.
Write Data to Selected Address .

MO R

&«

=
N

.
.

Control Store RAM Addressing .
Control Store RAM Data Latches

Microbranching
s

RAM

¢«

Store

o
@«

«
+
.
LOGIC.

STORE

SCOPE.,

CONTROL

el =T N

CHAPTER

MICROSEQUENCING.
Microsequencer

JT U

Events.

IBOX FUNCTIONAL DESCRIPTION

Control

b
s W N

L]
.

State

—

(NN

Time

@
®
L]
[

Overlapping Time

Wwwwwwww
l WWWwWwWwwwwwwwwww
I

L UTULE

L]
.

NN
W o=

File Structure
Assembly . . .

Relationship Between Microcycles and

o«

CPU Hardware

CPU

WWwhwwwiwWwwwwwuwwiodhdhNbdbh
N e

Other Loadable Binary

Microword

.
[
.
L]
.

[-—

Microcode
Microcode

i
ww
wwb

Ld
N

W
)
L) W

Definition of a Canonical Time State

SCOPE.

VAX 8800 MAIN CONTROL STORE OVERVIEW
Microcode Size and Allocation. . .

[

WwWwWbh

I s BB WWWWNNNNNNRNDNDNDNDNDDNDNDND

NNV NNMNNNMNNMDNNDNDNMNDNDNDNDNNNDNDNDDNDNDODND

»
@

*
.

[N =

CHAPTER

MICROCODE OVERVIEW AND PIPELINE CONCEPTS
=
|
P
W
W W Wt

CHAPTER

N
.

OY
=
N

~]1 O

Microtraps

=
N
w

Partial

=W
N

o
o

e
e
o

o
¢

W N

o
o

e
o
e

OO
U
Wi

e
e
e
®
e
e

e+
8
o

U W=

(IB

Logic

Flush

3-25

Prefetching

3-30

3-32

Flush)

3-32

3-34

3-38

3-39

Description.

3-39

3-32

Cache.

3-39

3-40

Control

3-40

Logic.

3-42

the

Monitor

Full

Logic.

.«

3-43

Load

Example.

3-43

The

3-45

Timing.

3-45

Read

Ports.

Data

3-46

Aligner.

3-51

Data

Formatter

Read

Example.

Manager

Read

Opcode

Decoder

3-73

Logic

3-76

Logic .
TEMPINC <2:0>

3-78

the

Address

Computing

Number

Decoder

Timing

Specifier
Entry

IBST

Validity.

3-81

3-82

Control

Signals.

Longwords

Consumed.

Operation.

Considerations
Entry

Point

MCA

Signals

Decoder

RAM

3-91
3-93

Addresses.

Microaddresses.

.
Related

3-85
3-93

Microaddresses

Decoding

3-96

3-104
3-111

Instructlon

(DRAM)

3-121

.
.
Instructions

3-128

3-118

Instructions

Simple

Move

Optimized

Pointer

Pipeline

Special

Logic

Operand
Opcode

3-66

Size

Stall.,

Read

3-60

Logic.

Modifying
IB

Scrambler

Operations.

Watcher

Checking

Data

Address

Specifier

and

Instruction

(o))

Pipeline

o
e

YU
W N

3-23
3-23

IB Write

IB
.

Refilling

Cache

the

General

DECODING.

Flush.

Flush

Reading

Full

.
.
Microaddresses

Supplied

I-Stream

.
L
L]
o

Disabling

Simple

Branch

MACROBRANCH

Returns.

Microtrap

Initializing

~N o

o
e
e
&
s
o
o
o
o
L]

.
L

»
»

«
o«
Servicing.

Console

OO UTUIULNTUTUVTUTUTUTUL
S D BB DB WWWWWN NN

o
o
o

DWWWWW

o
o
o
e

R LEDRDS DRSS SRR DDA

e
e

o
s
e
o
&
o

RSB

s
o
@
e
o
e

LWWWWWWwWwWwWWwwWwwwWwWwwwwWwWwwWwWwWwwwwwWwwWwwWwwWwwwwwwwww

1N
o

N
T

MACROINSTRUCTION

Y
@

RO NG RN ) BN 2 RN

e
L

(2NN

Wwwwwwwwwww

Microsubroutine
Microtraps

3-128

Instructions

INSTRUCTIONS

3-129

Branch

Instruction

Basics.

3-129

Branch

Instruction

Classes

3-130

Branches .
.
Conditional Branches

3-130

Unconditional
Short
Long

Conditional

Condition

Code

3-135

Branches.

and

Macro

Branch

3-141

Logic.

3-147

whh=

o
o

JTOOOOD

o
o
*

W N

e
o
o
o
o
e

Q00O

WWWwwWwwwwwwwww

SPECIAL REGISTER ADDRESSING.
RNUM1 and RNUM2 Registers.
RLOG Register. « v« « « o o
MDNUM Register . . ¢ « o« o
INTERRUPTS . v 4 ¢ o o « o o

+ 4« ¢ @« ¢« o« «
. .« « « « ¢ o«
o o o o« o o« o«
« o o o o o o
o o o o o o o
Interrupt Requests . . « ¢« ¢« ¢ ¢« ¢ ¢ o «
Interrupt Servicing. .« « « ¢ o o « &+ « o«
CONSOLE GATEWAY CONTROL. « & « & « o « o «
Loading Control Store and Decoder RAMs .
Starting the Micromachine. . . . . .
e
Data Transfer with Console Resident IPRs
Breakpoint Microtrap . . « « « ¢« +« o « «
Console Data Parity Check. . . . ¢« . . .

o«
&«
o«
o
o«
o
o«
o«
.
«
.
«
.

«
«
o
o
o+
o«
o«
o«
.
o
«
+
.

o
o
o
&
o
o«
o«
«
.
«
.
o
.

3-150
3-150
3-150
3-152
3-153
3-153
3—-153
3-158
3-158
3-160
3-160
3-160
3-161

FIGURES

IBox Block Diagram « .+ « « o o o o o o o o
NMI Interrupt Control (NICTRL) Register
Bit MADe
«
¢ ¢
o ¢ o o s
o
o o
o
o o o
o o
Interrupt Other Processor (INOP) Register
Bit Map.
«
¢ « « ¢
o o o
o
o
o s
o s o o o
IBox Error Register (IBER) Bit Map . « +. «

o«

1-14

o«

1-15

1-18

Microword Bit Format .
Sample Microword Field
I APORT Field. ¢ ¢« ¢ ¢

o«

Diagram -

Pipelined CPU

o«

FunctionS.

¢
& o
o
Diagram

o
.

o
+

o
«

o«
.

=
.

Basic

Time

State

Basic

CPU

Timing

N
W

Microcycles/CPU
IB

Decode

CYCle.

«
v

«
¢

Canonical Time StateS.
VAX 8800 Pipeline Time

o
o

. « «
State

Contrcl Store Logic Simplified Block Diagram
. .
Microaddress Bit Slices for Micromatch Register
Loading. . . .
e 4 e e o o o o o o o e s e s e«
Control Store RAM Load Path. « « ¢« « ¢« ¢« « ¢« « .
Microsequencer

LOgiC

2-4

33
37
3-8
3-10

o«

Normal INEXT Field Addressing. .
Microbranch Condition Selection.
Microbranch Latency.
. «
¢« « «
o
Microstack Operation .
.
.«
«
¢
¢
Microtrap ServiCing.
«
+
&«
o
«
o
Microtrap Latency
« «
o«
«
o
o
o

«
.

¢
.

«
.

o
.

«
.

o«
.

o
o
o
o

o
o
s
o

o
o
«
o

o
o«
s
o

o
o«
o«
o

o«
.
«
o«
o
»

Console

¢«

.«

o«

3-31

o«
s

3-12
3-14
3-20
3-22
3-26
3=27

NN N

H = P b
OO
B WO

AR S

WWWwWwwwwwwwww

O 00O
U1
W

Basic Time State Diagram - Nonpipelined CPU.

1-3

W N NN
O 00N
=

¢«

NNNITJNI\JNN

¢
o

. « ¢ ¢« ¢
Definiton
¢ o o
o
o

(NI

Page

Title

Micrecaddress.

Supplied

Instruction Buffer
IB Flush LOQiC 4+
«

Logic
«
«
o

.
o

«
o

¢«
o

&+
o

¢«
o

«
o

«
o«

o«
«

3-33
3=-35

o«

3-41

Load

LOGIC.

I-Stream

Data

Memory

Entering

Unit

the

Contents

IB.

for

MOVL

Read

Port

Example

Part

Read

Port

Example

Part

3-44
Example

3-48
3-49

Data

Aligner

Data

Aligner

Muxes,
Output

Data

Aligner

Example

Part

Output

Example

Part

Opcode

Mux

Data

Formatter

Read

Example.

PCNC

MCA

Block

Simplified

Instruction
Operand
Opcode

and

Data

Scrambler

Logic

3-74

Logic

3-83

Logic
Entry

Entry

Special

Address

Decoder

RAM

Read

Decoder

RAM

Output

Address

3-94
Format

Format.

Encoder

3-111

Logic.

Address

3-112

Format.

3-121

Signals

3-123

State

for

BRB

Pipeline

State

for

Successful

BEQL

for

Successful

AOBLEQ

and

Macro

Slice

MCAs.

Instruction

Instruction.

State

Instruction,

Code

Interrupt

Logic

Control

3-96

3-104

Format.

Pipeline

Gateway

3-61
3-69

Address

Decode

Address

3-57

Diagram®

Read

Address
Microaddress

File

3-55
.

Special

Condition

3-54

Specifier

Pipeline

3-51

Sources

3-47

3-131
3-140

3-145
Branch

Logic.
*

Simplified

Block

Diagram

Logic.

3-148
3-151

3-155
3-159

Ul
W N~

HWOWOO-JOU
D WN -

Title

Page

Microcode

Features

Resident

IBox

NICTRL

[N T

NN DMDDNDNDRDDDNDDNDND

=z
o

TABLES

INOP

IBER

Bit

VAX

8800

Bit

Descriptions

Description.

Descriptions.
Microcode

Transfer

Sample

Cache

Sample

CREG/IREG

Sample

Microbranch

Classes.

Sample

1-14
1-15
1-10

Files

Macroexpression

1-9
1-13

Definitions.

Field

Microword

IPRs

Command

Macros.

Sample Miscellaneous Macros.
Pipelined/Nonpipelined CPU Comparlsons
Pipeline Time States/CPU Events.

2-17

2-18
2-19
2=-22
2-31

o«

Conditions
T LTM
LD AW SN R S

Source.

Sources.

o«

Microtrap Conditions and Vectors

Microaddress

IBRTYPE/IBRMASK Microword Field Relatlonshlp

Microbranch Conditions

W OO~

|
U

Wwwwwwwww

Control Store RAM Segment Functionality.
.

Machine
11 11t1l

Check
8
S Wl
L

Microtrap
A
[

Special Microbranch Condition Bit Usage.

IBST and PCNC MCA Outputs After an 1IB Flush
IB Flush Relative State Changes - IBST and PCNC

MCAS

IB Read Address/IB Read Port

Data Aligner Control Signals/Data Selection.
IB Data Format Control Signals/Functions . .
IB Format Control Signals/Specifier Data Type
IB Data Formatter and Data Scrambler Qutput,.
Floating Point Short Literal Formats . . . .
Specifier Size Logic Control Signals . . . .
IB

Source.

Size

Slow Spec

Pointer

<2:0> Values.

.«

Operand Specifier Entry Address Blt

Descriptions

.«

o«

Operand Data Size/Access Type Correlation.
Operand Specifier Entry Address Symbolic

Labels

CYCLlES

Sample Field Value Assignments - I APORT

Opcode Entry Address Bit Descriptions. . . .
Special Microaddress Conditions. . . . . . .
Special Conditions Serviced During IB Decode
o

Decoder RAM Output Signal Descriptions . . .
Execute Code for a BRB Instruction . . . . .
Microword CTL.BRB.MEM Event Timing . . . . .
IMISC Field Settings for Macrobranch Recipes
IMISC Field Settings for PSL Condition Code
Recipes

Execute Code for a AOBLEQ Instructlon. o« o o
IMISC Field Settings for State Flag Control.

Hardware Interrupt Priority Levels
Interrupt

ID Codes/IPLS.

¢«

EXAMPLE
No.

Title

viii

SECTION

EXECUTION

CHAPTER

INTRODUCTION

1.1

BOX

GENERAL.

LOGIC

(EBOX)

l.1.1

1-1

EBox

Organization.

¢«

1.1.2

4«

EBOX

Operators

1=2

o«

1-4

1.1.2.1

Main

1.1.2.2

ALU

Cache

Data

Path

Watcher/Decoder
1.2

SLICE

MODULE

1.2.1

Parity

1.2.2

1.2.3

Slow

1.2.4

Program

Cache

1.2.6

Main
Bus

1.3

and

¢«

&«

1-5

(PAR)

o«

¢«

1-6

¢«

o«

1-6

Subsystem

o«

1-7

¢«

1=7

(PC)

Path

Arithmetic

(CDP).

Logic

Unit

Watcher/Decoder

MODULE

FUNCTIONS

(SDF)

Counter

Shifter

Bus

(RGF).

File

Data

SHIFTER

1.3.1

(CDP)

(SLC1/SLCO)

File

Data

(BWD).

Generator/Checker

1.2.5
1.2.7

(SHR)

(SHF).

(BWD).

¢«

(Main

ALU).

¢«

+«

1-8

&«

o«

1-8

FUNCTIONS

&«

1-9

¢«

o«

1-9

1.3.1.1

Integer

1.3.1.2

o«

1-9

Floating-Point

Data.

¢«

1-9

Decimal

Data.

¢«

1-10

Support.

+«

1-10

1.3.1.3
1.3.2

Data

String

Floating-Point

1.3.2.1

Priority

1.3.2.2

Shift

1,3.2.3

(FP)

Encoder

ALU

Exponent

1.3.3

ALU

1.4

EBOX

REGISTERS

POLR,

1.4.2

VAX

1.4.2.1

P1LR,

+«

1-10

o«

1-11

(XALU).:

and

System

1.4.2.3

Revision

1.4.2.4

EBox

o«

1=-11

(MULT).

&«

1-11

o«

1-13

SLR

Check

1.4.2.2

8800-Specific

Machine

(PEN)
v

(SALU)

Multiplier/Divider

l1.4.1

CHAPTER

Reglster

Identification
Registers

Parity

Error

2.1

GENERAL.

SLICE

(SID)

(REVR1l

(SLC1/SLCO)

1-13

(MCsTS).

1-13

REVR2)

1-12

1-14

1-15
1-17

(EBER).,

o«

DESCRIPTION

2-1

2-1
2-8

Generator/Checker

Formats

and

2.2

MODULE

Registers.

Status

DESCRIPTION

Parity

Bit

FUNCTIONAL

2.,2.1

Internal

(PAR)

2-1

2.2.1.1

Parity

Generator

¢«

4«

2.2.1.2

Parity

Checker

¢«

o«

2.2.1.3

EBox

Parity

(EBER).

2-11

Carry

Save

o
v

o
&«

o
v

o
4

o
o

o
o«

o
«

o«
o

2-12
2-14

(FPS)

2.2.1.4
2.2.2

Error
LOgiC

File

Floating-Point

2.2.2.2

Memory

2.2.3

Traps
Slow

Data
and

Data

(RGF).

2.2.2.1
2.2.2.3

v
v

Shuffle

(MD)

Stalls

File

v
.

v
v

¢«
v

Registers

2-8

2-14

2-16

¢«

o«

2-16

(SDF)

¢«

&«

o«

2-18

2.2.3.1

WEites

2-19

2.2.3.2

Reads.

¢«

o«

2-19

2.2.3.3

Stalls

and

Traps

o«

2-19

N
W
=
N

o
e

o
o

e
[Z

[NORN

e
®
o

W N

@
.

U
-

.
L]

N
w

e
.

W N
Ul s

LJ
.
o
o
*

o
o
¢«
[]

o
o
e
e
e

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NN

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&
&
©
o
e
e
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e

Program Counter (PC) . .
Cache Data Path (CDP). .
Cache Data Buffer (CDBF)
Cache Data Store (CDS) «

Main Arithmetic

L[]

AN
UL
b

wwwwwwwwwwwwwwwwwwt\)wl\)l\.‘vI\Jl\JNNNN

NN NBODODNODNMNDODNDNOONDNNDNNDDNDNDODN

Program Counter (PC) Subsystem
PC VA FA MultipleXer . « « o
Virtual Address (VA) File. .
Trap Shadow Logic. « « « ¢ ¢

Logic

2-272

2-22

«
¢
¢

¢
¢

«
«

«
o

&
&

2-22

2-23

2-24

«
¢
«

2-31
2-31

Unit

+« « « « « .
(Main ALU).

ALU First Half (ALF) ¢ o« o o
Main ALU Functions . . « « «
SHIFTER MODULE (SHR) DESCRIPTION
Shifter (SHEF).: « ¢ o o
o
&+ o
o
« ¢ «
¢
Shift Count BUuS. « «

2-33
2-41

o
o
,
o
o

o
¢
.
o
o

o
«
.
s
o

o
o
«
o
o

o
o
.
o
o

o
&
.
o
o

2-41

2—-44

2-51
2-51
2-55

Function Selection

.«

2-55

.
«

.
¢

.
o

.
¢

.
o

.
&

2-58

Decimal String Conversion.
~ Floating—-Point (FP) Support.
Priority Encoder (PEN) MCA

.
.
.

«
.
.

«
«
.

«
«
«

.«
«
.

.
=&
.

2-58

Shift ALU (SALU) v ¢ ¢ o o
" Exponent ALU (XALU). ¢« ¢ ¢
Multiplier/Divider (MULT). .
Data Interface Signals . .
Carry and Control Signals.

2-70

o
«
«
.

o
«
+
«

&«
o«
¢
«

o
«
«
.

o
+
o
.+

&
.

2-78

.«
«

«
o«

General

Logical Shift or
Arithmetic Shift

Rotate.
. . . ¢

Logical and Arithmetic Functions

Multiplier Operation
Divider Operation. «

.
.

.
«

«
«

2-58
2-60

2-62

2-86

2-86
2-86

2-86

2-95

2-96

FIGURES
Z

YU
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o)
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e
e

MDD
NN
|
|
[
W-JOoO
U
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[

Page

Title

s«
.
.

=
.
.

VAX 8800 CPU Kernel Block Diagram. . «
Execution Unit (EBox) Block Diagram. .
Machine Check Status Register (MCSTS).
System Identification (SID) Register

«
.
.

Diagram

Revision Register 1 (REVR1l), . . . . . . . ;
Revision

Slice Module

(REVR2).

(SLC1/SLCO)

Parity Generator/Checker

Block

(PAR)

¢«

Block Diagram

EBox Parity Error Register (EBER).
Register File (RGF) Block Diagram.
Slow Data File (SDF) Block Diagram

.
.
.

Block

Shifter Module (SHR) Block Diagram
Shift MCA (SHFT) Logic and Gating

(PC) Subsystem Block Diagram
(CDP) Block Diagram. . . . .
Leogic Unit (Main ALU)

Program Counter
Cache Data Path
Main Arithmetic

Block

Diagram.

Diagrame

o«

1-1

1-3
1-13
1-14
1-15

1-16

Shift

Control

Shift

Count

Block

Diagram.

2-13

VAX-11

2-14

Priority

MCA

Bus

(SHC)

Encoder

2-15

INMUX

Mapping

Shift

ALU

2-17

Exponent

2-18

Multiplier/Divider

the

(SALU)

Diagram

2-61

2-64

Data.

2-65

Diagram.

2-73

2-79

Block

BPORT

Block

(XALU)

Gating

Formats.

(PEN)

2-16

Diagram.

and

Floating-Point

ALU

Block

Signal

Input

Diagram

Block

(MULT)

Block

Diagram.

EBox

2-55

2-88

TABLES

Title

Privileged
POLR,

IPRs

PILR,

Maintained

and

SLR

the

Internal

Machine

Formats

Check Status Register (MCSTS)
Descriptions . .
.
.
.
.
.
.
.
.
.
.
System Identification (SID) Regis
ter Bit
Field Descriptions .
.
.
.
.
.
Revision Register 1 (REVR1) Bit Fie
ld
Descriptions .
.
.
.
.
.
.
.
.
.
.
.
..
Revision Register 2 (REVR2) Bit Field
Descriptions .
.
.
.
.
.
.
.
.
.
.
.
..

Bit

Parity

Generator/Checker

Descriptions

2-3

2-10

for

2-10

PAR<3,1>

2-10

B-Side

Control.

Port

Control.

Conditions

E_SHFT<4:0>

Control

ALUCIK1:0>

Source

(EBER).

Control

Signal

Port

Error Register

(PAR)

A-Side

Keepgoing

the

EBox

.
the

Parity

ALU

Carry-In

2-13

File

(RGF)

Address

File

(RGF)

Allocation

Signal

Descriptions,

2-17

Descriptions

2-20

Slow

Data

Program

File

E_VAWRT

and

Multiplexer
PC

(SDF)

Counter

Descriptions

2-13

.
I

Data

2—-14

Cache

Data

2—-15

CDS

Output

2-16

ALU

First

2-17

ALU

Second

Subsystem

Signal

Selection

Store

(CDBF)
(CDS)

(ALF)

Signal

Multiplexer

2-30
Description.

for

Each

Slice

Descriptions

Signal

Description.

Control

Signal

(ALS)

Multiplexer
Half

2-16

Input

Buffer

Half

Control

Input Selection.

Signals

Cache

APORT<7:6>

Multiplexer

Select

(PC)

Signal

Descriptions.

2-34
2-38

2-40
2-45
2-48

2-18

A-Side

2-19

Select

(ASEL)

Input

B-Side

Control

(BSEL)

Signals

Input

2-49

2-20

Select

Keepgoing/Stall

Control

Signals

Conditions

2-49

EALU<5:0>

Control

the

2-21

Field

Main

2-49

ALU.

2-50

(SHF) MCA Logic Functions. . . « « ¢ «
ESHFTSEL Selection of a Result Output

o«

&
=

shift Count Bus Signals and Source

ESHFT<4:0> Field Selection of Shifter
o

PfiDVQYQ1OHQ— et A

(INCR).

G<1:0> Guard Bit Input Selection .
Round Bit R<1:0> Input Selection .
SALU and XALU Control Signals

.
.

.«
.

.
.

the

BUS.

EFPFORMAT<1:0> Field Control of Decimal
C+rvinag
Ul.—l—-l_lg

Data
A e A

to the

Shift

BUS

Count

Increment Multiplexer Data (INCD) Selection

to the Incrementer

Sticky Bit Logic Input and Test Selection.

from the Microcode

EPEFUNC Field Selection of PEN Functions .
Priority Encoder (PE) Results Passed

ESXALUFN Field Control of the SALU Functions .
Resulting Sign of the Fraction . . . . . . .
SALU Selection of the APORT and BPORT Inputs

&
.

A-Latched Condition Code Inputs to the Branch

MultipleXer.

FUNCLEIONS.

o«

XALU Functions with E SXALUFN<5:3> Equal
to

000

¢«

.«

000

&«

o«

Inputs Passed to M3

XALU Functions with ESXALUFN<5 3> Not Equal
o

.«

M3 Inputs Passed to the Adder B-side .

XALU Condition Code

Tests

(XALUCC)

M2 Outputs to M6 or the XREG . . .+
M2 Data Passed to the BP Bus by M6

«
.

T I\TT
TM
1
o~
1
(W
E MULDIV Field Con t L
MULT Logic Signal Po rt

CACHE BOX LOGIC

CHAPTER

INTRODUCTION

L]
.

«
.

.+
.

=
.

o«

¢«

o«

Quiescent Stat@.
«
v
Read CycCle v
o
Write CyclesS +

«
o

+
o

o
o

o«

PIBA

(CBOX)

The

hvinctinng

CBOX OPERATION
CBOX CYCleS.

[]

MUUT

1
Description.
Function

CACHE BOX SYSTEM DESCRIPTION
e

NN
DN

SECTION

~~ £
) 1.

from the Microcode

)

Multiplier/Divider (MULT) Control Signals

Microbranch Condition Code Description . .
ESXALUFN<5:3) Control of the General XALU

o«

[
[]

<N o

[]

CycCleS.

Refill

U Wi

L )

e
e

U W

.
L J

L]
.

1-9

¢«

o«

1-10

Cycle

¢«

DESCRIPTION.

MCA

BYpPasS.

&«

¢«

DESCRIPTION.

o«

RAM

Match

RAM

Latch

SUBSYSTEMS
¢

Cache

Data

Cache

Tag

Cache

Match

Cache

Control

Path
MCA.

Number

Logic.

¢«

MCA.

.
.

¢«

o«

MCA.

¢«

DESCRIPTION.

MCA.

SUBSYSTEMS

Interface.

v
v

NMI

Address/Data

S1icCeS.

¢«

NMI

Out

¢«

Control.

NMI

o«

NMI

Arbitration/Acknowledgment

CBox

Control

NMI

Registers

[}

FIGURES

CBOX

CyCle

Buffer

Address

Match

Write

Sequence

MCA

Block

Fields

Diagram.

¢«

Diagram

Simplified

Block

.«

Diagram

PABH

MCA

~--

Simplified

Block

Diagram

PABL

Block

Diagram

MCA

Simplified

Latch

Logic

Latch

Bit

Routing

Refill

Latch

Bit

Routing

Block

NMI

Interface

NMI

Address/Data

NMI

2-14

Control

2-15

NMI

Diagram.

Out

Store

Block

+
--

Block

xiii

Cycle

MCA
o

Reference

«
--

Simplified

Microword
--

.«

Diagram

Slices

Control
Control

Diagram.

Diagram

Cache

[

Diagramo

Timingo

Translation

Virtual

Block
Do

BlOCk

DONNDNDNDDODDNDDNDNDDNDND
|
=0
00 J0 U
W IN

e
0o

Title

CBOX

Format

Simplified
o

Block

Diagram.

Diagram

Diagram.

1-10
1-11

Buffer
¢

e
*

DESCRIPTION

Latch

Cache.

S
T
W

NMI

¢«

SUBSYSTEMS

CBOX

Translation

CBOX

>
[]
*
*

[}

NN NNONNNOMNODNNNNDNONNODNONNNDNDNDNN
NN

CBOX
e

FUNCTIONAL

Stalls.

CHAPTER
WWWWWWWNNNNNNRN
e

Operation

Invalidate
CBox

NMI

Arbitration/Acknowledgment

Control

2-49
2-17

Timeout

2-18

CBox NMI Registers -- Location
Cache Register -- Bit Format .
Cache Error Register Byte 2 -Cache Error Register Byte 1 -Cache Error Register Byte 0 -NMI Fault/Status Register Byte

2-19
2-20
2-21
2-22

2-23

Flow

Format

NMI

Fault/Status

Bit

Format

2-52
2-53

Byte

2-56
2-57

2-60

2-67
2-69

2-55

ID Register -- Bit Format . . .
Control Register -- Bit Format.

Bit

2-51

Diagram . .
. . . . . .
Bit Format.
Bit Format.
Bit Format.
1 --

o«

.
.
.
.

Format

NMI Error Address Register -- Bit Format
NMI Silo Byte 2 -- Bit Format. . . . . .
NMI Silo Byte 1 -- Bit Format. . . . . .
NMI Silo Byte 0 -- Bit Format. . . . . .
Cache TAG Initialization Register -Diagnostic
Diagnostic

Bit

Diagram.

TABLES

Title
CBOX Cycles ®

PROTection

Field

<03:00>

Coding

Allowed.

«
.

+
.

&
.

Descriptions

and Access
o

«
.

.«

TB Match MCA Operation Coding. . «
Cache Register - Bit Descriptions.
Cache Error Register - Byte 2 Bit
Descriptions . « o« ¢« ¢ ¢
o« « « o ¢
Cache Error Register
Byte 1 Bit
.

Cache Error Register
Byte 0 Bit
Descriptions . . * - L L
*
®
®
L]
NMI Fault/Status Register Byte 1 -

Bit

Descrlptlons

NMI

Descriptions

NMI

Fault/Status
.«

- Bit

. .
. .
. .
Bit

.
.
.

Error Address

Descriptions

o«

¢«

-o

Bit
o

NMI Silo Byte 2 -- Bit Descriptions.
NMI Silo Byte 1 -- Bit Descriptions.
NMI Silo Byte 0 -- Bit Descriptions.
Cache TAG Initialization Register -DesCriptions

.« ¢« ¢
¢ ¢« o o o
o o o o o o
Diagnostic ID Register —-- Bit Descriptions
Diagnostic Contrcl Register -- Bit
Descriptions
L

X1iv

2-61

2-63
2-65

2-66

2-68

1.1

MANUAL

1.2

SCOPE

MANUAL

ORGANIZATION.

e
o

DOCUMENTATION.

DESCRIPTION

o«

1.5

PHYSICAL

1.6

FUNCTIONAL

1.6.1

Console

1.6.2

Subsystem.

Central

Processing

Unit.

Instruction

Box.

Module

(MBox).

Logic

1-23

1-24

Cache

1.6.3

Clock

1.6.4

Memory

1.6.4.1

Memory

1.6.4.2

MAR4

1.6.5

Memory

System

1.6.5.1
1.6.5.2

1.6.5.3

Control

VAX

8800

VAX

Bus

VAX

1.6.7

Power

Bus

Memory

Bus

and

1-25

1-27

1-29

Adapters

1-30

I/O

(NMI)
.

(VAXBI)

(VBus).

Interconnect

1-25
1-25

Interconnect

Visibility

1.6.6

Array.

Buses

1.6.2.3

Box.

Execution

1.6.2.1

1.6.2.2

SYSTEM

1.3
1.4

e pd

INTRODUCTION

OVERVIEW

e b

SYSTEM

I
JW W

CHAPTER

AND

INTRODUCTION

NN i
— O O WO W

SECTION

System

Complex

876

Controller

NBox

1-33

1.6.7.2

Power

1-34

1.6.7.3

Port

Module

1-34

1-35

Environmental

N =

Module.
.

CONTROL

COMPONENTS.

Hardware

SOFTWARE

Program.

Special
N

[]

Unit.

Control

Multiple

Program

.
.
.
.
Features

Command Streams .
Transfer Program.
.
.
.
Logical Block Server Program

Interface

(CsM).

File

Real-Time

CONSOLE

SUPPORT

Console
CSM

1-35

CONTROL

Control

=W
N

[]

Monitoring

Backup

Software
CONSOLE

W N~

e
o

o
¢

&
&

R R WWWWWWWN
NN

SYSTEM

GENERAL.

NN NNONNNNODNNDNODNONNDNDND

CHAPTER

Battery

Data

Console

Driver

MICROCODE

Support

Microcode

Structure.

Transfers/Protocol.

Support

Microcode

Entry

Points

NN AN
U
D e e

1.6.7.5

Supplies.

TYYYYY
|

1.6.7.4

Conditioner.

Power

DN RNNND
N NN
|
I

1.6.7.1

o
s
o

o
o
o

o
=
&

Command Validity
Saving Conscle Stat
Console Commands .« « «

Power

Fail

o«

.«

o«

+«

Functionalitv.
OperatioN. « «

«
«

«
o«

«
o

¢
o

«
o

o«
o

¢
o

o
o

Microcode Control.

(GWYC)

(UBRS).

Microbranch Siices

l——l

=
RO b

MicrotrapS

o
¢«
«

¢
«
¢«

o
«
«

&
.
.

«
.
.

¢
.
.

¢
«
.

o
.+
«

o
«
«

AdAressSeS.

.«

Micromatch . . «
Stop on Match.
Trap on Match.

Pipelining

MEMORY ADDRESSING AND READ/WRITE OPERATIONS.
Layout

Format

o«

Addresses

Table

Entry

Cache Operation. . «
Translation Buffer

«
.

+
.

«
.

o
.

«
«

=«
«

o«

Interface.

Page

Cach€.

NMI

Xvi

(UTRP)

Microtrap

Gateway Control

b
uwwwtiowwwwwww
TR N R
P |

Interrupt and Processor Register
Condition Code and Branch (CCBR)

Physical

[]

[N
R
N~

W W N
BB

Structure.

&«

U OODWOHOOASOUTUNE
WWWLWW N

Address Translation.

[]

SYSTEM OPERATION

Virtual

O Wi+

BW N NDNDDNDDNDN

Wwwwwwwwwwl

Microcode Characteristics.

o
o
.

[]

|
|
[
el el el B B

ONn

\_1

POWEYdOWN.:
Restart

Power

L
e

Dlsplaying the Logfile
17
Logical Terminals/Logt ile Integr:
Saving the Logfile . . . . . . .
POWER-UP/DOWN SEQUENCING . . . « . =

Warm

Prompts

W wwwww

[]

Console Command Language Display

INTRODUCTION
«
MICROCODE.

.
.

Local Display During Remote Operation.

System Logfile

CHAPTER

«
o

.+
o

.
o

o
o
o

Executing Console Commands
Console/Operator Display . .

¢«
o
¢

bR wwWwwWwiN
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e

.
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e
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.

o
o
¢

OPERATOR/CONSOLE INTERACTION
Console State Bits « ¢ « o

W N

¢«

ddd~lwoOoooaooooaooaosaotut
U

\S
NNNMNNMNNOMNNNNDODNNDNDNMNDNDDDNDNDDD [V

¢
o
«

«
o
+

«
o
«

OPERATIONAL MODES.
Console Mode « «
Program Mode . .«

o Oy
U

[

[]

N
w

Priority

Bits

3-19

3-20

Enable

Interrupts.

the

Interrupt.

3-20

Levels.

System

Control

Pagination

3-20

Block

Fo rmat

3-20
3-21

3-23

VAXBI

Direct

3-23

DIAGNOSTICS.

¢«

o«

¢«

o«

Error

Customer
Menu

Module

Diagnostics

SYSTEM

Placement

SO
O

Diagnostics
.

Verification

Messages

Mode

Mode.

Remote

Runnable

Auto-Test

Information

Error

S
T

and

Commands

S
O

S
N

Selftest

WWWH

Microdiagnostics

Macrodiagnostics

3-25

Status

3-25

AIDS

Micromonitor

3-23
3~-24

Devices.

MAINTENANCE

Exception.

Exceptions.,

AND

INTRODUCTION

CSM

GENERAL.

Console

Module

Key

Test.

Module

4-10

Placement

4-12

Power

Monitoring/Error

Default

DIAGNOSTIC

Connected

oo CO

Check

Types

Machine

—

Node

Format

NN
1

SCB

W N

{SCB)

W W

3-19

Address

W W

3-17

Devices

SCB

N =~

b WD
N

Offsetable

*«

WNNDN

EXCEPTIONS.

POWER/ENVIRONMENTAL

Mode

Operational
Voltage

Machine

Error

Margining.

MAINTENANCE
=

Significant

Interrupt

Servicing

o
o
o
*

[]

.
Selection

—

L]
.

DWW W

@
*

b
B

B
b

S
N
O
S
O
SO
.

- Y LSO S
Y
T

S
-

Y -t St T

o
¢«

> S

ol
.

AND

Types

Nk EREDWLWWLWWWWWWWWWWN

Transaction

NMI

CHAPTER

Operations.

Address

Servicing.

[]

Device

INTERRUPTS

WWWWwWwWwWwwwwwwwwwww

Read/Write

AIDS

Check

Reporting

Reporting
.
.

Logout

Xxvii

4-12
4-13
4-13

4-14

4-16

Stack

4-16

FIGURES

VAX 8800 System Major Component Locations
(Rear View).

&«

o«

SUDSYSEEM.

«
.

Simplified Block Diagram of Single CPU . .
Simplified Block Diagram of the CPU IBox .

Simplified Block Diagram of the CPU Execution

Box.

Slmpllfled Block Diagram of the CBox .«

Cardcage Module Layocut (Front View). . . Simplified Block Diagram of the VAX 8800 System.
Simplified Block Diagram of the Conso le
e

o
O i

Page

Title

.
.

Simplified Block Diagram of the Clock Modui@ . .
Simplified Block Diagram of the MBox .

o«

o
.«

«
o

=
-

Simplified Block Diagram of the VAX 8800 Memory
o

(Maximum Configuration). . « «
I1/0 Interconnect and Adapters.

«
.

¢
.

o
.

o
«

o«
«

Interconnect

Simplified Diagram of VAX Bus Interconnept
NMI-to-VAXBI Adapter

Simplified Block Diagram of the Power
System CompleX

.«

VAX 8800 System Hardware and Software Control
COmMPONENES

o«

&«

Simplified Pipelining. . « «
Virtual Address Space Layout

«
.

«
«

o
«

«
«

¢
«

o
«

«
«

«
o+

=
=

Console Operational Modes.

Local/Remote Display Character Flow.

MAP Enable Register Bit Configuration. . .
Page Table Entry Bit Configuration . « « «
System Space Virtual-to- Physical Address

.
+

.
«

.
.

Format

Virtual Address

Process Space | r

Address Translation.e

[

«w

Translation.

|..p.

Physical Address Space Layout.

on)

o«

.«

Virt: al-to-Physical
1

Address Translation. . « ¢
CBox Functional Components

¢
.

o
.«

¢
«

o
«

o
¢

o
o

o
¢

o
o

¢«

=«

NMI Address Bit Significance

NBI I/0 Adapter SCB Vector Offset Format .

xviii

Process Space (Pl Region) Virtual-to-Physical
NMI Address Selection.

=«

3-14
3-15

3-18

3-19
3-24

Testing.

Keying

Module

Key

Margin

Enable

Machine

Check

Test

O QO ~J O U

Error

Margin

Logout

4-2

Dlagram.

4-11

.
.
.
.
.
Registers

4-12

4-15

Stack

4-17

4-18

4-19

4-20

NMI

Interrupt
Fault

NMI

Error

U
W

Connections.

and

Block

bt =

Error

N
i
e

Error

S110

IBox

NMI

ot bt

Slmpllfled

EBox

NMI

ST ST S

CBox

Test

Bottom-Up

Module

Cache

Control

Summary.

Data@.

o«

4-21

Address

Machine

¢«

Check

Status

4-22

Revision

1/2

Registers

4-22

TABLES

Technical
Related
VAX

8800

Cabinet
Power

VAX

Description
System

Module

Supply

8800

Organization.

Characteristics

Identification.

Functional

Units/Data

Bus

Operations

Descriptions.

Adapters

Command

NMI

Function

Optional
NBIA

Clocks.

MCL

VAXBI

Physical

Processor

Descriptions
System

Manual

Documentation.

VAX

Bus

Interconnect

Registers

NBIB

RegiSters

NBox

Modules

¢«

Hardware

Major

and

Software

Sections

Console

Bit

Support

Examples

Component

CSM

Code

Microcode

Description.

Entry

Points

Console

Command

Overview

Console

Command

Language

Prompts

Sequence

.
.

Module
VAX
Page

Power

8800

System

Table

Translation
Hardware

Supply

Microtraps

Entry

Bit

Buffer

Interrupt

System

Control

Machine

Check

Turn-On
.

Description

Field

Priority

Block

Description

Page

Exception

X1ix

Level

(000-~1FF)

Examples

Assignments.

Microcode Error
Macrodiagnostic

¢«

.«

¢«

.
«

EXAMPLES

Title

Sample Microdiagnostic
Sample Microdiagnostic

Display Output.
Error Display .

EMM

Warning

Message€.

SYSTEM

BUS

CHAPTER

MEMORY

INTERCONNECT

o«

AND TIMING

.«

JOY Ui

NMI

ADDRESS

SPACE.

.«

TRANSACTIONS.

INTERRUPTS

READ/WRITE

.«

BUS

ARBITRATION.,
.

&«

.
o

NMI

Faults
.

=«

INTERCONNECT

VAX BUS

¢«

o«

VAXBI

SIGNALS

AND

TIMING

VAXBI

ADDRESS

SPACE.

FUNCTIONS.

(VAXBI)

BASIC

Address
BASIC

W
N -

I/0 Address

Memory

¢«

Levels.
¢ «
«
o

ERRORS

NMI Interrupt Priority
Device InterruptS.
«
«

INTRODUCTION

INTERLOCKED OPERATIONS

NMI

oYUt
TN U Uk b s
W

FUNCTIONS

(NMI)

SIGNALS

o
s
o
*

NMI

CHAPTER

BASIC

(o)

[]

el e

INTRODUCTION

NNONNONDNDNNONNDNNDNDDMDNDNDDNDND

o«

SUMMARY

SECTION

Address

¢«

Space

.«

SpacCe.

o«

Selection.

¢«

o«

FORMAT

o«
.

o
.

«
.

&
.

VAXBI

TRANSACTION

Command/Address Cycle. . ¢«
Embedded Arbitration Cycle

«
.

Data

¢«

BUS Parity . o« « o o
o
READ/WRITE TRANSACTIONS.
Write Data Cycles.
.
.

o
.
.

o
«
«

o
+
.

Read

Cycles.

Data

¢«

Cycles

Nonexistent

¢«

.«

Addresses.

+«

CSM

(IS ST

Diagnostic

for Use with

TEMP Register Addresses

v«

¢«

o«

TRANSACTIONS

INVALIDATE

TRANSACTIONS.

INTERRUPT

OPERATION

(INTR,

IDENT,

AND

(INTR)

Transactions.

(IDENT)

Transactions.

Interprocessor

Interrupt

Transaction.

¢«

TRANSACTIONS.

v
v

2.10

STOP

2.11

BUS

ARBITRATION

2.11.1

Bus

AND

Requests

(IPINTR)

CONTROL.

2.11.2

Arbitration

Modes.,

2.11.3

Arbitration

2.11.4

Control.

Extending ‘a.Transaction.,
Special Mode Functions .

ERRORS

Checking.

2.12.1

Parity

2.12.2

Transmit Check

2,12.3

Protocol

VISIBILITY

Checking.

BUS

INTRODUCTION
v

BASIC

Detection

(VBUS)
v

FUNCTIONS.

v
v

VBUS

SIGNALS
.

VBUS

REGISTERS

.
v

MODULE

WWWWWwwWwwww

NV
UT U
W N

CHAPTER 3

Error

VBUS

CHANNEL

CIRCUITRY.

VAXBI

2.11.5
2.12

Minimum Configuration.,

Expanded

SUMMARY.

Configuration

VBUS ADDRESS/DATA

VBUS

CONSOLE

COMMANDS.

Memory

Interconnect

NMI

Timing

NMI

Signals.

NMI

Address

(NMI),

¢«

o«

Selection.

Transaction.

Types.

Space.

Bits

NMI Address
NMI

Address

Basic

NMI

Write

NMI

Read

W N

e T S T o B S SRS
|

FIGURES

Title

NMI

Write

IPINTR

Transaction

XX1i

Il Wwwwwww

S | [
CO NN~

Interrupt

el o

.. ..

TRANSACTIONS

N
NN

BROADCAST

Identify

o
o

W OO ~Jd O

Retries.

Stalls

NMI

Read

Basic
NMI

Transaction

NMI

TYPES

Arbitration

Arbitrator

Line

Operation

Detailed NMI Arbitration
MEMORY BUSY Timing .
«
«

.«

1-30

Timing.

1-33

1-36

(Typical)

1-37

«
«

Line Timing
«
o«
s
o
o
&

1-38

[

—

DNV NNODNDDNNDNDNDDNDN
[
[
=
O O~ OYUT
W N
N = O

1-42

2-15
2-16

VAX

Bus

Interconnect

(VAXBI)

Timing

.«

SpacC€.

VAXBTI

SignalsS.

Basic

VAXBI

AddressS

.«

o«

2-10

2-13

o
¢«
.
.

¢
¢
.
.

o
«
.
.

o
o«
.
.

o
&
.
.

VAXBI Node Register Space. . «
VAXBI Required Registers .
.
.
BIIC-Specific Device Registers
VAXBTI Read/Write Address Bits,

¢«

.
.

2-6

Basic VAXBI Transaction Format . . . . . .
VAXBI Write Transaction (Octaword Length).
VAXBI Read Transaction (Octaword Length)
.
VAXBI Broadcast (BDCST) Transaction
(Octaword Length).
.
¢
o«
¢
¢«
o ¢ ¢
o
o
o
VAXBI Invalidate (INVAL) Transaction . .
VAXBI Interrupt (INTR) Transaction . . .
VAXBI Identify (IDENT) Transaction .
. .
VAXBI Interprocessor Interrupt (IPINTR)

o
.
.
.

Transaction.

VAXBI STOP Transaction . .
«
¢
Bus Arbitration Request Lines.

o«
.

«
.

o
«

«
+

o
+

2-19

Arbitration

2-20

VAXBI

2-17
2-18

e WO
o

[

w
w
oV

State

CLK

Bus

o«

Diagram.

2-30

2-33
2-35

2-37

2-40

.«

2-42

and

VBus

Control

o«

.«

o«

¢ v ¢ o o
(Minimum

o«

VBus
VBus

Access Register . . .
Channel in CPU Module
°

MADIT
Li

2-25

2-27

Configuration)

2-22

o«

2-18

2-21

2-38

Lil

2-17

Control

uiiaiiticir

2-16

VBus

Ty
VDUD

2-14
2-15

(Example).

(VBus)

Module).

Configuration)
!

o«

Arbitration

Visibility
(on

2-2

A )

TABLES

Title

1-3

|
W N

1-10

NMI

Signal Descriptions. . . .« « ¢« « « .+ &
Registers in NBI and Memory Controller
Interrupt Priority Levels (IPLs) . . .

NMI

EYYOrS

1-43

NMI

et bt

Page

Glossary

1/0

NMI

TermS.

o«

1-21

1-39

W N

VBus

VAXBI

VBus

Directory

Descriptions

CHAPTER

INTRODUCTION

(Y S

et e

Descriptior
.

Invalid

Initialize

1-4).

(Refer

Power

(Refer
(Refer

FUNCTION

DESCRIPTION

GENERAL.

INTERFACE

Figure

[

Peripheral

Port

Control.

Line

1-19

1-21

(PPI).

Port

ECPTI

Registers

Data

Transfer

and

Status

Xxxiii

1-6)
1-7).

Interface

Port

Figure

(RTI).

(R I

1-3).

(Refer

Restart/Boot/Halt
Fail

SEQUENCE.

Figure

Registers

I
II\)I\JNI\'JNNI\)

Driver

POWER

(Refer

.
.
.
Program

Interface
8800

e B S

.
.
Server

|
el
S

Block

Program.

R S

Valid.

COMPONENTS.

TR A
O

SOFTWARE

S o WP = b

Description.

W
-

State

W N

Running/WCS Invalid

Running/WCS

Powerdown

Stopped/WCS

Clock

Ul
W

Clock

Programmable
o

State

EMM/Console

INTERACTION

Mode.

o
di I

8800

.
.

Powerup

REF ERENCES

Real-Time

Off.

Clock

.
AND
.

CONSOLE/VAX

8800

CONSOLE

NN
e = e

COMPONENTS

1/0.

Console

.
D

=W
N e

Power

Serial

3-1

COWVWVOVWWYWOYOWIOAIO
N A BN
N

Console

[]
o
*

[]

Power-Up

REAL-TIME

PURPOSE

CONSOLE/VAX

Logical

@
e

DNDNNDN
DDV

AND

Control

—
o
¢
Ld

SUBSYSTEM

PPI

OO0
W W W

FUNCTION

Port

Descriptions

(Excerpt)

DOCUMENTATION

e o

NDNDNDNODDND N

[

Bit

[]

GENERAL.

Figure

SUBSYSTEM

P
P
U
P
[]

ey S S

R e e

\l\JflO\O‘\O‘\O\(flU’IUTU'IU'IU'IWU'IU'IerND—'

CONSOLE

.
.

Signal

SECTION

CHAPTER

Control

VAX

Terms.

Descriptions.

N DO

Signal

l\lJl\.)

VBUS

Glossary
VAXBI

o
.
o
.
.
.
o
=
&

2-16
2-16
2-16
2-17
2-17
2-19
2=20
2-20
2-21

. o« « .
& e e e e
e e e e .
e e o .

223
2=23
2-24
2-24

o o ¢ o o o
. . . . . .
o o o + « «
. « « .« « «
(TRIC) MCA.
o . s e e .
o = « = = «
o o o o o o
o o ¢ o o o

2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.4.1
2.3.4.2
2.3.5
2.3.6

CONSOLE INTERFACE. o « o o o ¢ s o
Buffer Translate and Synchronize
Console Address Decode . « « « «
Console Sequencer (CSEQ MCA) . .
Terminal Register/Interval Clock
Program Mode . . « « « o + o o
Console Mode v ¢ o o o« o o« o s
Data Output MuX. « « « ¢ ¢ o o o
Control Registers. . « « « « o o

2.3.8
2.3.9
2.4
2.4.1 . -

Console Interrupt Generation .
e
‘Power Status . . . . . .
e e
TION
INTERAC
8800
E/VAX
CONSOL
¢
o
o
v
«
«
.
.
ization
Initial

2.4 1.2
2.4.1.3
2.,4.1.4
2:4.1.5
2.4.1.6
2.4.1.7
2.4.2
2.4.2.1
2.4.2.2
2.4.3
2.5
2.5.1
2.5.2
2.5.3

2-24
227
o
o
o
o
o
o
o
o
o
o
o
75
o
N.
POWELO
Console
2-28
.
.
.
e
Softwar
-Up
e-Power
Consol
Run
Loafi .and
lon.
Appllcat
Power
Sequenced
- Initialize Hardware. « « o« s o o & o o o o« o 2736
e e e e e e . 2-44
e i e
Test and Checkout.
e s e s e« . 2-46
e
e
,.;.~;
DRAMS._.
Load RAMS and
o o o o & » 2763
o
o
o
o
o
e
v
. VAX 8800 CPU CORLXOL
o« « o « « - 2764
«
¢
«
o+
«
.«
ETr.
Console SeQUENC
"
o o o o o o 2-68
o
o
o
¢
«
«
«
rs.
Control Registe
|
o o o o o o+ 2=70
o
o
o
o«
«
&
o
.«
Data Transfers . v
o o o o @ 2-73
o
«
TIMING
AND
CONSOLE/VAX 8800 CLOCKS
o o o o 2-73
o
o
o
o
s
s
o
o
«
One-MHZ ClOCK. o « o
e e e e 2775
e
e
e
s
e
e
e
e
e
e
Interval Clock
o« o o« o 2-78
o
o
o
oo
o
o
o
¢
o
&
o
v
CPU TimeOULS

2.3.7

2.4.1.1-.
BN

Visibility Bus Control . -« « +« & o o o o ¢ o o 2—-22

.
e
e
@

.
e
e
v

.
e
e
o

Turn ON_and. Monitor System Power/Reset
T& T
EMM, T

2.5.4

CHAPTER 3 DETAILED DESCRIPTION '
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
3.4.1
3.4.2
3.5

GENERAL. « « o o o o o o o o o .0 o o o o o o
" TERMINAL REGISTER INTERVAL CLOCK {TRIC). &« +
" CONSOLE SEQUENCER MCA (CSEQ) .« « & -4 o« « o «
Console Strobe Sequencer .« « « « « o« o o o o
Read Acknowledge. .« « o o o6 o o o o e o o
Console Write Sequencer. . .« « « + s o o o o
Control Store Load SeqQuencer . . « .«o« s o o
e o o o
CONSOLE/VAX 8800 REGISTER SUMMARY.
.
7).
3
Figure
to
Console Regigtérs (Refer
3-8)
Flgure
to.
er
ers(Ref
' VAX 8800 CPU Regist
o o o o o
" CONSOLE CABLING. . « « « « o ¢ oo

XX1iV

o
«
o
o
o
o
o
o
.
.
o«

3-1
3=1
379
3=9
3-9
o 3-9
= 3-9
3-17
. 3-17
. 3-24
o 3728

o
&+
«
o
o
o
o

o
»
«
o

Diagram

Operation

Power—Up

Sequenceo

o«

Subsystem

Functional

Format.

Block

Diagram

¢«

o«

Format.

¢«

Format.

¢«

PPI

Control

Format.

o«

ECPI

Mode

¢«

o«

ECPI

Mode

o«

ECPI

Command

Registers

.
o

Line

Port

TXDB,

and

Power-0On

Environmental
SEQUENCE

Console

Serial

EventS.

o«

2-27

Registers

Load/Run

2-28

Events.

2-30

Sequenced

2-32

Port

¢«

Registers.

.«

Transfer

Power

Application

Ports

Interconnect

Through

Ports

Data

Unbuffered

and
.

Path

RXDB

«
¢«
«
¢
Testing

&«

2-39

2-40

2—-26

Test

and

Checkout

VBus

Parity

Initialization.

Events

Enable

Bits

2=-27

2-41

2-42

¢«

.«

2-44

2-49

Address.

¢«

2-53

2-57

2—-28

DRAM

2-29

MNI

Control

Store

2-30

RAM

Simplified

2-31

RAM/DRAM

Initialization

Sequence

TXDB

Console/Interface

Logic

and

Control

Write

o
o
o
o
Buffered

Hardware

2—-32

.
.
.
Test of

2—-24

2-33

.
.
Testing

.
.
.
.
Loopback

2-25

Reset

Test

Sequencer

Loopback

Console

Address

Events

Loopback

Software

Loopback

and

Path
Data

Data

Through

Module

Power-Up

Console

Data

Console

Through

Interface

Data

Interconnect

Access

Console

Interface

Monitoring
v

Status

Sequence

Power-0On

Line

¢«

and
.

i
=

RegisSters.

Control

System

Data
DBCS

VN0

Serial
RXDB,

DN
NN

N NN

Port

[\
(o))

PPI

NN
|

oD
e ]

WNNOOWOWWN

PPI

VBus

Sequence.

W N - o

Procedure.

Control

}

Power-Fail

.
v

Powerdown

Port

PPI

Console

¢«

Console

2—-23

Initialize

Restart/Boot/Halt.

the

EMM/Console

Modes

[)

U W

Block

|
~] O

Simplified
Subsystem‘

NDNDNDNDNDNN
|
1
0 JO0
T
WN

b
b
e e

=
|

=z
O

FIGURES

Title

Block

EventsS.
Timing

.«

Dlagram

@«

¢«

2-51

2-56

Signals

2-64

2-65

o«
«

2-66

Out)

o«

2-67

2-34

Read

Sequence

(Setup).

2-35

Read

Sequence

(Data

XXV

2-36
2-37
2-38

2-39

Simplified
Simplified
Simplified
Data

Transfer

CPU.

Data

Transfer

Interface.

~NOY
U
WN

|
[I R
T
A
W BB

Diagram of
Diagram of
Diagram of

MHz

Control
.

Clock

Control
Control
Control

VAX
¢

Interface-to-VAX
o

8800
¢

CPU-toConsole

¢«

Generation

Interval Clock Registers Bit Conflguratlon
Interval Clock Simplified Block Diagram.
Simplified CPU Timeout . . . .
« o e
Clock Status and Timeout Reglster (CST)
VBus Control/Data Signals. . . .+ . . .
VBus

Logic

TRIC

MCA

Block

Simplified

TRIC

MCA

Block

Diagram.

TRIC MCA Body Drawing.
CSEQ MCA Block Diagram
CSEQ MCA Pin Layout.
.

«
.
«

«
«
o

«
«
o«

o«
«
o

o
o
o

o«
o
«

o
o
o

=
o«
&

CSEQ MCA Body Drawing.
Console RegisterS. . ¢«
VAX 8800 CPU Registers

«
«
.

«
o
«

«
o
o«

«
o
«

o«
o
«

o
=

Diagram.

Console

Diagram

Layout.

Subsystem Cabling

TABLES

~JOY
U > W N+

Title

PPI Port B Bit Description . . . . . .
PPI Port C bit Description .
.
.
.
PPI Control Register Bit Descrlptlon .
ECPI Mode 1 Register Bit Description .
ECPI Mode 2 Register Bit Description .
ECPI Command Register Bit Description.
Serial Line Port Data and Status Registers
Bit Description.
L
*
.
L
®
Ld
L4
L]
L
Cavi1al
Taina
DnAavr+
N
Transfer Registers
L LWV
S I 3 N &
id d 11N
P U NP g W WY
4

Configuration

TRIC

MCA

TRIC

MCA

Signal

U o+~

Bit

CSEQ MCA
CSEQ MCA
Console

)

Signal/Functions.

Initialization

ICCS

wwwww

Key

)

.«

Assignments

.
.

.«

Descriptions

Pin Assignments . .
Signal Descriptions

.
.

Cable

List

XXVi

¢«

876A

Power

Controller.

NBox

Power

Converter

(MPS)

Battery

Backup

Unit

Controller.

MPS

Modules

Flow

System.

DISTRIBUTION

Power

and

Controls

frd

Unit.,

POWER
AC

o«

Breakers.

.
Requirements.

Sources

INDICATORS.

STATUS

876A

Power
.

Bu1lt In

Built-In

Modular

Power

Test

Equipment.

Supply

Environmental

Regulators.

Monitoring

Console

FUNCTIONAL

Controller.

H7170

System

Breakers

Power

NBox

Cage

SPECIFICATIONS.

AND

ILM

and

Device.

Module.

DESCRIPTION

INTRODUCTION

POWER

BLOCK

SYSTEM

DIAGRAM

OPERATION

NBOX

Converter.

e
L4

[

=W
N

Controller.

s B

Power

W NN N NN

876A

H7170

Control
Box

Start-up

Interface

New

Power

Logic

Power

Module

(ILM)

Translator

Modular

Power

System

Battery

Backup

Unit

BBU

Control.

Environmental

Module
(MPS)

(BBU
.

Monitoring

XXvii

DWW

[

(Regulators)

Backup

Circuit

(CSP)
.

(NBT).
.

Model

H7231M)

Module

(EMM).

U U

Conditioner.

Electrical

Power

FAULT
U WD
-

o
.

HO O

W N~
U

*
.
[1]
W w W N

H7231 M.

CONFIGURATION

Controls

Module.

Port

POWER

876A

Air

NBox

Battery

MECHANICAL

R S =
|

N U

Monitoring

[]

System

[]

System

Power

Modular

HEH OO
U U

R W
i1

Ry N

t
—

W N

L]
[]

[

[]

Environmental

—

[]

—

U
L
»

T
e

il el e o e S S S S S
.

SIMPLIFIED

WWWwwwwwwwwwiN
-

COMPONENTS.

Cooling

ot
[]
*

INTRODUCTION

SYSTEM

CHAPTER
DN DNNDDNODNDNDNDNDNDNDND

DESCRIPTION

GENERAL

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|
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COMPLEX

CHAPTER

SYSTEM

—

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o

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Key Monitoring .« «
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BBU Control. «
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Breakers

Summary

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POWER SYSTEM

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INTRODUCTION

NBOX POWER CONVERTER ASSEMBLY.
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H7189

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Indicators.

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H7189 Functional
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Backplanes

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Environmental Monitoring Module. . .
8085A Microprocessor System. . « .«
Electric Key Monitor . . . « « o ¢
Regulator Control Circuits . . . «
Regulator On/Off Control Circuits.

.
«
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.
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Backplane.

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Panel .
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H7186 Main Board .
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SYSTEM POWER-UP FLOWCHART (FIGURE 2-5) . . . .
CONSOLE POWER-DOWN FLOWCHART (FIGURE 2-6). . .
POWER-DOWN/POWER INTERRUPT WITH BBU FLOWCHART
(FIGURE

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and

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3-53

3-55

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Lontrol

(H7231-M).

3-59

3-63

3-65

8800

System

Power

System

Block

VAX

8800

Diagram

(60

Power

System

Block

VAX

8800

Diagram

(50

CPU

Cabinet

Front

VAX

8800

CPU

Cabinet

Rear

Power

VAX

8800

View

Physical

Showing

Section

System

¢«

Power

NBox

Front-Panel

Indicators

for

VAX

8800

MPS

Backplane

Power

Receptacles

.
.
Location

Functional

Power

Regulators.

Block

Diagram.

View).

(Rear

Functional

Block

Power-Up

Power-Down

Flowchart.,

o
e

4
.

BBU

Block

with

Operation

BBU

Panels

and

876A

Power

Controller

NBox

System

Rear

Block

Interconnect

Flowchart

Flowchart.

Diagram

Front

Flowchart.

Interrupt

from

Dlagram

Powerdown/Power

System

Power

Panel.

Subsystem

System

Powerup

Indicators.

Modular

o
Front

Configuration

Backup

Hz).

View

Indicators

Diagram.

Hz).
.

Circuit

System

View)

the

(Front

View.

Diagram

Controller

Front-Panel

Battery

Layout

Block

Power

876A

3-58

8800

EMM

3-58

VAX

EMM

Circuit

VAX

876A

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FIGURES

Block

WWwWwWwWwWwwwwwwwwww

Backup

Tests.

Unit

SUBSYSTEM.

Diagram.

—

Circuits

Circuit.

Voltage

Backup

Flow

COOLING

Sensing

Measuring

Title

]
el

Temperature

Voltage

.
.

Dlagram.

o«

ILM

Board

Signals

NBT

Board

Signals

MPS

Regulator

Configuration.

o«

H7186

Block

Diagram.

H7180

Block

Diagram.

H7189

Block

Diagram.

BITE

Indicators.

Organization
MPS

the

Power

Systmm

Backplane.

Backplane

Diagram.

Cirvcuit.

MPS

3-15

EMM

Block

3-16

Voltage

Margining

XX1X

AC/DC LO Timing Diagram. « «
AC/DC LO Circult . « o o ¢ ¢
Temperature Sensing Circuit.
Voltage Measuring Circuit. .
Voltage Measuring Technique.

3-17
3-18

3-19
3-20

3-21

BBU Block

Diagram.

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Air Flow Sensing Circuit

3-24

Air

-22

3-23

Title

Flow

Path.

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3-51
3-54

3-56
3-57
3-62
3-64

3-66

Distribution.

VAX 8800 Circuit Breakers. . . ¢« « ¢
H7170 Status Indicators. . .« « « « «
o«
MPS Regulator Indicators . . .
EMM Magnetic Status Indicator Codes.

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Functions

Side—-Panel Components and Interconnects.
Main Board Circuits and Interconnects.
Side Panel Components and Interconnects.
Main PCB Circuits and Interconnects.

H7189

Module

H7189

Outputs.

H7189

Module

H7189

Module

Interconnects.

and

Circuits
Circuits

and

TInterconnects

.«

300-V Buses, Power Sources, and Loads.
Battery Backup Interface Signals . . .

.
.

MPS

Connectors

Regulator

-«

MODULE

INTRODUCTION

W DN

CHAPTER

BASIC

CLOCK

STALLS

OPERATION,

BASIC

COMPONENTS

AND TIMING

(BY CONSOLE)

CLOCK

STATUS

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CLOCK CONTROL

TM=

MPS

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H7186
H7186
H7180
H7180
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CSP Voltages

VAX

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876A AC Power

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Voltage Regulators . . .
System Circuit Breakers.

NBOX

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Modules Using CSP Bias Voltages.

SECTION

T
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= b

Components.

Power
NBox

876A Power

et b

W N

TABLES

CHAPTER
2.1

FUNCTIONAL
DETAILED

DESCRIPTION

BLCCK

DIAGRAM

‘Phase

2-1

Logic.

2-2

Distribution

Clock

2.1.4

Control

Clock

.«

2.1.3

Generator.

Circuits.

2=2

2-2

2.1.1

Oscillator

2.1.2

2.2

CLOCK

2.3

SYSTEM

2.3.1

GENERATOR

CLOCK

Changing
SYSTEM

2.4.1

INITIALIZATION

PERIOD

Phase-Locked

2.3.2
2.4

CLOCK

2=7

Operation.

¢+

2-8

2-11

2-13

Period.

START/STOP/BURST

CONTROL

2.4.,2

Starting

the

Stopping

2.4.3

the

Clocks

Stopping

the

Unconditionally.

Clocks

Oy
U

.
L]

NN NN

(SN0
2 I SNV

Generation
4.

Bursting

Clocks.

the

CLOCK

.
.

Clocks

the
the

COMMANDS

2-12

Sync

2-16
e

CONTROL.

Y
2-18

2-19

2-20

CLK.

AND

2-8

2-13

Mlcromatch/Scope

GENERATION

CONSOLE

Single-Stepping
SLOW

Clocks.,

Single-Stepping

2-1

CONTROL.,

Loop

Clock

FIGURES

No.

1-1

Title

Page

Clock
on

Generator

Clock

(and

Module.

1-2

System

Clock

1-3

Clock

Control

Timing

1-4

Burst

Count

1-5

Clock

Period

1-6

Clock/Timeout

Console

Interface)

Diagram.

1-4

1-8

1-9

o«

2-3

C1rcu1try

o«

2-9

.
Register.,
Status

2-1

Clock

2-2

Simplified

Clock

2-3

Frequency

Simplified

Clock

2-4

LOglC
.
.
.
.
.
Start/Stop/Burst

Start/Stop/Burst

2-5
2-6

2~7

Generator

(Detailed

Control

Micromatch

Block

Diagram)

Control

Timing

Clock

Timing

Diagram.

XXX1

1 -10

Control

2-14

Diagram.

2-15

and Scope Sync Timing Diagram
Single-Stepping B CLK Timing Diagram .
.

Slow

1=2

2-16

2-18

2=19

TABLES

Title
.

System Clocks.

Clock Control
Descriptions

<«

.«

Descriptions.

Clock

Generator

Inputs

.«

Clock

Generator

Outputs.

.«

Clock

Console

.«

Commands

Signals

Used

MBox

o«

Sort-of-Write

Bus

Cycles

.
.

Longword

Bus

Cycles

(Table

1-3)

Bus

Write

Octaword

Bus

Cycles
Cycles

(Table
(Table

1-6)

Longword

Bus

Cycles

(Table

[]

Read

Octaword

Bus

Cycles

(Table

Read

Hexword

Controller

T
T

Cycles

(MCL).

1-7 )
1-8)

(Table

1-14

1-16

Normal

Write

1-20

Read

1-22

1-25

Board

1-29

Sequence

Command/Address

Memory

Bus

1-5).

Read

OOV
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BB DS DD W

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the

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T
S
T
T
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Masked

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MAR4

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MEMORY

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CONTROLLER

B0
N

1-32

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1-33

2-1).

(MCL)

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Cycle.

Cycle(s).

First

Read

Data

Read

Data

Cycles.

o«

Memory

Busy.

o«

Single-Bit

Error

Correction

NMI

Interrupt.

NMI

Masked

CSR

Write

Reads.

(DAD)

MCAS.

.«

DAD

POrtS.

Writes

NMI

Reads

from

Writes

Memory.

Requiring

Correction

Decode

Addressing.

Reading
CSR

Reads

CSR1
to

Field

the

.
.
.«
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.
RAM

NMI

.
o

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=

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the

(FUNK)

Function

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Initially

Memory

Error-Free

RAM

During

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1-30

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"Next"

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Command/Address

Write

FUNCTION
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and

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Command/Address

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FUNCTIONS
OVERVIEW.

Error

MBOX

o
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MANUAL

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SYSTEM

MEMORY

S RSy e

SECTION

MCA.,

xxxiii

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Write

Block
Write

Unlock

W
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Longword
Longword

Write
Write

Octaword

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to Memory
to CSR. .

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Immediately

MCIL Waits

MRM

Hold

for

Command

Data

Parity

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2-6).

.
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Parity

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2-7)

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Parity

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(Figure

2-7).

Fault Detect (Figure 28).
NMI ID/Mask (Figure 2-9) .

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o

o«

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Octaword Read (Figure 2 11)
c

o«

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Read

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the

Read

Does

Bus
.

Not

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the

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Back-to-Back

Read.

.
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2-46

o«

2-49

2-47

(Figure

with

the

Get

Reads

Octaword

Right

Get

not

Longword

Back-to-Back
Function.

CSRO

2—-49

CSRs
.

the

NMI.

Force One Cycle (Figure 2-6)
ARBITRATION/ID (ARID) MCA.
.
¢

Interrupts

Gets

the

(V)]

(03]
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(Figure 2-4). .
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2-49

2-14).

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Memory

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Memory

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2.4.5.5

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Memory

Confirmation

2.4.5.4

NMI

Longword

NMI

Quadword

Another

NNNNNDNDNDNDODN

FUNCEioN.

Write
Write

Longword

CSRs

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Lock=Timeout Counter
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b

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Read Lock Function .« « ¢
¢

OVERVIEW

MDB

Address
N

(Figure
Clock

Control

(Figure
In

2-49

(Figure

2-15)

2-16)

¢«

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2-54

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2-54

XXXiv

2-50

OO0
WM

In.

MDB

Data

Qut

Reads.

MEMORY

DATA

W N

MEMORY

DATA

2-56

Operation

2-58

o«

2-59

(MDB)

Port.

(Figure

2-17)

o«

2-62

.«

2-62

.«

BUFFER

CONTROL

into

Empty.
Octaword

the

Write

(MDBC)

MDB.

Write

With

Masked

Write

With

Unloading

Data

From

the

With

and

.«

Write

o«

.«

Wlth

Y Buffer

Data

2-63
.

MCA.

Masked

2—-64

2-66
2-67

Already

Errors.

2-76

Error.

2-78

Correctable

Uncorrectable

MDB.,

2-74

Error

2-79

2-80

.«

2-82

General.

¢«

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..
.

Select

2-59
2-61

Octaword

Out

2-57

X or

2-57
.

Normal

Buffers

Ul
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With

Write

Data

the

Blts

Port

LOGiC.

2-54

Port

Write

2-80

Logic

General.

2-83

Detailed

2-83

2—-84

Error,

Clocks
CHECK

Write

(DCHK)

Decode

RAM,

MCA

Generate.

Check.

Error

Status

.
.
.
e
(Figure 2- 28)

o«

Serializer

and

Diagnostic

Mode

and

CSR2.

Clocks

OVERVIEW

Board

(Figure

Select

2-99

2-104

Field

Selection.

Octaword

CSR
MSC

2-105

«v

2-106

.«

2-106

2-107

SEQUENCE

Buffer

CMD

Writes.

Buffer

Parity

Cycle(s)

READS.

AMRM

and

2-98

Load.

Writes.

Read-Data
Masked

2-95

Command

Error

Address

Write-Data

2-89

2-92

2-28)

NAB

Internal

2-89

2-33)

MDB

2-87
2-87

Error

NAB

W N~

2-54
s

—

U
®

BUFFER

CSR

—
D

Port

Reset

[]

Read

Syndrome

Operation.

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Data

Parity.

MRM

Read

DATA

Data

Masked

Data

Normal

o«

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[

[]

RN NONNODNENNDNONNONNNDNDNDNNDNDND
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and

Out.

Write-Enable

Masked

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NDNDNDNDNDND
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Data

Address

NN
N

MDB
MDB

CONTROL

Control

BUSY

PROC

e
(MSC)

(Figure

2-108

MCA)

2-35)

2-108
.

2-109

Operation

START

2-112

2-113

REQ.

XXXV

2-109

N
=

¢«

¢
e

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.
.

o
o
o

o
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o
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(Figure 2-40)

Address

.«

Incrementation

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Starting Address

Initial

Write Machine. « ¢«
Write Command BitsS

.
.
.

BMSC PRE CMD DONE.,
BMSC PRE MASK DONE
Command Parity . . .

MEMORY SEQUENCE CONTROL 1
Mask Store

(MSCl) MCA .

2-45)

(Figure

o
¢
o

¢
¢
e

¢
¢

¢«
+
.

.
.

o
o
o

¢
o
o

.
.

Masked-Write Logic (Figure 2-43)
Command Done Logic (Figure 2-44)

o
o

¢
o

o
¢

«
o

o
o

o
«

Select Out Buffer Control (Figure 2 46).
Read Buffer Control (Figure 2-47). . . .
MDB Address I/O Select Logic (Figure 2-48)
Error Address Pointer.
BMRM INVERT ADDR4. . .

.
.

.«

o
o

¢
o

o«
e

«
.

«
«

«
.

MDB Address In Select Bits .
MDB Address Out Select Bits.

=
=

¢«
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MEMORY ARRAY SEQUENCE CONTROL (MASC) MCA
2 49)

(Flgure

[]

Parity

Force

Board Number

Error

No Command.

MASC

EmPpLY

Board Select

W N

@
o
e

W WD NN

b
N
=

118

120

2—

120
124

2—

124

126

2 -

126

2=-

128

129

131

2 -

131

22—

133

134

137

139

2—-

142

2 -

143

2—

143

143
143

145

.«

145
146

(BMAS BD SELK2:0>)}.

.«

o
.
«
«

&
.
.
o«

2=-

146

.
.
=«

147

2 -

149

SERIAL

RD.

BMRM

SERIAL RDK2:0>.

AMRM

CSR WRITE

ARCS

FORCE CMD ACPT.

¢«

AMRM MPR DATA SEL.
BMRM FAKE CMD ACPT

149

2—

151

2—

151

«
¢

o
o

2- 52)

o
s
o

o
o

Enable.

¢«

Select

¢
o

Board

o
o

XXXV1

1AL

140

+
¢

.
&

SeleCct

z2—-

+
o

READ CMDKO>
READ CMDK1>

Board

(Figure

Board Select/Enable
N

118

2 -

Read Command Bits

B W
B

116

Valid (BMAS BD VALID). « « & ¢
READ CONTROL SEQUENCER (RCS) MCA
Power Control (Figure 2-50). .
CSR Control (Figure 2-51). « ¢

116

2 -

Command Accept (BMAS CMD ACPT) and Board

AMRM
BRCS

116

2 -

(BMAS BNUM<K2: 0>).

Send

2 -

.
.

Mask Address/Size Buffer (Figure 2-41)
Write Command Logic (Figure 2-42). . .
«
.«

113
113

o
o

¢
o

2- 38)

Command/Address Parity

*
L]

Command Channel. . «
Address/Size Channel

Starting Address Logic

O
e
[N

e
[]

[]

WWWWWwwWwwWwwwwwwwww

NN DNDDNDDNDNDND

Rl
e =

b
b
e
e et et b
b
bt bt b=

DN
N NN

[]

o
o

Size

2.11.1
2.11.2
2.11.3
2.11.4
2.11.4.1
2.11.4.2
2,11.5
2.11.6
2,12

o
o
o

o
o

«
o
.

«
«
.

2-36).
LOgiC.
Logic.

Command/Address/Slze Buffer (Flgure 2=-37)

2.11

MO NNDNONNOMNNMODNONDNNDNN

o
o
o«

(Figure
Probe
Error

N =~

o©o
&
&
[

e e
e
R
T
[

= O WOWOWONdI~JoaauundwWwWwWwidN

o
@&

OO0 O0OO0COOOOOOCOOO OO Oo

@&
e
®
*
[]

[]
®

[]

NNV NDNONNNNONNNDODNNNNONNNDDNDNDD

BNUM Probe Buffer and Error Logic

(Figure 2-52).

.
o

4—

2~ 151
2— 151
2- 153

2.13.5

Read

Data

2.13.5, 1

AMRM

DRIVE

2.13.5. 2

BMRM

2.13.6

RCS

1in

NAB

S5ignals

NEW

(Figure

DATA,

GATE.

Full/Empty

Status

z-52)

2-153

(Figure

2-52 )

2-153
2-154

2.13.6. 1

ARCS

FULL.

2.13.6. 2

BRCS

EMPTY

2-154

BACKUP

Loss

2.,14.2

Return

&
e
«

= G0 N

L]
*

Power.

2-156

MEMORY

BUS

Timing.

.
.
.
.
(Figures

OVERVIEW.,

Read

Operation
Operation

.
[]

L[ ]

DETAILED

LOogiC.

Banks

Cold

start
Bank

.«

Sequencing

3-34

3-36

3-38

3-39

Differences

Check

L]
[
[)
®
L)

.
L]
[

3-39

Selection

Array

Bank

3-41

Signals

3-41

3-42

Bits

Inhibit.

3-42

Data

3-42

Check.

3-44

BAD

[]

L]
L]

Parity

DATA

Output

3-44

Enable

3-44

3-46

Enable.

3-47

[]
[]

Data

Refresh.,

Transfer

Read

SNC

Control.

Select.

DRDY

.
.

[]

.
.

Battery

.
.

MAR4

Control

3-38

Bank

MAR4

3-38

[)

INT

Data

Parity

Done.

Busy

Check

[

(]

Mode

ECC/DPARITY.

Write

[]

Not

¢«

L]
[]

[]
L]

Battery

Array

Write

Board

¢«

&«

Inhibit.

MAR4

¢«

Sequencing

Data

Generation

Write

Ready

Parser

Mode

Array

[]

Flow.

Components.

Bank

Refresh

ECC

Battery

Input

(Figures

DESCRIPTIONS

Array

Command

Write

(MAR4)

Command/Address

BOARD

2-154

(NAB)

Write

ARRAY

Timing

mmmmmmwmmwabbppwwwwwwwwmN(\.)(\)NNNNH

Timing

MAR4

Read

Data

[]

Read

Array

Longword

Array

L[]

Octaword

4MBARRAY

[]

ClocksS.

Clock

ARRAY

Longword

(BBU).

MEGABYTE

8800

UNIT

Power.
of

Signal

[]

FOUR

MAR4

WWWUWwWwWwWwwwwuwwwwwwwwwwWwwwwwwwwwwwww WA

[

VAX

[]

wwwwwwwwwwwwwwwwwwwwwwwwwwwwwwww WWWwwwwww

CHAPTER

BATTERY

Wwwwwwwww
|
!
|
!
|
[
I wwwww
[\ NN NN
N R
[
\O O N DWNWN OO

2.14

2.14.1

Read

Data

Transfer.

3-47

CLK

o«

3-48

Mode

3-438

Normal

3-48

Mode.

3-49

Battery

Mode

XXXVii

3-53

FIGURES

Diagram.
Diagram.

.
.

.«
.

=«
s

.
v

CSRS.

FUNK

¢«

S
o I
B

|
el

Logic.

Read/Return and Read/Continue Loglc
Clock

<
'—l

2-16
2-17

2-138
2-19

2-20
2-21
2~-22

2-23

2-24
I
=

LT LD

2-26

2=-27

Interrupt Logic. .
«
CSR Logic. . .
Loglc.
Memory Busy

«
s
.

2—-29
2-30
2-31
2~32

2-33
2—34

2-35
2-36

«
s
e

«
e

«
s

«
e
e

«
s

«
e

o«

e
o

e
e

Clock, Reset, and Unjan Loglc . e .
Memory Data Path (MDP) Block Diagram
Memory Data Buffer (MDB) Block Diagram
CSR

Logic.

MDBC -- MDB Data- In %@lectlon
Input Load Command Detect Logic.
e
.

s
o

e
Full Logic . .
X and Y Bit Storage

e
.«

MDBC

Selection

«
.

MDBC -- MDB Feedback Selecflon
Double-Bit Error Logic . . . .
——~

OQut

MDR

Data-Qut

Select

MDBC --

Flow Diagram.

Internal Error, Write

«
.

Decofle

o«

Diagram

Error Check Block Diagram.
Error Status Block Diagram
Serializer Block Diagram .

.
.
.

«
.
.

.«
.
.

.
.
=

CSR2 Bit MaAD v v o
MRM Block Diagram.
MSC Block Diagram.
Buffer Control . .

o
.
.+
¢

o
«
o«
¢

o
¢
o
«

o
o«
¢
&

o
+
o
+

Clocks

DCHK Block

o
.+
+
«

o
«
«
+

o
«
«
¢

BNUM Probe Buffer and Error Logic.

2-37

Command/Address/Size

2—-38

Size

2=~39

«
e

Arbitration/Hold Loglr . . s
NMI Arbitration/Hold Timing.

and
2-28

Fault Detect Logic
ID/Mask Logic. . .

Logic.

and Command Control

Parity Generation and Checking

FUNK Function and pontrol

= W

DFA Block
DAD Block

Fields.

Command

MAR4

Hex

Logic

State Machine

o«

Buffer.
o

Flow Diagram

U W

Flow Diagram

Read/Write

MAR4

0 ~d

o
=

e
.
.

]

Diagram

[

Block

et e
b
e

}
|
|
0 ~1 Ot

Command/Address Flow jlagram e
Write Data Cycly Flow Diagram.
Read Data Cycle Flow Diagram .

Masked Write Data Cycle Flow Diagram

|
!
00 ~J OY U

et b

MBox

2-15

Diagram.

MBox Simplified Block

W NN~

MBox Read/Write Simplified Block Ulagram

0
I
W

Page

Title

2-40

Starting

2—-41

Mask

2—-42

Write

2-43

Mask

Address

Command
Write

2-44

Command

2-45

Mask

Done

Store

Select-Out
Read

Butfer

2~-48

MDB

Address

-49

MASC

Block

2-50

Power

2-51

CSR

Logic

Diagram

Control

Control
I/0

Block

Select

2-140
2—-141

2-144

2—-1438

Control

2-150

Diagram.

2-152

2-155

2-157

2-158

Flow

Diagram.

Read

Timing

Octaword

Diagram

Read

Timing

MAR4

Timing

Diagram.

3-5

3-6

Diagram

3-7

LJ.LQBLQ'l

[

[}

Diagram

3-11

Diagram.

Rlpck

Diarc»o

Oy U

.
c

Clock

|
=0 00

Clock

152 SN 4 WIS LN

Write

Array

Refresh

Flow

Diagram

Input

Parser

Block

Diagram

2-138

Diagram

Write

Flow

Logic
Timing

4MBARRAY

Ulégram.

Longword

Array

2-132

2-135

Flow

rlow

2-130

Block

Longword

Read

2-127

Diagram,

Down
Up

2-122
2-125

Block

Power

.
.

Diagram

Read

Power

.
.

Control.

BBU

.
.

(S2IN0)]

Array

MCL

2-52

.
.

Buffer

Control.

2-53

.
.

Block

2-46

Buffer

Logic.

Logic

2-47

Logic

Address/Size

Block

Dlagram.

Diagram

Bank

Block

Command

Flow

ECC/DPARITY

Block

Control

Refresh

Time

Refresh

Block

o
e
e
.
.
.
.
.
Diagram (Bank

3-24

3-25
0

Shown

3-27

Diagram

Data

Output

3-13
3-15

3-30

3-35
.

3-43

Diagram.

3-45

3-51

Diagram.
Block

Periods

Diagram.

3-40

3-50

Refresh

Flow

Diagram

Refresh

Normal

Flow

Mode.

Diagram

Battery

3-52

Mode

3-55

Initiation

Termination

Battery

Flow-Diagram

Mode

Battery

Symbols

Refreshes

Mode

3-57

Refreshes.

3-58

A-1

TABLES

Title

e
e
e

s wWN
OO0 ~JOY U

ST SRRy S
i
!

NMI

Signals

MBox

Used

Command

Write
NMI

Page

Longword

Bus

Confirmation

Write

Duadword*

Octaword

Read

Longword

Read

Octaword

Read

Hexword

the

Functions
Codes

Bus
Bus

Bus

Cycles.,

Bus

MBox
.

1-7

1-8

1-9

1-10

Cycles

1-10

Cycles.

1-11

1-12

Cycles

Cycles.,

XXX1X

1-13
1-15

NN NDNDNDDNDNDN NN
|I I
[
|
o = 0 00 S
W N

«
.

o
.

o
.+

o
=

.«

Write State Code .
Write Command Code
«

Write

o«

Code.

Size

= O

Read Bank Shift Register Modes

Signals.

.
o
o

Initial Address Truth Table.

Distribution

(NMI TO VAXBI ADAPTER)

INFORMATION.

BASIC BLOCK DIAGRAM.
BASIC OPERATION. . «

.
o

.«
«

«
¢

+
o

«
o

=
o

Interrupt Operation.

GENERAL

PHYSICAL DESCRIPTION AND CIRCUIT

Error

Q0
O

N DN

O
o

.«

NN
N

Registers.

.«

1.5.2.13

(BICSR).

Control

Intervrupt

(DTYPE).

Device Register

(BIIC)

=«

IPINTR Source Register (IPINTRSRC) « o
Starting and Ending Address Registers

INTR Destination Register (INTRDES)
IPINTR Mask Register (IPINTRMSK) .
IPINTR/STOP Destination Register

(SADR and

L[]

VAXBI Control/Status Register
Bus Error Register (BER) .

NBIB

(FIPSDEJS).

o U1t

Control/Status Reglsters (CSRO and CSR1)
Vector Registers (BR4VR through BR7VR)

NBI REGISTERS. «
NBIA Registers

ERURE
RN
Lo

TECHNOLOGY.

CPU Read/Write Data Transfers.
DMA Read/Write Data Transfers.

w N

Ut
Ulul e bW

ENABLE ECC Truth Table

(EINTRCSR)

CommandS

NMI Confirmation Codes
Read Function Codes. «
Read Command Code. . .

W W

.
+«
«

.
«
«

w
o

e e b

e b

.
+
«

.
«
«

INTRODUCTION

CodesS

Function

et ot = e et b

CHAPTER

NBI

SECTION

Code.

Size

Clock

—

o
o

NAB

Command Code

EADR).

BCI Control and Status Reglqter (BCICSR)

Write Status Register (WSTAT).
Force TPINTR/STOP Command Register
(FIPSCMD).

¢«

(UINTRCSR)

User Interrupt Control Register

General Purpose Registers (GPR <3:0>).
x1

SignalsS.

¢«

SPACe.

TransactionS.

o«

Timing

NMI

AdAress

NMI

Read/Write

NMI

Arbitration/Memory

BUSY.

NMI

Interrupts

EXrrorsS

VAXBI.

(BETWEEN

VAXBI

SignalS.

Basic

Timing

VAXBI

AdAress

VAXBI

Read/Write

Interrupt

o
o
L]

U W=

AND

NBIB)

o«

SpaCe.

TransactionS.

o«

(INTR,

¢«

IDENT,

and

IPINTR

o«

Identify

(IDENT)

TransactionS.

.
.

Interprocessor

Interrupt

(IPINTR)

Transactions

o«

TransactionS.

(INVAL)

Transactions.

.«

Modes.

Arbitration.

Arbitration

Control.

Extending

Transaction.

Mode

Functions

Bus

Requests

Special

EXrOrS

¢«

o«

¢«

o«

«o

v v v
Detection

Protocol

FUNCTIONAL

¢«

DESCRIPTION

INTRODUCTION
NBIA

Checking.

o«

Block

Diagram

NMI

Data

Buffer.

¢«

o«

NPAR

MCA

3.1.1.3

NBIM

MCA

3.1.1.4

NBED MCA

3.1.1.5

NBAP

MCA

¢«

3.1.1.6

NBCT

MCA

3.1.1.7

DSEQ

MCA

3.1.1.8

DC022

Buffer

3.1.1.9

o«

Data

3.1.2.1

Checking. .« v
Transmit Check Error

Parity

3.1.1.1

3.1.1.10

3.1.1.2

3.1.2

Arbitration

=
N
w

Data

NBIB

Transaction

o
o

I
U

W N

W]
O
OO
WO
o

O O WO

Transactions.

VAXBI

w
W

L]
.
e
[

WWwWwwWwwwwwwwww

DN
N

¢
.

[]
[

MDNNDNDNDDNNDDNNDDNDNDDNDDONDN

Operation

Invalidate

3.1.1

(INTR)

Bus

Interrupt

STOP

3.1

o«

Transactions).

CHAPTER

NBIA

.
(Bus) Buffers .
.
.
¢
v
v
¢
o«
o
o
o
=
Bus (and Transaction Buffer) Controls

Block

Data

Bus

3.1.2.2

BCI

Data

3.1.2.3

Parity

Diagram

Data

¢«

o«

Buffer

o
¢
v
Logic

Buffer.

and

.
¢«
v
Translation

x1li

I
I
e
Db BN b

BUS

N A
U

NMI

e
e
NI

Basic

|
S
OO

DESCRIPTIONS

WWWWwWWwwWwwwwwwwwww

o
o

~OY
U s
N~

NMI

U=
W N

s
e

e
*

L ]

INTERFACE

DATA

NMI.

WWWWWWN
e
e s

e
o
o

NDNDNDNDNDNDND
NN

CHAPTER

Sequencers

o
«
¢«

o
«
«

¢
«
¢«

o
o
¢

INITIALIZATION/SELFTEST., « « o«
Basic NBI Initialization . .
BIIC Initialization/Selftest

s
.
.

BIIC

.«

VAXBI Clock Drlver/Recelver.

INIT/UNJAM

o«

o
o
«

o
o
o

o
o
o«

o
&
=&

Local Read/Write Operations.

o
o«

¢
¢«

o
o

s
o

o
o

=~
N
W

=
[]

W N

«
¢«

o«
«

NMI Address Decoding and Translation .

o«

Command/Address Cycle.

RESET (By Connected VAXBI Dev1ce).
«

1
I
I wwwww
|
S
el el
i S
Oy b BN DWW
S0

wwwWw

U
0 ~Jd O

.«

NBI

o
.

Uk
W N~

.
LJ

Port

Master and Slave

POWETrUDPe

UMb WWwWwwwiNNNDND
DD
=

[]

Length and Interrupt Control Logic .

CPU READ/WRITE OPERATIONS.

p—

s
o
e

o
o
.

BEDWWWWWWWWwwwwwwwwhN NN
e

wwwwwwwwwwwwwwwwwwww WWWwWwWwWwwwww
L]
®

Data Buffer Read/Write Control

o
o

o
¢

¢
o

&
=

VAXBI Read/Write (and IDENT) Operations.

¢
.«

o
.

Write Data Cycle .
Return Data Cycle.

Parity Generation and Checking .

Command/Address Transfer

«
.

Write Data Transfer. « « ¢
Return Read Data Transfer.
«
«

«
o

¢
¢

o
o

DMA READ/WRITE OPERATIONS.

Write Sequence Faults. .
NMI BUS ACCESS TIMEOUTS.
VAXBI

BrrOorS

o«

Command/Address Transfer

¢
o

¢
s

o
o

«
o

¢
o

o
o

o
«

o
¢

o
o

o
«

¢
«

Parity Generation and Checking

Command/Address to BCI Data Buffer

o«

End of VAXBI Transaction (and Retries) .
Write Data to NBIA's Transacticn Buffer.,
Write Data to NMI (NMI Write Data Cycle

.
.

and Data Bus Buffer.

¢«

Command/Address to NBIA's Transaction
Buffer

CYCle)

Command/Address to NMI (NMI Command/Address

Write

Data Bus Buffer.

Data Transfer.

Write Data to BCI Data Buffer
and

Oor Cycles)

.«

NMI Write Transaction Retries (NO
ACCESS/MEMORY BUSY/NOACK). « o o o

Return Read Data to Transaction Buffer .

DMA

EFTYOrS

&«

Return Read Data Transfer.

NMI Read Transaction Retries

¢ o o o
to NBIB

o
.

o
«

o
¢

.
o

(VAXBI READ DATA CYCLE).
End of VAXBI Transaction

.
.

¢
.

¢«
.

o«

&
e

o
o

o
e

o
s

Parity Generation and Checking

(MEMORY BUSY). «
Return Read Data

Return Read Data to BCI Data Buffer and BIIC
DMA Errors

(VAXBI Transaction Retrles)

x1ii

Command/Address and Write Data/Mask
Parity L
L J | ] L J [ ] . [ ] . L 2 [ ] L ] L[] L L
*
Return Read Data/Status Parity . .
.
Timeouts.
® [] L] L4 L4 L]
. » L4 L] L] L] .
L]

3-86

.
L]

.
* .

3-90

Read

Sequence

(by

VAXBI

INVAL

DIAGNOSTIC
NBIA

CPU

pd
o
Wi

e
e

O 00O

e
b
b
e

=
B>
w N S ()

b
b
P
=

3-90

3-91

Requests.
.

NodesS)

3-96

3-92

Operations
«

o«

3-96

Transactions

3-96

and

DATA

BROADCAST

TRANSFERS.

&«

3-97

Requests

3-97

3-98
99

Wraparound.

and

.«

Memory

<22>).

(Flip

Address

o«

Title

—

{

¢«

TransactionS.

Loopback

<29>

OPERATIONS

Read/Write

Bits

¢«

Read/Write

VAXBI

Stop

¢«

OPERATIONS

VAXBI

IPINTR)

Interrupt

Other

BIIC

AND

NBI

Configuration.

NBI

Basic

DC022

Block

Diagram

Transaction

Buffer

Organization

CPU Read/Write Data Transfer .
DMA Read/Write Data Transfers.
INTR/IPINTR Operation
.«
«
o
«

.
.
«

+
.
o

«
¢«
o

o«
o«
o

o
o«
o

o
o
o

Interrupt

SCB

Vector

Format

(Example)

Control/Status
Control/Status

Registers

(BR4VR

Device

(DTYPE).

Bus

Control/Status

Error

Interrupt

INTR

Destination

Control

Destination

Ending

Address

VAXBI

Control/Status

Status

Force

IPINTR/STOP

NBIA

and

Basic
NMI

NMI

NBIB

o«

(CSRO)
(CSR1)

.
.

BR7VR)

¢
.

(BICSR).

=«

¢«

o
¢

«
«

.
.

(FIPSDES)

.«

(BICSR).

(SADR)

.
¢«

¢«

Input/Output

(SADR)

(GPR

(EINTRCSR).

(IPINTRSRC)

Registers

Space

(INTRDES).

Command

¢«

(WSTAT).

Control

Timing

Address

Interrupt

Write
User

General-Purpose

(IPINTRMSK)

Address

¢«

Starting

through

(BER)

IPINTR/STOP

Source

¢«

IPINTR Mask
IPINTR

0
0

Vector
VAXBI

(FIPSCMD)

(UINTRCSR)
<3:0>).

.
.

Signals

Decoding

MISCELLANEOUS

BIIC

FaultsS

(INTR

INTERRUPT

3-88

.
«

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.
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o

o
«
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o
¢
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=
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2-19

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2-38

2-13

MEMORY BUSY Timing .
Fault Signal Timing
Basic VAXBI Timing «
VAXBI

SpPac€.

Address

o«

o
«
o

o
.
o

«
«
«

«
«

VAXBI Node Register Space. « «
VAXBI-Required Registers . . «
BIIC-Specific Device Registers

2-14

.
.

. .
Basic NMI Arbitration Line Timing
l)
(Typica
NMI Arbitration Line Timing

2-16
2-18

2—-22
2—-34

2-37
2-38

VAXBI Write Transaction (Octaword Length)
VAXBI Read Transaction (Octaword Length)
VAXBI Interrupt (INTR) Transaction . . .
VAXBI Identify (IDENT) Transaction . . .
VAXBI Interprocessor Interrupt (IPINTR)
o

VAXBI Invalidate (INVAL) Transaction .

W N
= O
W

¢
.

. . «
INIT

«
.

2-51

2-53

2-56

2-55

o
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2-49

2-58

2-60

o«
.

«
«

s
+

¢
«

o
.

3-19

«
.

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«

.
NMI Address Decoding and Translation
Local Read/Write Command/Address Cycle .

3-23

Basic Information Flow Between NMI and VAXBIL
NMI to VAXBI Command/Address Transfer. .

3-34

.
.+

.
¢«

«
¢

«
«

NMI to VAXBI Write Data Transfer

o
&

. .

o
¢

VAXBI to NMI Return Read Data Transfer .
Aligned and Unaligned Quadword Read Data
Ordering

=«

POWEXrUP

2-46

.
.

«
«

2-43

—_

NBIA Detailed Block Diagram.
NBIB Detailed Block Diagram

Local Write Data Cycle
Iocal Read Data Cycle

«
.

Reset by VAXBI Node
UNJAM/Programmed NBI

—

= AD 00 ~JOY U

WWWWWWwwWwwWwwwwwww
|
[
|

Arbitration State Diagram. .
VAXBI Arbitration (Example).

Bus Arbitration Request Lines.

NBI

2-42

(.I»Jw

VAXBI STOP Transaction

¢«

TransactionN.

2-39

~N Ut~
W

NMI Write Transaction
NMI Read Transaction .

Bacsic Information Flow Between VAXBI and
During DMA Read/Write Operations . . . .

3-27
3-29
3-31

3-37

3-44
3-50

3-64

VAXBI to NMI Command/Address Transfer. .
VAXBI to NMI Write Data Transfer . . . .
NMI to VAXBI Return Read Data Transfer .

3-67

3-101

INTR/IPINTR Operations

o«

FLIP 29/22 Diagnostic Data Transfers

x1liv

3-74

3-80
3-93

TABLES

Title
NBIA

Registers

Control/Status
Descriptions

(BIIC)

Descriptions

INTR

Destination

Descriptions
Mask

IPINTR/STOP

Descriptions

Status

Descriptions
Force

.
.

Descrlptlons

(BICSR)

NMI

Signals

Connecting

Blt

Bit

(SADR)

Blt

(BCICSR)

Bit

(FIPSCMD)

(UINTRCSR)

NBIA

2=-5

[]

2-25

[]

2-30

Signals

BCI

|
N

NBI

CPU

Read/Write

Summary

Signals.

.
.

(IPINTRSRC

Command

Control

(IPINTRMSK)

(EINTRCSR)

(INTRDES)

Bit

.
o
v
v
v
v
v
v
4
4
e
Register (WSTAT) Bit

Interrupt

Descriptions

Bit

4
v
Bit

User

VAXBI

IPINTR/STOP

Bus

.
.
v
v
v
v
v
v
Register (EADR)

Bit

Data

Control/Status

Descriptions

Bit

Descriptions.

Address

DesCriptions

Destination

Address

Descriptions

Ending

Source

Starting

Descriptions

Bit

Control

Bit

IPINTR

Interrupt

IPINTR

(DTYPE)

(CSR1)

Error

Contrcl/Status

Error

Write

(CSRO)

Registers.

Descriptions

BCI

.«

Bus

[

Descriptions

Device

VAXBI

Control/Status
NBIB

DMA

o«

Read/Write

SUmMmMAYY

3-21

3-61

Signals.

¢«

Initialization

3-9

+«

¢«

o«

3-13

x1lv

EK-KA88I-TD-PRE

SECTION
INSTRUCTION

BOX

(IBOX)

CHAPTER

'INTRODUCTION

1.1
The

OVERVIEW
Instruction

the

entire

functions

Buffer

Decode

Monitor

IBox
part

unit

(IBox)

(except
IBox are

contains

the

for
some
as follows:

prefetched VAX
supplied by the Cache

and

The
and

CPU
the

instruction
unit (CBox)

macroinstructions

and

Supply

I-stream
embedded
immediate mode data, etc.)

and

CPU

the

interface

path

stream

the

between

their

The

IBoxs

own

interface

operate

the

independently

Clock

(CLK)

1-1

data

execution

interrupts,

example,
Execution unit

Clock

also maintains four internal privileged
of the processor status longword (PSL).

IBox.

(I-stream)

(for

l.1.1
Dual-Processor Configuration
Each processor in the VAX 8800 dual-processor
own

major

example,

the

controls
The

their

for

data

that

operations).

control

and service microtraps,
exceptions

Provide

microcode

Cache

1literals,

(EBox)

(CLK)

module

registers

(IPRs)

configuration
of

module.

each

other

has
and

its
have

1.2

LOGIC

ELEMENTS

Sequencer
(DEC),
the Decoder
The IBox resides on three modules:
1-1.
Figure
to
Refer
(WCS).
and the Writeable Control Store
(SEQ)
follows:
as
are
The logic elements contained on each module
Module

Logic Element

DEC

Instruction Buffer (IB)
IB

Manager

Decoder

Gateway Control
Bus Watcher

Microsequencer

SEQ

Part of the control store logic

Condition Code and Macro Branch Logic
Interrupt and Processor Register Logic
File

Address

Generator

Rest of the Control Store

WCS

NOTE

The Bus Watcher logic is functionally part of
the EBox and is described in the EBox section
of

1.2.1

this manual.

Physical Implementation

-4

Most IBox logic is implemented by Macrocell Arrays (MCAs) which are
ECL chips that form the basis for most CPU logic.
high density,
The MCA mnemonics are indicated in parentheses in Figure 1-1.

——

from u-code

MACRO

SIZE DEP BRANCH CONDS \

BRANCH

LOGIC

STATE FLAGS

INTERRUPT

and

<8:0>>

INTR PENDING

INTR ID <4:0~

CBOX
EBOX

Machine

IBOX

check conds

INPR MCA

CONSOLE
GATEWAY

to other CPU

¥
iY

LOGIC

CS RAM write control
DRAM Write control
—»

GWYC MCA

CONS BIDI

to Decoder

DEC UADDR ———»]
from Decoder

Transmit/
Receive

to/from

RAM

Discrete

[

Logic

CACHE DATA ———»

—»

t0 Decoder

—

to IB DATA BUS <7:0-

[

CONS IPR DATA <7:0>

CONTROL
STORE
RAMs

<13:00>

muxes

————» CBOX control
|———-—» EBOX control

—

<7:0:

16K
x 143

DRAM WRITE DATA <7:0=

module

CS RAM
ADDR

u-PC
addr

<7:0>

Console
via CLK

WRT DATA

u-PC ADDR ———

CONS DATA <7:0>

DATA BUS
<7:0>

[

5 UBRS MCAs
1T UTRP MCA

—

————»

module

to Micro-PC

Sequencing control

Control

u-PC addr <13:00>

address muxes

CONSOLE REQUEST

CONTROL

from

MICRO
SEQUENCER
LOGIC

INTR OTHER PROC

»1

from p-code

-1

from

SET MHICROMATCH

I_MISC

Console
via CLK

u-Trap conds

PROCESSOR

CACHE DATA —»]

<TP, FDP, CUR MD, V>

————

w-Branch conds

—

PSL bits

Faults

PSL CCs

CCBR MCA

Interrupts/

[

CODE
and

————» |BOX control

h—-—-—-——-——_—-—_-—_--_-__J

]

CONDITION

-MISC

I_SIZE

[

RAW CCs -———»{
W BUS <3:0> —»
from EBOX

Status from
CBOX/EBOX/IBOX

MKV86-0688

Figure

1-1

IBox

Block

Diagram

(Sheet

-——"————j

r—_--————-—""———————————————————_n—_———

1
|
| CACHE DATA
BUS <31:00>
| from
CBOX
|
I
|

IB DATA BUS <31:00>

4 x 32
TION
INSTRUC
BUFFER

SPEC GRPNUM <3:0>
OPCODE <7:0>

(1B)

SPEC. <7:0>

MCAs
41 IBUF
MCA
IBFO
Y y ¥

from
u-code
>

DEC SELECT ——{

from u-code

1B Control

from Decoder

—

ASIDE RD ADDR

4K x 17

DECODER
RAMS
(DRAMS)

INSTRUCTION
BUFFER

MANAGER

SPEC NUM/SIZE/TYPE
IB STALL

IB PE

Discrete

Muxes/
Latches

B MD VALID -

ADDRES
ENCODERS

BW B RD ADDR >

FADs

DECODER
and
SPECIAL

WR ADDR <1:0>

|
l
|
|
i
|
|
I
|
|

|
|
—>
|
I_APORT
BSIDE RD ADDR
E_BPORT ——
|
—>
FILE | FILE WR ADDR
_WRTADDR—{ ADDRESS
— |
»| SLICES
MD STALL
|
BW WR ADDR
—>
BUS
—=|
MDNUM
VALID
MD
A
|
R
WATCHE
BW A RD ADDR >
- . ||
<2:0> > 2
to EBOX

MCAs

(Part
of

A CD READY -

—

1B Control

—»

DEC UADDR <13:00>

—»

to IB Manager

to Micro-PC

sheet 2 of 2

address muxes

PC INC <2:0>
to EBOX

DRAM WRITE DATA <7:0> and write cornitrol

from sheet 2 of 2

|
|
|
|
|
|
|
|
|
|

Lm________________m_______________m_______m____J
CBOX/EBOX Special Address conditions

MKV86-0687

Figure 1-1

IBox Block Diagram (Sheet 2 of 2)

l1.2.2
Instruction Buffer
The instruction buffer is
prefetched

following

VAX

data

(IB)
a

4-longword

I-stream data

relative

the

Current

Specifier

GPR

Specifier

extension

code

the

byte

the

operand

EBox

current

the

The op
code
and
current
specifier
extension
bytes

bytes
IB

byte

the

Prefetched

the

I-stream

CACHE

specified

increments

point

the

read

BUS.

the
this

write
value

the

starting

address,

<1:0>.

the

alignment

The

IB manager

The
for

which

location

ADDR

read

<1:0>,

address

updates

reflect

(second

the

are
are

the

one

are

the

new

stores
the

decoder

generator

data,

literals,

etc.)

output
simultaneously,
sign extended and output

4-longword

longword

1loaded

treated

the

memory

time

from

location

The
1IB
manager
enters the IB to

16-byte

memory

specified
and

the
points to

points
these

outputs

manager

address

treated

data

The

control

op code byte
the
first

enters

The

IB -

byte

The

and

bus

specifier
(if
any)

The

(immediate

data

memory.

CBox

address, IB WR ADDR <1:0>.
by one each time a longword
location to receive data.

the

CNTL

processed

data

DATA

1.2.2.2
Reading
when read.
The

IB -

the

and

file

later.

1.2.2.1
Writing
when written,

macroinstruction:

manager

specifier

number

(1l6-byte)

supplied

the

pointers
I-stream

by a combination of
the
alignment control, IB ALIGN
the
appropriate
1longword;

proper
each

byte
time

the

longword.

specifier

positioning.

is read directly from the IB in the
decode
cycle
specifier.
It is then stored in a "Cycle Op Code"
becomes the source of the op
code
for
subsequent

sixth

specifiers).

1-5

IB Manager

l1.2.3

The IB manager controls the IB read/write operations and computes
the amount of IB data "consumed" during each IB decode cycle. It

also indicates the current specifier’'s type (literal, register
mode, etc.) and position (first through sixth) in the instruction
to the

Decoder.

1.2.3.1 1IB Read/Write Control - The IB manager supplies the read,
write, and the alignment control inputs to the IB. See Sections
1.2.2.1

and

1.2.2.2.

1.2.3.2 Computing Amount of IB Data Consumed - The amount of data
consumed during the first cycle of an instruction includes the op
code, the first specifier, and up to four specifier extension
In subsequent cycles (second to sixth specifiers), it
bytes.
includes the specifier and up to four extension bytes.
Example:

Instruction - MOVL #°%X12345678, B"04(RO)
Cycle

IB Data Consumed

First

Six bytes - op code, first specifier,

Second

Two bytes - second specifier, one

four extension bytes

extension byte

The IB manager indicates the amount of IB data consumed to the EBox
as a PC increment value, PC INC <2:0>. The EBox uses this value to
update

the VAX PC.

In the first IB decode cycle, the PC INC <2:0> value ranges from O
to 6 and 1is based on the op code byte and the current specifier
type bits. Thereafter, it ranges from 0 to 5 and 1is based on
either the current specifier type bits alone or in combination with
"predicted"

size bits from the decoder.
NOTES

The predicted size bits are only used if
specifier in the second to sixth
a
a branch displacement or
is
position
The bits are output
data.
mode
immediate

in the current decode cycle, but indicate
the next specifier to be
size of
the

processed.

PC INC <2:0> can never be equal to
the

first

architecture

extensions.

decode

does

not

cycle;

support

the

VAX

3-byte

l.2.4
Decoder Logic
The decoder logic consists

(DRAM)

muxes

and

special

priority

of a 4K word
by
address encoder, which

encoders.

1.2.4.1
Decoder RAMs specifier
number,
the

(2-byte op codes).
supplied by the IB

Major

Supply

DRAMs
code

are
addressed
byte,
and
by

The specifier number and
manager, the op code byte

the

address

code

the 2-byte signal
is supplied by the

with part
of
the
entry
specifier microroutines

and

Assist

Indicate which EBox
memory
receive data from memory for

Address

DRAMs

every

the

supply

the

When

the
decoder.

Manager

controlling

the

bits

data

the

routine
specifier

the

entry-point

the

than

microsequencer

addresses

for

microword

takes

control

for

the

exits,

specifier

routine.

control

1is

returned

processed

to
the
manner.

then

instruction

new

1is
to
request

address

one

the

Once all specifiers are processed, the DRAMs supply
of
the entry address for the routine that performs

the

point

those

specifier,

additional

specifier
The

low

microroutine.

service
generates
the

that

are
IB.

Generation

specifier

required

by
the
current
"2-byte" signal

microsequencer

for

Entry

and

The
op

writeable
RAM
composed of discrete

functions
1.

The

17-bit

(the execute
instruction is to be

code)

and

inform

same

the
the

the

low 5
actual

1IB

bits
work

Manager

executed.

Control

The DRAMs work in conjunction with
"shift"
the
next specifier out of

data

size

the

MDR

Addressing

The

MDRs

reside

scratchpad

supply

decode

specifier

the

registers

MDNUM
cycle.

where

EBox

+the
the

1IB
IB.
applicable.

for

all

data

select

the

appropriate

(The

MDRs

are

manual.
)

file

requested

described

1-7

manager
to
logically
They also indicate the

MDR
in

(RGF)

and

from memory.

during

the

EBox

each

serve
The

DRAMs

specifier

section

this

1.2.4.2 Special Address Encoder - The special address encoder
CPU conditions that may affect
"special”
certain
monitors
instruction execution.

When a special condition is present, the special address encoder:

Generates the entry point address for a routine to service

Outputs the "special” entry address to the

the

condition

in place of the specifier or op code address

microsequencer

I1f the condition is not critical, such as a TB miss while accessing
the I-stream, the special condition microroutine returns control to
the decoder after it services the condition.

If the condition is critical, such as an IB parity error, the
special routine indicates the error in the IBox error register an
passes control to a machine check microroutine (see Section 1.5.2).
Depending on the severity of the condition, the machine check
routine either 1invokes a macrolevel service routine to record the
error in the system error log or reports the error on the VAX
console

1.2.5

and halt

the CPU.

Microsequencer Logic

The microsequencer is responsible for determining which of several
sources is to supply the address of the next microword to be
executed to the microPC address latches of the control store RAMs:
Current microword

Decoder entry-point microaddress
EBox or CBox microtrap vector
Machine check microtrap vector

Trapped microPC from a microPC silo
Microsubroutine return address from a microstack
Console supplied microaddress

All address sources, except for the decoder, are multiplexed by the
The address from the decoder and the one
microsequencer logic.
The
multiplexed by discrete logic.
are
encer
from the microsequ
microPC
in
stored
is
wide,
bits
14
1is
which
selected address,
address latches and presented to the control store RAMs.

VI 1-8

Control Store
l1.2.6
The CPU control store microcode 1is 16K words deep by 143 bits
wide
and
resides
in
16K
by
1
bit writeable RAMs.
The microcode is
loaded into the control store RAMs from the console Winchester disk
during
system
initialization.,
The
major microcode features are
listed in Table 1-1.

Table

1-1

Microcode

Features

Feature

Description

Horizontal
in nature

Microword bits are grouped
Each field directly
feeds

Pipelined
operation

More than one microword is active
at any
given time.
Allows
the
CPU
to perform

1into
fields.
and controls a
specific CPU logic element.
(Some fields
have vertical functionality in that
they
control more than one element.)

several

Segmented
structure

operations

Control store RAMs
physical segments:
CS0
CS1
CS2

- SEQ module,
- WCS module,
- WCS module,

simultaneously.

are

48
48
47

divided

into

three

bits wide
bits wide
bits wide

Each segment has its own parity bit
parity) and one or more spare bits.

Approximately
available for

14K words
of
microcode
control
the
user written code, and 1K are reserved

l.2.7
Condition Code and Macrobranch Logic
The CCBR MCA maintains the PSL condition code bits
and

CPU

state

(odd

CPU,
1K
are
to DIGITAL.

(N,

and V)

flags.

l1.2.7.1
PSL CC Bits - The CCBR MCA receives "raw" condition
codes
that
result
from
various
EBox operations (for example, main ALU
functions) and generates
a
group
of
size-dependent
microbranch
conditions
based
on
the
raw
CCs and the size of the data being
processed.
The size-dependent conditions can
then
be
tested
by
microbranch

logic

the microsequencer.

The raw CCs can also be compared to the
affect
bits.

macrobranch

instruction

VI 1-9

current

stored

PSL
as

the

bits

new

PSL

are
flags
state
CPU
7
Flags - The
State
l.2.7.2 CPU
another
microprogramming aids that provide firmware writers with
means of controlling microcode flow. The flags can be set (one at

a time) or cleared (individually or as a group) in one microroutine
The
and then tested as microbranch conditions in a later routine.
in
cleared
are
and
de
microco
the
by
led
flags are explicitly control
the first microword of every macroinstruction.
1.2.8

1Interrupt and Processor Register Logic

The interrupt and processor register logic are
the

both

contained

INPR MCA.

MCA
1.2.8.1 1Interrupt Logic - The interrupt section of the INPR
level)
y
priorit
upt
(interr
IPL
the
of
maintains the hardware image
field of the PSL. It monitors hardware interrupts, encodes the
level of the highest pending request, and compares it to the
current IPL.

If the encoded level is greater than the current IPL,

the interrupt logic outputs an interrupt identification tag (INTR
ID <4:0>) and request that microcode take an 1interrupt branch by
asserting an interrupt pending line (INTR PEND) .

Processor Register Logic - The

1.2.8.2

processor

logic

maintains the hardware images of four VAX internal privileged
registers. These registers, which are described in Section 1.4,
control or supply data to the:
Interrupt logic
Microsequencer logic

e
e

Memory management logic {in the CBox)

The INPR MCA also maintains copies of PSL Dbits <30,27,25:24,5:4>.
(The entire PSL is kept in an EBox slow data file register.)
1.2.9

File Address Generator

MCAs.

This logic performs the fcllowing:

(FADS)

The file address generator consists of 2 file address slice
EBox

Supplies most of the address inputs to the

Stores GPR numbers referenced by operand specifiers

Records changes made

Allows fast access to operands requiring more than one GPR

file (RGF) and slow data file (SDF) registers

autodecrement operations

GPRs

(quad and octaword operands)

during

autoincrement

and

1.2.10
Gateway Control Logic
The gateway control logic (GWYC

console
resident

1.2.10.1

MCA)
providing
a
data path
the clock (CLK) module.

by
on

Primary

Decode

Control

console

the

commands

transfers

data

between

Console

transmit/receive

Console

control

CPU

the

the
CPU
to
the
VAX
console interface logic

CPU/CLK module

data
registers:

These

Functions

1links
to the

interval

registers

and

count

path
the

data

status

CPU

following

control

store

CPU micromatch
CPU

decoder

Cache

the

buffers

console

RAMs

control

module

registers

reside

the

CLK

registers

CLK module.

Control

and

sequencer

vl 1-11

RAMs

CPU

interface

elements:

logic

IBOX BUSES

the CPU:
Three major buses interface the IBox to the rest of
1.3

Cache Data Bus

Cons Bidi Data Bus

IB Data Bus

parity). It
Dbits wide (32 data,(Sec4 tion
The cache data bus is 36
1.2.2) and
IB
the
I-stream data for sters.
supplies the IBoX with
with data for the IBox and CLK module regi
byte of
time from the low
ten one byte at ares
Register data is writ
the
ains
cont
bus
the
that
the cache data bus. Microcodes ensu
.
ster
regi
cted
sele
of the
1.3.1

Cache Data Bus

correct data for high-order byte

IB Data Bus
1.3.2
lies
4 parity). It supp
36 bits wide (32 data,from
The IB data bus isI-st
2)
1.2.
tion
(Sec
IB
the
ream embedded data module registers.
the EBox with
and with data read from the IBox and CLK
significant byte
byte at a time (least
Register data are outputof one
s are assembled
byte
The
the IB data bus.
first) to the low byte

into a longword in the EBOX.

that links
an 8-bit, bidirectionalto bus
The cons bidi data bus isCPU.
access registers
It allows the CPU
the
the CLK module to modu
interface logic
ole
cons
le and, through the console subs
resident on the CLK to comm
ystem.
unicate with the
1.3.3

Cons Bidi Data Bus

of the CLK module,

vi 1-12

1.4
IBOX RESIDENT INTERNAL PRIVILEGED REGISTERS (IPRs)
Microcode implements the hardware images of
two
VAX
architecture
and
two
VAX
8800-specific
1IPRs
in the IBox (IPR numbers are in
nex).

Refer

Table

1-2.

Table

1-2

1IBox

Resident

Name

VAX Architecture

IPRs

Mnemonic

Number

IPL
PME

12
3D

NICTRL

INOP

IPRs

Interrupt Priority Level
Performance Monitor Enable

VAX 8800 Specific IPRs
NMI

Interrupt

Control

Other

Processor

The IPRs reside in the INPR
MCA
of
the
SEQ
module.
They
written from the low order byte of the CACHE DATA BUS after the
passes

the

through
DEC module

DEC module.
it detects a

The INPR MCA reports bad
parity error on the bus.

parity

l.4.1
VAX Architecture IPRs
The IPL and PME registers are

read/write

software

but

maintains

the

software

images

IBox

hardware.

the

EBox

Microcode

IPRs

When
both

a MTPR instruction writes the
the INPR MCA and to the SDF.

IPL or
When a

IPR,

the

SDF

data

slow data

obtained

The INPR MCA receives
bus.
However,
the

file

from

PME bit 0
Microcode

PME

bit

is sent
shifts

the

proper

backplane

write-only
for

the

PME,
MFPR

the data is
instruction

sent
reads

to
an

copy.

position

to
the
INPR
MCA
as
the
bit to the proper

available

(SDF).

IPL data as bits <4:0> from
the
bits
are
stored
as PSL <20:16>

Microcode shifts the bits to
software image to the SDF.

are
bus

1-13

for

when

CACHE
DATA
position on

external

cache
in the

data
SDF.

writing

the

BUS
bit
the bus.

1.
The

monitoring.

l1.4.2

The two

VAX 8800-Specific

mechanism of

IPRs

8800-specific

VAX

both

1IPRs

deal

with

the

interrupt

CPU.

the

Both registers are written from the low byte of the cache data
bus
The 32-bit software
registers to hardware.
8-bit
as
appear
and
=

[

LOrma Lo

1in

SNown

NICTRL
(NICTRL) - The
Register
Control
Interrupt
NMI
1.4.2.1
by the
requested
interrupts
to
response
controls the CPUs
register
as
and,
write-only
is
register
The
two NBIAs and by NMI memory.
such,

has no SDF software

image.

| MEM

MBZ

NBIA Device O Interrupt

NBIA Device 1 Interrupt Enable
Memory Interrupt Enable
MKV8E-Ubry

Figure 1-2

NMI Interrupt Control

Tabie

1-3

—~

(NICTRL)

NICTRL Register Bit Descriptions

Bit

Mnemonic

Description

<7>

DOIE

When set, enables the CPU to respond to interrupts
from NBIA Device 0. Cleared by CPU init.,.

<6>

D1IE

Same as above,

but for NBIA 1.

<5>

MIE

Same as above,

but for Main Memory.

l.4.2.2
register

1Interrupt
controls

processor

and

has

SDF

Other
Processor
Register
(INOP)
whether
an interrupt is requested
dual-CPU system.
This register is also

The
the

other

write

only

image.

MBZ

INOP

|IOP

Interrupt Other Processor
MKV86-0690

Figure

1-3

1Interrupt

Table

1-4

Other

1INOP

Bit

Mnemonic

Description

<0>

IOP

When

set,

processor

The
set

Processor

causes
of

Bit

(INOP)

one

CPU

clock

cycle

later.

Map

the

other

configuration.

INOP register exists as a latch in the INPR MCA.
when
microcode
addresses
the
register and is

cleared

Bit

Description

interrupt

dual-CPU

The latch
is
automatically

1.5

The

1IBOX MICROCODE VISIBLE ONLY REGISTERS

IBox

maintains

three

accessible by the microcode:

2.
3.

1.5.1

hardware

registers

that

are

only

Clear interrupt other processor (CIOP)
1IBOX error register (IBER)
Clear error register (CER)

Clear Interrupt Other Processor (CIOP)

sor
This register clears the interrupt requested by the other proces
signal
a
as
of a dual-processor system. The register only exists
ses the
addres
ode
microc
when
ed
assert
1is
that
in the INPR MCA
register and is negated one CPU clock cycle later.
1.5.2

IBox Error Register (IBER)

The IBER is a 12-bit register that records errors detected by IBox
hardware and by microcode. The register is maintained by microcode
in an EBox SDF register. (Refer to Figure 1-4 and Table 1-5.)

similar
1.5.2.1 IBER Usage - The IBER is stored along with othera SDF
data
error registers from the CBox (CBER) and EBOX (EBER) in
structure known as a machine check error bank.

nt
When a CPU error occurs, the error registers, and other relevaand
stack
the
to
n
writte
are
etc.),
PSL,
t
data (virtual PC, curren
to the MC error bank. If the error 1is recoverable, the system
in the
software will obtain the data from the stack and record it consol
e
VAX
the
rable,
recove
not
is
error
system error log. If the
the
to
it
report
and
bank
ervor
MC
the
from
will obtain the data
console operator. (Machine checks are discussed in Chapter 3.)

l.._-l

Vi 1-16

1.5.2.2
the

1IBER Bits

DEC

module

modules.

The

are

"locked"

then

reported

<7:0>

and

latches

until

report
only

the

These

one

the

Bits

<7:6,4,0>

all

The

transfer

the

set,

module

data

and

dropped

module

first
a

serviced.

parity

was

module

picked)

the

latches
DEC

and

error

received.

second

error

Thus,

the
first
cleared by

errors

Table

detecting

being

error

DEC

(or

indicate

mnemonics

was

the

that = the

discrete

on
SEQ

They

from

being

second

error

one, the new
writing
the

error
clear

(CER).

registers,
and

detected

prevent

occurs
before
microcode
services
indication is lost.
The latches are
error

reside

errors

store

hardware

first

bits

parity

the

from

detected

the

bit

data

when

accessing

indicate

error.

transferred

received

while

1-5

the
SEQ

from

processor

direction

For

example,

DEC

module

module.

the

routed

the

cache

the

This

data

SEQ

means

bus

bit

the

but

SEQ

module.

1.5.2.3

<11:08>

the

SDF

1image

the

microroutines

that

service

the

special

only

1IBER Bits

1in

special

Bit

since
Bit

address

is
it

encoder

reported
1is

indicates

microroutine

never

causes

and

there

1is

double

or
a

address

‘'such

that

machine

error

microwords

will

microcode

indicate

mentioned

by
in

but
the
the

1.2.4.2).

considered

microsequencer,

All

latches

written

1IBox

problem

IB.

the

logic

parity

Section

are

conditions

(see

but

exist

They

the

fatal

only

not

either

routine

hardware

error

Bits

CBox

the

IBER.

generated

accessed.
to

bits

discussion

the

that

some

control

These

the

contain

set

bit

10.

the

addressing

bug

decoder,

microword
Since

that

code
this

should

pass

means

there

mechanism,

the

check.

that

determine
occurs,

parity

which

only

1-17

error

longword
PE

was
at

detected;

fault.

reported

(bit

If
09).

;

| DEC | PRC

MEM [ MCR|
PE | PE | SEQ | REG
BRK
|ADR | UW | Lw | PE
|PE
T

IB Memory Broken

[

|DEC | CON|
|[RAM | DEC|
|PE
| PE

cSo | CS1 | CS2 | DEC
PE

| PE

| CON
PE

—

lllegal Micro-address

IB Parity Error Upper Word

IB Parity Error Lower Word

DECoder to SEQuencer Parity Error

PROcessor REGister Parity Error

DECoder RAM Parity Error

CONsole to DECoder Parity Error

Control Store segment O Parity Error

Control Store segment 1 Parity Error
e

LOUNUOUL

OLOTE

Sseyinielnt

rdarly

crror

DECoder to CONsole Parity Error
MKV86-0691

|... v
[o%)

Error

I,._...I

1IBox

1-4

Figure

(IBER)

Bit

Map

Table

1-5

IBER

Bit

Mnemonic

Description

<11>

1IB

Error
while

<10>

ILL

MEM

BRK

MCR

ADR

1IB

Microsequencer,

1IB

<07>

DEC

SEQ

Same

<06>

PRO

REG

DEC

RAM

<04>

CON

DEC

word

(TB, NMI, Cache,
I-stream data for IB.

decoder,

illegal

the

except

detected

module

while

DEC

module

detected

writing

microcode

received

cache

SEQ module

data

for

bad

parity

word

parity

data

processor

parity

processor

from

bus.

low

writing

bad

etc.)

itself

microaddress.

location
of

bit

CBox

DEC

while
<05>

longword

upper

<08>

Descriptions

detected by
prefetching

generated

<09>

Bit

bus.

from

cache

the

data

bus

DEC

module

detected

bad

DEC

module

bus

while

detected
reading a

bad

parity
CLK module

on cons bidi data
processor register.

parity

decoder

RAMs.

<03>

(€SO0

SEQ module

detected

bad

parity

from

the

CS0

RAMs.

<02>

CCS1

WCS

module

detected

bad

parity

from

the

CS1

RAMs.

<01>

CCS2

WCS

module

detected

bad

parity

from

the

CS2

RAMs.

<00>

DEC

CON

CLK module

detected
writing a

bus

1.5.3
The

Clear Error
is a write
The latch is

CER

MCA.

cleared

one

Writing

<7:0>.
not

CPU

while

clock

when microcode
cycle

later.

bad parity on cons bidi
processor register.

exists as
addresses

one to the CER clears the latc
hes
Since
IBER
bits <11:08> only

affected

the

CER

and

must

1-19

cleared

latch

the

that

reside

data

in the INPR
register and is

store

the

IBER

SDF,

by microcode.

they

bits

are

CHAPTER

MICROCODE

2.1

CHAPTER

SCOPE

This

chapter

describes

the

VAX

8800

pipelining.

the

The

Since

and

following

structure

and

assembly

file

format

Microcode

pipelining

the

VAX

8800

are

bit

VAX

controls

essential

field

this

microcode

chapter:

definitions

concepts

the

processor

microcode

pipelining

and

CONCEPTS

organization

concept

covered

Microword

PIPELINE

and

the

are

Microcode

the

structure

presents

topics

Characteristics

how

general

microcode

OVERVIEW AND

8800

pipeline

pipelined

the

machine,

hardware

understanding

and

the

understanding

the

concept

operation

the

CPU.

!
o ———

2.2

VAX 8800 MAIN CONTROL STORE OVERVIEW

The

main

except

control
for

that

interprets

the

requested

commands from the
functions.

for

2.2.1

Microcode

information

The

main

and

resides

Kkernel

are

that

the

14K

8800

are

example,

microcode

16K

control

store

is 16K words deep by
bit writeable RAMs.

RAMs

microcode
are

for

the

console's

bits wide
microcode

Winchester

are

dedicated

available

for

controlling

user-written

code,

and

DIGITAL.

File

microcode

1logically

Structure
consists
grouped

routines

reside

another.

from

143
The

initialization.

routines
the

reside

store
and
controls
CBox section of this

microcode.

all

kernel operations
its own microcode

and Allocation

macroinstructions
and

CBox

words

Microcode

VAX

the

operations,

reserved

2.2.2
The

set

system

Approximately

store

into

during

CPU

Size

control

loaded

CPU
has

main control
Refer to the

CBox

manual

disk

store microcode controls all
CBox functions.
The CBox

certain

microroutines

large

function

that

handle

one

Table

contained

2-1

file

2-1
each

set

into

integer

while

lists
file.

microroutines

separate
all

the

files.

and

memory

For

logical

management

microcode

files

Microcode Assembly

2.2.3

The microcode is initially written in the MICRO2 assembler language
The source code files are then
code files.
source
of
set
a
as
files:
output
ASCII
two
assembled by MICRO2 into
.
.

file

UCODE.ULD - Microcode object (data)
UCODE.MCR - Microcode listing file

The UCODE.ULD file is further processed by a MICRO2 support utility
This file contains
that produces a loadable file called UCODE.BIN.
the binary data that

loaded into the main control store RAMs.

The UCODE.MCR file contains the text from the original source files
and the hexadecimal equivalent of the machine code generated by the
The UCODE.MCR file is available on microfiche.
MICRO2 assembler.
Table
File

2-1

VAX 8800 Microcode Files

Microroutines

Name

For

CHARSTR.MIC

Character string and CRC instructions

CSX.MIC

CSM overlay

CONTROL.MIC
CSM.MIC

PC control instructions
Console support microcode
and user WCS

area

DECIMAL.MIC
EDITPC.MIC
FLOAT . MIC
IANDE.MIC
INTLOG.MIC

Decimal string instructions
Edit instructions
Floating-point instructions
Interrupt and exception routines
Integer and logical instructions

MM.,MIC

Memory management

LDSV.MIC

MULDIV.MIC
MXPR.MIC
PCALL.MIC
MT

Miniies

1Tnadvrn
1instructions

Variable

VIELD.MIC

routines

Integer multiply and divide instructions
Move to/from privileged register instructions
Procedure call/return instructions
Queue

guuuu.m;C
ATIRITED

Load/Save process context instructions

length bit

field instructions

NOTE

There are two other files associated with the
main

control

store:

DEFIN.MIC

and

MACRO.MIC.

required
by
These files contain definitions
Refer
MICRO2 to generate the UCODE.BIN file.

Section

2.2.5.

2.2.3.1
there

Other
are

Loadable

other
initialization:

system

File

Name

CCODE,.BIN

CBox

NMI

DRAM.BIN

IBox

Decoder

SDFDEF.BIN

EBox

Slow

files

create

the

2.2.4

Microword

VAX

8800

Figure

2-1

name

field.

function.

file

RAMs

manner

divided

RAM

similar

into

unique

bit

segment

Table

2-2

that

several

symbolic

format,
(see

the

Chapter

briefly

Convention

function.
indicates

used

fields.

Each

name

indicative

bits

supplied

3),

describes

The

For

that

portion
of

first

and

the

letter

are

assigned

example,

the

logic

means

the

Functionality

bits

with

one

the

symbolic

function

that

field

"I"

element

the

microword

Note

one

field

functionality
Bits

functionality

field

name

of
1in

with

executed.

2-1

while

the
the

field " deals

Figure

name

portion

resides

that

some

are

most

assigned

with

multiple

that

name

1in

than

they

assignment

that

they

names

are

control

one

field

said

have

only

one

CPU

have

vertical

said

several

name

are

control
to

functions.

depends

the

used

The

function

setting

fields.

Certain

microword
other

specifies
unit,

during

controls.

address

bits

horizontal

with

UCODE.BIN,

loaded

more.

Microword

other

also

RAMs

data

microword

"NEXT"

the

Field

microword

the
name

The

generating

the

Naming

for

2.2.4.2

field

field.

field

IBOX.

are

which
major CPU kernel unit (CBox, EBox, IBox) contains
element(s) the field controls.
The rest of the name is a

mnemonic
NEXT

addition

that

microseguencer

assigned

store

Field

indicates
the logic

two

the

each

file,

1is

shows

each

files

Format

field

control

2.2.4.1

generated

microword

function

each

are

UCODE.BIN

microword
the

Files

binary

Destination

These

The

Binary

three

1is

Otherwise,
E SHFTCNT

fields

fields.

the

function

only

valid

E MULDIV

are
For

only

performed
if

1is

the

valid

example,
E

MULDEN

considered

field.

2-3

when
the

the

EBox

field

MULDIV

combination
field,

which

multiplier/divider

enables

the

multiplier.

part

the

larger

047 046 045 044

rar

, 014 (13
, 019 018 ,
028027 026 023 024023022 ,
/7
/7 /7

Wy
g/

SL
7/

L——-cso SPARE
CSO PARITY

I_BRMASK

I_BRTYPE

1_APORT

E_BPORT

—

036 033

7 /7

CS0 RAM SEGMENT

1_USTACK

000

I_NEXT

7 AL
7/

SL
rdvan

L
J/
7z

DY
7

L—-————-I_RTNTRAP

1_DECODER
E_FPSUFL

=7 IA

CS1 RAM SEGMENT
-

E_SHFTCNT

eyl
7 /7

J L
7 /-

< L
r ve

L— E_SX_BY_EN

E_XALUCC_SIZE
Y.
/7 7/

050 049 048

E_SXALU_FN

E_SHFTCNTEN

E_MULDIV

093 094 093

033032

0580370360355 _,,
éfluo . ,,
7
7 /7

L,
P an

067 066 065

E_SHFTSEL

088 087

7 7/

I_WRTADDR

E_ALU

/J//

4///

I——— CS1 SPARE
—— (CS1 PARITY

0g2 081 080 079 078

7 /7

074 073 072 071 070

L —— E_SHFTFPOUT

E_SXALU_FORM

068

E_SHIFT

4///11

E_PEFUNC
L—- E_MULDEN

L—— E_ALUCON
E_ALUCI

E_FPFORMAT
MKV86- 1304

Figure

2-1

Microwocrd Bit

Format

(Sheet

1 of

Ccse
119

L, .,

RAM

13 u2 m 1o

SEGMENT

107 106 105 104 103 102 101 100 099 098 097 096

7z /7

I_MISC

E_WRTEN

fi//lg

l— E_VAWRT

7//L

E_PFLUSH

E_PCCTRL ——,

L— E_RECIPE

E_LDCSL

E_SIGNWR_ROTROP

E_ALUENBP

1_SIZE

G-¢

I_NORET
E_SDWRTEN
C_SCF

C_WCF
142

141

L, .,
7 /

138 137 136

'13%

129 128

125124

4rd

CS2 SPARES

C_RCF

C_MREG

C_MSIZE

7/,L

7//L

7//1

7/,4

L— CSe PARITY

l— I_CHKIV

122121

120

— E_MLT_BYTE_OFF
MKV86-1305

Figure

2-1

Microword

Bit

Format

(Sheet

Table
Bit(s)

Field

013:000

2-2

Name

Microword

Field

Definitions

Description

Contains

the

microword

base
be

fields

address

the

executed.

018:014

I_BRMASK

These

022:019

I BRTYPE

conditional microbranching.

combine

to control multiway

I BRMASK - Specifies which I _NEXT <4:0>
bits (one or more) can be modified to
affect

a microbranch.

I BRTYPE - Specifies which of 16 microbranch condition groups to branch on.
024:023

I_USTACK

Controls microstack operation for
subroutine calls/returns and returns

from

microtraps.
025

I _RTNTRAP

Releases the microPC silo on
from a microtrap routine,

026

I _DECODER

Selects the decoder logic
of the next microaddress.

027

E_FPSUFL

Enables

the

floating-point

returning

the

source

"shuffle"

function.
035:028

I_APORT

Specifies

the

source

for

the

EBox

A port

mux:

® Register file
@ Slow data file
e PC or VA register
e

data

bus

during operand
(RNUM1, RNUM2,
FADS
044:036

E_BPORT

specifier processing
and RLOG registers in

the

MCAs).

Specifies

the

source

for

the

EBox

Port

mux:

®@
e

data

bus

046:045

CS0O0

SPARES

CS0

RAM

segment

spare

bits,

047

CSO0

PARITY

CS0

RAM

segment

parity

bit

(odd parity).

Table

2-2

Bit(s)

Field

Name

049:048

E SHFTFPOUT

Microword

Definitions

Specifies
EBox

the

format

shifter

E_SXALU_

Specifies

the

FORM

input

to,

from,

the

EBox

(SALU,

E _SXALU
FN

E_SX
BY EN

function

Enables

data

output

from

and

format

shift

format
of

and

data

output

exponent

ALUs

XALU).

Function

for

logic.

source
the

Interpretation
the
055:053

(Cont)

Description

the
052:050

Field

code
the

this

for

SALU

the

output

written

from

the

~nrnlsr

field

encoded

and

the

EBox

22133

VUllly

depends

E SXALU
FN

XALU.

SALU

and

bypass
£

valildu

XALU

bus,

CVYVAT TT

on
field.

oA”ALy

AT
FIN

2 ~
1D

encoded with a bypass function.
57

E SHEFTSEL

Selects

source

shifter

64-bit

result

the

Interpretation

the
060:058

E SHFTCNTEN

067:061

E_SHFTCNT

E_MULDIV

the

source

Specifies

The

direct

absolute

(unsigned)

E_XALUCC

SIZE

shift
is

code

for

Specifies
format

the

depends

field.

shift

count

the

treated

value

XALU

the
is

for

the

range

multiplier/divider

enabled

type

generate

data)
correct

condition

Priority

encoder

2-7

function.

the

exponent
required
FP

codes

microbranching.
E_PEFUNC

output.

bus.

floating-point

(F/D or

over/underflow

070:068

E SHFT

the

63.

Function

the

count

field

longword

field

shift

unit i1f the unit
E MULDEN field.
067

this

encoded

shifter's

input

which

shifter

shifter.
to

065:0061

function

Selects
the

data

specifies

for

Table 2-2

Microword Field Definitions

(Cont)

Bit(s)

Field Name

Description

071

E_MULDEN

Multiplier/Divider unit enable.

072:072

FPFQORMAT

Defines

format

data

input

shifter

Or, specifies type
and priority encoder.
of BCD conversion to be performed by
shifter.

078:074

E_SHFT

Shifter function code.

Selects hardwired constant of 4 as input

079

E ALUCON

081:080

E ALUCI

087:082

E ALU

Main ALU function code.

093:088

I_WRTADDR

Specifies address of register file

094

CS1 SPARE

CS1 RAM segment spare bit.

095

CS1 PARITY

CS1 RAM segment parity bit (odd parity).

097:096

E RECIPE

Selects the SALU CC bits that result from

098

E SIGNWR

This bit performs three basic functions:

B port mux.

Selects source of carry bit input to main
ALU,

location to be written.

FP operations as microbranch recipes.

1.
2.

Controls loading of the SALU sign latch.
Enables

checking

the

trap

(if selected by E SXALU FCRM},

SALU.

Indicates data size (byte, word, longword)

)

[o3e]

for size-dependent microbranch conditions.

I SIZE

FP reserved operand

Helps control FP exponent subtraction

ROPTRAP

100:099

ALU

to main

Table

Bit(s)
101

Field

2-2

Name

I NONRET

Microword

Sets

the

NORETRY

the

IBox

hardware

word

every

NORETRY

check

E_SDWRTEN

flag,

which

during

flag

tested

instruction can
machine check.

restarted

Enables

the

VAX

105

E_LDCSL

Loads
the

writing

addressed

function

main

carry

Enables

slow

code

ALU's
bit

the

cleared

first

micro-

macroinstruction.

determine

E_PCCTRL

the

104:103

E_ALUENBP

(Cont)

microcode

106

Definitions

Description

The

102

Field

main

a macrofollowing a

data

the

file

E BPORT

(increment,

carry

for

machine

save

later

field.
load

latch.

PC).

(Saves

use.)

ALU

the

WBus

drive

the

bypass

bus.

110:107

E_WRTEN

Selects

bytes

the

on
file

WRTADDR

Location

field

written

addressed
hardware.

(There

is one E_WRTEN bit per data byte.)
111

E_VAWRT

Enables
EBoxs'

112

I _PFLUSH

writing
VA

Specifies
a

partial

returning

119:113

I_MISC

contents

that

IBox

flush

PSL

CPU

state

Certain

VAX

used

select

tested

the

Bus

IB.

1Issued

service

field

for

latch.

perform
prior

writing:

flags

IPRs
the

PSL

routines.

bits

conditional

2-9

CBoxs'

hardware

control

from microtrap

Miscellaneous

Also

and

bits

macrobranches.

Table 2-2

Microword Field Definitions (Cont)

Bit(s)

Field Name

Description

121:120

I _MDNUM

Specifies that IBox hardware is to supply
the address of the EBox MD register to
receive memory read data.

The

I _MDNUM field overrides the C_MREG

field.

Specifies the cache data size (byte, word,

124:122

C MSIZE

128:125

C_MREG

135:129

C RCF

CBox read functions {memory and registers).

135:125

C_WCF

Memory write functions.

135:122

C _SCF

longword,

I _CHKIV

octaword).

Specifies the MD register to receive

memory read data (overridden by I_MDNUM).

Miscellaneous CBox functions (special

memory reads and writes, TB checks and
writes,

136

quadword,

CBox register writes).

Enables IBox hardware to generate an

integer overflow microtrap if PSL <V> and

<IV>

bits

are both

set.

E MLT

Controls writing least significant byte

141:138

CS2 SPARES

CS2 RAM segment spare bits.

142

CS2 PARITY

CS2 RAM segment parity bit (odd parity).

137

BYTE OFF

from Mul/Div unit to bypass bus.

VI 2-18

2.2.5

Microcode

MICRO2

supports

Definition
all

processor-specific

loaded

the

information
File

two

Name

store

source

MACRO.MIC

before

RAMs.

code

Information

DEFIN.MIC

systems

information

control

Files

VAX-based

The

2.2.5.1

Definitions

valid

Definitions

field

Field

the

name,

the

default

setting

I_APORT

field

for

the
in

with

File

bits

field.

each

certain
data

supply

this

fields

For

DEFIN.MIC

that

DEFIN.MIC

example,
as

data

allow

the

microword
statement.

symbolic

spanned

the

several

DEFIN.MIC
in

and

field.

specify
one

definitions

microword

appears

microword

for

macroexpressions

settings

Definition

microword

assemble

supplied

microprogrammers

supply

requires

can

microprogrammers

files:

considered

field

and
it

Microprogrammers
by

the
the

specifying

field,

and

definition

the

for

the

follows:

| _APORT/=<35:28>,.DEFAULT=<I_APORT/TO>

Field name ——T

Microword bits spanned

Assembler qualifier keyword
Field default setting
MKV86-0723

Figure
The

above

I_APORT

2-2

Sample

definition
to

microword

Microword
instructs
bits

following

default

the

value

paragraphs).
the

field

Definiton

MICRO2

<35:28>

TO as the default for the field
the

Field

and

to
to

value

microprogrammers.

I APORT

assign
the

2-11

automatically
is

not

Field

symbolic

(symbolic values are
MICRO2

use

value

discussed
encodes

explicitly

name
of

in
the

specified

Symbolic

Names

Field Value

|_.‘ -

1
p artia
a
1is
fiel
ORT
the I AP
’.—l

following
The
associated with

Q-

Each microword field definition is immediately followed by a series
wvalid hexadecimal values for the
the
equate
that
statements
of
use to represent the values.
mmers
field to symbols the microprogra
o~

P2 DN R 119

the

{4 4w

Example

General

Purpose

General

Purpose

General

Purpose

General

Purpose

General

Purpose

General

Purpose

General

Purpose

General

Purpose

General

Purpose

General

Purpose

GPR

2-1

Sample

POINTER

STACK

W= O

WO--JOHUTd

Purpose

-e

SP=8E

-9

R12=8C
R13=8D

R11=8B

R10=8A

General

LY}

R9=89

R8=88

Purpose

R7=87

General

R6=86

R5=85

Purpose

-y

R4=84

General

TM9

R3=83

R2=82

Purpose

- e

R1=81

General

~ e

R0O=80

I_APORT/=<35:28>,.DEFAULT=<I_APORT/TO>

Field Value

Assignments

I APORT

equating
definition
value
field
interprets each
left of the equal sign to the hexadecimal value
the
on
the
The semicolon character separates
right.

MICRO2
symbol
the

comment

text.

Assigning

Values

Fields

Once MICRO2 equates hexadecimal values to the field value
the

microprogrammers

can

then

specify

symbols,

settings

field

For example, the following statement encodes a value
symbolically.
of 80 (hex) in the I APORT field:
I _APORT/RO
Microprogrammers

use

the amount of coding
or microcode update
modity the DEFIN.MIC

symbols to represent
that would otherwise
1s

made.

file,

not

(The
all

field
be required

a hardware

microprogrammers

microcode

source

files.)

2.2.5.2
of

Macrodefinition

descriptive statements
microword fields.
By

using

tield,
a

File

macroexpressions,

few

statements

the

and

(reducing

are

the

macro

the
in

that

defined

When

MICRO2

microcode
1.
2.

All

other

values,

the

values

for

each

CBox

encounters

source

file,

definitions

write

longword

WCF/WRITE.V.CHECK,

the

WRITE

LONG

Searches

DEFIN.MIC

for

definitions

values

WRITE.V.CHECK

LONG

microword
values

from

microprogrammer

macroexpression

the

CMSIZE
will

other

macros,

the

CWCF

the

macro

the

CWCF

with

their

and

the

symbols:
field

field

fields

(individual

definition

for

data

C MSIZE/LONG"

it:

hex

by
the
microword
microword
fields
are
commas.
For
example,
the

the

can

followed

for

Encodes

only

The

MACRO.MIC

fields

microword

microword with
required).

field

Searches

CMSIZE

several

Format

the

LONG

use

for

settings

follows:

WRITE

the

microword

consist of a macroname
expression
represents.
quotes and are separated by
instructs

supports

functionally

default

Macrodefinitions

fields
enclosed

MICRO2

fully define a
amount of coding

the

Definition

single-line,

can

and individual
microword.

same

Macroexpression

MACRO.MIC

represent

microprogrammers

Macroexpressions

used

that

macroexpressions

the

which

be
or

field

2-13

encoded
values

value

explicitly

symbols).

default

supplied

Macroexpression

Parameters

Microprogrammers can directly specify settings for microword fields
by
supplying the symbolic values for the fields as parameters in a
macroexpression.
The only restriction is that the parameters
must
be valid symbolic value names for microword fields.
MICRO2
recognizes
the
square
bracket
([])
and
the
"at"TM
(@)
characters
in macroexpression definitions as parameter indicators.
For example,

the macrodefinition:

READ LONG

[]

"C_RCF/READ.V.CHECK,

C_MSIZE/LONG,

C_MREG/@1"

informs MICRO2 that the programmers will supply the symbolic
value
for
the
C_MREG field each time the macro is used by enclosing the
symbol
in
Dbrackets.
The
@
character
in
the
macrodefinition
associates the C MREG field with the parameter.

The following is an example of a READ LONG macro that instructs the
CBox
to
read
a
1longword of data and to store the data in memory
data

LONG

the

[MD1]

Wwhen MICRO2 encounters
1.

EBox.

the READ LONG

[MDl]

macro

it:

Searches MACRO.MIC for the macrodefinition.

Searches

DEFIN.MIC for the CRCF,

CMSIZE,

and

CMREG

field

definitions.

Encodes

the

hex value

READ.V.CHECK

LONG

the

for

in the
CMSIZE

the

CRCF

Relates the [MD1l] parameter
marked by the @ character -

Encodes

hex value

field

4.,

the

symbol:

for

in
the
macro
to
CMREG in this case.

the

MDl

symbol

the

field

the

CMREG

field.

Macroexpressions can have several parameters.
The decimal
integer
following
the @ character in the definition indicates the position
of the parameter in the macro.
If several parameters are used, the
left-most
parameter
will be designated "@1", the one to the right
so

on.

L
i

and

"@2",

113

that

Macroexpression

Classes

Macroexpressions
For

example,

one

group

functions
shown

are

all

1in

another

function

deal

macros

with

2<3

Macrogroup

group.

the

The

MACRO.MIC

transfer

deal

with

file.

functions

are

microbranching

macroexpression

Macroexpression

classes

are

Classes

Controls

Transfer

Data

transfers

Macros

further

multiplier,
XALU,
- PE)

Cache

in
data

that

2-3,

Table

that

while

are
Table

grouped

macros

commands

Memory

CREG/IREG

through

EBox

grouped

and

floating-point

read/write

operations.

Data

transfers

Microbranch

Miscellaneous

functions

to/from

resident

and

(SALU,

CBox,

special

IBox,

and

registers,

functions.

functions:

Set/clear

PSL

Set/clear

CPU

state

flags

decoder

calls

Instruction

Subroutine
Trap

path.

shifter,

functions.

CBox

console

data

ALU,

bits

calls/returns

returns

Others

Tables

2-4

2.2.6

Microcode

For

through

structure,

2-8

detailed
refer

(EK-KA88E-UG)
.

list

examples

the

various

macroclasses.

Documentation
description

the

VAX

8800

2-15

the

Microcode

VAX

8800

microcode

Interpretation

Guide

Table

Sample Register Transfer Macros

2-4

Macroexpression

CPU Function

ALULKC>

Set ALU carry bit based on sum of A and

<- A[]

+ BI]

inputs

<- A[]

F[]

<- A[].SL.[]

Result

is not

of A and B port inputs in a

sum

Store

+ B[]

F[]

ALU.

fast data RAM register

(EBox).

shifted A port input in a
left
Store
fast data RAM register. Shift amount is

given in the E_SHFTCNT field.
F[]<15-0>

<- B[]

& VA <- A[]

s{]

<- A[]

SHFT

VA &

FI]

F[]

FLUSH

<15:0>

Load

PC and

slow data RAM register

port

Load
RAM

<- A[}

WRUS

<- A[]

<- A[]l

+ BI]

+ B[]

shift

EBox

(EBox).

count latches from A

input of main ALU.

shift count latches and slow data
register

VA
Lcad
register,
from

VA & WBUS

registers (EBox) with

I-stream data;
new
for
start address
initialize the instruction buffer.

Load

S{]

from B port into a

Store logical OR of A and B port inputs

<- B[]

bits

fast data RAM register.

<- A[].OR.B[]

SHFT

Store

Load

ports;

from B port.

RAM
data
fast
a
register,
register
RAM
data
slow
a
and

port.

also output

with sum of A and B

result to WBus.

Output sum of A and B ports

2-16

to WBus.

Table

2-5

Sample

Cache

Command

Macroexpression

CPU

CHECK

READ

Probe

for

read

CHECK

WRITE

Probe

for

write

READ

LONG

ACCESS
ACCESS

[]

Function

Read

longword

EBox

memory

address
READ

LONG

MDNUM

Macros

above,

IBox

access.

and

data

access.

store

given

except

MDR

hardware

the

C MREG

address

(selected

LONG

WRITE,UNLOCK

LONG

Table

2-6

longword

memory.

Write

longword

and

unlock

CREG/IREG

Macroexpression

CPU

CLEAR

IBCER

Clear

IBox

READ

CONSOLE

Read

console's

STATUS

CREG

[]

and

reside

Read

CBox

IBERI

READ

RXDB

WRITE

DATA

INOP

CBox

the

error

transmit

status

IREG

memory.

the

IBox

Read

the

console's

the

Write

field.

error

2-17

and

receive

(Registers

given

IBox

address

receive

data

other
the

C_MREG

given

buffer.

processor

IBox).

resident
is

The

the

interrupt

(resident

registers.

resident

Read

Write

[]

CLK module.)

address

given

Macros

field.
READ

Function

control

READ

MDR

I _MDNUM

Write

Sample

field.

field).
WRITE

data

(MDR).

I MISC

Table

2-7

Sample Microbranch Macros

CPU Function - take microbranch based on:

Macroexpression

Example of a pseudo macro.

(

ACCESS

ALLOWED

)

N/A.

ACCESS

ALLOWED

Status returned by CBox after a

)

ALUKC>

+ WBUSKN>

INT PEND

)

PSLLC>

WBUSK3-0>

<C>

state

flag

Interrupt pending

PSL

WBUS

<C>

associated

code

flag.

bit.

bits

* pseudo macros are programming
debug

bit.

Main ALU <C> bit and WBUS <N> bit,
CPU

)

FLAGO

check.

TB access probe

Main ALU

ALULKC>

with

<3:0>.

aids

use

microprogrammers

dynamic microbranch conditions.

While the pseudo macros appear in the microcode listing

file,

they do not generate actual code.

The programmer includes a pseudo macro in a microword 1f the
word is to set up a dynamic microbranch condition to be tested
by a later microword. A MICRO2 support program checks all
such

microword

pairs

to ensure that the word that tests the

condition is at least three CPU cycles removed
that

set

not,

microcode

the

from

the

one

the condition (microcode pipeline reguirement).
support program reports an error when the

1is assembled.

Note that pseudo macros and true microbranch macros have th
The only difference is that the pseudo
same basic format.
s instead of question marks.
parenthese
macros are enclosed in

Table

2-8

Sample

Miscellaneous

Macros

Macroexpression

CPU

CALL

Subroutine call.
Push address of current
microword on microstack, get start address

[]

CHECK

ROP

Function

called

routine

from

for

integer

overflow

Check

for

floating-point

trap;

data

type

Check

A.FD

CLEAR

FLAGO

Clear

CPU

state

CLEAR

ALL

Clear

all

CPU

CLEAR

TRAP

Clear

microtrap.

END

FLAGS

INSTRUCTION

not

restart

for

EXIT

End

current

field.

trap.

reserved

flag

state

flags.

Release

trap

silos,

microwords

(see

TRAP

macroinstruction,

decode

address

supplied

Return

from

silos,
entry

instruction.
by

request

instruction

FORCE

MDVALID

GOTO

[]

GOTO

Mark
Jump

DECODER

all
to

new

SETCC
SET

[]

TRAP

memory

Get

address

from

next
the

decoder.

trap

silos,

(see

macro).

data

address

start

microword

microwords

registers

microroutine.

starting

RETURN

EBox

Release

trapped

CLEAR

has

executed
NOP

microtrap.

restart
for

entry

macro.)

decoder.
EXIT

operand

F/D-float.

trapped

TRAP

I NEXT

new

valid.

field

routine.

microword

instruction

decoder.

nothing.

Return

from

subroutine.

popped

from

microstack

[]

Set

PSL

FLAGO

Set

CPU

state

bits.

2-19

flag

Logically

with

Recipe
0.

address

I NEXT

field.

I MISC

field.

2.3

MICROCODE

PIPELINING CONCEPTS

commonly
technique
design
VAX 8800 CPU operations are based on a
microcode
the
presents
section
This
pipelining.
microcode
as
known
section
This
pipeline concepts common to most pipelined machines.
pipeline.
8800
VAX
the
of
characteristics
the
discusses
Pipelining Rationale

2.3.1

The major advantage to microcode pipelining is that it enhances the
speed of a CPU by allowing more than one microword to
operational
be active at any given time.

In a pipelined machine, the microcode can control several CPU logic
the hardware may bDe
For example,
simultaneously.
elements
on previously
computation
a
perform
data,
instructed to read new
all at
computation
previous
a
of
result
the
store
and
data,
read
a
yields
hardware
the
of
use
efficient
more
This
the same time.
machine.
nonpipelined
a
over
performance
in
substantial increase
Pipelined Versus Nonpipelined Machines
2.3.2
Each microword of a microcode-controlled CPU must,

in some

manner,

perform three basic operations:

1.
2.
3.

Read data from memory or from a register
Modify the data (add, shift, etc.) if required
Write the result to memory or to a register

These operations are generally considered to be performed during
what are known as a "microcycles" with each microcycle being one or

more CPU clock cycle

in duration.

between microwords
Figure 2-3 illustrates the timing relationship
2-4 does the same
Figure
CPU.
a nonpipelined
of
and microcycles
three
takes
it
that
assume
figures
Both
for a pipelined CPU.
look-up
microaddress
microcycles to execute one microword (ignoring
time,

data access time,

Table 2-8 lists the
types.

traps,

major

stalls,;

differences

etc.).

between

the

two

machine

Microcycles

Microword N

RD | MOD | WRT
Microword N+1

|MOD |WRT
Microword N+2

RD | MOD | WRT

MKv86-0724

Figure

2-3

Basic

Time

State

Diagram

NonPipelined

CPU

Microcycles
4

RD | MOD |WRT | Microword
N

RD | MOD | WRT | Microword N+1

RD | moD | WRT| Microword N+2
Normal pipeline state
MKV86-0725

Figure

2-4

Basic

Time

State

2-21

Diagram

Pipelined

CPU

Table 2-9

Pipelined/Nonpipelined CPU Comparisons
Pipelined CPU

Nonpipelined CPU

New microword

New microword started every

started

every three microcycles.

microcycle.

Serial operation - one
operation per cycle.

Parallel operation - three
operations per cycle.

hardware

Majority of hardware active

Majority

in each cycle.

idle in each cycle.

number of
Performance Factors - Although it takes the same
r CPU type, a
microcycles to execute any given microword in eithepipel
ined CPU
a
substantial increase in performance is gained in examp
le, with one
since the operations are "overlapped." For a nonpi
pelined CPU
microword executed every three microcycles,
oword routine. A
would take nine <cycles to execute a three-micr
factor ratio of
pipelined CPU would take only five, a performance ne
ases, the
1.8 to 1. As the number of microwords in a routi ofincre
3 to 1 1in
performance factor ratio also increases, to a limit
2.3.2.1

the case of a three-stage pipeline.

2-22

2,4

VAX

8800

PIPELINE

CHARACTERISTICS

Microcode pipelining in the VAX 8800 processor is
of
the
precise
timing
supplied
by
the clock
latch-based

CLK

and

the

CLK,

correct

2.4.1
The

CPU

VAX

from

design

8800

signal.
cycles

start

sequence

and

clock

edge
an

The

nominal

clock

issuing

the

VAX

8800

2.4.2

CPU

elements
The

data

timing
The

and

timing

through

signals,
the

(Refer

CLOCK

the

either

the

CBox

CLK;

Figure

nanoseconds.

command

from

and

period

the

The

rate

can

U
based

coupli

together

with

modified

(Refer

logic

elements
the

Ao T

required

CPU

latches

serve
by

cycle,

the

requires

opposite

clock

"A"

can

latch

lower
data

data

buffers
the

only

portion
can

l.llg

latches.
(under

between

CLK

from

Processed

logic

Clocked

into

Obtained

from

Processed

another

the

second

latch

and

transferred
For

elements.

the

transferred

Figure

between

example,

2-5,

data

"B"

During

CLK

latches

previously

latch.
single-CPU

element

latch

the

made

cycles

microcycles

latch

latch
logic
logic

element
element,

available

for

the

data

clock

NOTE

Clock

logic

microcode

the

l—Speeu,

The

be:

Obtained

phases.

processed

the

functions

either

data

another

Design

strobed

CLK

clock

Guide.)

MT D Ly
design

design

EBox

2-5,)

console.

are

hardware

time

CLK

the

data

the

time.

considered

the

Refer

Wi+~

propagated

proper

edge

latches

clock

CLK.

User's

perform

hardware

stored

primary

signal.

strobed

Once

cycle

leading

rate

Hardware

control),

the

start

i1
LY
hardware

combinational

cycles

SET

Console

CPU

clock
on

data

The

because

subsystem

Cycle

The

hardware.

that

CPU

1IBox

the

ensure

Clock

leading

possible

will

the

remaining

2-23

referred

text.

then

input

cycle.

le——15ns -—-»I

Clock Cycle

-l

45ns

A CLK —‘I
B CLK

DATA—/

LOGIC

ELEMENT

0 next

T B logic

A CLK

B CLK

A CLK

element

Note: Cbox and Ebox clock cycles start on an A CLK,
ibox cycies start on a B CikK.

MKVB6-0728

Figure 2-5

Basic CPU Timing

VI 2-24

2.4.3
VAX

Relationship

8800

execute

can

(ignoring

stalls,

correspond

modify,

the

and

associated

cache

Between

microwords

basic

write).

with

Figure

and

three

traps,

CPU

etc.).

functions

The

decoding

2-6

and

modify,

other

Functions

five

microcycles

Three

the

following
write

Cycle

CPU

Function

Read

Select

the

data

temporary

Modify

Perform
data

Write

source
path

CPU

must

perform

two

cycles

are

optional

and

performing

the

temporary

1IB

Decode

addition

optional
the

but
Otherwise, it

data

the

basic

input

GPR,

microword,

there

the

microcode

operation

result

1in

(memory,

the

etc.)

the

specified

GPR,

microcode

etc.)

that

cycles

associated

with

decoding

buffer,

I-stream data

cycle
is

hardware.

are

certain

etc.)

read/modify/write

cycle

(read,

and

microword.

logical,

with

cycles

Cycle

the

instruction

decode

time,

specified

the

concerned

(memory,

(arithmetic,

Store

are

destination

2.4.4

table

microcycles

these

the

macroinstructions

and

EBox

The

from

operations,

read,

from

Microcycles

take

precedes the three basic
microword
cycles
in
only
wused
during
macroinstruction
execution.
effectively treated as
a
"no-op"
cycle
by
the

NOTE

Figure

2-7

Refer

Figure

for

illustration
2-9

representation.

2-25

for

purposes
more

only.

precise

Microcycles

3rd —>
jt— 15t —>{e—2nd —>j&——

Clock phase —>A

READ

MODIFY

WRITE

Read data from a GPR, microcode

temp register, or from memory

Perform specified operation
(add, shift, etc.), if any

Write result to a GPR, microcode

temp register, or to memory

MKV86-0727

Figure

2-6

Microcycles/CPU Functions

VI 2-26

2.4,5

Canonical

Since
the

Time

States

the microcycles
time

referred

at
as

which

its

the

CPU

canonical

microwords
event

time

the

occurs

pipeline
a

given

overlap,

microword

state.

NOTE

The

term

VAX

2.4.5.1

"canonical"

8800

the

hardware

set

the

rules

used

engineers.

A Canonical

the

time

period

from

the

leading

edge

opposite

phase

is,

the

are

both

Note

Figure

states:

even

the

time

periods

considered

2-8

that

states
= ela
T o

2.4.5.2

Overlapping
has

being
next

1its

one

start

Time
own

third,

Figure

and

With

several

the

hardware
to

States

For

2-8

CLK

are

CLK

canonical

leading

and

time

edge

phase.

from

CLK

one
That

CLK

into

two

time

CLK

pulse,

odd

pulse .

Figure

2-8

state

the

example,

divided

start

time

from

also

State

states.

states

removed

also

shows

that

each

periods

with

each

corresponding

time

state

T10

the

time

second

the

first

microword,

time
of

(top)

forth.

microwords

designers

the

CLK

canonical

microword.

microword

the

time

(oL S & W5

cycle

Time

microcycles

numbered

time
~ LAl

microword

from A

canonical

numbered

relative

design

reference

the

clock

the

defined

1is

the

with

refers

Definition

state

CPU

microword

process
always
just

refer

entering

time,
to

the

avoid

timing

confusion,

CPU

events

pipeline.

NOTE

Canonical
only.

assumed

Figure
console.

during

2-8
The

that

was

TO
1is

1is

shown
to

<considered

for
be

reference
T2 of the

microword.

the

address

loaded

address

canonical

time

into
each

time

the

first

microPC

subsequent

the

2.4.6).

VI 2-27

microword

address

microword

shown

latches

microword

1is

the

generated

(see

Section

Clock

B
MODIFY

READ

DECODE | ADR

WRITE

)

Microaddress iook-up time

Decode i-stream data from
the IB (optional cycle)
MKV86-0728

©C——%

Figure

1IB Decode Cycle

2-7

/i\

,LI\

E|3

DECODE

ADR

READ

DECODE | ADR

-a«—

-«———Time state

Clock phase

MOD

WRITE

READ

MOD

WRITE

READ

MOD

WRITE

READ

MOD

WRITE

READ

MQD

DECODE | ADR

DECODE

ADR

DECCDE | ADR

WRITE
MKV86-0729

Figure

2-8

Canonical
Vi 2-28

Time

States

State

-his

except

case,

canonical

"igure

2-9

the

pipeline.

each

‘elative
hat

the

when

TO0

illustrates

time
to
CPU

Table

state.
the
is

the

pipeline

CPU

executing

are

included.

the

CPU

2-9

The

top

active

the

event

briefly
time

microword
process

timing

shown
of

executing

canonical

T3
1In

several

the

given
the

from

macroinstruction.

for

describes

states

T10

Events

considered

N
Ne)

Time

microword

.4,.6

that

the

table

1in

figure.
a

microwords

events
It

occur
are

assumed

macroinstruction.

€

]

MICROWORD

| Decoder I Decoder
!

b e e

e o

Uraadr

€so

| Cycle 1 Cycle
b

File
Reads

Generate

r ————— I

cs2

Sherd | ek | e

Har
e

U-adar | Reads

€S0
Lookup

Half

Cs2

CS1

File Writes

ALU Operations

Cache

Operations [Operations

Lookup

e e
—

pe-¢

e e

File

Generate

T
Decoder | Decoder
P! Cyce
F\llrcs:3 || S%Xglsd
|

Cache

Operatons |Operations

Lookup

— —

r -TTTZvY T

N+1

File Wrntes

ALU Operatons

——————

cso

| CYde
b. Cycle
| Second
First

N+2

i
|

b e

e o

Une();;

Reads

CSs2
Lookup

-addr

Lookup

Half

{
i

Haif

File

Generate

§ Decoder | Decoder

Cs1
Lookup

ALU Operations

File Writes
Cache
B
Operations |Operations

—

TTT
Ir' T
Decoder 1 Decoder
|

Cycle

CS1

Lookup

e e

U-addr

Lookup

| Second
Half

!U First
Hanr

N+3

Generate
”eg‘d

CS0

Cycle

e o

File
R(Aa(lis
o

CSs2

]
File Writes

ALU Operations

Lookup

Cache

Opcrations [Operations

r
| Pecoder | Decoder

|| Se\éoncl
FIVFSI
Half
Half

Cycle

N+4

I
|

Cycle

e e

Lookup
Cso

Generate
Unes:j

Filo
Reaéjs

Csi
Lookup

CS2
Lookup

-addr

ALU Operations

File Writes
Cache
TM
Operations |Operations

——
AR =B

Figure

2-9

VAX

8800

Pipeline

Time

State

Dlagram

ObLYE

Time
TO

State
T1

Table

2-10

CPU

Events

Pipeline

checks

I-stream

address

time

the

outputs

the

TS5

required

are

the

decoder

(if

currently

data

service

enters

generated

any)

the

for

micro-

specifier.

specifiers,

the

address

microaddress

three

control

store

CS0

RAMs

start

cycle

for

RAM

outputting
the

decoder

for

the

latched

CS0O

RAMs

the

microword

bits

microaddress

passed

microPC

for

(second

RAM

start

cycle

RAM

RAMs

outputting

the

microword

EBox

Microsequencer
from

CSO

microword

bits

latched

IBox

examines
to

passed

for

(third

start

cycle

bits

for

the

routed

the

bits

address

<26:00>
of

executed.

microaddress

RAMs

and

microword

determine

latches

write

address

segment).

logic.

Current

CS2

the

microword.

and

segment

microword

for

microword.

latches

RAMs

(first

segments).

Current

CS1

being

address

the

entry-point

latches

CS52

(Note:

considered

enabled.

address

CSO0

write

longword.

specifier

entry-point

to
more

the

appropriate

and

microPC

CS1

its

routine.

modify

longword

microword.)

I-stream

operation

there

new

decoder.

generates

read

the

Decoder

code
to

code

routine
It

for

Events

decodes

generally

longword

write

1is

1IB

macroinstruction

generates

time

States/CPU

accept
so,

preparation

New

processed

can

canonical

data.

Time

RAMs

outputting

the

microword

microword.

2-31

microPC

RAM

address

segment).
bits

for

the

Table
State

Time

Té6

(cont'd)

(Cont)

Pipeline Time States/CPU Events

2-10
Event

CS1 RAM microword bits latched and routed to the
appropriate EBox logic.

CS0 RAM microword bits select source of
be

data to

input to EBox data path.

Microaddress of next microword to be executed is
address latches of CS0O RAMs;

latched in microPC

-3

new microword started.

CS0 segment completed.

CS1 segment controls the first halt cycle of the
EBox data path operation (main ALU, multiplier/

divider,

shifter,

etc.).

CS2 RAM microword bits latched and routed to the
appropriate CBox, EBox, and IBoOX logic elements.
T7

CS1

segment

completed.

half

CS2 segment controls second

cycle

EBox

data path operation.

CBox receives and decodes cache command (if any)

T11

segment.

g iste r w
i o ns
1C

—~

cfm

H\fi

ert

T10

CS2

s EBox
O
egm ent control
/write
a /wri
rms cache r read

TI10

CBox

performs any virtual to physical address
This operation is
(Note:
translation required.
controlled by the CBox, not by microcode.)

-3

[6 9]

supplied

ites.

CBox

any).R

CBox outputs data to EBox if memory read request

(CBox generates a stall condition if
was made.
required data is not in cache and must be
the
retrieved from main memory.)

Pending

microtrap

conditions (if any) signaled

to IBox microtrap logic.

CHAPTER
IBOX

3.1
This

FUNCTIONAL

CHAPTER SCOPE

chapter describes

the

operation

the

IBox

hardware

diagram
level,
It
includes functional block diagrams of
IBox logic section and discusses how the hardware interacts
various microword fields where applicable.
Certain sections of this chapter, such as the one that
macroinstruction
decode process, include more detailed
to better illustrate the operation of the hardware.
To

DESCRIPTION

understand

the

interaction

recommended

avallable
@

@
@

the

that

the

between

the

following

hardware

VAX

8800

and

the

reference

Microcode Listings
Microcode Interpretation Guide, EK-KA88E-UG
Machine Check Interpretation Guide, EK-KA88H-UG

3-1

block

discusses
the
block diagrams

reader:

the

each major
with
the

microcode,

material

3.2

CONTROL STORE LOGIC

The control store logic resides on the SEQ and the

consists

the

WCS

modules.

16K by 1 bit writeable RAMs, which contain the main

CPU microcode, and the necessary RAM address and data latches.

Figure 3-1 is a simplified block diagram of the control store logic.
3.2.1

Control Store RAM Segments

To implement the microcode pipeline effect, the control store RAMs are

physically divided 1into three segments known as CS0, CS1, and CSZ2.
The CSO segment resides on the SEQ module, the CSl1 and CCS2 segments
both reside on the WCS module.

Each CS RAM segment corresponds to a different cycle of the microword.
CS0 supplies the microword bits for the read cycle, CS1 for the modify
cycle, and CS2 for the write cycle. The following table indicates the

primary CPU functions controlled by each segment.

Table 3-1

Control Store RAM Segment Functionality

Segment

U-Word Bits

CsO

<047:000>

CPU Functions

Next micro-PC address formation.

Microstack operations.
Register

Csl

<095:048>

CS2

<142:096>

file

reads.

Data manipulation operations.

file write set-up.

Cache and TB operations.
Condition code setting.
Miscellaneous operations,

Refer to Chapter 2 for descriptions of the microword bits supplied

each

RAM

segment.

3-2

CS0O RAMS
16K x 48

RAM WRITE DATA <7:0>

DATA IN

CSO WRT
CONTROL
WRITE SEG ID <2:0> ———————»

€SO Microword Bits
CSO SEG SEL <b5:0>
\

—

CSO WRITE STROBE ——————

CSO DATA
LATCHES

IA
£€-¢

(unlatched fields)

SEG WRT
STROBES

CSO ADR
LATCHES
UPC <13:00>
DEC UADDR <13:00>

ewsmsse{

UPCO <13:0>

CSO Microword Bits
(latched fields)

ADDR

"MICROTRAP

CONS UADDR REQ

SEL

DECODER SELECT

B CLK

STALLED A CLK

(T3)

(T4)

~
m—

UPCO <13:0>
To CS1 Adr Latches
Sheet 2 of 2
MKV86-0697

Figure

3-1

Control

Logic

Simplified

Block

Diagram

(Sheet

CS1 RAMS
16K x 48

DATA IN

RAM WRITE DATA <7:0>
CS1 WRT

WRITE SEG
ID <2:0>

CS1 DATA

CONTROL
e

cs1 WRITE ——

STROBE

CS1 SEG
SEL <5:0>

LATCHES

SEG WRT
STROBES

CS1 Microword Bits

:::::>

CS1 ADR

7-¢€

LATCHES

UPCO <13:0> el

UPC1 <13:0>

B CLK
(T5)

ADDR

From Sheet
1 of 2

STALLED A CLK
(T4)

CS2 RAMS

——

16K x 47

=mp-1

RAM WRITE DATA <7:0>

DATA IN

CS2 WRT
CONTROL

WRITE SEG

ID <2:0>

CS2 SEG

CS2 WRITE —

SEL <5:0>

SEG WRT
STROBES

CS2 ADR
LATCHES

CS2 Microword Bits

—

STROBE

UPC2 <13:0>

CS2 DATA
LATCHES

ADDR

D
A CLK
STALLE
(T6)

MKV86-0698

B CLK

(T5)

2)
Figure 3-1 Control Logic Simplified Block Diagram (Sheet 2 of

3.2.2

Control

Refer
way

to
1n

3-1.

which

the

propagated

The
of

through

address
two

Store

Figure

RAM Addressing
The

the

address

effect
the

latches

microword

Source

3-2

Logic

direct

microword
the

result
to

RAM

executed

Microaddress

Signals

the

executed

segments.

derived

from

one

Decoder

DEC

Microsequencer

UADDR

state

the

DECODER

is
the
primary
microsequencer is
asserted,

the

UPC

Sources

Comment
Entry

<13:0>

The

sources:

Table

pipeline

address

point

microaddresses

microroutines

<13:0>

SELECT

for

that:

Process

operand

Execute

macroinstructions

Service

special

All

input

specifiers

conditions

other microaddresses.

the

CS0

RAM

address

latches

factor
in determining whether the IB decoder or
to supply the next microaddress.
If the
signal

decoder

selected.

Otherwise,

the

the
is

microsequencer

selected.
The

selected

canonical
propagated

CS2

address

3.2.3

The

microaddress

the

Control
one

the

microword

CSO

1in

appropriate

CPU

Data

time

are

the

lookup

latches

CS0

RAM

cycle).
T4

(CS1

address

The

latches

address

lookup)

then

the

into

data

and

lookup).

Latches

each

after

read

latches,

logic

(CS0O

(CS2

RAM

bits

data

output

canonical

the

loaded

address

Store

bits

latches

stored

CS1

latches

microword

the microword

the

segment
segment

time

microword

elements.

RAM
the

3-5

and

bits

are
is

clocked

read.

latched

are

then

For
at

example,

T4.

routed

Once

the

nt are not latched
Note that microword bits <25:00> from the CS0 segme
with the generation of
in the €SO data latches. These bits all deal
to, and latched 1in, the
the next microaddress and are fed directly
This ensures that the microsequencer will be
microsequencer logic.
canonical T4 and have it
able to compute the next microaddress duringical
T5 (T2 and T3 relative
ready for the CS0 address latches by canon
to the next microword).

3.2.4

Loading The Control Store RAMs

and is 1loaded
The microcode resides on the console's Winchester disk
into the CS RAMs during system initialization. Figure 3-3 shows the
CS RAM load path.

NOTE

le
The CS RAM load process is covered 1in the consothe
of
ights
highl
the
Only
section of this document.
process are presented here.

bidirectional Cons
The RAMs are loaded a byte at a time from thee 8-bit
DEC module. The
the
to
modul
CLK
Bidi Data bus which 1links the
load process by
the
ols
contr
e
console interface logic on the CLK modul
Data bus to
Bidi
Cons
the
over
passing commands, addresses, and data
the gateway control (GWYC) MCA on the DEC module.

There are three basic steps involved with loading the CS RAMs:

Write address of the microword to be loaded in the micromatch~

Write data to the selected microword a byte at

Verify parity of each microword loaded.

time

over

the Cons Bidi Data bus.

microaddresses are 14
3.2.4.1 Load Control Store Microaddress - Since
only 8 bits wide, the
1is
bus
Data
bits wide and the Cons Bidi
ter in slices as
regis
match
micro
microaddresses are loaded in the

»)

-t

3-2.

F—

shown in Figure

5 MICRO-PC BITS

T— 11 = LOAD CS ADDRESS <14:10>
10 = LOAD CS ADDRESS <09:05>
01 =LOAD CS ADDRESS <04:00>

MKV86-1255

Figure

Microaddress

3-2

Bit

Slices

For

Micromatch

The

field

micromatch

points to
register.

only be set up once
micromatch register
Note

bit

that

14,

3.2.4.2

bit

The
WRT
GWYC

The

from

Data

the

CSO
CS1

RAMs

CS2

RAMs

RAM

CS1l,
SEG
MCA

CS2

<2:0>

through

all

top

address

slice,

which

microword.

Selected

RAM

are

WRITE

into

signals

the

specify

control

are

loaded

Bidi

Data

byte

the

the
need

the

remains

RAM

address

latches.

would

become

address

Data

for

each

microaddress

order:

bus.

time,

Data

First

Second

Third

CSo0

CSs1

CS2

<047:040>

<095:088>

<142:136>

<039:032>

<087:080>

<135:128>

<031:024>

<079:072>

<127:120>

<023:016>

<071:064>

<119:112>

<015:008>

<063:056>

<111:104>

<007:000>

<055:048>

<103:096>

RAM

bits

data

are

segment

"don't

banks

select

the

within

RAM

chips

segment
the

each.

load,

segment.

The

the
The

signals.

writes

in
and

address

following

bank

consecutive

that

the

STROBE

Cons
with

significant

The

Address

segments

divided

signals

supplies

RAMs

clocked

segments

the

slice
order

RAMs

and

each

the

into

location

Note

for

and

bit
any

used.

Write

loaded

CS0,

not

the appropriate microaddress
The
address may be sent in

cares".

3-7

most

less

significant

loaded

the

Cons

bits)

than

the

Bidi

bits

byte

selected

Data

first,

RAM

bus:

wide,

the

most

RAM WRITE DATA <7:0>

CONS BIDI DATA —] XCVR

WRITE SEG ID <2:0>
cSo WRITE STRORE

CONS CMD FLAG
CONS STROBE

GWYC
MCA

WOV

VYT

CS1 WRITE STROBE

CS2 WRITE STROBE

CONSOLE REQUEST

SET MICROMATCH REG

MICRO

MATCH

|——— UPC <13:00>

REG.

UBRS MCAS

Figure 3-3

Control Store RAM Load Path

3-8

MKV86-1256

3.3

MICROSEQUENCING

Each microword contains several fields that either contribute
to
the
formation
of
the next microaddress or inform the microsequencer when
to select one of several
alternate
address
sources,
This
section
overviews
the
microsequencer
hardware
and
describes
the
various
microsequencing methods.

3.3.1
Refer

Microsequencer
to Figure 3-4.

Hardware
The
microseguencer

microbranch
slice
(UBRS)
by 15 bit microstack.

MCAs,

a microtrap

consists
(UTRP)

of
MCA,

5
and

identical
a

16 word

3.3.1.1
Microbranch Slice (UBRS) MCAs - The UBRS MCAs are responsible
for
determining
the address of the next microword to be executed and
for supplying the address to the CS0 RAM address
latches.
The
next
microaddress may be derived from any of the following sources:
®
e
®

Current microword
1IB Decoder
Microstack

Microtrap

VAX

logic

Console

The UBRS MCAs multiplex all address sources except the one from the IB
decoder.
The address from the decoder and the one from the UBRS MCAs
are multiplexed by the CS0 RAM address latches.
Each UBRS MCA handles a 3 bit slice of the microaddress, a total of 15
address bits.
The low 14 bits become the UPC <13:00> lines fed to the
CS0 RAM address latches, the 15th bit is unused.

3.3.1.2
Microtrap (UTRP) MCA - The UTRP MCA receives and
prioritizes
all
CPU
microtrap
conditions
and
supplies
the UBRS MCAs with the
microvector of
the
highest
priority
condition
present.
It
also
generates
the
address
and
control
signals for the microstack, and
notifies the rest of the CPU hardware when a microtrap has occurred.

3.3.1.3
Microstack - The microstack supports the subroutine call
return
functions
of
the
microcode.
Subroutines may be nested
depth of 15
<calls,
after
which
the
microstack
wraps
back.

and
to a
The

microstack
operates on a last-in/first-out basis which means that
last address pushed onto the stack is the first one popped off.

the

3-9

DEC UADDR <13:00:>
FROM IB DECODER

N1
I_NEXT

I_BRTYPE,

|_USTACK,

I_BRMASK

[_RTNTRAP
1|

LATCH

T2
T2

MUX

Cso
cso.

UPC <13:00>

>
SPECIAL MICROBRANCH CONDIT!ONS\
OTHER MICROBRANCH
ROBRANCH CONDITIONS
CO

:
73 [UPCA <13.0>
>

B CLK
MICROBRANCH

CONSOLE REQUEST

LOGIC

SET MICROMATCH REG

5
UBRS

RAM WRITE DATA <8:0>

MCAs

MICROMATCH

=
.

|_DECODER

DECODER
o

GLOBAL TRAP

MICRO-VECTORS

‘

MICRO-STACK POP

PUSH

MICRO
STACK

16 x 15

MICRO-STACK POP

RAM

MICRO-VECTORS
——

DECODER NEXT

h
MACHINE CHECK MICROTRAPS

POINTER

OTHER MICROTRAP CONDITIONS

l DECODER MARKER
MICROBREAK

MICROTRAP

WRITE ENA

LOGIC

GLOBAL UTRAP

%RAP

UTRAP RET STATE

NEW INSTRUCTION

NORETRY FLAG

STALL

SPEC MDNUM <2.0>

INTERNAL CPU INIT
PSL IV

DISABLE TRAPS

BLOCK WRITES

NO RETRY FLAGS

Microsequencer

3-4

Figure

Logic

N TP

3.3.2

Normal Microcode Flow
microsequencer normally selects the I NEXT
field
of
microword
as
the next microaddress unless instructed to
(modify the address based on a microbranch
condition, pop
from the microstack, select a microtrap
vector, etc.).
The

Refer

segment

Figure
at

UBRS

MCAs

the

other

the

I _NEXT

MCAs

T4.

field

3.3.3

1IB

decoder

field

current

and

become

time

various

the

1is

read

microword

control

the

field

UPC

(T3

the

TIf

<13:00>

address

CS0

latched

UBRS

signals

current
otherwise

the

microaddress.

I NEXT
time

from
and

frame,

Supplied

the

prior

Decoder

I NEXT

fields

output

latches

The

The
T3

During

microword

will

address

3-5.

canonical

+the

RAM

MCAs

the

check

determine

so,
to

the

UBRS

CSO

RAM

microword).

Microaddress

responsible

for supplying the
entry
point
(first)
microroutine that processes an operand specif
ier
of the current macroinstruction.
If more than than one
microword
1is
required
to service a specifier, the microsequencer will
generate the
additional addresses for the specifier routine
.
Once
all
specifiers

microaddress

are

processed,

execute

Note

code

that

supplied

instruction

3.3.4

RAM

will

supply

the

entry

point

will

only

select

address

for

the

decoder

instruction.

address

the

will

select

decode

latches

I_DECODER
the

bit

the

current

microsequencer

process

Table

3-3.

covered

supplied

later

microword

this

the

set.

address.

chapter.

Microbranching
to

The

BRTYPE

Figure

UBRS MCAs
modify

bits

decoder

the

CS0

they

Refer

(one

the

each

address

Otherwise,

The

for

possible

and

BRMASK

and

microword

fields,

combination,

result

the

allow

the

to test up to five CPU hardware conditions at a time and to

the

3-6

=zero)
the

I_NEXT

field

the

based

the

tested conditions

field,

allowing

target microaddresses.

the

3-11

test.

are ORed with

UBRS

MCAs

the

The

state

low order

generate

5
32

I_NEXT

UPC <13:00~

W
s

> mMux| T3 UPCA<13:C#)>

CSO
RAM

B CLK

UBRS MCAS
MKV86-12568

Figure

3-5

Normal

I NEXT

Field

Addressing

Microbranch
(some

groups

conditions
have

conditions,

the

slice

are

less

one

divided

than

per

groups

conditions).

group,

branch-sensitive

handles

into

and

I NEXT

Each

field

bit

<0>,

slice

receives

all

four

I BRTYPE

bits.

each

MCA monitors

for modifying

For

handles

conditions

UBRS

responsible

I NEXT

example,

I NEXT

bit

UBRS

<1>,

one
MCA

and

on.

Each

UBRS

masking

MCA

bit

from

the

BRMASK

field.

microword

The

BRTYPE

microbranch condition group to be selected by all

masking
to

bit

affect

determines

the

Note

that

the

appropriate

For

example,

bits

the

implement
to

Microbranch

all

CPU

the

various

1logic

Dependent

Some

EBox

generated

bits

that

EBox

outputs

ensure

full

32-way

the

I NEXT

microbranch,

UBRS

The

MCA

MCA.
ensure

field

all

that

are

zeros.

1low

order

zeros.

Microbranch

including

conditions

the

and

conditions

IBox

the

itself.

are

generated

Table

branch-sensitive

condition.

are

3-4

lists

bit

microbranch
based

these

conditions

the

microbranch

size

are

the

conditions

intermediate

data

being

either

condition

processed.

WBUS

The

<N,Z,C,V>

<KN,Z,C,V>.

that

the

EBox

conditions,

field

same

below

indicates

the

SIZE

the

generates

the

correct

size

data

size

specified

values

that
for

must

produces

the

I SIZE

the

conditions.

dependent

the

I SIZE

The

table

field.

Size
Unused

Byte

Word

Longword

dependent
in

path

the

microword

character

data

Data

<1:0>

Size

given

microprogrammers

Conditions

microbranch

the
of

one

Conditions

code

microbranch,

bits

and

five UBRS MCAs.

handled

units,

each

tested

specifies

bit

microbranch

associated with

ALU

condition

bits

I NEXT

implement

field must

3.3.4.1

the

branch-sensitive

Size

branch-sensitive

field

microbranch

Table

conditions

3-4.

3-13

are

denoted

the

asterisk

(*)

I_BRTYPE,

I_NEXT

NEXT <13:5>

|_BRMASK,

UPC <13-00~ 1:> MUX T3 JUPCA <13:0> )

CSO
RAM
16K
X

48 BITS

NEXT <4:0>

MASK BITS

TYPE BITS

SPECIAL
MICROBRANCH
CONDITIONS

B CLK

-4

Elh

SEL

MUX

OTHER

MICROBRANCH
CONDITIONS

UBRS MCAS

NOTE:

EACH UBRS MCA HANDLES ONE BIT
OF THE FIVE BRANCH-SENSITIVE I_NEXT
FIELD BITS. THE I_BRMASK FIELD SELECTS
WHICH UBRS MCAS ARE TO BE ENABLED.

Figure

3-6

Microbranch Condition Selection

3-3

I BRTYPE/I

BRMASK

Specifies
enabled

Specifies

Select

branch

(0]

HHEFOOHMOOHMEFOOMMHOO

Select

(Hex)

1FX

MCA

NATION

MHMHFOOCO

condition

1EX

UBRS

field

COMBI-

EF OO0

1DX

W N

I NEXT

1BX

17X

use

Operation

group

N TYIY7

UL'A

QOIPOOJIOU
D WNRFO

N/A,

Enable

RO
OCO0O

Code

Microbranch

ANY

NATION

= O

T
el R =

b
=

==
O
=

N/A

11111

ANY

microbranch

BRTYPE

<3:0>

COMBI-

the

MCA(s)

Relationship

more).

MOO

<4:0>

l__l

BRMASK

UBRS
or

Field

group under test (1 of 16).

POOHOHOMHOHOFOIM-O

Microword

the

(one

Table

XX0
XX1
XX2

XX3

XX4
XX5
XX6

XX7
XX8

XX9
XXA
XXB

XXC
XXD

XXE
XXF

XX denotes any combination (except lFX)——-—-——J

3-15

Table

Key:

Microbranch Conditions

3-4

- dynamic condition
- gsize dependent condition

@
*

Microbranch condition group - selected by I BRTYPE field
I_NEXT bits to be modified - selected by I_BRMASK field
<3>

<2>

<1>

STATE FLAG

SALU CC<L5>

<5>

<1>

TB STATUS

<1>

<0>

* WBUS <Z>

WBUS

PSL <N>

<3>

<FPD>

WRITE CHK
(C_SCF<7>)

WBUS

<2>

SALU CCK1>

WRITE
(C_SCF<13>)

<CURO>

MD NO <2>

<0>

* WBUS <N>
@

XALU CC

HALT

PENDING

MD NO 1>

@
PSL <TP>

PSL <KC>

PSL <KV>

PSL

WBUS

SALU CC<K2>

<CUR1>

<1>

SALU CCK3>

SALU CCK2>

PSI. <Z>

PSL

WBUS

INTR PENDING

PSL

* ALU <C>
@

SALU CCKO>

XALU CC

<0>

<4>

* WBUS <Z>

ILLEGAL OP

MD NO <0>

€

Table

Key:

3-4

Microbranch

dynamic

size

condition

I NEXT

bits

CACHE

condition

group

modified

<3>

CMD<4>

(C_SCF<7>)

STATE

CACHE

CMD<K3>

selected

<2>

(C_SCF<10>)

FLAG

(Cont)

condition

dependent

Microbranch

<4>

Conditions

CACHE

CMD<2>

ALU

I BRMASK

field

<1>

(C_MSIZE<2>)

I BRTYPE

<C>

CACHE

<0>

CMD<K1>

(C_MSIZE<1>)

WBUS

<N>

CACHE

CMD<O>

(C _MSIZE<0>)

WBUS

<Z>

<5>

ALU

<V>

STATE

FLAG

LOW

DIGIT

VALID

<3>

<4>

WBUS

<31>

WBUS

<30>

WBUS

<29>

WBUS

<28>

WBUS

<27>

NORETRY FLAG

* WBUS <2>
@

SALU

<2>

INTR

STATE
<6>

SALU

<3>

<4>

FLAG

INTR

STATE

SALU

<4>

<3>

FLAG

1INTR

STATE

<3>

<2>

3-17

STATE

<5>

<2>

FLAG

INTR

FLAG

<5>

<1>

VA REGK31>

INTR

<0>

VA REGK30>

Special Microbranch Conditions

Microbranch conditions in groups 7 and 8 (I _BRTYPE field equal to 7 or
8) are used exclusively by microtrap service routines that handle

This
memory management related microtraps (TB miss, TB ACV, etc.).
the
of
includes memory management microcode and certain sections
interrupt and exception microcode.

three
low
All special microbranch conditions, except for the
p
microtra
a
conditions in group 7, are latched in the UBRS MCAs when
is detected and are saved in the MCAs for the duration of the trap
service

routine,

The low three group 7 conditions are copies of TRAP MD <2:0> bits from
The TRAP MD <2:0> bits are latched and saved in the CBox on
the CBox.
The top two
(refer to the CBox section of this document).
p
a microtra
from the
bits
certain
of
copies
are
s
condition
8
group
all
group 7 and
C_SCF field of the trap causing microword.
NOTE

The CSCF field is read from the CS2 RAMs at canonical
T6 of the trap causing microword, but the UBRS MCAs do
not check microbranch conditions until T10 (a pipeline
The C_SCF bits are propagated through
restriction).
in the UBRS MCAs to accommodate for
latches
l
additiona
the

timing discrepancy.

The following table briefly describes how microtrap
use the special microbranch condition bits.

Table 3-5

service

routines

Special Microbranch Condition Bit Usage

Group

Bits

Used by Microtrap Service Routine to:

<2:0>

Restore the pointer to the EBox memory data
rcgister

(MDR)

that
AL WY
LU

was

receive
R
~ T et 2 M

memory
att

read data prior to the microtrap.

Perform a 32-way microbranch based on the
original command issued to CBox on exiting
(requeues the cache command).
~—

from the trap

<4:0>

originally issued

the trap causing microword
CBox by
to the
microtrap
The
check.
write
or
was a write
«call
to
type
command
the
know
handler must
fault.
the
fix
to
the proper subroutine

fmd

Determine if the command

()

<4:3>

State

The

Flags

IBox

with
in

the

MCA

CPU

and

group)

IBox

every

flexibility

CCBR

written
The

contains

can

and

latency

branch

that

since

tested

may

encoded

Noretry

interrupt

flag,

the

any

flags

can

set

microbranch
by

flags

during

The

flags

the

set

state

first

(or

conditions,

microword

cleared)

after

are

one

minimum

routine.

hardware

the

flag

reside

(individually

field.

then

later

state

information

caused

modified

flag

instruction

cleared

I MISC

during

field

(microcode

this

the

first

microword

restriction).

hardware

that

non-retryable

(except

GPR

GPRs

being

during

registers

noretry

the

I_NORETRY

flag

microword

are

sources,

restarted

determine

after

cleared

during

then

properly

the

set

operation

restarted

operations

the

FADS

the

MCAs

following

include

UTRP

and

MCA

first
the

that

Latency
delay

available

the

and

could

prevent

writes

GPRs

memory

writes.

operations
therefore,

set

pipeline

Due

the

pipeline

before

microbranch

the

MCAs

UBRS

latency

for

3-19

for

IPRs

Note

that

are

backed

retryable,

effect,

conditional

testing.

the

and

canonical

conditions

microword

fault.

are,

and

microword

first

auto-increment/decrement
in

resides

cycle

the

restoring

field.

Microbranch

normally

illustrates

other

auto-increment/decrement)

The

3.3.4.2

can

must

performs

Examples

RLOG

from

fault

GPRs.

from

state

instruction

all

The

period,

macroinstruction.

writes

The

cleared

use

and

that

noretry

every

I MISC

the special NORETRY flag to inform machine
check
routines whether a macroinstruction can be restarted
machine check fault.
The machine check code examines
the

instruction

The

the

microprogrammers

service

following
noretry

and

the

flow.

Flag

Microprogrammers

provide

microcode

(individually)

state flags are
macroinstruction,

set

the

microword
not

which

T9.

clears

cycle

Note

macroinstruction.

microroutine

flags

controlling

specified

canonical

hardware

state

there

generated

Figure

microbranching.

is
by

3-7

T
Ai

T
T

T
2l

T
5‘

T
f?

T
7‘

T
8‘

T
9|

T
1|O

T
‘I“I

T
1|2

T
1‘3

T
14

T
15

T
16

T
17

T
18

GENERATES MICROBRANCH CONDITION(S)

TESTS MICROBRANCH CONDITION(S)
TARGET MICROWORD

NOTES:
1.

ABLE TO THE UBRS MCAS AT
ALL MICROBRANCH CONDITIONS ARE AVAIL
PRODUCING MICROWORD
TION
CANONICAL T10 RELATIVE TO THE CONDI WORD)
.
MICRO
(T4 RELATIVE TO CONDITION TESTING

TION PRODUCING AND THE
THE TWO MICROWORDS BETWEEN THE CONDI
ALLOWED TO PERFORM
ONLY
CONDITION TESTING MICROWORDS ARE THE MICRO
BRANCH CONDITIONS
T
AFFEC
NOT
WILL
OPERATIONS WHICH
(MICROPROGRAMMING RESTRICTION).

H LATENCY PERIOD DO NOT
MICROTRAPS OR STALLS DURING THEOFBRANC
BRANCH. HOWEVER,
MICRO
THE
G
ICNIN
FUNCT
CT
CORRE
AFFECT THE
NOT PRESERVED
ARE
TEXT)
(SEE
DYNAMIC MICROBRANCH CONDITIONS
ACROSS IB DECODE CYCLES.

Figure 3-7

MKV86-1216

Microbranch Latency

There

are

two

microbranch
®

Dynamic

Static

Dynamic

for
one

Table

Figure

3-8.

the

WBUS

subroutine

The

I USTACK

depth

return),

3.3.5.1

Normal
in

the

calls,

field

the

new

MCA will

Note

and

I USTACK

bits,

are

only

wvalid

microstack

keep

microaddress
will
selected microstack

the

incremented
the

I NEXT

field

by one

the

address,
address

and
by

any later
the
"@"

microsubroutine
Subroutines

the

stack

microstack

MCA

control

the

microstack

calls
may

wraps

specifies

the

not

back,

exclusively

operations.

the

operation

pointer

specified

and

(call

supplies

calling
1is

the
then

the

(no

new microword

the

constant

one

microstack

the

subroutine

pointer

On
in

operation

each

the

the microaddress
As long as

request

normal
of

T3).

microstack

point

During

address

simply
overwrite
location.

address

the

UTRP

Operation

3.3.5.2
Microsubroutine Calls the
calling microword is loaded
pushes

which

that

the

location

does
the

supports

microstack.

for microtrap

field

return),

microword

the third
indicated

signal.

Microstack
or

the
after

not

MCA maintains

enable

<call

UTRP

RAM

(relative

Returns

wuse

This
occurs
at the same time
RAM address latches (canonical

CS0

<N,Z,C,V>

hardware

entries.

The

UTRP

write

subroutine

IBox

the
of

microword

the

stack

Calls And

calls/returns,

microstack.

starting

conditions

The

for

loaded

3-4.

through

overwriting

the

microbranch

1indefinitely
and may be tested by
Dynamic microbranch conditions are

returns

nested

the

such

Microsubroutine

Refer

cycle and can be tested only by the third microword after the
produces them.
Static conditions, such as the
state
flags,

character

3.3.5

types

conditions,

one
that

are
valid
microword.

and

basic

latency):

pointer.

loaded into the
I USTACK field
call
so

CSO
of

return,

the

that

the

previously

stored

a subroutine call, the address
the stack and the stack pointer

1location.

<calling

microword

microword,
selected

which
by

the

This
onto

the

specifies

the

UBRS

and

MCAs

the

of
is

effectively
stack.

The
subroutine

sent

the

latches.,

The microprogrammers can also also specify conditional
multiple-entry
point subroutine calls by encoding a subroutine call and a conditional
microbranch in the same microword.
1In this case, the
condition
bits
are
ORed
with
the I NEXT field of the calling microword, generating

one of several subroutine entry points.

3-21

I_NEXT

I_USTACK

1_NEXT > T4
T2

{

UBRS MCAs

)

NEXT FIELD

'SAVED UPC

NEXT UPCO

AMuUX| T3 | NEXT <13:0> >

A CLK

Cso
RAM

B CLK

STACK
MICRO-STACK POP

{SAVED UPC)

x 15
16
RAM

UTRP MCA

I_USTACK

POINTER

LOGIC

WRITE ENA

ARG

Figure

3-8

Microstack

3-22

Operation

SnH

3.3.5.3

Microsubroutine
Returns - On
a
pointer
1is first decremented

microstack
entry

containing

address
with

1is

then

low

the

microword.
address
Note

the

address

popped
order

The

bits

ORing

field

have

return

constraint

applied

one

(or

calling
from

For

example,

<0>

use
T N

Ml.l._x

any

comb
N \/1ILL

the

microword.
ORing

the

microword

the

1is

field

MCAs,

This

and

ORed

the

then

sent

the

CS0O

RAM

low

bits

the

five

with

the

<0>

the

allows

implement

address

the

returning

single

return,

subroutine
the

calling

microword:

low

order

address

bits

ORed

with

the

corresponding

return

microword,

set

the

following

the

bit

can

also

return

microword must be 0.
.
1
A A
the low
five
address
specify

encoding

case,

the

bit

address

conditional,

UBRS

and

MCAs
with

the

address

multiple-return

microbranch

form
the

microword,

(Single point returns
|29
Pl
N
h 4~
e PR
\
b i ts in this manner.)

conditional

popped microaddress

returning microword

Figures

are
from

alters

the

fixed

type

handler

been

used

the

return

OR of

the

can

points

the

point

enabled microbranch

selected.

can

caused

control

return

address

<4:0>

bits

conditions.

Microtraps

the

others
a

are

trap

second

<check
be

the

faults

the

Nested
service

trap

traps

controlled

the

serious

CBox
as

system

microtrap

which

enter

For

and

that

and

access

two

within
trap

only

after

(such

control

this

manner

based

have

the
trap

3-23

such

machine
expected

or more

traps)
first

store
they

microtraps

control

violations.

not

are

trap

are

routines

serviced

are

parity
are

call

microtraps

priorities

the

since

conditions

logic

higher priority microtrap
routines

vector

would

appropriate

example,

management

TB misses

(traps

that
is

the

faults,

error,

execution.
memory

traps

current
hardware

address

vector,

taken

the

occurs,

condition.

parity

such

prevent

microtrap

generating

microcode

store

prioritized

cycle,

ignored.

Machine
cannot

such

same

Instead,

discussions.

which

overriding

service
by

When

microtrap

forces

macroinstruction

extensively
service

The

following

conditions

flow

address,

the

properly.

microcode

store

for

detected

detected,

normal

3-10

executing

microroutine

due

during

and

hardware

current

trap

Microtraps
check

3-9

control

otherwise

that

microword.

UBRS

field

1is

microaddress

I NEXT

this

Microtraps

I NEXT

microaddress

the

zero.

ination
n

microword

that

calling
to

the
stack

Microtraps

Refer

the

sent

popped

calling

subroutine

3.3.6

from

points.

I NEXT

Microprogrammers

from

original

stack,

returning

more)

must

bit

the

microword

the

bit(s)

the

subroutine
return,
one to point to the

latches.,

that

for

of
the

resulting

I NEXT

from

occur

and

the

supported.

arranged

such

1is

serviced.

error),

however,

unpredictable.

It is the responsibility of the priority encoder logic in the UTRP MCA
to monitor all microtrap conditions and to generate the microvector of
the highest priority condition present. The following table lists the
various microtrap conditions and the corresponding microvectors.
Table 3-6

Microtrap Conditions And Vectors

Vector

Microtrap Condition

Priority

03EO

Microbreakpoint Hit

Highest

0320
0300

FP Rounding Error (addition)
FP Rounding Error (multiply)

03CO0
03A0
0380
0360
0340

Machine Check
VA Parity Error
TB Tag Parity Error
trap
Reserved for ECO
Operand
FP
Illegal

02E0Q
02CO

Integer Overflow
TB Miss

02A0

TB ACV

0280

Modify Bit Not Set

0260

Page

0240
0220

0200

Cross

Unaligned Page Cross
Unaligned Address

Conditional macrobranch

Lowest

Machine Check Microtraps

The UTRP MCA generates a common vector of 03C0 for certain types of
Depending on the type of fault, a machine
machine <check exceptions.

W N

check may be reported by one of four mechanisms:
.

Microtrap vector from the UTRP MCA

.
.

Interrupt vector from the INPR MCA
Current microword I NEXT field

Special address from the IB decoder logic

The following table lists the machine check exceptions reported by the

microtrap mechanism.

Table

3-7

Cache
Cache

Machine

Check

Data

Bus

Tag

Parity

Microtrap Conditions

Parity Errors
Errors

Control
Console

Store RAM Parity Errors
Receive Data Parity Error

Decoder
IB Data

RAM
Bus

Parity
Parity

Error
Error

Main

ALU Parity Errors
Processor Register Parity

Data

Parity

Errors

Error

Note that VA parity errors and TB tag parity errors are
also
machine
check exceptions but have their own microtrap vectors (03A0 and 0380).

3.3.6.1
Microtrap Servicing - Microtrap conditions are
generated
at
various
times
of a microword but are not honored until canonical T10
by the UTRP MCA.
For example, a machine check trap due to
a
decoder
RAM
parity
error is sensed at T4 while a TB miss microtrap is sensed
at T9 time.
Microtrap conditions sensed
early
1in
a
microword
are
propagated
through
a series of latches so that all conditions arrive
at the priority encoder in the UTRP MCA at canonical T10 of
the
trap
causing microword.

a microtrap
Ut
W N+

When

occurs,

the

hardware

Preserve

the

current

pipeline

Preserve

the

current

CPU

must:

state

Service the microtrap
Return from the trap
Restore CPU state to proper post

3-25

trap condition

I_NEXT

I_RTNTRAP

I_USTACK

‘

_NEXT
Sl

I_NEXT

UPC <13:0>

SILO

{RELEASE)

SILO

|13

€S0
|UPCA <13:0>

RAM

—

16K

48 BITS

E 0
G

SILO

I_RTNTRAP

SILO

(FREEZE)

B CLK

C c

UBRS MCAS

MICROVECTOR

GLOBAL TRAP

UTRP MCA

CONTROL

|_USTACK

A
[a¥al

PRIORITY

D COMDITIONS A
Hh

eYellal
I
LOGIC

ViIIND

BLOCK WRITES

NOTES:

WHEN A MICROTRAP OCCURS, THE UTRP MCA QUTPUTS THE:
¢ MICRCVECTOR O
L

mAm
e

AT AR

APPRC ODIATE TRAP HANDI ER ROUITINE
L1 94M

Ciu/mr

» GLOBAL TRAP SiGNAL TO FREEZE THE MICRO-PC SILO

{SAVES THE UPCS OF THE FOUR MICROWORDS iN THE PIPELINE

THAT FOLLOWED THE TRAP CAUSING MICROWORD)

e BLOCK WRITES SIGNALS TO INHIBITS WRITES BY THE FOUR
MICROWORDS IN THE SHADOW OF THE TRAP.

THE LAST MICROWORD OF THE TRAP HANDLER ROUTINE RETURNS
FROM THE TRAP BY ISSUING EITHER:

o | RTNTRAP-RETURN TO ORIGINAL FLOW, REQUES TRAPPED
MICROWORDS.

o |_USTACK/RLS.SILO-ABORT ORIGINAL FLOW, RELEASES MICRO-PC

SILO, DOES NOT REQUE TRAPPED MICROWORDS.
AVTRVRES

Figure 3-9

Microtrap Servicing

3-26

" GLOBAL TRAP’ VALID FROM T10 THROUGH T12.
FREEZES THE MICRO-PC SILO AND BLOCKS WRITES
OF NEXT FOUR MICROWORDS IN PIPELINE

CAUSES A MICRO-TRAP

1ST IN SILO

2ND IN SILO

3RD IN SILO

NOTE:

4TH IN SILO

MICROVECTOR OF THE TRAP HANDLER FROM THE UTRP MCA
OVERRIDES THE MICRO-PC OF THE FOURTH WORD

}___ FIRST MICRO OF

MICROTRAP HANDLER

LZ-€ 1A

17N\
—

]

MICRO-TRAP HANDLER ROUTINE
.

]
MICRO-PC SILO
(IN UBRS MCAS)

NOTE:

UPC 1

RE-QUEUED MICROWORD

UPC 2

RE-QUEUED MICROWORD

UPC 3

SEE NOTES ON FIGURE 3-9
FOR REQUEUING MICROWORDS

UPC 4

RE-QUEUED MICROWORD

EXECUTION CONTINUES
NOTE:

MICRO-PC SILO IS CONTINUALLY
LOADED WITH THE UPCS
OF THE MICROWORDS IN THE
PIPELINE UNTIL FROZEN BY
THE GLOBAL MICROTRAP SIGNAL.

Figure

3—10_

Microtrap

MKV86-1257

Latency

Preserving The Current Pipeline State

microwords are already
Due to microcode pipelining, three additionalword
generated by the time
started and the address of a fourth microthe origi
nal microcode flow
the UTRP MCA responds to a trap. To allow of these four
microwords are
to resume on a trap return, the addresses
saved in the micro-PC silo maintained by the UBRS MCAs.
O3
TITIYTY

silo is continually loaded
During normal microcode flow, the micro-PC
a microtrap occurs,
with the address of each microword executed. When
it further loading of
the GLOBAL UTRAP signals from the UTRP MCA inhib
addresses of the
Since the silo is four words deep, the are
the silo.
thus saved in
microword
four microwords following the trap causing UBRS
MCAs requeue these four
On a normal trap return, the
the silo.
addresses, allowing the original microcode flow to continue.
Preserving The Current CPU State

after the one that caused
The three microwords already in the pipeline
the CPU state so that the
the trap must be prevented from altering
fault. (Note that the
the
ce
servi
trap service routine can properly
ed, only the address 1is
start
yet
not
fourth microword in pipeline has
formed and saved in the micro-PC silo.)

either saving potentially
The current CPU state 1is preserved by
CPU or by inhibiting the
the
in
corruptible data 1in various silos
other three microwords
the
by
rmed
writes that would otherwise be perfo
already in the pipeline.

signals to inform the
The UTRP MCA issues the GLOBAL UTRAP CONTand<2:0>
to save critical CPU state
rest

the

CPU that a trap occurred

conditions in the appropriate silos.

<3:0> signals to inhib
The UTRP MCA also issues the BLOCK WRITE CONT
trap causing microword.
all writes starting at T1ll relative to the
Servicing The Microtrap

priate vector
When a microtrap occurs, the UTRP MCA cutputs the L appro
signal to the
UTRAP
GLOBA
the
for the trap service routine along with
trap vector
micro
the
t
selec
to
UBRS MCAs. This forces the UBRS MCAs
as the source of the next microaddress.

dy completed
Since the microword that caused the trap hass alrea
the trap
trap,
the
honor
MCA
UTRP
(unsuccessfully) by the time the
ble)
possi
(if
fault
the
cting
service routine is responsible for corre
eted
compl
word
micro
the
if
as
such that the net result is the same

Returning

From A Microtrap

Some

microtrap

while

others

first

the

faults,

service

The

settings

microword
return
UTRP

from

the

RTNTRAP

the

normal

CSO0

trap

RAM

The

exception

only

not

saved

decoder,

1in

the

DECODER

selection

the

This

this

routines

also

trap

micro-PC

from

the

perform

the

potential

and

the

field

and

the

saved

microwords

that

the

addresses

generated

silo

1is

source

are

the

flagged

DECODER microword

location

original

may

bit).

marked,

terminated

the

and

the

issuing

the

decoder.

itself.

microcode

This

issued

flow

releases

any

the

micro-PC

microword

silo,

trap

constraint:

(I _RTNTRAP)

same

from
silo

microaddress

micro-order

normally

the

bit

generated

the

traps.

Trap

decoder

the

one

from which

location

future

orders

MCAs

were

four

address

re-enabling

operation

last

trap.

(derived

following

the

that

abort

after

the

USTACK

I RTNTRAP

When

return

the

microaddresses

that

order

trap

flow,

silo.

return

routines

The

routine

requeues

the

micro-PC

service

microword

field

follows:

four

caused

microcode

I_USTACK/RLS.SILO

the

USTACK

I_USTACK/RLS.SILO

selected

release

Trap

with

the

routine determine how the
the

silo

and

those

check.

effect,

address

routine

machine

The

silo.

trap

for

include

return

silo

type

normal

MARKER

the

management

second

micro-PC

corresponding

Then,

memory

UBRS

that

with

Routines

the

such

flow

flow.

the

encoded

the

microcode

new

informs

addresses.

the

one

bit

return,

followed

service
of

original

enter

I RTNTRAP

I_RTNTRAP/ENABLE,
On

faults,

original

are

that

the

and

The

the

field

flow

Routines

trap service

whether

return

those

miss.

trap.

release

I USTACK

return

original

serious

the

routines

the

include
a

MCA

used

type

such

that

service
abort

that
the

encode

must

microcode

the

microword.
trap

microword

performs

the

want

very

trap

release

and

the

routines

that

operations

the

3-29

one

must

causing

return.

silo

operation.

may

potential

Trap

causing

after

issued

trap
not

release

containing

the

return

return
the

trap

but

first

causing

3.3.6.2

Disabling

Microtraps

The

setting

Microtrap

bit

module.

1If

checks

traps,

console

and

two

in
this

are

from

bit

can

has

the

generated

console

micromatch

equal,

the

The

the

are

compared

MICROMATCH

address

consocle

and

with

the

current

UPC

sent

selected

response
over

UBRS

back

all

the
an

the

write

MCAs.

other

the

machine

<13:00>

written

ability

precedence

logic

including

only

signal

takes

microtraps

interface

microtraps,

Microaddresses

3-11.

disable

all

Supplied

Figure

can

console

The

Console

console

request

set,

cleared.

contents

The

normally

the

inhibited.

microaddress

bit

the

3.3.7
Refer

this

are

console

CLK

Disable

The
and,

console.
explicit
sources.

CLOCK MODULE

SEQ MODULE

TRIC MCAs

UBRS MCAs

PAJ
<7:0>

CONS DATA <7:0>

CONS

ADDR <4:0>
TO/FROM

DATA LOAD
AND
COMMAND LOAD
REGISTERS

SET MICROMATCH

(::*

CONS

BIDATA <7:0>

LOOPBACK
CONTROL

CONSOLE
<7:0>

DATA

UPC

MICROMATCH

COMMANDS
'

CONS POWER | cong DATA <3

DECODE

COMPARE

(ENABLE MICROMATCH)

GWYC MCA

A CLK

CLOCK
CONTROL
LOGIC

MICROMATCH

MKV86-1261

Figure

3-11

Console-Supplied

Microaddress

3.4

MACROINSTRUCTION DECODING

selecting a block of
The macroinstruction decode process entails
decoding the opcode
I-stream data from the instruction buffer (IB),
entry point address
and current operand specifier, and generating thespeci
fier. After each
the
for the microroutine required to service the
logically shifted
is
IB
ssed,
proce
is
specifier of the instruction
available for decoding.
so that the next specifier (if any) is made point
address for the
entry
the
Once all specifiers are processed,
execute code of the instruction is then generated.

Refer to Figure 3-12.

The

description

process begins with the operation of the 1IB.

the

instruction

decode

1Initializing the IB (IB Flush)

3.4.1

mented value (for
When the VAX PC is modified by other than its incre
the .decoder must be
and
IB
the
t),
example, summed with a branch offse
by microcode to
ed
invok
is
initialized. This "IB Flush" operation
n to be executed
uctio
instr
next
the
ensure that the I-stream data for
is processed properly.

There are two types of IB Flush operations:

Full flush

microroutines

Used

that handle

PC control instructions, interrupts,

exceptions, and other macro services

Partial flush -

Used by microtrap service routines

1IB flush 1is
3.4.1.1 Full IB Flush - An example of when a fullinstru
ction.
ranch
required is the execution of a successful macrob
deliver the
When a successful macrobranch is executed, the CBox will
ning the
contai
rd
longwo
new I-stream data to the IB starting with the
ation
correl
a
longer
no
is
opcode of the new instruction. Since there
it is
rs,
pointe
s
addres
t
between data entering the IB and its curren
for
opcode
the
access
highly likely that the next decode cycle will
that
s
outine
micror
all
To prevent this,
the wrong instruction.
issue a full IB flush before exiting.
tions
instruc
ranch
macrob
service
forces the Decoder to
This

initializes

the

address inputs and

1IB's

“

wait for the CBox to deliver the new I-stream.

TRAP OPCODE
g

)

CYCLE OPCODE

:) PAROUT ~3:0

INIT

ClR

Jrlr

l E? 213

T[T

als|e|7]8|9

TM OPCODE A/B «7.0.v CLR

IB DATA

ALIGNER

ax32

UNIT

CACHE DATA
BUS <31:00>

wwo

> SPEC GPRNUM <3:0>

H—

PORT A

LW 1

I ]

LW 2

)

LW 3

)

PORT C

—TM

)

l ]

]]

[——\/

:> IBDATA4 <70

j’)

SEL
DIS

1::

A
::) IBDATA3 <7:0>
FORMAT

ADDR <1:0>

CNTRL

DATA

NEW OPCODE

1B TRAP

SCRAMBLER

|
|

IBUFMCA'S@4) _ _ _ _ _ _ _

IBDATA2 <7:0>

IBDATA1 <7.0>

IBFO MCA

FORMAT

GEN

NTRL
.
PARITY

::>

‘

CROM

1BUF MCA

IBUNFORIBDATA2 <7:0~

DATA

I8 ALIGN CNTL <1:0>

<7.0>

FORMATTER

CCLJINGWNRL

WRITE
DECODE
IBWR ADDR <1:0>_____
g

SEL

EN <3:0>

IBFOSPEC

> IBUNFORIBDATAT <7:0-

] I

PORT B

BUFFERFULL ]

SP <700

READ
PORTS

MEMORY

‘

GEN

[ IBDATA2 PAR

|— IBDATA1

PAR

_E:lBUNFORIBDATAZ <75 —]

IBUNFORIBDATA1 <7>

IBFORCNTA/B <1:0>

[BDATAFORCNT <6:0>

MK VEs g75%

Figure

3-12

1Instruction

3-33

Buffer

Logic

3.4.1.2 1IB Flush Logic - Refer to Figure 3-13. The VAX Branch logic
of the IBST MCA determines if a full IB flush is required by checking
When this field is in the range of 20
the I MISC microword field.
es is being executed:
microroutin
2F, one of the following
I MISC

Microservice Routine for:

20 to 2E

Simple conditional branches
Loop control instructions

(eg: BEQL, BNEQ)

(eg: ACBx, AOBLEQ)

Unconditional branches (BRB, BRW)
Subroutine instructions (BSBB, JSB,

Interrupts,

exceptions,

CPU init,...

RSB)
etc.

The I MISC settings in the range 20 to 2F and the instruction(s)
are

listed below.

I _MIsC

Instruction

represent

BGRT
BLEQ,
BGEQ
BLSS,
BNEQ
BEQL
BVC
BVS

20
21
22
23
24
25
20
27

I _MIsC

Instruction

28
29
2A
2B
2C
2D
2E
2F

BGTRU
BLEQU
BCC
BCS
AOBLEQ, ACBx
AOBLSS
BBx, BBxXx
BRx, BSxx

SOBGTR
SOBGEQ

they

PSL CC
When a conditional branch is executed, I MISC specifies which
(the
taken
be
the VBRL should test to see if the branch should
bit(s)
PSL CC bits are also contained in the CCBR MCA).
Example:

If:

Then:

I MISC

Test

PSL Z

bit for BNEQ instruction

Meaning

Operation

Set

Branch

VBRL negates IB FLUSH.

fail

instruction

Clear

Branch

VBRL asserts

Bit

success

from

I-stream

IB.

IB FLUSH.

offset to VAX PC.

enter

3-34

IBox executes next

EBox sums branch

IBox waits for the new

1IB.

ONE SHOT FLUSH
PCNC

FLUSH IB WRCNT

MCA

I_MISC

PARTIAL FLUSH

MISC <6:0>

EITHER FLUSH

GE-¢

CS2
RAMS
|..PFLUSH

IBST

PFLUSH IBST

CCBR
MCA
I_MISC/

1B FLUSH

MCA

DLY IB FLUSH

=20
to

BLOCK WRITES

NORMAL FLUSH IBST

T9
MKV86-0733

Figure

3-13

Flush

Logic

If an unconditional branch is executed (I_MISC equal to 2F), the VBRL
does not test any CC bits but immediately “asserts IB FLUSH to force an
flush,

unconditional

Refer to Table 3-8. When IB FLUSH 1is asserted, the discrete DEC
module logic issues several IB flush related signals to the IBST MCA
and to the PCNC MCA (the signals are listed in chronological order):
1.
2.,
3.

EITHER FLUSH
NORMAL FLUSH IBST
ONE SHOT FLUSH

DLY

FLUSH

IB WRCNT

These signals initialize the

and

1IB

the

Decoder

outputs of the IBST and PCNC MCAs into a known state.

forcing

most

The column labeled FULL FLUSH in Table 3-8 lists the IBST and PCNC MCA
outputs after a full 1IB flush. The mnemonic "Idep" means that the
output is instruction dependent and remains unchanged until a new

[o)

)

IB.

)

the

instruction enters

Table

3-8

1IBST And

PCNC

MCA

IBST

Outputs

After

Flush

MCA

State

Output

Signal

WRADDR

<1:0>

INDEXED

Full

INDEX

ACCEPTED

SEQ

Flush

Partial
Flush

Clear

SLOW

BRANCH

Clear

Restored

SPEC

Clear

Restored

Clear

Restored

<2:0>

SPEC

WAS

TWO

BYTE

NEW

OPCODE

SILO

NEW

RMODE
_

OPCODE

SPECIAL

ADDR

DLY

XOR

OPN

ENBL
IBS

PRED

DATA

SIZE

SPEC

TYPE

<3:0>

<1:0>

PCNC
IB

FULL

ADDR

INC

ALIGN

EMPTY

<2:0>

DEC

NOOP

DEC

NOOP

Restored

Set

Restored

Set

Restored

Idep

Restored

Idep

MCA
Clear

Clear

CNTL

IB
SET

<K1:0>

Set

<1:0>

Load

Clear
w/

FILE

Set

Idep

BRANCH

Idep

3-37

<1:0>

The IBST MCA and PCNC MCA output state changes relevant to an IB flush
are described below.
Table

3-9

The other changes will be covered later.

IBST And PCNC MCAs

IB Flush Relative State Changes -

Clearing
IB WR ADDR <1:0>

Forces the new I-stream to be written
to and read from the IB starting with

IB RD ADDR <1:0>

its

Loading IB ALIGN
CNTL <1:0> with
VA FILE <1:0>

Ensures that the first byte read from
the IB will be the opcode byte of the
new instruction.

longword

location.

equal VAX PC
and therefore
byte in the first

always
<1:0>
FILE
VA
<1:0> after an IB flush

pocint to the opcode
longword

delivered

Cache.

Asserting
NEW OPCODE

to select the opcode
IB
the
Forces
from its memory unit instead of
byte

Clearing
SPEC NO <2:0>

the
generate
to
Forces the Decoder
microroutine
the
for
address
entry
of
that services the first specifier

from

the

its

new

"Cycle Opcode

instruction.

3.4.1.3

Partial IB Flush - A partial flush is invoked when

IBST

DLY

microword

bit
I PFLUSH is set.
This bit is sent as the signal PARTIAL FLUSH to
the same logic used for a full IB flush.
The only difference is
that
1issue the signal PFLUSH IBST instead of NORMAL FLUSH
will
1logic
the
and

PFLUSH

IBST

FLUSH,

forces

the

IBST

MCA

"restore"

several

indicators
(operand
data
size, specifier number, etc.)
they were in prior to the time that a
microtrap
occurs

in
FLUSH
PARTIAL
labeled
routines
to
recover
from

state

to the state
(see
column

This allows microtrap service
Table 3-8.
traps
that
occur
during
instruction

execution,

indicators are stored

in a silo

detected.

microtrap

W)
@

IB state

The
when

internal to the

IBST

MCA

3.4.2

1I-Stream

Prefetching

I-stream

prefetching

the

1IB

supplied

the

CBox

and

enhances

with

instruction

I-stream

described

data.

detail

1in

manual,

3.4.2.1

General

Instruction

the

loaded
flow
a

During
to

accepts

longword
The

each

Dby

CBox

asserts

the

after

longword

Address

longword

with

(eg:

Description

Buffer

new
a

its

idle

the

PIBA

offers

the

data,

the

which

assumes
IB

each

FULL.

1In

CBox

case,

The

and

PIBA

change

fetches

from

the

CACHE

in
is

address

initially

the

I-stream

updated

BUS.

when

idle

pointed
If

point

CBox

unless

suspended

the

IB.

and

the

IBox

negates

IBox

and

Prefetching

the

cycle,

the

incrementing

this

Physical
the

longword

DATA

four

accepted

PIBA

offered

processed

section

the

resumes
IB

FULL.,

Refilling

Cache - Each time a PIBA
request
1is
made,
there
possibility that Cache will not contain the required data.
event, Cache will report a "read miss", forcing
the
CBox
to
the data from NMI memory by performing an operation known
as a

exists

the

this

obtain
PIBA

"refill."

PIBA

refilling

longword

entails

time)

fetching

and

the

PIBA

The

NMI

hexaword

The

first

requested

receives

Cache

the

and

PIBA was
longwords

IB.

rest

This

the

first

octaword
of

the

allows

data

hexaword

the

data

operation

returned

read

longword,

the

NMI

are

two

key

I-stream decoding:

octawords

NMI

miss

when

always

stored

3-39

are

simultaneously

read

miss

stored

continue

the

one

stores

occurred

CBox

the

octaword

IBox

being

two

from

There

IB.

aligned
first

bytes)

Cache.

relevant
as

Cache

the

(32

transferred

longword

offers

three

refill

when

storing

about

the

longword
this

keeping

function

IB.

incremented

contains

instruction)

the

there

PIBA

When

when

branch

the

once

points

IB.

maintains

the

longword

referenced

3.4.2.2

which

cycles,

last

longword

CBox

the

offered

CBox

(PIBA)

formed

the

The

delivered

speed

operation

successful

accepted

execution

The

the

Cache.

occurred,
Cache

decode

the

and

process

offered
while

Loading The 1B
3.4.3
Refer to Figure 3-14.

The IBUF MCAs always assume the CACHE DATA BUS carries 1I-stream data
destined for the IB. This means that they will attempt to store data
(The IB load operation is asynchronous
from the bus on every B clock.
to the pipeline in that no microword field controls the IB.)

The IBUFFER FULL signal from the PCNC MCA determines if data should
enter the 1IB. When this signal is negated, it indicates that the IB
longword addressed by IB WRADDR <1:0> is "empty" and can be loaded
(An IB longword is considered
with data from the CACHE DATA BUS.
empty if ALL the bytes in the longword are processed.)

The Write Decode logic of the IBUF MCAs checks IBUFFER FULL on every A
If the signal 1is negated, the logic will decode IB WRADDR
clock.
<1:0> and clock the longword from the CACHE DATA BUS into the selected
IB location on the following B clock.

3.4.3.1

1IB Write Control - The IB load method has one

drawback:

allows the IB to capture data from the CACHE DATA BUS even if the data
(The CACHE DATA BUS also supplies data for
are intended for the EBox.
EBox operations.)

1f IB WRADDR <1:0> were to change state each time Cache sent

the

would

be loaded with the wrong data.

data

Since this

the

EBox,

that

the write address only changes state when data on the CACHE DATA

would corrupt the instruction decode process, the IBST MCA must ensure

BUS is destined for the IB.

To do this, the IBST

MCA

monitors

signals:

Signal

Source

Description

DEST 1I5 IB

CBox

CACHE DATA RBUS carries I-stream

CACHE DATA VALID

CBox

MEMORY BROKEN

CBox

CBox detected some type of parity

FLUSH IB WRCNT

IBox

IB Flush operation in progress

IBUFFER FULL

IBox

IB cannot accept another longword

data destined

for the

Last Cache reference resulted in

Signal also forced
a cache hit.
true when source of data is NMI.
error

(TB,

Cache,

NMI,

etc.)

five

IBUF MCAs

INIT

J;CLR

4 X 32

MEMORY
UNIT

LW
O
LW
1

CACHE DATA BUS <31:00>

LW
2

Iv-€

LW
3

EN <3:0>

IBST MCA

DEST IS IB

MEMORY BROKE-

IB WR ADDR <1:0>

CACHE DATA VALID ————i
MONITOR

LW ACCEPTED

DIS
PCNC MCA

LOGIC

IB FULL
LOGIC

IBUFFER FULL

A CLK

P> TOoOq4>r

SEL

——

FLUSH IB WRCNT

WRITE
DECODE

CACHE

MKV86-0734

Figure

3-14

Load

Logic

3.4.3.2 Cache Monitor Logic - When these
conditioned, the Cache Monitor logic in

properly
are
signals
the IBST MCA asserts the

It
signal LW ACCEPTED to indicate that a longword has entered the IB.,
IB
next
the
to
point
to
one
by
<1:0>
WRADDR
IB
s
then increment
location to receive data from Cache.

The following chart indicates the state of LW ACCEPTED and

1IB

WRADDR

<1:0> for any given condition.

LW ACCEPTED

FLUSH

IB WRCNT
0

CACHE DATA VALID

DEST IS 1IB

MEMORY BROKE

IBUFFER FULL

IB WRADDR <1:0>

value + 1

Other combinations

Previous value

Don't care

Cleared

Note that IB WRADDR <1:0> are unconditionally cleared when FLUSH 1IB
This ensures that the first longword from the CBox
WRCNT is asserted.
is loaded in the IB's longword 0 location.

From this point on, the IBST MCA will increment IB WRADDR <1:0> by one
each time a longword on the CACHE DATA BUS is destined for and loaded
Once all four IB longwords are loaded, the write address
into the IB.
is "wrapped back" to again point to the IB's longword 0 location.

Since IB WRADDR <l:0> can only change state when the CACHE DATA BUS is
destined for the IB, they will always point to an "empty" IB location
1IB
the problem of the
Thus,
(assuming IBUFFER FULL is negated).
longword
new
the
resolved;
trying to capture data on every B clock is
simply replaces one that was already processed by the IBox.

3.4.3.3

1IB Full Logic - When a longword enters the IB, the
assertion
LW ACCEPTED causes the PCNC MCA to increment a counter which tracks
the number of
longwords
available
for
decoding.
This
"IB
Full"

counter

1is

incremented

one

decremented

supplies

data

causing

the

counter

the

CBox

data,

IBUFFER

one

FULL

3.4.3.4

Load

longword

aligned,

the

when

prevent

any

Example

the

new

instruction

may

from

the

include

Figure

3-15

shows

instruction
associated

may

with

Since
data

longword

from

this

any

means

data

1IB.

the

IBox
PCNC

data

the

can

restrictions

1I-stream

MOVL

issue

the

other

process

enters

with

xx's

IB.

the

some

and

MCA will

the

such

IB.

always

that

the

boundary,

for

The

the

imposes

byte

enters

from

entering

I-stream

associated

the

than

overflow,

data

I-stream

enter

other

processed

faster

Although

begin

how

would

the

VAX architecture

instruction.

CBox

when

longword

first

for

instruction.

#©9X12345678,

represent

longword

I-stream data

instructions.

Assumptions:

Note

Starting

that

Flush

the

location.
although

first

This
the

three

1IB

aspect

the

just

completed

for

longword

always

instruction
locations
IB

MOVL

will

1003

(address

the

only
to

case

occupies

contain

become

the

apparent

1000)

after

3-43

stored

flush.

the

IB's

Also

note

that

memory,

takes

seven

bytes

data.

The

consequences

discussion.

the

this

Assembler Syntax
Machine code

MOVL #©X12345678, RO
50 12345678 8F DO

Instruction as
stored in memory

Address

Contents

1000

xx XX XX

34 56 78 8F
xx xx 50 12

1004
1008

ADDR 1000

First longword
IB contents

XX XX XX XX

L*““‘LVV 0 ————*4
ADDR 10004

Second longword

IB contents

78 8F

XX XX XX XX

le——1LW 1
Third longword

DO xx XX XX

XX XX

LW 0—>

ADDR 1008

xx xx 50 12

e w2 — b

34 56 78 8F

DO XX XX XX

—f—1w

o—
MKV86-1137

Figure

3-15

I-Stream Data Entering The 1IB

3-44

3.4.4

Reading

The

Although

I-stream

treated

selecting

data

the

The

enters

sixteen

entalls
to

IB
data

rest

six
of

the

byte

consecutive

the

IBox.

Opcode

Current

specifier

(if

extension

bytes

opcode

their

byte

address

sent

1inputs.

during the first decode
register
then
becomes

longword

bytes

read.

from

bytes

the

time,

The

and

consist

the

read

1is

operation

outputting

the

the:

any)

the

when

These

buffer

(eg:

immediate

Decoder

also

RAMs

saved

data)

(DRAMS)

"Cycle

form

part

Opcode"

cycle of the instruction.
The
cycle
the source of the opcode for subsequent

opcode
decode

cycles,
The

specifier

operand

byte

Size

(byte,

(literal,

each

The

size

bytes

the

are

sent

extension

specifiers,

the
to

Dbe

EBox

use

are

mode,

write,

will

determine

the

PCNC

—~
e

etc.)
(1

MCA which

computes

the

always

6)
determines

amount

current

four

bytes

microroutine

that

will

ready

Decoder

extended

EBox

from

the

reads

the

data

general

class

"consumed"

are

the

for

micro-PC

the

byte

and

DATA

BUS.

this

data

may

Microcode

performed
the

specifier

3-45

for

determines

word

Since
or

may

the

canonical

T1.

bus.

generate

service

the

IB,

specifier.
from

sign

the

read

the

Timing

are

Pipeline

have

which

sent

all

the

and

the

bytes,

allows

time

MCA which

longword)

instruction

and

are

bytes

not

3.4.4.1

IBST

cycle,

consecutive

This

the

(read,

instruction

decode

four

word,

mode

Position
Both

sent

Type

Access

specifier's:

during

entry

(or

address

opcode)

latches

for

the

during

T3.

t nine consecutive bytes
3.4.4.2 1IB Read Ports - The Read Portstheselec
longword pointed to by IB RD
from the IB Memory unit starting t with
read ports to the 1IB Data
ADDR <1:0>. The bytes are outpu on three
Ports A and B are both four bytes wide, port C is one byte
Aligner.
wide.

The following table shows the relatio

and data selected by the IB Read Ports.

Table 3-10

IB Read Address/IB Read Port Source

IB RD ADDR

PORT A

PORT B

PORT C

0 0

LW O

LW 1

LW 2 Byte 0

LW 1

LW 2

LW 3 Byte O

LW 2

Lw 3

LW 0 Byte 0

LW 3

LW O

LW 1 Byte O

<1:0>

Source

around" when the read address
Note that the read ports perform a "wrap
to always access nine
is equal to 2 or 3. This allows the readingports
longword address.
consecutive bytes regardless of the start

bytes at a time is in case the
The reason the read ports select nine
e byte
first specifier of an instruction is being decoded and the opcod
occupies byte

3 of a LW.

position in a longword and 1is
Since the opcode byte can end up intheanyfirst
specifier, up to six bytes
"consumed" in the decode cycle of ss the first
operand:

of IB data may be required to proce
Opcode
.

i L

A de

Example:
@

Instruction

instruction

MOVL
The

I-stream

{The

xx's

just

for

#©X12345678,
the

indicate

MOVL

ended

executed

B®©04

would

byte

the

shown

is:

(RO)

I-stream data

loaded

into

associated

with

other

1st LW of

3rd LW of

MOVL

8F | DO

LW 3

LW 2

below,

instructions.)

2nd LW of

IB Memory unit

executed

xx 04

LW 1

LW
O

IB RD ADDR <1:0 > =2
MKV86-1125

Figure

First

Decode

3-16

Cycle

Memory

- MOVL

Unit

Contents

#©X12345678,

Notice

that

output

the

first

performing

decode

I-stream

for

CBox.

Also,

selecting

six

bytes

required

byte

the

wrap

the

cycle

MOVL

decode

read
the

the

same
at

cycle

3-47

Example

ports

even

order
a

with

read

MOVL.

function,

bytes

LW.

around

nine

MOVL

B©04(RO0)

Figure 3-17 shows the data selected by the
address

For

time,

though

the

was

they
the

read

ports

delivered
can

opcode

read

by
all

occupied

IB Miemory unit contents

LW 3

LW 2

LW 1

LW O

34 56 78 8F

DO xx xx XX

XX XX XX XX

xx 04 AOD 12

IB RD ADDR <1:0> =2
PORT A = LW 2

PORT B =LW 3

PORT C = LW O Byte O

)

34 56 78 8F

DO XX XX XX

IB Read Ports
MKV86-1126

Note:

the I-stream
If the previous instruction caused a change in the
MOVL would
for
branch or jump), the I-stream
flow (eg:
would be
data
However, the
still be output from the IB.
ed at
shift
"
ignored since the 1IB would not be "logically
ous

canonical T3 time of

the

last

microword

instruction.

1IB Read Port Example - Part 1

First

lr No ]

B 04{R0)
[8]

inN

MOVL #©X12345673,

Figure 3-17

Decode Cycle

the

previ

Second

While

Decode

the

updated

Cycle

first
to

MOVL

specifier

point

#©X12345678,

being

the

B©04(R0)

processed,

longword

specitier,
The

second

figure

decode

shows

the

data

selected

containing

the

ADDR
the

Read

cycle,.

<1:0>

are

second

operand

Ports

the

IB Memory unit contents

LW 3
XX

LW 2

XX XX XX

XX XX XX XX

LWO

XX XX XX XX

xx 04 AO

v/’

XX XX XX XX

xx 04 AQ 12

e ————————

IB RD ADDR <1:0> =0
PORT

A=LWO

PORT B = LW 1

PORT C = LW 2 Byte O

IB Read Ports
MKV86-1127

Figure

LWs

other

3-18

and

are

shown

instruction

delivered

Read

the

Port

containing

since

1IB

Example

new

data

I-stream

while

the

Part

associated

data

first

will

specifier

decoded.

Figure

3-18

1IB

MOVL

Read

Port

#©X12345678,

Second

Decode

3-49

Example

B©04(R0O)
Cycle

most

Part

with

some

likely

being

Figures 3-17 and

3-18

serve

concerning the IB Read Ports:
1.

1illustrate

two

aspects

important
decode

cycle

By selecting nine bytes at a time, the Read Ports can

access

The opcode byte appears in PORT A in the first

of each new instruction

all

cycle

I-stream

data associated with a specifier in one decode

Exceptions:

Since the second byte of

two

Dbyte

opcode

the

true

The
opcode, the first Dbyte is given its own decode cycle.
cycle.
decode
next
the
second byte will appear in PORT A in
Except for this, instructions
the same as any
processed

with two byte opcodes are
(Note:
other instructions.

Microcode treats the first byte of a two byte opcode as if it
were a NOP macroinstruction.)

Indexed and big immediate (quad/octaword, double,

huge) specifiers require additional decode cycles.

3-50

grand

and

3.4.4.3
1IB
byte
wide.
input field
@
@
e

Data Aligner They
select
consisting of:

The six data aligner
muxes
are
each
six
consecutive bytes from an eleven

Nine bytes from the IB Read
The Cycle Opcode Register
The Trap Opcode Silo

Ports

The following figure shows the aligner muxes, the data they output
the
destination of the data.
The indicator "internal®TM means that
data from a mux remains internal to the IBUF MCAs.

UNFOR IB DATA MUXES
IB4

IB3

IB2

SPC

IB1

OPC

| UNFOR
SPC

MUX | MUX | OPC

——

=
=

Unformatted
Specifier

Opcode

0OPCODE A <7:0> to PCNC MCA

OPCODE B <7:0> to Decoder logic

» SP <7:0> to IBST and PCNC MCAs
IBFOSPEC <7:0> to IBFO MCA

SPEC GPRNUM <3:0> to FADS MCAs
> [BUNFORIBDATA1 <7:0> TO IBFO MCA

- |BUNFORIBDATA2 <7:0> TO IBFO MCA

» |BUNFORIBDATAS (internal)
»|BUNFORIBDATAA4 (internal)
MKV86-1138

Figure

3-19

1IB

Data

3-51

one
byte

Aligner

Muxes

and
the

Data

The

Aligner

Control

Data Aligner Muxes
o

NEW OPCODE

ALIGN

1IB TRAP

are controlled

CNTL

<1:0>
IBST

PCNC

the

following

signals:

MCA

discrete

DEC module

logic

The next

table shows

the relationship between the control

the

selected

the

data

Table

3-11

Data Aligner Control
IB

ALIGN

signals

muxes,

CNTL

Signals/Data Selection

TRAP

Data Aligner Muxes

<1:0>

00
01
1 0
11

IB4

IB3

IB2

IB1

SPC

B-1
B-2
B-3
C

B-0
B-1
B-2
B-3

A-3
B-0
B-1
B-2

A-2
A-3
B-0
B-1

A-1
A-2
A-3
B-0

OPC

A-0
A-1
A-2
A-3

CYC
OPC
REG

NEW OPCODE = 1 (First decode cycle) -——------ l

NEW

OPCODE

(Subsequent

ALIGN

TRAP

CNTL

cycles)

o
a—an
e
m
am
—
—
—

NEW OPCODE

(don't

Data Aligner Muxes

care)

<1:0>

IB4

IB3

IB2

IB1

SPC

OPC
TRAP

Don't

care

OPCODE
SILO

Note:

A-0,

A-1,

byte

etc.

the

represent

the

port

If:

TRAP

Then:

OPC

MUX

Read

Port
For

a mux.
=1, IB

ALIGN

selects

Byte

(A-0)

PORT

and

the

example:

selected by
=0, NEW OPCODE

CNTL

<K1: 0>

=00

and

Data Aligner Operation

The overall Data Aligner operation will be
#©X12345678,

B©04(RO)

instruction as

The MOVL instruction was assumed to be
IB

78 8F

LW 3

In the

Memory

loaded in the

IB as

MOVL

follows:

Unit

DO xxX XX XX

XX XX XX XX

LW 2

LW 1

first decode cycle,

illustrated using the

an example.

xx 04 AQ

LW O

IB RD ADDR <1:0> pointed

the

longword

Data

Aligner

containing
the
opcode
byte
(LW
2).
They were then updated in the
second cycle to point to the longword containing the second
specifier
(LW

0).

Figures 3-20 and 3-21 show the bytes selected by the IB

muxes

for each decode

cycle of

the

MOVL.

3-53

IB ALIGN CNTL <1:0> = 11
Start at PORT A byte 3

IB READ PORTS

NEW OPCODE = 1
Select opcode
byte from PORT A
Save opcode in Cycle
Opcode Register

CYcC
OPC
REG

Y Y

)

B4 | IB3 | IB2 | IB1 | SPC | OPC
12

DATA ALIGNER MUXES
MKV86-1128

Figure

3-20

1IB

Data

MOVL

Aligner

Output

#©X12345678,
First

Decode

3-54

Example

B©04 (RO)
Cycle

Part

IB ALIGN CNTL <1:0> =00

Start at PORT A byte O

IB READ PORTS

C
XX

B
XX

A
XX

—_

| AO

J
NEW OPCODE =0
Select Cycle
Opcode Register

Restore register

CYC

OPC
REG

S —.

Yy
IB4 | IB3 | IB2

IB1

| SPC | OPC

| AO

Yy ¥

DATA ALIGNER MUXES
MKV86-1129

Figure

3-21

1IB

Data

MOVL

Aligner

Output

#©X12345678,

Second

Decode

3-55

Example

B©04(R0O)
Cycle

Part

OPC Mux Source Selection
Refer to Figure 3-22.

es which
t to the OPC mux determinPort
The selection of the sourceto inpu
s.
Read
IB4 muxes select from the
bytes the SPC and the IBl

There are six possible source inputs to the OPC
e

e
e

mux:

Four PORT A bytes

Cycle Opcode Register
Trap Opcode Silo

the first decode
OPCODE is asserted in ct
Figure 3-20 shows that NEW forc
es the OPC mux to sele the PORT A byte
cycle of the MOVL. This
pointed to by IB ALIGN CNTL <1:0>.
first cycle of an
ys equal VAX PC <1:0> inde the
IB ALIGN CNTL <1:0> alwa
. The opcode is
e point to the opco and byte
instruction and therefor
stored in the Cycle
thus selected from the appropriate PORT A byte
Opcode register.

t
IB ALIGN CNTL <1:0> poin
in the second cycle, spec
Figure 3-21 shows thatprec
the
of
ead
ifier 1inst
edes the second
to the byte that
be able to select
must
mux
OPC
the
use
specifier itself. This isA beca
then from the Cycle
in the first cycle and ce
the opcode from PORT subseque
the amount of
e. To redu
Opcode register in each , IB ALIGntN cycl
ned to point
CNTL <1:0> are conditiothe
logic needed to do this
first.
to a "dummy" byte in PORT A in every decode cycle except
N CNTL <1:0>,
tion established by IB ALIG
With the starting byte posi
s from the Read Ports are selected by
the next five consecutiveIB4byte
muxes.

[

(O8]

the SPC mux and the IB1 to

IB ALIGN CNTL <1:0>
NEW OPCODE

IB TRAP

SEL
PORT A

OPCODE A/B <7:0>

BYTE 3

CYCLE
OPCODE
REGOSTER

XC2

BYTE 2

]

BYTE 1

MOUOOTO

BYTE O
TRAP
OPCODE
SILO

MKV86-1136

Figure

3-22

Opcode

3-57

Mux

Sources

SPC Mux Source Selection

The SPC mux always selects the specifier byte in the decode cycle
associated with a specifier. The only exception to this is when the
specifier is indexed or is a big immediate.

Indexed and big immediate specifies both require additional decode
cycles to fully process the operand. In this case, the SPC mux will
select data as follows:

Specifier Type

SPC MUX Action

Index mode

Select index in first decode cycle then

Big immediate

base in second cycle (if base is a big
immediate, the following also applies).

Select specifier

byte

1in

£first cycle

of each subsequent
then low order byte
longword in the following cycles.

IBl - IB4 Mux Source Selection

Data selected by the IBl to IB4 muxes is considered unformatted
it may or may not be related to the current specifier.

since

In the first cycle of the MOVL, all four muxes contain data related to
the first specifier. Since data formatting is not required, the four
extension bytes are sent unmodified to the EBox on the IB DATA BUS.
In the second cycle, only the IBl mux contains data related to the
Since the byte displacement (04) is to be summed with GPR
specifier,
RO to form a longword address, it must be sign extended before being
sent to the IB DATA BUS. This sign extending is a function performed
by the Data Scrambler and Data Formatter logic. Once the displacement
is properly sign extended, it 1s then sent to the EBox on the IB DATA
BUS.

Note that the EBox does not always reguire all four bytes from the 1IB
DATA BUS to be related to the current specifier. For example, to
process the first specifier of a MOVB $#©xX12, RO instruction, the EBox
only uses the low byte of the bus and ignores the upper three.

3-58

Cycle
In

Opcode

the

OPC

second

mux

opcode
Or”

mux

Since

cycle

select

the

selected

and

stored

MOVL

the
in

However,

For

performed

decode

Cycle
the

the

with

cycle.

two

NEW

OPCODE

Most

instructions

use

However,

since

certain

they

These

Trap

Silo

The

Opcode

Trap

Opcode

were,

ago
and

Trap

Opcode

which
the

copy

the

the
IB
has
specifier.
(Every
four

two

Silo

provides

the

opcode

point

say,

NEW

MOVL,

the

instructions

and

stays
its

the

last

examine

execute

not

own

subsequent

after

the

covered

subsequent

signal

the

code.

need

this

cycle

the

last

TRAP

routine

are

second
opcode

the

requires

Decoder
do

opcode

the

each

third

for

and

again

the

address

MOVP,

byte

the

such

for

OPCODE

first

allow

code

selected

input

for

the

copy

delay

microroutine
is

wusually

latches

<cycles

the

later.

Selection

corresponds

start

through

this

cycle

second

the
the

negated

execute

"Optimized"

passed

operands,
decode

the

OPC

asserted.

The

the

Opcode

instructions,

combine

specifier.

entry

two

since

then

This

the

opcodes,

cycle

Cycle

generate

and

the

cycle,

in the
instruction.

the

opcode

force

this

times,

processed.

1is

During

has

cycles.

specifier

negated

instruction

byte

second

Opcode

once,

several
cycle of the

the

OPCODE

only

recycled

decode

instructions

asserted

NEW

Opcode

instruction

specifier.
be

MOVL,

Cycle

from

specifier

the

back

"recycling"
would

Selection

in
the

required

been

Figure
opcode

the

opcode

between

that
since

the

services
by

the

beyond

3-22

one

equal
get

silo.)

3-59

from

the

when

was

occurrence

it.

time

"shifted"

mux

A
a

the

cycle.
OPC mux

four

trap

cycles

trap

cycle

old

detected,

problem

causing

Thus,

output

the

takes
of

Trap service routines use the Trap Opcode Silo along with certain data
saved in the IBST MCA to restore IB state indicators to the state they
The IB itself is flushed and
were in at the time the trap occurred.
to by a copy of the VAX PC
pointed
data
refilled with the 1I-stream
PC Silo maintained by the
Trap
a
in
manner
which is saved in a similar
EBox.

3.4.4.4 IB Data Formatter and Data Scrambler - One of the functions
of the 1IB is to supply the EBox with I-stream embedded data such as
short literals, immediates, branch offsets and displacements, and
This function is performed during canonical T2
absolute addresses.
through T5 by the data formatter and data scrambler.
Data Formatter/Scrambler Logic
Refer

Figure

3-23.

They
The Data Formatter and Data Scrambler consist mostly of muxes,
the
and
muxes
IB4
to
IBl
receive the unformatted IB data from the
mode
addressing
the
on
Then, based
specifier byte from the SPC mux.
of the specifier and various control signals, they format the data and
send
IB

to the EBox on the

Format

Control

IB DATA BUS.

Inputs

The format control inputs to the Format Generator, IBDATAFORCNT <6:0>,
represent the general instruction class and the data size of the
current

specifier.

[

(o)

(A)

Table 3-12 lists the state of the format control signals for any given
The order in which a signal appears in the table indicates
data type.
highest
SET BRANCH has the
That 1is,
1logical precedence.
its
negated,
both
are
signals
When these
precedence followed by SEQ LW.
the remaining inputs indicate the data type of the specifier.

DATA
ALIGNER

MUXES
IB4

—>

IBDATA4 <7:0>

DATA

IB3

IB2

—>

IB1

»|

—

FORMATTER | |BDATA3 <7.0>

CONTROL

SPC

IBDATA2 <7:0>

DATA

SCRAMBLER |
=
<7>

<7>

|BDATA1 <7:0>

CONTROL

FORMAT

<7:6>

IBFORCNTA/B <1:0>

GEN
A

SET BRANCH

DATA SIZE <2:0>
EXTRA BIT

IBDATAFORCNT <6:0>

TWO BYTE

(Format control signals)

SEQ LW

MKV86-1130

Notas:

The

Format

The

Data

Only

bit

the

Format

Figure

Generator

Formatter
<7>

from

and

the

resides
IBl

Data

and

the

Scrambler

IBUF

Data

IB2

and

bits

<7:5>

Formatter

And

Data

Scrambler

3-61

the

IBFD

MCA.,

MCAs.,

Generator.

3-23

reside

from

SPC

Logic

are

sent

Table 3-12

1IB Data Format Control Signals/Functions

Signal

Function

SET BRANCH

of
Indicates current specifier is the branch offset
branch
control
loop
or
,
unconditional
conditional,
a
instruction.

SIZE

DATA

(See

notes,)

Indicates data size of current specifier:

<2:0>

011

000,

used

Not

Word

010
160

Longword,
Quadword,

101

001

Byte

Octaword,
110
111 = Octaword,
EXTRA

TWO

SEQ

BIT

BYTE

F-Float
D-Float,

G-Float

H-Float
H-Float

(except 1lst specifier)
(1lst specifier only)

word sized branch
and
byte
between
Distinguishes
offsets (see SET BRANCH) and, with TWO BYTE, between
the various data types when the DATA SIZE <2:0> bits
110 or

100,

111.

are equal

to 010,

Indicates

instruction has two byte opcode

for

BIT).

EXTRA

(see entry

processing a
1is
Indicates the current decode cycle
immediate specifier
big
a
of
subsequent longword
(quad/octaword,

double,

grand or huge data).

Notes:

a
of
cycle
SET BRANCH is also asserted in the first decode
an
of
cycle
only,
and
first,
1in
and
opcode
byte
two
prevents
This
NOP).
instruction that has no operands (eg:
of a
byte
second
the
Generator from interpreting
Format
the
a
as
instruction
new
a
of
two byte opcode or the opcode
specifier.

displacement
branch
for
asserted
not
1s
BRANCH
SET
type are
this
of
Specifiers
B®D(Rn).
as
such
specifiers,
decoded from their addressing mode bits, SPC <7:5>.

Table

3-13

1IB

Format

Control

Signals/Specifier

Set

SEQ

Data

Extra

Two

Branch

Size

Bit

Byte

001

010

100
0

Type

Word

Longword

F-Float

D-Float

Quadword

G-Float

101

Byte

110

Octaword

H-Float

111

Data

Octaword

H-Float

Subsequent

Branch

byte

Branch

word

3-63

LWs

Type

SET BRANCH asserted

When SET BRANCH is asserted, the EXTRA BIT signal represents the data
size of a branch offset. Depending on the state of this input, the
Format Generator determines the sign of the offset from either:
SPC <7> - byte offset
IBl <7> - word offset

@
e

the Format
the offset,
Once it establishes the size and sign of
output the
to
Formatter
Data
and
Generator causes the Data Scrambler
and Data
Scrambler
Data
(The
BUS.
sign extended offset to the IB DATA
Formatter outputs will be shown later.)
SET BRANCH negated,

SEQ LW asserted

This combination indicates that the

output

subsequent

longword of a big immediate specifier. Since no further formatting of
and the
the data is required, the contents of the SPC mux (low byte)
the IR
to
d,
unmodifie
IB1 to IB3 muxes (upper three bytes) are sent,
DATA

BUS.

SET BRANCH and SEQ LW both negated

both

Wwhen SET BRANCH and SEQ LW are
control

negated,

the

inputs determine the specifier data type.

remaining

Data Type

How Determined

Byte, Word

DATA SIZE <2:0> alone specifies the data size

since there
data

1s only one 8 bhit and

one 16 bit

type.

specifies a 32-bit data type,

Longword,

DATA SIZE <2:0>

Quadword,
D, G-Frioat

specifies a 64-bit data type,
DATA SIZE <2:0>
EXTRA BIT and TWO BYTE combincd tell which one

Octaword,
H-Float

DATA SIZE <2:0> specifies a 128-bit data type,
EXTRA BIT tells which one

F-Float

EXTRA BIT tells which one,.

format

Defining
To

the

Specifiers

completely

its

define

addressing

examining

the

SPC

<7:5>

such,

SPC

Format

Since

raw

less

than

Sign

specifier,

the

and,

<7:5>,

the

data
a

and

for

IB1l

Format

branch

<7>,

and

Generator must

offsets,

IB2

<7>

its

(SPC

sign.

bit

<4>

equals

basic

need

the

specifier

only

longword,

only

Addressing

addressing

formatted
three

when

the

addressing

mode

Literal

00x

SPC mux

contains

selects

SPC

are

Formatter/Scrambler

DATA

mux
BUS

All

displ

IBl

mux

Byte

relative

Data

Scrambler

and

deferred.

sign

extended

other
IB

used

and,

extension

1is

Operation

literal.
as

input

either

contains

deferred.

Generator

displ

110

deferred.

Data
and

unmodified

above

and

IB2

sign

and

from

Data

except

word
IB2

literal).

byte.

IBl1
to

displacement
<7>

has

Format

<7>,

Formatter

displacement

muxes.

(FP

data

(integer

later.)

displacement

derives

Scrambler

outputs

forces

output

DATA

BUS.

IBI

sign.

relative
deferred

addressing

extension
the

101

and

not

considered:

literal),
or
‘"scrambled"
(FP literal format is shown

Word

SPC
Data

and

this

bits

specifier

modes

<7:5>

Word

does

type.

Mode

Byte

determine

Generator).

usually

define

mode

Mode

DATA

bytes
BUS

at
in

modes

all.

the

same

either

Data

for

format

have

longword

these

modes

received

3-65

from

extensions

therefore

the

Data

output

Aligner.

Data Formatter and Data Scrambler Outputs

Table 3-14 shows which bytes the Data Formatter and Data Scrambler
output to the IB DATA BUS. The mnemonics SPC and IBl to IB4 refer to
the data selected from the IB Data Aligner muxes. SIGN refers to sign
extended branch offsets or displacements. The indicator "x"
that the data being output is not related to the current specifier
(but will have good parity).

"scrambled"

format

floating

Microcode "unscrambles" the data in the EBox.

point

3.4.4.5 1IB Read Example - Figure 3-24 (4 pages) shows the e
read operation for the decode cycles of the following instruc
ADDL3 #©X12345678,

B®04

(R3),

short

literals.

the

cr
3

Table 3-15 shows

Assumptions:

Instruction loaded into IB starting at byte 1 of longword O

microtraps

interrupts

occur

instruction

execution

The Data Formatter and the Data Scrambler are
the

during

example

the

FORMATTER.

shown

collectively

1in

Table

3-14

Specifier

1IB

Data

Type

Formatter

Data

And

Data

Formatter

Scrambler

Data

Output

Scrambler

Instruction

Literal

IBDATA4

IBDATA3

IBDATA2

IBDATAl

modes

integer

types

and

Float

and

Float

Immediate

SPC

All

class

See

notes

See

notes

mode

Byte

Word

IB1

IB2

IB1

Longword

Subsequent

Displacement

LWs

IB4

IB3

IB2

IB1

IB3

IB2

IB1

SPC

modes

Byte

SIGN

Word

SIGN

IB1

SIGN

IB2

IB1

IB4

IB3

IB2

IB1

Longword

Branch

instructions

Byte

offset

SIGN

Word

offset

SIGN

SPC

SIGN

IB1

SPC

Notes:

1IB
G

supplies

H-Float

first

longword

literals;

H-Float

1literals

are

literals

(Table

3-15).

in
3.

only
and

the

First

big

immediates

are

selected

mode

IB4)

longword

Entries
relative

for
and

upper

and

for

longwords.

in
same
format
as
G-float
Microcode performs format conversion

(9F)

address

quad/octaword

supplies

output

EBox.
longword

for

microcode

and

from

address
same

for

absolute

source

muxes

(IBl

also

apply

immediates.

displacement
relative

mode

deferred

3-67

specifiers
modes.

Table 3-15

Floating Point Short Literal Formats
IBDATAIL

IBDATAZ

76 543210

76543210

01 0000%xX

x x xx 0000

{emmm e >

F and D Float

010000O0O0

0 x x x x x x0

{mmmm e >

G and H Float

(V8]

SPC

<5:0>

IB MEMORY UNIT

LONGWORD 3 | LONGWORD 2 | LONGWORD 1 | LONGWORD @

wx | xx | xx | xx|wwlww|SB|B4|A3] 12| 34|56|78|BF|C1|vu

A7
IB RD ADDR <1:®>
Port A

READ PORT MULTIPLEXORS

= @2

Port

LW 2 byte

IB ALIGN CNTL <1:®

A3|12

P4l

L @

Port

34|56 78|B8F

Port

A byte

NEW OPCODE =

Get

121

4131}

UNFORIB

opcode fraom Aligner

opcode mux;

|Cl1l]|

ALIGNER MUXES

=01

Aligner selects data starting
at

34|56 | 78|

Ci|C
B8F | C1

store opcode

1in Cycle Opcode Register

FORMATTER

cYC

IB DATA

OPC

413|211

REG.

" IB FORCNT <1:0> = 90
No

format

output

change;

data as

121

56]

34|

To EBox

ouver

To Decoder

IB DATA BUS
Figure

3-24

ADDL3

Read

Example

#©X12345678,

3-69

B©®© 04

(Sheet

(R3),

IB MEMORY UNIT

LONGWORD @

LONGWORD 1

LONGWORD 3 | LONGWORD 2

)

8 = 01
IB RD ADDR <1:

READ PORT MULTIPLEXORS
A

Port A= LW 1

‘?G—flhuibaflmum-9|

—\

juyy

|y | yy

wx | xx | xx| xxlww]ww|S0|B4|A3| 12| 34| 56| uy

xx | wwluww]| S8} 84| A3]{12 | 34| S6

Port C = LW 3 byte @

2
t
B = LW
Por

ol
'

ALIGNER MUXES

IB ALIGN CNTL <1:® = 108

a]sl2]z]c|c

NEW OPCODE = @

Ignore Opcode byte:

1|10

UNFORIB

Aligner selects data starting
at Port A byte 2

A3 C1

ww lww | S8 841

get opcode

from Cycle Opcode Reg.

IB FORCNT <1:8>

Ir—

FORMATTER

= 91

Disp lacement positive;

IB DATA

zero

413121|1

2>
extend IB DATA bytes <4:

anl ol

v
To

EBeox

over

Decoaer

IB DATA BUS
Figure

3-24

ADDL3

IR Read Example
#©X12 345678,

3-70

B®04

(Sheet
(R3),

2 of
RO

IB MEMORY UNIT

LONGWORD 3
XX

| LONGWORD 2

LONGWORD

xxX|xxIxx|wu]lww|SR|v4]|

IB RD ADDR <1:®
Port

A = LW

Port

B = LW 3

Port

zzlzzlzzlzz

yyluyluyluy
) —

-2

A 4

B
|

—

READ PORT MULTIPLEXORS

C
byte

| LONGWORD @&

XX |

XX ]

XXl

ww]ww]|

—

SB|

:DNot usead

g
—

CYC

IB ALIGN CNTL

<1:®

Aligner

selects

A byte

Port

Opcod

——e

ALIGNER

data starting

REG.

MUXES

UNFORIB

S|0

413|12]1)|C]C

NEW OPCODE = @
Ignor

= 9@

'[__'OPC

byte;

get

opcod

e
XX

wwg

from Cycle Opcode Reg.

IB FORCNT <1: 2> = 08

Note:_

data as

IB DATA BUS not

for

this

PORMATTER

No format change;
output

relevant

DATA

4|1

31211

xXx|ww!l

specifier

Figure

3-24

ADDL3

Cl,

1IB

Read

EBox

over

DATA

BUS

Example

#©X12345678,

3-71

B©04

(Sheet

(R3),

Decoder

IB MEMORY UNIT

LONGWORD 3 | LONGWORD 2

LONGWORD 1 | LONGWORD @

uyjuy
x| xx | xx| xx|wwjww|SB|B4|zz]|Z2Z|ZZ|2zZ|UY yuyl

ADDR <1:®<1:@=> 18= 1@
11__13 RD
opcode byte
Point to inst
N ONTL
ALIG
| IB
ruction
of next

NEW OPCODE = @

Select opcode from Cycle Opcode Register

CYC
oPC

REG.

To Decoder

All outputs from IB except for the opcode

are don’t care during the opcode decode cycle

Figure 3-24

IB Read Example (Sheet 4 of 4)

(

ADDL3 #©X12345678, B®04 (R3), RO

NOTE:

3.4.5
The IB
The

1IB Manager Operations
Manager consists of the

PCNC

MCA

(Figure

3-25)

PCNC

MCA

and

supplies

the

part
read

the

address

IBST

MCA.

and

alignment

control
inputs
and
computes
the
amount of IB data consumed during
every decode cycle.
It also decodes the opcode
and
current
operand
specifier
and
supplies
some of the addressing inputs to the Decoder
RAMs.

The

IBST

has

entered

The

following

The

MCA

supplies
the

text

manager

preceding

3.4.5.1

describes
related

Read Address
IB

When microcode

FLUSH

initialize

EITHER

IB write

address

and

RD ADDR
invokes

are
IB

the

operations

functions

RD ADDR

ALIGN

FLUSH

Logic
<1:0>

when

longword

performed

the

IBST

the

MCA were

PCNC

MCA.

discussed

<1:0>

CNTL

causes

and

ALIGN
the

causes

the

ALIGN

CNTL

EITHER

FLUSH

Read

Address

<1:0>

VAX

mux

the

lower

outputs

right

EBox.

The

ONE

SHOT

FLUSH

the

Read Address logic to select OLD PC <3:2>
<1:0> and OLD PC <1:0> as the source for

forces

logic

the

which

ADDR

referred

rest

the

follows:

the

are

latched

Read

Address

responds

with

become

logic

OLD

issue

LW AVAIL.

Read

and
a

<1:0>

and

ALIGN

CNTL

four

bit

address

into

This

collectively

text.

3-73

the

"IB

<1:0>

DATA

signal

can

the

causes

for IB
<1:0>.

and will

pointer"

that
from

<3:0>.

as the source
IB ALIGN CNTL

the

Address

the two
flush,

NOTE

thought

ONE

logic

<K1:0>

the two inputs hardwired to logical 0
<1:0>, which equal VAX PC <1:0> after
mux

and

O
=

the

Full

<1:0>

signals

<1:0>

the

CNTL

This
and

Flush,

asserted.

RD ADDR

logic to select
receive VA FILE

ADDR

detects

sections.

Initializing

SHOT

the

IB.

g—

—

LW ACCEPTED

NO DATA IN IB
LW REMAIN<1:0> —

i
|
|

i
I
,

B FULL
\
NO LVAVE

I
I

OPCODE A<7:0>

TWO BYTE

I
p
J—-

BRANC- MODE
oPCO D

}

WATCHER | BRANCHO

BRANCHO SIZE <1:0>

FIRGT

IMDMODE

1
I

I
1

SPEC IS INDEX —]

NEW OPCODE —{ OPCODE

SEQ LW

L LW AVAIL<1:0>

INIT B —] CLR

I
I
I

SLOW BRANCH

L NO Lw AVAIL

LWAVB-<1:0>

g\IAZ“.AE 20

i
]

R4 NEW OPCO —

SPEC SIZE
SP<7:0>
o
PRED DATA SIZE<1:0> o}
—
NEW

OPCODE

SLOW SPEC SIZE<2:0=-

NITA

L SPEC IS INDEX

NO LW AVAIL —

OLD PC<3:00 —1
ASTALL ]

SILO NEW OPCODE

OPCODE NEXT

DEC SELECT<1>

IB READ

SEL OPCO

]
DLY 18 FLUSH ————
IB PAR ERR —————

NEW OPCODE

OPC <3:0>

ONE SHOT FLUSH —f}—|

L R4 NEW OPCO

| OLD PCB<3:0>

OLD PC<3:0~
T4

{Oz\

EITHER FLUSH

LW REMAIN<1:0>

NO DATA IN IB

[BMPTY

VA FILE<1:0>

PC INC<2:0:

;

18 oec noor or pe

|--———---.-_.....___.1

L\qvoREM

TRAP<1>

IB ALIGN CNTL A(B) <1:0>
5 oec noop

LK
<2:0>
VBUS PCINC<2:0>
|

LOGIC

SHIFT IB

IB RD ADDR< 1,0~

L
[

TEMPING <2:0
LW AVAIL<1:0> —
0>

18T SPEC SIZE<2:0> l—

SET BRANCH

OP IS FD

”

1B EMPTY
1B FULL
IBUFFER FULL

i
INIT A—

L o e e o

CLR

o e e MK V86-0731

Figure

3-25

PCNC

MCA

Block

Diagram

Computing
At

the

end

1IB.

for

become

two

Data

flush,

the

first

Full

decode

cycle

data

CBox

INC

will

and

new

the

LW AVAIL.

the

new

instruction.

for
on

any
the

value

cycle

<2:0>

bits.

the

EBox,

are

derived

Cycle
Active

Function

Opcode

First

Decode

Watcher

opcode

increment

of fsets

Size

logic

All

and

mode

first

specifier

position.

Note:

Also

active

decode

cycle

for

Compute

first
not

cycle

handled

Compute

all

byte

second

instructions

opcodes.

increment

for
by

those

amount in
specifiers

Opcode

Watcher

increment

amount

subsequent

3-75

branch

occupy

that

two

compute

for

immediate

specifiers

with

Specifier

byte

amount

specifiers.

IB
data

indicated

These

Sources

Source

the

I-stream

decode

data

asserts

enables

enough

given

sent

<2:0>

contains

MCA

TEMPINC

sources:

TEMPINC

I-stream

IBST
This

value

<2:0>

deliver

arrives

negates

check

required

increment

the

logic
to

Required

longword

logic

temporary

which

one

the

first

amount
a

Address

the

The
as

When

ACCEPTED,
Reid

Amount

for

bits,

from

3.4.5.2 Opcode Watcher Logic - The Opcode Watcher is enabled by the
This signal 1is asserted in the first cycle of
signal NEW OPCODE,
every instruction and, for the FD class two byte opcodes, along with
TWO BYTE in the second decode cycle.

When NEW OPCODE is asserted, the

Opcode

Watcher

checks

the

FIRST IMDMODE to see if the first specifier is immediate mode.

signal

If FIRST IMDMODE is negated, the Opcode Watcher then determines 1if the
instruction falls into one of the following categories:
HALT,

etc.

No operands - NOP,

Branch offset in first specifier - BNEQ, BSBW, etc.

FD class two byte opcode - ADDG2, MOVO, etc.

If the instruction falls into any of these categories, the Opcode
Watcher will indicate the amount of IB data required for the first
decode cycle on the BRANCHO SIZE <1:0> bits as follows:
BRANCHO

<1:0>

01
10
11

0 0

SIZE

Instruction Class

No operands or first byte of two byte opcode
Branch with byte offset (eg: BNEQ, BSBB)
Branch with word offset (eg: BRW, BSBW)
Otherwise

Note that BRANCHO SIZE <1:0> equal 2 for a branch instruction with a
byte offset and 3 for a word offset. This is because the opcode byte
is always consumed along with the first specifier bytes in the first
decode cycle of an instruction. (The only exception is the first byte
of a two byte opcode which is given in its own decode cycle.)

vVl

3-76

addition

asserts

the

encoding

following

BRANCHO

Signal

Function

BRANCHO

Forces

SET

BRANCH

TEMPINC

(TEMPINC

bit

Address

logic

Prevents

INDEX

from

asserted

offset
OP

FIRST

the

opcode

then

the

Since

IMM

the

includes
extension
follows:

SIZE

Opcode

Watcher

requires

Read

when

subsequent

last

specifier

instruction

(IBST

MCA)

cycle

and

asserted,

the

amount

<2:0>

bits.

byte

the

data
of

using

specifier

of
FD

class

the

TWO

BYTE

allow

two

Opcode

byte

<1:0>.

Read

signal

also

branch

ACBB.)

has

BRANCH

two

Opcode

byte

State

Silo

second

Watcher

opcode.

Watcher

size

operated

data

required

and

must
by

first

the

decode

instruction.

encodes

the

amount

of
IB
data
consumed
in
the
first
decode
cycle
opcode,
the
first specifier, and up to four specifier
bytes, the IMM SIZE
value
ranges
from
three
to
six
as
the

Size

IMM

SIZE

<2:0>

Example

Byte

011

MOVB

#©X12,

Word

100

MOVW

#©X1234,

Longword

110

MOVL

#©X12345678,

The

also

bits.)

from

SET

SIZE

stored

returned

instruction

second

the

logic

logic.

logic

increment

Address

Size

BRANCHO

amount

Extension

Note:

select

the

forced

opcode.

determine

computes

Asserted

IMDMODE
to

<1:0>,

mux

<2>

Spec

(eg:

decode

When

SIZE

signals:

increment

immediate

value

specifiers

for

the

subsequent

computed

3-77

the

RO
RO

longwords

Spec

Size

big

logic.

3.4.5.3
First
If

Specifier

Decode

the

Size

Logic

Cycle

first

specifier

the

Specifier

SPEC

SIZE

Size

not

1logic

will

type

handled

provide

the

some

four,

the

specifiers
1ST

specifier)

SPEC

six

have

SIZE

New

extension

<2:0>

(opcode,
1ST

value

specifier,
SPEC

SIZE

Opcode

bytes

can

longword

<2:0>

1ST

SPEC

010

1ST

have

011

CO - DF

. 100

SPEC

three

SLOW

and

cCycC

control

The

Speci

[

Decode

first

follows:

Size

110

000

Cycle

Size

logic

{2nd

SIZE

<2:0>

control

signals,

each

(opcode,

110
BF

for

<2:0>
010

the

Watcher,

value

Values

two

extension)

value

Opccde

others

from

Subsequent

and

range

<7:0>

the

increment

<2:0>,

Since

eCO
ecode

o6th

provides

the

increment

value

specifiers)

SLOW

Fa e ir

value

signals

and

Table

specifier

type.

based

from

the

IBST

3-17

3-78

the

TS T

SIZE

current

MCA.

indicates

SPEC

the

Table

SLOW

subsequent

<2:0>.
specifier
3-16

SPEC

byte

describes

SIZE

<2:0>

Table

3-16

Specifier

Signal

Indication

SLOW

Second

BRANCH

sixth

(eg:

last

branch

from

RAM

DATA

Size

SIZE

<1:0>

that

occupies

branch

from

Subsequent

being

all

SLOW BRANCH

offset

second

PRED

DATA

longword

from

IBST

DATA

Decoder

immediate

SIZE
big

SIZE

offset

instructions

from

sixth

Signals

branch

ACBx

processed.

Derived

Control

offset),

PRED

SEQ

Logic

specifier

Derived

Size

mode

specifier

<2:0>

from

immediate

<2:0>

from

RAM.

specifier

position.

Decoder

specifier

Decoder

Notes:

The

signals

class
2.

The

two

signals

indicate
3.

The
to

are

byte
are

data

not

used

opcodes

available

type/size

SLOW BRANCH

during

signal

unconditionally

the

(NEW OPCODE
in

for
also

assert

second
still

current

SET

3-79

asserted).

decode

cycle

but

specifier.

forces

the

cycle

the

Opcode

BRANCH

Watcher

signal.

RAM.
is

RAM,.

Table 3-17

Slow

Branch

Slow Spec Size <2:0> Values

SPp

.~ PRED Data

SEQ

Slow Spec

00 to 8E

00 1

101

100

010

011

90 to 9E

00 1

101

A0 to BF

010

CO0 to DF

01 1

EQO to FF

1 01

100

001

010

<7:0>

Size <1:0>

Size <2:0>

3.4.5.4
every

Checking
B

clock,

based

means

must

read

value

first

Full

AVAIL
LW

AVAIL

<1:0>

this

case,

that
for

the

value,

based

Read

on
of

are

number

valid

This

Read

current

data.

TEMPINC
<1:0>

output

Address

from

<2:0>

and

the

OLD

the

counter

keep

track

decoding:

currently

the

"empty").

longwords

LW AVAIL

yet

have

negated.

the

TEMPINC

only

therefore

logic

ignore

Stall"

knows

based

LW AVAIL

operation

that

old

<1:0>

data.
and

(described

The

OLD

value

Read
<1:0>

later).

state

current

the

byte

does

not

only

valid

informs

data,

not

data,

the

Read

Address

contains

enough

Read

cycle.

contains

enough

bytes

position)

and

available

the

from

LW AVAIL

available).

data,

Read

then

the

<1:0>

compares

Address

logic

OLD PC

<1:0>

bits
this

(total

amount

may

value.
enough

TEMPINC

the

some

decode

longwords

<2:0>

LW AVAIL

contains

<2:0>

pointer

the

value

Address

current

updated

logic

decode

remain

may

cycle

depending

unchanged

for

cycle.

initiate

instruction.
the

the

for

occur

could

maintains

available

(IB

value

LW AVAIL

3-25)

longwords

Address

could

"Decoder

contains

whether

the

all

Only

the

with

number

<1:0>

Encoded

the

TEMPINC

Figure

processed

the

wuse

AVAIL
of

not

(starting

the

AVAIL,

been

computes

number
the

reads

Deasserted

determine

bits

TEMPINC

validity

already

will

deasserted

first

the

Asserted

the

logic

AVAIL

(top

longwords

since

initiate

data

the

TEMPINC

value

Since

Asserted

1invalid

Address

and

logic

decoded.

AVAIL

logic

the

that

from

the

signals

LW AVAIL

number

the

The

over

use

determines

the

left

that

the

Validity

possibility

can

logic

<2:0>
a

’

signals

and

ensure

address

which

data

Dbefore

based

<1:0>.
The

I-stream

that

logic
The

TEMPINC

there

the

contain

"Decoder

enough

Stall"

data,

operation

3-81

the

Read

described

Address

below.

logic

the

will

data for
3.4.5.5 Decoder Stall - When the IB does not contain enough
te a
initia
will
logic
s
the current decode cycle, the IB Read Addres
NOOP OR PE.
"Decoder Stall" operation by asserting the signal IB DEC
The assertion of IB DEC NOOP OR PE causes the Special Address

logic

output

Encoder
of
place
in
ord
microw
STALL
the address of an 0S.IB.

the address that the Decoder would have otherwise generated (opcode or

specifier entry address).

request another
The only function of the O0S.IB.STALL microword is to ively
"stalls” the
effect
IB decode cycle (I DECODER bit set). This
to deliver
time
more
decode process for one cycle and allows the CBox
the required data to the IB.

by the end
1f the CBox fails to supply a new longword of I-stream data ed,
the 1IB
requir
is
rd
of the "stall" cycle or if more than one longwo
the
g
forcin
ed,
assert
Read Address logic will keep IB DEC NOOP OR PE
ord
microw
STALL
0S.IB.
Special Address Encoder to again generate the
address. This operation will continue until the CBox delivers enough
I-stream data for the current decode cycle.

ns enough data
3.4.5.6 Modifying the IB Pointer - When the 1IB contai
examines its
logic
s
for the current decode cycle, the IB Read Addres be modifi
ed by the
other inputs to determine if the IB pointer should
cycle.
next
the
TEMPINC <2:0> value or remain in its current state for

Address logic
Figure 3-26 is a conceptual block diagram of the IB Read
of the figure
top
The logic at the
that controls the 1IB pointer.
in the
determines if the IB pointer should point to the opcode byte the
next

first decode cycle of an instruction or to the byte preceding of the
specifier for a subsequent cycle. The logic at the bottom
figure determines if the pointer will stay in its current state or be

modified by the TEMPINC <2:0> value.

Read
Table 3-18 shows the relationship between the inputs to thenextIB decode
the
Address logic and the state of the IB pointer for
refers
cycle. The mnemonic OPC refers to the OLD PC <3:0> bits, TPC signal
input
to TEMPINC <2:0>. The indicator "-" means that the given
is "don't care". For example, if DLY IB FLUSH is true (1), all other
signals

are

ignored.

SILO NEW OPCODE

—

R4 NEW OPCODE

OPCODE NEXT
DO
—— SEL OPCO

IB-SHIFT

]

ENA
1

)

——

INDEX

SEL

BRANCH

SEL

TRAP

DEC STALL

T‘\

DEC NEXT

Q__/

/
0

DLY IB FLUSH

s__/

}

PC INC <2:0>

TEMP INC =2:0>
A+B

OLD PC <3:0>

'
=

—

SEL

OPC <3:0>

IB RD ADDR <1:0>

SEL

-1

ALIGN

CNTL

<1:0>

ere—

-1
DLY IB FLUSH

DEC STALL ——(O
1B SHIFT

SEL

IB DISPATCH

DEC NEXT

MKV8E-1141

Figure

3-26

Simplified

3-83

Read

Address

Logic

OPCODE | R4 NEW | SILO NEW

DLY IB

0
IA

1
0

v8-¢

DEC

0
1

1
0

0
J
1

Pointer

opPC

Full IB Flush

OPC

Subsequ

OPC -1
oPC

OPC -1

oPC
OPC -1
orC
OPC -1

OPC + TPC

first decode cycle
Trap during
ent cycle
Stall on first decode cycle

Subsequent cycle

e - first cycle
IB decod
NoSubseq
uent cycle

Execute cycle - most inst.
Shouldn’t happen
Execute cycle - optimized inst.

OPC + TPC -1 |Normal subsequent spec. cycles

OPC + TPC -1 |Index mode specifer

REMARKS

New IB

OPC + TPC

Last specifer branch offset

OPC + TPC -1 | Shouldn’t happen

OPC = OLD PC <3:0>
TPC = TEMPINC <2:0>
MKV86-1140

3.4.5.7

Read

describes

the

which

appear

DLY

they

This

Address

1IB

Read
in

Table

Control
logic

Signals

control

signals

This
in

section

the

order

3-18.

FLUSH

signal

asserted

OLD

<K3:0>

bits

are

initialized

opcode

Logic

Address

the

Dbits
new

during

become

during

full
the

full

instruction

new

flush
IB

force

pointer.

partial

delivered

flush

the

(The

unmodified

OLD PC

point

<3:0>

the

IBR,)

TRAP

The

TRAP

signal

Microtraps
Thus,

the

are

detected

assertion

instruction
To

indicates

caused

determine

that

late

TRAP

the

trap.

cycle

was

the

state

NEW

OPCODE

the

IBST

MCA

1issues

which

decode

cycle

four

OPCODE

cycle
the

Decode

old

First

Negated

Subsequent

TRAP

(see

Figure

During

the

negated,

exits.
cycles

asserted,

3-25),

and

SILO

(Microcode
within

trap

the

copy

of
new

time

signal

mean

the

SILO
NEW

that

time).

the

current

trap,

NEW

the

OPCODE.

OPCODE

instruction

T10

signal

and,

that
such,

follows:

Progress

cycle
cycle

NEW OPCODE

returned

ensuing microtrap
forcing

the

progress

Cycle

Asserted

When

start

(canonical

necessarily

progress

was

occurred.

pipeline

not

saves

SILO

NEW

the

does

logic

Address

SILO

microtrap

which

Read

indicates

does

both
be

not

routines.)

3-85

output

SEL

OPCO,

latched

NEW OPCODE.

routine,

NEW OPCODE

convention

TRAP

and

recirculated

allow

"nested"

DEC
until

traps

SELECT

are

the

routine

decode

invoked
1is
flush
IB
At the end of the microtrap routine, a partial
used
then
is
OPCODE
NEW
R4
bits.
<3:0>
the OLD PC
initializes
which
to select

the

appropriate

IB pointer source:

Trap
During

R4 NEW
OPCODE

IB Pointer
Source

Reason

First

True

Unmodified

Points to opcode byte

Subsequent
Cycle

False

Cycle

In either case,

first

decode

OLD PC

of trapped instruction

OLD PC-1

Points to byte preceding
specifier being processed
when

trap

occurred

the IB pointer will address the proper IB byte in

cycle

after the

trap

the

released.

NOTE

Microtraps that occur in the "shadow" of a full
flush
(DLY IB FLUSH asserted) are ignored by the logic.
DEC

STALL

Indicates

When

that a Decoder stall condition

DEC STALL is true,

the

is present.

IB Read Address

logic uses R4

NEW

OPCODE

determine if the stall occurred during the first decode cycle of a

new

instruction or

some

subsequent

NEW

cycle:

Stall during

OPCODE

IB Pointer Source

First

cycle

True

Unmodified OLD PC

Subsequent cycle

False

OLD PC -1

R4 NEW OPCODE is also used when DEC STALL
and
DEC
SELECT
are
both
negated.
This condition is the norm when there is no Decoder stall or
IB decode request.
The selection of the source for the new IB pointer
is

described

above.

Quiescent

The

above

pointer

along
To

operations

with

ensure

cycle,

DEC

This
and

the

pointer

Read

latching

for

OPCO

would

(The

cause

text

assuming

the

would

DLY

not

<3:0>

and

change

for

all

the

OLD

<3:0>

value

used

instead,

and

the

decremented

decrement

remaining

FLUSH,

TRAP,

the

value

DEC

this
1

the

manner

assertion

PC-1
the

STALL

value.

latches.)

the

OLD

inputs

and

the

<3:0>

1IB

data.

external

were

the

requested

for

OLD

the

enough

state

the

force

"shift"

contains

returning

3-25

select

the

they

recirculates

pointer

describes

that

does

common:

until

and

Figure

pointer mux

logic

following

OPC

(see

state

logic

recirculating

thing

below)

Address

<3:0>

the

value.)

Read

Address

all

negated.

decode

request

are

SELECT

signal
causes

specifier

PCNC

for
When

the

state

keep

(if

decode

DEC

SELECT,

time

from

pointer

issues

Decoder

generated

entry

address

for

microroutine

required)

the

pointer

preparation

cycle
the

the
in

microcode

occur:

opcode

SHIFT
the

selects
or

MCA modifies

the

receives
of

each

operations

Microsequencer

should

asserted

two

the

(see

the

one

current

SELECT

1if

logic

have

its

QLD

reason

cycle.

this

that

The

DEC
that

The
SEL

stay

the

does

cycle

State

Read

Decoder
its

current

cycle.

3-87

Address

RAMs

logic

(DRAMs)

state

first

examines

determine

or modify

for

it
the

SHIFT

cycle of
SHIFT IB is always asserted by the DRAMs in the first decode data
is to
every instruction and whenever the next block of I-stream
be shifted out of the

IB.

gic selects either the
IFT IB is asserted, the IB Re ad Address logl
OLD PC + TEMPINC value or the OLD PC + TEMPINC-1 value as the source
If the signal 1is negated, -either the
of the new IB pointer.
unmodified OLD PC value or the OLD PC-1 value is selected.

The selection of one of these sources depends on the

state

other input signals which are used in conjunction with SHIFT IB:

three

Asserted if the specifier is the branch offset

SET BRANCH

of a PC control (BNEQ, BBC, etc.) or a loop
control (ACBB, AOBLEQ, etc.) instruction.

Also asserted in the first, and only, decode
cycle of an instruction that has no specifiers
(HALT, NOOP, etc.), and in the first cycle of
an instruction with a two byte opcode.

INDEX

Asserted if the specifier is index mode.

OPCODE NEXT

Asserted by the DRAMs if the next decode cycle

will be the first cycle of a new instruction.

Note that SHIFT IB and OPCODE NEXT, like all other DRAM

outputs,

are

the
issued during the current decode cycle but control operations for time
the
to
prior
le
availab
are
signals
next cycle. Therefore, the
the logic receives DEC SELECT from microcode.

The following assumes SHIFT IB is asserted when the current

SELECT.

o
0

DEC

issues

routine

microcode

SET

BRANCH

Since

a branch offset
instruction, the next
new instruction.
If

SET

BRANCH

signal,

which

TEMPINC

value.

This
of

flush
is

class

instruction

the

cycle

will

should

the

operation

also

used

two

following

the

one

case,

pointer

fail.

the

has

and

of
the

(On

macrobranch

selects
opcode

the

cycle

the

INDEX

the

OLD

byte

branch

the

success,

the

pointer,)

pointer
to

a
first

ignores

and

the

initialize

opcode

logic

this

modify

that

specifier
always

Address

branch

would

byte

last
will

the IB Read
meaningless is

This

method
a

always

true,

1is

instruction

ensuing

decode

for

point

the
the

second
opcode

specifiers.

byte
of

the

NOTE

long

hardware
and

the

DRAMs

failure

are

properly

exists,

SET

BRANCH

are

negated

should

never

the

both

case

asserted

1loaded

and

which

SHIFT

in
and

OPCODE

occur.

INDEX

The

assertion

specifier

this

OLD

the
of

case,
+

the

will

SET

BRANCH

negated

(It

takes

the

index

Read

value

address

least

immediate,

longword.)

means

mode.

logic
as

will

the

new

the

base

cycles

ignore
IB

two

operand

and

additional

one

operand

process

for

cycles

the

are

The

OPCODE

pointer.

specifier.

for

big

INDEX with

TEMPINC-1

pointer
the

indexed

base

that

This

the

and

will

current

select
ensure

the

second

decode

index

mode

specifier:

operand.

required,

one

for

the

each

base

the
that

cycle

one
is

INDEX signal is especially important when the last specifie
r of
instruction
1is indexed since the base operand byte would otherwise
interpreted as the opcode of a new instruction.

3-89

subsequent

OPCODE

When SET BRANCH and INDEX are both negated, the state of OPCODE NEXT
determines whether the IB pointer should address the opcode byte of a
new instruction or a subsequent specifier of the current instruction.

If all specifiers of the current instruction have yet to be processed,
the DRAMs keep OPCODE NEXT negated. This forces the IB Read Address
logic to select the OLD PC + TEMPINC-1 value which points to the byte

preceding the next specifier to be processed.

After the last specifier is processed, the DRAMs negate SHIFT 1IB and
assert OPCODE NEXT. This forces the IB Read Address logic to select
the unmodified OLD PC value since this value points to the opcode byte
of the next

instruction.

NOTE

IBST MCA to 1issue NEW
OPCODE NEXT alsoc causes the
However, the IBUF MCAs will
OPCODE to the IBUF MCAs.
not use this signal until the next decode cycle,

Optimized

Instructions

The only exception to the operand specifier processing described above
is the decode cycle for the last specifier of "optimized" instructions
1In this cycle, the DRAMs assert both SHIFT 1IB and
such as a MOVL.
OPCODE NEXT to force the selection of the OLD PC + TEMPINC value.
This is because the execute code for optimized instructions 1is
incorporated in the last specifiers microroutine. Thus, there is no
decode cycle to generate the entry point address for the execute
U R

)

|98

[

miCroCcoae.

Computing Number Of IB Longwords
3.4.5.8
the IB pointer, the IB Read Address logic
of

longwords

consumed

during

the

TEMPINC

<2:0>

(bytes

Summing

(starting

byte

longword
current

decode

cycle.

This

that

also

will

When

does

yields
be

compute

requested)

position).

boundaries

Consumed
must

crossed

number

this

OLD

the

wupdates

the

by:

<1:0>

number

accessing

IB
the

specifier.

Subtracting
compares

above

the

actually

sum

from

number

available

the

AVAIL

<1:0>.

1longwords

This

requested

effectively
to

the

number

1IB,

NOTE

LW AVAIL

<1:0>

false.

always

equal

actually

available,
Based

the

than

the

This
1

LW AVAIL

1is,
if

AVAIL

false,

the

number

they

equal

two

is
bits

1longwords

longwords

are

etc.
of
the

means

1less

meaning

with

available,

than;

"< "

result

one

have

available.

longword

performs

only

addition,

less

this

comparison,

operations

below

than).

3-91

the

(the

Read
symbol

Address
">"

logic

means

then

greater

Result
0

Amount of
Data in IB

IB Read Address Logic Response

Just enough

Clear
DATA

LW
IN

REMAIN <1:0> and assert NO

IB.

IB Full logic will issue NO LW AVAIL
next
to cause a Decoder stall in the

cycle if the CBox does not deliver

new longword in time.

than

More
enough

Negate NO DATA IN IB and indicate
LW
number of longwords remaining as
REMAIN <1:0>.

LW REMAIN <1:0> become LW AVAIL <1:0>
the CBox does
in the next cycle if
not deliver a new longword.

Not

enough

Return LW AVAIL <1:0> and NO LW AVAIL
LW REMAIN
as
1logic
to the IB Full
<1:0> and NO DATA IN IB.

Note: The IB Read Address logic would
have already invoked a Decoder stall
by asserting IB DEC NOOP OR PE.

3-92

3.4.6

Refer

1Instruction

Figure

following

Decoder

3-27.

instruction

decode

logic

<consists

components:

Special

Address

Part

the

Primary

Operation

The

bit

Decoder

RAM

Decode

(DRAM)

Encoder

IBST

MCA

the

Generate

opcode

the

and

entry

current

point

operand

address

specifier

for

all

operand

specifier

microroutines
®

After

all

address

specifiers

for

instruction
®

Monitor
routine

Assist

Decoder

reduces

signal

3.4.6.1

I DECODER

routine
its

CSO

micro-PC

to
RAM

code)

DEC

UADDRA
of

initiate

address

MCAs

CS0

there

with

may

last

next
the

that

all

microword

latches.

3-93

affect

address

The
not

the

instruction

address

the

are

point

for

the

sent

are

the

<13:00>.

This

latches.

Decoder

operates

explicitly

controlled

bit,

I _DECODER,

which

pipeline.
of

decode

signal

work

UADDRB

microword

the

entry

microaddresses,

DEC

the

actual

point

microaddress
and

one

the

controlling

micro-PC

the

Considerations

Decoder

the

<13:00>
the

the

latch

which

the
entry
the condition

IBST

pipeline

However,

data

and

Timing

couples
set

conditions

copies

the

generate

performs

generate

services

microcode.

effectively

execute

microaddresses,

Pipeline

asynchronous

(the

PCNC

Two

microsequencer,

that

which

generated

wide.

processed,

routine

and

the

are

the

"special"

execution

the

Functions

bits

DEC

every

cycle.

specifier

and

The

output

bit

SELECT which

sent

opcode

from
the

DRAM BIT

POSITION

IBUF

SP <7:0>

Teo s

SET BRANCH

DEC SELECT

IB DEC NO

eSIZE <1:0>
PRED DATA

EXTRA BIT

<14 >

IBST

MCA | INDEXED OR INDEX PC

SPEC TYPE <30>

RAM SLOW BRANCH

SPECIAL ADDRESS ENBL

IBST and PCNC MCAs

OPERAND DATA SIZE <2:0>

<4:2 >

IBST and PCNC MCAs

MCA
IBST MCA
IBST

6
=z

IBST and IBFO MCAS

.
<1:0 >
1

SEL

USE OPCO ADDR ————

SHIFT IB A

SPECIAL

Other Special
Conditions from

ADDRESS
ENCODER

CBOX and IBOX

DRAM <16, 19, 12:6, 4:0>
DPAR2

—

(IBST DATA %le <20 >
IBFO DATA SIZE <2:0>)
an

UADDRA(B) <13:00 o —— DEC
To Micro-PC

FRC

IB PE <1:0>

DLY OPN XOR IBS

7
AAddress Encoder

<13 >
<12 >
<5 >

IBST DATA SIZE <2:0>

CD PE <1:0>

BFO MCA

OPCODE NEXT

SLW RADDR <8:4> = OPCODE <7:3>

\
7~

DRAM Parity Checker

Special
FADS MCAs

ACCESS TYPE <1:.0 >

Part | SPEC WAS RMODE

‘

Special Address Encoder

119
<./
8.7 >

RAM SLOW BRANC H

GEN'R

SHIFT IB

OPCODE NEXT
)

DPAR2

<15 >

DRAM ADDR <11:00> RAM MD NUM
oEC
RN I PRED DATA SIZE <10<1.0 >
E Rgoggg

C 3
NO <2:0>|
SPE
8

OP IS FD ‘

<16>

IB B
SHIFT
prp—
ADDR
oP
DECODER
>
<2:0

OPCODE <7:0>

MCAS

SHIFT IB A

DESTINATION

Address latches
(SEQ MODULE)

SEL SPECIAL ADDR

SPECIAL ADDR <3:0>

DRAM PE

DRAM
PARITY
CHECKER

IBOX Error Register

and Micro-trap logic
(UTRP MCA-SEQ module)

MKV86-1142

Figure

3-27

Instruction Decode

Logic

The

state

the

microaddress

DEC

SELECT

selected

SELECT

Asserted

Decoder

logic.

I_DECODER

the

that

T3
IB,

the

outputs

CSO0

The

SELECT

decoder

micro-PC

and

commonly

MCAs)

canonical

DEC

SELECT

the

and

the

correspond
is

micro-PC

during

with

these

address

current

presented

TS5.

microword

the

address

the

or
the

I-stream

data

entry

address

for

opcode)

time

latches

states

perform

block

generate

execute

SHIFT

data.

SELECT

from
of

the

entry

no more

the

negated,
this

are

data

asserted,

processed.

for

specifiers)

T3
the

case,

both

address

1In

3-95

DRAM

I-stream

cycle.

select

DEC

the

code

latches

set).

SHIFT

routine.

latches

address

(I _DECODER

I-stream

(or

address

micro-PC

SELECT
of

block

signal

(or

DEC

block

the

output

then

same

(UBRS

executed.

supplied

will

the

RAM

generates

routine

available
either

asserted

will

specifier

same

Next".

latched

and

specifier

Decoder

the

Relationship

current

Decoder,

Decoder

DEC

the

operation

"Dec

logic

CS0

latches

Source

functions:

then

source

latches:

Operation

the

microword

respective

Time

the

address

This

Timing

from

bit

address

the

their

The

micro-PC

Canonical

Basic

output

microword.
to

Microsequencer

Pipeline

determines

micro-PC

Microaddress

referred
Negated

signal

the

and

make

time.
IB

the

will
Decoder

output
will

the

output

3.4.6.2
address

Operand Specifier Entry Point Addresses - The entry point
for an operand specifier microroutine is derived from three

sources.

Figure 3-28 shows the format of the entry point address and the source

each

bit.

Table 3-19 briefly describes how the

address

bits

are

derived

and

used.

data
Table 3-20 shows the relationship between the operand specifiers
same
the
1s
3-20
Table
in
used
on
size and its access type. The notati
that
means
.RW
e,
exampl
For
card.
as that used on the VAX programming
the operand is read access, data size is word,

DEC UADDR <13:00>

13 12 11 10
1

SPEC

Special

08 07 06 05

l«— Address

04 03 02

OPERAND | ACCESS

DATA SIZE

TYPE

<2:0>

<3:0>
IBST MCA

TYPE

<1:0>

DRAMs ———»|

Encoder

MKV86-1131

Figure 3-28

Operand Specifier Entry Address Format

3-96

Table 3-19

Operand Specifier Entry Address Bit Descriptions

Bit(s)

How

13:10

Forced

(*)

state

special
is

DRAM

signal

USE

specifiers

except

branch

not

have

own

the

their

execute

INDEXED

current

decode

index mode

processed

Based

for

the

IBST

Represents

big
-

from

the

IBST

process

the

(The

specifier

subsequent

DATA

SIZE

either

the

immediate

negated

for

offsets

are

serviced

specifier

Asserted

the

base

index

byte

cycle;

see

byte,

bits

specifier

they

MCA.

longwords

<2:0>

text).

from

the

operand
would

have

text.)

<7:0>,

big

from:-

the

immediates,

the

DRAM,

type

which

being

processed:

longword

Literal
PC

absolute

(all

sizes)

relative

(all

sizes)

PC relative deferred (all sizes)
Index (index byte, not the base)

Auto-decrement

Auto-increment

Displacement

(all

Displacement

deferred

Immediate:

OO~

WNOHFHO

(see

Encoder

later).

Branch

since

either

or,

ADDR which

offsets.

cycle
in

Address

(discussed

cycles

specifier.

been

OPCO

decode

microcode

INDEX

Special

pending

Bit

04:00

indicated

condition

all
by

08:05

Derived

deferred

Immediate:

deferred

Byte,

sizes)
(all

Word,

sizes)

Longword,

F-float

lst

LW of

Quad/Octaword,

2nd

Quadword,

D/G-float

4th

LW of

Octaword,

H-float.,.

Immediate:

2nd

LW of

Octaword,

H-float.

Immediate:

3rd

LW of

Octaword,

H-float.

DRAM

bits

mode

cases,

<4:0>.
the

See

Encoded

current

Table

with

operand

3-20.

3-97

the

data

except

for

or,

D/G/H-float.

size

or,

and

certain

access
special

Operand Data Size/Access Type Correlation

Table 3-20

OPERAND DATA SIZE <2:0> --> DEC UADDR <4:2>
--> DEC UADDR <1:0>
[———ACCESS TYPE <1:0>

Not used - Reserved for TRAP vector address space

Not used - Reserved for future expansion
Illegal

w N = O

.RL,

w N

.RW
<MW

. AW

WW - Also,

.MW for ADAWI only

.RF

LML,

.MF

.AL,

.AF

WL - Except for special

.WLs below

Special - .WL and set CCs' for optimized instructions
Special - .WL 3rd spec of EDIV; 4th spec of EMODs'
(eg: BBC through BBSSI)
.VB - Normal case
.VB - Abnormal case

.AG,

.AQ

WD,

WG,

.AQ

wN = O

.MQ

+AD,

.RQ

.MG,

.RB

w N

.RG,

.MD,

.RD,

.AB

wN = O

opcode

Not used - Reserved for future expansion

w N = O

Operand Specifier Notation or Special Case

.RH,

(eg:

CMPV,

CMPZV)

.MB
.WB

.RO - Except first specifier
There

are

A L N

no
2N

® L dNs

enecifiers

uk/ vvvvvvvv

.AH,

.AO

WH,

.WO

.RH,

.RO - First specifier only

w N

W N

—

Mg
[

.MH

- ACBH only

Illegal - Should never be encoded
Illegal - Reserved for Special Addresses

3-98

Operand

Specifier

Entry

Point Address

Labels

Each operand specifier entry address is assigned
OPSP.MIC (OPerand SPecifier MICrocode) module of

Taple 3-21 shows the operand specifier entry
the mnemonics used in each label field.

Example:

Specifier
read

access,

(Rn)+,

not

a unique label
the microcode.

address

label

format

the

and

indexed,

longword

Reserved
Certain
in

ANMNMDECC

When

Label

3908

OS.AINC.NI.RD.LF

Addressing
specifier

reserved

AL LIINDTWD

Address

Mode

Faults

addressing mode

addressing

mode

and

access

faults.

For

type

combinations

example,

result

with

ar~r~o

reserved

addressing mode

fault

occurs,

the

Decoder

will

still

generate
an
entry
address for the specifier.
However, all routines
entered in this manner contain code to immediately transfer control to
a reserved addressing mode fault service routine,

The reserved addressing mode fault
service
routine
resides
1in
the
IANDE.MIC
module.
The routine starts at the label IE.FLT.ILL.ADR and
is entered by the GOTO macroexpression as follows:

Example:

Specifier

RMODE,

not

indexed,

address

access,

longword

Address

Label

Microword

38AA

OS.REG.NI.ADR.LF

GOTO

3-99

contents

[IE.FLT.ILL.ADR]

Table 3-21

Operand Specifier Entry Address Symbolic Labels

Label format:

Field
oS

OS.AAA.BBB.CCC.DDD

Meaning

Mnemonics

OPSP.MIC

N/A

module

AAA

Address
mode

{--+

LIT

Literal

REG
RDEF
ADEC

DIS

Displacement

ABS

Absolute

RLDEF

Relative deferred

IND

AINC
AIDEF
DSDEF
IMM

REL

Indexed

Auto-increment
Auto-increment deferred
Displacement deferred <-+
-+
Immediate

Relative

BBB

Index
mode

I
NI

Indexed
Not indexed

CCC

Access
mode

ADR
ILL2B

Address
Illegal opcode

MOD
RD

WRT

DDD

Data
size

<-4

General
Register
Addressing
Modes

PC Addressing

Modes

Modify
Read

Write,

ncormal

case

- used for

WRTCC

Write and set CCs'

WRTNLST

Write/not last specifier - 3rd spec

instructions

optimized

VLD
VLDRD

of EDIV, 4th spec of EMODs'
Vield - last operand only
Vield - not last operand

BYTE
WORD
LF

Bvte
Word
Longword and F-float

HO
HOFST

H-float, Octaword (not first operand)
H-float, Octaword (first operand,

DGQ

OoDD1
ODD2

D/G-float,

Quadword

read only)

H-float 3rd operand (modify only)

Special; used with WRTCC, WRTNLST,
VLD and VLDRD

Special;

used with ILL2B

The

major
1.

functions
Restore

the

VAX

IE.FLT.ILL.ADR

GPRs

the

routine

state

they

are

were

to:
in

prior

the

System

Control

fault

When

Form

the

exception

Block

(SCB)

fault

routine

will

push

fault

the
the

instruction

One

entry

address

With

the

following

entry

address

for

and

entry

per

item

immediate

should

routine

stack

will

and

which

report

determine

the

1if

the

only

one

aborted.

Decoder

will

generated
by

the

require

one

for

execute

generate

for

two

the

(but

not

big

literal)

address

for

each

only

branch

entry

base.

also

services

offset.

The

code.

entry

literals

control

appropriate

Software

the

specifiers

immediate,

that

the

processed

and

Big

passes

into

specifier:

1index

separate

(hex)

specifier

address

mode

onto

exceptions,

1Index

software.

each

Big

restarted

offset

the

exits,

PSL
system

can

vector

the

addresses,

(If

the

one

base

for

big

applies.)

require
the

one

mode

specifiers

require

entry

specifier

address since
supplies
the

macrobranch

instructions:

the routine
additional

longwords.
Branch

There

offsets

are

two

general

classes

Branch

Class

Description

Simple

branch

Offset

(BNEQ,

BRB,

and

BRW,

etc.)

Loop

control

(ACBx,

BBx,

AOBx,

etc.)

only,

the

Decoder

first,

specifier

last

always

specifier

the

Immediately

generate
for

address

Generate

for

3-101

the

code.
entry

execute

Action

entry

execute
Offset

longword.

address

code

last

processed.

after

specifier

In either case,

DATA BUS,

Index mode

the branch offset

is sign extended,

and summed with the VAX PC during

output to

the execute

code,.

the

1IB

specifiers

The signal INDEXED OR INDEX PC from the IBST
MCA
determines
if
the
Decoder
1is
to
generate the entry point address for the index or for
the

base operand microroutine.

Indexed or Index PC

Indication

Negated

If SPEC TYPE <3:0> = 4,

index operand.
not

Asserted

Big

immediate

specifier is an

Otherwise,

specifier is

indexed.

Specifier

the base operand.

specifiers

the
wide,
bits
Since Quadword, D-Float, and G-Float data are all 64
value
represented
by OPERAND DATA SIZE <2:0> for these data types is
the same.
This
means
that
the
routine
that
services
the
first
longword
of
a
Quadword
big
immediate is also the one used for tne
first longword of a D or G-float
immediate.
This
also
applies
to
Octaword
and
H-Float
data
since these data types are both 128 bits
wide.

As each

longword of a big

MCA

updates

the

The

IBUF MCAs and the

immediate specifier is processed,

the

IBST

SPEC TYPE <3:0> bits so that a different routine is

entered to service the next longword.
This
ensures
that
the
EBox
logic will be conditioned according to the longword being processed.

formatted

before

being

IBFO MCA ensure
sent

the

3-102

that each

EBoX.

longword

1is

properly

Specifier
Some

routine

specifier

require
®

two

length

types

Specifier

types

and

displacement

All

relative

Specifier

handled

serviced

All

Literals
®

can

microwords:
by

Microword
specifier

except

multiple

(except

auto-increment).

modes

literals

and

modes.

bit

I _DECODER

routine.

the

for

the

current
at

least

either

case,

cycle,

address

the

CBox

if
the

except

always

set

word

specifier

routine

the

starts

cycles

Special

the

single

two

routines

than

longword.

microword

routines

deferred.

immediates.

does

the

last

requested
T3

time).

before

contain

enough

Encoder

will

data

3-103

the

cycle

multiple

word

data

every

that

clock

for

continually

stalling

IB.

For

means

one

the

not

(3BFF),

this

only

Address

required

microword

routines,

(next

elapse

0S.IB.STALL microword

delivers

bigger

For

requested,

decode

not

mode.

indexed

after

routines,

deferred

others

deferred.

serviced

absolute

while

deferred.

types

Big

cycle

microword

immediates

All

decode

microword

and

Auto-increment

single

except

Auto-decrement,

All

deferred.

modes
modes

decode

the

output

decoder

the

until

operand
all
Microaddresses - After
Point
Entry
for branch
(except
processed
are
instruction
an

Opcode
3.4.6.3
of
specifiers

offsets),

the Decoder then generates the entry address for the execute

code.

The only exception to this are the "optimized" instructions, such as a
MOVL,
which
do
not
have
a separate opcode decode cycle since they
incorporate the execute code in the last specifier routine.
g F
ANV

ZWiraAle

LAV

Figure 3-29 shows the format of
the
opcode
entry
address
and
the
source of each address bit.
Table 3-22 briefly describes how the Dbits
derived

and

used.

DEC UADDR <13:00>

03 02 01

OPCODE

<7:3 >

<2:0 >

109108 07 06 05 04

D
E

T
E

Special

«—— Address —»

o—— [BUF MCAs —»te—— DRAMs —

Encoder

IBST MCA
MKVBE-11

Figure

3-29

Opcode

Entry

3-104

Address

Format

A
N

are

Table

Forced

Bit

SPEC

state

Bit

Descriptions

actually
all

WAS

was

copy

DRAM

opcode

RMODE

from

IBST

OPCODE

opcode

byte

opcode

bits

DRAM

bit

<03:01>.,

Equal

USE

One

byte

opcode

Two

byte

opcode

Encoder

OPCO

Asserted

from

opcode

3-105

ADDR which

specifier

addresses.

last

IB.

itself

take

<0>.
]

signal

MCA.

<7:3>

byte

bits

Address

Two

DRAM

Special

entry

One

03:01

pending.

for

instruction

Latched

indicated

condition

asserted

08:04

Address

Derived

special

Entry

13:10

How

Opcode

Bit(s)

3-22

the

two

<2:0>.

values

order

Two Opcode Entry Points Per Instruction

one when the 1last
Most instructions have two execute routines:
when the transfer
one
and
r,
transfe
data
operand required a memory
which routine
nes
determi
bit
RMODE
involved a VAX GPR. The SPEC WAS
is

entered:

SPEC Was RMODE

Execute Routine Entered

Asserted
Negated

Two opcode entry points exist even for instructions with no operands
and for the simple branch instructions; microcode requires there be a
valid first microword at every entry point.

Exception:

Reason:

Instructions whose last specifier is

access,

ADDRESS

such as an ADDP4

RMODE mode with ADDRESS access is a reserved
addressing mode which would be detected while

Therefore, the entry
decoding the specifier.
address for the register transfer code could
never be

generated.

Opcode Entry Address Symbolic Label

The symbolic label assigned to an opcode entry address ends with .MEM
for the memory transfer code and .REG for the register transfer code.
Instruction - ADDL2

3F80
3D80

INT.ADDLZ.REG
INT.ADDLZ2.MEM

Asserted
Negated

(o))

Label

Address

SPEC Was RMODE

Example:

While

operand

execute

Module

routines

reside

Name

Instruction

CHARSTR.MIC

Character

PC,

DECIMAL.MIC

Decimal

EDITPC.MIC

BEdit

FLOAT.MIC

Floating

INTLOG.MIC

Integer

LDSV.MIC

Load/Save

MULDIV.MIC

Integer

MXPR.MIC

Move

PCALL.MIC

Procedure

loop

Queue

Variable

decoder

without

logic

Entering

String

and

one

module

and

CRC

subroutine

control;

CASE,

with

Simple

Multiply

Context
and

Divide

Privileged

Call/Return
length

bit

Execute

Code

field

generates

specifier

Illegal

one

Reserved

First
Instructions

The

DRAM

USE

OPCODE

address

byte

With

ADDR

the

specifiers

(BNEQ,

byte

escape

immediately

for

branches

opcode

address

for

(BPT,

HALT,

BEQL,

opcodes
opcodes

two

byte

BRB,

(57,
(FE

59,

and

the

entry

opcode

Simple

issues

OPCO

ADDR,

the

DEC

UADDR mux

instruction.

3-107

5A,

address

instruction

etc.)

5B,

77)

(FD)

and

USE

NOP,

BSBB,

point

following

FF)

Specifiers

forces

JMP

Logical

Process

types:

Those

(OPSP.MIC),

point
and

immediately

preceding

Types

to/from

QUEUE.MIC

For

reside

modules:

string

VIELD.MIC

Cases

all

several

CONTROL.MIC

Special
The

specifier

routines

Branches

SHIFT

select

and
the

OPCODE
opcode

NEXT.
entry

output the opcode and
SHIFT IB and OPCODE NEXT instruct the IB to This
allows the Decoder tO
first specifier of the next instruction.
start decoding the next instruction while microcode processes the
current

one.

Conditional branch instructions that result in

Exception:

a branch success and unconditional branches
cause microcode to invoke a full 1IB flush.
This prevents the Decoder from decoding any IB
data until the CBox delivers the new I-stream.

Illegal One Byte Opcodes

USE OPCO ADDR is negated and DRAM bits <4:0> are encoded to a value of
5 to indicate an illegal opcode (see Table 3-19).

the DEC UADDR mux is
The negation of USE OPCO ADDR usually means that
For illegal opcodes, this
to select a specifier entry address.
implies that the Decoder will form a separate opcode entry address for

every possible specifier combination (a microcode requirement).
to immediately
All microwords addressed in this manner contain code
reserved opcodes.
transfer control to a microroutine that servicesmodule
, starts at
This routine, which resides 1in the TIANDE.MIC
entered by the GOTO
is
and
IE.FLT.RES.OPCD
label
symbolic
macroexpression:
Example:

Instruction - Any illegal opcode

— — p— —

Label

—— . - . W - .

don't

care

. WD D S R s S

Microword contents
[

—— .

gsize

Address

- RMODE, not indexed, access type and data

Specifier

———

The

IE.FLT.RES.OPCD

reserved
is

that

The

the

DRAM

value

opcode

asserted.

The

are
as

OPCO

ADDR

WAS

RMODE

SPEC

the

.REG

Opcode
FE

SHIFT

IB
that

case,
vector

(the

same

Although

from

the

into

not

only

routine
10

the

causes

MCAs)

illegal

used

The

(hex)

also

(UBRS

illegal

main

service

difference

instead

formation

ILLEGAL OPCODE

the

addressing

1C.
an

microsequencer

mode

from

illegal

but

are

treated

one

byte

opcodes,

with

specifiers:

Asserted
determines

should

SPEC

Was

the

entry

address

for

Address

Negated

3DFC

IE.ESCE.MEM

3FFC

IE.ESCE.REG

Negated

3DFE

IE.ESCF.MEM

Asserted

3FFE

IE.ESCF.REG

opcode

points

function

and

then pass

used

for

illegal

and

SHIFT

not

used;

the

(hex)

Asserted

first

reside

specifier

the

byte
are

1IB.

3-109

the

instruction.

module.
form

illegal

the

each

exception

opcode

routine

data

output

opcodes).

asserted,

exception

IANDE.MIC

microword

control

one

.MEM

Label

Asserted

OPCODE

the

generated:

RMODE

leads

instructions

one

the

SCB

but

logic

also

out

entry

only

OPCODE

the

address,

code

and

shifts

the

(IE.FLT.ILL.ADR).

Opcodes

instructions

USE

similar

distinguish

similar manner
1.

Note

microbranch

Escape

faults

vector

entry

uses
the
signal
opcode exceptions.
Reserved

mode

exception

<4:0>

illegal

These

routine

addressing

handler

the

new

routine

will

overwrite

Two

Byte

Opcodes

asserted
DRAM signals USE OPCO ADDR, SHIFT IB and OPCODE NEXT are all
(The byte is treated as
for the first byte (FD) of a two byte opcode.
if

it were a macro NOP

with

reserved

instruction.)

escape

nnhndpq
~ S A R a2

first byte of a two byte opcode

there

are
%
(A 1

two

entry

points

for

(also in the IANDE.MIC module):

Address

Label

Microword contents

3FFA
3DFA

IE.ESCD.REG
IE.ESCD.MEM

GOTO DECODER
GOTO DECODER

the

that
means
The GOTO DECCDER expression (microword bit I DECODER set)
of the microword is to request a "Dec Next" cycle
function
only
the
for the second, or true, opcode byte of the instruction.
Decoder
the
FD microword,
the
for
address
As it forms the
prepares for the second opcode byte by performing the following:

also

out

the

two

1.
2.

SHIFT IB and OPCODE NEXT instruct the IB

shift
has

PCNC MCA issues OP IS FD to indicate instruction
byte

second opcode byte and the first specifier bytes.

opcode

1IBST MCA saves OP IS FD as the signal TWO BYTE
its normal

incrementing of

and

1inhibits

the SPEC NO <2:0> bits.

The TWO BYTE signal is affixed to the DRAM
address
pointer
for
the
This enables the DRAM to
decode cycles.
subsequent,
all
and
next,
Dbyte
one
its
from
distinguish the second byte of a two byte opcode
the second byte of CVTDH is the same as the
(eg:
alike
1look
opcode
wrong
the
output
Otherwise, the DRAMs would
opcode byte of CVIWL).
BT

data

for

each

bpcuLLler.

If the second opcode byte is an illegal opcode,

DRAM

<4:0>

will

equal to 2.
This will cause the Decoder to generate the entry address
for an illegal opcode microroutine the same way it
does
for
1illegal
one

byte

opcodes.

3-110

3.4.6.4
The

Special

affect
by

Special

events

Decoder
When

Address

normal
that

interrupt,

Microaddresses

Encoder

they

the

caused

Stall.
special

condition

Disables

the

specifier

Generates
service

Address

Special

condition

lines.

Bits

ADDRESS

<3:0>

from

entry

Figure
CPU

These

current

the

detected,

Decoder

the

Special

condition

several

execution.

external

may

Refer

monitors

instruction
occur

Special

the

which

may

instruction,

outputting

point

conditions

instruction

the

opcode

3-31.

such

itself,

may

caused
as

such

Address

Encoder:

entry

address

routine.

address

for

the

on
bits

the

set,
the

level

routine

condition

required

for

Generation
addresses

<09:00>
which

are

also
forced

are

encoded

with

output

DEC
<13:10>

present,

the

DEC UADDR <13:00>

13121110

|09 0807 06 0504 03 020100

SPECIAL
ADDRESS

<3:0>
A

Encoded level of
———— highest priority
condition present
MKV86-1134

Figure

3-30

Special

Microaddress

3-111

Format

UADDR
receive
highest

<13:00>
SPECIAL
priority

SHIFT 1B A

IBC DEC NODP DR PE
SPECIAL ADDR ENBL

SEL_SPECIAL ADDR

ANY INSTR

0
HP

INT_PENDING

PRIORITY

TP SET | encoDer

FPD_SET

SPECIAL ADDR DECODE <210

SPECIAL

ADDR <31)

1B PE <O

IB PE <>

MEMORY BROKEN
1B PAGE_CROSS

iB T8 MISS| redoen
IB_ACV

USE DPCO ADDR

TRUE H

SEL SPECIAL_ADDR

IB DATA

STATUS <10> | A
T
!
c

IB TB MISS

BATA
S
STATU

IB
DECODE |ACV
WP

1] 0 | Status

|
HALT
—

TB MISS
0/
LY
HER0|IB

l N

1| 0 | Don’t Core

11 1 | Data Vaud
HALT

PENDING

A _l

MUX

SEL

l’

DECADDR NEW INSTR
MKV86-1303

ju—

Special Address Encoder Logic

Figure 3-31

Special
The

Condition

Special

event

Address

classes

Event

and

Classes

Encoder

services

categorizes

each

Class

External

When
current

the

current

decode

condition

boundary

event

3-23

ADDRESS

<3:0>

cycle

takes

lists

class,

Serviced

into

two

times:

Example
Interrupt

decode

cycle

special

Table

conditions

defined

boundaries

instruction

special

Instruction

instruction
Caused

class

the

relative
field

1is

coincides

with

pending

1in

precedence

and

special
and

the

DEC

3-113

instruction

event

selected

also

UADDR

condition,

each

conditions

priority.

Decoder

Stall

the

decode

class

shows

<13:00>

boundary

class,
the

and,

the

and

instruction
cycle.

within

encoded

generated

each

SPECIAL

for

each

Table

3-23

Conditions
Condition

Special Microaddress

Serviced

Priority

Conditions

Instruction

Boundaries

Special ADDR

DEC

<3:0>

Not used
Not

Highest

used

Halt

Pending

Interrupt

Pending

UADDR

<13:0>

0001

07FF

0011

OFFF

0101

17FF

0111

1FFF

Trace

Pending

1001

27FF

First

Part

1011

2FFF

1101

37FF

1111

3FFF

Done

Reserved

(Note

Reserved

(Note

Conditions
Condition

Lowest

Serviced on
Priority

<0>

(Note

<K1>

(Note

Memory

Page

ACV

Highest

Broken

Cross

Miss

Not

used

Stall

(Note

Lowest

Decode

Special

ADDR

Cycle
Decoder

UADDR

<3:0>

<13:0>

0000

03FF

0010

OBFF

0100

13FF

0110

1BFF

1000

23FF

1010

2BFF

1100

33FF

1110

3BFF

NOTES

Special

Address

<3:0>

1101

Conflicts

with

User

1111

Conflicts

with

Opcode

Refer

Parity

error,

lower

word

longword

error,

upper

word

longword

both

<0>

Although

PEs'
is

the

assigned

since

Table

the

names

address,

generates

time

are

indicated

This

signal

determine

3BFF,
the

Address

(double

error),

address

entry

the
is

address

allowed

address

OPC

times
of

and

OPC+TPC

SPECIAL

the

ADDR

control

Selection
by

is
when

the

ENBL

the

signal

issued

under

new

DLY

FLUSH

DEC

STALL

DEC

NOOP

NEW

FLUSH

OPCODE

one

additional

1issued

instruction

boundary

SPECIAL

ADDR

the

conditions

same

instruction

the

ENBL
read

BYTE

VvI

3-115

Pointer"
few

same
IBST

SPECIAL

asserted.

from being

opcode.

the

(internal

imposed
1is

With

correspond

exceptions,

even

same:

(actually

OPCODE

condition

"New

issued.

are

condition
TWO

column

signals

Signal Used
by IBST MCA

NEW

3BFF.

3-18.

Signal Listed
in Table 3-18

same

IB.

the

byte

MCA

the

specifiers,

Special

MCA.

PCNC

Stall
to

specifier

1IBST

the

occur

reported.

range

entries

There

space

Parity

cannot

space

<0>

The

store
point

boundaries

the

entry

1111:

the
by

control

Instruction

from

1101

Boundary

used

equal

Instruction

from

cannot

signaled

signal)
MCA

signal)

ADDR
This

twice

ENBL:

prevents

for

two

IB Decode Special Address Selection

the signals SHIFT IB from the
These special conditions are sensed when MCA
asserted. This means
DRAM and IB DEC NOOP OR PE from the PCNC al are
ss if the IB either
that the encoder will only generate a specint addre
data
does not contain enough data for the curre decode cycle or the
is flagged with an error of some sort.

tions are serviced during
The next table describes which special condiinstr
uction boundaries.
1B decode cycles that do not coincide with
Table 3-24
Condition

IB PE
<1:0>

Special Conditions Serviced During IB Decode Cycles

Meaning

good
CBox sent a longword on the CACHE DATA BUS with
the
when
y
parit
bad
d
sense
e
parity but the DEC modul
reported
data entered the IB.

The parity

in the next decode cycle.

IB PEs only

indicate

error

that some 1B longword received

bad parity, not which one.

Therefore, the

error may

or may not be related to the next IB longword read.

IB PEs are indications of problems with the CACHE
DATA BUS or with the IBUF MCAs. This is because the

CBox asserts MEMORY BROKE when 1t senses bad parity
on data read from cache or from the NMI, Since the
assertion of this signal prevents data from entering
the IB, no IB PE would be reported.

IB Memory
Broken

CBox detected an error in the cache/memory subsystem
(TB, cache, NMI, etc.) and was unable to prefetch the
next longword of the I-stream.

A longword is sent to, but not loaded in, the IB (see
the entry for IB PE <1:0> above).

Table

3-24

Special
IB

Condition

Meaning

CBox

Page

Cross

detected

the

The

longword

PIBA

longword

the

CBox

the

I-stream.

The

tagged

the

first

ACV

fetch

The

last

Access

ACVs

Stall

are
the

may

fault

Not

enough

Special

"page

cross"

with

legal
and

common,

may

not

data

special

address

the

address

for

instruct

with

PTE

and

page

faults,

management

service

request

miss.

the

routine
miss.

resulted

(ACV).

fatal.

for

current

Microcode

appropriate
decode

generates

whose

encoder

the

determines

action.

cycle.

address

only

function

will

continually

0S.IB.STALL microword
required data.

not
will

prefetching

for
to

request.

The

the

so,

overwritten

non-fatal

takes

decode

resulted

memory

and

encoder

prefetch

issue

delivers

usually

Violation

and,

usually

microcode

page.

request

enter

microword

CBox

new

The

with

Instruction

continue

location

the

appropriate

address

I-stream.

PIBA

O5.IB.STALL

new

fetching

"tagged"

Physical

cross
a

while

CBox.)

severity
IB

but

the

I-stream

the

will

Control

the

prefetch

microcode

crossing

the

longword

I-stream

TB misses

current

During

I-stream.

longword

Miss

The

the

(PIBA

form

Serviced

(Cont)

boundary

loaded

page

the

Last

tagged

Cycles

page

CROSS.

Address

check

longword

PAGE

Buffer

Conditions

Decode

3-117

again

generate

until

the

NOTE

IB PE

<1:0>

hardware

and

problems

MEMORY

BROKE

are

indications

and are reported to the IBox Error

the
saved along with
The IBER is
Register (IBER).
(EBER and CBER) and
EBox and CBox error registers
VLllo Lo

other

relevant
LT LT vAalIL

data
ulati

(PSL,
\ L wridy§

Guide

(EK-KA88H-UG).

PC,

etc,)
o

microcode

structure known as the Machine Check Error Bank.
data
Interpretation
Refer to the VAX 8800 Machine Check

Decoding - The
3.4.6.5 IBST MCA Signals Related To Instruction
either not
were
which
signals
MCA
IBST
those
describes
text
following
explanation.
additional
need
or
sections
preceding
covered in
SPEC

<2:0>

Function:

Form the upper three read address inputs to the Decoder RAMs

Indicate which specifier of instruction is

processed

next.

Operation:

They are
SPEC NO <2:0> are cleared at the start of every instruction.
and
asserted
are
IB
SHIFT
and
SELECT
DEC
when
incremented by one
then
0
to
equal
be
will
bits
the
that
means
This
IB DEC NOOP is negated.
forth,
so
and
cycle,
second
in
1
in the first specifier decode cycle,
Exception:

The bits are not incremented in subsequent cycles
the
of indexed or big immediate specifiers or in
first cycle of

a two byte opcode.

SPEC
When the opcode cycle of an instruction is to be performed,
instruction.
the
in
operands
of
<2:0> usually reflect the number

Since the bits are cleared at the start of an instruction, this means
they will point to a DRAM location for a specifier that does not
that
1In this case, the selected DRAM location is not encoded with
exist.
but with data necessary to generate and select the
specifier data,
entry point address for the opcode routine.

3-118

For

example,

cycle
A

value

that

an
of

the

for

DRAM

operand.

SPEC

ADDL2

will

Exception:

instruction

with

selected

the

since

last

(ACBx,

SPEC

TYPE

value

contain

The

<2:0>

word

However,

selected

will

equal

instruction.

ADDL2

the

only

data

has

required

specifier

AOBLEQ,

etc.)

two
by

cycle,

the

SPEC

<2:0>

one

used

the

does

data

the

mean

the

third

DRAM

word

cycle.

instruction

branch

offset.

not

have

its

own

value

for

the

specifier

opcode

would

for

the

opcode

control

operands

operands,
the

always

this

specifier

containing

loop

Since
the

three

one

decode

cycle.

<3:0>

Function:
®

Encoded

represent

the

current

specifier

type

(literal,

etc.).

Become

DEC

UADDR

Figure

3-28

and

<8:4>

Table

operand

entry

point

address

(see

3-19.

Operation:
The

SPEC

byte,

The

TYPE

<3:0>

<7:0>,

exception

which

first

this

case,

processed

easily

and

mistake

are

the

IB.

this

specifiers

byte

bits

from

during

<7:0>

subsequent

the

IBST

the

normally

first

byte

specifier.

(Table

the

3-119

current

cycles

represent

remember

size

additional

not

longword

MCA must

data

the

does

based

specifier

big

specifier

immediate
but

the

3-14).

that

big

operand.

subsequent

immediate

Otherwise,

longword

being
could

new

When it first decodes the

and

byte

<7:0>

that

determines

current specifier is immediate mode, the IBST MCA:

the

Encodes the SPEC TYPE <3:0> bits with a value of C (hex)

always
mode

the

case

specifiers

the

first

cycle

decode

(Table

Gates the SPEC TYPE value just generated with DRAM bits

DATA SIZE

IBST

<2:0>

IBST DATA SIZE <2:0> represent the data size of the current operand
and are sent to the IBST MCA the same time the entry point address for
the first longword is being

formed.

toc

affect

the

When IBST DATA SIZE <2:0> equal 4, 6 or 7, indicating the

operand

for

the

Although the IBST DATA SIZE <2:0> bits arrive to late

SPEC TYPE value in the first cycle, the IBST MCA uses them to generate
the value for the next, and each subsequent, cycle.

bigger than a longword (Table 3-20), the IBST MCA will:
3.

1Issue SEQ LW to the PCNC MCA

Inhibit incrementing SPEC NO <2:0>

Encode SPEC TYPE <3:0> with the

next decode cycle

(Table 3-20)

value

appropriate

The IBST MCA performs steps 3 to 5 once for D-float, G-float and for
Quadword big immediates and three times for H-float and Octaword. 1In
either case, normal specifier decoding resumes after the last longword
is

processed.

DLY OPN

XOR

IBS

This signal is the logical "XOR" of the DRAM signals OPCODE
SHIFT

and

1B.

DLY OPN XOR IBS is sent along with the other DRAM outputs to discrete
parity checking 1logic on the DEC module. If bad parity is sensed in
This
the DRAM, the parity check logic will issue the signal DRAM PE.
signal is latched in the IBox Error Register (IBER) and is sent to the
microtrap logic on the SEQ module.

3.4.6.6
Decoder RAM (DRAM) - The 4K x 17 bit DRAM serves
a
look-up
table
of
opcode
and
operand
specifier
microaddresses.
The DRAM is loaded by
the
VAX
Console
system initialization sequence.

basically as
entry
point
during
the

There is one DRAM word for every specifier of an
for
the
opcode.
In
addition,
a
DRAM
word
illegal one byte and two byte opcode.

instruction
is allocated

Exceptions

for

DRAM

There

no corresponding

Opcode

Branch

specifier of

Read

an optimized

DRAM word

the:

instruction

branch class

instruction

Address

The DRAM is indexed by an 11 bit read address which
is
three
fields.
The following figure shows the address
MY

UL
L

nf
X

and
one
to every

ocarh
At

fi1a21A4
i
AN
L4
0

DECODER ADDR <11:00 >

|08 07 06 05 04 03 02 01

SPEC NO

T B
WY
T
o

OPCODE <7:0>

<2:0>

E
\

‘ <—MCA
IBST

|
-t

IBUF MCAs

IBST MCA
MKV86-1133

Figure

3-32

Decoder

RAM

3-121

Read

Address

Format

comprised
format and

of
the

DECODER ADDR A <11:00>
There are six copies of the DRAM read address:
of the read address
loading
This reduces
DECODER ADDR F <11:00>.
to
which are required
bits
DRAM
certain
of
lines and speeds the selection
early

the

decode

cycle.

Copies A, B, and D each feed a single DRAM chip.
feed

seven

Copies E and F

each

~Im
A o

chips.

which are
<8:4>,
bits
Instead,
Copy C does not address the DRAM.
Bits
mux.
UADDR
DEC
the
to
equal to OPCODE <7:3>, are sent directly
<8:1> are sent to the "visibility bus" as VBUS OPCODE <7:0>.

DRAM Output

Signals

Figure 3-33 shows the 17 DRAM output bits and the signal name assigned

',._J

Table 3-25 briefly describes each signal.

to each bit.

DRAM OUTPUT SIGNALS

|15 | 14

10,09

08 07]
A

SHIFT IB

06 | 05
A

|04:0302|01

fi\

A ——

DPAR2
EXTRA BIT
SHIFT IBB

USE OPCO ADDR

MD NUM <2:0>
PRED DATA SIZE <1:0>

OPCODE NEXT

OPERAND DATA SIZE <2:0>
ACCESS TYPE <1:0>
MKV86-1139

Figure

3-33

Decoder

RAM

3-123

Output

Signals

Table

DRAM

3-25

Decoder RAM Output Signal Descriptions

Signal

Description

SHIFT

Gated with IB STALL OR PE (originally IB DEC

NOOP OR PE from PCNC MCA).

Forces Special Address

Encoder

to check for

special conditions when IB is shifted.

DPAR2

DRAM parity bit (odd parity)

When a DRAM word has bad parity, the signal
DRAM PE is asserted. This signal is recorded
in bit 5 of the 1IBox Error Register (IBER)
and is reported to the microtrap logic as
machine check condition bit IBox MC COND <0>.

EXTRA
BIT

SHIFT
IB

USE

OPCO

Allows IBFO MCA to distinguish between byte
and word size offsets and between different
data types of 32, 64 and 128 bit operands.

Signals PCNC MCA and IBST MCA when next block
of I-stream data is to be shifted out of IB.
L
~ A3

Forces DEC UADDR <13:00> mux to select opcode

entry address for current instruction.

ADDR
ATV

A1SO

oA~

see

erncry

OPCODE
s

3-124

—

NEXT,

Table

3-25

Decoder

RAM

Output

Signal

Descriptions

(Cont)

DRAM

Signal

Description

Specifies
which
EBox
Memory
Data Register
(MDR)
1is to receive data for
specifiers that

NUM

<2:0>

request

data

from

A maximum of
instruction,
Encoding

from

VAX

6 MDRs can
be
assigned
one per specifier.
NUMs

microroutines
MD[MDNUM],

memory

the

refer

instead

DRAM

Specifies

data

size

DATA

immediate

mode

specifiers

for

SIZE

through

specifier

branch
that

specifier

implicitly

explicitly

PRED

sixth

allows

to MDRs

GPR.

MD[MDO].

offsets
occupy

and

second

positions,

<1:0>

Bits

are

output

indicate

data

Bits

are

latched

PCNC

MCA

Allows

PCNC

size

MCA

current

IBST

MCA and

current

Asserted

SLOW

offset

BRANCH

ACBB,

if
a

next
PC

control

AOBLEQ,...

etc.)

3-125

but

presented

will

cycle.

appropriate

specifier

loop

cycle

specifier

generate

increment amount for next
for next decode cycle.

RAM

decode

operand.

time

the

branch

instruction

(eg:

Table

Decoder RAM Output Signal Descriptions

3-25

(Cont)

DRAM

Signal

Description

OPCODE

Asserted

first

&
the

one

new

‘cycle will

uecod

the

instru

The OPCODE NEXT and USE OPCO ADDR signals are
of
cycle
both asserted in the opcode decode
an instruction but are used during
different
canonical
USE

times:

OPCO ADDR

Used by DEC UADDR muxes
during T2 so that
the opcode entry address will be available
to the micro-PC address latches by T3.
e

OPCODE

Latched

PCNC and

IBST MCAs

during

T3.

PCNC MCA uses the signal to establish
IB pointer for the next decode cycle.

the

NEW
IBST MCA uses the signal to generate
OPCODE which forces IB
to
output opcode

and

first

sserting

the

specifier of

both

Decoder to

signals

decode

[w)]

one.

)

current

the

instruction.

simultanecusly

the

while microcode processes
of

the

allcws

instruction

execute

code

Table

3-25

Decoder

RAM

Output

have

dual

Signal

Descriptions

DRAM

Signal

Description

OPERAND

These

bits

functionality:

DATA

SIZE

Specifier

cycle

Represent

current

<2:0>

ACCESS

Opcode

operand

Bits

<1:0>

opcode

<2>

bits

size

cycle

Bit

These

data

also

have

<1:0>

dual

functionality:

TYPE

<1:0>

Specifier

cycle

Represent

current

Opcode

operand

access

cycle

Bit

<1>

opcode

Bit

<0>

one

byte

opcode

two

byte

opcode

bit

3-127

<0>

mode

(Cont)

Optimized

3.4.7

Instructions

Optimized instructions incorporate the execute code and last specifier
routine
1into
a
single
microroutine
to yield a one cycle saving in
instruction execution

instructions

Optimized

time.

fall

into two general classes:

Simple moves - MOVAx, MOVL, MOVZBL and MOVZWL
Simple branches - BEQ, BNEQ, BRB, BRW, etc.

1.
2.

not
do
instructions
Simple Move Instructions - Simple move
3.4.7.1
the
on
performed
is
operation
no
since
code
execute
require
destination operand, which is of the WRITE LONG AND SET CC's type (see
When the last specifier routine issues the I DECODER bit,
Table 3-20.

the Decoder will output the entry address for the first
the

current

instead

instruction

one,

Although the simple move

are

specifier

opcode entry address for the

the

instructions exclude the opcode cycle,

there

some specifier addressing modes which defeat the one cycle saving

execution

time.

Examples:

Reason for Lost Optimization

Instruction
MOVL

(RO),

MOVL RO,

RI1

04(R1)

Cache latency fetching first operand
"optimized"

code

to wait

Not enough data ports
the

write

operation

an extra

in the
one

forces

cycle.

EBox to perform

cycle.

NOTE

The MOVZBL and MOVZIWL instructions
both
zero
extend
the
source
operand
1in
the routine that handles the
operand.
Except as noted above, this is done
without
a

performance

penalty.

3.4.7.2

Simple

Branch

execute

microword
specifier.

Instead,

address

the

The

for

execute

and

encodes

the

- These instructions only take one
there is no decode cycle for the branch
Decoder will
immediately
output
the
entry

since

execute

code

sending

Instructions

code.

responsible

the

EBox

microbranch

for

the

condition

sign

extending

Data

Bus.

for

the

recipe

the

The

branch

execute

offset

code

also

microsequencer

NOTE

Loop

control

exclude

not

the

instructions

branch

considered

(ACBx,

specifier

optimized

AOBLEQ,

cycle.

since

etc.)

However,

they

require

clock

also

they

are

additional

cycles to calculate the new index, generate
condition code bits and test the branch condition.

3.5

MACROBRANCH INSTRUCTIONS
instructions are part of

Branch

potentially

include

subroutine

procedure

The

the

3.5.1

Nautilus

Branch
the

VAX

the

this

new

(BSBx,

JSB,

RSB),

RET)

the

1instructions

that

instructions

case

basic

control

Refer

Microcode

Control"

(CASEx)

and

hardware/

instructions

the

microcode

Interpretation

executed.

all

1Initialize

Generate

the

Initiate

the

(flush)

updated

Guide

Since

the

offset,

that

the

there

microcode

using

listings

(EK-KA88E-UG)

that

the

branch

prefetch

operation

the

above

fetched

will

start

the

branch

from

processing

routine

resultant

will

not

way

branch

change

contain

the

predict

instructions

offset

Cache

1is

for

with

branch,

the

service

physical

instruction

the
and

unconditionally:

new

successful

bit

branch

means

microroutines

conditionally,

Sum

logic

usually

advance,
code

the

Basics

flow

also

instructions.

present

examples.

modified

decode

group

"PC

servicing

Instruction
PC

I-stream

microword
microword
On

section

larger

These

(CALLx,

with

8800

instruction

contain

this

involved

PC.

information.

When

VAX

control

instructions

VAX

the

call/return

intent

concepts
branch

modify

the

operations

Cache
the

and

new

requests

are

carried

delivered

instruction

"Dec

Next"

out

the

when

cycle

and

the

IB.

The

the

last

(I_DECODER

set),

unsuccessful

instruction

branch,

the

above

operations

executed.

3-129

are

inhibited

and

the

Branch Instruction Classes

3.5.2

There are,

in general, three branch instruction classes:
BRW, JMP, etc.

Unconditional branches - BRB,

Short conditional branches - BEQL,

BNEQ,

Long conditional branches - ACBB,

AOBLEQ,

3.5.3

etc.

BBC, etc.

Unconditional Branches

An unconditional branch only requires a single microword to execute.
However, due to the time required to generate a new physical PC and to
fetch new I-stream from Cache, there is always a delay before the next
instruction

is delivered to the

1IB.

the
During the delay incurred fetching new I-stream data from Cache,
This
.
microwords
"Noop"
of
series
a
with
"padded"
be
must
pipeline
prevents the microsequencer from selecting the Decoder as the source
of the next microaddress until the new instruction enters the IB.
Otherwise,

the wrong instruction would be executed next.

Figure 3-34 shows the pipeline state during the execution of a BRB
(The reason for showing six microwords will be addressed
instruction.
in

the

text).

Table 3-26 lists the

symbolic

1labels,

micro-orders

and

operations

performed by the BRB execute code.

NOTE

All branch instructions have two

execute

code

entry

last specifier of the previocus
the
if
one
points:
it was
if
and one
mode,
register
was
n
instructio
last
the
that
assumes
example
This
memory mode.
specifier was memory mode.

3-130

CTL. BRB.MEM:

PC&VA--A[PC}+B{IB)], FLUSH IB, GOTO[CTL.NOP)

r— T
Decoder | Decoder
=g
I Cycl
I
|
e

Generate

ot
1| Serond
harr
Half

Lookup

e e

File Writes

ALU Operations

CcSs2

Lookup

CTL.NOP:

NOP

| Decoder :
Cycle

Decoder
Cycle

Half

:
|

First

Generate

Lookup

to deliver new

Reads

cs1

cs2

Lookup

e -

CTL.NOP.3:

Wait for CBOXJ

File

Uneg;
-addr

Cso

| Second

Generate

Cycle

CcSo

First

Second

Lookup

Har

Cach

Operations

|Operations

ache

NOP

: Decoder | Decoder
I

File Writes

ALU Operations

rTTTTTT T

|-stream data

Cache

Operations {Operations

e —

[

IE€T-¢

Cs1

I
i

File

cso | Uaddr | Reads

Half

RZ:ZS

6323

CTL.NOP.2:

i
\

ALU Operations

CS2

Lookup

e ——

File Writes

U-addr

Cache

Operations |Operations

NOP

Generate

Decoder | Decoder

(li}lr(;lf
|] S%zglr?d
Half
Half

L(‘?cfi(?:p

Fite

Uneg;

Reads

Cs1

CSs2

-addr

Lookup

ALU Operations

Lookup

File Writes
B

Cache

Operations

[Operations

|SR ——

CTL.NOP.1:
First
1
d
of
irst longword
of new

r
|

I-stream should be in IB, ]

start decoder,

Decoder
Cycle

NOP, END INSTRUCTION

Generate

I
|

Decoder
Cycle

cso

First

Second

Hait

Looku

T
|

next
U-addr

cs1
Loockup

File
Reads

cs2

Decoder

(l::?/rble

Cycle

Branch target|
]

]
|

st
Half

|
|

Second
.
Half

Lookup

r—___| —————

| Decoder |

Fle Wittes

ALU Operations
Operations

Generate
Uneszi

CSO_

Lookup

3-34

Pipeline

State

for

Ccs1
Lookup

BRB

Fie

Reads
r

First microword of new instruction or
0S.1B.STALL microword if cache read miss.

Figure

Cache
|Operations

Instruction

CSs2
Lookup

File Wnites

ALU Operations

Cache

Operations

|Operations

Table

3-26

Execute Code For A BRB Instruction

Microword

Micro-order

Function

CTL.BRB.MEM

PC & VA <- A[PC] + BI[IB]

Add sign extended branch
offset

(IB DATA BUS)

updated PC,

store sum in

PC and VA registers.

virtual PC to
Translate
physical PC and prefetch
new

I-stream data.

FLUSH IB

Unconditional IB Flush

GOTO [CTL.NOP]

Enter No-op routine

CTL.NOP
CTL.NOP. 3
CTL.NOP. 2

NOP
NOP
NOP

Pad pipeline
Pad pipeline
Pad pipeline

CTL.NOP.1

NOP, END INSTRUCTION

Issue "Decoder Next".

3-132

The

first

microword

of the BRB code performs the actual
work
The
next three microwords "pad" the pipeline,
CBox to fetch and deliver the first longword of

instruction.
time for the
I-stream

The

macro

the

microword

muxes

The

timing

the

sixth

the

INSTRUCTION

I DECODER
Decoder

1is
the

the

fifth

microword

force

the

source

the

microword
or

between

assertion

to
the

executed

"Decoder

the

will

Stall"

arrival

I DECODER

the

new

indicates

micro-PC

address

microaddress.

first

1longword

determines

whether

the

first

microword

the

new

time

3-27 lists the events that occur during
CTL.BRB.MEM microword starting with T8.

3-133

the

bit

micro-word,

Table
the

set

the

Timing

relationship

and

instruction

END

bit

select

Cache/Decoder

the

1IB.

expression

that

allowing

0S.IB.STALL.

each

canonical

Table 3-27

Time

Microword CTL.BRB.MEM Event Timing
Event

EBox outputs new virtual PC to CBox

T ransia ti on
3

Buffer

\ LT) e
(TB)

T8 - T9

TB generates new physical PC.

T9 - T10

Cache read operation requested.

T10

Cache outputs first longword of new

T11

First longword stored in IB.

T12

Decoder generates entry address for

T13

Entry address latched in micro-PC

I-stream

1IB.

first specifier of new instruction,.

address

latches.

Canonical

T11,

T12,

T3,

and

TS5

T4,

times

that

the

Read

Latched

Presented

the

CBox
to

the

can

The

the

CS0

the

T12

cannot

data

micro-PC

the

first

have

address

IB.

the

entry

Once

this

address

ready

for

with

canonical

always

the

CBox

Decoder

first

the

Decoder
of

micro-PC

will

the

new

address

time,

the

address

generates

address,

the

address

output

delivers

will

specifier

the

specifier

output

and

continually

the

T11,

first

longword

Decoder

will

until

the

first

the

data).

happens,
for

these

muxes

longword

Decoder

Encoder

microword

correspond

is during

latches

for

the

(the

wrong

Address

OS.IB.STALL

the

address

disable

microword

based

Special

deliver

will

CTL.BRB.MEM

is:

RAM

entry

and

CTL.NOP.1l.

RAM

CS0

deliver

Encoder

OS.IB.STALL

relative
to

T13,

CBox

Address

from

generate

instruction
muxes

T13

I DECODER bit

able

and

relative

the

resume
the

first

the
even

the

longword

control

new

Special

and

supply

instruction.

3.5.4

Short Conditional Branches
conditional branches (BEQL, BNEQ, etc.)
are to only perform
branch function if a certain condition
is true.
The execute codes
these instructions are similar in struc
ture in that they all test
Short

PSL.

The

condition

only

difference

example,

while

Branch

The

BEQL

BNEQ will

execute

Table

the

PSL

determine

branch

condition

instruction

microwords
code

field.

I MISC

bit(s)

bits

the

will

bit

the

code

branch

bit(s)
if

the

should

under
PSL

test.

<Z>

bit

clear.

the

taken.

For
is

set

Recipes

condition
I_MISC

code

the
for

3-28

bit(s)
The

<6:0>
lists

under

test

short

under

branch

recipe

010xxxx

the

I_MISC

for

all

conditional

test

field

by
is

branches

encoding
of

the

settings

macrobranch

VI 3-135

specify

the

"branch

recipe"

PSL

condition

PSL
the

form:

and

instructions.

code

Table 3-28

I MISC Field Settings For Macrobranch Recipes

I _MISC

Instruction

Take Branch If

20
21

BGRT
BLEQ, SOBGTR

PSL <N OR 2> = 0
PSL <N OR Z2> =1

28
29
2A
2B

BGTRU
BLEQU
BCC
BCS

PSL.
PSL
PSL
PSL

22
23
24
25
26
27

2D
2E
2F

BGEQ
BLSS, SOBGEQ
BNEQ
BEQL
BVC
BVS

PSL
PSL
PSL
PSL
PSL
PSL

= 0
=1
= 0
=1
= 0
=1

<C OR Z> = 0
<C OR 2> = 1
<KC> = 0
KC> =1

AOBLE(Q, ACBx

WBUS <N> XOR ALU V> =1

BBx, BBxx

WBUS 2> =1

AOBLSS
BRX,

BSxX

( (WBUS <KN> XOR ALU <V>) OR WBUS KZ2>) =1

UNCONDITIONAL

Note:

The I _MISC field 1is monitored by the CCBR MCA.
'

W
N

(O8]

fmd

Figure 3-37.

Refer to

Short

Conditional

Branch

Execute

Code

Short conditional branches, like
executed
by a single microword.

the unconditional branches, are
The execute code for a BEQL is
below.
Except for the PSL condition code bit(s) under test, the
for other short conditional branches are similar in structure.

The

Microword

Micro-Orders

CTL.BEQL.REG

COND.PC

LOAD

FLUSH

CTL.BEQL.MEM

END

first micro-order

A[PC]
IB

also
shown
codes

BI[IB],

IF[PSLKZ>.EQ.1],

INSTRUCTION

stipulates

conditionally

load

the

and

registers
in
the
EBox
with the sum of the up-dated PC and the sign
extended branch displacement.
If the branch is successful, the new PC
is
then
to be routed from the EBox, over the VA BUS, and loaded into
the

latch

The

second micro-order

only

the

The

third

set

the

PSL

CBox.

<Z>

micro-order

end

the

Conditionally

specifies

bit

set;

indicates

instruction

the

and

load

the

otherwise,
that

the

request

and

new

and

I _DECODER

flush

the

1IB

microword

bit

1is

nothing.

decoder

registers

cycle.

effectively

guess

that
will

the
load

branch will succeed.
If the branch
the new PC in the VA latch, form the

is successful, the CBox
physical PC, and
fetch

the

new

I-stream data.

the

signal
the

COND BR

new

Pipeline
Note

that

CTL.NOP

the

Timing
the

request

(see

the

Figure

branch
3-37)

fails,

inhibit

IBox will

the

CBox

issue

from

the

latch.

Consideration

execute

routine

unconditional
bit

FAIL

code

"pad"

branch.

Since

the

Decoder

from

when

the

decode

not

decoding

I DECODER

bit

conditional

pipeline

1Instead,

another

stop

for
the

the

immediately

does

not

execute

asserts

call

code

the

for

I DECODER

cycle.

under microcode
the

branch

does

I-stream

set,

the

is
the correct entry address for
processed to the micro-PC address

control,

data

Decoder

the next
latches.

3-137

the

will

there
IB.

supply

specifier

way

This

means

what

(or

opcode)

to
that

thinks

I-stream flow and the
If the branch fails, there is no change to the execu
ted (assuming Cache
IB should contain the next instruction to be
generate the next
ore
theref
will
r
hits on the I-stream). The Decode
in the IB. 1In this
dy
alrea
data
eam
address based on the correct I-str
case, the branch instruction effectively becomes a NOP.

I-stream flow
On a branch success, however, there is a change to tothebe execut
ed. The
ction
instru
next
and the IB will not contain the
current
1IB's
the
on
based
always
is
Decoder generated address, which
contents, will therefore be based on the wrong next instruction.

the I MISC field
The timing relationship between the I_DECODER bit sandwhen
a conditional
happen
what
to
of a microword 1is the key factor
branch results in a branch success.

Refer to microword CTL.BEQL.REG shown at the top of Figure 3-35.

while the
The I_DECODER bit is available at T5 time of CTL.BEQL.REG that
before
means
This
time.
I MISC field 1is not available until T8
the
taken,
be
should
branch
a
the I MISC field can determine whether
Decoder will have already:

Decoded the next block of I-stream data currently in the IB

Generated the address of microword "g"

Sent the address to the micro-PC address muxes

will have
Also, by the time I MISC is actually used, microwordhave"U"genera
ted the
will
generated the address for microword "V" which
address for microword "W".

to the point
Therefore, before the CTL.BEQL.REG microword progresses ous
microwords
where it «can test the branch condition, three errone
will already be in various stages of execution.
Conditional Branch Microtrap

the time the
Since microwords "U", "V" and "W" are already started tby the
microwords
branch condition 1is tested, the hardware must inhibi
s. If
succes
branch
from performing their normal write operations on a
n
contai
may
n
writte
this is not done, the register or memory location

w
o

'.. el

the wrong data for the next instruction to be executed.

The

IBox

generating

case

hardware

with

all

inhibits

the

microtraps,

GLOBAL

UTRAP

inhibit

the

writes

SUCCESS

The

COND

routine

address

The

trap
the

only

and

the
the

BLOCK

the

causes

WRITES

microwords

"COND

logic

condition

The

the

CTL.TRAP.COND.BR

CLEAR

Note

that

the

1IB
to

these

since
and

the

that
as

the

issue

"wW"

the

signals

single

This

vector

Figure

3-35.

cycle.

word

the

release

the

The

code

for

and
the

flushed
trap are

not

perform

TRAP,

INSTRUCTION

CTL.BEQL.REG microword loaded the PC
three microwords in the "shadow" of

would

and

WRITES

the

restarted,

functions

CTL.TRAP.COND.BR microword

to request another "Decoder Next"
CTL.TRAP.COND.BR microword is given below,

Micro-Orders

logic

BLOCK

handled

and

Microword

"v"

elements.

vector of 0200 (hex).
CTL.TRAP.COND,BR microword shown in
of

"uU",

SUCCESS".

the microtrap

signals.

appropriate

microtrap

condition

this

END

not

writes

microtrap

function

silos

the

microtrap

CTL.TRAP.COND.BR microword

other

microtrap

3-139

service

need

routines.

)

CTL.BEOQL.REG: COND PC & VA- A[PC|+B[IB], LOAD PC & FLUSH IB IF |[PSL- Z -.EQ.1}, END INSTRUCTION
File
Gunerate
|

meT

| Decoder | Decoder

Cycle

First
ha

Lookup

| Second
Haif

ALU Operations

CS2

CS1

Lookup

File Writes

Reagis

U-addr

CSO

Cycle

.
B

Cache

Operauons |Operations

—
NS
[,

cTTTTS

Cycle

| Decoder
|

First
VT

Generate

Decoder

Lookup

| Second
Half
|

Lookup

T —I"
r Decoder
| Decoder
Cvele | Cycle
v
(IFirst |I Second
Half
1 Hai

cso

ALU Operat

perations

Ccs2

CSs1

Lookup

Flle W

File

Reads

U-addr

CSOo

Cycle

VWrites

Cache

Operations |Operations

ObT-€

|WS
—

i by these
Writes

microwords inhibited

Sucess
on a Branch
:
Block Writes
by the
Signals

File
Read

CS1
Lookup

CSs2
Lookup

eads

U-addr

Lookup

Generate
next

ALU Operations

Decoder | Decoder
Cycle

First

|boHalb

U-addr

Lookup

Half

Reads

Cso

Cycle

| Second

Cache
8
Operations |Operations

File

Generate

——
=

Microwords in the
branch trap

th
adow otof the
— “'Shadow’"

File Writes

peratons

cs2
Lookup

Cs1
Lookup

File Writes

ALU Operat

Cache
B
Operations {Operations

—
I
E
[,

CTL.TRAP.COND.BR: CLEAR TRAP, END INSTRUCTION
=

I
|

irst

Haif

|
1

U'j:éér

cSo

1 Décolder : Dgccnljer
trap
Condiional
yee
handler, microvector = 0200 | ch
Second
.

Generate

———————

Lookup

Half

Ccsi
Lookup

File

Reads

CSs2
Lookup

ALU Operations

Flle Writes

Cache
T8
Operations |Operations

Generate

Branch

Decoder | Decoder

destination |

%YCIE
irst

Half

]

(

SCychad
Secon
Half

CSkO

Lookup

Unegfj

-addr

CS1

Lookup

N
File
Reads
Ccs2
.

Lookup

ALU Operations

Cache .

ile Writes

Operations {Operations

First microword of the new instruction or

0S.1B.STALL microword if cache read miss.
.

Figure

3-35

Pipeline State for a Successful BEQL Instruction

MKVB6-0721

3.5.5
Long

Long

Conditional

conditional
Loop

control

Branch

Multi-way
The

execute

few

three

codes

several

low

bit

for

long

conditionals

these

"guess"

would
data

instructions
and
that
a

the

branch

"LOAD

The

first

microword

1its

FLUSH

either
save
register and

the
then
should be

PSL

Condition

Some

long

the

using

branch

current
load

the

value

new

IF[]"

guess

later

the

conditional

code

Code

such

the

to modify

taken

only

based

examine

the

microword

contains

the

encoded

Table

3-29

lists

field

value

and

enhance

temporary

the

IB.

This

cycles

that

new

I-stream

will

that

includes

expression.

Recipes

need

that

deliver

loop

the
on

PSL
the

the

control

instructions,

bits

and

new

bit

current

then

settings.

bit

settings

success/fail,

"recipe"

the

microword

branch

only

first microword

flush

wrong,

ten.

number

from

BLBC

microcode

and

proves

size

than

The

Cache

for

"optimized"

the

success.

for

setting/clearing of
field
of a microword.
CC

waiting

The

PSL

executed

code

vary

code

of a long conditional that is not
optimized
will
new PC or the branch offset in a microcode temporary
transfer control to a routine that determines if the
taken.
In this case, the last microword of the code
"LOAD PC & FLUSH IB IF[]" expression.

should

conditionals
branch

BBCCI

the

wasted

operations

branch

the

branches

example,

reduces

conditionals,

arithmetic
the

the

BLBS

CASEx

For

types:

SOBxxXx

succeed

saved

instruction

BBxxx

will

success.

the

include

save

with

branch

BLBC,

speed

branch

reloaded

must

BBxx,

unconditionally

otherwise
on

are

execution

following

conditional

while

Some

the

AOBxxx,

BBx,

branching

Code

ACBx,

bit

Optimized
long

include

microwords.

microwords

instruction

Branches

branches

the

Other

long

to determine

PSL CC bits is controlled
by
the
I MISC
Instructions that modify the CC bits include a

expression

the

various

new

perform

determine

PSL

I MISC

SETCC

bit

[]

"SETCC

expressions,

settings.

3-141

[]"

which

indicates

the

field.
the

encoded

I MISC

Sample

Execute

Refer

to Figure

Code

3-36 and Table

3-30.

whose

The AOBLEQ instruction is typical of an long conditional branch
execute

code:

the

current

Saves

Unconditionally loads the new PC and flushes the

Performs an arithmetic operation to modify the PSL CC bits.
the

Reloads the saved PC if

branch

should

IB.

have

not

been

taken.

The first microword of the AOBLEQ execute code saves the current PC in
EBox Memory Data Register (MDR 6), performs the unconditional load
an
the
at
I-stream data
PC/flush IB and requests a Cache read for new
predicted

branch

target

address.

The second microword increments the index operand by one and modifies
condition code bits according to the condition code "recipe"
PSL
the
specified by the expression SETCC

[OP6]

(see Table

3-29).

The third microword subtracts the new index value from the

1limit

returns the WBUS and ALU condition codes that result to the

and

IBox.

be
branch will
The forth microword determines if the guess that the
successful
was
correct
with the LOAD PC & FLUSH IB IF[] expression.

It also checks whether an integer overflow trap is to be taken when an
(In the case of an
integer overflow occurs and the PSL IV bit is set.
AOBLEQ instruction, an integer overflow will occur if
the
index
was
the largest positive integer before being incremented).
If

the

initial guess that the branch will be

successful

was

correct

and no integer overflow trap is to be taken, the AOBLEQ code will wait
one more cycle for Cache to deliver the new I-stream by executing
the
CTL.NOP.1
microword.
Otherwise, the IBox will force the microcode to
enter either the conditional
branch
or
the
integer
overflow
trap
handler

routine.

3-142

Table

3-29

I MISC

New

OPl=1F

Field

WBUS<K3>

Settings

New

WBUS<K2>

FROM,WBUS=1F

For

PSL

New

WBUSK1>

Condition

New

Code

WBUS<K0>

OP2=1

*WBUS<N>

*WBUS<Z>

*ALUKVY>

*ALULC>

OP3=4

*WBUS<KN>

*WBUSKZ>

OP4=3

ALULKV>

*WBUS<KN>

*WBUS<KZ>

OP5=5

*WBUSKN>

*WBUSKZ>

OP6=0

*WBUS<N>

*WBUSKZ>

*ALUKV>

QOP7=1C

*WBUSKN>

*WBUS<KZ>

XOR

AND

*WBUSKZ>

OP9=8

*WBUS<KN>

OP10=15

*WBUS<KN>

*WBUSKZ>

OP11=0D

*ALULKV>

OP12=1D

*WBUS<KZ>

OPl6=1E

carry

<- borrow

\V/

Set

\Y/

Clear

Set

*WBUSKZ>

SET.V=1A

AND

3-143

bits

WBUS

CLR.N=10

OP15=1A

from

SET.N=18

OP14=10

Set

*WBUS<KN>

OP13=18

Notes

out

not

(*ALU<KC>)

OP8=14

AND

Recipes

1IMISC Field Settings For PSL Condition

Table 3-29

Code Recipes

New N
OP17=0E

(Cont)

New Z

New V

NOT

(*WBUSKZ>)

OP18=0F

New C

Notes

NOT

(*WBUSKZ>)

0OP19=0B

*WBUSKZ>

0OP20=16

*WBUS<KN>

*WBUSKZ>

OP21=6

*WBUS<KN>

*WBUSKZ>

oP22=7

*WBUS<KN>

*WBUSKZ>

*WBUSKN>

*WBUSKZ>

*ALULKV>

(*ALUKC>)

OP24=9

*WBUS<N>

OP25=11

Clear Z

OP26=1B

Set C

0oP27=13

Clear C

Clear V

0P29=0A

*WBUSKZ>

0OP30=19

OP23=2

not

C <- borrow in

CLR.Z=11

SET.C=1B

CLR.C=13

0OP28=12
CLR.V=12

Set Z

SET.Z=19

Open recipe

OP31=17
0

0P32=0C

"xw _

*WBUSKZ>

gState of bit is size dependent.
I SIZE field of microword.

3-144

Data size given by

CTL AOBLEQ REG: PC' & VA
=

—

Decoder

(

Cycle

First

Second

Half

A[PC]1B[IB] FLUSH 1B, FIMDGJ-

——

1
|

Generate

Decoder

A[PC|.SL.[O]

File

' ¥y

U-addr

File Writes

Reads

Lookup

ALU

CS1
Lookup

[

Operations

Cs2
Lookup

TM8

Cache

Operations

[Operations

FIRNUM1}—A[RNUM
1)+ 1, SETCC [OP6], SIZE[LON
G]), SET NORETRY, CALL [CTL.AO
B.REG.COMPARE]

ll_ TTTTTTT
|

Decoder

| Cyele
Firs
bobr
|

Generate

Decoder

File

I Cycle
€so
) Seoond o] | Lookup

Reads

J addr
[T

Lookup

File Writes

ALU Operations

cs2

Lookup

Operations

Cache

|Operations

CTL.AOB.REG.COMPARE: WBUS.--B
[MDO)] - A[RNUM1|, SIZE ILONG],
RETURN [ 1}

.T
|

Decoder
Cocl

SP1-€

A
bobait
]

Generate

Decoder

| siii'fid
e

Loc(i(: P

)
I

File

next
U-addr

s
Reads

cst

cs2

Lookup

COND.PC & VA ~—A[MDS6], LOAD

]

Decoder
Cycle

First
Half

)

PC & FLUSH IB IF[N.XOR.v], CHECKVIV

Decoder
Cycle

Reads

-agar

Cs1

CTL.NOP.1:

File Writes

ALU Operations

Cs2

Lookup

, GOTO [CTL.NOP.
1]

File

U”esz’

CSso

Lookup

Half

Lookup

Decoder |

CYCIE
First
Half

|
1

Cache

Operations

|Operations

NOP, END INSTRUCTION

r—_— T
|

Cache

Operations |Operations

Generate

| Second

]

Lookup

r TTTTTTTT

File Writes

ALU Operations

i
i

Generate

Decoder

Cycle
Second

Unegtd

€so
Lookup

Half

a0
.

File
Reads
cs2

Lookup

r____l—__—

Branch Target |
Vo

)

Decoder |

(f::?rcslf
har

[

Generate

Decoder

: S(égg'r?d
Half

i
A,

Une:j(;

LC?OSk(l)J

File Writes

ALU Operations

CSs1

-addr

CS1
Lookup

Cache

Operations

[Operations

File
Reads
CS2

File Writes

ALU Operations

Lookup

~
Cache

Operations

|Operations

First microword of the new instructi
on or
OS.IB.STALL microword if cache
read miss
MKVEE-0/722

Figure

3-36

Pipeline

State

for

Successful

AOBLEQ

Instruction

3-30

Table

Execute

Code

Instruction

For A AOBLEQ

CTL.AOBLEQ.REG:
§

. o

——

i LD

D TED S

S SED

A AL SR e

Uncond

load

PC/flush

1IB.

Save

—— —
— —o
-m—————————

Increment index.
Set PSL CC bits.

F[RNUM1] <- A[RNUM1l] + 1,
SETCC [OP6], SIZE [LONG],
SET

NORETRY,

CALL

[CTL.AOB.REG.COMPARE]

CTL.AOB.REG,COMPARE:

WBUS <- B[MDO]

SIZE [LONG],
RETURN [1]

COND.PC & VA <- A[MD6],

GOTO

[CTL.NOP.1]

-t

CHECK

1V,

index

saved PC if branch
not have been taken.
Reload PC if incremented

index greater than limit.
Check for integer overflow.
On

branch

success,

need

one

more cycle due to IB flush.

The code given here is in the order in which the microwords
microwocrds
are executed, not the order in which
b o~

Lilc

listings.

the

(V]

Note:

point.

should

FLUSH IB IF[N.XOR.V],

Return

Reload

LOAD PC &

]mmmm e

caller

Return

limit

Compare

- A[RNUM1]j,

3.5.6
The

Condition

CCBR

MCA

hardware

which

images

provide

controlling
to

Sized

Branch

EBox

the

The

"raw"

longword

The

Not

Word

Longword

later

PSL

Condition

The

PSL

left

sized

where

Code

the

may

bits

from

the

WBUS

are
as

state

the

flags

available

for

dependent
condition

or
the

considered

microbranch

codes

from

the

microword.
can

SIZE

fed

the

new

represent

byte,

field

the

the
PSL

determine

conditions

they may

MISC

are

PSL

word,
current

Condition

bits,

and

macrobranch

also

tested

Note

output

when

PSL

Code

the

VAX

success/fail.

the

microbranch

conditions

with

the

NOP

MISC

the

not

value

the
CC

recipe

bits

will

other than a
required

normally

PSL

the

wused

3F).

outputs

the

EBox,

the

PSL

that

causes

recipe.

setting

field

the

the
Sized
Branch
directly set/cleared
new CCs are to be based

MISC

the

based
that

encoded with

MISC

They

microword

bits
Note

from

3-29).

CCs'.

codes

that

the

flags

derived

the

same

the

field

encoded

state

current

condition

conditions.,.
not

help

addition,

The

(Table

specified

size:

stored

unchanged
if the

raw

current

sets

the

methods

size

EBox

logic

the

"raw",

the

field

changes

from

The

Code

microword,

MISC

inhibit

maintaining

Logic

current

new

maintains

microword.

recipe.

logic

the

Condition
1in

from

the

conditions

may

they

MCAs)

data

where

addition,

encoded

one

also

Used

microbranch

logic,

some

with

Size

Byte

they

field

the

Branch

bits.

generates a set
intermediate, or

codes

(UBRS

operations.

Data

where

size

SIZE

sized

PSL

writers

I SIZE

indicates

logic,

logic

condition

microword

Logic
execution

flow.

logic

based

Branch

Logic

Branch
on

Macro

3-37.

conditions
and

the

firmware

Figure

Sized

And

macroinstruction

microcode

Refer

The

Code

supports

opcode

may

the

condition

3-147

also

the

EBox

recipe

always

produce

current macroinstruction
codes;

only

the

recipe.

the

CONDITION CODE AND
MACRO BRANCH LOGIC
- CCBR MCA -

WBUS <31> ———\

ALU NBIT <1:0>

ALU ZBIT <3:0>

ALU VBIT <2:0>
.
ALU CBIT <2:0>

SIZED

BRANCH
LOGIC

— SIZE DEP WBUS <N,Z>

| Si1ZE DEP ALU <C,V>
L SIZED NOT WBUS Z

|_SIZE <1:0>

PSL

.
.WBUS <3:0>

COND
CODE

I_MISC <6:0>

LOGIC

PSL CC <N.C.V,Z>

BLOCK WRITES

COND BR FAIL

BRANCH

UNCOND FLUSH

LOGIC

BR SUCCESS

IB FLUSH

STATE

NEW INSTR

FLAG

LOGIC

STATE FLAG <6:0>

MKV86-0692

Figure 3-37

Condition Code And Macro Branch Logic

The PSL CC bits are available to the VAX Branch-logic where
tested

determine

logic

where

they

may

macrobranch
be

tested

success/fail
microbranch

VAX

Branch

The
and

VAX Branch logic examines the sized
the
macrobranch recipe encoded in

From

The

these

inputs,

Flag

State

firmware
The state

Note

from

time

typically

the

control

the

they

are

microbranch

conditions.

VAX

Branch

signals

branch conditions, the CC bits
the I MISC field (Table 3-28).

logic

SUCC,

then

UNCOND

generates
FLUSH

and

the

appropriate

COND BR

FAIL.

Logic
Flag

logic

maintains

microcode

state

flags

which

provide

writers with more flexibility in controlling microcode flow.
flags are set/cleared as specified by the I MISC field.

Table

Logic

macrobranch

State

and

3-31

I MISC

Field

Settings

For

State

Flag

Clear

Flag

Set

Flag

Clear

Flag

Set

Flag

Clear

Flag

Set

Flag

Clear

Flag

Set

Flag

Clear

Flag

Set

Flag

Clear

Flag

Set

Flag

Clear

Flag

Set

Flag

Clear

All

change

the
but

above

table

Flags

that

may

cleared

set-up

one

the

state

individually

microroutine

and

flags

can

then

Control

(NOP)

only

group.

tested

set

The

one

flags

are

microbranch

conditions
by a latter routine.
The flags are all cleared during
first microword of every macroinstruction by the signal NEW INSTR.

3-149

the

3.6

SPECIAL REGISTER ADDRESSING

The File Address Slice (FADS) MCAs supply the addressing for the A and
They also record changes made to GPRs
B port inputs to EBox main ALU.
tast
ent operations, and provide
auto-decrem
and
ent
during auto-increm
access

to operands requiring multiple GPRs.

the slow
(RGF),
The main ALU inputs include the EBox register file
the IB
Bus,
Data
Cache
the
registers,
VA
and
PC
(SDF), the
file
data
Data

Bus,

and

the

Bypass

Bus.

RNUM2,
The FADS MCAs contain the MDNUM, RNUMI,
Refer to Figure 3-38.
logic.
control
address
write
and
read
and RLOG registers, and the file
explicitly
addresses
register
specify
The FADS MCAs allow microcode to
or implicitly through the RNUM1, RNUM2, MDNUM, or the RLOG registers.
RNUM1 And RNUM2 Registers
3.6.1
The RNUM1 and RNUM2 registers are both 4 bits wide.

The GPR number of the current specifier is available during the first
and may be used to address the
a specifier routine
microword of
register file, or be saved in the RNUM1l or RNUM2 registers.

a
first microword of
Since the GPR number is available only in the
later
by
use
for
specifier routine, it is stored in the RNUMI1 register

microwords.

This

the

allows

microprogrammers

write

generic

specifier flows without needing to remember which GPR is in use.

a
than
bigger
operands
The RNUM1 register is also used for reading
use
that
few
a
(except
all register writes
for
from GPRs,
longword
RNUM2),

and for communicating with the RLOG.

The function of the RNUM2 register is similar to RNUM1, but its use is
records the GPR number used in the first of the two
It
specialized.

write specifiers for EDIV and EMODx instructions.

3.6.2

RLOG Register

to
made
The RLOG is a six stage shift register which records changes
This enables
during autoincrement and autodecrement operations.
GPRs

the microcode to "roll

back"

the

GPRs

fault

occurs

during

macroinstruction execution,

implement GPR autoincrement/
to
required by microcode
Constants
operations are loaded in certain SDF locations when the
autodecrement
system is

restoration

initialized.

Specifier

flows

code subtracts the constants.

add

the

constants,

RLOG

For example, autoincrement

saves
and
GPR,
adds the appropriate constant (1, 2, 4, etc.) to the
When restoring
GPR number and the increment amount in the RLOG.
the
the register,
the
same
GPR address
is
wused,
but
the
value
is
subtracted.

I_APORT<5:0>
E_BPORT<2:1>
I_WRTADDR<5:0>

NEW INSTR

DECODER NEXT

i_FPSULF
EXPONENT COMPARE

SPEC GPRNUM

A SIDE READ

‘

ADDR <4:0>
[
.

B SIDE READ
ADDR <3:0>

RNUM1
>

REG

FILE

E_BPORT<3:0>

RLOG

READ
AND

FILE WRITE
ADDR<4:0>

WRITE

ADDRESS

CONTROL

BWACH AREAD
ADDR<4:0>
po

BWACH BREAD
ADDR <4:0>

RNUM2

—

REG

BWACH WRITE
ADDR <4:0>
.

—

SPEC MDNUM<2:0> | MPNUM
REG

MKV86-1263

Figure

3-38

File

Address

3-151

Slice

MCAs

modes use the RLOG
Note that only autoincrement/decrement addressing resul
t is that during
The
due to access limitation to specifier GPRs. med
first, and then the
use of the SP, the memory operation is perfor
ion fails, the
SP is changed. This ensures that if the memory operat
need to pe
not
SP change will not have taken place, and will
corrected.

ses are also
To allow quick access to large sized operands, file addres
MDNUM by 1).
and
indexed by some constants in hardware (RNUM1 by 1,2,3 be modifi
to
For a floating point operation, file addresses mayALU (floatingedpoint
effect a swap of operands on the twc ports of main
shuffle).

ter

MDNUM Regis
3.6.3
register (MDR)
The MDNUM saves the address of the EBox memory data
processing an
which 1is to receive data from the Cache Data Bus while
operand. A different MDR number is supplied by the decoder RAMs for
each specifier.

t specifier
The MDR number is a function of the opcode and n curren
ent opcodes
number and eliminates the need for agreement betwee differ
is that the
concerning the location of the specifiers. The exception
MOVL, MOVAx, MOVZBL, MOVZWL group must agree 1n order to be optimized.
The microcoders decide which specifier of which opcode goes in which
MDR.

The MDNUM value can be:

Merged into a cache read command sO that there is no need for

Substituted for the register destination field of in the
the
microword so that specifier routines can drop operands

separate routines for each MDR

right

Both uses serve to deliver operands into known MDRs

for

wuse

Dby

the

instructions execute code.

being
The MDR number is valid the entire time a specifier theis decode
r
in
jobs
two
its
of
either
for
It may be used
processed.
one
last
the
ing
includ
ord
microw
later
generated microword, and in any
of the specifier routine. It is unpredictable in the opcode routine.

3-152

3.7

INTERRUPTS

This

section

describes

the

hardware

point

Guide

(EK-KA88E-UG)

Interpretation

Interrupt

NBIs

and

fail,

Each

software

can

memory,

software

interrupt

(IPL)

the

current

greater

than

causing

the

appropriate

oftware

generated

internal

(MTPR

detailed

CPU

external

assigned
VAX

specific

The

flow,

the

CPU

1
int

Y ril

the

current

suspend

service
p

such

process,

the

current

routine

3
iority

for

nlae
levels

f or

the

IPL

are

device

Hardware

IPLs

reserved

for

priority

level

of
of

are

numbered

IPLs

devoted

are

interrupts
numbered

external

reserved

Table

3-32

that

devices

3.7.2
Refer

The

lists

devices

for

the

that

For
two

and

Figure

interrupt

hardware

IPLs for
interrupt

the

device

interrupt

and

will

identification

enter

the

17 AV

VAA

QONN

ey de ~

(e ReRVAV)

_YD Clil

these

1F.

software

entirely

use.

microsequencer

the

There

are

levels

levels.
Interrupt

(NBIs,
CPU

implemented

memory,

levels

console,

conditions

(power

etc.),
fail

and

serious

hardware interrupt
requests,
Note
the same level are listed in order of

interval

timer

interrupt

has

precedence

Servicing
3-39.

logic,

which

part

requests

and

the

INPR

generates

MCA,

monitors

five-bit

all

interrupt

code,

pending

INTR ID <4:0>, to
represent
the
level
of
the
request.
The
1identification code is tested by the
as
a
microbranch
condition,
allowing
multi-way

branching

PENDING

asserted

occur,

interrupts.

interrupt

highest

(or

interrupt

device.

o
i
t1

are

totally

internal

example,

NBI

Interrupt
to

device

faults).

the

power

ha rd ware
re.

hardware

priority.

CPU

order

process

the

IPL

such

interrupt

architecture.

macroinstruction
IPL

devices,

conditions,

have

over

from

8800
Microcode
1information
on
how

SIRR).

the

interrupt

IPLs

are

mechanism

VAX

interrupts.

must

These

priority

microcode.

for

servicing

the

device

Software

the

3 31

are

interrupt

Refer

h1ere

handle

request

defined

condition)

8800

Requests

requests

VAX

view,

3.7.1

and

microcode

the

various

interrupt

service

indicate

INTR

3-153

routines.

<4:0>

validity.

The

signal

INTR

Table 3-32

Hardware Interrupt Priority Levels

Interrupt Device

IPL

(Hex)

Priority

Unassigned

Highest

or Condition

Power Fail
Machine Check
NMI Fault
Unassigned
NBI 0, NMI BRY
NBI 1, NMI BR7
Interval Timer
NBI O, NMI BRO
NBI 1, NMI BRG6
NBI 0, NMI BR5
NBI 1, NMI BRS5
Memory, NMI BR5
NBI 0, NMI BR4
NBI 1, NMI BR4
Console Receive
Console Transmit
Other Processor
Unassigned

1E
1D
1C
1B-18
17
17
16
16
16
15
15
15
14
14
14
14
14
13-10

Lowest

CACHE DATABUS <4:0>
——

SST-€ 1A

I_MISC

IPL
LATCH
SEL

MAGNITUDE

REQUEST

INTREQ «5:0>
e

COMPARE

OTHER PROC INTREQ

LATCH

»1

LATCH

» INT PENDING

A>B

CONVERTION
LOGIC

PRIORITY
ENCODER
LOGIC
DEV1 INTR
DEVO INTR

DEV1 INTR LVL <1:0>
DEVO INTR LVL <1:0>

| LATCH
AND

INTR ID <4:0=

LATCH

DECODE

MEM INTR

MKV86-1262

Figure

3-39

Interrupt

Logic

Simplified

Block

Diagram

The encoded INTR ID <4:0> value of a device
directly related to the IPL of the device.
encoded INTR ID <4:0> values and the IPLs.

(or condition) 1s not
Table 3-33 contrasts the

between
Pending interrupts are honored at two different times:
next
the
before
instructions (after one instruction has finished and
at
and
ces),
has stored any results or made any memory referen

well-defined
example,

during

times

a MOVP).

the

execution

of long instructions (for

The special address encoder (part of the IB decoder logic) checks for
for
interrupts at instruction boundaries, the microsequencer checks1logic
These
interrupts during the execution of 1long instructions.
elements both use the INTR PENDING bit to determine if the interrupt
is

to be

honored.

The VAX 8800 system supports two I/0 subsystems with the NBIany I/0
of
adapters (NBIA/NBIB module pair). Each NBI can an interrupt at
INTR

four NMI BR levels (BR 4 to 7). The signals DEVO INTR and DEV1
signify the wvalidity of the interrupt level encoded on the DEV0 INTR
LVL <1:0> and DEV1 INTR LVL <1:0> lines.

to
Note that in a dual processor system, only one CPU is allowed and
respond to 1interrupts generated by NMI connected devices (NBIs each
memory). The NMI interrupt control register (see Chapter 1) of will
CPU is set up at system boot time to insure that only one CPU
accept

NMI

interrupts.

The INTREQ <5:0> lines represent interrupts from the following:

Wk WU

Device or Condition
CPU power fail

Bit

Console receive
Console transmit

CBox error
NMI

(machine check)

fault

Interval

T+~

clock

The INTREQ <5:0> lines are latched to provide a time window for
priority arbitration. The priority arbitration logic is updated every
clock cycle to reflect the current state of the devices and conditions
which may generate

interrupts.

3-156

Table

3-33

Interrupt

1Interrupt

Device

Condition

Power

fail

Machine

Check

ID Codes/IPLs

INTR

IPL

<4:0>

(Hex)

11110

11100

11010

NMI

fault

NBI

NMI

BR7

110600

NBI

NMI

BR7

10110

10100

NBI

Interval
0,

NMI

BR6

10010

NBI

NMI

BR6

10000

NBI

NMI

BR5

01110

NBI

NMI

BR5

01100

Memory,

Timer

NMI

BR5

01010

NBI

NMI

BR4

01000

NBI

NMI

BR4

00110

Console

Receive

00100

Console

Transmit

00010

Other

processor

Passive

release

00001

00000

N/A

NOTE

All

other

microcode

INTR

<4:0>

codes

enter

the

machine

3-157

are

1illegal

check

and

routine.

cause

3.8

CONSOLE GATEWAY CONTROL

The gateway control (GWYC) MCA controls data transfers between IPRs
resident in the console interface logic of the CLK module and the rest
1IBox in the dual processor
Note that each
of VAX 8800 CPU.
CLK module.
the
to
interface
own
its
has
environment
2T\
C

My
L
J¥W

ric

structures

t rols

'
during

system

the

1loading

the
<=

following
il L ilUWwW

CPU

data

@
@

CPU contrcl store RAMS
Cache control store RAMs

Decoder

RAMs

block

diagram

Figure 3-40 is a simplified

T
o

Micromatch register

1ilT

Lz 2l PN ~

gateway

control

logic.

Loading Control Store And Decoder RAMs

3.8.1

The console loads the CS RAMS and the decoder RAMS from the console
Winchester disk through the bidirectional Cons Bidi Data bus which
links the console interface logic on the CLK module to the IBox.

The console specifies the operation to be performed by 1issuing a
Addresses and data are transferred to the
command byte to the GWYC.
GWYC in bytes and is controlled with a strobe signal from the console
interface.

The basic sequence for loading the RAMs and DRAMs 1is:

loaded
Write physical segment count for RAMs or DRAMs to be
to be
bytes
of
number
the
defines
count
segment
(physical
loaded)

Point VBUS to parity error Dbits

Write

Write RAM or DRAM data

Check

RAM or

DRAM address

(in bytes)

Parity

separate
The gateway logic buffers the console data and distributes a
a module
and
control
write
a
with
1IBox module along
to each
copy

During the time the
specific strobe signal to the destination module.
is generated
signal
ADDRESS
SET
specific
a
GWYC is writing an address,
for each

structure.

DRAM,

data
store
or CPU control
store,
manual
this
of
section
Console
the
of
2
to Chapter

cache

Refer

control

for a description of the RAM/DRAM loading process.

p—————— RAM WRT DATA <7:0>

CONS BIDI DATA <7:0>
-

RCVR

DRAM WRITE DATA<6:0>

—CONSOLE

IPR DATA<8:0>

INT CONS DATA <7:0>

65T-€ 1A

XMTR

LATCH

¢———— CACHE DATA <8:0>

XMIT DISABLE

CONS TO DEC PAR
—
CS RAM WRITE CONTROL

» DECODER RAM WRITE CONTROL

CONS CMD FLAG

-—————
|B MUX CONTROL

CONS STROBE
GWYC MCA
BRKPT TRAP EN
MICROMATCH

[-MISC <6:0>"

———»

CONS IPR

———

XMIT TO CONS

—————

CONSOLE REQUEST

ADRS <2:0>

{————
SET MICROMATCH REG
f————

» MICROBREAK
CONDEC

MKV86-1264

Starting The Micromachine

3.8.2

depends

Starting the micromachine

console

the

interaction

between

the

interface on the CLK module and the GWYC MCA.

GWYC
the
The console defines the operation to
register
micromatch
command byte after the

a
MCA through with
(in the UBRS MCAs) is

loaded with the appropriate microaddress.

the
of
source
the
as
The GWYC MCA selects the micromatch register
then
console
The
signal.
REQUEST
CONSOLE
the
microaddress with
the appropriate
clocks
the
initializes the microcode by bursting
initialized, the
is
pipeline
When the microcode
times.
number of
is started by unblocking the clocks.

micromachine

3.8.3

Data Transfer With Console Resident IPRs

the
and
CPU
the
between
The GWYC MCA also controls data transfers
the
when
only
occcurs
This function
resident IPRs.
interface
console
the
field of
micromachine is running and is specified by the I MISC
microword.

the
to enable
1IB MUX CONTROL signal
the
The GWYC MCA generates
to
is
data
When
console data when IPRs are being read.
selection of
enable
to
be written to IPRs, the GWYC MCA generates the XMIT signal
During the IPR write
transfer of data to the console interface.
the
and read functions, the GWYC MCA specifies the byte address of the IPR
with

the

IPR ADDRESS

lines.

Breakpoint Microtrap

3.8.4

to
console
the
allows
Hardware supports a breakpoint feature which
In this stopped state,
VAX CPU based on a consocle command.
the
stop
it is possible for the console to examine the state of the CPU via the
a
specifying
by
accomplished
1is
feature
breakpoint
The
Vbus.
MCAs
UBRS
the
breakpoint microaddress in the micromatch register of
and

request
®
e

one

Stop
Trap

on
on

two actions:

Match
Match

The micromatch register allows the console to set a breakpoint at

microaddress except

Once

the

breakpoint

any

IB decoder generated addresses.

1is

feature

established,

hardware

constantly

breakpoint
the
micro-PC with
the
of
contents
the
compares
microaddress.
When a match
is
found,
the
micromachine
1is
either
stopped by disabling the CPU clocks or a microtrap is generated.
The console specifies to the GWYC
MCA whether
assertion
the
through
microtrap
a
generate
(breakpoint

trap enable)

signal.

3-160

a
micromatch
should
BRKPT TRAPEN
the
of

3.8.5
The

Console

GWYC

MCA

two

actions

for

handling

the

error

running

Data

Parity

Check

checks

parity

in
a

inbound

the

event

parity

error

the

micromachine

1is

stopped

the

assertion

parity

error

3-161

machine

and

The

state

console

signal.

data

error.

current
the

PAROUT

results

console

parity

performs

controlling
the

alerted

the

check

one

factor

micromachine.
of

the

parity

micromachine

microtrap.

EK-KA88E-TD-PRE

SECTION
EXECUTION

BOX

LOGIC

(EBOX)

CHAPTER

INTRODUCTION

1.1

GENERAL

Figure
of

the

The

1-1

execution

EBox

basic

block

diagram

unit

(EBox)

performs

direct

control

(IBox)

logic.

The

control

the

macroinstructions
that

logical

the

main

functions

Perform

logical

Process

CBox
®

Generate

the
)

that

are

to:

shifts

and

from

with

the

CBox

virtual

check

from

parity

operators

WBUS

cs BUS

program

counter

the

cache

unit

IBox

and

pass

the

and

pass

data

received
to

the

from

| MD BUS
-

the

CBox

VA BUS

EBox.

|42 B | pox | PABUS | cpox
-

the

information

internal

1B0X

VAX

(IBox).

BUS

integer

address.

logic.

the

registers

IB DATA
CONSOLE

decodes

routines

execute

from

branch

SUBSYSTEM €«———p (CLK)

and

microcode

and

update

unit

the

unit

and

instruction

condition

under

instruction

fetches

the

rotates,

code

IBox

placement

functions

the

required

IBox microsequencer

Generate
or

logical
kernel.

from

initiates

set

the

data

along

1IBox

operations

data

and

the
CPU

arithmetic

and

EBox

instruction

Transfer

(CBox)

the

floating-point

[

8800

kernel.

the

(PC).

showing
VAX

microcode

from memory
CPU

native

and

CPU

the

Lal

)

S
> =

J\/
SCLD-273

Figure

1-1

VAX

8800

CPU

VI 1-1

Kernel

Block

Diagram

1.1.1

EBox Organization

Figure 1-2 is a basic block diagram of the EBox. The EBox consists
of three modules that form the following logic:

most

also maintains

processor registers
-

The

slice

data word,

The

slice

data word,

logic

module

1
bits

internal

(SLC1l)

processes

the upper

IPRs).

<15:00>.

slice modules also contain the main arithmetic

wunit

(Main

ALU), which performs arithmetic

integer and floating-point data.

The SHR provides additional MCA and

that perform the shift/rotate

and

ALU

operators

multiply/divide

and
data
floating-point
operations on integer or
manipulate the signed exponent of a floating datum.

[

(SHR)

privileged

module (SLCO) processes the lower

0
bits

Shifter

the

<31:16>.

operations on both

Module

(privileged

)

Modules

The slice module section provides the main address
kernel. It
CPU
and data routing circuitry for the

'-J

Data Path
Slice (SLC)

r—————

—

APS

«——NBUS

BUS

MD BUS

| CD BUS

DATA PATH

[ .o

MAIN ALU

SECOND

VA BUS

HALF

(ALS)

SLICE

MODULES

(SLC1/SLCO)

BUS

APORT

SHIFTER

MODULE

BPORT

(SHR)

L———— — — AT— ———— S— A —— C——— —— —S ——— — R —— C— ———4
CS BUS
IBOX <

vV BUS

SCLD-274

Figure

1-2

Execution

Unit

VII

1-3

(EBox)

Block

Diagram

1.1.2

EBox

Operators

The EBox contains the arithmetic logic unit (ALU)} and macrocell
elements, called operators, that perform the logical
(MCA)
array
requested by the VAX native instruction
or arithmetic functions
set.

Operand data is applied
EBox operators are connected in parallel.
to all of the operators, but only the one that applies to the task

is used by
the
cycles,

For operations that require multiple
the microcode.
results of one cycle can be passed directly to the

Main

ALU -- The main ALU is located on the slice modules

same, or another, operator to complete the calculation.

1.1.2.1

and

consists

ALU First Half

The
the

two halves.

(ALF)

ALF performs the main multiplexing functions for the rest of
EBox and contains the partial sum logic for the first part of

an arithmetic operation.

ALU Second Half

(ALS)

The ALS contains the final sum and carry logic, which outputs the
result of an arithmetic operation. The outputs from the ALS and
operators located on the SHR are all connected in parallel on the

bypass

(BP)

bus.

the first part of an arithmetic operation to the
ALF passes
The
It also
on the A and B partial select (APS and BPS) lines.
ALS
1integer or
an
operand of
second
and
first
the
passes
SHR module over the APORT and
to the
floating-point operation
The selected operator then passes the result on the
BPORT lines.
back to the data paths {(slice modules) where the data can
BP bus
be stored or passed along

1.1.2.2

Cache

Data

Another

section

The

CDP

logic

1is

Path

to the CBox or

IBoX.

(CDP) and Bus Watcher/Decoder (BWD) --

located on the slice modules for fast access.

EBox logic called the bus watcher/decoder is

located on the decoder (DEC) module in the IBoX.

VII

1-4

1.2

SLICE

The

data

SLCO),
32-bit

MODULE

path .

e ach
logic:

Parity

Program

Main

1.2.1
The

The

File

(SDF)

Counter

(PC)

the

(CDP)

Arithmetic

Logic

the
PAR

the

SHR module

SDF,

RGF,

performs

Contains

Unit

over

the

Asserts

the

(SLC1

the

and

following

operation
(BP)

write

first

used

four

where

that
of

stores

a main

and

lowest

four

used

the

for

the

ALU

carry-in

are

ALU

the

result

functions:

logic
a

the main

passes

bus.

cycle

highest
they

from

bus.

(W)

logical

carry-save
the

ALU)

(PAR)

CDP

following

(Main

bypass

from

IBox

the

allowing

the.

result

the

carry-out

modules

slice

(PAR)

the

slice

Subsystem

Path

receives

two

16-bit

(RGF)

File

Data

provides

Parity Generator/Checker
PAR

from
to

FUNCTIONS

formed

Generator/Checker

Data

Cache

1is

which

(SLC1l/SLCO)

logic

longword

operation,

cycle.

W bus

bits

microbranch

test

code

conditions.
Generates

the

bits

the

for

zero

byte,

byte

asserts

W bus

negative

(N)

condition

word,

and

longword

and

passes

data)

the

parity.

Generates

with

detected,
byte

W bus

from

the

form

byte

parity

the

Combines

the

and

them

IBox.

Generates

(Z)

it
and

destination

nibble

parity

the

parity

data

received
sets

the

generates

from

VII

the

trap.

1-5

bus

stored

data

and

(with

the

location.

generated

parity

bit

received

where

the

main

the main

ALU

and

compares

bits.

error

parity

error

is
for

1.2.2
The

RGF

consists

parity.

File
of

used

Fifteen

(RGF)
high

data

rate

longword

registers

with

byte

to maintain:

general-purpose

registers

(GPRs),

except

the

Nine

temporary

scratchpad

Eight

registers

memory

data

(TEMPs)

that

are

wused

the microcode.

registers

(MDRs)

that

store

data

from

cache memory.

The

GPRs

are

available

MDRs

are

only

accessible

The

RGF

the

partial

stores

all

software

levels.

autoincrement/autodecrement

results

The

TEMPS

and

the

the microcode.

1long

arithmetic

results (in GPRs) or
operations
{(in
TEMP

registers).
The

RGF

(FPS).

can

also

This

according
1.2.3

can

their

Slow

Data

The

slow

the

microcode

the

The

data

VAX

SDF

parity.

wused

exponent
File

file

for

256

used

and

file (RGF) are both used by
storage and for maintaining many

registers.
low

data

rate

longword

registers

with

byte

maintain:

Most

The

data

Additional

microcode

Temporary

data

are

the

perform a floating-point shuffle
sort
two floating-point operands

size.

temporary

architectural

(SDF)

provides

enabled

internal

path

processor

registers

(IPRs)

constants

when

scratchpad
the

RGF

registers
temporary

(TEMP)

registers

full

Registers

reserved

for microdiagnostic

test

patterns

The
IPRs are available only to the privileged software. All other
registers
are
only
accessed
by the microcode. The SDF operates
under
timing
restraints
that
inhibit
further access to it for
three cycles after a write operation.

VII

1-6

1.2.4
The

and

Program Counter (PC) Subsystem
subsystem maintains the PC, the
trap

PC,

and

file.
These

registers

have

the

following

Supplies

with

Updates
equal

the

processed

increment
PC

(the

I-size).

and
6
generator

The

use

The

two

byte

alignment.

logic

1.2.5

IBox.

instruction

the microtrap

recent

the

copy

the

that

bits

the

are

data

buffer

CDBF

there,

are

also

for

use

in byte

bypass

(CDBF)

can

data

the

data

the

being

fault.

active

virtual

the

for

activity,

routines
the

time

example).

address

the

sent

CBox.

causes
IBox

with

Serves

microtrap.

sequencer

(SEQ)

sent

the

SHR module

instruction

alignment

after

for

use

buffer

(IB)

flush.

Cache

memory

CDS

the

latch

Data Path (CDP)
functionally part of the CBox,
located
on
the slice modules.
The

The

service

code

logic.

sent

They

the

and

was

reserved

allows

address

sent

microbranch

bits

the

service

last

This

examine

history

address

backup

the

occurred
(a TB miss,

wvirtual

code

the

example).

being

value

a macroexception

Although

the

restoring

the

IBox

the

providing

lowest-order
the

from

Maintains

highest-order

for

CBox

value

data

increment

supplied

routines

Holds

two

module

(VA)

the

increment

1is

service

backup

(I-stream).

I-stream

The

software

the

and

for

causes

failing

the

for

microtrap
File

fault,

(TB)

stream

adding

size

operand

copy

the

instruction

Trap

buffer

instruction

Stores
the
PC
macroinstruction,

the

address

functions:

translation

the

between

Backup

virtual

virtual address for each operating code
<code),
operand
specifier
(op
spec), and

(op

Incrementer

incrementer,
the

the

operand

the

called

can

the

written

the

CDS

bus

data

with

the

(from

asserts

store

modified

CBox

written

multiplexer
written

cache

written

from

data

CBox

and

IBox

where

new

VII

1-7

data path
consists of the

from

memory

(CDP)

cache

the

data

W bus

(MD)

bus.

with
From

RAM.
on

data

RAM.

cache

(CDS).
data

the

CDS

the

CDP

the

cache

data

written

those

(CD)

bus

to memory).

lines

while

1.2.6

Main Arithmetic Logic Unit (Main ALU)

The main ALU is a 32-bit adder that performs the main multiplexing
functions for the EBox (see Section 1.1.1). It performs the
following arithmetic functions and operations:

and

Addition

borrows

carries and
propagated
with
or decimal string
floating-point,

subtraction

integer,

data.

Generates

carry

Provides

masking

the data and passes them to the

for

the

IBox.

hidden

bit and overflow bit

positions on floating-point instructions.
OR,

and XOR operations.

Logical AND,

results of an operation to the PAR MCAs over
the
Passes
The results are then passed on the W bus to
the BP bus.
the RGF or SDF, or to the cache data path (CDP) or IBox.

a CDP destination, the virtual address is passed to
For
The VA file contents are
translation buffer.
CBox
the
event that the virtual
the
in
also sent as a backup
address

1.2.7

causes

trap.

Bus Watcher/Decoder

(BWD)

The BWD controls the bypassing operation, which selects the
for the BP bus and selects the inputs to the main ALU.
outputs
When the BWD detects a condition that could prevent data from
arriving at its destination in time for the current operation, it
overrides the microcode fields that normally select the main ALDU
inputs, and enables the BP bus for the transfer.

1.3

SHIFTER MODULE

The
SLC
on

shifter
logic
the

module
the

bus.

APORT
It

Floating-Point

The

Priority

Shift

Exponent

Support

Encoder

(PEN)

ALU

microcode

operators

(including
performs

XALU

1.3.1

ALU

executing
decimal

while

32-bit

sets

operators:

VAX

the

SHF,

native

operations).

from

the

result

and

main

instruction

set

while

that

integer data

MULT,

However,

conversions

functions

extracts

processing

Integer

Floating-Point

Decimal

String

1Integer

Data

l.3.1.1

data

the

support

the

SHF

PEN,

SALU,

the

types.

(SHF)

shift

use

the

string

hardware

shift matrix

input

(MULT)

extensive

and G_floating

Shifter

64-bit

bits
a

(XALU)

floating-point

provide

SHF

(SALU)

makes

1in

all
several

Dfloating

returns

following

(FP)

Multiplier/Divider

ALU

The

the

and

(SHF)

CPU

and

BPORT

provides

Shifter

FUNCTIONS

receives

and

(SHR)

(or

rotate)

arithmetic

right

32-bit

the

following

SHF

performs

output

three

from

data

types:

(FP)

—--

The

arithmetic

shift

right

than

left

logical

integer

data.

On
output

the

1is

sign-extended.
1.3.1.2

align,

Floating-Point

right

floating-point
shift
the

count

shift

datum.
received

count

The

SHF

performs

1left

Data

shift

the

fraction

from

the

bus.

VII

1-9

field
support

shift
logic

normalize,

field

based

(PEN

the

SALU)

1.3.1.3

Data

String

Decimal

decimal string data conversions:
32-bit
16-bit
32-bit
32-bit

The SHF performs the following

trailing --> 16-bit packed
packed --> 32-bit trailing
packed --> 32-bit integer
integer --> 32-bit packed

Floating-Point

1.3.2

Support

(FP)

The FP support logic processes the sign and exponent fields of the
F floating, Dfloating, and G floating data types.

three elements, each of which consists of a single MCA:
Priority Encoder (PEN)
Shift ALU (SALU)
Exponent ALU (XALU)

1.
2.
3.
1.3.2.1

Priority

following logical
PE

consists of

Logic

(PEN)

Encoder

The

PEN

consists

the

subsections:

logic scans
This
floating datum to
bit.

the mantissa field of a
find the most significant 1

then passes the shift count necessary

to normalize the number to the shifter (SHF) and

to the exponent ALU (XALU).
Round
Logic

Select

Sticky Bit

During an FP alignment, this logic saves the
last two bits shifted out of the data field for
use as the rounding bits in a normalization.
This logic examines the eight most significant
bits shifted out during an FP alignment. If alil
8 bits are 0, the logic sets a carry-in bit for
the main ALU.

shift
number,

increment

Rounding
Increment

performs a 0 or 1l-bit right or left

the low-order byte of a floating
and passes the result to the rounding
logic.

This logic takes the normalized 8 bits from the
fast normalize logic and adds a 0 or 1 to it,
according to the rounding bits and the operation
(add or subtract). When enabled, it passes the

result

number.

the

low-order

byte of the floating

1.3.2.2

Shift

two

operands

ALU

(SALU)
and

difference.

This

shift

then

shifts

the

fraction

align

the

1.3.2.3

Exponent

inputs.
the

MULT

from

the

are

sent

the

shifter

data

performs

correction

other

field

8-bit

scale

multiply

per

bits

produce

the

correct

that

the

cycle.
end

applied

result

MCAs

that

are

(VLSI)

32-bit

integer

result

which

order

arithmetic

data

the

integration

both

according

per

MULT

result.

algorithm

cycle.

Eight

that
cycles

result.

complement

premultlply

custom

floating-point

multiply

32-bit

two's

divide

and

technology.

results

for

post-multiply

sign

necessary.

one-bit-at-a-time

bits

floating

of
the

logic.

eight

the

(SHF),

XALU

the

(MULT)

exponents

based

operand

eight
-bit-at-a-time

Producing

bit

the

count

smaller

The

exponent

64-bit

eight

required

integer

each

shift

by:

generates

uses

subtracts

=--

fields

large

speed

Using

quotient

SALU

the

very

produces

multiplication

(XALU)

adjusts

consists

improves

field

exponent

count

implementation

count

Multiplier/Divider
MULT

The

ALU

the

shift

1.3.3
The

The

operands.

operations
its

generates

division

algorithm

that

The

quotient

bits

are

each

division

loop

quotient.

VII

1-11

generates

subtracted
produce

the

two

from
true

EBOX REGISTERS

1.4

Table 1-1 lists the privileged internal processor registers (IPRs)
The register numbers
maintained in the EBox slow data file (SDF).
Software access is
notation.
(hex)
in hexadecimal
expressed
are
shown as read/write
Table

1-1

(R/W)

or read-only

Privileged

IPRs Maintained by

the EBox

Mnemonic

Number

Access

KSP
ESP

00
01

02
03
04
08
)
0A
0B
0C
0D
10
11
12
13
15

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

MCSTS
SID
REVR1
- REVR2

26
3E
86
87

R/W
R/0O
R/0O
R/O

Registers

Kernel Stack Pointer
Executive Stack Pointer

Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer
PO Base Register
PO Length Register
Pl Base Register
Pl Length Register
System Base Register
System Length Register
Process Control Block Base
System Control Block Base
Interrupt Priority Level
Asynchronous System Trap Level
Software Interrupt Summary
VAX

(R/0).

SSP
UsP
ISP
POBR
POLR
P1BR
P1LR
SBR
SLR
PCBB
SCBB
IPL
ASTLVL
SISR

8800-Specific Registers

Machine Check Status Register
System Identification Register
Revision Register 1
Revision Register 2
Notes:

Refer
VAX

to the VAX Architecture Handbook

Architectural

for descriptions

the

IPRs.

The
IPL
register
resides
1in
the
1IBox
as part of the PSL
hardware
1image
and
in
the
SDF as part of the PSL software
image.
The microcode maintains both images equally.

l.4.1

POLR,

PI1LR,

than

seen

P1LR,
and

the

requirements.
Conversion
executed.

and

POLR,

The

P1LR

1.4.2
The

VAX
EBox

Formats
SDF

are
MTPR

and

different

memory management

1listed
and

SLR

MFPR

format

microcode

Table

1-2.

instructions

Internal

are

Formats

Format
format

largest

multiplied

virtual

minus

the

512.

address

software

space

format multiplied

512.

8800-Specific

contains

the

Pl1LR,

(7FFFFFFF),
by

Bit
the

changes

software

The

because

when

Internal
SLR

Internal

stored

format
place

1-2

SLR

are

software

The

takes

Table

POLR

and

SLR

four

Registers

registers

that

are

unique

the

VAX

8800

system.

1.4.2.1

Machine

status

information

Check

operating
system
descriptions.

Status

for

the

shown

machine

(MCSTS)

check

Figure

—-

microcode

1-3.

Table

The
and

1-3

MCSTS

stores

the

VAX/VMS

provides

bit

03 02 01 00
MBZ

SCLD-275

Figure

1-3

Machine

Check

VII

Status

1-13

(MCSTS)

Machine Check Status Register (MCSTS) Bit

Table 1-3

Descriptions

Description

Bit(s)

Name

<31:03>

Must be

Unused and must be

Zeros

zeros.

(MBZ)

Set

Abort (ABT)

<00>

Check

Machine

the

(MC)

1is
instruction
an
when
microcode
if
Used by VMS to determine
aborted.
the error caused a fault or abort.

was
Indicates that the MC microcode
Checked
entered but did not complete.

Enter Machine
Check (MC)

<01>

to
starts
microcode
MC
the
when
MC
the
set,
If
error.
an
service

the
to
control
passes
microcode
microcode.
halt
error
double
sets
microcode
MC
the
Otherwise,
error.
ENTER MC and processes the

Indicates

Enter VMS

<02>

that

the

VMS handler was

entered but did not complete. Checked
finishes
microcode
MC
the
when
the VMS
set,
If
error.
an
servicing
handler did not finish processing the
and the MC microcode
error
previous
the double error
to
control
passes
MC
the
Otherwise,
code.
halt
ENTER MC bit,
the
resets
microcode
bit and passes
VMS
ENTER
the
sets
to the VMS handler. When VMS
control
processes the error, it
successfully
resets the ENTER VMS bit.

shown in
Register -- As
(SID)
Identification
System
1.4.2.2
i n codes
Figure 1-4, the SID register holds the system identificatio

that

identify a specific VAX system.

1-4 des
Table
apgie 1—4%

o’ s

the bit

fields.

16 15

24 23 22

SYSTEM SERIAL NUMBER

CPU TYPE

HARDWARE
REVISION

LEVEL

Figure

1-4

SCLD-276

System Identification

vii 1-14

(SID)

Table

1-4

System

Bit
Bit(s)

Name

<31:24>

CPU

Identification

Field

Type

Hardwired

the

backplane

for
Left/Right

define

value

The

the

VAX

equal

00000110

8800

the

identification

physical

the

Right

CPU

Left

CPU

Hardware

Kernel

Revision

Changed

when

Level

hardware

revision

impacts

the

VMS

operating

system

hardware

revision

level.

System

Hardwired

Serial

Equal

Number

imprinted

jumpers

the

system

the

during

1-5

system

backplane.

serial

cabinet

both

number

nameplate.

CPUs

initialization.

shows

the

REVR1

bit

format,

and

Table

1-5

describes

the

shows

the

REVR2

bit

format,

and

Table

1-6

describes

the

fields.

Figure
bit

Registers
(REVR1 and REVR2) -- REVR1 and REVR2
(in decimal) the revision levels of the modules and other
components, and also some of the software components that

loaded

Figure
bit

Revision

indicate
hardware
are

and

CPU

cabinet:

It
1is
the
same
for
dual-processor system.

1.4.2.3

(six)

location

diagnostics.
<15:00>

order

processor.

system.

logical

system

specific

Defines

the

<22:16>

Description

<23>

(SID)

Descriptions

1-6

fields.

SHR

SLCA1

SLCO

ADP

CCS

DEC

WCS

SEQ

SCLD-277

Figure

1-5

Revision

VII 1-15

(REVR1)

Table 1-5

Revision Register 1 (REVR1) Bit Field Descriptions

Bit Field

Unit

Module Revision Level

<31:28>

EBox

Shifter module (SHR)

<27:24>

EBox

Slice 1 module (SLCl)

<23:20>

EBox

Slice 0 module (SLCO)

<19:16>

CBox

Address Data Path module (ADP)

<15:12>

CBox

Cache Control Sequencer module (CCS)

<11:08>

IBox

Decoder module (DEC)

<07:04>

IBox

Writeable Control Store module (WCS)

<03:00>

IBox

Sequencer module (SEQ)

MRS

08 07

16 15

24 23

ODE

RESERVED

04 03

OO.

CPU/NMI | CLK
sSCLD-278

Figure 1-6

Revision Register 2

(REVR2)

Table

Bit

1-6

Revision

Field

<31:24>

(REVR2)

Name

Definition

Software

Revision

Elements

loaded
the

level

console

components

Field

the

software

CPU

Cache

medium.

Constants

Data

Store

Control

into

made

the

released.)

being

SDF

individual

before

the

user

are

package

user microcode

the

WCS.

<15:08>

Reserved

<07:04>

CPU/NMI

Revision

level

the

CPU/NMI

Clock

Revision

level

the

Clock

<03:00>

RAMs

components

complete

level

software

I-decode

into

1loaded

from

firmware

incorporated

Revision

time

The

firmware

Store

loaded

User

components

initialization

storage

Control

Microcode

Descriptions

include:

—

(Changes

<23:16>

system

Bit

backplane.

(CLK)

module.

EBER

indicates

Module

l1.4.2.4

EBox

parity

errors

pointers
The

Parity

the

microcode

similar

source
stores

registers

called

the

occurs,

several

MCEB.

The

MCEB

access

the

MCEB,

refer

this

The
only

the

EBER

the

check

machine
is

contents

CBox

error
pushed

and

The

BPORT buses

with

(MCEB).

onto

check

along

IBox

bank

registers.

the machine

(EBER)

and

provides

errors.

check-related

then

various

the APORT

machine

For

stack

contents

data

written

provide
the

check
to

the

software

information
in

structure

a machine

are
to

further

description

SDF

When

registers
the

the

IBox

the

section

manual.

EBER

detail

Error

detected

1is

located

accessible

Chapter

in
the

the

parity generator/checker

microcode.

VII

1-17

(PAR)

described

and

further

CHAPTER
FUNCTIONAL

2,1

GENERAL

The

EBox

logic
is

makes

(ECL)

based

logical

This
and

for
1in

extensive

its

main

wuse

array

describes

intended

for

SLICE

MODULE

2-1

use

(MCA)

the

EBox

logic

the

module

(SLC1/SLCO)

block

diagram

and

SLCO

modules.

the

following

EBox

the

SLCl

Parity

Slow

Program

Cache

)

Main

2.2.1

2-2

(PAR)

logic,
MCA

generates

File

(PC)

Arithmetic

Logic

block
is

passes

one

byte

parity

the

block

PAR

provides

for

Unit

Generator

Parity

Checker

Carry

Table

2-1

Error
Save

describes

diagram

level

32-bit

data

path

provides

logic

formed

16-bit

slice

two

data

storage

(Main

ALU)

(PAR)

following

Parity
Parity

main

(PAR)

diagram

formed

byte

the

logic

the

sets.

the

parity

generator/checker

PAR MCAs

each

the

with,

rest
or

checks

slice module.
data

on,

data.
The

ECL

DESCRIPTION

the

Generator/Checker

which

this

Subsystem

(CDP)

that make

(SDF)

Path

emitter-collector

(RGF)

Counter

Data

Most

Each module
operators:

File

Data

Parity

Figure

Generator/Checker

density

chips

with

Each

high

functions.

operators.

2,2
by

logical

macrocell

chapter
is

Figure

DESCRIPTION

(PE)

logical

functions:

Logic

the

PAR

input

VII

and

2-1

output

signals.

the

paths

and

received

PARITY
GENERATOR/

WBUS | CHECKER

(PAR)

BP BUS

(FM SHR)

MAIN ALU
SLOW DATA
FILE (SDF)

APS

BP_ BUS

SDF

256 X 36

ALU

FIRST

FB SDF

_»

PC VA FA

A CD

(RGF)

¢-¢ IIA

Pl (ALF)

BPS

p{ HALF

(ALS)

APORT
SHR)

» (TO

» BPORT

HALF

QEgOND

pc suB-

SYSTEM

» VA BUS
(TO CBOX)

IB DATA
(FM I1BOX)
CD BUS

(TO

MD CD

I1BOX)

CACHE DATA PATH (CDP)
WR DATA

WBUS OUT
«30:27,03:00>
(TO IBOX)

CACHE DATA

BUFFER

(CDBF)

| i

CACHE DATA

STORE

(CDS)

A CD

PA BUS (FM CBOX)

» MD BUS (TO/FM CBOX)
SCLD-279

Figure

2-1

Slice Module

(SLC1/SLCO)

Block Diagram

PARITY GENERATOR/CHECKER
(TWO PAR MCAs PER SLICE)

BP BUS<31:00>

H—

SLC SHFT <3:0>

H—

APORT PAR<7:0>

H—

IB PAR<3:0>
A CD PAR<3:0>
FILE A PAR<3:0>

L —(Q
H —
H —

I_APORT<7>
PORT CNTL<11:08,03:00>

L—=C

BPORT PAR<7:0>

H——

WBUS PAR<3:0> H,
——— WBUS<31:00> H
BP BUS

ALU

GENERATOR

pP—

ALU ZBIT<3:0>

PARITY

NBIT

<8,1:0> H
L

A-SIDE

PARITY

CHECKER

PAR<3:0>

H—]

PE<1:0>

L—O

A CD PAR<3:0> H

B-SIDE

FILE B PAR<3:0> H

SLC<1:0>

gfig&\éfl

SDF PAR<3:0>

H—

ALU CBIT<2:1>
ALUCi<i:0>
<1:0>

H —
H

ERR PAR H
'

OCIN
CARRY

CINSRC<1:0>H

INH

SAVE

ALU

SRC<4>
CIN

LATCH AND

SDF WR H —

STALLED A CLK H ——

B CLK H——— DISTRIBUTION

KEEPGOINGA<1:0>H

SCLD-280

Figure

2-2

Parity

Table

2-1

Generator/Checker

Parity

Data

Input

Bypass

(BP

Diagram

(PAR)

Description
and

Parity

Bus

BUS<31:00>

Slice
(SLC

Name

Block

Generator/Checker
Descriptions

Signal

(PAR)

The

Shift
SHFT<3:0>

Control
PAR

Valid

Signals

section

data

E SHFT<4:3,1:0>
H)

receives

from the main ALU or
shifter (SHR) module ALUs
bypass (BP) bus.

VII

2-3

the

from the microword
the PAR MCA parity register
Table 2-5).

control
(see

longword

Table

Signal

Parity Generator/Checker (PAR)
Signal Descriptions (Cont)

2-1

Name

Valid

Description

Data and Parity Output
Write

Bus

(W BUS<31:00> H)

The W bus passes received BP bus

data to the slow data file, register file, and BP cache data path.

T8 to TI10

W BUS <30:27,03:00> H are asserted
to the sequencer (SEQ) module as
W BUS 0UT<30:27,03:00> H for
microbranch conditions.

Write Bus Parity
(W BUS PAR<K3:0> H)

Byte parity is generated on

received BP bus data and asserted
as the W bus byte parity bits
(one bit from each PAR MCA).

T8 to T10

W BUS PAR<3:0> are written to the
slow data file, register file, or
cache data path along with the
received BP bus data.

ALU Negative Bit
(ALU NBIT<3,1:0> H)

Asserted to the IBox, which

produces the negative (N) condition
code bit for a byte,

word,

T10

longword. ALU NBIT<3> H is asserted
from PAR 3 as W BUS OUT<31> H.

ALU

Zero Bit

(ALU ZBIT<3:0> L)

Asserted to the IBox, which

combines the signals and produces

the zero (Z)

a byte,

word,

T8 to T10

condition code bit for
or longword.
NOTE

and Z byte values are generated
the

valid

error

Parity Error
(PE<1:0> H)

BP bus

when

inputs and are not

reading

the

parity

ORed on each slice module. Asserts
the slice parity error signals
SI.C1 PAR ERR H and SLCO PAR ERR H
to the sequencer (SEQ) module to
generate a machine check. (These
bits do not include cache data
path parity errors.)

VII

2-4

T8 to TI10

Table

2 -1

Parity

Signal
Signal

Name

A-Side

Input

APORT

Parity

(APORT

Generator/Checker

Descriptions

Description

valid

Signals
APORT

PAR<7:0>

nibble

each

parity

the

first-half

eight

(ALF)

generated

main

MCAs

Parity

(IB

PAR<K3:0>

Cache

Data

PARK3:0>

File

Parity

(FILE A
I

Parity

PAR<3:0>

APORTK7>

(APORT<7>

Instruction

buffer

parity

the

IBox.

from

the

from

Byte

parity

path

(CDP).

File

A byte

parity

file

from

(SLC1/SLCO

CSO

the

Used
to

PORT

select

the

data/parity

Control

A-side

port

CNTL<11:08,

(DEC)

module.

B-Side

Input

BPORT

Parity

(BPORT

Cache

Data

PAR<3:0>

File

Parity
H)

Parity

(FILE

Slow

Data

PAR<3:0>
File

Parity

(SDF

PAR<3:0>

A-side

BPORT

PAR<7:0>

PAR<3:0>

signal

CNTL<11:08,03:00>
A-side

byte

source

(see

Used

above,

byte

from

the

with
to

select

data/parity

source.

Signals

Parity

(IB

microword

control

I APORT<7>,

the

data

the

2-2).

(PORT

the

bit

APORT

03:00>

cache

DATA<1>

backplane).

with

Table

byte

from

ALU

(RGF)

I APORT<7>

(IB)

ALU

operation.
IB

(PAR)

(Cont)

nibble

each

parity

the

first-half

(ALF)

Instruction

buffer

from

the

generated

main

ALU

MCAs.
(IB)

byte

parity

IBox.

Byte

parity

path

(CDP).

File

byte

eight

from

parity

file

Byte

parity

file

(SDF).

the

from

data

the

(RGF).

from

VII

cache

2-5

the

slow

data

Table

Signal
Slow

Name.

Data

From

the

vValid

SDF,

inhibits

E _BPORT<8>

E BPORT<8>

RD MODE

parity

checking during a write
Valid from T8 to T10 of
microinstruction
SDF write.

(PAR)

Description

File

Write
(SDF WRITE

2-1
Parity Generator/Checker
Signal Descriptions (Cont)

from

requesting

SLC1/SLCO

DATA<6>

the

Used

with

PORT

TI10

T6é

SDF.

the

the microword

(asserted
L

to the
the

CSO

backplane).

CNTL<15:12,07:04>

to select the B-side byte
data/parity input source
(see
BPORT

Control

B-side

(PORT CNTL<15:12,
07:04> H)

Carry
ALU

Save

Carry

(ALU

Table

and

Trap

Bit

port

control

from

decoder (DEC) module.
E BPORT<8>, above, to

B-side

byte

Shadow

Signals

Asserted

CBIT<2:1>

2-3).

the

data/parity

from

upper

the

Used with
select the

input

source.

upper ALU byte

PAR byte

the

same

slice module. Valid from T7 to T9
of the instruction producing a word
Carry.

Output
In

Carry

Asserted

Source

(OCIN

SRC<4>

each

from

the

slice

CIN SRC<K1> H
in the upper

upper

module.

PAR byte

Asserted

to the carry save logic
PAR byte of the other

module.

ALU

Carry

(ALUCIK1:0>

E ALUCI<K1:0>
H)

with

ALU CIN carry
2-6).

Table

ALU Carry
(ALU

CIN

In
H)

from

Used

Asserted

both

CSL

from

ALU bytes

the

CTL<0>

microword.
to

select

source

(see

upper

PAR byte

same

the

slice

module. Valid from T6 to T8 of the
microinstruction using the carry in.

Table

Signal
Carry

2-1

Name

Parity

Generator/Checker

Signal

Descriptions

(PAR)

(Cont)

Description

Source

(CINSRCK1:0>

valid

CINSRCK1>

the

PAR byte

upper

OCIN

SRC<4>
of

the

from

other

slice module. Valid from T7 to T9
the microinstruction generating

the

carry.

CINSRC<KO0>
the

SLC1
of

and

the

carry.
CTL<1>

Save

CSL

Latch

Control

microword

(CSL

CTL<K1:0>

carry

save

CSL

CTL<KO>
byte

carry

(INH

SDF

Write

WR H)

from

both

generating

from

the

load

the

FPOP

from

the

same

slice

the

upper

module.

select

the

floating-point

source

for

the

subsystem

Tll

T17

a microinstruction

global

trap.

from

T1ll

T17;

half-cycle

delayed

trap

this

and

1is

3-cycle

signal.

Control

Keepgoing

Holds

(KEEPGOINGA

latches

the

extended

<1:0>

used

ALUCI<K1:0>

following

causing

Distribution

from

E LDCSL

CIN.

Valid

Clock

Valid

carry

Asserted

SRC1<0>
logic

latch.

with

integer

Inhibit

and

ALU

Used

CIN
bit

SLCO.

the

ALU

microinstruction

Carry

SHR guard

the

outputs)

Table

cache

open

during

2-4).

VII

2-7

data

CD
a

parity

PAR<3:0>
stall

(see

2.2.1.1
the

Parity

following

-- The parity generator logic performs

functions:

data from the main ALU on the BP bus if ALUENBP
Receives
receives data from the SHR
it
Otherwise,
asserted.
is
module
or
receives
only zeros. It distributes received
data

Generator

on the W bus

the

RGF,

SDF,

and CDP.

the received BP bus data and
on
parity
byte
Generates
from where it may be written
bus
W
the
on
it
distributes
parity may be forced for
Zero
CDP.
or
SDF,
RGF,
the
to

maintenance operations.

Generates the negative (N) and zero (Z) bit for each byte
to the IBox where they are combined to
them
passes
and
7Z condition code bits of the processor
and
N
the
form
status

longword

(PSL).

2.2.1.2
Parity
Checker
-- The parity checker logic performs the
following operations on the main ALU data:

the main ALU performs an add or subtract operation,
When
parity on the data asserted to its
nibble
generates
it
It outputs the nibble parity to the
B-side.
and
A-side
checker where it is
parity
the
of
B-side
and
A-side
combined

The

parity

form byte

parity.

checker

compares

slices are ORed and asserted to
both
module to generate a machine check.

the sequencer

Checker
es

®
)
°

the byte parity bits with

sources applied to the A-side and
data
the
from
those
ALU. The byte parity error signals
the main
of
B-side
from
(SEQ)

A-Side

the

nain

following

sources:

Instruction Buffer (ILB) parity bits
Cache Data A (A CD) output parity bits
File A (FILE A) output parity bits

I _APORT<7>

and the port control fields

PORT CNTL<11:08,03:00>

from

module control the A-side checker as shown in
(DEC)
decoder
the
Table
2-2.
Only
the lowest bit-pair is described; the functions
for the other 3 pairs are

identical.

B-Side

Checker

The

B-side

with

the

checker

parity

bits

compares the main ALU BPORT parity
from the following sources:

Instruction
Cache

for

the

Other

)

bit

output

2-3.
other

File

and

decoder

bits

control

module

fields

control

the

PORT

CNTL<15:12,07:04>

B-side

checker

described;

the

shown

functions

The
parity checker is disabled during SDF writes and for
A-side
data
that
involves
a
floating-point
mask
(a
function that changes the data before asserting it on the
APORT
1lines).
(The
parity checker may also be disabled

maintenance

functions.)

The
first
parity
parity error trap.
the

parity

not

(PE)

1locked.
but

Further

are

and

errors

serviced

that

the

EBox

side

same

the

side

are

parity

error

check.

microinstruction

the
or

error on either side generates an EBox
The error for that side is reported in

error

1is

recorded

machine

)

bits

parity

Functions:

port

(DEC)

bits

parity bits
parity bits

(SDF)

the

parity

output

Only the lowest bit-pair
3 pairs are identical.

Checker

for
®

(FILE

Data

the

Table

CD)

Slow
BRDMODE

(IB)

from

Buffer
A

File

The

Data

output

write
not.

the

Further

Cache

data

stall,

depending

bits and
in Table

that

generates

destination

writes

(CD)

are

parity

the memory
2-4.

the

data

VII

blocked

checks

are

state

2-9

bad

whether

the

parity

the

data

completes
is correct

the

trap

shadow.

maintained

CD ready

(MD)

valid

during

valid

bit

shown

Table
PORT

2-2

A-Side

Port

Control

CNTL

I_APORT<7>

Selected Data/Parity Bit

Virtual

1
-

0
0

0
1

File A
Instruction

1
1

0
1

Bypass (BP) Bus
Cache Data (CD)

Address

(VA)

Source
or

Program

(PC)

Table

Buffer

2-3

(IB)

Bus

B-Side

Port

Control

CNTL

PORT

BRDMODE

Selected Data/Parity

Slow

Data

File

Instruction

1
1

0
1

Bypass (BP) Bus
Cache Data (CD)

Table

Counter

2-4

Keepgoing

File

Conditions

Buffer

(IB)

Bus

for A CD PARK3,1>

Valid

Ready

Valid

Keepgoing

~
-

1
0

0
1

2-10

Source

(SDF)

VII

Bit

2.2.1.3
EBER bit

EBox Parity Error Register
format and functions. This

each byte
®

and

peforms

Monitors

the

source

Records
data

EBER

2-5

A parity

that

shows

following

ALU

byte

the

A-side

Table

the

select

byte

parity
and

the

E SHFT

either

side

lines

determine

the

error.

B-side)

produced

how

functions:

1input

parity

first
the

(EBER) -- Figure 2-3 shows the
register occurs in the MCA for

error

that

indicates

occurs

the

(for

source

the

controls

the

error.

field

the microword

logic.
on

generates

parity error

trap

and

1is

stored, locking that side of the register. Further errors generate
machine checks. The effects of parity errors can only be inhibited
by disabling all traps from the console.

B-SIDE

A-SIDE

DATA SOURCE

A-SIDE
PAR

ERR

B-SIDE
PAR ERR

DATA SOURCE VALUE

onn
nw

SDF
CACHE - IB MD CD BUS
BP BUS (NO PAR CHECK)
CACHE - A CD BUS
RGF - FILE B

A-SIDE

|
|I
I
LI

~PWN—+O

B-SIDE

DATA SOURCE VALUE
VA OR PC

(NO

PAR CHECK)

CACHE - IB MD CD BUS
BP BUS (NO PAR CHECK)
CACHE - A CD BUS
RGF -

FILE

A
SCLD-281

Figure

2-3

EBox

Parity

VII

Error

2-11

(EBER)

Table 2-5
E_SHFT<4:0> Control of the
EBox Parity Error Register (EBER)
E

SHFT

Bits

11-00

Function
during

Inhibits
A-side
parity
checking
floating-point mask operation.

11-01

Forces

zero

bus

parity

during

a maintenance

operation.

11-10

Clears

(opens)

Reads

(closes/latches)

-11

onto

2.2.1.4

Carry

following

Save

functional

the

the parity error register.

the

Logic

The

carry

The

carry-in multiplexer

®
®

The
The

carry save latch (CSL)
floating-point carry selection

Save

save

logic

contains

the

elements:

Carry

parity error register

W bus.

latch

Functions

PAR
MCA for the upper byte on each slice module uses the CSL
preserve
word
and
longword carries from an ALU operation. A
latched
carry-out
1is
then
wused
as
a carry in on the next ALU

The
to

vxrm
T o~

cycie:

A
is

latched
carried

A
latched
(CSL<15>)

integer carry-out from ALU bit <31> (CSL<31>)
into ALU bit <00> on the next integer cycle.
floating-point
carry-out
is
~carried
1into
ALU
bit

floating-point

cvcle.

VII

2-12

from
<16>

ALU
ALU

bit

<15>

the

Table

2-6

from

hardware
0,

shows

the
l,

how

the

EALUCIK1:0>
both

the

select
CSL,

carry-in multiplexer

field

carry

the

guard

in.

The

bit

operation

(FPOP)

the

integer

floating-point

bit

from

The

the

controlled

microword

from

floating-point
cycle

source

the microword.

can

and

select

SHR module.

the ALU defines

The

whether

operation.

Traps
On

trap,

carry

save

SDF

write

trap

shadow,

backup

and

(INH

values

latches.

The

1latches

are

floating-point

SDF

loading
to

the

signal
backup

carry

latches

Table

WR)
the

are

2-6

from

the

latches,
and

loaded

Carry-In

save

selection

PC
and

the

contents

latches.

subsystem

The

trap

Control

ALU

carry

routine.

the

Source

ALU1K16>

Carry-In

Source

<--

ALU0OKO00>

<-=-

ALUOK16>

<--1

ALU0O<K00>

<--

CSL<31>

(Integer)

ALU1<16>

<--

CSL<K15>

(FP)

VII

2-13

the

indicates

Bits

FPOP

inhibit

also multiplexing

floating-point

E ALUCI<1:0>
ALU

ALUCI

save

not

used

carry

CIN

the

selection

2.2.2

The

RGF

outputs

File

and

data

(RGF)

passed

outputs are multiplexed with the SDF data

the B-side of the main ALU (Figure 2-1).

the parity outputs for both RGF File A and File B, and
However,
for the SDF, are connected to the A-side and B-~side inputs of the
PAR parity

checker.

1is a block diagram of the register file (RGF) logic,
2-4
Figure
which provides thirty-two 32-bit registers with byte parity. The
RGF consists of a set of write-enable delay latches that drive two
MCAs per slice.

custom ECL muliple-register (MPR)

RGF is used for all of the general-purpose registers
The
The remaining 17
except the program counter.
(GPRs)

microprogram
the
by
used
are
locations
management and scratchpad registers.

outputs

separate

(File

memory

A and File B) carry 32-bit

Two

Two separate read addresses and two separate write
addresses may be applied to the RGF RAM at once. Two read
and two write functions may take place at the same time

data to the A-side and B-side of the main ALU.

with the

Two

following limitations:

reads

may

writes

access the same location at the same

time.

Two

results.

bus has byte,

word,

2-7

describes

or longword access to all

locations.

the lowest 8
to
access
longword
has
CD bus
The
are the memory data (MD) registers
These
locations.
and are not used as general-purpose registers.

Table

The

location at the same time

unspecified

produces

same

the

shows

the

RGF

memory

address allocation. Table 2-8

the RGF read and write signals.

-- Under control of the
(FPS)
Shuffle
Floating-Point
2.2.2.1
the SHR module, the IBox performs an FP shuffle by
and
microcode
A shuffle occurs when FPS is
addresses.
read
the RGF
swapping
(EFPSUFL from the microword) and the XALU compare (XALUCC
enabled
H)

signal

Bit

<1>

compare

is asserted by the XALU on the SHR module.

either read address is also complemented if the XALU

signal is asserted and address bit <2> is a l. This swaps

for read purposes, but
locations
scratch
quadword/longword
the
file areas that are defined with address bit <2> as a 1.
in
only
The function is mainly used to sort two floating-point operands in
order according to their exponent size.

VIT

2-14

RADDR A<4:0>

—

]
I
1
|
i

W BUS

PAR<3:0>

W BUS<31:00> H

;
]

|
|
I
]
!

W WADDR<4:0>

W WRITE

]

DATA PORT

L ———dLAT

WRTEN<3:0> L—d2,rb—dpaTh

DCDR

;
!

—»

3:::

i
I|
|

CD BUS

PAR<3:0>

CD BUS«31:00>

FILE

A<31:00>

PAR<3:0>

FILE

B<31:00>

>
v

L —qLAT

FILE

|
t

DCDR

|»~

X 36

LAT

CD DEST<3>

|SA

{

B CLK L,H
A

FILE

C WADDR<2:0>

S1-¢

IIA

INH FILE WR<3:0> H

PAR<3:0>

C WRITE
DATA PORT

RADDR

B<4:0>

SCLD-282

Figure

2-4

File

(RGF)

Block

Diagram

Data

Memory

2.2.2.2

Registers -- All MD registers are set

(MD)

valid in the first microinstruction of a new macroinstruction.
However, an individual MD register may be invalidated by the first
re

in val i

—de o~

o LC

}-l-

microinstruction.

may

A
read

and

R
wr

ated.

invalid MD register expects that cache will eventually perform
An
a write to the location and the register cannot be used until the
in one of two
cache write is no longer pending. This is determined
,
ways:

in the

MD register.

Cache has written its result

)

A trap occurs where cache informs the microcode that the
requested data will not be written (no writes are pending
to

peeds

the MD register).

2.2.2.3 Traps and Stalls -- A trap takes priority over a stall.
In the first case above, the MD register becomes valid and can be
MD will not be valid until the
the
the second case,
In
used.
a new
case,
either
1In
ction.
macroinstru
new
a
of
beginning
macroinstruction cannot be started until there are no cache writes
pending

RGF

signals

the MD registers.

write

must

normally

starts

at T9.

However, the write enable

delayed. The write enable for the cache side is

by one latch. The write enable for the W
<cycle
one-half
delayed
bus side is delayed by one cycle by two latches.
Table

2-7

(RGF)

Address Allocation

Location

0-D

General-Purpose Registers

E
F
10-12
13-17

18-1E
1F

GPR Stack Pointer
Memory Write Data Temp
Memory Management Temps
Scratchpad Registers

(GPRs)

Memory Data (MD) Registers
MD Memory Mangagement Register

VII

2-16

Table

Signal

Name

A-Port

Data

File

(FILE
File

Read

PAR<3:0>

Address

(FILE
File

Read

B<4:0>

data

Byte

parity

A-port

Bus

Data

Bus

Data

Write

(W
W

Bus

BUS
Bus

Bus

data

Byte

parity

B-port

from

the

bits

read

the

RGF

from

the

RGF

for

B-port.

the

RGF

TI10

Té

data.
of

the

and

the

Address

Write

for

A-port.

data.

Concatenation

PAR<3:0>

(WRTEN<3:0>

bits

RGF

microword
from

E BPORT<4>

BSIDE

the

from

READ

microsequencer.

Signals

Parity

(W WADDR<4:0>

the

READ ADDR<4:0>

Read

Write

(W BUS<31:00>

from

read

ADDR<3:0>
W

Valid

PAR<3:0>

Address

(RADDR

Descriptions

Signals

Parity
B

Signal

microsequencer.

Data

Read

ASIDE

B<31:00>

(FILE
Read

Data

(RADDR A<4:0>

File

(RGF)

Parity

File

Signals

Data

B-Port

Description

A<31:00>

(FILE
Read

2-8

Enable

data

same

bus

from

slice

the

byte

parity

same

slice

module.

FILE

WRITE

ADDR<4:0>

decoder

(DEC)

E_WRTEN<3:0>

logic

bits

from

the

module.
from

VII

PAR

module.

2-17

the

microword.

Table 2-8

Signal Name

Description

Valid

Inhibit File Writes

BLOCK WRITES<5:2> from the

T10 tc Tleé

(INH FILE WR<3:0> H) microsequencer inhibit byte

writes to the RGF during a trap

shadow.

Valid from T1l0 to T1l6 of

the trapping

instruction.

RGF writes occur at T9,

therefore:

trapping instruction
the
of
- T11l
first microthe
of
T9
blocks
instruction in the trap shadow

- T13

blocks

- T15

blocks

TO9

the

second

the

third

microinstruction

CD Bus Data Write Signals

to TI10

data path (CDP) logic.

(CD BUS<31:00> H)

IB CD MD<31:00> from the cache

CD Bus Parity

(CD BUS PAR<3:0> H)

IB CD MD PAR<K3:0> from the cache

data path (CDP)

T8 to T10

Cache Write Address

CACHE DATA DEST<2:0> on the same

T7 to T9

Cache Write Enable

CACHE DATA DEST<3> on the same

T8 to T10

CD Bus Data

(C WADDRK2:0> L)

(C WE L)

2¢2.3

The

logic.

slice module.

Siow Data File {(SDF)

microcode

uses

the

SDF for the following types of register

functions:

)
®
®
®
®
)

Figure

Page table base registers
Error registers
Stack pointers
Masks
Constants

Additional scratchpad locations

2-5

is a block diagram of the slow data file (SDF) logic,

which provides 256 32-bit registers with byte parity.
Table 2-9 describes the SDF read and write signals.

VII

2-18

2.2.3.1
is
CLK

Writes

delayed
latches.

SHR

Reads

occur

SDF

write
next

followed

the

CLK)

read

after

Stalls
is

During

and

T10,

occurs

the

T7,

and

data

latches

CLK

STALLED A

and

from

the

and

are

modified
same
then

the

CLK)

which

the

main

the

inhibited

CLK

T10.

location,

the

corresponds

second,

address

trap,

ALU

and

gated

during

For

the

of the third.
reading microinstruction,

Traps

The

latches

stall

writes

the

are

trap

disabled

routine

can

when

wuntil

begin,

later.

the

stall

first

microcycles

SDFWRT
L

SDFWRT L —qgB
W BUS PAR <3:0>
W BUS<31:00> H

SDWRTEN L —dg

ADDR<7:0> L

LAT

LAT
1

SA :>J B
LAT:)—-—C

SDFWRITE

LAT

b—

|SDF RAM
256
X 18

—SDF<31:00> H

DATA

SDF

LAT
B

LATP—1

SDFWRT L

’—Q

2-5

Slow

Data

File

VII

2-19

(SDF)

PAR<3:0>

ADDR
WR EN

SDF WR CLK L —
Figure

write.

SDF

and

microcode

asserted.

microinstruction

TS5

T8.

the

address

sets

during

read
at

SDF

two

occurs

write

the

cycles

W bus
read

microinstruction,

2.2.3.3
signal

the

through

asserted

An SDF
SDF RAM,.

from

write,

the

which

Therefore,
three

write,

performs

cycles

SDWRTEN

2.2.3.2

Reads

two

received

directly

for

SCLD-283

Block

Diagram

Table 2-9

Slow Data File (SDF)

Signal

Signal Name
Output

Descriptions

Description

valid

Read data from the SDF RAM 1is

TS5 to T7

Signails

SDF Data

(SDF<31:00> H)

multiplexed and asserted to the
FB

SDF Parity

(SDF PAR<K3:0> H)

SDF Write Signals

the main ALU as

B-side of

SDF<31:00>

Byte parity from the SDF RAM is

asserted to the PAR parity check

T5 to T7

inputs.

The SDF write enable signal

(SDWRTEN L) from the IBox 1is
delayed one cycle and asserted
to the PC trap logic as SDFWRITE L.
There, it is gated with an

extended trap signal and returned
to

the SDF

logic

SDFWRT L.

Under control of the PC trap logic,

SDFWRT L selects either the read or

write address and

is valid from T9

to Tll. It is delayed by a half
cycle and sent to the clock

distribution logic as SDFWR L
where it is gated with A CLK to
form the SDF write clock SDF WR
CLK L, which is valid from
T10

T12.

VII

2-20

T8 to TI10

Table

2-9

.Signal
Signal

Name

Input

Signals

Slow

Address

ADDR<7:0>

E_BPORT<7:4>
and

Bus

parity
the

Bus

BUS

Parity

PARK1:0>

PAR

SDF

Write

(SD

WRT

Enable
L)

READ

RAM

data

the

T10

microword

ADDR<3:0>

ALU

from

output

data

the

write

inputs.

source

parity

from

SDF

outputs

the

the
RAM

inputs.

Asserted

microword.

address
with

concatenation

module.

latched

logic

write

from

error

SDF

W bus
H)

(DEC)

Asserts

BUS<31:00>

BSIDE

decoder

Write

(SDF)

(Cont)
Valid

{ADDR<K7:0>

File

Description

Read/Write

Write

Data

Descriptions

E SDWRTEN
Selects

and

the

eventually gated

CLK

form

clock

(SDF

CLK

Signal

description).

VII

2-21

of the
read/write

the
L,

SDF

see

write

Output

Program Counter

2,2.4

2-6

Figure

block

(PC)

Subsystem

diagram

the

program

counter (PC)

subsystem, which contains the following main logical elements:
PC

FA Multiplexer

Virtual Address (VA) File
Trap Shadow Logic
Program Counter (PC), Backup PC,

The slice section contains four PC MCAs,

one
two

and Trap PC

each of which operates on

byte of data or address information. The SLCl module contains
MCAs. The SLCO module contains one PC2 and one PCl
type
PC2

type MCA.

The PC1l MCA operates on byte 0

(PC bits <07:00>).

Table 2-10 describes the PC subsystem input and output signals.
2.2.4.1

PC VA FA Multiplexer -- The

VA FA multiplexer connects

input of the main ALU. Its inputs are selected by
A-side
the
to
VA WRT and APORT<7:6> bits of the microword as shown in Table
the
2-11.

2.2.4.2
Virtual
Address
(VA) File -- The VA file is loaded from
and is a duplicate of the VA register on the cache
ALU
the main
VA file holds the virtual
The
module.
(CCS)
sequencer
control
cache memory. If the
to
request
transfer
data
a
for
address
a trap (a TB miss, for example), the VA file
in
results
request
contents are used for the repair and retry of the request.
Traps

When
file

a
trap
occurs,
INH VAWR from the trap logic causes the VA
to
hold its current address until the trap routine is ready

to execute. The trap logic also inhibits the VA file bypass during
the
first
microinstruction
of
a trap routine, following a trap

shadow.

In the EBox timing, micro-operations can overlap where the VA file
may
be physically read first and then written. If a VA read cycle
is
requested
immediately
after
a write cycle, the VAWRT signal
selects the VA file write input data through the VA bypass bus.

VII

2-22

Shadow

Logic

concatenated

2.2.4.3

Trap

latches

that

cause

trap

occurs.

When

from

the

1IBox,

this

logic

trap

receives

produces

cycles
that
are
wused
microinstruction of the

The

the

series

during
the trap
trap routine.
SLC1

shadow

delay

logic

1/2

global

microtrap

signals

shadow,

and

L —d

pcvAa
FA MUX |

.
PC VA FA<31:16>

VA WRT H —

VA FILE<31:30> H

OP CODE FLAG OUT L —q

H —] BACKUP

b—PRO OUT L

PC CTL<1:0>

H —] TRAP PC

PROP<1:0> L —d FC

COND BR EN H —

SDF WRITE L —q
STALLED A CLK L —d

BCOLK L —d
*NOTE:

TRAP
SHADOW

INH SDF WR H

SDF WRT L

the

cLock

PIST.

THIS SIGNAL IS PROP<2>
FROM BYTE 2 TO BYTE 3.
SCLD-284

Figure

2-6

Program

Counter

(Sheet

VII

(PC)

Subsystem

2-23

Block

succeeding

signal

pc,

PC CRY IN

GLOBAL MICROTRAP H —

when

(TWO PC2 MCAS)

FILE AsSii18>
<ol:1b> "H —m
APORT<7:6>

consists

cycles

Diagram

first

SLCO (PC2 AND PC1

FiLE

VA<15:00>
A<15:00>

APPORT<7:6>

H —
H —

L —d

PC VA

MCAS)

PG VA FA<15:005

<19:90>

\'IA<\'A'IR’? H — FA MUX — VA FILE<1:0> H
O— VA FILE2<1:0>

NEW INSTR H—

PC,

>— OP CODE FLAG OUT L *
—— PC CRY IN

PC CTL<1:0>

H— TRAP PC o—

H *

SDF WRT1/WRT L

BR EN H —
COND

GLOBAL MICROTRAP H — % — INH SDF WR H
b— SDF WRT L

SDF WRITE L —

STALLED A CLK L —4

B CLK H,L —{

*NOTE:

CLOCK

DIST

THESE SIGNALS ARE ASSERTED FROM
THE SLCG PC1 MCA TO ALL PCS2 MCAS
ON BOTH SLC1 AND SLCO.
SCLD-285

Figure

2-6

Program Counter

2.2.4.4

Program

Counter

Durin

operation,

the

(PC)

(Sheet

(PC)

Subsystem Block

Diagram

The

incremented with a

value
of
0 to 6 as determined by the decoder (DEC) module and
latched at T4 of the currently executing macroinstruction.
©PC

makes

use

1is

the following logical

functions:

)

Backup

Incrementer

Trap

Steering

Multiplexer

Incrementer

The PC is incremented by a value of
value
to
the
three
1lowest-order
with
any
preceding
byte boundary
PC<07:04>,
PCK15:08>»,
PC<23:16>,
incremented

0 to 6 by adding the increment
bits. The resulting carry-out,
propagates, determines whether
and/or
PC<K31:24>,
are
to be

VII

2-24

Backup

When

backup

macroexception
PC

The

backup

point

then

points

loaded

1is

the
to

the

during

generated,

offending
op

code

T1ll

the

code

flag

bit

so
that
the
microinstruction of
Trap

from

the

microtrap

the

correct

priority

value
a macroinstruction

the

trap

shadow.

trap

PC
It

one

return
problem.

the

occurs,

trap

the

When

that

from

the

trap PC. The backup
first microinstruction

the

beginning

cycle

the

backup

than

setting

the

lost

1is

not
causes a

PC.

new

current

Clearing
op
the

code

last

trap.

occurs,

then

trap

routine

before

backed

the

its

beginning

caused the trap). This is
microinstruction following

the

value

the

(just

the

correct state
the microcycle
the correct value

the

hardware

one

during

the

forces the PC to be
second microinstruction

reloads

the

final
microinstruction
microcode
prevent
the
from

writing

higher

restored

following

for

enables

the

The
op
code
flag
(NEW
INSTR)
signals
macroinstruction.
Set
during
the
first

macroinstruction,

code.

before

T13

new macroinstruction.

the

value

in
PC
is

the
from
not

VII

with

trap
being

changed.

2-25

itself

during

shadow.
changed

that

had

loaded

with

trap

the

the
third

and
The
hardware and
so that the return

PC Steering Multiplexer

are loaded to the PC through the steering

signals

following

The

multiplexer:

e
®

VA Bus
VA File

)

Backup PC

Trap

Table

in the

2-12

summarizes the five bits that control the multiplexer

following priority order:

LD PC INC and LD TRAP PC from the trap logic
the

PC MCAs)

Highest

COND BR EN from the decoder

E_PCCTRL<1:O>

microinstruction

produce

trap

{(DEC) module

from the microword - Lowest

that

from

{(internal to

1loads

which

a new value into the PC must not

there can be a return.

(The trap PC

the

IBox assumes

would not hold the correct value.)

improve

performance on conditional branches,

branch will succeed and sets up for the new I-stream by
that the
the new address to the VA file. Meanwhile, the microcode
writing
fail and proceeds with the
the branch will
that
assumes
microinstructions in the current sequence. If the branch succeeds,
blocking the results of the
the Trap signal,
issues
1IBox
the
a
issues
It alsc
locgic.
to branch
failure
assumed
EBoXx's
that causes the PC to be
signal
Branch Successful
Conditional
loaded from the VA file

instead of the Trap PC.

VII

2-26

Program

Signal
Signal

Name

Virtual

(PC

Address/File

Out

Address

(VA<31:00>

H)
In

the

Data

A<31:00>

A-Port

Control

(APORT<K7:6>

it.

file

Write

(VA WRT

the

main

Address

MSBs

(VA

File

(VA

File

LSBs

FILE<1:0>

from

file

bypass

APORT<7:6>

the

VA,

2-11).

Output

Signals

two

(MSBs)

most

are

the

main

the

microword

T1l1

T10

T11

for

inputs

(see

microword

the

when
and

the

Table

file

selected

file

(see

significant

used

two

least

are

enables

the

bits

sequencer

module microbranch

(LSBs)
byte

from

ALU A-side

either

The

from

PC,

E VAWRT

(SEQ)
VA

the

data

selects

The

FILE<31:30>

from

ALU.

2-11).

writes

Virtual

main

port.

select

Table

outputs

the

Valid

I_APORT<7:6>

Signals

from T7 to
microinstruction that

the

address

generates

the

A-side

VA bus.

File

Input/Output

FA multiplexer

Virtual

ALU

(FILE

vValid

A Multiplexer

File

Subsystem

Description

FA<K31:00>

Virtual

Counter (PC)
Descriptions

2-10

Table

logic.

significant

used

alignment

bits
by the IBox for
after an IB

flush.
VA
(VA

File

LSBs

FILE2<1:0>

The
L)

two

(LSBs)

least
are

significant

also

used

shifter (SHR) module
read/write data byte

VII

2-27

bits

the

for
alignment.

Table

2-10
Program Counter
Signal Descriptions

Signal Name

(PC) Subsystem
(Cont)

Description

Program Counter

(PC)

Input/Ouput

valid
Signals

New

Instruction

OP FLAG H from the decoder

(NEW

INSTR H)

(DEC) module to the PC1l MCA
on SLCO. Flags the op code
the

for

location

instruction

decode.

Opcode Flag

Issued from the PCl MCA on

(OPCODE

SLCO. Indicates a new
instruction to all PC2 MCAs
and enables writes to the

FLAG OUT L)

backup

T4 to T6

T9 to Tl1ll1

PC.

PC Carry In
(PC CRY IN H)

CARRY OUT from the
3-bit adder in the

low order
PC1l MCA to
Used with PRO OUT

T4 to T6

PC Increment
(PC INC<2:0> H)

From the IBox only to the PCl
MCA. Selects the increment value

T3 to T5

all PC2 MCAs.
(PROP<2>) and PROPK1:0> to
increment the next highest
order PC byte by 1.

(0 to
3-bit

Propogate
(PROP<2:0> L)

the

CTLK1:0> H)

select

Shadow

Input/Output

Conditional
Branch

{(see Table

(COND BR EN

T2 to T4

source.

MCA

2-12).

Signals

From the

Enable

input

internal

Used with

T4 to T6

from the microword

the PC

signals
Trap

are

byte

E_PCCTL<1:0>

PC Control

low order

A PROP bit 1s asserted by a
PC2 MCA when all eight PC bits
of

(PC

6) for the
PC1l adder.

IBox.

Used with the

GLOBAL MICROTRAP signal to
indicate that a conditional

branch

to be taken.

The new

PC value is loaded from the VA
file instead of the trap PC.

VII

2-28

T10

to T12

Table

Signal

2-10

Program Counter
Signal Descriptions

Name

Microtrap
(GLOBAL MICROTRAP

Valid

TRAP

SIGNAL

from

valid

from

T10

caused

the

following

Causes

MCA

trap

shadow:

The

functions

trap

microinstruction in
shadow. Valid from T11

T13.

file

bypass

the

file

T14.

first

trap

The

write

are

also

Write

WRITE

trap

Asserted

the

file

and

shadow

PAR

values

Valid

MCAs

during

preserve

registers,

the

parity

carry

save

Valid from T1l1l to T16
microinstruction that

carry

caused

the

trap.

Slow

Data

the

SDF

selection

File

(SDF)

from

the

IBox

goes

logic

for

each

slice

delayed

WRITE,

cycle.

asserted

logic

both

slice)

and

VII

2-29

Tll

the

latch.

the

and

SD WRT

an
from

backup

latch,

the

T12

with

during

shadow.

Write

the

T1l6

the

from

Valid

microinstruction
TI15.

during

access

loaded

inhibited

error

(SDF

the

pretrap

can

Valid

value.

T10

trap

TI15.

from

trap

is inhibited so
microinstruction

routine
contents.

T12

the

second

during

SDF

with

the

trapping

Signals

loaded
the

during

the

T13

Control

occur

incremented

Write

Tl10

contents

the

that

trap.

that

SDF

IBox

the

SDF

the

T12

microinstruction

(INH

Subsystem
(Cont)

Description

Global

Inhibit

(PC)

The
to

where
output,

the

trap

MCAs (on the same
valid from T8 to T10.

Program Counter (PC) Subsystem

Table 2-10

Signal Descriptions (Cont)

valid

Description

Signal Name

In each PC MCA, SDF WRITE is gated

SDF Write Out

with the negated state of GLOBAL

(SDF WRT L)

MICROTRAP to obtain the SDF WRT

output signal. In the SDF logic for
each slice, SDF WRT selects either
the fast or slow address for a

write or read of the SDF RAM. Valid
from T8

to T10.

From the SDF logic, SDF WRT is

SDF Write

(SDF WR L) asserted as SDF WR to the
slice clock logic. There it is ANDed
with A CLK to form the write clock
(SDF WR CLK L) for the SDF RAM.
Valid from T8 to TI10.

With GLOBAL MICROTRAP asserted, SDF
WRT and SDF WR are inhibited for
three cycles, blocking SDF writes
during a trapping microinstruction
and trap shadow. Valid from T1l0 to
T15.

E_VAWRT and I _APORT<7:6> Control of

Table 2-11

PC VA FA Multiplexer Input Selection
I APORT

<7 6>

E_VAWRT
-

Inputs

File A Data

1
1

are

Gated to the Outputs

0
0

0
1

These

VA File
VA File Bypass

PC Multiplexer Input Selection

Table 2-12

PC Multiplexer Select Signals

LD TRAP

LD PC

Backup PC

Trap PC
VA File

COND

PC CTL

BR EN
-

0
1

0
1
1

INC
0

Selected Input
Incremented PC

VA Bus

Incremented PC

2.2.5
The

Cache

Data

cache

memory

three main

logical

(CDP)

Cache

Tag

Store

Cache

Tag

Valids

Cache

Data

Path

path
For
CBox

Figure

2-7

following

CBox

consists

the

following

(CTV)
(CDP)

this manual.

block

diagram

Cache

Data

Buffer

Cache

Data

Store

2.2.5.1

Cache

cache

2-13

Data

data

which
passes
the CDS RAM.

CDBF

the

CDP

(CDBF)

MCA

logic

which

elements:

one

(CDS)

Buffer

buffer

byte

describes

RAM

MCAs

of memory or

the

make

Write

Data

Buffer

Delay-Write

Write

CDBF

the

input

following

Each

the

contains

2-7,

Sheet

1),

CPU data

and

parity

and

output

signals.

data

path

registers:

Buffer

each

from

One

longword

and

byte

parity

One

longword

and

byte

parity

One

octaword

(four

each)

Data

slice module

(Figure

Buffer

Buffer/Output

contains

logic

(CDBF)

MCAs

Write

(CTS)

Table

the

1logically
part
of
the cache memory logic, the cache data
(CDP) group is physically located on the EBox slice modules.
further
information on cache memory functions,
refer to the

section

two

groups:

While

The

Path

section

with byte

longwords,

parity

Buffer

The

write

data

buffer

data

(WR

DATA)

bus

consists
with

data

of a B-latch that
received from one

drives
of the

the write
following

sources:

The

MD bus

)

The

W bus from the
W bus, delayed

from

the

IBox
slice PAR
one cycle

VII

2-31

logic
by the

delay-write

buffer

Delay-Write

The

Buffer

delay-write

slice

PAR

buffer

1logic,

receives

passing

write

the

bus

write

(W BUS)

data

buffer

from

and

the

write

buffer.

Write

Buffer/Output

Four

36-bit

writes

the

MD BUS

buffers
the

longwords)

Buffer

1is

(data

same

and

parity)

act

The

write

octaword.

parallel-loaded

the

output

small

buffer
buffer,

cache
(all

which

for
four

drives

lines.

CACHE DATA BUFFER (CDBF)
(TWO PER SLICE)
MD BUS PTY IN<3:0>
MD BUS33 IN

(IN)

H —
H |

MCA

}

MD BUS<30:00> H N DLY WR

— WR RAM DATA PTY<3:0> H
WBUS PTY<3:0> H —J] BUF AND —— WR DATA<31:00> H
WBUS<31:00> H —] WR DATA |
B-LATCH

DLY WR LD H —
WR SEL<1:0> H —]

WR CDS<3:0> L —d

MD BUS WR EN HH —
—|

WBUF WR ADD<1:0>

WBUF WREN<3:0> H —] WR BUF
LD WR BUF L —d

AND

T
Y<3:
DATA PTY<3:0>

CDP PTY ERR<3:0> H

BUS PTY OUT<3:0> H
L » MD
MD BUS33 OUT H
>

—p MD BUS<30:00>

H (OUT)

OUT BUF
LD OUT BUF H —
RD ADD<1:0> H —

QUT |v sp| <1:05 H
DLY WR MUX SEL<3:0> H — CDP
MUX SEL
A CLK

H —

CLOCK

B CLK

H —

DIST.
SCLD-286

Figure

2-7

Cache

Data

Path

(CDP)

VII

Block

2-32

Diagram

(Sheet

CACHE DATA STORE (CDS) MCA
16K X 18 BITS PER SLICE

WR DATA PTY<3:0>

WR DATA<31:00>

LAT[ IB

MD CD PTY<3:0>

MD CD<31:00>

—

WR RAM DATA PTY<3:0> H—] CDS RAM
16K

SLC

SEL

H —|

WR CDS<3:0>

L —]

PA1<15:09> H —
PA2<15:09>
PA<08:02>

H-—]
H —{

A CLK L —g

CD<31:00>

ADDRESS

’

CACHE BYPASS H —]

OUT SEL <1:0> H—|
SLC<1:0>

A CD PAR<3:0>

CLOCK
DIST

B CLK L
WCLK H,L

DLY WR HIT

L’

X 36

popnet

SCLD-287

Figure

2.2.5.2

16K

2-7

Cache

18-bit

passes

two

Table

2-14
of

CDS
Two

Data

CDS

bytes

consists

Cache

(CDS)

set

(Figure

memory

describes
the
RAM

memory,

sets

Each

2-7,

CDS

RAM

Diagram

slice

Sheet
data

module

and

logic

(Sheet

that
byte

2-15

output

multiplexers.

the

parity.

signals.

multiplexers,

signal

VII

one

and/or

The

logic

which

uses

the

cache

data

bits

data/bypass

control

contains

stores

elements:
32K

one

outputs.

Table

shows

Block

read/write

the

following

A-latched

(CDP)

Store

RAM
of

Path

2-33

functions

for

Table 2-13

Cache Data Buffer (CDBF) Signal Description

Signal Name
Write

Description

Data B-Latch Outputs

Write Data
(WR DATA<31:00> H)

Carries the write data B-latch contents
to the CDS RAM and to the EBOX and
The B-latch is loaded from one
IBox.
of the following data sources
(depending on the states of WR
SEL<1:0>):

The received W BUS value
The delay-write buffer

The received MD BUS value from the
CBox

Write RAM Data Parity
(WR RAM DATA PTY<3:0> H)

Carries the write data B-latch byte
These
parity bits to the CDS RAM.

B-latch bits are loaded with the byte
parity value from the selected data
source.

Write Data Parity

>
(WR DATA PTY<3:0H)

With WR CDS<3:0> negated, byte parity
errors are inhibited from CDP PTY

ERR<3:0>. Byte parity is generated on
the B-latch contents and asserted on WR
DATA PTY<3:0>

to the

EBox and

IBox.

With any WR CDS<3:0> bits asserted,

the

selected write data B-latch byte parit

bits are asserted on WR DATA PTY<3:0>.
Byte parity errors are reported on CDP
PTY ERR<3:0>.

CDP Parity Error
(CDP PTY ERR<3:0> H)

Byte parity is generated on the B-latch
contents and compared with the byte
parity bits from the data source.

With

any WR CDS<3:0> bits asserted, selected
byte parity errors are reported on CDP
PTY

ERR<3:0>.

VII

2-34

Table

2-13

Signal

Name

Inputs

Memory

Data

(MD BUS33

Cache

Data

Buffer

(CDBF)

Signal

Description

(Cont)

Description

the

Delay-Write

Bus

Buffer

and

Asserted

Write
from

Data

the

write

data

written

B-Latch

CBox

B-latch.
the

CDS

bit

From

RAM

<31>

there,

DATA<K31>.

Memory

Data

Bus

(MD BUS<30:00>

Memory

Data

(MD BUS

PTY

Write

Bus

(In)

Bus

Data

bidirectional

data

Parity

IN<3:0>

(W BUSK31:00>

The

the

Memory

data

passed

ALU

from

data

parity

the

pass

the

from

write

asserted

received

lines

CBox

the

data

delay-write buffer
write data B-latch

CBox

PAR

and

to the write data B-latch
delay-write buffer.
The
the

data

B-latch.

the

W bus

memory

write

logic

asserted

and

the

is asserted to
and the write

buffer.

Write
(W

Bus

BUS

Parity

PTY<3:0>

Byte
H)

(on

parity
the

bus.

B-latch

along
The

generated

ALU data)
is
and

with

1is

asserted
the

the

received
to

the

delay-write

PAR

logic

the W

write

data

buffer

write data.

delay-write

buffer

parity

bits

are

asserted to the write data B-latch and
the write buffer along with the write
data.
Delay

Write

(DLY WR

Load

LD H)

Asserted,

clocked

causes

the

received

W BUS

data

It is written on the following cycle
the write data B-latch or the write
buffer.

VII

2-35

delay-write buffer.
to

Table

Signal

2-13

Cache

Data

Name

Buffer

(CDBF)

Signal

Description

(Cont)

Description

Write Select
(WR SEL<1:0>

Select

one

of the following data and
input sources for the write data

parity

B-latch:
il

SEL

Cache

Data

Store

Delay-write

W bus
there,
or

Control
CDS

Data

Memory

Data

(MD BUS

Data

Bus

(MD BUS<30:00>
Memory

CDS

writes

byte

parity

Byte

parity

from

CDP

Asserted,

the

write

bits

are

Byte

reported

Asserted

from

generated

asserted
errors

the

DATA

are

PTY ERR<3:0>.
data

B-latch

asserted
parity

CDP

PTY

errors

byte

DATA

are

ERR<3:0>.

Outputs

Bus

OUT

written

IBox.

checking

contents

PTY<3:0>.

BUS33

the

inhibited

parity

(MD

data

parity

PTY<3:0>.

Memory

the

RAM.

Negated,

Buffer

buffer

bus

passed

B-latch

Output

Source

RAM

(WR CDS<3:0>

Data

From

Write

Bus

buffer
{Out)

H)
Parity

PTY OUT<3:0>

the

bit

<31>

The

bidirectional

lines

the

output

buffer

from

the

Byte

parity

passed

VII

2-36

the

output

CBox.

the

pass

data

from

CBox.

output

buffer

Table

2-13

Signal

Name

Write

Buffer

Bus

Cache

Buffer

(CDBF)

and

Output

Enable

Buffer

Asserted,

for

the

Buffer

Write

WR ADD<1:0>

bits

NMI

(Selects

Buffer

Write

Load

WREN<3:0>

Write

(LD WR
Load

(LD

Output

OUT

Buffer

BUF

passed

paths

bus

The
on

the

Output

Delay

specified

Write

buffer

bytes

buffer

PA<3:2>.)

Writes

write

the

buffer

selected
delay-write

buffer bytes from
during A CLK.

Causes

all

four

write

written

buffers

the

after

output

write

buffers

Multiplexer

the

NMI

the

CBox.

the

selected

the

NMI

Selects

one

for

assertion

the

data

NMI

four

paths

on
the

one

CLK

write

output
writing

data

32-bit

paths

output

the

MD BUS

CBox.

Control

for

through

buffers

Passed

Select

(DLY WR MUX SEL<3:0>

BUS

of four 32-bit write
for a write operation.
the longword within an

Buffer

Write

Multiplexer

and

CBox.

Read

CDP

data

the

buffer. Deasserted, causes
buffer data to be held for

Address
(RD ADDK1:0>

drivers

byte mask.
Enables valid
be written from the
delay-write buffer to the selected
write buffer.

Enable

(WBUF

(Cont)

one

octaword

Write

the

buffer.

are

data

registers

enables

output

Selects

Address

(WBUF

Description

Inputs

parity

Write

Signal

Description

Write

(MD BUS

Data

the

slice

signals

Output Select A
SEL A<1:0>) and Output
slice 0 (OUT SEL B<1:0>)

(OUT

Select

CDS

RAM

output

These

bits

are

driven

write

valids.

the

cache

Used

DLY

the

make

work

VII

for

delay

one

2-37

write

cycle

multiplexer.

by
with

hit/read

(see

Table

HIT

cycles

2-14).

SLC

Table 2-14
Signal

Cache Data Store (CDS) Signal Description
Description

Name

CDS Multiplexer Output Signals
Cache

Data

The

Bus

(IB MD CD<31:00> H)

CDS

RAM data outputs

are output

through an A-latch multiplexer to the
IBox and the register file.

Write data from the WR DATA bus

asserted for a bypass when a write is
immediately followed by a read to the
location.

same

Cache Data Bus Parity
(IB MD CD PTY<31:00> H)

The CDS RAM parity cutputs are output

through an A-latch multiplexer to the
IBox and the register file along with
the

data.

Parity from the WR DATA bus is asserted
for a bypass when a write is
immediately followed by a read to the
location.

same

Cache

Data

Bus

(A CD<31:00> H)

The

CDS

RAM data

outputs

are

multiplexed and passed unlatched to the
A-side and B-side of the main ALU first
half

(ALF).

Write data from the WR DATA bus is
asserted for a bypass when a write is
immediately followed by a read to the
same

The

location.

CDS

RAM parity outputs

are

multiplexed and passed unlatched to the
A-side and B-side of the main ALU first
half

(ALF).

Parity from the WR DATA bus is asserted
for a bypass when a write is
immediately followed by a read to the
same

location.

Table

RAM

Write

Slice

DATA

Description

(Cont)

the

write

CDBF

data
the

B-latch

CDS

output multiplexers

(see

Passes

the

data

parity

bits

from

the

write

data

write

RAM

contents

and

Table

the

2-13).

B-latch

CDBF

the

byte
CDS

RAM,

Passes

Parity

PTY<3:0>

Select
SEL H)

B-latch

byte

parity bits, or the byte parity
generated on the write data B-latch
contents, from the CDBF to the output
multiplexers.
(See the WR CDS<3:0>
description, Table 2-13.)

Negated,
selected

Physical

Address
(SLC PA

Signal

Input Signals

from

Data

DATA

(CDS)

Passes

Data

Parity (WR RAM
PTY<3:0> H)

(WR

Logic

DATA<K31:00>

Write

Store

Description

RAM and RAM

Write

(WR

Cache Data

Name

Signal

CDS

2-14

the
for

PA2<15:09>
addressing

PABH address
the CDS RAM.

Asserted, the PA1<15:09> and PA<08:02>
fast TB addresses are selected for
addressing the CDS RAM.
Write
(WR

Used with

CDS

CDS<3:0>

produce

write

the

clock

byte

(W CLK)

write

pulses

for

bits

<15:09>

CDS

RAM.

Physical

Address

(PA1<15:09>

Physical Address
(PA2<15:09> H)
Physical

Address

(PA<08:02>

from

the

physical address high buffer
the translation buffer (TB).

Physical

(PAHB)

Physical address bits <15:09>
fast address register.

from the

Bits

latch

VII

address

<08:02>

from the

2-39

the

virtual

address

fast

address

Table 2-14

Cache Data Store

(CDS) Signal Description (Cont)

Description

Signal Name
Output Multiplexer Control
TIrs

CACHE

BYPASS

Asserted, enables WR DATA bus inputs
directly to the output multiplexers.
Passes
to

BUS

Delay Write Hit
(DLY WR HIT SLC

Slice
L)

CDS
the

RAM write
IBox.

data

from

the

Asserted for the slice on a match
between delay-write address bits
<15:02> and the corresponding address
of the current cycle. Used with DLY WR
MUX SEL to assert read data from the
delay-write buffer instead of CDS RAM
when a write is followed by a read to
the same location (cache is not yet
Enables the WR DATA bus
updated).
inputs directly to the output
multiplexers (valid only when OUT SEL
A,B<1:0>

equals

01).

Output Select A/B

Selects WR DATA bus or CDS RAM data for

(OUT SEL

output from the CDS output
multiplexers. OUT SEL<K1> controls the
upper byte and OUT SEL<K0> controls the
lower byte for each slice (see Table

<1:0> H)

2-15).

Table 2-15

CDS Output Multiplexer Control for Each Slice

CACHE
BYPASS

DLY WRT
HIT SLC

OUT SEL
<1> <0>

Selected Input Asserted from
the Multiplexer Output Bytes
Lower Mux Byte
Upper Mux Byte

RAM

Data

CDS

RAM

Data

CDS RAM

Data

CDS

RAM

Data

CDS RAM

Data

WR DATA Bus

CDS

WR DATA Bus

WR PATA Bus

WR DATA Bus

CDS

VII

2-49

RAM

Data

2.2.6
Main Arithmetic Logic Unit
Figure
2-8
shows
the
main
ALU
following two types of MCAs:
1.

ALU

First

Half

(ALF)

(Main ALU)
1logic,

Four

ALF

process

Second

Half

(ALS)

Two

per
(1

with

slice.

nibble)

Each

result

carry

data,

MCAs

byte

the

per

slice.

data,

function

final

Each

completing
and

output-

result.

2-16

describes

the

ALF

input/output

and

control

signals.

Table

2-17

describes

the

ALS

input/output

and

control

signals.

part

ALU

First

add

partial

result

information
ALF

chips

bits

The
the

byte

following
ALF,
PC

where

the

ALS

passes

form

the

ALS

uses

nibble

Bus

apply

data

RGF

the

processes

operation.

the

first

passes

the

carry

the

operation.

Each pair

ALS

chip,

combines

the

A-side

generate/propagate
which

and/or

internally latched

File

Data

Bus

stage

(SUB)

with

complete

parity

data,

and

applied

coming

and

virtual

information

subsystem
CD

ALF

subtract

along

counter

The

parity.

buses

Bus

(ALF)

(ADD)

the

Half

the

propagate/-

Table

2.2.6.1

the

information.

arithmetic

ting

consists

partial

ALS

process
an

bits

along

generate
ALU

MCAs

passing
ALS

which

from

the

address,

preselected

the

B-side

selected:
or

program

the

A-side.
bus

bus

for

writing
to
store
(CDS)

cache,
and is

bypasses
the
applied to the

cache data
A-side and

Bypass

data

applied

the

A-side

and

applied

bus

B-side.
IB

Data

SDF

Bus

Instruction

the

A-side

RGF

File

Buffer

and
B

multiplexer

and

VII

information

B-side.
SDF

data

applied

2-41

the

preselected

B-side.

A-Side Input Select (ASEL<1:0>)

11:10><09:08>
Each pair of the port control bits (PORT CNTL<
) selects
<03:02><01:00> from the bus watcher MCA on the DEC module
one A4-bit field on the A-side of an ALF MCA as shown in Table
B-Side Input Select (BSEL<1:0>)

13:12>
Each pair of the port control bits (PORT CNTL<15:14><
s
select
)
module
DEC
the
on
MCA
r
watche
<07:06><05:04> from the bus
Table
in
shown
as
MCA
ALF
an
of
B-side
one A4-bit field on the
2-19. BSEL<2> (EBRDMODE from the microword) selects data from
either the RGF File B or SDF lines.
Stalls

All
bus

CD
of the main ALU A latches may be stalled except for the A ts
e asser
input latches. The bus watcher MCA on the DEC modul
ter valid (MD

the cache data ready (CD READY) and memory data(CDregis
VALID) signal is
VALID) signals while the cache data valid
As shown in Table 2-20, these signals are
asserted by cache.
whether the CD
encoded into the KEEPGOING signal, which determines
latches stall for either side while the other side is waiting for
data.

They also determine when the stall will be released.

VII

2-42

ALU

FIRST

HALF (ALF)

(FOUR

PER SLICE)

MCAS

ALU

SECOND HALF
(TWO PER

PORT CNTL

APS<31:00>

FA<31:00>

H —

A-SIDE

APORT DATA<31:00> H
|

APS<31:00>

A CD<31:00> H —]
FILE

ev-¢ IIA

<31:00> H

—1

BUS<31:00>

SDF<31:00> H—0
B RD MODE L

IB DATA<31:00> L —9
<
FB SDF

<31:00>

15:12,07:04>

H—]

E_ALU<5:0>

H—]

ACLK L _d

B CLK L —d

GNIB<3:0>

L—o

PMOD<1:0>

DCDR

0— PNIB<3:0>

H
H

—

— CBIT<2:0>

— VBIT<2:0>

| FPOP

— FAST

NORM BIT

MOD NUM L —o
B

— BP<31:00>

—

STALLED CLK L —o0

b— GNIB1<3:0> L
b— GNIB2<3:0>

BPOUT EN
E_ALU<5:0>

BPORT PAR<7:0> H,

Func.

L —o

GMOD<1:0> L —o

— BPORT DATA<31:005 H

EFF SUB H —

KEEPGOING<1:0>

BPS<31:00>

B-SIDE

E_ALUCON H —

STALLED A CLK L —q

L —0

H —
CIN

H —|

PORT CNTL

PNIB<3:0>

MCAS

VA PAR<3:1>
— VA<31:00> H

H——

H ]

PC VA

(ALS)

SLICE)

CLK

L—o

CLOCK
DIST.

H —
PNIB<3:0>

—o LOOK-

}— GMOD<1:0>

L PMOD<1:0>

—— BCD DIGIT

OK<1:0>

AHEAD

GNiIB1<3:0> L — ;;K
GNIB2<3:0>

—

CHECK

H
SCLD-288

Figure

2-8

Main Arithmetic Logic Unit
(Main ALU) Block Diagram

2.2.6,2

addition

Main

(ADD)

ALU

and

-- The main ALU logic performs
(SUB) of the following types of
subtraction

Functions

numbers:
®

°
®
ALU

Integer

Floating—-Point
Packed Decimal

Function Control

1lists the ALU functions that take place under control
2-21
Table
from the microword and are used to perform the
EALU<5:0>
of
following kinds of operations:

Performs a floating—-point mask of A-side data.

Generates Integer and Floating-Point carries.

Generates
on

byte,

microcode

)

Generates
is

Overflow (V) and Carry (C) condition code bits

word,

and longword boundaries (ignored by the

if not relevant).

checked

nibble parity on A-side and B-side data, which
against

the source input data parity in the

PAR.

Outputs

the

ALU data or result on the VA bus and BP bus

(when enabled by BPOUT EN).

Table

Signal
Data
A

Partial

Signals

Data

Partial

Port

(BPORT
B

Port

(BPORT

Data

Signals

Sum

Data

the

Parity

Signals

PAR

File
(FB

Signals

B/Slow

Data

SDF<31:00>

A-side

input

T6é

(SHR)

module.
T6

parity
A-side

the

generated
input

same

data

on
to

slice.

ALS

data

partial

the

sum

slice.

selected

B-side

input

shifter

(SHR)

module.

the

nibble

the

selected

the

PAR

B-side

same

parity

B-side

the

same

generated

input

data

slice.

- A-Side

Input

B-Side

From

FA<31:00>

shifter

the

Passes

PARK7:0>

sum

selected

nibble
on

A-side

slice.

the

A-side,

File

subsystem

selects

information
Data

Descriptions

same

selected

Passes

the

Multiplexer

(PC

Signal

Valid

partial

Passes

DATA<31:00>

Input

data

Passes

PARK7:0>

(BPS<31:00>

ALS

Passes

Parity

Output

(ALF)

A-Side

the

Data

Half

Passes

DATA<31:00>

Port

Sum

(APORT

First

Description

Output

Port

ALU

Name

(APS<31:00>
A

2-16

PC,

VA,

(see

Table

data

from

the

2-11).

B-Side

Multiplexed
File

selected
from

SDF
by

the microword

VII

2-45

the

RGF

data outputs,
RD MODE (EBPORT<8>
(see

Table

2-19).

Table

Signal
Data

2-16

ALU First Half

Name

Input Signals

Signal

Descriptions

(Cont)

Description
- A-Side

A Cache Data
(A CD<31:00> H)

Bypass

(ALF)

Bus

(BP BUSK31:00> H)

valid

and B-Side

to T7

data

to T7

A-Side -- Each pair of the PORT
CNTL bits <11:10><09:08><03:02>

to T7

EALUCON from the microword, when
T5
asserted, forces a constant of 4
to be read by the least significant
nibble on the B-side and a value of
0 by all other ALF MCAs.
(A value
of 0000 0004 is read from the B-side
instead of the data input value.)

to T7

From the unlatched CD multiplexer.
Inputs cache read data or cache
write/read bypass

data.

Driven

the

ALS

an ALU on

the

SHR module; inputs to the PAR to
become the W bus.
Inputs directly
to the ALF in order to bypass the
W bus

when

accepting

data

from

the

SHR.

(IB

Data

Bus

DATAK31:00> L)

Control

Instruction

from

the

buffer

operand

IBox.

Input Signals

ALU Port Control
(PORT CNTL<15:00> H)

<01:00>

from

the

the A-side byte
(ASEL<3:2,1:0>,

DEC module

selects

inputs for the slice.
see Table 2-18.)

B-Side -- Each pair of the PORT
CNTL bits <15:14><13:12><07:06>
<05:04> from the DEC module selects
the byte inputs for the slice.
(BSEL<3:2,1:0>). B RD MODE is
EBPORT<8> from the microword
(see Table 2-19).
ALU Constant
(EALUCON H)

/11

2-46

Table
Signal

ALU

First

Name

Function
ALU

2-16

Decode

Function

(EALU<3:0>

Half

(ALF)

SUB

EALU<3:0> from the microword
control the ALF partial sum

carry generates to the ALS
logic on the same slice.

to T8

carry

T6é

Signals

Control

Subtract

ALS

Nibble

converts

Generate

Nibble

(PMOD<1:0>

2-21).

add to a
partial sum.

the

ALS

Module

the

ALS

(PMOD<1:0>

word

MCAs

are

Cross-module

propagates

logic

Cross-module

(GMOD<K1:0>
signal.)
Propagate

an FP
the ALF

look-ahead

Module

(GMOD<1:0>

with

Table

look-ahead

Nibble

{PNIB<K3:0>

(see

a Floating-Point Shuffle
operation.
A special case

(FPS)

that

Propagate

conjunction

Indicates

(GNIB<3:0>

functions

subtract
Generate

(Cont)
Valid

functions

(EFF

Descriptions

Description

the

Effective

Signal

other

fanout

are

carry

ALS

slice.

generates

the

word

MCAs

the

same

carry

the

slice.

the

same

propagates

the

other

fanout

slice.

the

same

signal.)
BCD

DIGIT

<K1:0>

Indicates

a
Clock

Distribution

KEEPGOING<K1:0>

valid

that

the

decimal

nibble

contains

digit.

Control
Asserted

the

A-side

latches

during

open

stall.

B-side
until

available.

VII 2-47

Holds

A CLK

the

expected

data

Table 2-17

ALU Second Half (ALS) Signal Descriptions

Signal Name

Description

valid

Virtual address to the Cbox.

T7 to T9

Output Signals

Virtual Address Bus
(VvA<31:00> H)

Virtual Address Parity Virtual address parity to the

T7 to T9

(VA PAR<K3:0> H)

Cbox.

Bypass Bus
(BP<31:00> H)

Bypass bus data from the ALS
or the SHR module inputs directly

Carry Bits

Carry (C) bits from ALF bits

T7 to T9

Overflow (0O) bits calculated on

T7 to T9

(CBIT<2:0> H)

Overflow Bits

the

PAR and ALF

MCAs.

<31,15,07>.

and longword

(VBIT<2:0> H)

byte, word,

Floating-Point Opcode

Indicates that the current

(FPOP H)

T7 to T9

boundaries.

instruction is floating-point.

T6 to T8

Controls the carry save logic
in the
on the

next higher byte
same slice.

PAR MCA

Fast Normalize Bit (FAST NORM BIT H)
Input

Signals

A Partial Sum

Partial sum nibble inputs from

T6 to T8

(APS<31:00> H)

the ALF A-side.

B Partial Sum

Partial sum nibble inputs from

T6 to T8

Carry In
(CIN H)

Carry input from the next lower
byte PAR MCA on the same slice.

Té to T8

Bypass Output Enable

EALENBP from the microword.

Té to T8

(BPS<¢31:00> H)

(BPOUT EN H)

ALU Function Control
(ALU<5:0>

Module Number
(MOD NUM L)

the ALF B-side.

Enables the selected ALS outputs

the

bypass

bus.

EALU<5:0> from the microword.

Selects the ALU function to be
performed (see Table 2-21).

Hardwired high or low.
the

slice

for

VIT 2-48

each

ALS

Identifies
MCA.

T5 to T7

Table
ASEL

2-18

A-~-Side

Select

Input

<2,0>

Selected

DATA

Table
RD

2-19

Bus
Bus

Bus
CD

B-Side

Bus

Select

(BSEL)

Input

Control

Signals

BSEL Bits
<3,1>

SDF

<2,0>

Selected

Input

RGF

DATA

bus

Bus

data

2-20

Keepgoing/Stall

Table

Data

data

File

Bus

data
data

data

Conditions

CD Vvalid

CD Ready

MD Vaiid

Keepgoing

1
-

1
0
0

Keepgoing,

Signals

Data

MODE<2>

Input

Control

Bits

<3,1>

(ASEL)

Note:

Stall.

VII

2-49

State*

EALU<5:0> Field Control of the Main ALU

Table 2-21
EALU<5:0>

ALF Results

BPS

Carry Enable

A+B+Carry (FP, no mask) AorB

-{AandB)

APSandBPS, 1

AcrB

- {AandB)

APSandBPS,

(G mask)

AorB

-(AandB)

APSandBPS,

A+B+Carry (H mask)

AorB

- (AandB)

APSandBPS,

A-B-1+Carry

- (-AandB)

-(Aand-B)

APSandBPS,

-(-AandB)

-(Aand-B)

APSandBPS,

APS

Value

General ALU Function

00
01

A+B+Carry {(F & D mask)

A+B+Carry

(FP,

no mask)

A-B-1+Carry

A-B-1+Carry (G mask)

- (-AandB)

-(Aand-B)

APSandBPS,

A-B-1+Carry

(H mask)

~-{-AandB)

-(Aand-B)

APSandBPS,

2's Compl. A

-A

APSandBPS,

D mask)

(0-A-1+Carry)

A+B+Carry Integer

AorB

- (AandB)

APSandBPS,

A-B-1+Carry Integer

- (-AandB)

-(Aand-B)

APSandBPS,

BCD 1lst Cycle Add

- -

APSandBPS,

Inc A (A+Carry)

APSandBPS,

Inc B (B+Carry)

APSandBPS,

B-A-1+Carry

-(Aand-B)

-(-AandB)

APSandBPS,

BCD 1ist Cycle Sub

- -

APS5andBP5,

AorB

-(AandB)

APS

notAandB

-(-AandB)

- (Aand-B)

-APS

Pass A

APS

BCD 2nd Cycle

AorB

- {AandB)

APS

Pass B

APS

Aand.notB

- {Aand-B)

-(-AandB)

-APS

notA

-A

APS

AandB

AorB

-{AandB)

-BPS

AxXorB

AorB

-(AandB)

APSandBPS,

Force VA parity

APSVA

Clear

Dec.

-A

Integer

to O

(A-Carry)

VII

2-58

PAR=0,

-BPS

-APS

2.3

SHIFTER MODULE

The

SHR

additional
with
64-bit

main

operand

result

operators

and
ALU

the

(BP)

the

Shifter

Floating-Point

shift
shows

the
the

Figure

2-9

identifies

in
16

parallel
a

the

32-bit
logical

(FP)

Support

(MULT)

(SHF)

set

SHR processes
returns

Priority Encoder (PEN)

The
and

Shift ALU (SALU)
Exponent ALU (XALU)

also

providing

connected

(SHF)

Shifter

through

shows
from

bus.

slice modules,
are

lines

the

that

modules.

shifter

shows

SHR:

Multiplier/Divider

2.3.1
The

SLC

APORT/BPORT

bypass

provided

DESCRIPTION

extension

MCA operators

)

ALUs

the

(SHR)

functional

contains
MCA (SHFT)

the
of

output

NOR

gates

shift
control
microcode
that

two types of MCA logic.
logic, which consists of
gating

located

that
on

MCA (SHC)
control

drives

the

Figure 2-10
eight MCAs.
BP bus

SHR module.

lines

Figure

2-11

signals and two other signals
the SHFT MCAs. The SHF shifts

integer
or
floating-point
data
and
provides
several
other
functions,
one
of which is to perform direct conversions between
some

perform

the
the

decimal

following

Logical

Shift

Arithmetic
Decimal
FP

string

formats.

Its

main

hardware

functions

operations:

Rotate

Shift

String

Conversion

Normalize

FP Align
The

that

SHF

mainly

also

available.

operand

and

For

applied

lower

different

processes

apply

32-bit

the

bits

64-bit

32-bit
data,

APORT

operands

but

operands.
or

the

several

32-bit

functions

output

the

result

1is

selected

BPORT.

For

64-bit

data,

result

cycles.

VII

has

Only

2-51

are

gated

the

for

the

is
the

upper

BP bus

BP BUS «
<31,07,

05:00>

SHIFTCD

APORT

SHIFTER

BPORT

—>

(SHF)

HIFTAB

@—’

SHFTCNT A LATCH

SHFTCNT BUS

_p{ PRIORITY

<25:24>,|

ENCODER
»' (PEN)

- >

[—=23:18>

—p
UCODE

SHFTCNT
BUS

—»
p|

SHIFT

ALU

(SALU)

»| EXPONENT
L

ALU

P (XALU)

XALU OUT

MULTIPLIER/

TM DIVIDER
(MULT)

MULTRES

SCLD-289

Figure

2-9

Shifter Module

VII

2-52

(SHR)

Block

Diagram

SHIFTER

APORT<31:24>

BPORT<«31:24>

MCAS (SHFT)

OR GATES (SHFT)

1
1g- 24>
> SHIFTAB1<31:
McA ob

1
L

SHIFTAB1<15:08>

NOR GATES

(SHR)

flH!FTAB<31:24> L

SHIFTCD<31:24>

BP BUS<31:24>

>— BCD ZONE OK2 L

MCA 1

SHIFTAB2<23:16>

L, SHIFTAB2<07:00>

SHIFTAB<23:16>

SHIFTCD<23:16> LflD‘BP BUS<23:16> H
Wmmeas:o& L

smmcsas:o&SD' BP BUS<15:08> H

SHIFTAB<07:00>

APORT<23:16>

MCA
2
BPORT<23:16>

SHIFTAB1<23:16>

. SHIFTAB1<07:00>

H
Po— BCD

ZONE

OK1

_SHIFTAB2<15:08>

MCA 3b

SHIFTAB2<31:24>

BPORT<15:08>

SHIFTCD1<15:08>

L
|

BCD ZONE OK H

OR GATES (SHFT)

H
>— BCD ZONE OK2 L
SHIFTCD2<07:00>

MCA 5b SHIFTCD2
I
<23:16>
:

MCA
4

BCD ZONE OK1

BCD ZONE OK3 L

SHIFTCD1<31:24>

B8C0 ZONE OKZ
-

APORT<15:08>

SHIFTCD<07:00> LHD’ BP BUS<07:00> H

SHIFTCD<31:24>

SHIFTCD<23:16>

[OD—

APORT<07:00>

BPORT<07:00>

MCA
6

SHIFTCD1<07:00>

SHIFTCD1<23:16>

o— BCD ZONE OK3

SHIFTCD<07:00>

SHIFTCD2<31:24>

S SHIFTCD2<15:08>

@—\ SHIFTCD<15:08> L

SCLD-290

Figure

2-10

Shift

MCA

(SHFT)

VIT

Logic

2-53

and

Gating

Block

Diagram

> 10 ALL SHFT MCAS

E_SHFTFPOUT<1:0>H

E_FPFORMAT<1:0> H

APORT<16> H —

BYPASS BUS<31>

S'GN
LOGIC

CQINAI Ul
. DiI\alN
[}

H—

BLOCKEDWRITE<0> H ——

SHIFT CNT BUS<5:0>
BYPASS BUS<05:00>

SELECT

SHIFT COUNT

T
AA W
N

H ——

E_SHFTCNTEN<2:0> H ——
BYPASS BUS<07:06,04:03>

H—

FAST NORM BIT H——|

E_FPFORMAT<1> H——|

EFFECTIVE SUB L —O

SHFTCNT A

FAST NORM

Pob[ SEL

LATCH<0> H

L SA<0> H
—— MSEL (A0:D0)<1> H

ESHFTSEL H——

LOGIC

GTR OPERAND L — O

L MSEL (A1:D1)<1>

O—— MSEL (A1:D1)<0> L
L RIGHT H

O— BCD L

L FORCE ONES H

E_SHFT<4:0> H—]

E_MULDEN H—

LGESHFT H—

FUNCTION

| FORCE ZERO H

LOGIC

—— ZER EXTND BYTE H

DECODE

S AL T1 L

O—— ENBLRND L

STALLED A CLK H—
B CLK H—

SCLD-291

Figure

2-11

Shift Control MCA (SHC)

VIT 2-54

Block Diagram

2.3.1.1

shift

BUS<5:0>)

Figure

Count

1is

2-12.

These

Table

Signal
SALU

Bus

UCODE

signals

2-22

CNT

SHIFT

The

shift

the

are

described

shift

Count

Name

SHIFT

Bus

wire-OR

three

Bus

Source
BUS<K5:0>

Six

BUS<3:0>

CNT

BUS<5:0>

the

bits

Six

bits

from

Source

Count/Amount

SALU.

the

from

complement

CNT

shown

2-22.

and

the

(SHIFT

signals

Shift

from

Four

bus

Table

Signals

bits

the

count
sets

PEN.

the

microcode

ESHFTCNT<5:0>)

wvirtual

(the

from

address byte selection
(VA<1:0>)
when
enabled
by

bits

ESHFTCNTEN<2:1>,

VA<1:0>

are

bits
<5,2:0>

The
by

shift
the

the

A-latched

addition,
a

amount

value

amount

passed

microcode.

2.3.1.2

the

amount

bus

that

following

SHC

operand

and

passing

operation,

bits

are

the

most

passed

SALU
PE

SHIFT
SHIFT

bits

zeros).

normally

(SHFTCNT

the

LATCH<4:0>)

operations
be

readily

Selection
ESHFT<4:0>

the

BP bus

CNT BUS<5:0>
CNT BUS<3:0>

through
used

]

Table

field

used with
operation

bus.

(MS)

the
the

controlled
SHC

the

passes

PEN.

leave

shift

count

For

the

least

result

64-bit

significant

(LS)

cycles,

(WIRE-OR)

SHIFT

CNT BUS<5:0>

SHIFT

CNT

H
BUS<5:0>

000

E_SHFTCNTEN<1> H —:FP
E_SHFTCNTEN<2> H

Figure

2-12

Shift

Count

SCLD-292

Bus

VII

Signal

2-55

and

XALU

2-23 lists the SHF
the microword. Table
the ESHFT<4:0> field
on an APORT or BPORT

and

successive

—UCODE
VA<1:0>

count

operations,

significant

E_SHFTCNT<5:0>
0,

XALU

shift

shows how the ESHFTSEL bit is
selecting the result of a 32-bit

asserted

remaining

types

can

Function

selected

are

(the

cycle.

2-24

the

floating-point

General

functions

certain

shift

certain
on

For

passed

<4:3>

Gating

Block

Diagram

Table

2-23

ESHFT<4:0> Field Selection of Shifter
(SHF)

MCA Logic

Functions

ESHFT<4:0>
Value (Hex)

Selected General Function

Left

Right

Arithmetic

rotate

(same

rotate

bits by SHFTCNT value

bits

1left

by SHFTCNT value

shift

logical

shift

bits by SHFTCNT value

left)

Arithmetic
right
shift 64 bits by SHFTCNT value
(sign
saved
1in SIGN SAVE register on a previous
code

cycle)

Logical

left

Logical

right shift

Logical

left

Logical

right shift

FP normalize

Reserved

FP fast

normalize

MS half

(FASTNORMMS)

FP fast normalize

LS half

(FASTNORMLS)

ocC

FP left shift 64

FP right

shift 64

shift

64
32

bits by SHFTCNT value
bits

by SHFTCNT value

bits by SHFTCNT value

by SHFTCNT value

shift

right

bits

align

by SHFTCNT value

bits

SHFTCNT value

two

32-bit operands

SHFTCNT

value

FP right

Zero-extend byte

Zero-extend word to longword

Logical
left
shift 64 bits by SHFTCNT value and
load SIGN SAVE register from BP bus bit <31>

Short

align 64-bit operand

arithmetic

longword

right

by SHFTCNT value

(SHFTCNT

(SHFTCNT = 0)

shift

places)

Pass

Logical

left

VIT 2-56

shift

= 0)

bits

to 7

Table

2-23

ESHFT<K4:0>
(SHF)

MCA

Field

Selection of

Logic

Functions

Shifter

(Cont)

ESHFT<4:0>

Value

(Hex)

Selected

General

ClearMult

Function

Clear

bus

when

must

using

the

MULT

logic
16

BCD

functions

(SHFTCNT

see

Section

2.3.1.8)
17

Shifter

18--1B

Reserved

off

Inhibit

(force

APORT

ones

parity

NOR gates)

check

(used

with

ALU

masking)
1D

Force

Wbus

Clear

parity

Read

Table

Ebox

2-24

parity

error,

parity

ESHFTSEL

Equal

Value

Selects

0--5,

12,

half

shifted
6,
11,
B,

10,

APORT

zero
open

error

parity

the

error

ESHFTSEL Selection
Output

ESHFT<4:0>

Result

BP Bus

ESHFTSEL

Equal

Operand

Selects
of

the

result

half

shifted

input

BPORT

Data
of

the

Size

bits

input

bits

Function

bits

result
input

14
C,

half

shifted

the

half

result

shifted

BPORT

input

APORT

BPORT

input

Illegal

Note:

The

ESHFTSEL

Decimal

bit

ignored

the

conversion

Clear parity error
FP right align two

32-bit

operands

2-57

the

result

following

operations:

one
To

passes
cycle.

functions

the

Rotate

Shift

Logical

2.3.1.3

data,
of
byte
shifts
perform

are

chip

=-- Each SHFT MCA processes Or

performing a 0 to 7-bit shift in one
than 7 bits, complementary
more
of

shared between the even and odd MCAs as determined

identification code (ID codes 0 through 7).

The ID

code for each SHFT MCA is hardwired to the persconality select (PS)
input

pins.

Example of

a Logical

To
perform a 2-bit
left
two
places.
shifted
into
the

Shift of APORT or

left shift, MCAs
The
upper
two
lower
two bits.

BPORT data follows:

0, 2, 4, and 6 shift the data
bits
are lost and zeros are
However, MCAs 1, 3, 5, and 7

shift
the
data
right six places.
MCAs 1 and 3 shift zeros into
the
upper
six
bits, while MCAs 5 and 7 shift in ones to satisfy
the AND requirement by the NOR gates to the BP bus.
(The MULT and
XALU MCAs are unused in the operation and force 1ls to satisfy this
condition.)
The outputs of MCAQ0 are then inclusive-ORed with MCA3
to
assert the shifted byte on BP BUS<31:24>.
For a right rotate,
MCA1l
asserts bits <31:30> (from the APORT or BPORT).
For a right
shift,

2.3.1.4

asserts

zeros

for

those

bits.

Arithmetic Shift -- An arithmetic

shift performs

the same

a logical shift except that, on an arithmetic right
as
functions
sign-extended from the SIGN SAVE latch. Two
1is
data
the
shift,
The first cycle operates on ESHFT<4:0> code
are required.
cycles
which asserts the data on the BP bus, shifting it left Dby the
12,
to place the sign bit on BP bus bit
places
number of
necessary
The SIGN SAVE latch is loaded from BP bus bit <31> and the
<31>.
actual right shift must take place on a subsequent cycle.
SIGN SAVE latch is normally not altered except by the 12 code
The
Its state is held over
or when corrupted by an FP fast normalize.
should not be altered by a trap service routine unless
and
traps
it is first saved (by an arithmetic right shift), then restored.
Arithmetic Short Shift

The
arithmetic
short
shift
function
<can
right shift a 64-bit
that is useful when
function
a
places,
7
to
0
from
integer
converting bit addresses

to byte or word addresses.

16 in the
of
A value
-Conversion
String
Decimal
2.3.1.5
the microword selects the conversion of BCD
of
field
ESHFT<4:0>
string formats (except packed decimal
decimal
the
data between

to/from
leading separate numeric).
Conversion takes place on the
APORT
operand.
SHFTCNT A LATCH<4:0> must assert a value of zero.
Table
2-25 shows how EFPFORMAT<1:0> select conversion between the
UL

.
trailing

-~ 11T
numeric,

packed,

and

]
integer

VII

2-58

formats.

Table

2-25

EFPFORMAT<1:0>

of
EFPFORMAT<1:0>

ESHFT<4:0>

Value

No,

Mask

(Hex)

Decimal
Value

Field

String

Equal
If

Select

Convert

trailing

Output
the

the

fiag

packed

bits

32-bit

Mask

a
of

OK
of

H is
each

one

bits

branch

asserted if
byte in the

32-bit

trailing

conversion on

packed

Converts

lower

microcode

-->

the

packed

the

ZONE

format

16-bit

The

nibble

Performs
16

BCD
upper

l16-bit

Mask

-->

bus.

trailing
F,

Conversions

Yes,

32-bit

Control

Data

the

lower

APORT.
<-->

32-bit

longword

integer

format

the

other
by swapping the two end bytes
and swapping the two center bytes.
H

Mask

Reserved

VII

2-59

Floating-Point

The

SHR=

module

(FP)

Support

provides

three

floating-point
calculations
is a single MCA:
®

Priority

°®

Shift

Exponent

These
D_,

operators

and

each

that
microcode.

the

support

Each

ALU

(XALU)

are

mainly

data

concerned

formats

with

operations

shown

Figure

used

the

2-13.

are performed entirely by the microcode.)

MCA

logic

arithmetic
PEN

(PEN

operators

may

also

receives

for

general

functions.

FP data

Rounds

and

the

performs

significant
3.

BPORT

The

and

performs

three

separate

0
an

generates

the

subtract

(SUB),

request

XALU

fields

and

are

the

1l-bit shift of the least

FP normalization.

rounding

bits

floating

sending

some

exponent

by
£

T ~Abl

both

e
e o

The

APORT

receives

the

exponent

the

The

first

BPORT

receives

the

exponent

the

second

SALU

1is

mainly

with

the

addition

the

same

operand.

subtraction

operands:

Produces

the

resulting

sign

SLCO

module

BP BUS<K15>.

the

exponents

the

Subtracts

the

difference.

(SHF), which
field of the
®

concerned

operands:

floating

add

carry-in

ALU.

controlled

the

for

possibly

Main

both
9

receive

find the most
or to aid the
it.

°®
The
two

a
of

and

microcode

byte

(ADD)

SALU

(LS)

Stores

(plus

Floating

Sections of

microcode

Priority
encodes floating data in order to
significant
(MS)
1l-bit
in
the
mantissa
microcode in finding the byte that contains

the

operations:
1.

the

operator

(SALU)

G_Floating

operations

The

Encoder

ALU

made

2.3.2

Generates

microcode

aligns

the
smaller.
most

and

Sends

result

operands

the

2-6%

the

fraction

generates

the

branching.

VII

shift

the

shifting

condition

and

returns

count

based

shifter

logic

the

code

fraction

bits

for

F_FLOATING

EXPONENT

FRACTION

A+2

31
15

16
14

FRACTION

A+2

FRACTION

A+4

FRACTION

A+6

63
48

G_FLOATING

04
EXPONENT

00
FRACTION

FRACTION

A+2

FRACTION

Asd

FRACTION

A+6

63
48

H_FLOATING

EXPONENT

FRACTION

A+2

FRACTION

A+4

FRACTION

A+

FRACTION

A+8

FRACTION

A+10

FRACTION

A+12

FRACTION

A+14

127

113
SC.D-293

Figure

2-13

VAX-11

VII

Floating-Point

2-61

Formats

The

XALU

floating

mainly

concerned

Performs
12-bit
register
(XREG).
on BP BUS<K14:04>.
Generates
branching.
2.3.2.1

Priority

main functional
PE

with

a multiply or

divide

two

operands:

one

exponent
Returns

Encoder

areas

Tests

Logic

find
the

Sticky Bit

condition

(PEN)

the

code

MCA -- Figure

1in
the
exponent
to the SLCO module

bit

for

microcode

2-14

identifies

the

PEN logic:
the

mantissa

floating

datum

the most significant 1 bit, then passes
shift
count value needed to the SHF to

normalize

the

Examines

the

shifted
out
bits
are
0,
ALU

arithmetic
the result

fraction.

eight

most

significant bits

on
an FP align.
the carry-in bit

If all eight
for the main

set.

Guard and Round
Bit Select Logic

Saves
data

Fast Normalize

Increment
(INCR) logic input.
Performs a 0
or
1-bit right or left shift of the LS byte
of
a floating number, and passes the result
to the rounding increment logic.

Rounding

Increment
(INCR)
logic
output.
Takes the
normalized
8-bit
result
from
the
fast
1logic and adds a 0 or 1 according
normalize
to
the
rounding bits and operation (ADD or
SUR).
When enabled,; it passes the result to
the
LS
byte
of the floating
number on BP

Increment

the last two bits shifted out
field
on an FP align.
These
used
as
the
rounding
bits
normalization.

BUS<23:16>.

VII

2-62

of
bits

the
are

Function

Decoder

The

function

functions

fileld

shown

Input Multiplexer
The

the

INMUX

format

(EPSFUNCz:0>)

Tasle

selects

the

BPORT

value

for

operation

input as shown in Figure 2-15.

exponent represents the hidden bit and

bit of the fraction.
as PEDATA<20:00>.
Encoder

The

logic

the hidden
the
shift
shown
in
it asserts

PEN

operating

(INMUX)

aligns

Priority

the

2~26.

This

data

passed

The LS bit position of

is aligned with the MS
the

rest

the

logic

(PE)
tests

the

mantissa

floating

number

(including

bit) to find the most significant 1-bit. It then passes
amount
needed
for a normalize to the SHF and XALU as
Table 2-27.
1If a 1l-bit is not found on the first pass,
the ALL ZERO status signal to the microcode.

EFFECTIVE SUB L
ALIGN

(FM SALY)

SHIFTCNT

LATCH<3:0>

(FM 8HF)

d,.m

STKY

—————4 CIN

SRC<0>

——— SAc3:0>
M

STICKYIN

“ 14:08 >

<8:0>

G<1:0>
AND

<06:00>

MULT}

SA<3

_— P FUN<2:0>
.

it
DCOR

STICKY

<0%:00>

PEN

.
<2:0> HH
E_PERFUNC<2:0>

BITS

<8:0>

—-» oBIT

QUOTIENTBIT L

(FM

FOUND

BIT

MUX

PEN FUNGTIONS
1

BPOAT<07:00> H

1IA

BPORAT<31:16>

PEDATA

«20:00>

[

8SA<2:0»

2008

79-¢

A<1:0

QBIT

INCMUX

RND<1>

[}

ALl zero o

ENA QBIT

—

0
<3:0>
SHFTAMT
]
SHETAMT<3:0>

BUS<25:24»

pfq

H—F———————10

SHET
out
SA<0>

FUN<Os-—
FIGHT
(FM

“

0
CD<8:0>

RNDTRAP H

_—

SHC)

PE SHIFT CNT

BUS<3 0> H

GNT

RND<0>

INCR

(o1)

)

[O—4 pE<7:0> L
{TO

E_SHFTCNTEN<2>
ENBLRAND
(FM

NOR

GATES,

BUS<2316>)

]
————————

SHC)
BCL0-204

Figure

2-14

Priority

Encoder

(PEN)

Block

Diagram

G_FLOATING
20

PEDATA

BPORT<04:00>

BPORT<31:16>

/D_FLOATING

PEDATA

BPORT<07:00>

BPORT<31:24>

SCLD-295

Figure

Table

2-15

2-26

INMUX Mapping

EPEFUNC

Field

the

BPORT

Selection

Input

PEN

Data

Functions

EPEFUNC

<21

Function

Comments

000

Left

shift

into

byte,

Left

shift

place

into

byte,

place

Add

Load

round

bits

RND<1:0>

from

RND<1:0>

from

010

011

Load

round

bits

R<1:0>

SHFTCNT BUS

<--

value

(F_/D_

SHFTCNT

<--

value

(G_

110

111

rounding
increment

BUSK15:14>

100
01

rounding

BUS

format)

SHFTCNT BUS

{--

OBIT

Divide

<--

Multiply

BUSK16>

SHFTCNT BUS

VII

2-65

Rounding Incrementer (INCR)

(INCMUX) aligns the lowest nine INMUX
multiplexer
For a fast
in Table 2-28.
shown
as
incrementer
the
for
bits
(FAST NORM), the INCMUX outputs are directed by the
normalization

The

increment

state of SHIFTCNT A LATCH<KO>
SA<KO>
SAKO0>

(SA<K0>)

from the SHF:

Passes the true state of PEDATA<7:0> and RNDKI1>.

place,
one
1left by
or
right
value
the
Shifts
according to the RIGHT signal (0 = left, 1 = right).

With E_PEFUNC<O> asserted, the INCR adds INCD<0> to INCDK1>. With
it passes the rounded result of INCD<8:1> to
ENBLRND asserted,
RNDTRAP is asserted to
to BP BUS<23:16>).
assertion
(for
PE<7:0>
a carry-out from
caused
bit
rounding
the
adding
if
the microcode
INCD<8>.

Sticky,

Guard, and Round Bits

Inputs to this logic are controlled by the shift count A-latch
The
value asserted by the SHF as shown in Table 2-29.
(SA<3:0>)
gating
SRC)
(CIN
Source
Carry-In
the
to
STKY
asserts
logic
sticky
to the Guard and Round Bit logic when any of the tests are
and
true.

VII

2-66

Table

Input

2-27

Priority Encoder (PE) Results Passed
to the Shift Count Bus

Conditions

Logical

Test

Results

PEDATA<20:13>

Equal

Assert
Then,

SHFTCNT<3>
if:

and

E PEFUNC<K2>

test

PEDATA<K12:05>.

assert

PEDATA<12:05>

are

also

equal

E PEFUNC<2>

assert

ALL

ZERO

RND<K1>

Negate

SHFTCNT<3>

ALL

ZERO

rounding

bit

set,.

PEDATA<20:13>
Not

Equal

either

value

Test

Bit

final

Value

Output

shift

count

000

001

----

011

00001--

100

000O01--

101

000O0O01

110

000O0CO0O01
0000O0O0O

111
111

must

BUS<3:0>.

VII

asserted

2-67

010

Passed

SHFTCNT<2:0>

===
- -

E SHFTCNTEN<2>
CNT

the

---

0
0

SHIFT

assert

PEDATA<20:13>.

-----=-

0001

test

follows:

54321

001

Note:

case,

and

pass

the

SHFTCNT<3:0>

result

Table

Increment Multiplexer Data (INCD)
Selection to the Incrementer (INCR)

2-28

SA<K0>

RIGHT

INCR Bits <8 - - - 2>

<0>

0
1
1

0
1

PEDATA Bits <7 - - = 1>
PEDATA Bits <8 = - - 2>
PEDATA Bits <6 - - = 0>

>
RND<1
<0>
RND<O>

L———- ENA OBIT: 0 = RNDK1>
110)

(Code

Note:

E_PEFUNC<0>

Assert RNDTRAP if

Table

assert R<1:0>

INCR<K8> produced a

Selected

(round bits);

carry-out.

Input or Test

to the Guard and Round
PEDATA<14:06>
Asserts
1logic
Sticky
STICKYIN<K8:0>.
on
logic
Bit
an OR of PEDATA<K05:00> where any bit
performs
on

Equal

RND<1:0>

Sticky Bit Logic Input and Test Selection

2-29

Input Selection
Equal

added to INCR<K1> and INCR<K8:1> are asserted as PE<7:0>.

(RND<1>)

SA<K3>

= OBIT

If E PEFUNCKO> = 0, RND<1:0> assert BP BUS<K25:24>.
If

SA<K3>

asserts

STKY.

PEDATA<06:00> to the Sticky logic and
Asserts
(Zeros are
Bit logic.
Round
and
Guard
the
1logic
Sticky
STICKYIN<K8:7>.)
on
asserted
PEDATAKG6:00>,
of
OR
selective
a
performs
as selected by
STKY
asserts
1l-bit
a
where
SAL2:0>:

SA Bits

Selects OR Test
of PEDATA Bits

0 00
0 01
010
011

- <0>
<1:0>
<2:0>

<3:0>
<4:0>
<5:0>
<6:0>

00
1 01
110
111

VII 2-68

Comments

STKY negated

STKY asserted
if any bit 1is
a 1

Table

2-30

G<1:0>

Guard

Bit

STICKYIN

SA Bits
<21

<4 <
- -

coi1r0

011

100

=-XX

110

111

XX
indicate

assertion

Table
EFF

ALIGN

SUB

2-31

the

two

guard

the

Round
Bits

STKY

-4

==
- =

STICKYIN

bits

round

Bit

Selected

bits

G<1:0>

bits

R<1:0>

(and

selected

for

possible

R<1:0>).

Input

Seiection

Outputs

(Outputs

R<1:0>

<K--

GK1:0>

R<1:0>

<K==

Ones

R<1:0>

R<1>

deselected)

<-<K--

VII

- ==
- = ===
== «
- =

the

=-XX

assertion

Selected

X X
X X =-=-XX - -

Selection

G<1l:0>
76543210

co1r

Note:

Bits

for Assertion

ocooo0

Input

GK1:0>
XOR

2-69

(Complement

G<1:0>

and

R<K0>

G<1:0>)
<--

G<0>

2.3.2.2 Shift ALU (SALU) -- In addition to their special FP
functions, the SALU and XALU may be used by the microcode for
They are both
or register operations.
arithmetic
general
shown in Table
as
fields
ode
microc
same
controlled by some of the
Figure

2-16

identifies

the

main

functional

areas of the SALU

logic:

SALU Function Decoder (SFND)
SALU Sign

(SSGN)

SALU Input Select

(SINS)

SALU Symmetrical Difference (SDIF)
SALU Output Inverter (SOPI)
SALU Branch Logic (SBRL)

SALU Function Decoder (SFND)

The

SALU/XALU

function

of the microword (E_SXALUFN<5:0>)

field

controls the SALU functions as shown in Table 2-33.

Condition Codes

The SFND 1logic does not produce any microbranch condition codes.
However, each of the other logical areas produces codes that are
asserted to the SBRL logic, where they are either used directly or
to generate other types of codes.

SALU Sign

(SSGN)

The SSGN logic receives the fractional signs of the first and
For a
second floating operand on APORT<15> and BPORT<K15>.
floating add or subtract, the SSGN produces the sign of the
resulting fraction, as shown in Table 2-34, and writes it to the
sign

latch.

Sign Latch -- The sign latch is a 1-bit recirculating register
consisting of a stalled A-clock and B-clock latch. The sign latch
holds the resulting sign of the fraction for assertion to BP
BUS<15> or for use as a microbranch condition. The stalled
A-clock latch (ASIGN LATCH) value is passed to the SBRL.
SALU Input Select (SINS)

The SINS consists of a set of multiplexers that receive the
exponent of the first operand on the APORT<14:04> inputs and
receive the exponent of the second operand on the BPORT<K14:04>
inputs.

2-70

Table

Signal
CS0

RAM

2-32

XALU Control

from

Microcode

Bit

Name
Segment

SALU and

Asserted,

RAM

Description

(SALU)

EFPSUFL

CS1

the

Segment

Signals

(SALU

and

the

(Described
Selects

ESXALUFN<2:1>

the

0
1
ESXBYEN

general

Tables

specialized

microcode

Selects

ESXALUFN<O>

floating-point

shuffle

XALU)

Selects

ESXALUFN<5:3>

enables

IBox.

the

SALU

(the

and

functions

functions.

2-38.)
according

operation.

input/output

= Operand
= Operand

value

SALU/XALU
2-33

is
is

format:

F
or D Floating
G Floating or Integer

Asserted,

enables

resulting

sign

the

SIGN

LATCH

the

fraction)

the

resulting

to BP BUSK15>.
XALU

Asserted,

exponent
(or
BP BUS<14:04>,
CS1

RAM

Segment

RAM

Segment

ERECIPE<K1:0>

ESIGNWR

the

operation)

(SALU)

ESHFTCNTEN<2>

CS2

enables

result

the

Enables

the

shift

SALU SHIFT CNT<5:0>

count

value

bus.

(SALU)

Selects
one of four microbranch condition
code groups from the branch multiplexer.
1l

= Writes

enables
logic.

the

Inverts

sign

reserved

the

SIGN

LATCH

trap

and

check

shift amount.
(Is used if
set
on
the first pass

WRONG
SHIFT
was
through the SALU.)

VII 2-71

the

operand

Table
E_SXALUFN

<5 4 3 2 1>
See

<-- SIGN LATCH;

<--

Note

BUSK15>

BP BUSK15>

SIGN

LATCH

<-- SIGN LATCH;

SHFTCNT

<--

SHFT AMT

ADD

SHFTCNT

<--

SHFT AMT

SUB

001- -

SIGN

LATCH

<-- SIGN

10100

SIGN

LATCH

<--

610 - 011 - 100 - 1
0

10111

110 - 111 - Notes:

Comments

Note 2.

BP BUSK15> <-- SIGN LATCH

BP BUS<K15>

0
1

SALU Functions

Exponent Operation or Function

00011

;
;

the

Note

000O00O

See

ESXALUFN Field Control of

2-33

SIGN LATCH
SIGN LATCH

Fraction

Note 4.

SIGN LATCH <-- BPORTK15>
SIGN LATCH <-- SIGN LATCH XORed with Sign of
SIGN LATCH <-- SIGN LATCH XORed with Sign of
ESXALUFN<O> -- Equal

SIGN LATCH

selects

Fraction
Fraction
format for

the

Equal to 1, selects
F /D Floating.
format for G _Floating/Integer.

the

-- The
sign
latch
value is passed to BP
BUSK15>
if
E SXBYEN
1s
asserted.
Otherwise,
the
operation is performed
but

Write SIGN

the

result

not

sent.

-- The reserved operand trap
is

check

enabled

when

(RES OP TRAP)
E SIGNWR

1is

asserted.

BPORT<15>

MUL

MUL
MUL

<-- APORT<15>
.
<-- 0

XORed with Sign of

SIGN LATCH <-- SIGN LATCH XORed with Sign of Fraction
SIGN LATCH <-- SIGN LATCH XORed with Sign of Fraction
SIGN LATCH <-- Sign of the Larger Fraction

-- If

the

cperand

result
trap,

inverted.

VII 2-72

generates

the

BPORT

reserved

sign

not

MUL
DIV

E_SXBYEN

SIGN

(TO NOR GATES,
BP BUS<15>)

APORT<15> H

»8

LAT

XOR

BPORT<15> H

_
SBRL
y

COND. CODES

E_RECIPE<1:0> H

E_SIGNWR L

g
SINS

SDIF

P BRANCH<5:0> H

RCSPVI'g

» RES OP TRAP H
LGESHFT H

cc's

A MINUS B

<10:08>

SDIF

1IA
eL-C

a[‘,x

CcC'S

COND.

ALIGN GT 16 H

CODE

LOGIC

GTR OPERAND L

D—

APORT<14> H

—1— >0

| | LOAD STATIC L
SUBTRACTER

APORT<13:12> H

BPORT<14> H ——>0
BPORT<13:12> H

SOPI

ces

EFF_ADD H

BPORT<11:04> H

r_iHR

4k
s

[

APORT<11:04> H

— EXPONENT COMPARE L

SALU SHIFT

EFFECTIVE SUB L

» EFF SUB!

E_FPSUFL L— 1

CNT BUS<5:0»

—

E_SXALUFN<0> H
(SEL G FORMAT H)
E_SHFTCNTEN<2>

—

—p
FUNCTION |.

E_SXALUFN<5:1> H

BrND [ SALU FUNCTIONS
L

SCLD-296

Figure

2-16

Shift

ALU

(SALU)

Block

Diagram

jI; EFF SUB2 H

Table

2-34

Resulting

Sign of

the

Fraction
Resulting

Operation

Resulting

(+A)

(+4B)

Plus

Effective

ADD

(+A)

(+BR)

Plus,

Minus,

Effective

SUB

(+A)

(-B)

Plus,

Minus,

Effective

SUB

(+A)

(-B)

Plus

Effective

ADD

(-A)

(4B)

Minus,

(-A)
(=A)
(-A)

+
-

(+B)
(-B)
(-B)

Minus
Minus
Minus,

Table

2-35

Floating

SINS

<10

APORT or

BPORT

SALU

Format

Sign

Operation

Plus,

Selection

Outputs

Inputs

the

APORT

SDIF

and

ADD
ADD
SUB

BPORT

Inputs

00>

Comments

SINS

<14 13 12 11 10 09 08 07 06 05 04>

F /D

<14 13 12 14 13 12 11 10 09 08 07>
Input

SUB

Effective
Effective
Effective

Subtracter

Exponent

Effective

Value

G—

Small,

F_/D_

Note

G—-

Large,

F_/D_

Note

Zero,

F_/D

Note

Notes:

Asserts

OVR_UND

exponents

exponents
Asserts

POSS

have

may

ADD

EFFECTIVE

ADD

value

less

64.

result

OVR UND

POSS

either
exponent has
exponents may result
Asserts
Asserts

B
B

ZERO
ZERO

floating

and

both

(Adding

the

underflow.)
and

the

if
the

see

ADD

see

a value of all ones.
(Adding
in a floating overflow.)

EXPA

EXPB

than

see

the

EFFECTIVE

ADD

APORT exponent

BPORT

exponent

zero.

Exponent
VAX

Sign

architecture

uses

produce

are

inverted

both

SINS

Input

The

APORT

the

SET)

the

adder,

Symmetrical

The

SDIF

<10>

and
to

SALU

Output

The

SOPI

MINUS

assert
SALU

The

the

signals
the

four

that
code

The

upper
also

which

are

wused

condition

(which

A-side
are

the

lower

eight

produces

also

these

the

SBRL.

the

SDIF

adder.

the

B-side

applied

the

bits
to

the

subtraction

carry

produce

outputs

and

assert

result
from

bits

condition

bits

subtraction

shift

bits

amount

tests

result

required

that

for

produce

and

(SBRL)

receives

sections,

are

passed

input

set
same

The

2-36,

under

describes

the

microbranch

are

they

101

000X1

are

them

codes.

static

stalled A-clock

until

condition

using

2-37

signals

Table

the

either

shown

codes

produced

directly

SBRL outputs
the

the

control

logical

with
one of

the

states

that

are

logic.

condition

latches.

codes

The

again

loaded

the

nonstatic

one

latch
of

states

two

SALU

Trap

TRAP

signal

ESIGNWR,

but

part

subtracter.

the

uses

field.

Operand

codes

are

(SOPI)

groups

negative

the

receives

kinds

SBRL

assert

latches

three

other

(SDIF)

produce

the

BPORT

E SXALUFN<5:3>

RES

latches

full-time

E_SXALUFN<5:1>

Enabled

logical

that

remain
the
functions:

Reserved

that

branch multiplexer

other

conditions

loaded

tests
APORT

the

codes

Logic

E_ RECIPE<1:0>

Most

the

condition

SBRL

and

align.

sign

BPORT<145>

logic.

the

applied

receives

and

are each multiplexed to a B-latch
selected format as shown in Table 2-35.

wused

Inverter

Branch

exponent

SBRL.

B<07:00>)

floating

SINS

the

APORT<14>

operands

Difference

<07>,

Subtracter

are

receives

the

B<10:08>).

codes

side

making

state

Therefore,

SDIF

side

SALU

MINUS

and

are
1

inverted

zero.

input

BPORT

The

MUX

However,

and

GSBRL.

input

according

registers

the

positive

Registers

true

its

one

asserted

exponent

zero.

VII

2-75

the

sign

condition
either

codes.

fraction

Table 2-36

E_RECIPE

Bits

A-Latched Condition Code Inputs
to the Branch Multiplexer

Branch Multiplexer Outputs to the BRANCH<5:0> B-Latch

<1:0>

BRANCH<5>

BRANCH<4>

BRANCH<3>

A_EFF ADD

A_ANY OP ZERO

A BOTH OP ZERO

A _GTR 64 ALIGN

A GTR 32 ALIGN

A_ANY OP ZERO

A SIGN LATCH*

A_ZERO OP B

ASIGN OF EXP*

A _GTR 32 ALIGN

A_EFF ADD

A ALIGN 1632

<1:0>

BRANCH<2>

BRANCH<1>

>
BRANCH<O0

A _SIGN LATCH*

A_EFF ADD

A _WRONG SHIFT

A _BOTH OP ZERO

A _ZERO OP A

A _GTR 32 ALIGN

A OVR OR ANY

A _UNKNOWN WRONG

A FULL NORM

OP_ZERO

Nonstatic

Condition Codes

LARGE

Table

Signal
A EFF

LATCH
OP

Asserted

shown

Table

ZERO

ALIGN

Either

ALIGN

1632

Description

result

The

the

states

calculated

are

=zero.

zero.
subtraction

will

exponent

subtraction

will

subtraction

will

32.
exponent

shift

32.

amount

microcode
must
force
from the subtractor.)
OP

The

APORT exponent

zero.

A _ZERO

The

BPORT

zero.

A SIGN

EXP

The

sign

for

converting

exponent

the

A _ZERO

result.

exponents

exponent

range

sign

64.
an

than

result

the

exponents

result

than

greater

The

SHIFT

fractional

the

greater

depending

2-34.

both

The

be
A_WRONG

be
A ALIGN

Code

negated

the

Both

be
A GTR

Asserts

ZERO

Condition

Function

ADD

A BOTH

A GTR

Microbranch

Name

A SIGN
A _ANY

2-37

BPORT

from

wrong.

correct

exponent.

floating

(The

result

(Useful

integer

format.)
A OVR

ANY
OP ZERO

The

result

too

large

for

floating

exponent

the

size

overflow

subtraction may

the

wunderflow

may

unknown

the

result.)
A _UNKNOWN

WRONG_LARGE

Which

operand

exponents

subtract

add).
the
A _FULL

NORM

larger

shift

Nonstatic

Condition

the

greater

Codes

VII

larger

2-77

equal

(anything

However,

normalize.
the
smaller
l1-bit.)

1is

are

other

the
two

than

second

effective

operand

may

necessary

fractions.

than

1is

(The
microcode must
fraction
to
find

then scan
the first

2.3.2.3
Exponent
ALU (XALU) -- Figure 2-17 shows the location of
1identifies the main functional
and
data multiplexers
main
the
areas of

the

XALU logic:

XALU Function Decoder (XALF)
Exponent Register (XREG)
XALU Shifter (XALS)
XALU Adder

(XALA)

XALU

Function

Decoder

The

microcode signals

(XALF)

that

control

the XALU come

from the CS1 RAM

segment.

Table
2-38
shows
the
general
defined by ESXALUFN<5:3>.

Table
when

2-39

shows

the

E SXALUFN<5:3>

Table

2-40 shows

the

when E_SXALUFN<5:3>

Exponent

The

XREG

stalled

1is

A-clock

functions
are

equal

XALU functions

selected by
to

all

that

are

E _SXALUFN<2:0>

zeros.

functions selected by E SXALUFN<2:0>
contain a

code

other than

zero.

(XREG)

12-bit

recirculating

(REGXA)

consists

and a B-clock register

(REGXB).

The
XREG
holds
the
first operand for a subsequent operation or
holds
the
result
for assertion to the BP bus. REGXA is used for
condition
code (CC) tests that assert XALUCC directly to the IBox
(Table

2-41).

REGXB
contents
can
be
passed
to the BP bus or asserted to the
A-side
of
the adder.
The adder can receive the true or inverted
value
of
REGXB,
or a value of zero (Table 2-38).
A global trap
inhibits

REGXB

from being

loaded.

VII

2-78

EXPONENT

REG

INV,

CLR, |

REG

XALR

(GLOBAL TRAP H)

BLOCKEDWRITE<1> H

(XREG)

E_SHFTCNT<6>

¥ XALUCC

H
XALA

IIA

SHFTCNT BUS<5:0>

APORT<14:04>

XALS

M1
BPORT<15:04>

)

:L’

———

XALOUT<10:00>

(TO

NOR GATES,

BUS<14:045>)

-f —p»
GTR OPERAND LE_SXBYEN

H ——}
XALF

E_SXALUFN<5:0>

FUNC

-——

SA<0> H
(ADD

[—P»

DCDR [—— XALU FUNCTIONS

EFF ADD H

MUL NORM H —

NORM)

SCLD-297

Figure

2-17

Exponent

ALU

(XALU)

Block

Diagram

Table 2-38

ESXALUFN<5:3)
XALU

Function

ESXALUFN

Control of the General

Functions

<5 4 3 2>

Name

Exponent Operation or Function

0 -

Bypass

BP BUS<14:04>

1 -

Add

XREG<11:00>

<--

XREG<11:00> + INPUT<K11:00>

0 -

Increment

XREG<11:00>

<--

XREGK11:00>

1 -

Add-Increment

XREG<11:00>

<--

XREG<11:00> + INPUT<11:00> + 1

0 -

Sel.

Exponent

XREG<11:00>

<--

Larger of APORT or BPORT value

Pass

XREG<11:00>

<--

INPUTK11:00>

Decrement

XREG<11:00>

<--

XREGK11:00> - 2

Decrement

XREG<11:00>

<--

XREGK11:00> -1

Subtract

XREG<11:00>

<--

XREG<11:00> + INPUT<11:00> + 1

111 -

<--

XREG<K10:00>

(See Note 1)

+ 1

Notes:

The
the

output is passed to the BP bus if E SXBYEN 1s asserted by
microcode.
Otherwise, the operation is performed but the

result

not

sent.

The

Invert/Clear/Pass

XREG

data.

With

1logic has

E SXALUFN<5:3>

the

equal

111

Invert - Assert XREG<11:00>

Clear - Assert

00,

though

zeros

the

following effects on the
to:

for subtraction.

to pass

101

value

All Other
Codes

Pass - Assert the contents of
for an exponent operation.

the

true

input

adder.

XREG<K11:00>

Table

2-39

XALU

Functions

Equal

with

E_SXALUFN<5:3>

000

E_SXALUFN

<21

General

XALU

Function

Comments

000

Bus

<--

XREG

001

F /D
_

BP Bus

010

<--

XREG

Reserved

011

BP Bus

<--

XREG

Bus

{-=-

XREG

+1/-1

Bus

{--

XREG

+1/-1

110

Bus

<--

XREG

111

-1

Bus

{--

XREG

-1

Integer

(No

Bias)

F_/D_ ADD/SUB

ADD/SUB

F_/D_ MUL

Fast

Norm

Fast

Norm

Fast

Norm

MUL

Fast

Norm

result

Notes:
E_SXBYEN

must

Otherwise,

SA<KO0>

from

contents

(on

ADD

0).
if

NORM

the
are

exponent

(-1),

the

asserted

operation

shift

control
to

modified,

correction

send

performed

sent

the

MCA
BP

(SHC)

bus

the

one

from

(on

the

(+1),

from

the

Table

SHF

logic

adder

instead

2-40

XALU
Not

MUL

NORM

from

the

Functions
Equal

the

MULT

bus.

sent.

the

XREG

unmodified

SALU then

the

not

whether

asserted,

negated.

select

result

determines

modified

EFF ADD

©plus

the

but

selects

minus

one

logic

causes

XREG.

with

ESXALUFN<5:
3>

000

E_SXALUFN

<21

XALU

Input

Function

Comments

00O

INPUT

<--

SHFTCNT BUS,

INPUT

<--

APORT,

010

2's

INPUT

<--

011

APORT,

Bias

INPUT

F_/D Floating

<--

APORT,

See

Bias

Note.

G Floating

See

Note.

INPUT

<--

SHFTCNT BUS

INPUT

<--

BPORT,

2's

110

INPUT

<--

111

BPORT,

Bias

INPUT

F_/D Floating

<--

BPORT,

See

Bias

Note.

G Floating

See

Note.

performs

reserved

1l's

Complement

Bits

Note:

The

SALU

operand

asserted.

VIiI 2-81

check

E SIGNWR

1is

Table 2-41
E SXALUFN Bits

XALU Condition Code (XALUCC) Tests

< 54321>

Conditions that Assert XALUCC

000 - -

XREG<11> is set (negative fraction).

XREG<K11:00> are zero.

010-20
110-20

The fraction and exponent sign bits are
not equal and E_SHFTCNT<6> is:

010-1
110-1
001--

011 - 100

111 - -

XALU Shifter

)
XOR bits REGXA<08:07> (F_/D

XOR bits REGXA<il:10> (G_/Integer)

(XALS)

The XALS has two sets of input multiplexers that select the input
data and pass it (shifted or wunshifted) to the B-side of the
adder:

Input Multiplexer (Ml) - M1 passes the selected input
port data and format to M3 (Table 2-42). On the first
pass, GTR OPERAND from the SALU selects the larger of the
two operands.

shift Multiplexer (M3) - The M3 outputs are passed to the
The M3 input data and
B-side of the adder (Table 2-43).
format are selected from one of two sources:

The

true

negative (one's complement) value from

u M

the shift count bus.

o
IR
o)}

O
il

hifted

VII 2-82

wvalue

of the first or second

XALU

Output

The

XALU

has

exponent

the

two

(BP)

Adder

the

with

Multiplexer

output
1ll-bit

output

Output

(M2

and

adder

(M2)

the

adder

the

result

bus

XREG

(M6)

received

SXALUFN

GTR

OPERAND

<15

1
-

(bits

passes

from M2

Inputs

result

complete

It may
<10:00>)

the

(Table

12-bit

also
to

pass
for

correct

2-45)

and

format

inverts

its complemented value.
E SXBYEN is asserted by

Passed

Multiplexer

the

pass

2-44),

sign
bit
back
outputs
are enabled
the microcode.)

2-42

pass

Table

participate

value

(Table

that

XREG,

may

exponent

(The

M6)

and

exponent

Multiplexer

the

bus:

adder

multiplexers

operation

bypass
®

Multiplexers

Output

Bits

04>

APORT<14

04>

BPORT<15

04>

Note:

APORT<14>

The

larger

applied

the

two

the

inputs

operands

for

both

selected

VII 2=83

bits

the

<15>

first

and

pass.

<14>.

Table

2-43

Inputs

Passed

to the Adder B-side

<21 0>

Source

Input

Multiplexer

Outputs

000

SHFTCNT BUS

<05 04 03

01 00>

100

SHFTCNT BUS

<05

X 01

PORT

(G)

<15

10 09

08 07 06 05 04>

X10

PORT

(F/D)

<14

X 11

PORT

(G)

<14

05 04>

SXALUFN

+~--~—~

<A4

Bias

Note:

The

(invert)

Zeros

above

<11 10 09 08 07 06 05 04 03 02 01 00>

the

sign

are asserted

values

are

true

the

remainder

(BIAS

all

other

VII 2-84

codes.

07>

REM).

to the adder when ESXALUFN<5:3>

for

00>

000

= gig

Table

2-44

Outputs

E_SXALUFN

E_SXBYEN ADDNORM

E_SXALUFN<5:3>
-

Not

Equal

Inputs

the

MULNORM

the

XREG

Passed

Outputs

Comments

000

ADDERK

11:00>

E SXALUFN<5:3>

Equal

000

XREGK11:00>

Invert

XREG<11:00>

Clear

for

XREGK10>

XREG<10>

integer

operation

XREG<11:00>

Bit

<11>

Notes:

1is

logic

but

shift

count

the

MULT

Table

XREG<11:00>
ADDER<K11:00>
XREGK11:00>

ADDERK11:00>

wused

not

the

sent

A-latch

adder,

the

(SA<0>)

from

logic.

2-45

Data

Passed

XREG,

bus.

the

and

condition

ADDNORM

the

SHF.

BP Bus

bit

code

<0>

MULNORM

comes

E_SXALUFN<O>

Output

Value

Format

<14

04>

G_ or

Integer

<10

00>

<07

00>

Note:

The

outputs

are

Outputs

enabled

microcode.

VII

when

2-85

the

E_SXBYEN

Bus

asserted

the

(CC)

the

from

2.3.3
The

Multiplier/Divider
MULT

chips,

section

each

2.3.3.1

identifies

the

2.3.3.2

the

identifies

and

the
Tt

one

and

shows

2-46

MULT

logical

Table

2-47

control
Table
ports

Control

<control

also

signals

describes
and

2-18,

used

gating

signals
the

and

Sheet

in multiply
that

Figure

the

data

carry

shift

the

2-48
as

the

microcode

arithmetic

functions.

describes

2.3.3.3

describes

they

are

Logical

(although

the

shown

the

MULT

E MULTDIV<4:0>

operands

drives

2-18,

(MUL
the

Sheet

propagate/generate

signals

the
in

and

Arithmetic
up

exponent may

1in

that

field.

functions

the

Figure

shift

1is

MULT

used

divide

with

the

loaded

gquard

the

E MULDIV

divisor
position

take

the

control

place

MULTIPR

under

chip

the

signal

logic.

Functions

bits

=--

from

The

MULT accepts

the APORT

and

BPORT

Sheet

the

1loaded

the

the MULT
LS byte.

load.

first

the

byte

logic,
Thus,

MULT

load

cycle

the

fraction

while the sign
an 8-bit right
takes

and

cycles,

the

operand

second.
code

with

forced
- N e N e Na

bits

that

be masked).

2-18,

accomplished

fields

operations

used

bit

microcode

field
1is
1loaded to the MS byte of
and exponent field is loaded to the

(MULTIPR)

data.

Figure

output

Signals

identifies

floating

loop
the

custom multiplier

byte

operations.

Table

eight

Signals

input

also

NOR gates.

Carry

signals.
(DIV)

data

through

operates

Interface

operations.
bus

consists

which

Data

(MULT)

the

bits.

zero

and

exponent

The

sign

the
[P 9

Ad A NANANr i

hidden

when

(hex)

and

bit
A
e

"load

VII

2-86

loads

exponent
is

the

field

inserted
e N4

LA
N de

with mask"

multiplicand

of
into
e NS

e £ 8

the
the
LTM

operand
LS

specified.

bit

The

NOP

code

states,

and

later

following

This

byte

pause

the
of

all

zeros,

tested

for

the
1is

This
ones

CLEAR MULT
the

and

the

SHF
of

enable

being

the

drive

VII

2-87

zero).

not

used

bus

15),
the

6),
8)

(when

requirement
NOR

gates,

However,
forces
BP

bus

SHF

bit.

output

would

the

cycle

the

(instead

bus.

=
=

the

asserts

the
corrupted.

quotient

the

internal

interrupted

bus

SHFT<4:0>

the

example),

(E_SHFT<4:0>
ALU

from

its

required

enable the

because

and

drive

the

normalize.

for

saves

(E_PEFUNC<K2:0>

substitute

left

and

operation

care

data

will

MULT

cycle,

normalize

shift

enabled

ones.

later

required

left

will

the

divide

this

multiplier,

allowing

prevent

PEN

assert

byte,

normalize

operator

function,

for

pauses

quotient

MULT
the

operators

(hex)

multiply

the

bit)

LOAD

active

the

and

When
assert

the

doing

rounding

1F
a

multiplier

reading

must

continued.

quotient

When

allowing

the

doing

normally

that

unused

allowing

the

special

SHF

a
BP

(with

bus
data

to
to

all
be

MULT LOGIC

MULTLOOP

——— «63:56> H

—1mi

APORT
<07:00> H

__1 MULTFAN

RO p—
H

R0<63:32>

MULTLOOP
<23:16> H

MULTLOOP

88-C

-------- <31:24> H
MULTLOOP

<39:32> H

R0<31:00>

IIA

<23:16>

<15:08>

<31:24> H

|—

BPgROT

APORT

—-—zfiéJQLTé-S?PH

MLl MLO

i— DI

<47:40> H

MLI MLO

RO p—

MULTLOOP

’1—<55348> H

MLl MLO

0 ——MLI MLO

DATA SIGNALS

MULTLOOP

MLl

— M|

BPORT
<07:00> H ——|DI

MLI

MLO

RO p——

MLl

MLO

RO p—

MULTLOOP

<15:08> H

MLl

MLO

)

MULTRES L
<31:00>

TO BNOR GATES,
_ZASJ;T&SSPH

BUS<31:00>)

MLO

RO b

RO b—

B
LAT

NOR GATES

:>-_BP BUS

«15:08>

BPORT H
45

APORT
15085 H

Eggfigs> y

E_MLT_BYTE_OFF

B
H—{ At
SCLD-298

Figure

2-18

Multiplier/Divider
(Sheet

(MULT)

Block Diagram

MULT

MULTLOOP<55> H —{DSI

MULTLOOP<47> H —{DSI

QUOTIENTBIT L —q DDI
caMs L —dci

—q DDI

P p— P<7> L
Gp—G<7> L

CiMs L— CI

CO pb—

FAN

68-C IIA

E_MULDEN

qbDI

P p—P<6> L
G p—G<6> L

MULTLOOP<31> H —{DSI

caLs L — Cl

G b—G<5> L

CO pb—

NRO|—

NRO| FNC

TRAP

6 —|PS

5 —{PS

4 —|ps

MULTLOOP<25> H

DSl

MULTLOOP<15> H —{DSI

MULTLOOP<07> H —{DSI

APORT<15> H—{DS]

QUOTIENTBIT L

DDI

courz L

Pp—P<3> L

q 0Dl
—o

cop—

CO b— CcOoUT<2> L

NDTRAR? Mo D O—

ONE H—qCl
NAI

NRO|—

NRO |-

NRO|— RNDTRAP2 H

FNC

TRAP
2 —|Ps

G b—Geo> L
CO p— COUT<0> L

NAI

FNC

TRAP
a —|Ps

P pb—P<0> L

]

Gpb-Get> L
cop—

NAI
NRO|— RNDTRAP1 H

Pp—P<i> L

couTo L—o|Cl

G Geas L

L{FNe

4 DDI

q DDI

Gp—Geas L S8 LG

MUL NORM H —— +—{NAI

RNDTRAP1

P pb—P<2> L

G pb—Ged> L

NAI

FNC

TRAP

P p—P<4> L

CO p—COUT<4> L

NAI

FNC

TRAP

-4 DO!

P p—P<5> L

couTs L —dclI

NRO|—MUL NORM H

FNC

H-—-

SIGNALS

MULTLOOP<38> H—{DSI

NAI

NRO

MULT-

CONTROL

CO p—

MUL NORM H —]NAI

E MULDIV<4:0> H—_

LOGIC

FNC

TRAP
1 —PS

TRAP
o —|Ps
SCLD-299

Figure

2-18

Multiplier/Divider
(Sheet

(MULT)

Block

Diagram

Table

2-46

(MULT)

Multiplier/Divider

Control Signals

from the Microcode
Signal

Signal

Name

E MULDIV<K4:0>

These
count

SHF

Functions

five bits of the shi
1lower
the
are
(E_SHFTCNT) field and are applied to t
from the microcode shift coun
XALU
and

bus.
E MULDEN

This

0 =

the

bit has

following effects:

Enables the MULT under the control of the
E_MULDIV<4:0>

1 =

the MULT and preserves internal
Disables
order to resume execution later
in
states
the same effect as an E _MULDIV code
(Has
of

BYTE OFF
E_MLT

field.

all

1is.)

This bit has the following effects:

0 =

1Inhibits

the

LS byte from being written

to BP BUS<K15:08>.

Outputs

the

LS byte to BP BUS<K15:08> if

required conditions are met.
other
SHF must be doing an 8-bit FP right shift

with E FPFORMAT<K1:0> and E_SHFTFPOUT<1:0>

both equal to 3.)

Table
E MULTDIV

321

00O0O

0001

2-47
Bits

E MULDIV

Field

Control

Multiply/Divide

LOAD

Load

64-bit

LOAD

Load

64-bit

G format

LOAD

STORE

Load

64-bit

F_/D format
bit.

Store

32-bit

result

with

STORE

Store
no

00110

STORE

Round

STORE

MS
Trap

Store

LAST

MLT

Last

01001

STORE

Store

01010

STORE

bits

the

rounded
Check

result

with

rounding,

for

bits

Round
of

result

Check

multiply
32

normalized
with

Check

and

masking.

masking,

result

masking.

normalized

load

check.

rounded

01000

masking;

F_format

Round

Store

hidden

Trap.

rounded

00111

load

multiplicand/divisor

normalize,

masking.

multiplicand/divisor

masking;

with

for
00101

Function

multiplicand/divisor,

with

hidden
00100

Functions

Reserved.

bit.
00011

MULT

Name

Mnemonic

masking.
00010

the

Trap.

normalized
with

for

and

D format

Round

and

G format

Trap.

cycle.
bits

the

result

with

masking.

Store

bits

the

G format

bits

the

D format

result.

01011

STORE

Store
result.

01100

FIRST

MLT

First

multiply

supplies
01101

MAIN

MLT

Main

2-91

loop.

multiplier

multiply

supplies

VII

the

loop.

(Microcode

byte.)
(Microcode

multiplier

byte.)

Table

2-47

E_MULDIV Field

E_MULTDIV Bits

<4 321 0>
01110 to

Name

Mnemonic

Control of the MULT Functions (Cont)

Multiply/Divide Function
Reserved.

10l11l

Load

Dividend and do first division

11000

LOAD DD

11001

MAIN DIV

Main division loop.

11010

LAST DIV

Last division loop.

loop.

Reserved.

11011 to 11101

11110 and 11111

NOP

Preserve internal states and inhibit

writes

the

BP BUS.

Table
MULTIPR

Data

Port

I/0O

MULT

Logic

Signal

Port

Signal

Name

Function

Loop

(MLI/MLO)

multiply

the

(DI)

Multiplier

(MI )

multiplicand

bits

may

and

the

word

the

For

exponent
DIV

first.

loaded

through

The

the

one

bits

result

are

separate

all

(MULTFAN)

bits

port

byte

then
on

the

MI
with

starting

chips

supplied

and is
the MULT

from

logic.

(R0<63:32>)

cycle,

the

2-93

divisor

APORT<23:16>

passed

1is

byte

BPORT,

out.

of
the

and

the

the final
BP bus on

cycles.

divide

time

cycle,

(RO<31:00>)

quotient

VIT

applied

the

dividend

operation,

multiplier

to
the

For

each
byte.

up
to

applied

the

byte.

the

cycle.

MUL

through

following
a

masked

operation,

loaded

The

(DSI)

divisor

APORT

asserted

loaded
is

fanout

Shift

word

the microcode

Divider

the

and

byte

product

The

Each

(RO)

each

port.

input
the LS

Out

multiplier

Result

cycle,

accumulating

right-shifted
Data

Description

Signals

Multiplier

In/Out

2-48

the

accumulating

left-shifted

one

byte.,

bit

MULT Logic Signal Port Function Description (Cont)

Table 2-48
Port

ok aa ¥ 2
varllrl
nut
o

[6F-%

s
g

Carry-In

Propagate

(P),
(G)

) 2

(

Generate

Function

n:arry—ont
AL L
-

passed

from
R
1

bvute
Y -

directly

the

4.,
4

2
&~
F

carry-in port

A carry-in for
of the next MS byte.
each
of
the other bytes comes from
the carry look-ahead logic.
The

carry

signals

propagate

from

QUOTIENTBIT

Divider

Data

Signal

Look—-Ahead Signals
)~

Carry and

Name

~ O

MULTIPR

generate

chips

drive

the

1is

passed

from

the

carry look-ahead logic

{(DDI)

and

all

to all

chips:

The
first
cycle
of
a
divide
the
from
dividend
the
subtracts
If the result is negative,
divisor.
QUOTIENTBIT is asserted and the next
of the partial
add
an
does
cycle
remainder.
1f
the
result
is
positive,
the
next
cycle
does
a
subtract.

Control

I/0 Signals

Normalize

(NAI)

When RNDTRAP is asserted by
byte
3
or 0, the
1internal
states
of all
chips
are
preserved
and
the
RO
outputs
disabled.
The MULT is thus
disabled
for
the
next
3
cycles
(during pipeline latency).

Normalize/Round
Out (NRO) and
TRAP

Function

(FNC)

Position

Select

MUL
NORM
1is asserted if the MS bit
in the hidden bit position,
not
is
causing a l-bit left shift.

E_MULDIV<4:0>
and E MULDEN from the
microcode
are
applied to all chips
through
the
MULT
fanout (MULTFAN)
logic. (See Tables 2-46 and 2-47.)
(PS)

Each chip has
a
3-bit
PS
input
hardwired
to
the code that defines
its
order
of
byte
significance.
(Byte 7 is MS; Byte 0 is LS.)

2.3.3.4

byte,

Multiplier

the

Operation

microcode

multiplier

Starting with the LS multiplier
the
stored
multiplicand
with a

each

cycle,

applied

each
partial
result
1is
multiplier loop (MULTLOOP)

passed
lines.

The

Each

byte

supplies

multiplier

first

using

multiplier

E MULDIV

bytes

1is

using

code

(hex),

sent

byte

code

applied

the

of
the

byte

containing

the

multiplier

the

multiply

be
end

the

this

The

the

last

STORE

part

separate

the

long

and

the

result

but

correct

only

the

through

multiplier
with zeros.

the

and

the

sign

multiply

bits

cycles

using

for

all

must

code

bytes

have

8
is

been

G format

This

passed
during

appears

next
is

loops,

the

bus

the

byte

write
the

the

bus

For

discarded.

represents
part
of
the
that no traps may be

bits

time

microinstruction.

usually

For

a
an

required
provoked

stored

can

the

signal

the

and

bus

sent

masked,

XALU

after

using

internal

and

rounded.

MUL

NORM

decrement

occurs,
then

can

also

SALU

the

The

logic

the

result
the

is
bus

allowing

the

merged

with

BP bus.

normalized
by

over

bits

can

the

multiplier

(hex).

output

from

the

sent

9--B
LS

byte

the

producing

fixes

the

normalization

asserted
A

rounding

product
round

result

trap.

the

XALU

increment

carry-out
The

ROUND

propagating

the

remainder.

prescale

result

carry

the

and

The

microsubroutine

byte

and

hardware

performed

multiply.

exponent

rounded

the

chip

loop,

multiplier

sent

and

fields

also

the

first

main

multiply

this

4--7,

TRAP

far
is

byte

result

can

Because

result.

BP bus.)

<cycles.

performed,

the

RESTRICTION

cycle

exponent

from

byte

cycle

codes

multiplier

The

multiply

main

thus

this

ALU

function

bits

and

multiply,

sent

sign

first

multiply,
this
a MICROCODE

with

following

last

(the

microinstruction,

floating-point

integer

the

logic

generated

current

result,

partial

byte to obtain the required sign bits).
(For
mantissa is always positive so a byte of all

the

(Because

new

on APORT<23:16>,

sent.)

product

middle

one
the

MULT

the

<15:08>.
the

each

can

the

required on the first multiply cycle
Thereafter, each of the next higher

(hex).

sign-extended by
floating-point,
zeros

byte

generating

mantissa

one

the

involves

three

not

byte-aligned,

operands

either

the

shift

bits

left,

then

VII 2-95

three

necessary

times

G format

multiplicand

bits

back,

and

the

filling

Two
cycles are required to store an F_format multiply result with
normalization
and
rounding.
This is because the rounding occurs
late
1in
the multiply cycle.
The STORE order is performed twice,
with the result of the first STORE being ignored and the result of
the

second

STORE being

valid.

2.3.3.5
Divider Operation -- The division
nonrestoring
technique that generates one
Both

operands

To start
code
1,

must

algorithm is
quotient bit

based on a
per cycle.

positive.

the division algorithm, the divisor is first loaded using
2,
or
3
(hex),
the
same
functions used to load the

multiplicand.

The
dividend
1is
then
1loaded
and
the
first division cycle is
performed
using
code 18 (hex).
A hardwired left shift of 8 bits
is
1involved in this load.
To compensate, the dividend must first
have
been
right-rotated
by
8
bits.
At
the end of the first
division
cycle,
the MS quotient bit is
output at register write
time
and
written
to
BP
BUSK16>.
The division algorithm then
continues,
using
the
main division loop function code 19 (hex),
which generates

one

quotient bit per cycle.

On the last cycle, the last divide loop is coded and the remainder
is
generated.
The
remainder
is correct if it is positive.
If
not,
it
must
be
corrected
by
adding
the divisor to it.
The
gquotient then requires that a value of 1 be subtracted from it (if
the
remainder
was
corrected).
Function codes 5 and 9 (hex) are
then

used

to output

the

remainder.

For
an aid in implementing the H format divide, it is possible to
divide
an
arbitrarily
large dividend by the 56-bit divisor.
On
each
division cycle, APORTK15> is shifted into the LS bit of each
partial result (under normal operation these bits should be zero).
The
MS
part
of
the
dividend
is
1initially
1loaded
into
the
multiplier/divider.
Thereafter, the remaining bits are shifted in
one bit at a time on each successive cycle.
The
LS part of the dividend must be shifted left by 1 bit on each
division
«cycle.
This
works in conjunction with the 1-bit shift
required for quotient accumulation.
As the dividend is shifted in
from
its
MS
end,
the new quotient bits are shifted into the LS

end.
time,

By
supplying
the correct part of the dividend at the right
it 1is possible to perform divides of large dividends.

VII

2-96

SECTION

CACHE

BOX

LOGIC

(CBOX)

CHAPTER

INTRODUCTION

1.1

CACHE

As
of

Figure
three

BOX

1-1

SYSTEM

DESCRIPTION

illustrates,

the

VAX

8800

cache

subsystems:

Translation

Cache

NMI

buffer

box

(CRox)

consists

(TR)

interface

The

B
is
a
address-to-physical

hardware

mechanism

address

that

speeds

virtual

translations.

NOTE

Cache

and

without

The

the

translation

holds

taken

trap

routine

the

TB.

control

bit).

perform

performs
receives

instruction

The

also

the

MCAs

sent

the

NMI

1is

made

reference
when

addresses

miss

data

cache
as

And,

for
in

address,
1is,

and

address

the

these

and

used

occurs.

REF/INVAL

received

the

The

cause
it

the

into

address

TB,

the

address
PA3

write

The

from

NMI

VIIT

1-1

physical

and

modify

that

stored

the

cache

receives

CMD

bits

vector

used

output

<31:00>,

CACHE

<31:00>
This

<29:00>

holds

field

functions.

<15:02>.

where

<28:02>

from

data

address

and

write

reads

also

address

the

<29:16>

cache.

interface

miss

use.
the

required

protection

physical

process
Within

PA3

TB,

occur

cache.

the

future

the

will

translation

virtual

check

produced

produces

matching
to

EBox.
be

made

TB.

exists

microtrap

(that

hardware

how

the

physical

virtual

from
entry

the

vector

data

<03:02>

required

translations

address

address.

use

out
the

the

information

address
a

address

physical

cannot

address.

virtual

unavailable,

data

addition

accesses

physical

Subsequent

page

The

for

the
1is

calculated

translation

translated

memory

plus
MDNUM

cause

points

TAG

the

whenever

and
is

cache

with refill data
refill/invalidate

the

NMI

interface

NMI

DATA

<31:00>,

when

cache

The
cache
1is
a
hardware
mechanism
that provides the CPU fast
access
to
frequently-used
data.
It is addressed by a physical
address
vector (PA <15:02>) produced in the TB. If the referenced
data

in the cache,

it will be

read

from the cache and

no memory

request
1is
required.
However,
1if the referenced cache data is
unavailable,
a
request to memory is made to obtain it. Returning
refill
data
1is
sent
to
the requester and is also written into
cache.
Subsequent use of the data causes it to be read out of the
cache.

The
cache
is
"read
allocate
only";
a
new cache location is
a write updates the
and
occurs,
miss
read
a
after
only
created
cache
if
it
1is
a
<cache
hit.
However, if a write does hit in

cycle,
"delay
write

the
next
possible
cache
write
algorithm"
1is used

reguest is stalled. Instead, a
to update the cache on the next

cycle.

The
cache
1is
written by the EBox (by means of WBUS <31:00>) and
refilled by the NMI interface with MD BUS <31:00> data by means of
the
MD BUS. It sends data to the EBox ALU as A CD BUS <31:00>. It

also
file

sends

and

CACHE DATA BUS

the

<31:00> data bits to the EBox register

IBox.

VIIT

1-2

WRITE DATA
waus <31:00>

LOGIC

READ/WRITE

CACHE

DATA

CD BUS<31:00>

BA RREAM

TRANSLATION
BUFFER
PA<15:02>

r\,TO

IA»ALU

(FIG.2-1)

READ/WRITE DATA

CACHE DATA BUS <31 :00>‘

EBOX

STREAM DATA

IBOX

B_EflL_Pfill

ITIA
¢-1

VA<31:00>

CDP

RTUAL/PHYSICAL
DRESS

FROM
EBOX

0,1

(FIG.2-10)

> <
o=

S(N D |
]
3

EBOX SLICE

PA3<29:16>

NMI

INTERFACE

MD BUS<31:00>

(FIG.2-15)

____]
WRITE/READ

MISS

)

REFILL

DATA

=
=z

ADDRESSES
»

PA3<29:00>

PA/DATA

NMI

REFILL/INVALIDATE ADDRESSES
REF/INVAL

ADDR/DATA

<31:00>

«28:02>

SCLD-300

Figure

1-1

CBox

Block

Diagram

interface

NMI

The

All

subsystems.

the

1is

requests

CPU

1interface

memory

and

I/0

and

memory

subsystems

I/0

are

interface.

processed by the NMI

NMI interface provides the control and data path by which th e

The

communicates

CPU

uses

interface

the

When a cache read misses,

the NMI.

address

read-miss

the NM

to build an NMI command/

The TB
transaction and then sends the address to memory.
address
free to process additional CPU requests,
become
then
cache
and
When
NMI interface handles the transaction to memory.
the
while
the NMI

memory data arrives,

Takes control of the cache
Loads the data into the cache data store

1.
2.

Validates the cache tag valids with the new tag address.

When

write

interface:

the

data

completion

executes

CPU

memory

a write, the NMI interface transfers the

making

without

the CPU wait for a write

to memory.

usage. Any
cache or memory data defines its
of
destination
The
destined for the EBox is data stream, or D-stream data. Data
data
or I-stream data.
1IBox is instruction stream,
the
for
destined

I-stream data is held in a 4-longword instruction buffer (IB). The

content

the

1IB is always

interpreted as macroinstructions by

It is used by the IBox decoder as the basis for forming
the IBox.
microcode and, thus, starting
VAX 8800
the
into
entry points

the
to
refers
I-stream
an
Normally,
execution.
microcode
contiguous set of longwords within a page currently being fetched.
1is when the next longword being fetched is not
I-stream
A "new"
the

contiguocus

one.

for

the

destined

Data

EBox

1is

used

data

an address

It can only be requested by microcode and is always
calculation.
register. The MD number is a
(MD)
into a memory data
written
and is used to
the microcode
1in
field
specification
register
of eight possible MD registers for the destination of
select one
the

read

data.

All
D-stream
read
accesses
must
specify
a
known MD register
number; the MD number must be sent along with the D-stream data to
the

EBox.

The

EBox

uses

the MD number to write the data into the selected

GPR

file.

When

microcode requests a cache read

for an MD register, the MD register is invalidated by
destined
the MD register becomes valid when the data
1logic;
control
EBox
Whenever a reference is made to an EBox MD register that
returns.
it

invalid,

the CPU MD stalls,

VIII

and waits for the read.

1-4

1.2

CBOX OPERATION

The

CBox

These

and

per

instructions

consist

"housekeeping"

The

operates

functions

CACHE

Figure

illustrates

command

and

associated

T7.

The

form

with

CBox

the

address

becomes

available

accessed

during

T9-T10.

data

available.

(or

1is

The

cache)

8800

is,

the

CBox

request

CACHE

wused

signals.

The

cache

tag

and

T10,

the

CACHE

HIT

signal

T8-T10

for

cache

that
<cycle

decode

the

and

address

ALU.

the

data

physical

and

are

cache

instruction.

the

The

store

a microinstruction

determine

TB,

command

the

T9.

the

write

functions

The

from

cycle

CBox

control

available

The

hardware).

CBox

look

cycle

has
and
the
function.

timing.

T7-T8

microcode.

read

instruction
any

c¢ycle

wused

microinstruction
performs

VAX

(that

support

used

appropriate

access

half-cycle

are

half-cycle

T9-T10

CBox

that

the

command.

1-2

received

accesses

functions

CBox-specific microcode

the

data

the

Every

canonical

where

time. The
microinstruction

CBOX CYCLE

T10

CACHE COMMAND

NEXT CACHE

COMMAND

VA RECEIVED

NEXT VA

FROM THE ALU
PHYSICAL ADDR

Access
B

| PUYSICAL
LOOK UP

CACHE TAG AND
DATA STORE

CACHE HIT
CACHE DATA

SCLD-301

Figure

Basically,

the

commands.

the

miss

read

memory
requests

command

address
a

and

obtain
are

needs

read

data

and

miss

command

flow
a

read

NMI

the

VIIT

NMI

data

unless
it

Timing

the

send

the

processed
before

Cycle

occurs,

required

processing,
used

CBox

eventually
the

processed

microinstruction
or

read

1-2

NMI

the

interface.

interface

NMI

for

all

must

transaction

for

received

1-5

similar
interface

cache.

out

interface

All

Whether

does

CACHE

process

not

CACHE

affect

becomes

from memory.

the

write

full

microfield

cache

The

the

depending

«consists

function

the

several

field.

overlapping fields,

combination specifies the following information:

field

being

used.

command - Decoded to control the generation of memory

management

valid

CACHE command - An encoding of the type of CBox function
being requested (for example, read, write). Additionally,
it also specifies whether a physical address or virtual
address

Each

traps.

cycles, when it
read
for
MD number - Only relevant
On any other
data.
read
for
n
the destinatio
specifies
type of cycle, a nonvalid MD number is specified.

Size

- Access

size,

relevant.

1is transparent to the microcode. Whether the data being
The CBox
to (or being delivered) is in memory or in the cache does
written
not affect

its

functionality.

the
part of
command
CACHE
be
can
command
CACHE
a
cycle;
one
microinstruction is completed in
and
microcode
The
cycle.
machine
CBox on every
to the
presented
the CBox determine whether any function 1is performed as a result
is unavailable for a particular
CBox
the
I1f
this.
of
the CPU will stall. The default state of the
microinstruction,
Relative

microfield is
1.2.1

the

CPU,

the

interrupted as a "no operation"

CBox Cycles

request.

or cycles, based on the
The CBox performs certain functions,
Table 1-1 lists and
microcode.
command it receives in the VAX 8800
describes

the CBox cycles.

Table
CBox

Cycle

CPU

1-1

CBox

Command

Cycles

NMI

Function

PIBA

Quiescent

Noop

None

Missed

Read

None

arbitration

Write

None

arbitration

PIBA

Noop

None

Yes

Don't

command

care

cache

Yes

Refill

Stall

cmd**

Refill

arbitration

Invalidate

Stall

cmd**

1Invalidate

arbitration

Stall

cmd**

Noned

arbitration

* %

returns

PIBA

does

CPU

command

will

stall

until

not

commands.

Not

really

read

that

l1.2.1.1

the

NMI

the

condition

for

quiescent

Page

<cross

command

with
The

following
®
®

the

with

Second

cache

been

the

1IB,

conflicts

the

new

the

CPU

applicable

state

I-stream

data

the

1is

control

delivery.

The

state:
-

The

state

has

occurred.

Whenever

was

set

I-stream

fetching

fetch

and

fetch

stopped

crosses

is
prevented
I-stream fetch

the

quiescent

hits

This

current

further

I-stream

command,

Not

until

page

until an LD PC
on another page

address.

incremented,
and

access.

paths.

I-stream

access

clear

CPU

cleared.
an

translated

octaword

has

When

completion

additional

state

sets

cycle

the

make

quiescent

for

miss

further

new

The

not

completes.

but

1last

cache

there

quiescent

the

conditions

misses,

the

does

address/data

clearing

PIBA

cache

boundary,

accesses
set

function

activity,

State

Quiescent

NMI

PIBA

conditions

the

uses

arbitration;

overridden.

Quiescent

mechanism
following

have

the
PIBA

starts

1-7

new

refill

data

accesses

fetching.

VIII

refill

state.

can

I-stream
return

fetch.
The

has

been

sent

made

without

1.2.1.2

Read

Cycle

read

cycle

can

requested

only

microcode.
The
microcode
specifies
an
MD number, which is the
destination of the read data and the size of the read. The address
of the read is latched at the input of the TB.
If

memory management

errors

are

detected,

trap

generated.

the
address
does
not
cause a trap, and the read data is in the
cache,
the
read
1is
a
cache hit and it takes only one cycle to
complete.
The microcode request is received at T7 and decoding is
started.
The VA is taken from the latched output of the TB at T8.
The
address
translation
RAM
1in the TB is "looked up" in the T8
cycle.
At

T9,

the

physical

address

selected

and

latched

the

output

of
the
TB.
During
T9,
a
tag
and data store in the cache are
addressed. The data becomes available at T10. If the read caused a
cache hit, the data is taken by the EBox and eventually written to
the
specified
MD
register. If the read misses in the cache, the
CBox NMI interface initiates a request to memory for the data.
l1.2.1.3

Write

The microcode
number
from
a

Cycles

-- Write

specifies

the

because
read
data
VA latch at the TB

cache

by means

Writes

can

address

the

are

size,

requested

but

does

not

by microcode.
specify

an MD

1is not expected. The address is taken
input, and the data is supplied to the

WBus.

with

requires

cycles

write

use

virtual

the

physical

for

address.

translation.

virtual

any memory

management
problems
occur,
a trap will be generated. Otherwise,
the
TB supplies the physical address needed for the cache access.
If
the
EBox specifies a physical address, the TB is bypassed and

the

address

The

CBox

writes

implements

to memory.

as
soon
as
these writes,
The

taken

CBox

required

directly
a

buffered

the

Latch

write-through

Write-through means

that

complete

delay-write

write

that

algorithm

updates

the

algorithm

writes

possible.
Buffered means the NMI
buffers them, and then sends them

1implements

out

TB
to

input.
control

to memory

interface collects
to memory.
[]

the

HAR
TS
- ¥
N\

ru~rlac
"
P

cache.

The

ave

A
e S

first

cycle
1is
used as the look-up cycle to determine if the write hit
in
the
<cache. If the write hit, the write must update the cache.
And,
1if
the
write
did
not
hit, the write does not update the
cache.
If

two

write

cycles

occur

consecutively,

any

CBox

request

that

follows
the
write
must
stall
for
one
cycle
while the write
completes
the
wupdate
of
the cache. Thus, the CBox implements a
"delay
write
algorithm", If a write hits in the cache it updates
the cache only during the next occurrence of a write {that is, the
write to cache is delayed until the next write).

The

first

cycle

following
a

cycle,

the

write

perforwms

cache

physical

address

the

delay-write

look-up.

write

During

loaded

the

into

address
buffer (in the TB)
and the data is loaded
delay-write data puffer (in the cache).
If the next cycle
is
a
read,
both
the
write
address in the delay-write address
buffer
and
the
data
in
the
delay-write
data
buffer
remain
unchanged.
If
the
next
cycle
1is a write, the write performs a
look-up
by
addressing a tag store in the cache.
The delay-write
address
in
the
TB is then sent to the cache data store, and the
data
in
the TB delay-write buffer is written to the cache,
if it
was previously a hit.

into

NOTE

the

cache

from

1.2.1.4

The

address

latch

updating

was

control

PIBA

longword

write

-~
the

the

The
TB.

I-stream

contiguous

within

page

will

three

will

The

start

Cycles

Writing
Flushing

the

Checking

the

The

the

address

can

miss.

Any

the

and
be

the

contents

holds

the

page
be

cycles make

context

boundary.

each

the

If
any

the

PIBA
then

the

new

exclusive

use

PIBA
the

point to
addresses
crosses

further,

a
of

successful

PIBA

microcode

fetch

address

incremented
when

incremented

I-stream

the

fetched.

memory management

loading
TB

the

miss.

and

the

issues

page.

the

TB.

They

flushed.

this

the

page

The

table

latch

entry

(PTE)

taken

into

the

source

data.

reference

Typically,

after

write

TB means

result

entries.

always

in the TB is
1is not used

not

new

a miss,

the

functions:

Writing

informed.

command

1.2.1.5
have

longwords

boundary,

refers

PIBA

data

the PIBA
The
TB

prevents

cache.

PIBA

The

delivery of IB data,
the
next
longword.
a

previously

logic

This

means

used

invalidating

invalidated

clear

switch.

VIIT

1-9

the

one

entry

after

or more

causes

CPU

reset,

1.2.1.6

Refill Operation -- When a reference misses in the cache,

device.

Data

the

CBox

sends

read request for the data to memory or an 1/0

returned

by memory or an I/0O device, is termed the

refill, or returned data. For the duration of the returning data,
the CBox performs refill cycles, passing data to the IBox or EBOX
of
and writing the data into the cache data store. The number can
d,
require
cycles
of
number
the
longwords returned, and, hence,
be one longword or two octawords. The size of the refill expected
depends on the type of the original read reference.

A read request 1is sent to memory oOr an 1/0 device because of:
A D-stream read miss
An I-stream read miss

®
e

The

I/0 read

address for the refill is the physical address. It is used to

address the cache tag and cache data store during the cache refill

cycles.

Data is returned from memory on the NMI address/data lines. The
received data is sent (by means of the MD-bus) to the cache data
store and the cache data bus. The first longword is always the
data missed in the original reference. For D-stream Or I/0 reads,
this 1is always passed to the EBox. I-stream data is sent to the
IBox only if it can accept the data. All the refill data is
written to the cache data store and set valid, except if:
°

The refill is for an I1/0 device

)

An error occurred during the refill

The cache

is off,

The size of the refill data determines the number of refill cycles

required. The CBox determines the size of the refill expected by
the type of read reference made. If it has been waiting for a
longword return and, instead, a hexword is returned, this is an
T AnetI
A

ryatirrn

error condition.

.
(termed
"first-octaword refill"), a minimum gap of two nonrefill cycles,
and then four additional, consecutive data refill cycles (termed
"second-octaword refill"). A refill size of one longword takes

¢
A hexaword refill requires a minimum of 10 cycles for
cycles
tive
consecu
data
four
of
consists
It

only one cycle to complete.

1.2.1.7 Invalidate Cycle -- The NMI interface interprets writes
on the NMI, with any ID other than its own, as an invalidate
cycle. The address accompanying the write is taken from the NMI
and then sent to the TB as the source for the cache physical
address. This is then used as the physical address to look up the
cache

tag

store.

Invalidates
cycle

1is

invalidate
the

can

take

wused

address

cache

and

hit,

then
invalidated;

one

two

the

look-up

misses,

then

further

modified

cycles

cycle

the

for

CBox.

cache

The

hit.

first
If

the
the block being modified is not in
action is necessary. If it was a cache

data
is
in
the
subsequent
accesses
must

<cache

and

must

access

the

data

from

the

available

for

memory.

The

address

1in

two

cycles.

The

invalidate
1.2.2
A

the

CBox

stall

CPU

unavailability

Each

latch

the

current

are

blocked,

the

cycle

the

condition,

CPU

that

thereby

data

two

address

stalls

from

the

set

processing

due

current

required

the

retain

stalls,
operation, the

normal

When

CPU

stall

happens,

the

information

(for

clocked

stalled

by a
clock

clocks

retaining

stalls:

stall

stalls

occur

invalidates,
the

whereby

MD stalls

path

types

stalls

during

cache).

affected

can

the

requested

made

the state of the "stalled" latches
occurred. Thus, microinstructions that
completed after the stalling conditions are

before
stall

are

when

During

A clocks.

cleared.
There

not

pipeline cannot continue
certain resources or data.

clock."

1is

the

instruction)

functions

cause

cycle

store

Stalls

"stalled

data

cycle.

microinstructions
to

refill/invalidate

cache

when

being

or
again

cache
The

CPU

for

the

when

the

(for

CPU must

requests

other
next

example,
wait

The

tries
and

CPU

the

because

until

cache

cycle

the

same

can

wait

must

stop

present

use

data

the

data

for more

time.

VIIT

cache

refill,

some
has

and

1-11

data

not

that

yet

reference missed
arrives

and

NOTE

CPU

the

example,

microoperation.

The

but

(for

cycle.

CPU
cycle

functions

returns).

during

occur
by

the

used

than

one

MD at

then

was

arrived

the

execute

CHAPTER
FUNCTIMNNAL

2.1

CBOX

SUBSYSTEMS

2.1.1

Translation

Because

the

address

must

memory;

the

CBox

VAX

translations.
address
that
The

The

DESCRIPTION

Buffer

8800

system

the

buffer

Read

Refill/invalidate

and

the

Read

Cache

Write

write

read

Delay-write

°®

Cache

required

always

perform

physical

addresses

types

the

from

EBox

the

address

NMI

interface

vectors:

buffer

TAG
consist

Refill/invalidate
Write

not

the

algorithm

does
receives

from

addresses

instruction

inputs

2-1

performs

virtual

address

miss

Physical

Figure

every

physical

miss

read

data

(TB)

TB
it

addresses

following

CBox

addresses,

actual

receives:

buffer

sometimes

its

translation.

translation

produces

virtual

translation

However,
no

uses

translated

translations;

require

DESCRIPTION

data

for

the

illustrates,

input

RAM

match

RAM

latch

of:

data

(addresses)

RAM

the

consists

latch
MCA

bypass

VIII

2-1

from

of:

the

NMI

interface

| CBOX ADP MODULE
ADP CS2

DATA

<02:00>

IFB%)'(,A

180

MODULE

LATCH

.
CMCF«<02:00>

(SH 2

OF 10)

LT VA<31:18>»

VA
LATCH
(SH1 OF 10)

111N

(SH1

¢—C

TM
RAM

TB TAG
<30:18>

TRANSLATION OK . TO

OF 10)

<03:00>

(FIG. 2-5)

M BIT

TB DATA<29:09> o TO
TB DATA

<15:09>

SH.2

PABH

MCA

(FIG

<16:09>

FROM

NMI INTERFACE

<15:2>
PA3<29:16>

‘

B\CHE

DATA
PATH
T0O

CACHE
TAG,MATCH

(FIG.2-10)

LT VA<29:16>
VA<08:00>

2-7)

(FIG 2-10)

LT VA<15:09>

PA LATCH

PA2C
(SH 3 OF 10) | <16:00>

FIG.2-5

(BOX

(F1G.2-5)

SEQ
MODULE

INTERFACE
QEIDCRE/gATA REF_INVAL<15:09>

|
[

MATCH
(FIG.2-1)

PROT

FOM

> CACHE

L TO

FROM
EBOX

TB BR COND<01:00>

EM,

WCS

CONDITIONS

TB VALID,

...,..S,QEEP.QEfi,,,,,,,,__,,

VA<31:09>

—
FROM
IBOX

(SH 2 OF 10)

I
.

TRAP

T8 MATCH

> MCA

TBM CTRL<02:00
>
<

PA3<29:00>3

> TO SH2

CACHE CMD
MONUM<3:2>

PABL
MCA

TM (SH 8 OF 14)

PA
UNBUF
0802

<08:92>

NMI
INTERFACE
ADDR/DATA

SLICES

(F1G.2-12)

—CACHE HIT

~..
REF
ADDR/DATA SLICES _ INVAL<08:02
(FIG.2-12)

SCLD-302

Figure 2-1

Translation Buffer - Block Diagram

Basically,

the

plus

EBox,

determine

held

MCA,

the

address

cache

input

received

command

operation.

contains
<31:00>

virtual

The

CMCF

virtual

latch

VA bits

address

and

then

RAM

TB
RAM,
and
the
physical-to-virtual

<02:00>
in

from

bits

that

bits

distributed
bypass

<31:00>

field
to

logic.

<31:09>

the
If

address

translation

for

address

from

the

input:

)

The

required

The
TB

accessed
match

Page

following

fault

the

Access

violation

Memory

trap

Modify

bit

physical
sent

when

not

wused;

When

the

check

determines

the

data

address

that

RAM.

the

are

checked:

assembled

received

in the PA latch
<15:02> bits.

from

logic

the

produces

the

physical

used for an address translation, and a
does not contain a valid translation, the

data
into
procedure
1is

the
TB
repeated

RAM
and
to
produce

required

cache

store

physical

address

vector.

wvirtual/physical

address

VA<31:0>

bits

data

EBox,

EBox
writes
the
physical-address-access

the

validity

conditions

store

the TB RAM bypass
PA latch.

the

RAM

vector

cache

physical

for

trap

address

RAM

input

checked

RAM

crossing

However,

address

and

1is

translation

accessed

EBox

MCA.

Presence

physical

TB match

received

the
the

from

the

EBox:

)

<31:09>

The

page
®

Data

the
Thus,
and

and

corresponding

frame

VA<8:0>.

number

within

PFN

wvirtual

VA<8:0>,

specifies

Figure

2-2

page

frame

translation

number

(VPN).

the

for

VPN

the

(PFN).
page

full

virtual

physical

specified

address

and

(virtual

input

physical)

pointed

VA<K8:0>.
is

physical

comprised
address

illustrates

VIIT

2-3

the

VPN

(VA

comprised

virtual

address

<31:09>)
the

fields.

PFN

3222222222211 11111t11100000O0O0O0O0O0O0
098765432 109876543210098765432710

3
1

‘

VIRTUAL PAGE FRAME

TB TAG

TB INDEX——P1¢—SPECIFIES DATA—p
WITHIN
A PAGE

——P‘ ¢— MSB OF TB INDEX

USED TO MAP SYSTEM
OR PROCESS PTES

SCLD-305

Figure

2-2

Virtual

Address

Fields

PFN is a part of a page table entry (PTE) data structure that
The
The CBox TB RAM, in
information specific to the page.
holds
the
a subset of
also holds
PFN,
the
to holding
addition
(the protection field and the
PTE
the
1in
included
information
modify

bit).

2.1.1.1

mechanism
received

loaded

Latch

for

from

The

high-order

bits
It

EBox.

the

1latch (Figure 2-1)

is the holding

of the VA <31:00> input

<31:09>

is clocked with a STALLED A CLK and

During a VA stall,

by means of LD VA EN from the PABL MCA.

it holds bits <31:09> until the cache can process the command.

Figure

2-1

LT
VA
<31:16>
with
compared
i
R
ae

.
ermine

s £
1if

<31,17:09>

<09:00>,

and

bits
to
the
TB
match MCA where it is
TB RAM TB TAG <30:18> output bits to
he
T
TB

has
hit 1~
4
hit

bits

PVA

o
has

occurred.
~
¥
occurre

FVA

<K09:00>

<09:00>,
to

the

(physical)

address

control/status

signals.

LT VA <29:16>

bits to the

PA latch.

translated

the VA latch sends:

illustrates,

and

TVA <09:00>, SVA
RAM to access

also

produce

2.1.1.2

RAM

The

virtual-to-physical
system

PTEs

<30:18>

and

<09:00>,
a

flush

and

512

process

addresses

provides

entries

(PTEs),

PTEs.

bits

cache

receives

FVA

of 1K calculated
consisting of 512

data

<09:00>,

TVA

bits

and PVA <09:00> from
signal from the cache

SVA

the VA latch, plus write enables
control MCA (Figure 2-10).

and

RAM

VPN

The

VAK31>

directly maps

wused

translations

and

VA<17:9>

used

RAM

table

<09:00>,

Bit

page

are

the

map

the
other
to map the

bits

one

<31:09>

half

into

the

RAM

entries.

for

system
half for process translations. Bits
system and process PTEs into the 512

entries.
NOTE

the

VA<8:0>
Whether

determined
received

all

not

address

1in

RAM

not

physical

used

RAM

the

traps

wused

traps

the

use

are

from

are

the

blocked

from

RAM,

the

four

sets

used

access

the

RAM,

and

perform

input

RAM

1is

produce

physical

address

bits

wupper

<15:02>

for

PABH

bits

are

MCA

wvalid

pointed

low)

MCA

addresses

the

not

and

otherwise

set,
are

1logic

the

taken

and

memory

PAl

output
used

not

virtual
used

Instead,

the

address
produce

RAM

latch

high)

MCA

produce

address.

<08:02>
the

form

store.

produce

if
the

comprises

the

And,

address,

from

physical

output

the

written

being made.
virtual
are

from

was

The

data

vector.
-

that

instead
RAM

received

address

access

cache

<09:00>

contains

<15:09>

the

bit

all

output.

bypass

buffered

translation

compared

determine

data.

sends

cache

the

(unless

bypass

that is
is set,

translations

MME

<15:09>

the

address

<15:09>)

PAl

the

for

occur

bits

physical

RAM

bit
bit

This
the

are

<15:02>

bypass

used

the

would
PABL

(in
bits

upper

then

(physical

address

bits

cache.

Whenever

MCA

cache

bits

bypass

the

translation

occurring.

EBox

for

input),

the

with

address

bits

sends

used;

(PA2

the

vector

(physical

combined

for

EBox
<31:00>

<15:09>

logic
the

address

the

used

from

address

RAM

checks

<31:09>

bits

enable (MME)
When the MME

translated

When

the

for

the

When

are

the

pages,

translated.

translations;

latch

into

allowed

command).
for

addresses

management

Within

translates

need

references

management

defined

the

not

by setting a memory management
from
the
cache control logic.

virtual

memory

RAM

match

access

against

the

And,

address

TRANSLATION

MCA

then

the

the
is
OK

made,

LT VA

produced

the

signal

address

data.

VIIT

2-5

the

vector

RAM

bits

determined

determines

physical

the

<31:16>

TAG

the

<30:18>

TB match

translation

valid,
cache

cache

the

match

data

contains

MCA.

entry

the

buffer

TB match
The

being

required

18T

110

aanb1g

ENABLE .| RAM ARRAYS WRITTEN

T8D [TBD1[TBD2[TBY
|0

|1]TB

TAG

DATP<15:07>,

TB VALIDS,

PROT<31:00>

VALIDS

2ND

191

3RD

TB DAT<29:10>, VALIDS, MBIT

FLUSH

TB VALIDS

RAM

INFO

THE TAG AND

WRITE

PFN(8-0),

WRITE

THE

VALID
RAM
TBV

VA LATCH
HOLD THE TB

INDEX

TB VALID

PROT AND MBIT AS TBDATA2

PFN<20-7>

AS TBDATA1

DATA

RAMS

PAlI

A,B<15:09>

DATA<29:09>

e e

’

PROT,
MBIT

3eyy
v

B TAG
<30:18>

PROT<3:0>

TAG
RAM
TBT

9243

MBIT

SLOW
RAM
TBD 1

9-¢

IIIA

FAST
RAM
TBD2

se3ea3sniiT

INDEX

WRITE

SCLD-304

Figure

2-3

Write

Sequence

Diagram

WYY

LOAD TB

wuexbeip petjridurs

SEQUENCE

W
N =
g

TRUE
B WRITE

£-¢

RAM

WRITE

CYCLE

*sdousnbes o31aMm

Figure

2-3

illustrates,

Flushed

Written

)

Checked

The

data

RAM

entries.

context
The

TB
has

RAM

address
Table

bits

has

2-1

written
being

2-1

Protect

type

Access

RAM

is:

invalidate

1is

(clear)

flushed

one

after

made.
with

page
it

table

does

not

the

encoding

<03:00>

after

the
data

the

PROTection

Coding

and

Allowed

0O>

U
NONE

NONE

RES

NONE

RW
NONE

NONE

NONE
NONE

NONE

VIIT

2-7

field

Access

reset

valid

Codes
<3

contain

allowed.

Field

CPU

entries

made.

access

PROTection

that

correlates

the

Table

been

determined
reference

Typically,

switch

MCA

flushed

the

its

match

for

the

<03:00>

Allowed

2.1.1.3 TB Match MCA -- The TB match MCA (Figure 2-4) checks the
As Figure
the TB RAM virtual address translations.
validity of
<30:18>
TAG
2-4 illustrates, the TB match MCA checks the TB RAM TB
If
latch.
VA
output bits against the LT VA <31:16> bits from the
the
of
the two inputs do not match, or if the TB VALID bit output
TB RAM has not been set, a TB MISS TRAP error signal is generated,
indicating that the translation referenced by the EBox is not in
a valid translation, a
the TB RAM contains
If
the TB RAM.
TRANSLATION OK signal is sent to the cache control.

The TB match MCA is controlled by means of a TBM CTRL <02:00>
field received from the EBox and a MME signal from the cache
control.

Table 2-2 provides a correlation of the TB match MCA operations to
the type of TB match control bits TBM CTRL <02:00> and the setting
bit.

Table 2-2

TB Match MCA Operation Coding

TB
State

Encoding
<1>

<TBS>

TB MISS

ACV

MBIT

TB OK

MME OFF

the MME

TRANSLATION

TBM CTRL<2:0>

BUFFER

MATCH

(TBM)

MCA

MATCH
CONTROL

ACCESS
VIOLATION
CHECK

ACV TRAP

ACCESS
N

READ

GHECK

VIOLATION

MNE

TRANSLATION

PROBLEM

TRAP

CHECK

TRANSLATION

B S S

PROT<3:0>
CUR MODE
A<1:0>

o—¢

IIIA

NO TRAP

>
.|

STATE

TB BR
COND<01:00>

TB_MISS

TAG
LT VA
<30:18>

MATCH

TAG

<30:18>

MISS

TRAP
»

NO TRAP
MBIT
TRAP

MBIT

TRAP

SCLD-303

Figure

2-4

Match

MCA

Simplified

Block

Diagram

2.1.1.4

physical
been

the

RAM

address

Bypass

1input

The

RAM bypass logic produces a

the PA latch whenever the TB RAM has

It consists of a PABH MCA, a PABL MCA,

turned

off.

fcllowing

types

and part

logic in the cache match MCA. The TB RAM bypass logic produces
of

addresses:

PIBA

®
®

Delay write
Refill/Invalidate

PIBA Addresses

A PIBA address contains a physical address that points to the next

longword of I-stream data to be fetched. Because the PIBA is used
to store a physical address, and fetches contiguous longwords from

memory,

address

The

translation need only be done once per page.

address

translation

1is

performed

and

the

PIBA is loaded

whenever:

®
®

There

Jump

A conditional branch is successfully taken, or
A PIBA page crossing has occurred

Delay-Write Addresses

the address of a write waiting to be
1is
A delay-write address
address held in the TB RAM bypass
The
<cache.
the
into
written
corresponds to the data held in the delay-write address buffer.

DELAY WR ADDR <15:09> is loaded during a CPU write operation, with
either TB DATA <15:09> bits, or the LT VA <15:09> input bits to
the PABH MCA. This delay-write address is used to update the cache
1if the write was determined to be a hit in the cache,
data store
or to check subsequent CPU reads to determine if they hit in the
same cache data store location that is waiting to be updated.

MCA contains only the <15:059> bits of the delay-write
this
Since
low bits <08:02>), it generates the
(PABL MCA contains
address
is used by the cache match MCA to
that
signal
HIT
WR
DELAY
PART2

generate the DELAY WRITE HIT signal.

PABH MCA
The
during
loaded
by the signal

NOTE

DELAY WR ADDRS latch is
an A clock, and is gated

DELAY WR LOAD.

VIII

2-1@

Refill/Invalidate
When

reference

request

for

r~turned

data.

performs

writing

the

data

refill
a

and

data

into

Within

sent

the

The

and

data

the

tag

Q2
in

the

CBox

sends

the

I/0

device.

the

refill,

The

returned

the

CBox

IBox

EBox

and

the

Read

from
the

one
TB

these

during

NMI

interface

(because
of

these

RAM

bypass

MCAs

the

refill.

MCAs

for

input

the

refill

This

logic:

PABL

MCA

produces

the

refill

address

low

bits

MCA

produces

the

refill

address

high

bits

cache

The

REFILL/INVAL

increments
longword

during

the

has

low
the

refill
MCA

MCA

match

address

the

proper

PABH

tag

refill

MCA

the

hexword

gated

bits
incremented,

<15:09>

latching

these

clock

During

into

for

the

cache

hit)

bit

Figures
the

PIBA,

this

MCAs

that

2-5
TBR

was

the

The

CLK,
the

address

determine

that

being

REFILL/INVAL
and is
signal

written

address

loaded into an A
LD REFILL/INVAL.

and the PABL
point to the
to

the

cache

received

latch, which
As with the

operation, the REFILL/INVAL address is loaded
with the address (which had been checked for a
present

2-6,

RAM bypass

delay-write,

refill

the
REFILL/INVAL ADDR do not have to be
section
of
the
PABH MCA simply provides

appropriate

and

the

bits.

invalidate

three

valid

checks

exists.

is stored in the three MCAs,
three bits of the address to

cycle.
B
by

PIBA,

the

cycle.

RAM bypass

PABH

The

was

queues,

<15:09>.
®

read

Data

input,

<15:09>.
®

data

duration

PA within
latch

the

store.

selected

for

held

1latched

1latches
the

device

PIBA

returning

always

file

address

selected

the

cache

The

and

I/0

sending

address

latch

the

cycles,

slices

<cache,

memory

refill/invalidate
address

the

duration

miss).

then

memory

refill

address/data
first

data

the

misses

the

For

The

Addresses

and

the

NMI,

cache

and

are

PABH

MCAs.

PABL

refill/invalidate

VIIT

used

clear

the

locations.

respectively,
and

then

2-11

simplified
They

block

illustrate

addresses

are

diagrams
how

the

produced.

PHYSICAL ADDRESS BYPASS HIGH

LT VA<15:09>

“\\\

PA3

(PABH)

10
PIBA 9

<15:09>

MCA

\\\]
///J

PA2 C<15:. 09>

PIBA

ADDR

TB DATA

LATCH

<15:09>

DELAY

WRITE
ADDR

LATCH

—

DELAY

REFILL INVAL

—P WRITE
:
INVAL | <75:09>
INVAL

PA<15:09>

WR INDEX MATCH

INDEX OC TAL MATCH

///J

o/ ING

)

LATCH

DLY WR HIT
TB

SLCO/SLC1
»

DATA<15:00>

SCLD-306

Figure

2-5

PABH MCA - Simplified Block Diagram

IIT

2-12

[ PHYSICAL ADDRESS BYPASS LOW (PABL) MCA
VA/PA<8:0>

MATCH

ATCH | VA<08:00>

PAGE

HEX

MATCH

ADDRESS
DLY

WRT HIT<1:0> _
>

LD VA

VA<08:02>

DLY

WRITE
ADDR

DELAY WRITE<08:02>

¢el-¢ IIIA

LATCH

DLY WR

REF/INVAL

REFILL

INVAL<08:02>

PIBA
208025

ADD<8:2>

08-

PA<08:02>

REFILL

CONTROL

ADDR

AND

LATCH

LONGWORD
COUNTER

STOP REF

PIBA

»|

INC

LOOP

SCLD-307

Figure

2-6

PABL

MCA

Simplified

Block

Diagram

PABL MCA

functions

include:

Storage and control of

)

bits <08:00>, and the
ADDRESS
WRITE
DELAY
of
Storage
for a match in thi
signal
HIT
WRT
of the DLY
generation
section

the

the PIBA bits

<08:00>

address

Storage and control of REFILL/INVAL ADDR bits

Detection of four microtrap conditions:

)

Unaligned

Page

Unaligned

2.1.1.5

<08:00>

cross

page

cross

Latch

=- The

<15:02>

for

PA 3

<29:16>

PA latch produces

the following

address

vectors:

I",[j

igure

TAG PA

2-7

cache

data

store

for the cache match MCA and cache tag MCA

<29:00>

address/data

the

that

1is

sent

the

NMI

slices

<15:04>

that

sent

the

is a simplitied diagram of the

cache TAG MCA

PA latch.

interface

CBOX ADP

MODULE

PA LATCH
FROM
oass

DATA<29:09>

T<.9_9.1s>

(FI1G.2-1)
FROM
NM!

|
PA3<29:16>

REF INVAL<28:10>

INTERFACE

ADDR/DATA SLICES

(FIG.2-12)

FROM

30P

2710

LT VA<29:16>

TB BYPASS
(FIG.2-1)

;

1:29:165]

‘

'TB

PA SEL|

CACHE

PA3<15:09>

)

FROM

PA2 C<15:09>

SH 1

CBOX CCS

DATA

1<15:095

PA3<29:16>

PA3<29:00>

TAG

p MATCH

> (F1G.2-10)
»

TO NM!

INTERFACE
ADDR/DATA
SLICES
(FIG.2-12)

MODULE
FROM TBr
(BFY%\S;

i
UNBUF PA<08.04>\

—

;?f4

78P

PA3<08>

2/10

FROM VA<08:00> IégTCH
EBOX
TM 5714
LT

<07:00>

73P

PA3<07:00>

8/14'

<7:2>

<B8:2>

<8:4> | LATCH

46P

PA SEL
—_—

08:04
<08:04>

2/10

TB DATA

<15:09>

p |<15:09>
—

TAG PA

<15:04>

PA2 C
<15:09>

|
i

=E20t—£
(F1G.2-10)

PA SEL

PA1

A/B<15:09>

15:2

(TPOG.ZJ)

PA2 A/B<15:09>

PABL

BUFFER|
»l(sH
8
OF 14)

PATH

(FIG 2-10)

PA A<08:02>
PA B<08:02>
<7:2>

SH 2

SCLD-308

Figure

2-7

Latch

VIIT

2-15

Logic

Diagram

The data PA latch produces the cache data store look-up address
vector PA <15:02>. It has the same timing as the tag PA latch, but
in the «case of writes, loaded from a different source (the
is,

delay-write address buffer in both the PABH MCA and the PABL MCA) .

ndex the cache data
latch is used only to
PA
data
the
Because
e L
e
2L
T
bk
A~
1
A
+h
he
index bits (that
a
beyon
bits
any
store, it does not need
needed).
is, PA <29:16> bits are not
o

11C

The

PA latch

The data

bypass

RAM

PABH

loaded

with

MCA

o
N\

from:

bits

with

PAl <15:09>

(or from the TB RAM

bits PA2 <15:09>) during a cache

read operation.

The

delay-write

with

address

buffer

in PABL for CPU writes

<08:02>.

The tag PA latch produces the cache tag MCA look-up address vector

The tag PA latch holds the same address as the
TAG PA <15:04>.
data PA latch during all CBox cycles (except the write cycle).

The

bits

tag

reads

(or

and

latch is loaded from the TB RAM with TB DATA <15:09>

TB RAM bypass PABH MCA with bits PA2 C <15:09>) for CPU

"new

PC"

reads.

illustrates

Figure

2-8

(Figure

2-12).

the

bit routing through the TB PA latch

when a refill address is received from the NMI address/data slices

CBCX ADP

MODULE

LATCH

FROMoAss

PROM

_TB DATA<29:09>

<29:16>

(FIG.2-1)

FROM
NMI

27P

REF INVAL<28:10>

INTERFACE

ADDR/DATA SLICES

<29:16>

(FIG.2-12)

“"

FROM
TB

PA3<29 18>

2/10

—_——

LT VA<29:16>

BYPASS

(FIG.2-1)

DATA

| [_—_’(FIG.Z-‘]O)
_I PA3<29:00>

<15:08>

T0
MATCH

PA3<29:16>

PA3<15 09>

FROM

PA2 C<15:08>

SH 1
S

ADDR/DATA
SLICES

CBOX CCS MODULE
FaoM S

I
UNBUF PA<08:04>

EBOX

LATCH

10P

FROM _VA<08:00>y] LATCH
gp

78P

PA3<08>=

—

2/10

8/14

‘

LT VA

}

73pP

PA3<07:00> ‘

8/14

—

2_>_

PA
)

<07:00>

<7:2>

(FIG.2-12)

(FIG.2-3)

TO NMI

INTERFACE

<8:4>|

LATCH
46P

PA SEL|

<08:04>

2/10

TB DATA
<15:09>

49p | <15:09>
PA2 C

TAG PA

TAG

(FIG.2-10}

——_
<15:09>
|

<15:04> CACHE

PA_SEL
PA1

l
(FIG 2-1)

A/B<15:09>

PA2_A/B<15:09>

PABL

—

BUFFER PA A<08:02>

MlShs

14)

Psos 10

=32 CACHE

HT
I

(FIG

2-10)

B<08:02>

<7:2>

SH 2

SCLD-3088

Figure

2-8

Latch

Bit

VIII

Routing

2-17

Refill

Cycle

illustrates the bit routing of the TB RAM the TB DATA
through the PA latch when the EBox makes a virtual address
2-9

Figure
output

reference

to the CBox.

CBOX ADP MODULE

F’A LATCH

FROM

TB DATA<29:09>

FROM
NMI INTERFACE

REF_INVAL<28:10>

e e

TB BYPASS

(FIG.2-1)

(FIG.2-12)
FROM
TB BYPASS
(FIG.2-1)

ADDR/DATA SLICES

LT VA<29:16>

CBOX CCS MODULE

FROM ITB
From

30P | <29:16>

210

EBOX
M

VA<08:00>
2]

8/14

—

LT VA

<07:00>

Q_,<2

TB DATA

I! ,JA3<29'16>

095 !

LS\TCH

¥ (FIG.2-10))
TO NMI

INTESFA(_JrE

SLICES

| l

ADDR/DATA
(FIG.2-12)

I I

—

‘

8/14

PA3<29:00>
I
——i|

PA3<08>]

58P

2/10

l |

‘

I
{

73P

<8:2>

—

PA SEL

PA3<OZ&J

—_—

PA2 C<15:09>

|
<7:2>

<15:09>

. >]
UNBUE_PA<08:04

LATCH
e
8P

PA3<20:16>

(FIG.2-3)
FROM

DA SE!

PA SEL

SFEOM

e e

<29:16>

<08:04>

46P

<8:4> 1 LATCH

1B DATA

<15:09>

2/10

<15:04>

<15:095

TAG PA

PA2 C

ggcr{

T 1AG
(FIG.2-10)

<15:09> |
—____<12.U9>

PA_SEL

]1
|

|
T8
1)<
(F,G_2_

PA1 AiB<15:09>

g
> (FIG
PATH 2-10)
|

i
|

FROM

15 2> o

) >
PA2 A/B<15:09

‘

—

PABL

Rl PA A<08:02 \ |

. (BSU;FEE | PA A<08:02>

OF 14) PA 8.08:02;

t—

__l

<7:2> > TO /
SH 2

SCLD-308C

Figure

2-9

PA Latch Bit Routing

Reference

2,2

CBOX SUBSYSTEMS

2.2.1
As

Cache

Figure

2-10
Data
Tag

illustrates,
path

2.2.1.1
consists

consists

of:

logic

MCA

number

MCA

cCache

Data

Path

move

data

out

cache

MCA

Control
MD

the

MCA

Match

used

DESCRIPTION

Logic
of

the

=-- The cache data path logic
CBox

the

IBox

and

of:

A write

data

output multiplexer

data

store

)

delay-write
cache

data

ALU bypass

write

the

EBox.

latch

multiplexer

buffer

Basically,
°

Data

read

from

and multiplexed
cache

the
)

Alternately,

DATA

IBox,
is

bus

data

the

bits

store

ALU bypass
the

EBox

bits

cache

multiplexer)

and

<08:00>

bits

two

these

data

the

EBox

store

EBox

can

write

destinations.

VIII

2-19

ALU
be

data

bypassed

sent

<08:00>

multiplexer

bypass

cache

means

<31:00>

multiplexed
the

the

file

as
and

<31:00>
(by means

DATA

CDB

EBOX SLICE O, 1 MODULES
CACHE DATA PATH

CACHE WRITE DATA SOURCE
MULTIPLEXER-LATCH

EBOX

WB«<31:00>

WRITE DATA
WBLS
<31:00>
om

CACHE

INPuT
LATCH

DLY WR LD

DATA
LATCH

DATA IN<08:00> _ALGORITHM DATA P
DATA—p
—REFILL
TOIFROM 4—MEMORY
WRITE DATA —
MD BUS<31:00>
ADGHIDATA
SLICES

MEMORY

DATA-

(FIG.2-12)

DATA IN

WRITE BUFFER

<08:00>
WRITE

BUFFER
LATCH

ge—¢

—WRITE DATA—b-DELAY WRITE

DELAY

1IIA

CONTROL
3)
(SH

WRITE DATA
OUTPUT

OQUPUT

BUFFER

MISG

LOGIC

MEMORY
WRITE

TATOM
Wt

—WRITE DATA-

DELAY
EFILL WRITE/- I
DATA
)

<08:00>
10
> sheer
‘

c DB

DATA

INT MD
<08:00>

WBLUF WR ADD<1:0> I TATGH
¥ sELECT

DECODER

WBUF

LATCH

WREN

wlwa Bur |
AD ADD<1:0>

—»

OUT BUF,]
__LD

LATCH

LATCH e

INTERFACE

MD BUS WREN | LATCH

NM! [N
CONTROL

(FIG.2-15)

SCLD-309

Figure 2-10

Cache - Block Diagram (Sheet 1 of 3)

[

. EBOX SLICE 0,1

| CACHE DATA PATH

MODULES
I

CACHE DATA STORE

CACHE DATA

BUS

WRITE

DATA

MUX

READ/WRITE

DATA

CACHE DATA BUS <31:00>

WR DATA
SHEET 1

WRITE,

RD<08:00

REFILL DATA
FROM

» 1BOX

. T0
» EBOX
REGISTER
FILE

READ DATA

DELAY WRITE/-

TRANS-

PA<15:02>

» 10

ALU

LATION
BUFFER
PA LATCH
(FIG.2-1)

SLCO,1

CACHE

DATA SEL

CACHE BYPASS
OUT SEL

SCLD-310

Figure

2-10

| = 19

Cache

Block

VIIT

Diagram

2-21

(Sheet

CBOX ADP MODULE
___TRANSLATION OK

CACHE

MATCH | CACHE MISS

PA3<29:16>
CTAG DATA<28:16>

CACHE

TAG
TAG PA<15:04>

RDp"

CLOCK

> MCA

. 10

» NMI INTERFACE

NMI_IN
CONTROL

4/10

(FIG.2-15)

MCA
4/10

CACHE

CTAG VALID<3:0>

_CTAG WR EN

TRANSLATION

HIT

» BUFFER

(FIG.2-1)

FAOM REFILLING 1B
FROM

SEQ MODULE

.
FROM

oM \TERFAGE

NMi

IN CONTROL

(F1G.2-15)

DLY WR LD A,B
|STALL <7:0>

»)

.
_BUF RETURN TYPE<1:00>

TRAP_SUMMARY

IBOX
(2

MME ON

CACHE NMI CR ID<1:0>_

(/14

»”

ND
M

MCA

CACHE OMD

MDNUM<3:0>

EBOX

_ [ ShKCE 0.1

'SLICE PA SEL A.B

CMSIZE<2:0>

WOS

CONTROL| FORGE DATA VALID [

TB CMD<2:0>

FROM ¢
CACHE HIT<1>

CACHE

CMCF<6:3>

¢¢—¢

IIIA

CBOX CCS MODULE

2114

NMI

INTERFACE

NMi_OUT
CONTROL

(F1G.2-13)

TRAP MD<2:0> =fl%%x

N
DECODER

CACHE DEST<3:0>

WR CDS<3:0>

>
.
>

DLY WR MUX SEL<3:0>
>
WBUF WREN<3:0>

EBOX

0,1
SLICE
COP

SCLD-311

Figure 2-10

Cache - Block Diagram (Sheet 3 of 3)

The

<cache

latch
The

data

data
®

the

store

output

source
Data

1is

loaded

the

multiplexer
directly

from

with

cache
used

the

EBox

delayed

DATA
e

INTernal

the

EBox

<08:00>
MD

MD bus)

input

from

during

<08:00>

the

<31:00>

delay-write

the

NMI

data must

from

multiplexer.

during

data

written

cache

buffer

operation.

(by

means

the

cache

During

buffer

DATA

buffer,

put
on
the
MD bus as MD bus <31:00>, and then
to memory by means of the NMI address/data slices
NMI.
Incoming WBus data <31:00> bits are either:

written
and

the

Sent
WB

write

operation

1IN

directly

<31:00>,

Latched

<08:00>

the

memory,

output

write

data

1is

which

can

data

The

write

buffer

The

delay-write

data

buffer

the

WBus

output

EBox
is

provides

storage

executes

written

read

cache

delay-write

algorithm

operation

data

means

the

cache

requires

data

cache

data

store

held

cache

tag

the

DLY WR

holds

MCA.

°®

The

WBus

)

The

delay-write

°®

The MD bus

(if a delay
<08:00> output of

data

received

(at which
store

placed

1loaded

control

during

signal

MCA.

The

data
write

from

time

the

into

the

store

buffer

another write

into

write)
®

latch

multiplexer,

until:

The

output multiplexer

the
delay-write
data
requested),
the DATA IN
be sent to either:

write

data

delay-write

buffered

1in

write

The

°®

the

control

<08:00>

interface

RAM,

The

CDB

source

delay-write-algorithm

from

when memory

DATA

data

select:
as

write.
®

write

data

the
is

corresponding
written

buffer,

VIII 2-23

from:

data

delay-write

from

for

the

cache

addresses

The cache data bypass and cache ALU MD bypass multiplexers located

at the output of the cache data store are used to select between
the output of the cache data store and the cache write data source
latch. This allows the data being written to the cache data store
to also be sent to the EBox and IBox if necessary, Or in the case

a delay-write hit, to be taken directly out of the delay-write

data buffer.

The ALU MD bypass allows data to be sent more gquickly to the ALU
from the cache data store, instead of through the MD registers. It
contains the same information as the cache data bus, but the data

is wunlatched and, therefore, driven slightly earlier (the input
latch of the ALU has the same timing as the latch that drives the

cache data bus).

The write buffer is a l-octaword (l16-byte) write-only, write-back
cache that is used for writing data to the cache data store or VAX
8800 memory. It allows the following types of large data blocks:
Quadword
Octaword

Grand-floating
Huge-floating
Character strings
Stack writes

to be grouped 1into blocks that correspond to the memory block
size. This minimizes the number of required main memory write

cycles.

The write buffer consists of:

Input latch selection logic

16-byte write buffer

Output buffer
Output multiplexer
o

with a longword. The latch
1
asicaill y, the wrwr i (WS bbuffer i s written
ections are then selected for writing to the output buffer by
WBUF WR ADD <01:00> bits from the translation buffer after being
enabled by WBUF WREN control signal [from the cache contrel logic
(MD number MCA)].

VIIT

2-24

Longwords

bus

ADD

the

BUS

output

<31:00>

<01:00>

buffer

bits

control

are

read

means

(multiplexed)

the

MD BUS

signals.

onto

the

and

BUF

check

NOTE

During

the

being

the
a

that

the

multiplexed

write
new

time
buffer

longword

approximately

can
of

again

data,

200-ns

2.2.1.2

Cache

consists

written

MCA

the

current

output

with

<15:04>

bits

cache

Cache

Match

Detects

°®

Provides

cache

MCA

for

consists

Cache

Refill match

Write

for

<3:0>

TAG

match

the

NMI

tag

between

MCA

used

several

1in

the

registers.

cache.
The

RAM

catch match

part

MCA:

part

the

buffer

PIBA address

and

address

of:

match

buffer

CTAG

match.

providing

"hits"

write

accepting

reference

Plus

The

cache

°®

Basically,

storage

MCA

cache

RAM,

thus

bits
and
addressed by means of PA
translation buffer). The CTAG VALID
<03:00>
octaword within a cache block is
valid.

cache

delay

match

The

<29:16>

the

which

)

the

TAG

(from

indicates

2.2.1.3

The

Tag

requested

buffer

the MD bus,

delay

availability of data.

data

output

onto

match

DATA
If

condition

interface

<28:16>

they

TAG match

logic

and

do match,

condition
does

not

(Figure

<29:16>

they

are

produce

exist,

CACHE

inputs

gated

are

with

VALID

signal.

CACHE

HIT

MISS

signal

2-11).

compared

CTAG
is

sent

a
to

NOTE

The

FORCE

the

cache

the

Additionally,
PABH

and

several
states

fetch

CACHE MISS

there

PABL

MCAs.

primary
in

read

output.

are

partial

The

major

"hit"

order

data,

CACHE MISS input signal from
control MCA can also produce

signals
cause

mark

data

VIII

"delay-write

outputs

that

are

stall,

"valid"

2-25

the

hit"

terms

cache

match

from

the

MCA

are

combined

with

other

start

NMI

sequence

for

the

IBox

and

CBox

EBox.

The

cache

match

also

<checks

cache

write

read
cache

that

block,
RAMs

delay

but

the

write

Both

write

address,

the

PA3

for

forwarding

and

delay

cache

also

instead

The

of
the

cache

MATCH

delay

cache

write

buffer

write

the

requested
of

the

data

means

valid

the

cache

from

amn b1 A
returned

that

the
on

information

can

valid
which

within

longword

with

buffer

the

N
to

WA
the

longword

cache block, but some
will be fetched, is in

delay
<cache
same address

write

longer

received

the

PIBA

all

delay
match

PIBA

by the cache
latch and the

the

MCA

write

hit

cache

tag

DATA<K29>=[1},

write

buffer

the delay-write
<cleared
(since

the

MCA, it is latched
cache write latch,

hit

Logic

and

the

PA3

(or

new

PIBA latch loaded. Once the PIBA
cycles match with the PIBA latch

(selected
by
the
match
data
the received PA3 corresponds to
loaded.

compares

address)

RAMs.

since

latch

logic

physical

and

hits
be

match
delay

represented

the
cache

hit,

a refill
bit must

immediately

cache

the

buffer

write buffer, if
block. Thus, the

stale).

the
received
PA3
Similarly, whenever

<29:16>

output

and

updated

before

cache

wused

loaded,

multiplexer).

bits

match,

buffer

bytes

buffer
and
the
information from the

<29:16>

write,

tag

write

is
NOT
within
a
that
cache block,

cache

being

hit signal. When
delay-write hit valid

When

latch

the

checking

buffer,.

contain

data

must

buffer

distinction between
hit
1is
the
cache
the

delay

longword

and

Hitting

the

valid,

the

Hitting

one

i
write

being
requested
information
from

addition

the

"stale®TM

cache

requester.

"hits"

buffer.

means

data

MCA,

for

This

I/0

the

match

the

field

current

comparison

address

space

arrays,

one

(that

reference

always

is,

miss

referenced

to
if

this

way.

The

hit

data

logic

with

the
happens

contains

two

match

cache

tag

DATA

the

delay-write
relatively
determines

speed

cache

data,

compared

Since
OK

with

there
forced

the

address.
early

ultimately

the

cache

match

tag

and

PA3

one

The

while

time

cache

output

signal

for

parity

compare

delay-write

the

bits

parity
during

compare

the

parity

the match data
is no TB lookup

true,

and

VIII 2-26

forced

OK.

data

compare

data

from

(available and
PIBA cycles or

match

signals.

parity

received

the
match

address

tag

hit

the

compare
In

check

the

order
of

the

RAMs

are

checked early).
invalidates, TB

2.2.1.4

cache

general

control

bits

CMCF

cache

data

stall

and

The

cache
cache

<6:3>
path
trap

the

Control
and

and

The

operation.

<2:0> into
translation buffer
data to the IBox.

MCA

effected

performs
on

cache

priority

Refill/invalidate

(function

invalidate
happen
°

cache
same

CPU

request.

Requested

Noop.

The

default

operation.
occur.

the

When

The

microcode
state

Microcode

request

PIBA

cycle,

no operation
PIBA cycle missed in
set,

which

occurring

until

refill

the

PIBA

or quiescent
Additionally,

for
of

controlling
the

other

NMI

the

out

the

cache

only

and

there

the

NMI

cache,

further

when

cycles

arbitrating

PIBA,

and

does

(that

is,

quiescent

requests).

the

not

could
the

activity.
quiescent

occurs.

state

read

1is

cycles

PIBA

change

control

microcode

uses

quiescent

or to
cannot

etc.

further

no
then

The

control

data

write,

the

2-27

miss

level.

descending

two

participates

VIIT

MPXT

invalidate

cycles

the microcode makes

in
are

NMI

and

the

sends

Arbitration

the

read

for

also

field

activities

read,

I-stream

the

from

prevents

type

the

true,

1is

CBox.

the

complete

request

this

has

Refill

sequence.

signals

NMI

cycle

return

block.

MCA)

The

Requested

either

command

latch.

arbitration.

the

time.

return.

(microsequencer

MCA provides

cache

control

basis.

each

cycle.

MCA)
the

decodes

CMSIZE

the highest priority level and
following
1is
the
priority
for
order:
®

cache control

the

status

control
is

MCA

CBox

from

Neither

for

the

mechanism

affect

operation

can

set

when

Which function is granted use of the cache data path defines what
(for example, if refill occurs then the
is performing
CBox
the
CBox is said to be performing a refill cycle).
.

NOTE

If
the NMI
writes
out
quiescent,
quiescent

interface is busy processing
to
the NMI and the PIBA is
the
CBox
1is
then
1in
a

state.

-- The MD number MCA receives the number
MCA
2.2.1.5 MD Number
CACHE CMD MDNUM bits <3:00>) of the memory data (MD) register
(as
and sends it as CACHE
to,
written
be
to
1is
data
cache
that
the EBox. When the translation buffer TB
to
<03:00>
DESTination
match MCA generates a MEM TRAP signal, the number of the register
should have received the cache data) content is sent to the
(that
(microsequencer MCA) as TRAP MD <02:00>, and is
control
out
NMI
used when the required read miss data is received from memory.

VIII

2-28

2.3

CBOX SUBSYSTEMS

2.3.1
The

NMI Interface

NMI

which

the

DESCRIPTION

1interface

the

NMI

CPU

provides

communicates

interface uses the
buffer
(TB)

translation

transaction

become

interface
data
cache

write

arrives
and

the

Figure

the

cache

CPU

data

process

path

and

the

NMI.

When

tag

memory

function

cache

read

The

memory.

the

NMI

interface
the

with

write,

without

the

new
NMI

making

When

cache

while
the

illustrates,

Address/data

the

NMI

control
store.

slices

NMI

out

NMI

in control
arbitration/acknowledgment
hardware registers

NMI
NMI

control

VIII

2-29

logic

NMI

of
It

the
also

address.

interface

then

the

read-miss

data

tag

the

takes

cache

the

and

requests,

transaction.

1into

valids

CPU

transfers

wait

for

to memory.
2-11

with

misses,

address received from the
an
NMI
command/address

memory

control

read-missed
to
build

data

executes

data

additional

from memory,

1loads
the

completion
As

sends

processes

validates
When

and

available

a
on

consists

of:

the

write

CBOX

MD BUS
TO/FROM

<31:00>

ADDRESS/DATA
SLICES

(FIG.2-10)

—

DATA

REG WRITE

(FIG.2-12)

REGISTERS
REG

READ DATA

_ LD WRITE

BUF

LD WRITE/-

PIBA Q1,Q1

CONTROL

NMI SOURCE

SEL<1.0>

pe-¢ 11in

(FIG.2-13)

NMI CS DATA OUT<22:0>

CONTROL

NMI

FROM

CACHE

FUNCTION SEL<2:0>

NMI SOURCE SEL<1:0>

SREETADE/)STSST

CACHE NMI CMD<1:0>

CONTROL

WD Bus

WR EN

INNMl

NMI

ARB/ACK

B T0 et |
|NMIEN

(F1G.2-16) | NMIi_FAULT REG<4:0>

CACHE DATA
(PATC};I 2-10)

NMI

(FIG.2-15)

CPU HOLD

NMI FAULT INT

CACHE Efig—fig—> CONTROL

MATCH
(FIG.2-12)

»|

DATA

(FIG.2-10)

.
NMI CONFIRM<1.0>

EXPECT READ/PIBA DATA

TIMEOUT STATUS<1.0>

NMI FAULT

NM!I EN

'CBOX ADP MODULE
CLOCK
MCA
8/10

NMI

FUNCTION<4:0>

NMI

PA<29>

NMI

MASK<3:0>

Y
SCLD-312

Figure

2-11

MNI

Interface - Block

Diagram

2,3.1.1

NMI

Address/Data

Slices

There

are

eight

NMI

address/data slice MCAs; six are located on the address data path
(ADP) module, and the other two are located on the cache control
sequence (CCS) module. Their function is to send:
®

Read-miss/write addresses and write data to memory

Read-miss

data

(that

received

from memory) to the

cache

)

Read-miss addresses to the translation buffer

Figure 2-12 is a simplified diagram of the NMI address/data slice
MCAs. As Figure 2-12 illustrates, the MCAs basically consist of:
®

A physical address

(PA)

An NMI address/data bus

An MD-bus

VIIT

file

2-31

CBOX ADP,

CCS MODULES
NMI ADR/DATA SLICES 1.2

MCAS
MUX &

2-BIT

ADDR QUELE
& CONTROL
(PA

IIIA
¢e—¢

<29°00>

TRANS-

LATCH

LATION

READ Q

WRITE

HIT

PIBA

INVAL

—
¥

C2 READ ADR<2:0>

REFILL/
INVALIDATE
MUX & DRIVER

PIBA

PA3

HIT

FILE)

1]
»

WRITE INVAL

—

Cz PiBA ADR

REF/INV<28:02>

TRANSLATION
BUFFER
B!

2 WRITE ADR

2-BIT
COMPARE
& DRIVER

|
i

BUFFER
(FIG.2-3)

B BYPASS

(F1G.2-1)

WRITE

WA Q1
HIT REFILL

Q1 WRITE_ADDR
LD PIBA

LD PIBA

PIBA

ANYWAY

WRITE Q1

VALID

WRITE

ADD ERR REG SEL

READ REG.

DATA<3:0>

ACV

DATA<2.0>

l’"ng'}E. -

BUFFER

LD WA Q

¥ c30x

LDPC UPPER ]

ERR
ADDRESS

LD WRITE Q1

Rec

WRT CUR
MOD<1:0>

—

DATA

FROM

——PA/DATA

—]

CBOX

xmiT

BUFFER (ZR08A
Trom

NMI

—

NMisteERs

(F1G.2-18)

80s_

TOFROM
CACHE
oA

<3100

(FI1G.2-10)

READ PEG SEL<3.0>

CEFILL OATA

«—REFILL DATA —}——

<31:00>

ADDRIDATA

» TO/FROM
MEMORY

NMLEN|

SH'2

REGISTERS
(FIG 2-18)

NMI SRC SEL<1:0>

4——WRITE DATA FOR MEMORY —

8CLD-313

Figure

2-12

NMI Address/Data Slices MCA - Simplified
Block

Diagram

File

The

fill

consists

Read

Q1,

PIBA

Q1,

Write

Q1,

three,

two-deep

queues:

Briefly,
Memory

holds

reads

read

read-miss

address

cache

PIBA

and

address

CPU

The

file

start

data

hold

memory

queues

The

from

the

addresses

PIBA

operation

and

are

sent

with

the

part

write

stalls

read

memory

data

transaction,

cycle

For

the

during

needs

(taken

PIBA

for

write

from

reference
different

address

file

data

MD BUS

queues

For

and

the

used

1is

placed

last

time

unless

reads,

queue. Write
requests; the

taken

the

when

the

retry

the

NMI

address port with the
to
load
the
refill

sequencer.

IBox.

cache

write

to a full queue.
times. First, to

recognizes that a read return
is
taking place, it loads the

refill/invalidate
refill
address

the

command.

this

necessary.

sequencer
sequence

the

slices

NOTE

write,

address

the

read-miss

transaction.

to do a
conceptually two

same

the

queue

When

The (TB then

and

queue.

destined

1loads

attempts

wires

cache

miss

wused

load

buffer)

the

address/data

miss

write

appropriate

read

EBox.

from memory, the

for

NMI

address

1is

The

the

is sent to the TB.

vector

the

queue.

for

store.

read

(miss)

destined

received

)

1is

references

read

in the read gueue

transferred

)

the

addresses

data

produces
the

1load

miss

2-33

out

NMI

the

address

When a cache read miss occurs, and if the PA file read queue Q2 is
empty, the miss address is transferred from read queue Ql to Q2.
The NMI out control (microsequencer MCA) then uses the address in

read queue Q2 for the read transaction. If a second miss occurs,
the address of the miss remains in input gqueue Q1 until the data
the first read has been received from memory.

from

The two-deep read queue enables the CPU to continue processing
while a miss is outstanding. If a second miss occurs while the
a bit in the stall logic is set that
1is still out,
first miss
indicates "stall if read." When there are two read misses
outstanding, the CPU VA stalls on read. When the data comes back
from memory, the miss address in read Q2 1is placed in the
refill/invalidate multiplexer and driver logic and sent to the
translation buffer as REFILL/INVAL <28:02>.

PIBA gueue functions similarly to the read queue, except that

The

the high-order bits are loaded when there is a:
Branch
PC change,
Page cross

o
®
o

or
PC

initially loaded, the upper bits go to
is
PIBA queue
is another PC change and no miss has
there
If
Q2.
queue
output
the high-order bits are again transferred to Q2. The
occurred,
lower bits, PIBA<8:2> are loaded in PIBA Q2 in the cycle that the
the

When

occurred

miss

there

data,
PIBA

the

in.

1is a branch while PIBA Q2 is full, and waiting for read

new

PIBA high-order bits (PIBA <29:09>) are loaded in

OQl.

NOTE

ahead of

When
of

instruction execution.

the data for the address in PIBA 02 is returned, the content

PIBA Q1

is moved

PIBA Q2.

VIIT

2-34

The

<cache

write

buffer

(Figure

2-10)

2-octawords

deep,

and

can

support
two
independent
transactions. Therefore, the related PA
file
write queue in the NMI address/data slice MCAs (Figure 2-12)
is
two
addresses (queues) deep. The first write of a sequence to
load
the
cache write buffer will load the input side (Q1) of the
gueue. When either:
®

The

explicit

The

write

The

sequence

cache

cache
-

the

NMI

out

validate memory

crosses

octaword

buffer

1in

write

NMI

bit

write

address

control
When

write

output

output
-

microcode

write

sequence

2-13).

sets

boundary:

2-10)

copied

the

queue

copied

the

NMI

out

Q2.

(Figure

control

set,

buffer.

the

queue

(Figure

requested

the

from

command

the

address

cycle

of
the
NMI write sequence, it examines the write mask buffer for
the
output
write buffer and modifies the lower bits of the write
address
to
fall on the natural data type boundary, (that is, the
write
buffer
can
be loaded with byte writes, but be an octaword
write to the memory).
The

address

1in

output

write

queue

multiplexed

the NMI source select multiplexer (by means
NMI
SRC
SEL
<01:00>
signal) and is then
ADD/DATA
<31:00>.
The
address
1is
held

means

of the NMI out control
sent to the NMI as NMI
1in
write
Q2 until an

acknowledgment

from
the last write to memory is received. If the
acknowledgment
1is
received, the register valid bit is cleared so
the
next write can be processed. However, if no acknowledgment is
received,
the
address
in the PA file is used for a memory-write
retry until it completes successfully, or a timeout occurs.

NMI
The

Address/Data
NMI

Bus

address/data

bus

1is

sourced

1in

the

NMI

address/data

slice's
MCAs. It is a multiplexed address and data bus and is the
major interconnect between the CPU and the memory and I/0O devices.
It
is
wused
by the NMI in control (function MCA) and as an input
port
to
the
cache,
and
1is
wused
by
the
NMI
out
control
(microsequencer MCA) output as a cache output port.

VIIT

2-35

in a given cycle, the NMI out control, has not requested and
If,
or, if the NMI in
obtained use of the NMI address/data bus,
1is not processing a refill sequence, receive logic in the
control
address/data slices processes the received memory information
NMI

both address and data. The refill/invalidate wires in the NMI
as
address/data slices are driven to load the refill register in the
The MD bus is then used to send the received
translation buffer.
data to the cache data path where it is loaded into a cache write
the NMI in control (function MCA) sufficient
allows
This
latch.
type of NMI transaction is currently being
what
determine
to
time
a refill or an invalidate transaction, the
is
it
If
processed.
data will be at the correct place
in control

During
driven
MD bus

(cache write latch) when the NMI

it.

needs

a CPU-initiated transaction, the NMI address/data bus 1is
with addresses from the PA file and data received from the

(from the cache).

Bus

The MD bus is a bidirectional data path that provides an interface
CPU and the NMI. The NMI out control uses it to move
the
between
the cache data path to the NMI address/data bus
from
write data
to the cache. The NMI out control
from memory
refill data
and
for register reads and writes.
bus
MD
the
(microsequencer) uses
MD bus arbitration is performed in the arbitration/acknowledgment
2-16). When the NMI in control is not requesting
(Figure
control
the MD bus is enabled for the NMI in control refill
the MD bus,
control is determining if the received
in
NMI
the
While
path.
read return data,; the data is loaded into the MD bus
1is
functicon
receive

latch.

2.3.1.2

NMI

Out

Control

The

NMI

out

control:

Controls the NMI address/data sliice MCAs PA file gueues

Controls

Figure

the

Write

Output

cache:

buffer

Sends NMI transactions to memory and I/O devices

2-13

illustrates

1is a simplified block diagram of NMI out control.
that

consists

address

chip

A next

)

A microsequencer

NMI

control

MCA

store

of:

RAM WRT DATA<7:0>

CONTROL

TEST

STORE

LOAD ADDR<7:0>

WRT SEG 1D

SILO TEST DATA<7:0>

SET

NM!I

CUSTORE ADD REG

SOURCE SEL<1:0>

CUSTORE WR STROBE

NMI_FUNCTION SEL<2:0>
NMI

NEXT
ADDR

CMD<2:0>

CACHE NMI

UADD<7:5>

DATA OUT<27:0>

CMD<1:0>

ARB OK

NEXT ADD<4:0>

REC CONFIRMATION<1:0>

Le-C II1IA

UADD
<7:0>

NMI

INTERLOCK WR
MD BUS BUSY

VIR

UADDR<4:05

CMD<1:0>

UADDRESS<4:0>

ERROR SELECT<1:0>

TIMEQOUT STATUS<1:0>
READ/WR

CYCLE

CURRENT PA<29>
NEW INSTR
BRANCH

GROUP SEL<2:0>

READ Q

PIBA

Q1/Q2

CACHE MISS TD NMi
_ WRITE

BUFFER

MISS

READ/WRITE PA<29>

/
D WRIT
ITE Q2 A/B

LD OUT BUF B TO SLICE 1

NMI

»|

(FIG.2-12)

CURRENT PA<29>
DISABLE

LD WR BUF A/B

TO SLICE

0/1

CACHE

_ ( (FIG.2-10)
»

NMi

SCLD-314

Figure

2-13

NMI

Out

Control

Simplified

Block

Diagram

is a microcoded sequencer that handles
The NMI microsequencer
command traffic to the NMI. It contains logic that holds the state
of the NMI address/data slice MCAs PA file and maintains the order
CPU memory requests. It is in control of all commands from the CPU
that are destined to the NMI, and performs some error handling and
CBox register reads and writes.

the RNMI
directly control
control store
the
outputs of
The
address/data slices, some part of the cache, and provide the next
address and branch selects to the sequencer itself.

The microsequencer sends read and write commands to the memory and
for the CPU. These commands are made up of several
I1/0 devices
steps:

priority

and

ordering logic produce the address of

The

The sequencer fetches the address of the command from the

the next pending

to
it
writes
PA file,
For
timers.
appropriate
the

instruction.

NMI

and starts the
NMI bus,
the
writes, write data is moved to

bus.

checks the received confirmation lines to
sequencer
The
For a write, the
the data.
got
receiver
the
if
see
1is the same in relation to pending writes, but
situation

can

second pending read (from the PIBA queue, for example)
be

done

while

the

sequencer

waits

for the read

confirmation.

When the confirmation of the transaction is received from
the seguencer sets or clears the appropriate
the NMI,
For writes, this means clearing the valid bit in
state.
state and moving the Ql address to Q2.
the write queue
For reads, this means getting the appropriate EXPECT READ
DATA bit

the

function MCA.

The microsequencer MCA contains logic that monitors the loading of
write, and PIBA queues in the NMI address/data slices.
the read,
logic that keeps PA file reads and writes in
includes
also
It
a 2-bit number as they are received by the
them
giving
by
order,
number is incremented whenever a read that
The
MCA.
cer
microsequen
write. This ensures that there can be no
a
by
followed
1is
missed
1 in the numbers of the commands at the
of
difference
a
than
more

front of the queues at any one time. Thus, at a given time, if a
read and a write have the same number, the write goes first.

Within
the

the microsequencer

numbers

their

wvalid

blocks

with

bits.

1logic

checks

1if

the

number;

the

other

the

equal

PIBA

any

then

the

read

number
if

number.
valid

order

CPU

one

less
write

the

select

three

valid,
or

equal

PIBA

read

then

PIBA

read.

the

are

uses
One

at
and

two

block

the

CPU

read

than

equal

and

less

than

command

lowest

number

the

with

and

less

looks

queues

first.

valid

write

command

logic
file

then

goes

number

write

one

than

the

read

the

which

the

read,

command

than

command,

otherwise,
both

each

determine

checks

other
If

Dispatch

If
to

write

processed,

processed.

MCA,

associated

lowest

(and

valid),

logic

1in
the
microsequencer
MCA
generates
dispatch
from
the
control store based on command types in
write,
and
PIBA
queue
state
logic. It prioritizes

microaddresses
the

read,

pending

requests

initiating
There

are

the
two

NMI

Pending

third

path

for

serviced

The

cycle

hit,

and

the

can

the

control

read

file

cycle
file
PA

finish

queue

file

sequence

state

queue

logic

state

saved if nothing else
command must be sent to

the

store,

pending.

first
PA

the

highest

priority

for

the

group

NMI

in
response
location
1in
the

to
PA

the

NMI

rather

than

priority

the

CPU

and

memory
in

does

data

again

this

the

load

request

microsequencer
to

priority

microsequencer

through
The

1If

block,

the

Because

and

highest

address

finish.

delivers

with

around

CPU.

has

The

lowest

path

can

microsequencer

processing
read

involved

the

group

appropriate
error

that

must be
the NMI

bus.

first
NMI

address

sequence.

delay-write

sequencer,

microsequencer.
The

the

generating

cycle,

the

address/date

bypass

from

only

requests

for

timeouts,

commands

loaded

sends

cycle

groups

functions

and

first

two

passes
after

group

the

1is

timed-out
the

read

misses

the
the

address

sequencer

the

read

back

into

first

one

comes

delay-write

masked

read/write

ALU

and

VIIT

2-39

registers

the

NMI

timeouts.

timeout
clears the
file to allow further

that

the

into

the
is

same

cache

the

cache

back.

hit.

the

handles

The

cache

IBox.

The
NMI

and

for the
If any of the PA file queue entries are waitinofg the
above
none
1if
ssed
microsequencer MCA, they are proce
in
kept
be
to
have
s
write
and
requests are pending. Since reads
y
simpl
ems)
probl
data
stale
of
order (to avoid various types
each
d,
Instea
work.
not
prioritizing reads and writes will
r as it comes from the
location in the PA file is given a numbenumber
s and selects the
these
CPU. The next command logic looks at
Dby the NMI
order
in
ssed
next command. Besides being proce
Thus, the
order.
in
ed
microsequencer, the commands are also finish
received
it
that
m
confir
receiver (memory or an I/0 device) must
data.
write
the
of
all
the read command or the write command and
the
and
n
writte
is
flow
This 1is handled by the way the microcode
takes
write
rd
longwo
branch on the received confirmation. Hence, a
four lines of microcode.

Figure 2-14 illustrates the format of the control store microword.

2423

20 |19

16,15,

1.1

1211

RANGH

NEXT ADDRESS<7:0>

08[07

GROUP
SELECT
5 h

MoGlR
WR

REQ )F ACK

<1>

PARITY
Odd parity on the
28 microword bits
INTERLOCK

<3>

WRITE

for

BUS

<6:4>

detected.

1
0

SET EXPECT PIBA DATA
Used to set the EXPECT PIBA
DATA state bit in FUNC MCA
during PIBA READ cycles.

<10>

NMI
FUNGTION SELECT

R FDRCNEN"

R ELA

1
0

<12:11>

to generate

WRITE
WRITE
PIBA
WRITE

FUNCTION

UNNLOCK

<13>

Select DIAGNOSTIC ID for
transmission on the NMI.
No Operation
Select DIAGNOSTIC

<8>

cVCFIKITE QUEUE
L

when CONFIRMATION is received

from
<18>

<19>

the

NMI

devi1

SEND HOLD
Used to assert the CPU
line on the NMI during
transactions.

HOLD
write

NMI| BUS REQUEST
Used to assert NMI BUS REQUEST
when arbitrating for use of
the NMI bus.

<27:20>

NEXT ADDRESS

Because the NEXT MICROADDRESS
contlnuahon of NMI microcode

Write

for

sequences

SOURCE SELECT

CONTINUE SEQUENCE
Select between the DISPATCH
and the NEXT ADDRESS microaddress.

0
1

<16:14>

REQUEST MD BUS WRITE

Dispatch
Continue

sequence

BRANCH GROUP SELECT
Selects branch bits for replacement
of next microaddress <2 0>
Also performs
ERROR
CLEAR function
interface,
and ERROR ADDRESS REGISTER (EAFI) loading.

Requests the SLC moduies to
send WRITE DATA on the MD BUS.
1
0

PIBA

DATA

0 MD BUS
1 READ ADDRESS
2 WRITE ADDRESS
3 PIBA ADDRESS

DATA

SELECT CIAGNOSTIC

BAY.

Select the source of intormati
for transmission on the NMI ADDRESS
DATA Lines.
It
is also decoded and
used to start the timeout counter
and determine whether ID or MASK
should be sent on the
NMI.

READ INTERLOCK

<7>

1
0

NMI

$BLT | INLK
PRE

SELECT

No Operation
Request MD BUS read

No Operation
Request Register

<17> (L:JLEARI WRI'II'E QZHIF
o clear
€

bit

REQUEST REGISTER WRITE
Used during Cbox REGISTER WRITES
to enable the actual writing
of the registers.

SET EXPECT READ DATA

NODIAGNOSTIC

Read this

cache, set the REFILL/INVAL select
lines to select the READ QUEUE
and enable the data onto the MD BUS.

READ LOCK

UNLOCK is

Used to set the EXPECT READ
DATA state bit in FUNC MCA
during CPU READ cycles.

NO NHEWN—O

v—C I1IA

<2>

REQUEST MD BUS READ
During
Cbox Register

REQ
NMI
SET
PTY
& P50
MNcrion sear
ETY

is sgd to requgesl the use of the

ARB

Re-arbitration

after

<9>

WR
<0>

04 |03

No Operation
Request data

B%’}Incyo#grfi';(z)
0

| NEXT

UADDRS<2>

NEXT UADDRS<2>

2 | NEXT UADDRS<2>

3 | NEXT UADDRS<2>
4

| NEXT

BRANCH ADDR«1

BRANCH ADDR<0

components< z

RCVD CONF<0>
MEMORY BUSY

INTR

MD BUS BUSY

TIMEOUT

Write

TIMEOUT

ARB OK

RCVD CONF<1>
0

REBOOT

UADDRS<0> { No

UADDRS<2-

6 | Write Unlock

components< g

RCVD CONF<1>

5 | NEXT UADDRS<2>

7 | NEXT UADDRS<2>

UADDRS<1>

Unlock

RCVD CONF<0>
)

ERROR CLEAR

branch

Select Error Clr &
set

up LD EAR.

WRITE

PIBA

READ

LD EAR
-

--—mm-

-————-

22X
|
L.

WRITE

PIBA

READ

LOAD

SCLD-315

Figure

2-14

Control

Store

Microword

Format

Diagram

|
=
e

]

ot
o

IRWN

~N
R

g*1°¢e’¢

3 0

MODULE

OF 14)

Sile
5

NMI ID MASK<3:0>

NEW INSTR

2_ :*
O

GLOBAL UTRAP

REC 1D

INVAL SEL A/B
.

SIl.O DATA<7:3> ,

EUFC
UN

<4:0>

RET CMD <1:0>

BUF RETURN TYPE<1:0>

MD NMI RD EN

DIAG FUNC<4:0>

X
»

NMI In Control - Block Diagram

=
rr

—
\Q
p

L
o

SCLD-316

Figure 2-15

.TO

» VD NO.

9®°UL

-/SIZE

NM| _PA<29>
MCA/LOC MCA PA SEL<1:0>
CNTRL
M (REFILL
SEQUENCER) | MD NMI RD EN
NMI FUNCTION<4:0>
M (3 OF 14)
FUNGTION

TWN

WRITE MASK

31
TOIJUOD

REG WRITE
DATA<7:4>

<1:0>

SOURCE SEL

MASK/IC
CNTRL

o
O

S3ISTSUOD
STOA3UOD

NMI

WHICH CPU

e JO
ejep

PA3<«3.:2>

TOA3Uu0)

CCS

Mask/ID MCA

The

mask/ID
MCA stores the valid (or state) queues for the cache
write
buffers
indicating
which
bytes are valid. The outputs of
this chip include the mask/ID field for the NMI, state information
for
the
microsequencer,
and
information
needed
for
write
transactions
for
the function MCA. Within the mask/ID MCA, valid
queue
encode logic looks at VA<K03:00>, the CPU WRITE command, and
the
size
of
the
reference
to
determine
what bytes are being
written
in the NMI address/data slices PA file write
buffer, and
then
sets the
corresponding bit in valid queue 1. Conditions are
monitored
in this block to determine whether or not to move Queue
1
to
Queue
2
and
whether
or not to clear Queue 1. Within the
mask/ID
MCA, valid queue decode logic provides information needed
for
the
NMI
write
transaction.
From the data in valid Queue 2
logic, the following is determined:
°

The

size

The

the

starting

octaword,

NMI

write

transaction

address

(VA<3:2>)

for

quadword,

that write
and

any

(00

for

for an

longword

writes)

Whether

not

the

transaction

a masked

or unmasked

write

the

write

1is

contains

masked,

the

proper mask

for

each data

cycle

The

mask/ID MCA

Generates

that:

the NMI MASK/ID field during command cycles in

which
the CBox is
control lines from

)

logic

the commander using the CPU number and
the CBox microsequencer

Monitors
the
MASK/ID
field
at
times when the CBox is
transmitted
1ID was
the
that
ensure
to
transmitting
properly,
(otherwise,
a
multiple transmitter fault has
occurred)

Monitors
return

the MASK/ID field during NMI command cycles

data

the

for

CBox

The mask/ID MCA also calculates parity on the MASK/ID field of the
NMI control. This term is then combined with the parity calculated

MCA
function
the
by
acknowledgment/arbitration
control

on
MCA

the
in
field
function
the
NMI
the
on
parity
to complete the

field.

VIIT

2-43

Function MCA

The

from

function

MCA

the NMI bus.

1is

in control of data and invalidates received

It is completely synchronized with NMI traffic.

1is refill data for the cache, a
data
memory
received
the
When
to see if read data is expected for that ID, then
made
is
check
and automatically obtains use of the
requests
MCA
function
the
cache and writes the refill data into it.
Any
writes
to
memory
space cause the function MCA to perform a
function MCA (Figure 2-15) serves two
The
invalidate.
two-cycle
functions

the

It is the controller for received NMI traffic.

the

cache:

the

first

interface

case,

to the NMI FUNCTION

the

output

<4:0>

path

field.

for

the

NMI

microsequencer to drive the FUNCTION field to other devices on the
NMI. In the second case, it produces all the control to direct the
refill data, or invalidating the
1loading
in
MCA
control
cache
cache.

Function
Encode
-The
output
portion
of the function MCA is
controlled by the microsequencer MCA. One field is output from the
control

store

that

selects

the

function

to go to

the bus.

For

1lines are encoded with the mask bit and WRITE SIZE
these
writes,
<1:0>
1lines
from
the
mask/ID
MCA.
Reads are encoded from the

[I\.)

from the microsequencer

function

[

read

current

MCA.

Function

Read

associated
1.

State

read

commands.

EXPECT

READ

DATA

This

bit

1is

confirmation
returned.

MCA

checks

for

this

cycle.

set

the

READ

this

bit

data

MCA

clears

this

the

bit

this

state

READ

back,

the

data

during

bit

the

sent

sure

the

reference

clears

four

microsequencer

to make

writing

bits

the

1is

the

function

expected

data

into

when

command

the

last

cache.
data

has

timeout,

when

enters

The

return

the

NMI

timeout

routine.

bit

loaded

NMI

bus.

PA<K29>=0,

the

hit

VALIDATE
This

read

the

bit

cache
that

NMI

the

cache

the

same

that

CPU

the

size

The

Aa+a
WA

read
hex;

function

1 e

A LA

+~n

e Ty N

L.\J

expect

| 73

goes
if

the

PA<29<=1,

MCA

uses

vyatrnnrnaAd

)

this
I+

PURRNPIR
AV IF oy D AV
B

read

from

storing

does

cache

block),

in the
This

data.

read

stale
miss

half-block

the

data

(or

data

followed
an

the
by

invalidate

requires

from

read, but the
The
specific

the

data
data

read miss is sent to the CPU, but only a
is set by address checking logic in

bit

ADD/DATA

the

when

not the data returned by the
been
written
to
memory.

requested
longword.
the

long.

minch

ERA QW B WY P

fashion

the
If

the

LIS VY

read

DATA

keeps

1is
had

PA<K29>

the
is

hnaw

same

case.

occurs

LR A

RETURN

following
write

e W

with

size

Aotermine

e L/

cleared

NMI

receiver

before

This

the

read

has

SIZE

then

the

MCA

are:

1ID

microsequencer

service

function
They

from

When

function

The

with

MCAs

same

time

function

not

and

the

cleared

EXPECT

to validate

READ

the

DATA

function

BIT.

returned

block

MCA

causes

the

cache.
4.

READ

HIT

This

bit

keeps

reads

memory

executes

two

half-block

the

NMI

for

microsequencer

the

same

consecutive

(read

quad,

for

for
the
second
read
first
read.
Instead

is
of

microsequencer

the

directs

half

from doing
If

the

same

cache

instance),

the

correct

data

reads

contained
reading
read

back

in
to
to

the

two

block.

the return for
memory,
the
the

CPU

the
NMI

CPU.

This
bit is set by the address checking logic in the NMI
ADD/DATA
MCAs if the expect read data line is set. It is
cleared
by
the
NMI microsequencer when the read finish
sequence

1is

executed.

VIIT

2-45

Function

PIBA

associated
1.

State

with

The

function

MCA

has

read

data.

four state bits

PIBA commands.

EXPECT

PIBA

DATA

PIBA

SIZE

PIBA

PA<K29>,.

Same

for

read data,

except

that

VALIDATE
cache
-Same
check is done against the

OLD/NEW
-This
bit
is
unique to the PIBA state. If,
while
the PIBA miss is out, a PC change occurs, the PIBA
in
the
PIBA
address register is no longer the same one

that

caused

the miss.
into

This

the

IB.

the

This means
cache,

bit

1is

that while

does

set by a

The

Decode

input

the

the data

not want

to be

sent

PC change while the

EXPECT
READ
DATA bit is set and cleared by
MCA during the last data return cycle.

Function

that

being written

as
read data, except
PIBA Q2 address.

set

the

function

Logic

1logic

decodes

the

received

function,

examines

the

received
ID if READ RETURN and PA <29> if write, and decides what
to
do.
To
do
a
READ RETURN, the received ID has to be checked
against
the
EXPECTING
READ DATA bit. If, for that ID (one ID is
for
PIBA
READ,
one for CPU READ), it is not expecting data, the
UNEXPECTED READ FAULT line is raised. If it is expecting data, the
function MCA requests and wins the cache and does the refill.
For a

CPU

read,

In
to
<

function

MCA:

the first cycle, loads the refill/invalidate register
write
the
cache
with the data that has been loaded
—~

intdo

the

theée

~ o~

Ccacne

Ty,
A

write

l1atcii.

Also
1in
the first cycle, reads out the MD NUMber of the
reference
that caused the miss currently being refilled.
This
directs
the
first
word
to
the
requesting
MD
register.

)

Increments
the
refill
pointer
received
NMI
function
i1ndicates
not incremented on PAUSE.

When
EXPECT
during

the

refill

counter

READ RETURN DATA bit
the sequence.

has
if

for
every
READ RETURN

reached eight,
there

have

been

cycle
the
DATA CONT,

clears
no

the

errors

the

refill

1is

1in

response

PIBA

READ miss,

then

the

function
MCA
responds
Along
with
the
EXPECT

slightly
differently in one of two ways.
PIBA
READ DATA bit in the function MCA,

there

says

bit

that

whether

not

there

has

been

change,
while the read was out. If there was a PC change then the
data
1s
put
in
the
cache
just
as the read data was with the
exception
of
reading
out
an
MD
NUMber. If there was not a PC
change, then the function MCA puts out a signal that says step the
PIBA
with
the
refill.
So
1if the IB is not full, it will get a
longword
crosses
During

cycle

the
an

the

and

looks

the

will

NMI

either

operation,

first
up

cycle,
the

next
given

cycle,

NMI

notify

"commander"

arbitration

command
fault

field

cycle.

logic,

full

the

refill

function
the

refill/invalidate

pointed

hit.

MCA:

the

that

line

missed,

address.
the

then

this

cycle

requester.

Arbitration/Acknowledgment

acknowledgment

the

tag

another

Acknowledgment/Arbitration
The

becomes

invalidates

was

the

loads

cache

1lookup

boundary.

invalidate

cycle's

2.3.1.4

wuntil

wrapped

and

Also
the

used

MCA
field

used

the

data

status

determine

included
NMI

1is

the

parity

the

logic.

VIII

2-47

the

MCA

NMI

"responder"

transfer.

"commander"

the

timeout

The

NMI

the

logic,

the

Arbitration Logic

1lowest

the

has

CPUO0

NMI

and,

priority

dual-processor

arrangement, CPUl is just above it. This piece of logic determines
cycle. This is
arbitration
the
been granted
CPU has
the
if
determined by checking the NMI arbitration lines coming into the
to see if a device of higher priority is arbitrating for the
chip
If the CPU number is '0', it is the lowest device in
next cycle.
the scheme and it may assume that it has won the bus at this point
else wants the bus. However, CPUl must make sure that
one
no
if
has been asserted the cycle before it
1line
arbitration
own
its
other device of lower
no
that
ensures
This
bus.
the
desires
priority (CPUO) thinks it has the bus. In summary, CPUO may assume
when no one else is arbitrating. CPUl must
bus
the
won
has
it
be sure that its own arbitration line has
to
check
additionally
has not, to assert it and try again next
it
if
and
asserted,
been

Finally,
cycle.
is
transaction

hold if the
NMI
sends
1logic
arbitration
the
the
notifies
and
cycle,
one
than
longer
the bad memory busy response occurs.

microsequencer

Acknowledgment

Logic

The

NMI

arbitration/acknowledgment

transaction confirmation

codes:

control

(Figure

2-16)

has

AC
OK

BUSY

BUSY
NO

These

INTERLOCKED
RESPONSE

codes

are

transmitted

by the

receiver one cycle

after

the NMI microsequencer is a
When
date.
or
command
a
receives
and NO RESPONSE like
INTERLOCKED,
it treats BUSY, BUSY
commander,
command. When the
the
retrying
were busy responses and keeps
they
MCA is receiving read return data,

function

The

CPU

never busy

returned

VIIT

data.

2-48

it only sends ACK OK.

MODULE

14)

FAULT

DETECT

NMI

FAULT

INT

NMI

CPU

NMI

EN A/B

NMI

CPU BUS

NMI

SLOW CLOCK

h 4

CONFIRMATION<1:0>

NMI

HOLD

EN
ENABLE

I1IA

NMI

ov-¢

NMI
ARB

CONTROL
(10

14)

NMI

RIGHT/LEFT

NMI

MEMORY HOLD/ARB

NMI

1/0

NMI

MEMORY BUSY ARB

DIS

DEAD CYCLE

0/1

CPU

HOLD/ARB

NMi

ACK/ARB
CNTRL

HOLD/ARB

NMI

RT/LFT

CPU

NMI

MCL BUS

NMI

CACHE

I/0

ERR

BUS

REG<5:0>

CBOX ERR/MC TRAP
MEMORY BROKE

Y YvYYy

CCS

SCLD-317

Figure

2-16

NMI

Arbitration/Acknowledgment

Block

Diagram

Control

Simplified

Timeout

Logic

Basically,

this block is a counter that is given a slow clock from
the
NMI
and monitors the three types of CBox transactions (read,
write,
and
PIBA
read) for timeouts. For the read and PIBA read,
there are two periods to the transaction that are timed. The first
is
from the time the NMI microsequencer starts the read until the
responder
confirms
the command with ACK
OK. This means the READ
command

can

bus

the

timeout

either

responder

was

because

busy

there

was

not

access

there.

the

NMI

When positive

confirmation
1is
received, the timer is restarted to wait for the
data. In the first cycle of read return data, the timer associated
with that data is set back to the idle state. For writes, only the
first case of timeout is necessary. In the event of a timeout, the
NMI microsequencer sets the timer to the idle state and clears the
address
queue
of
the
timed-out
transaction. Timeout locks the
fault
register
and
NMI silo for examination by system software.
These
timeouts
occur
when cycles of the slow clock pass without
the
transaction
being
completed.
For
diagnostic purposes, the
timers
<can
be
switched
from running off the slow clock (system
clock
divided
by
approximately one thousand) to running off the
normal system clock for very fast timeouts.
Figure

2-17

illustrates

the

timeout

flow.

—

IDLE

READ| START

TO PIBA

C(C:XLJENATER

NO ACCIESS

TO BUS STATE

ARB

CLR
PIBA

WAIT

FOR_

ARB OK

}1!MO

ACCESS

TO BUS

16-¢ IIIA

CLfiv
ARB OK

WAIT
FOR
CONT

ACK| OK

General

TIMO,

START PIBA OR

WRITE

can

PIBA

wrte

STATE

WAIT

FOR

RETURN

FINISHED

DATA

READ,

while

CLR

PIBA

Timeout

result

PIBA

conditions

that

broken

for

Counter:

cleared

loop in

writing

ARB

on the

cycle.

the

first

The

WAIT

timeout.

macrosequencer

ARB OK

ACCESS TO BUS

attempt

FOR ARB OK

Cache microcode,
timeout
code.

which

These

are

checks

this

point

The

WAIT

should

FOR CONT state

PIEA

timed

TIMO

ACK OK is

PIBA

this

RETURN
FINISHED

or WRITE operation, or it there is a PIBA return
outstanding, the PIBA RETURN can come back and clear the
PIBA state.
|f there is no PIBA or WRITE to be done,
the counter will count until timeout occurs or the read

WAL

second

CLEAR

by the

cycle

Cache microcode,

after

set,

the

waiting

command/address

for

EXPECT READ DATA bit

the

sent

the

NMI.

be set.
This will result in the WAIT FOR RETURN DATAwillstate.

return

CLR

WRITE,

a tight

only

branch

TIM
READ

state

PIBA

READ

Notes

The Timeout counter is

OPERATION

PIBA

point,

cleared.
STATE

AND

CONTINUE TO WAIT FOR

READ RETURN

timeout

the

mlcrosequencer

finished.

|If

there

counter

IDLE

state.

read

returns,

counter will

will

this

disabled,

time,

other

a PIBA read

can

begin

the

cycle

and

PIBA

read

state

return

progress,

outstandung

the

will

the

continue to count until the PIBA
or

times

out.

SCLD-318

Figure

2-17

Timeout

Flow

Diagram

SILO DATA
| 27735

FUNCTION
3/14

NMI RIGHT CPU ARB
NMI

LEFT

Mask/ID

BUFFER
130P

CPU ARB

MCA
5/14

SILO

DATA

an
| 25

10/14

_NMI_TO

“1

NMI_TO 0 ARB
NMi

ARB

MEMORY BUSY ARB

SILO

DATA<18:12>

DIAG
SILO

¢S—¢ IIIA

;

eronms

JLAFTER

MCA
6/14

(SILO REC CONF<10>
=2

FAULT)

SILO

MARKER

[¢
DATA<19>

9/14

READ

DATA

—

SILO

TEST

4/14

sILo

gfi\n

FUNC

ACK OK

_ FORCE CTL PTY ERROR|

178p | <07:00>

DATA<7:0>

GONTROL

_,FORCE
<

V1A

ADDR/

SLICES

(FIG.2-12)

SILO

<19:00>

DIAGNOSTIC

/D REG

NMI ARB

CACHE ERROR REG<5:0>

10/14

NMI

TO NMI

<4:0>

FROM

i,
1A /
<10

NMI_FAULT

BUFFER

CBOX ADP MODULE

11/14

(VIA
ADDR/DATA

SLICES)

(FIG.2-12)

REG<4:0>

»]

CACHE

<3:0>

4/10

TAG

11/14

§8CiLD-319

Figure

2-18

CBox

NMI

Regilsters

Locatlion

Diagram

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6°'1°¢€°¢
Xodo
s93rI3ISNIIT
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IKN

CBOX CCS MODULE

Cache
The

cache.

control

the

Figure

2-19

Cache

only

controls

READ/WRITE

illustrates

and

the

overall

Table

2-3

the

operation

the

CBox.

describes

the

format

313029 2827262524232221201918 171615 1413121110 0908 07 06 05040302
01 00

o/0j0j0j0jO00j0]|0{O

ojojolojo|ololololo]lolo

0'0

NM! DRIVER ENABLE —T T
CACHE ON ——
|
MME ON
SCLD-320

Figure

Table

Bit

Name

<2>

NMI

2-19

2-3

Cache

Bit

Format

Descriptions

Description
DRIVER

ENABLE

When

NMI

DRIVER

prevents

being

the

set

turning

off

permits

some

performed

NMI

bus.

cleared,

ENABLE

the
the

This

ENABLE

NMI

signal

CBox,
NMI

effect

drivers.

diagnostic
without

READ/WRITE

bit

set

from

This

functions

disturbing

the

cleared

CPU

normal

CPU

INIT.
NOTE

This

<1>

must

operation

CACHE

When

operation

cleared,

misses.
reads

bus

this

all

bit

enabled.

cache
be

set,

When

references

Additionally,
will

for

occur.

all

reads

NMI

cache

will

D-stream

conserve

NMI

cycles.

This

READ/WRITE

INIT.

VIIT

2-53

bit

cleared

CPU

Table
Bit

Name

<0>

MME

2-3

Cache Register - Bit Descriptions

(Cont)

Description

management

memory

This

the

enables
hardware

virtual
the

enable

Dbit

memory management

translation

buffer.

The operation of this bit is generally
defined by VAX 8800 architecture. When
this
bit
1is
cleared,
the
virtual
address range of the system is 30 bits
rather
than
32
bits. The mapping of
addresses, with MME
physical
virtual
(o0},
=
PA<31:30>
is
cleared,
PA<29:00>

VA<K29:00>.

1is cleared, the translation
MME
When
buffer
does
not
perform
protection
checking or page cross checking.
This

read/write

INIT.

cach e

parity

error

c hecking

interface .
®

cleared

by CPU

Error Register

Cache
The

bit

Included

bus

holds
in
the

the error
CBox
=--

bits for the
other
than

various
the NMI

are:

parity

Physical address parity

(this generally means TB parity)

Memory
data
parity,
which
1is the parity of the MD bus
information received at the cache data path end

tag

parity

NMI

microsequencer

NMI

data parity

Data destined for an EBox MD register

BAD READ DATA that

Bad

PIRA

parity

error

data

for

on:

is
the

not

prefetch

current

VIII 2-54

PIBA

data

The

entire

unlocked

cache
by

error

CBox

locks

the

write

first

error,

address

and

(hexadecimal).
The

cache

Cache
2-4

error

Error

describes

the

Byte

format

cleared

the

CPU

Figure
Cache

INIT.

2-20

Error

illustrates
Register

and

Byte

Table
2.

313029 2827262524232221201918171615 1413 1211100908 07 0605 040302
01 00

o;j0/0)j0/0f0|j0 ,0(0|0|0O|O|O|O|O|O|O|O|0|O|0|O]|O|0O0]O

A‘Tl
VA PARITY

ERROR<2>

VA PARITY

ERROR«<i>

SPARE
TB

DATA PARITY

ERROR<2>

DATA PARITY

ERROR<1>

DATA

ERROR<0>

PARITY

SCLD-321

Figure

Table

2-20

2-4

Cache

Error

Byte

Bit

Name

Description

<05:04>

These

bits

there

was

PARITY

ERROR

<2:1>

bits

Bit

Format

Bit

Descriptions

are

set

parity

<31:16>

indicate

error

bits

that

the

<15:09>,

respectively.
<03>

Spare

<02:00>

Read

DATA

ERROR

PARITY

<2:0>

ZERO.

bits

are

error

the

(TB)

data.

These

following

VIIT

set

translation

The

bits

fields

DATA<29:23>

DATA<K22:16>

DATA<15:09>

2-55

parity
buffer

pertain

the

data:

the

Cache

2-5

Error Register - Byte
describes the format of

1 -- Figure 2-21 illustrates and Table
the Cache Error Register - Byte 1.

3130292827262524232221201918 171615 14131211100908 07 06 05040302 01 00
o/0ojojo0j0j0oi0cj0i0i0j0|0]|0

ocjojof|ofjo|0O|O|O|O|O]|O}O

A A A

T
CACHE TAG PARITY ERROR<i>

CACHE TAG PARITY ERROR<0>
MEM DATA PARITY ERROR<3>
MEM DATA PARITY ERROR<2>
MEM DATA PARITY ERROR«1>
MEM DATA PARITY ERROR<0>
SCLD-322

Figure

Table

2-21

2-5

Cache

Error

Byte

Bit

Name

Description

<05:04>

CACHE TAG PARITY
ERROR<1:0>

These

bits

parity

- Bit

are

error

set

Bit

Descriptions

when

detected

tag
data
<28:24>
respectively.
<03:00>

MEMORY

DATA

ERROR<3:0>

PARITY

These

bits

error

was

by
one
of

VIIT

Format

indicate
detected

there
on

the

cache

<K23:16>,

that

parity
bus

data

the cache data buffer. There is
parity error bit for each byte
data.

2-56

Cache
2-6

Error

describes

the

Byte

format

the

Figure
Cache

2-22

Error

illustrates
Register

and

Byte

313029 28 27262524 232221201918 171615
141
12 3
11 10 0908 07 06 0504 0302 01
|

000000000000000000000!0000’0
!

TB TAG

NMI

PARITY

ERROR

CS PARITY

ERROR

FITTT
—

‘

Table
0.

——

BAD READ DATA
BAD PIBA

NMI

DATA

DATA PARITY

ERROR
SCLD-323

Figure

Table

2-22

2-6

Bit

Name

<05>

Read

<04>

Cache

Error

Byte

Bit

Format

Descriptions

Description
as

TAG

ZERO

PARITY

ERROR

This

bit

parity

error

RAMs.

parity
tag,

set

when

detected

the

check
MBIT,

there

the

1logical

conditions

for

PROTection,

<03>

NMI

PARITY

ERROR

This

indicates

that

error

the

parity

<02>

BAD

READ

DATA

CBox

NMI

BAD

READ

return

control

received

<01>

BAD

PIBA

DATA

data

the

code

(which

that

was

memory

data

was

BAD

PIBA

the

that

was

data

was

VIITI

2-57

DATA

CPU

1is

the

NMI

set

BAD

DATA

the

miss

function

read

the

was

read

that

for

being

VALID

when

returned

indicates

was

I-stream.

BAD

DATA

(which

memory

the

prefetch

data

the

data.

uncorrectable)

not

received

bits

set

for

being

code

store

1is

there

indicates

was

return

tag

and

fields.

CPU

the

data

from

the

and

the

data.

when

the

PIBA

miss

NMI
that

returned

function
the

data

from

the

uncorrectable)

and

the

return

current

for

the

Table 2-6

Cache Error Register Byte 0 - Bit Descriptions (Cont)

Bit

Name

Description

<00>

NMI DATA PARITY

NMI DATA PARITY ERROR is set when

ERROR

1is

a parity error on return

or data that was destined

there

data
for

that

the

was

current

destined

for an MD

PIBA.

Fault/Status Register

NMI

Fault/Status Register - Byte 1 —-- Figure 2-23 illustrates and
NMI
2-7 describes the format of the NMI Fault/Status Register Table
Byte

31302928 27262524232221201918 1716151413 1211100908 07 06 0504030201 00

ololojojlolo|olojojo|0|Of0|O|OjOfO]O|0|0O|0O|0]|0|0|0|0]|O
I

A A A

NMI FAULT RECEIVED
BUF ID

<1>

BUF ID

<0>

ADDRESS/DATA PARITY ERR

CONTROL PARITY ERROR
SCLD-324

Figure 2-23

Table 2-7

NMI Fault/Status Register Byte 1 - Bit Format

NMI Fault/Status Register Byte 1 - Bit Descriptions

Bit

Name

Description

<04>

NMI FAULT RECEIVED

This bit shows the state of the NMI
FAULT wire at
If
read.
is

the time the register
this bit is not set,

fault/status
NMI
of
<1:0>
bits
1 and bits <4:3> of
byte
register

Dbyte
register
fault/status
NM I
no
have
detects)
CPU
the
(that
meaning.

VIII 2-58

Table

2-7

NMI

Fault/Status

Byte

Bit

1is

Descriptions

(Cont)
Bit

Name

<03:02>

BUF

Description

BUF

<1:0>

used

<K1:0>

determine

transaction

condition.

encoded
which

buffers

The

had

encoding

field

of
a

the

timeout

1is

shown

<01:00>

PARITY

ERROR

FAULT

BUF

<1>

<K0>

=00

— OO

below:

Buffer
No

Code

Timeout

Write
Read

Timeout
Timeout

PIBA Timeout

ADDRESS /DATA

PARITY

ERROR

and

ERROR

indicate

that

CONTROL

PARITY

the

detected

CBox

parity

error

the
ADDRESS/DATA or CONTROL parity
lines
on
the
NMI.
These are NMI
FAULT conditions, and are held from
the
time
the
fault
was detected
until the NMI FAULT line is cleared
(by a transaction to a memory CSR).
If
the
NMI
FAULT received bit is
not
set,
these
bits
have
no
meaning.
The
information
that is
latched
in
these bits pertains to
the
cycle
on the NMI in which the
fault
was
detected, not the cycle
in
which
the
FAULT
1line
was
asserted.

VIIT 2-59

NMI Fault/Status Register - Byte 0 -- Figure 2-24 illustrates and
2-8 describes the format of the NMI Fault/Status Register Table
Byte

313029 2827262524232221201918 171615 1413 1211100908 07 06 05040302 0100

olololololololo]lolo|o|lolo|o|ojoloj0]0jO|0OjO}0O|0|0|0|O
AA4

READ SEQUENCER ERROR

TRANSMITTER DURING FAULT
TIMEOUT STATUS<2>
TIMEOUT STATUS<1>

TIMEQUT STATUS<0>
SCLD-325

Figure 2-24

Table 2-8

NMI Fault/Status Register Byte 0 - Bit Format

NMI Fault/Status Register Byte 0 - Bit Descriptions

Bit

Name

Description

<04>

READ SEQUENCE
ERROR Fault

Read Sequence Error is another of
the NMI FAULT conditions. It 1is set

data is sent to
return
read
when
no READ command was
when
CPU
the

This

outstanding.

also one of

1is

the NMI FAULT REGISTER bits. If NMI
FAULT RECEIVED is not set, this Dbit

<03>

<02:00>

TRANSMITTER DURING
FAULT

TIMEOUT STATUS
<2:0>

meaning.

has

TRANSMITTER DURING
the

that

CPU

FAULT indicates

was transmitting on

the cycle that caused
in
NMI
the
It is undefined if the
fault.
the
NMI FAULT RECEIVED bit is not set.

type
the
Three-bit field for
occurred.,
that
timeout
following

table shows the encoding

bits:

those

<2>

<K1>

<0> Timeout Code

No Timeout

Reserved

0
1

1
1

Interlock Timeout

0
1

No Access

Mo Access

0
1

VIII

2-68

1
0
1

of
The

Return Read

Data
response

No Access to bus
No Access - interlocked
busy

NMI

Error Address

The
MNMI
error
address
register
holds the address of a CPU NMI
transaction
that
has timed out on the NMI. It is loaded with the
address
from
the
PA
FILE
under the control of the NMI control
store
microcode
when a timeout occurs. This is done by asserting
the
NMI
source
select
bits and strobing the LOAD ERROR ADDRESS
REGISTER
signal
at
the
correct
time.
The
NMI
error address
register
is
read
only
to
the
CPU
microcode.
Figure
2-25
illustrates
and
Table
2-9 describes the format of the NMI Error
Address

313029 2827262524232221201918171615 1413 1211100908 07 06 0504030201 00

A A T
NMI

SOURCE<29:00>

MODE<1> (1B

WRITE ADDRESS)

SCLD-326 |
Figure

Table 2-9

2-25

NMI

Error Address

Format

NMI Error Address Register - Bit Descriptions

Bit

Name

Description

<31:30>

ERROR ADDRESS
REGISTER

In the NMI PA file, the CPU ACCESS
MODE
for the write is stored along
with the write address. If there 1is
of a write operation on
timeout
a
NMI, bits <31:30> of the error
the
loaded with
are
register
address
these saved access mode bits at the
1is
address
write
the
time
same
being loaded into bits <29:00>.
are undefined for read
bits
These
and should be
timeouts,
PIBA
and

Only bits <29:00> contain
ignored.
valid address information for these
types.

VIIT

2-61

Table
Bit

2-9

NMI

Error Address

Name

- Bit

Descriptions

(Cont)

Description

For
the

diagnostic
<capability

Ao+
o
agatca

{+hao
y L

data)

canrreca
SCULCE

into

purposes, there 1is
to load the MD bus
nfF
OL o Fhes
Ui

the

NIMT
INML

error

writo
Wi Ll®

address

When
this
diagnostic
1is
wused,
bits <31:30>

contain

significant

the

special

and
<29:00>

Error

Address

use

their

these

<29:00>

timed out
is loaded
microcode.

the

microcode

diagnostic

Normally

bits

CBox

two

most

bus
data.
This diagnostic function can
only be accessed through the use of
which

bits

seguence,

programmers

create

testing.

bits

contain

address

on the NMI. This
under control of

address

that

has

NMI

Silo

The

NMI

fault,

silo

plus

the

normally

written

NMI

fields

that

the

prevented

from

returning

the

type

cycle

mode,

the

silo

the

with

and

the

data
NMI

and

the

its

silo

with

locked,

counter
the

driven,

thus

cycle,

other

increments
counter

selected

contents

this

are

saved.
silo

the

NMI

the

most

the

decrements

locked.

This

NMI

Silo

Byte

describes

the

READ

format

ONLY

for

=--

the

all

bit

the

reads

and

after

each

silo

2-26

NMI

illustrates

Byte

and

Table

0000000000000000000000]000}000!
!

il
AFTER
DIAG

FAULT

SILO

MARKER

NMI

MEMORY BUSY

NMI

ARB
SCLD-327

2-26

NMI

Silo

Byte

VIII 2-63

write;

313029 28 27262524 232221201918171615 1413121110 0908 07 06 0504 0302
01 00

Figure

recent

not

locations.

Figure

Silo

silo

each

about

successive

when

When

can

information

after

UNDEFINED

place

not

group

taking

read.

The

silo

NMI

with

words,

NMI

the

When

contents

preceding

The

are

capturing

the

address

events

transaction

information

faulting

information.

address

predecessors.

return

the

NMI

cycle.

contents

1is

faulted

cycle

further

older

file

the

indicate
on

of
starting

history

for

Address

reads

cycles,

when

every
that

signal

faulting

locked,

running

events

«c¢ycle.

FAULT

the

255-cycle

Bit

Format

2-10

Table 2-10
Bit

Name

<03>

AFTER FAULT

NMI Silo Byte 2 - Bit Descriptions
Description

AFTER FAULT signal is asserted
The
after NMI FAULT is
for one cycle
deasserted on the NMI. In the silo,
indicates the first line
bit
this
information added to the silo
of
of the NMI
deassertion
the
after
uishes
disting
fault wire. This bit
silo
the
to
added
information
In
faults.
to two separate
leading
when
set
it will only be
general,
the system has a high error rate.

<02>

DIAG SILO MARKER

SILO MARKER is a synonym
DIAG
The
for the LOAD ADDRESS ERROR REGISTER
the CBox
of
out
comes
that
bit

store. It helps diagnostic
control
determine the start of
programmers
diagnostic
special
certain
sequences when examining the silo
after a diagnostic test.

<01:00>

NMI Arbitration
lines

The NMI MEMORY BUSY and NMI IO 0
ARB are two of the NMI arbitration
lines.

VIII 2-64

NMI

Silo

describes

Byte

the

format

=-of

the

Figure

2-27

NMI

Silo

illustrates
Byte

and

Table

2-11

313029 28 27262524232221201918 1716151413 1211100908 07 0605040302 01 00

6/0,0,0/0|0|0OfO|0O|O|O|OfO|0|O|O|O|O|O(0O|0fO|O]O

!
A A2

* T

NMI ID 1 ARB

NMI MEMORY ARB
NMI

LEFT CPU ARB

NM!|

RIGFHT

NM!I

MASK<3>

CPU ARB

NMI

MASK<2>

NMI

MASK<1>

NMI

MASK<0>
SCLD-328

Figure

Table

Bit

Name

<07:04>

NMI

2-27

2-11

NMI

Silo

Byte

Bit

Format

Descriptions

Description
Arbitration

lines

<03:00>

NMI

These

bits

various

MASK<3:0>
'

capture

the

arbitration

devices

the

The

MASK bits

NMI
the

VIII

mask

commander

2-65

for

bus.

command/address
byte

state

lines

contain the ID
during
NMI

cycles,

write

data

and
cycles.

the

NMI

Silo

describes

the

Byte

format

-of

Figure

the

NMI

2-28

Silo -

illustrates and Table
Byte

2-12

313029 2827262524232221201918171615 1413 1211100908 07 0605040302 01 00

ol|o|jojo|O0j0j|O|0OfO|O|O|OfO|O|O|O]|O|O|O|OjO|O]|O]|O

T
NMI

A AA A

FUNCTION<4>

NMI FUNCTION<3>
NMI

FUNCTION<2>

NMI

FUNCTION<1>

NMI

FUNCTION<O>

NMI

PA<29>

NMI CONFIRMATION<1>
NMI

CONFIRMATION<0O>
SCLD-329

Figure

Table

2-28

2-12

Bit

Name

<07:03>

NMI FUNCTION

NMI

Silo Byte

Silo Byte 0

- Bit

<4:0>

The
for

NMI

Descriptions

Description

function

specifies

<02>

Format

<29>

the

field

the

type

the

bus

transfer

NMI

cycle.

This
bit
records
the
state
of
address/data
bit <29>, which is of
interest
during
command/address
transactions
Dbecause
it indicates
that
I/0
address
space
1is being
accessed.

<01:00>

NMI

CONFIRMATION

These

are

¥Wil L \,11%

wh1~h

the

ral=]

confirmation

"']"\D
LW

command/address
earlier.

)

Yesgponse
Lvuyun;uv

transfer

twoc

lines,
to

cycles

Cache

TAG

Figure
Cache

Initialization

2-29
TAG

illustrates

and

Initialization

Table

2-13

describes

the

format

313029 28 27262524232221201918 1716151413 1211100908 07 06 05040302
01

oj0yj0j0/0/0/0j0|0|0jO|0O|O|O|O|O|O|O

the

0|0O|0O|O|O0|0O|O|0O|O]O

i i

Figure

Table

2-29

2-13

Bit

Name

<03:00>

CACHE

Cache

TAG

CACHE TAG

INIT<3>

CACHE TAG

INIT<2>

CACHE TAG

INIT<1>

CACHE TAG

INIT<0>

Initialization

SCLD-330

Bit

Format

Descriptions

Description
TAG

INIT<3:0>

These

bits

with

the

command

are

used

cache
load

the

conjunction

INIT

microcode

cache

tag

bits.

valid

The
main
purpose
is
to
initialize the cache tag RAMS after

powerup

all

valid

The
CPU

The

zero

cache

bits

good

parity

into

the

TAG bits

are

and

cache.

cleared

INIT.

CACHE

cleared

operation.

VIII

putting

2-67

TAG

INIT

before

bits
normal

must

be
CPU

Diagnostic

ID Register

Figure 2-30 illustrates
Diagnostic ID Register.

and

Table

2-14

describes

the

format

the

31302928 27262524232221201918 1716151413 1211100908 07 0605040302 01 00

o|0|0|0|0|0|0Oj0O|0O|0O|O|0|0|0j0|0|0|0j0|0|0|0O|O0]O

0|l0|0}|0

AA A

PROGRAMMABLE ID<3>

PROGRAMMABLE 1D<2>
PROGRAMMABLE

ID<1>

PROGRAMMABLE

1D<0>
SCLD-331

Figure

Table

2-30

2-14

Diagnostic

Bit

Name

<07:04>

PROGRAMMABLE

ID Register

Bit

Format

Descriptions

Description
ID

<3:0>

This

1is

allows

the

replace
transfer

some
the

diagnostic
diagnostic

normal
with

error
CBox.
by

the

bit

the

The

VIIT

2-68

of
ID

CPU

to
NMI

perform

in
is

DIAGNOSTIC ID SELECT
CBox microcode.

PROGRAMMABLE

cleared

programmer

another

that

checking
functions
The
programmable ID

enabled

out

feature

INIT.

bits

are

Diagnostic

Figure

Control

2-31

Diagnostic

illustrates
Control

and

Table

2-15

describes

the

format

the

313029 2827262524 232221201918 171615 1413 1211100908 07 0605040302 01 00

ojo/ofofojojoofo]ojofojo|olojojojo|ojofo]o|olojo]o]o
|

EEE
A

LOAD SILO DURING FAULT ——]
SILO

LOCK ON OVERFLOW

FORCE CONTROL PARITY

ERR

FORCE CPU LOST ARB

FORCE FUNC ACK OK

Figure

Table

2-15

Bit

Name

<04>

LOAD
FAULT

2-31

Diagnostic

Control

SCLD-332

Bit

Format

Descriptions

Description
SILO

DURING

Prevents
NMI

This
0

the

SILO

bit

asserted

asserted.

initialization
FAULT

This

bit

writing

silo

VIIT

from

locking

FAULT.

2-69

asserted

must
a

lock

one

LOAD

that

SILO

after

be
to

low:

cleared
CPU

DURING
INIT.

deasserted
it)

properly

is,
CPU

cause

FAULT.

(by
the

Table

2-15

Bit

Name

<03>

SILO

Diagnostic Control Register - Bit

Descriptions

(Cont)

Description
LOCK ON

OVERFLOW

Causes

the

when

the

NMI

overflow.

be
the

This

stop

address

permits

loading
counters

the

silo

stopped
even in the absence of
NMI FAULT signal, which is the

normal
silo.
This
0

silo

mechanism

bit

for

asserted

asserted.

locking

low:

the

that

cleared

1is,

CPU

initialization
so
SILO
LOCK
ON
is
asserted
after
CPU
INIT.
This
bit must be deasserted

OVERFLOW

02>

FORCE

CONTROL

PARITY

(by

writing

the

silo

correctly

load

(until

Forces

one

FAULT

the

NMI

it)

allow

continue

received.)

control

parity

generation
logic
to
transmit bad
parity
along
with
the
current
FUNCTION/ID
MASK
transfer
on the

ERR

NMI.

Cleared

<01>

FORCE

CPU

LOST

ARB

Forces

the

bus

NMI

Cleared

<00>

FORCE

FUNC

ACK

This
to

INIT.

CPU

enables

vyaraiund
EA A
YA Y2
e
A

the

ARB

from

logic.

INIT.

diagnostic
the

indicates
a

to get

arbitration

generate

which
sent

CPU

command
rmnacitivre

hJVhJJ.\..LV\.d

ACK
that
to

programmers
OK
the

the

signal,
CPU
NMI

amnrbnAawlelAAamandt:

MVJ\IIU'V.LV\A&LLL\/IA\.

has
and
+A
LR

command, which permits testing
some
hardware
1in
the
CBox
without
actually having to use the
of

NMI

bus.

Digital Equipment Corporation.Bedford, MA 01730