VAX 8800 System Technical Description Volume 2

This document is "VAX 8800 System Technical Description, Volume 2 (EK-KA882-TD-PRE)," a preliminary edition from July 1986, prepared by Digital Equipment Corporation's Educational Services for internal use. It provides a detailed technical overview of the VAX 8800 system, specifically focusing on its core hardware components and their functional logic.

The key areas covered in this volume include:

• Instruction Box (IBOX): Describes the CPU's instruction unit, including its microcode structure, instruction buffering, macroinstruction decoding, microsequencing, interrupt and processor register logic, and the internal bus architecture. It elaborates on microcode pipelining concepts, canonical time states, and internal privileged registers (IPRs).
• Execution Box (EBOX): Details the CPU's execution unit, covering the arithmetic logic unit (ALU), shifter module, multiplier/divider, and various EBOX-specific registers responsible for data manipulation and program counter management.
• Cache Box (CBOX): Explains the cache unit's operation, including the Translation Buffer (TB) for virtual-to-physical address translation, cache memory operations, and the NMI (Memory Interconnect) interface, along with their associated control and error handling.
• Memory System (MBOX): Provides an in-depth look at the memory controller and the Four Megabyte Memory Array Board (MAR4), detailing bus cycles, write/read operations, error correction, and battery mode functionality.
• NBI (NMI to VAXBI Adapter): Describes the interface facilitating communication between the NMI and the VAXBI bus, covering registers, data transfer, and interrupt handling mechanisms.

The document delves into intricate details of hardware design, control signals, timing relationships (including microcycles and pipeline stages), and the interaction between microcode and hardware elements. It is intended for an audience requiring a deep technical understanding of the VAX 8800 system's internal workings.