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July 1986

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Document:	VAX 8800 System Technical Description Volume 1
Order Number:	EK-KA881-TD
Revision:	PRE
Pages:	540
Original Filename:

OCR Text

EK-KA881-TD-PRE

VAX 8800 System

Technical Description
Volume 1

FOR INTERNAL USE ONLY

ify

EK-KA881-TD-PRE

VAX 8800 System

Technical Description
Volume 1

FOR INTERNAL USE ONLY

Prepared by Educational Services

of
Digital Equipment Corporation

Preliminary Edition,

July 1986

Rights Reserved

The information in this document is subject to change
notice and should not be construed as a
without
Digital
commitment by Digital Equipment Corporation.
for any
ty
sibili
respon
no
s
Equipment Corporation assume
errors that may appear in this document.
Printed

U.S.A.

Class A Computing Devices

Notice:

This equipment generates, uses,

and

may

emit

The equipment has been type
radio frequency energy.
tested and found to comply with the limits for a Class A

computing device pursuant to Subpart J of Part 15 of FCC
reasonable
provide
to
rules, which are designed
erence
interf
ncy
protection against such radio freque
of
ion
Operat
when operated in a commercial environment.

a residential area may cause
in
equipment
this
interference in which case the user at his own expense

required

may

The

following

take

measures

correct

thne

interference.

Corporation:

are

trademarks

Digital

Equipment

logo

DECwriter

RSX

DEC
DECmate
DECset
DECsystem-10
DECSYSTEM-20
DECUS

MASSBUS
PDP
P/0S
Professional
Rainbow
RSTS

ULTRIX
UNIBUS
VAX
VMS
VT
Work Processor

logo

DIBOL

Scholar

CONTENTS

Clock

Memory

Box.

Unit.,

Module

(MBox).

Control

Loglc

Array.

Buses

Memory

Interconnect

Interconnect
Bus

.
c

(VAXBI)

(VBus).,

Interconnect

and

I/0

(NMI)

Adapters.

Complex

o«

Port

NBox

Controller

Conditioner.

Power

Environmental
Battery

Monitoring

Backup

Unit.

Module.

CONTROL

Software

Hardware

e«

[]

b
N

W N
B

®
L]

Multiple

File

Transfer

Logical

N
W

[]

Console
Console

Data

Streams

Program.
Server

Interface

SUPPORT

CSM

Block

Real-Time

CONSOLE

Command

Program

Driver

MICROCODE

Support

COMPONENTS.
.
.
.
.«
Program.
.,
.
.
.
.
.
.
o
o
Special Control Program
Features

SOFTWARE

Control

o
.

«
.

(CsSM).

Microcode Structure.
.
Transfers/Protocol.
c
e
o
o
W
Support Microcode Entry Poin
ts

iii

+
.,

.
.

U B

.
.

CONTROL

NDNDNDNDNDN NN
N NN N

SYSTEM

Supplies.

[

Subsystem.
Processing

JWWN

W
o

Module

N =~

e
e

System

CONSOLE

e
*

e
o

Power

SYSTEM

e
o

Memory

GENERAL.

[]

876
5

L]
L]
-

Bus

.h.b.h.::.wwwwwwwwwwo—'

MO ODNDNNNDNONNODNDNDNND
N

Visibility

8800

Bus

VAX

Power

VAX

Box.

System

Box.

MAR4

Memory

Execution

DESCRIPTION

Cache

DESCRIPTION

Instruction

.2,

Console

.2,

Central

.2,

NSO

PHYSICAL

.
.

DOCUMENTATION.

DESCRIPTION

FUNCTIONAL

CHAPTER

[]

SCOPE .,
.
.
.
ORGANIZATION.

SYSTEM

L[ Z

MANUAL
MANUAL

i e e

INTRODUCTION

OVERVIEW

SYSTEM

CHAPTER

AND

—

INTRODUCTION

O\G\O’\O\O\O\O\O?\O\O\O\O\O‘\G\ mmmmmmmm.&wms—'

r—-r—-w—w—-w-—w—-w—u-w—u—w—w-—-n—-w-- I——‘l—‘b—‘l—‘b—-‘o—‘l—'r—'l——'b—-‘b—-‘l—J

SECTION

s
LOCa

Logical Terminals/Logfile Integrity.

Displaying the Logfile

.«

Power

owerdown.,

Warm Restart

CHAPTER 3

SYSTEM OPERATION
.

Structure.

=
N

.
.

Microcode Control.

Interrupt and Processor Register

Condition Code and Branch
Gateway Control (GWYC)
Microbranch Clicreg
Pipelining . . . .
W/

Stop on Match.
Trap on Match.

.
.

Micromatch

Microtraps

(UTRP)

Microtrap

o~~~

b
W
-

8
e

=
N

¢«

.«

Format

Addresses

Table

Entry

Cache Operation. .
Translation Buffer
=

NMI

Interface.

Cache.

Page

—

W W N

Address Translation.

B
b

Layout

Physical

UBRS)

MEMORY ADDRESSING AND READ/WRITE
Virtual Addresses.

(CCBR)

[]

[

Functionality.
Operation. . .

L]
LJ

@
e
L]
.

Microcode Characteristics

U wWwhNhDNDNDNON
- -

W N

[]
[]

WwWwwwwwwwwwwihdbdoNpdn NN

INTRODUCTION

Saving the Logfile .
- POWER-UP/DOWN SEQUENCING
Fail

Operation.

OPERATIONS

oo
owo oo oot B LW W W W W NN

System Logfile
.

During Remote

W wwwwwww w wWww
11
|
|
I

Display

TAr~nal

Cconsole Command Language Display Prompts

W wwwww
] WwWwwwwwww W
|
1
|
|
1t
[
i el ol |

[]

Executing Console Commands
Console/Operator Display .

Saving Console State
Console Commands .

Console State Bits
Command Validity

Power

wwwwwwwwwwwwwwwwwww W wwwwwwww

OPERATOR/CONSOLE INTERACTION

s s BB WWWNND

[]

\J\INJ\IG\G\G\O\O\O\O\G\O\ONO‘\O\O\U’\U'IU'I

NNMRNMNOMMNMNDNODNNNDNDNDNDNDDNDDODD NN

.
.
.

OPERATIONAL MODES.
Console Mode . .
Program Mode . .

3-17

3-19

Significant
.

¢«

Format.

3-21

Connected
.

Exception.
.

3-23

Devices.

3-25

o«

DIAGNOSTICS.

&«

3-24

Microdiagnostics

Information

Messages.

Diagnostics.

.
.

N
w

and

Error

Error
.

Runnable

o«

Remote Diagnostics .
.
.
POWER/ENVIRONMENTAL SYSTEM

¢«

Placement

Verification.,

Module

Key

Test.

Module

Placement

Monitoring/Error

Default

Mode

Operational
Voltage

Machine

Error

Margining.
AIDS

Check

Mode.

¢«

Reporting

Reporting.

.
.

¢«

o«

Stack

Logout

Mode

Auto-Test

Selftest

Commands

3-23

¢«

3-20

(SCB)

AIDS

Micromonitor

MAINTENANCE

Status

INTRODUCTION

CSM

Block

W
.

Ul
.

3-20

GENERAL.,

Power
e

3-20

Exceptions.

AND

DIAGNOSTIC

3-20

Direct

3-20

Devices

Check

Offsetable

o
.

VAXBI

Format

o
.

Pagination

Types

3-20

SCB

Module

Interrupt.

Levels.

Control

Customer

WNoDNDNND P

3-19

SO S

the

Macrodiagnostics

—

Enable

Bits
.

SN S

Interrupts.

Node

Address

EXCEPTIONS.

—

s
[
!
COOQOOWWXNO
s WWW =

Console

.
.

System

SCB

.
.

ped pd

=
N
w

Servicing

=W
-

W W N
W

Types

.
.

Interrupt

Priority

NMI

Selection

—

@
*®

OO
U

e
I

[]

. N SR PSRN UU I Y
L
N

S
L]

ST~ S S

.
[]

T
DWW
W N

[]
®
e
"

BB
DU

AND

MAINTENANCE
L]

S
S
S
S
e
o

SR N

QN SN SO SO

LSS DWWWWwww

S
®

S
Y
1

Transaction

SErviCing.

CHAPTER

Operations.

Address

INTERRUPTS

Device

Machine
e

WWWWwwwwwwwwwwwwww

Read/Write

FIGURES

Title

Locations

VAX 8800 System Major Component
(Rear

View).

Subsystem.

Simplified
Simplified

Block
Block

Diagram of
Diagram of

Single CPU .
the CPU IBox

.
.

BOX:e

Diagram
Diagram
Diagram
Diagram

of
of
of
of

the
the
the
the

Interconnect

the CPU Execution

Simplified Block
Simplified Block
Simplified Block
Simplified Block
.

CBox . .
.« .
Clock Modulp . .
MBox . . .
.
VAX 8800 Memory
e

Simplified Diagram of VAX Bus Interconnect
(Maximum Configuration). . « + « ¢ « + « o
I/0 Interconnect and
NMI~to—-VAXBI Adapter

Simplified
System

N
w

~OY
U1 o
W N

[

W wwwwww

«©

Adapters.
«
«
o«
«
o

Diagram of

System Hardware

ComponentsS

Block

Complex

VAX 8800

3-11

o
.
System.

Simplified Block Diagram of

3-10

Cardcage Module Layout (Front Vlew;. o« o
Simplified Block Diagram of the VAX 8800
Simplified Block Diagram of the Console

the
¢

Simplified

Pipelining.

Address

Space

Virtual

Address

Format

Physical

Address

MAP

Enable

Page

Table

Software
o

«
o

Translation.

Process

Space

(Pl

o
o

s
e

¢«

Layout.

o«

Conflguratlon.

Reglon)

NMI

Address

3-13

NBI

I/0 Adapter

Bit

.«

Region)

o«

o
.
¢

o
«
o

o
«
¢

Significance

Vector

Vlrtual to- Phy31cal
o«
.
.+

SCB

Vlrtual
-to-Physical

Address TranslatiofN. . ¢« «
CBox Functional Components
NMI Address Selection. . .

3-12

o
.«

Configuration

Address

.
e
Flow

(PO

Control

Translation.

&
o

Address

Space

o
.«

System Space Virtual-to- Physical

Process

o
o

Power

+«
o

.
o

Layout

Space

Entry

.
o

and

Console Operational Modes. . .
Local/Remote Display Character

Virtual

.
o

Offset

o
«
o

o
o
o

¢«

Format

=
o
&
e

Module

Key

Margin

Enable

Machine

Check

Test

Simplified

Connections.

and

Margin

Logout

Block

4-2

Diagram.

4-11

4-15

Testing.

Keying

.
«
e
Registers

Bottom-Up

Module

4-12

Stack

Error

o«

CBox

Error

IBox

EBox

NMI

Interrupt

NMI

Fault

NMI

Silo

NMI

Error

Cache

Control

Summary.

Data.

4-17
4-18

4-18
.

4-19

4-20

o«

4-21

Address

Machine

Check

1/2

4-22

Revision

Status

Registers

4-22

TABLES

Title
Technical
Related
VAX

8800

Cabinet
Power
VAX

Description

Documentation.
System

Supply

Characteristics

Identification.

Functional

Units/Data

Bus

Operations

¢«

Descriptions.

o«

Descriptions.

Command

NMI

Function

Optional
NBIA

Organization,

Clocks.

MCL

VAXBI

Identification.

Processor

Descriptions
System

Physical

Module

8800

Manual

VAX

Bus

Registers

Interconnect

Adapters
.

NBIB

Registers

NBox

Modules

o«

Description.

Hardware

Major

Software

Sections

Console

Bit

and

Support

Examples

Component

CSM

Code

Microcode

Entry

Points

Console

Command

Conscle

Overview

Command

Language

¢«

Prompts

Sequence

Module

VAX
Page

Power

8800

System

Table

Translation
Hardware

Supply

Microtraps

Entry

Bit

Buffer

Interrupt

System

Control

Machine

Check

Turn-On

Description

Field

Priority

Block

Description

Page

Exception

vii

Level

Assignments,

(000--1FF)

Examples

Macrodiagnostic Tests.

.«

EXAMPLES

Title

Sample Microdiagnostic Display Output.

Sample Mlcrodlagnostlc Error Display .
&

EMM Warning Messag

CHAPTER

MEMORY INTERCONNECT (NMI)
INTRODUCTION &« &«
BASIC FUNCTIONS

NMI

o
o

Interrupts.

&«

o
.
¢«
¢

o
.
¢
o

¢
«
o
o

o
«
o«
o

o
.+
o
o

o«

o
e

o
o

o
s

o
e

s
o

o
.«
«

¢
«
o

o
«
o

o
o
o

BASIC VAXBI TRANSACTION FORMAT
Command/Address Cycle. . « .«
EFmbedded Arbitration Cycle .

e
«
.

o
«
.

e
«
.

e
.
=«

NMI

VAX

—

BUS

TR TN

AR TAT T

o
.

INTERCONNECUTL

INTRODUCTION o« o«
BASIC FUNCTIONS.

VAXBI

o
.

Faults
ERRORS .

NMI

SIGNALS AND TIMING

VAXBI ADDRESS SPACE. .
Memory Address Space
I1/0 Address SpPacC. «

.«

Device

o
=
&

=
N

o«

¢«

NMI Interrupt Priority Levels.

UTULE W
NN

NN NNMNNDNDNODNONNDNONDNDDNDNDND

SIGNALS AND TIMING

INTERRUPTS

CHAPTER 2

NMI ADDRESS SPACE. . .« ¢
READ/WRITE TRANSACTIONS.
INTERLOCKED OPERATIONS .
BUS ARBITRATION. « ¢ ¢ o

L ]

SYSTEM BUS SUMMARY

OO OO0
Ul
W

L
s el el sl i

SECTION

«
.
«

Address Selection.

o«

BUus Parity « o « o o o
READ/WRITE TRANSACTIONS.
Write Data Cycles. . .«
Read Data Cycles . ¢« «
Nonexistent AddressesS.

o
.
«
¢
.

o
.«
«
«
«

o
«
o
o
«

o
«
o
«
«

Data

CyclesS.

"Vv1i1l1l

o
+
o
o
o

o
«
o
o
o«

oy
N

.«

CSM

Diagnostic

Microcode Error Register Addresses

TEMP Register Addresses for Use with

Stalls

Retries.

2-23

TRANSACTIONS

2—-24

BROADCAST

INVALIDATE

TRANSACTIONS.

2—-24

INTERRUPT

OPERATION

2~26

(INTR,

IDENT,

Interrupt

(INTR)

Identify

Transactions.

(IDENT)

Transactions.

AND

2-28
2-29
2-31

Interprocessor

Interrupt

Transaction.

(IPINTR)

TRANSACTIONS.

2-36

CONTROL.

2-38

2.10

STOP

2.11

BUS

ARBITRATION

AND

2-34

2.11.1

Bus

2.11.2

Arbitration

2-38

2.11.3

Modes.

2.11.4

Control.

Extending

.
.
Transaction.,

2-39

2-41

Mode

ERRORS

Functions

2-41

2-42

Checking.

2.12.1

Parity

2.12.2

Transmit

Check

2.12.3

Protocol

Checking.

2-43

2-44

(VBUS)
o

FUNCTIONS.

.
.

VBUS

SIGNALS

REGISTERS

CIRCUITRY.

VBUS

Minimum

Configuration.

Expanded

Configuration

SUMMARY.

CHANNEL

VBUS

ADDRESS/DATA

VBUS

CONSOLE

COMMANDS.

Title
Memory

Interconnect

NMI

Timing

(NMI).,

.
.

Signals.

.«

NMI

Address

Space.

o«

NMI

Address

Bits

NMI

Address

Selection.

NMI

Write

Transaction.

NMI

Read

NMI

Write

Types.

NMI

e
|

Basic

prd
0]

FIGURES

O OO
U D WN

2-42

Detection

VBUS

MODULE
N

BUS

VISIBILITY

INTRODUCTION

[]

BASIC

~NOoO

W wwwwwwww

CHAPTER

Error

Fwwwwwww
I
I

VAXBI

Transaction

OO~

Special

2.12

—

2.11.5

Requests

NMI Arbitrator Operation
o
«

o
«

o
o«

o
«

s
o

o«
o

(VAXBI)

Timing

SpPace.

.«

Node Register SpacC€.
Required Registers .

«
«

«
.

«
«

&
«

o
¢

o
o

o
=

VAXBI Write Transaction (Octaword Length).
VAXBI Read Transaction (Octaword Length) .
VAXBI Broadcast (BDCST) Transaction

.
.

H WO
= 00 ~IOY U
N

.
.
.

« « «
VAXBI STOP Transaction
Lines.
Request
Bus Arbitration
Arbitration State Diagram. . +
VAXBI Arbitration (Example). .

«
.
«
.

«
.
«
«

o
.
«
«

o+
«
o«
.«

o
+
o
«

«
.«
o
.

o
&

o
o
o

o
o
¢

o+
o
o

=
=
o

VAXBI
VAXBI
VAXBI
VAXBI

o«

TransSactioN.

Visibility Bus

and VBus Control

(VBus)

(on CLK Module). « & o
VBus Control Register.
VBus Access Register .

VBus Channel

«
.
.

o
.
¢«

in CPU Module

Co“flguratlon)

Configuration)

o
«
¢

o
o«
¢

o
o
o

o
«
o«

(Minimum

o
o
¢

‘

VBus Channel in CPU Modulp (Expénaea
.

o ~Ju

Length).

Invalidate (INVAL) Transaction . .
Interrupt (INTR) Transaction . . .
Identify (IDENT) Transaction . . .
Interprocessor Interrupt (IPINTR)

.
.
o

.
.«
.

.
.«

.
.
.

.
.

.
.
.

l\)l\)l\lJN
|
|

.
.

BIIC-Specific Device Registers
VAXBI Read/Write Address Bits.
Basic VAXBI Transaction Format

(O3]

VAXBI
VAXBI

NN NDNDDNDDNDDND
b
o
|
]
e
e

Address

VAXBI

DO N b= b

|
Oy UT W

Basic VAXBI

N = O

o
o

Interconnect

SignalsS.

VAXBI

o
et

o
o

Bus

(Octaword

o
.

MEMORY BUSY Timing .+
Fault Signal Timing.

Detailed NMI Arbitration Line Timing

VAX

|
O 00~

MR NDNDNNNDNDDDDDNDNDNDND

1-13

W WM

1-12

.«

Basic NMI Arbitration Line Timing.

1-11

Read Transaction Type€S

NMI

1-10

o«

TABLES
Page

|
W

e
N

Title

Glossary
NMI

Signal

1-3

Descriptions.

1-10

TermS.

NMI

Registers in NBI and Memory Controller
Interrupt Priority Levels (IPLs) . . .

NMT

INESE 2FaY

1/0
N A

LYrrors

.
.

1-21
1-39
1-43

.
.

INTERACTION

Invalid.

Stopped/WCS

Clock

Running/WCS

Clock

Invalid.

Running/WCS

valid.,

State

Description.

SOFTWARE

COMPONENTS.

=
W N

SEQUENCE.

toc Figure 1-3.
.
Initialize (Refer to

=
N

8800

POWER

{Refer

YYD
e

Power

Server Program
Interface Driver .

Fail

Powerdown

(Refer
(Refer

to
to

FUNCTION

DESCRIPTION

GENERAL.

REAL-TIME

INTERFACE

Programmable

Figure
Figure

.
.
.
(RTI).

Peripheral

Figure

1
.

1 -19

1 -21

[

.
/D

Interface

000

Port

000

Control.

Port

ECPI

Data

Line

Registers

Transfer

and

Status

Port
PPI

Port

Serial

(O]

1-6)
1-7).

Clock

WWWH

Off.

—

Power

Description

Registers

OO0

State

[

8800
Mode.

|
I e e o B e T o S Ry S
O W
(R——— —
|
i
i
{I T
I
[
|
QOO WL VWOUNITOAO
OO SN
O O SY

Figure 1—4)0
.
.
.
.
.
.
Restart/Boot/Halt (Refer

U1
o
W

EMM/Console

Real-Time

=W
N

fod

AND

oD
NN

Powe riim
D

CONSOLE/VAX

REFERENCES

Program.

Block

PURPOSE

Logical

[]

Control

I/0.

Console

COMPONENTS

8800

CONSOLE

(Excerpt)

W w

Descriptions

.
.

Bit

Console
=W
N

=W wwww
N

&
o
¢

»
e

[

AND

Power-Up

[]
L]

CONSOLE/VAX

[]
[]

.
.

FUNCTION

.
.

DOCUMENTATION

SUBSYSTEM

Tl e
L]

R S e R R
i

L]
®

e e e

[
»

e
o

——

DN NDNDDNDDNDNDND
-

o
e

CHAPTER

.
.

SUBSYSTEM

GENERAL.

) T [y O

NN OO
W N

INTRODUCTION

.
.

RELATED DOCUMENTATION

1-2 provides a 1list of related documents containing
Table
. The
additional information pertaining to the VAX 8800 system
ble at
availa
n
ntatio
docume
to
refer
references listed in the table
des a
provi
l
manua
this
of
on
secti
FEach
the system level only.
list of related information for the specific area of the system if
applicable.

1 1-2

Table

1-2

Documentation

Title

Document

VAX

8800

System

VAX

Hardware

8800

System

Diagnostic

User's
Guide

User's

VAX

8800

System

VAX

Maintenance

8800

System

VAX

8800

Installation

Site

VAX

8800

Field

Preparation

1.4

SYSTEM

The

following

description
an

The

VAX

System

either
The

8800

all

single

EK-8800P-SP-001

with
an

VAX/VMS

general,

8800

system.

major

technical

dual-CPU

VAX

provide

the

1is

VAX

the

provide
the

interact

system

supports

how

chapters

adaptable

Guide

Set

DESCRIPTION

explanation

subsequent

EK-88XV1-MG-001
EK-8800I-IN-001

Planning

paragraphs
description
of
is
intended to

functional

EK-8800H-UG-001
EK-KA88D-UG-001

Guide

and

Maintenance

Guide

Number

overview

components

each

and

high

operating

system

the

system

and

the

performance

system
applications.
The

commercial

system.

and

functional

described

other.

LSI-based,

physical,
The

and

configured

dual-CPU

primary

CPU

assigned

1.5

system allows asymmetrical
multiprocessing with the
performing
all I/O transfers.
The secondary CPU is
perform compute-ready processe
s.
'

PHYSICAL

Figure

1-1

DESCRIPTION

shows

the

and

the

list

each

characteristic.

1location

the

The

system
following:

physical

1is

Module

cabinet

the

power

dual-CPU

components.

characteristics

housed

Cooling

layout

major

and

H9650

VAX

Table

applicable

cabinet

8800

1-3

system

provides

parameters

for

contains

the

and

system

Module

cardcage (backplane)
Input/output bulkhead

H9652

input
Figure

lists
1-5

expansion

transformer
1-2

and

shows a
identifies

identifies

the

cabinet

the

layout

the

system
of

used

VAX

house

the

1-3

the

backup

8800

contained
in

battery

the

modules

used

power

cardcage

module

system

Table

1-4

unit.

the

and

cardcage.

power

system

Table
(MPS).

A.M.D.

TS2

AFS

TS3

H7188]

AES

TS4

MPS BACKPLANE # 2

|€———MPS BACKPLANE # t+—Pl€—
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300 VBUS # 2

300 VBUS # 3

300 VBUS # 1

MODULAR POWER SUPPLIES, BACKPLANE, AND CAGE

CPU

MEMORY

cPU

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LOGIC CARDCAGE
1/0

NBOX

NOTE:

TS1

BULKHEAD

876

POWER

CONTROLLER

TS = TEMPERATURE SENSE
AFS = AIR FLOW SENSE
A.M.D = AIR MOVING DEVICE
SCLD-74

Table

1-3

VAX

8800

System

Physical

Characteristics

Parameters

Cabinet

Type

H9650

Cabinet

Dimensions

Width

46.5

Height

61.5

inches

Depth

30.0

inches

6500

Watts

Characteristics

inches

Environmental

Estimated

Maximum

Heat

Temperature

Rise

Degrees

Operational

Nonoperational

-40

Temperature

Celsius

Range

Humidity

Degrees

Celsius

Degrees

Celsius

Operational

percent

Nonoperational

relative

humidity

percent

relative

humidity

Cooling

System

Type

Air moving

Drive

Air
Air

Mover

device

Three

phase

induction

Quad

inlet,

208
dual

Vac,

outlet

blower

Source

Electrical
Input

Vac,

centrifugal
:

Filtered

ambient

air

Requirements

Three
50

Internally

Hz/440

motor

Generated

phase

300

Vvdc

+ /-5

Vvdc

+/-12
+10

Vvdc

Vdc

-5.2

Vdc

-2.0

vdc

1-5

208

Vac,

Hz/440

Vac,

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Figure

1-2

Cardcage

Module

Layout

(Front

View)

Table

1-4

Cabinet

Slot

Module

Description

WCS

SEQ

Writable

DEC

CCS

ADP

SLCO

SLC1

SHR

NBIA

CLK
NBIA

WCS

SEQ

DEC

16
17

CCs
ADP

SLCO

Address

Data

Slice

Right
Right

Data

Slice

Right

Sequencer

Right

Path

Right

Right
Right

Shifter

I/0

Right

Both

Reserved
Clock
I/0

and

Console

2
Writable

Interface

Both
Both

Control

Store

Sequencer

Left
Left

Instruction Decoder
Cache Control Sequencer
Address Data Path

Left

Left
Left

Data

Slice

Left

Controller

Both

SLC1

Data

SHR

MCL

Shifter
Memory

MAR4

4-Mbyte

VAXBIO/

VAX

Bus

VAXBI1

Table

1-5

Supply

Left

Memory

Array
Interconnect

Power

Supply

Both
Options

Both

Identification

Description

MOD

H7186

MOD

+5.0

H7186

Vdc

Supply

MOD

+5.0

H7187

Vdc

Supply

=-2.0

Vdc

Supply

H7180

=5.2

EMM

MOD

Store

Decoder

Control

Power

Control

Instruction

Cache

Identification

CPU

Sequencer

10
12

Module

Environmental

Vdc

(Battery

Monitoring

Backup)

Module

Supply

MOD
F

H7189

MOD

+5.0,

H7189

-2.0,

+/-12,

-5.2,

+5.0,

+15

Vvdc

-2.0,

+/-12,

Supply

-5.2,

+15

vdc

Supply

Figure

1-3

1.6
The

FUNCTIONAL
VAX

the

8800

console

subsystem
Oor

two

system

with
VAX

8800

memory
connect

one

path

4-Mbyte

CPU,

(VAXBI)

(NMI).
bus

shown

arrays,

synchronous

between

VAX

primary

interconnect

through

the

eight

interconnect

communications

that

configuration

subsystem,

bus

interconnected

DESCRIPTION

The
the

1-7

secondary
power

backplane

NMI

bus

provides

CPUs,

memory,

consists

CPU,

system,

adapters.

interconnects.,

The

and

one

system

called

the

memory
and

the

VAX

system with
the

adapters

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HOLINOW

Console

1.6.1
The

console

Figure
stores,

1-4,

and

Subsystem

subsystem

controls

general
Series 380

in the simplified block diagram of

—

shown

power

the

seguencing, loading of control

VAX
the
operation
with
8N)
(PRO-3
Computer

and dual floppy disks is used as a console device
-y

system.
T

1-8

8800

system.

a Winchester disk
for

the

VAX

8800

Communication

between

accomplished

interface

the

VAX

8800

The

console
computer
interface
(RTI)
that

PRO-38N

VAX

path

between

clock

module.

The

RTI

line

units
PPI

and

control

One

the

PRO-38N

the

three

the

SLUs

with

the

ability

The

other

connected

This
VAX

8800

The

SLU

has

rear

remote

port

the

of
an

Refer

SLU

the

VAX

8800

DATA

input

located

not

the

PRO-38N

optional

rear

contains

printer
1link

console

can

the

this

1-9

I1/0

two

data,

provides

and
on

ports

serial

address,

interface.
monitoring

the

TRANSMIT

the

VAX

used

currently

console

power

serial

DATA

8800

for

the

output

bulkhead.

simple

supported

printer

and

data

the

port

for

console.

that

manual

subsystem.

and

system.

established

PRO-38N

located

environmental

could

six-slot

communications

console

monitor

CPUs

console

real-time

the

several

(PPI)

the

and

connector
but

and

complex,

connector

transferring

console

the

with

8800

the

interface

software.

Section
the

RECEIVE

control.

concerning

for

six

provides

interface

control

PR0O-38N,

diagnostic
the

RTI

VAX

from

called

slot

console

ports
the

1in

the

and

option

processor

system

spare

the

connected

power

spare
the

console

connecting
A

the

parameters

wunused

transters

8-bit

1is

(EMM)

The

peripheral

between

module

environmental

and

module.

console

programmable

signals

either

data

an I/0
installed

1is

interconnect.

contains

and

contains

(SLU).

The

clock

bus

provides

including

console

transferring

for

through

configured

detailed

existing
for

modem

information

VAX 8800 CABINET

PRO-38N CONSOLE COMPUTER

REAL-TIME

WINCHESTER

CLOCK MODULE

INTERFACE

DISK

PRIMARY
CPU

CONSOLE
|€—

PPl

INTERFACE

DUAL
FLOPPY

DiISK

StLU

DISPLAY

BROCESSOR

AND
KEYBOARD

POWER SYSTEM

SECONDARY
cPuU

EMM

512K

MEMORY

NONVOLATILE

TODR CLOCK

OPTIONAL
PRINTER

REMOTE
TERMINAL
SCLD-77

Figure

Simplified Block Diagram of the Console Subsystem

1-4

Central Processing Unit

1.6.2

The VAX 8800 processor shown in Figure 1-5 consists of three
The
and associated data transfer buses.
units
functional
Table
in
d
describe
and
listed
are
buses
functional units and data
‘._.l.

1-6.

the following individual sections of this manual for

Refer
.

Ama‘l

LiUulliadal

Ormatlon

Functional

nannnrn1ng

Unit

Instruction BoOX
Execution Box
Cache Box

+he
[

Section
5
6
7

1-1a

functlonal

nn1fq

fh@

CPU:

Table

1-6

VAX

8800

Processor

Functional

Units/Data

Descriptions

Functional

Unit/Bus

Instruction

Box

Description
CPU

microcode

store

the

writable

control

decoder
Execution

Box

and

Processes

data

logical,
SLCl),

Box

and

Contains
the

the
the

the

1is

and

buffered

data

sequencer

Address

Bus

Data

Cache

Data

Bus

Data

and

Write

Data

Bus

Bypass

Bus

CBox

path

(ADP)

for

from

box

the

for

the

cache.

Bypass

written

into,

Bus

Slow
Lo

speed
access

Instruction

Bus

Buffer

Data

The

path

data

address
and

cache

write

data

but

data

that

bus

for

data.

are

The

mapped

address
control

virtual

address

the

cache.

the

execution

the

vet

and

the

CPU

box.

longword

addresses,

displacements

transferred

valid

console

execution

absolute

bus.

have

the

data

box

execution

scheduled

word,

Branch

data

the

allows

byte,

also

buffer

1-11

direct

cache.

cache

latched

displacements,

immediate

index,

and
The

and

not

that

transfer

consists

instruction

I/0.

direct

from

does

internally

literals

buffer,

the

modules.

Data

and

consists

the

data.
Visibility

EBox

parser.

path

transferring

execution

path

The

modules.

instruction

Data

box
Cache/ALU

the

The

(CCS)

path

from

and

physical

and

(SLCO

virtual-to-physical

translations.

address

cache

module.

write-through

buffer

the

arithmetic,

translation

64-KByte

the

modules

(SHR)

and

(SEQ).

operations.

memory

cache

from

slice

cache,

mapped

translation

Virtual

shift
data

(DEC)

Performs

shifter

interface

Consists

(WCS),

modules

received

bit

control.

store

boxes,

and

consists

and

sequencer

instruction

Cache

Bus

over

and

the

CONSOLE SUBSYSTEM

CLOCK AND CONSOLE INTERFACE
?

CLOCKS

VISIBILITY BUS
CONSOLE | DATA

INSTRUCTION BOX
CACHE

BUS

DATA \

WORD

IBOX

MICRO-

BUS

o
g —

—>

wsusl
>

EXECUTION BOX

BUS

BYPASS

CACHE BOX

T
Figure 1-5

CPU

NMI
SCLD-78

Simplified Block Diagram of Single CPU

1 1-12

1.6.2.1
Figure

Instruction
1-6

functions
®

the

performed

Buffering

received
®

Box

CPU's

the

from

Decoding

The

microcode

IBox

instruction
store

cache

and

box

(I Bo X)
wr

control

Monitoring

and

VAX

instruction

controlling

servicing

the

microtraps,

exceptions.
®

Supplying

)

instruction

immediate

data)

Providing

stream

the

stream

data

execution

interrupts,

and

embedded

execution

interface

between

data

(literals,

box.
the

clock

CPU.

module

and

CACHE DATA BUS
IB

DATA BUS

it OP
SPEC?EER
CO
BUFFER

RD TALIGN

INSTRUCTION

|«

MANAGER

BUFFER

INSTRUCTION

» DECODER

FILE

BUS

ADDRESS | »| WATCHER O NTROL

DECODER CONTROL

» MJ Imicro. | conTROL <

CONDITION

CODE AND
BRANCH

BRANCH

INTERRUPT [
LOGIC

MICRO-

”|

SEQUENCER

Fworp

] STORE

{’

»TO EBOX

»TO CBOX—p

—p

SEQUENCING CONTROL

CONS DATA/CONTROL

GATEWAY

CONTROL

SCLD-79

Figure

1-6

Simplified

Block
T

Major

box.

microinstructions.

shown

cen ter.

include:

prefetched

the

and

1-13

Diagram

the

CPU

1Rox

the

The
the

1IBox

resides on the

following

DEC,

SEQ,

and WCS modules

and

consists

elements:

Instruction

buffer

(IB)

Decoder

Microsequencer
Control

store

Condition
Interrupt
File

address

Console

Instruction

code and microbranch logic
and processor register logic
generator

gateway

control

Buffer

The
1instruction
buffer
1is
a
4-longword,
16-byte
memory that
receives
prefetched
VAX
I-stream
data
from
the
CBox.
The
instruction buffer outputs the following macroinstruction data:
Op

code

byte

Current operand specifier
GPR number of the current
Specifier

extension

specifier

bytes

Instruction stream data enters the instruction buffer one longword
at
a
time
from
the
cache data bus.
The data is loaded into a
longword
location
that
is
indicated
by the write address.
An
instruction
buffer
manager controls the read/write operations of
the

instruction

buffer.

Decoder

The
decoder
consists of a 4K x 17-bit writable RAM (DRAM), and a
special address encoder composed of discrete priority encoders and
multiplexers.

The
DRAMs
are
addressed by the current specifier number, the op
code
byte,
and a 2-byte indicator signal.
The specifier number
and
the 2-byte indicator signal are received from the instruction
buffer
manager, and the op code from the instruction buffer.
The
DRAMs perform the following functions:

Supply
address

the
microsequencer
with part of the entry point
for op code and specifier microroutines.

Assist

the

instruction

instruction buffer manager

in controlling

the

buffer.

Indicate
which
the
data
from

EBox
memory
memory
for

data.

T 1-14

data register 1is
those specifiers

to receive
requesting

Microsequencer
The

microsequencer

sources

the
to

Logic

next
be

logic

supply

microword

executed

control

executed.

include:

Current

entry-point

EBox

CBox

The

check

Trapped

microPC

bit

Control
The

16K

from

supplied

selected

the

control

several

The

possible

the

possible

address

microwords

vector

microPC

silo

return

address

from

address

stored

microstack

microPC

bits,

resides

store.

break

latches.and

Store

microcode

with

vector

microtrap

wide

one
RAMs

microaddress

microtrap

Machine

Console

which
store

microword

Decoder

Microsubroutine

presented

determines

the

control

1-bit

means

Approximate

store

writable
the

RAM

gateway

usage

16K

The

Amount

Use

15K

CPU

and

Macrobranch

are

loaded

during

from

system

of:

Control
User-Written

Code

143

RAMs

controller

consists

Condition

RAMs.

the

set

console

initialization.

Code

Logic

The
condition
code
and
macrobranch
logic
are responsible for
maintaining
the
condition
code
bits
of
the
processor status
longword,
and
seven
CPU
state
bits.
Raw condition codes from
various
EBox operations are used in
the generation of microbranch
conditions
based
on the size of the data bein
g processed and the
raw

condition

the

current

instruction,
The

CPU

state

stored

The

raw

condition

the

code

new

codes

bits

longword

bits

can

create

condition

compared

with

macrobranch

bits.

are microprogramming aids that
provide firmware
method of controlling microcod
e flow.
The bits can
set or cleared in a microroutine
and then tested as conditions
later routines.

Wwriters
be

codes.

longword

with

1-15

Interrupt and Processor Logic

The interrupt and processor logic contains the priority interrupt
hardware and the four internal processor registers (IPRs). The
interrupt portion of the logic monitors all hardware interrupts,

encodes the level of the highest pending request, and compares it
to the current priority level. If the encoded level is higher than
the current level, the interrupt logic will request an interrupt
-

by asserting an interrupt pending line.

The internal processor registers control and supply data to the
interrupt logic, microsequencer, and the memory management logic
in

the

CBox.

File Address

Generator

The file address generator performs the following functions:

for the EBox register file and slow

Supplies

addressing

Stores

general-purpose

Records

changes

data

file

numbers

referenced by

general—-purpose

registers in

operand specifiers

made

auto-increment/decrement operations

Gateway Control Logic

The gateway control (GWC) controls the data paths between the CPU
The GWC controls the loading of the
interface.
and the console
register, and the loading of the
ch
control store RAMs and micromat
decoder and cache control RAMs.

1.6.2.2 Execution Box =-- The execution box shown in Figure 1-7
processes data received from the CBox and the IBox, and returns
the processed data along with the virtual address to the CBox.
Functions performed by the EBox include:

CPU

required

)

All

)

Maintaining

arithmetic,

logical,

and

bit shift

operations.

the

program

counter

and

general-purpose

registers.

Maintaining the internal processor registers.

Controlling

data

Providing

condition

clock

module

transfers

between the CBox,

IBox, and

registers.

code

microsequencer.

T 1-14

information

the

1IBox

VA BUS
FROM CBOX

_»| PROGRAM
COUNTER

—»

|¢———

> gl(_)CIJr\/j\_I]'ING
ARITHMETIC
AND
LOGIC
UNIT

SHIFTER

CACHE DATA BUS’ ———

FROM CBOX

FILE

SlE

—P

BYPASS BUS
FROM CBOX

P MULTIPLIER

gfigg;w

DATA BUS

FROM IBOX
SLOW DATA

> FiLE

< %ngox

—»

LATCH |q—

—]

’

BYPASS BUS
SCLD-81

Figure

The

EBox

1-7

Simplified

consists

file

Slow

data

Program

Main

the

Block

Diagram

following

major

Floating-point

CBox

major

elements

modules
decoder

(SLCO

(DEC)

CPU

Execution

Box

elements:

logic

arithmetic

and

logic

support

unit

logic

Multiplier

slice

the

file

counter

Shifter

The

that

make

and

SLCl),

the

module.

1-17

EBox

shifter

are

located

(SHR),

and

the

part

data

the

File

file consists of 32 high-speed 36-bit registers (32
register
The
The 32 registers in the register
bits of data and 4 parity bits).
file

include:

15 general-purpose registers

temporary

registers

(GPR)

(TEMPS)

microcode

scratchpad

registers

memory

data

registers

(MDR)

store data received from

cache

the

File

Slow Data

slow data file has a timing restraint that

The

file

the

inhibits access to

for three cycles following a write operation.

The file

1low data rate 36-bit registers (32 bits of data
256
of
consists
and 4 parity bits). Slow data file registers consist of:
internal processor registers

VAX

Data

)

Diagnostic

Program

path

(IPR)

constants

test

patterns

Counter

maintains the VAX PC, PC incrementer,
(PC)
counter
program
The
backup and trap PCs, and the virtual address file (VAF) register.

VAX

PC supplies the CBox translation buffer with the virtual
VAX
The
op code, operand, and operand specifier of the
each
tor
address
instruction

stream.

Incrementer

the PC by adding an increment value
updates
incrementer
PC
The
The increment
equal to the size of I-stream data being processed.
value (0-6) is supplied by the PC increment generator in the IBox.

Backup

The
backup PC saves macroinstruction op codes and restores the PC
Saving the op
1in a macroexception.
results
instruction
the
if
allows a service routine to examine the op code of a failing
code
instruction

and

service

the

fault.
I

1-18%

Trap

The

trap

provides

microtrap

Virtual
A

maintains

microtrap

copy

each

causes

Main Arithmetic
The

the

virtual

address

file.

This

and

Logic

and

following

recent
the

active

activity,
PC

the

and
time

wunit

and

functions:

Addition

)

Logical

and

OR,

and

Auxiliary

functions

Multiplexing

Supplying

memory

virtual

)

Supplying

Routing

)

Providing

binary

subtraction

AND,

the

CBox

used

data

32-bit

coded

(carries

exclusive

performed

data

1is

saved

the

backup

the

Unit

1logic

floating-point,

sent

copy

microtrap.

arithmetic

integer,

of
with

File

address

history
routines

occurs.

Address

virtual

service

adder

decimal

that

data

processes

perform

propagated)

include:

received
and

address

the

data

the

and

from

carry

and

condition

the

CBox

shift

slice
the

translation

codes

modules

CBox

the

buffer

module
IBox

Shifter
The

shifter

handles

data

is
in

64-bit

all

formats

operation:
®

Integer

Floating-point

Binary

coded

input,

32-bit

output

following

one

the

shift

matrix

three

that

modes

decimal

Floating-Point
This

support
floating-point

are:

shift

system
data.

count

processes
Included

ALU,

priority

the
the

sign and exponent fields of
floating-point support logic

encoder,

I 1-19

and

exponent

ALU.

Multiplier

The multiplier is a 64-bit multiplier that enhances the speed of
integer and floating-point multiplication. Characteristics of the

multiplier

are:

Incorporates

Prcduces

Incorporates

an "eight bit at a time" multiply algorithm

that generates eight result bits per cycle.
results for

generates

integer data.

"one

the

bit

<correct

two's

complement

at a time" division algorithm

that generates l-quotient bits per cycle.

1.6.2.3 Cache Box -- The cache box (CBox) shown in Figure 1-8, is
byte physical indexed, direct mapped, and buffered
64K
a
write-through cache that speeds address translations and provides
a communication path for the CPU to the NMI.

The

CBox consists of a translation buffer, NMI interface, and the

64K byte data store cache.

Translation Buffer

The translation buffer (TB) is a 1K direct mapped cache of virtual

The TB consists of a tag store
to physical address translations.
1is organized into 512 per process
The TB
and a data store.
translations and 512 system region translations.

The tag store uses a portion of the virtual address (VA) to access
a RAM array and compares the contents of the RAM with the
remaining VA bits. When the comparison results are equal and the
TB valid bit is set, the address has "HIT" and the contents of the
Data Store will be valid for that address.

The data store uses the page frame number (PFN) of the page table
If the tag store comparison
(PTE) for the virtual address.
entry
in a TB HIT, the PFN concatenated with VA<8:0> is used as
results
the physical

address.

Cache

cache
The
frequently

1is a hardware mechanism used to provide fast access to
1If
used data, and is addressed by a physical address.

the data is
1in the cache,
required read data is available
If the data is
extracted and a memory request is not required.
a memory request is initiated to
not available 1in the cache,
is passed on to the
The data from memory
the data.
provide
requester and is also placed in the cache for subsequent use.
1 1-2@

NMI

Interface

The

NMI

for
When

interface
communication
a

cache

provides
with

read

MISSES

missed

address

memory.

This

allows

free

process

arrives

from

build

the

interface

into

assumes

the

data

cache

| .

the

When

translation

CPU

the

control

requests
the

and data path
interconnect (NMI).
the interface uses the

transaction

buffer

requested
of

control

memory

comparison),
command/address

and

until
data

cache

the

send
to

requested

arrives

and

cache

loads

from
the

to
be

data

memory ,
new

data

BUFFER
TO/FROM
NMi

TAN
tm\a

STORE

VIRTUAL

with

8800

store.

TRANSLATION

[ i

CPU

VAX

(no

additional

memory.

the

NMI

PHYSICAL

ADDRESS

INTERFACE

DATA

STORE

I DATA

ADDRESS

’——P

CACHE

CACHE DATA

STORE

MICROWORD FROM IBOX

TO
IBOX

AND EBOX

CACHE DATA BUS
SCLD-82

1.6.3
The

Figure

1-8

Clock

Module

clock

module

generate,

all

control,

system

between

the

Section

the

clock

modules.

console
of

logic.

this

Simplified

contains
and

all

the

manual

rest
for

Diagram

distribute

Included

and

Block

the

the
the

detailed

1-21

VAX

the

hardware

VAX

clock

the

8800

module

8800

CBox

necessary

system

timing

interface

the

system.

information

Refer

pertaining

EXT CLK

REF CLK

PHASE

GENERATOR

OSCILLATOR

w—»

A
»

»
LB

CLOCK

W—TM
pIsTRIBUTION |——
——FA—3 LZLI
FB—» S
o
X

GATING

CLOCK

CONTROL
LOGIC

| NMI HARBINGER

NMI SLOW CLOCK ENABLE
L

MICROMATCH

STEP B CLOCK

CONSOLE

CONSOLE DATA
CLOCK PERIOD

P
INTERVAL SYNC ———
SCLD-83

Figure 1-9

The basic
oscillator

Simplified Block Diagram of the Clock Module

the clock module is a 250 kHz
reference signal used by the phase

timing source of
that generates a

generator to produce two nonoverlapping clock phases.

The phase generator output consists of Phase A, B, and W. The W
phase signal is similar to the A phase, but longer in duration.
The A and B clock phases are gated in the distribution logic by
signals from the clock control logic to produce gated system
clocks that can be started, stopped, or burst by the clock control
'

logic.

The distribution logic also produces free-running (ungated) clocks
Table 1-7 lists and
that are used in the VAX 8800 system.
identifies

clock

the

clock

signals

generated

module.
T

1-22

and distributed by the

Table

Clock

Signal

Function

Main

and

CLK

1-7

system

1/0

System

clocks

adapters

CLK

Free-running

operations
FA

and

The

CLK

console

operator

clock

registers

system

clocks

for

1.6.4
The

VAX

interface

clocks

stopped.

controls

within

the

console.

the

clock

console

Clock

control

Clock

period

Burst

count

and

the

clocks

Start

and

stop

the

Burst

the

clocks

step
a

Change

the

clock

Disable

clock
the

(MBox)

8800

memory

eight

MAR4

4-Mbyte

are

fourth

used

The

memory

the

for

CPU when

with

interface.

control
provides

registers

and

console

logic

console

the

sequence

generation
the

write

used

the.

status

are:

allows

the

system

operator

to:

clocks
on

micromatch

period

stalls

NMI

Memory

module

RAM

clocks

stop

clock

Control

(MCL)

used

the

status

Enable

logic
A

SLC1.

monitor

clock

means

operator.

control

Single

the

and

synchronize

wused

Also

and

modules

and

adapters

control

commands

logic

located

I/O

CPU

SLCO

clocks

operations.

Timeout
Console

system

synchronize

subsystem

Three

modules

and

are

the

System

CPU

Free-running

sequence

controller

initiated

information

used

operations.
W

Clocks

timeout

system

located

memory

clock

(MBox)
slot

array

(NMI

slow

consists

the

boards.

clock

memory

cardcage,

The

enable)

array

control

and

one to
boards are

1in slots 22 through 29 of the
cardcage. Figure 1-10 shows
simplified block diagram of the
MBox with one MARA4 array board
.
Refer
to
Section
8
of
this
manual for additional informatio
n
pertaining to the MBox.
a

1-23

MEMORY CONTROL LOGIC (MCL)

TO/FROM

.
—

LEFT CPU

8
18]

23
o

TO/FROM

&
CONSGLE _ ¥ <z
INTERFACE

DATA

i= |——»{gARRAY

Z l¢——|INTERFACE[—®
=

!—*

[

BANK 0 [—
|

BANK 1

L—»{Bank 3 |

|
POWER

=o |

P <

CONTROL
LOGIC

POWER
CONTROL

SYSTEM

MAR4 ARRAY BOARD
SCLD-84

Figure

Simplified Block Diagram of

1-10

the MBox

-- The MCL provides control and a
Logic
Control
Memory
1.6.4.1
and the memory array
NMI
the
between
interface
communications

boards.

The single MCL has the capability to control up to eight

boards,
array
simultaneously.

arrays
three
on
operations
menitor
<can
and
1-8 describes the command operations that
Table
array.

the MCL performs on the MAR4

Table

1-8

MCL Command Operations

Operation

Description

Longword Write

Writes

Longword Read

Reads a data longword and seven ECC check bits

Octaword Read

Reads four data longwords and associated check

bits

data

into one of

from one of

bits

longword

the MAR4

from a MAR4
1 1-24

and seven ECC check

array banks.

array.

MAR4

selection

and

enabling

The

MCL

backup

performs

power

1.6.4.2

from

MAR4

four

1-Mbyte

each

MAR4.
and

transfer

and

accomplished
memory

refresh

and

system

during

power

Array

banks

array

seven

banks

error

interfacing

VAX

data

transfers

8800

between

the

code

board

Mbytes

bit

(ECC)

line

board.
battery

interruptions.

memory

means

select
array

distributes

array

contain

board

appropriate

MAR4

total

correction

accomplished

has

three

and

)

VAX

8800

VAX

bus

Visibility
VAX

8800

data

between

The

VAX

memory

for

wide

check

control

the

consists

VAX

common
bits.

logic

8800

I/0
Data

and

the

array

bus

external

perform

error

1.6.5.1

VAX

1-11

interconnect

major

system

path

for

bus

8800

major
Primary

(VAXBI)

point

provides
1latch

1is

backplane

and

the

between

during

Memory

the

components

console

contents.

allows

bus

that

transfer

system

VAX

I/O

bus

that

8800

system

and

Interconnect

backplane
the

VAX

CPU
CPU

Memory

system

NMI

VAXBI

operator
The

with

diagnostic

VBus

also

used

The

NMI

shown

initialization.

synchronous

Secondary
to

(NMI)

components

adapters.

checks

units.

interconnect

internal

Figure

provide

bus

connected

wvisibility

access

that

interconnect

connection

device

following

memory

the

level buses
information.

interconnect

the

bus

provides

system

status

interconnects

The

the

System Buses

The

for

.
(NAB)

1.6.5

periodic

array

asserting

1logic

Memory

boards

control
the

The

longword
array

is
the

controller

adapters

(NBI)

1-25

(NMI)

bus

8800

that

interconnects

system:

the

<<:

MEMORY

SECONDARY
CPU
NEXUS

PRIMARY

CPU
NEXUS

NEXUS

VAX 8800 MEMORY INTERCONNECT i:}

170
ADAPTER
NEXUS

(NBI

110
ADAPTER
NEXUS

(NBT

NOTE:

NEXUS = HARDWARE
CONNECTION
SCLD-85

Figure

1-11

Ssimplified

Block

Diagram

the VAX 8800 Memory

Interconnect

Table 1-9 1lists the primary functions performed by the NMI, nand2
provides a brief description of each of them. Refer to Sectio
of this manual for detailed information concerning the NMI,

Table

Function

Write

1-9

NMI

Function

Descriptions

Description

Transactions

Supports

longword,

quadword,

longword,

octaword,

write.
Read

Transactions

Supports

read.
Memory

Read/Write

Operations

I/0

Write

Read/

Operations

Allows

the

memory

through

Allows

the

CPUs

the

devices

Handling

Transmits

the

CPU

interrupt

memory

and

I/0

CPU.
System

Provides

Synchronization

System

Allows

Initialization
Power-Fail

NMI).

Warning

the

Provides

ACLO

access

transactions.

I/O

I/0

adapters,

bus

and

nexus

connected

initialize

DCLO

all

signals

VAX

(VAXBI)

through
Each

Interconnect

I/0

bus

for VAX

provides

(VAXBI)

8800

the

NBI

system

Bus

the

NMI
to VAXBI
(NBI)
adapter can interface up
for

when

two

maximum
NBI

adapters

adapter

four
are

and
two

VAX

VAXBIs

installed.

1-27

The

VAX

connected
shown

all

interface

the

Figure

system

1-12.
interconnects and
be connected to the

bus
to

bus

nexus.

1.6.5.2

and

read/write

requests generated by
adapters to the primary

clocks to all
blocks
physically

console

hexword

access

system

(hardware
the

memory,

octaword

and

adapters

through

transactions.

Interrupt

I/0

read/write

primary

registers

I1/0

and
bus

and

PRIMARY

SECONDARY

VAX 8800 MEMORY INTERCONNECT (NMI)
v

[7NMLT -VAXB! ADAPTER (NB!U

<:l

i:>

VAXBI BUS

<‘r

MEMORY

CONTROLLER

CPU

VAXBI BUS

I >

NMI-TO-VAXBI ADAPTER (NBI)

VAXBI BUS
\/

VAXBI BUS

i>>
SCLD-86

Figure 1-12

The

VAXBI

Simplified Diagram of VAX Bus Interconnect
(Maximum Configuration)

1is a 32 bit wide synchronous bus that interconnects up

of O
to 16 VAXBI interfaces (VAXBI nodes) with logical addresses
plug
ID
an
by
ined
determ
is
node
a
of
through 15. The address
node.
inserted on the backplane. Address 0 is reserved for the NBI

The remaining nodes
adapters interfacing

description

consist of I/0 device cont o1
the system's 1/0 devices to the VAXBI.
L

T o am

1Sl >,

ailu

of some of the different types of bus adapters can be

found in Section 1.6.6.

Table

1-10 identifies and describes the basic functions performed

by the VAX bus

interconnect.

Table

1-10

VAXBI

Function

Description

Memory

Allows

Read/Write

Operations

DMA

the

I/0

Write

Read/

Allows

Operations

Interrupt

Handling

transfers

VAXBI

through

bus

the

System

read/write

through

devices

bus

originated

the

I/0

primary

transactions

directed

Provides

NBI

generated

connected

the

node S

Visibility
bus

The

VBus

data

allows
the

the

system

VBus

include:

console

8800

and

clocks

CPU

system
are

console

Verifying

system
®

and

console

located

access

during
CPU

that

loading
controls

the

clock

registers

Select

The

and

during

Major

module

CPUs

the

Step

the

Send

serial

Halt

the

store

during

and

the

reads

perform

VBus

clocks
VBus

input
that

slow

lines.

latched

used

performed

the

and

entered

revision

errors

the

VBus

1-29

the

during

not

occur

initialization.

means

two

The

registers

VBus

control

functions:

channel
operate

when

execution

commands

interface.

following

addresses

operation

system

VBus

console
the

all

execution

VBus

during

parity

and

debug.

microcode

module's

bus

internally

The

line,

control

the

installation

control

nodes

power-fail

signals

functions

response

system

all

NBI.

two

read

initialization.

the

INTR

node.

reset

VAXBI

visibility

lines

operator

bus

DCLO

modules

stopped.

VAXBI

clocks

the

initialization.

Ensuring

when

and

data

Monitoring
the state
microdiagnostics
or

the

The

sixteen

the

VAX

microdiagnostics

(VBus)

the
NBI

assert

generated

Bus

consisting

VAXBI

through

the

nodes.

1.6.5.3

the

transactions

CPU

simulated

ACLO

memory

VAXRI.

device

I/0

NBI.

devices

the

Provides

access

read/write

the

I1/0

main

transactions.

I/0

sequence

speed

8800

CPU

initialize

Warning

VAX

Allows

Power-Fail

between

the

primary

interrupt

System

and

registers

Enables

Synchronization

Descriptions

VBus
CPU

address

modules

shift

VAX Bus Interconnect and I/0 Adapters

1.6.6

8800 memory interconnect-to-VAXBI interconnect (NBI)
provide a connection point for the VAX 8800 CPUs to the
adapters
Additional optional adapters can be connected to the
backplane.
as shown in Figure 1-13 to allow for connection of the
backplane

The

VAX

CPUs to other I/O devices. Table 1-11 lists and identifies some of
the optional adapters that can be connected to the VAXBI.
Table 1-11

Optional VAX Bus Interconnect Adapters

Adapter

Function

DWBUA-CA

VAXBI

Bus—-to-UNIBUS

expansion

cabinet

controller.

and

uses

Requires

existing

UNIBUS

adapters.

KDB50-BA

VAXBI Bus-to-Storage Interconnect disk controller.

BSA

VAXBI Bus-to-Storage Interconnect disk and magnetic

DEBNT-AA

VAXBI BUS-to-Network Interconnect controller.

CIBCA-AA

VAXBI Bus—-to-Computer Interconnect controller.

CIBCI-CA

VAXBI Bus-to-Computer Interconnect controller.

KLESI-AA

VAXBI Bus-to-Native tape controller.

DMB32-LF

VAXBI Bus-to-Native asynchronous comm. controller.

DRB32-AA

VAXBI Bus-to-Multifunction controller.

tape

controller.

Uses

Ethernet.

SECONDARY
CPU

MEMORY
CONTROLLER

MEMORY INTERCONNECT (NMI)

' >

PRIMARY
CPU

[NMI-TO-VAXBI ADAPTER (NBI)J

rNMI-TO-VAXBI ADAPTER (NBIfl

/Y A

VAXBI INTERCONNECT

: :’

VAXBI INTERCONNECT

DWBUA-CA

VAXBI/

DEBNT-AA

CIBCA-AA

CONTROLLER

VAXBI/NI

38 'nquLé% LLER

BSA

VAXBI/CI

VAXBI/SI

DRB32-AA

KPBS0-BA

CONTROLLER

VAXBUMUX

CONTROLLER

CONTROLLE!

KLESI-AA

DMB32-LF

CONTROLLER

VAXBI/COMM

VAXBI/LESI

<STORAGE INTERCONNEC?
\

)

DISK/TAPE

Y
UNIBUS CONNECT

{

T WOX INTERCONNECT

STORAGE INTERCONNECT

COMPUTER INTERCONNECT
DISKS

< TOW END STORAGE >
\4

NETWORK INTERCONNEC">

ETHERNET

< COMMUNICATIONS INTERCONNECT >
SCLD

Figure

1-13

1I/0

Interconnect

I 1-31

and

Adapters

The NMI-to-VAXBI (NBI) adapter shown in Figure 1-14 consists of an
and one or two NBIB
interfaces to the NMI,
NBIA module that
The NBIB modules interface to the VAXBI through the use
modules.
of a VAXBI

The

NBIA

module

interface chip

module

contains

(BIIC).

the NMI nexus registers, and the NBIB

contains

the VAXBI connecting registers.

Tables 1-12 and

1-13 list and identify the registers on each module.

———
NBI

\/
NBIA MODULE

NBIB

VAXBI 0 ) €

VAXBI 1 )
SCLD-88

Figure

1-14

NMI-to-VAXBI Adapter

1-32

Table
Address

1-12

NBIA

Registers

2X080000

Control/Status

2X080004

(CSRO)

Control/Status

(CSR1)

2X080008

VAXBI

2X08000cC

Stop

VAXBI

2X080010

Stop Register

BR4

Vector

2X080014

Offset

(BR4VR)

BR5

Vector

2X080018

Offset

BR6

Vector

(BR5VR)

Offset

2X08001cC
X

NBIA

Table
Address

1-13

(BI1I)

(BR6VR)

BR7 Vector Offset

(BIOI)

(BR7VR)

NBIB

Registers

2X000000

Device

2X000004

VAXBI

Type
Control/Status

2X000008

Bus

2X00000cC

Error

2X000010

Interrupt

Error

Interrupt

Control

Destination

2X000014

Interrupt

2X000018

2X00001cC

Interrupt

Destination

Interrupt

Source

2X000020

Starting

2X000024

Ending

2X000028

BCI

Mask

Address

Control

2X00002cC

Write

2X000040

Status

User

Interrupt

NBIA

0/BI

NBIA

0/BI

NBIA

1/BI

NBIA

1/BI

1.6.7
The

Power
power

operate

8800

the

for

developed

System Complex
complex
provides

CPUs,

the

diagram

manual

for

memory,

Three
the

wusing

within

system

system.

source

Control

VAX

the

phase

system.

the

8800

the

utility

The

the

VAX

voltages

bus

and

necessary

interconnect

power

required

power modules

used
and

voltage

cabinet.

power

detailed

and

as
dc

the

regulators

Section

information

the

complex.

1-33

the

power

are

located

simplified

to
VAX

primary

voltages

Figure 1-15 shows
system complex. Refer to
concerning

block

this

system

/\
3-PHASE

208/240 —pf
)

i
]

MODULE
POWER

SUPPLIES

L
» 1/0

- CPU

0 —>
|

{——3 CPU

———» MEM

3-PHASE

876

> gg%

CONTROLLER

»| CONDITIONER <fi|

[ap]

120/240

pl BACKUP

}

UNIT

lSENSE
>

CONSOLE
PARAMETERS

ENVIRONMENTAL
MONITORING

POWER-FAIL WARNING <
SCLD-89

Figure

1-15

Simplified Block

Diagram of

the

Power System Complex

1.6.7.1
876 Power Controller -- The 876 controller is the main ac
input module for the power system. Power is received from the main
circuit
breaker and distributed to the other system componcnts by
the
876
controller.
The
controller
distributes the following
power:

Unit

Power

NBox

Single

BBU
Console

Unswitched
Unswitched

single phase
single phase

Alr

Unswitched

three

Mover

and

three

phase

1.6.7.2
NBox
Port
Conditioner
-The
NBox is a multifunction
power
assembly containing five modules. Table 1-14 identifies the
modules

and

describes

the

function

1 1-34

each module.

Table

Module
H7170

1-14

NBRox

Modules

Function
X

Convert

three-phase

output.

H7170

Same

interface

Module

Control
Power

Logic

(ILM)

and

Startup

H7170

Provide

logic

signal

and

other

BBU

operation.

Convert

(CSP)

Box

(NBT)

Translator

CPU

Module
group

cardcage

regulated

the

Supplies:

EMM

Converts

and

logic

initialization.

1.6.7.3
are

the

CPU,

Power
of

the

power

memory,

Supplies

power

and

interface

System

single-phase

voltages.

for
New

power

power
+12,

The

module

modules

and

backplane

main

CPU

supplies

cabinet.

that

extender

provide

modules.

the

logic
and

startup

and

power
The

supplies

located

MPS

vdc

EMM

Controls

-12,

ILM.
for

300

between

components.

+5,

signals

into

level
+10.5

(MPS)

above

the

contains

the

operating

power

for

1.6.7.4
Environmental
Monitoring
Module
-The
environmental
monitoring
module
(EMM)
is
g
microprocessor-based
unit
that
monitors
the
power
and
environmental conditions
within the VAX
8800
system.
The EMM responds to cons
ole control commands duri
ng

power-up

backup
the

and

power-down

operations.

EMM.

The

sequencing,

console

initialization,

controls

the

power

and

battery

system

through

1.6.7.5
Battery
Backup
Unit
-The
battery backup unit (BBU)
gives the power system a
method of providing protecti
on voltage to
the
main CPU memory during an
ac power failure.
The BBU contains
a

48-Vdc

rechargeable
battery
pack,
charging
circuit,
and a
converter.
The
converter
provides 300 Vdc during
the
mode.

dc-to-dc

backup

1-35

CHAPTER
SYSTEM

2.1

GENERAL

This

chapter

and

the

describes
by

console

the

SYSTEM
console

2.2.1

Software

console

between

the

controls

VAX

2.2.2

Hardware
of

status,

and

the

operator

and

located

within

the

software

provide

the

console.

streams

console

and

allows
locations in

main

Figure

shows

2-1

system

and
by

identified

the

chapter

displays,

is
is

and

the

software

and

control

the

communications

using

encoded

VAX

system

data

and

console.

access

simplified
Table

diagram.

the

block

involved

console.

block

several

directly

console
memory.

software
the

this

means

hardware

system

means

access

cannot

accomplished

support

CSM

8800

code, called the console
console
to
access
portions

console

VAX

complex
mixture
8800 system.

the

hardware

data

resident

the

hardware,

VAX microcode

Control

registers

the
VAX

Included

commands,

is
a
the VAX

function

and

the

CONTROL

that

primary

between

how

software.

console

subsystem

hardware

The

and

logfile.

2.2
The

interaction

subsystem,

overview

system

the

console

controlled

CONTROL

2-1

in
2-1

microcode

the

VAX

diagram

the

body
CPU

hardware

internal

CPU

of
control

describes

command,
paths

(CSM),

8800

media

allows

that

link.

registers

some

of
the

the

and

VAX

the

VAX

the
The

and

key

8800

components

CONSOLE

RTI
CONTROL

lAjr;\fo NG

RAREING

CNTRL.TSK

Ry
e

ATI

DRIVER

DATA

RT.TSK

CNTRL/

gg)FI‘RM—_::—b

_TERMINAL__|
TRAFFIC

ADDR

STATUS

VAX

BIDI

—

RXDB

SEQ

TXDB

INTERFACE

|—»

REGS

CLK CNTL
LOADING

WCs

ccs

CSM

CODE

SLCO
SLCA

INT CLK

CNTRL
SCLD-80

Figure 2-1

VAX 3800 System Hardware and Software Control
Components

Table

2-1

Hardware

and

Component

Function

Console

Handles

Software

input

Responds

from

VAX

Driver

system

and

EMM

Commands

and

issues

all

S$QIO

transfers

and

the

and

encoded

Handles

and

asynchronous

input

EMM.

VAX/WCS

resident microcode
functions requested by the

The

CSM

receives

parameters

control

from

RTI

Hardware

The

RTI

module

contains

(PPI)

that

system

through

Data

across

the

VAX

system

from

the

VAX

system

that

Interface

bus

RTI

The

the

with

between

route,

the

The

console

the

PPI

data
VAX

the

data

bus

and

receive

transfer
8800

link

system

and

interface

VAX

8800

ports.

from

PPI

serial

the
the

line

resides

the

ports

console

port

hardware

control

the

for

the

VAX

the

data

between

clock

data

stream

system.

console

the

necessary

communicates

internal

2-3

the

EMM.

and

interface

bus

bidirectional
Transmit

and

console

computer,

module.

the

contains

generated

console

with

and

interrupt

console

the

interface

and

receive,

clock

~contains

commands

peripheral

the

software.

under

addressable

connecting

console

module

three

executes

console

PRO-38N

communicates

communication
Console

the

transferred
a

interface
The

data

for

programmable

for

system

commands.

RTI

VAX

driver

result

the

and

encoded

the

requests

commands

EMM.

appropriate

$QI0s

console,

EMM.

and

with

RSX-based

service

between

Generates

Console Support
Microcode (CSM)

VAX

actions.

Services

Description

the

control

driver.
RTI

Component

side

VAX

means
and

of
the

side.

buffers

provide

the

bus

the

data

PPI

buses.

and

CONSOLE SOFTWARE COMPONENTS

2.3

components:

consists

software

console

The

1.
2.

Control program
File transfer program

Real-time interface driver

the

following

four

major

Logical block server program

Control Program

2.3.1

The control program
and
program
both
micromonitor,

and remote access.

1is

program

control

The

1is the main console program and implements
EMM support,
logfiles,
mode,
console

composed
(ASTs),

interruptable

code

and

which are software interrupt

system traps
and is interrupted
routines. The main body of code executes,
are executed when
nes
routi
AST
te.
periodically, when ASTs execu
asynchronous

some type of I/0 or other system event occurs.

The

control

program

normally

has a QIO outstanding to the EMM,

When operating in
remote port (when enabled), and local termienal.
represent entire
QIOs
remot
and
the console mode, the 1local
sent single
lines. During program mode operation, the QIOsin repre
different modes
can be
characters. The 1local and remote ports
terminal driver
le
conso
The
usly.
taneo
or the same mode simul
~U and RUBOUT during
echoes and implements special characters like drive
r performs the
the console mode, and the VAX terminal
identical function during program mode.

The

control

¢ ¢ 00 0O

directives:

2.3.1.1

program

makes

full use of the following RSX system

Set

Clear

Wait for event flag
Timed requests
1
.
&+
24
NITO
wait
with
O/IC

0IO without wait

OIO with AST completion routines
0IO without AST completion routines

Special Control Program Features

CPU Designation

ry" and
Console software maintains mappings from the LOGICAL "prima
CPUs.
"
"right
and
"left"
al
physic
"secondary" CPUs, to the
than
rather
CPU
ary
second
or
y
primar
Start-up procedures refer to
left or

right.

1 2-4

Automatic
If

Remapping

the

CPU

designated

program

can

remap

start-up

Disable
A

procedures

Secondary

secondary

control

CPU

1is

not

The

When

CPU

Current

The

allow

and

1left

CURRENTPRIMARY

the

VAX

from

come

and

8800

system

independent
creates

independently

from

console.

The

control
by

variable

STREAM

fourth

creates

commands

temporary

database

the

one

designated

either

primary,

program

will

BOOT

will

console
to

force

assert

SECONDARY

ignored
timeout

the

waiting

operator

primary.

designate

The

keywords

the

SET

CPU

specify

the

logical

—-—

both

the

The

the

results

control

local

additional
secondary

primary.

entered

additional

that

which

copy

copied

the

back.

2-5

each

used

executing

interpreted

remote

command
A

global

use.

prevent

The

prior

local

the

requirement

stream.

database

commands.

database

not

and

rebooting

independent

for

console

can

the

three

database

'local'

either

the

listens
ports

requirement

the

copy

remote

can

and

CPU.

program

and

CPU

The

commands

command,

simultaneous

database

command
is

set

will

CPU

separate

the

temporary

implements
a

CPU

the

apply

incorrect

command.

the

selects

copy

corruption

the

operational.

the

control

primary

Streams

having

set

from

allows

CPU

stream

program

streams

control
and

automatically

primary

from

that

activity

another

console

not

the

The

streams.
is

microsequencer.

requirement

command
system

the

also

operator

Command

This

CPU

set,

NEXTPRIMARY

commands

'remote’

the
CPU

properly.

NMI

the

right

accepts

dual-CPU

Operate

command

Multiple

times.

physical

Primary

2.3.1.2
all

available,

up.

and

not

other

CPU

can

VMS

disabled.

NEXTPRIMARY

the

other

the

commands

Primary

bit

disabled

secondary

SET

either

the

disable

CPU

is
the

secondary

disabled

and

secondary

the

state

the

miscellaneous

miscellaneous
for

continue

operation.

INIT

CPU

when

secondary

CPU

"primary"

CPU.

secondary

single

will

operational,

primary

command

"primary"

disabled

program

the

control

database
program

processing

each

successfully,

the

2.3.2

File

The

transfer

file

the

Transfer

console

disk

transfer

transferring

functions

process

without

record

delete

Logical

Block

block

the

operating

system

The

VAX

VMB.

VMB

1is

8800
A

logical

block

console

the

file
to

transfer

control

and

program.

all

disk

I/O

write,

and

VAX.
is

used

read,

Program

(LBS)

with

RTI

file

logical

supports

and

the

mechanism

writes

console

arbitrarily

request

the

(CSAl:

the

driver

the

VAX

large

the

virtual

read

system

and

floppies

disk.

floppy,
block

write

read

which

media.

virtual

Winchester

block

into

LBS

operation.

logical

When

the

write

block

two

CSA2:).

operating

system

device

driver

through

program.

logical

sub-drivers

serial

1line

2.4

CONSOLE
CSM

console

command

cannot

directly

for

PPI

SUPPORT
special

and

between

and

file

communications

sub-driver

DEPOSIT,

ACKNOWLEDGE

RTI

with

hardware
programs.

the

PPI

translates

1into

commands

MICROCODE (CSM)
group of microcoded

processing

the

transfer

the
for

routines

port

console

appropriate
the

PPI.

that

control

inside the VAX system where the console
hardware. The CSM is used to access the

registers

and

main

2.4.1

Console

Support

consists

used

The

EXAMINE

WRITE,

link

server,

the

CPU

describes

block

access

internal

CSM

READ,

1is

are

wunit.

such

sequence

Interface Driver
program provides the

control,

commands,

UNIX

VAX

the

Real-Time

RTI

Separate

and

the

accesses

the

(RMS)

program

writing

server

communicates

2.3.4

The

between

VAX

console

from

provides

allows

devices

and

Server

floppy

logical

and

RXDB/TXDB

The

the

(VMS/UNIXTM) reads

virtual

the

functions

to/from

server

console

reading

converts

and

files

system

files

The

allows

management

logical

The

data

drive.

files.

2.3.3

LBS

disk

interference

The

transfers

Winchester

This

The

Program

program

each

trademark

Microcode

four

the

memory.

major

Structure

sections

sections.

AT&T.

2-6

code.

Table

2-2

lists

Table

2-2

Major

Section

Sections

Wait

Loop

Polls

RXCS

and

data.
Points

specific
Command

Exit

into

CSM

Many

Tests

Routines

order

utilize

WCS

microcode

resident
is

CSM

always

Data

overlaid

the

numerous

vroutines

transfers

are

bytes

responsible

guidelines

describe

bytes

long.

Responses

are

bytes

long.

2.4.3

CSM

console-to-VAX
transmitted

other

console
and

code

space

and

PROBEW

registers.

space.

This

information.

Most

execute

for

building

transfers,

During

VAX-to-console

transmitted

transfers,

successfully.

protocol

"packets"

during

data

the

most

significant

the

least

significant

first.

byte

(ISP)

the

The

are

the

PROBER,

of USER WCS code
troubleshooting.

Commands

During

(resident

top

and

)

byte

MFPR,

access

one

transfers:

°®

manner,

processing

byte

console.

following

transcends

and

routine.

Transfers/Protocol

require

executive

initialization

transmitted

set

commands,

correct

locations

CSM

The

instruction

CSM

efficient
two

routines

for

send

CSM

routines

and

utilize

used

states.

MTPR,

code

2.4.2

for

Cleans
up
VAX/CONSOLE

space

console-to-VAX

microaddresses.

bits

allow

Nonresident

The

for

microcode

Data

loaded

instructions

RXDB

dispatches

resides

nonresident).

and

entry-point

routines

Dispatcher

support

The

Code

Description

Executive

Entry

CSM

first.

Console

can

exXecution.

Support Microcode Entry Poin
ts
entered by both hardware and ISP

Table

2-3

lists

the

entry

2-7

points.

(instruction)

code

Table 2-3

Console Support Microcode Entry Points

Type of Entry

Entry Point

Hardware

Microtraps

Special Address

Startup Constrained Addresses

MTPR/MFPR Instructions
VAX Communications

Software
(ISP Shared)

2.5

PROBER/PROBEW Instructions

OPERATIONAL MODES

The console operates in one of two modes as shown in Figure 2-2.
Refer to Section 3 (Console) of the manual for additional
information concerning modes of operation and machine states.

VAX 8800

CONSOLE CPU

HALTED

ChmEONSOLE

RUNNING

PROGRAM
CONSOLE

SCLD-91

Figure 2-2
2.5.1

Console Operational Modes

Console Mode

The console mode can be in effect with the VAX 8800 system halted
or running. While the VAX system is halted, the entire range of
console commands is available to the operator.

Typing a CTRL/P while the VAX system is running causes the console
to enter the console mode (leaving the VAX system running). Since
the VAX system is running, the available commands during the
console mode are

limited.

2-8

2.5.2

Program Mode

Program

mode

this

allows

mode,

interrupt-driven.

2.6

the

OPERATOR/CONSOLE

The

VAX

that

8800

must

system

conditions,

and

time

turned

are

console.

The

console

operating

independent

2.6.1

and

Console

states

scoftware,

and

Which

system

Bits
system

wused

console

Left

Right

Common

hardware

)

Command

streams

are

and

functions

the

two

states.

console

implement
The

separate
The

are

complex
and

are

"state"

are

commands.

normal

valid

any

the

VAX

and

CPUs

state

maintained
state

that

can

one

CPU

restrictions

following

system

abnormal

console

state

information

CPU

examples

Table

2-4

the

state

Bit

?
enabled

Backup

AUTOBOOT

Clock

port

Battery

CPU

During

system

CPU

provides

power

terminal.

VAX

bits.

Examples
Type

Remote

EMM

VAKX

wunder

State
VAX

constitute

CPU.

VAX

2-4

CPUs

off.

other

the

operated

combination

are

available:

Table

console

State

the

and

transitions

the

act

with

dependent

VAX

any

INTERACTION

and

1initialized,

particular

The

console

communications

unit

enabled

Common

?
working

Common
?

Common

running

halted

Terminal

Common

?
Console

Program

Left/Right
mode

Per

command

stream

Command Validity -- Each console command calls a utility
that specifies which state bits must be TRUE and which

2.6.1.1
routine

must be FALSE for a specific command. Unspecified bits are not
If the specified bits are not in the correct states, the
checked.
command will not be executed and an error message will be printed.

Some bits require access to the hardware each time it is
The clock may stop if the microPC matches
(Example:
referenced.
was set. It must be checked each time the
icromatch
stop-on-m
and
clock bit

referenced.)

Each console command can specify whether the CPU-specific bits to
1in the CPU for which the command was issued, the
be checked are
other CPU, or both CPUs. This causes some commands to be dependent
on

the

both CPUs.

states of

2.6.1.2 Saving Console State -— Important console state variables
are preserved during console power failures. These include:
settings

Default

anything

that can be set with SET

DEFAULT.

Logfile

Console

Clock

Reboot-Primary

Shadow copies of clock board registers.

TODR,

2.6.2

The

block.

control

)

"state

bits",

which

include

the

AUTO

BOOT/RESTART/POWERON switches.

VAX

rate.

date,

ID.

and time TODR was written.

Console Commands

8800

Console

Command

Language

(CCL)

is the intertace

between the operator and the control and monitoring capabilities
2-5
the VAX 8800 console and micromonitor subsystems. Table
of
Console
the
to
Refer
commands.
8800
VAX
of
overview
provides an
User's Guide for a complete description of each command.

I 2-19

Table

2-5

Console

Command

Description

Opens

specified

within
BOOT

CLEAR

Command

the

Executes

file

Overview

and

processes

the

records

file

Device

nameBOO.CMD;

1if

specified,

executes

DEFBOO.CMD

ACCUMULATOR

Resets

settings

made

SOMM

commands

the

SET

device

and

PROBE

TOMM

CONTINUE

Starts

execution

DEPOSIT/EXAMINE

Deposit/Examine

DISABLE/ENABLE

Establishes

Auto

address/data
parameters:

Restart/Boot/Poweron

User

Printer,

Console

monitoring

EXIT

Terminates

FIND

Enables

64Kb

console

memory

Restart

CPU

current

console

Odometer,

HALT

program

search:

good

memory

Parameter

halts

Block

the

macroinstruction

boundary
HELP

Prints

Enables

INITIALIZE

Sets

LINK

Creates

LOAD

Loads

MICROSTEP

Bursts

Steps

PERFORM

help

the

specified

topic

conditional

execution

CPUs

defined

temporary

the
the

clock
VAX
the

through

2-11

command

file

store
cycles
(n)

temporary

LINK

(n)

commands

state

indirect

memory/control

Executes

with

for

macroinstructions
command

file

created

Table

2-5

Console Command Overview

(Cont)

Command

Description

POWER

Turns power ON/OFF/STANDBY

PROBE

ORs VBus bit into Accumulator

REPEAT

Causes

command

Senses

revisions of

SENSE

line

executed

continuously

REVISION

specified component

SET

Sets Clocks, CPU Primary, Defaults

SHOW

Shows

START

Starts execution of macro/microcode

TEST

Starts customer diagnostics or micromonitor

UNJAM

Asserts/Deasserts

VERIFY

Verifies

EMM Power Margins, Relocation
Values for EXAM/DEP, SOMM,
TOMM, Verify/Nonverify

Defaults,

and

Value/Status:

Logfile,

EMM,

lo memory

Accumulator,

Revision History

CPU,

UNJAM,

reloads NBI with hi

module

placement,

limits

EMM,

revision

history

2.6.2.1 Executing Console Commands —-- All commands that read or
write the VAX 8800 system hardware are implemented by means of
to the RTI driver program. Commands that require the power,
0I0Os
or CPU to be in a specific state, generate a state check
clocks,
prior to executing the command.

Commands from the console are passed to the VAX system as 8 bits
the RTI driver. The command data is transferred by
of data by
the console computer and the
connecting
bus
the PPI
means of
console

interface on the clock module.

The command data being transferred contains encoded identification
and data fields describing the type, purpose, and destination of
The console interface places the command data into
the command.
receive data buffer (RXDB) so that it can be transferred to
the
the VAX CPU decoder module by means of the bidirectional data bus
connecting the console interface and the VAX 8800 CPU.

2-12

2.6.3
The

Console/Operator

display

for

terminal.

Only

shown

the

system

testing

observed

Status

longer

view

other

console

2.6.3.1
at
over

the
the

same

remote

the

logfile
of

Display

8800

system

VAX

8800

the
screen

the micromonitor
simultaneously.

displayed
time

during

the

normal

mode,

bottom

the

scrolling

when

During

Remote

Display
the

time.

local

The

port

monitoring

well

character

and

local

remote

the

Operation

enabled,

flow

the

can

all

local

during

operations.

I 2-13

from

screen
is

can

monitor

remote

CPUs

operation.

screen

terminals

operator

enabling

console

dual

output

the

output.

both

PRO-38N

system's

during

remote

When

example

one

Local

operations,

VAX

display

may

the

remote

both

CPUs

allow

for

During
be

the

remote

operational
input/output
function.

activity

Figure

simultaneous

During

responding

monitoring

screen.

display
will

appears

2-3

local

shows

and

remote

RIGHT
CcPU

CSM DATA

LEFT
CPU
LEFT
LOG

OPA1:

DATA LOST

FILE

OPAD:

[ZaeloN]

CHARS.

CONTROL

TO
iD

I
vi-¢

ECHOED

OPA2:

OPAO:

RIGHT

CONSOLE

COMMANDS

|VMS
|BITS
OPA2

REMOTE SCREEN
(PROGRAM MODE)

LOCAL SCREEN
(CONSOLE

LOCAL

—

REMOTE

MODE)

KEYBOARD

E—

KEYBOARD

LOCAL SCREEN SET TO LEFT CPU
LOCAL TERMINAL IN CONSOLE MODE
LOCAL TERMINAL SET TO OPAO:

REMOTE USER 1S

ENABLED

REMOTE PORT SET TO RIGHT CPU
REMOTE TERMINAL IN PROGRAM MODE
RIGHT TERMINAL SET TO OPA2:
SCLD-92

2.6.3.2

Console

describes

local

the

and

Command

console

remote

display

Table

Language

command

2-6

Console

Description

>>>

Console

MIC>

Micromonitor
Link

Command

Level

2.6.4

System
console

reviewing

Mode

All

mode

the

Input

back

2.6.4.1

that

from

the

Displaying

provision

for

display.
appended

(Reference

Data
to

the

2.6.4.2

on
the

the

SET

will

eliminate

VAX,

but

LINK

not

the

during

the

all

TERMINAL

OPAO:

OPAl:

filling

the

and

CPU.

2-6
the

PERFORM

and

file

storing

720

screen

during

data

during

the

program

and

display
not

logfile

the

Integrity

for

prior

with

the

mode

are

allows

with

pages

logfile will
the

Logical

normal

logfile.

program

unwanted

console
saved

command

with

terminal

(30

logfile.

changing

and

logfile

lines

logfile

displayed

placed

2-15

the

LOGFILE
of

the

SHOW

and

command

VAX,

down,

1logical

Fach

the

saved

The

saving

from

contents

Terminals/Logfile

standard

purpose

each

display

output

made

Logfile
at

the

capable

are

received
of

for

the

entries

the

end

and

the

operations,

Prompts

line.

scrolling

Logical

buffer
per

appears

1look

viewing.

OPAOQ:

logfiles

well

Console

operator

Table

Input

pertaining

circular

data

logfile.

two

output

characters

operations,

echoed

the

a
80

Language

appear

Logfile

maintains

console

consists
screens)

that

Input

Commands)

The

Prompts

prompts

screens.

Prompt

<LK

Display

language

mode

data.

the
the

present

terminal

system
Entering

operations

2.6.4.3 Saving the Logfile -- Logfile data is preserved if either
or the console power fails.
stops,
program
control
the
Nonvolatile data is stored in the first block of the logfile:
Logfile control block

Micromatch address
Verify switch

Examine/Deposit defaults
Default

radix

Internal trace bits

State

bits

Clock

rate

Regulator margin mask
Reboot primary identity
Memory

limits

Shadow copies of clock board registers

TODR written by the VAX system

P/0S date and time when TODR written
Micromonitor state variables

UP/DOWN SEQUENCING

POWERparagraphs provide a brief overview of the
ing
follow
The
e and
power-up/down and restart functions. Refer to the Consol
concer
ation
Power Sections of the manual for detailed inform on and ning
boot
recovery, and initializati
sequencing,
power—on
2.7

processes.

2.7.1

Power On

The power-on sequence can be initiated by either a VAX 8800d system
power-fail recovery, Or by entering the POWER ON comman at the
console terminal.

The

console

software

determines

whether

the

recovery

was

console-only failure by examining the VAX power status by means of
the environmental monitoring module in the power system.

to
power-up procedure requires that the consocle send commands 2-7
Table
ce.
the EMM to apply system power in a particular seguen s are turned
shows the sequence in which the power supply module

The
on.

2-16

Table
Order

2-7

Module

Power

Supply

Turn-On

Sequenc

Power Application

+300

Memory/Battery

+/-

12,

-5.2,

+5,

-2

VAXBI

+/-

12,

=-5.2,

+5,

-5.2

VAXBI

-2

2.7.2

Power

failure

recognition

power

system will

result

the

system

assert

the

Fail

means

ACLO

the
and

the

console
DCLO

environmental

interface.

2.7.3

backup

The

wunit

powerdown
console

and

initiate

and

initiated

operator

software

informs

the

enabled.

module

VAX

8800

directed

the

power-fail

checks

operator

command

the

status

the

BBU

not

the

battery

present

backup

power is not available, the software asks the
operator
should continue or abort the powerdown process.
If the BBU
enabled
or
the
operator
wishes
to continue without backup

power,

the

EMM

initiate

power

2.7.4

Warm

EMM

the

Powerdown

intentional

console.

The

signals,

sequence.

monitoring

interrupt

restart

turning
restart

directed

assert

the

ACLO

the

shutdown.

and

DCLO

signals

and

sequence

for

Restart
uses

the

system

parameter

same

block

procedures

power.

must

power-on

Memory

must

available

for

2-17

be
a

backed

warm

restart.

and

SYSTEM

3.1

INTRODUCTION

This

chapter

memory

contains

addressing,

exceptions.

Refer

information.

3.2

MICROCODE

The

control

16K

words

store

the

bits.

from

brief

the

The

usage

is:

CPU

°®

control

User-written code --

Microcode

3.2.1.1

Functionality

Horizontal

field

(Some
more

fields
than

3.2.1.2

one

sections

CPU

during

system

microcode,

interrupts

and

this

for

manual

consists

the

of
control

initialization.

The

Characteristics

have

bits

are grouped into fields with
each
controlling a specific CPU
element.
vertical functionality in that
they control

feeding

and

element.)

Operation

Pipelined

-More
than
Pipelining
allows

time.

simultaneously.

3.2.1.3

one
the

microword
CPU

is active at any given
perform multiple operations

Structure

Segmented

and

enhances

CS0

the

and

15K

Microword

directly

resides in the IBox and
microcode is loaded into

console

store

3.2.1

overview
operations,

individual

microcode

143

RAMs

control

read/write

detailed

CS1l,

CHAPTER 3
OPERATION

RAM

Each

Cs2.

the

microword

Dividing

pipelining

divided

the

into

microword

three

into

process.

segments,

three

CSO,

segments

Segment

Resides
<47:0>.

the

Provides

SEQ

module

and

early

control

3-1

consists

IBox

and

EBox

microword
operations.

bits

CS1

RAM

Segment

Resides

the

WCS

module

and

consists of microword bits

the

WCS

module

and

consists of microword bits

<95:48>. Provides mid/late control - EBox operations.

CS2

RAM

Segment

Resides

<142:96>. Provides late control - EBox and CBox operations.

3.2.2

The

Microcode Control

module

sequencer

operation

the

controls

(SEQ)

microcode. The primary duties performed by the SEQ module are:

the

appropriate

microPC

1input

for the control

Select

Monitor hardware and software interrupt requests.

Provide CSO segment microcode data to the kernel.

[

Monitor microbranch and microtrap conditions.

°®

Provide a data path between the CPU and the console.

store

address

the

latches.

The functional areas of

the sequencer are:

INPR

CCBR

GWYC
UTRP
UBRS

3.2.2.1

Interrupt and Processor Register (INPR)
prioritizes

Receives

and

Provides

interrupt

hardware interrupts (software

interrupts are handled by microcode).

conditions

the

microtrap

vectors

microsequencer

processing.

3-2

and

logic

microbranch

for interrupt

3.2.2.2
o

Condition
Monitors

Code
EBox

Provides

Contains

)

Controls

and
)

3.2.2.3
®

the

STATE

Gateway

Control

console

Microtrap

(UTRP)

Receives

and

for

Provides

SILO

Slices

instruction

during

macrobranch

branching.

the

Monitors

microvectors

)

Supplies

micromachine

during

all

the

data

macro-

microbranch

save

and

uPC

machine

during

transfers.

and

slice

microtrap

logic.

mux.
state

during

conditions
from

the

microPC

from

the

microtrap
the

CPU

traps.

kernel.

logic.

control

sfiore

microstack

RAM

(UBRS)

microbranch

data

and

receives

RETURN

address

data.

Pipelining

process

more
Figure

pipelining
(processing
multiple
microwords
allows the VAX 8800 syst
em to utilize the hardware
efficient manner, and incr
ease the performance of
the

simultaneously)
a

microcode

errors

control

Monitors

3.2.3

flushing

addressing

The

during

bits.

prioritizes

microstack

Provides

vectors

requests.

parity

Controls

the

access

Microbranch

buffer

microcode

Monitors

trap

bits.

(GWYC)

console

and

latches.

flags

microvectors

)

and

Provides

3.2.2.5

CPU.

<N,

(CCBR)

condition

instruction

conditions.
®

PSI,

Contains

3.2.2.4

CBox

macrotrap.

Controls

and

Branch

macrobranch

exXecution.
o

and

3-1

shows

simplified

drawing

3-3

VAX

8800

pipelining.

DEC
1ST

|DEC
2ND

T—l

0 _f

HALF |[HALF |UP

TIME STATES

TB CACHE

|uPC

MICROWORD 1

|[CS2
CSt1
LOOK [LOOK

DEC

|UP

|DEC

|CSo0

|GEN

|[FILE |MAIN ALU | FILE WRT

OPS

HST [|2ND [LOOK|NEXT |READ
|uPC
HALF |HALF{UP

MICROWORD 2

TB CACHE

CS1
|CS2
LOOK |LOOK

uUP

upP

DEC |DEC |CSO |GEN |FILE | MAIN ALU | FILE WRT
OPS
1ST |2ND |LOOK|NEXT|READ
TB CACHE
|uPC
HALF |HALF |UP

MICROWORD| 3

{CS2
CS1
LOOK | LOOK

MICROWORD 4

jUP

|DEC

|CSO0

|GEN

|FILE|MAIN ALU | FILE WRT

HALF|HALF| UP

|uPC

TB CACHE

DEC

|[1ST

|2ND | LOOK|NEXT|READ

OPS

CS1
|CS2
LOOK|{LOOK
|UP
UP

Figure 3-1

3.2.4

Microtraps

are

hardware

Simplified Pipelining

conditions

that

prevent

the

current

microword from executing properly. When a microtrap occurs, the
hardware forces the control store address to a fixed location {the
location 1is dependent on the type of trap) overriding the address
that would have been selected. The forced address is the starting
location of the trap handler microcode routine.

are used extensively by the memory management system,
Microtraps
.system faults such as parity and bus errors.
resolving
for
and

Table

3-1

1lists the various types of microtraps for the VAX 8800

system.

3-4

Table

Microtrap

3-1

VAX

8800

System Microtraps

Condition

Priority

Microbreak
Machine

Check

Parity

Tag

Not

Error

Parity

Floating-Point
Integer

Page

ADD

Error,

Multiply

Bit

Cross

Unaligned
Integer

Page Cross
Conditional

Overflow

Lowest

microtrap

otherwise

blocked

the

cause

microPC

the

3.2.5

the

trap

the.

silo

blocked

allow

cache

microwords

of
the state-saving
microinstructions.

Microaddresses
of

any
by

most

blocked

queued

occurs,

performed

until

performs

has

been

and

writes

the

cleared.,

restoration

microinstructions
for

the

microinstructions.

possibility

that

would

pipeline

The
for

are
of

are

hardware
return

saved
a

branch

a
in

Micromatch

method

micromatch.

halting

[The

with

the

The

micromatch

specified

when

micromatch

Stop

Match

Trap

Match

console

Match
state
restarts

micromachine

matches

breakpoint

the

hardware

function
a

3.2.5.1
Stop
on
micromatch,
the
from

Branch

Machine Check

When

One

Round

Overflow

Unaligned

one

Error,

Violation

Modify

the

Operand

Round

Miss

Access

Floating-Point

Error

Used

Reserved

Highest

provides
occurs:

-of
the

through

every microPC
microaddress.
]

When

for

one

the

(program

two

use

counter)

actions

the clocks are stopped
during a
machine is frozen unti
l a command
system clocks.

the

Match -- Following a microPC match, the
on
3.2.5.2 Trap
intended
micromachine traps to a specified location to perform the
at the
ued
contin
be
can
flow
Ooriginal microcode
operation.
completion of the trap routine.

3.3

MEMORY ADDRESSING AND READ/WRITE OPERATIONS

3.3.1

Virtual Addresses

s for each
processor generates a 32-bit virtual addres
The
es, the
execut
s
proces
the
instruction and operand 1in memory. As
s.
system translates each virtual address to a physical addres

Virtual address space
byte location in the
512-byte units,

1is a 32-bit unsigned integer specifying a
physical address space and is arranged in

called pages.

mapping the
A memory management system provides the mechanism for ble
physical
availa
the
active part of the virtual address space to
separate
en
betwe
ction
address space and provides page prote
ical
-phys
al-to
virtu
the
processes. The operating system controls
the
of
parts
ive
1inact
address mapping tables and places the
.
virtual address space on the external storage media

memory mapping is disabled, virtual addresses are translated

when

to physical addresses by ignoring bits 30 and 31.

virtual
The translation buffer in the CBox is wused tos speed
ations
transl
addres
ated
address translations by holding calcul
1in
exists
s
addres
l
virtua
a
for future use. If the translation for
s.
addres
al
physic
the
for
the translation buffer, the data is used
a microtrap
If the desired address translation does not exist, ation.
When
transl
s
addres
occurs and a trap routine performs the
ated
transl
the
s,
proces
the trap routine completes the translation
address is written into the translation buffer.

yout -- Virtual address space is divided into two equal
Per-process address space

System address

Per-process
system and

space

space 1is distinct for each process running on the
system space is shared by all processes. Figure 3-2

shows the layout for virtual address space.

3.3.1.2
shown

Format

in Figure 3-3.

The

format for the 32-bit virtual address 1is

I 3-6

00000000

PO (PROGRAM REGION)
LENGTH REGISTER = POLR

PER/PROCESS
SPACE

3FFFFFFF

(CONTROL REGION)
LENGTH REGISTER = PiLR

40000000

7FFFFFFF

S (SYSTEM REGION)
LENGTH REGISTER = SLR

80000000

SYSTEM
SPACE

BFFFFFFF

C0000000
RESERVED REGION

FFFFFFFF
SCLD-94

Figure

3-2

Virtual

Address

3-7

Space

Layout

3t 30

BYTE NUMBER

VPN <31:9>

BIT 31

1
0

VPN (VIRTUAL PAGE NUMBER) -- SPECIFIES THE VIRTUAL PAGE TO BE REFERENCED
SYSTEM SPACE ADDRESS
PER-PROCESS SPACE ADDRESS

BIT 30 PER-PROCESS SPACE
1

= CONTROL REGION

0 = PROGRAM REGION

BYTE NUMBER -- SPECIFIES THE BYTE ADDRESS WITHIN THE PAGE

Figure

3-3

Virtual Address Format

3.3.2

Physical

address

space.

Memory

IFFFFFFF.
the

I/0

physical

Addresses

space
space

space

begins

address

consists
starts

space

two

parts,

address

20000000
3FFFFFFF.

memory

zero

and

continues

Figure

3-4

space.

space

and

end

shows

the

layout

PRIMARY MEMORY

1FFFFFFF

(512 MB)

20000000

NBI

>R— 32MBYTES

<+ 32 MBYTES

SPACE

22000000

SELECT =

(VAXBI #0)

23FFFFFF

(VAXB! #1)

/0O SELECT =

24000000

NBI #1

<+—

32 MBYTES

26000000

NBI

28000000

RESERVED

|
i

(352

MB)

MEMORY

E000000

o —
S

<«

(VAXBI #1)

27FFFFFF

3DFFFFFF

CONTROLLER

MBYTES

1/0 SELECT =

|
T
(

32 MBYTES
SCLD-96

Figure 3-4

Physical Address Space Layout

3-9

the

00000000

21FFFFFF

I/0

HEX BYTE ADDRESS

and

continues

Address Translation

3.3.3

The process of translating a virtual address to a physical address

is controlled by setting the memory mapping enable (MME) bit in
the MAPEN (MAP ENABLE) internal processor register. Figure 3-5

shows the bit configuration of the MAP enable register.

MME

MBZ <31:1>
1

MME (MEMORY MAP ENABLE)

MEMORY MANAGEMENT ENABLED
MEMORY MANAGEMENT DISABLED
SCLD-97

Figure 3-5

MAP Enable Register Bit Configuration

3.3.3.1 Page Table Entry —-- The CPU uses a page table entry (PTE)
to translate virtual addresses to physical addresses. Figure 3-6
shows the format and bit configuration of the PTE. Table 3-2
describes the function and purpose of the PTE bits.

3-9 show simplified diagrams of the
through
3-7
Figures
space and process space regions O
system
for
translation process

Q
(=]

]

N
Q

N
n

n
w

n
L

]
[¢]

N
[$4]

PROT

(&)
[ ]

N
~

and

PFN

SCLD-98

Figure 3-6

Page Table Entry Bit Configuration

1 3-10

Table

3-2

Page

Bit

Symbol

Function

Valid

Table

Entry

Bit

Determines

validity

PFN

field.

reserved

PROT

Protection

Always

Field

hardware.

Modify

Bit

When

bit

Zero

Bit

OWN

Owner

Bits

1is

the
been

Reserved

for

the

not

PFN

bit

20-0

PFN

Software
Page

Bits

Frame

Number

Reserved

the

bit

the

has

been

set,

the

page
bit is

modified.

DIGITAL

software.

for

DIGITAL

access

mode

Upper

address

3-11

for

DIGITAL

bits
of

the

base

are

CPU

software.
for

the

owner.

22-21

and

valid.

fields

the

zero.

Reserved

the

software.

set,

whether
1If

and

Used

have

be
24-23

DIGITAL

may

page

Valid,

the

valid.

modified.

for

indicates

Description

Comments

When

30-27

Bit

software.
physical
of

the

page.

Must

Use
page

‘

3130 29

VIRTUAL

SYSTEM

ADDRESS

09 08
BYTE

|0
:

EXTRACT AND CHECK LENGTH

02 |01 00

0
ADD

SYS

PHYSICAL BASE ADDRESS OF SYSTEM PAGE TABLE

%ggh

YIELDS

PHYSICAL ADDRESS OF PAGE TABLE ENTRY
FETCH

PAGE
TABLE

ENTRY

21 20

31 30

PAGE FRAME NUMBER

CHECK ACCESS

09 |08

PHYSICAL ADDFESS
SCLD-99

Figure 3-7

System Space Virtual-to-Physical Address Translation

PROCESS

3130 29

SPACE
VIRTUAL
ADDRESS

olo

BYTE

(PROGRAM)

EXTRACT AND CHECK LENGTH

|22

|01

0
0

ADD
PO
BASE
REG

SYS VIRTUAL

eT-¢ 1

BASE ADDRESS OF PO

PAGE TABLE

YIELDS

SYS VIRTUAL

ADDRESS OF PAGE TABLE

ENTRY

FETCH BY SYSTEM SPACE TRANSLATION
ALGORITHM.
INCLUDES LENGTH AND KERNEL MODE ACCESS
CHECK.
31

PTE

PAGE FRAME NUMBER
CHECK AGCCESS

(ACCESS CHECK IN

PHYSICAL

ADDRESS

CURRENT MODE)

|29

|08

SCLD-101

Figure

3- 8

Process

Space

(PO

Region)

Translation

Virtual-to-Physical

Address

PR
FROCESS

3130 29

ADDRESS

VIRTUAL

(CONTROL)

09 08
BYTE
EXTRACT AND CHECK LENGTH

02 |01 00

23 |22

0
ADD

SYS VIRTUAL BASE ADDRESS OF P1 PAGE TABLE

gége
Pi-¢

YIELDS

SYS VIRTUAL ADDRESS OF PAGE TABLE

FETCH BY SYSTEM SPACE TRANSLATION ALGORITHM.
INCLUDES LENGTH AND KERNEL MODE ACCESS CHECK.

PTE

21 20

31 30

PAGE FRAME NUMBER

(ACCESS CHECK IN CURRENT MODE)

CHECK ACCESS

09 |08

31 30 |29
PHYSICAL ADDRESS

0
SCLD-106

" Figure 3-9

Process Space (Pl Region) Virtual—-to-Physical
Address

Translation

3.3.4
The

Cache
CBox

Operation

shown

Figure

3-10

consists

three

major

functional

areas:

Translation

Cache

NMI

3.3.4.1

buffer
wuse.

(TB)

Interface

Translation

hardware
future

Buffer

wused

calculated

also

The

the

physical

the

translation

page.

hold

contains

Table

3-3

translation
address

control

lists

buffer

information

and

describes

> »

CACHE

PHYSICAL ADDRESS

» BUFFER

1is

translations

a
for

concerning

the

buffer.

TRANSLATION

XB%B%@%

The

fields

P CACHE
DATA

>o INTERFACE
NMI
- NMI

MICROWORD
FROM IBOX

SCLD-102

Figure
Table

3-3

3-10

CBox

Functional

Translation

Buffer

Field

Description

Used

Tag

virtual
TB

Data

the

Components
Description

matching

process

contains

determine

translation

for

address.

Consists

the

table

page

the

page

frame

number

entry

(PTE)

for

(PFN)

the

virtual

address.
Protection

Protection

information

from

entry

the

Compared

current

processor

capabilities
M
TB

Bit
Valid

Modify
Bit

page.

bit

the

page.

from

the

page

Indicates

whether

wvalid

bit

page

the

mode

3-15

not

table

the

entry

same

entry.

table

with

determine

table

the

page

the

access

entry.
is

valid.

the

The

valid

Hit

A translation buffer hit indicates that the currently accessed TB
entry 1is the correct translation for the virtual address. A TB

by accessing the TB with virtual address bi‘ts

determined

1is

hit

<31, 17:9> and matching the TB tag field with virtual address bits
If the addresses match and the entry is valid, the
<30:18>.
translation is for the virtual address, and protection and modify

bit checks are

initiated.

If there are no protection or Mbit problems, then it is a TB hit
and the PFN concatenated with VA<8:0> is used as the physical
address.

TB Miss

miss

when

occurs

there

address to a physical address.

is no translation of the virtual

3.3.4.2 Cache =-- The cache is a read allocate only device, and
cache locations are updated only if a previous cache hit existed.
Write misses do not affect the cache. In order for the cache to
process either reads or writes in one cycle and in any order, the
cache uses a delay write algorithm that delays the update until
the

next write

cycle.

The cache is divided into three sections:
Tag

Cache Tag Valids

Cache

Data

Cache

The
the

Store

Cache

Tag

Store

cache tag store holds the cache tags that are compared with
incoming PA<K28:16> as part of the effort to determine a cache

hit.

Cache Tags Valid

Each tag entry has four associated valid bits that are used to
The wvalid bits are used in the
indicate an octaword valid.

matching process to determine a cache hit.

Cache

Data

The

cache

tag.

1If

from

the

Store
data
the

IBox

store

contains

the

access

results

cache

data

3.3.4.3

NMI

Interface

path

that

memory

The

allows

interconnect.

interface

uses

command/address
NMI.

The

CPU

transaction

When

the

cache,

requests

valids

missed

read

means

the

while

arrives,

the

data

with

the

backplane

the

CBox

VAX

bus

are

8800

that

any

device

must

NMI

requesting

request

device

write

the

transaction

initiating
transfers

the

transactions
bus

and

the

data

during

may
the

address
the

provides

with

read

the
the

control
VAX

miss,

read

either

8800

the

NMI

build

memory

means

are

free

process

memory

cache

the

NMI

interface

handles

the

NMI

interface

assumes

control

the

tag

cache

store,

and

validates

address.

generated
memory

the

of
the

’

interconnect,

device

the

read

assertion

and

which

CPUs,

by
I/0

the

NMI

devices

synchronous

memory,

and

1I/0

NMI,

the

information

the

asserted
involved

some

the

asserting

for

the

The

and

one

device

then

complete

the

arbitrates

for

containing

transfers

third

for

data.

device

transfer

the

read

transactions.

transaction,

transaction.

3-17

the

and

write

The

bus

read

command/address

3-11.

the

bus

hexword

read/write

the

transfers

the

signal

transfer.

followed

cycle.

read

granted

enable

command/address.

during
in

bus

for

requesting

transfer

data

the

bus

one

multiple

arbitrates
for

only

bus

arbitrates

device

second

required

Figure

The

requires

transfers

Dbeginning

line.

require

First,

the

shown

and

transactions

transaction

command/address

transaction.

address

transferred

memory

cycle.

data

passed

Operations
device can perform a transfer
request and be granted use of

arbitration

data

Read/Write

Before

Read

and

the

into

new

being

communicate

sends

cache

data

cache

interconnects

adapters.

and

buffer

command/address
in

3.3.5

the

interface

Following

hit,

data

NMI.

data

loads

interface
of

the

NMI
to

the

with

Read/write

the

transaction

memory

tag

valid

CPU

translation

additional

cache

corresponding

cache

EBox.

and

data

store

data
a

NMI

the

cycle

address

30-bit

NMI

identify

selection

(1Y)

MEMORY ADDRESS

1/0 REGISTER ADDRESS

28 27 26

1/0 ADAPTER 0 REGISTER SELECT BITS

0010
25

—

24
VAXBI 0 REGISTER SELECT BITS

WHEN 1/0
ADAPTER

—

IS NBI
(NB1 0)

VAXB! 1 REGISTER SELECT BITS

)

28 27 26 25
1/O ADAPTER 1 REGISTER SELECT BITS

010 |1

—

24
VAXBI 0 REGISTER SELECT BITS

WHEN 1/0

\ ADAPTER

—

VAXB! 1 REGISTER SELECT BITS

28 27 26
11111

24
MEMORY CONTROLLER CSR SELECT BITS

1
—_—

SCLD-103

Figure

3-11

NMI Address Selection

I 3-18

3.3.6

Device Address

Address

bit

address.

I/O

further

<29>

define

appropriate

VAXBI

select

an
a

Transaction
are

bits

for

the

1).

Bits

controller

Significant
depends

Figure

shows

3-12

READ LONGWORD (TO

(NBI

the

then

NBI

bit

<25>

<25:29>

must

bits

then

memory

<28:26>
is

being

selects

set

the

one

bits

CSR.

Address
on

address

address,

addressed,

significant,

different

specified

1I/0

adapter

1is

memory

3.3.6.1

1is

1I/0

NBI

address

performed.

which

addressed.
order

Selection

determines

the

Bits
type

—-of

significant

transactions.

Which

transaction
and

being

nonsignificant

WORD-ORIENTED DEVICE)

313029

SIGNIFICANT ADDRESS BITS

READ LONGWORD, READ OCTAWORD, READ HEXWORD, WRITE LONGWORD
313029

0100

SIGNIFICANT ADDRESS BITS

WRITE QUADWORD
313029

0302 0100

SIGNIFICANT ADDRESS BITS

XXX

WRITE OCTAWORD
313029

0403020100

X|X

NOTE:

SIGNIFICANT ADDRESS BITS

X INDICATES THAT THE BIT
BY THE RESPONDING

NOT SIGNIFICANT AND IS

X|X|XX

IGNORED

DEVICE.
SCLD-104

Figure

3-12

NMI

Address

I 3-19

Bit

Significance

3.4

INTERRUPTS

3.4.1
The

EXCEPTIONS

Servicing

two

the

AND

VAX

8800

processor

NMI
nexus
exclusively

3.4.1.1

CPUs
or

(I/0
by the

NMI

handle

from

devices
CPU that

Interrupt

Enable

control

interrupt

handling

for

other

that

processor.

The

Interrupts

from

NMI

Device

Enable

Interrupts

from

NMI

Device

Enable

Interrupts

from

Main

Memory

two

types

Types

Interrupts

—--

There

locally

the

NBI,

the

I/0

devices

Locally

connected

generated

interrupt

3.4.1.3

interrupts

requests

can

Servicing

CPU

vector
one

Locally

the
the

has

disables

NICTRL

are

NBI.

are

The

and

T/0

the

interrupt

request

generated

BR4

one

level
is

will

level

(Refer

any

and

I/0

service

read

initiated

registers

level.

from

interrupts

offset,

can

1interrupt

can

one

NBI.

Interrupt
wvalue

are

any

firmware

four

generated

vector

offset

in
of

the

performs

registers

the

Table

NBI

interrupt,

system

four

device

3-4.)

control

vector

interrupt

offset

determines

used.
use

devices

page

use

zero

pages

(0)

the

SCB

for

the

through

offset.

3.4.2

Priority

Levels

order

for

the

interrupt

must

have

the

processor

hardware

IPL

assignments.

the

Enable

generated

NBIs.

vector

bits

the
handied

processor

enables

the

Each

from

are

Function

which

from within

Interrupts

Bit

generated

block

(NICTRL)

requests

the

originate

follows:

3.4.1.2

the

that

processor.

and
memory
controller)
is designated as primary.

interrupt
used

interrupts

the

IPL

CPU

respond

interrupt
status

priority
longword

interrupt,

level

(IPL)

(PSL).

the

incoming

greater

Table

3-4

than
lists

Table

Device

3-4

Hardware

Interrupt

Priority

Condition

Interrupt

Unassigned

Power

Fail

CBox

Error

NMI

<1R:18>

(NBI

#0),

(NBI

NMI

#1),

BR7

NMI

BR7

Timer

(NBI

#0),

NMI

(NBI

BR6

#1),

NMI

BR6

I/0 Adapter
I/0 Adapter

(NBI

#0),

(NBI

NMI

BR5

NMI

Memory,

#1),

RRS

BR5

NMI

I/0 Adapter
I/0 Adapter

(NBI

#0),

NMI

(NBI

BR4

#1),

NMI

BR4

Console

Terminal

Console

Receive

Terminal

Transmit

14
14
14
14

Processor

Unassigned

pages

vectors.

and

<13:10>

System Control

system

NMI

devices
devices).

(HEX)

I/0 Adapter
I/0 Adapter

3.4.3

Level

I/0 Adapter
I/0 Adapter

The

Priority

Unassigned

Other

Assignments

Fault

Interval

Level

Block

control

block

vectors

that

are

page

(page

The

first

nexus

vectors,

connected
Table 3-5

for

(SCB)
the

Format

VAX

8800

allocated

and

through
shows the

system
three

reserved

subsequent

pages

can

have

levels

for

are

VAX

3-21

architectural

allocated

the
NBI
adapters
(maximum
configuration of SCB page
0.

interrupt

I/0

Table 3-5

System Control Block Page 0 (000--1FF)

Vector (HEX)

Condition

NOP

Kernel Stack not Valid Abort

Machine Check

Power Fail

10
14

Reserved/Privileged Instruction
Customer Reserved Instruction

Reserved Operating Mode

Reserved Operand

20
24

Access Control Violation Fault
Translation Not Valid

Breakpoint Instruction

Trace Pending

30
34
38
3C

Not Used
Arithmetic
Not Used
Not Used

40
44
48
4C

CHMK
CHME
CHMS
CHMU

50
54
58

Not Used
Not Used
Not Used

60 -- 6C

Not Used

70 -=- 7C

Not Used

80
84
88

Tnterrupt Other Processor
Software Level 1
Software Level 2
Software Level 3

90
94

Software Level 4
Software Level 5

AO
Ad
A8
AC

Software
Software
Software
Software

98
9C

NMI

Fault

Software Level 6
Software Level 7
Level
Level
Level
Level
I

8
9
A
B

3-22

3-5

Table
Vector

System

(HEX)

Control

Block

Software

Level

Software

Level

Software

Level

Software

Level

Interval

Timer

Not

Used

Not

Used

Not

Used

Not

Used

Terminal

Receive

Consoie

Terminal

Transmit

11C

Not

12C

Not

Used

I/0

Adapter

13C

Not

Used

Not

Used

120

140,

144

148

Memory

14C

3.4.3.1
are

Used

I/0 Adapter

130
134

1FF

SCB

Not

for

devices

(NMI)

=--

The

devices
are

Used

Pagination

allocated

Interrupt

pages

classified

3.4.3.2

Offsetable
Devices
interrupts
from
devices
on

3.4.3.3

page

VAXBI

Node

devices

numbered

page

blank

page

with

each

the

SCB

through

either

bus

NMI

offsetable

Offsetable

another

following
the

devices

will

use

the

page

adapters.
directly

that

pass

first

page

connected
Depending

connected

connected.

following

(Cont)

Console

124

for

(000--1FF)

100

Condition

FO,

Page

Connected
be

amount

exist

direct

Devices

located

following

the

may

Direct
will

the

pages

result

connected

devices.

VAXBI.
I

for

required

3-23

Vectors

beginning

the

for

offsetable

page

direct

first

offsetable

starting
One

even

devices.
devices,

even

numbered

will

allocated

SCB

Format

NBI

The

I/0

format

adapter

for

are

the

shown

SCB

vector

offset

Figure

3-13.

(o]
[e]

3.4,3.4

supplied

LEVEL

NM! ADAPTER VECTOR FIELD (SCB PAGE 0)
11

BR LEVEL

OFFSETABLE VECTOR FIELD (31
13

NON 1-31

THE NBI
TO 0

<4—
1

LOADED IN

PAGE PER UNIBUS

ADAPTER DETECTS VAXB!I

EACH BUA IN

UNIBUS VECTOR——»|

OFFSET

FROM THE VAXBI

PAGES AVAILABLE)

ZERO

:UNIBUS

(4]
n

VECTOR <13:9>

NOT EQUAL

AND PASSES THE VECTOR TO THE NMI.

THE SYSTEM MUST HAVE A DIFFERENT VALUE

THE VECTOR OFFSET REGISTER

FOR PROPER

SCB OFFSETTING.

o | o]

PAGE PER VAXBI

VAXBI NODE VECTOR FIELD
08

BR LEVEL

MUST BE ZERO

VAXBI NODE

0 | o

0-3:RSVD

FROM NONOFFSETTABLE

gfgg‘;

VAXBI

> BRe

NODES

7. BR7

THE NBI ADAPTER DETECTS VAXBI VECTOR <13:9> EQUAL TO 0
FROM THE VAXBiI AND ORS THE NBi VOR <13:9> BELOW.

|
13

NBlI

VOR REG.

BR LEVEL

VAXBI

NODE ID

I #0
HARDWARE SET L————| 01 =VAXB
=VAXBI #1
SCLD-105

Figure

3-13

NBI

I/0

Adapter
I

3-24

SCB

Vector

Offset

Format

values

3.4.4
A

Machine

machine

check

internal
The

Check

Exception

exception

error

exception

occurs

and

reports

1is

taken

the

any

time

error

the

processor

VMS

detects

Operating

system.

into the system contro
l block at virtual
Communication betwee
n the VMS system and
the
CPU
microcode
during
machine
check handling is acc
omplished by
means of the machin
e
address

SCBB

+04.

check

3.4.4.1
of

Types

either

the

machine

3-6
8800

the

Exceptions

fault

created

exception

lists

status

examples
system.

abort.

stable.

Machine
Faults

retried

Aborts

faults

and

check

allow

because

not

aborts

allow

that

exceptions

the

consist
instruction that

assumes

for

may

the

state

retry.

Table

occur

the

VAX
|

Table
Type
FAULTS

3-6

Machine

Check

Exception

Examples

Description

Location

Sequencer-to-Console

Data

Parity

Console
Data

Processor

Parity

Decoder
Console

Error

Processor
Error

Memory

Failure

Tag

Memory

Virtual

IBox

RAM-to-Sequencer

Parity

Cache

Processor

Error

Parity

Data

IBox
IBox

CBox

Error

Parity

Buffer

Tag

Translation

Buffer

Data

Read

Input

Error

Translation

Data

Parity

CBox

Parity

Address

Data

Error

CBox

Error
Parity
Parity

CBox
Error
Error

’

CBox
CBox
CBox

3-25

Table 3-6

Machine Check Exception Examples

(Cont)

Location

Type

Description

ABORTS

CS0 Parity Error

IBoOX

CS1 Parity Error

iBox

CS2 Parity Error

IBOX

NMI Sequencer Control Store Parity Error

CBox

Decoder RAM Output Data Parity Error

IBox

FAULTS OR ABORTS DEPENDING ON SOURCE

B - Side Byte 3 Parity Error

EBoxX

A - Side Byte 3 Parity Error

EBox

B - Side Byte 2 Parity Error

EBox

A - Side Byte 2 Parity Error

EBOX

B - Side Byte 1 Parity Error

EBoOX

A - Side Byte 1 Parity Error

EBoOX

B - Side Byte 0 Parity Error

EBoOX

A - Side Byte 0 Parity Error

EBox

I 3-26

CHAPTER
DIAGNOSTIC

4,1

chapter

maintenance
chapter

and

User's

Guide

4,2

contains
aids

power

VAX

wused

description

brief

the

environmental

for

8800

sequence
test

for

the

overview
VAX

module

system.

detailed

8800

information

the

system.

keying

Refer

diagnostics
Included

verification
the

System

concerning

diagnostic

order

top-down

software

the

CPU

cluster

should

run

achieve

test

maximum

sequence

also

verification

exceeds

field

limitations.

run

dual

service

processor

and

this

and

the

Diagnostic

diagnostic

use.

monitor

one

controls

dispatching

The

default

diagnostic

test

single

the

left

mode

and

for

the

and

designed

installation

bottom-up

time.

The

sequence

can

run

microdiagnostic

microdiagnostics

both

the

dual

CPUs.

are

)

The

not

making

this

processor
user

must

configuration
explicitly

select

tested.

CAUTION

cannot

processor

while

running

the

specific

right

Diagnostics

8800

were

isolation.

provided

time

they

bottom-up
Tests

user.

processor

exerciser)

sequence

and

system.

some microdiagnostic tests
processors, and others must be

both

processor

transparent

both

run

provides

the

configuration,

concurrently

sequentially

the

and

coverage

repair

package

verifying

programs

for,

VAX

AIDS

GENERAL

The

MAINTENANCE

INTRODUCTION

This

AND

both

run

operating

one

system

other.

diagnostics

require

(for

example,

processors

NMI

exerciser,

running

cluster

cooperative

macroprograms.

The

flowchart

sequence

for

1in
the

abbreviated,

but

running

gained

Figure
VAX

when

4-1

8800

shows

system.

failure

every

test.

4-1

complete

Normally,

detected,

the

bottom-up
sequence

test

can

information

will

( POWER-ON SYSTEM)
POWERUP VERIFICATION

TEST

CPU CLUSTER MICRO
BOTTOM-UP_SEQ

CHECK OUT CONSOLE SUBSYSTEM,

LOAD PATH TO WCS,

TEST IBOX,

EBOX,

CLOCK,

CBOX,

BVMM
VAXBI FAULT

MBOX

VERIFY CACHE AND INTERLOCKS

DUAL PROCESSOR DIAG

FULLY VERIFY

MEMORY CONTROLLER/
MEMORY ARRAY

MEMORY CONTROLLER

AND MEMORY ARRAYS

v
LOAD CPU WCS AND OTHER
CONTROL STORE FOR VAX ISP
SUPPORT LOAD AND RUN
EVKAA HARDCORE

LOAD DIAG

INSTRUCTION TEST

RUN EVKAB, EVKAC, EVKAD, EVKAA
AND THE VAX 8800 SPECIFIC TEST

SUPRVSR,

RUN CLUSTER MACROS

USE AUTO SIZER,
RUN 1/0 ADAPTER

SET UP FOR MACRODIAGNOSTICS
AND RUN THE VAX HARD CORE

LOAD AND
DIAGNOSTICS

TEST NBI,

ClI

ADAPTER,

MASS

STORAGE CONTROLLER AND DEVICE

iESTS,

COviM

PNV

DEVICE

TESTS,

ETC.

BOOT VMS, RUN VSDP, CVU,
UETP OR CSSE DEFINED
SYSTEM TEST

COMPLETE

SCLD-107

Bottom-Up

4-1

)

Figure

BOTTOM-UP
VERIFICATION

Testing

4,3

DIAGNGCSTICS

The

diagnostics

following

major

for

the

VAX

8800

system

are

areas:

Console

divided

into

the

selftest

Microdiagnostics
Macrodiagnostics
Customer
BEach

the

major

sections

4.3.1

Console

The

the

<console

power

VAX

failure

display.

That

Disk

The

the

4.3.2

certain

section

during

console

RTI

(floppy

(real-time

PRO

console

automatically
no

the

when

intervention
console

selftest

the

failed
area
selftest checks:

hardware

P/0OS

will

run

console

the

console

results

the

operator's

(professional

hard)

interface)

Series
error

and

the

manuals

for

additional

analysis.

information

Microdiagnostics
VAX

console

8800
by

micromonitor
The

tests

system)

drives

the

concerning

The

initiated
requires

of
console

The

operating

Refer

and

identification

console

areas

system.

Selftest

selftest
A

diagnostics

diagnostic

8800

applied

operator.

graphic

runnable

specific

microdiagnostics

entering

commands

(MICMON)

mode.

micromonitor

program

the console processor. It
both
console-based
and
microdiagnostics test:
®

The

left

The

clock/console

)

The

NMI

)

Memory

and

right

part

the

used

the

WCS-based

CPUs
interface

I 4-3

are

console

load,

initiated

keyboard

software

control,

from

when

and

the
the

runs

and monitor

microdiagnostics.

The

4.3.2.1
console

-- A subset of console commands requiring
CSM Commands
running
available while
1is
(CSM)
support microcode

diagnostics.

If CSM commands are executed between tests,

the test

Because some CSM code may use functions that
cannot be continued.
some tests may not function correctly
tested,
been
not vyet
have
'
from the console.
commands
CSM
after executing
console CSM commands while running diagnostics, enter
execute
To
the MIC> prompt. This will
following
command
3000
START/C
the
CSM code and turn the
diagnostic
of
start
the
to
UPC
the
force
wvalid:
be
will
commands
ciocks ON. The following
L

DEPOSIT/PHYSICAL/LONG

DEPOSIT/PHYSICAL/BYTE

EXAMINE/PHYSICAL/LONG

EXAMINE/PSL

DEPOSIT/PSL

EXAMINE/SDF

DEPOSIT/SDF

EXAMINE/TEMP

DEPOSIT/TEMP

DEPOSIT/CACHE

running
while
commands
EXAMINE/DEPOSIT/TEMP
the
Executing
different
using
requires
code)
CSM
diagnostic
(using
diagnostics
the TEMP
1lists
4-1
Table
registers.
TEMP
the
for
addresses
register addresses to be used for diagnostic CSM.

Table

4-1

TEMP

with
Temp

Addresses
Diagnostic CSM

Address

TO
T1
T2
T3

T4
MT1
MT2

MT3
MDO
MD1
MD2

MD3
MD4

MD5
ML

MM.MDR

BACK.UP.PC

INVALID

The

microcode
code,

addresses

(Hex)

CSM

use

“ijflUju>\D(x>\lO\U'l4>wN|—‘O

WDR

for

error

using

listed

registers

the

can

EXAMINE/IPR

Table

4-2.

I 4-5

read

when

running

command

with

the

diagnostic

error

Microcode Error Register Addresses

Table 4-2

Address

Format of Returning Register Data

Cache Register

Bits<2-0> = NMI ON, CACHE ON, and

Cache Err Reg Byte 2

Bits<5-0> = CER Byte 2

Cache Err Reg Byte 1

Bits<5-0> = CER Byte 1

Cache Err Reg Byte 0

Bits<5-0> = CER Byte 0

NMI Error Address Reg 4

Bits<29-1> = PA<K29-1>

MM ENABLE,

respectively

NMI Fault Reg Byte 1

Bits<4-0> = NFSR Byte 1

NMI Fault Reg Byte 0

Bits<4-0> = NFSR Byte 0

NMI Silo

Bits<19-0>

EBox Error Reg

IBox Error Reg

The
the

Byte

NMI

and Byte 0,

SILO

Byte 2,

respectively

NBI diagnostic routines test for error conditions and detect
cursor prompt for the
The
NMI.
the
of
condition

microdiagnostics

'MIC>'.

4.3.2.2 Status and Error Information -- During the execution of
1is made
much information as possible
as
microdiagnostics,
the operator. Both section and test tracing
to
available

the

name

and

revision 1Pv 1 of each
)

vil

niame

displays

tracing

section that is being executed. Test tracing display fw

Section

is provided.

information

an
TM

a brief description of each test being executed.

error printout is available that provides the SYNCH
fields for hardware debug. SYNCH UPC provides the
UPC
UPC and CONT
WCS address at the top of the loop, and CONT UPC provides the WCS
address of the microinstruction just beyond the error loop.
An

extented

Example 4-1
output with
sample

shows a sample micromonitor/microdiagnostic display
Example 4-2 shows a
section and test trace enabled.

output with

error message.

MIC>

DIAGNOSE

TESTING

LEFT

EZKBA

REV

X.Z

RIGHT

CPU

TEST

(Description

TEST

Test

(Description

Test

EXKBB

TEST

END

REV

X.Z

(Description

PASS

[NO

ERRORS

DETECTED]

MIC>

Example

4-1

MIC>

SELECT

MIC>

DIAGNOSE

Microdiagnostic

RIGHT

EZKBA

REV

CPU

TEST

(Description

Test

(Description

Test

RIGHT CPU

FAILING

Output

X.Z

TEST

***

Display

RIGHT

TESTING
-

Sample

FAILED

HW:

SYNCH

UPC:

Example

4-2

***

M1234,

aaaa

EZKBA

M5678,

CONT

***

TEST

M9012

UPC:

***

ERROR (01

....

bbbb

MIC>

Sample

Microdiagnostic

4-7

Error

Display

***

4.3.2.3

Micromonitor Error Messages -- The following is a list of

possible micromonitor error messages:

Unexpected trap occurred (type of trap)

Unexpected interrupt occurred (type of interrupt)
NOTE

a
detected by
error
unexpected
An
the
that
s
indicate
diagnostic usually
illegal
to some
code went off
WCS
location.

Illegal error number received from WCS-based test

Illegal message received from WCS-based diagnostic
Failure sending message to diagnostic
Power

not

Illegal section name(s)
No section currently loaded
Illegal test number(s)
Maximum test number exceeded
Micmon protocol error

Unable to load console-based section
Unable to load WCS-based section
Unable to load diagnostic CSM

4.3.3

Macrodiagnostics

The macrodiagnostics are both VAX 8800 system specific and generic
Macrodiagnostics (except EVKAA) are run under the
diagnostics.
VAX diagnostic supervisor

(DS>).

The macrodiagnostics are used to test and isolate problems in the:
CPU kernel (both left and right CPU)
I/0

subsystem

I1/0

adapters

I1/C devices such as the NBIA,

NBIB, VAXBI,; SI

The macrodiagnostics are also used to exercise various portions of
the VAX 8800 system as well as repair verification. The cursor
prompt for the macrodiagnostics is:

In order to
both
system,

DS>.

NOTE

fully test the VAX 8800
the macrodiagnostics and

the microdiagnostics must be run.

Table

4-3

1lists

and

describes the major tests available in the

macrodiagnostic programs.

1 4-8

Table

4-3

Macrodiagnostic

Test

Description

EVKAA

Function

Verification

EVKAB

Basic

Instruction

Instructions

the

VDS

Kernel

Exerciser.

Instruction

Set

Native

Mode

Runs

in:

Integer

Arithmetic

Variable-Length
Control
Queue

Tests

Bit

Fields

Instructions

Character Strings
Decimal Strings
EVKAC

VAX

Floating-Point

EVKAE

VAX

Privileged

EZKAX

VA
VAX

8800

EZKAX

Exerciser

Architecture

System-Speci
1fic
3

Processor

Power

Processor

Halts

User

Writable

Machine

EZXCA

NMI

Diagnostic

Customer

system

are

When

the

operator

the

failing

and

are

The
the

required

passed

failed.

Customer

(CRD)
to

option.

fast

and

are

enable
CRDs

packaged
the

are

easy

use.

and

the

TEST

wunder

the

user

media

Auto-Test

mode

loaded

CRDs

will

status

complete

runnable

automatically

the

test,

diagnostics

mode

test
and

All

command

option

being

checked,

whether

that

user

two

given,
of

inform
the

particular

with

the

results

and

the

with

control

system

isolate

test

the

provide

set

designed

English.

proceeds

micromonitor.

Test

designed

diagnostic

test

Test

Diagnostics

mind,

Store

Diagnostic

diagnostics

problems

printed

the

Runnable

runnable

Access

Communication

Adapter

Activity

Control

NMI-to-VAXBI

customer

Exerciser.

Failure

EZCJA

user-friendly

Cluster

Checks

Dual-Processor

4.3.4

CPUJ

tests:

Internal

Customer

Diagnostic

the

the
time

option

options:

4,3.4.1

Auto-Test

operation
diagnostic

The

internal
The test

auto-test

opticns,
requires

mode

verifies

VMS system disk,
approximately 20

the

and the
minutes

complete.

4,3.4,2

Mode

allows

verification

time

dependent

4.3.5

Remote

port

COMM
of

REMOTE

remote

terminal.

the

remote

port

local

state

from

inadvertently
and

4.4

console

PRO-38N

system.

From

remote

the

CPUs.

This

The

NBox

keying

test

prior

4.4.1

Module

placement

step

modules

when

4.4.1.1

Module
are

Key

will

and

the

NBIA

state

console

1is

the

operator

while

diagnostic

the

change

local

is
and

from

the

can

operator

8800

the
to

power

1is

key

remote

limited

operation.

system

turned

cooling

blower

the

for

EMM

the

performed

test

that
szl

The

second

and

the

to
the

module

backplane.

key

test

1in

one

34—

damage
m Lt la

verifies

The

lohNa

two

that

steps.

there
to

that

the
[N 3

the

The

are

module
FST S WA W S W g R v

correc

slot.

<correctly

ensure

cause
LR
W R
)

step

intended

will
J-S- S

module
.

VAX
to

voltage

slot

Test

contrel

prevents

remote

PRINTER

that

1local

command

executed

operating

machine

modules

Memory

commands

1local

groupings:
CPU

not

the

for

software

Verification

the

1installed

Clock
L)

=W
N =

module

applied.

installed

modules

module

DISABLE

applied

application

available

console

The

the

verification

uses
is

run

SYSTEM

Placement

console.

during

supplies

ingerted
o
g S
S

that

test

options.

POWER

The

breaker

power

module

system

1identical

restriction

place.

circuit

1is

execute

changing

commands

position,

NBox.

first

The

the

connected

cannot

taking

main

auto-test

reasons,

commands

port

status

port

safety

POWER/ENVIRONMENTAL

When

installed

)

control

VAX

1is

the

8800

MONITORING

the

debugging

remote
the

mode,

the

options.

VAX
For

from

DISABLE

When

rear

the

console.

accepted

extension

number

pmst

not

the

wview,

operator's

supported

Diagnostics
on

access

point

the

system

remote

upon

mode

all

O
(OR
j

Mode

of
the
CPU
1load
disk.

module

I 4-19

verifies
of

the

VAX

8800

following

that

four

The

modules

cannot

Dbe

correct
CPU

within

grouping,

decoder

There

1is

they

will

EMM

module

wrong

slot

into

the

shifter

test

the

other

segments

card.

CPU,

memory

and

<clock,

power

The

the

MCL,

requirements

and

installed

the

(for

module

array

slots.

pins,

circuit

signal

1is

and

back

compares

and

key

enable

backplane

EMM

from

front

module

the

EMM.

the

shows

how

the

groups

and

returned

EMM

Key

VAXBI

memory

VAXBI

modules,

array

key

sense

power

use

modules

use

input

shown

input

Holding

with

holds

the

EMM

"Electrical

Key

used

VAX

signal

the

system.

the

EMM

internal

EMM

looped

Key

Override"
8800

reset

commands
from
illuminates the KEY

not

EMM

from

test

The

the

LED

VREF
<

state

state,

keeps

the console.
FAULT LED on
switch on the

system.

through

the

Figure

four

4-2

Module

MODULE KEY

SENSE

Keying

Test

I4-11

Simplified

Block

4-3

module

SCLD-108

Figure

the

reference

CPU BACKPLANE

| cOMPARE

reset

MODULE KEY

DISABLE

a
two

The

Sense.

EMM

EMM.

that

POWER

modules

NBIA

looped

example,

slot).

and

the

wire

Sense

key

Source
to

the

signal

receiving

front

Key

uses

turn

single

detected.

the

asserts

error

the
EMM
Failure
the

fit

sense

voltage

the

installed

parallel

4-2

computer

The

similar

that

cards.

Figure
key

have

requirement

not

three
five-segment

The

group

provided

even

module

use

segment

damaged,

Diagram

CPU BACKPLANE

WIS|D|[C|A|S|S|S|IN|S|IC|IN|W|S|ID|C|A|S|S|S|M
C|E|E|C|D|L|L|H|B|P|L|B|C|E|E|C|D|L|L|H]|C
[A|lK]|lI

SiQ|C|S|P|C|{C|R]I

0|1

|S|Q|C|S|{P|C|C|R|L

0|1

5 lolototo—to-to—to+ olo | o] o|rorofo—to—qo—10—10—O0—1 ©
ooooooooo'_:;
olololo |o |o|o |o]|o|o

A28
B28

L, C28
_(o)oooooooo | of|
ooooooooooJ_(o)l
D28
ololo lolo lololo
O
o—

ololojo |o |ojo (o

MCL
A28 = GND
B28 = GND
C28 = OPEN
D28 = GND

CLK
A28 = GND
B28 = OPEN
C28 = GND
D28 = GN

CcPU
= OPEN

égg = GND

C28 = GND
D28 = GND

KEY SENSE

KEY SOURCE

NBIA/SPARE
A28 = GND

B28 = GND

C28 = GND
D28 = OPEN
SCLD-109

Module Key Test Connections

Figure 4-3

Placement

Module

4.4.1.2

-- When the key test verifies that the

are installed in a correct grouping and power is applied,
modules
Vbus is used to determine that the correct module is inserted
the
in

the

clock

Vbus

The

the

within

and CPU

test

CPU

slots.

that is used to test for correct module placement

group

not work if the clock module is not

will

slot. (The Vbus control registers are
correct
the
in
installed
on the console interface portion of the clock module.)
located
used

4.,4.2

The
has

to check

for the presence of

the

Power Monitoring/Error Reporting

environmental
for
sensors

module in the power system complex
cabinet
airflow,
system
cooling

monitoring
monitoring

temperatures, and line and system operating voltages. The EMM also
contains actuators that control the application and removal of the
the battery backup unit in response to console
and
power
system
commands.

The

EMM

has

a microprocessor that communicates with the console

processor
and
performs
a
power shutdown when the environmental
are not within allowable specifications established by
parameters
the

console.
I

4-12

4.4.2.1

Default

first

applied

Mode

Error

and

the

communications

with

parameters

monitor

barameters

RAM

during

the

are

the

EMM

character
of

EMM.

When

the

The

where

the

operator

following

default

when

the

sequence

console
to

pass

Flow

Battery

error

not

monitoring

establishing

When

one

the

console

not

command

sample

resolved
and

EMM

shuts

warning

five

message

DMCODE

16-18;

Diff

D12-Dl4

20-21;

establish

=--

set

the

unsolicited

five

minutes,

During

error

the

EMM

power-up

A-L

the

power—-up

parameters

monitored

minute

the

system

I 4-13

AFF1-2

passes

default

display.

with

console

the

Regulator

it
the

Reporting

sequence.

used

T1-T4

begin

down

are

point

Therm

sends

single

until

prints

0-11;

the

and

EMM

console

point

fails

12-15;

parameters

display

the

power-up

codes

the

DMCODE

EMM

software
the

the

communicate

DMCODE

DMCODE
Fault

the

default

into

test

the

DMCODE

communications.

specifications,

error

DMCODE

Fault

replace

ready

default

inform

failing

The

parameters:

Transition

set

selftest,

reaches

stops

reached

Operational
Error
initialization
process, the
EMM

power

established

loaded

message,

and

EMM

the

console

parameter

4.4.2.2
the

the

display

has

Backup

are

the

console

the
EMM,

Temperature

Air

and

repeats

the

system
yet

uses

console

Temperature

the

When
not

performance.

ROM

the

Voltage

Module

EMM

during

EMM

until

receives
with

EMM

error

sent

sequence

console

the
system

the

communications
message

failure.

-has

procedure.

successfully

power-up

the

code

EMM,
power

boot

detects

error

test

passes

the

stored

EMM

Reporting
console

EMM

used

asserts

power.

longer

meets

message
the

the

Example

prior

warning

timer.

and

TOTAL

4-3

problem

OFF

shows

**** WARNING, ENVIRONMENTAL MONITORING MESSAGE RECEIVED

VOLTAGE EXCEPTION REPORTED BY EMM 2067, 5-AUG-85

REG A transition from 'In Range' to 'Below Range’
input: 2
hilim: 0000

mea: 0001
lolim: 0000

pol: +
mar: 0000

AUTOMATIC SHUTDOWN IN PROGRESS (BLINKING)

B
ok

C
ok

D
ok

E
ok

F
ok

G
ok

H
ok

reg:
mok :

A
ok

sig:

AF1 BBF CBF AF2 ACL DCL PEN PER

val:

Example 4-3

4.4.3

10:00:00

I
ok

J
ok

K
ok

L
ok

KAC LAC KEY
ok ok ok

EMM Warning Message

Voltage Margining

ed up
The voltage regulators in the VAX 8800 system can be margin
d.
comman
or down by the console operator, using the SET MARGIN
ers
The Margin Enable (MARGEN) and Margin Hi Lo (MARHILO) Regist
Module
shown 1in Figure 4-4 are EMM registers used to margin the voltage
Power Supply Regulators. The MARGEN Register enables
margining for the appropriate regulator when the correspondinifg bit
the
is set. The same bit in the MARHILO register determines
regulator voltage is raised or lowered.

MARGIN

ENABLE REGISTER
SET - MARGIN
RESET = RETURN
TO

BIT
BIT

= RT

L UE

NOT USED

REGULATOR

B +5.0

V BBU

REGULATOR C +5.0

REGULATOR D -2.0

REGULATOR E -5.2

REGULATOR F Bl
REGULATOR H B
NOT USED

MARGIN

BIT

LO REGISTER

SET =

MARGIN HI

BIT RESET = MARGIN LO

NOT USED
REGULATOR B +5.0

V BBU

REGULATOR C +5.0

REGULATOR

D -2.0

REGULATOR

E -5.2

VvV

REGULATOR F Bl
REGULATOR

H B

NOT USED
SCLD-110

Figure

4-4

Margin

Enable

and

I 4-15

Margin

Registers

4.5

MAINTENANCE AIDS

4.5.1

Machine Check Logout Stack

time the processor detects
A machine check exception is taken any excep
tion must be detected
check
an internal error. Each machine blis
Parameters from the
way.
hed
and reported to VMS in an esta red
be collected from
to
have
environment in which the error occur
a Machine Check
onto
d
various locations in the machine and pushe
to determine
VMS
by
stack is used
Logout Stack. The data in the lly
to Conscle
n
retur
and
or halt
whether to continue to run norma show
Machine
the
of
t
forma
the
Mode. Figures 4-5 through 4-15
registers.
Check Logout Stack and associated error

I 4-16

STACK

FRAME LENGTH

BYTES

(20

MACHINE CHECK STATUS REGISTER

HEX)

(MCSTS)

MICROPC

VA/VIBA

IBOX

ERROR REGISTER

(IBER)

CBOX ERROR REGISTER (CBER)

EBOX ERROR REGISTER

(EBER)

NMI

FAULT SUMMARY REGISTER

(NMIFSR)

NMI

ERROR ADDRESS REGISTER

(NMIEAR)

MACROPC

PROCESSOR STATUS LONGWORD (PSL)
SCLD-11+

Figure

4-5

Machine

Check

I 4-17

Logout

Stack

CBOX ERROR REGISTER

03 02 0100
31 302928 27262524 232221201918 1716151413 121110 09 08 07 06 0504

o|{o|0|0j0|0OfO0O|O0O0]|0

0(0}0

VA PARITY ERROR ————

TB DATA PARITY ERROR

CACHE DATA PARITY ERROR
MEM DATA PARITY ERROR
TB TAG PARITY ERROR
NMI CS PARITY ERROR
BAD READ DATA
BAD PIBA DATA

NMI DATA PARITY ERROR
SCLD-112

Figure

4-6

CBox

Error Register

IBOX ERROR REGISTER

31 30 29 28 2726 2524 23 2221201918 171615 1413 121110 09 08 07 06 05
04 03 02 0100

O
olo|ofojo|0j0O|Of0O|0O|O|O|0O|O|0O|OjO|0|0
PiBA

FAILURE

BAD MICROADDRESS

iIB

PARITY ERROR, UPPER WORD

PARITY ERROR, LOWER WORD
SEQ IPR

PARITY ERROR

DEC IPR

PARITY ERROR

DECODER RAM OUTPUT PARITY ERROR

CONSOLE TO DEC PARITY ERROR
CS0 PARITY ERROR
CS1 PARITY ERROR
CS2 PARITY ERROR

DEC TO CONSOLE PARITY ERROR

I.—.J
20

—

SCLD-113

EBOX ERROR REGISTER

PARITY ERROR

SOURCE FOR B SIDE

B SIDE PARITY ERROR \J
A SIDE

fi/\)
,

DATA

]

SOURCE FOR A SIDE DATA
SCLD-114

Figure

NICTRL

NM!

4-8

EBox

Error

INTERRUPT CONTROL IPR#

= 80

WRITE ONLY

31302928 27262524 2322212019
18 171615 1413 12 1110 09 08 07 06
05 04 03 02 0100

o“;oo{o%;o; 00 ooio%loo ojojo]o oo]oo
T

DEVICE

INTERRUPT ENABLE

DEVICE

INTERRUPT ENABLE

MEMORY INTERRUPT AND NMI

0 OWlOW
T

]

FAULT ENABLE
SCLD-115

Figure

4-9

NMI

Interrupt

4-19

Control

IPR# = 82 READ ONLY

NMIESR - NMI FAULT SUMMARY

31 30 29 28 2726 2524 23 22 21 201918 171615 1413 121110 09 08 07

0|0]0

00\0\\
T

06 05 04 03 02 0100

0000\0 O\OOOGOO\OlOOO
H

]

TIMEQUT STATUS 0
TIMEOUT STATUS 1
TIMEOUT STATUS 2
TRANSMIT

READ SEQUENCE ERROR

CONTROL PARITY ERROR

ADDRESS/DATA PARITY ERROR
BUFFER ID <0>
BUFFER ID

<1>

NMI FAULT

<0>

BUFFER CODE

<1>

0
0

0
1

NO TIMEOUT
WRITE TIMEOUT

PIBA TIMEQUT

BUF

READ TIMEOUT

TIMEOUT CODE VALID IF BUF ID INDICATES TIMEOUT
<0>
_LO_.LO_LQ—LO

<i>
..n._soo_n—loo

a0 00

<2>

NO TIMEOUT
RESERVED

INTERLOCK TIMEOUT
NO RETURN READ DATA

NO ACCESS - NO RESPONSE
NO ACCESS TO BUS

NO ACCESS - INTERLOCKED
NO ACCESS BUSY

SCLD-116

Figure 4-10

NMT Fault Summary
1 4-20

NMISILO

NMI

SILC

DATA

READ

ONLY

31302828 27262524232221201918 1716151413 121110 09 08 07 06 05040302010
0
)

i
|

0
|
|

00!00
I

RS
L

NMI CONFIRMATION
NMI

ADDRESS/DATA

NMI

FUNCTION

NMi

MASK

RIGHT CPU ARB

LEFT CPU ARB
MEMORY ARB

1/0

ARB

I/0

ARB

MEMORY BUSY

DIAGNOSTIC
AFTER

SILO

MARKER

FAULT
SCLD-117

Figure

NMIEAR -

NMI

4-11

ERROR ADDRESS REGISTER

NMI

IPR#

Silo

Data

READ ONLY

31 3029 28 2726 2524 23 2221
2019 18 171615 1413 1211
10 09 08 07 06 05 04 03 02 0100

NMi ADDRESS <29::00>

SCLD-118

Figure

4-12

NMI

Error

4-21

Address

READ/WRITE
IPR# = 85
COR - CACHE ON REGISTER
3 121110 09 08 07 06 050403 020100
171615141
918
232221201
27262524
28
31 30 29

0000000000000000000000000000000
CACHE ON
SCLD-118

Figure 4-13

MCSTS - MACHINE CHECK STATUS

Cache ON Register

READ VERSION

iPR# = 26

31 30 29 28 2726 2524 232221201918 1716151413 121110 09 08 07 06 0504 03 02 0100
00
000000000000000000000000000
MACHINE CHECK ENTERED FROM INTERRUPT
MACHINE CHECK IN PROGRESS

ABORT
SCLD-120

Figure 4-14

REVR1 - REVISION REGISTER 1

Machine Check Status

IPR# = 86

READ ONLY

31 30 29 28 2726 2524 232221201918 1716151413 121110 09 08 07 06 05 04 03 02 0100

SHR

SLC1

SLCO

ADP

CCS

DEC

SEQ

WCS

READ ONLY
IPR# = 87
REVR2 - REVISION REGISTER 2
121110 09 08 07 06 0504 03 02 0100
1413
34 30 29 28 2726 2524 232221201918 171615

UCODE TOP REV

USER UCODE REV

Figure 4-15

CONSOLE TOP REV

BACKPLN

Revision 1/2 Registers
1 4-22

CLK

EK-KA88B-TD-PRE

SECTION
SYSTEM

BUS

SUMMARY

CHAPTER
MEMORY

1.1

INTRODUCTION

The

Memory

Interconnect

interconnects
I1/0

adapters as
description that
The
and

NMI

has

system

(NMI)

follows

are

multiplexed
It

CPU)

arbitration

bus

signals

ECL,

The

primary

systems.)

The

NMI

CPU

services

CPU

may

also

supports

Write

Read

the

all

quadword,

I/0

following

octaword,

data.

Only

left

Terms
wused
Table 1-1.
lines

(bus

for

data

longword,
longword,

and

plus

bus

line

in
and

left
DC

right

CPU

the NMI.
(The
dual-processor

transfers

the

NMI.

transactions:

quadword,
octaword,

hexword

1-1

lines

generated

and
and

octaword
hexword

transactions

are

used

for

I1/0

transfers.
If desired, memory data transfers
may be
interlocked by the memory nexus (inte
rlocked reads/unlock

and
NMI

control

arbitrator
AC

that

the

control

(NMI)

memory,
1in

and

FET-driven

read/write

longword

CPUs,

address/data

interrupts

transactions:

memory

except

the

transactions:

transfer

has

backplane

attached

centralized

either

performs

Longword,

data

are

address/data
also

Bus

primary

synchronous

defined

parity.
and

VAX 8800 primary and
shown
in
Figure
1-1.

clocks.

signals.

the

INTERCONNECT

hardware

writes).

CPU 0
(PRIMARY CPU)
NEXUS

CPU 1
(ATTACHED CPU)
NEXUS

(MEMORY INTERCONNECT

1/0
ADAPTER
NEXUS
(NBI 1)

1/0
ADAPTER 0

(NMI)

MEMORY
NEXUS

SCLD-122

Interconnect

Memory

}..._J

1-1

Figure

(NMI)

Table

1-1

Term

Definition

Nexus

Transaction

hardware

Glossary

block

transaction

consists

data).

(command/address
return

The

read

discrete

one

transfer

two

one

(command/address

three

two

transfers

data

that

NMI

transfer

and

before

may

consist

relinquishes

NMI.

example,

(1)
or

cycle(s)

The

nexus

the

CPU

The

NMI.

(read/write). A transa
ction
transfers. For example,
a write

followed

that

the

(2)

initiates

nexus

that

the

memory

the

responder.

1-3

after
bus

nexus
the

cycles.

cycle of a read
command/address cycle
and the

transaction.
a

read

example,

CPU

one

occurs

command/address

the

write

commander.

Responder

the

transaction

Commander

NMI

consists

transfer

connects

control

data

Terms

data).

gets

For

read

NMI

physically

task performed on the
consists of one or more

and

Transfer

that

transaction.

For

from memory,

object

initiates

of
a

read

example,

the

CPU

transaction.
from

memory,

if
the

For
the

1.2

BASIC

FUNCTIONS

The NMI performs six major functions.

Memory read/write operations —-- By means of bus read/write

the CPUs and I/0 adapters to access
allows
transactions,
(Memory read/write operations by the I/O adapters
memory.
are DMA operations initiated by the I/O devices connected
to the adapters.)

I/0 register read/write operations -- Again by means of
the primary CPU to
allows
transactions,
read/write
bus
I/0
memory,
the
in
registers
tatus
control/s
access
adapters.
the
to
connected
devices
1/0
the
adapters, and
Interrupt

handling

Transmits

interrupt

requests

generated by the memory and I/0 adapters to the primary
by an I/0 adapter may be
(Interrupt requests
CPU.
itself or by the I1/0 devices
adapter
I/O
generated by the
connected to the adapter.)

System synchronization -- Provides system

clocks

all

nexus.

System initialization -- Allows console to initialize all
(UNJAM console command asserts UNJAM signal on
nexus.

NMI.)

Power loss warning —-- Provides AC LO and DC LO signals

].—l
|

all

nexus.

t—4
1=

1.3

NMI

SIGNALS

Generally,

bus

AND

are

TIMING

signals

are

asserted

and

which

phase

cycle,

signals
Refer

bus

received

Figure

and

latched

negated

the

using

NM|

BUS

system

phase

1-2,

B CLK H

CYGLE

the

beginning

clock.

the

Also,

system

bus

clock.

%’i

j:><:

TRANSMIT PERIOD
f'

A CLK H

DATA VALID

///r—*———“\\\
RECEIVE

PERIOD

f DATA

LATCHED
SCLD-123

Figure

All

the

1-2.

NMI

signals

Most

nexus.

However,

signals

connect

module).

to
LO

shown

are

the

originate

signals
power

are

signals

1-2

on
and

the
bus
DC

NMI

Figure

generated

system

the

Basic

clocks

clock

subsystem.

1-5

1-3

(and

and

only

some

module,

arbitrator
signals

Timing

are

the

defined

connect

to)

miscellaneous

and

the

left

generated

bus

CPU
by

NMI

control

arbitration

(in
the

Table

the

the
EMM

CCS
the

32
i

NMI

JARS

FUNCTION<4:0> H

4 .

DATA PARITY H, FUNCT ID PARITY H

CONFIRMATION<1:0> H

INTERRUPT AND FAULT LINES

NMI

NExus

ID MASK<3:0> H

~
NEXUS |

ADDRESS DATA <31:00> H

32
yd

(SEE SHEET 3)

ARBITRATION
LINES (SEE SHEET 2)

CLOCK AND MISC.
<

CONTROL LINES (SEE SHEET 4)

AC LO L/DC

LO L|(SEE

SHEET 4)

CLOCK

EMM

BUS

ARBITRATOR 4—— ARBITRATOR
O CATED, o

MODULE

CCS MODULE

ARBITRATION LINES

(LEFT CPU)

MEMORY HOLD H
(1)
LEFT CPU HOLD H (1)
RIGHT CPU_HOLD H£1§

MEMORY ARB H
1/0 0 ARB H
170 1 ARB H

MCL BUS EN
1/0 0 BUS EN
1/0 1 BUS EN

i/0

RIGHT

1/0 0 HOLDH
i

HOLD

MEMORY BUSY H

((11))

LEFT CPU ARB H_

LCPU MEM INTR H
DEVO LINTR

DEV1

LINTR

LVL<1:0>

FAULT LINES

(14)

(1)

DEV1 LINTR H

H (2)

CPU

BUS

MISC.

RCPU MEM INTR

DEV1 RINTR H

DEVO RINTR

DEV1

(5)

LVL<1:0>

RINTR LVL<1:0>

(1)

CONTROL LINES

H
SLOW MODE
HARBINGER <2: 0>
RESET <1:0>

SYSTEM CLOCKS

(SEE SHEET 4)

(10)

UNJAM <2:0> H
{3)
SLOW CLOCK ENABLE H §1 g

DEVO RINTR H

FAULT DETECT<3:0> H (4)

FAULT

LEFT CPU BUS EN 513

ARB

MEMCRY BUSY ARB H

INTERRUPT LINES

DEVO LINTR H

CPU

(1)
(1)
1

1
éS;
2

BACKPANEL SELECT LEVELS
170

SEL <1>

ONE LEVEL H

(1)
SCLD-124

Figure

1-3

NMI

Signals

1T 1-6

(Sheet

NMI_ARBITRATION

NEXUS

LEFT

CPU

LEFT

CPU ARB

¢«

_LEFT

CPU BUS

«—

MEMORY BUSY

RIGHT

HOLD

¢«

BUS

«MEMORY BUSY

BUS
<_(ARB
ARBITRATOR

CPU)

—>

EN H

HOLD

ARB H

1/0

BUS

1/0

|
<

REQ LINES)
"

ADAPTER 0

170
ADAPTER 1

/0 1 ARB H
1/0

BUS

NEXUS

HOLD H

MEMORY BUSY

H_,

NEXUS

¢ MEMORY HOLD H

MEMORY

¢ MEMORY BUSY H

.5
— BUS EN LINES) L /g

MEMORY BUSY ARB H

<« MEMORY ARB H

(SEE_NOTE)

NOTE:

MEMORY BUSY

¢—(HOLD LINES)

CCS MODULE

CPU HOLD H

RIGHT CFU

RIGHT CPU ARB H

SE;(JUS

(LEFT

LINES

NEXUS

MEMORY BUSY ARB H

MCL BUS

EN H

MEMORY BUSY ARB IS NOT AN
ARBITRATION REQUEST LINE.
OF MEMORY BUSY THAT CONNECTS
TO THE BUS ARBITRATOR.

COPY

SCLD-125

Figure

1-3

NMI

Signals

1-7

(Sheet

INTERRUPT AND FAULT LINES

DEVC INTR H

DEVQ LINTR H

LEFT

CPU

NEXUS

IO
2
5
0
(DEVO LINTR LVL<1:0> H 7| Lg 7 DEVO LINTR LVL<1:0> H| ADAPTER
NEXUS

¢ DEV1 LINTR H

DEVO RINTR H

I ,2 DEV0 RINTR LVL<1:0> H

(SEE NOTE) ¢ DEVI LINTR LVL<1:0> H/2

FAULT DETECT <2> H

¢ LCPU MEM INTR H

)

FAULT H

1/O SEL<1> H=0

FAULT DETECT 0 H
FAULT H

NEXUS

(HARD WIREDj¢—ONE LEVEL H
<

2 DEV1 LINTR LVL<1:0> H

DEVO RINTR LVL<1:0> H
¢ DEY1 RINTR H

¢ BCPU MEM INTR H

KSAPTER
1
NEXUS

DEV1 RINTR H

‘7,2 DEV1 RINTR LVL<1:0> H

(SEE NOTE) . DEV1 RINTR LVL<1:0> H 2
¢

DEV1 LNTR H

¢ DEVO RINTR H

cPU

FAULT DETECT <3> H
FAULT H

FAULT DETECT1 H
<

/0 SEL<1> H=1

FAULT H

(HARD wineD)«——ONE LEVEL H
¢ LCPU_MEM INTR H

MEMORY

INTR H

BCRU MEM BT
¢

FAULT DETECT<3:0> H

NEXUS

¢ FAULT H

NOTE: ONLY THE PRIMARY CPU IS
ENABLED TO SERVICE NMI
INTERRUPTS.

SCLD-126

NMI Signals (Sheet 3 of 4)

Figure 1-3

SYSTEM

CLOCKS AND

MISCELLANEOUS

CONTROL SIGNALS

A\
AC LO H

CPU

NEXUS

EMM

DC LO H

SLIOW CLOCK ENABLE H

< AC IO H
<« X 1O0H

UNJAM <n> H
SLOW CLOCK

ENABLE

110

SLOW MODE H
HARBINGER

3
UNJAM <2:0>

DC LO

SLOW MODE H

(SEE

2
UNJAM

<2>

SLOW CLOCK ENABLE

(SEE

NOTE 2:

HARBINGER

SIGNAL

NOTE

HARBINGER

NEXUS

SYSTEM

CPU

A CLK H/L,

MEMORY | F

110

CLK

NOT USED BY

MEMORY
NEXUS

CLOCKS

NOTE

SLOW MODE H
SYSTEM

& RESET <n> H

RESET <1:0>

ADAPTER
NEXUS

Tpno= <i:0>

i
MODULE

<n>

AC LO H

SLOW CLOCK ENABLE

NBI.

<2>

CLOCKS USED
B

CLK

H/L

CLK

B CLK

H/L

H/L,

A CLK H/L,

F A CLK H/L,

H/L

B CLK H/L

(THESE

CLOCKS NOT USED BY NBI)
SCLD-127

Figure

1-3

NMI

Signals

1T 1-9

(Sheet

Table

Signal

Line(s)

ADDRESS
DATA<31:00>

1-2

Number
32

FUNCTION<K4:0>

NMI

Signal

Descriptions

Description
Transfer 30-bit read/write address
during NMI command/address cycles
and 32-bit longword of read/write
data during NMI data cycles.
Specify type of bus transaction
(command type) during command/address
cycle and type of data during NMI
data

cycles.

FUNCTION<K4:0>

(Hex)

Command/Data

Type

Read

Longword

Read

Octaword

Read

Hexword

Read

Longword

Read

Octaword

Read

Hexword

(Interlocked)
(Interlocked)
(Interlocked)

Write

Longword

Write

Octaword

Write

Longword

Masked

Write

Quadword

Masked

Write

Octaword

Masked

Write

Longword

Unlock

Write

Quadword

Unlock

Masked

Write

Octaword

Unlock

Masked

Memory

Return

Read

Data

(Good

Return

Read

Data

(Bad

Masked

Pause

(Not

Used)
Data)

Data)

Read

Continuation

(Good

Read

Continuation

(Bad

Write

1-19

Data

Data)

Table

Signal
ID

Line(s)

MASK<3:0>

1-2

NMI

Number
H

Signal

Descriptions

(Cont)

Description

Specify

commander

command/address
data

cycles.

memory

nexus

commander

cycles
ID

because

during

and

required
it

bus

NMI

return

read

for

never

the

transaction.

Nexus

0100

CPU

(Primary

CPU

(Attached

NBI

(VAXBI

NBI

(VAXBI

NBI

(VAXBI

NBI

(VAXBI

0101
0110

0111
1000

1001
1010

1011
1100

1101
1110

1111

CPU)

During

NMI write data cycles of masked
transactions, specify the bytes in
longword (four bytes) of write data

write
the
to

MASK

written.

BIT

3210

DATA

PARITY

Write

byte

Write

byte

1XX

Write

byte

Write

byte

parity

bit

for

the

during

NMI

command/-

Transfers
ADDRESS

address

even

DATA

lines

and data
transmitter.

nexus.

11 1-11

cycles.

Parity

checked

computed

all

Table

Signal

1-2

Number

Line(s)

FUNCTION ID
PARITY H

NMI

Signal Descriptions

Description

Transfers even parity bit for the five
FUNCTION lines and four ID MASK lines during
NMI command/address and data cycles. Parity
computed by transmitter. Parity checked by
all

CONFIRM-

ATION<1:0>

(Cont)

nexus.

Specify response
sent

(by responder)

to function

commander.

CONFIRMATION

<1:0>

Arbitration

Response

Responder

response

10
11

Responder
Responder

accepts

data
interlocked
busy

Lines

MEMORY ARB H

Asserted by memory nexus to request use of
the bus. This bus arbitration request line
has the highest priority.

10 0 ARB H

Asserted by I/0 adapter 0
request

LEFT

ARB H

CPU

ARB

RIGHT CPU ARB H

use

the

Asserted by

I/0 adapter 1

request

use

the

nexus

(NBI

nexus

(NBI

bus.

Asserted by
of the bus.

left

Asserted by

right CPU nexus

the

CPU

nexus

request

reguest

bus.

NOTE

Arbitration requests by I/O0 adapter and
CPU
nexus
have
the same (lowest) priority and are granted on
an alternating basis.
That is, if there
are
both
CPU
and
1I/0
adapter requests, a CPU will get the

bus

I/0 adapter was given the bus

last

(and

vice
versa).
Also, if there are two CPU requests
when a CPU is given the bus, CPU 0 gets the bus
if
CPU
1
was
given
the
bus last (and vice versa).
Similarly, if there are two
1I/O
adapter
requests
when an I/0 adapter is given the bus, I/0 adapter O
gets the bus if I/0 adapter 1
was
given
the
Dbus
last (and vice versa).

use

Table

Signal

Line(s)

MEMORY

BUSY

1-2

Number

NMI

Signal

Descriptions

Description
Asserted

data

memory

buffers

transmitter
rearbitrate

are

during
of
MEMORY

BUSY

abort
the

bus

copy

the

bus

when

line

will

LEFT

RIGHT

HOLD

CPU

HOLD

CPU

HOLD

when

arbitration

MEMORY

BUSY

during

read,

first

data

cycle

request

line.

connects

arbitrator.

only

Asserted by memory nexus
command/data buffers are full. This
disables the bus arbitrator so that it

Asserted

nexus

another

(more

winning

the

bus.

Asserted

left

another

(more

winning

the

bus.

Asserted

right

another

(more

winning

the

bus.

Asserted

I/O

requires

another

memory

winning

than

CPU

another

I/O

winning

CPU

nexus

one)

bus

(more

than

requires

after

cycle

when

cycle

nexus

requires

after

requires

after

when

one)

bus

cycle

bus.

adapter

(more

than

the

cycle

when

bus

adapter

the

requires

when

bus

nexus

one)

than

by the CPU and
arbitrator will
the memory nexus.)

(The

one)

than

Asserted

requests

nexus

when

one)

bus

cycle

bus.

NOTE

HOLD

signals

cannot

MCL

BUS

disable

arbitrate

bus

requests

arbitrator
by

Asserted
nexus

its

from

after

and

memory

that

command/

asserted

write.

not arbitrate
adapter nexus.
arbitrate requests

after

its

current

transaction
bus

cycle

I/0

MEMORY

when

Causes

command/address

memory

Not

nexus

full.

for

command/address

ARB

(Cont)

use

1-13

any

by
of

that

nexus.

bus
the

arbitrator
bus.,.

grant

memory

Table
Line(s)

Interrupt
0

BUS

LEFT

CPU

BUS

Description

Asserted by bus
adapter 1 nexus

arbitrator to grant I1I/0
(NBI 1) use of the bus.

Asserted

arbitrator

CPU

BUS

INTR

nexus

Asserted
CPU

MEM

(Cont)

arbitrator to grant I/0
(NBI 0) use of the bus.

LCPU
PT

Descriptions

Asserted by bus
adapter 0 nexus

RIGHT

Signal

Lines

Number

NMI

|—

Signal

1-2

nexus

Asserted
left

bus

use

bus

use

CPU.

the

arbitrator

the

memory

(Left

grant

left

grant

right

bus.

nexus

CPU

bus.

enabled

interrupt
as

the

primary

CPU.)
RCPU
PT

MEM

INTR

Asserted
right

CPU.

memory
(Right

nexus
CPU

interrupt

enabled

the

the
primary

CPU.)
DEVO

LINTR

Asserted

interrupt
the

DEV0O

RINTR H

primary

Asserted

DEVO

LINTR

LVLL1:0>

the

by
the

DEVQ

RINTR

LVIK1:0>

(Left

Asserted

specify

the

CPU.

DEVO

nexus

(Left

adapter

CPU

CPU.

adapter

interrupt

enabled

nexus

(NBI

(Right

CPU

nexus

(NBI

request

enabled

I/0

adapter

interrupt

CPU

(L/R)INTR

nexus

reguest

enabled

LVL

level

primary

enabled

(NBI

primary

BR4
BR5

BR6

BR7

Level

0)
to

to
left

CPU.)

level

Interrupt
Request

1-14

(NBI

CPU

CPU.)

I/0

(Right

<1:0>

CPU.

right

primary

specify

CPU.

I/O

the

Asserted

adapter

left

CPU.)

interrupt

I/0

the

Q)
tc

to
right

CPU.)

Table

Signal
Fault

DEV1

Line(s)

1-2

NMI

Number

Signal

Descriptions

Description

Lines

LINTR

RINTR

Same

DEVO

adapter

Same

DEVO

adapter
DEV1

LINTR

Same

LVLL1:0>
DEV1

RINTR

FAULT

by
4

DEVO

except

I/0

except

asserted

I/0

nexus.

LINTR

asserted

nexus.

RINTR

(NBI

adapter

line

adapter
a

I/0

Each

DETECT<3:0>

I/0

LINTR

(NBI

LVL<1:0>

(NBI

except

asserted

nexus.

Same as DEVO.RINTR LVL<1:0> except asserted

LVLL1:0>

FAULT

(Cont)

CPU

nexus

Left

Right

I/0

Asserted

nexus

signal

been

ORed

fault-handling

Fault

has

are

DETECT

Detected

CPU

nexus

CPU

fault-handling

logic

FAULT

asserted.

Used

request,

freeze

interrupt

detected

nexus
adapter 0 nexus
adapter 1 nexus

that

I/0

nexus.

FAULT

nexus.

corresponding

Signals

when

memory

logic

has

(NBI

asserted

fault.

DETECT

(NBI

memory

line

generate

a CPU
the NMI transaction
latch the fault status

silo

in the CBox, and
registers in all nexus.

Miscellaneous
Control

UNJAM

Signals

Initializes
status
UNJAM

the

also

VAXBI.

response

all

nexus

registers.

1-15

causes

If
a

Asserted
the

without
I/0

nexus

power-fail

console

clock

clearing
is

sequence

module

command.

fault

NBI,

Table

Signal

Line(s)
<1:0>

RESET

1-2

Number

Signal

NMI

Descriptions

(Cont)

Description

Each line asserted by corresponding NBI
adapter if VAXBI RESET is asserted. Causes
console to stop both CPUs and then boot the

system (a cold start). The boot
occur until RESET is negated.
Asserted

RESET

MODE

SLOW

(NBI
(NBI

0)
1)

Asserted by clock module and used to
increment timeout counters in all nexus.

SLOW CLOCK
ENABLE

not

1/0 adapter 0 nexus
I/0 adapter 1 nexus

0
1

does

Early-warning signal asserted by clock
module to indicate that the normal system
clocks (A CLK and B CLK) are about to
start or stop. Asserted a minimum of 4
microseconds

HARBINGER<2:0>

before

HARBINGER.

All lines asserted by clock module during
last B PHASE clock when normal

clocks are stopped.

system

Used as clock blocking

signal by nexus using free-running clocks
(F A CLK and F B CLK) to simulate stoppedclock condition.
HARBINGER

0
1

I1/0 adapter
I/0 adapter

Memory

0 nexus
1 nexus

nexus

FET driven and received power-loss warning
signal asserted by EMM when ac power 1is
below specified

Connects

limits,

FET driven and received power-loss warning
signal asserted by EMM when dc power 1is
below specified limits.

1-16

Table

Signal

Line(s)

1-2

Number

NMI

Signal

Descriptions

(Cont)

Description

Backpanel

Select

I/0

Levels

SELK1>

Backplane-generated

(hard-wired)

that

determines

address

each

I/0

adapter

generated

I/0

SEL

nexus.

CLK

I/0

connects

output

equivalent

NMI

Base

Address

(Hex)

2000

0000

2400

0000

level
I/0

that

LEVEL

Logic

output

nexus.

the

(logical

Used

one)

assert

asserted

I/O

SEL

input

backplane.

Clocks
H/L

Phase

clock

module.

CLK

ONE

connection

nexus

signal
B

one

signal

the

for

logical

wiring

Adapter

each

System

(No

signal

space

zero.)

SEL

<1>

LEVEL

nexus.

backplane

input

logical

I/0

ONE

the

I/O

H/L

normal

gating

Phase

module.

normal

period

CLK

and

asserted

clock
the

system

Stalled

bus

the

with

the

system

NMI

clock.
CLK

CLK

between
the

Generated
generated

STALL.

The

clock.

cycle

Generated

leading

defined

edge

next.

CLK

H/L

Phase

free-running

system

clock.

CLK

H/L

Phase

free-running

system

clock.

NOTE

nexus

may

specific
copy

receive

than

one

system

clock

from

the

clock

system

clock

pair

driven
and received
destination module.

signals

1-17

copy

module.

Each

differentially

connecting

STALL

CBox.

on
in

only

one

NMI
1

ADDRESS

Gbyte

1-4,

One

other

half

I1/0

half,
is

the

two

space

and

Mbytes

evenly

(the
the

each

CSRs)

and

The

NMI

the

VAXBIs

two

VAXBI).

the

NBI

address,

the

which

1lines

Figure

multiple

16).
to

This
zeros

that

Three

Four

thus,

low-order
—~ v =

asserted

—

bits

—~ nm

low-order

bits

The

the

NMI

data

transferred

NMI

VAXBI

ADDRESS

DATA

(during
on

the

the
30

lines

bits

transaction
to

addresses

that

are

bits

address

quadword

address

octaword

address

are

type.

naturally

quadword

low-order

s R

VAXBI,

The

for

address

the

significant.

each

purposes.

upon

longword

are

example,

high-order

depends

addresses

(32

controller

the

two

all

for

asserted

addressing

adapter

transaction

1is

addresses,

NBI,

registers

space

for

following
not

set

allocated

(for

VAXBI

used

octaword

352

[ QN AP A

write

are

low-order

Chapter

address

the

NBI

address

write

the

one

and

longword

means

Two
o~~~

(even

memory

1-3.

read

not

the

bits,

not

eight,

significance

and,

private

and

registers

DATA<29:00>).

transactions,

addresses

Table

VAXBI

space

connect

registers,

for

The

are

1-5,

Their

write

(ADDRESS

DATA<31:30>)

significant.

cycle).

(ADDRESS

are

may

registers

discussed

beginning

I/0

node

space

VAXBI

The

the

each

block

controller

1in

reserved

adapter

node

are

allocated
a

memory

NMI

space

The

I/0

CSRs).

VAXBI

Figure

low-order

aligned

are

memory.

When

that

I/O

shown

physical

allocated

nexus

command/address

During

The

block

total),

(CSRs).
is

space.

listed

shown

block

space

node

address

lines

64-Mbyte
Mbytes

address

registers

VAXBI

the

nexus

(128

allocated

registers

VAXBI

NBI

are

includes

I/0

32-Mbyte

for

either

registers

Dbetween

Mbytes

space

Mbytes,

adapters

control/status
the

address

512

allocated

I/0

Mbytes,

SPACE
NMI

1.4
The

multiple

can

that
of

assumed

During

read

blocks

the

transactions,

data,

but

for

read

address

identify

the

low-order

bits
the

are
two

except

1/0

devices).

may

Dbe

and

high-order
Basic

<29>

1),
the

longword

(address

DATA

lines

there

bit

during
transfer

I/0

addition,
one

DATA

selection

the

address,

when
(0

select

shown

address

bits

VAXBI

<28:26>

the

I/0

1).

memory

lines.

read

bit

<01>

for

All

must

are

data

Figure

1-19

data

(The
at

over

I1/0

adapter
bit

<25>

(<29:25>)

time.)

the

address.

NBI,

CSR.

word

the

Address

controller

the

over

1-6.

I/0O

bits

word

the

these

read

cycles.
of

that

<01>

specify

returned

not

most

devices
NMI

must

are

and

bit

returned

memory

adapter

UNIBUS

Thus,

the two
longword

address

(memory

explicit

longword

specify

only
write

address

are

longword

(some

aligned

wrapped.

transactions

devices

is
=

naturally

first;:

transaction

<01>

normally

read

devices

lines

ADDRESS

adapter),

read

NMI address
determines

1,0

(address

appropriate

equal

the

ADDRESS

DATA

word-oriented
because

low-order

may

hexword

longword-oriented

words

read

Low

words

bits

This

address.

High

for

For

significant.

ADDRESS

not

and

from

to
be
transferred
significant.
Also, as

low-order

connected

transaction

octaword

longword

address,

significant

transfers are also
multilongword transfers

bit

selects
must

0000

NBI ADAPTER ADDRESS ALLOCATION

PHYSICAL
MEMORY
(512 MB)

(32 MB FOR EACH VAXBI)
©
NBI

_
2000 0000
1FFF FFFF
2000

0000

23FF FFFF
2400

0000

1/0
ADAPTER 0

21FF FFFF

FFFF

2800

0000

(32 MB MB)

I1
fl2200 0000 | VvAXB
(32 MB)
23FF FFFF

(64 MB)

110

2400 0000

ADAPTER 1

27FF

0
VAXB!

(64 MB)

25FF FFFF

(352 MB)

27FF FFFF

NBI 1
VAXBI 0

(32 MB)

MEMORY

CONTROLLER

(32

MB)

SCLD-128

Figure 1-4

NMI Address

11 1-28

Space

Table

Address
NBI
+
+

bb
bb
bb

Bus

Interrupt

(BICSR)

(BER)

Control

Destination

IPINTR

IPINTR/STOP

Mask

IPINTR

Starting

Ending

BCI

Source

Address

Control/Status

Status

Force

IPINTR/STOP

User

(WSTAT)

Command

Interrupt

Control

(UINTRCSR)

General-Purpose

Not
Not

Nexus)

(GPRO)

used

General-Purpose
Not

used

General-Purpose
Not

used

General-Purpose

(NMI

(FIPSCMD)

—-—

NBI

(SADR)

(EADR)

(BCICSR)

Write

(IPINTRSRC)

(IPINTRMSK)

Destination

(FIPSDES)

(INTRDES)

—-=

(DTYPE)

(EINTRCSR)

—-—

Error

——

Control/Status

Device
VAXBI

Controller

Registers

bb
bb

and Memory

NBI

Registers

Node)

Registers

(Hex)*

(VAXBI

I/0

1-3

used

Registers

2x08

0000

Control/status

2x08

0004

Control/status

2x08

0008

Reserved

2x08

000cC

Reserved

2x08

0010

BR4

vector

2x08

0014

BR5

vector

2x08

0018

BR6

vector

2x08

001C

BR7

vector

11 1-21

Table

1-3

1I/0

Address
Memory
—_—

Registers

NBI

and

(Hex)*

Memory

Controller

(Cont)

Registers

Controller

Registers

300

0000

Control/status

3E00

0004

Control/status

3E00

0008

Control/status

3E00

000C

Control/status

3E00
3E00
3E00

0010
0014
0018

Control/status
Control/status
Control/status

4
5
6

*NOTE:
For

NBI

(VAXBI

Node)

For

Registers

NBI

(NMI

Nexus)

Registers

2000

0000

(hex)

2000

(hex)

node

(NBI

VAXBI

2200

0000

(hex)

2000

(hex)

node

(NBI

VAXBI

2400

0000

(hex)

2000

(hex)

node

(NBI

VAXBI

2600

0000

(hex)

2000

(hex)

node

(NBI

VAXBI

0)
1)

READ LONGWORD (TO

WORD-ORIENTED DEVICE)

313029
X|

SIGNIFICANT

ADDRESS BITS

READ LONGWORD, READ OCTAWORD, READ HEXWORD, WRITE
LONGWORD
3130 29

X| X

SIGNIFICANT ADDRESS BITS

X | X

WRITE QUADWORD
3130 29

X\ X

SIGNIFICANT ADDRESS BITS

02 01

WRITE OCTAWORD
313029

X| X
NOTE:

SIGNIFICANT ADDRESS BITS
AN X

INDICATES

BIT

NOT USED FOR ADDRESSING

X[
X| X]|X

PURPOSES.

SCLD-129

Figure

1-5

NMI

1-23

Address

Bits

l 0!

MEMORY ADDRESS
I/0

28 2726

1/O ADAPTER G REGISTER SELECT BITS

0:10:0

VAXBI 0 REGISTER SELECT BITS

28 2726

VAXB! 1

EN 1/0
ADAPTER

IS NBI

(NB1 0)

25
I/O ADAPTER 0 REGISTER SELECT BITS

0|01

00 ___1

24
VAXB! 0 REGISTER SELECT BITS

WHEN /0

RAUACIcCH

/ls NBI
(NBI

28 2726

11111

VAXB!

24
MEMORY CONTROLLER

CSR

SELECT

BITS

SCLD-130

Figure

1-6

NMI

Address

11 1-24

Selection

1.5

READ/WRITE

Before

any

first

request

TRANSACTIONS

nexus

can

and

then

asserting

1its

arbitrator

monitors

than

one

grants

requesting
transfer

HOLD

Bus
A

1is

bus

and

write

bus

read

commander

The
of

read

for

During

write

and

the

transaction

the

FUNCTION

type

the

bus

the

nexus

the

bus

arbitrate

during

necessary

the

transfer

transaction

The

bus

some

the

and

cycle

ADDRESS
and

required.

one

transfer.

DATA
ID

1-25

first

read

the

and

assert

last

the

nexus

First,

the

read

transfer

transactions.

not

ready

octaword.

transmits

octaword

followed
by

are

the

transaction,

number

the

third

hexword

data

the

for

command/address.

transaction

lines.

is,

return

transmitted

write

own

bus

read

commander

example,

its

the

That

transfer

transfer.

octaword

information

the

second

for

second

free)
to

only.

arbitrates

transfers

for

arbitrator.)

information

than

and

bus

transfer.

responder)

requires

except

the

bus

line

must

1.7.

transaction.

(the

bus
EN)

cycle

transfer

disables

command/address

for

(for

lines

one

must

The

priority

the

one

c¢ycle,

NMI

for

1line.

(BUS

commander)

1-8.

first

(when

enable

Section

indicated.
the

this

(the

following

1-7

does

request

cycle,

NMI,

only

must

and

nexus

the

requires

ends

when

one

bus.

transaction

commander

then

command/address

address

the

commander
may

data

the

request

bus

granted

discussed

This

the

transferred

lines

cycle

transaction

data

Figures

bus

transfers

occurs

Timing

than

arbitrates

This

transaction

responder

data

take

the

bus,

bus

from

resolves
a

The
each

the

use
(ARB)

asserting

signal

then

transfer

requests,

HOLD

data.

addressed

all

during

initiating

granted

requesting

(The

write

arbitration

nexus.

arbitration

nexus

bus

signal

cycle.

NMI

nexus
the

perform

and

the

memory

the
or

transmits

read

MASK

signal

called

the

also

shown

NMI

longword)

lines.

I/0

the
on

WRITE OCTAWORD

WRITE QUADWORD

WRITE LONGWORD

NMI CYCLE

C/A

30-BIT
ADDR

ADDRESS DATA <31:00> | <29:00>

DATA

| WRITE | WRITE | WRITE |
DATA
DATA
DATA

WRITE
DATA

LEGEND

MAN

% ; g%gPONggg
AN =

C/A

FUNCTION<4:0>

WRITE | WRITE

SOURCE

ID MASK<3:0>

CMD

DATA

CMDR'S |

SOURCE

DATA PARITY
CHK

WRITE

DATA
C

BYTE

ADDRESS

WRITE |

DATA
C

WRITE

DATA
C

BYTE

MASK

EVEN

EVEN | EVEN

BY
(23DY
EVEN | EVEN | IGNORED

CONFIRMATION<1:0>

MASK

|¢—

ID
C

GEN

NEXUS

COMMAND/

CYCLE

SOURCE

ALL

MASK FIELD

INUT

IVIRONLC
W

WRITE.

SOURCE

CONFIRMATION OCCURS THIS CYCLE

T
HOLD H

WRITE

1-7

LONGWORD

Figure

FOR ALL WRITE COMMANDS.

WRITE QUADWORD

L——

NMI Write Transaction

1-26

WRITE

OCTAWORD

LEGEND
C =
R

COMMANDER

AN =

C/A

RESPONDER
ALL

READ HEXWORD (SEE NOTE 2)

NEXUS

%%%ASSND/ADDRESS

READ OCTAWORD

MN—

READ
LONGWORD

NMI
CYCLE

C/A

.
T

30BIT

SEE NOTE 1—J

ADDR

ADDRESS

DATA

)

DATA

—\

DATA

READ | READ | READ

DATA

__DATA

|READ |

<29:00>

DATA

READ | READ | READ

DATA | DATA |DATA
5

<31:00>

SOURCE
FUNCTION

READ

<4:0s

CMD

SOURCE |
€
ID MASK
CMDR

<3:0>

SOURCE
GEN

EVEN

CHK

CONFIRMATION

SOURCE

NOTE 2:

NM!

AVAILABLE

RTN | READ | READ

|READ

DATA | CONT | CONT | CONT

| ovoR
ID

EVEN | EVEN | EVEN | EVEN

CMDR | CMDR |CMDR
ID

EVEN | EVEN | EVEN | EVEN

| AN

—7

| AN

p
fig;

HOLD H

R
| R | R
B
|cmoR [ cmoR [ovoR [omor |

<1:0>

NOTE

DATA | CONT | CONT | CONT

~ | B

PAR

RTN | READ | READ | READ

l[:

FOR OTHER TRANSACTIONS.

RESPONDER (MEMORY)

RELEASES NMI AFTER TRANSFER
OF FIRST OCTAWORD
THE READ HEXWORD TRANSACTIO
N SHOW.
RESPONDER (MEMORY) MAY
ALSO HOLD BUS AND TRANSFER
ALL THE DATA (EIGHT SUCCE
SSIVE DATA
CYCLES) IF SECOND OCTAWORD
IS READY FOR TRANSMISSION.

SCLD-132

Figure

1-8

NMI

Read

1-27

Transaction

ction 1is a
Following the command/address cycle and if the transa
the ADDRESS DATA
write, the commander transmits the write data on numbe
r of these
The
lines during the next bus cycle or cycles.
data cycles depends on the transaction type. (One longword of data

cycle.)
may be transferred over the 32 ADDRESS DATA lines eachs bus
the FUNCTION

also, during the data cycles, the commander assert its a Dbyte
lines to identify the data as write data, and it transm
write.
mask on the 1ID MASK lines if the transaction isrd a ofmasked
data
write
longwo
the
in
bytes
which
(The byte mask indicates
cycles
data
no
read,
a
is
ction
transa
the
If
are to be written.)
immediately follow the command/address cycle.

When the
All nexus monitor the NMI during each bus cycle.
it will
responder 1is addressed during a command/address cycle,
data"
ts
accep
onder
"resp
a
ng
mitti
trans
accept the transaction by
MATION
CONFIR
The
lines.
MATION
CONFIR
(OK) response on the NMI
ess cycle.
lines are asserted two bus cycles after the command/addr
der taking
respon
the
with
ction
transa
These steps complete a write
the write data as it is received during each data cycle.

for the NMI
A read transaction requires the responder to arbitrate
S DATA
ADDRES
the
over
der
comman
the
to
data
and return the read
data
of
number
the
,
(Again
.
cycles
data
lines in one or more
cycles depends on the transaction type. Two separate transfers of

FUNCTION lines
data may be required as stated previously.) The data
of a
identify the data as return read data. The first otherscycle
a
have
all
ied;
specif
on
functi
transfer has a return data
ies
specif
on
functi
the
Also,
ied.
read continuation function specif
Bad data 1is data that cannot be
if the data is good or bad.
corrected

by memory.

y the
During all read data cycles, the ID MASK lines byspecif
the
taking
ction
transa
the
tes
comple
commander and the commander
not
does
It
der.
respon
the
by
read data as it is transmitted
notify the responder that the data has been taken.

Figures 1-9 and 1-10 show the specific format

write

for

each

read

and

transaction type.

itte
Two separate even parity bits are generated by the transm
data
and
ess
d/addr
comman
during
der)
respon
(either commander or
on
ation
inform
the
for
ted
genera
is
which
cycles. One parity bit,
line.
PARITY
DATA
the
on
itted
transm
is
the ADDRESS DATA lines,
The other parity bit, which is generated for the information on
both

the

FUNCTION and ID lines, is transmitted on the FUNCTION ID

bad
PARITY line. The two parity bits are checked by all nexus. 1fother
and
Parity
fault.
NMI
an
(odd) parity is detected, it causes
errors that can occur during NMI read/write transactions are
discussed

in Section 1.9.

1-28

WRITE

CYCLE

LONGWORD

C/A

DATA

DATA|

ADDRESS DATA<31:00>

——

|ADR

FUNCTION<4:0>

—=

|wRITE | wRITE|

——

MASK<3:0>

|LONG

| DATA

——

| —=

—— | CMDR | BYTE | —=—
——
1D
MASK | ——

CONFIRMATION<1:0>

WRITE

CYCLE

QUADWORD

C/A

. DATA , DATA

|ADR

ADDRESS DATA<31:00>

——

FUNCTION<4:0>

—— | WRITE | WRITE | WRITE| ——

DATA | DATA|

——

—— | QUAD | DATA | DATA | ——

MASK<3:0>

—— | CMDR | BYTE | BYTE | ——
——

CONFIRMATION<1:0>

|ID

MASK | MASK | ——

| ——

WRITE OCTAWORD

CYCLE

C/A

|DATA

,DATA , DATA A DATA

ADDRESS DATA<31:00>

—— | ADR

FUNCTION<4:0>

—— | WRITE | WRITE
—— | OCTA | DATA

MASK<3:0>

CONFIRMATION<1:0>

—_——

:::1

SCLD-133

Figure

1-9

NMI

Write

1-29

Transaction

Types

ALL READS

(COMMAND/ADDRESS TRANSFER)

C/A

CYCLE
ADDRESS DATA<31:00>

| ——

|ADR

| —=—

FUNCTION<4:0>

—— | READ | ——
—— | TYPE

| ——

== | CMDR

| ——

MASK<3:0>

CONFIRMATION<1:0>

READ LONGWORD (RETURN READ DATA TRANSFER)

CYCLE

DATA

ADDRESS DATA<31:00> | =——

DATA

FUNCTION<4:0>

— =

|meap | ——

ID MASK<3:0>

——

— | ID

|owor | —Z

—_

CONFIRMATION<1:0>

—_

READ OCTAWORD (RETURN

|pmN

—_——

| —C

DATA TRANSFER)

CYCLE

DATA | DATA

ADDRESS DATA<31:00> | —~—

DATA

DATA | DATA | ——

DATA

FUNCTION<4:0>

—=— | READ

ID MASK<3:0>

—— | CMDR | CMDR | CMDR|

CONFIRMATION<1:0>

——

—— | HTRN

-_—— 1 |D

READ | READ|

READ | —=

CONT | CONT | CONT | TM=

CMDR | ——

—

_—

SCLD-134A

Figure 1-10

NMI Read Transaction Types

1-30

(Sheet 1 of 2)

READ HEXWORD (ONE

RETURN DATA TRANSFER)

CYCLE

DATA

ADDRESS DATA<31:00>

DATA

DATA | DATA

DATA

FUNCTION<4:0>

READ | READ
RTBN | CONT

READ
CONT

READ | READ
CONT | RTRN

READ
CONT

CMDR | CMDR
1D
ID

CMDR
1D

CMDR | cMDR

CMDR
iD

CMDR
ID

CMDR
1D

DATA

READ
RTRN

READ
CONT

CMDR

MASK<3:0>

CONFIRMATION<«1:0>

READ HEXWORD (TWO RETURN DATA TRANSFE
RS)

READ | READ
RTRN | CONT

MASK<3:0>

CMDR | CMDR

READ
CONT
CMDR
ID

o
o
o

00
o

oo
oo
0o

CONFIRMATION<1:0>

DATA
0

DATA

DATA | DATA

DATA

FUNCTION<4:0>

DATA

ADDRESS DATA<31:00>

DATA

CYCLE

CMDR
ID

SCLD-134

Figure

1-10

NMI

Read

Transaction

1-31

Types

(Sheet

1.6 INTERLOCKED OPERATIONS
s memory to be interlocked
The memory nexus has hardware that allow
by a write transaction. This 1is
by a read transaction and unlockedsses
in dual-CPU configurations
to allow synchronization of procery.

that access shared areas of memo

locked read transaction, the
when the memory eXxecutes an inter
ord, oOr hexword) is performed.
normal read function (longword, octaw
further interlocked read
However, it will not accept any been
removed by a write unlock
transactions until the interlock has
can hold a hardware
nexus
a
transaction. Also, to limit the time
the interlock after
e
remov
interlock, a counter in the memory will is excee
ded, the memory
a timeout period.

the

time

interrupts the (primary) CPU.

limit

it will accept normal read
During the time memory is interlocked,
However, a "responder
actio
transactions and all write trans to ns.
commander on the
the
interlocked" response 1is returned
n is attempted.
actio
trans
CONFIRMATION lines when a read interlock

11 1-32

1.7
To

BUS

ARBITRATION

control

bus

arbitration

(BUS

EN)

The

memory

line

However,

only

The

other

BUSY

line

nexus.

arbitration

(ARB)

connecting

NMI,

bus

the

bus

ARB

lines

one

(MEMORY

BUSY
from

has

connects

the

line,

two

nexus
(MEMORY

Basic

request

ARB)

ARB)
the

arbitration

CYCLE

C/A

memory

line

NEXUS

each

HOLD

nexus

line,

arbitrator

copy
nexus

timing

connecting

bus

and

MEMORY

the

shown

bus

enable

1left

the

CPU.

arbitrator.

request

BUSY.

CPU
in

bus

the

arbitration

has

The

and

I/0

Figure

line.

MEMORY
adapter

1-11.

Y
C/A

)

BUS EN x__/*/

DATA

Ang__//KL_‘____“_

BUS EN Y

}:///,/’

HOLD Y

SCLD-135

Figure

1-11

Basic

NMI

Arbitration

1-33

Line

Timing

ARB
its
assert
must
nexus
each
To request the use of the bus,
request
line.
The request line is asserted at the beginning of a
As
More than one nexus may request the bus at a time.
bus cycle.
the left CPU resolves request
in
arbitrator
bus
the
result,
a
priority and asserts the BUS EN line for the
winning
nexus.
The
BUS
EN line is asserted immediately if the bus is not currently in
use.
If the bus is in use, the BUS EN line is not
asserted
until

the
bus
1is
free.
This ensures a dead cycle between transfers on
the NMI, which is necessary due to electrical constraints.
When
a
nexus
receives
its BUS EN signal, it negates its ARB request line
at

the

beginning

the

bus

cycle.

If a nexus wins the bus and requires more than one bus cycle for
a
transfer,
1t
must assert its HOLD line to keep the bus.
The HOLD
line is asserted at the beginning of the first
bus
c¢ycle
1in
the

transfer.
It is negated at the beginning of the last bus cycle in
the transfer.
1In
the
bus
arbitrator,
the
asserted
HOLD
1line
disables
any
further
bus arbitration.
It also causes
line to the nexus holding the bus to remain asserted.

the

BUS

The memory nexus has the highest priority when requesting the
bus.
The
CPUs
and
I/0 adapters have the lowest priority and share the
bus on an alternating basis.
Operation of the
bus
arbitrator
is
shown

The CPUs
If
both

Figure

1-12.

and I/0 adapters share the bus in
the
following
a CPU and an I/0 adapter are requesting the bus,

CPU rather than an I/0 adapter won
the
adapter
wins
the
Dbus.
Conversely,

adapter had the bus last,

the CPU wins.

manner.
and if a

bus
1last,
then
the
1I/0
1if a CPU rather than an I/O

Furthermore,

both

I1/0

nexus

may

adapters are requesting the bus and an I/0O adapter wins, it will be
the one that did not use the bus last.
Similarly, if both CPUs are
requesting
the bus and a CPU wins, it will be the one that did not
use the bus last.
Typical arbitration line sequencing is shown
in
Figure

1-13.

addition

to having

the

highest

priority,

the

memory

assert
MEMORY
BUSY,
which
causes
the
arbitrator to completely
ignore requests by the CPUs and I/0 adapters.
MEMORY
BUSY
causes
the
arbitrator
to ignore requests by means of the MEMORY BUSY ARB
line (the copy of MEMORY BUSY connecting to
the
bus
arbitrator).
That
1is,
1like
the
HOLD
1lines,
MEMORY
BUSY
ARB
disables the
arbitrator but only for CPU or I/0 adapter requests.
Bus
requests
by
the
memory
1itself
can
still be granted.
Timing is shown in
Figure

1-14.

11 1-34

The

memory

full.

asserts

adapters)

data.

from

Also,

unrestricted

and,

thus,

MEMORY

memory

using

the

use

BUSY

addition

memory

that

transaction.

possible

some

MEMORY

during

indicates
the

When

MEMORY

first

the

write

this

case,

otherwise
These

nexus

should

(MEMORY

asserted

data

command

current

busy"

time.

the

cycle

will

not

transmitter

does

CONFIRMATION

lines

the

command

indicated

1lines

transaction.

are

and

memory
have

before

the

wvalid

bus.

That

code

returned

during

the

1-35

is,

"responder

and

before

become

current

code

retrying

the

another

available
for

line

further

the

busy"

then

asserted

only

1lower

two

the
bus

command/address

write

the

will

status

preventing

cycle
but
transaction, it also
the
memory.
Again,

wait

for

retrying

data

cycle

memory.

accepted

ignored

commander

the

retry

has

the

BUSY
is
asserted
during a
multilongword memory write tran
octaword),

the

early-warning

memory

the

not

nexus

accepted

the

BUSY

after

memory

current

I/0

commands

the

aborting

bus,

are

and

the

for

cases.)

first

the

data

buffers
CPUs

indicates

wait

before

allows

gets

BUSY

the

1lines

This

shortest

have

the

temporarily

transactions

command/address

not

data,

(the

possible.

acts

nexus

the

will

function

not

nexus

read

soon

during

BUSY

can

return

command

1its

priority

When

bus

MEMORY

CONFIRMATION

cycles

the

command/data

other

contain

the

does

until

buffers

its

the

transaction,

read/write

Lransmitter

bus

asserted

respect,

when

prevent

buffers

the

BUSY

the

read/write

this

the

this

empty

transmitter
In

MEMORY

does

the

"responder
transaction.

data cycle following the
saction
(write
quadword
current

accepted
on

the

second

transmitter.

memory

CONFIRMATION
data

cycle

unless
lines.
of

the

BUS ARBITRATION REQUEST

YES

HOLD

MEMORY »\ves

ARB

MEMORY HOLD

MEMORY
BUS
ARB

MCL BUS EN = 1

YES /
NO

CRFI)CLSJHT

LEFT

CPU

ARB

1/0

ARB

CPUY
LAST
USER

GPY

YES

110 0

ARB

YES

ARB

YES

YES
<«

ARB

UAST

RIGHT

ARB
cPU
YES
LAST
US‘E—R_Q__E_

HOLD

LEFT CPU BUS EN

UAST

ARB

/70 1

170 1

ARB

LAST

USER

veg|

RIGHT CPU

CPU

UAST

CPU

1/0 0

ARB

LAST

YES | USER

YES

NO
1/0

HOLD

RIGHT CPU BUS EN

ARB

CcPU

“NO

LEFT CPU

cPU

HO‘LD

1/0 0 BUS EN

170 1 BUS EN
SCLD-136

Figure

1-12

NMI

Arbitrator

Operation

NEXUS

CYCLE

C/A

MEMORY ARB H

LEFT CPU ARB H

RIGHT CPU ARB H
ARB H

I/0

ARB H

LEFT CPU HOLD H

Le-T

I/0

MEMORY HOLD H

MEMORY

LEFT CPU
WRT

DATA

/70

READ | READ | READ | READ

C/A

DATA | DATA | DATA | DATA

MCL BUS EN H

LEFT CPU BUS EN H

RIGHT CPU BUS EN H
{/0

BUS EN H

I/0

BUS EN H

N
SCLD-137

Figure

1-13

Detailed

NMI

Arbitration

Line

Timing

(Typical)

MEMORY BUSY DISABLES ALL

NEXUS

MEM

(CPU)

DATA

MEMORY BUSY ARB

(CPU ARB)

MEMORY ARB

C/A

|/~

=
>/

ARB)

)

_/———\_-

MCL BUS EN H

(CPU

EXCEPT BY MEMORY

REA

CYCLE

(1/0

BUS ARBITRATION

BUS EN)

_/__\-

MEMORY BUSY ASSERTED

COMMAND/ADDRESS CYCLE

ABORTS MEMORY READ/WRITE

NEXUS

TRANSACTION

C/A

CYCLE

C/A

(MEM R/W)

MEMORY BUSY H

(ABORT)

(RETRY)

ARB X H

—/'—\

US EN
X H

MINIMUN ASSERTION TIME
IS TWO BUS CYCLES

/—'\_

/_—'_\

CONFIRMATION<1:0>

_\_

—><
et

NOTE:

MEMORY BUSY ASSERTED

ALSO ABORTS TRANSACTION

FIRST

L BUSY RESPONSE

DATA CYCLE OF MEMORY WRITE.

AND CAUSES RETRY.

SCLD-138

Figure

1-14

MEMORY

BUSY

Timing

1.8

INTERRUPTS

The

interrupt

the

primary

enabled

There

are

lines
CPU

setting

two

on
bit

<00>

NMI

Conventional

special

FAULT

is,
an

the

when

NMI

state

when

certain

silo

bus

Interrupt

Priority

lists

interrupt

NMI

interrupt.

(1C)

and

highest

The

BR7

IPL

level

one

17.

The

IPL

14.

(IPL

15).

Table

1-4

the

NMI

errors

the

priority
an

other

only

CPU

are

I/0

condition

CPUs,

the
can

NMI

assert

detected.

This

for

bus

level
NMI

That

CPU,

silo

holds

the

faulting

and

the

request

highest

level

has

the

will

interrupt

Priority

Levels

IPL

(Hex)

(BR7)

I/0 Adapter

(BR6)

I/0 Adapter
I/0 Adapter

(BRS)

(BR5)

15
15
15

(BR4)

14
14

1-39

the

freezes

1/0
BR

each

highest
4,

IPL

adapter
5,

corresponding

priority

I/0 Adapter
I/0 Adapter

(BR4)

assigned

levels:

(BRS5)

has

priority

lowest

always

Interrupt

(IPL)

fault

Interrupts

the

0
1

the

primary

CBox.

has

Condition

I/0 Adapter
I/0 Adapter

(memory

assertion

signals

Fault

Memory

enable

device

error

bus

priority.

memory

I/0

including

seen,

possible

BR4

However,

Levels

level

The

Device
NMI

can

four

request

CPUs.

interrupts.

cycles.

1-4

bus

NMI

may

both
NMI

interrupt

interrupts

1.8.1

the

by
has

types

Table

thus

selected

the

NMI

nexus,

only

transaction

preceding

its

caused

All

not

interrupts.

interrupt

FAULT

CPU.

1line.

FAULT

connect

interrupts

nexus)

report

NMI

enabled

types

adapter

the

1is

corresponding

BR5

(IPLs)

request

1.8.2

Device

Interrupts

Seven NMI lines connect

the

primary

CPU

request

device

interrupt request line from the memory
an
1is
There
interrupts.
INTR
(DEVQ
(CPU MEM INTRPT) and one from each of the I/O adapters

and DEV1 INTR).
from
lines
LVL<L1:0>).

In addition, there are two interrupt request level

INTR
DEVI]
and
INTR LVL<1:0>
(DEVO
adapter
each
set
One
lines.
seven
these
of
sets
two
are
There

only
However,
connects to the left CPU and one to the right CPU.
as
interrupts
accept
to
enabled
1is
(the primary CPU)
one CPU
explained previously.

The

interrupt sequence

follows.

When ready to interrupt, the interrupting device simply asserts its
line and (if it is an I/O adapter) transmits a
interrupt request
More than one device may
request level code on the INTR LVL lines.
be requesting an interrupt at any time.
INTR LVLK1:0>

BR Level

00
01
10
11

BR4
BR5
BR6
BR7

interrupt
priority device
highest
the
to service
ready
When
microcode
CPU
the
request, and if the request is by an I/0 adapter,
register
The
reads an interrupt vector from an adapter register.
microcode
CPU
The
by means of an NMI read transaction.
read
is
does not read a vector from the memory when the memory interrupts.
I/0 adapter to
from an
vector
a
read
The CPU microcode must
That is, the interrupt can be
device.
interrupting
the
identify
or it
locally generated by the adapter itself (one vector wvalue)
can be generated by any one of the I/O devices connected to the
The vector is used
adapter {vector value depending cn the device).
(It is
to generate an address in the SCB.
the CPU microcode
by
are
added to the SCBB.) The contents of the SCB location, in turn,
by the CPU microcode to dispatch to the appropriate interrupt
used
service

routine.

of
each
by
The vector addresses for locally generated interrupts
an
case,
In this
I/0 adapters are in page 0 of the SCB.
two
the
vector
whose
adapter is interrupting as an NMI nexus like memory,
Vectors for devices connected to the adapters
in page 0.
also
is
are

allocated

starting with page

1.8.3
The

NMI

bus

These

Faults

errors

Bus

Write

Read

When

FAULT

are

the

nexus

checking

for

each

error,

nexus

detects

fault,

DETECT

line.

(Refer

DETECT

Figure

line

ORed
at

nexus

line

for

in
the

each

the

CPU

detects

fault,

from

the

primary

asserted

the

memory

all

they

the

256
of

bus
the

NMI

scheme

(faulting)
information.

cycle

the

FAULT

for

line.)

The

does

remains

(to

dismiss

CSR5

NMI

the

fault

SCB.

error

freezes

holds

status

bits

silo.

history

including

the

faulting

NMI

are

stored

further

This

file

cycle.

for

sequence.

(prevents

transaction

lines

to
the

causes

are

line

(When

reading

address

FAULT

locations,

each

silo,

the

The

last

states

cycle.

lines

lines
lines

lines

addressing

NMI

<29>

error

vector

CPU,

ADDRESS

FAULT

microcode

interrupt

CONFIRMATION

transaction

CPU

cleared

NMI

following

accessed

the

cycles

MASK

signals

FAULT
line
previously, and

the

nexus.

during

Arbitration
ID

the

other

and

There

cycle.

latches

256

FUNCTION

asserts

single

FAULT

of)

containing

and

bus

all

i1t

discussed

1-15.)

examined

primary

are

asserted

The

causing

stated

FAULT
page

adapter,

also

the

cleared

nexus,

may

controller.

condition

CPU,

until

the

memory

request

interrupt).

I/0

nexus

following.

interrupt

and

memory

beginning

connects

1In

follows.

errors

adapter

asserted

errors

I/0

The

condition

FAULT

memory

the

sequence

fault

errors

sequence

and

NMI

logically

FAULT

1.9.

CPU

negates

parity

errors,

Section

causing

DATA

silo

1logging

allows

IPR

(NMISILO

programs.

the

bus

information

read

first,

1-41

and

"last

in/first

for
the
most
followed
by
the

can

be
out"

recent

older

During
and

microdiagnostics,

the

silo

the

conditioned

silo
to

address
freeze

can

<cleared

when

the

address

(increments from the highest address back to
zero).
silo
information
to
be
captured without having to

fault

zero

overflows

This
induce

allows
an NMI

condition.

FAULT DETECT<n>H

FAULT H

CLEARED BY
READING CSR5

i
g4

—~f

MEMORY

CONTROLLER

SCLD-139

Figure

NMI

are

NMI

errors.

Signal

Timing

ERRORS
two

classes

Interrupt

(Only)

interrupt

request

Memory and
interrupt)

I/0 nexus
generate
request by means of

NMI.

Interrupt

These

the

requests

errors

nexus

the
the

only

cause

detecting

the

error.

interrupt
(a
interrupt lines

CPU

nexus

CPU

interrupt

are

CPU

device
on the

internally

generated.

also
of

fault

freezes

errors

are

transactions

causes

the
those

are

NMI

transaction

for

useful

which

I
[\

Faults

}._..J
i

There

Fault

1.9

1-15

silo.

recent

determining

request
Thus,

history

the

but

this
of

cause

NMI

class
bus

error.

NMI

errors

are

listed

Table

1-5.

1-5

NMI

Errors

Nexus

Checking

Error

Interrupt/
NMI

Error

Fault

Return

Read

Access

Access,

Busy

Access,

Interlocked

(Timeout)

Data

Bus

(Timeout)

(Timeout)
(Timeout)

Access,

Response

Interlock,

Unlock

Bus

Error

Parity

Write
Read

Sequence
Sequence

Errors

all

Error
Error

causing

timeout

adapter

nexus

conventional

That

generates

the

receive

return
certain

read

memory

denerates

for

long

too

Specifically,

checked

memory

read

data.

timeout

error

response

does

Yes

by the individual
timeout counter in a

when

access
Also,

request

The

not

check

commander

during

(The

bus

to
a

the

when

nexus

CPU

nexus

bus

timeout

are

does

another

counter

has

occurs

when

transfer.

This

requests

I/O

access

receive

following
these

absence

CPU

other
or

lines

for

because

code,

timeout

bus

the

continues

CONFIRMATION

gain

time.

access

the

return

transaction.)

1is,

interrupt

bus

granting

adapter

Yes

interrupt

Memory

I/O
not

nexus

1in

the

been

interlocked

the

arbitrator

time.

delays

the

data

length

I/0

interrupts

errors.

after

(Timeout)

CPU

return

error

only

read

data

will

errors
"no

occur

conditions

1-43

when

response"

CPU
a

code

cycle.

because

read

I/O

"busy"
on

The
is

not

cause

the

code,

response

transfer

initiating

command/address

transaction.

ITI

bus

adapter

"interlocked"

the

condition

the

memory

never

the

and
read
and
errors
parity
Errors causing an NMI fault are bus
responder
a
when
is
error
sequence
A write
sequence errors.
write
enough
That is, there are not
does not receive enough write data.
read
A
transaction.
specified
the
to complete
cycles
data
write
read
enough
receive
not
does
sequence error is when a commander
Also,
transaction.
the
complete
data (too few read data cycles) to
a read sequence error can be caused when a "read continuation" code
is
received
on
the
FUNCTION lines during a read data cycle, and
there was no "return read data" code received (flagging
the
first
longword
of
read
data)
during
a
previous
data
cycle
in the
transfer.

NMI errors detected by a CPU nexus will set error bits in
the
NMI
fault/status register (NMIFSR).
NMI errors detected by a memory Or
1/0
adapter
nexus
will
set
error
bits
1in
the
nexus
first
control/status

(CSRO).

11 1-44

CHAPTER
VAX

2.1

INTRODUCTION

The

VAX

VAXBI

Bus

shown

VAXBIs
system

Interconnect

connects

Figure

allowing
when

following

the

both

VAXBI

(VAXBI)

system

2-1.

Each

maximum

NBI

adapters

description

the

through

NBI
of
are

are

I/0

the

2-1

may

VAXBIs

installed.

defined

INTERCONNECT

bus

NMI

adapter
four

BUS

for

the

VAXBI

interface
to

The

Table

system.

(NBI)

connected
terms

2-1.

used

(VAXBI)

adapter

two

the

CPU 0

CPU

MEMORY

A
PR

NMI

‘

NBI

NB!

.
Ll

BOTH AN NMI NEXUS AND

A VAXB! NODE.

SECOND VAXBI (VAXBI 1) CONNECTION (IF ANY)

FIRST VAXBI (VAXBI 0) CONNECTION

BUS INTERCONNECT (VAXBI)

VAXBI
NODE

OTHER VAXBI
mDES

oooooo’

(1F ANY)

DEVICE

VAXBI
NODE

DEVICE(S)

\4
OTHER DEVICES (IF

ANY)
SCLD-140

Figure 2-1

VAX Bus Interconnect (VAXBI)

Table

2-1

Term

Definition

Node

Transaction

Master

hardware

block

connecting

(and

locations

on)

the

one

The

execution

the

term

VAXBI

loopback

the

request.

within

node

without

that

gains

node

VAXBI

node

one

VAXBI

physically

sixteen

node

command

special

loopback

using

the

VAXBI
the

VAXBI

interconnects
logical

bit

addresses

responds

wide

associated

with

the

VAXBI

devices
VAXBI

I/0

the

devices

nodes

(I/O

plug

I/O

VAXBI.

UNIBUS

used

inserted

one

bus

node.

adapters

example

adapter

processors)

the

also

bus

samples

all

then

(when

assumes

control

bus

(when
busy,

the
an

bus

inactive)
is

embedded

bus

transaction.

The

VAXBI

supports

Write

Read

busy).

bus

I/O

and

initiates

parity

not

backplane.)

the

that

requests.

The

during

allow

bus
is

following

longword,

2-3

any

node.
A
requesting

the

bus

quadword,

highest

bus

cycle

transaction

when

the

part

transactions:

quadword,

the

UNIBUS

one

node
with

arbitration

1is
of

Processor

VAXBI.

current

included

read/write

longword,

the

I1I/0

I/0

the

NBI

system's

family

node

The

the

adapter

each

following

are

system.

where

bus

the

controlled

used

the

nodes

bus

allows

cycle

transactions:

the

other

connected

transactions:

The

that

arbitration

the

lines.

initiated

with

interfacing

peripherals

can

priority

the

(DWBUA)

Bus arbitration for the VAXBI is
distributed
arbitration
scheme
use

bus

a
data

VAXBI
interfaces
(VAXBI
nodes) having
through
15.
(The
address
of
a
node
is

controllers

synchronous

Also,

transfers

VAXBI

transaction

determined

device

VAXBI.

data

master.

The

execution

operation

the

control

mode

transaction.

that

logical

consists

modules.

Terms

Interface)

occupying

VAXBI

VAXBI.

VAXBI

applies

The

Slave

Glossary

octaword
octaword

bus

every

All read/write transaction types

(longword,

are used for memory data transfers.
used to transfer I/0 register data.

Only

quadword,

longword

and octaword)

transactions

are

I1f desired,
memory
read/write
transactions
may
be
1interlocked
(interlocked
reads/unlock
writes).
Also,
memory
read/write
transactions may be specified
as
having
cache
1intent
following
cache misses.
This facilitates the invalidating of cache locations
in
cached
multiprocessor
configurations
on
the
VAXBI
(not
applicable
to this system, because any
VAXBI must have their caches turned off

processors that
as
explained

may
1n

be on a
Section

2.8).

All nodes using the VAXBI must use a ZMOS integrated circuit called
the
VAXBI
interface
<chip (BIIC) as the bus interface.
This chip
initiates and responds to all hus transactions in response to input
commands by the node's internal logic.
BIIC operation 1s discussed
in

2.2

the

NBI

BASIC

A VAXBI

Technical

Description.

FUNCTIONS

the

VAX

8800

system

performs

the

following

major

functions.

Memory read/write operations -- By means of bus read/write
transactions
directed
to
the
NBI node, allows DMA data
transfers between an I/0O
device
on
the
VAXBI
and
the
system's
main memory (on the NMI).
(Main memory may also
be accessed by an I/0 processor node on the VAXRBI.)

1I/0 register read/write
read/write transactions

operations
originated

-By
means
of
bus
by the NBI node, allows

the primary CPU (on the NMI) to access
example,
CSRs)
in the I/0 devices on
1/0 registers may also he accessed
hy
node

the

I/0 registers
(fnr
the VAXBI.
(Device
an
I/0
processor

VAXBI.)

Interrupt handling -- By means of
bus
INTR
transactions
directed
to
the
NBI node, allows the I/0 devices on the
VAXBI to interrupt the primary CPU (on the NMI).
Also, 1n
response
to
the
interrupts
and
by
means of bus IDENT
transactions
originated
by
the
NBI
node,
allows
the
primary CPU to read interrupt vectors from the I/0 devices
on the VAXBI.
(Interrupts by I/0 devices and the NBI
may
also be fielded by an I/O processor node on the VAXBI.)

System

synchronization

operation

all

nodes.

Clock

ANV

node

rovi
Provides

—--

ks
clock

are

generated

synchronize

the

NBI

System
a

initialization

node

sequence

the

causing

NMI

Power

all

2.3

VAXBI

VAXBI
All

The

and

near

the

are

the

and

The

VAX

console

and

basic

bus

Figure

bus

cycle.

end

the

information

confirmation,

signals

(AC

negated

asynchronously

LO,

signals

also

line,

allows

(AC

asserts

halt

both

LO/DC

RESET

CPUs

and

signals

start).

and

The

are

shown
are

The

ARB,

RESET,

respect

2-5

are

Figure

signals

signals.
the

2-2.

except

the

Data

path

2-3.

and

received

path

and

Table

clocks.

synchronous

BSY

STF,

ECL
in

levels),

asserted

data

The
and

defined

the

signals

cycle.

with

and

voltage

and

signals

signals.
NO

2-2

(TTL

timing

control

LO,

RESET

power-fail

NBI

cold

Provides

VAXBI

node.

the

ZMOS-driven

synchronous

parity,

NBI

bootstrap

warning

shown

are

asserting

AND TIMING

are

signals

beginning

system

loss

SIGNALS

signals

clocks

the

simulated

nodes.

FET-driven

and

LO)

initiate
6.

initiate

negated

and
are

The

are

bus

cycle.

the

latched
the

control

BAD)

other

data,

signals
control

asserted

and

D<31:00> L

VAXBI

NODE

(NBD)

PO L

NO ARB L

BSY L

RESET L

BAD L

STF

yaAXBI TIME H/L

VAXBI

PHASE H/L

AC LO L

DC LO L

AC LO AND DC LO GENERATED
BY NBI AND ALSO BY POWER

SUPPLY IN EXPANSION CABINETS.

‘

NODE

5
»

POWER

SUPPLY
(SEE NOTE)

SCLD-141

(@)}

VAXBI

2-2

Figure

NOTE:

VAXB!

Signals

Table

Signal

Line(s)

D<31:00>

2-2

Number
32

VAXBI

Signal

Descriptions

Description
Data

lines

and

30-bit

cycles

Specify

address
read,

transactions.

and/or

write,

(Also

destination

command/address
Transfer

data

arbitrating

I<3:0>

and

mask

read,

Specify
nodes

of transfer
command/address

invalidate

specify

cycles

write,

cycles.

length

during

interrupt

information
of

other

transactions.)

vector

decoded

during

level

during

data

IDs

during

arbitration

cycles.

Information

lines -- Specify VAXBI command
command/address cycles, byte
mask
write data cycles, and data statu
s

during
during

during

read

specify

the

arbitration

and

vector

master's

data

cycles.

during

read

with

cycles.

Also

embedded

I<3:0>

(Hex)

Command

Reserved

Read

(READ)
Interlocked

intent
3

Read

with

cache

Write

(WRITE)

Write

with

Unlock

write

intent

(UWMCI)

Write

intent

cache

masked

with

Interrupt

(INTR)

Identify

(IDENT)

Reserved

Stop

Invalidate

Broadcast

Interprocessor

2-7

(RCI)

intent

masked

(WMCI)

cache

(IRCI)

with

cache

(WCI)
cache

intent

(STOP)
(INVAL)
(BDCST)

interrupt

(IPINTR)

Table

Signal Line(s)

2-2

Number

VAXBI Signal Descriptions
Description
I<3:0>

CNF<2:0>

Byte

Mask

O
1

XXX1
XX1X
X1XX
1XXX

Write byte
Write byte
Write byte
Write byte

I<3:0>

Data

0X00
0X01

Reserved
Read data

0X10
0X11
0X00
1X01

Corrected read data
Read data substitute
Reserved
Read data, don't cache

2
3

Status

Corrected read data, don't cache
Read data substitute, don't cache

1X10
1X11

(Cont)

Parity line -- Transfers odd parity bit
for the I lines during embedded
arbitration cycles, and for the D and I
lines during command/address cycles, and
during data cycles when read/write (or
vector) data is being transmitted.

Confirmation lines —-- Specify response by
slave(s) to command sent by master, by
data cycles of a
slave(s) during the
receiving data
node
transaction, and by
during the two bus cycles following the
data cycles of a transaction.
CNF

<2:0>

Response

000

No Acknowledgment

001

Illegal

010

Illegal

011

Acknowledgment

100

Illegal

101

STALL

110
111

RETRY
Illegal

11 2-8

(NOACK)

(ACK)

Table

Signal

Line(s)

ARB

2-2

Number

VAXBI

Signal

No arbitration line -- Asserted by
arbitrating nodes, master, pending
slave

the

master

Busy

line

TIME

winning

the

bus

start

perform

special

loopback

request.

line

VAXBI

any

VAX

console

Indicates

selftest

Selftest

fast

line

mode

MHz

one

all

differentially

delay
order

such

simulate
sequence.

the

NMI

halt

both

CPUs.

the

system

RESET

to
LO)

RESET

boots

VAXBI

selftest
20

assert

then

when

NBI

LO/DC

node

operations

the

(AC

The

line

transaction,

NBI

the

start)

asserted

mode

Causes

causing
VAX

slave

the

power-fail

causes

together with NO ARB)
next transaction in

the

Reset

master

also

current

asserted

after

cycle.

transaction

the

Bad

H/L

pending

Asserted
that

nodes

The

May

detected
L

node

master,

cycle.

arbitration

extend

cold

STF

bus

Also

the

arbitration

progress.

BAD

indicate

(when

inhibit

embedded

RESET

during
an
L

(Cont)

Description

Oor

BSY

Descriptions

negated.

nodes

other

error.

Enables

the

fast

nodes.
driven

clock

lines

(ECL) -- Used in conjunction with PHASE
H/L to provide reference for VAXBI cycle
timing in all nodes. Generated by the NBI.
PHASE

H/L

MHz

(ECL)

H/L to
timing
AC

differentially

driven clock lines
Used in conjunction with TIME
provide reference for VAXBI cycle
in all nodes. Generated by the NBI.

line

Indicates

specified

limits.

expander

cabinets.

below
and

line

VAXBI

Indicates

specified

2-9

limits.

expander

Asserted

power

NBI

power

Asserted

cabinets.

below

and

NBI

VAXB!

BUS CYCLE

{200

NS}

€—— 50 NS—W

TIME H __/_\_/-—\__F_\__/_\_—/—\__/_\—-—
Va

PHASE H

TRANSMIT PERIOD

|
|

RECEIVE
PERIOD

100 NS ————P

100 NS

|
|

L———— DATA

LATCHED
SCLD-142

Figure 2-3

Basic VAXBI Timing

11 2-10

2.4

VAXBI

ADDRESS

SPACE

The

VAXBI

address

space

half

(512

Mbytes)

Gbyte.

physical

memory

shown

space.

2.4.1

Memory

Except

when

processor

memory

the

VAXBI

the

NBI

System

The

memory

the

1I/0

2.4.2
The

and

node

I/0 Address

allocated

VAXBI

each

I/0

when

the

transaction,
VAXBI

NMI

transfers

initiated

place

not

transfers

only

VAXBI

this

(on

the

I/0

VAXRBI

supported

case,
VAXBI

1is

are

memory

nodes,

the

CPU(s).

NBI

cannot

that

(directly

for

2000

four)

space

the

NBI

VAXBI

0000

VAXBIs

must

accessed
clear

translation

initiated
between

the

system.

the

address

Mbytes.

FFFF

shown

NBI

bits

(Hex)

VAXBI

The

(HEX),

same

for

This
means
that
response to an NMI
<26:25> during the NMI

below.

[Bits

I/O

Addresses(Hex)

<26:25>

Cleared

NBI]

0000

21FF

FFFF

VAXBI

0000

(NBI

23FF

O0)

FFFF

2000

VAXBI

0000

(NBI

21FF

FFFF

2000

0000

21FF

FFFF

2400

0000

25FF

FFFF

VAXBI

2600

0000

(NBI

27FF

FFFF

2000

VAXBI

0000

21FF

(NBI

FFFF

2000

0000

21FF

FFFF

for

each

VAXBI

Mbytes

each

window

I/O

node,

space

multicast

space.

contains

(Refer

addresses

space,

again

for

which

space

contains

VAXBI.

registers

For

example,

the

and

vector

addresses.
nodes

is,
other

interfacing

the
bus

VAXBI

allocated

another

bus

are

addresses,

each

that

nexus

1is

used
and

its

not

have

2-11

space

adapter

NBI

the

Node

from

the

node

(the

private

mapping

block

space

respond.

the

addresses
A

and

Multicast
can

node

devices

accessed

address

example).

node.

node

registers

for

space,

2-4.)

one

are

converted
for

consist
private

Figure
than

registers)

space

addresses

(UNIBUS

NMI

offset

Window

node

to
more

private
CSRs,

by
the

range

the

2200

NMI

associated

node).

21FF

VAXBI

I/0 Addresses

for

through

device
of

response

transfers

VAXBI

devices

NMI)

(The

I/0

actually

2000

The

I/0

the

independently

the

associated

support

supported.

memory

1In

local

space

1I/0

address

one

Space

I/O

(up

2-4,

half

system

memory

VAXBI

addresses,

VAXBI

the

data

take

its

main

data

and

VAXBI

memory

that

are

the
space

system's

processor.

processor

The

is,

the

memory

transfers,

the

memory

transaction.)

with

That

transfers

initiate

connected
VAXBI

to/from

node.

DMA

the

space.

are

Figure

other

Space

memory

node,

NMI

are

Address
a

The

space
adapter

VAXBI.

specific
of

window

That

the

space

2-5.
The register space for each node (8K bytes) is shown ined Figure
ers,
regist
The first group of registers, called the VAXBI requir
group

must be implemented by every node on the VAXBI. The second may or
are the BIIC-specific registers. A register in this group
may not be used depending upon the node design.

in the
The VAXBI required and BIIC-specific registers are contained 2-7
and
node's BIIC. These registers are shown in Figures 2-6 and pecifi
are described in the NBI Technical Description. The BIIC-sIf morec
general-purpose registers.
four
include
registers
be implemented outside the BIIC but
may
they
registers are needed,
these addresses are still within the 8K bytes of register space
allocated for the node.

s Selection

2.4.3 Addres
on the
A VAXBI memory or I/0 register address (30 bits) is asserted
write
or
read
a
of
cycle
bus
first
data lines during the
lines
data
rder
high-o
two
the
2-8,
Figure
transaction. As shown in
of
length
the
y
specif
to
used
are
but
sing,
are not used for addres
As stated
longword, gquadword, oOr octaword.
the transaction:

previously,
data.

is an

only

longword

transactions

are used to transfer I/0

Thus, only a longword length 1is specified when

address

the

I/0 address.

ses,
Because data is transferred to/from naturally aligned addresicant
some number of the low-order address bits are not signif
depending upon the transaction type.

not
are
For longword transactions, the two low-order bits
a word or
significant except when the transaction is directed to
(A longword transaction 1is wused to
byte-oriented I/0 device.
address these devices because there is no specific word or byte
to
transaction type.) Word and byte references are made only
to
cted
restri
are
and
r
adapte
an
h
throug
buses
devices on other
node window space.

Multilongword write transfers are not wrapped, so the three
low-order address bits of write guadword transactions and the four
low-order address bits of write octaword transactions are not
However, multilongword read transactions may Dbe
significant.
wrapped. Thus, the address must specify the first longword to be
transferred and only the two low-order address bits are not
significant.

ADDRESS(HEX)

0000

1/0 SPACE

0000

2000 0000

NODE 0 REG SPACE

2000 1FFF
2000
VAXBI

MEMORY
SPACE

(512

2000

2000 3FFF
2000

MB)

4000

NODE 2

2000 5FFF
2000

6000

2000

7FFF

NODE 4 REG SPACE

21FF

FFFF

2200

0000

(8KB)

(32

(8KB)

MB)

2001 E000

RESERVED FOR
MULTIPLE VAXBI
SYSTEMS
(480

NODE 5 REG SPACE

2000 BFFF

1/0 SPACE

2001

FFFF

2002

0000

:
NODE 15 REG SPACE

2003

FFFF

203F FFFF
2040

(8KE)

MULTICAST

SPACE

RESERVED

2004 0000

MB)

REG SPACE

(8KB)

2000 A000

FFFF

REG SPACE

(8KB)

2000 9FFF
1FFF

REG SPACE

(8KB)

NODE 3

2000 8000

2000 0000

(8KB)

NODE 1

ADDRESS(HEX)

0000

(3.75 MB)
ADAPTER WINDOW
SPACE
#0

(258KE)
))

2043 FFFF

(128KB)

NODE PRIVATE SPACE

207C 0000

ADAPTER WINDOW
SPACE #15

207F FFFF
2080

3FFF

NOTE:

VAXBI

FFFF

RESERVED

21FF FFFF

(24 MB)

MEMORY SPACE

IN A VAX 8800 SYSTEM IS THE SYSTEM’'S MAIN
MEMORY
EXCEPT FOR ANY MEMORY SPACE ALLOCATED TO AN
PROCESSOR'S VAXBI MEMORY NODE.

SPACE (ON
/O

(256KB)

0000

THE NMI)

SCLD-426

Figure

2-4

VAXB1

2-13

Address

Space

ADDRESS (HEX)
[SEE NOTE]

bb + 00
VAXB!
bb

REQUIRED REGISTERS

BIIC CSR SPACE

(256

BIIC

bb +

SPECIFIC

REGISTERS

REMAINDER OF 8 KB NODE

FOR USER CSR REGISTERS
(NOT IMPLEMENTED IN BIIC)

NOTE:

BYTES)

bb = BASE ADDRESS = 2000 0000 (HEX) + 2000 (HEX) X NODE ID
SCLD-144

Figure

2-5

VAXBI

Node

11 2-14

Space

ADDRESS (HEX)

[SEE

NOTE]
31

04 | VAXBI

CONTROL/STATUS

BUS ERROR REGISTER

bb + 0C
bb +

NOTE:

DEVICE

ERROR INTERRUPT CONTROL

DESTINATION

BASE ADDRESS = 2000

0000

(HEX)

+ 2000

(HEX)

X NODE ID

SCLD-145

Figure

2-6

VAXBI

Required

2-15

Registers

ADDRESS (HEX)
(SEE NOTE]

bb + 14

IPINTR MASK REGISTER

bb + 18

IPINTR/STOP DESTINATION REGISTER

bb +

IPINTR

+ 20

STARTING

SOURCE REGISTER

ADDRESS REGISTER

bb + 24

ENDING ADDRESS REGISTER

bb + 28

BC! CONTROL REGISTER

WRITE STATUS REGISTER

+ 2C

bb + 30
bb

FORCE IPINTR/STOP COMMAND REGISTER

+ 34

UNUSED

bb + 38

UNUSED

bb + 3C

UNUSED

bb + 40

USER INTERRUPT CONTROL REGISTER

+ 44
=

UNUSED

eb + FO

GENERAL-PURPCSE REGISTER ©

GENERAL-PURPOSE REGISTER

bb + F8

GENERAL-PURPOSE REGISTER 2

GENERAL-PURPOSE REGISTER 3

NOTE:

BASE ADDRESS = 2000 0000 (HEX)

+ 2000 (HEX)

X NODE ID
SCLD-148

Figure

2-7

BIIC-Specific

11 2-16

Device

Registers

READ/WRITE
31

LONGWORD (TO

30 28

LONGWORD (TO

WORD-ORIENTED

ADDRESS BITS

DEVICE,

WINDOW SPACE ONLY)

LNG

SIGNIFICANT

READ/WRITE
31

WINDOW SPACE ONLY)
00

SIGNIFICANT

READ/WRITE
30

DEVICE,

)

LNG

BYTE-ORIENTED

LONGWORD,

READ QUADWORD,

ADDRESS BITS

READ OCTAWORD

30 29

LNG

SIGNIFICANT

ADDRESS BITS

WRITE QUADWORD
31

30 29

LNG

SIGNIFICANT

ADDRESS BITS

MBZ (SEE NOTE)——J

WRITE QUADWORD
31

30 29

LNG

SIGNIFICANT ADDRESS BITS

MBZ (SEE NOTE)‘—|
NOTES:
1.

INDICATES

HOWEVER,

BIT

<02>

NOT SIGNIFICANT

WRITE

AND SHOULD BE IGNORED BY SLAVE.
QUADWORD ADDRESS AND BITS <03:02> IN WRITE

OCTAWORD ADDRESS MUST BE ZERO(MBZ)
2.

BITS

<31>

AND

<30>

SPECIFY

<31:30>

LENGTH

TO PREVENT WRAPPED WRITES
OF

SOME NODES.

DATA TRANSFER.

DATA LENGTH

RESERVED CODE

LONGWORD
QUADWORD

10
11

OCTAWORD

SCLD-183

Figure

2-8

VAXBI

Read/Write

2-17

Address

Bits

2,5

BASIC

VAXBI

TRANSACTION

All

VAXBI

transactions

embedded

cycle.

Refer

FORMAT

consist

Figure

slave

(or

slave(s),

CYCLE

specify

the

30-bit

this

Embedded

arbitration
be

asserts

one

may

Also,

the

during

the

Section

the

information

also

its

line

the

one

data

...
..

the

busy).

corresponding

the

other
(D)

selection
lines.

transmits

length

4-bit

For

read/write

code

along

1lines.
data

a
the

size

with

discussed
(longword,

transaction.

second

use

bus,

request
its

high
lines

lines.

2-18

2.11.

VAXBI

every

for

arbitration

opportunity

lines

the

cycle

additional

high-order

select
select

Cycle

provides

the

data

1lines.

2-bit

read/write

cycle

bus

(I)

the

etc.),

specifies

the

must

type.

address
mask

transmits

code
of

embedded

node

followed

least

Format

master

command

write,

address

cycle
the

DATA

bus

the

(read,

low-order

one

transmits

the

read/write

Arbitration

(when

cycle,

type

length

This

cycle

CYCLE(S)

Transaction

destination

arbitration

transaction.

VAXBI

specify

a
a

octaword)

embedded

node

and

read/write

previously,

2.5.2

types,

Cycle

command

code

quadword,

Basic

transmits
such

transaction

The

2-9

slaves)

command

the

ARBITRATION

command/address

information

followed

EMBEDDED

Command/Address
the

command/address

COMMAND/

Figure

2.5.1

cycle

2-9.

ADDRESS

During

arbitration

node

ID.

priority

the

The

low

priority

cycle,

the

current

arbitration

line

may

request)

Bus

bus

request).
bus

master

discussed

2.5.3
For

Data

Cycles

single-responder

slave),
cycle

the

data

transfer

slave

over

broadcast
than

master

2.5.4
Odd

the

Bus

the

transmitted.
for

bus

(including
(even)

The

the

This

and

also

parity

cycle,

The
but
this

transmits

(CNF)

responding

arbitration

the

master

transferred

the

(more

multiresponder

data

cycle,

and

for

transaction

other

During

is
as

response

1lines.

generated

when
bit

actually

all

data

code

the

errors

the

will

the

data

being

checked

(or
on

cycle,

and

respond

transaction.

detected

generation
and
following sections.

during
checking

vector)

the

parity

lines.

during
is

generated

error
a

embedded

all

flag

parity

the

transaction
data

for

embedded

command/address

checked

all

line.

generated.

during

data

During

the

2-19

the

during

parity

not

during

and

and each node sets
an
detected.
Nodes detecting

cycle

VAXBI

master)

parity

the

cycles

asserted

the

I-line

arbitration

read/write

arbitration

both

only

checked

generates the parity bit
arbitration
cycles.
Parity

aborts

Parity

the

embedded

command/address

parity

also

slave).

master

embedded

between

one

embedded

multiresponder

embedded

transactions

information

arbitration
The

than

the

Parity

transactions.

the

lines.

confirmation

data

cycle,

slave(s)

is
generated
command/address
and

Except

data

parity

cycles

vector)

Write

which
a

responding

(or

(never

following

responding

contain
over

cycles

1lines.

possible

transferred

bus

transaction,

one

read/write

the

transactions

Cycles,

transactions

cycle

error

and
nodes

if
in

bad
the

command/address.

1is

not

aborted

arbitration

cycles

cycle.

discussed

2.6

READ/WRITE TRANSACTIONS

Examples of write type and read type transactions are shown in
Except for data length (octaword in the
2-10 and 2-11.
Figures
examples), all write transaction formats are basically the same and
A write
all read transaction formats are basically the same.
a
intent,
cache
with
write
a
write,
normal
a
be
may
n
transactio
(with cache intent), or an unlock write masked (with
write masked
a read
read,
normal
A read transaction may be a
cache intent).
with cache intent, or an interlocked read

(with cache intent).

and
command/address
the
following
cycles
number of data
The
depends
transaction
read
or
write
a
of
cycles
arbitration
embedded
also depends upon whether
It
upon the length of the transfer.
(refer to Sections 2.6.4 and
retry
a
or
stalls
any
there are
required for an octaword
are
cycles
data
four
of
A minimum
2.6.5).
transfer requires a
quadword
a
ngly,
Correspondi
data transfer.
a
requires
transfer
longword
a
and
cycles
data
two
of
minimum
minimum of

one.

Data Cycles

2.6.1 Write

master
bus
the
transaction,
a write
During each data cycle of
and
lines
D
the
on
slave
selected
the
to
data
write
the
transmits

transmits a 4-bit byte mask on the I lines if the write transaction
(The byte mask indicates which byte or bytes in
is a masked write.
also
the longword of write data are to be written.) The bus master
The
the D and I lines on the PO line.
for
parity
odd
transmits
errors)
no
detected
has
it
if
and
ready
is
it
(if
slave
selected
and transmits an acknowledgment (ACK) code
the write data
takes

also
1s
response
ACK
An
lines.
back to the master on the CNF
the slave for the two cycles following the last data
by
generated
the
executing
detected when
cycle to indicate that no error was
transaction.

slave
the
by
detected
1is
error)
If an error (such as a parity
a data cycle, it asserts no CNF lines {(a NO ACK response)
during

at
for
and
transaction
the
during any remaining data cycles in
The NO ACK
cycle.
data
1last
the
following
<cycles
two
least
the
terminate
response causes the master to set an error flag and
transaction.

Read

2.6.2

Data Cycles

During each data cycle of a read transaction,

(if

ready

the

selected

slave

and if it has detected no errors) transmits the

ACK
an
read data back to the master on the D lines, together with
It also transmits a read data status
CNF lines.
the
on
response
on
bit
code on the I lines as well as the D and I-line odd parity
the

line.

2-20

VAXBI

CYCLE

C/A

DATA

LENGTH
<31:30>

LEGEND
—_—

M =
S =

AN =

IDDEC,D

AAN

ALL
=

NODES

’%BEQRB ING

LOW

C/A = COMMAND/

<31:16>

IA =

PRIOR

D<31:00>

MASTER
SLAVE

30-BIT

WRITE | WRITE | WRITE | WRITE

fggfln\

DATA | DATA

DATA

BYTE
MASK

ADDRESS CYCLE

IMBEDDED ARB
CYCLE

DEC'D
ID
HIGH
PRIOR

<15:00>

MASK FIELD

SOURCE
1<3:0>

SOURCE

AAN

WRITE
CMD

| MASTER |
ID

GEN

BYTE |
MASK |

CHK

ACK

M,S

M,AAN

M.S

M,S

BSY L

NO ARB L

UNDEFINED
NOT MASKED WRITE.

SOURCE

CNF<2:0>

NOTES:

ACK

ACK
S

ACK
s

AN ASTERISK

(*) INDICATES SLAVE MAY STALL (GIVE STALL RESPONSE)
FOR ONE OR MORE BUSY CYCLES BEFORE TAKING DATA (ACK RESPONSE)

A DOUBLE ASTERISK

TRANSACTION

(GIVE

INDICATES SLAVE
RETRY RESPONSE).

(**)

MAY REQUEST RETRY OF

SCLD-185

Figure

2-10

VAXBI

Write

Transaction

2-21

(Octaword

Length)

C/A

VAXBI CYCLE

DATA

DATA
LEGEND

LENGTH

<31:30>

M = MASTER
S = SLAVE

AN = ALL NODES

AAN = il\&l_(lslleé_RB ING

IDDEC,D
LOW

C/A = COMMAND/

<31:16>

IA =

PRIOR

READ
READ | READ
DATA | DATA | DATA

30-BIT
ADDR

D<31:00>

<29:00>

SOURCE
1<3:0>

SOURCE
PO

GEN
CHK

AAN

MASTER
ID

READ
STAT

CNF<2:0>

READ
READ
STAT | STAT

CYCLE

S
READ
STAT
S

ACK

M.,S

M,S

SOURCE

IMBEDDED ARB

DEC'D
ID
HIGH
PRIOR
<15:00>

READ
CMD
M

READ
DATA

ADDRESS CYCLE

ACK

BSY L

//,————fl\\?,AAN

NOC ARB L

NOTES:

44//fi#7

AN ASTERISK (*) INDICATES SLAVE MAY STALL (GIVE STALL RESPONSE)
FOR ONE OR MORE BUSY CYCLES BEFORE TAKING DATA (ACK RESPONSE).
A DOUBLE ASTERISK (**) INDICATES SLAVE MAY REQUEST RETRY OF
TRANSACTION (GIVE RETRY RESPONSE).

SCLD-186

Figure

2-11

VAXBI Read Transaction (Octaword Length)

The

status

code

corrected,
DATA

SUBSTITUTE

1limit

systems,

code

the
the

indicates

uncorrectable
causes

caching

status

the

and

code

the

(READ

data

DATA

master

subsequent

indicates

the

(this

the

write,

time

detected

error

when

an
an

2.6.3
If

error
error

Nonexistent

there

first
the

master
NO

ACK

and

ends

read

The
the

not

some

the

CNF

1lines

the

last

data

cycle

after

error

parity

ACK

for

the

ACK

cycles

condition

response

error,

causing

write,

data

slave

read

causes

example)
to

response

set

the

transaction

the

master

transaction.

Addresses

the

during

data

cycle,

the

master

sets

transaction.

slave

during

any

not

data

ready

cycle,

to
it

lines.

During
lines
For

transmitted

execution

the

data

Also,

ACK

response

selected
data

stall

continues

data

until
a

read

until

the

slave.

slave

for
the

takes

transaction,

the

has

error

cycles

transmit

the

state)

after)
end

read

data

error

Stalls

the

CNF

and

the

flag.)

READ

cycles

error

for

error

but

flag

2.6.4

not

wvalid

code).

response (no
responding
slaves)
during
the
a read or write transaction, it probably indicates
transmitted a nonexistent memory or I/0 address.
As for

cycle

any

transaction

condition.
flag

is
two

set

successfully.

that

Also,

(and

for

completed

during

flag.

during

response

indicates

was

set

ACK

master)

transaction

master

slave

an
the

valid,

invalidation

cached.

SUBSTITUTE

flag,

stalled

the
the

lines

and

128

generates

and

2-23

transaction.

ACK

or
code

the

master

write

STALL

data

undefined

response

consecutive
a

data
STALL

generates

are

ACK

transaction,

longword

data

write

assert

write

same

data

generate

accept
can

ACK
(may

are

and

the

response.
be

any

transmitted

responses,

response,

return

sets

ends

the

2.6.5

Retries

A selected slave not ready to accept write data or send
read
data
may
not
Just
stall.
It
may also cause the master to retry the
transaction.
A

slave

may

cause

etry

the

first

cyc
ycle e

data

or
or

following
follo

stall
data
cycle
if no data has previously -been transferred) by
transmitting a RETRY response on the CNF lines.
The master, or the
slave following a stall data cycle, then ends the transaction.
The

master can retry the transaction after arbitrating

again

for

the

bus.
If a slave causes a transaction
master sets an error flag.

4096

times,

the

2.7

BROADCAST

retried

TRANSACTIONS

The broadcast transaction, not currently
wused
during
normal
bus
operation,
allows
more than one node to be written at a time.
It
provides a means of announcing events to a number of nodes
without
using

interrupt

Format

for

the

requests.
broadcast

:
transaction

shown

Figure

2-12.

octaword
data
1length
1is
shown.
The transaction is similar to a
write, except that the
bus
master
transmits
no
memory
or
I/O
address
on the D lines during the command/address cycle.
Instead,
it transmits a destination mask on the 16 low-order D lines.
The D
lines
asserted
correspond
to
the
node
1IDs of the slaves to be
selected.

During

each

slave

must

response

data

cycle

generate

during

data

broadcast

ACK

cycle

(or

last

data

c¢ycle)

causes

the

write

transaction.

Unlike

can

respond

retry
£V

.L_Lclg

of
s

the
s

the

LeoecociveD

—~

and

TYDOYMMD7

ARN1L

2-24

the

single

transaction.
NMAT

during

master

write,

master,

broadcast

transaction,

response

two

set

because

slave

the

Lt:'bb)ullbt::.

1least

lines.

cycles

error

cannot

Thus,
T

CNF

than

stall

master

after

flag

the

during

one
or

sets

one

NO ACK

cause
an

slave
a

error

VAXBi

CYCLE

C/A

DATA

LENGTH

LEGEND

<31:30>

——

M = MASTER

DEC'D

WRITE | WRITE | WRITE | WRITE

MASK

AAN

CMD
M

gfi

ID
M

CNF<2:0>

SOURCE

| DATA

DATA

C/A =

COMMAND/

IMBEDDED ARB
YCLE

ADDRESS CYCLE

cve

PRIOR

| <15:00>

BDCST | MASTER

SOURCE

NODES

DEC’D
ID
HIGH

<15:00>

SOURCE
1<3:0>

ALL

NODES

DATA

BDCST

= SLAVE OR SLAVES

AN =

AAN= ALL ARB'ING

RES'D
LOW
FIELD
PRIOR
<29:16> | <31:16>

D<31:00>

S(S)

BSY L

NO ARB L

M,AAN
//r__fi\\,

M
BYTE |

BYTE

MASK | MASK
M
M

MASK
M

S(8S)

S(S)

ACK
S(S)

ACK
ACK
S(S) | S(S)

V4
SCLD-187

Figure

2-12

VAXBI

Broadcast

(BDCST)

2-25

Transaction

(Octaword

Length)

2.8
The

INVALIDATE

TRANSACTIONS

invalidate

transaction

(Figure

2-13)

allows

a processor

node

signal other nodes that they may have cached data that is no longer
valid.
The bus master transmits the address and data length of the
invalid
block of data in the command/address cycle.
More than one
slave may respond with an ACK response on the CNF lines during
the
transaction's
and parity is
is

response

single data cycle.
(No
not generated or checked
by

any

node,

error

data is actually transferred
during this cycle.) If there

flag

set

the

master.

The invalidate transaction is not used on a VAXBI in
Any
processor
nodes
must
have their caches turned
previously.
This is because the addresses of
memory

this
system.
off as stated
transactions

local

the

caches

VAXBI

(if

turned

NMI

are

on)

not

could

passed

contain

11 2-26

the

VAXBI;

invalid

data.

thus,

the

VAXB!

CYCLE

C/A

LENGTH

<31:30>

LEGEND
M =

MASTER

S(S)

= SLAVE OR SLAVES
AN = ALL NODES

IDDECD

AAN =

ALL ARB'ING

PRIOR

C/A

COMMAND/

LOW

30-BIT

| <31:16>

<29:00>

NODES

ADDRESS

ADDR

D<31:00>

RESV'D

FIELD

CYCLE

IMBEDDED ARB

CYCLE

DEC'D
ID
HIGH
PRIOR

<15:00>

SOURCE
1<3:0>

M
INVAL

SOURCE

GEN

CHK

CMD

AAN
MASTER | RESV'D

FIELD

M
AN

RESV'D
FIELD

M
AN

CNF<2:0>

SOURCE

S(S)

VAXBI

BSY

VAXBI

NO ARB L

SCLD-188

Figure

2-13

VAXBI

Invalidate

2-27

(INVAL)

Transaction

2.9 INTERRUPT OPERATION (INTR, IDENT, AND IPINTR TRANSACTIONS)
The interrupt (INTR) and identify (IDENT) transactions are used to
signal and service conventional device type interrupts on the
That is, a node can send an interrupt

VAXBI.

request

one

(As for the NMI, there are
more nodes using the INTR transaction.
four request priority levels; BR4, 5, 6, and 7.} Then, when an
interrupt fielding node is ready to service the interrupt requests

at a specific request level, it uses an IDENT transaction to read
an 1interrupt vector from the interrupting node. Because more than
one node may be interrupting at that request level, the vector 1is
read from the highest priority device based on the node ID.

The VAXBI also allows one processor node to interrupt another
This 1is done using the interprocessor interrupt
processor node.
(IPINTR) transaction. Transaction format is similar to the INTR
However, there 1is no need for a node responding to
transaction.
the interrupt request to follow with an IDENT transaction. This is
because the interrupt fielding node stores the vector (and also the
request level) information for this type of interrupt.

The interrupt fielding nodes on a VAXBI in the system are the NBI
and any I/0 processors that are installed. The NBI node services
INTR transactions by passing the interrupt requests on to the NMI
It then issues an IDENT transaction to
and the primary CPU.
collect the vector information when the primary CPU reads an NBI

vector

(There are four vector registers in

the NBI, one for each request level.) The interrupt requests
generated on the VAXBI are normally from I/0 device nodes but may
also be from an 1/0 processor node.

The

NBI

can

also

field

IPINTR

transactions

allowing

1/0

processor to interrupt the primary CPU using an interprocessor
(An I/O processor can also interrupt another
interrupt request.
I/0 processor using an IPINTR.) Not only can the NBI field an
It can also generate an INTR,
IPINTR, it can generate one.
allowing the primary CPU to interrupt an 1/0 processor with either
type of

interrupt

request.

2-28

2.9.1

Interrupt

Format

the

for

(INTR)
INTR

bit

VAXBI,

the

16-bit

the

mask

allowing

interrupt.

I/0

The

also

the

master

For

example,

bit

for

that

data

each

node,

level

for

than

one

request

I/O

device

same

attached

time

and

different

one

request

ready)

Requests

level

service

other

levels

transaction.

the

During

the

service

the

lines.
data

below.

This

single
the

error

both

have

request

XX1X

BR5
BR4

cycle
request

essentially

responds

flag.

2-29

master

(More

When

fielding

than
at

more
node

request

using

(an

the
than

(when

only.

another

INTR

command/address

and

Priority)

the

selected

the

There

Level

ACK

command

between

four

interrupting

again

(Lowest

asserts

and

cycle.

levels.)

(Highest

any

the

field

NBI

request

priority

made

following

cycles,

interrupt

Request

XXX1

allows

the

transaction.
can

highest

BR7

slave

signal

Each

nodes

slaves

interrupt

INTR

the

BR6

transferred

This
an

adapter

specified,

data

make

1XXX

interrupt

being

slave(s).
sets

single

Oor

lines.

possible

request level
command/address

shown

X1XX

arbitration

one

interrupt

D<19:16>

embedded

node)

one

assigned

will

During

low-order

the

2-14.

interrupting

the

during

with

Figure

(the

the master may
interrupting.

example)

one

select

the

lines

shown

master

mask

the

destination

transmits

high-order

adapter

cycle,

corresponds

processor

master

the

Transactions

transaction

command/address

transmits

the

slave

that

response

confirmation
master

ACK

and

intends

the

CNF

cycle
the

response),

with no
selected

the

master

C/A

VAXBI CYCLE

LEGEND
MASTER

M =

S(S) = SLAVE OR SLAVES

AN = ALL NODES

RESV'D

DEC'D
FIELD || ID

<31:20>

LOW

PRIOR

<31:16>

ALL ARB’ING

C/A =

COMMAND/

INTR
LEVEL

D<31:00>

AAN =

NODES

ADDRESS CYCLE

IMBEDDED ARB

CYCLE

RESV'D

<19:16>

FIELD

INTR

DEST

MASK

<15:00>|

SOURCE

M
INTR

1<3:0>

SOURCE

GEN

CHK

CMD
M

DEC'D

HIGH

PRIOR

<15:00>

AAN
MASTER | RESV'D

FIELD

RESV'D

FIELD

S(S)

SOURCE

VAXB! BSY L

/—

M,AAN

NO ARB L

SNl
SCLD-189

)
&

VAXBI Interrupt (INTR) Transaction

[\®)

Figure 2-14

VAXB!

2.9.2
As

Identify

stated

INTR

(IDENT)

previously,

transaction

vector.

IDENT

During

the

format

the

high-order

information
asserted.

level

does
is

interrupt

fielding

transaction

IDENT

shown

command/address

transaction,

the

Transactions
an

master

cycle

1lines.

line

and

asserted

only

the

cycle

arbitration

high-order
node

0010

BR5

0001

BR4

following

master

lines.

Only

the

16)

will

fielding

the

specified

doing

the

IDENT.

During

the

next
by

arbitrating

IDs

are

must

arbitrate

is,

only

vector

the
on

this

transmitted

one
the

because

node

bus

(Lowest

the

bus,

cycle

The

and

the

high-order

may

become

Nodes

interrupt

serviced

request

IDENT

not

the

slave

2-31

return

can

the

when

decoded

The

nodes
That

unless

made.

IDENT.

arbitration

transaction)

request

the

the
one

interrupt

bus

lines.)

interrupt

(However,
by

than

wanting

data

and

the

master's

service

the

serviced

winning

(INTR

before

embedded
on

the

with

nodes

2.11).

one

want

(Section

request

transmission

master

only

nodes
not

and

decoded

for

only

should

Priority)

can

may

IDENT,

lines

select

interrupt

corresponding

level

only

Priority)

its

there

the

INTR
four

Level

arbitrate

another

four

must

may

master.

the

single

asserted.

cycle

(Highest

line

request

master

become

of
the

transmits

because

node

bus

the

necessary

interrupt

service

to
level

one

2-15.

command/address

the

pending

node

the

cycle,

(plus

master's

BR7

interrupt

similar

Request

BR6

interrupt

serviced.

1000

read

the

specifies

0100

responding

and

However,

D<19:16>

During

Figure

transmits

transmitted
The

node

interrupt
must

they

make

are

After winning the bus, the slave (if it is ready)
asserts
an
ACK
response
on
the CNF lines and transmits the vector on the D lines
during the next bus cycle.
At the
same
time,
and
1like
a
read
transaction, the slave transmits a data status code on the I lines,
and it transmits D and I-line parity on the PO line.
(A READ
DATA
SUBSTITUTE
status
code
causes
the master to set an error flag.)
Also, similar to a read transaction, the slave may transmit a STALL
response
on
the
CNF lines for one more cycle until the vector is
ready to transmit.
(An adapter node would do this
1if
the
vector
had to be first read from an attached I/0O device.) Again, 128 stall
cycles
<cause
the
slave
to
set
an
error
flag
and
end
the
transaction.
Once
the
vector
1is
sent
by the slave ending the

transaction, the master transmits an ACK response on the CNF
lines
for
the
next
two
bus
cycles
if
the
transaction was executed
correctly.
If not (a parity error
detected
by
the
master,
for
example),
a
NO ACK response causes an error flag to be set in the
slave.

A slave serviced by an
IDENT
previous
interrupt
request.
occurred just before it could

may
not
necessarily
have
made
a
The
interrupt
condition
may have
arbitrate for the bus and transmit an

INTR transaction.
For this reason, a node cannot arbitrate
bus to do an INTR during the
embedded
arbitration
cycle
IDENT.
it

may

It
win

may
the

would

then

been

serviced.

A NO ACK
is
not

win

the

bus

following

have

and

become

arbitration

abort

the

INTR

pending

for

bus

service

because

the

master,
the

request

for
of

the
the

and

then

IDENT.

had

already

response occurring during (not after) an IDENT transaction
an
error
condition.
This can happen if the IDENT is the

result

interrupt

node,

and

the

request

reguest
has

than

already

been

serviced

i1 2-32

one

interrupt

fielding

node.

another

VAXB!

CYCLE

C/A

INTR
ARB

DMID

DATA

LEGEND
M =
S =
,

RESV'D
FIELD

<31:20> | ID
DEC'D

DEC'D

LOW

PRIOR

| |ID
DECD

|ID

SLAVES

ADDRESS CYCLE

LEVEL

<19:16>

<15:00>{

SOURCE
1<3:0>

AAN

IDENT
D

<15:00> | <15:00>{

FIELD

SOURCE
Po

GEN
CHK

<15:00>

| STATUS

RESV'D

NOTE:

N,AAN

A NO ACK BY SLAVE

A VALID

M,S

M,S/

M,S

M.S

ALSO,

SLAVE MAY STALL (GIVE
BUS CYCLES BEFORE RETURNING

STALL

RESPONSE)

VECTOR (ACK

ACK

RESPONSE INDICATING

INTERRUPT HAS BEEN SERVICED

VECTOR DATA

/
NO ACK
S

INTERRUPT OR THE

IF ACK RESPONSE
CYCLE

FIELD

SOURCE

NO ARB

(VAXBI NODE)
(OFFSETABLE DEVICE)

'\s"I

ACK/

ARB

)

CNF<2:0>

BSY L

CYGLE

IMBEDDED

RESV'D | VECTOR

| FIELD

A,fi"s

0'S

APS

| MASTER | RESV'D|

NODES

C/A = COMMANDy

[<31:16>|<31:16>

DEC'D
ID
RESV'D | HIGH
FIELD | PRIOR

ALL

APS = SLAVES
ALL POTENTIAL

D<31:00>

AAN= NODES
ALL ARB’ING

MASTER |ARB'ING|

<31:16>

MASTER
SLAVE

A TRANSIENT

BY ANOTHER NODE.
FOR ONE OR MORE

RESPONSE).
SCLD-18¢C

Figure

2-15

VAXBI

Identify

2-33

(IDENT)

Transaction

2.9.3 Interprocessor Interrupt (IPINTR) Transaction

The format for the IPINTR transaction (Figure 2-16) differs from
the INTR transaction only in the selection information transmitted
by the master in the command/address cycle. A destination mask is
transmitted on the low-order D lines, but no interrupt level is
This is because the
transmitted on the high-order D lines.
the interrupt request
holds
slave)
(the
interrupt fielding node
transmitted on the
1is
ID
decoded
s
level. Instead, the master'
an IDENT. This is
of
cycle
third
the
high-order D 1lines as in
accept
to
enabled
be
not
necessary because a slave may
interprocessor interrupt requests from the current master.

As for the INTR, the single data cycle following the embedded
(No
arbitration cycle is essentially a command confirmation cycle.
slave
one
least
At
slave.)
and
master
data is transferred between
must respond with an ACK during the cycle or an error flag is set
in

the

master.

2-34

VAXBI

CYCLE

C/A

LEGEND

MASTER | DEC’D
DEC'D
|ID

M = MASTER
S(S) = SLAVE

Bies | FNGR

<31:16>

D<31:00>

AAN

RESV'D
FIELD

P
INTR
DEST
MASK

OR SLAVES

AN = ALL NODES
=

ALL

ARB’ING

NODES

C/A =

COMMAND/
ADDRESS CYCLE

iIA

IMBEDDED ARB
CYCLE

DEC’D
)
HIGH

<15:00> | PRIOR
<15:00>

SOURCE

1<3:0>

AAN

IPINTR | MASTER | RESV'D

SOURCE

CMD

GEN

CHK

FIELD

RESV'D

FIELD

SOURCE

VAXBI BSY L
VAXB!I

NO ARB L

S(S)

M, AAN

SCLD-191

Figure

2-16

VAXBI

Interprocessor

2-35

Interrupt

(IPINTR)

Transaction

2.10

STOP TRANSACTIONS

The STOP transaction is used to force nodes to a state where they
cannot issue any more VAXBI transactions while retaining as much
nodes
However,
error and other status information as possible.
must still be able to respond to VAXBI transactions so that the
retained status information can be examined by another node.
A processor node can use the STOP transaction to first stop all bus
It can then read status
activity after an error condition.
logging or diagnostic
error
for
nodes
more
or
one
in
registers
operation by forcing a
normal
to
returned
be
can
node
A
purposes.
by the BIIC
generated
is
indication
LO
DC
(A
operation.
selftest
)
node.
the
s
initialize
which
sequence,
selftest
the
during
STOP transaction format (Figure 2-17) is similar to INTR and IPINTR
format, except that the master transmits only a destination mask on
More than one slave
the D lines during the command/address cycle.
be addressed and at least one must generate an ACK response on
may

Like the INTR and
the CNF lines or the master sets an error flag.
1in the single data cycle
1is generated
the response
IPINTR,
1is actually
(No data
following the embedded arbitration cycle.
transferred over the D lines in this cycle.)

If a responding slave cannot enter STOP mode by the end of the
an ACK
still generates
it
single data cycle,
transaction's
it must
However, until the STOP sequence is complete,
response.

either

hold

the

bus (by asserting BSY) or it must generate RETRY

to
and NO ACK responses
responses to single-responder commands
Section
in
discussed
is
signal
BSY
(The
commands.
der
multirespon
2.11.)

2-36

VAXBI

CYCLE

C/A

A
LEGEND
,

M =

RESV'D | DEC'D

FIELD

PRIOR

AAN

<31:16>

C/A =

<31:00> | LOW

RESV'D
D<31:00>

FIELD

INTR
DEST
MASK
<15:00> |

DEC'D
ID
HIGH
PRIOR
<15:00>

AAN

SOURCE
1<3:0>

STOP

SOURCE

CMD
M

GEN

CHK

ALL NODES
ALL

ARB’ING

COMMAND/

ID
M

IMBEDDED ARB

CYCLE

FIELD

RESV'D

FIELD

CNF<2:0>

ACK

SOURCE

S(S)

VAXBI BSY L

VAXB! NO ARB L

/x/

/
M,AAN

SCLD-192

Figure

2-17

VAXBI

2-37

STOP

NODES

ADDRESS CYCLE

| MASTER | RESV'D

MASTER

S(S) = SLAVE OR SLAVES

Transaction

2.11

BUS

ARBITRATION

AND

CONTROL

A node may request the bus during any bus cycle
when
the
bus
is
inactive.
It
may
also
request
the
bus
during
the
embedded
arbitration cycle of any VAXBI transaction when the
bus
1is
busy.
Each
requesting
node
monitors
all
requests
(distributed
arbitration), and if it has the highest priority,
assumes
control
of
the
bus as bus master, either in the next cycle (when there is
no

transaction

progress)

transaction.
When
arbitration cycle of
pending

bus

current

2.11.1

master

transaction

Bus

the

end

the

current

a
node
wins
the
bus
during
the
embedded
the current
transaction,
it
is
called
the
until

assumes

control

the

bus

when

the

ends.

Reguests

Nodes request use of the bus by asserting a D line that corresponds
to
its node ID.
As shown in Figure 2-18, the line asserted may be
one of the 16 high-order lines or one of the
16
low-order
lines.
The
1low-order
1lines
are
high priority requests.
The high-order
lines are low priority requests.
Within each group of high or
low
priority
requests,
the node with the lowest ID (lowest numbered D
line asserted) has the
highest
priority.
Of
course,
any
high
priority request always has a higher priority than any low priority
request.

VAXB!

LINES

NODE

16 15

DATA

[

LOW PRIORITY

[

REQUEST LINES

0 15

[

HIGH

PRIORITY

REQUEST LINES

[

PRIORITY

» HIGHER
LOWER 4—

NOTE:

NODE ASSERTS EITHER A HIGH OR LOW REQUEST LINE TO ARBITRATE FOR VAXBI.
SCLD-193

Figure

2-18

Bus

Arbitration

Request

Lines

2.11.2

Arbitration

Whether

line

node

depends

round

Fixed

high

Fixed

low

are

mode,

the

than

does.

All

nodes

the

some

all
1in

assert

its

access

operate

dual

fixed

two

bus

ARB

1is

the

bus

2-19.
NO ARB

asserted

various

current

times

during

any

1length,

cycles.

Null

the

mode

bus

embedded

assures

requires
mode.

cycles

last

the

bus

programmed

That

is,

will

requesting

programming
low-priority

any

VAXBI

node

always

the

other

(only

can

and

seen,

BSY.

nodes
and

requesting
pending

bus

(as

bus.

nodes

requests

described

arbitration

the

depending

(no

bus

data
bus

arbitration

bus.

masters

upon

and

the

and the responses generated.
The
always asserted
except
during
the

pending

cycle

access

line.

which

can

when

priority)

master,

equal

mode.
request

priority

arbitration

rapid

1line

transaction

Command/address
The

(higher

low

mode

progress)

its

enhanced

asserted

the

priority

lower

request

round-robin

high

asserts

applications,

further

dual

its

will

Control

for

signals,

node

low-priority

Figure

type,
1its
that NO ARB

the
during

high-priority

Arbitration

shown

real-time

may

has

round-robin

high-priority

arbitration

asserts

time,

lines

nodes.

asserted).

2.11.3
The

operate

node

master

other
ID

fixed

Also,

the

special

operate

bus

any

transaction.

average,

for

requesting

the

bus

priority

store

asserted

priority

robin

programmed

low

modes.

priority

normally

only

its high priority line or
its
arbitration mode.
There are three

the

Dual

this

the

Modes

asserts

Nodes
In

the

above)

controlled

1is

the

slave

also
at

transaction

net result is
following
bus

transaction

cycles

cycle

master

transactions

2-39

unless

there

|
m

O
m

<+
INO ARB

l NO ARB * REQ
WIN A

BSY

CYCLE

—LOSE

ARB

WIN » BSY

PENDING
MASTER

lBSY

BSY

[€—

MASTER

[¢

SCLD-194

Figure

2-19

Arbitration State Diagram

a
during
slave
and
current master
BSY is asserted only by the
The master asserts BSY during the command/address and
transaction.
assert
Both the master and slave can
embedded arbitration cycles.
BSY can also be
BSY during data cycles as for the NO ACK signal.
during
asserted to extend a transaction and, together with NO ARB,
the
during
asserted
not
is
BSY
well.
as
functions
mode
special
bus

cycles.

Null

cycles

Arbitration

fcllowing

cycles

(when

there

1is

transaction

1in

progress)

The last cycle of transactions or special
(see

Section

2.11.5)

2-49

mode

functions

When

the

ARB

transaction

arbitration

before

Timing

for

Figure

and

nodes

for

2.11.4

cycles

busy

STOP

mode.

2.11.5

some

special
Or

and

may

pending

BSY

during

seen,

the

not

assertion

node

normal

stop
to

example,

bus

start

when

the

using

shown

activity

cycle

the

transaction

activity

until

additional

the

activity

and

cycles,

one

data

transfer

one

discussed
next

STOP

may

asserted
A

For

until

called

ready

example,

transaction

delays

bus

progress.

BSY

doing

the

node

cycles,

node

transaction.

the

functions.

node

until

may
it

to
node

assert

can

enter

Functions

ARB

extend

The

another

transactions

transaction

registers

BSY

bus

before

bus

the

node

during

transaction
when

start

extending

the

and

BIIC

loopback

1is

internal

reading

data

loopback

asserts

operation

and

complete.

paths

BSY

2-41

writing

only.

NO
A

execution

between

the special mode function is completed.
(The
asserted to identify the operation as a special

For

cycle

raising

length.

previously

Mode

arbitration

Transaction

the

mode

the

cycle.

arbitration

next,

bus

2-19.)

until

little

increased

begins

operation

dead

embedded

follows

master

arbitration

one

with

bus

during
begin

Figure

embedded

there

and

bus

the

embedded

However,

the

typical

until
is

when

1least

during

1its

Special

BSY

the

during

bus
may

winning

master

bus

can

node

again

the

transaction

the

node

bus.

delay

Both

bus

(Refer

wait

immediately

cycles,

responding

becomes

wins

begin.

properly

BSY

example,

must

1is

asserted

stall

For

its

and

there

beyond

respond

may

Extending

may

cycle.

arbitrating

the

for

asserted,

arbitrating

transaction

arbitrate

not

BSY

begin

can

may

1is

cycle.

node

ARB

nodes

BSY

2-20.

transaction

BSY

can

transaction,

rate

BSY

nodes

the

when

When

the

Similarly,
0

asserted,

when

transaction
cycle

not

cycle.

ARB

other

transaction,

bus

transaction

NO
ARB
signal
mode function.)
cannot

to
of

respond

prevent

1loopback

one

nodes

its

any

operation

own

BIIC

CYCLE

NULL |ARB | C/A | |A

MASTER

|DATA| ARB | C/A | IA

PENDING

MASTER

ARB’ING

NODE(S)

BSY L

ARB L

»‘JRANSACHON 3 {

FTRANSACTION 2

‘LRANSACTION j’{

|DATADATA|

C/A | 1A

B,C

|DATA|C/A

SCLD-195

Figure 2-20

2.12

VAXBI

ERRORS

VAXBI Arbitration

The error detection by VAXBI nodes
the

(Example)

(done by the BICC)

consists

following:

Parity Checking

Transmit Check Error Detection

AR R

2.12.1

Parity Checking

embedded
for
Except
(PO).
1line
parity
The VAXBI has a single
parity bit (when it is generated) is for
the
cycles,
arbitration
arbitration
During embedded
the information on the D and I lines.
The nodes generating and
only I-line parity is generated.
cycles,
checking parity during VAXBI cycles are listed below.

Cycle

Command/Address

Embedded
Decoded

Write

Arbitration
ID

(IDENT)

(Vector)

Parity

Checking

Node

Node(s)

Master

All

Master

All

Master

Data

Read

Parity

Generating

Null

Potential

Master

Slave

Master

N/A

All

Data

Transaction

Aborted

Slave(s)

Yes
Yes

(see

note)

N/A

NOTE

All

nodes

asserted

When

bus

node

error

detects

during

the

2.12.2
There

two

information
not

compare

check

1is

(IDENT)

parity

the

Check

with

the

made

when

on
and

1its

the

error

The

check

asserting

error

BSY

the

error

VAXBI

lines.
and

that

and

does

not

Again,

generates

transaction

bad

detect

IDENT

cycle.

check

master

errors.

the

received

master

ARB,

However,

transaction

transmit

flag

interrupt

its

request

parity

acknowledge

command/address,

error

during

(ACK)

the

parity

transaction

error

not

when

the

Detection

information

received

bus

enabled).

are

detecting

nodes

transmit

during

sets an
generates

not

cycle

lines

arbitration

Error

Nodes

1ID

and

interrupt

IDENT

error,

BIIC)

enabled.

transmitted

cycles

are

types

information

(if

Also,

the

transmitted

flag

cycle.

decoded
in

Transmit
are

null

cycles

command/address.

participate

that

during

(in

interrupts

command/address

check

(by

and

does

detect

node

interrupt

sets

progress,

2-43

or
an

a
the

the

information

sets

other
slave
flag
(if

error

request

type

should

asserted

error

not

The

decoded

interrupt

The

does

transmitting

request

lines

node).

node

PO
and

master

aborted.

not

data,

When

the

master

the

same

generates

the

1lines.

also

when

and

only

compare,

type

write

the

One

state
its

bus

enabled).

aborted.

2.12.3 Protocol Checking

The following errors in VAXBI transaction
When

error is detected by a node,

checked.

are

execution

it sets an error flag in its

bus error register and generates an interrupt request (if enabled).
NO ACK

Mul + 1

(=]

NO
a
received
IPINTR command.

onder

Command

response

for

Rece
ceil ved

I NVAL,

STOP,

master

INTR,

Interlock Sequence Error - A node successfully completed
transaction that was not preceded by a
an unlock write
corresponding read interlocked transaction.

received by
IDENT Vector Error - An ACK response was not
correctly
not
the vector was
indicating
master
the
received by

the

slave.

(or
Read Data Substitute Error - A read data substitute
vector)
(or
read
with
received
was
code
status
reserved)
data and no parity error was detected.

Retry Timeout - The master received 4096 consecutive RETRY
responses from the slave for the same transaction.

slave transmitted 128 consecutive
slave to abort the
the
Causes

Stall Timeout - The
responses.
STALL
transaction.

Bus Timeout - A node was unable to

start

transaction after 4096 consecutive bus cycles.

Nonexistent Address - A master received no response

read/write

or transmit
information.

type

bus

pending
to

command/address
the
for
error
check
Causes the master to abort the transaction.

Illegal Confirmation Error - A master or slave detected

reserved or

command, and it detected no parity error

illegal response code.

2-44

CHAPTER

3.1

INTRODUCTION

The

visibility

lines

and

selected
the

execution

PRO-38N

levels
of

the

control

VBus

the

outputs

speed

allow

CPU

modules.

when

reads

and

the

module's

VBus

the

RTI.

Both

the

VBus

are

shown

Figure

consisting

data

console

read

system

clocks

means

access

multiplexer),
and

the

stopped.

two

registers

These

registers,

(actually

accessed
control

the

3-1.

PRO-38N

console

perform

the

during

console

CPU

during

system

clock

1in the
bursts.

Verify

during

Module

Check
case,

the

revision

that

system

3.3

VBUS

SIGNALS

VBus

signals,

VBus

The

3-1,

the

control

clock

which

ECL

3-1

execution
are

(with
at

this

usually

full

and

clock

correctly.

time.

errors
occur
initialization.
1In
flags)

the

clocks

the

installed

parity
error

driven

‘

read

major

entered

signals

are

system

(parity

running

are

also

store

during

bits

the

single-stepped

modules
are

following

commands

initialization

numbers

data

between

CPU

loaded

debug.

interval

system

that

microcode

Table

initialization.

VBus

Monitor the state of the CPU(s)
microdiagnostics or in response

stopped)

during

FUNCTIONS
allows

examined

(VBUS)

mainly

are

functions:
1.

used

interface.

VBus

the

data

BUS

PRO-38N

during

console

and

VBus

bus

the

system

interface

BASIC

and

console

VBus

slow

that

over

3.2

the

used

clock

PRO-38N

The

controls

lines

microdiagnostics

VBus

located
the

(VBus)

control

logic

Normally,

The

bus

two

VISIBILITY

are

read

when

this
with

speed.

received,

are

defined

RIGHT CPU MODULES

LEFT CPU MODULES

»
>

stco

»
|—<1%2

<7z

SHR

4__<6_>_

sSLCH

«=]

sico

aop

|—=<122»p

<32

ccs

»
f—1>

<2>
=2

DEC

_SJOL_}

<«=<>]

sea

se@

|—2—»

<0>

wcs

VBUS DATA <7:0> H

—

ssR

4+—3>—

sLCA

wes

VBUS |ADDRESS H

VBUS STOP SHIFT H

/,8

<14>

)

<8>
|

VBUS DATA <15:8> H

CLK

BOLK H

CLOCK (CLK)

MODULE

CLK

fif_

VBUS DATA MUX

SEL | Mux | STOP|

STEP|vBUS | VBUS CONTROL

SEL | SHFT|BCLK|ADDR | REGISTER
A
_A'

—» (TO/FROM OTHER CONSOLE
INTERFACE REGISTERS)

PRO-38N INTERFACE

PPI

PRO-38N
CONSOLE
SCLD-196

Visibility Bus (VBus) and VBus Control (on CLK Modul )

—
[

Figure 3-1

Table

Signal
VBUS

Line

DATA

<15:0>

3-1

VBUS

Signal

Descriptions

Number

Description

Transfer

VBus

console
Each

data

module

line

and

channel.
VBus

data

interface

connects

Left/Right

CPU

DATA

SHR

SLC1

STOP

SLCO

ADP

CCs

<11>

<10>

<9>

DEC

SEQ
WCS

<8>

<7>

<6>

SHR

SILC1

<5>

<4>

SLCO

ADP

CCs

<2>

<1>

DEC

SEQ

WCS

VBus

interface

data

all

address

CPU

into VBus
registers) on
a time.

Asserted

console

disable

the

shifting

registers
DEC,

and

in
SEQ

some

hold

their

current

data

address)

asserted.

IT 3-3

console

Address

address

each

registers
module one

interface

CPU

modules).

VBus

from

modules.

shifted

bit
VBUS

Module

(shift

SHIFT

CPU

Transfer

CPU
VBus

<15>

<0>
1

one
one

module.

<14>

<3>

modules

(CLK)

to
to

<12>

ADDRESS

CPU

clock

corresponds

<13>

VBUS

from

address

modules

(Cccs,

The

contents
as

VBus

long

registers

(the
as

the

current
line

The 16 data lines allow 16 separate visibility channels to ofbe theread
16
by the console. That is, a data line connects from each
CPU modules to the VBus data multiplexer on the console 1interface.
(There are eight modules 1in the left CPU and eight in the right

CPU.) Eight VBus channels, either the eight left CPU channels or
the eight right CPU channels, can be read by the console at a time.
One,
The two VBus control lines connect to more than one module.
reads
console
The
.
modules
all
to
s
the VBus ADDRESS line, connect
VBus data from a module by first shifting an address onto this line
one bit at a time. The address is held in the module (in a shift
is
register) and it selects the single VBus data bit that
address
the
Because
line.
data
transmitted on the module's VBus
in
line connects to all modules, a VBus data bit may be selected the
above,
ed
mention
As
.
address
single
more than one module by a
VBus data bits from all modules can be read eight bits at a time
once an address is loaded.

The second VBus control line, VBus STOP SHIFT, connects to only the
ccs, DEC, and SEQ modules in each CPU. When asserted by the
console, this signal causes the shift registers holding the VBus
data address bits in the modules to hold that address even if the
system clocks are started. The selected VBus data bits may then be
examined during normal operation when clocks are running at full
speed.

This is done during the loading of microcode when the

VBus

is used to monitor control store parity error flags. (These parity
error flags in the CCS, DEC, and SEQ modules are all selected by

the same VBus data address bits: 100110, where the right-most or
least significant bit is the last bit shifted into the VBus address

path.)

VBus STOP SHIFT can also be asserted during system debug so that
selected VBus signals may be scoped on the backpanel while the
system clock

3.4

VBUS

is running.

REGISTERS

Register bit formats for the two VBus registers on the console
interface are shown in Figures 3-2 and 3-3. The VBus control
register is a write-only register. The VBus access register, which
is the output of the VBus data multiplexer, is a read-only
register.

The bits in the VBus control register are defined in Table 3-2.

The VBus ADDRESS and STOP SHIFT control bits (latch outputs) drive
the two VBus control lines. These control bits hold thelr current
state unless changed when the VBus control register is written

again.

The

STEP

1is

every

BCLK

set
time

operations

shift

control

BCLK

first

bit

into

repeated

the

VBus

hold

the

VBus

bit

the module's
wuntil

all

data

VBus

the

ADDRESS

system

one

the

VBus

and

wused

into

address

loads

ADDRESS

The

cycle)
1is

address

data

console

line.

BCLK

clock

generated.

that

When

one

(for

clock

BCLK).

loads
the

causes

momentarily

registers

clocked

bit

only

the

VBus

bits

address

are

VBUS CONTROL REGISTER

(VBCTL)

the

setting

READ/
WRITE

are

data

address

bit,

STEP

| 03

transmits
the

address

BCLK.

This

shifted

MUX

NOT USED

(The

modules

modules.

CONSOLE
ADDRESS
(HEX)

modules.

shifts

shift

set
VBus

which

then

during

the

latch,

console

generated.

must

into

|STOP | STEP | vBUS

SEL |SHIET|BCLK | ADDR
SCLD-197

Figure

Table

3-2

VBus

Control

Bit

Descriptions

Bit(s)

Description

<T7:4>

Not

<3>

Multiplexer

select.

Selects

which

VBus

are

console

when

reads

the

Cleared

CPU

used.

read

access
MUX

<2>

SEL

VBUS

INIT.

CHANNELS

Eight

channels

from

left

Eight

channels

from

right

from

shifting
DEC, and

Stop

shift.

that

hold

Used

Cleared
Step
Set
<0>

SELECTED

channels
VBus

flags

<1>

VBus

BCLK

address

CCS,

control

freeze

address

these

modules

when

BCLK.
for

Prevents

VBus

CPU

one

address.

serial

VBus

Cleared

one

store

microcode

system

clock

registers
SEQ modules.
parity

error

loaded.

This

address

path

INIT.

3-5

BCLK

generated.

cycle.

address
CPU

CPU

INIT.

Causes

only

CPU

bit is
(in each

shifted
module)

into
by BCLK.

is
the

CONSOLE

VBUS ACCESS REGISTER (VBACC)

READ/

ADDRESS

WRITE

(HEX)

04 | 03
|

VBUS DATA BITS

SLCO

SHR

MODULE

SLC1

ADP

MODULE

NOTE: VBUS DATA
IF BIT<3>
CLEARED.
DATA BITS

MODULE

SEQ

CCS

MODULE

DEC

MODULE

WCS

MODULE

BiTS ARE FROM LEFT CPU
IN VBUS CONTROL REGISTER IS
|IF BIT<3> IS SET, VBUS
ARE FROM RIGHT CPU MODULES.
SCLD-198

Figure

3-3

VBus Access Register

The MUX SELECT control bit (another latch output) simply drives the
the VBus data multiplexer and determines which
for
1line
select
eight VBus channels are read by the console when it reads the VBus
access

typical
a
during
follows
The console uses the VBus registers as
off).
turned
clock
read of one or more VBus channels (system
1.

Loads VBus ADDRESS bit and STOP SHIFT = 0

Loads same VBus ADDRESS bit, STOP SHIFT = 0,
= 1 (to shift address bit into modules)

Repeats steps 1 and 2

Loads MUX SELECT bit and reads VBus data bits

and STEP BCLK

(until all address bits are

shifted

into modules)

Note that a copy of the VBus ADDRESS bit is loaded when the BCLK is
This is because the console is not allowed to change the
stepped.
also
It
set.,.
1is
BCLK
STEP
state of the VBus ADDRESS bit when
of the STOP SHIFT bit when STEP BCLK is
state
the
change
cannot
the
to
due
necessary
are
restrictions
These programming
set.
LIS

3-6

3.5

MODULE

The

VBus

VBUS

CHANNEL

channel

CIRCUITRY

circuitry

following:
1.

One

the

VBus

console.

modules.

One

amount

shown

read

the

console

tail"

bit

VBus

data

bits

these
the

minimum

WCS

modules.

flags

can

tail

be
bit

and

both

reads

each

read

bit

different

be
data
most

address

basically

BCLK)
the

bits

are

the

that

module
not

for

hold
by

the

used

when

tail

and

that

out

also

address
VBus

the

shift
channel
that

the

verifies

bit.)

not

used
shift

may

the

tail

that

console

and

error

tail

bits,

VBus

because

SLC1,

module's

channel,

verifies

test

reads
having

parity

stream

the

"eat

SLCO,

shifted

through

the

SHR,
number

data

Modules

revision

Furthermore,

the

CPU
allow

console

address

that

test

slot.

are

must

also

The

store

VBus

bit

and

control

testing

verify

number

for

modules

operation.

two

the

own

each module,

and

operating
module

bit

the

address

correct

slot.

Configuration
allow

wusing

multiplexers
part,

its
When

CPU

initialization.

serial

but,

the

modules

examined

the

required

all

revision

circuitry

addition
in

is,

channel

module,

successful

Expanded
CPU

and

installed

configuration
VBus

into

circuitry

That

system

VBus

WCS

purposes

back

VBus

console.

installed
module

the

followed

correctly.

3.5.2

channel
3-4.,

during

(In

the

shifts

Some

(clocked

shifted

number

module's

test

amount

selection

read

VBus

Figure

the

same

the

for

registers
address

module

Minimum Configuration

minimum

module

The

CPU

more data multiplexers that select
the
VBus
data
specified
by the address.
The bit is transmitted on
module's single VBus data line.

the

3.5.1

The

all

bit

The

shift
data

are

capability

the

are

large

VBus.

required

located

shown
are

the

number

Thus,
in

the

within

Figure

ADP,

the

3-5.

CCS,

3-7

internal

additional

DEC,

module
MCAs.

logic

shift

and
A

levels

registers

and

these,

for

typical

expanded

Modules

having

and

modules.

SEQ

the

expanded

REVISION

p| DATA
——

VBUS DATA <n> H

MUX

(JUMPERS)

SHIFT
REG.

TAIL BIT

3
|-2 —»

OTHER DATA INPUTS —P

SEL

(IF ANY)

| 0

)

SHIFT DIRECTION
<4+

BCLK H—

VBUS

03__02

ADDRESS

VBUS ADDRESS H

L
BIT
T = TAI
SCLD-189

n]
Figure 3-4 VBus Channel in CPU Module (Minimum Configuratio

1T 3-8

MCA

—>

NPUTS

||I

Mux

SEL

SHIFT —>
REG.

MUX

—>

/ SEL
BCLK

—»

REVISION

SHIFT |
REG.

—>

VBUS STOP

SHIFT H —¥
BCLK

NUMBER

]

TAIL BIT

VBUS DATA <n> H
SEL

OTHER DATA INPUTS —»

.
e

H —»

TM Mux

(

—

VBUS ADDRESS H —T
VBUS

SHIFT DIRECTION
—

ADDRESS

MCA_ DATA

__05

SELECT

MCA

SELECT

= TAIL

VBUS DATA

SELECT

BIT
SCLD-200

Figure

3-5

VBus

Channel

CPU

Module

3-9

(Expanded

Configuration)

3.6 VBUS ADDRESS/DATA SUMMARY

The VBus directory in the System Maintenance Guide lists the
logic
levels in each module that can be read using the VBus.
(An excerpt
from the beginning of the directory is given
1in
Table
3-3.)
The
minimum
number
of VBus data address bits required for each module
(each channel) varies from three bits to ten
bits
(not
including
the

tail

bit).

3.7 VBUS CONSOLE COMMANDS
There are three VBus console

PROBE

SHOW

VBUS

CLEAR ACCUMULATOR

commands:

<accumulator

bit>

ACCUMULATOR

The PROBE VBUS command selects a single VBus data bit and loads
it
into
(actually
ORs
it
with)
one
of
the
bits
in
a
32-bit
accumulator.
The use of an accumulator allows a
string
of
these

commands to assemble several bits of VBus data into a useful format
before the data is
finally
examined
with
the
SHOW
ACCUMULATOR
command.
All bits in the 32-bit accumulator can be cleared at any
time with the CLEAR ACCUMULATOR command.

The address for the PROBE VBUS command consists of a channel number
and a VBus data address.
This is followed by the bit number in the
32-bit accumulator.
The command causes the console
to
shift
the
VBus
data
address out to all modules, read the selected VBus data
(eight channels), and then load the
data
bit
for
the
specified
channel into the specified bit position in the accumulator.
Use of the VBus commands is illustrated below.
The
example
1is
a
command
file
that reads the address of the first microword in the
pipeline.
The address bits, stored in the microPC silo on the
SEQ
module, are assembled in bits <13:00> cf the accumulator,
IMICROPC.CMD

lassembles
CLEAR

microPC

bits

from VBus

and

displays

ACCUMULATOR

PROBE VBus
PROBE VBus
PROBE VBus

%X1007
%X100F
%X1017

00
01
02

!read
!read
!read

bit
bit
bit

O
1
2

PROBE
PROBE

%X1117
%X111F

12
13

lread
lread

bit
bit

12
13

SHOW

VBus
VBus

ACCUMULATOR

them

Table

3-3

VBus

Directory

(Excerpt)

Channel

Module

WCS

F1009

SEQ

F1008

Module

Type

DEC

F1007

CCs

F1006

ADP

F1005

SLCO

F1004

SLC1

F1003

SHR

F1002

PROBE

Channel

VBus

Address

(Hex)

(Binary)*

0000

0008

Data

Signal

Remarks

000

TAIL

BIT

000

BIT

Tail

bit

should

INT

bit

010

Tail

0002

TAIL

CS1

should

011

INT

CS1

CS2

Parity

100

Error

MODULE

CS2

Parity

Error

0003

0004

0005

101

0006

MODULE

REVISION

<1>

0007

110

MODULE

111

REVISION

<2>

MODULE

REVISION

<3>

REVISION

<0>

1000

000

1001

INT

001

BIT

Parity

1041

TAIL

CS0

XXX

TAIL

BIT

bit

should

010

1002

001

Tail

MODULE

Tail

bit

should

Cs0,

CS1,

CSO

REVISION

<0>

1003

011

1004

MODULE

REVISION

<1>

100

MODULE

REVISION

<2>

REVISION

<3>

1005

1006

1007

00X

000

101

MODULE

110

PARITY

111

DIG

UADDR

ERROR

<0>

100F

00X

001

111

1017

DIG

UADDR

00X

010

<1>

111

DIG

UADDR

<2>

101F

00X

011

111

1027

DIG

UADDR

00X

<3>

111

100

1087

DIG

UADDR

01X

108F

111

000

<4>

DIG

01X

UADDR

001

111

<5>

DIG

UADDR

<6>

CS2

1097

01X

010

111

109F

DIG

UADDR

01X

<7>

111

011

10A7

DIG

UADDR

01X

111

100

<8>

1107

DIG

UADDR

10X

<9>

111

000

110F

DIG

UADDR

10X

001

<10>

111

DIG

UADDR

<11>

(address

1117

10X

010

111F

111

DIG

UADDR

10X

011

<12>

111

DIG

UADDR

<13>

uPC

right-most bit of the VBms data address (binary
) is the least
significant bit and the last bit shifted
into the serial address path.

3-11

Address of first
microword in pipeline

The

silo)

EK-KAB88X~-TD-PRE

CONSOLE

SECTION 3
SUBSYSTEM

CHAPTER 1
INTRODUCTION

1.1

GENERAL

This

section

console

containing

Chapter
at

the

interacts

Chapter

VAX

overview

diagram

functional

8800

divided

the

level.

description

system.

into

the

VAX

three

console

8800

chapters

subsystem

and

how

analysis
of the console interface and a
input/output ports, timing signals, MCA
logic,
definitions.

the

DOCUMENTATION AND

technical

pertaining

information:

and

description

1is

Detailed

1.2

block

the

description

This

technical
section

introduction

with

The

following

simplified

Chapter

and

provides

subsystem.

description

the

references

have

maintenance

does

Professional

been

the

REFERENCES
not

contain

Series

provided

380

for operation,

PRO-38N:

Professional

300

Series

Professional

300

Installation

Guide

Professional

300

User's

for

Professional

300

Communications

Manual

Professional

300

Pocket

Card

Professional

300

Technical

Professional

300

Field

Owner's

Guide

Service

detailed

computer.

Manual

Maintenance

Disk

System

(EK=PC3XX~-PC)

(EK=PC3XX-TM
Print

Set

(MP-01394-00)

Maintenance

Set

(MP-01410-00)

LK201

Field

Maintenance

Set

(MP-01395-00)

KEF1ll

Field

Maintenance

Set

(MP001473-00)

System

Hardware

VAX

8800

System

Installation

User's

Guide

IIT

1-1

(AA-N603A-TH)

(AA-N602B-TH)

Field

8800

and

(AA-N587A-TH)

VR210

VAX

following

installation,

(AZ-N626A-TH)

Hard

Manual

information

The

(EK-8800H-UG-001)

(EK-8800I~IN-001)

1.3

FUNCTION

The

console

provides

AND

PURPOSE

subsystem

primary

1is

control

independent

the

VAX

8800

computer

system.

system

that

of
switching,
loading
of
of
a
dual-CPU VAX 8800

the
console
subsystem
controls
power
microcode,
and
the
general
operation

The

software

system.

l.4

SUBSYSTEM

The

console

COMPONENTS

subsystem

shown

Figure

1-1

uses

Professional

Series 380 computer (PRO-38N) as a console device.
The PRO-38N is
a
self-contained system that consists of a Winchester disk drive,
dual-floppy disks, display monitor, and terminal keyboard.
A
real-time interface (RTI) I/O module located in slot six of the
PRO-38N,
provides
the communication path between the console and
the
VAX
8800
CPU(s). All of the console/VAX 8800 communications
are
transmitted
and
received
through
the RTI.
The RTI uses a
programmable
peripheral
interface
(PPI)
and a serial line unit
(SLU) as I/0 devices for communication.
The

PPI
communicates
by
means
of an 8-bit bus to the VAX 8800
cabinet,
and
handles
the
transfer
of
read/write data, system
status, and control signals. The SLU is the console's interface to
the
VAX
8800 power subsystem. Control and status signals between
the
console
and a microprocessor in the environmental monitoring
module
(EMM)
provide
the
<console
with
the ability to monitor
specific
parameters
in
the
VAX
8800
cabinet such as voltage,
temperature, and airflow.

The

PPI

VAX

8800

8800
with
Anr

FAF S

bus

«clock

backplane
the

VAX

"+
~
Vt}

through

provides

8800

h.]

LTM

serial

diagnostic

PRO-38N

The

the

console

clock

interface

module's

console

with

residing

connection

point

+n
s W/

+the
L VSR Ay Y

the

VAX

communication

CPUs.

nrintar
18 G N Ao

remote
the

connected
module.

~an

he
A

printer
link

that

~cAannartad
+
o s LaLAN~ L e s i

port

the

can

established

set

for

modem

ITTI

1-2

rear

through

control.

rAanenle
AL AAd s d N

the
an

acitheuvectam
" Al -~ u_z A e N det

PRO-38N.

existing

port

PRO-38N

CONSOLE

FIXED-

VAX 8800

REAL-TIME

HEAD

ATAR

CABINET

CLOCK MODULE

INTERFACE

PRIMARY
PPI

DUALFLOPPY
DISK

»|

—»

CONSOLE

cPu

INTERFACE

SLU

£-T III

DISPLAY
AND
KEYBOARD

POWER

SECONDARY
CPU

512

OPTIONAL

MEMORY

PRINTER

J-11

SYSTEM

CPU

NONVOLATILE
CLOCK (TOY)

REMOTE
TERMINAL

SCLD-211

Figure

1-1

Simplified

Block

Diagram

the

Console

Subsystem

1.5

CONSOLE/VAX

The

console

power-up
modes,

and

1.5.1

INTERACTION

1in

boot

because

power—-up

8800

operates

mode

the

two

modes

included

important

role

Power-Up

Power

Monitoring

environmental

°®

Performing

loopback

°®

Verifying

[

Performing

)

Providing

VAX

Console

I/0

that

The

Placing

the

can

firmware

halt

interface

comparisons

and

effect
mode,

booting

during

the

halted

must

support
not

system

the

can

stepping

software

the

either

console

VAX

Commands

VAX

8800

perform,

and

clock

during
to

these

microcode

(CSM)

requiring

microcode

halt

examine,

control
functions

communicate
assistance

wit
are

mode.

CTRL/P

independently

the

microcode/macrocode

console

identification

8800

console

either

with

available

has

the console is responsible
the
following
VAX
8800

compatibility

the
of

the

console

1limits

mode

the

operator,

during

amount

but

allows

VAX,

the

console.

The

placement

allow

system

During

deposit,

functions.

revision

run mode.

mode

correct module

[

valid

console

1-2.

operating

status

testing

[

console

the

application/sequencing

[

The

Figure

Mode

and

discussion

sequence.,

During
the power-up mode of operation,
for
the
sequencing
and
control
of
functions:

1.5.2

shown

the

of
the

VAX

8800

console

CPU

run

commands
to

run

VAX 8800

CPU

CONSOLE CPU

|
|

HALTED

POWERUP
AND
BOOT

I
|
|

|
|

CONSOLE

MODE

|
|

_______ _1____-______———Jl-——-_———----——--____--...__________

RUN

MODE

RAM

}
|

]

CONSOLE

MODE

SCLD-212

Figure

1-2

Modes

IIT

1-5

Operation

Program
mode
places
the
console
1in a state similar to any VAX
terminal.
Communication with the VAX 8800 CPU is under interrupt
control using the ready and done conditions.
During program mode,
the
console
is
free
to
interact
with
the
VAX
8800
at the
instruction
set processor (ISP) level and perform normal operator
interactive

functions.

1.5.3
VAX 8800 State Description
The
VAX
8800
CPU
exists
1in
hardware/operational states:
1.

Power

off

Clock

stopped/WCS

invalid

Clock

running/WCS

invalid

Clock

running/WCS

valid

1.5.3.1

Power Off

-- All

one

regulators

turned

the

following

four

off.

1.5.3.2
Clock Stopped/WCS Invalid -- The VAX 8800 regulators have
been
turned
on and the clock is stopped while the console checks
module and software revisions.
Microcode has not been loaded, and
volatile
RAM
locations
remain
invalid.
The
clocks
are then
started

load microcode.

1.5.3.3
Clock
Running/WCS Invalid -- There are two conditions in
which
this
state can be true:
during powerup and loading of the
WCS.
The
<clock
1is running during the power-up seguence and all
RAM
areas are volatile and invalid.
During WCS and IBox loading,
the clock is running.

Running/WCS Valid -- Microcode has been
loaded into
1IBox
decoder
RAMs
and
cache control store are

loaded.

VAX

the

VAX

The
8800

i.5.3.4
<Clock
WCS;
the

the

CPU

system

is executing

ready

the

state.

111 1-6

a NOP microinstruction and

1.5.4
The

Console

console

Power

The

CPU

State

Description

exists

one

the

following

operational

states:

Off

power

switch

the

PRO-38N

the

OFF

position.

Stuck
Console
not

selftests

have

failed.

Power-up

and

boot

proceed.

sequence

will

P/0S
The

console

can

use

the

running

result

P/OS,

the

PRO

operating

intentional

result

exit

system.
from

console-only

This

the

VAX

power

condition

8800

system

failure.

NOTE

The

P/OS

system

state
has

console

will

been

exist

applications

have

installed.

Console

not

been

have begun. The console is initializing the
spawning the RTI driver. Testing of the real-time
environmental monitoring module, and VAX 8800 hardware

and

interface,
are

the

applications

base

have

the

and

Applications

Console

data

when

assembled

not

been

valid

performed.

Commands

during

this

and

clock

module

Commands

for

testing

and

interrogation

state.

Test
EMM,

RTI,

successfully.

loopback
the

EMM

valid.

testing

have

been

begin

VAX

8800

and

the

clock

completed

powerup

are

Power

VAX

8800

Commands

and

CPU
to

cache

power

start

has

the

control

been

clock

store

applied
and

load

are

valid.

I1T

microcode,

valid.

1-7

The

IBox

NOT

running.

decoder

POWERDOWN

RAMs,

command

Micromonitor Mode

am that allows
Micromonitor 1is a subset of the console progr
and WCS-based
sed
loading, <control, and monitoring of console-ba

microdiagnostics.

commands

The

that

are

wvalid

include

the conventional console

commands plus a set of micromonitor commands.

Console Mode

loaded.
The VAX 8800 ISP with console support microcode has been valid.
are
g
commands that are allowable when the clock is runnin
Microbreak

Clock stopped, microcode execution halted.
of one of the following:

°
®

This state is a result

MicroPC match and stop on micromatch set
Clock burst of (n) cycles complete
SET CLOCK OFF command

Intermediate

to
This state exists during the transition from console almode
and a
program mode. Characters are not passed from the termin
limited amount of commands are valid.

Program Mode

Normal mode of operation for the VAX 8800 run mode.
Boot

The console is in the process of booting the VAX 8800 system.
Restart

The console is in the process of restarting the VAX 8800 system.

111 1-8

1.6

CONSOLE

The

console

processes

SOFTWARE

software

implement

consists
control

Control

program

Logical

block

Real-time

l1.6.1

Control

The

control

for

implementing

control

the

console

EMM

WAIT

the

following

the

VAX

8800

three

distinct

system:

program
driver

Program

program

REQUESTS,

server

interface

program

micromonitor,

COMPONENTS

main

modes

support,
uses

EVENT

console

and

RSX

and

remote

system

FLAGS,

program

(program

and

console

terminal

directives

QUEUED

I/0

responsible

I/0),

logfiles,

access.

The

CLEAR,

TIMED

SET,

WAIT.

During

system
initialization,
the control software installs
initializes
the
RTI
driver, spawns the logical block server
disk
access
programs,
reads
nonvolatile console state from
console

disk

1.6.2
The
or

drive,

Logical
logical

write

Block

block

files
the

creating

1.6.3

Real-Time

The

real-time

the

RTI

Interface

functions

programs.

Separate

control,

enables

the

VAX

8800

CPU

disks.

The

console

8800

large

virtual

floppies

read
by

drive.

Driver
provides

PRO-38N,

logical

subdrivers

programmable

database.

floppy

VAX

driver
the

console

Winchester

interface

the

and

the

Program

program

from

the

circuitry

the

Server

and

floppies

file

initializes

server

presents

either

and

block

are

peripheral

the

and

software

the

server,

used

link

hardware

for

interface,

and

between

independent

file

transfer

communications

the

serial

with

line
The
PPI
subdriver
provides
mapping
from
high-level
functions, to machine-specific operations (for example: Examine or
Deposit
requests
require
a correct sequencing of reads, writes,

unit.

and

acknowledge

operations).

111

1-9

1.7

The

CONSOLE/VAX 8800 POWER SEQUENCE

description

the console and VAX 8800 power sequencing is

into five functional areas:
Powerup

Ul
W N

divided

EMM/Console initialize
Restart/Boot/Halt
Power

fail

Powerdown

Each of the five functional areas is illustrated with a flowchart
The flowcharts are intended as a
in Figures 1-3 through 1-7.
reference for the brief overview of the VAX 8800 power sequencing,

and do not contain sufficient information for a detailed analysis.

Refer

to Section 10 of the manual for information about the power

subsystem.

1.7.1

Powerup (Refer to Figure 1-3)

The power—-up sequence involves two independent processors to bring
the VAX 8800 system to ready state. The microprocessor in the
environmental monitoring module, and the console processor perform
numerous cooperative tasks that ensure the correct sequencing of
power and initialization of the system.

111 1-10

l
|

AC TO POWER
CONTROLLER

AC TO CONSOLE
SUBSYSTEM

(CONSOLE POWER ON
N

AC TO BBU

YES

AC TO NBOX

¢,

|¢—

(EéNSOLEINITIALIZ%)

TO EMM

(EMM INITIALIZE)
SCLD-213

Figure
When

the

turned

The

main

the

)

876

Console

876

12-volt

power-on

and

Power-Up

circuit

position,

power

conditioner)
a

power

1-3

breaker

voltage

Sequence
on

the

VAX

applied

8800

cabinet

the

following:

voltage

the

NBox

(BBU).

The

controller

subsystem

controller

applies

the

backup

5-volt

battery
dc

the

unit

EMM,

sequence.

ITT

1-11

enabling

the

EMM

NBOX
to

(port

provides
begin

the

l1.7.2
EMM/Console Initialize (Refer to Figure 1-4)
The
dc
voltages
applied to the EMM reset the microprocessor and
begin the initialize sequence by performing a module keying
test.
If
the
keying test is satisfactory, the EMM conducts a selftest.
Failure
of
either the keying test or the selftest will result 1in
an error message to
will
prevent
the
completion
of
the

the console and a reset of the
EMM from responding to console
selftest,
the
EMM will load

EMM.
The reset
commands.
Upon
its own default

monitoring parameters, initiate auto shutdown monitoring,
for the console to be switched "ON".

and wait

When
the
console operator places the PRO-38N power switch to the
"l"
position,
the
console
processor performs a selftest of the
PRO-38N's
major
components.
Satisfactory
completion
of
the
selftest
results
in
the
1loading
and
running
of
the console
software.
The
console software initializes the database and the
RTI driver so that it can communicate with the EMM in the VAX 8800
system.

As
soon
as the console software verifies that it can communicate
with
the EMM, the console sends specific monitoring parameters to
the
EMM
and enables failure monitoring.
The specific parameters
replace
the
default
parameters
loaded
by
the
EMM during the
powerup without the console.
The
console
software
checks
the INITIALIZE IN
determine
if
a
previous
powerup
attempt
had
completion. If the flag indicates that a previous

aborted,
sequence

the console
1is aborted.

is set to the
Power supply

PROGRESS flag to
failed prior to
attempt had been

console I/0 mode and the power
status is checked to determine

if
it
was
a console-only power failure. If a console-only power
failure
had
occurred,
the console clears the CONSOLE GONE flag,
and
sets
either
console
or program mode depending on the state
when the console failed.

The
console executes SYSINIT.COM and the
POWER
ON
to
determine
if
the console
automatic
power
sequence
or
abort
T

LIID

rii~E g

" oo

LLULLID

command file checks AUTO
should continue with the
and
wait
for
further

The
console performs a series of loopback tests to determine that
all
required
communication
paths
with
the VAX 8800 system are
operational.
Successful
completion
of the loopback tests allows
the
console
to
verify
correct
module
placement
and revision
status.

When

the

console

placed,
and
the
WCS, cache control
- v
are

o 'S 1T et 1amAaA
initialized

o
and

1is

satisfied

that

all

modules

are

correctly

revisions are compatible, the console loads the
store, and IBox
decoder RAMs.
IPRs and memory

TINT TA

UNJAM

1
is

P
~A
performed

11T 1-12

3 initialize

I/0.

( BviM INITlAUZE)

GONSOLE INIT!ALI29

\
RESET BVM
MICRO CPU

CHK MODULE KEYING

()
YES

ERROR MSG
AND HALT

RUN SELFTESTS

>
YES

LOAD DEFAULT
MONITOR PARAMETERS

MONITOR AUTO
SHUTDOWN

i
y

CONSOLE ON )

CONSOLE POWER ON
CONSOLE ON

YES
y
A

SHEET

SCLD-214

Figure

1-4

EMM/Console

ITT

Initialize

1-13

(Sheet

RUN_CONSOLE
SELFTEST

(o«
YES

LOAD & RUN

CONSOLE SOFTWARE

INITIALIZE
DATABASE &
RTi DRIVER

A
T

Cgfig%rdg ©

ENABLE EMM

COMMUNICATION

ERR MSG
TO CONS

SET NEW

PARAMETERS

MONITOR
FOR FAILURES

%ifi%mfiggsm ©
TO EMM

HALT

ENABLE EMM
MONITORING

SCLD-215

Figure 1-4

EMM/Console Initialize (Sheet 2 of 4)

)

CHECK PREVIOUS
CONSOLE STATE

(:INIT %QUENc;fi\w
COMPLETE
PL

)

‘lMD

YES
HALT POWER ON

BOOT PRIMARY
INIT SEQ DONE =
FALSE
@ SYSINIT.COM

¢ NO

\ 4

KAUTO POWER ON )

YES

ABORT
CONS

SET

CONS

OLE

POWE

1/0

FAIL

RECOVERY

BEGIN SEQUENCED
POWER APPLICATION

ENABLE BvM
POWER SEQUENCE

y
(POWER ON COMPLETE)

YES

y
E

SCLD-2186

Figure

1-4

EMM/Console

IIT

Initialize

1-15

(Sheet

EXECUTE
LOOPBACK
TESTS

h 4

MONITOR KEY
VOLTAGES

START EMM FAIL
MONITORING

(

YES

CHECK MODULE
PLACEMENT

#NO

( POWER FAIL)

(

/ NO

YES
Y

CHECK
EEVISIONS

YES l

SET CONS 1/0

)

LOAD RAMS,
CACHE, WCS,
ETC.

REPAIR
RETRY

AND

CHECK
REVISIONS

INITIALIZE
IPR & MEMORY

<
Y

RESTART/BOOT/
HALT

CHECK
REVISIONS

SCLD-217

Figure

1-4

EMM/Console

Initialize

(Sheet

1.7.3

Restart/Boot/Halt

When

the

ready

the

shown

power-on
enter

Figure

secondary

primary

CPU.

the

memory,

and

continue

The

FIND

memory,

MEMORY

memory.

left

The

FIND

memory

the
has

the

warm
been

SP
RPB

for

keyswitch
and

program

backed

and

the

cold

CPU

is
a

VAX

halt

VMB.

found,

the

restart

keyswitch.

The

flowchart,

8800

RPB

VAX

saved

set.

restart

IIT

the

Kbytes

the

main

block

plus

512

set.

microcode
block.

search
If

restart

parameter

uses

results

64-Kb

address

the

when

contiguous

boot

The

console

microcode

CPU.

memory

the

boot,

starting

warm

1-17

page—-aligned

parameter

primary

successful

flag

system

depending

the

for

8800
mode,

locate

initiates

flag

1-5)
the

restarted

requests

restart

and

mode.

block

restart

using

indicates

address

command

mode

the

executes

I/O

valid

boot,

command
at

Figure

CPU.

microcode

starting

good

refers

secondary

primary

completed,

software

only

The

loads

the

restart,

restarted

software
support

the

1is

the

console

1-5,

CPU

requested

either

position

(Refer

sequence

block

states
is

RPB

physical
is

found,

that

memory

available.

GESTART/BOOT/HALT)
o

RESTART

(

FOUND

>_NQT’( A)

(

FOUND

> NO

A 4

BOOT l

KAIE\IM%RE\%K GOOD

RESTART

PARAMETER BLOCK
FIND

HALT

lYES

l YES
'

SET WARM RESTART
FLAG

SET COLD RESTART
FLAG

LOAD/EXECUTE BOOT

LOAD RPB

RESTART MICROCODE

G@D’BOOT } o

(CONSOLE HALT)

lYES
(\ PROGRAM MODE )

SCLD-218

'_..I

|
|_.I

Restart/Boot/Halt

!
b=t
-4

Figure 1-5

1.7.4
The
a

Power

pending

power

console.

When

asserts

least

the

DCLO

and

secondary

the

EMM

Figure
module

and

decrease

ACLO.

the

console

responsible

informing

senses

called

1-6)
is

the
in

The

VAX

means

that

sensed

VAX

five

milliseconds

signal.

CPUs

subsystem

interrupt

DCLO

and

after

asserts

and

the

disables

power

1is

executes

the

still

8800

ITT

1-19

CPU

and

the

voltage,

ACLO

signal

generates

the

console

voltage

has

signal,

INIT

signal

microcode

active,

POWER OFF

recognizing

monitored

ACLO

CPU

for

limits.

console

fail

interrupt

informs

acceptable

the

(Refer

monitoring

signal

power—-fail
and

Fail

environmental

the

command

interface

fallen

below

the

EMM

asserts

the

primary

execution.

console

the

recognizes

(o)
v

BEMM RECOGNIZES
FAILURE

h4
BW ASSERTS ACLO

A 4
ACLO GENERATES

POWER-FAIL INTERRUPT

I
BvMM ASSERTS DCLO

CPU INITIALIZE

ASSERTED

MICROPROCESSING
DISABLED

Y
CONSOLE EXECUTES
POWER OFF COMMAND

A4
PRINT “POWER
FAIL® MESSAGE

!
SCLD-219

I.-—l

[§ )

Power—-Falil

b=y

1-6

b=t
+q

Figure

Sequence

1.7.5
An
the

of
If

Powerdown

intentional
command

the
the

backup

battery
BBU

power,

seqguential

(Refer

Figure

powerdown

initiated

recognized,

backup

shutdown

console

software

command.

checks

unit.

enabled

the

1-7)

EMM
of

the

1is

operator

directed

voltage

wishes

the

regulators.

111 1-21

the

continue

console

When
status

without

begin

Crmm)
!

POWER OFF

QPERATOR TYPES

DISABLES

BATTERY BACKUP UNIT

POWER DOWN

POWER STANDBY KEEPS
BATTERY BACKUP ENABLED
AND POWER TO MEMORY

CONSOLE CHECKS
BATTERY

BACKUP

STATUS

v
CONSOLE DIRECTS
EVMM TO ASSERT
ACLO

CONSOLE DIRECTS
EMM TO ASSERT
DCLO

CHECK STANDBY
STATUS

oENABLED

fi\\

YES

DIRECT BW TO TURN
OFF ALL REGULATORS
EXCEPT MEMORY

DISABLE

BATTERY

BACKUP UNIT

A
DIRECT BvMM TO
TURN OFF ALL
REGUALTORS

( CONSOLE 1/0 Moog
-

sclLp-220

Figure

1-=7

Powerdown

ITT

1-22

Procedure

CHAPTER
FUNCTIONAL

2.1

GENERAL

This

chapter

contains

functional

interacts

diagrams

illustrate

subsystem

and

Simplified

block

status

and

control,

Figure

2-1 is a
designed

1is

VAX

8800

how

data

functional

system

signals.

and

show

Refer

the

INTERFACE

(RTI)

interface

module.

The

RTI

the

PRO-38N

backplane

data

path

the

RTI

IEEE

transfer

and

point

"A"

8800

power

VAX

system,
and

8800.

connector

the

present

two

connected

controlling

provides

the

storage,

from

the
and

line

for

the

provides

Serial

line

the

8800

VAX

8800

environmental

monitoring

the

the
power

port

"B"

bulkhead.

configuration.

11T

link

the
VAX

2-1

The

the

between

console
8800

and

console
is

system

PRO-38N
8800

through

CPUs

with

components.
(PPI),

the

primary

data

Serial

1line

port

module
with

environmental
connected
IEEE

the
key

VAX

computer

interface

system.

The

the

system

monitoring
and

the

control

PPI

and

following

located

peripheral

ports.

subsystem,

indicating

display,

programmable

and

data

console
by

interface

serial

only

connected

and

console

consists

port,

the

console

the

1level,

diagram

block

real-time

clock

system.

initialization,

console

the

console

the

flow

REAL-TIME

and

the
8800

between

functional

2.2

computer

of
VAX

process

diagram

interaction

The

console

the

transfers.

block

the

description
with

description.

The

DESCRIPTION

port

the

VAX

means

parameters

to
is

not

spare
used

CONSOLE INTERFACE

PROGRAMMANALE
PERIPHEAAL
W TERFACE

BUFFER

TRAMBLATOR

PORT

[ T
X

ADOREBS PP G

[ ropT

DATA

)

pata 00

READWRITE
OoNTROL

ADDFESS

INTERRUPT

BUFFER
—

FROM PORT B

INTERRUPT!

— 'I
LOGIC

35?5""5

DATA FROM_OONSOLE

TO LEFT CPU {8EQ)

—

BIDIRECTIONAL

BIDIREG-

o
PN THOL <L

DATA OUT

DATA BUS
TOF ROM

LEFT CPU (DEC)

m\fl

BUFFER

BLICE «7:4>

LEFT CPU HIGH TRIC

—'

[

BIDIREC-

USED

P
Ll

UNT
A

—

;‘u‘)snm.
CONTROL

RECEIVE

BERIAL
LINE

DATA

INTERRUPT
LOGIC

POWER-FAL INTERAUPT TO LEFT _CiU

REAL-TIME
WNTERF ACE

INTERRUPT l
LOGIC

INPUT

AXTX NI FRALP T

INTERAUPT
AT AX/TX

e -

CONTROL BIGNALS

TO LEFT AMD RIGHT CPUB

PRO-10N

CONBOLE

INTERAUP s

TO RIGHT CPU (BEQ)
»

BIDIRECTIONAL

DATA BUS

BIDIREC-

DONE

AG INPUT
TO CONBOLE

E%NAL

CONTROL

RIGHT CPU (DEC)

VAX $880 POWER SYBTEM

HIGH
RIGHT CPU HIGH TRIC

MODULE

TEMPERATURE SENSE ——J

DATA

RIGHT CPU LOW TRIC

[ ranswar

BIDIAECTIONAL

l_ VOLTAGE SENSE

INTERRUPT
LOGIC

POWER-FAIL_INTERRUPT TO RIGHT CPU
VBUS DATA

SERIAL NUMBER

CPY REVISION
VBUS

SHIFT/ADDRESS

\——- CLOCK MODULE REVISION
A

AR HNIM*—J

%"T

AC POMER

DISTRIBUTION

ENVIRONMENTAL
MONITOR

scLD-270

Figure

2-1

Console Subsystem Functional Block Diagram

2.2.1
The

Programmable

PPI

contains

address,

and

system.

The

synchronize

the

PPI

bus.

2.2.1.1

Port

and

from

Peripheral

three

control
PPI

are

circuitry

VAX

2-2

shows

CPU

between

the

(PPI)

that

connected

Eight-bit
8800

Interface
ports

signals

ports

Figure

the

8-bit

are
the

format

transferred

PPI

data
by

transfer
and

buffer,

interface

bidirectional

are

console

the

console

the

used

data,

VAX

8800

translator,

board

Port

port.

means

the

and

means

Data

bits

this

port.

MKV86-1265

2.2.1.2

Port

Figure

2-3

and

that

passed

enable/disable

interface,

and

Eight-bit

Table
to

address

2-1).
the

Bits

interrupts

and

<3:0>

console

console-to-CPU

mask

Port

Format

control

contain

address

decoder.

communications,

CONSOLE | SELECT | MASK
READ
GONE
KEY
INTRPTS | ENABLE

port

the

console.

(refer
to
information

address

Bits

enable

reads

MKV86-1266

Figure

2-3

PPI

Port

11T 2-3

Format

<7:4>

from

the

Table

2-1

PPI

Port B Bit Description

Bit

Name

Description

<07>

CONSOLE GONE

0 = Console power 1s ON.
1

= Pulled up to "1" by clock module,
when console power is OFF, or
when any of the cables connecting
RTI

the

clock module

are

disconnected.
<06>

SELECT

KEY

Provides multiple use of

(mask

interrupts)

INTRPTS

MASK

and READ ENABLE bits.

0 = MASK INTERPTS and READ ENABLE bits
perform normal functions.
1

= MASK

INTERPTS

serves

the

KEY DATA

The

key

and READ ENABLE serves the

function,

function.

KEY CLOCK

data

and key clock signals are used in
the unlock

sequence of

console

isolation.
<05>

MASK

(Mask

INTERPTS

Interrupts)

Function determined by SELECT KEY bit.
If the SELECT KEY bit is a "0", this bit
masks all interrupts from the console

If the SELECT
interface to the console.
the READ
and
KEY bit is a "1", this bit
ENABLE bit enable console-to—-CPU communications.

nterrupts

SELECT

KEY

11T

2-4

0
1

are

not masked.

The mask bit
Interrupts are masked.
must be set prior to a read/write

= Normal mode, no action.
= Provides a serial data input to the
shift registers that enable the
console sequencer following a console
power failure or cable disconnect.

Table

Bit

Name

<04>

READ

2-1

PPI

Port

Bit

Description

(Cont)

Description
ENABLE

Function
If

the

determined

SELECT

initiates
console

bit

with
the

KEY

read

MASK

INTERRUPTS

interface

KEY

Enable

console

SELECT

KEY

input

enable
a

bit

the

SELECT

KEY

conjunction

bit,

and

bit.

this

unlocks

enables

communications.

read

Clock
ing

the

initiate

this

KEY

"0",

from

bit,

"1",

SELECT

sequence

interface.

console-to~-CPU

the

SELECT
is

console

Read

bit

toggled

from

sequencing

control

interface.
=

the

PRO-38N

the

shift

console
power

registers

sequencer

failure

used

followcable

disconnect.
<03>

CLK_MOD

ADRS

<3:0>

(Clock

Module

Address)

Four-bit

decoder

II1

address

2-5

the

console

address

interface.

2.2.1.3 Port C ——- Eight-bit bidirectional status and
Bits <3,
2-2).
Table
and
2-4
Figure
to
(refer

control

port

5, and 7> are
Bits <6 and 4>

read-only bits that display PPI status information.
used by the console's I/0 driver to control interrupts during
are
are
<2:0>
RBits
data transfers to and from the console interface.
programmable bits used for the detection of RTI power-up diagnostic
(LOOPBACK
test
Bit 0 enables the console interconnect
execution.
A).

Bit 1 enables the

interface data path test

-OUTPUT ;L'\J."PTT

INPUT

S.S;/T

BUF FULL

ENABLE

BUF FULL

RUPT TO |-RTI

ENABLE

(LOOPBACK B).

Egépc_"\'

NOT

PRO-38N |DIA MODE BACK

USED
MKV88-1267

Figure

Table 2-2
Bit

Name

2-4

PPI

Port

Format

PPI Port C Bit Description
Description

<07>

-OUTPUT BUF FULL
(Output Buffer
Full)

0 = PPI Port "A" output buffer contains
data for the console interface.
1 = PPI Port "A" output buffer is empty.

<06>

XMT RUPT ENABLE
(Transmit

0 = Disables interrupts to the console,
when PPI Port "A" output buffer is

Interrupt

Enabled)

empty.

1 = Enables

interrupts to the console,
PPI

when the
is

Port

"A"

output

buffer

empty.

<05>

INPUT BUF FULL
(Input Buffer
Full)

0 = PPI Port "A" input buffer is empty.
1 = PPI Port "A" input buffer contains
data from the console interface.

<04>

RCV RUPT ENABLE
(Receive

0 = Disables interrupts to the console
when the PPI Port "A" input buffer

Enable)

1 = Enables

Interrupt

full.

interrupts to the console

when the PPI
is

full.

Port

"A"

input

buffer

Table

Bit
<03>

<02>

2-2

Name

Port

Bit

Description

(Cont)

Description

RUPT

TO PRO-38N
(Interrupt to

Inactive
PRO-38N.

PRO-38N)

Active

Real-time

-RTI

DIA

(RTI

Diagnostic

MODE

Mode)
<01>

PPI

ENABLE

LOOPBACK

interrupt

are

Loopback

disabled.

Loopback

enabled.

IIT

VAX

2-7

8800

the

power-up

executing.

Normal

request.

interface

diagnostics

request

console

operation.

2.2.1.4
8-bit

two

2-5
bit
the

PPI

Control

control

word

The

PPI

controlled

The

control

word

programming
register

performs

functions

selected by the MSB of the register (refer to
Figure
and
Table
2-3).
When the MSB eguals 0, the CWR controls the
set and reset functions of PPI Port "C".
1If the MSB equals
1,
CWR selects the modes of operation of Ports "A", "B", and "C".

CAUTION

The

control word register should never be written to by
anything other than the console's I/0 driver or VAX 8800

diagnostics.

Writing to this register using either the BIT SET/RESET
function or the MODE SELECT function can cause damage to
the RTI or clock module hardware.
Reading

PPI
data

and

unknown
The

2-5

control

places

the

shows

word

drives

the

bus

the

clock

the

control

data

handshaking

accordance

with

the

undefined

signals

into

state.

contents

when

Figure

the

specification

the

read.

control

word

after the system has been booted.
altered except by
the
console's

word

diagnostics.

IIT

2-8

are

not

returned

should

appear

configuration should not be
driver
and
the
VAX
8800

CONTROL WORD REGISTER (WRITE ONLY)
PRO-38N ADDRESS = 17775216 (OCTAL)

CW FUNC

A MODE

Al/-O
0

Cu /-0 | B MODE

B1/-O

CL 1/-0

MKV86-1268

Figure

Table

2-3

2-5

PPI

Control

Bit(s)

Name

Description

07>

CW FUNC

(Control Word
Function)

= Mode select
and "C")

<05:06>

A MODE (Port "A"
Mode Control)

<04>

A I/-0 (Port
Input/Output

Must

<03>

I/-0

Upper

<02>

"A"
Mode)

set

and

(Ports

(Strobed

1 This bit is
RTI ROM only

reset

"A",

"B",

Bidirectional)

used

the

"C"

Output

I/0)

Input

= Basic input/output (outputs
latched, inputs unlatched, no

handshaking)
Strobed input/output

"B"
Mode)

0
1

=
=

Output
Input

(Port

"C"

Output

bits

I/0)

Input

<01>

B I/-O0 (Port
Input/Output

<00>

= Mode

bit

(Port

B MODE (Port "B"
Control)

I/-0

"C"

Description

bits

Mode

Lower

Port

Format

ITIT

2-9

2.2.2

Serial

line

the

Line

port

Port

"A"

provides

environmental

supply.

major

component

programmable

communications

the

communication

method

three

for

programmable

transmitting

the
the

module
serial

interface

between

registers.

and

conscle

monitoring

the

data

line

communication 1link
the
VAX 8800 power

port

(EPCI).

console

Three

receiving

with
1in

and

the

enhanced

The

ECPI

controls

and

the

EMM

registers

are

used

reading

status

from

the

EMM,

2.2.2.1

ECPI

Registers

between

the

console

and

command

defines
received.

the

Mode

required

Mode

The

ECPI

the

EMM

controls

with

format

all

(Figure

the

two mode

(Figure

2-6

messages

2-7

through

hardware

and

Table

communications

registers
and

and

Table

one
2-4)

transmitted

2-5)

defines

the

clock
source,
internal
baud
rate
generator
frequency, and the
receiver/transmitter clock baud rate factor.
The command
register
(Figure
2-8
and
Table 2-6) enables/disables loopback testing and
data transfers, and resets error flags in the status register.

MODE REGISTER 1 (READ/WRITE)
PRO-38N ADDRESS = 17775244 (OCTAL)
07

STOP BITS
1

PARTYP | PAREN

CHAR LENGTH

M/B FACT
O

i
MKV86-1269

Figure

2-6

ECPI

IIT

Mode

2-10

Table

2-4

ECPI

Mode

Bit(s)

Name

Description

<06:07>

STOP

BITS
(Number of
Stop Bits)

0=1.5

<05>

PAR

TYP

(Parity
<04>

PAR

Type)

(Parity

Enable)

Stop

Don't

Bit

care

bit

Disable

Enabled

Description

bits

(Parity

<02:03>

CHAR

LENGTH
(Character Length)

8-bit

<00:01>

M/B

FACT

(Mode

and

Baud

Rate

Asynchronous
and

Factors)

disabled

characters

Unity

communication

baud

rate

NOTE

The

required

1.5
length,

stop

Mode

bits,

format

for

parity

EMM

communications

disabled,
8-bit word
asynchronous communications,
and
a
unity
baud rate factor.
This configuration is programmed
by writing 215 Octal to mode regis
ter 1.

IIT

2-11

MODE REGISTER 2 (READ/WRITE)
PRO-38N ADDRESS = 17775244 (OCTAL)

]

[

BAUD RATE SEL

RCV/XMT CLOCK

0
MKV86-1270

ECPI Mode 2 Register

Figure 2-7

Table 2-5

ECPI Mode 2 Register Bit Description

Bits

Name

Description

<04:07>

RCV/XMT CLOCK
(Receiver and

0011

BAUD RATE SEL

1110 = 9600 Baud

Internal clock source
Unity baud rate factor

Transmitter Clock)

<00:03>

(Baud

Rate

Select)

NOTE

Console communications with the EMM require setting
internal clock source at 9600 baud with unity
the
This is accomplished by writing
baud rate factor.
076

{octal)

to mode register 2.

for register access.
Mode registers 1 and 2 use the same address
alternating access to
allows
An alternating mode register pointer
s. The pointer can
operation
e
the registers during normal read/writ
with either a RESET
1
initialized to point to mode register
be
command, or a read command register operation.

ITT

2-12

The
and

command

receiver,

reset

used

signals into the high
command
register
is
to
condition

deasserted.

set

for

enable

flags

error

key

low

the

state.

have

disable

following

normal

operation.

transmitter

Normal

operation

loopbacks

The

the

status

disabled

drawing

and

shows

the

OP MODE

1/0

Figure

Bit(s)

Name

<06:07>

2-6

ECPI

RTS

Request

<04>

RST

FRC

Data

1/0

Command

1/0

Bit

Mode)

Description

Normal

Local

Loopback

enabled

(all

characters

echo

operation

Disabled

Enabled

Reset

not

Reset

status

Send)

Error)

bit

Control)

(Force

Terminal

flags
0

Normal

Receiver

disabled

Receiver

enabled

Disabled

Enabled

Transmitter

disabled

Transmitter

enabled

operation

Ready)

<00>

XMT

CTL

(Transmit

Control)

ITT

2-13

back)

enabled

Break)

CTL

DTR

(Force

(Receiver
<01>

ECPI

Command

BRK

(Force
RCV

write-only

<02>

2-8

ERR

(Reset

<03>

1/0

MODE

FRC

Description

(Operating

<05>

Table

break

command

COMMAND REGISTER (ACCESS AS SPECIFIED)
PRO-38N ADDRESS = 17775246 (OCTAL)
07

force

for

error

2.2.2.2
uses
RTI

and

holding

from

Data

Transfer

three

the

buffer

the

and

registers
EMM

(refer

Status

for
to

Fiqgure

EMM.

The

transmit

holds

data

that

8-bit

and

status,

receiver

and

done

data

transmitted
data

shift

The
and

serial
status

and Table 2-7).
buffer that holds

holding

transmitter

ready

2-9

data

,,,,,,,,,,,,,,,,,, ,

detect

Registers

transferring

set

ready

line

port

between

the

The
data

receive
received

1is

8-bit

the

EMM.

The

and

status,

data

and

06
]

bits.

]

DATA RECEIVED FROM THE EMM
l

]

TRANSMIT HOLDING REGISTER (WRITE ONLY)
PRO-38N ADDRESS = 17775240 (OCTAL)

06
1

05
1

04
I

03
I

DATA TO TRANSMIT TO THE EMM
|

STATUS REGISTER (READ ONLY)
PRO-38N ADDRESS = 17775242 (OCTAL)

DSR

DCD

FRA ERR | OVR ERR | PAR ERR | XSR EM

|RCV DON

|XMT RDY

MKV86-1272

Figure

2-9

Serial

Line

Port

Data

and

Status

carrier

transmitter

RECEIVE HOLDING REGISTER (READ ONLY)
PRO-38N ADDRESS = 17775240 (OCTAL)
07

data
status

Registers

Table

2-7

Serial

Line

Bit

Bit
07>

<06>

Name

<03>

<02>

DSR

(Data

DCD

Input

Ready)

active

DCD

Input

not

DCD

(Data

FRA

Detect)

ERR

Error)

OVR

ERR
(Overrun

Error)

PAR

DSR

Input

DSR

Input

Error

Error
No

error
Error

XSR

Shift

<00>

DSR

XMT

shift

Done)

DSR

active

not

DSR

DCD)

RCV

DON
(Receiver

active

not

change

Empty/Change

active

Error

ERR
(Parity Error)

Registers

error

(Transmitter

<01>

Status

Set

(Framing
<04>

Data and
Description

Description

Carrier
<05>

Port

empty/No

DCD

empty/Change

DCD

Rcvr

holding

Rcvr

holding

empty

full

RDY

(Transmitter

Xmt

holding

full

Xmt

holding

empty

ITIT

2-15

Ready)

2.3

CONSOLE

INTERFACE

The console

interface provides the console and the VAX 8800

8800

system.

system

cConsoie

-LN

1in T e

£ L

—~

ace

a medium for communication with, and control of, the VAX 8800
with
real-time
the
from
received
Data and control signals are
CPUs.
of the
areas
¢
the console and distributed to specifi
1l n
interface
T

~adl

nEir~l

CcoOntro.L,

10Cading,

The primary functional

areas of

Buffer,

translate,

Console

address

nAd
an
“

the console

+he

cne

VAY

VAX

interface are:

and synchronization circuitry

decode

Console sequencer (CSEQ MCA)
Terminal register interval clock
'
Data output mux
CPU

(TRIC MCA)

registers

control

Visibility bus
Console interrupts
Power

status

2.3.1

Buffer Translate and Synchronize

being

placed

The buffer translate and synchronize
logic
buffers
the
incoming
signals
from
the
console and provides translation of the console
output signals from TTL to
ECL
logic.
The
translated
data
is
applied to the TRIC MCAs, control registers, VBus control and clock
control logic.
The lower four bits
of
the
translated
port
"B"
address data are applied to the address decoder where they are used
in the generation of control
signals
for
the
operation
of
the
console
interface.
Most of the signals coming from port C or the
upper four bits of port B are synchronized
to
the
VAX
8800
CPU
clocks
after
being
translated
to ECL logic levels.
Control and
data to the console is translated from ECL to TTL
1logic
prior
to
in

the

output drivers.

2.3.2 Console Address Decode
The address decoder logic uses the lower four
bits
<K3:0>
of
the
incoming
port "B" address from the PPI to generate control signals
for control registers <2:0>, VBus
control,
the
clock
registers,
console receive data buffer, and the console load paths to the CPU.

The address decoder
ready

and

receiver done

also used
signals

for

IIT 2-16

the

VAX

generation
IPRs.

transmit

2.3.3
The

Console

console

control

point

acknowledge
transfers

control

MCA

include:

the

console

generated

well

creation

and

RAMs.

Major

Console

read

interrupt

Console

write

sequencing

Control

store

load

generation

(IPR)

Receive

loading
by

and
data

the

VAX

the

CSEQ

data

and
The

TRIC

control

use

the
MCAs

required

include:

Buffer

(TRIC)

TRIC

MCAs

make

MCA

transfer
interface and the

console

CPU

Clock

two

the

implement

VAX
the

internal

transfer

CPU.

processor

process.

The

IPR

Receive

Data

Receive

Control

Transmit

and

(

RXDB

Status

<15:0>

)

(

<7:0>

RXCS

)

IPR

Transmit

Data

Transmit

Control

Interval

Figure

VAX

CPUs

between

both

for

performed

timing

registers

one

isolation

address

8800

flags

functions

strobe

sequencing

mechanism

CPU timeout
1 MHz clock

VAX

Synchronized
proper

command

input/output

generation

CPU

write

the

data

sequencing

Console/VAX

signals

for

store

combination
IPRs

<centralized

interface.

Console

the

control

the

are

Terminal
of

for

CPU

2.3.4

(CSEQ MCA)

MCA

signals
as

8800

Each

Sequencer

sequencer

Buffer
and

(

TXDB

Status

<15:0>

)

(

<7:0>

TXCS

)

Clock

®
®

Interval Count Register ( ICR <30:0> )
Interval Count Register ( NICR <31:0>

Interval
2-10

shows

configuration

Clock
the
each

Control/Status

IPRs

contained

11T 2-17

TRIC

(

)

ICCS
MCAs,

<31:0>
and

the

)
bit

CONSOLE WRITE ONLY - CPU READ ONLY

RECEIVE DATA BUFFER (L/R RXDB)

15
DATA

OVER

ID3

ID2

IDO1

IDO

RUN

HIGH TRIC

LOW TRIC

]

00
T

DATA <3:0 >

DATA <7:4>
|

01
T

HIGH TRIC

LOW TRIC

TRANSMIT DATA BUFFER (L/R TXDB)

CONSOLE READ ONLY - CPU WRITE ONLY

ID3

ID2

ID1

IDO

HIGH TRIC

LOW TRIC

DATA <7:4>
]

géfig

READ

LOW TRIC

DATA BUFFER CONTROL/STATUS (DBCS)

00
|

DATA <3:0>

HIGH TRIC

EE(ESY

RXDB

INTRPT

ENABLED

READ/WRITE

READ

ONLY

READ/WRITE

02
TXDB

INTRPT

ENABLED

READ/WRITE

ONLY

Figure

2-10

RXDB,

TXDB,

and

DBCS

The

data

bits

buffer

the

control/status

RXCS

common

<7:6>

are

8800
Input

mapped

microcode
and

output

transferred

decoder.

(program

formed

two

the

RXCS

<7:6>

are

into

DBCS

<3:2>.

compatible

data

between

over

The

and

control
console).

8-bit

process

bits

mapped

The

with

the

VAX

into

DBCS

bits

are

VMS.
CPU

and

bidirectional

bus

determined

TXCS

combining

<7:6>,

and

reformatted

the

TRIC

connected

the

two

into

TXCS

VAX

MCA

the

CPU

operating

mode

2.3.4.1

Program Mode -- Data from the console to
the CPU
is
under
interrupt
control
using the DONE bit from the receive data
buffer
in the High slice TRIC MCA.
The
transmit
data
buffer
wuses
the

READY

bit

transfers

the

low

slice

TRIC

console.

11T 2-19

for

interrupt

control

data

the
operation,
2.3.4.2 Console Mode —-- During the console mode of
the
of
status
the
READY and DONE bits to determine
the
polls
CPU
data

transfer registers.

buffers
The READY and DONE bits from the receive and transmit data
These
MCA.
CSEQ
generator on the
interrupt
the
to
applied
are
the
to
signal
strobe
interrupt
an
create
signals are used to
are
signals
same
The
console for use in the data transfer process.
the
identify
to
flag
a
as
also applied to the data output mux
source

the

2.3.5

Data

interrupt.

Output

Mux

of
The data output mux is the centralized collection point for all
console
the
from
<console
the
to
going
status
and
data
the
are
Console address bits <3:1> determine which signals
interface.
Input signals to
the mux for output to the console.
in
selected
the mux

consist

of:

Right

TXDB data
TXDB data

VBus

data

Left

Interrupt

Clock

status

Left CPU timeout
Right CPU timeout
Clock module revision
CPU backplane revision
Serial number

The selected mux data is translated to TTL logic levels and sent to
the conscle by means of the 8-bit bidirectional PPI port "A" bus.

IIT

2-20

2.3.6

Control

The

console

CR2)

write-only

Registers

interface

control

console

and

from

console

the

uses

transfer

registers

the

registers

receive

the

Port

enable

strobes,

and

the

address

control

signals

latch

configuration

three

the

decoder

control

(CRO,

CRI1,

and

8800

CPUs.

The

VAX

"A"
data
the
from
register load commands

1logic.

Figure

registers

and

2-11

shows

identifies

configurations.

CONTROL REGISTER

CONTROL REGISTER
07

NMi
UNJAM

|ENABLE |
LFT RXDB|

NMI
SLOW

INTRPT

MODE

LEFT
CPU
INIT

G0
RIGHT
CPU
INIT

WRITE ONLY
02

HALT
LEFT

[ENABLE
|[TRAP ON

HALT
RIGHT

|INTRPT

CPU

RT MATCH

CPU

LTMATCH|

WRITE ONLY
04

Noeo | Uorp | Doep

CONTROL REGISTER
07

WRITE ONLY

ENABLE

DISABLE| DISABLE | CLEAR

BACK

WRITES | WRITES

SET CPU

FLAG

MKV86-1274

Figure

2-11

Control

ITT

2-21

Registers

the

the
bit

2.3.7

Visibility

Bus

Control

The visibility bus provides the console with
wvisibility
into
the
VAX
8800
system
and
enables
the console to monitor the sixteen
modules using the VBus.
Port "A" data from
the
console
controls
the selection of VBus signals through the use of the visibility bus
control register (Figure 2-12).
The VBus data
1s
read
from
the
VBus
access
register
and
muxed with the outgoing signals in the
output

mux.

VISIBILITY BUS CONTROL

WRITE ONLY

NOT
USED

SHR

SLC1

VBUS
DATA

\/BUIS
DATA

STEP
B
CLOCKS

VBUS
ADDRESS
[OUTPUT

SEQ

WCS

VRBUS
DATA

vBUS
DATA

READ ONLY

SLCO

ADP

VBUS
DATA

SELECT
|STEP
RHT CPU | ADDRESS|
INPUT
SHIFT

VISIBILITY BUS ACCESS
o7

VBUS
DATA

CCS

VBUS
DATA

DEC

VBUS
DATA

MKVE6-1275

Figure

2-12

VBus Control

i~
=t
[

data

and Access Registers

2.3.8

Console

Console
events.

having

Interrupt

interrupts
The

the

NMI

events

highest

Generation
occur

are

from

listed

any

one

the

following

priority

sequence

external

with

NMI

priority:

five
reset

Reset

request

system

from

halt

and

TXDB

Not

Ready

TXDB

Not

Ready

processor

reboot

VAX

transmit

8800

CPU

has

data

placed

Not

Done

(Primary

RXDB

Not

Done

(Secondary

the

buffer

Requests

for

interrupt

placed

VAX

8800

processor(s).

CSEQ

data

for

the

console

into

CPU)
CPU)

the

empty

console
the

the

8800

buffer.

RXDB

data

VAX

CPU)
(Secondary CPU)

the

The

the

(Primary

The

generator

receive

and

ready

interrupt
module,

data

for

are

which

buffer

another
passed

handles

the

data
to

transfer.

the

from

the

ACLO

signal

used

The

clock

Status
interface

EMM

and

receives

translates

a
the

copy

signals

interrupt

sequencing

request.

2.3.9 Power
The console

bits

can

the

ACLO

and

ECL

logic

DCLO

signals

levels.
is synchronized with the VAX 8800
CPU
<clocks
and
generate the power-fail interrupt to the VAX 8800 CPU.

synchronized

control

initialization

signal

DCLO signal is
register
0,

CPU

INIT.

ITT

2-23

used to
assert
including
the

all
CPU

the

The

of
the
hardware

2.4 CONSOLE/VAX 8800

INTERACTION

the console
The following paragraphs describe the interaction of
control,
read/write
and the VAX 8800 system during initialization,
and data

2.4.1

transfers.

Initialization

The console controls the operations required to get the VAX 8300
involved in this
Major tasks
system powered up and running.
process

include:
Turn

"ON"

Reset

EMM

Console

system power

power

Load and run console power software
Sequenced power application

Initialize hardware
Test and checkout
Load RAMs and DRAMs

The initialization process is presented in detailed flowchart form,
The
and the events are shown in the sequence in which they occur.

command
flowcharts include a combination of operator commands,
They are intended to
and hardware actions and responses.
files,
At the
show the sequence of events that occur during a process.
the flowcharts is a table listing some of the key signals
end of
a
1is
Included
in the flowcharts.
identified
and functions
description of the signal and the logic circuit where the signal is

processed.

2.4.1.1 Turn ON and Monitor System Power/Reset EMM

The

events

initial turn-on of power to the VAX 8800 system,
the
in
involved
and the subsequent resetting of the environmental monitoring module
These events are controlled by
are shown in Figures 2-13 and 2-14.

system
power
the
to
Refer
complex.
the VAX 8800 power system
a complete description of the events
for
the manual
of
section
shown

in Figures
-

LV
S
)

2-13

and

2-14.

IIT

2-24

TURN ON AND
MONITOR SYSTEM

POWER

MAIN

BREAKER ON

v
AC VOLTAGE TO CSP,
BBU, AND CONSOLE

v
+/-

TO ILM

AND +5

AND BUW .

Y
+5

V TO NBT

!
PERFORM MODULE
KEYING TEST

Y
+10.5 V TO MPS
BACKPLANE

v
FAIL SAFE
ENABLE TO BBU

!
-MOD A INTERLOCK
T0 BvW

(

RESET Bw )
SCLD-221

Figure

2-13

System

ITT

2-25

Power-0On

Sequence

RESET EMM )
|

v
RUN SELFTEST

;

LOAD DEFAULT
PARAMETERS
BOM TQ BAM

BEGIN AUTC
SHUTDOWN
MONITORING

WAIT-CONSOLE TO
COMMUNICATE
WITH

BUWM

(CONSOLE POWER ON)
{

SCLD-222

tal Monitoring Module Reset Sequence

2.4,.1.2

"1",

the

with

the

events

Console

Poweron

-—

begins

console

VAX

8800

power

that

occur

when

Professional

300

Series

When

the

selftest

console

the

sequence.

Figure

the

power

console

handbooks

for

power

switch

PRO-38N

before

continuing

2-15

shows

the

applied.

additional

POWER SWITCH
SET TO 1

RECEIVE DCOK
FROM CONSOLE
POWER SUPPLY

4
RECEIVE POK
FROM CONSOLE

POWER SUPPLY

h 4
RUN SELFTEST

LOAD AND RUN
CONSOLE POWERUP
SOFTWARE
SCLD-223

2- 15

Console

11T

2-27

Power-On

Refer

information.

(CONSOLE POWER ON)

Figure

set

Events

major

the

2.4.1.3 Load and Run Console Power-Up Software -- When the VAX 8800
main
cabinet
power
switch is turned on, the power supply and the
environmental monitoring module are
waiting
for
control
signals
from

the

console

proceed

Preliminary tasks of the console
with

the

EMM

with

macrocode

the

power-on

require

sequence.

communication

to:

Establish and test communications
Send environmental parameters to the EMM RAM
Enable EMM monitoring tasks
Enable sequenced power application to VAX 8800

modules

Serial data is transferred between the console and
EMM
using
the
transmit
and
receive holding registers in the serial line port of
the RTI.
Figure 2-16 shows a simplified drawing of the
three
key
registers
in
the
serial
1line
port.
Figure 2-17 identifies the
events that occur during the loading and
running
of
the
console
power—-up

software.

-—

TRANSMIT HOLDING REGISTER

RDY

SERIAL DATA
. TO/FROM EMM

-y

REE mlm o|

CONSOLE DATA TO EMM

STATUS

RECEIVE HOLDING REGISTER

DONE

’

Figure

2-16

Serial

Line

Port

11T

2-28

EMM DATA TO CONSOLE

Data Transfer Registers

Bits

and

status

Table

2-8).

the

Table

2-8

status

holding

Serial

Name

Description

<01>

DONE

Receiver
and

<00>

READY

holding

ready

character

from

holding

contains

the

last

the

EMM.

Transmit

EMM

the

not

character

vet.

Transmit

holding

The

EMM

has

and

the

another

IIT 2-29

the
to

empty
data

EMM.
still

character

another

taken

of
(refer

Registers

holding

has

console

transfers

Receiver

The

the

data

Line Port Data Transfer
Bit Description

Bit

inform
during

the

last

ready

for

placed

full.

last

empty.

character

accept
transfer.

LOAD AND RUNCONSOLE POWERUP
SOFTWARE

INITIALIZE
DATABASE

SPAWN RTI
DRIVER

ISSUE ASYNC

QIOS

VERIFY

BMM

COMMUNICATIONS

VERIFY BMM REVISION
COMPATIBILITY

LOAD SPECIFIC
PARAMETERS IN
RAM

(TO

SHEET 2)
SCLD-225

Figure

2-17

Load/Run Console Power-Up
(Sheet 1 of 2)

I1T 2-38

Software

Events

(FROM SHEET 1)

RESTORE CONSOLE
STATE FROM
LOGFILE

CHECK STATE FOR
PREVIOUS POWERUP
ABORT

CHECK STATUS
(MOD OK, ACLO,
AND DCLO)

SEE IF
CONSOLE-ONLY
POWER FAILURE

SET SYSTEM INIT
IN PROGRESS FLAG

SEQUENCED POWER

APPLICATION

SCLD-226

Figufe 2-17

Load/Run Console Power-Up Software Events
(Sheet

ITT

2-31

2.4.1.4

Sequenced

application

Application

Power

The

sequenced

power

consists of a series of software commands to the power

es to the
system that enable the module regulators to apply voltag
Response from the previous command is
various VAX 8800 components.
required to proceed to the next event in the sequence. Figure 2-18
ijdentifies

the

ad
criac

occur
e

durlng
.

the power application

phase.

SEQUENCED POWER
APPLICATION

v
CHECK AUTO
POWER ON

CHECK EMM/CONSOLE
INTERRUPT (-MOD OK)

TELL BW TO

BEGIN SEQUENCED
POWERON

TURN ON

REGULATED VOLTAGE

TO _MOD J

‘______

VOLTAGE TO FAN
AND AIRFLOW
SENSORS

DEASSERT AC LO

WHEN 300 V BUS =

200 _V

(TO SHEET 2)
SCLD-227

Figure

2-18

Sequenced Power Application Events (Sheet 1 of 4)

111 2-32

(FROM

SHEET 1)

CLOCK OPAMPS RECEIVE +12

v
CONSOLE RECEIVES

MOD J

i
TELL

EMM TO TURN ON REGULATED B 45

v
MEMORY GETS +5B (COLD STATUS SAVED)

|
DEASSERT NMI

BAT DC LO

Y
BATTERY BACKUP RECEIVES ENABLE AND 48 V

v
CONSOLE RECEIVES MOD B STATUS OK

v
TELL BMM TO TURN ON REGULATED +5C

y
CLOCK, MEMORY, AND NBIAS GET +5 V

(TO SHEET 3)
SCLD-228

Figure

2-18

Sequenced

Power Application

ITTI

2-33

Events

(Sheet

(FROM

SHEET 2)

!
CONSOLE RECEIVES MOD C STATUS OK

Y
TELL BEMM TO TURN ON REGULATED F

v
VAXB! ‘1’

RECEIVES POWER

CONSOLE RECEIVES MOD F STATUS OK

TELL BMM TO TURN ON REGULATED H

'
VAXBI ‘*0''

RECEIVES POWER

]

CONSOLE RECEIVES MOD H STATUS OK

TELL BMM TO TURN ON REGULATED E -5.2 V

;

CLK, CPU, MEM, AND 1/0 RECEIVE -5.2 V
i

(TO SHEET 4)
SCLD-229

Figure

2-18

Sequenced

Power

Application

ITT 2-34

Events

(Sheet

3 of

(FROM SHEET 3)

v
CONSOLE RECEIVES MOD E STATUS OK

v
TELL

BMM TO TURN ON REGULATED D -2

'
CLK,

CPU,

MEM, AND I/0O

RECEIVE -2

'
CONTROL REGISTER 0

ASSERTS CPU INIT

CONSOLE RECEIVES MOD D STATUS OK

POWER-ON SEQUENCE COMPLETE

( HARDWARE

INITIALIZE

>
SCLD-230

Figure

2-18

Sequenced

Power

Application

IIT 2-35

Events

(Sheet

2.4.1.5 Initialize Hardware -- When the sequenced power application
process
1is
complete,
the
console
software must ensure that the
console interface
is
1initialized
and
ready
for
communications
between
the
console and the VAX 8800 CPUs.
The first step in the
initialization process involves verifying the
communications
path
with
a
console
interconnect
loopback and an interface data path
loopback.

The two tests allow the console to test data, address, and
control
paths between the console and the console interface, as well as the
data path between the console and the VAX 8800 CPUs.
Enabling
the
tests
requires
modification of the ECPI command register, the PPI
control word register, bit 4 of control register 2, and
bit
1
of
PPI

port

"C".

CAUTION

The control word register should never be written
to by anything other than the console's I/0 driver
or VAX

8800

diagnostics.

Writing to this register using either the BIT
SET/RESET function or the MODE SELECT function can
cause damage to the RTI or clock module hardware.
Reading the control word register in accordance
with the PPI specification will drive the data bus
with undefined data and place the clock handshaking
signals

into

an unknown

state.

The contents of the control word register are
returned when the register is read.

not

The console interconnect loopback test verifies
the
operation
of
the PPI ports through the console interface.
Figures 2-19 and 2-20
show simplified block diagrams of the bits
and
signalis
that
are
verified.

IIT 2-36

PPI
PORT ““A'"

CONSOLE INTERFACE
DATA OUT

<7:0><¢

TTLEGL
8
|

PORT
‘‘B'' <20
<5:0
©

PORT **C’"

TRANSLATE ~<510>“—!J

! AND

<7:5>

»|

| OUTPUT BUF FULL

DECODE

INPUT

BUF

FULL

SCLD-231

Figure

2-19

Console

Interconnect
Ports

PPI

PORT ‘' C

Loopback
and

Testing

Through

CONSOLE INTERFACE

<6:4>

€4—

TTLECL

MUX

PORT ‘“‘B’'’

<7,6>

TRANSLATE
AND

—<7.6>

DECODE

PPI

CONTROL

SCLD-232

Figure

2-20

Console

Interconnect
Ports

ITT

2-37

and

Loopback
C

Testing

Through

The

interface

link

between

data

path

the

console

same data path that is
unbuffered data to and

loopback
and

the

test
VAX

verifies
8800

the

CPUs.

communication

The

test

wused
in
transferring
both
from the VAX 8800 system.

uses

buffered

the

and

Figure 2-21 shows the two-step procedure for testing the unbuffered
data
path used in loading the VAX 8800 control store.
Figure 2-22
shows the procedure for testing the buffered data path through RXDB
and

TXDB.

CONSOLE INTERFACE

ADDRESS Lgfig
REGISTER

PPl
1 TRANSCVR

WRITE <7:0>

OF PORT ‘*A’’
OUTPUT LATCH

»|

—

ADDR
DECODE

C
TXDB

CONSOLE INTERFACE
PPI

ADDRESS THE

TRANSCVR

Ald—

TXDB AND READ

<7:0> OF PORT ““A"’
INPUT LATCH

__»|

ADDR
DECODE

C
TXDB

SCLD-233

Figure

2-21

1Interface

Data

Path

Loopback

Test

Unbuffered

Data

CONSOLE

INTERFACE

ADDRESS THE
RXDB AND
WRITE <7:0>
OF PORT "*A
TM"
OUTPUT LATCH

RXDB

TRANSCVR

ADDR
DECODE

TXDB

CONSOLE INTERFACE
PPI

ADDRESS THE
TXDB AND
READ <7:0>
OF PORT “*A’"
INPUT LATCH

RXDB

TRANSCVR

ADDR
DECODE

TXDB

SCLD-234

Figure

2-22

Interface

Data

Path

Through

During

powerup

console

and

testing

sequencer

(CSEQ)

subsystem
During

normal

console.

cable

the

signal

CPU.

VAX

8800

operation,
the

connecting

pullup
GONE

from

the
and

bit

Loopback

RXDB

the

console

PPI

the

PPI

bit

all

Buffered

interface
to

the
at

clock
the

2-39

driven

power

failure

module

1is

clock

console

IIT

port
a

module

operations

Data

hardware,

isolate

CPU.

experiences

disables

Test

TXDB

disabled

PRO-38N

line

and

console

low

the

that

the

console

disconnected,

asserts

the

CONSOLE

could

affect

been
When the PRO-38N and the RTI power-up diagnostics have
by
CPU
the
completed, the console enables communications with
iplexer oOn
sending a sequence of serial data (KEY DATA) to a demultcontr
ols the
6)
bit
B
(port
l
signa
The SELECT KEY
the CSEQ MCA.
OCK
KEYCL
READ/
and
DATA
KEY
MASK/
two demultiplexers that allow the
signals to be used for two functions.

er by the KEY
Key data is clocked into the key circuit shift regist
Figure 2-23
s.
signal
INIT
and
unlock
the
es
CLOCK signal and produc
shows a simplified drawing of the CSEQ enable logic.

SYNCHRONIZER
LOGIC

PORT B <5>

MASK INTRPTS

PORT B _<6>

CONSOLE GONE

K
C

SEL

DEMUX
SEL

» READ ENABLE

—|

—» MASK INTRPTS

K EY

DATA

SELECT KEY
PORT B <7>

DEMUX

| S

PORT B <4>
READ ENABLE

——p|

DISAB
CSEQ

SHIFT

REG

)—
Po——

—

SET

JNIT
AN

RESET

UNLOCK
CSEQ

—

CLK
SCLD-235

Figure 2-23

Console Sequencer Enable Logic

Hardware

initialization

writing

the

EMM.

control

ACLO——»

DCLO

CPU

———»

INIT

Figure

2-24

THL

of
bit

the
of

VAX

8800

control

shows

simplified

initialization

CPUs

signals

block

are

performed
asserting

diagram

by
DCLO
how

generated.

ASYNC ACLO

YNCHRONIZER

ECL
ASYNG DCLO

LoGIC

| o

DCLO

|
»

INIT B LATCH

LaToH

LATCH

[

INIT

CNTRL ©

INIT

CNTRL 1

[

—P

—»>

SCLD-236

Figure

2-24

Control

11T

2-41

Initialization

The

initialization

8800

modules

the

known

system.

Figure

hardware

initialization

2-25

hardware

state

sets

prior

identifies

the

clock,

the

test

events

that

and

console,
checkout

occur

and

VAX

the

during

process.

INITIALIZE
HARDWARE

'
CONSOLE RUNS LOOPBACK TESTS WITH CLOCK

'
INITIALIZE

RT!

DRIVER

DATABASE

'
ENABLE CONSOLE INTERFACE SEQUENCER

'
SET CLOCKS ‘*ON"’

y
HRDWRE INIT

INTERFACE,

CPU,

AND NBIA'S

v
TELL

BWM TO DEASSERT LAT

DC LO

v
CLOCK RECEIVES

-CPU

DC LO

v
MEM RECEIVES -NMI

(TO

DC LO

SHEET 2)
SCLD-237

Figure

2-25

Hardware

Initialization

11T 2-42

Events

(Sheet

the

(FROM SHEET 1)

I/0

RECEIVES -NMI

DC LO ON NBI

TELL

BEMM TO DEASSERT LAT AC LO

CLOCK RECEIVES -CPU AC LO

CPU DEASSERTS POWER FAIL

RECEIVES -NM!

AC LO NBI

TELL EMM TO BEGIN
DEFAULT MONITORING

v
CONSOLE DEASSERTS CPU INIT

HARDWARE INITIALIZATION

COMPLETE

< TEST AND CHECKOUD
SCLD-238

Figure

2-25

Hardware

Initialization

ITT

2-43

Events

(Sheet

2.4.1.6 Test and Checkout -- CPU module placement is checked using
a callable diagnostic routine that writes the address of a module
onto the VBus address path. The tail bit of the address 1is read
This procedure 1is
back in the VBus data path and verified.
in both of
modules
the
of
all
for
"O0"
and
"1"
a
both
performed with
the

CPUs.

After completion of the module placement test, the console proceeds
with

the revision sensing test.

Figure 2-26 identifies the events

that occur during the test and checkout process.

G EST AND CHECKOU'D
SET CLOCK PERIOD TO 50 NS

TEST VBUS, AND VERIFY MODULE PLACEMENT

DETERMINE MODULE AVAILABILITY

SET PRIMARY AND SECONDARY CPU
!

(TO SHEET 2)
SCLD-239

Figure 2-26

Test and Checkout Events (Sheet 1 of 2)

ITT

2-44

(FROM SHEET 1)

CHECK CLOCK AND CPU MODULE REVISION

v
CHECK CPU BACKPLANE REVISION

Y
CHECK EMM SOFTWARE & SERIAL NO.

REV.

'
CHK CONSOLE SOFTWARE & SERIAL

NO.

REV.

v
VERIFY ALL

REVISION

COMPATABILITIES

v
VERIFY

RAM PARITY

ERROR CHECK

!
SET ALL CLOCKS RUNNING

'
COMPARE MICROCODE REV.

WITH CPU KERNEL

LOAD RAMS
AND DRAMS

SCLD-240

Figure

2-26

Test

and

Checkout

ITIT

2-45

Events

(Sheet

2.4.1.7 Load RAMs and DRAMs
-The
<console
1is
responsible
for
loading
the
VAX 8800 microcode into the control store (CS2 - CS0)
located on the WCS and SEQ modules, IBox decoder RAMs (DRAMs),
and
the

NMI

control

store

located

The microcode

to be

and

by means

loaded

loaded
of

resides
the

WCS, and CCS.
The normal
cannot be used because of

the

CCS

module.

the

unbuffered

console
data path

Winchester

disk

SEQ,

the

DEC,

buffered
data
path
through
the
the lack of cooperating microcode.

IPRs

Commands and data are transferred to each CPU through the use of
a
command
load
register
and a data load register.
Data written to
either the command load or data load register is
actually
latched
into the micromatch register on the decoder module of the IBox.
During

the

stalls
and CPU
Parity
using

The

that

the

RAMs

are

error bits
VBus.

involved

being

the

NMI

loaded,

clocks

microsequencer

the

VAX

8800

RAMs

are

running,

disabled,

can

read

the

LOAD

time

and traps are disabled,
INIT is deasserted.

the

Control

Store

SEQUENCE

sequence

for

Write

physical

Point

VBus

+->

Write

]

the

control

segment

counts

parity

error

control

store

address

Write

control

store

Check

parity using

store

data

CS2

CSO

Dbits

the VBus

11T

for

is:

2-46

the

specified

address

(18

bytes)

PHYSICAL

SEGMENT

The

physical

each

RAM

segment

address

different

RAMs

that

The

must

Data

Command
Data

Load

RESETTING

The

RAM

that
be

prior

the

bits

The

command

ADDRESS

load

Load

the

Count

NMI

decoder

CSO

the

Write

equal

Write

the

counts

Write

The

Count

PSEG

contains

Count

PSEG

CS2

equal

are:

PSEG

CS1

equal

loaded.

1load

load

into

CS).

with

segment

store

module

being

loaded

control

Currently

currently

varies

five

Currently

MODE

the

are

Currently

MODE

number

Count

counter

counter must

process

writing

ADDRESS

than

The

bits

slice

sent

mode.

sent

can

bytes

and

MODE

Count

command

slices.

being

beginning
the

follows:
Command

PSEG

there

DRAM,

XXXX1110

byte

greater

slices

CSO,

for

PSEG

CS2

to
to

STORE

several

Address

CS1

the

XXXX1101

mechanism

CONTROL

COUNTER

BYTE

console,

PSEG

THE

reset

address

number
Because

XXXX1100

XXXX1000(binary)

bus

the

CS1,

the

CS0

points

WRITE

counts

Load

one.

(CS2,

Load

loaded

segment

Load

count
minus

loaded

physical

Command

COUNT

the
in

is
CS

any

loaded

means

field

points

control

store

the

address

latches.

order.

loaded

with

address

XXXX0001

XXXX0000l1

1is

Mode

loaded

Set

console

destination

enter

three

the

SET

slices

Address

Data

Load

011AAAAA

AAAAA

Address

<14:10>

Data

Load

010AAAAA

AAAAA

Address

<9:5>

Data

Load

001AAAAA

AAAAA

Address

<4:0>

111 2-47

WRITE CONTROL STORE

DATA

The control store is partitioned into three sections (Cs0, CSi, and
cs2) and data for each microaddress is loaded into each of the
sections in the following order:

First --- CSO
Second -- CSl1
Third --- CS2

Fach section 1is
significant byte

most
the
beginning with
in bytes,
1loaded
The
byte.
t
significan
least
the
and ending with

sequencer on the decoder module points to the byte currently

being

loaded.

The data load process begins by writing XXXX010l1 to set the command
load register mode, followed by 18 consecutive writes to the data
load register. 1If a RAM data segment written to the data load
register is less than 8 bits wide, the most significant bits are
"don't

care"

bits.

Command Load Register = XXXX0101
Data
Data
Data
Data
Data
Data

Load
Load
Load
Load
Load
Load

Register = Data for CSO0
Data for CSO
Register
Data for CSO0
Register
Data for CS0
Register
Data for CS0
Register
Data for CSO0
Register

<47:40>
<39:32>
<31:24>
<23:16>
<15:08>
<07:00>

Data for CS1
Data for CS1
Data for CS1
Data for CS1

<95:88>
<87:80>
<K79:72>
<K71:64>

Data Load Register
Data Lcad Register
Data Load Register
Data Load Register

Data for CS1

TAnA

Dantakar

Data Load Register = Data for CS2
Data
Data
Data
Data
Data

Load
Load
Load
Load
Load

<63:56>

Data Load Register
MNoadon

Mode = Write CS Data

Data
Data
Data
Data
Data

for
for
for
for
for

CS2
CS2
CS2
CS2
CS2

<142:136> -- (7 bits only)
<135:128>
<127:120>
<119:112>
<K111:104>
<103:96>

CHECK

The

PARITY

VBus

parity
module),
of

the

into

bits

the

decoder

CS0,

parity
least

access

error

CS1l,

error

bits

CPU

CS2

are

the

NMI

(VBA
(VBA

console

control
<2>

from

the

from

the

VBus

the

VBus

1interface

store

<1>

selected

digit

(refer

the

RAMs

and

significant

the

for

DEC
SEQ

2-27).

contains

<3>

from

module),
module).

address

Figure

(VBA

the

and

the

26(hex).
last

the

CCS

All

bit

04 -

SHR

SLC1

SLCO

ADP

ccs

DEC

SEQ

WCS

1
|

—

the

The

shifted

L— OR OF CSX PARITY ERROR (HI TRUE)
DRAM PARITY ERROR (LOW TRUE)
NMI CS PARITY ERROR (HI TRUE)

MKV86-1276

Figure

LOAD

When
on

FUNCTION

the
the

control

store
module

the

XXXX0000

VBus

Parity

has

been

loaded,

left

the

procedure

Bits

INACTIVE

decoder

starting

2-27

machine.
the

command

data
must

This
load

IIT

2-49

the

inactive

mechanism

state

performed

prior

writing

LOAD

the

Decoder RAMs

SEQUENCE

Machine Executing Nonfunctional Loop

Hardware
Write

initialization

DRAM physical

Point VBus

+-->

)|
|

(CPU INIT)

segment count

to parity error bits

Reset

byte

counter

Write

DRAM

address

Write DRAM data (3 bytes)
Check parity using VBus
1

fmmm e +

Zero

Set

MACHINE

the

load address

load function inactive

EXECUTING NONFUNCTIONAL LOOP

from the
1load address
the
The decoder RAM address is the OR of
When one
decoder.
the
from
field
the op code address
console and
to
Prior
zero.
be
must
other
the
of these two inputs is used,
d
accomplishe
be
must
ion
initializat
the DRAMs, a hardware
loading
to force the op code address

field to zero.

the machine must bDe
zero,
Wwhen the address field is to remain
RAMs are being
decoder
the
in a nonfunctional loop while
operating
ction
microinstru
one
the
This creates the requirement that
loaded.
control
the
into
necessary to execute the loop be loaded previously
store.

PHYSICAL

SEGMENT

COUNT

Command Load Register = XXXX101l1
Data Load Register = DRAM PSEG Count

Mode = Write DRAM PSEG Count
Currently equal to 2

WRITE

DRAM

ADDRESS

(Figure

2-28)

WRITE DRAM ADDRESS

DECODER RAM ADDRESS <11:0>
07

SL ID

6 BITS OF ADDRESS
1

1 = DRAM ADDRESS <11:06>

0 = DRAM ADDRESS <05:00>
MKV86-1277

Figure

The

command

DRAM

load

ADDRESS

Command

Load

mode

and

the

2-28

DRAM Address

loaded

address

with

XXXX0010

loaded

Mode

two

Set

DRAM

enter

the

Address

Data

Load

01AAAAAA

AAAAAA

DRAM

Address

Data

<11:6>

Load

00AAAAAA

AAAAAA

DRAM

Address

<5:0>

WRITE

DRAM

DATA

The

command

DRAM

DATA

Command

SET

slices.

load

mode

Load

and

the

data

loaded
is

with

loaded

XXXX0110

three

Mode

Set

Data

Load

Data

for

DRAM

<16:12>

Data

Load

Data

for

DRAM

<11:06>

Data

Load

Data

for

DRAM

<05:00>

ITT

2-51

enter

consecutive

DRAM

Data

the

SET

slices.

CLEAR THE LOAD ADDRESS

Command Load Register = XXXxX0010

0000
Data Load Register == 0100
0000
0000
er
ist
Data Load Reg

Mode = Set DRAM Address

= 0
DRAM Address <11:06>
DRAM Address <05:00> = 0

LOAD FUNCTION INACTIVE

mechanism on the
been loaded, the loading
when the DRAM data has
state prior to starting
be left in the inactive
decoder module must proc
edure is performed by writing XXXX0000 to
the machine. This ster
.
the command load regi

111 2-52

the NMI

Control

Store

SEQUENCE

LOAD

Write NMI CS physical segment count
Point VBus to parity error bits
Reset byte counter
+-->

Write

NMI

address

Write

NMI

data

bytes)

Check parity using VBus

1
1

fmmm e +

Zero

the

Set

load

function

SEGMENT

COUNT

PHYSICAL

load

address

inactive

Command Load Register = XXXX1lll
Mode = Write NMI CS PSEG Count
Data Load Register = NMI CS PSEG Count Currently equal to 3

WRITE

NMI

CS ADDRESS

(Figure

2-29)

WRITE NMI CS ADDRESS
NMI CONTROL STORE ADDRESS <7:0>

02
|

'g"EULX

SLICE ID

01
)

00
I

4 BITS OF ADDRESS
]

| MUX SELECT SELECTS LOAD ADDRESS
01 = MUX SELECT AND NMI CS ADDRESS <07:04>
10 = NMI CS ADDRESS <03:00>
MKV86-1278

Figure

2-29

NMI

Control

I11 2-53

Store Address

The command load register is loaded with XXXX001ll to enter the
NMI CS ADDRESS mode and the address is loaded in two slices.
Command Load Register = XXXX001l

Mode = Set NMI CS Address

Data Load Register = 0101AAAA
Data Load Register = 0110AAAA

AAAA = NMI CS Address <7:4>
AAAA = DRAM Address <3:0>

WRITE

NMI

SET

DATA

The command load register is loaded with XXXX011l1l to enter the

NMI

GSET

WRITE DATA mode and the data is loaded in four consecutive

slices.

Command Load Register = XXXX011l1
Data Load Register
Data Load Register
Data Load Register
Data Load Register

CLEAR THE

LOAD ADDRESS

Data for NMI CS
Data for NMI CS
Data for NMI CS
Data for NMI CS

Mode = Write NMI CS Data
<27:24>
<23:16>
<15:08>
<07:00>

PATH

Command Load Register = XXXX001l1

Mode = Set NMI CS Address

Data Load Register = 0001XXXX

MUX SELECT = 0

LOAD

FUNCTION

INACTIVE

1loading
the
been 1loaded,
store data has
When the NMI control
state
inactive
mechanism on the decoder module must be left in the
by
performed
1is
This procedure
prior to starting the machine.
writing XXXX0000 to the command load register.

11T 2-54

RAM/DRAM

Load

Circuitry

Figure

2-30

transfer

the
module
to

proper

addresses
The

flag

generated

the

and
by

and

console

written

simplified

block diagram of the data path
used
The gateway control (GWYC) on the decode
r
distribution device, and routes the RAM
data

location.

commands

connecting
be

process.

functions

the

sending
must

shows

the

console

over

interface

communicates

the

with

8-bit

the

command

1load

data

load

for

the

GWYC

signals

CSEQ

MCA

used

the

11T

console

2-55

with the GWYC by
bidirectional
bus

decoder

strobe
the

The

data

module.

and

appropriate
to

load

interface.

the

Commands
data

and

CPU.
RAMs

are

BIDI

TRANSGVR

CONS DATA

DATA

XCVR

WRT

ADDR

CONS ADDRESS

LATCH

DECODE

CONS CONTROL

CSEQ

CMD FLAG
STROBE

—p

GWYC

[DEC]

CONSOLE INTERFACE

o arn

»| DATA
WRT

ADDR

CSo

DATA
WRT

r ADDR
»| LATCH

CSt

DATA
WRT

ADDR

CcS2

p| LATCH
[WCS]

[SEQ]

» DATA

WHT

p| LATCH

NMI

csS

» ADDR

[CCS]

SCLD-241

Figure 2-30

RAM Loading Simplified Block Diagram

Figure 2-31 identifies
process of loading the

the sequence of
RAMs and DRAMs.

events

that occur during

LOAD RAMS

AND DRAMS

!
DISABLE WRITES TO SLOW DATA FILE

'
SET CLOCKS OFF

Y
LOAD VBUS ADDRESS FOR RAM PE BIT

SET CLOCKS ON

LOAD CONTROL STORE RAMS-CS0/CS1/CS2

LOAD MICROPC WITH ADDRESS OF NOP

(TO SHEET 2)
SCLD-242

Figure 2-31

RAM/DRAM Loading Events

ITTI

2-57

(Sheet

1 of

the

(FROM SHEET 1)

ASSERT/DEASSERT CPU INIT
(INITIALIZE SEQ, DEC, CCS, AND ADP)

'
LOAD NMI CONTROL STORE

!
LOAD DRAM CONTROL STORE

'
SET CLOCKS OFF

!
LOAD CSM INIT

INTO MICROPC

v
SET CLOCKS ON

Y
MICROCODE HALTS VAX

'
MICROCODE ENTERS WAIT LOOP

!
SET CLOCKS OFF

(TO SHEET 3)
SCLD-243

Figure

2-31

RAM/DRAM

Events

(Sheet

(FROM SHEET 2)

DISABLE SDF WRITES

v
LOAD STARTING MICROP
C

Y
BURST CLOCKS

v
ENABLE SDF WRITES

y
START CLOCKS

MICROCODE HALTS VAX

DISABLE NMI,

v
STALLS,

TRAPS

v
ENABLE SDF WRITES

(TO SHEET 4)
SCLD-244

Figure

2-31

RAM/DRAM

IIT

2-59

Events

(Sheet

(FROM SHEET 3)

v
LOAD SDF DATA -

ADDRESS

A4
LOAD USER MICROCODE

SET CLOCKS OFF

LOAD CSM INIT INTO MICROPC

MICROCODE HALTS VAX

INITIALIZE COMMAND

INITIALIZE IPRS

(TO SHEET 5)

TM)

}_.l -

SCLD-245

Lnnfling

11T 2-6¢

Events

(Sheet

(FROM SHEET 4)

'
VERIFY

MIN

MEMORY AND |/O

REQUIREMENTS

ENABLE STALLS, TRAPS,
NM! MICROSEQUENCER

'
SET CPU NEXT PRIMARY

v
ASSERT UNJAM

[

v
VERIFY MCL AND NBI

REVISION

'
DETERMINE AVAILABLE

MEMORY

v
IF

COLD START,

INITIALIZE

MEMORY ARRAYS

v
CLEAR COLD BIT

v
CLEAR SYSTEM INIT

PROGRESS FLAG

y
END INITIALIZATION

PROCESS

SCLD-246

Figure

2-31

RAM/DRAM

IIT

2-61

Events

(Sheet

Table 2-9 lists some of the key hardware signals and functions used
during
the
initialization
process,
and
identifies
the console
interface logic that
performs
the
process.
These
signals
and
functions
are
described
in
more detail in the discussion of the
individual

logic

Table

areas

2-9

identified.

Key

Initialization

Signal/Function

Console

Logic

ACLO/DCLO

Synchronizer

Signal/Functions

Comments
Received
lated

from EMM

and

clock

-- Trans-

synced.

Initializes console interface
registers and sends power-fail
interrupt to VAX 8800 CPU.

CPU

INIT

Control

Reg

Created in control register 0
from console data (software
command) or forced by assertion
of

UNLOCK CSEQ

Console
Sequencer

DCLO.

Generated by serial data
sequence from port B bit
Enables

for

the

console

communication

sequencer

with

the

console.

DISABLE

SDF

RAM STROBE
COMMAND FLAG

Control

Reg

Console
Sequencer

Disables write to slow data
file in VAX 8800 CPU.

Strobe signal and command/data flag to the VAX 8800 CPU
decoders.

DISABLE STALLS,
TRAPS, NMI

Control

Reg

Disable signal to minimize
undesirable events (stalls,
traps, NMI traffic) during
TrmitialaeatriAan

11T 2-62

2.4.2

VAX

8800

Read/write
CPUs

Control
of

performed

registers
Console

CPU

control
in

the

data
by

conscle

sequencer

transfers,

the

setup

functions:

Console

read/write

Console

interrupt

RAM

strobe

and

Console/CPU

sequencing
generation

flag

generation

isolate

and

control

signals:

Control

CPU

Control

Disable

traps

Disable

stalls

Disable

NMI

CPU

disable

init

and

sequencer

interface.

Control

console

UNJAM

Enable

receive

Enable

slow

Enable

breakpoint

Set

CPU

mode
trap

halt

Control

Disable

slow

Set

timeout

CPU

interrupts

data

file

ITT

writes

2-63

console

and

of
the

the

VAX

three

8800

control

2.4.2.1 Console Sequencer -- Communications between the console and
and
signals
handshaking
requires
interface
console
the
Figure
synchronization of the data transfers to the VAX 8800 CPU.
2-32 shows a simplified drawing of the key signals used in the data
transfers.

PPI OUTPUT FULL —

MASK INTERRUPTS
———— P

> PPl ACKNOWLEDGE

» CONSOLE WRITE

SEQUENCER

READ ENABLE

—Pp

————p CONSOLE READ

PPl INPUT FULL

——P

————
PPI STROBE
SCLD-247

Figure 2-32

Console/Interface Timing Signals

ITTI

2-64

Read/Write
The

Sequencing

console

the

writes

interface

PPI.

The

PPI

OUTPUT

FULL

that

acknowledge
be

write
When

the

clock

handshaking

interface
can

data

signals

and

data

enables

transferred.

interface

1location

associated

PPI

ACKNOWLEDGE.

now

the

output

Figure

the

with
PPI

available

2-33

buffer
shows

writing

port

PPI

asserted

for

generates

one

the

process.

interrupt

from

simplified

two

PPI

microseconds.

WRITE

are

term

enabled,

the

completion

the

CONSOLE

PORT A <7:0>

CONSOLE DATA <7:0>

PORT B <3:0>

CONSOLE ADDRESS <3:0>

The

the

PPI

that

the

data

drawing

the

PPl

OUTPUT FULL

PPl

ACKNOWLEDGE

console

for
wuse in
the console

PORT

are

the PPI OUTPUT FULL signal, it responds
ACKNOWLEDGE.
The
ACKNOWLEDGE
signal is held

interrupts

PORT C <7>

the

receives

CONSOLE

the

informs

console.

sequence.

the interface
asserting
PPI

operation
full

the

address

this

output

from

the

"B"

sequencer

the data transfer
will
receive
an

data

transfer.

INTERFAGE

CSEQ

|———»CONS WRITE

SCLD-248

Figure

2-33

III

Write

2-65

Sequence

The

console

location

sets

the

read

read
to

sequence

the

asserting READ ENABLE (PPI port B
mux input to be placed on

the

read

initiates
signals

console

sequence

with

a
to

the

writing
by

means

the
of

address
PPI

<4>).
The
address
data bus to the

desired

Read enable
handshaking

interface
the

port

the

and

selects

the

console.

re ad
sequence
by
sending
the
expected
the PPI and enabling the bidirectional bus
appropriate

timing.

Figure

2-34

shows

the

setup.

PPI

CONSOLE INTERFACE

PORT A <7:0>

CONS DATA

¢ MUX DATA

PORT B <3:0>

CONS ADDR

PORT B <4>

READ ENABLE

CSEQ

CONS READ

SCLD-249

Figure

2-34

Read

Seguence

(Setup)

The

control

STROBE

PPI

that
used

used

PPI

INPUT

buffer,

and

the

buffer

1is

full

port

the

buffer

signals

and

the

FULL.

data
The

PPI

STROBE

INPUT

and

will

has

been

during

cleared.

Figure

the

transfer

process.

transfer

2-35

PPl

FULL

not

the

informs

shows

CONSOLE

PORT A <7:0>

process

latches

the

are

the

PPI

data

into

the

interface

data

until

control

the

signals

INTERFACE

SONS DATA

MUX DATA

PORT B <3:0>

CONS ADDR

PORT C <5»

PPI_INPUT

FULL

PORT C <4>

PPI_STROBE

csea

cons
CON

__]
SCLD-250

Figure

2-35

Read

IIT

Sequence

2-67

(Data

Out)

PORT “*A""’

TRNSVR

<7:0>

89-¢ III

«<7:0>

|<6>-DIS LFT CPU TRAP —®TO SEQ

DATA

REG

TO CCS
-—<§>-—DIS LFT CPU NMI—p

TO CCS
| 23> _DIS RHT CPU STALL—®
[__<2>_DIS
__<1>—DIS

LATCH

——» TO CPU

RHT CPU TRAP —p TO SEQ
TO CCS
RHT CPU NM!—p

L————3 TRIC

LATCH

L——3 TRIC

MCA INIT
RHT
L
» TO CPU

MCA INIT
SCLD-251

Figure

2-36

Simplified Diagram of Control Register O

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*suo0T3OoUN3 Ndd 9yl o[gesip 10 o[grUd
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oATo091 sxd3siboa Toa3UOD oyl -— sao3sibay TOAUOD Z°'Z°V°C
8TOSU0D

$ LFT CPU STALL—® TO CCS

CONS
PPt

PPl

PORT: A

TRNSVR

<7:0>

—<7>—NMI

CONS
DATA

REG

<7:0>

UNJAM

p TO MCL,

NBIA

—<6>— ENA LFT RCV INTRPT—» TO SEQ
—<5>—ENA NMI

SLOW——
> TO MCL,

NBIA

—<4>—ENA RHT RCV INTRPT—p TO SEQ

—<3>—ENA LFT BKPT TRAP—3p TO DEC
—<2>—SET LFT CPU HALT—

TO DEC

—~<1>—ENA RHT BKPT

TRAP —3p

TO DEC

HALT——»

TO DEC

—<0>—SET

RHT CPU

SCLD-252

Figure

2-37

Simplified

Diagram of

CONQ

—< 7>

» NOT USED

DATA

—<6 >

¥ NOT USED

——<5>

» NOT USED

—<4>

AL (o]

<7:0>

Control

REG

<3:0>

ENA IDP

LOOPBACK

—<3>— DIS LFT SDF WRITE—» TO WCS

—<2>— DIS RHT SDF WRITE—®» TO WCS
—<1>— CLEAR

RESET——p

—<0>— SET CPU TIMEOUT——»

TO CSEQ
MCA
SCLD-253

Figure

2-38

Simplified

Diagram

ITIT

2-69

Control

2.4.3

Data Transfers

are
The receive data buffer (RXDB) and transmit data buffer (TXDB)
8800
VAX
the
and
used in the transfer of data between the console
CPUs. The low byte of the registers contains the information being
transferred, and the high byte identifies the use of the data being
transferred.

interrupt
the
When the console has data to transfer to the CPU,
the last
that
verify
to
order
in
register must be examined
status
to
ready
and
empty
is
RXDB
the
data transfer has been completed and
console
the
empty,
is
If the RXDB
accept data to be transferred.
The hardware
writes two bytes to the RXDB by means of PPI port A.
are
interrupts
if
CPU
the
in the TRIC MCA generates an interrupt to
DONE
the
poll
can
CPU
If interrupts are not enabled, the
enabled.
bit

reading

the RXCS.

The console must wait for the deassertion of the DONE signal before
If RXDB interrupts to the console are
to the RXDB again.
writing
enabled, the deassertion of DONE will interrupt the console.
The VAX 8800 CPU responds to the interrupt, reads the data from the
Parity checks of
and hardware in the TRIC MCA clears DONE.,
RXDB,
data transfers between the interface and the CPU are performed and
Figure 2-39 shows a simplified drawing of
monitored by the CPU.
the

transfer

process.

CONSOLE INTERFACE

VAX 8800

CPU DECODER

CONS DATA

PARITY

GEN

PARITY

——»
10

RXDB

X
S
DBCS

»|
»

BUS
CNTR

—p TO IBOX

DATA BUS

|—»

INTRPT

» TO SEQ

DONE

» INTRPT STATUS TO MUX

L
» INTRPT

TO CSEQ

SCLD-254

Figure

2-39

Data

Transfer

Console

IIT

2-71

Interface-to-VAX

8800

CPU

le
Data transfers from the VAX 8800 CPU to the conso
code.

interface

are

The microcode
performed under the control of the if micro
data buffer
mit
trans
the
monitors the READY signal to determine
data word
last
the
ins
(TXDB) has been cleared or if it still conta rupt (deasserti
on of
inter
sent. When the console receives an data
le
conso
the
TXDB,
the
READY) informing it that there is sets inREADY
CPU
er
anoth
for
initiates a TXDB read and the TRIC MCA
a simplified drawing of the
shows
2-40
Figure
write.
CPU-to-interface data transfer.

VAX 8800 CPU

CONSOLE INTERFACE
PARITY
K
CHEC

DATA/INTRPT

TO DATA MUX
«—

<«

TXDB

TO|CSEQ
READY

DBCS |4—
pi INTRPT

3 TO

PARITY

SEQ

PARITY

GEN

BUS

CNTR

—( FROM CACHE DATA BUS
—p» TO SEQ
[DEC]

Figure 2-40

Data Transfer VAX 8800 CPU-to-Console Interface

2.5

CONSOLE/VAX

The

Console

and

1-MHz

8800

Interface

timeout
clock

also

The

during

VAX-1l

generate

interrupts.

2.5.1
The

One-MHz

description

The

clock,

source

for

data

and

the

basic

VAX

8800

ICLOCK

INC

asserted

signal

asserted

derived

from

the

terminal

The

the

MOD

MSB

one

7-bit

the

32-bit

monitor

the

The

timers,

timing

timer

software

clock

provided

VAX
MOD

8800

once

each

CPU

counter

the

crystal

oscillator

(interval

sync)

that

The

value

used

clock

(N)

equal

held

comparator

and

control

used

the

time

events

VAX

8800

and

CPUs

Section

the
clock

phase-locked

(N)

constant

reference

microsecond

cycle.

and

clock
on

with

TRIC
the

produces

times

the

250-kHz

the

clock

period

the

module

the

generation

comparator

reference

values

and

interval

zero

sync

logic

wvalues;

uses

3N/4,

are

used

value

and

will

the

2N/4,

latched

generation

1-MHz

PPI

the

ENABLE

value

signal

following

PPI

READ
WRITE
FLAG

I1T

output

oscillator.
register

the

three

and

1-MHz

produce
reference

against
the
changing
the EN ICLOCK INC whenever the
signal is generated at
a
rate

(250

kHz)

used

handshaking

STROBE

COMMAND

period
The

constant

produce

the

1-MHz

ACKNOWLEDGE

CONSOLE
RAM

the

STROBE

CONSOLE
PPI

clock

MCA.

N/4.

INC
and

comparison

create

comparison is found.
The resultant
four
times the oscillator frequency
regardless

and

ICLOCK

signal.

three

clock

interval

frequency

The

interval

PPI

timer,

system.

Clock

The

8800

applied

interval

VAX

the

diagnostic

circuits

the

manual.

remains
is

MHz

used

the 1-MHz clock logic shown in Figure
2-41
is
to
a constant clock frequency to the TRIC MCA interval clocks
timing
source
for
PPI
data
transfers.
A
functional

provide
and
a

this

timing

Timeout
program mode.

function

transfers to
interval clock is a

system

the

that

basic

operating

during

contains

circuit
the

wused

signal.

CLOCKS AND TIMING

2-73

the

CSEQ

signals:

MCA

the

N)—

REF
XTAL

PHA
DE-H-SE

FILTER

VCO

- A CLK

EEGSE

L
» B CLK
F(OUT)

onr.

[

F(IN)

INTERVAL

F(OUT)

= 250 KHZ

= N X F(IN)

SYNC

CLOCK
PERIOD

CLOCK

PERIOD

(=N)
CLOCK LOGIC

FL-C 111

-J— ——

COMPARE

—|

COMPARE

<
R

€

ADD

«—

(CSEQ MCA)

RIGHT

SHIFT

N/2
]

L
COMPARE

CONSOLE INTERFACE

RIGHT

SHIFT

N/4

<___.

ZERO

COMPARE

» EN ICLK

———»|

LATCH

INC

(TO TRIC

MCA)

|—»1 MHZ ENABLE

SCLD-256

Figure

2-41

MHz

Clock

Generation

2.5.2

Interval

Each

VAX

8800

interface.
control

and

identical

Clock
CPU

has

The

three

interval

clock

1logic

and

data

transfer

MCAs.

are

Figure

evenly

registers,

interval

The

and Figure
clock.
registers

Interval

2-43

that

Count

Interval

Count

2-42
is

are

residing

three
the

used

for

Control/Status

ICCS

LOW TRIC

28
D<31:28>

rL\]?(I;VR

interval

clocks

are:

(ICCS)

| SGL|

ERR | RUN | XFR

D<23:20>

D<19:16>

HIGH TRIC

LOW TRIC

D<7:4>

D<3:0>

HIGH TRIC

LOW TRIC

HIGH TRIC

LOW TRIC

D<31:28>

D<27:24>

D<23:20>

D<19:16>

HIGH TRIC

LOW TRIC

HIGH TRIC

LOW TRIC

D<15:12>
HIGH TRIC

)

D<11:8>

D<7:4>

LOW TRIC

HIGH TRIC

LOW TRIC

D<11:8>

IL(%V

D<15:12>

HICH

LOW TRIC

diagram

D<27:24>

HIGH TRIC

block

HIGH

NICR

1located

configuration

HIGH TRIC

console

provide

(NICR)

INT [ IE

HIGH TRIC

the

that

{ICR)

the

and

bit

simplified

registers

sliced,

shows

the

D<3:0>
LOW TRIC
SCLD-257

Figure

2-42

1Interval

Clock

Registers

111 2-75

Bit

Configuration

two

the
the

The interval timer provides a method for accurately measuring
variable time intervals and enables the software to perform
time-dependent events. The timer informs the CPU of a completed
interval by means of an interrupt generated by the overflow of the
interval count register being incremented to a full count.

The interval count register (ICR) 1is a 32-bit counter that
The
at the rate of one microsecond per count.
increments
clock
1-MHz
incrementing pulse (EN ICLOCK INC) is supplied by the
on the CSEO. The next interval count register (NICR) is a 32-bit
register containing the value to be loaded into the ICR each time
the ICR overflows. Control and status is provided by the interval

clock control and status register (ICCS).
configuration of

the ICCS.

Table 2-10

Table 2-10 shows the bit

1ICCS Bit Configuration

Bit

Name

Function

<07>

INT (Interrupt
Request)

Set when the ICR overflows. Interrupts
the CPU if interrupts are enabled.

IE (Interrupt

Allows interrupt to occur at ICR

Enable)

overflow.

<05>

SGL (Single)

Used for maintenance functions.

<03>

ERR (Error)

Indicates that a second overflow

<06>

Cleared by writing 1 to this bit.

set, the count register will increment
Set for one cycle only.
by one.
interrupt has been requested before
Cleared by
the first is serviced.

writing

<02>

RUN

When

to this Dbit.

Provides the function of counter

enable.

Cleared on powerup and

initialize.

<01>

XFR (Transfer)

Transfers the contents of the NICR
to the ICR.

111 2-76

Set for one cycle only.

The

procedure

value

microseconds
enable,

into
the

the

and

using

between

the

timer

the

interrupts

transfer

bits

requires

two's

and

1in

the

complement

setting
ICCS.

the
of

the

The

NICR with
the

run,

NICR

number

interrupt

will

loaded

ICR and the ICR will begin counting.
When the
ICR
makes
transition from all ones to zero, an interrupt is
generated and
next value is loaded from the NICR.
If a transition
is
again

reached
set

for

corresponding

and

before

the

counting

1last

interrupt

NICR

ICR

WR NICR <3:0>——
ICCS

RUN

—

serviced,

CPU DATA <7:0>—p

IcCS STEP

the

continues.

error

flag

<31:0
CR ICR <31:0>

[——» OVERFLOW NEXT

____y| INTERVAL

CLOCK

» ENABLE ICR

ICCS TRANSFER —p»
REFRESH ICR
)|

» LOAD ICR

.
S:
| INTERRUPT = HI TRIC |
| ERROR =

LOW TRIC

INTR

OR ERR

ERR

ACLOCK —
p1

INT

B CLOCK ——p

—
9 HOLD INTRPT/ERR
———» 1cCS <3>

CPU DATA <2>——p

WR ICCS

— 3

CPU DATA <1> ——3pt

WR ICCS

oTEp

|—IcCS

INT

i INTRPT ENBL = HI TRIC

| RUN = LOW TRIC

5 ices RN

|——p STEP ICR

| TRANSFER

ICR

TRIC
=

LO TRIC

b e el

— XFR

{STEP ICR

| TRANSFER NICR
SCLD-258

Figure

2-43

1Interval

Clock

Simplified

111 2-77

Block

Diagram

2.5.3

CPU Timeouts

The console interface monitors the VAX 8800 system for
a
possible
CPU hang.
A timeout flag is maintained for each CPU and is checked
periodically
by
the
console
software.
Figure
2-44
shows
a
simplified
block
diagram
of
the
timeout
1logic
on the console
interface.
Figure
2-45
shows
the
bit
configuration
of
the
read-only clock status/timeout register (CST).
The timeout flag is set by a signal from control register 2,
which
is
set
by
console
software.
The
flag is cleared when the CPU
hardware releases a stall.
Time detects a CPU infinite stall.

CONS ADDR —j

—

SET CPU TIMEOUT

FROM CONSOLE

TIMEQUT
LOGIC

|——»CPU TIMEOUT —pf =

MUX DATA OUT

TO PPl

PORT A

CLEAR CPU TIMEOUT ——
FROM CLOCK DISTR
(CPU STALL DEASSERTION)

SCLD-259

Figure

2-44

GATED
]

CLOCKS

STOPPED

Simplified

]

R CPU
|

MICRO

L CPU

MATCH

L CPU

TIMEOUT

MATCH

MICRO

CPU Timeout

R CPU

BURST

DONE

TIMEOUT
SCLD-260

Figure

2-45

Clock

Status

and Timeout

11T 2-78

(CST)

2.5.4
The

Visibility

console

interface
shows

the

Figure

Bus

uses

the

signals

2-47

VBus

shows

control/access

logic

on
CPU.

the

console
Figure 2-46
involved in the reading of the VBus
information.
a simplified block diagram of the VBus logic.

address

and

read

VBus

data

the

4# RIGHT CPU VBUS

MUX

<4—~— LEFT CPU VBUS

VBUS ACCESS <7:00> ¢—

SEL

VBUS

CONS DATA <3:0> —p

————p STOP SHIFT

CONTROL |o sTEP B CLK

WR VBUS CONTROL

|
» VBUS ADDRESS

SCLD-261

Figure

Bit

selects
stop

which

shift

VBus

and

data

supplies
the

the

either

the

STEP

subsequent

B
B

VBus

control
the

VBus

1is

2-46

input

address

from

right

1is

the

mux

inputs

used

the

console

serial

shift

Stop

shift

shifting

ITT

the

2-79

Signals

CPU

are

the

signal.
clocks

1left

applied

Control/Data

the

select
the

process

interface.
register

freezes

the

address.

and

bit

and

console.

The

selecting

The

address

bit

clocked

address

prevent

—
—P

—» LATCH

—P
—P

—p!

LATCH

MUX SELECT

[MCA]
e

s i

s v

STOP SHIFT

ADDRS OUT
STEP B CLK

JISZIS1|SOl82’S1 so|®
CPU

CONSOLE INTERFACE

MODULE

Figure

2-47

VBus Logic Simplified Block Diagram

CHAPTER
DETAILED

3.1

DESCRIPTION

GENERAL

This

chapter

specific

contains

areas

additional

the

console

and

descriptions

detailed

subsystem.

information

1Included

CSEQ

TRIC

concerning

this

chapter

are:

[

Diagrams

Console

)

Console

subsystem

cabling

TERMINAL

INTERVAL

3.2
The

console

implement
the

VAX

minor

the
8800

system.

3-2

MCA.

signal
MCA

and

Data

received

data

Despite

and

3-3

Table

3-1

1is

applied

and

3-2

status

block
pin

each

from

diagram
layout

the

both

the

normal

path

buffer.

The

(RXDB

for

data

SELECT
the

DATA)

RXDB.
is

transfers

the

key

signals

the

CPU

applied

the

for

the

means

2-byte

output

the

data

DATA)

Data

transfers

unbuffered

1incoming

transmit
blocks

from

data

data
the

(CONS

VAX

the

8800

microcode

enable
data

along

data

the

buffer

with

the

and
the interval clock
byte of ICCS DATA).
The
eight mux inputs will be
CPU

mux.

will

the

console

bus

and

CPU

(TXDB)

buffered

and

unbuffered

CPU-to-console

during

triggered

the

deassertion

console

received

transfer

mux

and
path

receive

bus

cannot

(RXDB)

the

DATA.

data

signals

the

buffer

data

output

8800

buffer

bidirectional

bidirectional
of

bus

VAX

CONS

LOAD

REG

buffered

(IPR

DATA).

the

8800

transfer

The

VAX

unbuffered

ENABLE

output

the

data

The

WRITE

bidirectional

the

functions.

translators

control/status
(DBCS
DATA)
information
outputs
(Four
bytes of ICR data and one
3-bit
RCV
ADRS
determines which of the
determines

signal

drawing

low

MCA.

and
to

body

TRIC

the

RXDB
applied

single

receive

have

and

identifies

the

mux.

TRICs

high

and

console

directly
to
the output mux is used
during the initialization process.
The

and

to
and

the

MCAs

console

TTL-to-ECL

output

MCAs,
of

TRIC

the

MCA

some

description

bus

between

facilitate

TRIC

lists

interface

bidirectional

MCAs

(TRIC)

identical

the

transferred

the

and

19-0TRIC-00

show

1lists

CLOCK
four

being
a

the

order

shows

Table

provides

from

DATA

wiring

3-1

assigned.

TRIC

CONS

Figure

Figures
TRIC

contains

transfer

variations

slicing.

the

interface

summary

waiting

additional

data

TXDB.

the

until

IIT

3-1

The

XMIT

data

READY

output

The

been

into

the

interrupt

informs
VAX

the

signal

from

condition
has

received

DISABLE

transfer.

processed.
READY

are

latched

8800

the
CPU

reasserted.

PARITY
GEN

DEC TO CONS PARITY €—

BID!

DATA <3:0>
PARITY

BCY ADDR . N

—A

LSS

(TO/FROM CPU DEC) «

OUT

> Do—

|—

EN LOAD REG

B|Dl

XMIT DISABLE

CNTRL

CONS DATA <3:0>

BUS

RXDBO SELECT

EN LOOPBCK B

ICCS INTRPT SET—

-3

REFRESH ICR ————p

EN ICLK INC>

CARRY IN

ICCS STEP———P
ICCS

<3:0>

|\NTERVAL

[

CLOCK

—— CARRY OUT <3:0>

RUN _—»

!CLK INTRPT

LSTEP OR XFER

[INTRPT OR AN

ICCS

ICCS TRANSFER

ICR
ICCS

DATA
DATA——

DBCS DATA———

RXDB DATA

ADRS

<2:0%

ADDRs
DECODE

———PID

[
WR NICR
—— WR ICCS
LOW SLICE

—» TERMINAL
CONSOLE
ID

SET DONE OR READY——P
WRiTE gip

IPR

—— WRITE TXDB

—~

WRITE DBCS

RXDB

CONS DATA

Figure

3-1

TRIC

MCA

Block

Diagram

()

(7)( 6)( 3)[

(69)

(0]

——r

(16)

(14)

(12)

(10)

8)( 6)( 4)( 2)

(68)

(67)

(66)

(65)

(64)

(63)

(62)

(61)

(60)

(59)

(58)

(57)

(56)

(55)

(54)

(

MCA PINNING

e
e
e
et
——

N
w

(1 9)

-_—

(11)

—

(13)

(15)

DEVICE TYPE =

DC957

38)

(40)

(42)

(46)

(48)

(50)

(53)

(52)

(37)

(39)

(41) (43) (45)

(47)

(49) (51)

(72)

(44)

SCLD-264

Figure

3-2

TRIC

ITT

MCA

3-3

Layout

TERMINAL REGISTER/
INTERVAL CLOCK

SET DONE/READY—O

O BID! CPU DATA <3:0>
— TXDB DATA <3:0>

SELECT RXDB—Q
SELECT HI BYTE —
—O
WRITE ENABLE

— CONS TO DEC PAR

CONS DATA <3:0> —

EN LOOPBACK B —
EN LOAD REG—O

— DEC TO CONS PAR
O

DONE OR READY

XMIT ADRS <2:0>—0
RCV ADRS <2:0>—0
XMIT DISABLE —
—
READ IPR—O
EN ICLK INC —
REFRESH ICR —O
WRITE IPR

— DBCS INTRPT

— ICLOCK INTRPT

LOW SLICE ID —

O CARRY OUT

CARRY IN<3:0>—0O

O INTRPT OR RUN

ICCS INTRPT SET-O

O STEP OR TRANSFER

ICCS RUN—O

ICCS STEP—O
R
—O
ICCS TRANSFE
INIT

—
TRIC

STALL ACLK1 IN—Q
A CLK IN
B CLK IN

—C
—O
SCLD-265

Figure

3-3

TRIC MCA Body Drawing

Table

Signal

3-1

ICLK

INTRPT

-BIDI

CPU

DATA

GROUND

—CARRY

<3>

DATA

-CARRY

OUT

CONS

NEG

52V

BUFF

INTRPT

<2>

DEC

-CARRY

OUT

DEC

CONS

<1>

<2>

PARITY
<1>

PARITY

~CARRY

TRANSMIT

DATA

-DONE

READY

CPU

DATA

<1>
BUFFER

GROUND

-BIDI

TRANSMIT

DATA

BUFFER

TRANSMIT

DATA

BUFFER

-BIDI

GROUND

TRANSMIT

CPU

DATA

—CARRY

-CARRY

OUT

NOT

-STALLED

GROUND

<3>

SELECT

HIGH

-WRITE

ENABLE

NOT

—-READ

NOT ASSIGNED
—-SET DONE OR READY
NOT ASSIGNED
NOT ASSIGNED
NOT ASSIGNED

-SELECT

ADRS

<0>

-XMIT

ADRS

<K1>

WRITE

IPR

40
41

-XMIT ADRS <2>
-A CLCKi 1IN

CONS

NEG

CONS

DATA

<3>

CONS

DATA

<0>

CONS

DATA

<1>

-ICCS

<2>

TRANSFER

INIT

—-ICCS

INTERRUPT

ENABLE

LOOPBACK

TRIC
SET

<2>

XMIT

<1>

LOW SLICE 1ID
—RECV ADDRESS
-RECV ADDRESS

-RECV ADDRESS

<0>

55
<0>

ASSIGNED

IPR

DATA

DATA
52V

ICR

BYTE

RECEIVE

-XMIT

LOAD

ASSIGNED

-ENABLE

<0>
CLOCK1l

Assignment

-REFRESH

<0>

Signal

<0>
BUFFER

Assignments

<3>

DATA

CNTRL/STATUS

MCA

Assignment

TRIC

BUFFER

IIT

-ICCS

RUN

-ICCS

STEP

GROUND

ENABLE

NOT ASSIGNED

ICLK

-B

-CARRY

—INTERRUPT

GROUND

-BIDI

CLCK1l

<2>

INC

OUT

<3>
OR

RUN

DATA <2>
STEP OR TRANSFER

GROUND

3-5

DISABLE

Table 3-2

Comments

Signal

BIDI

TRIC MCA Signal Descriptions

DATA <3:0>

CPU

bus between the VAX 8800
data
Bidirectional
CPU
and the TRIC MCAs. Consists of four bits
of

RECV ADRS

<2:0>

data

LOAD

the
DISABLE

CONS

DATA

ADRS

the VAX

8800

CPU.

bus.

Control
signal
from
the
DEC
module
that
disables bidirectional bus data output to the
VvAX 8800 CPU when input data is being sent by
console interface. (The default state of
the
this
signal
1is asserted.) The bidirectional
between the clock and decoder modules is
bus
disabled at both ends when not used.

<3:0>

Eight

bits

console

data

from the

PPI

port

A. Sliced into four bits each on the high and
low
TRICs;
this data is applied to the data
buffer for output to the VAX 8800 CPU.

LOOPBACK

XMIT

A
control
signal
from
the console address
Used to create the SELECT
circuitry.
decode
SELECT LOAD PATH selects
signal.
PATH
LOAD
either the buffered (RXDB) or unbuffered (RAM
load) data to be applied to the bidirectional
forces the deassertion of INT
and
bus
data
XMIT
DISABLE
that
allows the TRIC to drive

REG

XMIT

the MCA slices.

bits of address data from the VAX 8800
Three
Selects the mux input that
module.
DEC
CPU
will
be applied to the bidirectional bus for
output

from each of

<2:0>

Console
control
Enables
testing
data buffers, and
VAX

8800

CPU

signal from the PPI port C.
of the receive and transmit
the load path to the CPU.

control

signal

from the

DEC

module.
The
3-bit
signal is used to if the
incoming
data
word
from the CPU is console
data
or interval timer control.
The decoded
address
generates
the
write enable signals
for the interval timer and TXDB.
WRITE

TIPR

A
latched
enable
signal
derived
from the
XMIT-to-CONS
signal
from the CPU DEC. WRITE
IPR
enables
the
decoders
that
select the
write
signals
for
the
interval
<clock and
transmit

data

ITT

buffers.

3-6

Table

Signal
RXDBO

3-2

TRIC

MCA

<3:0>

DATA

<3:2>

Output

of
buffers.

Two

<3:2>

the

VAX

high

the

VAX

8800

status

CPU

and

status
the

interrupts

and

receive

data

Two

bits

status

state

CPU
CPU

<3:0>

Four
the

bytes
VAX

each

TRIC

applied
to

the

NICR,

NICR

ICCS

write-enable

ICCS,

the

XMIT

ADRS

8800

CPU.

ICLOCK

Latched

signal
CARRY

CARRY

OUT

ICCS

<3:0>
<3:0>

INTRPT

SET

CARRY

ICR

ICLOCK

for
IN

and

CARRY

signals

process

TRIC

MCA

the

Internally

the

count

data.

create

the

and

transmit

the

VAX

clock

data

informs

interval

error

count

clock.

and

that

WRITE

are

run

data

supplied

timer

mux

and

are

IPR

the

1-MHz

INC

1is

OUT

for

data

transfer

are

bit

This

signal
and

the

interval
four

for

the

count

CSEQ

enable

timer.

bits

count

counting

setting

the

ICCS.
signal

of
1is

the

primary

control

1loading

interrupt

clock

used

and

are

from

used

TXDB

input

timer

signal

derived

the

are

error

3-7

interval

ICCS.

IIT

CPU

the

output

generated

transfer

8800
bits,

interval

DBCS,

that

control

timer

for

nibbles

incrementing

control

interval
REFRESH

and

output

VAX

done

controil

bus.

signals

VAX

MCA.

Two
The

DBCS

ICCS

interval

TRIC

TXDB

output

suppliied.

the

for

and

MCA.

for

the

bidirectional

INC

data

state

CPU.

the

buffer

enabled

8800

data

ready

status

information

data

from

buffers.

the

Interrupt

receive

data

CPU.

Informs

from

slice

output

the

are

control/status

ICR

(Cont)

information

from

the

low

8800

and

RXDB

Dbits

the

ICCS

Descriptions

Comments

console
DBCS

Signal

NICR
also

error

bits

used

and

ICR

used

the

Table

3-2

Signal

TRIC

MCA Signal

Descriptions

(Cont)

and

are

Comments

ICCS

STEP

ICCS

RUN

ICCS

TRANSFER

generated signals derived from the CPU data
input,
and
are enabled by the WR ICCS term.
They
are
used internally to enable the step
and
run
of
the counter and to transfer the
NICR count to the ICR.

LOW

SLICE

STEP,

RUN,

Differentiates

1ID

TRANSFER

high

and

1low

internally

slices

the

TRIC.
SET

DONE

SELECT

READY

RXDB

The

SET DONE or READY, and SELECT RXDB are
generated
by
the
console
address
decoder
logic.
The
DONE and READY signals are used
in the interrupt logic to the VAX 8800 CPU to

show
data

the
state
of the receive and transmit
buffers. SELECT RXDB selects the RXDB to
receive data from the console.

READ

Derived

IPR

from

the

RECV

FR CONS

signal

from

the

DEC
module.
Asserted for one cycle when the
CPU
1is
reading
a TRIC IPR.
This signal is
also
one of the control signals used for the
RXDB
data
overrun
error
bit and DBCS done
bit.
WRITE

ENAB

SELECT

HIGH

BYTE

Control
latching

signal
of data

Control

signal

from
the
CSEQ that enables
received from the console.
from

the

console

decoder.
Determines selection of
high slice of data for the TXDB.
DEC

ICLOCK

CONS

PAR

INTRPT

Parity bit calculated from
from the DEC module to the
clock

Interval

interrupt

address

the

low

and

eight bits of data
console interface.
from

console

CPU

SEQ.
STEP

INTRPT

TXDB

XFER
OR

DATA

RUN

Internally generated interval clock signals.
Created
by
CPU data and enabled by WR ICCS.
Latched
to
create the ICCS STEP, ICCS XFER,
ICCS
INTRPT,
and
ICCS
RUN
depending
on
whether the signal is coming from high or low
TRIC

MCA.

Mux

selected

CPU

selects
applied

the

output

data

console.

The

either
high or
to the interface
ITT

3-8

from
TRIC

the

VAX

8800

output

mux

low slice data to
data output mux.

Table

3-2

TRIC

Signal
DBCS

Signal

Descriptions

(Cont)

Comments

INTRPT

DONE

MCA

Internally

READY

CPU

SEQ

and

READY

data

and

DONE

generated

<created
(Low

and

source

Slice)

the

bits

interrupt

DONE
and

(High

enabled

3.3

CONSOLE
console

are

wused

interrupts

sequencer

MCA

between

the

provides

write

clock
the

for

CPU

(DONE

identify

the

RXDB

of
identifies

the

CSEQ

the

signals

on
functions.

CSEQ

Console

The

console

transfers

and

the

interface

with

controls

latch

signal

the

(PPI

Table

and

3-4

shows

the

3-3

lists

each

read

from

the

data

from

also

block

diagram

layout

CSEQ

and

body

MCA

pin and
of the key
the signal

lists some
description of

Sequencer
controls

bidirectional

the

data

the

PPI

the

data

assertion

transfer

STROBE)

acknowledge

VAX

8800

the

logic

CPU

transmit

3.3.3

Console

Control

sequencing

console

interface

logic.

also

Write

the

port

direction

bus

between

CONS

READ

console

the

data

console

signal.

1It

providing

buffer.

controls

the

timing

informing

the

CPU

data

buffer

has

1is

data

generates

console

clock,

and

the

interface

control

Control
enable

initialization

Store

store

the

been

received

the

from

the

console

the

signals

registers,

that

VBus

write

sequencer

enable

control

writing

registers.

Load
of

control

1load

transfers

accomplished

the

control

of data transfers
(DATA ACCEPTED) when

Sequencer

that

CSEQ

synchronized

3-4

console.

3.3.4

console

Read Acknowledge

The

transfers

The

1-MHz

show

Table
provides a

sequencer
PPI

also

3.3.2

MCA

the

3-6

read/write

system.

IPRs

Figure
and

19-0CSEQ-00

8800

the

assigned.

Strobe

strobe

MCA.

signal

the

3-5

single

VAX

timer.

Figures

sequencing

the

timing

interval

MCA.

the

and

address

READY

(CSEOQ)

contains

implement

console

drawing

3.3.1

the

CSEQ

SEQUENCER MCA

interface

the

TXDB)
.

The

Slice)

DBCS.
READY

console

from

Sequencer
sequencer
the

process.
ITI

generates

«control

3-9

store

the

control

RAMs

signals

during

the

RESET INTRPT—

SYNC NM!
RESET

CONSOLE

OMUX
D y|MASK INTRPT

KEY DATA

ACKNOW-

pd ENA

—
READ IN PROG

I; consoe | PP ACK

KEYCLK

—»DAT
ACCEPTED

N
E LEDGE

DMUX
—]

READ OR

|—

—pd ENA

__J

INTRPT REQ ———

MASK OR

PPl STROBE

“———D—_ EESESCER [ » CONS READ

CLR RESET

SELECT
PEv-C ! —L—pds ¥

WRITE

EN ICLK

»q

INC

PPl INPUT FULL
PPI OUTPUT FULL

Lz 1 Mz

CLOCK PERIOD <6:1>

INTERVAL SYNC <6:0>

—P

SEQUENCER

|——pCONS WR

CNTRL __ |—CS LOAD STP
STORE

'égéo

|—CMD FLAG

L RAM STRB
L R RAM STRB

LOAD CMD
L/R

EN LOAD REG

DISABLE CSEQ

L/R CONS

IPR ADRS <2:0>—

EEéFT

4
>
~

NLK

CSEQ

INIT

DATA

KEY

CLK

cPU
SPRs

DELAY

L L/R xmiT
ADRS <2:0>

SCLD-266

Figure

3-4

CSEQ MCA Blecck

ITT

3-10

Diagram

(17)

(15)

(13)

(11)

(. 9)( 7)( 5)( 3)[

(19)

(16)

(14)

(12)

(10)

(

(69

8)( 6)( 4)( 2)

(68

(67)

(66

(21)

(23)

MCA PINNING

(65) (64

(25)

(63)

(27)

(61) (60

(29)

DEVICE TYPE = DC956

(62)

(59) (58)

(31)

(57)

(56)

(33)

(55)

(54

(36)

(38)

(40)

(42)

(44)

(46)

(48)

(50)

(53)

(52

(35)

(37)

(39)

(41)

(43)

(45)

(47) (49) (51)

(72

3CLD-267

Figure

3-5

CSEQ

ITIT

MCA

3-11

Layout

CONTROL

SEQUENCER

— PPI ACKNOWLEDGE
— PPI STROBE

PPl OUTPUT FULL —Q

PPl INPUT FULL —
MASK OR KEY DATA —]
READ OR KEYCLK —j
INTRPT REQ

— CONS READ

O— CONS WRITE

~— DATA ACCEPTED

—

| RESET INTRPT
| CS LOAD STEP

SYNC NMI RESET
CLEAR RESET —

h— L RAM STROBE
b— R RAM STROBE
O— CMD FLAG

L EN LOAD REQ —C
R EN LOAD REG —Q
LOAD CMD —C

O— L XMIT ADRS <2:0>

>
LCONS IPR ADRS<2:0—(Q
>
—Q
<2:0
ADRS
IPR
RCONS
—
UT
L CLR CPU TIMEO
R CLR CPU TIMEOUT —-Q
SET CPU TIMEOUT —
INTERVAL SYNC <6:0> __
CLOCK PERIOD <6:0> —

O— R XMIT ADRS <2:0>
L L CPU TIMEOUT
— R CPU TIMEOUT
— EN ICLOCK INC

SELECT KEY —
DISABLE CSEQ —

L STALLED A CLK1 IN —Q
R STALLED A CLKi iN —C
F A CLK1

—C

IN —C
F B CLK1

SCLD-268

Figure

3-6

CSEQ MCA Body Drawing

ITT

3-12

Table

Signal

CSEQ MCA

Assignment

-DATA ACCEPTED

CPU

3-3

TIMEOUT

GROUND

INTERVAL

-R

XMIT

-R

CLR

SYNC
ADRS

CPU

<1>

Assignments

Signal

-R

-LOAD

Assignment
LOAD

REG

CMD

INTERVAL

CLOCK

SYNC

PERIOD

<1>

CLOCK

PERIOD

TIMEOUT

<2>

CLOCK

PERIOD

<K1>

-CONS

READ

NEG

TIMEOUT

NEG

-L

STALLED A

-CMD

FLAG

-R

CONS

-PPI

-R

ACKNOWLEDGE

INTERVAL

-L

-R

RAM

-L

STROBE

-L

XMIT

ADRS

GROUND

MASK

-PPI

—-R

-L

READ

RAM

STROBE

XMIT

ADRS

ICLOCK

CPU

52V

SYNC

<2>
<K1>

STROBE

GROUND

INTERVAL

-CONS

NOT

INTERVAL

26
27

LOAD

<6>
<4>

<2>

INC
SYNC

<5>

STEP

WRITE

ASSIGNED
SYNC

<4>

52V

<K0>

CONS

IPR

ADRS

<2>

CONS

IPR

ADRS

CONS

IPR

ADRS

<K2>

CONS

IPR

ADRS

<K1>

KEY

DATA

CONS

IPR

ADRS

SELECT

KEY

CLEAR

RESET

SET

-R

SYNC

CPU
NMI

CLOCK
-F

GROUND
-L

-L

NOT

TIMEOUT

STALLED A

CLK1

RESET

PERIOD
CLK1

CLR

CPU

<6>

1IN
TIMEOUT

ASSIGNED

EN LOAD REG
INTERVAL SYNC <3>

-L

XMIT

ADRS

<0>

-F

-R XMIT

ADRS

<0>

PPI

CLOCK

CLK1

INPUT

PERIOD

<3>

GROUND

<5>

PERIOD
DISABLE CSEQ

RESET

33
34

NOT ASSIGNED
INTERVAL SYNC

-L

GROUND

INTRPT

GROUND

-PPI

<0>

REQ

OUTPUT

FULL

ITT

GROUND

3-13

FULL

INTRPT

XMIT

<K1>

KEYCLK

GROUND

ADRS

CLK1

IPR

ADRS

<2>

CSEQ MCA Signal Descriptions

Table 3-4
Signal

Comments

SYNC NMI RESET

Generated

the

NMI

reset from the NBIA.

and

sets

LATCHED RESET, which

the synchronizer logic to become
1in
Latched
MCA detects the
CSEQ
The
RESET.
NMI
SYNC

edge

rising

generates an interrupt to the console.

for

The OR

LATCHED RESET and SYNC NMI RESET are used
interrupt status

the console

bit

CLEAR RESET
TERM REG INTRPT

Generated

control register 2 as a result

a console command.

LATCHED RESET.

Clears

Internally generated interrupt enable signal.

One of the signals used to create PPI STROBE.
Derived from RXDB DONE and TXDB READY of both
CPUs.

MASK OR KEYDATA

Control

signal received from PPI port B, bit

5. Performs one of two functions depending on
If the
the SELECT KEY input.
of
state
the
KEY bit is set, it provides the input
SELECT
generating the
for
register
shift
the
to
If the SELECT KEY is not
term.
CSEQ
UNLOCK
the function of interrupt
performs
it
set,
mask.

READ OR KEYCLK

Control
Dual

signal received from PPI port B, bit

function determined

SELECT KEY

the

KEY bit is not set,
SELECT
the
If
signal.
strobe
the
to
passed
is
enable
read
demux
the
set,
is
KEY
SELECT
If
sequencer.
unlock
CSEQ
the
to
pulse
clocking
a
output is
shift

= 4

that

ates

buffer

contains

data

the

for the

PPI

console.

input

PPI

internally on the CSEQ to
sequence. PPI OUTPUT FULL

FULL is used
INPUT
tread
a
terminate

buffer has data
output
the
that
indicates
transferred to
be
to
is
that
from the console
signal is
FULL
OUTPUT
The
CPU.
VAX 8800
the
and the
ENABLE
LOAD
CS
the
generate
to
used
PPI
T O
CLCCK

DERDTAN

PERIOD

ACKNOWLEDGE.
.

Control signals fro m the clock m odu
create INTERVAL SYNC the 1-MHz cloc
'y

IIT

3-14

Table

3-4

CSEC

MCA

Signal

Comments

LOAD

Console

CMD

LOAD REG

control
address

command

flag

8800

decoder

the

gateway

control

address

signals

and

the

CSEQ

console

L/R

IPR ADRS
XMIT ADRS

Internally
DEC.

STROBE

VAX

used

the

RAMs

load

derived

logic.

signal

the

signals

decoder

used

for

that

RAM

used

(L/R

create

the

write

enable

MCA.

The

CSEQ

only

mechanism.
generated

console

disable

signal

interface

that

data

from

XMIT

generated

the

Internally
READY

the

TXDB

has

bit.

used

for

the

PPI

signal

ITIT

been

3-15

signal

Informs

read

another

VAX

used
8800

the

data

the

into

bidirectional

generated

ADRS)

buffer.

Internally

ready

The

signals for
provides
a

transceiver.
ACCEPTED

the

failure

signals

enable/disable

DATA

the

disconnect.

address

the

module.

power

TRIC

the

are

generation

strobe

PRO-38N

delayed

Internally

during

from

These

the

port

READ

the

used

latching

CONS

FLAG

are

generated

Clock

delaying
PPI

sent

RAM

during

cable

the
the

initialization.

ENABLE/DISABLE

from

Generates

process.

used

signals

during

that

signals

control

strobe

derived
logic.

decoder

right

(Cont)

COMMMAND

control

console

gateway

L/R CONS

signal

module.

Console

left

CSEQ

signal
decoder

initialization

primary

DISABLE

Descriptions

console

the

L/R EN

signal

used

port

set

system

console

transfer.

data

the
that

and

Table

3-4

CSEQ MCA Signal Descriptions (Cont)

Signal

Comments

PPI ACKNOWLEDGE

Internally generated signal that enables the
console to drive the bidirectional bus from
PPI

CONS WRITE

port

Internally generated signal that is used as a

control

create

the

signals:

WR CLOCK PERIOD
WR BURST COUNT
WR CLOCK CONTROL

WR CLOCK REG <2:0>
WR VBUS CONTROL

WR CONTROL REG <2:0>
SET L/R RCVR DONE

IIT

3-16

following

enable

3.4

CONSOLE/VAX

3.4.1

Console

8800

Registers

(Refer

SUMMARY

Figure

3-7)

LEFT RECEIVE DATA BUFFER
LRXDB
WRITE ONLY
CONSOLE ADDRESS =0

<7:0>

INITIALIZED BY DCLO OR CPU INIT TO OO(HEX)

DATA FROM CONSOLE TO LEFT CPU

LEFT RECEIVE DATA BUFFER
LRXDB
WRITE ONLY
CONSOLE ADDRESS = 1
INITIALIZED BY DCLO OR CPU INIT TO O
07

<156:8>

NOT

USED

L RXDB
IDENT 3

L RXDB

NOT
USED

L RXDB
IDENT 1

L RXDB
IDENT O

IDENT 2

RIGHT RECEIVE DATA BUFFER
RRXDB
WRITE ONLY
CONSOLE ADDRESS = 2

<7:0>

INITIALIZED BY DCLD OR CPU INIT TO OO(HEX)

DATA FROM CONSOLE TO RIGHT CPU

MKV86-1279

Figure

3-7

Console

Registers

ITI

3-17

(Sheet

<15:8>

RRXDB
RIGHT RECEIVE DATA BUFFER
CONSOLE ADDRESS =3
WRITE ONLY
INITIALIZED BY DCLO OR CPU INIT TO O

NOT
USED

NOT

USED

R RXDB | R RXDB
IDENT 3 | IDENT 2

NOT
USED

R RXDB | RRXDB
IDENT 1 | IDENT O

LCLR
LEFT COMMAND LOAD REGISTER
CONSOLE ADDRESS = 4
WRITE ONLY
INITIALIZED BY CPU INIT TO O

(015)

NOT

COMMAND TO GATEWAY CONTROL

]

MCA OF LEFT CPU

USED

]

LDLR
LEFT DATA LOAD REGISTER
CONSOLE ADDRESS =5
WRITE ONLY

NOT INITIALIZED

RAM DATA OR ADDRESS TO LEFT CPU
|

]

RIGHT COMMAND LOAD REGISTER RCLR
CONSOLE ADDRESS = 6
WRITE ONLY

NOT

USED

INITIALIZED BY CPU INIT TO O

NOT

USED

COMMAND TO GATEWAY CONTROL
MCA OF RIGHT CPU
|

Figure 3-7

]

Console Registers (Sheet 2 of 7)

RIGHT DATA LOAD REGISTER
RDLR
WRITE ONLY
CONSOLE ADDRESS = 7

)

NOT INITIALIZED
V4

[

RAM DATA OR ADDRESS TO RIGHT CPU
|

]

CONTROL REGISTERO
WRITE ONLY

CRO

CONSOLE ADDRESS = 8

INITIALIZED BY DCLO TO FF(HEX)

LEFT

CPU
INIT

CONTROL REGISTER 1
WRITE ONLY

RIGHT
CPU
it

CR1

CONSOLE ADDRESS = 9

INITIALIZED BY DCLO TO OO(HEX)
07

M
ENABLE | NMI
UNJAM | LRXDB | SLOW

HALT

|ENABLE

| RRXDB

|TRAPON|

LEFT

INTRPT

|TRAPON|

| INTRPT

RIGHT

|LMATCH|

CPU

|RMATCH|

CPU

| MODE

ENABLE

|ENABLE

HALT

CONTROL REGISTER 2 CR2
WRITE ONLY
CONSOLE ADDRESS — A
INITIALIZED BY DCLO TO 0
07

SgETD

ngTD

ngo

ENABLE

| DISABLE | DISABLE | CLEAR

| SET CPU

BACK

| WRITES | WRITES

| FLAG

IDPLOOP-{|

LSDF

| RSDF | LATCHED | TIMEOUT
|RESET

MKV86-1281

Figure

3-7

Console

Registers

ITT

3-19

(Sheet

VBC

VISIBILITY BUS CONTROL

WRITE ONLY

CONSOLE ADDRESS = B

INITIALIZED BY DCLO TO O

NOT

SELECT |STOP

STEP

XBD%EESS

USED

|OUTPUT

CLOCK CONTROL REGISTER CCR
WRITE ONLY CONSOLE ADDRESS = C

INITIALIZED BY CONSOLE SOFTWARE TO 78(HEX)

'L‘ngTD

ngD

LNJ(s)gD

STOP

|DISABLE

CLOCKS

|L MATCH |R MATCH| BURSTS

|DISABLE | DISABLE | ENABLE

stow
START |STOP ON |STOP ON|clocKk || CLOCK

BURST COUNT REGISTER BCR
WRITE ONLY CONSOLE ADDRESS = D
INITIALIZED BY CONSOLE SOFTWARE TO 0O

00
1

NUMBER OF CYCLES FOR CLOCK TO RUN DURING A BURST OPERATION
L

CLOCK PERIOD REGISTER CPR
WRITE ONLY CONSOLE ADDRESS =E
INITIALIZED BY DCLO TO 38(HEX)

INITIALIZED PERIOD = 70.18 NS

SELECT

{1/ (CLOCK PERIOD x 250K} } -1

LO FREQ
RANGE

]

}

!
MKV86-1282

Figure 3-7

Console Registers
ITI

3-20

(Sheet 4 of 7)

LEFT TRANSMIT DATA BUFFER

READ ONLY

LTXDB <7:0>

CONSOLE ADDRESS =0

DATA FROM LEFT CPU TO CONSOLE

LEFT TRANSMIT DATA BUFFER LTXDB <15:8>
READ ONLY
CONSOLE ADDRESS = 1

NOT

L TXDB

NOT

L TXDB

USED

IDENT

USED

IDENT

<3>

<2>

<1>

<0>

RIGHT TRANSMIT DATA BUFFER RTXDB <7:0>
READ ONLY
CONSOLE ADDRESS = 2
07

DATA FROM RIGHT CPU TO CONSOLE

RIGHT TRANSMIT DATA BUFFER
READ ONLY

ngD

NOT

R TXDB

<3>

<2>

USED

IDENT

RTXDB <15:8>

CONSOLE ADDRESS =3

IDENT

NOT

R TXDB

<1>

<0>

UgED

USED

IDENT

MKV86-1283

Figure

3-7

Console

Registers

ITI

3-21

(Sheet

VISIBILITY BUS ACCESS

VBA

CONSOLE ADDRESS = 4

READ ONLY

IST
CONSOLE INTERRUPT STATUS
CONSOLE ADDRESS = 6
READ ONLY

NOT

NMI

LEFT

RIGHT | MUST

RIGHT | LEFT

USED

CST
CLOCK STATUS/TIMEOUT
CONSOLE ADDRESS = 8
READ ONLY

Sf‘JSE’S

II'IMCCPRUO

Enfé:izuo

CLOCKS|

BURST | NOT

NOT

|LePu

R CPU

USED | TIMEOUT | TIMEOUT

USED

RO | MaTcn | DONE

TIMEOU =1 TIMEOUT=1

STOP=1 MATCH=0 MATCH=0 DONE=0

BACKPLANE/CLOCK REVISION REV
CONSOLE ADDRESS = A
READ ONLY

]

CLOCK MODULE REVISION LEVEL

CPU BACKPLANE REVISION LEVEL
|

|
]

]

]
MKV86-1285

Console Registers

b=l

Figure 3-7

(Sheet 6 of 7)

SERIAL NUMBER
READ ONLY
07

SER

<7:0>

CONSOLE ADDRESS = C
04

LOW BYTE OF SERIAL NUMBER FOR SYSTEM IDENTIFICATION REGISTER
]

]

SERIAL NUMBER
06
I

CONSOLE ADDRESS = E

05
|

SER <15:8>

READ ONLY

]

02
I

HIGH BYTE OF SERIAL NUMBER FOR SYSTEM IDENTIFICATION REGISTER
]

]

]
MKV86-1286

Figure

3-7

Console

Registers

ITTI

3-23

(Sheet

VAX 8800 CPU Registers (Refer to Figure 3-8)

3.4.2

TRANSMIT DATA BUFFER TXDB <7:0>
CPU ADDRESS =0
WRITE ONLY
INITIALIZED BY DCLO OR CPU INIT TO OC

DATA FROM CPU TO CONSOLE
1

]

TRANSMIT DATA BUFFER TXDB <15:8>
CPU ADDRESS = 1
WRITE ONLY
INITIALIZED BY DCLO OR CPU INIT TO O

NOT
USED

TXDB
o
IDENT
3

TXDB
IDENT
ol

NOT
USED

TXDB
IDENT
i

TXDB
IDENT
g

NCT

DATA BUFFER CONTROL AND STATUS

CPU ADDRESS = 2
WRITE ONLY
INITIALIZED BY DCLO OR CPU INIT TO O

NOT

E%ELE

NOT

E’;‘('ggLE

INTRPT

USED

USED | NTRPT

INTERVAL CLOCK CONTROL/STATUS

CPU ADDRESS =3
WRITE ONLY
INITIALIZED BY DCLO OR CPU INIT TO O

DBCS

USED

)

ICCS

USED

noT | ciear | FUN |TRANSFR | not
CLEAR | ENABLE | STEP
USED
NICR
oy oy- ||TOICR
(jgep | ERROR | CLOCK
|
INTERVL
|
TIMER
|
nTrpr INTRPT | cLocK
|

WRITE 1
TO CLEAR

Figure

3-8

VAX 8800 CPU Registers
ITI

3-24

MKVE6-1287

(Sheet

NEXT INTERVAL COUNT REGISTER

WRITE ONLY

NICR

<7:0>

CPU ADDRESS =4

INITIALIZED BY DCLO OR CPU INIT TO 00

INTERVAL COUNT REFRESH VALUE BYTE O
|

NEXT INTERVAL COUNT REGISTER
WRITE ONLY
CPU ADDRESS =5
INITIALIZED BY DCLO OR CPU INIT TO 00

NICR

<15:8>

INTERVAL COUNT REFRESH VALUE BYTE 1
]

]

NEXT INTERVAL COUNT REGISTER

NICR

<23:16>

WRITE ONLY
CPU ADDRESS = 6
INITIALIZED BY DCLO OR CPU INIT TO 00
07

06
]

03
]

INTERVAL COUNT REFRESH VALUE BYTE 2
L

]

NEXT INTERVAL COUNT REGISTER
WRITE ONLY
CPU ADDRESS = 7
INITIALIZED BY DCLO OR CPU INIT TO 00

06
!

05
1

{

NICR

<31:24>

INTERVAL COUNT REFRESH VALUE BYTE 3
L

]

]
MKv86-1284

Figure

3-8

VAX

8800

CPU

IIT

Registers

3-25

(Sheet

RXDB <7:0>
CPU ADDRESS = 0

RECEIVE DATA BUFFER
READ ONLY

INITIALIZED BY DCLO OR CPU INIT TO 00

]

04
|

03
T

DATA FROM CONSOLE TO CPU
|

]

RXDB <15:8>
RECEIVE DATA BUFFER
CPU ADDRESS = 1
READ ONLY
INITIALIZED BY DCLO OR CPU INIT TO 44(HEX)
07

RXDB

ERROR

OCCURRED

RXDB

IDENT

<3>

<2>

RXDB

IDENT

TXDB

DATA BUFFER CONTROL AND STATUS
CPU ADDRESS = 2
READ ONLY
INITIALIZED BY DCLO OR CPU INIT TO O8(HEX)

RXDB

INTRPT
DONE | ENABLED

RXDB

ENABLED

IcCS

iINITIALIZED BY DCLO OR CPU INIT TG O
Yl

NTRPT

| TIVER

i
al> AV

INTRPT
occurrep| ENABLED

atal

Nalal

<0>

DBCS

Renb | INTRPT

INTERVAL CLOCK CONTROL/STATUS
READ ONLY
CPU ADDRESS = 3
H-

<1>

lals» 1N

ERROR

02
INTERVL

|occurrep| CLOCK
RUNNING

MKV86-1288

Figure

3-8

VAX 8800 CPU Registers

IIT

3-26

(Sheet

3 of 4)

INTERVAL COUNT REGISTER
READ ONLY
CPU ADDRESS = 4
INITIALIZED BY DCLO OR CPU INIT TO 00
07

ICR

{

<7:0>

]

BYTE O OF CURRENT INTERVAL COUNT
]

]

INTERVAL COUNT REGISTER

ICR

<15:8>

READ ONLY
CPU ADDRESS =5
INITIALIZED BY DCLO OR CPU INIT TO 00
07

]

BYTE T OF CURRENT INTERVAL COUNT
]

INTERVAL COUNT REGISTER
READ ONLY
CPU ADDRESS = 6
INITIALIZED BY DCLO OR CPU INIT TO 00

ICR

<23:16>

]

BYTE 2 OF CURRENT INTERVAL COUNT
|

INTERVAL COUNT REGISTER

ICR

<31:24>

READ ONLY
CPU ADDRESS = 7
INITIALIZED BY DCLO OR CPU INIT TO 00

04
|

03
l

02
|

{

]

BYTE 3 OF CURRENT INTERVAL COUNT
|

]

MKV86-1292

Figure

3-8

VAX

8800

CPU

ITT

Registers

3-27

(Sheet

3.5

CONSOLE CABLING

The
cables
that
connect
the console to the VAX 8800 system are
listed
in
Table
3-5
and
illustrated
in Figure 3-7. The first
column
of the table (Item) contains a callout reference to Figure
3-9.

Table

3-5

Console Cable

List

Item Description

Part No.

From

(A)
(B)
{C})
(D)
(E)

17
17
17

Cons Dist J6
CPU J22
CPU J23
Cons Dist J2
88X

MPS 2
Jé63
Cons Dist J4
Cons Dist J5
PC 380
PC 380

Console to EMM cable
Console Cable #2
Console Cable #1
PC 380 BCC26-201 CBL
PC 380 Power Cable

17
17

00655-01
00651-01
00649-01
00665-01
00442-17

I11

3-28

MODULAR POWER SUPPLY

:
(A)

MPS 2
J63

—P

(?)

CLK

J22
J23

XBl0o

VAXBI1

CPU

MEM

(C)—»
BULKHEAD
DISTRIBUTION

|
J5J4

88X

VAX8800

CABINET

(D)

—>

<4—(E)

PRO-38N

SCLD-269

Figure

3-9

Console

Subsystem

IIT

3-29

Cabling

Diagram

EK-KA88P-TD-PRE

SECTION
POWER

SYSTEM

COMPLEX

CHAPTER
GENERAL

1.1

INTRODUCTION

The

power

main
ac

supply

CPU(s),
utility

voltages
dc

DESCRIPTION

power

required

voltage

1is
are

the

system.

Chapter

Both

required

operate

Chapters

the

Details

wused
located

general

the

power

supply

This

chapter

and

indicators

and

are

illustrations

operational

the

for

the

system.
the

referred

comprehensive

and

the

specifications

the

Appendix.

configurations,

8800

power

system

and

the

system.

its

basic

components,

controls,
includes

components,
and

general

system.

1-2

block

diagram

the

power

system.

Figure

1-3

block

diagram of

the

power

system.

1-1

layout
the

the

Figure

and

1-1

physical

following

descriptions

module

dc
the

components.

Figure

layout

and

supply.

power

The

modules
In

the

functions.

power

operate

Three-phase

of the power supply and
generate
the
dc
voltages

components,

power

power
power

cabinet.

power

its

VAX

descriptions

specifications

CPU

system.

occasionally

signals

the

presented

introduces

8800

description

their

operating

modules

and

contain

modules

the
is

used

CPU

necessary

VAX

energize

refer

the

using

supply

the

voltages

of
to

components

and

supply

developed

names

provides

the

VAXBI

power

1
introduces

power

and

regulators

paragraphs,
power

provides

memory

blower

the

VAX

8800

system

showing

subsystem.

the

CPU CABINET

FRONT END CABINET

BLOWER ASSEMBLY

Cl1750

BA11-A
MODULAR POWER SYSTEM (MPS)

BBU
CPU-VAXBI-MEMORY

CONSOLE

CARDCAGE

XFORMER
AC IN T
UTILITY

876A

NBOX

POWER

Figure

SCLD-445

1-1

VAX 8800 System Physical Layout

(Front View)

3-PHASE AC

3-PHASE

BLOWER

208

SYSTEM

FACILITY
INPUT

+/-12, +5
+10.5 V

VDC (ISOLATED)

NBOX
PORT

876A

CONTROLLER
TROLLE

gble%SE

»| CONDITIONER

VOLTS

300 VDC

1-PHASE

PRO-38N

SINGLE
PHASE

H7180

H7180 AIR/TEMP
SENSORS

B H7187 | CPU B/P

H7187

SPARE | MEMORY

CONSOLE

H7188

B/P

7189 | CPU B/P | cPU
»

120 V

H7189|1/0

yaN

H7186

[B/P

BATTERY

H7186

BACKUP

BACKPLANES

MPS

UNIT

120

VOLTS

H7231-D

300 VDG

SCLD-447

Figure

1-2

VAX

8800

Power

System

1-3

Block

Diagram

(60

Hz)

3-PHASE AC
FACILITY
INPUT

3-PHASE

BLOWER

| &0 M2)

SYSTEM
+/-12, +5 VDC (ISOLATED)

+10.5

XFORMER
NBOX

876A

> CONDITIONER

gg@HeSE

CONTROLLER

300 VDC

VOLTS

1-PHASE =

H7180

AIR/TEMP >
» H7180 FerNSORS

H7187 |CPU B/P

120 V

H7188

H7187

SPARE | MEMORY

H7186 |B/P

BACKUP

ISDH\/I\%EE

PRO-38N

H7186

BATTERY

CONSOLE

B/P

H7189 [CPU B/P

2
@

H7189 [1/0

PORT

UNIT

BACKPLANES

120

VOLTS

H7231-D

300

VDC

SCLD-448

Figure 1-3
1.2

The

SYSTEM COMPONENTS

power

listed

VAX 8800 Power System Block Diagram (50 Hz)

system

in Table

shown

1-1.

Table

1-1

Component
876A power controller

NBox power converter

Modular power supplies
Environment monitor module
Battery backup (option)

Air flow blower system

Power

System Components

Mnemonic

Component Number

876A

NPC

H7180, H7186,

MPS

H7187,

H7188
H7231-D

EMM
BBU

AFS
v

1-4

H7189

1.2.1
The

876A
876A

power

is
to

system.

passed
the

Power

power

Three-phase

through

876A

for

from

Controller

controller

BRKRl,

power

the

1is

the

main

distribution

876A

main

facility

feeds

system
to

the

switched

Switched
the

three-phase

and

Unswitched

)

Switched

single-phase

three-phase

power

single-phase

power

breaker,

1.2.2

NBox
NBox

modules

listed

Power

Module

H7170A

H7170A
ILM

(X)

(Y)

system

unswitched

power

single-phase

power

BBU.

blower

system.

the

expander

units

Converter

1is

Table

multifunction

power

assembly

that

contains

1-2.

Table
NBox

1-2

NBox

Modules

Converts

for

300

Same

3-phase

power

into

300

Vdc

power

out

bus.

above.

Provides

logic

power

signal

system

interface

components.

between

Also

EMM

and

controls

BBU

operation.

NBT

the

Function

other

CSP

the

components.

(C1750).

The

for

8800

the

module
VAX

and

system

unswitched

power

the

circuit

NBox.

input

and

follows:

)

power

Converts

single-phase

voltages:

Converts

logic

signals

Also

interfaces

operation.

Vv,

+/-12

1-5

power

+10.5
for

with

for

logic

EMM,

level

ILM.

start-up

and

system

DIGITAL

power

bus.

1.2.3
The

Modular
Modular

located

above

contains

the

operating

system.

The

MPS

nest

(EMM),

described

Power

1is

by
are

fed

CPU

from

cardcage

the

regulators

main

CPU,

also

contains

briefly
to

the

memory,

the

connected

(MPS)

power

applied

cabling

System

the

8800

Power

main

that

and

the

power

supply

CPU

extender

the

Environmental

power

supplies,

located

ac-to-dc

power

bus.

The

the

The

converters

nest
MPS

power

for

the

Monitoring

section.

power

modules

following

300-Vdc

module

cabinet.

provide

the

H7170

Module

MPS

nest,

300-Vdc
located

VAX

buses
in

the

area,

one

NBox.

There

are

which

three

provide

power

The

backplane

MPS

300-Vdc

connects
to

The

the

power

power
CPU

memory

provides

power

assignment)

The

EMM,

The

CPU

The

environmental

1.2.4
The

and

Environmental

(8085)

during

signals

the
ILM

battery

the

MPS

regulator

backup

used

operation.

for:

(MPS

power

the

powerup,

powerdown,

and

requlators

modules

(via

NBox

backplane)

backplane

Environmental

based

located

module

connections

control

BBU

CSP,

buses

supply

monitoring

Monitoring

module

1located

signals

Module

(EMM)

MPS

cage.

the

microprocessor-

used

monitor:
power

regulator

status

Power

system

start-up

Environmental
The

EMM

system

the

main
the

during

backup

description

functions

and

conditions

and

control

battery

complete

the

also

console

provides
during

operation

system

operation

within

communications
power

system.

power-up

and

the

main

link

CPU

between

cabinet.
the

Additionally,

power-down

VAX

8800

the

EMM

sequencing

and

operations.
of

the

performs

EMM

module

and

presented

(o))

Power

detailed

Chapter

discussion

1.2.5

Cooling

for

internal

System

the

VAX

operating

range

accomplished

induction
°

motor.
A

motor

centrifugal

the

wvanes
CFM

blower

The

air

the

EMM

CPU

1.2.6

blower

Battery

the

capability

that

also

Backup

utility

the

Unit

two

the

charging

circuit

)

dc-to-dc

converter

battery

backup

converts
mode.

the

The

BBU

This

three-phase

include:

416

Vac,

Hz)

sets

vanes

and

deliver
8800

1100

cabinet

each

end

the

cabinet.

approximately

CPU

1200

cabinet,

monitored
air

provides

the

VAX

main

CPU

memory

lost.

The

the

CFM.

outputs
The

continuously

thermistors

flow

rate

within

H7231-M
the

rechargeable

the

proper

shaft

VAX

acid

300

vdc)

300

volts

(48

volts
is

option

1-7

8800
data

BBU

lead

batteries)

The

(or

the

temporarily

system

type

senses

(BBU)

protect

power

CPU

monitored.

Unit

48-volt

with

used

the

movers

approximately

within

cooling

double-ended
air

maintain

operation.

powered

within

shaft

within

Battery

Vac,

placed

The

208

with

which

cabinet

system

the

module,

strategically

designed

cabinet

system

air.

rate

temperature
the

CPU

forward-curved

free

flow

normal

dual-outlet

motor

are
in

CPU

air-moving

three-phase

Quad-inlet,

1800

main

components

The

the

The

system

the

for

wusing

induction

8800

temperature

battery

for

the

system
in

the

consists
pack

for

VAX

with
event

of:

(four

use

8800

the

systemn.

1.3

The
the

MECHANICAL

CONFIGURATION

VAX
8800 power system components are housed in two cabinets,
main CPU cabinet. The front-end
the
and
cabinet
front-end

cabinet

contains:
AC distribution components
The main circuit breaker (BRKR1)
The

BBU

I1/0 expander modules
Power

cables

transformer

The components contained
876A

Power

(BAll-A),

(CI750)

(international only)

in the CPU cabinet

are:

Controller

NBox

MPS

power

regulators

EMM

Blower

system

300

buses

MPS

backplanes

I/0

bulkhead

Console interface
Power/Signal distribution

Figures
cabinet,

1-4
and
and
the

1-5
show
location

the
of

cables

front
and rear view of the CPU
the
power components within the

ju—

cabinet.

A.M.D.

BLOWER ASSEMBLY

MODULAR

POWER REGULATORS AND CAGE

[€—— MPS BACKPLANE # 2

101

P€——MPS BACKPLANE # 1—3{
H

HoooH

7
8

L
|

CPU

;

CONSOLE

BOX

/ VAXBI | VAXBI
|

;

CARDCAGE

POWER

LOGIC

|
>

MEMORY

‘

300 V BUSES

1/0 BULKHEAD

876 POWER
CONTROLLER

NBOX POWER

CONVERTER

SCLD-449

Figure

1-4

VAX

8800

CPU

1-9

Cabinet

Front

View

300

VBUS #

300

TS2

VBUS #

7
1

TS3

%’1

MODULAR POWER SUPPLIES,

Ts4

MPS BACKPLANE # 2

AFS

H7188

VBUS #

AFS

|€——MPS BACKPLANE # 1+—plg
H

300

BACKPLANE,

]

AND CAGE

C
L
0

CPU

MEMORY

M
0
D

LOGIC

CARDCAGE

1/0

BULKHEAD

876

NBOX

NOTE:

TS =

AFS

AM.D

O
TS1

POWER

CONTROLLER

TEMPERATURE SENSE
=

AIR
=

FLOW SENSE

AIR

MOVING

DEVICE
SCLD-74

Figure

1-5

VAX

8800

CPU

Cabinet

Rear

View

876A Power Controller
1.3.1
The
876A
power
controller
mounts
to the base of the H9650 CPU
cabinet at the lower left side, as viewed from the front. The 876A
is
approximately
10.0
1inches
ide
by 10.0 inches deep by 8.0"
high.

NBox Port Conditioner
1.3.2
The
NBox
mounts
to
the
base of the H9650 cabinet on the lower
right
side
as
viewed
from the front. The NBox is approximately
19.0 inches wide by 19.0 inches deep by 7.0 inches high and weighs
100 pounds. Connections to the NBox include:
DIGITAL

power

control

300-vdc

power

bus

300-Vdc storage capacitors
MPS backplane control logic
Battery backup unit

(EMM)

A
minimal
amount
of
«cooling
is
required by the NBox. This is
accomplished by placing the NBox in the intake air stream with its
heat
sinks in the air flow path. Screened openings in the chassis
of the NBox allow the moving air to circulate through the chassis.
1.3.3

MPS Modules

The
MPS
cage
to
supporting
of
the
power

(Regulators)

and Cage

is a sheet metal/tubing structure that, in addition
the MPS modules and the EMM, provides for mounting
backplane
and
the
300-Vdc
bus input to the MPS

regulators.

The
cage
1is
mounted
on
four corners and bolted to the cabinet
directly
above the logic cardcage. It has the capacity to contain
up

The

MPS

modules

backplane

and

the

spans

EMM.

the

width

the

MPS

cage

and is

fabricated
in
two sections. The MPS backplanes contain the power
control
signals
and environmental monitoring signals to and from
the

EMM

module.

The
MPS
regulator
modules are inserted into the MPS cage in the
designated
area.
Each module provides regulated dc power that is
distributed

means

connected

the

CPU

logic

the

MPS

backplanes.

1-11

backplane

or bus

bar straps

1.3.4
The

Battery
optional

cabinet

Backup

Unit

1is

mounted

BBU

viewed

from

the

assemblies:

)

The

charging

The

°®

dc-to-dc

The

48-volt

The

BBU

inches

module

wide

and

cooling.

Therefore,

the

1.3.5

converter

lead

1is

BBU

side

Air

Flow

CPU

cabinet,

above

The

rotary

blower

for

acid

7.0

causes

air

flow

through

the

cabinet.

Thermistor
temperature

MPS

creates

cabinet

three

circuit

high
pounds. It

flow

15.12

inches

requires

flow

system

located

cage.

negative

drawn

into

components

(T1-T4)

air

monitoring

front-end

battery pack

inches

air

the

sensors
and

the

contains

deep

minimal

19.0

amount

front-end

cabinet

System
the

which

module

of
the
module
in
the
convection cooling requirements.

blower

for

right

The

circuit

weighs

The

EMM

the

placement

satisfies

the

front.

and

rate

and

air

before

flow

1-12

the

within

cabinet

provide

purposes.

pressure

the

sensors
this

the

exiting

top

(AFS)

the

cabinet,

bottom
the

top

sense

information

and
of

the
the

1.4

POWER

l1.4.1

Power

utility

the

power

front-end

main

terminal
The

power

single-phase

The

the

876A

system

Dby

plugs

provided.

Figure

shows

power

1-6
1-3

1lists

the
the

from

8800

power

the

is made to
cabinet.

system
is

cabled

and

power

the

the
to

rear

BRKRI1,

connected

powered

provided.

1-13

Dranetz

phase

console

the

second

monitor

outlet

box

single-phase ac power to
receptacles located on its

located

components

blocks

cabinet.

system

components

receptacles

terminal
CPU

the

three-phase
means

for

VAX
ac

from which

is routed
cabinet.

receptacles

Table

cabled

located

front-end

distributes

Power

breaker,

cable

CPU

the

distribution.

connection

the

components

chassis.

system
power

into

Three-phase

<circuit

for

power

accessed

located

brought

controller

three-phase
port

cabinet.

system
blocks

three-phase

876A

DISTRIBUTION

are

inserted

the

rear

the

876A

into

the
and

the

876A.
the

CPU CABINET (LEFT SIDE

FRONT END CABINET

CPU CABINET

]

Jaeds | U
B
B

\T*—-‘

J20o

EXPANDER CABINET

—

AC DISTRIBUTION BOX

N
-

“‘_—j/

oo__:

[

% —
C 2

J2
o

=
-

CONSOLE

\\ Q)

Sin
¢ ¢

PC-38N SYSTEM UNIT
(BACK VIEW)

CONSOLE POWER

OUTLET ASSEMBLY

e
}

:
p—

RTI

RECEPTACLE

FRONT END CABINET (RIGHT SIDE VIEW)

PANEL

~ MAIN AC POWER

DISTRIBUTION

o J1

- \Fu

TRANSFORMER BOX

BBU

1/0 BULKHEAD

VIEW)

RECEPTACLE

AC POWER
RECEPTACLE

(-J18)
5CLD-72

Figure 1-6

876A Rear View Showing Receptacles

Table

1-3

876A

Power

Distribution

Component

Three-Phase

Single-Phase

NBox

Blower

BBU

CI1I750

1.4.2
The

DC
VAX

Power

8800

system

uses

(H7170X

and

300-volt

BBU,

produce

the

logic

During

normal

two

H7170

lost,

the

NBox.

During
support

Figure
dc

power

system

voltages

modules

300-Vdc

power

dropouts,

module

the

power

1-7
1is a block
section of the

the

300

Vdc

diagram
VAX

of
8800.

the

provided

regulator

operate

power
NBox.

the

supplied

power

distribution

300-V

provided

memory

power,

the

required

located

supply

operation,

power

discussion

the

is
If

BBU

supply

the

NBox

that

system.

supplied
ac

the

BBU

module.

presented

the

components

utility

controlled

1-15

the

modules

through

is
A

used

detailed

Chapter

that

the

power

support

the

p H71gg
NBOX

+5,-2,+15
o

ILM
1-PHASE

+/-12,+5

CcSP

+10.5

‘

7189

7170X
H7170

300 VDC

+/-12,-5,

+5,-2,+415

CPU

H7180

NBT

3-PHASE
C

1205

+/-1

H7180

5.2
5.2

17
H7170Y

300 VDC

r—b— H7187

=20

»| H7is7 20

+50
‘

H7186

|20

300 VDG
>

)

MEM

BBU

SCLD-450

()]

Section

l.__l

Power

'.-_l

1-7

Figure

Block

Diagram

1.4.3

Controls

1.4.3.1
system

the

Controls
are

BRKRI,

front-end

system

Breakers

=--

The

primary

power

the

main

circuit

breaker,

cabinet,

and

the

Placing

these

two

console

keyboard

switches

operate

are

PRO-38N

issue

accomplishes

system

all

the

tasks

and

Circuit
Breakers
-fully configured VAX 8800
two

(2)

single-phase.

characteristics

the

Table

VAX

for

the

panel.

front

There

power

8800

Breaker

876A

1-4

1lists

Circuit

BRKR2(CB1)

Main

BBU

Aux.

BRKR1(CR1)

Main

Dranetz

Module

Input

H7170Y

CrR

Module

Console

power

system

8800

The
that

location

and

Sys.CR

NBox

8800

the

3
3

VAX

system.

VAX

Out.
H7170X/Y

H7170X

Figure

means

Input

NBox

The

Comment

Console

the
the

Breakers

Cab.

allows

8800
the

the

are nine (9) circuit breakers
system, seven (7} three-phase

VAX

enabling

system

for

8800

rear

breakers.

Phases

F.E.

position

power

VAX

the

located

mode,

the

switch

(1)

device

Component

console

Table

circuit

1-4

controls

1.4.3.2

(1/0)

the

for

located

software-driven

commands

frontpanel

power

the

EMM.

There

ON/OFF

controls

console.

system

the

and

circuit

1-8.

1-17

breaker

Ph.Mon.

Input

diagram

shown

FRONT

END

CABINET

J14,J15

BLOWER
J17

47231

BBU}——
J13

UTILITY

INPUT

—

csp

cBl

J12

CB2

CB1

v
DRANETZ

H7170X

|«

PORT

CB3

cB2

81-T

H7170Y

CB1

CB4

J11
NBOX

CB1

CONSOLE

SCLD-451

Figure

1-8

VAX 8800 Power System Circuit Location

Diagram

1.5

The

POWER

following

SPECIFICATIONS
a

summary

the

VAX

8800

power

1.5.1

Electrical

1.5.1.1

Power

Sources

vac,

Hz,

3-Phase,

5-Wire

WYE

Hz,

3-Phase,

4-Wire

Delta

requirements.

Requirements

Domestic

120/208

connected

service.

International

240/416

Vac,

Taps

are

and

440-Vac

available

inputs.

applied.

Refer

additional

Line

the

VAX

8800

details.

the

Taps

must

System

transformer

and

selected

Installation

connected

service.

accommodate

380-vac

wired

Guide

before

(EK-8800I-IN)

Voltage

equipment

156-222

rms

line-to-line,

208

nominal.

equipment

312-444

rms

line-to-line,

416

nominal.

Amps

max.

156

rms

Amps

max.

312

rms

Line

Current

equipment

Power

Factor

0.65

minimum

0.85

minimum

Power

6500

Consumption

Watts

maximum;

Maximum

Heat

dissipation

1-19

22.2K

power

BTU/hr

for

Environmental

Requirements

DIGITAL STANDARD 102

for Class A environments

Temperature

Ambient

Range

Temperature

Operating

- Centigrade - 15 to 32

degrees

Fahrenheit

Storage - Centigrade
Fahrenheit

-40

degrees

- -40

to +151

to +66

degrees

Humidity

to 80

relative humidity

Altitude

Level

Sea

8000

feet

Weight

1700

1lbs

combined weight

for both

cabinets

Dimensions

inches d x 60

inches h x 73.5

inches combined width

1.6

FAULT AND

The

only

available
messages

the

Each

system

the

inform

The

outer
be

Fault

l.6.1

876A

upper

right

power

Figure

contain

However,

side

covers
the

fault

1indicators

following

Power

power

the

and

shows

and

status

monitor

occur

and

for

CPU

front-panel

these

and

status

the

that

displays

the

status

indicators

displays

are

front-end

not

cabinets

indicators.

power

system

paragraphs.

components

are

located

the

Controller

controller
of

the

has

front

three
panel,

applied.

1-9

faults

status.

operation.

the

when

fault

console

components

normal

view

The

system.

and

status

876A

system

operator

power

front-panel

and

operator.

fault

removed

described

the

power

during

must

The

display

visible

INDICATORS

1indication

modules

that

STATUS

visible

the

front

CB2

panel

CB4

CB3

POWER CONTROL

"POWER"
which

the

lamps

light

876A

when

facility

PC.

REMOTE/LOCAL SWITCH

N
®

\\@
L11©Q O F
o

L2@© (F2
3@ (OFs

2lalR g

SEUN

Teee]]

CB1
SCLD-60

Figure

1.6.2
Figure
Table

1-9

876A

Power

Controller

Front

Panel

NBox
1-10
1-3

shows

the

front-panel

defines

the

visual

location

indicators
Iv

1-21

the

provided.

NBox

indicators.

H7170

3o|
O

NBT

RlR1815

csp

O
O
=

L |
O
d
[

O
A

_OFF

OFF

\_'1_1‘—!—"‘

sus ox O

mobute ok O

over voLTacE O

over cURRENT O
WINDOW DISPLAY

]

'fi

wun

PCM A FAILED

2 | PCM B FAILED
5 | CLOCK FAIL
8 | MANUAL RESET

H7170-A

ELECTROMECHANICAL DISPLAY(OCTAL)
0|

| MANUAL

INTERVENTION

5 | CSP OVERTEMP

7 | MOD B OVERTEMP

SCLD-7i

Figure

1-10

NBox

Front-Pa

Indicators

1.6.2.1
H7170
of

H7170
has

the

Built-In

four

Test

indicators

module.

The

indicate

status.
indication.

Equipment
display

1indicators

Table

1-5

are

lists

H7170

the

<colored

Indicators

GREEN

BUS

GREEN

MODULE

RED

OVERVOLTAGE

FAULT

BLINKING

OVERCURRENT

FAULT

1.6.2.2

1ILM

contains
magnetic

Built-In

two

types

latches

and

Equipment

165

The

Binary

Manual

Binary

CSP

Binary

MOD

digit

display
below:

only

fault

(OO RO BN

failed
failed

BITE
dfined

H7170X

failure.

CLOCK

vdc

has

1ILM

occurred

front

panel

display.

located

below

the

digit

display,

the

ILM

front

panel

the

console

indicates

FAIL

MANUAL

RESET

indication
All

LED

H7170Y

light

the

Intervention

conditions

the

electro-mechanical

below:

that

and

Crowbar

LED

indicators

status

problems

single-digit

electro-mechanical

The

voltage

indicators:

defined

single

Bus

fault/status

are

fault

The

Test

LEDs

Status

panel

operating

indicators

Indication

YELLOW

front

the

Indicator/Color

The

current

other

sent

fault

the

EMM

indications

1-23

for

apply

the

NBox.

MOD

Modular Power Supply Regulators

1.6.3

Figure 1-11
the modular

shows the location of the front-panel indicators for
power regulators. All power regulators have the same

status indications,

as defined in Table 1-5.

Table 1-6

Indicator

Indication

Green LED

Module OK

MPS Regulator Indicators

Definition

The power supply module is operating

properly,

within
other

the

output

regulation

faults

voltage

range,

and

1is

exist.

Red LED

Overvoltage

The module voltages have crowbarred.

Yellow LED

Overcurrent

The module's output current is above

(Blinking)

its rating.

GREEN

LED
o

o
RED
YELLOW ©

H718X

Figure 1-11

1Indicators for the Modular Power Regulators

1.6.4

Environmental

Figure

1-12

location
signal
The

four

fault
are

the

KEY

FAULT.

magnetic

conditions

weighted

Monitoring

diagram
front-panel

latches

above

the

EMM

front

components.

defined

shown

Module

the

Table

Figure

LEDs

1-8.

The

are

The

panel
red

used

octally

indicate

TOTAL OFF CODE

INPUT

KEY FAULT
MOD FAULT

ELECTRICAL KEY
OVERRIDE

(NOT

USED)

SCLD-453

Figure

1-12

EMM

Front-Panel

1-25

Indicators

the

indicators

coded

1-12.

showing

LED

the

latches

Table

Coded

Readout

1-7

EMM

(Octal)

Magnetic

Status

Indicator

Indication

Codes

Device

Black = 0
Yellow = 1

OOO

No failure

001

Not

010

Overtemperature

Module

H71856

011

Overtemperature

Module

H7186

100

Overtemperature

Module

used

(either
101

Overtemperature

Module

H7187

one)
E

(either

H7180

one)

110

Overtemperature

Module

H7189

111

Overtemperature

Module

H7189

1000

Not

used

1001

Not

used

1010

Not

used

1011

Not

used

1100

Overtemperature

Cabinet

(any
1101

Not

used

1110

Not

used

1111

Not

used

1.6.5

System Console

Operation
system

and

console,

control
a

sensors

one

four)

Device
of

the

VAX

modified

8800

PRO-38N

system
that

allows

performed
the

interact
with
the
system.
system
console,
including

A complete discussion of
1its
specifications
and

characteristics,

provided

Section

1-26

this

operator

the

to
the PRO-38N
performance

manual.

CHAPTER
FUNCTIONAL

2.1
Chapter
the

VAX

INTRODUCTION
1

8800
block

descriptions

2,2

DESCRIPTION

this

document

power

system.

diagram

are

POWER

Figure

2-1

system

showing

and

introduced
This

flowchart

presented

the

chapter

level.

Chapter

components

describes
More

the

that

make

power

detailed

system

component

SYSTEM

interconnections.

a
the

BLOCK DIAGRAM
functional block
major

diagram

components

2-1

of
the

the

VAX

system

8800
and

power
the

3-PHASE
I

208 V

AlR

FLOW

SYSTEM
+/-12, +5 VDC (ISOLATED)

876 3-PHASE >
POWER
208
VOLTS
120 V

CONTROLLER

A
UDD

NBOX

SINGLE

CONSOLE

CPU B/P

H7180

"
H7180
AIR/TEMP
H7188 |I"SENSORS
7

H7187

|CPU B/P o

n7187

SPARE
H7186

| MEMORY

H7186 | B/P

120/240

MPS

VOLTS

BACKPLANES

END CAB

FRONT
TRANSFORMER

BAT.(;TERY

ENCLOSURE

UNIT

C1750

BA11-A

BACKUP

H7231-C

] AC FACILITY
L

H7189

o
9

PHASE

| POWER PORT

H7189 | /0 BIP ,,

INPUT

SCLD-454

Figure 2-1

VAX 8800 Power System Block Diagram

2-2

2.3

SIMPLIFIED OPERATION

Utility

front-end

power

breaker,

BRKR1l,

Connections

The

cabinet.

brought
The

and
the

connects

Console

power

port

Dranetz

phase

monitor

)

876A

power

console/printer

The

console

provide

power

port

unswitched

The

Dranetz

which

the

876A

2.3.1

power

Dranetz

876A

power

input

port

Control

for

the

(via

the

The

ngteCt

Interface

876A,

switched

the

and

single-phase

the

Circuit

the

876A

are

console

the

circuit

following:

Breaker

located

power

the

CPU

receptacle

subsystem

three-phase

plug

following

VAX

and

printer

receptacle

into

inserted,

section.

interfaces

8800

3-phase

power

input

and

reptacles

l-phase

for

system modules

with

main

DIGITAL
VAX

three-phase

The

power

listed

system

from

utility

functions

the

system modules

2-1.

modules

(K1

power

conditicns

(BRKR

bus

control

power

2-3

fault

control

power

Table

modules

power

8800

unswitched

modules

the

system.

power

application

Provide

block.

include

switch)
4.

distribution

single-phase

are:

Filter

through

system

Controller

the

system
main

power

monitor

Distribute

the

and

provides

8800

port

controller

block

port

Power

power

VAX

through

the

voltage

described

876A

The

the

controller

(LAS0).

876A

distribution

cabinet.

The

into

passes

module,

the

distributes

three-phase

and

Table

2-1

876A

Power

Module

Phases

NBox

W
Ww

Blower
BBU

BAl1-A

Auxiliary

2.3.2
The

Distribution

port

NBox
NBox

power

converter

H7170

power

converters

above

modules

assembly

containing

the

following

modules:

ILM

CSP

NBT

Each

the

described

the

following

paragraphs.

2.3.2.1

H7170

converts

the

for

use

There

the

are

H7170Y.
connected

Power

the

these

supplies

power
PCs

BBU

regulators.

H7170

both

The
power

MPS

outputs

When

input

two

The

Converter

three-phase

the

these

NBox

H7170
power converter
300-Vdc output power

(NPC),

wunits

designated

supply

the

other

and

buses

regulators.

voltage

input

wunits
300-Vdc

either

H7170

falls

below

regulators

156

rms,

are disabled. Battery backup power from the
power
to regulator B for main memory bias

support.

All

H7170X

300-Vdc

are

disabled

when

2-4

occurs.

2.3.2.2

Control

Start-up

Power

unswitched

single-phase

and

the

The

creates

following

)

+/-12 V

+15

+10.5

output

voltages

2-2

are

+15

shown

Using

CSP

Bias

Modules

Used

ILM,

EMM

ILM,

EMM

V(3)

All

MPS

Table

2-2.

power

Module

functions:

interface

logic

Controls

logic

the

Generates

clocks

Initiates

BBU

for

power

Purpose

Bias

(ILM)

for

the

operation

MPS

Startup

pcb

system

for

Bias

Logic

Provides

The

ILM

power-up

the

Interfaces

utility

New

output

signals

the

system

event

that

Translator

signal

used
with
a

the

during
"FAIL

regulator

DIGITAL

system

Module

conversions
the

power

SAFE,"
is

BBU

control

(NBT)

and

off,

2-5

=--

combination

sequences.

which

turned

performs

sequence

means

bus

The

NBT

power

Box

1logic

with

module

regulators

NBox

2.3.2.4

receives

controller

Voltages

Regulators

provides

CSP

power

Bias

CLK/CNSL

Interface

following

The

876A

voltages:

+10.5

used

Modules

+/=-

the

Voltage

the

bias

(CSP)

from

Table

2.3.2.3

power

CSP

Module

prevents
or

The
BBU

tripped.

logic

NBT

also

the

control

module

functions
provides

operation

the

2.3.3
Modular Power System (MPS)
The
modular
power
system
includes
the
power
regulators
provide the dc voltages necessary to operate the following:
Main CPU

°®
e

Memorv

VAXBI

modules

The
power
regulators are powered
which is split into two sections.

The

that

regulators have

the

kHz

clock

300-volt

dc power bus,

following common characteristics:

Pulse width modulation
50

from the

from

(PWM)

ILM

Line and load regulation
Remote voltage sensing

The EMM module, which monitors the output of the dc regulators and
the
environment
1in
the CPU cabinet, is located in the MPS along
with the eight (8) regulated power supplies.
The

MPS module cage

cabinet

that

a mechanical

The modular power
The

The

MPS

structure

internal

to the CPU

supports:

EMM

supplies

module

The

300-V

The

MPS

cage

buses

backplanes

located

above

the main

CPU

cardcage.

Table
2-3
1lists
the
regulator
modules by part designation, dc
output voltage, and the area of the computer system they service.

Table
Regulator

Module

2-3

Output

H7186

(B)

H7186

5.0

(C)

5.0

H7187

(D)

2.0

H7180

(E)

5.2

H7189

(F,

The

the

output

12.0,

voltages

Flexible

cable
bus

straps

CPU

backplane

etches

MPS

bus

straps

backplane

backplanes,
schematically

VAXBI

connected

are

used

connections

with

minimum

from

Figure

the

H7189 | H7189

H7180

(-5.2)

CPU

volta ge

voltage

CPU,

the

backplanes

drop

memory

and

VAXBI

cabinet,

are

shown

MOD
D | MOD
D

P
MOD
C | MOD
B

| H7180 | H7188 | H7187 | H7187 | SPARE | H7186 | H7186

| -5.2

EMM

(-2.0) | -2.0

+5.0

l+5.0

,——LL—IJ LT GND LT] L‘J[J —
L

52y

—

|
)

YV¢

v
|

VAXBI

BACKPLANES

TO
CPU
BACKPLANE

MEMORY

CPU
BACKPLANE
SCLD-455

Figure

2-2

MPS

Backplane
Iv

Configuration
2-7

when

d r Op.

BACKPLANE 2

MOD
E | MOD
E

VAXBI | (VAXBI)|

the

minimize

the

rear

2-2.

l€———BACKPLANE 1
MOD
H | MOD
F

Memory

5.2,

are

connections

viewed

Backplane(s)

CPU

Laminated

current

Logic

CPU

high

(volts)

Memory

following:

laminated

Regulators

Battery

making
The

+/-

regulator

using

The

Voltage

(Rear

View)

2,3.4
The

Battery
H7231-M

Backup

Battery

system consists
A

battery

dc-to-dc

[

48-volt

The

BBU

The

BBU

Backup

charger

Model

Unit

output

during

Charging

for

acid

battery

power

regulator

(BBU)

backup

failure

supports

power

occurs

regulator

short-term utility

the

48-volt,

battery

the

BBU

from

The

applied

the

level

The
of

BBU
9

provide

The

volts

The

300-volt

the

CPU

memory

for

the

system

8800

power

pack

the

only

active

during

normal

outs.
occurs

120-volt,
876A

H7230

modules

operation.

drop

unswitched

single-phase

power

controller.

charging

circuit

that

batteries.
the
the

batteries
ILM

supporting

from

fully

monitor
the

monitored

its

memory

charged

memory

modules

battery.

modules

during

charge
for
is

prevent

status.
a

minimum

intended

short-term power

occur.

for

converts

700

with

the

BBU

48-volt

dc-to-dc

from

the

converter

battery

pack

module

300

mA.

output

300-volt
a

the

signal

circuit

that

regulator

occasionally

output

During

<charge

capable

(H7240)
dc

1is

and

power
that

fed

current

minutes

losses

voltage

overcharging

VAX

module

power

voltage

that

for

during

The

the

pack

the

for

(H7240A)

battery

system operation
by means

controls

H7231-M)

(H7230A)

converter

lead

provides

utility

(BBU

of:

when

Unit

applied

bus

used

power

loss

modules,

but

period,
only

the

feed
the

module

NBox

the

where

power

300-volt
is

enabled.

interfaced

regulator modules.
is

applied

all

2.3.4.1

BBU

Control

performed

operation

the

BBU

The

in
LO

received

the

response
signal

from

power

1line

voltage

level

Upon

battery

The

responds

Enabling
Asserting
must

The

OFF

BUS

the
to

The

EMM,

Module
The

BBU

208

signal,

(MODULE

RTN)

that

power

signal

sequence

are

true,

then

the

system

power

will

2-3

subsystem

the

EMM

L).

the

signals

the

ILM

correctly

EMM

functioning

asserted.
BBU

provides

(MODULE

ENABLE

disable

300

volts

300-volt

bus

signaled

ILM

requesting

will

completely

turn

shut

down

functional
the

associated

block

(maximum

Mod

off

the

BBU.

the

system

diagram

with

BBU module.

2-9

signal

the
flow

700

BBU,

except

time

deasserted,

control

logic

the

power

control

the

from

regulators

returns.

EMM

all

deasserted.

showing

interconnects

supply

power
the

signal

when
normal ac

The

H).

the

and

rms.

occurs

rms.

ENABLE

met,

OK,

not

output

are

bus.

response

by:

above

continues

backup

commands

module.

NBox.

volts

programmed

156

not

return

Figure

RQUEST

until

reporting

these

below

minutes)
The

response
the

power

issues

EMM

(MODULE

the

must

300-volt

initiates

from

signal

conditions

the

BBU's

which

EMM

request

power

the

monitor

indicate

signal

the

module,

request

power

(ILM

the

ILM

falls

BBU

asserting

line

the

TOTAL

BBU

sent

backup

2.
B

Control
the

phase-to~-phase

receipt

Module

voltage

provide

ILM

-by

Mod
If

operator,

battery
and

the

all

backup
power

AC 1O / BUS LO

3-PHASE

NBOX

BBU

REQ RTN

TO/FROM

CONSOLE

H7188

MODULE ENABLE L

AT
- sumomn
MOD B L

4\ mooue e

SIGNAL

ac
IN

MODULE
B

1/0

H7186

CHARGER

o
TM

BATTERY PACK

<V7

H7230

48 VOLT

+5 VOC B

TO MEMORY
BACKPLANE

DGC-TO-DC
CONVERTER

300

VDG

H7240

BATTERY BACKUP UNIT
H7231-M
SCLD-458

[

Battery Backup Subsystem Functional Block

2-3

Figure

Diagram

2.3.5

The

that

Environmental

environmental

performs

the

Monitoring

Module

monitoring module

following

(EMM)

a multipurpose

logic module

functions:

Monitors

the

status

Monitors

the

environmental

the

modular
status

Communicates logically with the
Enables/disables the regulators

power
of

the

system

supplies
CPU

cabinet

console

Communicates with the ac power system
correct CPU pc board installation

Verifies

The

EMM
contains

is
the

an
8-bit
microprocessor-based
(8085)
module
following microprocessor system support chips.

that

RAM
ROM

I/0
RS232

communications

The
RAM chip provides temporary storage for data and
sent
to
the
EMM
from
the
system
console
over
communications line.
The

ROM

perform

chip

contains

routine

EMM

Regulator
AC

the

tasks.
on/off

preprogrammed

These

set

needed

include:

control

system monitoring

Regulator

output

voltage

Regulator

output

margin

Regulator

temperature

CPU
BBU

instruction

instructions
the
serial

monitoring
testing

monitoring

cabinet environmental
on/off control

monitoring

Figure 2-4 is a functional block diagram of the EMM module showing
the
communications
interface with the system console and the I/O
interfaces to the power system monitoring and testing devices.

2-11

MODULE

KEY LOOPS

KEY

MONITOR

REGULATOR CONTROL
T

POWREG

MARGEN

BBU ENABLED

REGULATOR
— ON/OFF/MARGIN

———————ij

CONTROL LINES

e!
!

MARHILO

!
i

b -5

PRO-38N
SYSTEM

CONSOLE

A4
BBU

CONTROL
y

STATUS

)

REGISTERS

MPS/BBU/EXT

oo }

L __._16-BIT
:

MODOK

ACLO/DCLO

A i‘ -ISBAE(_S _____ y

LOGIC

;

————>

AC/DC LO

(FROM AC INPUT MOD)

SYSTEM AC/DC LO

—————P
.

soD 1

PEEIDEPA

IN/

AIR FLOW STATUS LINES

]

EXTERNAL

OUT CTL

———»(NOT
USED)

;
|

;

—>

VOLTAGE

AIR

ALOW

SENSOR CTL

I SE SENSOR RESET

MEASURING
CIRCUIT

8
b

‘v7

VOLREG

VINSEL

TOTAL-OFF

FTTTTTTTTTTTTTTTTT!

CONTROL

T-

[4¢—————

REGULATOR

OVERTEMP

—————®

TOTAL-OFF

BUS

(TO AC POWER CONTROL)

4—[—‘ THERMISTOR VOLTS

N
<4——— BACKPLANE VOLTS

/__/\__\

PROCESSOR
SYSTEM

BBU ON
———»

GROUND
CURRENT
MONITOR

[4————— GROUND CURRENT

SCLD-457

Figure

2-4

EMM

Functional

2-12

Block

Diagram

The

serial

the

communications

functioning

The

system

the

console

VAX

link
8800

the

power

primary

system

console

vital

system.

user

interface

the

VAX

8800

with

the

system.

The

EMM

system

power

console

system

Function

Power

The

EMM

and

the

2.3.6

Power

main

functions

Monitoring

Notifying

The

monitoring

the

8085

shown

include

the
Key

System

system

a fault occurs, and
action to be taken.

receives

the

EMM

are:

power

system
console

done

using

devices

components
of
that

malfunctions
provide

I/0O

EMM

interface

2-4,

the

I/0

block

section

diagram.

The

the

monitored

located

I/0

signals

following:
faults

control

status

LO
overtemp

temperature

following

the

power

system

Regulator

briefly,

the

<console
when
the corrective

the

MPS/BBU/EXT.

The

conditions

the

Figure

side

AC/DC
CPU

communicates

Monitoring

Regulator
BBU

continually

computer.

1in

right

fault

regarding

The

with

status

system

signals

instructions

monitor,

regarding:

paragraphs

indicating

their

describe

purpose

and

EMM.

2-13

the

input

the

resulting

and

output

signals

fault

response

2.3.6.1
Key Monitoring -- The PC boards in the CPU cage are keyed
to
assure
correct insertion into the CPU PCB slots. The key loop
circuit
verifies that the PCBs are correctly inserted. Failure to
satisfy this requirement causes:

The

Power-up

Reinitialization

power—-up

2.3.6.2

sequence

the microprocessor

cannot

proceed

All

temperature

the

2.3.6.3

and

regulators

BBU

the

thermal

are

fixed

The

Control

EMM

corrected.

modules

EMM,

response

Sends

Signals

BBU

the

output

EMM

AC/DC

request

the

1is

control

also monitored

runaway.

design.

communicates

monitor
BBU
status
and
to
request
signal has been received by the EMM.
The

provides

and

overheating

The

fault

for

internal

the

logic

prevent

Control

until

(8085)

turning
the dc voltage regulators on and off, margin testing,
monitoring the dc output voltage(s) of the regulators.
The

Regulator

halted

the

BBU

with

output when

ILM

an AC/DC

the

signal

has

signal:
ILM

system

console

that

(see

power-down

the

AC/DC

occurred
The

2. 3

ILM

enables

Air

Flow

throughout

the

The

air

falls

flow

below

the

BBU

Status

air

CPU

moving

cabinet

Incorporated
cugtem

for

rate

the

specified

sequence).

into

that
—airia

the

VAX

8800

continuallsx,
R
N
S
J

system

forces
VE
AW

air
4

tlow

rate

coollng.

continuously

monitored.

minimum,

the

EMM

the

air

notifies

the

system

console.,

The

console

responds

initiating

system

shutdown

procedure.

2.3.6.5

AC/DC

Signals

power

system

fault

signals

sent

occurs

utility

the

exists,

power

indication

1in

either

voltage

When

the

receives

EMM

signals

system console
power

Notifies

the

CPU,

through

NBI,

Overtemp.

the

four

The

located

T2,

T3,

CPU

cage

thermistors

with

the

EMM

and

therefore,

location
The

temperature

the

(red

=zone),

initiates

The

the

T4,

fault

temperature

exists

memory

the

monitor

system.

CPU
Cabinet
Temperature
continucusly monitors the thermal
cabinet while the VAX 8800 system is

the

CPU

forced

MPS

cabinet:

air

input

the

air

module

indication

values

flow

the

CPU

output

cage
between

the

cage

reflected

continuously

the

air

temperature

the

thermistors

monitored

the

EMM

located

the

and

compared

upper

limits

set

limits.

senses

sends

power-down

console

thermistor.

REGULATOR

ILM

temperature

message

(TOTAL

OFF)

outside

the

for

the

system

the

OVERTEMP

voltage

signal

1is

regulator

limit.

2-15

has

console.

system,

876A.

individual

the

and

located

the

voltage

are
temperature-sensitive
resistors
that vary
temperature. The thermistor volts signal sensed by
translation of the value of thermistor resistance,

are

EMM

and

specification

When

the

cabinet

line

EMM

CPU

thermistors

condition

immediately:

the

within

1is

that
the

and

phases

disable

operating.

inversely

low

environment

three

Tl,

all

the AC LO condition
system power-down procedure

Volts)

fundamental

fault

Regulator

two

displays

(Thermistor

are

that

indication,

the

There

are

H7170s.

BBU

2.3.6.6

when

EMM

Requests

<console

CPU

the

Notifies

initiates

DC
EMM

system.

and

and
the

The

LO
to

single-phase

line

the

logic

tripping

indication

exceeded

Then

1its

BRKR2

that

operating

The

regulator

when

All

temperature

the

design

regulators

1in

overtemperature

indicator

that

when

temperature

the

When

the

sensors

temperature

module

this

system

2.4

POWER

Powering

proceed

occurs,

(TOTAL

the

EMM

are

the

bimetallic

VAX

8800

generates

system

logic

2.4.1

exceeds

its

upper

notifies

the

system

you

system

VAX

8800

orderly

The
the

main
last

There
seven

All

CBs

must

also

CB,

are

876A

Table

(7)

The

the

verify

are

the

system

manner

power
except

"ON"

turned

limit.

console,

initiating

sequential

successful

process

system

set

the

which

power-up

sequence

all

the

which
on

(9)

BRKR1l,

lists

that

operation

must
is

for

circuit

the

VAX

8800

system

breakers

(CB)

the

position.
enables

CBs
ac

the
in

CBs

controller

manually

the

that

BRKR1l,

nine

2-4

EMM

Breakers

three-phase

modules

the

SEQUENCES

the

initiating

must

OFF).

Circuit

that

contain

signal

achieved.

Prior

devices

exceeded.

part

circuit
they

and

are

at
of

fully
two

contains

located
as

utility

start

the
the

8800
CBs.

system:

CBs.

rear

the

contained

located.

The

2-16

system,

sequence.

VAX

breakers

the

single-phase

prepower-up

indicated.

power-up

configured

(2)

four

power

the

front-end

cabinet

preparations.

function

the
of

system
the

CBs

and
are

Table

Part

Designation

2-4

System Circuit

Breakers

Phases

Amp.

CB2

CB1

Console

876A

input
for H7231-M

CB1

CBl1

(BRKR1)

(BRKR2)

CB2

Rating

Comment
Main
cab)

system
to phase

CB (front-end
monitor

input

CB3

876A

blower

CB4

876A

NBox

CB1

H7170

input

CBl

H7170

input

The

power

sequences

discussed
Figures

2-5

are

.
o«

W
N

There

1in

through

four

with

the

following

power

sequences

for

the

VAX

8800

powerup

section

flowcharts

2-8.

power

Routine
AC

presented

conjunction

(H7170s)

from

BBU

operation

Powerdown

from

console

Powerdown

from

power

command

interrupt

2-17

with

BBU

system:

shown

are

2.4.2

Summary

The

first

the

1is

"ON"

system,
The

step

put

sequence

BRKR1l,

the

to manually

main

circuit

put

all

CBs

breaker

for

the

cabinet

and

last.
ac

distributed

Sequence

power—-up

position.

three-phase

Power-Up

the

utility

the

power

enters

the

controlling

front-end

components

the

power

system.

Three-phase

Dranetz

876A

phase

CPU

Single-phase

unswitched

port

power

the

to:

monitor

the

inside

sent

inside

the

front-end

cabinet

also

sent

the

system

console

console/printer.

NOTE

When

power

PRO-38N

system

console

proceeds

powerup

and

See

the

details

applied
console
to

execute

initialization

following

the

unit,

the

its

own

routine.

publications

console

for

start

procedure.

Iinside

the

VAX

CPU

«cabinet,

The

BBU

The

CSP module

delay

and

+/-12

ILM

EMM

+10.5

Vdc

generated

this

manual

User's

unswitched

(located

less

than

Vdc

bias

voltage

bias
the

module,

signal

+n
Y
A

FMM
1211t 1w

+tha
L
R
S

System

singie-phase

the

minute,

for

Guide

the

sent

from

NBox)
the

CSP

module

following

generates

modules:

NBT

8800

to:

Vdc,

The

Section

876A

After

the

for

the

MPS

regulator

start-up

power

also

CSP.

also

BBU.

located

the

NBox,

response,

the

BBU

2-18

sends

FAIL

BBU

SAFE

AVAIL

ENABLE

signal

Upon

receiving

the

module,

the

ILM

module

displays

the

number

"0"

Similarly,
+/-12
The

Vdc
key

the
bias

<circuit,

EMM

power-up

sequence

may

fault

console

The

cannot

its

the

faults

bias

voltages

performs

display,

after

from

the

CSP

selftest,

and

"OK."

receiving

the

and

correct

placement of CPU PCBs,
detected, indicating that the

are

proceed.

until

the

key

fault

problem

communicate

with

console

issues

the

EMM

the

console

acknowledged

Vdc
on,

numerical

checks

detected,

halts

control

which

the

+/-12

powers

EMM module powers on
voltages from the CSP.

signals

sequence

and

the

POWER
no

key

LED

lights

resolved.

and

During

the
a

power-up

fault,

the

system.

command

faults

the

EMM,

which

exist.

NOTE

CSP

the

automatically when utility
applied.
Otherwise,
the

power

operator

POWER

provides

+15

AIR

CLK/CNSL

POWER

FLOW

REQUEST

switch,

S1,

Blower

NBox

BAl1l-As

mode,

must

type

enable

the

is
console

power

system.

to:

SENSOR

PCB

PCB
signal

from

the

also

sent

the

876A

ILM

enable

power

Vdc

supply

the

power

controller

to:

motor

(H7170s)

The

H7170s

the

regulators

sequentially

set

power

been

power

command

The

has

will

AUTOPOWERON

generate
by

1in
the

300

the

MPS

EMM,

rack.
with

enabled.

The

module

2-19

300-Vdc

buses

feeding

are

enabled

regulators
D

being

the

last

CB 1

Place

(50 Amp)
ON (1)

AC to Console
via J1 CONSOLE

AC to 876s
unswitched

ocutlets
phase

PWR OUTLET BOX

and

indicators

Console performs

AC to BBU
and

After

CSP

a delay

selftest

one

more than

minute, the CSP
gegerates G5fV

EE‘N +/-12
T

aillu

CSP monitors
internal 300 V,

for

generates

1 LIVl

BULK

Alsoc +10.5 bias
voltage for the
MPS

EMM and
receive
+/-12 ¥V

LM
+5 and

init

selftest,

Sna BendeFaiL

o i f test

Shows a

C/Bs are closed

EMM powered, but| | ILM performs

held

state

SAFE

ENABLE"

fo BBU if all

numeric display
number
ok

BEVM performs

‘“‘hard’'’ tests:
EMM tests
parallel key
sense (CPU
module misplace)

If
is

a KEY fault
found; light

‘“'key fault"”
LED on EMM
front panel

v
EMM deasserts

MOD A ENABLE
iLM receives
BULK OK'",
and MOD A
ENABLE
ILM

deasserts

“MOD A INTLK LTM
and sends to EMM

SCLD-475

Figure 2-5

System Power-Up Flowchart

(Sheet 1 of 4)

EMM receives
““MOD

A INTLK

H and

releases

from init.
condition

EMM performs

‘‘default
(in

mode"

ROM)

tests

EMM tests for

Console

air flow (which
> ?flar}fisqrated

establishes data
link (RS232) with

environment

8800

temperatures

parameters.

28 syetom

1t faults are

incurred,

are

timers

started

if
fault is
not removed,

and

TOTAL OFF is
asserted and 876
CB1 is tripped

EMM, and loads
specific

User performs

‘e

power

command
console

EMM

via

v
Asserts

“-SHUTDOWN

RTN

MOD J L'’ and
sends it to ILM
{(turns on MOD J)

JLM asserts
“PWR RQST H''
to

876

and

“FAN/AFS
for CSP

[ j
B

PWR"

CSP sends

v
AIR

FLOW SENSOR

power

Backplane

MPS

(B/P)

CSP sends

+15

switched

CLK/CNSL

board

via

MPS B/P

SCLD-458

Figure

2-5

System

Power-Up

Flowchart

2-21

(Sheet

876

H7170Y lights

“MOD

OK'

powers

and distributes
AC to Blower
Motor, H7170Y,
and H7170X

and

H7170X lights
”MOD

OK''

and

H7170Y distri-

Hri7ox distol.

H7186s,
H7187s

H7180s

and

NBT receives
“MOD OK' and

NBT receives
*MOD OK' and

A OK'’

8 OK”

to ‘“‘PCM
renames

to “‘PCM
renames

Y
NBT receives
“AC LO"
“BUS LO"

deasserted from
the H7170s

A
C

SCLD-459

Figure 2-5

System Power-Up Flowchart

2-22

(Sheet 3 of 4)

NBT sends

“PCM

and B OK" as
well as “*‘AC LO"

ILM

A
ILM

merges

“PCM

and

B OK'

“MOD

““AC

LO’"

make

OK'',

also

becomes

“EMM5 AC LO MODL”
and ““BUS LO’'' becomes
“BUS

LO MODL”

ILM sends “MOD

J OKH', “EMMS

If MODJ OK is not

»|

received by EMM/con-

‘t‘BUEVILVIO MobL”

halted.

NOTE: this ‘‘handshake’’

‘.E_'\SNHUaTSDSOeV{,fi RTN MOD

is repeated for each

B L'

regulator.

and sends it

ILM,

ILM

enables

B
MOD
A
Regulator

B generates

“MOD

B OK H''

and

sends

ILM

EMM,

generates

ENABLE"”

“TOTAL
not

'‘BBU

providing

OFF"

asserted

y
EMM powers

up the
MPS regulators
in this sequence
C,

and

D
SCLD-460

Figure

2-5

System

Power-Up

Flowchart

2-23

(Sheet

SYSTEM

POWER-UP

The

main

the

front-end

FLOWCHART

circuit

(FIGURE

breaker

cabinet,

2-5)

(CB

1),

located

must

placed

the

rear

the

"ON"

position.
AC

distributed

printer),
to

the

L3)

J1/J2

unswitched
the

power,
the

via

876

the

Power

console

outlets

PRO-38N

console

the

and

(BRO-38N

power

phase

software

and

indicators

(L1,

L2,

Upon

selftest,

(this

LAS50

box,

Controller.

performs

and

outlet

takes

receipt
and

loads/runs

approximately

minute).

The
the

wunswitched
battery

(the

control

The

CSP

within
and

1is

the

need

After

MPS

+5
J4

(modular
to

the

CSP

J5
The

backplane,
each

power
1in

the

CSP

also

signal

The

box

bias

which

cabinet

the

position

(ON),

the

NBT

the

NBT,

BBU

the

indicate

BBU

also

(via

sends

information

J320

BBU).

BBU

ready

its

status

via

panel

The

the
of

sends

"batt

the

ILM.

MPS

"BBU

voltage

The

CSP

"FAIL

power

the

when

"ON"

enable

front-end

CBs

th e

the

SAFE

AVAIL

ILM.

1if

safe

CBs:

a
The

cir
cuit
N A

LLLCA A

above

J378

the

main
12

also

power

fail

the

voltage.

following

supply

the

are

sends

EMM),
in

the

NBT's
all

the

located

sent

and

CSP

to the
to J64
of

receives

the

reflected

the

point,

B/P.

H7170¢

front-end

(via

(turn-on)
MPS

NOM)

CBl.

this

(300-Vdc

(NBT)

the

J50

+10.5

the

876A

J20

voltage

BULK

also

monitors

J69).

circuits

minute,

ILM

CB),

the

front

CSP

powers

which

one

(ILM)

for

the

(main

the

used

translator

This

CBl1

to
J5

connector

module

The

filtered

circuit
breakers
vvvvvvvvvvvvvvv

cab

NBox

ILM/console.

than

distributes

input

resultant

circuitry,

ILM).

1is

and

from

the

charging

operative

connector,

logic

inserted

its

breaker

supply)

interface

which

position.

The

and +/- 12 V, which is distributed
CSP and J15, J9 connectors on NBox,

power

rectified,

new

not

distribute

and

module

NBox.

become

876

J22,

(CSP)

the

(H7231)

regulator

monitors

the

intervention/control

and
NBox.

connector

located

delay

generates
EMM
(via

(J17)

unit

start-up
BBU

outlets

backup

(4)

are

ENABLE"
NBox,

the

EMM

needed.

the

ILM,

which

displays

stat"

led,

which

The
this

located

When

the

ILM

performs

"OK",

the

When

front
the

state

panel

EMM

1is

"MOD

key

sense

detected,

LED

its

front

the

EMM

the
the

EMM

(via

connector,

INTLK

1ILM

J50

initialized

state.

perform

"default

H7188AB

ROM.

"IDLE"

can

now
to

this

both
and

console

the

EMM,

number/console

(i.e.,
MPS

and

this

VAX

are:

BULK

This

The

now

begins

the

Assuming

testing

console
this

command

Providing

there

power

initiated
and

sends

the

EMM,

the

ILM).

is
are

begins

when
this
J58

the

system

"MOD

from

begins

system

allows

the

air

mover

link

system

(RS232)

sending

1is

without

the

with
EMM's

system-specific

drawings

code
for

communications

the

EMM's

limits

are

specific

the

specific

line

code

loaded.

is
The

limits

code.

"POWER ON"

EMM,

system-specific

defaulted by the
until "MOD J ENABLE"

code

MPS

temperature,

the

J58

within

matches
AD

"MOD A

sends

EMM

bus

located

data

message.

set

11,

EMM

key

the

fault"

and

functioning

the

matched,

EMM

are

and

"key

ENABLE".

that

state

point,

the

tests.

deassertion

"OK"

Refer

and

The

system

and

the

overtemp,

the

INTLK

codes.

then

MPS

init

state,

incommunicado.

forced,

8750

If
no codes are
defaulted to an error

init

internal

the

communications

begin

establish

VAX

located

the

EMM).

code.

backplane).

matched,

10.

8800

connectors

tests

access

its

NBox

held

"MOD

faulting.
The

are

numeric

held

"CSP

"MOD

EMM).

tries

state,

the
power

illuminates

being

+/-12

8085

misplace)

tests

from

and
H.

EMM

mode"

These

with

EMM

flow
(which
is
ILM/NBT
to
the "LOW"
asserted

system

and

in the
element is

module

the

air
is

the

INIT

the

test

"0"

display

deasserts

ILM
of

this

number

deasserts

allows

powers

and

the

it
of

such

receives

the

Vv,

results

tests"

the

and

ILM

ENABLE",
to

+/-12

the

INLK

panel
in

deactivated,

When

(CPU

1is

and

ILM.

but

"hardware

fault
on

the

receives

awaiting

parallel

active,

performs

When

TILM
displays
the
element.
The numeric

circuitry
EMM

the

display
on

receives
selftest.

the

1initial

sent
no

MPS

power-up

the

faults

within

up.

asserts
the

2-25

situation,

(via
J9

detected

This

J50
of

the

operator.

"-SHUTDOWN

ILM

connector,

console

sequence

EMM

signal

the

sequence

RTN

MOD

connector

NBox,

L"
for
pin

12.

Wwhen
"PWR
and

13!

the ILM receives "-SHUTDOWN RTN MOD J L"
H" for the 876 (via J5 of the ILM,
ROST

to J4 of

CSP
RS,

sent

the

876).

power to the AIR FLOW
sensor
flow
air
sends
The AFS power
cabinet.
CPU
main
the
in
located
o~

via

J9 of the CSP,

(modular power supply)
MPS
of
outputs
the
releases

them

low "OK"

14.

it asserts
to J8 NBox

report

to J58 and J60 pin 5 of the

backplane connectors. The ILM
the air flow sensors to allow

a fault (until this time they were held

by pins 74,

42 of

the

ILM).

The CSP sends +5 V switched to the CLK/CNSL board (via J4
pin 14 the NBox connector), to Jb64
to Jl15
CSP
the
of
to J56 Pll, then to J59 pin 11, then to J65
then
(pl4)
P17. A cable then routes this to the CPU backplane.

15.

16.

The 876 completes its power-on sequencing and distributes
ac to the blower motor (via J13 of the 876, to the blower
to H7170Y (via J12 of the 876, to
Jl1),
connector
motor
connector for the H7170Y), and to H7170X (via
NBox
J380
J11 of the 876, to J382 NBox connector for the H7170X).
internal faults
no
have
H7170X
and
H7170Y
Providing
the "MOD OK" and "BUS OK" LEDs (located on
by
reflected
the front panel) being lit, each will begin producing 300
vdc.

17.

distributes
H7170Y
The
MPS
the
in
regulators

directly to the H7180
Vdc
300
backplane (via the 300-Volt
II

bus).
18.

distributes 300 Vvdc to the H7189, H7187, and
H7170X
The
in the MPS backplane (via the 300-Volt
regulators
H7186
distribution module has four
The
distribution module).
J100 through Ji03. Each connector interfaces
connectors,
to the 300-Volt bus. J100
component
system
power
some
H7170X; J101 interfaces to the H7189
the
to
interfaces
H7186
and
H7187
the
to
interfaces
J102
regulators.
J103 interfaces the BBU connector J9 to
and
regulators,
the

19.

distribution module.

H7170s send control signals to the EMM, via the new
Both
1logic module
interface
the
and
(NBT)
translator
box
(ILM). The H7170Y sends "MOD OK" H to the NBT (via Jl1 and
P320/3320
to
H7170Y
the
for
connectors
NBox
J381
connector for the NBT), which is renamed "PCM A OK" H.

2-26

20.

21.

H7170X

sends

"MOD

connectors

for

NBT),

which

Each

H7170

renamed

state
the

generate

H7170X

sends

deasserted
NBT.

OK"

the

"AC

the

input

"PCM

NBT

(via

P320/J320

NBox

backplane,

one

"PCM

the

The

NBT

sends

the

"AC

LO"

P320/3320
23.

The

"PCM

are

merged

becomes

and

L"TM

and

"BUS

connector
"AC

the

NBT,

and

"PCM

LO"

the

NBT,

OK"

"PCM

become

"EMM5

LO"

and

signals

the

OK"

"MOD

are

25.

The

ILM

sends

MODL

MPS

connector,

The

EMM
and

and

H",

"EMM5

26.

MOD

the

H".

"BUS

the

asserted,

ENABLE"

L",

and

condition,

directly

the

ILM

turns

sensing

Once

MOD

the

"BUS

LO"

well

ILM

(via

within

the

ILM,

signal

"AC

LO"

becomes

"BUS

L",

the

and

ILM,

MPS

(+5),

MOD

powered

the

RTN

asserts

ILM

MOD

"BUS

J58

B/P

MOD C,

MOD

(-2).

The

sensing

before

"ILM

EMM

power

MOD

and

MOD B

MOD

battery

asserts
enables

regulator,
the

"MOD

senses

the

the
the

OVERRIDE
turns

ILM

providing

which

combined

sends

SHUTDOWN

regulator.

regulator

for

modules.

PHASE

the

are

MODL
of

MOD
and

"-SHUTDOWN

+5-V

signal

the

signal.

the

LO
J9

has

regulator.
and

(-5),

directly

asserted,

with

ILM
B

then

array

the

OK"

for

the

The

LO"

regulator
E

the

EMM).

regulator

"MOD

and

sends

MOD

ILM,

the

that

the

each

asserts

Regulator

memory

Starting

EMM

and

When

powered

the

(via

each

regulator's

RTN

J50

(BIP),

that

each

First

27,

OK
EMM

sequence.

MOD

verifies

the

powers

particular
F,

"MOD
to

signals,

MODL".
24,

NBox

for

ILM).

MODL"

P320/3320

the

"BUS

J379

H".

signals.
22.

and

connector

"BBU

when

the

BBU.

EMM

signal

signal.

assert

verifies

signal

"MOD

OFF"

ENABLE"

the
OK

that

"TOTAL

EMM/ILM

2-27

"BBU

detects

from

H"
is

The

"BBU

REQ

is
not

RTN

The power

system power-down

flowchart

shown

in Figure

Console operator
issues “POWER DOWN"
command (asserts CPU
AC L,

ms wait,

asserts

CPU DC L,

then sequences
MPS regulators
D,E,H,F,C,B)

off

BEMM deasserts
“-SHUTDOWN RTN MCD
J L’ and sends to
ILM,

also

power

ILM

CLK/CNSL
removed

deasserts

“PWR RQST H'
and sends to 876

876 opens contactor
which removes AC

from the switched
outlets (BLOWER
and H7170s)

!
300

Vdc

Bus

begins

dissipating

voltage

v
H7170s

assert

‘‘AC

LO’" and after at
feast 5 ms ““BUS

LO”

(DC

LO)

MOD J OK H
is deasserted and
is sent to BMM

The

“*Q0’’

should

numeric

display

element

nlawy
piay

The CSP and
have power,

BEMM still
BVMM

waiting

for

CONSOLE command

SCLD-461

Figure

2-6

System

Power-Down

2-28

Flowchart

2-6.

CONSOLE

POWER-DOWN

The

console

This

asserts

the

operator

both

MPS

EMM

receives

power—-down

which
the

When

the
the

ILM

controller

(via

the

876

These

outlets

300-V
should

bus
By

this

least

"AC

LO",

case,

The

ILM

ILM,

"PWR
ac

H7170s

MOD

sent

the

H"
the

the

H7170s
signals

asserted

have

assert
are

CPU

and

should

display

which

"0"

from

indicates

CSP.

still

EMM

also

the

The

the

EMM

just

issued

it.

CSP

and

waiting

for

2-29

the

negated,

the

876

power

876).

opens

"AC

the

outlets.

and

voltage.

300-V

LO".

After

LO"

(DC

LO).

still

this

console

had

its

has

the

The

assertion

J",

motor

because

element,

the

CPU

the

MOD

from

"BUS

ignored

begins

J58

switched

asserted

(holdup)

All

(switched

negated,

blower

sequence

RTN

EMM,

from

will

milliseconds

the

RTN

ROST

and

power

removed.

which

the

removes

the

these

previously

H",

of
the

this

"-SHUTDOWN

J50

command.

CPU

command

Also

"-SHUTDOWN

DOWN"

later,

bus begins dissipating its
reach 0 volts in 5 minutes.

time

"POWER

disabled

(via

board

2-6)

DOWN"

ILM).

supply

H7170s.

The

ILM

receives

that

are

deasserting

RQST
J5

the

and

the

receives

"PWR

contactor

"POWER

the

CLK/CNSL

deasserts

When

(FIGURE

issues

the

sequence

sent

MPS,

CPU

regulators

b,E,H,C,B,J.

The

FLOWCHART

numeric

and

have

console

display

+/-

power,

and

command

Figure

2-7

1is

flow

of the signal events that occur

diagram

during short-term power interruptions.

H7170s or CSP assert
““AC LO L'’ and send

NBT monitors all
major AC circuit

to ILM

breakers

An open C/B will

ILM receives ‘‘AC

cause ‘‘FAIL SAFE
EN’’ de-assertion and

LO L'’ and asserts
“EMM5 AC LO MODL L'’

BBU AVAILABLE

EMM

BBU will deassert

which is sent to

BEMM receives

’

“EMMS5S

AC LO MODL L’ .WRéCh

generates ‘‘CPU
- and ‘e ‘‘SBIA
1O L
AC LO H’’ which are
sent to the CPU(s)
and VAXBI B/Ps

CPU now has 5 ms

fo
perform
foutine

power-fail

As a result of

‘*AC

BEMM asserts

the

“BBU

REQ RTN L’

and sends to

The ILM

ILM

the

receives

“BBU REQ RTN L'’ and
asserts ‘‘ILM BBU

REQ RTN L'’ and
“PHASE OVERRIDE A L
which are sent to the
BBU, unless circuit
breaker

trips
:

The BBU receives ‘‘ILM
BB REQ RTN L'’ and
asserts “MODULE
ENABLE L'’ which
sent to the EMM

The EMM receives

“MODULE ENABLE L’
and shuts down all
of the regulators
(except MOD B)
A

ILM keeps MOD B
regulator functioning
SCLD-462

Figure 2-7

Powerdown/Power Interrupt with BBU Flowchart
iv

2-30

POWER-DOWN/POWER

(FIGURE
The

VAX

8800

monitors
The

the

four

backup

main

breaker

(CBl)

H7170s.

the
any

backup

assertion

Either

module

can

sent

1is

connector

H7170s

1ILM

environmental
ILM,

The

EMM

"CPU

the

"EMM5

between

the

EMM

RTN

L",
MPS

UNIT.

which

{(EMM)
of

MODL

L",

J50

VAXBI

(via

J50

(via

(CSP)

asserted,

(via

NBT

asserted,

the

and

which

"AC

backplane

the

EMM).
generates

signals

the

are

sent

EMM,

J65

MPS

LO"

signal

and

the

VAXBI

that

"EMM5

MODL

process

was

that

defined

the

This

connector,

the

(ILM)

sends

These

CPU(s)

the

H".

The

the

power
is

the

trip,

due

module

recognized
began

BACKUP

J58

the

and

backplane

connector).

asserted,

REQ

J58,

SBIA AC

should

main

for

ILM).

"AC

module

connector

and

backplane.

"BBU

that

receives

the

MODL

CPU(s)

jumpered

EMM,

logic

monitoring

MPS

backplane

BATTERY

breakers

start-up

(CB1)

the

L".

"AC

that

system.

breaker

operate,

Once

interface
to

the

control

L".

circuit

cabinet,

breakers

not

backup

main

above

recognizes

"EMM5

the

P320/J320,

the

and

the

876,

ENARLE

"AC

front-end

will

SAFE

FLOWCHART

contains

are:

the

unit

assert

the

"FAIL

the

asserts

When

BBU

breakers

breakers
rear

for

battery

WITH

translator

circuit

located

When

INTERRUPT

2-7)

sent
to

2-31

accomplished

to
J5

the
of

ILM

the

(via

ILM).

asserting

J50

the

When

the

signals

Mod

ILM

"BBU REQ RTN L",

receives

it asserts two

("ILM BBU REQ RTN LL" and "PHASE OVERRIDE A L")

J is requested,

and Mod B

"OK".

These signals are

the BBU (via J5 of the ILM, to J18 of the BBU).
to
sent
A L" disables an internal ac monitoring
OVERRIDE
"PHASE
BBU, which allows any BBU request to be
the
in
circuit

taken control of MOD J EN,
also
has
ILM
The
honored.
power outage,
the
throughout
enabled
keeps
it
which
return

awaiting

ac.

any of the major ac circuit breakers should trip, the
If
deasserts "FAIL SAFE ENABLE L", which causes the BBU
NBT
inhibits the BBU from
and
L"
AVAIL
"BBU
deassert
to
recognizing any request for battery backup operation.

time, the ILM has a circuit that monitors: "BBU
this
At
RTN L" from the EMM, "BUS LO L" from the H7170s, and
REQ
"BUFFERED

CSP BULK OK L"

from the

control

start-up power

(CSP) module. When any of these signals are asserted, the
of MOD B regulator, by the EMM, is taken over by
control
the

ILM

(see

note).

BBU receives "ILM BBU REQ RTN L" and asserts "MODULE
The
L", which is sent to the ILM, which then gates it
ENABLE
LO L or H7170's MOD OK deassertion. It then sends
AC
by
to the EMM (via J18 of the BBU, to J58 of
ENABLE"
"MODULE

MPS,
the
supplying

J103 of

also begins
BBU
The
EMM).
the
of
J50
to
the BBU to
of
J9
(via
bus
300-V
the
to
vdc
300

the 300-V distribution module).

is
L"
ENABLE
"MODULE
that
recognizes
EMM
the
When
MPS
the
of
all
down
shut
to
begins
it
asserted,
regulators, except MOD B. This is done by deasserting all
MMOD X L" signals. This shutdown
"-SHUTDOWN.RTN
the
of
of MODULE ENABLE L. These
assertion
of
6ms
within
occurs
to each regulator plugged
interfaced
are
signals
shutdown
into

the

MPS

backplane.

2-32

The

ILM

and

does

MOD

Vdc

the

memory

the

loss

recognizes
so

the

need

the

BBU,

now

turning

MOD

regulator

keep

NOTE

the

CSP would

able
V.

for

MOD

the

Overtemp

only

ILM

the

and

the

MOD

ILM,

H7170s

with

CsPp,

not

and

+/-12

on
+5

Vdc

uses

(MOD

MOD

signals).

the

are
NBT,

lose

and

ILM

for

working

remains
ILM

and

+/-12

regulator,

the

and

and ILM. This means
regulator provides +5 V

components

still

down

EMM

generate

affected

power

provide

the

that

system

the:

MOD

and

BBU.

phase,

provides

The

power

the

and

+/-12

2-33

the

CSP

EMM

and

vdc.

regulator

provides

cperating

arrays).

MOD

which

300

(providing

on
vdc
+5

a
is
2-8
Figure
operation sequence.

flowchart

the

from the

power—-up

MOD B regulator

supplying +5 Vdc
to Memory Arrays

v
to

AC restored
system

CSP powers

Y
ILM

deasserts

“MOD A INTLK L’
and sends to BEMM

Refer to System
Power Up Flow,
Steps 8 — 25

h 4
ILM

receives

“MOD 4 OK HTM
and “-SHUTDOWN
RTN MOD B L'

“PHASE
OVERRIDE B L

ILM

asserts

and sends to

BBU

SCLD-463

}

BBU

from

Powerup

TMo

2-8

Figure

Opera CLi0n

owchart

BBU

POWERUP

FROM

BBU

FLOWCHART

MOD

regulator

the

system's

memory

arrays.

1is

restored

system and
the signal

up.

The

CSP

and

sends

under

(FIGURE

the

generates

the

BBU

ILM

2-8)

control

(via

and

providing

the CSP begins to power
"DELAYED CSP BULK OK H"
of

the

CSP,

ILM).
The

ILM

deasserts

sequence

command
steps
The

the

same

1is

executed.

through

ILM

(via

"MOD

1is

receives

RTN

connector,

result

MOD

asserts

receives

"PHASE

Volts

and

the

connector,

MPS

J58

(via

(Refer

"MOD

"-SHUTDOWN

BBU

A
INTLK
L"
and the power-up
console powerup. The "POWER ON"

NBT

ILM

the

system power-up

flow,

25.)

P320/3320

the

Vdc

put

"MOD

from

to
J

"PHASE

the

ILM,
the

the
of

and

J18
B

charge

2-35

the

to
EMM

the

OVERRIDE

OVERRIDE
in

from

H7170s

J5
(via

L",

the

NBT

ILM) and
the EMM,

ILM).

"-SHUTDOWN

B
of

via

of the
J50 of

L",

L" and sends it to
the BBU). When the

the
BBU

300

mode.

stops

RTN

MOD

supplying

CHAPTER
DETAILED

3.1

INTRODUCTION

This

chapter

described
the

focuses

briefly

importance
Among

those

the

components

system,

described

controller

NBOX

power

converter

Power

supply

Buses

and

EMM module

BBU

Air

BLOCK
detailed

3-1,

and

interconnections.

The

876A

following

system

that

were

but,

because

their

require
in

additional

this

chapter

information.
are:

cooling

THE

diagram

the

power

backplanes

identifies

operating

the

regulators

DIAGRAM

block

chapters,

power

flow

parts

preceding

876A

Figure

the

on
the

3.2
A

DESCRIPTION

the

controller,

modules

VAX

the

key

which

8800

POWER

VAX

8800

components

interfaces

the

power

3-1

paragraphs.

SYSTEM
power

the

system,

power

utility

system,

1is

shown

system

input

power

discussed

and

the

CPU CAB.

FRONT END CAB.

BLOWER
)

/1 PHASE

EXPANDER

UNIT BA11-A

LOGIC

BACKPLANES —\

BBU

H7230

e e _|

BATT

PACK

H7240

/3B AC

BLOCK

19,
’

TRANSFORMER

| BLOCK

pOLE

RELAY

—

V
300

NBOX

BUSES

"""| 300 v DC #1
i
>

H7 170X

—Fac

H7170Y

csp

(

NBT

[
!

NBOX BP

POWER
CONTROL

7338 AcC
|77,
}
735 AC

DISTRIB.

| 50 HZ

RECEPT.

876A |

DRANETZ

by
—
W =

‘

3¢

}#1

300 V DC

]

[

I 300 v DC

[

H7189

H7180 H

EMM

Heti
[

{
I
L

CPU

H7187 |

SPARE [

+12V, -45 V

10 AC

H7187 1

| vAXBI

H7180 H

H7186 |

+10.5

MEM

H7186 |-

H7189 | | VAXEI
1

| 42

MPS BACKPLANES —/

JBOX

CONSOLE
RECEPTACLES

o [ 111}

3¢

—

CONSOLE

OPTIONAL

30PAC

UTILITY POWER

PRINTER

MKV86-1252

Figure 3-1

Power System Block Diagram

3.3

876A

The

876A

circuit
to

the

POWER CONTROLLER

receives

Dbreaker,
system

and

wutility

components,

Table

power

distributes
as

3-1

shown

876A AC

from

switched
in

Table

Power

60/50

BRKR1,

and

l-phase,

unswitched

l-phase,

unswitched

3-phase,

switched

(NBox)

3-phase,

switched

(expander)

l-phase,

switched

l-phase,

switched

Blower

motor

H7170X&Y

BAl1l-A
Aux.

port

distributed

located
with
system

Figure

the
is

the

designated

the

power

3-2

shows

the

system

components

876A.

The

receptacles

locations.

the

circuit

front

power

Supplied

system

and

breakers,

rear

using

panels

lamps,

receptacles

components

receive

energized.

illustrating
their

rear

system

Hz,

BBU

(NBox)

Distribution

120/240

module

main

3-1.

Component

CSP

the

unswitched

and

power

are

mated

when

the

of
the
876A,
receptacles and

DEC POWER

DELAYED

TOTAL

CONTROL BUS
AL

ouT

OFF

I 1/_/%

F= @ o E
Ja

REAR VIEW

J10

J12

J13

®
2

TM\

D EG

o
o)

O
7,

J18

®
o

;—‘—

UNSWITCHED
—/
FRONT VIEW

DIGITAL 876A

POWER CONTROL

L1 © OF1®

® __

12 ©® OF2

dlelHd

CB1

CBZ

AC INPUT

CB3

}

[RL-A-2]

CB4
MKV86-1221

Figure

3-2

876A Front
Iv

3-4

and Rear Panels

L_“T—__—'
J17

N BOX
——-—-

——

"1
CB2

CB1 (BRKR2)

UTILITY

POWER

3/
J18

RFI
FILTER

120/208 V

X FORMER

JFILTER

—

3,412

H7170X

—

| 7170y
N %Li]l-Il_

/RELAY

—_—————

CIRCUIT

AC 50/60 H2

|
—
ILM

CB4

A / JRECTIFICATION |— | SURGE
PROTECT

NBT

F—————

30A

G-¢

“T1

PLC

}@) }@ ::§>

SELECT

OUTLETS

POWER LAMPS

SW.
(S1)

;

J15

J16
CB3

TOTAL OFF

OUTLETS

J8 & J9

OUTLETS

POWER
CONTROL BUS

J13

J1, J2, J4, U6

OUTLETS

r~—"""7

DELAY

OUTPUT

J3&J7

BLOWER

MKV86-1253

Figure

3-3

876A

Power

Controller

Block

Diagram

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ST

A
I
BBU
l+—— CONTROL

Referring

immediately
enclosure.

CB1(BRKR2),

The

three-phase

RFI

filter

applied

to:

lamps,

wutility

wupon

power

entering

the

1is
876A

L1-L3

876A main

single-phase

circuit

power

breaker

routed

the

BBU-CSP

branch

a single-phase circuit breaker (CB2). Three-phase power
to the transformer/filter/rectification/relay circuits.

output

power

then

indicator

CBl,

through
applied

The

3-3,

From

ac.

Figure
sent

this

section

controlled

the

876A

referred

the

power

control

bus

and

power

through

Sl1,

switched

three

pole

relay.

switched

three-phase

sent

surge

protectors

to:

CB3

)

CB4

3.4

The

for

NBOX

NBex

functions
1.

1is

3-phase

blower

l1-phase

BAll

l-phase

aux.

3-phase

H7170

POWER

port

power

VAX

Converts

(2)

located

NBox

CONVERTER ASSEMBLY

multifunction

the

converter

8800

assembly

power

three-phase

distribution

the

that

performs

the

following

system:
ac

MPS

input

power

regulators

300

means

Vdc

for

the

300-V

logic

level

Bus.

Converts

single-phase

voltages

for

the

ILM

1input

and

power

EMM

modules

and

the

MPS

regulators.
3.

Controls

the

Communicates
sequencing

Distributes
the

300-vdc

operation
with

and

the

battery

300-Vdc

the

EMM

during

backup

power

battery

Monitors

circuit

Monitors

breaker

and

power—-up

unit

(BBU).

and

power-down

and

the

operations.

from

the

buses.

backup

status.
signals.

H7170s

BBU

N BOX

J17

|
3@ UTILITY
POWER

H7170X

H7170Y

I
l

-1

POV
§
|

igac

+10 5V

+5V

NBT

I
|

MPS

300 VD

MOD H
H7189

v¥

CcsP

300 V

MOD.

D¢

PWR

pist.

300 VvV BUS

]

| ]

2 AC

ILM

I
I

L=€

300 V BUS

VAX BI

MOD F
H7189
OPTIONAL

MOD E
H7180

876A

J11

]

J12

]

GND

OPTIONAL -5.2V

MOD E
H7180

GND
-5.2V

EMM

MOD D
H7187
OPTIONAL

MOD D
H7187

CPU
LOGIC

GND
DD

SEpN—

300 vV BUS

SPARE

MOD C
H7186
MEMORY
MOD B
H7186

&v:lJ
MKV86-1251

Figure

3-4

NBox

System

Interconnect

*y-¢ 2anbig ul umoys ST

300 V

SUOT3O9UUODILUT Wwe3sAs Y3Tm XOgN oYyl Jo weiabelp 320Tq pellieisp

« FROM H7231M

3.4.1
The

NBox

Modules

function

contained

the

description

functions

NBox
each

performed

are

listed

module

1is

each

Table

presented

the

modules

3-2.

detailed

the

following

paragraphs.

Table
Module
H7170

3-2

NBox

Modules

Function(s)
(2)

Convert

CSP

3-phase

Converts

(+5

ILM

1l-phase

+/-

300

power

for

modules),

(+15

Provides

interface

Controls
NBT

operation

Converts

logic

circuit

breaker

EMM

for

vdc
to

and

logic

MPS

logic

ILM),

CLK/CNTL

for

regulators.
level

10.5

voltages

for

MPS

module).

between

MPS

and

EMM.

BBU.

signals

during

status.

powerup.

Monitors

and

signals.

3.4.1.1

H7170

located

1in

converting
300-V

and

H7170Y,

The

bus

300-V

There
NBox

three-phase

The
power

the

unregulated
are

located

output

are

that

input
dc

from

H7170

the

to
MPS

the

power

identical

power

output

connected
within

two

perform

from

conversion
functions,

300-Vdc
the

separate

two

modules
that

converters,

sections

300-vdc

the

NBox

the

cage.

BBU

1is

00}

H7170X

the

brought

into

interface with the outputs of the H7170s and be distributed
300-V power bus during battery backup operation.

is,

power.

3.4.2
The

CSP
control

input

start-up

power

indicated

power

logic

Table

3-3,

Table
DC

Logic

+/=12
+5

Voltage

3-3

ILM

assembly

functions

module

The
that

CSP

ILM

EMM,

ILM

the

interface
provides

following

for

single-phase

use

(ILM)

the

modules

Voltages
Supplied

Regulators

logic

power

converts

voltages

EMM,

MPS

3.4.2.1
board

Modules

VvV

+10.5

(CSP)

level

module

signal

interfacing

single

and

system modules:

control

CSP
EMM
BBU

H7170

drive

1ILM

the

and

clock

Module

NBT

The

System

module

also

contains

front-panel

BITE

(built

indicators

test

described

3-9

equipment)

Chapter

circuits

Figure 3-5 shows the PC board connector for the ILM module and the

signals

that

interface

to the

ILM.

ILM. J5

BAT STAT

RIN |

84 e

83 o

@ OVERRIDE A

@ OVERRIDE B

BBU ENABLE | | __

BBUENABLERTN |

., | MOD A SHUTDOWN

MOD ENABLE RTN | | o5
MOD ENABLE FEED | _ o
ILM BBURQST | , .

ILM BBU ROST RTN | |
BBU AVAIL |

BBU AVAILRTN |
MSTR CLOCK IN
; 56
MSTR CLOCKRTN |
ACLO
* 93
BRKR TRIP | | o

PCM OK (H7170X) ¥

| . 3?
* 4
43

PCM OK (H7 170Y)

EMM4MOD J OK H

a0 =
46 o]

MOD B +5 V (+5 VB)

44 e

EMMS5 AC LO OUT

91 e}

BUSLO

PWR REQUEST | _ -,
48

PWR REQUEST RTN |

—- 66

H7170BUSLO |

EMM TOT OFF RTN
50 ®

EMM BBU REQST RTN L

6, o|
o

IM-12V.

£g |

CSPO.T. H

§7 o}

CSPO.T RTN

60 o

CSP+5 V

Jg o]

FAN/AFS PWR

&9 o

CSP BULK OK

g9 o]

MOD B OT

AINTERLOCK LO

;’é ~_ | EMM MOD B SHUTDOWN L
g5 o] LM MOD B SHUTDOWN SOURCE
ILM MOD B SHUTDOWN RTN L

23 . 1 MODBOKH
90 e}

712V POWER

89 o_|

MAN. INTERVENTION H

99 o_|

MAN. INTERVENTION L

CSP +5 V RTN

62 o

MKV86-1226

Figure

3-5

1ILM
I

Board

3-10

Signals

The

ILM

receives

from

the

CSP module,

the

ILM

three

receives

signals,

DELAYED

°®

CSP

POWER

resulting

with

system

When

RESET

output,

=
N

ILM

asserts

POWER

receipt

HIGH,

which

INTERLOCK

up,

causes

activated:

LO,

allowing

sent

the

EMM

to
to

POWER
ON command from
L, causing the ILM to

power
power

relay,
is

operation

the

able

Module

or
The

ILM

respond

BULK

RESET

not

has

PCM

not

PCM

the

EMM

communicate

Kl,

located

delivered

the

the console,
assert power
in

the

power

876A.
system

and

asserts

request

power.

asserted.

PCM

from

MOD

battery

operating

power

has

dropped

MOD

ILM
a

BBU

TOTAL

OFF

MOD

the

H7170

indicate

power
proper

not

(MOD

156

RETURN

signal

power

rms

if:

asserted),

(DELAYED

CSP

and

BULK

the

BBU

does

not

asserted)

ENABLE

signal
is

backup

properly
below

not

REQUEST

request

H7170s.

asserted.

occurred.
A

ILM

asserts
a

ENA

CSP

of
the

energized,

Timeout

respond

SENSE

sequence

provided:

ILM

ILM,

1is

converters,

The

powering

KEY

power-up

console.

BUFFERED

Upon

After

and

microprocessor,

the

The

energizes

the

Chapter

which

components

V during

HIGH

the

The
EMM,
upon
receiving
asserts
SHUTDOWN
RTN
MOD
request,

8085

+/-

BULK

ILM

the

and

explained

BULK

INTERLOCK

release

the

internal

The

(PIN

75)

from

the

ILM.

if:

asserted,

asserted

3-11

enable

The

BBU

BATT

STAT

indicate
the

[LM

three-state

battery
(H7061).

status.
1he

signal

The

three

LED

sent
1s

the

located

indications

ILM

from

the

front

BBU

panel

are:

OFF

current

signal.

BBU

not

available.

READY

Continuous
current
flow
or
available and batteries fully

Oscillating

current

"slowly."

BBU

charged.

Charging

flow

available
in

signal.
charged.
1

but

LED

Hz.

"ON."

LED

batteries

BBU

blinking
not

fully

process.

Oscillating
"fast."

Phase

Override

This

signal

located

responds

BBU

current
is

flow

and

used

override

the

BBU

when

wusing

BBUR

signal

providing

the
a

from

Hz.

level

detect

three-phase

the

ILM

LED

blinking

power.

gated

circuitry

system.
by

the

The

BBU

following

signals:
®

PHASE

OVERRIDE

Assures

that

the

BBU

will

turn

on.

PHASFE

OVERRIDE

=--

Assures

that

the

BRBU

will

turn

off.

Control

System

power

requested

request
1ssueG
Dby the
MOD J SHUTDOWN RTN L to

ILM

responds
REgihsT

activace

hhe

cateed

relay
to

FEMM

xolay

withiin

the

1in

876A.

876A

and

system.

response

response,

contacts.

the

closing

RTN).

POWER

the

The

system console.
the ILM.

Power

Tne

K1,

(POWER

POWER

provide

the

power

EMM

sends

REQUEST

swiiched

and

sighnals

power

syscen

The

CLOCK

syster

mazns

oio

syncnronizes
e3>

Bit=
The

tax

built

reseft

test

after

C5P

MANUAL

MOD

CLOCK

modulzted

witain

RTN.

The

power

the

ILM

master

regulators

clock

the

been

when

contains

following:
FAILURE

CLOCK

H7170X,

MANUAL

H7170Y

The

ILM

that

has

been

front

continue

to
automatically

indicators

condition

module

corrected.

seven-segment

MOD

ILM

(PLMA,

LED

digital

display

that

power

input

OK)

RESET

located

the

H7170s

This

sent

the

BUS

Bias

Indications

starts

NBox

signal

CPU

This

signal

deteriorate.

indicates

within

acceptable

the
The

the
is

that

ILM

when

signals

performs

via

signal

signal
down

the

)

removed.

fault

indicators

are:

the

H7170s

located

(overtemperature)

also

Status

(BITE)

latching

INTERVENTION

Power

the

are:

power-fail

routine,

and

the

The

EMM,

sent

the

system

parameters,

CPU

via

voltages

and

the

are

EMM.

longer

system must

1immediately.

shut

Circuit

(+12

bias
'V

voltages

POWER,

operation.

The

Zinerated

MSTR

width

has

faults

ILM

The

31i77a0

ans

equipment

power

powerup

indicates

pales

magnetically

monitcored

The

the

syscedn.

are

display

The

Liid=kidr

ZLTC0«

Indicators

panel

Tne

METH

During

develop
+12

ILM

provide

the

gignal

during

for
-12

ILM
V

battery

the

bias

from

the

source

and

logic

are

CSP

backup,

derived

from

and/or

MOD

fed

from

the
B

CSP

inputs

during

normal

Mod

(MOD

BIAS

voltages.
CSP

voltage

wire-ORed
tor

the

powerup.
IV

3-13

with

the

ILM

MOD

+12

SHUTDOWN

SOURCE

3.4.2.2

NBT

Module

convert

operating

system

signals

The

New

signals

functions

that

are

Box

during

required

translated

Input

Translator
the

H7170

MOD

H7170

BUS

TOT

OFF

for

together
NBT

both
when
It

the

also

the

Figure

3-6

and

the

module

the

+5
PC

sends

above
out

provided

V during

powerup.

BBU

CSP

operation.

during

Both

normal

supplies

are

board.

circuit

and

sends

response

out

MOD

monitors

H7170s
any

NBT

and

breaker
out

breakers
TOT

OFF

BRKR TRIP

board

status

signal
are

command

signal

(BRKRs

[FAIL

SAFE

and

ENABLE

and

CBl

(FSE

FEED)]

power

system

tripped.
to

from

connector

shut

the

diagram

NBT.

Power

TRIP

operation

The

used

ORed

perform

BRKR

after

Output

BUS

and

module

sequence

are:

MOD

(NBT)

power-up

during

The

logic

[

down

the

ILM.
showing

the

signals

MAIN CB SENSE

FSE FEED |

876 CB SENSE
FSE RTN

[]

[

BUS LO (OUT)

CSP BULK

OKRTN

TOT OFF RTN

TOT OFF

[]

ACLO

[ J

MOD OK X

[]

csp 45V | °

¥ MOD OK Y

— 37

H7170Y OK | °

ACLO IN

AC LO RTN

H7170X OK |~ °°

. 45

BUS LO (IN)

BUS LO RTN

® 49

MOD B +5 V

NOTE: PINS 5-10 REMOVED
MKV86-1224

Figure

3-6

NBT
IV

Board

3-15

Signals

3.4.3
-

System

The

modular

Modular

power

supplies

are

pulse

width

modulated

regulators
VAX

8800

Figure
a
the

3-7

is
VAX

not

asterisk

the

MPS
the

VAX

(PWM)

locgic

8800

voltages

power

system

complex

regulators.

necessary

operate

The
the

system.

front
8800

backplanes

Regulators

provide

computer

dual-CPU
MPS

Power

are

used

view

system.

The

described
a

fully
in

the

single-CPU

(*).

configured

regulators,

3-16

VAX

their

following
8800

MPS

assembly

for

indicators,

and

paragraphs.

system

are

indicated

MOD C | MOD B

MODD | MODD | EMM

MOD E

H7187 | H7187 | H7188

H7180

1
MOD E

MOD F

MOD H

LT-¢t

SPARE

H7186 | H7186

H7180

H7189

MPS BACKPLANE # 2

MPS BACKPLANE # 1
MKV86-1220

Figure

3-7

MPS

Regulator

Configuration

The dc logic voltages supplied by the MPS are listed in Table 3-4.
Table

3-4

VAX 8800

MPS Regulators

(DC)

Quantity

Regulator

Volts

1
1
l
1l

B
C
D
E

+5 V
+5 vV
-2V
-5.2 V

1
1

or
or

2
2

F
H

3.4.3.1

H7186

(H7186)
(H7186)
(H7187)
(H7180)

(H7189)
(H7189)

+5.0-Volt

v,
v,

+/-12 Vv,
+/-12 V,

Regulator

The

modules
B
and
C, generate an output of
provide power to the CPU memory modules.

provide

block

diagram of

power

Vdc

H7186
at

-2V,

+15V

-2V,

+15 V

regulators,
tec

the H7186.

the memory modules

when ac facility power is

3-8

used

backup operation,

00]

Figure

also

1is

battery

(U9

during

Module

-5.2 Vv,
-5.2V,

lost.

SIDE

PANEL

ASSY

+5.0 BUS
)

{

T
2

OUTPUT

[Mscr

RECTIFIER

OUTPUT

TERMINALS

]

+5.0 RET

OUTPUT

FILTER

OVER \5“

BOARD

TEMP

SWITCH

781

1
2 654

300

vDC

INPUT —

‘{/\F;JS

61-¢€

PULSE

OVER

WIDTH
MODULATOR
CIRCUIT

» LEDS

VOLTAG
+ CURRENT
E
AND MODULE OK
—
~ TO
CIRCUITS
SE——)

ISOLATION

CIRCUIT

REFERENCE

CONTROL
CiRCUIT

|—»

LEDS

AND
MARGINING
CIRCUITS

YELLOW (OVER CURRENT)

REMOVE SENSE

RED (OVER VOLTAGE)

CIRCUITS

GREEN (MODULE OK)

AND

CURRENT SHARE

50 PIN

BACKPLANE
CONNECTION

—

—-J
—

10
J1

MAINBOARD
MKV86-1250

Figure

3-8

H7186

Block

Diagram

The H7186 is made up of two major subassemblies:
1.
2.

3.4.3.2

Side Panel
Main Board

Side

Panel

The

functions and interconnects for the

H7186 side-panel assembly are defined in Table 3-5.
Table 3-5

H7186 Side-Panel Components and Interconnects

Component/Interconnect

Description/Function

Connects

Power

Overtemperature Switch

Senses temperature on output rectifier

filter board to main

output

board.

transformer

isolates

the dc

steps

input voltage.

down and

heatsink.

Indicates overtemperature condition at
100 degrees C (212 degrees F)
Generates

SCR (Silicon Rectifier)

shutdown signal

to EMM,

Overvoltage protection device.

3-20

3.4.3.3
and

H7186

Main

interconnects

Table

3-6

Board

the

H7186

main

Main

The

functions

board

Board

are

Circuits

and

Description/Function

Connects

J?2

signals

MPS

the

logic

Table

circuits

3-6.

from

the

main

board

backplane.

Connects

Interconnects

Circuit/Interconnect

the

defined

overtemperature

main

Connects

switch

and

board.

output

300-Vdc

the

input

main
to

board.
the

main

board.
Connec ts
+Nn

and

5-A

outpu

NeAntan
ANS
te t}

¥ )=1

1 S olation

circuits

nsforme r

L L CA1io

yv il

600-V

o) f

(—r

fuses

used

for

input

overload

protection.
Isolation

Circuit

Isolates

high

voltages

the

main

board.

Pulse
and

Width

Control

Modulator

Provides

Circuit

variable

input
Overvoltage

Circuit

stable
pulse

voltage

Crowbar

and

output
red

output

using

compensate

for

fluctuations.

circuit

designed

voltage.

LED

for

(7.3

Overvoltage

load

protection

disable
Lights

voltage

width

overvoltage.
Vdc

max.

6.3

Vdc

min.).
Disables

Blinks

output

vyellow

IRY)

I.__l

overcurrent.

Circuit

Overcurrent

voltage.

LED

on/off

signal

H7186 Main Board Circuits and Interconnects (Cont)

Table 3-6

Circuit/Interconnect

Description/Function

Ref Voltage and Margin

Provides 1 of 3 jumper selected voltage

Circuit

outputs.

+/-5%

selected can be margined

Output

the

through

EMM.

Module OK Circuit

Lights green LED to signal MOD OK.

Remote Sense Circuit

Enables

Current Sharing Circuit

Allows

remote

sensing

output voltage at

1load

load.

sharing

current when

cross—connected with another H7186.

H7187 -2.0-Volt Regulator

3.4.4

regulator, Module D, provides an output of -2.0 Vdc at
The H7187
The output is connected by bus bar straps to the CPU
A.
100
to
up
area.

backplane

The block diagram for the H7187 is identical to that shown for the
H7186

in Figure 3-8 due to the similarity of components.

The mechanical configuration of the H7187 is virtually identical
wup of two
1is made
It
the H7186 with minor exceptions.
to
subassemblies,

The

components,

are described

‘

the side panel and the main board.

c¢ircuits, and interconnects for each subassembl

in Tables

3-5

and 3-6.

Two module D regulators are used in the dual-CPU configuration.
3.4.5

H7180

-5.2-Volt Regulator

Backplane 1,
MPS
in
located
E,
module
regulator,
H7180
The
bar straps
Bus
A.
200
to
up
at
Vdc,
=5.2
of
output
an
provides
area.
backplane
CPU
the
to
E
MOD
connect the dc voltage from
Figure 3-9

Two

is a block diagram of

module

regulators

are

the H7180.

used

the

dual-CPU

system

configuration.

H7180 consists of two major subassemblies, the side panel and
The
The components, circuits, and
board.
circuit
printed
main
the
discussed in the following
are
subassembly
each
on
interconnects
paragraphs.

SIDE

PANEL

ASSY

)

e|
3

OUTPUT

—{

5.2 BUS

{

[ 5Cfl

RECTIFIER

OUTPUT

TERMINALS

4
3

vDC

INPUT —

—

OVER
TEMP
(4

PG
+

{

—

SWITCH

300

-5.2 RET

]

—

1379

£C-t

Ja
(TO J6)

ISOLATION

CIRCUIT

PULSE

OVER

L~ LEDS

MODULATOR
CIRCUIT

AND MODULE OK
CIRCUITS

10
—— J6

WIDTH

VOLTAGE + CURRENT

50 PIN
J6

PWM

REFERENCE

CONNECTOR

VOLTAGE

—

MARGINING
CIRCUITS

O YELLOW (OVER CURRENT)

REMOTE SENSE

f—

CURRENT SHARE
RS

S J6

CONTROL

CIRCUIT

AND

BACKPLANE

LEDS

]

RED (OVER VOLTAGE)

O GREEN (MODULE OK)
PRINTED

CIRCUIT

BOARD
MKV86-1249

Figure

3-9

H7180

Block

Diagram

3.4,5.1
H7180
Side Panel -The functions of the components and
interconnects on the side panel assembly are defined in Table 3-7.
Table

3-7

H7180

Side

Panel Components

and

Component/Interconnect

Description/Function

Connects

P7/37

Connects
crowbar
return terminal to

Transformer'1 and

Power
and

S —-—-

300 vVdc

the

used

input

Switch/Sensor

regulator.

SCR and power
PC board.

transformers

isolate

to step down

mounted

(Silicon Rectifier)

shutdown

Overvoltage
the

power

signal

protection

output

voltage.

rectifier
heatsink
to
overtemperature
condition
212 deg. F).
Generates

SCR

Interconnects

output

indicate
(100 deg. C

EMM.

device used at

terminals

3.4.5.2
H7180
Main
PC
Board
-The
functions
of
the logic
circuits and interconnects on the H7180 main printed circuit board
are

defined

Table

3-8

3-8.

H7180 Main PCB Circuits

and

Interconnects

Circuit/Interconnect

Description/Function

Connects

300

Connects
step-down

Vvdc

to PC

board.

isolation
«circuits
to
transformers
and

the
PWM

circuitry.

Connects

overtemperature

switch

to PC

board.

Connector

and

that

interfaces

terminal

and

Connects

board

Input
600-V

overload
type.

3-24

power output

board.

to MPS

backplane.

protection

fuses,

10-A

Table

3-8

H7180

Main

PCB

Circuits

and

Interconnects

Circuit/Interconnect

Description/Function

Isolation

Isolates

Pulse

Circuit

Width

Modulator

high

voltages

from

(Cont)

board.

Provides

variable

pulse

width

control

(PWM)

for

input

voltage

and

circuit

designed

stable

compensate

output

voltage

using

load

fluctuations.
Overvoltage

Circuit

SCR

Crowbar

disable

Lights

red

protection

the

output

LED

Overvoltage

Vdc
Overcurrent

Circuit

voltage.

output

condition

fault.

(7.0

vVdc

Disables
Blinks

output

Ref

Voltage

and

Margin

Module

yellow

Remote

Connects

using

Circuit

Sense

Circuit

LED

on/off

Sharing

Circuit

one

three

output

Verifies

fault-free

Lights

green

Enables

Allows

voltage

outputs

margined

+/-5%.

status.

LED.

output

voltage

sensing

load.

sharing

cross—-connected

common

overcurrent

jumpers.

Selected

remote

Current

6.0

voltage.

condition.

Circuit

max.

min.).

load.

3-25

of
with

1load

current

another

when

H7186

3.4.6

The

H7189 BIP Regulator

H7189

module

(VAXBI)

that

regulator

power

1is

multiple voltage output power

provides operating voltages for the Bus Interconnect

module exclusively.

A VAXBI module can contain up to six VAXBI PC boards depending on
number of peripherals used. It provides the interface between
the
peripheral equipment and the VAX 8800 system.

Two

H7189

power regulators can be configured into backplane I of

the MPS to accommodate two VAXBI modules, as required.

Figure

3-10

illustrating

1is

block

diagram

its major components.

of the H7189 power regulator,

3-26

MPS
BACKFLANE
J1

gEH'SSEAAL

GREEN

P
300V
DC BUS

SWITCHING
REGULATOR

—

L— -2V RETURN

glLJTTgé'T

YELLOW

—

FRONT PANEL INDICATORS

-2V
CONTROL

SWITCHING
TRANSISTORS

RED [

MPS BACKPLANE

+BV

]

OUTPUT

BALEN

FILTER

MODULE | , 5y

SWITCH

LC-€

ENABLE

SYNCH

REG
CONTROL

MODULE |
MODULE I

J3
+15V

LINEAR
REG.

r—

+15V

FILTER

LINEAR
REG.

FILTER

LINEAR
REG.

RTN

+15V

SWITCHING

+15V RTN

TRANSISTORS

+12V

+10.5V

+12V RTN

ENABLE
SYNCH

-12V

FILTER

LINEAR

REG.

-12V RTN

-5.2V RTN

+ 12V

FILTER

RTN

-12V

+10.5v

-5.2V

MPS BACKPLANE
J1

ENABLE

SYNCH

SWITCH
REG. CONT

MKV8E6-1254

Figure

3-10

H7189

Block

Diagram

There

are

three

Module

®
®

Module
BALUN

Modules

boards

the H7189

regulator:

II
Module

and II

interface with the MPS backplane through 80-pin

PC
board
connectors. The functions performed by Modules
and the BALUN module are shown in Table 3-9.

Table

3-9

H7189 Module

Functions Provided

-2 Vdc

switched

regulator output

+5-Vdc

switched

requlator

drivers

Functions

Module

LED

and

—--

output

green
red
yellow

Overtemperature

BALUN

)

(oY
e]

linear

regulated output

+12-Vdc

linear

regulated

output

-12-Vdc

linear

regulated

output

-5.2-Vdc

switched

Storage

capacitors

brief

following

output

el =)

output

the

H7189

°w

functional

description

section.

3-28

(2)

regulator output

NOWO

kl\./

circuit

+15-Vdc

Power

witchi

sense

connectors

voltages

required.

presented

the

3.4.6.1
the

H7189

transistor

3-10).

Functional
the

bus

modules

and

connected

High

Stepped

down

Stepped

voltage

TI1,

isolation
voltage

current

located

—-2-V

switching

+5-V

output

regulator
Transformer

between

the

module

T2,

regulator
filter.

the

and

The

primary

located

output
+5-V

and

into

switching
T2

(Figure

regulators

secondary

output

filter

supply

uses

switching

Module

II,

applies

secondary

output

to:

+12-V

filter

and

linear

regulator

-12-V

filter

and

linear

regulator

-5.2-V

filter

regulator

types

High-powered

Linear

High-powered

and

-5.2

used

supply

regulators

uses

switching

the

H7189

regulation

module:
performed

the

performed

the

(-2

regulation

performed

regulation

power

linear

T2.

switching

are

-5.2-V

primary

regulation

high-current

+15

switching

Low-powered

secondary

two

(the

the

regulation

primary

provide

bus

applies

feeding

brought
two

regulators

filter

the

regulators

+15-V

Vdc
to

transformers

Three

300

applied

to:

voltage

and

provide:

)

Transformer

Description

connector

the

by
is

used

VAXBI.

Module

3-29

for

These

regulators

those

outputs

are:

that

The
high-powered
switching
regulation provided for the +5-V and
-5.2-V
supplies
also
provides
a quasi-regulated voltage to the
inputs of the following regulators:
o

-2V

+15

+12

-12

The

=-2-V

handling

(2)

supply

wuses

switching

regulator

for

higher power

capacity.

Linear

requlators

because

the

are

used
for
the
required is lower.

current

Module

voltage

outputs

The

switching
regulator control circuits located on Module I and
IT
PC
boards
provide
interfacing and control functions for the
high-power switching regulators. These functions include:
®

POWER

SYNCH

ENABLE

—--

Enables

operation

Synchronizes

switching

the

regulators

system

clock

These
signals
are
backplane connectors

Other
he

The

signals
1

regulator

front

regulator

brought into the H7189
for Modules I and II.

brought
start-up
e

into
.

bias
=]
L

panel

contains

operating

status.

Indicator

(LED)

the H7189

are

module

through

+/-12 V and

the

MPS

+/-12 V RTN,

voltages.
1

three

LED

1indicators

that

Indication

GREEN

faults

—--

RED

Overvoltage

YELLOW

Overcurrent

Normal

operation

display

The
all

GREEN LED is driven by an AND circuit sensor
regulator outputs are operating correctly.

The
RED
LED
will
1light
when
overvoltage fault condition.
The
vyellow
overcurrent

LED

will

1light

any

when

any

the

lights

when

regulators

have

regulators

have

fault.

A THERMAL SENSE circuit, located on Module I,
an overtemperature condition has been sensed.

Table

3-10

1lists

H7189

regulator

the

that

the

output

voltage,

VAXBI

Table

Output Voltage

(Vdc)

the

3-10

Current

current,

H7189

Outputs

Power

5.0

275

2.0

5.2

130

12.0

15.0

7.5

15.0

7.5

3-31

the

EMM when

and power provided

module.

(Amps)

signals

(Watts)

Tables

two

3-11

and 3-12 describe the components and
board subassemblies, Module I and Module

functions

II,

of the
the H7189

regulator.

Table

3-11

H7189

Component/Interconnect
J

Module

Circuits

and

Interconnects

Description/Function
80-pin

board

connector

MPS

backplane

300-Vdc

bus

Intermodule

Isolation

power

connector

transformer

with

multiple

outputs

01,02

Power

switching

transistors

for

regulator

Switching

Table

3-12

H7189

Module

requlator

Circuits

and

for

Description/Function

MPS

300-Vdc

bus

connector

Intermodule

connector

Regulates

connector

+15-V

supply

+12-V

linear

regulator

-12-V

linear

regulator

Switching

3-32

supply

Interconnects

Circuit/Interconnect

backplane

+5-V

regulator

for

(2)

=-5.2

5-V

3.4.7
The

MPS

Regulator

regulators

equipment

(BITE)

operating

status

Table

1-3

BITE

indicators
of

repeated

each
here

Indicator

Indication

Green

Module

LED

Indicators

contained

the

MPS

provide

regulator,
for

cage

a
as

convenience,

Figure

test

Chapter

the
1.

1-7.

Definition

The

power

within

LED

built

indication

described

regulator

properly.

Red

have

visual

Overvoltage

The

output

regulation

faults

are

The

regulator

operating
voltage

range.

evident.
voltage

has

crowbarred.
Yellow

LED

Overcurrent

The

above

3-33

regulator

its

output

rating.

current

LEDS:

Module 0.K. ©

GREEN

Over Current O

RED

Over Voltage O

YELLOW

Input:300V.D.C.@1.2A,

Qutput:5.05.2V.D.C.885A,

Ehsnesl
Power Supply
H7186-A

=
©
MKVEE-1225

Figure

BITE

3-11
IV

3-34

Indicators

3.4.8
Buses and Backplanes
Signal
and
power
connections between functional
VAX 8800 system are made using the following:

sections

the

Multilayer, multiconnection printed wiring boards
Flexible, multiconductor printed wiring cables
Flexible,

insulated,

Laminated,

Rigid,
The

major

functional

876A

NBox

)

CPU

VAXBI

power

and

discussed

3.4.9
The

high-current

and

rigid

conductor

sections

the

multiconductor

conductor

cable

straps

buses

VAX

8800

system

are:

MPS

)

The

single-

high-current,

MPS
MPS

signal
the

connections

following

and

between

these

sections

are

Backplane

backplane

sections

paragraphs.

that

consists

span

the

provides
electrical
following:

two

width

contacts

hardwire-etched
the

between

MPS
the

cage.

conductor

The

requlators

backplane
and

the

EMM

CSP

CPU

backplane

VAXBI

backplane

System

The

EMM

interacts

The

with

the

regulators

<B:H>

Monitor

regulator

output

Monitor

regulator

temperature

Margin

test

Start

up/shut

Monitor

CSP
means

the

clock

MPS

down

(+/-12

voltage
faults

output

regulators

power

and

the

regulators

the

(+10.5

and

EMM

and

ILM modules

the

pulse

backplane.

provides

circuits

to:

status

start-up

voltages

system

modulator

regulator

fault

provides

operating
by

clock

the

synchronizing
regulators.

3-35

signals

width

dc outputs are connected to the CPU backplane from
regulator
The
backplane. High-current outputs are connected to the CPU
MPS
the
backplane using laminated copper straps to reduce voltage drops.
The

VAXBI

voltage

outputs of the H7189 regulators are connected to the

backplane

from the MPS backplane using flexible cable.

Each regulator interfaces to the MPS backplane through multipin PC
board connectors

Table

3-13

that mate with

identifies

Table

Figure
power

the

regulator PCBs.

the connector(s)

3-13

MPS

for each regulator type.

Regulator Connectors

Regulator

Connector

No.

H7180

H7186

H7187

H7189

J1l

and

of Pins

3-12 illustrates the backplane and bus organization of
of
details
show
3-14
and
3-13
Figures
system.

backplanes.

3-36

the
the

MPS

MPS1 BACKPLANE

T80

“150

H7186

MODC

| MODB

MPS 2 BACKPLANE

SPARE

“Ts0

150

H7187

H7189

MODD

| MOD
D

L’

150 “Ts0T50
“Ts0

EMM

H7180

MODE

| MODE

T150

T80

180

H7189

| MODF | MODH

300 V BUS

_30oveus

apoveus

BBU

300 Vdc

]

DIST

N BOX

H7170 X

1B AC

H7170Y

876A

38 AC
MKVE6-1248

Figure

3-12

Organization
IV

3-37

the

Power

System

UJ?

J11

DJQ

J25s ]

MKVED-1222

Figure

MPS

3-13
IV

3-38

Backplane

J56
Jb8

F J57

DJ61
J60

DJGG

J65
J68

J64

J59

[]JGB

MKV86-1223

Figure

3-14

MPS

3-39

Backplane

3.4.9.1
dc

300-vdc

voltages

converters

There

are

indicated

the

two

No.

SECB

~--

The

300-Vdc

the

3-14

bus

sections

supplying

300-V Buses,

Source

Power

Sources,

Regulator
MOD

(H7189)

MOD

(H7189)

H7170X

MOD

(H7186)

BBU

MOD

(H7186)

MOD

(H7187)

MOD

(H7180)

for

dual-CPU

300

Vdc

1is

cage.

The

buses
to

the

high-power

ac-to-dc

power

the

requlators,

cabled

are

the

1leaf

and

Loads

Load

BBU

The

high-voltage

H7170X

MPS

Connections

carry

and

3-14.

H7170Y

required

buses

H7170X

regulators.

300-Vdc

Power

SECA

MPS

Table

Bus

Buses

developed

configuration.

from

rails

the

NBox

located

regulators
contacts

the

below

are

made

1located

buses

the

located

through
the

the

regqulators.
high-current,

front

panel

the

regulators.

The

connectors

when

the

mate

electrically

regulator modules

are

Each
regulator
must
make
connections in the MPS:
®

Multipin

)

300-vVdc

power

board
to

and

mechanically

inserted

least

the

bus

MPS

3-40

two

into

the

mechanical

backplane

with

the

designated

and

Dbuses
slots.

electrical

3.4.10
The
power

Environmental

environmental
system

chapter,

the

described

The

These

major

functions,

major

8085A

elements

included

Microprocessor

Key

Regulator

Status

(EMM)

described

contained

the

are:

Electric

EMM

are

performs

LO/DC

Voltage

System

Monitor

LO Circuits
Control

Measuring

(Battery

Air

Flow

Sensor

Temperature

Circuit

Backup

Control

Sensing

Console

Unit)

Circuits

Communication/Interface

3-41

the

shown

Control

BBU

Chapter

Registers

Total-Off

System

logic

Module

module

detail.

elements

Monitoring

monitoring

EMM

variety
2.

1In

module

Figure

this

are

3-15.

MODULE KEY
ORI OR

<—_~,

»»g

REGULATOR CONTROL

;

POWREG

;

LOOPS

BBU

ENABLED

REGULATOR

ON/OFF/MARGIN

CONTROL LINES

MARGEN

—

KEY

pTTTTTTTI T '

;

MARHILO

PRO-38N
SYSTEM

CONSOLE

BBU

CONTROL

STATUS

=4 <+—8

MICRO-

PROCESSOR

}
e
e
1

I
8-BIT
—

MISREG

SID_,.

J MPS/BBU/EXT IN/

AIR FLOW STATUS LINES

LO
; __ACIDC
(FROM AC INPUT MOD)

ACLODELO
LOGIC‘

- SYSTEM AC/DC LO

EXTERNAL
OUT
CTL

(NOT USED)

sop _ !

SYSTEM

BBU ON

)| e
16-BIT_
Lo
MODOK
:
!

B8085A

REGISTERS

—--~——%-2 Vv CROBAR

VOLTAGE

AIR

FLOW

SENSOR CTL

———————% SENSOR RESET

MEASURING
CIRCUIT

‘

--------------------- .)

VOLREG

;

VINSEL

TOTAL-OFF

]

___________________ J

yY
|

|
TEMPERATURE
CENSE OTL

¢—————

—_—

REGULATOR OVERTEMP

P TOTAL-OFF BUS

{TO AC POWER CONTROL)

THERMISTOR VOLTS
7}
o3 o

4——— BACKPLANE

1 <+

GROUND

CURRENT
MONITOR

VOLTS

l¢———— GROUND CURRENT

SCLD-457

Figure 3-15

EMM BRlock Diagram

3.4.10.1
the

8085A

Microprocessor

8085A microprocessor
8085A

The

the

byte

PROM

8x1K

byte

RAM

PCI

(Program

byte

PROM

8085A.

the

Communications

the

main

components

chip

the

byte

software

connects

serial

The

chip

stores

The

are:

single-chip microprocessor

8x8K

contains
PCI

8-bit,

System

system

EMM

main

RAM

body

the

provides

registers
to

Interface)
the

EMM

program

executed

working

storage

area

and

console.

The

addressable

console

over

the

EIA

RS423

RS232

line.

NOTE

The interface
a nonstandard
the

data

also

to the serial line is
interface that allows

transmitted

received

the

requirement

communications

The

8085A,

PROM,

(ADR)
8085A

bus
and
asserts

memory

addresses

I/0

are

asserted

the

The

the

PCI

ADR

the
AD

bus

I/O

registers
etc.)

the

PCI

PCI.

This

EMM/console

protocol.

all

connect

between

8-bit

address

bus.

and

the

bus,

operation.
the

addressed

I/0

MISREG,

and

the

a
multiplexed
8-bit address/data (AD) bus.
The
I/0
register addresses and the high-order byte of

addresses

read/write
operation,

and

RAM,

used

low-order
but

During
is

used

the

EMM

are

the

EMM

the

rest

transfer

or memory

part

only

data

(RAM)

and

addresses

beginning
the

read/write

between

the

8085A

location.

hardware

control

memory

the

registers

monitor

(POWREG,

power

system

operation.
Other

When

logic

elements

the

8085A microprocessor

)

5.0688-MHz

°®
®

synch counter
parity generator/checker
a

RAM

parity

Counter)

1is

reset

done

similar

the

oscillator

error

and

power-up

for

8085A

detected,

selftest

sequence.

and

3-43

PCI

the

system

include:

clock

8085A

(including

RAM

(Program

test)

selftest

prevent

error

sent

the

parity

operations,

parity

the

check

control

(including

error

EMM

enable

Dbit

from

bit)

the

EMM's

any

time

can

read

the

8085A

read/write

The

needed

the

being

can

8085A's

serial

control

8085A's

serial

EMM's

3.4.10.2

bits

Each
to

parallel

the

EMM

VAX

following

data

1line

some
line

measuring

this

the

execution

8085A

series
and

the

8085A),

depending

the

operation

these

machine

and

the

called

cycles

data

bits

serial

used

(SOD)

EMM's

used

over

the

data.

set

are

circuits.

the

read

fault

KEY

output

The
of

The

electric
key
monitor
negating a logic level (KEY
detected.

FAULT)

mislocated

parallel

The

clear

control

circuit.

the

(SID)

(MODULE

system,

closes

Memory

Clock

signals

the

<c¢ircuit

fault.

board

1in

the

key.

I/0

controller

adapter

The

parallel

key

prevent

module

CKT,

backplane

module
which

damage.

slot

normally

This

can

intended

For

example,

when

CPU

series

the

module

key

loop

parallel

plugged

not

key

loop

into

being

used

open,

occur

for

board.

(the

CPU

into

keying

module

8800

groups

The

entirely

transfers

when
the

selftest

bit

status

console.

between

single

ENABLE)

message

instruction.

Electric
Key
Monitor
-stops the power-up sequence by

LED

the

The

read/write

five

receive

in
data

module

during

control

differ,

circuit

error

set

almost

processed

8085A

8-bit

output

voltage

(as

one

send

input

8085A

MISREG.

operations

single

making

8085A

single
the

data

and

execute

the

normally

operations

executed.

cycle,

addition

bus,

causes

addresses.

read/write

instructions
machine

the

consists

transfer

addresses,

sequence

data

I1I/0

resetting

clears

instructions
and

failure)

program

memory

RAM

console,.

when

closed

faulted

module

plugged

different

function

closed

being

(by

memory

controller

VAX

3-44

the

8800

group

grounded)

module

slot.

configuration.

addition

monitor

(module

key

MODULE

ENABLE,

supplying

Holds
Causes
ac

3-4.

)

The

microprocessor

regulator

3-7

POWREG

MARGEN

MARHILO

MARGEN

modules

returns,

the

logic,
--

and

high

console

MARHILO

and

low,

the

MPS

the

electric

commands

CPU

each

MPS

registers

(+/-5%).

3-45

key
the

initialize

The

currently

state
shut

signal

regulators

for

are listed in
configuration. The

3-15,

requlator

console

allow

down
1is

start.

cabinet,

Figure

response

mod

sequence

regulator
in

backup

initialized

(except

Circuits

shown

allows

EMM

battery

8085A's

power-up

Control
located

the

normal

shows

control

margin-tested

that

EMM

system,

off

indicates

the
all

faults,

asserted.

cabinet:

allowing

Figure

regulator

keying

receiving

the

Regulator

8800

from

power

deasserted,

3.4.10.3

module

EMM

which

power

VAX

the

fault)

2.
When

detecting

disables

the

Table
EMM's

contains:
to

turned

commands

each

regulator

3.4.10.4

Regulator

regulators
EMM.

The

attached
program

One

the

turned

Circuits

1lines

power

Battery

and

off

(SHUT

receive

the

command

DOWN

ON/OFF

The

RTN

power

from

MOD

commands

the

<B:H>)

under

EMM

power

that

enables

the

11t0m
matic
au

occurs.

activated

regulator

the

regulator

Engineering

when AC

applied

from

negates

circuit

(except
be

cleared,

causes:

microprocessor

(except

EMM

when

power

LO)

ENABLE

regulators

(AC

backup

EMM's

EN,

backup

power

MODULE

REQ

regulators

Backup

The

BBU

battery

All

BBU

REGL

through

be
to

held
be

turned

regulator

off

initialized

asserted

EN,

which

turns

off

all

(D-CS-5415304-0-EMM5)

for

details

the

B).

drawing

allows

regulator

apply

+5.0

Vdc

the

backplane.

3.4.10.5

Regulator

margin-tested
Eight

are

control

POWREG

bit,

Interrupted

memory

Control

control.

activation

MPS

regulator

POWREG

Refer

On/Off

MPS

Margin

Control

grounding

either

regulators

)

EMM

°®

MARGEN

MARHILO

<B:H>

microprocessor

can

Circuits
its

high

margined

=-or

using:

low

regulator
margin

line.

H7188

/
/

MPS

MARGEN REG

MARHILO REG

N/U

REGULATORS

N/U

MOD H
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170

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|

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H7186
+5.0

MODULE
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+12V

DC REG
EN

BBD

FROM BBU

FROM UPC
MKV86-124/

Figure

3-16

Voltage Margining Circuit

*S3TNOITO Tox3juod bButuibaew WWH oyl Jo weabeip e sT 9[-€ =2anb14

EMM

3.4.11
There

The

Status
are

two

MODOK

MISREG

MODOK

Registers

status

bits

Regulator

The

EMM
LO

registers

module

regulator

power

been

range

The

MISREG

the

serial

the

and

MPS

<B:H>

BIT

cage

has

EMM

board:

OK)

status

<2:0>)

status

bits

flow

RAM

parity

error

RAM

parity

check

its

detected

The

line.

asserts

used
AC LO

Air

its

MODULE

output

other

(latched)

AVAIL

(fully

status
within

line
the

the backplane
etch. It
1is
the
during EMM/console communications
signal is discussed later.
indicate:

enable

charged

faults.

crowbar

voltage

faults

AC
BBU

(ID

applied,

address

-2-V

(MODULE

determined

physical

over

~JOY
U s W N

has

number

EMM's

the

status

Each

The

indicates:

once

regulation

located

and

3-48

ready

for

use)

3.4.11.1

AC/DC

the

system

complex

power

BUS

Circuits

when

the

NBox

falls

the

signal

BUS

asserted

the

below

205

specifications.

regulators

System

Refer

start

AC LO
EMM.

from
holds
and

EMM

that

the

Dbelow

that

needed

LO,

which

sequences

The

SBIA,

also

asserted

the

discussed

power

and

the

MODL

converters
responds

the

voltage

maintain

LO,

H7170s
to

the

regulator

indicates

that:

Chapter

for

details

BBU
the

system

REQUEST

and

memories

operator

these

the

EMM

signals

when

negated.

until

the

any

are

signals
means

to be asserted
BUS LO IN L to
is

shown

MODULE

powerup,

notified.

in
be

Figure

signal,

this

signal

regulators

are

turned

signals

generated,

are

used

the

EMM

after

the

normally.

The

for

asserted

and

BUS

CPU

can

ILM

input

DOWN,

initiates

NBox,

main

POWER

power

The

voltage from

after

BBU

diagram

The

and

EMM

providing

warning

The

for

flows.

loss

)

occurs

requests

power

signals

lost

CPU,

regulator
BUS

signal

output

timing

operating

The

fault

the

signal from the NBox causes AC LO IN L
The BUS LO signal from the NBox causes

asserted.

BUS

(EMM5

300-vVdc

lost,

The

to
rms.

indicates

signal

power

EMM

the

power-down

ILM

the

level
165

1is

below

when

operator

the

The
the

power

Vdc.

BUS

When

ac-input

signaling

power

power-down

regulator

main

asserted

MPS

The

(H7170s)

falls

are:

SBIA

and

only

fault

condition

timing

signals.

BUS

cleared

has

been

signals

for:

CPU

SBIA

IN
by

output
a

cleared.

signals

console

Figure

3-49

are

POWER

3-17

latched

command

shows

the

AC/DC

Figure 3-18 shows a detailed view of

ACLOINL

BUS LO IN L

CPUACLOL

SBIA ACLO L

CPUDC LO L

BB1A DCLOL

the AC LO/DC LO circuit.

AC ON

AC OFF

}({

oms
10
MS
10.8MS
MIN 1 MIN
|

(

))

@ DC POWER BUS OK AND REGULATORS TURNED ON BY CONSOLE
@ SYSTEM AC LO & DC LO TURNED OFF BY CONSOLE

@ INITIATES SYSTEM POWER-FAIL RECOVERY SEQUENCE
MKV86-1240

Figure

3-17

AC/DC

LO Timing

Diagram

AC FROM
876 POWER

FROM MPS

REGULATORS

CONTROLLER

NBOX POWER CONV.

MOD<B-UsUKH

CONTROL AND

L
S
LO IN
BU

EMM

H7188

STARTUP PWR

INTERFACE

14-¢

LOGIC MODE

Egs

INE

LAT

| PCLo H

~ TO HOST
> CPU(S)
AND 1/0
BACKPLANES

DRIVER

LAT DC
L
LO

——

PCM
A

(H7170)

MIS
REG

PCM
B
(H7170)

A
8085

AC LO

MOD

IN L

OK
REG

B
U

MICRO

cpu
SYS

- 10

"CONSOLE

LAT AC
H
LO

(SOD)
LINE P

aT ac

FET
DRIVER

SID SOD

AC LO L

MKV86-1244

Figure

3-18

AC/DC

Circuit

3.4.11.2

Total-Off

total-off

circuit

all
CB.

modules
A

When

The

POWER

o
o

CPU

OFF

flow

falls

air

filter

The

air
BBU

The

NBox

BA1ll-A

TOTAL

OFF

EMM

ILM

EMM

876A
can

tripping

occur

when:

below

specified

limit

interlock

command

BRKR2,

flow
cabinet

Regulator

and

originates

During

cabinet

normal

system

Regulator

Air

During
When

BBU
any

command

and

from

two

sources:

TOTAL

OFF

sensors

the

ILM

also

can

the

EMM

initiates

the

front

eitkef

the

monitors:

(MOD
of

OT)

cabinet

monitors

MOD

<cited

above

EMM

the

ILM

OT.

default,
to

TOTAL

disable

power

restored

panel

manually

the

TOTAL

the

the cause of the
removed and reset

OFF
EMM

resetting

command,
module

BRKR2

the

display

fault. The latches
on powerup.

the

magnetic
a

retain

4-bit

the

OFF

BRKR2

876A.

indicate

Figure

interlocks

bottom

conditions

power

filter

overtemperature

sent

the

air

screens

+ 1

(see

overtemperature

operation

operation,
of

876A

temperature

filter

main

single-phase)

following

(C:H)

CPU

the

The

power

(blower)

The

CPU

from:

3-15):
Air

open

removed

(three-phase

monitors

Circuits

shutdown

overheats

power

mover

The

Indicator

emergency

overheats

The

trips,

and
an

command

Air

The

the

cabinet

regulator

BRKR2

The

powered

The
A

¢«

=W
N e

TOTAL

Control
1initiates

876A.

latches
code

code

to
when

When

EMM

does

cause

TOTAL

OFF

not

the

interface

(air

filter

logic

resistor

strings

the

CPU

CPU/MPS

CPU

EMM's

the

system

Sensing

which

the

delta

TOTAL

OFF

program

and
are

also

made

from

power

emergency

The

EMM

fails

The

EMM

program

indicates

Figure

console,

the

indicate

the

RTN

SW2

The

temperature

divider

response

the

circuits

EMM

SENSE

are:

SENSE

<2:4>)

<2:4>

monitors
a

the

thermistor.

SENSE

series

temperature-sensitive

the

command

the
EMM.
Thermistor
shutdown when:

cabinet

Temperature

MEASURE

usually

CPU

overtemperatures.

requests

from

temperature

(T3)

used

module

faulty

excessive

sensing

(THERM

CPU

connection

(THERM

when

fault.

voltage
a

(THERM

are

and

routinely

Console

indications

temperature

regulator

console.

sensing

resistor

temperature

internal

EMM

component

temperature

control

display

temperature-sensing

initiate

shown

the

indicating

the

temperature

amb.

asserts

voltage

fixed

default

The

latch

Circuits

one

The

the

cabinet

temperatures
measurements

made

(ILM)

grounded,

monitored

resistor.

junction

Measurements

The

Temperature

circuits

thermistor

initiated
magnetic

module

interlock)

sensing

the

fault.

The

3.4.11.3

command

cause

temperature

circuitry

contained

3-19.

3-53

the

EMM

H7188

EMM

(12 V)

VOLTAGE

‘ {THERMISTOR SOURCE L)

GENERATOR

SwW2
(AIR FILTER-

THERM SENSE <3>

TOTAL OFF

TEMPERATURE

THERM SENSE <4:1>

SENSE

TEMP FAIL L

CONTROL

CONTROL
AND

TOTAL OFF

BUS

INDICATORS

OT SWITCH —»

g:mg ;;

POWER
CONVERTOR

_Z/L_.
TO 876
POWER

MOD <B:J= L

20—

INTLK)

(SEL) ——

T4 O—

T30—

_____? }:E[D) 2;

CONTROLLER

(RESET)

T10OAIR
FLOW

SENSOR
CONTROL

SOD
A
D

»|

VOLTAGE

MEASURING

THERM sense | CIRCUIT

8/
/

Blg

8
/

:mcc):goscfiu

T/
/

SYSTEM

TOFROM
CONSOLE

<4:1>

SID

MKVB6-1245

Figure

3-19

Temperature

Sensing Circuit

3.4.11.4
Voltage Measuring Circuit -- The EMM performs
measurements under program control on the following:
1.

All

MPS

All

thermistors

regulators

voltage

<B:H>

<1:4>

Voltage
measurements
are
performed
wusing the circuits shown in
Figure 3-20. The unknown voltage is determined using the following
steps:

EMM program specifies

Unknown
to

voltage

selected

Reference
voltage
comparator ramps up

When

using

tested.
VINSEL

command

reference

(8-bit
D/A)
1is
also
from 0 V at 27 MV/step.

volts

unknown

and

fed

connected

volts,

comparator

unknown

voltage.

outputs

signal.

Digital

value

Analog

voltage

digital

code

regulator

to be

comparator.

voltage

in D/A = value

for

Analog
voltage
(compliment)
of

27.6 MV X decimal

equivalent

333.3
MV
X
decimal
8-bit
digital
code
for

voltage.

NOTE

To
maintain
positive
slope
for
converting temperature measurements

(thermistors
have
a
temperature
coefficient),

negative
the A/D
magnitude
1is the complement of the
voltage drop across the thermistor.
That
is,
it
is
the
digital
complement of the value measured by
the EMM's voltage measuring circuit
and
contained
1in the VOLREG after
the

measurement.

8-bit

voltage.

3-55

equivalent
thermistor

TO/FROM

CONSOLE

1y
7

8085 A
SYSTEM

AD BUS

—

DAC

VOLREG

> SID

COMP

UNKNOWN VOLTAGE

8,
v

VINSEL
hEQ

8,
~

DECODE

16,

#—>|

RELAYS

__J
MKVEE-1243

Figure

3-20

Voltage Measuring Circuit
IV

3-56

V = DIGITAL COUNT x 27.3 MV

V UNKNOWN - COMPARATOR INPUT

T = DIG. COUNT COMP. X 333 MV

VOLTS %

V REF - D/A OUTPUT

(COMPARATOR
INPUT)

LG—-¢

L 27.3 MV/ STEP FOR
VOLTAGE,

333 MV FOR

THERMISTOR

T ——

CLOCK

flflflflflflflM’lflflfl!’L

J_—

COMPARATOR OUT
MKV86-1241

Figure

3-21

Voltage

Measuring

Technique

3.4.11.5 EMM/Console Voltage Tests -- Voltage measurements of
regulator output and thermistor temperature can be requested by
the console using the MEASURE command.

Voltage

readings

returned to the console by the

to a MEASURE command,
1.
2.
3.

consist of:

An 8-bit binary value
A sign bit
An input select code

3.4.11.6 Battery Backup
control 1logic activates
signals

°
°

EMM in response

are

Control -- The EMM's BBU
(BBU)
Unit
power when the following
backup
battery

asserted:

AC LO (from 876A in NBoOX)
MODULE OK H (from Regulator B)

responds to the above conditions by asserting BBU REQ EN
EMM
The
to the ILM. The ILM asserts BBU RQOST RTN and provides backup power
if the BBU batteries are fully charged.

300 vdc to the NBox, which is connected to the
The BBU provides
1is regulator b. Regulator b, the only regulator
as
300-vdc bus,
provides +5 V to the
active during battery backup operation,

memory array and the CSP. The CSP module uses MOD B +5 V to create
+/-12 V to bias the EMM and ILM modules during battery backup.

power returns to the 876A, the 300-V output from the BBU
ac
When
is disabled and power is supplied by the NBox H7170 modules.

is applied to regulator B, the EMM asserts ARRAY +5 V
When power
OK, enabling refresh operations in the memory array. The signal is
asserted as long as the MODULE OK signal for regulator B is true.
Refer to Figure 3-22 for a

detailed

3-58

diagram

of the BBU system.

3.4.12

Battery Backup

Unit

The
battery
backup
unit
300-vdc
backup
power
to
momentarily

interrupted.

The

consists

H7231-M
[

charger
1.

receives
and

400-milliamp

output

120

provides

(H7240)
lead acid

Vac

two

battery

pack

at its input from the 876A poWer

levels

charge

the

battery

Charge - 400 milliamp to 59 volts dc battery
Maintenance - 10 milliamp above 59 volts dc

The

VAX 8800 system delivers
when
utility
power is

of:

charger (H7230)
A dc-to-dc converter
A 48-V rechargeable,

controller

The

for the
bus
2

°
®

The

(H7231-M)
(BBU)
300-V

falls

charge

below

dc—-to-dc

level

reinitiated

when

volts.

converter

pack:

output

the

battery

voltage

‘

(H7240)

steps

the

48-V

to
300
Vdc
wusing
a
flyback
transformer
converter. The 300 V
generated
by
the
converter
1is
provided on demand to the NBox,
which is connected to the 300-Vdc bus feeding the regulators.

modulation

Regulation

of
the
(pwm).

voltage

continuously

The

are

H7240

has

the

H7240 output is accomplished using pulse width
The
ac
1input line voltage and the dc battery

following

overvoltage

operation

A
primary
components
limit, fuse

power

operation

monitored.

the

protection

protection
output

overcurrent
from
output
protected).

transistor
above

circuits:

circuit

voltage

inhibit

converter

330

nominal.

Vdc

sense circuit to protect circuit
overload
condition
(3 A surge

overtemperature

degrees

exceeds

3-59

(194

circuit

degrees

F).

inhibit

The

battery

backup

FAIL

DIGITAL

Both

signals

power.

The

control

signal

The

BBU

open

two

special

features:

monitor

power

ENABLE

relay

signal

terminating

allows

the

battery

H7240

backup

respond

inputs.

interfaces

3-22

bus

the

SAFE

power

The

has

ENABLE

power

(TOTAL OFF
H7240.

connector.

Figure

SAFE

FAIL

DIGITAL

signal
of the

system

bus

RTN),

the

interface

shows

the

BBU

interface

which,

monitors

when

power

system

signals

are

subsystem

the

asserted,

means

defined

block

emergency

disables

Table

diagram.

shutdown

the

15-pin
3-15,

output

type

Table

3-15

Battery

Signal
BBU

Backup

Interface

Signals

Definition

Enable

Activates
be

the

asserted

series

power

relay. Must
battery backup is

before

requested.

BBU

ENABLE

BBU

AVAIL

RTN

BBU

ENABLE

When

true,

provide
BBU

AVAIL

ILM

BBU

RTN

BBU

RQST

signal

BBU

backup

signal

Requests

load

indicates

battery

AVAIL

return.

backup

the

loss

the

occurred.
ILM

BBU

MOD

ENABLE

RQST

RTN

ILM

BBU

Enables

backup
MOD

ENABLE

BAT

STAT

ROST

RTN

MOD

signal

"Reqgulator

Indicates

signal

return.

battery

status

State

Current

OFF

READY

constant

power

the

main

has

return.

power.

ENABLE

Flow

current

battery

follows:

Batteries

charging
full

charge

rate

(slow)
ON

rate

(fast)

NOTE

The

signal

pairs,

and

ENABLE

RTN

from
ground

BBU

ETC,

opto-couplers
isolation

protection

the

and

ENABLE/BBU

are

obtained

that

provide

high-voltage

ILM.

3-61

return.

battery

when

available

power.

charging

discharging

MPS BACKPLANE #2

MPS BACKPLANE #1
.

r
300 VDC BUS

EMM

REGULATORS

o188

REGULATORS

(BBU REQ RTN)

(MODULE ENBL)

SIGNAL I/O

OVERTEMP

I
i

l
|

NBOX PORT
CONDITIONER
-

300 Vdc

SIGNAL 1/0

(TOTALOFFRTN)I|

876A

CONVERTER

POWER BOARD

FROM

RETURN

300 Vdc

» 10

| OUTPUT

]

BUS I
DEC POWER
5

CONTROL BOARD

H7240

SENSOR

SIGNAL 1/0
H7230

| 2,
|eaTTERY
’
)

BATTERY | 2, | BOARP

)

| 1| BaTTERY
2,
.
.

CHARGER

2, | BATTERY
/

BATTERY

BACKUP

|
!

FROM

876A

UNIT H7231-D
MKVE6-1 248

Figure

3-22

BBU
IV

Block

3-62

Diagram

3.4.13
Air Flow Sensing Circuit
The
EMM monitors two air flow sensors located in the
AIR
FLOW
1
and
AIR FLOW 2, The EMM program checks
each sensor by reading the MISREG.
Wnen

notice
When

single
is

both

shutdown
The
The

sent

flow

the

can

air

flow

sequence,
command.

and

3-23

read

the
the

sensors

are

time

shows

any

the

air

flow

detected,

cabinet,
state of

five-minute

shutdown

console.

indicate

sent

also

fault

system's

detectors

notice

console

Figure

air
to

CPU
the

air

system's
air

flow

reset

flow

fault

the

thereafter

sensing

3-63

fault,

two-minute

console.
sensors
EMM

circuit.

during

response

any

time.

power-up

a WRITE

EMM

H7188
1,

MISREG

TO/FROM

6
8

A—f—

AF2

AFS

79-¢€

s08E A

TOTAL OFF

MICRO CPU

INDICATOR

CIRCUIT

SYSTEM

Q (IND 1)

Q (IND 2)

—Q (IND 3)

QO (IND 4)

‘

SOD

(RESET)

AF1 /AFR | O

FLOW

CONTROL

AFS

AIR

Sensor

AIR FLOW RESET

MKV86-1242

Figure

3-23

Air

Flow

Sensing

Circuit

3.5

COOLING

SUBSYSTEM

The

cooling

air

moving

the

bottom

the

three-phase

The

moving

below

entering
that

through

and

CPU

876A,

cabinet

negative

cardcage.

washable

located

The

air

drawn

pressure

aluminum mesh

the

filter

Correctly

through

created

bottom

filter

shelf,

interlocked

just

before

assure

place

leaving

the

cardcage

the

back

maximum VAX

dissipate

seated

8800

area,

the

system

6500-watt

the

CPU
(a

heat

moving

dual-CPU

load

4100

watts

the

CPU

logic

.
.

2000

watts

the

MPS

cage

The

balance

400

air

enters

the

MPS

area

cabinet.

CPU

with

is:

exits

The

passes

NBox

the

cabinet

motor.

2.
Upon

and

alr

the

through

CPU

watts

configuration)

module

expected

follows:

the

area

NBox

An additional 400 watts is dissipated by the three-phase motor.
The

power

require
The

dissipated

forced

temperature

degrees
CPU

F),

1logic

MPS

power

air

four
Four

rise

the

degree

and

degrees

rate

to
is

air

The

1100

satisfy

the

mounted

the

outlets

housing

front-end

corners

air.

the

with

flow

assembly

cabinet

not

sufficient

CPU
rise

(44.6

cabinet
(50

deg.

degrees

contributed

degrees

rise

allowed

(62.6
by

the

for

the

and

1200

above

within

steel

CPU

cabinet

the

rear

the

air

into

direct

plenum,

which

CFM

has

been

requirements.

determined
The

plenum/housing

above

the

exhaust

the

air

flow
with

function

Figure

3-24

outlets,

during

acoustically
a

there

rear

guide

damper

The

secured

illustration

the

cage.

the

exhaust the heated
door mounted exhaust

air

downward

mechanism

plastic/sheet

absorbent

noise-reduction

maintenance.

cabinet

the

further

MPS

motor/blower

and

rear.

lined

cooling.

regulators.

sufficient

the

air

material

that

metal

that

deflects

plenum

allows

is
to

muffler.

the

3-65

air

flow

the

CPU

cabinet.

AIR MUFFLER
AIR MOVERS ——L]

BACKPLANE

CARD

EXHAUST

POWER

CONTROL

T 1/0 PANELS

\
AIR FILTERS

INTAKE AIRFLOW
MKVE6-1239

Figure

3-24
IV

Air
3-66

Flow Path

EK-KA88K~-TD-PRE

SECTION 5
CLOCK MODULE

CHAPTER

INTRODUCTION

1.1

BASIC

OPERATION

The

clock

generator

the

1left

and

adapters.
by

the

generates

right
is

located

PRO-38N

and

CPUs,
on

console.

distributes

the
the

memory

clock

basic

(CLK)

block

the

module

diagram

PRO-38N

shown
clock

controls

the

period,

the

block
and

clock

generator

diagram,

clock

burst

count

but

are

written

via

the

located

the

CLK

module.

fourth

status

allows

the

are

also

read

actually

interface.)

performs

Subsystem

via

the

Technical

output

console

system

copy

with

The

generator

clock

timeout

module

counters

can

each

have

also

the

CLK,

the

CPUs,

CLK

Main

and

1-1

CLK,

having

one

slow

within

the

functions

the

only

copy
clock

one

Console

CLK

clocks

same
to

and

I/O

CPU

modules

clock.)

increment

adapters.

I/0

system

controller

two

clocks

and

(not

system

CPU

SLC1).

Vv 1-1

used

sequence

operation.

adapters

Free-running

RAMs

sequence

operation.

Free-running

used

Also

used
clock

module

and

connect

by NBI).
used

types

in
the

destination

the

used

controller,

adapters

synchronize

CLK

multiplexer

bits;

status

System Clocks

system

I/0

memory

(The

generator
are
listed
clock are transmitted on

than

memory

synchronize
F

status

Function
B

also

clock/timeout

clock

and

clock
is

clock
each

generates

Table
Clocks

the

which

interface.

data

control,

Description.

1in

described

system clocks generated by
Table
1-1.
Several
copies
backplane,

are
(the

I/O

Figure

registers.

clock

examine

interface
are

The

module.

console

(the

interface,

PC350

the

The

console

the

controlled

shown

three

registers)

generator,

these

using

these registers

clocks

and

1-1.
The

system

subsystem,

write

(SLCO

and

CLOCK (CLK)

MODULE

VAN

SYS CLK
DISTRIBUTION_

——»

GENERATOR

—p

Yyv

cLoc

OSCILLATOR

PHASE

REFEEENCE

SYSTEM

CLOCKS
B
>

(SEE

TEXT)

CLK
SAMPLE

GATES

PERIOD

SLOW CLOCK ENABLE

CLOCK CONTROL LOGIC

CLK CONTROL REG

HARBINGER
MICROMATCH

CLK BURST CNT REG

SCOPE SYNC

CLK PERIOD REG

>
Z

A
CLOCK

STATUS

SYNC

DISABLE STALL

SELECT

|BCLK

MODULE CLOCK

CONSOLE

INTEé%iCE

(SEE NOTE)

CLK/T.O. STATUS REG

DISTRIBUTION
SYSTEM
INT

CLOCKS

CLKS
]

SAMPLE

STALL

(SEE_NOTE)

INTERVAL

DATA/REG

|STEP

SLOW MODE

CONSOLE

TO/FROM
CONSOLE

NOTE:

CONSOLE INTERFACE

AND CONNECTIONS TO

SYSTEM DESCRIBED IN
CONSCOLE SUBSYSTEM
TECHNICAL DESCRIPTION.
SCLD-201

Figure

1-1

Clock Generator

(and Console

Interface)

on Clock

Module

1.2

BASIC

COMPONENTS

The

clock

generator

Oscillator

The

Phase

generator

Clock

distribution

Clock

control

oscillator

second
that

clock

distribution

from

the

main

(gated)

started,

the

system

clocks,

free-running
slow

ENAB,

thus,

they

are

System

clock

produces

six.
in

will

started,

the

normal
clock

change

the

periods

ranging

The

period

SLOW

the

reference

and

shown

3.28

milliseconds

140

CLOCK

clock
at

and

the

produce
(from

clock

plus

duration.

and

the

two

PHASE

The

clock

with

PHASE

several

These

clocks

may

control

logic.

The

CLK.

clock
the

free-running
A

and

generator,

65,536

copies

logic.

phases)

CLKs

with

the

called
It

that
main

Figure

1-2.

the

and

the

SLOW

CLOCK

derived

from

are

generated)

system

The

reference

clocks

clock

phase

clock

(ungated)

bursted.

when

generator

frequency

is normally 120 MHz, this results
trequency of 20 MHz and, thus, a normal

ns.

However,

clock

the

frequency

down

ENAB,

frequency.
the

used

produce

the

control

dividing

1is

phase).

clock

every

reference
from

CLK

the

reference

period

bursted

system clock

system

logic

synchronized

«clocks

Because

stopped,

timing

the

PHASE

gate

the

for

and

turn,

and

produced

once

components.

longer

clocks,

CLK,

that

but

control

(from

clock

also

basic

generator,

PHASE

circuits

generated

(asserted

and,

CLK

clock

CLK

phase

clock

stopped,

distribution

following

reference

PHASE

system

clock

phases,

circuits,

signals

the

circuits

the

similar

logic

generates

component,

nonoverlapping

The

AND TIMING
consists

normal

console

produce

system

ns.

derived

from

This

signal

system

clock

v 1-3

system's

can

clock

'
B

CLK,

also depends -

asserted

rate.

once

every

REFERENCE
CLOCK

B PHASE

W PHASE

AN
B

AN
N

/
/S

A PHASE

(

SCLD-202

Figure

1-2

System Clock Timing

v 1-4

Diagram

1.3

CLOCK

CONTROL

(BY

The

CC.TSOLE)

PC350

console

can

control

following

Stop

Start

the

clocks

Burst

the

clocks

the

clocks

(burst

Single-step

Enable

the

clocks

Change

the

clock

the

clocks
to

period

The

Single-step

Disable

console

CLOCK
CPUs,

can

ENABLE
memory

The

CLK

also

output

set

CLK

stalls

255

(when

left

assert
to

I/0

the

clocks

are

controlled

generator.

mainly

Control

bits

the

this

clocks

flags

by
in

without

the
the

This

the

given

the

clock

definitions

burst).

clock

clocks

clocks.)

period

Clock

1-3

given

count

through
Table

burst

CLK)

clock

errors

force

the

them
a

the

during

stop

SLOW

done

after

slow

Figures
are

to
or

clock

burst

address)

registers

the

generatcr's

control

the

number

and

having

three

clock

CLK

allows

and

timeout

generated

The

CLK

the

CPU)

are

asserted.

VBus

also

specified

single-steps

clock

generate

the console to start the main system clocks
and
unconditionally
(when
a
micromatch
occurs)
number

clocks

free-running

right

adapters.

timeout

that

and

one

changes

(by

used

(also

only

pairs

micromatch

condition.

clock

system

continuously

controller,

diagnostics
error

the

burst

stop

period)
7.

(gated)

(unconditionally)

CLK)

main

ways:

allow
either

specified

control

bit
in
continuously

system

burst

clocks

count

one

period -is determined by
the
value
Bit format for the three registers

1-5.

1-2.

vV 1-5

Clock

control

bit

Most console control of the system clocks affects both CPUs.
is,

clock

the

outputs

That

each CPU from the clock generator are

synchronized with each other and are not independently controlled.
unconditionally stopped and then
are
when clocks
For example,
(the clock period changed),
restarted at a different frequency
in both CPUs stops and then starts agai n at the
sequencing
and
Similarly, clocks in both CPUs singledifferent rate.
is
CLK
B
the
only
also true when
1s
This
together.
burst
case,
this
In
single-stepped during the loading of a VBus address.
o

OLCH

the

single-stepping

controlled

not

it is controlled by a bit in the

in the console

VBus

clock

control

generator

interface.

in
The clocks also stop together when a stop on micromatch occurs
a
in
value
microPC
A micromatch is when the current
either CPU.
.
IBox)
the
1in
(also
CPU's IBox equals a preloaded microaddress
condition, in addition to stopping the clocks when enabled by
This
the console,

sync on

the

always causes the clock generator to generate a

scope

backplane.

it
Before the console unconditionally stops the clocks, or before
burst,
clock
a
the clocks to stop on a micromatch or after
enables
as
it must place the memory controller and some I/0 adapters, such
console
The
NBI, into a slow (unpipelined) mode of operation.
the
signal
The
does this by asserting a SLOW MODE signal on the NMI.
control bit in a console
a
sets
console
the
asserted when
is
interface register

(control register 1).

Another early-warning signal, HARBINGER,
the

is asserted on the NMI

clock generator hardware just before the clocks actually stop.

free-running
the
sequenced by
1is
which
The memory controller,
uses the signal to block its
clocks,
the gated
not
and
clocks
condition
clock
stopped
the
simulate
and
clocks
free-running
This signal is
1in the CPUs and other system components.
occurring
allow
to
also deasserted by hardware just before the clocks start

the memory controller to unblock its free-running clocks.

1.4

CLOCK

One

type

the

when

STALLS
of

system

stalling

cache

made.

appropriate

CLK

with

The

CCS

generator.

These

transmitted
has

its

itself.

(Refer

Although

the

assertion

done
the

the

during

system

generated

1.5

CLOCK

console

There

are

main

the

clocks

left

Two

other

the

circuits

clock

for

system

each

clocks

Every

module

CLK

module

the

can

writing

that

1loaded.

0).

all

bits

This

the

The

stalls

prevent

control

system

STALL

could

occur

its

done

clocks

signal

during

the

disabled.

clock

Bit

definitions

are

stopped,

the

either

cleared)

writes

each
a

indicate

clock

flag

the

left

whether
or

format

Table

the

because

faulty

are used
or right

reading

shown

the

1-3,

One indicates
whether
others, valid only when

clocks
of

stopped

micromatch

as flags by
CPU is hung

at
in

the console
in a stalled

the
the

to
(A

located
1in
the
console
interface.
the flags and (if the flags are

reads

bit

control

stall

the

cleared

set
when
period), it
the

given

burst

control

flag

still

indicating

bit

CPU.

bits

set,

status

generator status bits.
clocks are stopped.
The

specified

right

generator

clock

bit

timeout

1inhibits

generator.

unwanted

CLK) state.
The
flags
are
Periodically,
the
console

ensure

are

determine

Once

status

system
a

sets

is,

can

gating

the

including

STALL,

CPUs

determines

four

the

not

That

access

STATUS

1-6.

end

receive

clock

the

done

distribution

assert

(control

and

The

not

This

logic

1-1.)

the

microcode

microcode, 4

clock/timeout

Figure

not

initialization

process

The

does

the

until
CPU

circuits

Figure

written.

signal.

that

CPUs.

interface)

stalling

STALL

clock

when

the

both

console

read

sequencing
in

affect

temporarily
the

circuits

either

interface

(and

backplane

console

not

CPU

stopped

distribution

again

console
are

stop

clock

asserting

are

own

does

some

module

immediately

CLK)

CLKs

control

CLK

(by

STALL

module.

cannot

sequencing
be

clock

only

when

read
again
indicates
a
CPU.

v 1-7

associated
the

by the
hung

stall

CPU

The

ends.

console (at
state
with

control

progress.

Thus,

the end of
the
set

the
bit

ADDRESS

CONSOLE

READ/

(HEX)

WRITE

CLOCK CONTROL REGISTER
07

NOT USED

-SLOW CLOCK

‘ -RIGHT

STOP

CLOCK

| SOMM

HOLD

-LEFT

-BURST

SOMM

ENABLE
SCLD-203

Figure

Table

1-2

Clock Control

1-3

Clock Control Register Bit Descriptions

Bit(s)

Description

<KT>

Stops clock. When set to 1, stops main system clocks.
When set to 0, starts main system clocks. Initialized
to

<6>

Enables

console.

left CPU to stop on micromatch

Initialized

<5>

Enables

<2:0>

(when set

to 0).

console.

(when set

to 0).

console.

Enables clock to stop at end of clock burst specified
by burst count register (when set to 0). Initialized
to

<3>

right CPU to stop on micromatch

Initialized

<4>

Holds

on NMI
Not

console.

(force assertion of)
(when

set

to 0).

used.

vV 1-8

slow clock enable signal

1Initialized

by console.

CONSOLE

Agopsqgss

(HEX)

READ/

BURST COUNT REGISTER

WRITE

CLOCK BURST éOUNT |

128i64l32!161

NOTE:

BURST COUNT CAN BE

1 TO 255 FOR NORMAL OPERATION.
BURSTS 256 CLOCKS BUT BURST DONE FLAG
IN CLOCK/TIMEOUT STATUS REGISTER IS SET TO 1
BEFORE (AS WELL AS AFTER) CLOCK BURST.

A COUNT OF 0

SCLD-204

Figure

ESB'S%E

(HEX)
E

1-4

Burst

Count

READ/

CLOCK PERIOD REGISTER

WRITE

327

[

CLOCK PERIOD (NZ
16

’

LOW FREQ
SELECT

NOTES:

SYSTEM CLOCK FREQUENCY =

SYSTEM CLOCK PERIOD = 990

VALUES

(N
+ 1)

OF N FOR SPECIFIED

.25

NANOSECONDS

LOW AND

HIGH

SYSTEM CLOCK FREQUENCIES ARE GIVEN

LOW FREQ

SELECT

CLOCK

FREQUENCY

TO 99

14.25

TO 99

MHZ TO 25

MHZ TO

12.5

RANGE OF

BELOW.

CLOCK

MHZ

PERIOD
MHZ

MHZ

NS TO 40

140

NS TO 80

SCLD-205

Figure

1-5

Clock

vV 1-9

Period

CONSOLE

|
CLOCK/TIMEOUT STATUS REGISTER

READ/

ADDRESS

(HEX)

WRITE

|
NOT USED

CLOCK
OFF

LEFT STALL

MICRO|
MATCH |

-RIGHT

TIMEOUT

-BURST

-LEFT

MICROMATCH

RIGHT STALL

DONE

TIMEOUT

SCLD-206

Figure

Table
Bit({s)
<7>

1-3

1-6

Clock/Timeout

Status

Clock/Timeout Status Register Bit Descriptions

Description
Clock

off.

1Indicates main

system clocks

are

turned

CPU.

off.

<6>

When equal

to 0,

indicates micromatch

left

<5>

When

indicates

right

<4>

Burst done. When equal
has reached a count of

<3:2>

<1>

<0>

Not

equal

to
0,

micromatch

indicates

burst

CPU.

counter

used.

Left stall

timeout.

stall

state.

Right

stall

atall

state.

timeout.

Indicates

v 1-19

left CPU hung

right

CPU

in A CLK

hung

A CLK

CHAPTER
FUNCTIONAL

2.1

DETAILED

detailed

2-1.

BLOCK

block

Clock

DESCRIPTION

DIAGRAM

diagram of

generator

input

the

clock

and

output

generator
is

defined

shown
in

Figure

Tables

2-1

and

2-2

2.,1.1
The

Oscillator

oscillator

source

phase-locked

the

consists

(250

1input

kHz),
loop

and

circuit

(REFERENCE

crystal-controlled

1low

phase-locked

circuit.

multiplies

CLOCK)

the

low

1loop

frequency

system

clock

frequency
to

phase

The

produce

generator.

The low frequency is normally multiplied by a factor of (N 1) X
&6,
where
N
1is the value loaded in the clock generator's clock period
register.
Besides
the

allowing

value

REFERENCE
the

CLOCK

the

derived

frequency

1in

the

free-running
rest

from

the

addition

REFERENCE

its

seven

CLOCK

SYNC

together with

outputs

from

the

REFERENCE

CLOCK

the

interval
(and,

from

the

v 2-1

clock
the

sample,
a

phase

divided

copy

the

connect

system

1loop

clock)

MHz)

the

These

with

interface.
period

system

phase-locked

frequency

current

the

backplane

that

console

timer

thus,

changed.

the

(based
the

the

one

the

outputs

constant

clock

output,

located

with

hardware,

timer

to maintain

This

received

INTERVAL

controls

comparing

source

CLOCK.
1loop

frequencies

closely

continuously

CLK)

clocks.

interval

system

has

though

CLOCK

loop

frequency

phase-locked

system's
signals,

low

REFERENCE

clock

circuit

used

REFERENCE

phase-locked

crystal-controlled

clocks

different

N),

are
even

frequency

Phase

phase

the

Generator

generator

REFERENCE

nonoverlapping

circuits
single

distribution
and

and

output

copy

All

circuits.

2.1.3

Clock

Control

contrel

period

contains

1In

produced

counter,

burst

and

CLOCK

ENAB)

memory

2.1.4

the

Clock

clock

gating

Distribution

and

«clock

destination
he

PHASE,

PHASE

plus

to the
both A

control

the

free-running

the

clock

clock
PHASE

logic.

zero

produces

timeout
GATE

the

These

NMI

counters
The

and

the

are

transmit

from
end

system

consist

the

mainly

CPUs,

the

The

clock

(SLOW

the

CPUs,

the

ECL

memory

Several

(radially)

driven

clocks

from

control

the

signal

the

also
clock

start/stop

the

locaded

signal

(turned

PHASE).

counter,

itself.

distributed

PHASE).

from

two

Latch

1logic

PHASE)

levels
main

that

system

with

outputs

copies

each

that

drivers

main

phases

logic

CLK,

free-running

system

copy

connect

CLK,

clock

clocks

are

gated

with

start,

stop,

and

but

and
also

single

CLK)

and

the

are

PHASE,

derived

GATE

burst

I/0
each

consisting

phases
A

that

controller,

module.

directly
and

phase.

control

count

counter

module

differentially

free-running

derived

clock

are

and

divide
the

Circuits

adapters,
pair

clock

circuits

clocks

the

as inputs
copies of

the

adapters.

signals

the

system

burst

error

I/O

transmit

system

slow

counter

circuits

that

generate

PHASE

clock

decrements

distribution

the

burst

The

and

(turned

the

the clock distribution
on the backplane.

clock

well

used

the

increment

clock

GATE

enable
clocks

The

used

slow

controller,

generates

and

The

are

and

logic.

burst.

each

contains

control

clock

registers
and

copies are used
addition, single

that

start/stop
count

shift
six

Logic

logic

burst

of
by

phases,

copies

are

clock

four

PHASE

clock

mainly

frequency

PHASE.

The

consists

CLOCK

2.1.2
The

from

GATE

clocks.

SYSTEM

EXTERNAL CLOCK

C':EXTERNAL CLOCK ENABLE
» TEST DIVIDER

{

TEST PHASE GENERATOR

i
BEFERENCE | PHASE

PHASE-LOCKED
XTAL |-250 khz | FPHAS

TESTER

]

CLK

PERIOD

L.F A CLK

«<8:1> ¢——u—] PERIOD

<7:0>

|,..—:
-

GATE

—

B PHASE

%
.

A GATE
B GATE

_PHASE

B GATE

€—¢
A

——————
(. ENABLE MATCH)

(ENABLE BURST)

———®
(R ENABLE MATCH)

p—M

SLOW COUNT HOLD

WA CLOCK

PERIOD

sToP

CLK CONTROL REG
|

5
>—>—PF

B CLK

-—»

4—A CLK

4—B CLK

CONTROL |3 > ———)

73>

S fiJ

-—>»

stary

»
>

» CONSOLE START

CLK PERIOD HEG,]

|
L

L
»
[ >
[,

20 P B CLK
——

L~ »

A _PHASE

OLOCK CONTROL

SYSTEM

? CLOCKS

PHASE

———p

——>—» A CLK

4
TCD’—D--%/—;
W CLK
W

clock ~ (CLK SAMPLE)

A PHASE

|—p

INTERVAL SYNC <s:o><—7zJ7

TO
CONSOLE
NTERFACE

/‘,

i —» >—¢—®»F A CLK

___l

—B
A

———»

GENERATOR

OSCILLATOR

Toonom
)

CLOCK

DISTRIBUTION

WR CLOCK CONTROL

INTERNAL CLOCKS

—F A CLK
«4—F

—»

4———— FROM CLK MODULE

CLK

CLOCK

DISTRIBUTION

4—CLOCK INIT

—>\

» NMI HARBINGER<3:0» (TO MCL, 1/0 ADAPTERS)

—»

——p

BURST

COUNT
0>

BURST

CNTR

HARBINGER

UPPER_COUNT

LOWER COUNT

STOPPED
L

(FROM

SCOPE

RIGHT

SEQ

MODULE)

SYNC

(TO

BACKPLANE)

MATCH

IBURST COUNT REG.

——pWR CLOCK CONTROL

(FROM LEFT SEQ MODULE)

MICROMATCH

» R SCOPE SYNC

R
\_fi/_‘

——pWR CLOCK PERIOD
-——WA BURST COUNT

MCROMATCH

A MATCH

BURST
DONE

SLOW

» NMI SLOW CLOCK ENAB (TO MCL, 1/0 ADAPTERS)

CLOCK

WR BURST COUNT

CNTR

TEST SLOW CLOCK}*___ M(TO/FROM MODULE TESTER)

COUNTER

TEST

8
WR CLOCK
(FROM

REG<2:4

CONSOLE

INTERFACE)

CONSOLE

(FROM

DATA<7:0>

CONSOLE

INTERFACE)

STEP

BOLK

(FROM CONSOLE INTERFACE)

(To co~s0LE<7|é3r>ERFACE)

SCLD-333

Figure

2-1

Clock

Generator

(Detailed

Block

Diagram)

Table

Signal(s)
CONSOLE

2-1
Number

DATA

<7:0>

Clock

Generator

Inputs

Description
Transfers
~Aananmla

'in-l-ev-F-:hg

CONSsSCiLe

data
whaoan

1ncerra’le

written

from
o

wien

~1Ae

C.Lo6C

the

console.
WR

CLOCK

REG

<2:0>

Loads

addressed

clock

when

written

console.

three

lines

are

outputs

address

decoder

The

console

interface.
WR

CLOCK

REG

LOADS

<2>

Clock

<1>

Burst

period

Clock

STEP

BCLK

Causes

one

Output

VBus

in
CLOCK

console

logic

MICROMATCH

CLOCK

ENAB

clock

console

left

Asserted

clock

Asserted

output

source

REFERENCE

CLOCK

clocks.

Used

device

during

test/repair

VvV 2-4

from

to
by

detected

micromatch

CPU.

Enables

interface.

micromatch

CPU.

generated.

period

Indicates

right
EXTERNAL

control

Asserted

Indicates

MICROMATCH

CLK

interface.

Initializes

INIT

control

CPU's

IBox.

detected

CPU's

IBox.

external

produce
and,

thus,

module

test

manufacturing

procedures.

system

Table

2-1

Signal(s)

Clock

Generator

Number

EXTERNAL

CLOCK

1IN

Inputs

(Cont)

Description

External

test

clock

device.

source

See

from

EXTERNAL

module

CLOCK

ENAB.

TEST

PHASE

GENERATOR

Initializes

(An

CLK

signal

five

SLOW

CLOCK

with

CLOCKS

occur.)

device

during

Used

during

REFERENCE

Used

by module
manufacturing

test

procedures.

Initializes

zero.

after test
and deasserted
REFERENCE CLOCK,

additional

test/repair
TEST

generator.

generated

asserted

coincident
and

phase

slow

clock

module

counter

test

manufacturing

test/repair

procedures.

Table

Signal(s)
System

2-2

Clock

Number

Generator

Description

Clocks
CLK

Gated

clock

CLK

Gated

clock

CLK

Free-running

clock

CLK

Free-running

clock

CLK

Used

INTERVAL

SYNC

<6:0>

clock

(free-running)

keep

console

with
CLK

Outputs

PERIOD

<6:1>

Six

interval

interface

system

outputs

Used

SYNC

<6:0>

interval

timer

interface

VvV 2-5

synchronized

INTERVAL

system

timer

clocks.

high-order

period

clock

with
keep

console

synchronized

clocks.

device

with

Table

2-2

Signal(s)

CLK STATUS

Clock
Number

<7:4>

Generator Outputs
Description

Clock

CLK

HARBINGER

<3:0>

generator status

bits

clock/timeout status register
(outputs of a data multiplexer)
in console interface.

——

NMI

(Cont)

STATUS

" — —— —

b ——— —

STATUS

BITS

—— —n

— v —

<T7>

CLOCK OFF

<6>

LEFT

<5>

RIGHT

MICROMATCH

<4>

BURST

DONE

Early-warning
controller

MICROMATCH

signal

that

clocks

memory
are

about

to stop (when signal is
asserted) or start (when signal
is deasserted).
L.

SCOPE

SYNC

Scope sync signal asserted on
backplane when micromatch occurs
in

R SCOPE

NMI

SYNC

SLOW CLOCK

ENARLE

left

CPU.

Scope sync signal asserted on
backplane when micromatch occurs
in right CPU.

Slow

clock

timeout

used

controller,
TEST

DIVIDER

counters

and

I/O0

increment
CPU,

memory
adapters.

Output of divider circuit in
oscillator's phase-locked loop
circuit. (Signal is a copy of
DIVIDED ACLK.) Used by module
test

device during manufacturing
test/repair procedures.

COUNTER TEST

Overflow

(borrow

output)

from

eight high-order stages of
16-bit slow clock counter.
by module

test

manufacturing

device

Used

during

test/repair

2.2

CLOCK

GENERATOR

INITIALIZATION

At powerup, DC LO asserts CLOCK INIT, which loads
a
value
of
56
into
the
clock period register.
Also, at powerup, the oscillator
starts to generate the system
c¢lock
phases.
The
clock
period,
determined
by the value preset in the clock period register, is 70
ns.
The
console
lowers
the
<clock
period
(increases
clock
frequency)
to
its
normal
value during the system initialization
sequence

that

follows

powerup.

With the system clock phases running, the clock generator
1is
also
producing
the
free-running
clocks.
This
allows the console to
access the clock (and console interface)
registers
during
system
initialization.
(The
console must start, stop, burst, and change
the frequency of the clocks during the loading of microcode and the
many
other operations performed.) When system initialization ends,
the clock generator is left in the following state:
@

Clocks
running
register)

(STOP

Clock period

set

CLOCK

cleared

1in

clock

<clock

control

period

bits

set

clock

control

ENABLE

set

clock

control

(-SLOW CLOCK HOLD set

clock

control

Micromatch

stop disabled

(-SOMM

Clock

bursts

disabled

(-BURST

Slow clock

running

vV 2-7

SYSTEM

CLOCK

clock

controlled

the

circuit is used
of
frequencies
register.

Refer

Phase

Low

Voltage

Low

Divide

loaded
Whenever

and

not

the

DOWN .
clock

The
sample

phase
The

low

pass

the

VCO

output
that

the

following

components.

period

difference

KkHz

This

been

7-bit

low

divided

counter,

clock

period

clock

sample

count

between
asserts

than

clock

counts),

frequencies

two

signals,

1is

the

crystal-controlled
two

divided
or
a

crystal-controlled

outputs

the

one

again,

connecting

on whether the
(UP
asserted)

the

CLK).

ACLK.

the

that

decrementing

DIVIDED

indicating

DOWN

(after

starts

system

called

detector

and

has

the

exists

asserted)

that

system

crystal-controlled

sample

counter.

asserted depends
lower
frequency

the

are
or

system
higher

frequency.

proportional

the

detected.

filter

the

(by

ACLK,

phase

signal
has a

250

from

signal

DIVIDED

the

divided
This

the

(VCO)

clock

reaches

clock

the

phase

phases.

the
system

divide

counter

the

integrates

the

output,

(or

1input

contains

oscillator

compare

difference

voltage

The

range
period

Counter

with

(DOWN

duration

wvalue

same,

frequency

The

the

and

circuit.

Operation

circuit

decremented

phase

1loop

divider

the

detector.

frequency

filter

asserts

phase

period)

2-2,

controlled

range

the

from

clock

detector

pass

with

reloads

Loop

source

continuously

Figure

loop

detector

frequency

system

phase-locked

VCO.

which

VCO

LOW

RANGE

output

generator

(The

the

UP/DOWN

signals

voltage

determines

The

high

divides

output

frequency

divided

control

by
six

divided
bit

paragraph.)

phase

thus,

oscillator's

Phase-Locked

frequency

(and,

as a frequency synthesizer to produce a wide
determined
by
the
wvalue
N
in the clock

phase-locked

The

CONTROL

)

2.3.1
The

PERIOD

frequency

2.3

System

1is

two)
to

set

produce

the

wave.

REFERENCE

the

when
as

frequency

square

produce

two

This

VCO

CLOCK

the

system

clock

the

clock

period

described

1in

the

PHASE-LOCKED LOOP

SYSTEM GLOCK
LO

250 KHZ

PHASE

DETECTOR

RANGE

DIVIDER
1 Low

PASS
FILTER

DOVWN

(DC)

VGO

DISTRIBUTION

5\
=

Chock -

PHASE

GENERATOR

SLoCKS

> z
o

6-C A

CNTR

DIVIDED ACLK

INTERVAL

TIMER

J (INTERVAL

(CLK

F A CLK

SYNC)

PERIOD)

LO
CLOCK
PERIOD

7
<4~

7
/]

4—~——]

RANGE SEL

SCLD-335

Figure

2-2

Simplified

Clock

Frequency

Control

Circuitry

At poweron,

the clock period register

initialized to a value

56
(by
CLOCK
INIT,
which
1is asserted by DC LO).
Also, the VCO
begins generating the REFERENCE CLOCK; the
phase
detector
starts
generating
UP
or
DOWN
signals
to
bring
the
REFERENCE
CLOCK
frequency to a
value
where
the
divided
system
clock
and
the
crystal-controlled
frequency
are the same.
When this occurs, the

phase-locked

loop

locked and

(for N = 56 and the LOW

RANGE

bit

cleared)
the
REFERENCE CLOCK frequency is 85.5 MHz and the system
clock frequency is 14.25 MHz (70 ns clock period).
Further
phase
detector
outputs
are minimal, compensating only for slight drifts
in the clock frequency.
Of course, when the clock period
register
is
loaded with a new value of N, the phase detector outputs (which
are pulses) sharply increase in duration
and
then
decrease
over
time as the clock frequency quickly approaches and locks to the new
value.

The relationship between N,
the
system clock frequency is derived
At

the

input

the

DIVIDED

phase

1low

frequency

source,

below.

detector:

CLK

FREQUENCY

LOW

FREQUENCY

CLOCK

FREQUENCY

250

kHz

SYSTEM CLOCK

FREQUENCY

SOURCE

Substituting:
SYSTEM

Thus:

v 2-19

250

kHz

and

the

can

seen,

the

crystal-controlled

its

value

also

determines

system

clock

can

smallest

250

kHz

the

system

normal

the

clock

frequencies

99).

The

bit

can
divider
range

within
12.5

can

factor

diagnostic

clock

the

«clock

frequency
range
or

operating

purposes,

any

the

1is,
of

the

course,

made

the

system

MHz

range
LOW

clock

the

RANGE

the

VCO

range

range.
1),

still

control

That

range
lower

operating

are
is,

regardless

VCO.

MHz

half
the

to
of

system

how

the

clocks.

the

console

sized

increment

clock
change

when

a
bit

the

program
in

the

introduce
period

component

v 2-11

new

decrement

may

falls

within

The
low

transient

not

The

malfunction.

made
the

be
as
is

normal
can
the

clock

changing

change

cause

value

need

restriction

normal,

period

can

only
to

running.

clock

change

loads

clocks

range.
from

clock

system

simply

The

frequency

operating
no

divider

other

kHz

produce

control
This

with

operating

250

the
loop;

Period

range

RANGE

period.

normal

period,

specified

LOW

memory,

frequency

resulting

should

low,

low

the

MHz

values

period

and

the

the
the

Clock
clock

first,

there

clock

divided

Changing

generator's
that

range

14.25

low

the

can

the

always

long

that

The

the

and,

that

output

only

That

kHz

Note

are

stopped

debug

size.
250

range.

49).

frequency

and

frequencies

they

mainly

not

specified

decrement

changing

phase-locked

the

in the clock period register causing the
1low
divide
the
VCO frequency by two.
This gives a
specified

change

for

set

clock

2.3.2

source

step

multiple

the

1its

frequency

some

increment

what
VCO

the

generated

system

MHz

frequency

that

frequency

operation,

for

only

frequency

limiting

However,

1low

reference

to
of

cause
system

sequencing

CPU,

2.4 SYSTEM CLOCK START/STOP/BURST CONTROL
Figure 2-3 shows the clock control logic that

starts,

stops,

and

bursts
the
main
system clocks.
(Timing is shown in Figure 2-4.)
The major control element is a latch circuit
that,
when
cleared,
asserts the gating signals (A GATE and B GATE) that allow the clock
distribution circuits to transmit the main
system
<clocks
on
the
backplane.
This latch, when set, stops transmission of the clocks
and asserts the CLOCK OFF bit in the clock/timeout status
register
that

can

read

the

console.

The first clock generated when the clocks are
started
is
A
CLK.
The
last
clock
generated
when
the clocks are stopped is B CLK.
Before the last B CLK (and when the last A CLK occurs),
the
clock
control
1logic
asserts
HARBINGER
on the NMI.
This 1is the signal
used
by
the
memory
controller,
which
is
sequenced
by
the
free-running
<clocks,
as
a clock blocking signal.
The controller
can
then
simulate
stopped
<clock
operation
even
though
the
free-running
clocks continue to be generated after the main clocks
are stopped.
HARBINGER, when it is deasserted, also serves
as
an
early-warning
signal that the clocks are about to start.
When the
clocks are restarted, HARBINGER is
deasserted
by
a
free-running
clock
(F
A
CLK)
one
system clock period before the first A CLK
occurs.

Besides requiring the assertion
of
stop,
the
memory
controller
must

HARBINGER
also
be

before
in
a

the
clocks
slow mode of

operation as discussed in Chapter 1.
That
1is,
the
console
must
assert
SLOW
MODE on the NMI by setting a contrecl bit in a console
interface register (control register 1).
(Some I/0
adapters
such
as
the
NBI must also be set to slow mode before the clocks stop.)
The

SLOW

MODE

microseconds

signal

before

must

the

asserted

clocks

stop.

v 2-12

the

consocle

least

four

2.4.1
The

Starting

console

clock

the

control

CLOCK

Clocks

starts

OFF

asserted.

the

clocks

latch
The

This

enabling
clocks

the

burst.

Once

console

clocks

2.4.2
The

end
1is

for

the

Stopping

console

CLOCK

bit

the

console,

Clocks

stop

the

1in

the

clock

first,

sets

the

CLOCK

GATE

however.)

OFF

latch

the

and

GATE

remain

the

clear

CLOCK
pulse

the

way

STOP

that

the

clears

until

stop

only

bit

signals

running

micromatch

stopped,

again

STOP

START

stopped

condition,
to

restart

CLOCK

the

bit.

Unconditionally

can

asserted

GATE

will

unconditionally
the

clearing
generates

clock

any

control
Setting

time

STOP

preventing

signals.

V 2-13

just

CLOCK

setting

the

(SLOW MODE
asserts

assertion

STOP,

the

STOP

must

GATE

which

and

A PHASE

PHASE
GENERATOR

START/STOP
J]>_LI__\

CLOCK CONTROL REGISTER

STOP
CLOCK

LEFT
SOVM

RIGHT
SOMM

CLK

CLOCK OFF

CONTROL

[

B PHASE

LATCH

)

(WHOA)
START
(PULSE) oleiEAR

(CLOCK OFF)

BURST STOP
ENAB
CLK EN

N GATE
S
:

" |l>*4__.74,.|>A GATE

B GATE

_:::j::>F_~W FF

—>—1——»
B catE

¥1-¢ A

WR CLOCK
CONTROL

R MATCH

UPPER COUNT

BURST
CNTR

| LOWER COUNT,,

D—1—<> Narencer

(CLOCK QFF)

STOP

--------D
~£~ (BURST CNTR=0)

L‘D——” L. SCOPE SYNC

ALLOWS BURST

COUNTER TO

R MICROMATCH

R MATCH <

LOAD WHEN

BURST COUNT

—-—p R SCOPE SYNC

B _HARBINGER

STEP CLK
SCLD-334

Figure

2-3

Simplified Clock Start/Stop/Burst Control Logic

CLOCKS STARTED

CLOCKS

START

BURST COUNTER

< R EURSTING eLocKs

( BURST COUNTER = 0 )

(STOP CLOCKS)

(LATCH CLEARED)

STOP/L

CLOCK OFF
LATCH (WHOA)

yaaN

A PHASE M

STOPPED

A GATE

MATCHR

MATCH/

B GATE

(ENABLE A CLK)

(ENABLE B CLK)

ACK /TN

HARBINGER

CLOCKS ABOUT
TO START

CLOCKS ABOUT
TO STOP

SCLD-207

Figure

2-4

Start/Stop/Burst

v 2-15

Control

Timing

Diagram

2.4.3 Stopping the Clocks on Micromatch/Scope Sync Generation
The console can enable the clock control logic to stop
the
clocks
when
the microPC in the left or right CPU is at a specified value.

This condition,

a micromatch,

micromatch

though

generate

a scope

even

sync.

the

also causes the clock

The scope sync

clocks

are

not

control

1logic

always generated by a

enabled

stop.

To cause a micromatch (and scope sync) on a specific microPC value,
the
console
must load that value in the CPU's micromatch register
located in the IBox.
If the console wants to stop the clocks
when
a micromatch occurs, it asserts SLOW MODE and clears the CPU's SOMM
(stop on micromatch) bit in the clock control
register.
(A
SOMM
bit is asserted when equal to 0.) The loading of the microPC value,
the assertion SLOW MODE, and the clearing of the SOMM bit are
done
with

the

clocks

turned

off.

Once the clock is turned on and if a micromatch occurs,
the
CPU's
IBox
asserts
a MICROMATCH signal.
This signal (one for each CPU)
generates the
scope
sync
(there
1is
one
for
each
CPU).
The
micromatch signal also sets the CLOCK OFF latch to stop
provided the corresponding SOMM bit has been asserted.
and scope sync timing is shown in Figure 2-5.

After the clocks stop on

a micromatch,

the

the clocks,
Micromatch

MICROMATCH

signal

1is

normally
deasserted.
If it is still asserted when the clocks are
restarted (indicating the microinstruction has branched to its
own
microaddress), the clock control logic generates one pair of system
clocks, an A CLK and a B CLK, and stops the clock again.

ACLK_/_\

VRN

B CLK

— CLOCKS STOP IF

STOP

ON MICROMATCH ENABLED

MICROMATCH

SCOPE SYNC

/TN
SCLD-208

Figure

2-5

Micromatch

and

Scope

Sync

Timing

Diagram

2.4.4

Bursting

the

generated.

the

burst

frequency

Clocks

clocks

causes

clock

occur

cycle

specified

burst

asserts

the

burst

clock

the

control

value

During

starts

clock
When

number

burst,
the

clocks

previously

OFF

latch

The

console

BURST

status

set

are

stopped

The

stop

counter

when

the

its

clocks

is generated.
clock burst as

the

BURST

which

the

ENABLE

can

burst

simply

counter
zero

is
and

end

burst

has

status

the

count

each

clock

the

BURST

ENABLE

control's

CLOCK

specified

reading

the

during

the

restarted.

the

clock/timeout

burst

and

the

clocks.

micromatch

clocks

burst.

ended
bit

load

loaded.)

that

clock

another

restarting
by

with

the

any

the

decremented

and

starting

(indicating

console,

bit

count

current
are

the

bit

the

clock

first

count

generate

console

bits,

count,

console
burst

ENABLE

the

period

automatic

clocks

and

1is,

clock

the

then

the

loads

clocks

burst

may

operation

the

The

that

BURST

from

Single-Stepping
equal

SOMM

counter

holds

when

the

generated),

the

CLK.)

frequency;
contents

burst

cycles

(This

burst

been

one

stopped,

loaded

clock

counter.

reaches

the

single-step

count

2.4.5

have

tell

Dburst

completes

the

count

(burst

the

burst

also

clock

the

The

burst

asserted

can

DONE

0.)

and

asserted),

clears

whenever

the

normally.

cycle.

bit

255,

control's

hardware

clocks

(Like

CLK

clock

already

and

number

current

the

not

equal

console

does

the

one

nominal

clock

the

with

(if

specified

when

from

the

performed

The

MODE

count

asserted

into

clocks,

SLOW

reloading

the

clocks

burst,

interrupted

the

burst

Clocks

just

single

clock

clock
cycle

The console loads the burst
described in Section 2.4.4.

vV 2-17

burst
(one

with

CLK

count

and

the
one

burst
B

CLK)

produces

the

2.4.6

Single-Stepping

the B CLK

During VBus operations,

shift

the

VBus

the console must single-step the B

data

address

into

the

CLK

modules.

CPU

The

as
clock
single-stepping of the B CLK is not done by bursting the
a complete clock cycle (generating both an A
single-stepping
when
the
in
Instead, the console sets a control bit
CLK and a B CLK).
immediately
is
bit
The
CLK.
B
STEP
<called
register
control
VBus
clock
cleared by hardware so that it remains asserted for only one
asserts
signal
CLK
B
STEP
the
logic,
control
clock
the
In
period.
one
causing
signals
the GATE B (but not the GATE A) clock enable
Timing

system B CLK to be generated.

A PHASE fi

STEP B CLK

is shown in Figure 2-6.

/m’\

/TM

B GATE

BCLK /TN

SCLD-20¢

Figure

2-6

Single-Stepping B CLK Timing Diagram

VvV 2-18

2.5

SLOW

CLOCK

counter

turned

asserted

errors

the

SLOW

wuse

the

are

return

module's

own

clock

frequency).

smaller
were

Because

its

the

clock

rate

way

and

can

force

the

SLOW

CLOCK

HOLD

bit
the

SLOW

quickly

CLOCK

set

continuous
in

the

BCLK

SLoW cLock

B 0K

/
\

its

maximum

value

65,536

for

(for

the

but

only

when

scheme

are

and

the
the

long

timeout

used,

forcing

control

0.)
the

the

periods.

clearing

(This

this

much
clocks

the system
The
console

65,536 B CLKS

has

system

signal

/~ \

ENAB

flag.

/" \

system

count

signal

Diagnostics
error flag.

clocked

use

comparatively

counter to
associated error

timeout

normal

the

period.
access

CLOCK

only

l‘

SLOW

)

counters

allows

necessary

CLK

detecting

example,

milliseconds

one

counters

range

assertion

/~\

asserted

ENAB

is
asserted when equal to
timeout condition and check

is,

clock

are

signal

value

timeout

the

clocks

ENAB

minimum

That

system

SLOW CLOCK

clock

counter

its

enable

clocking

causes

bit

3.28

would

slow

16-bit

2-7.

clocks

the

This

main

The

starting

every

through

the

reaches

ENAB

logic.

Figure

data).

This

asserted

CLK).

millisecond

than

state

signal

the

count

asserted

CLOCK

(once

counters

used

system

asserted

long
by

count

read

been

1is

counter

shown

seen,

that

the

new

CONTROL

control

clocked

AND

signal,

clock

after

begins

nexus

bus,

Timing

can

NMI

decrements

(it

just

(64K).

the

continuously

when

GENERATION

ENAB,

the

control

simulate

/7~
\

64K

SCLD-210

Figure

2-7

Slow

Clock

v 2-19

Timing

Diagram

2.6

CLOCK

Three

CLOCK
clock
SOMM

CONSOLE

console

command
period.
command

generated)
scope

sync

enables

can

The

generated

and

three

SET
a

CLOCK

2-3

Clock

also

clocks.
a scope

command

enables

and

commands

Console

SET

The

SET

change

the

The
SET
sync to be

only

TOMM

generated

affect

the

OFF

Turns

off

sets

CLOCK

clocks

CLOCK

Turns

NORMAL

Sets

CLOCK

SLCW

FAST

OFF

(Asserts

clock

deasserts
clocks.

CLOCK

OFF

ns.

MODE,

MODE.)

(Asserts

SLOW

control

period

(Loads

SLOW

control

SLOW

clock

deasserts

clock

period
CLOCK

Commands

clocks.

MODE,

SLOW MODE.)

its

normal

into

value

clock

Sets

clock

period

value

ns.

clock

period

(Loads

high

margin

into

Sets

clock

pericd

value

ns.

clock

period

its

(Loads

low

margin

into

the

command

Description

SET

and

the
(and

sync

console

clears

SET

SYNC

scope

clock

clocks.

clocks

micromatch,;

SET

system

the

CPUs.

Command

SET

main

start

command bursts
clocks to stop

a micromatch.
be

the

and

The MICROSTEP
enables
the

Table

SET

control

stop

microtrap

micromatch.)
both

COMMANDS

commands

Table

2-3

Command
SET

Clock

Console

CLOCK

<value>

Sets
to

MICROSTEP

clock

period.

period
range

Bursts

the

140

into

ns.

stepcount

Restricted

cycles

range

stepcount

are

one

clock

cycle

the

space

bar

causes

one

generated.

(single-step)
pressing

This

mode

carriage
the

clocks

generated

occurs

the

CPU;

equal

microaddress.

CPU's

cycle

specified.

pressing

clock

cycle

bar

exited

stop

the

After

(<cr>).

when

that

burst,

and
a

is,

scope

micromatch

when

the

specified

(Loads the microaddress
micromatch register and

asserts

the

control

v 2-21

clock

space

can

Enables

microPC

255

return

sync

burst.

to
is

specifies

the

single-stepped.)

last
be

clock

the
to

burst

(The clocks

(Loads

The

clocks.

specifies

Restricted

period

clock

value

clock

cycles.

The

nanoseconds.

number

generated

SOMM

(Cont)

Description

clock

SET

Commands

SOMM

bit

the

clock

Digital Equipment Corporation.Bedford, MA 01730