VAX 8800 System Technical Description Volume 1

This document, "VAX 8800 System Technical Description, Volume 1" (Preliminary Edition, July 1986), serves as a comprehensive technical manual for the VAX 8800 system, intended for internal use. It details the system's functional and operational characteristics at both a high-level overview and a detailed logic level.

The document is organized into several sections, each providing in-depth information on a specific aspect of the VAX 8800:

1. Introduction and System Overview (Section 1): Provides a general description of the VAX 8800 as an LSI-based, high-performance system, configured as a single or dual-CPU. It outlines the physical layout, major components (Console Subsystem, Central Processing Unit (CPU) comprising Instruction Box, Execution Box, and Cache Box, Clock Module, Memory Box), and the primary system buses (NMI, VAXBI, Visibility Bus), along with the Power System Complex.
2. System Bus Summary (Section 2): Delves into the architecture, signals, timing, and transaction types of the key interconnects:
   • Memory Interconnect (NMI): The synchronous backplane bus connecting CPUs, memory, and I/O adapters, detailing read/write transactions, interlocked operations, bus arbitration, interrupts, and error handling.
   • VAX Bus Interconnect (VAXBI): The 32-bit synchronous I/O bus, describing its basic functions, address space, transaction formats (command/address, embedded arbitration, data cycles), parity, stalls, retries, and broadcast/invalidate transactions.
   • Visibility Bus (VBus): A slow-speed diagnostic bus used by the console to monitor internal CPU module data, verify placement, and check control store parity errors.
3. Console Subsystem (Section 3): Describes the role of the console (a PRO-38N computer) in controlling and interacting with the VAX 8800. It covers the console's hardware (Real-Time Interface, PPI, Serial Line Ports) and software components (control program, file transfer, logical block server, Console Support Microcode - CSM), various operational modes, power-up/down sequencing, initialization procedures, and detailed register descriptions.
4. Power System Complex (Section 4): Focuses on the power distribution system, including components like the 876 Power Controller, NBox power converter, Modular Power System (MPS), Environmental Monitoring Module (EMM), and Battery Backup Unit (BBU). It details power distribution, functional operations, physical configuration, monitoring capabilities (voltage, temperature, airflow), and power-on/power-down sequences.
5. Clock Module (Section 5): Explains the generation and distribution of system clocks, detailing the oscillator, phase generator, clock distribution circuits, and clock control logic. It describes how the console controls clock functions such as starting, stopping, bursting, changing clock periods, and single-stepping.
6. Instruction Box (IBox) (Section 6): Provides a comprehensive overview of the CPU's instruction box, covering its microcode store and control, pipelining concepts, microsequencing logic (including microtraps and microbranching), and macroinstruction decoding. It describes the various internal registers and data paths.

The document extensively uses tables and figures to illustrate component layouts, block diagrams, signal descriptions, timing diagrams, and register bit configurations, providing a thorough technical foundation for understanding the VAX 8800 system.