Digital PDFs

EK-KA630-UG-001

February 1986

174 pages

Original

5.2MB

view download

OCR Version

5.3MB

view download

Document:	KA630-AA CPU Module User's Guide
Order Number:	EK-KA630-UG
Revision:	001
Pages:	174
Original Filename:

OCR Text

EK-KA630-UG-001

KAG630-AA
CPU Module
User’s Guide

Prepared by Educational Semvices
of Digital Equipment Comporation

1st

Edition,

Equipment Corporation

February

1986

1986.

A
All

Rights

Reserved,

The material in this document is for informational purposes and is
subject
to change without notice; it should not be construed as a
commitment
by
Digital
Equipment Corporation.
Digital Equipment
Corporation
assumes
no
responsibility
for
any errors that may
appear in this document.

FCC
Notice:
This
equipment
generates, uses, and may emit radio
frequency
energy. The equipment has been type tested and found to
comply
with the limits for a Class A computing device pursuant to

Subpart

of Part 15 of FCC Rules, which are designed to provide

reasonable

protection

against

such

radio

frequency

interference

when
operated
in
a
commercial
environment.
Operation of this
equipment
in
a
residential area may cause interference in which
case
to

the

user

correct

at his own

the

expense may be

required

take measures

interference.
Printed

U.S.A.

The
manuscript
for
this book was created on a VAX-11/780 system
running
WPS-PLUS.
The
book was produced by Educational Services
Development

and

Motorola

The

following

Publishing

registered

are

Marlboro,

trademark

trademarks

MA.

Motorola,

Digital

Inc.

Equipment

Corporation:

DECNET
DECUS

MASSBUS
OMNIBUS
0s/8
PDP
PDT

RSTS
RSX
RT
UNIBUS
VAX

DIBOL
IAS
LSI-11

Professional
Q-Bus
Rainbow

VMS
VT
Work

DEC
DECmate

DECwriter

P/0S

VAXstation
Processor

CONTENTS

Page

PREFACE

MEMORY ..ot ocevecvoceoscssoancssssanssosnsenons 1KBYTE BOOT AND DIAGNOSTIC ROM..csescossscacscone 1-

CONSOLE

SERIAL

Q22-BUS

INTERFACE....cccoeeosocscoccccsscsonsascscs 1-

LINE

UNIT

(SLU)¢eecosccssocsonnsaoscse 1~

KA630-AA
KA630-AA

OPERATION MODES..eeecescescascssccassacsns 1SPECIFICATIONS...cceeececsvessnosavosccansa 1-

INSTALLATION

KA630~AA
Memory

CONNECTORS . caveeesescscscscsssscsosnonsassl=
Expansion Connector (Jl)...cseeeecscccoeselm

COMPATIBLE

Www

BOOTING

DISTRIBUTION PANEL INSERT..c.ceacesas
(TOY) CloCk BBU.:uecsssncosssoncnnse

SYSTEM

AND

ENCLOSURES..esecesscsascssasccssl

CONSOLE

PROGRAM

CK-KA630-A CPU
Time-0f-Year

INI])N
|
1

Configuration and Display Connector (J2)..eeeoeese=
Console SLU Connector (J3)seeeeesescscencacsssaselr
KA630CNF CONFIGURATION BOARD..ceseeesoscscssosanoans

[

INTRODUCTION. ccecooescsccosansascnossscsessnsansoosseeld

78032 MICROPROCESSOR CHIP.sesecsocsosansns 1~
78132 FRU CHIP..:eeeeeecsccesscssossnnscns 1~
INTERFACE GATE ARRAY....cevecsvescsancsane 1-

INTERFACE

INTRODUCTION. s coosecosesaseensaseonsssescassasoacess3—

[+ X))

[=)]

W N~

POWER-UP...citvetncesssecoscecssosssosassssssasasscssld—

.1
.2

Power-Up

Power

Mod€..iceeesessosocecccsosssensososscsesd—

Stabilization

Console
Battery

ROM

CheckSUM....es00se0es3-

Program Initialization....iceeesceccecaesal-3
Backup CheCK..ceeeeeescsorsescessnosassessaeald=5

InterProcessor

(IPCR)

and

= OWOWUUNN N

OB WM
NN -

NNONNDNNDDDNDN

DN WWWWWN

CHAPTER

W Wi

INTRODUCTION. cccccoveenosassocscccsoscesccscasosonnca 1-

MicroVAX
MicroVAX
MicroVAX
LOCAL

CHAPTER

OVERVIEW

W wwH

@
o
s
s
o
8
o
o
¢

WO
JAWUL B WK -

Sl
e el al

CHAPTER 1

Communication

TeSt...veeeeeeeoosesecscsscnsnssssssssneeneld=b

Determining

Alternate

the

Console

Terminal

Console Device

TyPe€..sesseeesss3=5

Hardware

Determination...ccesececcecionesanenceasscsseeeld=5

Console

Terminal

DeterminationN....eveveessceesea3—6

iii

Primary Bootstrap Program (VMB)......eeveeeeveeee3=12
Bootstrap DevicCeS...eeeseeceaccscccecccososonesld=1l3

bt b
b

Bootstrap

Booting
Booting

from
from

BOOL.cuevoesoseosensessoosscssossassassensosasesecs3—26
Comment (!).eeesecsesscsscsescocsavnsescseonssssald—27
CONtinNUe. . vveesescsvssssnsccanscscscasassscansesi—27
DepoSiticecerseesasscsscscssacsosscnassocnsnseeld—27
EXAMine. . .veesesescsossosessesccscsasnsconsccseead—29
Find.ieeeeeeaoeoeeasssesscssossosssnsssssssoscessssd—30
Initialize.eseeesoosocssaoesansnssssasecncssnseld—3l
Halt.ueeeooeaooasanassonososeasasnscsosassnsssad=3l
REPEAL.evseeaecscssnessassssscsscssssncssoseaes3—3l
StALt.vessecsasssesessanssosonasassnssssncssesld—32
- =I
-0
UNJAM.eeeeeeososoaoacasssosnsssssanssssanssnsene3—32
Consocle Errors and Error MeSSa8ge€S.esececesessssse3=32
Halts and Halt MeSSAgeS..csessesccsscsscscocnsseld—32
CONSOLE I/0 MODE (SYSTEM RUNNING).:eeeososeeseassea3=35

8
Y

INTRODUCTION .. oeeoeoossvcososssncsssosccssssssacsccs
STATE..ccevrocccssscssssccscscsoscssncssassce

Halt

S
o
o

|
o

-G
s

INterrUPtS. s eaecesocscoccracsccosnssosscsssosnssss
EXCePLiONS. vt eersscessscssccsossctssscssocssssnscs
Machine Check ParameterS..ccecceesecccccoccccsce

RegiSterS..seecessescccscocccccsscsanns

Processor

INSTRUCTION SET.sceccveccccasssssesssoscooancscsssse
EXCEPTIONS AND INTERRUPTS.ccectocecccccccscscssocne

General Purpose Registers...cccevsceesccescnscsce
Processor Status Longword...cceeeoosscsscccscsns

]

PROCESSOR

ConditionS..ceceeeccccccsccesososnssocsssccnccsse

OWONANANNWH
-

ARCHITECTURE

[

e
e
«

Hi= ==
WK ~O

D D DD

WUS WN -

Console Command SYyNta@X..eceoessossesssnssssssses3—24
References to Processor Registers and Memory....3-24
Console COMMANAS.cssoessosscessoscsssscsnssosaases3—25
Binary Load and Unload (X).seeeceosecscoesseeseald—25

= b

DD WN

Fl.......cc0itetiecencnnnsseeld=1ld

from Disk....ceevecenesescoconassenessld-ld
from Tape.....cveeeeecesnnsosesscnseseld=1l?

System Control BloCK...eeeoeoesooeoscaocsosonsased=l
HARDWARE DETECTED ERRORS...eestcesososcsasscscssssd=l2
Nonexistent Memory ErrorS..c.ceesecescacceassecessd—12
Parity Error DetectioN..eeceeceessscesossccoesssd—l3
Interrupt Vector TimeoutS....eceeesecssccsssoeea4-13
NO SAcCk TimMeOUES.eeeceessessscosoasascssssssenesd—ld
[T

)
»
&

I
N
N
@

E D

o
o«
o

R
e

S
¢

BB BRWNNNDN
-

CHAPTER

Command

Booting
Booting

PROM..::ceeseneonsossesssssosasass3d—1l7
DEQNA...ceiesseecssocsssassecsass3—l9
Booting an Auxiliary Processor.......cceeeee.,3-19
Secondary Bootstrap Program.......ccceeeeseees0.3-20
CONSOLE I/0 MODE (SYSTEM HALTED) .:ceeeeosssscoooass3=22
Console Control CharacterS..ceeeseccsssesscessesi=22

0
B
b o

s
¢

@
o
€
e
o+
e

OV U B

@
o
o
o
o

o
s
s

BOOTSTRAP .cccetevssoccsccosccscessoscsssanssssascssse3=l0

DIAGNOSTICS .t ceeecasenossscacsssesssosasssssssssssee3—8
RESTART . cosececcscssossassssccacsncscsoscasssssscsssses3=8

Console Message Language ChecCK....eeeeeoeeceoeees3d—6
ENTRY/DISPATCH..... e

PN NNNNYNNAUNNVNNNNNNNNA
U s WD

WWWWWWWWWWiWwwWwiwWwwwWwWwWwWwwwwwwwuwwwwwuwwww

Contents

LATENCY . veevoeoososossscssnssosssscssssnssanccssassssd=1l4
Interrupt LatenCy..ccsecsceccossosscsossoccscscaceasecd—ld
DMA LatenCY..coesssseacososcsccsescsssacsnssssesscd—ld

SYSTEM IDENTIFICATION REGISTER (SID).ceesessoesecss4d-15
MEMORY MANAGEMENT ... ceeescsacasosssscsssanscccosssd=16
Physical and Virtual Address Space€....sceesec...4-16
Memory Management Control Registers.............4-16
System Space Address Translation.....ececeeeese.4-17
Process Space Address Translation......eceesees.4=-17
-

o
o

WK
-

&
¢
¢
&

=
N

8
&

AU
W N
N

R OO0
QOO

=
.

T
L

NN
e
P

WWWNNDNDNDNDND
N

N
N
e

N
s
&

N
2
o

R
9

R
o

R
&

Y
e
)

e bt e b b b e et bt b
et b
s bt bt bt et b b

- "[

T
ol ol ol ol el
e
DAEDBDWWWWWWWWN

Region

Address

TranslationN....scceeeeesceeccd=-17

Pl Region Address Translation....ccceveeceess.4-20
Page Table ENtrIY..ceceesescsconssesossnansnssssead—21
KA630-AA MEMORY SYSTEM..veeeeaesoeasocsossosessesessd=2l
Local Memory Mapping Register Format............4-21
Mapping Register Addresses (2008XXXX Hex).......4-22
Q22-Bus Map OperationN...eceeececssescesacasenserd=23
Memory System RegisterS...cececeseccescsncescosssd=24
Memory System Error Register (20080004 Hex)...4-24
CPU Error Address Register....eveceecccccsscssd=27
DMA Error Address Register....cececesccsccessos4-28
Memory System Operation...cesecescccesecescess..q4-28
KA630~AA BOOT AND DIAGNOSTIC FACILITY...secevses..4-30
Boot and Diagnostic Register....seseesececcesss.4=-30
ROM MEMOTYevssosasossoscsssesscnsscscsassoseecnssd=32
ROM SOCKELS.:iesosresssvssssnsoscossnssocsosscsased=32
ROM AQAresSs SpPaACe..scssescscccsssssscsccsssessd=32

RR S

N
N

s A WD WD AD WD WO O L0 D 00 00 0 00 000 0 0 ) OO

Contents

KA630-AA Console Program OperationN..eceeseee..4-33
KAG630-AA TOY CLOCK.uieeovaesaassosccsssensensascssssd=34
Battery Backed-Up Watch Chip....ccveeeecceesess.4-34
Watch Chip RegisterS...ecsceccececccccscsesessecd—34
TOY Data RegisterS..ecececscsescccsccacssseseasd—34
Control and Status Register A....cccesecevses.d4-36

Control and Status Register B...ceseesesessss.4-36
Control and Status Register C...ceecscceccasssd=37
Control and Status Register D.u.eecescsocasssssd-37
RAM MEMOTY.cosooeossocssonccsnsssnsannoseonssesd—38
POWEIr~UPuceeeeesosossossssasssssssasosseassssassed=38

Valid RAM and Time...vesescacscscsssncscessesesd=38
Invalid RAM and Time...eesesessvesaacacasesesssq—38
INTERVAL TIMER. .. ceesecocsssosncsossoscscascscsnessd=d0
Interval
Register

Clock Control and Status
(ICCS).eevecocsessessvsnssssscnoscsssssd—40

Interval Timer Operation......eceecececccccasesss.q4-40
CONSOLE SLU...vevecvossaosserssoasscsnsscsnsnnsesesd=40
Console Functionality.ieeeoesesccossoscscceesessd=-40
Console REgiSterS...csesessassnssosssscscssessssd—4l
Console Receiver CSR (IPR 32).4.cevccscsncsesnd-41
Console Receiver Data Buffer (IPR 33).........4-41
Console Transmitter CSR (IPR 34)..ceceesescs..4-44
Console Transmitter Data Buffer (IPR 35)......4-45
Break RESPONS@..cesesvcsscascscasssssssnsnsssessd—45

Q22~BUS CONTROL..ceeeececooccccocascssncssasoncsssd=45

Bus Initialize Register (IPR 55).cccccencesessss4-45
Multilevel INterrupPtS..c.cceccesccsocsccccocnonsesd=45

Contents

Interprocessor Communications Facility..........4-46
Interprocessor Communication Register.........4-46
Interprocessor Doorbell InterruptS.......e....4-48
d-48
RATIONS
.. .ccsossnscccsessoss
MULTIPROCESSOR CONSIDE

Auxiliary/Arbiter Differences.....coevsvesvsssses.4-48
Multiprocessor FeatUreS...eeiceesccccssocassess
qd-49
KA630-AA Based Multiprocessor Systems...........4-49
PDP-11 Based Multiprocessor SystemS.....c.e.se...4-50

Memory Data TeSt...ieeeecsescsossecocsscossvssscssd=2
Memory AdAress TeSt.eseeeceessscoocsosnssssonsoasaned=2

WU BN VE I

WU, B0 -1

022-Bus Mapping Registers TesSt.....eceeeeeeceesesed3
MicroVAX CPU Chip TeSt..eeessesccscosonsoneneossed3
Software Interrupts and TrapS.cesecececccsceccecssao—d
System Interrupts and Data Paths......ccceveceaes5Console TeSt..uiesosesrsocscscasessososnsssossocssesd
Console Program/ROM Diagnostic Interface.........5ERROR OUTPUT . ¢ecesvoosonacsssssosnasanssososenoansasd
KAG30~AA LED DISPLAY . .0eevsconcsscsnssossvnsssssaessdTM

APPENDIX

[o, W= W

(]

[« BEN IR I

o
8

INTRODUCTION . eetoesacocncsasoosssoscassssocsssssceasd]
FUNCTIONAL DESCRIPTION...:cecevescecssosscncsaccsacasd]l
IPCR Te@St.ceeoseeaasnosasossasnssocsscsccsaonsscesed=2

o
s

DIAGNOSTICS

*«

T, BV RO RC R, S
O
(S, C N0, IV

BWNNDNDNDNDND
DN -

CHAPTER

APPENDIX B

Q22-BUS

SPECIFICATION

ACRONYMS

FIGURES

2-2

2-3
2-4
2-5

2-6

2-7
3-1
3-2
3-3
3-4
3-5

3-6
3-7

KAG630CNF Configuration Board...cececeseesccscacscons

o
o

MicroVAX II System Level Block Diagram.......cceee
KA630-AA Pin and LED Orientation...ccecsescecccece

CPU Module.ceceoveeecocaans

KAG630CNF J2 and J3 Pin Orientation.....ccecececcasss
KAG630CNF J1 and J4 Pin Orientation.ccceiecccacccncne
CK-KA630-A Distribution Panel Insert..csccecesccccs

OO
AU

2-1

(MicroVAX 630)

MS630 Memory ModuleS..eecesseocccoscssscrosscosccsces
KA630-AA Block Diagram...seceeesceescscesssssccscsns

1-3
1-4

KA630-AA

“«

1-2

INNI\)N(})F—‘HTH
[
|
[

1-1

Page

Title

Figure No.

CK~KA630-A Connectors (Front View).....ceveveoesss2-1
CK-KA630-A Connectors (Rear View)...oeoeeeecsessss2-10
Console Memory Map After Initialization............3-4
RPB FOIMAL .o eeeruoeeeossassannssososscsssesosssnsese3=9
BOOED10CK FOIMAEteseseaseessscsonssasssscssonassessld—lbd

PROM Bootstrap Memory Format (Signature Block)....3-18

Extended RPB....ceceosen eoessecscssesrasasssnsscssse3=20
Secondary Bootstrap Argument List.........ccecs.0.3-21
Secondary Bootstrap Memory MapP.....eeeeecececsssss3=2l

Contents

hh-hlll-hbbhL}

Processor

4-9
4-10

4-11
4-12
4-13
4-14
4-15
4-16

Status Longword (PSL).cceeceocncssscncasesd=3
Interrupt ReGISterS.ccicesceasossccncscoscssosssancsald=T
Machine Check ParametersS,.c...c.scesoccececccsnsece.ld-8
System Control Block Base Register (SCBB).........4-10
System Identification Register (SID)..¢eeececcesscd-15
Virtual AdAresSs SpPaCe..cscecccccoccscssscsasssneasad=lb

Physical Address SpPacC@...cecccesecscoscsssccssessad—1lb
Memory Management (Mapping) Enable Register
(MAPEN) teeevesecacsosssscososssossossosssesssscseessd=l?
Translation Buffer Invalidate Single Register
(TBIS).sessssonsnosescsscssccsonsososancsssasnosssssd=l?
Translation Buffer Invalidate All Register
(TBIA).uceoseossnsecssnssssosnsaonssscscsssanssssnsesd=l?
System Space Virtual to Physical Address
TranslatioN.ceeceeceesceescescsscoanecsscccacsosessd—18B
PO Virtual to Physical Address Translation........4-19
Pl Vvirtual to Physical Address Translation........4-20
Page Table Entry (PTE)..icceesvacrcocccsecconeesssd=2l
Mapping RegiSter..cecececeacocsvcoscssscccacsenessd=22
022-Bus to Local Memory Physical Address
TranslatioN...eevesseseesecscccscscsccccscacansceaesd—24

4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25

Memory System Error Register (MSER)....ccevesoceesd4-25
CPU Error Address Register (CEAR)...cccecocesesas.q4-27
DMA Error Address Register (DEAR).cscecssescssesesd—28
Boot and Diagnostic Register (BDR).cseescscsscoees4-32
Control and Status Register A (CSR A)..vceseesese.4-36
Control and Status Register B (CSR B)i.seeecseses.d-36
Control and Status Register D (CSR D).cesececcossesd—37
Console Program Mailbox (CPMBX)...ceeececocescsssoa4-38
Interval Clock Control and Status Register

4-26
4-27
4-28
4-29

(ICCS) eueeesesssnacsosssscssossssssasasesescsncssesd—d0
Console Receiver CSRiuiisveseserencsonsasascccesassd—q2
Console Receiver Data Buffer...c.ececevaccccecese.4-43
Console TransMitter CSRi.cieceresosssccscsocnnscessd—44
Interprocessor Communication Register (IPCR).,.....4-46

TABLES

Title

Memory

Expansion

Configuration

and

Connector
Display

(J1)

PinoutS...eecseccesecs

Connector

(J2)

Pinouts...

Console SLU Connector (J3) PinoutS,...ececececcocesnece
KA630CNF Switch SelectionS....ceeeecsccaccsscncnnes
KA630CNF Connector and SwitcheS....eeeeceeccccsccese
POWEr—Up MOAEeS..cvcveetsassocasassssssscnsocsecsnccs
Additional Language Selections (VCBOl Only)........
Console Entry Decision Table...cseeeescsonscesancos
VMB Register UsSage....covesecscvacscscceancnancacsel

N
~JU W

VariantS.....cceeeecoancscccsns

Module

luwwwwtrmwo—-»—-b-e
|

Memory

Electrical SpecificationsS......ccvoecececcecccecsccns
Environmental Specifications.....ceceeceoesccsocccas

MS630

Page

)

BWN =W
WN -

WWWWNNNNNNN

Table No.

vii

L VR VS
N
T
T
[

WNHFNIOOUL

Contents

VMB Bootstrap Command FlagS....ccecceecsevcessossa3—15
Console Error MeSSageS..seecesccccscasassccecseess3d—33
KA630-AA Halt MeSSAgE@S.ceeccccseccssoecasssossssss3—34
Processor Status Longword Description..............4-2
Processor Register SUMMAIY....ccceecccncccscccsscessd—4
System Control Block Format.....c.cececesesassscssed-10
system Identification Register Format.............4-15
Memory Register FOIMAt...ccoveoescocaccosccsoosssad22
Mapping Register AdAresSSeS.....eeeceecessssoscocsssead-23
Memory System Error Register Format......eeeeoee...4-25
Boot and Diagnostic Register Format....ceceeessso.4-31
Watch Chip RegiSterS..ceesveeecssscecsosoccssansaead=35
Time-of-Year Data Register AddresseS...ecessesessa4=-35
Console Program Mailbox Format....cceeeeceeoescsssd-39
SLU Console RegiSterS.c.cecesescescsccscoscsscscssd=dl
Console Receiver CSR FOrMat...cseseeescsncsassescad—42

Console Receiver Data Buffer Format....c.eoceeeess..c4-43
d-44
Console Transmitter CSR FOrmat...ceceeescccccces.
Interprocessor Communication Register Format......4-47
Diagnostic TeStS...eseeoessesessossscccscssssasaneead2

KA630-AA LED InterpretatioN.c.eseceececcccccncocecesd7

viii

PREFACE

intended for the design engineer or applications
is
This manual
familiar with Digital's extended LSI-11 bus
is
who
programmer
(022-Bus) and the VAX instruction set. This manual is divided into
chapters:

the

following

the KA630-AA MicroVAX CPU module and
Introduces
OVERVIEW -and
features
module
including
modules,
memory
MS630
specifications.

INSTALLATION -- Describes the installation of the KA630-AA and

MS630 modules

in Q22-Bus backplanes and system enclosures.

BOOTING AND CONSOLE PROGRAM INTERFACE -- Describes the console
program, device booting sequence and console commands.

ARCHITECTURE

DIAGNOSTICS -- Describes the KA630-AA boot diagnostics.

instruction

-- Provides a description of KA630-AA registers,
set

and

memory.

CONVENTIONS

The

following

chart

lists

Convention

Meaning

<mm:nn>

Read

<CR>

the

"mm

conventions

through

used

nn,"

this manual.

indicates

bit

field

example,
For
signals.
or
1lines
of
set
a
or
the mnemonic device that stands for
is
<17:00>
A
17

address

lines

enclosed

label

00.

through

angle

brackets

represents

(usually a control or special character key)

keyboard

(in

this

NOTE

Contains

general

CAUTION

Contains

case,

the

carriage

key

on the

return).

information.

information

prevent

damage

equipment.

Boldface

capital

indicate variables.

Preface

related documentation.

Microcomputer Interfaces Handbook
Microcomputers and Memories Handbook

VAX Architecture Handbook
VAX-11 Architecture Reference Manual

You can order these documents from:
Digital Equipment Corporation
Accessories and Supplies Group
P. 0. Box CS2008
Nashua,

Attention:

03061

Documentation Products

EB-20175-20
EB-18451-20
EB-19580-20
EK-VAXAR-RM

CHAPTER

OVERVIEW

INTRODUCTION

1.1

The
KA630-AA
(Figure
1-1) is a quad-height VAX processor module
for
the
(Q22-Bus (extended LSI-11 bus). It is designed for use in
high speed, real-time applications and for multiuser, multitasking
environments. It can be configured as an arbiter or auxiliary CPU.
The
major
components
following paragraphs.

the

KA630-AA

are

described

ROM

GATE
ARRAY

Low

BYTE

ROM

HIGH
BYTE

Figure

1-1

KA630-AA

(MicroVAX

630)

CPU Module

the

Overview

1.2

MicrovAX

The
MicroVAX
manual)
is
a

78032

MICROPROCESSOR CHIP

78032 (referred
32-bit virtual

to as the MicroVAX CPU chip in
memory microprocessor packaged

this
in a

68-pin ZMOS (double metal NMOS) chip. It requires no special clock
generator or support chips. At its maximum frequency, the MicroVAXx
CPU
chip
achieves
a 200 ns microcycle and a 400 ns I/0 (memory)
cycle.
The
MicroVAX
CPU chip contains a 32-bit extension of the
industry standard microprocessor interface.
The

MicrovaX

CPU

chip

includes

VAX

compatible,

demand-paged

Memory
Management
Unit (MMU). This MMU provides direct access to
four
gigabytes (2**32) of virtual memory and one gigabyte (2**30)
of
physical
memory. Virtual mapping of system space addresses is
accomplished
through single level page tables. Virtual mapping of
process
space addresses is accomplished through double level page
tables.

The

MicrovVAX

data

types.

CPU

chip

provides

the

following

subset

the

VAX

Byte

Word
Longword
Quadword
Character string
Variable length bit
The

MicrovAX

78132

field

Floating

Point

Unit

(FPU)

chip

(referred

the
MicrovAX
FPU
chip
1in
this
manual)
provides
support for
F_floating,
D_floating and G_floating data types. Support for the
remaining VAX data types can be provided by macrocode emulation.
The

MicroVAX

instruction

CPU

chip

provides

the

following

subset

the

VAX

for

the

set.

Integer

arithmetic

and

logical

Address

variable length
Control
Procedure call
Miscellaneous

bit

field

Queue

Character
Operating
The

MicroVAX

emulation
decimal

string moves (MOVC3
system support

CPU

chip

the

remaining

string,

EDIT

provides
Packed

VAX
to

and MOVCS)

microcode

assistance

instructions:
Character

character

string

string,

(EDITPC)

and

Cyclic Redundancy Check (CRC). Support for floating data types and
instructions is provided by the MicroVAX FPU chip (Section 1.3).

Overview

MicroVAX 78132 FPU CHIP

1.3

The
MicroVAX
FPU
chip
supports
D_floating,
F_floating
and
G floating
data
types
and
instructions,
It
does
not support

Hfloating
data
types or instructions.
be provided by macrocode emulation.

H_floating data types can

MicroVAX INTERFACE GATE ARRAY
1.4
The
MicroVAX
interface
gate
array consists of two custom Large
Scale
Integration
(LSI)
chips.
The
gate
array
includes
the
following features.
)

Provides interface
and module logic

Provides
signals to the KA630-AA LEDs
and diagnostic boot state

indicating

Decodes
signals
from
the
KA630-AA
determine module characteristics

connector

Contains
a
1local
decoder and address latch, for use by
the memory subsystem and other KA630-AA logic elements

1.5

between the MicroVAX CPU and FPU

chips

console

LOCAL MEMORY

The
KA630-AA
CPU
contains 1 Mbyte of on-board local memory, and
supports
one
or
two MS630 memory expansion modules (Figure 1-2)
for
a
maximum
of
9
Mbytes
of
local
memory.
The
KA630-AA
communicates with MS630 memory modules through the CD interconnect

with

three

The

local

system

each

backplane

memory

variants

and

module.

(Table

1-1),

through a

50-conductor

cable

included

MS630 memory modules are available

all

populated

with

256

RAM chips.

KA630-AA provides byte parity generation and checking
memory.

Chapter

The

memory

mapping

procedure

for all

described

1.6
64 KBYTE BOOT AND DIAGNOSTIC ROM
The
KA630-AA
boot
and
diagnostic
ROM
provides
power-up
diagnostics,
boot
programs for standard devices, and a subset of
the
VAX
console
program.
The
power-up
diagnostics,
booting
procedure

1.7
The

and

console

program

are

CONSOLE SERIAL LINE UNIT
console
SLU,
described
in

processor

features

in Chapter

using

four

externally

VAX

Internal

selectable

described

(SLU)
Chapter

Processor

baud

rates.

Chapter

accessed

Registers

The

IPRs

the

(IPRs),

and

are

described

Overview

MS630-BA (2 MBYTE)

MS630-BB
(4 MBYTE)

MS630-AA (1 MBYTE)

Figure 1-2

Table 1-1

Variant
MS630-AA
MS630~-BA
MS630-BB

Storage

MS630 Memory Modules

MS630 Memory Module Variants

Module

Current at

(Mbytes)

Height

Number

+5 Vdc (Max)

1
2
4

Dual
Quad
Quad

M7607-AA
M7608-AA
M7608-BA

1.0 A
1.3 A
1.8 A

Overview

Q22-BUS INTERFACE

1.8

features.

The Q22-Bus interface provides the following
)

Block mode

)

022-Bus
memory

and single

1/0 map,
through

independent

transfer Direct Memory Access

(DMA)

which allows DMA devices to access
a
4
Mbyte
window
divided
into

local
8192

pages

Q22-Bus
interrupt
requests
configured as an arbiter CPU)

240 Q

Figure

1-3

system level

BIRQ7

(when

termination

1is

block diagram of the KA630-AA.

block diagram.

]

TRANSCEIVER f

=
&

MicroVAX

2018 S
[8
o
|

5331 022:8Us

u [:] e

B 21 o
[}
:14-21]0' 2

—Té
2

MicroVAX

icm

CHIP

pRT
-1

E:]

- §

ToY
ROM

CONSOLE

0-15

MAP

0-15

ARRAY
16-21
kt
AN

| <

MEMORY

GATE

17}

[uwm cormscroa]

0-15

ARRAY

is a

| LEDs l | 20-PIN CONNEC‘TORJ
9-15

‘ PARITY

Fiqgure 1-4

r 50-PIN CONNECTOR

B
ON-B0ARD

through

MicroVAX

FPU

CHIP

liEMORY INTERCONNECTI

ROW D AND C OF BACKPLANE

ROW B AND A OF BACKPLANE

Q22-BUS INTERFACE J
MR-0186-0001

Figure

1-3

KA630-AA

Block

Diagram

Overview

CPU REAR I/0
DISTRIBUTION INSERT
CONSOLE

50-PIN CABLE
MicroVAX LOCAL MEMORY INTERCONNECT (32-8IT DATA)

LOCAL

MEMORY

CPU/FPU

EXPANSION

ARRAY

MEMORY

]/ 1
Q22-

MEMORY

{a]

- - - - - — -

|
|
i

)

LBASK"_LAEE _________________________________

SERIAL
LINE

170 DISTRIBUTION
ERT

REMOTE TERMINAL

CONTROLLER

PRINTER

LOCAL TERMINALS

um0198.0079 B

Figure

1-4

MicrovAX

System

Level

Block

Diagram

Overview

NETWORK

OTHER

INTERFACE

Q22-8US

CONTROLLER

OPTIONS

_____________________________________

!
|
[

!1
|

_______________________________
g

[
BPOK, BOCOK,

BEVENT

|
ALT
1

RESTARTI
ENABLE |

DISK

STaRT

CONTROLLER

TAPE

CONTROLLER

POWER

SUPPLY

READY |
>

[

E
-

€

(=]

RD WRT
PRO

ROY,

MASS STORAGE SIGNAL
DISTRIBUTION PANEL
AC POWER

DISK DRIVE NO. O

DISK DRIVE NO. 1

DISK DRIVE NO. 2
“R0196.0029.4

Figure

1-4

(Cont)

Overview

1.9
When

KA630-AA
configured

MODES

arbiter

CPU, the KA630-AA must be installed
slot
of
a
Q22-Bus
backplane
containing the CD
It
arbitrates
bus
mastership
and fields Q22-Bus

in
the
first
interconnect.

interrupt

OPERATION
as

requests

BIRQ7

through

also

responds

interrupt

requests
from
its
own
interval
timer,
console
SLU
arnd
interprocessor
doorbell.
The
interprocessor doorbell provides a
means for auxiliary CPUs to request control of the Q22-Bus.
When

configured

auxiliary

CPU,

the

KA630-AA

can

installed

in
any backplane slot containing the CD interconnect. The arbiter
may
be
a
Q22-Bus
PDP-11 CPU or another KA630-AA. The auxiliary
KA630-AA
requests
bus
mastership to access the Q22-Bus. It does
not field Q22-Bus interrupt requests, but can respond to interrupt
requests
from
its
own
interval
timer,
console
SLU
and
interprocessor doorbell,
1.10
The

KA630-AA SPECIFICATIONS
KA630-AA
CPU
module

specifications

are

Table

electrical

listed

Tables

1-2 and

1-2

Electrical

and

1-3,

environmental

respectively.

Specifications

Maximum Currents

Q22~Bus Loads

Height

+5 vdc

+12 vdc

Quad

6.2

0.14

2.7

1.0

Module

Table

1-3

Environmental

Specifications

Specification

Range

Ambient storage temperature

-40 to +65°C

(-40 to +149°F)

Operating temperature (CPU
in an enclosure):

mounted

150 ft/min air flow

250 ft/min air flow

Relative

Storage

5 to 40°C

(41 to 1o4gp)

5 to 50°C (41 to 122°F)

humidity:

9.1

90% noncondensing, altitude
km

(50,000

ft).

Derate

maximum temperature by 1°c for each
1000

ft for each 1000 ft)

altitude.

Operating

10% to 90% noncondensing

CHAPTER

INSTALLATION

2.1

INTRODUCTION

This chapter contains information required to install the KA630-AA
in a system. It describes the following.
KA630-AA connectors

Configuration board
CPU distribution panel
Compatible system enclosures

2.2

The

KA630-AA CONNECTORS

communicates with local memory, the console device,

KA630-AA

and the 022-Bus through three J connectors and through its four
module fingers. The user can configure the KA630-AA through a CPU
insert or a configuration board. The slot
distribution panel
pinouts on the fingers of the KA630-AA are listed in Appendix A.
The KA630-AA has three connectors (Figure 2-1), J1 through J3.

I 8421
DC OK
LEDs

a
MR-17280

Figure 2-1

KA630-AA Pin and LED Orientation

Installation

2,2.1
Memory Expansion Connector (J1)
The
50-pin
memory
expansion
connector
between

rows

the

KA630-AA

slots

and

MS630

3 of

memory

Q22-Bus

interconnect.
Table
2-1
1lists
connector contains the following
[

BUFENL

e
e

BDIRTL
PE

GND

)

2.2.2

The

pins)

<03:00>

(1
{4

pin)
pins)

backplane

(memory data

(ground

has

jumper

interface
in

the

containing

lines --

the CD

switch

pins)

change

pins)

Configuration and Display Connector

KA630-AA

the

installed

Jl pinouts. The memory expansion
control, data and ground signals.

<01:00>

<31:00>

provides

modules

(J2)

settings

set.

Module
configuration
is
done
using
switches
on
the
CPU
distribution panel insert or the KA630CNF configuration board. The
20-pin
configuration
and
display
connector is connected to the
inside

board.

Table

2-2

Table

2-1

cable,

the

CPU

distribution

panel

insert

20-conductor

directly to connector J2 of the KA630CNF configuration
lists

pinouts.

Memory

Expansion Connector

(J1)

Pinouts

Mnemonic

01
02
03
04
05

GND
MDO
MD1
MD2
MD3
GND
MD5
MD4
MD7
MD6
MDY
MD8
GND
MD10
MD11
MD12
MD13

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

GND
PEL3
BUFENL
MD15
GND
GND
PEL2
MD17
MD18
MD19
MD20
MD21
GND
MD23
MD22
MD25
MD24

GND

07
08
09
10
11
12
13
14
15
16
17

18
19
20
21
22
23
24

MD14
PELO
GND
BDIRTL
MD16
BUFENL
PEL1

GND

43
44
45
46
47
48
49

MD27
MD26
GND
MD28
MD29
MD30
MD31

Installation

Configuration and Display Connector (J2) Pinouts?

Table 2-2
Pin

Mnemonic

Meaning

GND

Ground.

GND

Ground.

GND

Ground.

04
05

CPU CDO L
CPU CD1 L

This 2-bit code can be
CPU Code <01:00>.
configured only by using switches 7 and 8 on
the

2-4.)

KAG630CNF

configured

configuration board.

determines

(See Table

whether the KA630-AA is

the arbiter or as one of three

auxiliaries.

CPU Code

<01:00>

Arbiter
Auxiliary

00
01
10
11

CPU

Configuration

Auxiliary 2
Auxiliary 3

Code <01:00> is read by software from the

BDR.

the CPU distribution panel

the

arbiter

insert

is used,

made to pins 4 and 5. In
are
connections
no
by
negated
are
1levels
signal
case,
that
resistors on the KA630-AA, making it
pull-up
06

GND

07
08
09
11

DSPL
DSPL
DSPL
DSPL

CPU.

Ground.

00
01
02
03

L
L
L
L

Bits <03:00>. When asserted
Register
Display
output signals lights a
four
these
of
each
LED on the module. DSPL <03:00>
corresponding
by power-up and by the
(low)
asserted
are
OK. They are updated by boot
DC
of
negation
from the BDR.

and diagnostic programs

BTRY VCC

Battery

GND

Ground.

BDG

CDO

Boot

BDG

CD1

software

BDG CDl1 L

backup voltage

for

and Diagnostic Code

TOY clock.

<01:00>.

code indicates power-up mode,
from

the

BDR.

and

This

2-bit

is read by

Installation

Table

Configquration and Display Connector

2-2

(J2)

Pinouts*

(Cont)

Mnemonic

HLT

ENB

Meaning
L

Halt

Enable.

This

input

signal

controls

the

response to an external halt condition, If HLT
ENB is asserted (low), then the KA630-AA halts

and
enters
the
following occur.

console

program

any

The program executes
kernel mode.

The

)

The
KA630-AA
1is configured as an arbiter
CPU and the Q22-Bus halt line is asserted.

)

The KA630-AA is configured as an auxiliary
CPU
and
the interprocessor communication
register AUX HLT bit is set.

HLT

ENB

detects

1is negated

halt

instruction

break

character.

the

[

console

(high),

then the halt

break character are ignored and the
and
line
program responds to a halt instruction by
ROM
restarting or rebooting the system. If HLT ENB
and the KA630-AA is configured as
negated
is
program
ROM
the
then
CPU,
auxiliary
an
assertion of the ICR AUX HLT bit
to
responds
1is read by software
ENB
HLT
rebooting.
by
from

the

BDR.

Ground.

GND

CSBR

18
19

CSBR
CSBR

01
00

L
L

<02:00>. These three bits
Rate
Baud
Console
by using either the baud rate
configured
are
switch on the CK-KA630-A distribution
select
or switches 2, 3 and 4 of the KA6 30CNF
panel,
configuration

20
*

VvV

Fused +5

board.

volts,

KA630-AA module has 10 K pull-up resistors for the 8 input
signals (pins 4 through 5, 13 through 15 and 17 through 19).

The

Installation

Console SLU Connector (J3)
2.2.3
console SLU connector provides the connection between
10-pin
The
the KA630-AA and the console terminal. It is connected to the
inside of the CPU distribution panel by a 1l0-conductor cable, or
directly to connector J3 of the KA630CNF configuration board. A
cable from the outside of the distribution panel or J1 of the
KA630CNF provides the external connection to the console terminal.
Table 2-3 lists J3 pinouts.

Meaning

Mnemonic

(J3) Pinouts

Console SLU Connector

Table 2-3

EIA signal out.

GND

Ground.

SLU OUT L

Console SLU output from the KA630-AA.

GND

Ground.

GND

Ground.

Key

(no pin).

SLU IN +

Console SLU differential

GND

Ground.

+12 V

Fused +12 volts.

2.3

inputs to the

KA630~-AA.

IN -

SLU

KA630CNF CONFIGURATION

BOARD

Q
KA630CNF (H3263-00) configuration board (Figures 2-2, 2-3, 2-4)
is
provided
with each KA630-AA. The KA630CNF plugs directly into
connectors
J2
and
J3
on
the
configure the KA630-AA by setting
in Table 2-4.
Connector

1is

used

Connector

for

closest

connector

Table

to
2-5

1lists

corresponding
connectors

the

Jl1

the

and

Battery

the

pins

connectors
through
8

on
on

halts;

determine

CPU

::::iz;.

baud

lines

the

KA630-AA

right
side
Switches
1
console

positive
on

have

cable

Backup

connectors

both

corresponding

and

connect

KA630CNF

KA630-AA.
It allows the user to
the 10 switches on SW1l as listed

Unit

console

The J4

switches

connectors

connector.

and

rate.

SW1

required

switches

for

than

The

J3,

mode,

and

normal

the

Note

that

there

are

pins

two

left

power-up

connect

operation

and

SW1l.

J2 and J3 of the KA630CNF are
SWl set values that enable or

operation

SLU.

pin.
KA630-AA

and

the

(BBU).

and

disable

mode,

transmit

two

unused.

and

loopback

Installation

TOP VIEW

O TITITIT

PYTTTTTTTT

LbLb

MR.-14508

SIDE VIEW

citee

++1

J 0000000000

| 12345678910

Figure

2-2

KA630CNF Configuration

2
0

12
0

Board

3
MR-17281

Figure

2-3

KA630CNF J2

[

and J3

Pin Orientation

INEEREEEEER

+ -

Swi
MR.17282

Figure

2-4

KA630CNF J1

and

Orientation

Installation

Table

2-4

KA630CNF

Switch

switch/Setting

Mode/Function

Halt Mode

off
on

Disabled
Enabled

Console Baud Rate

off

Off

Selections

300

Off

600

Off
On
on
on
On

2,400
4,800
9,600
19,200
38,400

1,200

On
Off
Oon
off
Oon

Oon
Off
Off
Oon
On

Oon

Off

Power-Up Mode

Off

Oon

Off

Normal

off

Off

Oon

Off

operation.

connected.

Receive

Transmit

1line

line connected.

Language inquiry mode. Transmit line
Receive line connected.

connected.

Loopback

Transmit

test
line

mode

(maintenance).

connected to

receive

line and console.

Manufacturing

off

memory

Other

Note:

settings

for

use

only.

Bypasses

test.

6, 9 and 10 should not be

switches 5,

used.

CPU Operation Mode

of f

off

Arbiter

Off

Auxiliary

off

Auxiliary

CPU
J2

Mnemonic

2-5

KA630CNF Connector

CNF J2

CNF SwWl

CNF
J4

Connector

Switch

Pin | Pin

DSPL

1
2
3
4
5
6

5
7
8

10
11
12
13

DSPL

BTRY VCC
DSPL 03 L
GND
BDG CDO L~

12
13
14
15

BDG

CD1

15
16
17
18

HLT ENB
GND
CSBR 02
CSBR 01

17
18
19
20

CSBR 00

2
3

23
24
+10

from

BBU

CNF
Jl

Connector

Switch

6
7
8
9

CNF SWl

2
3

Mnemonic

CNF J3

2
3

GND
GND
GND
CPU CDO
CPU CD1
GND

L
L

CPU
J3

Switches

1
2
3
4
5
6

L
L

and

TOY

clock

chip

on CPU

EIA
GND

OUT

SLU OUT L

GND
GND
Key
SLU

(no pin)
IN +

6
7
8
9

SLU

GND

+12 V

uorierIe3ISUI

Table

12
13
14

4,
4,

5,
5,

3
2,
2,
7

9
2,

Installation

CK-KA630-A CPU DISTRIBUTION PANEL INSERT

2.4

in a MicroVAX II system, the
installed
when the KA630-AA is
CK-KA630-A CPU distribution panel insert (Figures 2-5, 2-6, 2-7)
in the rear I/0 distribution panel is used to select configuration
The KA630-AA can only function as an arbiter when it is
settings.
connected to the CK-KA630-A.

the CK-KA630-AB and

CK-KA630-A is available in two variants:

The

CK-KA630-AF.

J3 cables.
enclosures.

The difference is in the cable length for the J2 and

The CK-KA630-AB is used in Digital BA23-A and BAl123-A
in the H9642 and BAll-S
The CK-KA630-AF is used

enclosures.

Time-Of-Year

2.4.1

(TOY)

Clock BBU

The CK-KA630-A also contains a BBU for the TOY clock chip. The BBU
is

1located

the

back of the CK-KA630-A.

It consists of three

in series for a combined
nickel-cadmium batteries connected
voltage of 3.75 Vdc. The minimum required voltage is 3.6 Vdc. The
BBU provides power for the TOY clock chip when power is not
the KA630-AA from the system power supply. The BBU
to
supplied
recharges when dc power is applied to the KA630-AA. In addition to
the

time-of-year

Status

program
restart

Registers

data,

(CSRs)

the

TOY clock contains four Control and

and 50 bytes of RAM used by the console

(described in Chapter 3) to store information required to
the processor following a halt. The TOY clock chip and

four CSRs are described

in detail

in Chapter 4.

MR- 17217

Figure 2-5

CK-KA630-A Distribution Panel Insert

Installation

HALTS ENABLED
HALTS DIiSABLED

/HEX

DISPLAY

=/
LANGUAGE INQUIR"Y MODE
/
-»/
—/
0

NORMAL OPERATION

& @/ CONNECTOR

— LOOPBACK TEST MODE

300

600

1200

|- FOR consoLE

TERMINAL

2400
4800

%00

19200

(©

38400
OUTSIDE
MR.14503

Figure

2-6

CK-KA630-A Connectors

(Front

View)

BATTERY
BACKUP

TO CPU

UNIT

MODULE
J2

TO CPU

MODULEJ3\

INSIDE

Figure

2-7

CK-KA630-A

MR.14504

Connectors

(Rear

View)

Installation

2.5

COMPATIBLE

The KA630-AA
BAll-S

SYSTEM

ENCLOSURES

is compatible with the following Digital enclosures.

The
BAll-S
contains
a 4 row X 9 slot backplane with
22-bit
addressing
on slots A/B. The C/D rows contain
the
CD
interconnect. The backplane can contain up to
nine
dual~height
or
nine
quad-height
modules.

Dimensions
are 13.2 X 48.3 X 57.8 cm (5.2 X 19 X 22.7
in).
The
power
supply includes a master console and
provides

BA23-A

+5 V and

A at +12 V.

a 4 row X 8 slot 22-bit address
contains
BA23-A
The
backplane. Slots 1 through 3 provide 22-bit addressing
on
the
A/B
rows
and the CD interconnect on the C/D
rows.
Slots
4 through 8 provide 22~bit addressing on
both
the
A/B and C/D rows. Up to 8 quad-height, or 3
quad-height and 10 dual-height modules can be mounted.
The BA23-A has mounting

mass

master

+12

console

BA23-A

which
for

storage

space

devices.
and

The

for

provides

power

13.2 cm

(5.25

in)

supply includes a

36 A at +5 V and 7

A at

V.,

The

BA123-A

provides 8
26.5 cm

also

available

additional

(10.5

in)

mass

in an H9642

cabinet,

backplane slots and space
storage devices.

BAl123-A contains a 4 row X 12 slot 22-bit address
The
backplane. Slots 1 through 4 provide 22~bit addressing
on
the
A/B
rows
and the CD interconnect on the C/D
Slots 5 through 12 provide 22-bit addressing on
rows.,
both

space

the

for

A/B

and C/D

13.2 cm

rows.

The BAl1l23~A has mounting

(5.25 in)

mass storage devices.

The
power
supply
includes
a
master
console and 2
that provide 36 A at +5 V and 7 A at +12 V
regulators
per
regulator.
Total
power from each regulator must
not

exceed

230

CHAPTER

BOOTING AND CONSOLE PROGRAM INTERFACE
INTRODUCTION

3.1

This chapter describes the KA630-AA console program and booting
sequence. The console program, in conjunction with the KA630-AA
hardware, gains control whenever the KA630-AA halts. For the
KA630-AA, halting means only that control is transferred to this
program, not that the processor stops executing instructions.

The console program is located in ROM on the KA630-AA. The ROM
address range is located in the KA630-AA local I/0 space. The
console program uses the KA630-AA LEDs and console terminal output
to

communicate diagnostic progress and error reports to the user.

In order for the console program to operate, the processor must be
functioning at a level able to execute instructions from the
console

program ROM.

The console program provides the following services.

restart or bootstrap following processor halts

Automatic

[

Interactive command language allowing the user to examine

[)

Diagnostic tests executed on power-up that perform checks

]

Support

power-up

initial

and alter

the state of the processor

on the CPU, memory system and Q22-Bus I/0O map
terminal

not
are
Users
output
console

a video or hard-copy terminal as the console

assumed to speak English.
messages in 11 languages.

The console program can
If there is no language

specified
when
the system powers up, the console program prompts
the user for a language. The user language is then recorded (CPMBX
<07:04>)
in
battery
backed
up
RAM
on the TOY clock chip. The
preferred language is thus retained when the system is turned Off.

Booting

and

Console

Program

Interface

The
KA630-AA
decodes
the
ROM
addresses
so
that the same ROM
appears
more
than once in the address space. The console program
is written in position-independent code so that it can be executed
from
any
address
range.
The
KA630-AA
uses
this
feature
to
selectively enable and disable the external halt circuitry. If the

console
program is executing in the first address range (20040000
to
2004FFFF
hex),
external
halt conditions are ignored. If the
console program is executing in the second address range (20050000
to
200S5FFFF
hex),
external
halt
conditions
are
honored, the
console
program
halts,
and
immediately
starts
again
(at its
beginning)
to
process
the
halt.
The
console program normally
executes
from
the
first
address
range,
while the diagnostics
software normally executes from the second address range.
A console

terminal is not required for operation, but halts
enabled on a system not having a console terminal.

not

The

console

program

divided

into

the

following

major

should

sections.

Power-up

Entry/dispatch
Diagnostics
Restart

Bootstrap

Console
Console

I/0 mode
I/0 mode

(system halted)
(system running)

The console program receives control whenever the processor halts,
which occurs as a result of any of the following conditions.
Power-up

External halt signal
Execution of a halt instruction
Serious system error

When any halt occurs,

the processor performs the

)

Switches

Saves the Program Counter (PC), Processor Status Longword
(PSL), and Interrupt Stack Pointer (ISP) internally

Encodes and saves the condition that caused the halt
halt

)

to physical

following.

addressing

in a

code

Branches

the

start

the

console

program ROM

OK signal is present, the hex value F is displayed on
DC
the
If
the KA630-AA LEDs. Upon entry, the console program outputs the hex

LEDs,
<console
the
to
E
value
instruction
has
been
executed.
Register (BDR) bit 15
Diagnostic
power

stable.

1least one
at
that
1indicating
It
then
1loops
until Boot and
(PWR OK) is set, indicating that

Booting

and

Console

Program

Interface

<14:08> in IPR 43, noting if
a power-up halt, the console

The console program then checks bits
the halt is a power-up halt. If it is
program begins the power-up sequence
the halt is the result of a condition

described in Section 3.2, If
other than power-up, control
passes to the entry and dispatch code described in Section 3.3.
POWER-UP

3.2

At power-up, the console initializes the KA630-AA by performing a
variety of operations unique to the power-up process.
Power-Up Mode
3.2.1
BDR <10:09> is interpreted as a power-up mode field
At power-up,
are dependent on the
power-up operations
Several
3-1).
(Table
power—-up mode.

Table

Mode

3-1

Power-Up Modes

Language Prompt

Diagnostics

Prompt for language only if

Run full diagnostics.

Prompt for language on every

Run full diagnostics.

TOY battery backup failed.

power-up.

2
3

‘

3.2,.2
The

Set

language to English.

Set

language

loopback

English.

terminal

tests.

Run abbreviated

diagnostics.

Power Stabilization and ROM Checksum
console

indicating

program

that

calculates
a
against
the
computed
Program

code

Run console

outputs

the

power

the

hex

value

stabilization

wait

the

over.

LEDs,

then

checksum
of
the console program ROM and checks it
wvalid
checksum
stored
in
the
ROM itself., If the

checksum

differs

hangs

loop.

proceeds

the

from
the

the

stored

checksum

checksum,
the

same,

the
the

console
power-up

step.

3.2.3
Console Program Initialization
The
next
step
of
the
power-up
initialization is location and
initialization
of
the
memory
needed
for
the
console program
itself,
The hex value C is output to the LEDs at the beginning of
this step.

During

this

available

step,

memory

the console ROM code searches top-down through

for

program
for
writeable
for the console's direct

‘h bitmap
the

bitmap

contiguous

block

used

storage. This block consists
use and additional pages for

the

console

of two
use to

pages

store

available memory. The amount of memory allocated to

varies

according

the

amount

memory

available.

Booting

and Console

Following

The

stack

Program

initialization,

Interface

memory appears as

shown

Figure

console program memory is used by the consocle program for
and

other

data

structures.

3-1.

its

The bitmap is filled in at a later time with a map of valid memory
pages by the power-up memory diagnostics. This bitmap is passed to
the bootstrap as a map of valid memory. Beginning from the base of
bit corresponds to the first page of low
first
the
bitmap,
the
memory,
the
second bit to the second page, and so on. If the bit

if the bit is clear, the page failed the

is set, the page is good;

memory

test.

follows

that

The

bitmap does not map itself or any other memory

in the console program.

Since system software

is expected to use only pages marked as good

not expected to modify the bitmap or the
1is
it
bitmap,
the
in
program memory. However, the console program memory pages
console
checksummed by the console program to guard
bitmap are
the
and
against accidental modification by system software.

If the console program cannot locate enough memory for its own use
it hangs. Following initialization of its
bitmap,
the
for
and
the console program clears the following Console Program
memory,

Mailbox

(CPMBX)

<01:00> -~ Processor halt action

3 -- "Restart in progressTM flag

2 -~

"Bootstrap

in progress"

flag

000000
Low

THIS MEMORY IS NOT TESTED DURING
CONSOLE INITIALIZATION. IT IS TESTED LATER
8Y THE POWER-UP MEMORY DIAGNOSTICS.

MEMORY
BITMAP

SET BY THE MEMORY DIAGNOSTICS TO MAP
ALL GOOD LOW MEMORY.

CONSOLE

USED BY THE CONSOLE PROGRAM.

MEMORY |

MEMORY
HIGH

MEMORY

BAD MEMORY SKIPPED OVER DURING CONSOLE
MEMORY INITIALIZATION.

XX0000
wn 15706

Figure 3-1

Console Memory Map After Initialization

Booting

and

Console

Program

Interface

3.2.4
Battery Backup Check
The
console program then checks the TOY clock to determine if the
battery backup has failed. If this has happened, time-of-year data
has been lost along with the contents of all the TOY clock RAM. If
the
battery
backup
has failed, the console program performs the
following steps.
°
°
°

The

Stops the TOY clock
Zeros the time and all TOY RAM
Initializes the four TOY clock CSRs

operating

system must check TOY clock CSR B and determine

the
clock
is
time. No change

3.2.5

stopped
is made

to know if
to the LEDs

the TOY clock contains
during this operation.

InterProcessor Communication Register

Next,

the

IPCR

during
this
arbitrating
console

1is

tested.

value

test.
The
test
determines
properly.
If
the CPU module

program hangs

3.2.6

The hex

Determining

this

(IPCR)

output

Test
to

the

LEDs

whether the Q22-Bus is
is not arbitrating, the

point.

the Console Terminal

Type

3.2.6.1
Alternate Console Device Hardware Determination -- If
processor
is
an
arbiter,
the console
program
next checks
the
presence
of
a VCBOl or
VCB02 as the
console device.
the KA630-AA is an auxiliary processor, this test is
skipped.
hex value A is output to the LEDs during the test.

VCBO1l

and

testing

(for

alternate
terminal

the

VCBO0l),

response

and

VCB02

for

and

then

either

console

short

devices

VCB0O2

video

diagnostic

message

initialization
point.

language

the

CSR

20001F00
are

code

diagnostics
succeed,
the
console
terminal,
skips
console

console

1location,

determination

a VCB01l
a

alternate
presence

hex

not

(for

subsystem

check

diagnostic

determined

20001E92

hex

VCB02).

program

and moves

the
for
If
The

there

assumes

that

the

console

initialized

3.2.6.2).

detected,

executed.

console
the next

are

first

console

present

(Section

1is

devices
address

the

a valid

uses
step

the

the
and

(Section

fails,

the

initialization

VCBOl
moves

or VCB02
directly

3.2.7).

as
to

either

system hangs

and

the
the
the

this

Booting

and

Console

Program

Interface

3.2.6.2
Console
Terminal
Determination
-When VCBOl or VCBO2
alternate
console
devices are not detected, it is assumed that a
normal
console terminal is connected to the console port, or that
no
terminal
is
connected.
The console program then attempts to
determine the type of terminal connected. This information is used
when
in
console
I/0
mode to govern how command line editing is
performed.
The
console
program
sends the console port a device
attribute
request
escape sequence. If the device responds with a
recognizable
response,
the
terminal
1is
<classified
as a video
terminal.
The
terminal
must
respond
in 1 second to the device
query.
when
there
1is
no
response
or
the
response
1is
not
recognized,
the
test is repeated twice. If the device still does
not
respond
or
the
response is not recognized, the terminal is
classified
as
a
hard-copy
terminal,
Terminal
response
is
recognized in either 8- or 7-bit mode.

The
information
obtained
in
this
procedure
1is
also
used to
determine
if
the
terminal
supports
the
Digital Multinational
Character
Set
(MCS).
The
<console
program assumes that all new
terminals
(VT200
series and beyond) support MCS. If the terminal
does not support MCS, CPMBX <07:04> is set to 2, selecting English
as the console display language. The value 9 is output to the LEDs
during

this

3.2.7

test.

Console Message Language Check

The
console
next
outputs
the
value
8
to
the
LEDs and then
determines
the
appropriate
1language
to
use
for
all
console
messages.
The
console
1language
is stored in CPMBX <07:04>. The
algorithm

used

power-up

language

Note
one

determine

the

language

mode

(Table

English

and

3-1)

follows.

is 2 or

set the console

exit.

If
power-up
mode is 1 and the terminal supports MCS, or
if
the value of CPMBX <07:04> is 0, solicit the language
from
the
user.
If
the user does not respond within 30
seconds, set the language to English (mode 2) and exit.

that when the terminal is queried, if it is not recognized as
that supports MCS, CPMBX <07:04> is set to 2, forcing English

as
the console language. English messages use the 7-bit subset of
MCS.
1If
a
1loss
of power to the TOY clock chip is detected, the
contents
of
the TOY RAM are zeroed. This means that step 2 above
causes
the
wuser
to
be
prompted
for
language if the terminal
supports

3-6

the

MCS.

and

Booting

the

console

program

used
being
is
system
selecting
one
of
the

system

variants

querying

DEC

the

uses

(Table 3-2).
the

determines

Program

Console

that

Interface

a VCBOl video display

step in addition to
a
console,
the
as
languages
1is required. The VCBO1l display

LK20l1 keyboard, which comes in 16 national

The keyboard variant cannot be determined by

keyboard

the language selected or

itself;

it must be determined either

from

by means of an additional menu selection.

French, German or English is selected, the keyboard variant
If
The user
displayed.
1is
menu
additional
the
and
ambiguous
to specify which national keyboard variant is in use.
prompted
respond in 30 seconds, the last selection
not
does
user
the

is
is
If
is

assumed.

ENTRY/DISPATCH
3.3
determination of the console language on power-up,
the
Following

entry from any other halt condition, the console
on
directly
or
dispatches to the appropriate code to service the halt.
To determine what action to take, the console program examines the
(IPR 43 <14:08>), the halt enable bit (BDR 14),
code
error
halt
action (CPMBX <01:00>). It then acts in
halt
processor
the
and
accordance with the decision table shown

Table
ROM

3-2

Additional

in Table

Language Selections

3-3.

(VCBOl Only)

Language

Selected/
Additional

Selections

French

German

English

Canada

Germany/Austria

United Kingdom

France/Belgium

Switzerland

United

States/

Canada
3

Switzerland

Table

3-3

Halt

Entry Decision

Table*

Processor

Enable
(BDR

Console

14)

Power-Up
Halt

Halt Action
(CPMBX <01:00>)

Functions

Diagnostics,

Halt.

halt.

F
F
X

T
F
F

X
0
1

Diagnostics, bootstrap, halt.
Restart, bootstrap, halt.
Restart, halt.

Halt.

true,

matter.

Bootstrap,

false,

halt.

= condition of the bit(s) does not

Booting and Console Program Interface

If a power-up halt (second column) is true, it is one in which the
halt
error
code
contained
in IPR 43 <14:08> equals 3. When the

processor halt action is 1, 2 or 3, the condition of BDR bit 14 is
0, the action is
1is
halt action
the processor
wWhen
ignored.
the condition of HLT ENB (BDR bit 14). Multiple
by
determined
actions mean that the first action is taken, and if and only if it

the next action is taken. Diagnostics are an exception. If
fails,
fail, the console program hangs without attempting to
diagnostics

the processor. If they succeed, then the next action is

bootstrap
taken.

Note that because the KA630-AA does not support battery backup for
it examines the halt code and does not attempt to
main memory,
perform restart operations following power-up.
DIAGNOSTICS

3.4

the console outputs the message "performing normal
On power-up,
of systemTM to the console terminal. The
tests
diagnostic
Entry/Dispatch code dispatches the diagnostics to check the

processor

diagnostics

and

a "countdown"

The

first

continues

memory

before

proceeding.

each

test in the

is run, it is output to the console terminal, causing
to be displayed on the processor LEDs.

diagnostic

the

LED

code

is 8. Executing the diagnostics

countdown. The diagnostic codes are listed in

Chapter

At the conclusion of all tests, the message "Tests successfully
completed” is output to the console terminal. If a diagnostic test
detects a fatal error, an error message is displayed on the

console, along with a summary message indicating that continued
operation is not possible. The console program then hangs there,
leaving the test code on the LEDs. If halts are disabled, the only
way to clear the system is to turn it Off and then On again. If
halts are enabled, the system can be cleared by manually halting
it to enter console command mode. Additional
causing
it,
information on the diagnostics is located in Chapter 5.
RESTART

3.5

The console can restart a halted operating system. To do so, the
console searches system memory for the Restart Parameter Block
(RPB, Figure 3-2), a page-aligned control block created for this
purpose by the operating system. 1If a valid RPB is found, the
console restarts the operating system at an address specified in
the

3-8

RPB.

Booting

and

Console

Program

PHYSICAL ADDRESS OF THE RPB

Interface

:RPB

PHYSICAL ADDRESS OF THE RESTART ROUTINE

CHECKSUM OF THE FIRST 31 LONGWORDS OF THE RESTART ROUTINE
SOFTWARE RESTART iN PROGRESS FLAG (BIT O}

MRI§787

Figure

The

console
1,

uses

Searches
in
an

the

following

for

the
first
RPB fails.

Reads

the

address

RPB

page

address,

Calculates

the
of

contains

the

RPB:

found,

routine).

page
If

the

same

algorithm

2's

first

used

address

(the
is

for

physical

not

console

complement

sum

31
longwords
of
not match the third

routine.
If the sum does
the
RPB,
the
console program returns to
sum does match, a valid RPB exists and has

The

its

the

valid

program

check for 0 is necessary to ensure
not pass the test for a valid RPB.

32-bit
the

find

that

none

1longword
restart

overflows)

memory

the

returns to step 1. The
that a page of 0s does

Format

sequence

longword.

second

physical

3-2

for

both

arbiter

(ignoring
the restart
longword of

step
been

1. If the
found.

and

auxiliary

processors.,

The
console
keeps
which
it
wuses
to
operating

system.

maintained

The

console

a
"Restart in progress"
avoid
repeated attempts
An

additional

software

uses

following

the

"Restart

flag in CPMBX bit 3,
to restart a failing

progress"

restart

sequence

system:

Checks
it

the
set,

Prints

the

console

Sets

CPMBX

Looks
If

none

"Restart
restart

for
is

flag

may

RPB.

progress"”

flag

the

CPMBX

operating

bit

system”

fails.

message

"Restarting

the

operating

terminal.

bit

RPB

found,

left

memory

restart

fails.

the

operating

systenm.

Booting

and

Console

Reads
of

the

Program

Interface

software

"Restart

fourth

longword

the

progress®
RPB.

flag
is

from

set,

bit

restart

fails.

Loads
plus

the
512

Loads
43

Stack

Pointer

(SP)

with

the

address of

the

RPB

bytes.

the

Argument

Pointer

(AP)

with

the

halt

code

(IPR

<14:08>).

Displays

the

console

LEDs.

Starts
the
©processor
at
the restart address,
read from the second longword in the RPB.

which

If
restart
fails, the console program prints "Attempt to restart
operating
system
failed"TM on the console terminal. If the restart
is successful, the operating system must clear CPMBX bit 3.
3.6

BOOTSTRAP

The
console
program
can load and start (bootstrap)
system. To do so, it performs the following steps:
1.

Searches
system

for a 64 Kbyte segment of correctly

an operating
functioning

memory.

Sets SP equal

to the base address of

the segment plus

512

bytes.

Copies
the
primary
bootstrap,
called
Virtual
Memory
program ROM to the
console
the
from
(VMB),
Bootstrap
segment starting at the location specified by the SP.

Branches
and

the first location in VMB, which then loads

starts

the

operating

system.

in which the console program repeatedly
situation
a
prevent
To
bootstrap the operating system, the console
to
fails
and
tries
program maintains a "Bootstrap in progress® flag in CPMBX bit 2.
The console uses the following

sequence to bootstrap the operating

system:

Begins

step

if the bootstrap is the result of a

console

Bootstrap command.

Checks

the

Prints the message

console

Sets

set,

TMBootstrap in progress”
the bootstrap fails.

terminal.

CPMBX

bit

"Starting

flag

the operating

in CPMBX bit

system"TM

on the

Booting

Locates

such

page-aligned,

segment

Initializes

this

the

I/0

map

that

the

local

memory.
and
1is
Q22-Bus

all

processors,

map
registers
during boot, as
a.

Turn

Disable

the

(1)

This

the

good

bootstrap

The

the

pages

pages
a

that

main

the

in the

processor

Q22-Bus

first
I

memory.

fails.

function

arbiter

MicroVAX

all

are

Mbytes

compatibility

auxiliary

invalid.

the

I/0 map

022-Bus

map.

Interface

not done for auxiliary processors. Any
I/0
mapping must be coordinated with

bit

for

the

preset

1is

Program

segment

unoccupied

KA630-AA

Set

1I/0

are marked
follows.

IPCR

following

found,

corresponding

feature,
auxiliary
other

Kbyte

1is

all

Console

Q22-Bus

1initialization

mapped
of

cannot

and

halt

The

by clearing

IPCR

arbiter

I/0

map

the

I/0

rebuilt

flag.

each

page

processor

bitmap

bit

processor,

address

bits

corresponding

the

map

the

local

memory

page.

(2)

the

turn

corresponding

valid

(3)

If
the

the
KA630-AA is
valid bit in all

Enable

the

until

page

bit

that

steps

the

its

general

off

the

unoccupied,

valid

IPCR

bit

auxiliary

past

the

Invokes

VMB
base
VMB,

from
of

and

while

are
the

processor,

present

Q22-Bus

synchronize

bootstrap

registers

the
the

VMB

turn

off

5.
loop

console
good

fails,

map

a
is

auxiliary

host.)
for

VMB

shown

ROM

address

segment.
the

perform

I/0

3-4.

Copies

bit.

cleared.

namely,

with

turn

setting

function

initialized,
processor

page

an auxiliary processor,
map registers.

KA630-AA

secondary

Loads

occupied,

I/0 map

IPCR

(Note

Q22-Bus

bit.

bootstrap

fails.

Table

512

bytes

Booting

and

Console

Program

Table

Interface

3-4

Description

ASCII

Contents

Memory

Address

Unused

Software

VMB

name

(from

device

(from

size

memory

boot

R11

Halt

PSL

Halt

code

(argument

512

bytes

past

bootstrap

If
the

and

fails,

failed"TM

only)

value

value
pointer)

base

Kbytes

good

memory

pointer)

the

flags

command

Halt

bitmap

R10

system

command)

bytes

control

Bootstrap

(stack

Bootstrap

BDR

bitmap

Usage

console

prints

"Attempt

start

operating

terminal.

the
bootstrap
1is successful, the operating
"Bootstrap" and "Restart in progressTM flags
clear
the
LED
display
by
depositing
a

system must clear
in CPMBX <03:02>,
value of 0 in BDR

<03:00>.

3.6.1
Primary Bootstrap Program (VMB)
VMB is the KA630-AA primary bootstrap. It is executed
part
of
a
two-part system bootstrap operation. VMB
code that executes the following operations.
[

Initialization

System

Initialization

the
)

relevant

Selection

extended
a

Control

Page

RPB

bootstrap

Block

(SCB)

RPB

Frame

Number

(PFN)

bitmap

and

fields
device

Performance
of
a
Files-11
ODS2,
boot
load of the secondary bootstrap

down-line

as the first
contains the

block,

ROM,

Booting

The

secondary

bootstrap

KA630-AA systems, primary
and
secondary
bootstrap
system being booted.

VMB

finds

the

bootstrap

Console

Program

Interface

continues
the bootstrap operation. For
bootstrap operations are defined by VMB,
operations are defined by the operating

device

If
the
bootstrap
1is
command
and
a
device
that device is searched

and

one

three

ways.

the result of a console Bootstrap
name is specified in the command,
for the secondary bootstrap.

If the bootstrap is not the result of a console Bootstrap
command
or
if no device name is specified, VMB searches
the following devices, in the order shown.
a.

b.
c.
d.
e,

A bootable fixed disk
TK50 tape unit
MRV1l PROM
DEQNA, for a down~line

bootable

the

bootstrap

<01:00>
system

VMB

3.6.1.1
supported

attempt

the

RQDX2,

can

bootstrap

the

the operating
flags).

fails,

Bootstrap
by

1is

disk

result

equal to 2, that is, a
to
reboot the system,

to bootstrap
same command
When

removable

the

Devices --

The

program.

RQDX3,

KDA,

and

any

disk

boot

from

system

halt

used

with

CPMBX

the

following

bootstrap devices

are

RC25

disk

VMB

program

MSCP

unit

RA81.

unit

controllers.

supported

Units supported by RQDX2
and RD53. Units supported
supported

(as well

halts.

controller.
RD51,
RDS2
The

console

request from the operating
the device used previously

the

an MSCP disk

and RQDX3 are RX50,
by KDA are RA63 and

KLESI

the

RC25.

The

Bootstrap
command
designation
for these units is DUAO,
DUAl,
etc.
The
first
controller must be configured at
Q22-~Bus

address

(octal).

CSR

and

DEQNA

17772150

Additional

vector

(octal)

and

interrupt

<controllers are

located

vector

154

floating

space.

Ethernet

adapter.

This

controller

connects

Ethernet
cable.
The
Bootstrap
command designation for
this device is XQAO. The controller must be configured at
Q22-Bus
for one
MRV11

address
17774440 (octal)
unit or the first unit).
Programmable

Bootstrap

TMSCP
1s

tape

MUAO.

Q22-Bus

command

Read-Only

designation

controller.
The

address

TQKS50

The

vector

Memory

(octal).

(PROM)

124

(octal,

board.

The

PRAO.

Bootstrap

controller

17774500

and

command

must

designation

confiqured

Booting

and

Console

Program

Interface

3.6.1.2
Bootstrap Command Fl -- When a bootstrap is invoked using
the
Bootstrap
command,
the
user can specify several Bootstrap
command
flags
by bit encoding the flags in a flag word specified
with
the
/R5:
qualifier.
These
command flags are described in
Table

3-5.

3.6.1.3
Booting
from
Disk -- For VMB to boot using an MSCP disk
controller,
the
first
<controller must be configured at 17772150
(octal)
and
subsequent
controllers
must be configured in their
appropriate
floating CSRs and vectors. When VMB determines that a
controller is present, it searches for an accessible unit attached
to
the controller that has a removable volume. The search is made
in order of increasing unit number (DUAO, DUAl, etc.). If it finds
such
a
unit
with
a removable volume, VMB proceeds as described

below. If it finds no such volume, it searches the same controller
again, but this time checking for nonremovable volumes. If by this
time
no
accessible
volume
1is
found,
it
checks
for the next
controller
and
repeats
the
found, the disk boot fails.

process.

no more controllers are

If an accessible volume is located, VMB then determines if it is a
volume for file
the
searches
it
1is,
it
If
volume.
Files-11
[SYSO.SYSEXE] SYSBOOT.EXE, which contains the secondary bootstrap.
loads and executes it (performs a
VMB
found,
1is
file
this
If
secondary bootstrap).

the

block

volume

is not a Files-11 volume, VMB then checks logical

of the volume for a valid bootblock

(Figure 3-3).

If the

and executes the
1loads
VMB
a valid bootblock,
is
bootblock
in the bootblock. If there is no
secondary bootstrap specified
next
the
for
resumes
search
the
present,
bootblock
valid
accessible

Note

that

volume,

the

command flags,

bootstrap

as described

process

can

in Table 3-5.

altered by Bootstrap

Booting

Table

3-5

VMB

and

Bootstrap

Console

Command

Program

Flags

Bit
Number (s)

value
(Hex)

Flag

00000001

Conversation

Conversational

00000008

Bootblock

Secondary

Word

Interface

Description

bootblock.

bootstrap.

bootstrap
When this

from
bit is

set,

VMB reads logical block
number
0 of the boot device
and tests it for conformance
with
the
bootblock format.
If in conformance, the block
is
executed to continue the
bootstrap.
No
attempt
to
perform a Files-1l bootstrap
is made.
04

00000010

Diagnostic

00000040

Header

Diagnostic
bootstrap.
Wwhen
this
bit
is
set
the
secondary
bootstrap is file
{SYS0.SYSMAINT]DIAGBOOT.EXE.
Image

header.

not

set,

control

this

VMB

bit

transfers

the

first

location
of
the
secondary
bootstrap.
If
this
bit is
set,

to
the
08

00000100

Solicit

File

VMB

transfers

control

the address specified
file's image header.
name

Solicit.

When

this

bit
is set, VMB prompts the
operator for the name of the
secondary bootstrap file,
09

00000200

Halt

transfer., When
before
Halt
this
bit
is set, VMB halts
before
transferring control
to the secondary bootstrap.

<31:28>

X0000000

Topsys

X
can
be
any value from 0
through
F
(hex). This flag
changes
the
top
level
directory
name
for
system
disks
with
multiple
operating
systems.
For
example,
if
X = 1, the top
level
directory
name
is
[sYS1l....l.

Booting

and

Console

Program

Interface

BB
+ O
1

ANY

LOW LBN

VALUE

HIGH LBN

B8 + 2°N
+0:

CHECK

BYTE

+4:

ANY VALUE

+8:

18 (HEX

1 0R 81

SIZE IN BLOCKS OF THE IMAGE

+12:

LOAD OFFSET FROM DEFAULT LOAD ADDRESS

+16:

OFFSET INTO IMAGE TO START EXECUTION

+20:

SUM OF PREVIOUS THREE LONGWORDS

MR52TS

Figure

3-3

two

These

This
the

Bootblock

bytes

can

Format

have

any

value,

value is the word offset from the start of
bootblock
to
the
1identification
area

described

below.
must

This

This longword contains the logical block number
(word swapped) of the secondary image.

(2*n)

hex = VAX

(2*n)

instruction

instruction set.

set.)

This

unknown.)

defines

byte

volume.

This byte defines the expected controller type.
(0

This byte defines the expected
(18

byte

It may be

the

file structure on the

any value.

This byte must be the 1's complement of the sum
of

the previous
byte

must

three

(2*n)

This

(2*n)

This byte must be 1 or 81
the version number
defines

standard and
the high
1;

double-sided

bytes.

(hex). This byte
format
the
of

the type of disk. The version is
bit is 0 for single-sided, 1 for

volumes.

Booting

BB +

(2*n)

+ 6:

These two

BB +

(2*n)

This

they

{in

BB +

(2*n)

12:

are

BB +

(2*n)

+ 16:

BB +

(2*n)

+ 20:

3.6.1.4

attempts

1is
of

entry

This

Program

any value,

This
the

from

bootstrap

Interface

but generally

longword

containing

the

secondary

bootstrap

longword

1is

the

size

image.

containing

load

(usually
0)
from
the
default
of the secondary bootstrap.

1is

entry

is a

Tape

from

longword

three

bootstrap

containing

longwords.

-- If no bootable disk

TKS50

1load

a longword containing the byte

entry

offset
into
the
secondary
execution is to begin.

Booting
to

bytes may be

entry

offset
address

Console

blocks)

This

and

tape.

where

the sum of

is found, VMB

If
a
TKS0
1is present, VMB determines if a tape is loaded and if
the
unit is on-line. If so, VMB rewinds the tape and searches for
the
file
TAPEBOOT.EXE. (The user may specify an alternative file
name by setting the Solicit bit in the software command register.)
If
this
file
1is found, VMB loads and
file would contain a program to load an
onto a system disk.,.

executes it. Normally
operating system from

this
tape

If
a user has both disks and tape and a disk is bootable, to boot
from
tape
the user must either take all bootable disks off-line,
or explicitly boot the TK50 using the console Bootstrap command.

3.6.1.5

Booting

from
checks

PROM
for

-a

If
PROM

neither

disk

bootable,

VMB

bootstrap.

bootstrap,
addresses

VMB searches the Q22-Bus address range
by
page, looking for readable memory.

nor

tape

locate

is
PROM

from high to low
If the first six
longwords
of
any
such page contain a valid PROM signature block
(Figure 3-4), VMB passes control directly to the bootstrap code in
the
PROM.
It
does
not
copy
the PROM code to local memory for
execution, as it does for all other secondary bootstraps.
Note
VMB

that
does

bootstrap
may be in

KA630-AA's

while
not

defined

MRV1l

and

mapped

require

PROM

the

that

the

equivalent

Q22-Bus.

signature

bootstrap,

or the
code
be in PROM. The signature block or bootstrap code
ROM, nonvolatile RAM, or it could be loaded into another

RAM

actually

block

Booting

and

Console

Program

Interface

CHECK BYTE

ANY VALUE

+4:

18 (HEX)

+8:

SIZE OF PROM IN PAGES

+12:

MUST BE ZERO

+16:

OFFSET INTO PROM TO START EXECUTION

+20:

SUM OF PREVIOUS THREE LONGWORDS
MR 5776

Figure

3-4

PROM Bootstrap Memory Format

This byte must be

(Signature Block)

(hex).

This byte must be 0.

This byte may be any value.

This byte must be the 1's complement of the sum

the previous

three bytes.

This

byte

must

be 0.

must

This

byte

These

two

This

longword

the

bytes may be

any value.

contains the size

(in pages)

PROM.

12:

This

longword

must

16:

This longword contains the byte offset into the

20:

This

PROM where execution

is to begin.

entry is a longword containing the sum of

the previous

three

longwords.

Booting

3.6.1.6
found,

from

Booting
VMB

attempts

DEQNA
to

and

Console

Program

Interface

If no other bootstrap device is

bootstrap

from

the

DEQNA

Ethernet

the secondary bootstrap is down-line
case,
this
In
controller.
using DECnet low-level
the Ethernet,
from a host on
loaded
Maintenance Operation Protocol (MOP) Version 3.0. The DEQNA module
must be configured at 022-Bus address 17774440 (octal).
The down-line load process consists of the following steps:
1.

VMB
performs
local
testing
of the DEQNA. If the tests
fail,
the
bootstrap attempt fails and the three LEDs on
the
DEQNA are set according to the problem detected. The
LED settings and their interpretations are as follows.
°
°

3
2

'}
2.

LEDs on: DEQNA initialization failure
LEDs on: internal loopback failure
LED on: external loopback failure

VMB
transmits
a
program
request
Ethernet.
The message destination
multicast

address

The MOP

address

1is

AB-00-00-01-00-00.

The message

source

the DEQNA station address

(from DEQNA

PROM).

program

type

operating

system.

VMB waits approximately 30 seconds
If

does

request

response
fails.

not

every
is

MOP message over the
is the load assistant

receive

30 seconds

not

for a

received

response,

response.

retransmits

total of 2 minutes.

two minutes,

the

If a

bootstrap

VMB
accepts
MOP
load
messages and loads the data into
memory, terminating when the final message is received as
indicated
in
the MOP message protocol.
If the interval
between
1load
messages
exceeds
the DEQNA bootstrap at step 2.

3.6.1.7

Booting

Auxiliary

Processor

seconds,

VMB

auxiliary
processor by using the ROM bootstrap
the 022-Bus initialization algorithm in Section
Note

receive a

that

whenever

IPCR bit 8,
until
some

Steps 1
other

processor

proceeds

with

arbiter

the

processors.

console

bootstrap host,

the

processor

the

program

and 5 ensure that
processor
clears
bootstrap.

control

over

the

restarts

bootstraps

protocol.
3.6.

entered,

Refer

turns

an
to

off

an auxiliary processor loops
IPCR
bit
8.
When another

clears
This

VMB

IPCR

bit

the

synchronization

bootstrapping

all

auxiliary
gives

the

auxiliary

Booting

and

Console

auxiliary

the

processor

normal

only
for the
be
either
a
bootstrap

3.6.2
The

system

can

not

the

bootstrap
VMB

itself

from

auxiliary

any

checks

equivalent

bootstrap

IPCR

may
the

RAM.

with the bootstrap
bootstrap host, in

bit

the

unless

IPCR

bit

Program

Following

invoked

successful

bootstrap

second

execution

has

either

been

part

the

primary

loaded

into

in
ROM,
It
1is
the
responsibility
of the
to complete the bootstrap of the processor.

secondary

processor
at

auxiliary

program

secondary

VMB
calls
the
following state.

stack

the

Bootstrap

bootstrap.

The

construct

bootstrap

memory
or
located
secondary bootstrap

)

directly

devices,

auxiliary
does not proceed
host clears IPCR bit 8. The

clear

Secondary

bootstrap,

cannot

ROM bootstrap described above. The ROM bootstrap
block
of nonvolatile memory on the Q22-Bus, or

host

secondary

Interface

bootstrap

either
case,
the
until the bootstrap
turn,
should
is clear.

Program

IPL

R1l contains
3-5) created

bootstrap

running

with

the

processor

kernel

mode

the

interrupt

(hex).

the

base

address

the

extended

VMB.

OFFSET (HEX):

00:

ADDRESS OF THE EXTENDED RPB

04:

08:

0ocC:

10:

PC AT RESTART/HALY

14:

PSL AT RESTART/HALT

18:

HALT CODE

1C:

VMB INPUT REGISTER RO

20:

VMB INPUT REGISTER R1

24:

VMB INPUT REGISTER R2

28:

VMB INPUT REGISTER R3

2C:

VMB INPUT REGISTER R4

30:

VMB INPUT REGISTER R5

34:

TWO LONGWORDS RESERVED

DISK BLOCK ADDRESS OF SECONDARY BOOTSTRAP

40:

SIZE OF SECONDARY BOOTSTRAP FILE IN BLOCKS

44:

DESCRIPTOR OF PFN BITMAP (TWO LONGWORDS)

NUMBER OF GOOD PHYSICAL PAGES

4ac:

RESERVED

50:

PRYSICAL CSR ADDRESS OF 800T DEVICE

FOUR LONGWORDS RESERVED

SECONDARY BOOTSTRAP FILE NAME (40 CHARACTERS)

EIGHT LONGWORDS RESERVED

SYSTEM CONTROL BLOCK BASE ADDRESS

B 25784

Figure

3-5

Extended RPB

RPB

(Figure

Booting

contains

argument
SP

list

contains

which

1is

secondary
System

the

also

address

the

address

(Figure

Block

contains

Console

Program

secondary

Interface

bootstrap

3-6).

the

bootstrap

Control

address

(Figure

and

the

Base

top of

the

stack

beginning

plus

the

3-7).
(SCBB,

address

the

internal

SCB

processor

created

by VMB,

first four longwords of the VMB-created, extended
the
that
RPB
would not be recognized as a valid RPB by the console restart
up to the secondary bootstrap or the operating
|is
It
algorithm,
system itself to complete the RPB if automatic restart is desired.

Note

(AP)+00:

(AP)+04:

RESERVED

{APYH08:

RESERVED

(APY+12:

LOWEST VALID PFN

{AP}+16:

HIGHEST VALID PFN

{AP)+24:

PFN MAP SIZE IN BYTES

{AP}+28:

ADDRESS OF PFN BITMAP

{APY+32:

RESERVED

(APV+36;

RESERVED

(APY+40:

PROCESSOR 1D {87772)

(API+44:

RESERVED

(AP)+48:

RESERVED
15788

Figure

3-6

R1%:

Secondary

Bootstrap Argument

List

EXTENDED RPB BUILT BY VMB

+ 200 (HEX):

VMB

+ TBS (HEX):

2-PAGE SCB USED BY VMB

+ TBS (HEX):

8-PAGE PFN BITMAP

+ TBS {HEX):

4.-PAGE STACK FOR SECONDARY BOOTSTRAP

+ TBS (HEX):

SECONDARY BOOTSTRAP

+ 10000 (HEX):

Figure

.sCBB

'SP
Ma15783

3-7

Secondary

Bootstrap Memory Map

Booting

and

Console

Program

Interface

3.7
CONSOLE 1/0 MODE (SYSTEM HALTED)
When
the
KA630-AA
is
halted,
the operator controls the system
through
the
console terminal using the console command language.
The
console
terminal is in console I/0 mode. The console prompts
the operator for input with the string >>>,

3.7.1
In

Control

I/0

the

control

that
key

Console

console

while
°

holding
<CR>

several

down
The

carriage

taken

command.

the
a

special

return

command

ends

until

functions.

the

key.
A
treated

Note

character

command

after

Carriage
Return
carriage return is

line.

terminated

null
1line
as a valid,

action
1is
taken,
and
the
console
1input.
Carriage
return
1is
echoed
as
line feed.

Pressing

previously
typed
terminal
depends
hard-copy

have

typed by pressing
key (<CTRL>).

reprompts
for
carriage return,
°

are
Control

the

by
pressing
terminated
by
null

keys

characters

~--

action

Characters

mode,

the

Rubout

character. What
on
whether the

key

deletes

the

appears on the console
terminal is a video or

terminal.

hard-copy

terminals,

when

console
echoes
character being

with
a
deleted.

rub-outs,

additional

the

pressed,

the

backslash
(\), followed by the
If the operator types additional
characters

deleted

are

echoed.

When
the
operator
types
a
nonrub-out
character, the
console
echoes
another
backslash,
followed
by
the
character
typed.
The
result
1is to echo the characters
deleted, surrounding them with backslashes. For example:
The
The

operator types:
console echoes:

The

console

video

previous
cursor is

sees

EXAMI;E <Rubout> <Rubout>
EXAMI;E\E\;\NE <CR>

the

command

terminals,

when

line:

EXAMINE

1is

<CR>

pressed,

character
is
erased
from
the screen
restored to its previous position.

and

the

The console does not delete characters past the beginning
of
a
command
1line. If the operator types more rub-outs
than there are characters on the line, the extra rub-outs

are

ignored.

rub-out

typed on a

blank

line,

ignored.

<CTRL>

entire

echoed,
another

line.

and

The

console

<CTRL>

otherwise

command.

echoes

typed

ignored.

<CR>,

and

deletes

on an empty line,
The

console

prompts

the

for

Booting and Console Program Interface

This

S§

<CTRL>

stops output to the console terminal

1is typed.
<CTRL> O,

Q
<CTRL>
until
echoed. <CTRL> C,

<CTRL> S and <CTRL> Q are not
and <Break> also clear <CTRL>

are

[}

Q -- This resumes output to the console terminal.

¢CTRL>

Additional

<CTRL>

echoed.

not

Qs are

ignored.

<CTRL> S and <CTRL> Q

O =-- The console throws away transmissions to the

CCTRL>

<CTRL> O is entered.
next
the
until
terminal
console
¢CTRL> O is echoed as 0 <CR> when it disables output, but
Iis
Output
output.
reenables
it
echoed when
not
is

the console prints an error message, or if
if
reenabled
prompts for a command from the terminal. Displaying a
it
does not reenable output. When output is
Repeat command

prompt
console
command, the
reading a
for
reenabled
displayed. Output is also enabled by entering program
is
and by <CTRL> C. <CTRL> O clears
<Break>
by
1/0 mode,
S.

<CTRL>

R =-- This causes the console to echo <CR> <LF>
<CTRL>
followed by the current command line. This function can
be used to improve the readability of a command line that
been heavily edited.

has

<CTRL>

command.

data

C -- The console echoes C and aborts processing a

<CTRL> C has no effect as part of a binary load

<CTRL>

stream.

<clears

<CTRL> S, and reenables

<CTRL> O. When <CTRL> C is typed as
by
output stopped
part of a command line, the console deletes the line as
it

does

with

<CTRL>

<Break> -~ If the console is in console I/0 mode, <Break>

to <CTRL> C, but is not echoed at all. If
eguivalent
is
the console is in program I/0 mode and halt is disabled,
<Break> is ignored. If the console is in program I/O mode
and halt is not disabled,

halt

an
If
caret

and

enter

console

<Break> causes the processor to

I/0 mode.

unrecognized control character is typed, it is echoed as a
(") followed by the ASCII code character plus 64. A control

here, means a character with an ASCII code less than 32
character
between 128 and 159 decimal [Cl]. For example,
or
[CO0)],
decimal
(ASCII code 7) is echoed as "G, since capital G is ASCII code
BEL

+ 64 = 71. When a control character is deleted by rubout,

it is

echoed
the
same
way.
After
echoing the control character, the
console
processes it like a normal character. Unless the control
character
is
part
of a comment, the command is invalid, and the
console

responds

with

error

message.

Booting

3.7.2

and

Console

Program

Console Command

The
console
commands
are

Interface

Syntax

accepts
commands
up
responded
to with an

not

include
rub-outs,
carriage return.

Commands
may be
characters
from
from their first

rubbed

out

to 80
error

characters,

abbreviated.

Abbreviations

the end of
character.

keyword.

Multiple adjacent spaces
the console. Leading and
Command
qualifiers can
any symbol or number in

and tabs
trailing

characters long. Longer
message. The count does

All

are

the

formed

commands

are

terminating

dropping

recognized

are treated as a single space
spaces and tabs are ignored.

appear after
the command.

the

command

keyword,

after

All
numbers
(addresses, data, counts) are in hexadecimal. (Note,
though,
that symbolic register names include decimal digits.) Hex
digits
are
0
through
9,
and A through F. The console does not
distinguish
between upper and lower case either in hex numbers (A
through F) or in commands. Both are accepted.

3.7.3

The

References

KA630-AA

ROM.
For
modified
entered,
page
and

to Processor Registers and Memory

console

1is implemented by macrocode executing from
this
reason,
the actual processor registers cannot be
by
the
command
interpreter.
When console I/0 mode is
the
console
saves the processor registers in a scratch
all
command
references
to
them
are directed to the

corresponding
scratch
page
locations,
not
to
the
registers
themselves.
When
the
console
reenters
program mode, the saved
registers
are
restored
and
any
changes then become operative.
References
to
processor memory are handled normally except where
noted

below,

Generally,

free

page

the

interrupt stack

is used for the

scratch page, so the console does not modify the machine state. If
free page on the interrupt stack cannot be located, the console
a

program uses the last valid page in contiguous physical memory and
the

original

machine

state

1lost.

This should occur only on

power-up.

scratch page by Examine and Deposit
the console
to
References
is
Access
by the /U qualifier.
be gqualified
commands must
primarily to simplify debugging of the console program. The binary
reference the console scratch
cannot
commands
unload
load and
page.

Booting

3.7.4

Fonsole Commands

3.7.4.1

Binary Load and Unload

and

Console

Program

Interface

(X)

Syntax:

Command

X <address> <count> <CR> <checksum>

The
X
command is for use by automatic systems communicating with
the
console. It is not intended for use by operators. The console
loads or unloads (that is, writes to memory, or reads from memory)
the
specified
number
of
data
bytes, starting at the specified
address.

If
bit
31
of
the count is clear, data is to be received by the
console, and deposited into memory. If bit 31 of the count is set,
data
is
to
be
read
from
memory
and sent by the console. The
remaining
bits
1in the count are a positive number indicating the
number

bytes

The
console
return.
The

load

unload.

accepts
the
command
upon
receiving
next
byte
the
console
receives
1is

the carriage
the
command

checksum, which is not echoed. The command checksum is verified by
adding
all
command
characters, including the checksum, (but not
including
the
terminating
carriage
return
or
rub-outs
or
characters
deleted
by rub out), into an 8-bit register initially
set
to
zero.
If
no
errors
occur,
the result is zero. If the
command
checksum
1is correct, the console responds with the input
prompt
and
either
sends
data
to
the requester or prepares to
receive

data.

the

command

checksum

responds
with
an
error
message.
inadvertent
operator
entry
into
a
accepting

characters

sequence

possible,

bit

the

from

the

count

1is

error,

The
intent
mode
where

keyboard

clear

data,

(binary

the

console

1is
to
prevent
the console is

load

with

escape

commands),

the

console responds with the input prompt, then accepts the specified
number
of
data bytes for depositing to memory, and an additional
byte of received data checksum. The data is verified by adding all
data
characters and the checksum character into an 8-bit register
initially
set
to
=zero. If the final contents of the register is
nonzero,

the

responds

with

bit

console
number
to

data

responds
of
bytes

error

the

checksum

are

error,

and

the

console

message.

count

1is

set

(binary

unload

with the input prompt, followed
of binary data. As each byte is

commands),

the

by the specified
sent it is added

a
checksum
register initially set to zero. At the end of the
transmission,
the
2's complement of the low byte of the register
is

sent.

Booting

and

the

1line

Console

data

checksum

errors
transmission
is

message.
If
memory being

Program

©possible

all

Data

the

during

control

characters
(<CTRL>
C,
unload
commands.
It is

incorrect

during

on a

load,

transmission

if memory errors

data,

the

data

using

the

console

completed,
and then the console
an
error occurs during loading, the
loaded are unpredictable.

Echo
is
suppressed
checksums.
It

occur

Interface

received
being

the

receiving

console

<CTRL>
S, <CTRL> O, etc.)
not possible during binary

characters

loaded

the

the entire
issues an error
contents of the

with

are

valid

binary

load

string

and

control

during
binary
load commands,

data.

command

must

received

the console at a rate of at least one byte per second. The command
checksum
that
precedes
the data must be received by the console
within
10
seconds
of the <CR> that terminates the command line.
The
data
checksum must be received within 10 seconds of the last
data
byte.
If any of these timing
requirements are not met, the
console
aborts
the
transmission by issuing an error message and
prompting for input.
The

entire

console

character
of data in

command,

single

rate.
The
a single X

3.7.4.2

Boot

Command

Syntax:

BOOT

[<qualifier

The

device

two-letter
number,

The

boots

and

including

burst

console is
command.

list>]

specification

console

is a

checksum,
may be

able

the

sent

console's

receive

least

the

specified
4

Kbytes

[<device>]

device mnemonic,
u

the

characters

one-~digit

the format ddcu, where dd is a

is an optional one-digit controller

unit

number.

initializes the processor and starts VMB running. VMB

the operating system from the specified devi?e. The default

bootstrap device

is determined as described

in Section 3.6.

Qualifier:

/R5:<data> -- After initializing the processor and befo;e
starting VMB, R5 is loaded with the specified data. This
allows a console user to pass a parameter to VMB. (To
remain compatible with previous processors, /<data> 1s
also

recognized

and

has

the

same

result.)

Booting

Command

Console

Program

Interface

(1))

Comment

3.7.4.3

and

Syntax:

The comment command
command sequences.

3.7.4.4
Command

ignored.

used

annotate

console

I/0

Continue
Syntax:

CONTINUE

The

processor

begins

instruction

currently
contained
initialization
1is
not
mode.

3.7.4.5

Syntax:

DEPOSIT

([<qualifier

command

address
are

the

list>]

deposits

space

last

Examine
address
and the

execution

data

the
size

address

command.
space
default

response.

deposited,

The

address

data

into

the

qualifiers

space

After

and

address

are

data

processor

the

may

PSL

specified

The

space

The

one

on
of

the

space

the

legal.

program

set

stack

the

processor

identified

address

data

extended

also

space

address

Processor
program I/0

size

used

default

smaller

left

status

the

and

defaults

Deposit

the
size

default
is

long,

size
issues an

to be
error

data
the

data

size

zeros.
symbolic

longword.

PSL

(machine

counter

the

data

than

with

following

When

specified.

specified,

1initialization,

is physical memory,
address is zero.

qualifier

the

<data>

If
the
specified data is too large to fit in
deposited,
the
console
ignores
the command

program
counter,
The console enters

Deposit

Command

This

in
the
performed.

addresses:
address

examined,

the

space

address

dependent).

(general

15).

The

14).

The

/G.

pointer

(general

/G.

3-27

Booting

and

Console

General

decimal.
D

R10

Program

The

1234

address

6FF00

Interface

equivalent
is

space
to

equivalent

The

/G.

For

D/G

1234.

D/G

number

example:

6FF00.

-- The location immediately following the last location
referenced
in
an
Examine
or
Deposit
command.
For
references
to
physical
or
virtual
memory spaces, the
location
referenced is the last address plus the size of
the
1last
reference
(1
for
byte,
2
for
word, 4 for
longword).
For other address
spaces, the address is the
last address referenced plus one.

—-- The location immediately preceding the last location
referenced
in
an
Examine
or
Deposit
command.
For
references
to
physical
or
wvirtual
memory spaces, the
location referenced is the last address minus the size of
this
reference (1 for byte, 2 for word, 4 for longword).
For other address spaces, the address is the last address
referenced minus one.

*
—The
1location
Deposit command.

The

referenced

1last

1location
an

referenced

addressed

Examine

Deposit

1in

the

1last

command.

Examine

1location

Qualifiers:
/B

The

data

size

byte.

/W --

The

data

size

word.

The

data

size

longword.

/V -- The address space is virtual memory. All access and
protection
<checking
occurs.
1If the access would not be
allowed
to
a
program running with the current PSL, the
console
issues
an error message. Virtual space Deposits
cause
PTE
bit
M
to
be
set. If memory mapping is not
enabled,
virtual
addresses
are
equal
to
physical
addresses.

The

address

space

-- The address space

These
are
the
instructions.

through

PC.

registers

The address space

physical

internal
addressed

memory.

processor registers.
by

is the general

the MTPR and

MFPR

Booting

=~-

Access

qualifier

console

also

and

Console

program

disables

memory

virtual

/N:<count>

The

console
deposits
specified
number
address

the

first
succeeding

first

repeated

allowed.

addresses.

Even

‘'-*,

the

The

the
the
succeeding

symbolic address
the direction of

references

Deposit

range.

The
not

This

protection

then

address
larger addresses.
starting address,

Repeat

Interface

address,

symbolic

are
at
only the
succession.
For
use

the

addresses
specifies

addresses,

address

checks.
P

Program

preceding

<data>.

NOTE

Only
memory may
words.
General

be accessed
registers,

as bytes or
the PSL and

IPRs must be accessed using the longword
reference. This means that the /B and /W
qualifiers
may
not be used with the /I
and /G qualifiers.
For

example:

D/P/B/N:1FF

Clears

the

first

512

bytes

physical

Deposits
5
into four longwords
at virtual address 1234,

starting

memory.

D/V/L/N:3

D/N:8

1234

FFFFFFFF

Loads
with

D/N:200

general

registers

through

clears

513

specified,

the

-1,

Starting

address,

bytes.

conflicting

console

3.7.4.6

address

ignores

the

and

data

issues

sizes

are

error

response.

Examine

Command

Syntax:

EXAMINE

[<qualifier

Examgngs

the

specified,

symbolic

space

command

'+'

list>]

contents

addresses

[<address>]

the

assumed.
described

specified

The
under

address.

address may also

Section

3.7.4.5,

address

be one of

the

Deposit.

Qualifiers:

The

same

Deposit,

qualifiers

used

with

Examine

may

used

with

Booting

and

Console

Program

Interface

Response:

<tab>
The

<address

address

space

identifier>

identifier

can

<tab>

<data>

be:

P
-Physical
memory. Note that when virtual memory is
examined,
the
address space and address in the response
are the translated physical address.

[}

G -- General

)

Internal

processor

-- Machine dependent

the

(used

only

for

display

PSL).

3.7.4.7

Find

Command

Syntax:

{<qualifier

FIND

1list>]

The
console
searches
main memory starting at address zero for a
page-aligned,
64
Kbyte segment of good memory, or an RPB., If the
segment
or
block is found, its address plus 512 bytes is left in

SP.

issued,
is

the

and

specified,

segment

block

1is not found an error message is

the contents of SP are
/RPB

unpredictable.

If no qualifier

assumed.

Qualifiers:

-- Searches memory for a page-aligned segment of
/Memory
64 Kbytes in length. The search includes a
memory,
good
leaves the contents of
and
memory
of
test
read/write
memory

unpredictable,

Searches memory for a restart parameter block.
/RPB -The search leaves the contents of memory unchanged.

Booting

and

Console

Program

Interface

following

registers

Initialize

3.7.4.8

Syntax:

Command

INITIALIZE

A
processor
are set (all

All

other

The

PSL

041F0000

IPL
ASTLVL

SISR

ICCs
RXCS

0
0

TXCS

MAPEN

registers

The previous
in
to

initialization is performed.
values are hexadecimal):

are

console

unpredictable.

reference defaults

(the

defaults

used

unsupplied qualifiers for Deposit and Examine commands)
physical address, longword size and address 0.

3.7.4.9

BRalt

Command

Syntax:

fill

are

set

HALT

The
when

Halt
command
has no
in console I/0 mode.

3.7.4.10

Repeat

Command

Syntax:

REPEAT

The

console

command.
console
exception

The

repeatedly
repeating

command
of

may

effect;

the

displays
1is

stopped

specified

processor

and
by

executes
typing

for

the

already

the

<CTRL>

command

halted

specified
Any
with

valid
the

Repeat.

3-31

Booting

and

Console

3.7.4.11

Start

Command

Syntax:

START
The
If

Program

Interface

[<address>]

console
no

starts

address

instruction

given,

the

execution

current

the

used.

specified
If

address.

qualifier

present,
macroinstruction execution is started. If memory mapping
is
enabled,
macroinstructions
are executed from virtual memory.
The
Start command is equivalent to a Deposit to PC, followed by a
Continue. No Initialize is performed.
3.7.4.12

Test

Command

Syntax:

TEST

[<test

number>]

The
console
invokes
number>.
Valid
test
number is supplied, no

a
diagnostic test program denoted by <test
numbers
are
3 through 7 and B. If no test
test is performed.

3.7.4.13 Unjam
Command

I/0

Syntax:

bus

3.7.5

reset

Console

Some
error

console
occurs

responds
Table
3.7.6

HLT

The

performed.

Errors

commands
as
the

and

Error Messages

result
result

in errors. For
of
a console

with

error message.

Halts

and

Halt Messages

The error

example,
command,

messages

if a memory
the console

are

listed

3-6.

Whenever
the
error message,
For example:

halt

processor
halts,
and the hex value

the console prints the halt code,
contained in the program counter.

INST

800050D3
halt

code

messages

is
are

passed
listed

to
in

the

operating

Table

3-7.

system

restart.

The

Table

Ralt

3-6

Booting

and

Console

Error

Program

Interface

Messages

Message

Explanation

FNF

VMB
could
file.

ILL REF

The

ILL CMD

The command string cannot be parsed.

INV DGT

A number has an

LTL

The

Code

not

find

requested

the

secondary

reference

bootstrap

would

violate

virtual
memory
protection, the address is
not mapped, the reference is invalid in the
specified
address
space,
or the value is
invalid in the specified destination.

command

invalid digit.

was

too

large for the console

to buffer. The message is fssued only after
the

console
receives
return.

the

terminating

falls

outside the

carriage

ILL ADR

The

address

limits

VAL TOO LRG

The

specified

the

value

address

space.

specified

does

not fit

in the

destination.

SW CONF

Switch conflict.
data
sizes
are

For example, two different
specified with an Examine

command.
1p

UNK

SYM

The

switch

CHKSM

The

HLTED

The

FND

ERR

RPB
22

TMOUT

MEM

ERR

Find

During

the

Parity

Examine

unrecognized.
data

entered

command

checksum

incorrect.

operator

address

command

command
20

unrecognized.

symbolic

Deposit
1F

Kbytes

time
error

Halt

failed

good

command,

expected.
detected.

command.

either

find

the

memory.

data

failed

arrive

Booting

and

Console

Program

Table

Interface

3-7

KA630~-AA

Halt

Messages

Halt

Code

Message

EXT HLT

Explanation
<Break>
QBHALT

typed on

the console,

QBINIT or

push

onto

asserted.

ISP ERR

DBL ERR

The processor attempted to report a machine

HLT INST

The

SCB ERR3

The vector had bits <01:00> equal to 3.

SCB ERR2

The vector had bits <01:00> equal to 2.

CHM FR ISTK

A change mode instruction was executed when

CHM TO ISTK

The

ocC

SCB RD ERR

hard

interrupt

access

MCHK AV

was
was

attempting

interrupt

stack

during

check to the operating system,
machine check occurred.

PSL

bit

KSP AV

second

mode.

set.

IS was

exception vector for a change mode had
set.

processor

memory
was

translation

and a

executed a halt instruction

processor

kernel

interrupt

the

or
exception,
the
processor
discovered that
the interrupt stack was mapped No Access or
Not Vvalid.

error

access

translation

occurred

while the

trying to read an exception

vector.

violation

occurred

exception processing.

state

violation

occurred

invalid

during machine check

during processing of

an invalid kernel stack pointer exception.

3-34

Booting

3.8

CONSOLE I/0 MODE

and

Console

Program

Interface

(SYSTEM RUNNING)

when
the processor is not executing instructions from the console
program
ROM,
it
1is
in
program I/0 mode, in which all terminal
interaction
is
handled
by
the operating system. In program I/0
mode, the console terminal behaves like any other operating system
terminal.
If
halts
are disabled, break is ignored. If halts are
enabled,
break
causes
the
processor to halt, that is, to enter
console I/0 mode.
Oon
successful
identifies
the

program

ROM.

normal

tests.

power-up,
processor

the
and

first
version

1line of
number

The next line explains that the

the console
(XX) of the

system

display
console

is performing

The
countdown
sequence assures the user that the
system is progressing through its tests, and documents which tests
are
executed. When diagnostics are complete, the console notifies
the
user
that
the
tests
completed successfully.
system
software” message indicates the beginning of

sequence.

The

remaining

digits

successful

execution

the

completion

the

bootstrap

countdown
a

The "Loading
the bootstrap
sequence causes the

bootstrap

occurs

displayed.
in

the

Because

context

the

operating
system
bootstrapped,
a
confirming message indicating
that
the
system power-up has completed can only be issued by the
bootstrapped operating system.
When

fatal

sequence

problems

diagnostic
number,

are

interrupted

message
and

personnel.

detected
and

composed

three

than

one

the

diagnostics,

diagnostic

message

gquestion

parameters
such

mark,

‘a

use

for

error

the

countdown

islgisplayed.

message

subtest

The

code

diagnostic

possible,

but

unlikely. The summary message that follows indicates that the test
failed
and
that
normal
operation is not possible.
The console

program

then

Catastrophic
program

the

errors

cannot

program

terminal.

hangs.

are

continue.

attempts

Following

to
that

errors
When

of
a

display

such

severe

catastrophic

attempt,
infinite
1loop at IPL 31 (there is no
example
of
catastrophic
error
is
unable to locate any working memory.

error

magnitude
error

message

the

processor

halt

state

when

the

for

that

the

detected,

the

console

goes

an
An

into
MicroVAX).

console

program

Booting

and

Console

possible

enabling

halts

Program

bypass
and

Interface

all

diagnostic

manually

tasks.

halting

the

This may
processor

done

following

power-up
or
reset,
The
diagnostics
are
then
halted
and the
processor
enters
console
I/0
mode.
This option allows a field
service
engineer
to
bypass a failing test and enter console I/0
mode,
where
the console commands can be used to further diagnose
the problem.
As

part

each

diagnostic

subtest,

test

code

displayed

the
console
and
on
the LEDs, making it possible to monitor the
progress
of
the
diagnostics.
The
two
display
mechanisms use
unrelated logic, providing a high probability that at least one is
currently

operative.

hard

error

detected

by a

test,

diagnostic
message is displayed on the console. If a catastrophic
error
occurs,
it
may
not
be
©possible to display a diagnostic
message
the

the

console,

but

the

most

recent

test

code

left

the

LEDs,.

The

following

KA630-AA

[

significant

console

features

are

omitted

program.

Microstep

command

Not

supported

the

Microvax CPU

chip.

The

Load

Set command -- No set options are defined.

)

-- No

console
MCS

console

command -- Not

command -- No

displaying
echoing

command

supports

foreign

supported

console

the

1language

characters,

storage

device

MCS.

messages

supported.

the MicroVAX CPU chip.

storage device

Digital

supported.

This support extends to

with

MCS,

accepting and

and accepting a device attributes report

(the console queries the terminal to determine if it is a CRT)
However, all console
characters of MCS.
control
the Cl1
using
using the American National Standards
entered
be
commands must
Institute

the

message

{(ANSI)

subset.

terminal

does

not support MCS, the console uses English

texts.

four characters that are national
The console program uses
the caret ("), the backslash (\) and the
characters,
replacement
square brackets ([ ]). The caret is used by the
1left
right and
characters. The backslash is used to
denote control
to
console
console input. The square
editing
when
deletions
text
delimit
brackets are used to denote directory specifications when the user
the bootstrap to solicit a secondary bootstrap file name.
directs

provision

characters.

made

for

terminals

that replace any of these

CHAPTER

ARCHITECTURE

4.1

INTRODUCTION

This

chapter

contains

list

and
processor
registers
structures and formats, as
also described.
4.2
The

the

data

types,

implemented
by
well as MicroVAX

PROCESSOR STATE
processor state is stored

instruction groups

the KA630-AA. Register
memory management, are

processor

registers,

rather

than

in
memory.
This
section
describes the processor registers, the
general
purpose
register
set, and the Processor Status Longword
(PSL).
Nonprivileged
software
can
access
the
general purpose
register
set
and
the
Processor
Status Word (PSW, bits <15:00>
within
the
PSL). The processor registers and bits <31:16> of the
PSL

can

only

Processor

accessed

(MTPR)

privileged

and

Move

software,

From

using

Processor

the

Move

(MFPR)

instructions.

4.2.1

General Purpose Registers

There
are
16 general purpose registers, R0 through R15. The
of a register are numbered from right to left, 0 through 31.
The

following

registers

1is

R15

address
.

R14

1is

address
)

R13

R12

the

defined

Program

the

are

top

the

Counter

Pointer

the

VAX

architecture.

(PC).

instruction

8Stack

the

byte

(SP).

bits

The

the

The

contains

the

program.

processor-defined

contains

the

stack.

is the current Frame Pointer
(FP). The VAX procedure
call
convention
builds
a
data
structure on the stack
called
a stack frame. The FP contains the address of the
base of the stack frame.
is

the

convention

The

Argument

uses

Pointer

(AP).

data

structure

contains

the

address

The

VAX

procedure

call

termed

argument

list.

base

the

this

data

structure,

4.2.2
Processor Status Longword
The
PSL (Table 4-1, Figure 4-1) determines
the processor at any time.

the

execution

state

4-1

Architecture

Table

4-1

Processor

Status

Longword

Bit(s)

Mnemonic

Name/Meaning

Compatibility
Mode.*
as
0.
Loading
a
1

Description

This bit always reads
into this bit has no

effect.

Trace

<29:28>

Must

Pending.
Be

Zero.

FPD

First

Interrupt

<25:24>

CUR

Current

<23:22>

PRV

Previous Mode.

Must

<20:16>

IPL

Done.
Stack.

Mode,

Zero.

Interrupt Priority Level.

<15:08>

Part

Must

Zero.

Decimal
Overflow
read/write
bit
has
hardware.
It can be
emulates VAX decimal

Trap
Enable.
This
no effect on MicroVAax
used by macrocode
instructions.

Floating Underflow Fault

Integer Overflow Trap Enable.

Trace

Negative Condition Code.

Zero Condition Code.

Overflow Condition Code.

Carry Condition Code.

* Note

that

macrocode.

bit

compatibility

that

Enable.

Trap Enable.

mode

instructions can be emulated by

Since the emulation software runs in native mode, the
never

actually

set.

Architecture

313029282726252423222120
1

1615

080706050403 020100

TT1

LER

IPL

FPD | CUR

MBZ

SR
W

TIN|Z}V]C

MBZ

MOD

PRV

MBZ

MOD
e 15778

Figure

4.2.3

4-1

Processor

Status

Longword

(PSL)

Processor Registers

processor registers can be accessed through the MFPR and MTPR
The
privileged instructions. Each of the processor registers listed in
Table 4-2 falls into one of the following numbered categories.
1.

VAX

processor

registers implemented as described in the

VAX
Architecture
Reference
Manual (EK-VAXAR-RM)}.
registers are implemented by the MicroVAX CPU chip.

These

VAX
processor
registers
implemented
external
MicroVAX CPU chip by the KA630-AA logic.

the

Processor

(NOP)

registers

read

no operation

registers
(that
1is,

implemented
by
MicroVAX
CPU chip
registers
not described in the VAX

write.

Processor
uniquely

Architecture

Reference

Processor

results

reserved

Manual).

access not
operand

allowed.

fault.

Attempted access

Architecture

Table

4-2

Processor

Summary

Number

Mnemonic Type Category*

0
1
2
3
4
)
6
7

Kernel Stack Pointer
Executive Stack Pointer
Supervisor Stack Pointer
User Stack Pointer
Interrupt Stack Pointer
Reserved
Reserved
Reserved

KSP
ESP
SSP
usp
ISP

R/W
R/W
R/W
R/W
R/W

P0 Base Register

POBR

R/W

9
10
11
12
13
14
15
16

PO Length Register
Pl Base Register
Pl Length Register
System Base Register
System Length Register
Reserved
Reserved
Process Control Block Base

POLR
P1BR
P1LR
SBR
SLR

R/W
R/W
R/W
R/W
R/W

PCBB

R/W

1
1
1
1
1
5
5
1

System Control Block Base

SCBB

R/W

19
20
21

AST Level
Software Interrupt Request
Software Interrupt Summary

ASTLVL
SIRR
SISR

R/W
W
R/W

1R
1
1R

23
24

CMI Error Register
Interval Clock Control/Status

CMIERR
ICCS

R/W
R/W

25
26
27
28
29
30
31

Next Interval Count Register
Interval Count Register
TOY Register
Console Storage Receiver Status
Console Storage Receiver Data
Console Storage Transmit Status
Console Storage Transmit Data

NICR
ICR
TODR
CSRS
CSRD
CSTS
CSTD

W
R
R/W
R/W
R
R/W
W

3
3
3
3
3
3
3

33
34
35
36
37
38
39
40

Console Receiver Data Buffer
Console Transmit Control/Status
Console Transmit Data Buffer
Translation Buffer Disable
Cache Disable Register
Machine Check Error Summary
Cache Error Register
Accelerator Control/Status

RXDB
TXCS
TXDB
TBDR

R
R/W
W
R/W

R/W
R/W
R/W
R/W

2R
2R
2R
3
3
3
3
5

41
42
43

Console Saved ISP
Console Saved PC
Console Saved PSL
WCS Address

SAVISP
SAVPC
SAVPSL
WCSA

R/W
R/W
R/W

4
4
4

Interrupt Priority Level

Interprocessor Interrupt

Console Receiver Control/Status

IPL

IPIR

RXCS

CADR
MCESR
CAER
ACCS

R/W

1
1}
1
1
1
s
5
5

5
4R

Architecture

Table

4-2

Processor

Summary

(Cont)

Number

Mnemonic Type Category*

45
46
47

WCS Data
Reserved
Reserved

WCSB

R/W

SBI Fault/Status

SBIFS

R/W

49
50

SBI Silo
SBI Silo Comparator

3
3

SBI Error Register
SBI Timeout Address Register
SBI Quadword Clear
I/0 Bus Reset
Memory Management Enable

SBIMT

R
R/W

52
53
54
55
56

SBI Maintenance

SBIS
SBISC

SBIER
SBITA
SBIQC
JORESET
MAPEN

R/W
R
W
W
R/W

3
3
3
2
1

57
58
59
60
61

TB Invalidate All
TB Invalidate Single
Translation Buffer Data
Microprogram Break
Performance Monitor Enable

TBIA
TBIS
TBDATA
MBRK
PMR

W
W
R/W
R/W
R/W

1
1
3
3
3

63
64--127

Translation Buffer Check
Reserved

TBCHK

1
5

System

Identification

SID

5
5
5

R/W

* An
following the category number indicates that the
is cleared by power-up and by the negation of DC OK.

4.3

INSTRUCTION

instruction groups.
Integer

arithmetic

Address
Variable

SET

The MicroVAX CPU chip implements all
VAX

length

bit

and

instructions

in the following

logical

field

Control
Procedure

call

Miscellaneous

The
the

Queue
Character

string

moves

Operating

system

support

MicrovV Ax
emulation

BEdit

and

MOVCS)

CpPU
chip provides special microcode "hooks” to aid
of the following instruction groups by macrocode.

Character string
Decimal string
CRC

{(MOVC3

moves

(except

MOVC3

and

MOVCS5)

Architecture

The

following

instruction

chip.

FPU

F_floating

.
.

G_floating
D _floating

The

following

emulated

instruction
macrocode.

groups

are

implemented

groups

are

not

the

implemented,

MicroVAX

but

may

H floating

Octaword

Compatibility

mode

instructions

4.4

EXCEPTIONS AND INTERRUPTS
Both
exceptions
and
interrupts divert execution from the normal
flow
of control. An exception is typically handled by the current
process
(for example, an arithmetic overflow), while an interrupt
typically
interrupt

transfers
control outside the process
from an external hardware device).

Interrupts
4.4.1
The
MicrovVAX
architecture
(IPLs), as follows.

specifies

IPL

Condition

Nonmaskable
1F
1E

19~-1D

HALT L asserted
Unused
PWRFL L asserted
Unused

Unused

BIRQ7

asserted

BIRQ5

asserted

10--13

doorbell, or BIRQ4
Unused
Software interrupt

Interval timer

Console

01--0F

The

Q22-Bus

requests

interrupt

When
BIRQ7

terminal

after

interrupt

terminal

levels 4

interrupts,
L

interprocessor

asserted

request

through

interprocessor doorbell
timer

levels

set

IPL equal

17,

single grant does
levels and grants
set to 14 after a

interrupt.

is set

interrupt.

from
1its
own
console
SLU and from its interprocessor
(in
that
order
of
priority).
It
also
responds
to
requests from its own interval timer.

interrupt

corresponds

4-6

interval

priority

the
KA630-AA
is
confiqured as an auxiliary CPU it ignores
through
4
interrupt
requests, but does respond to IPL 14

requests
doorbell

The

example,

interrupt, BIRQ6 L asserted

since
the
(Q22-Bus has only one grant line. The
not
differentiate between the different request
the first requesting device it finds. The IPL is

console

(for

system

PSL

shown

(SIRR),

all

and

1is

controlled

<20:16>.),

the

Figure

the

Software

4-2,

the

Software

Interrupt

IPL

Interrupt

Summary

(IPL

Request

Architecture

0504

TYyTr17TrrrrrrrrrryrvTTd

IGNORED, RETURNS 0

kil

LR
PSL<20:16>]

0403

EEEREEEARREAEREERREREEEREEEBRER
IGNORED
REQUEST|

Lrr

0T 0T 1T 110
V1T T rrr1i
Trrrrtri1rrrrqrrry

{11 1141ty 41q)

:SIRR

1615

kil

:IPL

L.l

PENDING SOFTWARE INTERRUPTS

\FEDCBIAISET765432)!

:SISR

MBZ
wn1s779

Figure 4-2

Interrupt Registers

Exceptions

4.4.2

The MicroVAX architecture recognizes six classes of exceptions, as
follows.

Exception Class

Arithmetic

trap/fault

Instances

Integer overflow trap
Integer divide by zero trap
Subscript range trap
Floating overflow fault

Floating divide by zero fault
Floating underflow fault

Memory

management

Operand

reference

Instruction

execution

Access control violation fault
Translation not valid fault

Reserved addressing mode fault
Reserved operand fault or abort

Reserved/privileged instr.
Breakpoint

Tracing
System

Trace

failure

fault

Emulated instruction fault
Extended function fault
fault

trap

Memory read error abort
Memory write error abort
Kernel stack not valid abort

Interrupt stack not valid abort

Machine

check

abort

Architecture

4.4.3

Machine

response

are

pushed

onto

Check

Parameters

machine check,
the stack.

the

parameters

shown

BYTE COUNT {0000000C HEX)

Figure

4-3

(reported

:SP

MACHINE CHECK CODE
MOST RECENT VIRTUAL ADDRESS

INTERNAL STATE INFORMATION
PC
PSL

MR 15781

Figure

check

code

Machine

(FSD)

(SSD)

FPU error code 7
memory management

Undefined

status

memory management

(TB

miss)

status

Process

PTE

address

Process

PTE

Undefined

80
81

Read
Read

Write

bus

Write

bus

Internal

address

interrupt

Pl space
code

VAP is virtual address
VAP is physical address
error, VAP is virtual address

error,

virtual

Current
state

space

error,
error,

bus

recent

<31:00>

VAP

physical

contents

VAP

information:

<28:24>

Current

contents

ATDL

Current

<19:16>

contents

STATE

Current

contents

=
=

ALU

<07:00>

PSL:

address

address:

<23:20>

PC:

Parameters

Undefined
Undefined

I T

Impossible microcode state
Impossible microcode state
Undefined FPU error code 0

Most

Check

(hex):

O
E WN -

Machine

4-3

condition

codes
Current contents of VAX restart bit
PC
increment
at t he time of the exception
zero if FPD set in saved PSL)

<31:00>

the

Current

start

conten ts

the
of

current

PSL

instructions

Architecture

4.4.4

Halt Conditions

If
the
hardware
or kernel software environment becomes severely
corrupted,
the
chip may be unable to continue normal processing.
In
this
case,
the
chip
passes
control
to recovery code (the
console
program
described
in
Chapter
3) beginning at physical
address
20040000
(hex).
The
previous
state
of the machine is
stored in temporary registers that are read as processor
registers
using
the
MFPR instruction. The previous state of the machine
is
as follows,
1.
2.

IPR

contains
43

the

saved

contains

management

the

(MAPping)

IPR

console.psl

saved

IPR

console.psl

bit

IPR

console.psl

bits

IPR

contains

the

are

these

saved

must

process

Error

severe

and

contains

<14:08>

saved
and

<07:00>

the

saved

contain

interrupt

sets

For

accessed

the

stack

error

contain

MAPEN
error

the

bit.
code.

pointer.

that

before

use

the

using

example,

they

executing

registers

for

the

state

041F0000

(hex)

MAPEN

20040000

(hex)

ASTLVL

Unchanged

SISR

(set

Unchanged

(cleared

that

the

by
by

indicate

chip,

follows.

power-up)
power-up)

the

reason

for

the

halt

are

Condition

2
3

Assertion

4
5

Interrupt stack not valigd during exception
Machine
check
during
machine check or kernel

Halt

7
8
A
ig

memory

the

storage.

codes

restrictions

values,

Code

PSL

The
error
follows,

<31:16>

the

(MAPEN)

NOTE

There

instructions

halt

bits

PSL,
bit

PSL.

temporary

The

saved

ENable

code.
a.

PC.

Initial

not

external

hailt

power-up

valid

exception

instruction executed

stack

in kernel mode

SCB vector bits <01:00> = 11
SCB vector bits <01:00> = 10
CHMx executed while on interrupt
stack
ACV or TNV during machine check
exception
ACV

TNV

during

kernel

stack

not

valid

exception

4-9

Architecture

4.4.5
System Control Block
The
SCB
consists
of
two
pages
that
contain
the vectors for
servicing
interrupts and exceptions. The SCB is pointed to by the
SCBB
(Figure
4-4). The KA630-AA uses SCB device vector 204 (hex)
for
the
interprocessor
doorbell
interrupt.
The
SCB format is
described in Table 4-3.

31302928272625242322212019181716 15141312 1110090807 06050403 020100
TI

MBZ

ITTT T
T T I T

Figure

T
I T

PHYSICAL LONGWORD ADDRESS Of PCB

MBZ

4-4

System

Control

Table

4-3

System Control

Block

Base

Block

Number
Vector

Name

Unused

Machine

Kernel

Not

ocC

Type

Check
Stack

(SCBB)

Format

Parameters

Notes

Serviced

Abort
Abort

Valid

Power

:sCBe8

Fail

Interrupt

stack,
raised

IPL is
to 1F

IPL

raised

Reserved/
Privileged
Instruction

Fault

Extended

Fault

Instruction
18

Reserved

Operand

Reserved
Addressing

Access

XFC

Fault/

Not

always

recoverable

Fault

Mode

Control

Violation

is
1E

instruction

Abort
1C

interrupt

Parameters

virtual
address,
status code

are

Architecture

System Control Block Format

Table 4-3

vector

Name

Type

Translation
Not Valid

Fault

Number

(Cont)

Parameters

Notes

Parameters
are virtual
address,

status

Trace Pending

Fault

Breakpoint

Fault

Unused

Arithmetic

38--3C

Unused

Instruction

code

Compatibility
mode

Trap/

CHMK

Trap

CHME

Trap

CHMS

Trap

CHMU

Trap

50--5C

Unused

60--80

Unused

Software

Level

Interrupt

Software Level

Interrupt

Software

1Interrupt

Fault

Level

in VAX

Parameter
type

code

Parameter is
operand

word

Parameter is
operand

word

Parameter

operand

word

operand

word

Ordinarily

used for AST
delivery

Ordinarily
used

for

process

scheduling

90--BC

Software Levels
4

through

Interrupt

4-11

Architecture

Table

4-3

System

Control

Block

Format

Number
Vector

Name

Interval

Timer

(Cont)

Type

Parameters

Notes

Interrupt

IPL

(INTTIM
c4

Unused

Emulation

Start

Fault

Same mode
exception;
FPD

parameters

opcode,

are

PC,

specifiers
cc

Emulation
Continue

Fault

Same mode
exception;
FPD

parameters

DO--F4

Unused

Console

Receive

Interrupt

IPL

Console

Transmit

Interrupt

IPL

100-~1FC

Adapter

Vectors

Interrupt

Not

used

KA630-AA
200-~3FC

Device

Vectors

Interrupt

Correspond

bus

vectors

000

~--

1FC;

KA630-AA
appends the
assertion of
bit 9

4.5
HARDWARE DETECTED ERRORS
The
KA630-AA
detects
certain
error
conditions
during program
execution,
These
conditions
and
the
resultant
actions
are
described

4.5.1
If
in

below.

Nonexistent

Memory

the processor attempts a
local
memory
or
1I1/0

Errors
read or write
space, then a

to a nonexistent address
nonexistent memory error

occurs.

the

BDOUT)

that
in a

processor
a device

device within
machine check

attempts a read or
the Q22-Bus, and

write (by asserting BDIN
if BRPLY is not asserted

10 ps, a bus timeout error occurs.
abort and trap through vector 4.

This

or
by

results

Architecture

Parity Error Detection

4.5.2

parity errors can be detected during read operations from local
memory address space, Q22-Bus memory address space and Q22-Bus I/0
space.

page address

Memory System Error Register (MSER) bit 0 enables parity error
detection for all reads from local memory, whether it is accessed
through local memory address space or through the Q22-Bus memory
address space (through the bus map). MSER bit 0 has no effect on
parity

error

detection for reads from external Q22-Bus memory or

Q22-Bus devices.

puring read operations from the local memory address space, parity
is checked only for those bytes designated by the processor as
Byte Mask signals (BM, <03:00>). Because the MicroVAX chip must
receive a stable ERRor signal (ERR) at least 150 ns before it
requires stable data, performance considerations dictate that
parity errors occurring during reads from local memory address
space do not cause ERR assertion during the cycle for which the
parity error was detected. Instead, the KA630-AA asserts ERR for
the next cycle, and if that cycle was a prefetch read cycle, for
the cycle after that as well,

When a parity error occurs during a local memory access through
local memory address space, the processor is allowed to complete
that cycle and may execute an instruction that alters the
processor's internal state. However, the processor recognizes a
machine check and traps through vector 4 when it attempts the next
external

cycle.

During read operations from Q22-Bus space (including the access of
local memory through the Q22-Bus map), a parity error is detected
if both BDAL bits 17 and 16 are asserted. ERR is then asserted.
When the processor reads local memory from the Q22-Bus memory
space, parity is checked on both bytes of each word accessed, even
if the processor only requested a single byte.

When ERR is asserted, the processor responds as follows.

)
°

For nonprefetch reads, the processor recognizes a machine

check and traps through vector

For

prefetch

Prefetch

cycle

operations,
and

performs

the
a

processor

aborts

the

nonprefetch read if an

instruction fetch is required from that location.

4.5.3

Interrupt Vector

Timeouts

An interrupt vector timeout occurs when BRPLY L is not asserted by
a

device within 10 ps after an interrupt is acknowledged

the

interrupt

not

(BIAK L)

processor. The ERR is asserted. The processor aborts the

occur.

cycle and continues as though the interrupt request did

Architecture

4.5.4
A
No

Sack

within

BDMG

L).

Sack

Timeouts

timeout
us

The

occurs

after

KA630-AA

when
been

has

continues

a device does not assert BSACK L
granted bus mastership (received
as

though

the

DMA

occur.

4.6

LATENCY

4.6.1

Interrupt

Interrupt
interrupt

did

not

Latency

latency
1is
request (BIRQ

Interrupt

request

latency

defined
as
the time between receiving an
L) and acknowledging the request (BIAK L).

can

divided

into

the

following

three

segments.

)

The
1length
of
priority
1level
period is highly

time
the processor
that
masks out the
software dependent.

The
last

1length
of
instruction

time
after

The

1length

time

mastership.

Because

the
the

runs at an
interrupt.

processor takes
interrupt.

takes

the

arbiter

the KA630-AA
KA630-AA is

interrupt
This time

execute

to
the

the

gain bus
highest

priority
DMA
device,
this
period is equal to the time
required
for
the previous bus master to finish its data
transfer(s)
and
relinquish
the bus.
(This represents a
change
from the traditional priority structure where DMA
devices have a higher priority than either CPU fetches or
interrupts.) Eight block mode transfers typically require
about
5
ps.
The KA630-AA asserts DMA when it needs the
bus,
1limiting
a block mode device to no more than eight
additional
transfers.
A
nonexistent
memory
timeout
typically requires 10 to 15 ps.
4.6.2

DMA

Latency

DMA latency is
(BDMR
L)
and
made
assuming
control

requests.,

defined as the time between receiving a DMA request
granting the request (BDMG L). This calculation is
that
the
DMA
request
occurs
while the CPU has

the

The

latency.

The

bus,

and

that

there

result

this

calculation

DMA

the
CPU-induced
devices,

latency
1latency

The
CPU-induced
DMA
longest CPU operation
KA630-AA

operation

CPU

the

requests
exchange
one

that

bus,

is
it

by
the

any

device

latency

conflicting

1is
is

combination

induced

that

the
does

retains

lowest
not

control

non-block-mode

has

other

of
DMA

priority

regain

device

control

the

bus

completed

its

set

32-bit

memory.

relinquishes
the

bus

have been honored. Thus, two high bandwidth
control of the bus, effectively locking out

them

DMA

the CPU-induced

latency is the time required to complete the
that retains control of the bus. The longest

read-lock/write-unlock

When

seen
and

are

transfers.

until

control
all

devices
the CPU

DMA

could
until

Architecture

The arbiter KA630-AA CPU is the highest priority bus device in the
system. After it has relinquished control of the bus, it can
regain control of the bus during the next bus arbitration.
account the
System level DMA latency calculations must take into
fact that the arbiter KA630-AA can request the bus as the highest
priority bus device.

IDENTIFICATION REGISTER (SID)

SYSTEM
4.7
The read-only SID (Figure 4-5 and Table 4-4), processor register
, and
62, 1is implemented by the MicroVAX CPU chip. On the KA630-AA
on all other processors that use the MicroVAX CPU chip, the SID
always reads 00080000.

n
The KA630-AA implements a 32-bit System Identification Extensio
register (SIE) at physical location 20040004. This 32-bit register
exists within the KA630-AA console program ROM.

1514

2423

EEEEEERERERRREERRRRRRREREEE
RESERVED
VERSION
SYSCODE

T IO T

T T

0
T
0

O I

Y A

Figure 4-5

System Identification Register (SID)

Table 4-4

System Identification Register Format

Bits

Mnemonic

Name/Meaning

<31:24>

SYSCODE

System

Code. This field reads as 1 for the

KA630-AA.

<23:16>

Version number of console program ROM.

<15:00>

Reserved.

Architecture

4.8

MEMORY

4.8.1
The

MANAGEMENT

Physical
virtual

Figure 4-6. The
shown in Figure
4.8.2
Memory
MAPEN,

and virtual

address

space

physical
4-7.

Address

four

address

Space

gigabytes

space

one

(2**32),

shown

gigabyte

(2*#*30),

Memory Management Control Registers
management
1is
controlled
by
three processor registers:
Translation
Buffer
Invalidate
Single
(TBIS),
and

Translation
0, as shown

Buffer Invalidate
in Figure 4-8.

All

(TBIA).

MAPEN

contains

Translation

one

bit,

buffer invalidation is controlled by TBIS (Figure 4-9)
and
TBIA
(Figure
4-10).
Writing
a
wvirtual
address into TBIS
invalidates
any entry that maps that virtual address. Writing a 0
into TBIA invalidates the entire translation buffer.

00000000

MEMORY
SPACE
1FFFFFFF
20000000

1/0
SPACE

3FFFFFFF
wn.15932

Figure

4-6

Virtual

Address

Space

THE PO LENGTH REGISTER (POLR)

00000000

THAT
ES
THE LENGTH OF
SPECIFI

REGION IN PAGES.

PO
REGION

‘

PO REGION GROWTH DIRECTION

3FFFFFFF

40000000

P1 REGION GROWTH DIRECTION
P

REGION

ER
(P1LR)
| THE P1 LENGTH REGIST
——
S
LENGTH OF THAT
THEIFIE
SPEC

IN PAGES (2°*21-P1LR}.
REGION
THE SYSTEM LENGTH REGISTER

TFFFFFFF
80000000

(SLR) SPECIFIES THE LENGTH
OF THAT REGION IN PAGES.

SYSTEM
REGION
BFFFFFFF

SYSTEM REGION GROWTH DIRECTION

€0000000
RESERVED
REGION
FFFFFFFF
sz

Figure

4-7

Physical

Address

Space

Architecture

020100

llllll—lTTTllllllllilllllllllh"

m | :mapen

MBZ

Figure 4-8

Memory Management

(Mapping)

Enable Register

5
N

VIRTUAL ADDRESS

A
M

:TBIS

0
TIT

T
T I T

ITT

MBZ

Lyl

ZTBIA

elr

Translation Buffer Invalidate All Register

Figure 4-10

System Space Address Translation
4.8.3
A
virtual
address
with
bits
<31:30>
= 2
system virtual address

(sPT),

(TBIS)

Translation Buffer Invalidate Single Register

Figure 4-9

System

(MAPEN)

Refer

is an address in the

to Figure 4-11.

space is mapped by the System Page Table

address

virtual

which

space.

(TBIA)

is defined by the System Base Register

SBR
The
contains

(SLR).
Register
Length
System
address
of
the
SPT.
The
SLR

(SBR)

and the

the physical
contains
the size of the SPT in

longwords,
that is, the number of Page Table Entries (PTEs).
The
PTE
addressed
by
the
SBR maps the first page of system virtual

address
4.8.4

space,

that

Process

is,

Space

virtual

Address

byte address

80000000

(hex).

Translation

A
virtual
address
with
bit 31 = 0 is an address in the process
virtual
address
space. Process space is divided into two equally
sized,
separately
mapped regions. If virtual address bit 30 = 0,
the
address
1is
1in region PO. If virtual address bit 30 = 1, the
address

4.8.4.1

PO
Region
Address
Translation -- Refer to Figure
region of the address space is mapped by the PO Page

The

(POPT), which

region

Length
Register
address
of
the
longwords,
that
POBR
maps
space, that

Pl.

defined

the

Base

(POBR)

and

4-12.

Table
the

(POLR).
The
POBR
contains
the system virtual
POPT.
The POLR contains the size of the POPT in
is, the number of PTEs. The PTE addressed by the

the

first

is,

virtual

page

byte

the

address

region
0.

the

virtual

address

Architecture

109

1.0

LIS

MB2

3
LS

MBZ | :SBR

1.0

A
A
0
LENGTH OF SPT IN LONGWORDS

T
T T T

SVA:
[SYSTEM
VIRTUAL

ADDRESS)
3

B
‘SLR

7T
T T I
T

T[TT T

A O

TTTT

BYTE

B A

B B

R O

EXTRACT AND

CHECK LENGTH

3f2

T T

T O

2}2

T[T
T T T

T
T T T

2410
I

0
T

MBZ

LIS

TIT

PHYSICAL LONGWORD ADDRESS OF SPT

0
T

ADD

SBR:

LS,

PHYSICAL BASE ADDRESS OF SPT
et

ety

YIELDS

PHYSICAL ADDRESS OF PTE

10
TTI I

PTE:

TT I

DL L B

rreappp

bty

FETCH

0
T

TT T

PFN

CHECK ACCESS

OF DATA:

THIS ACCESS CHECK

PHYSICAL ADDRESS

IN CURRENT MODE

L B AL L

e et
b
i

Figure

4-11

System
Address

Space Virtual
Tran slation

Physical

<593

Architecture

1t 0

TIT 11T TP

MBZ

T 1T 11T 111

[¢]
PVA:
(PROCESS VIRTUAL bl

ADDRESS)

iroryd

MBZ | :POBR

T 1T P T

T T T 1T T

1T 1T 11717

1T T

LENGTH OF POPT IN LONGWORDS

1T 1T T

POLR

9 8

] T

A T

11T

BYTE
O O

EXTRACT AND

CHECK LENGTH

212

1T T T
0
T T T

2
9

3 3
10

S N

MBZ

TTr T

SYSTEM VIRTUAL LONGWORD ADDRESS OF POPT

3i2

T T TTTTITT

T ] T

2410

iTrrlT

Y O

ADD

POBR

T
Ty T
rr T Ty 11t
117117

Tttt
U

VIRTUAL BASE ADDRESS OF POPT

TR
U

U NU T

0 O
O M B

YIELDS

VIRTUAL ADDRESS OF PTE

AN
O

NN U

0
O

FETCH BY SYSTEM
SPACE

2 2

KERNEL MODE ACCESS CHECKS.

TTT T TTT T
PTE:

TRANSLATION ALGORITHM,
INCLUDING LENGTH AND

0
T

111

PFN

R
I T A

CHECK ACCESS

0
U

AU€

THIS ACCESS CHECK

IN CURRENT MODE

PHYSICAL ADDRESS

OF DATA

MR 15938

Figure

4-12

PO Virtual to Physical Address Translation

Architecture

4.8.4.2

Pl
Region
Address
Translation -- Refer to Figure 4-13.
region of the address space is mapped by the Pl Page Table
which is defined by the Pl Base Register (P1BR) and the Pl
Register
(PlLR).
Because
Pl
space grows toward smaller

The
Pl
(P1PT),
Length

addresses, and because a consistent hardware interpretation of the
base and length registers is desirable, P1BR and PlLR describe the
portion
of
Pl
space
that
is
not
accessible.
Note that PILR

contains the
address
of
is,
wvirtual
not
PTEs

number of nonexistent PTEs. P1BR contains the virtual
what
would be the PTE for the first page of Pl, that
byte
address 40000000 (hex). The address in PlBR is

necessarily
must

a valid physical address,
valid physical addresses.

but

all

L L

the

addresses

mBz

S8W

S U

0 W U(0 O

L LS

AR B

MBZ | :P1BR

AN O

TT T

MBZ

1.0

PVA:

(PROCESS VIRTUAL

TT T

TT TT T

LENGTH OF P1PT IN LONGWORDS
ey

TTITT

:PILR

BYTE

EXTRACT AND

CHECK LENGTH

3|2
L

eyttt

242

T[T

L L

bbb

ADDRESS)

LSS

VIRTUAL LONGWORD ADDRESS OF P1PT

2] 10

0
B

L B0 O

byt

ADD

TT T

P1BR:

T I

TT T

VIRTUAL BASE ADDRESS OF P1PT
Ll

rid

YIELDS

TTT T

T
T T T

YTT T

TT T

T
I T 1T

VIRTUAL ADDRESS OF PTE

Lttt

bbbyt

FETCH BY SYSTEM
SPACE

2 2

KERNEL
MODE ACCESS CHECKS.

L
PTE:

TRANSLATION ALGORITHM,
INCLUDING LENGTH AND

A G

0
O

PEN

I ST
CHECK ACCESS

PHYSICAL ADDRESS

OF DATA

WO S

THIS ACCESS CHECK

IN CURRENT MODE

jO U O

O W

U U

T T U

9ls

T[T

T T

1111

S O O

|
wa 15530

Figure

4-13

Virtual

Physical

Address

Translation

Architecture

Page Table Entry
4.8.5
The format of a valid PTE is shown in Figure 4-14, where:
v
PROT
M
OWN
PFN

I1f

bit

=
=
=
=
=

Valid bit (must be set)
Protection code
Modify bit
Owner bits
Page frame number,

is clear, the format of the remaining bits

(the V bit)

is not examined by the hardware.

33
10

22222222
76543210
T
\
L

proT

|m|ofowN o

11
1 e e e

PFN

Figure

4.9

0
L

Page Table

4-14

KA630-AA MEMORY

Entry

:PTE

(PTE)

SYSTEM

The
KA630-AA
memory
system
consists
of the local memory and a
Q22-Bus
map
that
allows
Q22-Bus
master devices to access this
local
memory.
The memory system also includes two registers that
are

used

primarily

for

diagnostic purposes.

The KA630-AA

supports

up
to
9
Mbytes of local memory. The KA630-AA typically accesses
this
memory
directly,
through
physical
addresses
00000000 to
O0FFFFFF.
Any
Q22-Bus master device, including the KA630-AA,
access this memory indirectly through the Q22-Bus map. Mapping
be

independently

The

KA630-AA

physical
I/0 space

enabled

and

accesses

the

disabled

for

each

page.

(Q22-Bus memory address space

addresses
30000000 to 303FFFFF. It
through physical addresses 20000000

registers

Figure 4-15 and Table
of Q22-Bus space into
Each

mapping

written

can

only

load

longword

these

32-bit

longword

with

the

Each

format

4-5, and each one can map a page
a selected page of local memory.

using

located

instructions.

registers

with

longword

boundary
word

and

data.

Q22-Bus

these

shown

(512

Byte

undefined

through

accesses the
to 20001FFF.

4.9.1
Local Memory Mapping Register Format
The
Q22-Bus
map
contains
8192 mapping registers.

mapping

can
can

bytes)

and

must

instructions

Architecture

1t 0

Trrrrrrrrrr

5 4

TTT T T
T
A23-A09

llllllllllllllllllllllllllll

Fiqure

Table

4-15

4-5

Mapping

Memory

PFormat

Bit(s)

Mnemonic

Name/Meaning

valid.
When a mapping register is selected
by
a
Q22-Bus
address,
the
wvalid
bit
determines
whether
the
Q22-Bus
map
is
enabled
for that address. If the valid bit
is
set,
the
map is enabled. If the valid
bit
1is
clear, the map is disabled and the
KA630-AA does not respond to that address.

<30:15>
<14:00>

Unused.
A23--A09

Address

These

bits

always

read

<23:09>.

When

physical address of
address bits <14:02> are
of the page they map.

each

mapping

bits

through

as local memory
Q22-Bus address
as local memory

4.9.2
Mapping Register Addresses (2008XXXX Hex)
The
mapping
registers
(Table
4-6) are located within
register
space
at
physical addresses 20088000 through
They can only be accessed from the processor.
The

1is selected by a 022-Bus address,
that
register's valid bit is set,

then these 15 bits are used
address
bits 23 through 9.
bits
8
through 0 are used

address

the local
2008FFFC.

Architecture

Table 4-6

Mapping Register Addresses

Q022-Bus Addresses
Mapped (Hex)

Q22-Bus Addresses
Mapped (Octal)

20088000
20088004
20088008
2008800C

000000--0001FF
000200--0003FF
000400~--0005FF
000600--0007FF

00000000--00000777
00001000--00001777
00002000--00002777
00003000--00003777

20088010
20088014
20088018
2008801C

000800--0009FF
000A00~--000BFF
000C00--000DFF
000E00--000FFF

00004000--00004777
00005000--00005777
00006000--00006777
00007000--00007777

2008FFF0
2008FFF4
2008FFF8
2008FFFC

3FF800--3FFOFF
3FFAQ00-~-3FFBFF
3FFC00--3FFDFF
3FFEQ0--3FFFFF

17774000--17774777
17775000--17775777
17776000~--17776777
17776000--17777777

022-Bus Map Operation

4.9.3

Q22-Bus mapping registers, including
powver-up,
At
bits,
are
undefined. External access to local memory is
as long as the IPCR LM EAE bit is cleared.

the valid

disabled

completing the ROM diagnostics that are part of its console

After

program,

an arbiter KA630-AA enables the mapping registers to map

sufficient

EAE

space to boot the system, and then sets

memory

bit. When the operating system gains control, it may

the

Upon

completion,

the ROM programs in an auxiliary KA630-AA clear

The

(22-Bus

map

monitors each Q22-Bus cycle and responds if the

either invalidate or reassign various pages, as required.

all mapping register valid bits, and then set the LM EAE bit.
following

three

conditions

The

The valid bit of the selected mapping register

For

read

EAE

bit

met:

IPCR

are

operations,

mapped

into

checking

for

set.

existent

the

mapping

local

memory.

is set.

must have

(During

write

operations, the response depends only on conditions 1 and
BRPLY before
Q22-Bus
returns
KA630-AA
the
because
2
existent

local

memory.)

Architecture

2
1

022-BUS ADDRESS

L1t

O B B
8YTE

[

L1t

tf1

EXTRACT AND

USE TO SELECT
MAPPING REGISTER

SELECTED MAPPING REGISTER:
33
1

LIS

vyt

3
LI I A

9'g
I

0
O

PHYSICAL ADDRESS OF LOCAL MEMORY

MR-15942

Figure

4-16

Q22-Bus
Address

The

translation

address

shown

from
in

Q22-Bus

Figure

to Local Memory
Translation

address

Physical

local

memory

physical

4-16.

4.9.4
Memory System Registers
The
three registers associated with the memory system are located
in
the
local register I/O address space and can only be accessed
by
the
on-board
processor.
Software
uses
the MSER to monitor
parity
and
nonexistent
memory
errors,
and
to
control parity
generation
and
checking
for
the
1local
memory.
The CPU Error
Address
Register (CEAR) contains the address of the page in local
memory that caused a parity error during an access by the on-board
CPU. The DMA Error Address Register (DEAR) contains the address of
the
page
in
1local
memory
that caused a parity error during an
access by an external device.
4.9.4.1

Memory

(Figure
address

4-17,
space

Table
4-7)
at
physical

accessed

on-board

the

System

MSER bits <07:05> and
through
SCB
vector
device
memory.

receives

Error

(20080004

Hex)

1is
1located in the local
address
20080004.
It

The

MSER

processor.

3 indicate the
4.
MSER bit 4
parity

error

status
is set
while

of
if

machine check traps
an external Q22-Bus

reading

KA630-AA

local

Architecture

09876543210

TrTrIT7

[N U

1ty

1T T

UNUSED, RETURNS 0
S
T T
U

TTd

Y W

MEM CD?

MEM CDO
CPU NXM

CPU LPE
CPU QPE

CMA QPE
MS LEB

WRW PAR
PAR ENB
MR.15343

Bit(s)

Figure 4-17

Memory System Error Register (MSER)

Table 4-7

Memory System Error Register Format

Mnemonic

Unused. Reads as 0.

<31:10>

09
08

Name/Meaning

MEM CDl
MEM CDO

Memory Code <01:00>. When one of the two CPU
parity error bits (MSER <06:05>) is set, thea

two read-only MEM CD bits are loaded with
2-bit code indicating the source of the parity

error,

follows.

MEM CD <09:08>

022-Bus memory or device

KA630-AA on-board memory

Memory expansion module 1
Memory expansion module 2

10
11

Source

second

parity

error

does not update this

CPU
code unless software has cleared the
are
parity error bits. MEM CDl and MEM CDO
OK,
DC
of
on
negati
the
by
up,
powerby
d
cleare
and by writes to the BIR.

CPU NXM

CPU

Nonexistent Memory Error. This bit is set

operation
by any CPU nonprefetch read or write
ng a
that references nonexistent memory, causi
1 to this
trap through SCB vector 4. writing a bit
no
bit clears it; writing a 0 to this -up, has
the
by
power
by
ed
clear
is
NXM
CPU
effect.
negation of DC OK, and by writes to the BIR.

Architecture

Table

4-7

Bit(s)

Mnemonic

CPU

LPE

Memory

System

Error

Address

Space

Format

(Cont)

Name/Meaning
CPU

Local

parity

error

set),

then

detection
CPU

LPE

access

(prefetch

memory

address

error.

The
indication
cycle
1is
vector
writing
by

4.
a

Only

bit

0
set by any CPU read
nonprefetch)
to
local
that

causes

parity

does

a 1 to this
effect. CPU

bit
LPE

negation

by the
BIR.

the

memory

bytes

<03:00>

can

error.

Writing
has no

those

outputs

(MSER

not receive an error
on
that
cycle. The next MicroVax
aborted, causing a trap through SCB

power-up,

writes

Error.

enabled

space

processor

Parity

Because

the

clears it;
is cleared
OK,

and

selected by processor
a CPU LPE parity

cause

fetch

that

parity

caused

the

error
1is
not
aborted,
it
could be
difficult for software to determine the result
of
the
error. For this reason, parity errors
that
set
this
bit
are generally treated as
fatal errors.
05

CPU

QPE

CPU

Q22-Bus

Address

QPE
1is set by
to the Q22-Bus
parity
error
vector

Space

any CPU
address
causing

the

CPU

accessing

through

the

(22-Bus

map,

enabled

only

bit

MSER

Parity

Error.

CPU

nonprefetch read access
space that results in a
a CPU trap through SCB
parity

local

memory

detection

set.

the

is
CPU

is
accessing the Q22-Bus, parity detection is
enabled
or
disabled
at the external Q22-Bus
memory
or
device.
Writing
a
1 to this bit

DMA

QPE

clears

it;

effect.

CPU

QPE

negation

OK,

DMA

writing

(Q022-Bus

cleared

and

Address

this

writes

Space

bit

power-up,

Parity

the

has

the

BIR.

Error,

parity
error detection is enabled (MSER bit 0
set), then DMA QPE is set by any external read
access
to
KA630-AA local memory that results
in
a
parity error. This type of parity error
does

4.
an

not

(The
error

cause

the

CPU

trap

through

SCB

vector

DMA device typically interrupts with
indication.) Writing a 1 to this bit

clears
1it;
effect. DMA
negation of

writing
a
0
to this bit
QPE is cleared by power-up,
DC OK, and by writes to the

has no
by the
BIR.

Architecture

Table

4-7

Memory

Bit(s)

Mnemonic

LEB

System

PAR

OK,

and

ENB

Read

writes
as

the

BIR.

Os.

Write

Wrong Parity. If this
set, and either the CPU or a
to
local memory, then wrong
into
the parity bits of the

is
is
DC
PAR

(Cont)

System Lost Error Bit. This bit is set
by
an operation that sets MSER bit 6 or bit 5
after
one
or
both of those bits has already
been
set.
Writing a 1 to this bit clears it;
writing
a 0 to this bit has no effect. MS LEB
is
cleared
by power-up, by
the negation of

Unused.

Format

Memory

WRW

Name/Meaning

Error

read/write bit is
DMA device writes
parity is written
RAMs, If this bit

clear,
correct parity is written. WRW PAR
cleared
by
power-up, by the negation of
OK, and by writes to the BIR.

Parity
Enable, If this read/write bit is set,
local
memory
parity
error
detection
is
enabled.
If
this bit is clear, parity errors
are
1ignored during all CPU and DMA reads from
local

memory.

PAR

ENB

negation

OK,

the

cleared

and

power-up,

by writes

the

BIR.

PAR
ENB controls parity detection for all CPU
reads
from
local
memory, including accesses
through the Q22-Bus map. PAR ENB has no effect
on CPU reads from external Q22-Bus memory.

4.9.4.2
located
address

CPU
in

(CPU

physical

It
can
only
be
accessed
by
the
contains valid information only when either

on-board
MSER bit

20080008.

processor
6

Error
Address Register -- The CEAR (Figure
the
1local
register
I/0
address
space at

and

LPE)

MSER

bit

(CPU

QPE)

4-18)

set.

UNUSED, RETURNS 0

LOCAL MEMORY

ADDRESS BITS <23:09>

MR- 15944

Figure

4-18

CPU

Error

Address

(CEAR)

Architecture

The

CEAR

caused

contains

parity

the

address

error

during

the

page

access

the

local

memory

on-board

contents

MSER
bit
effect on

5 is set. Additional local memory parity errors
the CEAR until software clears MSER <06:05>.

Local

this

memory

address

<14:00>.

CEAR

4.9.4.3
located

DMA
in

address

2008000C.

processor

and

QPE)

The

DEAR

bits

are

bits

<31:15>

latched

<23:09>

always

are

read

contents

contains

contains
parity
of

can

only

valid

memory

DEAR

loaded

MSER

into

the

error

this

address

during

only

the

access

are

address

bits

<31:15>

page
by

1latched

<23:09>

always

read

bit

The
6

have

CEAR

bits

accessed

information

Additional
1local
memory parity errors
until software clears MSER bit 4.

<14:00>.

either

Error
Address Register -- The DEAR (Figure
the
1local
register
I/0
address
space at

set.

caused

Local

when

that

CPU.

are

the
MSER

local

external

when

have

when

4-19)

MSER

1loaded

on-board
bit

(DMA

memory

that

device.

bit

effect

physical

set.

the

DEAR

bits

into

The

LOCAL MEMORY

UNUSED. RETURNS 0

ADDRESS BITS <23:09>
MR-15945

Figure

4-19

DMA

Error

Address

4.9.5
Memory System Operation
KA630-AA memory system can perform
and memory refresh cycles.

The

the

following

MicroVAX

accesses

local

memory

directly.

MicroVAX

accesses

local

memory

through

)

MicroVvAX
Q022-Bus

[
°

MicroVAX
External

Q22-Bus
°

External

Q22-Bus
°

KA630-AA

accesses
I/0

on-board

address

(DEAR)

registers

data

transfer

Q22-Bus map.
in

the

local

space.

accesses

Q22-Bus

(Q22-Bus

device

memory

accesses

registers,
local

memory

through

map.
Q22-Bus

I/0

device

accesses

the

KA630-AA

space.

performs

memory

refresh

cycle.

IPCR

the

Architecture

NOTE

KA630-AA does not require access to
The
accesses
it
when
system
memory
the
processor registers (including
internal
the
to
external
implemented
those
MicrovAax CPU chip).

Access

the local memory data/address paths and control of the

control

the

are arbitrated independently. An external device can gain

022-Bus

space)

address

022-Bus

-and

access a KA630-AA register (in the

while the MicroVAX CPU chip is accessing

local memory. When an external device accesses KA630-AA local
memory, MicroVAX cycles are not interrupted until the Q22-Bus map
has decoded the local memory address.

When the local memory is between cycles, it continually decodes
the address on the MicroVAX address/data lines. When it receives a
refresh or external device request, it switches off the MicroVAX
address/data lines and monitors the address lines from the refresh
from the Q22-Bus map.

logic or

local memory is between cycles, the arbitrator for the
memory responds to requests in the following order of

the

When

local

priority:
1.

MicroVAX

Refresh

request

External device

request

When the local memory is completing a cycle, the arbitrator for
the local memory responds to requests in the following order of
priority:

1.
2.
3.

The

1local

refresh

The
out

External device request
Refresh request
MicroVAX request

time

cycle

memory

400 ns for all read, write or

cycles.

MicroVAX must have control of the Q22-Bus before it can carry

the

following
Perform

Access

actions.

any

local

read-lock

memory

the IPCR or

Perform

Q22-Bus

cycle

through

one of

the Q22-Bus map

the Q22-Bus.map registers

cycles

On an arbiter KA630-AA, which contains the Q22-Bus arbitrator, the
control of the Q22-Bus except when the KA630-AA has
has
MicroVAX
granted
an
external
DMA request. An auxiliary KA630-AA can gain
control

the

Q22-Bus

only

posting

DMA

request.

Architecture

The

MicroVAX
accesses
Q22-Bus
following Q22-Bus cycles.
°

DATa-Out-Byte

DATa-In

)

DATa-Out

DATa

Block

DATa

Block

Out

)

DATI

a
°

(DATI)

and

registers

for

8-bit

writes

16-bit

reads

(nonlocked)

for

16-bit

(DATBI)

followed

DATBI

for

(DATO)

16-bit

(DATOB)

memory

for

using

the

writes

32-bit

reads

(DATBO)

for

32-bit

for

DATO

(nonlocked)

writes

16-bit

read-lock

followed

write-unlock

followed

32-bit

DATBO

for

32-bit

read-lock

followed

write-unlock

When
performing
32-bit
reads
from
non-block-mode
memory, two
successive
DATI
cycles are substituted for the DATBI cycle. When
performing
32-bit
writes
to
non-block-mode
memory,
the
two
successive
DATO
cycles
are
substitued for the DATBO cycle. The
same substitutions are made for the 32-bit read-lock followed by a
32-bit
write-unlock.,
In
all
three
cases, the KA630~-AA retains
control of the bus between successive DATI and/or DATO cycles.

When
the
performs
byte

processor
reads
DATI cycle with

a byte
address

from the Q22-Bus, the KA630-AA
bit 0 correctly reflecting the

address.

4.10
The

KA630-AA BOOT AND DIAGNOSTIC
KA630-AA

and

read-only

and

two

28-pin

memory.

boundaries
references.

and

The
KA630-AA
bytes
of
ROM
console

boot

The

may

ROM

the

accessed

new

ROM

facility

sockets

memory

populates each
(or
EPROM).

program.

applications,

FACILITY

diagnostic
is

for

located

through

of the
These

two
two

features

16,

32
on

one

16-bit

Kbytes

consecutive

longword,

word

ROM sockets with
ROMs contain the

these

ROMs

are

replaced

must

contain

some

version

for

32
64

word

byte

K X 8
Kbyte

special

the

console

physical

program,

4.10.1
The

Boot and
16-bit
BDR

address

20080000.

Diagnostic Register
(Table
4-8, Figure
It

can

accessed

4-20)
by

by
external
Q22-Bus
devices.
The
BDR
diagnostic
ROM
programs
to
read various
bits

and

load

the

4-bit

error

located

KA630-AA

display.

software,

but not
allows
the
boot
and
KA630-AA configuration

Architecture

4-8

Table

Boot

and

Diagnostic

Bit(s)

Mnemonic

Name/Meaning

PWR

Power

OK.

Q22-Bus
BP OK is

HLT ENB

This

read-only

signal

Format

bit

asserted

set

and

the

clear

negated.

Halt
Enable.
This read-only bit reflects the
status
of
external connector pin 15. The set
condition
of
this signal enables the various

external
halts. Also, following the execution
of
a
halt
instruction
in
kernel mode, the
KA630-AA
ROM program reads the HLT ENB bit to
decide
whether
to
enter the console program
(HLT
ENB
set)
or
to
restart the operating
system (HLT ENB clear).
Unused.

<13:12>
11
10

CPU
CPU

CD1
CDO

Always

the

arbiter

CPU CD

<11:10>

00
0l
10

CD1
CDO

or
as
follows.

one

the

three

Configuration
Arbiter
Auxiliary
Auxiliary
Auxiliary

BDG
BDG

CPU
Code <01:00>,
These two
read-only
bits
originate
from
connector
pins 4 and 5. They
indicate whether the KA630-AA is configured as
auxiliaries,

09
08

reads

1
2
3

Boot
and Diagnostic
Code <01:00>, This 2-bit
read-only
code
reflects
the
status
of
configuration
and
display
connector
pins
<14:13>,

<07:04>

03
02

01l

Unused.
DSPL
DSPL

03
02

DSPL 01
DSPL

Always

reads

Display
<03:00>.
These
four write-only bits
update an external LED display. Writing a 1 to
a bit
1lights the corresponding LED; writing a
0 to a bit turns its LED off. The display bits
are
set (all LEDs are lit) by power~up and by
the

negation

OK.

Architecture

PWR OK —]

HLT ENB

CPU CD1

CPU CDO

8DG CD1

BDG CDO

DSPL 03
DSPL 02
DSPL 01

0SPL 0O
MR-15946

Figure

4-20

4.10.2

ROM Memory

4.10.2.1

ROM

and

Sockets
K

input

address

bit

Boot

=--

byte

(for

and

The

two

ROMs.

(for

(BDR)

compatible

with 8,
selects the

jumper

and

parts)

ROM

with

the

diagnostic

ROM

parts).

The
KA630~AA
jumper in the

is
shipped
with
32 K
address bit 14 position,

4.10.2.2

Address

ROM

ROM sockets are
machine-inserted

either
K

Diagnostic

Space

The

byte

ROMs,

entire

boot

and

can be read from either the 64 Kbyte halt mode ROM space or
Kbyte run mode ROM space. Writes to either of these address
result in a nonexistent memory trap.
Any

I-Stream

halt

to
Any

the

read

mode.

from

The

MicroVAX

I-Stream

CPU

the

front

chip

read

halt

panel

that

the

Writes
run

MicroVAX

and

mode/halt

CPU

chip

does

D-Stream
mode

reads

status.

ROM

light

space

places

off

and

the

KA630-AA

the

halt

input

mode

ROM

space,

disabled.

including
reads
from the run
in
run
mode. The front panel
to

mode

Run

the 64
spaces

not

access

the

halt

mode ROM space, places the KA630-AA
Run light is 1lit and the halt input

reenabled.

any

address

space

have

effect

Architecture

include all instruction fetches (except when the
I-Stream reads
MicrovAX CPU chip retries a fetch following a nonexistent memory
or parity error) and certain character string data fetches (again,
except for those retries that follow an error). All reads that are
not I-Stream reads are D-Stream reads. When running in halt mode,
the ROM programs cannot use character string instructions to fetch
data from outside the halt mode ROM address space.

when

Kbyte

halt

2004FFFF).

appears

space.

mode,

ROM

mode

the KA630-AA always responds to the full 64
addresses

(hex

space

20040000

through

When the KA630-AA contains 16 Kbytes of ROM memory, it

once within each 16 Kbytes of halt mode ROM

times,

four

When

the

KA630-AA

mode,

the

contains 32 Kbytes of ROM memory, it

appears twice, once within each 32 Kbytes of ROM space.

When

run

KA630-AA always responds to the full 64

through
20050000
(hex addresses
mode ROM space
run
Kbyte
When the KA630-AA contains 16 Kbytes of ROM memory, it
2005FFFF).
run mode ROM space. When the
the
times within
four
appears
KA630-AA contains 32 Kbytes of ROM memory, it appears two times
within

the

memory

ROM

space.

Note that the run mode ROM space

accesses the same ROM code as the halt mode ROM space.

4.10.2.3 KA630-AA Console Program Operation -- The console program
is entered by transferring program control to location 20040000.
cause the MicroVAX to
that
conditions
There are various halt

transfer
include

external

halt

to location 20040000. These conditions

control

program

the

instruction,

halt

mode

kernel

machine checks. When DC OK has been negated,

reboot,

the

program execution

assertion

combined

assertion

the

to the MicroVax CPU chip, and certain fatal

input

location

either at power-up or

of DC OK and P OK initiates

20040000.

The KA630-AA console program provides the following services,
[

[

Automatic

restart or bootstrap following processor halts

power-up

Interactive command language allowing the user to examine
and

)

]

initial

alter

the

state

Diagnostic

tests

the

system

memory

Support
as

The KA630-AA

the

executed
and

the

processor

on power-up
Q22-Bus

that check

the CPU,

map

of video or hard-copy console terminals, as well

support of VCBOl-based bitmapped
console

program

described

terminals

detail

in Chapter

Architecture

4.11

KA630-AA

TOY

CLOCK

4.11.1
Battery Backed-Up
The
KA630-AA
contains
a
battery

backup

mounted

J2.

than
240
series.
The

Chip

Motorola*

circuitry

that
distribution

the CPU
battery
backup

The

Watch

hours

when

for

CMOS

connected
panel through

this

using

MC146818

are

chip

three

watch

to three
KA630-AA

specified

nickel~cadmium

chip

and

batteries
connector

greater

batteries

operating

system
software
must fetch the correct time from
whenever power is restored to the system. If the power
long
enough
for
the
battery
voltage
to
go
below
specification,
or
if
the
battery
was temporarily disconnected
while
the
system
power
was
Off, the time in the watch chip is
undefined. If the operating system detects a cleared Valid RAM and
Time
bit
(VRT, in watch chip register CSR D), it must prompt the

this
was

chip
Off

system

watch

operator

Although
of

for

the

time,

and

then

load

this

time

into

the

chip.

the
ms,

Therefore,

MicroVAX
the

the

While

After
chip

interval

watch

time

chip

resolution

under

full

powered

follows.

supply --

for

interrupts
has

power

power-down
is

timer
only

1less

battery)

than
--

have

resolution

resolution
of

seconds.

ms
240

hours

(while

watch

second

4.11.2
Watch Chip Registers
watch
chip
contains
64 8-bit registers (Table 4-9). Ten of
these
registers
contain
time
of
day
data and 4 are CSRs. The
remaining
50
provide 50 bytes of battery backed-up RAM. They are
addressed
from
a
base
address of 200B8000, as described in the
following sections.
The

Even

though

RAM

locations

the

addressing

are

loaded

into

word

boundaries,

read

out

the

TOY

chip

data

byte

and

time.

4.11.,2.1 TOY
Data
Registers
-Software
reads
the
TOY
data
registers
(Table
4-10)
only
after
reading a cleared Update In
Progress
bit
(UIP, CSR A bit 7) and only when all interrupts are
disabled.
(This
assures
that
reading
of
the registers is not
delayed
beyond
the
time for which they are valid.) When the UIP
bit
is clear, the contents of these registers is guaranteed to be
stable

for

Software

least

1loads

the

244

TOY

us.

data

registers

only

after

setting

the

SET

bit
(SET,
CSR
B bit 7). After loading the correct time and date
into
the
TOY
data registers, software loads 20 (hex)
into CSR A
and then clears SET by loading 6 into CSR B.

Motorola

registered

trademark

Motorola,

Inc.

Architecture

Table

4-9

Watch
Address

Chip Registers

Offset

Number

Function

From Base Address

Comments

Seconds

Used on reads only

Second alarm

Not used

Minutes

Loaded and read

Minute alarm

Not used

Hours

Loaded and read

)

Hour alarm

Not used

Day of week

ocC

Not used

Date of month

Loaded and read

Month

Loaded and read

Year

Loaded to produce
28th or
(not

29th day Feb.

read

by VMS)

CSR A

Loaded and read

CSR B

Loaded and read

CSR C

Not used

CSR D

Read-only

lst

byte

RAM

1Cc

Uses assigned by the

ROM code

50th

byte

Table

4-10

RAM

Time-of-Year Data

Decimal

Hexadecimal

Address

Units

Range

200B8000

Seconds

0--59

00--3B

200B8004
200B8008

Minutes
Hours

0--59
0--23

00--3B
00--17

200B8BOOE

Day of month

1--31

01--1F

200B8010
200B8012

Month
Year

1--12
0--99

01--0C
00--63

Architecture

4.11,2.2 Control
and
Status
Register
A
-- CSR A (Figure 4-21)
contains the UIP, the divider selection bits (DV <02:00>), and the
rate selection bits (RS <03:00>).
The
UIP is a read-only bit that is set when there is an update in
progress
within
the chip. This bit must be read prior to reading
the time., If the UIP is a 1, an update is in progress and the time
registers are undefined. If the UIP is a 0, there are at least 244
us
available
prior
to
the next update cycle. If interrupts are
disabled,
the time required to read the 5 time registers does not
exceed

pus.

CSR A is undefined after battery power has been lost. Whenever the
operating
system
software
loads the TOY data registers, it must
also
1load 20 (hex) into CSR A. Setting DV <02:00> = 2 sets up the
timer
for
operation
with
the 32.768 kHz oscillator. Setting RS
<03:00>
= 0 disables the unused interrupt and square wave outputs
from the chip.
CSR
A is not affected
BBU
mode,
as
1long
specification.

by the chip going
as
the
battery

into or out of the
voltage
remains

normal
within

4.11.2.3 Control
and
Status
Register
B
~-- CSR B (Figure 4-22)
contains
four bits that enable functions not used in the KA630-AA

design,
SET,
operation.

and

three

bits

that

control

timer

format

and

SET
is
a
read-write
bit
used
to
enable
and
disable
clock
operation.
When written with a 0, the internal time updates occur
every
second.
When written with a 1, the updates are disabled so

that the program may load the TOY data registers.

set
prior to setting the time.
update, setting this bit aborts

uip | Ov2 | OV1

()

If the chip
the update.

[ Dvo | RS3 | RS2 | RS1 | RSO

o
i

Figure

4-21

Control

This bit must be

in the middle of

15847

and Status Register A

SET

PIE

AIE | UIE

|SQWE]

|24/12|

DSE

@lo|jofjo|m|n|

(CSR A)

o
R 15948

Figure

4-22

Control

and

Status Register

(CSR B)

Architecture

(PIE),
Enable
1Interrupt
periodic
ended Interrupt Enable (UIE)
Update
are not used.

Alarm Interrupt Enable
and SQuare-Wave Enable

(AIE),
(SQWE)

pata
Mode (DM) is a read-write bit that controls whether the time
and
date
registers
use
binary
or
Binary
Coded Decimal (BCD)
formats. This bit is loaded with a 1 to select binary format,
24/12
1is a read-write bit that controls whether the hour register
operates
in
24or l2-hour mode. This bit is loaded with a 1 to
select 24-hour mode.
Daylight
Saving
Enable (DSE) is a read-write bit that enables or
disables
special daylight saving time changes for the last Sunday
in April and the last Sunday in October. This bit is loaded with a
0 to disable this function.

CSR B is undefined after battery power has been lost. Whenever the
operating
system
software
loads the TOY data registers, it must
restart
the
timer
by loading 6 (hex) into CSR B, Loading 6 into
CSR B clears SET, and correctly loads the DM, 24/12 and DSE bits.
CSR

BBU

not affected by the chip going

mode,

specification.

long

4.11.2.4 Control

and

the

Status

into or out of the normal

battery

voltage

remains

C -- This register

within
is not

used.

4.11.2.5 Control and Status Register D -- CSR D (Figure 4-23) is a
read-only register that contains the VRT. The remaining seven bits
always
The

VRT

read

O0s.

read

software,

before

reading

the

time

registers,

verify the validity of the time. If the battery voltage goes below
specification
while
in
BBU
mode, this bit is reset to 0 by the
hardware
sensing
circuitry
during power-up, indicating that the
time
registers are undefined. If the VRT is 0, the time registers
must
be
updated
immediately. VRT is automatically set to 1 when
CSR
D
1is
read,
indicating
that the chip contains a valid time
setting.
If

battery

power-down,

voltages
KA630-AA

are

logic

removed

and

guarantees

that

VRY

then
VRT

restored
0.

READ
AS ZEROS
|

MR- 1554y

Figure

4-23

Control

and

Status

(CSR

during

Architecture

4.11.2.6 RAM
Memory -- The 50 bytes of RAM memory are used by the
KA630-AA
console program to store information required to restart
the
machine
following
a halt. Halts transfer program control to
location
20040000
(hex). One of these RAM locations -- CPMBX, is
used
for
communication
between
the
operating
system
and the
console

program.

The
CPMBX
(Figure 4-24, Table 4-11) contains the console message
text
language,
"Restart in Progress"TM and "Bootstrap in Progress"
flags,
and
the
processor halt action.
14, Its address is 200B801C.
15

038

The CPMBX

)

]

)

)
LNG

is TOY

(]

00
T

RIP | BIP

]

HLT

L ACT
MR-0286-0266

Figure

Console

Program Mailbox

(CPMBX)

Power-Up

4.11.3

Following

bit

4-24

power-up,

in CSR D.

the KA630-AA console program

this bit

is set,

reads

the VRT

the RAM and time data are valid.

If
this
bit
is
<c¢lear,
RAM
and time data are invalid,
console program disables the clock by setting CSR B SET.

and

the

When
the operating system gains control of the machine, it checks
SET. If that bit is set, the operating system must regquest
B
CSR
the

correct

time

4.11.3.1 valid

RAM

valid.

are

data

year

and

from

the

Time

operator.

-- If the VRT is set, RAM and time

The operating

system reads the

UIP

in CSR A

that an update is not in progress. If this bit is read
to assure
the watch chip is doing an update and the data is invalid
1,
as
The maximum time for the update is
the update is complete.
until
1.984

ms.

1is read as 0, the clock registers can be read by the
UIP
the
If
The operating system reformats the time into a
system.
operating
and loads it into the memory location that contains
32-bit count
the

time of

day count during system operation.

4.11.3.2 Invalid RAM and Time -- If the VRT is clear, RAM and time
The operating system stops timer operation by
invalid.
are
data
setting CSR B bit 7 (SET), and then requests the time of year from
the operator. After loading the correct time and date into the TOY
data registers, the operating system loads 10 (hex) into CSR A and
then

clears

The

operating

and

loads

day count

SET

system also

during

into

CSR

reformats the time

into a

32-bit count,

into the memory location that contains the time of
system

operation.

Architecture

Table

4-11

Console

Program Mailbox

Bit(s)

Mnemonic

Name/Meaning

<07:04>

LNG

Console

Message

controls

the

console

terminal.

program

the

Other

settings

Setting

National

1
2

German
English

3
4

Spanish
French
Italian
Danish

user

set,

must

when

set

the
the

the

console
field

follows.

Processor

Halt

Action.

control

the

software

This

mailbox

override
are cleared

progress.

This

system

progress.

the

operating

succeeds.

This

field

used

restart/bootstrap

allows

operating

system

the
BDR HLT ENB field.
on power-up and when the

exits.

HLT

Action

<01:00>

operating

automatic

Both
bits
console
program
follows.
ACT

attempt

bootstrap

procedure.

the

cleared

the

Variant

bootstrap

flag

system

ACT

are

If
set, a restart attempt
flag
must
be
<cleared by
when the restart succeeds,

BIP

HLT

set

field
to

Norwegian
Swedish
Portuguese

This

<01:00>

texts

Dutch
Finnish

This

message

When

prompts

9
10

RIP

Language.
of

power-up.

5
6
7
8

Text

output

Format

The

Use

HLT
determine

Restart,

Reboot,

Halt.

bits

ENB

may

(BDR

set

<14>)

action.
if

that

fails,

halt.
halt.

Architecture

INTERVAL TIMER
4.12
The
KA630-AA
interval timer is
chip.
When
it
1is enabled, the
request every 10 ms.

contained within the MicroVAX CPU
interval timer posts an interrupt

4.12.1
Interval Clock Control and Status Register (ICCS)
The
ICCS (Figure 4-25) is accessed as IPR 24. ICCS implementation
is
unique
to
the
MicroVAX
CPU
chip and consists of a minimal
interval

timer

control.

ICCS

bit 6 (IE) is a read-write bit that enables and disables the
interval timer interrupts. When this bit is set, an interval timer
interrupt
is
requested
every
10
ms. When ICCS bit 6 is clear,
interval
timer
interrupts are disabled. ICCS bit 6 is cleared by
power-up and by the negation of DC OK.

Interval Timer Operation
4.12.2
When
ICCS
bit
6
is
set, the interval timer posts an interrupt
request
every
10
ms. The interval timer is the highest priority
device
at
IPL
16
(hex).
The interrupt vector for the interval
timer

(hex).

3
1

765

§S

UNUSED, RETURNS
O

Y O

TT
T 1T

0000O0O0

L1
1 11

INTERRUPT ENABLE (IE)
MR-15950

Figure 4-25

Interval Clock Control

4.13

CONSOLE

SLU

4.13.1

Console

Functionality

and Status Register

(ICCS)

The
console
serial
1line
provides the KA630-AA processor with a
full-duplex serial interface for the console terminal. It provides
an RS-423-A EIA

interface

that

also RS-232-C

compatible.

The
serial data format of the console SLU contains 8-bit data, no
parity, and one stop bit. The interrupt vectors of the console SLU

are
Its

IPL

(hex)

for the receiver and FC

described

Section

4.4.1.

(hex)

for the transmitter.

Architecture

The receive and transmit baud rates are always identical and are
determined by the Baud Rate Select signals (BRS <02:00> L), which
received from an external 8-position switch through a
are
connector mounted at the top of the module.

BRSOl L

BRS00 L

Baud Rate

qaite o}

300
600

i~ I

1,200

2,400
4,800
9,600

sallt= -1 o= -

[l ol ol s~ -

~J= - ol

BRSO02 L

The baud rate is selected as follows.

19,200

38,400

Console Registers
4.13.2
are four registers (Table 4-12) associated with the console
There
SLU. They are accessed through IPRs 32 to 35 (decimal).

Table 4-12

SLU Console Registers

Number

Mnemonic

32
33
34

RXCS
RXDB
TXCS

Console Receiver Control/Status
Console Receiver Data Buffer
Console Transmit Control/Status

TXDB

Console Transmit Data Buffer

4.13.2.1 Console
Receiver
CSR
(IPR
32)
-- The contents of
console receiver CSR are shown in Figure 4-26 and Table 4-13.

the

4.13.2.2 Console
Receiver Data Buffer (IPR 33) -- The contents of
the
console
receiver
data
buffer
are shown in Figure 4-27 and
Table

4-14.
NOTE

present until
remain
conditions
Error
the next character is received, at which
point
error

the
bits

negation

the

error
bits are updated. The
are cleared by power-up and
of

OK.

Architecture

111

210

rTr1rrTrrrryrrr

TTrrryy

UNUSED. RETURNS
O

8765

i
000

bbbt

riT

00000

L1t

RCV ACT
RX DONE
RX IE
15981

Figure

Table

Bit (s)

Mnemonic

<31:12>
11

4-13

Console

RCV

ACT

DONE

Receiver

CSR

Format

Name/Meaning
Unused.

<10:08>
07

4-26

Read

Os.

Receiver Active.
the
center
of

This
the

read-only bit is
bit of the

start

set

serial

input
data,
center
(per
the
end
of

and
1is cleared at the expected
DLART timing) of the stop bit at
the serial data. RX DONE is set

one

bit

time

after

Unused.

Read

Receiver
an

Done.

entire

ready

RCV ACT

Os.

This

read-only

character

clears.

read

has

from

the

been
RBUF

bit

set

received

when

and

This

bit
1is
automatically
cleared
when RBUF is
read.
It is also cleared by power-up, by the
negation
06

Receiver

OK,

1Interrupt

and

writes

Enable.

This

the

BIR.

read/write

bit
is
cleared by power-up, by the negation
of
DC
OK,
and
by writes to the BIR., If RX
DONE
and
RX
1IE
are
both
set,
a program
interrupt is requested.
<05:00>

Unused.

Read

O0s.

Architecture

§1

UNUSED. RETURNS
O

rvrrTirld

rTrTrrTrryrrrirird

loo

1111

ERR

OVR ERR ————
FRM ERR

RCV BRK

RECEIVED DATA BITS
MR.15952

Console Receiver Data Buffer

Figure 4-27

Table 4-14

Bit(s)

Mnemonic

<31:16>
15

ERR

OVR

Console Receiver Data Buffer Format
Name/Meaning
as

Always

Error.

This read-only bit is set if RBUF bit

program

interrupt.

13
or
14
are
bits

ERR

read

Unused.

1is set. ERR is clear if these two
This bit cannot generate a
<clear.

Overrun Error. This read-only bit is set if a
was not read
character
received
previously
present
the
by
overwritten
being
before
character.,

FRM

ERR

Unused.

This read-only bit is set if
Error.
Framing
the present character has no valid stop bit.

RCV

BRK

This bit always

reads as 0.

Break. This read-only bit is set at
Received
the end of a received character for which the
space
the
in
remained
input
data
serial
for all 11 bit times. RCV BRK then
condition
input
data
serial
the
until
set
remains

condition. RCV BRK is
the mark
to
returns
cleared by power-up and by the negation
also

OK.

<10:08>

Unused.

<07:00>

Received
contain

These bits always

Data

the

last

Bits.

read as

These

read-only

received character.

bits

Architecture

Transmitter
4.13.2.3 Console
CSR (IPR 34)
console transmitter CSR are shown in Figure

The

contents

4-28

and

Table

765

3210

the

bit

|is

4-15.

3
1

TTTTrTTrTryryr
|

oeTrT T

UNUSED. RETURNS
O
S T
O
U
T
T
T
T

TrTT
O

000
11

TX RDY

TX IE

MAINT

XMIT BRK
MR.15953

Figure
Table

Bit(s)

4-15

Mnemonic

Console Transmitter CSR

Console

RDY

Transmitter

Read

Transmitter

Ready.

This

read-only

loaded and sets when XBUF
character. XMT RDY is set
negation of DC OK, and by

Transmitter Interrupt Enable. This read/write
bit
is
cleared by power-up, by the negation
of
DC
OK, and by writes to the BIR. If both
TX RDY and TX IE are set, a program interrupt

requested.

Unused.

<05:03>
02

Format

Os.

clear
when XBUF is
can receive another
by power-up, by the
writes to the BIR.
06

CSR

Name/Meaning
Unused.

<31:08>
07

4-28

Read

Maintenance.
facilitate

MAINT

Os.

read/write bit is used to
This
maintenance
self-test.
When

the external serial input
set,
1is
MAINT
disconnected and the serial output is used
is cleared
bit
This
input.
serial
the
negation of DC OK, and
the
by
power-up,
writes

Unused.

XMIT

BRK

Transmit

the

Read

is
as

by
by

BIR.

Break.

When this read/write bit is

set, the serial output is forced to the space
BRK is cleared by power-up,
XMIT
condition.
of DC OK, and by writes to
negation
the
by
the

BIR.

Architecture

(IPR 35) -- XBUF bits
4.13.2.4 Console Transmitter Data Buffer
¢31:08> are not used. XBUF bits <07:00> are write-only bits used
to load the transmitted character.
Break Response

4.13.3

The KA630-AA console SLU may be configured either to perform a
halt operation or to have no response when a break condition is
to transfer
the processor
A halt operation causes
received.
program control to ROM location 20040000
signal

break

halt

The

is asserted.

enabled if the connector HLT ENB

1is

option

(hex).

The DLART recognizes a break condition at the end of a received
for which the serial data input remained in the space
character
condition for all 11 bit times. The break recognition line remains
asserted until software reads the RBUF.
022-BUS CONTROL

4.14

4.14.1

The

BIR

Bus Initialize Register

(decimal).

to clear on writes

the BIR.

On an arbiter KA630-AA,

this
to
writing
10 ps (+ 20%) and
specified

(IPR 55)

is accessed as IPR 55
to

On an auxiliary KA630-AA,

writing to this register does not assert the Q22-Bus BINIT signal,
but it does clear all on-board register bits specified to clear on
or
(arbiter
configuration
either
For
BIR.
the
to
writes
auxiliary),

this

auxiliary

always

reads

NOTE

module receives

KA630-AA

BINIT
from
the
Q22-Bus
and uses that
signal
to
initialize
the MicrovVAX CPU
chip, and to clear all internal register
bits
that are specified to clear on the
negation

OK.

Stated

another way,

the
assertion
of
the
(22-Bus
BINIT
signal
has
the
same
effect
as
the
negation of DC OK on auxiliary modules.
4.14.2
When the

Multilevel Interrupts
KA630-AA is configured

interrupt
interrupt
SLU

and

BIRQ4

and

the

interprocessor

have

priority

After
responding
KA630-AA
sets the

1interrupt

processor

the

requests
BIRQ7
through
acknowledge protocol (DIN

doorbell
all

are

can

Q22-Bus

to
any
interrupt
processor priority

requests

priority.

over

arbiter

4
with
followed

disabled

CPU,

responds

the standard
by IAK). The
request

BIRQ4

interrupts

interrupt

Q22-Bus
console
at

requests.

request BIRQ7 through 4, the
to IPL 17. All BIRQ7 through

unless

software

lowers

the

Architecture

When

the

KA630-AA

respond

the

interprocessor
Interrupt
requests

BIRQ4

as
an auxiliary, it does not
from the Q22-Bus.
However, it does
interrupt requests from its console SLU and

from

the

have

responding

MicrovAX

configured

requests

doorbell.

requests

internally
After

1is

interrupt

CPU

the

KA630-AA

MicroVAX

CPU

higher

priority

interval

chip

an
sets

interval

chip.
than

BIRQ6

timer

the

processor

remain

enabled.

timer

Interval

are

handled

timer

interrupt

requests.

interrupt

priority

request,
IPL

the

16.

Thus,

4.14.3
Interprocessor Communications Facility
The
KA630-AA
interprocessor
communication facility allows

other

BIRQ7

interrupt

processors

KA630-AA
also

requests

the

system

without

wusing
external

controls

Q22-Bus

map,

and

request

the Q22-Bus
access
to

allows

other

program

interrupts

from

the

interrupt request lines.
local memory by means of

It
the

processors

halt

auxiliary

CPU.

4.14.3.1

4-29,
and

Interprocessor

Table
can

the

any

KA630-AA

the

device

1itself.

Q22-Bus

I/0

32-Bit

The

page

that

can

become

The

IPCR

1is

(Q22-Bus

address
of
the
IPCR
varies
arbiter and auxiliary KA630-AA,

Octal

20001F40

17777500

IPCR

20001F42
20001F44

17777502
17777504

IPCR
IPCR

CPU)
(Auxiliary 1)
(Auxiliary 2)

20001F46

17777506

IPCR

(Auxiliary

3
1

DMA QPEAl

|
0

the

low

four

22-Bit
Register

space

master,

with
the
as follows.

Address

(Figure

accessible,

either

Address

IPCR

address

byte

that a write-byte instruction can write
byte without affecting the other byte.

The
1/0
page
configurations of

Hex

Communication

resides

accessed

including

meaning
or high

4-16)

2
IR

0
|

(Arbiter

0
T

—

1
0

Ll
0

2
T

0
1

T
0

0
l

AUX HLT

DBIIE
LM EAE

DBI RQ

Figure

4-29

Interprocessor

Communication

(IPCR)

Architecture

Format

Interprocessor Communication Register

Table 4-16

Bit(s)

Mnemonic

Name/Meaning

DMA QPE

(022-Bus Address Space Parity Error. This
DMA
bit is set if MSER bit 4 (DMA QPE)
read-only
bit indicates that a
OQPE
DMA
The
set.,
is
parity error occurred when an external device
the KA630-AA local
accessing
was
CPU)
(or
memory.

Read as O0s.

Unused.

<14:09>

AUX HLT

Auxiliary Halt. On an auxiliary KA630-AA, AUX
is a read/write bit. When set, typically
HLT
arbiter CPU, it causes the on-board
the
by
transfer program control to the halt
to
CPU
On an arbiter KA630-AA, AUX
mode ROM code.

1is a read-only bit that always reads as
HLT
0. It has no effect on arbiter CPU operation.

DBI

Read

Unused.

This bit, when
Interrupt Enable.
Doorbell
doorbell
interprocessor
enables
set,
interrupt requests through IPCR bit 0. When

the on-board CPU is Q22-Bus master, DBI IE is

a read/write bit. When an external device (or
DBI IE is a read-only
is bus master,
cpU)

bit.

DBI

1is cleared by power-up, by the

negation of DC OK, and by writes to the BIR.

EAE

Local

Access

Enable. This

Memory

External

memory

(by means of the Q22-Bus map).

enables

external access to

bit,

when

set,

when

the

on-board CPU is Q022-Bus master, LM

local

EAE is a read/write bit. When an external
1is bus master, LM EAE is a
device (or CPU)
read-only bit. LM EAE is s cleared by
power-up and by the negation of DC OK.
Unused.

<04:01>

DBI

Doorbell
(DBI

Read

IE)

Os.

Interrupt

Request.

TIPCR bit 6

is set, writing a 1 to DBI RQ sets

DBI RQ, thus requesting a doorbell interrupt.
I1f IPCR bit 6 is clear, writing a 1 to DBI RQ
has no effect. Writing a 0 to DBI RQ has no

effect. DBI RQ is cleared when the CPU grants

the

doorbell

interrupt

request.

held clear whenever DBI IE is clear.

DBI RQ is

Architecture

4.14.3.2
is
bit

set,

doorbell

interrupt

The

Interprocessor
any

interprocessor

interrupt

Doorbell

0Q22-Bus

priority

writing

doorbell
is

Interrupts

master

can

into

IPCR

interrupt

described

request

bit

IPCR

DBI

interprocessor

vector

Section

the

204

(hex).

Its

4.4.1.

NOTE

Following

interrupt,
14.
The

the
IPL

Q22-Bus

BIRQ4

4.15

MULTIPROCESSOR

4.15.1
When

Auxiliary/Arbiter

differs
1.

KA630-AA

operation

The

arbiter

doorbell
KA630-AA sets the IPL =
1is set = 17 for external

interrupts.

CONSIDERATIONS

Differences
configured as

from

interprocessor

arbiter

KA630-AA

the

arbiter

mastership

using

auxiliary,

several

arbitrates

Q22-Bus
DMA
protocol. The
on an auxiliary KA630-AA.

Both

and
the

bus

its operation
important areas:

mastership

arbitration

logic

auxiliary
KA630-AA
(Q22-Bus
DMA request

per

the

disabled

request bus
protocol, as

follows.
a.

They

both

assert

BDMR

the

The
arbiter
KA630-AA
receives
DMGI
arbitration
logic.
The auxiliary receives
its Q22-Bus BDMGI pin.

€.

Only the auxiliary
the Q022-Bus.

KA630-AA

Q22-Bus.

actually

from
DMGI

asserts

its
from

BSACK

The
when

arbiter
XA630-AA
asserts
the (022-Bus BINIT signal
DC OK is negated and when its CPU software writes to

its

BIR.

The

auxiliary

KA630-AA

never

asserts

Q22-Bus

BINIT,
but
receives BINIT and uses it to initialize the
MicrovAX
CPU
chip
and
to clear all internal registers
that are specified to clear on the negation of DC OK.
The
the
An

physical address of the IPCR is different for each
four KA630-AA arbiter/auxiliary configurations.
auxiliary

KA630-AA

HLT) of its IPCR. On
disabled and AUX HLT
as

can

an
is

halted

setting

bit

(Aqx

arbiter KA630-AA, this feature is
a read-only bit that always reads

Architecture

CPU
ENB

The
HLT

affected

are controlled by the external connector
external halts that are
the
However,

halts
input.

differ

somewhat

KA630-AA modules.

for the arbiter and auxiliary

can field
auxiliary KA630-AA module
arbiter or
Each
timer, from its
interval
its
from
requests
interrupt
its interprocessor doorbell,
from
and
device,
console
interrupts from
field
can
KA630-AA
arbiter
the
only
Q22-Bus interrupt request lines BIRQ7 through 4.

The arbiter asserts BIAKO to the Q22-Bus when it responds
a
to
BIAKO
BIAKI

request, The auxiliary asserts
interrupt
(022-Bus when it receives the assertion of

022-Bus
the
to

from the Q22-Bus.

Although both arbiter and auxiliary KA630-AA modules
contain the same TOY clock and battery backup circuitry,
auxiliary will be configured
the
that
is assumed
it

batteries and that its clock will never actually

without

enabled.

4.15.2

Multiprocessor Features

its use

in multiprocessor systems.

have been added to the KA630-AA to allow

features

following

The

A 2-bit code, received at the external connector, allows
the KA630-AA module to be configured as the arbiter or as

one of three auxiliaries.

provides

IPCR

The

[

mechanism

for

interprocessor

interrupts, for enabling and disabling external access to
local memory, and for flagging local memory parity errors

caused

modules,

external
also

references.

provides

auxiliary KA630-AA

a mechanism for halting the

CPU.

4.15.3

KA630-AA Based

Multiprocessor

Systems

The
KA630-AA
multiprocessor
features were designed for use in a
message
passing
environment similar to the System Communications
Architecture
architecture.

(SCA)

that

currently

layered

the

port

Each
KA630-AA processor in a system fetches instructions and data
primarily
from
1its
own
1local
memory.
The
various processors
communicate
by
way of message queues stored in local memory that
has
been
mapped
to
the
Q22-Bus
address space. Typically, the
processors
use
the
interprocessor doorbell feature to interrupt
each

other

after

placing

message

empty

queue.

Architecture

In
most
systems,
all
Q22-Bus devices would be under the direct
processor, which fields all interrupts.
arbiter
the
of
control
a disk controller is under the direct control of the arbiter
when
up the transfer of program and data
set
must
arbiter
the
CPU,
and the auxiliary
disks
corresponding
the
between
information
The auxiliary processor is responsible for setting up
processors.
Q22-Bus map to point to the local memory space that is a
own
its
target

that

transfer.

Following a power-up or system restart, the auxiliary CPU runs its
self-test

diagnostics,

clears

the valid bits

in its Q22-Bus map

enters halt mode ROM space, and then sets its
registers,
mapping
(AUX HLT) and <06:05> (DBI IE and LM EAE). The
8
IPCR bits
own
CPU waits for the auxiliary's LM EAE bit to set and then
arbiter
the auxiliary CPU by loading the appropriate programs and
boots
into the arbiter's own local memory. These programs and data
data
space through the
to an assigned Q22-Bus address
are mapped

022-Bus map. The arbiter then clears the auxiliary's AUX HLT bit.
The auxiliary CPU, still in halt mode ROM space, waits for its AUX
HLT bit to clear and then begins auxiliary execution at a
specified location in the Q22-Bus address space (referencing local
memory

4.15.4

the

arbiter).

PDP-11 Based Multiprocessor Systems

three auxiliary KA630-AA modules can be added to a KDF11-B

or KDJ11-B based Q22-Bus system. Operation of a PDP-11 based
system is similar to that of a KA630-AA based system. However, the
following issues must be addressed.

Wwhen a PDP-11 processor is arbiter, its "local” memory is
memory.

actually

Q22-Bus

modules'

local memory.

This

appears

present no

special problems. A portion of the Q22-Bus memory address
space must be reserved for mapping the auxiliary KA630-AA

Since the PDP-11 processor does not contain an IPCR, an
external device must be added that allows the auxiliary
KA630-AA modules to interrupt the processor. Since the

KA630-AA console program does not interrupt the arbiter
require
cpU, the auxiliary KA630-AA modules do notcompatib
le
modification if this external device is not
with

the KA630-AA IPCR.

CHAPTER

DIAGNOSTICS

INTRODUCTION

5.1

The
diagnostics
test
the
basic
functionality
of
an
arbiter
KA630-AA.
The
KA630-AA
diagnostics operate in the following two
modes.

Power-up mode
Console I/0 mode

°
°

In
power-up
mode,
program,
test
the

the diagnostics, in conjunction with the boot
KA630-AA's
ability to load and run a typical

In console

each of

operating
system or diagnostic supervisor. Seven diagnostic tests
are
performed.
They
cover CPU functionality, system pathing and
memory. The boot program tests the Q22-Bus interface.

I/0 mode,

the seven tests can be selected using

the Test command. Before each test is executed, its test number is
output
by
the console program to the LEDs on the KA630-AA and to
the
console
terminal.
This
provides
an external indication of
testing
progress,
so that a loss of control may be traced to the
failing
The

test.

diagnostics

KA630-AA.

They

The

are

areas

TOY

clock

Bus

reset

1located

not

test

tested

Console

saved

ISP

Console

saved

all

are

(IPR
(IPR

(IPR

the
as

console

the

program

functional

follows.

the

areas of

ROM

the

55)
41)

42)

Console saved ISL (IPR 43)
ASTLVL register
(IPR 19)
DMA

Category

5.2
The

circuitry

registers

FUNCTIONAL DESCRIPTION
KA630-AA
diagnostics
include

sequence

;tist

designed

covering

two

seven

localize

failures.

functional

areas),

tests

The

and

that

tests

are

run

are

run

from

described

Table

Diagnostics

Table

5-1

Diagnostic

Tests

Test

Coverage

IPCR

Memory

data

Memory

address

Q22-Bus mapping registers (no interrupts),
MSER and CEAR (no wrong parity)

CPU

Interrupts

(no

Error Type*

interrupts)

chip
and

traps

TOY
MSER

CEAR

Q22-Bus

Interval
Console

* C

timer

(Catastrophic)

(Hard)

5.2.1

This

state of KA630-AA

-- KA630-AA cannot operate,

(Fatal)

-- The

Memory

reads

unpredictable.

but console commands can

used.

IPCR Test

test

error.

the IPCR. No interrupts are generated. No traps

should occur. An IPCR test checks the interprocessor communication
register and

interprocessor doorbell

Memory Data

5.2.2

interrupt.

Test

This test checks all the memory for shorted and stuck conditions,
and builds a memory bitmap. This bitmap does not include the VMB
map or the console program scratch pages. The memory data test is
executed with PAR ENB set. Therefore, MSER and CEAR are checked
for

error exists when 64 Kbytes of contiguous memory are not

fatal

found within the

5.2.3

This
is

first 4 Mbytes of

Memory Address

Test

local memory.

test checks every cell of the memory to be sure each address

unique.

Diagnostics

5.2.4

This

022-Bus Mapping Registers Test

test

checks

Q22-Bus

mapping

registers

for

shorted

and

stuck

bits.

5.2.5

This

MicroVAX CPU Chip Test

test

MicrovaXx

<checks

data

the

test

CPU

chip.

The

following

checks

assumes

that

paths

Since

only

the

between

is a

the

console

basic path

MicroVAX CPU

for

program

ROM

and

the diagnostics,

chip can malfunction.

are performed:

Checks

general

shorted

and

registers

stuck

and

bits

<07:04>

PSL

for

bits.

Executes a limited set of instructions. This set includes
all
instructions in all modes that are necessary to load
software,
plus all instructions that are used in the ROM
diagnostic,
This
forces
a
functional
check
of
bits
<03:00>

PSL

well.

Checks
Process
Control
Block
Base
(PCBB);
executive,
supervisor, and user stack pointers;
for shorted and stuck bits.

Checks

for

TBIA for

kernel,
and TBIS

SBR,

POBR,

shorted

and

PCBB

stuck

bits

<01:00>

for

<29:02>

bits,

and

<31:30>

for

a proper

PlLR

bits

<31:22>

for

state,

Checks

SLR,

€21:00>

for

Checks

MAPEN

bit

Checks

P1BR

bits

and
9.

stuck

Checks
for

POLR,

shorted
0

and

and
for

stuck

and

bits.

<01:00>

for

0s,

and

31,

and

<08:00>

<31:02>

for

shorted

for

and

<29:09>

bits.

SCBB

shorted

bits
and

10.

Checks

the

MMU,

11.

Checks

the

FPU.

stuck

30,

bits.

0s,

Diagnostics

5.2.6

Software

This
group
MicroVAX CPU
The

Interrupts

consists
chip. It

following

algorithm

Ensure

Walk

that

and

Traps

of
data
path
tests
between
the ROM and
checks exceptions and software interrupts.
is

SISR

through

used:

SIRR

0.
bits

<03:00>

<16:01>.

Decrease
to

PSL

IPL

bits

Drop

IPL to
interrupts.

(hex)

Increase

Check

Drop
mode
protection

Drop

IPL

traps

mode

Drop

mode

protection

tests

Check

and

BDR

bits

and

start

responding

and

compare

the

software

and

P1LR.

(hex).
limits

SLR,

POLR

executive,

check

PSL

bits

<25:22>

and

check

PSL

bits

<25:22>

and

check

bits

<25:22>

and

check

supervisor,

trap.

wuser,

check

PSL

trap.

are

and

bits

<13:11>

<03:00>

for

Check

Map

Check

CEAR

for

Check

MSER

for

Write

data

into

trap

should

interval

pages

Data

Paths

interrupts as
check the TOY

well as several processor
register, interval timer,

performed:

two

<04:00>,

bits

violating

5.2.7
System Interrupts
These
tests verify system
board
data
paths.
They
CEAR and MSER.

following

bits

SISR

trap.

protection

using

check

<20:16>.

The

(hex)

and

proper

<07:04>

for

bit

for

code.

timer.

good

and

good

occur.

memory

set

PAR

pages

into

ENB

Q22-Bus

bit

memory.

map

registers.

0.
Read

locally.

Diagnostics

Set WRW bit 1. Write data into good pages.

data locally. Since wrong parity was used, the test

Read

traps through vector 4 of the SCB.

Check bits <09:03> of MSER for proper code.

10.

Check bits <14:00> of CEAR for proper error address.

11.

Clear bits <01:00> of MSER.

12.

Write data to memory through Q22-Bus.

13.

Read data from memory locally. No trap should occur.

14.

Read data from memory through Q22-Bus.

15.

Set

16.

Read data from memory locally. Since wrong parity was
used, the test traps through vector 4 of the SCB.

17.

Check bits <09:03> of MSER for proper code.

18.

Check bits <14:00> of CEAR for proper error address.

19.

Check bit

20.

Write data to memory through Q22-Bus.

21.

Read data from memory through Q22-Bus. Since wrong parity

22.

Check bits <09:03> of MSER for proper code.

23.

Check bits <14:00> of CEAR for proper error address.

24.

Check

25.

Write data into nonexistent I/0 register and trap.

MSER

through

<01:00>,

bits

Q22-Bus.

15 of

WRW

and

PAR

ENB. Write data

IPCR.

was used, the test traps through vector 4 of the SCB.

5.2.7.1

bit

Console

thg

console

This

test

Test —- The diagnostic sets maintenance bit 2 of

transmitter

checks

Receiver
Receiver

IPCR.

the

CSR,

and outputs four null characters.

following.

and transmitter
Done and Active

interrupts
bits

Receiver buffer Error and Overrun Error

flags

Diagnostics

5.2.8

Console Program/ROM Diagnostic Interface
In
either
power-up
or
console
1/0
mode,
the console program
invokes
one
test at a time. Each test number is displayed on the
LEDs
and
the console terminal. No carriage returns are output as
part
of
the code display, so if all tests complete normally, the
string
8...7...6...5...4...3...
1is seen on the console terminal.
If the diagnostic detects a catastrophic or fatal error, it passes

the
status
and
error number to the console program immediately,
and
no
further
testing
is
done.
If
hard (memory) errors are
detected, the diagnostic passes the status and number of bad pages

the

console

the

console

end

program

program.

only

the

test,

This

way

the

end

the

test.

diagnostic

Repeat

Test

easily
implemented. Before each
"Test in Progress" safeguard flag.

(an

test,

passes

optional

the

status

the

specifier)

can

diagnostic

sets

the

NOTE
Test

commands

test

of
contents
RPB
may
system

may

include

read/write

memory

in
be

that
leaves
memory
an unpredictable state. The
1lost.
In
this
case, the

must

rebooted

restore

the

RPB.

5.3
If
the

ERROR OUTPUT
a

diagnostic detects a
status and error number

catastrophic or fatal error, it passes
to the console program, and no further

testing
is
done.
Neither text nor error
the diagnostic program. All text and error
the console in the appropriate language.
5.4

KA630-AA

There

are

not

are
are

printed
printed

by
by

LED DISPLAY

four

red

LEDs

the

interpreted
as
a 4-bit hexadecimal
5-2.
All
LED
codes
are displayed
indicated only if the CPU stops at a
An

messages
messages

LED

is illuminated if its
illuminated if its control

KA630-AA.
These
four LEDs,
digit, are described in Table
during power-up. A problem is

particular

control

bit

bit
0.

LED code.

the

BDR

and

It
1is possible for privileged
processor
is in program mode.
the
interpretation
of
the
discouraged.

code to output to the LEDs when the
Because this may cause confusion in
LEDs,
this
use
of
the
LEDs
is

When
also

sequence,

executing

output

the

power-up

console

terminal.

the

codes

through

are

Diagnostics

Table

5-2

KA630-AA LED Interpretation

Code

Activity

Exit Criteria

Electrical power-up.

MicroVAX

Wait

BDR bit 15 set.

from

for PWR OK.

starts execution

console

program

ROM.

Perform ROM checksum and TOY

Test success,

Initialize console program
memory.

Console memory and bitmap
initialized, registers

Run IPCR tests.*

Test success.

RAM

tests,*

saved.

VCB01l operational or not

Test for and check VCBO1l

video

console display,

present.

present.*

Perform console port tests and
terminal identification.*

Console terminal type
determined.

Query console

Exits power-up

language,*

automatically, otherwise

then enter console command

exits on console Continue,

mode.

Boot

Start,

Test

commands.

Run memory pattern tests.+

least 64 Kbytes of

contiguous
found.

good

memory

Run memory address tests.*

All address tests passed.

Run

I/O0

map

Test

success.

Run

CPU

tests.*

Test

success.

Run

interrupt

Test

success.

for

tests.*

bootstrap

device.#

Valid

bootstrap

device

located.

Load

bootstrap.#

Bootstrap

successfully

loaded.

0
*

Program mode.
Performed

only

Not

power-up

+ Performed

on power-up entry

only

Performed

during

entry

into

applicable.

console

program.

and on operator-requested

bootstrap.

APPENDIX

022-BUS

SPECIFICATION

GENERAL DESCRIPTION

A.l

The Q22-Bus, also known as the extended LSI-11 Bus, is the low-end
member of Digital's bus family. All of Digital's microcomputers,
such as the MicrovAX I, Microvax II, and MicroPDP-11, use the
Q22-Bus.

bidirectional and 2 unidirectional

consists

Q22-Bus

The

signal 1lines. These form the lines along which the processor,
memory, and I/0 devices communicate with each other.

Addresses, data, and control information are sent along these
signal 1lines, some of which contain time-multiplexed information.
The lines are divided as follows.

Sixteen multiplexed data/address lines —- BDAL<15:00>

)

Two multiplexed address/parity lines -- BDAL<17:16>

[

Four extended address lines —-- BDAL<21:18>
BRPLY,

system

Six

)

BSYNC,

BDCOK,

Ten

[

lines

BDMR,

for

these

The

module

Most

control

interrupt

-- BIAKO,

BSACK,

1lines

control
BIAKI,

-- BHALT, BREF, BEVNT, BINIT,

and

direct memory access control

BIRQ4, BIRQ5,

BIRQ6, BIRQ7, BDMGO,

BDMGI

number

the bus.

Refer

power,

ground,

Appendix

applies

to Table A-1

for a

and

space

lines

are

detailed description

lines.

discussion

physical

-- BBS7, BDIN, BDOUT,

BWTBT

BPOK

addition,

defined

1lines

«control

transfer

data

Six

[

address

must

use

this

capability.
22-bit

All

modules

used

the general

with

the

22-bit

KA630-A

CPU

addressing.

Q22-Bus signals are bidirectional and use terminations for a

(high)
negated
high-impedance
asserted

state

1level. Devices connect to these lines via
signal
drivers. The
and open collector
receivers
bus

produced

when

bus

driver

asserts

the

line

low.

Q22-Bus Specification

1lines are electrically bidirectional (any
Although bidirectional
point along the line can be driven or received), certain lines are
functionally unidirectional. These lines communicate to or from a
bus master (or signal source), but not both. Interrupt acknowledge

(BDMG) signals are
direct memory access grant
and
(BIAK)
physically unidirectional in a daisy-chain fashion. These signals
originate at the processor output signal pins. Each is received on
(BIAKI or BDMGI) and is conditionally
pins
input
device
(BIAKO or BDMGO). These
output pins
device
via
ted
retransmit
received from higher-priority devices and are
are
signals

retransmitted

lower-priority

along

devices

establishing the position-dependent priority scheme.
A.l.1

the

bus,

Master/Slave Relationship

Communication between devices on the bus is asynchronous. A
master/slave relationship exists throughout each bus transaction.
Oonly one device has control of the bus at any one time. This
controlling device 1is termed the bus master, or arbiter. The
master device controls the bus when communicating with another
device on the bus,

termed the slave.

The bus master (typically the processor or a DMA device) initiates
a bus transaction. The slave device responds by acknowledging the
by receiving data from, or
and
progress
in
transaction
transmitting data to, the bus master. Q22-Bus control signals
transmitted or received by the bus master or bus slave device must
complete the sequence according to bus protocol.

The processor controls bus arbitration, that is, which device
this
becomes bus master at any given time. A typical example of
relationship is a disk drive, as master, transferring data to
ked so
memory as slave. Communication on the Q22-Bus is interloc
device,
master
the
by
issued
signals
control
certain
for
that,
the
there must be a response from the slave in order to complete
makes the
transfer. It is the master/slave signal protocol that
022-Bus asynchronous. The asynchronous operation precludes the
need for synchronizing with, and waiting for, clock pulses.

Since

bus

cycle

completion

by the bus master requires response

timeout
from the slave device, each bus master must include a does
not
error circuit that aborts the bus cycle if the slave
The actual time
respond to the bus transaction within 10 ps.
before a timeout error occurs must be longer than the reply time
of the slowest peripheral or memory device on the bus.

A.2

Table

022-BUS SIGNAL ASSIGNMENTS

A-1

1lists

the

signal

assignments

for the data/address,

control, power/ground, and spare functions of the Q22-Bus.

Q22-Bus Specification

Table

A-1

Name

Signal

Assignments

Pin Assignment

DATA AND ADDRESS
BDALO
BDAL1
BDAL2
BDAL3
BDAL4

AU2
AvV2
BE2

BF2
BH2
BJ2
BK2
BL2
BM2
BN2

BDALS
BDAL6
BDAL7
BDALS
BDALY
BDALI10
BDAL11
BDAL12
BDAL13
BDAL14
BDAL15

BpP2
BR2
BS2
BT2
BU2
BV2
ACl
AD1
BCl
BD1
BE1l
BF1

BDAL16
BDAL17
BDAL18
BDAL19
BDAL20
BDAL21
CONTROL
Data

Control

BDOUT

AE2

BRPLY

AF2

BDIN

AH2

BSYNC

AJ2

BWTBT

AK?2

BBS7

AP2

Interrupt

Control

BIRQ7

BP1

BIRQ6

AB1l

BIRQS
BIRQ4

AL2

BIAKO

AN2

BIAKI

AM2

DMA

AAl

Control

BDMR
BSACK
BDMGO
BMDGI

AN1
BN1
AS2
AR2

Q22-Bus Specification

Table A-1

Signal Assignments

Name

Pin Assignment

System Control

APl
AR1
BR1
AT2
BAl
BBl

BHALT
BREF
BEVNT
BINIT
BDCOK
BPOK
POWER AND GROUND

+5B
+12B

(Cont)

(battery)

AS1

(battery)

+12B
+5B

BS1
AV1

AA2

BA2

+5
+12
+12
+12

BV1
AD2
BD2
AB2

=12

AB2

-12

BB2

GND
GND
GND
GND

AC2
AJl
AM1
ATl

GND

BC2

GND
GND

BJ1
BM1

GND

BTl

SPARES

SsSparel

AE]

SSpare3
SSpare8
SSpare2
MSpareA
MSpareB
MSpareB
MSpareB

AH1
BH1
AF1l
AK1l
ALl
BK1
BL1

PSparel
ASpare2

AUl
BU1

Q22-Bus

A.3
DATA TRANSFER BUS CYCLES
Data transfer bus cycles are listed and defined

Specification

in Table A-2.

These
bus cycles, executed by bus master devices, transfer 32-bit
words
or
8-bit
bytes
to
or from slave devices. In block mode,
multiple
words
may
be transferred to sequential word addresses,
starting
from
a
single
bus
address. The bus signals listed in
Table
A-3
are
wused in the data transfer operations described in
Table A-2.

Table A-2

Bus Cycle

Mnemonic

Description

DATI
DATO

Data
Data

Transfer

Operations

Function

Respect

Read
Write
Write-byte
Read-modify-write
Read-modify-write
Read block

Data

Write

Table
Mnemonic

word
word

(with

the Bus Master)

input
output
Data byte output
Data word input/output
Data word input/byte output
Data block input

DATOB
DATIO
DATIOB
DATBI
DATBO

BDAL<21:00>

Data

block

A-3

output

Bus

Signals

Description
L

for

Data

byte

block

Transfers

Function

Data/address

lines

BDALK15:00>

are

used

for

word
and
byte transfers.
BDALK17:16> L are used for

extended
addressing,
memory
parity error (16),
and
memory
parity
error
enable
(17),
functions.
BDAL<21:18> L are used for
extended addressing beyond
256 Kbytes.
BSYNC

Bus

cycle

control

Indicates

in
BDIN

BDOUT

BRPLY

Data

input

Data

output

Slave's

bus
BWTBT

BBS?

indicator
indicator

acknowledge

Strobe

signals.

Strobe

signals.

Strobe

signals.

cycle

Write/byte

control

I1/0 device select

bus

Control

signals.

Indicates
the

transaction

progress.

I/0

address

page.

1is

Q22-Bus

Specification

Data transfer bus cycles can be reduced to five basic types: DATI,
DATO(B),
DATIO(B),
DATBI,
and
DATBO.
These transactions occur
between
the
bus
master and one slave device selected during the
addressing portion of the bus cycle.

A.3.1
Bus Cycle Protocol
Before
initiating
a bus cycle, the previous bus transaction must
have
been
completed (BSYNC L negated) and the device must become
bus
master.
The
bus
cycle
can
be
divided into two parts: an
addressing
portion,
and
a
data
transfer
portion.
During the
addressing
portion,
the
bus
master outputs the address for the
desired
slave
device,
memory
location, or device register. The
selected
slave
device
responds by latching the address bits and
holding
this
condition
for
the duration of the bus cycle until
BSYNC
L
becomes
negated.
During the data transfer portion, the
actual

data

A.3.2

transfer

occurs.

Device Addressing

The
device
addressing
comprises
an
address

portion
of
a
data
transfer
bus cycle
setup and deskew time, and an address hold
the address setup and deskew time, the bus

and deskew time.

During

master

following.

does

the

BDAL<21:00>

)

Asserts

BBS7

Asserts

BWTBT

address

with

device

the

desired

slave

device

bits

1in

the 1/0 page is being

addressed

the cycle is a DATO(B)

or DATBO bus

cycle

address, BBS7 L, and BWTBT L signals are
the
time,
this
During
asserted at the slave bus receiver for at least 75 ns before BSYNC

I/0 page ignore the 9 high-order
the
in
Devices
active.
goes
and instead, decode BBS7 L along with
BDAL<21:13>,
bits
address
bits. An active BWTBT L signal during
address
low-order
13
the
that a DATO(B) or DATBO operation
indicates
time
setup
address
BWTBT L indicates a DATI, DATBI, or
inactive
an
while
follows,
DATIO(B)

operation.

The address hold and deskew time begins after BSYNC L is asserted.
The

slave

device

uses the active BSYNC L bus

received output to

BBS7 L, and BWTBT L into its internal
bits,
BDAL address
clock
BDAL<21:00> L, BBS7 L, and BWTBT L remain active for 25 ns
logic.
(minimum)

active

for

after BSYNC L bus receiver goes active. BSYNC L remains
the

duration

the

bus

cycle.

and peripheral devices are addressed similarly, except for
Memory
way the slave device responds to BBS7 L. Addressed peripheral
the
not decode address bits on BDAL<21:13> L. Addressed
must
devices
bus cycle when BBS7 L is
a
to
respond
may
devices
peripheral
the addressing portion of the cycle. When
during
(low)
asserted
BBS7 L indicates that the device address resides in the
asserted,

Q022-Bus

1/0

page

not

(the

Specification

upper

respond

4 K address space). Memory devices generally
addresses in the I/0 page; however, some system

applications
may
permit memory to reside in the 1/0 page for
as DMA buffers, read-only memory bootstraps, diagnostics, etc.
DATI

BDIN

The

DATI

bus

cycle,

shown

Figure A-1,

use

read

operation.
During
DATI,
data
1is
input to the bus master. Data
consists
of
16-bit
word transfers over the bus. During the data
transfer
portion
of
the
DATI bus cycle, the bus master asserts
device
TM

100

responds
Asserts

(minimum)

BDIN

BRPLY

L
L

timeout)
after
before BDAL bus
°

after

active
0

BSYNC

(minimum)

receiving
driver data

follows.
(8

BDIN
bits

L,
are

asserted.

The

slave

maximum

avoid

and 125
valid.

(maximum)

bus

Asserts

BDAL<21L00>
L
with the addressed data and error
information
0
ns (minimum) after receiving BDIN, and 125
ns (maximum) after assertion of BRPLY.

BUS MASTER

SLAVE
{MEMORY OR DEVICE}

{PROCESSOR OR DEVICE}

ADDRESS DEVICE MEMORY
* ASSERT BDAL <21:00> L WITH
ADDRESS AND
o ASSERT BBS7 IF THE ADDRESS
1S IN THE 1/0 PAGE

ASSERT BSYNC L
\

—

DECODE ADDRESS
¢

STORE“DEVICE SELECTED"

OPERATION
’

,_,——""”
/

REQUEST DATA
*

REMOVE THE ADDRE
FROM
SS

BDAL <21:00> L AND
NEGATE BBS7 L
* ASSERT BOIN L

‘\

—_—

INPUT DATA
*

,,, -»

’~’—__,,.,

- -

TEAMINATE INPUT TRANSFER
*

PLACE DATA ON BDAL < 15:00>
ASSERT BRPLY

ACCEPT DATA AND RESPO

BY NEGATING BDIN L

ND
__‘\‘_\5

‘\\\

—

TERMINATE BUS CYCLE
¢

NEGATE BSYNC L

OPERATION COMPLETED

-—

Figure A-1

DATI

Bus

NEGATE BRPLY

Cycle

——

Q22-Bus

When

Specification

the
)

bus

master

Waits

]

data

used

for

Negates

BRPLY

The

receives

BRPLY

does

the

1least 200 ns deskew time and
BDAL<17:00>
L bus receivers.

transmitting

parity

BDIN

goes

200

errors

(minimum)

to
to

then

accepts

input

BDAL

<17:16>

the
2

active,

following.

(maximum)

slave

device responds to BDIN L negation by negating
removing
read
data
from
BDAL bus drivers. BRPLY L
negated
100
ns
(maximum)
prior to removal of read data.
and

master

responds

Conditions
°

for

BSYNC

)

Figure

the

negated

the

BSYNC

must

remain

BSYNC

must

not

BRPLY

negation.

A-2

shows

DATI

BRPLY

assertion

negated

for

are

200

become

asserted

cycle

timing.

bus

negating

are

master.

BSYNC

after

BRPLY

must

The

bus

follows.

(minimum).

within

300

NOTE

Continuous
control

assertion

the

bus

BSYNC

the

retains

bus

master,

and
the
previously
addressed
slave
device
remains
selected.
This is done
for
DATIO(B)
bus
cycles where DATO or

DATOB

follows
a
DATI
without BSYNC L
negation
and a second device addressing
operation. Also, a slow slave device can

hold

off

keeping

the

master

DATO(B)

~--

Data

1is

transferred

from

the

can

occur

has

been

input
The

DATO(B),

bus

data
and

During

master

after

the

asserted

transfer

setup

part

transfer
deskew

the

data

transfers

BRPLY

keep BSYNC

shown

32-bit

the

asserted,

Figure

words

slave

itself

which

causes

asserted.
A-3,

(DATO)

device.

is
or

The

write

8~bit

data

transfer

addressing

portion

the

master,

immediately

bus

DATIO(B)

portion

time

and

of
a

bus

operation.

bytes

cycle

when

(DATOB)

output
BWTBT

following

cycle.

DATO(B)

data

hold

bus

and

cycle

deskew

comprises

data

time.

data setup and deskew time, the bus master outputs
the
BDAL<15:00>
L
at least 100 ns after BSYNC L assertion.
BWTBT
L
remains
negated for the length of the bus cycle.
If the
transfer
is
a
byte transfer, BWTBT L remains asserted.
If it is
the
output
of
a
DATIOB, BWTBT L becomes asserted and lasts the
duration of the bus cycle.
data

Q22-Bus Specification

T/R DAL

T ADDR

TDIN

141

R DATA

x
200 NS _‘l

MINIMUM[® TM MAXIMUM

L,w NS >

200 NS MINIMUM
#——————————————

M'N'MUMy

TSYNC

{4)

100 NS

CLOCK DATA

le————200 NS MINIMUM

100 NS MINIMUM —
8 uS MAXIMUM

le—

200 NS
MiniMUM —o

300 NS MINIMUM————a
R RPLY

150 NS

"‘ MINIMUM ol +

’-—\oo NS MINIMUM

T8S7

(4)

TWIBT

4
TIMING AT MASTER DEVICE

14)

R ADDR

R/T DAL

RSYNC

I M INIMUM

(4)

25 NS

ons |

T DATA

{4)

Fons MINIMUM

+—125 NS MAXIMUM

100 NS MAXIMUM

MINIMUM

le— 75 NS

te——200 NS MINIMUM

MINIMUM

150 NS

MIMIMUM

R DIN

300 NS MINIMUM ———f

TRPLY

fe— 75 NS MINIMUM

—-1

RBS7T

RWTBT

(4)

(4)
-

25 NS MINIMUM

[

(E2]
TIMING AT SLAVE DEVICE

NOTES

1. TIMING SHOWN AT MASTER AND SLAVE DEVICE

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT

BUS DRIVER INPUTS AND BUS RECEIVER QUTPUTS
2 SIGNAL NAME PREFIXES ARE DEFINED BELOW

SIGNAL NAMES INCLUDE A “B” PREFIX.
4. DON'T CARE CONDITION

T = BUS DRIVER INPUT
R = BUS RECE!VER QUTPUT
“A 6037

Figure

A-2

DATI

Bus

Cycle

Timing

Q022-Bus

Specification

BUS MASTER

SLAVE

(PROCESSOR OR DEVICE)

(MEMORY OR DEVICE)

ADDRESS DEVICE/MEMORY
ASSERT BDAL <21:00> L WITH
ADDRESS AND

ASSERT BBS7 L

IF ADDRESS IS

IN THE 1/0 PAGE
ASSERT BWTBT L (WRITE

CYCLE)
o

ASSERT BSYNC

—
—
—
—

DECODE ADDRESS

_—

OUTPUT DATA
¢

—

__—* STORE

"DEVICE SELECTED

OPERATION

REMO
THE ADDRESS
VE
FROM

BDAL <21:00> L AND NEGATE BBS7 L
*

NEGATE BWTBT L UNLESS DATOB

PLACE DATA ON BDAL < 15:00>

ASSERT

8DOUT L
—_—
—

TAKE DATA

RECEIVE
DATA FROM BDAL
LINES

o —— *

ASSERT BRPLY L

,,,

"/__,,,_
TERMINATE
OUTPUT TRANSFER

NEGATE BDOUT L (AND BWTBT

IF A DATOB BUS CYCLE)

REMOVE DATA FROM BDAL <15:00> L

—_—

OPERATION COMPLETED
——”-"”__,,-

TERMINATE BUS CYCLE
«

NEGATE BSYNC

NEGATE BRPLY

L
MR- 6029

Figure

A-3

DATO

DATOB

Bus

Cycle

Q22~Bus

Specification

During
a
byte transfer, BDAL<00> L selects the high or low byte.
This
occurs
while
in
the
addressing
portion of the cycle. If
asserted,
the
high
byte (BDAL<15:08> L) is selected; otherwise,
the low byte (BDAL<K07:00> L) is selected. An asserted BDAL 16 L at
this
time
forces a parity error to be written into memory if the
memory
1is
a
parity~type memory. BDAL 17 L is not used for write

operations.
The
bus master asserts BDOUT L at least 100 ns after
BDAL
and
BDWTBT
L
bus
drivers
are
stable.
The slave device
responds
by
asserting BRPLY L within 10 us to avoid bus timeout,.
This completes the data setup and deskew time.
During
BRPLY
least

the

data

L
and
150
ns

hold

negates
from the

and

deskew time,

the bus master

receives

BDOUT L, which must remain asserted for
receipt of BRPLY L before being negated

at
by

the
bus
master. BDAL<17:00> L bus drivers remain asserted for at
least
100
ns after BDOUT L negation. The bus master then negates
BDAL

inputs.

During
this
time,
the slave device senses BDOUT L negation. The
data
is
accepted
and
the slave device negates BRPLY L. The bus
master
responds
by negating BSYNC L, However, the processor does
not
negate
BSYNC
L
for at least 175 ns after negating BDOUT L.
This completes the DATO(B) bus cycle. Before the next cycle, BSYNC
L
must
remain
wunasserted
for at least 200 ns. Figure A~4 shows
DATO(B) bus cycle timing.
DAITO(B)
-- The protocol for a DATIO(B) bus cycle is identical to
the
addressing and data transfer portions of the DATI and DATO(B)

bus
cycles,
and
is
device,
a
DATI cycle

BSYNC

L
byte

between

cycle

in
Figure A-5. After addressing the
performed as explained earlier; however,

is not negated. BSYNC L
transfer [DATO(B)]. The

assertion.
BSYNC L, as

bus

shown

remains

bus

active for an output word
master maintains at least 200

BRPLY
L
negation
during the DATI cycle and BDOUT L
The
cycle
1is
terminated when the bus master negates
described for DATO(B). Figure A-6 illustrates DATIO (B)

timing.

Q22-Bus

Specification

r.—O NS MINIMUM

T DAL

(41 T ADDR

150 NS
HINIMUM“

TSYNC

T DATA

‘-100 NS MINIMUM

—01

(4)

L_u)o
NS
LN

84S

I‘E/-\xlmur»_/l.l

MINIMUM
175 NS

F*—200
NS MINIMUM—as

T DOUT

150 NS MINIMUM—.i

L—

300 NS MINIMUM

R RPLY

TBS7

|._ 100 NS MINIMUM

(4)

—.J
TwTBT

(4}

le—150 NS MINIMUM

(4)

150 NS

MINIMUM

ASSERTION = BYTE

100 NS

(4)

100 NS

MINIMUM

TIMING AT MASTER DEVICE

R DAL

(4)

X R ADW

—

R SYNC

R DATA

25 NS MINIMUM

—-1

/
TENS

L—zs NS MINIMUM
AN

100 NS MINIMUM—’LL‘;O NS MINIMUM

MINIMUM

R DOUT

150 NS

MINIMUM [*—

~#{25 NS
TRPLY

RWTBT

300 NS MINIMUM ——

MINIMUM

R BS7

(4)

(4}

75 NS

MiNiMum

25 NS MINIMUM

(4)

TSNS oo g

MINIMUM

4)(

\ {

(4)

—

r—zs NS MINtMUM

ASSERTION = BYTE

L—zs NS MINIMUM

(4)

TIMING AT SLAVE DEVICE
NOTES
1

TIMING SHOWN AT MASTER AND SLAVE DEVICE

BUS DRIVER INPUTS AND BUS RECEIVER QUTPUTS
2 SIGNAL NAME PREFIXES ARE DEFINED BELOW

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B~ PREFIX
4.

T =BUS DRIVER INPUT

DON'T CARE CONDITION

R = BUS RECEIVER QUTPUT
[FURTE?Y

Figure

A-12

A-4

DATO

DATOB

Bus

Cycle

Timing

Q22-Bus Specification

SLAVE

BUS MASTER

(MEMORY OR DEVICE)

(PROCESSOR OR DEVICE)
ADDRESS DEVICE/MEMORY

ASSERT BDAL <21:00> L WITH

ASSERT BBS7 L IF THE
ADDRESS IS IN THE 1/0 PAGE

ASSERT BSYNC L

ADDRESS

~* DECODE ADDRESS
e

REQUEST DATA

REMOVE THE ADDRESS FROM

L
ASSERTBDIN

BDAL <21:00> L

——

T INPUT DATA
e

PLACE DATA ON BDAL <16:00> L

ASSERTBRPLY L

TERMINATE INPUT TRANSFER
e

STORE “DEVICE SELECTED"

OPERATION

ACCEPT DATA AND RESPOND BY
TERMINATING BDIN L

~——

———

COMPLETE INPUT TRANSFER
e

REMOVE DATA

NEGATE BRPLY L

-~ - - -

OUTPUT DATA
PLACE OUTPUT DATA ON BDAL <15:00> L
e

(ASSERT BWTBT L IF AN OUTPUT
BYTE TRANSFER)

ASSERT BDOUT L

\\\*

TAKE DATA

-~ -

RECEIVE DATA FROM BDAL LINES

ASSERT BRPLY L

- //

TERMINATE OUTPUT TRANSFER

REMOVE DATA FROM BDAL LINES

NEGATE BDOUT L

—— — — -

—

TERMINATE BUS CYCLE
®

-— -

—

OPERATION COMPLETED
NEGATE BRPLY L
®

NEGATE BSYNC L

(AND BWTBT L IF IN
A DATIOB BUS CYCLE)
MRA-6030

Figure A-5

DATIO or

DATIOB

Bus

Cycle

Q22-Bus

Specification

Io—lSONSMINIMUM

RT DAL

(4) xTADDR)<
100 NS

MINMUM
TMTM

—‘1

(a)

RDATA X

(a)

TDATA

200 NS MAXIMUM

L_ 100] NS MINIMUM

—

T SYNC

IO-ONSMINIMUM

J
100 NS MINIMUM
[~

T pouT

-flli"m’:sa—

200Ns

200 NS

MINIMUM

200 NS

—o

[* minimom
T DIN

’

R RPLY

150 NS

MINIMUM TM1
300 NS

le—

MINIMUM

T8S7

x
—+

}e— 100 NS MINIMUM

T WTBT M%L

100 NS MINIMUM—

ASSERTION = BYTE

(4)

t#— 150 NS MINIMUM

TIMING AT MASTER DEVICE

RT/DAL

(&)

XR ADDRx

RSYNC

25 NS
MINIMUM

ToATA

(4)

R DATA

’

— L- 25 NS MINIMUM

- L_ 100 N§

MAXIMUM

l#— 75 NS MINIMUM
—»{

R OOUT

25 NS MINIMUM

125NS

MAXIMUM

100 NS

miNiMUM
150NS

MINIMUM

-]
le-150 NS MINIMUM

R DIN

\
150 NS

300NS

MINIMUM

T RPLY

—.l

R 8S7

— 75 NS MINIMUM

—-‘

fe— 75 NS MINIMUM

RWTBT |4>\

‘1

(@)
~—

le— 25 NS MINIMUM

r—zs NS MINIMUM

ASSERTION = BYTE

(4)

25 NS MINIMUM

TIMING AT SLAVE DEVICE
NOTES

TIMING SHOWN AT REQUESTING DEVICE

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A “B” PREFIX.

BUS DRIVER INPUTS AND BUS RECEIVER QUTPUTS
4

2 SIGNAL NAME PREFIXES ARE DEFINED BELOW

DON'T CARE CONDITION

T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT
MR 6036

Figure

A-6

DATIO

DATIOB

Bus

Cycle

Timing

Q22-Bus

Specification

DIRECT MEMORY ACCESS

A.4

data
The direct memory access (DMA) capability allows direct using
when
useful
is
This
memory.
and
devices
I/0
between
transfer
mass storage devices (for example, disks) that move large blocks
the
of data to and from memory. A DMA device needs to know only
starting address in memory, the starting address in mass storage,
the length of the transfer, and whether the operation is read or
write. When this information is available, the DMA device can
transfer data directly to or from memory. Since most DMA devices
must perform data transfers in rapid succession or lose data, DMA
devices are provided the highest priority.

DMA is accomplished after the processor (normally bus master) has
passed bus mastership to the highest-priority DMA device that is
requesting the bus. The processor arbitrates all requests and
grants the bus to the DMA device electrically closest to it. A DMA
device remains bus master until it relinquishes its mastership.
The following control signals are used during bus arbitration.
DMA
DMA
DMA
Bus

BDMGI L
BDMGO L
BDMR L
BSACK L

grant input
grant output
request line
grant acknowledge

DMA Protocol

A.4.1

A DMA transaction can be divided into three phases:
1.

Bus mastership acquisition phase

Bus mastership relinquishment phase.

Data

transfer

phase

During the bus mastership acquisition phase, a DMA device requests
bus by asserting BDMR L. The processor arbitrates the request
the
and initiates the transfer of bus mastership by asserting BDMGO L.
The maximum time between BDMR L assertion and BDMGO L assertion is
DMA
latency. This time is processor-dependent. BDMGO L/BDMGI L is

one
signal
that
is
daisy-chained
through
each
module in the
backplane.
It
is driven out of the processor on the BDMGO L pin,
enters
each
module
on the BDMGI L pin, and exits on the BDMGO L
pin. This signal passes through the modules in descending order of
priority
until
it
is
stopped
by
the
requesting
device. The
requesting
device
blocks the output of BMDGO L and asserts BSACK
L.

BDMR

During
BSACK

continuously

asserted,

the

bus

hangs.

the data transfer phase, the DMA device continues
L.
The
actual
data
transfer
is
performed as

asserting
described

earlier.

The

DMA

device

(minimum)

after

becomes

negated.

can

assert

BSYNC

for

it received BDMGI L and

data

transfer

its BSYNC L bus

250

receiver

Q22-Bus

Specification

During

the

gives
(or
BSACK

BSYNC

DMA

bus
mastership
relinquishment phase, the DMA device
the bus by negating BSACK L. This occurs after completing
aborting)
the
1last
data
transfer cycle
(BRPLY L negated).

up
L

may

negated

Figure

A-7

request/grant

shows

the

maximum

DMA

300

protocol,

and

before

Figure

timing.

negating

A-8

NOTE

multiple
during this

data

transfers are performed
phase, consideration must be

given
to
the
use of
system functions, such
(if required).

the
as

bus for other
memory refresh

KDJ11-A PROCESSOR

BUS MASTER

(MEMORY IS SLAVE}

{CONTROLLER)

REQUEST BUS
—

GRANT BUS CONTROL

—— " ® ASSERT BDMR L

_—

® NEAR THE END OF THE

CURRENT BUS CYCLE

{BRPLY
IS NEGATED).
~— _

ASSERT BOMGO L AND

INHIBIT NEW PROCESSOR

GENERATED BYSNC L FOR
THE DURATION OF THE

ACKNOWLEDGE BUS
& MASTERSHIP

DMA OPERATION

—~

BSYNC L AND BRPLY L

TERMINATE GRANT

® RECEIVE BOMG

®WAIT FOR NEGATION OF

® ASSERT BSACK

SEQUENCE

® NEGATE BDMGO

L AND

WAIT FOR DMA QPERATION TM

TO BE COMPLETED

T~
~~

—a

EXECUTE A DMA DATA
TRANSFER
® ADDRESS MEMORY AND

TRANSFER UP TO 4 WORDS

OF DATA AS DESCRIBED
FOR DATI.

OR DATO BUS

CYCLES
.~

RESUME

PROCESSOR

OPERATION

®RELEASE
THE BUS BY

TERMINATING BSACK L

(NO SOONER THAN

—

NEGATION

LAST

BRPLY

AND BSYNC L

® ENABLE PROCESSORGENERATED BSYNC
L

(PROCESSOR IS BUS

WAIT 4 4S OR UNTIL

MASTER) OR ISSUE

ANOTHER FIFO TRANSFER

ANOTHER GRANT IF

BDMR

1S PENDING BEFORE

L IS ASSERTED

REQUESTING BUS AGAIN.
A

Figure

A-7

DMA

Protocol

5030

shows

Q22-Bus

Specification

SECOND

—-t

REQUEST

le— DMa LATENCY
R anbenyant el sty ally ol day Shav iy S

T OMA

[

—

L—-onswmmum

A
L

Vb airalve
A

Lok

—_—————

R DMG

T SACK

\
r_

250 NS MINIMUM —e

\\\\\'

\\\\ \—.l\—-.

250 NS MINIMUM:

0NSM|N|MUM—D1

300 NS MINIMUM

L—

FONS MINIMUM

—»

0 NS MINIMUM

T DAL

(ALSO 8S7,

WTBT,

ADDR

r—300 NS MAXIMUM

—

DATA

r—mo NS MAXIMUM

REF)
NOTES:

1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER

3. BUS DRIVER OUTPUT AND BUS RECEIVER INPUT

INPUTS AND BUS RECEIVER QUTPUTS.

SIGNAL NAMES INCLUDE A “B" PREFIX.

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW:
T = BUS DRIVER INPUT
R = BUS RECEIVER QUTPUT

Figure A-8

A.4.2
For

Block Mode
increased

device
In
a

for
block

asserted,

consecutive

DMA Request/Grant Timing

DMA

throughput,

block

mode

DMA

may

wuse with memories that support this
mode
transaction,
the
starting

followed

data

for

assertion

that

implemented

type of transfer.
memory address is

address,

and

data

for

addresses.

eliminating
the
the
transfer
rate
cycles are described

1is

almost

below.

the

address

doubled.

The

for

each

DATBI

and

data

word,

DATBO

bus

Q22-Bus

Specification

A.4.2.1
the
same

DATBI
-- The
as
described

A-9.)
BWTBT

bus
the

The
BBS7

The
onto

master

device addressing
earlier for other

gates

BDAL<21:00>,

portion of the cycle is
bus cycles.
(See Figure

BBS7,

and

bus.

master asserts
a
maximum of

the first BDIN 100 ns
50 ns after asserting

BBS7

1is
remains

the

after BSYNC,
BDIN for the

negation

and asserts
first time.

a
request
to the slave for a block mode transfer. BBS7
asserted
wuntil a maximum of 50 ns after the assertion of
BDIN
for
the
last
time.
BBS7
may
be
gated
as
soon as the
conditions for asserting BDIN are met.
The

slave

asserts BRPLY a minimum of 0 ns (8 ns maximum to avoid
timeout)
after vreceiving BDIN, It asserts BREF concurrently
BRPLY
if
it
1is
a block mode device capable of supporting

bus
with

another
onto

BDIN

the

(maximum)

master

the

assertion
It

after

The
BDIN.

after

bus

the

BRPLY

negates

200

slave

gates

BDAL<15:00>

and

assertion

BDIN,

125

BRPLY.

data

The

the

stable

until

BDIN

one.

after

assertion

receives
of

current

(minimum)

from

200

(minimum)
(minimum)

(maximum)

after
after

the
the

after
negation of

assertion

BRPLY.

The

slave

negates

BBS7

and

BREF

slave

prepares

for

after

BDIN

master

asserts

BRPLY

are

(minimum)

both

another

BDIN

negation

BRPLY

BBS7

BDIN.

negated,

BRPLY

negated.

ns
The

(minimum)

after

BRPLY

negated,

and

BDIN

150

stable

from

the

after

until

cycle.

the

when

asserted
150

after

asserted

125

the
cycle
1is continued as before. (BBS7 remains asserted and the
slave
responds
to BDIN with BRPLY and BREF.) BREF is stable from
75
ns after BRPLY is asserted until 20 ns (minimum) after BDIN is
negated.
If

BBS7 and BREF are not both asserted when BRPLY is negated, the
slave
removes
the
data
from
the bus 0 ns (minimum) and 100 ns
(maximum)
after
negating
BRPLY. The master negates BSYNC 250 ns
(minimum)
after
the
assertion
of
the
1last
BRPLY,
and
0 ns
(minimum) after the negation of that BRPLY.

A.4.2.2
DATBO
the
same
as
BDAL<21:00>,

-- The device addressing
shown
1in
Fiqure
A-10.

BBS7,

minimum

the

negated

and

asserts

The

BDOUT

slave

before

the

after

BWTBT

minimum

receives

the

negation

100

and

assertion

BDOUT.

receiving

BDOUT.

block

mode

current

one.

after

a
the

assertion

BSYNC

are
of

100

stable
of
The
also

put
ns

data
BDOUT

slave

BWTBT

onto

asserted,
onto

after

and
to

asserts

device

portion of the cycle is
The
bus
master
gates

BREF

capable

data

the

bus.

gating

the

BWTBT

from

BRPLY

the

on
The

BDAL<15:00>
master

(minimum)
0

then

data.

(minimum)
after

(minimum)

concurrently
of

bus.

supporting

with

BRPLY

another

the

after
if

BDOUT

Q22-Bus

Specification

SIGNALS AT BUS MASTER

Tas?
R/T DAL

150

ja— 0 —o

100

TSYNC

—|

T DIN

3 |

00—

2000°

|n-2oo—-

|——300—

]

(vl

s|lag]

alelal
R RPLY

200 1}

le—100 -

R DATA

XXXXX
200°

xxxxX | R DATA
200°

T ADDRESS

R REF

TIMES ARE MIN. EXCEPT WHERE “*” DENOTES MAX.
MR-15966

Figure A-9

DATBI Bus Cycle Timing

SIGNALS AT BUS MASTER

Tos7

AL,

TSYNC |

._.1

‘._100__

150+1oo

[
o—.I

150

100+

150

-—150-fl

175—-'-—200—1

T DOUT

R RPLY

DATA

ADDRESS

T DAL

—

u It2

t3|t4 t5|t6

R REF

3}
ha—17

J-_

TIMES ARE MIN. EXCEPT WHERE “*” DENOTES MAX.

s
MRA-15967

Figure A-10

DATBO

Bus

Cycle

Timing

A-19

Q022-Bus

Specification

The

master
negates BDOUT 150 ns
(minimum) after the assertion of
BRPLY. If BREF was asserted when BDOUT was negated, and the master
wants to transmit more data in this block mode cycle, the new data
is
gated
onto
the
bus 100 ns (minimum) after BDOUT is negated.

BREF
is stable from 75
20
ns
(minimum) after
100
ns
minimum

(minimum)
after BRPLY

BREF

was
does

master

removes

not

asserted
want

data

BDOUT.

The

slave

BDOUT.

The

bus

(maximum)
is

after

negated.

when

BDOUT was

transmit

from

the bus
negates
BRPLY

master
and 0 ns

negating

BDOUT,

A.4.3

DMA Guidelines

negates
(minimum)

100
0

ns
ns

BSYNC

after

Systems
with memory refresh over
devices
that
perform
more
acquisition.

Bus masters that
DATI, four DATO,

do
or

Block

masters
transfers

mode

limited
4.,

BRPLY
The

master

after
gating new data onto the
negates. The cycle continues as

not

master

BDOUT

bus
eight

not
two

until

asserts

BDOUT

bus and
before.

negated,
data

asserted

this

(minimum)
(minimum)

150

the

bus

cycle,

the

after
after

negating
negating

175
ns
(minimum) after
the negation of BRPLY.

the bus must not include
than
one
transfer
per

use block mode are limited to four
DATIO transfers per acquisition.
that

per

do
not
monitor
acquisition.

BDMR

are

If
BDMR is not asserted after the seventh transfer, block
mode
bus masters that do monitor BDMR may continue making
transfers
until
the
bus
slave fails to assert BREF, or
until
they
reach
the
total
maximum
of
16 transfers.
Otherwise, they stop after eight transfers.

A.5
INTERRUPTS
The
interrupt
capability
of the 022-Bus allows an I/0 device to
temporarily
suspend
(interrupt)
current
program
execution and
divert
processor
operation to service the requesting device. The

processor

inputs

vector

from the

device

start

the

service

routine
(handler).
Like
the
device
register address, hardware
fixes
the
device
vector
at locations within a designated range
below location 001000. The vector indicates the first of a pair of
addresses.
The processor reads the contents of the first address,
the starting address of the interrupt handler. The contents of the
second address is a new processor status word (PS).
The

new

preventing

can

raise

lower-level

the

interrupt

interrupts

from

priority
breaking

1level,
into

the

thereby
current

interrupt
service routine. Control is returned to the interrupted
program
when
the
interrupt
handler
1is
ended.
The
original
interrupted
program's
address
(PC)
and
its
associated PS are
stored on a stack. The original PC and PS are restored by a return

from interrupt (RTI or RTT) instruction at the end of the handler.
The
use
of
the stack and the Q22-Bus interrupt scheme can allow
interrupts
to
occur
within
interrupts
(nested
interrupts),
depending on the PS,

A-20

Q22-Bus

Specification

be caused by 022-Bus options or the MicroVAX CPU.
can
Interrupts
from within the processor are
that originate
interrupts
Those
“traps®TM.

called

Traps are caused by programming errors,

errors, special instructions, and maintenance features.

hardware

The following are Q22-Bus signals used in interrupt transactions.
BIRQ4
BIRQS
BIRQ6
BIRQ7
BIAKI

L
L
L
L
L

Interrupt
Interrupt
Interrupt
Interrupt
Interrupt

request priority level
request priority level
request priority level
request priority level
acknowledge input

4
5
6
7

Interrupt acknowledge output

BIAKO L

BDAL<21:00>
BDIN L
BRPLY L

Data/address lines
Data input strobe
Reply

Device Priority
A.5.1
The Q22-Bus supports the following

two methods of device priority.

Distributed Arbitration -- Priority levels are implemented
on
the
hardware.
When
devices
of equal priority level
request
an
interrupt,
priority
1is
given to the device
electrically closest to the processor.

Position-Defined
Arbitration
-~
Priority
is determined
solely
by
electrical
position
on the bus. The closer a
device is to the processor, the higher its priority is.

A.5.2
Interrupt Protocol
Interrupt
protocol on the 022-Bus

has three
request
phase,
interrupt
acknowledge
and
phase,
and interrupt vector transfer phase.
interrupt request/acknowledge sequence.

phases: the interrupt
priority arbitration
Figure A-11 shows the

The
interrupt
request
phase
begins
when
a
specific
conditions
for
interrupt
requests.

device
meets
For
example,

its
the

device
is
ready,
done,
or an error has occurred. The interrupt
enable
bit
in
a
device status register must be set. The device
then
initiates
the
interrupt by asserting the interrupt request
line(s).
BIRQ4
L
1is
the
lowest hardware priority level and is
asserted

for

all

interrupt

requests

for

compatibility

with

previous Q22 processors. The level at which a device is configured

must

also

that
must
discussion

Interrupt

4
S
g

asserted.

special

case

exists

for

level

also
assert level 6. For an explanation,
below on arbitration involving the 4-level

Level

devices

to
scheme.

Lines

Asserted

by Device

BIRQ4
BIRQ4
BIRQ4

L
L,
L,

BIRQS
BIRQ6

L
L

BIRQ4

BIRQ6

BIRQ7

refer

the

Q022-Bus

Specification

DEVICE

PROCESSOR

INITIATE REQUEST

STROBE INTERRUPTS

® ASSERT BDIN L

—_—

—— ® ASSERT BIRQ L

—_—

—

S——

—_—

‘

RECEIVE BDIN L
® STORE “INTERRUPT SENDING”

IN DEVICE

GRANT REQUEST
e PAUSE AND ASSERT BIAKO L

—

—_—
—_—

—

RECEIVE BIAKI L
®

RECEIVE BIAK(I L AND INHIBIT

BIAKO
L

® PLACE VECTOR ON BDAL < 15:00
> L
e ASSERT BRPLY L

® NEGATE BIRQ L
-

RECEIVE VECTOR AND
TERMINATE REQUEST
e

INPUT VECTOR ADDRESS

NEGATE BDIN L AND BIAKO L

— -

—
—_—

—_—

TE
VECTOR TRANSFER
COMPLE
®

REMOVE VECTOR FROM BDAL BUS

- -® NEGATEBRPLY L

— -

PROCESS
THE INTERRUPT

® SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK

® {OAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION

® EXECUTE INTERRUPT SERVICE
ROUTINE FOR THE DEVICE
MR-1182

Figure A-11

Interrupt Request/Acknowledge Sequence

022-Bus

The

interrupt

acknowledged.

Specification

request line remains asserted until the request is

interrupt acknowledge and priority arbitration phase,
puring the
interrupts under the
acknowledges
processor
LSI-11/23
the
following conditions.

interrupt priority is higher than the current

The

device

The

processor

PS<7:5>.

additional

has completed instruction execution and no

bus cycles

are pending.

The processor acknowledges the interrupt request by asserting BDIN
BIAKO L. The device
later asserting
(minimum)
ns
150
and
L,
electrically closest to the processor receives the acknowledge on
its BIAKI L bus receiver.

At this point,
If
separately.
4-level

types of arbitration must be discussed
two
the
the device that receives the acknowledge uses the

interrupt scheme,

reacts as follows.

If not requesting an interrupt, the device asserts BIAKO L
acknowledge propagates to the next device on the
the
and

bus.

1is requesting an interrupt, it must check
device
the
If
is currently requesting an
device
higher-level
no
that
interrupt. This

lines.The

table

is done by monitoring higher-level

below

1lists

the

request

1lines that need to be

monitored by devices at each priority level.

7 and 4, level 7 devices must
1levels
asserting
to
addition
In
the monitoring and
simplify
to
done
is
This
6.
level
drive
4 and 5 devices. In this protocol, level 4
1level
by
arbitration
and
5
devices
need
not monitor level 7 because level 7 devices
assert
level
6.
Level 4 and 5 devices become aware of a level 7
request
because
they
monitor the level 6 request. This protocol
for level 4, 5, and 6 devices, since level 7
optimized
been
has
devices

are

Device

very

seldom

necessary.

Priority Level

Line(s)

4
5

BIRQS5,
BIRQ6

BIRQ7

Monitored
BIRQ6

Q22-Bus

Specification

If
no higher-level device is requesting an interrupt, the
acknowledge
1is
blocked
by
the
device.
(BIAKO L is not
asserted.)
Arbitration
1logic
within the device uses the
leading
edge
of
BDIN L to clock a flip~-flop that blocks
BIAKO
L.
Arbitration
1is
won,
and the interrupt vector
transfer phase begins.

If
a
higher-level
disqualifies
1itself
acknowledge

Signal

reacts

the

device

timing

4-level
If

request
line
1is
and asserts BIAKO

must
be
considered
interrupts. See Figure A-12,

single-level
as

interrupt

along

the

carefully

device

active, the device
L to propagate the

receives

bus.
when

the

implementing

acknowledge,

follows.

TIf not requesting an interrupt, the
and
the
acknowledge propagates to

device asserts BIAKO L
the next device on the

bus.

INTERRUPT LATENCY
MINUS SERVICE TIME

TIRQ

p-—

150 NSMINIMUM—’1

—

R 1AKI
TRRLY

4.]\

125 NS MAXIMUM —]

T DAL

RSYNC

{UNASSERTED)

f'—mo NS MAXIMUM

—

)(

VECTOR

{UNASSERTED!

R BS?
NOTES

1. TIMING SHOWN AT REQUESTING DEVICE BUS DRIVER
INPUTS AND BUS RECEIVER OUTPUTS

3. BUS DRIVER QUTPUT AND BUS”fiECEIVER INPUT
SIGNAL NAMES INCLUDE A "8 PREFIX

2. SIGNAL NAME PREFIXES ARE DEFINED BELOW

4. DON'T CARE CONDITION

T = BUS DRIVER INPUT

R = BUS RECEIVER QUTPUT
LRI

Figure A-12

Interrupt Protocol Timing

Q22-Bus

Specification

If the device was requesting an interrupt, the acknowledge
is
blocked
using
the
1leading
edge
of
BDIN
L,
and
arbitration
1is
won.
The interrupt vector transfer phase
begins.

The interrupt vector transfer phase is enabled by BDIN L and BIAKI
L.
The device responds by asserting BRPLY L and its BDAL<15:00> L
bus
driver
inputs
with
the
vector
address bits. The BDAL bus
driver inputs must be stable within 125 ns (maximum) after BRPLY L
is
asserted.
The
processor
then
inputs the vector address and
negates
BDIN
L
and BIAKO L. The
100
ns
(maximum)
later
removes
processor then enters the device's

device then negates BRPLY L
the
vector
address bits.
service routine.

and
The

NOTE

Propagation
delay from BIAKI
L
must
not
be greater than
Q22-Bus slot.

L to BIAKO
500 ns per

The device must assert BRPLY L within 10
us (maximum) after the processor asserts
BIAKI

A.5.3
- Q22-Bus 4-Level Interrupt Configurations
If you have high-speed peripherals and desire better software
performance,
you
can
use
the
4-level
interrupt
scheme. Both
position-independent
and position-dependent configurations can be
used with the 4-level interrupt scheme.
Figure
A-13
shows
the
position-independent configuration. This
allows peripheral devices that use the 4-level interrupt scheme to
be
placed
in the backplane in any order. These devices must send
out
interrupt
requests and monitor higher-level request lines as
described.
The
level
4
request
1is
always
asserted
from
a
requesting
device
regardless of priority. If two or more devices
of
equally
high
priority
request
an
interrupt,
the
device
physically closest to the processor wins arbitration. Devices that
use

the

single-level

end

the

bus,

interrupt

for

scheme
arbitration

must

be modified, or placed
function properly.

Figure
A-14
shows
the
position-dependent
configuration.
This
configuration
is
simpler
to
implement.
A
constraint
1is that
peripheral
devices
must
be
inserted
with the highest~priority
device located closest to the processor, and the remaining devices
placed
in the backplane in decreasing order of priority (with the
lowest-priority
devices
farthest
from the processor). With this
configuration,
each
device
has to assert only its own level and
level
4.
Monitoring
higher-level
request lines is unnecessary.
Arbitration
is
achieved through the physical positioning of each
device
on
the
bus.
Single-level
interrupt
devices on level 4
should be positioned last on the bus.

BIAK (INTERRUPT ACKNOWLEDGE)

LEVEL4

DEVICE

BIRQ
4 (LEVEL
4 INTERRUPT REQUEST)

jglak | LEVEL6

|BlaK | LEVELS

DEVICE

|gjak | LEVEL7
DEVICE

)

BIRQ S (LEVEL 5 INTERRUPT REQUEST)
BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)
BIRQ
7 (LEVEL
7 INTERRUPT REQUEST)

]
MR -2888

Figure A-13

Position-Independent Configuration

BIAK (INTERRUPT ACKNOWLEDGE)

LEVEL7

DEVICE

DEVICE

BIRQ 4 (LEVEL 4 INTERRUPT
REQUEST)
BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)
BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)

BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)

A
MA-2889

Figure

A-14

Position-Dependent Configuration

uor3jeostjyioads sng-zzd

9¢-¥

KDJ11

Q22-Bus

Specification

CONTROL FUNCTIONS

A.6

The following Q22-Bus signals provide control functions.
BREF L
BHALT L
BINIT L

BPOK H
BDCOK H

Memory refresh
Processor halt
Initialize
Power OK
DC power

(also block mode DMA)

Memory Refresh
A.6.1
If
BREF
1is
asserted
during
the
address portion of a bus data
transfer cycle, it causes all dynamic MOS memories to be addressed
simultaneously.
The sequence of addresses required for refreshing
the
memories
1is determined by the specific requirements for each

memory.
The complete memory refresh cycle consists of a series of
refresh
bus
transactions.
A
new
address
is
used
for
each
transaction.
A
complete
memory
refresh cycle must be completed
within
1
or 2 ms. Multiple data transfers by DMA devices must be
avoided since they could delay memory refresh cycles. This type of
refresh
is
done
only
for memories that do not perform on-board
refresh.

A.6.2

Halt

Assertion
of BHALT L for at least 25 ns interrupts
which
stops
program
execution
and
forces
unconditionally into console I/0 mode.
A.6.3

the processor,
the
processor

Initialization

Devices
along
the
bus are initialized when BINIT L is asserted.
The processor can assert BINIT L as a result of executing a reset
instruction
as part of a power-up or power—-down sequence. BINIT L
is asserted for approximately 10 us when reset is executed.
A.6.4
Power Status
Power
status
protocol
BDCOK
H.
These signals
the power supply).
A.6.5
When

BDCOK
asserted,

least
3
ms.
power
fails,
remains.

is
are

H
this

indicates
Once asserted,
It
1indicates

controlled

driven

that

this
that

by two signals, BPOK H and
an external device (usually

power has been stable for at
line remains asserted until the
only
5 us of dc power reserve

A.6.6
BPOK H
When asserted, this indicates there is at least an
dc
power,
and that BDCOK H has been asserted for
Once

BPOK

3 ms. The
sequence,
power

has

been

asserted,

must

remain

8 ms reserve of
at least 70 ms.

asserted

for

negation of this line, the first event in the
indicates that power is failing and that only

reserve

remains.

least

power-fail
4 ms of dc

Q22-Bus

Specification

A.6.7
Power-up
BDCOK

the

Power-Up/Down Protocol
protocol begins when the
negated.

device

This

forces

the

power

supply

processor

voltages
asserts

floating

applies

assert

power

BINIT

with

When

are
stable, the power supply or other external
H. The processor responds by clearing the PS,
status register (FPS), and floating point exception
BDCOK

point
register
(FEC). BINIT L is asserted for 12.6 us, and then negated
for 110 ps. The processor continues to test for BPOK H until it is

asserted.
BDCOK

The

sequence.

The

power-down

BPIK

then
maintained at

sequence

current

terminated
corruption

asserts

processor

power must be
sequence can begin.

power-down

the

supply

Normal

power-down

When

power

asserted.

begins when the power
instruction is completed,

routine

with
as the

a
dc

location

24.

The

halt instruction
voltages decay.

end

(minimum)

performs

least

its

3.0

after

power-up

before

supply negates BPOK
the processor traps

avoid

the

any

routine

possible

H.
to

memory

When
the
processor
executes
the halt instruction, it tests the
BPOK
H
signal.
If
BPOK
H is negated, the processor enters the
power—-up
sequence.
It clears internal registers, generates BINIT
L,
and
continues
to check for the assertion of BPOK H. If it is
asserted
and dc voltages are still stable, the processor performs
the
rest
of
the
power-up
sequence.,
Figure
A-15
shows
power-up/power—-down

BINIT L

timing.

—'l I‘— 8-204S

|‘—ONSMINIMUM

——

8 POK H

\L_—_____[

3Msy

\__._l!

3Mms
MINIMUM | IMAXIMUM

145
MAXIMUM

J
70 MS

4MS

1 minvom [*
lf

BDCOK H
— }7

MINIMUM

IMUM
ro—
3 MS
MINIMU

'J
=

5uS

MiNIMUM

70 MS

MINIMUM

r—

DC POWER

POWER UP

SEQUENCE

NORMAL

POWER-DOWN

POWER

SEQUENCE

POWER UP

SEQUENCE

NORMAL
POWER

NOTE
ONCE A POWER-DOWN SEQUENCE IS STARTED
1T MUST BE COMPLETED BEFORE A POWER UP

SEQUENCE 1S STARTED

“n $012

Figure

A-15

Power-Up/Power-Down

Timing

Q22-Bus

A.7

Q22-BUS

SIGNAL

LEVEL

Input

Output

A.7.1

Logic

ground.

loads

Low
High

0.8
2.0

Vdc
Vdc

(maximum)
(minimum)

0.4
2.4

Vvdc
Vdc

(maximum)
(minimum)

Levels:

Logical
Logical

Load

loads

Levels:

Logical
Logical

TTL
TTL

ELECTRICAL CHARACTERISTICS

SPECIFICATION

Logic

TTL
TTL

Specification

Low
High

Definition

make

the

unit

maximum

load

capacitance

defined

are

allowed

9.35

per

signal line
capacitance. DC

defined
as maximum current allowed with a signal line
asserted or unasserted., A unit load is defined
as 210 pA in
unasserted state.

driver

the

A.7.2
120-0hm Q22-Bus
The electrical conductors
treated

transmission

terminated
electrical

in
its
signal

interconnecting
1lines,

the

bus

wuniform

characteristic

device

slots

transmission

are

line,

impedance,
propagates
an
reflections.
Since
bus
drivers,
receivers,
and wiring connected to the bus have finite resistan
ce
and
nonzero
reactance,
the
transmission
line impedance is not
uniform,
and
introduces distortions into pulses propagat
ed along
it.
Passive
components
of the 022-Bus (such as wiring, cabling,
and
etched
signal
conductors)
are
designed
to have a nominal
characteristic impedance of 120 ohms.
The
maximum
length
within the backplane,
A.7.3

Bus Drivers
driving
the

Devices
outputs

and

meet

the

without

interconnecting
cable, excluding
limited to 4.88 m (16 ft).

120-ohm
following

Q22-Bus

must

have

open

specifications.

wiring

collector

SPECIFICATIONS

Output
1low
(maximum)
.

Output

high

voltage

These

conditions

and

input

sinking

1leakage current when connected

(even

when

power

signal

must

applied,
be

levels.

met

except

for

current:

to 3.8 Vdc:

0.7

25 uA

BDCOK H and BPOK H).

worst-case

supply

temperature,

Q22-Bus

Specification

SPECIFICATIONS

Bus

driver

output

Propagation

delay:

Skew

(difference
fastest gate): Not

Rise/fall times:
transition,
90%
faster

A.7.4
Devices
the
DC

than

Not
in
to

Transition
to

load:

10%

ns.

Not

exceed

pPF.

ns.

propagation
exceed 25 ns.

time

between

slowest

and

time (from 10% to 90% for positive
for negative transition) must be no

signals
requirements.

following

from

the

1.3

120-ohm

Q22-Bus

must

meet

Vdc:

(even

SPECIFICATIONS

Input

low

Input

high

voltage
voltage

(maximum):
(minimum):

current when
applied).

These

specifications

voltage,

temperature,

1.7

connected

must

and

be
met
output signal

3.8

worst-case
conditions.

supply

SPECIFICATIONS

Bus

receiver

Propagation

input

capacitance

delay:

Not

Skew

(difference
fastest gate): Not

A.7.5
The

Bus
120-ohm

propagation

Termination
Q22-Bus
must
terminator,
as
voltage divider

120

ohms

3.4

exceed

appropriate
done
as
a

exceed

Bus Receivers
that
receive

Maximum
input
if no power is

capacitance

load:

Not

exceed

pF.

ns.

time

between

slowest

ns.

terminated
at
each
end
by
shown
in Figure A-16. This is to
with its Thevenin equivalent equal

and

an
be

to
type of termination is provided
REV11-A refresh/boot/terminator, BDV11-AA, KPV11-B, TEV1l,
certain backplanes and expansion cards.
and

(nominal).

This

Q22-Bus

Specification

+5V

178 Q2

3302
1200
BUS LINE
TERMINATION

250
Q2
BUS LINE
TERMINATION

383 Q

680
Q

Figure A-16

Bus

MA-8033

Line

Terminations

Each
of
the
several
(Q22-Bus lines (all signals whose mnemonics
start
with
the letter B) must see an equivalent network with the
following characteristics at each end of the bus.
Input
(with
Open

impedance
respect to
circuit

Capacitance

120

ohm +5%,

-15%

3.4

Vdc

+5%

Not

exceed

ground)

voltage
load

NOTE

The
resistive
termination
may
be
provided
by
the
combination
of
two
modules.
(The processor module supplies
220
ohms
to
ground. This, in parallel
with
another 220-ohm card, provides 120
ohms.)
Both
terminators
must
reside
physically within the same backplane.
A.7.6

Bus

Interconnecting

Wiring

A.7.6,1
Backplane Wiring ~irterface
slots
on
the
specifications.

The
a

conductors

respect

must

characteristic
to

Crosstalk
percent.

the

simultaneously
measuring

the

arranged

impedance

bus

between
Note

The wiring that connects
Q022~-bus
must
meet
the

commen

any

that

that
120

each
ohms

line

exhibits

(measured

with

return).

two

lines

worst-case

driving
effect

all device
following

all
the

must

crosstalk

but

undriven

one

greater

signal

line.

than

manifested

1line

5
by

and

Q22-Bus

Specification

DC
resistance of the signal path, as measured between the
near-end
terminator
and
the
far-end
terminator module
(including
all
intervening connectors, cables, backplane

wiring,

connector-module

etch,

ohms,
4.

etc.)

must

not

exceed

resistance
of
the
common
return
path, as measured
between the near-end terminator and the far-end terminato
r
module
(including
all
intervening
connectors,
cables,
backplane
wiring,
connector-module
etch, etc.) must not
exceed
an equivalent of 2 ohms per signal path. Thus, the
composite signal return path dc resistance must not exceed
2 ohms divided by 40 bus lines, or 50 milliohms. Note that
although
this
common
return path is nominally at ground
potential, the conductance must be part of the bus wiring.
The
specified
1low impedance return path must be provided

the

power

bus

wiring

ground

distinguished

from

the

common

path.

system

A.7.6.2

Intra-Backplane
Bus Wiring -- The wiring that connects
connector slots within one contiguous backplane is part of
the
overall
bus
transmission
1line.
Owing
to
implementation
constraints,
the nominal characteristic impedance of 120 ohms may
the

bus

not

amount

exceed

achievable.
required

Distributed

per

achieve

signal

line

wiring

capacitance

the

nominal

per

backplane.

120-ohm

excess

impedance

A.7.6.3
Power and Ground -- Each bus interface slot has
pins assigned for the following dc voltages. The maximum
current

with

percent

per

1is

maximum

ripple

with

maximum

)

Vdc

+12

Ground

Vdc

1.5

Vdc

must

100

pp.

+12

Vdc

pp.

Three

---

Two

ripple

200

pins

(4.5

pins

Eight

(3.0
pins

maximum
maximum

(shared

SYSTEM
systems

per

bus

per

bus

power

device
device

return

is
not bussed between backplanes
interconnecting bus cables.

CONFIGURATIONS
can be divided

into

backplane

Systems

containing

one

Systems

containing

multiple

two

connector
allowable

to 5 percent
regulated to 3

NOTE

A.8
Q22-Bus

the
not

regulated

must

return)

Power
on any

of
may

types:

backplanes

slot)
slot)

and

signal

Q22-Bus

Before

module

configuring
any
in the system must
Power

system,
three
be known:

consumption

Specification

characteristics

Vdc

and

+12

for

Vdc

each

current

requirements.

AC
bus
presents

loading
-The
to a bus signal

terms
of
ac
capacitance.
DC
bus
module

Power

each

1loads,

1loading
presents

-to

(undriven).

where

load

one

amount
of capacitance a module
line. AC loading is expressed in
where one ac load equals 9.35 pF of

The
amount
of dc leakage current a
a
bus
signal when the line is high

equals

expressed

210

terms

loads,

(nominal),

consumption,
ac loading, and dc loading specifications for
module are included in the Microcomputer Interface Handbook.
NOTE

The
ac
and
dc
1loads
and
the
power
consumption
of
the
processor
module,
terminator module, and backplane must be
included
in
determining
the
total
loading of a backplane.
Rules

for

configuring

When
can

using

single-backplane
a

processor

accommodate

with

modules

loads

may

220-ohm

that

(total)
before
additional
Figqure
A-17.)
If more than
other end. of the bus must be
then

systems:

250 Q

UNIT
LOAD

the

{

present.

ONE

LOAD

UNIT

| OPTIONAL

UNIT

1209

34V

—

35 AC LOADS

20 DC LOADS

PROCESSOR

)

34V

1~
-

TERM
MR-5034

Figure

A-17

bus

loads

(14 IN) MAXIMUM

P
ONE

termination,

termination is required.
(See
20 ac loads are included, the
terminated with 120 ohms, and

BACKPLANE WIRE

35.6 CM

have

Single~Backplane

Configuration

022-Bus

Specification

With
120-ohm processor termination, up to 35 ac loads can
be
used
without
additional
termination. If 120-ohm bus
termination
1is added, up to 45 ac loads can be configured

the

backplane.

The

bus

can

The
(14

bus
in)

signal
long.

Rules

for

accommodate

configuring

Figure

lines

A-18
system.

The
(10

signal
1lines
in) long.

Each

shows

each

can
(total).

not

added

will

the

that

backplane
loads

DC
20

1loading
loads

another

all

can

loads

(total).

35.6

may

make

25.4

systems:

three

backplanes

backplane

can

accommodate modules that
Unused ac loads from one

exceed

backplane

have up to 22
backplane may

backplane

the

second

desirable

loads.

backplanes
equally,
or
with
first and second backplanes.
4.

multiple-backplane

the

modules

the

all

highest

backplanes

backplane
to

loads

cannot

load

the

exceed

(total).

Both
ends
of
the
bus must be terminated with 120 ohms.
This
means
the
first
and
last backplanes must have an
impedance of 120 ohms. To achieve this, each backplane may
be
1lumped
together
as
a
single
point.
The resistive
termination
may
be
provided
by
a
combination
of two
modules
in
the
backplane
- the processor providing 220
ohms
to
ground in parallel with an expansion paddle card
providing 250 ohms to give the needed 120-ohm termination.
Alternately,
a
processor
with 120-ohm termination would
need
no
additional
termination
on
the
paddle card to
attain
120 ohms in the first box. The 120-ohm termination
in
the
1last
box
can
be
provided
in
two
ways:
the
termination
resistors
may reside either on the expansion
paddle
card,
or
on
a bus termination card (such as the
BDV1l).

The

61
7.

The

cable(s)

ft)

connecting

the

first

two

backplanes

(are)

length.

cable(s) connecting the second backplane to the third
backplane
is
(are)
122 cm (4 ft) longer or shorter than
the cable(s) connecting the first and second backplanes.~

combined

(16

ft).

The
120

ohms.

cables

1length

used

must

of both cables

have

cannot exceed 4.€8 m

characteristic

impedance

Q22-Bus

|‘_'

BACKPLANE WIRE

35.6CM (18 IN) MAX
]

250 Q

—{

Specification

)
l

ONE

UNIT

LOAD

CABLE

34V

—

20 AC LOADS MAX

PROCESSOR

BACKPLANE WIRE

|'—— 25.4 CM (10 IN) MAX

CABLE

[

ONE

UNIT

LOAD

ADDITIONAL

CABLE

20 AC LOADS MAX

CABLES AND

BACKPLANE

BACKPLANE WIRE

25.4 CM {10 IN}) MAX

’l

|
ONE

1200

UNIT

34V

CABLE/

LOAD

ONE

UNIT
LOAD

TERM

M
20 AC LOADS MAX

NOTES:
1. TWO CABLES (MAX) 4.88 M (16 FT) (MAX)
TOTAL LENGTH.

2.20 DC LOADS TOTAL (MAX).
MR.6035

Figure A-18

Multiple-Backplane

Configuration

Q22-Bus

Specification

Power Supply Loading
A.8.1
Total
power
requirements for each backplane can be determined by
obtaining
the
total
power
requirements
for each module in the
backplane.
Obtain separate totals for +5 V and +12 V power. Power
requirements
for
each
module are specified in the Microcomputer
Interfaces

Handbook.

When
distributing
power
in
multiple-backplane
systems, do not
attempt
to
distribute
power
via
the
022-Bus
cables. Provide
separate,
appropriate power wiring from each power supply to each
backplane. Each power supply should be capable of asserting BPOK H
and BDCOK H signals according to bus protocol; this is required if
automatic
specific
The

power-fail/restart
require

peripherals

proper

use

BPOK

programs
orderly

and

BDCOK

are
implemented,
or
if
power-down halt segquence.
H

signals

strongly

recommended.
A.9

MODULE CONTACT FINGER IDENTIFICATION
Digital's
plug-in
modules
all use the same
identification system., A typical pin is shown
The

022-Bus
into a 2-slot
on
both
the
board).

contact finger (pin)
in Figure A-19,

is based on the use of quad-height modules that plug
bus connector. Each slot contains 36 lines (18 lines
component
side
and the solder side of the circuit

Slots,
row A, and row B include a numeric identifier for the side
of the module. The component side is designated side 1, the solder
side
is
designated
side
2,
as
shown
1in Figure A-20. Letters
ranging
from
A
through
V (excluding G, I, 0, and Q) identify a
particular pin on a side of a slot. Table A-4 lists and identifies
the
bus
pins
of
the
quad-height
module. A bus pin identifier
ending with a 1 is found on the component side of the board, while
a
bus
pin identifier ending with a 2 is found on the solder side
of the board.

The
positioning
protrusion on the

notch
between the two rows
connector block for correct

of pins mates with a
module positioning.

BE2

MODULE SIDE

SLOT (ROW) IDENTIFIER
“SLOT B"

IDENTIFIER
“SIDE
2" (SOLDER

SIDE)
PIN IDENTIFIER

“"PIN E”
MR-16553

Figure

A-19

Typical

Identification

System

Q22-Bus

Specification

ROW A

ROW B

ROWC

SIDE 1

SIDE 2

COMPONENT S)DE

SOLDER SIDE

ROW D

MR.5456

Figure

A-20

Quad

Height

Module

Contact

Finger

Identification

A-37

Q22~-Bus

Specification

Table A-4
Bus

Bus

Identifiers

Mnemonic(s)

Description

AAl

BIRQS

Interrupt

request

priority

level

ABl

BIRQ6

Interrupt

request

priority

level

ACl

BDAL16

Extended

address

bit

protocol;

during

memory

error

data

data
AD1

AE1l

BDAL17

Extended

SSPARE1l

(alternate

transfer

address

bit

protocol;

memory

during

transfer

data

Special

+5B)

protocol.

Spare

in
Digital's
assemblies;
connection.

used

for

power

~--

during

error

Not

keep

addressing

logic

assigned

cable
available
V

during

enable

protocol.

Optionally,

addressing
line

or
this

battery
critical

during

bussed

backplane
for
user

(+5

circuits

may

backup
alive

power
failures.
A
Jumper
Iis
required
on
Q22-Bus
options
to
open
(disconnect) the +5 B circuit in systems
that use this line as SSPARE1.

AF1

SSPARE2

Special

Spare -- Not assigned or bussed
in
Digital's
cable
or
backplane
assemblies;
available
for
user
interconnection. In the highest-priority
device
slot, the processor may use this
pin
for
a
signal
to indicate its RUN
state.

AH1

SSPARE3
SRUN

AJl

GND

Special

Spare -- Not assigned or bussed
simultaneously
in
Digital's
cable
or
backplane assemblies; available for user
interconnection.
An
alternate
SRUN
signal
may
be
connected
in
the
highest-priority set.
Ground

System

signal

ground

and

return.
AK1

MSPAREA

Maintenance
together
location

ALl

MSPAREB

Maintenance
together
location

Spare

on the
(not a

Spare

on the
(not a

Normally

connec?ed

backplane at e§ch option
bussed connection).

-- Normally

connec?ed

backplane at egch option
bussed connection).

Q022~Bus

Table A-4

Bus

Identifiers

Bus Pin

Mnemonic(s)

Description

AM1

GND

Ground

Specification

(Cont)

System

signal

ground

and

return.

AN1

BDMR

Direct

Memory Access (DMA) Reguest -- A
device
asserts
this
signal to request
bus mastership. The processor arbitrates
bus
mastership
between
itself and all

DMA

devices

the

bus.

the

processor

is
not
bus
master (it has completed a
bus
cycle
and
BSYNC
L
is
not being
asserted
by
the
processor), it grants
bus
mastership to the requesting device
by
asserting
BDMGO
L.
The
device
responds
by
negating
BDMR
L
and
asserting BSACK L.
APl

BHALT

Processor

Halt

asserted

for

-at

When

BHALT

1least

us,

is
the

processor
services
the
halt interrupt
and
responds
by halting normal program
execution.
External
interrupts
are
ignored but memory refresh interrupts in
Q22
are
enabled if W4 on the M7264 and
M7264~YA
processor
modules
is removed
and

DMA

request/grant

enabled.
The processor
microcode,
and
the
operation is invoked.
ARl

BREF

Memory

Refresh

sequences

executes
consocle

Asserted

are

the ODT
device

DMA

device.
This
signal forces all dynamic
MOS
memory
units requiring bus refresh
signals
to
be activated for each BSYNC
L/BDIN
L
bus
transaction.
It is also
used

control

signal

for

block

mode

DMA,

CAUTION:
The
wuser

must
avoid multiple DMA data
transfers
(burst
or
"hot"
mode) that
could
delay
refresh operation if using

DMA

refresh.

must

occur

required.

Complete
once

refresh

every

1.6

cycles
ms

022-Bus Specification

Table A-4
Bus
AS1

Bus

Identifiers

(Cont)

Description

(s)
Mnemonic
+12

+12

keep
power

Vdc

bussed

battery

backup

critical
c¢ircuits
alive
signal
This
failures.

BSl

System

all

power

during
not
is

Digital’'s

backplanes.
A jumper is required on all
022-Bus options to open (disconnect) the
backup
circuit
from the bus in systems
the alternate
at
1line
this
wuse
that
voltage.

ATl

Ground

GND

signal ground and dc

return.

AUl

PSPARE

AVl

Spare

customer usage

assigned;

Not

damage when
Prevents
recommended.
not
modules are inserted upside down.
+5

power

Power

Battery

connection.

-- Secondary +5 V

Battery power can be

used with certain devices.

BAl

BDCOK

BBl

BPOK

Power OK —-- A power supply-generated
DC
the
asserted when
is
that
signal
1is sufficient to
available dc voltage
sustain reliable system operation.

Power OK -- Asserted by the power supply
is negated when ac
after BDCOK
ms
70
drops below the value required to
power

(approximately

power

sustain

75%

When negated during processor

nominal).

operation, a power-fail trap seguence is
initiated.

BC1

Special

SSPARE4
BDAL18

only)

(22-bit

BD1

BE1l

only)

BF1

SSPARES6
BDAL20 L

SSPARE7
BDAL21

Spare

Bussed

the

Q22-Bus --

22-bit

Not

cable and

backplane assemblies; available for user
interconnection.

CAUTION:

SSPARES
BDAL19 L

(22-bit

assigned.

These pins may be used by manufacturing
as test points in some options.

the

lines

Q22-Bus,

are

these

address

bussed address

lines

521:18>;

currently not used during data time.

address
In the 022-Bus, these bussed <21:1
8>;
lines
ss
addre
are
lines
currently not used during data time.

Q22-Bus

Table

Bus
BH1

A-4

Bus

Identifiers

Mnemonic(s)

Description

SSPARES

Special

Spare
Digital’s

assemblies;

interconnection.
BJ1

GND

Ground

(Cont)

Not assigned
cable
and

available

System

MSPAREB

BL1

Maintenance

MSPAREB

together

location

(not

BM1

GND

Ground

Spare
the

signal

bussed

System

bussed
backplane

BSACK

and

connected

each

option

connection).

signal

ground

return.

BN1

user

ground

Normally

backplane

for

return,

BK1

Specification

and

This
signal
in
response

is asserted by a DMA device
to the processor's BDMGO L
indicating
that the DMA device

signal,
is bus master.
BP1

BIRQ7

BR1

BEVNT

Interrupt

External

request

Event

asserted,

Interrupt

the

entering

priority

+12

BT1

GND

Vdc

AS]l

service

Ground

battery

all

Request

processor

address
1008.
A
signal
is
as
interrupt.
BS1

level

routine

wuse
line-time

backup

System

PSPARE2

Power

signal

Spare

function;
module
1is

BV1

down

appears

this
clock

(not bussed
backplanes).

ground

Not

and

assigned

not recommended for use. If a
using -12 V (on pin AB2), and
module is accidentally inserted

if
the
upside

vector

power

Digital's

return.

BU1

via

typical

When

responds

the

backplane,

-12

vdc

BUl.

Power

Normal

Vdc

system

Power

Normal

Vdc

system

power,

AA2

power.

A-41

Q22-Bus Specification

Table A-4
Bus

AB2

Bus

Identifiers

(Cont)

Mnemonic(s)

Description

-12

=12
-Power
V
=12
devices
(optional)

power
Vdc
requiring

for
this

voltage.
NOTE:

requires
that
module
Q22-Bus
Each
contains an inverter
voltages
negative
required
the
generates
that
circuit

-12 V power is
Therefore,
voltage(s).
not required with Digital's options.

AC2

Ground

GND

System

signal ground and dc

return.

AD2

+12

AE2

BDOUT

+12 V Power -- +12 Vdc
L

system power.

BDOUT
asserted,
When
-~
Output
Data
that valid data is available on
implies
output
an
that
and
L
BDAL<0:15>
transfer, with respect to the bus master

device,

1is

taking

place. BDOUT L is

data on the
to
respect
with
deskewed
The slave device responding to the
bus.
must assert BRPLY L to
signal
L
BDOUT
complete the transfer.

AF2

BRPLY

Reply -- BRPLY L is asserted in response

L or BDOUT L and during IAK
BDIN
to
transactions. It is generated by a slave
that it has placed
indicate
to
device
data on the BDAL bus or that it has
its
accepted output data from the bus.

AH2

BDIN

Data

Input

BDIN

L is used for two

types of bus operations:

When asserted during BSYNC L time, BDIN
L implies an input transfer with respect

to the current bus master, and requires
a response (BRPLY L). BDIN L is asserted
ready
is
device
the master
when
accept data from a slave device.

%t
without BSYNC L,
asserted
When
indicates that an interrupt operation is
occurring. The master device must deskew
input data

A-42

from BRPLY L.

Q22~-Bus

Table A-4

Bus
AJ2

Mnemonic(s)
BSYNC

Bus

Synchronize
-BSYNC
L is asserted by
the
bus
master device to indicate that
it
has
placed an address on BDAL<0:17>
L.

BWTBT

The

transfer

sequence

BIRQ4

AM2

BIAKI

AN2

Interrupt

BIAKO

with

and

are

asserts

BIAKO

than

signal

when

and

interrupt

set.

the

responds
request
by

~--

L.
In

accordance

the

processor

acknowledge

receipt

interrupt. The bus transmits this
BIAKI
L
of the device electrically

closest

the

accepts

the

interrupt

two

output

Level

the

BIAKO

protocol,
L

edge

processor

Acknowledge

interrupt

two

addressing.

this

enable

rather

Priority

asserts

7 is 0, the
acknowledging

BDIN

BDOUT

byte

flips-flops

asserting

leading
that

during

Request

used

follow.

bit

1is

the

for

interrupt

word

until

cycle:

DATOB),

device

request

cycle,

Interrupt

asserted

process

bus

indicate

(DATO

bus

level

its

sequence,

DATOB

BWTBT

asserted

BSYNC

input

control

1is

negated.

Write/Byte
ways

AL2

(Cont)

Description

BSYNC

AK2

Identifiers

Specification

conditions:

the bus
device

processor.
1.)

the

This

acknowledge

device

device
under

requested

asserting

BIRQXL, and 2.) the
the
highest-priority
reguest
on
the
bus at that

has

interrupt
time.

If
these
conditions
are
device
asserts
BIAKO
L
device
on
the
bus.

not met, the
to
the
next

This
process
continues in a daisy-chain fashion until
the
device
with
the highest-interrupt
priority
receives
the
interrupt

acknowledge

signal.

Q22-Bus Specification

Table A-4
Bus
AP2

Mnemonic(s)
BBS7

Bus

Identifiers

(Cont)

Description
Bank
7 Select -- The bus master asserts
this
signal
to
reference the I/0 page
(including
that portion of the I/O page
reserved
for
nonexistent
memory). The
address
in
BDAL<0:12> L when BBS7 L is

asserted

the

address within

the

I/0

page.

AR2

BDMGI

AS2

BDMGO

Direct
Memory
Access
Grant -- The bus
arbitrator
asserts this signal to grant
bus
mastership
to a requesting device,
according
to
bus
mastership protocol.
The
signal
is
passed in a daisy-chain
from the arbitrator (as BDMGO L) through
the
bus to BDMGI L of the next priority
device
(the device electrically closest
on
the
bus).
This
device accepts the
grant
only
if
it
requested to be bus
master (by a BDMR L). If not, the device
passes
the
grant
(asserts BDMGO L) to
the next device on the bus. This process
continues
until
the
requesting device
acknowledges

the

grant.

CAUTION:

AT2

BINIT

DMA

device

with

the

transfers

memory

must

refresh

not

interfere

cycle.

Initialize
-~
This
signal is used for
system reset, All devices on the bus are
to
return
to
a
known, initial state;
that

1is,

and
logic
Exceptions
documented
engineering

registers

are

reset

zero,

is
reset
to
state
0.
should
be
completely
in
programming
and
specifications
for
the

device.
AU2

BDALO

AV2

BDAL1

two lines
These
-Data/Address lines
are part of the 16-line data/address bus
which address and data information
over

are communicated.

Address information is

the bus
by
bus
the
on
placed
first
then
device
same
The
device,
master
or
from,
data
input
receives
either

to,
data
outputs
memory
or
device
lines.

addressed slave
the
bus
same
the
over

022-Bus

Table A-4

Bus

Identifiers

Bus Pin

Mnemonic(s)

Description

BA2

Power

Specification

(Cont)

Normal

Vdc

system

power.

BB2

-12

supplied)

Power
-—

(optional)

(voltage

-12
devices

normally

vdc

power
requiring

voltage.
BC2

GND

Ground

System

signal

ground

not
for
this

and

return.

BD2

+12

Power

BE2

BDAL2

Data/Address

BF2

BDAL3

part

BH2

BDAL4

BJ2

BDALS

BK2

BDAL6

BL2

BDAL7

BM2

BDALS

BN2

BDALY9

BP2
BR2

BDAL1O

BDAL1l

BS2

BDAL12

BT2

BDAL13

BU2

BDALl14
BDAL1S

L
L

BV2

the

+12

Lines

16-line

system

power.

These 14 lines are
data/address bus.

A-45

APPENDIX

ACRONYMS

Interrupt Enable

AIE ~- Alarm
ANSI

- American National

ASTLVL -- Asynchronous
--

Binary

BDR

Boot

--~

BRS

Byte

CEAR

Coded

and

CPU

Error

Cyclic

CSR

Control

Select

Console

CRC

DEAR

DMA

Data

Program

Error

DSE

Daylight

MailBoX

Check

Status

Address

Memory

EIA

Electronic

ERR

ERRor

EDIT

Frame

Access

Saving

EDITPC

Mode

Direct

FPU

Address

and

signals

Redundancy

DMA

Mask
Rate

Decimal

Diagnostic

Baud

CPMBX

System Trap LeVel

Battery Backup Unit

BCD ~--

Institute

Pointer

AP -- Argument

BBU

Standards

Packed

Enable
to

Character

Industries

signal

Pointer

Floating

Point

Unit

string

Association

Acronyms

ICCS -- Interval Clock Control and Status register

IPCR -~ InterProcessor Communication Register
IPL -- Interrupt Priority Level

IPR -- Internal Processor Register
ISP -- Interrupt Stack Pointer
LSI -- Large Scale Integration

MAPEN -- memory management (MAPping) ENable register
MBZ

Must

Zero

MCS -~ Multinational Character Set

MFPR -- Move From Processor Register

MMU -- Memory Management Unit

MOP -- Maintenance Operation Protocol
MSER -- Memory System Error Register
MTPR -- Move To Processor Register

POBR -- PO

(P zero) Base Register

P1BR ~- Pl Base Register
PC

Program Counter

PIE -- Periodic Interrupt Enable

POLR -- PO (P zero)

Length Register

P1LR -- Pl Length Register
Page Table

POPT -- PO

(P zero)

P1PT -- Pl

Page Table

PROM -- Programmable Read-Only Memory
PSL -- Processor Status Longword
PSW -- Processor Status Word
PTE --

Page Table Entry

RPB -- Restart Parameter Block

Acronyms

SBR -- System Base Register

SCA -- System Communications Architecture
SCB -- System Control Block
SCBB -- System Control Block Base

SID -- System IDentification register
SIE -- System Identification Extension
SIRR -- Software Interrupt Request Register
SISR -- Software Interrupt Summary Register
SLR -- System Length Register
SLU -- Serial Line Unit
SP -- Stack Pointer
SPT -- System Page Table

SQWE -- SQuare-Wave Enable

TBIA -- Translation Buffer Invalidate All

TBIS -- Translation Buffer Invalidate Single
TOY -- Time-of-Year

UIE -- Update

Interrupt Enable

UIP -- Update

in Progress bit

VRT -- Valid
VMB

RAM and Time

-- Virtual

Memory

bit

Bootstrap

INDEX

Address

space

Console

halt mode, 4-43
run mode, 4-43
Address translation
PO region, 4-17

binary
boot,

console

unit

program

(BBU),

check

Boot

and diagnostic
(BDR), 4-30
Boot command flags,

Bootstrap,

3-10,

of,

3-36

auxiliary processor,
command,

3-19

3-14

from

DEQNA,

from
from

disk,
PROM,

3-17

from

tape,

3-17

order

3-13,

3-13

3-20

sequence,

3-10

supported

devices,

3-13

unload,

3-5

microstep,
next,

3-36

repeat,
set,

3-31

3-36

start,

test,

3-32

Console

command

syntax,

Console

control

characters

break, 3-23
carriage return,
control

3-22

control

3-23

control

3-23

control

R, 3-23
control U, 3-22
rubout, 3-22
Console error messages,

@ command,

Console
5-1

3-36

Configuration

Connector

J1,
J2,
J3,

2-2
2-3

2-5

board,

pinouts

2-5

3-24

3-23

Catastrophic

error, 3-35
CD interconnect, 1-3
CK-KA630-A insert, 2~9

3-25%

3-27

initialize,
load, 3-26

unjam,

3-19
3-14

devices,

secondary,

2-9

and

continue, 3-27
deposit, 3-27
examine, 3-29
find, 3-30
halt, 3-31

Arbiter mode, 1-8, 4-48
Argument pointer (AP), 4-1
Auxiliary mode, 1-8, 4-48
backup

load
3-26

comment,

Pl region, 4-20
process space, 4-17

Battery

commands

3-36

1/0 mode,

3-22,

Console

languages,

Console

program,

3-35,

3-6

3-1,

bitmap, 3-4
initialization,

3-3

power-up

3-3

modes,

3-33

4-33

Index-1

Index

Console program mailbox

Interrupts,

(CPMBX), 3-4, 3-7, 4-39
Console serial line unit (SLU),
4-40

Console terminal type, 3-5
Control and status register
4-36
4-36
4-37
4-37

connector
connector
connector

compatible, 2-11
Entry/dispatch, 3-7

nonexistent memory,
4-12

parity,

Error messages,

4-12

[=]

catastrophic, 3-35
hardware, 4-12

3-33

summary, 5-7
Load command, 3-36
Local memory, 1-3

CPU, 4-27
DMA, 4-28
memory, 4-24

Exceptions,

4-16

Gate array,

1-3

2-4,

3-1,

M7607-AA,
M7608-AA,

1-3
1-3

Machine check parameters, 4-8

3-2,

conditions, 4-9
error codes, 4-9
messages, 3-34
on break, 4-45
Hardware errors, 4-12
HLT ENB, 2-4, 4-31

3-7,

3-22

See Console program mailbox
Mapping registers, 4-21, 4-22

data transfer cycle, 4-28

management,

4-16

management control registers,
4-16

operation,

Instruction set, 1-2, 4-5
Interprocessor doorbell, 4-6
Interrupt latency, 4-14
Interrupt priority registers,

Interrupt vector timeouts,

Mailbox

Memory

4-32

4-7

Error

Le-]

Enclosures

4-14

Latency, 4-14
LED error codes
3, 5-7

4-28

DMA latency,

2-~1

4-48
1-8, 4-48

configuration board,

NN WWUUAODNN

1-2

DMA error address

Index-2

2-2
2-3
2-5

Language selections
LK201 keyboard, 3-7
Languages, 3-1

types

supported,

4-6,

4-46

2-5

4-1

4-32

D-stream,

I-stream,

pinouts,
pinouts,
pinouts,

connectors,

KA630CNF

t
wwtiuww wwt;:u\mm

CPU panel insert, 2-9
Current frame pointer,

Halt,

4-40,

auxiliary mode,

4-27

Error

4-6

timer,

KA630-AA CPU module
arbiter mode, 1-8,

CPU error address

Data

J1
J2
J3

A,
B,
Cc,
D,

Interval

4-13

4-28

refresh cycle, 4-28

registers, 4-22, 4-24
Memory management enable
(MAPEN),

Messages

halt,

3-34

4-16

Microstep command, 3-36

Index

MicroVAX 78032 microprocessor
chip,

1-2

MicroVax CPU chip,

MicroVAX interface gate array,
1-3

MS630 memory,

1-4

Multilevel interrupts, 4-45
Multiprocessing, 4-48

features, 4-49
Multiprocessor based systems
pDP-11, 4-49
Multinational character set

4-38

RAM memory,
Registers

console,

control
control
control
control

4-41

and
and
and
and

status
status
status
status

general purpose,

A, 4-36
B, 4-36
C, 4-37
D, 4-37

4-1

interprocessor communication,
4-46

mapping, 4-21
memory, 4-24

memory management control,
4-16

memory management enable,

Next command, 3-36
No Sack timeouts, 4-14
Nonexistent

4-16

errors,

memory

4-12

time-of-year,

1-3

region address

translation,

4-17

regicon address translation,
4-20

Page table entry
4-21

4-17,

(PTE),

4-12

Parity errors,

Physical

address

space,

4-16

Power-up mode, 5-1
Primary bootstrap, 3-12
Process space address
translation, 4-17

Processor

3-24

registers,

categories, 4-3
list, 4-4
summary, 4-4
Processor state, 4-1
Processor status longword
(PSL),

Processor

4-3

system identification
4-15

On-board memory,
PO

processor,

4-2

status word

4-1

Program counter
Q22-Bus, 3-5,
cycle, 4-23
initialize,
map, 4-23

(PC),

4-21,
3-11

(PSW},
4-1

4-23

watch chip,
Restart, 3-8

4-34,

(SID),

4-35

4-34

Restart parameter

block

ROM address space,
ROM memory, 4-32
Run mode, 4-33

4-32

3-8, 3-20
format, 3-9

(RPB),

Secondary bootstrap, 3-20
Serial line unit (SLU), 4-40
Set command, 3-36
Specifications
KA630-AA, 1-8
Stack pointer, 4-1

System base register
4-17

System control

block

(SBR),
(SCB),

4-10

. System

identification

System page table (SPT),
System space address
translation, 4-17

4-17

Index-3

Index

Test

battery backup unit

(BBU),

3-5

interprocessor communication
register (IPCR), 3-5
Q22-Bus, 3-5
VCBOl/VCB02, 3-5

Time-of-year (TOY)
BBU, 2-9, 4-34

clock, 3-5, 4-34
registers, 4-35
Timeouts, 4-13
Translation buffer

invalidate

all (TBIA), 4-16
Translation buffer invalidate
single (TBIS), 4-1%6

VCBO1/VCB(O2 console
hardware, 3-5
Virtual address space,

4-16
Virtual memory bootstrap (VME),
3-12
registers, 3-12

Index~4